diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 93ddb55..ca9cd7c 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -7,6 +7,7 @@ on: - 'pab-[0-9]*' - 'jaj-[0-9]*' - 'pab-v3-[0-9]*' + - 'pab-can-[0-9]*' pull_request: concurrency: @@ -42,8 +43,9 @@ jobs: run: | TAG="${GITHUB_REF_NAME}" case "$TAG" in - pab-v3-*) PRODUCT="pab-v3"; VERSION="${TAG#pab-v3-}"; TARGET="PAB_V3" ;; - pab-*) PRODUCT="pab"; VERSION="${TAG#pab-}"; TARGET="PAB" ;; + pab-v3-*) PRODUCT="pab-v3"; VERSION="${TAG#pab-v3-}"; TARGET="PAB_V3" ;; + pab-can-*) PRODUCT="pab-can"; VERSION="${TAG#pab-can-}"; TARGET="PAB_CAN" ;; + pab-*) PRODUCT="pab"; VERSION="${TAG#pab-}"; TARGET="PAB" ;; jaj-*) PRODUCT="jaj"; VERSION="${TAG#jaj-}"; TARGET="JAJ" ;; *) echo "::error::Unrecognized tag format: $TAG"; exit 1 ;; esac diff --git a/README.md b/README.md index 243ad35..032dbd8 100644 --- a/README.md +++ b/README.md @@ -18,6 +18,7 @@ Scripts for building and flashing a Jetson **Orin Nano** or **Orin NX** on an AR | `PAB` | ARK Jetson PAB Carrier | | `JAJ` | ARK Just a Jetson Carrier | | `PAB_V3` | ARK Jetson PAB V3 Carrier | +| `PAB_CAN` | ARK PAB CAN Jetson Carrier | ## Build & Flash @@ -31,7 +32,7 @@ Download the BSP, root filesystem, and kernel source tarballs (one time): ``` ./build.sh PAB --clean --provision ``` -- Targets are `PAB`, `JAJ`, `PAB_V3`, or `all`. +- Targets are `PAB`, `JAJ`, `PAB_V3`, `PAB_CAN`, or `all`. - `--clean` wipes `staging/{TARGET}/` and re-stages from scratch. - `--provision` preinstalls [ARK-OS](https://github.com/ARK-Electronics/ARK-OS) and tooling into the image. Omit it for a bare image. To bake in your own packages, edit [`provision.sh`](provision.sh). @@ -68,7 +69,7 @@ ssh jetson@jetson.local ## Cameras -Every carrier ships with an IMX219 overlay already selected, so cameras work out of the box: the quad overlay on **PAB**, the dual overlay on **JAJ** and **PAB_V3**. To use a different camera, select an overlay with NVIDIA's `jetson-io` tool. List what's available: +Every carrier ships with an IMX219 overlay already selected, so cameras work out of the box: the quad overlay on **PAB**, the dual overlay on **JAJ**, **PAB_V3**, and **PAB_CAN**. To use a different camera, select an overlay with NVIDIA's `jetson-io` tool. List what's available: ``` sudo /opt/nvidia/jetson-io/config-by-hardware.py -l ``` diff --git a/build.sh b/build.sh index 48e0eb0..7e44125 100755 --- a/build.sh +++ b/build.sh @@ -1,6 +1,6 @@ #!/bin/bash -# Usage: ./build.sh [--clean] [--provision] +# Usage: ./build.sh [--clean] [--provision] # --clean wipe staging/{TARGET}/ and re-stage from downloads before building # --provision install ARK-OS into the rootfs (staging only: first build or --clean) # @@ -21,13 +21,13 @@ TARGET="" for arg in "$@"; do case "$arg" in - PAB|JAJ|PAB_V3) TARGET="$arg" ;; + PAB|JAJ|PAB_V3|PAB_CAN) TARGET="$arg" ;; all) TARGET="all" ;; --clean) CLEAN=1 ;; --provision) PROVISION=1 ;; *) echo "Invalid argument: $arg" >&2 - echo "Usage: $0 [--clean] [--provision]" >&2 + echo "Usage: $0 [--clean] [--provision]" >&2 exit 1 ;; esac @@ -40,18 +40,20 @@ if [ -z "$TARGET" ]; then echo "1) PAB" echo "2) JAJ" echo "3) PAB_V3" - echo "4) all" - read -p "Enter your choice (1-4): " choice + echo "4) PAB_CAN" + echo "5) all" + read -p "Enter your choice (1-5): " choice case $choice in - 1|PAB) TARGET="PAB" ;; - 2|JAJ) TARGET="JAJ" ;; - 3|PAB_V3) TARGET="PAB_V3" ;; - 4|all) TARGET="all" ;; + 1|PAB) TARGET="PAB" ;; + 2|JAJ) TARGET="JAJ" ;; + 3|PAB_V3) TARGET="PAB_V3" ;; + 4|PAB_CAN) TARGET="PAB_CAN" ;; + 5|all) TARGET="all" ;; *) echo "Invalid choice. Exiting."; exit 1 ;; esac else - echo "ERROR: target required (PAB | JAJ | PAB_V3 | all) when running non-interactively." >&2 - echo "Usage: $0 [--clean] [--provision]" >&2 + echo "ERROR: target required (PAB | JAJ | PAB_V3 | PAB_CAN | all) when running non-interactively." >&2 + echo "Usage: $0 [--clean] [--provision]" >&2 exit 1 fi fi @@ -96,7 +98,7 @@ sudo -v if [ "$TARGET" = "all" ]; then trap 'echo ""; echo "Aborted."; exit 130' INT - for t in PAB JAJ PAB_V3; do + for t in PAB JAJ PAB_V3 PAB_CAN; do echo "" echo "=========================================" echo " Building $t" diff --git a/docs/cameras.md b/docs/cameras.md index d715626..1ddd6ce 100644 --- a/docs/cameras.md +++ b/docs/cameras.md @@ -6,11 +6,11 @@ This document covers tested camera sensors, available device tree overlays, and | Sensor | Lanes | Resolution | Overlays | Status | |--------|-------|------------|----------|--------| -| IMX219 | 2 | 3280x2464 | dual (JAJ/PAB_V3), quad (PAB) | Working | -| IMX477 | 2 | 4056x3040 | dual (JAJ/PAB_V3), quad (PAB) | Working | -| IMX708 | 2 | 4608x2592 | dual (JAJ/PAB_V3), quad (PAB) | Working | +| IMX219 | 2 | 3280x2464 | dual (JAJ/PAB_V3/PAB_CAN), quad (PAB) | Working | +| IMX477 | 2 | 4056x3040 | dual (JAJ/PAB_V3/PAB_CAN), quad (PAB) | Working | +| IMX708 | 2 | 4608x2592 | dual (JAJ/PAB_V3/PAB_CAN), quad (PAB) | Working | -Each carrier ships exactly one overlay per sensor: dual on JAJ / PAB_V3 (two CSI ports), quad on PAB (four CSI ports). +Each carrier ships exactly one overlay per sensor: dual on JAJ / PAB_V3 / PAB_CAN (two CSI ports), quad on PAB (four CSI ports). ## IMX219 (Sony, 8MP) @@ -18,12 +18,13 @@ Tested and working in 2-lane mode. - **PAB**: Tested on all 4 CSI ports (quad overlay) - **JAJ / PAB_V3**: Tested on both CSI ports (dual overlay) +- **PAB_CAN**: same dev-kit CSI wiring as PAB_V3 (dual overlay) ### Overlays | Overlay | Filename | Ports | |---------|----------|-------| -| Dual | `tegra234-p3767-camera-p3768-imx219-dual.dtbo` | CAM0 + CAM1 (JAJ/PAB_V3 default) | +| Dual | `tegra234-p3767-camera-p3768-imx219-dual.dtbo` | CAM0 + CAM1 (JAJ/PAB_V3/PAB_CAN default) | | Quad | `tegra234-p3767-camera-p3768-imx219-quad.dtbo` | All 4 ports (PAB default) | ## IMX477 (Sony Starvis, 12.3MP) @@ -34,7 +35,7 @@ Tested and working in 2-lane mode on all carrier boards. | Overlay | Filename | Ports | |---------|----------|-------| -| Dual | `tegra234-p3767-camera-p3768-imx477-dual.dtbo` | CAM0 + CAM1 (JAJ/PAB_V3) | +| Dual | `tegra234-p3767-camera-p3768-imx477-dual.dtbo` | CAM0 + CAM1 (JAJ/PAB_V3/PAB_CAN) | | Quad | `tegra234-p3767-camera-p3768-imx477-quad.dtbo` | All 4 ports (PAB) | The quad overlay is new and not yet hardware-validated: it pairs the port wiring of the IMX219 quad (the PAB default) with the sensor modes of the retired single overlay. @@ -53,7 +54,7 @@ Driver is RidgeRun's `nv_imx708`, vendored under `kernel_overlay/`. One 10-bit m | Overlay | Filename | Ports | |---------|----------|-------| -| Dual | `tegra234-p3767-camera-p3768-imx708-dual.dtbo` | CAM0 + CAM1 (JAJ/PAB_V3) | +| Dual | `tegra234-p3767-camera-p3768-imx708-dual.dtbo` | CAM0 + CAM1 (JAJ/PAB_V3/PAB_CAN) | | Quad | `tegra234-p3767-camera-p3768-imx708-quad.dtbo` | All 4 ports (PAB) | ## Installing a Camera Overlay @@ -66,7 +67,7 @@ The overlays ARK ships live under `products//overlay/` (the `.dts`/`.dts Build the overlay DTBs (from host): ``` -./build.sh PAB # or JAJ, PAB_V3 +./build.sh PAB # or JAJ, PAB_V3, PAB_CAN ``` Copy the overlay to the Jetson: diff --git a/docs/device-tree.md b/docs/device-tree.md index 47dc03b..77ff757 100644 --- a/docs/device-tree.md +++ b/docs/device-tree.md @@ -28,7 +28,7 @@ Each product carries only the files it actually changes: - `bootloader/.../tegra234-mb*-bct-*-p3767-*.{dtsi,dts}` — the MB1/MB2 BCT pinmux, GPIO, pad-voltage and misc config for the carrier (ARK's Pinmux spreadsheet output). These are bootloader inputs, compiled separately from the kernel DTBs, so they stay as full files. - `source/hardware/nvidia/t23x/nv-public/nv-platform/ark--overrides.dtsi` — the **one fragment** holding every kernel-DTB change for the carrier (UARTB, USB topology, HDA, display, etc.), expressed as overrides (`&{/path} { ... }`) over the stock tree. -- `source/.../nv-platform/tegra234-dcb-p3737-0000-p3701-0000-hdmi.dtsi` (JAJ, PAB_V3 only) — the HDMI display-control block the fragment `#include`s. +- `source/.../nv-platform/tegra234-dcb-p3737-0000-p3701-0000-hdmi.dtsi` (JAJ, PAB_V3, PAB_CAN only) — the HDMI display-control block the fragment `#include`s. Model strings are **not** files — they live in `products//dtb_models.env`. diff --git a/docs/gpio.md b/docs/gpio.md index 67588e8..8083b18 100644 --- a/docs/gpio.md +++ b/docs/gpio.md @@ -1,6 +1,6 @@ # GPIO on ARK Jetson Carriers -Using GPIO pins on ARK JAJ / PAB / PAB_V3 carriers running JetPack 6 (L4T r36.x). +Using GPIO pins on ARK JAJ / PAB / PAB_V3 / PAB_CAN carriers running JetPack 6 (L4T r36.x). ## TL;DR @@ -25,7 +25,7 @@ I2S0 connector pins on **PAB** and **JAJ**, exposed as GPIO by default (configur `PAC.06` is on the AON GPIO controller, which retains state through SC7 suspend; main GPIO does not. -On **PAB_V3**, `PAC.06` is reserved for the KSZ8795 ethernet switch reset and is driven HIGH by BCT — do not use as general GPIO. +On **PAB_V3**, `PAC.06` is reserved for the KSZ8795 ethernet switch reset and is driven HIGH by BCT — do not use as general GPIO. On **PAB_CAN**, `PAC.06` is LAN96455S SWITCH_RSTn (module pin 211 / GPIO09): active-low (low = reset, high = run). MB1 holds it **LOW** through early boot; a kernel gpio-hog then drives **HIGH** so the rising edge starts unmanaged ROM boot — do not use as general GPIO. ## Verify the lines @@ -37,7 +37,7 @@ sudo gpioinfo | grep -E '"P(H\.07|I\.0[0-2]|AC\.06)"' All five show as `unused` **inputs** at idle — the four outputs held high by their pull-ups, DIN floating. Your app claims a line and sets its direction when it needs to drive or read. -> **PAB** and **JAJ** wire this connector and ship it GPIO-by-default. **PAB_V3** does not route the I2S0 signals to a connector, so it has no connector GPIO here (and `PAC.06`/MCLK is its KSZ8795 ethernet reset — see above). The `ark_i2s_gpio` jetson-io overlay has been removed from all three. +> **PAB** and **JAJ** wire this connector and ship it GPIO-by-default. **PAB_V3** and **PAB_CAN** do not route the I2S0 signals to a connector, so they have no connector GPIO here (and `PAC.06`/MCLK is their ethernet switch reset — see above). The `ark_i2s_gpio` jetson-io overlay has been removed from all carriers. ## Drive and read diff --git a/docs/i2c.md b/docs/i2c.md index 0f69cf5..46c7ef0 100644 --- a/docs/i2c.md +++ b/docs/i2c.md @@ -1,6 +1,6 @@ # I2C on ARK Jetson Carriers -Orin Nano / NX, all ARK carriers (JAJ / PAB / PAB_V3). +Orin Nano / NX, all ARK carriers (JAJ / PAB / PAB_V3 / PAB_CAN). ## Scan a bus diff --git a/flash.sh b/flash.sh index 07eb536..c49189a 100755 --- a/flash.sh +++ b/flash.sh @@ -2,7 +2,7 @@ # Usage: ./flash.sh [--sdcard] [--usb] # -# TARGET: PAB | JAJ | PAB_V3 +# TARGET: PAB | JAJ | PAB_V3 | PAB_CAN # # Flashes a previously-built target directly from its staging directory. # The device must be in USB recovery mode before running this script. @@ -16,7 +16,7 @@ TARGET="" while [[ $# -gt 0 ]]; do case $1 in - PAB|JAJ|PAB_V3) + PAB|JAJ|PAB_V3|PAB_CAN) TARGET="$1" shift ;; --sdcard) @@ -28,7 +28,7 @@ while [[ $# -gt 0 ]]; do shift ;; *) echo "Unknown option: $1" >&2 - echo "Usage: ./flash.sh [--sdcard] [--usb]" >&2 + echo "Usage: ./flash.sh [--sdcard] [--usb]" >&2 exit 1 ;; esac done @@ -39,16 +39,18 @@ if [ -z "$TARGET" ]; then echo "1) PAB" echo "2) JAJ" echo "3) PAB_V3" - read -p "Enter your choice (1-3): " choice + echo "4) PAB_CAN" + read -p "Enter your choice (1-4): " choice case $choice in 1) TARGET="PAB" ;; 2) TARGET="JAJ" ;; 3) TARGET="PAB_V3" ;; + 4) TARGET="PAB_CAN" ;; *) echo "Invalid choice. Exiting."; exit 1 ;; esac else - echo "ERROR: target required (PAB | JAJ | PAB_V3) when running non-interactively." >&2 - echo "Usage: ./flash.sh [--sdcard] [--usb]" >&2 + echo "ERROR: target required (PAB | JAJ | PAB_V3 | PAB_CAN) when running non-interactively." >&2 + echo "Usage: ./flash.sh [--sdcard] [--usb]" >&2 exit 1 fi fi diff --git a/packaging/README.md b/packaging/README.md index 2b3bc89..a6f2b0f 100644 --- a/packaging/README.md +++ b/packaging/README.md @@ -9,6 +9,7 @@ This document covers how flash packages are generated, released, and consumed. E | PAB | ARK Jetson PAB Carrier | `pab-` | | JAJ | ARK Just a Jetson Carrier | `jaj-` | | PAB_V3 | ARK Jetson PAB V3 Carrier | `pab-v3-` | +| PAB_CAN | ARK PAB CAN Jetson Carrier | `pab-can-` | Each carrier has its own device tree. A flash package built for one carrier will not work on another. diff --git a/packaging/flash_from_package.sh b/packaging/flash_from_package.sh index 982ad73..ef95e03 100755 --- a/packaging/flash_from_package.sh +++ b/packaging/flash_from_package.sh @@ -18,7 +18,7 @@ # # Usage: # ./flash_from_package.sh # specific release (e.g. pab-6.2.1.1); auto-detects a draft of that tag -# ./flash_from_package.sh # latest published release for a product (pab, jaj, pab-v3) +# ./flash_from_package.sh # latest published release for a product (pab, jaj, pab-v3, pab-can) # ./flash_from_package.sh --draft # latest DRAFT release for a product (needs gh read access) # ./flash_from_package.sh --full # regenerate images even if cached ones match # ./flash_from_package.sh --clean # remove all cached data @@ -36,6 +36,7 @@ usage() { echo " $(basename "$0") pab Flash the latest PAB release" echo " $(basename "$0") jaj Flash the latest JAJ release" echo " $(basename "$0") pab-v3 Flash the latest PAB_V3 release" + echo " $(basename "$0") pab-can Flash the latest PAB_CAN release" echo " $(basename "$0") pab-v3 --draft Flash the latest PAB_V3 DRAFT (needs gh read access)" echo " $(basename "$0") pab --full Regenerate flash images even if cached ones match" echo " $(basename "$0") --clean Remove all cached data" @@ -46,7 +47,7 @@ usage() { is_product_name() { case "$1" in - pab|jaj|pab-v3) return 0 ;; + pab|jaj|pab-v3|pab-can) return 0 ;; *) return 1 ;; esac } diff --git a/packaging/generate_flash_package.sh b/packaging/generate_flash_package.sh index 1a8c3c5..8b1bfcf 100755 --- a/packaging/generate_flash_package.sh +++ b/packaging/generate_flash_package.sh @@ -23,17 +23,17 @@ TARGET="" while [[ $# -gt 0 ]]; do case $1 in - PAB|JAJ|PAB_V3) TARGET="$1"; shift ;; + PAB|JAJ|PAB_V3|PAB_CAN) TARGET="$1"; shift ;; *) echo "Unknown option: $1" >&2 - echo "Usage: ./generate_flash_package.sh " >&2 + echo "Usage: ./generate_flash_package.sh " >&2 exit 1 ;; esac done if [ -z "$TARGET" ]; then - echo "ERROR: target required (PAB | JAJ | PAB_V3)." >&2 - echo "Usage: ./generate_flash_package.sh " >&2 + echo "ERROR: target required (PAB | JAJ | PAB_V3 | PAB_CAN)." >&2 + echo "Usage: ./generate_flash_package.sh " >&2 exit 1 fi diff --git a/packaging/publish_release.sh b/packaging/publish_release.sh index 3c3a1d3..c3a686f 100755 --- a/packaging/publish_release.sh +++ b/packaging/publish_release.sh @@ -11,7 +11,7 @@ set -e if [ $# -lt 2 ]; then - echo "Usage: ./publish_release.sh " + echo "Usage: ./publish_release.sh " echo " e.g. ./publish_release.sh PAB 6.2.1.1" echo "" echo "Creates and pushes a tag — CI handles the rest." @@ -24,9 +24,9 @@ SCRIPT_DIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)" ROOT_DIR="$(cd "$SCRIPT_DIR/.." && pwd)" case "$TARGET" in - PAB|JAJ|PAB_V3) ;; + PAB|JAJ|PAB_V3|PAB_CAN) ;; *) - echo "ERROR: Invalid target '$TARGET'. Must be PAB, JAJ, or PAB_V3." + echo "ERROR: Invalid target '$TARGET'. Must be PAB, JAJ, PAB_V3, or PAB_CAN." exit 1 ;; esac diff --git a/products/PAB_CAN/Jetson_Orin_NX_and_Orin_Nano_series_Pinmux_Config_Jetpack_6.xlsm b/products/PAB_CAN/Jetson_Orin_NX_and_Orin_Nano_series_Pinmux_Config_Jetpack_6.xlsm new file mode 100644 index 0000000..9328a6d Binary files /dev/null and b/products/PAB_CAN/Jetson_Orin_NX_and_Orin_Nano_series_Pinmux_Config_Jetpack_6.xlsm differ diff --git a/products/PAB_CAN/default_overlays b/products/PAB_CAN/default_overlays new file mode 100644 index 0000000..c973d46 --- /dev/null +++ b/products/PAB_CAN/default_overlays @@ -0,0 +1,11 @@ +# Device-tree overlay(s) baked into this product's image at flash time, so they are +# active on the first boot with no jetson-io step. flash.sh hands each dtbo to +# tegraflash as ADDITIONAL_DTB_OVERLAY, which merges it into the base DTB on top of +# whichever Orin Nano/NX SKU the flasher detects — so one image still covers every +# SKU. One dtbo basename per line ('#' comments allowed); each must be built into +# kernel/dtb/ via overlay/dtbo.list. A user can still switch cameras with jetson-io: +# it boots its own FDT'd entry off the clean /boot/dtb kernel DTB, superseding this +# without a duplicate-node collision. + +# PAB_CAN ships with the dual IMX219 camera enabled by default. +tegra234-p3767-camera-p3768-imx219-dual.dtbo diff --git a/products/PAB_CAN/device_tree/bootloader/generic/BCT/tegra234-mb1-bct-padvoltage-p3767-dp-a03.dtsi b/products/PAB_CAN/device_tree/bootloader/generic/BCT/tegra234-mb1-bct-padvoltage-p3767-dp-a03.dtsi new file mode 100644 index 0000000..ffdd0f1 --- /dev/null +++ b/products/PAB_CAN/device_tree/bootloader/generic/BCT/tegra234-mb1-bct-padvoltage-p3767-dp-a03.dtsi @@ -0,0 +1,69 @@ +/*This dtsi file was generated by jetson orin nano&nx pinmux hdmi.xlsm Revision: 1.04 */ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 'AS IS' + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#define IO_PAD_VOLTAGE_1_2V 1200000 +#define IO_PAD_VOLTAGE_1_8V 1800000 +#define IO_PAD_VOLTAGE_3_3V 3300000 +/dts-v1/; +/ { + pmc@c360000 { + io-pad-defaults { + sdmmc1_hv { + nvidia,io-pad-init-voltage = ; + }; + + eqos { + nvidia,io-pad-init-voltage = ; + }; + + qspi { + nvidia,io-pad-init-voltage = ; + }; + + g2 { + nvidia,io-pad-init-voltage = ; + }; + + ao_hv { + nvidia,io-pad-init-voltage = ; + }; + + g9 { + nvidia,io-pad-init-voltage = ; + }; + + ufs { + nvidia,io-pad-init-voltage = ; + }; + + }; + }; +}; diff --git a/products/PAB_CAN/device_tree/bootloader/generic/BCT/tegra234-mb1-bct-pinmux-p3767-dp-a03.dtsi b/products/PAB_CAN/device_tree/bootloader/generic/BCT/tegra234-mb1-bct-pinmux-p3767-dp-a03.dtsi new file mode 100644 index 0000000..5adbc03 --- /dev/null +++ b/products/PAB_CAN/device_tree/bootloader/generic/BCT/tegra234-mb1-bct-pinmux-p3767-dp-a03.dtsi @@ -0,0 +1,2161 @@ +/*This dtsi file was generated by jetson orin nano&nx pinmux hdmi.xlsm Revision: 1.04 */ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 'AS IS' + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; +#include "pinctrl-tegra.h" + +#include "./tegra234-mb1-bct-gpio-p3767-dp-a03.dtsi" +/ { + pinmux@2430000 { + pinctrl-names = "default", "drive", "unused"; + pinctrl-0 = <&pinmux_default>; + pinctrl-1 = <&drive_default>; + pinctrl-2 = <&pinmux_unused_lowpower>; + + pinmux_default: common { + /* SFIO Pin Configuration */ + shutdown_n { + nvidia,pins = "shutdown_n"; + nvidia,function = "shutdown"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + vcomp_alert_pee1 { + nvidia,pins = "vcomp_alert_pee1"; + nvidia,function = "soc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + batt_oc_pee3 { + nvidia,pins = "batt_oc_pee3"; + nvidia,function = "soc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + hdmi_cec_pgg0 { + nvidia,pins = "hdmi_cec_pgg0"; + nvidia,function = "hdmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + touch_clk_pcc4 { + nvidia,pins = "touch_clk_pcc4"; + nvidia,function = "gp"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + uart3_tx_pcc5 { + nvidia,pins = "uart3_tx_pcc5"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + uart3_rx_pcc6 { + nvidia,pins = "uart3_rx_pcc6"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + gen2_i2c_scl_pcc7 { + nvidia,pins = "gen2_i2c_scl_pcc7"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + gen2_i2c_sda_pdd0 { + nvidia,pins = "gen2_i2c_sda_pdd0"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + gen8_i2c_scl_pdd1 { + nvidia,pins = "gen8_i2c_scl_pdd1"; + nvidia,function = "i2c8"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + gen8_i2c_sda_pdd2 { + nvidia,pins = "gen8_i2c_sda_pdd2"; + nvidia,function = "i2c8"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + can0_dout_paa0 { + nvidia,pins = "can0_dout_paa0"; + nvidia,function = "can0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + can0_din_paa1 { + nvidia,pins = "can0_din_paa1"; + nvidia,function = "can0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gp_pwm3_px3 { + nvidia,pins = "gp_pwm3_px3"; + nvidia,function = "gp"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + uart2_tx_px4 { + nvidia,pins = "uart2_tx_px4"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + uart2_rx_px5 { + nvidia,pins = "uart2_rx_px5"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + uart2_rts_px6 { + nvidia,pins = "uart2_rts_px6"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + uart2_cts_px7 { + nvidia,pins = "uart2_cts_px7"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + extperiph1_clk_pp0 { + nvidia,pins = "extperiph1_clk_pp0"; + nvidia,function = "extperiph1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + extperiph2_clk_pp1 { + nvidia,pins = "extperiph2_clk_pp1"; + nvidia,function = "extperiph2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + cam_i2c_scl_pp2 { + nvidia,pins = "cam_i2c_scl_pp2"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + cam_i2c_sda_pp3 { + nvidia,pins = "cam_i2c_sda_pp3"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + soc_gpio24_pp5 { + nvidia,pins = "soc_gpio24_pp5"; + nvidia,function = "soc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + pwr_i2c_scl_pp7 { + nvidia,pins = "pwr_i2c_scl_pp7"; + nvidia,function = "i2c5"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + pwr_i2c_sda_pq0 { + nvidia,pins = "pwr_i2c_sda_pq0"; + nvidia,function = "i2c5"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + soc_gpio29_pq2 { + nvidia,pins = "soc_gpio29_pq2"; + nvidia,function = "nv"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + uart1_tx_pr2 { + nvidia,pins = "uart1_tx_pr2"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + uart1_rx_pr3 { + nvidia,pins = "uart1_rx_pr3"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + gen1_i2c_scl_pi3 { + nvidia,pins = "gen1_i2c_scl_pi3"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + gen1_i2c_sda_pi4 { + nvidia,pins = "gen1_i2c_sda_pi4"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + soc_gpio07_pi6 { + nvidia,pins = "soc_gpio07_pi6"; + nvidia,function = "gp"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + sdmmc1_clk_pj0 { + nvidia,pins = "sdmmc1_clk_pj0"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,loopback = ; + }; + + sdmmc1_cmd_pj1 { + nvidia,pins = "sdmmc1_cmd_pj1"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc1_dat0_pj2 { + nvidia,pins = "sdmmc1_dat0_pj2"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc1_dat1_pj3 { + nvidia,pins = "sdmmc1_dat1_pj3"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc1_dat2_pj4 { + nvidia,pins = "sdmmc1_dat2_pj4"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc1_dat3_pj5 { + nvidia,pins = "sdmmc1_dat3_pj5"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + qspi0_sck_pc0 { + nvidia,pins = "qspi0_sck_pc0"; + nvidia,function = "qspi0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,loopback = ; + }; + + qspi0_cs_n_pc1 { + nvidia,pins = "qspi0_cs_n_pc1"; + nvidia,function = "qspi0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + qspi0_io0_pc2 { + nvidia,pins = "qspi0_io0_pc2"; + nvidia,function = "qspi0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + qspi0_io1_pc3 { + nvidia,pins = "qspi0_io1_pc3"; + nvidia,function = "qspi0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + qspi0_io2_pc4 { + nvidia,pins = "qspi0_io2_pc4"; + nvidia,function = "qspi0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + qspi0_io3_pc5 { + nvidia,pins = "qspi0_io3_pc5"; + nvidia,function = "qspi0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l1_clkreq_n_pk2 { + nvidia,pins = "pex_l1_clkreq_n_pk2"; + nvidia,function = "pe1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + pex_l1_rst_n_pk3 { + nvidia,pins = "pex_l1_rst_n_pk3"; + nvidia,function = "pe1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + pex_l4_clkreq_n_pl0 { + nvidia,pins = "pex_l4_clkreq_n_pl0"; + nvidia,function = "pe4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + pex_l4_rst_n_pl1 { + nvidia,pins = "pex_l4_rst_n_pl1"; + nvidia,function = "pe4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + pex_l7_clkreq_n_pag0 { + nvidia,pins = "pex_l7_clkreq_n_pag0"; + nvidia,function = "pe7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + pex_l7_rst_n_pag1 { + nvidia,pins = "pex_l7_rst_n_pag1"; + nvidia,function = "pe7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + pex_l8_clkreq_n_pag2 { + nvidia,pins = "pex_l8_clkreq_n_pag2"; + nvidia,function = "pe8"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + pex_l8_rst_n_pag3 { + nvidia,pins = "pex_l8_rst_n_pag3"; + nvidia,function = "pe8"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + pex_l9_clkreq_n_pag4 { + nvidia,pins = "pex_l9_clkreq_n_pag4"; + nvidia,function = "pe9"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + pex_l9_rst_n_pag5 { + nvidia,pins = "pex_l9_rst_n_pag5"; + nvidia,function = "pe9"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + dap4_sclk_pa4 { + nvidia,pins = "dap4_sclk_pa4"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + dap4_dout_pa5 { + nvidia,pins = "dap4_dout_pa5"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + dap4_din_pa6 { + nvidia,pins = "dap4_din_pa6"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + dap4_fs_pa7 { + nvidia,pins = "dap4_fs_pa7"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + /* GPIO Pin Configuration */ + ao_retention_n_pee2 { + nvidia,pins = "ao_retention_n_pee2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + power_on_pee4 { + nvidia,pins = "power_on_pee4"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + spi2_sck_pcc0 { + nvidia,pins = "spi2_sck_pcc0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + spi2_miso_pcc1 { + nvidia,pins = "spi2_miso_pcc1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + spi2_mosi_pcc2 { + nvidia,pins = "spi2_mosi_pcc2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + spi2_cs0_pcc3 { + nvidia,pins = "spi2_cs0_pcc3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + can0_stb_paa4 { + nvidia,pins = "can0_stb_paa4"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + can0_en_paa5 { + nvidia,pins = "can0_en_paa5"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + can1_err_pbb3 { + nvidia,pins = "can1_err_pbb3"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + soc_gpio08_pb0 { + nvidia,pins = "soc_gpio08_pb0"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + spi3_sck_py0 { + nvidia,pins = "spi3_sck_py0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + spi3_miso_py1 { + nvidia,pins = "spi3_miso_py1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + spi3_mosi_py2 { + nvidia,pins = "spi3_mosi_py2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + spi3_cs0_py3 { + nvidia,pins = "spi3_cs0_py3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + spi3_cs1_py4 { + nvidia,pins = "spi3_cs1_py4"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + usb_vbus_en0_pz1 { + nvidia,pins = "usb_vbus_en0_pz1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + spi1_sck_pz3 { + nvidia,pins = "spi1_sck_pz3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + spi1_miso_pz4 { + nvidia,pins = "spi1_miso_pz4"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + spi1_mosi_pz5 { + nvidia,pins = "spi1_mosi_pz5"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + spi1_cs0_pz6 { + nvidia,pins = "spi1_cs0_pz6"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + spi1_cs1_pz7 { + nvidia,pins = "spi1_cs1_pz7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + soc_gpio25_pp6 { + nvidia,pins = "soc_gpio25_pp6"; + nvidia,function = "vi0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + soc_gpio30_pq3 { + nvidia,pins = "soc_gpio30_pq3"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + soc_gpio32_pq5 { + nvidia,pins = "soc_gpio32_pq5"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + soc_gpio33_pq6 { + nvidia,pins = "soc_gpio33_pq6"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + uart1_rts_pr4 { + nvidia,pins = "uart1_rts_pr4"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + uart1_cts_pr5 { + nvidia,pins = "uart1_cts_pr5"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + dp_aux_ch0_hpd_pm0 { + nvidia,pins = "dp_aux_ch0_hpd_pm0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + soc_gpio39_pn1 { + nvidia,pins = "soc_gpio39_pn1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + soc_gpio13_pg0 { + nvidia,pins = "soc_gpio13_pg0"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + soc_gpio19_pg6 { + nvidia,pins = "soc_gpio19_pg6"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + soc_gpio20_pg7 { + nvidia,pins = "soc_gpio20_pg7"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + soc_gpio21_ph0 { + nvidia,pins = "soc_gpio21_ph0"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + uart4_cts_ph6 { + nvidia,pins = "uart4_cts_ph6"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + soc_gpio41_ph7 { + nvidia,pins = "soc_gpio41_ph7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + soc_gpio42_pi0 { + nvidia,pins = "soc_gpio42_pi0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + soc_gpio43_pi1 { + nvidia,pins = "soc_gpio43_pi1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + soc_gpio44_pi2 { + nvidia,pins = "soc_gpio44_pi2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + cpu_pwr_req_pi5 { + nvidia,pins = "cpu_pwr_req_pi5"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + spi5_sck_pac0 { + nvidia,pins = "spi5_sck_pac0"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + /* SWITCH_RSTn (GPIO09): driven output. MB1 GPIO BCT holds it low + * (reset); the kernel gpio-hog then drives it high (run). */ + soc_gpio59_pac6 { + nvidia,pins = "soc_gpio59_pac6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + pex_l2_clkreq_n_pk4 { + nvidia,pins = "pex_l2_clkreq_n_pk4"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + pex_l2_rst_n_pk5 { + nvidia,pins = "pex_l2_rst_n_pk5"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + pex_wake_n_pl2 { + nvidia,pins = "pex_wake_n_pl2"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + dap6_sclk_pa0 { + nvidia,pins = "dap6_sclk_pa0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + }; + + pinmux_unused_lowpower: unused_lowpower { + sce_error_pee0 { + nvidia,pins = "sce_error_pee0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + soc_gpio26_pee5 { + nvidia,pins = "soc_gpio26_pee5"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + soc_gpio27_pee6 { + nvidia,pins = "soc_gpio27_pee6"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + bootv_ctl_n_pee7 { + nvidia,pins = "bootv_ctl_n_pee7"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + can1_dout_paa2 { + nvidia,pins = "can1_dout_paa2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + can1_din_paa3 { + nvidia,pins = "can1_din_paa3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + soc_gpio49_paa6 { + nvidia,pins = "soc_gpio49_paa6"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + can0_err_paa7 { + nvidia,pins = "can0_err_paa7"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + can1_stb_pbb0 { + nvidia,pins = "can1_stb_pbb0"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + can1_en_pbb1 { + nvidia,pins = "can1_en_pbb1"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + soc_gpio50_pbb2 { + nvidia,pins = "soc_gpio50_pbb2"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gpu_pwr_req_px0 { + nvidia,pins = "gpu_pwr_req_px0"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + cv_pwr_req_px1 { + nvidia,pins = "cv_pwr_req_px1"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + gp_pwm2_px2 { + nvidia,pins = "gp_pwm2_px2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + uart5_tx_py5 { + nvidia,pins = "uart5_tx_py5"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + uart5_rx_py6 { + nvidia,pins = "uart5_rx_py6"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + uart5_rts_py7 { + nvidia,pins = "uart5_rts_py7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + uart5_cts_pz0 { + nvidia,pins = "uart5_cts_pz0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + usb_vbus_en1_pz2 { + nvidia,pins = "usb_vbus_en1_pz2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + soc_gpio23_pp4 { + nvidia,pins = "soc_gpio23_pp4"; + nvidia,function = "vi0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + soc_gpio28_pq1 { + nvidia,pins = "soc_gpio28_pq1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + soc_gpio31_pq4 { + nvidia,pins = "soc_gpio31_pq4"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + soc_gpio35_pq7 { + nvidia,pins = "soc_gpio35_pq7"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + soc_gpio37_pr0 { + nvidia,pins = "soc_gpio37_pr0"; + nvidia,function = "gp"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + soc_gpio56_pr1 { + nvidia,pins = "soc_gpio56_pr1"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + dp_aux_ch1_p_pn3 { + nvidia,pins = "dp_aux_ch1_p_pn3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + dp_aux_ch1_n_pn4 { + nvidia,pins = "dp_aux_ch1_n_pn4"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + dp_aux_ch1_hpd_pm1 { + nvidia,pins = "dp_aux_ch1_hpd_pm1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + dp_aux_ch2_p_pn5 { + nvidia,pins = "dp_aux_ch2_p_pn5"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + dp_aux_ch2_n_pn6 { + nvidia,pins = "dp_aux_ch2_n_pn6"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + dp_aux_ch2_hpd_pm2 { + nvidia,pins = "dp_aux_ch2_hpd_pm2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + dp_aux_ch3_p_pn7 { + nvidia,pins = "dp_aux_ch3_p_pn7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + dp_aux_ch3_n_pn0 { + nvidia,pins = "dp_aux_ch3_n_pn0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + dp_aux_ch3_hpd_pm3 { + nvidia,pins = "dp_aux_ch3_hpd_pm3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + soc_gpio55_pm4 { + nvidia,pins = "soc_gpio55_pm4"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + soc_gpio36_pm5 { + nvidia,pins = "soc_gpio36_pm5"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + soc_gpio53_pm6 { + nvidia,pins = "soc_gpio53_pm6"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + soc_gpio38_pm7 { + nvidia,pins = "soc_gpio38_pm7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + soc_gpio40_pn2 { + nvidia,pins = "soc_gpio40_pn2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + soc_gpio14_pg1 { + nvidia,pins = "soc_gpio14_pg1"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + soc_gpio15_pg2 { + nvidia,pins = "soc_gpio15_pg2"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + soc_gpio16_pg3 { + nvidia,pins = "soc_gpio16_pg3"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + soc_gpio17_pg4 { + nvidia,pins = "soc_gpio17_pg4"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + soc_gpio18_pg5 { + nvidia,pins = "soc_gpio18_pg5"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + soc_gpio22_ph1 { + nvidia,pins = "soc_gpio22_ph1"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + soc_gpio06_ph2 { + nvidia,pins = "soc_gpio06_ph2"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + uart4_tx_ph3 { + nvidia,pins = "uart4_tx_ph3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + uart4_rx_ph4 { + nvidia,pins = "uart4_rx_ph4"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + uart4_rts_ph5 { + nvidia,pins = "uart4_rts_ph5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + qspi1_sck_pc6 { + nvidia,pins = "qspi1_sck_pc6"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,loopback = ; + }; + + qspi1_cs_n_pc7 { + nvidia,pins = "qspi1_cs_n_pc7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + qspi1_io0_pd0 { + nvidia,pins = "qspi1_io0_pd0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + qspi1_io1_pd1 { + nvidia,pins = "qspi1_io1_pd1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + qspi1_io2_pd2 { + nvidia,pins = "qspi1_io2_pd2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + qspi1_io3_pd3 { + nvidia,pins = "qspi1_io3_pd3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + eqos_txc_pe0 { + nvidia,pins = "eqos_txc_pe0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + eqos_td0_pe1 { + nvidia,pins = "eqos_td0_pe1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + eqos_td1_pe2 { + nvidia,pins = "eqos_td1_pe2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + eqos_td2_pe3 { + nvidia,pins = "eqos_td2_pe3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + eqos_td3_pe4 { + nvidia,pins = "eqos_td3_pe4"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + eqos_tx_ctl_pe5 { + nvidia,pins = "eqos_tx_ctl_pe5"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + eqos_rd0_pe6 { + nvidia,pins = "eqos_rd0_pe6"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + eqos_rd1_pe7 { + nvidia,pins = "eqos_rd1_pe7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + eqos_rd2_pf0 { + nvidia,pins = "eqos_rd2_pf0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + eqos_rd3_pf1 { + nvidia,pins = "eqos_rd3_pf1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + eqos_rx_ctl_pf2 { + nvidia,pins = "eqos_rx_ctl_pf2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + eqos_rxc_pf3 { + nvidia,pins = "eqos_rxc_pf3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + eqos_sma_mdio_pf4 { + nvidia,pins = "eqos_sma_mdio_pf4"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + eqos_sma_mdc_pf5 { + nvidia,pins = "eqos_sma_mdc_pf5"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi5_miso_pac1 { + nvidia,pins = "spi5_miso_pac1"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + spi5_mosi_pac2 { + nvidia,pins = "spi5_mosi_pac2"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + spi5_cs0_pac3 { + nvidia,pins = "spi5_cs0_pac3"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + soc_gpio57_pac4 { + nvidia,pins = "soc_gpio57_pac4"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + soc_gpio58_pac5 { + nvidia,pins = "soc_gpio58_pac5"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + soc_gpio60_pac7 { + nvidia,pins = "soc_gpio60_pac7"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + soc_gpio45_pad0 { + nvidia,pins = "soc_gpio45_pad0"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + soc_gpio46_pad1 { + nvidia,pins = "soc_gpio46_pad1"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + soc_gpio47_pad2 { + nvidia,pins = "soc_gpio47_pad2"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + soc_gpio48_pad3 { + nvidia,pins = "soc_gpio48_pad3"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + ufs0_ref_clk_pae0 { + nvidia,pins = "ufs0_ref_clk_pae0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ufs0_rst_n_pae1 { + nvidia,pins = "ufs0_rst_n_pae1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l0_clkreq_n_pk0 { + nvidia,pins = "pex_l0_clkreq_n_pk0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + pex_l0_rst_n_pk1 { + nvidia,pins = "pex_l0_rst_n_pk1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + pex_l3_clkreq_n_pk6 { + nvidia,pins = "pex_l3_clkreq_n_pk6"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + pex_l3_rst_n_pk7 { + nvidia,pins = "pex_l3_rst_n_pk7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + soc_gpio34_pl3 { + nvidia,pins = "soc_gpio34_pl3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + pex_l10_clkreq_n_pag6 { + nvidia,pins = "pex_l10_clkreq_n_pag6"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + pex_l10_rst_n_pag7 { + nvidia,pins = "pex_l10_rst_n_pag7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + can2_dout_ps0 { + nvidia,pins = "can2_dout_ps0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + can2_din_ps1 { + nvidia,pins = "can2_din_ps1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + can2_stb_ps2 { + nvidia,pins = "can2_stb_ps2"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + can2_en_ps3 { + nvidia,pins = "can2_en_ps3"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + can2_err_ps4 { + nvidia,pins = "can2_err_ps4"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + can3_dout_ps5 { + nvidia,pins = "can3_dout_ps5"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + can3_din_ps6 { + nvidia,pins = "can3_din_ps6"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + can3_stb_ps7 { + nvidia,pins = "can3_stb_ps7"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + can3_en_pt0 { + nvidia,pins = "can3_en_pt0"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + can3_err_pt1 { + nvidia,pins = "can3_err_pt1"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + soc_error_pu0 { + nvidia,pins = "soc_error_pu0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + uart7_tx_pu1 { + nvidia,pins = "uart7_tx_pu1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + uart7_rx_pu2 { + nvidia,pins = "uart7_rx_pu2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + spi7_sck_pu3 { + nvidia,pins = "spi7_sck_pu3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + spi7_miso_pu4 { + nvidia,pins = "spi7_miso_pu4"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + spi7_mosi_pu5 { + nvidia,pins = "spi7_mosi_pu5"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + spi7_cs0_pu6 { + nvidia,pins = "spi7_cs0_pu6"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + soc_gpio51_pu7 { + nvidia,pins = "soc_gpio51_pu7"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + soc_gpio52_pv0 { + nvidia,pins = "soc_gpio52_pv0"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + soc_gpio61_pw0 { + nvidia,pins = "soc_gpio61_pw0"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + soc_gpio62_pw1 { + nvidia,pins = "soc_gpio62_pw1"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + dap6_dout_pa1 { + nvidia,pins = "dap6_dout_pa1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + dap6_din_pa2 { + nvidia,pins = "dap6_din_pa2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + dap6_fs_pa3 { + nvidia,pins = "dap6_fs_pa3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lpdr = ; + }; + + pex_l5_clkreq_n_paf0 { + nvidia,pins = "pex_l5_clkreq_n_paf0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + pex_l5_rst_n_paf1 { + nvidia,pins = "pex_l5_rst_n_paf1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + pex_l6_clkreq_n_paf2 { + nvidia,pins = "pex_l6_clkreq_n_paf2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + pex_l6_rst_n_paf3 { + nvidia,pins = "pex_l6_rst_n_paf3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,lpdr = ; + }; + + emmc_clk { + nvidia,pins = "emmc_clk"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,loopback = ; + }; + + emmc_cmd { + nvidia,pins = "emmc_cmd"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,loopback = ; + }; + + emmc_dat0 { + nvidia,pins = "emmc_dat0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,loopback = ; + }; + + emmc_dat1 { + nvidia,pins = "emmc_dat1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,loopback = ; + }; + + emmc_dat2 { + nvidia,pins = "emmc_dat2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,loopback = ; + }; + + emmc_dat3 { + nvidia,pins = "emmc_dat3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,loopback = ; + }; + + emmc_dat4 { + nvidia,pins = "emmc_dat4"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,loopback = ; + }; + + emmc_dat5 { + nvidia,pins = "emmc_dat5"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,loopback = ; + }; + + emmc_dat6 { + nvidia,pins = "emmc_dat6"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,loopback = ; + }; + + emmc_dat7 { + nvidia,pins = "emmc_dat7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,loopback = ; + }; + + emmc_dqs { + nvidia,pins = "emmc_dqs"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + + drive_default: drive { + }; + }; +}; diff --git a/products/PAB_CAN/device_tree/bootloader/generic/BCT/tegra234-mb2-bct-misc-p3767-0000.dts b/products/PAB_CAN/device_tree/bootloader/generic/BCT/tegra234-mb2-bct-misc-p3767-0000.dts new file mode 100644 index 0000000..3436dbb --- /dev/null +++ b/products/PAB_CAN/device_tree/bootloader/generic/BCT/tegra234-mb2-bct-misc-p3767-0000.dts @@ -0,0 +1,16 @@ +/dts-v1/; + +#include "tegra234-mb2-bct-common.dtsi" + +/ { + mb2-misc { + eeprom { + cvm_eeprom_i2c_instance = <0>; + cvm_eeprom_i2c_slave_address = <0xa0>; + cvm_eeprom_read_size = <0x100>; + cvb_eeprom_i2c_instance = <0x0>; + cvb_eeprom_i2c_slave_address = <0xae>; + cvb_eeprom_read_size = <0x0>; + }; + }; +}; diff --git a/products/PAB_CAN/device_tree/bootloader/tegra234-mb1-bct-gpio-p3767-dp-a03.dtsi b/products/PAB_CAN/device_tree/bootloader/tegra234-mb1-bct-gpio-p3767-dp-a03.dtsi new file mode 100644 index 0000000..2f20882 --- /dev/null +++ b/products/PAB_CAN/device_tree/bootloader/tegra234-mb1-bct-gpio-p3767-dp-a03.dtsi @@ -0,0 +1,126 @@ +/*This dtsi file was generated by jetson orin nano&nx pinmux hdmi.xlsm Revision: 1.04 */ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 'AS IS' + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "tegra234-gpio.h" + + +/ { + gpio@2200000 { + gpio-init-names = "default"; + gpio-init-0 = <&gpio_main_default>; + + gpio_main_default: default { + /* PAC.06 / GPIO09 = SWITCH_RSTn (LAN96455S nRESET, active-low). + * Hold LOW through MB1 so nRESET stays asserted while rails/clocks + * come up. Kernel gpio-hog then drives HIGH (run), producing the + * rising edge the chip needs to latch straps and start ROM boot. + * Low = reset, high = run. */ + gpio-input = < + TEGRA234_MAIN_GPIO(B, 0) + TEGRA234_MAIN_GPIO(Y, 0) + TEGRA234_MAIN_GPIO(Y, 1) + TEGRA234_MAIN_GPIO(Y, 2) + TEGRA234_MAIN_GPIO(Y, 3) + TEGRA234_MAIN_GPIO(Y, 4) + TEGRA234_MAIN_GPIO(Z, 1) + TEGRA234_MAIN_GPIO(Z, 3) + TEGRA234_MAIN_GPIO(Z, 4) + TEGRA234_MAIN_GPIO(Z, 5) + TEGRA234_MAIN_GPIO(Z, 6) + TEGRA234_MAIN_GPIO(Z, 7) + TEGRA234_MAIN_GPIO(P, 6) + TEGRA234_MAIN_GPIO(Q, 5) + TEGRA234_MAIN_GPIO(Q, 6) + TEGRA234_MAIN_GPIO(R, 4) + TEGRA234_MAIN_GPIO(R, 5) + TEGRA234_MAIN_GPIO(M, 0) + TEGRA234_MAIN_GPIO(N, 1) + TEGRA234_MAIN_GPIO(G, 0) + TEGRA234_MAIN_GPIO(G, 7) + TEGRA234_MAIN_GPIO(L, 2) + >; + gpio-output-low = < + TEGRA234_MAIN_GPIO(H, 0) + TEGRA234_MAIN_GPIO(H, 6) + TEGRA234_MAIN_GPIO(H, 7) + TEGRA234_MAIN_GPIO(I, 0) + TEGRA234_MAIN_GPIO(I, 1) + TEGRA234_MAIN_GPIO(I, 2) + TEGRA234_MAIN_GPIO(I, 5) + TEGRA234_MAIN_GPIO(AC, 0) + TEGRA234_MAIN_GPIO(AC, 6) + TEGRA234_MAIN_GPIO(K, 4) + TEGRA234_MAIN_GPIO(K, 5) + >; + gpio-output-high = < + TEGRA234_MAIN_GPIO(Q, 3) + TEGRA234_MAIN_GPIO(G, 6) + TEGRA234_MAIN_GPIO(A, 0) + >; + }; + }; + gpio@c2f0000 { + gpio-init-names = "default"; + gpio-init-0 = <&gpio_aon_default>; + + gpio_aon_default: default { + gpio-input = < + TEGRA234_AON_GPIO(EE, 2) + TEGRA234_AON_GPIO(EE, 4) + >; + gpio-output-low = < + TEGRA234_AON_GPIO(CC, 0) + TEGRA234_AON_GPIO(CC, 2) + TEGRA234_AON_GPIO(CC, 3) + TEGRA234_AON_GPIO(AA, 4) + >; + gpio-output-high = < + TEGRA234_AON_GPIO(CC, 1) + TEGRA234_AON_GPIO(AA, 5) + TEGRA234_AON_GPIO(BB, 3) + >; + }; + }; + gpio@9250000 { + gpio-init-names = "default"; + gpio-init-0 = <&gpio_fsi_default>; + + gpio_fsi_default: default { + gpio-input = < + >; + gpio-output-low = < + >; + gpio-output-high = < + >; + }; + }; + +}; diff --git a/products/PAB_CAN/device_tree/source/hardware/nvidia/t23x/nv-public/nv-platform/ark-PAB_CAN-overrides.dtsi b/products/PAB_CAN/device_tree/source/hardware/nvidia/t23x/nv-public/nv-platform/ark-PAB_CAN-overrides.dtsi new file mode 100644 index 0000000..7403b30 --- /dev/null +++ b/products/PAB_CAN/device_tree/source/hardware/nvidia/t23x/nv-public/nv-platform/ark-PAB_CAN-overrides.dtsi @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ARK PAB_CAN carrier device-tree delta. + * + * build.sh appends an #include of this file to the stock + * tegra234-p3768-0000+p3767-xxxx-nv-common.dtsi, so it is layered last over the + * pristine BSP tree. Only ARK's delta lives here; everything else tracks the BSP. + * Per-SKU model strings are stamped separately from products/PAB_CAN/dtb_models.env. + * + * The carrier is the PAB_V3 with the IO MCU removed, the Jetson CAN controller + * (stock-enabled mttcan@c310000, module pins 143/145) routed through an on-board + * TCAN1057A to the Pixhawk Payload Bus connector, UART0 moved from the M.2 Key E + * Bluetooth pins to an external JST-GH, and the KSZ8795 ethernet switch replaced + * by a Microchip LAN96455S. + */ + +#include + +/* HDMI display: re-assigns display@13800000's nvidia,dcb-image with the HDMI blob. */ +#include "tegra234-dcb-p3737-0000-p3701-0000-hdmi.dtsi" + +/ { + aliases { + serial3 = &uartb; + }; +}; + +/* UARTB is wired on the carrier but undefined by the stock SoC dtsi. Declared as an + * hsuart (not the tegra20-uart/8250 base) so it enumerates as /dev/ttyTHS*, like the + * other Tegra UARTs. Stays PIO — stock's gpcdma RX-DMA corrupts the hsuart RX stream + * at high baud (see UART-A below). */ +&{/bus@0} { + uartb: serial@3110000 { + compatible = "nvidia,tegra194-hsuart"; + reg = <0x0 0x03110000 0x0 0x10000>; + interrupts = ; + clocks = <&bpmp TEGRA234_CLK_UARTB>; + resets = <&bpmp TEGRA234_RESET_UARTB>; + reset-names = "serial"; + status = "okay"; + }; +}; + +/* UART-A (ttyTHS1) inherits gpcdma RX/TX DMA from stock R36.5.0, and that DMA path + * corrupts the hsuart RX stream at 3 Mbaud. Force PIO, like UART-B. */ +&{/bus@0/serial@3100000} { + /delete-property/ dmas; + /delete-property/ dma-names; +}; + +/* HD-Audio is used on the carrier. */ +&{/bus@0/hda@3510000} { + status = "okay"; +}; + +/* Hotplug detect line is active-low on the PAB_CAN carrier. Also drop the stock + * hdcp_enabled: it's inert on L4T (no HDCP) and triggers the JP6.2.2 DpAuxchCtrl DCE-RPC + * regression on the DP->HDMI path. Native HDMI here shouldn't hit it, but keep HDCP off + * across all carriers for consistency. */ +&{/display@13800000} { + os_gpio_hotplug_a = <&gpio TEGRA234_MAIN_GPIO(M, 0) GPIO_ACTIVE_LOW>; + /delete-property/ hdcp_enabled; +}; + +/* SPI1 pin group for the LAN96455S management interface. + * Module connector labels these pins SPI0; the SoC controller is SPI1 + * (spi@3210000, pinmux spi1_*_pz3..pz6). */ +&{/bus@0/pinmux@2430000} { + spi1_default: spi1-default { + spi1-pins { + nvidia,pins = "spi1_sck_pz3", "spi1_miso_pz4", + "spi1_mosi_pz5", "spi1_cs0_pz6"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; +}; + +/* SPI1: LAN96455S-I/8MW ethernet switch management interface on CS0. + * Strapped for SPI client (MGMT_MODE=3) and ROM boot (BOOT_MODE=3). + * + * SWITCH_RSTn is module pin 211 (GPIO09 / AUD_MCLK / PAC.06), active-low + * nRESET: low = reset, high = run. MB1 BCT holds PAC.06 LOW through early + * boot; a gpio-hog then drives HIGH so the rising edge latches straps and + * starts unmanaged ROM boot. Leave the hog high for the life of Linux. + * + * Override stock spi@0 (tegra-spidev) so CS0 is not double-registered. R36 + * 5.15 has no LAN9645x DSA driver, so nothing binds; the node reserves CS0. */ +&{/bus@0/spi@3210000} { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_default>; + + spi@0 { + compatible = "microchip,lan96455s"; + reg = <0x0>; + spi-max-frequency = <50000000>; + /* reset-gpios owned by the hog below until a DSA driver lands. */ + controller-data { + nvidia,enable-hw-based-cs; + nvidia,rx-clk-tap-delay = <0x10>; + nvidia,tx-clk-tap-delay = <0x0>; + }; + }; +}; + +/* Release SWITCH_RSTn after rails are up: BCT held it low; hog drives high + * (rising edge → strap latch + ROM boot) and keeps run for the kernel life. */ +&{/bus@0/gpio@2200000} { + lan96455s_reset_hog { + gpio-hog; + gpios = ; + output-high; + line-name = "lan96455s-reset-n"; + }; +}; + +/* Carrier USB port mapping: only usb3-0 (USB-C) is brought out. Stock wires + * usb3-1 for the devkit's second SS port; drop the port and disable its lane. */ +&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1} { + status = "disabled"; +}; + +&{/bus@0/padctl@3520000/ports} { + /delete-node/ usb3-1; + usb3-0 { nvidia,usb2-companion = <0>; }; +}; + +&{/bus@0/usb@3550000} { + phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>, + <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-0}>; + phy-names = "usb2-0", "usb3-0"; +}; + +&{/bus@0/usb@3610000} { + phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>, + <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-1}>, + <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-2}>, + <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-0}>; + phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0"; +}; diff --git a/products/PAB_CAN/device_tree/source/hardware/nvidia/t23x/nv-public/nv-platform/tegra234-dcb-p3737-0000-p3701-0000-hdmi.dtsi b/products/PAB_CAN/device_tree/source/hardware/nvidia/t23x/nv-public/nv-platform/tegra234-dcb-p3737-0000-p3701-0000-hdmi.dtsi new file mode 100644 index 0000000..a6a6a45 --- /dev/null +++ b/products/PAB_CAN/device_tree/source/hardware/nvidia/t23x/nv-public/nv-platform/tegra234-dcb-p3737-0000-p3701-0000-hdmi.dtsi @@ -0,0 +1,549 @@ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: Copyright (c) 2021-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. + +/ { + display@13800000 { + nvidia,dcb-image = [ + 55 aa 16 00 00 37 34 30 30 e9 4c 19 77 cc 56 49 + 44 45 4f 20 0d 00 00 00 70 01 00 00 00 00 49 42 + 4d 20 56 47 41 20 43 6f 6d 70 61 74 69 62 6c 65 + 01 00 00 00 10 00 82 18 30 33 2f 31 36 2f 32 33 + 00 00 00 00 00 00 00 00 21 18 50 00 e1 2b 00 00 + 50 4d 49 44 00 00 00 00 00 00 00 a0 00 b0 00 b8 + 00 c0 00 0e 47 41 31 30 42 20 56 47 41 20 42 49 + 4f 53 0d 0a 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 56 65 72 73 69 6f 6e 20 39 34 2e + 30 42 2e 30 30 2e 30 30 2e 32 31 20 0d 0a 00 43 + 6f 70 79 72 69 67 68 74 20 28 43 29 20 31 39 39 + 36 2d 32 30 32 33 20 4e 56 49 44 49 41 20 43 6f + 72 70 2e 0d 0a 00 00 00 ff ff 00 00 00 00 ff ff + 47 50 55 20 42 6f 61 72 64 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 43 68 69 70 20 52 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40 00 00 00 00 00 00 + 00 06 00 00 00 00 00 05 05 00 00 00 00 00 00 00 + 00 00 ]; + }; +}; diff --git a/products/PAB_CAN/dtb_models.env b/products/PAB_CAN/dtb_models.env new file mode 100644 index 0000000..693e154 --- /dev/null +++ b/products/PAB_CAN/dtb_models.env @@ -0,0 +1,8 @@ +# Per-SKU device-tree model strings, stamped onto the stock p3768 DTS by build.sh. +# Format: =. The matching -nv-super DTB gets " Super" appended. +# SKUs not listed keep NVIDIA's stock model. +0000=NVIDIA Jetson Orin NX 16GB ARK PAB_CAN Jetson Carrier +0001=NVIDIA Jetson Orin NX 8GB ARK PAB_CAN Jetson Carrier +0003=NVIDIA Jetson Orin Nano 8GB ARK PAB_CAN Jetson Carrier +0004=NVIDIA Jetson Orin Nano 4GB ARK PAB_CAN Jetson Carrier +0005=NVIDIA Jetson Orin Nano 8GB ARK PAB_CAN Jetson Carrier diff --git a/products/PAB_CAN/overlay/dtbo.list b/products/PAB_CAN/overlay/dtbo.list new file mode 100644 index 0000000..b7cdd47 --- /dev/null +++ b/products/PAB_CAN/overlay/dtbo.list @@ -0,0 +1,9 @@ +# Overlays ARK ships for PAB_CAN — the explicit dtbo set built into the image and +# offered by jetson-io. One dtbo basename per line ('#' comments allowed); each +# must have a matching source file in this dir. build.sh disables the stock p3768 +# camera overlays and builds exactly this list (plus the BSP's non-camera +# overlays). PAB_CAN uses the dev-kit i2c-mux-gpio wiring, so it ships the dual +# IMX219/IMX477/IMX708 overlays. +tegra234-p3767-camera-p3768-imx219-dual.dtbo +tegra234-p3767-camera-p3768-imx477-dual.dtbo +tegra234-p3767-camera-p3768-imx708-dual.dtbo diff --git a/products/PAB_CAN/overlay/tegra234-camera-rbpcv2-imx219.dtsi b/products/PAB_CAN/overlay/tegra234-camera-rbpcv2-imx219.dtsi new file mode 100644 index 0000000..44593fb --- /dev/null +++ b/products/PAB_CAN/overlay/tegra234-camera-rbpcv2-imx219.dtsi @@ -0,0 +1,761 @@ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. + +#include +#include + +/ { + fragment-camera@0 { + target-path = "/"; + __overlay__ { + tegra-capture-vi { + num-channels = <2>; + ports { + #address-cells = <1>; + #size-cells = <0>; + vi_port0: port@0 { + reg = <0>; + rbpcv2_imx219_vi_in0: endpoint { + port-index = <0>; + bus-width = <2>; + remote-endpoint = <&rbpcv2_imx219_csi_out0>; + }; + }; + vi_port1: port@1 { + reg = <1>; + rbpcv2_imx219_vi_in1: endpoint { + port-index = <2>; + bus-width = <2>; + remote-endpoint = <&rbpcv2_imx219_csi_out1>; + }; + }; + }; + }; + + bus@0 { + host1x@13e00000 { + nvcsi@15a00000 { + num-channels = <2>; + #address-cells = <1>; + #size-cells = <0>; + csi_chan0: channel@0 { + reg = <0>; + ports { + #address-cells = <1>; + #size-cells = <0>; + csi_chan0_port0: port@0 { + reg = <0>; + rbpcv2_imx219_csi_in0: endpoint@0 { + port-index = <0>; + bus-width = <2>; + remote-endpoint = <&rbpcv2_imx219_out0>; + }; + }; + csi_chan0_port1: port@1 { + reg = <1>; + rbpcv2_imx219_csi_out0: endpoint@1 { + remote-endpoint = <&rbpcv2_imx219_vi_in0>; + }; + }; + }; + }; + csi_chan1: channel@1 { + reg = <1>; + ports { + #address-cells = <1>; + #size-cells = <0>; + csi_chan1_port0: port@0 { + reg = <0>; + rbpcv2_imx219_csi_in1: endpoint@2 { + port-index = <2>; + bus-width = <2>; + remote-endpoint = <&rbpcv2_imx219_out1>; + }; + }; + csi_chan1_port1: port@1 { + reg = <1>; + rbpcv2_imx219_csi_out1: endpoint@3 { + remote-endpoint = <&rbpcv2_imx219_vi_in1>; + }; + }; + }; + }; + }; + }; + cam_i2cmux { + i2c_0:i2c@0 { + imx219_cam0: rbpcv2_imx219_a@10 { + compatible = "sony,imx219"; + /* I2C device address */ + reg = <0x10>; + /* V4L2 device node location */ + devnode = "video0"; + /* Physical dimensions of sensor */ + physical_w = "3.680"; + physical_h = "2.760"; + sensor_model = "imx219"; + use_sensor_mode_id = "true"; + /** + * ==== Modes ==== + * A modeX node is required to support v4l2 driver + * implementation with NVIDIA camera software stack + * + * == Signal properties == + * + * phy_mode = ""; + * PHY mode used by the MIPI lanes for this device + * + * tegra_sinterface = ""; + * CSI Serial interface connected to tegra + * Incase of virtual HW devices, use virtual + * For SW emulated devices, use host + * + * pix_clk_hz = ""; + * Sensor pixel clock used for calculations like exposure and framerate + * + * readout_orientation = "0"; + * Based on camera module orientation. + * Only change readout_orientation if you specifically + * Program a different readout order for this mode + * + * == Image format Properties == + * + * active_w = ""; + * Pixel active region width + * + * active_h = ""; + * Pixel active region height + * + * pixel_t = ""; + * The sensor readout pixel pattern + * + * line_length = ""; + * Pixel line length (width) for sensor mode. + * + * == Source Control Settings == + * + * Gain factor used to convert fixed point integer to float + * Gain range [min_gain/gain_factor, max_gain/gain_factor] + * Gain step [step_gain/gain_factor is the smallest step that can be configured] + * Default gain [Default gain to be initialized for the control. + * use min_gain_val as default for optimal results] + * Framerate factor used to convert fixed point integer to float + * Framerate range [min_framerate/framerate_factor, max_framerate/framerate_factor] + * Framerate step [step_framerate/framerate_factor is the smallest step that can be configured] + * Default Framerate [Default framerate to be initialized for the control. + * use max_framerate to get required performance] + * Exposure factor used to convert fixed point integer to float + * For convenience use 1 sec = 1000000us as conversion factor + * Exposure range [min_exp_time/exposure_factor, max_exp_time/exposure_factor] + * Exposure step [step_exp_time/exposure_factor is the smallest step that can be configured] + * Default Exposure Time [Default exposure to be initialized for the control. + * Set default exposure based on the default_framerate for optimal exposure settings] + * + * gain_factor = ""; (integer factor used for floating to fixed point conversion) + * min_gain_val = ""; (ceil to integer) + * max_gain_val = ""; (ceil to integer) + * step_gain_val = ""; (ceil to integer) + * default_gain = ""; (ceil to integer) + * Gain limits for mode + * + * exposure_factor = ""; (integer factor used for floating to fixed point conversion) + * min_exp_time = ""; (ceil to integer) + * max_exp_time = ""; (ceil to integer) + * step_exp_time = ""; (ceil to integer) + * default_exp_time = ""; (ceil to integer) + * Exposure Time limits for mode (sec) + * + * framerate_factor = ""; (integer factor used for floating to fixed point conversion) + * min_framerate = ""; (ceil to integer) + * max_framerate = ""; (ceil to integer) + * step_framerate = ""; (ceil to integer) + * default_framerate = ""; (ceil to integer) + * Framerate limits for mode (fps) + * + * embedded_metadata_height = ""; + * Sensor embedded metadata height in units of rows. + * If sensor does not support embedded metadata value should be 0. + */ + mode0 { /* IMX219_MODE_3280x2464_21FPS */ + mclk_khz = "24000"; + num_lanes = "2"; + tegra_sinterface = "serial_a"; + lane_polarity = "6"; + phy_mode = "DPHY"; + discontinuous_clk = "yes"; + dpcm_enable = "false"; + cil_settletime = "0"; + active_w = "3280"; + active_h = "2464"; + mode_type = "bayer"; + pixel_phase = "rggb"; + csi_pixel_bit_depth = "10"; + readout_orientation = "90"; + line_length = "3448"; + inherent_gain = "1"; + mclk_multiplier = "9.33"; + pix_clk_hz = "182400000"; + gain_factor = "16"; + framerate_factor = "1000000"; + exposure_factor = "1000000"; + min_gain_val = "16"; /* 1.00x */ + max_gain_val = "170"; /* 10.66x */ + step_gain_val = "1"; + default_gain = "16"; /* 1.00x */ + min_hdr_ratio = "1"; + max_hdr_ratio = "1"; + min_framerate = "2000000"; /* 2.0 fps */ + max_framerate = "21000000"; /* 21.0 fps */ + step_framerate = "1"; + default_framerate = "21000000"; /* 21.0 fps */ + min_exp_time = "13"; /* us */ + max_exp_time = "683709"; /* us */ + step_exp_time = "1"; + default_exp_time = "2495"; /* us */ + embedded_metadata_height = "2"; + }; + mode1 { /* IMX219_MODE_3280x1848_28FPS */ + mclk_khz = "24000"; + num_lanes = "2"; + tegra_sinterface = "serial_a"; + lane_polarity = "6"; + phy_mode = "DPHY"; + discontinuous_clk = "yes"; + dpcm_enable = "false"; + cil_settletime = "0"; + active_w = "3280"; + active_h = "1848"; + mode_type = "bayer"; + pixel_phase = "rggb"; + csi_pixel_bit_depth = "10"; + readout_orientation = "90"; + line_length = "3448"; + inherent_gain = "1"; + mclk_multiplier = "9.33"; + pix_clk_hz = "182400000"; + gain_factor = "16"; + framerate_factor = "1000000"; + exposure_factor = "1000000"; + min_gain_val = "16"; /* 1.00x */ + max_gain_val = "170"; /* 10.66x */ + step_gain_val = "1"; + default_gain = "16"; /* 1.00x */ + min_hdr_ratio = "1"; + max_hdr_ratio = "1"; + min_framerate = "2000000"; /* 2.0 fps */ + max_framerate = "28000000"; /* 28.0 fps */ + step_framerate = "1"; + default_framerate = "28000000"; /* 28.0 fps */ + min_exp_time = "13"; /* us */ + max_exp_time = "683709"; /* us */ + step_exp_time = "1"; + default_exp_time = "2495"; /* us */ + embedded_metadata_height = "2"; + }; + mode2 { /* IMX219_MODE_1920x1080_30FPS */ + mclk_khz = "24000"; + num_lanes = "2"; + tegra_sinterface = "serial_a"; + lane_polarity = "6"; + phy_mode = "DPHY"; + discontinuous_clk = "yes"; + dpcm_enable = "false"; + cil_settletime = "0"; + active_w = "1920"; + active_h = "1080"; + mode_type = "bayer"; + pixel_phase = "rggb"; + csi_pixel_bit_depth = "10"; + readout_orientation = "90"; + line_length = "3448"; + inherent_gain = "1"; + mclk_multiplier = "9.33"; + pix_clk_hz = "182400000"; + gain_factor = "16"; + framerate_factor = "1000000"; + exposure_factor = "1000000"; + min_gain_val = "16"; /* 1.00x */ + max_gain_val = "170"; /* 10.66x */ + step_gain_val = "1"; + default_gain = "16"; /* 1.00x */ + min_hdr_ratio = "1"; + max_hdr_ratio = "1"; + min_framerate = "2000000"; /* 2.0 fps */ + max_framerate = "30000000"; /* 30.0 fps */ + step_framerate = "1"; + default_framerate = "30000000"; /* 30.0 fps */ + min_exp_time = "13"; /* us */ + max_exp_time = "683709"; /* us */ + step_exp_time = "1"; + default_exp_time = "2495"; /* us */ + embedded_metadata_height = "2"; + }; + mode3 { /* IMX219_MODE_1640x1232_30FPS */ + mclk_khz = "24000"; + num_lanes = "2"; + tegra_sinterface = "serial_a"; + lane_polarity = "6"; + phy_mode = "DPHY"; + discontinuous_clk = "yes"; + dpcm_enable = "false"; + cil_settletime = "0"; + active_w = "1640"; + active_h = "1232"; + mode_type = "bayer"; + pixel_phase = "rggb"; + csi_pixel_bit_depth = "10"; + readout_orientation = "90"; + line_length = "3448"; + inherent_gain = "1"; + mclk_multiplier = "9.33"; + pix_clk_hz = "182400000"; + gain_factor = "16"; + framerate_factor = "1000000"; + exposure_factor = "1000000"; + min_gain_val = "16"; /* 1.00x */ + max_gain_val = "170"; /* 10.66x */ + step_gain_val = "1"; + default_gain = "16"; /* 1.00x */ + min_hdr_ratio = "1"; + max_hdr_ratio = "1"; + min_framerate = "2000000"; /* 2.0 fps */ + max_framerate = "30000000"; /* 60.0 fps */ + step_framerate = "1"; + default_framerate = "30000000"; /* 60.0 fps */ + min_exp_time = "13"; /* us */ + max_exp_time = "683709"; /* us */ + step_exp_time = "1"; + default_exp_time = "2495"; /* us */ + embedded_metadata_height = "2"; + }; + mode4 { /* IMX219_MODE_1280x720_60FPS */ + mclk_khz = "24000"; + num_lanes = "2"; + tegra_sinterface = "serial_a"; + lane_polarity = "6"; + phy_mode = "DPHY"; + discontinuous_clk = "yes"; + dpcm_enable = "false"; + cil_settletime = "0"; + active_w = "1280"; + active_h = "720"; + mode_type = "bayer"; + pixel_phase = "rggb"; + csi_pixel_bit_depth = "10"; + readout_orientation = "90"; + line_length = "3448"; + inherent_gain = "1"; + mclk_multiplier = "9.33"; + pix_clk_hz = "182400000"; + gain_factor = "16"; + framerate_factor = "1000000"; + exposure_factor = "1000000"; + min_gain_val = "16"; /* 1.00x */ + max_gain_val = "170"; /* 10.66x */ + step_gain_val = "1"; + default_gain = "16"; /* 1.00x */ + min_hdr_ratio = "1"; + max_hdr_ratio = "1"; + min_framerate = "2000000"; /* 2.0 fps */ + max_framerate = "60000000"; /* 60.0 fps */ + step_framerate = "1"; + default_framerate = "60000000"; /* 60.0 fps */ + min_exp_time = "13"; /* us */ + max_exp_time = "683709"; /* us */ + step_exp_time = "1"; + default_exp_time = "2495"; /* us */ + embedded_metadata_height = "2"; + }; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + rbpcv2_imx219_out0: endpoint { + port-index = <0>; + bus-width = <2>; + remote-endpoint = <&rbpcv2_imx219_csi_in0>; + }; + }; + }; + }; + }; + i2c_1: i2c@1 { + imx219_cam1: rbpcv2_imx219_c@10 { + compatible = "sony,imx219"; + /* I2C device address */ + reg = <0x10>; + /* V4L2 device node location */ + devnode = "video1"; + /* Physical dimensions of sensor */ + physical_w = "3.680"; + physical_h = "2.760"; + sensor_model = "imx219"; + use_sensor_mode_id = "true"; + /** + * ==== Modes ==== + * A modeX node is required to support v4l2 driver + * implementation with NVIDIA camera software stack + * + * == Signal properties == + * + * phy_mode = ""; + * PHY mode used by the MIPI lanes for this device + * + * tegra_sinterface = ""; + * CSI Serial interface connected to tegra + * Incase of virtual HW devices, use virtual + * For SW emulated devices, use host + * + * pix_clk_hz = ""; + * Sensor pixel clock used for calculations like exposure and framerate + * + * readout_orientation = "0"; + * Based on camera module orientation. + * Only change readout_orientation if you specifically + * Program a different readout order for this mode + * + * == Image format Properties == + * + * active_w = ""; + * Pixel active region width + * + * active_h = ""; + * Pixel active region height + * + * pixel_t = ""; + * The sensor readout pixel pattern + * + * line_length = ""; + * Pixel line length (width) for sensor mode. + * + * == Source Control Settings == + * + * Gain factor used to convert fixed point integer to float + * Gain range [min_gain/gain_factor, max_gain/gain_factor] + * Gain step [step_gain/gain_factor is the smallest step that can be configured] + * Default gain [Default gain to be initialized for the control. + * use min_gain_val as default for optimal results] + * Framerate factor used to convert fixed point integer to float + * Framerate range [min_framerate/framerate_factor, max_framerate/framerate_factor] + * Framerate step [step_framerate/framerate_factor is the smallest step that can be configured] + * Default Framerate [Default framerate to be initialized for the control. + * use max_framerate to get required performance] + * Exposure factor used to convert fixed point integer to float + * For convenience use 1 sec = 1000000us as conversion factor + * Exposure range [min_exp_time/exposure_factor, max_exp_time/exposure_factor] + * Exposure step [step_exp_time/exposure_factor is the smallest step that can be configured] + * Default Exposure Time [Default exposure to be initialized for the control. + * Set default exposure based on the default_framerate for optimal exposure settings] + * + * gain_factor = ""; (integer factor used for floating to fixed point conversion) + * min_gain_val = ""; (ceil to integer) + * max_gain_val = ""; (ceil to integer) + * step_gain_val = ""; (ceil to integer) + * default_gain = ""; (ceil to integer) + * Gain limits for mode + * + * exposure_factor = ""; (integer factor used for floating to fixed point conversion) + * min_exp_time = ""; (ceil to integer) + * max_exp_time = ""; (ceil to integer) + * step_exp_time = ""; (ceil to integer) + * default_exp_time = ""; (ceil to integer) + * Exposure Time limits for mode (sec) + * + * framerate_factor = ""; (integer factor used for floating to fixed point conversion) + * min_framerate = ""; (ceil to integer) + * max_framerate = ""; (ceil to integer) + * step_framerate = ""; (ceil to integer) + * default_framerate = ""; (ceil to integer) + * Framerate limits for mode (fps) + * + * embedded_metadata_height = ""; + * Sensor embedded metadata height in units of rows. + * If sensor does not support embedded metadata value should be 0. + */ + mode0 { /* IMX219_MODE_3280x2464_21FPS */ + mclk_khz = "24000"; + num_lanes = "2"; + tegra_sinterface = "serial_c"; + phy_mode = "DPHY"; + discontinuous_clk = "yes"; + dpcm_enable = "false"; + cil_settletime = "0"; + active_w = "3280"; + active_h = "2464"; + mode_type = "bayer"; + pixel_phase = "rggb"; + csi_pixel_bit_depth = "10"; + readout_orientation = "90"; + line_length = "3448"; + inherent_gain = "1"; + mclk_multiplier = "9.33"; + pix_clk_hz = "182400000"; + gain_factor = "16"; + framerate_factor = "1000000"; + exposure_factor = "1000000"; + min_gain_val = "16"; /* 1.00x */ + max_gain_val = "170"; /* 10.66x */ + step_gain_val = "1"; + default_gain = "16"; /* 1.00x */ + min_hdr_ratio = "1"; + max_hdr_ratio = "1"; + min_framerate = "2000000"; /* 2.0 fps */ + max_framerate = "21000000"; /* 21.0 fps */ + step_framerate = "1"; + default_framerate = "21000000"; /* 21.0 fps */ + min_exp_time = "13"; /* us */ + max_exp_time = "683709"; /* us */ + step_exp_time = "1"; + default_exp_time = "2495"; /* us */ + embedded_metadata_height = "2"; + }; + mode1 { /* IMX219_MODE_3280x1848_28FPS */ + mclk_khz = "24000"; + num_lanes = "2"; + tegra_sinterface = "serial_c"; + phy_mode = "DPHY"; + discontinuous_clk = "yes"; + dpcm_enable = "false"; + cil_settletime = "0"; + active_w = "3280"; + active_h = "1848"; + mode_type = "bayer"; + pixel_phase = "rggb"; + csi_pixel_bit_depth = "10"; + readout_orientation = "90"; + line_length = "3448"; + inherent_gain = "1"; + mclk_multiplier = "9.33"; + pix_clk_hz = "182400000"; + gain_factor = "16"; + framerate_factor = "1000000"; + exposure_factor = "1000000"; + min_gain_val = "16"; /* 1.00x */ + max_gain_val = "170"; /* 10.66x */ + step_gain_val = "1"; + default_gain = "16"; /* 1.00x */ + min_hdr_ratio = "1"; + max_hdr_ratio = "1"; + min_framerate = "2000000"; /* 2.0 fps */ + max_framerate = "28000000"; /* 28.0 fps */ + step_framerate = "1"; + default_framerate = "28000000"; /* 28.0 fps */ + min_exp_time = "13"; /* us */ + max_exp_time = "683709"; /* us */ + step_exp_time = "1"; + default_exp_time = "2495"; /* us */ + embedded_metadata_height = "2"; + }; + mode2 { /* IMX219_MODE_1920x1080_30FPS */ + mclk_khz = "24000"; + num_lanes = "2"; + tegra_sinterface = "serial_c"; + phy_mode = "DPHY"; + discontinuous_clk = "yes"; + dpcm_enable = "false"; + cil_settletime = "0"; + active_w = "1920"; + active_h = "1080"; + mode_type = "bayer"; + pixel_phase = "rggb"; + csi_pixel_bit_depth = "10"; + readout_orientation = "90"; + line_length = "3448"; + inherent_gain = "1"; + mclk_multiplier = "9.33"; + pix_clk_hz = "182400000"; + gain_factor = "16"; + framerate_factor = "1000000"; + exposure_factor = "1000000"; + min_gain_val = "16"; /* 1.00x */ + max_gain_val = "170"; /* 10.66x */ + step_gain_val = "1"; + default_gain = "16"; /* 1.00x */ + min_hdr_ratio = "1"; + max_hdr_ratio = "1"; + min_framerate = "2000000"; /* 2.0 fps */ + max_framerate = "30000000"; /* 30.0 fps */ + step_framerate = "1"; + default_framerate = "30000000"; /* 30.0 fps */ + min_exp_time = "13"; /* us */ + max_exp_time = "683709"; /* us */ + step_exp_time = "1"; + default_exp_time = "2495"; /* us */ + embedded_metadata_height = "2"; + }; + mode3 { /* IMX219_MODE_1640x1232_30FPS */ + mclk_khz = "24000"; + num_lanes = "2"; + tegra_sinterface = "serial_c"; + phy_mode = "DPHY"; + discontinuous_clk = "yes"; + dpcm_enable = "false"; + cil_settletime = "0"; + active_w = "1640"; + active_h = "1232"; + mode_type = "bayer"; + pixel_phase = "rggb"; + csi_pixel_bit_depth = "10"; + readout_orientation = "90"; + line_length = "3448"; + inherent_gain = "1"; + mclk_multiplier = "9.33"; + pix_clk_hz = "182400000"; + gain_factor = "16"; + framerate_factor = "1000000"; + exposure_factor = "1000000"; + min_gain_val = "16"; /* 1.00x */ + max_gain_val = "170"; /* 10.66x */ + step_gain_val = "1"; + default_gain = "16"; /* 1.00x */ + min_hdr_ratio = "1"; + max_hdr_ratio = "1"; + min_framerate = "2000000"; /* 2.0 fps */ + max_framerate = "30000000"; /* 60.0 fps */ + step_framerate = "1"; + default_framerate = "30000000"; /* 60.0 fps */ + min_exp_time = "13"; /* us */ + max_exp_time = "683709"; /* us */ + step_exp_time = "1"; + default_exp_time = "2495"; /* us */ + embedded_metadata_height = "2"; + }; + mode4 { /* IMX219_MODE_1280x720_60FPS */ + mclk_khz = "24000"; + num_lanes = "2"; + tegra_sinterface = "serial_c"; + phy_mode = "DPHY"; + discontinuous_clk = "yes"; + dpcm_enable = "false"; + cil_settletime = "0"; + active_w = "1280"; + active_h = "720"; + mode_type = "bayer"; + pixel_phase = "rggb"; + csi_pixel_bit_depth = "10"; + readout_orientation = "90"; + line_length = "3448"; + inherent_gain = "1"; + mclk_multiplier = "9.33"; + pix_clk_hz = "182400000"; + gain_factor = "16"; + framerate_factor = "1000000"; + exposure_factor = "1000000"; + min_gain_val = "16"; /* 1.00x */ + max_gain_val = "170"; /* 10.66x */ + step_gain_val = "1"; + default_gain = "16"; /* 1.00x */ + min_hdr_ratio = "1"; + max_hdr_ratio = "1"; + min_framerate = "2000000"; /* 2.0 fps */ + max_framerate = "60000000"; /* 60.0 fps */ + step_framerate = "1"; + default_framerate = "60000000"; /* 60.0 fps */ + min_exp_time = "13"; /* us */ + max_exp_time = "683709"; /* us */ + step_exp_time = "1"; + default_exp_time = "2495"; /* us */ + embedded_metadata_height = "2"; + }; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + rbpcv2_imx219_out1: endpoint { + port-index = <2>; + bus-width = <2>; + remote-endpoint = <&rbpcv2_imx219_csi_in1>; + }; + }; + }; + }; + }; + }; + lens_imx219@RBPCV2 { + min_focus_distance = "0.0"; + hyper_focal = "0.0"; + focal_length = "3.04"; + f_number = "2.0"; + aperture = "0.0"; + }; + }; + + tcp: tegra-camera-platform { + compatible = "nvidia, tegra-camera-platform"; + /** + * Physical settings to calculate max ISO BW + * + * num_csi_lanes = <>; + * Total number of CSI lanes when all cameras are active + * + * max_lane_speed = <>; + * Max lane speed in Kbit/s + * + * min_bits_per_pixel = <>; + * Min bits per pixel + * + * vi_peak_byte_per_pixel = <>; + * Max byte per pixel for the VI ISO case + * + * vi_bw_margin_pct = <>; + * Vi bandwidth margin in percentage + * + * max_pixel_rate = <>; + * Max pixel rate in Kpixel/s for the ISP ISO case + * + * isp_peak_byte_per_pixel = <>; + * Max byte per pixel for the ISP ISO case + * + * isp_bw_margin_pct = <>; + * Isp bandwidth margin in percentage + */ + num_csi_lanes = <4>; + max_lane_speed = <1500000>; + min_bits_per_pixel = <10>; + vi_peak_byte_per_pixel = <2>; + vi_bw_margin_pct = <25>; + max_pixel_rate = <240000>; + isp_peak_byte_per_pixel = <5>; + isp_bw_margin_pct = <25>; + /** + * The general guideline for naming badge_info contains 3 parts, and is as follows, + * The first part is the camera_board_id for the module; if the module is in a FFD + * platform, then use the platform name for this part. + * The second part contains the position of the module, ex. "rear" or "front". + * The third part contains the last 6 characters of a part number which is found + * in the module's specsheet from the vendor. + */ + modules { + cam_module0: module0 { + badge = "jakku_front_RBP194"; + position = "front"; + orientation = "1"; + cam_module0_drivernode0: drivernode0 { + pcl_id = "v4l2_sensor"; + sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/cam_i2cmux/i2c@0/rbpcv2_imx219_a@10"; + }; + cam_module0_drivernode1: drivernode1 { + pcl_id = "v4l2_lens"; + sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/lens_imx219@RBPCV2"; + }; + }; + cam_module1: module1 { + badge = "jakku_rear_RBP194"; + position = "rear"; + orientation = "1"; + cam_module1_drivernode0: drivernode0 { + pcl_id = "v4l2_sensor"; + sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/cam_i2cmux/i2c@1/rbpcv2_imx219_c@10"; + }; + cam_module1_drivernode1: drivernode1 { + pcl_id = "v4l2_lens"; + sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/lens_imx219@RBPCV2/"; + }; + }; + }; + }; + }; + }; +}; diff --git a/products/PAB_CAN/overlay/tegra234-p3767-camera-p3768-imx219-dual.dts b/products/PAB_CAN/overlay/tegra234-p3767-camera-p3768-imx219-dual.dts new file mode 100644 index 0000000..d107138 --- /dev/null +++ b/products/PAB_CAN/overlay/tegra234-p3767-camera-p3768-imx219-dual.dts @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. + +/dts-v1/; +/plugin/; + +#define CAM0_RST TEGRA234_MAIN_GPIO(H, 3) +#define CAM0_PWDN TEGRA234_MAIN_GPIO(H, 6) +#define CAM1_PWDN TEGRA234_MAIN_GPIO(AC, 0) +#define CAM_I2C_MUX TEGRA234_AON_GPIO(CC, 3) + +#include +#include "tegra234-camera-rbpcv2-imx219.dtsi" + +/ { + overlay-name = "Camera IMX219 Dual"; + jetson-header-name = "Jetson 22pin CSI Connector"; + compatible = JETSON_COMPATIBLE_P3768; + + fragment-camera-imx219@0 { + target-path = "/"; + __overlay__ { + bus@0 { + cam_i2cmux{ + status = "okay"; + compatible = "i2c-mux-gpio"; + #address-cells = <1>; + #size-cells = <0>; + i2c-parent = <&cam_i2c>; + mux-gpios = <&gpio_aon CAM_I2C_MUX GPIO_ACTIVE_HIGH>; + i2c@0 { + status = "okay"; + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + rbpcv2_imx219_a@10 { + reset-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>; + }; + }; + i2c@1 { + status = "okay"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + rbpcv2_imx219_c@10 { + reset-gpios = <&gpio CAM1_PWDN GPIO_ACTIVE_HIGH>; + }; + }; + }; + gpio@2200000 { + camera-control-output-low { + gpio-hog; + output-low; + gpios = ; + label = "cam0-rst"; + }; + }; + }; + }; + }; +}; diff --git a/products/PAB_CAN/overlay/tegra234-p3767-camera-p3768-imx477-dual.dts b/products/PAB_CAN/overlay/tegra234-p3767-camera-p3768-imx477-dual.dts new file mode 100644 index 0000000..e72f7eb --- /dev/null +++ b/products/PAB_CAN/overlay/tegra234-p3767-camera-p3768-imx477-dual.dts @@ -0,0 +1,492 @@ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. + +/dts-v1/; +/plugin/; + +#define CAM0_PWDN TEGRA234_MAIN_GPIO(H, 6) +#define CAM1_PWDN TEGRA234_MAIN_GPIO(AC, 0) +#define CAM_I2C_MUX TEGRA234_AON_GPIO(CC, 3) + +#include + +/ { + overlay-name = "Camera IMX477 Dual"; + jetson-header-name = "Jetson 22pin CSI Connector"; + compatible = JETSON_COMPATIBLE_P3768; + + fragment@0 { + target-path = "/"; + __overlay__ { + tegra-capture-vi { + num-channels = <2>; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + rbpcv3_imx477_vi_in0: endpoint { + port-index = <0>; + bus-width = <2>; + remote-endpoint = <&rbpcv3_imx477_csi_out0>; + }; + }; + port@1 { + reg = <1>; + rbpcv3_imx477_vi_in1: endpoint { + port-index = <2>; + bus-width = <2>; + remote-endpoint = <&rbpcv3_imx477_csi_out1>; + }; + }; + }; + }; + tegra-camera-platform { + compatible = "nvidia, tegra-camera-platform"; + /** + * Physical settings to calculate max ISO BW + * + * num_csi_lanes = <>; + * Total number of CSI lanes when all cameras are active + * + * max_lane_speed = <>; + * Max lane speed in Kbit/s + * + * min_bits_per_pixel = <>; + * Min bits per pixel + * + * vi_peak_byte_per_pixel = <>; + * Max byte per pixel for the VI ISO case + * + * vi_bw_margin_pct = <>; + * Vi bandwidth margin in percentage + * + * max_pixel_rate = <>; + * Max pixel rate in Kpixel/s for the ISP ISO case + * + * isp_peak_byte_per_pixel = <>; + * Max byte per pixel for the ISP ISO case + * + * isp_bw_margin_pct = <>; + * Isp bandwidth margin in percentage + */ + num_csi_lanes = <4>; + max_lane_speed = <1500000>; + min_bits_per_pixel = <10>; + vi_peak_byte_per_pixel = <2>; + vi_bw_margin_pct = <25>; + max_pixel_rate = <7500000>; + isp_peak_byte_per_pixel = <5>; + isp_bw_margin_pct = <25>; + /** + * The general guideline for naming badge_info contains 3 parts, and is as follows, + * The first part is the camera_board_id for the module; if the module is in a FFD + * platform, then use the platform name for this part. + * The second part contains the position of the module, ex. "rear" or "front". + * The third part contains the last 6 characters of a part number which is found + * in the module's specsheet from the vendor. + */ + modules { + module0 { + badge = "jakku_front_RBPCV3"; + position = "front"; + orientation = "1"; + drivernode0 { + pcl_id = "v4l2_sensor"; + sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/cam_i2cmux/i2c@0/rbpcv3_imx477_a@1a"; + }; + }; + module1 { + badge = "jakku_rear_RBPCV3"; + position = "rear"; + orientation = "1"; + drivernode0 { + pcl_id = "v4l2_sensor"; + sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/cam_i2cmux/i2c@1/rbpcv3_imx477_c@1a"; + }; + }; + }; + }; + bus@0 { + host1x@13e00000 { + nvcsi@15a00000 { + num-channels = <2>; + #address-cells = <1>; + #size-cells = <0>; + channel@0 { + reg = <0>; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + rbpcv3_imx477_csi_in0: endpoint@0 { + port-index = <0>; + bus-width = <2>; + remote-endpoint = <&rbpcv3_imx477_out0>; + }; + }; + port@1 { + reg = <1>; + rbpcv3_imx477_csi_out0: endpoint@1 { + remote-endpoint = <&rbpcv3_imx477_vi_in0>; + }; + }; + }; + }; + channel@1 { + reg = <1>; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + rbpcv3_imx477_csi_in1: endpoint@2 { + port-index = <2>; + bus-width = <2>; + remote-endpoint = <&rbpcv3_imx477_out1>; + }; + }; + port@1 { + reg = <1>; + rbpcv3_imx477_csi_out1: endpoint@3 { + remote-endpoint = <&rbpcv3_imx477_vi_in1>; + }; + }; + }; + }; + }; + }; + cam_i2cmux { + status = "okay"; + compatible = "i2c-mux-gpio"; + #address-cells = <1>; + #size-cells = <0>; + mux-gpios = <&gpio_aon CAM_I2C_MUX GPIO_ACTIVE_HIGH>; + i2c-parent = <&cam_i2c>; + i2c@0 { + status = "okay"; + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + rbpcv2_imx219_a@10 { + status = "disabled"; + }; + rbpcv3_imx477_a@1a { + reset-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>; + compatible = "ridgerun,imx477"; + /* I2C device address */ + reg = <0x1a>; + /* V4L2 device node location */ + devnode = "video0"; + /* Physical dimensions of sensor */ + physical_w = "3.680"; + physical_h = "2.760"; + sensor_model = "imx477"; + use_sensor_mode_id = "true"; + /** + * ==== Modes ==== + * A modeX node is required to support v4l2 driver + * implementation with NVIDIA camera software stack + * + * == Signal properties == + * + * phy_mode = ""; + * PHY mode used by the MIPI lanes for this device + * + * tegra_sinterface = ""; + * CSI Serial interface connected to tegra + * Incase of virtual HW devices, use virtual + * For SW emulated devices, use host + * + * pix_clk_hz = ""; + * Sensor pixel clock used for calculations like exposure and framerate + * + * readout_orientation = "0"; + * Based on camera module orientation. + * Only change readout_orientation if you specifically + * Program a different readout order for this mode + * + * lane_polarity + * Based on the camera connector pin. + * CSIx_D0 | CSIx_D1 | CSI(X+1)_D0 | CSI(X+1)CSIx_D1 + * LSB | BIT1 | BIT2 | MSB + * if there is a polarity swap on any lane, the bit corrsponding + * to the lane should be set + * e.g. polarity swap on CSIx_D0 only -> lane_polarity = "1"; 0001 + * e.g. polarity swap on CSIx_D1 and CSI(X+1)_D0 -> lane_polarity = "6"; 0110 + * + * == Image format Properties == + * + * active_w = ""; + * Pixel active region width + * + * active_h = ""; + * Pixel active region height + * + * pixel_t = ""; + * The sensor readout pixel pattern + * + * line_length = ""; + * Pixel line length (width) for sensor mode. + * + * == Source Control Settings == + * + * Gain factor used to convert fixed point integer to float + * Gain range [min_gain/gain_factor, max_gain/gain_factor] + * Gain step [step_gain/gain_factor is the smallest step that can be configured] + * Default gain [Default gain to be initialized for the control. + * use min_gain_val as default for optimal results] + * Framerate factor used to convert fixed point integer to float + * Framerate range [min_framerate/framerate_factor, max_framerate/framerate_factor] + * Framerate step [step_framerate/framerate_factor is the smallest step that can be configured] + * Default Framerate [Default framerate to be initialized for the control. + * use max_framerate to get required performance] + * Exposure factor used to convert fixed point integer to float + * For convenience use 1 sec = 1000000us as conversion factor + * Exposure range [min_exp_time/exposure_factor, max_exp_time/exposure_factor] + * Exposure step [step_exp_time/exposure_factor is the smallest step that can be configured] + * Default Exposure Time [Default exposure to be initialized for the control. + * Set default exposure based on the default_framerate for optimal exposure settings] + * + * gain_factor = ""; (integer factor used for floating to fixed point conversion) + * min_gain_val = ""; (ceil to integer) + * max_gain_val = ""; (ceil to integer) + * step_gain_val = ""; (ceil to integer) + * default_gain = ""; (ceil to integer) + * Gain limits for mode + * + * exposure_factor = ""; (integer factor used for floating to fixed point conversion) + * min_exp_time = ""; (ceil to integer) + * max_exp_time = ""; (ceil to integer) + * step_exp_time = ""; (ceil to integer) + * default_exp_time = ""; (ceil to integer) + * Exposure Time limits for mode (sec) + * + * framerate_factor = ""; (integer factor used for floating to fixed point conversion) + * min_framerate = ""; (ceil to integer) + * max_framerate = ""; (ceil to integer) + * step_framerate = ""; (ceil to integer) + * default_framerate = ""; (ceil to integer) + * Framerate limits for mode (fps) + * + * embedded_metadata_height = ""; + * Sensor embedded metadata height in units of rows. + * If sensor does not support embedded metadata value should be 0. + */ + mode0 { /* IMX477_MODE_3840x2160 */ + mclk_khz = "24000"; + num_lanes = "2"; + tegra_sinterface = "serial_a"; + phy_mode = "DPHY"; + discontinuous_clk = "no"; + dpcm_enable = "false"; + cil_settletime = "0"; + lane_polarity = "6"; + active_w = "3840"; + active_h = "2160"; + mode_type = "bayer"; + pixel_phase = "rggb"; + csi_pixel_bit_depth = "10"; + readout_orientation = "90"; + line_length = "11200"; + inherent_gain = "1"; + mclk_multiplier = "80"; + pix_clk_hz = "300000000"; + gain_factor = "16"; + framerate_factor = "1000000"; + exposure_factor = "1000000"; + min_gain_val = "16"; /* 1.00x */ + max_gain_val = "356"; /* 22x */ + step_gain_val = "1"; + default_gain = "16"; /* 1.00x */ + min_hdr_ratio = "1"; + max_hdr_ratio = "1"; + min_framerate = "2000000"; /* 2.0 fps */ + max_framerate = "30000000"; /* 30.0 fps */ + step_framerate = "1"; + default_framerate = "30000000"; /* 30.0 fps */ + min_exp_time = "13"; /* us */ + max_exp_time = "683709"; /* us */ + step_exp_time = "1"; + default_exp_time = "2495"; /* us */ + embedded_metadata_height = "2"; + }; + mode1 { /* IMX477_MODE_1920X1080 */ + mclk_khz = "24000"; + num_lanes = "2"; + tegra_sinterface = "serial_a"; + phy_mode = "DPHY"; + discontinuous_clk = "no"; + dpcm_enable = "false"; + cil_settletime = "0"; + lane_polarity = "6"; + active_w = "1920"; + active_h = "1080"; + mode_type = "bayer"; + pixel_phase = "rggb"; + csi_pixel_bit_depth = "10"; + readout_orientation = "90"; + line_length = "7000"; + inherent_gain = "1"; + mclk_multiplier = "80"; + pix_clk_hz = "300000000"; + gain_factor = "16"; + framerate_factor = "1000000"; + exposure_factor = "1000000"; + min_gain_val = "16"; /* 1.00x */ + max_gain_val = "356"; /* 22x */ + step_gain_val = "1"; + default_gain = "16"; /* 1.00x */ + min_hdr_ratio = "1"; + max_hdr_ratio = "1"; + min_framerate = "2000000"; /* 2.0 fps */ + max_framerate = "60000000"; /* 60.0 fps */ + step_framerate = "1"; + default_framerate = "60000000"; /* 60.0 fps */ + min_exp_time = "13"; /* us */ + max_exp_time = "683709"; /* us */ + step_exp_time = "1"; + default_exp_time = "2495"; /* us */ + embedded_metadata_height = "2"; + }; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + rbpcv3_imx477_out0: endpoint { + status = "okay"; + port-index = <0>; + bus-width = <2>; + remote-endpoint = <&rbpcv3_imx477_csi_in0>; + }; + }; + }; + }; + }; + i2c@1 { + status = "okay"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + rbpcv2_imx219_c@10 { + status = "disabled"; + }; + rbpcv3_imx477_c@1a { + reset-gpios = <&gpio CAM1_PWDN GPIO_ACTIVE_HIGH>; + compatible = "ridgerun,imx477"; + /* I2C device address */ + reg = <0x1a>; + /* V4L2 device node location */ + devnode = "video1"; + /* Physical dimensions of sensor */ + physical_w = "3.680"; + physical_h = "2.760"; + sensor_model = "imx477"; + use_sensor_mode_id = "true"; + mode0 { /* IMX477_MODE_3840x2160 */ + mclk_khz = "24000"; + num_lanes = "2"; + tegra_sinterface = "serial_c"; + phy_mode = "DPHY"; + discontinuous_clk = "no"; + dpcm_enable = "false"; + cil_settletime = "0"; + lane_polarity = "0"; + active_w = "3840"; + active_h = "2160"; + mode_type = "bayer"; + pixel_phase = "rggb"; + csi_pixel_bit_depth = "10"; + readout_orientation = "90"; + line_length = "11200"; + inherent_gain = "1"; + mclk_multiplier = "80"; + pix_clk_hz = "300000000"; + gain_factor = "16"; + framerate_factor = "1000000"; + exposure_factor = "1000000"; + min_gain_val = "16"; /* 1.00x */ + max_gain_val = "356"; /* 22x */ + step_gain_val = "1"; + default_gain = "16"; /* 1.00x */ + min_hdr_ratio = "1"; + max_hdr_ratio = "1"; + min_framerate = "2000000"; /* 2.0 fps */ + max_framerate = "30000000"; /* 30.0 fps */ + step_framerate = "1"; + default_framerate = "30000000"; /* 30.0 fps */ + min_exp_time = "13"; /* us */ + max_exp_time = "683709"; /* us */ + step_exp_time = "1"; + default_exp_time = "2495"; /* us */ + embedded_metadata_height = "2"; + }; + mode1 { /* IMX477_MODE_1920X1080 */ + mclk_khz = "24000"; + num_lanes = "2"; + tegra_sinterface = "serial_c"; + phy_mode = "DPHY"; + discontinuous_clk = "no"; + dpcm_enable = "false"; + cil_settletime = "0"; + lane_polarity = "0"; + active_w = "1920"; + active_h = "1080"; + mode_type = "bayer"; + pixel_phase = "rggb"; + csi_pixel_bit_depth = "10"; + readout_orientation = "90"; + line_length = "7000"; + inherent_gain = "1"; + mclk_multiplier = "80"; + pix_clk_hz = "300000000"; + gain_factor = "16"; + framerate_factor = "1000000"; + exposure_factor = "1000000"; + min_gain_val = "16"; /* 1.00x */ + max_gain_val = "356"; /* 22x */ + step_gain_val = "1"; + default_gain = "16"; /* 1.00x */ + min_hdr_ratio = "1"; + max_hdr_ratio = "1"; + min_framerate = "2000000"; /* 2.0 fps */ + max_framerate = "60000000"; /* 60.0 fps */ + step_framerate = "1"; + default_framerate = "60000000"; /* 60.0 fps */ + min_exp_time = "13"; /* us */ + max_exp_time = "683709"; /* us */ + step_exp_time = "1"; + default_exp_time = "2495"; /* us */ + embedded_metadata_height = "2"; + }; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + rbpcv3_imx477_out1: endpoint { + status = "okay"; + port-index = <2>; + bus-width = <2>; + remote-endpoint = <&rbpcv3_imx477_csi_in1>; + }; + }; + }; + }; + }; + }; + + gpio@6000d000 { + camera-control-output-low { + gpio-hog; + output-low; + gpios = ; + label = "cam1-pwdn", "cam0-pwdn"; + }; + }; + }; + }; + }; +}; diff --git a/products/PAB_CAN/overlay/tegra234-p3767-camera-p3768-imx708-dual.dts b/products/PAB_CAN/overlay/tegra234-p3767-camera-p3768-imx708-dual.dts new file mode 100644 index 0000000..025efdc --- /dev/null +++ b/products/PAB_CAN/overlay/tegra234-p3767-camera-p3768-imx708-dual.dts @@ -0,0 +1,295 @@ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +// SPDX-FileCopyrightText: Copyright (c) 2023, RidgeRun. All rights reserved. + +/dts-v1/; +/plugin/; + +#define CAM0_RST TEGRA234_MAIN_GPIO(H, 3) +#define CAM0_PWDN TEGRA234_MAIN_GPIO(H, 6) +#define CAM1_PWDN TEGRA234_MAIN_GPIO(AC, 0) +#define CAM_I2C_MUX TEGRA234_AON_GPIO(CC, 3) + +#include + +/ { + overlay-name = "Camera IMX708 Dual"; + jetson-header-name = "Jetson 22pin CSI Connector"; + compatible = JETSON_COMPATIBLE_P3768; + + fragment-camera@0 { + target-path = "/"; + __overlay__ { + tegra-capture-vi { + num-channels = <2>; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + imx708_vi_in0: endpoint { + port-index = <0>; + bus-width = <2>; + remote-endpoint = <&imx708_csi_out0>; + }; + }; + port@1 { + reg = <1>; + imx708_vi_in1: endpoint { + port-index = <2>; + bus-width = <2>; + remote-endpoint = <&imx708_csi_out1>; + }; + }; + }; + }; + tegra-camera-platform { + compatible = "nvidia, tegra-camera-platform"; + num_csi_lanes = <4>; + max_lane_speed = <2500000>; /* imx708 pixel clock is 297.6 MHz vs imx219's 182.4 MHz */ + min_bits_per_pixel = <10>; + vi_peak_byte_per_pixel = <2>; + vi_bw_margin_pct = <25>; + max_pixel_rate = <240000>; /* per-stream ~167 Mpix/s, same as imx219 */ + isp_peak_byte_per_pixel = <5>; + isp_bw_margin_pct = <25>; + modules { + module0 { + badge = "ark_imx708_front_IMX708"; + position = "front"; + orientation = "1"; + drivernode0 { + pcl_id = "v4l2_sensor"; + sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/cam_i2cmux/i2c@0/imx708_a@1a"; + }; + }; + module1 { + badge = "ark_imx708_rear_IMX708"; + position = "rear"; + orientation = "1"; + drivernode0 { + pcl_id = "v4l2_sensor"; + sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/cam_i2cmux/i2c@1/imx708_c@1a"; + }; + }; + }; + }; + bus@0 { + host1x@13e00000 { + nvcsi@15a00000 { + num-channels = <2>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + channel@0 { + reg = <0>; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + imx708_csi_in0: endpoint@0 { + port-index = <0>; + bus-width = <2>; + remote-endpoint = <&imx708_out0>; + }; + }; + port@1 { + reg = <1>; + imx708_csi_out0: endpoint@1 { + remote-endpoint = <&imx708_vi_in0>; + }; + }; + }; + }; + channel@1 { + reg = <1>; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + imx708_csi_in1: endpoint@2 { + port-index = <2>; + bus-width = <2>; + remote-endpoint = <&imx708_out1>; + }; + }; + port@1 { + reg = <1>; + imx708_csi_out1: endpoint@3 { + remote-endpoint = <&imx708_vi_in1>; + }; + }; + }; + }; + }; + }; + cam_i2cmux { + status = "okay"; + compatible = "i2c-mux-gpio"; + #address-cells = <1>; + #size-cells = <0>; + i2c-parent = <&cam_i2c>; + mux-gpios = <&gpio_aon CAM_I2C_MUX GPIO_ACTIVE_HIGH>; + i2c@0 { + status = "okay"; + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + /* Disable the baked-default IMX219 dual on the shared camera i2c-mux so only IMX708 is active. */ + rbpcv2_imx219_a@10 { + status = "disabled"; + }; + + imx708_a@1a { + status = "okay"; + reset-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>; + compatible = "sony,imx708"; + reg = <0x1a>; + devnode = "video0"; + physical_w = "6.45"; + physical_h = "3.63"; + sensor_model = "imx708"; + use_sensor_mode_id = "true"; + + mode0 { /* IMX708_MODE_4608x2592_14FPS */ + mclk_khz = "24000"; + num_lanes = "2"; + tegra_sinterface = "serial_a"; + lane_polarity = "6"; + phy_mode = "DPHY"; + discontinuous_clk = "yes"; + dpcm_enable = "false"; + cil_settletime = "0"; + active_w = "4608"; + active_h = "2592"; + mode_type = "bayer"; + pixel_phase = "rggb"; + csi_pixel_bit_depth = "10"; + readout_orientation = "90"; + line_length = "4808"; + inherent_gain = "1"; + pix_clk_hz = "297600000"; + gain_factor = "16"; + framerate_factor = "1000000"; + exposure_factor = "1000000"; + min_gain_val = "16"; + max_gain_val = "256"; + step_gain_val = "1"; + default_gain = "16"; + min_hdr_ratio = "1"; + max_hdr_ratio = "1"; + min_framerate = "2000000"; + max_framerate = "14000000"; + step_framerate = "1"; + default_framerate = "14000000"; + min_exp_time = "500"; + max_exp_time = "65487"; + step_exp_time = "1"; + default_exp_time = "1600"; + embedded_metadata_height = "4"; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + imx708_out0: endpoint { + status = "okay"; + port-index = <0>; + bus-width = <2>; + remote-endpoint = <&imx708_csi_in0>; + }; + }; + }; + }; + }; + i2c@1 { + status = "okay"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + rbpcv2_imx219_c@10 { + status = "disabled"; + }; + + imx708_c@1a { + status = "okay"; + reset-gpios = <&gpio CAM1_PWDN GPIO_ACTIVE_HIGH>; + compatible = "sony,imx708"; + reg = <0x1a>; + devnode = "video1"; + physical_w = "6.45"; + physical_h = "3.63"; + sensor_model = "imx708"; + use_sensor_mode_id = "true"; + + mode0 { /* IMX708_MODE_4608x2592_14FPS */ + mclk_khz = "24000"; + num_lanes = "2"; + tegra_sinterface = "serial_c"; + phy_mode = "DPHY"; + discontinuous_clk = "yes"; + dpcm_enable = "false"; + cil_settletime = "0"; + active_w = "4608"; + active_h = "2592"; + mode_type = "bayer"; + pixel_phase = "rggb"; + csi_pixel_bit_depth = "10"; + readout_orientation = "90"; + line_length = "4808"; + inherent_gain = "1"; + pix_clk_hz = "297600000"; + gain_factor = "16"; + framerate_factor = "1000000"; + exposure_factor = "1000000"; + min_gain_val = "16"; + max_gain_val = "256"; + step_gain_val = "1"; + default_gain = "16"; + min_hdr_ratio = "1"; + max_hdr_ratio = "1"; + min_framerate = "2000000"; + max_framerate = "14000000"; + step_framerate = "1"; + default_framerate = "14000000"; + min_exp_time = "500"; + max_exp_time = "65487"; + step_exp_time = "1"; + default_exp_time = "1600"; + embedded_metadata_height = "4"; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + imx708_out1: endpoint { + status = "okay"; + port-index = <2>; + bus-width = <2>; + remote-endpoint = <&imx708_csi_in1>; + }; + }; + }; + }; + }; + }; + gpio@2200000 { + camera-control-output-low { + gpio-hog; + output-low; + gpios = ; + label = "cam0-rst"; + }; + }; + }; + }; + }; +}; diff --git a/provision.sh b/provision.sh index c82f678..5b8591c 100755 --- a/provision.sh +++ b/provision.sh @@ -1,7 +1,7 @@ #!/bin/bash # # Rootfs provisioning — runs during staging when build.sh is given --provision. -# Env: ROOTFS_DIR (the staged rootfs), TARGET (PAB|JAJ|PAB_V3). +# Env: ROOTFS_DIR (the staged rootfs), TARGET (PAB|JAJ|PAB_V3|PAB_CAN). # # /proc, /sys, /dev are bind-mounted and DNS is set up; /run is not, so ARK-OS's # postinst sees no running systemd and defers its runtime steps to first boot. The diff --git a/scripts/device_tree/README.md b/scripts/device_tree/README.md index dc95e31..8c27eaa 100644 --- a/scripts/device_tree/README.md +++ b/scripts/device_tree/README.md @@ -2,7 +2,7 @@ Helpers for working on the per-product device-tree overlays (see [docs/device-tree.md](../../docs/device-tree.md) for the overlay model itself). -## `classify.sh [PAB|JAJ|PAB_V3|all]` +## `classify.sh [PAB|JAJ|PAB_V3|PAB_CAN|all]` Drift check: flags any file under `products//device_tree/source/` that is byte-identical to the pinned BSP. Such files are pointless copies that go stale silently — the thing the overlay refactor removed. Extracts the stock tree from the BSP tarball in `downloads/` (cached), and exits non-zero if a duplicate is found, so it can gate CI or a BSP bump. diff --git a/scripts/device_tree/classify.sh b/scripts/device_tree/classify.sh index 333ea5c..4fed1bc 100755 --- a/scripts/device_tree/classify.sh +++ b/scripts/device_tree/classify.sh @@ -5,7 +5,7 @@ # one BSP and revert everything the BSP later changes, which is exactly what the device-tree # overlay refactor removed. Run this after a BSP bump (or in CI) to catch re-introduced copies. # -# Usage: scripts/device_tree/classify.sh [PAB|JAJ|PAB_V3|all] (default: all) +# Usage: scripts/device_tree/classify.sh [PAB|JAJ|PAB_V3|PAB_CAN|all] (default: all) # Needs the BSP source tarball in downloads/ (run ./setup.sh first). Exits non-zero on a DUPLICATE. set -euo pipefail @@ -17,9 +17,9 @@ source "$REPO/versions.env" TARGET="${1:-all}" case "$TARGET" in - PAB|JAJ|PAB_V3) TARGETS=("$TARGET") ;; - all) TARGETS=(PAB JAJ PAB_V3) ;; - *) echo "usage: $0 [PAB|JAJ|PAB_V3|all]" >&2; exit 1 ;; + PAB|JAJ|PAB_V3|PAB_CAN) TARGETS=("$TARGET") ;; + all) TARGETS=(PAB JAJ PAB_V3 PAB_CAN) ;; + *) echo "usage: $0 [PAB|JAJ|PAB_V3|PAB_CAN|all]" >&2; exit 1 ;; esac PUB="$REPO/downloads/$PUBLIC_SOURCES_FILE" diff --git a/setup.sh b/setup.sh index 8823792..8e9210a 100755 --- a/setup.sh +++ b/setup.sh @@ -201,4 +201,4 @@ echo "" echo "Setup complete in $(date -d@${TOTAL_TIME} -u +%H:%M:%S)" echo "Downloads cached in: $DOWNLOADS_DIR" echo "" -echo "Next: ./build.sh (PAB | JAJ | PAB_V3 | all)" +echo "Next: ./build.sh (PAB | JAJ | PAB_V3 | PAB_CAN | all)"