From 2431d83809679e8f85ad6d31109a99c90a83137d Mon Sep 17 00:00:00 2001 From: Vladimir Umek Date: Mon, 2 Mar 2026 13:17:53 +0100 Subject: [PATCH] Board layers: make RAM separate load region for AC6 --- .../RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src | 3 +++ .../RTE/Device/SSE-315-FVP/ac6_linker_script.sct.src | 3 +++ .../RTE/Device/SSE-320-FVP/ac6_linker_script.sct.src | 3 +++ .../RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src | 3 +++ .../RTE/Device/SSE-315-FVP/ac6_linker_script.sct.src | 3 +++ .../RTE/Device/SSE-320-FVP/ac6_linker_script.sct.src | 3 +++ .../RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src | 3 +++ .../RTE/Device/SSE-315-FVP/ac6_linker_script.sct.src | 3 +++ .../RTE/Device/SSE-320-FVP/ac6_linker_script.sct.src | 3 +++ .../RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src | 3 +++ .../RTE/Device/SSE-315-FVP/ac6_linker_script.sct.src | 3 +++ .../RTE/Device/SSE-320-FVP/ac6_linker_script.sct.src | 3 +++ 12 files changed, 36 insertions(+) diff --git a/board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src b/board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src index 233a6de6..220ca387 100644 --- a/board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src +++ b/board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src @@ -48,6 +48,9 @@ LR_ROM1 __ROM1_BASE __ROM1_SIZE { ER_ROM1 __ROM1_BASE __ROM1_SIZE { *(+RO +XO) } +} + +LR_RAM0 __RAM0_BASE { RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) { *.o(.bss.noinit) diff --git a/board/Corstone-315/RTE/Device/SSE-315-FVP/ac6_linker_script.sct.src b/board/Corstone-315/RTE/Device/SSE-315-FVP/ac6_linker_script.sct.src index 233a6de6..220ca387 100644 --- a/board/Corstone-315/RTE/Device/SSE-315-FVP/ac6_linker_script.sct.src +++ b/board/Corstone-315/RTE/Device/SSE-315-FVP/ac6_linker_script.sct.src @@ -48,6 +48,9 @@ LR_ROM1 __ROM1_BASE __ROM1_SIZE { ER_ROM1 __ROM1_BASE __ROM1_SIZE { *(+RO +XO) } +} + +LR_RAM0 __RAM0_BASE { RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) { *.o(.bss.noinit) diff --git a/board/Corstone-320/RTE/Device/SSE-320-FVP/ac6_linker_script.sct.src b/board/Corstone-320/RTE/Device/SSE-320-FVP/ac6_linker_script.sct.src index 233a6de6..220ca387 100644 --- a/board/Corstone-320/RTE/Device/SSE-320-FVP/ac6_linker_script.sct.src +++ b/board/Corstone-320/RTE/Device/SSE-320-FVP/ac6_linker_script.sct.src @@ -48,6 +48,9 @@ LR_ROM1 __ROM1_BASE __ROM1_SIZE { ER_ROM1 __ROM1_BASE __ROM1_SIZE { *(+RO +XO) } +} + +LR_RAM0 __RAM0_BASE { RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) { *.o(.bss.noinit) diff --git a/example/FVP_Audio/board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src b/example/FVP_Audio/board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src index 233a6de6..220ca387 100644 --- a/example/FVP_Audio/board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src +++ b/example/FVP_Audio/board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src @@ -48,6 +48,9 @@ LR_ROM1 __ROM1_BASE __ROM1_SIZE { ER_ROM1 __ROM1_BASE __ROM1_SIZE { *(+RO +XO) } +} + +LR_RAM0 __RAM0_BASE { RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) { *.o(.bss.noinit) diff --git a/example/FVP_Audio/board/Corstone-315/RTE/Device/SSE-315-FVP/ac6_linker_script.sct.src b/example/FVP_Audio/board/Corstone-315/RTE/Device/SSE-315-FVP/ac6_linker_script.sct.src index 233a6de6..220ca387 100644 --- a/example/FVP_Audio/board/Corstone-315/RTE/Device/SSE-315-FVP/ac6_linker_script.sct.src +++ b/example/FVP_Audio/board/Corstone-315/RTE/Device/SSE-315-FVP/ac6_linker_script.sct.src @@ -48,6 +48,9 @@ LR_ROM1 __ROM1_BASE __ROM1_SIZE { ER_ROM1 __ROM1_BASE __ROM1_SIZE { *(+RO +XO) } +} + +LR_RAM0 __RAM0_BASE { RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) { *.o(.bss.noinit) diff --git a/example/FVP_Audio/board/Corstone-320/RTE/Device/SSE-320-FVP/ac6_linker_script.sct.src b/example/FVP_Audio/board/Corstone-320/RTE/Device/SSE-320-FVP/ac6_linker_script.sct.src index 233a6de6..220ca387 100644 --- a/example/FVP_Audio/board/Corstone-320/RTE/Device/SSE-320-FVP/ac6_linker_script.sct.src +++ b/example/FVP_Audio/board/Corstone-320/RTE/Device/SSE-320-FVP/ac6_linker_script.sct.src @@ -48,6 +48,9 @@ LR_ROM1 __ROM1_BASE __ROM1_SIZE { ER_ROM1 __ROM1_BASE __ROM1_SIZE { *(+RO +XO) } +} + +LR_RAM0 __RAM0_BASE { RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) { *.o(.bss.noinit) diff --git a/example/FVP_Hello/board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src b/example/FVP_Hello/board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src index 233a6de6..220ca387 100644 --- a/example/FVP_Hello/board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src +++ b/example/FVP_Hello/board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src @@ -48,6 +48,9 @@ LR_ROM1 __ROM1_BASE __ROM1_SIZE { ER_ROM1 __ROM1_BASE __ROM1_SIZE { *(+RO +XO) } +} + +LR_RAM0 __RAM0_BASE { RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) { *.o(.bss.noinit) diff --git a/example/FVP_Hello/board/Corstone-315/RTE/Device/SSE-315-FVP/ac6_linker_script.sct.src b/example/FVP_Hello/board/Corstone-315/RTE/Device/SSE-315-FVP/ac6_linker_script.sct.src index 233a6de6..220ca387 100644 --- a/example/FVP_Hello/board/Corstone-315/RTE/Device/SSE-315-FVP/ac6_linker_script.sct.src +++ b/example/FVP_Hello/board/Corstone-315/RTE/Device/SSE-315-FVP/ac6_linker_script.sct.src @@ -48,6 +48,9 @@ LR_ROM1 __ROM1_BASE __ROM1_SIZE { ER_ROM1 __ROM1_BASE __ROM1_SIZE { *(+RO +XO) } +} + +LR_RAM0 __RAM0_BASE { RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) { *.o(.bss.noinit) diff --git a/example/FVP_Hello/board/Corstone-320/RTE/Device/SSE-320-FVP/ac6_linker_script.sct.src b/example/FVP_Hello/board/Corstone-320/RTE/Device/SSE-320-FVP/ac6_linker_script.sct.src index 233a6de6..220ca387 100644 --- a/example/FVP_Hello/board/Corstone-320/RTE/Device/SSE-320-FVP/ac6_linker_script.sct.src +++ b/example/FVP_Hello/board/Corstone-320/RTE/Device/SSE-320-FVP/ac6_linker_script.sct.src @@ -48,6 +48,9 @@ LR_ROM1 __ROM1_BASE __ROM1_SIZE { ER_ROM1 __ROM1_BASE __ROM1_SIZE { *(+RO +XO) } +} + +LR_RAM0 __RAM0_BASE { RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) { *.o(.bss.noinit) diff --git a/example/FVP_Video/board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src b/example/FVP_Video/board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src index 233a6de6..220ca387 100644 --- a/example/FVP_Video/board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src +++ b/example/FVP_Video/board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src @@ -48,6 +48,9 @@ LR_ROM1 __ROM1_BASE __ROM1_SIZE { ER_ROM1 __ROM1_BASE __ROM1_SIZE { *(+RO +XO) } +} + +LR_RAM0 __RAM0_BASE { RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) { *.o(.bss.noinit) diff --git a/example/FVP_Video/board/Corstone-315/RTE/Device/SSE-315-FVP/ac6_linker_script.sct.src b/example/FVP_Video/board/Corstone-315/RTE/Device/SSE-315-FVP/ac6_linker_script.sct.src index 233a6de6..220ca387 100644 --- a/example/FVP_Video/board/Corstone-315/RTE/Device/SSE-315-FVP/ac6_linker_script.sct.src +++ b/example/FVP_Video/board/Corstone-315/RTE/Device/SSE-315-FVP/ac6_linker_script.sct.src @@ -48,6 +48,9 @@ LR_ROM1 __ROM1_BASE __ROM1_SIZE { ER_ROM1 __ROM1_BASE __ROM1_SIZE { *(+RO +XO) } +} + +LR_RAM0 __RAM0_BASE { RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) { *.o(.bss.noinit) diff --git a/example/FVP_Video/board/Corstone-320/RTE/Device/SSE-320-FVP/ac6_linker_script.sct.src b/example/FVP_Video/board/Corstone-320/RTE/Device/SSE-320-FVP/ac6_linker_script.sct.src index 233a6de6..220ca387 100644 --- a/example/FVP_Video/board/Corstone-320/RTE/Device/SSE-320-FVP/ac6_linker_script.sct.src +++ b/example/FVP_Video/board/Corstone-320/RTE/Device/SSE-320-FVP/ac6_linker_script.sct.src @@ -48,6 +48,9 @@ LR_ROM1 __ROM1_BASE __ROM1_SIZE { ER_ROM1 __ROM1_BASE __ROM1_SIZE { *(+RO +XO) } +} + +LR_RAM0 __RAM0_BASE { RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) { *.o(.bss.noinit)