From cf3150ff7139b5289c470221ba8560d498614e61 Mon Sep 17 00:00:00 2001 From: Albert Huang <58316522+AlbertHuang-CPU@users.noreply.github.com> Date: Wed, 21 Jul 2021 17:50:41 +0800 Subject: [PATCH] Update core_cm33.h Add SFSR and SFAR in SCB_Type. --- CMSIS/Core/Include/core_cm33.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/CMSIS/Core/Include/core_cm33.h b/CMSIS/Core/Include/core_cm33.h index f9cf6ab183..d72e0bff43 100644 --- a/CMSIS/Core/Include/core_cm33.h +++ b/CMSIS/Core/Include/core_cm33.h @@ -528,7 +528,10 @@ typedef struct __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ - uint32_t RESERVED3[92U]; + uint32_t RESERVED_ADD1[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ uint32_t RESERVED4[15U]; __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */