From e9bbf5a2749b0aa6b5f1842f4047b3d31be1c77a Mon Sep 17 00:00:00 2001 From: Ioannis Deligiannis Date: Mon, 25 Oct 2021 16:49:11 +0200 Subject: [PATCH 1/3] Fix: Infinite while-loop issue in SCB_DisableDCache(), SCB_InvalidateDCache(), SCB_CleanDCache() functions when compiling with -O0 --- CMSIS/Core/Include/cachel1_armv7.h | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/CMSIS/Core/Include/cachel1_armv7.h b/CMSIS/Core/Include/cachel1_armv7.h index abebc95f94..f0eeda87f8 100644 --- a/CMSIS/Core/Include/cachel1_armv7.h +++ b/CMSIS/Core/Include/cachel1_armv7.h @@ -181,9 +181,9 @@ __STATIC_FORCEINLINE void SCB_EnableDCache (void) __STATIC_FORCEINLINE void SCB_DisableDCache (void) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; + register uint32_t ccsidr; + register uint32_t sets; + register uint32_t ways; SCB->CSSELR = 0U; /* select Level 1 data cache */ __DSB(); @@ -219,9 +219,9 @@ __STATIC_FORCEINLINE void SCB_DisableDCache (void) __STATIC_FORCEINLINE void SCB_InvalidateDCache (void) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; + register uint32_t ccsidr; + register uint32_t sets; + register uint32_t ways; SCB->CSSELR = 0U; /* select Level 1 data cache */ __DSB(); @@ -254,9 +254,9 @@ __STATIC_FORCEINLINE void SCB_InvalidateDCache (void) __STATIC_FORCEINLINE void SCB_CleanDCache (void) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; + register uint32_t ccsidr; + register uint32_t sets; + register uint32_t ways; SCB->CSSELR = 0U; /* select Level 1 data cache */ __DSB(); @@ -289,9 +289,9 @@ __STATIC_FORCEINLINE void SCB_CleanDCache (void) __STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; + register uint32_t ccsidr; + register uint32_t sets; + register uint32_t ways; SCB->CSSELR = 0U; /* select Level 1 data cache */ __DSB(); From 0efc88ca01c49c3e2a520f00196e69f7f8a2b7e1 Mon Sep 17 00:00:00 2001 From: Ioannis Deligiannis Date: Mon, 25 Oct 2021 17:57:32 +0200 Subject: [PATCH 2/3] update fileheader date to '25. October 2021' --- CMSIS/Core/Include/cachel1_armv7.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CMSIS/Core/Include/cachel1_armv7.h b/CMSIS/Core/Include/cachel1_armv7.h index f0eeda87f8..c785803c6d 100644 --- a/CMSIS/Core/Include/cachel1_armv7.h +++ b/CMSIS/Core/Include/cachel1_armv7.h @@ -2,7 +2,7 @@ * @file cachel1_armv7.h * @brief CMSIS Level 1 Cache API for Armv7-M and later * @version V1.0.1 - * @date 19. April 2021 + * @date 25. October 2021 ******************************************************************************/ /* * Copyright (c) 2020-2021 Arm Limited. All rights reserved. From 66982bc51bb975be36cd8e9d9a70fd46abae3d59 Mon Sep 17 00:00:00 2001 From: Ioannis Deligiannis Date: Tue, 26 Oct 2021 09:35:43 +0200 Subject: [PATCH 3/3] update fileheader version --- CMSIS/Core/Include/cachel1_armv7.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/CMSIS/Core/Include/cachel1_armv7.h b/CMSIS/Core/Include/cachel1_armv7.h index c785803c6d..3c5059c0c1 100644 --- a/CMSIS/Core/Include/cachel1_armv7.h +++ b/CMSIS/Core/Include/cachel1_armv7.h @@ -1,8 +1,8 @@ /****************************************************************************** * @file cachel1_armv7.h * @brief CMSIS Level 1 Cache API for Armv7-M and later - * @version V1.0.1 - * @date 25. October 2021 + * @version V1.0.2 + * @date 26. October 2021 ******************************************************************************/ /* * Copyright (c) 2020-2021 Arm Limited. All rights reserved.