diff --git a/.github/workflows/corevalidation.yml b/.github/workflows/corevalidation.yml index c7bc55d1e..ebfddd13a 100644 --- a/.github/workflows/corevalidation.yml +++ b/.github/workflows/corevalidation.yml @@ -21,12 +21,16 @@ jobs: strategy: fail-fast: true matrix: - compiler: [AC6, GCC, Clang] + compiler: [AC6, GCC, Clang, Clang_TI] runs-on: ubuntu-22.04 env: ARM_UBL_ACTIVATION_CODE: ${{ secrets.ARM_UBL_ACTIVATION_CODE }} + CLANG_TI_VERSION: "5.1.0.LTS" + CLANG_TI_TC_SUFFIX: "5_1_0" + CLANG_TI_INSTALL_PATH: "/home/runner/" + CLANG_TI_SHA256: "c758668b78c080be5ec75393cdd09d077742fd1183aa0c181318a0119d58c4d0" steps: - run: | @@ -81,7 +85,33 @@ jobs: queries: security-and-quality - uses: ammaraskar/gcc-problem-matcher@master - if: matrix.compiler == 'Clang' || matrix.compiler == 'GCC' + if: matrix.compiler == 'Clang' || matrix.compiler == 'Clang_TI' || matrix.compiler == 'GCC' + + - name: Set TI Arm Clang Environment Variables and Path + if: matrix.compiler == 'Clang_TI' + run: | + echo "CLANG_TI_PATH=${{ env.CLANG_TI_INSTALL_PATH }}ti-cgt-armllvm_${{ env.CLANG_TI_VERSION }}" >> $GITHUB_ENV + echo "CLANG_TI_TOOLCHAIN_${{ env.CLANG_TI_TC_SUFFIX }}=${{ env.CLANG_TI_INSTALL_PATH }}ti-cgt-armllvm_${{ env.CLANG_TI_VERSION }}/bin" >> $GITHUB_ENV + + - name: Cache TI Arm Clang + if: matrix.compiler == 'Clang_TI' + id: cache-ti-arm-clang + uses: actions/cache@v5 + with: + path: ${{ env.CLANG_TI_PATH }} + key: ${{ runner.os }}-ti-arm-clang-${{ env.CLANG_TI_VERSION }} + + - name: Download and Verify TI Arm Clang Installer + if: matrix.compiler == 'Clang_TI' && steps.cache-ti-arm-clang.outputs.cache-hit != 'true' + working-directory: /home/runner + run: | + FILE="ti_cgt_armllvm_${{ env.CLANG_TI_VERSION }}_linux-x64_installer.bin" + URL="https://dr-download.ti.com/software-development/ide-configuration-compiler-or-debugger/MD-ayxs93eZNN/${{ env.CLANG_TI_VERSION }}/${FILE}" + + curl -L "$URL" -o "$FILE" + echo "${{ env.CLANG_TI_SHA256 }} $FILE" | sha256sum --check + chmod +x "$FILE" + ./"$FILE" --mode unattended --prefix "${{ env.CLANG_TI_INSTALL_PATH }}" - name: Build working-directory: ./CMSIS/CoreValidation/Project @@ -98,7 +128,7 @@ jobs: - name: Execute working-directory: ./CMSIS/CoreValidation/Project - run: | + run: | echo "Run test projects ..." ./build.py --verbose -c ${{ matrix.compiler }} -d "CM*" run || echo "::warning::==== Some configurations failed to run! ===" diff --git a/CMSIS/CoreValidation/Layer/App/Validation_Cortex-M/App.clayer.yml b/CMSIS/CoreValidation/Layer/App/Validation_Cortex-M/App.clayer.yml index b5604dc12..17144777e 100644 --- a/CMSIS/CoreValidation/Layer/App/Validation_Cortex-M/App.clayer.yml +++ b/CMSIS/CoreValidation/Layer/App/Validation_Cortex-M/App.clayer.yml @@ -11,6 +11,7 @@ layer: add-path: - ../../../Include - ../../../Source/Config + - ../../../Source/Clang_TI_Semihost misc: - for-compiler: AC6 @@ -69,3 +70,8 @@ layer: files: - file: ../../../Source/CV_Framework.c - file: ../../../Source/CV_Report.c + + - group: TI Arm Clang Compiler Semihost Support + for-compiler: CLANG_TI + files: + - file: ../../../Source/Clang_TI_Semihost/clang_ti_semihost.c \ No newline at end of file diff --git a/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/clang_ti_linker_script.cmd b/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/clang_ti_linker_script.cmd new file mode 100644 index 000000000..064b95107 --- /dev/null +++ b/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/clang_ti_linker_script.cmd @@ -0,0 +1,76 @@ +--stack_size=__STACK_SIZE +--heap_size=__HEAP_SIZE +--symbol_map=_start=_c_int00 +--entry_point=Reset_Handler +--retain="*(.vectors)" +--retain="*(.intvecs)" + +/* Macros for Stack/Seal */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define __STACKSEAL_SIZE 8 +#else + #define __STACKSEAL_SIZE 0 +#endif + +MEMORY +{ + ROM0 (RX) : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE + RAM0 (RW) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE +} + +SECTIONS +{ + /* 1. Vectors forced to the base of ROM */ + .intvecs : load = __ROM0_BASE + { + *(.vectors) + *(.intvecs) + } + + /* 2. Code and Read-Only Data */ + .text : {} > ROM0 + + /* 3. CMSE Veneers */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + Veneer$$CMSE : {} > ROM0 +#endif + + .rodata : {} > ROM0 + .TI.crctab : {} > ROM0 + + /* 4. Runtime Initialization Tables */ + .binit : {} > ROM0 + .cinit : {} > ROM0 + .pinit : {} > ROM0 + .init_array : {} > ROM0 + .fini_array : {} > ROM0 + .ovly : {} > ROM0 + + /* 5. Initialized Data */ + .data : load = ROM0, run = RAM0, table(BINIT) + + /* 6. Uninitialized Data */ + .bss : type = NOINIT {} > RAM0 + .sysmem : type = NOINIT {} > RAM0 + + /* 7. Stack & Security Seal */ + /* (HIGH) ensures these are placed at the end of RAM0 */ + GROUP : > RAM0 (HIGH) + { + .stack : type = NOINIT, palign = 8 + { + __stack_limit = .; + . += __STACK_SIZE; + __INITIAL_SP = .; /* CMSIS startup: initial SP loaded from vector table (8-byte aligned) */ + __stack = . - 1; /* TI CRT _c_int00 compatibility: CRT computes SP = __stack + 1 */ + } + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + .stackseal : type = NOINIT, palign = 8 + { + __stack_seal = .; + . += __STACKSEAL_SIZE; + } +#endif + } +} \ No newline at end of file diff --git a/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/tiac_arm.cmd b/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/tiac_arm.cmd deleted file mode 100644 index 391dda4f0..000000000 --- a/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/tiac_arm.cmd +++ /dev/null @@ -1,41 +0,0 @@ -/****************************************************************************/ -/* tiac_arm.cmd - COMMAND FILE FOR LINKING ARM C PROGRAMS */ -/* */ -/* Description: This file is a sample command file that can be used */ -/* for linking programs built with the TI Arm Clang */ -/* Compiler. Use it as a guideline; you may want to change */ -/* the allocation scheme according to the size of your */ -/* program and the memory layout of your target system. */ -/* */ -/****************************************************************************/ --c /* LINK USING C CONVENTIONS */ --stack 0x4000 /* SOFTWARE STACK SIZE */ --heap 0x4000 /* HEAP AREA SIZE */ ---args 0x1000 - -/* SPECIFY THE SYSTEM MEMORY MAP */ -MEMORY -{ - V_MEM : org = 0x00000000 len = 0x00001000 /* INT VECTOR */ - P_MEM : org = 0x00001000 len = 0x20000000 /* PROGRAM MEMORY (ROM) */ - D_MEM : org = 0x20001000 len = 0x20000000 /* DATA MEMORY (RAM) */ -} - -/* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */ -SECTIONS -{ - .intvecs : {} > 0x0 /* INTERRUPT VECTORS */ - .bss : {} > D_MEM /* GLOBAL & STATIC VARS */ - .data : {} > D_MEM - .sysmem : {} > D_MEM /* DYNAMIC MEMORY ALLOCATION AREA */ - .stack : {} > D_MEM /* SOFTWARE SYSTEM STACK */ - - .text : {} > P_MEM /* CODE */ - .cinit : {} > P_MEM /* INITIALIZATION TABLES */ - .const : {} > P_MEM /* CONSTANT DATA */ - .rodata : {} > P_MEM, palign(4) - .init_array : {} > P_MEM /* C++ CONSTRUCTOR TABLES */ - - - .TI.ramfunc : {} load=P_MEM, run=D_MEM, table(BINIT) -} diff --git a/CMSIS/CoreValidation/Layer/Target/CM0/Target.clayer.yml b/CMSIS/CoreValidation/Layer/Target/CM0/Target.clayer.yml index 8f926e457..b78933a17 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM0/Target.clayer.yml +++ b/CMSIS/CoreValidation/Layer/Target/CM0/Target.clayer.yml @@ -22,6 +22,9 @@ layer: - for-compiler: CLANG script: RTE/Device/$Dname$/clang_linker_script.ld regions: RTE/Device/$Dname$/regions_$Dname$.h + - for-compiler: CLANG_TI + script: RTE/Device/$Dname$/clang_ti_linker_script.cmd + regions: RTE/Device/$Dname$/regions_$Dname$.h - for-compiler: IAR script: RTE/Device/$Dname$/iar_linker_script.icf regions: RTE/Device/$Dname$/regions_$Dname$.h diff --git a/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/clang_ti_linker_script.cmd b/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/clang_ti_linker_script.cmd new file mode 100644 index 000000000..064b95107 --- /dev/null +++ b/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/clang_ti_linker_script.cmd @@ -0,0 +1,76 @@ +--stack_size=__STACK_SIZE +--heap_size=__HEAP_SIZE +--symbol_map=_start=_c_int00 +--entry_point=Reset_Handler +--retain="*(.vectors)" +--retain="*(.intvecs)" + +/* Macros for Stack/Seal */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define __STACKSEAL_SIZE 8 +#else + #define __STACKSEAL_SIZE 0 +#endif + +MEMORY +{ + ROM0 (RX) : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE + RAM0 (RW) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE +} + +SECTIONS +{ + /* 1. Vectors forced to the base of ROM */ + .intvecs : load = __ROM0_BASE + { + *(.vectors) + *(.intvecs) + } + + /* 2. Code and Read-Only Data */ + .text : {} > ROM0 + + /* 3. CMSE Veneers */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + Veneer$$CMSE : {} > ROM0 +#endif + + .rodata : {} > ROM0 + .TI.crctab : {} > ROM0 + + /* 4. Runtime Initialization Tables */ + .binit : {} > ROM0 + .cinit : {} > ROM0 + .pinit : {} > ROM0 + .init_array : {} > ROM0 + .fini_array : {} > ROM0 + .ovly : {} > ROM0 + + /* 5. Initialized Data */ + .data : load = ROM0, run = RAM0, table(BINIT) + + /* 6. Uninitialized Data */ + .bss : type = NOINIT {} > RAM0 + .sysmem : type = NOINIT {} > RAM0 + + /* 7. Stack & Security Seal */ + /* (HIGH) ensures these are placed at the end of RAM0 */ + GROUP : > RAM0 (HIGH) + { + .stack : type = NOINIT, palign = 8 + { + __stack_limit = .; + . += __STACK_SIZE; + __INITIAL_SP = .; /* CMSIS startup: initial SP loaded from vector table (8-byte aligned) */ + __stack = . - 1; /* TI CRT _c_int00 compatibility: CRT computes SP = __stack + 1 */ + } + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + .stackseal : type = NOINIT, palign = 8 + { + __stack_seal = .; + . += __STACKSEAL_SIZE; + } +#endif + } +} \ No newline at end of file diff --git a/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/tiac_arm.cmd b/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/tiac_arm.cmd deleted file mode 100644 index 391dda4f0..000000000 --- a/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/tiac_arm.cmd +++ /dev/null @@ -1,41 +0,0 @@ -/****************************************************************************/ -/* tiac_arm.cmd - COMMAND FILE FOR LINKING ARM C PROGRAMS */ -/* */ -/* Description: This file is a sample command file that can be used */ -/* for linking programs built with the TI Arm Clang */ -/* Compiler. Use it as a guideline; you may want to change */ -/* the allocation scheme according to the size of your */ -/* program and the memory layout of your target system. */ -/* */ -/****************************************************************************/ --c /* LINK USING C CONVENTIONS */ --stack 0x4000 /* SOFTWARE STACK SIZE */ --heap 0x4000 /* HEAP AREA SIZE */ ---args 0x1000 - -/* SPECIFY THE SYSTEM MEMORY MAP */ -MEMORY -{ - V_MEM : org = 0x00000000 len = 0x00001000 /* INT VECTOR */ - P_MEM : org = 0x00001000 len = 0x20000000 /* PROGRAM MEMORY (ROM) */ - D_MEM : org = 0x20001000 len = 0x20000000 /* DATA MEMORY (RAM) */ -} - -/* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */ -SECTIONS -{ - .intvecs : {} > 0x0 /* INTERRUPT VECTORS */ - .bss : {} > D_MEM /* GLOBAL & STATIC VARS */ - .data : {} > D_MEM - .sysmem : {} > D_MEM /* DYNAMIC MEMORY ALLOCATION AREA */ - .stack : {} > D_MEM /* SOFTWARE SYSTEM STACK */ - - .text : {} > P_MEM /* CODE */ - .cinit : {} > P_MEM /* INITIALIZATION TABLES */ - .const : {} > P_MEM /* CONSTANT DATA */ - .rodata : {} > P_MEM, palign(4) - .init_array : {} > P_MEM /* C++ CONSTRUCTOR TABLES */ - - - .TI.ramfunc : {} load=P_MEM, run=D_MEM, table(BINIT) -} diff --git a/CMSIS/CoreValidation/Layer/Target/CM0plus/Target.clayer.yml b/CMSIS/CoreValidation/Layer/Target/CM0plus/Target.clayer.yml index 8f7da0e94..29b021fb2 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM0plus/Target.clayer.yml +++ b/CMSIS/CoreValidation/Layer/Target/CM0plus/Target.clayer.yml @@ -22,6 +22,9 @@ layer: - for-compiler: CLANG script: RTE/Device/$Dname$/clang_linker_script.ld regions: RTE/Device/$Dname$/regions_$Dname$.h + - for-compiler: CLANG_TI + script: RTE/Device/$Dname$/clang_ti_linker_script.cmd + regions: RTE/Device/$Dname$/regions_$Dname$.h - for-compiler: IAR script: RTE/Device/$Dname$/iar_linker_script.icf regions: RTE/Device/$Dname$/regions_$Dname$.h diff --git a/CMSIS/CoreValidation/Layer/Target/CM23S/RTE/Device/ARMCM23/ARMCM23_ac6.sct b/CMSIS/CoreValidation/Layer/Target/CM23S/RTE/Device/ARMCM23/ARMCM23_ac6.sct deleted file mode 100644 index a0317e6c0..000000000 --- a/CMSIS/CoreValidation/Layer/Target/CM23S/RTE/Device/ARMCM23/ARMCM23_ac6.sct +++ /dev/null @@ -1,123 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc -; command above MUST be in first line (no comment above!) - -;Note: Add '-mcmse' to first line if your software model is "Secure Mode". -; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc -mcmse - - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/*--------------------- CMSE Veneer Configuration --------------------------- -; CMSE Veneer Configuration -; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> -; - *----------------------------------------------------------------------------*/ -#define __CMSEVENEER_SIZE 0x200 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - -/* ---------------------------------------------------------------------------- - Stack seal size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __STACKSEAL_SIZE ( 8 ) -#else -#define __STACKSEAL_SIZE ( 0 ) -#endif - - -/*---------------------------------------------------------------------------- - Region base & size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) -#define __CV_SIZE ( __CMSEVENEER_SIZE ) -#else -#define __CV_SIZE ( 0 ) -#endif - -#define __RO_BASE ( __ROM_BASE ) -#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) - -#define __RW_BASE ( __RAM_BASE ) -#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) - - -/*---------------------------------------------------------------------------- - Scatter Region definition - *----------------------------------------------------------------------------*/ -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_NOINIT __RW_BASE UNINIT __RW_SIZE { - *(.bss.noinit) - } - - RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { - *(+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack - } -#endif -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers - ER_CMSE_VENEER __CV_BASE __CV_SIZE { - *(Veneer$$CMSE) - } -} -#endif diff --git a/CMSIS/CoreValidation/Layer/Target/CM23S/RTE/Device/ARMCM23/ARMCM23_ac6.sct.base@1.1.0 b/CMSIS/CoreValidation/Layer/Target/CM23S/RTE/Device/ARMCM23/ARMCM23_ac6.sct.base@1.1.0 deleted file mode 100644 index a0317e6c0..000000000 --- a/CMSIS/CoreValidation/Layer/Target/CM23S/RTE/Device/ARMCM23/ARMCM23_ac6.sct.base@1.1.0 +++ /dev/null @@ -1,123 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc -; command above MUST be in first line (no comment above!) - -;Note: Add '-mcmse' to first line if your software model is "Secure Mode". -; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc -mcmse - - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/*--------------------- CMSE Veneer Configuration --------------------------- -; CMSE Veneer Configuration -; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> -; - *----------------------------------------------------------------------------*/ -#define __CMSEVENEER_SIZE 0x200 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - -/* ---------------------------------------------------------------------------- - Stack seal size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __STACKSEAL_SIZE ( 8 ) -#else -#define __STACKSEAL_SIZE ( 0 ) -#endif - - -/*---------------------------------------------------------------------------- - Region base & size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) -#define __CV_SIZE ( __CMSEVENEER_SIZE ) -#else -#define __CV_SIZE ( 0 ) -#endif - -#define __RO_BASE ( __ROM_BASE ) -#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) - -#define __RW_BASE ( __RAM_BASE ) -#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) - - -/*---------------------------------------------------------------------------- - Scatter Region definition - *----------------------------------------------------------------------------*/ -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_NOINIT __RW_BASE UNINIT __RW_SIZE { - *(.bss.noinit) - } - - RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { - *(+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack - } -#endif -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers - ER_CMSE_VENEER __CV_BASE __CV_SIZE { - *(Veneer$$CMSE) - } -} -#endif diff --git a/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/clang_ti_linker_script.cmd b/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/clang_ti_linker_script.cmd new file mode 100644 index 000000000..064b95107 --- /dev/null +++ b/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/clang_ti_linker_script.cmd @@ -0,0 +1,76 @@ +--stack_size=__STACK_SIZE +--heap_size=__HEAP_SIZE +--symbol_map=_start=_c_int00 +--entry_point=Reset_Handler +--retain="*(.vectors)" +--retain="*(.intvecs)" + +/* Macros for Stack/Seal */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define __STACKSEAL_SIZE 8 +#else + #define __STACKSEAL_SIZE 0 +#endif + +MEMORY +{ + ROM0 (RX) : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE + RAM0 (RW) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE +} + +SECTIONS +{ + /* 1. Vectors forced to the base of ROM */ + .intvecs : load = __ROM0_BASE + { + *(.vectors) + *(.intvecs) + } + + /* 2. Code and Read-Only Data */ + .text : {} > ROM0 + + /* 3. CMSE Veneers */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + Veneer$$CMSE : {} > ROM0 +#endif + + .rodata : {} > ROM0 + .TI.crctab : {} > ROM0 + + /* 4. Runtime Initialization Tables */ + .binit : {} > ROM0 + .cinit : {} > ROM0 + .pinit : {} > ROM0 + .init_array : {} > ROM0 + .fini_array : {} > ROM0 + .ovly : {} > ROM0 + + /* 5. Initialized Data */ + .data : load = ROM0, run = RAM0, table(BINIT) + + /* 6. Uninitialized Data */ + .bss : type = NOINIT {} > RAM0 + .sysmem : type = NOINIT {} > RAM0 + + /* 7. Stack & Security Seal */ + /* (HIGH) ensures these are placed at the end of RAM0 */ + GROUP : > RAM0 (HIGH) + { + .stack : type = NOINIT, palign = 8 + { + __stack_limit = .; + . += __STACK_SIZE; + __INITIAL_SP = .; /* CMSIS startup: initial SP loaded from vector table (8-byte aligned) */ + __stack = . - 1; /* TI CRT _c_int00 compatibility: CRT computes SP = __stack + 1 */ + } + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + .stackseal : type = NOINIT, palign = 8 + { + __stack_seal = .; + . += __STACKSEAL_SIZE; + } +#endif + } +} \ No newline at end of file diff --git a/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/tiac_arm.cmd b/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/tiac_arm.cmd deleted file mode 100644 index 391dda4f0..000000000 --- a/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/tiac_arm.cmd +++ /dev/null @@ -1,41 +0,0 @@ -/****************************************************************************/ -/* tiac_arm.cmd - COMMAND FILE FOR LINKING ARM C PROGRAMS */ -/* */ -/* Description: This file is a sample command file that can be used */ -/* for linking programs built with the TI Arm Clang */ -/* Compiler. Use it as a guideline; you may want to change */ -/* the allocation scheme according to the size of your */ -/* program and the memory layout of your target system. */ -/* */ -/****************************************************************************/ --c /* LINK USING C CONVENTIONS */ --stack 0x4000 /* SOFTWARE STACK SIZE */ --heap 0x4000 /* HEAP AREA SIZE */ ---args 0x1000 - -/* SPECIFY THE SYSTEM MEMORY MAP */ -MEMORY -{ - V_MEM : org = 0x00000000 len = 0x00001000 /* INT VECTOR */ - P_MEM : org = 0x00001000 len = 0x20000000 /* PROGRAM MEMORY (ROM) */ - D_MEM : org = 0x20001000 len = 0x20000000 /* DATA MEMORY (RAM) */ -} - -/* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */ -SECTIONS -{ - .intvecs : {} > 0x0 /* INTERRUPT VECTORS */ - .bss : {} > D_MEM /* GLOBAL & STATIC VARS */ - .data : {} > D_MEM - .sysmem : {} > D_MEM /* DYNAMIC MEMORY ALLOCATION AREA */ - .stack : {} > D_MEM /* SOFTWARE SYSTEM STACK */ - - .text : {} > P_MEM /* CODE */ - .cinit : {} > P_MEM /* INITIALIZATION TABLES */ - .const : {} > P_MEM /* CONSTANT DATA */ - .rodata : {} > P_MEM, palign(4) - .init_array : {} > P_MEM /* C++ CONSTRUCTOR TABLES */ - - - .TI.ramfunc : {} load=P_MEM, run=D_MEM, table(BINIT) -} diff --git a/CMSIS/CoreValidation/Layer/Target/CM3/Target.clayer.yml b/CMSIS/CoreValidation/Layer/Target/CM3/Target.clayer.yml index 2d95c5dd8..13e354763 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM3/Target.clayer.yml +++ b/CMSIS/CoreValidation/Layer/Target/CM3/Target.clayer.yml @@ -22,6 +22,9 @@ layer: - for-compiler: CLANG script: RTE/Device/$Dname$/clang_linker_script.ld regions: RTE/Device/$Dname$/regions_$Dname$.h + - for-compiler: CLANG_TI + script: RTE/Device/$Dname$/clang_ti_linker_script.cmd + regions: RTE/Device/$Dname$/regions_$Dname$.h - for-compiler: IAR script: RTE/Device/$Dname$/iar_linker_script.icf regions: RTE/Device/$Dname$/regions_$Dname$.h diff --git a/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33/clang_ti_linker_script.cmd b/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33/clang_ti_linker_script.cmd new file mode 100644 index 000000000..86fb57e67 --- /dev/null +++ b/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33/clang_ti_linker_script.cmd @@ -0,0 +1,76 @@ +--stack_size=__STACK_SIZE +--heap_size=__HEAP_SIZE +--symbol_map=_start=_c_int00 +--entry_point=Reset_Handler +--retain="*(.vectors)" +--retain="*(.intvecs)" + +/* Macros for Stack/Seal */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define __STACKSEAL_SIZE 8 +#else + #define __STACKSEAL_SIZE 0 +#endif + +MEMORY +{ + ROM0 (RX) : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE + RAM0 (RW) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE +} + +SECTIONS +{ + /* 1. Vectors forced to the base of ROM */ + .intvecs : load = __ROM0_BASE + { + *(.vectors) + *(.intvecs) + } + + /* 2. Code and Read-Only Data */ + .text : {} > ROM0 + + /* 3. CMSE Veneers */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + Veneer$$CMSE : {} > ROM0 +#endif + + .rodata : {} > ROM0 + .TI.crctab : {} > ROM0 + + /* 4. Runtime Initialization Tables */ + .binit : {} > ROM0 + .cinit : {} > ROM0 + .pinit : {} > ROM0 + .init_array : {} > ROM0 + .fini_array : {} > ROM0 + .ovly : {} > ROM0 + + /* 5. Initialized Data */ + .data : load = ROM0, run = RAM0, table(BINIT) + + /* 6. Uninitialized Data */ + .bss : type = NOINIT {} > RAM0 + .sysmem : type = NOINIT {} > RAM0 + + /* 7. Stack & Security Seal */ + /* (HIGH) ensures these are placed at the end of RAM0 */ + GROUP : > RAM0 (HIGH) + { + .stack : type = NOINIT, palign = 8 + { + __stack_limit = .; + . += __STACK_SIZE; + __INITIAL_SP = .; /* CMSIS startup: initial SP loaded from vector table (8-byte aligned) */ + __stack = . - 1; /* TI CRT _c_int00 compatibility: CRT computes SP = __stack + 1 */ + } + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + .stackseal : type = NOINIT, palign = 8 + { + __stack_seal = .; + . += __STACKSEAL_SIZE; + } +#endif + } +} \ No newline at end of file diff --git a/CMSIS/CoreValidation/Layer/Target/CM33/Target.clayer.yml b/CMSIS/CoreValidation/Layer/Target/CM33/Target.clayer.yml index f5c93b813..534e754e5 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM33/Target.clayer.yml +++ b/CMSIS/CoreValidation/Layer/Target/CM33/Target.clayer.yml @@ -25,6 +25,9 @@ layer: - for-compiler: CLANG script: RTE/Device/$Dname$/clang_linker_script.ld regions: RTE/Device/$Dname$/regions_$Dname$.h + - for-compiler: CLANG_TI + script: RTE/Device/$Dname$/clang_ti_linker_script.cmd + regions: RTE/Device/$Dname$/regions_$Dname$.h - for-compiler: IAR script: RTE/Device/$Dname$/iar_linker_script.icf regions: RTE/Device/$Dname$/regions_$Dname$.h diff --git a/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33/clang_ti_linker_script.cmd b/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33/clang_ti_linker_script.cmd new file mode 100644 index 000000000..064b95107 --- /dev/null +++ b/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33/clang_ti_linker_script.cmd @@ -0,0 +1,76 @@ +--stack_size=__STACK_SIZE +--heap_size=__HEAP_SIZE +--symbol_map=_start=_c_int00 +--entry_point=Reset_Handler +--retain="*(.vectors)" +--retain="*(.intvecs)" + +/* Macros for Stack/Seal */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define __STACKSEAL_SIZE 8 +#else + #define __STACKSEAL_SIZE 0 +#endif + +MEMORY +{ + ROM0 (RX) : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE + RAM0 (RW) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE +} + +SECTIONS +{ + /* 1. Vectors forced to the base of ROM */ + .intvecs : load = __ROM0_BASE + { + *(.vectors) + *(.intvecs) + } + + /* 2. Code and Read-Only Data */ + .text : {} > ROM0 + + /* 3. CMSE Veneers */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + Veneer$$CMSE : {} > ROM0 +#endif + + .rodata : {} > ROM0 + .TI.crctab : {} > ROM0 + + /* 4. Runtime Initialization Tables */ + .binit : {} > ROM0 + .cinit : {} > ROM0 + .pinit : {} > ROM0 + .init_array : {} > ROM0 + .fini_array : {} > ROM0 + .ovly : {} > ROM0 + + /* 5. Initialized Data */ + .data : load = ROM0, run = RAM0, table(BINIT) + + /* 6. Uninitialized Data */ + .bss : type = NOINIT {} > RAM0 + .sysmem : type = NOINIT {} > RAM0 + + /* 7. Stack & Security Seal */ + /* (HIGH) ensures these are placed at the end of RAM0 */ + GROUP : > RAM0 (HIGH) + { + .stack : type = NOINIT, palign = 8 + { + __stack_limit = .; + . += __STACK_SIZE; + __INITIAL_SP = .; /* CMSIS startup: initial SP loaded from vector table (8-byte aligned) */ + __stack = . - 1; /* TI CRT _c_int00 compatibility: CRT computes SP = __stack + 1 */ + } + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + .stackseal : type = NOINIT, palign = 8 + { + __stack_seal = .; + . += __STACKSEAL_SIZE; + } +#endif + } +} \ No newline at end of file diff --git a/CMSIS/CoreValidation/Layer/Target/CM33NS/Target.clayer.yml b/CMSIS/CoreValidation/Layer/Target/CM33NS/Target.clayer.yml index 51693352e..aabbe744c 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM33NS/Target.clayer.yml +++ b/CMSIS/CoreValidation/Layer/Target/CM33NS/Target.clayer.yml @@ -25,6 +25,9 @@ layer: - for-compiler: CLANG script: RTE/Device/$Dname$/clang_linker_script.ld regions: RTE/Device/$Dname$/regions_$Dname$.h + - for-compiler: CLANG_TI + script: RTE/Device/$Dname$/clang_ti_linker_script.cmd + regions: RTE/Device/$Dname$/regions_$Dname$.h - for-compiler: IAR script: RTE/Device/$Dname$/iar_linker_script.icf regions: RTE/Device/$Dname$/regions_$Dname$.h diff --git a/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33/clang_ti_linker_script.cmd b/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33/clang_ti_linker_script.cmd new file mode 100644 index 000000000..064b95107 --- /dev/null +++ b/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33/clang_ti_linker_script.cmd @@ -0,0 +1,76 @@ +--stack_size=__STACK_SIZE +--heap_size=__HEAP_SIZE +--symbol_map=_start=_c_int00 +--entry_point=Reset_Handler +--retain="*(.vectors)" +--retain="*(.intvecs)" + +/* Macros for Stack/Seal */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define __STACKSEAL_SIZE 8 +#else + #define __STACKSEAL_SIZE 0 +#endif + +MEMORY +{ + ROM0 (RX) : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE + RAM0 (RW) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE +} + +SECTIONS +{ + /* 1. Vectors forced to the base of ROM */ + .intvecs : load = __ROM0_BASE + { + *(.vectors) + *(.intvecs) + } + + /* 2. Code and Read-Only Data */ + .text : {} > ROM0 + + /* 3. CMSE Veneers */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + Veneer$$CMSE : {} > ROM0 +#endif + + .rodata : {} > ROM0 + .TI.crctab : {} > ROM0 + + /* 4. Runtime Initialization Tables */ + .binit : {} > ROM0 + .cinit : {} > ROM0 + .pinit : {} > ROM0 + .init_array : {} > ROM0 + .fini_array : {} > ROM0 + .ovly : {} > ROM0 + + /* 5. Initialized Data */ + .data : load = ROM0, run = RAM0, table(BINIT) + + /* 6. Uninitialized Data */ + .bss : type = NOINIT {} > RAM0 + .sysmem : type = NOINIT {} > RAM0 + + /* 7. Stack & Security Seal */ + /* (HIGH) ensures these are placed at the end of RAM0 */ + GROUP : > RAM0 (HIGH) + { + .stack : type = NOINIT, palign = 8 + { + __stack_limit = .; + . += __STACK_SIZE; + __INITIAL_SP = .; /* CMSIS startup: initial SP loaded from vector table (8-byte aligned) */ + __stack = . - 1; /* TI CRT _c_int00 compatibility: CRT computes SP = __stack + 1 */ + } + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + .stackseal : type = NOINIT, palign = 8 + { + __stack_seal = .; + . += __STACKSEAL_SIZE; + } +#endif + } +} \ No newline at end of file diff --git a/CMSIS/CoreValidation/Layer/Target/CM33S/Target.clayer.yml b/CMSIS/CoreValidation/Layer/Target/CM33S/Target.clayer.yml index a513f15aa..0369e70bf 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM33S/Target.clayer.yml +++ b/CMSIS/CoreValidation/Layer/Target/CM33S/Target.clayer.yml @@ -25,6 +25,9 @@ layer: - for-compiler: CLANG script: RTE/Device/$Dname$/clang_linker_script.ld regions: RTE/Device/$Dname$/regions_$Dname$.h + - for-compiler: CLANG_TI + script: RTE/Device/$Dname$/clang_ti_linker_script.cmd + regions: RTE/Device/$Dname$/regions_$Dname$.h - for-compiler: IAR script: RTE/Device/$Dname$/iar_linker_script.icf regions: RTE/Device/$Dname$/regions_$Dname$.h diff --git a/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/clang_ti_linker_script.cmd b/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/clang_ti_linker_script.cmd new file mode 100644 index 000000000..3bc7c4949 --- /dev/null +++ b/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/clang_ti_linker_script.cmd @@ -0,0 +1,76 @@ +--stack_size=__STACK_SIZE +--heap_size=__HEAP_SIZE +--symbol_map=_start=_c_int00 +--entry_point=Reset_Handler +--retain="*(.vectors)" +--retain="*(.intvecs)" + +/* Macros for Stack/Seal */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define __STACKSEAL_SIZE 8 +#else + #define __STACKSEAL_SIZE 0 +#endif + +MEMORY +{ + ROM0 (RX) : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE + RAM0 (RW) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE +} + +SECTIONS +{ + /* 1. Vectors forced to the base of ROM */ + .intvecs : load = __ROM0_BASE + { + *(.vectors) + *(.intvecs) + } + + /* 2. Code and Read-Only Data */ + .text : {} > ROM0 + + /* 3. CMSE Veneers */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + Veneer$$CMSE : {} > ROM0 +#endif + + .rodata : {} > ROM0 + .TI.crctab : {} > ROM0 + + /* 4. Runtime Initialization Tables */ + .binit : {} > ROM0 + .cinit : {} > ROM0 + .pinit : {} > ROM0 + .init_array : {} > ROM0 + .fini_array : {} > ROM0 + .ovly : {} > ROM0 + + /* 5. Initialized Data */ + .data : load = ROM0, run = RAM0, table(BINIT) + + /* 6. Uninitialized Data */ + .bss : type = NOINIT {} > RAM0 + .sysmem : type = NOINIT {} > RAM0 + + /* 7. Stack & Security Seal */ + /* (HIGH) ensures these are placed at the end of RAM0 */ + GROUP : > RAM0 (HIGH) + { + .stack : type = NOINIT, palign = 8 + { + __stack_limit = .; + . += __STACK_SIZE; + __INITIAL_SP = .; /* CMSIS startup: initial SP loaded from vector table (8-byte aligned) */ + __stack = . - 1; /* TI CRT _c_int00 compatibility: CRT computes SP = __stack + 1 */ + } + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + .stackseal : type = NOINIT, palign = 8 + { + __stack_seal = .; + . += __STACKSEAL_SIZE; + } +#endif + } +} \ No newline at end of file diff --git a/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/tiac_arm.cmd b/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/tiac_arm.cmd deleted file mode 100644 index 391dda4f0..000000000 --- a/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/tiac_arm.cmd +++ /dev/null @@ -1,41 +0,0 @@ -/****************************************************************************/ -/* tiac_arm.cmd - COMMAND FILE FOR LINKING ARM C PROGRAMS */ -/* */ -/* Description: This file is a sample command file that can be used */ -/* for linking programs built with the TI Arm Clang */ -/* Compiler. Use it as a guideline; you may want to change */ -/* the allocation scheme according to the size of your */ -/* program and the memory layout of your target system. */ -/* */ -/****************************************************************************/ --c /* LINK USING C CONVENTIONS */ --stack 0x4000 /* SOFTWARE STACK SIZE */ --heap 0x4000 /* HEAP AREA SIZE */ ---args 0x1000 - -/* SPECIFY THE SYSTEM MEMORY MAP */ -MEMORY -{ - V_MEM : org = 0x00000000 len = 0x00001000 /* INT VECTOR */ - P_MEM : org = 0x00001000 len = 0x20000000 /* PROGRAM MEMORY (ROM) */ - D_MEM : org = 0x20001000 len = 0x20000000 /* DATA MEMORY (RAM) */ -} - -/* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */ -SECTIONS -{ - .intvecs : {} > 0x0 /* INTERRUPT VECTORS */ - .bss : {} > D_MEM /* GLOBAL & STATIC VARS */ - .data : {} > D_MEM - .sysmem : {} > D_MEM /* DYNAMIC MEMORY ALLOCATION AREA */ - .stack : {} > D_MEM /* SOFTWARE SYSTEM STACK */ - - .text : {} > P_MEM /* CODE */ - .cinit : {} > P_MEM /* INITIALIZATION TABLES */ - .const : {} > P_MEM /* CONSTANT DATA */ - .rodata : {} > P_MEM, palign(4) - .init_array : {} > P_MEM /* C++ CONSTRUCTOR TABLES */ - - - .TI.ramfunc : {} load=P_MEM, run=D_MEM, table(BINIT) -} diff --git a/CMSIS/CoreValidation/Layer/Target/CM4/Target.clayer.yml b/CMSIS/CoreValidation/Layer/Target/CM4/Target.clayer.yml index def139200..0ba37a8e6 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM4/Target.clayer.yml +++ b/CMSIS/CoreValidation/Layer/Target/CM4/Target.clayer.yml @@ -22,6 +22,9 @@ layer: - for-compiler: CLANG script: RTE/Device/$Dname$/clang_linker_script.ld regions: RTE/Device/$Dname$/regions_$Dname$.h + - for-compiler: CLANG_TI + script: RTE/Device/$Dname$/clang_ti_linker_script.cmd + regions: RTE/Device/$Dname$/regions_$Dname$.h - for-compiler: IAR script: RTE/Device/$Dname$/iar_linker_script.icf regions: RTE/Device/$Dname$/regions_$Dname$.h diff --git a/CMSIS/CoreValidation/Project/build.py b/CMSIS/CoreValidation/Project/build.py index 41f654839..3ed71e8a7 100755 --- a/CMSIS/CoreValidation/Project/build.py +++ b/CMSIS/CoreValidation/Project/build.py @@ -41,11 +41,25 @@ class DeviceAxis(Enum): CM85S = ('Cortex-M85S', 'CM85S') CM85NS = ('Cortex-M85NS', 'CM85NS') CA5 = ('Cortex-A5', 'CA5') + CA5NEON = ('Cortex-A5neon', 'CA5neon') CA7 = ('Cortex-A7', 'CA7') + CA7NEON = ('Cortex-A7neon', 'CA7neon') CA9 = ('Cortex-A9', 'CA9') -# CA5NEON = ('Cortex-A5neon', 'CA5neon') -# CA7NEON = ('Cortex-A7neon', 'CA7neon') -# CA9NEON = ('Cortex-A9neon', 'CA9neon') + CA9NEON = ('Cortex-A9neon', 'CA9neon') + CA35 = ('Cortex-A35', 'CA35') + CA35NEON = ('Cortex-A35neon', 'CA35neon') + CA53 = ('Cortex-A53', 'CA53') + CA53NEON = ('Cortex-A53neon', 'CA53neon') + CA55 = ('Cortex-A55', 'CA55') + CA55NEON = ('Cortex-A55neon', 'CA55neon') + CA57 = ('Cortex-A57', 'CA57') + CA57NEON = ('Cortex-A57neon', 'CA57neon') + CR4 = ('Cortex-R4', 'CR4') + CR5 = ('Cortex-R5', 'CR5') + CR7 = ('Cortex-R7', 'CR7') + CR8 = ('Cortex-R8', 'CR8') + CR52 = ('Cortex-R52', 'CR52') + CR52NEON = ('Cortex-R52neon', 'CR52neon') def has_bl(self): return self in [ @@ -76,6 +90,7 @@ class CompilerAxis(Enum): GCC = ('GCC') IAR = ('IAR') CLANG = ('Clang') + CLANG_TI = ('Clang_TI') @property def image_ext(self): @@ -84,6 +99,7 @@ def image_ext(self): CompilerAxis.GCC: 'elf', CompilerAxis.IAR: 'elf', CompilerAxis.CLANG: 'elf', + CompilerAxis.CLANG_TI: 'elf', } return ext[self] @@ -93,7 +109,8 @@ def toolchain(self): CompilerAxis.AC6: 'AC6', CompilerAxis.GCC: 'GCC', CompilerAxis.IAR: 'IAR', - CompilerAxis.CLANG: 'CLANG' + CompilerAxis.CLANG: 'CLANG', + CompilerAxis.CLANG_TI: 'CLANG_TI', } return ext[self] @@ -131,11 +148,25 @@ class OptimizationAxis(Enum): DeviceAxis.CM85S: ("FVP_MPS2_Cortex-M85", []), DeviceAxis.CM85NS: ("FVP_MPS2_Cortex-M85", []), DeviceAxis.CA5: ("FVP_VE_Cortex-A5x1", []), + DeviceAxis.CA5NEON: ("FVP_VE_Cortex-A5x1", []), DeviceAxis.CA7: ("FVP_VE_Cortex-A7x1", []), + DeviceAxis.CA7NEON: ("FVP_VE_Cortex-A7x1", []), DeviceAxis.CA9: ("FVP_VE_Cortex-A9x1", []), -# DeviceAxis.CA5NEON: ("_VE_Cortex-A5x1", []), -# DeviceAxis.CA7NEON: ("_VE_Cortex-A7x1", []), -# DeviceAxis.CA9NEON: ("_VE_Cortex-A9x1", []) + DeviceAxis.CA9NEON: ("FVP_VE_Cortex-A9x1", []), + DeviceAxis.CA35: ("FVP_Base_Cortex-A35", []), + DeviceAxis.CA35NEON: ("FVP_Base_Cortex-A35", []), + DeviceAxis.CA53: ("FVP_Base_Cortex-A53", []), + DeviceAxis.CA53NEON: ("FVP_Base_Cortex-A53", []), + DeviceAxis.CA55: ("FVP_Base_Cortex-A55", []), + DeviceAxis.CA55NEON: ("FVP_Base_Cortex-A55", []), + DeviceAxis.CA57: ("FVP_Base_Cortex-A57", []), + DeviceAxis.CA57NEON: ("FVP_Base_Cortex-A57", []), + DeviceAxis.CR4: ("FVP_VE_Cortex-R4", []), + DeviceAxis.CR5: ("FVP_VE_Cortex-R5x1", []), + DeviceAxis.CR7: ("FVP_VE_Cortex-R7x1", []), + DeviceAxis.CR8: ("FVP_VE_Cortex-R8x1", []), + DeviceAxis.CR52: ("FVP_BaseR_Cortex-R52", []), + DeviceAxis.CR52NEON: ("FVP_BaseR_Cortex-R52", []), } QEMU_MACHINE = { @@ -264,7 +295,7 @@ def cbuild(config): f"{result.command.config.device}." f"{title}")) def model_exec(config): - cmdline = [MODEL_EXECUTABLE[config.device][0], "-q", "--simlimit", 100, "-f", model_config(config)] + cmdline = [MODEL_EXECUTABLE[config.device][0], "-q", "--simlimit", 5, "-f", model_config(config)] cmdline += MODEL_EXECUTABLE[config.device][1] cmdline += ["-a", f"{build_dir(config)}/{output_dir(config)}/Validation.{config.compiler.image_ext}"] if config.device.has_bl(): @@ -298,5 +329,44 @@ def filter_gcc_cm52(config): return device and compiler +@matrix_filter +def filter_clang_ti_supported_devices(config): + device = not config.device.match('CM0') + device &= not config.device.match('CM0plus') + device &= not config.device.match('CM3') + device &= not config.device.match('CM4') + device &= not config.device.match('CM33') + device &= not config.device.match('CM33S') + device &= not config.device.match('CM33NS') + device &= not config.device.match('CR4') + device &= not config.device.match('CR5') + device &= not config.device.match('CR52') + device &= not config.device.match('CR52neon') + compiler = config.compiler.match('Clang_TI') + return device and compiler + + +@matrix_filter +def filter_unsupported_devices(config): + device = config.device.match('CA5neon') + device |= config.device.match('CA7neon') + device |= config.device.match('CA9neon') + device |= config.device.match('CA35') + device |= config.device.match('CA35neon') + device |= config.device.match('CA53') + device |= config.device.match('CA53neon') + device |= config.device.match('CA55') + device |= config.device.match('CA55neon') + device |= config.device.match('CA57') + device |= config.device.match('CA57neon') + device |= config.device.match('CR4') + device |= config.device.match('CR5') + device |= config.device.match('CR7') + device |= config.device.match('CR8') + device |= config.device.match('CR52') + device |= config.device.match('CR52neon') + return device + + if __name__ == "__main__": main() diff --git a/CMSIS/CoreValidation/README.md b/CMSIS/CoreValidation/README.md index 0c0eea5c4..0fe2fc54c 100644 --- a/CMSIS/CoreValidation/README.md +++ b/CMSIS/CoreValidation/README.md @@ -20,6 +20,7 @@ Currently, the following build configurations are provided: - Arm Compiler 6 (AC6) - GNU Compiler (GCC) - LLVM/Clang (Clang) + - TI Arm Clang (Clang_TI) (CM0/0+/3/4/33/33S/33NS) 2. Devices - Cortex-M0 - Cortex-M0+ @@ -68,6 +69,7 @@ The following tools are required to build and run the CoreValidation tests: - [Arm Compiler 6.20](https://artifacts.keil.arm.com/arm-compiler/6.20/21/)* - [GCC Compiler 13.2.1](https://artifacts.keil.arm.com/arm-none-eabi-gcc/13.2.1/)* - [Clang Compiler 17.0.1](https://github.com/ARM-software/LLVM-embedded-toolchain-for-Arm/releases/tag/release-17.0.1)* +- [TI Arm Clang Compiler 5.1.0 LTS](https://www.ti.com/tool/download/ARM-CGT-CLANG) - [Arm Virtual Hardware for Cortex-M based on FastModels 11.22.39](https://artifacts.keil.arm.com/avh/11.22.39/)* - [Python 3.9](https://www.python.org/downloads/) @@ -84,6 +86,8 @@ Install the Python packages required by `build.py`: ./CMSIS/CoreValidation/Project $ pip install -r requirements.txt ``` +TI Arm Clang Compiler is not supported through vcpkg and must be manually installed. After installation, configure the environment variable `CLANG_TI_TOOLCHAIN_` with the format specified by [CMSIS-Toolbox Installation -> Compiler Registration](https://open-cmsis-pack.github.io/cmsis-toolbox/installation/). + ## Build and run To build and run the CoreValidation tests for one or more configurations use the following command line. @@ -101,8 +105,8 @@ For example, build and run the tests using GCC for Cortex-M3 with low optimizati [GCC][Cortex-M3][none](build:csolution) csolution succeeded with exit code 0 [GCC][Cortex-M3][none](build:cbuild) cbuild Validation.GCC_low+CM3/Validation.GCC_low+CM3.cprj [GCC][Cortex-M3][none](build:cbuild) cbuild succeeded with exit code 0 -[GCC][Cortex-M3][none](run:model_exec) VHT_MPS2_Cortex-M3 -q --simlimit 100 -f ../Layer/Target/CM3/model_config.txt -a Validation.GCC_low+CM3/Validation.GCC_low+CM3_outdir/Validation.GCC_low+CM3.elf -[GCC][Cortex-M3][none](run:model_exec) VHT_MPS2_Cortex-M3 succeeded with exit code 0 +[GCC][Cortex-M3][none](run:model_exec) FVP_MPS2_Cortex-M3 -q --simlimit 5 -f ../Layer/Target/CM3/model_config.txt -a Validation.GCC_low+CM3/Validation.GCC_low+CM3_outdir/Validation.GCC_low+CM3.elf +[GCC][Cortex-M3][none](run:model_exec) FVP_MPS2_Cortex-M3 succeeded with exit code 0 Matrix Summary ============== diff --git a/CMSIS/CoreValidation/Source/CV_Report.c b/CMSIS/CoreValidation/Source/CV_Report.c index 3fa2d2382..ea7a26039 100644 --- a/CMSIS/CoreValidation/Source/CV_Report.c +++ b/CMSIS/CoreValidation/Source/CV_Report.c @@ -7,6 +7,9 @@ #include "CV_Report.h" #include #include +#if defined(__clang__) && defined(__ti__) +#include "clang_ti_semihost.h" +#endif TEST_REPORT test_report; static AS_STAT current_assertions; /* Current test case assertions statistics */ @@ -380,7 +383,11 @@ static void MsgFlush(void) { static void MsgPrint (const char *msg, ...) { va_list args; va_start(args, msg); +#if defined(__clang__) && defined(__ti__) + clang_ti_vprintf_semihost(msg, args); +#else vprintf(msg, args); +#endif va_end(args); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) diff --git a/CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_semihost.c b/CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_semihost.c new file mode 100644 index 000000000..d2d509b9f --- /dev/null +++ b/CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_semihost.c @@ -0,0 +1,51 @@ +/*****************************************************************************/ +/* CLANG_TI_SEMIHOST.C - ARM semihosting support for TI Arm Clang compiler */ +/* */ +/* clang_ti_vprintf_semihost: formats output into a local buffer via */ +/* vsnprintf, then writes it to the ARM debug console in a single */ +/* SYS_WRITE0 semihosting trap. No file descriptor management required. */ +/* */ +/* __FM_init (ARMv8-R only): ARMv8-R FastModel starts in HYP mode; this */ +/* naked/retained function switches to SVC mode and redirects execution to */ +/* _c_int00 so that the SVC-based semihosting trap is reachable. */ +/*****************************************************************************/ +#include +#include +#include +#include "clang_ti_semihost.h" + +/*---------------------------------------------------------------------------*/ +/* clang_ti_vprintf_semihost */ +/*---------------------------------------------------------------------------*/ +int clang_ti_vprintf_semihost(const char *_format, va_list _ap) +{ + static char buf[128]; + int n = vsnprintf(buf, sizeof(buf), _format, _ap); + if (n > 0) { + ARMSemihost_Call(SYS_WRITE0, (int32_t)buf); + } + return n; +} + +/*---------------------------------------------------------------------------*/ +/* __FM_init (ARMv8-R only) */ +/*---------------------------------------------------------------------------*/ +#if __ARM_ARCH_8R__ == 1 + +__attribute__((naked, retain)) +void __FM_init(void) +{ + __asm volatile( + "MRS r0, cpsr\n" + "MOV r1, #0x13\n" /* SET SVC MODE */ + "BFI r0, r1, #0, #5\n" + "MSR spsr_cxsf, r0\n" + "LDR r0, =_c_int00\n" /* Force reset vector to _c_int00 */ + "MSR elr_hyp, r0\n" + "DSB\n" + "ISB\n" + "ERET\n" + ); +} + +#endif /* __ARM_ARCH_8R__ == 1 */ diff --git a/CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_semihost.h b/CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_semihost.h new file mode 100644 index 000000000..d373c924b --- /dev/null +++ b/CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_semihost.h @@ -0,0 +1,87 @@ +/*****************************************************************************/ +/* CLANG_TI_SEMIHOST.H - ARM semihosting support for TI Arm Clang compiler */ +/* */ +/* Provides: */ +/* - ARM semihosting operation codes */ +/* - ARMSemihost_Call(): architecture-correct semihosting trap */ +/* - clang_ti_vprintf_semihost(): vprintf routed to the debug console */ +/*****************************************************************************/ +#ifndef _CLANG_TI_SEMIHOST_H_ +#define _CLANG_TI_SEMIHOST_H_ + +#include +#include + +/*---------------------------------------------------------------------------*/ +/* ARM semihosting operation codes */ +/*---------------------------------------------------------------------------*/ +#define SYS_CLOCK (0x10) +#define SYS_CLOSE (0x02) +#define SYS_ELAPSED (0x30) +#define SYS_ERRNO (0x13) +#define SYS_EXIT (0x18) +#define SYS_EXIT_EXTENDED (0x20) +#define SYS_FLEN (0x0C) +#define SYS_GET_CMDLINE (0x15) +#define SYS_HEAPINFO (0x16) +#define SYS_ISERROR (0x08) +#define SYS_ISTTY (0x09) +#define SYS_OPEN (0x01) +#define SYS_READ (0x06) +#define SYS_READC (0x07) +#define SYS_REMOVE (0x0E) +#define SYS_RENAME (0x0F) +#define SYS_SEEK (0x0A) +#define SYS_SYSTEM (0x12) +#define SYS_TICKFREQ (0x31) +#define SYS_TIME (0x11) +#define SYS_TMPNAM (0x0D) +#define SYS_WRITE (0x05) +#define SYS_WRITEC (0x03) +#define SYS_WRITE0 (0x04) + +/*---------------------------------------------------------------------------*/ +/* ARMSemihost_Call - Issue the architecture-correct semihosting trap. */ +/* */ +/* M-profile: BKPT #0xAB */ +/* T32 (A/R): SVC #0xAB */ +/* A32 (A/R): SVC #0x123456 */ +/*---------------------------------------------------------------------------*/ +__attribute__((noinline, optnone)) +static inline int ARMSemihost_Call(int command, int32_t arg) +{ + int ret; + __asm volatile ( + "mov r0, %[rsn] \n" + "mov r1, %[arg] \n" +#if __ARM_ARCH_PROFILE == 'M' + "bkpt #0xab \n" +#else +#ifdef __thumb__ + "svc #0xab \n" +#else + "svc #0x123456 \n" +#endif +#endif + "mov %[val], r0 \n" + : [val] "=r" (ret) + : [rsn] "r" (command), [arg] "r" (arg) + : "r0", "r1", "r2", "r3", "ip", "lr", "memory", "cc" + ); + return ret; +} + +/*---------------------------------------------------------------------------*/ +/* clang_ti_vprintf_semihost - vprintf routed to the ARM debug console. */ +/*---------------------------------------------------------------------------*/ +#ifdef __cplusplus +extern "C" { +#endif + +int clang_ti_vprintf_semihost(const char *_format, va_list _ap); + +#ifdef __cplusplus +} +#endif + +#endif /* _CLANG_TI_SEMIHOST_H_ */