From 8c76ee3d419b19a41aded41f87e55adf9023160f Mon Sep 17 00:00:00 2001 From: Shawn Mason <255018043+smmasongt@users.noreply.github.com> Date: Fri, 20 Feb 2026 00:11:38 -0500 Subject: [PATCH 01/17] Add TI Arm Clang Compiler Support to CMSIS Core Validation --- .../Target/CM0/RTE/Device/ARMCM0/tiac_arm.cmd | 41 ------------ .../Layer/Target/CM0/Target.clayer.yml | 2 + .../CM0plus/RTE/Device/ARMCM0P/tiac_arm.cmd | 41 ------------ .../Layer/Target/CM0plus/Target.clayer.yml | 2 + .../Target/CM3/RTE/Device/ARMCM3/tiac_arm.cmd | 41 ------------ .../Layer/Target/CM3/Target.clayer.yml | 2 + .../Layer/Target/CM33/Target.clayer.yml | 2 + .../Layer/Target/CM33NS/Target.clayer.yml | 2 + .../Layer/Target/CM33S/Target.clayer.yml | 2 + .../Target/CM4/RTE/Device/ARMCM4/tiac_arm.cmd | 41 ------------ .../Layer/Target/CM4/Target.clayer.yml | 2 + CMSIS/CoreValidation/Project/build.py | 62 ++++++++++++++++--- CMSIS/CoreValidation/README.md | 4 ++ 13 files changed, 73 insertions(+), 171 deletions(-) delete mode 100644 CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/tiac_arm.cmd delete mode 100644 CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/tiac_arm.cmd delete mode 100644 CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/tiac_arm.cmd delete mode 100644 CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/tiac_arm.cmd diff --git a/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/tiac_arm.cmd b/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/tiac_arm.cmd deleted file mode 100644 index 391dda4f0..000000000 --- a/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/tiac_arm.cmd +++ /dev/null @@ -1,41 +0,0 @@ -/****************************************************************************/ -/* tiac_arm.cmd - COMMAND FILE FOR LINKING ARM C PROGRAMS */ -/* */ -/* Description: This file is a sample command file that can be used */ -/* for linking programs built with the TI Arm Clang */ -/* Compiler. Use it as a guideline; you may want to change */ -/* the allocation scheme according to the size of your */ -/* program and the memory layout of your target system. */ -/* */ -/****************************************************************************/ --c /* LINK USING C CONVENTIONS */ --stack 0x4000 /* SOFTWARE STACK SIZE */ --heap 0x4000 /* HEAP AREA SIZE */ ---args 0x1000 - -/* SPECIFY THE SYSTEM MEMORY MAP */ -MEMORY -{ - V_MEM : org = 0x00000000 len = 0x00001000 /* INT VECTOR */ - P_MEM : org = 0x00001000 len = 0x20000000 /* PROGRAM MEMORY (ROM) */ - D_MEM : org = 0x20001000 len = 0x20000000 /* DATA MEMORY (RAM) */ -} - -/* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */ -SECTIONS -{ - .intvecs : {} > 0x0 /* INTERRUPT VECTORS */ - .bss : {} > D_MEM /* GLOBAL & STATIC VARS */ - .data : {} > D_MEM - .sysmem : {} > D_MEM /* DYNAMIC MEMORY ALLOCATION AREA */ - .stack : {} > D_MEM /* SOFTWARE SYSTEM STACK */ - - .text : {} > P_MEM /* CODE */ - .cinit : {} > P_MEM /* INITIALIZATION TABLES */ - .const : {} > P_MEM /* CONSTANT DATA */ - .rodata : {} > P_MEM, palign(4) - .init_array : {} > P_MEM /* C++ CONSTRUCTOR TABLES */ - - - .TI.ramfunc : {} load=P_MEM, run=D_MEM, table(BINIT) -} diff --git a/CMSIS/CoreValidation/Layer/Target/CM0/Target.clayer.yml b/CMSIS/CoreValidation/Layer/Target/CM0/Target.clayer.yml index 8f926e457..ec2ff0fae 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM0/Target.clayer.yml +++ b/CMSIS/CoreValidation/Layer/Target/CM0/Target.clayer.yml @@ -22,6 +22,8 @@ layer: - for-compiler: CLANG script: RTE/Device/$Dname$/clang_linker_script.ld regions: RTE/Device/$Dname$/regions_$Dname$.h + - for-compiler: CLANG_TI + regions: RTE/Device/$Dname$/regions_$Dname$.h - for-compiler: IAR script: RTE/Device/$Dname$/iar_linker_script.icf regions: RTE/Device/$Dname$/regions_$Dname$.h diff --git a/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/tiac_arm.cmd b/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/tiac_arm.cmd deleted file mode 100644 index 391dda4f0..000000000 --- a/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/tiac_arm.cmd +++ /dev/null @@ -1,41 +0,0 @@ -/****************************************************************************/ -/* tiac_arm.cmd - COMMAND FILE FOR LINKING ARM C PROGRAMS */ -/* */ -/* Description: This file is a sample command file that can be used */ -/* for linking programs built with the TI Arm Clang */ -/* Compiler. Use it as a guideline; you may want to change */ -/* the allocation scheme according to the size of your */ -/* program and the memory layout of your target system. */ -/* */ -/****************************************************************************/ --c /* LINK USING C CONVENTIONS */ --stack 0x4000 /* SOFTWARE STACK SIZE */ --heap 0x4000 /* HEAP AREA SIZE */ ---args 0x1000 - -/* SPECIFY THE SYSTEM MEMORY MAP */ -MEMORY -{ - V_MEM : org = 0x00000000 len = 0x00001000 /* INT VECTOR */ - P_MEM : org = 0x00001000 len = 0x20000000 /* PROGRAM MEMORY (ROM) */ - D_MEM : org = 0x20001000 len = 0x20000000 /* DATA MEMORY (RAM) */ -} - -/* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */ -SECTIONS -{ - .intvecs : {} > 0x0 /* INTERRUPT VECTORS */ - .bss : {} > D_MEM /* GLOBAL & STATIC VARS */ - .data : {} > D_MEM - .sysmem : {} > D_MEM /* DYNAMIC MEMORY ALLOCATION AREA */ - .stack : {} > D_MEM /* SOFTWARE SYSTEM STACK */ - - .text : {} > P_MEM /* CODE */ - .cinit : {} > P_MEM /* INITIALIZATION TABLES */ - .const : {} > P_MEM /* CONSTANT DATA */ - .rodata : {} > P_MEM, palign(4) - .init_array : {} > P_MEM /* C++ CONSTRUCTOR TABLES */ - - - .TI.ramfunc : {} load=P_MEM, run=D_MEM, table(BINIT) -} diff --git a/CMSIS/CoreValidation/Layer/Target/CM0plus/Target.clayer.yml b/CMSIS/CoreValidation/Layer/Target/CM0plus/Target.clayer.yml index 8f7da0e94..8d3bd714c 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM0plus/Target.clayer.yml +++ b/CMSIS/CoreValidation/Layer/Target/CM0plus/Target.clayer.yml @@ -22,6 +22,8 @@ layer: - for-compiler: CLANG script: RTE/Device/$Dname$/clang_linker_script.ld regions: RTE/Device/$Dname$/regions_$Dname$.h + - for-compiler: CLANG_TI + regions: RTE/Device/$Dname$/regions_$Dname$.h - for-compiler: IAR script: RTE/Device/$Dname$/iar_linker_script.icf regions: RTE/Device/$Dname$/regions_$Dname$.h diff --git a/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/tiac_arm.cmd b/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/tiac_arm.cmd deleted file mode 100644 index 391dda4f0..000000000 --- a/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/tiac_arm.cmd +++ /dev/null @@ -1,41 +0,0 @@ -/****************************************************************************/ -/* tiac_arm.cmd - COMMAND FILE FOR LINKING ARM C PROGRAMS */ -/* */ -/* Description: This file is a sample command file that can be used */ -/* for linking programs built with the TI Arm Clang */ -/* Compiler. Use it as a guideline; you may want to change */ -/* the allocation scheme according to the size of your */ -/* program and the memory layout of your target system. */ -/* */ -/****************************************************************************/ --c /* LINK USING C CONVENTIONS */ --stack 0x4000 /* SOFTWARE STACK SIZE */ --heap 0x4000 /* HEAP AREA SIZE */ ---args 0x1000 - -/* SPECIFY THE SYSTEM MEMORY MAP */ -MEMORY -{ - V_MEM : org = 0x00000000 len = 0x00001000 /* INT VECTOR */ - P_MEM : org = 0x00001000 len = 0x20000000 /* PROGRAM MEMORY (ROM) */ - D_MEM : org = 0x20001000 len = 0x20000000 /* DATA MEMORY (RAM) */ -} - -/* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */ -SECTIONS -{ - .intvecs : {} > 0x0 /* INTERRUPT VECTORS */ - .bss : {} > D_MEM /* GLOBAL & STATIC VARS */ - .data : {} > D_MEM - .sysmem : {} > D_MEM /* DYNAMIC MEMORY ALLOCATION AREA */ - .stack : {} > D_MEM /* SOFTWARE SYSTEM STACK */ - - .text : {} > P_MEM /* CODE */ - .cinit : {} > P_MEM /* INITIALIZATION TABLES */ - .const : {} > P_MEM /* CONSTANT DATA */ - .rodata : {} > P_MEM, palign(4) - .init_array : {} > P_MEM /* C++ CONSTRUCTOR TABLES */ - - - .TI.ramfunc : {} load=P_MEM, run=D_MEM, table(BINIT) -} diff --git a/CMSIS/CoreValidation/Layer/Target/CM3/Target.clayer.yml b/CMSIS/CoreValidation/Layer/Target/CM3/Target.clayer.yml index 2d95c5dd8..aecfe6aa5 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM3/Target.clayer.yml +++ b/CMSIS/CoreValidation/Layer/Target/CM3/Target.clayer.yml @@ -22,6 +22,8 @@ layer: - for-compiler: CLANG script: RTE/Device/$Dname$/clang_linker_script.ld regions: RTE/Device/$Dname$/regions_$Dname$.h + - for-compiler: CLANG_TI + regions: RTE/Device/$Dname$/regions_$Dname$.h - for-compiler: IAR script: RTE/Device/$Dname$/iar_linker_script.icf regions: RTE/Device/$Dname$/regions_$Dname$.h diff --git a/CMSIS/CoreValidation/Layer/Target/CM33/Target.clayer.yml b/CMSIS/CoreValidation/Layer/Target/CM33/Target.clayer.yml index f5c93b813..7633def5e 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM33/Target.clayer.yml +++ b/CMSIS/CoreValidation/Layer/Target/CM33/Target.clayer.yml @@ -25,6 +25,8 @@ layer: - for-compiler: CLANG script: RTE/Device/$Dname$/clang_linker_script.ld regions: RTE/Device/$Dname$/regions_$Dname$.h + - for-compiler: CLANG_TI + regions: RTE/Device/$Dname$/regions_$Dname$.h - for-compiler: IAR script: RTE/Device/$Dname$/iar_linker_script.icf regions: RTE/Device/$Dname$/regions_$Dname$.h diff --git a/CMSIS/CoreValidation/Layer/Target/CM33NS/Target.clayer.yml b/CMSIS/CoreValidation/Layer/Target/CM33NS/Target.clayer.yml index 51693352e..77d7645aa 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM33NS/Target.clayer.yml +++ b/CMSIS/CoreValidation/Layer/Target/CM33NS/Target.clayer.yml @@ -25,6 +25,8 @@ layer: - for-compiler: CLANG script: RTE/Device/$Dname$/clang_linker_script.ld regions: RTE/Device/$Dname$/regions_$Dname$.h + - for-compiler: CLANG_TI + regions: RTE/Device/$Dname$/regions_$Dname$.h - for-compiler: IAR script: RTE/Device/$Dname$/iar_linker_script.icf regions: RTE/Device/$Dname$/regions_$Dname$.h diff --git a/CMSIS/CoreValidation/Layer/Target/CM33S/Target.clayer.yml b/CMSIS/CoreValidation/Layer/Target/CM33S/Target.clayer.yml index a513f15aa..780b241db 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM33S/Target.clayer.yml +++ b/CMSIS/CoreValidation/Layer/Target/CM33S/Target.clayer.yml @@ -25,6 +25,8 @@ layer: - for-compiler: CLANG script: RTE/Device/$Dname$/clang_linker_script.ld regions: RTE/Device/$Dname$/regions_$Dname$.h + - for-compiler: CLANG_TI + regions: RTE/Device/$Dname$/regions_$Dname$.h - for-compiler: IAR script: RTE/Device/$Dname$/iar_linker_script.icf regions: RTE/Device/$Dname$/regions_$Dname$.h diff --git a/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/tiac_arm.cmd b/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/tiac_arm.cmd deleted file mode 100644 index 391dda4f0..000000000 --- a/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/tiac_arm.cmd +++ /dev/null @@ -1,41 +0,0 @@ -/****************************************************************************/ -/* tiac_arm.cmd - COMMAND FILE FOR LINKING ARM C PROGRAMS */ -/* */ -/* Description: This file is a sample command file that can be used */ -/* for linking programs built with the TI Arm Clang */ -/* Compiler. Use it as a guideline; you may want to change */ -/* the allocation scheme according to the size of your */ -/* program and the memory layout of your target system. */ -/* */ -/****************************************************************************/ --c /* LINK USING C CONVENTIONS */ --stack 0x4000 /* SOFTWARE STACK SIZE */ --heap 0x4000 /* HEAP AREA SIZE */ ---args 0x1000 - -/* SPECIFY THE SYSTEM MEMORY MAP */ -MEMORY -{ - V_MEM : org = 0x00000000 len = 0x00001000 /* INT VECTOR */ - P_MEM : org = 0x00001000 len = 0x20000000 /* PROGRAM MEMORY (ROM) */ - D_MEM : org = 0x20001000 len = 0x20000000 /* DATA MEMORY (RAM) */ -} - -/* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */ -SECTIONS -{ - .intvecs : {} > 0x0 /* INTERRUPT VECTORS */ - .bss : {} > D_MEM /* GLOBAL & STATIC VARS */ - .data : {} > D_MEM - .sysmem : {} > D_MEM /* DYNAMIC MEMORY ALLOCATION AREA */ - .stack : {} > D_MEM /* SOFTWARE SYSTEM STACK */ - - .text : {} > P_MEM /* CODE */ - .cinit : {} > P_MEM /* INITIALIZATION TABLES */ - .const : {} > P_MEM /* CONSTANT DATA */ - .rodata : {} > P_MEM, palign(4) - .init_array : {} > P_MEM /* C++ CONSTRUCTOR TABLES */ - - - .TI.ramfunc : {} load=P_MEM, run=D_MEM, table(BINIT) -} diff --git a/CMSIS/CoreValidation/Layer/Target/CM4/Target.clayer.yml b/CMSIS/CoreValidation/Layer/Target/CM4/Target.clayer.yml index def139200..973d0b36e 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM4/Target.clayer.yml +++ b/CMSIS/CoreValidation/Layer/Target/CM4/Target.clayer.yml @@ -22,6 +22,8 @@ layer: - for-compiler: CLANG script: RTE/Device/$Dname$/clang_linker_script.ld regions: RTE/Device/$Dname$/regions_$Dname$.h + - for-compiler: CLANG_TI + regions: RTE/Device/$Dname$/regions_$Dname$.h - for-compiler: IAR script: RTE/Device/$Dname$/iar_linker_script.icf regions: RTE/Device/$Dname$/regions_$Dname$.h diff --git a/CMSIS/CoreValidation/Project/build.py b/CMSIS/CoreValidation/Project/build.py index 41f654839..dc6c03f29 100755 --- a/CMSIS/CoreValidation/Project/build.py +++ b/CMSIS/CoreValidation/Project/build.py @@ -41,11 +41,17 @@ class DeviceAxis(Enum): CM85S = ('Cortex-M85S', 'CM85S') CM85NS = ('Cortex-M85NS', 'CM85NS') CA5 = ('Cortex-A5', 'CA5') + CA5NEON = ('Cortex-A5neon', 'CA5neon') CA7 = ('Cortex-A7', 'CA7') + CA7NEON = ('Cortex-A7neon', 'CA7neon') CA9 = ('Cortex-A9', 'CA9') -# CA5NEON = ('Cortex-A5neon', 'CA5neon') -# CA7NEON = ('Cortex-A7neon', 'CA7neon') -# CA9NEON = ('Cortex-A9neon', 'CA9neon') + CA9NEON = ('Cortex-A9neon', 'CA9neon') + CA53 = ('Cortex-A53', 'CA53') + CA53NEON = ('Cortex-A53neon', 'CA53neon') + CR4 = ('Cortex-R4', 'CR4') + CR5 = ('Cortex-R5', 'CR5') + CR52 = ('Cortex-R52', 'CR52') + CR52NEON = ('Cortex-R52neon', 'CR52neon') def has_bl(self): return self in [ @@ -76,6 +82,7 @@ class CompilerAxis(Enum): GCC = ('GCC') IAR = ('IAR') CLANG = ('Clang') + CLANG_TI = ('Clang_TI') @property def image_ext(self): @@ -84,6 +91,7 @@ def image_ext(self): CompilerAxis.GCC: 'elf', CompilerAxis.IAR: 'elf', CompilerAxis.CLANG: 'elf', + CompilerAxis.CLANG_TI: 'elf', } return ext[self] @@ -93,7 +101,8 @@ def toolchain(self): CompilerAxis.AC6: 'AC6', CompilerAxis.GCC: 'GCC', CompilerAxis.IAR: 'IAR', - CompilerAxis.CLANG: 'CLANG' + CompilerAxis.CLANG: 'CLANG', + CompilerAxis.CLANG_TI: 'CLANG_TI', } return ext[self] @@ -131,11 +140,17 @@ class OptimizationAxis(Enum): DeviceAxis.CM85S: ("FVP_MPS2_Cortex-M85", []), DeviceAxis.CM85NS: ("FVP_MPS2_Cortex-M85", []), DeviceAxis.CA5: ("FVP_VE_Cortex-A5x1", []), + DeviceAxis.CA5NEON: ("_VE_Cortex-A5x1", []), DeviceAxis.CA7: ("FVP_VE_Cortex-A7x1", []), + DeviceAxis.CA7NEON: ("_VE_Cortex-A7x1", []), DeviceAxis.CA9: ("FVP_VE_Cortex-A9x1", []), -# DeviceAxis.CA5NEON: ("_VE_Cortex-A5x1", []), -# DeviceAxis.CA7NEON: ("_VE_Cortex-A7x1", []), -# DeviceAxis.CA9NEON: ("_VE_Cortex-A9x1", []) + DeviceAxis.CA9NEON: ("_VE_Cortex-A9x1", []), + DeviceAxis.CA53: ("FVP_VE_Cortex-A53x1", []), + DeviceAxis.CA53NEON: ("_VE_Cortex-A53x1", []), + DeviceAxis.CR4: ("FVP_MPS2_Cortex-R4", []), + DeviceAxis.CR5: ("FVP_MPS2_Cortex-R5", []), + DeviceAxis.CR52: ("FVP_MPS2_Cortex-R52", []), + DeviceAxis.CR52NEON: ("_VE_MPS2_Cortex-R52", []), } QEMU_MACHINE = { @@ -298,5 +313,38 @@ def filter_gcc_cm52(config): return device and compiler +@matrix_filter +def filter_clang_ti_supported_devices(config): + device = not config.device.match('CM0') + device = not config.device.match('CM0plus') + device &= not config.device.match('CM3') + device &= not config.device.match('CM4') + device &= not config.device.match('CM33') + device &= not config.device.match('CM33S') + device &= not config.device.match('CM33NS') + device &= not config.device.match('CR4') + device &= not config.device.match('CR5') + device &= not config.device.match('CR52') + device &= not config.device.match('CR52neon') + device &= not config.device.match('CA53') + device &= not config.device.match('CA53neon') + compiler = config.compiler.match('Clang_TI') + return device and compiler + + +@matrix_filter +def filter_unsupported_devices(config): + device = config.device.match('CA5neon') + device |= config.device.match('CA7neon') + device |= config.device.match('CA9neon') + device |= config.device.match('CA53') + device |= config.device.match('CA53neon') + device |= config.device.match('CR4') + device |= config.device.match('CR5') + device |= config.device.match('CR52') + device |= config.device.match('CR52neon') + return device + + if __name__ == "__main__": main() diff --git a/CMSIS/CoreValidation/README.md b/CMSIS/CoreValidation/README.md index 0c0eea5c4..fb7f02a0a 100644 --- a/CMSIS/CoreValidation/README.md +++ b/CMSIS/CoreValidation/README.md @@ -20,6 +20,7 @@ Currently, the following build configurations are provided: - Arm Compiler 6 (AC6) - GNU Compiler (GCC) - LLVM/Clang (Clang) + - TI Arm Clang (Clang_TI) (CM0/0+/3/4) 2. Devices - Cortex-M0 - Cortex-M0+ @@ -68,6 +69,7 @@ The following tools are required to build and run the CoreValidation tests: - [Arm Compiler 6.20](https://artifacts.keil.arm.com/arm-compiler/6.20/21/)* - [GCC Compiler 13.2.1](https://artifacts.keil.arm.com/arm-none-eabi-gcc/13.2.1/)* - [Clang Compiler 17.0.1](https://github.com/ARM-software/LLVM-embedded-toolchain-for-Arm/releases/tag/release-17.0.1)* +- [TI Arm Clang Compiler 5.0.0](https://www.ti.com/tool/download/ARM-CGT-CLANG) - [Arm Virtual Hardware for Cortex-M based on FastModels 11.22.39](https://artifacts.keil.arm.com/avh/11.22.39/)* - [Python 3.9](https://www.python.org/downloads/) @@ -84,6 +86,8 @@ Install the Python packages required by `build.py`: ./CMSIS/CoreValidation/Project $ pip install -r requirements.txt ``` +TI Arm Clang Compiler is not supported through vcpkg and must be manually installed. After installation, configure the environment variable `CLANG_TI_TOOLCHAIN_` with the format specified by [CMSIS-Toolbox Installation -> Compiler Registration](https://open-cmsis-pack.github.io/cmsis-toolbox/installation/). + ## Build and run To build and run the CoreValidation tests for one or more configurations use the following command line. From 0451d70356450d1a33eb15254c31202b98176f3c Mon Sep 17 00:00:00 2001 From: Shawn Mason <255018043+smmasongt@users.noreply.github.com> Date: Sun, 22 Feb 2026 16:41:16 -0500 Subject: [PATCH 02/17] Add TI Arm Clang Compiler to Core Validation Workflow --- .github/workflows/corevalidation.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/corevalidation.yml b/.github/workflows/corevalidation.yml index 75bee70ae..330dc62a4 100644 --- a/.github/workflows/corevalidation.yml +++ b/.github/workflows/corevalidation.yml @@ -21,7 +21,7 @@ jobs: strategy: fail-fast: true matrix: - compiler: [AC6, GCC, Clang] + compiler: [AC6, GCC, Clang, Clang_TI] runs-on: ubuntu-22.04 From 4baf5878f9417f01840de2fae14e75239ff58521 Mon Sep 17 00:00:00 2001 From: Shawn Mason <255018043+smmasongt@users.noreply.github.com> Date: Fri, 6 Mar 2026 23:33:01 -0500 Subject: [PATCH 03/17] Add TI Arm Clang Compiler Download and Cache to Core Test Workflow --- .github/workflows/core.yml | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/.github/workflows/core.yml b/.github/workflows/core.yml index 5bf1a4ea9..fdf3a7c3d 100644 --- a/.github/workflows/core.yml +++ b/.github/workflows/core.yml @@ -20,6 +20,9 @@ jobs: env: ARM_UBL_ACTIVATION_CODE: ${{ secrets.ARM_UBL_ACTIVATION_CODE }} + CLANG_TI_VERSION: "5.0.0.STS" + CLANG_TI_PATH: "~/ti_arm_cgt" + CLANG_TI_SHA256: "7a71570703f93f3682258b95d5a14a620cd6a5fc74dc5233f2d6c56d366c6da2" steps: - uses: actions/checkout@v6 @@ -52,6 +55,28 @@ jobs: - uses: ammaraskar/gcc-problem-matcher@master + - name: Cache TI Arm Clang + id: cache-ti-arm-clang + uses: actions/cache@v4 + with: + path: ${{ env.CLANG_TI_PATH }} + key: ${{ runner.os }}-ti-arm-clang-${{ env.CLANG_TI_VERSION }} + + - name: Download and Verify TI Arm Clang Installer + if: steps.cache-ti-arm-clang.outputs.cache-hit != 'true' + run: | + FILE="ti_cgt_armllvm_${{ env.CLANG_TI_VERSION }}_linux-x64_installer.bin" + URL="https://dr-download.ti.com/software-development/ide-configuration-compiler-or-debugger/MD-ayxs93eZNN/${{ env.CLANG_TI_VERSION }}/${FILE}" + + curl -L "$URL" -o "$FILE" + echo "${{ env.CLANG_TI_SHA256 }} $FILE" | sha256sum --check + chmod +x "$FILE" + ./"$FILE" --mode unattended --prefix "${{ env.CLANG_TI_PATH }}" + + - name: Set TI Arm Clang Environment Variable + run: | + echo "CLANG_TI_TOOLCHAIN_${{ env.CLANG_TI_VERSION }}=${{ env.CLANG_TI_PATH }}/bin" >> $GITHUB_ENV + - name: Run LIT working-directory: ./CMSIS/Core/Test run: | From 28202e8a3d90bc35fc5acb374971b229e38b8bc9 Mon Sep 17 00:00:00 2001 From: Shawn Mason <255018043+smmasongt@users.noreply.github.com> Date: Sun, 8 Mar 2026 17:34:16 -0400 Subject: [PATCH 04/17] Add TI Arm Clang Compiler to GitHub Workflow --- .github/workflows/corevalidation.yml | 28 ++++++++ .../Device/ARMCM0/clang_ti_linker_script.cmd | 66 +++++++++++++++++++ .../Layer/Target/CM0/Target.clayer.yml | 1 + .../Device/ARMCM0P/clang_ti_linker_script.cmd | 66 +++++++++++++++++++ .../Layer/Target/CM0plus/Target.clayer.yml | 1 + .../Device/ARMCM3/clang_ti_linker_script.cmd | 66 +++++++++++++++++++ .../Layer/Target/CM3/Target.clayer.yml | 1 + .../Device/ARMCM33/clang_ti_linker_script.cmd | 66 +++++++++++++++++++ .../Layer/Target/CM33/Target.clayer.yml | 1 + .../Device/ARMCM33/clang_ti_linker_script.cmd | 66 +++++++++++++++++++ .../Layer/Target/CM33NS/Target.clayer.yml | 1 + .../Device/ARMCM33/clang_ti_linker_script.cmd | 66 +++++++++++++++++++ .../Layer/Target/CM33S/Target.clayer.yml | 1 + .../Device/ARMCM4/clang_ti_linker_script.cmd | 66 +++++++++++++++++++ .../Layer/Target/CM4/Target.clayer.yml | 1 + 15 files changed, 497 insertions(+) create mode 100644 CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/clang_ti_linker_script.cmd create mode 100644 CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/clang_ti_linker_script.cmd create mode 100644 CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/clang_ti_linker_script.cmd create mode 100644 CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33/clang_ti_linker_script.cmd create mode 100644 CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33/clang_ti_linker_script.cmd create mode 100644 CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33/clang_ti_linker_script.cmd create mode 100644 CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/clang_ti_linker_script.cmd diff --git a/.github/workflows/corevalidation.yml b/.github/workflows/corevalidation.yml index 330dc62a4..90815999f 100644 --- a/.github/workflows/corevalidation.yml +++ b/.github/workflows/corevalidation.yml @@ -27,6 +27,10 @@ jobs: env: ARM_UBL_ACTIVATION_CODE: ${{ secrets.ARM_UBL_ACTIVATION_CODE }} + CLANG_TI_VERSION: "5.0.0.STS" + CLANG_TI_TC_SUFFIX: "5_0_0" + CLANG_TI_INSTALL_PATH: "/home/runner/" + CLANG_TI_SHA256: "7a71570703f93f3682258b95d5a14a620cd6a5fc74dc5233f2d6c56d366c6da2" steps: - run: | @@ -83,6 +87,30 @@ jobs: - uses: ammaraskar/gcc-problem-matcher@master if: matrix.compiler == 'Clang' || matrix.compiler == 'GCC' + - name: Set TI ARM CLANG Environment Variables and Path + run: | + echo "CLANG_TI_PATH=${{ env.CLANG_TI_INSTALL_PATH }}ti-cgt-armllvm_${{ env.CLANG_TI_VERSION }}" >> $GITHUB_ENV + echo "CLANG_TI_TOOLCHAIN_${{ env.CLANG_TI_TC_SUFFIX }}=${{ env.CLANG_TI_INSTALL_PATH }}ti-cgt-armllvm_${{ env.CLANG_TI_VERSION }}/bin" >> $GITHUB_ENV + + - name: Cache TI ARM CLANG + id: cache-ti-arm-clang + uses: actions/cache@v4 + with: + path: ${{ env.CLANG_TI_PATH }} + key: ${{ runner.os }}-ti-arm-clang-${{ env.CLANG_TI_VERSION }} + + - name: Download and Verify TI ARM CLANG Installer + working-directory: /home/runner + if: steps.cache-ti-arm-clang.outputs.cache-hit != 'true' + run: | + FILE="ti_cgt_armllvm_${{ env.CLANG_TI_VERSION }}_linux-x64_installer.bin" + URL="https://dr-download.ti.com/software-development/ide-configuration-compiler-or-debugger/MD-ayxs93eZNN/${{ env.CLANG_TI_VERSION }}/${FILE}" + + curl -L "$URL" -o "$FILE" + echo "${{ env.CLANG_TI_SHA256 }} $FILE" | sha256sum --check + chmod +x "$FILE" + ./"$FILE" --mode unattended --prefix "${{ env.CLANG_TI_INSTALL_PATH }}" + - name: Build working-directory: ./CMSIS/CoreValidation/Project run: | diff --git a/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/clang_ti_linker_script.cmd b/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/clang_ti_linker_script.cmd new file mode 100644 index 000000000..a898c464e --- /dev/null +++ b/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/clang_ti_linker_script.cmd @@ -0,0 +1,66 @@ +--stack_size=__STACK_SIZE +--heap_size=__HEAP_SIZE +--symbol_map=_start=_c_int00 + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define __STACKSEAL_SIZE 8 +#else + #define __STACKSEAL_SIZE 0 +#endif + +#if defined (__ROM0_BASE) + __stack = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; + __stack_seal = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; + __stack_limit = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE; + #define __STACK_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1) + #define __STACK_LIMIT_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE) +#else + __stack = __ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - 1; + __stack_seal = __ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - 1; + __stack_limit = __ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - __STACK_SIZE; + #define __STACK_ADDR (__ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - 1) + #define __STACK_LIMIT_ADDR (__ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - __STACK_SIZE) +#endif + +MEMORY +{ +#if defined (__ROM0_BASE) + ROM0 : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE +#else + ROM0 : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE +#endif + +#if defined (__ROM1_BASE) + ROM1 : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE +#endif + +#if defined (__RAM0_BASE) + RAM0 : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE +#else + RAM0 : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE +#endif + +#if defined (__RAM1_BASE) + RAM1 : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE +#endif +} + +SECTIONS +{ +.vectors: 0x00000000 +.cinit: palign=4 {} > ROM0 +.pinit: palign=4 {} > ROM0 + +.text: palign=4 {} > ROM0 +.const: palign=4 {} > ROM0 +.rodata: palign=4 {} > ROM0 + +.data: palign=4 {} > RAM0 +.bss: type=NOINIT, palign=4 {} > RAM0 + +.stack: run=__STACK_LIMIT_ADDR, type=NOLOAD {} > RAM0 + +#if __STACKSEAL_SIZE > 0 + .stackseal: run=__STACK_ADDR, type=NOLOAD {} > RAM0 +#endif +} \ No newline at end of file diff --git a/CMSIS/CoreValidation/Layer/Target/CM0/Target.clayer.yml b/CMSIS/CoreValidation/Layer/Target/CM0/Target.clayer.yml index ec2ff0fae..ca971446f 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM0/Target.clayer.yml +++ b/CMSIS/CoreValidation/Layer/Target/CM0/Target.clayer.yml @@ -23,6 +23,7 @@ layer: script: RTE/Device/$Dname$/clang_linker_script.ld regions: RTE/Device/$Dname$/regions_$Dname$.h - for-compiler: CLANG_TI + script: RTE/Device/$Dname$/clang_ti_linker_script.ld regions: RTE/Device/$Dname$/regions_$Dname$.h - for-compiler: IAR script: RTE/Device/$Dname$/iar_linker_script.icf diff --git a/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/clang_ti_linker_script.cmd b/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/clang_ti_linker_script.cmd new file mode 100644 index 000000000..a898c464e --- /dev/null +++ b/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/clang_ti_linker_script.cmd @@ -0,0 +1,66 @@ +--stack_size=__STACK_SIZE +--heap_size=__HEAP_SIZE +--symbol_map=_start=_c_int00 + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define __STACKSEAL_SIZE 8 +#else + #define __STACKSEAL_SIZE 0 +#endif + +#if defined (__ROM0_BASE) + __stack = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; + __stack_seal = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; + __stack_limit = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE; + #define __STACK_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1) + #define __STACK_LIMIT_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE) +#else + __stack = __ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - 1; + __stack_seal = __ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - 1; + __stack_limit = __ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - __STACK_SIZE; + #define __STACK_ADDR (__ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - 1) + #define __STACK_LIMIT_ADDR (__ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - __STACK_SIZE) +#endif + +MEMORY +{ +#if defined (__ROM0_BASE) + ROM0 : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE +#else + ROM0 : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE +#endif + +#if defined (__ROM1_BASE) + ROM1 : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE +#endif + +#if defined (__RAM0_BASE) + RAM0 : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE +#else + RAM0 : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE +#endif + +#if defined (__RAM1_BASE) + RAM1 : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE +#endif +} + +SECTIONS +{ +.vectors: 0x00000000 +.cinit: palign=4 {} > ROM0 +.pinit: palign=4 {} > ROM0 + +.text: palign=4 {} > ROM0 +.const: palign=4 {} > ROM0 +.rodata: palign=4 {} > ROM0 + +.data: palign=4 {} > RAM0 +.bss: type=NOINIT, palign=4 {} > RAM0 + +.stack: run=__STACK_LIMIT_ADDR, type=NOLOAD {} > RAM0 + +#if __STACKSEAL_SIZE > 0 + .stackseal: run=__STACK_ADDR, type=NOLOAD {} > RAM0 +#endif +} \ No newline at end of file diff --git a/CMSIS/CoreValidation/Layer/Target/CM0plus/Target.clayer.yml b/CMSIS/CoreValidation/Layer/Target/CM0plus/Target.clayer.yml index 8d3bd714c..a771830f4 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM0plus/Target.clayer.yml +++ b/CMSIS/CoreValidation/Layer/Target/CM0plus/Target.clayer.yml @@ -23,6 +23,7 @@ layer: script: RTE/Device/$Dname$/clang_linker_script.ld regions: RTE/Device/$Dname$/regions_$Dname$.h - for-compiler: CLANG_TI + script: RTE/Device/$Dname$/clang_ti_linker_script.ld regions: RTE/Device/$Dname$/regions_$Dname$.h - for-compiler: IAR script: RTE/Device/$Dname$/iar_linker_script.icf diff --git a/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/clang_ti_linker_script.cmd b/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/clang_ti_linker_script.cmd new file mode 100644 index 000000000..a898c464e --- /dev/null +++ b/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/clang_ti_linker_script.cmd @@ -0,0 +1,66 @@ +--stack_size=__STACK_SIZE +--heap_size=__HEAP_SIZE +--symbol_map=_start=_c_int00 + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define __STACKSEAL_SIZE 8 +#else + #define __STACKSEAL_SIZE 0 +#endif + +#if defined (__ROM0_BASE) + __stack = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; + __stack_seal = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; + __stack_limit = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE; + #define __STACK_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1) + #define __STACK_LIMIT_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE) +#else + __stack = __ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - 1; + __stack_seal = __ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - 1; + __stack_limit = __ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - __STACK_SIZE; + #define __STACK_ADDR (__ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - 1) + #define __STACK_LIMIT_ADDR (__ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - __STACK_SIZE) +#endif + +MEMORY +{ +#if defined (__ROM0_BASE) + ROM0 : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE +#else + ROM0 : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE +#endif + +#if defined (__ROM1_BASE) + ROM1 : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE +#endif + +#if defined (__RAM0_BASE) + RAM0 : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE +#else + RAM0 : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE +#endif + +#if defined (__RAM1_BASE) + RAM1 : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE +#endif +} + +SECTIONS +{ +.vectors: 0x00000000 +.cinit: palign=4 {} > ROM0 +.pinit: palign=4 {} > ROM0 + +.text: palign=4 {} > ROM0 +.const: palign=4 {} > ROM0 +.rodata: palign=4 {} > ROM0 + +.data: palign=4 {} > RAM0 +.bss: type=NOINIT, palign=4 {} > RAM0 + +.stack: run=__STACK_LIMIT_ADDR, type=NOLOAD {} > RAM0 + +#if __STACKSEAL_SIZE > 0 + .stackseal: run=__STACK_ADDR, type=NOLOAD {} > RAM0 +#endif +} \ No newline at end of file diff --git a/CMSIS/CoreValidation/Layer/Target/CM3/Target.clayer.yml b/CMSIS/CoreValidation/Layer/Target/CM3/Target.clayer.yml index aecfe6aa5..f9e07e31b 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM3/Target.clayer.yml +++ b/CMSIS/CoreValidation/Layer/Target/CM3/Target.clayer.yml @@ -23,6 +23,7 @@ layer: script: RTE/Device/$Dname$/clang_linker_script.ld regions: RTE/Device/$Dname$/regions_$Dname$.h - for-compiler: CLANG_TI + script: RTE/Device/$Dname$/clang_ti_linker_script.ld regions: RTE/Device/$Dname$/regions_$Dname$.h - for-compiler: IAR script: RTE/Device/$Dname$/iar_linker_script.icf diff --git a/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33/clang_ti_linker_script.cmd b/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33/clang_ti_linker_script.cmd new file mode 100644 index 000000000..a898c464e --- /dev/null +++ b/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33/clang_ti_linker_script.cmd @@ -0,0 +1,66 @@ +--stack_size=__STACK_SIZE +--heap_size=__HEAP_SIZE +--symbol_map=_start=_c_int00 + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define __STACKSEAL_SIZE 8 +#else + #define __STACKSEAL_SIZE 0 +#endif + +#if defined (__ROM0_BASE) + __stack = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; + __stack_seal = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; + __stack_limit = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE; + #define __STACK_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1) + #define __STACK_LIMIT_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE) +#else + __stack = __ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - 1; + __stack_seal = __ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - 1; + __stack_limit = __ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - __STACK_SIZE; + #define __STACK_ADDR (__ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - 1) + #define __STACK_LIMIT_ADDR (__ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - __STACK_SIZE) +#endif + +MEMORY +{ +#if defined (__ROM0_BASE) + ROM0 : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE +#else + ROM0 : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE +#endif + +#if defined (__ROM1_BASE) + ROM1 : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE +#endif + +#if defined (__RAM0_BASE) + RAM0 : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE +#else + RAM0 : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE +#endif + +#if defined (__RAM1_BASE) + RAM1 : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE +#endif +} + +SECTIONS +{ +.vectors: 0x00000000 +.cinit: palign=4 {} > ROM0 +.pinit: palign=4 {} > ROM0 + +.text: palign=4 {} > ROM0 +.const: palign=4 {} > ROM0 +.rodata: palign=4 {} > ROM0 + +.data: palign=4 {} > RAM0 +.bss: type=NOINIT, palign=4 {} > RAM0 + +.stack: run=__STACK_LIMIT_ADDR, type=NOLOAD {} > RAM0 + +#if __STACKSEAL_SIZE > 0 + .stackseal: run=__STACK_ADDR, type=NOLOAD {} > RAM0 +#endif +} \ No newline at end of file diff --git a/CMSIS/CoreValidation/Layer/Target/CM33/Target.clayer.yml b/CMSIS/CoreValidation/Layer/Target/CM33/Target.clayer.yml index 7633def5e..95e16f426 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM33/Target.clayer.yml +++ b/CMSIS/CoreValidation/Layer/Target/CM33/Target.clayer.yml @@ -26,6 +26,7 @@ layer: script: RTE/Device/$Dname$/clang_linker_script.ld regions: RTE/Device/$Dname$/regions_$Dname$.h - for-compiler: CLANG_TI + script: RTE/Device/$Dname$/clang_ti_linker_script.ld regions: RTE/Device/$Dname$/regions_$Dname$.h - for-compiler: IAR script: RTE/Device/$Dname$/iar_linker_script.icf diff --git a/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33/clang_ti_linker_script.cmd b/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33/clang_ti_linker_script.cmd new file mode 100644 index 000000000..a898c464e --- /dev/null +++ b/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33/clang_ti_linker_script.cmd @@ -0,0 +1,66 @@ +--stack_size=__STACK_SIZE +--heap_size=__HEAP_SIZE +--symbol_map=_start=_c_int00 + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define __STACKSEAL_SIZE 8 +#else + #define __STACKSEAL_SIZE 0 +#endif + +#if defined (__ROM0_BASE) + __stack = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; + __stack_seal = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; + __stack_limit = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE; + #define __STACK_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1) + #define __STACK_LIMIT_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE) +#else + __stack = __ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - 1; + __stack_seal = __ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - 1; + __stack_limit = __ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - __STACK_SIZE; + #define __STACK_ADDR (__ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - 1) + #define __STACK_LIMIT_ADDR (__ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - __STACK_SIZE) +#endif + +MEMORY +{ +#if defined (__ROM0_BASE) + ROM0 : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE +#else + ROM0 : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE +#endif + +#if defined (__ROM1_BASE) + ROM1 : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE +#endif + +#if defined (__RAM0_BASE) + RAM0 : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE +#else + RAM0 : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE +#endif + +#if defined (__RAM1_BASE) + RAM1 : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE +#endif +} + +SECTIONS +{ +.vectors: 0x00000000 +.cinit: palign=4 {} > ROM0 +.pinit: palign=4 {} > ROM0 + +.text: palign=4 {} > ROM0 +.const: palign=4 {} > ROM0 +.rodata: palign=4 {} > ROM0 + +.data: palign=4 {} > RAM0 +.bss: type=NOINIT, palign=4 {} > RAM0 + +.stack: run=__STACK_LIMIT_ADDR, type=NOLOAD {} > RAM0 + +#if __STACKSEAL_SIZE > 0 + .stackseal: run=__STACK_ADDR, type=NOLOAD {} > RAM0 +#endif +} \ No newline at end of file diff --git a/CMSIS/CoreValidation/Layer/Target/CM33NS/Target.clayer.yml b/CMSIS/CoreValidation/Layer/Target/CM33NS/Target.clayer.yml index 77d7645aa..e1f829859 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM33NS/Target.clayer.yml +++ b/CMSIS/CoreValidation/Layer/Target/CM33NS/Target.clayer.yml @@ -26,6 +26,7 @@ layer: script: RTE/Device/$Dname$/clang_linker_script.ld regions: RTE/Device/$Dname$/regions_$Dname$.h - for-compiler: CLANG_TI + script: RTE/Device/$Dname$/clang_ti_linker_script.ld regions: RTE/Device/$Dname$/regions_$Dname$.h - for-compiler: IAR script: RTE/Device/$Dname$/iar_linker_script.icf diff --git a/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33/clang_ti_linker_script.cmd b/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33/clang_ti_linker_script.cmd new file mode 100644 index 000000000..a898c464e --- /dev/null +++ b/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33/clang_ti_linker_script.cmd @@ -0,0 +1,66 @@ +--stack_size=__STACK_SIZE +--heap_size=__HEAP_SIZE +--symbol_map=_start=_c_int00 + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define __STACKSEAL_SIZE 8 +#else + #define __STACKSEAL_SIZE 0 +#endif + +#if defined (__ROM0_BASE) + __stack = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; + __stack_seal = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; + __stack_limit = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE; + #define __STACK_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1) + #define __STACK_LIMIT_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE) +#else + __stack = __ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - 1; + __stack_seal = __ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - 1; + __stack_limit = __ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - __STACK_SIZE; + #define __STACK_ADDR (__ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - 1) + #define __STACK_LIMIT_ADDR (__ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - __STACK_SIZE) +#endif + +MEMORY +{ +#if defined (__ROM0_BASE) + ROM0 : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE +#else + ROM0 : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE +#endif + +#if defined (__ROM1_BASE) + ROM1 : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE +#endif + +#if defined (__RAM0_BASE) + RAM0 : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE +#else + RAM0 : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE +#endif + +#if defined (__RAM1_BASE) + RAM1 : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE +#endif +} + +SECTIONS +{ +.vectors: 0x00000000 +.cinit: palign=4 {} > ROM0 +.pinit: palign=4 {} > ROM0 + +.text: palign=4 {} > ROM0 +.const: palign=4 {} > ROM0 +.rodata: palign=4 {} > ROM0 + +.data: palign=4 {} > RAM0 +.bss: type=NOINIT, palign=4 {} > RAM0 + +.stack: run=__STACK_LIMIT_ADDR, type=NOLOAD {} > RAM0 + +#if __STACKSEAL_SIZE > 0 + .stackseal: run=__STACK_ADDR, type=NOLOAD {} > RAM0 +#endif +} \ No newline at end of file diff --git a/CMSIS/CoreValidation/Layer/Target/CM33S/Target.clayer.yml b/CMSIS/CoreValidation/Layer/Target/CM33S/Target.clayer.yml index 780b241db..9f4371219 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM33S/Target.clayer.yml +++ b/CMSIS/CoreValidation/Layer/Target/CM33S/Target.clayer.yml @@ -26,6 +26,7 @@ layer: script: RTE/Device/$Dname$/clang_linker_script.ld regions: RTE/Device/$Dname$/regions_$Dname$.h - for-compiler: CLANG_TI + script: RTE/Device/$Dname$/clang_ti_linker_script.ld regions: RTE/Device/$Dname$/regions_$Dname$.h - for-compiler: IAR script: RTE/Device/$Dname$/iar_linker_script.icf diff --git a/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/clang_ti_linker_script.cmd b/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/clang_ti_linker_script.cmd new file mode 100644 index 000000000..a898c464e --- /dev/null +++ b/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/clang_ti_linker_script.cmd @@ -0,0 +1,66 @@ +--stack_size=__STACK_SIZE +--heap_size=__HEAP_SIZE +--symbol_map=_start=_c_int00 + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define __STACKSEAL_SIZE 8 +#else + #define __STACKSEAL_SIZE 0 +#endif + +#if defined (__ROM0_BASE) + __stack = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; + __stack_seal = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; + __stack_limit = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE; + #define __STACK_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1) + #define __STACK_LIMIT_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE) +#else + __stack = __ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - 1; + __stack_seal = __ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - 1; + __stack_limit = __ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - __STACK_SIZE; + #define __STACK_ADDR (__ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - 1) + #define __STACK_LIMIT_ADDR (__ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - __STACK_SIZE) +#endif + +MEMORY +{ +#if defined (__ROM0_BASE) + ROM0 : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE +#else + ROM0 : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE +#endif + +#if defined (__ROM1_BASE) + ROM1 : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE +#endif + +#if defined (__RAM0_BASE) + RAM0 : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE +#else + RAM0 : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE +#endif + +#if defined (__RAM1_BASE) + RAM1 : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE +#endif +} + +SECTIONS +{ +.vectors: 0x00000000 +.cinit: palign=4 {} > ROM0 +.pinit: palign=4 {} > ROM0 + +.text: palign=4 {} > ROM0 +.const: palign=4 {} > ROM0 +.rodata: palign=4 {} > ROM0 + +.data: palign=4 {} > RAM0 +.bss: type=NOINIT, palign=4 {} > RAM0 + +.stack: run=__STACK_LIMIT_ADDR, type=NOLOAD {} > RAM0 + +#if __STACKSEAL_SIZE > 0 + .stackseal: run=__STACK_ADDR, type=NOLOAD {} > RAM0 +#endif +} \ No newline at end of file diff --git a/CMSIS/CoreValidation/Layer/Target/CM4/Target.clayer.yml b/CMSIS/CoreValidation/Layer/Target/CM4/Target.clayer.yml index 973d0b36e..e1764c924 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM4/Target.clayer.yml +++ b/CMSIS/CoreValidation/Layer/Target/CM4/Target.clayer.yml @@ -23,6 +23,7 @@ layer: script: RTE/Device/$Dname$/clang_linker_script.ld regions: RTE/Device/$Dname$/regions_$Dname$.h - for-compiler: CLANG_TI + script: RTE/Device/$Dname$/clang_ti_linker_script.ld regions: RTE/Device/$Dname$/regions_$Dname$.h - for-compiler: IAR script: RTE/Device/$Dname$/iar_linker_script.icf From c1c4a256ca232cf139ae806ba2bde95f4cc39403 Mon Sep 17 00:00:00 2001 From: Shawn Mason <255018043+smmasongt@users.noreply.github.com> Date: Sun, 8 Mar 2026 18:19:44 -0400 Subject: [PATCH 05/17] Correct error in Clang_TI linker file name --- .../Layer/Target/CM0/Target.clayer.yml | 2 +- .../Layer/Target/CM0plus/Target.clayer.yml | 2 +- .../Layer/Target/CM3/Target.clayer.yml | 2 +- .../Layer/Target/CM33/Target.clayer.yml | 2 +- .../Layer/Target/CM33NS/Target.clayer.yml | 2 +- .../Layer/Target/CM33S/Target.clayer.yml | 2 +- .../Layer/Target/CM4/Target.clayer.yml | 2 +- CMSIS/CoreValidation/Project/build.py | 44 ++++++++++++++----- 8 files changed, 40 insertions(+), 18 deletions(-) diff --git a/CMSIS/CoreValidation/Layer/Target/CM0/Target.clayer.yml b/CMSIS/CoreValidation/Layer/Target/CM0/Target.clayer.yml index ca971446f..b78933a17 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM0/Target.clayer.yml +++ b/CMSIS/CoreValidation/Layer/Target/CM0/Target.clayer.yml @@ -23,7 +23,7 @@ layer: script: RTE/Device/$Dname$/clang_linker_script.ld regions: RTE/Device/$Dname$/regions_$Dname$.h - for-compiler: CLANG_TI - script: RTE/Device/$Dname$/clang_ti_linker_script.ld + script: RTE/Device/$Dname$/clang_ti_linker_script.cmd regions: RTE/Device/$Dname$/regions_$Dname$.h - for-compiler: IAR script: RTE/Device/$Dname$/iar_linker_script.icf diff --git a/CMSIS/CoreValidation/Layer/Target/CM0plus/Target.clayer.yml b/CMSIS/CoreValidation/Layer/Target/CM0plus/Target.clayer.yml index a771830f4..29b021fb2 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM0plus/Target.clayer.yml +++ b/CMSIS/CoreValidation/Layer/Target/CM0plus/Target.clayer.yml @@ -23,7 +23,7 @@ layer: script: RTE/Device/$Dname$/clang_linker_script.ld regions: RTE/Device/$Dname$/regions_$Dname$.h - for-compiler: CLANG_TI - script: RTE/Device/$Dname$/clang_ti_linker_script.ld + script: RTE/Device/$Dname$/clang_ti_linker_script.cmd regions: RTE/Device/$Dname$/regions_$Dname$.h - for-compiler: IAR script: RTE/Device/$Dname$/iar_linker_script.icf diff --git a/CMSIS/CoreValidation/Layer/Target/CM3/Target.clayer.yml b/CMSIS/CoreValidation/Layer/Target/CM3/Target.clayer.yml index f9e07e31b..13e354763 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM3/Target.clayer.yml +++ b/CMSIS/CoreValidation/Layer/Target/CM3/Target.clayer.yml @@ -23,7 +23,7 @@ layer: script: RTE/Device/$Dname$/clang_linker_script.ld regions: RTE/Device/$Dname$/regions_$Dname$.h - for-compiler: CLANG_TI - script: RTE/Device/$Dname$/clang_ti_linker_script.ld + script: RTE/Device/$Dname$/clang_ti_linker_script.cmd regions: RTE/Device/$Dname$/regions_$Dname$.h - for-compiler: IAR script: RTE/Device/$Dname$/iar_linker_script.icf diff --git a/CMSIS/CoreValidation/Layer/Target/CM33/Target.clayer.yml b/CMSIS/CoreValidation/Layer/Target/CM33/Target.clayer.yml index 95e16f426..534e754e5 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM33/Target.clayer.yml +++ b/CMSIS/CoreValidation/Layer/Target/CM33/Target.clayer.yml @@ -26,7 +26,7 @@ layer: script: RTE/Device/$Dname$/clang_linker_script.ld regions: RTE/Device/$Dname$/regions_$Dname$.h - for-compiler: CLANG_TI - script: RTE/Device/$Dname$/clang_ti_linker_script.ld + script: RTE/Device/$Dname$/clang_ti_linker_script.cmd regions: RTE/Device/$Dname$/regions_$Dname$.h - for-compiler: IAR script: RTE/Device/$Dname$/iar_linker_script.icf diff --git a/CMSIS/CoreValidation/Layer/Target/CM33NS/Target.clayer.yml b/CMSIS/CoreValidation/Layer/Target/CM33NS/Target.clayer.yml index e1f829859..aabbe744c 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM33NS/Target.clayer.yml +++ b/CMSIS/CoreValidation/Layer/Target/CM33NS/Target.clayer.yml @@ -26,7 +26,7 @@ layer: script: RTE/Device/$Dname$/clang_linker_script.ld regions: RTE/Device/$Dname$/regions_$Dname$.h - for-compiler: CLANG_TI - script: RTE/Device/$Dname$/clang_ti_linker_script.ld + script: RTE/Device/$Dname$/clang_ti_linker_script.cmd regions: RTE/Device/$Dname$/regions_$Dname$.h - for-compiler: IAR script: RTE/Device/$Dname$/iar_linker_script.icf diff --git a/CMSIS/CoreValidation/Layer/Target/CM33S/Target.clayer.yml b/CMSIS/CoreValidation/Layer/Target/CM33S/Target.clayer.yml index 9f4371219..0369e70bf 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM33S/Target.clayer.yml +++ b/CMSIS/CoreValidation/Layer/Target/CM33S/Target.clayer.yml @@ -26,7 +26,7 @@ layer: script: RTE/Device/$Dname$/clang_linker_script.ld regions: RTE/Device/$Dname$/regions_$Dname$.h - for-compiler: CLANG_TI - script: RTE/Device/$Dname$/clang_ti_linker_script.ld + script: RTE/Device/$Dname$/clang_ti_linker_script.cmd regions: RTE/Device/$Dname$/regions_$Dname$.h - for-compiler: IAR script: RTE/Device/$Dname$/iar_linker_script.icf diff --git a/CMSIS/CoreValidation/Layer/Target/CM4/Target.clayer.yml b/CMSIS/CoreValidation/Layer/Target/CM4/Target.clayer.yml index e1764c924..0ba37a8e6 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM4/Target.clayer.yml +++ b/CMSIS/CoreValidation/Layer/Target/CM4/Target.clayer.yml @@ -23,7 +23,7 @@ layer: script: RTE/Device/$Dname$/clang_linker_script.ld regions: RTE/Device/$Dname$/regions_$Dname$.h - for-compiler: CLANG_TI - script: RTE/Device/$Dname$/clang_ti_linker_script.ld + script: RTE/Device/$Dname$/clang_ti_linker_script.cmd regions: RTE/Device/$Dname$/regions_$Dname$.h - for-compiler: IAR script: RTE/Device/$Dname$/iar_linker_script.icf diff --git a/CMSIS/CoreValidation/Project/build.py b/CMSIS/CoreValidation/Project/build.py index dc6c03f29..f9544c7fd 100755 --- a/CMSIS/CoreValidation/Project/build.py +++ b/CMSIS/CoreValidation/Project/build.py @@ -46,10 +46,18 @@ class DeviceAxis(Enum): CA7NEON = ('Cortex-A7neon', 'CA7neon') CA9 = ('Cortex-A9', 'CA9') CA9NEON = ('Cortex-A9neon', 'CA9neon') + CA35 = ('Cortex-A35', 'CA35') + CA35NEON = ('Cortex-A35neon', 'CA35neon') CA53 = ('Cortex-A53', 'CA53') CA53NEON = ('Cortex-A53neon', 'CA53neon') + CA55 = ('Cortex-A55', 'CA55') + CA55NEON = ('Cortex-A55neon', 'CA55neon') + CA57 = ('Cortex-A57', 'CA57') + CA57NEON = ('Cortex-A57neon', 'CA57neon') CR4 = ('Cortex-R4', 'CR4') CR5 = ('Cortex-R5', 'CR5') + CR7 = ('Cortex-R7', 'CR7') + CR8 = ('Cortex-R8', 'CR8') CR52 = ('Cortex-R52', 'CR52') CR52NEON = ('Cortex-R52neon', 'CR52neon') @@ -140,17 +148,25 @@ class OptimizationAxis(Enum): DeviceAxis.CM85S: ("FVP_MPS2_Cortex-M85", []), DeviceAxis.CM85NS: ("FVP_MPS2_Cortex-M85", []), DeviceAxis.CA5: ("FVP_VE_Cortex-A5x1", []), - DeviceAxis.CA5NEON: ("_VE_Cortex-A5x1", []), + DeviceAxis.CA5NEON: ("FVP_VE_Cortex-A5x1", []), DeviceAxis.CA7: ("FVP_VE_Cortex-A7x1", []), - DeviceAxis.CA7NEON: ("_VE_Cortex-A7x1", []), + DeviceAxis.CA7NEON: ("FVP_VE_Cortex-A7x1", []), DeviceAxis.CA9: ("FVP_VE_Cortex-A9x1", []), DeviceAxis.CA9NEON: ("_VE_Cortex-A9x1", []), - DeviceAxis.CA53: ("FVP_VE_Cortex-A53x1", []), - DeviceAxis.CA53NEON: ("_VE_Cortex-A53x1", []), - DeviceAxis.CR4: ("FVP_MPS2_Cortex-R4", []), - DeviceAxis.CR5: ("FVP_MPS2_Cortex-R5", []), - DeviceAxis.CR52: ("FVP_MPS2_Cortex-R52", []), - DeviceAxis.CR52NEON: ("_VE_MPS2_Cortex-R52", []), + DeviceAxis.CA35: ("FVP_Base_Cortex-A35", []), + DeviceAxis.CA35NEON: ("FVP_Base_Cortex-A35", []), + DeviceAxis.CA53: ("FVP_Base_Cortex-A53", []), + DeviceAxis.CA53NEON: ("FVP_Base_Cortex-A53", []), + DeviceAxis.CA55: ("FVP_Base_Cortex-A55", []), + DeviceAxis.CA55NEON: ("FVP_Base_Cortex-A55", []), + DeviceAxis.CA57: ("FVP_Base_Cortex-A57", []), + DeviceAxis.CA57NEON: ("FVP_Base_Cortex-A57", []), + DeviceAxis.CR4: ("FVP_VE_Cortex-R4", []), + DeviceAxis.CR5: ("FVP_VE_Cortex-R5x1", []), + DeviceAxis.CR7: ("FVP_VE_Cortex-R7x1", []), + DeviceAxis.CR8: ("FVP_VE_Cortex-R8x1", []), + DeviceAxis.CR52: ("FVP_BaseR_Cortex-R52", []), + DeviceAxis.CR52NEON: ("FVP_BaseR_Cortex-R52", []), } QEMU_MACHINE = { @@ -316,7 +332,7 @@ def filter_gcc_cm52(config): @matrix_filter def filter_clang_ti_supported_devices(config): device = not config.device.match('CM0') - device = not config.device.match('CM0plus') + device &= not config.device.match('CM0plus') device &= not config.device.match('CM3') device &= not config.device.match('CM4') device &= not config.device.match('CM33') @@ -326,8 +342,6 @@ def filter_clang_ti_supported_devices(config): device &= not config.device.match('CR5') device &= not config.device.match('CR52') device &= not config.device.match('CR52neon') - device &= not config.device.match('CA53') - device &= not config.device.match('CA53neon') compiler = config.compiler.match('Clang_TI') return device and compiler @@ -337,10 +351,18 @@ def filter_unsupported_devices(config): device = config.device.match('CA5neon') device |= config.device.match('CA7neon') device |= config.device.match('CA9neon') + device |= config.device.match('CA35') + device |= config.device.match('CA35neon') device |= config.device.match('CA53') device |= config.device.match('CA53neon') + device |= config.device.match('CA55') + device |= config.device.match('CA55neon') + device |= config.device.match('CA57') + device |= config.device.match('CA57neon') device |= config.device.match('CR4') device |= config.device.match('CR5') + device |= config.device.match('CR7') + device |= config.device.match('CR8') device |= config.device.match('CR52') device |= config.device.match('CR52neon') return device From 1fa93505ca8a3ab0e2ce4fd17169c22cbc422a1b Mon Sep 17 00:00:00 2001 From: Shawn Mason <255018043+smmasongt@users.noreply.github.com> Date: Mon, 9 Mar 2026 10:23:24 -0400 Subject: [PATCH 06/17] Revert updates to Core Test workflow Revert changes as these changes are in separate pull request. --- .github/workflows/core.yml | 25 ------------------------- 1 file changed, 25 deletions(-) diff --git a/.github/workflows/core.yml b/.github/workflows/core.yml index fdf3a7c3d..5bf1a4ea9 100644 --- a/.github/workflows/core.yml +++ b/.github/workflows/core.yml @@ -20,9 +20,6 @@ jobs: env: ARM_UBL_ACTIVATION_CODE: ${{ secrets.ARM_UBL_ACTIVATION_CODE }} - CLANG_TI_VERSION: "5.0.0.STS" - CLANG_TI_PATH: "~/ti_arm_cgt" - CLANG_TI_SHA256: "7a71570703f93f3682258b95d5a14a620cd6a5fc74dc5233f2d6c56d366c6da2" steps: - uses: actions/checkout@v6 @@ -55,28 +52,6 @@ jobs: - uses: ammaraskar/gcc-problem-matcher@master - - name: Cache TI Arm Clang - id: cache-ti-arm-clang - uses: actions/cache@v4 - with: - path: ${{ env.CLANG_TI_PATH }} - key: ${{ runner.os }}-ti-arm-clang-${{ env.CLANG_TI_VERSION }} - - - name: Download and Verify TI Arm Clang Installer - if: steps.cache-ti-arm-clang.outputs.cache-hit != 'true' - run: | - FILE="ti_cgt_armllvm_${{ env.CLANG_TI_VERSION }}_linux-x64_installer.bin" - URL="https://dr-download.ti.com/software-development/ide-configuration-compiler-or-debugger/MD-ayxs93eZNN/${{ env.CLANG_TI_VERSION }}/${FILE}" - - curl -L "$URL" -o "$FILE" - echo "${{ env.CLANG_TI_SHA256 }} $FILE" | sha256sum --check - chmod +x "$FILE" - ./"$FILE" --mode unattended --prefix "${{ env.CLANG_TI_PATH }}" - - - name: Set TI Arm Clang Environment Variable - run: | - echo "CLANG_TI_TOOLCHAIN_${{ env.CLANG_TI_VERSION }}=${{ env.CLANG_TI_PATH }}/bin" >> $GITHUB_ENV - - name: Run LIT working-directory: ./CMSIS/Core/Test run: | From ef3b4f3f2e71f3410a7aaf0bdd1f47754f690357 Mon Sep 17 00:00:00 2001 From: Shawn Mason <255018043+smmasongt@users.noreply.github.com> Date: Sun, 29 Mar 2026 14:09:20 -0400 Subject: [PATCH 07/17] Address issues with semihosting and CMSE in Clang TI Compiler tests. --- .github/workflows/corevalidation.yml | 8 +- .../App/Bootloader_Cortex-M/App.clayer.yml | 6 + .../App/Validation_Cortex-M/App.clayer.yml | 8 + .../Device/ARMCM0/clang_ti_linker_script.cmd | 42 +- .../Device/ARMCM0P/clang_ti_linker_script.cmd | 42 +- .../Device/ARMCM3/clang_ti_linker_script.cmd | 42 +- .../Device/ARMCM33/clang_ti_linker_script.cmd | 42 +- .../Device/ARMCM33/clang_ti_linker_script.cmd | 42 +- .../Device/ARMCM33/clang_ti_linker_script.cmd | 42 +- .../Device/ARMCM4/clang_ti_linker_script.cmd | 42 +- .../Project/Validation.csolution.yml | 5 +- CMSIS/CoreValidation/Project/build.py | 14 +- CMSIS/CoreValidation/README.md | 8 +- CMSIS/CoreValidation/Source/CV_Framework.c | 13 + CMSIS/CoreValidation/Source/CV_Report.c | 7 + .../clang_ti_fastmodel_cio.c | 81 ++++ .../clang_ti_format_semihost.h | 134 +++++++ .../Clang_TI_Semihost/clang_ti_semihost.c | 371 ++++++++++++++++++ .../Clang_TI_Semihost/clang_ti_semihost.h | 61 +++ .../clang_ti_semihost_call.h | 43 ++ .../clang_ti_vprintf_semihost.c | 96 +++++ .../clang_ti_vprintf_semihost.h | 20 + 22 files changed, 957 insertions(+), 212 deletions(-) create mode 100644 CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_fastmodel_cio.c create mode 100644 CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_format_semihost.h create mode 100644 CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_semihost.c create mode 100644 CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_semihost.h create mode 100644 CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_semihost_call.h create mode 100644 CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_vprintf_semihost.c create mode 100644 CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_vprintf_semihost.h diff --git a/.github/workflows/corevalidation.yml b/.github/workflows/corevalidation.yml index 90815999f..a2c1a74c2 100644 --- a/.github/workflows/corevalidation.yml +++ b/.github/workflows/corevalidation.yml @@ -27,10 +27,10 @@ jobs: env: ARM_UBL_ACTIVATION_CODE: ${{ secrets.ARM_UBL_ACTIVATION_CODE }} - CLANG_TI_VERSION: "5.0.0.STS" - CLANG_TI_TC_SUFFIX: "5_0_0" + CLANG_TI_VERSION: "5.1.0.LTS" + CLANG_TI_TC_SUFFIX: "5_1_0" CLANG_TI_INSTALL_PATH: "/home/runner/" - CLANG_TI_SHA256: "7a71570703f93f3682258b95d5a14a620cd6a5fc74dc5233f2d6c56d366c6da2" + CLANG_TI_SHA256: "c758668b78c080be5ec75393cdd09d077742fd1183aa0c181318a0119d58c4d0" steps: - run: | @@ -126,7 +126,7 @@ jobs: - name: Execute working-directory: ./CMSIS/CoreValidation/Project - run: | + run: | echo "Run test projects ..." ./build.py --verbose -c ${{ matrix.compiler }} -d "CM*" run || echo "::warning::==== Some configurations failed to run! ===" diff --git a/CMSIS/CoreValidation/Layer/App/Bootloader_Cortex-M/App.clayer.yml b/CMSIS/CoreValidation/Layer/App/Bootloader_Cortex-M/App.clayer.yml index 8e154b9eb..8cfa71cca 100644 --- a/CMSIS/CoreValidation/Layer/App/Bootloader_Cortex-M/App.clayer.yml +++ b/CMSIS/CoreValidation/Layer/App/Bootloader_Cortex-M/App.clayer.yml @@ -5,6 +5,12 @@ layer: # packs: # - pack: ARM::CMSIS + misc: + - for-compiler: CLANG_TI + Link: + # Reference TI Arm Clang Compiler ToolUser's Guide, v5.1, Section 6 Cortex-M Security Extensions (CMSE) + - -Xlinker --import_cmse_lib_out=implib.o + groups: - group: Source Files files: diff --git a/CMSIS/CoreValidation/Layer/App/Validation_Cortex-M/App.clayer.yml b/CMSIS/CoreValidation/Layer/App/Validation_Cortex-M/App.clayer.yml index b5604dc12..941639499 100644 --- a/CMSIS/CoreValidation/Layer/App/Validation_Cortex-M/App.clayer.yml +++ b/CMSIS/CoreValidation/Layer/App/Validation_Cortex-M/App.clayer.yml @@ -11,6 +11,7 @@ layer: add-path: - ../../../Include - ../../../Source/Config + - ../../../Source/Clang_TI_Semihost misc: - for-compiler: AC6 @@ -69,3 +70,10 @@ layer: files: - file: ../../../Source/CV_Framework.c - file: ../../../Source/CV_Report.c + + - group: TI Arm Clang Compiler Semihost Support + for-compiler: CLANG_TI + files: + - file: ../../../Source/Clang_TI_Semihost/clang_ti_fastmodel_cio.c + - file: ../../../Source/Clang_TI_Semihost/clang_ti_semihost.c + - file: ../../../Source/Clang_TI_Semihost/clang_ti_vprintf_semihost.c \ No newline at end of file diff --git a/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/clang_ti_linker_script.cmd b/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/clang_ti_linker_script.cmd index a898c464e..4ae39a49f 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/clang_ti_linker_script.cmd +++ b/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/clang_ti_linker_script.cmd @@ -8,37 +8,21 @@ #define __STACKSEAL_SIZE 0 #endif -#if defined (__ROM0_BASE) - __stack = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; - __stack_seal = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; - __stack_limit = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE; - #define __STACK_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1) - #define __STACK_LIMIT_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE) -#else - __stack = __ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - 1; - __stack_seal = __ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - 1; - __stack_limit = __ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - __STACK_SIZE; - #define __STACK_ADDR (__ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - 1) - #define __STACK_LIMIT_ADDR (__ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - __STACK_SIZE) -#endif +__stack = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; +__stack_seal = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; +__stack_limit = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE; +#define __STACK_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1) +#define __STACK_LIMIT_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE) MEMORY { -#if defined (__ROM0_BASE) - ROM0 : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE -#else - ROM0 : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE -#endif +ROM0 : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE #if defined (__ROM1_BASE) ROM1 : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE #endif -#if defined (__RAM0_BASE) - RAM0 : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE -#else - RAM0 : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -#endif +RAM0 : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE #if defined (__RAM1_BASE) RAM1 : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE @@ -47,20 +31,22 @@ MEMORY SECTIONS { -.vectors: 0x00000000 -.cinit: palign=4 {} > ROM0 -.pinit: palign=4 {} > ROM0 +.vectors: {} > 0x00000000 .text: palign=4 {} > ROM0 -.const: palign=4 {} > ROM0 .rodata: palign=4 {} > ROM0 +.noinit: palign=4 {} > RAM0 .data: palign=4 {} > RAM0 +.sysmem: palign=4 {} > RAM0 .bss: type=NOINIT, palign=4 {} > RAM0 .stack: run=__STACK_LIMIT_ADDR, type=NOLOAD {} > RAM0 - #if __STACKSEAL_SIZE > 0 .stackseal: run=__STACK_ADDR, type=NOLOAD {} > RAM0 #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + Veneer$$CMSE: palign=8 {} > ROM1 +#endif } \ No newline at end of file diff --git a/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/clang_ti_linker_script.cmd b/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/clang_ti_linker_script.cmd index a898c464e..4ae39a49f 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/clang_ti_linker_script.cmd +++ b/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/clang_ti_linker_script.cmd @@ -8,37 +8,21 @@ #define __STACKSEAL_SIZE 0 #endif -#if defined (__ROM0_BASE) - __stack = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; - __stack_seal = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; - __stack_limit = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE; - #define __STACK_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1) - #define __STACK_LIMIT_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE) -#else - __stack = __ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - 1; - __stack_seal = __ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - 1; - __stack_limit = __ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - __STACK_SIZE; - #define __STACK_ADDR (__ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - 1) - #define __STACK_LIMIT_ADDR (__ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - __STACK_SIZE) -#endif +__stack = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; +__stack_seal = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; +__stack_limit = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE; +#define __STACK_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1) +#define __STACK_LIMIT_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE) MEMORY { -#if defined (__ROM0_BASE) - ROM0 : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE -#else - ROM0 : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE -#endif +ROM0 : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE #if defined (__ROM1_BASE) ROM1 : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE #endif -#if defined (__RAM0_BASE) - RAM0 : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE -#else - RAM0 : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -#endif +RAM0 : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE #if defined (__RAM1_BASE) RAM1 : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE @@ -47,20 +31,22 @@ MEMORY SECTIONS { -.vectors: 0x00000000 -.cinit: palign=4 {} > ROM0 -.pinit: palign=4 {} > ROM0 +.vectors: {} > 0x00000000 .text: palign=4 {} > ROM0 -.const: palign=4 {} > ROM0 .rodata: palign=4 {} > ROM0 +.noinit: palign=4 {} > RAM0 .data: palign=4 {} > RAM0 +.sysmem: palign=4 {} > RAM0 .bss: type=NOINIT, palign=4 {} > RAM0 .stack: run=__STACK_LIMIT_ADDR, type=NOLOAD {} > RAM0 - #if __STACKSEAL_SIZE > 0 .stackseal: run=__STACK_ADDR, type=NOLOAD {} > RAM0 #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + Veneer$$CMSE: palign=8 {} > ROM1 +#endif } \ No newline at end of file diff --git a/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/clang_ti_linker_script.cmd b/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/clang_ti_linker_script.cmd index a898c464e..4ae39a49f 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/clang_ti_linker_script.cmd +++ b/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/clang_ti_linker_script.cmd @@ -8,37 +8,21 @@ #define __STACKSEAL_SIZE 0 #endif -#if defined (__ROM0_BASE) - __stack = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; - __stack_seal = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; - __stack_limit = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE; - #define __STACK_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1) - #define __STACK_LIMIT_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE) -#else - __stack = __ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - 1; - __stack_seal = __ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - 1; - __stack_limit = __ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - __STACK_SIZE; - #define __STACK_ADDR (__ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - 1) - #define __STACK_LIMIT_ADDR (__ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - __STACK_SIZE) -#endif +__stack = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; +__stack_seal = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; +__stack_limit = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE; +#define __STACK_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1) +#define __STACK_LIMIT_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE) MEMORY { -#if defined (__ROM0_BASE) - ROM0 : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE -#else - ROM0 : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE -#endif +ROM0 : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE #if defined (__ROM1_BASE) ROM1 : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE #endif -#if defined (__RAM0_BASE) - RAM0 : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE -#else - RAM0 : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -#endif +RAM0 : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE #if defined (__RAM1_BASE) RAM1 : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE @@ -47,20 +31,22 @@ MEMORY SECTIONS { -.vectors: 0x00000000 -.cinit: palign=4 {} > ROM0 -.pinit: palign=4 {} > ROM0 +.vectors: {} > 0x00000000 .text: palign=4 {} > ROM0 -.const: palign=4 {} > ROM0 .rodata: palign=4 {} > ROM0 +.noinit: palign=4 {} > RAM0 .data: palign=4 {} > RAM0 +.sysmem: palign=4 {} > RAM0 .bss: type=NOINIT, palign=4 {} > RAM0 .stack: run=__STACK_LIMIT_ADDR, type=NOLOAD {} > RAM0 - #if __STACKSEAL_SIZE > 0 .stackseal: run=__STACK_ADDR, type=NOLOAD {} > RAM0 #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + Veneer$$CMSE: palign=8 {} > ROM1 +#endif } \ No newline at end of file diff --git a/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33/clang_ti_linker_script.cmd b/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33/clang_ti_linker_script.cmd index a898c464e..4ae39a49f 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33/clang_ti_linker_script.cmd +++ b/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33/clang_ti_linker_script.cmd @@ -8,37 +8,21 @@ #define __STACKSEAL_SIZE 0 #endif -#if defined (__ROM0_BASE) - __stack = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; - __stack_seal = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; - __stack_limit = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE; - #define __STACK_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1) - #define __STACK_LIMIT_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE) -#else - __stack = __ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - 1; - __stack_seal = __ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - 1; - __stack_limit = __ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - __STACK_SIZE; - #define __STACK_ADDR (__ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - 1) - #define __STACK_LIMIT_ADDR (__ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - __STACK_SIZE) -#endif +__stack = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; +__stack_seal = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; +__stack_limit = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE; +#define __STACK_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1) +#define __STACK_LIMIT_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE) MEMORY { -#if defined (__ROM0_BASE) - ROM0 : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE -#else - ROM0 : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE -#endif +ROM0 : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE #if defined (__ROM1_BASE) ROM1 : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE #endif -#if defined (__RAM0_BASE) - RAM0 : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE -#else - RAM0 : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -#endif +RAM0 : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE #if defined (__RAM1_BASE) RAM1 : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE @@ -47,20 +31,22 @@ MEMORY SECTIONS { -.vectors: 0x00000000 -.cinit: palign=4 {} > ROM0 -.pinit: palign=4 {} > ROM0 +.vectors: {} > 0x00000000 .text: palign=4 {} > ROM0 -.const: palign=4 {} > ROM0 .rodata: palign=4 {} > ROM0 +.noinit: palign=4 {} > RAM0 .data: palign=4 {} > RAM0 +.sysmem: palign=4 {} > RAM0 .bss: type=NOINIT, palign=4 {} > RAM0 .stack: run=__STACK_LIMIT_ADDR, type=NOLOAD {} > RAM0 - #if __STACKSEAL_SIZE > 0 .stackseal: run=__STACK_ADDR, type=NOLOAD {} > RAM0 #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + Veneer$$CMSE: palign=8 {} > ROM1 +#endif } \ No newline at end of file diff --git a/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33/clang_ti_linker_script.cmd b/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33/clang_ti_linker_script.cmd index a898c464e..4ae39a49f 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33/clang_ti_linker_script.cmd +++ b/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33/clang_ti_linker_script.cmd @@ -8,37 +8,21 @@ #define __STACKSEAL_SIZE 0 #endif -#if defined (__ROM0_BASE) - __stack = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; - __stack_seal = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; - __stack_limit = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE; - #define __STACK_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1) - #define __STACK_LIMIT_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE) -#else - __stack = __ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - 1; - __stack_seal = __ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - 1; - __stack_limit = __ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - __STACK_SIZE; - #define __STACK_ADDR (__ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - 1) - #define __STACK_LIMIT_ADDR (__ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - __STACK_SIZE) -#endif +__stack = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; +__stack_seal = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; +__stack_limit = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE; +#define __STACK_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1) +#define __STACK_LIMIT_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE) MEMORY { -#if defined (__ROM0_BASE) - ROM0 : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE -#else - ROM0 : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE -#endif +ROM0 : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE #if defined (__ROM1_BASE) ROM1 : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE #endif -#if defined (__RAM0_BASE) - RAM0 : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE -#else - RAM0 : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -#endif +RAM0 : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE #if defined (__RAM1_BASE) RAM1 : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE @@ -47,20 +31,22 @@ MEMORY SECTIONS { -.vectors: 0x00000000 -.cinit: palign=4 {} > ROM0 -.pinit: palign=4 {} > ROM0 +.vectors: {} > 0x00000000 .text: palign=4 {} > ROM0 -.const: palign=4 {} > ROM0 .rodata: palign=4 {} > ROM0 +.noinit: palign=4 {} > RAM0 .data: palign=4 {} > RAM0 +.sysmem: palign=4 {} > RAM0 .bss: type=NOINIT, palign=4 {} > RAM0 .stack: run=__STACK_LIMIT_ADDR, type=NOLOAD {} > RAM0 - #if __STACKSEAL_SIZE > 0 .stackseal: run=__STACK_ADDR, type=NOLOAD {} > RAM0 #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + Veneer$$CMSE: palign=8 {} > ROM1 +#endif } \ No newline at end of file diff --git a/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33/clang_ti_linker_script.cmd b/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33/clang_ti_linker_script.cmd index a898c464e..4ae39a49f 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33/clang_ti_linker_script.cmd +++ b/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33/clang_ti_linker_script.cmd @@ -8,37 +8,21 @@ #define __STACKSEAL_SIZE 0 #endif -#if defined (__ROM0_BASE) - __stack = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; - __stack_seal = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; - __stack_limit = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE; - #define __STACK_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1) - #define __STACK_LIMIT_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE) -#else - __stack = __ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - 1; - __stack_seal = __ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - 1; - __stack_limit = __ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - __STACK_SIZE; - #define __STACK_ADDR (__ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - 1) - #define __STACK_LIMIT_ADDR (__ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - __STACK_SIZE) -#endif +__stack = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; +__stack_seal = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; +__stack_limit = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE; +#define __STACK_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1) +#define __STACK_LIMIT_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE) MEMORY { -#if defined (__ROM0_BASE) - ROM0 : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE -#else - ROM0 : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE -#endif +ROM0 : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE #if defined (__ROM1_BASE) ROM1 : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE #endif -#if defined (__RAM0_BASE) - RAM0 : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE -#else - RAM0 : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -#endif +RAM0 : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE #if defined (__RAM1_BASE) RAM1 : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE @@ -47,20 +31,22 @@ MEMORY SECTIONS { -.vectors: 0x00000000 -.cinit: palign=4 {} > ROM0 -.pinit: palign=4 {} > ROM0 +.vectors: {} > 0x00000000 .text: palign=4 {} > ROM0 -.const: palign=4 {} > ROM0 .rodata: palign=4 {} > ROM0 +.noinit: palign=4 {} > RAM0 .data: palign=4 {} > RAM0 +.sysmem: palign=4 {} > RAM0 .bss: type=NOINIT, palign=4 {} > RAM0 .stack: run=__STACK_LIMIT_ADDR, type=NOLOAD {} > RAM0 - #if __STACKSEAL_SIZE > 0 .stackseal: run=__STACK_ADDR, type=NOLOAD {} > RAM0 #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + Veneer$$CMSE: palign=8 {} > ROM1 +#endif } \ No newline at end of file diff --git a/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/clang_ti_linker_script.cmd b/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/clang_ti_linker_script.cmd index a898c464e..4ae39a49f 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/clang_ti_linker_script.cmd +++ b/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/clang_ti_linker_script.cmd @@ -8,37 +8,21 @@ #define __STACKSEAL_SIZE 0 #endif -#if defined (__ROM0_BASE) - __stack = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; - __stack_seal = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; - __stack_limit = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE; - #define __STACK_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1) - #define __STACK_LIMIT_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE) -#else - __stack = __ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - 1; - __stack_seal = __ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - 1; - __stack_limit = __ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - __STACK_SIZE; - #define __STACK_ADDR (__ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - 1) - #define __STACK_LIMIT_ADDR (__ROM_BASE + __ROM_SIZE - __STACKSEAL_SIZE - __STACK_SIZE) -#endif +__stack = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; +__stack_seal = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; +__stack_limit = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE; +#define __STACK_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1) +#define __STACK_LIMIT_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE) MEMORY { -#if defined (__ROM0_BASE) - ROM0 : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE -#else - ROM0 : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE -#endif +ROM0 : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE #if defined (__ROM1_BASE) ROM1 : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE #endif -#if defined (__RAM0_BASE) - RAM0 : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE -#else - RAM0 : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -#endif +RAM0 : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE #if defined (__RAM1_BASE) RAM1 : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE @@ -47,20 +31,22 @@ MEMORY SECTIONS { -.vectors: 0x00000000 -.cinit: palign=4 {} > ROM0 -.pinit: palign=4 {} > ROM0 +.vectors: {} > 0x00000000 .text: palign=4 {} > ROM0 -.const: palign=4 {} > ROM0 .rodata: palign=4 {} > ROM0 +.noinit: palign=4 {} > RAM0 .data: palign=4 {} > RAM0 +.sysmem: palign=4 {} > RAM0 .bss: type=NOINIT, palign=4 {} > RAM0 .stack: run=__STACK_LIMIT_ADDR, type=NOLOAD {} > RAM0 - #if __STACKSEAL_SIZE > 0 .stackseal: run=__STACK_ADDR, type=NOLOAD {} > RAM0 #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + Veneer$$CMSE: palign=8 {} > ROM1 +#endif } \ No newline at end of file diff --git a/CMSIS/CoreValidation/Project/Validation.csolution.yml b/CMSIS/CoreValidation/Project/Validation.csolution.yml index 185969f28..4c31eefaf 100644 --- a/CMSIS/CoreValidation/Project/Validation.csolution.yml +++ b/CMSIS/CoreValidation/Project/Validation.csolution.yml @@ -16,6 +16,9 @@ solution: - for-compiler: IAR Link: - --semihosting + - for-compiler: CLANG_TI + Link: + - -Xlinker --map_file=map.txt packs: - pack: ARM::CMSIS @@ -145,7 +148,6 @@ solution: debug: on projects: - - project: ./Validation/Validation.cproject.yml - project: ./Bootloader/Bootloader.cproject.yml for-context: - +CM23NS @@ -154,6 +156,7 @@ solution: - +CM52NS - +CM55NS - +CM85NS + - project: ./Validation/Validation.cproject.yml output-dirs: cprjdir: ./build/$TargetType$/$Compiler$/$BuildType$/$Project$ diff --git a/CMSIS/CoreValidation/Project/build.py b/CMSIS/CoreValidation/Project/build.py index f9544c7fd..e6b80cdfe 100755 --- a/CMSIS/CoreValidation/Project/build.py +++ b/CMSIS/CoreValidation/Project/build.py @@ -184,22 +184,22 @@ def config_suffix(config, timestamp=True): return suffix -def project_name(config): - return f"Validation.{config.compiler}_{config.optimize}+{config.device[1]}" - - def bl_project_name(config): return f"Bootloader.{config.compiler}_{config.optimize}+{config.device.bl_device}" -def output_dir(config): - return f"Validation/outdir" +def project_name(config): + return f"Validation.{config.compiler}_{config.optimize}+{config.device[1]}" def bl_output_dir(config): return f"Bootloader/outdir" +def output_dir(config): + return f"Validation/outdir" + + def model_config(config): return f"../Layer/Target/{config.device[1]}/model_config.txt" @@ -297,9 +297,9 @@ def cbuild(config): def model_exec(config): cmdline = [MODEL_EXECUTABLE[config.device][0], "-q", "--simlimit", 100, "-f", model_config(config)] cmdline += MODEL_EXECUTABLE[config.device][1] - cmdline += ["-a", f"{build_dir(config)}/{output_dir(config)}/Validation.{config.compiler.image_ext}"] if config.device.has_bl(): cmdline += ["-a", f"{build_dir(config)}/{bl_output_dir(config)}/Bootloader.{config.compiler.image_ext}"] + cmdline += ["-a", f"{build_dir(config)}/{output_dir(config)}/Validation.{config.compiler.image_ext}"] return cmdline diff --git a/CMSIS/CoreValidation/README.md b/CMSIS/CoreValidation/README.md index fb7f02a0a..ce3e459d1 100644 --- a/CMSIS/CoreValidation/README.md +++ b/CMSIS/CoreValidation/README.md @@ -20,7 +20,7 @@ Currently, the following build configurations are provided: - Arm Compiler 6 (AC6) - GNU Compiler (GCC) - LLVM/Clang (Clang) - - TI Arm Clang (Clang_TI) (CM0/0+/3/4) + - TI Arm Clang (Clang_TI) (CM0/0+/3/4/33/33S) 2. Devices - Cortex-M0 - Cortex-M0+ @@ -69,7 +69,7 @@ The following tools are required to build and run the CoreValidation tests: - [Arm Compiler 6.20](https://artifacts.keil.arm.com/arm-compiler/6.20/21/)* - [GCC Compiler 13.2.1](https://artifacts.keil.arm.com/arm-none-eabi-gcc/13.2.1/)* - [Clang Compiler 17.0.1](https://github.com/ARM-software/LLVM-embedded-toolchain-for-Arm/releases/tag/release-17.0.1)* -- [TI Arm Clang Compiler 5.0.0](https://www.ti.com/tool/download/ARM-CGT-CLANG) +- [TI Arm Clang Compiler 5.1.0](https://www.ti.com/tool/download/ARM-CGT-CLANG) - [Arm Virtual Hardware for Cortex-M based on FastModels 11.22.39](https://artifacts.keil.arm.com/avh/11.22.39/)* - [Python 3.9](https://www.python.org/downloads/) @@ -105,8 +105,8 @@ For example, build and run the tests using GCC for Cortex-M3 with low optimizati [GCC][Cortex-M3][none](build:csolution) csolution succeeded with exit code 0 [GCC][Cortex-M3][none](build:cbuild) cbuild Validation.GCC_low+CM3/Validation.GCC_low+CM3.cprj [GCC][Cortex-M3][none](build:cbuild) cbuild succeeded with exit code 0 -[GCC][Cortex-M3][none](run:model_exec) VHT_MPS2_Cortex-M3 -q --simlimit 100 -f ../Layer/Target/CM3/model_config.txt -a Validation.GCC_low+CM3/Validation.GCC_low+CM3_outdir/Validation.GCC_low+CM3.elf -[GCC][Cortex-M3][none](run:model_exec) VHT_MPS2_Cortex-M3 succeeded with exit code 0 +[GCC][Cortex-M3][none](run:model_exec) FVP_MPS2_Cortex-M3 -q --simlimit 100 -f ../Layer/Target/CM3/model_config.txt -a Validation.GCC_low+CM3/Validation.GCC_low+CM3_outdir/Validation.GCC_low+CM3.elf +[GCC][Cortex-M3][none](run:model_exec) FVP_MPS2_Cortex-M3 succeeded with exit code 0 Matrix Summary ============== diff --git a/CMSIS/CoreValidation/Source/CV_Framework.c b/CMSIS/CoreValidation/Source/CV_Framework.c index 112c82866..7eacbe5d2 100644 --- a/CMSIS/CoreValidation/Source/CV_Framework.c +++ b/CMSIS/CoreValidation/Source/CV_Framework.c @@ -6,6 +6,11 @@ *----------------------------------------------------------------------------*/ #include "CV_Framework.h" #include "cmsis_cv.h" +#if defined(__clang__) && defined(__ti__) +#include "clang_ti_semihost.h" +/* Declare the initialization routine provided in clang_ti_semihost.c */ +extern void _system_post_cinit(void); +#endif /* Prototypes */ void ts_cmsis_cv(void); @@ -27,6 +32,9 @@ void closeDebug(void); Debug session dead end - debug script should close session here. */ void closeDebug(void) { +#if defined(__clang__) && defined(__ti__) + ARMSemihost_exit(); +#endif __NOP(); // Test completed } @@ -83,6 +91,11 @@ Program flow: */ void cmsis_cv (void) { +#if defined(__clang__) && defined(__ti__) + /* Initialize semihosting file descriptors for STDOUT/STDERR */ + _system_post_cinit(); +#endif + /* Init test suite */ if (ts.Init != NULL) { ts.Init(); /* Init hardware */ diff --git a/CMSIS/CoreValidation/Source/CV_Report.c b/CMSIS/CoreValidation/Source/CV_Report.c index 3fa2d2382..2156836e0 100644 --- a/CMSIS/CoreValidation/Source/CV_Report.c +++ b/CMSIS/CoreValidation/Source/CV_Report.c @@ -7,6 +7,9 @@ #include "CV_Report.h" #include #include +#if defined(__clang__) && defined(__ti__) +#include "clang_ti_vprintf_semihost.h" +#endif TEST_REPORT test_report; static AS_STAT current_assertions; /* Current test case assertions statistics */ @@ -380,7 +383,11 @@ static void MsgFlush(void) { static void MsgPrint (const char *msg, ...) { va_list args; va_start(args, msg); +#if defined(__clang__) && defined(__ti__) + clang_ti_vprintf_semihost(msg, args); +#else vprintf(msg, args); +#endif va_end(args); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) diff --git a/CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_fastmodel_cio.c b/CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_fastmodel_cio.c new file mode 100644 index 000000000..e9c4789a8 --- /dev/null +++ b/CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_fastmodel_cio.c @@ -0,0 +1,81 @@ +/*****************************************************************************/ +/* FASTMODEL_CIO.C v##### - Setup Arm FastModel as standard device for CIO */ +/* Copyright (c) 2024@%%%% Texas Instruments Incorporated */ +/*****************************************************************************/ +/*****************************************************************************/ +/* CLANG_TI_FASTMODEL_CIO.C */ +/*****************************************************************************/ + +#include +#include +#include +#include +#include +#include "semihost.h" + +//---------------------------------------------------------------------------- +// __FM_INIT - SET RESET VECTOR AND SVC STATE REQUIRED BY SVC SEMIHOSTING. +//---------------------------------------------------------------------------- +__attribute__((naked,retain)) +void __FM_init() +{ +#if __ARM_ARCH_8R__ == 1 + __asm volatile( + "MRS r0, cpsr\n" + "MOV r1, #0x13\n" // SET SVC MODE + "BFI r0, r1, #0, #5\n" + "MSR spsr_cxsf, r0\n" + "LDR r0, =_c_int00\n" // Force reset vector to _c_int00 + "MSR elr_hyp, r0\n" + "DSB\n" + "ISB\n" + "ERET\n" + ); +#else + __asm volatile( + "b _c_int00\n" + ); +#endif +} + +//---------------------------------------------------------------------------- +// PARSE_CMDLINE - PARSE THE FASTMODELS SIMULATOR COMMAND LINE FOR ARGUMENTS. +// +// The script that invokes the simulator passes a command line argument to the +// simulator containing the arguments in the form of a space-separated string +// in which the first string is the value of argc: "argc arg0 arg1 ...". It +// passes this using '-C Dhrystone.Core.cpu0.semihosting-cmd_line="${ENVPATH} +// $# ${ARGS}"'.This function is responsible for tokenizing argc and the +// arguments and copying them into the memory location of __c_args__. +//---------------------------------------------------------------------------- +void parse_cmdline(ARGS *pargs, char* buf, char *env) +{ + uint32_t argv_addr = (uint32_t)pargs->argv; + + // Tokenize the command line. + char* token = strtok(buf, " "); + if (token) + { + // CODEGEN-12869: The first token is ENV. + strncpy(env, token, strlen(token) + 1); + token = strtok(NULL," "); + + // The second token is ARGC. + pargs->argc = atoi(token); + + uint32_t aptr = argv_addr + (4 * (pargs->argc + 1)); + + // Process and copy the argvs. + int i = 0; + char *arg = strtok(NULL, " "); + while (arg != NULL) { + memcpy((void*)(argv_addr + i++ * 4), (unsigned char*)&aptr, 4); + + size_t len = strlen(arg) + 1; + strncpy((char*)aptr, (char*)arg, len); + aptr += len; + + arg = strtok(NULL, " "); + } + } +} diff --git a/CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_format_semihost.h b/CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_format_semihost.h new file mode 100644 index 000000000..50e09a1ff --- /dev/null +++ b/CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_format_semihost.h @@ -0,0 +1,134 @@ +/*****************************************************************************/ +/* FORMAT.H */ +/* */ +/* Copyright (c) 1995 Texas Instruments Incorporated */ +/* http://www.ti.com/ */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in */ +/* the documentation and/or other materials provided with the */ +/* distribution. */ +/* */ +/* Neither the name of Texas Instruments Incorporated nor the names */ +/* of its contributors may be used to endorse or promote products */ +/* derived from this software without specific prior written */ +/* permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ +/* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ +/* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ +/* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ +/* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ +/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ +/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ +/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ +/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ +/* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Structures and macros used in printf and scanf */ +/*****************************************************************************/ +#ifndef __CLANG_TI_FORMAT_SEMIHOST_H +#define __CLANG_TI_FORMAT_SEMIHOST_H +#include + +#if defined (MINIMAL) +#define FORMAT_CONVERSION_BUFSIZE 32 +#elif defined (__MSP430__) +#define F_CONVERSION_BUFSIZE 100 +#define FLOAT_VALUE_BUFSIZE 32 +#else +/****************************************************************************/ +/* The minimum max conversion size to be C89 compliant is 509 */ +/****************************************************************************/ +#define F_CONVERSION_BUFSIZE 510 +#define FLOAT_VALUE_BUFSIZE 100 +#endif + +#if !defined(MINIMAL) +#define FORMAT_CONVERSION_BUFSIZE F_CONVERSION_BUFSIZE +#endif + + int __TI_scanfi(void *inp, const char *_format, va_list _ap, + int (*_chkmbc)(void **inp, char **_format, int *num_read), + int (*_inpchar)(void **inp), + void (*_uninpchar)(void **inp, int outchar)); + + /**************************************************************************/ + /* _FIELD STRUCTURE AND MACROS USED FOR PRINTF AND SCANF */ + /**************************************************************************/ + typedef struct { + unsigned int flags; /* Format flags */ + int fwidth; /* Field width */ + int precision; /* Field precision */ + char conv; /* Conversion specifier */ +#if defined(VECTOR_PRINTF_SUPPORT) + int vn; /* Vector size expressed in the format */ + /*************************************************************************/ + /* CODEGEN-4880: WORKAROUND */ + /*************************************************************************/ + /* The variables below are required to handle a special case for */ + /* char2 or uchar2 arguments. Explanation given in _pproc_v_dioux */ + /*************************************************************************/ + uchar2 arguc2; + int arguc2_leftover; + int last_v_dioux_arg_size; + /*************************************************************************/ + /* CODEGEN-4880: WORKAROUND END */ + /*************************************************************************/ +#endif + } _PFIELD; + + typedef struct { + unsigned int flags; /* Format flags */ + int fwidth; /* Field width */ + int precision; /* Field precision */ + char scanset[96]; /* Scanset used for '[' conversion */ + char conv; /* Conversion specifier */ + } _SFIELD; + +/****************/ +/* PRINTF FLAGS */ +/****************/ + +#define _PFMINUS 0x01 +#define _PFPLUS 0x02 +#define _PFSPACE 0x04 +#define _PFPOUND 0x08 +#define _PFZERO 0x10 + +/***************/ +/* SCANF FLAGS */ +/***************/ + +#define _SFSTAR 0x01 +#define _SFCIRC 0x02 + +/****************/ +/* MUTUAL FLAGS */ +/****************/ + +#define _MFH 0x20 +#define _MFL 0x40 +#define _MFLD 0x80 +#define _MFLL 0x100 +#define _MFHH 0x200 +#define _MFI40 0x400 +#define _MFJ 0x800 +#define _MFZ 0x1000 +#define _MFT 0x2000 +#if defined(VECTOR_PRINTF_SUPPORT) +#define _MFHL 0x3000 /* OpenCL 1.2 vector specifier flag */ +#endif + +#endif \ No newline at end of file diff --git a/CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_semihost.c b/CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_semihost.c new file mode 100644 index 000000000..1ac2c42eb --- /dev/null +++ b/CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_semihost.c @@ -0,0 +1,371 @@ +/*****************************************************************************/ +/* SEMIHOST.C v##### - Generic C functions for interfacing with simulators */ +/* that support ARM-conformant semihosting */ +/* Copyright (c) 2024@%%%% Texas Instruments Incorporated */ +/*****************************************************************************/ +/*****************************************************************************/ +/* CLANG_TI_SEMIHOST.C - Generic C functions for interfacing with */ +/* simulators that support ARM-conformant semihosting */ +/*****************************************************************************/ +#include +#include +#include +#include +#include +#include // This is a standard header, no need to rename. +#include "clang_ti_semihost.h" +#include "clang_ti_semihost_call.h" + +//---------------------------------------------------------------------------- +// _SYSTEM_POST_CINIT -- SETUP ARGV ARGUMENTS AFTER VARIABLE INITIALIZATION. +//---------------------------------------------------------------------------- +static int sys_open(const char *path, unsigned flags); + +static int fd_stdout, fd_stderr; + +extern __attribute__((weak)) ARGS __c_args__; + +#define ENV_SIZE 1000 +char __c_args_env__[ENV_SIZE]; + +void _system_post_cinit() +{ + // Setup c_args. + if (&__c_args__ != NULL) + { + register ARGS *pargs = (ARGS*)&__c_args__; + char buf[128]; + struct { + int32_t arg1; + int32_t arg2; + } arg = { + .arg1 = (int32_t) buf, + .arg2 = sizeof(buf) + }; + + pargs->argc = 0; + int32_t ret = ARMSemihost_Call(SYS_GET_CMDLINE, (int32_t) &arg); + if (ret == 0) + parse_cmdline(pargs, buf, __c_args_env__); + } + + // Open and save off STDIO file descriptors. + fd_stdout = sys_open(":tt", 4); + fd_stderr = sys_open(":tt", 4); +} + +//---------------------------------------------------------------------------- +// ARMSemihost_OPEN - OPEN A FILE DESCRIPTOR TO A FILE. +//---------------------------------------------------------------------------- +static int sys_open(const char *path, unsigned flags) { + struct { + int32_t arg1; + int32_t arg2; + int32_t arg3; + } arg = { + .arg1 = (int32_t) path, + .arg2 = flags, + .arg3 = strlen(path) + }; + + return (int) ARMSemihost_Call(SYS_OPEN, (int32_t) &arg); +} + +// Semihosting file open modes. +#define SH_OPEN_R 0 +#define SH_OPEN_R_PLUS 2 +#define SH_OPEN_W 4 +#define SH_OPEN_W_PLUS 6 +#define SH_OPEN_A 8 +#define SH_OPEN_A_PLUS 10 + +#define SH_OPEN_R_B 1 +#define SH_OPEN_R_PLUS_B 3 +#define SH_OPEN_W_B 5 +#define SH_OPEN_W_PLUS_B 7 +#define SH_OPEN_A_B 9 +#define SH_OPEN_A_PLUS_B 11 + +int ARMSemihost_open(const char *path, unsigned flags, int llv_fd) +{ + int semiflags = 0; + + // Translate from open() flags to the semihosting file open mode. + // O_RDONLY (0x0000) open for reading + // O_WRONLY (0x0001) open for writing + // O_RDWR (0x0002) open for read & write + // O_APPEND (0x0008) append on each write + // O_CREAT (0x0200) open with file create + // O_TRUNC (0x0400) open with truncation + // O_EXCL (0x0800) open exclusive + // O_BINARY (0x8000) open in binary mode + switch (flags & (O_RDONLY|O_WRONLY|O_RDWR)) { + case O_RDONLY: + semiflags = SH_OPEN_R; /* 'r' */ + break; + case O_WRONLY: + if (flags & (O_TRUNC | O_EXCL)) + semiflags = SH_OPEN_W; /* 'w' */ + else if (flags & O_APPEND) + semiflags = SH_OPEN_A; /* 'a' */ + break; + default: + semiflags = SH_OPEN_R_PLUS; /* 'r+' */ + if (flags & (O_TRUNC | O_EXCL)) + semiflags = SH_OPEN_W_PLUS; /* 'w+' */ + else if (flags & O_APPEND) + semiflags = SH_OPEN_A_PLUS; /* 'a+' */ + break; + } + + // When opening a file with exclusive write access, verify that + // the file does not already exist by attempting to read it. + // If the file exists, return -1 to indicate a file open error. + if (flags & O_EXCL) { + int fd = sys_open(path, SH_OPEN_R); + if (0 <= fd) { + ARMSemihost_close(fd); + return -1; + } + } + + if (flags & O_BINARY) + semiflags |= 0x1; + + return (int) sys_open(path, semiflags); +} + +//---------------------------------------------------------------------------- +// ARMSemihost_CLOSE - CLOSE A FILE DESCRIPTOR. +//---------------------------------------------------------------------------- +int ARMSemihost_close(int dev_fd) +{ + if (dev_fd <= 2) + return 0; + + struct { + int32_t arg1; + } arg = { + .arg1 = dev_fd + }; + + return ARMSemihost_Call(SYS_CLOSE, (int32_t) &arg); +} + +//---------------------------------------------------------------------------- +// USE_STDIO_FDS - MAKE SURE ALLOCATED FDS FOR STDIO ARE ALWAYS USED. +//---------------------------------------------------------------------------- +int use_stdio_fds(int fd) +{ + switch (fd) { + case 0: return -1; + case 1: return fd_stdout; + case 2: return fd_stderr; + default: return fd; + } +} + +//---------------------------------------------------------------------------- +// ARMSemihost_WRITE - WRITE TO A FILE DESCRIPTOR. +//---------------------------------------------------------------------------- +int ARMSemihost_write(int dev_fd, const char *buf, unsigned count) +{ + struct { + int32_t arg1; + int32_t arg2; + int32_t arg3; + } arg = { + .arg1 = use_stdio_fds(dev_fd), + .arg2 = (int32_t) buf, + .arg3 = (int32_t) count + }; + + int ret = (int)ARMSemihost_Call(SYS_WRITE, (int32_t) &arg); + return (count - (unsigned) ret); +} + +//---------------------------------------------------------------------------- +// ARMSemihost_READ - READ FROM A FILE DESCRIPTOR. +//---------------------------------------------------------------------------- +int ARMSemihost_read(int dev_fd, char *buf, unsigned count) +{ + if (dev_fd == 0) { + int ch = ARMSemihost_Call(SYS_READC, 0); + *(char *) buf = ch; + return 1; + } + + struct { + int32_t arg1; + int32_t arg2; + int32_t arg3; + } arg = { + .arg1 = use_stdio_fds(dev_fd), + .arg2 = (int32_t) buf, + .arg3 = (int32_t) count + }; + + int ret = ARMSemihost_Call(SYS_READ, (int32_t) &arg); + return (count - (unsigned) ret); +} + +//---------------------------------------------------------------------------- +// ARMSemihost_FLEN - GIVEN A FILE DESCRIPTOR, RETURN FILE LENGTH. +//---------------------------------------------------------------------------- +static int ARMSemihost_flen(int dev_fd) +{ + struct { + int32_t arg1; + } arg = { + .arg1 = (int32_t) dev_fd, + }; + + return (int32_t) ARMSemihost_Call(SYS_FLEN, (int32_t) &arg); +} + +//---------------------------------------------------------------------------- +// ARMSemihost_LSEEK - SEEK TO A POSITION IN THE FILE FROM BEGINNING OR END. +//---------------------------------------------------------------------------- +off_t ARMSemihost_lseek(int dev_fd, off_t offset, int origin) +{ + // NOTE: SEEK_CUR with offset == 0 is often used by ftell()/fseek() to get + // the current file position. This isn't supported by FastModel + // semihosting, so just return 0. The current file position of an open + // file must be maintained in software. + if (origin == SEEK_CUR && offset == 0) + return 0; + + if (origin == SEEK_END) { + int flen = ARMSemihost_flen(dev_fd); + if (flen != -1) { + origin = SEEK_SET; + offset += flen; + } + } + + if (origin != SEEK_SET || dev_fd < 0) { + return (off_t) -1; + } + + struct { + int32_t arg1; + int32_t arg2; + } arg = { + .arg1 = dev_fd, + .arg2 = offset + }; + + int32_t ret = ARMSemihost_Call(SYS_SEEK, (int32_t) &arg); + if (ret == 0) + return offset; + return -1; +} + +//---------------------------------------------------------------------------- +// ARMSemihost_UNLINK +//---------------------------------------------------------------------------- +int ARMSemihost_unlink(const char *path) +{ + struct { + int32_t arg1; + int32_t arg2; + } arg = { + .arg1 = (int32_t) path, + .arg2 = strlen(path) + }; + + return (int32_t) ARMSemihost_Call(SYS_REMOVE, (int32_t) &arg); +} + +//---------------------------------------------------------------------------- +// ARMSemihost_RENAME +//---------------------------------------------------------------------------- +int ARMSemihost_rename(const char *old_name, const char *new_name) +{ + struct { + int32_t arg1; + int32_t arg2; + int32_t arg3; + int32_t arg4; + } arg = { + .arg1 = (int32_t) old_name, + .arg2 = strlen(old_name), + .arg3 = (int32_t) new_name, + .arg4 = strlen(new_name) + }; + + return (int) ARMSemihost_Call(SYS_RENAME, (int32_t) &arg); +} + +//---------------------------------------------------------------------------- +// ARMSemihost_EXIT - EXIT FAST MODELS SIMULATION. +//---------------------------------------------------------------------------- +void ARMSemihost_exit() +{ + (void)ARMSemihost_Call(SYS_EXIT, 0); +} + +//---------------------------------------------------------------------------- +// ARMSemihost_TIME - RETURN SYSTEM TIME IN SECONDS FROM JAN 1, 1970. +//---------------------------------------------------------------------------- +long long ARMSemihost_time() +{ + return ARMSemihost_Call(SYS_TIME, 0); +} + +//---------------------------------------------------------------------------- +// ARMSemihost_CLOCK - RETURN ELAPSED CLOCK TICKS FROM START OF EXECUTION. +//---------------------------------------------------------------------------- +unsigned long ARMSemihost_clock() +{ + struct { + unsigned long long arg1; + } arg; + + if (ARMSemihost_Call(SYS_ELAPSED, (int32_t) &arg) == 0) + return (unsigned long) arg.arg1; + + return 0; +} + +//---------------------------------------------------------------------------- +// ARMSemihost_GETENV - GETENV -- RETURN ENVIRONMENT PATH FOR GIVEN VARIABLE +//---------------------------------------------------------------------------- +// Global process environment variables +char semihost_environ[ENV_SIZE]; +int env_len = -1; + +// Helper routine to gather environment variables. +void initialize_sys_environ() +{ + // Gather and open the environment path passed into the simulator + int fd = sys_open(__c_args_env__, SH_OPEN_R); + if (fd == -1) { + ARMSemihost_write(fd_stderr, "Failed to generate semihost environment: unable to open file.\n",63); + ARMSemihost_exit(); + } + + env_len = ARMSemihost_read(fd, semihost_environ, ENV_SIZE); + if (env_len == -1) { + ARMSemihost_write(fd_stderr, "Failed to generate semihost environment: unable to read file.\n",63); + ARMSemihost_exit(); + } + + ARMSemihost_close(fd); +} + +char *ARMSemihost_getenv(const char *_string, char *pout) +{ + if (env_len == -1) + initialize_sys_environ(); + + size_t len = strlen (_string); + for (pout = semihost_environ; pout < semihost_environ + env_len; + pout += strlen(pout) + 1) { + if (_string[0] == pout[0] && strncmp(_string, pout, len) == 0 && + pout[len] == '=') + return pout + len + 1; + } + + return NULL; +} \ No newline at end of file diff --git a/CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_semihost.h b/CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_semihost.h new file mode 100644 index 000000000..c360f8e0d --- /dev/null +++ b/CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_semihost.h @@ -0,0 +1,61 @@ +/*****************************************************************************/ +/* SEMIHOST.H v##### - Generic C functions for interfacing with simulators */ +/* that support ARM-conformant semihosting */ +/* Copyright (c) 2024@%%%% Texas Instruments Incorporated */ +/*****************************************************************************/ +/*****************************************************************************/ +/* CLANG_TI_SEMIHOST.H - Generic C functions for interfacing with */ +/* simulators that support ARM-conformant semihosting */ +/*****************************************************************************/ +#ifndef _CLANG_TI_SEMIHOST_H_ +#define _CLANG_TI_SEMIHOST_H_ + +#include + +// Device I/O routines. +int ARMSemihost_open(const char *path, unsigned flags, int llv_fd); +int ARMSemihost_close(int dev_fd); +int ARMSemihost_write(int dev_fd, const char *buf, unsigned count); +int ARMSemihost_read(int dev_fd, char *buf, unsigned count); +off_t ARMSemihost_lseek(int dev_fd, off_t offset, int origin); +int ARMSemihost_unlink(const char *path); +int ARMSemihost_rename(const char *old_name, const char *new_name); + +// Auxiliary device routines. +void ARMSemihost_exit(); +long long ARMSemihost_time(); +unsigned long ARMSemihost_clock(); +char* ARMSemihost_getenv(const char*, char*); + +#define SYS_CLOCK (0x10) +#define SYS_CLOSE (0x02) +#define SYS_ELAPSED (0x30) +#define SYS_ERRNO (0x13) +#define SYS_EXIT (0x18) +#define SYS_EXIT_EXTENDED (0x20) +#define SYS_FLEN (0x0C) +#define SYS_GET_CMDLINE (0x15) +#define SYS_HEAPINFO (0x16) +#define SYS_ISERROR (0x08) +#define SYS_ISTTY (0x09) +#define SYS_OPEN (0x01) +#define SYS_READ (0x06) +#define SYS_READC (0x07) +#define SYS_REMOVE (0x0E) +#define SYS_RENAME (0x0F) +#define SYS_SEEK (0x0A) +#define SYS_SYSTEM (0x12) +#define SYS_TICKFREQ (0x31) +#define SYS_TIME (0x11) +#define SYS_TMPNAM (0x0D) +#define SYS_WRITE (0x05) +#define SYS_WRITEC (0x03) +#define SYS_WRITE0 (0x04) + +//---------------------------------------------------------------------------- +// PARSE_CMDLINE - PARSE THE FASTMODELS SIMULATOR COMMAND LINE FOR ARGUMENTS. +typedef struct { int argc; char *argv[1]; } ARGS; + +void parse_cmdline(ARGS *pargs, char* buf, char* env); + +#endif /* _CLANG_TI_SEMIHOST_H_ */ \ No newline at end of file diff --git a/CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_semihost_call.h b/CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_semihost_call.h new file mode 100644 index 000000000..726d807a5 --- /dev/null +++ b/CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_semihost_call.h @@ -0,0 +1,43 @@ +/*****************************************************************************/ +/* SEMIHOST_CALL.C v##### - Target-specific instruction sequence for */ +/* triggering ARM-conformant semihosting */ +/* Copyright (c) 2024@%%%% Texas Instruments Incorporated */ +/*****************************************************************************/ +/*****************************************************************************/ +/* CLANG_TI_SEMIHOST_CALL.H - Target-specific instruction sequence for */ +/* triggering ARM-conformant semihosting */ +/*****************************************************************************/ +#ifndef _CLANG_TI_SEMIHOST_CALL_H_ +#define _CLANG_TI_SEMIHOST_CALL_H_ + +#include + +//---------------------------------------------------------------------------- +// ARMSemihost_Call - Issue instruction sequence to the simulator with +// arguments. +//---------------------------------------------------------------------------- +__attribute__((noinline,optnone)) +static inline int ARMSemihost_Call(int command, int32_t arg) { + int ret; + __asm volatile ( + "mov r0, %[rsn] \n" + "mov r1, %[arg] \n" +#if __ARM_ARCH_PROFILE == 'M' + "bkpt #0xab \n" +#else +#ifdef __thumb__ + "svc #0xab \n" +#else + "svc #0x123456 \n" +#endif +#endif + "mov %[val], r0 \n" + + : [val] "=r" (ret) /* outputs */ + : [rsn] "r" (command), [arg] "r" (arg) /* inputs */ + : "r0", "r1", "r2", "r3", "ip", "lr", "memory", "cc" /* clobber */ + ); + return ret; +} + +#endif /* _CLANG_TI_SEMIHOST_CALL_H_ */ \ No newline at end of file diff --git a/CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_vprintf_semihost.c b/CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_vprintf_semihost.c new file mode 100644 index 000000000..931228a40 --- /dev/null +++ b/CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_vprintf_semihost.c @@ -0,0 +1,96 @@ +/*****************************************************************************/ +/* CLANG_TI_VPRINTF_SEMIHOST.C */ +/* */ +/* Specialized version of vprintf that directs output to an ARM debugger */ +/* using semihosting calls via ARMSemihost_write. */ +/*****************************************************************************/ +/*****************************************************************************/ +/* VPRINTF.C */ +/* */ +/* Copyright (c) 1995 Texas Instruments Incorporated */ +/* http://www.ti.com/ */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in */ +/* the documentation and/or other materials provided with the */ +/* distribution. */ +/* */ +/* Neither the name of Texas Instruments Incorporated nor the names */ +/* of its contributors may be used to endorse or promote products */ +/* derived from this software without specific prior written */ +/* permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ +/* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ +/* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ +/* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ +/* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ +/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ +/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ +/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ +/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ +/* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Functions: */ +/* VPRINTF - Print formatted output to stdio */ +/* _OUTC - Put a character in a stream */ +/* _OUTS - Put a string in a stream */ +/*****************************************************************************/ +#include +#include "clang_ti_format_semihost.h" +#include +#include +#include "clang_ti_semihost.h" +#include "clang_ti_vprintf_semihost.h" + +extern _CODE_ACCESS int __TI_printfi(char ** __restrict _format, + va_list _ap, void * __restrict _op, + int (*_outc)(char, void *), + int (*_outs)(char *, void *, int)); + +static int _outc_sh(char c, void *_op); +static int _outs_sh(char *s, void *_op, int len); + +/*****************************************************************************/ +/* CLANG_TI_VPRINTF_SEMIHOST */ +/*****************************************************************************/ +_CODE_ACCESS int clang_ti_vprintf_semihost(const char *_format, va_list _ap) +{ + char *fptr = (char *)_format; + + /* Route formatting engine to semihosting callbacks */ + return (__TI_printfi(&fptr, _ap, NULL, _outc_sh, _outs_sh)); +} + +static int _outc_sh(char c, void *_op) +{ + /* Use FD 1 (stdout) which maps to the debugger console in semihost.c */ + if (ARMSemihost_write(1, &c, 1) == 1) + { + return (int)(unsigned char)c; + } + + return EOF; +} + +static int _outs_sh(char *s, void *_op, int len) +{ + int result = ARMSemihost_write(1, s, len); + if (result < 0) + { + return EOF; + } + + return result; +} \ No newline at end of file diff --git a/CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_vprintf_semihost.h b/CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_vprintf_semihost.h new file mode 100644 index 000000000..c34ddcb93 --- /dev/null +++ b/CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_vprintf_semihost.h @@ -0,0 +1,20 @@ +/*****************************************************************************/ +/* CLANG_TI_VPRINTF_SEMIHOST.H */ +/*****************************************************************************/ +#ifndef _CLANG_TI_VPRINTF_SEMIHOST_H_ +#define _CLANG_TI_VPRINTF_SEMIHOST_H_ + +#include +#include <_ti_config.h> + +#ifdef __cplusplus +extern "C" { +#endif + +_CODE_ACCESS int clang_ti_vprintf_semihost(const char *_format, va_list _ap); + +#ifdef __cplusplus +} +#endif + +#endif /* _CLANG_TI_VPRINTF_SEMIHOST_H_ */ \ No newline at end of file From d10da7b9d13442d01b7444eccffa92225afd80bf Mon Sep 17 00:00:00 2001 From: Shawn Mason <255018043+smmasongt@users.noreply.github.com> Date: Sun, 29 Mar 2026 15:17:40 -0400 Subject: [PATCH 08/17] Update GitHub Cache Action to v5 to address Node.js warning. --- .github/workflows/corevalidation.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/corevalidation.yml b/.github/workflows/corevalidation.yml index a2c1a74c2..3e73f53b7 100644 --- a/.github/workflows/corevalidation.yml +++ b/.github/workflows/corevalidation.yml @@ -94,7 +94,7 @@ jobs: - name: Cache TI ARM CLANG id: cache-ti-arm-clang - uses: actions/cache@v4 + uses: actions/cache@v5 with: path: ${{ env.CLANG_TI_PATH }} key: ${{ runner.os }}-ti-arm-clang-${{ env.CLANG_TI_VERSION }} From 6838d211ab99aa4884aa698a534becd4626c2e81 Mon Sep 17 00:00:00 2001 From: Shawn Mason <255018043+smmasongt@users.noreply.github.com> Date: Sun, 29 Mar 2026 23:51:05 -0400 Subject: [PATCH 09/17] Correct issue with Clang execution of NS devices --- .../Device/ARMCM0/clang_ti_linker_script.cmd | 2 +- .../Device/ARMCM0P/clang_ti_linker_script.cmd | 2 +- .../Device/ARMCM3/clang_ti_linker_script.cmd | 2 +- .../Device/ARMCM33/clang_ti_linker_script.cmd | 2 +- .../Device/ARMCM33/clang_ti_linker_script.cmd | 2 +- .../Device/ARMCM33/clang_ti_linker_script.cmd | 2 +- .../Device/ARMCM4/clang_ti_linker_script.cmd | 2 +- .../Project/Validation.csolution.yml | 3 ++- CMSIS/CoreValidation/Project/build.py | 18 ++++++++++-------- 9 files changed, 19 insertions(+), 16 deletions(-) diff --git a/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/clang_ti_linker_script.cmd b/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/clang_ti_linker_script.cmd index 4ae39a49f..e621f7891 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/clang_ti_linker_script.cmd +++ b/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/clang_ti_linker_script.cmd @@ -47,6 +47,6 @@ SECTIONS #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - Veneer$$CMSE: palign=8 {} > ROM1 + Veneer$$CMSE: palign=8 {} > ROM0 #endif } \ No newline at end of file diff --git a/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/clang_ti_linker_script.cmd b/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/clang_ti_linker_script.cmd index 4ae39a49f..e621f7891 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/clang_ti_linker_script.cmd +++ b/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/clang_ti_linker_script.cmd @@ -47,6 +47,6 @@ SECTIONS #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - Veneer$$CMSE: palign=8 {} > ROM1 + Veneer$$CMSE: palign=8 {} > ROM0 #endif } \ No newline at end of file diff --git a/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/clang_ti_linker_script.cmd b/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/clang_ti_linker_script.cmd index 4ae39a49f..e621f7891 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/clang_ti_linker_script.cmd +++ b/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/clang_ti_linker_script.cmd @@ -47,6 +47,6 @@ SECTIONS #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - Veneer$$CMSE: palign=8 {} > ROM1 + Veneer$$CMSE: palign=8 {} > ROM0 #endif } \ No newline at end of file diff --git a/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33/clang_ti_linker_script.cmd b/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33/clang_ti_linker_script.cmd index 4ae39a49f..e621f7891 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33/clang_ti_linker_script.cmd +++ b/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33/clang_ti_linker_script.cmd @@ -47,6 +47,6 @@ SECTIONS #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - Veneer$$CMSE: palign=8 {} > ROM1 + Veneer$$CMSE: palign=8 {} > ROM0 #endif } \ No newline at end of file diff --git a/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33/clang_ti_linker_script.cmd b/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33/clang_ti_linker_script.cmd index 4ae39a49f..e621f7891 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33/clang_ti_linker_script.cmd +++ b/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33/clang_ti_linker_script.cmd @@ -47,6 +47,6 @@ SECTIONS #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - Veneer$$CMSE: palign=8 {} > ROM1 + Veneer$$CMSE: palign=8 {} > ROM0 #endif } \ No newline at end of file diff --git a/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33/clang_ti_linker_script.cmd b/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33/clang_ti_linker_script.cmd index 4ae39a49f..e621f7891 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33/clang_ti_linker_script.cmd +++ b/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33/clang_ti_linker_script.cmd @@ -47,6 +47,6 @@ SECTIONS #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - Veneer$$CMSE: palign=8 {} > ROM1 + Veneer$$CMSE: palign=8 {} > ROM0 #endif } \ No newline at end of file diff --git a/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/clang_ti_linker_script.cmd b/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/clang_ti_linker_script.cmd index 4ae39a49f..e621f7891 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/clang_ti_linker_script.cmd +++ b/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/clang_ti_linker_script.cmd @@ -47,6 +47,6 @@ SECTIONS #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - Veneer$$CMSE: palign=8 {} > ROM1 + Veneer$$CMSE: palign=8 {} > ROM0 #endif } \ No newline at end of file diff --git a/CMSIS/CoreValidation/Project/Validation.csolution.yml b/CMSIS/CoreValidation/Project/Validation.csolution.yml index 4c31eefaf..7c167b660 100644 --- a/CMSIS/CoreValidation/Project/Validation.csolution.yml +++ b/CMSIS/CoreValidation/Project/Validation.csolution.yml @@ -148,6 +148,7 @@ solution: debug: on projects: + - project: ./Validation/Validation.cproject.yml - project: ./Bootloader/Bootloader.cproject.yml for-context: - +CM23NS @@ -156,7 +157,7 @@ solution: - +CM52NS - +CM55NS - +CM85NS - - project: ./Validation/Validation.cproject.yml + output-dirs: cprjdir: ./build/$TargetType$/$Compiler$/$BuildType$/$Project$ diff --git a/CMSIS/CoreValidation/Project/build.py b/CMSIS/CoreValidation/Project/build.py index e6b80cdfe..e557b28b2 100755 --- a/CMSIS/CoreValidation/Project/build.py +++ b/CMSIS/CoreValidation/Project/build.py @@ -184,22 +184,22 @@ def config_suffix(config, timestamp=True): return suffix -def bl_project_name(config): - return f"Bootloader.{config.compiler}_{config.optimize}+{config.device.bl_device}" - - def project_name(config): return f"Validation.{config.compiler}_{config.optimize}+{config.device[1]}" -def bl_output_dir(config): - return f"Bootloader/outdir" +def bl_project_name(config): + return f"Bootloader.{config.compiler}_{config.optimize}+{config.device.bl_device}" def output_dir(config): return f"Validation/outdir" +def bl_output_dir(config): + return f"Bootloader/outdir" + + def model_config(config): return f"../Layer/Target/{config.device[1]}/model_config.txt" @@ -295,11 +295,13 @@ def cbuild(config): f"{result.command.config.device}." f"{title}")) def model_exec(config): - cmdline = [MODEL_EXECUTABLE[config.device][0], "-q", "--simlimit", 100, "-f", model_config(config)] + cmdline = [MODEL_EXECUTABLE[config.device][0], "-q", "--simlimit", 5, "-f", model_config(config)] cmdline += MODEL_EXECUTABLE[config.device][1] - if config.device.has_bl(): + if config.device.has_bl() and (config.compiler == CompilerAxis.CLANG_TI): cmdline += ["-a", f"{build_dir(config)}/{bl_output_dir(config)}/Bootloader.{config.compiler.image_ext}"] cmdline += ["-a", f"{build_dir(config)}/{output_dir(config)}/Validation.{config.compiler.image_ext}"] + if config.device.has_bl() and (config.compiler != CompilerAxis.CLANG_TI): + cmdline += ["-a", f"{build_dir(config)}/{bl_output_dir(config)}/Bootloader.{config.compiler.image_ext}"] return cmdline From d5d4cdec6a55de2c1e274159c87e6211c571bfc7 Mon Sep 17 00:00:00 2001 From: Shawn Mason <255018043+smmasongt@users.noreply.github.com> Date: Mon, 30 Mar 2026 00:13:19 -0400 Subject: [PATCH 10/17] Cleanups --- .../CM23S/RTE/Device/ARMCM23/ARMCM23_ac6.sct | 123 ------------------ .../Device/ARMCM23/ARMCM23_ac6.sct.base@1.1.0 | 123 ------------------ .../Project/Validation.csolution.yml | 1 - CMSIS/CoreValidation/README.md | 2 +- 4 files changed, 1 insertion(+), 248 deletions(-) delete mode 100644 CMSIS/CoreValidation/Layer/Target/CM23S/RTE/Device/ARMCM23/ARMCM23_ac6.sct delete mode 100644 CMSIS/CoreValidation/Layer/Target/CM23S/RTE/Device/ARMCM23/ARMCM23_ac6.sct.base@1.1.0 diff --git a/CMSIS/CoreValidation/Layer/Target/CM23S/RTE/Device/ARMCM23/ARMCM23_ac6.sct b/CMSIS/CoreValidation/Layer/Target/CM23S/RTE/Device/ARMCM23/ARMCM23_ac6.sct deleted file mode 100644 index a0317e6c0..000000000 --- a/CMSIS/CoreValidation/Layer/Target/CM23S/RTE/Device/ARMCM23/ARMCM23_ac6.sct +++ /dev/null @@ -1,123 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc -; command above MUST be in first line (no comment above!) - -;Note: Add '-mcmse' to first line if your software model is "Secure Mode". -; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc -mcmse - - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/*--------------------- CMSE Veneer Configuration --------------------------- -; CMSE Veneer Configuration -; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> -; - *----------------------------------------------------------------------------*/ -#define __CMSEVENEER_SIZE 0x200 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - -/* ---------------------------------------------------------------------------- - Stack seal size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __STACKSEAL_SIZE ( 8 ) -#else -#define __STACKSEAL_SIZE ( 0 ) -#endif - - -/*---------------------------------------------------------------------------- - Region base & size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) -#define __CV_SIZE ( __CMSEVENEER_SIZE ) -#else -#define __CV_SIZE ( 0 ) -#endif - -#define __RO_BASE ( __ROM_BASE ) -#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) - -#define __RW_BASE ( __RAM_BASE ) -#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) - - -/*---------------------------------------------------------------------------- - Scatter Region definition - *----------------------------------------------------------------------------*/ -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_NOINIT __RW_BASE UNINIT __RW_SIZE { - *(.bss.noinit) - } - - RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { - *(+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack - } -#endif -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers - ER_CMSE_VENEER __CV_BASE __CV_SIZE { - *(Veneer$$CMSE) - } -} -#endif diff --git a/CMSIS/CoreValidation/Layer/Target/CM23S/RTE/Device/ARMCM23/ARMCM23_ac6.sct.base@1.1.0 b/CMSIS/CoreValidation/Layer/Target/CM23S/RTE/Device/ARMCM23/ARMCM23_ac6.sct.base@1.1.0 deleted file mode 100644 index a0317e6c0..000000000 --- a/CMSIS/CoreValidation/Layer/Target/CM23S/RTE/Device/ARMCM23/ARMCM23_ac6.sct.base@1.1.0 +++ /dev/null @@ -1,123 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc -; command above MUST be in first line (no comment above!) - -;Note: Add '-mcmse' to first line if your software model is "Secure Mode". -; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc -mcmse - - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/*--------------------- CMSE Veneer Configuration --------------------------- -; CMSE Veneer Configuration -; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> -; - *----------------------------------------------------------------------------*/ -#define __CMSEVENEER_SIZE 0x200 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - -/* ---------------------------------------------------------------------------- - Stack seal size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __STACKSEAL_SIZE ( 8 ) -#else -#define __STACKSEAL_SIZE ( 0 ) -#endif - - -/*---------------------------------------------------------------------------- - Region base & size definition - *----------------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) -#define __CV_SIZE ( __CMSEVENEER_SIZE ) -#else -#define __CV_SIZE ( 0 ) -#endif - -#define __RO_BASE ( __ROM_BASE ) -#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) - -#define __RW_BASE ( __RAM_BASE ) -#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) - - -/*---------------------------------------------------------------------------- - Scatter Region definition - *----------------------------------------------------------------------------*/ -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_NOINIT __RW_BASE UNINIT __RW_SIZE { - *(.bss.noinit) - } - - RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { - *(+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack - } -#endif -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers - ER_CMSE_VENEER __CV_BASE __CV_SIZE { - *(Veneer$$CMSE) - } -} -#endif diff --git a/CMSIS/CoreValidation/Project/Validation.csolution.yml b/CMSIS/CoreValidation/Project/Validation.csolution.yml index 7c167b660..443b1f75e 100644 --- a/CMSIS/CoreValidation/Project/Validation.csolution.yml +++ b/CMSIS/CoreValidation/Project/Validation.csolution.yml @@ -158,7 +158,6 @@ solution: - +CM55NS - +CM85NS - output-dirs: cprjdir: ./build/$TargetType$/$Compiler$/$BuildType$/$Project$ outdir: ./build/$TargetType$/$Compiler$/$BuildType$/$Project$/outdir diff --git a/CMSIS/CoreValidation/README.md b/CMSIS/CoreValidation/README.md index ce3e459d1..554a50aab 100644 --- a/CMSIS/CoreValidation/README.md +++ b/CMSIS/CoreValidation/README.md @@ -20,7 +20,7 @@ Currently, the following build configurations are provided: - Arm Compiler 6 (AC6) - GNU Compiler (GCC) - LLVM/Clang (Clang) - - TI Arm Clang (Clang_TI) (CM0/0+/3/4/33/33S) + - TI Arm Clang (Clang_TI) (CM0/0+/3/4/33/33S/33NS) 2. Devices - Cortex-M0 - Cortex-M0+ From 9f42dc5107ca4e11591d6623a9db0d76b4391359 Mon Sep 17 00:00:00 2001 From: Shawn Mason <255018043+smmasongt@users.noreply.github.com> Date: Sun, 12 Apr 2026 16:29:03 -0400 Subject: [PATCH 11/17] Clang TI Linker Command File Cleanup --- .../App/Bootloader_Cortex-M/App.clayer.yml | 16 ++-- .../Device/ARMCM0/clang_ti_linker_script.cmd | 84 ++++++++++++------- .../Device/ARMCM0P/clang_ti_linker_script.cmd | 84 ++++++++++++------- .../Device/ARMCM3/clang_ti_linker_script.cmd | 84 ++++++++++++------- .../Device/ARMCM33/clang_ti_linker_script.cmd | 84 ++++++++++++------- .../Device/ARMCM33/clang_ti_linker_script.cmd | 84 ++++++++++++------- .../Device/ARMCM33/clang_ti_linker_script.cmd | 84 ++++++++++++------- .../Device/ARMCM4/clang_ti_linker_script.cmd | 84 ++++++++++++------- .../Project/Validation.csolution.yml | 3 - CMSIS/CoreValidation/Project/build.py | 4 +- CMSIS/CoreValidation/Source/CV_Framework.c | 14 ---- 11 files changed, 404 insertions(+), 221 deletions(-) diff --git a/CMSIS/CoreValidation/Layer/App/Bootloader_Cortex-M/App.clayer.yml b/CMSIS/CoreValidation/Layer/App/Bootloader_Cortex-M/App.clayer.yml index 8cfa71cca..89ae8bc0b 100644 --- a/CMSIS/CoreValidation/Layer/App/Bootloader_Cortex-M/App.clayer.yml +++ b/CMSIS/CoreValidation/Layer/App/Bootloader_Cortex-M/App.clayer.yml @@ -5,13 +5,19 @@ layer: # packs: # - pack: ARM::CMSIS - misc: - - for-compiler: CLANG_TI - Link: - # Reference TI Arm Clang Compiler ToolUser's Guide, v5.1, Section 6 Cortex-M Security Extensions (CMSE) - - -Xlinker --import_cmse_lib_out=implib.o + add-path: + - ../../../Include + - ../../../Source/Config + - ../../../Source/Clang_TI_Semihost groups: - group: Source Files files: - file: ./bootloader.c + + - group: TI Arm Clang Compiler Semihost Support + for-compiler: CLANG_TI + files: + - file: ../../../Source/Clang_TI_Semihost/clang_ti_fastmodel_cio.c + - file: ../../../Source/Clang_TI_Semihost/clang_ti_semihost.c + - file: ../../../Source/Clang_TI_Semihost/clang_ti_vprintf_semihost.c diff --git a/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/clang_ti_linker_script.cmd b/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/clang_ti_linker_script.cmd index e621f7891..0805b7776 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/clang_ti_linker_script.cmd +++ b/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/clang_ti_linker_script.cmd @@ -1,52 +1,80 @@ --stack_size=__STACK_SIZE --heap_size=__HEAP_SIZE --symbol_map=_start=_c_int00 +--entry_point=Reset_Handler +/* Macros for Stack/Seal */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __STACKSEAL_SIZE 8 #else #define __STACKSEAL_SIZE 0 #endif -__stack = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; -__stack_seal = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; -__stack_limit = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE; -#define __STACK_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1) -#define __STACK_LIMIT_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE) - MEMORY { -ROM0 : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE + ROM0 (RX) : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE + RAM0 (RW) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE +} -#if defined (__ROM1_BASE) - ROM1 : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE -#endif +--retain="*(.vectors)" +--retain="*(.intvecs)" + +SECTIONS +{ + /* 1. Vectors forced to the base of ROM */ + .intvecs : load = __ROM0_BASE + { + *(.vectors) + *(.intvecs) + } -RAM0 : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE + /* 2. Code and Read-Only Data */ + .text : + { + *(.text.Reset_Handler) + *(.text:_c_int00_noargs) + *(.text.main) + *(.text*) + } > ROM0 -#if defined (__RAM1_BASE) - RAM1 : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE + /* 3. CMSE Veneers */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + Veneer$$CMSE : {} > ROM0 #endif -} -SECTIONS -{ -.vectors: {} > 0x00000000 + .rodata : {} > ROM0 + .TI.crctab : {} > ROM0 -.text: palign=4 {} > ROM0 -.rodata: palign=4 {} > ROM0 + /* 4. Runtime Initialization Tables */ + .binit : {} > ROM0 + .cinit : {} > ROM0 + .pinit : {} > ROM0 + .init_array : {} > ROM0 + .fini_array : {} > ROM0 + .ovly : {} > ROM0 -.noinit: palign=4 {} > RAM0 -.data: palign=4 {} > RAM0 -.sysmem: palign=4 {} > RAM0 -.bss: type=NOINIT, palign=4 {} > RAM0 + /* 5. Initialized Data */ + .data : load = ROM0, run = RAM0, table(BINIT) -.stack: run=__STACK_LIMIT_ADDR, type=NOLOAD {} > RAM0 -#if __STACKSEAL_SIZE > 0 - .stackseal: run=__STACK_ADDR, type=NOLOAD {} > RAM0 -#endif + /* 6. Uninitialized Data */ + .bss : type = NOINIT {} > RAM0 + .sysmem : type = NOINIT {} > RAM0 + + /* 7. Stack & Security Seal */ + /* (HIGH) ensures these are placed at the end of RAM0 */ +GROUP : > RAM0 (HIGH) + { + .stack : type = NOINIT, palign = 8 { + __stack_limit = .; + . += __STACK_SIZE; + __stack = . - 1; + } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - Veneer$$CMSE: palign=8 {} > ROM0 + .stackseal : type = NOINIT, palign = 8 { + __stack_seal = .; + . += __STACKSEAL_SIZE; + } #endif + } } \ No newline at end of file diff --git a/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/clang_ti_linker_script.cmd b/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/clang_ti_linker_script.cmd index e621f7891..0805b7776 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/clang_ti_linker_script.cmd +++ b/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/clang_ti_linker_script.cmd @@ -1,52 +1,80 @@ --stack_size=__STACK_SIZE --heap_size=__HEAP_SIZE --symbol_map=_start=_c_int00 +--entry_point=Reset_Handler +/* Macros for Stack/Seal */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __STACKSEAL_SIZE 8 #else #define __STACKSEAL_SIZE 0 #endif -__stack = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; -__stack_seal = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; -__stack_limit = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE; -#define __STACK_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1) -#define __STACK_LIMIT_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE) - MEMORY { -ROM0 : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE + ROM0 (RX) : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE + RAM0 (RW) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE +} -#if defined (__ROM1_BASE) - ROM1 : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE -#endif +--retain="*(.vectors)" +--retain="*(.intvecs)" + +SECTIONS +{ + /* 1. Vectors forced to the base of ROM */ + .intvecs : load = __ROM0_BASE + { + *(.vectors) + *(.intvecs) + } -RAM0 : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE + /* 2. Code and Read-Only Data */ + .text : + { + *(.text.Reset_Handler) + *(.text:_c_int00_noargs) + *(.text.main) + *(.text*) + } > ROM0 -#if defined (__RAM1_BASE) - RAM1 : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE + /* 3. CMSE Veneers */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + Veneer$$CMSE : {} > ROM0 #endif -} -SECTIONS -{ -.vectors: {} > 0x00000000 + .rodata : {} > ROM0 + .TI.crctab : {} > ROM0 -.text: palign=4 {} > ROM0 -.rodata: palign=4 {} > ROM0 + /* 4. Runtime Initialization Tables */ + .binit : {} > ROM0 + .cinit : {} > ROM0 + .pinit : {} > ROM0 + .init_array : {} > ROM0 + .fini_array : {} > ROM0 + .ovly : {} > ROM0 -.noinit: palign=4 {} > RAM0 -.data: palign=4 {} > RAM0 -.sysmem: palign=4 {} > RAM0 -.bss: type=NOINIT, palign=4 {} > RAM0 + /* 5. Initialized Data */ + .data : load = ROM0, run = RAM0, table(BINIT) -.stack: run=__STACK_LIMIT_ADDR, type=NOLOAD {} > RAM0 -#if __STACKSEAL_SIZE > 0 - .stackseal: run=__STACK_ADDR, type=NOLOAD {} > RAM0 -#endif + /* 6. Uninitialized Data */ + .bss : type = NOINIT {} > RAM0 + .sysmem : type = NOINIT {} > RAM0 + + /* 7. Stack & Security Seal */ + /* (HIGH) ensures these are placed at the end of RAM0 */ +GROUP : > RAM0 (HIGH) + { + .stack : type = NOINIT, palign = 8 { + __stack_limit = .; + . += __STACK_SIZE; + __stack = . - 1; + } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - Veneer$$CMSE: palign=8 {} > ROM0 + .stackseal : type = NOINIT, palign = 8 { + __stack_seal = .; + . += __STACKSEAL_SIZE; + } #endif + } } \ No newline at end of file diff --git a/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/clang_ti_linker_script.cmd b/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/clang_ti_linker_script.cmd index e621f7891..0805b7776 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/clang_ti_linker_script.cmd +++ b/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/clang_ti_linker_script.cmd @@ -1,52 +1,80 @@ --stack_size=__STACK_SIZE --heap_size=__HEAP_SIZE --symbol_map=_start=_c_int00 +--entry_point=Reset_Handler +/* Macros for Stack/Seal */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __STACKSEAL_SIZE 8 #else #define __STACKSEAL_SIZE 0 #endif -__stack = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; -__stack_seal = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; -__stack_limit = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE; -#define __STACK_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1) -#define __STACK_LIMIT_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE) - MEMORY { -ROM0 : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE + ROM0 (RX) : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE + RAM0 (RW) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE +} -#if defined (__ROM1_BASE) - ROM1 : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE -#endif +--retain="*(.vectors)" +--retain="*(.intvecs)" + +SECTIONS +{ + /* 1. Vectors forced to the base of ROM */ + .intvecs : load = __ROM0_BASE + { + *(.vectors) + *(.intvecs) + } -RAM0 : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE + /* 2. Code and Read-Only Data */ + .text : + { + *(.text.Reset_Handler) + *(.text:_c_int00_noargs) + *(.text.main) + *(.text*) + } > ROM0 -#if defined (__RAM1_BASE) - RAM1 : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE + /* 3. CMSE Veneers */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + Veneer$$CMSE : {} > ROM0 #endif -} -SECTIONS -{ -.vectors: {} > 0x00000000 + .rodata : {} > ROM0 + .TI.crctab : {} > ROM0 -.text: palign=4 {} > ROM0 -.rodata: palign=4 {} > ROM0 + /* 4. Runtime Initialization Tables */ + .binit : {} > ROM0 + .cinit : {} > ROM0 + .pinit : {} > ROM0 + .init_array : {} > ROM0 + .fini_array : {} > ROM0 + .ovly : {} > ROM0 -.noinit: palign=4 {} > RAM0 -.data: palign=4 {} > RAM0 -.sysmem: palign=4 {} > RAM0 -.bss: type=NOINIT, palign=4 {} > RAM0 + /* 5. Initialized Data */ + .data : load = ROM0, run = RAM0, table(BINIT) -.stack: run=__STACK_LIMIT_ADDR, type=NOLOAD {} > RAM0 -#if __STACKSEAL_SIZE > 0 - .stackseal: run=__STACK_ADDR, type=NOLOAD {} > RAM0 -#endif + /* 6. Uninitialized Data */ + .bss : type = NOINIT {} > RAM0 + .sysmem : type = NOINIT {} > RAM0 + + /* 7. Stack & Security Seal */ + /* (HIGH) ensures these are placed at the end of RAM0 */ +GROUP : > RAM0 (HIGH) + { + .stack : type = NOINIT, palign = 8 { + __stack_limit = .; + . += __STACK_SIZE; + __stack = . - 1; + } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - Veneer$$CMSE: palign=8 {} > ROM0 + .stackseal : type = NOINIT, palign = 8 { + __stack_seal = .; + . += __STACKSEAL_SIZE; + } #endif + } } \ No newline at end of file diff --git a/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33/clang_ti_linker_script.cmd b/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33/clang_ti_linker_script.cmd index e621f7891..0805b7776 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33/clang_ti_linker_script.cmd +++ b/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33/clang_ti_linker_script.cmd @@ -1,52 +1,80 @@ --stack_size=__STACK_SIZE --heap_size=__HEAP_SIZE --symbol_map=_start=_c_int00 +--entry_point=Reset_Handler +/* Macros for Stack/Seal */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __STACKSEAL_SIZE 8 #else #define __STACKSEAL_SIZE 0 #endif -__stack = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; -__stack_seal = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; -__stack_limit = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE; -#define __STACK_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1) -#define __STACK_LIMIT_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE) - MEMORY { -ROM0 : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE + ROM0 (RX) : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE + RAM0 (RW) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE +} -#if defined (__ROM1_BASE) - ROM1 : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE -#endif +--retain="*(.vectors)" +--retain="*(.intvecs)" + +SECTIONS +{ + /* 1. Vectors forced to the base of ROM */ + .intvecs : load = __ROM0_BASE + { + *(.vectors) + *(.intvecs) + } -RAM0 : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE + /* 2. Code and Read-Only Data */ + .text : + { + *(.text.Reset_Handler) + *(.text:_c_int00_noargs) + *(.text.main) + *(.text*) + } > ROM0 -#if defined (__RAM1_BASE) - RAM1 : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE + /* 3. CMSE Veneers */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + Veneer$$CMSE : {} > ROM0 #endif -} -SECTIONS -{ -.vectors: {} > 0x00000000 + .rodata : {} > ROM0 + .TI.crctab : {} > ROM0 -.text: palign=4 {} > ROM0 -.rodata: palign=4 {} > ROM0 + /* 4. Runtime Initialization Tables */ + .binit : {} > ROM0 + .cinit : {} > ROM0 + .pinit : {} > ROM0 + .init_array : {} > ROM0 + .fini_array : {} > ROM0 + .ovly : {} > ROM0 -.noinit: palign=4 {} > RAM0 -.data: palign=4 {} > RAM0 -.sysmem: palign=4 {} > RAM0 -.bss: type=NOINIT, palign=4 {} > RAM0 + /* 5. Initialized Data */ + .data : load = ROM0, run = RAM0, table(BINIT) -.stack: run=__STACK_LIMIT_ADDR, type=NOLOAD {} > RAM0 -#if __STACKSEAL_SIZE > 0 - .stackseal: run=__STACK_ADDR, type=NOLOAD {} > RAM0 -#endif + /* 6. Uninitialized Data */ + .bss : type = NOINIT {} > RAM0 + .sysmem : type = NOINIT {} > RAM0 + + /* 7. Stack & Security Seal */ + /* (HIGH) ensures these are placed at the end of RAM0 */ +GROUP : > RAM0 (HIGH) + { + .stack : type = NOINIT, palign = 8 { + __stack_limit = .; + . += __STACK_SIZE; + __stack = . - 1; + } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - Veneer$$CMSE: palign=8 {} > ROM0 + .stackseal : type = NOINIT, palign = 8 { + __stack_seal = .; + . += __STACKSEAL_SIZE; + } #endif + } } \ No newline at end of file diff --git a/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33/clang_ti_linker_script.cmd b/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33/clang_ti_linker_script.cmd index e621f7891..0805b7776 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33/clang_ti_linker_script.cmd +++ b/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33/clang_ti_linker_script.cmd @@ -1,52 +1,80 @@ --stack_size=__STACK_SIZE --heap_size=__HEAP_SIZE --symbol_map=_start=_c_int00 +--entry_point=Reset_Handler +/* Macros for Stack/Seal */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __STACKSEAL_SIZE 8 #else #define __STACKSEAL_SIZE 0 #endif -__stack = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; -__stack_seal = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; -__stack_limit = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE; -#define __STACK_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1) -#define __STACK_LIMIT_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE) - MEMORY { -ROM0 : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE + ROM0 (RX) : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE + RAM0 (RW) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE +} -#if defined (__ROM1_BASE) - ROM1 : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE -#endif +--retain="*(.vectors)" +--retain="*(.intvecs)" + +SECTIONS +{ + /* 1. Vectors forced to the base of ROM */ + .intvecs : load = __ROM0_BASE + { + *(.vectors) + *(.intvecs) + } -RAM0 : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE + /* 2. Code and Read-Only Data */ + .text : + { + *(.text.Reset_Handler) + *(.text:_c_int00_noargs) + *(.text.main) + *(.text*) + } > ROM0 -#if defined (__RAM1_BASE) - RAM1 : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE + /* 3. CMSE Veneers */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + Veneer$$CMSE : {} > ROM0 #endif -} -SECTIONS -{ -.vectors: {} > 0x00000000 + .rodata : {} > ROM0 + .TI.crctab : {} > ROM0 -.text: palign=4 {} > ROM0 -.rodata: palign=4 {} > ROM0 + /* 4. Runtime Initialization Tables */ + .binit : {} > ROM0 + .cinit : {} > ROM0 + .pinit : {} > ROM0 + .init_array : {} > ROM0 + .fini_array : {} > ROM0 + .ovly : {} > ROM0 -.noinit: palign=4 {} > RAM0 -.data: palign=4 {} > RAM0 -.sysmem: palign=4 {} > RAM0 -.bss: type=NOINIT, palign=4 {} > RAM0 + /* 5. Initialized Data */ + .data : load = ROM0, run = RAM0, table(BINIT) -.stack: run=__STACK_LIMIT_ADDR, type=NOLOAD {} > RAM0 -#if __STACKSEAL_SIZE > 0 - .stackseal: run=__STACK_ADDR, type=NOLOAD {} > RAM0 -#endif + /* 6. Uninitialized Data */ + .bss : type = NOINIT {} > RAM0 + .sysmem : type = NOINIT {} > RAM0 + + /* 7. Stack & Security Seal */ + /* (HIGH) ensures these are placed at the end of RAM0 */ +GROUP : > RAM0 (HIGH) + { + .stack : type = NOINIT, palign = 8 { + __stack_limit = .; + . += __STACK_SIZE; + __stack = . - 1; + } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - Veneer$$CMSE: palign=8 {} > ROM0 + .stackseal : type = NOINIT, palign = 8 { + __stack_seal = .; + . += __STACKSEAL_SIZE; + } #endif + } } \ No newline at end of file diff --git a/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33/clang_ti_linker_script.cmd b/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33/clang_ti_linker_script.cmd index e621f7891..0805b7776 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33/clang_ti_linker_script.cmd +++ b/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33/clang_ti_linker_script.cmd @@ -1,52 +1,80 @@ --stack_size=__STACK_SIZE --heap_size=__HEAP_SIZE --symbol_map=_start=_c_int00 +--entry_point=Reset_Handler +/* Macros for Stack/Seal */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __STACKSEAL_SIZE 8 #else #define __STACKSEAL_SIZE 0 #endif -__stack = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; -__stack_seal = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; -__stack_limit = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE; -#define __STACK_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1) -#define __STACK_LIMIT_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE) - MEMORY { -ROM0 : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE + ROM0 (RX) : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE + RAM0 (RW) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE +} -#if defined (__ROM1_BASE) - ROM1 : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE -#endif +--retain="*(.vectors)" +--retain="*(.intvecs)" + +SECTIONS +{ + /* 1. Vectors forced to the base of ROM */ + .intvecs : load = __ROM0_BASE + { + *(.vectors) + *(.intvecs) + } -RAM0 : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE + /* 2. Code and Read-Only Data */ + .text : + { + *(.text.Reset_Handler) + *(.text:_c_int00_noargs) + *(.text.main) + *(.text*) + } > ROM0 -#if defined (__RAM1_BASE) - RAM1 : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE + /* 3. CMSE Veneers */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + Veneer$$CMSE : {} > ROM0 #endif -} -SECTIONS -{ -.vectors: {} > 0x00000000 + .rodata : {} > ROM0 + .TI.crctab : {} > ROM0 -.text: palign=4 {} > ROM0 -.rodata: palign=4 {} > ROM0 + /* 4. Runtime Initialization Tables */ + .binit : {} > ROM0 + .cinit : {} > ROM0 + .pinit : {} > ROM0 + .init_array : {} > ROM0 + .fini_array : {} > ROM0 + .ovly : {} > ROM0 -.noinit: palign=4 {} > RAM0 -.data: palign=4 {} > RAM0 -.sysmem: palign=4 {} > RAM0 -.bss: type=NOINIT, palign=4 {} > RAM0 + /* 5. Initialized Data */ + .data : load = ROM0, run = RAM0, table(BINIT) -.stack: run=__STACK_LIMIT_ADDR, type=NOLOAD {} > RAM0 -#if __STACKSEAL_SIZE > 0 - .stackseal: run=__STACK_ADDR, type=NOLOAD {} > RAM0 -#endif + /* 6. Uninitialized Data */ + .bss : type = NOINIT {} > RAM0 + .sysmem : type = NOINIT {} > RAM0 + + /* 7. Stack & Security Seal */ + /* (HIGH) ensures these are placed at the end of RAM0 */ +GROUP : > RAM0 (HIGH) + { + .stack : type = NOINIT, palign = 8 { + __stack_limit = .; + . += __STACK_SIZE; + __stack = . - 1; + } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - Veneer$$CMSE: palign=8 {} > ROM0 + .stackseal : type = NOINIT, palign = 8 { + __stack_seal = .; + . += __STACKSEAL_SIZE; + } #endif + } } \ No newline at end of file diff --git a/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/clang_ti_linker_script.cmd b/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/clang_ti_linker_script.cmd index e621f7891..0805b7776 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/clang_ti_linker_script.cmd +++ b/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/clang_ti_linker_script.cmd @@ -1,52 +1,80 @@ --stack_size=__STACK_SIZE --heap_size=__HEAP_SIZE --symbol_map=_start=_c_int00 +--entry_point=Reset_Handler +/* Macros for Stack/Seal */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __STACKSEAL_SIZE 8 #else #define __STACKSEAL_SIZE 0 #endif -__stack = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; -__stack_seal = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1; -__stack_limit = __ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE; -#define __STACK_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - 1) -#define __STACK_LIMIT_ADDR (__ROM0_BASE + __ROM0_SIZE - __STACKSEAL_SIZE - __STACK_SIZE) - MEMORY { -ROM0 : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE + ROM0 (RX) : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE + RAM0 (RW) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE +} -#if defined (__ROM1_BASE) - ROM1 : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE -#endif +--retain="*(.vectors)" +--retain="*(.intvecs)" + +SECTIONS +{ + /* 1. Vectors forced to the base of ROM */ + .intvecs : load = __ROM0_BASE + { + *(.vectors) + *(.intvecs) + } -RAM0 : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE + /* 2. Code and Read-Only Data */ + .text : + { + *(.text.Reset_Handler) + *(.text:_c_int00_noargs) + *(.text.main) + *(.text*) + } > ROM0 -#if defined (__RAM1_BASE) - RAM1 : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE + /* 3. CMSE Veneers */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + Veneer$$CMSE : {} > ROM0 #endif -} -SECTIONS -{ -.vectors: {} > 0x00000000 + .rodata : {} > ROM0 + .TI.crctab : {} > ROM0 -.text: palign=4 {} > ROM0 -.rodata: palign=4 {} > ROM0 + /* 4. Runtime Initialization Tables */ + .binit : {} > ROM0 + .cinit : {} > ROM0 + .pinit : {} > ROM0 + .init_array : {} > ROM0 + .fini_array : {} > ROM0 + .ovly : {} > ROM0 -.noinit: palign=4 {} > RAM0 -.data: palign=4 {} > RAM0 -.sysmem: palign=4 {} > RAM0 -.bss: type=NOINIT, palign=4 {} > RAM0 + /* 5. Initialized Data */ + .data : load = ROM0, run = RAM0, table(BINIT) -.stack: run=__STACK_LIMIT_ADDR, type=NOLOAD {} > RAM0 -#if __STACKSEAL_SIZE > 0 - .stackseal: run=__STACK_ADDR, type=NOLOAD {} > RAM0 -#endif + /* 6. Uninitialized Data */ + .bss : type = NOINIT {} > RAM0 + .sysmem : type = NOINIT {} > RAM0 + + /* 7. Stack & Security Seal */ + /* (HIGH) ensures these are placed at the end of RAM0 */ +GROUP : > RAM0 (HIGH) + { + .stack : type = NOINIT, palign = 8 { + __stack_limit = .; + . += __STACK_SIZE; + __stack = . - 1; + } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - Veneer$$CMSE: palign=8 {} > ROM0 + .stackseal : type = NOINIT, palign = 8 { + __stack_seal = .; + . += __STACKSEAL_SIZE; + } #endif + } } \ No newline at end of file diff --git a/CMSIS/CoreValidation/Project/Validation.csolution.yml b/CMSIS/CoreValidation/Project/Validation.csolution.yml index 443b1f75e..185969f28 100644 --- a/CMSIS/CoreValidation/Project/Validation.csolution.yml +++ b/CMSIS/CoreValidation/Project/Validation.csolution.yml @@ -16,9 +16,6 @@ solution: - for-compiler: IAR Link: - --semihosting - - for-compiler: CLANG_TI - Link: - - -Xlinker --map_file=map.txt packs: - pack: ARM::CMSIS diff --git a/CMSIS/CoreValidation/Project/build.py b/CMSIS/CoreValidation/Project/build.py index e557b28b2..1dde2ef68 100755 --- a/CMSIS/CoreValidation/Project/build.py +++ b/CMSIS/CoreValidation/Project/build.py @@ -297,10 +297,8 @@ def cbuild(config): def model_exec(config): cmdline = [MODEL_EXECUTABLE[config.device][0], "-q", "--simlimit", 5, "-f", model_config(config)] cmdline += MODEL_EXECUTABLE[config.device][1] - if config.device.has_bl() and (config.compiler == CompilerAxis.CLANG_TI): - cmdline += ["-a", f"{build_dir(config)}/{bl_output_dir(config)}/Bootloader.{config.compiler.image_ext}"] cmdline += ["-a", f"{build_dir(config)}/{output_dir(config)}/Validation.{config.compiler.image_ext}"] - if config.device.has_bl() and (config.compiler != CompilerAxis.CLANG_TI): + if config.device.has_bl(): cmdline += ["-a", f"{build_dir(config)}/{bl_output_dir(config)}/Bootloader.{config.compiler.image_ext}"] return cmdline diff --git a/CMSIS/CoreValidation/Source/CV_Framework.c b/CMSIS/CoreValidation/Source/CV_Framework.c index 7eacbe5d2..7a7b1ebfc 100644 --- a/CMSIS/CoreValidation/Source/CV_Framework.c +++ b/CMSIS/CoreValidation/Source/CV_Framework.c @@ -6,11 +6,6 @@ *----------------------------------------------------------------------------*/ #include "CV_Framework.h" #include "cmsis_cv.h" -#if defined(__clang__) && defined(__ti__) -#include "clang_ti_semihost.h" -/* Declare the initialization routine provided in clang_ti_semihost.c */ -extern void _system_post_cinit(void); -#endif /* Prototypes */ void ts_cmsis_cv(void); @@ -32,9 +27,6 @@ void closeDebug(void); Debug session dead end - debug script should close session here. */ void closeDebug(void) { -#if defined(__clang__) && defined(__ti__) - ARMSemihost_exit(); -#endif __NOP(); // Test completed } @@ -90,12 +82,6 @@ Program flow: -# Main thread is initialized */ void cmsis_cv (void) { - -#if defined(__clang__) && defined(__ti__) - /* Initialize semihosting file descriptors for STDOUT/STDERR */ - _system_post_cinit(); -#endif - /* Init test suite */ if (ts.Init != NULL) { ts.Init(); /* Init hardware */ From 97042d4de6b390598514033c12dab8d01268ea46 Mon Sep 17 00:00:00 2001 From: Shawn Mason <255018043+smmasongt@users.noreply.github.com> Date: Sun, 12 Apr 2026 19:48:07 -0400 Subject: [PATCH 12/17] Claude Code Review and Refactoring of TI Semihost Implementation --- .../App/Bootloader_Cortex-M/App.clayer.yml | 14 +- .../App/Validation_Cortex-M/App.clayer.yml | 4 +- .../Device/ARMCM0/clang_ti_linker_script.cmd | 52 +-- .../Device/ARMCM0P/clang_ti_linker_script.cmd | 52 +-- .../Device/ARMCM3/clang_ti_linker_script.cmd | 52 +-- .../Device/ARMCM33/clang_ti_linker_script.cmd | 52 +-- .../Device/ARMCM33/clang_ti_linker_script.cmd | 52 +-- .../Device/ARMCM33/clang_ti_linker_script.cmd | 52 +-- .../Device/ARMCM4/clang_ti_linker_script.cmd | 154 ++++--- CMSIS/CoreValidation/Source/CV_Framework.c | 1 + CMSIS/CoreValidation/Source/CV_Report.c | 2 +- .../clang_ti_fastmodel_cio.c | 81 ---- .../clang_ti_format_semihost.h | 134 ------ .../Clang_TI_Semihost/clang_ti_semihost.c | 422 +++--------------- .../Clang_TI_Semihost/clang_ti_semihost.h | 148 +++--- .../clang_ti_semihost_call.h | 43 -- .../clang_ti_vprintf_semihost.c | 96 ---- .../clang_ti_vprintf_semihost.h | 20 - 18 files changed, 361 insertions(+), 1070 deletions(-) delete mode 100644 CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_fastmodel_cio.c delete mode 100644 CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_format_semihost.h delete mode 100644 CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_semihost_call.h delete mode 100644 CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_vprintf_semihost.c delete mode 100644 CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_vprintf_semihost.h diff --git a/CMSIS/CoreValidation/Layer/App/Bootloader_Cortex-M/App.clayer.yml b/CMSIS/CoreValidation/Layer/App/Bootloader_Cortex-M/App.clayer.yml index 89ae8bc0b..2b5088c29 100644 --- a/CMSIS/CoreValidation/Layer/App/Bootloader_Cortex-M/App.clayer.yml +++ b/CMSIS/CoreValidation/Layer/App/Bootloader_Cortex-M/App.clayer.yml @@ -5,19 +5,7 @@ layer: # packs: # - pack: ARM::CMSIS - add-path: - - ../../../Include - - ../../../Source/Config - - ../../../Source/Clang_TI_Semihost - groups: - group: Source Files files: - - file: ./bootloader.c - - - group: TI Arm Clang Compiler Semihost Support - for-compiler: CLANG_TI - files: - - file: ../../../Source/Clang_TI_Semihost/clang_ti_fastmodel_cio.c - - file: ../../../Source/Clang_TI_Semihost/clang_ti_semihost.c - - file: ../../../Source/Clang_TI_Semihost/clang_ti_vprintf_semihost.c + - file: ./bootloader.c \ No newline at end of file diff --git a/CMSIS/CoreValidation/Layer/App/Validation_Cortex-M/App.clayer.yml b/CMSIS/CoreValidation/Layer/App/Validation_Cortex-M/App.clayer.yml index 941639499..17144777e 100644 --- a/CMSIS/CoreValidation/Layer/App/Validation_Cortex-M/App.clayer.yml +++ b/CMSIS/CoreValidation/Layer/App/Validation_Cortex-M/App.clayer.yml @@ -74,6 +74,4 @@ layer: - group: TI Arm Clang Compiler Semihost Support for-compiler: CLANG_TI files: - - file: ../../../Source/Clang_TI_Semihost/clang_ti_fastmodel_cio.c - - file: ../../../Source/Clang_TI_Semihost/clang_ti_semihost.c - - file: ../../../Source/Clang_TI_Semihost/clang_ti_vprintf_semihost.c \ No newline at end of file + - file: ../../../Source/Clang_TI_Semihost/clang_ti_semihost.c \ No newline at end of file diff --git a/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/clang_ti_linker_script.cmd b/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/clang_ti_linker_script.cmd index 0805b7776..064b95107 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/clang_ti_linker_script.cmd +++ b/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/clang_ti_linker_script.cmd @@ -2,6 +2,8 @@ --heap_size=__HEAP_SIZE --symbol_map=_start=_c_int00 --entry_point=Reset_Handler +--retain="*(.vectors)" +--retain="*(.intvecs)" /* Macros for Stack/Seal */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) @@ -16,26 +18,17 @@ MEMORY RAM0 (RW) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE } ---retain="*(.vectors)" ---retain="*(.intvecs)" - SECTIONS { /* 1. Vectors forced to the base of ROM */ - .intvecs : load = __ROM0_BASE + .intvecs : load = __ROM0_BASE { *(.vectors) *(.intvecs) } /* 2. Code and Read-Only Data */ - .text : - { - *(.text.Reset_Handler) - *(.text:_c_int00_noargs) - *(.text.main) - *(.text*) - } > ROM0 + .text : {} > ROM0 /* 3. CMSE Veneers */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) @@ -46,35 +39,38 @@ SECTIONS .TI.crctab : {} > ROM0 /* 4. Runtime Initialization Tables */ - .binit : {} > ROM0 - .cinit : {} > ROM0 - .pinit : {} > ROM0 - .init_array : {} > ROM0 - .fini_array : {} > ROM0 - .ovly : {} > ROM0 + .binit : {} > ROM0 + .cinit : {} > ROM0 + .pinit : {} > ROM0 + .init_array : {} > ROM0 + .fini_array : {} > ROM0 + .ovly : {} > ROM0 /* 5. Initialized Data */ - .data : load = ROM0, run = RAM0, table(BINIT) + .data : load = ROM0, run = RAM0, table(BINIT) /* 6. Uninitialized Data */ - .bss : type = NOINIT {} > RAM0 - .sysmem : type = NOINIT {} > RAM0 + .bss : type = NOINIT {} > RAM0 + .sysmem : type = NOINIT {} > RAM0 /* 7. Stack & Security Seal */ /* (HIGH) ensures these are placed at the end of RAM0 */ -GROUP : > RAM0 (HIGH) + GROUP : > RAM0 (HIGH) { - .stack : type = NOINIT, palign = 8 { - __stack_limit = .; + .stack : type = NOINIT, palign = 8 + { + __stack_limit = .; . += __STACK_SIZE; - __stack = . - 1; - } + __INITIAL_SP = .; /* CMSIS startup: initial SP loaded from vector table (8-byte aligned) */ + __stack = . - 1; /* TI CRT _c_int00 compatibility: CRT computes SP = __stack + 1 */ + } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - .stackseal : type = NOINIT, palign = 8 { - __stack_seal = .; + .stackseal : type = NOINIT, palign = 8 + { + __stack_seal = .; . += __STACKSEAL_SIZE; - } + } #endif } } \ No newline at end of file diff --git a/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/clang_ti_linker_script.cmd b/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/clang_ti_linker_script.cmd index 0805b7776..064b95107 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/clang_ti_linker_script.cmd +++ b/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/clang_ti_linker_script.cmd @@ -2,6 +2,8 @@ --heap_size=__HEAP_SIZE --symbol_map=_start=_c_int00 --entry_point=Reset_Handler +--retain="*(.vectors)" +--retain="*(.intvecs)" /* Macros for Stack/Seal */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) @@ -16,26 +18,17 @@ MEMORY RAM0 (RW) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE } ---retain="*(.vectors)" ---retain="*(.intvecs)" - SECTIONS { /* 1. Vectors forced to the base of ROM */ - .intvecs : load = __ROM0_BASE + .intvecs : load = __ROM0_BASE { *(.vectors) *(.intvecs) } /* 2. Code and Read-Only Data */ - .text : - { - *(.text.Reset_Handler) - *(.text:_c_int00_noargs) - *(.text.main) - *(.text*) - } > ROM0 + .text : {} > ROM0 /* 3. CMSE Veneers */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) @@ -46,35 +39,38 @@ SECTIONS .TI.crctab : {} > ROM0 /* 4. Runtime Initialization Tables */ - .binit : {} > ROM0 - .cinit : {} > ROM0 - .pinit : {} > ROM0 - .init_array : {} > ROM0 - .fini_array : {} > ROM0 - .ovly : {} > ROM0 + .binit : {} > ROM0 + .cinit : {} > ROM0 + .pinit : {} > ROM0 + .init_array : {} > ROM0 + .fini_array : {} > ROM0 + .ovly : {} > ROM0 /* 5. Initialized Data */ - .data : load = ROM0, run = RAM0, table(BINIT) + .data : load = ROM0, run = RAM0, table(BINIT) /* 6. Uninitialized Data */ - .bss : type = NOINIT {} > RAM0 - .sysmem : type = NOINIT {} > RAM0 + .bss : type = NOINIT {} > RAM0 + .sysmem : type = NOINIT {} > RAM0 /* 7. Stack & Security Seal */ /* (HIGH) ensures these are placed at the end of RAM0 */ -GROUP : > RAM0 (HIGH) + GROUP : > RAM0 (HIGH) { - .stack : type = NOINIT, palign = 8 { - __stack_limit = .; + .stack : type = NOINIT, palign = 8 + { + __stack_limit = .; . += __STACK_SIZE; - __stack = . - 1; - } + __INITIAL_SP = .; /* CMSIS startup: initial SP loaded from vector table (8-byte aligned) */ + __stack = . - 1; /* TI CRT _c_int00 compatibility: CRT computes SP = __stack + 1 */ + } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - .stackseal : type = NOINIT, palign = 8 { - __stack_seal = .; + .stackseal : type = NOINIT, palign = 8 + { + __stack_seal = .; . += __STACKSEAL_SIZE; - } + } #endif } } \ No newline at end of file diff --git a/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/clang_ti_linker_script.cmd b/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/clang_ti_linker_script.cmd index 0805b7776..064b95107 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/clang_ti_linker_script.cmd +++ b/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/clang_ti_linker_script.cmd @@ -2,6 +2,8 @@ --heap_size=__HEAP_SIZE --symbol_map=_start=_c_int00 --entry_point=Reset_Handler +--retain="*(.vectors)" +--retain="*(.intvecs)" /* Macros for Stack/Seal */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) @@ -16,26 +18,17 @@ MEMORY RAM0 (RW) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE } ---retain="*(.vectors)" ---retain="*(.intvecs)" - SECTIONS { /* 1. Vectors forced to the base of ROM */ - .intvecs : load = __ROM0_BASE + .intvecs : load = __ROM0_BASE { *(.vectors) *(.intvecs) } /* 2. Code and Read-Only Data */ - .text : - { - *(.text.Reset_Handler) - *(.text:_c_int00_noargs) - *(.text.main) - *(.text*) - } > ROM0 + .text : {} > ROM0 /* 3. CMSE Veneers */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) @@ -46,35 +39,38 @@ SECTIONS .TI.crctab : {} > ROM0 /* 4. Runtime Initialization Tables */ - .binit : {} > ROM0 - .cinit : {} > ROM0 - .pinit : {} > ROM0 - .init_array : {} > ROM0 - .fini_array : {} > ROM0 - .ovly : {} > ROM0 + .binit : {} > ROM0 + .cinit : {} > ROM0 + .pinit : {} > ROM0 + .init_array : {} > ROM0 + .fini_array : {} > ROM0 + .ovly : {} > ROM0 /* 5. Initialized Data */ - .data : load = ROM0, run = RAM0, table(BINIT) + .data : load = ROM0, run = RAM0, table(BINIT) /* 6. Uninitialized Data */ - .bss : type = NOINIT {} > RAM0 - .sysmem : type = NOINIT {} > RAM0 + .bss : type = NOINIT {} > RAM0 + .sysmem : type = NOINIT {} > RAM0 /* 7. Stack & Security Seal */ /* (HIGH) ensures these are placed at the end of RAM0 */ -GROUP : > RAM0 (HIGH) + GROUP : > RAM0 (HIGH) { - .stack : type = NOINIT, palign = 8 { - __stack_limit = .; + .stack : type = NOINIT, palign = 8 + { + __stack_limit = .; . += __STACK_SIZE; - __stack = . - 1; - } + __INITIAL_SP = .; /* CMSIS startup: initial SP loaded from vector table (8-byte aligned) */ + __stack = . - 1; /* TI CRT _c_int00 compatibility: CRT computes SP = __stack + 1 */ + } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - .stackseal : type = NOINIT, palign = 8 { - __stack_seal = .; + .stackseal : type = NOINIT, palign = 8 + { + __stack_seal = .; . += __STACKSEAL_SIZE; - } + } #endif } } \ No newline at end of file diff --git a/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33/clang_ti_linker_script.cmd b/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33/clang_ti_linker_script.cmd index 0805b7776..86fb57e67 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33/clang_ti_linker_script.cmd +++ b/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33/clang_ti_linker_script.cmd @@ -2,6 +2,8 @@ --heap_size=__HEAP_SIZE --symbol_map=_start=_c_int00 --entry_point=Reset_Handler +--retain="*(.vectors)" +--retain="*(.intvecs)" /* Macros for Stack/Seal */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) @@ -16,26 +18,17 @@ MEMORY RAM0 (RW) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE } ---retain="*(.vectors)" ---retain="*(.intvecs)" - SECTIONS { /* 1. Vectors forced to the base of ROM */ - .intvecs : load = __ROM0_BASE + .intvecs : load = __ROM0_BASE { *(.vectors) *(.intvecs) } /* 2. Code and Read-Only Data */ - .text : - { - *(.text.Reset_Handler) - *(.text:_c_int00_noargs) - *(.text.main) - *(.text*) - } > ROM0 + .text : {} > ROM0 /* 3. CMSE Veneers */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) @@ -46,35 +39,38 @@ SECTIONS .TI.crctab : {} > ROM0 /* 4. Runtime Initialization Tables */ - .binit : {} > ROM0 - .cinit : {} > ROM0 - .pinit : {} > ROM0 - .init_array : {} > ROM0 - .fini_array : {} > ROM0 - .ovly : {} > ROM0 + .binit : {} > ROM0 + .cinit : {} > ROM0 + .pinit : {} > ROM0 + .init_array : {} > ROM0 + .fini_array : {} > ROM0 + .ovly : {} > ROM0 /* 5. Initialized Data */ - .data : load = ROM0, run = RAM0, table(BINIT) + .data : load = ROM0, run = RAM0, table(BINIT) /* 6. Uninitialized Data */ - .bss : type = NOINIT {} > RAM0 - .sysmem : type = NOINIT {} > RAM0 + .bss : type = NOINIT {} > RAM0 + .sysmem : type = NOINIT {} > RAM0 /* 7. Stack & Security Seal */ /* (HIGH) ensures these are placed at the end of RAM0 */ -GROUP : > RAM0 (HIGH) + GROUP : > RAM0 (HIGH) { - .stack : type = NOINIT, palign = 8 { - __stack_limit = .; + .stack : type = NOINIT, palign = 8 + { + __stack_limit = .; . += __STACK_SIZE; - __stack = . - 1; - } + __INITIAL_SP = .; /* CMSIS startup: initial SP loaded from vector table (8-byte aligned) */ + __stack = . - 1; /* TI CRT _c_int00 compatibility: CRT computes SP = __stack + 1 */ + } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - .stackseal : type = NOINIT, palign = 8 { - __stack_seal = .; + .stackseal : type = NOINIT, palign = 8 + { + __stack_seal = .; . += __STACKSEAL_SIZE; - } + } #endif } } \ No newline at end of file diff --git a/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33/clang_ti_linker_script.cmd b/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33/clang_ti_linker_script.cmd index 0805b7776..064b95107 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33/clang_ti_linker_script.cmd +++ b/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33/clang_ti_linker_script.cmd @@ -2,6 +2,8 @@ --heap_size=__HEAP_SIZE --symbol_map=_start=_c_int00 --entry_point=Reset_Handler +--retain="*(.vectors)" +--retain="*(.intvecs)" /* Macros for Stack/Seal */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) @@ -16,26 +18,17 @@ MEMORY RAM0 (RW) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE } ---retain="*(.vectors)" ---retain="*(.intvecs)" - SECTIONS { /* 1. Vectors forced to the base of ROM */ - .intvecs : load = __ROM0_BASE + .intvecs : load = __ROM0_BASE { *(.vectors) *(.intvecs) } /* 2. Code and Read-Only Data */ - .text : - { - *(.text.Reset_Handler) - *(.text:_c_int00_noargs) - *(.text.main) - *(.text*) - } > ROM0 + .text : {} > ROM0 /* 3. CMSE Veneers */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) @@ -46,35 +39,38 @@ SECTIONS .TI.crctab : {} > ROM0 /* 4. Runtime Initialization Tables */ - .binit : {} > ROM0 - .cinit : {} > ROM0 - .pinit : {} > ROM0 - .init_array : {} > ROM0 - .fini_array : {} > ROM0 - .ovly : {} > ROM0 + .binit : {} > ROM0 + .cinit : {} > ROM0 + .pinit : {} > ROM0 + .init_array : {} > ROM0 + .fini_array : {} > ROM0 + .ovly : {} > ROM0 /* 5. Initialized Data */ - .data : load = ROM0, run = RAM0, table(BINIT) + .data : load = ROM0, run = RAM0, table(BINIT) /* 6. Uninitialized Data */ - .bss : type = NOINIT {} > RAM0 - .sysmem : type = NOINIT {} > RAM0 + .bss : type = NOINIT {} > RAM0 + .sysmem : type = NOINIT {} > RAM0 /* 7. Stack & Security Seal */ /* (HIGH) ensures these are placed at the end of RAM0 */ -GROUP : > RAM0 (HIGH) + GROUP : > RAM0 (HIGH) { - .stack : type = NOINIT, palign = 8 { - __stack_limit = .; + .stack : type = NOINIT, palign = 8 + { + __stack_limit = .; . += __STACK_SIZE; - __stack = . - 1; - } + __INITIAL_SP = .; /* CMSIS startup: initial SP loaded from vector table (8-byte aligned) */ + __stack = . - 1; /* TI CRT _c_int00 compatibility: CRT computes SP = __stack + 1 */ + } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - .stackseal : type = NOINIT, palign = 8 { - __stack_seal = .; + .stackseal : type = NOINIT, palign = 8 + { + __stack_seal = .; . += __STACKSEAL_SIZE; - } + } #endif } } \ No newline at end of file diff --git a/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33/clang_ti_linker_script.cmd b/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33/clang_ti_linker_script.cmd index 0805b7776..064b95107 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33/clang_ti_linker_script.cmd +++ b/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33/clang_ti_linker_script.cmd @@ -2,6 +2,8 @@ --heap_size=__HEAP_SIZE --symbol_map=_start=_c_int00 --entry_point=Reset_Handler +--retain="*(.vectors)" +--retain="*(.intvecs)" /* Macros for Stack/Seal */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) @@ -16,26 +18,17 @@ MEMORY RAM0 (RW) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE } ---retain="*(.vectors)" ---retain="*(.intvecs)" - SECTIONS { /* 1. Vectors forced to the base of ROM */ - .intvecs : load = __ROM0_BASE + .intvecs : load = __ROM0_BASE { *(.vectors) *(.intvecs) } /* 2. Code and Read-Only Data */ - .text : - { - *(.text.Reset_Handler) - *(.text:_c_int00_noargs) - *(.text.main) - *(.text*) - } > ROM0 + .text : {} > ROM0 /* 3. CMSE Veneers */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) @@ -46,35 +39,38 @@ SECTIONS .TI.crctab : {} > ROM0 /* 4. Runtime Initialization Tables */ - .binit : {} > ROM0 - .cinit : {} > ROM0 - .pinit : {} > ROM0 - .init_array : {} > ROM0 - .fini_array : {} > ROM0 - .ovly : {} > ROM0 + .binit : {} > ROM0 + .cinit : {} > ROM0 + .pinit : {} > ROM0 + .init_array : {} > ROM0 + .fini_array : {} > ROM0 + .ovly : {} > ROM0 /* 5. Initialized Data */ - .data : load = ROM0, run = RAM0, table(BINIT) + .data : load = ROM0, run = RAM0, table(BINIT) /* 6. Uninitialized Data */ - .bss : type = NOINIT {} > RAM0 - .sysmem : type = NOINIT {} > RAM0 + .bss : type = NOINIT {} > RAM0 + .sysmem : type = NOINIT {} > RAM0 /* 7. Stack & Security Seal */ /* (HIGH) ensures these are placed at the end of RAM0 */ -GROUP : > RAM0 (HIGH) + GROUP : > RAM0 (HIGH) { - .stack : type = NOINIT, palign = 8 { - __stack_limit = .; + .stack : type = NOINIT, palign = 8 + { + __stack_limit = .; . += __STACK_SIZE; - __stack = . - 1; - } + __INITIAL_SP = .; /* CMSIS startup: initial SP loaded from vector table (8-byte aligned) */ + __stack = . - 1; /* TI CRT _c_int00 compatibility: CRT computes SP = __stack + 1 */ + } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - .stackseal : type = NOINIT, palign = 8 { - __stack_seal = .; + .stackseal : type = NOINIT, palign = 8 + { + __stack_seal = .; . += __STACKSEAL_SIZE; - } + } #endif } } \ No newline at end of file diff --git a/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/clang_ti_linker_script.cmd b/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/clang_ti_linker_script.cmd index 0805b7776..3bc7c4949 100644 --- a/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/clang_ti_linker_script.cmd +++ b/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/clang_ti_linker_script.cmd @@ -1,80 +1,76 @@ ---stack_size=__STACK_SIZE ---heap_size=__HEAP_SIZE ---symbol_map=_start=_c_int00 ---entry_point=Reset_Handler - -/* Macros for Stack/Seal */ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define __STACKSEAL_SIZE 8 -#else - #define __STACKSEAL_SIZE 0 -#endif - -MEMORY -{ - ROM0 (RX) : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE - RAM0 (RW) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE -} - ---retain="*(.vectors)" ---retain="*(.intvecs)" - -SECTIONS -{ - /* 1. Vectors forced to the base of ROM */ - .intvecs : load = __ROM0_BASE - { - *(.vectors) - *(.intvecs) - } - - /* 2. Code and Read-Only Data */ - .text : - { - *(.text.Reset_Handler) - *(.text:_c_int00_noargs) - *(.text.main) - *(.text*) - } > ROM0 - - /* 3. CMSE Veneers */ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - Veneer$$CMSE : {} > ROM0 -#endif - - .rodata : {} > ROM0 - .TI.crctab : {} > ROM0 - - /* 4. Runtime Initialization Tables */ - .binit : {} > ROM0 - .cinit : {} > ROM0 - .pinit : {} > ROM0 - .init_array : {} > ROM0 - .fini_array : {} > ROM0 - .ovly : {} > ROM0 - - /* 5. Initialized Data */ - .data : load = ROM0, run = RAM0, table(BINIT) - - /* 6. Uninitialized Data */ - .bss : type = NOINIT {} > RAM0 - .sysmem : type = NOINIT {} > RAM0 - - /* 7. Stack & Security Seal */ - /* (HIGH) ensures these are placed at the end of RAM0 */ -GROUP : > RAM0 (HIGH) - { - .stack : type = NOINIT, palign = 8 { - __stack_limit = .; - . += __STACK_SIZE; - __stack = . - 1; - } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - .stackseal : type = NOINIT, palign = 8 { - __stack_seal = .; - . += __STACKSEAL_SIZE; - } -#endif - } +--stack_size=__STACK_SIZE +--heap_size=__HEAP_SIZE +--symbol_map=_start=_c_int00 +--entry_point=Reset_Handler +--retain="*(.vectors)" +--retain="*(.intvecs)" + +/* Macros for Stack/Seal */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define __STACKSEAL_SIZE 8 +#else + #define __STACKSEAL_SIZE 0 +#endif + +MEMORY +{ + ROM0 (RX) : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE + RAM0 (RW) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE +} + +SECTIONS +{ + /* 1. Vectors forced to the base of ROM */ + .intvecs : load = __ROM0_BASE + { + *(.vectors) + *(.intvecs) + } + + /* 2. Code and Read-Only Data */ + .text : {} > ROM0 + + /* 3. CMSE Veneers */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + Veneer$$CMSE : {} > ROM0 +#endif + + .rodata : {} > ROM0 + .TI.crctab : {} > ROM0 + + /* 4. Runtime Initialization Tables */ + .binit : {} > ROM0 + .cinit : {} > ROM0 + .pinit : {} > ROM0 + .init_array : {} > ROM0 + .fini_array : {} > ROM0 + .ovly : {} > ROM0 + + /* 5. Initialized Data */ + .data : load = ROM0, run = RAM0, table(BINIT) + + /* 6. Uninitialized Data */ + .bss : type = NOINIT {} > RAM0 + .sysmem : type = NOINIT {} > RAM0 + + /* 7. Stack & Security Seal */ + /* (HIGH) ensures these are placed at the end of RAM0 */ + GROUP : > RAM0 (HIGH) + { + .stack : type = NOINIT, palign = 8 + { + __stack_limit = .; + . += __STACK_SIZE; + __INITIAL_SP = .; /* CMSIS startup: initial SP loaded from vector table (8-byte aligned) */ + __stack = . - 1; /* TI CRT _c_int00 compatibility: CRT computes SP = __stack + 1 */ + } + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + .stackseal : type = NOINIT, palign = 8 + { + __stack_seal = .; + . += __STACKSEAL_SIZE; + } +#endif + } } \ No newline at end of file diff --git a/CMSIS/CoreValidation/Source/CV_Framework.c b/CMSIS/CoreValidation/Source/CV_Framework.c index 7a7b1ebfc..112c82866 100644 --- a/CMSIS/CoreValidation/Source/CV_Framework.c +++ b/CMSIS/CoreValidation/Source/CV_Framework.c @@ -82,6 +82,7 @@ Program flow: -# Main thread is initialized */ void cmsis_cv (void) { + /* Init test suite */ if (ts.Init != NULL) { ts.Init(); /* Init hardware */ diff --git a/CMSIS/CoreValidation/Source/CV_Report.c b/CMSIS/CoreValidation/Source/CV_Report.c index 2156836e0..ea7a26039 100644 --- a/CMSIS/CoreValidation/Source/CV_Report.c +++ b/CMSIS/CoreValidation/Source/CV_Report.c @@ -8,7 +8,7 @@ #include #include #if defined(__clang__) && defined(__ti__) -#include "clang_ti_vprintf_semihost.h" +#include "clang_ti_semihost.h" #endif TEST_REPORT test_report; diff --git a/CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_fastmodel_cio.c b/CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_fastmodel_cio.c deleted file mode 100644 index e9c4789a8..000000000 --- a/CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_fastmodel_cio.c +++ /dev/null @@ -1,81 +0,0 @@ -/*****************************************************************************/ -/* FASTMODEL_CIO.C v##### - Setup Arm FastModel as standard device for CIO */ -/* Copyright (c) 2024@%%%% Texas Instruments Incorporated */ -/*****************************************************************************/ -/*****************************************************************************/ -/* CLANG_TI_FASTMODEL_CIO.C */ -/*****************************************************************************/ - -#include -#include -#include -#include -#include -#include "semihost.h" - -//---------------------------------------------------------------------------- -// __FM_INIT - SET RESET VECTOR AND SVC STATE REQUIRED BY SVC SEMIHOSTING. -//---------------------------------------------------------------------------- -__attribute__((naked,retain)) -void __FM_init() -{ -#if __ARM_ARCH_8R__ == 1 - __asm volatile( - "MRS r0, cpsr\n" - "MOV r1, #0x13\n" // SET SVC MODE - "BFI r0, r1, #0, #5\n" - "MSR spsr_cxsf, r0\n" - "LDR r0, =_c_int00\n" // Force reset vector to _c_int00 - "MSR elr_hyp, r0\n" - "DSB\n" - "ISB\n" - "ERET\n" - ); -#else - __asm volatile( - "b _c_int00\n" - ); -#endif -} - -//---------------------------------------------------------------------------- -// PARSE_CMDLINE - PARSE THE FASTMODELS SIMULATOR COMMAND LINE FOR ARGUMENTS. -// -// The script that invokes the simulator passes a command line argument to the -// simulator containing the arguments in the form of a space-separated string -// in which the first string is the value of argc: "argc arg0 arg1 ...". It -// passes this using '-C Dhrystone.Core.cpu0.semihosting-cmd_line="${ENVPATH} -// $# ${ARGS}"'.This function is responsible for tokenizing argc and the -// arguments and copying them into the memory location of __c_args__. -//---------------------------------------------------------------------------- -void parse_cmdline(ARGS *pargs, char* buf, char *env) -{ - uint32_t argv_addr = (uint32_t)pargs->argv; - - // Tokenize the command line. - char* token = strtok(buf, " "); - if (token) - { - // CODEGEN-12869: The first token is ENV. - strncpy(env, token, strlen(token) + 1); - token = strtok(NULL," "); - - // The second token is ARGC. - pargs->argc = atoi(token); - - uint32_t aptr = argv_addr + (4 * (pargs->argc + 1)); - - // Process and copy the argvs. - int i = 0; - char *arg = strtok(NULL, " "); - while (arg != NULL) { - memcpy((void*)(argv_addr + i++ * 4), (unsigned char*)&aptr, 4); - - size_t len = strlen(arg) + 1; - strncpy((char*)aptr, (char*)arg, len); - aptr += len; - - arg = strtok(NULL, " "); - } - } -} diff --git a/CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_format_semihost.h b/CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_format_semihost.h deleted file mode 100644 index 50e09a1ff..000000000 --- a/CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_format_semihost.h +++ /dev/null @@ -1,134 +0,0 @@ -/*****************************************************************************/ -/* FORMAT.H */ -/* */ -/* Copyright (c) 1995 Texas Instruments Incorporated */ -/* http://www.ti.com/ */ -/* */ -/* Redistribution and use in source and binary forms, with or without */ -/* modification, are permitted provided that the following conditions */ -/* are met: */ -/* */ -/* Redistributions of source code must retain the above copyright */ -/* notice, this list of conditions and the following disclaimer. */ -/* */ -/* Redistributions in binary form must reproduce the above copyright */ -/* notice, this list of conditions and the following disclaimer in */ -/* the documentation and/or other materials provided with the */ -/* distribution. */ -/* */ -/* Neither the name of Texas Instruments Incorporated nor the names */ -/* of its contributors may be used to endorse or promote products */ -/* derived from this software without specific prior written */ -/* permission. */ -/* */ -/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ -/* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ -/* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ -/* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ -/* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ -/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ -/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ -/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ -/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ -/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ -/* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* */ -/*****************************************************************************/ - -/*****************************************************************************/ -/* Structures and macros used in printf and scanf */ -/*****************************************************************************/ -#ifndef __CLANG_TI_FORMAT_SEMIHOST_H -#define __CLANG_TI_FORMAT_SEMIHOST_H -#include - -#if defined (MINIMAL) -#define FORMAT_CONVERSION_BUFSIZE 32 -#elif defined (__MSP430__) -#define F_CONVERSION_BUFSIZE 100 -#define FLOAT_VALUE_BUFSIZE 32 -#else -/****************************************************************************/ -/* The minimum max conversion size to be C89 compliant is 509 */ -/****************************************************************************/ -#define F_CONVERSION_BUFSIZE 510 -#define FLOAT_VALUE_BUFSIZE 100 -#endif - -#if !defined(MINIMAL) -#define FORMAT_CONVERSION_BUFSIZE F_CONVERSION_BUFSIZE -#endif - - int __TI_scanfi(void *inp, const char *_format, va_list _ap, - int (*_chkmbc)(void **inp, char **_format, int *num_read), - int (*_inpchar)(void **inp), - void (*_uninpchar)(void **inp, int outchar)); - - /**************************************************************************/ - /* _FIELD STRUCTURE AND MACROS USED FOR PRINTF AND SCANF */ - /**************************************************************************/ - typedef struct { - unsigned int flags; /* Format flags */ - int fwidth; /* Field width */ - int precision; /* Field precision */ - char conv; /* Conversion specifier */ -#if defined(VECTOR_PRINTF_SUPPORT) - int vn; /* Vector size expressed in the format */ - /*************************************************************************/ - /* CODEGEN-4880: WORKAROUND */ - /*************************************************************************/ - /* The variables below are required to handle a special case for */ - /* char2 or uchar2 arguments. Explanation given in _pproc_v_dioux */ - /*************************************************************************/ - uchar2 arguc2; - int arguc2_leftover; - int last_v_dioux_arg_size; - /*************************************************************************/ - /* CODEGEN-4880: WORKAROUND END */ - /*************************************************************************/ -#endif - } _PFIELD; - - typedef struct { - unsigned int flags; /* Format flags */ - int fwidth; /* Field width */ - int precision; /* Field precision */ - char scanset[96]; /* Scanset used for '[' conversion */ - char conv; /* Conversion specifier */ - } _SFIELD; - -/****************/ -/* PRINTF FLAGS */ -/****************/ - -#define _PFMINUS 0x01 -#define _PFPLUS 0x02 -#define _PFSPACE 0x04 -#define _PFPOUND 0x08 -#define _PFZERO 0x10 - -/***************/ -/* SCANF FLAGS */ -/***************/ - -#define _SFSTAR 0x01 -#define _SFCIRC 0x02 - -/****************/ -/* MUTUAL FLAGS */ -/****************/ - -#define _MFH 0x20 -#define _MFL 0x40 -#define _MFLD 0x80 -#define _MFLL 0x100 -#define _MFHH 0x200 -#define _MFI40 0x400 -#define _MFJ 0x800 -#define _MFZ 0x1000 -#define _MFT 0x2000 -#if defined(VECTOR_PRINTF_SUPPORT) -#define _MFHL 0x3000 /* OpenCL 1.2 vector specifier flag */ -#endif - -#endif \ No newline at end of file diff --git a/CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_semihost.c b/CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_semihost.c index 1ac2c42eb..d2d509b9f 100644 --- a/CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_semihost.c +++ b/CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_semihost.c @@ -1,371 +1,51 @@ -/*****************************************************************************/ -/* SEMIHOST.C v##### - Generic C functions for interfacing with simulators */ -/* that support ARM-conformant semihosting */ -/* Copyright (c) 2024@%%%% Texas Instruments Incorporated */ -/*****************************************************************************/ -/*****************************************************************************/ -/* CLANG_TI_SEMIHOST.C - Generic C functions for interfacing with */ -/* simulators that support ARM-conformant semihosting */ -/*****************************************************************************/ -#include -#include -#include -#include -#include -#include // This is a standard header, no need to rename. -#include "clang_ti_semihost.h" -#include "clang_ti_semihost_call.h" - -//---------------------------------------------------------------------------- -// _SYSTEM_POST_CINIT -- SETUP ARGV ARGUMENTS AFTER VARIABLE INITIALIZATION. -//---------------------------------------------------------------------------- -static int sys_open(const char *path, unsigned flags); - -static int fd_stdout, fd_stderr; - -extern __attribute__((weak)) ARGS __c_args__; - -#define ENV_SIZE 1000 -char __c_args_env__[ENV_SIZE]; - -void _system_post_cinit() -{ - // Setup c_args. - if (&__c_args__ != NULL) - { - register ARGS *pargs = (ARGS*)&__c_args__; - char buf[128]; - struct { - int32_t arg1; - int32_t arg2; - } arg = { - .arg1 = (int32_t) buf, - .arg2 = sizeof(buf) - }; - - pargs->argc = 0; - int32_t ret = ARMSemihost_Call(SYS_GET_CMDLINE, (int32_t) &arg); - if (ret == 0) - parse_cmdline(pargs, buf, __c_args_env__); - } - - // Open and save off STDIO file descriptors. - fd_stdout = sys_open(":tt", 4); - fd_stderr = sys_open(":tt", 4); -} - -//---------------------------------------------------------------------------- -// ARMSemihost_OPEN - OPEN A FILE DESCRIPTOR TO A FILE. -//---------------------------------------------------------------------------- -static int sys_open(const char *path, unsigned flags) { - struct { - int32_t arg1; - int32_t arg2; - int32_t arg3; - } arg = { - .arg1 = (int32_t) path, - .arg2 = flags, - .arg3 = strlen(path) - }; - - return (int) ARMSemihost_Call(SYS_OPEN, (int32_t) &arg); -} - -// Semihosting file open modes. -#define SH_OPEN_R 0 -#define SH_OPEN_R_PLUS 2 -#define SH_OPEN_W 4 -#define SH_OPEN_W_PLUS 6 -#define SH_OPEN_A 8 -#define SH_OPEN_A_PLUS 10 - -#define SH_OPEN_R_B 1 -#define SH_OPEN_R_PLUS_B 3 -#define SH_OPEN_W_B 5 -#define SH_OPEN_W_PLUS_B 7 -#define SH_OPEN_A_B 9 -#define SH_OPEN_A_PLUS_B 11 - -int ARMSemihost_open(const char *path, unsigned flags, int llv_fd) -{ - int semiflags = 0; - - // Translate from open() flags to the semihosting file open mode. - // O_RDONLY (0x0000) open for reading - // O_WRONLY (0x0001) open for writing - // O_RDWR (0x0002) open for read & write - // O_APPEND (0x0008) append on each write - // O_CREAT (0x0200) open with file create - // O_TRUNC (0x0400) open with truncation - // O_EXCL (0x0800) open exclusive - // O_BINARY (0x8000) open in binary mode - switch (flags & (O_RDONLY|O_WRONLY|O_RDWR)) { - case O_RDONLY: - semiflags = SH_OPEN_R; /* 'r' */ - break; - case O_WRONLY: - if (flags & (O_TRUNC | O_EXCL)) - semiflags = SH_OPEN_W; /* 'w' */ - else if (flags & O_APPEND) - semiflags = SH_OPEN_A; /* 'a' */ - break; - default: - semiflags = SH_OPEN_R_PLUS; /* 'r+' */ - if (flags & (O_TRUNC | O_EXCL)) - semiflags = SH_OPEN_W_PLUS; /* 'w+' */ - else if (flags & O_APPEND) - semiflags = SH_OPEN_A_PLUS; /* 'a+' */ - break; - } - - // When opening a file with exclusive write access, verify that - // the file does not already exist by attempting to read it. - // If the file exists, return -1 to indicate a file open error. - if (flags & O_EXCL) { - int fd = sys_open(path, SH_OPEN_R); - if (0 <= fd) { - ARMSemihost_close(fd); - return -1; - } - } - - if (flags & O_BINARY) - semiflags |= 0x1; - - return (int) sys_open(path, semiflags); -} - -//---------------------------------------------------------------------------- -// ARMSemihost_CLOSE - CLOSE A FILE DESCRIPTOR. -//---------------------------------------------------------------------------- -int ARMSemihost_close(int dev_fd) -{ - if (dev_fd <= 2) - return 0; - - struct { - int32_t arg1; - } arg = { - .arg1 = dev_fd - }; - - return ARMSemihost_Call(SYS_CLOSE, (int32_t) &arg); -} - -//---------------------------------------------------------------------------- -// USE_STDIO_FDS - MAKE SURE ALLOCATED FDS FOR STDIO ARE ALWAYS USED. -//---------------------------------------------------------------------------- -int use_stdio_fds(int fd) -{ - switch (fd) { - case 0: return -1; - case 1: return fd_stdout; - case 2: return fd_stderr; - default: return fd; - } -} - -//---------------------------------------------------------------------------- -// ARMSemihost_WRITE - WRITE TO A FILE DESCRIPTOR. -//---------------------------------------------------------------------------- -int ARMSemihost_write(int dev_fd, const char *buf, unsigned count) -{ - struct { - int32_t arg1; - int32_t arg2; - int32_t arg3; - } arg = { - .arg1 = use_stdio_fds(dev_fd), - .arg2 = (int32_t) buf, - .arg3 = (int32_t) count - }; - - int ret = (int)ARMSemihost_Call(SYS_WRITE, (int32_t) &arg); - return (count - (unsigned) ret); -} - -//---------------------------------------------------------------------------- -// ARMSemihost_READ - READ FROM A FILE DESCRIPTOR. -//---------------------------------------------------------------------------- -int ARMSemihost_read(int dev_fd, char *buf, unsigned count) -{ - if (dev_fd == 0) { - int ch = ARMSemihost_Call(SYS_READC, 0); - *(char *) buf = ch; - return 1; - } - - struct { - int32_t arg1; - int32_t arg2; - int32_t arg3; - } arg = { - .arg1 = use_stdio_fds(dev_fd), - .arg2 = (int32_t) buf, - .arg3 = (int32_t) count - }; - - int ret = ARMSemihost_Call(SYS_READ, (int32_t) &arg); - return (count - (unsigned) ret); -} - -//---------------------------------------------------------------------------- -// ARMSemihost_FLEN - GIVEN A FILE DESCRIPTOR, RETURN FILE LENGTH. -//---------------------------------------------------------------------------- -static int ARMSemihost_flen(int dev_fd) -{ - struct { - int32_t arg1; - } arg = { - .arg1 = (int32_t) dev_fd, - }; - - return (int32_t) ARMSemihost_Call(SYS_FLEN, (int32_t) &arg); -} - -//---------------------------------------------------------------------------- -// ARMSemihost_LSEEK - SEEK TO A POSITION IN THE FILE FROM BEGINNING OR END. -//---------------------------------------------------------------------------- -off_t ARMSemihost_lseek(int dev_fd, off_t offset, int origin) -{ - // NOTE: SEEK_CUR with offset == 0 is often used by ftell()/fseek() to get - // the current file position. This isn't supported by FastModel - // semihosting, so just return 0. The current file position of an open - // file must be maintained in software. - if (origin == SEEK_CUR && offset == 0) - return 0; - - if (origin == SEEK_END) { - int flen = ARMSemihost_flen(dev_fd); - if (flen != -1) { - origin = SEEK_SET; - offset += flen; - } - } - - if (origin != SEEK_SET || dev_fd < 0) { - return (off_t) -1; - } - - struct { - int32_t arg1; - int32_t arg2; - } arg = { - .arg1 = dev_fd, - .arg2 = offset - }; - - int32_t ret = ARMSemihost_Call(SYS_SEEK, (int32_t) &arg); - if (ret == 0) - return offset; - return -1; -} - -//---------------------------------------------------------------------------- -// ARMSemihost_UNLINK -//---------------------------------------------------------------------------- -int ARMSemihost_unlink(const char *path) -{ - struct { - int32_t arg1; - int32_t arg2; - } arg = { - .arg1 = (int32_t) path, - .arg2 = strlen(path) - }; - - return (int32_t) ARMSemihost_Call(SYS_REMOVE, (int32_t) &arg); -} - -//---------------------------------------------------------------------------- -// ARMSemihost_RENAME -//---------------------------------------------------------------------------- -int ARMSemihost_rename(const char *old_name, const char *new_name) -{ - struct { - int32_t arg1; - int32_t arg2; - int32_t arg3; - int32_t arg4; - } arg = { - .arg1 = (int32_t) old_name, - .arg2 = strlen(old_name), - .arg3 = (int32_t) new_name, - .arg4 = strlen(new_name) - }; - - return (int) ARMSemihost_Call(SYS_RENAME, (int32_t) &arg); -} - -//---------------------------------------------------------------------------- -// ARMSemihost_EXIT - EXIT FAST MODELS SIMULATION. -//---------------------------------------------------------------------------- -void ARMSemihost_exit() -{ - (void)ARMSemihost_Call(SYS_EXIT, 0); -} - -//---------------------------------------------------------------------------- -// ARMSemihost_TIME - RETURN SYSTEM TIME IN SECONDS FROM JAN 1, 1970. -//---------------------------------------------------------------------------- -long long ARMSemihost_time() -{ - return ARMSemihost_Call(SYS_TIME, 0); -} - -//---------------------------------------------------------------------------- -// ARMSemihost_CLOCK - RETURN ELAPSED CLOCK TICKS FROM START OF EXECUTION. -//---------------------------------------------------------------------------- -unsigned long ARMSemihost_clock() -{ - struct { - unsigned long long arg1; - } arg; - - if (ARMSemihost_Call(SYS_ELAPSED, (int32_t) &arg) == 0) - return (unsigned long) arg.arg1; - - return 0; -} - -//---------------------------------------------------------------------------- -// ARMSemihost_GETENV - GETENV -- RETURN ENVIRONMENT PATH FOR GIVEN VARIABLE -//---------------------------------------------------------------------------- -// Global process environment variables -char semihost_environ[ENV_SIZE]; -int env_len = -1; - -// Helper routine to gather environment variables. -void initialize_sys_environ() -{ - // Gather and open the environment path passed into the simulator - int fd = sys_open(__c_args_env__, SH_OPEN_R); - if (fd == -1) { - ARMSemihost_write(fd_stderr, "Failed to generate semihost environment: unable to open file.\n",63); - ARMSemihost_exit(); - } - - env_len = ARMSemihost_read(fd, semihost_environ, ENV_SIZE); - if (env_len == -1) { - ARMSemihost_write(fd_stderr, "Failed to generate semihost environment: unable to read file.\n",63); - ARMSemihost_exit(); - } - - ARMSemihost_close(fd); -} - -char *ARMSemihost_getenv(const char *_string, char *pout) -{ - if (env_len == -1) - initialize_sys_environ(); - - size_t len = strlen (_string); - for (pout = semihost_environ; pout < semihost_environ + env_len; - pout += strlen(pout) + 1) { - if (_string[0] == pout[0] && strncmp(_string, pout, len) == 0 && - pout[len] == '=') - return pout + len + 1; - } - - return NULL; -} \ No newline at end of file +/*****************************************************************************/ +/* CLANG_TI_SEMIHOST.C - ARM semihosting support for TI Arm Clang compiler */ +/* */ +/* clang_ti_vprintf_semihost: formats output into a local buffer via */ +/* vsnprintf, then writes it to the ARM debug console in a single */ +/* SYS_WRITE0 semihosting trap. No file descriptor management required. */ +/* */ +/* __FM_init (ARMv8-R only): ARMv8-R FastModel starts in HYP mode; this */ +/* naked/retained function switches to SVC mode and redirects execution to */ +/* _c_int00 so that the SVC-based semihosting trap is reachable. */ +/*****************************************************************************/ +#include +#include +#include +#include "clang_ti_semihost.h" + +/*---------------------------------------------------------------------------*/ +/* clang_ti_vprintf_semihost */ +/*---------------------------------------------------------------------------*/ +int clang_ti_vprintf_semihost(const char *_format, va_list _ap) +{ + static char buf[128]; + int n = vsnprintf(buf, sizeof(buf), _format, _ap); + if (n > 0) { + ARMSemihost_Call(SYS_WRITE0, (int32_t)buf); + } + return n; +} + +/*---------------------------------------------------------------------------*/ +/* __FM_init (ARMv8-R only) */ +/*---------------------------------------------------------------------------*/ +#if __ARM_ARCH_8R__ == 1 + +__attribute__((naked, retain)) +void __FM_init(void) +{ + __asm volatile( + "MRS r0, cpsr\n" + "MOV r1, #0x13\n" /* SET SVC MODE */ + "BFI r0, r1, #0, #5\n" + "MSR spsr_cxsf, r0\n" + "LDR r0, =_c_int00\n" /* Force reset vector to _c_int00 */ + "MSR elr_hyp, r0\n" + "DSB\n" + "ISB\n" + "ERET\n" + ); +} + +#endif /* __ARM_ARCH_8R__ == 1 */ diff --git a/CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_semihost.h b/CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_semihost.h index c360f8e0d..d373c924b 100644 --- a/CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_semihost.h +++ b/CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_semihost.h @@ -1,61 +1,87 @@ -/*****************************************************************************/ -/* SEMIHOST.H v##### - Generic C functions for interfacing with simulators */ -/* that support ARM-conformant semihosting */ -/* Copyright (c) 2024@%%%% Texas Instruments Incorporated */ -/*****************************************************************************/ -/*****************************************************************************/ -/* CLANG_TI_SEMIHOST.H - Generic C functions for interfacing with */ -/* simulators that support ARM-conformant semihosting */ -/*****************************************************************************/ -#ifndef _CLANG_TI_SEMIHOST_H_ -#define _CLANG_TI_SEMIHOST_H_ - -#include - -// Device I/O routines. -int ARMSemihost_open(const char *path, unsigned flags, int llv_fd); -int ARMSemihost_close(int dev_fd); -int ARMSemihost_write(int dev_fd, const char *buf, unsigned count); -int ARMSemihost_read(int dev_fd, char *buf, unsigned count); -off_t ARMSemihost_lseek(int dev_fd, off_t offset, int origin); -int ARMSemihost_unlink(const char *path); -int ARMSemihost_rename(const char *old_name, const char *new_name); - -// Auxiliary device routines. -void ARMSemihost_exit(); -long long ARMSemihost_time(); -unsigned long ARMSemihost_clock(); -char* ARMSemihost_getenv(const char*, char*); - -#define SYS_CLOCK (0x10) -#define SYS_CLOSE (0x02) -#define SYS_ELAPSED (0x30) -#define SYS_ERRNO (0x13) -#define SYS_EXIT (0x18) -#define SYS_EXIT_EXTENDED (0x20) -#define SYS_FLEN (0x0C) -#define SYS_GET_CMDLINE (0x15) -#define SYS_HEAPINFO (0x16) -#define SYS_ISERROR (0x08) -#define SYS_ISTTY (0x09) -#define SYS_OPEN (0x01) -#define SYS_READ (0x06) -#define SYS_READC (0x07) -#define SYS_REMOVE (0x0E) -#define SYS_RENAME (0x0F) -#define SYS_SEEK (0x0A) -#define SYS_SYSTEM (0x12) -#define SYS_TICKFREQ (0x31) -#define SYS_TIME (0x11) -#define SYS_TMPNAM (0x0D) -#define SYS_WRITE (0x05) -#define SYS_WRITEC (0x03) -#define SYS_WRITE0 (0x04) - -//---------------------------------------------------------------------------- -// PARSE_CMDLINE - PARSE THE FASTMODELS SIMULATOR COMMAND LINE FOR ARGUMENTS. -typedef struct { int argc; char *argv[1]; } ARGS; - -void parse_cmdline(ARGS *pargs, char* buf, char* env); - -#endif /* _CLANG_TI_SEMIHOST_H_ */ \ No newline at end of file +/*****************************************************************************/ +/* CLANG_TI_SEMIHOST.H - ARM semihosting support for TI Arm Clang compiler */ +/* */ +/* Provides: */ +/* - ARM semihosting operation codes */ +/* - ARMSemihost_Call(): architecture-correct semihosting trap */ +/* - clang_ti_vprintf_semihost(): vprintf routed to the debug console */ +/*****************************************************************************/ +#ifndef _CLANG_TI_SEMIHOST_H_ +#define _CLANG_TI_SEMIHOST_H_ + +#include +#include + +/*---------------------------------------------------------------------------*/ +/* ARM semihosting operation codes */ +/*---------------------------------------------------------------------------*/ +#define SYS_CLOCK (0x10) +#define SYS_CLOSE (0x02) +#define SYS_ELAPSED (0x30) +#define SYS_ERRNO (0x13) +#define SYS_EXIT (0x18) +#define SYS_EXIT_EXTENDED (0x20) +#define SYS_FLEN (0x0C) +#define SYS_GET_CMDLINE (0x15) +#define SYS_HEAPINFO (0x16) +#define SYS_ISERROR (0x08) +#define SYS_ISTTY (0x09) +#define SYS_OPEN (0x01) +#define SYS_READ (0x06) +#define SYS_READC (0x07) +#define SYS_REMOVE (0x0E) +#define SYS_RENAME (0x0F) +#define SYS_SEEK (0x0A) +#define SYS_SYSTEM (0x12) +#define SYS_TICKFREQ (0x31) +#define SYS_TIME (0x11) +#define SYS_TMPNAM (0x0D) +#define SYS_WRITE (0x05) +#define SYS_WRITEC (0x03) +#define SYS_WRITE0 (0x04) + +/*---------------------------------------------------------------------------*/ +/* ARMSemihost_Call - Issue the architecture-correct semihosting trap. */ +/* */ +/* M-profile: BKPT #0xAB */ +/* T32 (A/R): SVC #0xAB */ +/* A32 (A/R): SVC #0x123456 */ +/*---------------------------------------------------------------------------*/ +__attribute__((noinline, optnone)) +static inline int ARMSemihost_Call(int command, int32_t arg) +{ + int ret; + __asm volatile ( + "mov r0, %[rsn] \n" + "mov r1, %[arg] \n" +#if __ARM_ARCH_PROFILE == 'M' + "bkpt #0xab \n" +#else +#ifdef __thumb__ + "svc #0xab \n" +#else + "svc #0x123456 \n" +#endif +#endif + "mov %[val], r0 \n" + : [val] "=r" (ret) + : [rsn] "r" (command), [arg] "r" (arg) + : "r0", "r1", "r2", "r3", "ip", "lr", "memory", "cc" + ); + return ret; +} + +/*---------------------------------------------------------------------------*/ +/* clang_ti_vprintf_semihost - vprintf routed to the ARM debug console. */ +/*---------------------------------------------------------------------------*/ +#ifdef __cplusplus +extern "C" { +#endif + +int clang_ti_vprintf_semihost(const char *_format, va_list _ap); + +#ifdef __cplusplus +} +#endif + +#endif /* _CLANG_TI_SEMIHOST_H_ */ diff --git a/CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_semihost_call.h b/CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_semihost_call.h deleted file mode 100644 index 726d807a5..000000000 --- a/CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_semihost_call.h +++ /dev/null @@ -1,43 +0,0 @@ -/*****************************************************************************/ -/* SEMIHOST_CALL.C v##### - Target-specific instruction sequence for */ -/* triggering ARM-conformant semihosting */ -/* Copyright (c) 2024@%%%% Texas Instruments Incorporated */ -/*****************************************************************************/ -/*****************************************************************************/ -/* CLANG_TI_SEMIHOST_CALL.H - Target-specific instruction sequence for */ -/* triggering ARM-conformant semihosting */ -/*****************************************************************************/ -#ifndef _CLANG_TI_SEMIHOST_CALL_H_ -#define _CLANG_TI_SEMIHOST_CALL_H_ - -#include - -//---------------------------------------------------------------------------- -// ARMSemihost_Call - Issue instruction sequence to the simulator with -// arguments. -//---------------------------------------------------------------------------- -__attribute__((noinline,optnone)) -static inline int ARMSemihost_Call(int command, int32_t arg) { - int ret; - __asm volatile ( - "mov r0, %[rsn] \n" - "mov r1, %[arg] \n" -#if __ARM_ARCH_PROFILE == 'M' - "bkpt #0xab \n" -#else -#ifdef __thumb__ - "svc #0xab \n" -#else - "svc #0x123456 \n" -#endif -#endif - "mov %[val], r0 \n" - - : [val] "=r" (ret) /* outputs */ - : [rsn] "r" (command), [arg] "r" (arg) /* inputs */ - : "r0", "r1", "r2", "r3", "ip", "lr", "memory", "cc" /* clobber */ - ); - return ret; -} - -#endif /* _CLANG_TI_SEMIHOST_CALL_H_ */ \ No newline at end of file diff --git a/CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_vprintf_semihost.c b/CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_vprintf_semihost.c deleted file mode 100644 index 931228a40..000000000 --- a/CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_vprintf_semihost.c +++ /dev/null @@ -1,96 +0,0 @@ -/*****************************************************************************/ -/* CLANG_TI_VPRINTF_SEMIHOST.C */ -/* */ -/* Specialized version of vprintf that directs output to an ARM debugger */ -/* using semihosting calls via ARMSemihost_write. */ -/*****************************************************************************/ -/*****************************************************************************/ -/* VPRINTF.C */ -/* */ -/* Copyright (c) 1995 Texas Instruments Incorporated */ -/* http://www.ti.com/ */ -/* */ -/* Redistribution and use in source and binary forms, with or without */ -/* modification, are permitted provided that the following conditions */ -/* are met: */ -/* */ -/* Redistributions of source code must retain the above copyright */ -/* notice, this list of conditions and the following disclaimer. */ -/* */ -/* Redistributions in binary form must reproduce the above copyright */ -/* notice, this list of conditions and the following disclaimer in */ -/* the documentation and/or other materials provided with the */ -/* distribution. */ -/* */ -/* Neither the name of Texas Instruments Incorporated nor the names */ -/* of its contributors may be used to endorse or promote products */ -/* derived from this software without specific prior written */ -/* permission. */ -/* */ -/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ -/* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ -/* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ -/* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ -/* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ -/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ -/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ -/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ -/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ -/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ -/* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* */ -/*****************************************************************************/ - -/*****************************************************************************/ -/* Functions: */ -/* VPRINTF - Print formatted output to stdio */ -/* _OUTC - Put a character in a stream */ -/* _OUTS - Put a string in a stream */ -/*****************************************************************************/ -#include -#include "clang_ti_format_semihost.h" -#include -#include -#include "clang_ti_semihost.h" -#include "clang_ti_vprintf_semihost.h" - -extern _CODE_ACCESS int __TI_printfi(char ** __restrict _format, - va_list _ap, void * __restrict _op, - int (*_outc)(char, void *), - int (*_outs)(char *, void *, int)); - -static int _outc_sh(char c, void *_op); -static int _outs_sh(char *s, void *_op, int len); - -/*****************************************************************************/ -/* CLANG_TI_VPRINTF_SEMIHOST */ -/*****************************************************************************/ -_CODE_ACCESS int clang_ti_vprintf_semihost(const char *_format, va_list _ap) -{ - char *fptr = (char *)_format; - - /* Route formatting engine to semihosting callbacks */ - return (__TI_printfi(&fptr, _ap, NULL, _outc_sh, _outs_sh)); -} - -static int _outc_sh(char c, void *_op) -{ - /* Use FD 1 (stdout) which maps to the debugger console in semihost.c */ - if (ARMSemihost_write(1, &c, 1) == 1) - { - return (int)(unsigned char)c; - } - - return EOF; -} - -static int _outs_sh(char *s, void *_op, int len) -{ - int result = ARMSemihost_write(1, s, len); - if (result < 0) - { - return EOF; - } - - return result; -} \ No newline at end of file diff --git a/CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_vprintf_semihost.h b/CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_vprintf_semihost.h deleted file mode 100644 index c34ddcb93..000000000 --- a/CMSIS/CoreValidation/Source/Clang_TI_Semihost/clang_ti_vprintf_semihost.h +++ /dev/null @@ -1,20 +0,0 @@ -/*****************************************************************************/ -/* CLANG_TI_VPRINTF_SEMIHOST.H */ -/*****************************************************************************/ -#ifndef _CLANG_TI_VPRINTF_SEMIHOST_H_ -#define _CLANG_TI_VPRINTF_SEMIHOST_H_ - -#include -#include <_ti_config.h> - -#ifdef __cplusplus -extern "C" { -#endif - -_CODE_ACCESS int clang_ti_vprintf_semihost(const char *_format, va_list _ap); - -#ifdef __cplusplus -} -#endif - -#endif /* _CLANG_TI_VPRINTF_SEMIHOST_H_ */ \ No newline at end of file From d591a9c7f189ba4bd635e5c82b6384a656359515 Mon Sep 17 00:00:00 2001 From: Shawn Mason <255018043+smmasongt@users.noreply.github.com> Date: Sun, 12 Apr 2026 20:35:31 -0400 Subject: [PATCH 13/17] Reverts all changes to Bootloader CMSIS Toolbox files --- .../CoreValidation/Layer/App/Bootloader_Cortex-M/App.clayer.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CMSIS/CoreValidation/Layer/App/Bootloader_Cortex-M/App.clayer.yml b/CMSIS/CoreValidation/Layer/App/Bootloader_Cortex-M/App.clayer.yml index 2b5088c29..8e154b9eb 100644 --- a/CMSIS/CoreValidation/Layer/App/Bootloader_Cortex-M/App.clayer.yml +++ b/CMSIS/CoreValidation/Layer/App/Bootloader_Cortex-M/App.clayer.yml @@ -8,4 +8,4 @@ layer: groups: - group: Source Files files: - - file: ./bootloader.c \ No newline at end of file + - file: ./bootloader.c From 775b910ddfea758f55fc7024ec6ca07a556d7cb9 Mon Sep 17 00:00:00 2001 From: Shawn Mason <255018043+smmasongt@users.noreply.github.com> Date: Sun, 12 Apr 2026 20:46:31 -0400 Subject: [PATCH 14/17] Adds Clang_TI to gcc-problem-matcher action --- .github/workflows/corevalidation.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/corevalidation.yml b/.github/workflows/corevalidation.yml index 3e73f53b7..a9f8fdbb9 100644 --- a/.github/workflows/corevalidation.yml +++ b/.github/workflows/corevalidation.yml @@ -85,7 +85,7 @@ jobs: queries: security-and-quality - uses: ammaraskar/gcc-problem-matcher@master - if: matrix.compiler == 'Clang' || matrix.compiler == 'GCC' + if: matrix.compiler == 'Clang' || matrix.compiler == 'Clang_TI' || matrix.compiler == 'GCC' - name: Set TI ARM CLANG Environment Variables and Path run: | From f7a4d3572275eb6a414527a12b36f11bd5926b04 Mon Sep 17 00:00:00 2001 From: Shawn Mason <255018043+smmasongt@users.noreply.github.com> Date: Mon, 13 Apr 2026 19:54:42 -0400 Subject: [PATCH 15/17] Copilot Review - Cortex-A9 Neon Fast Model Error Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com> --- CMSIS/CoreValidation/Project/build.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CMSIS/CoreValidation/Project/build.py b/CMSIS/CoreValidation/Project/build.py index 1dde2ef68..3ed71e8a7 100755 --- a/CMSIS/CoreValidation/Project/build.py +++ b/CMSIS/CoreValidation/Project/build.py @@ -152,7 +152,7 @@ class OptimizationAxis(Enum): DeviceAxis.CA7: ("FVP_VE_Cortex-A7x1", []), DeviceAxis.CA7NEON: ("FVP_VE_Cortex-A7x1", []), DeviceAxis.CA9: ("FVP_VE_Cortex-A9x1", []), - DeviceAxis.CA9NEON: ("_VE_Cortex-A9x1", []), + DeviceAxis.CA9NEON: ("FVP_VE_Cortex-A9x1", []), DeviceAxis.CA35: ("FVP_Base_Cortex-A35", []), DeviceAxis.CA35NEON: ("FVP_Base_Cortex-A35", []), DeviceAxis.CA53: ("FVP_Base_Cortex-A53", []), From b78be9880f7634cd6289caa1412009159c11f130 Mon Sep 17 00:00:00 2001 From: Shawn Mason <255018043+smmasongt@users.noreply.github.com> Date: Mon, 13 Apr 2026 21:17:23 -0400 Subject: [PATCH 16/17] Copilot Review - README Inconsistencies Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com> --- CMSIS/CoreValidation/README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CMSIS/CoreValidation/README.md b/CMSIS/CoreValidation/README.md index 554a50aab..24d6c1d1c 100644 --- a/CMSIS/CoreValidation/README.md +++ b/CMSIS/CoreValidation/README.md @@ -105,7 +105,7 @@ For example, build and run the tests using GCC for Cortex-M3 with low optimizati [GCC][Cortex-M3][none](build:csolution) csolution succeeded with exit code 0 [GCC][Cortex-M3][none](build:cbuild) cbuild Validation.GCC_low+CM3/Validation.GCC_low+CM3.cprj [GCC][Cortex-M3][none](build:cbuild) cbuild succeeded with exit code 0 -[GCC][Cortex-M3][none](run:model_exec) FVP_MPS2_Cortex-M3 -q --simlimit 100 -f ../Layer/Target/CM3/model_config.txt -a Validation.GCC_low+CM3/Validation.GCC_low+CM3_outdir/Validation.GCC_low+CM3.elf +[GCC][Cortex-M3][none](run:model_exec) FVP_MPS2_Cortex-M3 -q --simlimit 5 -f ../Layer/Target/CM3/model_config.txt -a Validation.GCC_low+CM3/Validation.GCC_low+CM3_outdir/Validation.GCC_low+CM3.elf [GCC][Cortex-M3][none](run:model_exec) FVP_MPS2_Cortex-M3 succeeded with exit code 0 Matrix Summary From 64c2c8a9f495c577ca198bb3f639643f836c3514 Mon Sep 17 00:00:00 2001 From: Shawn Mason <255018043+smmasongt@users.noreply.github.com> Date: Mon, 13 Apr 2026 21:34:05 -0400 Subject: [PATCH 17/17] Copilot Review - Gate Github Workflow actions for Clang TI and Update README --- .github/workflows/corevalidation.yml | 10 ++++++---- CMSIS/CoreValidation/README.md | 2 +- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/.github/workflows/corevalidation.yml b/.github/workflows/corevalidation.yml index f47716605..ebfddd13a 100644 --- a/.github/workflows/corevalidation.yml +++ b/.github/workflows/corevalidation.yml @@ -87,21 +87,23 @@ jobs: - uses: ammaraskar/gcc-problem-matcher@master if: matrix.compiler == 'Clang' || matrix.compiler == 'Clang_TI' || matrix.compiler == 'GCC' - - name: Set TI ARM CLANG Environment Variables and Path + - name: Set TI Arm Clang Environment Variables and Path + if: matrix.compiler == 'Clang_TI' run: | echo "CLANG_TI_PATH=${{ env.CLANG_TI_INSTALL_PATH }}ti-cgt-armllvm_${{ env.CLANG_TI_VERSION }}" >> $GITHUB_ENV echo "CLANG_TI_TOOLCHAIN_${{ env.CLANG_TI_TC_SUFFIX }}=${{ env.CLANG_TI_INSTALL_PATH }}ti-cgt-armllvm_${{ env.CLANG_TI_VERSION }}/bin" >> $GITHUB_ENV - - name: Cache TI ARM CLANG + - name: Cache TI Arm Clang + if: matrix.compiler == 'Clang_TI' id: cache-ti-arm-clang uses: actions/cache@v5 with: path: ${{ env.CLANG_TI_PATH }} key: ${{ runner.os }}-ti-arm-clang-${{ env.CLANG_TI_VERSION }} - - name: Download and Verify TI ARM CLANG Installer + - name: Download and Verify TI Arm Clang Installer + if: matrix.compiler == 'Clang_TI' && steps.cache-ti-arm-clang.outputs.cache-hit != 'true' working-directory: /home/runner - if: steps.cache-ti-arm-clang.outputs.cache-hit != 'true' run: | FILE="ti_cgt_armllvm_${{ env.CLANG_TI_VERSION }}_linux-x64_installer.bin" URL="https://dr-download.ti.com/software-development/ide-configuration-compiler-or-debugger/MD-ayxs93eZNN/${{ env.CLANG_TI_VERSION }}/${FILE}" diff --git a/CMSIS/CoreValidation/README.md b/CMSIS/CoreValidation/README.md index 24d6c1d1c..0fe2fc54c 100644 --- a/CMSIS/CoreValidation/README.md +++ b/CMSIS/CoreValidation/README.md @@ -69,7 +69,7 @@ The following tools are required to build and run the CoreValidation tests: - [Arm Compiler 6.20](https://artifacts.keil.arm.com/arm-compiler/6.20/21/)* - [GCC Compiler 13.2.1](https://artifacts.keil.arm.com/arm-none-eabi-gcc/13.2.1/)* - [Clang Compiler 17.0.1](https://github.com/ARM-software/LLVM-embedded-toolchain-for-Arm/releases/tag/release-17.0.1)* -- [TI Arm Clang Compiler 5.1.0](https://www.ti.com/tool/download/ARM-CGT-CLANG) +- [TI Arm Clang Compiler 5.1.0 LTS](https://www.ti.com/tool/download/ARM-CGT-CLANG) - [Arm Virtual Hardware for Cortex-M based on FastModels 11.22.39](https://artifacts.keil.arm.com/avh/11.22.39/)* - [Python 3.9](https://www.python.org/downloads/)