From b1b2bb5b4527bfd5fe42f02aa34b1eef86ef0dc9 Mon Sep 17 00:00:00 2001 From: Jacob Abrams Date: Thu, 16 Apr 2026 12:44:36 -0700 Subject: [PATCH] Short-circuit dcache disable Do not attempt to clean and invalidate the DCache if SCB_DisableDCache is invoked when it was not enabled in the first place. This prevents landing junk into RAM after a POR. --- CMSIS/Core/Include/core_starmc1.h | 5 +++++ CMSIS/Core/Include/m-profile/armv7m_cachel1.h | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/CMSIS/Core/Include/core_starmc1.h b/CMSIS/Core/Include/core_starmc1.h index a9fc7206..bd621661 100644 --- a/CMSIS/Core/Include/core_starmc1.h +++ b/CMSIS/Core/Include/core_starmc1.h @@ -3326,6 +3326,11 @@ __STATIC_FORCEINLINE void SCB_DisableDCache (void) uint32_t sets; uint32_t ways; + /* Return if D-cache is not enabled (prevent flushing junk after POR) */ + if ((SCB->CCR & SCB_CCR_DC_Msk) == 0U) { + return; + } + SCB->CSSELR = 0U; /* select Level 1 data cache */ __DSB(); diff --git a/CMSIS/Core/Include/m-profile/armv7m_cachel1.h b/CMSIS/Core/Include/m-profile/armv7m_cachel1.h index 78ab56aa..eea30254 100644 --- a/CMSIS/Core/Include/m-profile/armv7m_cachel1.h +++ b/CMSIS/Core/Include/m-profile/armv7m_cachel1.h @@ -189,6 +189,11 @@ __STATIC_FORCEINLINE void SCB_DisableDCache (void) #endif ; + /* Return if D-cache is not enabled (prevent flushing junk after POR) */ + if ((SCB->CCR & SCB_CCR_DC_Msk) == 0U) { + return; + } + SCB->CSSELR = 0U; /* select Level 1 data cache */ __DSB();