diff --git a/docs/sbsa/arm_sbsa_testcase_checklist.md b/docs/sbsa/arm_sbsa_testcase_checklist.md
index 56a22327..d502f9ce 100644
--- a/docs/sbsa/arm_sbsa_testcase_checklist.md
+++ b/docs/sbsa/arm_sbsa_testcase_checklist.md
@@ -451,14 +451,23 @@ The checklist provides information about:
|
- | L5 |
- S_L5SM_04 |
- S_L5SM_04 |
- Not Covered |
- |
- |
- |
+ L5 |
+ S_L5SM_04 |
+ B_SMMU_09 |
+ 310 |
+ Check S-EL2 & SMMU Stage1 support |
+ Yes |
+ Yes |
+ No |
|
+
+
+ | B_SMMU_20 |
+ 311 |
+ Check S-EL2 & SMMU Stage2 Support |
+ Yes |
+ Yes |
+ No |
|
@@ -589,11 +598,11 @@ The checklist provides information about:
| L6 |
S_L6PE_08 |
S_L6PE_08 |
- Not covered |
- |
- |
- |
- |
+ 37 |
+ Check SPE if implemented |
+ Yes |
+ Yes |
+ No |
|
@@ -608,14 +617,59 @@ The checklist provides information about:
|
- | L6 |
- S_L6SM_04 |
- S_L6SM_04 |
- Not covered |
+ L6 |
+ S_L6SM_04 |
+ B_SMMU_03 |
+ 316 |
+ Check SMMU Large VA Support |
+ Yes |
+ Yes |
+ No |
|
+
+
+ B_SMMU_04 |
+ 317 |
+ Check TLB Range Invalidation |
+ Yes |
+ Yes |
+ No |
|
+
+
+ | B_SMMU_05 |
+ 330 |
+ Check DVM capabilities |
+ Yes |
+ Yes |
+ No |
+ |
+
+
+ | B_SMMU_13 |
+ 318 |
+ Check SMMU 16 Bit ASID Support |
+ Yes |
+ Yes |
+ No |
|
+
+
+ | B_SMMU_14 |
+ 319 |
+ Check SMMU Endianess Support |
+ Yes |
+ Yes |
+ No |
|
+
+
+ | B_SMMU_23 |
+ 315 |
+ Check SMMU 16 Bit VMID Support |
+ Yes |
+ Yes |
+ No |
|
@@ -3621,6 +3675,9 @@ The checklist provides information about:
## Latest Checklist Changes
+- Updated S_L5SM_04, S_L6PE_08, S_L6SM_04
+
+### v26.03_SBSA_8.0.1
- **FR Added:** LVQBC, KBRZG
- **RI_ Added:** RI_PWR_1
- B_PCIe_10 and B_PCIe_11 mapped to S_PCIe_10
diff --git a/val/src/rule_metadata.c b/val/src/rule_metadata.c
index 4471199a..6de48e97 100644
--- a/val/src/rule_metadata.c
+++ b/val/src/rule_metadata.c
@@ -465,6 +465,14 @@ rule_test_map_t rule_test_map[RULE_ID_SENTINEL] = {
.flag = BASE_RULE,
.test_num = ACS_PE_TEST_NUM_BASE + 48,
},
+ [S_L6PE_08] = {
+ .test_entry_id = PE037_ENTRY,
+ .module_id = PE,
+ .rule_desc = "Check SPE if implemented",
+ .platform_bitmask = PLATFORM_BAREMETAL | PLATFORM_UEFI,
+ .flag = BASE_RULE,
+ .test_num = ACS_PE_TEST_NUM_BASE + 37,
+ },
[S_L7PE_02] = {
.test_entry_id = PE049_ENTRY,
.module_id = PE,
@@ -1317,6 +1325,13 @@ rule_test_map_t rule_test_map[RULE_ID_SENTINEL] = {
.flag = BASE_RULE,
.test_num = ACS_SMMU_TEST_NUM_BASE + 12,
},
+ [S_L5SM_04] = {
+ .test_entry_id = NULL_ENTRY,
+ .module_id = SMMU,
+ .rule_desc = "S-EL2 & SMMU Stage1 and Stage2 support",
+ .platform_bitmask = PLATFORM_BAREMETAL | PLATFORM_UEFI,
+ .flag = ALIAS_RULE,
+ },
[S_L6SM_02] = {
.test_entry_id = I013_ENTRY,
.module_id = SMMU,
@@ -1333,6 +1348,13 @@ rule_test_map_t rule_test_map[RULE_ID_SENTINEL] = {
.flag = BASE_RULE,
.test_num = ACS_SMMU_TEST_NUM_BASE + 14,
},
+ [S_L6SM_04] = {
+ .test_entry_id = NULL_ENTRY,
+ .module_id = SMMU,
+ .rule_desc = "Check SMMU large VA/TLB/DVM ASID VMID",
+ .platform_bitmask = PLATFORM_BAREMETAL | PLATFORM_UEFI,
+ .flag = ALIAS_RULE,
+ },
[S_L7SM_01] = {
.test_entry_id = I022_ENTRY,
.module_id = SMMU,
@@ -3007,9 +3029,6 @@ rule_test_map_t rule_test_map[RULE_ID_SENTINEL] = {
[S_L6PE_07] = {
.module_id = PE,
},
- [S_L6PE_08] = {
- .module_id = PE,
- },
[S_L8PE_08] = {
.module_id = PE,
},
@@ -3109,12 +3128,6 @@ rule_test_map_t rule_test_map[RULE_ID_SENTINEL] = {
[S_L3SM_01] = {
.module_id = SMMU,
},
- [S_L5SM_04] = {
- .module_id = SMMU,
- },
- [S_L6SM_04] = {
- .module_id = SMMU,
- },
[P_L1SM_01] = {
.module_id = SMMU,
},
@@ -4845,6 +4858,13 @@ RULE_ID_e s_l8cxl_rule_list[] = {
RULE_ID_SENTINEL
};
+/* S_L5SM_04 */
+RULE_ID_e s_l5sm_04_rule_list[] = {B_SMMU_09, B_SMMU_20, RULE_ID_SENTINEL};
+
+/* S_L6SM_04 */
+RULE_ID_e s_l6sm_04_rule_list[] = {B_SMMU_03, B_SMMU_04, B_SMMU_05, B_SMMU_13,
+ B_SMMU_14, B_SMMU_23, RULE_ID_SENTINEL};
+
/* PCBSA alias lists */
/* P_L2WD_01 */
RULE_ID_e p_l2wd_01_rule_list[] = {B_WD_01, B_WD_02, B_WD_03, B_WD_04, B_WD_05,
@@ -4939,6 +4959,8 @@ const alias_rule_map_t alias_rule_map[] = {
{LVQBC, lvqbc_rule_list},
{S_L8CXL_1, s_l8cxl_rule_list},
{XDGKZ, xdgkz_rule_list},
+ {S_L5SM_04, s_l5sm_04_rule_list},
+ {S_L6SM_04, s_l6sm_04_rule_list},
/* PCBSA alias rules */
{P_L1_01, bsa_l1_rule_list},