Hello,
I am currently using Timeloop for latency and energy modeling and am looking into Accelforge as a more modern alternative. I have a few questions about the tool.
- To learn about the accelerator modeling, I am trying to implement a Gemmini architecture, but I am unsure about a few details here. For reference, here is the architecture I currently have: https://gist.github.com/patschmidt2/38a66e9be50578d2dd4f2daa9c3d9e4e
Gemmini uses a scratchpad to store inputs and weights and an accumulator to store psums. In Timeloop, every column of the systolic array was modeled separately, resulting in the accumulator being split into multiple SRAMs, each of which has a width of one word. I tried to replicate this, but I am unsure if I understand the documentation correctly. I think so far I only have a 1x16 array, but I don't know how to model the full array properly.
Additionally, I'd like to understand if this column-wise model is still necessary or if I can somehow model the array and memory as they appear in the RTL. As far as I know, this Timeloop model is the way it is due to limitations of Timeloop. Ideally, I'd like to have a 16x16 array and one scratchpad and one accumulator.
-
Is it possible to get the latency in clock cycles? Additionally, how is the latency calculated? My model does not provide a clock frequency.
-
The features section mentions “heterogeneous architectures”. Am I understanding this correctly to mean an architecture composed of, for example, an Eyeriss and a Simba device? If so, is there an example available?
Thanks in advance for your help!
Hello,
I am currently using Timeloop for latency and energy modeling and am looking into Accelforge as a more modern alternative. I have a few questions about the tool.
Gemmini uses a scratchpad to store inputs and weights and an accumulator to store psums. In Timeloop, every column of the systolic array was modeled separately, resulting in the accumulator being split into multiple SRAMs, each of which has a width of one word. I tried to replicate this, but I am unsure if I understand the documentation correctly. I think so far I only have a 1x16 array, but I don't know how to model the full array properly.
Additionally, I'd like to understand if this column-wise model is still necessary or if I can somehow model the array and memory as they appear in the RTL. As far as I know, this Timeloop model is the way it is due to limitations of Timeloop. Ideally, I'd like to have a 16x16 array and one scratchpad and one accumulator.
Is it possible to get the latency in clock cycles? Additionally, how is the latency calculated? My model does not provide a clock frequency.
The features section mentions “heterogeneous architectures”. Am I understanding this correctly to mean an architecture composed of, for example, an Eyeriss and a Simba device? If so, is there an example available?
Thanks in advance for your help!