diff --git a/SW2.cache/ip/2025.1/1/4/14830d1ba75c4316/14830d1ba75c4316.xci b/SW2.cache/ip/2025.1/1/4/14830d1ba75c4316/14830d1ba75c4316.xci deleted file mode 100644 index 07bf940..0000000 --- a/SW2.cache/ip/2025.1/1/4/14830d1ba75c4316/14830d1ba75c4316.xci +++ /dev/null @@ -1,37 +0,0 @@ - - - xilinx.com - ipcache - 14830d1ba75c4316 - 0 - - - design_1_RotaryEnc_0_0 - - - design_1_RotaryEnc_0_0 - zynquplus - realdigital.org:aup-zu3-8gb:part0:1.0 - xczu3eg - sfvc784 - VERILOG - - -2 - - E - 14830d1ba75c4316 - $Change: 6131539 $ - 5635e54d - 50 - IP_Unknown - 2 - TRUE - . - - . - 2025.1 - GLOBAL - - - - diff --git a/SW2.cache/ip/2025.1/1/4/14830d1ba75c4316/design_1_RotaryEnc_0_0.dcp b/SW2.cache/ip/2025.1/1/4/14830d1ba75c4316/design_1_RotaryEnc_0_0.dcp deleted file mode 100644 index a7fcbd0..0000000 Binary files a/SW2.cache/ip/2025.1/1/4/14830d1ba75c4316/design_1_RotaryEnc_0_0.dcp and /dev/null differ diff --git a/SW2.cache/ip/2025.1/1/4/14830d1ba75c4316/design_1_RotaryEnc_0_0_sim_netlist.v b/SW2.cache/ip/2025.1/1/4/14830d1ba75c4316/design_1_RotaryEnc_0_0_sim_netlist.v deleted file mode 100644 index 92f81f0..0000000 --- a/SW2.cache/ip/2025.1/1/4/14830d1ba75c4316/design_1_RotaryEnc_0_0_sim_netlist.v +++ /dev/null @@ -1,252 +0,0 @@ -// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2025.1 (win64) Build 6140274 Thu May 22 00:12:29 MDT 2025 -// Date : Tue Apr 28 15:54:33 2026 -// Host : Lab016-05 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_RotaryEnc_0_0_sim_netlist.v -// Design : design_1_RotaryEnc_0_0 -// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified -// or synthesized. This netlist cannot be used for SDF annotated simulation. -// Device : xczu3eg-sfvc784-2-e -// -------------------------------------------------------------------------------- -`timescale 1 ps / 1 ps - -module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_RotaryEnc - (Clk, - ROT_A, - ROT_B, - RotL, - RotR); - input Clk; - input ROT_A; - input ROT_B; - output RotL; - output RotR; - - wire Clk; - wire FF; - wire FF_i_1_n_0; - wire ROT_A; - wire ROT_B; - wire RotL; - wire RotL0; - wire RotR; - wire RotR0; - wire ffA; - wire ffB; - wire prevA; - - LUT3 #( - .INIT(8'hE8)) - FF_i_1 - (.I0(FF), - .I1(ffA), - .I2(ffB), - .O(FF_i_1_n_0)); - FDRE #( - .INIT(1'b1)) - FF_reg - (.C(Clk), - .CE(1'b1), - .D(FF_i_1_n_0), - .Q(FF), - .R(1'b0)); - (* SOFT_HLUTNM = "soft_lutpair0" *) - LUT4 #( - .INIT(16'h0040)) - RotL_i_1 - (.I0(FF), - .I1(ffB), - .I2(ffA), - .I3(prevA), - .O(RotL0)); - FDRE #( - .INIT(1'b0)) - RotL_reg - (.C(Clk), - .CE(1'b1), - .D(RotL0), - .Q(RotL), - .R(1'b0)); - (* SOFT_HLUTNM = "soft_lutpair0" *) - LUT4 #( - .INIT(16'h2000)) - RotR_i_1 - (.I0(prevA), - .I1(FF), - .I2(ffB), - .I3(ffA), - .O(RotR0)); - FDRE #( - .INIT(1'b0)) - RotR_reg - (.C(Clk), - .CE(1'b1), - .D(RotR0), - .Q(RotR), - .R(1'b0)); - FDRE #( - .INIT(1'b1)) - ffA_reg - (.C(Clk), - .CE(1'b1), - .D(ROT_A), - .Q(ffA), - .R(1'b0)); - FDRE #( - .INIT(1'b1)) - ffB_reg - (.C(Clk), - .CE(1'b1), - .D(ROT_B), - .Q(ffB), - .R(1'b0)); - FDRE #( - .INIT(1'b1)) - prevA_reg - (.C(Clk), - .CE(1'b1), - .D(ffA), - .Q(prevA), - .R(1'b0)); -endmodule - -module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_RotaryEnc_wrap - (RotL, - RotR, - ROT_A, - ROT_B, - Clk); - output RotL; - output RotR; - input ROT_A; - input ROT_B; - input Clk; - - wire Clk; - wire ROT_A; - wire ROT_B; - wire RotL; - wire RotR; - - decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_RotaryEnc i_wrap - (.Clk(Clk), - .ROT_A(ROT_A), - .ROT_B(ROT_B), - .RotL(RotL), - .RotR(RotR)); -endmodule - -(* CHECK_LICENSE_TYPE = "design_1_RotaryEnc_0_0,RotaryEnc_wrap,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) -(* x_core_info = "RotaryEnc_wrap,Vivado 2025.1" *) -(* NotValidForBitStream *) -module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix - (ROT_A, - ROT_B, - Clk, - RotL, - RotR); - input ROT_A; - input ROT_B; - input Clk; - output RotL; - output RotR; - - wire Clk; - wire ROT_A; - wire ROT_B; - wire RotL; - wire RotR; - - decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_RotaryEnc_wrap U0 - (.Clk(Clk), - .ROT_A(ROT_A), - .ROT_B(ROT_B), - .RotL(RotL), - .RotR(RotR)); -endmodule -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - parameter GRES_WIDTH = 10000; - parameter GRES_START = 10000; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - wire GRESTORE; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - reg GRESTORE_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - assign (strong1, weak0) GRESTORE = GRESTORE_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - - initial begin - GRESTORE_int = 1'b0; - #(GRES_START); - GRESTORE_int = 1'b1; - #(GRES_WIDTH); - GRESTORE_int = 1'b0; - end - -endmodule -`endif diff --git a/SW2.cache/ip/2025.1/1/4/14830d1ba75c4316/design_1_RotaryEnc_0_0_sim_netlist.vhdl b/SW2.cache/ip/2025.1/1/4/14830d1ba75c4316/design_1_RotaryEnc_0_0_sim_netlist.vhdl deleted file mode 100644 index f74e853..0000000 --- a/SW2.cache/ip/2025.1/1/4/14830d1ba75c4316/design_1_RotaryEnc_0_0_sim_netlist.vhdl +++ /dev/null @@ -1,198 +0,0 @@ --- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. --- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2025.1 (win64) Build 6140274 Thu May 22 00:12:29 MDT 2025 --- Date : Tue Apr 28 15:54:33 2026 --- Host : Lab016-05 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix --- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_RotaryEnc_0_0_sim_netlist.vhdl --- Design : design_1_RotaryEnc_0_0 --- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or --- synthesized. This netlist cannot be used for SDF annotated simulation. --- Device : xczu3eg-sfvc784-2-e --- -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_RotaryEnc is - port ( - Clk : in STD_LOGIC; - ROT_A : in STD_LOGIC; - ROT_B : in STD_LOGIC; - RotL : out STD_LOGIC; - RotR : out STD_LOGIC - ); -end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_RotaryEnc; - -architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_RotaryEnc is - signal FF : STD_LOGIC; - signal FF_i_1_n_0 : STD_LOGIC; - signal RotL0 : STD_LOGIC; - signal RotR0 : STD_LOGIC; - signal ffA : STD_LOGIC; - signal ffB : STD_LOGIC; - signal prevA : STD_LOGIC; - attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of RotL_i_1 : label is "soft_lutpair0"; - attribute SOFT_HLUTNM of RotR_i_1 : label is "soft_lutpair0"; -begin -FF_i_1: unisim.vcomponents.LUT3 - generic map( - INIT => X"E8" - ) - port map ( - I0 => FF, - I1 => ffA, - I2 => ffB, - O => FF_i_1_n_0 - ); -FF_reg: unisim.vcomponents.FDRE - generic map( - INIT => '1' - ) - port map ( - C => Clk, - CE => '1', - D => FF_i_1_n_0, - Q => FF, - R => '0' - ); -RotL_i_1: unisim.vcomponents.LUT4 - generic map( - INIT => X"0040" - ) - port map ( - I0 => FF, - I1 => ffB, - I2 => ffA, - I3 => prevA, - O => RotL0 - ); -RotL_reg: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => Clk, - CE => '1', - D => RotL0, - Q => RotL, - R => '0' - ); -RotR_i_1: unisim.vcomponents.LUT4 - generic map( - INIT => X"2000" - ) - port map ( - I0 => prevA, - I1 => FF, - I2 => ffB, - I3 => ffA, - O => RotR0 - ); -RotR_reg: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => Clk, - CE => '1', - D => RotR0, - Q => RotR, - R => '0' - ); -ffA_reg: unisim.vcomponents.FDRE - generic map( - INIT => '1' - ) - port map ( - C => Clk, - CE => '1', - D => ROT_A, - Q => ffA, - R => '0' - ); -ffB_reg: unisim.vcomponents.FDRE - generic map( - INIT => '1' - ) - port map ( - C => Clk, - CE => '1', - D => ROT_B, - Q => ffB, - R => '0' - ); -prevA_reg: unisim.vcomponents.FDRE - generic map( - INIT => '1' - ) - port map ( - C => Clk, - CE => '1', - D => ffA, - Q => prevA, - R => '0' - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_RotaryEnc_wrap is - port ( - RotL : out STD_LOGIC; - RotR : out STD_LOGIC; - ROT_A : in STD_LOGIC; - ROT_B : in STD_LOGIC; - Clk : in STD_LOGIC - ); -end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_RotaryEnc_wrap; - -architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_RotaryEnc_wrap is -begin -i_wrap: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_RotaryEnc - port map ( - Clk => Clk, - ROT_A => ROT_A, - ROT_B => ROT_B, - RotL => RotL, - RotR => RotR - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is - port ( - ROT_A : in STD_LOGIC; - ROT_B : in STD_LOGIC; - Clk : in STD_LOGIC; - RotL : out STD_LOGIC; - RotR : out STD_LOGIC - ); - attribute NotValidForBitStream : boolean; - attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; - attribute CHECK_LICENSE_TYPE : string; - attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "design_1_RotaryEnc_0_0,RotaryEnc_wrap,{}"; - attribute downgradeipidentifiedwarnings : string; - attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes"; - attribute ip_definition_source : string; - attribute ip_definition_source of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "package_project"; - attribute x_core_info : string; - attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "RotaryEnc_wrap,Vivado 2025.1"; -end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; - -architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is -begin -U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_RotaryEnc_wrap - port map ( - Clk => Clk, - ROT_A => ROT_A, - ROT_B => ROT_B, - RotL => RotL, - RotR => RotR - ); -end STRUCTURE; diff --git a/SW2.cache/ip/2025.1/1/4/14830d1ba75c4316/design_1_RotaryEnc_0_0_stub.v b/SW2.cache/ip/2025.1/1/4/14830d1ba75c4316/design_1_RotaryEnc_0_0_stub.v deleted file mode 100644 index 856d753..0000000 --- a/SW2.cache/ip/2025.1/1/4/14830d1ba75c4316/design_1_RotaryEnc_0_0_stub.v +++ /dev/null @@ -1,27 +0,0 @@ -// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2025.1 (win64) Build 6140274 Thu May 22 00:12:29 MDT 2025 -// Date : Tue Apr 28 15:54:33 2026 -// Host : Lab016-05 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_RotaryEnc_0_0_stub.v -// Design : design_1_RotaryEnc_0_0 -// Purpose : Stub declaration of top-level module interface -// Device : xczu3eg-sfvc784-2-e -// -------------------------------------------------------------------------------- - -// This empty module with port declaration file causes synthesis tools to infer a black box for IP. -// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. -// Please paste the declaration into a Verilog source file or add the file as an additional source. -(* CHECK_LICENSE_TYPE = "design_1_RotaryEnc_0_0,RotaryEnc_wrap,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) -(* x_core_info = "RotaryEnc_wrap,Vivado 2025.1" *) -module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(ROT_A, ROT_B, Clk, RotL, RotR) -/* synthesis syn_black_box black_box_pad_pin="ROT_A,ROT_B,RotL,RotR" */ -/* synthesis syn_force_seq_prim="Clk" */; - input ROT_A; - input ROT_B; - input Clk /* synthesis syn_isclock = 1 */; - output RotL; - output RotR; -endmodule diff --git a/SW2.cache/ip/2025.1/1/4/14830d1ba75c4316/design_1_RotaryEnc_0_0_stub.vhdl b/SW2.cache/ip/2025.1/1/4/14830d1ba75c4316/design_1_RotaryEnc_0_0_stub.vhdl deleted file mode 100644 index 86c1690..0000000 --- a/SW2.cache/ip/2025.1/1/4/14830d1ba75c4316/design_1_RotaryEnc_0_0_stub.vhdl +++ /dev/null @@ -1,41 +0,0 @@ --- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. --- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2025.1 (win64) Build 6140274 Thu May 22 00:12:29 MDT 2025 --- Date : Tue Apr 28 15:54:33 2026 --- Host : Lab016-05 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix --- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_RotaryEnc_0_0_stub.vhdl --- Design : design_1_RotaryEnc_0_0 --- Purpose : Stub declaration of top-level module interface --- Device : xczu3eg-sfvc784-2-e --- -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - -entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is - Port ( - ROT_A : in STD_LOGIC; - ROT_B : in STD_LOGIC; - Clk : in STD_LOGIC; - RotL : out STD_LOGIC; - RotR : out STD_LOGIC - ); - - attribute CHECK_LICENSE_TYPE : string; - attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "design_1_RotaryEnc_0_0,RotaryEnc_wrap,{}"; - attribute downgradeipidentifiedwarnings : string; - attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes"; - attribute ip_definition_source : string; - attribute ip_definition_source of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "package_project"; -end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; - -architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is - attribute syn_black_box : boolean; - attribute black_box_pad_pin : string; - attribute syn_black_box of stub : architecture is true; - attribute black_box_pad_pin of stub : architecture is "ROT_A,ROT_B,Clk,RotL,RotR"; - attribute x_core_info : string; - attribute x_core_info of stub : architecture is "RotaryEnc_wrap,Vivado 2025.1"; -begin -end; diff --git a/SW2.cache/ip/2025.1/3/5/35d46e42f86c55d9/35d46e42f86c55d9.xci b/SW2.cache/ip/2025.1/3/5/35d46e42f86c55d9/35d46e42f86c55d9.xci deleted file mode 100644 index 4616199..0000000 --- a/SW2.cache/ip/2025.1/3/5/35d46e42f86c55d9/35d46e42f86c55d9.xci +++ /dev/null @@ -1,297 +0,0 @@ - - - xilinx.com - ipcache - 35d46e42f86c55d9 - 0 - - - design_1_clk_wiz_0_0 - - - 100000000 - 25000000 - 125000000 - MMCM - false - empty - cddcdone - cddcreq - clkfb_in_n - clkfb_in - clkfb_in_p - SINGLE - clkfb_out_n - clkfb_out - clkfb_out_p - clkfb_stopped - 100.0 - 0.010 - 100.0 - 0.010 - Buffer - 148.007 - false - 84.520 - 50.000 - 25 - 0.000 - 1 - true - Buffer - 107.502 - false - 84.520 - 50.000 - 125 - 0.000 - 1 - true - Buffer - 0.0 - false - 0.0 - 50.000 - 100.000 - 0.000 - 1 - false - Buffer - 0.0 - false - 0.0 - 50.000 - 100.000 - 0.000 - 1 - false - Buffer - 0.0 - false - 0.0 - 50.000 - 100.000 - 0.000 - 1 - false - Buffer - 0.0 - false - 0.0 - 50.000 - 100.000 - 0.000 - 1 - false - Buffer - 0.0 - false - 0.0 - 50.000 - 100.000 - 0.000 - 1 - false - 600.000 - clk_100mhz - Custom - clk_in_sel - clk25 - false - clk125 - false - clk_out3 - false - clk_out4 - false - clk_out5 - false - clk_out6 - false - clk_out7 - false - CLK_VALID - auto - design_1_clk_wiz_0_0 - daddr - dclk - den - Custom - Custom - din - dout - drdy - dwe - false - false - false - false - false - false - false - false - false - FDBK_AUTO - input_clk_stopped - frequency - Enable_AXI - Units_MHz - Units_UI - UI - No_Jitter - locked - OPTIMIZED - 12.500 - 0.000 - false - 10.000 - 10.000 - 50.000 - 0.500 - 0.000 - false - 10 - 0.500 - 0.000 - false - 1 - 0.500 - 0.000 - false - 1 - 0.500 - 0.000 - false - false - 1 - 0.500 - 0.000 - false - 1 - 0.500 - 0.000 - false - 1 - 0.500 - 0.000 - false - false - AUTO - 1 - None - 0.010 - 0.010 - false - 2 - false - false - false - LATENCY - false - UNKNOWN - OPTIMIZED - 4 - 0.000 - 10.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - CLKFBOUT - SYSTEM_SYNCHRONOUS - 1 - None - 0.010 - power_down - 1 - clk_in1 - MMCM - mmcm_adv - 100.000 - 0.010 - 10.000 - Differential_clock_capable_pin - psclk - psdone - psen - psincdec - 100.0 - REL_PRIMARY - Custom - reset - ACTIVE_HIGH - 100.000 - 0.010 - 10.000 - clk_in2 - Single_ended_clock_capable_pin - CENTER_HIGH - 250 - 0.004 - STATUS - empty - 100.0 - 100.0 - 100.0 - 100.0 - true - false - false - false - false - false - false - true - false - false - true - false - false - false - false - false - true - false - false - false - zynquplus - realdigital.org:aup-zu3-8gb:part0:1.0 - xczu3eg - sfvc784 - VERILOG - - -2 - - E - e6a05ff8 - 35d46e42f86c55d9 - design_1_clk_wiz_0_0 - $Change: 6131539 $ - 70f51334 - 62 - IP_Unknown - 16 - TRUE - . - - . - 2025.1 - GLOBAL - - - - diff --git a/SW2.cache/ip/2025.1/3/5/35d46e42f86c55d9/design_1_clk_wiz_0_0.dcp b/SW2.cache/ip/2025.1/3/5/35d46e42f86c55d9/design_1_clk_wiz_0_0.dcp deleted file mode 100644 index f25ec2c..0000000 Binary files a/SW2.cache/ip/2025.1/3/5/35d46e42f86c55d9/design_1_clk_wiz_0_0.dcp and /dev/null differ diff --git a/SW2.cache/ip/2025.1/3/5/35d46e42f86c55d9/design_1_clk_wiz_0_0_sim_netlist.v b/SW2.cache/ip/2025.1/3/5/35d46e42f86c55d9/design_1_clk_wiz_0_0_sim_netlist.v deleted file mode 100644 index 2079875..0000000 --- a/SW2.cache/ip/2025.1/3/5/35d46e42f86c55d9/design_1_clk_wiz_0_0_sim_netlist.v +++ /dev/null @@ -1,293 +0,0 @@ -// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2025.1 (win64) Build 6140274 Thu May 22 00:12:29 MDT 2025 -// Date : Tue Apr 28 14:09:34 2026 -// Host : Lab016-05 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_clk_wiz_0_0_sim_netlist.v -// Design : design_1_clk_wiz_0_0 -// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified -// or synthesized. This netlist cannot be used for SDF annotated simulation. -// Device : xczu3eg-sfvc784-2-e -// -------------------------------------------------------------------------------- -`timescale 1 ps / 1 ps - -(* NotValidForBitStream *) -module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix - (clk25, - clk125, - reset, - locked, - clk_in1_p, - clk_in1_n); - output clk25; - output clk125; - input reset; - output locked; - input clk_in1_p; - input clk_in1_n; - - wire clk125; - wire clk25; - (* IBUF_LOW_PWR *) (* RTL_KEEP = "yes" *) wire clk_in1_n; - (* IBUF_LOW_PWR *) (* RTL_KEEP = "yes" *) wire clk_in1_p; - wire locked; - wire reset; - - decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_design_1_clk_wiz_0_0_clk_wiz inst - (.clk125(clk125), - .clk25(clk25), - .clk_in1_n(clk_in1_n), - .clk_in1_p(clk_in1_p), - .locked(locked), - .reset(reset)); -endmodule - -module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_design_1_clk_wiz_0_0_clk_wiz - (clk25, - clk125, - reset, - locked, - clk_in1_p, - clk_in1_n); - output clk25; - output clk125; - input reset; - output locked; - input clk_in1_p; - input clk_in1_n; - - wire clk125; - wire clk125_design_1_clk_wiz_0_0; - wire clk25; - wire clk25_design_1_clk_wiz_0_0; - wire clk_in1_design_1_clk_wiz_0_0; - wire clk_in1_n; - wire clk_in1_p; - wire locked; - wire reset; - wire NLW_mmcme4_adv_inst_CDDCDONE_UNCONNECTED; - wire NLW_mmcme4_adv_inst_CLKFBIN_UNCONNECTED; - wire NLW_mmcme4_adv_inst_CLKFBOUT_UNCONNECTED; - wire NLW_mmcme4_adv_inst_CLKFBOUTB_UNCONNECTED; - wire NLW_mmcme4_adv_inst_CLKFBSTOPPED_UNCONNECTED; - wire NLW_mmcme4_adv_inst_CLKINSTOPPED_UNCONNECTED; - wire NLW_mmcme4_adv_inst_CLKOUT0B_UNCONNECTED; - wire NLW_mmcme4_adv_inst_CLKOUT1B_UNCONNECTED; - wire NLW_mmcme4_adv_inst_CLKOUT2_UNCONNECTED; - wire NLW_mmcme4_adv_inst_CLKOUT2B_UNCONNECTED; - wire NLW_mmcme4_adv_inst_CLKOUT3_UNCONNECTED; - wire NLW_mmcme4_adv_inst_CLKOUT3B_UNCONNECTED; - wire NLW_mmcme4_adv_inst_CLKOUT4_UNCONNECTED; - wire NLW_mmcme4_adv_inst_CLKOUT5_UNCONNECTED; - wire NLW_mmcme4_adv_inst_CLKOUT6_UNCONNECTED; - wire NLW_mmcme4_adv_inst_DRDY_UNCONNECTED; - wire NLW_mmcme4_adv_inst_PSDONE_UNCONNECTED; - wire [15:0]NLW_mmcme4_adv_inst_DO_UNCONNECTED; - - (* BOX_TYPE = "PRIMITIVE" *) - (* CAPACITANCE = "DONT_CARE" *) - (* IBUF_DELAY_VALUE = "0" *) - (* IFD_DELAY_VALUE = "AUTO" *) - IBUFDS #( - .DIFF_TERM("FALSE"), - .IOSTANDARD("DEFAULT")) - clkin1_ibufds - (.I(clk_in1_p), - .IB(clk_in1_n), - .O(clk_in1_design_1_clk_wiz_0_0)); - (* BOX_TYPE = "PRIMITIVE" *) - (* XILINX_LEGACY_PRIM = "BUFG" *) - (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) - BUFGCE #( - .CE_TYPE("ASYNC"), - .SIM_DEVICE("ULTRASCALE_PLUS")) - clkout1_buf - (.CE(1'b1), - .I(clk25_design_1_clk_wiz_0_0), - .O(clk25)); - (* BOX_TYPE = "PRIMITIVE" *) - (* XILINX_LEGACY_PRIM = "BUFG" *) - (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) - BUFGCE #( - .CE_TYPE("ASYNC"), - .SIM_DEVICE("ULTRASCALE_PLUS")) - clkout2_buf - (.CE(1'b1), - .I(clk125_design_1_clk_wiz_0_0), - .O(clk125)); - (* BOX_TYPE = "PRIMITIVE" *) - (* OPT_MODIFIED = "MLO" *) - MMCME4_ADV #( - .BANDWIDTH("OPTIMIZED"), - .CLKFBOUT_MULT_F(12.500000), - .CLKFBOUT_PHASE(0.000000), - .CLKFBOUT_USE_FINE_PS("FALSE"), - .CLKIN1_PERIOD(10.000000), - .CLKIN2_PERIOD(0.000000), - .CLKOUT0_DIVIDE_F(50.000000), - .CLKOUT0_DUTY_CYCLE(0.500000), - .CLKOUT0_PHASE(0.000000), - .CLKOUT0_USE_FINE_PS("FALSE"), - .CLKOUT1_DIVIDE(10), - .CLKOUT1_DUTY_CYCLE(0.500000), - .CLKOUT1_PHASE(0.000000), - .CLKOUT1_USE_FINE_PS("FALSE"), - .CLKOUT2_DIVIDE(1), - .CLKOUT2_DUTY_CYCLE(0.500000), - .CLKOUT2_PHASE(0.000000), - .CLKOUT2_USE_FINE_PS("FALSE"), - .CLKOUT3_DIVIDE(1), - .CLKOUT3_DUTY_CYCLE(0.500000), - .CLKOUT3_PHASE(0.000000), - .CLKOUT3_USE_FINE_PS("FALSE"), - .CLKOUT4_CASCADE("FALSE"), - .CLKOUT4_DIVIDE(1), - .CLKOUT4_DUTY_CYCLE(0.500000), - .CLKOUT4_PHASE(0.000000), - .CLKOUT4_USE_FINE_PS("FALSE"), - .CLKOUT5_DIVIDE(1), - .CLKOUT5_DUTY_CYCLE(0.500000), - .CLKOUT5_PHASE(0.000000), - .CLKOUT5_USE_FINE_PS("FALSE"), - .CLKOUT6_DIVIDE(1), - .CLKOUT6_DUTY_CYCLE(0.500000), - .CLKOUT6_PHASE(0.000000), - .CLKOUT6_USE_FINE_PS("FALSE"), - .COMPENSATION("INTERNAL"), - .DIVCLK_DIVIDE(1), - .IS_CLKFBIN_INVERTED(1'b0), - .IS_CLKIN1_INVERTED(1'b0), - .IS_CLKIN2_INVERTED(1'b0), - .IS_CLKINSEL_INVERTED(1'b0), - .IS_PSEN_INVERTED(1'b0), - .IS_PSINCDEC_INVERTED(1'b0), - .IS_PWRDWN_INVERTED(1'b0), - .IS_RST_INVERTED(1'b0), - .REF_JITTER1(0.010000), - .REF_JITTER2(0.010000), - .SS_EN("FALSE"), - .SS_MODE("CENTER_HIGH"), - .SS_MOD_PERIOD(10000), - .STARTUP_WAIT("FALSE")) - mmcme4_adv_inst - (.CDDCDONE(NLW_mmcme4_adv_inst_CDDCDONE_UNCONNECTED), - .CDDCREQ(1'b0), - .CLKFBIN(NLW_mmcme4_adv_inst_CLKFBIN_UNCONNECTED), - .CLKFBOUT(NLW_mmcme4_adv_inst_CLKFBOUT_UNCONNECTED), - .CLKFBOUTB(NLW_mmcme4_adv_inst_CLKFBOUTB_UNCONNECTED), - .CLKFBSTOPPED(NLW_mmcme4_adv_inst_CLKFBSTOPPED_UNCONNECTED), - .CLKIN1(clk_in1_design_1_clk_wiz_0_0), - .CLKIN2(1'b0), - .CLKINSEL(1'b1), - .CLKINSTOPPED(NLW_mmcme4_adv_inst_CLKINSTOPPED_UNCONNECTED), - .CLKOUT0(clk25_design_1_clk_wiz_0_0), - .CLKOUT0B(NLW_mmcme4_adv_inst_CLKOUT0B_UNCONNECTED), - .CLKOUT1(clk125_design_1_clk_wiz_0_0), - .CLKOUT1B(NLW_mmcme4_adv_inst_CLKOUT1B_UNCONNECTED), - .CLKOUT2(NLW_mmcme4_adv_inst_CLKOUT2_UNCONNECTED), - .CLKOUT2B(NLW_mmcme4_adv_inst_CLKOUT2B_UNCONNECTED), - .CLKOUT3(NLW_mmcme4_adv_inst_CLKOUT3_UNCONNECTED), - .CLKOUT3B(NLW_mmcme4_adv_inst_CLKOUT3B_UNCONNECTED), - .CLKOUT4(NLW_mmcme4_adv_inst_CLKOUT4_UNCONNECTED), - .CLKOUT5(NLW_mmcme4_adv_inst_CLKOUT5_UNCONNECTED), - .CLKOUT6(NLW_mmcme4_adv_inst_CLKOUT6_UNCONNECTED), - .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .DCLK(1'b0), - .DEN(1'b0), - .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .DO(NLW_mmcme4_adv_inst_DO_UNCONNECTED[15:0]), - .DRDY(NLW_mmcme4_adv_inst_DRDY_UNCONNECTED), - .DWE(1'b0), - .LOCKED(locked), - .PSCLK(1'b0), - .PSDONE(NLW_mmcme4_adv_inst_PSDONE_UNCONNECTED), - .PSEN(1'b0), - .PSINCDEC(1'b0), - .PWRDWN(1'b0), - .RST(reset)); -endmodule -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - parameter GRES_WIDTH = 10000; - parameter GRES_START = 10000; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - wire GRESTORE; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - reg GRESTORE_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - assign (strong1, weak0) GRESTORE = GRESTORE_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - - initial begin - GRESTORE_int = 1'b0; - #(GRES_START); - GRESTORE_int = 1'b1; - #(GRES_WIDTH); - GRESTORE_int = 1'b0; - end - -endmodule -`endif diff --git a/SW2.cache/ip/2025.1/3/5/35d46e42f86c55d9/design_1_clk_wiz_0_0_sim_netlist.vhdl b/SW2.cache/ip/2025.1/3/5/35d46e42f86c55d9/design_1_clk_wiz_0_0_sim_netlist.vhdl deleted file mode 100644 index 89b1ceb..0000000 --- a/SW2.cache/ip/2025.1/3/5/35d46e42f86c55d9/design_1_clk_wiz_0_0_sim_netlist.vhdl +++ /dev/null @@ -1,221 +0,0 @@ --- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. --- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2025.1 (win64) Build 6140274 Thu May 22 00:12:29 MDT 2025 --- Date : Tue Apr 28 14:09:34 2026 --- Host : Lab016-05 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix --- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_clk_wiz_0_0_sim_netlist.vhdl --- Design : design_1_clk_wiz_0_0 --- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or --- synthesized. This netlist cannot be used for SDF annotated simulation. --- Device : xczu3eg-sfvc784-2-e --- -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_design_1_clk_wiz_0_0_clk_wiz is - port ( - clk25 : out STD_LOGIC; - clk125 : out STD_LOGIC; - reset : in STD_LOGIC; - locked : out STD_LOGIC; - clk_in1_p : in STD_LOGIC; - clk_in1_n : in STD_LOGIC - ); -end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_design_1_clk_wiz_0_0_clk_wiz; - -architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_design_1_clk_wiz_0_0_clk_wiz is - signal clk125_design_1_clk_wiz_0_0 : STD_LOGIC; - signal clk25_design_1_clk_wiz_0_0 : STD_LOGIC; - signal clk_in1_design_1_clk_wiz_0_0 : STD_LOGIC; - signal NLW_mmcme4_adv_inst_CDDCDONE_UNCONNECTED : STD_LOGIC; - signal NLW_mmcme4_adv_inst_CLKFBIN_UNCONNECTED : STD_LOGIC; - signal NLW_mmcme4_adv_inst_CLKFBOUT_UNCONNECTED : STD_LOGIC; - signal NLW_mmcme4_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC; - signal NLW_mmcme4_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC; - signal NLW_mmcme4_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC; - signal NLW_mmcme4_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC; - signal NLW_mmcme4_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC; - signal NLW_mmcme4_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC; - signal NLW_mmcme4_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC; - signal NLW_mmcme4_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC; - signal NLW_mmcme4_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC; - signal NLW_mmcme4_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC; - signal NLW_mmcme4_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC; - signal NLW_mmcme4_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC; - signal NLW_mmcme4_adv_inst_DRDY_UNCONNECTED : STD_LOGIC; - signal NLW_mmcme4_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC; - signal NLW_mmcme4_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); - attribute BOX_TYPE : string; - attribute BOX_TYPE of clkin1_ibufds : label is "PRIMITIVE"; - attribute CAPACITANCE : string; - attribute CAPACITANCE of clkin1_ibufds : label is "DONT_CARE"; - attribute IBUF_DELAY_VALUE : string; - attribute IBUF_DELAY_VALUE of clkin1_ibufds : label is "0"; - attribute IFD_DELAY_VALUE : string; - attribute IFD_DELAY_VALUE of clkin1_ibufds : label is "AUTO"; - attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM : string; - attribute XILINX_LEGACY_PRIM of clkout1_buf : label is "BUFG"; - attribute XILINX_TRANSFORM_PINMAP : string; - attribute XILINX_TRANSFORM_PINMAP of clkout1_buf : label is "VCC:CE"; - attribute BOX_TYPE of clkout2_buf : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of clkout2_buf : label is "BUFG"; - attribute XILINX_TRANSFORM_PINMAP of clkout2_buf : label is "VCC:CE"; - attribute BOX_TYPE of mmcme4_adv_inst : label is "PRIMITIVE"; - attribute OPT_MODIFIED : string; - attribute OPT_MODIFIED of mmcme4_adv_inst : label is "MLO"; -begin -clkin1_ibufds: unisim.vcomponents.IBUFDS - generic map( - DIFF_TERM => false, - IOSTANDARD => "DEFAULT" - ) - port map ( - I => clk_in1_p, - IB => clk_in1_n, - O => clk_in1_design_1_clk_wiz_0_0 - ); -clkout1_buf: unisim.vcomponents.BUFGCE - generic map( - CE_TYPE => "ASYNC", - SIM_DEVICE => "ULTRASCALE_PLUS" - ) - port map ( - CE => '1', - I => clk25_design_1_clk_wiz_0_0, - O => clk25 - ); -clkout2_buf: unisim.vcomponents.BUFGCE - generic map( - CE_TYPE => "ASYNC", - SIM_DEVICE => "ULTRASCALE_PLUS" - ) - port map ( - CE => '1', - I => clk125_design_1_clk_wiz_0_0, - O => clk125 - ); -mmcme4_adv_inst: unisim.vcomponents.MMCME4_ADV - generic map( - BANDWIDTH => "OPTIMIZED", - CLKFBOUT_MULT_F => 12.500000, - CLKFBOUT_PHASE => 0.000000, - CLKFBOUT_USE_FINE_PS => "FALSE", - CLKIN1_PERIOD => 10.000000, - CLKIN2_PERIOD => 0.000000, - CLKOUT0_DIVIDE_F => 50.000000, - CLKOUT0_DUTY_CYCLE => 0.500000, - CLKOUT0_PHASE => 0.000000, - CLKOUT0_USE_FINE_PS => "FALSE", - CLKOUT1_DIVIDE => 10, - CLKOUT1_DUTY_CYCLE => 0.500000, - CLKOUT1_PHASE => 0.000000, - CLKOUT1_USE_FINE_PS => "FALSE", - CLKOUT2_DIVIDE => 1, - CLKOUT2_DUTY_CYCLE => 0.500000, - CLKOUT2_PHASE => 0.000000, - CLKOUT2_USE_FINE_PS => "FALSE", - CLKOUT3_DIVIDE => 1, - CLKOUT3_DUTY_CYCLE => 0.500000, - CLKOUT3_PHASE => 0.000000, - CLKOUT3_USE_FINE_PS => "FALSE", - CLKOUT4_CASCADE => "FALSE", - CLKOUT4_DIVIDE => 1, - CLKOUT4_DUTY_CYCLE => 0.500000, - CLKOUT4_PHASE => 0.000000, - CLKOUT4_USE_FINE_PS => "FALSE", - CLKOUT5_DIVIDE => 1, - CLKOUT5_DUTY_CYCLE => 0.500000, - CLKOUT5_PHASE => 0.000000, - CLKOUT5_USE_FINE_PS => "FALSE", - CLKOUT6_DIVIDE => 1, - CLKOUT6_DUTY_CYCLE => 0.500000, - CLKOUT6_PHASE => 0.000000, - CLKOUT6_USE_FINE_PS => "FALSE", - COMPENSATION => "INTERNAL", - DIVCLK_DIVIDE => 1, - IS_CLKFBIN_INVERTED => '0', - IS_CLKIN1_INVERTED => '0', - IS_CLKIN2_INVERTED => '0', - IS_CLKINSEL_INVERTED => '0', - IS_PSEN_INVERTED => '0', - IS_PSINCDEC_INVERTED => '0', - IS_PWRDWN_INVERTED => '0', - IS_RST_INVERTED => '0', - REF_JITTER1 => 0.010000, - REF_JITTER2 => 0.010000, - SS_EN => "FALSE", - SS_MODE => "CENTER_HIGH", - SS_MOD_PERIOD => 10000, - STARTUP_WAIT => "FALSE" - ) - port map ( - CDDCDONE => NLW_mmcme4_adv_inst_CDDCDONE_UNCONNECTED, - CDDCREQ => '0', - CLKFBIN => NLW_mmcme4_adv_inst_CLKFBIN_UNCONNECTED, - CLKFBOUT => NLW_mmcme4_adv_inst_CLKFBOUT_UNCONNECTED, - CLKFBOUTB => NLW_mmcme4_adv_inst_CLKFBOUTB_UNCONNECTED, - CLKFBSTOPPED => NLW_mmcme4_adv_inst_CLKFBSTOPPED_UNCONNECTED, - CLKIN1 => clk_in1_design_1_clk_wiz_0_0, - CLKIN2 => '0', - CLKINSEL => '1', - CLKINSTOPPED => NLW_mmcme4_adv_inst_CLKINSTOPPED_UNCONNECTED, - CLKOUT0 => clk25_design_1_clk_wiz_0_0, - CLKOUT0B => NLW_mmcme4_adv_inst_CLKOUT0B_UNCONNECTED, - CLKOUT1 => clk125_design_1_clk_wiz_0_0, - CLKOUT1B => NLW_mmcme4_adv_inst_CLKOUT1B_UNCONNECTED, - CLKOUT2 => NLW_mmcme4_adv_inst_CLKOUT2_UNCONNECTED, - CLKOUT2B => NLW_mmcme4_adv_inst_CLKOUT2B_UNCONNECTED, - CLKOUT3 => NLW_mmcme4_adv_inst_CLKOUT3_UNCONNECTED, - CLKOUT3B => NLW_mmcme4_adv_inst_CLKOUT3B_UNCONNECTED, - CLKOUT4 => NLW_mmcme4_adv_inst_CLKOUT4_UNCONNECTED, - CLKOUT5 => NLW_mmcme4_adv_inst_CLKOUT5_UNCONNECTED, - CLKOUT6 => NLW_mmcme4_adv_inst_CLKOUT6_UNCONNECTED, - DADDR(6 downto 0) => B"0000000", - DCLK => '0', - DEN => '0', - DI(15 downto 0) => B"0000000000000000", - DO(15 downto 0) => NLW_mmcme4_adv_inst_DO_UNCONNECTED(15 downto 0), - DRDY => NLW_mmcme4_adv_inst_DRDY_UNCONNECTED, - DWE => '0', - LOCKED => locked, - PSCLK => '0', - PSDONE => NLW_mmcme4_adv_inst_PSDONE_UNCONNECTED, - PSEN => '0', - PSINCDEC => '0', - PWRDWN => '0', - RST => reset - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is - port ( - clk25 : out STD_LOGIC; - clk125 : out STD_LOGIC; - reset : in STD_LOGIC; - locked : out STD_LOGIC; - clk_in1_p : in STD_LOGIC; - clk_in1_n : in STD_LOGIC - ); - attribute NotValidForBitStream : boolean; - attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; -end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; - -architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is -begin -inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_design_1_clk_wiz_0_0_clk_wiz - port map ( - clk125 => clk125, - clk25 => clk25, - clk_in1_n => clk_in1_n, - clk_in1_p => clk_in1_p, - locked => locked, - reset => reset - ); -end STRUCTURE; diff --git a/SW2.cache/ip/2025.1/3/5/35d46e42f86c55d9/design_1_clk_wiz_0_0_stub.v b/SW2.cache/ip/2025.1/3/5/35d46e42f86c55d9/design_1_clk_wiz_0_0_stub.v deleted file mode 100644 index b2ea77b..0000000 --- a/SW2.cache/ip/2025.1/3/5/35d46e42f86c55d9/design_1_clk_wiz_0_0_stub.v +++ /dev/null @@ -1,28 +0,0 @@ -// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2025.1 (win64) Build 6140274 Thu May 22 00:12:29 MDT 2025 -// Date : Tue Apr 28 14:09:34 2026 -// Host : Lab016-05 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_clk_wiz_0_0_stub.v -// Design : design_1_clk_wiz_0_0 -// Purpose : Stub declaration of top-level module interface -// Device : xczu3eg-sfvc784-2-e -// -------------------------------------------------------------------------------- - -// This empty module with port declaration file causes synthesis tools to infer a black box for IP. -// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. -// Please paste the declaration into a Verilog source file or add the file as an additional source. -(* CORE_GENERATION_INFO = "design_1_clk_wiz_0_0,clk_wiz_v6_0_16_0_0,{component_name=design_1_clk_wiz_0_0,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *) -module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk25, clk125, reset, locked, clk_in1_p, clk_in1_n) -/* synthesis syn_black_box black_box_pad_pin="reset,locked,clk_in1_p,clk_in1_n" */ -/* synthesis syn_force_seq_prim="clk25" */ -/* synthesis syn_force_seq_prim="clk125" */; - output clk25 /* synthesis syn_isclock = 1 */; - output clk125 /* synthesis syn_isclock = 1 */; - input reset; - output locked; - input clk_in1_p; - input clk_in1_n; -endmodule diff --git a/SW2.cache/ip/2025.1/3/5/35d46e42f86c55d9/design_1_clk_wiz_0_0_stub.vhdl b/SW2.cache/ip/2025.1/3/5/35d46e42f86c55d9/design_1_clk_wiz_0_0_stub.vhdl deleted file mode 100644 index 510ab4c..0000000 --- a/SW2.cache/ip/2025.1/3/5/35d46e42f86c55d9/design_1_clk_wiz_0_0_stub.vhdl +++ /dev/null @@ -1,36 +0,0 @@ --- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. --- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2025.1 (win64) Build 6140274 Thu May 22 00:12:29 MDT 2025 --- Date : Tue Apr 28 14:09:34 2026 --- Host : Lab016-05 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix --- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_clk_wiz_0_0_stub.vhdl --- Design : design_1_clk_wiz_0_0 --- Purpose : Stub declaration of top-level module interface --- Device : xczu3eg-sfvc784-2-e --- -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - -entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is - Port ( - clk25 : out STD_LOGIC; - clk125 : out STD_LOGIC; - reset : in STD_LOGIC; - locked : out STD_LOGIC; - clk_in1_p : in STD_LOGIC; - clk_in1_n : in STD_LOGIC - ); - - attribute CORE_GENERATION_INFO : string; - attribute CORE_GENERATION_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "design_1_clk_wiz_0_0,clk_wiz_v6_0_16_0_0,{component_name=design_1_clk_wiz_0_0,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}"; -end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; - -architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is - attribute syn_black_box : boolean; - attribute black_box_pad_pin : string; - attribute syn_black_box of stub : architecture is true; - attribute black_box_pad_pin of stub : architecture is "clk25,clk125,reset,locked,clk_in1_p,clk_in1_n"; -begin -end; diff --git a/SW2.cache/ip/2025.1/5/b/5be5567f865f5e2e/5be5567f865f5e2e.xci b/SW2.cache/ip/2025.1/5/b/5be5567f865f5e2e/5be5567f865f5e2e.xci deleted file mode 100644 index 67d73dc..0000000 --- a/SW2.cache/ip/2025.1/5/b/5be5567f865f5e2e/5be5567f865f5e2e.xci +++ /dev/null @@ -1,37 +0,0 @@ - - - xilinx.com - ipcache - 5be5567f865f5e2e - 0 - - - design_1_HDMI_TX_0_0 - - - design_1_HDMI_TX_0_0 - zynquplus - realdigital.org:aup-zu3-8gb:part0:1.0 - xczu3eg - sfvc784 - VERILOG - - -2 - - E - 5be5567f865f5e2e - $Change: 6131539 $ - 4457ddfd - 55 - IP_Unknown - 2 - TRUE - . - - . - 2025.1 - GLOBAL - - - - diff --git a/SW2.cache/ip/2025.1/5/b/5be5567f865f5e2e/design_1_HDMI_TX_0_0.dcp b/SW2.cache/ip/2025.1/5/b/5be5567f865f5e2e/design_1_HDMI_TX_0_0.dcp deleted file mode 100644 index 7531f70..0000000 Binary files a/SW2.cache/ip/2025.1/5/b/5be5567f865f5e2e/design_1_HDMI_TX_0_0.dcp and /dev/null differ diff --git a/SW2.cache/ip/2025.1/5/b/5be5567f865f5e2e/design_1_HDMI_TX_0_0_sim_netlist.v b/SW2.cache/ip/2025.1/5/b/5be5567f865f5e2e/design_1_HDMI_TX_0_0_sim_netlist.v deleted file mode 100644 index 23f7683..0000000 --- a/SW2.cache/ip/2025.1/5/b/5be5567f865f5e2e/design_1_HDMI_TX_0_0_sim_netlist.v +++ /dev/null @@ -1,3374 +0,0 @@ -// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2025.1 (win64) Build 6140274 Thu May 22 00:12:29 MDT 2025 -// Date : Tue Apr 28 14:09:27 2026 -// Host : Lab016-05 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_HDMI_TX_0_0_sim_netlist.v -// Design : design_1_HDMI_TX_0_0 -// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified -// or synthesized. This netlist cannot be used for SDF annotated simulation. -// Device : xczu3eg-sfvc784-2-e -// -------------------------------------------------------------------------------- -`timescale 1 ps / 1 ps - -module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_HDMI_TX - (DE, - HDMI_CK_N, - HDMI_CK_P, - HDMI_D0_N, - HDMI_D0_P, - HDMI_D1_N, - HDMI_D1_P, - HDMI_D2_N, - HDMI_D2_P, - HSync, - ResetN, - VSync, - pxClk, - pxClkX5, - B, - G, - R); - input DE; - output HDMI_CK_N; - output HDMI_CK_P; - output HDMI_D0_N; - output HDMI_D0_P; - output HDMI_D1_N; - output HDMI_D1_P; - output HDMI_D2_N; - output HDMI_D2_P; - input HSync; - input ResetN; - input VSync; - input pxClk; - input pxClkX5; - input [7:0]B; - input [7:0]G; - input [7:0]R; - - wire [7:0]B; - wire \Cnt[1]_i_1__0_n_0 ; - wire \Cnt[1]_i_1__1_n_0 ; - wire \Cnt[1]_i_1_n_0 ; - wire \Cnt[1]_i_2__0_n_0 ; - wire \Cnt[1]_i_2_n_0 ; - wire \Cnt[2]_i_1_n_0 ; - wire \Cnt[2]_i_2__0_n_0 ; - wire \Cnt[2]_i_2__1_n_0 ; - wire \Cnt[2]_i_2_n_0 ; - wire \Cnt[2]_i_3__0_n_0 ; - wire \Cnt[2]_i_3__1_n_0 ; - wire \Cnt[2]_i_3_n_0 ; - wire \Cnt[2]_i_4_n_0 ; - wire \Cnt[2]_i_5_n_0 ; - wire \Cnt[3]_i_1__0_n_0 ; - wire \Cnt[3]_i_1_n_0 ; - wire \Cnt[3]_i_2__0_n_0 ; - wire \Cnt[3]_i_2__1_n_0 ; - wire \Cnt[3]_i_2_n_0 ; - wire \Cnt[3]_i_3__0_n_0 ; - wire \Cnt[3]_i_3__1_n_0 ; - wire \Cnt[3]_i_3_n_0 ; - wire \Cnt[3]_i_4__0_n_0 ; - wire \Cnt[3]_i_4__1_n_0 ; - wire \Cnt[3]_i_4_n_0 ; - wire \Cnt[3]_i_5__0_n_0 ; - wire \Cnt[3]_i_5__1_n_0 ; - wire \Cnt[3]_i_5_n_0 ; - wire \Cnt[3]_i_6__0_n_0 ; - wire \Cnt[3]_i_6_n_0 ; - wire \Cnt[3]_i_7_n_0 ; - wire \Cnt[3]_i_8_n_0 ; - wire \Cnt[4]_i_10__0_n_0 ; - wire \Cnt[4]_i_10__1_n_0 ; - wire \Cnt[4]_i_10_n_0 ; - wire \Cnt[4]_i_11__0_n_0 ; - wire \Cnt[4]_i_11__1_n_0 ; - wire \Cnt[4]_i_11_n_0 ; - wire \Cnt[4]_i_12__0_n_0 ; - wire \Cnt[4]_i_12__1_n_0 ; - wire \Cnt[4]_i_12_n_0 ; - wire \Cnt[4]_i_13__0_n_0 ; - wire \Cnt[4]_i_13__1_n_0 ; - wire \Cnt[4]_i_13_n_0 ; - wire \Cnt[4]_i_14__0_n_0 ; - wire \Cnt[4]_i_14__1_n_0 ; - wire \Cnt[4]_i_14_n_0 ; - wire \Cnt[4]_i_15__0_n_0 ; - wire \Cnt[4]_i_15__1_n_0 ; - wire \Cnt[4]_i_15_n_0 ; - wire \Cnt[4]_i_16__0_n_0 ; - wire \Cnt[4]_i_16__1_n_0 ; - wire \Cnt[4]_i_16_n_0 ; - wire \Cnt[4]_i_17__0_n_0 ; - wire \Cnt[4]_i_17_n_0 ; - wire \Cnt[4]_i_18__0_n_0 ; - wire \Cnt[4]_i_18_n_0 ; - wire \Cnt[4]_i_19__0_n_0 ; - wire \Cnt[4]_i_19_n_0 ; - wire \Cnt[4]_i_1__0_n_0 ; - wire \Cnt[4]_i_1__1_n_0 ; - wire \Cnt[4]_i_1_n_0 ; - wire \Cnt[4]_i_20__0_n_0 ; - wire \Cnt[4]_i_20_n_0 ; - wire \Cnt[4]_i_21__0_n_0 ; - wire \Cnt[4]_i_21_n_0 ; - wire \Cnt[4]_i_22_n_0 ; - wire \Cnt[4]_i_23_n_0 ; - wire \Cnt[4]_i_24_n_0 ; - wire \Cnt[4]_i_25_n_0 ; - wire \Cnt[4]_i_2__0_n_0 ; - wire \Cnt[4]_i_2__1_n_0 ; - wire \Cnt[4]_i_2_n_0 ; - wire \Cnt[4]_i_3__0_n_0 ; - wire \Cnt[4]_i_3__1_n_0 ; - wire \Cnt[4]_i_3_n_0 ; - wire \Cnt[4]_i_4__0_n_0 ; - wire \Cnt[4]_i_4__1_n_0 ; - wire \Cnt[4]_i_4_n_0 ; - wire \Cnt[4]_i_5__0_n_0 ; - wire \Cnt[4]_i_5__1_n_0 ; - wire \Cnt[4]_i_5_n_0 ; - wire \Cnt[4]_i_6__0_n_0 ; - wire \Cnt[4]_i_6__1_n_0 ; - wire \Cnt[4]_i_6_n_0 ; - wire \Cnt[4]_i_7__0_n_0 ; - wire \Cnt[4]_i_7__1_n_0 ; - wire \Cnt[4]_i_7_n_0 ; - wire \Cnt[4]_i_8__0_n_0 ; - wire \Cnt[4]_i_8__1_n_0 ; - wire \Cnt[4]_i_8_n_0 ; - wire \Cnt[4]_i_9__0_n_0 ; - wire \Cnt[4]_i_9__1_n_0 ; - wire \Cnt[4]_i_9_n_0 ; - wire \Cnt_reg[2]_i_1__0_n_0 ; - wire \Cnt_reg[2]_i_1_n_0 ; - wire \Cnt_reg[3]_i_1_n_0 ; - wire DE; - wire [7:0]G; - wire HDMI_CK_N; - wire HDMI_CK_P; - wire HDMI_D0_N; - wire HDMI_D0_P; - wire HDMI_D1_N; - wire HDMI_D1_P; - wire HDMI_D2_N; - wire HDMI_D2_P; - wire HSync; - wire [7:0]R; - wire ResetN; - wire \TMDS_0/D1 ; - wire \TMDS_0/D2 ; - wire [4:1]\TMDS_0/i_Enc/Cnt_reg_n_0_ ; - wire \TMDS_0/i_Enc/p_0_in ; - wire \TMDS_0/i_Enc/p_10_in ; - wire \TMDS_0/i_Enc/p_12_in ; - wire \TMDS_0/i_Enc/p_2_in ; - wire \TMDS_0/i_Enc/p_4_in ; - wire \TMDS_0/i_Enc/p_6_in ; - wire \TMDS_0/i_Enc/p_8_in ; - wire [0:0]\TMDS_0/i_Enc/qD_reg_n_0_ ; - wire [2:0]\TMDS_0/i_GBox/cntMod5_reg_n_0_ ; - wire [9:2]\TMDS_0/i_GBox/sReg_reg_n_0_ ; - wire \TMDS_1/D1 ; - wire \TMDS_1/D2 ; - wire [4:1]\TMDS_1/i_Enc/Cnt_reg_n_0_ ; - wire \TMDS_1/i_Enc/p_0_in ; - wire \TMDS_1/i_Enc/p_10_in ; - wire \TMDS_1/i_Enc/p_12_in ; - wire \TMDS_1/i_Enc/p_2_in ; - wire \TMDS_1/i_Enc/p_4_in ; - wire \TMDS_1/i_Enc/p_6_in ; - wire \TMDS_1/i_Enc/p_8_in ; - wire [0:0]\TMDS_1/i_Enc/qD_reg_n_0_ ; - wire [2:0]\TMDS_1/i_GBox/cntMod5_reg_n_0_ ; - wire [9:2]\TMDS_1/i_GBox/sReg_reg_n_0_ ; - wire \TMDS_2/D1 ; - wire \TMDS_2/D2 ; - wire [4:1]\TMDS_2/i_Enc/Cnt_reg_n_0_ ; - wire \TMDS_2/i_Enc/p_0_in ; - wire \TMDS_2/i_Enc/p_10_in ; - wire \TMDS_2/i_Enc/p_12_in ; - wire \TMDS_2/i_Enc/p_2_in ; - wire \TMDS_2/i_Enc/p_4_in ; - wire \TMDS_2/i_Enc/p_6_in ; - wire \TMDS_2/i_Enc/p_8_in ; - wire \TMDS_2/i_Enc/p_9_in ; - wire [0:0]\TMDS_2/i_Enc/qD_reg_n_0_ ; - wire [2:0]\TMDS_2/i_GBox/cntMod5_reg_n_0_ ; - wire [9:2]\TMDS_2/i_GBox/sReg_reg_n_0_ ; - wire \TMDS_3/D1 ; - wire \TMDS_3/D2 ; - wire \TMDS_3/Reset ; - wire [2:0]\TMDS_3/i_GBox/cntMod5_reg_n_0_ ; - wire [3:3]\TMDS_3/i_GBox/sReg_reg_n_0_ ; - wire VSync; - wire \cntMod5[0]_i_1__0_n_0 ; - wire \cntMod5[0]_i_1__1_n_0 ; - wire \cntMod5[0]_i_1__2_n_0 ; - wire \cntMod5[1]_i_1__0_n_0 ; - wire \cntMod5[1]_i_1__1_n_0 ; - wire \cntMod5[1]_i_1__2_n_0 ; - wire \cntMod5[2]_i_1__0_n_0 ; - wire \cntMod5[2]_i_1__1_n_0 ; - wire \cntMod5[2]_i_1__2_n_0 ; - wire \cntMod5[2]_i_1_n_0 ; - wire \cntMod5[2]_i_2__0_n_0 ; - wire \cntMod5[2]_i_2__1_n_0 ; - wire \cntMod5[2]_i_2__2_n_0 ; - wire g0_b0__0_n_0; - wire g0_b0__1_n_0; - wire g0_b0__2_n_0; - wire g0_b0__3_n_0; - wire g0_b0__4_n_0; - wire g0_b0_n_0; - wire g0_b1__0_n_0; - wire g0_b1__1_n_0; - wire g0_b1__2_n_0; - wire g0_b1__3_n_0; - wire g0_b1__4_n_0; - wire g0_b1_n_0; - wire g0_b2__0_n_0; - wire g0_b2__1_n_0; - wire g0_b2__2_n_0; - wire g0_b2__3_n_0; - wire g0_b2__4_n_0; - wire g0_b2_i_1__0_n_0; - wire g0_b2_i_1__1_n_0; - wire g0_b2_i_1_n_0; - wire g0_b2_i_2__0_n_0; - wire g0_b2_i_2__1_n_0; - wire g0_b2_i_3__0_n_0; - wire g0_b2_i_3__1_n_0; - wire g0_b2_i_3_n_0; - wire g0_b2_i_4__0_n_0; - wire g0_b2_i_4__1_n_0; - wire g0_b2_i_4_n_0; - wire g0_b2_n_0; - wire i_ODDRE_N_i_1__0_n_0; - wire i_ODDRE_N_i_1__1_n_0; - wire i_ODDRE_N_i_1__2_n_0; - wire i_ODDRE_N_i_1_n_0; - wire i_ODDRE_N_i_2__0_n_0; - wire i_ODDRE_N_i_2__1_n_0; - wire i_ODDRE_N_i_2__2_n_0; - wire i_ODDRE_N_i_2_n_0; - wire [2:0]plusOp; - wire pxClk; - wire pxClkX5; - wire [1:0]qC1C0; - wire qDE; - wire \sReg[0]_i_1__0_n_0 ; - wire \sReg[0]_i_1__1_n_0 ; - wire \sReg[0]_i_1__2_n_0 ; - wire \sReg[0]_i_1_n_0 ; - wire \sReg[1]_i_1__0_n_0 ; - wire \sReg[1]_i_1__1_n_0 ; - wire \sReg[1]_i_1__2_n_0 ; - wire \sReg[1]_i_1_n_0 ; - wire \sReg[1]_i_2__0_n_0 ; - wire \sReg[1]_i_2__1_n_0 ; - wire \sReg[1]_i_2_n_0 ; - wire \sReg[1]_i_3_n_0 ; - wire \sReg[1]_i_4_n_0 ; - wire \sReg[1]_i_5_n_0 ; - wire \sReg[2]_i_1__0_n_0 ; - wire \sReg[2]_i_1__1_n_0 ; - wire \sReg[2]_i_1_n_0 ; - wire \sReg[2]_i_2__0_n_0 ; - wire \sReg[2]_i_2__1_n_0 ; - wire \sReg[2]_i_2_n_0 ; - wire \sReg[3]_i_1__0_n_0 ; - wire \sReg[3]_i_1__1_n_0 ; - wire \sReg[3]_i_1__2_n_0 ; - wire \sReg[3]_i_1_n_0 ; - wire \sReg[3]_i_2__0_n_0 ; - wire \sReg[3]_i_2__1_n_0 ; - wire \sReg[3]_i_2_n_0 ; - wire \sReg[3]_i_3_n_0 ; - wire \sReg[3]_i_4_n_0 ; - wire \sReg[4]_i_1__0_n_0 ; - wire \sReg[4]_i_1__1_n_0 ; - wire \sReg[4]_i_1_n_0 ; - wire \sReg[5]_i_1__0_n_0 ; - wire \sReg[5]_i_1__1_n_0 ; - wire \sReg[5]_i_1_n_0 ; - wire \sReg[5]_i_2__0_n_0 ; - wire \sReg[5]_i_2__1_n_0 ; - wire \sReg[5]_i_2_n_0 ; - wire \sReg[5]_i_3_n_0 ; - wire \sReg[5]_i_4_n_0 ; - wire \sReg[5]_i_5_n_0 ; - wire \sReg[6]_i_1__0_n_0 ; - wire \sReg[6]_i_1__1_n_0 ; - wire \sReg[6]_i_1_n_0 ; - wire \sReg[6]_i_2__0_n_0 ; - wire \sReg[6]_i_2__1_n_0 ; - wire \sReg[6]_i_2_n_0 ; - wire \sReg[7]_i_1__0_n_0 ; - wire \sReg[7]_i_1__1_n_0 ; - wire \sReg[7]_i_1_n_0 ; - wire \sReg[7]_i_2__0_n_0 ; - wire \sReg[7]_i_2__1_n_0 ; - wire \sReg[7]_i_2_n_0 ; - wire \sReg[7]_i_3__0_n_0 ; - wire \sReg[7]_i_3_n_0 ; - wire \sReg[7]_i_4_n_0 ; - wire \sReg[8]_i_1__0_n_0 ; - wire \sReg[8]_i_1__1_n_0 ; - wire \sReg[8]_i_1_n_0 ; - wire \sReg[9]_i_1__0_n_0 ; - wire \sReg[9]_i_1__1_n_0 ; - wire \sReg[9]_i_1_n_0 ; - wire \sReg[9]_i_2__0_n_0 ; - wire \sReg[9]_i_2__1_n_0 ; - wire \sReg[9]_i_2_n_0 ; - wire \sReg[9]_i_3_n_0 ; - wire \sReg[9]_i_4_n_0 ; - wire \NLW_TMDS_0/i_ODDRE_N_CLKDIV_UNCONNECTED ; - wire \NLW_TMDS_0/i_ODDRE_N_T_OUT_UNCONNECTED ; - wire [7:1]\NLW_TMDS_0/i_ODDRE_N_D_UNCONNECTED ; - wire \NLW_TMDS_0/i_ODDRE_P_CLKDIV_UNCONNECTED ; - wire \NLW_TMDS_0/i_ODDRE_P_T_OUT_UNCONNECTED ; - wire [7:1]\NLW_TMDS_0/i_ODDRE_P_D_UNCONNECTED ; - wire \NLW_TMDS_1/i_ODDRE_N_CLKDIV_UNCONNECTED ; - wire \NLW_TMDS_1/i_ODDRE_N_T_OUT_UNCONNECTED ; - wire [7:1]\NLW_TMDS_1/i_ODDRE_N_D_UNCONNECTED ; - wire \NLW_TMDS_1/i_ODDRE_P_CLKDIV_UNCONNECTED ; - wire \NLW_TMDS_1/i_ODDRE_P_T_OUT_UNCONNECTED ; - wire [7:1]\NLW_TMDS_1/i_ODDRE_P_D_UNCONNECTED ; - wire \NLW_TMDS_2/i_ODDRE_N_CLKDIV_UNCONNECTED ; - wire \NLW_TMDS_2/i_ODDRE_N_T_OUT_UNCONNECTED ; - wire [7:1]\NLW_TMDS_2/i_ODDRE_N_D_UNCONNECTED ; - wire \NLW_TMDS_2/i_ODDRE_P_CLKDIV_UNCONNECTED ; - wire \NLW_TMDS_2/i_ODDRE_P_T_OUT_UNCONNECTED ; - wire [7:1]\NLW_TMDS_2/i_ODDRE_P_D_UNCONNECTED ; - wire \NLW_TMDS_3/i_ODDRE_N_CLKDIV_UNCONNECTED ; - wire \NLW_TMDS_3/i_ODDRE_N_T_OUT_UNCONNECTED ; - wire [7:1]\NLW_TMDS_3/i_ODDRE_N_D_UNCONNECTED ; - wire \NLW_TMDS_3/i_ODDRE_P_CLKDIV_UNCONNECTED ; - wire \NLW_TMDS_3/i_ODDRE_P_T_OUT_UNCONNECTED ; - wire [7:1]\NLW_TMDS_3/i_ODDRE_P_D_UNCONNECTED ; - - LUT5 #( - .INIT(32'h906F6F90)) - \Cnt[1]_i_1 - (.I0(g0_b2_i_1_n_0), - .I1(\Cnt[4]_i_4_n_0 ), - .I2(\Cnt[4]_i_6_n_0 ), - .I3(\TMDS_0/i_Enc/Cnt_reg_n_0_ [1]), - .I4(\Cnt[2]_i_4_n_0 ), - .O(\Cnt[1]_i_1_n_0 )); - LUT5 #( - .INIT(32'h609F9F60)) - \Cnt[1]_i_1__0 - (.I0(g0_b2_i_1__0_n_0), - .I1(\Cnt[4]_i_3__0_n_0 ), - .I2(\Cnt[4]_i_5__0_n_0 ), - .I3(\TMDS_1/i_Enc/Cnt_reg_n_0_ [1]), - .I4(\Cnt[1]_i_2__0_n_0 ), - .O(\Cnt[1]_i_1__0_n_0 )); - LUT5 #( - .INIT(32'h9F60609F)) - \Cnt[1]_i_1__1 - (.I0(g0_b2_i_1__1_n_0), - .I1(\Cnt[4]_i_4__1_n_0 ), - .I2(\Cnt[4]_i_6__0_n_0 ), - .I3(\TMDS_2/i_Enc/Cnt_reg_n_0_ [1]), - .I4(\Cnt[1]_i_2_n_0 ), - .O(\Cnt[1]_i_1__1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair32" *) - LUT4 #( - .INIT(16'h9669)) - \Cnt[1]_i_2 - (.I0(g0_b0__4_n_0), - .I1(\TMDS_2/i_Enc/p_8_in ), - .I2(\TMDS_2/i_Enc/p_9_in ), - .I3(\TMDS_2/i_Enc/p_12_in ), - .O(\Cnt[1]_i_2_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair33" *) - LUT4 #( - .INIT(16'h6996)) - \Cnt[1]_i_2__0 - (.I0(g0_b0__3_n_0), - .I1(g0_b2_i_2__1_n_0), - .I2(\TMDS_1/i_Enc/p_8_in ), - .I3(\TMDS_1/i_Enc/p_12_in ), - .O(\Cnt[1]_i_2__0_n_0 )); - LUT6 #( - .INIT(64'h8B8BB88BB88B8B8B)) - \Cnt[2]_i_1 - (.I0(\Cnt[2]_i_2_n_0 ), - .I1(\Cnt[4]_i_6_n_0 ), - .I2(\Cnt[2]_i_3_n_0 ), - .I3(\Cnt[2]_i_4_n_0 ), - .I4(\Cnt[2]_i_5_n_0 ), - .I5(\TMDS_0/i_Enc/Cnt_reg_n_0_ [1]), - .O(\Cnt[2]_i_1_n_0 )); - LUT6 #( - .INIT(64'h639C39C6936C36C9)) - \Cnt[2]_i_2 - (.I0(\Cnt[4]_i_4_n_0 ), - .I1(\TMDS_0/i_Enc/Cnt_reg_n_0_ [2]), - .I2(\TMDS_0/i_Enc/Cnt_reg_n_0_ [1]), - .I3(\Cnt[3]_i_8_n_0 ), - .I4(g0_b2_i_1_n_0), - .I5(\Cnt[2]_i_4_n_0 ), - .O(\Cnt[2]_i_2_n_0 )); - LUT5 #( - .INIT(32'hA6596A95)) - \Cnt[2]_i_2__0 - (.I0(\TMDS_1/i_Enc/Cnt_reg_n_0_ [2]), - .I1(\Cnt[1]_i_2__0_n_0 ), - .I2(g0_b2_i_1__0_n_0), - .I3(\Cnt[4]_i_12__0_n_0 ), - .I4(\TMDS_1/i_Enc/Cnt_reg_n_0_ [1]), - .O(\Cnt[2]_i_2__0_n_0 )); - LUT5 #( - .INIT(32'hA9569A65)) - \Cnt[2]_i_2__1 - (.I0(\TMDS_2/i_Enc/Cnt_reg_n_0_ [2]), - .I1(\Cnt[1]_i_2_n_0 ), - .I2(g0_b2_i_1__1_n_0), - .I3(\Cnt[4]_i_9__1_n_0 ), - .I4(\TMDS_2/i_Enc/Cnt_reg_n_0_ [1]), - .O(\Cnt[2]_i_2__1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair34" *) - LUT2 #( - .INIT(4'h6)) - \Cnt[2]_i_3 - (.I0(\TMDS_0/i_Enc/Cnt_reg_n_0_ [2]), - .I1(\Cnt[4]_i_10__1_n_0 ), - .O(\Cnt[2]_i_3_n_0 )); - LUT6 #( - .INIT(64'hF0960F6969F0960F)) - \Cnt[2]_i_3__0 - (.I0(\Cnt[4]_i_3__0_n_0 ), - .I1(\Cnt[1]_i_2__0_n_0 ), - .I2(\TMDS_1/i_Enc/Cnt_reg_n_0_ [2]), - .I3(g0_b2_i_1__0_n_0), - .I4(\Cnt[4]_i_12__0_n_0 ), - .I5(\TMDS_1/i_Enc/Cnt_reg_n_0_ [1]), - .O(\Cnt[2]_i_3__0_n_0 )); - LUT6 #( - .INIT(64'hC9366C93C6399C63)) - \Cnt[2]_i_3__1 - (.I0(\Cnt[4]_i_4__1_n_0 ), - .I1(\TMDS_2/i_Enc/Cnt_reg_n_0_ [2]), - .I2(\TMDS_2/i_Enc/Cnt_reg_n_0_ [1]), - .I3(\Cnt[4]_i_9__1_n_0 ), - .I4(g0_b2_i_1__1_n_0), - .I5(\Cnt[1]_i_2_n_0 ), - .O(\Cnt[2]_i_3__1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair41" *) - LUT4 #( - .INIT(16'h6996)) - \Cnt[2]_i_4 - (.I0(g0_b0__2_n_0), - .I1(\TMDS_0/i_Enc/p_8_in ), - .I2(g0_b2_i_2__0_n_0), - .I3(\TMDS_0/i_Enc/p_12_in ), - .O(\Cnt[2]_i_4_n_0 )); - LUT6 #( - .INIT(64'hAA69995A995A5596)) - \Cnt[2]_i_5 - (.I0(g0_b1__2_n_0), - .I1(\TMDS_0/i_Enc/p_12_in ), - .I2(\sReg[5]_i_4_n_0 ), - .I3(g0_b0__2_n_0), - .I4(\TMDS_0/i_Enc/p_10_in ), - .I5(g0_b2_i_1_n_0), - .O(\Cnt[2]_i_5_n_0 )); - LUT5 #( - .INIT(32'hB88B8BB8)) - \Cnt[3]_i_1 - (.I0(\Cnt[3]_i_2_n_0 ), - .I1(\Cnt[4]_i_6_n_0 ), - .I2(\Cnt[3]_i_3_n_0 ), - .I3(\Cnt[3]_i_4_n_0 ), - .I4(\Cnt[3]_i_5_n_0 ), - .O(\Cnt[3]_i_1_n_0 )); - LUT6 #( - .INIT(64'h6F60FFFF6F600000)) - \Cnt[3]_i_1__0 - (.I0(\Cnt[3]_i_2__0_n_0 ), - .I1(\Cnt[3]_i_3__0_n_0 ), - .I2(\Cnt[4]_i_3__0_n_0 ), - .I3(\Cnt[3]_i_4__1_n_0 ), - .I4(\Cnt[4]_i_5__0_n_0 ), - .I5(\Cnt[3]_i_5__1_n_0 ), - .O(\Cnt[3]_i_1__0_n_0 )); - LUT6 #( - .INIT(64'h6F60606F606F6F60)) - \Cnt[3]_i_2 - (.I0(\Cnt[3]_i_6_n_0 ), - .I1(\Cnt[4]_i_9_n_0 ), - .I2(\Cnt[4]_i_4_n_0 ), - .I3(\Cnt[4]_i_15_n_0 ), - .I4(\Cnt[3]_i_7_n_0 ), - .I5(\Cnt[4]_i_14_n_0 ), - .O(\Cnt[3]_i_2_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair20" *) - LUT5 #( - .INIT(32'h60666690)) - \Cnt[3]_i_2__0 - (.I0(\Cnt[4]_i_12__0_n_0 ), - .I1(\TMDS_1/i_Enc/Cnt_reg_n_0_ [2]), - .I2(\TMDS_1/i_Enc/Cnt_reg_n_0_ [1]), - .I3(g0_b2_i_1__0_n_0), - .I4(\Cnt[1]_i_2__0_n_0 ), - .O(\Cnt[3]_i_2__0_n_0 )); - LUT6 #( - .INIT(64'h9969669666699996)) - \Cnt[3]_i_2__1 - (.I0(\TMDS_2/i_Enc/Cnt_reg_n_0_ [3]), - .I1(\Cnt[4]_i_17__0_n_0 ), - .I2(g0_b2_i_1__1_n_0), - .I3(\Cnt[4]_i_11__1_n_0 ), - .I4(\Cnt[4]_i_14__1_n_0 ), - .I5(\TMDS_2/i_Enc/Cnt_reg_n_0_ [2]), - .O(\Cnt[3]_i_2__1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair25" *) - LUT5 #( - .INIT(32'hFAD28705)) - \Cnt[3]_i_3 - (.I0(\Cnt[2]_i_4_n_0 ), - .I1(g0_b2_i_1_n_0), - .I2(\Cnt[3]_i_8_n_0 ), - .I3(\TMDS_0/i_Enc/Cnt_reg_n_0_ [1]), - .I4(\TMDS_0/i_Enc/Cnt_reg_n_0_ [2]), - .O(\Cnt[3]_i_3_n_0 )); - LUT6 #( - .INIT(64'h9696666696996696)) - \Cnt[3]_i_3__0 - (.I0(\Cnt[4]_i_21_n_0 ), - .I1(\TMDS_1/i_Enc/Cnt_reg_n_0_ [3]), - .I2(\TMDS_1/i_Enc/Cnt_reg_n_0_ [2]), - .I3(\Cnt[1]_i_2__0_n_0 ), - .I4(\Cnt[4]_i_12__0_n_0 ), - .I5(g0_b2_i_1__0_n_0), - .O(\Cnt[3]_i_3__0_n_0 )); - LUT6 #( - .INIT(64'h6F60606F606F6F60)) - \Cnt[3]_i_3__1 - (.I0(\Cnt[3]_i_4__0_n_0 ), - .I1(\Cnt[3]_i_5__0_n_0 ), - .I2(\Cnt[4]_i_4__1_n_0 ), - .I3(\Cnt[4]_i_13__1_n_0 ), - .I4(\Cnt[3]_i_6__0_n_0 ), - .I5(\Cnt[4]_i_12__1_n_0 ), - .O(\Cnt[3]_i_3__1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair27" *) - LUT5 #( - .INIT(32'h74474774)) - \Cnt[3]_i_4 - (.I0(\TMDS_0/i_Enc/Cnt_reg_n_0_ [2]), - .I1(\Cnt[4]_i_10__1_n_0 ), - .I2(g0_b2_i_1_n_0), - .I3(\Cnt[4]_i_13_n_0 ), - .I4(g0_b2__2_n_0), - .O(\Cnt[3]_i_4_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair26" *) - LUT5 #( - .INIT(32'h66906066)) - \Cnt[3]_i_4__0 - (.I0(\Cnt[4]_i_9__1_n_0 ), - .I1(\TMDS_2/i_Enc/Cnt_reg_n_0_ [2]), - .I2(\TMDS_2/i_Enc/Cnt_reg_n_0_ [1]), - .I3(g0_b2_i_1__1_n_0), - .I4(\Cnt[1]_i_2_n_0 ), - .O(\Cnt[3]_i_4__0_n_0 )); - LUT4 #( - .INIT(16'h9669)) - \Cnt[3]_i_4__1 - (.I0(\Cnt[4]_i_14__0_n_0 ), - .I1(\TMDS_1/i_Enc/Cnt_reg_n_0_ [3]), - .I2(\Cnt[4]_i_21_n_0 ), - .I3(\Cnt[4]_i_15__0_n_0 ), - .O(\Cnt[3]_i_4__1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair21" *) - LUT4 #( - .INIT(16'h69AA)) - \Cnt[3]_i_5 - (.I0(\TMDS_0/i_Enc/Cnt_reg_n_0_ [3]), - .I1(g0_b2__2_n_0), - .I2(\Cnt[4]_i_13_n_0 ), - .I3(\Cnt[4]_i_10__1_n_0 ), - .O(\Cnt[3]_i_5_n_0 )); - LUT6 #( - .INIT(64'h9696666699969666)) - \Cnt[3]_i_5__0 - (.I0(\Cnt[4]_i_14__1_n_0 ), - .I1(\TMDS_2/i_Enc/Cnt_reg_n_0_ [3]), - .I2(\TMDS_2/i_Enc/Cnt_reg_n_0_ [2]), - .I3(\Cnt[1]_i_2_n_0 ), - .I4(\Cnt[4]_i_9__1_n_0 ), - .I5(g0_b2_i_1__1_n_0), - .O(\Cnt[3]_i_5__0_n_0 )); - LUT6 #( - .INIT(64'h59A6A956A65956A9)) - \Cnt[3]_i_5__1 - (.I0(\TMDS_1/i_Enc/Cnt_reg_n_0_ [3]), - .I1(g0_b2_i_1__0_n_0), - .I2(\Cnt[4]_i_19_n_0 ), - .I3(\Cnt[4]_i_21_n_0 ), - .I4(\TMDS_1/i_Enc/Cnt_reg_n_0_ [2]), - .I5(\Cnt[4]_i_20_n_0 ), - .O(\Cnt[3]_i_5__1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair21" *) - LUT5 #( - .INIT(32'h956A6A95)) - \Cnt[3]_i_6 - (.I0(\TMDS_0/i_Enc/Cnt_reg_n_0_ [3]), - .I1(\TMDS_0/i_Enc/Cnt_reg_n_0_ [2]), - .I2(\Cnt[4]_i_10__1_n_0 ), - .I3(\Cnt[4]_i_13_n_0 ), - .I4(g0_b2__2_n_0), - .O(\Cnt[3]_i_6_n_0 )); - LUT3 #( - .INIT(8'h96)) - \Cnt[3]_i_6__0 - (.I0(\TMDS_2/i_Enc/Cnt_reg_n_0_ [3]), - .I1(\Cnt[4]_i_10__0_n_0 ), - .I2(g0_b2__4_n_0), - .O(\Cnt[3]_i_6__0_n_0 )); - LUT3 #( - .INIT(8'h69)) - \Cnt[3]_i_7 - (.I0(\TMDS_0/i_Enc/Cnt_reg_n_0_ [3]), - .I1(\Cnt[4]_i_13_n_0 ), - .I2(g0_b2__2_n_0), - .O(\Cnt[3]_i_7_n_0 )); - LUT6 #( - .INIT(64'h4B44222DB4BBDDD2)) - \Cnt[3]_i_8 - (.I0(g0_b2_i_1_n_0), - .I1(\TMDS_0/i_Enc/p_10_in ), - .I2(g0_b0__2_n_0), - .I3(\sReg[5]_i_4_n_0 ), - .I4(\TMDS_0/i_Enc/p_12_in ), - .I5(g0_b1__2_n_0), - .O(\Cnt[3]_i_8_n_0 )); - LUT2 #( - .INIT(4'h7)) - \Cnt[4]_i_1 - (.I0(qDE), - .I1(ResetN), - .O(\Cnt[4]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair1" *) - LUT4 #( - .INIT(16'h4004)) - \Cnt[4]_i_10 - (.I0(\Cnt[1]_i_2__0_n_0 ), - .I1(\Cnt[4]_i_12__0_n_0 ), - .I2(\Cnt[4]_i_13__0_n_0 ), - .I3(g0_b2__3_n_0), - .O(\Cnt[4]_i_10_n_0 )); - LUT6 #( - .INIT(64'hE2A0AA28AA288B0A)) - \Cnt[4]_i_10__0 - (.I0(g0_b1__4_n_0), - .I1(\TMDS_2/i_Enc/p_12_in ), - .I2(\sReg[6]_i_2__1_n_0 ), - .I3(g0_b0__4_n_0), - .I4(\TMDS_2/i_Enc/p_10_in ), - .I5(g0_b2_i_1__1_n_0), - .O(\Cnt[4]_i_10__0_n_0 )); - LUT6 #( - .INIT(64'h8228811842248228)) - \Cnt[4]_i_10__1 - (.I0(g0_b1__2_n_0), - .I1(\TMDS_0/i_Enc/p_12_in ), - .I2(\sReg[5]_i_4_n_0 ), - .I3(g0_b0__2_n_0), - .I4(\TMDS_0/i_Enc/p_10_in ), - .I5(g0_b2_i_1_n_0), - .O(\Cnt[4]_i_10__1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair28" *) - LUT2 #( - .INIT(4'h6)) - \Cnt[4]_i_11 - (.I0(g0_b2__2_n_0), - .I1(\Cnt[4]_i_13_n_0 ), - .O(\Cnt[4]_i_11_n_0 )); - LUT2 #( - .INIT(4'h7)) - \Cnt[4]_i_11__0 - (.I0(g0_b2__3_n_0), - .I1(\Cnt[4]_i_13__0_n_0 ), - .O(\Cnt[4]_i_11__0_n_0 )); - LUT6 #( - .INIT(64'h6A0000A900A96A00)) - \Cnt[4]_i_11__1 - (.I0(g0_b1__4_n_0), - .I1(\TMDS_2/i_Enc/p_10_in ), - .I2(g0_b2_i_1__1_n_0), - .I3(\TMDS_2/i_Enc/p_12_in ), - .I4(\sReg[6]_i_2__1_n_0 ), - .I5(g0_b0__4_n_0), - .O(\Cnt[4]_i_11__1_n_0 )); - LUT6 #( - .INIT(64'h65595665A6655665)) - \Cnt[4]_i_12 - (.I0(\TMDS_0/i_Enc/Cnt_reg_n_0_ [4]), - .I1(\TMDS_0/i_Enc/Cnt_reg_n_0_ [3]), - .I2(g0_b2__2_n_0), - .I3(\Cnt[4]_i_13_n_0 ), - .I4(\Cnt[4]_i_10__1_n_0 ), - .I5(\TMDS_0/i_Enc/Cnt_reg_n_0_ [2]), - .O(\Cnt[4]_i_12_n_0 )); - LUT6 #( - .INIT(64'h5F6CC9FAA0933605)) - \Cnt[4]_i_12__0 - (.I0(g0_b2_i_1__0_n_0), - .I1(g0_b0__3_n_0), - .I2(\TMDS_1/i_Enc/p_10_in ), - .I3(\sReg[6]_i_2_n_0 ), - .I4(\TMDS_1/i_Enc/p_12_in ), - .I5(g0_b1__3_n_0), - .O(\Cnt[4]_i_12__0_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair26" *) - LUT4 #( - .INIT(16'hD040)) - \Cnt[4]_i_12__1 - (.I0(\TMDS_2/i_Enc/Cnt_reg_n_0_ [2]), - .I1(\Cnt[1]_i_2_n_0 ), - .I2(\Cnt[4]_i_9__1_n_0 ), - .I3(g0_b2_i_1__1_n_0), - .O(\Cnt[4]_i_12__1_n_0 )); - LUT6 #( - .INIT(64'hEFF708102BD40000)) - \Cnt[4]_i_13 - (.I0(\TMDS_0/i_Enc/p_10_in ), - .I1(\TMDS_0/i_Enc/p_12_in ), - .I2(g0_b2_i_1_n_0), - .I3(\sReg[5]_i_4_n_0 ), - .I4(g0_b1__2_n_0), - .I5(g0_b0__2_n_0), - .O(\Cnt[4]_i_13_n_0 )); - LUT6 #( - .INIT(64'h2EAA0A82AAB882A0)) - \Cnt[4]_i_13__0 - (.I0(g0_b1__3_n_0), - .I1(\TMDS_1/i_Enc/p_12_in ), - .I2(\sReg[6]_i_2_n_0 ), - .I3(\TMDS_1/i_Enc/p_10_in ), - .I4(g0_b0__3_n_0), - .I5(g0_b2_i_1__0_n_0), - .O(\Cnt[4]_i_13__0_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair24" *) - LUT5 #( - .INIT(32'h49326DB3)) - \Cnt[4]_i_13__1 - (.I0(\Cnt[1]_i_2_n_0 ), - .I1(\TMDS_2/i_Enc/Cnt_reg_n_0_ [2]), - .I2(g0_b2_i_1__1_n_0), - .I3(\Cnt[4]_i_9__1_n_0 ), - .I4(\TMDS_2/i_Enc/Cnt_reg_n_0_ [1]), - .O(\Cnt[4]_i_13__1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair25" *) - LUT4 #( - .INIT(16'h0107)) - \Cnt[4]_i_14 - (.I0(g0_b2_i_1_n_0), - .I1(\Cnt[2]_i_4_n_0 ), - .I2(\Cnt[3]_i_8_n_0 ), - .I3(\TMDS_0/i_Enc/Cnt_reg_n_0_ [2]), - .O(\Cnt[4]_i_14_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair20" *) - LUT5 #( - .INIT(32'h86319E73)) - \Cnt[4]_i_14__0 - (.I0(\Cnt[1]_i_2__0_n_0 ), - .I1(\TMDS_1/i_Enc/Cnt_reg_n_0_ [2]), - .I2(g0_b2_i_1__0_n_0), - .I3(\Cnt[4]_i_12__0_n_0 ), - .I4(\TMDS_1/i_Enc/Cnt_reg_n_0_ [1]), - .O(\Cnt[4]_i_14__0_n_0 )); - LUT6 #( - .INIT(64'h5555A959A959AAAA)) - \Cnt[4]_i_14__1 - (.I0(g0_b2__4_n_0), - .I1(\Cnt[4]_i_20__0_n_0 ), - .I2(\Cnt[4]_i_21__0_n_0 ), - .I3(\Cnt[4]_i_22_n_0 ), - .I4(\Cnt[4]_i_23_n_0 ), - .I5(g0_b1__4_n_0), - .O(\Cnt[4]_i_14__1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair23" *) - LUT5 #( - .INIT(32'hE8A5A58E)) - \Cnt[4]_i_15 - (.I0(\TMDS_0/i_Enc/Cnt_reg_n_0_ [2]), - .I1(\TMDS_0/i_Enc/Cnt_reg_n_0_ [1]), - .I2(\Cnt[3]_i_8_n_0 ), - .I3(g0_b2_i_1_n_0), - .I4(\Cnt[2]_i_4_n_0 ), - .O(\Cnt[4]_i_15_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair40" *) - LUT4 #( - .INIT(16'h8FEF)) - \Cnt[4]_i_15__0 - (.I0(\TMDS_1/i_Enc/Cnt_reg_n_0_ [2]), - .I1(\Cnt[1]_i_2__0_n_0 ), - .I2(\Cnt[4]_i_12__0_n_0 ), - .I3(g0_b2_i_1__0_n_0), - .O(\Cnt[4]_i_15__0_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair22" *) - LUT3 #( - .INIT(8'h7F)) - \Cnt[4]_i_15__1 - (.I0(g0_b2__4_n_0), - .I1(\Cnt[4]_i_10__0_n_0 ), - .I2(\Cnt[4]_i_11__1_n_0 ), - .O(\Cnt[4]_i_15__1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair27" *) - LUT3 #( - .INIT(8'h7F)) - \Cnt[4]_i_16 - (.I0(g0_b2__2_n_0), - .I1(\Cnt[4]_i_13_n_0 ), - .I2(\Cnt[4]_i_10__1_n_0 ), - .O(\Cnt[4]_i_16_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair22" *) - LUT5 #( - .INIT(32'h553C55C3)) - \Cnt[4]_i_16__0 - (.I0(\TMDS_2/i_Enc/Cnt_reg_n_0_ [2]), - .I1(g0_b2__4_n_0), - .I2(\Cnt[4]_i_10__0_n_0 ), - .I3(\Cnt[4]_i_11__1_n_0 ), - .I4(g0_b2_i_1__1_n_0), - .O(\Cnt[4]_i_16__0_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair19" *) - LUT3 #( - .INIT(8'h69)) - \Cnt[4]_i_16__1 - (.I0(\TMDS_1/i_Enc/Cnt_reg_n_0_ [3]), - .I1(g0_b2__3_n_0), - .I2(\Cnt[4]_i_13__0_n_0 ), - .O(\Cnt[4]_i_16__1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair19" *) - LUT5 #( - .INIT(32'hD00FDFFF)) - \Cnt[4]_i_17 - (.I0(\Cnt[4]_i_12__0_n_0 ), - .I1(\Cnt[1]_i_2__0_n_0 ), - .I2(g0_b2__3_n_0), - .I3(\Cnt[4]_i_13__0_n_0 ), - .I4(\TMDS_1/i_Enc/Cnt_reg_n_0_ [3]), - .O(\Cnt[4]_i_17_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair24" *) - LUT5 #( - .INIT(32'hA0B41E5F)) - \Cnt[4]_i_17__0 - (.I0(\Cnt[1]_i_2_n_0 ), - .I1(g0_b2_i_1__1_n_0), - .I2(\Cnt[4]_i_9__1_n_0 ), - .I3(\TMDS_2/i_Enc/Cnt_reg_n_0_ [1]), - .I4(\TMDS_2/i_Enc/Cnt_reg_n_0_ [2]), - .O(\Cnt[4]_i_17__0_n_0 )); - LUT4 #( - .INIT(16'h0001)) - \Cnt[4]_i_18 - (.I0(\TMDS_1/i_Enc/Cnt_reg_n_0_ [2]), - .I1(\TMDS_1/i_Enc/Cnt_reg_n_0_ [1]), - .I2(\TMDS_1/i_Enc/Cnt_reg_n_0_ [3]), - .I3(\TMDS_1/i_Enc/Cnt_reg_n_0_ [4]), - .O(\Cnt[4]_i_18_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair29" *) - LUT3 #( - .INIT(8'h6A)) - \Cnt[4]_i_18__0 - (.I0(g0_b2_i_1__1_n_0), - .I1(g0_b2__4_n_0), - .I2(\Cnt[4]_i_10__0_n_0 ), - .O(\Cnt[4]_i_18__0_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair40" *) - LUT2 #( - .INIT(4'h2)) - \Cnt[4]_i_19 - (.I0(\Cnt[4]_i_12__0_n_0 ), - .I1(\Cnt[1]_i_2__0_n_0 ), - .O(\Cnt[4]_i_19_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair18" *) - LUT3 #( - .INIT(8'h82)) - \Cnt[4]_i_19__0 - (.I0(\Cnt[4]_i_11__1_n_0 ), - .I1(\Cnt[4]_i_10__0_n_0 ), - .I2(g0_b2__4_n_0), - .O(\Cnt[4]_i_19__0_n_0 )); - LUT6 #( - .INIT(64'hB800B8FFB8FFB800)) - \Cnt[4]_i_1__0 - (.I0(\Cnt[4]_i_2__0_n_0 ), - .I1(\Cnt[4]_i_3__0_n_0 ), - .I2(\Cnt[4]_i_4__0_n_0 ), - .I3(\Cnt[4]_i_5__0_n_0 ), - .I4(\Cnt[4]_i_6__1_n_0 ), - .I5(\Cnt[4]_i_7_n_0 ), - .O(\Cnt[4]_i_1__0_n_0 )); - LUT6 #( - .INIT(64'h6F60FFFF6F600000)) - \Cnt[4]_i_1__1 - (.I0(\Cnt[4]_i_2__1_n_0 ), - .I1(\Cnt[4]_i_3__1_n_0 ), - .I2(\Cnt[4]_i_4__1_n_0 ), - .I3(\Cnt[4]_i_5__1_n_0 ), - .I4(\Cnt[4]_i_6__0_n_0 ), - .I5(\Cnt[4]_i_7__0_n_0 ), - .O(\Cnt[4]_i_1__1_n_0 )); - LUT6 #( - .INIT(64'hB800B8FFB8FFB800)) - \Cnt[4]_i_2 - (.I0(\Cnt[4]_i_3_n_0 ), - .I1(\Cnt[4]_i_4_n_0 ), - .I2(\Cnt[4]_i_5_n_0 ), - .I3(\Cnt[4]_i_6_n_0 ), - .I4(\Cnt[4]_i_7__1_n_0 ), - .I5(\Cnt[4]_i_8_n_0 ), - .O(\Cnt[4]_i_2_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair17" *) - LUT5 #( - .INIT(32'hAF87D250)) - \Cnt[4]_i_20 - (.I0(\Cnt[1]_i_2__0_n_0 ), - .I1(g0_b2_i_1__0_n_0), - .I2(\Cnt[4]_i_12__0_n_0 ), - .I3(\TMDS_1/i_Enc/Cnt_reg_n_0_ [1]), - .I4(\TMDS_1/i_Enc/Cnt_reg_n_0_ [2]), - .O(\Cnt[4]_i_20_n_0 )); - LUT6 #( - .INIT(64'h00A230FFFF5DCF00)) - \Cnt[4]_i_20__0 - (.I0(\Cnt[4]_i_24_n_0 ), - .I1(g0_b1__1_n_0), - .I2(g0_b2_i_3__1_n_0), - .I3(g0_b2__1_n_0), - .I4(\Cnt[4]_i_25_n_0 ), - .I5(\sReg[6]_i_2__1_n_0 ), - .O(\Cnt[4]_i_20__0_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair16" *) - LUT2 #( - .INIT(4'h6)) - \Cnt[4]_i_21 - (.I0(g0_b2__3_n_0), - .I1(\Cnt[4]_i_13__0_n_0 ), - .O(\Cnt[4]_i_21_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair44" *) - LUT2 #( - .INIT(4'h6)) - \Cnt[4]_i_21__0 - (.I0(\TMDS_2/i_Enc/p_10_in ), - .I1(\TMDS_2/i_Enc/p_12_in ), - .O(\Cnt[4]_i_21__0_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair44" *) - LUT3 #( - .INIT(8'h69)) - \Cnt[4]_i_22 - (.I0(\TMDS_2/i_Enc/p_10_in ), - .I1(\TMDS_2/i_Enc/p_9_in ), - .I2(\TMDS_2/i_Enc/p_8_in ), - .O(\Cnt[4]_i_22_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair32" *) - LUT4 #( - .INIT(16'h8228)) - \Cnt[4]_i_23 - (.I0(g0_b0__4_n_0), - .I1(\TMDS_2/i_Enc/p_8_in ), - .I2(\TMDS_2/i_Enc/p_9_in ), - .I3(\TMDS_2/i_Enc/p_12_in ), - .O(\Cnt[4]_i_23_n_0 )); - LUT6 #( - .INIT(64'hBFFBFBBFBFFFFFFF)) - \Cnt[4]_i_24 - (.I0(\TMDS_2/i_Enc/qD_reg_n_0_ ), - .I1(g0_b0__1_n_0), - .I2(\TMDS_2/i_Enc/p_8_in ), - .I3(\TMDS_2/i_Enc/p_12_in ), - .I4(\TMDS_2/i_Enc/p_10_in ), - .I5(g0_b1__1_n_0), - .O(\Cnt[4]_i_24_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair12" *) - LUT5 #( - .INIT(32'hFF96FFFF)) - \Cnt[4]_i_25 - (.I0(\TMDS_2/i_Enc/p_10_in ), - .I1(\TMDS_2/i_Enc/p_12_in ), - .I2(\TMDS_2/i_Enc/p_8_in ), - .I3(g0_b0__1_n_0), - .I4(\TMDS_2/i_Enc/qD_reg_n_0_ ), - .O(\Cnt[4]_i_25_n_0 )); - LUT6 #( - .INIT(64'h177EE881E78E1871)) - \Cnt[4]_i_2__0 - (.I0(\Cnt[4]_i_8__0_n_0 ), - .I1(\Cnt[4]_i_9__0_n_0 ), - .I2(\Cnt[4]_i_10_n_0 ), - .I3(\TMDS_1/i_Enc/Cnt_reg_n_0_ [3]), - .I4(\TMDS_1/i_Enc/Cnt_reg_n_0_ [4]), - .I5(\Cnt[4]_i_11__0_n_0 ), - .O(\Cnt[4]_i_2__0_n_0 )); - LUT6 #( - .INIT(64'hD7D755D7577F5757)) - \Cnt[4]_i_2__1 - (.I0(\Cnt[4]_i_8__1_n_0 ), - .I1(\Cnt[4]_i_9__1_n_0 ), - .I2(\TMDS_2/i_Enc/Cnt_reg_n_0_ [2]), - .I3(\TMDS_2/i_Enc/Cnt_reg_n_0_ [1]), - .I4(g0_b2_i_1__1_n_0), - .I5(\Cnt[1]_i_2_n_0 ), - .O(\Cnt[4]_i_2__1_n_0 )); - LUT6 #( - .INIT(64'h41111444BEEEEBBB)) - \Cnt[4]_i_3 - (.I0(\Cnt[4]_i_9_n_0 ), - .I1(\TMDS_0/i_Enc/Cnt_reg_n_0_ [3]), - .I2(\TMDS_0/i_Enc/Cnt_reg_n_0_ [2]), - .I3(\Cnt[4]_i_10__1_n_0 ), - .I4(\Cnt[4]_i_11_n_0 ), - .I5(\Cnt[4]_i_12_n_0 ), - .O(\Cnt[4]_i_3_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair1" *) - LUT5 #( - .INIT(32'h000FFBB0)) - \Cnt[4]_i_3__0 - (.I0(\Cnt[1]_i_2__0_n_0 ), - .I1(\Cnt[4]_i_12__0_n_0 ), - .I2(g0_b2__3_n_0), - .I3(\Cnt[4]_i_13__0_n_0 ), - .I4(\TMDS_1/i_Enc/Cnt_reg_n_0_ [4]), - .O(\Cnt[4]_i_3__0_n_0 )); - LUT6 #( - .INIT(64'h5695555595A96969)) - \Cnt[4]_i_3__1 - (.I0(\TMDS_2/i_Enc/Cnt_reg_n_0_ [4]), - .I1(g0_b2__4_n_0), - .I2(\Cnt[4]_i_10__0_n_0 ), - .I3(\TMDS_2/i_Enc/Cnt_reg_n_0_ [2]), - .I4(\Cnt[4]_i_11__1_n_0 ), - .I5(\TMDS_2/i_Enc/Cnt_reg_n_0_ [3]), - .O(\Cnt[4]_i_3__1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair28" *) - LUT4 #( - .INIT(16'h03D4)) - \Cnt[4]_i_4 - (.I0(\Cnt[4]_i_10__1_n_0 ), - .I1(g0_b2__2_n_0), - .I2(\Cnt[4]_i_13_n_0 ), - .I3(\TMDS_0/i_Enc/Cnt_reg_n_0_ [4]), - .O(\Cnt[4]_i_4_n_0 )); - LUT5 #( - .INIT(32'h4DB2B24D)) - \Cnt[4]_i_4__0 - (.I0(\Cnt[4]_i_14__0_n_0 ), - .I1(\Cnt[4]_i_15__0_n_0 ), - .I2(\Cnt[4]_i_16__1_n_0 ), - .I3(\Cnt[4]_i_17_n_0 ), - .I4(\TMDS_1/i_Enc/Cnt_reg_n_0_ [4]), - .O(\Cnt[4]_i_4__0_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair29" *) - LUT4 #( - .INIT(16'h03D4)) - \Cnt[4]_i_4__1 - (.I0(\Cnt[4]_i_11__1_n_0 ), - .I1(g0_b2__4_n_0), - .I2(\Cnt[4]_i_10__0_n_0 ), - .I3(\TMDS_2/i_Enc/Cnt_reg_n_0_ [4]), - .O(\Cnt[4]_i_4__1_n_0 )); - LUT6 #( - .INIT(64'hBBD2D24B442D2DB4)) - \Cnt[4]_i_5 - (.I0(\Cnt[4]_i_14_n_0 ), - .I1(\Cnt[4]_i_15_n_0 ), - .I2(\Cnt[4]_i_16_n_0 ), - .I3(\TMDS_0/i_Enc/Cnt_reg_n_0_ [3]), - .I4(\Cnt[4]_i_11_n_0 ), - .I5(\TMDS_0/i_Enc/Cnt_reg_n_0_ [4]), - .O(\Cnt[4]_i_5_n_0 )); - LUT5 #( - .INIT(32'h0000FDDF)) - \Cnt[4]_i_5__0 - (.I0(\Cnt[4]_i_12__0_n_0 ), - .I1(\Cnt[1]_i_2__0_n_0 ), - .I2(g0_b2__3_n_0), - .I3(\Cnt[4]_i_13__0_n_0 ), - .I4(\Cnt[4]_i_18_n_0 ), - .O(\Cnt[4]_i_5__0_n_0 )); - LUT6 #( - .INIT(64'hE771E88E188E1771)) - \Cnt[4]_i_5__1 - (.I0(\Cnt[4]_i_12__1_n_0 ), - .I1(\Cnt[4]_i_13__1_n_0 ), - .I2(\Cnt[4]_i_14__1_n_0 ), - .I3(\TMDS_2/i_Enc/Cnt_reg_n_0_ [3]), - .I4(\Cnt[4]_i_15__1_n_0 ), - .I5(\TMDS_2/i_Enc/Cnt_reg_n_0_ [4]), - .O(\Cnt[4]_i_5__1_n_0 )); - LUT6 #( - .INIT(64'h7777777777777770)) - \Cnt[4]_i_6 - (.I0(\Cnt[4]_i_10__1_n_0 ), - .I1(\Cnt[4]_i_11_n_0 ), - .I2(\TMDS_0/i_Enc/Cnt_reg_n_0_ [3]), - .I3(\TMDS_0/i_Enc/Cnt_reg_n_0_ [2]), - .I4(\TMDS_0/i_Enc/Cnt_reg_n_0_ [1]), - .I5(\TMDS_0/i_Enc/Cnt_reg_n_0_ [4]), - .O(\Cnt[4]_i_6_n_0 )); - LUT6 #( - .INIT(64'h7777777777777770)) - \Cnt[4]_i_6__0 - (.I0(\Cnt[4]_i_11__1_n_0 ), - .I1(\Cnt[4]_i_14__1_n_0 ), - .I2(\TMDS_2/i_Enc/Cnt_reg_n_0_ [4]), - .I3(\TMDS_2/i_Enc/Cnt_reg_n_0_ [3]), - .I4(\TMDS_2/i_Enc/Cnt_reg_n_0_ [1]), - .I5(\TMDS_2/i_Enc/Cnt_reg_n_0_ [2]), - .O(\Cnt[4]_i_6__0_n_0 )); - LUT6 #( - .INIT(64'h599A9999A9959999)) - \Cnt[4]_i_6__1 - (.I0(\TMDS_1/i_Enc/Cnt_reg_n_0_ [4]), - .I1(\TMDS_1/i_Enc/Cnt_reg_n_0_ [3]), - .I2(g0_b2__3_n_0), - .I3(\Cnt[4]_i_13__0_n_0 ), - .I4(\Cnt[4]_i_19_n_0 ), - .I5(g0_b2_i_1__0_n_0), - .O(\Cnt[4]_i_6__1_n_0 )); - LUT6 #( - .INIT(64'h8E0A8EA0E8AFE8FA)) - \Cnt[4]_i_7 - (.I0(\Cnt[4]_i_20_n_0 ), - .I1(\TMDS_1/i_Enc/Cnt_reg_n_0_ [2]), - .I2(\Cnt[4]_i_21_n_0 ), - .I3(\Cnt[4]_i_19_n_0 ), - .I4(g0_b2_i_1__0_n_0), - .I5(\TMDS_1/i_Enc/Cnt_reg_n_0_ [3]), - .O(\Cnt[4]_i_7_n_0 )); - LUT6 #( - .INIT(64'h87EEE17778111E88)) - \Cnt[4]_i_7__0 - (.I0(\Cnt[4]_i_16__0_n_0 ), - .I1(\Cnt[4]_i_17__0_n_0 ), - .I2(\Cnt[4]_i_18__0_n_0 ), - .I3(\Cnt[4]_i_19__0_n_0 ), - .I4(\TMDS_2/i_Enc/Cnt_reg_n_0_ [3]), - .I5(\TMDS_2/i_Enc/Cnt_reg_n_0_ [4]), - .O(\Cnt[4]_i_7__0_n_0 )); - LUT6 #( - .INIT(64'hA9959999599A9999)) - \Cnt[4]_i_7__1 - (.I0(\TMDS_0/i_Enc/Cnt_reg_n_0_ [4]), - .I1(\TMDS_0/i_Enc/Cnt_reg_n_0_ [3]), - .I2(g0_b2__2_n_0), - .I3(\Cnt[4]_i_13_n_0 ), - .I4(\Cnt[4]_i_10__1_n_0 ), - .I5(g0_b2_i_1_n_0), - .O(\Cnt[4]_i_7__1_n_0 )); - LUT6 #( - .INIT(64'hBB822282EEEB88EB)) - \Cnt[4]_i_8 - (.I0(\Cnt[3]_i_3_n_0 ), - .I1(\Cnt[4]_i_11_n_0 ), - .I2(g0_b2_i_1_n_0), - .I3(\Cnt[4]_i_10__1_n_0 ), - .I4(\TMDS_0/i_Enc/Cnt_reg_n_0_ [2]), - .I5(\TMDS_0/i_Enc/Cnt_reg_n_0_ [3]), - .O(\Cnt[4]_i_8_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair17" *) - LUT5 #( - .INIT(32'hBAF7F710)) - \Cnt[4]_i_8__0 - (.I0(\Cnt[1]_i_2__0_n_0 ), - .I1(g0_b2_i_1__0_n_0), - .I2(\TMDS_1/i_Enc/Cnt_reg_n_0_ [1]), - .I3(\TMDS_1/i_Enc/Cnt_reg_n_0_ [2]), - .I4(\Cnt[4]_i_12__0_n_0 ), - .O(\Cnt[4]_i_8__0_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair18" *) - LUT5 #( - .INIT(32'h6A95956A)) - \Cnt[4]_i_8__1 - (.I0(\TMDS_2/i_Enc/Cnt_reg_n_0_ [3]), - .I1(\Cnt[4]_i_11__1_n_0 ), - .I2(\TMDS_2/i_Enc/Cnt_reg_n_0_ [2]), - .I3(\Cnt[4]_i_10__0_n_0 ), - .I4(g0_b2__4_n_0), - .O(\Cnt[4]_i_8__1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair23" *) - LUT5 #( - .INIT(32'h02BF1502)) - \Cnt[4]_i_9 - (.I0(\Cnt[2]_i_4_n_0 ), - .I1(g0_b2_i_1_n_0), - .I2(\TMDS_0/i_Enc/Cnt_reg_n_0_ [1]), - .I3(\TMDS_0/i_Enc/Cnt_reg_n_0_ [2]), - .I4(\Cnt[3]_i_8_n_0 ), - .O(\Cnt[4]_i_9_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair16" *) - LUT5 #( - .INIT(32'h9999F099)) - \Cnt[4]_i_9__0 - (.I0(g0_b2__3_n_0), - .I1(\Cnt[4]_i_13__0_n_0 ), - .I2(\TMDS_1/i_Enc/Cnt_reg_n_0_ [2]), - .I3(\Cnt[4]_i_12__0_n_0 ), - .I4(\Cnt[1]_i_2__0_n_0 ), - .O(\Cnt[4]_i_9__0_n_0 )); - LUT6 #( - .INIT(64'h7877EEE18788111E)) - \Cnt[4]_i_9__1 - (.I0(g0_b2_i_1__1_n_0), - .I1(\TMDS_2/i_Enc/p_10_in ), - .I2(g0_b0__4_n_0), - .I3(\sReg[6]_i_2__1_n_0 ), - .I4(\TMDS_2/i_Enc/p_12_in ), - .I5(g0_b1__4_n_0), - .O(\Cnt[4]_i_9__1_n_0 )); - MUXF7 \Cnt_reg[2]_i_1 - (.I0(\Cnt[2]_i_2__0_n_0 ), - .I1(\Cnt[2]_i_3__0_n_0 ), - .O(\Cnt_reg[2]_i_1_n_0 ), - .S(\Cnt[4]_i_5__0_n_0 )); - MUXF7 \Cnt_reg[2]_i_1__0 - (.I0(\Cnt[2]_i_2__1_n_0 ), - .I1(\Cnt[2]_i_3__1_n_0 ), - .O(\Cnt_reg[2]_i_1__0_n_0 ), - .S(\Cnt[4]_i_6__0_n_0 )); - MUXF7 \Cnt_reg[3]_i_1 - (.I0(\Cnt[3]_i_2__1_n_0 ), - .I1(\Cnt[3]_i_3__1_n_0 ), - .O(\Cnt_reg[3]_i_1_n_0 ), - .S(\Cnt[4]_i_6__0_n_0 )); - FDRE #( - .INIT(1'b0)) - \TMDS_0/i_Enc/Cnt_reg[1] - (.C(pxClk), - .CE(1'b1), - .D(\Cnt[1]_i_1_n_0 ), - .Q(\TMDS_0/i_Enc/Cnt_reg_n_0_ [1]), - .R(\Cnt[4]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \TMDS_0/i_Enc/Cnt_reg[2] - (.C(pxClk), - .CE(1'b1), - .D(\Cnt[2]_i_1_n_0 ), - .Q(\TMDS_0/i_Enc/Cnt_reg_n_0_ [2]), - .R(\Cnt[4]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \TMDS_0/i_Enc/Cnt_reg[3] - (.C(pxClk), - .CE(1'b1), - .D(\Cnt[3]_i_1_n_0 ), - .Q(\TMDS_0/i_Enc/Cnt_reg_n_0_ [3]), - .R(\Cnt[4]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \TMDS_0/i_Enc/Cnt_reg[4] - (.C(pxClk), - .CE(1'b1), - .D(\Cnt[4]_i_2_n_0 ), - .Q(\TMDS_0/i_Enc/Cnt_reg_n_0_ [4]), - .R(\Cnt[4]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \TMDS_0/i_Enc/qC1C0_reg[0] - (.C(pxClk), - .CE(1'b1), - .D(HSync), - .Q(qC1C0[0]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \TMDS_0/i_Enc/qC1C0_reg[1] - (.C(pxClk), - .CE(1'b1), - .D(VSync), - .Q(qC1C0[1]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \TMDS_0/i_Enc/qDE_reg - (.C(pxClk), - .CE(1'b1), - .D(DE), - .Q(qDE), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \TMDS_0/i_Enc/qD_reg[0] - (.C(pxClk), - .CE(1'b1), - .D(B[0]), - .Q(\TMDS_0/i_Enc/qD_reg_n_0_ ), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \TMDS_0/i_Enc/qD_reg[1] - (.C(pxClk), - .CE(1'b1), - .D(B[1]), - .Q(\TMDS_0/i_Enc/p_0_in ), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \TMDS_0/i_Enc/qD_reg[2] - (.C(pxClk), - .CE(1'b1), - .D(B[2]), - .Q(\TMDS_0/i_Enc/p_2_in ), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \TMDS_0/i_Enc/qD_reg[3] - (.C(pxClk), - .CE(1'b1), - .D(B[3]), - .Q(\TMDS_0/i_Enc/p_4_in ), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \TMDS_0/i_Enc/qD_reg[4] - (.C(pxClk), - .CE(1'b1), - .D(B[4]), - .Q(\TMDS_0/i_Enc/p_6_in ), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \TMDS_0/i_Enc/qD_reg[5] - (.C(pxClk), - .CE(1'b1), - .D(B[5]), - .Q(\TMDS_0/i_Enc/p_8_in ), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \TMDS_0/i_Enc/qD_reg[6] - (.C(pxClk), - .CE(1'b1), - .D(B[6]), - .Q(\TMDS_0/i_Enc/p_10_in ), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \TMDS_0/i_Enc/qD_reg[7] - (.C(pxClk), - .CE(1'b1), - .D(B[7]), - .Q(\TMDS_0/i_Enc/p_12_in ), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \TMDS_0/i_GBox/cntMod5_reg[0] - (.C(pxClkX5), - .CE(1'b1), - .D(plusOp[0]), - .Q(\TMDS_0/i_GBox/cntMod5_reg_n_0_ [0]), - .R(\cntMod5[2]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \TMDS_0/i_GBox/cntMod5_reg[1] - (.C(pxClkX5), - .CE(1'b1), - .D(plusOp[1]), - .Q(\TMDS_0/i_GBox/cntMod5_reg_n_0_ [1]), - .R(\cntMod5[2]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \TMDS_0/i_GBox/cntMod5_reg[2] - (.C(pxClkX5), - .CE(1'b1), - .D(plusOp[2]), - .Q(\TMDS_0/i_GBox/cntMod5_reg_n_0_ [2]), - .R(\cntMod5[2]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \TMDS_0/i_GBox/sReg_reg[0] - (.C(pxClkX5), - .CE(1'b1), - .D(\sReg[0]_i_1_n_0 ), - .Q(\TMDS_0/D1 ), - .R(\TMDS_3/Reset )); - FDRE #( - .INIT(1'b0)) - \TMDS_0/i_GBox/sReg_reg[1] - (.C(pxClkX5), - .CE(1'b1), - .D(\sReg[1]_i_1_n_0 ), - .Q(\TMDS_0/D2 ), - .R(\TMDS_3/Reset )); - FDRE #( - .INIT(1'b0)) - \TMDS_0/i_GBox/sReg_reg[2] - (.C(pxClkX5), - .CE(1'b1), - .D(\sReg[2]_i_1_n_0 ), - .Q(\TMDS_0/i_GBox/sReg_reg_n_0_ [2]), - .R(\TMDS_3/Reset )); - FDRE #( - .INIT(1'b0)) - \TMDS_0/i_GBox/sReg_reg[3] - (.C(pxClkX5), - .CE(1'b1), - .D(\sReg[3]_i_1_n_0 ), - .Q(\TMDS_0/i_GBox/sReg_reg_n_0_ [3]), - .R(\TMDS_3/Reset )); - FDRE #( - .INIT(1'b0)) - \TMDS_0/i_GBox/sReg_reg[4] - (.C(pxClkX5), - .CE(1'b1), - .D(\sReg[4]_i_1_n_0 ), - .Q(\TMDS_0/i_GBox/sReg_reg_n_0_ [4]), - .R(\TMDS_3/Reset )); - FDRE #( - .INIT(1'b0)) - \TMDS_0/i_GBox/sReg_reg[5] - (.C(pxClkX5), - .CE(1'b1), - .D(\sReg[5]_i_1_n_0 ), - .Q(\TMDS_0/i_GBox/sReg_reg_n_0_ [5]), - .R(\TMDS_3/Reset )); - FDRE #( - .INIT(1'b0)) - \TMDS_0/i_GBox/sReg_reg[6] - (.C(pxClkX5), - .CE(1'b1), - .D(\sReg[6]_i_1_n_0 ), - .Q(\TMDS_0/i_GBox/sReg_reg_n_0_ [6]), - .R(\TMDS_3/Reset )); - FDRE #( - .INIT(1'b0)) - \TMDS_0/i_GBox/sReg_reg[7] - (.C(pxClkX5), - .CE(1'b1), - .D(\sReg[7]_i_1_n_0 ), - .Q(\TMDS_0/i_GBox/sReg_reg_n_0_ [7]), - .R(\TMDS_3/Reset )); - FDRE #( - .INIT(1'b0)) - \TMDS_0/i_GBox/sReg_reg[8] - (.C(pxClkX5), - .CE(1'b1), - .D(\sReg[8]_i_1_n_0 ), - .Q(\TMDS_0/i_GBox/sReg_reg_n_0_ [8]), - .R(\TMDS_3/Reset )); - FDRE #( - .INIT(1'b0)) - \TMDS_0/i_GBox/sReg_reg[9] - (.C(pxClkX5), - .CE(1'b1), - .D(\sReg[9]_i_1_n_0 ), - .Q(\TMDS_0/i_GBox/sReg_reg_n_0_ [9]), - .R(\TMDS_3/Reset )); - (* XILINX_LEGACY_PRIM = "ODDRE1" *) - (* XILINX_TRANSFORM_PINMAP = "C:CLK SR:RST GND:T Q:OQ D1:D[0] D2:D[4]" *) - (* box_type = "PRIMITIVE" *) - OSERDESE3 #( - .DATA_WIDTH(8), - .INIT(1'b0), - .IS_CLK_INVERTED(1'b0), - .ODDR_MODE("TRUE"), - .OSERDES_D_BYPASS("FALSE"), - .OSERDES_T_BYPASS("TRUE"), - .SIM_DEVICE("ULTRASCALE_PLUS"), - .SIM_VERSION(2.000000)) - \TMDS_0/i_ODDRE_N - (.CLK(pxClkX5), - .CLKDIV(\NLW_TMDS_0/i_ODDRE_N_CLKDIV_UNCONNECTED ), - .D({\NLW_TMDS_0/i_ODDRE_N_D_UNCONNECTED [7:5],i_ODDRE_N_i_2__0_n_0,\NLW_TMDS_0/i_ODDRE_N_D_UNCONNECTED [3:1],i_ODDRE_N_i_1_n_0}), - .OQ(HDMI_D0_N), - .RST(\TMDS_3/Reset ), - .T(1'b0), - .T_OUT(\NLW_TMDS_0/i_ODDRE_N_T_OUT_UNCONNECTED )); - (* XILINX_LEGACY_PRIM = "ODDRE1" *) - (* XILINX_TRANSFORM_PINMAP = "C:CLK SR:RST GND:T Q:OQ D1:D[0] D2:D[4]" *) - (* box_type = "PRIMITIVE" *) - OSERDESE3 #( - .DATA_WIDTH(8), - .INIT(1'b0), - .IS_CLK_INVERTED(1'b0), - .ODDR_MODE("TRUE"), - .OSERDES_D_BYPASS("FALSE"), - .OSERDES_T_BYPASS("TRUE"), - .SIM_DEVICE("ULTRASCALE_PLUS"), - .SIM_VERSION(2.000000)) - \TMDS_0/i_ODDRE_P - (.CLK(pxClkX5), - .CLKDIV(\NLW_TMDS_0/i_ODDRE_P_CLKDIV_UNCONNECTED ), - .D({\NLW_TMDS_0/i_ODDRE_P_D_UNCONNECTED [7:5],\TMDS_0/D2 ,\NLW_TMDS_0/i_ODDRE_P_D_UNCONNECTED [3:1],\TMDS_0/D1 }), - .OQ(HDMI_D0_P), - .RST(\TMDS_3/Reset ), - .T(1'b0), - .T_OUT(\NLW_TMDS_0/i_ODDRE_P_T_OUT_UNCONNECTED )); - FDRE #( - .INIT(1'b0)) - \TMDS_1/i_Enc/Cnt_reg[1] - (.C(pxClk), - .CE(1'b1), - .D(\Cnt[1]_i_1__0_n_0 ), - .Q(\TMDS_1/i_Enc/Cnt_reg_n_0_ [1]), - .R(\Cnt[4]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \TMDS_1/i_Enc/Cnt_reg[2] - (.C(pxClk), - .CE(1'b1), - .D(\Cnt_reg[2]_i_1_n_0 ), - .Q(\TMDS_1/i_Enc/Cnt_reg_n_0_ [2]), - .R(\Cnt[4]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \TMDS_1/i_Enc/Cnt_reg[3] - (.C(pxClk), - .CE(1'b1), - .D(\Cnt[3]_i_1__0_n_0 ), - .Q(\TMDS_1/i_Enc/Cnt_reg_n_0_ [3]), - .R(\Cnt[4]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \TMDS_1/i_Enc/Cnt_reg[4] - (.C(pxClk), - .CE(1'b1), - .D(\Cnt[4]_i_1__0_n_0 ), - .Q(\TMDS_1/i_Enc/Cnt_reg_n_0_ [4]), - .R(\Cnt[4]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \TMDS_1/i_Enc/qD_reg[0] - (.C(pxClk), - .CE(1'b1), - .D(G[0]), - .Q(\TMDS_1/i_Enc/qD_reg_n_0_ ), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \TMDS_1/i_Enc/qD_reg[1] - (.C(pxClk), - .CE(1'b1), - .D(G[1]), - .Q(\TMDS_1/i_Enc/p_0_in ), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \TMDS_1/i_Enc/qD_reg[2] - (.C(pxClk), - .CE(1'b1), - .D(G[2]), - .Q(\TMDS_1/i_Enc/p_2_in ), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \TMDS_1/i_Enc/qD_reg[3] - (.C(pxClk), - .CE(1'b1), - .D(G[3]), - .Q(\TMDS_1/i_Enc/p_4_in ), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \TMDS_1/i_Enc/qD_reg[4] - (.C(pxClk), - .CE(1'b1), - .D(G[4]), - .Q(\TMDS_1/i_Enc/p_6_in ), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \TMDS_1/i_Enc/qD_reg[5] - (.C(pxClk), - .CE(1'b1), - .D(G[5]), - .Q(\TMDS_1/i_Enc/p_8_in ), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \TMDS_1/i_Enc/qD_reg[6] - (.C(pxClk), - .CE(1'b1), - .D(G[6]), - .Q(\TMDS_1/i_Enc/p_10_in ), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \TMDS_1/i_Enc/qD_reg[7] - (.C(pxClk), - .CE(1'b1), - .D(G[7]), - .Q(\TMDS_1/i_Enc/p_12_in ), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \TMDS_1/i_GBox/cntMod5_reg[0] - (.C(pxClkX5), - .CE(1'b1), - .D(\cntMod5[0]_i_1__0_n_0 ), - .Q(\TMDS_1/i_GBox/cntMod5_reg_n_0_ [0]), - .R(\cntMod5[2]_i_1__0_n_0 )); - FDRE #( - .INIT(1'b0)) - \TMDS_1/i_GBox/cntMod5_reg[1] - (.C(pxClkX5), - .CE(1'b1), - .D(\cntMod5[1]_i_1__0_n_0 ), - .Q(\TMDS_1/i_GBox/cntMod5_reg_n_0_ [1]), - .R(\cntMod5[2]_i_1__0_n_0 )); - FDRE #( - .INIT(1'b0)) - \TMDS_1/i_GBox/cntMod5_reg[2] - (.C(pxClkX5), - .CE(1'b1), - .D(\cntMod5[2]_i_2__0_n_0 ), - .Q(\TMDS_1/i_GBox/cntMod5_reg_n_0_ [2]), - .R(\cntMod5[2]_i_1__0_n_0 )); - FDRE #( - .INIT(1'b0)) - \TMDS_1/i_GBox/sReg_reg[0] - (.C(pxClkX5), - .CE(1'b1), - .D(\sReg[0]_i_1__0_n_0 ), - .Q(\TMDS_1/D1 ), - .R(\TMDS_3/Reset )); - FDRE #( - .INIT(1'b0)) - \TMDS_1/i_GBox/sReg_reg[1] - (.C(pxClkX5), - .CE(1'b1), - .D(\sReg[1]_i_1__0_n_0 ), - .Q(\TMDS_1/D2 ), - .R(\TMDS_3/Reset )); - FDRE #( - .INIT(1'b0)) - \TMDS_1/i_GBox/sReg_reg[2] - (.C(pxClkX5), - .CE(1'b1), - .D(\sReg[2]_i_1__0_n_0 ), - .Q(\TMDS_1/i_GBox/sReg_reg_n_0_ [2]), - .R(\TMDS_3/Reset )); - FDRE #( - .INIT(1'b0)) - \TMDS_1/i_GBox/sReg_reg[3] - (.C(pxClkX5), - .CE(1'b1), - .D(\sReg[3]_i_1__0_n_0 ), - .Q(\TMDS_1/i_GBox/sReg_reg_n_0_ [3]), - .R(\TMDS_3/Reset )); - FDRE #( - .INIT(1'b0)) - \TMDS_1/i_GBox/sReg_reg[4] - (.C(pxClkX5), - .CE(1'b1), - .D(\sReg[4]_i_1__0_n_0 ), - .Q(\TMDS_1/i_GBox/sReg_reg_n_0_ [4]), - .R(\TMDS_3/Reset )); - FDRE #( - .INIT(1'b0)) - \TMDS_1/i_GBox/sReg_reg[5] - (.C(pxClkX5), - .CE(1'b1), - .D(\sReg[5]_i_1__0_n_0 ), - .Q(\TMDS_1/i_GBox/sReg_reg_n_0_ [5]), - .R(\TMDS_3/Reset )); - FDRE #( - .INIT(1'b0)) - \TMDS_1/i_GBox/sReg_reg[6] - (.C(pxClkX5), - .CE(1'b1), - .D(\sReg[6]_i_1__0_n_0 ), - .Q(\TMDS_1/i_GBox/sReg_reg_n_0_ [6]), - .R(\TMDS_3/Reset )); - FDRE #( - .INIT(1'b0)) - \TMDS_1/i_GBox/sReg_reg[7] - (.C(pxClkX5), - .CE(1'b1), - .D(\sReg[7]_i_1__0_n_0 ), - .Q(\TMDS_1/i_GBox/sReg_reg_n_0_ [7]), - .R(\TMDS_3/Reset )); - FDRE #( - .INIT(1'b0)) - \TMDS_1/i_GBox/sReg_reg[8] - (.C(pxClkX5), - .CE(1'b1), - .D(\sReg[8]_i_1__0_n_0 ), - .Q(\TMDS_1/i_GBox/sReg_reg_n_0_ [8]), - .R(\TMDS_3/Reset )); - FDRE #( - .INIT(1'b0)) - \TMDS_1/i_GBox/sReg_reg[9] - (.C(pxClkX5), - .CE(1'b1), - .D(\sReg[9]_i_1__0_n_0 ), - .Q(\TMDS_1/i_GBox/sReg_reg_n_0_ [9]), - .R(\TMDS_3/Reset )); - (* XILINX_LEGACY_PRIM = "ODDRE1" *) - (* XILINX_TRANSFORM_PINMAP = "C:CLK SR:RST GND:T Q:OQ D1:D[0] D2:D[4]" *) - (* box_type = "PRIMITIVE" *) - OSERDESE3 #( - .DATA_WIDTH(8), - .INIT(1'b0), - .IS_CLK_INVERTED(1'b0), - .ODDR_MODE("TRUE"), - .OSERDES_D_BYPASS("FALSE"), - .OSERDES_T_BYPASS("TRUE"), - .SIM_DEVICE("ULTRASCALE_PLUS"), - .SIM_VERSION(2.000000)) - \TMDS_1/i_ODDRE_N - (.CLK(pxClkX5), - .CLKDIV(\NLW_TMDS_1/i_ODDRE_N_CLKDIV_UNCONNECTED ), - .D({\NLW_TMDS_1/i_ODDRE_N_D_UNCONNECTED [7:5],i_ODDRE_N_i_2__1_n_0,\NLW_TMDS_1/i_ODDRE_N_D_UNCONNECTED [3:1],i_ODDRE_N_i_1__0_n_0}), - .OQ(HDMI_D1_N), - .RST(\TMDS_3/Reset ), - .T(1'b0), - .T_OUT(\NLW_TMDS_1/i_ODDRE_N_T_OUT_UNCONNECTED )); - (* XILINX_LEGACY_PRIM = "ODDRE1" *) - (* XILINX_TRANSFORM_PINMAP = "C:CLK SR:RST GND:T Q:OQ D1:D[0] D2:D[4]" *) - (* box_type = "PRIMITIVE" *) - OSERDESE3 #( - .DATA_WIDTH(8), - .INIT(1'b0), - .IS_CLK_INVERTED(1'b0), - .ODDR_MODE("TRUE"), - .OSERDES_D_BYPASS("FALSE"), - .OSERDES_T_BYPASS("TRUE"), - .SIM_DEVICE("ULTRASCALE_PLUS"), - .SIM_VERSION(2.000000)) - \TMDS_1/i_ODDRE_P - (.CLK(pxClkX5), - .CLKDIV(\NLW_TMDS_1/i_ODDRE_P_CLKDIV_UNCONNECTED ), - .D({\NLW_TMDS_1/i_ODDRE_P_D_UNCONNECTED [7:5],\TMDS_1/D2 ,\NLW_TMDS_1/i_ODDRE_P_D_UNCONNECTED [3:1],\TMDS_1/D1 }), - .OQ(HDMI_D1_P), - .RST(\TMDS_3/Reset ), - .T(1'b0), - .T_OUT(\NLW_TMDS_1/i_ODDRE_P_T_OUT_UNCONNECTED )); - FDRE #( - .INIT(1'b0)) - \TMDS_2/i_Enc/Cnt_reg[1] - (.C(pxClk), - .CE(1'b1), - .D(\Cnt[1]_i_1__1_n_0 ), - .Q(\TMDS_2/i_Enc/Cnt_reg_n_0_ [1]), - .R(\Cnt[4]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \TMDS_2/i_Enc/Cnt_reg[2] - (.C(pxClk), - .CE(1'b1), - .D(\Cnt_reg[2]_i_1__0_n_0 ), - .Q(\TMDS_2/i_Enc/Cnt_reg_n_0_ [2]), - .R(\Cnt[4]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \TMDS_2/i_Enc/Cnt_reg[3] - (.C(pxClk), - .CE(1'b1), - .D(\Cnt_reg[3]_i_1_n_0 ), - .Q(\TMDS_2/i_Enc/Cnt_reg_n_0_ [3]), - .R(\Cnt[4]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \TMDS_2/i_Enc/Cnt_reg[4] - (.C(pxClk), - .CE(1'b1), - .D(\Cnt[4]_i_1__1_n_0 ), - .Q(\TMDS_2/i_Enc/Cnt_reg_n_0_ [4]), - .R(\Cnt[4]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \TMDS_2/i_Enc/qD_reg[0] - (.C(pxClk), - .CE(1'b1), - .D(R[0]), - .Q(\TMDS_2/i_Enc/qD_reg_n_0_ ), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \TMDS_2/i_Enc/qD_reg[1] - (.C(pxClk), - .CE(1'b1), - .D(R[1]), - .Q(\TMDS_2/i_Enc/p_0_in ), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \TMDS_2/i_Enc/qD_reg[2] - (.C(pxClk), - .CE(1'b1), - .D(R[2]), - .Q(\TMDS_2/i_Enc/p_2_in ), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \TMDS_2/i_Enc/qD_reg[3] - (.C(pxClk), - .CE(1'b1), - .D(R[3]), - .Q(\TMDS_2/i_Enc/p_4_in ), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \TMDS_2/i_Enc/qD_reg[4] - (.C(pxClk), - .CE(1'b1), - .D(R[4]), - .Q(\TMDS_2/i_Enc/p_6_in ), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \TMDS_2/i_Enc/qD_reg[5] - (.C(pxClk), - .CE(1'b1), - .D(R[5]), - .Q(\TMDS_2/i_Enc/p_8_in ), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \TMDS_2/i_Enc/qD_reg[6] - (.C(pxClk), - .CE(1'b1), - .D(R[6]), - .Q(\TMDS_2/i_Enc/p_10_in ), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \TMDS_2/i_Enc/qD_reg[7] - (.C(pxClk), - .CE(1'b1), - .D(R[7]), - .Q(\TMDS_2/i_Enc/p_12_in ), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \TMDS_2/i_GBox/cntMod5_reg[0] - (.C(pxClkX5), - .CE(1'b1), - .D(\cntMod5[0]_i_1__1_n_0 ), - .Q(\TMDS_2/i_GBox/cntMod5_reg_n_0_ [0]), - .R(\cntMod5[2]_i_1__1_n_0 )); - FDRE #( - .INIT(1'b0)) - \TMDS_2/i_GBox/cntMod5_reg[1] - (.C(pxClkX5), - .CE(1'b1), - .D(\cntMod5[1]_i_1__1_n_0 ), - .Q(\TMDS_2/i_GBox/cntMod5_reg_n_0_ [1]), - .R(\cntMod5[2]_i_1__1_n_0 )); - FDRE #( - .INIT(1'b0)) - \TMDS_2/i_GBox/cntMod5_reg[2] - (.C(pxClkX5), - .CE(1'b1), - .D(\cntMod5[2]_i_2__1_n_0 ), - .Q(\TMDS_2/i_GBox/cntMod5_reg_n_0_ [2]), - .R(\cntMod5[2]_i_1__1_n_0 )); - FDRE #( - .INIT(1'b0)) - \TMDS_2/i_GBox/sReg_reg[0] - (.C(pxClkX5), - .CE(1'b1), - .D(\sReg[0]_i_1__1_n_0 ), - .Q(\TMDS_2/D1 ), - .R(\TMDS_3/Reset )); - FDRE #( - .INIT(1'b0)) - \TMDS_2/i_GBox/sReg_reg[1] - (.C(pxClkX5), - .CE(1'b1), - .D(\sReg[1]_i_1__1_n_0 ), - .Q(\TMDS_2/D2 ), - .R(\TMDS_3/Reset )); - FDRE #( - .INIT(1'b0)) - \TMDS_2/i_GBox/sReg_reg[2] - (.C(pxClkX5), - .CE(1'b1), - .D(\sReg[2]_i_1__1_n_0 ), - .Q(\TMDS_2/i_GBox/sReg_reg_n_0_ [2]), - .R(\TMDS_3/Reset )); - FDRE #( - .INIT(1'b0)) - \TMDS_2/i_GBox/sReg_reg[3] - (.C(pxClkX5), - .CE(1'b1), - .D(\sReg[3]_i_1__1_n_0 ), - .Q(\TMDS_2/i_GBox/sReg_reg_n_0_ [3]), - .R(\TMDS_3/Reset )); - FDRE #( - .INIT(1'b0)) - \TMDS_2/i_GBox/sReg_reg[4] - (.C(pxClkX5), - .CE(1'b1), - .D(\sReg[4]_i_1__1_n_0 ), - .Q(\TMDS_2/i_GBox/sReg_reg_n_0_ [4]), - .R(\TMDS_3/Reset )); - FDRE #( - .INIT(1'b0)) - \TMDS_2/i_GBox/sReg_reg[5] - (.C(pxClkX5), - .CE(1'b1), - .D(\sReg[5]_i_1__1_n_0 ), - .Q(\TMDS_2/i_GBox/sReg_reg_n_0_ [5]), - .R(\TMDS_3/Reset )); - FDRE #( - .INIT(1'b0)) - \TMDS_2/i_GBox/sReg_reg[6] - (.C(pxClkX5), - .CE(1'b1), - .D(\sReg[6]_i_1__1_n_0 ), - .Q(\TMDS_2/i_GBox/sReg_reg_n_0_ [6]), - .R(\TMDS_3/Reset )); - FDRE #( - .INIT(1'b0)) - \TMDS_2/i_GBox/sReg_reg[7] - (.C(pxClkX5), - .CE(1'b1), - .D(\sReg[7]_i_1__1_n_0 ), - .Q(\TMDS_2/i_GBox/sReg_reg_n_0_ [7]), - .R(\TMDS_3/Reset )); - FDRE #( - .INIT(1'b0)) - \TMDS_2/i_GBox/sReg_reg[8] - (.C(pxClkX5), - .CE(1'b1), - .D(\sReg[8]_i_1__1_n_0 ), - .Q(\TMDS_2/i_GBox/sReg_reg_n_0_ [8]), - .R(\TMDS_3/Reset )); - FDRE #( - .INIT(1'b0)) - \TMDS_2/i_GBox/sReg_reg[9] - (.C(pxClkX5), - .CE(1'b1), - .D(\sReg[9]_i_1__1_n_0 ), - .Q(\TMDS_2/i_GBox/sReg_reg_n_0_ [9]), - .R(\TMDS_3/Reset )); - (* XILINX_LEGACY_PRIM = "ODDRE1" *) - (* XILINX_TRANSFORM_PINMAP = "C:CLK SR:RST GND:T Q:OQ D1:D[0] D2:D[4]" *) - (* box_type = "PRIMITIVE" *) - OSERDESE3 #( - .DATA_WIDTH(8), - .INIT(1'b0), - .IS_CLK_INVERTED(1'b0), - .ODDR_MODE("TRUE"), - .OSERDES_D_BYPASS("FALSE"), - .OSERDES_T_BYPASS("TRUE"), - .SIM_DEVICE("ULTRASCALE_PLUS"), - .SIM_VERSION(2.000000)) - \TMDS_2/i_ODDRE_N - (.CLK(pxClkX5), - .CLKDIV(\NLW_TMDS_2/i_ODDRE_N_CLKDIV_UNCONNECTED ), - .D({\NLW_TMDS_2/i_ODDRE_N_D_UNCONNECTED [7:5],i_ODDRE_N_i_2__2_n_0,\NLW_TMDS_2/i_ODDRE_N_D_UNCONNECTED [3:1],i_ODDRE_N_i_1__1_n_0}), - .OQ(HDMI_D2_N), - .RST(\TMDS_3/Reset ), - .T(1'b0), - .T_OUT(\NLW_TMDS_2/i_ODDRE_N_T_OUT_UNCONNECTED )); - (* XILINX_LEGACY_PRIM = "ODDRE1" *) - (* XILINX_TRANSFORM_PINMAP = "C:CLK SR:RST GND:T Q:OQ D1:D[0] D2:D[4]" *) - (* box_type = "PRIMITIVE" *) - OSERDESE3 #( - .DATA_WIDTH(8), - .INIT(1'b0), - .IS_CLK_INVERTED(1'b0), - .ODDR_MODE("TRUE"), - .OSERDES_D_BYPASS("FALSE"), - .OSERDES_T_BYPASS("TRUE"), - .SIM_DEVICE("ULTRASCALE_PLUS"), - .SIM_VERSION(2.000000)) - \TMDS_2/i_ODDRE_P - (.CLK(pxClkX5), - .CLKDIV(\NLW_TMDS_2/i_ODDRE_P_CLKDIV_UNCONNECTED ), - .D({\NLW_TMDS_2/i_ODDRE_P_D_UNCONNECTED [7:5],\TMDS_2/D2 ,\NLW_TMDS_2/i_ODDRE_P_D_UNCONNECTED [3:1],\TMDS_2/D1 }), - .OQ(HDMI_D2_P), - .RST(\TMDS_3/Reset ), - .T(1'b0), - .T_OUT(\NLW_TMDS_2/i_ODDRE_P_T_OUT_UNCONNECTED )); - FDRE #( - .INIT(1'b0)) - \TMDS_3/i_GBox/cntMod5_reg[0] - (.C(pxClkX5), - .CE(1'b1), - .D(\cntMod5[0]_i_1__2_n_0 ), - .Q(\TMDS_3/i_GBox/cntMod5_reg_n_0_ [0]), - .R(\cntMod5[2]_i_1__2_n_0 )); - FDRE #( - .INIT(1'b0)) - \TMDS_3/i_GBox/cntMod5_reg[1] - (.C(pxClkX5), - .CE(1'b1), - .D(\cntMod5[1]_i_1__2_n_0 ), - .Q(\TMDS_3/i_GBox/cntMod5_reg_n_0_ [1]), - .R(\cntMod5[2]_i_1__2_n_0 )); - FDRE #( - .INIT(1'b0)) - \TMDS_3/i_GBox/cntMod5_reg[2] - (.C(pxClkX5), - .CE(1'b1), - .D(\cntMod5[2]_i_2__2_n_0 ), - .Q(\TMDS_3/i_GBox/cntMod5_reg_n_0_ [2]), - .R(\cntMod5[2]_i_1__2_n_0 )); - FDRE #( - .INIT(1'b0)) - \TMDS_3/i_GBox/sReg_reg[0] - (.C(pxClkX5), - .CE(1'b1), - .D(\sReg[0]_i_1__2_n_0 ), - .Q(\TMDS_3/D1 ), - .R(\TMDS_3/Reset )); - FDRE #( - .INIT(1'b0)) - \TMDS_3/i_GBox/sReg_reg[1] - (.C(pxClkX5), - .CE(1'b1), - .D(\sReg[1]_i_1__2_n_0 ), - .Q(\TMDS_3/D2 ), - .R(\TMDS_3/Reset )); - FDRE #( - .INIT(1'b0)) - \TMDS_3/i_GBox/sReg_reg[3] - (.C(pxClkX5), - .CE(1'b1), - .D(\sReg[3]_i_1__2_n_0 ), - .Q(\TMDS_3/i_GBox/sReg_reg_n_0_ ), - .R(\TMDS_3/Reset )); - (* XILINX_LEGACY_PRIM = "ODDRE1" *) - (* XILINX_TRANSFORM_PINMAP = "C:CLK SR:RST GND:T Q:OQ D1:D[0] D2:D[4]" *) - (* box_type = "PRIMITIVE" *) - OSERDESE3 #( - .DATA_WIDTH(8), - .INIT(1'b0), - .IS_CLK_INVERTED(1'b0), - .ODDR_MODE("TRUE"), - .OSERDES_D_BYPASS("FALSE"), - .OSERDES_T_BYPASS("TRUE"), - .SIM_DEVICE("ULTRASCALE_PLUS"), - .SIM_VERSION(2.000000)) - \TMDS_3/i_ODDRE_N - (.CLK(pxClkX5), - .CLKDIV(\NLW_TMDS_3/i_ODDRE_N_CLKDIV_UNCONNECTED ), - .D({\NLW_TMDS_3/i_ODDRE_N_D_UNCONNECTED [7:5],i_ODDRE_N_i_2_n_0,\NLW_TMDS_3/i_ODDRE_N_D_UNCONNECTED [3:1],i_ODDRE_N_i_1__2_n_0}), - .OQ(HDMI_CK_N), - .RST(\TMDS_3/Reset ), - .T(1'b0), - .T_OUT(\NLW_TMDS_3/i_ODDRE_N_T_OUT_UNCONNECTED )); - (* XILINX_LEGACY_PRIM = "ODDRE1" *) - (* XILINX_TRANSFORM_PINMAP = "C:CLK SR:RST GND:T Q:OQ D1:D[0] D2:D[4]" *) - (* box_type = "PRIMITIVE" *) - OSERDESE3 #( - .DATA_WIDTH(8), - .INIT(1'b0), - .IS_CLK_INVERTED(1'b0), - .ODDR_MODE("TRUE"), - .OSERDES_D_BYPASS("FALSE"), - .OSERDES_T_BYPASS("TRUE"), - .SIM_DEVICE("ULTRASCALE_PLUS"), - .SIM_VERSION(2.000000)) - \TMDS_3/i_ODDRE_P - (.CLK(pxClkX5), - .CLKDIV(\NLW_TMDS_3/i_ODDRE_P_CLKDIV_UNCONNECTED ), - .D({\NLW_TMDS_3/i_ODDRE_P_D_UNCONNECTED [7:5],\TMDS_3/D2 ,\NLW_TMDS_3/i_ODDRE_P_D_UNCONNECTED [3:1],\TMDS_3/D1 }), - .OQ(HDMI_CK_P), - .RST(\TMDS_3/Reset ), - .T(1'b0), - .T_OUT(\NLW_TMDS_3/i_ODDRE_P_T_OUT_UNCONNECTED )); - LUT1 #( - .INIT(2'h1)) - \cntMod5[0]_i_1 - (.I0(\TMDS_0/i_GBox/cntMod5_reg_n_0_ [0]), - .O(plusOp[0])); - LUT1 #( - .INIT(2'h1)) - \cntMod5[0]_i_1__0 - (.I0(\TMDS_1/i_GBox/cntMod5_reg_n_0_ [0]), - .O(\cntMod5[0]_i_1__0_n_0 )); - LUT1 #( - .INIT(2'h1)) - \cntMod5[0]_i_1__1 - (.I0(\TMDS_2/i_GBox/cntMod5_reg_n_0_ [0]), - .O(\cntMod5[0]_i_1__1_n_0 )); - LUT1 #( - .INIT(2'h1)) - \cntMod5[0]_i_1__2 - (.I0(\TMDS_3/i_GBox/cntMod5_reg_n_0_ [0]), - .O(\cntMod5[0]_i_1__2_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair45" *) - LUT2 #( - .INIT(4'h6)) - \cntMod5[1]_i_1 - (.I0(\TMDS_0/i_GBox/cntMod5_reg_n_0_ [0]), - .I1(\TMDS_0/i_GBox/cntMod5_reg_n_0_ [1]), - .O(plusOp[1])); - (* SOFT_HLUTNM = "soft_lutpair46" *) - LUT2 #( - .INIT(4'h6)) - \cntMod5[1]_i_1__0 - (.I0(\TMDS_1/i_GBox/cntMod5_reg_n_0_ [0]), - .I1(\TMDS_1/i_GBox/cntMod5_reg_n_0_ [1]), - .O(\cntMod5[1]_i_1__0_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair47" *) - LUT2 #( - .INIT(4'h6)) - \cntMod5[1]_i_1__1 - (.I0(\TMDS_2/i_GBox/cntMod5_reg_n_0_ [0]), - .I1(\TMDS_2/i_GBox/cntMod5_reg_n_0_ [1]), - .O(\cntMod5[1]_i_1__1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair48" *) - LUT2 #( - .INIT(4'h6)) - \cntMod5[1]_i_1__2 - (.I0(\TMDS_3/i_GBox/cntMod5_reg_n_0_ [0]), - .I1(\TMDS_3/i_GBox/cntMod5_reg_n_0_ [1]), - .O(\cntMod5[1]_i_1__2_n_0 )); - LUT4 #( - .INIT(16'h04FF)) - \cntMod5[2]_i_1 - (.I0(\TMDS_0/i_GBox/cntMod5_reg_n_0_ [1]), - .I1(\TMDS_0/i_GBox/cntMod5_reg_n_0_ [2]), - .I2(\TMDS_0/i_GBox/cntMod5_reg_n_0_ [0]), - .I3(ResetN), - .O(\cntMod5[2]_i_1_n_0 )); - LUT4 #( - .INIT(16'h04FF)) - \cntMod5[2]_i_1__0 - (.I0(\TMDS_1/i_GBox/cntMod5_reg_n_0_ [1]), - .I1(\TMDS_1/i_GBox/cntMod5_reg_n_0_ [2]), - .I2(\TMDS_1/i_GBox/cntMod5_reg_n_0_ [0]), - .I3(ResetN), - .O(\cntMod5[2]_i_1__0_n_0 )); - LUT4 #( - .INIT(16'h04FF)) - \cntMod5[2]_i_1__1 - (.I0(\TMDS_2/i_GBox/cntMod5_reg_n_0_ [1]), - .I1(\TMDS_2/i_GBox/cntMod5_reg_n_0_ [2]), - .I2(\TMDS_2/i_GBox/cntMod5_reg_n_0_ [0]), - .I3(ResetN), - .O(\cntMod5[2]_i_1__1_n_0 )); - LUT4 #( - .INIT(16'h04FF)) - \cntMod5[2]_i_1__2 - (.I0(\TMDS_3/i_GBox/cntMod5_reg_n_0_ [1]), - .I1(\TMDS_3/i_GBox/cntMod5_reg_n_0_ [2]), - .I2(\TMDS_3/i_GBox/cntMod5_reg_n_0_ [0]), - .I3(ResetN), - .O(\cntMod5[2]_i_1__2_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair45" *) - LUT3 #( - .INIT(8'h6A)) - \cntMod5[2]_i_2 - (.I0(\TMDS_0/i_GBox/cntMod5_reg_n_0_ [2]), - .I1(\TMDS_0/i_GBox/cntMod5_reg_n_0_ [1]), - .I2(\TMDS_0/i_GBox/cntMod5_reg_n_0_ [0]), - .O(plusOp[2])); - (* SOFT_HLUTNM = "soft_lutpair46" *) - LUT3 #( - .INIT(8'h6A)) - \cntMod5[2]_i_2__0 - (.I0(\TMDS_1/i_GBox/cntMod5_reg_n_0_ [2]), - .I1(\TMDS_1/i_GBox/cntMod5_reg_n_0_ [1]), - .I2(\TMDS_1/i_GBox/cntMod5_reg_n_0_ [0]), - .O(\cntMod5[2]_i_2__0_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair47" *) - LUT3 #( - .INIT(8'h6A)) - \cntMod5[2]_i_2__1 - (.I0(\TMDS_2/i_GBox/cntMod5_reg_n_0_ [2]), - .I1(\TMDS_2/i_GBox/cntMod5_reg_n_0_ [1]), - .I2(\TMDS_2/i_GBox/cntMod5_reg_n_0_ [0]), - .O(\cntMod5[2]_i_2__1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair48" *) - LUT3 #( - .INIT(8'h6A)) - \cntMod5[2]_i_2__2 - (.I0(\TMDS_3/i_GBox/cntMod5_reg_n_0_ [2]), - .I1(\TMDS_3/i_GBox/cntMod5_reg_n_0_ [1]), - .I2(\TMDS_3/i_GBox/cntMod5_reg_n_0_ [0]), - .O(\cntMod5[2]_i_2__2_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair6" *) - LUT5 #( - .INIT(32'h96696996)) - g0_b0 - (.I0(\TMDS_0/i_Enc/qD_reg_n_0_ ), - .I1(\TMDS_0/i_Enc/p_0_in ), - .I2(\TMDS_0/i_Enc/p_2_in ), - .I3(\TMDS_0/i_Enc/p_4_in ), - .I4(\TMDS_0/i_Enc/p_6_in ), - .O(g0_b0_n_0)); - (* SOFT_HLUTNM = "soft_lutpair0" *) - LUT5 #( - .INIT(32'h96696996)) - g0_b0__0 - (.I0(\TMDS_1/i_Enc/qD_reg_n_0_ ), - .I1(\TMDS_1/i_Enc/p_0_in ), - .I2(\TMDS_1/i_Enc/p_2_in ), - .I3(\TMDS_1/i_Enc/p_4_in ), - .I4(\TMDS_1/i_Enc/p_6_in ), - .O(g0_b0__0_n_0)); - (* SOFT_HLUTNM = "soft_lutpair8" *) - LUT5 #( - .INIT(32'h96696996)) - g0_b0__1 - (.I0(\TMDS_2/i_Enc/qD_reg_n_0_ ), - .I1(\TMDS_2/i_Enc/p_0_in ), - .I2(\TMDS_2/i_Enc/p_2_in ), - .I3(\TMDS_2/i_Enc/p_4_in ), - .I4(\TMDS_2/i_Enc/p_6_in ), - .O(g0_b0__1_n_0)); - (* SOFT_HLUTNM = "soft_lutpair37" *) - LUT3 #( - .INIT(8'h96)) - g0_b0__2 - (.I0(\TMDS_0/i_Enc/p_4_in ), - .I1(\TMDS_0/i_Enc/p_0_in ), - .I2(g0_b2_i_2__0_n_0), - .O(g0_b0__2_n_0)); - (* SOFT_HLUTNM = "soft_lutpair43" *) - LUT3 #( - .INIT(8'h96)) - g0_b0__3 - (.I0(\TMDS_1/i_Enc/p_4_in ), - .I1(\TMDS_1/i_Enc/p_0_in ), - .I2(g0_b2_i_2__1_n_0), - .O(g0_b0__3_n_0)); - (* SOFT_HLUTNM = "soft_lutpair42" *) - LUT3 #( - .INIT(8'h96)) - g0_b0__4 - (.I0(\TMDS_2/i_Enc/p_0_in ), - .I1(\TMDS_2/i_Enc/p_4_in ), - .I2(\TMDS_2/i_Enc/p_9_in ), - .O(g0_b0__4_n_0)); - (* SOFT_HLUTNM = "soft_lutpair6" *) - LUT5 #( - .INIT(32'h177E7EE8)) - g0_b1 - (.I0(\TMDS_0/i_Enc/qD_reg_n_0_ ), - .I1(\TMDS_0/i_Enc/p_0_in ), - .I2(\TMDS_0/i_Enc/p_2_in ), - .I3(\TMDS_0/i_Enc/p_4_in ), - .I4(\TMDS_0/i_Enc/p_6_in ), - .O(g0_b1_n_0)); - (* SOFT_HLUTNM = "soft_lutpair0" *) - LUT5 #( - .INIT(32'h177E7EE8)) - g0_b1__0 - (.I0(\TMDS_1/i_Enc/qD_reg_n_0_ ), - .I1(\TMDS_1/i_Enc/p_0_in ), - .I2(\TMDS_1/i_Enc/p_2_in ), - .I3(\TMDS_1/i_Enc/p_4_in ), - .I4(\TMDS_1/i_Enc/p_6_in ), - .O(g0_b1__0_n_0)); - (* SOFT_HLUTNM = "soft_lutpair5" *) - LUT5 #( - .INIT(32'h177E7EE8)) - g0_b1__1 - (.I0(\TMDS_2/i_Enc/qD_reg_n_0_ ), - .I1(\TMDS_2/i_Enc/p_0_in ), - .I2(\TMDS_2/i_Enc/p_2_in ), - .I3(\TMDS_2/i_Enc/p_4_in ), - .I4(\TMDS_2/i_Enc/p_6_in ), - .O(g0_b1__1_n_0)); - LUT6 #( - .INIT(64'hB7E21DB7EDB847ED)) - g0_b1__2 - (.I0(\TMDS_0/i_Enc/p_4_in ), - .I1(\TMDS_0/i_Enc/qD_reg_n_0_ ), - .I2(\TMDS_0/i_Enc/p_0_in ), - .I3(\TMDS_0/i_Enc/p_2_in ), - .I4(g0_b2_i_1_n_0), - .I5(g0_b2_i_2__0_n_0), - .O(g0_b1__2_n_0)); - LUT6 #( - .INIT(64'h1DB7B7E247EDEDB8)) - g0_b1__3 - (.I0(\TMDS_1/i_Enc/p_4_in ), - .I1(\TMDS_1/i_Enc/qD_reg_n_0_ ), - .I2(\TMDS_1/i_Enc/p_0_in ), - .I3(\TMDS_1/i_Enc/p_2_in ), - .I4(g0_b2_i_1__0_n_0), - .I5(g0_b2_i_2__1_n_0), - .O(g0_b1__3_n_0)); - LUT6 #( - .INIT(64'h653FCF6A56F3FCA6)) - g0_b1__4 - (.I0(\TMDS_2/i_Enc/p_2_in ), - .I1(\TMDS_2/i_Enc/p_0_in ), - .I2(\TMDS_2/i_Enc/qD_reg_n_0_ ), - .I3(\TMDS_2/i_Enc/p_4_in ), - .I4(g0_b2_i_1__1_n_0), - .I5(\TMDS_2/i_Enc/p_9_in ), - .O(g0_b1__4_n_0)); - (* SOFT_HLUTNM = "soft_lutpair10" *) - LUT5 #( - .INIT(32'hE8808000)) - g0_b2 - (.I0(\TMDS_0/i_Enc/qD_reg_n_0_ ), - .I1(\TMDS_0/i_Enc/p_0_in ), - .I2(\TMDS_0/i_Enc/p_2_in ), - .I3(\TMDS_0/i_Enc/p_4_in ), - .I4(\TMDS_0/i_Enc/p_6_in ), - .O(g0_b2_n_0)); - (* SOFT_HLUTNM = "soft_lutpair11" *) - LUT5 #( - .INIT(32'hE8808000)) - g0_b2__0 - (.I0(\TMDS_1/i_Enc/qD_reg_n_0_ ), - .I1(\TMDS_1/i_Enc/p_0_in ), - .I2(\TMDS_1/i_Enc/p_2_in ), - .I3(\TMDS_1/i_Enc/p_4_in ), - .I4(\TMDS_1/i_Enc/p_6_in ), - .O(g0_b2__0_n_0)); - (* SOFT_HLUTNM = "soft_lutpair5" *) - LUT5 #( - .INIT(32'hE8808000)) - g0_b2__1 - (.I0(\TMDS_2/i_Enc/qD_reg_n_0_ ), - .I1(\TMDS_2/i_Enc/p_0_in ), - .I2(\TMDS_2/i_Enc/p_2_in ), - .I3(\TMDS_2/i_Enc/p_4_in ), - .I4(\TMDS_2/i_Enc/p_6_in ), - .O(g0_b2__1_n_0)); - LUT6 #( - .INIT(64'h481CC24800048000)) - g0_b2__2 - (.I0(\TMDS_0/i_Enc/p_4_in ), - .I1(\TMDS_0/i_Enc/qD_reg_n_0_ ), - .I2(\TMDS_0/i_Enc/p_0_in ), - .I3(\TMDS_0/i_Enc/p_2_in ), - .I4(g0_b2_i_1_n_0), - .I5(g0_b2_i_2__0_n_0), - .O(g0_b2__2_n_0)); - LUT6 #( - .INIT(64'hC248481C80000004)) - g0_b2__3 - (.I0(\TMDS_1/i_Enc/p_4_in ), - .I1(\TMDS_1/i_Enc/qD_reg_n_0_ ), - .I2(\TMDS_1/i_Enc/p_0_in ), - .I3(\TMDS_1/i_Enc/p_2_in ), - .I4(g0_b2_i_1__0_n_0), - .I5(g0_b2_i_2__1_n_0), - .O(g0_b2__3_n_0)); - LUT6 #( - .INIT(64'h92C0309480000010)) - g0_b2__4 - (.I0(\TMDS_2/i_Enc/p_2_in ), - .I1(\TMDS_2/i_Enc/p_0_in ), - .I2(\TMDS_2/i_Enc/qD_reg_n_0_ ), - .I3(\TMDS_2/i_Enc/p_4_in ), - .I4(g0_b2_i_1__1_n_0), - .I5(\TMDS_2/i_Enc/p_9_in ), - .O(g0_b2__4_n_0)); - LUT6 #( - .INIT(64'h00007177001077F7)) - g0_b2_i_1 - (.I0(g0_b1_n_0), - .I1(g0_b2_i_3_n_0), - .I2(\TMDS_0/i_Enc/qD_reg_n_0_ ), - .I3(g0_b0_n_0), - .I4(g0_b2_n_0), - .I5(g0_b2_i_4_n_0), - .O(g0_b2_i_1_n_0)); - LUT6 #( - .INIT(64'hEEEEEEEEEEEEEEE0)) - g0_b2_i_1__0 - (.I0(g0_b2_i_3__0_n_0), - .I1(g0_b2__0_n_0), - .I2(g0_b2_i_4__0_n_0), - .I3(\TMDS_1/i_Enc/p_12_in ), - .I4(\TMDS_1/i_Enc/p_10_in ), - .I5(g0_b1__0_n_0), - .O(g0_b2_i_1__0_n_0)); - LUT6 #( - .INIT(64'hBABABAFBA2BABABA)) - g0_b2_i_1__1 - (.I0(g0_b2__1_n_0), - .I1(g0_b2_i_3__1_n_0), - .I2(g0_b1__1_n_0), - .I3(g0_b2_i_4__1_n_0), - .I4(\TMDS_2/i_Enc/qD_reg_n_0_ ), - .I5(g0_b0__1_n_0), - .O(g0_b2_i_1__1_n_0)); - (* SOFT_HLUTNM = "soft_lutpair8" *) - LUT5 #( - .INIT(32'h96696996)) - g0_b2_i_2 - (.I0(\TMDS_2/i_Enc/p_6_in ), - .I1(\TMDS_2/i_Enc/p_2_in ), - .I2(\TMDS_2/i_Enc/p_0_in ), - .I3(\TMDS_2/i_Enc/qD_reg_n_0_ ), - .I4(\TMDS_2/i_Enc/p_4_in ), - .O(\TMDS_2/i_Enc/p_9_in )); - (* SOFT_HLUTNM = "soft_lutpair10" *) - LUT5 #( - .INIT(32'h96696996)) - g0_b2_i_2__0 - (.I0(\TMDS_0/i_Enc/p_6_in ), - .I1(\TMDS_0/i_Enc/p_2_in ), - .I2(\TMDS_0/i_Enc/p_0_in ), - .I3(\TMDS_0/i_Enc/qD_reg_n_0_ ), - .I4(\TMDS_0/i_Enc/p_4_in ), - .O(g0_b2_i_2__0_n_0)); - (* SOFT_HLUTNM = "soft_lutpair11" *) - LUT5 #( - .INIT(32'h96696996)) - g0_b2_i_2__1 - (.I0(\TMDS_1/i_Enc/p_6_in ), - .I1(\TMDS_1/i_Enc/p_2_in ), - .I2(\TMDS_1/i_Enc/p_0_in ), - .I3(\TMDS_1/i_Enc/qD_reg_n_0_ ), - .I4(\TMDS_1/i_Enc/p_4_in ), - .O(g0_b2_i_2__1_n_0)); - (* SOFT_HLUTNM = "soft_lutpair14" *) - LUT3 #( - .INIT(8'hE8)) - g0_b2_i_3 - (.I0(\TMDS_0/i_Enc/p_8_in ), - .I1(\TMDS_0/i_Enc/p_12_in ), - .I2(\TMDS_0/i_Enc/p_10_in ), - .O(g0_b2_i_3_n_0)); - LUT6 #( - .INIT(64'hE8FE80E800800000)) - g0_b2_i_3__0 - (.I0(\TMDS_1/i_Enc/p_10_in ), - .I1(\TMDS_1/i_Enc/p_12_in ), - .I2(\TMDS_1/i_Enc/p_8_in ), - .I3(\TMDS_1/i_Enc/qD_reg_n_0_ ), - .I4(g0_b0__0_n_0), - .I5(g0_b1__0_n_0), - .O(g0_b2_i_3__0_n_0)); - (* SOFT_HLUTNM = "soft_lutpair12" *) - LUT3 #( - .INIT(8'h17)) - g0_b2_i_3__1 - (.I0(\TMDS_2/i_Enc/p_10_in ), - .I1(\TMDS_2/i_Enc/p_12_in ), - .I2(\TMDS_2/i_Enc/p_8_in ), - .O(g0_b2_i_3__1_n_0)); - (* SOFT_HLUTNM = "soft_lutpair41" *) - LUT3 #( - .INIT(8'h96)) - g0_b2_i_4 - (.I0(\TMDS_0/i_Enc/p_8_in ), - .I1(\TMDS_0/i_Enc/p_12_in ), - .I2(\TMDS_0/i_Enc/p_10_in ), - .O(g0_b2_i_4_n_0)); - (* SOFT_HLUTNM = "soft_lutpair4" *) - LUT5 #( - .INIT(32'hFFFF90FF)) - g0_b2_i_4__0 - (.I0(\TMDS_1/i_Enc/p_10_in ), - .I1(\TMDS_1/i_Enc/p_12_in ), - .I2(\TMDS_1/i_Enc/p_8_in ), - .I3(\TMDS_1/i_Enc/qD_reg_n_0_ ), - .I4(g0_b0__0_n_0), - .O(g0_b2_i_4__0_n_0)); - (* SOFT_HLUTNM = "soft_lutpair13" *) - LUT3 #( - .INIT(8'h69)) - g0_b2_i_4__1 - (.I0(\TMDS_2/i_Enc/p_8_in ), - .I1(\TMDS_2/i_Enc/p_12_in ), - .I2(\TMDS_2/i_Enc/p_10_in ), - .O(g0_b2_i_4__1_n_0)); - LUT1 #( - .INIT(2'h1)) - i_ODDRE_N_i_1 - (.I0(\TMDS_0/D1 ), - .O(i_ODDRE_N_i_1_n_0)); - LUT1 #( - .INIT(2'h1)) - i_ODDRE_N_i_1__0 - (.I0(\TMDS_1/D1 ), - .O(i_ODDRE_N_i_1__0_n_0)); - LUT1 #( - .INIT(2'h1)) - i_ODDRE_N_i_1__1 - (.I0(\TMDS_2/D1 ), - .O(i_ODDRE_N_i_1__1_n_0)); - LUT1 #( - .INIT(2'h1)) - i_ODDRE_N_i_1__2 - (.I0(\TMDS_3/D1 ), - .O(i_ODDRE_N_i_1__2_n_0)); - (* SOFT_HLUTNM = "soft_lutpair39" *) - LUT1 #( - .INIT(2'h1)) - i_ODDRE_N_i_2 - (.I0(\TMDS_3/D2 ), - .O(i_ODDRE_N_i_2_n_0)); - LUT1 #( - .INIT(2'h1)) - i_ODDRE_N_i_2__0 - (.I0(\TMDS_0/D2 ), - .O(i_ODDRE_N_i_2__0_n_0)); - LUT1 #( - .INIT(2'h1)) - i_ODDRE_N_i_2__1 - (.I0(\TMDS_1/D2 ), - .O(i_ODDRE_N_i_2__1_n_0)); - LUT1 #( - .INIT(2'h1)) - i_ODDRE_N_i_2__2 - (.I0(\TMDS_2/D2 ), - .O(i_ODDRE_N_i_2__2_n_0)); - LUT1 #( - .INIT(2'h1)) - i_ODDRE_P_i_1 - (.I0(ResetN), - .O(\TMDS_3/Reset )); - LUT6 #( - .INIT(64'h9F90FFFF9F900000)) - \sReg[0]_i_1 - (.I0(\TMDS_0/i_Enc/qD_reg_n_0_ ), - .I1(\sReg[9]_i_2_n_0 ), - .I2(qDE), - .I3(qC1C0[0]), - .I4(\sReg[9]_i_3_n_0 ), - .I5(\TMDS_0/i_GBox/sReg_reg_n_0_ [2]), - .O(\sReg[0]_i_1_n_0 )); - LUT5 #( - .INIT(32'hC3AA00AA)) - \sReg[0]_i_1__0 - (.I0(\TMDS_1/i_GBox/sReg_reg_n_0_ [2]), - .I1(\TMDS_1/i_Enc/qD_reg_n_0_ ), - .I2(\sReg[9]_i_2__0_n_0 ), - .I3(\sReg[7]_i_4_n_0 ), - .I4(qDE), - .O(\sReg[0]_i_1__0_n_0 )); - LUT5 #( - .INIT(32'hC3AA00AA)) - \sReg[0]_i_1__1 - (.I0(\TMDS_2/i_GBox/sReg_reg_n_0_ [2]), - .I1(\TMDS_2/i_Enc/qD_reg_n_0_ ), - .I2(\sReg[9]_i_2__1_n_0 ), - .I3(\sReg[7]_i_3_n_0 ), - .I4(qDE), - .O(\sReg[0]_i_1__1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair39" *) - LUT4 #( - .INIT(16'hAABA)) - \sReg[0]_i_1__2 - (.I0(\TMDS_3/D2 ), - .I1(\TMDS_3/i_GBox/cntMod5_reg_n_0_ [2]), - .I2(\TMDS_3/i_GBox/cntMod5_reg_n_0_ [1]), - .I3(\TMDS_3/i_GBox/cntMod5_reg_n_0_ [0]), - .O(\sReg[0]_i_1__2_n_0 )); - LUT6 #( - .INIT(64'h00808880AAAAAAAA)) - \sReg[1]_i_1 - (.I0(\sReg[1]_i_2__0_n_0 ), - .I1(qDE), - .I2(\sReg[1]_i_3_n_0 ), - .I3(\Cnt[4]_i_6_n_0 ), - .I4(\sReg[1]_i_4_n_0 ), - .I5(\sReg[1]_i_5_n_0 ), - .O(\sReg[1]_i_1_n_0 )); - LUT5 #( - .INIT(32'hFFFB0008)) - \sReg[1]_i_1__0 - (.I0(\sReg[1]_i_2__1_n_0 ), - .I1(\TMDS_1/i_GBox/cntMod5_reg_n_0_ [1]), - .I2(\TMDS_1/i_GBox/cntMod5_reg_n_0_ [2]), - .I3(\TMDS_1/i_GBox/cntMod5_reg_n_0_ [0]), - .I4(\TMDS_1/i_GBox/sReg_reg_n_0_ [3]), - .O(\sReg[1]_i_1__0_n_0 )); - LUT6 #( - .INIT(64'hABAAA8AAA8AAA8AA)) - \sReg[1]_i_1__1 - (.I0(\TMDS_2/i_GBox/sReg_reg_n_0_ [3]), - .I1(\TMDS_2/i_GBox/cntMod5_reg_n_0_ [0]), - .I2(\TMDS_2/i_GBox/cntMod5_reg_n_0_ [2]), - .I3(\TMDS_2/i_GBox/cntMod5_reg_n_0_ [1]), - .I4(qDE), - .I5(\sReg[1]_i_2_n_0 ), - .O(\sReg[1]_i_1__1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair38" *) - LUT4 #( - .INIT(16'hAABA)) - \sReg[1]_i_1__2 - (.I0(\TMDS_3/i_GBox/sReg_reg_n_0_ ), - .I1(\TMDS_3/i_GBox/cntMod5_reg_n_0_ [2]), - .I2(\TMDS_3/i_GBox/cntMod5_reg_n_0_ [1]), - .I3(\TMDS_3/i_GBox/cntMod5_reg_n_0_ [0]), - .O(\sReg[1]_i_1__2_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair9" *) - LUT5 #( - .INIT(32'h609F9F60)) - \sReg[1]_i_2 - (.I0(g0_b2_i_1__1_n_0), - .I1(\Cnt[4]_i_4__1_n_0 ), - .I2(\Cnt[4]_i_6__0_n_0 ), - .I3(\TMDS_2/i_Enc/qD_reg_n_0_ ), - .I4(\TMDS_2/i_Enc/p_0_in ), - .O(\sReg[1]_i_2_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair35" *) - LUT4 #( - .INIT(16'hABAA)) - \sReg[1]_i_2__0 - (.I0(\TMDS_0/i_GBox/sReg_reg_n_0_ [3]), - .I1(\TMDS_0/i_GBox/cntMod5_reg_n_0_ [0]), - .I2(\TMDS_0/i_GBox/cntMod5_reg_n_0_ [2]), - .I3(\TMDS_0/i_GBox/cntMod5_reg_n_0_ [1]), - .O(\sReg[1]_i_2__0_n_0 )); - LUT6 #( - .INIT(64'h6696966600000000)) - \sReg[1]_i_2__1 - (.I0(\TMDS_1/i_Enc/p_0_in ), - .I1(\TMDS_1/i_Enc/qD_reg_n_0_ ), - .I2(\Cnt[4]_i_5__0_n_0 ), - .I3(\Cnt[4]_i_3__0_n_0 ), - .I4(g0_b2_i_1__0_n_0), - .I5(qDE), - .O(\sReg[1]_i_2__1_n_0 )); - LUT2 #( - .INIT(4'h6)) - \sReg[1]_i_3 - (.I0(\TMDS_0/i_Enc/qD_reg_n_0_ ), - .I1(\TMDS_0/i_Enc/p_0_in ), - .O(\sReg[1]_i_3_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair31" *) - LUT4 #( - .INIT(16'h6996)) - \sReg[1]_i_4 - (.I0(\TMDS_0/i_Enc/qD_reg_n_0_ ), - .I1(\TMDS_0/i_Enc/p_0_in ), - .I2(g0_b2_i_1_n_0), - .I3(\Cnt[4]_i_4_n_0 ), - .O(\sReg[1]_i_4_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair15" *) - LUT5 #( - .INIT(32'h10001010)) - \sReg[1]_i_5 - (.I0(\TMDS_0/i_GBox/cntMod5_reg_n_0_ [0]), - .I1(\TMDS_0/i_GBox/cntMod5_reg_n_0_ [2]), - .I2(\TMDS_0/i_GBox/cntMod5_reg_n_0_ [1]), - .I3(qDE), - .I4(qC1C0[0]), - .O(\sReg[1]_i_5_n_0 )); - LUT6 #( - .INIT(64'h606FFFFF606F0000)) - \sReg[2]_i_1 - (.I0(\sReg[2]_i_2_n_0 ), - .I1(\sReg[9]_i_2_n_0 ), - .I2(qDE), - .I3(qC1C0[0]), - .I4(\sReg[9]_i_3_n_0 ), - .I5(\TMDS_0/i_GBox/sReg_reg_n_0_ [4]), - .O(\sReg[2]_i_1_n_0 )); - LUT5 #( - .INIT(32'h3AFAFA3A)) - \sReg[2]_i_1__0 - (.I0(\TMDS_1/i_GBox/sReg_reg_n_0_ [4]), - .I1(qDE), - .I2(\sReg[7]_i_4_n_0 ), - .I3(\sReg[2]_i_2__0_n_0 ), - .I4(\sReg[9]_i_2__0_n_0 ), - .O(\sReg[2]_i_1__0_n_0 )); - LUT5 #( - .INIT(32'h3CFFAAAA)) - \sReg[2]_i_1__1 - (.I0(\TMDS_2/i_GBox/sReg_reg_n_0_ [4]), - .I1(\sReg[9]_i_2__1_n_0 ), - .I2(\sReg[2]_i_2__1_n_0 ), - .I3(qDE), - .I4(\sReg[7]_i_3_n_0 ), - .O(\sReg[2]_i_1__1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair31" *) - LUT3 #( - .INIT(8'h69)) - \sReg[2]_i_2 - (.I0(\TMDS_0/i_Enc/p_2_in ), - .I1(\TMDS_0/i_Enc/p_0_in ), - .I2(\TMDS_0/i_Enc/qD_reg_n_0_ ), - .O(\sReg[2]_i_2_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair43" *) - LUT3 #( - .INIT(8'h69)) - \sReg[2]_i_2__0 - (.I0(\TMDS_1/i_Enc/p_2_in ), - .I1(\TMDS_1/i_Enc/p_0_in ), - .I2(\TMDS_1/i_Enc/qD_reg_n_0_ ), - .O(\sReg[2]_i_2__0_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair42" *) - LUT3 #( - .INIT(8'h69)) - \sReg[2]_i_2__1 - (.I0(\TMDS_2/i_Enc/p_2_in ), - .I1(\TMDS_2/i_Enc/p_0_in ), - .I2(\TMDS_2/i_Enc/qD_reg_n_0_ ), - .O(\sReg[2]_i_2__1_n_0 )); - LUT6 #( - .INIT(64'hBFBFAFFFAAAAAAAA)) - \sReg[3]_i_1 - (.I0(\sReg[3]_i_2__1_n_0 ), - .I1(\sReg[3]_i_3_n_0 ), - .I2(qDE), - .I3(\sReg[3]_i_4_n_0 ), - .I4(\Cnt[4]_i_6_n_0 ), - .I5(\sReg[5]_i_5_n_0 ), - .O(\sReg[3]_i_1_n_0 )); - LUT6 #( - .INIT(64'hAAA3AAAAAAA0AAAA)) - \sReg[3]_i_1__0 - (.I0(\TMDS_1/i_GBox/sReg_reg_n_0_ [5]), - .I1(\sReg[3]_i_2_n_0 ), - .I2(\TMDS_1/i_GBox/cntMod5_reg_n_0_ [0]), - .I3(\TMDS_1/i_GBox/cntMod5_reg_n_0_ [2]), - .I4(\TMDS_1/i_GBox/cntMod5_reg_n_0_ [1]), - .I5(qDE), - .O(\sReg[3]_i_1__0_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair7" *) - LUT5 #( - .INIT(32'hFFFB0008)) - \sReg[3]_i_1__1 - (.I0(\sReg[3]_i_2__0_n_0 ), - .I1(\TMDS_2/i_GBox/cntMod5_reg_n_0_ [1]), - .I2(\TMDS_2/i_GBox/cntMod5_reg_n_0_ [2]), - .I3(\TMDS_2/i_GBox/cntMod5_reg_n_0_ [0]), - .I4(\TMDS_2/i_GBox/sReg_reg_n_0_ [5]), - .O(\sReg[3]_i_1__1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair38" *) - LUT3 #( - .INIT(8'h04)) - \sReg[3]_i_1__2 - (.I0(\TMDS_3/i_GBox/cntMod5_reg_n_0_ [0]), - .I1(\TMDS_3/i_GBox/cntMod5_reg_n_0_ [1]), - .I2(\TMDS_3/i_GBox/cntMod5_reg_n_0_ [2]), - .O(\sReg[3]_i_1__2_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair3" *) - LUT5 #( - .INIT(32'h609F9F60)) - \sReg[3]_i_2 - (.I0(g0_b2_i_1__0_n_0), - .I1(\Cnt[4]_i_3__0_n_0 ), - .I2(\Cnt[4]_i_5__0_n_0 ), - .I3(\TMDS_1/i_Enc/p_4_in ), - .I4(\sReg[2]_i_2__0_n_0 ), - .O(\sReg[3]_i_2_n_0 )); - LUT6 #( - .INIT(64'h8282288228828282)) - \sReg[3]_i_2__0 - (.I0(qDE), - .I1(\TMDS_2/i_Enc/p_4_in ), - .I2(\sReg[2]_i_2__1_n_0 ), - .I3(\Cnt[4]_i_6__0_n_0 ), - .I4(\Cnt[4]_i_4__1_n_0 ), - .I5(g0_b2_i_1__1_n_0), - .O(\sReg[3]_i_2__0_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair35" *) - LUT4 #( - .INIT(16'hA8AA)) - \sReg[3]_i_2__1 - (.I0(\TMDS_0/i_GBox/sReg_reg_n_0_ [5]), - .I1(\TMDS_0/i_GBox/cntMod5_reg_n_0_ [0]), - .I2(\TMDS_0/i_GBox/cntMod5_reg_n_0_ [2]), - .I3(\TMDS_0/i_GBox/cntMod5_reg_n_0_ [1]), - .O(\sReg[3]_i_2__1_n_0 )); - LUT6 #( - .INIT(64'h6996966996696996)) - \sReg[3]_i_3 - (.I0(\TMDS_0/i_Enc/p_4_in ), - .I1(\TMDS_0/i_Enc/qD_reg_n_0_ ), - .I2(\TMDS_0/i_Enc/p_0_in ), - .I3(\TMDS_0/i_Enc/p_2_in ), - .I4(g0_b2_i_1_n_0), - .I5(\Cnt[4]_i_4_n_0 ), - .O(\sReg[3]_i_3_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair37" *) - LUT4 #( - .INIT(16'h9669)) - \sReg[3]_i_4 - (.I0(\TMDS_0/i_Enc/p_4_in ), - .I1(\TMDS_0/i_Enc/qD_reg_n_0_ ), - .I2(\TMDS_0/i_Enc/p_0_in ), - .I3(\TMDS_0/i_Enc/p_2_in ), - .O(\sReg[3]_i_4_n_0 )); - LUT6 #( - .INIT(64'h909FFFFF909F0000)) - \sReg[4]_i_1 - (.I0(g0_b2_i_2__0_n_0), - .I1(\sReg[9]_i_2_n_0 ), - .I2(qDE), - .I3(qC1C0[0]), - .I4(\sReg[9]_i_3_n_0 ), - .I5(\TMDS_0/i_GBox/sReg_reg_n_0_ [6]), - .O(\sReg[4]_i_1_n_0 )); - LUT5 #( - .INIT(32'hC3AAFFAA)) - \sReg[4]_i_1__0 - (.I0(\TMDS_1/i_GBox/sReg_reg_n_0_ [6]), - .I1(g0_b2_i_2__1_n_0), - .I2(\sReg[9]_i_2__0_n_0 ), - .I3(\sReg[7]_i_4_n_0 ), - .I4(qDE), - .O(\sReg[4]_i_1__0_n_0 )); - LUT5 #( - .INIT(32'hC3FFAAAA)) - \sReg[4]_i_1__1 - (.I0(\TMDS_2/i_GBox/sReg_reg_n_0_ [6]), - .I1(\sReg[9]_i_2__1_n_0 ), - .I2(\TMDS_2/i_Enc/p_9_in ), - .I3(qDE), - .I4(\sReg[7]_i_3_n_0 ), - .O(\sReg[4]_i_1__1_n_0 )); - LUT6 #( - .INIT(64'hEFEFAFFFAAAAAAAA)) - \sReg[5]_i_1 - (.I0(\sReg[5]_i_2__1_n_0 ), - .I1(\sReg[5]_i_3_n_0 ), - .I2(qDE), - .I3(\sReg[5]_i_4_n_0 ), - .I4(\Cnt[4]_i_6_n_0 ), - .I5(\sReg[5]_i_5_n_0 ), - .O(\sReg[5]_i_1_n_0 )); - LUT5 #( - .INIT(32'hFFFB0008)) - \sReg[5]_i_1__0 - (.I0(\sReg[5]_i_2_n_0 ), - .I1(\TMDS_1/i_GBox/cntMod5_reg_n_0_ [1]), - .I2(\TMDS_1/i_GBox/cntMod5_reg_n_0_ [2]), - .I3(\TMDS_1/i_GBox/cntMod5_reg_n_0_ [0]), - .I4(\TMDS_1/i_GBox/sReg_reg_n_0_ [7]), - .O(\sReg[5]_i_1__0_n_0 )); - LUT5 #( - .INIT(32'hFFFB0008)) - \sReg[5]_i_1__1 - (.I0(\sReg[5]_i_2__0_n_0 ), - .I1(\TMDS_2/i_GBox/cntMod5_reg_n_0_ [1]), - .I2(\TMDS_2/i_GBox/cntMod5_reg_n_0_ [2]), - .I3(\TMDS_2/i_GBox/cntMod5_reg_n_0_ [0]), - .I4(\TMDS_2/i_GBox/sReg_reg_n_0_ [7]), - .O(\sReg[5]_i_1__1_n_0 )); - LUT6 #( - .INIT(64'h2828822882282828)) - \sReg[5]_i_2 - (.I0(qDE), - .I1(\TMDS_1/i_Enc/p_8_in ), - .I2(g0_b2_i_2__1_n_0), - .I3(\Cnt[4]_i_5__0_n_0 ), - .I4(\Cnt[4]_i_3__0_n_0 ), - .I5(g0_b2_i_1__0_n_0), - .O(\sReg[5]_i_2_n_0 )); - LUT6 #( - .INIT(64'h2828822882282828)) - \sReg[5]_i_2__0 - (.I0(qDE), - .I1(\TMDS_2/i_Enc/p_9_in ), - .I2(\TMDS_2/i_Enc/p_8_in ), - .I3(\Cnt[4]_i_6__0_n_0 ), - .I4(\Cnt[4]_i_4__1_n_0 ), - .I5(g0_b2_i_1__1_n_0), - .O(\sReg[5]_i_2__0_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair36" *) - LUT4 #( - .INIT(16'hA8AA)) - \sReg[5]_i_2__1 - (.I0(\TMDS_0/i_GBox/sReg_reg_n_0_ [7]), - .I1(\TMDS_0/i_GBox/cntMod5_reg_n_0_ [0]), - .I2(\TMDS_0/i_GBox/cntMod5_reg_n_0_ [2]), - .I3(\TMDS_0/i_GBox/cntMod5_reg_n_0_ [1]), - .O(\sReg[5]_i_2__1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair30" *) - LUT4 #( - .INIT(16'h9669)) - \sReg[5]_i_3 - (.I0(\TMDS_0/i_Enc/p_8_in ), - .I1(g0_b2_i_2__0_n_0), - .I2(g0_b2_i_1_n_0), - .I3(\Cnt[4]_i_4_n_0 ), - .O(\sReg[5]_i_3_n_0 )); - LUT6 #( - .INIT(64'h9669699669969669)) - \sReg[5]_i_4 - (.I0(\TMDS_0/i_Enc/p_8_in ), - .I1(\TMDS_0/i_Enc/p_4_in ), - .I2(\TMDS_0/i_Enc/qD_reg_n_0_ ), - .I3(\TMDS_0/i_Enc/p_0_in ), - .I4(\TMDS_0/i_Enc/p_2_in ), - .I5(\TMDS_0/i_Enc/p_6_in ), - .O(\sReg[5]_i_4_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair15" *) - LUT5 #( - .INIT(32'h10101000)) - \sReg[5]_i_5 - (.I0(\TMDS_0/i_GBox/cntMod5_reg_n_0_ [0]), - .I1(\TMDS_0/i_GBox/cntMod5_reg_n_0_ [2]), - .I2(\TMDS_0/i_GBox/cntMod5_reg_n_0_ [1]), - .I3(qC1C0[0]), - .I4(qDE), - .O(\sReg[5]_i_5_n_0 )); - LUT6 #( - .INIT(64'h909FFFFF909F0000)) - \sReg[6]_i_1 - (.I0(\sReg[6]_i_2__0_n_0 ), - .I1(\sReg[9]_i_2_n_0 ), - .I2(qDE), - .I3(qC1C0[0]), - .I4(\sReg[9]_i_3_n_0 ), - .I5(\TMDS_0/i_GBox/sReg_reg_n_0_ [8]), - .O(\sReg[6]_i_1_n_0 )); - LUT6 #( - .INIT(64'h3CC3AAAAFFFFAAAA)) - \sReg[6]_i_1__0 - (.I0(\TMDS_1/i_GBox/sReg_reg_n_0_ [8]), - .I1(\sReg[6]_i_2_n_0 ), - .I2(\TMDS_1/i_Enc/p_10_in ), - .I3(\sReg[9]_i_2__0_n_0 ), - .I4(\sReg[7]_i_4_n_0 ), - .I5(qDE), - .O(\sReg[6]_i_1__0_n_0 )); - LUT6 #( - .INIT(64'h96FFFFFF96FF0000)) - \sReg[6]_i_1__1 - (.I0(\sReg[9]_i_2__1_n_0 ), - .I1(\TMDS_2/i_Enc/p_10_in ), - .I2(\sReg[6]_i_2__1_n_0 ), - .I3(qDE), - .I4(\sReg[7]_i_3_n_0 ), - .I5(\TMDS_2/i_GBox/sReg_reg_n_0_ [8]), - .O(\sReg[6]_i_1__1_n_0 )); - LUT6 #( - .INIT(64'h6996966996696996)) - \sReg[6]_i_2 - (.I0(\TMDS_1/i_Enc/p_8_in ), - .I1(\TMDS_1/i_Enc/p_4_in ), - .I2(\TMDS_1/i_Enc/qD_reg_n_0_ ), - .I3(\TMDS_1/i_Enc/p_0_in ), - .I4(\TMDS_1/i_Enc/p_2_in ), - .I5(\TMDS_1/i_Enc/p_6_in ), - .O(\sReg[6]_i_2_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair30" *) - LUT3 #( - .INIT(8'h96)) - \sReg[6]_i_2__0 - (.I0(\TMDS_0/i_Enc/p_10_in ), - .I1(g0_b2_i_2__0_n_0), - .I2(\TMDS_0/i_Enc/p_8_in ), - .O(\sReg[6]_i_2__0_n_0 )); - LUT6 #( - .INIT(64'h9669699669969669)) - \sReg[6]_i_2__1 - (.I0(\TMDS_2/i_Enc/p_8_in ), - .I1(\TMDS_2/i_Enc/p_4_in ), - .I2(\TMDS_2/i_Enc/qD_reg_n_0_ ), - .I3(\TMDS_2/i_Enc/p_0_in ), - .I4(\TMDS_2/i_Enc/p_2_in ), - .I5(\TMDS_2/i_Enc/p_6_in ), - .O(\sReg[6]_i_2__1_n_0 )); - LUT6 #( - .INIT(64'h3FF3AAAA0CC0AAAA)) - \sReg[7]_i_1 - (.I0(\TMDS_0/i_GBox/sReg_reg_n_0_ [9]), - .I1(qDE), - .I2(\sReg[7]_i_2__0_n_0 ), - .I3(\sReg[9]_i_2_n_0 ), - .I4(\sReg[9]_i_3_n_0 ), - .I5(qC1C0[0]), - .O(\sReg[7]_i_1_n_0 )); - LUT6 #( - .INIT(64'h8228FFFF82280000)) - \sReg[7]_i_1__0 - (.I0(qDE), - .I1(\sReg[9]_i_2__0_n_0 ), - .I2(\sReg[7]_i_2_n_0 ), - .I3(\sReg[7]_i_3__0_n_0 ), - .I4(\sReg[7]_i_4_n_0 ), - .I5(\TMDS_1/i_GBox/sReg_reg_n_0_ [9]), - .O(\sReg[7]_i_1__0_n_0 )); - LUT5 #( - .INIT(32'h82FF8200)) - \sReg[7]_i_1__1 - (.I0(qDE), - .I1(\sReg[9]_i_2__1_n_0 ), - .I2(\sReg[7]_i_2__1_n_0 ), - .I3(\sReg[7]_i_3_n_0 ), - .I4(\TMDS_2/i_GBox/sReg_reg_n_0_ [9]), - .O(\sReg[7]_i_1__1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair4" *) - LUT2 #( - .INIT(4'h6)) - \sReg[7]_i_2 - (.I0(\TMDS_1/i_Enc/p_10_in ), - .I1(\TMDS_1/i_Enc/p_12_in ), - .O(\sReg[7]_i_2_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair14" *) - LUT5 #( - .INIT(32'h96696996)) - \sReg[7]_i_2__0 - (.I0(\TMDS_0/i_Enc/p_12_in ), - .I1(\TMDS_0/i_Enc/p_10_in ), - .I2(\TMDS_0/i_Enc/p_8_in ), - .I3(g0_b2_i_2__0_n_0), - .I4(g0_b2_i_1_n_0), - .O(\sReg[7]_i_2__0_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair13" *) - LUT5 #( - .INIT(32'h96696996)) - \sReg[7]_i_2__1 - (.I0(\TMDS_2/i_Enc/p_12_in ), - .I1(\TMDS_2/i_Enc/p_10_in ), - .I2(\TMDS_2/i_Enc/p_8_in ), - .I3(\TMDS_2/i_Enc/p_9_in ), - .I4(g0_b2_i_1__1_n_0), - .O(\sReg[7]_i_2__1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair7" *) - LUT3 #( - .INIT(8'h02)) - \sReg[7]_i_3 - (.I0(\TMDS_2/i_GBox/cntMod5_reg_n_0_ [1]), - .I1(\TMDS_2/i_GBox/cntMod5_reg_n_0_ [2]), - .I2(\TMDS_2/i_GBox/cntMod5_reg_n_0_ [0]), - .O(\sReg[7]_i_3_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair33" *) - LUT3 #( - .INIT(8'h69)) - \sReg[7]_i_3__0 - (.I0(g0_b2_i_1__0_n_0), - .I1(g0_b2_i_2__1_n_0), - .I2(\TMDS_1/i_Enc/p_8_in ), - .O(\sReg[7]_i_3__0_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair2" *) - LUT3 #( - .INIT(8'h02)) - \sReg[7]_i_4 - (.I0(\TMDS_1/i_GBox/cntMod5_reg_n_0_ [1]), - .I1(\TMDS_1/i_GBox/cntMod5_reg_n_0_ [2]), - .I2(\TMDS_1/i_GBox/cntMod5_reg_n_0_ [0]), - .O(\sReg[7]_i_4_n_0 )); - LUT6 #( - .INIT(64'h000C000000040004)) - \sReg[8]_i_1 - (.I0(qC1C0[0]), - .I1(\TMDS_0/i_GBox/cntMod5_reg_n_0_ [1]), - .I2(\TMDS_0/i_GBox/cntMod5_reg_n_0_ [2]), - .I3(\TMDS_0/i_GBox/cntMod5_reg_n_0_ [0]), - .I4(g0_b2_i_1_n_0), - .I5(qDE), - .O(\sReg[8]_i_1_n_0 )); - LUT5 #( - .INIT(32'h00101010)) - \sReg[8]_i_1__0 - (.I0(\TMDS_1/i_GBox/cntMod5_reg_n_0_ [0]), - .I1(\TMDS_1/i_GBox/cntMod5_reg_n_0_ [2]), - .I2(\TMDS_1/i_GBox/cntMod5_reg_n_0_ [1]), - .I3(qDE), - .I4(g0_b2_i_1__0_n_0), - .O(\sReg[8]_i_1__0_n_0 )); - LUT5 #( - .INIT(32'h00101010)) - \sReg[8]_i_1__1 - (.I0(\TMDS_2/i_GBox/cntMod5_reg_n_0_ [0]), - .I1(\TMDS_2/i_GBox/cntMod5_reg_n_0_ [2]), - .I2(\TMDS_2/i_GBox/cntMod5_reg_n_0_ [1]), - .I3(qDE), - .I4(g0_b2_i_1__1_n_0), - .O(\sReg[8]_i_1__1_n_0 )); - LUT5 #( - .INIT(32'h4C40404C)) - \sReg[9]_i_1 - (.I0(\sReg[9]_i_2_n_0 ), - .I1(\sReg[9]_i_3_n_0 ), - .I2(qDE), - .I3(qC1C0[1]), - .I4(qC1C0[0]), - .O(\sReg[9]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair2" *) - LUT5 #( - .INIT(32'h00070000)) - \sReg[9]_i_1__0 - (.I0(\sReg[9]_i_2__0_n_0 ), - .I1(qDE), - .I2(\TMDS_1/i_GBox/cntMod5_reg_n_0_ [0]), - .I3(\TMDS_1/i_GBox/cntMod5_reg_n_0_ [2]), - .I4(\TMDS_1/i_GBox/cntMod5_reg_n_0_ [1]), - .O(\sReg[9]_i_1__0_n_0 )); - LUT5 #( - .INIT(32'h00070000)) - \sReg[9]_i_1__1 - (.I0(\sReg[9]_i_2__1_n_0 ), - .I1(qDE), - .I2(\TMDS_2/i_GBox/cntMod5_reg_n_0_ [0]), - .I3(\TMDS_2/i_GBox/cntMod5_reg_n_0_ [2]), - .I4(\TMDS_2/i_GBox/cntMod5_reg_n_0_ [1]), - .O(\sReg[9]_i_1__1_n_0 )); - LUT5 #( - .INIT(32'hFFD50015)) - \sReg[9]_i_2 - (.I0(\Cnt[4]_i_4_n_0 ), - .I1(\Cnt[4]_i_10__1_n_0 ), - .I2(\Cnt[4]_i_11_n_0 ), - .I3(\sReg[9]_i_4_n_0 ), - .I4(g0_b2_i_1_n_0), - .O(\sReg[9]_i_2_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair3" *) - LUT3 #( - .INIT(8'h47)) - \sReg[9]_i_2__0 - (.I0(\Cnt[4]_i_3__0_n_0 ), - .I1(\Cnt[4]_i_5__0_n_0 ), - .I2(g0_b2_i_1__0_n_0), - .O(\sReg[9]_i_2__0_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair9" *) - LUT3 #( - .INIT(8'h47)) - \sReg[9]_i_2__1 - (.I0(\Cnt[4]_i_4__1_n_0 ), - .I1(\Cnt[4]_i_6__0_n_0 ), - .I2(g0_b2_i_1__1_n_0), - .O(\sReg[9]_i_2__1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair36" *) - LUT3 #( - .INIT(8'h02)) - \sReg[9]_i_3 - (.I0(\TMDS_0/i_GBox/cntMod5_reg_n_0_ [1]), - .I1(\TMDS_0/i_GBox/cntMod5_reg_n_0_ [2]), - .I2(\TMDS_0/i_GBox/cntMod5_reg_n_0_ [0]), - .O(\sReg[9]_i_3_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair34" *) - LUT4 #( - .INIT(16'h0001)) - \sReg[9]_i_4 - (.I0(\TMDS_0/i_Enc/Cnt_reg_n_0_ [4]), - .I1(\TMDS_0/i_Enc/Cnt_reg_n_0_ [1]), - .I2(\TMDS_0/i_Enc/Cnt_reg_n_0_ [2]), - .I3(\TMDS_0/i_Enc/Cnt_reg_n_0_ [3]), - .O(\sReg[9]_i_4_n_0 )); -endmodule - -module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_HDMI_TX_wrap - (HDMI_D0_P, - HDMI_D0_N, - HDMI_D1_P, - HDMI_D1_N, - HDMI_D2_P, - HDMI_D2_N, - HDMI_CK_P, - HDMI_CK_N, - pxClk, - pxClkX5, - ResetN, - DE, - HSync, - VSync, - R, - G, - B); - output HDMI_D0_P; - output HDMI_D0_N; - output HDMI_D1_P; - output HDMI_D1_N; - output HDMI_D2_P; - output HDMI_D2_N; - output HDMI_CK_P; - output HDMI_CK_N; - input pxClk; - input pxClkX5; - input ResetN; - input DE; - input HSync; - input VSync; - input [7:0]R; - input [7:0]G; - input [7:0]B; - - wire [7:0]B; - wire DE; - wire [7:0]G; - wire HDMI_CK_N; - wire HDMI_CK_P; - wire HDMI_D0_N; - wire HDMI_D0_P; - wire HDMI_D1_N; - wire HDMI_D1_P; - wire HDMI_D2_N; - wire HDMI_D2_P; - wire HSync; - wire [7:0]R; - wire ResetN; - wire VSync; - wire pxClk; - wire pxClkX5; - - decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_HDMI_TX i_wrap - (.B(B), - .DE(DE), - .G(G), - .HDMI_CK_N(HDMI_CK_N), - .HDMI_CK_P(HDMI_CK_P), - .HDMI_D0_N(HDMI_D0_N), - .HDMI_D0_P(HDMI_D0_P), - .HDMI_D1_N(HDMI_D1_N), - .HDMI_D1_P(HDMI_D1_P), - .HDMI_D2_N(HDMI_D2_N), - .HDMI_D2_P(HDMI_D2_P), - .HSync(HSync), - .R(R), - .ResetN(ResetN), - .VSync(VSync), - .pxClk(pxClk), - .pxClkX5(pxClkX5)); -endmodule - -(* CHECK_LICENSE_TYPE = "design_1_HDMI_TX_0_0,HDMI_TX_wrap,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) -(* x_core_info = "HDMI_TX_wrap,Vivado 2025.1" *) -(* NotValidForBitStream *) -module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix - (pxClk, - pxClkX5, - ResetN, - DE, - HSync, - VSync, - R, - G, - B, - HDMI_D0_P, - HDMI_D0_N, - HDMI_D1_P, - HDMI_D1_N, - HDMI_D2_P, - HDMI_D2_N, - HDMI_CK_P, - HDMI_CK_N); - input pxClk; - input pxClkX5; - input ResetN; - input DE; - input HSync; - input VSync; - input [7:0]R; - input [7:0]G; - input [7:0]B; - output HDMI_D0_P; - output HDMI_D0_N; - output HDMI_D1_P; - output HDMI_D1_N; - output HDMI_D2_P; - output HDMI_D2_N; - output HDMI_CK_P; - output HDMI_CK_N; - - wire [7:0]B; - wire DE; - wire [7:0]G; - wire HDMI_CK_N; - wire HDMI_CK_P; - wire HDMI_D0_N; - wire HDMI_D0_P; - wire HDMI_D1_N; - wire HDMI_D1_P; - wire HDMI_D2_N; - wire HDMI_D2_P; - wire HSync; - wire [7:0]R; - wire ResetN; - wire VSync; - wire pxClk; - wire pxClkX5; - - decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_HDMI_TX_wrap U0 - (.B(B), - .DE(DE), - .G(G), - .HDMI_CK_N(HDMI_CK_N), - .HDMI_CK_P(HDMI_CK_P), - .HDMI_D0_N(HDMI_D0_N), - .HDMI_D0_P(HDMI_D0_P), - .HDMI_D1_N(HDMI_D1_N), - .HDMI_D1_P(HDMI_D1_P), - .HDMI_D2_N(HDMI_D2_N), - .HDMI_D2_P(HDMI_D2_P), - .HSync(HSync), - .R(R), - .ResetN(ResetN), - .VSync(VSync), - .pxClk(pxClk), - .pxClkX5(pxClkX5)); -endmodule -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - parameter GRES_WIDTH = 10000; - parameter GRES_START = 10000; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - wire GRESTORE; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - reg GRESTORE_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - assign (strong1, weak0) GRESTORE = GRESTORE_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - - initial begin - GRESTORE_int = 1'b0; - #(GRES_START); - GRESTORE_int = 1'b1; - #(GRES_WIDTH); - GRESTORE_int = 1'b0; - end - -endmodule -`endif diff --git a/SW2.cache/ip/2025.1/5/b/5be5567f865f5e2e/design_1_HDMI_TX_0_0_sim_netlist.vhdl b/SW2.cache/ip/2025.1/5/b/5be5567f865f5e2e/design_1_HDMI_TX_0_0_sim_netlist.vhdl deleted file mode 100644 index ef0cb1f..0000000 --- a/SW2.cache/ip/2025.1/5/b/5be5567f865f5e2e/design_1_HDMI_TX_0_0_sim_netlist.vhdl +++ /dev/null @@ -1,4178 +0,0 @@ --- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. --- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2025.1 (win64) Build 6140274 Thu May 22 00:12:29 MDT 2025 --- Date : Tue Apr 28 14:09:27 2026 --- Host : Lab016-05 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix --- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_HDMI_TX_0_0_sim_netlist.vhdl --- Design : design_1_HDMI_TX_0_0 --- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or --- synthesized. This netlist cannot be used for SDF annotated simulation. --- Device : xczu3eg-sfvc784-2-e --- -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_HDMI_TX is - port ( - DE : in STD_LOGIC; - HDMI_CK_N : out STD_LOGIC; - HDMI_CK_P : out STD_LOGIC; - HDMI_D0_N : out STD_LOGIC; - HDMI_D0_P : out STD_LOGIC; - HDMI_D1_N : out STD_LOGIC; - HDMI_D1_P : out STD_LOGIC; - HDMI_D2_N : out STD_LOGIC; - HDMI_D2_P : out STD_LOGIC; - HSync : in STD_LOGIC; - ResetN : in STD_LOGIC; - VSync : in STD_LOGIC; - pxClk : in STD_LOGIC; - pxClkX5 : in STD_LOGIC; - B : in STD_LOGIC_VECTOR ( 7 downto 0 ); - G : in STD_LOGIC_VECTOR ( 7 downto 0 ); - R : in STD_LOGIC_VECTOR ( 7 downto 0 ) - ); -end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_HDMI_TX; - -architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_HDMI_TX is - signal \Cnt[1]_i_1__0_n_0\ : STD_LOGIC; - signal \Cnt[1]_i_1__1_n_0\ : STD_LOGIC; - signal \Cnt[1]_i_1_n_0\ : STD_LOGIC; - signal \Cnt[1]_i_2__0_n_0\ : STD_LOGIC; - signal \Cnt[1]_i_2_n_0\ : STD_LOGIC; - signal \Cnt[2]_i_1_n_0\ : STD_LOGIC; - signal \Cnt[2]_i_2__0_n_0\ : STD_LOGIC; - signal \Cnt[2]_i_2__1_n_0\ : STD_LOGIC; - signal \Cnt[2]_i_2_n_0\ : STD_LOGIC; - signal \Cnt[2]_i_3__0_n_0\ : STD_LOGIC; - signal \Cnt[2]_i_3__1_n_0\ : STD_LOGIC; - signal \Cnt[2]_i_3_n_0\ : STD_LOGIC; - signal \Cnt[2]_i_4_n_0\ : STD_LOGIC; - signal \Cnt[2]_i_5_n_0\ : STD_LOGIC; - signal \Cnt[3]_i_1__0_n_0\ : STD_LOGIC; - signal \Cnt[3]_i_1_n_0\ : STD_LOGIC; - signal \Cnt[3]_i_2__0_n_0\ : STD_LOGIC; - signal \Cnt[3]_i_2__1_n_0\ : STD_LOGIC; - signal \Cnt[3]_i_2_n_0\ : STD_LOGIC; - signal \Cnt[3]_i_3__0_n_0\ : STD_LOGIC; - signal \Cnt[3]_i_3__1_n_0\ : STD_LOGIC; - signal \Cnt[3]_i_3_n_0\ : STD_LOGIC; - signal \Cnt[3]_i_4__0_n_0\ : STD_LOGIC; - signal \Cnt[3]_i_4__1_n_0\ : STD_LOGIC; - signal \Cnt[3]_i_4_n_0\ : STD_LOGIC; - signal \Cnt[3]_i_5__0_n_0\ : STD_LOGIC; - signal \Cnt[3]_i_5__1_n_0\ : STD_LOGIC; - signal \Cnt[3]_i_5_n_0\ : STD_LOGIC; - signal \Cnt[3]_i_6__0_n_0\ : STD_LOGIC; - signal \Cnt[3]_i_6_n_0\ : STD_LOGIC; - signal \Cnt[3]_i_7_n_0\ : STD_LOGIC; - signal \Cnt[3]_i_8_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_10__0_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_10__1_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_10_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_11__0_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_11__1_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_11_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_12__0_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_12__1_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_12_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_13__0_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_13__1_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_13_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_14__0_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_14__1_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_14_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_15__0_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_15__1_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_15_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_16__0_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_16__1_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_16_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_17__0_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_17_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_18__0_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_18_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_19__0_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_19_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_1__0_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_1__1_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_1_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_20__0_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_20_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_21__0_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_21_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_22_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_23_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_24_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_25_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_2__0_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_2__1_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_2_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_3__0_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_3__1_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_3_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_4__0_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_4__1_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_4_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_5__0_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_5__1_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_5_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_6__0_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_6__1_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_6_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_7__0_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_7__1_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_7_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_8__0_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_8__1_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_8_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_9__0_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_9__1_n_0\ : STD_LOGIC; - signal \Cnt[4]_i_9_n_0\ : STD_LOGIC; - signal \Cnt_reg[2]_i_1__0_n_0\ : STD_LOGIC; - signal \Cnt_reg[2]_i_1_n_0\ : STD_LOGIC; - signal \Cnt_reg[3]_i_1_n_0\ : STD_LOGIC; - signal \TMDS_0/D1\ : STD_LOGIC; - signal \TMDS_0/D2\ : STD_LOGIC; - signal \TMDS_0/i_Enc/Cnt_reg_n_0_\ : STD_LOGIC_VECTOR ( 4 downto 1 ); - signal \TMDS_0/i_Enc/p_0_in\ : STD_LOGIC; - signal \TMDS_0/i_Enc/p_10_in\ : STD_LOGIC; - signal \TMDS_0/i_Enc/p_12_in\ : STD_LOGIC; - signal \TMDS_0/i_Enc/p_2_in\ : STD_LOGIC; - signal \TMDS_0/i_Enc/p_4_in\ : STD_LOGIC; - signal \TMDS_0/i_Enc/p_6_in\ : STD_LOGIC; - signal \TMDS_0/i_Enc/p_8_in\ : STD_LOGIC; - signal \TMDS_0/i_Enc/qD_reg_n_0_\ : STD_LOGIC_VECTOR ( 0 to 0 ); - signal \TMDS_0/i_GBox/cntMod5_reg_n_0_\ : STD_LOGIC_VECTOR ( 2 downto 0 ); - signal \TMDS_0/i_GBox/sReg_reg_n_0_\ : STD_LOGIC_VECTOR ( 9 downto 2 ); - signal \TMDS_1/D1\ : STD_LOGIC; - signal \TMDS_1/D2\ : STD_LOGIC; - signal \TMDS_1/i_Enc/Cnt_reg_n_0_\ : STD_LOGIC_VECTOR ( 4 downto 1 ); - signal \TMDS_1/i_Enc/p_0_in\ : STD_LOGIC; - signal \TMDS_1/i_Enc/p_10_in\ : STD_LOGIC; - signal \TMDS_1/i_Enc/p_12_in\ : STD_LOGIC; - signal \TMDS_1/i_Enc/p_2_in\ : STD_LOGIC; - signal \TMDS_1/i_Enc/p_4_in\ : STD_LOGIC; - signal \TMDS_1/i_Enc/p_6_in\ : STD_LOGIC; - signal \TMDS_1/i_Enc/p_8_in\ : STD_LOGIC; - signal \TMDS_1/i_Enc/qD_reg_n_0_\ : STD_LOGIC_VECTOR ( 0 to 0 ); - signal \TMDS_1/i_GBox/cntMod5_reg_n_0_\ : STD_LOGIC_VECTOR ( 2 downto 0 ); - signal \TMDS_1/i_GBox/sReg_reg_n_0_\ : STD_LOGIC_VECTOR ( 9 downto 2 ); - signal \TMDS_2/D1\ : STD_LOGIC; - signal \TMDS_2/D2\ : STD_LOGIC; - signal \TMDS_2/i_Enc/Cnt_reg_n_0_\ : STD_LOGIC_VECTOR ( 4 downto 1 ); - signal \TMDS_2/i_Enc/p_0_in\ : STD_LOGIC; - signal \TMDS_2/i_Enc/p_10_in\ : STD_LOGIC; - signal \TMDS_2/i_Enc/p_12_in\ : STD_LOGIC; - signal \TMDS_2/i_Enc/p_2_in\ : STD_LOGIC; - signal \TMDS_2/i_Enc/p_4_in\ : STD_LOGIC; - signal \TMDS_2/i_Enc/p_6_in\ : STD_LOGIC; - signal \TMDS_2/i_Enc/p_8_in\ : STD_LOGIC; - signal \TMDS_2/i_Enc/p_9_in\ : STD_LOGIC; - signal \TMDS_2/i_Enc/qD_reg_n_0_\ : STD_LOGIC_VECTOR ( 0 to 0 ); - signal \TMDS_2/i_GBox/cntMod5_reg_n_0_\ : STD_LOGIC_VECTOR ( 2 downto 0 ); - signal \TMDS_2/i_GBox/sReg_reg_n_0_\ : STD_LOGIC_VECTOR ( 9 downto 2 ); - signal \TMDS_3/D1\ : STD_LOGIC; - signal \TMDS_3/D2\ : STD_LOGIC; - signal \TMDS_3/Reset\ : STD_LOGIC; - signal \TMDS_3/i_GBox/cntMod5_reg_n_0_\ : STD_LOGIC_VECTOR ( 2 downto 0 ); - signal \TMDS_3/i_GBox/sReg_reg_n_0_\ : STD_LOGIC_VECTOR ( 3 to 3 ); - signal \cntMod5[0]_i_1__0_n_0\ : STD_LOGIC; - signal \cntMod5[0]_i_1__1_n_0\ : STD_LOGIC; - signal \cntMod5[0]_i_1__2_n_0\ : STD_LOGIC; - signal \cntMod5[1]_i_1__0_n_0\ : STD_LOGIC; - signal \cntMod5[1]_i_1__1_n_0\ : STD_LOGIC; - signal \cntMod5[1]_i_1__2_n_0\ : STD_LOGIC; - signal \cntMod5[2]_i_1__0_n_0\ : STD_LOGIC; - signal \cntMod5[2]_i_1__1_n_0\ : STD_LOGIC; - signal \cntMod5[2]_i_1__2_n_0\ : STD_LOGIC; - signal \cntMod5[2]_i_1_n_0\ : STD_LOGIC; - signal \cntMod5[2]_i_2__0_n_0\ : STD_LOGIC; - signal \cntMod5[2]_i_2__1_n_0\ : STD_LOGIC; - signal \cntMod5[2]_i_2__2_n_0\ : STD_LOGIC; - signal \g0_b0__0_n_0\ : STD_LOGIC; - signal \g0_b0__1_n_0\ : STD_LOGIC; - signal \g0_b0__2_n_0\ : STD_LOGIC; - signal \g0_b0__3_n_0\ : STD_LOGIC; - signal \g0_b0__4_n_0\ : STD_LOGIC; - signal g0_b0_n_0 : STD_LOGIC; - signal \g0_b1__0_n_0\ : STD_LOGIC; - signal \g0_b1__1_n_0\ : STD_LOGIC; - signal \g0_b1__2_n_0\ : STD_LOGIC; - signal \g0_b1__3_n_0\ : STD_LOGIC; - signal \g0_b1__4_n_0\ : STD_LOGIC; - signal g0_b1_n_0 : STD_LOGIC; - signal \g0_b2__0_n_0\ : STD_LOGIC; - signal \g0_b2__1_n_0\ : STD_LOGIC; - signal \g0_b2__2_n_0\ : STD_LOGIC; - signal \g0_b2__3_n_0\ : STD_LOGIC; - signal \g0_b2__4_n_0\ : STD_LOGIC; - signal \g0_b2_i_1__0_n_0\ : STD_LOGIC; - signal \g0_b2_i_1__1_n_0\ : STD_LOGIC; - signal g0_b2_i_1_n_0 : STD_LOGIC; - signal \g0_b2_i_2__0_n_0\ : STD_LOGIC; - signal \g0_b2_i_2__1_n_0\ : STD_LOGIC; - signal \g0_b2_i_3__0_n_0\ : STD_LOGIC; - signal \g0_b2_i_3__1_n_0\ : STD_LOGIC; - signal g0_b2_i_3_n_0 : STD_LOGIC; - signal \g0_b2_i_4__0_n_0\ : STD_LOGIC; - signal \g0_b2_i_4__1_n_0\ : STD_LOGIC; - signal g0_b2_i_4_n_0 : STD_LOGIC; - signal g0_b2_n_0 : STD_LOGIC; - signal \i_ODDRE_N_i_1__0_n_0\ : STD_LOGIC; - signal \i_ODDRE_N_i_1__1_n_0\ : STD_LOGIC; - signal \i_ODDRE_N_i_1__2_n_0\ : STD_LOGIC; - signal i_ODDRE_N_i_1_n_0 : STD_LOGIC; - signal \i_ODDRE_N_i_2__0_n_0\ : STD_LOGIC; - signal \i_ODDRE_N_i_2__1_n_0\ : STD_LOGIC; - signal \i_ODDRE_N_i_2__2_n_0\ : STD_LOGIC; - signal i_ODDRE_N_i_2_n_0 : STD_LOGIC; - signal plusOp : STD_LOGIC_VECTOR ( 2 downto 0 ); - signal qC1C0 : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal qDE : STD_LOGIC; - signal \sReg[0]_i_1__0_n_0\ : STD_LOGIC; - signal \sReg[0]_i_1__1_n_0\ : STD_LOGIC; - signal \sReg[0]_i_1__2_n_0\ : STD_LOGIC; - signal \sReg[0]_i_1_n_0\ : STD_LOGIC; - signal \sReg[1]_i_1__0_n_0\ : STD_LOGIC; - signal \sReg[1]_i_1__1_n_0\ : STD_LOGIC; - signal \sReg[1]_i_1__2_n_0\ : STD_LOGIC; - signal \sReg[1]_i_1_n_0\ : STD_LOGIC; - signal \sReg[1]_i_2__0_n_0\ : STD_LOGIC; - signal \sReg[1]_i_2__1_n_0\ : STD_LOGIC; - signal \sReg[1]_i_2_n_0\ : STD_LOGIC; - signal \sReg[1]_i_3_n_0\ : STD_LOGIC; - signal \sReg[1]_i_4_n_0\ : STD_LOGIC; - signal \sReg[1]_i_5_n_0\ : STD_LOGIC; - signal \sReg[2]_i_1__0_n_0\ : STD_LOGIC; - signal \sReg[2]_i_1__1_n_0\ : STD_LOGIC; - signal \sReg[2]_i_1_n_0\ : STD_LOGIC; - signal \sReg[2]_i_2__0_n_0\ : STD_LOGIC; - signal \sReg[2]_i_2__1_n_0\ : STD_LOGIC; - signal \sReg[2]_i_2_n_0\ : STD_LOGIC; - signal \sReg[3]_i_1__0_n_0\ : STD_LOGIC; - signal \sReg[3]_i_1__1_n_0\ : STD_LOGIC; - signal \sReg[3]_i_1__2_n_0\ : STD_LOGIC; - signal \sReg[3]_i_1_n_0\ : STD_LOGIC; - signal \sReg[3]_i_2__0_n_0\ : STD_LOGIC; - signal \sReg[3]_i_2__1_n_0\ : STD_LOGIC; - signal \sReg[3]_i_2_n_0\ : STD_LOGIC; - signal \sReg[3]_i_3_n_0\ : STD_LOGIC; - signal \sReg[3]_i_4_n_0\ : STD_LOGIC; - signal \sReg[4]_i_1__0_n_0\ : STD_LOGIC; - signal \sReg[4]_i_1__1_n_0\ : STD_LOGIC; - signal \sReg[4]_i_1_n_0\ : STD_LOGIC; - signal \sReg[5]_i_1__0_n_0\ : STD_LOGIC; - signal \sReg[5]_i_1__1_n_0\ : STD_LOGIC; - signal \sReg[5]_i_1_n_0\ : STD_LOGIC; - signal \sReg[5]_i_2__0_n_0\ : STD_LOGIC; - signal \sReg[5]_i_2__1_n_0\ : STD_LOGIC; - signal \sReg[5]_i_2_n_0\ : STD_LOGIC; - signal \sReg[5]_i_3_n_0\ : STD_LOGIC; - signal \sReg[5]_i_4_n_0\ : STD_LOGIC; - signal \sReg[5]_i_5_n_0\ : STD_LOGIC; - signal \sReg[6]_i_1__0_n_0\ : STD_LOGIC; - signal \sReg[6]_i_1__1_n_0\ : STD_LOGIC; - signal \sReg[6]_i_1_n_0\ : STD_LOGIC; - signal \sReg[6]_i_2__0_n_0\ : STD_LOGIC; - signal \sReg[6]_i_2__1_n_0\ : STD_LOGIC; - signal \sReg[6]_i_2_n_0\ : STD_LOGIC; - signal \sReg[7]_i_1__0_n_0\ : STD_LOGIC; - signal \sReg[7]_i_1__1_n_0\ : STD_LOGIC; - signal \sReg[7]_i_1_n_0\ : STD_LOGIC; - signal \sReg[7]_i_2__0_n_0\ : STD_LOGIC; - signal \sReg[7]_i_2__1_n_0\ : STD_LOGIC; - signal \sReg[7]_i_2_n_0\ : STD_LOGIC; - signal \sReg[7]_i_3__0_n_0\ : STD_LOGIC; - signal \sReg[7]_i_3_n_0\ : STD_LOGIC; - signal \sReg[7]_i_4_n_0\ : STD_LOGIC; - signal \sReg[8]_i_1__0_n_0\ : STD_LOGIC; - signal \sReg[8]_i_1__1_n_0\ : STD_LOGIC; - signal \sReg[8]_i_1_n_0\ : STD_LOGIC; - signal \sReg[9]_i_1__0_n_0\ : STD_LOGIC; - signal \sReg[9]_i_1__1_n_0\ : STD_LOGIC; - signal \sReg[9]_i_1_n_0\ : STD_LOGIC; - signal \sReg[9]_i_2__0_n_0\ : STD_LOGIC; - signal \sReg[9]_i_2__1_n_0\ : STD_LOGIC; - signal \sReg[9]_i_2_n_0\ : STD_LOGIC; - signal \sReg[9]_i_3_n_0\ : STD_LOGIC; - signal \sReg[9]_i_4_n_0\ : STD_LOGIC; - signal \NLW_TMDS_0/i_ODDRE_N_CLKDIV_UNCONNECTED\ : STD_LOGIC; - signal \NLW_TMDS_0/i_ODDRE_N_T_OUT_UNCONNECTED\ : STD_LOGIC; - signal \NLW_TMDS_0/i_ODDRE_N_D_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 ); - signal \NLW_TMDS_0/i_ODDRE_P_CLKDIV_UNCONNECTED\ : STD_LOGIC; - signal \NLW_TMDS_0/i_ODDRE_P_T_OUT_UNCONNECTED\ : STD_LOGIC; - signal \NLW_TMDS_0/i_ODDRE_P_D_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 ); - signal \NLW_TMDS_1/i_ODDRE_N_CLKDIV_UNCONNECTED\ : STD_LOGIC; - signal \NLW_TMDS_1/i_ODDRE_N_T_OUT_UNCONNECTED\ : STD_LOGIC; - signal \NLW_TMDS_1/i_ODDRE_N_D_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 ); - signal \NLW_TMDS_1/i_ODDRE_P_CLKDIV_UNCONNECTED\ : STD_LOGIC; - signal \NLW_TMDS_1/i_ODDRE_P_T_OUT_UNCONNECTED\ : STD_LOGIC; - signal \NLW_TMDS_1/i_ODDRE_P_D_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 ); - signal \NLW_TMDS_2/i_ODDRE_N_CLKDIV_UNCONNECTED\ : STD_LOGIC; - signal \NLW_TMDS_2/i_ODDRE_N_T_OUT_UNCONNECTED\ : STD_LOGIC; - signal \NLW_TMDS_2/i_ODDRE_N_D_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 ); - signal \NLW_TMDS_2/i_ODDRE_P_CLKDIV_UNCONNECTED\ : STD_LOGIC; - signal \NLW_TMDS_2/i_ODDRE_P_T_OUT_UNCONNECTED\ : STD_LOGIC; - signal \NLW_TMDS_2/i_ODDRE_P_D_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 ); - signal \NLW_TMDS_3/i_ODDRE_N_CLKDIV_UNCONNECTED\ : STD_LOGIC; - signal \NLW_TMDS_3/i_ODDRE_N_T_OUT_UNCONNECTED\ : STD_LOGIC; - signal \NLW_TMDS_3/i_ODDRE_N_D_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 ); - signal \NLW_TMDS_3/i_ODDRE_P_CLKDIV_UNCONNECTED\ : STD_LOGIC; - signal \NLW_TMDS_3/i_ODDRE_P_T_OUT_UNCONNECTED\ : STD_LOGIC; - signal \NLW_TMDS_3/i_ODDRE_P_D_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 ); - attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \Cnt[1]_i_2\ : label is "soft_lutpair32"; - attribute SOFT_HLUTNM of \Cnt[1]_i_2__0\ : label is "soft_lutpair33"; - attribute SOFT_HLUTNM of \Cnt[2]_i_3\ : label is "soft_lutpair34"; - attribute SOFT_HLUTNM of \Cnt[2]_i_4\ : label is "soft_lutpair41"; - attribute SOFT_HLUTNM of \Cnt[3]_i_2__0\ : label is "soft_lutpair20"; - attribute SOFT_HLUTNM of \Cnt[3]_i_3\ : label is "soft_lutpair25"; - attribute SOFT_HLUTNM of \Cnt[3]_i_4\ : label is "soft_lutpair27"; - attribute SOFT_HLUTNM of \Cnt[3]_i_4__0\ : label is "soft_lutpair26"; - attribute SOFT_HLUTNM of \Cnt[3]_i_5\ : label is "soft_lutpair21"; - attribute SOFT_HLUTNM of \Cnt[3]_i_6\ : label is "soft_lutpair21"; - attribute SOFT_HLUTNM of \Cnt[4]_i_10\ : label is "soft_lutpair1"; - attribute SOFT_HLUTNM of \Cnt[4]_i_11\ : label is "soft_lutpair28"; - attribute SOFT_HLUTNM of \Cnt[4]_i_12__1\ : label is "soft_lutpair26"; - attribute SOFT_HLUTNM of \Cnt[4]_i_13__1\ : label is "soft_lutpair24"; - attribute SOFT_HLUTNM of \Cnt[4]_i_14\ : label is "soft_lutpair25"; - attribute SOFT_HLUTNM of \Cnt[4]_i_14__0\ : label is "soft_lutpair20"; - attribute SOFT_HLUTNM of \Cnt[4]_i_15\ : label is "soft_lutpair23"; - attribute SOFT_HLUTNM of \Cnt[4]_i_15__0\ : label is "soft_lutpair40"; - attribute SOFT_HLUTNM of \Cnt[4]_i_15__1\ : label is "soft_lutpair22"; - attribute SOFT_HLUTNM of \Cnt[4]_i_16\ : label is "soft_lutpair27"; - attribute SOFT_HLUTNM of \Cnt[4]_i_16__0\ : label is "soft_lutpair22"; - attribute SOFT_HLUTNM of \Cnt[4]_i_16__1\ : label is "soft_lutpair19"; - attribute SOFT_HLUTNM of \Cnt[4]_i_17\ : label is "soft_lutpair19"; - attribute SOFT_HLUTNM of \Cnt[4]_i_17__0\ : label is "soft_lutpair24"; - attribute SOFT_HLUTNM of \Cnt[4]_i_18__0\ : label is "soft_lutpair29"; - attribute SOFT_HLUTNM of \Cnt[4]_i_19\ : label is "soft_lutpair40"; - attribute SOFT_HLUTNM of \Cnt[4]_i_19__0\ : label is "soft_lutpair18"; - attribute SOFT_HLUTNM of \Cnt[4]_i_20\ : label is "soft_lutpair17"; - attribute SOFT_HLUTNM of \Cnt[4]_i_21\ : label is "soft_lutpair16"; - attribute SOFT_HLUTNM of \Cnt[4]_i_21__0\ : label is "soft_lutpair44"; - attribute SOFT_HLUTNM of \Cnt[4]_i_22\ : label is "soft_lutpair44"; - attribute SOFT_HLUTNM of \Cnt[4]_i_23\ : label is "soft_lutpair32"; - attribute SOFT_HLUTNM of \Cnt[4]_i_25\ : label is "soft_lutpair12"; - attribute SOFT_HLUTNM of \Cnt[4]_i_3__0\ : label is "soft_lutpair1"; - attribute SOFT_HLUTNM of \Cnt[4]_i_4\ : label is "soft_lutpair28"; - attribute SOFT_HLUTNM of \Cnt[4]_i_4__1\ : label is "soft_lutpair29"; - attribute SOFT_HLUTNM of \Cnt[4]_i_8__0\ : label is "soft_lutpair17"; - attribute SOFT_HLUTNM of \Cnt[4]_i_8__1\ : label is "soft_lutpair18"; - attribute SOFT_HLUTNM of \Cnt[4]_i_9\ : label is "soft_lutpair23"; - attribute SOFT_HLUTNM of \Cnt[4]_i_9__0\ : label is "soft_lutpair16"; - attribute XILINX_LEGACY_PRIM : string; - attribute XILINX_LEGACY_PRIM of \TMDS_0/i_ODDRE_N\ : label is "ODDRE1"; - attribute XILINX_TRANSFORM_PINMAP : string; - attribute XILINX_TRANSFORM_PINMAP of \TMDS_0/i_ODDRE_N\ : label is "C:CLK SR:RST GND:T Q:OQ D1:D[0] D2:D[4]"; - attribute box_type : string; - attribute box_type of \TMDS_0/i_ODDRE_N\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \TMDS_0/i_ODDRE_P\ : label is "ODDRE1"; - attribute XILINX_TRANSFORM_PINMAP of \TMDS_0/i_ODDRE_P\ : label is "C:CLK SR:RST GND:T Q:OQ D1:D[0] D2:D[4]"; - attribute box_type of \TMDS_0/i_ODDRE_P\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \TMDS_1/i_ODDRE_N\ : label is "ODDRE1"; - attribute XILINX_TRANSFORM_PINMAP of \TMDS_1/i_ODDRE_N\ : label is "C:CLK SR:RST GND:T Q:OQ D1:D[0] D2:D[4]"; - attribute box_type of \TMDS_1/i_ODDRE_N\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \TMDS_1/i_ODDRE_P\ : label is "ODDRE1"; - attribute XILINX_TRANSFORM_PINMAP of \TMDS_1/i_ODDRE_P\ : label is "C:CLK SR:RST GND:T Q:OQ D1:D[0] D2:D[4]"; - attribute box_type of \TMDS_1/i_ODDRE_P\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \TMDS_2/i_ODDRE_N\ : label is "ODDRE1"; - attribute XILINX_TRANSFORM_PINMAP of \TMDS_2/i_ODDRE_N\ : label is "C:CLK SR:RST GND:T Q:OQ D1:D[0] D2:D[4]"; - attribute box_type of \TMDS_2/i_ODDRE_N\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \TMDS_2/i_ODDRE_P\ : label is "ODDRE1"; - attribute XILINX_TRANSFORM_PINMAP of \TMDS_2/i_ODDRE_P\ : label is "C:CLK SR:RST GND:T Q:OQ D1:D[0] D2:D[4]"; - attribute box_type of \TMDS_2/i_ODDRE_P\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \TMDS_3/i_ODDRE_N\ : label is "ODDRE1"; - attribute XILINX_TRANSFORM_PINMAP of \TMDS_3/i_ODDRE_N\ : label is "C:CLK SR:RST GND:T Q:OQ D1:D[0] D2:D[4]"; - attribute box_type of \TMDS_3/i_ODDRE_N\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \TMDS_3/i_ODDRE_P\ : label is "ODDRE1"; - attribute XILINX_TRANSFORM_PINMAP of \TMDS_3/i_ODDRE_P\ : label is "C:CLK SR:RST GND:T Q:OQ D1:D[0] D2:D[4]"; - attribute box_type of \TMDS_3/i_ODDRE_P\ : label is "PRIMITIVE"; - attribute SOFT_HLUTNM of \cntMod5[1]_i_1\ : label is "soft_lutpair45"; - attribute SOFT_HLUTNM of \cntMod5[1]_i_1__0\ : label is "soft_lutpair46"; - attribute SOFT_HLUTNM of \cntMod5[1]_i_1__1\ : label is "soft_lutpair47"; - attribute SOFT_HLUTNM of \cntMod5[1]_i_1__2\ : label is "soft_lutpair48"; - attribute SOFT_HLUTNM of \cntMod5[2]_i_2\ : label is "soft_lutpair45"; - attribute SOFT_HLUTNM of \cntMod5[2]_i_2__0\ : label is "soft_lutpair46"; - attribute SOFT_HLUTNM of \cntMod5[2]_i_2__1\ : label is "soft_lutpair47"; - attribute SOFT_HLUTNM of \cntMod5[2]_i_2__2\ : label is "soft_lutpair48"; - attribute SOFT_HLUTNM of g0_b0 : label is "soft_lutpair6"; - attribute SOFT_HLUTNM of \g0_b0__0\ : label is "soft_lutpair0"; - attribute SOFT_HLUTNM of \g0_b0__1\ : label is "soft_lutpair8"; - attribute SOFT_HLUTNM of \g0_b0__2\ : label is "soft_lutpair37"; - attribute SOFT_HLUTNM of \g0_b0__3\ : label is "soft_lutpair43"; - attribute SOFT_HLUTNM of \g0_b0__4\ : label is "soft_lutpair42"; - attribute SOFT_HLUTNM of g0_b1 : label is "soft_lutpair6"; - attribute SOFT_HLUTNM of \g0_b1__0\ : label is "soft_lutpair0"; - attribute SOFT_HLUTNM of \g0_b1__1\ : label is "soft_lutpair5"; - attribute SOFT_HLUTNM of g0_b2 : label is "soft_lutpair10"; - attribute SOFT_HLUTNM of \g0_b2__0\ : label is "soft_lutpair11"; - attribute SOFT_HLUTNM of \g0_b2__1\ : label is "soft_lutpair5"; - attribute SOFT_HLUTNM of g0_b2_i_2 : label is "soft_lutpair8"; - attribute SOFT_HLUTNM of \g0_b2_i_2__0\ : label is "soft_lutpair10"; - attribute SOFT_HLUTNM of \g0_b2_i_2__1\ : label is "soft_lutpair11"; - attribute SOFT_HLUTNM of g0_b2_i_3 : label is "soft_lutpair14"; - attribute SOFT_HLUTNM of \g0_b2_i_3__1\ : label is "soft_lutpair12"; - attribute SOFT_HLUTNM of g0_b2_i_4 : label is "soft_lutpair41"; - attribute SOFT_HLUTNM of \g0_b2_i_4__0\ : label is "soft_lutpair4"; - attribute SOFT_HLUTNM of \g0_b2_i_4__1\ : label is "soft_lutpair13"; - attribute SOFT_HLUTNM of i_ODDRE_N_i_2 : label is "soft_lutpair39"; - attribute SOFT_HLUTNM of \sReg[0]_i_1__2\ : label is "soft_lutpair39"; - attribute SOFT_HLUTNM of \sReg[1]_i_1__2\ : label is "soft_lutpair38"; - attribute SOFT_HLUTNM of \sReg[1]_i_2\ : label is "soft_lutpair9"; - attribute SOFT_HLUTNM of \sReg[1]_i_2__0\ : label is "soft_lutpair35"; - attribute SOFT_HLUTNM of \sReg[1]_i_4\ : label is "soft_lutpair31"; - attribute SOFT_HLUTNM of \sReg[1]_i_5\ : label is "soft_lutpair15"; - attribute SOFT_HLUTNM of \sReg[2]_i_2\ : label is "soft_lutpair31"; - attribute SOFT_HLUTNM of \sReg[2]_i_2__0\ : label is "soft_lutpair43"; - attribute SOFT_HLUTNM of \sReg[2]_i_2__1\ : label is "soft_lutpair42"; - attribute SOFT_HLUTNM of \sReg[3]_i_1__1\ : label is "soft_lutpair7"; - attribute SOFT_HLUTNM of \sReg[3]_i_1__2\ : label is "soft_lutpair38"; - attribute SOFT_HLUTNM of \sReg[3]_i_2\ : label is "soft_lutpair3"; - attribute SOFT_HLUTNM of \sReg[3]_i_2__1\ : label is "soft_lutpair35"; - attribute SOFT_HLUTNM of \sReg[3]_i_4\ : label is "soft_lutpair37"; - attribute SOFT_HLUTNM of \sReg[5]_i_2__1\ : label is "soft_lutpair36"; - attribute SOFT_HLUTNM of \sReg[5]_i_3\ : label is "soft_lutpair30"; - attribute SOFT_HLUTNM of \sReg[5]_i_5\ : label is "soft_lutpair15"; - attribute SOFT_HLUTNM of \sReg[6]_i_2__0\ : label is "soft_lutpair30"; - attribute SOFT_HLUTNM of \sReg[7]_i_2\ : label is "soft_lutpair4"; - attribute SOFT_HLUTNM of \sReg[7]_i_2__0\ : label is "soft_lutpair14"; - attribute SOFT_HLUTNM of \sReg[7]_i_2__1\ : label is "soft_lutpair13"; - attribute SOFT_HLUTNM of \sReg[7]_i_3\ : label is "soft_lutpair7"; - attribute SOFT_HLUTNM of \sReg[7]_i_3__0\ : label is "soft_lutpair33"; - attribute SOFT_HLUTNM of \sReg[7]_i_4\ : label is "soft_lutpair2"; - attribute SOFT_HLUTNM of \sReg[9]_i_1__0\ : label is "soft_lutpair2"; - attribute SOFT_HLUTNM of \sReg[9]_i_2__0\ : label is "soft_lutpair3"; - attribute SOFT_HLUTNM of \sReg[9]_i_2__1\ : label is "soft_lutpair9"; - attribute SOFT_HLUTNM of \sReg[9]_i_3\ : label is "soft_lutpair36"; - attribute SOFT_HLUTNM of \sReg[9]_i_4\ : label is "soft_lutpair34"; -begin -\Cnt[1]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"906F6F90" - ) - port map ( - I0 => g0_b2_i_1_n_0, - I1 => \Cnt[4]_i_4_n_0\, - I2 => \Cnt[4]_i_6_n_0\, - I3 => \TMDS_0/i_Enc/Cnt_reg_n_0_\(1), - I4 => \Cnt[2]_i_4_n_0\, - O => \Cnt[1]_i_1_n_0\ - ); -\Cnt[1]_i_1__0\: unisim.vcomponents.LUT5 - generic map( - INIT => X"609F9F60" - ) - port map ( - I0 => \g0_b2_i_1__0_n_0\, - I1 => \Cnt[4]_i_3__0_n_0\, - I2 => \Cnt[4]_i_5__0_n_0\, - I3 => \TMDS_1/i_Enc/Cnt_reg_n_0_\(1), - I4 => \Cnt[1]_i_2__0_n_0\, - O => \Cnt[1]_i_1__0_n_0\ - ); -\Cnt[1]_i_1__1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"9F60609F" - ) - port map ( - I0 => \g0_b2_i_1__1_n_0\, - I1 => \Cnt[4]_i_4__1_n_0\, - I2 => \Cnt[4]_i_6__0_n_0\, - I3 => \TMDS_2/i_Enc/Cnt_reg_n_0_\(1), - I4 => \Cnt[1]_i_2_n_0\, - O => \Cnt[1]_i_1__1_n_0\ - ); -\Cnt[1]_i_2\: unisim.vcomponents.LUT4 - generic map( - INIT => X"9669" - ) - port map ( - I0 => \g0_b0__4_n_0\, - I1 => \TMDS_2/i_Enc/p_8_in\, - I2 => \TMDS_2/i_Enc/p_9_in\, - I3 => \TMDS_2/i_Enc/p_12_in\, - O => \Cnt[1]_i_2_n_0\ - ); -\Cnt[1]_i_2__0\: unisim.vcomponents.LUT4 - generic map( - INIT => X"6996" - ) - port map ( - I0 => \g0_b0__3_n_0\, - I1 => \g0_b2_i_2__1_n_0\, - I2 => \TMDS_1/i_Enc/p_8_in\, - I3 => \TMDS_1/i_Enc/p_12_in\, - O => \Cnt[1]_i_2__0_n_0\ - ); -\Cnt[2]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"8B8BB88BB88B8B8B" - ) - port map ( - I0 => \Cnt[2]_i_2_n_0\, - I1 => \Cnt[4]_i_6_n_0\, - I2 => \Cnt[2]_i_3_n_0\, - I3 => \Cnt[2]_i_4_n_0\, - I4 => \Cnt[2]_i_5_n_0\, - I5 => \TMDS_0/i_Enc/Cnt_reg_n_0_\(1), - O => \Cnt[2]_i_1_n_0\ - ); -\Cnt[2]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"639C39C6936C36C9" - ) - port map ( - I0 => \Cnt[4]_i_4_n_0\, - I1 => \TMDS_0/i_Enc/Cnt_reg_n_0_\(2), - I2 => \TMDS_0/i_Enc/Cnt_reg_n_0_\(1), - I3 => \Cnt[3]_i_8_n_0\, - I4 => g0_b2_i_1_n_0, - I5 => \Cnt[2]_i_4_n_0\, - O => \Cnt[2]_i_2_n_0\ - ); -\Cnt[2]_i_2__0\: unisim.vcomponents.LUT5 - generic map( - INIT => X"A6596A95" - ) - port map ( - I0 => \TMDS_1/i_Enc/Cnt_reg_n_0_\(2), - I1 => \Cnt[1]_i_2__0_n_0\, - I2 => \g0_b2_i_1__0_n_0\, - I3 => \Cnt[4]_i_12__0_n_0\, - I4 => \TMDS_1/i_Enc/Cnt_reg_n_0_\(1), - O => \Cnt[2]_i_2__0_n_0\ - ); -\Cnt[2]_i_2__1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"A9569A65" - ) - port map ( - I0 => \TMDS_2/i_Enc/Cnt_reg_n_0_\(2), - I1 => \Cnt[1]_i_2_n_0\, - I2 => \g0_b2_i_1__1_n_0\, - I3 => \Cnt[4]_i_9__1_n_0\, - I4 => \TMDS_2/i_Enc/Cnt_reg_n_0_\(1), - O => \Cnt[2]_i_2__1_n_0\ - ); -\Cnt[2]_i_3\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => \TMDS_0/i_Enc/Cnt_reg_n_0_\(2), - I1 => \Cnt[4]_i_10__1_n_0\, - O => \Cnt[2]_i_3_n_0\ - ); -\Cnt[2]_i_3__0\: unisim.vcomponents.LUT6 - generic map( - INIT => X"F0960F6969F0960F" - ) - port map ( - I0 => \Cnt[4]_i_3__0_n_0\, - I1 => \Cnt[1]_i_2__0_n_0\, - I2 => \TMDS_1/i_Enc/Cnt_reg_n_0_\(2), - I3 => \g0_b2_i_1__0_n_0\, - I4 => \Cnt[4]_i_12__0_n_0\, - I5 => \TMDS_1/i_Enc/Cnt_reg_n_0_\(1), - O => \Cnt[2]_i_3__0_n_0\ - ); -\Cnt[2]_i_3__1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"C9366C93C6399C63" - ) - port map ( - I0 => \Cnt[4]_i_4__1_n_0\, - I1 => \TMDS_2/i_Enc/Cnt_reg_n_0_\(2), - I2 => \TMDS_2/i_Enc/Cnt_reg_n_0_\(1), - I3 => \Cnt[4]_i_9__1_n_0\, - I4 => \g0_b2_i_1__1_n_0\, - I5 => \Cnt[1]_i_2_n_0\, - O => \Cnt[2]_i_3__1_n_0\ - ); -\Cnt[2]_i_4\: unisim.vcomponents.LUT4 - generic map( - INIT => X"6996" - ) - port map ( - I0 => \g0_b0__2_n_0\, - I1 => \TMDS_0/i_Enc/p_8_in\, - I2 => \g0_b2_i_2__0_n_0\, - I3 => \TMDS_0/i_Enc/p_12_in\, - O => \Cnt[2]_i_4_n_0\ - ); -\Cnt[2]_i_5\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AA69995A995A5596" - ) - port map ( - I0 => \g0_b1__2_n_0\, - I1 => \TMDS_0/i_Enc/p_12_in\, - I2 => \sReg[5]_i_4_n_0\, - I3 => \g0_b0__2_n_0\, - I4 => \TMDS_0/i_Enc/p_10_in\, - I5 => g0_b2_i_1_n_0, - O => \Cnt[2]_i_5_n_0\ - ); -\Cnt[3]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"B88B8BB8" - ) - port map ( - I0 => \Cnt[3]_i_2_n_0\, - I1 => \Cnt[4]_i_6_n_0\, - I2 => \Cnt[3]_i_3_n_0\, - I3 => \Cnt[3]_i_4_n_0\, - I4 => \Cnt[3]_i_5_n_0\, - O => \Cnt[3]_i_1_n_0\ - ); -\Cnt[3]_i_1__0\: unisim.vcomponents.LUT6 - generic map( - INIT => X"6F60FFFF6F600000" - ) - port map ( - I0 => \Cnt[3]_i_2__0_n_0\, - I1 => \Cnt[3]_i_3__0_n_0\, - I2 => \Cnt[4]_i_3__0_n_0\, - I3 => \Cnt[3]_i_4__1_n_0\, - I4 => \Cnt[4]_i_5__0_n_0\, - I5 => \Cnt[3]_i_5__1_n_0\, - O => \Cnt[3]_i_1__0_n_0\ - ); -\Cnt[3]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"6F60606F606F6F60" - ) - port map ( - I0 => \Cnt[3]_i_6_n_0\, - I1 => \Cnt[4]_i_9_n_0\, - I2 => \Cnt[4]_i_4_n_0\, - I3 => \Cnt[4]_i_15_n_0\, - I4 => \Cnt[3]_i_7_n_0\, - I5 => \Cnt[4]_i_14_n_0\, - O => \Cnt[3]_i_2_n_0\ - ); -\Cnt[3]_i_2__0\: unisim.vcomponents.LUT5 - generic map( - INIT => X"60666690" - ) - port map ( - I0 => \Cnt[4]_i_12__0_n_0\, - I1 => \TMDS_1/i_Enc/Cnt_reg_n_0_\(2), - I2 => \TMDS_1/i_Enc/Cnt_reg_n_0_\(1), - I3 => \g0_b2_i_1__0_n_0\, - I4 => \Cnt[1]_i_2__0_n_0\, - O => \Cnt[3]_i_2__0_n_0\ - ); -\Cnt[3]_i_2__1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"9969669666699996" - ) - port map ( - I0 => \TMDS_2/i_Enc/Cnt_reg_n_0_\(3), - I1 => \Cnt[4]_i_17__0_n_0\, - I2 => \g0_b2_i_1__1_n_0\, - I3 => \Cnt[4]_i_11__1_n_0\, - I4 => \Cnt[4]_i_14__1_n_0\, - I5 => \TMDS_2/i_Enc/Cnt_reg_n_0_\(2), - O => \Cnt[3]_i_2__1_n_0\ - ); -\Cnt[3]_i_3\: unisim.vcomponents.LUT5 - generic map( - INIT => X"FAD28705" - ) - port map ( - I0 => \Cnt[2]_i_4_n_0\, - I1 => g0_b2_i_1_n_0, - I2 => \Cnt[3]_i_8_n_0\, - I3 => \TMDS_0/i_Enc/Cnt_reg_n_0_\(1), - I4 => \TMDS_0/i_Enc/Cnt_reg_n_0_\(2), - O => \Cnt[3]_i_3_n_0\ - ); -\Cnt[3]_i_3__0\: unisim.vcomponents.LUT6 - generic map( - INIT => X"9696666696996696" - ) - port map ( - I0 => \Cnt[4]_i_21_n_0\, - I1 => \TMDS_1/i_Enc/Cnt_reg_n_0_\(3), - I2 => \TMDS_1/i_Enc/Cnt_reg_n_0_\(2), - I3 => \Cnt[1]_i_2__0_n_0\, - I4 => \Cnt[4]_i_12__0_n_0\, - I5 => \g0_b2_i_1__0_n_0\, - O => \Cnt[3]_i_3__0_n_0\ - ); -\Cnt[3]_i_3__1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"6F60606F606F6F60" - ) - port map ( - I0 => \Cnt[3]_i_4__0_n_0\, - I1 => \Cnt[3]_i_5__0_n_0\, - I2 => \Cnt[4]_i_4__1_n_0\, - I3 => \Cnt[4]_i_13__1_n_0\, - I4 => \Cnt[3]_i_6__0_n_0\, - I5 => \Cnt[4]_i_12__1_n_0\, - O => \Cnt[3]_i_3__1_n_0\ - ); -\Cnt[3]_i_4\: unisim.vcomponents.LUT5 - generic map( - INIT => X"74474774" - ) - port map ( - I0 => \TMDS_0/i_Enc/Cnt_reg_n_0_\(2), - I1 => \Cnt[4]_i_10__1_n_0\, - I2 => g0_b2_i_1_n_0, - I3 => \Cnt[4]_i_13_n_0\, - I4 => \g0_b2__2_n_0\, - O => \Cnt[3]_i_4_n_0\ - ); -\Cnt[3]_i_4__0\: unisim.vcomponents.LUT5 - generic map( - INIT => X"66906066" - ) - port map ( - I0 => \Cnt[4]_i_9__1_n_0\, - I1 => \TMDS_2/i_Enc/Cnt_reg_n_0_\(2), - I2 => \TMDS_2/i_Enc/Cnt_reg_n_0_\(1), - I3 => \g0_b2_i_1__1_n_0\, - I4 => \Cnt[1]_i_2_n_0\, - O => \Cnt[3]_i_4__0_n_0\ - ); -\Cnt[3]_i_4__1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"9669" - ) - port map ( - I0 => \Cnt[4]_i_14__0_n_0\, - I1 => \TMDS_1/i_Enc/Cnt_reg_n_0_\(3), - I2 => \Cnt[4]_i_21_n_0\, - I3 => \Cnt[4]_i_15__0_n_0\, - O => \Cnt[3]_i_4__1_n_0\ - ); -\Cnt[3]_i_5\: unisim.vcomponents.LUT4 - generic map( - INIT => X"69AA" - ) - port map ( - I0 => \TMDS_0/i_Enc/Cnt_reg_n_0_\(3), - I1 => \g0_b2__2_n_0\, - I2 => \Cnt[4]_i_13_n_0\, - I3 => \Cnt[4]_i_10__1_n_0\, - O => \Cnt[3]_i_5_n_0\ - ); -\Cnt[3]_i_5__0\: unisim.vcomponents.LUT6 - generic map( - INIT => X"9696666699969666" - ) - port map ( - I0 => \Cnt[4]_i_14__1_n_0\, - I1 => \TMDS_2/i_Enc/Cnt_reg_n_0_\(3), - I2 => \TMDS_2/i_Enc/Cnt_reg_n_0_\(2), - I3 => \Cnt[1]_i_2_n_0\, - I4 => \Cnt[4]_i_9__1_n_0\, - I5 => \g0_b2_i_1__1_n_0\, - O => \Cnt[3]_i_5__0_n_0\ - ); -\Cnt[3]_i_5__1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"59A6A956A65956A9" - ) - port map ( - I0 => \TMDS_1/i_Enc/Cnt_reg_n_0_\(3), - I1 => \g0_b2_i_1__0_n_0\, - I2 => \Cnt[4]_i_19_n_0\, - I3 => \Cnt[4]_i_21_n_0\, - I4 => \TMDS_1/i_Enc/Cnt_reg_n_0_\(2), - I5 => \Cnt[4]_i_20_n_0\, - O => \Cnt[3]_i_5__1_n_0\ - ); -\Cnt[3]_i_6\: unisim.vcomponents.LUT5 - generic map( - INIT => X"956A6A95" - ) - port map ( - I0 => \TMDS_0/i_Enc/Cnt_reg_n_0_\(3), - I1 => \TMDS_0/i_Enc/Cnt_reg_n_0_\(2), - I2 => \Cnt[4]_i_10__1_n_0\, - I3 => \Cnt[4]_i_13_n_0\, - I4 => \g0_b2__2_n_0\, - O => \Cnt[3]_i_6_n_0\ - ); -\Cnt[3]_i_6__0\: unisim.vcomponents.LUT3 - generic map( - INIT => X"96" - ) - port map ( - I0 => \TMDS_2/i_Enc/Cnt_reg_n_0_\(3), - I1 => \Cnt[4]_i_10__0_n_0\, - I2 => \g0_b2__4_n_0\, - O => \Cnt[3]_i_6__0_n_0\ - ); -\Cnt[3]_i_7\: unisim.vcomponents.LUT3 - generic map( - INIT => X"69" - ) - port map ( - I0 => \TMDS_0/i_Enc/Cnt_reg_n_0_\(3), - I1 => \Cnt[4]_i_13_n_0\, - I2 => \g0_b2__2_n_0\, - O => \Cnt[3]_i_7_n_0\ - ); -\Cnt[3]_i_8\: unisim.vcomponents.LUT6 - generic map( - INIT => X"4B44222DB4BBDDD2" - ) - port map ( - I0 => g0_b2_i_1_n_0, - I1 => \TMDS_0/i_Enc/p_10_in\, - I2 => \g0_b0__2_n_0\, - I3 => \sReg[5]_i_4_n_0\, - I4 => \TMDS_0/i_Enc/p_12_in\, - I5 => \g0_b1__2_n_0\, - O => \Cnt[3]_i_8_n_0\ - ); -\Cnt[4]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"7" - ) - port map ( - I0 => qDE, - I1 => ResetN, - O => \Cnt[4]_i_1_n_0\ - ); -\Cnt[4]_i_10\: unisim.vcomponents.LUT4 - generic map( - INIT => X"4004" - ) - port map ( - I0 => \Cnt[1]_i_2__0_n_0\, - I1 => \Cnt[4]_i_12__0_n_0\, - I2 => \Cnt[4]_i_13__0_n_0\, - I3 => \g0_b2__3_n_0\, - O => \Cnt[4]_i_10_n_0\ - ); -\Cnt[4]_i_10__0\: unisim.vcomponents.LUT6 - generic map( - INIT => X"E2A0AA28AA288B0A" - ) - port map ( - I0 => \g0_b1__4_n_0\, - I1 => \TMDS_2/i_Enc/p_12_in\, - I2 => \sReg[6]_i_2__1_n_0\, - I3 => \g0_b0__4_n_0\, - I4 => \TMDS_2/i_Enc/p_10_in\, - I5 => \g0_b2_i_1__1_n_0\, - O => \Cnt[4]_i_10__0_n_0\ - ); -\Cnt[4]_i_10__1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"8228811842248228" - ) - port map ( - I0 => \g0_b1__2_n_0\, - I1 => \TMDS_0/i_Enc/p_12_in\, - I2 => \sReg[5]_i_4_n_0\, - I3 => \g0_b0__2_n_0\, - I4 => \TMDS_0/i_Enc/p_10_in\, - I5 => g0_b2_i_1_n_0, - O => \Cnt[4]_i_10__1_n_0\ - ); -\Cnt[4]_i_11\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => \g0_b2__2_n_0\, - I1 => \Cnt[4]_i_13_n_0\, - O => \Cnt[4]_i_11_n_0\ - ); -\Cnt[4]_i_11__0\: unisim.vcomponents.LUT2 - generic map( - INIT => X"7" - ) - port map ( - I0 => \g0_b2__3_n_0\, - I1 => \Cnt[4]_i_13__0_n_0\, - O => \Cnt[4]_i_11__0_n_0\ - ); -\Cnt[4]_i_11__1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"6A0000A900A96A00" - ) - port map ( - I0 => \g0_b1__4_n_0\, - I1 => \TMDS_2/i_Enc/p_10_in\, - I2 => \g0_b2_i_1__1_n_0\, - I3 => \TMDS_2/i_Enc/p_12_in\, - I4 => \sReg[6]_i_2__1_n_0\, - I5 => \g0_b0__4_n_0\, - O => \Cnt[4]_i_11__1_n_0\ - ); -\Cnt[4]_i_12\: unisim.vcomponents.LUT6 - generic map( - INIT => X"65595665A6655665" - ) - port map ( - I0 => \TMDS_0/i_Enc/Cnt_reg_n_0_\(4), - I1 => \TMDS_0/i_Enc/Cnt_reg_n_0_\(3), - I2 => \g0_b2__2_n_0\, - I3 => \Cnt[4]_i_13_n_0\, - I4 => \Cnt[4]_i_10__1_n_0\, - I5 => \TMDS_0/i_Enc/Cnt_reg_n_0_\(2), - O => \Cnt[4]_i_12_n_0\ - ); -\Cnt[4]_i_12__0\: unisim.vcomponents.LUT6 - generic map( - INIT => X"5F6CC9FAA0933605" - ) - port map ( - I0 => \g0_b2_i_1__0_n_0\, - I1 => \g0_b0__3_n_0\, - I2 => \TMDS_1/i_Enc/p_10_in\, - I3 => \sReg[6]_i_2_n_0\, - I4 => \TMDS_1/i_Enc/p_12_in\, - I5 => \g0_b1__3_n_0\, - O => \Cnt[4]_i_12__0_n_0\ - ); -\Cnt[4]_i_12__1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"D040" - ) - port map ( - I0 => \TMDS_2/i_Enc/Cnt_reg_n_0_\(2), - I1 => \Cnt[1]_i_2_n_0\, - I2 => \Cnt[4]_i_9__1_n_0\, - I3 => \g0_b2_i_1__1_n_0\, - O => \Cnt[4]_i_12__1_n_0\ - ); -\Cnt[4]_i_13\: unisim.vcomponents.LUT6 - generic map( - INIT => X"EFF708102BD40000" - ) - port map ( - I0 => \TMDS_0/i_Enc/p_10_in\, - I1 => \TMDS_0/i_Enc/p_12_in\, - I2 => g0_b2_i_1_n_0, - I3 => \sReg[5]_i_4_n_0\, - I4 => \g0_b1__2_n_0\, - I5 => \g0_b0__2_n_0\, - O => \Cnt[4]_i_13_n_0\ - ); -\Cnt[4]_i_13__0\: unisim.vcomponents.LUT6 - generic map( - INIT => X"2EAA0A82AAB882A0" - ) - port map ( - I0 => \g0_b1__3_n_0\, - I1 => \TMDS_1/i_Enc/p_12_in\, - I2 => \sReg[6]_i_2_n_0\, - I3 => \TMDS_1/i_Enc/p_10_in\, - I4 => \g0_b0__3_n_0\, - I5 => \g0_b2_i_1__0_n_0\, - O => \Cnt[4]_i_13__0_n_0\ - ); -\Cnt[4]_i_13__1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"49326DB3" - ) - port map ( - I0 => \Cnt[1]_i_2_n_0\, - I1 => \TMDS_2/i_Enc/Cnt_reg_n_0_\(2), - I2 => \g0_b2_i_1__1_n_0\, - I3 => \Cnt[4]_i_9__1_n_0\, - I4 => \TMDS_2/i_Enc/Cnt_reg_n_0_\(1), - O => \Cnt[4]_i_13__1_n_0\ - ); -\Cnt[4]_i_14\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0107" - ) - port map ( - I0 => g0_b2_i_1_n_0, - I1 => \Cnt[2]_i_4_n_0\, - I2 => \Cnt[3]_i_8_n_0\, - I3 => \TMDS_0/i_Enc/Cnt_reg_n_0_\(2), - O => \Cnt[4]_i_14_n_0\ - ); -\Cnt[4]_i_14__0\: unisim.vcomponents.LUT5 - generic map( - INIT => X"86319E73" - ) - port map ( - I0 => \Cnt[1]_i_2__0_n_0\, - I1 => \TMDS_1/i_Enc/Cnt_reg_n_0_\(2), - I2 => \g0_b2_i_1__0_n_0\, - I3 => \Cnt[4]_i_12__0_n_0\, - I4 => \TMDS_1/i_Enc/Cnt_reg_n_0_\(1), - O => \Cnt[4]_i_14__0_n_0\ - ); -\Cnt[4]_i_14__1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"5555A959A959AAAA" - ) - port map ( - I0 => \g0_b2__4_n_0\, - I1 => \Cnt[4]_i_20__0_n_0\, - I2 => \Cnt[4]_i_21__0_n_0\, - I3 => \Cnt[4]_i_22_n_0\, - I4 => \Cnt[4]_i_23_n_0\, - I5 => \g0_b1__4_n_0\, - O => \Cnt[4]_i_14__1_n_0\ - ); -\Cnt[4]_i_15\: unisim.vcomponents.LUT5 - generic map( - INIT => X"E8A5A58E" - ) - port map ( - I0 => \TMDS_0/i_Enc/Cnt_reg_n_0_\(2), - I1 => \TMDS_0/i_Enc/Cnt_reg_n_0_\(1), - I2 => \Cnt[3]_i_8_n_0\, - I3 => g0_b2_i_1_n_0, - I4 => \Cnt[2]_i_4_n_0\, - O => \Cnt[4]_i_15_n_0\ - ); -\Cnt[4]_i_15__0\: unisim.vcomponents.LUT4 - generic map( - INIT => X"8FEF" - ) - port map ( - I0 => \TMDS_1/i_Enc/Cnt_reg_n_0_\(2), - I1 => \Cnt[1]_i_2__0_n_0\, - I2 => \Cnt[4]_i_12__0_n_0\, - I3 => \g0_b2_i_1__0_n_0\, - O => \Cnt[4]_i_15__0_n_0\ - ); -\Cnt[4]_i_15__1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"7F" - ) - port map ( - I0 => \g0_b2__4_n_0\, - I1 => \Cnt[4]_i_10__0_n_0\, - I2 => \Cnt[4]_i_11__1_n_0\, - O => \Cnt[4]_i_15__1_n_0\ - ); -\Cnt[4]_i_16\: unisim.vcomponents.LUT3 - generic map( - INIT => X"7F" - ) - port map ( - I0 => \g0_b2__2_n_0\, - I1 => \Cnt[4]_i_13_n_0\, - I2 => \Cnt[4]_i_10__1_n_0\, - O => \Cnt[4]_i_16_n_0\ - ); -\Cnt[4]_i_16__0\: unisim.vcomponents.LUT5 - generic map( - INIT => X"553C55C3" - ) - port map ( - I0 => \TMDS_2/i_Enc/Cnt_reg_n_0_\(2), - I1 => \g0_b2__4_n_0\, - I2 => \Cnt[4]_i_10__0_n_0\, - I3 => \Cnt[4]_i_11__1_n_0\, - I4 => \g0_b2_i_1__1_n_0\, - O => \Cnt[4]_i_16__0_n_0\ - ); -\Cnt[4]_i_16__1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"69" - ) - port map ( - I0 => \TMDS_1/i_Enc/Cnt_reg_n_0_\(3), - I1 => \g0_b2__3_n_0\, - I2 => \Cnt[4]_i_13__0_n_0\, - O => \Cnt[4]_i_16__1_n_0\ - ); -\Cnt[4]_i_17\: unisim.vcomponents.LUT5 - generic map( - INIT => X"D00FDFFF" - ) - port map ( - I0 => \Cnt[4]_i_12__0_n_0\, - I1 => \Cnt[1]_i_2__0_n_0\, - I2 => \g0_b2__3_n_0\, - I3 => \Cnt[4]_i_13__0_n_0\, - I4 => \TMDS_1/i_Enc/Cnt_reg_n_0_\(3), - O => \Cnt[4]_i_17_n_0\ - ); -\Cnt[4]_i_17__0\: unisim.vcomponents.LUT5 - generic map( - INIT => X"A0B41E5F" - ) - port map ( - I0 => \Cnt[1]_i_2_n_0\, - I1 => \g0_b2_i_1__1_n_0\, - I2 => \Cnt[4]_i_9__1_n_0\, - I3 => \TMDS_2/i_Enc/Cnt_reg_n_0_\(1), - I4 => \TMDS_2/i_Enc/Cnt_reg_n_0_\(2), - O => \Cnt[4]_i_17__0_n_0\ - ); -\Cnt[4]_i_18\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0001" - ) - port map ( - I0 => \TMDS_1/i_Enc/Cnt_reg_n_0_\(2), - I1 => \TMDS_1/i_Enc/Cnt_reg_n_0_\(1), - I2 => \TMDS_1/i_Enc/Cnt_reg_n_0_\(3), - I3 => \TMDS_1/i_Enc/Cnt_reg_n_0_\(4), - O => \Cnt[4]_i_18_n_0\ - ); -\Cnt[4]_i_18__0\: unisim.vcomponents.LUT3 - generic map( - INIT => X"6A" - ) - port map ( - I0 => \g0_b2_i_1__1_n_0\, - I1 => \g0_b2__4_n_0\, - I2 => \Cnt[4]_i_10__0_n_0\, - O => \Cnt[4]_i_18__0_n_0\ - ); -\Cnt[4]_i_19\: unisim.vcomponents.LUT2 - generic map( - INIT => X"2" - ) - port map ( - I0 => \Cnt[4]_i_12__0_n_0\, - I1 => \Cnt[1]_i_2__0_n_0\, - O => \Cnt[4]_i_19_n_0\ - ); -\Cnt[4]_i_19__0\: unisim.vcomponents.LUT3 - generic map( - INIT => X"82" - ) - port map ( - I0 => \Cnt[4]_i_11__1_n_0\, - I1 => \Cnt[4]_i_10__0_n_0\, - I2 => \g0_b2__4_n_0\, - O => \Cnt[4]_i_19__0_n_0\ - ); -\Cnt[4]_i_1__0\: unisim.vcomponents.LUT6 - generic map( - INIT => X"B800B8FFB8FFB800" - ) - port map ( - I0 => \Cnt[4]_i_2__0_n_0\, - I1 => \Cnt[4]_i_3__0_n_0\, - I2 => \Cnt[4]_i_4__0_n_0\, - I3 => \Cnt[4]_i_5__0_n_0\, - I4 => \Cnt[4]_i_6__1_n_0\, - I5 => \Cnt[4]_i_7_n_0\, - O => \Cnt[4]_i_1__0_n_0\ - ); -\Cnt[4]_i_1__1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"6F60FFFF6F600000" - ) - port map ( - I0 => \Cnt[4]_i_2__1_n_0\, - I1 => \Cnt[4]_i_3__1_n_0\, - I2 => \Cnt[4]_i_4__1_n_0\, - I3 => \Cnt[4]_i_5__1_n_0\, - I4 => \Cnt[4]_i_6__0_n_0\, - I5 => \Cnt[4]_i_7__0_n_0\, - O => \Cnt[4]_i_1__1_n_0\ - ); -\Cnt[4]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"B800B8FFB8FFB800" - ) - port map ( - I0 => \Cnt[4]_i_3_n_0\, - I1 => \Cnt[4]_i_4_n_0\, - I2 => \Cnt[4]_i_5_n_0\, - I3 => \Cnt[4]_i_6_n_0\, - I4 => \Cnt[4]_i_7__1_n_0\, - I5 => \Cnt[4]_i_8_n_0\, - O => \Cnt[4]_i_2_n_0\ - ); -\Cnt[4]_i_20\: unisim.vcomponents.LUT5 - generic map( - INIT => X"AF87D250" - ) - port map ( - I0 => \Cnt[1]_i_2__0_n_0\, - I1 => \g0_b2_i_1__0_n_0\, - I2 => \Cnt[4]_i_12__0_n_0\, - I3 => \TMDS_1/i_Enc/Cnt_reg_n_0_\(1), - I4 => \TMDS_1/i_Enc/Cnt_reg_n_0_\(2), - O => \Cnt[4]_i_20_n_0\ - ); -\Cnt[4]_i_20__0\: unisim.vcomponents.LUT6 - generic map( - INIT => X"00A230FFFF5DCF00" - ) - port map ( - I0 => \Cnt[4]_i_24_n_0\, - I1 => \g0_b1__1_n_0\, - I2 => \g0_b2_i_3__1_n_0\, - I3 => \g0_b2__1_n_0\, - I4 => \Cnt[4]_i_25_n_0\, - I5 => \sReg[6]_i_2__1_n_0\, - O => \Cnt[4]_i_20__0_n_0\ - ); -\Cnt[4]_i_21\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => \g0_b2__3_n_0\, - I1 => \Cnt[4]_i_13__0_n_0\, - O => \Cnt[4]_i_21_n_0\ - ); -\Cnt[4]_i_21__0\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => \TMDS_2/i_Enc/p_10_in\, - I1 => \TMDS_2/i_Enc/p_12_in\, - O => \Cnt[4]_i_21__0_n_0\ - ); -\Cnt[4]_i_22\: unisim.vcomponents.LUT3 - generic map( - INIT => X"69" - ) - port map ( - I0 => \TMDS_2/i_Enc/p_10_in\, - I1 => \TMDS_2/i_Enc/p_9_in\, - I2 => \TMDS_2/i_Enc/p_8_in\, - O => \Cnt[4]_i_22_n_0\ - ); -\Cnt[4]_i_23\: unisim.vcomponents.LUT4 - generic map( - INIT => X"8228" - ) - port map ( - I0 => \g0_b0__4_n_0\, - I1 => \TMDS_2/i_Enc/p_8_in\, - I2 => \TMDS_2/i_Enc/p_9_in\, - I3 => \TMDS_2/i_Enc/p_12_in\, - O => \Cnt[4]_i_23_n_0\ - ); -\Cnt[4]_i_24\: unisim.vcomponents.LUT6 - generic map( - INIT => X"BFFBFBBFBFFFFFFF" - ) - port map ( - I0 => \TMDS_2/i_Enc/qD_reg_n_0_\(0), - I1 => \g0_b0__1_n_0\, - I2 => \TMDS_2/i_Enc/p_8_in\, - I3 => \TMDS_2/i_Enc/p_12_in\, - I4 => \TMDS_2/i_Enc/p_10_in\, - I5 => \g0_b1__1_n_0\, - O => \Cnt[4]_i_24_n_0\ - ); -\Cnt[4]_i_25\: unisim.vcomponents.LUT5 - generic map( - INIT => X"FF96FFFF" - ) - port map ( - I0 => \TMDS_2/i_Enc/p_10_in\, - I1 => \TMDS_2/i_Enc/p_12_in\, - I2 => \TMDS_2/i_Enc/p_8_in\, - I3 => \g0_b0__1_n_0\, - I4 => \TMDS_2/i_Enc/qD_reg_n_0_\(0), - O => \Cnt[4]_i_25_n_0\ - ); -\Cnt[4]_i_2__0\: unisim.vcomponents.LUT6 - generic map( - INIT => X"177EE881E78E1871" - ) - port map ( - I0 => \Cnt[4]_i_8__0_n_0\, - I1 => \Cnt[4]_i_9__0_n_0\, - I2 => \Cnt[4]_i_10_n_0\, - I3 => \TMDS_1/i_Enc/Cnt_reg_n_0_\(3), - I4 => \TMDS_1/i_Enc/Cnt_reg_n_0_\(4), - I5 => \Cnt[4]_i_11__0_n_0\, - O => \Cnt[4]_i_2__0_n_0\ - ); -\Cnt[4]_i_2__1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"D7D755D7577F5757" - ) - port map ( - I0 => \Cnt[4]_i_8__1_n_0\, - I1 => \Cnt[4]_i_9__1_n_0\, - I2 => \TMDS_2/i_Enc/Cnt_reg_n_0_\(2), - I3 => \TMDS_2/i_Enc/Cnt_reg_n_0_\(1), - I4 => \g0_b2_i_1__1_n_0\, - I5 => \Cnt[1]_i_2_n_0\, - O => \Cnt[4]_i_2__1_n_0\ - ); -\Cnt[4]_i_3\: unisim.vcomponents.LUT6 - generic map( - INIT => X"41111444BEEEEBBB" - ) - port map ( - I0 => \Cnt[4]_i_9_n_0\, - I1 => \TMDS_0/i_Enc/Cnt_reg_n_0_\(3), - I2 => \TMDS_0/i_Enc/Cnt_reg_n_0_\(2), - I3 => \Cnt[4]_i_10__1_n_0\, - I4 => \Cnt[4]_i_11_n_0\, - I5 => \Cnt[4]_i_12_n_0\, - O => \Cnt[4]_i_3_n_0\ - ); -\Cnt[4]_i_3__0\: unisim.vcomponents.LUT5 - generic map( - INIT => X"000FFBB0" - ) - port map ( - I0 => \Cnt[1]_i_2__0_n_0\, - I1 => \Cnt[4]_i_12__0_n_0\, - I2 => \g0_b2__3_n_0\, - I3 => \Cnt[4]_i_13__0_n_0\, - I4 => \TMDS_1/i_Enc/Cnt_reg_n_0_\(4), - O => \Cnt[4]_i_3__0_n_0\ - ); -\Cnt[4]_i_3__1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"5695555595A96969" - ) - port map ( - I0 => \TMDS_2/i_Enc/Cnt_reg_n_0_\(4), - I1 => \g0_b2__4_n_0\, - I2 => \Cnt[4]_i_10__0_n_0\, - I3 => \TMDS_2/i_Enc/Cnt_reg_n_0_\(2), - I4 => \Cnt[4]_i_11__1_n_0\, - I5 => \TMDS_2/i_Enc/Cnt_reg_n_0_\(3), - O => \Cnt[4]_i_3__1_n_0\ - ); -\Cnt[4]_i_4\: unisim.vcomponents.LUT4 - generic map( - INIT => X"03D4" - ) - port map ( - I0 => \Cnt[4]_i_10__1_n_0\, - I1 => \g0_b2__2_n_0\, - I2 => \Cnt[4]_i_13_n_0\, - I3 => \TMDS_0/i_Enc/Cnt_reg_n_0_\(4), - O => \Cnt[4]_i_4_n_0\ - ); -\Cnt[4]_i_4__0\: unisim.vcomponents.LUT5 - generic map( - INIT => X"4DB2B24D" - ) - port map ( - I0 => \Cnt[4]_i_14__0_n_0\, - I1 => \Cnt[4]_i_15__0_n_0\, - I2 => \Cnt[4]_i_16__1_n_0\, - I3 => \Cnt[4]_i_17_n_0\, - I4 => \TMDS_1/i_Enc/Cnt_reg_n_0_\(4), - O => \Cnt[4]_i_4__0_n_0\ - ); -\Cnt[4]_i_4__1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"03D4" - ) - port map ( - I0 => \Cnt[4]_i_11__1_n_0\, - I1 => \g0_b2__4_n_0\, - I2 => \Cnt[4]_i_10__0_n_0\, - I3 => \TMDS_2/i_Enc/Cnt_reg_n_0_\(4), - O => \Cnt[4]_i_4__1_n_0\ - ); -\Cnt[4]_i_5\: unisim.vcomponents.LUT6 - generic map( - INIT => X"BBD2D24B442D2DB4" - ) - port map ( - I0 => \Cnt[4]_i_14_n_0\, - I1 => \Cnt[4]_i_15_n_0\, - I2 => \Cnt[4]_i_16_n_0\, - I3 => \TMDS_0/i_Enc/Cnt_reg_n_0_\(3), - I4 => \Cnt[4]_i_11_n_0\, - I5 => \TMDS_0/i_Enc/Cnt_reg_n_0_\(4), - O => \Cnt[4]_i_5_n_0\ - ); -\Cnt[4]_i_5__0\: unisim.vcomponents.LUT5 - generic map( - INIT => X"0000FDDF" - ) - port map ( - I0 => \Cnt[4]_i_12__0_n_0\, - I1 => \Cnt[1]_i_2__0_n_0\, - I2 => \g0_b2__3_n_0\, - I3 => \Cnt[4]_i_13__0_n_0\, - I4 => \Cnt[4]_i_18_n_0\, - O => \Cnt[4]_i_5__0_n_0\ - ); -\Cnt[4]_i_5__1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"E771E88E188E1771" - ) - port map ( - I0 => \Cnt[4]_i_12__1_n_0\, - I1 => \Cnt[4]_i_13__1_n_0\, - I2 => \Cnt[4]_i_14__1_n_0\, - I3 => \TMDS_2/i_Enc/Cnt_reg_n_0_\(3), - I4 => \Cnt[4]_i_15__1_n_0\, - I5 => \TMDS_2/i_Enc/Cnt_reg_n_0_\(4), - O => \Cnt[4]_i_5__1_n_0\ - ); -\Cnt[4]_i_6\: unisim.vcomponents.LUT6 - generic map( - INIT => X"7777777777777770" - ) - port map ( - I0 => \Cnt[4]_i_10__1_n_0\, - I1 => \Cnt[4]_i_11_n_0\, - I2 => \TMDS_0/i_Enc/Cnt_reg_n_0_\(3), - I3 => \TMDS_0/i_Enc/Cnt_reg_n_0_\(2), - I4 => \TMDS_0/i_Enc/Cnt_reg_n_0_\(1), - I5 => \TMDS_0/i_Enc/Cnt_reg_n_0_\(4), - O => \Cnt[4]_i_6_n_0\ - ); -\Cnt[4]_i_6__0\: unisim.vcomponents.LUT6 - generic map( - INIT => X"7777777777777770" - ) - port map ( - I0 => \Cnt[4]_i_11__1_n_0\, - I1 => \Cnt[4]_i_14__1_n_0\, - I2 => \TMDS_2/i_Enc/Cnt_reg_n_0_\(4), - I3 => \TMDS_2/i_Enc/Cnt_reg_n_0_\(3), - I4 => \TMDS_2/i_Enc/Cnt_reg_n_0_\(1), - I5 => \TMDS_2/i_Enc/Cnt_reg_n_0_\(2), - O => \Cnt[4]_i_6__0_n_0\ - ); -\Cnt[4]_i_6__1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"599A9999A9959999" - ) - port map ( - I0 => \TMDS_1/i_Enc/Cnt_reg_n_0_\(4), - I1 => \TMDS_1/i_Enc/Cnt_reg_n_0_\(3), - I2 => \g0_b2__3_n_0\, - I3 => \Cnt[4]_i_13__0_n_0\, - I4 => \Cnt[4]_i_19_n_0\, - I5 => \g0_b2_i_1__0_n_0\, - O => \Cnt[4]_i_6__1_n_0\ - ); -\Cnt[4]_i_7\: unisim.vcomponents.LUT6 - generic map( - INIT => X"8E0A8EA0E8AFE8FA" - ) - port map ( - I0 => \Cnt[4]_i_20_n_0\, - I1 => \TMDS_1/i_Enc/Cnt_reg_n_0_\(2), - I2 => \Cnt[4]_i_21_n_0\, - I3 => \Cnt[4]_i_19_n_0\, - I4 => \g0_b2_i_1__0_n_0\, - I5 => \TMDS_1/i_Enc/Cnt_reg_n_0_\(3), - O => \Cnt[4]_i_7_n_0\ - ); -\Cnt[4]_i_7__0\: unisim.vcomponents.LUT6 - generic map( - INIT => X"87EEE17778111E88" - ) - port map ( - I0 => \Cnt[4]_i_16__0_n_0\, - I1 => \Cnt[4]_i_17__0_n_0\, - I2 => \Cnt[4]_i_18__0_n_0\, - I3 => \Cnt[4]_i_19__0_n_0\, - I4 => \TMDS_2/i_Enc/Cnt_reg_n_0_\(3), - I5 => \TMDS_2/i_Enc/Cnt_reg_n_0_\(4), - O => \Cnt[4]_i_7__0_n_0\ - ); -\Cnt[4]_i_7__1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"A9959999599A9999" - ) - port map ( - I0 => \TMDS_0/i_Enc/Cnt_reg_n_0_\(4), - I1 => \TMDS_0/i_Enc/Cnt_reg_n_0_\(3), - I2 => \g0_b2__2_n_0\, - I3 => \Cnt[4]_i_13_n_0\, - I4 => \Cnt[4]_i_10__1_n_0\, - I5 => g0_b2_i_1_n_0, - O => \Cnt[4]_i_7__1_n_0\ - ); -\Cnt[4]_i_8\: unisim.vcomponents.LUT6 - generic map( - INIT => X"BB822282EEEB88EB" - ) - port map ( - I0 => \Cnt[3]_i_3_n_0\, - I1 => \Cnt[4]_i_11_n_0\, - I2 => g0_b2_i_1_n_0, - I3 => \Cnt[4]_i_10__1_n_0\, - I4 => \TMDS_0/i_Enc/Cnt_reg_n_0_\(2), - I5 => \TMDS_0/i_Enc/Cnt_reg_n_0_\(3), - O => \Cnt[4]_i_8_n_0\ - ); -\Cnt[4]_i_8__0\: unisim.vcomponents.LUT5 - generic map( - INIT => X"BAF7F710" - ) - port map ( - I0 => \Cnt[1]_i_2__0_n_0\, - I1 => \g0_b2_i_1__0_n_0\, - I2 => \TMDS_1/i_Enc/Cnt_reg_n_0_\(1), - I3 => \TMDS_1/i_Enc/Cnt_reg_n_0_\(2), - I4 => \Cnt[4]_i_12__0_n_0\, - O => \Cnt[4]_i_8__0_n_0\ - ); -\Cnt[4]_i_8__1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"6A95956A" - ) - port map ( - I0 => \TMDS_2/i_Enc/Cnt_reg_n_0_\(3), - I1 => \Cnt[4]_i_11__1_n_0\, - I2 => \TMDS_2/i_Enc/Cnt_reg_n_0_\(2), - I3 => \Cnt[4]_i_10__0_n_0\, - I4 => \g0_b2__4_n_0\, - O => \Cnt[4]_i_8__1_n_0\ - ); -\Cnt[4]_i_9\: unisim.vcomponents.LUT5 - generic map( - INIT => X"02BF1502" - ) - port map ( - I0 => \Cnt[2]_i_4_n_0\, - I1 => g0_b2_i_1_n_0, - I2 => \TMDS_0/i_Enc/Cnt_reg_n_0_\(1), - I3 => \TMDS_0/i_Enc/Cnt_reg_n_0_\(2), - I4 => \Cnt[3]_i_8_n_0\, - O => \Cnt[4]_i_9_n_0\ - ); -\Cnt[4]_i_9__0\: unisim.vcomponents.LUT5 - generic map( - INIT => X"9999F099" - ) - port map ( - I0 => \g0_b2__3_n_0\, - I1 => \Cnt[4]_i_13__0_n_0\, - I2 => \TMDS_1/i_Enc/Cnt_reg_n_0_\(2), - I3 => \Cnt[4]_i_12__0_n_0\, - I4 => \Cnt[1]_i_2__0_n_0\, - O => \Cnt[4]_i_9__0_n_0\ - ); -\Cnt[4]_i_9__1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"7877EEE18788111E" - ) - port map ( - I0 => \g0_b2_i_1__1_n_0\, - I1 => \TMDS_2/i_Enc/p_10_in\, - I2 => \g0_b0__4_n_0\, - I3 => \sReg[6]_i_2__1_n_0\, - I4 => \TMDS_2/i_Enc/p_12_in\, - I5 => \g0_b1__4_n_0\, - O => \Cnt[4]_i_9__1_n_0\ - ); -\Cnt_reg[2]_i_1\: unisim.vcomponents.MUXF7 - port map ( - I0 => \Cnt[2]_i_2__0_n_0\, - I1 => \Cnt[2]_i_3__0_n_0\, - O => \Cnt_reg[2]_i_1_n_0\, - S => \Cnt[4]_i_5__0_n_0\ - ); -\Cnt_reg[2]_i_1__0\: unisim.vcomponents.MUXF7 - port map ( - I0 => \Cnt[2]_i_2__1_n_0\, - I1 => \Cnt[2]_i_3__1_n_0\, - O => \Cnt_reg[2]_i_1__0_n_0\, - S => \Cnt[4]_i_6__0_n_0\ - ); -\Cnt_reg[3]_i_1\: unisim.vcomponents.MUXF7 - port map ( - I0 => \Cnt[3]_i_2__1_n_0\, - I1 => \Cnt[3]_i_3__1_n_0\, - O => \Cnt_reg[3]_i_1_n_0\, - S => \Cnt[4]_i_6__0_n_0\ - ); -\TMDS_0/i_Enc/Cnt_reg[1]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClk, - CE => '1', - D => \Cnt[1]_i_1_n_0\, - Q => \TMDS_0/i_Enc/Cnt_reg_n_0_\(1), - R => \Cnt[4]_i_1_n_0\ - ); -\TMDS_0/i_Enc/Cnt_reg[2]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClk, - CE => '1', - D => \Cnt[2]_i_1_n_0\, - Q => \TMDS_0/i_Enc/Cnt_reg_n_0_\(2), - R => \Cnt[4]_i_1_n_0\ - ); -\TMDS_0/i_Enc/Cnt_reg[3]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClk, - CE => '1', - D => \Cnt[3]_i_1_n_0\, - Q => \TMDS_0/i_Enc/Cnt_reg_n_0_\(3), - R => \Cnt[4]_i_1_n_0\ - ); -\TMDS_0/i_Enc/Cnt_reg[4]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClk, - CE => '1', - D => \Cnt[4]_i_2_n_0\, - Q => \TMDS_0/i_Enc/Cnt_reg_n_0_\(4), - R => \Cnt[4]_i_1_n_0\ - ); -\TMDS_0/i_Enc/qC1C0_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClk, - CE => '1', - D => HSync, - Q => qC1C0(0), - R => '0' - ); -\TMDS_0/i_Enc/qC1C0_reg[1]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClk, - CE => '1', - D => VSync, - Q => qC1C0(1), - R => '0' - ); -\TMDS_0/i_Enc/qDE_reg\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClk, - CE => '1', - D => DE, - Q => qDE, - R => '0' - ); -\TMDS_0/i_Enc/qD_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClk, - CE => '1', - D => B(0), - Q => \TMDS_0/i_Enc/qD_reg_n_0_\(0), - R => '0' - ); -\TMDS_0/i_Enc/qD_reg[1]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClk, - CE => '1', - D => B(1), - Q => \TMDS_0/i_Enc/p_0_in\, - R => '0' - ); -\TMDS_0/i_Enc/qD_reg[2]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClk, - CE => '1', - D => B(2), - Q => \TMDS_0/i_Enc/p_2_in\, - R => '0' - ); -\TMDS_0/i_Enc/qD_reg[3]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClk, - CE => '1', - D => B(3), - Q => \TMDS_0/i_Enc/p_4_in\, - R => '0' - ); -\TMDS_0/i_Enc/qD_reg[4]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClk, - CE => '1', - D => B(4), - Q => \TMDS_0/i_Enc/p_6_in\, - R => '0' - ); -\TMDS_0/i_Enc/qD_reg[5]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClk, - CE => '1', - D => B(5), - Q => \TMDS_0/i_Enc/p_8_in\, - R => '0' - ); -\TMDS_0/i_Enc/qD_reg[6]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClk, - CE => '1', - D => B(6), - Q => \TMDS_0/i_Enc/p_10_in\, - R => '0' - ); -\TMDS_0/i_Enc/qD_reg[7]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClk, - CE => '1', - D => B(7), - Q => \TMDS_0/i_Enc/p_12_in\, - R => '0' - ); -\TMDS_0/i_GBox/cntMod5_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClkX5, - CE => '1', - D => plusOp(0), - Q => \TMDS_0/i_GBox/cntMod5_reg_n_0_\(0), - R => \cntMod5[2]_i_1_n_0\ - ); -\TMDS_0/i_GBox/cntMod5_reg[1]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClkX5, - CE => '1', - D => plusOp(1), - Q => \TMDS_0/i_GBox/cntMod5_reg_n_0_\(1), - R => \cntMod5[2]_i_1_n_0\ - ); -\TMDS_0/i_GBox/cntMod5_reg[2]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClkX5, - CE => '1', - D => plusOp(2), - Q => \TMDS_0/i_GBox/cntMod5_reg_n_0_\(2), - R => \cntMod5[2]_i_1_n_0\ - ); -\TMDS_0/i_GBox/sReg_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClkX5, - CE => '1', - D => \sReg[0]_i_1_n_0\, - Q => \TMDS_0/D1\, - R => \TMDS_3/Reset\ - ); -\TMDS_0/i_GBox/sReg_reg[1]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClkX5, - CE => '1', - D => \sReg[1]_i_1_n_0\, - Q => \TMDS_0/D2\, - R => \TMDS_3/Reset\ - ); -\TMDS_0/i_GBox/sReg_reg[2]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClkX5, - CE => '1', - D => \sReg[2]_i_1_n_0\, - Q => \TMDS_0/i_GBox/sReg_reg_n_0_\(2), - R => \TMDS_3/Reset\ - ); -\TMDS_0/i_GBox/sReg_reg[3]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClkX5, - CE => '1', - D => \sReg[3]_i_1_n_0\, - Q => \TMDS_0/i_GBox/sReg_reg_n_0_\(3), - R => \TMDS_3/Reset\ - ); -\TMDS_0/i_GBox/sReg_reg[4]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClkX5, - CE => '1', - D => \sReg[4]_i_1_n_0\, - Q => \TMDS_0/i_GBox/sReg_reg_n_0_\(4), - R => \TMDS_3/Reset\ - ); -\TMDS_0/i_GBox/sReg_reg[5]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClkX5, - CE => '1', - D => \sReg[5]_i_1_n_0\, - Q => \TMDS_0/i_GBox/sReg_reg_n_0_\(5), - R => \TMDS_3/Reset\ - ); -\TMDS_0/i_GBox/sReg_reg[6]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClkX5, - CE => '1', - D => \sReg[6]_i_1_n_0\, - Q => \TMDS_0/i_GBox/sReg_reg_n_0_\(6), - R => \TMDS_3/Reset\ - ); -\TMDS_0/i_GBox/sReg_reg[7]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClkX5, - CE => '1', - D => \sReg[7]_i_1_n_0\, - Q => \TMDS_0/i_GBox/sReg_reg_n_0_\(7), - R => \TMDS_3/Reset\ - ); -\TMDS_0/i_GBox/sReg_reg[8]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClkX5, - CE => '1', - D => \sReg[8]_i_1_n_0\, - Q => \TMDS_0/i_GBox/sReg_reg_n_0_\(8), - R => \TMDS_3/Reset\ - ); -\TMDS_0/i_GBox/sReg_reg[9]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClkX5, - CE => '1', - D => \sReg[9]_i_1_n_0\, - Q => \TMDS_0/i_GBox/sReg_reg_n_0_\(9), - R => \TMDS_3/Reset\ - ); -\TMDS_0/i_ODDRE_N\: unisim.vcomponents.OSERDESE3 - generic map( - DATA_WIDTH => 8, - INIT => '0', - IS_CLK_INVERTED => '0', - ODDR_MODE => "TRUE", - OSERDES_D_BYPASS => "FALSE", - OSERDES_T_BYPASS => "TRUE", - SIM_DEVICE => "ULTRASCALE_PLUS", - SIM_VERSION => 2.000000 - ) - port map ( - CLK => pxClkX5, - CLKDIV => \NLW_TMDS_0/i_ODDRE_N_CLKDIV_UNCONNECTED\, - D(7 downto 5) => \NLW_TMDS_0/i_ODDRE_N_D_UNCONNECTED\(7 downto 5), - D(4) => \i_ODDRE_N_i_2__0_n_0\, - D(3 downto 1) => \NLW_TMDS_0/i_ODDRE_N_D_UNCONNECTED\(3 downto 1), - D(0) => i_ODDRE_N_i_1_n_0, - OQ => HDMI_D0_N, - RST => \TMDS_3/Reset\, - T => '0', - T_OUT => \NLW_TMDS_0/i_ODDRE_N_T_OUT_UNCONNECTED\ - ); -\TMDS_0/i_ODDRE_P\: unisim.vcomponents.OSERDESE3 - generic map( - DATA_WIDTH => 8, - INIT => '0', - IS_CLK_INVERTED => '0', - ODDR_MODE => "TRUE", - OSERDES_D_BYPASS => "FALSE", - OSERDES_T_BYPASS => "TRUE", - SIM_DEVICE => "ULTRASCALE_PLUS", - SIM_VERSION => 2.000000 - ) - port map ( - CLK => pxClkX5, - CLKDIV => \NLW_TMDS_0/i_ODDRE_P_CLKDIV_UNCONNECTED\, - D(7 downto 5) => \NLW_TMDS_0/i_ODDRE_P_D_UNCONNECTED\(7 downto 5), - D(4) => \TMDS_0/D2\, - D(3 downto 1) => \NLW_TMDS_0/i_ODDRE_P_D_UNCONNECTED\(3 downto 1), - D(0) => \TMDS_0/D1\, - OQ => HDMI_D0_P, - RST => \TMDS_3/Reset\, - T => '0', - T_OUT => \NLW_TMDS_0/i_ODDRE_P_T_OUT_UNCONNECTED\ - ); -\TMDS_1/i_Enc/Cnt_reg[1]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClk, - CE => '1', - D => \Cnt[1]_i_1__0_n_0\, - Q => \TMDS_1/i_Enc/Cnt_reg_n_0_\(1), - R => \Cnt[4]_i_1_n_0\ - ); -\TMDS_1/i_Enc/Cnt_reg[2]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClk, - CE => '1', - D => \Cnt_reg[2]_i_1_n_0\, - Q => \TMDS_1/i_Enc/Cnt_reg_n_0_\(2), - R => \Cnt[4]_i_1_n_0\ - ); -\TMDS_1/i_Enc/Cnt_reg[3]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClk, - CE => '1', - D => \Cnt[3]_i_1__0_n_0\, - Q => \TMDS_1/i_Enc/Cnt_reg_n_0_\(3), - R => \Cnt[4]_i_1_n_0\ - ); -\TMDS_1/i_Enc/Cnt_reg[4]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClk, - CE => '1', - D => \Cnt[4]_i_1__0_n_0\, - Q => \TMDS_1/i_Enc/Cnt_reg_n_0_\(4), - R => \Cnt[4]_i_1_n_0\ - ); -\TMDS_1/i_Enc/qD_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClk, - CE => '1', - D => G(0), - Q => \TMDS_1/i_Enc/qD_reg_n_0_\(0), - R => '0' - ); -\TMDS_1/i_Enc/qD_reg[1]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClk, - CE => '1', - D => G(1), - Q => \TMDS_1/i_Enc/p_0_in\, - R => '0' - ); -\TMDS_1/i_Enc/qD_reg[2]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClk, - CE => '1', - D => G(2), - Q => \TMDS_1/i_Enc/p_2_in\, - R => '0' - ); -\TMDS_1/i_Enc/qD_reg[3]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClk, - CE => '1', - D => G(3), - Q => \TMDS_1/i_Enc/p_4_in\, - R => '0' - ); -\TMDS_1/i_Enc/qD_reg[4]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClk, - CE => '1', - D => G(4), - Q => \TMDS_1/i_Enc/p_6_in\, - R => '0' - ); -\TMDS_1/i_Enc/qD_reg[5]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClk, - CE => '1', - D => G(5), - Q => \TMDS_1/i_Enc/p_8_in\, - R => '0' - ); -\TMDS_1/i_Enc/qD_reg[6]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClk, - CE => '1', - D => G(6), - Q => \TMDS_1/i_Enc/p_10_in\, - R => '0' - ); -\TMDS_1/i_Enc/qD_reg[7]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClk, - CE => '1', - D => G(7), - Q => \TMDS_1/i_Enc/p_12_in\, - R => '0' - ); -\TMDS_1/i_GBox/cntMod5_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClkX5, - CE => '1', - D => \cntMod5[0]_i_1__0_n_0\, - Q => \TMDS_1/i_GBox/cntMod5_reg_n_0_\(0), - R => \cntMod5[2]_i_1__0_n_0\ - ); -\TMDS_1/i_GBox/cntMod5_reg[1]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClkX5, - CE => '1', - D => \cntMod5[1]_i_1__0_n_0\, - Q => \TMDS_1/i_GBox/cntMod5_reg_n_0_\(1), - R => \cntMod5[2]_i_1__0_n_0\ - ); -\TMDS_1/i_GBox/cntMod5_reg[2]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClkX5, - CE => '1', - D => \cntMod5[2]_i_2__0_n_0\, - Q => \TMDS_1/i_GBox/cntMod5_reg_n_0_\(2), - R => \cntMod5[2]_i_1__0_n_0\ - ); -\TMDS_1/i_GBox/sReg_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClkX5, - CE => '1', - D => \sReg[0]_i_1__0_n_0\, - Q => \TMDS_1/D1\, - R => \TMDS_3/Reset\ - ); -\TMDS_1/i_GBox/sReg_reg[1]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClkX5, - CE => '1', - D => \sReg[1]_i_1__0_n_0\, - Q => \TMDS_1/D2\, - R => \TMDS_3/Reset\ - ); -\TMDS_1/i_GBox/sReg_reg[2]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClkX5, - CE => '1', - D => \sReg[2]_i_1__0_n_0\, - Q => \TMDS_1/i_GBox/sReg_reg_n_0_\(2), - R => \TMDS_3/Reset\ - ); -\TMDS_1/i_GBox/sReg_reg[3]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClkX5, - CE => '1', - D => \sReg[3]_i_1__0_n_0\, - Q => \TMDS_1/i_GBox/sReg_reg_n_0_\(3), - R => \TMDS_3/Reset\ - ); -\TMDS_1/i_GBox/sReg_reg[4]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClkX5, - CE => '1', - D => \sReg[4]_i_1__0_n_0\, - Q => \TMDS_1/i_GBox/sReg_reg_n_0_\(4), - R => \TMDS_3/Reset\ - ); -\TMDS_1/i_GBox/sReg_reg[5]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClkX5, - CE => '1', - D => \sReg[5]_i_1__0_n_0\, - Q => \TMDS_1/i_GBox/sReg_reg_n_0_\(5), - R => \TMDS_3/Reset\ - ); -\TMDS_1/i_GBox/sReg_reg[6]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClkX5, - CE => '1', - D => \sReg[6]_i_1__0_n_0\, - Q => \TMDS_1/i_GBox/sReg_reg_n_0_\(6), - R => \TMDS_3/Reset\ - ); -\TMDS_1/i_GBox/sReg_reg[7]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClkX5, - CE => '1', - D => \sReg[7]_i_1__0_n_0\, - Q => \TMDS_1/i_GBox/sReg_reg_n_0_\(7), - R => \TMDS_3/Reset\ - ); -\TMDS_1/i_GBox/sReg_reg[8]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClkX5, - CE => '1', - D => \sReg[8]_i_1__0_n_0\, - Q => \TMDS_1/i_GBox/sReg_reg_n_0_\(8), - R => \TMDS_3/Reset\ - ); -\TMDS_1/i_GBox/sReg_reg[9]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClkX5, - CE => '1', - D => \sReg[9]_i_1__0_n_0\, - Q => \TMDS_1/i_GBox/sReg_reg_n_0_\(9), - R => \TMDS_3/Reset\ - ); -\TMDS_1/i_ODDRE_N\: unisim.vcomponents.OSERDESE3 - generic map( - DATA_WIDTH => 8, - INIT => '0', - IS_CLK_INVERTED => '0', - ODDR_MODE => "TRUE", - OSERDES_D_BYPASS => "FALSE", - OSERDES_T_BYPASS => "TRUE", - SIM_DEVICE => "ULTRASCALE_PLUS", - SIM_VERSION => 2.000000 - ) - port map ( - CLK => pxClkX5, - CLKDIV => \NLW_TMDS_1/i_ODDRE_N_CLKDIV_UNCONNECTED\, - D(7 downto 5) => \NLW_TMDS_1/i_ODDRE_N_D_UNCONNECTED\(7 downto 5), - D(4) => \i_ODDRE_N_i_2__1_n_0\, - D(3 downto 1) => \NLW_TMDS_1/i_ODDRE_N_D_UNCONNECTED\(3 downto 1), - D(0) => \i_ODDRE_N_i_1__0_n_0\, - OQ => HDMI_D1_N, - RST => \TMDS_3/Reset\, - T => '0', - T_OUT => \NLW_TMDS_1/i_ODDRE_N_T_OUT_UNCONNECTED\ - ); -\TMDS_1/i_ODDRE_P\: unisim.vcomponents.OSERDESE3 - generic map( - DATA_WIDTH => 8, - INIT => '0', - IS_CLK_INVERTED => '0', - ODDR_MODE => "TRUE", - OSERDES_D_BYPASS => "FALSE", - OSERDES_T_BYPASS => "TRUE", - SIM_DEVICE => "ULTRASCALE_PLUS", - SIM_VERSION => 2.000000 - ) - port map ( - CLK => pxClkX5, - CLKDIV => \NLW_TMDS_1/i_ODDRE_P_CLKDIV_UNCONNECTED\, - D(7 downto 5) => \NLW_TMDS_1/i_ODDRE_P_D_UNCONNECTED\(7 downto 5), - D(4) => \TMDS_1/D2\, - D(3 downto 1) => \NLW_TMDS_1/i_ODDRE_P_D_UNCONNECTED\(3 downto 1), - D(0) => \TMDS_1/D1\, - OQ => HDMI_D1_P, - RST => \TMDS_3/Reset\, - T => '0', - T_OUT => \NLW_TMDS_1/i_ODDRE_P_T_OUT_UNCONNECTED\ - ); -\TMDS_2/i_Enc/Cnt_reg[1]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClk, - CE => '1', - D => \Cnt[1]_i_1__1_n_0\, - Q => \TMDS_2/i_Enc/Cnt_reg_n_0_\(1), - R => \Cnt[4]_i_1_n_0\ - ); -\TMDS_2/i_Enc/Cnt_reg[2]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClk, - CE => '1', - D => \Cnt_reg[2]_i_1__0_n_0\, - Q => \TMDS_2/i_Enc/Cnt_reg_n_0_\(2), - R => \Cnt[4]_i_1_n_0\ - ); -\TMDS_2/i_Enc/Cnt_reg[3]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClk, - CE => '1', - D => \Cnt_reg[3]_i_1_n_0\, - Q => \TMDS_2/i_Enc/Cnt_reg_n_0_\(3), - R => \Cnt[4]_i_1_n_0\ - ); -\TMDS_2/i_Enc/Cnt_reg[4]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClk, - CE => '1', - D => \Cnt[4]_i_1__1_n_0\, - Q => \TMDS_2/i_Enc/Cnt_reg_n_0_\(4), - R => \Cnt[4]_i_1_n_0\ - ); -\TMDS_2/i_Enc/qD_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClk, - CE => '1', - D => R(0), - Q => \TMDS_2/i_Enc/qD_reg_n_0_\(0), - R => '0' - ); -\TMDS_2/i_Enc/qD_reg[1]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClk, - CE => '1', - D => R(1), - Q => \TMDS_2/i_Enc/p_0_in\, - R => '0' - ); -\TMDS_2/i_Enc/qD_reg[2]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClk, - CE => '1', - D => R(2), - Q => \TMDS_2/i_Enc/p_2_in\, - R => '0' - ); -\TMDS_2/i_Enc/qD_reg[3]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClk, - CE => '1', - D => R(3), - Q => \TMDS_2/i_Enc/p_4_in\, - R => '0' - ); -\TMDS_2/i_Enc/qD_reg[4]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClk, - CE => '1', - D => R(4), - Q => \TMDS_2/i_Enc/p_6_in\, - R => '0' - ); -\TMDS_2/i_Enc/qD_reg[5]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClk, - CE => '1', - D => R(5), - Q => \TMDS_2/i_Enc/p_8_in\, - R => '0' - ); -\TMDS_2/i_Enc/qD_reg[6]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClk, - CE => '1', - D => R(6), - Q => \TMDS_2/i_Enc/p_10_in\, - R => '0' - ); -\TMDS_2/i_Enc/qD_reg[7]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClk, - CE => '1', - D => R(7), - Q => \TMDS_2/i_Enc/p_12_in\, - R => '0' - ); -\TMDS_2/i_GBox/cntMod5_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClkX5, - CE => '1', - D => \cntMod5[0]_i_1__1_n_0\, - Q => \TMDS_2/i_GBox/cntMod5_reg_n_0_\(0), - R => \cntMod5[2]_i_1__1_n_0\ - ); -\TMDS_2/i_GBox/cntMod5_reg[1]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClkX5, - CE => '1', - D => \cntMod5[1]_i_1__1_n_0\, - Q => \TMDS_2/i_GBox/cntMod5_reg_n_0_\(1), - R => \cntMod5[2]_i_1__1_n_0\ - ); -\TMDS_2/i_GBox/cntMod5_reg[2]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClkX5, - CE => '1', - D => \cntMod5[2]_i_2__1_n_0\, - Q => \TMDS_2/i_GBox/cntMod5_reg_n_0_\(2), - R => \cntMod5[2]_i_1__1_n_0\ - ); -\TMDS_2/i_GBox/sReg_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClkX5, - CE => '1', - D => \sReg[0]_i_1__1_n_0\, - Q => \TMDS_2/D1\, - R => \TMDS_3/Reset\ - ); -\TMDS_2/i_GBox/sReg_reg[1]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClkX5, - CE => '1', - D => \sReg[1]_i_1__1_n_0\, - Q => \TMDS_2/D2\, - R => \TMDS_3/Reset\ - ); -\TMDS_2/i_GBox/sReg_reg[2]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClkX5, - CE => '1', - D => \sReg[2]_i_1__1_n_0\, - Q => \TMDS_2/i_GBox/sReg_reg_n_0_\(2), - R => \TMDS_3/Reset\ - ); -\TMDS_2/i_GBox/sReg_reg[3]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClkX5, - CE => '1', - D => \sReg[3]_i_1__1_n_0\, - Q => \TMDS_2/i_GBox/sReg_reg_n_0_\(3), - R => \TMDS_3/Reset\ - ); -\TMDS_2/i_GBox/sReg_reg[4]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClkX5, - CE => '1', - D => \sReg[4]_i_1__1_n_0\, - Q => \TMDS_2/i_GBox/sReg_reg_n_0_\(4), - R => \TMDS_3/Reset\ - ); -\TMDS_2/i_GBox/sReg_reg[5]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClkX5, - CE => '1', - D => \sReg[5]_i_1__1_n_0\, - Q => \TMDS_2/i_GBox/sReg_reg_n_0_\(5), - R => \TMDS_3/Reset\ - ); -\TMDS_2/i_GBox/sReg_reg[6]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClkX5, - CE => '1', - D => \sReg[6]_i_1__1_n_0\, - Q => \TMDS_2/i_GBox/sReg_reg_n_0_\(6), - R => \TMDS_3/Reset\ - ); -\TMDS_2/i_GBox/sReg_reg[7]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClkX5, - CE => '1', - D => \sReg[7]_i_1__1_n_0\, - Q => \TMDS_2/i_GBox/sReg_reg_n_0_\(7), - R => \TMDS_3/Reset\ - ); -\TMDS_2/i_GBox/sReg_reg[8]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClkX5, - CE => '1', - D => \sReg[8]_i_1__1_n_0\, - Q => \TMDS_2/i_GBox/sReg_reg_n_0_\(8), - R => \TMDS_3/Reset\ - ); -\TMDS_2/i_GBox/sReg_reg[9]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClkX5, - CE => '1', - D => \sReg[9]_i_1__1_n_0\, - Q => \TMDS_2/i_GBox/sReg_reg_n_0_\(9), - R => \TMDS_3/Reset\ - ); -\TMDS_2/i_ODDRE_N\: unisim.vcomponents.OSERDESE3 - generic map( - DATA_WIDTH => 8, - INIT => '0', - IS_CLK_INVERTED => '0', - ODDR_MODE => "TRUE", - OSERDES_D_BYPASS => "FALSE", - OSERDES_T_BYPASS => "TRUE", - SIM_DEVICE => "ULTRASCALE_PLUS", - SIM_VERSION => 2.000000 - ) - port map ( - CLK => pxClkX5, - CLKDIV => \NLW_TMDS_2/i_ODDRE_N_CLKDIV_UNCONNECTED\, - D(7 downto 5) => \NLW_TMDS_2/i_ODDRE_N_D_UNCONNECTED\(7 downto 5), - D(4) => \i_ODDRE_N_i_2__2_n_0\, - D(3 downto 1) => \NLW_TMDS_2/i_ODDRE_N_D_UNCONNECTED\(3 downto 1), - D(0) => \i_ODDRE_N_i_1__1_n_0\, - OQ => HDMI_D2_N, - RST => \TMDS_3/Reset\, - T => '0', - T_OUT => \NLW_TMDS_2/i_ODDRE_N_T_OUT_UNCONNECTED\ - ); -\TMDS_2/i_ODDRE_P\: unisim.vcomponents.OSERDESE3 - generic map( - DATA_WIDTH => 8, - INIT => '0', - IS_CLK_INVERTED => '0', - ODDR_MODE => "TRUE", - OSERDES_D_BYPASS => "FALSE", - OSERDES_T_BYPASS => "TRUE", - SIM_DEVICE => "ULTRASCALE_PLUS", - SIM_VERSION => 2.000000 - ) - port map ( - CLK => pxClkX5, - CLKDIV => \NLW_TMDS_2/i_ODDRE_P_CLKDIV_UNCONNECTED\, - D(7 downto 5) => \NLW_TMDS_2/i_ODDRE_P_D_UNCONNECTED\(7 downto 5), - D(4) => \TMDS_2/D2\, - D(3 downto 1) => \NLW_TMDS_2/i_ODDRE_P_D_UNCONNECTED\(3 downto 1), - D(0) => \TMDS_2/D1\, - OQ => HDMI_D2_P, - RST => \TMDS_3/Reset\, - T => '0', - T_OUT => \NLW_TMDS_2/i_ODDRE_P_T_OUT_UNCONNECTED\ - ); -\TMDS_3/i_GBox/cntMod5_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClkX5, - CE => '1', - D => \cntMod5[0]_i_1__2_n_0\, - Q => \TMDS_3/i_GBox/cntMod5_reg_n_0_\(0), - R => \cntMod5[2]_i_1__2_n_0\ - ); -\TMDS_3/i_GBox/cntMod5_reg[1]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClkX5, - CE => '1', - D => \cntMod5[1]_i_1__2_n_0\, - Q => \TMDS_3/i_GBox/cntMod5_reg_n_0_\(1), - R => \cntMod5[2]_i_1__2_n_0\ - ); -\TMDS_3/i_GBox/cntMod5_reg[2]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClkX5, - CE => '1', - D => \cntMod5[2]_i_2__2_n_0\, - Q => \TMDS_3/i_GBox/cntMod5_reg_n_0_\(2), - R => \cntMod5[2]_i_1__2_n_0\ - ); -\TMDS_3/i_GBox/sReg_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClkX5, - CE => '1', - D => \sReg[0]_i_1__2_n_0\, - Q => \TMDS_3/D1\, - R => \TMDS_3/Reset\ - ); -\TMDS_3/i_GBox/sReg_reg[1]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClkX5, - CE => '1', - D => \sReg[1]_i_1__2_n_0\, - Q => \TMDS_3/D2\, - R => \TMDS_3/Reset\ - ); -\TMDS_3/i_GBox/sReg_reg[3]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => pxClkX5, - CE => '1', - D => \sReg[3]_i_1__2_n_0\, - Q => \TMDS_3/i_GBox/sReg_reg_n_0_\(3), - R => \TMDS_3/Reset\ - ); -\TMDS_3/i_ODDRE_N\: unisim.vcomponents.OSERDESE3 - generic map( - DATA_WIDTH => 8, - INIT => '0', - IS_CLK_INVERTED => '0', - ODDR_MODE => "TRUE", - OSERDES_D_BYPASS => "FALSE", - OSERDES_T_BYPASS => "TRUE", - SIM_DEVICE => "ULTRASCALE_PLUS", - SIM_VERSION => 2.000000 - ) - port map ( - CLK => pxClkX5, - CLKDIV => \NLW_TMDS_3/i_ODDRE_N_CLKDIV_UNCONNECTED\, - D(7 downto 5) => \NLW_TMDS_3/i_ODDRE_N_D_UNCONNECTED\(7 downto 5), - D(4) => i_ODDRE_N_i_2_n_0, - D(3 downto 1) => \NLW_TMDS_3/i_ODDRE_N_D_UNCONNECTED\(3 downto 1), - D(0) => \i_ODDRE_N_i_1__2_n_0\, - OQ => HDMI_CK_N, - RST => \TMDS_3/Reset\, - T => '0', - T_OUT => \NLW_TMDS_3/i_ODDRE_N_T_OUT_UNCONNECTED\ - ); -\TMDS_3/i_ODDRE_P\: unisim.vcomponents.OSERDESE3 - generic map( - DATA_WIDTH => 8, - INIT => '0', - IS_CLK_INVERTED => '0', - ODDR_MODE => "TRUE", - OSERDES_D_BYPASS => "FALSE", - OSERDES_T_BYPASS => "TRUE", - SIM_DEVICE => "ULTRASCALE_PLUS", - SIM_VERSION => 2.000000 - ) - port map ( - CLK => pxClkX5, - CLKDIV => \NLW_TMDS_3/i_ODDRE_P_CLKDIV_UNCONNECTED\, - D(7 downto 5) => \NLW_TMDS_3/i_ODDRE_P_D_UNCONNECTED\(7 downto 5), - D(4) => \TMDS_3/D2\, - D(3 downto 1) => \NLW_TMDS_3/i_ODDRE_P_D_UNCONNECTED\(3 downto 1), - D(0) => \TMDS_3/D1\, - OQ => HDMI_CK_P, - RST => \TMDS_3/Reset\, - T => '0', - T_OUT => \NLW_TMDS_3/i_ODDRE_P_T_OUT_UNCONNECTED\ - ); -\cntMod5[0]_i_1\: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => \TMDS_0/i_GBox/cntMod5_reg_n_0_\(0), - O => plusOp(0) - ); -\cntMod5[0]_i_1__0\: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => \TMDS_1/i_GBox/cntMod5_reg_n_0_\(0), - O => \cntMod5[0]_i_1__0_n_0\ - ); -\cntMod5[0]_i_1__1\: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => \TMDS_2/i_GBox/cntMod5_reg_n_0_\(0), - O => \cntMod5[0]_i_1__1_n_0\ - ); -\cntMod5[0]_i_1__2\: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => \TMDS_3/i_GBox/cntMod5_reg_n_0_\(0), - O => \cntMod5[0]_i_1__2_n_0\ - ); -\cntMod5[1]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => \TMDS_0/i_GBox/cntMod5_reg_n_0_\(0), - I1 => \TMDS_0/i_GBox/cntMod5_reg_n_0_\(1), - O => plusOp(1) - ); -\cntMod5[1]_i_1__0\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => \TMDS_1/i_GBox/cntMod5_reg_n_0_\(0), - I1 => \TMDS_1/i_GBox/cntMod5_reg_n_0_\(1), - O => \cntMod5[1]_i_1__0_n_0\ - ); -\cntMod5[1]_i_1__1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => \TMDS_2/i_GBox/cntMod5_reg_n_0_\(0), - I1 => \TMDS_2/i_GBox/cntMod5_reg_n_0_\(1), - O => \cntMod5[1]_i_1__1_n_0\ - ); -\cntMod5[1]_i_1__2\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => \TMDS_3/i_GBox/cntMod5_reg_n_0_\(0), - I1 => \TMDS_3/i_GBox/cntMod5_reg_n_0_\(1), - O => \cntMod5[1]_i_1__2_n_0\ - ); -\cntMod5[2]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"04FF" - ) - port map ( - I0 => \TMDS_0/i_GBox/cntMod5_reg_n_0_\(1), - I1 => \TMDS_0/i_GBox/cntMod5_reg_n_0_\(2), - I2 => \TMDS_0/i_GBox/cntMod5_reg_n_0_\(0), - I3 => ResetN, - O => \cntMod5[2]_i_1_n_0\ - ); -\cntMod5[2]_i_1__0\: unisim.vcomponents.LUT4 - generic map( - INIT => X"04FF" - ) - port map ( - I0 => \TMDS_1/i_GBox/cntMod5_reg_n_0_\(1), - I1 => \TMDS_1/i_GBox/cntMod5_reg_n_0_\(2), - I2 => \TMDS_1/i_GBox/cntMod5_reg_n_0_\(0), - I3 => ResetN, - O => \cntMod5[2]_i_1__0_n_0\ - ); -\cntMod5[2]_i_1__1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"04FF" - ) - port map ( - I0 => \TMDS_2/i_GBox/cntMod5_reg_n_0_\(1), - I1 => \TMDS_2/i_GBox/cntMod5_reg_n_0_\(2), - I2 => \TMDS_2/i_GBox/cntMod5_reg_n_0_\(0), - I3 => ResetN, - O => \cntMod5[2]_i_1__1_n_0\ - ); -\cntMod5[2]_i_1__2\: unisim.vcomponents.LUT4 - generic map( - INIT => X"04FF" - ) - port map ( - I0 => \TMDS_3/i_GBox/cntMod5_reg_n_0_\(1), - I1 => \TMDS_3/i_GBox/cntMod5_reg_n_0_\(2), - I2 => \TMDS_3/i_GBox/cntMod5_reg_n_0_\(0), - I3 => ResetN, - O => \cntMod5[2]_i_1__2_n_0\ - ); -\cntMod5[2]_i_2\: unisim.vcomponents.LUT3 - generic map( - INIT => X"6A" - ) - port map ( - I0 => \TMDS_0/i_GBox/cntMod5_reg_n_0_\(2), - I1 => \TMDS_0/i_GBox/cntMod5_reg_n_0_\(1), - I2 => \TMDS_0/i_GBox/cntMod5_reg_n_0_\(0), - O => plusOp(2) - ); -\cntMod5[2]_i_2__0\: unisim.vcomponents.LUT3 - generic map( - INIT => X"6A" - ) - port map ( - I0 => \TMDS_1/i_GBox/cntMod5_reg_n_0_\(2), - I1 => \TMDS_1/i_GBox/cntMod5_reg_n_0_\(1), - I2 => \TMDS_1/i_GBox/cntMod5_reg_n_0_\(0), - O => \cntMod5[2]_i_2__0_n_0\ - ); -\cntMod5[2]_i_2__1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"6A" - ) - port map ( - I0 => \TMDS_2/i_GBox/cntMod5_reg_n_0_\(2), - I1 => \TMDS_2/i_GBox/cntMod5_reg_n_0_\(1), - I2 => \TMDS_2/i_GBox/cntMod5_reg_n_0_\(0), - O => \cntMod5[2]_i_2__1_n_0\ - ); -\cntMod5[2]_i_2__2\: unisim.vcomponents.LUT3 - generic map( - INIT => X"6A" - ) - port map ( - I0 => \TMDS_3/i_GBox/cntMod5_reg_n_0_\(2), - I1 => \TMDS_3/i_GBox/cntMod5_reg_n_0_\(1), - I2 => \TMDS_3/i_GBox/cntMod5_reg_n_0_\(0), - O => \cntMod5[2]_i_2__2_n_0\ - ); -g0_b0: unisim.vcomponents.LUT5 - generic map( - INIT => X"96696996" - ) - port map ( - I0 => \TMDS_0/i_Enc/qD_reg_n_0_\(0), - I1 => \TMDS_0/i_Enc/p_0_in\, - I2 => \TMDS_0/i_Enc/p_2_in\, - I3 => \TMDS_0/i_Enc/p_4_in\, - I4 => \TMDS_0/i_Enc/p_6_in\, - O => g0_b0_n_0 - ); -\g0_b0__0\: unisim.vcomponents.LUT5 - generic map( - INIT => X"96696996" - ) - port map ( - I0 => \TMDS_1/i_Enc/qD_reg_n_0_\(0), - I1 => \TMDS_1/i_Enc/p_0_in\, - I2 => \TMDS_1/i_Enc/p_2_in\, - I3 => \TMDS_1/i_Enc/p_4_in\, - I4 => \TMDS_1/i_Enc/p_6_in\, - O => \g0_b0__0_n_0\ - ); -\g0_b0__1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"96696996" - ) - port map ( - I0 => \TMDS_2/i_Enc/qD_reg_n_0_\(0), - I1 => \TMDS_2/i_Enc/p_0_in\, - I2 => \TMDS_2/i_Enc/p_2_in\, - I3 => \TMDS_2/i_Enc/p_4_in\, - I4 => \TMDS_2/i_Enc/p_6_in\, - O => \g0_b0__1_n_0\ - ); -\g0_b0__2\: unisim.vcomponents.LUT3 - generic map( - INIT => X"96" - ) - port map ( - I0 => \TMDS_0/i_Enc/p_4_in\, - I1 => \TMDS_0/i_Enc/p_0_in\, - I2 => \g0_b2_i_2__0_n_0\, - O => \g0_b0__2_n_0\ - ); -\g0_b0__3\: unisim.vcomponents.LUT3 - generic map( - INIT => X"96" - ) - port map ( - I0 => \TMDS_1/i_Enc/p_4_in\, - I1 => \TMDS_1/i_Enc/p_0_in\, - I2 => \g0_b2_i_2__1_n_0\, - O => \g0_b0__3_n_0\ - ); -\g0_b0__4\: unisim.vcomponents.LUT3 - generic map( - INIT => X"96" - ) - port map ( - I0 => \TMDS_2/i_Enc/p_0_in\, - I1 => \TMDS_2/i_Enc/p_4_in\, - I2 => \TMDS_2/i_Enc/p_9_in\, - O => \g0_b0__4_n_0\ - ); -g0_b1: unisim.vcomponents.LUT5 - generic map( - INIT => X"177E7EE8" - ) - port map ( - I0 => \TMDS_0/i_Enc/qD_reg_n_0_\(0), - I1 => \TMDS_0/i_Enc/p_0_in\, - I2 => \TMDS_0/i_Enc/p_2_in\, - I3 => \TMDS_0/i_Enc/p_4_in\, - I4 => \TMDS_0/i_Enc/p_6_in\, - O => g0_b1_n_0 - ); -\g0_b1__0\: unisim.vcomponents.LUT5 - generic map( - INIT => X"177E7EE8" - ) - port map ( - I0 => \TMDS_1/i_Enc/qD_reg_n_0_\(0), - I1 => \TMDS_1/i_Enc/p_0_in\, - I2 => \TMDS_1/i_Enc/p_2_in\, - I3 => \TMDS_1/i_Enc/p_4_in\, - I4 => \TMDS_1/i_Enc/p_6_in\, - O => \g0_b1__0_n_0\ - ); -\g0_b1__1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"177E7EE8" - ) - port map ( - I0 => \TMDS_2/i_Enc/qD_reg_n_0_\(0), - I1 => \TMDS_2/i_Enc/p_0_in\, - I2 => \TMDS_2/i_Enc/p_2_in\, - I3 => \TMDS_2/i_Enc/p_4_in\, - I4 => \TMDS_2/i_Enc/p_6_in\, - O => \g0_b1__1_n_0\ - ); -\g0_b1__2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"B7E21DB7EDB847ED" - ) - port map ( - I0 => \TMDS_0/i_Enc/p_4_in\, - I1 => \TMDS_0/i_Enc/qD_reg_n_0_\(0), - I2 => \TMDS_0/i_Enc/p_0_in\, - I3 => \TMDS_0/i_Enc/p_2_in\, - I4 => g0_b2_i_1_n_0, - I5 => \g0_b2_i_2__0_n_0\, - O => \g0_b1__2_n_0\ - ); -\g0_b1__3\: unisim.vcomponents.LUT6 - generic map( - INIT => X"1DB7B7E247EDEDB8" - ) - port map ( - I0 => \TMDS_1/i_Enc/p_4_in\, - I1 => \TMDS_1/i_Enc/qD_reg_n_0_\(0), - I2 => \TMDS_1/i_Enc/p_0_in\, - I3 => \TMDS_1/i_Enc/p_2_in\, - I4 => \g0_b2_i_1__0_n_0\, - I5 => \g0_b2_i_2__1_n_0\, - O => \g0_b1__3_n_0\ - ); -\g0_b1__4\: unisim.vcomponents.LUT6 - generic map( - INIT => X"653FCF6A56F3FCA6" - ) - port map ( - I0 => \TMDS_2/i_Enc/p_2_in\, - I1 => \TMDS_2/i_Enc/p_0_in\, - I2 => \TMDS_2/i_Enc/qD_reg_n_0_\(0), - I3 => \TMDS_2/i_Enc/p_4_in\, - I4 => \g0_b2_i_1__1_n_0\, - I5 => \TMDS_2/i_Enc/p_9_in\, - O => \g0_b1__4_n_0\ - ); -g0_b2: unisim.vcomponents.LUT5 - generic map( - INIT => X"E8808000" - ) - port map ( - I0 => \TMDS_0/i_Enc/qD_reg_n_0_\(0), - I1 => \TMDS_0/i_Enc/p_0_in\, - I2 => \TMDS_0/i_Enc/p_2_in\, - I3 => \TMDS_0/i_Enc/p_4_in\, - I4 => \TMDS_0/i_Enc/p_6_in\, - O => g0_b2_n_0 - ); -\g0_b2__0\: unisim.vcomponents.LUT5 - generic map( - INIT => X"E8808000" - ) - port map ( - I0 => \TMDS_1/i_Enc/qD_reg_n_0_\(0), - I1 => \TMDS_1/i_Enc/p_0_in\, - I2 => \TMDS_1/i_Enc/p_2_in\, - I3 => \TMDS_1/i_Enc/p_4_in\, - I4 => \TMDS_1/i_Enc/p_6_in\, - O => \g0_b2__0_n_0\ - ); -\g0_b2__1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"E8808000" - ) - port map ( - I0 => \TMDS_2/i_Enc/qD_reg_n_0_\(0), - I1 => \TMDS_2/i_Enc/p_0_in\, - I2 => \TMDS_2/i_Enc/p_2_in\, - I3 => \TMDS_2/i_Enc/p_4_in\, - I4 => \TMDS_2/i_Enc/p_6_in\, - O => \g0_b2__1_n_0\ - ); -\g0_b2__2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"481CC24800048000" - ) - port map ( - I0 => \TMDS_0/i_Enc/p_4_in\, - I1 => \TMDS_0/i_Enc/qD_reg_n_0_\(0), - I2 => \TMDS_0/i_Enc/p_0_in\, - I3 => \TMDS_0/i_Enc/p_2_in\, - I4 => g0_b2_i_1_n_0, - I5 => \g0_b2_i_2__0_n_0\, - O => \g0_b2__2_n_0\ - ); -\g0_b2__3\: unisim.vcomponents.LUT6 - generic map( - INIT => X"C248481C80000004" - ) - port map ( - I0 => \TMDS_1/i_Enc/p_4_in\, - I1 => \TMDS_1/i_Enc/qD_reg_n_0_\(0), - I2 => \TMDS_1/i_Enc/p_0_in\, - I3 => \TMDS_1/i_Enc/p_2_in\, - I4 => \g0_b2_i_1__0_n_0\, - I5 => \g0_b2_i_2__1_n_0\, - O => \g0_b2__3_n_0\ - ); -\g0_b2__4\: unisim.vcomponents.LUT6 - generic map( - INIT => X"92C0309480000010" - ) - port map ( - I0 => \TMDS_2/i_Enc/p_2_in\, - I1 => \TMDS_2/i_Enc/p_0_in\, - I2 => \TMDS_2/i_Enc/qD_reg_n_0_\(0), - I3 => \TMDS_2/i_Enc/p_4_in\, - I4 => \g0_b2_i_1__1_n_0\, - I5 => \TMDS_2/i_Enc/p_9_in\, - O => \g0_b2__4_n_0\ - ); -g0_b2_i_1: unisim.vcomponents.LUT6 - generic map( - INIT => X"00007177001077F7" - ) - port map ( - I0 => g0_b1_n_0, - I1 => g0_b2_i_3_n_0, - I2 => \TMDS_0/i_Enc/qD_reg_n_0_\(0), - I3 => g0_b0_n_0, - I4 => g0_b2_n_0, - I5 => g0_b2_i_4_n_0, - O => g0_b2_i_1_n_0 - ); -\g0_b2_i_1__0\: unisim.vcomponents.LUT6 - generic map( - INIT => X"EEEEEEEEEEEEEEE0" - ) - port map ( - I0 => \g0_b2_i_3__0_n_0\, - I1 => \g0_b2__0_n_0\, - I2 => \g0_b2_i_4__0_n_0\, - I3 => \TMDS_1/i_Enc/p_12_in\, - I4 => \TMDS_1/i_Enc/p_10_in\, - I5 => \g0_b1__0_n_0\, - O => \g0_b2_i_1__0_n_0\ - ); -\g0_b2_i_1__1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"BABABAFBA2BABABA" - ) - port map ( - I0 => \g0_b2__1_n_0\, - I1 => \g0_b2_i_3__1_n_0\, - I2 => \g0_b1__1_n_0\, - I3 => \g0_b2_i_4__1_n_0\, - I4 => \TMDS_2/i_Enc/qD_reg_n_0_\(0), - I5 => \g0_b0__1_n_0\, - O => \g0_b2_i_1__1_n_0\ - ); -g0_b2_i_2: unisim.vcomponents.LUT5 - generic map( - INIT => X"96696996" - ) - port map ( - I0 => \TMDS_2/i_Enc/p_6_in\, - I1 => \TMDS_2/i_Enc/p_2_in\, - I2 => \TMDS_2/i_Enc/p_0_in\, - I3 => \TMDS_2/i_Enc/qD_reg_n_0_\(0), - I4 => \TMDS_2/i_Enc/p_4_in\, - O => \TMDS_2/i_Enc/p_9_in\ - ); -\g0_b2_i_2__0\: unisim.vcomponents.LUT5 - generic map( - INIT => X"96696996" - ) - port map ( - I0 => \TMDS_0/i_Enc/p_6_in\, - I1 => \TMDS_0/i_Enc/p_2_in\, - I2 => \TMDS_0/i_Enc/p_0_in\, - I3 => \TMDS_0/i_Enc/qD_reg_n_0_\(0), - I4 => \TMDS_0/i_Enc/p_4_in\, - O => \g0_b2_i_2__0_n_0\ - ); -\g0_b2_i_2__1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"96696996" - ) - port map ( - I0 => \TMDS_1/i_Enc/p_6_in\, - I1 => \TMDS_1/i_Enc/p_2_in\, - I2 => \TMDS_1/i_Enc/p_0_in\, - I3 => \TMDS_1/i_Enc/qD_reg_n_0_\(0), - I4 => \TMDS_1/i_Enc/p_4_in\, - O => \g0_b2_i_2__1_n_0\ - ); -g0_b2_i_3: unisim.vcomponents.LUT3 - generic map( - INIT => X"E8" - ) - port map ( - I0 => \TMDS_0/i_Enc/p_8_in\, - I1 => \TMDS_0/i_Enc/p_12_in\, - I2 => \TMDS_0/i_Enc/p_10_in\, - O => g0_b2_i_3_n_0 - ); -\g0_b2_i_3__0\: unisim.vcomponents.LUT6 - generic map( - INIT => X"E8FE80E800800000" - ) - port map ( - I0 => \TMDS_1/i_Enc/p_10_in\, - I1 => \TMDS_1/i_Enc/p_12_in\, - I2 => \TMDS_1/i_Enc/p_8_in\, - I3 => \TMDS_1/i_Enc/qD_reg_n_0_\(0), - I4 => \g0_b0__0_n_0\, - I5 => \g0_b1__0_n_0\, - O => \g0_b2_i_3__0_n_0\ - ); -\g0_b2_i_3__1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"17" - ) - port map ( - I0 => \TMDS_2/i_Enc/p_10_in\, - I1 => \TMDS_2/i_Enc/p_12_in\, - I2 => \TMDS_2/i_Enc/p_8_in\, - O => \g0_b2_i_3__1_n_0\ - ); -g0_b2_i_4: unisim.vcomponents.LUT3 - generic map( - INIT => X"96" - ) - port map ( - I0 => \TMDS_0/i_Enc/p_8_in\, - I1 => \TMDS_0/i_Enc/p_12_in\, - I2 => \TMDS_0/i_Enc/p_10_in\, - O => g0_b2_i_4_n_0 - ); -\g0_b2_i_4__0\: unisim.vcomponents.LUT5 - generic map( - INIT => X"FFFF90FF" - ) - port map ( - I0 => \TMDS_1/i_Enc/p_10_in\, - I1 => \TMDS_1/i_Enc/p_12_in\, - I2 => \TMDS_1/i_Enc/p_8_in\, - I3 => \TMDS_1/i_Enc/qD_reg_n_0_\(0), - I4 => \g0_b0__0_n_0\, - O => \g0_b2_i_4__0_n_0\ - ); -\g0_b2_i_4__1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"69" - ) - port map ( - I0 => \TMDS_2/i_Enc/p_8_in\, - I1 => \TMDS_2/i_Enc/p_12_in\, - I2 => \TMDS_2/i_Enc/p_10_in\, - O => \g0_b2_i_4__1_n_0\ - ); -i_ODDRE_N_i_1: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => \TMDS_0/D1\, - O => i_ODDRE_N_i_1_n_0 - ); -\i_ODDRE_N_i_1__0\: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => \TMDS_1/D1\, - O => \i_ODDRE_N_i_1__0_n_0\ - ); -\i_ODDRE_N_i_1__1\: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => \TMDS_2/D1\, - O => \i_ODDRE_N_i_1__1_n_0\ - ); -\i_ODDRE_N_i_1__2\: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => \TMDS_3/D1\, - O => \i_ODDRE_N_i_1__2_n_0\ - ); -i_ODDRE_N_i_2: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => \TMDS_3/D2\, - O => i_ODDRE_N_i_2_n_0 - ); -\i_ODDRE_N_i_2__0\: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => \TMDS_0/D2\, - O => \i_ODDRE_N_i_2__0_n_0\ - ); -\i_ODDRE_N_i_2__1\: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => \TMDS_1/D2\, - O => \i_ODDRE_N_i_2__1_n_0\ - ); -\i_ODDRE_N_i_2__2\: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => \TMDS_2/D2\, - O => \i_ODDRE_N_i_2__2_n_0\ - ); -i_ODDRE_P_i_1: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => ResetN, - O => \TMDS_3/Reset\ - ); -\sReg[0]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"9F90FFFF9F900000" - ) - port map ( - I0 => \TMDS_0/i_Enc/qD_reg_n_0_\(0), - I1 => \sReg[9]_i_2_n_0\, - I2 => qDE, - I3 => qC1C0(0), - I4 => \sReg[9]_i_3_n_0\, - I5 => \TMDS_0/i_GBox/sReg_reg_n_0_\(2), - O => \sReg[0]_i_1_n_0\ - ); -\sReg[0]_i_1__0\: unisim.vcomponents.LUT5 - generic map( - INIT => X"C3AA00AA" - ) - port map ( - I0 => \TMDS_1/i_GBox/sReg_reg_n_0_\(2), - I1 => \TMDS_1/i_Enc/qD_reg_n_0_\(0), - I2 => \sReg[9]_i_2__0_n_0\, - I3 => \sReg[7]_i_4_n_0\, - I4 => qDE, - O => \sReg[0]_i_1__0_n_0\ - ); -\sReg[0]_i_1__1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"C3AA00AA" - ) - port map ( - I0 => \TMDS_2/i_GBox/sReg_reg_n_0_\(2), - I1 => \TMDS_2/i_Enc/qD_reg_n_0_\(0), - I2 => \sReg[9]_i_2__1_n_0\, - I3 => \sReg[7]_i_3_n_0\, - I4 => qDE, - O => \sReg[0]_i_1__1_n_0\ - ); -\sReg[0]_i_1__2\: unisim.vcomponents.LUT4 - generic map( - INIT => X"AABA" - ) - port map ( - I0 => \TMDS_3/D2\, - I1 => \TMDS_3/i_GBox/cntMod5_reg_n_0_\(2), - I2 => \TMDS_3/i_GBox/cntMod5_reg_n_0_\(1), - I3 => \TMDS_3/i_GBox/cntMod5_reg_n_0_\(0), - O => \sReg[0]_i_1__2_n_0\ - ); -\sReg[1]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"00808880AAAAAAAA" - ) - port map ( - I0 => \sReg[1]_i_2__0_n_0\, - I1 => qDE, - I2 => \sReg[1]_i_3_n_0\, - I3 => \Cnt[4]_i_6_n_0\, - I4 => \sReg[1]_i_4_n_0\, - I5 => \sReg[1]_i_5_n_0\, - O => \sReg[1]_i_1_n_0\ - ); -\sReg[1]_i_1__0\: unisim.vcomponents.LUT5 - generic map( - INIT => X"FFFB0008" - ) - port map ( - I0 => \sReg[1]_i_2__1_n_0\, - I1 => \TMDS_1/i_GBox/cntMod5_reg_n_0_\(1), - I2 => \TMDS_1/i_GBox/cntMod5_reg_n_0_\(2), - I3 => \TMDS_1/i_GBox/cntMod5_reg_n_0_\(0), - I4 => \TMDS_1/i_GBox/sReg_reg_n_0_\(3), - O => \sReg[1]_i_1__0_n_0\ - ); -\sReg[1]_i_1__1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"ABAAA8AAA8AAA8AA" - ) - port map ( - I0 => \TMDS_2/i_GBox/sReg_reg_n_0_\(3), - I1 => \TMDS_2/i_GBox/cntMod5_reg_n_0_\(0), - I2 => \TMDS_2/i_GBox/cntMod5_reg_n_0_\(2), - I3 => \TMDS_2/i_GBox/cntMod5_reg_n_0_\(1), - I4 => qDE, - I5 => \sReg[1]_i_2_n_0\, - O => \sReg[1]_i_1__1_n_0\ - ); -\sReg[1]_i_1__2\: unisim.vcomponents.LUT4 - generic map( - INIT => X"AABA" - ) - port map ( - I0 => \TMDS_3/i_GBox/sReg_reg_n_0_\(3), - I1 => \TMDS_3/i_GBox/cntMod5_reg_n_0_\(2), - I2 => \TMDS_3/i_GBox/cntMod5_reg_n_0_\(1), - I3 => \TMDS_3/i_GBox/cntMod5_reg_n_0_\(0), - O => \sReg[1]_i_1__2_n_0\ - ); -\sReg[1]_i_2\: unisim.vcomponents.LUT5 - generic map( - INIT => X"609F9F60" - ) - port map ( - I0 => \g0_b2_i_1__1_n_0\, - I1 => \Cnt[4]_i_4__1_n_0\, - I2 => \Cnt[4]_i_6__0_n_0\, - I3 => \TMDS_2/i_Enc/qD_reg_n_0_\(0), - I4 => \TMDS_2/i_Enc/p_0_in\, - O => \sReg[1]_i_2_n_0\ - ); -\sReg[1]_i_2__0\: unisim.vcomponents.LUT4 - generic map( - INIT => X"ABAA" - ) - port map ( - I0 => \TMDS_0/i_GBox/sReg_reg_n_0_\(3), - I1 => \TMDS_0/i_GBox/cntMod5_reg_n_0_\(0), - I2 => \TMDS_0/i_GBox/cntMod5_reg_n_0_\(2), - I3 => \TMDS_0/i_GBox/cntMod5_reg_n_0_\(1), - O => \sReg[1]_i_2__0_n_0\ - ); -\sReg[1]_i_2__1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"6696966600000000" - ) - port map ( - I0 => \TMDS_1/i_Enc/p_0_in\, - I1 => \TMDS_1/i_Enc/qD_reg_n_0_\(0), - I2 => \Cnt[4]_i_5__0_n_0\, - I3 => \Cnt[4]_i_3__0_n_0\, - I4 => \g0_b2_i_1__0_n_0\, - I5 => qDE, - O => \sReg[1]_i_2__1_n_0\ - ); -\sReg[1]_i_3\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => \TMDS_0/i_Enc/qD_reg_n_0_\(0), - I1 => \TMDS_0/i_Enc/p_0_in\, - O => \sReg[1]_i_3_n_0\ - ); -\sReg[1]_i_4\: unisim.vcomponents.LUT4 - generic map( - INIT => X"6996" - ) - port map ( - I0 => \TMDS_0/i_Enc/qD_reg_n_0_\(0), - I1 => \TMDS_0/i_Enc/p_0_in\, - I2 => g0_b2_i_1_n_0, - I3 => \Cnt[4]_i_4_n_0\, - O => \sReg[1]_i_4_n_0\ - ); -\sReg[1]_i_5\: unisim.vcomponents.LUT5 - generic map( - INIT => X"10001010" - ) - port map ( - I0 => \TMDS_0/i_GBox/cntMod5_reg_n_0_\(0), - I1 => \TMDS_0/i_GBox/cntMod5_reg_n_0_\(2), - I2 => \TMDS_0/i_GBox/cntMod5_reg_n_0_\(1), - I3 => qDE, - I4 => qC1C0(0), - O => \sReg[1]_i_5_n_0\ - ); -\sReg[2]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"606FFFFF606F0000" - ) - port map ( - I0 => \sReg[2]_i_2_n_0\, - I1 => \sReg[9]_i_2_n_0\, - I2 => qDE, - I3 => qC1C0(0), - I4 => \sReg[9]_i_3_n_0\, - I5 => \TMDS_0/i_GBox/sReg_reg_n_0_\(4), - O => \sReg[2]_i_1_n_0\ - ); -\sReg[2]_i_1__0\: unisim.vcomponents.LUT5 - generic map( - INIT => X"3AFAFA3A" - ) - port map ( - I0 => \TMDS_1/i_GBox/sReg_reg_n_0_\(4), - I1 => qDE, - I2 => \sReg[7]_i_4_n_0\, - I3 => \sReg[2]_i_2__0_n_0\, - I4 => \sReg[9]_i_2__0_n_0\, - O => \sReg[2]_i_1__0_n_0\ - ); -\sReg[2]_i_1__1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"3CFFAAAA" - ) - port map ( - I0 => \TMDS_2/i_GBox/sReg_reg_n_0_\(4), - I1 => \sReg[9]_i_2__1_n_0\, - I2 => \sReg[2]_i_2__1_n_0\, - I3 => qDE, - I4 => \sReg[7]_i_3_n_0\, - O => \sReg[2]_i_1__1_n_0\ - ); -\sReg[2]_i_2\: unisim.vcomponents.LUT3 - generic map( - INIT => X"69" - ) - port map ( - I0 => \TMDS_0/i_Enc/p_2_in\, - I1 => \TMDS_0/i_Enc/p_0_in\, - I2 => \TMDS_0/i_Enc/qD_reg_n_0_\(0), - O => \sReg[2]_i_2_n_0\ - ); -\sReg[2]_i_2__0\: unisim.vcomponents.LUT3 - generic map( - INIT => X"69" - ) - port map ( - I0 => \TMDS_1/i_Enc/p_2_in\, - I1 => \TMDS_1/i_Enc/p_0_in\, - I2 => \TMDS_1/i_Enc/qD_reg_n_0_\(0), - O => \sReg[2]_i_2__0_n_0\ - ); -\sReg[2]_i_2__1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"69" - ) - port map ( - I0 => \TMDS_2/i_Enc/p_2_in\, - I1 => \TMDS_2/i_Enc/p_0_in\, - I2 => \TMDS_2/i_Enc/qD_reg_n_0_\(0), - O => \sReg[2]_i_2__1_n_0\ - ); -\sReg[3]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"BFBFAFFFAAAAAAAA" - ) - port map ( - I0 => \sReg[3]_i_2__1_n_0\, - I1 => \sReg[3]_i_3_n_0\, - I2 => qDE, - I3 => \sReg[3]_i_4_n_0\, - I4 => \Cnt[4]_i_6_n_0\, - I5 => \sReg[5]_i_5_n_0\, - O => \sReg[3]_i_1_n_0\ - ); -\sReg[3]_i_1__0\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AAA3AAAAAAA0AAAA" - ) - port map ( - I0 => \TMDS_1/i_GBox/sReg_reg_n_0_\(5), - I1 => \sReg[3]_i_2_n_0\, - I2 => \TMDS_1/i_GBox/cntMod5_reg_n_0_\(0), - I3 => \TMDS_1/i_GBox/cntMod5_reg_n_0_\(2), - I4 => \TMDS_1/i_GBox/cntMod5_reg_n_0_\(1), - I5 => qDE, - O => \sReg[3]_i_1__0_n_0\ - ); -\sReg[3]_i_1__1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"FFFB0008" - ) - port map ( - I0 => \sReg[3]_i_2__0_n_0\, - I1 => \TMDS_2/i_GBox/cntMod5_reg_n_0_\(1), - I2 => \TMDS_2/i_GBox/cntMod5_reg_n_0_\(2), - I3 => \TMDS_2/i_GBox/cntMod5_reg_n_0_\(0), - I4 => \TMDS_2/i_GBox/sReg_reg_n_0_\(5), - O => \sReg[3]_i_1__1_n_0\ - ); -\sReg[3]_i_1__2\: unisim.vcomponents.LUT3 - generic map( - INIT => X"04" - ) - port map ( - I0 => \TMDS_3/i_GBox/cntMod5_reg_n_0_\(0), - I1 => \TMDS_3/i_GBox/cntMod5_reg_n_0_\(1), - I2 => \TMDS_3/i_GBox/cntMod5_reg_n_0_\(2), - O => \sReg[3]_i_1__2_n_0\ - ); -\sReg[3]_i_2\: unisim.vcomponents.LUT5 - generic map( - INIT => X"609F9F60" - ) - port map ( - I0 => \g0_b2_i_1__0_n_0\, - I1 => \Cnt[4]_i_3__0_n_0\, - I2 => \Cnt[4]_i_5__0_n_0\, - I3 => \TMDS_1/i_Enc/p_4_in\, - I4 => \sReg[2]_i_2__0_n_0\, - O => \sReg[3]_i_2_n_0\ - ); -\sReg[3]_i_2__0\: unisim.vcomponents.LUT6 - generic map( - INIT => X"8282288228828282" - ) - port map ( - I0 => qDE, - I1 => \TMDS_2/i_Enc/p_4_in\, - I2 => \sReg[2]_i_2__1_n_0\, - I3 => \Cnt[4]_i_6__0_n_0\, - I4 => \Cnt[4]_i_4__1_n_0\, - I5 => \g0_b2_i_1__1_n_0\, - O => \sReg[3]_i_2__0_n_0\ - ); -\sReg[3]_i_2__1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"A8AA" - ) - port map ( - I0 => \TMDS_0/i_GBox/sReg_reg_n_0_\(5), - I1 => \TMDS_0/i_GBox/cntMod5_reg_n_0_\(0), - I2 => \TMDS_0/i_GBox/cntMod5_reg_n_0_\(2), - I3 => \TMDS_0/i_GBox/cntMod5_reg_n_0_\(1), - O => \sReg[3]_i_2__1_n_0\ - ); -\sReg[3]_i_3\: unisim.vcomponents.LUT6 - generic map( - INIT => X"6996966996696996" - ) - port map ( - I0 => \TMDS_0/i_Enc/p_4_in\, - I1 => \TMDS_0/i_Enc/qD_reg_n_0_\(0), - I2 => \TMDS_0/i_Enc/p_0_in\, - I3 => \TMDS_0/i_Enc/p_2_in\, - I4 => g0_b2_i_1_n_0, - I5 => \Cnt[4]_i_4_n_0\, - O => \sReg[3]_i_3_n_0\ - ); -\sReg[3]_i_4\: unisim.vcomponents.LUT4 - generic map( - INIT => X"9669" - ) - port map ( - I0 => \TMDS_0/i_Enc/p_4_in\, - I1 => \TMDS_0/i_Enc/qD_reg_n_0_\(0), - I2 => \TMDS_0/i_Enc/p_0_in\, - I3 => \TMDS_0/i_Enc/p_2_in\, - O => \sReg[3]_i_4_n_0\ - ); -\sReg[4]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"909FFFFF909F0000" - ) - port map ( - I0 => \g0_b2_i_2__0_n_0\, - I1 => \sReg[9]_i_2_n_0\, - I2 => qDE, - I3 => qC1C0(0), - I4 => \sReg[9]_i_3_n_0\, - I5 => \TMDS_0/i_GBox/sReg_reg_n_0_\(6), - O => \sReg[4]_i_1_n_0\ - ); -\sReg[4]_i_1__0\: unisim.vcomponents.LUT5 - generic map( - INIT => X"C3AAFFAA" - ) - port map ( - I0 => \TMDS_1/i_GBox/sReg_reg_n_0_\(6), - I1 => \g0_b2_i_2__1_n_0\, - I2 => \sReg[9]_i_2__0_n_0\, - I3 => \sReg[7]_i_4_n_0\, - I4 => qDE, - O => \sReg[4]_i_1__0_n_0\ - ); -\sReg[4]_i_1__1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"C3FFAAAA" - ) - port map ( - I0 => \TMDS_2/i_GBox/sReg_reg_n_0_\(6), - I1 => \sReg[9]_i_2__1_n_0\, - I2 => \TMDS_2/i_Enc/p_9_in\, - I3 => qDE, - I4 => \sReg[7]_i_3_n_0\, - O => \sReg[4]_i_1__1_n_0\ - ); -\sReg[5]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"EFEFAFFFAAAAAAAA" - ) - port map ( - I0 => \sReg[5]_i_2__1_n_0\, - I1 => \sReg[5]_i_3_n_0\, - I2 => qDE, - I3 => \sReg[5]_i_4_n_0\, - I4 => \Cnt[4]_i_6_n_0\, - I5 => \sReg[5]_i_5_n_0\, - O => \sReg[5]_i_1_n_0\ - ); -\sReg[5]_i_1__0\: unisim.vcomponents.LUT5 - generic map( - INIT => X"FFFB0008" - ) - port map ( - I0 => \sReg[5]_i_2_n_0\, - I1 => \TMDS_1/i_GBox/cntMod5_reg_n_0_\(1), - I2 => \TMDS_1/i_GBox/cntMod5_reg_n_0_\(2), - I3 => \TMDS_1/i_GBox/cntMod5_reg_n_0_\(0), - I4 => \TMDS_1/i_GBox/sReg_reg_n_0_\(7), - O => \sReg[5]_i_1__0_n_0\ - ); -\sReg[5]_i_1__1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"FFFB0008" - ) - port map ( - I0 => \sReg[5]_i_2__0_n_0\, - I1 => \TMDS_2/i_GBox/cntMod5_reg_n_0_\(1), - I2 => \TMDS_2/i_GBox/cntMod5_reg_n_0_\(2), - I3 => \TMDS_2/i_GBox/cntMod5_reg_n_0_\(0), - I4 => \TMDS_2/i_GBox/sReg_reg_n_0_\(7), - O => \sReg[5]_i_1__1_n_0\ - ); -\sReg[5]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"2828822882282828" - ) - port map ( - I0 => qDE, - I1 => \TMDS_1/i_Enc/p_8_in\, - I2 => \g0_b2_i_2__1_n_0\, - I3 => \Cnt[4]_i_5__0_n_0\, - I4 => \Cnt[4]_i_3__0_n_0\, - I5 => \g0_b2_i_1__0_n_0\, - O => \sReg[5]_i_2_n_0\ - ); -\sReg[5]_i_2__0\: unisim.vcomponents.LUT6 - generic map( - INIT => X"2828822882282828" - ) - port map ( - I0 => qDE, - I1 => \TMDS_2/i_Enc/p_9_in\, - I2 => \TMDS_2/i_Enc/p_8_in\, - I3 => \Cnt[4]_i_6__0_n_0\, - I4 => \Cnt[4]_i_4__1_n_0\, - I5 => \g0_b2_i_1__1_n_0\, - O => \sReg[5]_i_2__0_n_0\ - ); -\sReg[5]_i_2__1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"A8AA" - ) - port map ( - I0 => \TMDS_0/i_GBox/sReg_reg_n_0_\(7), - I1 => \TMDS_0/i_GBox/cntMod5_reg_n_0_\(0), - I2 => \TMDS_0/i_GBox/cntMod5_reg_n_0_\(2), - I3 => \TMDS_0/i_GBox/cntMod5_reg_n_0_\(1), - O => \sReg[5]_i_2__1_n_0\ - ); -\sReg[5]_i_3\: unisim.vcomponents.LUT4 - generic map( - INIT => X"9669" - ) - port map ( - I0 => \TMDS_0/i_Enc/p_8_in\, - I1 => \g0_b2_i_2__0_n_0\, - I2 => g0_b2_i_1_n_0, - I3 => \Cnt[4]_i_4_n_0\, - O => \sReg[5]_i_3_n_0\ - ); -\sReg[5]_i_4\: unisim.vcomponents.LUT6 - generic map( - INIT => X"9669699669969669" - ) - port map ( - I0 => \TMDS_0/i_Enc/p_8_in\, - I1 => \TMDS_0/i_Enc/p_4_in\, - I2 => \TMDS_0/i_Enc/qD_reg_n_0_\(0), - I3 => \TMDS_0/i_Enc/p_0_in\, - I4 => \TMDS_0/i_Enc/p_2_in\, - I5 => \TMDS_0/i_Enc/p_6_in\, - O => \sReg[5]_i_4_n_0\ - ); -\sReg[5]_i_5\: unisim.vcomponents.LUT5 - generic map( - INIT => X"10101000" - ) - port map ( - I0 => \TMDS_0/i_GBox/cntMod5_reg_n_0_\(0), - I1 => \TMDS_0/i_GBox/cntMod5_reg_n_0_\(2), - I2 => \TMDS_0/i_GBox/cntMod5_reg_n_0_\(1), - I3 => qC1C0(0), - I4 => qDE, - O => \sReg[5]_i_5_n_0\ - ); -\sReg[6]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"909FFFFF909F0000" - ) - port map ( - I0 => \sReg[6]_i_2__0_n_0\, - I1 => \sReg[9]_i_2_n_0\, - I2 => qDE, - I3 => qC1C0(0), - I4 => \sReg[9]_i_3_n_0\, - I5 => \TMDS_0/i_GBox/sReg_reg_n_0_\(8), - O => \sReg[6]_i_1_n_0\ - ); -\sReg[6]_i_1__0\: unisim.vcomponents.LUT6 - generic map( - INIT => X"3CC3AAAAFFFFAAAA" - ) - port map ( - I0 => \TMDS_1/i_GBox/sReg_reg_n_0_\(8), - I1 => \sReg[6]_i_2_n_0\, - I2 => \TMDS_1/i_Enc/p_10_in\, - I3 => \sReg[9]_i_2__0_n_0\, - I4 => \sReg[7]_i_4_n_0\, - I5 => qDE, - O => \sReg[6]_i_1__0_n_0\ - ); -\sReg[6]_i_1__1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"96FFFFFF96FF0000" - ) - port map ( - I0 => \sReg[9]_i_2__1_n_0\, - I1 => \TMDS_2/i_Enc/p_10_in\, - I2 => \sReg[6]_i_2__1_n_0\, - I3 => qDE, - I4 => \sReg[7]_i_3_n_0\, - I5 => \TMDS_2/i_GBox/sReg_reg_n_0_\(8), - O => \sReg[6]_i_1__1_n_0\ - ); -\sReg[6]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"6996966996696996" - ) - port map ( - I0 => \TMDS_1/i_Enc/p_8_in\, - I1 => \TMDS_1/i_Enc/p_4_in\, - I2 => \TMDS_1/i_Enc/qD_reg_n_0_\(0), - I3 => \TMDS_1/i_Enc/p_0_in\, - I4 => \TMDS_1/i_Enc/p_2_in\, - I5 => \TMDS_1/i_Enc/p_6_in\, - O => \sReg[6]_i_2_n_0\ - ); -\sReg[6]_i_2__0\: unisim.vcomponents.LUT3 - generic map( - INIT => X"96" - ) - port map ( - I0 => \TMDS_0/i_Enc/p_10_in\, - I1 => \g0_b2_i_2__0_n_0\, - I2 => \TMDS_0/i_Enc/p_8_in\, - O => \sReg[6]_i_2__0_n_0\ - ); -\sReg[6]_i_2__1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"9669699669969669" - ) - port map ( - I0 => \TMDS_2/i_Enc/p_8_in\, - I1 => \TMDS_2/i_Enc/p_4_in\, - I2 => \TMDS_2/i_Enc/qD_reg_n_0_\(0), - I3 => \TMDS_2/i_Enc/p_0_in\, - I4 => \TMDS_2/i_Enc/p_2_in\, - I5 => \TMDS_2/i_Enc/p_6_in\, - O => \sReg[6]_i_2__1_n_0\ - ); -\sReg[7]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"3FF3AAAA0CC0AAAA" - ) - port map ( - I0 => \TMDS_0/i_GBox/sReg_reg_n_0_\(9), - I1 => qDE, - I2 => \sReg[7]_i_2__0_n_0\, - I3 => \sReg[9]_i_2_n_0\, - I4 => \sReg[9]_i_3_n_0\, - I5 => qC1C0(0), - O => \sReg[7]_i_1_n_0\ - ); -\sReg[7]_i_1__0\: unisim.vcomponents.LUT6 - generic map( - INIT => X"8228FFFF82280000" - ) - port map ( - I0 => qDE, - I1 => \sReg[9]_i_2__0_n_0\, - I2 => \sReg[7]_i_2_n_0\, - I3 => \sReg[7]_i_3__0_n_0\, - I4 => \sReg[7]_i_4_n_0\, - I5 => \TMDS_1/i_GBox/sReg_reg_n_0_\(9), - O => \sReg[7]_i_1__0_n_0\ - ); -\sReg[7]_i_1__1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"82FF8200" - ) - port map ( - I0 => qDE, - I1 => \sReg[9]_i_2__1_n_0\, - I2 => \sReg[7]_i_2__1_n_0\, - I3 => \sReg[7]_i_3_n_0\, - I4 => \TMDS_2/i_GBox/sReg_reg_n_0_\(9), - O => \sReg[7]_i_1__1_n_0\ - ); -\sReg[7]_i_2\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => \TMDS_1/i_Enc/p_10_in\, - I1 => \TMDS_1/i_Enc/p_12_in\, - O => \sReg[7]_i_2_n_0\ - ); -\sReg[7]_i_2__0\: unisim.vcomponents.LUT5 - generic map( - INIT => X"96696996" - ) - port map ( - I0 => \TMDS_0/i_Enc/p_12_in\, - I1 => \TMDS_0/i_Enc/p_10_in\, - I2 => \TMDS_0/i_Enc/p_8_in\, - I3 => \g0_b2_i_2__0_n_0\, - I4 => g0_b2_i_1_n_0, - O => \sReg[7]_i_2__0_n_0\ - ); -\sReg[7]_i_2__1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"96696996" - ) - port map ( - I0 => \TMDS_2/i_Enc/p_12_in\, - I1 => \TMDS_2/i_Enc/p_10_in\, - I2 => \TMDS_2/i_Enc/p_8_in\, - I3 => \TMDS_2/i_Enc/p_9_in\, - I4 => \g0_b2_i_1__1_n_0\, - O => \sReg[7]_i_2__1_n_0\ - ); -\sReg[7]_i_3\: unisim.vcomponents.LUT3 - generic map( - INIT => X"02" - ) - port map ( - I0 => \TMDS_2/i_GBox/cntMod5_reg_n_0_\(1), - I1 => \TMDS_2/i_GBox/cntMod5_reg_n_0_\(2), - I2 => \TMDS_2/i_GBox/cntMod5_reg_n_0_\(0), - O => \sReg[7]_i_3_n_0\ - ); -\sReg[7]_i_3__0\: unisim.vcomponents.LUT3 - generic map( - INIT => X"69" - ) - port map ( - I0 => \g0_b2_i_1__0_n_0\, - I1 => \g0_b2_i_2__1_n_0\, - I2 => \TMDS_1/i_Enc/p_8_in\, - O => \sReg[7]_i_3__0_n_0\ - ); -\sReg[7]_i_4\: unisim.vcomponents.LUT3 - generic map( - INIT => X"02" - ) - port map ( - I0 => \TMDS_1/i_GBox/cntMod5_reg_n_0_\(1), - I1 => \TMDS_1/i_GBox/cntMod5_reg_n_0_\(2), - I2 => \TMDS_1/i_GBox/cntMod5_reg_n_0_\(0), - O => \sReg[7]_i_4_n_0\ - ); -\sReg[8]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"000C000000040004" - ) - port map ( - I0 => qC1C0(0), - I1 => \TMDS_0/i_GBox/cntMod5_reg_n_0_\(1), - I2 => \TMDS_0/i_GBox/cntMod5_reg_n_0_\(2), - I3 => \TMDS_0/i_GBox/cntMod5_reg_n_0_\(0), - I4 => g0_b2_i_1_n_0, - I5 => qDE, - O => \sReg[8]_i_1_n_0\ - ); -\sReg[8]_i_1__0\: unisim.vcomponents.LUT5 - generic map( - INIT => X"00101010" - ) - port map ( - I0 => \TMDS_1/i_GBox/cntMod5_reg_n_0_\(0), - I1 => \TMDS_1/i_GBox/cntMod5_reg_n_0_\(2), - I2 => \TMDS_1/i_GBox/cntMod5_reg_n_0_\(1), - I3 => qDE, - I4 => \g0_b2_i_1__0_n_0\, - O => \sReg[8]_i_1__0_n_0\ - ); -\sReg[8]_i_1__1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"00101010" - ) - port map ( - I0 => \TMDS_2/i_GBox/cntMod5_reg_n_0_\(0), - I1 => \TMDS_2/i_GBox/cntMod5_reg_n_0_\(2), - I2 => \TMDS_2/i_GBox/cntMod5_reg_n_0_\(1), - I3 => qDE, - I4 => \g0_b2_i_1__1_n_0\, - O => \sReg[8]_i_1__1_n_0\ - ); -\sReg[9]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"4C40404C" - ) - port map ( - I0 => \sReg[9]_i_2_n_0\, - I1 => \sReg[9]_i_3_n_0\, - I2 => qDE, - I3 => qC1C0(1), - I4 => qC1C0(0), - O => \sReg[9]_i_1_n_0\ - ); -\sReg[9]_i_1__0\: unisim.vcomponents.LUT5 - generic map( - INIT => X"00070000" - ) - port map ( - I0 => \sReg[9]_i_2__0_n_0\, - I1 => qDE, - I2 => \TMDS_1/i_GBox/cntMod5_reg_n_0_\(0), - I3 => \TMDS_1/i_GBox/cntMod5_reg_n_0_\(2), - I4 => \TMDS_1/i_GBox/cntMod5_reg_n_0_\(1), - O => \sReg[9]_i_1__0_n_0\ - ); -\sReg[9]_i_1__1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"00070000" - ) - port map ( - I0 => \sReg[9]_i_2__1_n_0\, - I1 => qDE, - I2 => \TMDS_2/i_GBox/cntMod5_reg_n_0_\(0), - I3 => \TMDS_2/i_GBox/cntMod5_reg_n_0_\(2), - I4 => \TMDS_2/i_GBox/cntMod5_reg_n_0_\(1), - O => \sReg[9]_i_1__1_n_0\ - ); -\sReg[9]_i_2\: unisim.vcomponents.LUT5 - generic map( - INIT => X"FFD50015" - ) - port map ( - I0 => \Cnt[4]_i_4_n_0\, - I1 => \Cnt[4]_i_10__1_n_0\, - I2 => \Cnt[4]_i_11_n_0\, - I3 => \sReg[9]_i_4_n_0\, - I4 => g0_b2_i_1_n_0, - O => \sReg[9]_i_2_n_0\ - ); -\sReg[9]_i_2__0\: unisim.vcomponents.LUT3 - generic map( - INIT => X"47" - ) - port map ( - I0 => \Cnt[4]_i_3__0_n_0\, - I1 => \Cnt[4]_i_5__0_n_0\, - I2 => \g0_b2_i_1__0_n_0\, - O => \sReg[9]_i_2__0_n_0\ - ); -\sReg[9]_i_2__1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"47" - ) - port map ( - I0 => \Cnt[4]_i_4__1_n_0\, - I1 => \Cnt[4]_i_6__0_n_0\, - I2 => \g0_b2_i_1__1_n_0\, - O => \sReg[9]_i_2__1_n_0\ - ); -\sReg[9]_i_3\: unisim.vcomponents.LUT3 - generic map( - INIT => X"02" - ) - port map ( - I0 => \TMDS_0/i_GBox/cntMod5_reg_n_0_\(1), - I1 => \TMDS_0/i_GBox/cntMod5_reg_n_0_\(2), - I2 => \TMDS_0/i_GBox/cntMod5_reg_n_0_\(0), - O => \sReg[9]_i_3_n_0\ - ); -\sReg[9]_i_4\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0001" - ) - port map ( - I0 => \TMDS_0/i_Enc/Cnt_reg_n_0_\(4), - I1 => \TMDS_0/i_Enc/Cnt_reg_n_0_\(1), - I2 => \TMDS_0/i_Enc/Cnt_reg_n_0_\(2), - I3 => \TMDS_0/i_Enc/Cnt_reg_n_0_\(3), - O => \sReg[9]_i_4_n_0\ - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_HDMI_TX_wrap is - port ( - HDMI_D0_P : out STD_LOGIC; - HDMI_D0_N : out STD_LOGIC; - HDMI_D1_P : out STD_LOGIC; - HDMI_D1_N : out STD_LOGIC; - HDMI_D2_P : out STD_LOGIC; - HDMI_D2_N : out STD_LOGIC; - HDMI_CK_P : out STD_LOGIC; - HDMI_CK_N : out STD_LOGIC; - pxClk : in STD_LOGIC; - pxClkX5 : in STD_LOGIC; - ResetN : in STD_LOGIC; - DE : in STD_LOGIC; - HSync : in STD_LOGIC; - VSync : in STD_LOGIC; - R : in STD_LOGIC_VECTOR ( 7 downto 0 ); - G : in STD_LOGIC_VECTOR ( 7 downto 0 ); - B : in STD_LOGIC_VECTOR ( 7 downto 0 ) - ); -end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_HDMI_TX_wrap; - -architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_HDMI_TX_wrap is -begin -i_wrap: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_HDMI_TX - port map ( - B(7 downto 0) => B(7 downto 0), - DE => DE, - G(7 downto 0) => G(7 downto 0), - HDMI_CK_N => HDMI_CK_N, - HDMI_CK_P => HDMI_CK_P, - HDMI_D0_N => HDMI_D0_N, - HDMI_D0_P => HDMI_D0_P, - HDMI_D1_N => HDMI_D1_N, - HDMI_D1_P => HDMI_D1_P, - HDMI_D2_N => HDMI_D2_N, - HDMI_D2_P => HDMI_D2_P, - HSync => HSync, - R(7 downto 0) => R(7 downto 0), - ResetN => ResetN, - VSync => VSync, - pxClk => pxClk, - pxClkX5 => pxClkX5 - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is - port ( - pxClk : in STD_LOGIC; - pxClkX5 : in STD_LOGIC; - ResetN : in STD_LOGIC; - DE : in STD_LOGIC; - HSync : in STD_LOGIC; - VSync : in STD_LOGIC; - R : in STD_LOGIC_VECTOR ( 7 downto 0 ); - G : in STD_LOGIC_VECTOR ( 7 downto 0 ); - B : in STD_LOGIC_VECTOR ( 7 downto 0 ); - HDMI_D0_P : out STD_LOGIC; - HDMI_D0_N : out STD_LOGIC; - HDMI_D1_P : out STD_LOGIC; - HDMI_D1_N : out STD_LOGIC; - HDMI_D2_P : out STD_LOGIC; - HDMI_D2_N : out STD_LOGIC; - HDMI_CK_P : out STD_LOGIC; - HDMI_CK_N : out STD_LOGIC - ); - attribute NotValidForBitStream : boolean; - attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; - attribute CHECK_LICENSE_TYPE : string; - attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "design_1_HDMI_TX_0_0,HDMI_TX_wrap,{}"; - attribute downgradeipidentifiedwarnings : string; - attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes"; - attribute ip_definition_source : string; - attribute ip_definition_source of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "package_project"; - attribute x_core_info : string; - attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "HDMI_TX_wrap,Vivado 2025.1"; -end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; - -architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is -begin -U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_HDMI_TX_wrap - port map ( - B(7 downto 0) => B(7 downto 0), - DE => DE, - G(7 downto 0) => G(7 downto 0), - HDMI_CK_N => HDMI_CK_N, - HDMI_CK_P => HDMI_CK_P, - HDMI_D0_N => HDMI_D0_N, - HDMI_D0_P => HDMI_D0_P, - HDMI_D1_N => HDMI_D1_N, - HDMI_D1_P => HDMI_D1_P, - HDMI_D2_N => HDMI_D2_N, - HDMI_D2_P => HDMI_D2_P, - HSync => HSync, - R(7 downto 0) => R(7 downto 0), - ResetN => ResetN, - VSync => VSync, - pxClk => pxClk, - pxClkX5 => pxClkX5 - ); -end STRUCTURE; diff --git a/SW2.cache/ip/2025.1/5/b/5be5567f865f5e2e/design_1_HDMI_TX_0_0_stub.v b/SW2.cache/ip/2025.1/5/b/5be5567f865f5e2e/design_1_HDMI_TX_0_0_stub.v deleted file mode 100644 index 7188445..0000000 --- a/SW2.cache/ip/2025.1/5/b/5be5567f865f5e2e/design_1_HDMI_TX_0_0_stub.v +++ /dev/null @@ -1,41 +0,0 @@ -// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2025.1 (win64) Build 6140274 Thu May 22 00:12:29 MDT 2025 -// Date : Tue Apr 28 14:09:27 2026 -// Host : Lab016-05 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_HDMI_TX_0_0_stub.v -// Design : design_1_HDMI_TX_0_0 -// Purpose : Stub declaration of top-level module interface -// Device : xczu3eg-sfvc784-2-e -// -------------------------------------------------------------------------------- - -// This empty module with port declaration file causes synthesis tools to infer a black box for IP. -// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. -// Please paste the declaration into a Verilog source file or add the file as an additional source. -(* CHECK_LICENSE_TYPE = "design_1_HDMI_TX_0_0,HDMI_TX_wrap,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) -(* x_core_info = "HDMI_TX_wrap,Vivado 2025.1" *) -module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(pxClk, pxClkX5, ResetN, DE, HSync, VSync, R, G, B, - HDMI_D0_P, HDMI_D0_N, HDMI_D1_P, HDMI_D1_N, HDMI_D2_P, HDMI_D2_N, HDMI_CK_P, HDMI_CK_N) -/* synthesis syn_black_box black_box_pad_pin="ResetN,DE,HSync,VSync,R[7:0],G[7:0],B[7:0],HDMI_D0_P,HDMI_D0_N,HDMI_D1_P,HDMI_D1_N,HDMI_D2_P,HDMI_D2_N,HDMI_CK_P,HDMI_CK_N" */ -/* synthesis syn_force_seq_prim="pxClk" */ -/* synthesis syn_force_seq_prim="pxClkX5" */; - input pxClk /* synthesis syn_isclock = 1 */; - input pxClkX5 /* synthesis syn_isclock = 1 */; - input ResetN; - input DE; - input HSync; - input VSync; - input [7:0]R; - input [7:0]G; - input [7:0]B; - output HDMI_D0_P; - output HDMI_D0_N; - output HDMI_D1_P; - output HDMI_D1_N; - output HDMI_D2_P; - output HDMI_D2_N; - output HDMI_CK_P; - output HDMI_CK_N; -endmodule diff --git a/SW2.cache/ip/2025.1/5/b/5be5567f865f5e2e/design_1_HDMI_TX_0_0_stub.vhdl b/SW2.cache/ip/2025.1/5/b/5be5567f865f5e2e/design_1_HDMI_TX_0_0_stub.vhdl deleted file mode 100644 index 3ccaa75..0000000 --- a/SW2.cache/ip/2025.1/5/b/5be5567f865f5e2e/design_1_HDMI_TX_0_0_stub.vhdl +++ /dev/null @@ -1,53 +0,0 @@ --- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. --- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2025.1 (win64) Build 6140274 Thu May 22 00:12:29 MDT 2025 --- Date : Tue Apr 28 14:09:27 2026 --- Host : Lab016-05 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix --- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_HDMI_TX_0_0_stub.vhdl --- Design : design_1_HDMI_TX_0_0 --- Purpose : Stub declaration of top-level module interface --- Device : xczu3eg-sfvc784-2-e --- -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - -entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is - Port ( - pxClk : in STD_LOGIC; - pxClkX5 : in STD_LOGIC; - ResetN : in STD_LOGIC; - DE : in STD_LOGIC; - HSync : in STD_LOGIC; - VSync : in STD_LOGIC; - R : in STD_LOGIC_VECTOR ( 7 downto 0 ); - G : in STD_LOGIC_VECTOR ( 7 downto 0 ); - B : in STD_LOGIC_VECTOR ( 7 downto 0 ); - HDMI_D0_P : out STD_LOGIC; - HDMI_D0_N : out STD_LOGIC; - HDMI_D1_P : out STD_LOGIC; - HDMI_D1_N : out STD_LOGIC; - HDMI_D2_P : out STD_LOGIC; - HDMI_D2_N : out STD_LOGIC; - HDMI_CK_P : out STD_LOGIC; - HDMI_CK_N : out STD_LOGIC - ); - - attribute CHECK_LICENSE_TYPE : string; - attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "design_1_HDMI_TX_0_0,HDMI_TX_wrap,{}"; - attribute downgradeipidentifiedwarnings : string; - attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes"; - attribute ip_definition_source : string; - attribute ip_definition_source of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "package_project"; -end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; - -architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is - attribute syn_black_box : boolean; - attribute black_box_pad_pin : string; - attribute syn_black_box of stub : architecture is true; - attribute black_box_pad_pin of stub : architecture is "pxClk,pxClkX5,ResetN,DE,HSync,VSync,R[7:0],G[7:0],B[7:0],HDMI_D0_P,HDMI_D0_N,HDMI_D1_P,HDMI_D1_N,HDMI_D2_P,HDMI_D2_N,HDMI_CK_P,HDMI_CK_N"; - attribute x_core_info : string; - attribute x_core_info of stub : architecture is "HDMI_TX_wrap,Vivado 2025.1"; -begin -end; diff --git a/SW2.cache/wt/project.wpc b/SW2.cache/wt/project.wpc index 2599f42..d5e2b40 100644 --- a/SW2.cache/wt/project.wpc +++ b/SW2.cache/wt/project.wpc @@ -1,3 +1,3 @@ version:1 -6d6f64655f636f756e7465727c4755494d6f6465:7 +6d6f64655f636f756e7465727c4755494d6f6465:8 eof: diff --git a/SW2.cache/wt/synthesis.wdf b/SW2.cache/wt/synthesis.wdf index 068947f..d209a25 100644 --- a/SW2.cache/wt/synthesis.wdf +++ b/SW2.cache/wt/synthesis.wdf @@ -46,7 +46,7 @@ version:1 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64656275675f6c6f67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d657374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 -73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a343973:00:00 -73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323736322e3830314d42:00:00 -73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:323230352e3830354d42:00:00 -eof:3722403174 +73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30313a353473:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323838332e3334344d42:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:323239362e3439324d42:00:00 +eof:612253595 diff --git a/SW2.runs/.jobs/vrs_config_59.xml b/SW2.runs/.jobs/vrs_config_59.xml new file mode 100644 index 0000000..86d61e3 --- /dev/null +++ b/SW2.runs/.jobs/vrs_config_59.xml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/SW2.runs/design_1_EnemyController_0_0_synth_1/gen_run.xml b/SW2.runs/design_1_EnemyController_0_0_synth_1/gen_run.xml index da29697..6acf0e6 100644 --- a/SW2.runs/design_1_EnemyController_0_0_synth_1/gen_run.xml +++ b/SW2.runs/design_1_EnemyController_0_0_synth_1/gen_run.xml @@ -1,14 +1,11 @@ - - - + + - - @@ -52,9 +49,7 @@ - - Vivado Synthesis Defaults - + diff --git a/SW2.runs/design_1_GameController_0_0_synth_1/gen_run.xml b/SW2.runs/design_1_GameController_0_0_synth_1/gen_run.xml index b7d1779..530c584 100644 --- a/SW2.runs/design_1_GameController_0_0_synth_1/gen_run.xml +++ b/SW2.runs/design_1_GameController_0_0_synth_1/gen_run.xml @@ -1,14 +1,11 @@ - - - + + - - @@ -50,9 +47,7 @@ - - Vivado Synthesis Defaults - + diff --git a/SW2.runs/design_1_ImgGen_0_0_synth_1/gen_run.xml b/SW2.runs/design_1_ImgGen_0_0_synth_1/gen_run.xml index aaff6b8..12c19e9 100644 --- a/SW2.runs/design_1_ImgGen_0_0_synth_1/gen_run.xml +++ b/SW2.runs/design_1_ImgGen_0_0_synth_1/gen_run.xml @@ -1,14 +1,11 @@ - - - + + - - @@ -52,9 +49,7 @@ - - Vivado Synthesis Defaults - + diff --git a/SW2.runs/impl_1/.Vivado_Implementation.queue.rst b/SW2.runs/impl_1/.Vivado_Implementation.queue.rst deleted file mode 100644 index e69de29..0000000 diff --git a/SW2.runs/impl_1/.init_design.begin.rst b/SW2.runs/impl_1/.init_design.begin.rst deleted file mode 100644 index d7a44a7..0000000 --- a/SW2.runs/impl_1/.init_design.begin.rst +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/SW2.runs/impl_1/.init_design.end.rst b/SW2.runs/impl_1/.init_design.end.rst deleted file mode 100644 index e69de29..0000000 diff --git a/SW2.runs/impl_1/.opt_design.begin.rst b/SW2.runs/impl_1/.opt_design.begin.rst deleted file mode 100644 index d7a44a7..0000000 --- a/SW2.runs/impl_1/.opt_design.begin.rst +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/SW2.runs/impl_1/.opt_design.end.rst b/SW2.runs/impl_1/.opt_design.end.rst deleted file mode 100644 index e69de29..0000000 diff --git a/SW2.runs/impl_1/.phys_opt_design.begin.rst b/SW2.runs/impl_1/.phys_opt_design.begin.rst deleted file mode 100644 index d7a44a7..0000000 --- a/SW2.runs/impl_1/.phys_opt_design.begin.rst +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/SW2.runs/impl_1/.phys_opt_design.end.rst b/SW2.runs/impl_1/.phys_opt_design.end.rst deleted file mode 100644 index e69de29..0000000 diff --git a/SW2.runs/impl_1/.place_design.begin.rst b/SW2.runs/impl_1/.place_design.begin.rst deleted file mode 100644 index d7a44a7..0000000 --- a/SW2.runs/impl_1/.place_design.begin.rst +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/SW2.runs/impl_1/.place_design.end.rst b/SW2.runs/impl_1/.place_design.end.rst deleted file mode 100644 index e69de29..0000000 diff --git a/SW2.runs/impl_1/.route_design.begin.rst b/SW2.runs/impl_1/.route_design.begin.rst deleted file mode 100644 index d7a44a7..0000000 --- a/SW2.runs/impl_1/.route_design.begin.rst +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/SW2.runs/impl_1/.route_design.end.rst b/SW2.runs/impl_1/.route_design.end.rst deleted file mode 100644 index e69de29..0000000 diff --git a/SW2.runs/impl_1/.vivado.begin.rst b/SW2.runs/impl_1/.vivado.begin.rst deleted file mode 100644 index d9b3a50..0000000 --- a/SW2.runs/impl_1/.vivado.begin.rst +++ /dev/null @@ -1,40 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/SW2.runs/impl_1/.vivado.end.rst b/SW2.runs/impl_1/.vivado.end.rst deleted file mode 100644 index e69de29..0000000 diff --git a/SW2.runs/impl_1/.write_bitstream.begin.rst b/SW2.runs/impl_1/.write_bitstream.begin.rst deleted file mode 100644 index d7a44a7..0000000 --- a/SW2.runs/impl_1/.write_bitstream.begin.rst +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/SW2.runs/impl_1/.write_bitstream.end.rst b/SW2.runs/impl_1/.write_bitstream.end.rst deleted file mode 100644 index e69de29..0000000 diff --git a/SW2.runs/impl_1/ISEWrap.js b/SW2.runs/impl_1/ISEWrap.js deleted file mode 100644 index 61806d0..0000000 --- a/SW2.runs/impl_1/ISEWrap.js +++ /dev/null @@ -1,270 +0,0 @@ -// -// Vivado(TM) -// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 -// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -// - -// GLOBAL VARIABLES -var ISEShell = new ActiveXObject( "WScript.Shell" ); -var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); -var ISERunDir = ""; -var ISELogFile = "runme.log"; -var ISELogFileStr = null; -var ISELogEcho = true; -var ISEOldVersionWSH = false; - - - -// BOOTSTRAP -ISEInit(); - - - -// -// ISE FUNCTIONS -// -function ISEInit() { - - // 1. RUN DIR setup - var ISEScrFP = WScript.ScriptFullName; - var ISEScrN = WScript.ScriptName; - ISERunDir = - ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); - - // 2. LOG file setup - ISELogFileStr = ISEOpenFile( ISELogFile ); - - // 3. LOG echo? - var ISEScriptArgs = WScript.Arguments; - for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; - ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); - ISELogFileStr = ISEOpenFile( ISELogFile ); - - } else { // WSH 5.6 - - // LAUNCH! - ISEShell.CurrentDirectory = ISERunDir; - - // Redirect STDERR to STDOUT - ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; - var ISEProcess = ISEShell.Exec( ISECmdLine ); - - // BEGIN file creation - var wbemFlagReturnImmediately = 0x10; - var wbemFlagForwardOnly = 0x20; - var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); - var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); - var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); - var NOC = 0; - var NOLP = 0; - var TPM = 0; - var cpuInfos = new Enumerator(processor); - for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { - var cpuInfo = cpuInfos.item(); - NOC += cpuInfo.NumberOfCores; - NOLP += cpuInfo.NumberOfLogicalProcessors; - } - var csInfos = new Enumerator(computerSystem); - for(;!csInfos.atEnd(); csInfos.moveNext()) { - var csInfo = csInfos.item(); - TPM += csInfo.TotalPhysicalMemory; - } - - var ISEHOSTCORE = NOLP - var ISEMEMTOTAL = TPM - - var ISENetwork = WScript.CreateObject( "WScript.Network" ); - var ISEHost = ISENetwork.ComputerName; - var ISEUser = ISENetwork.UserName; - var ISEPid = ISEProcess.ProcessID; - var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.Close(); - - var ISEOutStr = ISEProcess.StdOut; - var ISEErrStr = ISEProcess.StdErr; - - // WAIT for ISEStep to finish - while ( ISEProcess.Status == 0 ) { - - // dump stdout then stderr - feels a little arbitrary - while ( !ISEOutStr.AtEndOfStream ) { - ISEStdOut( ISEOutStr.ReadLine() ); - } - - WScript.Sleep( 100 ); - } - - ISEExitCode = ISEProcess.ExitCode; - } - - ISELogFileStr.Close(); - - // END/ERROR file creation - if ( ISEExitCode != 0 ) { - ISETouchFile( ISEStep, "error" ); - - } else { - ISETouchFile( ISEStep, "end" ); - } - - return ISEExitCode; -} - - -// -// UTILITIES -// -function ISEStdOut( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdOut.WriteLine( ISELine ); - } -} - -function ISEStdErr( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdErr.WriteLine( ISELine ); - } -} - -function ISETouchFile( ISERoot, ISEStatus ) { - - var ISETFile = - ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); - ISETFile.Close(); -} - -function ISEOpenFile( ISEFilename ) { - - // This function has been updated to deal with a problem seen in CR #870871. - // In that case the user runs a script that runs impl_1, and then turns around - // and runs impl_1 -to_step write_bitstream. That second run takes place in - // the same directory, which means we may hit some of the same files, and in - // particular, we will open the runme.log file. Even though this script closes - // the file (now), we see cases where a subsequent attempt to open the file - // fails. Perhaps the OS is slow to release the lock, or the disk comes into - // play? In any case, we try to work around this by first waiting if the file - // is already there for an arbitrary 5 seconds. Then we use a try-catch block - // and try to open the file 10 times with a one second delay after each attempt. - // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. - // If there is an unrecognized exception when trying to open the file, we output - // an error message and write details to an exception.log file. - var ISEFullPath = ISERunDir + "/" + ISEFilename; - if (ISEFileSys.FileExists(ISEFullPath)) { - // File is already there. This could be a problem. Wait in case it is still in use. - WScript.Sleep(5000); - } - var i; - for (i = 0; i < 10; ++i) { - try { - return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); - } catch (exception) { - var error_code = exception.number & 0xFFFF; // The other bits are a facility code. - if (error_code == 52) { // 52 is bad file name or number. - // Wait a second and try again. - WScript.Sleep(1000); - continue; - } else { - WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - var exceptionFilePath = ISERunDir + "/exception.log"; - if (!ISEFileSys.FileExists(exceptionFilePath)) { - WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); - var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); - exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - exceptionFile.WriteLine("\tException name: " + exception.name); - exceptionFile.WriteLine("\tException error code: " + error_code); - exceptionFile.WriteLine("\tException message: " + exception.message); - exceptionFile.Close(); - } - throw exception; - } - } - } - // If we reached this point, we failed to open the file after 10 attempts. - // We need to error out. - WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); - WScript.Quit(1); -} diff --git a/SW2.runs/impl_1/ISEWrap.sh b/SW2.runs/impl_1/ISEWrap.sh deleted file mode 100644 index 05d5381..0000000 --- a/SW2.runs/impl_1/ISEWrap.sh +++ /dev/null @@ -1,85 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# ISEWrap.sh: Vivado Runs Script for UNIX -# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -# - -cmd_exists() -{ - command -v "$1" >/dev/null 2>&1 -} - -HD_LOG=$1 -shift - -# CHECK for a STOP FILE -if [ -f .stop.rst ] -then -echo "" >> $HD_LOG -echo "*** Halting run - EA reset detected ***" >> $HD_LOG -echo "" >> $HD_LOG -exit 1 -fi - -ISE_STEP=$1 -shift - -# WRITE STEP HEADER to LOG -echo "" >> $HD_LOG -echo "*** Running $ISE_STEP" >> $HD_LOG -echo " with args $@" >> $HD_LOG -echo "" >> $HD_LOG - -# LAUNCH! -$ISE_STEP "$@" >> $HD_LOG 2>&1 & - -# BEGIN file creation -ISE_PID=$! - -HostNameFile=/proc/sys/kernel/hostname -if cmd_exists hostname -then -ISE_HOST=$(hostname) -elif cmd_exists uname -then -ISE_HOST=$(uname -n) -elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ] -then -ISE_HOST=$(cat $HostNameFile) -elif [ X != X$HOSTNAME ] -then -ISE_HOST=$HOSTNAME #bash -else -ISE_HOST=$HOST #csh -fi - -ISE_USER=$USER - -ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) -ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) - -ISE_BEGINFILE=.$ISE_STEP.begin.rst -/bin/touch $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE - -# WAIT for ISEStep to finish -wait $ISE_PID - -# END/ERROR file creation -RETVAL=$? -if [ $RETVAL -eq 0 ] -then - /bin/touch .$ISE_STEP.end.rst -else - /bin/touch .$ISE_STEP.error.rst -fi - -exit $RETVAL - diff --git a/SW2.runs/impl_1/clockInfo.txt b/SW2.runs/impl_1/clockInfo.txt deleted file mode 100644 index 615c89a..0000000 --- a/SW2.runs/impl_1/clockInfo.txt +++ /dev/null @@ -1,51 +0,0 @@ -------------------------------------- -| Tool Version : Vivado v.2025.1 -| Date : Tue Jun 9 14:06:46 2026 -| Host : Lab016-04 -| Design : design_1 -| Device : xczu3eg-sfvc784-2-E- -------------------------------------- - -For more information on clockInfo.txt clock routing debug file see https://support.xilinx.com/s/article/000035660?language=en_US - -*********************** -Running Pre-CRP Checker -*********************** -Number of global clocks: 3 - Number of BUFGCE: 3 - Number of BUFGCE_HDIO: 0 - Number of BUFG_CTRL: 0 - Number of BUFGCE_DIV: 0 - Number of BUFG_GT: 0 - Number of BUFG_PS: 0 - Number of BUFG_FABRIC: 0 - Running suboptimal placement checker for 3 clocks (and their loads) which do not have the CLOCK_LOW_FANOUT property but have a fanout less than 2000... -Pre-CRP Checker took 0 secs - -******************************** -Clock Net Route Info (CRP Input) -******************************** -Clock 1: design_1_i/TickGenerator_0/inst/FrameTick_BUFGCE - Clock source type: BUFGCE - Clock source region: X1Y0 - initial rect ((0, 0), (1, 0)) - -Clock 2: design_1_i/clk_wiz_0/inst/clk25 - Clock source type: BUFGCE - Clock source region: X1Y2 - initial rect ((0, 0), (1, 2)) - -Clock 3: design_1_i/clk_wiz_0/inst/clk125 - Clock source type: BUFGCE - Clock source region: X1Y2 - Clock regions with locked loads: X1Y0 - initial rect ((0, 0), (1, 2)) - - - -***************** -User Constraints: -***************** -No user constraints found - - diff --git a/SW2.runs/impl_1/design_1_wrapper.bit b/SW2.runs/impl_1/design_1_wrapper.bit deleted file mode 100644 index 5142edd..0000000 Binary files a/SW2.runs/impl_1/design_1_wrapper.bit and /dev/null differ diff --git a/SW2.runs/impl_1/design_1_wrapper.tcl b/SW2.runs/impl_1/design_1_wrapper.tcl deleted file mode 100644 index dfeedd2..0000000 --- a/SW2.runs/impl_1/design_1_wrapper.tcl +++ /dev/null @@ -1,330 +0,0 @@ -namespace eval ::optrace { - variable script "C:/Users/lab/Documents/GitHub/SW2/SW2.runs/impl_1/design_1_wrapper.tcl" - variable category "vivado_impl" -} - -# Try to connect to running dispatch if we haven't done so already. -# This code assumes that the Tcl interpreter is not using threads, -# since the ::dispatch::connected variable isn't mutex protected. -if {![info exists ::dispatch::connected]} { - namespace eval ::dispatch { - variable connected false - if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} { - set result "true" - if {[catch { - if {[lsearch -exact [package names] DispatchTcl] < 0} { - set result [load librdi_cd_clienttcl[info sharedlibextension]] - } - if {$result eq "false"} { - puts "WARNING: Could not load dispatch client library" - } - set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ] - if { $connect_id eq "" } { - puts "WARNING: Could not initialize dispatch client" - } else { - puts "INFO: Dispatch client connection id - $connect_id" - set connected true - } - } catch_res]} { - puts "WARNING: failed to connect to dispatch server - $catch_res" - } - } - } -} -if {$::dispatch::connected} { - # Remove the dummy proc if it exists. - if { [expr {[llength [info procs ::OPTRACE]] > 0}] } { - rename ::OPTRACE "" - } - proc ::OPTRACE { task action {tags {} } } { - ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category - } - # dispatch is generic. We specifically want to attach logging. - ::vitis_log::connect_client -} else { - # Add dummy proc if it doesn't exist. - if { [expr {[llength [info procs ::OPTRACE]] == 0}] } { - proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} { - # Do nothing - } - } -} - -proc start_step { step } { - set stopFile ".stop.rst" - if {[file isfile .stop.rst]} { - puts "" - puts "*** Halting run - EA reset detected ***" - puts "" - puts "" - return -code error - } - set beginFile ".$step.begin.rst" - set platform "$::tcl_platform(platform)" - set user "$::tcl_platform(user)" - set pid [pid] - set host "" - if { [string equal $platform unix] } { - if { [info exist ::env(HOSTNAME)] } { - set host $::env(HOSTNAME) - } elseif { [info exist ::env(HOST)] } { - set host $::env(HOST) - } - } else { - if { [info exist ::env(COMPUTERNAME)] } { - set host $::env(COMPUTERNAME) - } - } - set ch [open $beginFile w] - puts $ch "" - puts $ch "" - puts $ch " " - puts $ch " " - puts $ch "" - close $ch -} - -proc end_step { step } { - set endFile ".$step.end.rst" - set ch [open $endFile w] - close $ch -} - -proc step_failed { step } { - set endFile ".$step.error.rst" - set ch [open $endFile w] - close $ch -OPTRACE "impl_1" END { } -} - - -OPTRACE "impl_1" START { ROLLUP_1 } -OPTRACE "Phase: Init Design" START { ROLLUP_AUTO } -start_step init_design -set ACTIVE_STEP init_design -set rc [catch { - create_msg_db init_design.pb - set_param general.maxThreads 6 - set_param chipscope.maxJobs 3 - set_param general.usePosixSpawnForFork 1 - set_param xicom.use_bs_reader 1 - set_param runs.launchOptions { -jobs 6 } -OPTRACE "create in-memory project" START { } - create_project -in_memory -part xczu3eg-sfvc784-2-e - set_property board_part_repo_paths {C:/Xilinx/Board_repo} [current_project] - set_property board_part realdigital.org:aup-zu3-8gb:part0:1.0 [current_project] - set_property design_mode GateLvl [current_fileset] - set_param project.singleFileAddWarning.threshold 0 -OPTRACE "create in-memory project" END { } -OPTRACE "set parameters" START { } - set_property webtalk.parent_dir C:/Users/lab/Documents/GitHub/SW2/SW2.cache/wt [current_project] - set_property parent.project_path C:/Users/lab/Documents/GitHub/SW2/SW2.xpr [current_project] - set_property ip_repo_paths { - C:/Xilinx/IP_Repo - C:/Xilinx/IP_Repo/OLED_ASCII -} [current_project] - update_ip_catalog - set_property ip_output_repo C:/Users/lab/Documents/GitHub/SW2/SW2.cache/ip [current_project] - set_property ip_cache_permissions {read write} [current_project] - set_property XPM_LIBRARIES XPM_CDC [current_project] -OPTRACE "set parameters" END { } -OPTRACE "add files" START { } - add_files -quiet C:/Users/lab/Documents/GitHub/SW2/SW2.runs/synth_1/design_1_wrapper.dcp - set_msg_config -source 4 -id {BD 41-1661} -limit 0 - set_param project.isImplRun true - add_files C:/Users/lab/Documents/GitHub/SW2/SW2.srcs/sources_1/bd/design_1/design_1.bd - set_param project.isImplRun false -OPTRACE "read constraints: implementation" START { } - read_xdc C:/Users/lab/Documents/GitHub/SW2/SW2.srcs/constrs_1/new/mainconstraint.xdc - read_xdc C:/Users/lab/Documents/GitHub/SW2/SW2.srcs/constrs_1/new/sideconstraint.xdc -OPTRACE "read constraints: implementation" END { } -OPTRACE "read constraints: implementation_pre" START { } -OPTRACE "read constraints: implementation_pre" END { } -OPTRACE "add files" END { } -OPTRACE "link_design" START { } - set_param project.isImplRun true - link_design -top design_1_wrapper -part xczu3eg-sfvc784-2-e -OPTRACE "link_design" END { } - set_param project.isImplRun false -OPTRACE "gray box cells" START { } -OPTRACE "gray box cells" END { } -OPTRACE "init_design_reports" START { REPORT } -OPTRACE "init_design_reports" END { } -OPTRACE "init_design_write_hwdef" START { } -OPTRACE "init_design_write_hwdef" END { } - close_msg_db -file init_design.pb -} RESULT] -if {$rc} { - step_failed init_design - return -code error $RESULT -} else { - end_step init_design - unset ACTIVE_STEP -} - -OPTRACE "Phase: Init Design" END { } -OPTRACE "Phase: Opt Design" START { ROLLUP_AUTO } -start_step opt_design -set ACTIVE_STEP opt_design -set rc [catch { - create_msg_db opt_design.pb -OPTRACE "read constraints: opt_design" START { } -OPTRACE "read constraints: opt_design" END { } -OPTRACE "opt_design" START { } - opt_design -OPTRACE "opt_design" END { } -OPTRACE "read constraints: opt_design_post" START { } -OPTRACE "read constraints: opt_design_post" END { } -OPTRACE "opt_design reports" START { REPORT } - set_param project.isImplRun true - generate_parallel_reports -reports { "report_drc -file design_1_wrapper_drc_opted.rpt -pb design_1_wrapper_drc_opted.pb -rpx design_1_wrapper_drc_opted.rpx" } - set_param project.isImplRun false -OPTRACE "opt_design reports" END { } -OPTRACE "Opt Design: write_checkpoint" START { CHECKPOINT } - write_checkpoint -force design_1_wrapper_opt.dcp -OPTRACE "Opt Design: write_checkpoint" END { } - close_msg_db -file opt_design.pb -} RESULT] -if {$rc} { - step_failed opt_design - return -code error $RESULT -} else { - end_step opt_design - unset ACTIVE_STEP -} - -OPTRACE "Phase: Opt Design" END { } -OPTRACE "Phase: Place Design" START { ROLLUP_AUTO } -start_step place_design -set ACTIVE_STEP place_design -set rc [catch { - create_msg_db place_design.pb -OPTRACE "read constraints: place_design" START { } -OPTRACE "read constraints: place_design" END { } - if { [llength [get_debug_cores -quiet] ] > 0 } { -OPTRACE "implement_debug_core" START { } - implement_debug_core -OPTRACE "implement_debug_core" END { } - } -OPTRACE "place_design" START { } - set_param project.isImplRun true - place_design - set_param project.isImplRun false -OPTRACE "place_design" END { } -OPTRACE "read constraints: place_design_post" START { } -OPTRACE "read constraints: place_design_post" END { } -OPTRACE "place_design reports" START { REPORT } - set_param project.isImplRun true - generate_parallel_reports -reports { "report_io -file design_1_wrapper_io_placed.rpt" "report_utilization -file design_1_wrapper_utilization_placed.rpt -pb design_1_wrapper_utilization_placed.pb" "report_control_sets -verbose -file design_1_wrapper_control_sets_placed.rpt" } - set_param project.isImplRun false -OPTRACE "place_design reports" END { } -OPTRACE "Place Design: write_checkpoint" START { CHECKPOINT } - write_checkpoint -force design_1_wrapper_placed.dcp -OPTRACE "Place Design: write_checkpoint" END { } - close_msg_db -file place_design.pb -} RESULT] -if {$rc} { - step_failed place_design - return -code error $RESULT -} else { - end_step place_design - unset ACTIVE_STEP -} - -OPTRACE "Phase: Place Design" END { } -OPTRACE "Phase: Physical Opt Design" START { ROLLUP_AUTO } -start_step phys_opt_design -set ACTIVE_STEP phys_opt_design -set rc [catch { - create_msg_db phys_opt_design.pb -OPTRACE "read constraints: phys_opt_design" START { } -OPTRACE "read constraints: phys_opt_design" END { } -OPTRACE "phys_opt_design" START { } - phys_opt_design -OPTRACE "phys_opt_design" END { } -OPTRACE "read constraints: phys_opt_design_post" START { } -OPTRACE "read constraints: phys_opt_design_post" END { } -OPTRACE "phys_opt_design report" START { REPORT } -OPTRACE "phys_opt_design report" END { } -OPTRACE "Post-Place Phys Opt Design: write_checkpoint" START { CHECKPOINT } - write_checkpoint -force design_1_wrapper_physopt.dcp -OPTRACE "Post-Place Phys Opt Design: write_checkpoint" END { } - close_msg_db -file phys_opt_design.pb -} RESULT] -if {$rc} { - step_failed phys_opt_design - return -code error $RESULT -} else { - end_step phys_opt_design - unset ACTIVE_STEP -} - -OPTRACE "Phase: Physical Opt Design" END { } -OPTRACE "Phase: Route Design" START { ROLLUP_AUTO } -start_step route_design -set ACTIVE_STEP route_design -set rc [catch { - create_msg_db route_design.pb -OPTRACE "read constraints: route_design" START { } -OPTRACE "read constraints: route_design" END { } -OPTRACE "route_design" START { } - route_design -OPTRACE "route_design" END { } -OPTRACE "read constraints: route_design_post" START { } -OPTRACE "read constraints: route_design_post" END { } -OPTRACE "route_design reports" START { REPORT } - set_param project.isImplRun true - generate_parallel_reports -reports { "report_drc -file design_1_wrapper_drc_routed.rpt -pb design_1_wrapper_drc_routed.pb -rpx design_1_wrapper_drc_routed.rpx" "report_methodology -file design_1_wrapper_methodology_drc_routed.rpt -pb design_1_wrapper_methodology_drc_routed.pb -rpx design_1_wrapper_methodology_drc_routed.rpx" "report_power -file design_1_wrapper_power_routed.rpt -pb design_1_wrapper_power_summary_routed.pb -rpx design_1_wrapper_power_routed.rpx" "report_route_status -file design_1_wrapper_route_status.rpt -pb design_1_wrapper_route_status.pb" "report_timing_summary -max_paths 10 -routable_nets -report_unconstrained -file design_1_wrapper_timing_summary_routed.rpt -pb design_1_wrapper_timing_summary_routed.pb -rpx design_1_wrapper_timing_summary_routed.rpx -warn_on_violation " "report_incremental_reuse -file design_1_wrapper_incremental_reuse_routed.rpt" "report_clock_utilization -file design_1_wrapper_clock_utilization_routed.rpt" "report_bus_skew -warn_on_violation -file design_1_wrapper_bus_skew_routed.rpt -pb design_1_wrapper_bus_skew_routed.pb -rpx design_1_wrapper_bus_skew_routed.rpx" } - set_param project.isImplRun false -OPTRACE "route_design reports" END { } -OPTRACE "Route Design: write_checkpoint" START { CHECKPOINT } - write_checkpoint -force design_1_wrapper_routed.dcp -OPTRACE "Route Design: write_checkpoint" END { } -OPTRACE "route_design misc" START { } - close_msg_db -file route_design.pb -} RESULT] -if {$rc} { -OPTRACE "route_design write_checkpoint" START { CHECKPOINT } -OPTRACE "route_design write_checkpoint" END { } - write_checkpoint -force design_1_wrapper_routed_error.dcp - step_failed route_design - return -code error $RESULT -} else { - end_step route_design - unset ACTIVE_STEP -} - -OPTRACE "route_design misc" END { } -OPTRACE "Phase: Route Design" END { } -OPTRACE "Phase: Write Bitstream" START { ROLLUP_AUTO } -OPTRACE "write_bitstream setup" START { } -start_step write_bitstream -set ACTIVE_STEP write_bitstream -set rc [catch { - create_msg_db write_bitstream.pb -OPTRACE "read constraints: write_bitstream" START { } -OPTRACE "read constraints: write_bitstream" END { } - set_property XPM_LIBRARIES XPM_CDC [current_project] - catch { write_mem_info -force -no_partial_mmi design_1_wrapper.mmi } -OPTRACE "write_bitstream setup" END { } -OPTRACE "write_bitstream" START { } - write_bitstream -force design_1_wrapper.bit -OPTRACE "write_bitstream" END { } -OPTRACE "write_bitstream misc" START { } -OPTRACE "read constraints: write_bitstream_post" START { } -OPTRACE "read constraints: write_bitstream_post" END { } - catch {write_debug_probes -quiet -force design_1_wrapper} - catch {file copy -force design_1_wrapper.ltx debug_nets.ltx} - close_msg_db -file write_bitstream.pb -} RESULT] -if {$rc} { - step_failed write_bitstream - return -code error $RESULT -} else { - end_step write_bitstream - unset ACTIVE_STEP -} - -OPTRACE "write_bitstream misc" END { } -OPTRACE "Phase: Write Bitstream" END { } -OPTRACE "impl_1" END { } diff --git a/SW2.runs/impl_1/design_1_wrapper.vdi b/SW2.runs/impl_1/design_1_wrapper.vdi deleted file mode 100644 index 5c3572e..0000000 --- a/SW2.runs/impl_1/design_1_wrapper.vdi +++ /dev/null @@ -1,831 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2025.1 (64-bit) -# SW Build 6140274 on Thu May 22 00:12:29 MDT 2025 -# IP Build 6138677 on Thu May 22 03:10:11 MDT 2025 -# SharedData Build 6139179 on Tue May 20 17:58:58 MDT 2025 -# Start of session at: Tue Jun 9 14:05:43 2026 -# Process ID : 8876 -# Current directory : C:/Users/lab/Documents/GitHub/SW2/SW2.runs/impl_1 -# Command line : vivado.exe -log design_1_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source design_1_wrapper.tcl -notrace -# Log file : C:/Users/lab/Documents/GitHub/SW2/SW2.runs/impl_1/design_1_wrapper.vdi -# Journal file : C:/Users/lab/Documents/GitHub/SW2/SW2.runs/impl_1\vivado.jou -# Running On : Lab016-04 -# Platform : Windows Server 2016 or Windows 10 -# Operating System : 19045 -# Processor Detail : Intel(R) Core(TM) i7-8700 CPU @ 3.20GHz -# CPU Frequency : 3192 MHz -# CPU Physical cores : 6 -# CPU Logical cores : 12 -# Host memory : 17030 MB -# Swap memory : 2550 MB -# Total Virtual : 19580 MB -# Available Virtual : 12132 MB -#----------------------------------------------------------- -Sourcing tcl script 'C:/Users/lab/AppData/Roaming/Xilinx/Vivado/Vivado_init.tcl' -source design_1_wrapper.tcl -notrace -create_project: Time (s): cpu = 00:00:21 ; elapsed = 00:00:05 . Memory (MB): peak = 512.504 ; gain = 232.082 -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Xilinx/IP_Repo'. -WARNING: [IP_Flow 19-3685] Ignored loading user repository 'c:/Xilinx/IP_Repo/OLED_ASCII'. The path is contained within another repository. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/2025.1/Vivado/data/ip'. -Command: link_design -top design_1_wrapper -part xczu3eg-sfvc784-2-e -Design is defaulting to srcset: sources_1 -Design is defaulting to constrset: constrs_1 -INFO: [Device 21-403] Loading part xczu3eg-sfvc784-2-e -INFO: [Project 1-5699] Read binary netlist with skipMacroContent - 1 -INFO: [Project 1-454] Reading design checkpoint 'c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_EnemyController_0_0/design_1_EnemyController_0_0.dcp' for cell 'design_1_i/EnemyController_0' -INFO: [Project 1-454] Reading design checkpoint 'c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_GameController_0_0/design_1_GameController_0_0.dcp' for cell 'design_1_i/GameController_0' -INFO: [Project 1-454] Reading design checkpoint 'c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_HDMI_TX_0_0/design_1_HDMI_TX_0_0.dcp' for cell 'design_1_i/HDMI_TX_0' -INFO: [Project 1-454] Reading design checkpoint 'c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_ImgGen_0_0/design_1_ImgGen_0_0.dcp' for cell 'design_1_i/ImgGen_0' -INFO: [Project 1-454] Reading design checkpoint 'c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_RotaryEnc_0_0/design_1_RotaryEnc_0_0.dcp' for cell 'design_1_i/RotaryEnc_0' -INFO: [Project 1-454] Reading design checkpoint 'c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_TickGenerator_0_0/design_1_TickGenerator_0_0.dcp' for cell 'design_1_i/TickGenerator_0' -INFO: [Project 1-454] Reading design checkpoint 'c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_VideoTiming_0_0/design_1_VideoTiming_0_0.dcp' for cell 'design_1_i/VideoTiming_0' -INFO: [Project 1-454] Reading design checkpoint 'c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_angle_encoder_1_0/design_1_angle_encoder_1_0.dcp' for cell 'design_1_i/angle_encoder_1' -INFO: [Project 1-454] Reading design checkpoint 'c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.dcp' for cell 'design_1_i/clk_wiz_0' -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.073 . Memory (MB): peak = 1480.551 ; gain = 0.000 -INFO: [Netlist 29-17] Analyzing 825 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds -WARNING: [Netlist 29-43] Netlist 'design_1_wrapper' is not ideal for floorplanning, since the cellview 'design_1_ImgGen_0_0_ImgGen' defined in file 'design_1_ImgGen_0_0.edf' contains large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. -INFO: [Project 1-479] Netlist was created with Vivado 2025.1 -INFO: [Project 1-570] Preparing netlist for logic optimization -Parsing XDC File [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0_board.xdc] for cell 'design_1_i/clk_wiz_0/inst' -Finished Parsing XDC File [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0_board.xdc] for cell 'design_1_i/clk_wiz_0/inst' -Parsing XDC File [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.xdc] for cell 'design_1_i/clk_wiz_0/inst' -create_clock: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1480.551 ; gain = 0.000 -INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.xdc:54] -INFO: [Timing 38-2] Deriving generated clocks [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.xdc:54] -get_clocks: Time (s): cpu = 00:00:13 ; elapsed = 00:00:10 . Memory (MB): peak = 2248.008 ; gain = 767.457 -Finished Parsing XDC File [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.xdc] for cell 'design_1_i/clk_wiz_0/inst' -Parsing XDC File [C:/Users/lab/Documents/GitHub/SW2/SW2.srcs/constrs_1/new/mainconstraint.xdc] -Finished Parsing XDC File [C:/Users/lab/Documents/GitHub/SW2/SW2.srcs/constrs_1/new/mainconstraint.xdc] -Parsing XDC File [C:/Users/lab/Documents/GitHub/SW2/SW2.srcs/constrs_1/new/sideconstraint.xdc] -Finished Parsing XDC File [C:/Users/lab/Documents/GitHub/SW2/SW2.srcs/constrs_1/new/sideconstraint.xdc] -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 2248.008 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: - A total of 42 instances were transformed. - DSP48E2 => DSP48E2 (DSP_ALU, DSP_A_B_DATA, DSP_C_DATA, DSP_MULTIPLIER, DSP_M_DATA, DSP_OUTPUT, DSP_PREADD, DSP_PREADD_DATA): 38 instances - IBUF => IBUF (IBUFCTRL, INBUF): 3 instances - IBUFDS => IBUFDS (DIFFINBUF, IBUFCTRL): 1 instance - -22 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. -link_design completed successfully -link_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:26 . Memory (MB): peak = 2248.008 ; gain = 1690.215 -Command: opt_design -Attempting to get a license for feature 'Implementation' and/or device 'xczu3eg' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu3eg' -Running DRC as a precondition to command opt_design - -Starting DRC Task -INFO: [DRC 23-27] Running DRC with 6 threads -INFO: [Project 1-461] DRC finished with 0 Errors -INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.923 . Memory (MB): peak = 2272.395 ; gain = 24.387 - -Starting Cache Timing Information Task -INFO: [Timing 38-35] Done setting XDC timing constraints. -Ending Cache Timing Information Task | Checksum: 24df1c074 - -Time (s): cpu = 00:00:04 ; elapsed = 00:00:00.940 . Memory (MB): peak = 2298.988 ; gain = 26.594 - -Starting Logic Optimization Task - -Phase 1 Initialization - -Phase 1.1 Core Generation And Design Setup -Phase 1.1 Core Generation And Design Setup | Checksum: 24df1c074 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 2711.895 ; gain = 0.000 - -Phase 1.2 Setup Constraints And Sort Netlist -Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 24df1c074 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 2711.895 ; gain = 0.000 -Phase 1 Initialization | Checksum: 24df1c074 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 2711.895 ; gain = 0.000 - -Phase 2 Timer Update And Timing Data Collection - -Phase 2.1 Timer Update -Phase 2.1 Timer Update | Checksum: 24df1c074 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.238 . Memory (MB): peak = 2711.895 ; gain = 0.000 - -Phase 2.2 Timing Data Collection -Phase 2.2 Timing Data Collection | Checksum: 24df1c074 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.258 . Memory (MB): peak = 2711.895 ; gain = 0.000 -Phase 2 Timer Update And Timing Data Collection | Checksum: 24df1c074 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.261 . Memory (MB): peak = 2711.895 ; gain = 0.000 - -Phase 3 Retarget -INFO: [Opt 31-1851] Number of loadless carry chains removed were: 0 -INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0 -INFO: [Opt 31-138] Pushed 5 inverter(s) to 60 load pin(s). -INFO: [Opt 31-49] Retargeted 0 cell(s). -Phase 3 Retarget | Checksum: 134a93b52 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.620 . Memory (MB): peak = 2711.895 ; gain = 0.000 -Retarget | Checksum: 134a93b52 -INFO: [Opt 31-389] Phase Retarget created 103 cells and removed 109 cells - -Phase 4 Constant propagation -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Phase 4 Constant propagation | Checksum: 15768403c - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.722 . Memory (MB): peak = 2711.895 ; gain = 0.000 -Constant propagation | Checksum: 15768403c -INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells - -Phase 5 Sweep -INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 -Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 2711.895 ; gain = 0.000 -INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 -Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 2711.895 ; gain = 0.000 -Phase 5 Sweep | Checksum: 1678a9b00 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.926 . Memory (MB): peak = 2711.895 ; gain = 0.000 -Sweep | Checksum: 1678a9b00 -INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells - -Phase 6 BUFG optimization -INFO: [Opt 31-194] Inserted BUFG design_1_i/TickGenerator_0/inst/FrameTick_BUFG_inst to drive 257 load(s) on clock net design_1_i/TickGenerator_0/inst/FrameTick_BUFGCE -INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets -INFO: [Opt 31-1077] Phase BUFG optimization inserted 0 global clock buffer(s) for CLOCK_LOW_FANOUT. -Phase 6 BUFG optimization | Checksum: d6cd27d7 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2711.895 ; gain = 0.000 -BUFG optimization | Checksum: d6cd27d7 -INFO: [Opt 31-662] Phase BUFG optimization created 1 cells of which 1 are BUFGs and removed 0 cells. - -Phase 7 Shift Register Optimization -INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs -Phase 7 Shift Register Optimization | Checksum: d6cd27d7 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2711.895 ; gain = 0.000 -Shift Register Optimization | Checksum: d6cd27d7 -INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells - -Phase 8 Post Processing Netlist -Phase 8 Post Processing Netlist | Checksum: d6cd27d7 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2711.895 ; gain = 0.000 -Post Processing Netlist | Checksum: d6cd27d7 -INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells - -Phase 9 Finalization - -Phase 9.1 Finalizing Design Cores and Updating Shapes -Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 1b5b5f3a9 - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2711.895 ; gain = 0.000 - -Phase 9.2 Verifying Netlist Connectivity - -Starting Connectivity Check Task - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 2711.895 ; gain = 0.000 -Phase 9.2 Verifying Netlist Connectivity | Checksum: 1b5b5f3a9 - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2711.895 ; gain = 0.000 -Phase 9 Finalization | Checksum: 1b5b5f3a9 - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2711.895 ; gain = 0.000 -Opt_design Change Summary -========================= - - -------------------------------------------------------------------------------------------------------------------------- -| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | -------------------------------------------------------------------------------------------------------------------------- -| Retarget | 103 | 109 | 0 | -| Constant propagation | 0 | 0 | 0 | -| Sweep | 0 | 0 | 0 | -| BUFG optimization | 1 | 0 | 0 | -| Shift Register Optimization | 0 | 0 | 0 | -| Post Processing Netlist | 0 | 0 | 0 | -------------------------------------------------------------------------------------------------------------------------- - - -Ending Logic Optimization Task | Checksum: 1b5b5f3a9 - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2711.895 ; gain = 0.000 - -Starting Power Optimization Task -INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. -Ending Power Optimization Task | Checksum: 1b5b5f3a9 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 2711.895 ; gain = 0.000 - -Starting Final Cleanup Task -Ending Final Cleanup Task | Checksum: 1b5b5f3a9 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 2711.895 ; gain = 0.000 - -Starting Netlist Obfuscation Task -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 2711.895 ; gain = 0.000 -Ending Netlist Obfuscation Task | Checksum: 1b5b5f3a9 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 2711.895 ; gain = 0.000 -INFO: [Common 17-83] Releasing license: Implementation -46 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. -opt_design completed successfully -opt_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:07 . Memory (MB): peak = 2711.895 ; gain = 463.887 -INFO: [Vivado 12-24828] Executing command : report_drc -file design_1_wrapper_drc_opted.rpt -pb design_1_wrapper_drc_opted.pb -rpx design_1_wrapper_drc_opted.rpx -Command: report_drc -file design_1_wrapper_drc_opted.rpt -pb design_1_wrapper_drc_opted.pb -rpx design_1_wrapper_drc_opted.rpx -INFO: [IP_Flow 19-1839] IP Catalog is up to date. -INFO: [DRC 23-27] Running DRC with 6 threads -INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/lab/Documents/GitHub/SW2/SW2.runs/impl_1/design_1_wrapper_drc_opted.rpt. -report_drc completed successfully -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [Timing 38-480] Writing timing data to binary archive. -Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 2722.973 ; gain = 0.000 -Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2722.973 ; gain = 0.000 -Writing XDEF routing. -Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.036 . Memory (MB): peak = 2722.973 ; gain = 0.000 -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.077 . Memory (MB): peak = 2723.781 ; gain = 0.809 -Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2723.781 ; gain = 0.000 -Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 2723.781 ; gain = 0.000 -Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.123 . Memory (MB): peak = 2723.781 ; gain = 0.809 -INFO: [Common 17-1381] The checkpoint 'C:/Users/lab/Documents/GitHub/SW2/SW2.runs/impl_1/design_1_wrapper_opt.dcp' has been generated. -Command: place_design -Attempting to get a license for feature 'Implementation' and/or device 'xczu3eg' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu3eg' -INFO: [Common 17-83] Releasing license: Implementation -INFO: [DRC 23-27] Running DRC with 6 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. -Running DRC as a precondition to command place_design -INFO: [DRC 23-27] Running DRC with 6 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. -INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 6 CPUs - -Starting Placer Task - -Phase 1 Placer Initialization - -Phase 1.1 Placer Initialization Netlist Sorting -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 2811.082 ; gain = 0.000 -Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d46e90ed - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 2811.082 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 2811.082 ; gain = 0.000 - -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 14d29efb1 - -Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 3805.191 ; gain = 994.109 - -Phase 1.3 Build Placer Netlist Model -Phase 1.3 Build Placer Netlist Model | Checksum: 198108b5a - -Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 3805.191 ; gain = 994.109 - -Phase 1.4 Constrain Clocks/Macros -Phase 1.4 Constrain Clocks/Macros | Checksum: 198108b5a - -Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 3805.191 ; gain = 994.109 -Phase 1 Placer Initialization | Checksum: 198108b5a - -Time (s): cpu = 00:00:18 ; elapsed = 00:00:14 . Memory (MB): peak = 3805.191 ; gain = 994.109 - -Phase 2 Global Placement - -Phase 2.1 Floorplanning - -Phase 2.1.1 Partition Driven Placement - -Phase 2.1.1.1 PBP: Partition Driven Placement -Phase 2.1.1.1 PBP: Partition Driven Placement | Checksum: 1d3ec0eae - -Time (s): cpu = 00:00:20 ; elapsed = 00:00:15 . Memory (MB): peak = 3805.191 ; gain = 994.109 - -Phase 2.1.1.2 PBP: Clock Region Placement -INFO: [Place 30-3162] Check ILP status : ILP-based clock placer completed successfully. -Phase 2.1.1.2 PBP: Clock Region Placement | Checksum: 2346510b9 - -Time (s): cpu = 00:00:20 ; elapsed = 00:00:15 . Memory (MB): peak = 3805.191 ; gain = 994.109 - -Phase 2.1.1.3 PBP: Compute Congestion -Phase 2.1.1.3 PBP: Compute Congestion | Checksum: 2346510b9 - -Time (s): cpu = 00:00:32 ; elapsed = 00:00:19 . Memory (MB): peak = 3892.230 ; gain = 1081.148 - -Phase 2.1.1.4 PBP: UpdateTiming -Phase 2.1.1.4 PBP: UpdateTiming | Checksum: 25bf084b3 - -Time (s): cpu = 00:00:32 ; elapsed = 00:00:19 . Memory (MB): peak = 3892.230 ; gain = 1081.148 - -Phase 2.1.1.5 PBP: Add part constraints -Phase 2.1.1.5 PBP: Add part constraints | Checksum: 25bf084b3 - -Time (s): cpu = 00:00:32 ; elapsed = 00:00:19 . Memory (MB): peak = 3892.230 ; gain = 1081.148 -Phase 2.1.1 Partition Driven Placement | Checksum: 25bf084b3 - -Time (s): cpu = 00:00:32 ; elapsed = 00:00:19 . Memory (MB): peak = 3892.230 ; gain = 1081.148 -Phase 2.1 Floorplanning | Checksum: 1fe4adc70 - -Time (s): cpu = 00:00:32 ; elapsed = 00:00:19 . Memory (MB): peak = 3892.230 ; gain = 1081.148 - -Phase 2.2 Update Timing before SLR Path Opt -Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1fe4adc70 - -Time (s): cpu = 00:00:32 ; elapsed = 00:00:19 . Memory (MB): peak = 3892.230 ; gain = 1081.148 - -Phase 2.3 Post-Processing in Floorplanning -Phase 2.3 Post-Processing in Floorplanning | Checksum: 1fe4adc70 - -Time (s): cpu = 00:00:32 ; elapsed = 00:00:19 . Memory (MB): peak = 3892.230 ; gain = 1081.148 - -Phase 2.4 Global Place Phase1 -Phase 2.4 Global Place Phase1 | Checksum: 22c2badca - -Time (s): cpu = 00:01:20 ; elapsed = 00:00:31 . Memory (MB): peak = 3951.840 ; gain = 1140.758 - -Phase 2.5 Global Place Phase2 - -Phase 2.5.1 UpdateTiming Before Physical Synthesis -Phase 2.5.1 UpdateTiming Before Physical Synthesis | Checksum: 258367ef3 - -Time (s): cpu = 00:01:22 ; elapsed = 00:00:32 . Memory (MB): peak = 3951.840 ; gain = 1140.758 - -Phase 2.5.2 Physical Synthesis In Placer -INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 107 LUT instances to create LUTNM shape -INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0 -INFO: [Physopt 32-1138] End 1 Pass. Optimized 49 nets or LUTs. Breaked 0 LUT, combined 49 existing LUTs and moved 0 existing LUT -INFO: [Physopt 32-670] No setup violation found. Equivalent Driver Rewiring was not performed. -INFO: [Physopt 32-65] No nets found for high-fanout optimization. -INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. -INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. -INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed. -INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. -INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. -INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed. -INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication -INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 3951.840 ; gain = 0.000 - -Summary of Physical Synthesis Optimizations -============================================ - - ------------------------------------------------------------------------------------------------------------------------------------------------------------ -| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ------------------------------------------------------------------------------------------------------------------------------------------------------------ -| LUT Combining | 0 | 49 | 49 | 0 | 1 | 00:00:00 | -| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| Equivalent Driver Rewiring | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| Total | 0 | 49 | 49 | 0 | 4 | 00:00:00 | ------------------------------------------------------------------------------------------------------------------------------------------------------------ - - -Phase 2.5.2 Physical Synthesis In Placer | Checksum: 1af5f8213 - -Time (s): cpu = 00:01:24 ; elapsed = 00:00:33 . Memory (MB): peak = 3951.840 ; gain = 1140.758 -Phase 2.5 Global Place Phase2 | Checksum: 11685d894 - -Time (s): cpu = 00:01:38 ; elapsed = 00:00:36 . Memory (MB): peak = 3951.914 ; gain = 1140.832 -Phase 2 Global Placement | Checksum: 11685d894 - -Time (s): cpu = 00:01:38 ; elapsed = 00:00:36 . Memory (MB): peak = 3951.914 ; gain = 1140.832 - -Phase 3 Detail Placement - -Phase 3.1 Commit Multi Column Macros -Phase 3.1 Commit Multi Column Macros | Checksum: 15d8d1590 - -Time (s): cpu = 00:01:51 ; elapsed = 00:00:40 . Memory (MB): peak = 3953.625 ; gain = 1142.543 - -Phase 3.2 Commit Most Macros & LUTRAMs -Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 147c52846 - -Time (s): cpu = 00:01:52 ; elapsed = 00:00:40 . Memory (MB): peak = 3953.625 ; gain = 1142.543 - -Phase 3.3 Small Shape DP - -Phase 3.3.1 Small Shape Clustering -Phase 3.3.1 Small Shape Clustering | Checksum: 108962473 - -Time (s): cpu = 00:02:17 ; elapsed = 00:00:47 . Memory (MB): peak = 4012.648 ; gain = 1201.566 - -Phase 3.3.2 Slice Area Swap - -Phase 3.3.2.1 Slice Area Swap Initial -Phase 3.3.2.1 Slice Area Swap Initial | Checksum: aecf74b9 - -Time (s): cpu = 00:02:30 ; elapsed = 00:00:51 . Memory (MB): peak = 4018.648 ; gain = 1207.566 -Phase 3.3.2 Slice Area Swap | Checksum: aecf74b9 - -Time (s): cpu = 00:02:30 ; elapsed = 00:00:51 . Memory (MB): peak = 4018.648 ; gain = 1207.566 -Phase 3.3 Small Shape DP | Checksum: 11b9d9446 - -Time (s): cpu = 00:02:56 ; elapsed = 00:00:58 . Memory (MB): peak = 4024.910 ; gain = 1213.828 - -Phase 3.4 Re-assign LUT pins -Phase 3.4 Re-assign LUT pins | Checksum: 1be97277b - -Time (s): cpu = 00:02:57 ; elapsed = 00:00:59 . Memory (MB): peak = 4024.910 ; gain = 1213.828 - -Phase 3.5 Pipeline Register Optimization -Phase 3.5 Pipeline Register Optimization | Checksum: 12742c475 - -Time (s): cpu = 00:02:57 ; elapsed = 00:00:59 . Memory (MB): peak = 4024.910 ; gain = 1213.828 -Phase 3 Detail Placement | Checksum: 12742c475 - -Time (s): cpu = 00:02:57 ; elapsed = 00:00:59 . Memory (MB): peak = 4024.910 ; gain = 1213.828 - -Phase 4 Post Placement Optimization and Clean-Up - -Phase 4.1 Post Commit Optimization -INFO: [Timing 38-35] Done setting XDC timing constraints. - -Phase 4.1.1 Post Placement Optimization -Post Placement Optimization Initialization | Checksum: 1cf884ade - -Phase 4.1.1.1 BUFG Insertion - -Starting Physical Synthesis Task - -Phase 1 Physical Synthesis Initialization -INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 6 CPUs -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=4.299 | TNS=0.000 | -Phase 1 Physical Synthesis Initialization | Checksum: 1d5195f83 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.102 . Memory (MB): peak = 4024.910 ; gain = 0.000 -INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. -Ending Physical Synthesis Task | Checksum: 2960f3b91 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.145 . Memory (MB): peak = 4024.910 ; gain = 0.000 -Phase 4.1.1.1 BUFG Insertion | Checksum: 1cf884ade - -Time (s): cpu = 00:03:17 ; elapsed = 00:01:04 . Memory (MB): peak = 4024.910 ; gain = 1213.828 - -Phase 4.1.1.2 Post Placement Timing Optimization -INFO: [Place 30-746] Post Placement Timing Summary WNS=4.299. For the most accurate timing information please run report_timing. -Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 26eac437e - -Time (s): cpu = 00:03:17 ; elapsed = 00:01:04 . Memory (MB): peak = 4024.910 ; gain = 1213.828 - -Time (s): cpu = 00:03:17 ; elapsed = 00:01:04 . Memory (MB): peak = 4024.910 ; gain = 1213.828 -Phase 4.1 Post Commit Optimization | Checksum: 26eac437e - -Time (s): cpu = 00:03:18 ; elapsed = 00:01:04 . Memory (MB): peak = 4024.910 ; gain = 1213.828 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 4064.852 ; gain = 0.000 - -Phase 4.2 Post Placement Cleanup -Phase 4.2 Post Placement Cleanup | Checksum: 2aa7c0893 - -Time (s): cpu = 00:03:33 ; elapsed = 00:01:10 . Memory (MB): peak = 4064.852 ; gain = 1253.770 - -Phase 4.3 Placer Reporting - -Phase 4.3.1 Print Estimated Congestion -INFO: [Place 30-612] Post-Placement Estimated Congestion - ________________________________________________________________________ -| | Global Congestion | Long Congestion | Short Congestion | -| Direction | Region Size | Region Size | Region Size | -|___________|___________________|___________________|___________________| -| North| 1x1| 1x1| 1x1| -|___________|___________________|___________________|___________________| -| South| 1x1| 1x1| 1x1| -|___________|___________________|___________________|___________________| -| East| 1x1| 1x1| 2x2| -|___________|___________________|___________________|___________________| -| West| 1x1| 1x1| 1x1| -|___________|___________________|___________________|___________________| - -Phase 4.3.1 Print Estimated Congestion | Checksum: 2aa7c0893 - -Time (s): cpu = 00:03:33 ; elapsed = 00:01:10 . Memory (MB): peak = 4064.852 ; gain = 1253.770 -Phase 4.3 Placer Reporting | Checksum: 2aa7c0893 - -Time (s): cpu = 00:03:33 ; elapsed = 00:01:10 . Memory (MB): peak = 4064.852 ; gain = 1253.770 - -Phase 4.4 Final Placement Cleanup -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 4064.852 ; gain = 0.000 - -Time (s): cpu = 00:03:33 ; elapsed = 00:01:10 . Memory (MB): peak = 4064.852 ; gain = 1253.770 -Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1f5317f71 - -Time (s): cpu = 00:03:33 ; elapsed = 00:01:10 . Memory (MB): peak = 4064.852 ; gain = 1253.770 -Ending Placer Task | Checksum: 13b4d14c8 - -Time (s): cpu = 00:03:33 ; elapsed = 00:01:10 . Memory (MB): peak = 4064.852 ; gain = 1253.770 -83 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. -place_design completed successfully -place_design: Time (s): cpu = 00:03:40 ; elapsed = 00:01:11 . Memory (MB): peak = 4064.852 ; gain = 1341.070 -INFO: [Vivado 12-24838] Running report commands "report_control_sets, report_io, report_utilization" in parallel. -Running report generation with 3 threads. -INFO: [Vivado 12-24828] Executing command : report_control_sets -verbose -file design_1_wrapper_control_sets_placed.rpt -report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 4064.852 ; gain = 0.000 -INFO: [Vivado 12-24828] Executing command : report_utilization -file design_1_wrapper_utilization_placed.rpt -pb design_1_wrapper_utilization_placed.pb -INFO: [Vivado 12-24828] Executing command : report_io -file design_1_wrapper_io_placed.rpt -report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.122 . Memory (MB): peak = 4064.852 ; gain = 0.000 -INFO: [Timing 38-480] Writing timing data to binary archive. -Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 4064.852 ; gain = 0.000 -Wrote PlaceDB: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.815 . Memory (MB): peak = 4064.852 ; gain = 0.000 -Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4064.852 ; gain = 0.000 -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.069 . Memory (MB): peak = 4064.852 ; gain = 0.000 -Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 4064.852 ; gain = 0.000 -Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 4064.852 ; gain = 0.000 -Write Physdb Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.967 . Memory (MB): peak = 4064.852 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/lab/Documents/GitHub/SW2/SW2.runs/impl_1/design_1_wrapper_placed.dcp' has been generated. -Command: phys_opt_design -Attempting to get a license for feature 'Implementation' and/or device 'xczu3eg' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu3eg' - -Starting Initial Update Timing Task - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.808 . Memory (MB): peak = 4064.852 ; gain = 0.000 -INFO: [Vivado_Tcl 4-2279] Estimated Timing Summary | WNS= 4.295 | TNS= 0.000 | -INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. All physical synthesis setup optimizations will be skipped. -INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified. -INFO: [Common 17-83] Releasing license: Implementation -94 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. -phys_opt_design completed successfully -INFO: [Timing 38-480] Writing timing data to binary archive. -Write ShapeDB Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.041 . Memory (MB): peak = 4064.852 ; gain = 0.000 -Wrote PlaceDB: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.910 . Memory (MB): peak = 4064.852 ; gain = 0.000 -Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4064.852 ; gain = 0.000 -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.069 . Memory (MB): peak = 4064.852 ; gain = 0.000 -Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 4064.852 ; gain = 0.000 -Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 4064.852 ; gain = 0.000 -Write Physdb Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 4064.852 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/lab/Documents/GitHub/SW2/SW2.runs/impl_1/design_1_wrapper_physopt.dcp' has been generated. -Command: route_design -Attempting to get a license for feature 'Implementation' and/or device 'xczu3eg' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu3eg' - - -Starting Routing Task -INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 6 CPUs - -Phase 1 Build RT Design -Checksum: PlaceDB: bc23d659 ConstDB: 0 ShapeSum: 23c7019c RouteDB: 5b623cd3 -Nodegraph reading from file. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.729 . Memory (MB): peak = 4064.852 ; gain = 0.000 -Post Restoration Checksum: NetGraph: d4785557 | NumContArr: 92fc82eb | Constraints: e45a4556 | Timing: c2a8fa9d -Phase 1 Build RT Design | Checksum: 30e781835 - -Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 4064.852 ; gain = 0.000 - -Phase 2 Router Initialization - -Phase 2.1 Fix Topology Constraints -Phase 2.1 Fix Topology Constraints | Checksum: 30e781835 - -Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 4064.852 ; gain = 0.000 - -Phase 2.2 Pre Route Cleanup -Phase 2.2 Pre Route Cleanup | Checksum: 30e781835 - -Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 4064.852 ; gain = 0.000 - -Phase 2.3 Global Clock Net Routing - Number of Nodes with overlaps = 0 -Phase 2.3 Global Clock Net Routing | Checksum: 1f9cd8a09 - -Time (s): cpu = 00:00:08 ; elapsed = 00:00:04 . Memory (MB): peak = 4096.516 ; gain = 31.664 - -Phase 2.4 Update Timing -Phase 2.4 Update Timing | Checksum: 219f9736e - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:04 . Memory (MB): peak = 4096.516 ; gain = 31.664 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=4.416 | TNS=0.000 | WHS=-0.197 | THS=-2.104 | - - -Phase 2.5 Soft Constraint Pins - Fast Budgeting -Phase 2.5 Soft Constraint Pins - Fast Budgeting | Checksum: 23f7209fc - -Time (s): cpu = 00:00:12 ; elapsed = 00:00:05 . Memory (MB): peak = 4110.000 ; gain = 45.148 - -Router Utilization Summary - Global Vertical Routing Utilization = 0.000317857 % - Global Horizontal Routing Utilization = 0 % - Routable Net Status* - *Does not include unroutable nets such as driverless and loadless. - Run report_route_status for detailed report. - Number of Failed Nets = 7355 - (Failed Nets is the sum of unrouted and partially routed nets) - Number of Unrouted Nets = 6012 - Number of Partially Routed Nets = 1343 - Number of Node Overlaps = 0 - -Phase 2 Router Initialization | Checksum: 27ce55b57 - -Time (s): cpu = 00:00:13 ; elapsed = 00:00:05 . Memory (MB): peak = 4110.000 ; gain = 45.148 - -Phase 3 Global Routing -Phase 3 Global Routing | Checksum: 27ce55b57 - -Time (s): cpu = 00:00:13 ; elapsed = 00:00:05 . Memory (MB): peak = 4110.000 ; gain = 45.148 - -Phase 4 Initial Routing - -Phase 4.1 Initial Net Routing Pass -Phase 4.1 Initial Net Routing Pass | Checksum: 184807e4d - -Time (s): cpu = 00:00:15 ; elapsed = 00:00:06 . Memory (MB): peak = 4110.000 ; gain = 45.148 -Phase 4 Initial Routing | Checksum: 22bee22de - -Time (s): cpu = 00:00:15 ; elapsed = 00:00:06 . Memory (MB): peak = 4110.000 ; gain = 45.148 - -Phase 5 Rip-up And Reroute - -Phase 5.1 Global Iteration 0 - Number of Nodes with overlaps = 861 - Number of Nodes with overlaps = 13 - Number of Nodes with overlaps = 1 - Number of Nodes with overlaps = 0 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=4.171 | TNS=0.000 | WHS=0.041 | THS=0.000 | - -Phase 5.1 Global Iteration 0 | Checksum: 246954b5a - -Time (s): cpu = 00:00:21 ; elapsed = 00:00:09 . Memory (MB): peak = 4110.000 ; gain = 45.148 - -Phase 5.2 Additional Iteration for Hold -Phase 5.2 Additional Iteration for Hold | Checksum: 2645350d1 - -Time (s): cpu = 00:00:21 ; elapsed = 00:00:09 . Memory (MB): peak = 4110.000 ; gain = 45.148 -Phase 5 Rip-up And Reroute | Checksum: 2645350d1 - -Time (s): cpu = 00:00:21 ; elapsed = 00:00:09 . Memory (MB): peak = 4110.000 ; gain = 45.148 - -Phase 6 Delay and Skew Optimization - -Phase 6.1 Delay CleanUp -Phase 6.1 Delay CleanUp | Checksum: 31fc1c383 - -Time (s): cpu = 00:00:21 ; elapsed = 00:00:09 . Memory (MB): peak = 4110.000 ; gain = 45.148 - -Phase 6.2 Clock Skew Optimization -Phase 6.2 Clock Skew Optimization | Checksum: 31fc1c383 - -Time (s): cpu = 00:00:21 ; elapsed = 00:00:09 . Memory (MB): peak = 4110.000 ; gain = 45.148 -Phase 6 Delay and Skew Optimization | Checksum: 31fc1c383 - -Time (s): cpu = 00:00:21 ; elapsed = 00:00:09 . Memory (MB): peak = 4110.000 ; gain = 45.148 - -Phase 7 Post Hold Fix - -Phase 7.1 Hold Fix Iter -INFO: [Route 35-416] Intermediate Timing Summary | WNS=4.171 | TNS=0.000 | WHS=0.041 | THS=0.000 | - -Phase 7.1 Hold Fix Iter | Checksum: 2ed986476 - -Time (s): cpu = 00:00:23 ; elapsed = 00:00:09 . Memory (MB): peak = 4110.000 ; gain = 45.148 -Phase 7 Post Hold Fix | Checksum: 2ed986476 - -Time (s): cpu = 00:00:23 ; elapsed = 00:00:09 . Memory (MB): peak = 4110.000 ; gain = 45.148 - -Phase 8 Route finalize - -Router Utilization Summary - Global Vertical Routing Utilization = 0.943518 % - Global Horizontal Routing Utilization = 1.17801 % - Routable Net Status* - *Does not include unroutable nets such as driverless and loadless. - Run report_route_status for detailed report. - Number of Failed Nets = 0 - (Failed Nets is the sum of unrouted and partially routed nets) - Number of Unrouted Nets = 0 - Number of Partially Routed Nets = 0 - Number of Node Overlaps = 0 - -Phase 8 Route finalize | Checksum: 2ed986476 - -Time (s): cpu = 00:00:23 ; elapsed = 00:00:09 . Memory (MB): peak = 4110.000 ; gain = 45.148 - -Phase 9 Verifying routed nets - - Verification completed successfully -Phase 9 Verifying routed nets | Checksum: 2ed986476 - -Time (s): cpu = 00:00:23 ; elapsed = 00:00:09 . Memory (MB): peak = 4110.000 ; gain = 45.148 - -Phase 10 Depositing Routes -Phase 10 Depositing Routes | Checksum: 2ed986476 - -Time (s): cpu = 00:00:24 ; elapsed = 00:00:10 . Memory (MB): peak = 4110.000 ; gain = 45.148 - -Phase 11 Resolve XTalk -Phase 11 Resolve XTalk | Checksum: 2ed986476 - -Time (s): cpu = 00:00:24 ; elapsed = 00:00:10 . Memory (MB): peak = 4110.000 ; gain = 45.148 - -Phase 12 Post Process Routing -Phase 12 Post Process Routing | Checksum: 2ed986476 - -Time (s): cpu = 00:00:24 ; elapsed = 00:00:10 . Memory (MB): peak = 4110.000 ; gain = 45.148 - -Phase 13 Post Router Timing -INFO: [Route 35-57] Estimated Timing Summary | WNS=4.171 | TNS=0.000 | WHS=0.041 | THS=0.000 | - -INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. -Phase 13 Post Router Timing | Checksum: 2ed986476 - -Time (s): cpu = 00:00:24 ; elapsed = 00:00:10 . Memory (MB): peak = 4110.000 ; gain = 45.148 -Total Elapsed time in route_design: 10.05 secs - -Phase 14 Post-Route Event Processing -Phase 14 Post-Route Event Processing | Checksum: 100f46cce - -Time (s): cpu = 00:00:25 ; elapsed = 00:00:10 . Memory (MB): peak = 4110.000 ; gain = 45.148 -INFO: [Route 35-16] Router Completed Successfully -Ending Routing Task | Checksum: 100f46cce - -Time (s): cpu = 00:00:25 ; elapsed = 00:00:10 . Memory (MB): peak = 4110.000 ; gain = 45.148 - -Routing Is Done. -INFO: [Common 17-83] Releasing license: Implementation -105 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. -route_design completed successfully -route_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:10 . Memory (MB): peak = 4110.000 ; gain = 45.148 -INFO: [Vivado 12-24828] Executing command : report_drc -file design_1_wrapper_drc_routed.rpt -pb design_1_wrapper_drc_routed.pb -rpx design_1_wrapper_drc_routed.rpx -Command: report_drc -file design_1_wrapper_drc_routed.rpt -pb design_1_wrapper_drc_routed.pb -rpx design_1_wrapper_drc_routed.rpx -INFO: [IP_Flow 19-1839] IP Catalog is up to date. -INFO: [DRC 23-27] Running DRC with 6 threads -INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/lab/Documents/GitHub/SW2/SW2.runs/impl_1/design_1_wrapper_drc_routed.rpt. -report_drc completed successfully -INFO: [Vivado 12-24828] Executing command : report_methodology -file design_1_wrapper_methodology_drc_routed.rpt -pb design_1_wrapper_methodology_drc_routed.pb -rpx design_1_wrapper_methodology_drc_routed.rpx -Command: report_methodology -file design_1_wrapper_methodology_drc_routed.rpt -pb design_1_wrapper_methodology_drc_routed.pb -rpx design_1_wrapper_methodology_drc_routed.rpx -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [DRC 23-133] Running Methodology with 6 threads -INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file C:/Users/lab/Documents/GitHub/SW2/SW2.runs/impl_1/design_1_wrapper_methodology_drc_routed.rpt. -report_methodology completed successfully -INFO: [Vivado 12-24828] Executing command : report_timing_summary -max_paths 10 -routable_nets -report_unconstrained -file design_1_wrapper_timing_summary_routed.rpt -pb design_1_wrapper_timing_summary_routed.pb -rpx design_1_wrapper_timing_summary_routed.rpx -warn_on_violation -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Temperature grade: E, Delay Type: min_max. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 6 CPUs -INFO: [Vivado 12-24838] Running report commands "report_incremental_reuse, report_route_status" in parallel. -Running report generation with 2 threads. -INFO: [Vivado 12-24828] Executing command : report_incremental_reuse -file design_1_wrapper_incremental_reuse_routed.rpt -INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. -INFO: [Vivado 12-24828] Executing command : report_route_status -file design_1_wrapper_route_status.rpt -pb design_1_wrapper_route_status.pb -INFO: [Vivado 12-24828] Executing command : report_power -file design_1_wrapper_power_routed.rpt -pb design_1_wrapper_power_summary_routed.pb -rpx design_1_wrapper_power_routed.rpx -Command: report_power -file design_1_wrapper_power_routed.rpt -pb design_1_wrapper_power_summary_routed.pb -rpx design_1_wrapper_power_routed.rpx -Running Vector-less Activity Propagation... - -Finished Running Vector-less Activity Propagation -122 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. -report_power completed successfully -report_power: Time (s): cpu = 00:00:10 ; elapsed = 00:00:05 . Memory (MB): peak = 4142.480 ; gain = 0.000 -INFO: [Vivado 12-24828] Executing command : report_clock_utilization -file design_1_wrapper_clock_utilization_routed.rpt -INFO: [Vivado 12-24828] Executing command : report_bus_skew -warn_on_violation -file design_1_wrapper_bus_skew_routed.rpt -pb design_1_wrapper_bus_skew_routed.pb -rpx design_1_wrapper_bus_skew_routed.rpx -INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Temperature grade: E, Delay Type: min_max. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 6 CPUs -generate_parallel_reports: Time (s): cpu = 00:00:37 ; elapsed = 00:00:14 . Memory (MB): peak = 4142.480 ; gain = 32.480 -INFO: [Timing 38-480] Writing timing data to binary archive. -Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.040 . Memory (MB): peak = 4142.480 ; gain = 0.000 -Wrote PlaceDB: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.822 . Memory (MB): peak = 4142.480 ; gain = 0.000 -Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4142.480 ; gain = 0.000 -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Wrote RouteStorage: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.165 . Memory (MB): peak = 4142.480 ; gain = 0.000 -Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.026 . Memory (MB): peak = 4142.480 ; gain = 0.000 -Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 4142.480 ; gain = 0.000 -Write Physdb Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 4142.480 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/lab/Documents/GitHub/SW2/SW2.runs/impl_1/design_1_wrapper_routed.dcp' has been generated. -Command: write_bitstream -force design_1_wrapper.bit -Attempting to get a license for feature 'Implementation' and/or device 'xczu3eg' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu3eg' -Running DRC as a precondition to command write_bitstream -INFO: [IP_Flow 19-1839] IP Catalog is up to date. -INFO: [DRC 23-27] Running DRC with 6 threads -INFO: [Vivado 12-3199] DRC finished with 0 Errors -INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. -INFO: [Designutils 20-2272] Running write_bitstream with 6 threads. -Loading data files... -Loading site data... -Loading route data... -Processing options... -Creating bitmap... -Creating bitstream... -Bitstream compression saved 24912672 bits. -Writing bitstream ./design_1_wrapper.bit... -INFO: [Vivado 12-1842] Bitgen Completed Successfully. -INFO: [Common 17-83] Releasing license: Implementation -136 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. -write_bitstream completed successfully -write_bitstream: Time (s): cpu = 00:00:25 ; elapsed = 00:00:14 . Memory (MB): peak = 4143.785 ; gain = 1.305 -INFO: [Common 17-206] Exiting Vivado at Tue Jun 9 14:08:29 2026... diff --git a/SW2.runs/impl_1/design_1_wrapper_2980.backup.vdi b/SW2.runs/impl_1/design_1_wrapper_2980.backup.vdi deleted file mode 100644 index fbfec12..0000000 --- a/SW2.runs/impl_1/design_1_wrapper_2980.backup.vdi +++ /dev/null @@ -1,809 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2025.1 (64-bit) -# SW Build 6140274 on Thu May 22 00:12:29 MDT 2025 -# IP Build 6138677 on Thu May 22 03:10:11 MDT 2025 -# SharedData Build 6139179 on Tue May 20 17:58:58 MDT 2025 -# Start of session at: Tue Jun 9 13:56:43 2026 -# Process ID : 2980 -# Current directory : C:/Users/lab/Documents/GitHub/SW2/SW2.runs/impl_1 -# Command line : vivado.exe -log design_1_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source design_1_wrapper.tcl -notrace -# Log file : C:/Users/lab/Documents/GitHub/SW2/SW2.runs/impl_1/design_1_wrapper.vdi -# Journal file : C:/Users/lab/Documents/GitHub/SW2/SW2.runs/impl_1\vivado.jou -# Running On : Lab016-04 -# Platform : Windows Server 2016 or Windows 10 -# Operating System : 19045 -# Processor Detail : Intel(R) Core(TM) i7-8700 CPU @ 3.20GHz -# CPU Frequency : 3192 MHz -# CPU Physical cores : 6 -# CPU Logical cores : 12 -# Host memory : 17030 MB -# Swap memory : 2550 MB -# Total Virtual : 19580 MB -# Available Virtual : 12572 MB -#----------------------------------------------------------- -Sourcing tcl script 'C:/Users/lab/AppData/Roaming/Xilinx/Vivado/Vivado_init.tcl' -source design_1_wrapper.tcl -notrace -create_project: Time (s): cpu = 00:00:22 ; elapsed = 00:00:05 . Memory (MB): peak = 504.492 ; gain = 223.402 -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Xilinx/IP_Repo'. -WARNING: [IP_Flow 19-3685] Ignored loading user repository 'c:/Xilinx/IP_Repo/OLED_ASCII'. The path is contained within another repository. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/2025.1/Vivado/data/ip'. -Command: link_design -top design_1_wrapper -part xczu3eg-sfvc784-2-e -Design is defaulting to srcset: sources_1 -Design is defaulting to constrset: constrs_1 -INFO: [Device 21-403] Loading part xczu3eg-sfvc784-2-e -INFO: [Project 1-5699] Read binary netlist with skipMacroContent - 1 -INFO: [Project 1-454] Reading design checkpoint 'c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_EnemyController_0_0/design_1_EnemyController_0_0.dcp' for cell 'design_1_i/EnemyController_0' -INFO: [Project 1-454] Reading design checkpoint 'c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_GameController_0_0/design_1_GameController_0_0.dcp' for cell 'design_1_i/GameController_0' -INFO: [Project 1-454] Reading design checkpoint 'c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_HDMI_TX_0_0/design_1_HDMI_TX_0_0.dcp' for cell 'design_1_i/HDMI_TX_0' -INFO: [Project 1-454] Reading design checkpoint 'c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_ImgGen_0_0/design_1_ImgGen_0_0.dcp' for cell 'design_1_i/ImgGen_0' -INFO: [Project 1-454] Reading design checkpoint 'c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_RotaryEnc_0_0/design_1_RotaryEnc_0_0.dcp' for cell 'design_1_i/RotaryEnc_0' -INFO: [Project 1-454] Reading design checkpoint 'c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_TickGenerator_0_0/design_1_TickGenerator_0_0.dcp' for cell 'design_1_i/TickGenerator_0' -INFO: [Project 1-454] Reading design checkpoint 'c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_VideoTiming_0_0/design_1_VideoTiming_0_0.dcp' for cell 'design_1_i/VideoTiming_0' -INFO: [Project 1-454] Reading design checkpoint 'c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_angle_encoder_1_0/design_1_angle_encoder_1_0.dcp' for cell 'design_1_i/angle_encoder_1' -INFO: [Project 1-454] Reading design checkpoint 'c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.dcp' for cell 'design_1_i/clk_wiz_0' -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.074 . Memory (MB): peak = 1481.082 ; gain = 0.000 -INFO: [Netlist 29-17] Analyzing 825 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds -WARNING: [Netlist 29-43] Netlist 'design_1_wrapper' is not ideal for floorplanning, since the cellview 'design_1_ImgGen_0_0_ImgGen' defined in file 'design_1_ImgGen_0_0.edf' contains large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. -INFO: [Project 1-479] Netlist was created with Vivado 2025.1 -INFO: [Project 1-570] Preparing netlist for logic optimization -Parsing XDC File [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0_board.xdc] for cell 'design_1_i/clk_wiz_0/inst' -Finished Parsing XDC File [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0_board.xdc] for cell 'design_1_i/clk_wiz_0/inst' -Parsing XDC File [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.xdc] for cell 'design_1_i/clk_wiz_0/inst' -create_clock: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1481.082 ; gain = 0.000 -INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.xdc:54] -INFO: [Timing 38-2] Deriving generated clocks [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.xdc:54] -get_clocks: Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 2248.500 ; gain = 767.418 -Finished Parsing XDC File [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.xdc] for cell 'design_1_i/clk_wiz_0/inst' -Parsing XDC File [C:/Users/lab/Documents/GitHub/SW2/SW2.srcs/constrs_1/new/mainconstraint.xdc] -Finished Parsing XDC File [C:/Users/lab/Documents/GitHub/SW2/SW2.srcs/constrs_1/new/mainconstraint.xdc] -Parsing XDC File [C:/Users/lab/Documents/GitHub/SW2/SW2.srcs/constrs_1/new/sideconstraint.xdc] -Finished Parsing XDC File [C:/Users/lab/Documents/GitHub/SW2/SW2.srcs/constrs_1/new/sideconstraint.xdc] -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 2248.500 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: - A total of 42 instances were transformed. - DSP48E2 => DSP48E2 (DSP_ALU, DSP_A_B_DATA, DSP_C_DATA, DSP_MULTIPLIER, DSP_M_DATA, DSP_OUTPUT, DSP_PREADD, DSP_PREADD_DATA): 38 instances - IBUF => IBUF (IBUFCTRL, INBUF): 3 instances - IBUFDS => IBUFDS (DIFFINBUF, IBUFCTRL): 1 instance - -22 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. -link_design completed successfully -link_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:26 . Memory (MB): peak = 2248.500 ; gain = 1691.980 -Command: opt_design -Attempting to get a license for feature 'Implementation' and/or device 'xczu3eg' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu3eg' -Running DRC as a precondition to command opt_design - -Starting DRC Task -INFO: [DRC 23-27] Running DRC with 6 threads -INFO: [Project 1-461] DRC finished with 0 Errors -INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.920 . Memory (MB): peak = 2273.035 ; gain = 24.535 - -Starting Cache Timing Information Task -INFO: [Timing 38-35] Done setting XDC timing constraints. -Ending Cache Timing Information Task | Checksum: 24df1c074 - -Time (s): cpu = 00:00:04 ; elapsed = 00:00:00.944 . Memory (MB): peak = 2299.715 ; gain = 26.680 - -Starting Logic Optimization Task - -Phase 1 Initialization - -Phase 1.1 Core Generation And Design Setup -Phase 1.1 Core Generation And Design Setup | Checksum: 24df1c074 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 2719.223 ; gain = 0.000 - -Phase 1.2 Setup Constraints And Sort Netlist -Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 24df1c074 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 2719.223 ; gain = 0.000 -Phase 1 Initialization | Checksum: 24df1c074 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.041 . Memory (MB): peak = 2719.223 ; gain = 0.000 - -Phase 2 Timer Update And Timing Data Collection - -Phase 2.1 Timer Update -Phase 2.1 Timer Update | Checksum: 24df1c074 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.247 . Memory (MB): peak = 2719.223 ; gain = 0.000 - -Phase 2.2 Timing Data Collection -Phase 2.2 Timing Data Collection | Checksum: 24df1c074 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.269 . Memory (MB): peak = 2719.223 ; gain = 0.000 -Phase 2 Timer Update And Timing Data Collection | Checksum: 24df1c074 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.271 . Memory (MB): peak = 2719.223 ; gain = 0.000 - -Phase 3 Retarget -INFO: [Opt 31-1851] Number of loadless carry chains removed were: 0 -INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0 -INFO: [Opt 31-138] Pushed 5 inverter(s) to 60 load pin(s). -INFO: [Opt 31-49] Retargeted 0 cell(s). -Phase 3 Retarget | Checksum: 134a93b52 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.615 . Memory (MB): peak = 2719.223 ; gain = 0.000 -Retarget | Checksum: 134a93b52 -INFO: [Opt 31-389] Phase Retarget created 103 cells and removed 109 cells - -Phase 4 Constant propagation -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Phase 4 Constant propagation | Checksum: 15768403c - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.714 . Memory (MB): peak = 2719.223 ; gain = 0.000 -Constant propagation | Checksum: 15768403c -INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells - -Phase 5 Sweep -INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 -Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 2719.223 ; gain = 0.000 -INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 -Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 2719.223 ; gain = 0.000 -Phase 5 Sweep | Checksum: 1678a9b00 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.918 . Memory (MB): peak = 2719.223 ; gain = 0.000 -Sweep | Checksum: 1678a9b00 -INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells - -Phase 6 BUFG optimization -INFO: [Opt 31-194] Inserted BUFG design_1_i/TickGenerator_0/inst/FrameTick_BUFG_inst to drive 257 load(s) on clock net design_1_i/TickGenerator_0/inst/FrameTick_BUFGCE -INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets -INFO: [Opt 31-1077] Phase BUFG optimization inserted 0 global clock buffer(s) for CLOCK_LOW_FANOUT. -Phase 6 BUFG optimization | Checksum: d6cd27d7 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2719.223 ; gain = 0.000 -BUFG optimization | Checksum: d6cd27d7 -INFO: [Opt 31-662] Phase BUFG optimization created 1 cells of which 1 are BUFGs and removed 0 cells. - -Phase 7 Shift Register Optimization -INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs -Phase 7 Shift Register Optimization | Checksum: d6cd27d7 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2719.223 ; gain = 0.000 -Shift Register Optimization | Checksum: d6cd27d7 -INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells - -Phase 8 Post Processing Netlist -Phase 8 Post Processing Netlist | Checksum: d6cd27d7 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2719.223 ; gain = 0.000 -Post Processing Netlist | Checksum: d6cd27d7 -INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells - -Phase 9 Finalization - -Phase 9.1 Finalizing Design Cores and Updating Shapes -Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 1b5b5f3a9 - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2719.223 ; gain = 0.000 - -Phase 9.2 Verifying Netlist Connectivity - -Starting Connectivity Check Task - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 2719.223 ; gain = 0.000 -Phase 9.2 Verifying Netlist Connectivity | Checksum: 1b5b5f3a9 - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2719.223 ; gain = 0.000 -Phase 9 Finalization | Checksum: 1b5b5f3a9 - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2719.223 ; gain = 0.000 -Opt_design Change Summary -========================= - - -------------------------------------------------------------------------------------------------------------------------- -| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | -------------------------------------------------------------------------------------------------------------------------- -| Retarget | 103 | 109 | 0 | -| Constant propagation | 0 | 0 | 0 | -| Sweep | 0 | 0 | 0 | -| BUFG optimization | 1 | 0 | 0 | -| Shift Register Optimization | 0 | 0 | 0 | -| Post Processing Netlist | 0 | 0 | 0 | -------------------------------------------------------------------------------------------------------------------------- - - -Ending Logic Optimization Task | Checksum: 1b5b5f3a9 - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2719.223 ; gain = 0.000 - -Starting Power Optimization Task -INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. -Ending Power Optimization Task | Checksum: 1b5b5f3a9 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 2719.223 ; gain = 0.000 - -Starting Final Cleanup Task -Ending Final Cleanup Task | Checksum: 1b5b5f3a9 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 2719.223 ; gain = 0.000 - -Starting Netlist Obfuscation Task -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 2719.223 ; gain = 0.000 -Ending Netlist Obfuscation Task | Checksum: 1b5b5f3a9 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 2719.223 ; gain = 0.000 -INFO: [Common 17-83] Releasing license: Implementation -46 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. -opt_design completed successfully -opt_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:07 . Memory (MB): peak = 2719.223 ; gain = 470.723 -INFO: [Vivado 12-24828] Executing command : report_drc -file design_1_wrapper_drc_opted.rpt -pb design_1_wrapper_drc_opted.pb -rpx design_1_wrapper_drc_opted.rpx -Command: report_drc -file design_1_wrapper_drc_opted.rpt -pb design_1_wrapper_drc_opted.pb -rpx design_1_wrapper_drc_opted.rpx -INFO: [IP_Flow 19-1839] IP Catalog is up to date. -INFO: [DRC 23-27] Running DRC with 6 threads -INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/lab/Documents/GitHub/SW2/SW2.runs/impl_1/design_1_wrapper_drc_opted.rpt. -report_drc completed successfully -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [Timing 38-480] Writing timing data to binary archive. -Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 2720.895 ; gain = 0.000 -Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2720.895 ; gain = 0.000 -Writing XDEF routing. -Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 2720.895 ; gain = 0.000 -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.077 . Memory (MB): peak = 2723.629 ; gain = 2.734 -Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2723.629 ; gain = 0.000 -Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 2723.629 ; gain = 0.000 -Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.121 . Memory (MB): peak = 2723.629 ; gain = 2.734 -INFO: [Common 17-1381] The checkpoint 'C:/Users/lab/Documents/GitHub/SW2/SW2.runs/impl_1/design_1_wrapper_opt.dcp' has been generated. -Command: place_design -Attempting to get a license for feature 'Implementation' and/or device 'xczu3eg' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu3eg' -INFO: [Common 17-83] Releasing license: Implementation -INFO: [DRC 23-27] Running DRC with 6 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. -Running DRC as a precondition to command place_design -INFO: [DRC 23-27] Running DRC with 6 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. -INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 6 CPUs - -Starting Placer Task - -Phase 1 Placer Initialization - -Phase 1.1 Placer Initialization Netlist Sorting -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 2824.785 ; gain = 0.000 -Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d46e90ed - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 2824.785 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 2824.785 ; gain = 0.000 - -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 14d29efb1 - -Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 3797.090 ; gain = 972.305 - -Phase 1.3 Build Placer Netlist Model -Phase 1.3 Build Placer Netlist Model | Checksum: 198108b5a - -Time (s): cpu = 00:00:18 ; elapsed = 00:00:14 . Memory (MB): peak = 3797.090 ; gain = 972.305 - -Phase 1.4 Constrain Clocks/Macros -Phase 1.4 Constrain Clocks/Macros | Checksum: 198108b5a - -Time (s): cpu = 00:00:18 ; elapsed = 00:00:14 . Memory (MB): peak = 3797.090 ; gain = 972.305 -Phase 1 Placer Initialization | Checksum: 198108b5a - -Time (s): cpu = 00:00:18 ; elapsed = 00:00:14 . Memory (MB): peak = 3797.090 ; gain = 972.305 - -Phase 2 Global Placement - -Phase 2.1 Floorplanning - -Phase 2.1.1 Partition Driven Placement - -Phase 2.1.1.1 PBP: Partition Driven Placement -Phase 2.1.1.1 PBP: Partition Driven Placement | Checksum: 1d3ec0eae - -Time (s): cpu = 00:00:20 ; elapsed = 00:00:15 . Memory (MB): peak = 3797.090 ; gain = 972.305 - -Phase 2.1.1.2 PBP: Clock Region Placement -INFO: [Place 30-3162] Check ILP status : ILP-based clock placer completed successfully. -Phase 2.1.1.2 PBP: Clock Region Placement | Checksum: 2346510b9 - -Time (s): cpu = 00:00:20 ; elapsed = 00:00:15 . Memory (MB): peak = 3797.090 ; gain = 972.305 - -Phase 2.1.1.3 PBP: Compute Congestion -Phase 2.1.1.3 PBP: Compute Congestion | Checksum: 2346510b9 - -Time (s): cpu = 00:00:31 ; elapsed = 00:00:18 . Memory (MB): peak = 3888.977 ; gain = 1064.191 - -Phase 2.1.1.4 PBP: UpdateTiming -Phase 2.1.1.4 PBP: UpdateTiming | Checksum: 25bf084b3 - -Time (s): cpu = 00:00:32 ; elapsed = 00:00:18 . Memory (MB): peak = 3888.977 ; gain = 1064.191 - -Phase 2.1.1.5 PBP: Add part constraints -Phase 2.1.1.5 PBP: Add part constraints | Checksum: 25bf084b3 - -Time (s): cpu = 00:00:32 ; elapsed = 00:00:18 . Memory (MB): peak = 3888.977 ; gain = 1064.191 -Phase 2.1.1 Partition Driven Placement | Checksum: 25bf084b3 - -Time (s): cpu = 00:00:32 ; elapsed = 00:00:18 . Memory (MB): peak = 3888.977 ; gain = 1064.191 -Phase 2.1 Floorplanning | Checksum: 1fe4adc70 - -Time (s): cpu = 00:00:32 ; elapsed = 00:00:18 . Memory (MB): peak = 3888.977 ; gain = 1064.191 - -Phase 2.2 Update Timing before SLR Path Opt -Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1fe4adc70 - -Time (s): cpu = 00:00:32 ; elapsed = 00:00:18 . Memory (MB): peak = 3888.977 ; gain = 1064.191 - -Phase 2.3 Post-Processing in Floorplanning -Phase 2.3 Post-Processing in Floorplanning | Checksum: 1fe4adc70 - -Time (s): cpu = 00:00:32 ; elapsed = 00:00:18 . Memory (MB): peak = 3888.977 ; gain = 1064.191 - -Phase 2.4 Global Place Phase1 -Phase 2.4 Global Place Phase1 | Checksum: 22c2badca - -Time (s): cpu = 00:01:19 ; elapsed = 00:00:31 . Memory (MB): peak = 3954.016 ; gain = 1129.230 - -Phase 2.5 Global Place Phase2 - -Phase 2.5.1 UpdateTiming Before Physical Synthesis -Phase 2.5.1 UpdateTiming Before Physical Synthesis | Checksum: 258367ef3 - -Time (s): cpu = 00:01:20 ; elapsed = 00:00:31 . Memory (MB): peak = 3954.016 ; gain = 1129.230 - -Phase 2.5.2 Physical Synthesis In Placer -INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 107 LUT instances to create LUTNM shape -INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0 -INFO: [Physopt 32-1138] End 1 Pass. Optimized 49 nets or LUTs. Breaked 0 LUT, combined 49 existing LUTs and moved 0 existing LUT -INFO: [Physopt 32-670] No setup violation found. Equivalent Driver Rewiring was not performed. -INFO: [Physopt 32-65] No nets found for high-fanout optimization. -INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. -INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. -INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed. -INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. -INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. -INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed. -INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication -INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 3954.016 ; gain = 0.000 - -Summary of Physical Synthesis Optimizations -============================================ - - ------------------------------------------------------------------------------------------------------------------------------------------------------------ -| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ------------------------------------------------------------------------------------------------------------------------------------------------------------ -| LUT Combining | 0 | 49 | 49 | 0 | 1 | 00:00:00 | -| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| Equivalent Driver Rewiring | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| Total | 0 | 49 | 49 | 0 | 4 | 00:00:00 | ------------------------------------------------------------------------------------------------------------------------------------------------------------ - - -Phase 2.5.2 Physical Synthesis In Placer | Checksum: 1af5f8213 - -Time (s): cpu = 00:01:22 ; elapsed = 00:00:32 . Memory (MB): peak = 3954.016 ; gain = 1129.230 -Phase 2.5 Global Place Phase2 | Checksum: 11685d894 - -Time (s): cpu = 00:01:37 ; elapsed = 00:00:36 . Memory (MB): peak = 3960.992 ; gain = 1136.207 -Phase 2 Global Placement | Checksum: 11685d894 - -Time (s): cpu = 00:01:37 ; elapsed = 00:00:36 . Memory (MB): peak = 3960.992 ; gain = 1136.207 - -Phase 3 Detail Placement - -Phase 3.1 Commit Multi Column Macros -Phase 3.1 Commit Multi Column Macros | Checksum: 15d8d1590 - -Time (s): cpu = 00:01:50 ; elapsed = 00:00:39 . Memory (MB): peak = 3960.992 ; gain = 1136.207 - -Phase 3.2 Commit Most Macros & LUTRAMs -Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 147c52846 - -Time (s): cpu = 00:01:51 ; elapsed = 00:00:40 . Memory (MB): peak = 3960.992 ; gain = 1136.207 - -Phase 3.3 Small Shape DP - -Phase 3.3.1 Small Shape Clustering -Phase 3.3.1 Small Shape Clustering | Checksum: 108962473 - -Time (s): cpu = 00:02:16 ; elapsed = 00:00:47 . Memory (MB): peak = 3964.539 ; gain = 1139.754 - -Phase 3.3.2 Slice Area Swap - -Phase 3.3.2.1 Slice Area Swap Initial -Phase 3.3.2.1 Slice Area Swap Initial | Checksum: aecf74b9 - -Time (s): cpu = 00:02:29 ; elapsed = 00:00:51 . Memory (MB): peak = 3964.539 ; gain = 1139.754 -Phase 3.3.2 Slice Area Swap | Checksum: aecf74b9 - -Time (s): cpu = 00:02:29 ; elapsed = 00:00:51 . Memory (MB): peak = 3964.539 ; gain = 1139.754 -Phase 3.3 Small Shape DP | Checksum: 11b9d9446 - -Time (s): cpu = 00:02:55 ; elapsed = 00:00:58 . Memory (MB): peak = 3992.586 ; gain = 1167.801 - -Phase 3.4 Re-assign LUT pins -Phase 3.4 Re-assign LUT pins | Checksum: 1be97277b - -Time (s): cpu = 00:02:56 ; elapsed = 00:00:58 . Memory (MB): peak = 3992.586 ; gain = 1167.801 - -Phase 3.5 Pipeline Register Optimization -Phase 3.5 Pipeline Register Optimization | Checksum: 12742c475 - -Time (s): cpu = 00:02:56 ; elapsed = 00:00:58 . Memory (MB): peak = 3992.586 ; gain = 1167.801 -Phase 3 Detail Placement | Checksum: 12742c475 - -Time (s): cpu = 00:02:56 ; elapsed = 00:00:58 . Memory (MB): peak = 3992.586 ; gain = 1167.801 - -Phase 4 Post Placement Optimization and Clean-Up - -Phase 4.1 Post Commit Optimization -INFO: [Timing 38-35] Done setting XDC timing constraints. - -Phase 4.1.1 Post Placement Optimization -Post Placement Optimization Initialization | Checksum: 1cf884ade - -Phase 4.1.1.1 BUFG Insertion - -Starting Physical Synthesis Task - -Phase 1 Physical Synthesis Initialization -INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 6 CPUs -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=4.299 | TNS=0.000 | -Phase 1 Physical Synthesis Initialization | Checksum: 1d5195f83 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.109 . Memory (MB): peak = 3992.586 ; gain = 0.000 -INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. -Ending Physical Synthesis Task | Checksum: 2960f3b91 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.155 . Memory (MB): peak = 3992.586 ; gain = 0.000 -Phase 4.1.1.1 BUFG Insertion | Checksum: 1cf884ade - -Time (s): cpu = 00:03:16 ; elapsed = 00:01:04 . Memory (MB): peak = 3992.586 ; gain = 1167.801 - -Phase 4.1.1.2 Post Placement Timing Optimization -INFO: [Place 30-746] Post Placement Timing Summary WNS=4.299. For the most accurate timing information please run report_timing. -Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 26eac437e - -Time (s): cpu = 00:03:16 ; elapsed = 00:01:04 . Memory (MB): peak = 3992.586 ; gain = 1167.801 - -Time (s): cpu = 00:03:16 ; elapsed = 00:01:04 . Memory (MB): peak = 3992.586 ; gain = 1167.801 -Phase 4.1 Post Commit Optimization | Checksum: 26eac437e - -Time (s): cpu = 00:03:16 ; elapsed = 00:01:04 . Memory (MB): peak = 3992.586 ; gain = 1167.801 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 4046.797 ; gain = 0.000 - -Phase 4.2 Post Placement Cleanup -Phase 4.2 Post Placement Cleanup | Checksum: 2aa7c0893 - -Time (s): cpu = 00:03:31 ; elapsed = 00:01:09 . Memory (MB): peak = 4046.797 ; gain = 1222.012 - -Phase 4.3 Placer Reporting - -Phase 4.3.1 Print Estimated Congestion -INFO: [Place 30-612] Post-Placement Estimated Congestion - ________________________________________________________________________ -| | Global Congestion | Long Congestion | Short Congestion | -| Direction | Region Size | Region Size | Region Size | -|___________|___________________|___________________|___________________| -| North| 1x1| 1x1| 1x1| -|___________|___________________|___________________|___________________| -| South| 1x1| 1x1| 1x1| -|___________|___________________|___________________|___________________| -| East| 1x1| 1x1| 2x2| -|___________|___________________|___________________|___________________| -| West| 1x1| 1x1| 1x1| -|___________|___________________|___________________|___________________| - -Phase 4.3.1 Print Estimated Congestion | Checksum: 2aa7c0893 - -Time (s): cpu = 00:03:31 ; elapsed = 00:01:09 . Memory (MB): peak = 4046.797 ; gain = 1222.012 -Phase 4.3 Placer Reporting | Checksum: 2aa7c0893 - -Time (s): cpu = 00:03:31 ; elapsed = 00:01:09 . Memory (MB): peak = 4046.797 ; gain = 1222.012 - -Phase 4.4 Final Placement Cleanup -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 4046.797 ; gain = 0.000 - -Time (s): cpu = 00:03:31 ; elapsed = 00:01:10 . Memory (MB): peak = 4046.797 ; gain = 1222.012 -Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1f5317f71 - -Time (s): cpu = 00:03:31 ; elapsed = 00:01:10 . Memory (MB): peak = 4046.797 ; gain = 1222.012 -Ending Placer Task | Checksum: 13b4d14c8 - -Time (s): cpu = 00:03:31 ; elapsed = 00:01:10 . Memory (MB): peak = 4046.797 ; gain = 1222.012 -83 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. -place_design completed successfully -place_design: Time (s): cpu = 00:03:38 ; elapsed = 00:01:11 . Memory (MB): peak = 4046.797 ; gain = 1323.168 -INFO: [Vivado 12-24838] Running report commands "report_control_sets, report_io, report_utilization" in parallel. -Running report generation with 3 threads. -INFO: [Vivado 12-24828] Executing command : report_control_sets -verbose -file design_1_wrapper_control_sets_placed.rpt -report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 4046.797 ; gain = 0.000 -INFO: [Vivado 12-24828] Executing command : report_utilization -file design_1_wrapper_utilization_placed.rpt -pb design_1_wrapper_utilization_placed.pb -INFO: [Vivado 12-24828] Executing command : report_io -file design_1_wrapper_io_placed.rpt -report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.120 . Memory (MB): peak = 4046.797 ; gain = 0.000 -INFO: [Timing 38-480] Writing timing data to binary archive. -Write ShapeDB Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.038 . Memory (MB): peak = 4046.797 ; gain = 0.000 -Wrote PlaceDB: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.768 . Memory (MB): peak = 4046.797 ; gain = 0.000 -Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4046.797 ; gain = 0.000 -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.080 . Memory (MB): peak = 4046.797 ; gain = 0.000 -Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.033 . Memory (MB): peak = 4046.797 ; gain = 0.000 -Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.033 . Memory (MB): peak = 4046.797 ; gain = 0.000 -Write Physdb Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.936 . Memory (MB): peak = 4046.797 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/lab/Documents/GitHub/SW2/SW2.runs/impl_1/design_1_wrapper_placed.dcp' has been generated. -Command: phys_opt_design -Attempting to get a license for feature 'Implementation' and/or device 'xczu3eg' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu3eg' - -Starting Initial Update Timing Task - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.816 . Memory (MB): peak = 4046.797 ; gain = 0.000 -INFO: [Vivado_Tcl 4-2279] Estimated Timing Summary | WNS= 4.295 | TNS= 0.000 | -INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. All physical synthesis setup optimizations will be skipped. -INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified. -INFO: [Common 17-83] Releasing license: Implementation -94 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. -phys_opt_design completed successfully -INFO: [Timing 38-480] Writing timing data to binary archive. -Write ShapeDB Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.033 . Memory (MB): peak = 4056.277 ; gain = 5.953 -Wrote PlaceDB: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.802 . Memory (MB): peak = 4057.391 ; gain = 7.047 -Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4057.391 ; gain = 0.000 -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.069 . Memory (MB): peak = 4057.391 ; gain = 0.000 -Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.026 . Memory (MB): peak = 4057.391 ; gain = 0.000 -Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 4057.391 ; gain = 0.000 -Write Physdb Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.941 . Memory (MB): peak = 4057.391 ; gain = 7.047 -INFO: [Common 17-1381] The checkpoint 'C:/Users/lab/Documents/GitHub/SW2/SW2.runs/impl_1/design_1_wrapper_physopt.dcp' has been generated. -Command: route_design -Attempting to get a license for feature 'Implementation' and/or device 'xczu3eg' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu3eg' - - -Starting Routing Task -INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 6 CPUs - -Phase 1 Build RT Design -Checksum: PlaceDB: bc23d659 ConstDB: 0 ShapeSum: 23c7019c RouteDB: 5b623cd3 -Nodegraph reading from file. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.592 . Memory (MB): peak = 4057.391 ; gain = 0.000 -Post Restoration Checksum: NetGraph: d4785557 | NumContArr: 92fc82eb | Constraints: e45a4556 | Timing: c2a8fa9d -Phase 1 Build RT Design | Checksum: 30e781835 - -Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 4057.477 ; gain = 0.086 - -Phase 2 Router Initialization - -Phase 2.1 Fix Topology Constraints -Phase 2.1 Fix Topology Constraints | Checksum: 30e781835 - -Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 4057.477 ; gain = 0.086 - -Phase 2.2 Pre Route Cleanup -Phase 2.2 Pre Route Cleanup | Checksum: 30e781835 - -Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 4057.477 ; gain = 0.086 - -Phase 2.3 Global Clock Net Routing - Number of Nodes with overlaps = 0 -Phase 2.3 Global Clock Net Routing | Checksum: 1f9cd8a09 - -Time (s): cpu = 00:00:08 ; elapsed = 00:00:04 . Memory (MB): peak = 4096.109 ; gain = 38.719 - -Phase 2.4 Update Timing -Phase 2.4 Update Timing | Checksum: 219f9736e - -Time (s): cpu = 00:00:09 ; elapsed = 00:00:04 . Memory (MB): peak = 4096.109 ; gain = 38.719 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=4.416 | TNS=0.000 | WHS=-0.197 | THS=-2.104 | - - -Phase 2.5 Soft Constraint Pins - Fast Budgeting -Phase 2.5 Soft Constraint Pins - Fast Budgeting | Checksum: 23f7209fc - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:05 . Memory (MB): peak = 4109.648 ; gain = 52.258 - -Router Utilization Summary - Global Vertical Routing Utilization = 0.000317857 % - Global Horizontal Routing Utilization = 0 % - Routable Net Status* - *Does not include unroutable nets such as driverless and loadless. - Run report_route_status for detailed report. - Number of Failed Nets = 7355 - (Failed Nets is the sum of unrouted and partially routed nets) - Number of Unrouted Nets = 6012 - Number of Partially Routed Nets = 1343 - Number of Node Overlaps = 0 - -Phase 2 Router Initialization | Checksum: 27ce55b57 - -Time (s): cpu = 00:00:12 ; elapsed = 00:00:05 . Memory (MB): peak = 4109.648 ; gain = 52.258 - -Phase 3 Global Routing -Phase 3 Global Routing | Checksum: 27ce55b57 - -Time (s): cpu = 00:00:12 ; elapsed = 00:00:05 . Memory (MB): peak = 4109.648 ; gain = 52.258 - -Phase 4 Initial Routing - -Phase 4.1 Initial Net Routing Pass -Phase 4.1 Initial Net Routing Pass | Checksum: 184807e4d - -Time (s): cpu = 00:00:15 ; elapsed = 00:00:06 . Memory (MB): peak = 4109.648 ; gain = 52.258 -Phase 4 Initial Routing | Checksum: 22bee22de - -Time (s): cpu = 00:00:15 ; elapsed = 00:00:06 . Memory (MB): peak = 4109.648 ; gain = 52.258 - -Phase 5 Rip-up And Reroute - -Phase 5.1 Global Iteration 0 - Number of Nodes with overlaps = 861 - Number of Nodes with overlaps = 13 - Number of Nodes with overlaps = 1 - Number of Nodes with overlaps = 0 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=4.171 | TNS=0.000 | WHS=0.041 | THS=0.000 | - -Phase 5.1 Global Iteration 0 | Checksum: 246954b5a - -Time (s): cpu = 00:00:21 ; elapsed = 00:00:09 . Memory (MB): peak = 4109.648 ; gain = 52.258 - -Phase 5.2 Additional Iteration for Hold -Phase 5.2 Additional Iteration for Hold | Checksum: 2645350d1 - -Time (s): cpu = 00:00:21 ; elapsed = 00:00:09 . Memory (MB): peak = 4109.648 ; gain = 52.258 -Phase 5 Rip-up And Reroute | Checksum: 2645350d1 - -Time (s): cpu = 00:00:21 ; elapsed = 00:00:09 . Memory (MB): peak = 4109.648 ; gain = 52.258 - -Phase 6 Delay and Skew Optimization - -Phase 6.1 Delay CleanUp -Phase 6.1 Delay CleanUp | Checksum: 31fc1c383 - -Time (s): cpu = 00:00:22 ; elapsed = 00:00:09 . Memory (MB): peak = 4109.648 ; gain = 52.258 - -Phase 6.2 Clock Skew Optimization -Phase 6.2 Clock Skew Optimization | Checksum: 31fc1c383 - -Time (s): cpu = 00:00:22 ; elapsed = 00:00:09 . Memory (MB): peak = 4109.648 ; gain = 52.258 -Phase 6 Delay and Skew Optimization | Checksum: 31fc1c383 - -Time (s): cpu = 00:00:22 ; elapsed = 00:00:09 . Memory (MB): peak = 4109.648 ; gain = 52.258 - -Phase 7 Post Hold Fix - -Phase 7.1 Hold Fix Iter -INFO: [Route 35-416] Intermediate Timing Summary | WNS=4.171 | TNS=0.000 | WHS=0.041 | THS=0.000 | - -Phase 7.1 Hold Fix Iter | Checksum: 2ed986476 - -Time (s): cpu = 00:00:23 ; elapsed = 00:00:09 . Memory (MB): peak = 4109.648 ; gain = 52.258 -Phase 7 Post Hold Fix | Checksum: 2ed986476 - -Time (s): cpu = 00:00:23 ; elapsed = 00:00:09 . Memory (MB): peak = 4109.648 ; gain = 52.258 - -Phase 8 Route finalize - -Router Utilization Summary - Global Vertical Routing Utilization = 0.943518 % - Global Horizontal Routing Utilization = 1.17801 % - Routable Net Status* - *Does not include unroutable nets such as driverless and loadless. - Run report_route_status for detailed report. - Number of Failed Nets = 0 - (Failed Nets is the sum of unrouted and partially routed nets) - Number of Unrouted Nets = 0 - Number of Partially Routed Nets = 0 - Number of Node Overlaps = 0 - -Phase 8 Route finalize | Checksum: 2ed986476 - -Time (s): cpu = 00:00:24 ; elapsed = 00:00:09 . Memory (MB): peak = 4109.648 ; gain = 52.258 - -Phase 9 Verifying routed nets - - Verification completed successfully -Phase 9 Verifying routed nets | Checksum: 2ed986476 - -Time (s): cpu = 00:00:24 ; elapsed = 00:00:09 . Memory (MB): peak = 4109.648 ; gain = 52.258 - -Phase 10 Depositing Routes -Phase 10 Depositing Routes | Checksum: 2ed986476 - -Time (s): cpu = 00:00:24 ; elapsed = 00:00:10 . Memory (MB): peak = 4109.648 ; gain = 52.258 - -Phase 11 Resolve XTalk -Phase 11 Resolve XTalk | Checksum: 2ed986476 - -Time (s): cpu = 00:00:25 ; elapsed = 00:00:10 . Memory (MB): peak = 4109.648 ; gain = 52.258 - -Phase 12 Post Process Routing -Phase 12 Post Process Routing | Checksum: 2ed986476 - -Time (s): cpu = 00:00:25 ; elapsed = 00:00:10 . Memory (MB): peak = 4109.648 ; gain = 52.258 - -Phase 13 Post Router Timing -INFO: [Route 35-57] Estimated Timing Summary | WNS=4.171 | TNS=0.000 | WHS=0.041 | THS=0.000 | - -INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. -Phase 13 Post Router Timing | Checksum: 2ed986476 - -Time (s): cpu = 00:00:25 ; elapsed = 00:00:10 . Memory (MB): peak = 4109.648 ; gain = 52.258 -Total Elapsed time in route_design: 10.073 secs - -Phase 14 Post-Route Event Processing -Phase 14 Post-Route Event Processing | Checksum: 100f46cce - -Time (s): cpu = 00:00:25 ; elapsed = 00:00:10 . Memory (MB): peak = 4109.648 ; gain = 52.258 -INFO: [Route 35-16] Router Completed Successfully -Ending Routing Task | Checksum: 100f46cce - -Time (s): cpu = 00:00:25 ; elapsed = 00:00:10 . Memory (MB): peak = 4109.648 ; gain = 52.258 - -Routing Is Done. -INFO: [Common 17-83] Releasing license: Implementation -105 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. -route_design completed successfully -route_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:10 . Memory (MB): peak = 4109.648 ; gain = 52.258 -INFO: [Vivado 12-24828] Executing command : report_drc -file design_1_wrapper_drc_routed.rpt -pb design_1_wrapper_drc_routed.pb -rpx design_1_wrapper_drc_routed.rpx -Command: report_drc -file design_1_wrapper_drc_routed.rpt -pb design_1_wrapper_drc_routed.pb -rpx design_1_wrapper_drc_routed.rpx -INFO: [IP_Flow 19-1839] IP Catalog is up to date. -INFO: [DRC 23-27] Running DRC with 6 threads -INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/lab/Documents/GitHub/SW2/SW2.runs/impl_1/design_1_wrapper_drc_routed.rpt. -report_drc completed successfully -INFO: [Vivado 12-24828] Executing command : report_methodology -file design_1_wrapper_methodology_drc_routed.rpt -pb design_1_wrapper_methodology_drc_routed.pb -rpx design_1_wrapper_methodology_drc_routed.rpx -Command: report_methodology -file design_1_wrapper_methodology_drc_routed.rpt -pb design_1_wrapper_methodology_drc_routed.pb -rpx design_1_wrapper_methodology_drc_routed.rpx -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [DRC 23-133] Running Methodology with 6 threads -INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file C:/Users/lab/Documents/GitHub/SW2/SW2.runs/impl_1/design_1_wrapper_methodology_drc_routed.rpt. -report_methodology completed successfully -INFO: [Vivado 12-24828] Executing command : report_timing_summary -max_paths 10 -routable_nets -report_unconstrained -file design_1_wrapper_timing_summary_routed.rpt -pb design_1_wrapper_timing_summary_routed.pb -rpx design_1_wrapper_timing_summary_routed.rpx -warn_on_violation -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Temperature grade: E, Delay Type: min_max. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 6 CPUs -INFO: [Vivado 12-24838] Running report commands "report_incremental_reuse, report_route_status" in parallel. -Running report generation with 2 threads. -INFO: [Vivado 12-24828] Executing command : report_incremental_reuse -file design_1_wrapper_incremental_reuse_routed.rpt -INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. -INFO: [Vivado 12-24828] Executing command : report_route_status -file design_1_wrapper_route_status.rpt -pb design_1_wrapper_route_status.pb -INFO: [Vivado 12-24828] Executing command : report_power -file design_1_wrapper_power_routed.rpt -pb design_1_wrapper_power_summary_routed.pb -rpx design_1_wrapper_power_routed.rpx -Command: report_power -file design_1_wrapper_power_routed.rpt -pb design_1_wrapper_power_summary_routed.pb -rpx design_1_wrapper_power_routed.rpx -Running Vector-less Activity Propagation... - -Finished Running Vector-less Activity Propagation -122 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. -report_power completed successfully -report_power: Time (s): cpu = 00:00:09 ; elapsed = 00:00:05 . Memory (MB): peak = 4143.941 ; gain = 0.000 -INFO: [Vivado 12-24828] Executing command : report_clock_utilization -file design_1_wrapper_clock_utilization_routed.rpt -INFO: [Vivado 12-24828] Executing command : report_bus_skew -warn_on_violation -file design_1_wrapper_bus_skew_routed.rpt -pb design_1_wrapper_bus_skew_routed.pb -rpx design_1_wrapper_bus_skew_routed.rpx -INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Temperature grade: E, Delay Type: min_max. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 6 CPUs -generate_parallel_reports: Time (s): cpu = 00:00:35 ; elapsed = 00:00:13 . Memory (MB): peak = 4143.941 ; gain = 34.293 -INFO: [Timing 38-480] Writing timing data to binary archive. -Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.040 . Memory (MB): peak = 4143.941 ; gain = 0.000 -Wrote PlaceDB: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.801 . Memory (MB): peak = 4143.941 ; gain = 0.000 -Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4143.941 ; gain = 0.000 -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.177 . Memory (MB): peak = 4143.941 ; gain = 0.000 -Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 4143.941 ; gain = 0.000 -Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 4143.941 ; gain = 0.000 -Write Physdb Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 4143.941 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/lab/Documents/GitHub/SW2/SW2.runs/impl_1/design_1_wrapper_routed.dcp' has been generated. -INFO: [Common 17-206] Exiting Vivado at Tue Jun 9 13:59:09 2026... diff --git a/SW2.runs/impl_1/design_1_wrapper_bus_skew_routed.pb b/SW2.runs/impl_1/design_1_wrapper_bus_skew_routed.pb deleted file mode 100644 index 3390588..0000000 Binary files a/SW2.runs/impl_1/design_1_wrapper_bus_skew_routed.pb and /dev/null differ diff --git a/SW2.runs/impl_1/design_1_wrapper_bus_skew_routed.rpt b/SW2.runs/impl_1/design_1_wrapper_bus_skew_routed.rpt deleted file mode 100644 index 712db8c..0000000 --- a/SW2.runs/impl_1/design_1_wrapper_bus_skew_routed.rpt +++ /dev/null @@ -1,17 +0,0 @@ -Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2025.1 (win64) Build 6140274 Thu May 22 00:12:29 MDT 2025 -| Date : Tue Jun 9 14:08:10 2026 -| Host : Lab016-04 running 64-bit major release (build 9200) -| Command : report_bus_skew -warn_on_violation -file design_1_wrapper_bus_skew_routed.rpt -pb design_1_wrapper_bus_skew_routed.pb -rpx design_1_wrapper_bus_skew_routed.rpx -| Design : design_1_wrapper -| Device : xczu3eg-sfvc784 -| Speed File : -2 PRODUCTION 1.30 05-15-2022 -| Design State : Routed -| Temperature Grade : E --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - -Bus Skew Report - -No bus skew constraints - diff --git a/SW2.runs/impl_1/design_1_wrapper_bus_skew_routed.rpx b/SW2.runs/impl_1/design_1_wrapper_bus_skew_routed.rpx deleted file mode 100644 index 9758e18..0000000 Binary files a/SW2.runs/impl_1/design_1_wrapper_bus_skew_routed.rpx and /dev/null differ diff --git a/SW2.runs/impl_1/design_1_wrapper_clock_utilization_routed.rpt b/SW2.runs/impl_1/design_1_wrapper_clock_utilization_routed.rpt deleted file mode 100644 index 9e37d0b..0000000 --- a/SW2.runs/impl_1/design_1_wrapper_clock_utilization_routed.rpt +++ /dev/null @@ -1,238 +0,0 @@ -Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2025.1 (win64) Build 6140274 Thu May 22 00:12:29 MDT 2025 -| Date : Tue Jun 9 14:08:10 2026 -| Host : Lab016-04 running 64-bit major release (build 9200) -| Command : report_clock_utilization -file design_1_wrapper_clock_utilization_routed.rpt -| Design : design_1_wrapper -| Device : xczu3eg-sfvc784 -| Speed File : -2 PRODUCTION 1.30 05-15-2022 -| Temperature Grade : E -| Design State : Routed --------------------------------------------------------------------------------------------------------------------------------------------------- - -Clock Utilization Report - -Table of Contents ------------------ -1. Clock Primitive Utilization -2. Global Clock Resources -3. Global Clock Source Details -4. Clock Regions : Clock Primitives -5. Clock Regions : Load Primitives -6. Clock Regions : Global Clock Summary -7. Clock Regions : Routing Resource Utilization -8. Device Cell Placement Summary for Global Clock g0 -9. Device Cell Placement Summary for Global Clock g1 -10. Device Cell Placement Summary for Global Clock g2 -11. Clock Region Cell Placement per Global Clock: Region X0Y0 -12. Clock Region Cell Placement per Global Clock: Region X1Y0 - -1. Clock Primitive Utilization ------------------------------- - -+------------+------+-----------+-----+--------------+--------+ -| Type | Used | Available | LOC | Clock Region | Pblock | -+------------+------+-----------+-----+--------------+--------+ -| BUFGCE | 3 | 88 | 0 | 0 | 0 | -| BUFGCE_DIV | 0 | 12 | 0 | 0 | 0 | -| BUFGCTRL | 0 | 24 | 0 | 0 | 0 | -| BUFG_PS | 0 | 72 | 0 | 0 | 0 | -| MMCM | 1 | 3 | 0 | 0 | 0 | -| PLL | 0 | 6 | 0 | 0 | 0 | -+------------+------+-----------+-----+--------------+--------+ - - -2. Global Clock Resources -------------------------- - -+-----------+-----------+-----------------+------------+--------------+--------------+------+-------------------+------------------+-------------------+-------------+-----------------+--------------+-----------------------------+-------------------------------------------------------+--------------------------------------------------+ -| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Root | Clock Delay Group | Clock Low Fanout | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | -+-----------+-----------+-----------------+------------+--------------+--------------+------+-------------------+------------------+-------------------+-------------+-----------------+--------------+-----------------------------+-------------------------------------------------------+--------------------------------------------------+ -| g0 | src0 | BUFGCE/O | None | BUFGCE_X0Y1 | X1Y0 | X1Y0 | | | 2 | 257 | 0 | | | design_1_i/TickGenerator_0/inst/FrameTick_BUFG_inst/O | design_1_i/TickGenerator_0/inst/FrameTick_BUFGCE | -| g1 | src1 | BUFGCE/O | None | BUFGCE_X0Y68 | X1Y2 | X0Y0 | | | 2 | 99 | 0 | 40.000 | clk25_design_1_clk_wiz_0_0 | design_1_i/clk_wiz_0/inst/clkout1_buf/O | design_1_i/clk_wiz_0/inst/clk25 | -| g2 | src2 | BUFGCE/O | None | BUFGCE_X0Y54 | X1Y2 | X1Y0 | | | 1 | 53 | 0 | 8.000 | clk125_design_1_clk_wiz_0_0 | design_1_i/clk_wiz_0/inst/clkout2_buf/O | design_1_i/clk_wiz_0/inst/clk125 | -+-----------+-----------+-----------------+------------+--------------+--------------+------+-------------------+------------------+-------------------+-------------+-----------------+--------------+-----------------------------+-------------------------------------------------------+--------------------------------------------------+ -* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered -** Non-Clock Loads column represents cell count of non-clock pin loads - - -3. Global Clock Source Details ------------------------------- - -+-----------+-----------+--------------------+------------+--------------+--------------+-------------+-----------------+---------------------+-----------------------------+---------------------------------------------------+-------------------------------------------------------+ -| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | -+-----------+-----------+--------------------+------------+--------------+--------------+-------------+-----------------+---------------------+-----------------------------+---------------------------------------------------+-------------------------------------------------------+ -| src0 | g0 | FDCE/Q | None | SLICE_X48Y39 | X1Y0 | 1 | 0 | | | design_1_i/TickGenerator_0/inst/FrameTick_reg/Q | design_1_i/TickGenerator_0/inst/FrameTick | -| src1 | g1 | MMCME4_ADV/CLKOUT0 | None | MMCM_X0Y2 | X1Y2 | 1 | 0 | 40.000 | clk25_design_1_clk_wiz_0_0 | design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 | design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 | -| src2 | g2 | MMCME4_ADV/CLKOUT1 | None | MMCM_X0Y2 | X1Y2 | 1 | 0 | 8.000 | clk125_design_1_clk_wiz_0_0 | design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 | design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 | -+-----------+-----------+--------------------+------------+--------------+--------------+-------------+-----------------+---------------------+-----------------------------+---------------------------------------------------+-------------------------------------------------------+ -* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered -** Non-Clock Loads column represents cell count of non-clock pin loads - - -4. Clock Regions : Clock Primitives ------------------------------------ - -+-------------------+---------------+---------------+---------------+---------------+---------------+---------------+---------------+---------------+ -| | Global Clock | BUFGCE | BUFGCE_DIV | BUFGCTRL | BUFG_GT | BUFG_PS | MMCM | PLL | -+-------------------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+ -| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | -+-------------------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+ -| X0Y0 | 2 | 24 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 24 | 0 | 0 | 0 | 0 | -| X1Y0 | 3 | 24 | 1 | 28 | 0 | 4 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 2 | -| X0Y1 | 0 | 24 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 24 | 0 | 0 | 0 | 0 | -| X1Y1 | 0 | 24 | 0 | 24 | 0 | 4 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 2 | -| X0Y2 | 0 | 24 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 24 | 0 | 0 | 0 | 0 | -| X1Y2 | 0 | 24 | 2 | 24 | 0 | 4 | 0 | 8 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 2 | -+-------------------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+ -* Global Clock column represents track count; while other columns represents cell counts - - -5. Clock Regions : Load Primitives ----------------------------------- - -+-------------------+------------------+------------------+------------------+------------------+------------------+------------------+------------------+ -| | Global Clock | FF | LUTRAM | Block RAM (18K) | DSP | GT | HARD IP | -+-------------------+--------+---------+--------+---------+--------+---------+--------+---------+--------+---------+--------+---------+--------+---------+ -| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | -+-------------------+--------+---------+--------+---------+--------+---------+--------+---------+--------+---------+--------+---------+--------+---------+ -| X0Y0 | 2 | 24 | 191 | 27840 | 0 | 4800 | 0 | 72 | 0 | 72 | 0 | 0 | 0 | 0 | -| X1Y0 | 3 | 24 | 210 | 19200 | 0 | 4800 | 0 | 72 | 0 | 48 | 0 | 0 | 0 | 0 | -| X0Y1 | 0 | 24 | 0 | 27840 | 0 | 4800 | 0 | 72 | 0 | 72 | 0 | 0 | 0 | 0 | -| X1Y1 | 0 | 24 | 0 | 19200 | 0 | 4800 | 0 | 72 | 0 | 48 | 0 | 0 | 0 | 0 | -| X0Y2 | 0 | 24 | 0 | 27840 | 0 | 4800 | 0 | 72 | 0 | 72 | 0 | 0 | 0 | 0 | -| X1Y2 | 0 | 24 | 0 | 19200 | 0 | 4800 | 0 | 72 | 0 | 48 | 0 | 0 | 0 | 0 | -+-------------------+--------+---------+--------+---------+--------+---------+--------+---------+--------+---------+--------+---------+--------+---------+ -* Global Clock column represents track count; while other columns represents cell counts - - -6. Clock Regions : Global Clock Summary ---------------------------------------- - -All Modules -+----+----+----+ -| | X0 | X1 | -+----+----+----+ -| Y2 | 0 | 0 | -| Y1 | 0 | 0 | -| Y0 | 2 | 3 | -+----+----+----+ - - -7. Clock Regions : Routing Resource Utilization ------------------------------------------------ - -All Modules -+-------------------+----------------------+----------------------+----------------------+----------------------+ -| | HROUTES | HDISTRS | VROUTES | VDISTRS | -+-------------------+------+-------+-------+------+-------+-------+------+-------+-------+------+-------+-------+ -| Clock Region Name | Used | Avail | Util% | Used | Avail | Util% | Used | Avail | Util% | Used | Avail | Util% | -+-------------------+------+-------+-------+------+-------+-------+------+-------+-------+------+-------+-------+ -| X0Y0 | 0 | 24 | 0.00 | 2 | 24 | 8.33 | 1 | 24 | 4.17 | 1 | 24 | 4.17 | -| X1Y0 | 0 | 24 | 0.00 | 3 | 24 | 12.50 | 1 | 24 | 4.17 | 1 | 24 | 4.17 | -| X0Y1 | 0 | 24 | 0.00 | 0 | 24 | 0.00 | 1 | 24 | 4.17 | 0 | 24 | 0.00 | -| X1Y1 | 0 | 24 | 0.00 | 0 | 24 | 0.00 | 1 | 24 | 4.17 | 0 | 24 | 0.00 | -| X0Y2 | 1 | 24 | 4.17 | 0 | 24 | 0.00 | 1 | 24 | 4.17 | 0 | 24 | 0.00 | -| X1Y2 | 4 | 24 | 16.67 | 0 | 24 | 0.00 | 1 | 24 | 4.17 | 0 | 24 | 0.00 | -+-------------------+------+-------+-------+------+-------+-------+------+-------+-------+------+-------+-------+ - - -8. Device Cell Placement Summary for Global Clock g0 ----------------------------------------------------- - -+-----------+-----------------+-------------------+-------+-------------+---------------+----------+-------------+----------+----------------+----------+--------------------------------------------------+ -| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | -+-----------+-----------------+-------------------+-------+-------------+---------------+----------+-------------+----------+----------------+----------+--------------------------------------------------+ -| g0 | BUFGCE/O | X1Y0 | | | | X1Y0 | 257 | 0 | 0 | 0 | design_1_i/TickGenerator_0/inst/FrameTick_BUFGCE | -+-----------+-----------------+-------------------+-------+-------------+---------------+----------+-------------+----------+----------------+----------+--------------------------------------------------+ -* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources -** IO Loads column represents load cell count of IO types -*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) -**** GT Loads column represents load cell count of GT types - - -+----+------+------------+-----------------------+ -| | X0 | X1 | HORIZONTAL PROG DELAY | -+----+------+------------+-----------------------+ -| Y2 | 0 | 0 | - | -| Y1 | 0 | 0 | - | -| Y0 | 178 | (R) (D) 79 | 0 | -+----+------+------------+-----------------------+ - - -9. Device Cell Placement Summary for Global Clock g1 ----------------------------------------------------- - -+-----------+-----------------+-------------------+----------------------------+-------------+----------------+----------+-------------+----------+----------------+----------+---------------------------------+ -| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | -+-----------+-----------------+-------------------+----------------------------+-------------+----------------+----------+-------------+----------+----------------+----------+---------------------------------+ -| g1 | BUFGCE/O | X1Y2 | clk25_design_1_clk_wiz_0_0 | 40.000 | {0.000 20.000} | X0Y0 | 99 | 0 | 0 | 0 | design_1_i/clk_wiz_0/inst/clk25 | -+-----------+-----------------+-------------------+----------------------------+-------------+----------------+----------+-------------+----------+----------------+----------+---------------------------------+ -* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources -** IO Loads column represents load cell count of IO types -*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) -**** GT Loads column represents load cell count of GT types - - -+----+--------+--------+-----------------------+ -| | X0 | X1 | HORIZONTAL PROG DELAY | -+----+--------+--------+-----------------------+ -| Y2 | 0 | (D) 0 | - | -| Y1 | 0 | 0 | - | -| Y0 | (R) 13 | 86 | 0 | -+----+--------+--------+-----------------------+ - - -10. Device Cell Placement Summary for Global Clock g2 ------------------------------------------------------ - -+-----------+-----------------+-------------------+-----------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+----------------------------------+ -| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | -+-----------+-----------------+-------------------+-----------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+----------------------------------+ -| g2 | BUFGCE/O | X1Y2 | clk125_design_1_clk_wiz_0_0 | 8.000 | {0.000 4.000} | X1Y0 | 45 | 8 | 0 | 0 | design_1_i/clk_wiz_0/inst/clk125 | -+-----------+-----------------+-------------------+-----------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+----------------------------------+ -* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources -** IO Loads column represents load cell count of IO types -*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) -**** GT Loads column represents load cell count of GT types - - -+----+----+--------+-----------------------+ -| | X0 | X1 | HORIZONTAL PROG DELAY | -+----+----+--------+-----------------------+ -| Y2 | 0 | (D) 0 | - | -| Y1 | 0 | 0 | - | -| Y0 | 0 | (R) 53 | 0 | -+----+----+--------+-----------------------+ - - -11. Clock Region Cell Placement per Global Clock: Region X0Y0 -------------------------------------------------------------- - -+-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+--------------------------------------------------+ -| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | -+-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+--------------------------------------------------+ -| g0 | 1 | BUFGCE/O | None | 178 | 0 | 178 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | design_1_i/TickGenerator_0/inst/FrameTick_BUFGCE | -| g1 | 20 | BUFGCE/O | None | 13 | 0 | 13 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | design_1_i/clk_wiz_0/inst/clk25 | -+-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+--------------------------------------------------+ -* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered -** Non-Clock Loads column represents cell count of non-clock pin loads -*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts - - -12. Clock Region Cell Placement per Global Clock: Region X1Y0 -------------------------------------------------------------- - -+-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+--------------------------------------------------+ -| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | -+-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+--------------------------------------------------+ -| g0 | 1 | BUFGCE/O | None | 79 | 0 | 79 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | design_1_i/TickGenerator_0/inst/FrameTick_BUFGCE | -| g1 | 20 | BUFGCE/O | None | 86 | 0 | 86 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | design_1_i/clk_wiz_0/inst/clk25 | -| g2 | 6 | BUFGCE/O | None | 53 | 0 | 45 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | design_1_i/clk_wiz_0/inst/clk125 | -+-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+--------------------------------------------------+ -* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered -** Non-Clock Loads column represents cell count of non-clock pin loads -*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts - - diff --git a/SW2.runs/impl_1/design_1_wrapper_control_sets_placed.rpt b/SW2.runs/impl_1/design_1_wrapper_control_sets_placed.rpt deleted file mode 100644 index 59d58ed..0000000 --- a/SW2.runs/impl_1/design_1_wrapper_control_sets_placed.rpt +++ /dev/null @@ -1,117 +0,0 @@ -Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. ---------------------------------------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2025.1 (win64) Build 6140274 Thu May 22 00:12:29 MDT 2025 -| Date : Tue Jun 9 14:07:41 2026 -| Host : Lab016-04 running 64-bit major release (build 9200) -| Command : report_control_sets -verbose -file design_1_wrapper_control_sets_placed.rpt -| Design : design_1_wrapper -| Device : xczu3eg ---------------------------------------------------------------------------------------------------------------------------------------------- - -Control Set Information - -Table of Contents ------------------ -1. Summary -2. Histogram -3. Flip-Flop Distribution -4. Detailed Control Set Information - -1. Summary ----------- - -+----------------------------------------------------------+-------+ -| Status | Count | -+----------------------------------------------------------+-------+ -| Total control sets | 39 | -| Minimum number of control sets | 39 | -| Addition due to synthesis replication | 0 | -| Addition due to physical synthesis replication | 0 | -| Unused register locations in slices containing registers | 91 | -+----------------------------------------------------------+-------+ -* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers -** Run report_qor_suggestions for automated merging and remapping suggestions - - -2. Histogram ------------- - -+--------------------+-------+ -| Fanout | Count | -+--------------------+-------+ -| Total control sets | 39 | -| >= 0 to < 4 | 6 | -| >= 4 to < 6 | 1 | -| >= 6 to < 8 | 0 | -| >= 8 to < 10 | 24 | -| >= 10 to < 12 | 2 | -| >= 12 to < 14 | 1 | -| >= 14 to < 16 | 0 | -| >= 16 | 5 | -+--------------------+-------+ -* Control sets can be remapped at either synth_design or opt_design - - -3. Flip-Flop Distribution -------------------------- - -+--------------+-----------------------+------------------------+-----------------+--------------+ -| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | -+--------------+-----------------------+------------------------+-----------------+--------------+ -| No | No | No | 38 | 19 | -| No | No | Yes | 44 | 28 | -| No | Yes | No | 67 | 27 | -| Yes | No | No | 2 | 1 | -| Yes | No | Yes | 236 | 85 | -| Yes | Yes | No | 14 | 5 | -+--------------+-----------------------+------------------------+-----------------+--------------+ - - -4. Detailed Control Set Information ------------------------------------ - -+---------------------------------------------------+-------------------------------------------------------+------------------------------------------------------+------------------+----------------+--------------+ -| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | Bels / Slice | -+---------------------------------------------------+-------------------------------------------------------+------------------------------------------------------+------------------+----------------+--------------+ -| design_1_i/clk_wiz_0/inst/clk25 | design_1_i/angle_encoder_1/inst/rot_l_delayed_i_1_n_0 | | 1 | 2 | 2.00 | -| design_1_i/clk_wiz_0/inst/clk25 | design_1_i/EnemyController_0/inst/HIT | PL_USER_PB0_IBUF_inst/O | 1 | 3 | 3.00 | -| design_1_i/clk_wiz_0/inst/clk125 | | design_1_i/HDMI_TX_0/U0/i_wrap/cntMod5[2]_i_1__0_n_0 | 1 | 3 | 3.00 | -| design_1_i/clk_wiz_0/inst/clk125 | | design_1_i/HDMI_TX_0/U0/i_wrap/cntMod5[2]_i_1__1_n_0 | 1 | 3 | 3.00 | -| design_1_i/clk_wiz_0/inst/clk125 | | design_1_i/HDMI_TX_0/U0/i_wrap/cntMod5[2]_i_1_n_0 | 1 | 3 | 3.00 | -| design_1_i/clk_wiz_0/inst/clk125 | | design_1_i/HDMI_TX_0/U0/i_wrap/cntMod5[2]_i_1__2_n_0 | 1 | 3 | 3.00 | -| design_1_i/clk_wiz_0/inst/clk25 | design_1_i/angle_encoder_1/inst/angle_reg[4]_i_2_n_0 | design_1_i/angle_encoder_1/inst/angle_reg[4]_i_1_n_0 | 2 | 4 | 2.00 | -| design_1_i/TickGenerator_0/inst/FrameTick_BUFGCE | design_1_i/EnemyController_0/inst/enemies[23][R] | PL_USER_PB0_IBUF_inst/O | 3 | 9 | 3.00 | -| design_1_i/TickGenerator_0/inst/FrameTick_BUFGCE | design_1_i/EnemyController_0/inst/enemies[2][R] | PL_USER_PB0_IBUF_inst/O | 4 | 9 | 2.25 | -| design_1_i/TickGenerator_0/inst/FrameTick_BUFGCE | design_1_i/EnemyController_0/inst/enemies[22][R] | PL_USER_PB0_IBUF_inst/O | 3 | 9 | 3.00 | -| design_1_i/TickGenerator_0/inst/FrameTick_BUFGCE | design_1_i/EnemyController_0/inst/enemies[4][R] | PL_USER_PB0_IBUF_inst/O | 3 | 9 | 3.00 | -| design_1_i/TickGenerator_0/inst/FrameTick_BUFGCE | design_1_i/EnemyController_0/inst/enemies[5][R] | PL_USER_PB0_IBUF_inst/O | 2 | 9 | 4.50 | -| design_1_i/TickGenerator_0/inst/FrameTick_BUFGCE | design_1_i/EnemyController_0/inst/enemies[3][R] | PL_USER_PB0_IBUF_inst/O | 5 | 9 | 1.80 | -| design_1_i/TickGenerator_0/inst/FrameTick_BUFGCE | design_1_i/EnemyController_0/inst/enemies[6][R] | PL_USER_PB0_IBUF_inst/O | 3 | 9 | 3.00 | -| design_1_i/TickGenerator_0/inst/FrameTick_BUFGCE | design_1_i/EnemyController_0/inst/enemies[8][R] | PL_USER_PB0_IBUF_inst/O | 3 | 9 | 3.00 | -| design_1_i/TickGenerator_0/inst/FrameTick_BUFGCE | design_1_i/EnemyController_0/inst/enemies[7][R] | PL_USER_PB0_IBUF_inst/O | 4 | 9 | 2.25 | -| design_1_i/TickGenerator_0/inst/FrameTick_BUFGCE | design_1_i/EnemyController_0/inst/enemies[9][R] | PL_USER_PB0_IBUF_inst/O | 4 | 9 | 2.25 | -| design_1_i/TickGenerator_0/inst/FrameTick_BUFGCE | design_1_i/EnemyController_0/inst/enemies[0][R] | PL_USER_PB0_IBUF_inst/O | 4 | 9 | 2.25 | -| design_1_i/TickGenerator_0/inst/FrameTick_BUFGCE | design_1_i/EnemyController_0/inst/enemies[10][R] | PL_USER_PB0_IBUF_inst/O | 3 | 9 | 3.00 | -| design_1_i/TickGenerator_0/inst/FrameTick_BUFGCE | design_1_i/EnemyController_0/inst/enemies[11][R] | PL_USER_PB0_IBUF_inst/O | 3 | 9 | 3.00 | -| design_1_i/TickGenerator_0/inst/FrameTick_BUFGCE | design_1_i/EnemyController_0/inst/enemies[12][R] | PL_USER_PB0_IBUF_inst/O | 3 | 9 | 3.00 | -| design_1_i/TickGenerator_0/inst/FrameTick_BUFGCE | design_1_i/EnemyController_0/inst/enemies[13][R] | PL_USER_PB0_IBUF_inst/O | 4 | 9 | 2.25 | -| design_1_i/TickGenerator_0/inst/FrameTick_BUFGCE | design_1_i/EnemyController_0/inst/enemies[14][R] | PL_USER_PB0_IBUF_inst/O | 5 | 9 | 1.80 | -| design_1_i/TickGenerator_0/inst/FrameTick_BUFGCE | design_1_i/EnemyController_0/inst/enemies[15][R] | PL_USER_PB0_IBUF_inst/O | 3 | 9 | 3.00 | -| design_1_i/TickGenerator_0/inst/FrameTick_BUFGCE | design_1_i/EnemyController_0/inst/enemies[17][R] | PL_USER_PB0_IBUF_inst/O | 3 | 9 | 3.00 | -| design_1_i/TickGenerator_0/inst/FrameTick_BUFGCE | design_1_i/EnemyController_0/inst/enemies[16][R] | PL_USER_PB0_IBUF_inst/O | 4 | 9 | 2.25 | -| design_1_i/TickGenerator_0/inst/FrameTick_BUFGCE | design_1_i/EnemyController_0/inst/enemies[18][R] | PL_USER_PB0_IBUF_inst/O | 3 | 9 | 3.00 | -| design_1_i/TickGenerator_0/inst/FrameTick_BUFGCE | design_1_i/EnemyController_0/inst/enemies[19][R] | PL_USER_PB0_IBUF_inst/O | 3 | 9 | 3.00 | -| design_1_i/TickGenerator_0/inst/FrameTick_BUFGCE | design_1_i/EnemyController_0/inst/enemies[20][R] | PL_USER_PB0_IBUF_inst/O | 4 | 9 | 2.25 | -| design_1_i/TickGenerator_0/inst/FrameTick_BUFGCE | design_1_i/EnemyController_0/inst/enemies[1][R] | PL_USER_PB0_IBUF_inst/O | 3 | 9 | 3.00 | -| design_1_i/TickGenerator_0/inst/FrameTick_BUFGCE | design_1_i/EnemyController_0/inst/enemies[21][R] | PL_USER_PB0_IBUF_inst/O | 4 | 9 | 2.25 | -| design_1_i/clk_wiz_0/inst/clk25 | | design_1_i/VideoTiming_0/inst/cntX[9]_i_1_n_0 | 3 | 10 | 3.33 | -| design_1_i/clk_wiz_0/inst/clk25 | design_1_i/VideoTiming_0/inst/cntX_TC | design_1_i/VideoTiming_0/inst/cntY[9]_i_1_n_0 | 3 | 10 | 3.33 | -| design_1_i/clk_wiz_0/inst/clk25 | | design_1_i/HDMI_TX_0/U0/i_wrap/Cnt[4]_i_1_n_0 | 10 | 12 | 1.20 | -| design_1_i/TickGenerator_0/inst/FrameTick_BUFGCE | design_1_i/VideoTiming_0/inst/VSync | PL_USER_PB0_IBUF_inst/O | 6 | 17 | 2.83 | -| design_1_i/clk_wiz_0/inst/clk25 | | PL_USER_PB0_IBUF_inst/O | 4 | 20 | 5.00 | -| design_1_i/TickGenerator_0/inst/FrameTick_BUFGCE | | PL_USER_PB0_IBUF_inst/O | 24 | 24 | 1.00 | -| design_1_i/clk_wiz_0/inst/clk125 | | design_1_i/clk_wiz_0/inst/locked | 12 | 33 | 2.75 | -| design_1_i/clk_wiz_0/inst/clk25 | | | 19 | 38 | 2.00 | -+---------------------------------------------------+-------------------------------------------------------+------------------------------------------------------+------------------+----------------+--------------+ - - diff --git a/SW2.runs/impl_1/design_1_wrapper_drc_opted.pb b/SW2.runs/impl_1/design_1_wrapper_drc_opted.pb deleted file mode 100644 index c8dbb55..0000000 Binary files a/SW2.runs/impl_1/design_1_wrapper_drc_opted.pb and /dev/null differ diff --git a/SW2.runs/impl_1/design_1_wrapper_drc_opted.rpt b/SW2.runs/impl_1/design_1_wrapper_drc_opted.rpt deleted file mode 100644 index b45094c..0000000 --- a/SW2.runs/impl_1/design_1_wrapper_drc_opted.rpt +++ /dev/null @@ -1,608 +0,0 @@ -Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. ---------------------------------------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2025.1 (win64) Build 6140274 Thu May 22 00:12:29 MDT 2025 -| Date : Tue Jun 9 14:06:28 2026 -| Host : Lab016-04 running 64-bit major release (build 9200) -| Command : report_drc -file design_1_wrapper_drc_opted.rpt -pb design_1_wrapper_drc_opted.pb -rpx design_1_wrapper_drc_opted.rpx -| Design : design_1_wrapper -| Device : xczu3eg-sfvc784-2-e -| Speed File : -2 -| Design State : Synthesized ---------------------------------------------------------------------------------------------------------------------------------------------- - -Report DRC - -Table of Contents ------------------ -1. REPORT SUMMARY -2. REPORT DETAILS - -1. REPORT SUMMARY ------------------ - Netlist: netlist - Floorplan: design_1 - Design limits: - Ruledeck: default - Max checks: - Checks found: 114 -+--------+----------+------------------------+--------+ -| Rule | Severity | Description | Checks | -+--------+----------+------------------------+--------+ -| DPIP-2 | Warning | Input pipelining | 38 | -| DPOP-3 | Warning | PREG Output pipelining | 38 | -| DPOP-4 | Warning | MREG Output pipelining | 38 | -+--------+----------+------------------------+--------+ - -2. REPORT DETAILS ------------------ -DPIP-2#1 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[10]4 input design_1_i/ImgGen_0/inst/enemyX[10]4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#2 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[11]4 input design_1_i/ImgGen_0/inst/enemyX[11]4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#3 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[13]4 input design_1_i/ImgGen_0/inst/enemyX[13]4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#4 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[14]4 input design_1_i/ImgGen_0/inst/enemyX[14]4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#5 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[15]4 input design_1_i/ImgGen_0/inst/enemyX[15]4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#6 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[17]4 input design_1_i/ImgGen_0/inst/enemyX[17]4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#7 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[19]2 input design_1_i/ImgGen_0/inst/enemyX[19]2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#8 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[1]2 input design_1_i/ImgGen_0/inst/enemyX[1]2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#9 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[21]2 input design_1_i/ImgGen_0/inst/enemyX[21]2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#10 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[22]2 input design_1_i/ImgGen_0/inst/enemyX[22]2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#11 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[23]2 input design_1_i/ImgGen_0/inst/enemyX[23]2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#12 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[2]2 input design_1_i/ImgGen_0/inst/enemyX[2]2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#13 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[3]2 input design_1_i/ImgGen_0/inst/enemyX[3]2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#14 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[3]2__0 input design_1_i/ImgGen_0/inst/enemyX[3]2__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#15 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[5]2 input design_1_i/ImgGen_0/inst/enemyX[5]2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#16 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[7]4 input design_1_i/ImgGen_0/inst/enemyX[7]4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#17 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[9]4 input design_1_i/ImgGen_0/inst/enemyX[9]4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#18 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[11]2 input design_1_i/ImgGen_0/inst/enemyY[11]2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#19 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[11]2__0 input design_1_i/ImgGen_0/inst/enemyY[11]2__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#20 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[13]4 input design_1_i/ImgGen_0/inst/enemyY[13]4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#21 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[16]4 input design_1_i/ImgGen_0/inst/enemyY[16]4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#22 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[17]4 input design_1_i/ImgGen_0/inst/enemyY[17]4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#23 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[19]4 input design_1_i/ImgGen_0/inst/enemyY[19]4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#24 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[1]2 input design_1_i/ImgGen_0/inst/enemyY[1]2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#25 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[1]2__0 input design_1_i/ImgGen_0/inst/enemyY[1]2__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#26 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[20]4 input design_1_i/ImgGen_0/inst/enemyY[20]4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#27 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[21]4 input design_1_i/ImgGen_0/inst/enemyY[21]4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#28 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[23]4 input design_1_i/ImgGen_0/inst/enemyY[23]4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#29 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[4]2 input design_1_i/ImgGen_0/inst/enemyY[4]2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#30 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[4]2__0 input design_1_i/ImgGen_0/inst/enemyY[4]2__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#31 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[5]2 input design_1_i/ImgGen_0/inst/enemyY[5]2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#32 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[5]2__0 input design_1_i/ImgGen_0/inst/enemyY[5]2__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#33 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[7]2 input design_1_i/ImgGen_0/inst/enemyY[7]2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#34 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[7]2__0 input design_1_i/ImgGen_0/inst/enemyY[7]2__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#35 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[8]2 input design_1_i/ImgGen_0/inst/enemyY[8]2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#36 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[8]2__0 input design_1_i/ImgGen_0/inst/enemyY[8]2__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#37 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[9]2 input design_1_i/ImgGen_0/inst/enemyY[9]2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#38 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[9]2__0 input design_1_i/ImgGen_0/inst/enemyY[9]2__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPOP-3#1 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[10]4 output design_1_i/ImgGen_0/inst/enemyX[10]4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#2 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[11]4 output design_1_i/ImgGen_0/inst/enemyX[11]4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#3 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[13]4 output design_1_i/ImgGen_0/inst/enemyX[13]4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#4 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[14]4 output design_1_i/ImgGen_0/inst/enemyX[14]4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#5 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[15]4 output design_1_i/ImgGen_0/inst/enemyX[15]4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#6 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[17]4 output design_1_i/ImgGen_0/inst/enemyX[17]4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#7 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[19]2 output design_1_i/ImgGen_0/inst/enemyX[19]2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#8 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[1]2 output design_1_i/ImgGen_0/inst/enemyX[1]2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#9 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[21]2 output design_1_i/ImgGen_0/inst/enemyX[21]2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#10 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[22]2 output design_1_i/ImgGen_0/inst/enemyX[22]2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#11 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[23]2 output design_1_i/ImgGen_0/inst/enemyX[23]2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#12 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[2]2 output design_1_i/ImgGen_0/inst/enemyX[2]2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#13 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[3]2 output design_1_i/ImgGen_0/inst/enemyX[3]2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#14 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[3]2__0 output design_1_i/ImgGen_0/inst/enemyX[3]2__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#15 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[5]2 output design_1_i/ImgGen_0/inst/enemyX[5]2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#16 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[7]4 output design_1_i/ImgGen_0/inst/enemyX[7]4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#17 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[9]4 output design_1_i/ImgGen_0/inst/enemyX[9]4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#18 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[11]2 output design_1_i/ImgGen_0/inst/enemyY[11]2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#19 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[11]2__0 output design_1_i/ImgGen_0/inst/enemyY[11]2__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#20 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[13]4 output design_1_i/ImgGen_0/inst/enemyY[13]4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#21 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[16]4 output design_1_i/ImgGen_0/inst/enemyY[16]4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#22 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[17]4 output design_1_i/ImgGen_0/inst/enemyY[17]4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#23 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[19]4 output design_1_i/ImgGen_0/inst/enemyY[19]4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#24 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[1]2 output design_1_i/ImgGen_0/inst/enemyY[1]2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#25 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[1]2__0 output design_1_i/ImgGen_0/inst/enemyY[1]2__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#26 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[20]4 output design_1_i/ImgGen_0/inst/enemyY[20]4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#27 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[21]4 output design_1_i/ImgGen_0/inst/enemyY[21]4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#28 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[23]4 output design_1_i/ImgGen_0/inst/enemyY[23]4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#29 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[4]2 output design_1_i/ImgGen_0/inst/enemyY[4]2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#30 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[4]2__0 output design_1_i/ImgGen_0/inst/enemyY[4]2__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#31 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[5]2 output design_1_i/ImgGen_0/inst/enemyY[5]2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#32 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[5]2__0 output design_1_i/ImgGen_0/inst/enemyY[5]2__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#33 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[7]2 output design_1_i/ImgGen_0/inst/enemyY[7]2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#34 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[7]2__0 output design_1_i/ImgGen_0/inst/enemyY[7]2__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#35 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[8]2 output design_1_i/ImgGen_0/inst/enemyY[8]2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#36 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[8]2__0 output design_1_i/ImgGen_0/inst/enemyY[8]2__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#37 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[9]2 output design_1_i/ImgGen_0/inst/enemyY[9]2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#38 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[9]2__0 output design_1_i/ImgGen_0/inst/enemyY[9]2__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-4#1 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[10]4 multiplier stage design_1_i/ImgGen_0/inst/enemyX[10]4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#2 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[11]4 multiplier stage design_1_i/ImgGen_0/inst/enemyX[11]4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#3 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[13]4 multiplier stage design_1_i/ImgGen_0/inst/enemyX[13]4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#4 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[14]4 multiplier stage design_1_i/ImgGen_0/inst/enemyX[14]4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#5 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[15]4 multiplier stage design_1_i/ImgGen_0/inst/enemyX[15]4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#6 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[17]4 multiplier stage design_1_i/ImgGen_0/inst/enemyX[17]4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#7 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[19]2 multiplier stage design_1_i/ImgGen_0/inst/enemyX[19]2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#8 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[1]2 multiplier stage design_1_i/ImgGen_0/inst/enemyX[1]2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#9 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[21]2 multiplier stage design_1_i/ImgGen_0/inst/enemyX[21]2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#10 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[22]2 multiplier stage design_1_i/ImgGen_0/inst/enemyX[22]2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#11 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[23]2 multiplier stage design_1_i/ImgGen_0/inst/enemyX[23]2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#12 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[2]2 multiplier stage design_1_i/ImgGen_0/inst/enemyX[2]2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#13 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[3]2 multiplier stage design_1_i/ImgGen_0/inst/enemyX[3]2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#14 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[3]2__0 multiplier stage design_1_i/ImgGen_0/inst/enemyX[3]2__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#15 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[5]2 multiplier stage design_1_i/ImgGen_0/inst/enemyX[5]2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#16 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[7]4 multiplier stage design_1_i/ImgGen_0/inst/enemyX[7]4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#17 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[9]4 multiplier stage design_1_i/ImgGen_0/inst/enemyX[9]4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#18 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[11]2 multiplier stage design_1_i/ImgGen_0/inst/enemyY[11]2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#19 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[11]2__0 multiplier stage design_1_i/ImgGen_0/inst/enemyY[11]2__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#20 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[13]4 multiplier stage design_1_i/ImgGen_0/inst/enemyY[13]4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#21 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[16]4 multiplier stage design_1_i/ImgGen_0/inst/enemyY[16]4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#22 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[17]4 multiplier stage design_1_i/ImgGen_0/inst/enemyY[17]4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#23 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[19]4 multiplier stage design_1_i/ImgGen_0/inst/enemyY[19]4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#24 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[1]2 multiplier stage design_1_i/ImgGen_0/inst/enemyY[1]2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#25 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[1]2__0 multiplier stage design_1_i/ImgGen_0/inst/enemyY[1]2__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#26 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[20]4 multiplier stage design_1_i/ImgGen_0/inst/enemyY[20]4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#27 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[21]4 multiplier stage design_1_i/ImgGen_0/inst/enemyY[21]4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#28 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[23]4 multiplier stage design_1_i/ImgGen_0/inst/enemyY[23]4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#29 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[4]2 multiplier stage design_1_i/ImgGen_0/inst/enemyY[4]2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#30 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[4]2__0 multiplier stage design_1_i/ImgGen_0/inst/enemyY[4]2__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#31 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[5]2 multiplier stage design_1_i/ImgGen_0/inst/enemyY[5]2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#32 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[5]2__0 multiplier stage design_1_i/ImgGen_0/inst/enemyY[5]2__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#33 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[7]2 multiplier stage design_1_i/ImgGen_0/inst/enemyY[7]2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#34 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[7]2__0 multiplier stage design_1_i/ImgGen_0/inst/enemyY[7]2__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#35 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[8]2 multiplier stage design_1_i/ImgGen_0/inst/enemyY[8]2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#36 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[8]2__0 multiplier stage design_1_i/ImgGen_0/inst/enemyY[8]2__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#37 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[9]2 multiplier stage design_1_i/ImgGen_0/inst/enemyY[9]2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#38 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[9]2__0 multiplier stage design_1_i/ImgGen_0/inst/enemyY[9]2__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - - diff --git a/SW2.runs/impl_1/design_1_wrapper_drc_opted.rpx b/SW2.runs/impl_1/design_1_wrapper_drc_opted.rpx deleted file mode 100644 index 64402f2..0000000 Binary files a/SW2.runs/impl_1/design_1_wrapper_drc_opted.rpx and /dev/null differ diff --git a/SW2.runs/impl_1/design_1_wrapper_drc_routed.pb b/SW2.runs/impl_1/design_1_wrapper_drc_routed.pb deleted file mode 100644 index c8dbb55..0000000 Binary files a/SW2.runs/impl_1/design_1_wrapper_drc_routed.pb and /dev/null differ diff --git a/SW2.runs/impl_1/design_1_wrapper_drc_routed.rpt b/SW2.runs/impl_1/design_1_wrapper_drc_routed.rpt deleted file mode 100644 index 9cf727d..0000000 --- a/SW2.runs/impl_1/design_1_wrapper_drc_routed.rpt +++ /dev/null @@ -1,608 +0,0 @@ -Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. ---------------------------------------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2025.1 (win64) Build 6140274 Thu May 22 00:12:29 MDT 2025 -| Date : Tue Jun 9 14:07:58 2026 -| Host : Lab016-04 running 64-bit major release (build 9200) -| Command : report_drc -file design_1_wrapper_drc_routed.rpt -pb design_1_wrapper_drc_routed.pb -rpx design_1_wrapper_drc_routed.rpx -| Design : design_1_wrapper -| Device : xczu3eg-sfvc784-2-e -| Speed File : -2 -| Design State : Fully Routed ---------------------------------------------------------------------------------------------------------------------------------------------- - -Report DRC - -Table of Contents ------------------ -1. REPORT SUMMARY -2. REPORT DETAILS - -1. REPORT SUMMARY ------------------ - Netlist: netlist - Floorplan: design_1 - Design limits: - Ruledeck: default - Max checks: - Checks found: 114 -+--------+----------+------------------------+--------+ -| Rule | Severity | Description | Checks | -+--------+----------+------------------------+--------+ -| DPIP-2 | Warning | Input pipelining | 38 | -| DPOP-3 | Warning | PREG Output pipelining | 38 | -| DPOP-4 | Warning | MREG Output pipelining | 38 | -+--------+----------+------------------------+--------+ - -2. REPORT DETAILS ------------------ -DPIP-2#1 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[10]4 input design_1_i/ImgGen_0/inst/enemyX[10]4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#2 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[11]4 input design_1_i/ImgGen_0/inst/enemyX[11]4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#3 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[13]4 input design_1_i/ImgGen_0/inst/enemyX[13]4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#4 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[14]4 input design_1_i/ImgGen_0/inst/enemyX[14]4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#5 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[15]4 input design_1_i/ImgGen_0/inst/enemyX[15]4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#6 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[17]4 input design_1_i/ImgGen_0/inst/enemyX[17]4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#7 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[19]2 input design_1_i/ImgGen_0/inst/enemyX[19]2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#8 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[1]2 input design_1_i/ImgGen_0/inst/enemyX[1]2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#9 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[21]2 input design_1_i/ImgGen_0/inst/enemyX[21]2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#10 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[22]2 input design_1_i/ImgGen_0/inst/enemyX[22]2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#11 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[23]2 input design_1_i/ImgGen_0/inst/enemyX[23]2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#12 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[2]2 input design_1_i/ImgGen_0/inst/enemyX[2]2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#13 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[3]2 input design_1_i/ImgGen_0/inst/enemyX[3]2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#14 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[3]2__0 input design_1_i/ImgGen_0/inst/enemyX[3]2__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#15 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[5]2 input design_1_i/ImgGen_0/inst/enemyX[5]2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#16 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[7]4 input design_1_i/ImgGen_0/inst/enemyX[7]4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#17 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[9]4 input design_1_i/ImgGen_0/inst/enemyX[9]4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#18 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[11]2 input design_1_i/ImgGen_0/inst/enemyY[11]2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#19 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[11]2__0 input design_1_i/ImgGen_0/inst/enemyY[11]2__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#20 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[13]4 input design_1_i/ImgGen_0/inst/enemyY[13]4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#21 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[16]4 input design_1_i/ImgGen_0/inst/enemyY[16]4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#22 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[17]4 input design_1_i/ImgGen_0/inst/enemyY[17]4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#23 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[19]4 input design_1_i/ImgGen_0/inst/enemyY[19]4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#24 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[1]2 input design_1_i/ImgGen_0/inst/enemyY[1]2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#25 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[1]2__0 input design_1_i/ImgGen_0/inst/enemyY[1]2__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#26 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[20]4 input design_1_i/ImgGen_0/inst/enemyY[20]4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#27 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[21]4 input design_1_i/ImgGen_0/inst/enemyY[21]4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#28 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[23]4 input design_1_i/ImgGen_0/inst/enemyY[23]4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#29 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[4]2 input design_1_i/ImgGen_0/inst/enemyY[4]2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#30 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[4]2__0 input design_1_i/ImgGen_0/inst/enemyY[4]2__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#31 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[5]2 input design_1_i/ImgGen_0/inst/enemyY[5]2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#32 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[5]2__0 input design_1_i/ImgGen_0/inst/enemyY[5]2__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#33 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[7]2 input design_1_i/ImgGen_0/inst/enemyY[7]2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#34 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[7]2__0 input design_1_i/ImgGen_0/inst/enemyY[7]2__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#35 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[8]2 input design_1_i/ImgGen_0/inst/enemyY[8]2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#36 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[8]2__0 input design_1_i/ImgGen_0/inst/enemyY[8]2__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#37 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[9]2 input design_1_i/ImgGen_0/inst/enemyY[9]2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-2#38 Warning -Input pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[9]2__0 input design_1_i/ImgGen_0/inst/enemyY[9]2__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPOP-3#1 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[10]4 output design_1_i/ImgGen_0/inst/enemyX[10]4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#2 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[11]4 output design_1_i/ImgGen_0/inst/enemyX[11]4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#3 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[13]4 output design_1_i/ImgGen_0/inst/enemyX[13]4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#4 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[14]4 output design_1_i/ImgGen_0/inst/enemyX[14]4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#5 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[15]4 output design_1_i/ImgGen_0/inst/enemyX[15]4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#6 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[17]4 output design_1_i/ImgGen_0/inst/enemyX[17]4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#7 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[19]2 output design_1_i/ImgGen_0/inst/enemyX[19]2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#8 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[1]2 output design_1_i/ImgGen_0/inst/enemyX[1]2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#9 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[21]2 output design_1_i/ImgGen_0/inst/enemyX[21]2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#10 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[22]2 output design_1_i/ImgGen_0/inst/enemyX[22]2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#11 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[23]2 output design_1_i/ImgGen_0/inst/enemyX[23]2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#12 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[2]2 output design_1_i/ImgGen_0/inst/enemyX[2]2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#13 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[3]2 output design_1_i/ImgGen_0/inst/enemyX[3]2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#14 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[3]2__0 output design_1_i/ImgGen_0/inst/enemyX[3]2__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#15 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[5]2 output design_1_i/ImgGen_0/inst/enemyX[5]2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#16 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[7]4 output design_1_i/ImgGen_0/inst/enemyX[7]4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#17 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[9]4 output design_1_i/ImgGen_0/inst/enemyX[9]4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#18 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[11]2 output design_1_i/ImgGen_0/inst/enemyY[11]2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#19 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[11]2__0 output design_1_i/ImgGen_0/inst/enemyY[11]2__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#20 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[13]4 output design_1_i/ImgGen_0/inst/enemyY[13]4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#21 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[16]4 output design_1_i/ImgGen_0/inst/enemyY[16]4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#22 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[17]4 output design_1_i/ImgGen_0/inst/enemyY[17]4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#23 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[19]4 output design_1_i/ImgGen_0/inst/enemyY[19]4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#24 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[1]2 output design_1_i/ImgGen_0/inst/enemyY[1]2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#25 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[1]2__0 output design_1_i/ImgGen_0/inst/enemyY[1]2__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#26 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[20]4 output design_1_i/ImgGen_0/inst/enemyY[20]4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#27 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[21]4 output design_1_i/ImgGen_0/inst/enemyY[21]4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#28 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[23]4 output design_1_i/ImgGen_0/inst/enemyY[23]4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#29 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[4]2 output design_1_i/ImgGen_0/inst/enemyY[4]2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#30 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[4]2__0 output design_1_i/ImgGen_0/inst/enemyY[4]2__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#31 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[5]2 output design_1_i/ImgGen_0/inst/enemyY[5]2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#32 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[5]2__0 output design_1_i/ImgGen_0/inst/enemyY[5]2__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#33 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[7]2 output design_1_i/ImgGen_0/inst/enemyY[7]2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#34 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[7]2__0 output design_1_i/ImgGen_0/inst/enemyY[7]2__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#35 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[8]2 output design_1_i/ImgGen_0/inst/enemyY[8]2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#36 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[8]2__0 output design_1_i/ImgGen_0/inst/enemyY[8]2__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#37 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[9]2 output design_1_i/ImgGen_0/inst/enemyY[9]2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-3#38 Warning -PREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[9]2__0 output design_1_i/ImgGen_0/inst/enemyY[9]2__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-4#1 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[10]4 multiplier stage design_1_i/ImgGen_0/inst/enemyX[10]4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#2 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[11]4 multiplier stage design_1_i/ImgGen_0/inst/enemyX[11]4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#3 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[13]4 multiplier stage design_1_i/ImgGen_0/inst/enemyX[13]4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#4 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[14]4 multiplier stage design_1_i/ImgGen_0/inst/enemyX[14]4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#5 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[15]4 multiplier stage design_1_i/ImgGen_0/inst/enemyX[15]4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#6 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[17]4 multiplier stage design_1_i/ImgGen_0/inst/enemyX[17]4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#7 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[19]2 multiplier stage design_1_i/ImgGen_0/inst/enemyX[19]2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#8 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[1]2 multiplier stage design_1_i/ImgGen_0/inst/enemyX[1]2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#9 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[21]2 multiplier stage design_1_i/ImgGen_0/inst/enemyX[21]2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#10 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[22]2 multiplier stage design_1_i/ImgGen_0/inst/enemyX[22]2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#11 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[23]2 multiplier stage design_1_i/ImgGen_0/inst/enemyX[23]2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#12 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[2]2 multiplier stage design_1_i/ImgGen_0/inst/enemyX[2]2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#13 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[3]2 multiplier stage design_1_i/ImgGen_0/inst/enemyX[3]2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#14 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[3]2__0 multiplier stage design_1_i/ImgGen_0/inst/enemyX[3]2__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#15 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[5]2 multiplier stage design_1_i/ImgGen_0/inst/enemyX[5]2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#16 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[7]4 multiplier stage design_1_i/ImgGen_0/inst/enemyX[7]4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#17 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyX[9]4 multiplier stage design_1_i/ImgGen_0/inst/enemyX[9]4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#18 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[11]2 multiplier stage design_1_i/ImgGen_0/inst/enemyY[11]2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#19 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[11]2__0 multiplier stage design_1_i/ImgGen_0/inst/enemyY[11]2__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#20 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[13]4 multiplier stage design_1_i/ImgGen_0/inst/enemyY[13]4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#21 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[16]4 multiplier stage design_1_i/ImgGen_0/inst/enemyY[16]4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#22 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[17]4 multiplier stage design_1_i/ImgGen_0/inst/enemyY[17]4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#23 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[19]4 multiplier stage design_1_i/ImgGen_0/inst/enemyY[19]4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#24 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[1]2 multiplier stage design_1_i/ImgGen_0/inst/enemyY[1]2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#25 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[1]2__0 multiplier stage design_1_i/ImgGen_0/inst/enemyY[1]2__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#26 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[20]4 multiplier stage design_1_i/ImgGen_0/inst/enemyY[20]4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#27 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[21]4 multiplier stage design_1_i/ImgGen_0/inst/enemyY[21]4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#28 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[23]4 multiplier stage design_1_i/ImgGen_0/inst/enemyY[23]4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#29 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[4]2 multiplier stage design_1_i/ImgGen_0/inst/enemyY[4]2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#30 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[4]2__0 multiplier stage design_1_i/ImgGen_0/inst/enemyY[4]2__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#31 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[5]2 multiplier stage design_1_i/ImgGen_0/inst/enemyY[5]2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#32 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[5]2__0 multiplier stage design_1_i/ImgGen_0/inst/enemyY[5]2__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#33 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[7]2 multiplier stage design_1_i/ImgGen_0/inst/enemyY[7]2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#34 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[7]2__0 multiplier stage design_1_i/ImgGen_0/inst/enemyY[7]2__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#35 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[8]2 multiplier stage design_1_i/ImgGen_0/inst/enemyY[8]2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#36 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[8]2__0 multiplier stage design_1_i/ImgGen_0/inst/enemyY[8]2__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#37 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[9]2 multiplier stage design_1_i/ImgGen_0/inst/enemyY[9]2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-4#38 Warning -MREG Output pipelining -DSP design_1_i/ImgGen_0/inst/enemyY[9]2__0 multiplier stage design_1_i/ImgGen_0/inst/enemyY[9]2__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - - diff --git a/SW2.runs/impl_1/design_1_wrapper_drc_routed.rpx b/SW2.runs/impl_1/design_1_wrapper_drc_routed.rpx deleted file mode 100644 index d37c6b8..0000000 Binary files a/SW2.runs/impl_1/design_1_wrapper_drc_routed.rpx and /dev/null differ diff --git a/SW2.runs/impl_1/design_1_wrapper_io_placed.rpt b/SW2.runs/impl_1/design_1_wrapper_io_placed.rpt deleted file mode 100644 index bcc1db6..0000000 --- a/SW2.runs/impl_1/design_1_wrapper_io_placed.rpt +++ /dev/null @@ -1,826 +0,0 @@ -Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. ----------------------------------------------------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2025.1 (win64) Build 6140274 Thu May 22 00:12:29 MDT 2025 -| Date : Tue Jun 9 14:07:42 2026 -| Host : Lab016-04 running 64-bit major release (build 9200) -| Command : report_io -file design_1_wrapper_io_placed.rpt -| Design : design_1_wrapper -| Device : xczu3eg -| Speed File : -2 -| Package : sfvc784 -| Package Version : PRODUCTION 1.1 3/6/2017 -| Package Pin Delay Version : PRODUCTION 1.0 4/13/2016 ----------------------------------------------------------------------------------------------------------------------------------------------------------- - -IO Information - -Table of Contents ------------------ -1. Summary -2. IO Assignments by Package Pin - -1. Summary ----------- - -+---------------+ -| Total User IO | -+---------------+ -| 16 | -+---------------+ - - -2. IO Assignments by Package Pin --------------------------------- - -+------------+------------------+------------------+------------------------------------+---------------+-------------+---------+------------+-------------------------+------+-------------------+----------------------+-----------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ -| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Output Impedance (ohms) | Slew | Input Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization | -+------------+------------------+------------------+------------------------------------+---------------+-------------+---------+------------+-------------------------+------+-------------------+----------------------+-----------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ -| A1 | | High Performance | IO_L8N_T1L_N3_AD5N_66 | User IO | | 66 | | | | | | | | | | | | | | | -| A2 | | High Performance | IO_L8P_T1L_N2_AD5P_66 | User IO | | 66 | | | | | | | | | | | | | | | -| A3 | | High Performance | IO_L9N_T1L_N5_AD12N_66 | User IO | | 66 | | | | | | | | | | | | | | | -| A4 | | High Performance | IO_L10N_T1U_N7_QBC_AD4N_66 | User IO | | 66 | | | | | | | | | | | | | | | -| A5 | | High Performance | IO_L19N_T3L_N1_DBC_AD9N_66 | User IO | | 66 | | | | | | | | | | | | | | | -| A6 | | High Performance | IO_L21N_T3L_N5_AD8N_66 | User IO | | 66 | | | | | | | | | | | | | | | -| A7 | | High Performance | IO_L21P_T3L_N4_AD8P_66 | User IO | | 66 | | | | | | | | | | | | | | | -| A8 | | High Performance | IO_L23N_T3U_N9_66 | User IO | | 66 | | | | | | | | | | | | | | | -| A9 | | High Performance | IO_L23P_T3U_N8_66 | User IO | | 66 | | | | | | | | | | | | | | | -| A10 | | High Density | IO_L10N_AD10N_25 | User IO | | 25 | | | | | | | | | | | | | | | -| A11 | | High Density | IO_L11N_AD9N_25 | User IO | | 25 | | | | | | | | | | | | | | | -| A12 | | High Density | IO_L11P_AD9P_25 | User IO | | 25 | | | | | | | | | | | | | | | -| A13 | | High Density | IO_L3N_AD9N_26 | User IO | | 26 | | | | | | | | | | | | | | | -| A14 | | High Density | IO_L2N_AD10N_26 | User IO | | 26 | | | | | | | | | | | | | | | -| A15 | | High Density | IO_L1N_AD11N_26 | User IO | | 26 | | | | | | | | | | | | | | | -| A16 | | | PS_MIO57_502 | PSS IO | | | | | | | | | | | | | | | | | -| A17 | | | PS_MIO62_502 | PSS IO | | | | | | | | | | | | | | | | | -| A18 | | | PS_MIO65_502 | PSS IO | | | | | | | | | | | | | | | | | -| A19 | | | PS_MIO75_502 | PSS IO | | | | | | | | | | | | | | | | | -| A20 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| A21 | | | PS_MGTREFCLK3P_505 | PSS IO | | | | | | | | | | | | | | | | | -| A22 | | | PS_MGTREFCLK3N_505 | PSS IO | | | | | | | | | | | | | | | | | -| A23 | | | PS_MGTRAVTT | PSS IO | | | | | | | | | | | | | | | | | -| A24 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| A25 | | | PS_MGTRRXP3_505 | PSS IO | | | | | | | | | | | | | | | | | -| A26 | | | PS_MGTRRXN3_505 | PSS IO | | | | | | | | | | | | | | | | | -| A27 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| A28 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| AA1 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| AA2 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| AA3 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| AA4 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| AA5 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| AA6 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| AA7 | | High Performance | VREF_64 | Voltage | | 64 | | | | | | | | | | | | | | | -| AA8 | ROT_A | High Density | IO_L11N_AD1N_44 | INPUT | LVCMOS33 | 44 | | | | | NONE | | FIXED | | | | NONE | | | | -| AA9 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| AA10 | | High Density | IO_L9N_AD3N_44 | User IO | | 44 | | | | | | | | | | | | | | | -| AA11 | | High Density | IO_L9P_AD3P_44 | User IO | | 44 | | | | | | | | | | | | | | | -| AA12 | | High Density | IO_L12N_AD8N_24 | User IO | | 24 | | | | | | | | | | | | | | | -| AA13 | | High Density | IO_L7P_HDGC_24 | GCLK | | 24 | | | | | | | | | | | | | | | -| AA14 | | High Density | VCCO_24 | VCCO | | 24 | | | | | | any** | | | | | | | | | -| AA15 | | | VCC_PSINTFP | PSS VCCINT | | | | | | | | | | | | | | | | | -| AA16 | | | VCC_PSINTFP | PSS VCCINT | | | | | | | | | | | | | | | | | -| AA17 | | | VCC_PSINTFP | PSS VCCINT | | | | | | | | | | | | | | | | | -| AA18 | | | VCC_PSINTFP | PSS VCCINT | | | | | | | | | | | | | | | | | -| AA19 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| AA20 | | | VCC_PSINTFP_DDR | PSS VCCINT | | | | | | | | | | | | | | | | | -| AA21 | | | VCC_PSINTFP_DDR | PSS VCCINT | | | | | | | | | | | | | | | | | -| AA22 | | | PS_DDR_A8_504 | PSS IO | | | | | | | | | | | | | | | | | -| AA23 | | | PS_DDR_A7_504 | PSS IO | | | | | | | | | | | | | | | | | -| AA24 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| AA25 | | | PS_DDR_A10_504 | PSS IO | | | | | | | | | | | | | | | | | -| AA26 | | | PS_DDR_A11_504 | PSS IO | | | | | | | | | | | | | | | | | -| AA27 | | | PS_DDR_A5_504 | PSS IO | | | | | | | | | | | | | | | | | -| AA28 | | | PS_DDR_A3_504 | PSS IO | | | | | | | | | | | | | | | | | -| AB1 | | High Performance | IO_L18P_T2U_N10_AD2P_64 | User IO | | 64 | | | | | | | | | | | | | | | -| AB2 | | High Performance | IO_L17P_T2U_N8_AD10P_64 | User IO | | 64 | | | | | | | | | | | | | | | -| AB3 | | High Performance | IO_L15N_T2L_N5_AD11N_64 | User IO | | 64 | | | | | | | | | | | | | | | -| AB4 | | High Performance | IO_L15P_T2L_N4_AD11P_64 | User IO | | 64 | | | | | | | | | | | | | | | -| AB5 | | High Performance | IO_T2U_N12_64 | User IO | | 64 | | | | | | | | | | | | | | | -| AB6 | PL_USER_PB0 | High Performance | IO_L6P_T0U_N10_AD6P_64 | INPUT | LVCMOS12 | 64 | | | | | NONE | | FIXED | | | | NONE | | | | -| AB7 | | High Performance | IO_L5P_T0U_N8_AD14P_64 | User IO | | 64 | | | | | | | | | | | | | | | -| AB8 | | High Performance | IO_L3P_T0L_N4_AD15P_64 | User IO | | 64 | | | | | | | | | | | | | | | -| AB9 | | High Density | IO_L12N_AD0N_44 | User IO | | 44 | | | | | | | | | | | | | | | -| AB10 | | High Density | IO_L12P_AD0P_44 | User IO | | 44 | | | | | | | | | | | | | | | -| AB11 | | High Density | IO_L8P_HDGC_AD4P_44 | GCLK | | 44 | | | | | | | | | | | | | | | -| AB12 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| AB13 | | High Density | IO_L7N_HDGC_24 | GCLK | | 24 | | | | | | | | | | | | | | | -| AB14 | | High Density | IO_L8N_HDGC_24 | GCLK | | 24 | | | | | | | | | | | | | | | -| AB15 | | High Density | IO_L8P_HDGC_24 | GCLK | | 24 | | | | | | | | | | | | | | | -| AB16 | | | VCC_PSINTFP | PSS VCCINT | | | | | | | | | | | | | | | | | -| AB17 | | | VCCO_PSIO0_500 | VCCO | | | | | | | | any** | | | | | | | | | -| AB18 | | | PS_MIO23_500 | PSS IO | | | | | | | | | | | | | | | | | -| AB19 | | | PS_MIO24_500 | PSS IO | | | | | | | | | | | | | | | | | -| AB20 | | | PS_MIO22_500 | PSS IO | | | | | | | | | | | | | | | | | -| AB21 | | | PS_MIO25_500 | PSS IO | | | | | | | | | | | | | | | | | -| AB22 | | | VCCO_PSDDR_504 | VCCO | | | | | | | | any** | | | | | | | | | -| AB23 | | | PS_DDR_A9_504 | PSS IO | | | | | | | | | | | | | | | | | -| AB24 | | | PS_DDR_A14_504 | PSS IO | | | | | | | | | | | | | | | | | -| AB25 | | | PS_DDR_A12_504 | PSS IO | | | | | | | | | | | | | | | | | -| AB26 | | | PS_DDR_A13_504 | PSS IO | | | | | | | | | | | | | | | | | -| AB27 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| AB28 | | | PS_DDR_A2_504 | PSS IO | | | | | | | | | | | | | | | | | -| AC1 | | High Performance | IO_L18N_T2U_N11_AD2N_64 | User IO | | 64 | | | | | | | | | | | | | | | -| AC2 | | High Performance | IO_L17N_T2U_N9_AD10N_64 | User IO | | 64 | | | | | | | | | | | | | | | -| AC3 | | High Performance | IO_L14N_T2L_N3_GC_64 | GCLK | | 64 | | | | | | | | | | | | | | | -| AC4 | | High Performance | IO_L14P_T2L_N2_GC_64 | GCLK | | 64 | | | | | | | | | | | | | | | -| AC5 | | High Performance | VCCO_64 | VCCO | | 64 | | | | | | 1.20 | | | | | | | | | -| AC6 | | High Performance | IO_L6N_T0U_N11_AD6N_64 | User IO | | 64 | | | | | | | | | | | | | | | -| AC7 | | High Performance | IO_L5N_T0U_N9_AD14N_64 | User IO | | 64 | | | | | | | | | | | | | | | -| AC8 | | High Performance | IO_L3N_T0L_N5_AD15N_64 | User IO | | 64 | | | | | | | | | | | | | | | -| AC9 | | High Performance | IO_L1P_T0L_N0_DBC_64 | User IO | | 64 | | | | | | | | | | | | | | | -| AC10 | | High Density | VCCO_44 | VCCO | | 44 | | | | | | 3.30 | | | | | | | | | -| AC11 | | High Density | IO_L8N_HDGC_AD4N_44 | GCLK | | 44 | | | | | | | | | | | | | | | -| AC12 | HDMI_CK_N | High Density | IO_L6P_HDGC_AD6P_44 | OUTPUT | LVCMOS33 | 44 | 12 | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| AC13 | | High Density | IO_L6N_HDGC_24 | GCLK | | 24 | | | | | | | | | | | | | | | -| AC14 | | High Density | IO_L6P_HDGC_24 | GCLK | | 24 | | | | | | | | | | | | | | | -| AC15 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| AC16 | | | PS_MIO9_500 | PSS IO | | | | | | | | | | | | | | | | | -| AC17 | | | PS_MIO12_500 | PSS IO | | | | | | | | | | | | | | | | | -| AC18 | | | PS_MIO17_500 | PSS IO | | | | | | | | | | | | | | | | | -| AC19 | | | PS_MIO18_500 | PSS IO | | | | | | | | | | | | | | | | | -| AC20 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| AC21 | | | PS_MIO21_500 | PSS IO | | | | | | | | | | | | | | | | | -| AC22 | | | PS_DDR_A17_504 | PSS IO | | | | | | | | | | | | | | | | | -| AC23 | | | PS_DDR_A16_504 | PSS IO | | | | | | | | | | | | | | | | | -| AC24 | | | PS_DDR_A15_504 | PSS IO | | | | | | | | | | | | | | | | | -| AC25 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| AC26 | | | PS_DDR_DQ16_504 | PSS IO | | | | | | | | | | | | | | | | | -| AC27 | | | PS_DDR_DQ28_504 | PSS IO | | | | | | | | | | | | | | | | | -| AC28 | | | PS_DDR_DQ31_504 | PSS IO | | | | | | | | | | | | | | | | | -| AD1 | | High Performance | IO_L16N_T2U_N7_QBC_AD3N_64 | User IO | | 64 | | | | | | | | | | | | | | | -| AD2 | | High Performance | IO_L16P_T2U_N6_QBC_AD3P_64 | User IO | | 64 | | | | | | | | | | | | | | | -| AD3 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| AD4 | | High Performance | IO_L13N_T2L_N1_GC_QBC_64 | GCLK | | 64 | | | | | | | | | | | | | | | -| AD5 | | High Performance | IO_L13P_T2L_N0_GC_QBC_64 | GCLK | | 64 | | | | | | | | | | | | | | | -| AD6 | | High Performance | IO_T0U_N12_VRP_64 | User IO | | 64 | | | | | | | | | | | | | | | -| AD7 | | High Performance | IO_L4P_T0U_N6_DBC_AD7P_64 | User IO | | 64 | | | | | | | | | | | | | | | -| AD8 | | High Performance | VCCO_64 | VCCO | | 64 | | | | | | 1.20 | | | | | | | | | -| AD9 | | High Performance | IO_L1N_T0L_N1_DBC_64 | User IO | | 64 | | | | | | | | | | | | | | | -| AD10 | | High Density | IO_L7N_HDGC_AD5N_44 | GCLK | | 44 | | | | | | | | | | | | | | | -| AD11 | | High Density | IO_L7P_HDGC_AD5P_44 | GCLK | | 44 | | | | | | | | | | | | | | | -| AD12 | HDMI_CK_P | High Density | IO_L6N_HDGC_AD6N_44 | OUTPUT | LVCMOS33 | 44 | 12 | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| AD13 | | High Density | VCCO_24 | VCCO | | 24 | | | | | | any** | | | | | | | | | -| AD14 | | High Density | IO_L5N_HDGC_24 | GCLK | | 24 | | | | | | | | | | | | | | | -| AD15 | | High Density | IO_L5P_HDGC_24 | GCLK | | 24 | | | | | | | | | | | | | | | -| AD16 | | | PS_MIO5_500 | PSS IO | | | | | | | | | | | | | | | | | -| AD17 | | | PS_MIO10_500 | PSS IO | | | | | | | | | | | | | | | | | -| AD18 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| AD19 | | | PS_MIO20_500 | PSS IO | | | | | | | | | | | | | | | | | -| AD20 | | | PS_DDR_DQ2_504 | PSS IO | | | | | | | | | | | | | | | | | -| AD21 | | | PS_DDR_DQ0_504 | PSS IO | | | | | | | | | | | | | | | | | -| AD22 | | | PS_DDR_DQ11_504 | PSS IO | | | | | | | | | | | | | | | | | -| AD23 | | | VCCO_PSDDR_504 | VCCO | | | | | | | | any** | | | | | | | | | -| AD24 | | | PS_DDR_DQ19_504 | PSS IO | | | | | | | | | | | | | | | | | -| AD25 | | | PS_DDR_DQ18_504 | PSS IO | | | | | | | | | | | | | | | | | -| AD26 | | | PS_DDR_DQ17_504 | PSS IO | | | | | | | | | | | | | | | | | -| AD27 | | | PS_DDR_DQ29_504 | PSS IO | | | | | | | | | | | | | | | | | -| AD28 | | | PS_DDR_DQ30_504 | PSS IO | | | | | | | | | | | | | | | | | -| AE1 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| AE2 | | High Performance | IO_L22P_T3U_N6_DBC_AD0P_64 | User IO | | 64 | | | | | | | | | | | | | | | -| AE3 | | High Performance | IO_L21P_T3L_N4_AD8P_64 | User IO | | 64 | | | | | | | | | | | | | | | -| AE4 | | High Performance | IO_T3U_N12_64 | User IO | | 64 | | | | | | | | | | | | | | | -| AE5 | | High Performance | IO_L12P_T1U_N10_GC_64 | GCLK | | 64 | | | | | | | | | | | | | | | -| AE6 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| AE7 | PL_USER_LED[1] | High Performance | IO_L4N_T0U_N7_DBC_AD7N_64 | OUTPUT | LVCMOS12 | 64 | 8 | | SLOW | | NONE | | FIXED | | | | NONE | | | | -| AE8 | | High Performance | IO_L2N_T0L_N3_64 | User IO | | 64 | | | | | | | | | | | | | | | -| AE9 | | High Performance | IO_L2P_T0L_N2_64 | User IO | | 64 | | | | | | | | | | | | | | | -| AE10 | HDMI_D0_N | High Density | IO_L4P_AD8P_44 | OUTPUT | LVCMOS33 | 44 | 12 | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| AE11 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| AE12 | | High Density | IO_L5P_HDGC_AD7P_44 | GCLK | | 44 | | | | | | | | | | | | | | | -| AE13 | | High Density | IO_L4P_AD12P_24 | User IO | | 24 | | | | | | | | | | | | | | | -| AE14 | | High Density | IO_L1N_AD15N_24 | User IO | | 24 | | | | | | | | | | | | | | | -| AE15 | | High Density | IO_L1P_AD15P_24 | User IO | | 24 | | | | | | | | | | | | | | | -| AE16 | | | VCCO_PSIO0_500 | VCCO | | | | | | | | any** | | | | | | | | | -| AE17 | | | PS_MIO11_500 | PSS IO | | | | | | | | | | | | | | | | | -| AE18 | | | PS_MIO15_500 | PSS IO | | | | | | | | | | | | | | | | | -| AE19 | | | PS_MIO19_500 | PSS IO | | | | | | | | | | | | | | | | | -| AE20 | | | PS_DDR_DQ1_504 | PSS IO | | | | | | | | | | | | | | | | | -| AE21 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| AE22 | | | PS_DDR_DQ10_504 | PSS IO | | | | | | | | | | | | | | | | | -| AE23 | | | PS_DDR_DM1_504 | PSS IO | | | | | | | | | | | | | | | | | -| AE24 | | | PS_DDR_DQ14_504 | PSS IO | | | | | | | | | | | | | | | | | -| AE25 | | | PS_DDR_DM2_504 | PSS IO | | | | | | | | | | | | | | | | | -| AE26 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| AE27 | | | PS_DDR_DQS_P3_504 | PSS IO | | | | | | | | | | | | | | | | | -| AE28 | | | PS_DDR_DM3_504 | PSS IO | | | | | | | | | | | | | | | | | -| AF1 | | High Performance | IO_L24P_T3U_N10_64 | User IO | | 64 | | | | | | | | | | | | | | | -| AF2 | | High Performance | IO_L22N_T3U_N7_DBC_AD0N_64 | User IO | | 64 | | | | | | | | | | | | | | | -| AF3 | | High Performance | IO_L21N_T3L_N5_AD8N_64 | User IO | | 64 | | | | | | | | | | | | | | | -| AF4 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| AF5 | PL_USER_LED[0] | High Performance | IO_L12N_T1U_N11_GC_64 | OUTPUT | LVCMOS12 | 64 | 8 | | SLOW | | NONE | | FIXED | | | | NONE | | | | -| AF6 | | High Performance | IO_L11N_T1U_N9_GC_64 | GCLK | | 64 | | | | | | | | | | | | | | | -| AF7 | | High Performance | IO_L11P_T1U_N8_GC_64 | GCLK | | 64 | | | | | | | | | | | | | | | -| AF8 | | High Performance | IO_L8P_T1L_N2_AD5P_64 | User IO | | 64 | | | | | | | | | | | | | | | -| AF9 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| AF10 | HDMI_D0_P | High Density | IO_L4N_AD8N_44 | OUTPUT | LVCMOS33 | 44 | 12 | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| AF11 | HDMI_D2_P | High Density | IO_L2P_AD10P_44 | OUTPUT | LVCMOS33 | 44 | 12 | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| AF12 | | High Density | IO_L5N_HDGC_AD7N_44 | GCLK | | 44 | | | | | | | | | | | | | | | -| AF13 | | High Density | IO_L4N_AD12N_24 | User IO | | 24 | | | | | | | | | | | | | | | -| AF14 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| AF15 | | | PS_MIO2_500 | PSS IO | | | | | | | | | | | | | | | | | -| AF16 | | | PS_MIO6_500 | PSS IO | | | | | | | | | | | | | | | | | -| AF17 | | | PS_MIO8_500 | PSS IO | | | | | | | | | | | | | | | | | -| AF18 | | | PS_MIO16_500 | PSS IO | | | | | | | | | | | | | | | | | -| AF19 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| AF20 | | | PS_DDR_DQ3_504 | PSS IO | | | | | | | | | | | | | | | | | -| AF21 | | | PS_DDR_DQS_P0_504 | PSS IO | | | | | | | | | | | | | | | | | -| AF22 | | | PS_DDR_DQ8_504 | PSS IO | | | | | | | | | | | | | | | | | -| AF23 | | | PS_DDR_DQS_P1_504 | PSS IO | | | | | | | | | | | | | | | | | -| AF24 | | | VCCO_PSDDR_504 | VCCO | | | | | | | | any** | | | | | | | | | -| AF25 | | | PS_DDR_DQS_P2_504 | PSS IO | | | | | | | | | | | | | | | | | -| AF26 | | | PS_DDR_DQS_N2_504 | PSS IO | | | | | | | | | | | | | | | | | -| AF27 | | | PS_DDR_DQS_N3_504 | PSS IO | | | | | | | | | | | | | | | | | -| AF28 | | | PS_DDR_DQ26_504 | PSS IO | | | | | | | | | | | | | | | | | -| AG1 | | High Performance | IO_L24N_T3U_N11_64 | User IO | | 64 | | | | | | | | | | | | | | | -| AG2 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| AG3 | | High Performance | IO_L20P_T3L_N2_AD1P_64 | User IO | | 64 | | | | | | | | | | | | | | | -| AG4 | | High Performance | IO_L19P_T3L_N0_DBC_AD9P_64 | User IO | | 64 | | | | | | | | | | | | | | | -| AG5 | | High Performance | IO_L10N_T1U_N7_QBC_AD4N_64 | User IO | | 64 | | | | | | | | | | | | | | | -| AG6 | | High Performance | IO_L10P_T1U_N6_QBC_AD4P_64 | User IO | | 64 | | | | | | | | | | | | | | | -| AG7 | | High Performance | VCCO_64 | VCCO | | 64 | | | | | | 1.20 | | | | | | | | | -| AG8 | | High Performance | IO_L8N_T1L_N3_AD5N_64 | User IO | | 64 | | | | | | | | | | | | | | | -| AG9 | | High Performance | IO_L7P_T1L_N0_QBC_AD13P_64 | User IO | | 64 | | | | | | | | | | | | | | | -| AG10 | | High Density | IO_L1P_AD11P_44 | User IO | | 44 | | | | | | | | | | | | | | | -| AG11 | HDMI_D2_N | High Density | IO_L2N_AD10N_44 | OUTPUT | LVCMOS33 | 44 | 12 | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| AG12 | | High Density | VCCO_44 | VCCO | | 44 | | | | | | 3.30 | | | | | | | | | -| AG13 | | High Density | IO_L3P_AD13P_24 | User IO | | 24 | | | | | | | | | | | | | | | -| AG14 | | High Density | IO_L2P_AD14P_24 | User IO | | 24 | | | | | | | | | | | | | | | -| AG15 | | | PS_MIO0_500 | PSS IO | | | | | | | | | | | | | | | | | -| AG16 | | | PS_MIO1_500 | PSS IO | | | | | | | | | | | | | | | | | -| AG17 | | | VCCO_PSIO0_500 | VCCO | | | | | | | | any** | | | | | | | | | -| AG18 | | | PS_MIO14_500 | PSS IO | | | | | | | | | | | | | | | | | -| AG19 | | | PS_DDR_DQ7_504 | PSS IO | | | | | | | | | | | | | | | | | -| AG20 | | | PS_DDR_DM0_504 | PSS IO | | | | | | | | | | | | | | | | | -| AG21 | | | PS_DDR_DQS_N0_504 | PSS IO | | | | | | | | | | | | | | | | | -| AG22 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| AG23 | | | PS_DDR_DQS_N1_504 | PSS IO | | | | | | | | | | | | | | | | | -| AG24 | | | PS_DDR_DQ15_504 | PSS IO | | | | | | | | | | | | | | | | | -| AG25 | | | PS_DDR_DQ23_504 | PSS IO | | | | | | | | | | | | | | | | | -| AG26 | | | PS_DDR_DQ20_504 | PSS IO | | | | | | | | | | | | | | | | | -| AG27 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| AG28 | | | PS_DDR_DQ27_504 | PSS IO | | | | | | | | | | | | | | | | | -| AH1 | | High Performance | IO_L23N_T3U_N9_64 | User IO | | 64 | | | | | | | | | | | | | | | -| AH2 | PL_USER_LED[2] | High Performance | IO_L23P_T3U_N8_64 | OUTPUT | LVCMOS12 | 64 | 8 | | SLOW | | NONE | | FIXED | | | | NONE | | | | -| AH3 | | High Performance | IO_L20N_T3L_N3_AD1N_64 | User IO | | 64 | | | | | | | | | | | | | | | -| AH4 | | High Performance | IO_L19N_T3L_N1_DBC_AD9N_64 | User IO | | 64 | | | | | | | | | | | | | | | -| AH5 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| AH6 | | High Performance | IO_T1U_N12_64 | User IO | | 64 | | | | | | | | | | | | | | | -| AH7 | | High Performance | IO_L9N_T1L_N5_AD12N_64 | User IO | | 64 | | | | | | | | | | | | | | | -| AH8 | | High Performance | IO_L9P_T1L_N4_AD12P_64 | User IO | | 64 | | | | | | | | | | | | | | | -| AH9 | | High Performance | IO_L7N_T1L_N1_QBC_AD13N_64 | User IO | | 64 | | | | | | | | | | | | | | | -| AH10 | | High Density | IO_L1N_AD11N_44 | User IO | | 44 | | | | | | | | | | | | | | | -| AH11 | HDMI_D1_P | High Density | IO_L3N_AD9N_44 | OUTPUT | LVCMOS33 | 44 | 12 | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| AH12 | HDMI_D1_N | High Density | IO_L3P_AD9P_44 | OUTPUT | LVCMOS33 | 44 | 12 | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| AH13 | | High Density | IO_L3N_AD13N_24 | User IO | | 24 | | | | | | | | | | | | | | | -| AH14 | | High Density | IO_L2N_AD14N_24 | User IO | | 24 | | | | | | | | | | | | | | | -| AH15 | | | PS_MIO3_500 | PSS IO | | | | | | | | | | | | | | | | | -| AH16 | | | PS_MIO4_500 | PSS IO | | | | | | | | | | | | | | | | | -| AH17 | | | PS_MIO7_500 | PSS IO | | | | | | | | | | | | | | | | | -| AH18 | | | PS_MIO13_500 | PSS IO | | | | | | | | | | | | | | | | | -| AH19 | | | PS_DDR_DQ6_504 | PSS IO | | | | | | | | | | | | | | | | | -| AH20 | | | PS_DDR_DQ5_504 | PSS IO | | | | | | | | | | | | | | | | | -| AH21 | | | PS_DDR_DQ4_504 | PSS IO | | | | | | | | | | | | | | | | | -| AH22 | | | PS_DDR_DQ9_504 | PSS IO | | | | | | | | | | | | | | | | | -| AH23 | | | PS_DDR_DQ12_504 | PSS IO | | | | | | | | | | | | | | | | | -| AH24 | | | PS_DDR_DQ13_504 | PSS IO | | | | | | | | | | | | | | | | | -| AH25 | | | PS_DDR_DQ21_504 | PSS IO | | | | | | | | | | | | | | | | | -| AH26 | | | PS_DDR_DQ22_504 | PSS IO | | | | | | | | | | | | | | | | | -| AH27 | | | PS_DDR_DQ24_504 | PSS IO | | | | | | | | | | | | | | | | | -| AH28 | | | PS_DDR_DQ25_504 | PSS IO | | | | | | | | | | | | | | | | | -| B1 | | High Performance | IO_L7N_T1L_N1_QBC_AD13N_66 | User IO | | 66 | | | | | | | | | | | | | | | -| B2 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| B3 | | High Performance | IO_L9P_T1L_N4_AD12P_66 | User IO | | 66 | | | | | | | | | | | | | | | -| B4 | | High Performance | IO_L10P_T1U_N6_QBC_AD4P_66 | User IO | | 66 | | | | | | | | | | | | | | | -| B5 | | High Performance | IO_L19P_T3L_N0_DBC_AD9P_66 | User IO | | 66 | | | | | | | | | | | | | | | -| B6 | | High Performance | IO_L20N_T3L_N3_AD1N_66 | User IO | | 66 | | | | | | | | | | | | | | | -| B7 | | High Performance | VCCO_66 | VCCO | | 66 | | | | | | 0.00-1.80 | | | | | | | | | -| B8 | | High Performance | IO_L22N_T3U_N7_DBC_AD0N_66 | User IO | | 66 | | | | | | | | | | | | | | | -| B9 | | High Performance | IO_L24N_T3U_N11_66 | User IO | | 66 | | | | | | | | | | | | | | | -| B10 | | High Density | IO_L9N_AD11N_25 | User IO | | 25 | | | | | | | | | | | | | | | -| B11 | | High Density | IO_L10P_AD10P_25 | User IO | | 25 | | | | | | | | | | | | | | | -| B12 | | High Density | VCCO_25 | VCCO | | 25 | | | | | | any** | | | | | | | | | -| B13 | | High Density | IO_L3P_AD9P_26 | User IO | | 26 | | | | | | | | | | | | | | | -| B14 | | High Density | IO_L2P_AD10P_26 | User IO | | 26 | | | | | | | | | | | | | | | -| B15 | | High Density | IO_L1P_AD11P_26 | User IO | | 26 | | | | | | | | | | | | | | | -| B16 | | | PS_MIO55_502 | PSS IO | | | | | | | | | | | | | | | | | -| B17 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| B18 | | | PS_MIO67_502 | PSS IO | | | | | | | | | | | | | | | | | -| B19 | | | PS_MIO71_502 | PSS IO | | | | | | | | | | | | | | | | | -| B20 | | | PS_MIO76_502 | PSS IO | | | | | | | | | | | | | | | | | -| B21 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| B22 | | | PS_MGTRAVCC | PSS IO | | | | | | | | | | | | | | | | | -| B23 | | | PS_MGTRTXP3_505 | PSS IO | | | | | | | | | | | | | | | | | -| B24 | | | PS_MGTRTXN3_505 | PSS IO | | | | | | | | | | | | | | | | | -| B25 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| B26 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| B27 | | | PS_MGTRRXP2_505 | PSS IO | | | | | | | | | | | | | | | | | -| B28 | | | PS_MGTRRXN2_505 | PSS IO | | | | | | | | | | | | | | | | | -| C1 | | High Performance | IO_L7P_T1L_N0_QBC_AD13P_66 | User IO | | 66 | | | | | | | | | | | | | | | -| C2 | | High Performance | IO_L12N_T1U_N11_GC_66 | GCLK | | 66 | | | | | | | | | | | | | | | -| C3 | | High Performance | IO_L12P_T1U_N10_GC_66 | GCLK | | 66 | | | | | | | | | | | | | | | -| C4 | | High Performance | IO_L11N_T1U_N9_GC_66 | GCLK | | 66 | | | | | | | | | | | | | | | -| C5 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| C6 | | High Performance | IO_L20P_T3L_N2_AD1P_66 | User IO | | 66 | | | | | | | | | | | | | | | -| C7 | | High Performance | IO_T3U_N12_66 | User IO | | 66 | | | | | | | | | | | | | | | -| C8 | | High Performance | IO_L22P_T3U_N6_DBC_AD0P_66 | User IO | | 66 | | | | | | | | | | | | | | | -| C9 | | High Performance | IO_L24P_T3U_N10_66 | User IO | | 66 | | | | | | | | | | | | | | | -| C10 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| C11 | | High Density | IO_L9P_AD11P_25 | User IO | | 25 | | | | | | | | | | | | | | | -| C12 | | High Density | IO_L12N_AD8N_25 | User IO | | 25 | | | | | | | | | | | | | | | -| C13 | | High Density | IO_L4N_AD8N_26 | User IO | | 26 | | | | | | | | | | | | | | | -| C14 | | High Density | IO_L4P_AD8P_26 | User IO | | 26 | | | | | | | | | | | | | | | -| C15 | | High Density | VCCO_26 | VCCO | | 26 | | | | | | any** | | | | | | | | | -| C16 | | | PS_MIO56_502 | PSS IO | | | | | | | | | | | | | | | | | -| C17 | | | PS_MIO60_502 | PSS IO | | | | | | | | | | | | | | | | | -| C18 | | | PS_MIO68_502 | PSS IO | | | | | | | | | | | | | | | | | -| C19 | | | PS_MIO70_502 | PSS IO | | | | | | | | | | | | | | | | | -| C20 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| C21 | | | PS_MGTREFCLK2P_505 | PSS IO | | | | | | | | | | | | | | | | | -| C22 | | | PS_MGTREFCLK2N_505 | PSS IO | | | | | | | | | | | | | | | | | -| C23 | | | PS_MGTRAVTT | PSS IO | | | | | | | | | | | | | | | | | -| C24 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| C25 | | | PS_MGTRTXP2_505 | PSS IO | | | | | | | | | | | | | | | | | -| C26 | | | PS_MGTRTXN2_505 | PSS IO | | | | | | | | | | | | | | | | | -| C27 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| C28 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| D1 | | High Performance | IO_L2N_T0L_N3_66 | User IO | | 66 | | | | | | | | | | | | | | | -| D2 | | High Performance | IO_T1U_N12_66 | User IO | | 66 | | | | | | | | | | | | | | | -| D3 | | High Performance | VCCO_66 | VCCO | | 66 | | | | | | 0.00-1.80 | | | | | | | | | -| D4 | | High Performance | IO_L11P_T1U_N8_GC_66 | GCLK | | 66 | | | | | | | | | | | | | | | -| D5 | | High Performance | IO_L14N_T2L_N3_GC_66 | GCLK | | 66 | | | | | | | | | | | | | | | -| D6 | clk_100mhz_clk_n | High Performance | IO_L13N_T2L_N1_GC_QBC_66 | INPUT | LVDS | 66 | | | | NONE | NONE | | FIXED | | | | NONE | | FALSE | EQ_NONE | -| D7 | clk_100mhz_clk_p | High Performance | IO_L13P_T2L_N0_GC_QBC_66 | INPUT | LVDS | 66 | | | | NONE | NONE | | FIXED | | | | NONE | | FALSE | EQ_NONE | -| D8 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| D9 | | High Performance | IO_L18N_T2U_N11_AD2N_66 | User IO | | 66 | | | | | | | | | | | | | | | -| D10 | | High Density | IO_L7N_HDGC_25 | GCLK | | 25 | | | | | | | | | | | | | | | -| D11 | | High Density | IO_L8N_HDGC_25 | GCLK | | 25 | | | | | | | | | | | | | | | -| D12 | | High Density | IO_L12P_AD8P_25 | User IO | | 25 | | | | | | | | | | | | | | | -| D13 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| D14 | | High Density | IO_L5N_HDGC_AD7N_26 | GCLK | | 26 | | | | | | | | | | | | | | | -| D15 | | High Density | IO_L5P_HDGC_AD7P_26 | GCLK | | 26 | | | | | | | | | | | | | | | -| D16 | | | PS_MIO53_502 | PSS IO | | | | | | | | | | | | | | | | | -| D17 | | | PS_MIO61_502 | PSS IO | | | | | | | | | | | | | | | | | -| D18 | | | VCCO_PSIO2_502 | VCCO | | | | | | | | any** | | | | | | | | | -| D19 | | | PS_MIO69_502 | PSS IO | | | | | | | | | | | | | | | | | -| D20 | | | PS_MIO74_502 | PSS IO | | | | | | | | | | | | | | | | | -| D21 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| D22 | | | PS_MGTRAVCC | PSS IO | | | | | | | | | | | | | | | | | -| D23 | | | PS_MGTRTXP1_505 | PSS IO | | | | | | | | | | | | | | | | | -| D24 | | | PS_MGTRTXN1_505 | PSS IO | | | | | | | | | | | | | | | | | -| D25 | | | PS_MGTRAVTT | PSS IO | | | | | | | | | | | | | | | | | -| D26 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| D27 | | | PS_MGTRRXP1_505 | PSS IO | | | | | | | | | | | | | | | | | -| D28 | | | PS_MGTRRXN1_505 | PSS IO | | | | | | | | | | | | | | | | | -| E1 | | High Performance | IO_L2P_T0L_N2_66 | User IO | | 66 | | | | | | | | | | | | | | | -| E2 | | High Performance | IO_L3N_T0L_N5_AD15N_66 | User IO | | 66 | | | | | | | | | | | | | | | -| E3 | | High Performance | IO_L5N_T0U_N9_AD14N_66 | User IO | | 66 | | | | | | | | | | | | | | | -| E4 | | High Performance | IO_L5P_T0U_N8_AD14P_66 | User IO | | 66 | | | | | | | | | | | | | | | -| E5 | | High Performance | IO_L14P_T2L_N2_GC_66 | GCLK | | 66 | | | | | | | | | | | | | | | -| E6 | | High Performance | VCCO_66 | VCCO | | 66 | | | | | | 0.00-1.80 | | | | | | | | | -| E7 | | High Performance | IO_T2U_N12_66 | User IO | | 66 | | | | | | | | | | | | | | | -| E8 | | High Performance | IO_L17N_T2U_N9_AD10N_66 | User IO | | 66 | | | | | | | | | | | | | | | -| E9 | | High Performance | IO_L18P_T2U_N10_AD2P_66 | User IO | | 66 | | | | | | | | | | | | | | | -| E10 | | High Density | IO_L7P_HDGC_25 | GCLK | | 25 | | | | | | | | | | | | | | | -| E11 | | High Density | VCCO_25 | VCCO | | 25 | | | | | | any** | | | | | | | | | -| E12 | | High Density | IO_L8P_HDGC_25 | GCLK | | 25 | | | | | | | | | | | | | | | -| E13 | | High Density | IO_L6N_HDGC_AD6N_26 | GCLK | | 26 | | | | | | | | | | | | | | | -| E14 | | High Density | IO_L6P_HDGC_AD6P_26 | GCLK | | 26 | | | | | | | | | | | | | | | -| E15 | | High Density | IO_L8N_HDGC_AD4N_26 | GCLK | | 26 | | | | | | | | | | | | | | | -| E16 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| E17 | | | PS_MIO59_502 | PSS IO | | | | | | | | | | | | | | | | | -| E18 | | | PS_MIO63_502 | PSS IO | | | | | | | | | | | | | | | | | -| E19 | | | PS_MIO64_502 | PSS IO | | | | | | | | | | | | | | | | | -| E20 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| E21 | | | PS_MGTREFCLK1P_505 | PSS IO | | | | | | | | | | | | | | | | | -| E22 | | | PS_MGTREFCLK1N_505 | PSS IO | | | | | | | | | | | | | | | | | -| E23 | | | PS_MGTRAVTT | PSS IO | | | | | | | | | | | | | | | | | -| E24 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| E25 | | | PS_MGTRTXP0_505 | PSS IO | | | | | | | | | | | | | | | | | -| E26 | | | PS_MGTRTXN0_505 | PSS IO | | | | | | | | | | | | | | | | | -| E27 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| E28 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| F1 | | High Performance | IO_L1N_T0L_N1_DBC_66 | User IO | | 66 | | | | | | | | | | | | | | | -| F2 | | High Performance | IO_L3P_T0L_N4_AD15P_66 | User IO | | 66 | | | | | | | | | | | | | | | -| F3 | | High Performance | IO_L4N_T0U_N7_DBC_AD7N_66 | User IO | | 66 | | | | | | | | | | | | | | | -| F4 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| F5 | | High Performance | IO_L6N_T0U_N11_AD6N_66 | User IO | | 66 | | | | | | | | | | | | | | | -| F6 | | High Performance | IO_L15N_T2L_N5_AD11N_66 | User IO | | 66 | | | | | | | | | | | | | | | -| F7 | | High Performance | IO_L16N_T2U_N7_QBC_AD3N_66 | User IO | | 66 | | | | | | | | | | | | | | | -| F8 | | High Performance | IO_L17P_T2U_N8_AD10P_66 | User IO | | 66 | | | | | | | | | | | | | | | -| F9 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| F10 | | High Density | IO_L5N_HDGC_25 | GCLK | | 25 | | | | | | | | | | | | | | | -| F11 | | High Density | IO_L6N_HDGC_25 | GCLK | | 25 | | | | | | | | | | | | | | | -| F12 | | High Density | IO_L6P_HDGC_25 | GCLK | | 25 | | | | | | | | | | | | | | | -| F13 | | High Density | IO_L7N_HDGC_AD5N_26 | GCLK | | 26 | | | | | | | | | | | | | | | -| F14 | | High Density | VCCO_26 | VCCO | | 26 | | | | | | any** | | | | | | | | | -| F15 | | High Density | IO_L8P_HDGC_AD4P_26 | GCLK | | 26 | | | | | | | | | | | | | | | -| F16 | | | PS_MIO30_501 | PSS IO | | | | | | | | | | | | | | | | | -| F17 | | | PS_MIO54_502 | PSS IO | | | | | | | | | | | | | | | | | -| F18 | | | PS_MIO58_502 | PSS IO | | | | | | | | | | | | | | | | | -| F19 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| F20 | | | PS_MIO77_502 | PSS IO | | | | | | | | | | | | | | | | | -| F21 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| F22 | | | PS_MGTRREF_505 | PSS IO | | | | | | | | | | | | | | | | | -| F23 | | | PS_MGTREFCLK0P_505 | PSS IO | | | | | | | | | | | | | | | | | -| F24 | | | PS_MGTREFCLK0N_505 | PSS IO | | | | | | | | | | | | | | | | | -| F25 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| F26 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| F27 | | | PS_MGTRRXP0_505 | PSS IO | | | | | | | | | | | | | | | | | -| F28 | | | PS_MGTRRXN0_505 | PSS IO | | | | | | | | | | | | | | | | | -| G1 | | High Performance | IO_L1P_T0L_N0_DBC_66 | User IO | | 66 | | | | | | | | | | | | | | | -| G2 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| G3 | | High Performance | IO_L4P_T0U_N6_DBC_AD7P_66 | User IO | | 66 | | | | | | | | | | | | | | | -| G4 | | High Performance | IO_T0U_N12_VRP_66 | User IO | | 66 | | | | | | | | | | | | | | | -| G5 | | High Performance | IO_L6P_T0U_N10_AD6P_66 | User IO | | 66 | | | | | | | | | | | | | | | -| G6 | | High Performance | IO_L15P_T2L_N4_AD11P_66 | User IO | | 66 | | | | | | | | | | | | | | | -| G7 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| G8 | | High Performance | IO_L16P_T2U_N6_QBC_AD3P_66 | User IO | | 66 | | | | | | | | | | | | | | | -| G9 | | High Performance | VREF_66 | Voltage | | 66 | | | | | | | | | | | | | | | -| G10 | | High Density | IO_L3N_AD13N_25 | User IO | | 25 | | | | | | | | | | | | | | | -| G11 | | High Density | IO_L5P_HDGC_25 | GCLK | | 25 | | | | | | | | | | | | | | | -| G12 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| G13 | | High Density | IO_L7P_HDGC_AD5P_26 | GCLK | | 26 | | | | | | | | | | | | | | | -| G14 | | High Density | IO_L9N_AD3N_26 | User IO | | 26 | | | | | | | | | | | | | | | -| G15 | | High Density | IO_L9P_AD3P_26 | User IO | | 26 | | | | | | | | | | | | | | | -| G16 | | | PS_MIO29_501 | PSS IO | | | | | | | | | | | | | | | | | -| G17 | | | VCCO_PSIO2_502 | VCCO | | | | | | | | any** | | | | | | | | | -| G18 | | | PS_MIO52_502 | PSS IO | | | | | | | | | | | | | | | | | -| G19 | | | PS_MIO66_502 | PSS IO | | | | | | | | | | | | | | | | | -| G20 | | | PS_MIO72_502 | PSS IO | | | | | | | | | | | | | | | | | -| G21 | | | PS_MIO73_502 | PSS IO | | | | | | | | | | | | | | | | | -| G22 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| G23 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| G24 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| G25 | | | PS_DDR_DQ61_504 | PSS IO | | | | | | | | | | | | | | | | | -| G26 | | | PS_DDR_DQ60_504 | PSS IO | | | | | | | | | | | | | | | | | -| G27 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| G28 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| H1 | | High Performance | IO_L8N_T1L_N3_AD5N_65 | User IO | | 65 | | | | | | | | | | | | | | | -| H2 | | High Performance | IO_T1U_N12_65 | User IO | | 65 | | | | | | | | | | | | | | | -| H3 | | High Performance | IO_L10N_T1U_N7_QBC_AD4N_65 | User IO | | 65 | | | | | | | | | | | | | | | -| H4 | | High Performance | IO_L10P_T1U_N6_QBC_AD4P_65 | User IO | | 65 | | | | | | | | | | | | | | | -| H5 | | High Performance | VCCO_65 | VCCO | | 65 | | | | | | 0.00-1.80 | | | | | | | | | -| H6 | | High Performance | IO_L20N_T3L_N3_AD1N_65 | User IO | | 65 | | | | | | | | | | | | | | | -| H7 | | High Performance | IO_L21N_T3L_N5_AD8N_65 | User IO | | 65 | | | | | | | | | | | | | | | -| H8 | | High Performance | IO_L24N_T3U_N11_PERSTN0_65 | User IO | | 65 | | | | | | | | | | | | | | | -| H9 | | High Performance | IO_L24P_T3U_N10_PERSTN1_I2C_SDA_65 | User IO | | 65 | | | | | | | | | | | | | | | -| H10 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| H11 | | High Density | IO_L3P_AD13P_25 | User IO | | 25 | | | | | | | | | | | | | | | -| H12 | | High Density | IO_L4N_AD12N_25 | User IO | | 25 | | | | | | | | | | | | | | | -| H13 | | High Density | IO_L10N_AD2N_26 | User IO | | 26 | | | | | | | | | | | | | | | -| H14 | | High Density | IO_L10P_AD2P_26 | User IO | | 26 | | | | | | | | | | | | | | | -| H15 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| H16 | | | PS_MIO31_501 | PSS IO | | | | | | | | | | | | | | | | | -| H17 | | | PS_MIO35_501 | PSS IO | | | | | | | | | | | | | | | | | -| H18 | | | PS_MIO38_501 | PSS IO | | | | | | | | | | | | | | | | | -| H19 | | | PS_MIO39_501 | PSS IO | | | | | | | | | | | | | | | | | -| H20 | | | VCCO_PSIO1_501 | VCCO | | | | | | | | any** | | | | | | | | | -| H21 | | | PS_MIO47_501 | PSS IO | | | | | | | | | | | | | | | | | -| H22 | | | PS_DDR_DQ45_504 | PSS IO | | | | | | | | | | | | | | | | | -| H23 | | | PS_DDR_DM5_504 | PSS IO | | | | | | | | | | | | | | | | | -| H24 | | | PS_DDR_DQ40_504 | PSS IO | | | | | | | | | | | | | | | | | -| H25 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| H26 | | | PS_DDR_DM7_504 | PSS IO | | | | | | | | | | | | | | | | | -| H27 | | | PS_DDR_DQ59_504 | PSS IO | | | | | | | | | | | | | | | | | -| H28 | | | PS_DDR_DQ58_504 | PSS IO | | | | | | | | | | | | | | | | | -| J1 | | High Performance | IO_L8P_T1L_N2_AD5P_65 | User IO | | 65 | | | | | | | | | | | | | | | -| J2 | | High Performance | IO_L9N_T1L_N5_AD12N_65 | User IO | | 65 | | | | | | | | | | | | | | | -| J3 | | High Performance | VCCO_65 | VCCO | | 65 | | | | | | 0.00-1.80 | | | | | | | | | -| J4 | | High Performance | IO_L19N_T3L_N1_DBC_AD9N_65 | User IO | | 65 | | | | | | | | | | | | | | | -| J5 | | High Performance | IO_L19P_T3L_N0_DBC_AD9P_65 | User IO | | 65 | | | | | | | | | | | | | | | -| J6 | | High Performance | IO_L20P_T3L_N2_AD1P_65 | User IO | | 65 | | | | | | | | | | | | | | | -| J7 | | High Performance | IO_L21P_T3L_N4_AD8P_65 | User IO | | 65 | | | | | | | | | | | | | | | -| J8 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| J9 | | High Performance | IO_L23N_T3U_N9_65 | User IO | | 65 | | | | | | | | | | | | | | | -| J10 | | High Density | IO_L1N_AD15N_25 | User IO | | 25 | | | | | | | | | | | | | | | -| J11 | | High Density | IO_L1P_AD15P_25 | User IO | | 25 | | | | | | | | | | | | | | | -| J12 | | High Density | IO_L4P_AD12P_25 | User IO | | 25 | | | | | | | | | | | | | | | -| J13 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| J14 | | High Density | IO_L11N_AD1N_26 | User IO | | 26 | | | | | | | | | | | | | | | -| J15 | | | PS_MIO27_501 | PSS IO | | | | | | | | | | | | | | | | | -| J16 | | | PS_MIO32_501 | PSS IO | | | | | | | | | | | | | | | | | -| J17 | | | PS_MIO37_501 | PSS IO | | | | | | | | | | | | | | | | | -| J18 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| J19 | | | PS_MIO41_501 | PSS IO | | | | | | | | | | | | | | | | | -| J20 | | | PS_MIO44_501 | PSS IO | | | | | | | | | | | | | | | | | -| J21 | | | PS_MIO48_501 | PSS IO | | | | | | | | | | | | | | | | | -| J22 | | | PS_DDR_DQ44_504 | PSS IO | | | | | | | | | | | | | | | | | -| J23 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| J24 | | | PS_DDR_DQ41_504 | PSS IO | | | | | | | | | | | | | | | | | -| J25 | | | PS_DDR_DQ63_504 | PSS IO | | | | | | | | | | | | | | | | | -| J26 | | | PS_DDR_DQS_P7_504 | PSS IO | | | | | | | | | | | | | | | | | -| J27 | | | PS_DDR_DQS_N7_504 | PSS IO | | | | | | | | | | | | | | | | | -| J28 | | | PS_DDR_DQ56_504 | PSS IO | | | | | | | | | | | | | | | | | -| K1 | | High Performance | IO_L7N_T1L_N1_QBC_AD13N_65 | User IO | | 65 | | | | | | | | | | | | | | | -| K2 | | High Performance | IO_L9P_T1L_N4_AD12P_65 | User IO | | 65 | | | | | | | | | | | | | | | -| K3 | | High Performance | IO_L11N_T1U_N9_GC_65 | GCLK | | 65 | | | | | | | | | | | | | | | -| K4 | | High Performance | IO_L11P_T1U_N8_GC_65 | GCLK | | 65 | | | | | | | | | | | | | | | -| K5 | | High Performance | IO_T3U_N12_65 | User IO | | 65 | | | | | | | | | | | | | | | -| K6 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| K7 | | High Performance | IO_L22N_T3U_N7_DBC_AD0N_65 | User IO | | 65 | | | | | | | | | | | | | | | -| K8 | | High Performance | IO_L22P_T3U_N6_DBC_AD0P_65 | User IO | | 65 | | | | | | | | | | | | | | | -| K9 | | High Performance | IO_L23P_T3U_N8_I2C_SCLK_65 | User IO | | 65 | | | | | | | | | | | | | | | -| K10 | | | VCCINT_IO | VCCINT | | | | | | | | | | | | | | | | | -| K11 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| K12 | | High Density | IO_L2N_AD14N_25 | User IO | | 25 | | | | | | | | | | | | | | | -| K13 | | High Density | IO_L2P_AD14P_25 | User IO | | 25 | | | | | | | | | | | | | | | -| K14 | | High Density | IO_L11P_AD1P_26 | User IO | | 26 | | | | | | | | | | | | | | | -| K15 | | | PS_MIO28_501 | PSS IO | | | | | | | | | | | | | | | | | -| K16 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| K17 | | | PS_MIO36_501 | PSS IO | | | | | | | | | | | | | | | | | -| K18 | | | PS_MIO40_501 | PSS IO | | | | | | | | | | | | | | | | | -| K19 | | | PS_MIO43_501 | PSS IO | | | | | | | | | | | | | | | | | -| K20 | | | PS_MIO45_501 | PSS IO | | | | | | | | | | | | | | | | | -| K21 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| K22 | | | PS_DDR_DQ46_504 | PSS IO | | | | | | | | | | | | | | | | | -| K23 | | | PS_DDR_DQS_N5_504 | PSS IO | | | | | | | | | | | | | | | | | -| K24 | | | PS_DDR_DQ43_504 | PSS IO | | | | | | | | | | | | | | | | | -| K25 | | | PS_DDR_DQ62_504 | PSS IO | | | | | | | | | | | | | | | | | -| K26 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| K27 | | | PS_DDR_DQ57_504 | PSS IO | | | | | | | | | | | | | | | | | -| K28 | | | PS_DDR_DQ52_504 | PSS IO | | | | | | | | | | | | | | | | | -| L1 | | High Performance | IO_L7P_T1L_N0_QBC_AD13P_65 | User IO | | 65 | | | | | | | | | | | | | | | -| L2 | | High Performance | IO_L12N_T1U_N11_GC_65 | GCLK | | 65 | | | | | | | | | | | | | | | -| L3 | | High Performance | IO_L12P_T1U_N10_GC_65 | GCLK | | 65 | | | | | | | | | | | | | | | -| L4 | | High Performance | VCCO_65 | VCCO | | 65 | | | | | | 0.00-1.80 | | | | | | | | | -| L5 | | High Performance | IO_L14N_T2L_N3_GC_65 | GCLK | | 65 | | | | | | | | | | | | | | | -| L6 | | High Performance | IO_L13N_T2L_N1_GC_QBC_65 | GCLK | | 65 | | | | | | | | | | | | | | | -| L7 | | High Performance | IO_L13P_T2L_N0_GC_QBC_65 | GCLK | | 65 | | | | | | | | | | | | | | | -| L8 | | High Performance | IO_L18N_T2U_N11_AD2N_65 | User IO | | 65 | | | | | | | | | | | | | | | -| L9 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| L10 | | | VCCINT_IO | VCCINT | | | | | | | | | | | | | | | | | -| L11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | | -| L12 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | | -| L13 | | High Density | IO_L12N_AD0N_26 | User IO | | 26 | | | | | | | | | | | | | | | -| L14 | | High Density | IO_L12P_AD0P_26 | User IO | | 26 | | | | | | | | | | | | | | | -| L15 | | | PS_MIO26_501 | PSS IO | | | | | | | | | | | | | | | | | -| L16 | | | PS_MIO33_501 | PSS IO | | | | | | | | | | | | | | | | | -| L17 | | | PS_MIO34_501 | PSS IO | | | | | | | | | | | | | | | | | -| L18 | | | PS_MIO42_501 | PSS IO | | | | | | | | | | | | | | | | | -| L19 | | | VCCO_PSIO1_501 | VCCO | | | | | | | | any** | | | | | | | | | -| L20 | | | PS_MIO46_501 | PSS IO | | | | | | | | | | | | | | | | | -| L21 | | | PS_MIO51_501 | PSS IO | | | | | | | | | | | | | | | | | -| L22 | | | PS_DDR_DQ47_504 | PSS IO | | | | | | | | | | | | | | | | | -| L23 | | | PS_DDR_DQS_P5_504 | PSS IO | | | | | | | | | | | | | | | | | -| L24 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| L25 | | | PS_DDR_DQ50_504 | PSS IO | | | | | | | | | | | | | | | | | -| L26 | | | PS_DDR_DQ51_504 | PSS IO | | | | | | | | | | | | | | | | | -| L27 | | | PS_DDR_DM6_504 | PSS IO | | | | | | | | | | | | | | | | | -| L28 | | | PS_DDR_DQ53_504 | PSS IO | | | | | | | | | | | | | | | | | -| M1 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| M2 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| M3 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| M4 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| M5 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| M6 | | High Performance | IO_L14P_T2L_N2_GC_65 | GCLK | | 65 | | | | | | | | | | | | | | | -| M7 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| M8 | | High Performance | IO_L18P_T2U_N10_AD2P_65 | User IO | | 65 | | | | | | | | | | | | | | | -| M9 | | | VCCINT_IO | VCCINT | | | | | | | | | | | | | | | | | -| M10 | | | VCCINT_IO | VCCINT | | | | | | | | | | | | | | | | | -| M11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | | -| M12 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | | -| M13 | | | VCCAUX_IO | VCCAUX | | | | | | | | | | | | | | | | | -| M14 | | | VCCAUX_IO | VCCAUX | | | | | | | | | | | | | | | | | -| M15 | | | VCCAUX_IO | VCCAUX | | | | | | | | | | | | | | | | | -| M16 | | | VCCAUX | VCCAUX | | | | | | | | 1.80 | | | | | | | | | -| M17 | | | VCCO_PSIO3_503 | VCCO | | | | | | | | any** | | | | | | | | | -| M18 | | | PS_MIO49_501 | PSS IO | | | | | | | | | | | | | | | | | -| M19 | | | PS_MIO50_501 | PSS IO | | | | | | | | | | | | | | | | | -| M20 | | | PS_ERROR_STATUS_503 | PSS IO | | | | | | | | | | | | | | | | | -| M21 | | | PS_DONE_503 | PSS IO | | | | | | | | | | | | | | | | | -| M22 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| M23 | | | PS_DDR_DQS_N4_504 | PSS IO | | | | | | | | | | | | | | | | | -| M24 | | | PS_DDR_DQ42_504 | PSS IO | | | | | | | | | | | | | | | | | -| M25 | | | PS_DDR_DQ48_504 | PSS IO | | | | | | | | | | | | | | | | | -| M26 | | | PS_DDR_DQ49_504 | PSS IO | | | | | | | | | | | | | | | | | -| M27 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| M28 | | | PS_DDR_DQ54_504 | PSS IO | | | | | | | | | | | | | | | | | -| N1 | | | NC | Not Connected | | | | | | | | | | | | | | | | | -| N2 | | | NC | Not Connected | | | | | | | | | | | | | | | | | -| N3 | | | NC | Not Connected | | | | | | | | | | | | | | | | | -| N4 | | | NC | Not Connected | | | | | | | | | | | | | | | | | -| N5 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| N6 | | High Performance | IO_L15N_T2L_N5_AD11N_65 | User IO | | 65 | | | | | | | | | | | | | | | -| N7 | | High Performance | IO_L15P_T2L_N4_AD11P_65 | User IO | | 65 | | | | | | | | | | | | | | | -| N8 | | High Performance | IO_L17N_T2U_N9_AD10N_65 | User IO | | 65 | | | | | | | | | | | | | | | -| N9 | | High Performance | IO_L17P_T2U_N8_AD10P_65 | User IO | | 65 | | | | | | | | | | | | | | | -| N10 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| N11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | | -| N12 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| N13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | | -| N14 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| N15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | | -| N16 | | | VCCAUX | VCCAUX | | | | | | | | 1.80 | | | | | | | | | -| N17 | | | PS_PADI_503 | PSS IO | | | | | | | | | | | | | | | | | -| N18 | | | PS_PADO_503 | PSS IO | | | | | | | | | | | | | | | | | -| N19 | | | PS_SRST_B_503 | PSS IO | | | | | | | | | | | | | | | | | -| N20 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| N21 | | | PS_JTAG_TMS_503 | PSS IO | | | | | | | | | | | | | | | | | -| N22 | | | PS_DDR_DQ35_504 | PSS IO | | | | | | | | | | | | | | | | | -| N23 | | | PS_DDR_DQS_P4_504 | PSS IO | | | | | | | | | | | | | | | | | -| N24 | | | PS_DDR_DQ39_504 | PSS IO | | | | | | | | | | | | | | | | | -| N25 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| N26 | | | PS_DDR_DQS_P6_504 | PSS IO | | | | | | | | | | | | | | | | | -| N27 | | | PS_DDR_DQS_N6_504 | PSS IO | | | | | | | | | | | | | | | | | -| N28 | | | PS_DDR_DQ55_504 | PSS IO | | | | | | | | | | | | | | | | | -| P1 | | | NC | Not Connected | | | | | | | | | | | | | | | | | -| P2 | | | NC | Not Connected | | | | | | | | | | | | | | | | | -| P3 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| P4 | | | NC | Not Connected | | | | | | | | | | | | | | | | | -| P5 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| P6 | | High Performance | IO_L16N_T2U_N7_QBC_AD3N_65 | User IO | | 65 | | | | | | | | | | | | | | | -| P7 | | High Performance | IO_L16P_T2U_N6_QBC_AD3P_65 | User IO | | 65 | | | | | | | | | | | | | | | -| P8 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| P9 | | High Performance | IO_T2U_N12_65 | User IO | | 65 | | | | | | | | | | | | | | | -| P10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | | -| P11 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| P12 | | Dedicated | VCCADC | XADC | | 0 | | | | | | | | | | | | | | | -| P13 | | Dedicated | GNDADC | XADC | | 0 | | | | | | | | | | | | | | | -| P14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | | -| P15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | | -| P16 | | | PS_POR_B_503 | PSS IO | | | | | | | | | | | | | | | | | -| P17 | | | PS_ERROR_OUT_503 | PSS IO | | | | | | | | | | | | | | | | | -| P18 | | | VCCO_PSIO3_503 | VCCO | | | | | | | | any** | | | | | | | | | -| P19 | | | PS_MODE0_503 | PSS IO | | | | | | | | | | | | | | | | | -| P20 | | | PS_MODE1_503 | PSS IO | | | | | | | | | | | | | | | | | -| P21 | | | PS_INIT_B_503 | PSS IO | | | | | | | | | | | | | | | | | -| P22 | | | PS_DDR_DQ34_504 | PSS IO | | | | | | | | | | | | | | | | | -| P23 | | | VCCO_PSDDR_504 | VCCO | | | | | | | | any** | | | | | | | | | -| P24 | | | PS_DDR_DQ37_504 | PSS IO | | | | | | | | | | | | | | | | | -| P25 | | | PS_DDR_DQ70_504 | PSS IO | | | | | | | | | | | | | | | | | -| P26 | | | PS_DDR_DQ68_504 | PSS IO | | | | | | | | | | | | | | | | | -| P27 | | | PS_DDR_DQ67_504 | PSS IO | | | | | | | | | | | | | | | | | -| P28 | | | PS_DDR_DQ66_504 | PSS IO | | | | | | | | | | | | | | | | | -| R1 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| R2 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| R3 | | | NC | Not Connected | | | | | | | | | | | | | | | | | -| R4 | | | NC | Not Connected | | | | | | | | | | | | | | | | | -| R5 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| R6 | | High Performance | IO_L6P_T0U_N10_AD6P_65 | User IO | | 65 | | | | | | | | | | | | | | | -| R7 | | High Performance | IO_L5P_T0U_N8_AD14P_65 | User IO | | 65 | | | | | | | | | | | | | | | -| R8 | | High Performance | IO_L4P_T0U_N6_DBC_AD7P_SMBALERT_65 | User IO | | 65 | | | | | | | | | | | | | | | -| R9 | | High Performance | VREF_65 | Voltage | | 65 | | | | | | | | | | | | | | | -| R10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | | -| R11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | | -| R12 | | Dedicated | VREFN | XADC | | 0 | | | | | | | | | | | | | | | -| R13 | | | VP | XADC | | | | | | | | | | | | | | | | | -| R14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | | -| R15 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| R16 | | | PS_REF_CLK_503 | PSS Clock | | | | | | | | | | | | | | | | | -| R17 | | | PS_PROG_B_503 | PSS IO | | | | | | | | | | | | | | | | | -| R18 | | | PS_JTAG_TDI_503 | PSS IO | | | | | | | | | | | | | | | | | -| R19 | | | PS_JTAG_TCK_503 | PSS IO | | | | | | | | | | | | | | | | | -| R20 | | | PS_MODE2_503 | PSS IO | | | | | | | | | | | | | | | | | -| R21 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| R22 | | | PS_DDR_DQ33_504 | PSS IO | | | | | | | | | | | | | | | | | -| R23 | | | PS_DDR_DM4_504 | PSS IO | | | | | | | | | | | | | | | | | -| R24 | | | PS_DDR_DQ38_504 | PSS IO | | | | | | | | | | | | | | | | | -| R25 | | | PS_DDR_DQ69_504 | PSS IO | | | | | | | | | | | | | | | | | -| R26 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| R27 | | | PS_DDR_DQS_P8_504 | PSS IO | | | | | | | | | | | | | | | | | -| R28 | | | PS_DDR_DQ65_504 | PSS IO | | | | | | | | | | | | | | | | | -| T1 | | | NC | Not Connected | | | | | | | | | | | | | | | | | -| T2 | | | NC | Not Connected | | | | | | | | | | | | | | | | | -| T3 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| T4 | | | NC | Not Connected | | | | | | | | | | | | | | | | | -| T5 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| T6 | | High Performance | IO_L6N_T0U_N11_AD6N_65 | User IO | | 65 | | | | | | | | | | | | | | | -| T7 | | High Performance | IO_L5N_T0U_N9_AD14N_65 | User IO | | 65 | | | | | | | | | | | | | | | -| T8 | | High Performance | IO_L4N_T0U_N7_DBC_AD7N_65 | User IO | | 65 | | | | | | | | | | | | | | | -| T9 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| T10 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| T11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | | -| T12 | | | VN | XADC | | | | | | | | | | | | | | | | | -| T13 | | Dedicated | VREFP | XADC | | 0 | | | | | | | | | | | | | | | -| T14 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| T15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | | -| T16 | | | VCC_PSPLL | PSS VCCPLL | | | | | | | | | | | | | | | | | -| T17 | | | VCC_PSPLL | PSS VCCPLL | | | | | | | | | | | | | | | | | -| T18 | | | VCC_PSPLL | PSS VCCPLL | | | | | | | | | | | | | | | | | -| T19 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| T20 | | | PS_MODE3_503 | PSS IO | | | | | | | | | | | | | | | | | -| T21 | | | PS_JTAG_TDO_503 | PSS IO | | | | | | | | | | | | | | | | | -| T22 | | | PS_DDR_DQ32_504 | PSS IO | | | | | | | | | | | | | | | | | -| T23 | | | PS_DDR_DQ36_504 | PSS IO | | | | | | | | | | | | | | | | | -| T24 | | | VCCO_PSDDR_504 | VCCO | | | | | | | | any** | | | | | | | | | -| T25 | | | PS_DDR_DQ71_504 | PSS IO | | | | | | | | | | | | | | | | | -| T26 | | | PS_DDR_DM8_504 | PSS IO | | | | | | | | | | | | | | | | | -| T27 | | | PS_DDR_DQS_N8_504 | PSS IO | | | | | | | | | | | | | | | | | -| T28 | | | PS_DDR_DQ64_504 | PSS IO | | | | | | | | | | | | | | | | | -| U1 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| U2 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| U3 | | | NC | Not Connected | | | | | | | | | | | | | | | | | -| U4 | | | NC | Not Connected | | | | | | | | | | | | | | | | | -| U5 | | | NC | Not Connected | | | | | | | | | | | | | | | | | -| U6 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| U7 | | Dedicated | PUDC_B | Config | | 0 | | | | | | | | | | | | | | | -| U8 | | High Performance | IO_L3P_T0L_N4_AD15P_65 | User IO | | 65 | | | | | | | | | | | | | | | -| U9 | | High Performance | IO_L2P_T0L_N2_65 | User IO | | 65 | | | | | | | | | | | | | | | -| U10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | | -| U11 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| U12 | | Dedicated | DXN | Temp Sensor | | 0 | | | | | | | | | | | | | | | -| U13 | | Dedicated | DXP | Temp Sensor | | 0 | | | | | | | | | | | | | | | -| U14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | | -| U15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | | -| U16 | | | VCC_PSDDR_PLL | PSS VCCPLL | | | | | | | | | | | | | | | | | -| U17 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| U18 | | | VCC_PSDDR_PLL | PSS VCCPLL | | | | | | | | | | | | | | | | | -| U19 | | | VCC_PSAUX | PSS VCCAUX | | | | | | | | | | | | | | | | | -| U20 | | | VCC_PSAUX | PSS VCCAUX | | | | | | | | | | | | | | | | | -| U21 | | | RSVDGND | GND | | | | | | | | | | | | | | | | | -| U22 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| U23 | | | PS_DDR_RAM_RST_N_504 | PSS IO | | | | | | | | | | | | | | | | | -| U24 | | | PS_DDR_ZQ_504 | PSS IO | | | | | | | | | | | | | | | | | -| U25 | | | PS_DDR_ALERT_N_504 | PSS IO | | | | | | | | | | | | | | | | | -| U26 | | | PS_DDR_ODT1_504 | PSS IO | | | | | | | | | | | | | | | | | -| U27 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| U28 | | | PS_DDR_ODT0_504 | PSS IO | | | | | | | | | | | | | | | | | -| V1 | | | NC | Not Connected | | | | | | | | | | | | | | | | | -| V2 | | | NC | Not Connected | | | | | | | | | | | | | | | | | -| V3 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| V4 | | | NC | Not Connected | | | | | | | | | | | | | | | | | -| V5 | | | NC | Not Connected | | | | | | | | | | | | | | | | | -| V6 | | | NC | Not Connected | | | | | | | | | | | | | | | | | -| V7 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| V8 | | High Performance | IO_L3N_T0L_N5_AD15N_65 | User IO | | 65 | | | | | | | | | | | | | | | -| V9 | | High Performance | IO_L2N_T0L_N3_65 | User IO | | 65 | | | | | | | | | | | | | | | -| V10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | | -| V11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | | -| V12 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | | -| V13 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| V14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | | -| V15 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| V16 | | | VCC_PSINTLP | PSS VCCINT | | | | | | | | | | | | | | | | | -| V17 | | | VCC_PSINTLP | PSS VCCINT | | | | | | | | | | | | | | | | | -| V18 | | | VCC_PSINTLP | PSS VCCINT | | | | | | | | | | | | | | | | | -| V19 | | | VCC_PSAUX | PSS VCCAUX | | | | | | | | | | | | | | | | | -| V20 | | | RSVDGND | GND | | | | | | | | | | | | | | | | | -| V21 | | | RSVDGND | GND | | | | | | | | | | | | | | | | | -| V22 | | | PS_DDR_BG1_504 | PSS IO | | | | | | | | | | | | | | | | | -| V23 | | | PS_DDR_BA0_504 | PSS IO | | | | | | | | | | | | | | | | | -| V24 | | | PS_DDR_PARITY_504 | PSS IO | | | | | | | | | | | | | | | | | -| V25 | | | VCCO_PSDDR_504 | VCCO | | | | | | | | any** | | | | | | | | | -| V26 | | | PS_DDR_CS_N1_504 | PSS IO | | | | | | | | | | | | | | | | | -| V27 | | | PS_DDR_CKE1_504 | PSS IO | | | | | | | | | | | | | | | | | -| V28 | | | PS_DDR_CKE0_504 | PSS IO | | | | | | | | | | | | | | | | | -| W1 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| W2 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| W3 | | | NC | Not Connected | | | | | | | | | | | | | | | | | -| W4 | | | NC | Not Connected | | | | | | | | | | | | | | | | | -| W5 | | | NC | Not Connected | | | | | | | | | | | | | | | | | -| W6 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| W7 | | Dedicated | POR_OVERRIDE | Config | | 0 | | | | | | | | | | | | | | | -| W8 | | High Performance | IO_L1P_T0L_N0_DBC_65 | User IO | | 65 | | | | | | | | | | | | | | | -| W9 | | High Performance | IO_T0U_N12_VRP_65 | User IO | | 65 | | | | | | | | | | | | | | | -| W10 | | High Density | IO_L10P_AD2P_44 | User IO | | 44 | | | | | | | | | | | | | | | -| W11 | | High Density | IO_L11N_AD9N_24 | User IO | | 24 | | | | | | | | | | | | | | | -| W12 | | High Density | IO_L11P_AD9P_24 | User IO | | 24 | | | | | | | | | | | | | | | -| W13 | | High Density | IO_L9N_AD11N_24 | User IO | | 24 | | | | | | | | | | | | | | | -| W14 | | High Density | IO_L9P_AD11P_24 | User IO | | 24 | | | | | | | | | | | | | | | -| W15 | | | VCC_PSINTLP | PSS VCCINT | | | | | | | | | | | | | | | | | -| W16 | | | VCC_PSINTLP | PSS VCCINT | | | | | | | | | | | | | | | | | -| W17 | | | VCC_PSINTLP | PSS VCCINT | | | | | | | | | | | | | | | | | -| W18 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| W19 | | | VCC_PSAUX | PSS VCCAUX | | | | | | | | | | | | | | | | | -| W20 | | | GND_PSADC | XADC | | | | | | | | | | | | | | | | | -| W21 | | | RSVDGND | GND | | | | | | | | | | | | | | | | | -| W22 | | | PS_DDR_BA1_504 | PSS IO | | | | | | | | | | | | | | | | | -| W23 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| W24 | | | PS_DDR_BG0_504 | PSS IO | | | | | | | | | | | | | | | | | -| W25 | | | PS_DDR_CK0_504 | PSS IO | | | | | | | | | | | | | | | | | -| W26 | | | PS_DDR_CK_N0_504 | PSS IO | | | | | | | | | | | | | | | | | -| W27 | | | PS_DDR_CS_N0_504 | PSS IO | | | | | | | | | | | | | | | | | -| W28 | | | PS_DDR_A0_504 | PSS IO | | | | | | | | | | | | | | | | | -| Y1 | | | NC | Not Connected | | | | | | | | | | | | | | | | | -| Y2 | | | NC | Not Connected | | | | | | | | | | | | | | | | | -| Y3 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| Y4 | | | NC | Not Connected | | | | | | | | | | | | | | | | | -| Y5 | | | NC | Not Connected | | | | | | | | | | | | | | | | | -| Y6 | | | NC | Not Connected | | | | | | | | | | | | | | | | | -| Y7 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| Y8 | | High Performance | IO_L1N_T0L_N1_DBC_65 | User IO | | 65 | | | | | | | | | | | | | | | -| Y9 | ROT_B | High Density | IO_L11P_AD1P_44 | INPUT | LVCMOS33 | 44 | | | | | NONE | | FIXED | | | | NONE | | | | -| Y10 | | High Density | IO_L10N_AD2N_44 | User IO | | 44 | | | | | | | | | | | | | | | -| Y11 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| Y12 | | High Density | IO_L12P_AD8P_24 | User IO | | 24 | | | | | | | | | | | | | | | -| Y13 | | High Density | IO_L10N_AD10N_24 | User IO | | 24 | | | | | | | | | | | | | | | -| Y14 | | High Density | IO_L10P_AD10P_24 | User IO | | 24 | | | | | | | | | | | | | | | -| Y15 | | | VCC_PSINTFP | PSS VCCINT | | | | | | | | | | | | | | | | | -| Y16 | | | GND | GND | | | | | | | | 0.0 | | | | | | | | | -| Y17 | | | VCC_PSINTFP | PSS VCCINT | | | | | | | | | | | | | | | | | -| Y18 | | | VCC_PSBATT | VBATT | | | | | | | | | | | | | | | | | -| Y19 | | | VCC_PSINTFP_DDR | PSS VCCINT | | | | | | | | | | | | | | | | | -| Y20 | | | VCC_PSADC | XADC | | | | | | | | | | | | | | | | | -| Y21 | | | RSVDGND | GND | | | | | | | | | | | | | | | | | -| Y22 | | | PS_DDR_A6_504 | PSS IO | | | | | | | | | | | | | | | | | -| Y23 | | | PS_DDR_ACT_N_504 | PSS IO | | | | | | | | | | | | | | | | | -| Y24 | | | PS_DDR_CK1_504 | PSS IO | | | | | | | | | | | | | | | | | -| Y25 | | | PS_DDR_CK_N1_504 | PSS IO | | | | | | | | | | | | | | | | | -| Y26 | | | VCCO_PSDDR_504 | VCCO | | | | | | | | any** | | | | | | | | | -| Y27 | | | PS_DDR_A4_504 | PSS IO | | | | | | | | | | | | | | | | | -| Y28 | | | PS_DDR_A1_504 | PSS IO | | | | | | | | | | | | | | | | | -+------------+------------------+------------------+------------------------------------+---------------+-------------+---------+------------+-------------------------+------+-------------------+----------------------+-----------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ -* Default value -** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. - - diff --git a/SW2.runs/impl_1/design_1_wrapper_methodology_drc_routed.pb b/SW2.runs/impl_1/design_1_wrapper_methodology_drc_routed.pb deleted file mode 100644 index 40b5ed8..0000000 Binary files a/SW2.runs/impl_1/design_1_wrapper_methodology_drc_routed.pb and /dev/null differ diff --git a/SW2.runs/impl_1/design_1_wrapper_methodology_drc_routed.rpt b/SW2.runs/impl_1/design_1_wrapper_methodology_drc_routed.rpt deleted file mode 100644 index 20c46c8..0000000 --- a/SW2.runs/impl_1/design_1_wrapper_methodology_drc_routed.rpt +++ /dev/null @@ -1,3031 +0,0 @@ -Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2025.1 (win64) Build 6140274 Thu May 22 00:12:29 MDT 2025 -| Date : Tue Jun 9 14:08:01 2026 -| Host : Lab016-04 running 64-bit major release (build 9200) -| Command : report_methodology -file design_1_wrapper_methodology_drc_routed.rpt -pb design_1_wrapper_methodology_drc_routed.pb -rpx design_1_wrapper_methodology_drc_routed.rpx -| Design : design_1_wrapper -| Device : xczu3eg-sfvc784-2-e -| Speed File : -2 -| Design State : Fully Routed --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - -Report Methodology - -Table of Contents ------------------ -1. REPORT SUMMARY -2. REPORT DETAILS - -1. REPORT SUMMARY ------------------ - Netlist: netlist - Floorplan: design_1 - Design limits: - Max checks: - Checks found: 599 -+-----------+------------------+-----------------------------+--------+ -| Rule | Severity | Description | Checks | -+-----------+------------------+-----------------------------+--------+ -| TIMING-17 | Critical Warning | Non-clocked sequential cell | 257 | -| DPIR-2 | Warning | Asynchronous driver check | 342 | -+-----------+------------------+-----------------------------+--------+ - -2. REPORT DETAILS ------------------ -TIMING-17#1 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[0][R][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#2 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[0][R][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#3 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[0][R][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#4 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[0][R][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#5 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[0][R][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#6 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[0][R][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#7 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[0][R][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#8 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[0][R][8]/C is not reached by a timing clock -Related violations: - -TIMING-17#9 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[0][R][9]/C is not reached by a timing clock -Related violations: - -TIMING-17#10 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[0][is_active]/C is not reached by a timing clock -Related violations: - -TIMING-17#11 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[10][R][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#12 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[10][R][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#13 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[10][R][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#14 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[10][R][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#15 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[10][R][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#16 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[10][R][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#17 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[10][R][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#18 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[10][R][8]/C is not reached by a timing clock -Related violations: - -TIMING-17#19 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[10][R][9]/C is not reached by a timing clock -Related violations: - -TIMING-17#20 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[10][is_active]/C is not reached by a timing clock -Related violations: - -TIMING-17#21 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[11][R][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#22 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[11][R][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#23 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[11][R][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#24 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[11][R][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#25 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[11][R][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#26 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[11][R][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#27 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[11][R][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#28 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[11][R][8]/C is not reached by a timing clock -Related violations: - -TIMING-17#29 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[11][R][9]/C is not reached by a timing clock -Related violations: - -TIMING-17#30 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[11][is_active]/C is not reached by a timing clock -Related violations: - -TIMING-17#31 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[12][R][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#32 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[12][R][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#33 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[12][R][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#34 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[12][R][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#35 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[12][R][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#36 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[12][R][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#37 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[12][R][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#38 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[12][R][8]/C is not reached by a timing clock -Related violations: - -TIMING-17#39 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[12][R][9]/C is not reached by a timing clock -Related violations: - -TIMING-17#40 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[12][is_active]/C is not reached by a timing clock -Related violations: - -TIMING-17#41 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[13][R][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#42 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[13][R][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#43 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[13][R][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#44 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[13][R][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#45 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[13][R][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#46 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[13][R][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#47 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[13][R][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#48 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[13][R][8]/C is not reached by a timing clock -Related violations: - -TIMING-17#49 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[13][R][9]/C is not reached by a timing clock -Related violations: - -TIMING-17#50 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[13][is_active]/C is not reached by a timing clock -Related violations: - -TIMING-17#51 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[14][R][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#52 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[14][R][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#53 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[14][R][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#54 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[14][R][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#55 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[14][R][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#56 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[14][R][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#57 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[14][R][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#58 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[14][R][8]/C is not reached by a timing clock -Related violations: - -TIMING-17#59 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[14][R][9]/C is not reached by a timing clock -Related violations: - -TIMING-17#60 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[14][is_active]/C is not reached by a timing clock -Related violations: - -TIMING-17#61 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[15][R][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#62 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[15][R][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#63 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[15][R][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#64 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[15][R][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#65 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[15][R][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#66 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[15][R][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#67 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[15][R][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#68 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[15][R][8]/C is not reached by a timing clock -Related violations: - -TIMING-17#69 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[15][R][9]/C is not reached by a timing clock -Related violations: - -TIMING-17#70 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[15][is_active]/C is not reached by a timing clock -Related violations: - -TIMING-17#71 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[16][R][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#72 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[16][R][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#73 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[16][R][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#74 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[16][R][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#75 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[16][R][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#76 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[16][R][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#77 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[16][R][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#78 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[16][R][8]/C is not reached by a timing clock -Related violations: - -TIMING-17#79 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[16][R][9]/C is not reached by a timing clock -Related violations: - -TIMING-17#80 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[16][is_active]/C is not reached by a timing clock -Related violations: - -TIMING-17#81 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[17][R][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#82 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[17][R][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#83 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[17][R][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#84 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[17][R][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#85 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[17][R][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#86 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[17][R][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#87 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[17][R][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#88 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[17][R][8]/C is not reached by a timing clock -Related violations: - -TIMING-17#89 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[17][R][9]/C is not reached by a timing clock -Related violations: - -TIMING-17#90 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[17][is_active]/C is not reached by a timing clock -Related violations: - -TIMING-17#91 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[18][R][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#92 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[18][R][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#93 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[18][R][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#94 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[18][R][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#95 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[18][R][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#96 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[18][R][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#97 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[18][R][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#98 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[18][R][8]/C is not reached by a timing clock -Related violations: - -TIMING-17#99 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[18][R][9]/C is not reached by a timing clock -Related violations: - -TIMING-17#100 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[18][is_active]/C is not reached by a timing clock -Related violations: - -TIMING-17#101 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[19][R][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#102 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[19][R][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#103 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[19][R][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#104 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[19][R][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#105 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[19][R][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#106 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[19][R][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#107 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[19][R][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#108 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[19][R][8]/C is not reached by a timing clock -Related violations: - -TIMING-17#109 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[19][R][9]/C is not reached by a timing clock -Related violations: - -TIMING-17#110 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[19][is_active]/C is not reached by a timing clock -Related violations: - -TIMING-17#111 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[1][R][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#112 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[1][R][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#113 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[1][R][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#114 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[1][R][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#115 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[1][R][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#116 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[1][R][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#117 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[1][R][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#118 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[1][R][8]/C is not reached by a timing clock -Related violations: - -TIMING-17#119 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[1][R][9]/C is not reached by a timing clock -Related violations: - -TIMING-17#120 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[1][is_active]/C is not reached by a timing clock -Related violations: - -TIMING-17#121 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[20][R][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#122 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[20][R][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#123 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[20][R][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#124 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[20][R][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#125 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[20][R][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#126 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[20][R][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#127 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[20][R][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#128 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[20][R][8]/C is not reached by a timing clock -Related violations: - -TIMING-17#129 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[20][R][9]/C is not reached by a timing clock -Related violations: - -TIMING-17#130 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[20][is_active]/C is not reached by a timing clock -Related violations: - -TIMING-17#131 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[21][R][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#132 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[21][R][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#133 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[21][R][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#134 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[21][R][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#135 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[21][R][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#136 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[21][R][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#137 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[21][R][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#138 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[21][R][8]/C is not reached by a timing clock -Related violations: - -TIMING-17#139 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[21][R][9]/C is not reached by a timing clock -Related violations: - -TIMING-17#140 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[21][is_active]/C is not reached by a timing clock -Related violations: - -TIMING-17#141 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[22][R][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#142 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[22][R][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#143 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[22][R][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#144 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[22][R][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#145 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[22][R][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#146 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[22][R][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#147 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[22][R][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#148 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[22][R][8]/C is not reached by a timing clock -Related violations: - -TIMING-17#149 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[22][R][9]/C is not reached by a timing clock -Related violations: - -TIMING-17#150 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[22][is_active]/C is not reached by a timing clock -Related violations: - -TIMING-17#151 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[23][R][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#152 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[23][R][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#153 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[23][R][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#154 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[23][R][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#155 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[23][R][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#156 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[23][R][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#157 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[23][R][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#158 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[23][R][8]/C is not reached by a timing clock -Related violations: - -TIMING-17#159 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[23][R][9]/C is not reached by a timing clock -Related violations: - -TIMING-17#160 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[23][is_active]/C is not reached by a timing clock -Related violations: - -TIMING-17#161 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[2][R][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#162 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[2][R][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#163 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[2][R][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#164 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[2][R][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#165 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[2][R][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#166 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[2][R][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#167 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[2][R][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#168 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[2][R][8]/C is not reached by a timing clock -Related violations: - -TIMING-17#169 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[2][R][9]/C is not reached by a timing clock -Related violations: - -TIMING-17#170 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[2][is_active]/C is not reached by a timing clock -Related violations: - -TIMING-17#171 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[3][R][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#172 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[3][R][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#173 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[3][R][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#174 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[3][R][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#175 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[3][R][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#176 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[3][R][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#177 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[3][R][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#178 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[3][R][8]/C is not reached by a timing clock -Related violations: - -TIMING-17#179 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[3][R][9]/C is not reached by a timing clock -Related violations: - -TIMING-17#180 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[3][is_active]/C is not reached by a timing clock -Related violations: - -TIMING-17#181 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[4][R][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#182 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[4][R][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#183 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[4][R][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#184 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[4][R][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#185 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[4][R][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#186 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[4][R][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#187 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[4][R][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#188 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[4][R][8]/C is not reached by a timing clock -Related violations: - -TIMING-17#189 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[4][R][9]/C is not reached by a timing clock -Related violations: - -TIMING-17#190 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[4][is_active]/C is not reached by a timing clock -Related violations: - -TIMING-17#191 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[5][R][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#192 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[5][R][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#193 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[5][R][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#194 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[5][R][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#195 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[5][R][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#196 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[5][R][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#197 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[5][R][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#198 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[5][R][8]/C is not reached by a timing clock -Related violations: - -TIMING-17#199 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[5][R][9]/C is not reached by a timing clock -Related violations: - -TIMING-17#200 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[5][is_active]/C is not reached by a timing clock -Related violations: - -TIMING-17#201 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[6][R][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#202 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[6][R][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#203 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[6][R][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#204 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[6][R][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#205 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[6][R][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#206 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[6][R][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#207 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[6][R][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#208 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[6][R][8]/C is not reached by a timing clock -Related violations: - -TIMING-17#209 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[6][R][9]/C is not reached by a timing clock -Related violations: - -TIMING-17#210 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[6][is_active]/C is not reached by a timing clock -Related violations: - -TIMING-17#211 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[7][R][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#212 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[7][R][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#213 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[7][R][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#214 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[7][R][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#215 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[7][R][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#216 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[7][R][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#217 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[7][R][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#218 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[7][R][8]/C is not reached by a timing clock -Related violations: - -TIMING-17#219 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[7][R][9]/C is not reached by a timing clock -Related violations: - -TIMING-17#220 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[7][is_active]/C is not reached by a timing clock -Related violations: - -TIMING-17#221 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[8][R][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#222 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[8][R][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#223 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[8][R][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#224 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[8][R][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#225 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[8][R][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#226 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[8][R][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#227 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[8][R][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#228 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[8][R][8]/C is not reached by a timing clock -Related violations: - -TIMING-17#229 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[8][R][9]/C is not reached by a timing clock -Related violations: - -TIMING-17#230 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[8][is_active]/C is not reached by a timing clock -Related violations: - -TIMING-17#231 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[9][R][1]/C is not reached by a timing clock -Related violations: - -TIMING-17#232 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[9][R][2]/C is not reached by a timing clock -Related violations: - -TIMING-17#233 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[9][R][3]/C is not reached by a timing clock -Related violations: - -TIMING-17#234 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[9][R][4]/C is not reached by a timing clock -Related violations: - -TIMING-17#235 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[9][R][5]/C is not reached by a timing clock -Related violations: - -TIMING-17#236 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[9][R][6]/C is not reached by a timing clock -Related violations: - -TIMING-17#237 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[9][R][7]/C is not reached by a timing clock -Related violations: - -TIMING-17#238 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[9][R][8]/C is not reached by a timing clock -Related violations: - -TIMING-17#239 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[9][R][9]/C is not reached by a timing clock -Related violations: - -TIMING-17#240 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/enemies_reg[9][is_active]/C is not reached by a timing clock -Related violations: - -TIMING-17#241 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/hited_reg/C is not reached by a timing clock -Related violations: - -TIMING-17#242 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/lfsr_reg[0]/C is not reached by a timing clock -Related violations: - -TIMING-17#243 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/lfsr_reg[10]/C is not reached by a timing clock -Related violations: - -TIMING-17#244 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/lfsr_reg[11]/C is not reached by a timing clock -Related violations: - -TIMING-17#245 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/lfsr_reg[12]/C is not reached by a timing clock -Related violations: - -TIMING-17#246 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/lfsr_reg[13]/C is not reached by a timing clock -Related violations: - -TIMING-17#247 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/lfsr_reg[14]/C is not reached by a timing clock -Related violations: - -TIMING-17#248 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/lfsr_reg[15]/C is not reached by a timing clock -Related violations: - -TIMING-17#249 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/lfsr_reg[1]/C is not reached by a timing clock -Related violations: - -TIMING-17#250 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/lfsr_reg[2]/C is not reached by a timing clock -Related violations: - -TIMING-17#251 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/lfsr_reg[3]/C is not reached by a timing clock -Related violations: - -TIMING-17#252 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/lfsr_reg[4]/C is not reached by a timing clock -Related violations: - -TIMING-17#253 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/lfsr_reg[5]/C is not reached by a timing clock -Related violations: - -TIMING-17#254 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/lfsr_reg[6]/C is not reached by a timing clock -Related violations: - -TIMING-17#255 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/lfsr_reg[7]/C is not reached by a timing clock -Related violations: - -TIMING-17#256 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/lfsr_reg[8]/C is not reached by a timing clock -Related violations: - -TIMING-17#257 Critical Warning -Non-clocked sequential cell -The clock pin design_1_i/EnemyController_0/inst/lfsr_reg[9]/C is not reached by a timing clock -Related violations: - -DPIR-2#1 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[10]4 input pin design_1_i/ImgGen_0/inst/enemyX[10]4/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#2 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[10]4 input pin design_1_i/ImgGen_0/inst/enemyX[10]4/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#3 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[10]4 input pin design_1_i/ImgGen_0/inst/enemyX[10]4/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#4 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[10]4 input pin design_1_i/ImgGen_0/inst/enemyX[10]4/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#5 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[10]4 input pin design_1_i/ImgGen_0/inst/enemyX[10]4/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#6 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[10]4 input pin design_1_i/ImgGen_0/inst/enemyX[10]4/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#7 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[10]4 input pin design_1_i/ImgGen_0/inst/enemyX[10]4/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#8 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[10]4 input pin design_1_i/ImgGen_0/inst/enemyX[10]4/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#9 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[10]4 input pin design_1_i/ImgGen_0/inst/enemyX[10]4/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#10 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[11]4 input pin design_1_i/ImgGen_0/inst/enemyX[11]4/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#11 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[11]4 input pin design_1_i/ImgGen_0/inst/enemyX[11]4/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#12 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[11]4 input pin design_1_i/ImgGen_0/inst/enemyX[11]4/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#13 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[11]4 input pin design_1_i/ImgGen_0/inst/enemyX[11]4/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#14 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[11]4 input pin design_1_i/ImgGen_0/inst/enemyX[11]4/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#15 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[11]4 input pin design_1_i/ImgGen_0/inst/enemyX[11]4/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#16 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[11]4 input pin design_1_i/ImgGen_0/inst/enemyX[11]4/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#17 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[11]4 input pin design_1_i/ImgGen_0/inst/enemyX[11]4/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#18 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[11]4 input pin design_1_i/ImgGen_0/inst/enemyX[11]4/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#19 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[13]4 input pin design_1_i/ImgGen_0/inst/enemyX[13]4/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#20 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[13]4 input pin design_1_i/ImgGen_0/inst/enemyX[13]4/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#21 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[13]4 input pin design_1_i/ImgGen_0/inst/enemyX[13]4/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#22 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[13]4 input pin design_1_i/ImgGen_0/inst/enemyX[13]4/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#23 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[13]4 input pin design_1_i/ImgGen_0/inst/enemyX[13]4/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#24 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[13]4 input pin design_1_i/ImgGen_0/inst/enemyX[13]4/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#25 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[13]4 input pin design_1_i/ImgGen_0/inst/enemyX[13]4/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#26 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[13]4 input pin design_1_i/ImgGen_0/inst/enemyX[13]4/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#27 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[13]4 input pin design_1_i/ImgGen_0/inst/enemyX[13]4/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#28 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[14]4 input pin design_1_i/ImgGen_0/inst/enemyX[14]4/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#29 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[14]4 input pin design_1_i/ImgGen_0/inst/enemyX[14]4/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#30 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[14]4 input pin design_1_i/ImgGen_0/inst/enemyX[14]4/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#31 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[14]4 input pin design_1_i/ImgGen_0/inst/enemyX[14]4/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#32 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[14]4 input pin design_1_i/ImgGen_0/inst/enemyX[14]4/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#33 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[14]4 input pin design_1_i/ImgGen_0/inst/enemyX[14]4/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#34 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[14]4 input pin design_1_i/ImgGen_0/inst/enemyX[14]4/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#35 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[14]4 input pin design_1_i/ImgGen_0/inst/enemyX[14]4/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#36 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[14]4 input pin design_1_i/ImgGen_0/inst/enemyX[14]4/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#37 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[15]4 input pin design_1_i/ImgGen_0/inst/enemyX[15]4/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#38 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[15]4 input pin design_1_i/ImgGen_0/inst/enemyX[15]4/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#39 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[15]4 input pin design_1_i/ImgGen_0/inst/enemyX[15]4/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#40 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[15]4 input pin design_1_i/ImgGen_0/inst/enemyX[15]4/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#41 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[15]4 input pin design_1_i/ImgGen_0/inst/enemyX[15]4/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#42 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[15]4 input pin design_1_i/ImgGen_0/inst/enemyX[15]4/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#43 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[15]4 input pin design_1_i/ImgGen_0/inst/enemyX[15]4/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#44 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[15]4 input pin design_1_i/ImgGen_0/inst/enemyX[15]4/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#45 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[15]4 input pin design_1_i/ImgGen_0/inst/enemyX[15]4/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#46 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[17]4 input pin design_1_i/ImgGen_0/inst/enemyX[17]4/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#47 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[17]4 input pin design_1_i/ImgGen_0/inst/enemyX[17]4/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#48 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[17]4 input pin design_1_i/ImgGen_0/inst/enemyX[17]4/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#49 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[17]4 input pin design_1_i/ImgGen_0/inst/enemyX[17]4/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#50 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[17]4 input pin design_1_i/ImgGen_0/inst/enemyX[17]4/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#51 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[17]4 input pin design_1_i/ImgGen_0/inst/enemyX[17]4/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#52 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[17]4 input pin design_1_i/ImgGen_0/inst/enemyX[17]4/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#53 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[17]4 input pin design_1_i/ImgGen_0/inst/enemyX[17]4/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#54 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[17]4 input pin design_1_i/ImgGen_0/inst/enemyX[17]4/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#55 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[19]2 input pin design_1_i/ImgGen_0/inst/enemyX[19]2/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#56 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[19]2 input pin design_1_i/ImgGen_0/inst/enemyX[19]2/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#57 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[19]2 input pin design_1_i/ImgGen_0/inst/enemyX[19]2/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#58 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[19]2 input pin design_1_i/ImgGen_0/inst/enemyX[19]2/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#59 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[19]2 input pin design_1_i/ImgGen_0/inst/enemyX[19]2/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#60 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[19]2 input pin design_1_i/ImgGen_0/inst/enemyX[19]2/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#61 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[19]2 input pin design_1_i/ImgGen_0/inst/enemyX[19]2/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#62 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[19]2 input pin design_1_i/ImgGen_0/inst/enemyX[19]2/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#63 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[19]2 input pin design_1_i/ImgGen_0/inst/enemyX[19]2/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#64 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[1]2 input pin design_1_i/ImgGen_0/inst/enemyX[1]2/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#65 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[1]2 input pin design_1_i/ImgGen_0/inst/enemyX[1]2/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#66 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[1]2 input pin design_1_i/ImgGen_0/inst/enemyX[1]2/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#67 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[1]2 input pin design_1_i/ImgGen_0/inst/enemyX[1]2/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#68 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[1]2 input pin design_1_i/ImgGen_0/inst/enemyX[1]2/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#69 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[1]2 input pin design_1_i/ImgGen_0/inst/enemyX[1]2/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#70 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[1]2 input pin design_1_i/ImgGen_0/inst/enemyX[1]2/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#71 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[1]2 input pin design_1_i/ImgGen_0/inst/enemyX[1]2/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#72 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[1]2 input pin design_1_i/ImgGen_0/inst/enemyX[1]2/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#73 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[21]2 input pin design_1_i/ImgGen_0/inst/enemyX[21]2/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#74 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[21]2 input pin design_1_i/ImgGen_0/inst/enemyX[21]2/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#75 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[21]2 input pin design_1_i/ImgGen_0/inst/enemyX[21]2/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#76 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[21]2 input pin design_1_i/ImgGen_0/inst/enemyX[21]2/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#77 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[21]2 input pin design_1_i/ImgGen_0/inst/enemyX[21]2/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#78 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[21]2 input pin design_1_i/ImgGen_0/inst/enemyX[21]2/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#79 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[21]2 input pin design_1_i/ImgGen_0/inst/enemyX[21]2/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#80 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[21]2 input pin design_1_i/ImgGen_0/inst/enemyX[21]2/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#81 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[21]2 input pin design_1_i/ImgGen_0/inst/enemyX[21]2/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#82 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[22]2 input pin design_1_i/ImgGen_0/inst/enemyX[22]2/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#83 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[22]2 input pin design_1_i/ImgGen_0/inst/enemyX[22]2/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#84 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[22]2 input pin design_1_i/ImgGen_0/inst/enemyX[22]2/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#85 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[22]2 input pin design_1_i/ImgGen_0/inst/enemyX[22]2/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#86 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[22]2 input pin design_1_i/ImgGen_0/inst/enemyX[22]2/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#87 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[22]2 input pin design_1_i/ImgGen_0/inst/enemyX[22]2/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#88 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[22]2 input pin design_1_i/ImgGen_0/inst/enemyX[22]2/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#89 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[22]2 input pin design_1_i/ImgGen_0/inst/enemyX[22]2/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#90 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[22]2 input pin design_1_i/ImgGen_0/inst/enemyX[22]2/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#91 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[23]2 input pin design_1_i/ImgGen_0/inst/enemyX[23]2/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#92 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[23]2 input pin design_1_i/ImgGen_0/inst/enemyX[23]2/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#93 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[23]2 input pin design_1_i/ImgGen_0/inst/enemyX[23]2/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#94 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[23]2 input pin design_1_i/ImgGen_0/inst/enemyX[23]2/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#95 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[23]2 input pin design_1_i/ImgGen_0/inst/enemyX[23]2/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#96 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[23]2 input pin design_1_i/ImgGen_0/inst/enemyX[23]2/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#97 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[23]2 input pin design_1_i/ImgGen_0/inst/enemyX[23]2/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#98 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[23]2 input pin design_1_i/ImgGen_0/inst/enemyX[23]2/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#99 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[23]2 input pin design_1_i/ImgGen_0/inst/enemyX[23]2/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#100 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[2]2 input pin design_1_i/ImgGen_0/inst/enemyX[2]2/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#101 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[2]2 input pin design_1_i/ImgGen_0/inst/enemyX[2]2/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#102 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[2]2 input pin design_1_i/ImgGen_0/inst/enemyX[2]2/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#103 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[2]2 input pin design_1_i/ImgGen_0/inst/enemyX[2]2/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#104 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[2]2 input pin design_1_i/ImgGen_0/inst/enemyX[2]2/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#105 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[2]2 input pin design_1_i/ImgGen_0/inst/enemyX[2]2/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#106 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[2]2 input pin design_1_i/ImgGen_0/inst/enemyX[2]2/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#107 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[2]2 input pin design_1_i/ImgGen_0/inst/enemyX[2]2/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#108 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[2]2 input pin design_1_i/ImgGen_0/inst/enemyX[2]2/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#109 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[3]2 input pin design_1_i/ImgGen_0/inst/enemyX[3]2/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#110 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[3]2 input pin design_1_i/ImgGen_0/inst/enemyX[3]2/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#111 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[3]2 input pin design_1_i/ImgGen_0/inst/enemyX[3]2/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#112 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[3]2 input pin design_1_i/ImgGen_0/inst/enemyX[3]2/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#113 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[3]2 input pin design_1_i/ImgGen_0/inst/enemyX[3]2/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#114 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[3]2 input pin design_1_i/ImgGen_0/inst/enemyX[3]2/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#115 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[3]2 input pin design_1_i/ImgGen_0/inst/enemyX[3]2/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#116 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[3]2 input pin design_1_i/ImgGen_0/inst/enemyX[3]2/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#117 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[3]2 input pin design_1_i/ImgGen_0/inst/enemyX[3]2/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#118 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[3]2__0 input pin design_1_i/ImgGen_0/inst/enemyX[3]2__0/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#119 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[3]2__0 input pin design_1_i/ImgGen_0/inst/enemyX[3]2__0/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#120 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[3]2__0 input pin design_1_i/ImgGen_0/inst/enemyX[3]2__0/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#121 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[3]2__0 input pin design_1_i/ImgGen_0/inst/enemyX[3]2__0/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#122 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[3]2__0 input pin design_1_i/ImgGen_0/inst/enemyX[3]2__0/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#123 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[3]2__0 input pin design_1_i/ImgGen_0/inst/enemyX[3]2__0/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#124 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[3]2__0 input pin design_1_i/ImgGen_0/inst/enemyX[3]2__0/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#125 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[3]2__0 input pin design_1_i/ImgGen_0/inst/enemyX[3]2__0/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#126 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[3]2__0 input pin design_1_i/ImgGen_0/inst/enemyX[3]2__0/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#127 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[5]2 input pin design_1_i/ImgGen_0/inst/enemyX[5]2/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#128 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[5]2 input pin design_1_i/ImgGen_0/inst/enemyX[5]2/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#129 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[5]2 input pin design_1_i/ImgGen_0/inst/enemyX[5]2/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#130 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[5]2 input pin design_1_i/ImgGen_0/inst/enemyX[5]2/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#131 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[5]2 input pin design_1_i/ImgGen_0/inst/enemyX[5]2/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#132 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[5]2 input pin design_1_i/ImgGen_0/inst/enemyX[5]2/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#133 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[5]2 input pin design_1_i/ImgGen_0/inst/enemyX[5]2/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#134 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[5]2 input pin design_1_i/ImgGen_0/inst/enemyX[5]2/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#135 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[5]2 input pin design_1_i/ImgGen_0/inst/enemyX[5]2/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#136 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[7]4 input pin design_1_i/ImgGen_0/inst/enemyX[7]4/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#137 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[7]4 input pin design_1_i/ImgGen_0/inst/enemyX[7]4/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#138 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[7]4 input pin design_1_i/ImgGen_0/inst/enemyX[7]4/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#139 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[7]4 input pin design_1_i/ImgGen_0/inst/enemyX[7]4/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#140 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[7]4 input pin design_1_i/ImgGen_0/inst/enemyX[7]4/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#141 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[7]4 input pin design_1_i/ImgGen_0/inst/enemyX[7]4/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#142 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[7]4 input pin design_1_i/ImgGen_0/inst/enemyX[7]4/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#143 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[7]4 input pin design_1_i/ImgGen_0/inst/enemyX[7]4/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#144 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[7]4 input pin design_1_i/ImgGen_0/inst/enemyX[7]4/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#145 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[9]4 input pin design_1_i/ImgGen_0/inst/enemyX[9]4/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#146 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[9]4 input pin design_1_i/ImgGen_0/inst/enemyX[9]4/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#147 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[9]4 input pin design_1_i/ImgGen_0/inst/enemyX[9]4/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#148 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[9]4 input pin design_1_i/ImgGen_0/inst/enemyX[9]4/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#149 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[9]4 input pin design_1_i/ImgGen_0/inst/enemyX[9]4/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#150 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[9]4 input pin design_1_i/ImgGen_0/inst/enemyX[9]4/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#151 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[9]4 input pin design_1_i/ImgGen_0/inst/enemyX[9]4/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#152 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[9]4 input pin design_1_i/ImgGen_0/inst/enemyX[9]4/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#153 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyX[9]4 input pin design_1_i/ImgGen_0/inst/enemyX[9]4/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#154 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[11]2 input pin design_1_i/ImgGen_0/inst/enemyY[11]2/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#155 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[11]2 input pin design_1_i/ImgGen_0/inst/enemyY[11]2/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#156 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[11]2 input pin design_1_i/ImgGen_0/inst/enemyY[11]2/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#157 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[11]2 input pin design_1_i/ImgGen_0/inst/enemyY[11]2/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#158 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[11]2 input pin design_1_i/ImgGen_0/inst/enemyY[11]2/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#159 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[11]2 input pin design_1_i/ImgGen_0/inst/enemyY[11]2/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#160 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[11]2 input pin design_1_i/ImgGen_0/inst/enemyY[11]2/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#161 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[11]2 input pin design_1_i/ImgGen_0/inst/enemyY[11]2/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#162 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[11]2 input pin design_1_i/ImgGen_0/inst/enemyY[11]2/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#163 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[11]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[11]2__0/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#164 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[11]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[11]2__0/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#165 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[11]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[11]2__0/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#166 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[11]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[11]2__0/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#167 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[11]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[11]2__0/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#168 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[11]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[11]2__0/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#169 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[11]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[11]2__0/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#170 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[11]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[11]2__0/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#171 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[11]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[11]2__0/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#172 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[13]4 input pin design_1_i/ImgGen_0/inst/enemyY[13]4/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#173 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[13]4 input pin design_1_i/ImgGen_0/inst/enemyY[13]4/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#174 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[13]4 input pin design_1_i/ImgGen_0/inst/enemyY[13]4/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#175 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[13]4 input pin design_1_i/ImgGen_0/inst/enemyY[13]4/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#176 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[13]4 input pin design_1_i/ImgGen_0/inst/enemyY[13]4/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#177 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[13]4 input pin design_1_i/ImgGen_0/inst/enemyY[13]4/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#178 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[13]4 input pin design_1_i/ImgGen_0/inst/enemyY[13]4/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#179 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[13]4 input pin design_1_i/ImgGen_0/inst/enemyY[13]4/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#180 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[13]4 input pin design_1_i/ImgGen_0/inst/enemyY[13]4/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#181 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[16]4 input pin design_1_i/ImgGen_0/inst/enemyY[16]4/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#182 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[16]4 input pin design_1_i/ImgGen_0/inst/enemyY[16]4/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#183 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[16]4 input pin design_1_i/ImgGen_0/inst/enemyY[16]4/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#184 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[16]4 input pin design_1_i/ImgGen_0/inst/enemyY[16]4/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#185 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[16]4 input pin design_1_i/ImgGen_0/inst/enemyY[16]4/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#186 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[16]4 input pin design_1_i/ImgGen_0/inst/enemyY[16]4/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#187 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[16]4 input pin design_1_i/ImgGen_0/inst/enemyY[16]4/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#188 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[16]4 input pin design_1_i/ImgGen_0/inst/enemyY[16]4/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#189 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[16]4 input pin design_1_i/ImgGen_0/inst/enemyY[16]4/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#190 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[17]4 input pin design_1_i/ImgGen_0/inst/enemyY[17]4/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#191 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[17]4 input pin design_1_i/ImgGen_0/inst/enemyY[17]4/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#192 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[17]4 input pin design_1_i/ImgGen_0/inst/enemyY[17]4/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#193 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[17]4 input pin design_1_i/ImgGen_0/inst/enemyY[17]4/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#194 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[17]4 input pin design_1_i/ImgGen_0/inst/enemyY[17]4/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#195 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[17]4 input pin design_1_i/ImgGen_0/inst/enemyY[17]4/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#196 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[17]4 input pin design_1_i/ImgGen_0/inst/enemyY[17]4/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#197 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[17]4 input pin design_1_i/ImgGen_0/inst/enemyY[17]4/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#198 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[17]4 input pin design_1_i/ImgGen_0/inst/enemyY[17]4/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#199 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[19]4 input pin design_1_i/ImgGen_0/inst/enemyY[19]4/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#200 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[19]4 input pin design_1_i/ImgGen_0/inst/enemyY[19]4/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#201 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[19]4 input pin design_1_i/ImgGen_0/inst/enemyY[19]4/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#202 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[19]4 input pin design_1_i/ImgGen_0/inst/enemyY[19]4/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#203 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[19]4 input pin design_1_i/ImgGen_0/inst/enemyY[19]4/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#204 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[19]4 input pin design_1_i/ImgGen_0/inst/enemyY[19]4/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#205 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[19]4 input pin design_1_i/ImgGen_0/inst/enemyY[19]4/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#206 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[19]4 input pin design_1_i/ImgGen_0/inst/enemyY[19]4/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#207 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[19]4 input pin design_1_i/ImgGen_0/inst/enemyY[19]4/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#208 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[1]2 input pin design_1_i/ImgGen_0/inst/enemyY[1]2/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#209 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[1]2 input pin design_1_i/ImgGen_0/inst/enemyY[1]2/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#210 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[1]2 input pin design_1_i/ImgGen_0/inst/enemyY[1]2/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#211 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[1]2 input pin design_1_i/ImgGen_0/inst/enemyY[1]2/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#212 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[1]2 input pin design_1_i/ImgGen_0/inst/enemyY[1]2/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#213 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[1]2 input pin design_1_i/ImgGen_0/inst/enemyY[1]2/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#214 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[1]2 input pin design_1_i/ImgGen_0/inst/enemyY[1]2/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#215 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[1]2 input pin design_1_i/ImgGen_0/inst/enemyY[1]2/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#216 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[1]2 input pin design_1_i/ImgGen_0/inst/enemyY[1]2/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#217 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[1]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[1]2__0/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#218 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[1]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[1]2__0/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#219 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[1]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[1]2__0/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#220 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[1]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[1]2__0/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#221 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[1]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[1]2__0/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#222 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[1]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[1]2__0/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#223 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[1]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[1]2__0/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#224 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[1]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[1]2__0/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#225 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[1]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[1]2__0/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#226 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[20]4 input pin design_1_i/ImgGen_0/inst/enemyY[20]4/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#227 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[20]4 input pin design_1_i/ImgGen_0/inst/enemyY[20]4/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#228 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[20]4 input pin design_1_i/ImgGen_0/inst/enemyY[20]4/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#229 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[20]4 input pin design_1_i/ImgGen_0/inst/enemyY[20]4/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#230 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[20]4 input pin design_1_i/ImgGen_0/inst/enemyY[20]4/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#231 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[20]4 input pin design_1_i/ImgGen_0/inst/enemyY[20]4/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#232 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[20]4 input pin design_1_i/ImgGen_0/inst/enemyY[20]4/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#233 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[20]4 input pin design_1_i/ImgGen_0/inst/enemyY[20]4/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#234 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[20]4 input pin design_1_i/ImgGen_0/inst/enemyY[20]4/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#235 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[21]4 input pin design_1_i/ImgGen_0/inst/enemyY[21]4/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#236 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[21]4 input pin design_1_i/ImgGen_0/inst/enemyY[21]4/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#237 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[21]4 input pin design_1_i/ImgGen_0/inst/enemyY[21]4/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#238 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[21]4 input pin design_1_i/ImgGen_0/inst/enemyY[21]4/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#239 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[21]4 input pin design_1_i/ImgGen_0/inst/enemyY[21]4/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#240 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[21]4 input pin design_1_i/ImgGen_0/inst/enemyY[21]4/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#241 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[21]4 input pin design_1_i/ImgGen_0/inst/enemyY[21]4/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#242 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[21]4 input pin design_1_i/ImgGen_0/inst/enemyY[21]4/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#243 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[21]4 input pin design_1_i/ImgGen_0/inst/enemyY[21]4/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#244 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[23]4 input pin design_1_i/ImgGen_0/inst/enemyY[23]4/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#245 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[23]4 input pin design_1_i/ImgGen_0/inst/enemyY[23]4/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#246 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[23]4 input pin design_1_i/ImgGen_0/inst/enemyY[23]4/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#247 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[23]4 input pin design_1_i/ImgGen_0/inst/enemyY[23]4/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#248 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[23]4 input pin design_1_i/ImgGen_0/inst/enemyY[23]4/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#249 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[23]4 input pin design_1_i/ImgGen_0/inst/enemyY[23]4/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#250 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[23]4 input pin design_1_i/ImgGen_0/inst/enemyY[23]4/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#251 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[23]4 input pin design_1_i/ImgGen_0/inst/enemyY[23]4/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#252 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[23]4 input pin design_1_i/ImgGen_0/inst/enemyY[23]4/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#253 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[4]2 input pin design_1_i/ImgGen_0/inst/enemyY[4]2/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#254 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[4]2 input pin design_1_i/ImgGen_0/inst/enemyY[4]2/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#255 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[4]2 input pin design_1_i/ImgGen_0/inst/enemyY[4]2/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#256 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[4]2 input pin design_1_i/ImgGen_0/inst/enemyY[4]2/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#257 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[4]2 input pin design_1_i/ImgGen_0/inst/enemyY[4]2/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#258 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[4]2 input pin design_1_i/ImgGen_0/inst/enemyY[4]2/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#259 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[4]2 input pin design_1_i/ImgGen_0/inst/enemyY[4]2/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#260 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[4]2 input pin design_1_i/ImgGen_0/inst/enemyY[4]2/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#261 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[4]2 input pin design_1_i/ImgGen_0/inst/enemyY[4]2/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#262 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[4]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[4]2__0/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#263 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[4]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[4]2__0/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#264 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[4]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[4]2__0/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#265 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[4]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[4]2__0/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#266 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[4]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[4]2__0/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#267 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[4]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[4]2__0/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#268 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[4]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[4]2__0/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#269 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[4]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[4]2__0/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#270 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[4]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[4]2__0/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#271 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[5]2 input pin design_1_i/ImgGen_0/inst/enemyY[5]2/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#272 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[5]2 input pin design_1_i/ImgGen_0/inst/enemyY[5]2/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#273 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[5]2 input pin design_1_i/ImgGen_0/inst/enemyY[5]2/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#274 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[5]2 input pin design_1_i/ImgGen_0/inst/enemyY[5]2/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#275 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[5]2 input pin design_1_i/ImgGen_0/inst/enemyY[5]2/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#276 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[5]2 input pin design_1_i/ImgGen_0/inst/enemyY[5]2/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#277 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[5]2 input pin design_1_i/ImgGen_0/inst/enemyY[5]2/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#278 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[5]2 input pin design_1_i/ImgGen_0/inst/enemyY[5]2/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#279 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[5]2 input pin design_1_i/ImgGen_0/inst/enemyY[5]2/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#280 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[5]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[5]2__0/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#281 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[5]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[5]2__0/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#282 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[5]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[5]2__0/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#283 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[5]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[5]2__0/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#284 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[5]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[5]2__0/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#285 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[5]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[5]2__0/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#286 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[5]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[5]2__0/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#287 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[5]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[5]2__0/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#288 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[5]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[5]2__0/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#289 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[7]2 input pin design_1_i/ImgGen_0/inst/enemyY[7]2/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#290 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[7]2 input pin design_1_i/ImgGen_0/inst/enemyY[7]2/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#291 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[7]2 input pin design_1_i/ImgGen_0/inst/enemyY[7]2/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#292 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[7]2 input pin design_1_i/ImgGen_0/inst/enemyY[7]2/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#293 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[7]2 input pin design_1_i/ImgGen_0/inst/enemyY[7]2/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#294 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[7]2 input pin design_1_i/ImgGen_0/inst/enemyY[7]2/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#295 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[7]2 input pin design_1_i/ImgGen_0/inst/enemyY[7]2/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#296 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[7]2 input pin design_1_i/ImgGen_0/inst/enemyY[7]2/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#297 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[7]2 input pin design_1_i/ImgGen_0/inst/enemyY[7]2/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#298 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[7]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[7]2__0/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#299 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[7]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[7]2__0/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#300 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[7]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[7]2__0/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#301 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[7]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[7]2__0/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#302 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[7]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[7]2__0/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#303 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[7]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[7]2__0/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#304 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[7]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[7]2__0/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#305 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[7]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[7]2__0/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#306 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[7]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[7]2__0/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#307 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[8]2 input pin design_1_i/ImgGen_0/inst/enemyY[8]2/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#308 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[8]2 input pin design_1_i/ImgGen_0/inst/enemyY[8]2/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#309 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[8]2 input pin design_1_i/ImgGen_0/inst/enemyY[8]2/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#310 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[8]2 input pin design_1_i/ImgGen_0/inst/enemyY[8]2/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#311 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[8]2 input pin design_1_i/ImgGen_0/inst/enemyY[8]2/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#312 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[8]2 input pin design_1_i/ImgGen_0/inst/enemyY[8]2/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#313 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[8]2 input pin design_1_i/ImgGen_0/inst/enemyY[8]2/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#314 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[8]2 input pin design_1_i/ImgGen_0/inst/enemyY[8]2/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#315 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[8]2 input pin design_1_i/ImgGen_0/inst/enemyY[8]2/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#316 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[8]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[8]2__0/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#317 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[8]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[8]2__0/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#318 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[8]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[8]2__0/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#319 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[8]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[8]2__0/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#320 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[8]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[8]2__0/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#321 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[8]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[8]2__0/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#322 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[8]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[8]2__0/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#323 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[8]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[8]2__0/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#324 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[8]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[8]2__0/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#325 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[9]2 input pin design_1_i/ImgGen_0/inst/enemyY[9]2/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#326 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[9]2 input pin design_1_i/ImgGen_0/inst/enemyY[9]2/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#327 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[9]2 input pin design_1_i/ImgGen_0/inst/enemyY[9]2/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#328 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[9]2 input pin design_1_i/ImgGen_0/inst/enemyY[9]2/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#329 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[9]2 input pin design_1_i/ImgGen_0/inst/enemyY[9]2/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#330 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[9]2 input pin design_1_i/ImgGen_0/inst/enemyY[9]2/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#331 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[9]2 input pin design_1_i/ImgGen_0/inst/enemyY[9]2/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#332 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[9]2 input pin design_1_i/ImgGen_0/inst/enemyY[9]2/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#333 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[9]2 input pin design_1_i/ImgGen_0/inst/enemyY[9]2/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#334 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[9]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[9]2__0/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#335 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[9]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[9]2__0/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#336 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[9]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[9]2__0/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#337 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[9]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[9]2__0/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#338 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[9]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[9]2__0/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#339 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[9]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[9]2__0/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#340 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[9]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[9]2__0/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#341 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[9]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[9]2__0/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - -DPIR-2#342 Warning -Asynchronous driver check -DSP design_1_i/ImgGen_0/inst/enemyY[9]2__0 input pin design_1_i/ImgGen_0/inst/enemyY[9]2__0/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. -Related violations: - - diff --git a/SW2.runs/impl_1/design_1_wrapper_methodology_drc_routed.rpx b/SW2.runs/impl_1/design_1_wrapper_methodology_drc_routed.rpx deleted file mode 100644 index a98d13e..0000000 Binary files a/SW2.runs/impl_1/design_1_wrapper_methodology_drc_routed.rpx and /dev/null differ diff --git a/SW2.runs/impl_1/design_1_wrapper_opt.dcp b/SW2.runs/impl_1/design_1_wrapper_opt.dcp deleted file mode 100644 index 6c48be4..0000000 Binary files a/SW2.runs/impl_1/design_1_wrapper_opt.dcp and /dev/null differ diff --git a/SW2.runs/impl_1/design_1_wrapper_physopt.dcp b/SW2.runs/impl_1/design_1_wrapper_physopt.dcp deleted file mode 100644 index d8918c6..0000000 Binary files a/SW2.runs/impl_1/design_1_wrapper_physopt.dcp and /dev/null differ diff --git a/SW2.runs/impl_1/design_1_wrapper_placed.dcp b/SW2.runs/impl_1/design_1_wrapper_placed.dcp deleted file mode 100644 index d17b5ea..0000000 Binary files a/SW2.runs/impl_1/design_1_wrapper_placed.dcp and /dev/null differ diff --git a/SW2.runs/impl_1/design_1_wrapper_power_routed.rpt b/SW2.runs/impl_1/design_1_wrapper_power_routed.rpt deleted file mode 100644 index a739962..0000000 --- a/SW2.runs/impl_1/design_1_wrapper_power_routed.rpt +++ /dev/null @@ -1,176 +0,0 @@ -Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. ----------------------------------------------------------------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2025.1 (win64) Build 6140274 Thu May 22 00:12:29 MDT 2025 -| Date : Tue Jun 9 14:08:08 2026 -| Host : Lab016-04 running 64-bit major release (build 9200) -| Command : report_power -file design_1_wrapper_power_routed.rpt -pb design_1_wrapper_power_summary_routed.pb -rpx design_1_wrapper_power_routed.rpx -| Design : design_1_wrapper -| Device : xczu3eg-sfvc784-2-e -| Design State : routed -| Grade : extended -| Process : typical -| Characterization : Production ----------------------------------------------------------------------------------------------------------------------------------------------------------------------- - -Power Report - -Table of Contents ------------------ -1. Summary -1.1 On-Chip Components -1.2 Power Supply Summary -1.3 Confidence Level -2. Settings -2.1 Environment -2.2 Clock Constraints -3. Detailed Reports -3.1 By Hierarchy - -1. Summary ----------- - -+--------------------------+--------------+ -| Total On-Chip Power (W) | 0.406 | -| Design Power Budget (W) | Unspecified* | -| Power Budget Margin (W) | NA | -| Dynamic (W) | 0.163 | -| Device Static (W) | 0.244 | -| Effective TJA (C/W) | 2.4 | -| Max Ambient (C) | 99.0 | -| Junction Temperature (C) | 26.0 | -| Confidence Level | Low | -| Setting File | --- | -| Simulation Activity File | --- | -| Design Nets Matched | NA | -+--------------------------+--------------+ -* Specify Design Power Budget using, set_operating_conditions -design_power_budget - - -1.1 On-Chip Components ----------------------- - -+----------------+-----------+----------+-----------+-----------------+ -| On-Chip | Power (W) | Used | Available | Utilization (%) | -+----------------+-----------+----------+-----------+-----------------+ -| Clocks | 0.002 | 5 | --- | --- | -| CLB Logic | 0.015 | 9994 | --- | --- | -| LUT as Logic | 0.014 | 7211 | 70560 | 10.22 | -| CARRY8 | 0.001 | 763 | 8820 | 8.65 | -| Register | <0.001 | 401 | 141120 | 0.28 | -| BUFG | <0.001 | 1 | 24 | 4.17 | -| Others | 0.000 | 25 | --- | --- | -| F7/F8 Muxes | 0.000 | 19 | 70560 | 0.03 | -| Signals | 0.010 | 7352 | --- | --- | -| MMCM | 0.100 | 0 | --- | --- | -| DSPs | 0.005 | 38 | 360 | 10.56 | -| I/O | 0.030 | 16 | 252 | 6.35 | -| Static Power | 0.244 | | | | -| Total | 0.406 | | | | -+----------------+-----------+----------+-----------+-----------------+ - - -1.2 Power Supply Summary ------------------------- - -+-----------------+-------------+-----------+-------------+------------+-------------+-------------+------------+ -| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) | -+-----------------+-------------+-----------+-------------+------------+-------------+-------------+------------+ -| Vccint | 0.850 | 0.083 | 0.038 | 0.045 | NA | Unspecified | NA | -| Vccint_io | 0.850 | 0.028 | 0.002 | 0.027 | NA | Unspecified | NA | -| Vccbram | 0.850 | 0.001 | 0.000 | 0.001 | NA | Unspecified | NA | -| Vccaux | 1.800 | 0.104 | 0.056 | 0.048 | NA | Unspecified | NA | -| Vccaux_io | 1.800 | 0.030 | 0.004 | 0.025 | NA | Unspecified | NA | -| Vcco33 | 3.300 | 0.013 | 0.006 | 0.007 | NA | Unspecified | NA | -| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | -| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | -| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | -| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | -| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | -| Vcco10 | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | -| Vccadc | 1.800 | 0.008 | 0.000 | 0.008 | NA | Unspecified | NA | -| VCC_PSINTFP | 0.850 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | -| VCC_PSINTLP | 0.850 | 0.005 | 0.000 | 0.005 | NA | Unspecified | NA | -| VPS_MGTRAVCC | 0.850 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | -| VCC_PSINTFP_DDR | 0.850 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | -| VCC_PSPLL | 1.200 | 0.002 | 0.000 | 0.002 | NA | Unspecified | NA | -| VPS_MGTRAVTT | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | -| VCCO_PSDDR_504 | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | -| VCC_PSAUX | 1.800 | 0.002 | 0.000 | 0.002 | NA | Unspecified | NA | -| VCC_PSBATT | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | -| VCC_PSDDR_PLL | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | -| VCCO_PSIO0_500 | 3.300 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | -| VCCO_PSIO1_501 | 3.300 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | -| VCCO_PSIO2_502 | 3.300 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | -| VCCO_PSIO3_503 | 3.300 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | -| VCC_PSADC | 1.800 | 0.002 | 0.000 | 0.002 | NA | Unspecified | NA | -+-----------------+-------------+-----------+-------------+------------+-------------+-------------+------------+ - - -1.3 Confidence Level --------------------- - -+-----------------------------+------------+-------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ -| User Input Data | Confidence | Details | Action | -+-----------------------------+------------+-------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ -| Design implementation state | High | Design is routed | | -| Clock nodes activity | Low | User specified less than 75% of clocks | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view | -| I/O nodes activity | Medium | More than 5% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | -| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | -| Device models | High | Device models are Production | | -| | | | | -| Overall confidence level | Low | | | -+-----------------------------+------------+-------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ - - -2. Settings ------------ - -2.1 Environment ---------------- - -+-----------------------+--------------------------+ -| Ambient Temp (C) | 25.0 | -| ThetaJA (C/W) | 2.4 | -| Airflow (LFM) | 250 | -| Heat Sink | medium (Medium Profile) | -| ThetaSA (C/W) | 5.5 | -| Board Selection | medium (10"x10") | -| # of Board Layers | 12to15 (12 to 15 Layers) | -| Board Temperature (C) | 25.0 | -+-----------------------+--------------------------+ - - -2.2 Clock Constraints ---------------------- - -+-----------------------------+-------------------------------------------------------+-----------------+ -| Clock | Domain | Constraint (ns) | -+-----------------------------+-------------------------------------------------------+-----------------+ -| clk125_design_1_clk_wiz_0_0 | design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 | 8.0 | -| clk25_design_1_clk_wiz_0_0 | design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 | 40.0 | -| clk_100mhz_clk_p | clk_100mhz_clk_p | 10.0 | -+-----------------------------+-------------------------------------------------------+-----------------+ - - -3. Detailed Reports -------------------- - -3.1 By Hierarchy ----------------- - -+-----------------------+-----------+ -| Name | Power (W) | -+-----------------------+-----------+ -| design_1_wrapper | 0.163 | -| design_1_i | 0.136 | -| EnemyController_0 | 0.003 | -| inst | 0.003 | -| HDMI_TX_0 | 0.004 | -| U0 | 0.004 | -| ImgGen_0 | 0.026 | -| inst | 0.025 | -| clk_wiz_0 | 0.103 | -| inst | 0.103 | -+-----------------------+-----------+ - - diff --git a/SW2.runs/impl_1/design_1_wrapper_power_routed.rpx b/SW2.runs/impl_1/design_1_wrapper_power_routed.rpx deleted file mode 100644 index dd7b61c..0000000 Binary files a/SW2.runs/impl_1/design_1_wrapper_power_routed.rpx and /dev/null differ diff --git a/SW2.runs/impl_1/design_1_wrapper_power_summary_routed.pb b/SW2.runs/impl_1/design_1_wrapper_power_summary_routed.pb deleted file mode 100644 index 07b8f89..0000000 Binary files a/SW2.runs/impl_1/design_1_wrapper_power_summary_routed.pb and /dev/null differ diff --git a/SW2.runs/impl_1/design_1_wrapper_route_status.pb b/SW2.runs/impl_1/design_1_wrapper_route_status.pb deleted file mode 100644 index b58cad6..0000000 Binary files a/SW2.runs/impl_1/design_1_wrapper_route_status.pb and /dev/null differ diff --git a/SW2.runs/impl_1/design_1_wrapper_route_status.rpt b/SW2.runs/impl_1/design_1_wrapper_route_status.rpt deleted file mode 100644 index 10b466c..0000000 --- a/SW2.runs/impl_1/design_1_wrapper_route_status.rpt +++ /dev/null @@ -1,12 +0,0 @@ -Design Route Status - : # nets : - ------------------------------------------- : ----------- : - # of logical nets.......................... : 43639 : - # of nets not needing routing.......... : 36277 : - # of internally routed nets........ : 31068 : - # of nets with no loads............ : 5209 : - # of routable nets..................... : 7362 : - # of fully routed nets............. : 7362 : - # of nets with routing errors.......... : 0 : - ------------------------------------------- : ----------- : - diff --git a/SW2.runs/impl_1/design_1_wrapper_routed.dcp b/SW2.runs/impl_1/design_1_wrapper_routed.dcp deleted file mode 100644 index 0a2b874..0000000 Binary files a/SW2.runs/impl_1/design_1_wrapper_routed.dcp and /dev/null differ diff --git a/SW2.runs/impl_1/design_1_wrapper_timing_summary_routed.pb b/SW2.runs/impl_1/design_1_wrapper_timing_summary_routed.pb deleted file mode 100644 index b9ba13a..0000000 Binary files a/SW2.runs/impl_1/design_1_wrapper_timing_summary_routed.pb and /dev/null differ diff --git a/SW2.runs/impl_1/design_1_wrapper_timing_summary_routed.rpt b/SW2.runs/impl_1/design_1_wrapper_timing_summary_routed.rpt deleted file mode 100644 index 11f65ba..0000000 --- a/SW2.runs/impl_1/design_1_wrapper_timing_summary_routed.rpt +++ /dev/null @@ -1,9018 +0,0 @@ -Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -| Tool Version : Vivado v.2025.1 (win64) Build 6140274 Thu May 22 00:12:29 MDT 2025 -| Date : Tue Jun 9 14:08:02 2026 -| Host : Lab016-04 running 64-bit major release (build 9200) -| Command : report_timing_summary -max_paths 10 -routable_nets -report_unconstrained -file design_1_wrapper_timing_summary_routed.rpt -pb design_1_wrapper_timing_summary_routed.pb -rpx design_1_wrapper_timing_summary_routed.rpx -warn_on_violation -| Design : design_1_wrapper -| Device : xczu3eg-sfvc784 -| Speed File : -2 PRODUCTION 1.30 05-15-2022 -| Design State : Routed -| Temperature Grade : E ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - -Timing Summary Report - ------------------------------------------------------------------------------------------------- -| Timer Settings -| -------------- ------------------------------------------------------------------------------------------------- - - Enable Multi Corner Analysis : Yes - Enable Pessimism Removal : Yes - Pessimism Removal Resolution : Nearest Common Node - Enable Input Delay Default Clock : No - Enable Preset / Clear Arcs : No - Disable Flight Delays : No - Ignore I/O Paths : No - Timing Early Launch at Borrowing Latches : No - Borrow Time for Max Delay Exceptions : Yes - Merge Timing Exceptions : Yes - Inter-SLR Compensation : Conservative - - Corner Analyze Analyze - Name Max Paths Min Paths - ------ --------- --------- - Slow Yes Yes - Fast Yes Yes - - ------------------------------------------------------------------------------------------------- -| Report Methodology -| ------------------ ------------------------------------------------------------------------------------------------- - -Rule Severity Description Violations ---------- ---------------- --------------------------- ---------- -TIMING-17 Critical Warning Non-clocked sequential cell 257 -DPIR-2 Warning Asynchronous driver check 342 - -Note: This report is based on the most recent report_methodology run and may not be up-to-date. Run report_methodology on the current design for the latest report. - - - -check_timing report - -Table of Contents ------------------ -1. checking no_clock (257) -2. checking constant_clock (0) -3. checking pulse_width_clock (0) -4. checking unconstrained_internal_endpoints (747) -5. checking no_input_delay (3) -6. checking no_output_delay (11) -7. checking multiple_clock (0) -8. checking generated_clocks (0) -9. checking loops (0) -10. checking partial_input_delay (0) -11. checking partial_output_delay (0) -12. checking latch_loops (0) - -1. checking no_clock (257) --------------------------- - There are 257 register/latch pins with no clock driven by root clock pin: design_1_i/TickGenerator_0/inst/FrameTick_reg/Q (HIGH) - - -2. checking constant_clock (0) ------------------------------- - There are 0 register/latch pins with constant_clock. - - -3. checking pulse_width_clock (0) ---------------------------------- - There are 0 register/latch pins which need pulse_width check - - -4. checking unconstrained_internal_endpoints (747) --------------------------------------------------- - There are 747 pins that are not constrained for maximum delay. (HIGH) - - There are 0 pins that are not constrained for maximum delay due to constant clock. - - -5. checking no_input_delay (3) ------------------------------- - There are 3 input ports with no input delay specified. (HIGH) - - There are 0 input ports with no input delay but user has a false path constraint. - - -6. checking no_output_delay (11) --------------------------------- - There are 11 ports with no output delay specified. (HIGH) - - There are 0 ports with no output delay but user has a false path constraint - - There are 0 ports with no output delay but with a timing clock defined on it or propagating through it - - -7. checking multiple_clock (0) ------------------------------- - There are 0 register/latch pins with multiple clocks. - - -8. checking generated_clocks (0) --------------------------------- - There are 0 generated clocks that are not connected to a clock source. - - -9. checking loops (0) ---------------------- - There are 0 combinational loops in the design. - - -10. checking partial_input_delay (0) ------------------------------------- - There are 0 input ports with partial input delay specified. - - -11. checking partial_output_delay (0) -------------------------------------- - There are 0 ports with partial output delay specified. - - -12. checking latch_loops (0) ----------------------------- - There are 0 combinational latch loops in the design through latch input - - - ------------------------------------------------------------------------------------------------- -| Design Timing Summary -| --------------------- ------------------------------------------------------------------------------------------------- - - WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints - ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- - 4.182 0.000 0 220 0.041 0.000 0 220 0.000 0.000 0 157 - - -All user specified timing constraints are met. - - ------------------------------------------------------------------------------------------------- -| Clock Summary -| ------------- ------------------------------------------------------------------------------------------------- - -Clock Waveform(ns) Period(ns) Frequency(MHz) ------ ------------ ---------- -------------- -clk_100mhz_clk_p {0.000 5.000} 10.000 100.000 - clk125_design_1_clk_wiz_0_0 {0.000 4.000} 8.000 125.000 - clk25_design_1_clk_wiz_0_0 {0.000 20.000} 40.000 25.000 - - ------------------------------------------------------------------------------------------------- -| Intra Clock Table -| ----------------- ------------------------------------------------------------------------------------------------- - -Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------ ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- -clk_100mhz_clk_p 2.000 0.000 0 1 - clk125_design_1_clk_wiz_0_0 6.683 0.000 0 73 0.041 0.000 0 73 0.000 0.000 0 55 - clk25_design_1_clk_wiz_0_0 31.910 0.000 0 147 0.042 0.000 0 147 19.725 0.000 0 101 - - ------------------------------------------------------------------------------------------------- -| Inter Clock Table -| ----------------- ------------------------------------------------------------------------------------------------- - -From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ----------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -clk25_design_1_clk_wiz_0_0 clk125_design_1_clk_wiz_0_0 4.182 0.000 0 30 0.049 0.000 0 30 - - ------------------------------------------------------------------------------------------------- -| Other Path Groups Table -| ----------------------- ------------------------------------------------------------------------------------------------- - -Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ----------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- - - ------------------------------------------------------------------------------------------------- -| User Ignored Path Table -| ----------------------- ------------------------------------------------------------------------------------------------- - -Path Group From Clock To Clock ----------- ---------- -------- - - ------------------------------------------------------------------------------------------------- -| Unconstrained Path Table -| ------------------------ ------------------------------------------------------------------------------------------------- - -Path Group From Clock To Clock ----------- ---------- -------- -(none) -(none) clk125_design_1_clk_wiz_0_0 -(none) clk25_design_1_clk_wiz_0_0 -(none) clk25_design_1_clk_wiz_0_0 - - ------------------------------------------------------------------------------------------------- -| Timing Details -| -------------- ------------------------------------------------------------------------------------------------- - - ---------------------------------------------------------------------------------------------------- -From Clock: clk_100mhz_clk_p - To Clock: clk_100mhz_clk_p - -Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA -Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA -PW : 0 Failing Endpoints, Worst Slack 2.000ns, Total Violation 0.000ns ---------------------------------------------------------------------------------------------------- - - -Pulse Width Checks --------------------------------------------------------------------------------------- -Clock Name: clk_100mhz_clk_p -Waveform(ns): { 0.000 5.000 } -Period(ns): 10.000 -Sources: { clk_100mhz_clk_p } - -Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin -Min Period n/a MMCME4_ADV/CLKIN1 n/a 1.071 10.000 8.929 MMCM_X0Y2 design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKIN1 -Max Period n/a MMCME4_ADV/CLKIN1 n/a 100.000 10.000 90.000 MMCM_X0Y2 design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKIN1 -Low Pulse Width Slow MMCME4_ADV/CLKIN1 n/a 3.000 5.000 2.000 MMCM_X0Y2 design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKIN1 -Low Pulse Width Fast MMCME4_ADV/CLKIN1 n/a 3.000 5.000 2.000 MMCM_X0Y2 design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKIN1 -High Pulse Width Slow MMCME4_ADV/CLKIN1 n/a 3.000 5.000 2.000 MMCM_X0Y2 design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKIN1 -High Pulse Width Fast MMCME4_ADV/CLKIN1 n/a 3.000 5.000 2.000 MMCM_X0Y2 design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKIN1 - - - ---------------------------------------------------------------------------------------------------- -From Clock: clk125_design_1_clk_wiz_0_0 - To Clock: clk125_design_1_clk_wiz_0_0 - -Setup : 0 Failing Endpoints, Worst Slack 6.683ns, Total Violation 0.000ns -Hold : 0 Failing Endpoints, Worst Slack 0.041ns, Total Violation 0.000ns -PW : 0 Failing Endpoints, Worst Slack 0.000ns, Total Violation 0.000ns ---------------------------------------------------------------------------------------------------- - - -Max Delay Paths --------------------------------------------------------------------------------------- -Slack (MET) : 6.683ns (required time - arrival time) - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/cntMod5_reg[2]/C - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[3]/D - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk125_design_1_clk_wiz_0_0 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 8.000ns (clk125_design_1_clk_wiz_0_0 rise@8.000ns - clk125_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 1.198ns (logic 0.357ns (29.809%) route 0.841ns (70.191%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.080ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 3.523ns = ( 11.523 - 8.000 ) - Source Clock Delay (SCD): 3.203ns - Clock Pessimism Removal (CPR): -0.400ns - Clock Uncertainty: 0.064ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.108ns - Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.889ns (routing 1.034ns, distribution 0.855ns) - Clock Net Delay (Destination): 1.678ns (routing 0.938ns, distribution 0.740ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.629 0.729 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.779 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.779 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.384 1.163 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - -0.127 1.036 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.250 1.286 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.028 1.314 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.889 3.203 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X39Y18 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/cntMod5_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X39Y18 FDRE (Prop_CFF2_SLICEM_C_Q) - 0.077 3.280 f design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/cntMod5_reg[2]/Q - net (fo=9, routed) 0.217 3.497 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/cntMod5_reg_n_0_[2] - SLICE_X38Y18 LUT5 (Prop_D5LUT_SLICEL_I1_O) - 0.157 3.654 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[5]_i_5/O - net (fo=2, routed) 0.576 4.230 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[5]_i_5_n_0 - SLICE_X38Y17 LUT6 (Prop_G6LUT_SLICEL_I5_O) - 0.123 4.353 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[3]_i_1/O - net (fo=1, routed) 0.048 4.401 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[3]_i_1_n_0 - SLICE_X38Y17 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 8.000 8.000 r - D7 0.000 8.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 8.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.519 8.598 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 8.638 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 8.638 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.333 8.971 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - 0.630 9.601 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.220 9.821 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.024 9.845 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.678 11.523 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X38Y17 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[3]/C - clock pessimism -0.400 11.123 - clock uncertainty -0.064 11.059 - SLICE_X38Y17 FDRE (Setup_GFF_SLICEL_C_D) - 0.025 11.084 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[3] - ------------------------------------------------------------------- - required time 11.084 - arrival time -4.401 - ------------------------------------------------------------------- - slack 6.683 - -Slack (MET) : 6.739ns (required time - arrival time) - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/cntMod5_reg[0]/C - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[0]/D - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk125_design_1_clk_wiz_0_0 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 8.000ns (clk125_design_1_clk_wiz_0_0 rise@8.000ns - clk125_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 1.187ns (logic 0.375ns (31.604%) route 0.812ns (68.396%)) - Logic Levels: 2 (LUT3=1 LUT5=1) - Clock Path Skew: -0.035ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 3.526ns = ( 11.526 - 8.000 ) - Source Clock Delay (SCD): 3.161ns - Clock Pessimism Removal (CPR): -0.400ns - Clock Uncertainty: 0.064ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.108ns - Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.847ns (routing 1.034ns, distribution 0.813ns) - Clock Net Delay (Destination): 1.681ns (routing 0.938ns, distribution 0.743ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.629 0.729 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.779 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.779 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.384 1.163 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - -0.127 1.036 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.250 1.286 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.028 1.314 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.847 3.161 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X36Y10 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/cntMod5_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X36Y10 FDRE (Prop_DFF2_SLICEL_C_Q) - 0.081 3.242 f design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/cntMod5_reg[0]/Q - net (fo=10, routed) 0.300 3.542 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/cntMod5_reg_n_0_[0] - SLICE_X36Y10 LUT3 (Prop_B6LUT_SLICEL_I2_O) - 0.148 3.690 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[7]_i_4/O - net (fo=5, routed) 0.463 4.153 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[7]_i_4_n_0 - SLICE_X38Y10 LUT5 (Prop_D6LUT_SLICEL_I3_O) - 0.146 4.299 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[0]_i_1__0/O - net (fo=1, routed) 0.049 4.348 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[0]_i_1__0_n_0 - SLICE_X38Y10 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 8.000 8.000 r - D7 0.000 8.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 8.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.519 8.598 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 8.638 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 8.638 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.333 8.971 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - 0.630 9.601 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.220 9.821 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.024 9.845 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.681 11.526 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X38Y10 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[0]/C - clock pessimism -0.400 11.126 - clock uncertainty -0.064 11.062 - SLICE_X38Y10 FDRE (Setup_DFF_SLICEL_C_D) - 0.025 11.087 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[0] - ------------------------------------------------------------------- - required time 11.087 - arrival time -4.348 - ------------------------------------------------------------------- - slack 6.739 - -Slack (MET) : 6.761ns (required time - arrival time) - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/cntMod5_reg[2]/C - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[5]/D - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk125_design_1_clk_wiz_0_0 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 8.000ns (clk125_design_1_clk_wiz_0_0 rise@8.000ns - clk125_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 1.120ns (logic 0.283ns (25.277%) route 0.837ns (74.723%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.080ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 3.523ns = ( 11.523 - 8.000 ) - Source Clock Delay (SCD): 3.203ns - Clock Pessimism Removal (CPR): -0.400ns - Clock Uncertainty: 0.064ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.108ns - Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.889ns (routing 1.034ns, distribution 0.855ns) - Clock Net Delay (Destination): 1.678ns (routing 0.938ns, distribution 0.740ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.629 0.729 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.779 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.779 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.384 1.163 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - -0.127 1.036 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.250 1.286 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.028 1.314 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.889 3.203 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X39Y18 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/cntMod5_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X39Y18 FDRE (Prop_CFF2_SLICEM_C_Q) - 0.077 3.280 f design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/cntMod5_reg[2]/Q - net (fo=9, routed) 0.217 3.497 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/cntMod5_reg_n_0_[2] - SLICE_X38Y18 LUT5 (Prop_D5LUT_SLICEL_I1_O) - 0.157 3.654 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[5]_i_5/O - net (fo=2, routed) 0.569 4.223 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[5]_i_5_n_0 - SLICE_X38Y17 LUT6 (Prop_F6LUT_SLICEL_I5_O) - 0.049 4.272 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[5]_i_1/O - net (fo=1, routed) 0.051 4.323 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[5]_i_1_n_0 - SLICE_X38Y17 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[5]/D - ------------------------------------------------------------------- ------------------- - - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 8.000 8.000 r - D7 0.000 8.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 8.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.519 8.598 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 8.638 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 8.638 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.333 8.971 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - 0.630 9.601 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.220 9.821 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.024 9.845 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.678 11.523 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X38Y17 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[5]/C - clock pessimism -0.400 11.123 - clock uncertainty -0.064 11.059 - SLICE_X38Y17 FDRE (Setup_FFF_SLICEL_C_D) - 0.025 11.084 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[5] - ------------------------------------------------------------------- - required time 11.084 - arrival time -4.323 - ------------------------------------------------------------------- - slack 6.761 - -Slack (MET) : 6.770ns (required time - arrival time) - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[0]/C - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_ODDRE_N/D[0] - (rising edge-triggered cell OSERDESE3 clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk125_design_1_clk_wiz_0_0 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 8.000ns (clk125_design_1_clk_wiz_0_0 rise@8.000ns - clk125_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 0.847ns (logic 0.168ns (19.835%) route 0.679ns (80.165%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.111ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 3.494ns = ( 11.494 - 8.000 ) - Source Clock Delay (SCD): 3.205ns - Clock Pessimism Removal (CPR): -0.400ns - Clock Uncertainty: 0.064ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.108ns - Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.891ns (routing 1.034ns, distribution 0.857ns) - Clock Net Delay (Destination): 1.649ns (routing 0.938ns, distribution 0.711ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.629 0.729 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.779 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.779 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.384 1.163 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - -0.127 1.036 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.250 1.286 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.028 1.314 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.891 3.205 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X39Y16 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X39Y16 FDRE (Prop_DFF_SLICEM_C_Q) - 0.078 3.283 f design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[0]/Q - net (fo=2, routed) 0.198 3.481 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/D1 - SLICE_X38Y15 LUT1 (Prop_H6LUT_SLICEL_I0_O) - 0.090 3.571 r design_1_i/HDMI_TX_0/U0/i_wrap/i_ODDRE_N_i_1/O - net (fo=1, routed) 0.481 4.052 design_1_i/HDMI_TX_0/U0/i_wrap/i_ODDRE_N_i_1_n_0 - HDIOLOGIC_M_X1Y3 OSERDESE3 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_ODDRE_N/D[0] - ------------------------------------------------------------------- ------------------- - - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 8.000 8.000 r - D7 0.000 8.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 8.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.519 8.598 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 8.638 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 8.638 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.333 8.971 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - 0.630 9.601 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.220 9.821 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.024 9.845 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.649 11.494 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - HDIOLOGIC_M_X1Y3 OSERDESE3 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_ODDRE_N/CLK - clock pessimism -0.400 11.094 - clock uncertainty -0.064 11.030 - HDIOLOGIC_M_X1Y3 OSERDESE3 (Setup_OPTFF_HDIOLOGIC_M_CLK_D[0]) - -0.208 10.822 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_ODDRE_N - ------------------------------------------------------------------- - required time 10.822 - arrival time -4.052 - ------------------------------------------------------------------- - slack 6.770 - -Slack (MET) : 6.786ns (required time - arrival time) - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[0]/C - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_ODDRE_N/D[0] - (rising edge-triggered cell OSERDESE3 clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk125_design_1_clk_wiz_0_0 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 8.000ns (clk125_design_1_clk_wiz_0_0 rise@8.000ns - clk125_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 0.829ns (logic 0.228ns (27.502%) route 0.601ns (72.498%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.113ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 3.496ns = ( 11.496 - 8.000 ) - Source Clock Delay (SCD): 3.209ns - Clock Pessimism Removal (CPR): -0.400ns - Clock Uncertainty: 0.064ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.108ns - Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.895ns (routing 1.034ns, distribution 0.861ns) - Clock Net Delay (Destination): 1.651ns (routing 0.938ns, distribution 0.713ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.629 0.729 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.779 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.779 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.384 1.163 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - -0.127 1.036 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.250 1.286 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.028 1.314 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.895 3.209 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X38Y10 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X38Y10 FDRE (Prop_DFF_SLICEL_C_Q) - 0.079 3.288 f design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[0]/Q - net (fo=2, routed) 0.113 3.401 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/D1 - SLICE_X38Y10 LUT1 (Prop_G6LUT_SLICEL_I0_O) - 0.149 3.550 r design_1_i/HDMI_TX_0/U0/i_wrap/i_ODDRE_N_i_1__0/O - net (fo=1, routed) 0.488 4.038 design_1_i/HDMI_TX_0/U0/i_wrap/i_ODDRE_N_i_1__0_n_0 - HDIOLOGIC_M_X1Y2 OSERDESE3 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_ODDRE_N/D[0] - ------------------------------------------------------------------- ------------------- - - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 8.000 8.000 r - D7 0.000 8.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 8.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.519 8.598 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 8.638 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 8.638 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.333 8.971 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - 0.630 9.601 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.220 9.821 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.024 9.845 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.651 11.496 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - HDIOLOGIC_M_X1Y2 OSERDESE3 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_ODDRE_N/CLK - clock pessimism -0.400 11.096 - clock uncertainty -0.064 11.032 - HDIOLOGIC_M_X1Y2 OSERDESE3 (Setup_OPTFF_HDIOLOGIC_M_CLK_D[0]) - -0.208 10.824 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_ODDRE_N - ------------------------------------------------------------------- - required time 10.824 - arrival time -4.038 - ------------------------------------------------------------------- - slack 6.786 - -Slack (MET) : 6.845ns (required time - arrival time) - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[1]/C - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_ODDRE_N/D[4] - (rising edge-triggered cell OSERDESE3 clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk125_design_1_clk_wiz_0_0 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 8.000ns (clk125_design_1_clk_wiz_0_0 rise@8.000ns - clk125_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 0.759ns (logic 0.169ns (22.259%) route 0.590ns (77.741%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.110ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 3.494ns = ( 11.494 - 8.000 ) - Source Clock Delay (SCD): 3.204ns - Clock Pessimism Removal (CPR): -0.400ns - Clock Uncertainty: 0.064ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.108ns - Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.890ns (routing 1.034ns, distribution 0.856ns) - Clock Net Delay (Destination): 1.649ns (routing 0.938ns, distribution 0.711ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.629 0.729 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.779 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.779 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.384 1.163 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - -0.127 1.036 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.250 1.286 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.028 1.314 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.890 3.204 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X38Y17 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X38Y17 FDRE (Prop_DFF_SLICEL_C_Q) - 0.079 3.283 f design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[1]/Q - net (fo=2, routed) 0.197 3.481 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/D2 - SLICE_X38Y14 LUT1 (Prop_H6LUT_SLICEL_I0_O) - 0.090 3.571 r design_1_i/HDMI_TX_0/U0/i_wrap/i_ODDRE_N_i_2__0/O - net (fo=1, routed) 0.393 3.964 design_1_i/HDMI_TX_0/U0/i_wrap/i_ODDRE_N_i_2__0_n_0 - HDIOLOGIC_M_X1Y3 OSERDESE3 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_ODDRE_N/D[4] - ------------------------------------------------------------------- ------------------- - - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 8.000 8.000 r - D7 0.000 8.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 8.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.519 8.598 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 8.638 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 8.638 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.333 8.971 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - 0.630 9.601 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.220 9.821 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.024 9.845 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.649 11.494 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - HDIOLOGIC_M_X1Y3 OSERDESE3 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_ODDRE_N/CLK - clock pessimism -0.400 11.094 - clock uncertainty -0.064 11.030 - HDIOLOGIC_M_X1Y3 OSERDESE3 (Setup_OPTFF_HDIOLOGIC_M_CLK_D[4]) - -0.222 10.808 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_ODDRE_N - ------------------------------------------------------------------- - required time 10.808 - arrival time -3.964 - ------------------------------------------------------------------- - slack 6.845 - -Slack (MET) : 6.848ns (required time - arrival time) - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/cntMod5_reg[0]/C - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[2]/D - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk125_design_1_clk_wiz_0_0 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 8.000ns (clk125_design_1_clk_wiz_0_0 rise@8.000ns - clk125_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 1.078ns (logic 0.325ns (30.161%) route 0.753ns (69.839%)) - Logic Levels: 2 (LUT3=1 LUT5=1) - Clock Path Skew: -0.035ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 3.526ns = ( 11.526 - 8.000 ) - Source Clock Delay (SCD): 3.161ns - Clock Pessimism Removal (CPR): -0.400ns - Clock Uncertainty: 0.064ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.108ns - Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.847ns (routing 1.034ns, distribution 0.813ns) - Clock Net Delay (Destination): 1.681ns (routing 0.938ns, distribution 0.743ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.629 0.729 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.779 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.779 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.384 1.163 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - -0.127 1.036 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.250 1.286 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.028 1.314 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.847 3.161 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X36Y10 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/cntMod5_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X36Y10 FDRE (Prop_DFF2_SLICEL_C_Q) - 0.081 3.242 f design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/cntMod5_reg[0]/Q - net (fo=10, routed) 0.300 3.542 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/cntMod5_reg_n_0_[0] - SLICE_X36Y10 LUT3 (Prop_B6LUT_SLICEL_I2_O) - 0.148 3.690 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[7]_i_4/O - net (fo=5, routed) 0.403 4.093 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[7]_i_4_n_0 - SLICE_X38Y10 LUT5 (Prop_C6LUT_SLICEL_I2_O) - 0.096 4.189 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[2]_i_1__0/O - net (fo=1, routed) 0.050 4.239 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[2]_i_1__0_n_0 - SLICE_X38Y10 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 8.000 8.000 r - D7 0.000 8.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 8.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.519 8.598 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 8.638 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 8.638 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.333 8.971 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - 0.630 9.601 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.220 9.821 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.024 9.845 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.681 11.526 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X38Y10 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[2]/C - clock pessimism -0.400 11.126 - clock uncertainty -0.064 11.062 - SLICE_X38Y10 FDRE (Setup_CFF_SLICEL_C_D) - 0.025 11.087 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[2] - ------------------------------------------------------------------- - required time 11.087 - arrival time -4.239 - ------------------------------------------------------------------- - slack 6.848 - -Slack (MET) : 6.852ns (required time - arrival time) - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/cntMod5_reg[1]/C - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[5]/D - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk125_design_1_clk_wiz_0_0 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 8.000ns (clk125_design_1_clk_wiz_0_0 rise@8.000ns - clk125_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 1.070ns (logic 0.203ns (18.971%) route 0.867ns (81.029%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.039ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 3.522ns = ( 11.522 - 8.000 ) - Source Clock Delay (SCD): 3.161ns - Clock Pessimism Removal (CPR): -0.400ns - Clock Uncertainty: 0.064ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.108ns - Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.847ns (routing 1.034ns, distribution 0.813ns) - Clock Net Delay (Destination): 1.677ns (routing 0.938ns, distribution 0.739ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.629 0.729 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.779 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.779 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.384 1.163 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - -0.127 1.036 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.250 1.286 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.028 1.314 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.847 3.161 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X36Y10 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/cntMod5_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X36Y10 FDRE (Prop_CFF_SLICEL_C_Q) - 0.079 3.240 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/cntMod5_reg[1]/Q - net (fo=9, routed) 0.816 4.056 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/cntMod5_reg_n_0_[1] - SLICE_X38Y11 LUT5 (Prop_H6LUT_SLICEL_I1_O) - 0.124 4.180 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[5]_i_1__0/O - net (fo=1, routed) 0.051 4.231 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[5]_i_1__0_n_0 - SLICE_X38Y11 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[5]/D - ------------------------------------------------------------------- ------------------- - - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 8.000 8.000 r - D7 0.000 8.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 8.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.519 8.598 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 8.638 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 8.638 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.333 8.971 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - 0.630 9.601 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.220 9.821 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.024 9.845 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.677 11.522 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X38Y11 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[5]/C - clock pessimism -0.400 11.123 - clock uncertainty -0.064 11.058 - SLICE_X38Y11 FDRE (Setup_HFF_SLICEL_C_D) - 0.025 11.083 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[5] - ------------------------------------------------------------------- - required time 11.083 - arrival time -4.231 - ------------------------------------------------------------------- - slack 6.852 - -Slack (MET) : 6.910ns (required time - arrival time) - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/cntMod5_reg[0]/C - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[4]/D - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk125_design_1_clk_wiz_0_0 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 8.000ns (clk125_design_1_clk_wiz_0_0 rise@8.000ns - clk125_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 1.016ns (logic 0.265ns (26.094%) route 0.751ns (73.906%)) - Logic Levels: 2 (LUT3=1 LUT5=1) - Clock Path Skew: -0.035ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 3.526ns = ( 11.526 - 8.000 ) - Source Clock Delay (SCD): 3.161ns - Clock Pessimism Removal (CPR): -0.400ns - Clock Uncertainty: 0.064ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.108ns - Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.847ns (routing 1.034ns, distribution 0.813ns) - Clock Net Delay (Destination): 1.681ns (routing 0.938ns, distribution 0.743ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.629 0.729 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.779 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.779 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.384 1.163 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - -0.127 1.036 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.250 1.286 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.028 1.314 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.847 3.161 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X36Y10 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/cntMod5_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X36Y10 FDRE (Prop_DFF2_SLICEL_C_Q) - 0.081 3.242 f design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/cntMod5_reg[0]/Q - net (fo=10, routed) 0.300 3.542 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/cntMod5_reg_n_0_[0] - SLICE_X36Y10 LUT3 (Prop_B6LUT_SLICEL_I2_O) - 0.148 3.690 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[7]_i_4/O - net (fo=5, routed) 0.402 4.092 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[7]_i_4_n_0 - SLICE_X38Y10 LUT5 (Prop_B6LUT_SLICEL_I3_O) - 0.036 4.128 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[4]_i_1__0/O - net (fo=1, routed) 0.049 4.177 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[4]_i_1__0_n_0 - SLICE_X38Y10 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[4]/D - ------------------------------------------------------------------- ------------------- - - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 8.000 8.000 r - D7 0.000 8.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 8.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.519 8.598 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 8.638 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 8.638 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.333 8.971 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - 0.630 9.601 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.220 9.821 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.024 9.845 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.681 11.526 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X38Y10 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[4]/C - clock pessimism -0.400 11.126 - clock uncertainty -0.064 11.062 - SLICE_X38Y10 FDRE (Setup_BFF_SLICEL_C_D) - 0.025 11.087 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[4] - ------------------------------------------------------------------- - required time 11.087 - arrival time -4.177 - ------------------------------------------------------------------- - slack 6.910 - -Slack (MET) : 6.911ns (required time - arrival time) - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/cntMod5_reg[0]/C - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[6]/D - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk125_design_1_clk_wiz_0_0 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 8.000ns (clk125_design_1_clk_wiz_0_0 rise@8.000ns - clk125_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 1.015ns (logic 0.264ns (26.021%) route 0.751ns (73.979%)) - Logic Levels: 2 (LUT3=1 LUT6=1) - Clock Path Skew: -0.035ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 3.526ns = ( 11.526 - 8.000 ) - Source Clock Delay (SCD): 3.161ns - Clock Pessimism Removal (CPR): -0.400ns - Clock Uncertainty: 0.064ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.108ns - Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.847ns (routing 1.034ns, distribution 0.813ns) - Clock Net Delay (Destination): 1.681ns (routing 0.938ns, distribution 0.743ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.629 0.729 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.779 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.779 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.384 1.163 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - -0.127 1.036 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.250 1.286 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.028 1.314 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.847 3.161 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X36Y10 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/cntMod5_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X36Y10 FDRE (Prop_DFF2_SLICEL_C_Q) - 0.081 3.242 f design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/cntMod5_reg[0]/Q - net (fo=10, routed) 0.300 3.542 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/cntMod5_reg_n_0_[0] - SLICE_X36Y10 LUT3 (Prop_B6LUT_SLICEL_I2_O) - 0.148 3.690 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[7]_i_4/O - net (fo=5, routed) 0.403 4.093 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[7]_i_4_n_0 - SLICE_X38Y10 LUT6 (Prop_A6LUT_SLICEL_I4_O) - 0.035 4.128 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[6]_i_1__0/O - net (fo=1, routed) 0.048 4.176 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[6]_i_1__0_n_0 - SLICE_X38Y10 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 8.000 8.000 r - D7 0.000 8.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 8.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.519 8.598 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 8.638 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 8.638 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.333 8.971 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - 0.630 9.601 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.220 9.821 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.024 9.845 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.681 11.526 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X38Y10 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[6]/C - clock pessimism -0.400 11.126 - clock uncertainty -0.064 11.062 - SLICE_X38Y10 FDRE (Setup_AFF_SLICEL_C_D) - 0.025 11.087 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[6] - ------------------------------------------------------------------- - required time 11.087 - arrival time -4.176 - ------------------------------------------------------------------- - slack 6.911 - - - - - -Min Delay Paths --------------------------------------------------------------------------------------- -Slack (MET) : 0.041ns (arrival time - required time) - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[3]/C - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[1]/D - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk125_design_1_clk_wiz_0_0 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk125_design_1_clk_wiz_0_0 rise@0.000ns - clk125_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 0.093ns (logic 0.053ns (56.989%) route 0.040ns (43.011%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: 0.006ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.831ns - Source Clock Delay (SCD): 2.034ns - Clock Pessimism Removal (CPR): -0.208ns - Clock Net Delay (Source): 1.028ns (routing 0.568ns, distribution 0.460ns) - Clock Net Delay (Destination): 1.165ns (routing 0.637ns, distribution 0.528ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.295 0.374 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.414 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.414 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.196 0.610 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - 0.230 0.840 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.149 0.989 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.017 1.006 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.028 2.034 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X36Y11 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X36Y11 FDRE (Prop_CFF_SLICEL_C_Q) - 0.039 2.073 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[3]/Q - net (fo=1, routed) 0.024 2.097 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg_n_0_[3] - SLICE_X36Y11 LUT5 (Prop_D6LUT_SLICEL_I4_O) - 0.014 2.111 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[1]_i_1__0/O - net (fo=1, routed) 0.016 2.127 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[1]_i_1__0_n_0 - SLICE_X36Y11 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.400 0.500 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.550 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.550 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.222 0.772 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - -0.295 0.477 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.170 0.647 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.019 0.666 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.165 1.831 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X36Y11 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[1]/C - clock pessimism 0.208 2.040 - SLICE_X36Y11 FDRE (Hold_DFF_SLICEL_C_D) - 0.046 2.086 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[1] - ------------------------------------------------------------------- - required time -2.086 - arrival time 2.127 - ------------------------------------------------------------------- - slack 0.041 - -Slack (MET) : 0.042ns (arrival time - required time) - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[4]/C - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[2]/D - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk125_design_1_clk_wiz_0_0 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk125_design_1_clk_wiz_0_0 rise@0.000ns - clk125_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 0.094ns (logic 0.053ns (56.383%) route 0.041ns (43.617%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: 0.006ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.852ns - Source Clock Delay (SCD): 2.053ns - Clock Pessimism Removal (CPR): -0.206ns - Clock Net Delay (Source): 1.047ns (routing 0.568ns, distribution 0.479ns) - Clock Net Delay (Destination): 1.186ns (routing 0.637ns, distribution 0.549ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.295 0.374 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.414 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.414 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.196 0.610 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - 0.230 0.840 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.149 0.989 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.017 1.006 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.047 2.053 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X38Y10 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X38Y10 FDRE (Prop_BFF_SLICEL_C_Q) - 0.039 2.092 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[4]/Q - net (fo=1, routed) 0.024 2.116 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg_n_0_[4] - SLICE_X38Y10 LUT5 (Prop_C6LUT_SLICEL_I0_O) - 0.014 2.130 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[2]_i_1__0/O - net (fo=1, routed) 0.017 2.147 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[2]_i_1__0_n_0 - SLICE_X38Y10 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.400 0.500 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.550 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.550 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.222 0.772 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - -0.295 0.477 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.170 0.647 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.019 0.666 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.186 1.852 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X38Y10 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[2]/C - clock pessimism 0.206 2.059 - SLICE_X38Y10 FDRE (Hold_CFF_SLICEL_C_D) - 0.046 2.105 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[2] - ------------------------------------------------------------------- - required time -2.105 - arrival time 2.147 - ------------------------------------------------------------------- - slack 0.042 - -Slack (MET) : 0.052ns (arrival time - required time) - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_GBox/sReg_reg[8]/C - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_GBox/sReg_reg[6]/D - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk125_design_1_clk_wiz_0_0 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk125_design_1_clk_wiz_0_0 rise@0.000ns - clk125_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 0.121ns (logic 0.053ns (43.802%) route 0.068ns (56.198%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.023ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.839ns - Source Clock Delay (SCD): 2.036ns - Clock Pessimism Removal (CPR): -0.220ns - Clock Net Delay (Source): 1.030ns (routing 0.568ns, distribution 0.462ns) - Clock Net Delay (Destination): 1.173ns (routing 0.637ns, distribution 0.536ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.295 0.374 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.414 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.414 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.196 0.610 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - 0.230 0.840 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.149 0.989 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.017 1.006 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.030 2.036 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X37Y4 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_GBox/sReg_reg[8]/C - ------------------------------------------------------------------- ------------------- - SLICE_X37Y4 FDRE (Prop_DFF_SLICEM_C_Q) - 0.039 2.075 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_GBox/sReg_reg[8]/Q - net (fo=1, routed) 0.050 2.125 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_GBox/sReg_reg_n_0_[8] - SLICE_X37Y5 LUT6 (Prop_A6LUT_SLICEM_I5_O) - 0.014 2.139 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[6]_i_1__1/O - net (fo=1, routed) 0.018 2.157 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[6]_i_1__1_n_0 - SLICE_X37Y5 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_GBox/sReg_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.400 0.500 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.550 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.550 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.222 0.772 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - -0.295 0.477 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.170 0.647 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.019 0.666 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.173 1.839 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X37Y5 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_GBox/sReg_reg[6]/C - clock pessimism 0.220 2.060 - SLICE_X37Y5 FDRE (Hold_AFF_SLICEM_C_D) - 0.046 2.106 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_GBox/sReg_reg[6] - ------------------------------------------------------------------- - required time -2.106 - arrival time 2.157 - ------------------------------------------------------------------- - slack 0.052 - -Slack (MET) : 0.055ns (arrival time - required time) - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[8]/C - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[6]/D - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk125_design_1_clk_wiz_0_0 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk125_design_1_clk_wiz_0_0 rise@0.000ns - clk125_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 0.121ns (logic 0.052ns (42.975%) route 0.069ns (57.025%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.020ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.853ns - Source Clock Delay (SCD): 2.051ns - Clock Pessimism Removal (CPR): -0.218ns - Clock Net Delay (Source): 1.045ns (routing 0.568ns, distribution 0.477ns) - Clock Net Delay (Destination): 1.187ns (routing 0.637ns, distribution 0.550ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.295 0.374 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.414 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.414 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.196 0.610 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - 0.230 0.840 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.149 0.989 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.017 1.006 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.045 2.051 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X39Y17 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[8]/C - ------------------------------------------------------------------- ------------------- - SLICE_X39Y17 FDRE (Prop_CFF_SLICEM_C_Q) - 0.038 2.089 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[8]/Q - net (fo=1, routed) 0.051 2.140 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg_n_0_[8] - SLICE_X39Y16 LUT6 (Prop_A6LUT_SLICEM_I5_O) - 0.014 2.154 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[6]_i_1/O - net (fo=1, routed) 0.018 2.172 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[6]_i_1_n_0 - SLICE_X39Y16 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.400 0.500 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.550 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.550 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.222 0.772 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - -0.295 0.477 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.170 0.647 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.019 0.666 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.187 1.853 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X39Y16 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[6]/C - clock pessimism 0.218 2.071 - SLICE_X39Y16 FDRE (Hold_AFF_SLICEM_C_D) - 0.046 2.117 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[6] - ------------------------------------------------------------------- - required time -2.117 - arrival time 2.172 - ------------------------------------------------------------------- - slack 0.055 - -Slack (MET) : 0.061ns (arrival time - required time) - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_3/i_GBox/cntMod5_reg[1]/C - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_3/i_GBox/cntMod5_reg[2]/D - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk125_design_1_clk_wiz_0_0 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk125_design_1_clk_wiz_0_0 rise@0.000ns - clk125_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 0.114ns (logic 0.059ns (51.974%) route 0.055ns (48.026%)) - Logic Levels: 1 (LUT3=1) - Clock Path Skew: 0.006ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.824ns - Source Clock Delay (SCD): 2.027ns - Clock Pessimism Removal (CPR): -0.208ns - Clock Net Delay (Source): 1.021ns (routing 0.568ns, distribution 0.453ns) - Clock Net Delay (Destination): 1.158ns (routing 0.637ns, distribution 0.521ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.295 0.374 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.414 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.414 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.196 0.610 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - 0.230 0.840 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.149 0.989 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.017 1.006 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.021 2.027 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X36Y24 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_3/i_GBox/cntMod5_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X36Y24 FDRE (Prop_CFF_SLICEL_C_Q) - 0.039 2.066 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_3/i_GBox/cntMod5_reg[1]/Q - net (fo=6, routed) 0.049 2.114 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_3/i_GBox/cntMod5_reg_n_0_[1] - SLICE_X36Y24 LUT3 (Prop_C5LUT_SLICEL_I1_O) - 0.020 2.134 r design_1_i/HDMI_TX_0/U0/i_wrap/cntMod5[2]_i_2__2/O - net (fo=1, routed) 0.006 2.140 design_1_i/HDMI_TX_0/U0/i_wrap/cntMod5[2]_i_2__2_n_0 - SLICE_X36Y24 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_3/i_GBox/cntMod5_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.400 0.500 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.550 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.550 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.222 0.772 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - -0.295 0.477 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.170 0.647 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.019 0.666 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.158 1.824 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X36Y24 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_3/i_GBox/cntMod5_reg[2]/C - clock pessimism 0.208 2.033 - SLICE_X36Y24 FDRE (Hold_CFF2_SLICEL_C_D) - 0.047 2.080 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_3/i_GBox/cntMod5_reg[2] - ------------------------------------------------------------------- - required time -2.080 - arrival time 2.140 - ------------------------------------------------------------------- - slack 0.061 - -Slack (MET) : 0.063ns (arrival time - required time) - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_3/i_GBox/cntMod5_reg[1]/C - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_3/i_GBox/sReg_reg[3]/D - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk125_design_1_clk_wiz_0_0 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk125_design_1_clk_wiz_0_0 rise@0.000ns - clk125_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 0.126ns (logic 0.071ns (56.565%) route 0.055ns (43.435%)) - Logic Levels: 1 (LUT3=1) - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.828ns - Source Clock Delay (SCD): 2.027ns - Clock Pessimism Removal (CPR): -0.214ns - Clock Net Delay (Source): 1.021ns (routing 0.568ns, distribution 0.453ns) - Clock Net Delay (Destination): 1.162ns (routing 0.637ns, distribution 0.525ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.295 0.374 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.414 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.414 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.196 0.610 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - 0.230 0.840 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.149 0.989 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.017 1.006 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.021 2.027 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X36Y24 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_3/i_GBox/cntMod5_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X36Y24 FDRE (Prop_CFF_SLICEL_C_Q) - 0.039 2.066 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_3/i_GBox/cntMod5_reg[1]/Q - net (fo=6, routed) 0.049 2.114 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_3/i_GBox/cntMod5_reg_n_0_[1] - SLICE_X36Y24 LUT3 (Prop_H5LUT_SLICEL_I1_O) - 0.032 2.146 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[3]_i_1__2/O - net (fo=1, routed) 0.006 2.152 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[3]_i_1__2_n_0 - SLICE_X36Y24 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_3/i_GBox/sReg_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.400 0.500 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.550 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.550 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.222 0.772 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - -0.295 0.477 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.170 0.647 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.019 0.666 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.162 1.828 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X36Y24 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_3/i_GBox/sReg_reg[3]/C - clock pessimism 0.214 2.042 - SLICE_X36Y24 FDRE (Hold_HFF2_SLICEL_C_D) - 0.047 2.089 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_3/i_GBox/sReg_reg[3] - ------------------------------------------------------------------- - required time -2.089 - arrival time 2.152 - ------------------------------------------------------------------- - slack 0.063 - -Slack (MET) : 0.064ns (arrival time - required time) - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/cntMod5_reg[1]/C - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[8]/D - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk125_design_1_clk_wiz_0_0 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk125_design_1_clk_wiz_0_0 rise@0.000ns - clk125_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 0.131ns (logic 0.052ns (39.836%) route 0.079ns (60.164%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.020ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.853ns - Source Clock Delay (SCD): 2.051ns - Clock Pessimism Removal (CPR): -0.218ns - Clock Net Delay (Source): 1.045ns (routing 0.568ns, distribution 0.477ns) - Clock Net Delay (Destination): 1.187ns (routing 0.637ns, distribution 0.550ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.295 0.374 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.414 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.414 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.196 0.610 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - 0.230 0.840 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.149 0.989 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.017 1.006 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.045 2.051 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X39Y18 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/cntMod5_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X39Y18 FDRE (Prop_CFF_SLICEM_C_Q) - 0.038 2.089 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/cntMod5_reg[1]/Q - net (fo=10, routed) 0.055 2.144 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/cntMod5_reg_n_0_[1] - SLICE_X39Y17 LUT6 (Prop_C6LUT_SLICEM_I1_O) - 0.014 2.158 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[8]_i_1/O - net (fo=1, routed) 0.024 2.182 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[8]_i_1_n_0 - SLICE_X39Y17 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.400 0.500 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.550 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.550 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.222 0.772 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - -0.295 0.477 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.170 0.647 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.019 0.666 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.187 1.853 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X39Y17 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[8]/C - clock pessimism 0.218 2.071 - SLICE_X39Y17 FDRE (Hold_CFF_SLICEM_C_D) - 0.046 2.117 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[8] - ------------------------------------------------------------------- - required time -2.117 - arrival time 2.182 - ------------------------------------------------------------------- - slack 0.064 - -Slack (MET) : 0.065ns (arrival time - required time) - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_GBox/cntMod5_reg[1]/C - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_GBox/cntMod5_reg[2]/D - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk125_design_1_clk_wiz_0_0 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk125_design_1_clk_wiz_0_0 rise@0.000ns - clk125_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 0.118ns (logic 0.059ns (49.995%) route 0.059ns (50.005%)) - Logic Levels: 1 (LUT3=1) - Clock Path Skew: 0.006ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.833ns - Source Clock Delay (SCD): 2.035ns - Clock Pessimism Removal (CPR): -0.207ns - Clock Net Delay (Source): 1.029ns (routing 0.568ns, distribution 0.461ns) - Clock Net Delay (Destination): 1.167ns (routing 0.637ns, distribution 0.530ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.295 0.374 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.414 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.414 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.196 0.610 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - 0.230 0.840 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.149 0.989 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.017 1.006 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.029 2.035 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X36Y3 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_GBox/cntMod5_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X36Y3 FDRE (Prop_CFF_SLICEL_C_Q) - 0.039 2.074 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_GBox/cntMod5_reg[1]/Q - net (fo=9, routed) 0.053 2.127 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_GBox/cntMod5_reg_n_0_[1] - SLICE_X36Y3 LUT3 (Prop_C5LUT_SLICEL_I1_O) - 0.020 2.147 r design_1_i/HDMI_TX_0/U0/i_wrap/cntMod5[2]_i_2__1/O - net (fo=1, routed) 0.006 2.153 design_1_i/HDMI_TX_0/U0/i_wrap/cntMod5[2]_i_2__1_n_0 - SLICE_X36Y3 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_GBox/cntMod5_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.400 0.500 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.550 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.550 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.222 0.772 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - -0.295 0.477 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.170 0.647 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.019 0.666 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.167 1.833 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X36Y3 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_GBox/cntMod5_reg[2]/C - clock pessimism 0.207 2.041 - SLICE_X36Y3 FDRE (Hold_CFF2_SLICEL_C_D) - 0.047 2.088 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_GBox/cntMod5_reg[2] - ------------------------------------------------------------------- - required time -2.088 - arrival time 2.153 - ------------------------------------------------------------------- - slack 0.065 - -Slack (MET) : 0.066ns (arrival time - required time) - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[6]/C - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[4]/D - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk125_design_1_clk_wiz_0_0 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk125_design_1_clk_wiz_0_0 rise@0.000ns - clk125_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 0.118ns (logic 0.052ns (44.068%) route 0.066ns (55.932%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.006ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.853ns - Source Clock Delay (SCD): 2.052ns - Clock Pessimism Removal (CPR): -0.205ns - Clock Net Delay (Source): 1.046ns (routing 0.568ns, distribution 0.478ns) - Clock Net Delay (Destination): 1.187ns (routing 0.637ns, distribution 0.550ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.295 0.374 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.414 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.414 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.196 0.610 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - 0.230 0.840 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.149 0.989 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.017 1.006 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.046 2.052 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X39Y16 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[6]/C - ------------------------------------------------------------------- ------------------- - SLICE_X39Y16 FDRE (Prop_AFF_SLICEM_C_Q) - 0.038 2.090 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[6]/Q - net (fo=1, routed) 0.045 2.135 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg_n_0_[6] - SLICE_X39Y16 LUT6 (Prop_B6LUT_SLICEM_I5_O) - 0.014 2.149 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[4]_i_1/O - net (fo=1, routed) 0.021 2.170 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[4]_i_1_n_0 - SLICE_X39Y16 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[4]/D - ------------------------------------------------------------------- ------------------- - - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.400 0.500 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.550 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.550 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.222 0.772 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - -0.295 0.477 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.170 0.647 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.019 0.666 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.187 1.853 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X39Y16 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[4]/C - clock pessimism 0.205 2.058 - SLICE_X39Y16 FDRE (Hold_BFF_SLICEM_C_D) - 0.046 2.104 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[4] - ------------------------------------------------------------------- - required time -2.104 - arrival time 2.170 - ------------------------------------------------------------------- - slack 0.066 - -Slack (MET) : 0.067ns (arrival time - required time) - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_GBox/sReg_reg[7]/C - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_GBox/sReg_reg[5]/D - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk125_design_1_clk_wiz_0_0 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk125_design_1_clk_wiz_0_0 rise@0.000ns - clk125_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 0.119ns (logic 0.079ns (66.387%) route 0.040ns (33.613%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: 0.006ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.833ns - Source Clock Delay (SCD): 2.034ns - Clock Pessimism Removal (CPR): -0.207ns - Clock Net Delay (Source): 1.028ns (routing 0.568ns, distribution 0.460ns) - Clock Net Delay (Destination): 1.167ns (routing 0.637ns, distribution 0.530ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.295 0.374 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.414 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.414 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.196 0.610 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - 0.230 0.840 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.149 0.989 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.017 1.006 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.028 2.034 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X36Y4 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_GBox/sReg_reg[7]/C - ------------------------------------------------------------------- ------------------- - SLICE_X36Y4 FDRE (Prop_FFF_SLICEL_C_Q) - 0.039 2.073 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_GBox/sReg_reg[7]/Q - net (fo=1, routed) 0.024 2.097 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_GBox/sReg_reg_n_0_[7] - SLICE_X36Y4 LUT5 (Prop_G6LUT_SLICEL_I4_O) - 0.040 2.137 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[5]_i_1__1/O - net (fo=1, routed) 0.016 2.153 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[5]_i_1__1_n_0 - SLICE_X36Y4 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_GBox/sReg_reg[5]/D - ------------------------------------------------------------------- ------------------- - - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.400 0.500 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.550 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.550 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.222 0.772 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - -0.295 0.477 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.170 0.647 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.019 0.666 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.167 1.833 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X36Y4 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_GBox/sReg_reg[5]/C - clock pessimism 0.207 2.040 - SLICE_X36Y4 FDRE (Hold_GFF_SLICEL_C_D) - 0.046 2.086 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_GBox/sReg_reg[5] - ------------------------------------------------------------------- - required time -2.086 - arrival time 2.153 - ------------------------------------------------------------------- - slack 0.067 - - - - - -Pulse Width Checks --------------------------------------------------------------------------------------- -Clock Name: clk125_design_1_clk_wiz_0_0 -Waveform(ns): { 0.000 4.000 } -Period(ns): 8.000 -Sources: { design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 } - -Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin -Min Period n/a OSERDESE3/CLK n/a 8.000 8.000 0.000 HDIOLOGIC_M_X1Y3 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_ODDRE_N/CLK -Min Period n/a OSERDESE3/CLK n/a 8.000 8.000 0.000 HDIOLOGIC_S_X1Y3 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_ODDRE_P/CLK -Min Period n/a OSERDESE3/CLK n/a 8.000 8.000 0.000 HDIOLOGIC_M_X1Y2 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_ODDRE_N/CLK -Min Period n/a OSERDESE3/CLK n/a 8.000 8.000 0.000 HDIOLOGIC_S_X1Y2 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_ODDRE_P/CLK -Min Period n/a OSERDESE3/CLK n/a 8.000 8.000 0.000 HDIOLOGIC_S_X1Y1 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_ODDRE_N/CLK -Min Period n/a OSERDESE3/CLK n/a 8.000 8.000 0.000 HDIOLOGIC_M_X1Y1 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_ODDRE_P/CLK -Min Period n/a OSERDESE3/CLK n/a 8.000 8.000 0.000 HDIOLOGIC_M_X1Y5 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_3/i_ODDRE_N/CLK -Min Period n/a OSERDESE3/CLK n/a 8.000 8.000 0.000 HDIOLOGIC_S_X1Y5 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_3/i_ODDRE_P/CLK -Min Period n/a BUFGCE/I n/a 1.290 8.000 6.710 BUFGCE_X0Y54 design_1_i/clk_wiz_0/inst/clkout2_buf/I -Min Period n/a MMCME4_ADV/CLKOUT1 n/a 1.071 8.000 6.929 MMCM_X0Y2 design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 -Low Pulse Width Slow OSERDESE3/CLK n/a 4.000 4.000 0.000 HDIOLOGIC_M_X1Y3 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_ODDRE_N/CLK -Low Pulse Width Fast OSERDESE3/CLK n/a 4.000 4.000 0.000 HDIOLOGIC_M_X1Y3 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_ODDRE_N/CLK -Low Pulse Width Slow OSERDESE3/CLK n/a 4.000 4.000 0.000 HDIOLOGIC_S_X1Y3 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_ODDRE_P/CLK -Low Pulse Width Fast OSERDESE3/CLK n/a 4.000 4.000 0.000 HDIOLOGIC_S_X1Y3 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_ODDRE_P/CLK -Low Pulse Width Slow OSERDESE3/CLK n/a 4.000 4.000 0.000 HDIOLOGIC_M_X1Y2 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_ODDRE_N/CLK -Low Pulse Width Fast OSERDESE3/CLK n/a 4.000 4.000 0.000 HDIOLOGIC_M_X1Y2 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_ODDRE_N/CLK -Low Pulse Width Slow OSERDESE3/CLK n/a 4.000 4.000 0.000 HDIOLOGIC_S_X1Y2 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_ODDRE_P/CLK -Low Pulse Width Fast OSERDESE3/CLK n/a 4.000 4.000 0.000 HDIOLOGIC_S_X1Y2 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_ODDRE_P/CLK -Low Pulse Width Slow OSERDESE3/CLK n/a 4.000 4.000 0.000 HDIOLOGIC_S_X1Y1 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_ODDRE_N/CLK -Low Pulse Width Fast OSERDESE3/CLK n/a 4.000 4.000 0.000 HDIOLOGIC_S_X1Y1 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_ODDRE_N/CLK -High Pulse Width Slow OSERDESE3/CLK n/a 4.000 4.000 0.000 HDIOLOGIC_M_X1Y3 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_ODDRE_N/CLK -High Pulse Width Fast OSERDESE3/CLK n/a 4.000 4.000 0.000 HDIOLOGIC_M_X1Y3 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_ODDRE_N/CLK -High Pulse Width Slow OSERDESE3/CLK n/a 4.000 4.000 0.000 HDIOLOGIC_S_X1Y3 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_ODDRE_P/CLK -High Pulse Width Fast OSERDESE3/CLK n/a 4.000 4.000 0.000 HDIOLOGIC_S_X1Y3 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_ODDRE_P/CLK -High Pulse Width Slow OSERDESE3/CLK n/a 4.000 4.000 0.000 HDIOLOGIC_M_X1Y2 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_ODDRE_N/CLK -High Pulse Width Fast OSERDESE3/CLK n/a 4.000 4.000 0.000 HDIOLOGIC_M_X1Y2 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_ODDRE_N/CLK -High Pulse Width Slow OSERDESE3/CLK n/a 4.000 4.000 0.000 HDIOLOGIC_S_X1Y2 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_ODDRE_P/CLK -High Pulse Width Fast OSERDESE3/CLK n/a 4.000 4.000 0.000 HDIOLOGIC_S_X1Y2 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_ODDRE_P/CLK -High Pulse Width Slow OSERDESE3/CLK n/a 4.000 4.000 0.000 HDIOLOGIC_S_X1Y1 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_ODDRE_N/CLK -High Pulse Width Fast OSERDESE3/CLK n/a 4.000 4.000 0.000 HDIOLOGIC_S_X1Y1 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_ODDRE_N/CLK - - - ---------------------------------------------------------------------------------------------------- -From Clock: clk25_design_1_clk_wiz_0_0 - To Clock: clk25_design_1_clk_wiz_0_0 - -Setup : 0 Failing Endpoints, Worst Slack 31.910ns, Total Violation 0.000ns -Hold : 0 Failing Endpoints, Worst Slack 0.042ns, Total Violation 0.000ns -PW : 0 Failing Endpoints, Worst Slack 19.725ns, Total Violation 0.000ns ---------------------------------------------------------------------------------------------------- - - -Max Delay Paths --------------------------------------------------------------------------------------- -Slack (MET) : 31.910ns (required time - arrival time) - Source: design_1_i/VideoTiming_0/inst/cntY_reg[9]/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[3]/D - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk25_design_1_clk_wiz_0_0 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (clk25_design_1_clk_wiz_0_0 rise@40.000ns - clk25_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 7.989ns (logic 1.125ns (14.081%) route 6.864ns (85.919%)) - Logic Levels: 10 (LUT2=2 LUT4=1 LUT6=7) - Clock Path Skew: -0.044ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 3.698ns = ( 43.698 - 40.000 ) - Source Clock Delay (SCD): 3.362ns - Clock Pessimism Removal (CPR): -0.380ns - Clock Uncertainty: 0.082ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.000ns - Clock Net Delay (Source): 2.054ns (routing 1.172ns, distribution 0.882ns) - Clock Net Delay (Destination): 1.859ns (routing 1.063ns, distribution 0.796ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.629 0.729 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.779 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.779 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.384 1.163 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - -0.127 1.036 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.244 1.280 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.028 1.308 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 2.054 3.362 design_1_i/VideoTiming_0/inst/pixClk - SLICE_X32Y21 FDRE r design_1_i/VideoTiming_0/inst/cntY_reg[9]/C - ------------------------------------------------------------------- ------------------- - SLICE_X32Y21 FDRE (Prop_EFF_SLICEL_C_Q) - 0.079 3.441 f design_1_i/VideoTiming_0/inst/cntY_reg[9]/Q - net (fo=106, routed) 1.976 5.417 design_1_i/ImgGen_0/inst/PosY[9] - SLICE_X23Y14 LUT6 (Prop_H6LUT_SLICEL_I0_O) - 0.150 5.567 r design_1_i/ImgGen_0/inst/R[5]_INST_0_i_33/O - net (fo=12, routed) 0.223 5.790 design_1_i/ImgGen_0/inst/R[5]_INST_0_i_33_n_0 - SLICE_X22Y13 LUT4 (Prop_C6LUT_SLICEL_I3_O) - 0.088 5.878 r design_1_i/ImgGen_0/inst/R[5]_INST_0_i_21/O - net (fo=10, routed) 0.256 6.134 design_1_i/ImgGen_0/inst/R[5]_INST_0_i_21_n_0 - SLICE_X22Y16 LUT6 (Prop_E6LUT_SLICEL_I0_O) - 0.123 6.257 r design_1_i/ImgGen_0/inst/R[5]_INST_0_i_8/O - net (fo=463, routed) 1.896 8.153 design_1_i/ImgGen_0/inst/PosX_5_sn_1 - SLICE_X30Y17 LUT6 (Prop_F6LUT_SLICEL_I0_O) - 0.049 8.202 f design_1_i/ImgGen_0/inst/R[7]_INST_0_i_70/O - net (fo=3, routed) 0.058 8.260 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_70_n_0 - SLICE_X30Y17 LUT6 (Prop_B6LUT_SLICEL_I5_O) - 0.148 8.408 r design_1_i/ImgGen_0/inst/R[6]_INST_0_i_93/O - net (fo=1, routed) 0.088 8.496 design_1_i/ImgGen_0/inst/R[6]_INST_0_i_93_n_0 - SLICE_X30Y18 LUT6 (Prop_H6LUT_SLICEL_I1_O) - 0.099 8.595 r design_1_i/ImgGen_0/inst/R[6]_INST_0_i_32/O - net (fo=11, routed) 0.986 9.581 design_1_i/ImgGen_0/inst/PosX[4]_8 - SLICE_X36Y9 LUT2 (Prop_D6LUT_SLICEL_I1_O) - 0.122 9.703 f design_1_i/ImgGen_0/inst/B[0]_INST_0_i_4/O - net (fo=3, routed) 0.463 10.167 design_1_i/ImgGen_0/inst/R[6]_INST_0_i_32_0 - SLICE_X31Y11 LUT2 (Prop_H6LUT_SLICEM_I1_O) - 0.090 10.257 f design_1_i/ImgGen_0/inst/R[0]_INST_0_i_7/O - net (fo=1, routed) 0.193 10.450 design_1_i/ImgGen_0/inst/R[0]_INST_0_i_7_n_0 - SLICE_X31Y10 LUT6 (Prop_D6LUT_SLICEM_I2_O) - 0.088 10.538 r design_1_i/ImgGen_0/inst/R[0]_INST_0_i_2/O - net (fo=1, routed) 0.088 10.626 design_1_i/ImgGen_0/inst/R[0]_INST_0_i_2_n_0 - SLICE_X30Y10 LUT6 (Prop_G6LUT_SLICEL_I1_O) - 0.089 10.715 r design_1_i/ImgGen_0/inst/R[0]_INST_0/O - net (fo=2, routed) 0.637 11.352 design_1_i/HDMI_TX_0/U0/i_wrap/R[3] - SLICE_X36Y6 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 40.000 40.000 r - D7 0.000 40.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 40.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.519 40.598 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 40.638 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 40.638 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.333 40.971 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - 0.630 41.601 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.214 41.815 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.024 41.839 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.859 43.698 design_1_i/HDMI_TX_0/U0/i_wrap/pxClk - SLICE_X36Y6 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[3]/C - clock pessimism -0.380 43.319 - clock uncertainty -0.082 43.237 - SLICE_X36Y6 FDRE (Setup_EFF2_SLICEL_C_D) - 0.025 43.262 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[3] - ------------------------------------------------------------------- - required time 43.262 - arrival time -11.352 - ------------------------------------------------------------------- - slack 31.910 - -Slack (MET) : 31.961ns (required time - arrival time) - Source: design_1_i/VideoTiming_0/inst/cntY_reg[9]/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/qD_reg[0]/D - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk25_design_1_clk_wiz_0_0 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (clk25_design_1_clk_wiz_0_0 rise@40.000ns - clk25_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 7.933ns (logic 1.017ns (12.819%) route 6.916ns (87.181%)) - Logic Levels: 9 (LUT2=1 LUT4=1 LUT6=7) - Clock Path Skew: -0.049ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 3.693ns = ( 43.693 - 40.000 ) - Source Clock Delay (SCD): 3.362ns - Clock Pessimism Removal (CPR): -0.380ns - Clock Uncertainty: 0.082ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.000ns - Clock Net Delay (Source): 2.054ns (routing 1.172ns, distribution 0.882ns) - Clock Net Delay (Destination): 1.854ns (routing 1.063ns, distribution 0.791ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.629 0.729 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.779 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.779 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.384 1.163 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - -0.127 1.036 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.244 1.280 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.028 1.308 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 2.054 3.362 design_1_i/VideoTiming_0/inst/pixClk - SLICE_X32Y21 FDRE r design_1_i/VideoTiming_0/inst/cntY_reg[9]/C - ------------------------------------------------------------------- ------------------- - SLICE_X32Y21 FDRE (Prop_EFF_SLICEL_C_Q) - 0.079 3.441 f design_1_i/VideoTiming_0/inst/cntY_reg[9]/Q - net (fo=106, routed) 1.976 5.417 design_1_i/ImgGen_0/inst/PosY[9] - SLICE_X23Y14 LUT6 (Prop_H6LUT_SLICEL_I0_O) - 0.150 5.567 r design_1_i/ImgGen_0/inst/R[5]_INST_0_i_33/O - net (fo=12, routed) 0.223 5.790 design_1_i/ImgGen_0/inst/R[5]_INST_0_i_33_n_0 - SLICE_X22Y13 LUT4 (Prop_C6LUT_SLICEL_I3_O) - 0.088 5.878 r design_1_i/ImgGen_0/inst/R[5]_INST_0_i_21/O - net (fo=10, routed) 0.256 6.134 design_1_i/ImgGen_0/inst/R[5]_INST_0_i_21_n_0 - SLICE_X22Y16 LUT6 (Prop_E6LUT_SLICEL_I0_O) - 0.123 6.257 r design_1_i/ImgGen_0/inst/R[5]_INST_0_i_8/O - net (fo=463, routed) 1.896 8.153 design_1_i/ImgGen_0/inst/PosX_5_sn_1 - SLICE_X30Y17 LUT6 (Prop_F6LUT_SLICEL_I0_O) - 0.049 8.202 f design_1_i/ImgGen_0/inst/R[7]_INST_0_i_70/O - net (fo=3, routed) 0.058 8.260 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_70_n_0 - SLICE_X30Y17 LUT6 (Prop_B6LUT_SLICEL_I5_O) - 0.148 8.408 r design_1_i/ImgGen_0/inst/R[6]_INST_0_i_93/O - net (fo=1, routed) 0.088 8.496 design_1_i/ImgGen_0/inst/R[6]_INST_0_i_93_n_0 - SLICE_X30Y18 LUT6 (Prop_H6LUT_SLICEL_I1_O) - 0.099 8.595 r design_1_i/ImgGen_0/inst/R[6]_INST_0_i_32/O - net (fo=11, routed) 0.986 9.581 design_1_i/ImgGen_0/inst/PosX[4]_8 - SLICE_X36Y9 LUT2 (Prop_D6LUT_SLICEL_I1_O) - 0.122 9.703 f design_1_i/ImgGen_0/inst/B[0]_INST_0_i_4/O - net (fo=3, routed) 0.380 10.084 design_1_i/ImgGen_0/inst_n_114 - SLICE_X30Y10 LUT6 (Prop_C6LUT_SLICEL_I5_O) - 0.123 10.207 r design_1_i/ImgGen_0/B[0]_INST_0_i_1/O - net (fo=1, routed) 0.041 10.248 design_1_i/ImgGen_0/B[0]_INST_0_i_1_n_0 - SLICE_X30Y10 LUT6 (Prop_D6LUT_SLICEL_I3_O) - 0.036 10.284 r design_1_i/ImgGen_0/B[0]_INST_0/O - net (fo=4, routed) 1.012 11.296 design_1_i/HDMI_TX_0/U0/i_wrap/G[0] - SLICE_X36Y16 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/qD_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 40.000 40.000 r - D7 0.000 40.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 40.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.519 40.598 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 40.638 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 40.638 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.333 40.971 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - 0.630 41.601 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.214 41.815 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.024 41.839 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.854 43.693 design_1_i/HDMI_TX_0/U0/i_wrap/pxClk - SLICE_X36Y16 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/qD_reg[0]/C - clock pessimism -0.380 43.314 - clock uncertainty -0.082 43.232 - SLICE_X36Y16 FDRE (Setup_FFF2_SLICEL_C_D) - 0.025 43.257 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/qD_reg[0] - ------------------------------------------------------------------- - required time 43.257 - arrival time -11.296 - ------------------------------------------------------------------- - slack 31.961 - -Slack (MET) : 31.984ns (required time - arrival time) - Source: design_1_i/VideoTiming_0/inst/cntY_reg[9]/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/qD_reg[7]/D - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk25_design_1_clk_wiz_0_0 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (clk25_design_1_clk_wiz_0_0 rise@40.000ns - clk25_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 7.916ns (logic 1.225ns (15.475%) route 6.691ns (84.525%)) - Logic Levels: 10 (LUT2=1 LUT4=1 LUT5=1 LUT6=7) - Clock Path Skew: -0.043ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 3.699ns = ( 43.699 - 40.000 ) - Source Clock Delay (SCD): 3.362ns - Clock Pessimism Removal (CPR): -0.380ns - Clock Uncertainty: 0.082ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.000ns - Clock Net Delay (Source): 2.054ns (routing 1.172ns, distribution 0.882ns) - Clock Net Delay (Destination): 1.860ns (routing 1.063ns, distribution 0.797ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.629 0.729 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.779 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.779 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.384 1.163 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - -0.127 1.036 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.244 1.280 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.028 1.308 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 2.054 3.362 design_1_i/VideoTiming_0/inst/pixClk - SLICE_X32Y21 FDRE r design_1_i/VideoTiming_0/inst/cntY_reg[9]/C - ------------------------------------------------------------------- ------------------- - SLICE_X32Y21 FDRE (Prop_EFF_SLICEL_C_Q) - 0.079 3.441 f design_1_i/VideoTiming_0/inst/cntY_reg[9]/Q - net (fo=106, routed) 1.976 5.417 design_1_i/ImgGen_0/inst/PosY[9] - SLICE_X23Y14 LUT6 (Prop_H6LUT_SLICEL_I0_O) - 0.150 5.567 r design_1_i/ImgGen_0/inst/R[5]_INST_0_i_33/O - net (fo=12, routed) 0.223 5.790 design_1_i/ImgGen_0/inst/R[5]_INST_0_i_33_n_0 - SLICE_X22Y13 LUT4 (Prop_C6LUT_SLICEL_I3_O) - 0.088 5.878 r design_1_i/ImgGen_0/inst/R[5]_INST_0_i_21/O - net (fo=10, routed) 0.256 6.134 design_1_i/ImgGen_0/inst/R[5]_INST_0_i_21_n_0 - SLICE_X22Y16 LUT6 (Prop_E6LUT_SLICEL_I0_O) - 0.123 6.257 r design_1_i/ImgGen_0/inst/R[5]_INST_0_i_8/O - net (fo=463, routed) 1.896 8.153 design_1_i/ImgGen_0/inst/PosX_5_sn_1 - SLICE_X30Y17 LUT6 (Prop_F6LUT_SLICEL_I0_O) - 0.049 8.202 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_70/O - net (fo=3, routed) 0.058 8.260 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_70_n_0 - SLICE_X30Y17 LUT6 (Prop_B6LUT_SLICEL_I5_O) - 0.148 8.408 f design_1_i/ImgGen_0/inst/R[6]_INST_0_i_93/O - net (fo=1, routed) 0.088 8.496 design_1_i/ImgGen_0/inst/R[6]_INST_0_i_93_n_0 - SLICE_X30Y18 LUT6 (Prop_H6LUT_SLICEL_I1_O) - 0.099 8.595 f design_1_i/ImgGen_0/inst/R[6]_INST_0_i_32/O - net (fo=11, routed) 0.342 8.937 design_1_i/ImgGen_0/inst/PosX[4]_8 - SLICE_X34Y16 LUT5 (Prop_D5LUT_SLICEM_I4_O) - 0.066 9.003 f design_1_i/ImgGen_0/inst/R[7]_INST_0_i_29/O - net (fo=1, routed) 0.285 9.288 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_29_n_0 - SLICE_X32Y15 LUT6 (Prop_F6LUT_SLICEL_I1_O) - 0.148 9.436 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_7/O - net (fo=1, routed) 0.420 9.856 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_7_n_0 - SLICE_X34Y11 LUT6 (Prop_H6LUT_SLICEM_I5_O) - 0.152 10.008 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_1/O - net (fo=2, routed) 0.315 10.323 design_1_i/ImgGen_0/inst_n_16 - SLICE_X36Y9 LUT2 (Prop_F6LUT_SLICEL_I0_O) - 0.123 10.446 r design_1_i/ImgGen_0/B[7]_INST_0/O - net (fo=2, routed) 0.833 11.278 design_1_i/HDMI_TX_0/U0/i_wrap/G[7] - SLICE_X37Y16 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/qD_reg[7]/D - ------------------------------------------------------------------- ------------------- - - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 40.000 40.000 r - D7 0.000 40.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 40.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.519 40.598 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 40.638 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 40.638 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.333 40.971 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - 0.630 41.601 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.214 41.815 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.024 41.839 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.860 43.699 design_1_i/HDMI_TX_0/U0/i_wrap/pxClk - SLICE_X37Y16 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/qD_reg[7]/C - clock pessimism -0.380 43.320 - clock uncertainty -0.082 43.238 - SLICE_X37Y16 FDRE (Setup_EFF_SLICEM_C_D) - 0.025 43.263 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/qD_reg[7] - ------------------------------------------------------------------- - required time 43.263 - arrival time -11.278 - ------------------------------------------------------------------- - slack 31.984 - -Slack (MET) : 31.994ns (required time - arrival time) - Source: design_1_i/VideoTiming_0/inst/cntY_reg[9]/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[0]/D - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk25_design_1_clk_wiz_0_0 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (clk25_design_1_clk_wiz_0_0 rise@40.000ns - clk25_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 7.905ns (logic 1.125ns (14.231%) route 6.780ns (85.769%)) - Logic Levels: 10 (LUT2=2 LUT4=1 LUT6=7) - Clock Path Skew: -0.044ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 3.698ns = ( 43.698 - 40.000 ) - Source Clock Delay (SCD): 3.362ns - Clock Pessimism Removal (CPR): -0.380ns - Clock Uncertainty: 0.082ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.000ns - Clock Net Delay (Source): 2.054ns (routing 1.172ns, distribution 0.882ns) - Clock Net Delay (Destination): 1.859ns (routing 1.063ns, distribution 0.796ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.629 0.729 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.779 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.779 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.384 1.163 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - -0.127 1.036 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.244 1.280 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.028 1.308 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 2.054 3.362 design_1_i/VideoTiming_0/inst/pixClk - SLICE_X32Y21 FDRE r design_1_i/VideoTiming_0/inst/cntY_reg[9]/C - ------------------------------------------------------------------- ------------------- - SLICE_X32Y21 FDRE (Prop_EFF_SLICEL_C_Q) - 0.079 3.441 f design_1_i/VideoTiming_0/inst/cntY_reg[9]/Q - net (fo=106, routed) 1.976 5.417 design_1_i/ImgGen_0/inst/PosY[9] - SLICE_X23Y14 LUT6 (Prop_H6LUT_SLICEL_I0_O) - 0.150 5.567 r design_1_i/ImgGen_0/inst/R[5]_INST_0_i_33/O - net (fo=12, routed) 0.223 5.790 design_1_i/ImgGen_0/inst/R[5]_INST_0_i_33_n_0 - SLICE_X22Y13 LUT4 (Prop_C6LUT_SLICEL_I3_O) - 0.088 5.878 r design_1_i/ImgGen_0/inst/R[5]_INST_0_i_21/O - net (fo=10, routed) 0.256 6.134 design_1_i/ImgGen_0/inst/R[5]_INST_0_i_21_n_0 - SLICE_X22Y16 LUT6 (Prop_E6LUT_SLICEL_I0_O) - 0.123 6.257 r design_1_i/ImgGen_0/inst/R[5]_INST_0_i_8/O - net (fo=463, routed) 1.896 8.153 design_1_i/ImgGen_0/inst/PosX_5_sn_1 - SLICE_X30Y17 LUT6 (Prop_F6LUT_SLICEL_I0_O) - 0.049 8.202 f design_1_i/ImgGen_0/inst/R[7]_INST_0_i_70/O - net (fo=3, routed) 0.058 8.260 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_70_n_0 - SLICE_X30Y17 LUT6 (Prop_B6LUT_SLICEL_I5_O) - 0.148 8.408 r design_1_i/ImgGen_0/inst/R[6]_INST_0_i_93/O - net (fo=1, routed) 0.088 8.496 design_1_i/ImgGen_0/inst/R[6]_INST_0_i_93_n_0 - SLICE_X30Y18 LUT6 (Prop_H6LUT_SLICEL_I1_O) - 0.099 8.595 r design_1_i/ImgGen_0/inst/R[6]_INST_0_i_32/O - net (fo=11, routed) 0.986 9.581 design_1_i/ImgGen_0/inst/PosX[4]_8 - SLICE_X36Y9 LUT2 (Prop_D6LUT_SLICEL_I1_O) - 0.122 9.703 f design_1_i/ImgGen_0/inst/B[0]_INST_0_i_4/O - net (fo=3, routed) 0.463 10.167 design_1_i/ImgGen_0/inst/R[6]_INST_0_i_32_0 - SLICE_X31Y11 LUT2 (Prop_H6LUT_SLICEM_I1_O) - 0.090 10.257 f design_1_i/ImgGen_0/inst/R[0]_INST_0_i_7/O - net (fo=1, routed) 0.193 10.450 design_1_i/ImgGen_0/inst/R[0]_INST_0_i_7_n_0 - SLICE_X31Y10 LUT6 (Prop_D6LUT_SLICEM_I2_O) - 0.088 10.538 r design_1_i/ImgGen_0/inst/R[0]_INST_0_i_2/O - net (fo=1, routed) 0.088 10.626 design_1_i/ImgGen_0/inst/R[0]_INST_0_i_2_n_0 - SLICE_X30Y10 LUT6 (Prop_G6LUT_SLICEL_I1_O) - 0.089 10.715 r design_1_i/ImgGen_0/inst/R[0]_INST_0/O - net (fo=2, routed) 0.553 11.268 design_1_i/HDMI_TX_0/U0/i_wrap/R[0] - SLICE_X36Y6 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 40.000 40.000 r - D7 0.000 40.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 40.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.519 40.598 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 40.638 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 40.638 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.333 40.971 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - 0.630 41.601 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.214 41.815 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.024 41.839 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.859 43.698 design_1_i/HDMI_TX_0/U0/i_wrap/pxClk - SLICE_X36Y6 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[0]/C - clock pessimism -0.380 43.319 - clock uncertainty -0.082 43.237 - SLICE_X36Y6 FDRE (Setup_EFF_SLICEL_C_D) - 0.025 43.262 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[0] - ------------------------------------------------------------------- - required time 43.262 - arrival time -11.268 - ------------------------------------------------------------------- - slack 31.994 - -Slack (MET) : 32.020ns (required time - arrival time) - Source: design_1_i/VideoTiming_0/inst/cntY_reg[9]/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/qD_reg[6]/D - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk25_design_1_clk_wiz_0_0 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (clk25_design_1_clk_wiz_0_0 rise@40.000ns - clk25_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 7.878ns (logic 1.169ns (14.838%) route 6.709ns (85.162%)) - Logic Levels: 10 (LUT3=1 LUT5=2 LUT6=7) - Clock Path Skew: -0.045ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 3.697ns = ( 43.697 - 40.000 ) - Source Clock Delay (SCD): 3.362ns - Clock Pessimism Removal (CPR): -0.380ns - Clock Uncertainty: 0.082ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.000ns - Clock Net Delay (Source): 2.054ns (routing 1.172ns, distribution 0.882ns) - Clock Net Delay (Destination): 1.858ns (routing 1.063ns, distribution 0.795ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.629 0.729 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.779 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.779 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.384 1.163 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - -0.127 1.036 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.244 1.280 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.028 1.308 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 2.054 3.362 design_1_i/VideoTiming_0/inst/pixClk - SLICE_X32Y21 FDRE r design_1_i/VideoTiming_0/inst/cntY_reg[9]/C - ------------------------------------------------------------------- ------------------- - SLICE_X32Y21 FDRE (Prop_EFF_SLICEL_C_Q) - 0.079 3.441 f design_1_i/VideoTiming_0/inst/cntY_reg[9]/Q - net (fo=106, routed) 1.976 5.417 design_1_i/ImgGen_0/inst/PosY[9] - SLICE_X23Y14 LUT6 (Prop_H6LUT_SLICEL_I0_O) - 0.150 5.567 r design_1_i/ImgGen_0/inst/R[5]_INST_0_i_33/O - net (fo=12, routed) 0.330 5.898 design_1_i/ImgGen_0/inst/R[5]_INST_0_i_33_n_0 - SLICE_X21Y11 LUT5 (Prop_E6LUT_SLICEL_I2_O) - 0.051 5.949 r design_1_i/ImgGen_0/inst/R[5]_INST_0_i_27/O - net (fo=35, routed) 0.438 6.387 design_1_i/ImgGen_0/inst/R[5]_INST_0_i_27_n_0 - SLICE_X23Y15 LUT6 (Prop_E6LUT_SLICEL_I3_O) - 0.147 6.534 r design_1_i/ImgGen_0/inst/R[6]_INST_0_i_75/O - net (fo=40, routed) 0.332 6.866 design_1_i/ImgGen_0/inst/R[6]_INST_0_i_75_n_0 - SLICE_X21Y13 LUT5 (Prop_B5LUT_SLICEL_I2_O) - 0.073 6.939 r design_1_i/ImgGen_0/inst/R[5]_INST_0_i_17/O - net (fo=105, routed) 1.421 8.360 design_1_i/ImgGen_0/inst/PosY_1_sn_1 - SLICE_X30Y11 LUT3 (Prop_D5LUT_SLICEL_I0_O) - 0.133 8.493 r design_1_i/ImgGen_0/inst/R[6]_INST_0_i_63/O - net (fo=1, routed) 0.225 8.718 design_1_i/ImgGen_0/inst/R[6]_INST_0_i_63_n_0 - SLICE_X26Y11 LUT6 (Prop_A6LUT_SLICEL_I5_O) - 0.050 8.768 r design_1_i/ImgGen_0/inst/R[6]_INST_0_i_19/O - net (fo=1, routed) 0.245 9.013 design_1_i/ImgGen_0/inst/R[6]_INST_0_i_19_n_0 - SLICE_X27Y4 LUT6 (Prop_F6LUT_SLICEL_I0_O) - 0.123 9.136 r design_1_i/ImgGen_0/inst/R[6]_INST_0_i_5/O - net (fo=3, routed) 0.372 9.508 design_1_i/ImgGen_0/inst_n_126 - SLICE_X29Y6 LUT6 (Prop_B6LUT_SLICEM_I5_O) - 0.149 9.657 r design_1_i/ImgGen_0/B[6]_INST_0_i_6/O - net (fo=1, routed) 0.086 9.743 design_1_i/ImgGen_0/B[6]_INST_0_i_6_n_0 - SLICE_X29Y7 LUT6 (Prop_B6LUT_SLICEM_I5_O) - 0.089 9.832 r design_1_i/ImgGen_0/B[6]_INST_0_i_2/O - net (fo=1, routed) 0.209 10.041 design_1_i/ImgGen_0/B[6]_INST_0_i_2_n_0 - SLICE_X29Y7 LUT6 (Prop_H6LUT_SLICEM_I3_O) - 0.125 10.166 r design_1_i/ImgGen_0/B[6]_INST_0/O - net (fo=2, routed) 1.075 11.241 design_1_i/HDMI_TX_0/U0/i_wrap/G[6] - SLICE_X36Y10 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/qD_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 40.000 40.000 r - D7 0.000 40.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 40.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.519 40.598 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 40.638 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 40.638 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.333 40.971 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - 0.630 41.601 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.214 41.815 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.024 41.839 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.858 43.697 design_1_i/HDMI_TX_0/U0/i_wrap/pxClk - SLICE_X36Y10 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/qD_reg[6]/C - clock pessimism -0.380 43.318 - clock uncertainty -0.082 43.236 - SLICE_X36Y10 FDRE (Setup_FFF_SLICEL_C_D) - 0.025 43.261 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/qD_reg[6] - ------------------------------------------------------------------- - required time 43.261 - arrival time -11.241 - ------------------------------------------------------------------- - slack 32.020 - -Slack (MET) : 32.147ns (required time - arrival time) - Source: design_1_i/VideoTiming_0/inst/cntY_reg[9]/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/qD_reg[4]/D - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk25_design_1_clk_wiz_0_0 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (clk25_design_1_clk_wiz_0_0 rise@40.000ns - clk25_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 7.748ns (logic 1.186ns (15.308%) route 6.562ns (84.692%)) - Logic Levels: 9 (LUT4=1 LUT5=1 LUT6=7) - Clock Path Skew: -0.049ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 3.693ns = ( 43.693 - 40.000 ) - Source Clock Delay (SCD): 3.362ns - Clock Pessimism Removal (CPR): -0.380ns - Clock Uncertainty: 0.082ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.000ns - Clock Net Delay (Source): 2.054ns (routing 1.172ns, distribution 0.882ns) - Clock Net Delay (Destination): 1.854ns (routing 1.063ns, distribution 0.791ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.629 0.729 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.779 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.779 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.384 1.163 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - -0.127 1.036 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.244 1.280 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.028 1.308 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 2.054 3.362 design_1_i/VideoTiming_0/inst/pixClk - SLICE_X32Y21 FDRE r design_1_i/VideoTiming_0/inst/cntY_reg[9]/C - ------------------------------------------------------------------- ------------------- - SLICE_X32Y21 FDRE (Prop_EFF_SLICEL_C_Q) - 0.079 3.441 f design_1_i/VideoTiming_0/inst/cntY_reg[9]/Q - net (fo=106, routed) 1.976 5.417 design_1_i/ImgGen_0/inst/PosY[9] - SLICE_X23Y14 LUT6 (Prop_H6LUT_SLICEL_I0_O) - 0.150 5.567 r design_1_i/ImgGen_0/inst/R[5]_INST_0_i_33/O - net (fo=12, routed) 0.223 5.790 design_1_i/ImgGen_0/inst/R[5]_INST_0_i_33_n_0 - SLICE_X22Y13 LUT4 (Prop_C6LUT_SLICEL_I3_O) - 0.088 5.878 r design_1_i/ImgGen_0/inst/R[5]_INST_0_i_21/O - net (fo=10, routed) 0.256 6.134 design_1_i/ImgGen_0/inst/R[5]_INST_0_i_21_n_0 - SLICE_X22Y16 LUT6 (Prop_E6LUT_SLICEL_I0_O) - 0.123 6.257 f design_1_i/ImgGen_0/inst/R[5]_INST_0_i_8/O - net (fo=463, routed) 1.977 8.234 design_1_i/ImgGen_0/inst/PosX_5_sn_1 - SLICE_X33Y1 LUT5 (Prop_D5LUT_SLICEL_I4_O) - 0.110 8.344 r design_1_i/ImgGen_0/inst/R[6]_INST_0_i_188/O - net (fo=1, routed) 0.172 8.516 design_1_i/ImgGen_0/inst/R[6]_INST_0_i_188_n_0 - SLICE_X33Y2 LUT6 (Prop_G6LUT_SLICEL_I0_O) - 0.123 8.639 r design_1_i/ImgGen_0/inst/R[6]_INST_0_i_90/O - net (fo=1, routed) 0.182 8.821 design_1_i/ImgGen_0/inst/R[6]_INST_0_i_90_n_0 - SLICE_X33Y2 LUT6 (Prop_D6LUT_SLICEL_I4_O) - 0.122 8.943 r design_1_i/ImgGen_0/inst/R[6]_INST_0_i_31/O - net (fo=7, routed) 0.440 9.383 design_1_i/ImgGen_0/inst/PosX[5]_4 - SLICE_X31Y8 LUT6 (Prop_D6LUT_SLICEM_I1_O) - 0.122 9.505 r design_1_i/ImgGen_0/inst/R[4]_INST_0_i_12/O - net (fo=1, routed) 0.052 9.557 design_1_i/ImgGen_0/inst/R[4]_INST_0_i_12_n_0 - SLICE_X31Y8 LUT6 (Prop_C6LUT_SLICEM_I4_O) - 0.145 9.702 r design_1_i/ImgGen_0/inst/R[4]_INST_0_i_2/O - net (fo=2, routed) 0.187 9.889 design_1_i/ImgGen_0/inst_n_18 - SLICE_X30Y8 LUT6 (Prop_H6LUT_SLICEL_I3_O) - 0.124 10.013 r design_1_i/ImgGen_0/B[4]_INST_0/O - net (fo=2, routed) 1.097 11.110 design_1_i/HDMI_TX_0/U0/i_wrap/B[4] - SLICE_X36Y16 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/qD_reg[4]/D - ------------------------------------------------------------------- ------------------- - - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 40.000 40.000 r - D7 0.000 40.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 40.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.519 40.598 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 40.638 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 40.638 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.333 40.971 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - 0.630 41.601 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.214 41.815 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.024 41.839 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.854 43.693 design_1_i/HDMI_TX_0/U0/i_wrap/pxClk - SLICE_X36Y16 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/qD_reg[4]/C - clock pessimism -0.380 43.314 - clock uncertainty -0.082 43.232 - SLICE_X36Y16 FDRE (Setup_FFF_SLICEL_C_D) - 0.025 43.257 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/qD_reg[4] - ------------------------------------------------------------------- - required time 43.257 - arrival time -11.110 - ------------------------------------------------------------------- - slack 32.147 - -Slack (MET) : 32.181ns (required time - arrival time) - Source: design_1_i/VideoTiming_0/inst/cntY_reg[9]/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/qD_reg[7]/D - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk25_design_1_clk_wiz_0_0 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (clk25_design_1_clk_wiz_0_0 rise@40.000ns - clk25_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 7.757ns (logic 1.225ns (15.792%) route 6.532ns (84.208%)) - Logic Levels: 10 (LUT2=1 LUT4=1 LUT5=1 LUT6=7) - Clock Path Skew: -0.005ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 3.737ns = ( 43.737 - 40.000 ) - Source Clock Delay (SCD): 3.362ns - Clock Pessimism Removal (CPR): -0.380ns - Clock Uncertainty: 0.082ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.000ns - Clock Net Delay (Source): 2.054ns (routing 1.172ns, distribution 0.882ns) - Clock Net Delay (Destination): 1.898ns (routing 1.063ns, distribution 0.835ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.629 0.729 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.779 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.779 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.384 1.163 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - -0.127 1.036 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.244 1.280 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.028 1.308 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 2.054 3.362 design_1_i/VideoTiming_0/inst/pixClk - SLICE_X32Y21 FDRE r design_1_i/VideoTiming_0/inst/cntY_reg[9]/C - ------------------------------------------------------------------- ------------------- - SLICE_X32Y21 FDRE (Prop_EFF_SLICEL_C_Q) - 0.079 3.441 f design_1_i/VideoTiming_0/inst/cntY_reg[9]/Q - net (fo=106, routed) 1.976 5.417 design_1_i/ImgGen_0/inst/PosY[9] - SLICE_X23Y14 LUT6 (Prop_H6LUT_SLICEL_I0_O) - 0.150 5.567 r design_1_i/ImgGen_0/inst/R[5]_INST_0_i_33/O - net (fo=12, routed) 0.223 5.790 design_1_i/ImgGen_0/inst/R[5]_INST_0_i_33_n_0 - SLICE_X22Y13 LUT4 (Prop_C6LUT_SLICEL_I3_O) - 0.088 5.878 r design_1_i/ImgGen_0/inst/R[5]_INST_0_i_21/O - net (fo=10, routed) 0.256 6.134 design_1_i/ImgGen_0/inst/R[5]_INST_0_i_21_n_0 - SLICE_X22Y16 LUT6 (Prop_E6LUT_SLICEL_I0_O) - 0.123 6.257 r design_1_i/ImgGen_0/inst/R[5]_INST_0_i_8/O - net (fo=463, routed) 1.896 8.153 design_1_i/ImgGen_0/inst/PosX_5_sn_1 - SLICE_X30Y17 LUT6 (Prop_F6LUT_SLICEL_I0_O) - 0.049 8.202 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_70/O - net (fo=3, routed) 0.058 8.260 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_70_n_0 - SLICE_X30Y17 LUT6 (Prop_B6LUT_SLICEL_I5_O) - 0.148 8.408 f design_1_i/ImgGen_0/inst/R[6]_INST_0_i_93/O - net (fo=1, routed) 0.088 8.496 design_1_i/ImgGen_0/inst/R[6]_INST_0_i_93_n_0 - SLICE_X30Y18 LUT6 (Prop_H6LUT_SLICEL_I1_O) - 0.099 8.595 f design_1_i/ImgGen_0/inst/R[6]_INST_0_i_32/O - net (fo=11, routed) 0.342 8.937 design_1_i/ImgGen_0/inst/PosX[4]_8 - SLICE_X34Y16 LUT5 (Prop_D5LUT_SLICEM_I4_O) - 0.066 9.003 f design_1_i/ImgGen_0/inst/R[7]_INST_0_i_29/O - net (fo=1, routed) 0.285 9.288 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_29_n_0 - SLICE_X32Y15 LUT6 (Prop_F6LUT_SLICEL_I1_O) - 0.148 9.436 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_7/O - net (fo=1, routed) 0.420 9.856 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_7_n_0 - SLICE_X34Y11 LUT6 (Prop_H6LUT_SLICEM_I5_O) - 0.152 10.008 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_1/O - net (fo=2, routed) 0.315 10.323 design_1_i/ImgGen_0/inst_n_16 - SLICE_X36Y9 LUT2 (Prop_F6LUT_SLICEL_I0_O) - 0.123 10.446 r design_1_i/ImgGen_0/B[7]_INST_0/O - net (fo=2, routed) 0.674 11.119 design_1_i/HDMI_TX_0/U0/i_wrap/B[7] - SLICE_X38Y15 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/qD_reg[7]/D - ------------------------------------------------------------------- ------------------- - - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 40.000 40.000 r - D7 0.000 40.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 40.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.519 40.598 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 40.638 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 40.638 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.333 40.971 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - 0.630 41.601 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.214 41.815 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.024 41.839 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.898 43.737 design_1_i/HDMI_TX_0/U0/i_wrap/pxClk - SLICE_X38Y15 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/qD_reg[7]/C - clock pessimism -0.380 43.357 - clock uncertainty -0.082 43.275 - SLICE_X38Y15 FDRE (Setup_EFF_SLICEL_C_D) - 0.025 43.300 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/qD_reg[7] - ------------------------------------------------------------------- - required time 43.300 - arrival time -11.119 - ------------------------------------------------------------------- - slack 32.181 - -Slack (MET) : 32.287ns (required time - arrival time) - Source: design_1_i/VideoTiming_0/inst/cntY_reg[9]/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/qD_reg[4]/D - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk25_design_1_clk_wiz_0_0 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (clk25_design_1_clk_wiz_0_0 rise@40.000ns - clk25_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 7.607ns (logic 1.186ns (15.591%) route 6.421ns (84.409%)) - Logic Levels: 9 (LUT4=1 LUT5=1 LUT6=7) - Clock Path Skew: -0.049ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 3.693ns = ( 43.693 - 40.000 ) - Source Clock Delay (SCD): 3.362ns - Clock Pessimism Removal (CPR): -0.380ns - Clock Uncertainty: 0.082ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.000ns - Clock Net Delay (Source): 2.054ns (routing 1.172ns, distribution 0.882ns) - Clock Net Delay (Destination): 1.854ns (routing 1.063ns, distribution 0.791ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.629 0.729 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.779 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.779 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.384 1.163 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - -0.127 1.036 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.244 1.280 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.028 1.308 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 2.054 3.362 design_1_i/VideoTiming_0/inst/pixClk - SLICE_X32Y21 FDRE r design_1_i/VideoTiming_0/inst/cntY_reg[9]/C - ------------------------------------------------------------------- ------------------- - SLICE_X32Y21 FDRE (Prop_EFF_SLICEL_C_Q) - 0.079 3.441 f design_1_i/VideoTiming_0/inst/cntY_reg[9]/Q - net (fo=106, routed) 1.976 5.417 design_1_i/ImgGen_0/inst/PosY[9] - SLICE_X23Y14 LUT6 (Prop_H6LUT_SLICEL_I0_O) - 0.150 5.567 r design_1_i/ImgGen_0/inst/R[5]_INST_0_i_33/O - net (fo=12, routed) 0.223 5.790 design_1_i/ImgGen_0/inst/R[5]_INST_0_i_33_n_0 - SLICE_X22Y13 LUT4 (Prop_C6LUT_SLICEL_I3_O) - 0.088 5.878 r design_1_i/ImgGen_0/inst/R[5]_INST_0_i_21/O - net (fo=10, routed) 0.256 6.134 design_1_i/ImgGen_0/inst/R[5]_INST_0_i_21_n_0 - SLICE_X22Y16 LUT6 (Prop_E6LUT_SLICEL_I0_O) - 0.123 6.257 f design_1_i/ImgGen_0/inst/R[5]_INST_0_i_8/O - net (fo=463, routed) 1.977 8.234 design_1_i/ImgGen_0/inst/PosX_5_sn_1 - SLICE_X33Y1 LUT5 (Prop_D5LUT_SLICEL_I4_O) - 0.110 8.344 r design_1_i/ImgGen_0/inst/R[6]_INST_0_i_188/O - net (fo=1, routed) 0.172 8.516 design_1_i/ImgGen_0/inst/R[6]_INST_0_i_188_n_0 - SLICE_X33Y2 LUT6 (Prop_G6LUT_SLICEL_I0_O) - 0.123 8.639 r design_1_i/ImgGen_0/inst/R[6]_INST_0_i_90/O - net (fo=1, routed) 0.182 8.821 design_1_i/ImgGen_0/inst/R[6]_INST_0_i_90_n_0 - SLICE_X33Y2 LUT6 (Prop_D6LUT_SLICEL_I4_O) - 0.122 8.943 r design_1_i/ImgGen_0/inst/R[6]_INST_0_i_31/O - net (fo=7, routed) 0.440 9.383 design_1_i/ImgGen_0/inst/PosX[5]_4 - SLICE_X31Y8 LUT6 (Prop_D6LUT_SLICEM_I1_O) - 0.122 9.505 r design_1_i/ImgGen_0/inst/R[4]_INST_0_i_12/O - net (fo=1, routed) 0.052 9.557 design_1_i/ImgGen_0/inst/R[4]_INST_0_i_12_n_0 - SLICE_X31Y8 LUT6 (Prop_C6LUT_SLICEM_I4_O) - 0.145 9.702 r design_1_i/ImgGen_0/inst/R[4]_INST_0_i_2/O - net (fo=2, routed) 0.187 9.889 design_1_i/ImgGen_0/inst_n_18 - SLICE_X30Y8 LUT6 (Prop_H6LUT_SLICEL_I3_O) - 0.124 10.013 r design_1_i/ImgGen_0/B[4]_INST_0/O - net (fo=2, routed) 0.956 10.969 design_1_i/HDMI_TX_0/U0/i_wrap/G[4] - SLICE_X36Y16 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/qD_reg[4]/D - ------------------------------------------------------------------- ------------------- - - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 40.000 40.000 r - D7 0.000 40.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 40.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.519 40.598 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 40.638 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 40.638 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.333 40.971 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - 0.630 41.601 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.214 41.815 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.024 41.839 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.854 43.693 design_1_i/HDMI_TX_0/U0/i_wrap/pxClk - SLICE_X36Y16 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/qD_reg[4]/C - clock pessimism -0.380 43.314 - clock uncertainty -0.082 43.232 - SLICE_X36Y16 FDRE (Setup_HFF_SLICEL_C_D) - 0.025 43.257 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/qD_reg[4] - ------------------------------------------------------------------- - required time 43.257 - arrival time -10.969 - ------------------------------------------------------------------- - slack 32.287 - -Slack (MET) : 32.359ns (required time - arrival time) - Source: design_1_i/VideoTiming_0/inst/cntY_reg[9]/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/qD_reg[0]/D - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk25_design_1_clk_wiz_0_0 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (clk25_design_1_clk_wiz_0_0 rise@40.000ns - clk25_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 7.541ns (logic 1.017ns (13.487%) route 6.524ns (86.513%)) - Logic Levels: 9 (LUT2=1 LUT4=1 LUT6=7) - Clock Path Skew: -0.044ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 3.698ns = ( 43.698 - 40.000 ) - Source Clock Delay (SCD): 3.362ns - Clock Pessimism Removal (CPR): -0.380ns - Clock Uncertainty: 0.082ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.000ns - Clock Net Delay (Source): 2.054ns (routing 1.172ns, distribution 0.882ns) - Clock Net Delay (Destination): 1.859ns (routing 1.063ns, distribution 0.796ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.629 0.729 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.779 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.779 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.384 1.163 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - -0.127 1.036 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.244 1.280 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.028 1.308 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 2.054 3.362 design_1_i/VideoTiming_0/inst/pixClk - SLICE_X32Y21 FDRE r design_1_i/VideoTiming_0/inst/cntY_reg[9]/C - ------------------------------------------------------------------- ------------------- - SLICE_X32Y21 FDRE (Prop_EFF_SLICEL_C_Q) - 0.079 3.441 f design_1_i/VideoTiming_0/inst/cntY_reg[9]/Q - net (fo=106, routed) 1.976 5.417 design_1_i/ImgGen_0/inst/PosY[9] - SLICE_X23Y14 LUT6 (Prop_H6LUT_SLICEL_I0_O) - 0.150 5.567 r design_1_i/ImgGen_0/inst/R[5]_INST_0_i_33/O - net (fo=12, routed) 0.223 5.790 design_1_i/ImgGen_0/inst/R[5]_INST_0_i_33_n_0 - SLICE_X22Y13 LUT4 (Prop_C6LUT_SLICEL_I3_O) - 0.088 5.878 r design_1_i/ImgGen_0/inst/R[5]_INST_0_i_21/O - net (fo=10, routed) 0.256 6.134 design_1_i/ImgGen_0/inst/R[5]_INST_0_i_21_n_0 - SLICE_X22Y16 LUT6 (Prop_E6LUT_SLICEL_I0_O) - 0.123 6.257 r design_1_i/ImgGen_0/inst/R[5]_INST_0_i_8/O - net (fo=463, routed) 1.896 8.153 design_1_i/ImgGen_0/inst/PosX_5_sn_1 - SLICE_X30Y17 LUT6 (Prop_F6LUT_SLICEL_I0_O) - 0.049 8.202 f design_1_i/ImgGen_0/inst/R[7]_INST_0_i_70/O - net (fo=3, routed) 0.058 8.260 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_70_n_0 - SLICE_X30Y17 LUT6 (Prop_B6LUT_SLICEL_I5_O) - 0.148 8.408 r design_1_i/ImgGen_0/inst/R[6]_INST_0_i_93/O - net (fo=1, routed) 0.088 8.496 design_1_i/ImgGen_0/inst/R[6]_INST_0_i_93_n_0 - SLICE_X30Y18 LUT6 (Prop_H6LUT_SLICEL_I1_O) - 0.099 8.595 r design_1_i/ImgGen_0/inst/R[6]_INST_0_i_32/O - net (fo=11, routed) 0.986 9.581 design_1_i/ImgGen_0/inst/PosX[4]_8 - SLICE_X36Y9 LUT2 (Prop_D6LUT_SLICEL_I1_O) - 0.122 9.703 f design_1_i/ImgGen_0/inst/B[0]_INST_0_i_4/O - net (fo=3, routed) 0.380 10.084 design_1_i/ImgGen_0/inst_n_114 - SLICE_X30Y10 LUT6 (Prop_C6LUT_SLICEL_I5_O) - 0.123 10.207 r design_1_i/ImgGen_0/B[0]_INST_0_i_1/O - net (fo=1, routed) 0.041 10.248 design_1_i/ImgGen_0/B[0]_INST_0_i_1_n_0 - SLICE_X30Y10 LUT6 (Prop_D6LUT_SLICEL_I3_O) - 0.036 10.284 r design_1_i/ImgGen_0/B[0]_INST_0/O - net (fo=4, routed) 0.620 10.903 design_1_i/HDMI_TX_0/U0/i_wrap/B[0] - SLICE_X37Y17 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/qD_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 40.000 40.000 r - D7 0.000 40.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 40.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.519 40.598 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 40.638 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 40.638 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.333 40.971 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - 0.630 41.601 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.214 41.815 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.024 41.839 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.859 43.698 design_1_i/HDMI_TX_0/U0/i_wrap/pxClk - SLICE_X37Y17 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/qD_reg[0]/C - clock pessimism -0.380 43.319 - clock uncertainty -0.082 43.237 - SLICE_X37Y17 FDRE (Setup_EFF_SLICEM_C_D) - 0.025 43.262 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/qD_reg[0] - ------------------------------------------------------------------- - required time 43.262 - arrival time -10.903 - ------------------------------------------------------------------- - slack 32.359 - -Slack (MET) : 32.389ns (required time - arrival time) - Source: design_1_i/VideoTiming_0/inst/cntY_reg[9]/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/qD_reg[3]/D - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk25_design_1_clk_wiz_0_0 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (clk25_design_1_clk_wiz_0_0 rise@40.000ns - clk25_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 7.511ns (logic 1.017ns (13.541%) route 6.494ns (86.459%)) - Logic Levels: 9 (LUT2=1 LUT4=1 LUT6=7) - Clock Path Skew: -0.044ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 3.698ns = ( 43.698 - 40.000 ) - Source Clock Delay (SCD): 3.362ns - Clock Pessimism Removal (CPR): -0.380ns - Clock Uncertainty: 0.082ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.000ns - Clock Net Delay (Source): 2.054ns (routing 1.172ns, distribution 0.882ns) - Clock Net Delay (Destination): 1.859ns (routing 1.063ns, distribution 0.796ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.629 0.729 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.779 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.779 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.384 1.163 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - -0.127 1.036 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.244 1.280 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.028 1.308 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 2.054 3.362 design_1_i/VideoTiming_0/inst/pixClk - SLICE_X32Y21 FDRE r design_1_i/VideoTiming_0/inst/cntY_reg[9]/C - ------------------------------------------------------------------- ------------------- - SLICE_X32Y21 FDRE (Prop_EFF_SLICEL_C_Q) - 0.079 3.441 f design_1_i/VideoTiming_0/inst/cntY_reg[9]/Q - net (fo=106, routed) 1.976 5.417 design_1_i/ImgGen_0/inst/PosY[9] - SLICE_X23Y14 LUT6 (Prop_H6LUT_SLICEL_I0_O) - 0.150 5.567 r design_1_i/ImgGen_0/inst/R[5]_INST_0_i_33/O - net (fo=12, routed) 0.223 5.790 design_1_i/ImgGen_0/inst/R[5]_INST_0_i_33_n_0 - SLICE_X22Y13 LUT4 (Prop_C6LUT_SLICEL_I3_O) - 0.088 5.878 r design_1_i/ImgGen_0/inst/R[5]_INST_0_i_21/O - net (fo=10, routed) 0.256 6.134 design_1_i/ImgGen_0/inst/R[5]_INST_0_i_21_n_0 - SLICE_X22Y16 LUT6 (Prop_E6LUT_SLICEL_I0_O) - 0.123 6.257 r design_1_i/ImgGen_0/inst/R[5]_INST_0_i_8/O - net (fo=463, routed) 1.896 8.153 design_1_i/ImgGen_0/inst/PosX_5_sn_1 - SLICE_X30Y17 LUT6 (Prop_F6LUT_SLICEL_I0_O) - 0.049 8.202 f design_1_i/ImgGen_0/inst/R[7]_INST_0_i_70/O - net (fo=3, routed) 0.058 8.260 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_70_n_0 - SLICE_X30Y17 LUT6 (Prop_B6LUT_SLICEL_I5_O) - 0.148 8.408 r design_1_i/ImgGen_0/inst/R[6]_INST_0_i_93/O - net (fo=1, routed) 0.088 8.496 design_1_i/ImgGen_0/inst/R[6]_INST_0_i_93_n_0 - SLICE_X30Y18 LUT6 (Prop_H6LUT_SLICEL_I1_O) - 0.099 8.595 r design_1_i/ImgGen_0/inst/R[6]_INST_0_i_32/O - net (fo=11, routed) 0.986 9.581 design_1_i/ImgGen_0/inst/PosX[4]_8 - SLICE_X36Y9 LUT2 (Prop_D6LUT_SLICEL_I1_O) - 0.122 9.703 f design_1_i/ImgGen_0/inst/B[0]_INST_0_i_4/O - net (fo=3, routed) 0.380 10.084 design_1_i/ImgGen_0/inst_n_114 - SLICE_X30Y10 LUT6 (Prop_C6LUT_SLICEL_I5_O) - 0.123 10.207 r design_1_i/ImgGen_0/B[0]_INST_0_i_1/O - net (fo=1, routed) 0.041 10.248 design_1_i/ImgGen_0/B[0]_INST_0_i_1_n_0 - SLICE_X30Y10 LUT6 (Prop_D6LUT_SLICEL_I3_O) - 0.036 10.284 r design_1_i/ImgGen_0/B[0]_INST_0/O - net (fo=4, routed) 0.590 10.873 design_1_i/HDMI_TX_0/U0/i_wrap/B[3] - SLICE_X37Y17 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/qD_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 40.000 40.000 r - D7 0.000 40.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 40.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.519 40.598 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 40.638 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 40.638 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.333 40.971 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - 0.630 41.601 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.214 41.815 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.024 41.839 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.859 43.698 design_1_i/HDMI_TX_0/U0/i_wrap/pxClk - SLICE_X37Y17 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/qD_reg[3]/C - clock pessimism -0.380 43.319 - clock uncertainty -0.082 43.237 - SLICE_X37Y17 FDRE (Setup_EFF2_SLICEM_C_D) - 0.025 43.262 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/qD_reg[3] - ------------------------------------------------------------------- - required time 43.262 - arrival time -10.873 - ------------------------------------------------------------------- - slack 32.389 - - - - - -Min Delay Paths --------------------------------------------------------------------------------------- -Slack (MET) : 0.042ns (arrival time - required time) - Source: design_1_i/VideoTiming_0/inst/DE_Y_reg/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/VideoTiming_0/inst/DE_Y_reg/D - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk25_design_1_clk_wiz_0_0 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk25_design_1_clk_wiz_0_0 rise@0.000ns - clk25_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 0.094ns (logic 0.054ns (57.390%) route 0.040ns (42.610%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.006ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.947ns - Source Clock Delay (SCD): 2.139ns - Clock Pessimism Removal (CPR): -0.197ns - Clock Net Delay (Source): 1.137ns (routing 0.640ns, distribution 0.497ns) - Clock Net Delay (Destination): 1.286ns (routing 0.716ns, distribution 0.570ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.295 0.374 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.414 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.414 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.196 0.610 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - 0.230 0.840 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.145 0.985 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.017 1.002 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.137 2.139 design_1_i/VideoTiming_0/inst/pixClk - SLICE_X33Y21 FDRE r design_1_i/VideoTiming_0/inst/DE_Y_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y21 FDRE (Prop_BFF_SLICEL_C_Q) - 0.039 2.178 r design_1_i/VideoTiming_0/inst/DE_Y_reg/Q - net (fo=2, routed) 0.025 2.203 design_1_i/VideoTiming_0/inst/DE_Y - SLICE_X33Y21 LUT6 (Prop_B6LUT_SLICEL_I4_O) - 0.015 2.218 r design_1_i/VideoTiming_0/inst/DE_Y_i_1/O - net (fo=1, routed) 0.015 2.233 design_1_i/VideoTiming_0/inst/DE_Y_i_1_n_0 - SLICE_X33Y21 FDRE r design_1_i/VideoTiming_0/inst/DE_Y_reg/D - ------------------------------------------------------------------- ------------------- - - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.400 0.500 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.550 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.550 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.222 0.772 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - -0.295 0.477 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.165 0.642 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.019 0.661 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.286 1.947 design_1_i/VideoTiming_0/inst/pixClk - SLICE_X33Y21 FDRE r design_1_i/VideoTiming_0/inst/DE_Y_reg/C - clock pessimism 0.197 2.145 - SLICE_X33Y21 FDRE (Hold_BFF_SLICEL_C_D) - 0.046 2.191 design_1_i/VideoTiming_0/inst/DE_Y_reg - ------------------------------------------------------------------- - required time -2.191 - arrival time 2.233 - ------------------------------------------------------------------- - slack 0.042 - -Slack (MET) : 0.050ns (arrival time - required time) - Source: design_1_i/angle_encoder_1/inst/angle_reg_reg[4]/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/angle_encoder_1/inst/angle_reg_reg[4]/D - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk25_design_1_clk_wiz_0_0 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk25_design_1_clk_wiz_0_0 rise@0.000ns - clk25_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 0.102ns (logic 0.054ns (53.137%) route 0.048ns (46.863%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.006ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.911ns - Source Clock Delay (SCD): 2.105ns - Clock Pessimism Removal (CPR): -0.199ns - Clock Net Delay (Source): 1.103ns (routing 0.640ns, distribution 0.463ns) - Clock Net Delay (Destination): 1.250ns (routing 0.716ns, distribution 0.534ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.295 0.374 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.414 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.414 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.196 0.610 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - 0.230 0.840 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.145 0.985 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.017 1.002 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.103 2.105 design_1_i/angle_encoder_1/inst/CLK - SLICE_X22Y3 FDRE r design_1_i/angle_encoder_1/inst/angle_reg_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X22Y3 FDRE (Prop_HFF_SLICEL_C_Q) - 0.039 2.144 r design_1_i/angle_encoder_1/inst/angle_reg_reg[4]/Q - net (fo=18, routed) 0.031 2.175 design_1_i/angle_encoder_1/inst/ANG[3] - SLICE_X22Y3 LUT6 (Prop_H6LUT_SLICEL_I1_O) - 0.015 2.190 r design_1_i/angle_encoder_1/inst/angle_reg[4]_i_3/O - net (fo=1, routed) 0.017 2.207 design_1_i/angle_encoder_1/inst/angle_reg[4]_i_3_n_0 - SLICE_X22Y3 FDRE r design_1_i/angle_encoder_1/inst/angle_reg_reg[4]/D - ------------------------------------------------------------------- ------------------- - - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.400 0.500 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.550 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.550 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.222 0.772 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - -0.295 0.477 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.165 0.642 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.019 0.661 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.250 1.911 design_1_i/angle_encoder_1/inst/CLK - SLICE_X22Y3 FDRE r design_1_i/angle_encoder_1/inst/angle_reg_reg[4]/C - clock pessimism 0.199 2.111 - SLICE_X22Y3 FDRE (Hold_HFF_SLICEL_C_D) - 0.046 2.157 design_1_i/angle_encoder_1/inst/angle_reg_reg[4] - ------------------------------------------------------------------- - required time -2.157 - arrival time 2.207 - ------------------------------------------------------------------- - slack 0.050 - -Slack (MET) : 0.055ns (arrival time - required time) - Source: design_1_i/VideoTiming_0/inst/cntX_reg[4]/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/VideoTiming_0/inst/cntX_reg[5]/D - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk25_design_1_clk_wiz_0_0 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk25_design_1_clk_wiz_0_0 rise@0.000ns - clk25_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 0.108ns (logic 0.061ns (56.370%) route 0.047ns (43.630%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.006ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.946ns - Source Clock Delay (SCD): 2.137ns - Clock Pessimism Removal (CPR): -0.197ns - Clock Net Delay (Source): 1.135ns (routing 0.640ns, distribution 0.495ns) - Clock Net Delay (Destination): 1.285ns (routing 0.716ns, distribution 0.569ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.295 0.374 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.414 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.414 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.196 0.610 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - 0.230 0.840 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.145 0.985 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.017 1.002 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.135 2.137 design_1_i/VideoTiming_0/inst/pixClk - SLICE_X33Y23 FDRE r design_1_i/VideoTiming_0/inst/cntX_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y23 FDRE (Prop_FFF_SLICEL_C_Q) - 0.039 2.176 r design_1_i/VideoTiming_0/inst/cntX_reg[4]/Q - net (fo=120, routed) 0.033 2.210 design_1_i/VideoTiming_0/inst/PosX[4] - SLICE_X33Y23 LUT6 (Prop_G6LUT_SLICEL_I5_O) - 0.022 2.232 r design_1_i/VideoTiming_0/inst/cntX[5]_i_1/O - net (fo=1, routed) 0.014 2.246 design_1_i/VideoTiming_0/inst/cntX[5]_i_1_n_0 - SLICE_X33Y23 FDRE r design_1_i/VideoTiming_0/inst/cntX_reg[5]/D - ------------------------------------------------------------------- ------------------- - - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.400 0.500 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.550 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.550 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.222 0.772 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - -0.295 0.477 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.165 0.642 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.019 0.661 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.285 1.946 design_1_i/VideoTiming_0/inst/pixClk - SLICE_X33Y23 FDRE r design_1_i/VideoTiming_0/inst/cntX_reg[5]/C - clock pessimism 0.197 2.143 - SLICE_X33Y23 FDRE (Hold_GFF2_SLICEL_C_D) - 0.047 2.190 design_1_i/VideoTiming_0/inst/cntX_reg[5] - ------------------------------------------------------------------- - required time -2.190 - arrival time 2.246 - ------------------------------------------------------------------- - slack 0.055 - -Slack (MET) : 0.063ns (arrival time - required time) - Source: design_1_i/GameController_0/inst/health_reg_reg[0]/C - (rising edge-triggered cell FDPE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/GameController_0/inst/health_reg_reg[2]/D - (rising edge-triggered cell FDCE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk25_design_1_clk_wiz_0_0 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk25_design_1_clk_wiz_0_0 rise@0.000ns - clk25_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 0.116ns (logic 0.075ns (64.823%) route 0.041ns (35.177%)) - Logic Levels: 1 (LUT3=1) - Clock Path Skew: 0.006ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.998ns - Source Clock Delay (SCD): 2.184ns - Clock Pessimism Removal (CPR): -0.192ns - Clock Net Delay (Source): 1.182ns (routing 0.640ns, distribution 0.542ns) - Clock Net Delay (Destination): 1.337ns (routing 0.716ns, distribution 0.621ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.295 0.374 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.414 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.414 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.196 0.610 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - 0.230 0.840 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.145 0.985 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.017 1.002 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.182 2.184 design_1_i/GameController_0/inst/Clk - SLICE_X48Y31 FDPE r design_1_i/GameController_0/inst/health_reg_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X48Y31 FDPE (Prop_DFF_SLICEM_C_Q) - 0.039 2.223 r design_1_i/GameController_0/inst/health_reg_reg[0]/Q - net (fo=4, routed) 0.033 2.256 design_1_i/GameController_0/inst/Q[0] - SLICE_X48Y31 LUT3 (Prop_C5LUT_SLICEM_I1_O) - 0.036 2.292 r design_1_i/GameController_0/inst/health_reg[2]_i_1/O - net (fo=1, routed) 0.008 2.300 design_1_i/GameController_0/inst/health_reg[2]_i_1_n_0 - SLICE_X48Y31 FDCE r design_1_i/GameController_0/inst/health_reg_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.400 0.500 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.550 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.550 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.222 0.772 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - -0.295 0.477 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.165 0.642 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.019 0.661 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.337 1.998 design_1_i/GameController_0/inst/Clk - SLICE_X48Y31 FDCE r design_1_i/GameController_0/inst/health_reg_reg[2]/C - clock pessimism 0.192 2.190 - SLICE_X48Y31 FDCE (Hold_CFF2_SLICEM_C_D) - 0.047 2.237 design_1_i/GameController_0/inst/health_reg_reg[2] - ------------------------------------------------------------------- - required time -2.237 - arrival time 2.300 - ------------------------------------------------------------------- - slack 0.063 - -Slack (MET) : 0.063ns (arrival time - required time) - Source: design_1_i/VideoTiming_0/inst/DE_Y_reg/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/qDE_reg/D - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk25_design_1_clk_wiz_0_0 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk25_design_1_clk_wiz_0_0 rise@0.000ns - clk25_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 0.115ns (logic 0.074ns (64.296%) route 0.041ns (35.704%)) - Logic Levels: 1 (LUT2=1) - Clock Path Skew: 0.006ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.947ns - Source Clock Delay (SCD): 2.139ns - Clock Pessimism Removal (CPR): -0.197ns - Clock Net Delay (Source): 1.137ns (routing 0.640ns, distribution 0.497ns) - Clock Net Delay (Destination): 1.286ns (routing 0.716ns, distribution 0.570ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.295 0.374 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.414 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.414 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.196 0.610 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - 0.230 0.840 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.145 0.985 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.017 1.002 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.137 2.139 design_1_i/VideoTiming_0/inst/pixClk - SLICE_X33Y21 FDRE r design_1_i/VideoTiming_0/inst/DE_Y_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y21 FDRE (Prop_BFF_SLICEL_C_Q) - 0.039 2.178 r design_1_i/VideoTiming_0/inst/DE_Y_reg/Q - net (fo=2, routed) 0.025 2.203 design_1_i/VideoTiming_0/inst/DE_Y - SLICE_X33Y21 LUT2 (Prop_D6LUT_SLICEL_I1_O) - 0.035 2.238 r design_1_i/VideoTiming_0/inst/DE_INST_0/O - net (fo=1, routed) 0.016 2.254 design_1_i/HDMI_TX_0/U0/i_wrap/DE - SLICE_X33Y21 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/qDE_reg/D - ------------------------------------------------------------------- ------------------- - - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.400 0.500 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.550 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.550 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.222 0.772 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - -0.295 0.477 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.165 0.642 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.019 0.661 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.286 1.947 design_1_i/HDMI_TX_0/U0/i_wrap/pxClk - SLICE_X33Y21 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/qDE_reg/C - clock pessimism 0.197 2.145 - SLICE_X33Y21 FDRE (Hold_DFF_SLICEL_C_D) - 0.046 2.191 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/qDE_reg - ------------------------------------------------------------------- - required time -2.191 - arrival time 2.254 - ------------------------------------------------------------------- - slack 0.063 - -Slack (MET) : 0.063ns (arrival time - required time) - Source: design_1_i/angle_encoder_1/inst/angle_reg_reg[2]/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/angle_encoder_1/inst/angle_reg_reg[2]/D - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk25_design_1_clk_wiz_0_0 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk25_design_1_clk_wiz_0_0 rise@0.000ns - clk25_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 0.115ns (logic 0.060ns (52.001%) route 0.055ns (47.999%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.006ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.907ns - Source Clock Delay (SCD): 2.100ns - Clock Pessimism Removal (CPR): -0.199ns - Clock Net Delay (Source): 1.098ns (routing 0.640ns, distribution 0.458ns) - Clock Net Delay (Destination): 1.246ns (routing 0.716ns, distribution 0.530ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.295 0.374 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.414 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.414 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.196 0.610 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - 0.230 0.840 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.145 0.985 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.017 1.002 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.098 2.100 design_1_i/angle_encoder_1/inst/CLK - SLICE_X20Y3 FDRE r design_1_i/angle_encoder_1/inst/angle_reg_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X20Y3 FDRE (Prop_BFF_SLICEM_C_Q) - 0.038 2.138 r design_1_i/angle_encoder_1/inst/angle_reg_reg[2]/Q - net (fo=38, routed) 0.034 2.173 design_1_i/angle_encoder_1/inst/ANG[2] - SLICE_X20Y3 LUT6 (Prop_B6LUT_SLICEM_I1_O) - 0.022 2.195 r design_1_i/angle_encoder_1/inst/angle_reg[2]_i_1/O - net (fo=1, routed) 0.021 2.216 design_1_i/angle_encoder_1/inst/angle_reg[2]_i_1_n_0 - SLICE_X20Y3 FDRE r design_1_i/angle_encoder_1/inst/angle_reg_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.400 0.500 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.550 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.550 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.222 0.772 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - -0.295 0.477 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.165 0.642 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.019 0.661 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.246 1.907 design_1_i/angle_encoder_1/inst/CLK - SLICE_X20Y3 FDRE r design_1_i/angle_encoder_1/inst/angle_reg_reg[2]/C - clock pessimism 0.199 2.106 - SLICE_X20Y3 FDRE (Hold_BFF_SLICEM_C_D) - 0.046 2.152 design_1_i/angle_encoder_1/inst/angle_reg_reg[2] - ------------------------------------------------------------------- - required time -2.152 - arrival time 2.216 - ------------------------------------------------------------------- - slack 0.063 - -Slack (MET) : 0.065ns (arrival time - required time) - Source: design_1_i/GameController_0/inst/health_reg_reg[0]/C - (rising edge-triggered cell FDPE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/GameController_0/inst/health_reg_reg[1]/D - (rising edge-triggered cell FDPE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk25_design_1_clk_wiz_0_0 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk25_design_1_clk_wiz_0_0 rise@0.000ns - clk25_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 0.118ns (logic 0.076ns (64.572%) route 0.042ns (35.429%)) - Logic Levels: 1 (LUT3=1) - Clock Path Skew: 0.006ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.998ns - Source Clock Delay (SCD): 2.184ns - Clock Pessimism Removal (CPR): -0.192ns - Clock Net Delay (Source): 1.182ns (routing 0.640ns, distribution 0.542ns) - Clock Net Delay (Destination): 1.337ns (routing 0.716ns, distribution 0.621ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.295 0.374 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.414 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.414 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.196 0.610 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - 0.230 0.840 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.145 0.985 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.017 1.002 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.182 2.184 design_1_i/GameController_0/inst/Clk - SLICE_X48Y31 FDPE r design_1_i/GameController_0/inst/health_reg_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X48Y31 FDPE (Prop_DFF_SLICEM_C_Q) - 0.039 2.223 r design_1_i/GameController_0/inst/health_reg_reg[0]/Q - net (fo=4, routed) 0.033 2.256 design_1_i/GameController_0/inst/Q[0] - SLICE_X48Y31 LUT3 (Prop_D5LUT_SLICEM_I2_O) - 0.037 2.293 r design_1_i/GameController_0/inst/health_reg[1]_i_1/O - net (fo=1, routed) 0.009 2.302 design_1_i/GameController_0/inst/health_reg[1]_i_1_n_0 - SLICE_X48Y31 FDPE r design_1_i/GameController_0/inst/health_reg_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.400 0.500 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.550 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.550 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.222 0.772 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - -0.295 0.477 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.165 0.642 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.019 0.661 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.337 1.998 design_1_i/GameController_0/inst/Clk - SLICE_X48Y31 FDPE r design_1_i/GameController_0/inst/health_reg_reg[1]/C - clock pessimism 0.192 2.190 - SLICE_X48Y31 FDPE (Hold_DFF2_SLICEM_C_D) - 0.047 2.237 design_1_i/GameController_0/inst/health_reg_reg[1] - ------------------------------------------------------------------- - required time -2.237 - arrival time 2.302 - ------------------------------------------------------------------- - slack 0.065 - -Slack (MET) : 0.071ns (arrival time - required time) - Source: design_1_i/angle_encoder_1/inst/rot_r_delayed_reg/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/angle_encoder_1/inst/angle_reg_reg[1]/D - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk25_design_1_clk_wiz_0_0 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk25_design_1_clk_wiz_0_0 rise@0.000ns - clk25_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 0.165ns (logic 0.091ns (55.100%) route 0.074ns (44.900%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: 0.047ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.907ns - Source Clock Delay (SCD): 2.102ns - Clock Pessimism Removal (CPR): -0.242ns - Clock Net Delay (Source): 1.100ns (routing 0.640ns, distribution 0.460ns) - Clock Net Delay (Destination): 1.246ns (routing 0.716ns, distribution 0.530ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.295 0.374 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.414 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.414 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.196 0.610 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - 0.230 0.840 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.145 0.985 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.017 1.002 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.100 2.102 design_1_i/angle_encoder_1/inst/CLK - SLICE_X22Y3 FDRE r design_1_i/angle_encoder_1/inst/rot_r_delayed_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X22Y3 FDRE (Prop_CFF2_SLICEL_C_Q) - 0.040 2.142 r design_1_i/angle_encoder_1/inst/rot_r_delayed_reg/Q - net (fo=8, routed) 0.065 2.207 design_1_i/angle_encoder_1/inst/rot_r_delayed - SLICE_X20Y3 LUT5 (Prop_D5LUT_SLICEM_I2_O) - 0.051 2.258 r design_1_i/angle_encoder_1/inst/angle_reg[1]_i_1/O - net (fo=1, routed) 0.009 2.267 design_1_i/angle_encoder_1/inst/angle_reg[1]_i_1_n_0 - SLICE_X20Y3 FDRE r design_1_i/angle_encoder_1/inst/angle_reg_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.400 0.500 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.550 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.550 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.222 0.772 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - -0.295 0.477 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.165 0.642 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.019 0.661 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.246 1.907 design_1_i/angle_encoder_1/inst/CLK - SLICE_X20Y3 FDRE r design_1_i/angle_encoder_1/inst/angle_reg_reg[1]/C - clock pessimism 0.242 2.149 - SLICE_X20Y3 FDRE (Hold_DFF2_SLICEM_C_D) - 0.047 2.196 design_1_i/angle_encoder_1/inst/angle_reg_reg[1] - ------------------------------------------------------------------- - required time -2.196 - arrival time 2.267 - ------------------------------------------------------------------- - slack 0.071 - -Slack (MET) : 0.071ns (arrival time - required time) - Source: design_1_i/RotaryEnc_0/U0/i_wrap/RotL_reg/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/angle_encoder_1/inst/rot_r_delayed_reg/D - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk25_design_1_clk_wiz_0_0 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk25_design_1_clk_wiz_0_0 rise@0.000ns - clk25_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 0.167ns (logic 0.039ns (23.413%) route 0.128ns (76.587%)) - Logic Levels: 0 - Clock Path Skew: 0.049ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.907ns - Source Clock Delay (SCD): 2.101ns - Clock Pessimism Removal (CPR): -0.242ns - Clock Net Delay (Source): 1.099ns (routing 0.640ns, distribution 0.459ns) - Clock Net Delay (Destination): 1.246ns (routing 0.716ns, distribution 0.530ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.295 0.374 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.414 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.414 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.196 0.610 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - 0.230 0.840 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.145 0.985 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.017 1.002 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.099 2.101 design_1_i/RotaryEnc_0/U0/i_wrap/Clk - SLICE_X21Y2 FDRE r design_1_i/RotaryEnc_0/U0/i_wrap/RotL_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X21Y2 FDRE (Prop_BFF_SLICEL_C_Q) - 0.039 2.140 r design_1_i/RotaryEnc_0/U0/i_wrap/RotL_reg/Q - net (fo=9, routed) 0.128 2.267 design_1_i/angle_encoder_1/inst/ROT_R - SLICE_X22Y3 FDRE r design_1_i/angle_encoder_1/inst/rot_r_delayed_reg/D - ------------------------------------------------------------------- ------------------- - - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.400 0.500 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.550 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.550 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.222 0.772 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - -0.295 0.477 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.165 0.642 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.019 0.661 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.246 1.907 design_1_i/angle_encoder_1/inst/CLK - SLICE_X22Y3 FDRE r design_1_i/angle_encoder_1/inst/rot_r_delayed_reg/C - clock pessimism 0.242 2.150 - SLICE_X22Y3 FDRE (Hold_CFF2_SLICEL_C_D) - 0.047 2.197 design_1_i/angle_encoder_1/inst/rot_r_delayed_reg - ------------------------------------------------------------------- - required time -2.197 - arrival time 2.267 - ------------------------------------------------------------------- - slack 0.071 - -Slack (MET) : 0.072ns (arrival time - required time) - Source: design_1_i/VideoTiming_0/inst/HSync_reg/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/qC1C0_reg[0]/D - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk25_design_1_clk_wiz_0_0 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk25_design_1_clk_wiz_0_0 rise@0.000ns - clk25_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 0.124ns (logic 0.039ns (31.448%) route 0.085ns (68.552%)) - Logic Levels: 0 - Clock Path Skew: 0.006ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.953ns - Source Clock Delay (SCD): 2.144ns - Clock Pessimism Removal (CPR): -0.196ns - Clock Net Delay (Source): 1.142ns (routing 0.640ns, distribution 0.502ns) - Clock Net Delay (Destination): 1.292ns (routing 0.716ns, distribution 0.576ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.295 0.374 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.414 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.414 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.196 0.610 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - 0.230 0.840 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.145 0.985 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.017 1.002 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.142 2.144 design_1_i/VideoTiming_0/inst/pixClk - SLICE_X35Y18 FDRE r design_1_i/VideoTiming_0/inst/HSync_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X35Y18 FDRE (Prop_DFF_SLICEL_C_Q) - 0.039 2.183 r design_1_i/VideoTiming_0/inst/HSync_reg/Q - net (fo=2, routed) 0.085 2.268 design_1_i/HDMI_TX_0/U0/i_wrap/HSync - SLICE_X35Y18 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/qC1C0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.400 0.500 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.550 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.550 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.222 0.772 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - -0.295 0.477 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.165 0.642 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.019 0.661 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.292 1.953 design_1_i/HDMI_TX_0/U0/i_wrap/pxClk - SLICE_X35Y18 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/qC1C0_reg[0]/C - clock pessimism 0.196 2.150 - SLICE_X35Y18 FDRE (Hold_AFF_SLICEL_C_D) - 0.046 2.196 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/qC1C0_reg[0] - ------------------------------------------------------------------- - required time -2.196 - arrival time 2.268 - ------------------------------------------------------------------- - slack 0.072 - - - - - -Pulse Width Checks --------------------------------------------------------------------------------------- -Clock Name: clk25_design_1_clk_wiz_0_0 -Waveform(ns): { 0.000 20.000 } -Period(ns): 40.000 -Sources: { design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 } - -Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin -Min Period n/a BUFGCE/I n/a 1.290 40.000 38.710 BUFGCE_X0Y68 design_1_i/clk_wiz_0/inst/clkout1_buf/I -Min Period n/a MMCME4_ADV/CLKOUT0 n/a 1.071 40.000 38.929 MMCM_X0Y2 design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 -Min Period n/a FDPE/C n/a 0.550 40.000 39.450 SLICE_X48Y31 design_1_i/GameController_0/inst/health_reg_reg[0]/C -Min Period n/a FDPE/C n/a 0.550 40.000 39.450 SLICE_X48Y31 design_1_i/GameController_0/inst/health_reg_reg[1]/C -Min Period n/a FDCE/C n/a 0.550 40.000 39.450 SLICE_X48Y31 design_1_i/GameController_0/inst/health_reg_reg[2]/C -Min Period n/a FDRE/C n/a 0.550 40.000 39.450 SLICE_X40Y15 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/Cnt_reg[1]/C -Min Period n/a FDRE/C n/a 0.550 40.000 39.450 SLICE_X40Y15 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/Cnt_reg[2]/C -Min Period n/a FDRE/C n/a 0.550 40.000 39.450 SLICE_X40Y16 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/Cnt_reg[3]/C -Min Period n/a FDRE/C n/a 0.550 40.000 39.450 SLICE_X40Y17 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/Cnt_reg[4]/C -Min Period n/a FDRE/C n/a 0.550 40.000 39.450 SLICE_X35Y18 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/qC1C0_reg[0]/C -Low Pulse Width Slow FDPE/C n/a 0.275 20.000 19.725 SLICE_X48Y31 design_1_i/GameController_0/inst/health_reg_reg[0]/C -Low Pulse Width Fast FDPE/C n/a 0.275 20.000 19.725 SLICE_X48Y31 design_1_i/GameController_0/inst/health_reg_reg[0]/C -Low Pulse Width Slow FDPE/C n/a 0.275 20.000 19.725 SLICE_X48Y31 design_1_i/GameController_0/inst/health_reg_reg[1]/C -Low Pulse Width Fast FDPE/C n/a 0.275 20.000 19.725 SLICE_X48Y31 design_1_i/GameController_0/inst/health_reg_reg[1]/C -Low Pulse Width Slow FDCE/C n/a 0.275 20.000 19.725 SLICE_X48Y31 design_1_i/GameController_0/inst/health_reg_reg[2]/C -Low Pulse Width Fast FDCE/C n/a 0.275 20.000 19.725 SLICE_X48Y31 design_1_i/GameController_0/inst/health_reg_reg[2]/C -Low Pulse Width Slow FDRE/C n/a 0.275 20.000 19.725 SLICE_X40Y15 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/Cnt_reg[1]/C -Low Pulse Width Fast FDRE/C n/a 0.275 20.000 19.725 SLICE_X40Y15 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/Cnt_reg[1]/C -Low Pulse Width Slow FDRE/C n/a 0.275 20.000 19.725 SLICE_X40Y15 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/Cnt_reg[2]/C -Low Pulse Width Fast FDRE/C n/a 0.275 20.000 19.725 SLICE_X40Y15 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/Cnt_reg[2]/C -High Pulse Width Slow FDPE/C n/a 0.275 20.000 19.725 SLICE_X48Y31 design_1_i/GameController_0/inst/health_reg_reg[0]/C -High Pulse Width Fast FDPE/C n/a 0.275 20.000 19.725 SLICE_X48Y31 design_1_i/GameController_0/inst/health_reg_reg[0]/C -High Pulse Width Slow FDPE/C n/a 0.275 20.000 19.725 SLICE_X48Y31 design_1_i/GameController_0/inst/health_reg_reg[1]/C -High Pulse Width Fast FDPE/C n/a 0.275 20.000 19.725 SLICE_X48Y31 design_1_i/GameController_0/inst/health_reg_reg[1]/C -High Pulse Width Slow FDCE/C n/a 0.275 20.000 19.725 SLICE_X48Y31 design_1_i/GameController_0/inst/health_reg_reg[2]/C -High Pulse Width Fast FDCE/C n/a 0.275 20.000 19.725 SLICE_X48Y31 design_1_i/GameController_0/inst/health_reg_reg[2]/C -High Pulse Width Slow FDRE/C n/a 0.275 20.000 19.725 SLICE_X40Y15 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/Cnt_reg[1]/C -High Pulse Width Fast FDRE/C n/a 0.275 20.000 19.725 SLICE_X40Y15 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/Cnt_reg[1]/C -High Pulse Width Slow FDRE/C n/a 0.275 20.000 19.725 SLICE_X40Y15 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/Cnt_reg[2]/C -High Pulse Width Fast FDRE/C n/a 0.275 20.000 19.725 SLICE_X40Y15 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/Cnt_reg[2]/C - - - ---------------------------------------------------------------------------------------------------- -From Clock: clk25_design_1_clk_wiz_0_0 - To Clock: clk125_design_1_clk_wiz_0_0 - -Setup : 0 Failing Endpoints, Worst Slack 4.182ns, Total Violation 0.000ns -Hold : 0 Failing Endpoints, Worst Slack 0.049ns, Total Violation 0.000ns ---------------------------------------------------------------------------------------------------- - - -Max Delay Paths --------------------------------------------------------------------------------------- -Slack (MET) : 4.182ns (required time - arrival time) - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/qD_reg[0]/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[4]/D - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk125_design_1_clk_wiz_0_0 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 8.000ns (clk125_design_1_clk_wiz_0_0 rise@8.000ns - clk25_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 3.209ns (logic 0.818ns (25.489%) route 2.391ns (74.511%)) - Logic Levels: 7 (LUT3=1 LUT5=3 LUT6=3) - Clock Path Skew: -0.431ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 3.526ns = ( 11.526 - 8.000 ) - Source Clock Delay (SCD): 3.392ns - Clock Pessimism Removal (CPR): -0.565ns - Clock Uncertainty: 0.202ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.120ns - Clock Net Delay (Source): 2.084ns (routing 1.172ns, distribution 0.912ns) - Clock Net Delay (Destination): 1.681ns (routing 0.938ns, distribution 0.743ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.629 0.729 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.779 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.779 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.384 1.163 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - -0.127 1.036 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.244 1.280 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.028 1.308 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 2.084 3.392 design_1_i/HDMI_TX_0/U0/i_wrap/pxClk - SLICE_X36Y16 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/qD_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X36Y16 FDRE (Prop_FFF2_SLICEL_C_Q) - 0.081 3.473 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/qD_reg[0]/Q - net (fo=12, routed) 0.212 3.685 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/qD_reg_n_0_[0] - SLICE_X36Y15 LUT5 (Prop_D5LUT_SLICEL_I0_O) - 0.110 3.795 r design_1_i/HDMI_TX_0/U0/i_wrap/g0_b1__0/O - net (fo=2, routed) 0.206 4.001 design_1_i/HDMI_TX_0/U0/i_wrap/g0_b1__0_n_0 - SLICE_X36Y15 LUT6 (Prop_B6LUT_SLICEL_I5_O) - 0.090 4.091 r design_1_i/HDMI_TX_0/U0/i_wrap/g0_b2_i_3__0/O - net (fo=1, routed) 0.138 4.229 design_1_i/HDMI_TX_0/U0/i_wrap/g0_b2_i_3__0_n_0 - SLICE_X36Y16 LUT6 (Prop_F6LUT_SLICEL_I0_O) - 0.089 4.318 r design_1_i/HDMI_TX_0/U0/i_wrap/g0_b2_i_1__0/O - net (fo=22, routed) 0.155 4.474 design_1_i/HDMI_TX_0/U0/i_wrap/g0_b2_i_1__0_n_0 - SLICE_X37Y16 LUT6 (Prop_H6LUT_SLICEM_I0_O) - 0.125 4.599 r design_1_i/HDMI_TX_0/U0/i_wrap/Cnt[4]_i_12__0/O - net (fo=14, routed) 0.496 5.094 design_1_i/HDMI_TX_0/U0/i_wrap/Cnt[4]_i_12__0_n_0 - SLICE_X39Y12 LUT5 (Prop_D5LUT_SLICEM_I1_O) - 0.110 5.204 f design_1_i/HDMI_TX_0/U0/i_wrap/Cnt[4]_i_3__0/O - net (fo=8, routed) 0.703 5.908 design_1_i/HDMI_TX_0/U0/i_wrap/Cnt[4]_i_3__0_n_0 - SLICE_X36Y11 LUT3 (Prop_H5LUT_SLICEL_I0_O) - 0.065 5.973 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[9]_i_2__0/O - net (fo=6, routed) 0.432 6.404 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[9]_i_2__0_n_0 - SLICE_X38Y10 LUT5 (Prop_B6LUT_SLICEL_I2_O) - 0.148 6.552 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[4]_i_1__0/O - net (fo=1, routed) 0.049 6.601 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[4]_i_1__0_n_0 - SLICE_X38Y10 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[4]/D - ------------------------------------------------------------------- ------------------- - - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 8.000 8.000 r - D7 0.000 8.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 8.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.519 8.598 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 8.638 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 8.638 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.333 8.971 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - 0.630 9.601 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.220 9.821 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.024 9.845 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.681 11.526 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X38Y10 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[4]/C - clock pessimism -0.565 10.961 - clock uncertainty -0.202 10.759 - SLICE_X38Y10 FDRE (Setup_BFF_SLICEL_C_D) - 0.025 10.784 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[4] - ------------------------------------------------------------------- - required time 10.784 - arrival time -6.601 - ------------------------------------------------------------------- - slack 4.182 - -Slack (MET) : 4.185ns (required time - arrival time) - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[4]/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_GBox/sReg_reg[3]/D - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk125_design_1_clk_wiz_0_0 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 8.000ns (clk125_design_1_clk_wiz_0_0 rise@8.000ns - clk25_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 3.203ns (logic 0.728ns (22.732%) route 2.475ns (77.268%)) - Logic Levels: 7 (LUT4=1 LUT5=2 LUT6=4) - Clock Path Skew: -0.435ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 3.495ns = ( 11.495 - 8.000 ) - Source Clock Delay (SCD): 3.365ns - Clock Pessimism Removal (CPR): -0.565ns - Clock Uncertainty: 0.202ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.120ns - Clock Net Delay (Source): 2.057ns (routing 1.172ns, distribution 0.885ns) - Clock Net Delay (Destination): 1.650ns (routing 0.938ns, distribution 0.712ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.629 0.729 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.779 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.779 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.384 1.163 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - -0.127 1.036 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.244 1.280 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.028 1.308 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 2.057 3.365 design_1_i/HDMI_TX_0/U0/i_wrap/pxClk - SLICE_X30Y7 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y7 FDRE (Prop_BFF_SLICEL_C_Q) - 0.079 3.444 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[4]/Q - net (fo=5, routed) 0.507 3.952 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/p_6_in - SLICE_X36Y6 LUT5 (Prop_B5LUT_SLICEL_I4_O) - 0.104 4.056 r design_1_i/HDMI_TX_0/U0/i_wrap/g0_b2__1/O - net (fo=2, routed) 0.301 4.357 design_1_i/HDMI_TX_0/U0/i_wrap/g0_b2__1_n_0 - SLICE_X36Y5 LUT6 (Prop_F6LUT_SLICEL_I0_O) - 0.097 4.454 r design_1_i/HDMI_TX_0/U0/i_wrap/g0_b2_i_1__1/O - net (fo=23, routed) 0.100 4.554 design_1_i/HDMI_TX_0/U0/i_wrap/g0_b2_i_1__1_n_0 - SLICE_X36Y6 LUT6 (Prop_H6LUT_SLICEL_I4_O) - 0.051 4.605 r design_1_i/HDMI_TX_0/U0/i_wrap/g0_b1__4/O - net (fo=4, routed) 0.294 4.899 design_1_i/HDMI_TX_0/U0/i_wrap/g0_b1__4_n_0 - SLICE_X34Y5 LUT6 (Prop_H6LUT_SLICEM_I0_O) - 0.101 5.000 r design_1_i/HDMI_TX_0/U0/i_wrap/Cnt[4]_i_10__0/O - net (fo=8, routed) 0.258 5.258 design_1_i/HDMI_TX_0/U0/i_wrap/Cnt[4]_i_10__0_n_0 - SLICE_X35Y4 LUT4 (Prop_A6LUT_SLICEL_I2_O) - 0.149 5.407 r design_1_i/HDMI_TX_0/U0/i_wrap/Cnt[4]_i_4__1/O - net (fo=8, routed) 0.336 5.743 design_1_i/HDMI_TX_0/U0/i_wrap/Cnt[4]_i_4__1_n_0 - SLICE_X36Y4 LUT6 (Prop_C6LUT_SLICEL_I4_O) - 0.096 5.839 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[3]_i_2__0/O - net (fo=1, routed) 0.242 6.081 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[3]_i_2__0_n_0 - SLICE_X36Y4 LUT5 (Prop_H6LUT_SLICEL_I0_O) - 0.051 6.132 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[3]_i_1__1/O - net (fo=1, routed) 0.436 6.568 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[3]_i_1__1_n_0 - SLICE_X36Y3 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_GBox/sReg_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 8.000 8.000 r - D7 0.000 8.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 8.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.519 8.598 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 8.638 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 8.638 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.333 8.971 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - 0.630 9.601 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.220 9.821 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.024 9.845 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.650 11.495 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X36Y3 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_GBox/sReg_reg[3]/C - clock pessimism -0.565 10.930 - clock uncertainty -0.202 10.728 - SLICE_X36Y3 FDRE (Setup_EFF_SLICEL_C_D) - 0.025 10.753 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_GBox/sReg_reg[3] - ------------------------------------------------------------------- - required time 10.753 - arrival time -6.568 - ------------------------------------------------------------------- - slack 4.185 - -Slack (MET) : 4.205ns (required time - arrival time) - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/qD_reg[0]/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[2]/D - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk125_design_1_clk_wiz_0_0 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 8.000ns (clk125_design_1_clk_wiz_0_0 rise@8.000ns - clk25_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 3.187ns (logic 0.758ns (23.784%) route 2.429ns (76.216%)) - Logic Levels: 7 (LUT3=1 LUT5=3 LUT6=3) - Clock Path Skew: -0.431ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 3.526ns = ( 11.526 - 8.000 ) - Source Clock Delay (SCD): 3.392ns - Clock Pessimism Removal (CPR): -0.565ns - Clock Uncertainty: 0.202ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.120ns - Clock Net Delay (Source): 2.084ns (routing 1.172ns, distribution 0.912ns) - Clock Net Delay (Destination): 1.681ns (routing 0.938ns, distribution 0.743ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.629 0.729 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.779 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.779 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.384 1.163 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - -0.127 1.036 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.244 1.280 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.028 1.308 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 2.084 3.392 design_1_i/HDMI_TX_0/U0/i_wrap/pxClk - SLICE_X36Y16 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/qD_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X36Y16 FDRE (Prop_FFF2_SLICEL_C_Q) - 0.081 3.473 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/qD_reg[0]/Q - net (fo=12, routed) 0.212 3.685 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/qD_reg_n_0_[0] - SLICE_X36Y15 LUT5 (Prop_D5LUT_SLICEL_I0_O) - 0.110 3.795 r design_1_i/HDMI_TX_0/U0/i_wrap/g0_b1__0/O - net (fo=2, routed) 0.206 4.001 design_1_i/HDMI_TX_0/U0/i_wrap/g0_b1__0_n_0 - SLICE_X36Y15 LUT6 (Prop_B6LUT_SLICEL_I5_O) - 0.090 4.091 r design_1_i/HDMI_TX_0/U0/i_wrap/g0_b2_i_3__0/O - net (fo=1, routed) 0.138 4.229 design_1_i/HDMI_TX_0/U0/i_wrap/g0_b2_i_3__0_n_0 - SLICE_X36Y16 LUT6 (Prop_F6LUT_SLICEL_I0_O) - 0.089 4.318 r design_1_i/HDMI_TX_0/U0/i_wrap/g0_b2_i_1__0/O - net (fo=22, routed) 0.155 4.474 design_1_i/HDMI_TX_0/U0/i_wrap/g0_b2_i_1__0_n_0 - SLICE_X37Y16 LUT6 (Prop_H6LUT_SLICEM_I0_O) - 0.125 4.599 r design_1_i/HDMI_TX_0/U0/i_wrap/Cnt[4]_i_12__0/O - net (fo=14, routed) 0.496 5.094 design_1_i/HDMI_TX_0/U0/i_wrap/Cnt[4]_i_12__0_n_0 - SLICE_X39Y12 LUT5 (Prop_D5LUT_SLICEM_I1_O) - 0.110 5.204 f design_1_i/HDMI_TX_0/U0/i_wrap/Cnt[4]_i_3__0/O - net (fo=8, routed) 0.703 5.908 design_1_i/HDMI_TX_0/U0/i_wrap/Cnt[4]_i_3__0_n_0 - SLICE_X36Y11 LUT3 (Prop_H5LUT_SLICEL_I0_O) - 0.065 5.973 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[9]_i_2__0/O - net (fo=6, routed) 0.469 6.441 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[9]_i_2__0_n_0 - SLICE_X38Y10 LUT5 (Prop_C6LUT_SLICEL_I4_O) - 0.088 6.529 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[2]_i_1__0/O - net (fo=1, routed) 0.050 6.579 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[2]_i_1__0_n_0 - SLICE_X38Y10 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 8.000 8.000 r - D7 0.000 8.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 8.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.519 8.598 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 8.638 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 8.638 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.333 8.971 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - 0.630 9.601 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.220 9.821 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.024 9.845 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.681 11.526 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X38Y10 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[2]/C - clock pessimism -0.565 10.961 - clock uncertainty -0.202 10.759 - SLICE_X38Y10 FDRE (Setup_CFF_SLICEL_C_D) - 0.025 10.784 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[2] - ------------------------------------------------------------------- - required time 10.784 - arrival time -6.579 - ------------------------------------------------------------------- - slack 4.205 - -Slack (MET) : 4.245ns (required time - arrival time) - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/qD_reg[0]/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[0]/D - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk125_design_1_clk_wiz_0_0 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 8.000ns (clk125_design_1_clk_wiz_0_0 rise@8.000ns - clk25_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 3.147ns (logic 0.720ns (22.879%) route 2.427ns (77.121%)) - Logic Levels: 7 (LUT3=1 LUT5=3 LUT6=3) - Clock Path Skew: -0.431ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 3.526ns = ( 11.526 - 8.000 ) - Source Clock Delay (SCD): 3.392ns - Clock Pessimism Removal (CPR): -0.565ns - Clock Uncertainty: 0.202ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.120ns - Clock Net Delay (Source): 2.084ns (routing 1.172ns, distribution 0.912ns) - Clock Net Delay (Destination): 1.681ns (routing 0.938ns, distribution 0.743ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.629 0.729 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.779 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.779 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.384 1.163 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - -0.127 1.036 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.244 1.280 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.028 1.308 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 2.084 3.392 design_1_i/HDMI_TX_0/U0/i_wrap/pxClk - SLICE_X36Y16 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/qD_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X36Y16 FDRE (Prop_FFF2_SLICEL_C_Q) - 0.081 3.473 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/qD_reg[0]/Q - net (fo=12, routed) 0.212 3.685 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/qD_reg_n_0_[0] - SLICE_X36Y15 LUT5 (Prop_D5LUT_SLICEL_I0_O) - 0.110 3.795 r design_1_i/HDMI_TX_0/U0/i_wrap/g0_b1__0/O - net (fo=2, routed) 0.206 4.001 design_1_i/HDMI_TX_0/U0/i_wrap/g0_b1__0_n_0 - SLICE_X36Y15 LUT6 (Prop_B6LUT_SLICEL_I5_O) - 0.090 4.091 r design_1_i/HDMI_TX_0/U0/i_wrap/g0_b2_i_3__0/O - net (fo=1, routed) 0.138 4.229 design_1_i/HDMI_TX_0/U0/i_wrap/g0_b2_i_3__0_n_0 - SLICE_X36Y16 LUT6 (Prop_F6LUT_SLICEL_I0_O) - 0.089 4.318 r design_1_i/HDMI_TX_0/U0/i_wrap/g0_b2_i_1__0/O - net (fo=22, routed) 0.155 4.474 design_1_i/HDMI_TX_0/U0/i_wrap/g0_b2_i_1__0_n_0 - SLICE_X37Y16 LUT6 (Prop_H6LUT_SLICEM_I0_O) - 0.125 4.599 r design_1_i/HDMI_TX_0/U0/i_wrap/Cnt[4]_i_12__0/O - net (fo=14, routed) 0.496 5.094 design_1_i/HDMI_TX_0/U0/i_wrap/Cnt[4]_i_12__0_n_0 - SLICE_X39Y12 LUT5 (Prop_D5LUT_SLICEM_I1_O) - 0.110 5.204 f design_1_i/HDMI_TX_0/U0/i_wrap/Cnt[4]_i_3__0/O - net (fo=8, routed) 0.703 5.908 design_1_i/HDMI_TX_0/U0/i_wrap/Cnt[4]_i_3__0_n_0 - SLICE_X36Y11 LUT3 (Prop_H5LUT_SLICEL_I0_O) - 0.065 5.973 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[9]_i_2__0/O - net (fo=6, routed) 0.468 6.440 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[9]_i_2__0_n_0 - SLICE_X38Y10 LUT5 (Prop_D6LUT_SLICEL_I2_O) - 0.050 6.490 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[0]_i_1__0/O - net (fo=1, routed) 0.049 6.539 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[0]_i_1__0_n_0 - SLICE_X38Y10 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 8.000 8.000 r - D7 0.000 8.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 8.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.519 8.598 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 8.638 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 8.638 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.333 8.971 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - 0.630 9.601 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.220 9.821 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.024 9.845 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.681 11.526 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X38Y10 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[0]/C - clock pessimism -0.565 10.961 - clock uncertainty -0.202 10.759 - SLICE_X38Y10 FDRE (Setup_DFF_SLICEL_C_D) - 0.025 10.784 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[0] - ------------------------------------------------------------------- - required time 10.784 - arrival time -6.539 - ------------------------------------------------------------------- - slack 4.245 - -Slack (MET) : 4.251ns (required time - arrival time) - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/qD_reg[0]/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[6]/D - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk125_design_1_clk_wiz_0_0 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 8.000ns (clk125_design_1_clk_wiz_0_0 rise@8.000ns - clk25_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 3.141ns (logic 0.720ns (22.922%) route 2.421ns (77.078%)) - Logic Levels: 7 (LUT3=1 LUT5=2 LUT6=4) - Clock Path Skew: -0.431ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 3.526ns = ( 11.526 - 8.000 ) - Source Clock Delay (SCD): 3.392ns - Clock Pessimism Removal (CPR): -0.565ns - Clock Uncertainty: 0.202ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.120ns - Clock Net Delay (Source): 2.084ns (routing 1.172ns, distribution 0.912ns) - Clock Net Delay (Destination): 1.681ns (routing 0.938ns, distribution 0.743ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.629 0.729 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.779 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.779 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.384 1.163 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - -0.127 1.036 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.244 1.280 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.028 1.308 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 2.084 3.392 design_1_i/HDMI_TX_0/U0/i_wrap/pxClk - SLICE_X36Y16 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/qD_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X36Y16 FDRE (Prop_FFF2_SLICEL_C_Q) - 0.081 3.473 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/qD_reg[0]/Q - net (fo=12, routed) 0.212 3.685 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/qD_reg_n_0_[0] - SLICE_X36Y15 LUT5 (Prop_D5LUT_SLICEL_I0_O) - 0.110 3.795 r design_1_i/HDMI_TX_0/U0/i_wrap/g0_b1__0/O - net (fo=2, routed) 0.206 4.001 design_1_i/HDMI_TX_0/U0/i_wrap/g0_b1__0_n_0 - SLICE_X36Y15 LUT6 (Prop_B6LUT_SLICEL_I5_O) - 0.090 4.091 r design_1_i/HDMI_TX_0/U0/i_wrap/g0_b2_i_3__0/O - net (fo=1, routed) 0.138 4.229 design_1_i/HDMI_TX_0/U0/i_wrap/g0_b2_i_3__0_n_0 - SLICE_X36Y16 LUT6 (Prop_F6LUT_SLICEL_I0_O) - 0.089 4.318 r design_1_i/HDMI_TX_0/U0/i_wrap/g0_b2_i_1__0/O - net (fo=22, routed) 0.155 4.474 design_1_i/HDMI_TX_0/U0/i_wrap/g0_b2_i_1__0_n_0 - SLICE_X37Y16 LUT6 (Prop_H6LUT_SLICEM_I0_O) - 0.125 4.599 r design_1_i/HDMI_TX_0/U0/i_wrap/Cnt[4]_i_12__0/O - net (fo=14, routed) 0.496 5.094 design_1_i/HDMI_TX_0/U0/i_wrap/Cnt[4]_i_12__0_n_0 - SLICE_X39Y12 LUT5 (Prop_D5LUT_SLICEM_I1_O) - 0.110 5.204 f design_1_i/HDMI_TX_0/U0/i_wrap/Cnt[4]_i_3__0/O - net (fo=8, routed) 0.703 5.908 design_1_i/HDMI_TX_0/U0/i_wrap/Cnt[4]_i_3__0_n_0 - SLICE_X36Y11 LUT3 (Prop_H5LUT_SLICEL_I0_O) - 0.065 5.973 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[9]_i_2__0/O - net (fo=6, routed) 0.463 6.435 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[9]_i_2__0_n_0 - SLICE_X38Y10 LUT6 (Prop_A6LUT_SLICEL_I3_O) - 0.050 6.485 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[6]_i_1__0/O - net (fo=1, routed) 0.048 6.533 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[6]_i_1__0_n_0 - SLICE_X38Y10 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 8.000 8.000 r - D7 0.000 8.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 8.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.519 8.598 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 8.638 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 8.638 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.333 8.971 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - 0.630 9.601 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.220 9.821 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.024 9.845 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.681 11.526 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X38Y10 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[6]/C - clock pessimism -0.565 10.961 - clock uncertainty -0.202 10.759 - SLICE_X38Y10 FDRE (Setup_AFF_SLICEL_C_D) - 0.025 10.784 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[6] - ------------------------------------------------------------------- - required time 10.784 - arrival time -6.533 - ------------------------------------------------------------------- - slack 4.251 - -Slack (MET) : 4.306ns (required time - arrival time) - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/qD_reg[0]/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[9]/D - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk125_design_1_clk_wiz_0_0 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 8.000ns (clk125_design_1_clk_wiz_0_0 rise@8.000ns - clk25_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 3.052ns (logic 0.743ns (24.349%) route 2.309ns (75.651%)) - Logic Levels: 7 (LUT3=1 LUT5=3 LUT6=3) - Clock Path Skew: -0.465ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 3.492ns = ( 11.492 - 8.000 ) - Source Clock Delay (SCD): 3.392ns - Clock Pessimism Removal (CPR): -0.565ns - Clock Uncertainty: 0.202ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.120ns - Clock Net Delay (Source): 2.084ns (routing 1.172ns, distribution 0.912ns) - Clock Net Delay (Destination): 1.647ns (routing 0.938ns, distribution 0.709ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.629 0.729 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.779 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.779 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.384 1.163 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - -0.127 1.036 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.244 1.280 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.028 1.308 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 2.084 3.392 design_1_i/HDMI_TX_0/U0/i_wrap/pxClk - SLICE_X36Y16 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/qD_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X36Y16 FDRE (Prop_FFF2_SLICEL_C_Q) - 0.081 3.473 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/qD_reg[0]/Q - net (fo=12, routed) 0.212 3.685 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/qD_reg_n_0_[0] - SLICE_X36Y15 LUT5 (Prop_D5LUT_SLICEL_I0_O) - 0.110 3.795 r design_1_i/HDMI_TX_0/U0/i_wrap/g0_b1__0/O - net (fo=2, routed) 0.206 4.001 design_1_i/HDMI_TX_0/U0/i_wrap/g0_b1__0_n_0 - SLICE_X36Y15 LUT6 (Prop_B6LUT_SLICEL_I5_O) - 0.090 4.091 r design_1_i/HDMI_TX_0/U0/i_wrap/g0_b2_i_3__0/O - net (fo=1, routed) 0.138 4.229 design_1_i/HDMI_TX_0/U0/i_wrap/g0_b2_i_3__0_n_0 - SLICE_X36Y16 LUT6 (Prop_F6LUT_SLICEL_I0_O) - 0.089 4.318 r design_1_i/HDMI_TX_0/U0/i_wrap/g0_b2_i_1__0/O - net (fo=22, routed) 0.155 4.474 design_1_i/HDMI_TX_0/U0/i_wrap/g0_b2_i_1__0_n_0 - SLICE_X37Y16 LUT6 (Prop_H6LUT_SLICEM_I0_O) - 0.125 4.599 f design_1_i/HDMI_TX_0/U0/i_wrap/Cnt[4]_i_12__0/O - net (fo=14, routed) 0.496 5.094 design_1_i/HDMI_TX_0/U0/i_wrap/Cnt[4]_i_12__0_n_0 - SLICE_X39Y12 LUT5 (Prop_D5LUT_SLICEM_I1_O) - 0.110 5.204 r design_1_i/HDMI_TX_0/U0/i_wrap/Cnt[4]_i_3__0/O - net (fo=8, routed) 0.703 5.908 design_1_i/HDMI_TX_0/U0/i_wrap/Cnt[4]_i_3__0_n_0 - SLICE_X36Y11 LUT3 (Prop_H5LUT_SLICEL_I0_O) - 0.065 5.973 f design_1_i/HDMI_TX_0/U0/i_wrap/sReg[9]_i_2__0/O - net (fo=6, routed) 0.114 6.087 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[9]_i_2__0_n_0 - SLICE_X36Y10 LUT5 (Prop_B5LUT_SLICEL_I0_O) - 0.073 6.160 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[9]_i_1__0/O - net (fo=1, routed) 0.284 6.444 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[9]_i_1__0_n_0 - SLICE_X36Y11 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[9]/D - ------------------------------------------------------------------- ------------------- - - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 8.000 8.000 r - D7 0.000 8.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 8.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.519 8.598 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 8.638 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 8.638 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.333 8.971 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - 0.630 9.601 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.220 9.821 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.024 9.845 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.647 11.492 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X36Y11 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[9]/C - clock pessimism -0.565 10.927 - clock uncertainty -0.202 10.725 - SLICE_X36Y11 FDRE (Setup_EFF_SLICEL_C_D) - 0.025 10.750 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[9] - ------------------------------------------------------------------- - required time 10.750 - arrival time -6.444 - ------------------------------------------------------------------- - slack 4.306 - -Slack (MET) : 4.375ns (required time - arrival time) - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/qD_reg[0]/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[3]/D - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk125_design_1_clk_wiz_0_0 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 8.000ns (clk125_design_1_clk_wiz_0_0 rise@8.000ns - clk25_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 2.980ns (logic 0.779ns (26.137%) route 2.201ns (73.863%)) - Logic Levels: 7 (LUT5=3 LUT6=4) - Clock Path Skew: -0.467ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 3.490ns = ( 11.490 - 8.000 ) - Source Clock Delay (SCD): 3.392ns - Clock Pessimism Removal (CPR): -0.565ns - Clock Uncertainty: 0.202ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.120ns - Clock Net Delay (Source): 2.084ns (routing 1.172ns, distribution 0.912ns) - Clock Net Delay (Destination): 1.645ns (routing 0.938ns, distribution 0.707ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.629 0.729 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.779 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.779 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.384 1.163 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - -0.127 1.036 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.244 1.280 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.028 1.308 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 2.084 3.392 design_1_i/HDMI_TX_0/U0/i_wrap/pxClk - SLICE_X36Y16 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/qD_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X36Y16 FDRE (Prop_FFF2_SLICEL_C_Q) - 0.081 3.473 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/qD_reg[0]/Q - net (fo=12, routed) 0.212 3.685 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/qD_reg_n_0_[0] - SLICE_X36Y15 LUT5 (Prop_D5LUT_SLICEL_I0_O) - 0.110 3.795 r design_1_i/HDMI_TX_0/U0/i_wrap/g0_b1__0/O - net (fo=2, routed) 0.206 4.001 design_1_i/HDMI_TX_0/U0/i_wrap/g0_b1__0_n_0 - SLICE_X36Y15 LUT6 (Prop_B6LUT_SLICEL_I5_O) - 0.090 4.091 r design_1_i/HDMI_TX_0/U0/i_wrap/g0_b2_i_3__0/O - net (fo=1, routed) 0.138 4.229 design_1_i/HDMI_TX_0/U0/i_wrap/g0_b2_i_3__0_n_0 - SLICE_X36Y16 LUT6 (Prop_F6LUT_SLICEL_I0_O) - 0.089 4.318 r design_1_i/HDMI_TX_0/U0/i_wrap/g0_b2_i_1__0/O - net (fo=22, routed) 0.155 4.474 design_1_i/HDMI_TX_0/U0/i_wrap/g0_b2_i_1__0_n_0 - SLICE_X37Y16 LUT6 (Prop_H6LUT_SLICEM_I0_O) - 0.125 4.599 f design_1_i/HDMI_TX_0/U0/i_wrap/Cnt[4]_i_12__0/O - net (fo=14, routed) 0.496 5.094 design_1_i/HDMI_TX_0/U0/i_wrap/Cnt[4]_i_12__0_n_0 - SLICE_X39Y12 LUT5 (Prop_D5LUT_SLICEM_I1_O) - 0.110 5.204 r design_1_i/HDMI_TX_0/U0/i_wrap/Cnt[4]_i_3__0/O - net (fo=8, routed) 0.703 5.908 design_1_i/HDMI_TX_0/U0/i_wrap/Cnt[4]_i_3__0_n_0 - SLICE_X36Y11 LUT5 (Prop_H6LUT_SLICEL_I1_O) - 0.051 5.959 f design_1_i/HDMI_TX_0/U0/i_wrap/sReg[3]_i_2/O - net (fo=1, routed) 0.241 6.200 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[3]_i_2_n_0 - SLICE_X36Y11 LUT6 (Prop_C6LUT_SLICEL_I1_O) - 0.123 6.323 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[3]_i_1__0/O - net (fo=1, routed) 0.050 6.373 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[3]_i_1__0_n_0 - SLICE_X36Y11 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 8.000 8.000 r - D7 0.000 8.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 8.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.519 8.598 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 8.638 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 8.638 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.333 8.971 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - 0.630 9.601 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.220 9.821 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.024 9.845 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.645 11.490 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X36Y11 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[3]/C - clock pessimism -0.565 10.925 - clock uncertainty -0.202 10.723 - SLICE_X36Y11 FDRE (Setup_CFF_SLICEL_C_D) - 0.025 10.748 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[3] - ------------------------------------------------------------------- - required time 10.748 - arrival time -6.373 - ------------------------------------------------------------------- - slack 4.375 - -Slack (MET) : 4.390ns (required time - arrival time) - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/qD_reg[0]/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[7]/D - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk125_design_1_clk_wiz_0_0 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 8.000ns (clk125_design_1_clk_wiz_0_0 rise@8.000ns - clk25_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 2.966ns (logic 0.721ns (24.309%) route 2.245ns (75.691%)) - Logic Levels: 7 (LUT3=1 LUT5=2 LUT6=4) - Clock Path Skew: -0.467ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 3.490ns = ( 11.490 - 8.000 ) - Source Clock Delay (SCD): 3.392ns - Clock Pessimism Removal (CPR): -0.565ns - Clock Uncertainty: 0.202ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.120ns - Clock Net Delay (Source): 2.084ns (routing 1.172ns, distribution 0.912ns) - Clock Net Delay (Destination): 1.645ns (routing 0.938ns, distribution 0.707ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.629 0.729 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.779 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.779 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.384 1.163 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - -0.127 1.036 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.244 1.280 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.028 1.308 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 2.084 3.392 design_1_i/HDMI_TX_0/U0/i_wrap/pxClk - SLICE_X36Y16 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/qD_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X36Y16 FDRE (Prop_FFF2_SLICEL_C_Q) - 0.081 3.473 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/qD_reg[0]/Q - net (fo=12, routed) 0.212 3.685 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/qD_reg_n_0_[0] - SLICE_X36Y15 LUT5 (Prop_D5LUT_SLICEL_I0_O) - 0.110 3.795 r design_1_i/HDMI_TX_0/U0/i_wrap/g0_b1__0/O - net (fo=2, routed) 0.206 4.001 design_1_i/HDMI_TX_0/U0/i_wrap/g0_b1__0_n_0 - SLICE_X36Y15 LUT6 (Prop_B6LUT_SLICEL_I5_O) - 0.090 4.091 r design_1_i/HDMI_TX_0/U0/i_wrap/g0_b2_i_3__0/O - net (fo=1, routed) 0.138 4.229 design_1_i/HDMI_TX_0/U0/i_wrap/g0_b2_i_3__0_n_0 - SLICE_X36Y16 LUT6 (Prop_F6LUT_SLICEL_I0_O) - 0.089 4.318 r design_1_i/HDMI_TX_0/U0/i_wrap/g0_b2_i_1__0/O - net (fo=22, routed) 0.155 4.474 design_1_i/HDMI_TX_0/U0/i_wrap/g0_b2_i_1__0_n_0 - SLICE_X37Y16 LUT6 (Prop_H6LUT_SLICEM_I0_O) - 0.125 4.599 r design_1_i/HDMI_TX_0/U0/i_wrap/Cnt[4]_i_12__0/O - net (fo=14, routed) 0.496 5.094 design_1_i/HDMI_TX_0/U0/i_wrap/Cnt[4]_i_12__0_n_0 - SLICE_X39Y12 LUT5 (Prop_D5LUT_SLICEM_I1_O) - 0.110 5.204 f design_1_i/HDMI_TX_0/U0/i_wrap/Cnt[4]_i_3__0/O - net (fo=8, routed) 0.703 5.908 design_1_i/HDMI_TX_0/U0/i_wrap/Cnt[4]_i_3__0_n_0 - SLICE_X36Y11 LUT3 (Prop_H5LUT_SLICEL_I0_O) - 0.065 5.973 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[9]_i_2__0/O - net (fo=6, routed) 0.286 6.258 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[9]_i_2__0_n_0 - SLICE_X36Y11 LUT6 (Prop_B6LUT_SLICEL_I1_O) - 0.051 6.309 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[7]_i_1__0/O - net (fo=1, routed) 0.049 6.358 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[7]_i_1__0_n_0 - SLICE_X36Y11 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[7]/D - ------------------------------------------------------------------- ------------------- - - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 8.000 8.000 r - D7 0.000 8.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 8.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.519 8.598 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 8.638 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 8.638 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.333 8.971 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - 0.630 9.601 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.220 9.821 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.024 9.845 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.645 11.490 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X36Y11 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[7]/C - clock pessimism -0.565 10.925 - clock uncertainty -0.202 10.723 - SLICE_X36Y11 FDRE (Setup_BFF_SLICEL_C_D) - 0.025 10.748 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[7] - ------------------------------------------------------------------- - required time 10.748 - arrival time -6.358 - ------------------------------------------------------------------- - slack 4.390 - -Slack (MET) : 4.420ns (required time - arrival time) - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/qD_reg[0]/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[1]/D - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk125_design_1_clk_wiz_0_0 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 8.000ns (clk125_design_1_clk_wiz_0_0 rise@8.000ns - clk25_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 2.936ns (logic 0.780ns (26.567%) route 2.156ns (73.433%)) - Logic Levels: 7 (LUT5=3 LUT6=4) - Clock Path Skew: -0.467ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 3.490ns = ( 11.490 - 8.000 ) - Source Clock Delay (SCD): 3.392ns - Clock Pessimism Removal (CPR): -0.565ns - Clock Uncertainty: 0.202ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.120ns - Clock Net Delay (Source): 2.084ns (routing 1.172ns, distribution 0.912ns) - Clock Net Delay (Destination): 1.645ns (routing 0.938ns, distribution 0.707ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.629 0.729 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.779 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.779 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.384 1.163 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - -0.127 1.036 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.244 1.280 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.028 1.308 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 2.084 3.392 design_1_i/HDMI_TX_0/U0/i_wrap/pxClk - SLICE_X36Y16 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/qD_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X36Y16 FDRE (Prop_FFF2_SLICEL_C_Q) - 0.081 3.473 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/qD_reg[0]/Q - net (fo=12, routed) 0.212 3.685 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/qD_reg_n_0_[0] - SLICE_X36Y15 LUT5 (Prop_D5LUT_SLICEL_I0_O) - 0.110 3.795 r design_1_i/HDMI_TX_0/U0/i_wrap/g0_b1__0/O - net (fo=2, routed) 0.206 4.001 design_1_i/HDMI_TX_0/U0/i_wrap/g0_b1__0_n_0 - SLICE_X36Y15 LUT6 (Prop_B6LUT_SLICEL_I5_O) - 0.090 4.091 r design_1_i/HDMI_TX_0/U0/i_wrap/g0_b2_i_3__0/O - net (fo=1, routed) 0.138 4.229 design_1_i/HDMI_TX_0/U0/i_wrap/g0_b2_i_3__0_n_0 - SLICE_X36Y16 LUT6 (Prop_F6LUT_SLICEL_I0_O) - 0.089 4.318 r design_1_i/HDMI_TX_0/U0/i_wrap/g0_b2_i_1__0/O - net (fo=22, routed) 0.155 4.474 design_1_i/HDMI_TX_0/U0/i_wrap/g0_b2_i_1__0_n_0 - SLICE_X37Y16 LUT6 (Prop_H6LUT_SLICEM_I0_O) - 0.125 4.599 f design_1_i/HDMI_TX_0/U0/i_wrap/Cnt[4]_i_12__0/O - net (fo=14, routed) 0.496 5.094 design_1_i/HDMI_TX_0/U0/i_wrap/Cnt[4]_i_12__0_n_0 - SLICE_X39Y12 LUT5 (Prop_D5LUT_SLICEM_I1_O) - 0.110 5.204 r design_1_i/HDMI_TX_0/U0/i_wrap/Cnt[4]_i_3__0/O - net (fo=8, routed) 0.606 5.810 design_1_i/HDMI_TX_0/U0/i_wrap/Cnt[4]_i_3__0_n_0 - SLICE_X37Y12 LUT6 (Prop_H6LUT_SLICEM_I3_O) - 0.125 5.935 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[1]_i_2__1/O - net (fo=1, routed) 0.294 6.229 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[1]_i_2__1_n_0 - SLICE_X36Y11 LUT5 (Prop_D6LUT_SLICEL_I0_O) - 0.050 6.279 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[1]_i_1__0/O - net (fo=1, routed) 0.049 6.328 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[1]_i_1__0_n_0 - SLICE_X36Y11 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 8.000 8.000 r - D7 0.000 8.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 8.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.519 8.598 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 8.638 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 8.638 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.333 8.971 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - 0.630 9.601 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.220 9.821 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.024 9.845 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.645 11.490 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X36Y11 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[1]/C - clock pessimism -0.565 10.925 - clock uncertainty -0.202 10.723 - SLICE_X36Y11 FDRE (Setup_DFF_SLICEL_C_D) - 0.025 10.748 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[1] - ------------------------------------------------------------------- - required time 10.748 - arrival time -6.328 - ------------------------------------------------------------------- - slack 4.420 - -Slack (MET) : 4.467ns (required time - arrival time) - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[4]/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_GBox/sReg_reg[2]/D - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk125_design_1_clk_wiz_0_0 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 8.000ns (clk125_design_1_clk_wiz_0_0 rise@8.000ns - clk25_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 2.926ns (logic 0.789ns (26.963%) route 2.137ns (73.037%)) - Logic Levels: 7 (LUT3=1 LUT4=1 LUT5=2 LUT6=3) - Clock Path Skew: -0.429ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 3.501ns = ( 11.501 - 8.000 ) - Source Clock Delay (SCD): 3.365ns - Clock Pessimism Removal (CPR): -0.565ns - Clock Uncertainty: 0.202ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.120ns - Clock Net Delay (Source): 2.057ns (routing 1.172ns, distribution 0.885ns) - Clock Net Delay (Destination): 1.656ns (routing 0.938ns, distribution 0.718ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.629 0.729 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.779 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.779 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.384 1.163 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - -0.127 1.036 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.244 1.280 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.028 1.308 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 2.057 3.365 design_1_i/HDMI_TX_0/U0/i_wrap/pxClk - SLICE_X30Y7 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y7 FDRE (Prop_BFF_SLICEL_C_Q) - 0.079 3.444 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[4]/Q - net (fo=5, routed) 0.507 3.952 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/p_6_in - SLICE_X36Y6 LUT5 (Prop_B5LUT_SLICEL_I4_O) - 0.104 4.056 r design_1_i/HDMI_TX_0/U0/i_wrap/g0_b2__1/O - net (fo=2, routed) 0.301 4.357 design_1_i/HDMI_TX_0/U0/i_wrap/g0_b2__1_n_0 - SLICE_X36Y5 LUT6 (Prop_F6LUT_SLICEL_I0_O) - 0.097 4.454 r design_1_i/HDMI_TX_0/U0/i_wrap/g0_b2_i_1__1/O - net (fo=23, routed) 0.100 4.554 design_1_i/HDMI_TX_0/U0/i_wrap/g0_b2_i_1__1_n_0 - SLICE_X36Y6 LUT6 (Prop_H6LUT_SLICEL_I4_O) - 0.051 4.605 r design_1_i/HDMI_TX_0/U0/i_wrap/g0_b1__4/O - net (fo=4, routed) 0.294 4.899 design_1_i/HDMI_TX_0/U0/i_wrap/g0_b1__4_n_0 - SLICE_X34Y5 LUT6 (Prop_H6LUT_SLICEM_I0_O) - 0.101 5.000 r design_1_i/HDMI_TX_0/U0/i_wrap/Cnt[4]_i_10__0/O - net (fo=8, routed) 0.258 5.258 design_1_i/HDMI_TX_0/U0/i_wrap/Cnt[4]_i_10__0_n_0 - SLICE_X35Y4 LUT4 (Prop_A6LUT_SLICEL_I2_O) - 0.149 5.407 f design_1_i/HDMI_TX_0/U0/i_wrap/Cnt[4]_i_4__1/O - net (fo=8, routed) 0.339 5.746 design_1_i/HDMI_TX_0/U0/i_wrap/Cnt[4]_i_4__1_n_0 - SLICE_X36Y4 LUT3 (Prop_D5LUT_SLICEL_I0_O) - 0.110 5.856 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[9]_i_2__1/O - net (fo=6, routed) 0.272 6.128 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[9]_i_2__1_n_0 - SLICE_X37Y5 LUT5 (Prop_C6LUT_SLICEM_I1_O) - 0.098 6.226 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[2]_i_1__1/O - net (fo=1, routed) 0.066 6.292 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[2]_i_1__1_n_0 - SLICE_X37Y5 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_GBox/sReg_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 8.000 8.000 r - D7 0.000 8.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 8.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.519 8.598 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 8.638 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 8.638 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.333 8.971 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - 0.630 9.601 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.220 9.821 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.024 9.845 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.656 11.501 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X37Y5 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_GBox/sReg_reg[2]/C - clock pessimism -0.565 10.936 - clock uncertainty -0.202 10.734 - SLICE_X37Y5 FDRE (Setup_CFF_SLICEM_C_D) - 0.025 10.759 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_GBox/sReg_reg[2] - ------------------------------------------------------------------- - required time 10.759 - arrival time -6.292 - ------------------------------------------------------------------- - slack 4.467 - - - - - -Min Delay Paths --------------------------------------------------------------------------------------- -Slack (MET) : 0.049ns (arrival time - required time) - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/qC1C0_reg[1]/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[9]/D - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk125_design_1_clk_wiz_0_0 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk125_design_1_clk_wiz_0_0 rise@0.000ns - clk25_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 0.336ns (logic 0.097ns (28.869%) route 0.239ns (71.131%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: 0.038ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.850ns - Source Clock Delay (SCD): 2.175ns - Clock Pessimism Removal (CPR): -0.363ns - Clock Uncertainty: 0.202ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.120ns - Clock Net Delay (Source): 1.173ns (routing 0.640ns, distribution 0.533ns) - Clock Net Delay (Destination): 1.184ns (routing 0.637ns, distribution 0.547ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.295 0.374 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.414 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.414 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.196 0.610 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - 0.230 0.840 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.145 0.985 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.017 1.002 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.173 2.175 design_1_i/HDMI_TX_0/U0/i_wrap/pxClk - SLICE_X38Y16 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/qC1C0_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X38Y16 FDRE (Prop_AFF_SLICEL_C_Q) - 0.039 2.214 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/qC1C0_reg[1]/Q - net (fo=1, routed) 0.233 2.447 design_1_i/HDMI_TX_0/U0/i_wrap/qC1C0[1] - SLICE_X38Y16 LUT5 (Prop_H5LUT_SLICEL_I3_O) - 0.058 2.505 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[9]_i_1/O - net (fo=1, routed) 0.006 2.511 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[9]_i_1_n_0 - SLICE_X38Y16 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[9]/D - ------------------------------------------------------------------- ------------------- - - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.400 0.500 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.550 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.550 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.222 0.772 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - -0.295 0.477 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.170 0.647 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.019 0.666 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.184 1.850 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X38Y16 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[9]/C - clock pessimism 0.363 2.213 - clock uncertainty 0.202 2.415 - SLICE_X38Y16 FDRE (Hold_HFF2_SLICEL_C_D) - 0.047 2.462 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[9] - ------------------------------------------------------------------- - required time -2.462 - arrival time 2.511 - ------------------------------------------------------------------- - slack 0.049 - -Slack (MET) : 0.116ns (arrival time - required time) - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[1]/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_GBox/sReg_reg[1]/D - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk125_design_1_clk_wiz_0_0 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk125_design_1_clk_wiz_0_0 rise@0.000ns - clk25_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 0.432ns (logic 0.124ns (28.727%) route 0.308ns (71.273%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: 0.067ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.837ns - Source Clock Delay (SCD): 2.133ns - Clock Pessimism Removal (CPR): -0.363ns - Clock Uncertainty: 0.202ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.120ns - Clock Net Delay (Source): 1.131ns (routing 0.640ns, distribution 0.491ns) - Clock Net Delay (Destination): 1.171ns (routing 0.637ns, distribution 0.534ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.295 0.374 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.414 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.414 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.196 0.610 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - 0.230 0.840 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.145 0.985 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.017 1.002 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.131 2.133 design_1_i/HDMI_TX_0/U0/i_wrap/pxClk - SLICE_X32Y9 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X32Y9 FDRE (Prop_DFF_SLICEL_C_Q) - 0.039 2.172 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[1]/Q - net (fo=10, routed) 0.245 2.417 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/p_0_in - SLICE_X36Y4 LUT5 (Prop_D6LUT_SLICEL_I4_O) - 0.035 2.452 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[1]_i_2/O - net (fo=1, routed) 0.046 2.498 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[1]_i_2_n_0 - SLICE_X36Y3 LUT6 (Prop_H6LUT_SLICEL_I5_O) - 0.050 2.548 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[1]_i_1__1/O - net (fo=1, routed) 0.017 2.565 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[1]_i_1__1_n_0 - SLICE_X36Y3 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_GBox/sReg_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.400 0.500 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.550 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.550 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.222 0.772 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - -0.295 0.477 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.170 0.647 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.019 0.666 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.171 1.837 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X36Y3 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_GBox/sReg_reg[1]/C - clock pessimism 0.363 2.201 - clock uncertainty 0.202 2.403 - SLICE_X36Y3 FDRE (Hold_HFF_SLICEL_C_D) - 0.046 2.449 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_GBox/sReg_reg[1] - ------------------------------------------------------------------- - required time -2.449 - arrival time 2.565 - ------------------------------------------------------------------- - slack 0.116 - -Slack (MET) : 0.127ns (arrival time - required time) - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/qC1C0_reg[0]/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[8]/D - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk125_design_1_clk_wiz_0_0 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk125_design_1_clk_wiz_0_0 rise@0.000ns - clk25_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 0.448ns (logic 0.061ns (13.631%) route 0.387ns (86.369%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.072ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.853ns - Source Clock Delay (SCD): 2.144ns - Clock Pessimism Removal (CPR): -0.363ns - Clock Uncertainty: 0.202ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.120ns - Clock Net Delay (Source): 1.142ns (routing 0.640ns, distribution 0.502ns) - Clock Net Delay (Destination): 1.187ns (routing 0.637ns, distribution 0.550ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.295 0.374 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.414 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.414 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.196 0.610 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - 0.230 0.840 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.145 0.985 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.017 1.002 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.142 2.144 design_1_i/HDMI_TX_0/U0/i_wrap/pxClk - SLICE_X35Y18 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/qC1C0_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X35Y18 FDRE (Prop_AFF_SLICEL_C_Q) - 0.039 2.183 f design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/qC1C0_reg[0]/Q - net (fo=9, routed) 0.363 2.545 design_1_i/HDMI_TX_0/U0/i_wrap/qC1C0[0] - SLICE_X39Y17 LUT6 (Prop_C6LUT_SLICEM_I0_O) - 0.022 2.567 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[8]_i_1/O - net (fo=1, routed) 0.024 2.591 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[8]_i_1_n_0 - SLICE_X39Y17 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.400 0.500 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.550 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.550 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.222 0.772 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - -0.295 0.477 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.170 0.647 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.019 0.666 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.187 1.853 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X39Y17 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[8]/C - clock pessimism 0.363 2.216 - clock uncertainty 0.202 2.418 - SLICE_X39Y17 FDRE (Hold_CFF_SLICEM_C_D) - 0.046 2.464 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[8] - ------------------------------------------------------------------- - required time -2.464 - arrival time 2.591 - ------------------------------------------------------------------- - slack 0.127 - -Slack (MET) : 0.130ns (arrival time - required time) - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[0]/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_GBox/sReg_reg[0]/D - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk125_design_1_clk_wiz_0_0 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk125_design_1_clk_wiz_0_0 rise@0.000ns - clk25_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 0.423ns (logic 0.080ns (18.914%) route 0.343ns (81.086%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.839ns - Source Clock Delay (SCD): 2.157ns - Clock Pessimism Removal (CPR): -0.363ns - Clock Uncertainty: 0.202ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.120ns - Clock Net Delay (Source): 1.155ns (routing 0.640ns, distribution 0.515ns) - Clock Net Delay (Destination): 1.173ns (routing 0.637ns, distribution 0.536ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.295 0.374 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.414 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.414 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.196 0.610 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - 0.230 0.840 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.145 0.985 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.017 1.002 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.155 2.157 design_1_i/HDMI_TX_0/U0/i_wrap/pxClk - SLICE_X36Y6 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X36Y6 FDRE (Prop_EFF_SLICEL_C_Q) - 0.039 2.196 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[0]/Q - net (fo=13, routed) 0.317 2.513 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg_n_0_[0] - SLICE_X37Y5 LUT5 (Prop_D6LUT_SLICEM_I1_O) - 0.041 2.554 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[0]_i_1__1/O - net (fo=1, routed) 0.026 2.580 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[0]_i_1__1_n_0 - SLICE_X37Y5 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_GBox/sReg_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.400 0.500 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.550 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.550 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.222 0.772 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - -0.295 0.477 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.170 0.647 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.019 0.666 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.173 1.839 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X37Y5 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_GBox/sReg_reg[0]/C - clock pessimism 0.363 2.203 - clock uncertainty 0.202 2.405 - SLICE_X37Y5 FDRE (Hold_DFF_SLICEM_C_D) - 0.046 2.451 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_GBox/sReg_reg[0] - ------------------------------------------------------------------- - required time -2.451 - arrival time 2.580 - ------------------------------------------------------------------- - slack 0.130 - -Slack (MET) : 0.137ns (arrival time - required time) - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/qD_reg[5]/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[7]/D - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk125_design_1_clk_wiz_0_0 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk125_design_1_clk_wiz_0_0 rise@0.000ns - clk25_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 0.424ns (logic 0.114ns (26.912%) route 0.310ns (73.088%)) - Logic Levels: 2 (LUT3=1 LUT6=1) - Clock Path Skew: 0.038ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.831ns - Source Clock Delay (SCD): 2.156ns - Clock Pessimism Removal (CPR): -0.363ns - Clock Uncertainty: 0.202ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.120ns - Clock Net Delay (Source): 1.154ns (routing 0.640ns, distribution 0.514ns) - Clock Net Delay (Destination): 1.165ns (routing 0.637ns, distribution 0.528ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.295 0.374 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.414 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.414 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.196 0.610 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - 0.230 0.840 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.145 0.985 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.017 1.002 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.154 2.156 design_1_i/HDMI_TX_0/U0/i_wrap/pxClk - SLICE_X36Y10 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/qD_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X36Y10 FDRE (Prop_EFF2_SLICEL_C_Q) - 0.040 2.196 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/qD_reg[5]/Q - net (fo=6, routed) 0.115 2.311 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_Enc/p_8_in - SLICE_X36Y15 LUT3 (Prop_C6LUT_SLICEL_I2_O) - 0.059 2.370 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[7]_i_3__0/O - net (fo=1, routed) 0.180 2.550 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[7]_i_3__0_n_0 - SLICE_X36Y11 LUT6 (Prop_B6LUT_SLICEL_I3_O) - 0.015 2.565 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[7]_i_1__0/O - net (fo=1, routed) 0.015 2.580 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[7]_i_1__0_n_0 - SLICE_X36Y11 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[7]/D - ------------------------------------------------------------------- ------------------- - - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.400 0.500 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.550 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.550 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.222 0.772 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - -0.295 0.477 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.170 0.647 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.019 0.666 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.165 1.831 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X36Y11 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[7]/C - clock pessimism 0.363 2.195 - clock uncertainty 0.202 2.397 - SLICE_X36Y11 FDRE (Hold_BFF_SLICEL_C_D) - 0.046 2.443 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[7] - ------------------------------------------------------------------- - required time -2.443 - arrival time 2.580 - ------------------------------------------------------------------- - slack 0.137 - -Slack (MET) : 0.139ns (arrival time - required time) - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/qC1C0_reg[0]/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[7]/D - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk125_design_1_clk_wiz_0_0 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk125_design_1_clk_wiz_0_0 rise@0.000ns - clk25_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 0.456ns (logic 0.089ns (19.508%) route 0.367ns (80.492%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.069ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.850ns - Source Clock Delay (SCD): 2.144ns - Clock Pessimism Removal (CPR): -0.363ns - Clock Uncertainty: 0.202ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.120ns - Clock Net Delay (Source): 1.142ns (routing 0.640ns, distribution 0.502ns) - Clock Net Delay (Destination): 1.184ns (routing 0.637ns, distribution 0.547ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.295 0.374 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.414 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.414 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.196 0.610 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - 0.230 0.840 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.145 0.985 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.017 1.002 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.142 2.144 design_1_i/HDMI_TX_0/U0/i_wrap/pxClk - SLICE_X35Y18 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/qC1C0_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X35Y18 FDRE (Prop_AFF_SLICEL_C_Q) - 0.039 2.183 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/qC1C0_reg[0]/Q - net (fo=9, routed) 0.351 2.534 design_1_i/HDMI_TX_0/U0/i_wrap/qC1C0[0] - SLICE_X38Y16 LUT6 (Prop_G6LUT_SLICEL_I5_O) - 0.050 2.584 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[7]_i_1/O - net (fo=1, routed) 0.016 2.600 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[7]_i_1_n_0 - SLICE_X38Y16 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[7]/D - ------------------------------------------------------------------- ------------------- - - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.400 0.500 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.550 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.550 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.222 0.772 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - -0.295 0.477 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.170 0.647 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.019 0.666 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.184 1.850 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X38Y16 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[7]/C - clock pessimism 0.363 2.213 - clock uncertainty 0.202 2.415 - SLICE_X38Y16 FDRE (Hold_GFF_SLICEL_C_D) - 0.046 2.461 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[7] - ------------------------------------------------------------------- - required time -2.461 - arrival time 2.600 - ------------------------------------------------------------------- - slack 0.139 - -Slack (MET) : 0.153ns (arrival time - required time) - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/qD_reg[6]/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[6]/D - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk125_design_1_clk_wiz_0_0 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk125_design_1_clk_wiz_0_0 rise@0.000ns - clk25_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 0.439ns (logic 0.129ns (29.417%) route 0.310ns (70.582%)) - Logic Levels: 2 (LUT3=1 LUT6=1) - Clock Path Skew: 0.037ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.853ns - Source Clock Delay (SCD): 2.179ns - Clock Pessimism Removal (CPR): -0.363ns - Clock Uncertainty: 0.202ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.120ns - Clock Net Delay (Source): 1.177ns (routing 0.640ns, distribution 0.537ns) - Clock Net Delay (Destination): 1.187ns (routing 0.637ns, distribution 0.550ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.295 0.374 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.414 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.414 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.196 0.610 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - 0.230 0.840 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.145 0.985 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.017 1.002 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.177 2.179 design_1_i/HDMI_TX_0/U0/i_wrap/pxClk - SLICE_X38Y12 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/qD_reg[6]/C - ------------------------------------------------------------------- ------------------- - SLICE_X38Y12 FDRE (Prop_EFF2_SLICEL_C_Q) - 0.040 2.219 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/qD_reg[6]/Q - net (fo=8, routed) 0.143 2.362 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/p_10_in - SLICE_X39Y16 LUT3 (Prop_H5LUT_SLICEM_I0_O) - 0.048 2.410 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[6]_i_2__0/O - net (fo=1, routed) 0.149 2.559 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[6]_i_2__0_n_0 - SLICE_X39Y16 LUT6 (Prop_A6LUT_SLICEM_I0_O) - 0.041 2.600 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[6]_i_1/O - net (fo=1, routed) 0.018 2.618 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[6]_i_1_n_0 - SLICE_X39Y16 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.400 0.500 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.550 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.550 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.222 0.772 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - -0.295 0.477 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.170 0.647 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.019 0.666 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.187 1.853 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X39Y16 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[6]/C - clock pessimism 0.363 2.216 - clock uncertainty 0.202 2.418 - SLICE_X39Y16 FDRE (Hold_AFF_SLICEM_C_D) - 0.046 2.464 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[6] - ------------------------------------------------------------------- - required time -2.464 - arrival time 2.618 - ------------------------------------------------------------------- - slack 0.153 - -Slack (MET) : 0.156ns (arrival time - required time) - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/Cnt_reg[3]/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[1]/D - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk125_design_1_clk_wiz_0_0 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk125_design_1_clk_wiz_0_0 rise@0.000ns - clk25_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 0.432ns (logic 0.103ns (23.837%) route 0.329ns (76.163%)) - Logic Levels: 2 (LUT6=2) - Clock Path Skew: 0.028ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.850ns - Source Clock Delay (SCD): 2.185ns - Clock Pessimism Removal (CPR): -0.363ns - Clock Uncertainty: 0.202ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.120ns - Clock Net Delay (Source): 1.183ns (routing 0.640ns, distribution 0.543ns) - Clock Net Delay (Destination): 1.184ns (routing 0.637ns, distribution 0.547ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.295 0.374 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.414 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.414 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.196 0.610 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - 0.230 0.840 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.145 0.985 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.017 1.002 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.183 2.185 design_1_i/HDMI_TX_0/U0/i_wrap/pxClk - SLICE_X40Y16 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/Cnt_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X40Y16 FDRE (Prop_HFF_SLICEM_C_Q) - 0.039 2.224 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/Cnt_reg[3]/Q - net (fo=10, routed) 0.063 2.287 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/Cnt_reg_n_0_[3] - SLICE_X40Y15 LUT6 (Prop_G6LUT_SLICEM_I2_O) - 0.050 2.337 r design_1_i/HDMI_TX_0/U0/i_wrap/Cnt[4]_i_6/O - net (fo=7, routed) 0.250 2.587 design_1_i/HDMI_TX_0/U0/i_wrap/Cnt[4]_i_6_n_0 - SLICE_X38Y17 LUT6 (Prop_D6LUT_SLICEL_I3_O) - 0.014 2.601 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[1]_i_1/O - net (fo=1, routed) 0.016 2.617 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[1]_i_1_n_0 - SLICE_X38Y17 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.400 0.500 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.550 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.550 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.222 0.772 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - -0.295 0.477 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.170 0.647 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.019 0.666 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.184 1.850 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X38Y17 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[1]/C - clock pessimism 0.363 2.214 - clock uncertainty 0.202 2.416 - SLICE_X38Y17 FDRE (Hold_DFF_SLICEL_C_D) - 0.046 2.462 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[1] - ------------------------------------------------------------------- - required time -2.462 - arrival time 2.617 - ------------------------------------------------------------------- - slack 0.156 - -Slack (MET) : 0.162ns (arrival time - required time) - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/Cnt_reg[3]/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[3]/D - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk125_design_1_clk_wiz_0_0 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk125_design_1_clk_wiz_0_0 rise@0.000ns - clk25_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 0.443ns (logic 0.111ns (25.073%) route 0.332ns (74.927%)) - Logic Levels: 2 (LUT6=2) - Clock Path Skew: 0.032ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.854ns - Source Clock Delay (SCD): 2.185ns - Clock Pessimism Removal (CPR): -0.363ns - Clock Uncertainty: 0.202ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.120ns - Clock Net Delay (Source): 1.183ns (routing 0.640ns, distribution 0.543ns) - Clock Net Delay (Destination): 1.188ns (routing 0.637ns, distribution 0.551ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.295 0.374 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.414 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.414 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.196 0.610 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - 0.230 0.840 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.145 0.985 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.017 1.002 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.183 2.185 design_1_i/HDMI_TX_0/U0/i_wrap/pxClk - SLICE_X40Y16 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/Cnt_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X40Y16 FDRE (Prop_HFF_SLICEM_C_Q) - 0.039 2.224 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/Cnt_reg[3]/Q - net (fo=10, routed) 0.063 2.287 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/Cnt_reg_n_0_[3] - SLICE_X40Y15 LUT6 (Prop_G6LUT_SLICEM_I2_O) - 0.050 2.337 r design_1_i/HDMI_TX_0/U0/i_wrap/Cnt[4]_i_6/O - net (fo=7, routed) 0.253 2.590 design_1_i/HDMI_TX_0/U0/i_wrap/Cnt[4]_i_6_n_0 - SLICE_X38Y17 LUT6 (Prop_G6LUT_SLICEL_I4_O) - 0.022 2.612 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[3]_i_1/O - net (fo=1, routed) 0.016 2.628 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[3]_i_1_n_0 - SLICE_X38Y17 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.400 0.500 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.550 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.550 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.222 0.772 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - -0.295 0.477 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.170 0.647 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.019 0.666 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.188 1.854 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X38Y17 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[3]/C - clock pessimism 0.363 2.218 - clock uncertainty 0.202 2.420 - SLICE_X38Y17 FDRE (Hold_GFF_SLICEL_C_D) - 0.046 2.466 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_GBox/sReg_reg[3] - ------------------------------------------------------------------- - required time -2.466 - arrival time 2.628 - ------------------------------------------------------------------- - slack 0.162 - -Slack (MET) : 0.165ns (arrival time - required time) - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/qDE_reg/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[3]/D - (rising edge-triggered cell FDRE clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk125_design_1_clk_wiz_0_0 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk125_design_1_clk_wiz_0_0 rise@0.000ns - clk25_design_1_clk_wiz_0_0 rise@0.000ns) - Data Path Delay: 0.469ns (logic 0.074ns (15.779%) route 0.395ns (84.221%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.056ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.831ns - Source Clock Delay (SCD): 2.139ns - Clock Pessimism Removal (CPR): -0.363ns - Clock Uncertainty: 0.202ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.120ns - Clock Net Delay (Source): 1.137ns (routing 0.640ns, distribution 0.497ns) - Clock Net Delay (Destination): 1.165ns (routing 0.637ns, distribution 0.528ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.295 0.374 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.414 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.414 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.196 0.610 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - 0.230 0.840 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.145 0.985 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.017 1.002 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.137 2.139 design_1_i/HDMI_TX_0/U0/i_wrap/pxClk - SLICE_X33Y21 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/qDE_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y21 FDRE (Prop_DFF_SLICEL_C_Q) - 0.039 2.178 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_Enc/qDE_reg/Q - net (fo=33, routed) 0.378 2.556 design_1_i/HDMI_TX_0/U0/i_wrap/qDE - SLICE_X36Y11 LUT6 (Prop_C6LUT_SLICEL_I5_O) - 0.035 2.591 r design_1_i/HDMI_TX_0/U0/i_wrap/sReg[3]_i_1__0/O - net (fo=1, routed) 0.017 2.608 design_1_i/HDMI_TX_0/U0/i_wrap/sReg[3]_i_1__0_n_0 - SLICE_X36Y11 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.400 0.500 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.550 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.550 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.222 0.772 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - -0.295 0.477 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.170 0.647 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.019 0.666 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.165 1.831 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - SLICE_X36Y11 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[3]/C - clock pessimism 0.363 2.195 - clock uncertainty 0.202 2.397 - SLICE_X36Y11 FDRE (Hold_CFF_SLICEL_C_D) - 0.046 2.443 design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_GBox/sReg_reg[3] - ------------------------------------------------------------------- - required time -2.443 - arrival time 2.608 - ------------------------------------------------------------------- - slack 0.165 - - - - - --------------------------------------------------------------------------------------- -Path Group: (none) -From Clock: - To Clock: - -Max Delay 473 Endpoints -Min Delay 473 Endpoints --------------------------------------------------------------------------------------- - - -Max Delay Paths --------------------------------------------------------------------------------------- -Slack: inf - Source: design_1_i/EnemyController_0/inst/enemies_reg[19][is_active]/C - (rising edge-triggered cell FDCE) - Destination: design_1_i/EnemyController_0/inst/enemies_reg[23][R][7]/CE - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 4.362ns (logic 0.366ns (8.391%) route 3.996ns (91.609%)) - Logic Levels: 4 (FDCE=1 LUT6=3) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X18Y12 FDCE 0.000 0.000 r design_1_i/EnemyController_0/inst/enemies_reg[19][is_active]/C - SLICE_X18Y12 FDCE (Prop_HFF2_SLICEL_C_Q) - 0.080 0.080 f design_1_i/EnemyController_0/inst/enemies_reg[19][is_active]/Q - net (fo=158, routed) 1.543 1.623 design_1_i/EnemyController_0/inst/enemies_reg[19][is_active]_0 - SLICE_X22Y23 LUT6 (Prop_H6LUT_SLICEL_I0_O) - 0.150 1.773 f design_1_i/EnemyController_0/inst/enemies[23][is_active]_i_10/O - net (fo=2, routed) 0.250 2.023 design_1_i/EnemyController_0/inst/enemies[23][is_active]_i_10_n_0 - SLICE_X22Y24 LUT6 (Prop_G6LUT_SLICEL_I5_O) - 0.097 2.120 f design_1_i/EnemyController_0/inst/enemies[23][is_active]_i_3/O - net (fo=256, routed) 1.396 3.516 design_1_i/EnemyController_0/inst/enemies[23][is_active]_i_3_n_0 - SLICE_X34Y51 LUT6 (Prop_H6LUT_SLICEM_I2_O) - 0.039 3.555 r design_1_i/EnemyController_0/inst/enemies[23][R][9]_i_1/O - net (fo=9, routed) 0.807 4.362 design_1_i/EnemyController_0/inst/enemies[23][R] - SLICE_X36Y53 FDCE r design_1_i/EnemyController_0/inst/enemies_reg[23][R][7]/CE - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: design_1_i/EnemyController_0/inst/enemies_reg[19][is_active]/C - (rising edge-triggered cell FDCE) - Destination: design_1_i/EnemyController_0/inst/enemies_reg[14][R][5]/D - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 4.191ns (logic 0.473ns (11.286%) route 3.718ns (88.714%)) - Logic Levels: 4 (FDCE=1 LUT6=3) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X18Y12 FDCE 0.000 0.000 r design_1_i/EnemyController_0/inst/enemies_reg[19][is_active]/C - SLICE_X18Y12 FDCE (Prop_HFF2_SLICEL_C_Q) - 0.080 0.080 f design_1_i/EnemyController_0/inst/enemies_reg[19][is_active]/Q - net (fo=158, routed) 1.543 1.623 design_1_i/EnemyController_0/inst/enemies_reg[19][is_active]_0 - SLICE_X22Y23 LUT6 (Prop_H6LUT_SLICEL_I0_O) - 0.150 1.773 f design_1_i/EnemyController_0/inst/enemies[23][is_active]_i_10/O - net (fo=2, routed) 0.250 2.023 design_1_i/EnemyController_0/inst/enemies[23][is_active]_i_10_n_0 - SLICE_X22Y24 LUT6 (Prop_G6LUT_SLICEL_I5_O) - 0.097 2.120 f design_1_i/EnemyController_0/inst/enemies[23][is_active]_i_3/O - net (fo=256, routed) 1.876 3.996 design_1_i/EnemyController_0/inst/enemies[23][is_active]_i_3_n_0 - SLICE_X12Y19 LUT6 (Prop_D6LUT_SLICEL_I5_O) - 0.146 4.142 r design_1_i/EnemyController_0/inst/enemies[14][R][5]_i_1/O - net (fo=1, routed) 0.049 4.191 design_1_i/EnemyController_0/inst/enemies[14][R][5]_i_1_n_0 - SLICE_X12Y19 FDCE r design_1_i/EnemyController_0/inst/enemies_reg[14][R][5]/D - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: design_1_i/EnemyController_0/inst/enemies_reg[19][is_active]/C - (rising edge-triggered cell FDCE) - Destination: design_1_i/EnemyController_0/inst/enemies_reg[14][R][1]/D - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 4.114ns (logic 0.473ns (11.496%) route 3.641ns (88.504%)) - Logic Levels: 4 (FDCE=1 LUT6=3) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X18Y12 FDCE 0.000 0.000 r design_1_i/EnemyController_0/inst/enemies_reg[19][is_active]/C - SLICE_X18Y12 FDCE (Prop_HFF2_SLICEL_C_Q) - 0.080 0.080 r design_1_i/EnemyController_0/inst/enemies_reg[19][is_active]/Q - net (fo=158, routed) 1.543 1.623 design_1_i/EnemyController_0/inst/enemies_reg[19][is_active]_0 - SLICE_X22Y23 LUT6 (Prop_H6LUT_SLICEL_I0_O) - 0.150 1.773 r design_1_i/EnemyController_0/inst/enemies[23][is_active]_i_10/O - net (fo=2, routed) 0.250 2.023 design_1_i/EnemyController_0/inst/enemies[23][is_active]_i_10_n_0 - SLICE_X22Y24 LUT6 (Prop_G6LUT_SLICEL_I5_O) - 0.097 2.120 r design_1_i/EnemyController_0/inst/enemies[23][is_active]_i_3/O - net (fo=256, routed) 1.799 3.919 design_1_i/EnemyController_0/inst/enemies[23][is_active]_i_3_n_0 - SLICE_X12Y22 LUT6 (Prop_D6LUT_SLICEL_I1_O) - 0.146 4.065 r design_1_i/EnemyController_0/inst/enemies[14][R][1]_i_1/O - net (fo=1, routed) 0.049 4.114 design_1_i/EnemyController_0/inst/enemies[14][R][1]_i_1_n_0 - SLICE_X12Y22 FDCE r design_1_i/EnemyController_0/inst/enemies_reg[14][R][1]/D - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: design_1_i/EnemyController_0/inst/enemies_reg[19][is_active]/C - (rising edge-triggered cell FDCE) - Destination: design_1_i/EnemyController_0/inst/enemies_reg[14][R][6]/D - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 4.109ns (logic 0.451ns (10.976%) route 3.658ns (89.024%)) - Logic Levels: 4 (FDCE=1 LUT6=3) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X18Y12 FDCE 0.000 0.000 r design_1_i/EnemyController_0/inst/enemies_reg[19][is_active]/C - SLICE_X18Y12 FDCE (Prop_HFF2_SLICEL_C_Q) - 0.080 0.080 f design_1_i/EnemyController_0/inst/enemies_reg[19][is_active]/Q - net (fo=158, routed) 1.543 1.623 design_1_i/EnemyController_0/inst/enemies_reg[19][is_active]_0 - SLICE_X22Y23 LUT6 (Prop_H6LUT_SLICEL_I0_O) - 0.150 1.773 f design_1_i/EnemyController_0/inst/enemies[23][is_active]_i_10/O - net (fo=2, routed) 0.250 2.023 design_1_i/EnemyController_0/inst/enemies[23][is_active]_i_10_n_0 - SLICE_X22Y24 LUT6 (Prop_G6LUT_SLICEL_I5_O) - 0.097 2.120 f design_1_i/EnemyController_0/inst/enemies[23][is_active]_i_3/O - net (fo=256, routed) 1.814 3.934 design_1_i/EnemyController_0/inst/enemies[23][is_active]_i_3_n_0 - SLICE_X12Y19 LUT6 (Prop_H6LUT_SLICEL_I5_O) - 0.124 4.058 r design_1_i/EnemyController_0/inst/enemies[14][R][6]_i_1/O - net (fo=1, routed) 0.051 4.109 design_1_i/EnemyController_0/inst/enemies[14][R][6]_i_1_n_0 - SLICE_X12Y19 FDCE r design_1_i/EnemyController_0/inst/enemies_reg[14][R][6]/D - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: design_1_i/EnemyController_0/inst/enemies_reg[19][is_active]/C - (rising edge-triggered cell FDCE) - Destination: design_1_i/EnemyController_0/inst/enemies_reg[15][R][9]/D - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 4.000ns (logic 0.423ns (10.574%) route 3.577ns (89.426%)) - Logic Levels: 4 (FDCE=1 LUT6=3) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X18Y12 FDCE 0.000 0.000 r design_1_i/EnemyController_0/inst/enemies_reg[19][is_active]/C - SLICE_X18Y12 FDCE (Prop_HFF2_SLICEL_C_Q) - 0.080 0.080 r design_1_i/EnemyController_0/inst/enemies_reg[19][is_active]/Q - net (fo=158, routed) 1.543 1.623 design_1_i/EnemyController_0/inst/enemies_reg[19][is_active]_0 - SLICE_X22Y23 LUT6 (Prop_H6LUT_SLICEL_I0_O) - 0.150 1.773 r design_1_i/EnemyController_0/inst/enemies[23][is_active]_i_10/O - net (fo=2, routed) 0.250 2.023 design_1_i/EnemyController_0/inst/enemies[23][is_active]_i_10_n_0 - SLICE_X22Y24 LUT6 (Prop_G6LUT_SLICEL_I5_O) - 0.097 2.120 r design_1_i/EnemyController_0/inst/enemies[23][is_active]_i_3/O - net (fo=256, routed) 1.734 3.854 design_1_i/EnemyController_0/inst/enemies[23][is_active]_i_3_n_0 - SLICE_X12Y29 LUT6 (Prop_C6LUT_SLICEL_I4_O) - 0.096 3.950 r design_1_i/EnemyController_0/inst/enemies[15][R][9]_i_2/O - net (fo=1, routed) 0.050 4.000 design_1_i/EnemyController_0/inst/enemies[15][R][9]_i_2_n_0 - SLICE_X12Y29 FDCE r design_1_i/EnemyController_0/inst/enemies_reg[15][R][9]/D - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: design_1_i/EnemyController_0/inst/enemies_reg[19][is_active]/C - (rising edge-triggered cell FDCE) - Destination: design_1_i/EnemyController_0/inst/enemies_reg[14][R][2]/D - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 3.993ns (logic 0.363ns (9.090%) route 3.630ns (90.910%)) - Logic Levels: 4 (FDCE=1 LUT6=3) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X18Y12 FDCE 0.000 0.000 r design_1_i/EnemyController_0/inst/enemies_reg[19][is_active]/C - SLICE_X18Y12 FDCE (Prop_HFF2_SLICEL_C_Q) - 0.080 0.080 r design_1_i/EnemyController_0/inst/enemies_reg[19][is_active]/Q - net (fo=158, routed) 1.543 1.623 design_1_i/EnemyController_0/inst/enemies_reg[19][is_active]_0 - SLICE_X22Y23 LUT6 (Prop_H6LUT_SLICEL_I0_O) - 0.150 1.773 r design_1_i/EnemyController_0/inst/enemies[23][is_active]_i_10/O - net (fo=2, routed) 0.250 2.023 design_1_i/EnemyController_0/inst/enemies[23][is_active]_i_10_n_0 - SLICE_X22Y24 LUT6 (Prop_G6LUT_SLICEL_I5_O) - 0.097 2.120 r design_1_i/EnemyController_0/inst/enemies[23][is_active]_i_3/O - net (fo=256, routed) 1.788 3.908 design_1_i/EnemyController_0/inst/enemies[23][is_active]_i_3_n_0 - SLICE_X12Y21 LUT6 (Prop_D6LUT_SLICEL_I1_O) - 0.036 3.944 r design_1_i/EnemyController_0/inst/enemies[14][R][2]_i_1/O - net (fo=1, routed) 0.049 3.993 design_1_i/EnemyController_0/inst/enemies[14][R][2]_i_1_n_0 - SLICE_X12Y21 FDCE r design_1_i/EnemyController_0/inst/enemies_reg[14][R][2]/D - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: design_1_i/EnemyController_0/inst/enemies_reg[19][is_active]/C - (rising edge-triggered cell FDCE) - Destination: design_1_i/EnemyController_0/inst/enemies_reg[15][R][8]/D - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 3.988ns (logic 0.363ns (9.102%) route 3.625ns (90.898%)) - Logic Levels: 4 (FDCE=1 LUT6=3) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X18Y12 FDCE 0.000 0.000 r design_1_i/EnemyController_0/inst/enemies_reg[19][is_active]/C - SLICE_X18Y12 FDCE (Prop_HFF2_SLICEL_C_Q) - 0.080 0.080 r design_1_i/EnemyController_0/inst/enemies_reg[19][is_active]/Q - net (fo=158, routed) 1.543 1.623 design_1_i/EnemyController_0/inst/enemies_reg[19][is_active]_0 - SLICE_X22Y23 LUT6 (Prop_H6LUT_SLICEL_I0_O) - 0.150 1.773 r design_1_i/EnemyController_0/inst/enemies[23][is_active]_i_10/O - net (fo=2, routed) 0.250 2.023 design_1_i/EnemyController_0/inst/enemies[23][is_active]_i_10_n_0 - SLICE_X22Y24 LUT6 (Prop_G6LUT_SLICEL_I5_O) - 0.097 2.120 r design_1_i/EnemyController_0/inst/enemies[23][is_active]_i_3/O - net (fo=256, routed) 1.783 3.903 design_1_i/EnemyController_0/inst/enemies[23][is_active]_i_3_n_0 - SLICE_X12Y29 LUT6 (Prop_D6LUT_SLICEL_I3_O) - 0.036 3.939 r design_1_i/EnemyController_0/inst/enemies[15][R][8]_i_1/O - net (fo=1, routed) 0.049 3.988 design_1_i/EnemyController_0/inst/enemies[15][R][8]_i_1_n_0 - SLICE_X12Y29 FDCE r design_1_i/EnemyController_0/inst/enemies_reg[15][R][8]/D - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: design_1_i/EnemyController_0/inst/enemies_reg[19][is_active]/C - (rising edge-triggered cell FDCE) - Destination: design_1_i/EnemyController_0/inst/enemies_reg[9][R][4]/CE - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 3.984ns (logic 0.363ns (9.111%) route 3.621ns (90.889%)) - Logic Levels: 4 (FDCE=1 LUT6=3) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X18Y12 FDCE 0.000 0.000 r design_1_i/EnemyController_0/inst/enemies_reg[19][is_active]/C - SLICE_X18Y12 FDCE (Prop_HFF2_SLICEL_C_Q) - 0.080 0.080 f design_1_i/EnemyController_0/inst/enemies_reg[19][is_active]/Q - net (fo=158, routed) 1.543 1.623 design_1_i/EnemyController_0/inst/enemies_reg[19][is_active]_0 - SLICE_X22Y23 LUT6 (Prop_H6LUT_SLICEL_I0_O) - 0.150 1.773 f design_1_i/EnemyController_0/inst/enemies[23][is_active]_i_10/O - net (fo=2, routed) 0.250 2.023 design_1_i/EnemyController_0/inst/enemies[23][is_active]_i_10_n_0 - SLICE_X22Y24 LUT6 (Prop_G6LUT_SLICEL_I5_O) - 0.097 2.120 f design_1_i/EnemyController_0/inst/enemies[23][is_active]_i_3/O - net (fo=256, routed) 1.535 3.655 design_1_i/EnemyController_0/inst/enemies[23][is_active]_i_3_n_0 - SLICE_X36Y17 LUT6 (Prop_H6LUT_SLICEL_I2_O) - 0.036 3.691 r design_1_i/EnemyController_0/inst/enemies[9][R][9]_i_1/O - net (fo=9, routed) 0.294 3.984 design_1_i/EnemyController_0/inst/enemies[9][R] - SLICE_X37Y18 FDCE r design_1_i/EnemyController_0/inst/enemies_reg[9][R][4]/CE - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: design_1_i/EnemyController_0/inst/enemies_reg[19][is_active]/C - (rising edge-triggered cell FDCE) - Destination: design_1_i/EnemyController_0/inst/enemies_reg[9][R][3]/CE - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 3.945ns (logic 0.363ns (9.202%) route 3.582ns (90.798%)) - Logic Levels: 4 (FDCE=1 LUT6=3) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X18Y12 FDCE 0.000 0.000 r design_1_i/EnemyController_0/inst/enemies_reg[19][is_active]/C - SLICE_X18Y12 FDCE (Prop_HFF2_SLICEL_C_Q) - 0.080 0.080 f design_1_i/EnemyController_0/inst/enemies_reg[19][is_active]/Q - net (fo=158, routed) 1.543 1.623 design_1_i/EnemyController_0/inst/enemies_reg[19][is_active]_0 - SLICE_X22Y23 LUT6 (Prop_H6LUT_SLICEL_I0_O) - 0.150 1.773 f design_1_i/EnemyController_0/inst/enemies[23][is_active]_i_10/O - net (fo=2, routed) 0.250 2.023 design_1_i/EnemyController_0/inst/enemies[23][is_active]_i_10_n_0 - SLICE_X22Y24 LUT6 (Prop_G6LUT_SLICEL_I5_O) - 0.097 2.120 f design_1_i/EnemyController_0/inst/enemies[23][is_active]_i_3/O - net (fo=256, routed) 1.535 3.655 design_1_i/EnemyController_0/inst/enemies[23][is_active]_i_3_n_0 - SLICE_X36Y17 LUT6 (Prop_H6LUT_SLICEL_I2_O) - 0.036 3.691 r design_1_i/EnemyController_0/inst/enemies[9][R][9]_i_1/O - net (fo=9, routed) 0.254 3.945 design_1_i/EnemyController_0/inst/enemies[9][R] - SLICE_X37Y18 FDCE r design_1_i/EnemyController_0/inst/enemies_reg[9][R][3]/CE - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: design_1_i/EnemyController_0/inst/enemies_reg[19][is_active]/C - (rising edge-triggered cell FDCE) - Destination: design_1_i/EnemyController_0/inst/enemies_reg[9][R][5]/CE - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 3.945ns (logic 0.363ns (9.202%) route 3.582ns (90.798%)) - Logic Levels: 4 (FDCE=1 LUT6=3) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X18Y12 FDCE 0.000 0.000 r design_1_i/EnemyController_0/inst/enemies_reg[19][is_active]/C - SLICE_X18Y12 FDCE (Prop_HFF2_SLICEL_C_Q) - 0.080 0.080 f design_1_i/EnemyController_0/inst/enemies_reg[19][is_active]/Q - net (fo=158, routed) 1.543 1.623 design_1_i/EnemyController_0/inst/enemies_reg[19][is_active]_0 - SLICE_X22Y23 LUT6 (Prop_H6LUT_SLICEL_I0_O) - 0.150 1.773 f design_1_i/EnemyController_0/inst/enemies[23][is_active]_i_10/O - net (fo=2, routed) 0.250 2.023 design_1_i/EnemyController_0/inst/enemies[23][is_active]_i_10_n_0 - SLICE_X22Y24 LUT6 (Prop_G6LUT_SLICEL_I5_O) - 0.097 2.120 f design_1_i/EnemyController_0/inst/enemies[23][is_active]_i_3/O - net (fo=256, routed) 1.535 3.655 design_1_i/EnemyController_0/inst/enemies[23][is_active]_i_3_n_0 - SLICE_X36Y17 LUT6 (Prop_H6LUT_SLICEL_I2_O) - 0.036 3.691 r design_1_i/EnemyController_0/inst/enemies[9][R][9]_i_1/O - net (fo=9, routed) 0.254 3.945 design_1_i/EnemyController_0/inst/enemies[9][R] - SLICE_X37Y18 FDCE r design_1_i/EnemyController_0/inst/enemies_reg[9][R][5]/CE - ------------------------------------------------------------------- ------------------- - - - - - -Min Delay Paths --------------------------------------------------------------------------------------- -Slack: inf - Source: design_1_i/EnemyController_0/inst/lfsr_reg[15]/C - (rising edge-triggered cell FDPE) - Destination: design_1_i/EnemyController_0/inst/lfsr_reg[0]/D - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 0.088ns (logic 0.059ns (67.045%) route 0.029ns (32.955%)) - Logic Levels: 2 (FDPE=1 LUT4=1) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X38Y36 FDPE 0.000 0.000 r design_1_i/EnemyController_0/inst/lfsr_reg[15]/C - SLICE_X38Y36 FDPE (Prop_GFF_SLICEL_C_Q) - 0.039 0.039 r design_1_i/EnemyController_0/inst/lfsr_reg[15]/Q - net (fo=1, routed) 0.023 0.062 design_1_i/EnemyController_0/inst/lfsr_reg_n_0_[15] - SLICE_X38Y36 LUT4 (Prop_D5LUT_SLICEL_I2_O) - 0.020 0.082 r design_1_i/EnemyController_0/inst/lfsr[0]_i_1/O - net (fo=1, routed) 0.006 0.088 design_1_i/EnemyController_0/inst/p_0_out[0] - SLICE_X38Y36 FDPE r design_1_i/EnemyController_0/inst/lfsr_reg[0]/D - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: design_1_i/EnemyController_0/inst/lfsr_reg[8]/C - (rising edge-triggered cell FDCE) - Destination: design_1_i/EnemyController_0/inst/lfsr_reg[9]/D - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 0.094ns (logic 0.039ns (41.568%) route 0.055ns (58.432%)) - Logic Levels: 1 (FDCE=1) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X38Y36 FDCE 0.000 0.000 r design_1_i/EnemyController_0/inst/lfsr_reg[8]/C - SLICE_X38Y36 FDCE (Prop_BFF_SLICEL_C_Q) - 0.039 0.039 r design_1_i/EnemyController_0/inst/lfsr_reg[8]/Q - net (fo=2, routed) 0.055 0.094 design_1_i/EnemyController_0/inst/p_0_in[5] - SLICE_X38Y36 FDCE r design_1_i/EnemyController_0/inst/lfsr_reg[9]/D - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: design_1_i/EnemyController_0/inst/enemies_reg[14][R][4]/C - (rising edge-triggered cell FDCE) - Destination: design_1_i/EnemyController_0/inst/enemies_reg[14][R][4]/D - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 0.096ns (logic 0.054ns (56.436%) route 0.042ns (43.564%)) - Logic Levels: 2 (FDCE=1 LUT6=1) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X13Y22 FDCE 0.000 0.000 r design_1_i/EnemyController_0/inst/enemies_reg[14][R][4]/C - SLICE_X13Y22 FDCE (Prop_BFF_SLICEL_C_Q) - 0.039 0.039 r design_1_i/EnemyController_0/inst/enemies_reg[14][R][4]/Q - net (fo=19, routed) 0.027 0.066 design_1_i/EnemyController_0/inst/enemies_reg[14][R][9]_0[3] - SLICE_X13Y22 LUT6 (Prop_B6LUT_SLICEL_I0_O) - 0.015 0.081 r design_1_i/EnemyController_0/inst/enemies[14][R][4]_i_1/O - net (fo=1, routed) 0.015 0.096 design_1_i/EnemyController_0/inst/enemies[14][R][4]_i_1_n_0 - SLICE_X13Y22 FDCE r design_1_i/EnemyController_0/inst/enemies_reg[14][R][4]/D - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: design_1_i/EnemyController_0/inst/enemies_reg[5][R][6]/C - (rising edge-triggered cell FDCE) - Destination: design_1_i/EnemyController_0/inst/enemies_reg[5][R][6]/D - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 0.096ns (logic 0.054ns (56.436%) route 0.042ns (43.564%)) - Logic Levels: 2 (FDCE=1 LUT6=1) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X15Y16 FDCE 0.000 0.000 r design_1_i/EnemyController_0/inst/enemies_reg[5][R][6]/C - SLICE_X15Y16 FDCE (Prop_BFF_SLICEL_C_Q) - 0.039 0.039 r design_1_i/EnemyController_0/inst/enemies_reg[5][R][6]/Q - net (fo=7, routed) 0.027 0.066 design_1_i/EnemyController_0/inst/enemies_reg[5][R][9]_0[5] - SLICE_X15Y16 LUT6 (Prop_B6LUT_SLICEL_I0_O) - 0.015 0.081 r design_1_i/EnemyController_0/inst/enemies[5][R][6]_i_1/O - net (fo=1, routed) 0.015 0.096 design_1_i/EnemyController_0/inst/enemies[5][R][6]_i_1_n_0 - SLICE_X15Y16 FDCE r design_1_i/EnemyController_0/inst/enemies_reg[5][R][6]/D - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: design_1_i/EnemyController_0/inst/lfsr_reg[11]/C - (rising edge-triggered cell FDPE) - Destination: design_1_i/EnemyController_0/inst/lfsr_reg[12]/D - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 0.097ns (logic 0.039ns (40.206%) route 0.058ns (59.794%)) - Logic Levels: 1 (FDPE=1) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X38Y36 FDPE 0.000 0.000 r design_1_i/EnemyController_0/inst/lfsr_reg[11]/C - SLICE_X38Y36 FDPE (Prop_EFF_SLICEL_C_Q) - 0.039 0.039 r design_1_i/EnemyController_0/inst/lfsr_reg[11]/Q - net (fo=1, routed) 0.058 0.097 design_1_i/EnemyController_0/inst/lfsr_reg_n_0_[11] - SLICE_X38Y36 FDCE r design_1_i/EnemyController_0/inst/lfsr_reg[12]/D - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: design_1_i/EnemyController_0/inst/lfsr_reg[5]/C - (rising edge-triggered cell FDPE) - Destination: design_1_i/EnemyController_0/inst/lfsr_reg[6]/D - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 0.097ns (logic 0.039ns (40.206%) route 0.058ns (59.794%)) - Logic Levels: 1 (FDPE=1) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X35Y33 FDPE 0.000 0.000 r design_1_i/EnemyController_0/inst/lfsr_reg[5]/C - SLICE_X35Y33 FDPE (Prop_EFF_SLICEL_C_Q) - 0.039 0.039 r design_1_i/EnemyController_0/inst/lfsr_reg[5]/Q - net (fo=1, routed) 0.058 0.097 design_1_i/EnemyController_0/inst/p_0_in[2] - SLICE_X35Y33 FDPE r design_1_i/EnemyController_0/inst/lfsr_reg[6]/D - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: design_1_i/EnemyController_0/inst/enemies_reg[23][R][2]/C - (rising edge-triggered cell FDCE) - Destination: design_1_i/EnemyController_0/inst/enemies_reg[23][R][2]/D - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 0.098ns (logic 0.053ns (54.342%) route 0.045ns (45.658%)) - Logic Levels: 2 (FDCE=1 LUT6=1) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X35Y51 FDCE 0.000 0.000 r design_1_i/EnemyController_0/inst/enemies_reg[23][R][2]/C - SLICE_X35Y51 FDCE (Prop_DFF_SLICEL_C_Q) - 0.039 0.039 r design_1_i/EnemyController_0/inst/enemies_reg[23][R][2]/Q - net (fo=8, routed) 0.029 0.068 design_1_i/EnemyController_0/inst/enemies_reg[23][R][9]_0[1] - SLICE_X35Y51 LUT6 (Prop_D6LUT_SLICEL_I4_O) - 0.014 0.082 r design_1_i/EnemyController_0/inst/enemies[23][R][2]_i_1/O - net (fo=1, routed) 0.016 0.098 design_1_i/EnemyController_0/inst/enemies[23][R][2]_i_1_n_0 - SLICE_X35Y51 FDCE r design_1_i/EnemyController_0/inst/enemies_reg[23][R][2]/D - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: design_1_i/EnemyController_0/inst/enemies_reg[15][R][9]/C - (rising edge-triggered cell FDCE) - Destination: design_1_i/EnemyController_0/inst/enemies_reg[15][R][9]/D - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 0.098ns (logic 0.053ns (54.257%) route 0.045ns (45.743%)) - Logic Levels: 2 (FDCE=1 LUT6=1) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X12Y29 FDCE 0.000 0.000 r design_1_i/EnemyController_0/inst/enemies_reg[15][R][9]/C - SLICE_X12Y29 FDCE (Prop_CFF_SLICEL_C_Q) - 0.039 0.039 r design_1_i/EnemyController_0/inst/enemies_reg[15][R][9]/Q - net (fo=4, routed) 0.028 0.067 design_1_i/EnemyController_0/inst/enemies_reg[15][R][9]_0[8] - SLICE_X12Y29 LUT6 (Prop_C6LUT_SLICEL_I2_O) - 0.014 0.081 r design_1_i/EnemyController_0/inst/enemies[15][R][9]_i_2/O - net (fo=1, routed) 0.017 0.098 design_1_i/EnemyController_0/inst/enemies[15][R][9]_i_2_n_0 - SLICE_X12Y29 FDCE r design_1_i/EnemyController_0/inst/enemies_reg[15][R][9]/D - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: design_1_i/EnemyController_0/inst/enemies_reg[19][R][7]/C - (rising edge-triggered cell FDCE) - Destination: design_1_i/EnemyController_0/inst/enemies_reg[19][R][7]/D - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 0.098ns (logic 0.053ns (54.206%) route 0.045ns (45.794%)) - Logic Levels: 2 (FDCE=1 LUT6=1) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X15Y6 FDCE 0.000 0.000 r design_1_i/EnemyController_0/inst/enemies_reg[19][R][7]/C - SLICE_X15Y6 FDCE (Prop_DFF_SLICEL_C_Q) - 0.039 0.039 r design_1_i/EnemyController_0/inst/enemies_reg[19][R][7]/Q - net (fo=5, routed) 0.029 0.068 design_1_i/EnemyController_0/inst/enemies_reg[19][R][9]_0[6] - SLICE_X15Y6 LUT6 (Prop_D6LUT_SLICEL_I5_O) - 0.014 0.082 r design_1_i/EnemyController_0/inst/enemies[19][R][7]_i_1/O - net (fo=1, routed) 0.016 0.098 design_1_i/EnemyController_0/inst/enemies[19][R][7]_i_1_n_0 - SLICE_X15Y6 FDCE r design_1_i/EnemyController_0/inst/enemies_reg[19][R][7]/D - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: design_1_i/EnemyController_0/inst/enemies_reg[1][R][7]/C - (rising edge-triggered cell FDCE) - Destination: design_1_i/EnemyController_0/inst/enemies_reg[1][R][7]/D - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 0.098ns (logic 0.053ns (54.206%) route 0.045ns (45.794%)) - Logic Levels: 2 (FDCE=1 LUT6=1) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X35Y35 FDCE 0.000 0.000 r design_1_i/EnemyController_0/inst/enemies_reg[1][R][7]/C - SLICE_X35Y35 FDCE (Prop_DFF_SLICEL_C_Q) - 0.039 0.039 r design_1_i/EnemyController_0/inst/enemies_reg[1][R][7]/Q - net (fo=6, routed) 0.029 0.068 design_1_i/EnemyController_0/inst/enemies_reg[1][R][9]_0[6] - SLICE_X35Y35 LUT6 (Prop_D6LUT_SLICEL_I5_O) - 0.014 0.082 r design_1_i/EnemyController_0/inst/enemies[1][R][7]_i_1/O - net (fo=1, routed) 0.016 0.098 design_1_i/EnemyController_0/inst/enemies[1][R][7]_i_1_n_0 - SLICE_X35Y35 FDCE r design_1_i/EnemyController_0/inst/enemies_reg[1][R][7]/D - ------------------------------------------------------------------- ------------------- - - - - - --------------------------------------------------------------------------------------- -Path Group: (none) -From Clock: clk125_design_1_clk_wiz_0_0 - To Clock: - -Max Delay 8 Endpoints -Min Delay 8 Endpoints --------------------------------------------------------------------------------------- - - -Max Delay Paths --------------------------------------------------------------------------------------- -Slack: inf - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_ODDRE_P/CLK - (falling edge-triggered cell OSERDESE3 clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: HDMI_D2_P - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 3.607ns (logic 3.604ns (99.917%) route 0.003ns (0.083%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.144ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.108ns - Phase Error (PE): 0.085ns - Clock Net Delay (Source): 1.885ns (routing 1.034ns, distribution 0.851ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk125_design_1_clk_wiz_0_0 fall edge) - 4.000 4.000 f - D7 0.000 4.000 f clk_100mhz_clk_p (IN) - net (fo=0) 0.100 4.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.629 4.729 f design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 4.779 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 4.779 f design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.384 5.163 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - -0.127 5.036 f design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.250 5.286 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.028 5.314 f design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.885 7.199 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - HDIOLOGIC_M_X1Y1 OSERDESE3 f design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_ODDRE_P/CLK - ------------------------------------------------------------------- ------------------- - HDIOLOGIC_M_X1Y1 OSERDESE3 (Prop_OPTFF_HDIOLOGIC_M_CLK_OQ) - 0.818 8.017 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_ODDRE_P/OQ - net (fo=1, routed) 0.003 8.020 HDMI_D2_P_OBUF - AF11 OBUF (Prop_OUTBUF_HDIOB_M_I_O) - 2.786 10.806 r HDMI_D2_P_OBUF_inst/O - net (fo=0) 0.000 10.806 HDMI_D2_P - AF11 r HDMI_D2_P (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_ODDRE_P/CLK - (falling edge-triggered cell OSERDESE3 clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: HDMI_D1_P - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 3.618ns (logic 3.615ns (99.917%) route 0.003ns (0.083%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.144ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.108ns - Phase Error (PE): 0.085ns - Clock Net Delay (Source): 1.871ns (routing 1.034ns, distribution 0.837ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk125_design_1_clk_wiz_0_0 fall edge) - 4.000 4.000 f - D7 0.000 4.000 f clk_100mhz_clk_p (IN) - net (fo=0) 0.100 4.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.629 4.729 f design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 4.779 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 4.779 f design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.384 5.163 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - -0.127 5.036 f design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.250 5.286 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.028 5.314 f design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.871 7.185 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - HDIOLOGIC_S_X1Y2 OSERDESE3 f design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_ODDRE_P/CLK - ------------------------------------------------------------------- ------------------- - HDIOLOGIC_S_X1Y2 OSERDESE3 (Prop_OPTFF_HDIOLOGIC_S_CLK_OQ) - 0.819 8.004 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_ODDRE_P/OQ - net (fo=1, routed) 0.003 8.007 HDMI_D1_P_OBUF - AH11 OBUF (Prop_OUTBUF_HDIOB_S_I_O) - 2.796 10.803 r HDMI_D1_P_OBUF_inst/O - net (fo=0) 0.000 10.803 HDMI_D1_P - AH11 r HDMI_D1_P (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_ODDRE_N/CLK - (falling edge-triggered cell OSERDESE3 clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: HDMI_D1_N - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 3.617ns (logic 3.614ns (99.917%) route 0.003ns (0.083%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.144ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.108ns - Phase Error (PE): 0.085ns - Clock Net Delay (Source): 1.872ns (routing 1.034ns, distribution 0.838ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk125_design_1_clk_wiz_0_0 fall edge) - 4.000 4.000 f - D7 0.000 4.000 f clk_100mhz_clk_p (IN) - net (fo=0) 0.100 4.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.629 4.729 f design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 4.779 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 4.779 f design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.384 5.163 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - -0.127 5.036 f design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.250 5.286 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.028 5.314 f design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.872 7.186 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - HDIOLOGIC_M_X1Y2 OSERDESE3 f design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_ODDRE_N/CLK - ------------------------------------------------------------------- ------------------- - HDIOLOGIC_M_X1Y2 OSERDESE3 (Prop_OPTFF_HDIOLOGIC_M_CLK_OQ) - 0.818 8.004 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_ODDRE_N/OQ - net (fo=1, routed) 0.003 8.007 HDMI_D1_N_OBUF - AH12 OBUF (Prop_OUTBUF_HDIOB_M_I_O) - 2.796 10.803 r HDMI_D1_N_OBUF_inst/O - net (fo=0) 0.000 10.803 HDMI_D1_N - AH12 r HDMI_D1_N (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_ODDRE_N/CLK - (falling edge-triggered cell OSERDESE3 clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: HDMI_D2_N - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 3.607ns (logic 3.604ns (99.917%) route 0.003ns (0.083%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.144ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.108ns - Phase Error (PE): 0.085ns - Clock Net Delay (Source): 1.874ns (routing 1.034ns, distribution 0.840ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk125_design_1_clk_wiz_0_0 fall edge) - 4.000 4.000 f - D7 0.000 4.000 f clk_100mhz_clk_p (IN) - net (fo=0) 0.100 4.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.629 4.729 f design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 4.779 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 4.779 f design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.384 5.163 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - -0.127 5.036 f design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.250 5.286 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.028 5.314 f design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.874 7.188 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - HDIOLOGIC_S_X1Y1 OSERDESE3 f design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_ODDRE_N/CLK - ------------------------------------------------------------------- ------------------- - HDIOLOGIC_S_X1Y1 OSERDESE3 (Prop_OPTFF_HDIOLOGIC_S_CLK_OQ) - 0.819 8.007 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_ODDRE_N/OQ - net (fo=1, routed) 0.003 8.010 HDMI_D2_N_OBUF - AG11 OBUF (Prop_OUTBUF_HDIOB_S_I_O) - 2.785 10.796 r HDMI_D2_N_OBUF_inst/O - net (fo=0) 0.000 10.796 HDMI_D2_N - AG11 r HDMI_D2_N (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_ODDRE_N/CLK - (falling edge-triggered cell OSERDESE3 clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: HDMI_D0_N - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 3.609ns (logic 3.606ns (99.917%) route 0.003ns (0.083%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.144ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.108ns - Phase Error (PE): 0.085ns - Clock Net Delay (Source): 1.869ns (routing 1.034ns, distribution 0.835ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk125_design_1_clk_wiz_0_0 fall edge) - 4.000 4.000 f - D7 0.000 4.000 f clk_100mhz_clk_p (IN) - net (fo=0) 0.100 4.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.629 4.729 f design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 4.779 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 4.779 f design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.384 5.163 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - -0.127 5.036 f design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.250 5.286 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.028 5.314 f design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.869 7.183 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - HDIOLOGIC_M_X1Y3 OSERDESE3 f design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_ODDRE_N/CLK - ------------------------------------------------------------------- ------------------- - HDIOLOGIC_M_X1Y3 OSERDESE3 (Prop_OPTFF_HDIOLOGIC_M_CLK_OQ) - 0.818 8.001 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_ODDRE_N/OQ - net (fo=1, routed) 0.003 8.004 HDMI_D0_N_OBUF - AE10 OBUF (Prop_OUTBUF_HDIOB_M_I_O) - 2.788 10.793 r HDMI_D0_N_OBUF_inst/O - net (fo=0) 0.000 10.793 HDMI_D0_N - AE10 r HDMI_D0_N (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_ODDRE_P/CLK - (falling edge-triggered cell OSERDESE3 clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: HDMI_D0_P - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 3.610ns (logic 3.607ns (99.917%) route 0.003ns (0.083%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.144ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.108ns - Phase Error (PE): 0.085ns - Clock Net Delay (Source): 1.867ns (routing 1.034ns, distribution 0.833ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk125_design_1_clk_wiz_0_0 fall edge) - 4.000 4.000 f - D7 0.000 4.000 f clk_100mhz_clk_p (IN) - net (fo=0) 0.100 4.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.629 4.729 f design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 4.779 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 4.779 f design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.384 5.163 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - -0.127 5.036 f design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.250 5.286 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.028 5.314 f design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.867 7.181 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - HDIOLOGIC_S_X1Y3 OSERDESE3 f design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_ODDRE_P/CLK - ------------------------------------------------------------------- ------------------- - HDIOLOGIC_S_X1Y3 OSERDESE3 (Prop_OPTFF_HDIOLOGIC_S_CLK_OQ) - 0.819 8.000 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_ODDRE_P/OQ - net (fo=1, routed) 0.003 8.003 HDMI_D0_P_OBUF - AF10 OBUF (Prop_OUTBUF_HDIOB_S_I_O) - 2.788 10.792 r HDMI_D0_P_OBUF_inst/O - net (fo=0) 0.000 10.792 HDMI_D0_P - AF10 r HDMI_D0_P (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_3/i_ODDRE_N/CLK - (falling edge-triggered cell OSERDESE3 clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: HDMI_CK_N - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 3.603ns (logic 3.600ns (99.917%) route 0.003ns (0.083%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.144ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.108ns - Phase Error (PE): 0.085ns - Clock Net Delay (Source): 1.858ns (routing 1.034ns, distribution 0.824ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk125_design_1_clk_wiz_0_0 fall edge) - 4.000 4.000 f - D7 0.000 4.000 f clk_100mhz_clk_p (IN) - net (fo=0) 0.100 4.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.629 4.729 f design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 4.779 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 4.779 f design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.384 5.163 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - -0.127 5.036 f design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.250 5.286 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.028 5.314 f design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.858 7.172 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - HDIOLOGIC_M_X1Y5 OSERDESE3 f design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_3/i_ODDRE_N/CLK - ------------------------------------------------------------------- ------------------- - HDIOLOGIC_M_X1Y5 OSERDESE3 (Prop_OPTFF_HDIOLOGIC_M_CLK_OQ) - 0.818 7.990 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_3/i_ODDRE_N/OQ - net (fo=1, routed) 0.003 7.993 HDMI_CK_N_OBUF - AC12 OBUF (Prop_OUTBUF_HDIOB_M_I_O) - 2.782 10.775 r HDMI_CK_N_OBUF_inst/O - net (fo=0) 0.000 10.775 HDMI_CK_N - AC12 r HDMI_CK_N (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_3/i_ODDRE_P/CLK - (falling edge-triggered cell OSERDESE3 clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: HDMI_CK_P - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 3.604ns (logic 3.601ns (99.917%) route 0.003ns (0.083%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.144ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.108ns - Phase Error (PE): 0.085ns - Clock Net Delay (Source): 1.855ns (routing 1.034ns, distribution 0.821ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk125_design_1_clk_wiz_0_0 fall edge) - 4.000 4.000 f - D7 0.000 4.000 f clk_100mhz_clk_p (IN) - net (fo=0) 0.100 4.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.629 4.729 f design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 4.779 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 4.779 f design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.384 5.163 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - -0.127 5.036 f design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.250 5.286 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.028 5.314 f design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.855 7.169 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - HDIOLOGIC_S_X1Y5 OSERDESE3 f design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_3/i_ODDRE_P/CLK - ------------------------------------------------------------------- ------------------- - HDIOLOGIC_S_X1Y5 OSERDESE3 (Prop_OPTFF_HDIOLOGIC_S_CLK_OQ) - 0.819 7.988 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_3/i_ODDRE_P/OQ - net (fo=1, routed) 0.003 7.991 HDMI_CK_P_OBUF - AD12 OBUF (Prop_OUTBUF_HDIOB_S_I_O) - 2.782 10.774 r HDMI_CK_P_OBUF_inst/O - net (fo=0) 0.000 10.774 HDMI_CK_P - AD12 r HDMI_CK_P (OUT) - ------------------------------------------------------------------- ------------------- - - - - - -Min Delay Paths --------------------------------------------------------------------------------------- -Slack: inf - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_3/i_ODDRE_P/CLK - (rising edge-triggered cell OSERDESE3 clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: HDMI_CK_P - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 1.609ns (logic 1.607ns (99.876%) route 0.002ns (0.124%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.144ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.108ns - Phase Error (PE): 0.085ns - Clock Net Delay (Source): 1.034ns (routing 0.568ns, distribution 0.466ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.295 0.374 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.414 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.414 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.196 0.610 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - 0.230 0.840 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.149 0.989 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.017 1.006 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.034 2.040 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - HDIOLOGIC_S_X1Y5 OSERDESE3 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_3/i_ODDRE_P/CLK - ------------------------------------------------------------------- ------------------- - HDIOLOGIC_S_X1Y5 OSERDESE3 (Prop_OPTFF_HDIOLOGIC_S_CLK_OQ) - 0.168 2.208 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_3/i_ODDRE_P/OQ - net (fo=1, routed) 0.002 2.210 HDMI_CK_P_OBUF - AD12 OBUF (Prop_OUTBUF_HDIOB_S_I_O) - 1.439 3.649 r HDMI_CK_P_OBUF_inst/O - net (fo=0) 0.000 3.649 HDMI_CK_P - AD12 r HDMI_CK_P (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_3/i_ODDRE_N/CLK - (rising edge-triggered cell OSERDESE3 clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: HDMI_CK_N - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 1.615ns (logic 1.613ns (99.876%) route 0.002ns (0.124%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.144ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.108ns - Phase Error (PE): 0.085ns - Clock Net Delay (Source): 1.036ns (routing 0.568ns, distribution 0.468ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.295 0.374 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.414 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.414 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.196 0.610 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - 0.230 0.840 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.149 0.989 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.017 1.006 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.036 2.042 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - HDIOLOGIC_M_X1Y5 OSERDESE3 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_3/i_ODDRE_N/CLK - ------------------------------------------------------------------- ------------------- - HDIOLOGIC_M_X1Y5 OSERDESE3 (Prop_OPTFF_HDIOLOGIC_M_CLK_OQ) - 0.175 2.217 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_3/i_ODDRE_N/OQ - net (fo=1, routed) 0.002 2.219 HDMI_CK_N_OBUF - AC12 OBUF (Prop_OUTBUF_HDIOB_M_I_O) - 1.438 3.658 r HDMI_CK_N_OBUF_inst/O - net (fo=0) 0.000 3.658 HDMI_CK_N - AC12 r HDMI_CK_N (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_ODDRE_P/CLK - (rising edge-triggered cell OSERDESE3 clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: HDMI_D0_P - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 1.615ns (logic 1.613ns (99.876%) route 0.002ns (0.124%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.144ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.108ns - Phase Error (PE): 0.085ns - Clock Net Delay (Source): 1.040ns (routing 0.568ns, distribution 0.472ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.295 0.374 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.414 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.414 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.196 0.610 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - 0.230 0.840 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.149 0.989 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.017 1.006 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.040 2.046 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - HDIOLOGIC_S_X1Y3 OSERDESE3 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_ODDRE_P/CLK - ------------------------------------------------------------------- ------------------- - HDIOLOGIC_S_X1Y3 OSERDESE3 (Prop_OPTFF_HDIOLOGIC_S_CLK_OQ) - 0.168 2.214 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_ODDRE_P/OQ - net (fo=1, routed) 0.002 2.216 HDMI_D0_P_OBUF - AF10 OBUF (Prop_OUTBUF_HDIOB_S_I_O) - 1.445 3.661 r HDMI_D0_P_OBUF_inst/O - net (fo=0) 0.000 3.661 HDMI_D0_P - AF10 r HDMI_D0_P (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_ODDRE_N/CLK - (rising edge-triggered cell OSERDESE3 clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: HDMI_D2_N - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 1.612ns (logic 1.610ns (99.876%) route 0.002ns (0.124%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.144ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.108ns - Phase Error (PE): 0.085ns - Clock Net Delay (Source): 1.044ns (routing 0.568ns, distribution 0.476ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.295 0.374 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.414 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.414 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.196 0.610 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - 0.230 0.840 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.149 0.989 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.017 1.006 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.044 2.050 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - HDIOLOGIC_S_X1Y1 OSERDESE3 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_ODDRE_N/CLK - ------------------------------------------------------------------- ------------------- - HDIOLOGIC_S_X1Y1 OSERDESE3 (Prop_OPTFF_HDIOLOGIC_S_CLK_OQ) - 0.168 2.218 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_ODDRE_N/OQ - net (fo=1, routed) 0.002 2.220 HDMI_D2_N_OBUF - AG11 OBUF (Prop_OUTBUF_HDIOB_S_I_O) - 1.442 3.662 r HDMI_D2_N_OBUF_inst/O - net (fo=0) 0.000 3.662 HDMI_D2_N - AG11 r HDMI_D2_N (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_ODDRE_N/CLK - (rising edge-triggered cell OSERDESE3 clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: HDMI_D0_N - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 1.622ns (logic 1.620ns (99.877%) route 0.002ns (0.123%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.144ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.108ns - Phase Error (PE): 0.085ns - Clock Net Delay (Source): 1.041ns (routing 0.568ns, distribution 0.473ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.295 0.374 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.414 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.414 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.196 0.610 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - 0.230 0.840 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.149 0.989 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.017 1.006 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.041 2.047 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - HDIOLOGIC_M_X1Y3 OSERDESE3 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_ODDRE_N/CLK - ------------------------------------------------------------------- ------------------- - HDIOLOGIC_M_X1Y3 OSERDESE3 (Prop_OPTFF_HDIOLOGIC_M_CLK_OQ) - 0.175 2.222 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_0/i_ODDRE_N/OQ - net (fo=1, routed) 0.002 2.224 HDMI_D0_N_OBUF - AE10 OBUF (Prop_OUTBUF_HDIOB_M_I_O) - 1.445 3.669 r HDMI_D0_N_OBUF_inst/O - net (fo=0) 0.000 3.669 HDMI_D0_N - AE10 r HDMI_D0_N (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_ODDRE_P/CLK - (rising edge-triggered cell OSERDESE3 clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: HDMI_D1_P - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 1.622ns (logic 1.620ns (99.877%) route 0.002ns (0.123%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.144ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.108ns - Phase Error (PE): 0.085ns - Clock Net Delay (Source): 1.042ns (routing 0.568ns, distribution 0.474ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.295 0.374 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.414 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.414 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.196 0.610 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - 0.230 0.840 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.149 0.989 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.017 1.006 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.042 2.048 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - HDIOLOGIC_S_X1Y2 OSERDESE3 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_ODDRE_P/CLK - ------------------------------------------------------------------- ------------------- - HDIOLOGIC_S_X1Y2 OSERDESE3 (Prop_OPTFF_HDIOLOGIC_S_CLK_OQ) - 0.168 2.216 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_ODDRE_P/OQ - net (fo=1, routed) 0.002 2.218 HDMI_D1_P_OBUF - AH11 OBUF (Prop_OUTBUF_HDIOB_S_I_O) - 1.452 3.671 r HDMI_D1_P_OBUF_inst/O - net (fo=0) 0.000 3.671 HDMI_D1_P - AH11 r HDMI_D1_P (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_ODDRE_P/CLK - (rising edge-triggered cell OSERDESE3 clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: HDMI_D2_P - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 1.619ns (logic 1.617ns (99.876%) route 0.002ns (0.124%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.144ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.108ns - Phase Error (PE): 0.085ns - Clock Net Delay (Source): 1.048ns (routing 0.568ns, distribution 0.480ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.295 0.374 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.414 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.414 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.196 0.610 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - 0.230 0.840 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.149 0.989 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.017 1.006 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.048 2.054 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - HDIOLOGIC_M_X1Y1 OSERDESE3 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_ODDRE_P/CLK - ------------------------------------------------------------------- ------------------- - HDIOLOGIC_M_X1Y1 OSERDESE3 (Prop_OPTFF_HDIOLOGIC_M_CLK_OQ) - 0.175 2.229 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_ODDRE_P/OQ - net (fo=1, routed) 0.002 2.231 HDMI_D2_P_OBUF - AF11 OBUF (Prop_OUTBUF_HDIOB_M_I_O) - 1.442 3.673 r HDMI_D2_P_OBUF_inst/O - net (fo=0) 0.000 3.673 HDMI_D2_P - AF11 r HDMI_D2_P (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_ODDRE_N/CLK - (rising edge-triggered cell OSERDESE3 clocked by clk125_design_1_clk_wiz_0_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: HDMI_D1_N - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 1.629ns (logic 1.627ns (99.877%) route 0.002ns (0.123%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.144ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.108ns - Phase Error (PE): 0.085ns - Clock Net Delay (Source): 1.043ns (routing 0.568ns, distribution 0.475ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk125_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.295 0.374 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.414 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.414 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.196 0.610 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1) - 0.230 0.840 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 - net (fo=1, routed) 0.149 0.989 design_1_i/clk_wiz_0/inst/clk125_design_1_clk_wiz_0_0 - BUFGCE_X0Y54 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.017 1.006 r design_1_i/clk_wiz_0/inst/clkout2_buf/O - X1Y0 (CLOCK_ROOT) net (fo=53, routed) 1.043 2.049 design_1_i/HDMI_TX_0/U0/i_wrap/pxClkX5 - HDIOLOGIC_M_X1Y2 OSERDESE3 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_ODDRE_N/CLK - ------------------------------------------------------------------- ------------------- - HDIOLOGIC_M_X1Y2 OSERDESE3 (Prop_OPTFF_HDIOLOGIC_M_CLK_OQ) - 0.175 2.224 r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_1/i_ODDRE_N/OQ - net (fo=1, routed) 0.002 2.226 HDMI_D1_N_OBUF - AH12 OBUF (Prop_OUTBUF_HDIOB_M_I_O) - 1.452 3.678 r HDMI_D1_N_OBUF_inst/O - net (fo=0) 0.000 3.678 HDMI_D1_N - AH12 r HDMI_D1_N (OUT) - ------------------------------------------------------------------- ------------------- - - - - - --------------------------------------------------------------------------------------- -Path Group: (none) -From Clock: clk25_design_1_clk_wiz_0_0 - To Clock: - -Max Delay 260 Endpoints -Min Delay 260 Endpoints --------------------------------------------------------------------------------------- - - -Max Delay Paths --------------------------------------------------------------------------------------- -Slack: inf - Source: design_1_i/VideoTiming_0/inst/VSync_reg/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/EnemyController_0/inst/enemies_reg[23][R][7]/CE - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 2.574ns (logic 0.180ns (6.993%) route 2.394ns (93.007%)) - Logic Levels: 1 (LUT6=1) - Clock Uncertainty: 0.163ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.085ns - Clock Net Delay (Source): 2.048ns (routing 1.172ns, distribution 0.876ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.629 0.729 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.779 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.779 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.384 1.163 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - -0.127 1.036 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.244 1.280 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.028 1.308 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 2.048 3.356 design_1_i/VideoTiming_0/inst/pixClk - SLICE_X32Y22 FDRE r design_1_i/VideoTiming_0/inst/VSync_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X32Y22 FDRE (Prop_DFF_SLICEL_C_Q) - 0.079 3.435 r design_1_i/VideoTiming_0/inst/VSync_reg/Q - net (fo=67, routed) 1.587 5.022 design_1_i/EnemyController_0/inst/FrameTick - SLICE_X34Y51 LUT6 (Prop_H6LUT_SLICEM_I0_O) - 0.101 5.123 r design_1_i/EnemyController_0/inst/enemies[23][R][9]_i_1/O - net (fo=9, routed) 0.807 5.930 design_1_i/EnemyController_0/inst/enemies[23][R] - SLICE_X36Y53 FDCE r design_1_i/EnemyController_0/inst/enemies_reg[23][R][7]/CE - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: design_1_i/GameController_0/inst/health_reg_reg[1]/C - (rising edge-triggered cell FDPE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: PL_USER_LED[1] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 2.192ns (logic 0.861ns (39.267%) route 1.331ns (60.733%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.163ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.085ns - Clock Net Delay (Source): 2.144ns (routing 1.172ns, distribution 0.972ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.629 0.729 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.779 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.779 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.384 1.163 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - -0.127 1.036 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.244 1.280 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.028 1.308 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 2.144 3.452 design_1_i/GameController_0/inst/Clk - SLICE_X48Y31 FDPE r design_1_i/GameController_0/inst/health_reg_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X48Y31 FDPE (Prop_DFF2_SLICEM_C_Q) - 0.080 3.532 r design_1_i/GameController_0/inst/health_reg_reg[1]/Q - net (fo=4, routed) 1.331 4.863 PL_USER_LED_OBUF[1] - AE7 OBUF (Prop_OUTBUF_HPIOB_S_I_O) - 0.781 5.644 r PL_USER_LED_OBUF[1]_inst/O - net (fo=0) 0.000 5.644 PL_USER_LED[1] - AE7 r PL_USER_LED[1] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: design_1_i/GameController_0/inst/health_reg_reg[2]/C - (rising edge-triggered cell FDCE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: PL_USER_LED[2] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 2.131ns (logic 0.904ns (42.429%) route 1.227ns (57.571%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.163ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.085ns - Clock Net Delay (Source): 2.144ns (routing 1.172ns, distribution 0.972ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.629 0.729 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.779 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.779 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.384 1.163 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - -0.127 1.036 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.244 1.280 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.028 1.308 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 2.144 3.452 design_1_i/GameController_0/inst/Clk - SLICE_X48Y31 FDCE r design_1_i/GameController_0/inst/health_reg_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X48Y31 FDCE (Prop_CFF2_SLICEM_C_Q) - 0.077 3.529 r design_1_i/GameController_0/inst/health_reg_reg[2]/Q - net (fo=4, routed) 1.227 4.756 PL_USER_LED_OBUF[2] - AH2 OBUF (Prop_OUTBUF_HPIOB_M_I_O) - 0.827 5.584 r PL_USER_LED_OBUF[2]_inst/O - net (fo=0) 0.000 5.584 PL_USER_LED[2] - AH2 r PL_USER_LED[2] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: design_1_i/VideoTiming_0/inst/VSync_reg/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/EnemyController_0/inst/enemies_reg[7][R][5]/CE - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 2.189ns (logic 0.204ns (9.318%) route 1.985ns (90.682%)) - Logic Levels: 1 (LUT6=1) - Clock Uncertainty: 0.163ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.085ns - Clock Net Delay (Source): 2.048ns (routing 1.172ns, distribution 0.876ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.629 0.729 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.779 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.779 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.384 1.163 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - -0.127 1.036 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.244 1.280 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.028 1.308 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 2.048 3.356 design_1_i/VideoTiming_0/inst/pixClk - SLICE_X32Y22 FDRE r design_1_i/VideoTiming_0/inst/VSync_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X32Y22 FDRE (Prop_DFF_SLICEL_C_Q) - 0.079 3.435 r design_1_i/VideoTiming_0/inst/VSync_reg/Q - net (fo=67, routed) 1.300 4.735 design_1_i/EnemyController_0/inst/FrameTick - SLICE_X16Y8 LUT6 (Prop_H6LUT_SLICEM_I0_O) - 0.125 4.860 r design_1_i/EnemyController_0/inst/enemies[7][R][9]_i_1/O - net (fo=9, routed) 0.686 5.546 design_1_i/EnemyController_0/inst/enemies[7][R] - SLICE_X17Y3 FDCE r design_1_i/EnemyController_0/inst/enemies_reg[7][R][5]/CE - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: design_1_i/VideoTiming_0/inst/VSync_reg/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/EnemyController_0/inst/enemies_reg[7][R][6]/CE - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 2.189ns (logic 0.204ns (9.318%) route 1.985ns (90.682%)) - Logic Levels: 1 (LUT6=1) - Clock Uncertainty: 0.163ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.085ns - Clock Net Delay (Source): 2.048ns (routing 1.172ns, distribution 0.876ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.629 0.729 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.779 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.779 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.384 1.163 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - -0.127 1.036 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.244 1.280 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.028 1.308 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 2.048 3.356 design_1_i/VideoTiming_0/inst/pixClk - SLICE_X32Y22 FDRE r design_1_i/VideoTiming_0/inst/VSync_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X32Y22 FDRE (Prop_DFF_SLICEL_C_Q) - 0.079 3.435 r design_1_i/VideoTiming_0/inst/VSync_reg/Q - net (fo=67, routed) 1.300 4.735 design_1_i/EnemyController_0/inst/FrameTick - SLICE_X16Y8 LUT6 (Prop_H6LUT_SLICEM_I0_O) - 0.125 4.860 r design_1_i/EnemyController_0/inst/enemies[7][R][9]_i_1/O - net (fo=9, routed) 0.686 5.546 design_1_i/EnemyController_0/inst/enemies[7][R] - SLICE_X17Y3 FDCE r design_1_i/EnemyController_0/inst/enemies_reg[7][R][6]/CE - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: design_1_i/VideoTiming_0/inst/VSync_reg/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/EnemyController_0/inst/enemies_reg[23][R][5]/CE - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 2.114ns (logic 0.180ns (8.515%) route 1.934ns (91.485%)) - Logic Levels: 1 (LUT6=1) - Clock Uncertainty: 0.163ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.085ns - Clock Net Delay (Source): 2.048ns (routing 1.172ns, distribution 0.876ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.629 0.729 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.779 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.779 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.384 1.163 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - -0.127 1.036 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.244 1.280 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.028 1.308 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 2.048 3.356 design_1_i/VideoTiming_0/inst/pixClk - SLICE_X32Y22 FDRE r design_1_i/VideoTiming_0/inst/VSync_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X32Y22 FDRE (Prop_DFF_SLICEL_C_Q) - 0.079 3.435 r design_1_i/VideoTiming_0/inst/VSync_reg/Q - net (fo=67, routed) 1.587 5.022 design_1_i/EnemyController_0/inst/FrameTick - SLICE_X34Y51 LUT6 (Prop_H6LUT_SLICEM_I0_O) - 0.101 5.123 r design_1_i/EnemyController_0/inst/enemies[23][R][9]_i_1/O - net (fo=9, routed) 0.347 5.470 design_1_i/EnemyController_0/inst/enemies[23][R] - SLICE_X36Y53 FDCE r design_1_i/EnemyController_0/inst/enemies_reg[23][R][5]/CE - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: design_1_i/VideoTiming_0/inst/VSync_reg/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/EnemyController_0/inst/enemies_reg[23][R][6]/CE - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 2.114ns (logic 0.180ns (8.515%) route 1.934ns (91.485%)) - Logic Levels: 1 (LUT6=1) - Clock Uncertainty: 0.163ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.085ns - Clock Net Delay (Source): 2.048ns (routing 1.172ns, distribution 0.876ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.629 0.729 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.779 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.779 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.384 1.163 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - -0.127 1.036 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.244 1.280 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.028 1.308 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 2.048 3.356 design_1_i/VideoTiming_0/inst/pixClk - SLICE_X32Y22 FDRE r design_1_i/VideoTiming_0/inst/VSync_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X32Y22 FDRE (Prop_DFF_SLICEL_C_Q) - 0.079 3.435 r design_1_i/VideoTiming_0/inst/VSync_reg/Q - net (fo=67, routed) 1.587 5.022 design_1_i/EnemyController_0/inst/FrameTick - SLICE_X34Y51 LUT6 (Prop_H6LUT_SLICEM_I0_O) - 0.101 5.123 r design_1_i/EnemyController_0/inst/enemies[23][R][9]_i_1/O - net (fo=9, routed) 0.347 5.470 design_1_i/EnemyController_0/inst/enemies[23][R] - SLICE_X36Y53 FDCE r design_1_i/EnemyController_0/inst/enemies_reg[23][R][6]/CE - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: design_1_i/GameController_0/inst/health_reg_reg[0]/C - (rising edge-triggered cell FDPE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: PL_USER_LED[0] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 1.953ns (logic 0.868ns (44.472%) route 1.084ns (55.528%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.163ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.085ns - Clock Net Delay (Source): 2.144ns (routing 1.172ns, distribution 0.972ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.629 0.729 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.779 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.779 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.384 1.163 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - -0.127 1.036 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.244 1.280 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.028 1.308 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 2.144 3.452 design_1_i/GameController_0/inst/Clk - SLICE_X48Y31 FDPE r design_1_i/GameController_0/inst/health_reg_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X48Y31 FDPE (Prop_DFF_SLICEM_C_Q) - 0.078 3.530 r design_1_i/GameController_0/inst/health_reg_reg[0]/Q - net (fo=4, routed) 1.084 4.615 PL_USER_LED_OBUF[0] - AF5 OBUF (Prop_OUTBUF_HPIOB_S_I_O) - 0.790 5.405 r PL_USER_LED_OBUF[0]_inst/O - net (fo=0) 0.000 5.405 PL_USER_LED[0] - AF5 r PL_USER_LED[0] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: design_1_i/VideoTiming_0/inst/VSync_reg/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/EnemyController_0/inst/enemies_reg[23][R][1]/CE - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 1.981ns (logic 0.180ns (9.086%) route 1.801ns (90.914%)) - Logic Levels: 1 (LUT6=1) - Clock Uncertainty: 0.163ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.085ns - Clock Net Delay (Source): 2.048ns (routing 1.172ns, distribution 0.876ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.629 0.729 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.779 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.779 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.384 1.163 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - -0.127 1.036 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.244 1.280 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.028 1.308 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 2.048 3.356 design_1_i/VideoTiming_0/inst/pixClk - SLICE_X32Y22 FDRE r design_1_i/VideoTiming_0/inst/VSync_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X32Y22 FDRE (Prop_DFF_SLICEL_C_Q) - 0.079 3.435 r design_1_i/VideoTiming_0/inst/VSync_reg/Q - net (fo=67, routed) 1.587 5.022 design_1_i/EnemyController_0/inst/FrameTick - SLICE_X34Y51 LUT6 (Prop_H6LUT_SLICEM_I0_O) - 0.101 5.123 r design_1_i/EnemyController_0/inst/enemies[23][R][9]_i_1/O - net (fo=9, routed) 0.214 5.337 design_1_i/EnemyController_0/inst/enemies[23][R] - SLICE_X34Y51 FDCE r design_1_i/EnemyController_0/inst/enemies_reg[23][R][1]/CE - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: design_1_i/VideoTiming_0/inst/VSync_reg/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/EnemyController_0/inst/enemies_reg[23][R][2]/CE - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 1.976ns (logic 0.180ns (9.109%) route 1.796ns (90.891%)) - Logic Levels: 1 (LUT6=1) - Clock Uncertainty: 0.163ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.085ns - Clock Net Delay (Source): 2.048ns (routing 1.172ns, distribution 0.876ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.629 0.729 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.779 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.779 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.384 1.163 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - -0.127 1.036 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.244 1.280 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.028 1.308 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 2.048 3.356 design_1_i/VideoTiming_0/inst/pixClk - SLICE_X32Y22 FDRE r design_1_i/VideoTiming_0/inst/VSync_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X32Y22 FDRE (Prop_DFF_SLICEL_C_Q) - 0.079 3.435 r design_1_i/VideoTiming_0/inst/VSync_reg/Q - net (fo=67, routed) 1.587 5.022 design_1_i/EnemyController_0/inst/FrameTick - SLICE_X34Y51 LUT6 (Prop_H6LUT_SLICEM_I0_O) - 0.101 5.123 r design_1_i/EnemyController_0/inst/enemies[23][R][9]_i_1/O - net (fo=9, routed) 0.209 5.332 design_1_i/EnemyController_0/inst/enemies[23][R] - SLICE_X35Y51 FDCE r design_1_i/EnemyController_0/inst/enemies_reg[23][R][2]/CE - ------------------------------------------------------------------- ------------------- - - - - - -Min Delay Paths --------------------------------------------------------------------------------------- -Slack: inf - Source: design_1_i/VideoTiming_0/inst/VSync_reg/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/EnemyController_0/inst/enemies_reg[11][is_active]/D - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 0.248ns (logic 0.080ns (32.268%) route 0.168ns (67.731%)) - Logic Levels: 1 (LUT6=1) - Clock Uncertainty: 0.163ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.085ns - Clock Net Delay (Source): 1.130ns (routing 0.640ns, distribution 0.490ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.295 0.374 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.414 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.414 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.196 0.610 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - 0.230 0.840 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.145 0.985 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.017 1.002 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.130 2.132 design_1_i/VideoTiming_0/inst/pixClk - SLICE_X32Y22 FDRE r design_1_i/VideoTiming_0/inst/VSync_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X32Y22 FDRE (Prop_DFF_SLICEL_C_Q) - 0.039 2.171 r design_1_i/VideoTiming_0/inst/VSync_reg/Q - net (fo=67, routed) 0.148 2.319 design_1_i/EnemyController_0/inst/FrameTick - SLICE_X28Y24 LUT6 (Prop_H6LUT_SLICEM_I0_O) - 0.041 2.360 r design_1_i/EnemyController_0/inst/enemies[11][is_active]_i_1/O - net (fo=1, routed) 0.020 2.380 design_1_i/EnemyController_0/inst/enemies[11][is_active]_i_1_n_0 - SLICE_X28Y24 FDCE r design_1_i/EnemyController_0/inst/enemies_reg[11][is_active]/D - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: design_1_i/VideoTiming_0/inst/VSync_reg/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/EnemyController_0/inst/enemies_reg[8][is_active]/D - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 0.251ns (logic 0.062ns (24.706%) route 0.189ns (75.294%)) - Logic Levels: 1 (LUT6=1) - Clock Uncertainty: 0.163ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.085ns - Clock Net Delay (Source): 1.130ns (routing 0.640ns, distribution 0.490ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.295 0.374 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.414 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.414 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.196 0.610 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - 0.230 0.840 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.145 0.985 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.017 1.002 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.130 2.132 design_1_i/VideoTiming_0/inst/pixClk - SLICE_X32Y22 FDRE r design_1_i/VideoTiming_0/inst/VSync_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X32Y22 FDRE (Prop_DFF_SLICEL_C_Q) - 0.039 2.171 r design_1_i/VideoTiming_0/inst/VSync_reg/Q - net (fo=67, routed) 0.169 2.340 design_1_i/EnemyController_0/inst/FrameTick - SLICE_X28Y23 LUT6 (Prop_H6LUT_SLICEM_I0_O) - 0.023 2.363 r design_1_i/EnemyController_0/inst/enemies[8][is_active]_i_1/O - net (fo=1, routed) 0.020 2.383 design_1_i/EnemyController_0/inst/enemies[8][is_active]_i_1_n_0 - SLICE_X28Y23 FDCE r design_1_i/EnemyController_0/inst/enemies_reg[8][is_active]/D - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: design_1_i/VideoTiming_0/inst/VSync_reg/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/EnemyController_0/inst/enemies_reg[18][is_active]/D - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 0.301ns (logic 0.074ns (24.554%) route 0.227ns (75.446%)) - Logic Levels: 1 (LUT6=1) - Clock Uncertainty: 0.163ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.085ns - Clock Net Delay (Source): 1.130ns (routing 0.640ns, distribution 0.490ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.295 0.374 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.414 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.414 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.196 0.610 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - 0.230 0.840 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.145 0.985 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.017 1.002 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.130 2.132 design_1_i/VideoTiming_0/inst/pixClk - SLICE_X32Y22 FDRE r design_1_i/VideoTiming_0/inst/VSync_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X32Y22 FDRE (Prop_DFF_SLICEL_C_Q) - 0.039 2.171 r design_1_i/VideoTiming_0/inst/VSync_reg/Q - net (fo=67, routed) 0.212 2.383 design_1_i/EnemyController_0/inst/FrameTick - SLICE_X23Y24 LUT6 (Prop_H6LUT_SLICEL_I0_O) - 0.035 2.418 r design_1_i/EnemyController_0/inst/enemies[18][is_active]_i_1/O - net (fo=1, routed) 0.015 2.433 design_1_i/EnemyController_0/inst/enemies[18][is_active]_i_1_n_0 - SLICE_X23Y24 FDCE r design_1_i/EnemyController_0/inst/enemies_reg[18][is_active]/D - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: design_1_i/VideoTiming_0/inst/VSync_reg/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/EnemyController_0/inst/enemies_reg[8][R][1]/CE - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 0.309ns (logic 0.079ns (25.599%) route 0.230ns (74.401%)) - Logic Levels: 1 (LUT6=1) - Clock Uncertainty: 0.163ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.085ns - Clock Net Delay (Source): 1.130ns (routing 0.640ns, distribution 0.490ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.295 0.374 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.414 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.414 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.196 0.610 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - 0.230 0.840 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.145 0.985 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.017 1.002 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.130 2.132 design_1_i/VideoTiming_0/inst/pixClk - SLICE_X32Y22 FDRE r design_1_i/VideoTiming_0/inst/VSync_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X32Y22 FDRE (Prop_DFF_SLICEL_C_Q) - 0.039 2.171 r design_1_i/VideoTiming_0/inst/VSync_reg/Q - net (fo=67, routed) 0.146 2.317 design_1_i/EnemyController_0/inst/FrameTick - SLICE_X28Y24 LUT6 (Prop_G6LUT_SLICEM_I0_O) - 0.040 2.357 r design_1_i/EnemyController_0/inst/enemies[8][R][9]_i_1/O - net (fo=9, routed) 0.084 2.441 design_1_i/EnemyController_0/inst/enemies[8][R] - SLICE_X27Y24 FDCE r design_1_i/EnemyController_0/inst/enemies_reg[8][R][1]/CE - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: design_1_i/VideoTiming_0/inst/VSync_reg/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/EnemyController_0/inst/enemies_reg[8][R][2]/CE - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 0.309ns (logic 0.079ns (25.599%) route 0.230ns (74.401%)) - Logic Levels: 1 (LUT6=1) - Clock Uncertainty: 0.163ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.085ns - Clock Net Delay (Source): 1.130ns (routing 0.640ns, distribution 0.490ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.295 0.374 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.414 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.414 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.196 0.610 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - 0.230 0.840 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.145 0.985 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.017 1.002 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.130 2.132 design_1_i/VideoTiming_0/inst/pixClk - SLICE_X32Y22 FDRE r design_1_i/VideoTiming_0/inst/VSync_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X32Y22 FDRE (Prop_DFF_SLICEL_C_Q) - 0.039 2.171 r design_1_i/VideoTiming_0/inst/VSync_reg/Q - net (fo=67, routed) 0.146 2.317 design_1_i/EnemyController_0/inst/FrameTick - SLICE_X28Y24 LUT6 (Prop_G6LUT_SLICEM_I0_O) - 0.040 2.357 r design_1_i/EnemyController_0/inst/enemies[8][R][9]_i_1/O - net (fo=9, routed) 0.084 2.441 design_1_i/EnemyController_0/inst/enemies[8][R] - SLICE_X27Y24 FDCE r design_1_i/EnemyController_0/inst/enemies_reg[8][R][2]/CE - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: design_1_i/VideoTiming_0/inst/VSync_reg/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/EnemyController_0/inst/enemies_reg[8][R][3]/CE - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 0.321ns (logic 0.079ns (24.638%) route 0.242ns (75.362%)) - Logic Levels: 1 (LUT6=1) - Clock Uncertainty: 0.163ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.085ns - Clock Net Delay (Source): 1.130ns (routing 0.640ns, distribution 0.490ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.295 0.374 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.414 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.414 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.196 0.610 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - 0.230 0.840 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.145 0.985 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.017 1.002 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.130 2.132 design_1_i/VideoTiming_0/inst/pixClk - SLICE_X32Y22 FDRE r design_1_i/VideoTiming_0/inst/VSync_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X32Y22 FDRE (Prop_DFF_SLICEL_C_Q) - 0.039 2.171 r design_1_i/VideoTiming_0/inst/VSync_reg/Q - net (fo=67, routed) 0.146 2.317 design_1_i/EnemyController_0/inst/FrameTick - SLICE_X28Y24 LUT6 (Prop_G6LUT_SLICEM_I0_O) - 0.040 2.357 r design_1_i/EnemyController_0/inst/enemies[8][R][9]_i_1/O - net (fo=9, routed) 0.096 2.453 design_1_i/EnemyController_0/inst/enemies[8][R] - SLICE_X29Y24 FDCE r design_1_i/EnemyController_0/inst/enemies_reg[8][R][3]/CE - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: design_1_i/VideoTiming_0/inst/VSync_reg/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/EnemyController_0/inst/enemies_reg[8][R][4]/CE - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 0.321ns (logic 0.079ns (24.638%) route 0.242ns (75.362%)) - Logic Levels: 1 (LUT6=1) - Clock Uncertainty: 0.163ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.085ns - Clock Net Delay (Source): 1.130ns (routing 0.640ns, distribution 0.490ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.295 0.374 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.414 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.414 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.196 0.610 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - 0.230 0.840 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.145 0.985 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.017 1.002 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.130 2.132 design_1_i/VideoTiming_0/inst/pixClk - SLICE_X32Y22 FDRE r design_1_i/VideoTiming_0/inst/VSync_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X32Y22 FDRE (Prop_DFF_SLICEL_C_Q) - 0.039 2.171 r design_1_i/VideoTiming_0/inst/VSync_reg/Q - net (fo=67, routed) 0.146 2.317 design_1_i/EnemyController_0/inst/FrameTick - SLICE_X28Y24 LUT6 (Prop_G6LUT_SLICEM_I0_O) - 0.040 2.357 r design_1_i/EnemyController_0/inst/enemies[8][R][9]_i_1/O - net (fo=9, routed) 0.096 2.453 design_1_i/EnemyController_0/inst/enemies[8][R] - SLICE_X29Y24 FDCE r design_1_i/EnemyController_0/inst/enemies_reg[8][R][4]/CE - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: design_1_i/VideoTiming_0/inst/VSync_reg/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/EnemyController_0/inst/enemies_reg[3][is_active]/D - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 0.323ns (logic 0.080ns (24.795%) route 0.243ns (75.205%)) - Logic Levels: 1 (LUT6=1) - Clock Uncertainty: 0.163ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.085ns - Clock Net Delay (Source): 1.130ns (routing 0.640ns, distribution 0.490ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.295 0.374 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.414 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.414 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.196 0.610 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - 0.230 0.840 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.145 0.985 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.017 1.002 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.130 2.132 design_1_i/VideoTiming_0/inst/pixClk - SLICE_X32Y22 FDRE r design_1_i/VideoTiming_0/inst/VSync_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X32Y22 FDRE (Prop_DFF_SLICEL_C_Q) - 0.039 2.171 r design_1_i/VideoTiming_0/inst/VSync_reg/Q - net (fo=67, routed) 0.223 2.394 design_1_i/EnemyController_0/inst/FrameTick - SLICE_X29Y33 LUT6 (Prop_H6LUT_SLICEM_I0_O) - 0.041 2.435 r design_1_i/EnemyController_0/inst/enemies[3][is_active]_i_1/O - net (fo=1, routed) 0.020 2.455 design_1_i/EnemyController_0/inst/enemies[3][is_active]_i_1_n_0 - SLICE_X29Y33 FDCE r design_1_i/EnemyController_0/inst/enemies_reg[3][is_active]/D - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: design_1_i/VideoTiming_0/inst/VSync_reg/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/EnemyController_0/inst/enemies_reg[8][R][5]/CE - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 0.324ns (logic 0.079ns (24.410%) route 0.245ns (75.590%)) - Logic Levels: 1 (LUT6=1) - Clock Uncertainty: 0.163ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.085ns - Clock Net Delay (Source): 1.130ns (routing 0.640ns, distribution 0.490ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.295 0.374 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.414 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.414 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.196 0.610 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - 0.230 0.840 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.145 0.985 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.017 1.002 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.130 2.132 design_1_i/VideoTiming_0/inst/pixClk - SLICE_X32Y22 FDRE r design_1_i/VideoTiming_0/inst/VSync_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X32Y22 FDRE (Prop_DFF_SLICEL_C_Q) - 0.039 2.171 r design_1_i/VideoTiming_0/inst/VSync_reg/Q - net (fo=67, routed) 0.146 2.317 design_1_i/EnemyController_0/inst/FrameTick - SLICE_X28Y24 LUT6 (Prop_G6LUT_SLICEM_I0_O) - 0.040 2.357 r design_1_i/EnemyController_0/inst/enemies[8][R][9]_i_1/O - net (fo=9, routed) 0.099 2.456 design_1_i/EnemyController_0/inst/enemies[8][R] - SLICE_X29Y24 FDCE r design_1_i/EnemyController_0/inst/enemies_reg[8][R][5]/CE - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: design_1_i/VideoTiming_0/inst/VSync_reg/C - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: design_1_i/EnemyController_0/inst/enemies_reg[8][R][6]/CE - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 0.324ns (logic 0.079ns (24.410%) route 0.245ns (75.590%)) - Logic Levels: 1 (LUT6=1) - Clock Uncertainty: 0.163ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.085ns - Clock Net Delay (Source): 1.130ns (routing 0.640ns, distribution 0.490ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.295 0.374 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.414 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.414 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.196 0.610 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - 0.230 0.840 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.145 0.985 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.017 1.002 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.130 2.132 design_1_i/VideoTiming_0/inst/pixClk - SLICE_X32Y22 FDRE r design_1_i/VideoTiming_0/inst/VSync_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X32Y22 FDRE (Prop_DFF_SLICEL_C_Q) - 0.039 2.171 r design_1_i/VideoTiming_0/inst/VSync_reg/Q - net (fo=67, routed) 0.146 2.317 design_1_i/EnemyController_0/inst/FrameTick - SLICE_X28Y24 LUT6 (Prop_G6LUT_SLICEM_I0_O) - 0.040 2.357 r design_1_i/EnemyController_0/inst/enemies[8][R][9]_i_1/O - net (fo=9, routed) 0.099 2.456 design_1_i/EnemyController_0/inst/enemies[8][R] - SLICE_X29Y24 FDCE r design_1_i/EnemyController_0/inst/enemies_reg[8][R][6]/CE - ------------------------------------------------------------------- ------------------- - - - - - --------------------------------------------------------------------------------------- -Path Group: (none) -From Clock: - To Clock: clk25_design_1_clk_wiz_0_0 - -Max Delay 16 Endpoints -Min Delay 16 Endpoints --------------------------------------------------------------------------------------- - - -Max Delay Paths --------------------------------------------------------------------------------------- -Slack: inf - Source: design_1_i/EnemyController_0/inst/enemies_reg[23][R][1]/C - (rising edge-triggered cell FDCE) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[3]/D - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 9.971ns (logic 3.937ns (39.486%) route 6.034ns (60.514%)) - Logic Levels: 25 (CARRY8=8 DSP_A_B_DATA=1 DSP_ALU=1 DSP_M_DATA=1 DSP_MULTIPLIER=1 DSP_OUTPUT=1 DSP_PREADD_DATA=1 FDCE=1 LUT1=1 LUT2=3 LUT3=1 LUT4=1 LUT5=1 LUT6=3) - Clock Uncertainty: 0.163ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.085ns - Clock Net Delay (Destination): 1.859ns (routing 1.063ns, distribution 0.796ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X34Y51 FDCE 0.000 0.000 r design_1_i/EnemyController_0/inst/enemies_reg[23][R][1]/C - SLICE_X34Y51 FDCE (Prop_DFF_SLICEM_C_Q) - 0.078 0.078 f design_1_i/EnemyController_0/inst/enemies_reg[23][R][1]/Q - net (fo=9, routed) 0.649 0.727 design_1_i/ImgGen_0/inst/enemyY[23]4/A[1] - DSP48E2_X3Y22 DSP_A_B_DATA (Prop_DSP_A_B_DATA_DSP48E2_A[1]_A2_DATA[1]) - 0.192 0.919 r design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_A_B_DATA_INST/A2_DATA[1] - net (fo=1, routed) 0.000 0.919 design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_A_B_DATA.A2_DATA<1> - DSP48E2_X3Y22 DSP_PREADD_DATA (Prop_DSP_PREADD_DATA_DSP48E2_A2_DATA[1]_A2A1[1]) - 0.076 0.995 r design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_PREADD_DATA_INST/A2A1[1] - net (fo=1, routed) 0.000 0.995 design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_PREADD_DATA.A2A1<1> - DSP48E2_X3Y22 DSP_MULTIPLIER (Prop_DSP_MULTIPLIER_DSP48E2_A2A1[1]_U[1]) - 0.505 1.500 f design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_MULTIPLIER_INST/U[1] - net (fo=1, routed) 0.000 1.500 design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_MULTIPLIER.U<1> - DSP48E2_X3Y22 DSP_M_DATA (Prop_DSP_M_DATA_DSP48E2_U[1]_U_DATA[1]) - 0.047 1.547 r design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_M_DATA_INST/U_DATA[1] - net (fo=1, routed) 0.000 1.547 design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_M_DATA.U_DATA<1> - DSP48E2_X3Y22 DSP_ALU (Prop_DSP_ALU_DSP48E2_U_DATA[1]_ALU_OUT[1]) - 0.585 2.132 r design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_ALU_INST/ALU_OUT[1] - net (fo=1, routed) 0.000 2.132 design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_ALU.ALU_OUT<1> - DSP48E2_X3Y22 DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_ALU_OUT[1]_P[1]) - 0.109 2.241 f design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_OUTPUT_INST/P[1] - net (fo=1, routed) 0.694 2.935 design_1_i/ImgGen_0/inst/enemyY[23]4_n_104 - SLICE_X31Y55 LUT1 (Prop_A6LUT_SLICEM_I0_O) - 0.100 3.035 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6242/O - net (fo=1, routed) 0.013 3.048 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6242_n_0 - SLICE_X31Y55 CARRY8 (Prop_CARRY8_SLICEM_S[0]_O[7]) - 0.241 3.289 f design_1_i/ImgGen_0/inst/R[7]_INST_0_i_4812/O[7] - net (fo=4, routed) 0.401 3.690 design_1_i/ImgGen_0/inst/enemyY[23]4__0[8] - SLICE_X24Y57 LUT3 (Prop_B5LUT_SLICEM_I2_O) - 0.143 3.833 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6221/O - net (fo=2, routed) 0.468 4.301 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6221_n_0 - SLICE_X30Y56 CARRY8 (Prop_CARRY8_SLICEL_CI_CO[7]) - 0.151 4.452 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_7103/CO[7] - net (fo=1, routed) 0.026 4.478 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_7103_n_0 - SLICE_X30Y57 CARRY8 (Prop_CARRY8_SLICEL_CI_O[7]) - 0.116 4.594 f design_1_i/ImgGen_0/inst/R[7]_INST_0_i_7493/O[7] - net (fo=1, routed) 0.220 4.814 design_1_i/ImgGen_0/inst/enemyY[23]2[16] - SLICE_X29Y57 LUT2 (Prop_H6LUT_SLICEM_I1_O) - 0.152 4.966 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_7113/O - net (fo=1, routed) 0.015 4.981 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_7113_n_0 - SLICE_X29Y57 CARRY8 (Prop_CARRY8_SLICEM_S[7]_CO[7]) - 0.117 5.098 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6251/CO[7] - net (fo=1, routed) 0.026 5.124 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6251_n_0 - SLICE_X29Y58 CARRY8 (Prop_CARRY8_SLICEM_CI_O[5]) - 0.116 5.240 f design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6243/O[5] - net (fo=3, routed) 0.292 5.532 design_1_i/ImgGen_0/inst/enemyY[23]0[22] - SLICE_X27Y58 LUT2 (Prop_E6LUT_SLICEL_I1_O) - 0.147 5.679 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_4824/O - net (fo=1, routed) 0.007 5.686 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_4824_n_0 - SLICE_X27Y58 CARRY8 (Prop_CARRY8_SLICEL_S[4]_CO[7]) - 0.153 5.839 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_3170/CO[7] - net (fo=1, routed) 0.026 5.865 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_3170_n_0 - SLICE_X27Y59 CARRY8 (Prop_CARRY8_SLICEL_CI_O[5]) - 0.116 5.981 f design_1_i/ImgGen_0/inst/R[7]_INST_0_i_1695/O[5] - net (fo=2, routed) 0.248 6.229 design_1_i/ImgGen_0/inst/R4__0[31] - SLICE_X26Y58 LUT2 (Prop_H6LUT_SLICEL_I0_O) - 0.099 6.328 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_1696/O - net (fo=1, routed) 0.010 6.338 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_1696_n_0 - SLICE_X26Y58 CARRY8 (Prop_CARRY8_SLICEL_S[7]_CO[7]) - 0.122 6.460 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_737/CO[7] - net (fo=1, routed) 0.504 6.964 design_1_i/ImgGen_0/inst/R3 - SLICE_X35Y52 LUT5 (Prop_H6LUT_SLICEL_I1_O) - 0.150 7.114 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_239/O - net (fo=1, routed) 0.348 7.462 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_239_n_0 - SLICE_X35Y36 LUT6 (Prop_H6LUT_SLICEL_I5_O) - 0.124 7.586 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_53/O - net (fo=1, routed) 0.437 8.023 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_53_n_0 - SLICE_X22Y29 LUT4 (Prop_G6LUT_SLICEL_I1_O) - 0.149 8.172 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_15/O - net (fo=1, routed) 0.192 8.364 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_15_n_0 - SLICE_X23Y28 LUT6 (Prop_H6LUT_SLICEL_I4_O) - 0.099 8.463 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_3/O - net (fo=6, routed) 0.820 9.284 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_3_n_0 - SLICE_X30Y10 LUT6 (Prop_G6LUT_SLICEL_I5_O) - 0.050 9.334 r design_1_i/ImgGen_0/inst/R[0]_INST_0/O - net (fo=2, routed) 0.637 9.971 design_1_i/HDMI_TX_0/U0/i_wrap/R[3] - SLICE_X36Y6 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.519 0.598 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.638 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.638 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.333 0.971 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - 0.630 1.601 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.214 1.815 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.024 1.839 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.859 3.698 design_1_i/HDMI_TX_0/U0/i_wrap/pxClk - SLICE_X36Y6 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[3]/C - -Slack: inf - Source: design_1_i/EnemyController_0/inst/enemies_reg[23][R][1]/C - (rising edge-triggered cell FDCE) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[0]/D - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 9.887ns (logic 3.937ns (39.822%) route 5.950ns (60.178%)) - Logic Levels: 25 (CARRY8=8 DSP_A_B_DATA=1 DSP_ALU=1 DSP_M_DATA=1 DSP_MULTIPLIER=1 DSP_OUTPUT=1 DSP_PREADD_DATA=1 FDCE=1 LUT1=1 LUT2=3 LUT3=1 LUT4=1 LUT5=1 LUT6=3) - Clock Uncertainty: 0.163ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.085ns - Clock Net Delay (Destination): 1.859ns (routing 1.063ns, distribution 0.796ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X34Y51 FDCE 0.000 0.000 r design_1_i/EnemyController_0/inst/enemies_reg[23][R][1]/C - SLICE_X34Y51 FDCE (Prop_DFF_SLICEM_C_Q) - 0.078 0.078 f design_1_i/EnemyController_0/inst/enemies_reg[23][R][1]/Q - net (fo=9, routed) 0.649 0.727 design_1_i/ImgGen_0/inst/enemyY[23]4/A[1] - DSP48E2_X3Y22 DSP_A_B_DATA (Prop_DSP_A_B_DATA_DSP48E2_A[1]_A2_DATA[1]) - 0.192 0.919 r design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_A_B_DATA_INST/A2_DATA[1] - net (fo=1, routed) 0.000 0.919 design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_A_B_DATA.A2_DATA<1> - DSP48E2_X3Y22 DSP_PREADD_DATA (Prop_DSP_PREADD_DATA_DSP48E2_A2_DATA[1]_A2A1[1]) - 0.076 0.995 r design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_PREADD_DATA_INST/A2A1[1] - net (fo=1, routed) 0.000 0.995 design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_PREADD_DATA.A2A1<1> - DSP48E2_X3Y22 DSP_MULTIPLIER (Prop_DSP_MULTIPLIER_DSP48E2_A2A1[1]_U[1]) - 0.505 1.500 f design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_MULTIPLIER_INST/U[1] - net (fo=1, routed) 0.000 1.500 design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_MULTIPLIER.U<1> - DSP48E2_X3Y22 DSP_M_DATA (Prop_DSP_M_DATA_DSP48E2_U[1]_U_DATA[1]) - 0.047 1.547 r design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_M_DATA_INST/U_DATA[1] - net (fo=1, routed) 0.000 1.547 design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_M_DATA.U_DATA<1> - DSP48E2_X3Y22 DSP_ALU (Prop_DSP_ALU_DSP48E2_U_DATA[1]_ALU_OUT[1]) - 0.585 2.132 r design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_ALU_INST/ALU_OUT[1] - net (fo=1, routed) 0.000 2.132 design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_ALU.ALU_OUT<1> - DSP48E2_X3Y22 DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_ALU_OUT[1]_P[1]) - 0.109 2.241 f design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_OUTPUT_INST/P[1] - net (fo=1, routed) 0.694 2.935 design_1_i/ImgGen_0/inst/enemyY[23]4_n_104 - SLICE_X31Y55 LUT1 (Prop_A6LUT_SLICEM_I0_O) - 0.100 3.035 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6242/O - net (fo=1, routed) 0.013 3.048 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6242_n_0 - SLICE_X31Y55 CARRY8 (Prop_CARRY8_SLICEM_S[0]_O[7]) - 0.241 3.289 f design_1_i/ImgGen_0/inst/R[7]_INST_0_i_4812/O[7] - net (fo=4, routed) 0.401 3.690 design_1_i/ImgGen_0/inst/enemyY[23]4__0[8] - SLICE_X24Y57 LUT3 (Prop_B5LUT_SLICEM_I2_O) - 0.143 3.833 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6221/O - net (fo=2, routed) 0.468 4.301 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6221_n_0 - SLICE_X30Y56 CARRY8 (Prop_CARRY8_SLICEL_CI_CO[7]) - 0.151 4.452 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_7103/CO[7] - net (fo=1, routed) 0.026 4.478 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_7103_n_0 - SLICE_X30Y57 CARRY8 (Prop_CARRY8_SLICEL_CI_O[7]) - 0.116 4.594 f design_1_i/ImgGen_0/inst/R[7]_INST_0_i_7493/O[7] - net (fo=1, routed) 0.220 4.814 design_1_i/ImgGen_0/inst/enemyY[23]2[16] - SLICE_X29Y57 LUT2 (Prop_H6LUT_SLICEM_I1_O) - 0.152 4.966 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_7113/O - net (fo=1, routed) 0.015 4.981 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_7113_n_0 - SLICE_X29Y57 CARRY8 (Prop_CARRY8_SLICEM_S[7]_CO[7]) - 0.117 5.098 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6251/CO[7] - net (fo=1, routed) 0.026 5.124 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6251_n_0 - SLICE_X29Y58 CARRY8 (Prop_CARRY8_SLICEM_CI_O[5]) - 0.116 5.240 f design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6243/O[5] - net (fo=3, routed) 0.292 5.532 design_1_i/ImgGen_0/inst/enemyY[23]0[22] - SLICE_X27Y58 LUT2 (Prop_E6LUT_SLICEL_I1_O) - 0.147 5.679 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_4824/O - net (fo=1, routed) 0.007 5.686 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_4824_n_0 - SLICE_X27Y58 CARRY8 (Prop_CARRY8_SLICEL_S[4]_CO[7]) - 0.153 5.839 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_3170/CO[7] - net (fo=1, routed) 0.026 5.865 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_3170_n_0 - SLICE_X27Y59 CARRY8 (Prop_CARRY8_SLICEL_CI_O[5]) - 0.116 5.981 f design_1_i/ImgGen_0/inst/R[7]_INST_0_i_1695/O[5] - net (fo=2, routed) 0.248 6.229 design_1_i/ImgGen_0/inst/R4__0[31] - SLICE_X26Y58 LUT2 (Prop_H6LUT_SLICEL_I0_O) - 0.099 6.328 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_1696/O - net (fo=1, routed) 0.010 6.338 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_1696_n_0 - SLICE_X26Y58 CARRY8 (Prop_CARRY8_SLICEL_S[7]_CO[7]) - 0.122 6.460 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_737/CO[7] - net (fo=1, routed) 0.504 6.964 design_1_i/ImgGen_0/inst/R3 - SLICE_X35Y52 LUT5 (Prop_H6LUT_SLICEL_I1_O) - 0.150 7.114 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_239/O - net (fo=1, routed) 0.348 7.462 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_239_n_0 - SLICE_X35Y36 LUT6 (Prop_H6LUT_SLICEL_I5_O) - 0.124 7.586 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_53/O - net (fo=1, routed) 0.437 8.023 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_53_n_0 - SLICE_X22Y29 LUT4 (Prop_G6LUT_SLICEL_I1_O) - 0.149 8.172 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_15/O - net (fo=1, routed) 0.192 8.364 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_15_n_0 - SLICE_X23Y28 LUT6 (Prop_H6LUT_SLICEL_I4_O) - 0.099 8.463 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_3/O - net (fo=6, routed) 0.820 9.284 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_3_n_0 - SLICE_X30Y10 LUT6 (Prop_G6LUT_SLICEL_I5_O) - 0.050 9.334 r design_1_i/ImgGen_0/inst/R[0]_INST_0/O - net (fo=2, routed) 0.553 9.887 design_1_i/HDMI_TX_0/U0/i_wrap/R[0] - SLICE_X36Y6 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.519 0.598 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.638 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.638 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.333 0.971 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - 0.630 1.601 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.214 1.815 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.024 1.839 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.859 3.698 design_1_i/HDMI_TX_0/U0/i_wrap/pxClk - SLICE_X36Y6 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[0]/C - -Slack: inf - Source: design_1_i/EnemyController_0/inst/enemies_reg[23][R][1]/C - (rising edge-triggered cell FDCE) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[5]/D - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 9.504ns (logic 4.013ns (42.223%) route 5.491ns (57.777%)) - Logic Levels: 26 (CARRY8=8 DSP_A_B_DATA=1 DSP_ALU=1 DSP_M_DATA=1 DSP_MULTIPLIER=1 DSP_OUTPUT=1 DSP_PREADD_DATA=1 FDCE=1 LUT1=1 LUT2=4 LUT3=1 LUT4=1 LUT5=1 LUT6=3) - Clock Uncertainty: 0.163ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.085ns - Clock Net Delay (Destination): 1.840ns (routing 1.063ns, distribution 0.777ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X34Y51 FDCE 0.000 0.000 r design_1_i/EnemyController_0/inst/enemies_reg[23][R][1]/C - SLICE_X34Y51 FDCE (Prop_DFF_SLICEM_C_Q) - 0.078 0.078 f design_1_i/EnemyController_0/inst/enemies_reg[23][R][1]/Q - net (fo=9, routed) 0.649 0.727 design_1_i/ImgGen_0/inst/enemyY[23]4/A[1] - DSP48E2_X3Y22 DSP_A_B_DATA (Prop_DSP_A_B_DATA_DSP48E2_A[1]_A2_DATA[1]) - 0.192 0.919 r design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_A_B_DATA_INST/A2_DATA[1] - net (fo=1, routed) 0.000 0.919 design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_A_B_DATA.A2_DATA<1> - DSP48E2_X3Y22 DSP_PREADD_DATA (Prop_DSP_PREADD_DATA_DSP48E2_A2_DATA[1]_A2A1[1]) - 0.076 0.995 r design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_PREADD_DATA_INST/A2A1[1] - net (fo=1, routed) 0.000 0.995 design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_PREADD_DATA.A2A1<1> - DSP48E2_X3Y22 DSP_MULTIPLIER (Prop_DSP_MULTIPLIER_DSP48E2_A2A1[1]_U[1]) - 0.505 1.500 f design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_MULTIPLIER_INST/U[1] - net (fo=1, routed) 0.000 1.500 design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_MULTIPLIER.U<1> - DSP48E2_X3Y22 DSP_M_DATA (Prop_DSP_M_DATA_DSP48E2_U[1]_U_DATA[1]) - 0.047 1.547 r design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_M_DATA_INST/U_DATA[1] - net (fo=1, routed) 0.000 1.547 design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_M_DATA.U_DATA<1> - DSP48E2_X3Y22 DSP_ALU (Prop_DSP_ALU_DSP48E2_U_DATA[1]_ALU_OUT[1]) - 0.585 2.132 r design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_ALU_INST/ALU_OUT[1] - net (fo=1, routed) 0.000 2.132 design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_ALU.ALU_OUT<1> - DSP48E2_X3Y22 DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_ALU_OUT[1]_P[1]) - 0.109 2.241 f design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_OUTPUT_INST/P[1] - net (fo=1, routed) 0.694 2.935 design_1_i/ImgGen_0/inst/enemyY[23]4_n_104 - SLICE_X31Y55 LUT1 (Prop_A6LUT_SLICEM_I0_O) - 0.100 3.035 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6242/O - net (fo=1, routed) 0.013 3.048 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6242_n_0 - SLICE_X31Y55 CARRY8 (Prop_CARRY8_SLICEM_S[0]_O[7]) - 0.241 3.289 f design_1_i/ImgGen_0/inst/R[7]_INST_0_i_4812/O[7] - net (fo=4, routed) 0.401 3.690 design_1_i/ImgGen_0/inst/enemyY[23]4__0[8] - SLICE_X24Y57 LUT3 (Prop_B5LUT_SLICEM_I2_O) - 0.143 3.833 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6221/O - net (fo=2, routed) 0.468 4.301 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6221_n_0 - SLICE_X30Y56 CARRY8 (Prop_CARRY8_SLICEL_CI_CO[7]) - 0.151 4.452 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_7103/CO[7] - net (fo=1, routed) 0.026 4.478 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_7103_n_0 - SLICE_X30Y57 CARRY8 (Prop_CARRY8_SLICEL_CI_O[7]) - 0.116 4.594 f design_1_i/ImgGen_0/inst/R[7]_INST_0_i_7493/O[7] - net (fo=1, routed) 0.220 4.814 design_1_i/ImgGen_0/inst/enemyY[23]2[16] - SLICE_X29Y57 LUT2 (Prop_H6LUT_SLICEM_I1_O) - 0.152 4.966 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_7113/O - net (fo=1, routed) 0.015 4.981 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_7113_n_0 - SLICE_X29Y57 CARRY8 (Prop_CARRY8_SLICEM_S[7]_CO[7]) - 0.117 5.098 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6251/CO[7] - net (fo=1, routed) 0.026 5.124 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6251_n_0 - SLICE_X29Y58 CARRY8 (Prop_CARRY8_SLICEM_CI_O[5]) - 0.116 5.240 f design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6243/O[5] - net (fo=3, routed) 0.292 5.532 design_1_i/ImgGen_0/inst/enemyY[23]0[22] - SLICE_X27Y58 LUT2 (Prop_E6LUT_SLICEL_I1_O) - 0.147 5.679 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_4824/O - net (fo=1, routed) 0.007 5.686 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_4824_n_0 - SLICE_X27Y58 CARRY8 (Prop_CARRY8_SLICEL_S[4]_CO[7]) - 0.153 5.839 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_3170/CO[7] - net (fo=1, routed) 0.026 5.865 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_3170_n_0 - SLICE_X27Y59 CARRY8 (Prop_CARRY8_SLICEL_CI_O[5]) - 0.116 5.981 f design_1_i/ImgGen_0/inst/R[7]_INST_0_i_1695/O[5] - net (fo=2, routed) 0.248 6.229 design_1_i/ImgGen_0/inst/R4__0[31] - SLICE_X26Y58 LUT2 (Prop_H6LUT_SLICEL_I0_O) - 0.099 6.328 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_1696/O - net (fo=1, routed) 0.010 6.338 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_1696_n_0 - SLICE_X26Y58 CARRY8 (Prop_CARRY8_SLICEL_S[7]_CO[7]) - 0.122 6.460 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_737/CO[7] - net (fo=1, routed) 0.504 6.964 design_1_i/ImgGen_0/inst/R3 - SLICE_X35Y52 LUT5 (Prop_H6LUT_SLICEL_I1_O) - 0.150 7.114 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_239/O - net (fo=1, routed) 0.348 7.462 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_239_n_0 - SLICE_X35Y36 LUT6 (Prop_H6LUT_SLICEL_I5_O) - 0.124 7.586 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_53/O - net (fo=1, routed) 0.437 8.023 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_53_n_0 - SLICE_X22Y29 LUT4 (Prop_G6LUT_SLICEL_I1_O) - 0.149 8.172 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_15/O - net (fo=1, routed) 0.192 8.364 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_15_n_0 - SLICE_X23Y28 LUT6 (Prop_H6LUT_SLICEL_I4_O) - 0.099 8.463 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_3/O - net (fo=6, routed) 0.686 9.149 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_3_n_0 - SLICE_X36Y9 LUT2 (Prop_A6LUT_SLICEL_I0_O) - 0.090 9.239 r design_1_i/ImgGen_0/inst/R[5]_INST_0_i_4/O - net (fo=2, routed) 0.180 9.419 design_1_i/ImgGen_0/inst/R[5]_INST_0_i_4_n_0 - SLICE_X35Y10 LUT6 (Prop_D6LUT_SLICEL_I5_O) - 0.036 9.455 r design_1_i/ImgGen_0/inst/R[5]_INST_0/O - net (fo=1, routed) 0.049 9.504 design_1_i/HDMI_TX_0/U0/i_wrap/R[5] - SLICE_X35Y10 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[5]/D - ------------------------------------------------------------------- ------------------- - - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.519 0.598 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.638 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.638 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.333 0.971 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - 0.630 1.601 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.214 1.815 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.024 1.839 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.840 3.679 design_1_i/HDMI_TX_0/U0/i_wrap/pxClk - SLICE_X35Y10 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[5]/C - -Slack: inf - Source: design_1_i/EnemyController_0/inst/enemies_reg[23][R][1]/C - (rising edge-triggered cell FDCE) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[7]/D - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 9.486ns (logic 3.987ns (42.030%) route 5.499ns (57.970%)) - Logic Levels: 25 (CARRY8=8 DSP_A_B_DATA=1 DSP_ALU=1 DSP_M_DATA=1 DSP_MULTIPLIER=1 DSP_OUTPUT=1 DSP_PREADD_DATA=1 FDCE=1 LUT1=1 LUT2=3 LUT3=2 LUT4=1 LUT5=1 LUT6=2) - Clock Uncertainty: 0.163ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.085ns - Clock Net Delay (Destination): 1.863ns (routing 1.063ns, distribution 0.800ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X34Y51 FDCE 0.000 0.000 r design_1_i/EnemyController_0/inst/enemies_reg[23][R][1]/C - SLICE_X34Y51 FDCE (Prop_DFF_SLICEM_C_Q) - 0.078 0.078 f design_1_i/EnemyController_0/inst/enemies_reg[23][R][1]/Q - net (fo=9, routed) 0.649 0.727 design_1_i/ImgGen_0/inst/enemyY[23]4/A[1] - DSP48E2_X3Y22 DSP_A_B_DATA (Prop_DSP_A_B_DATA_DSP48E2_A[1]_A2_DATA[1]) - 0.192 0.919 r design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_A_B_DATA_INST/A2_DATA[1] - net (fo=1, routed) 0.000 0.919 design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_A_B_DATA.A2_DATA<1> - DSP48E2_X3Y22 DSP_PREADD_DATA (Prop_DSP_PREADD_DATA_DSP48E2_A2_DATA[1]_A2A1[1]) - 0.076 0.995 r design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_PREADD_DATA_INST/A2A1[1] - net (fo=1, routed) 0.000 0.995 design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_PREADD_DATA.A2A1<1> - DSP48E2_X3Y22 DSP_MULTIPLIER (Prop_DSP_MULTIPLIER_DSP48E2_A2A1[1]_U[1]) - 0.505 1.500 f design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_MULTIPLIER_INST/U[1] - net (fo=1, routed) 0.000 1.500 design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_MULTIPLIER.U<1> - DSP48E2_X3Y22 DSP_M_DATA (Prop_DSP_M_DATA_DSP48E2_U[1]_U_DATA[1]) - 0.047 1.547 r design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_M_DATA_INST/U_DATA[1] - net (fo=1, routed) 0.000 1.547 design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_M_DATA.U_DATA<1> - DSP48E2_X3Y22 DSP_ALU (Prop_DSP_ALU_DSP48E2_U_DATA[1]_ALU_OUT[1]) - 0.585 2.132 r design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_ALU_INST/ALU_OUT[1] - net (fo=1, routed) 0.000 2.132 design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_ALU.ALU_OUT<1> - DSP48E2_X3Y22 DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_ALU_OUT[1]_P[1]) - 0.109 2.241 f design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_OUTPUT_INST/P[1] - net (fo=1, routed) 0.694 2.935 design_1_i/ImgGen_0/inst/enemyY[23]4_n_104 - SLICE_X31Y55 LUT1 (Prop_A6LUT_SLICEM_I0_O) - 0.100 3.035 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6242/O - net (fo=1, routed) 0.013 3.048 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6242_n_0 - SLICE_X31Y55 CARRY8 (Prop_CARRY8_SLICEM_S[0]_O[7]) - 0.241 3.289 f design_1_i/ImgGen_0/inst/R[7]_INST_0_i_4812/O[7] - net (fo=4, routed) 0.401 3.690 design_1_i/ImgGen_0/inst/enemyY[23]4__0[8] - SLICE_X24Y57 LUT3 (Prop_B5LUT_SLICEM_I2_O) - 0.143 3.833 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6221/O - net (fo=2, routed) 0.468 4.301 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6221_n_0 - SLICE_X30Y56 CARRY8 (Prop_CARRY8_SLICEL_CI_CO[7]) - 0.151 4.452 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_7103/CO[7] - net (fo=1, routed) 0.026 4.478 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_7103_n_0 - SLICE_X30Y57 CARRY8 (Prop_CARRY8_SLICEL_CI_O[7]) - 0.116 4.594 f design_1_i/ImgGen_0/inst/R[7]_INST_0_i_7493/O[7] - net (fo=1, routed) 0.220 4.814 design_1_i/ImgGen_0/inst/enemyY[23]2[16] - SLICE_X29Y57 LUT2 (Prop_H6LUT_SLICEM_I1_O) - 0.152 4.966 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_7113/O - net (fo=1, routed) 0.015 4.981 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_7113_n_0 - SLICE_X29Y57 CARRY8 (Prop_CARRY8_SLICEM_S[7]_CO[7]) - 0.117 5.098 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6251/CO[7] - net (fo=1, routed) 0.026 5.124 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6251_n_0 - SLICE_X29Y58 CARRY8 (Prop_CARRY8_SLICEM_CI_O[5]) - 0.116 5.240 f design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6243/O[5] - net (fo=3, routed) 0.292 5.532 design_1_i/ImgGen_0/inst/enemyY[23]0[22] - SLICE_X27Y58 LUT2 (Prop_E6LUT_SLICEL_I1_O) - 0.147 5.679 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_4824/O - net (fo=1, routed) 0.007 5.686 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_4824_n_0 - SLICE_X27Y58 CARRY8 (Prop_CARRY8_SLICEL_S[4]_CO[7]) - 0.153 5.839 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_3170/CO[7] - net (fo=1, routed) 0.026 5.865 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_3170_n_0 - SLICE_X27Y59 CARRY8 (Prop_CARRY8_SLICEL_CI_O[5]) - 0.116 5.981 f design_1_i/ImgGen_0/inst/R[7]_INST_0_i_1695/O[5] - net (fo=2, routed) 0.248 6.229 design_1_i/ImgGen_0/inst/R4__0[31] - SLICE_X26Y58 LUT2 (Prop_H6LUT_SLICEL_I0_O) - 0.099 6.328 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_1696/O - net (fo=1, routed) 0.010 6.338 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_1696_n_0 - SLICE_X26Y58 CARRY8 (Prop_CARRY8_SLICEL_S[7]_CO[7]) - 0.122 6.460 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_737/CO[7] - net (fo=1, routed) 0.504 6.964 design_1_i/ImgGen_0/inst/R3 - SLICE_X35Y52 LUT5 (Prop_H6LUT_SLICEL_I1_O) - 0.150 7.114 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_239/O - net (fo=1, routed) 0.348 7.462 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_239_n_0 - SLICE_X35Y36 LUT6 (Prop_H6LUT_SLICEL_I5_O) - 0.124 7.586 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_53/O - net (fo=1, routed) 0.437 8.023 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_53_n_0 - SLICE_X22Y29 LUT4 (Prop_G6LUT_SLICEL_I1_O) - 0.149 8.172 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_15/O - net (fo=1, routed) 0.192 8.364 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_15_n_0 - SLICE_X23Y28 LUT6 (Prop_H6LUT_SLICEL_I4_O) - 0.099 8.463 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_3/O - net (fo=6, routed) 0.686 9.149 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_3_n_0 - SLICE_X36Y9 LUT3 (Prop_A5LUT_SLICEL_I2_O) - 0.100 9.249 r design_1_i/ImgGen_0/inst/R[7]_INST_0/O - net (fo=1, routed) 0.237 9.486 design_1_i/HDMI_TX_0/U0/i_wrap/R[7] - SLICE_X36Y9 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[7]/D - ------------------------------------------------------------------- ------------------- - - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.519 0.598 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.638 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.638 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.333 0.971 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - 0.630 1.601 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.214 1.815 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.024 1.839 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.863 3.702 design_1_i/HDMI_TX_0/U0/i_wrap/pxClk - SLICE_X36Y9 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[7]/C - -Slack: inf - Source: design_1_i/EnemyController_0/inst/enemies_reg[23][R][1]/C - (rising edge-triggered cell FDCE) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[2]/D - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 9.368ns (logic 4.012ns (42.826%) route 5.356ns (57.174%)) - Logic Levels: 26 (CARRY8=8 DSP_A_B_DATA=1 DSP_ALU=1 DSP_M_DATA=1 DSP_MULTIPLIER=1 DSP_OUTPUT=1 DSP_PREADD_DATA=1 FDCE=1 LUT1=1 LUT2=4 LUT3=1 LUT4=1 LUT5=1 LUT6=3) - Clock Uncertainty: 0.163ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.085ns - Clock Net Delay (Destination): 1.861ns (routing 1.063ns, distribution 0.798ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X34Y51 FDCE 0.000 0.000 r design_1_i/EnemyController_0/inst/enemies_reg[23][R][1]/C - SLICE_X34Y51 FDCE (Prop_DFF_SLICEM_C_Q) - 0.078 0.078 f design_1_i/EnemyController_0/inst/enemies_reg[23][R][1]/Q - net (fo=9, routed) 0.649 0.727 design_1_i/ImgGen_0/inst/enemyY[23]4/A[1] - DSP48E2_X3Y22 DSP_A_B_DATA (Prop_DSP_A_B_DATA_DSP48E2_A[1]_A2_DATA[1]) - 0.192 0.919 r design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_A_B_DATA_INST/A2_DATA[1] - net (fo=1, routed) 0.000 0.919 design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_A_B_DATA.A2_DATA<1> - DSP48E2_X3Y22 DSP_PREADD_DATA (Prop_DSP_PREADD_DATA_DSP48E2_A2_DATA[1]_A2A1[1]) - 0.076 0.995 r design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_PREADD_DATA_INST/A2A1[1] - net (fo=1, routed) 0.000 0.995 design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_PREADD_DATA.A2A1<1> - DSP48E2_X3Y22 DSP_MULTIPLIER (Prop_DSP_MULTIPLIER_DSP48E2_A2A1[1]_U[1]) - 0.505 1.500 f design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_MULTIPLIER_INST/U[1] - net (fo=1, routed) 0.000 1.500 design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_MULTIPLIER.U<1> - DSP48E2_X3Y22 DSP_M_DATA (Prop_DSP_M_DATA_DSP48E2_U[1]_U_DATA[1]) - 0.047 1.547 r design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_M_DATA_INST/U_DATA[1] - net (fo=1, routed) 0.000 1.547 design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_M_DATA.U_DATA<1> - DSP48E2_X3Y22 DSP_ALU (Prop_DSP_ALU_DSP48E2_U_DATA[1]_ALU_OUT[1]) - 0.585 2.132 r design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_ALU_INST/ALU_OUT[1] - net (fo=1, routed) 0.000 2.132 design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_ALU.ALU_OUT<1> - DSP48E2_X3Y22 DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_ALU_OUT[1]_P[1]) - 0.109 2.241 f design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_OUTPUT_INST/P[1] - net (fo=1, routed) 0.694 2.935 design_1_i/ImgGen_0/inst/enemyY[23]4_n_104 - SLICE_X31Y55 LUT1 (Prop_A6LUT_SLICEM_I0_O) - 0.100 3.035 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6242/O - net (fo=1, routed) 0.013 3.048 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6242_n_0 - SLICE_X31Y55 CARRY8 (Prop_CARRY8_SLICEM_S[0]_O[7]) - 0.241 3.289 f design_1_i/ImgGen_0/inst/R[7]_INST_0_i_4812/O[7] - net (fo=4, routed) 0.401 3.690 design_1_i/ImgGen_0/inst/enemyY[23]4__0[8] - SLICE_X24Y57 LUT3 (Prop_B5LUT_SLICEM_I2_O) - 0.143 3.833 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6221/O - net (fo=2, routed) 0.468 4.301 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6221_n_0 - SLICE_X30Y56 CARRY8 (Prop_CARRY8_SLICEL_CI_CO[7]) - 0.151 4.452 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_7103/CO[7] - net (fo=1, routed) 0.026 4.478 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_7103_n_0 - SLICE_X30Y57 CARRY8 (Prop_CARRY8_SLICEL_CI_O[7]) - 0.116 4.594 f design_1_i/ImgGen_0/inst/R[7]_INST_0_i_7493/O[7] - net (fo=1, routed) 0.220 4.814 design_1_i/ImgGen_0/inst/enemyY[23]2[16] - SLICE_X29Y57 LUT2 (Prop_H6LUT_SLICEM_I1_O) - 0.152 4.966 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_7113/O - net (fo=1, routed) 0.015 4.981 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_7113_n_0 - SLICE_X29Y57 CARRY8 (Prop_CARRY8_SLICEM_S[7]_CO[7]) - 0.117 5.098 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6251/CO[7] - net (fo=1, routed) 0.026 5.124 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6251_n_0 - SLICE_X29Y58 CARRY8 (Prop_CARRY8_SLICEM_CI_O[5]) - 0.116 5.240 f design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6243/O[5] - net (fo=3, routed) 0.292 5.532 design_1_i/ImgGen_0/inst/enemyY[23]0[22] - SLICE_X27Y58 LUT2 (Prop_E6LUT_SLICEL_I1_O) - 0.147 5.679 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_4824/O - net (fo=1, routed) 0.007 5.686 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_4824_n_0 - SLICE_X27Y58 CARRY8 (Prop_CARRY8_SLICEL_S[4]_CO[7]) - 0.153 5.839 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_3170/CO[7] - net (fo=1, routed) 0.026 5.865 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_3170_n_0 - SLICE_X27Y59 CARRY8 (Prop_CARRY8_SLICEL_CI_O[5]) - 0.116 5.981 f design_1_i/ImgGen_0/inst/R[7]_INST_0_i_1695/O[5] - net (fo=2, routed) 0.248 6.229 design_1_i/ImgGen_0/inst/R4__0[31] - SLICE_X26Y58 LUT2 (Prop_H6LUT_SLICEL_I0_O) - 0.099 6.328 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_1696/O - net (fo=1, routed) 0.010 6.338 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_1696_n_0 - SLICE_X26Y58 CARRY8 (Prop_CARRY8_SLICEL_S[7]_CO[7]) - 0.122 6.460 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_737/CO[7] - net (fo=1, routed) 0.504 6.964 design_1_i/ImgGen_0/inst/R3 - SLICE_X35Y52 LUT5 (Prop_H6LUT_SLICEL_I1_O) - 0.150 7.114 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_239/O - net (fo=1, routed) 0.348 7.462 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_239_n_0 - SLICE_X35Y36 LUT6 (Prop_H6LUT_SLICEL_I5_O) - 0.124 7.586 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_53/O - net (fo=1, routed) 0.437 8.023 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_53_n_0 - SLICE_X22Y29 LUT4 (Prop_G6LUT_SLICEL_I1_O) - 0.149 8.172 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_15/O - net (fo=1, routed) 0.192 8.364 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_15_n_0 - SLICE_X23Y28 LUT6 (Prop_H6LUT_SLICEL_I4_O) - 0.099 8.463 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_3/O - net (fo=6, routed) 0.686 9.149 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_3_n_0 - SLICE_X36Y9 LUT2 (Prop_A6LUT_SLICEL_I0_O) - 0.090 9.239 r design_1_i/ImgGen_0/inst/R[5]_INST_0_i_4/O - net (fo=2, routed) 0.044 9.283 design_1_i/ImgGen_0/inst/R[5]_INST_0_i_4_n_0 - SLICE_X36Y9 LUT6 (Prop_C6LUT_SLICEL_I5_O) - 0.035 9.318 r design_1_i/ImgGen_0/inst/R[2]_INST_0/O - net (fo=1, routed) 0.050 9.368 design_1_i/HDMI_TX_0/U0/i_wrap/R[2] - SLICE_X36Y9 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.519 0.598 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.638 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.638 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.333 0.971 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - 0.630 1.601 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.214 1.815 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.024 1.839 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.861 3.700 design_1_i/HDMI_TX_0/U0/i_wrap/pxClk - SLICE_X36Y9 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[2]/C - -Slack: inf - Source: design_1_i/EnemyController_0/inst/enemies_reg[23][R][1]/C - (rising edge-triggered cell FDCE) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[1]/D - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 9.338ns (logic 3.986ns (42.685%) route 5.352ns (57.315%)) - Logic Levels: 25 (CARRY8=8 DSP_A_B_DATA=1 DSP_ALU=1 DSP_M_DATA=1 DSP_MULTIPLIER=1 DSP_OUTPUT=1 DSP_PREADD_DATA=1 FDCE=1 LUT1=1 LUT2=3 LUT3=1 LUT4=1 LUT5=1 LUT6=3) - Clock Uncertainty: 0.163ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.085ns - Clock Net Delay (Destination): 1.822ns (routing 1.063ns, distribution 0.759ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X34Y51 FDCE 0.000 0.000 r design_1_i/EnemyController_0/inst/enemies_reg[23][R][1]/C - SLICE_X34Y51 FDCE (Prop_DFF_SLICEM_C_Q) - 0.078 0.078 f design_1_i/EnemyController_0/inst/enemies_reg[23][R][1]/Q - net (fo=9, routed) 0.649 0.727 design_1_i/ImgGen_0/inst/enemyY[23]4/A[1] - DSP48E2_X3Y22 DSP_A_B_DATA (Prop_DSP_A_B_DATA_DSP48E2_A[1]_A2_DATA[1]) - 0.192 0.919 r design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_A_B_DATA_INST/A2_DATA[1] - net (fo=1, routed) 0.000 0.919 design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_A_B_DATA.A2_DATA<1> - DSP48E2_X3Y22 DSP_PREADD_DATA (Prop_DSP_PREADD_DATA_DSP48E2_A2_DATA[1]_A2A1[1]) - 0.076 0.995 r design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_PREADD_DATA_INST/A2A1[1] - net (fo=1, routed) 0.000 0.995 design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_PREADD_DATA.A2A1<1> - DSP48E2_X3Y22 DSP_MULTIPLIER (Prop_DSP_MULTIPLIER_DSP48E2_A2A1[1]_U[1]) - 0.505 1.500 f design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_MULTIPLIER_INST/U[1] - net (fo=1, routed) 0.000 1.500 design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_MULTIPLIER.U<1> - DSP48E2_X3Y22 DSP_M_DATA (Prop_DSP_M_DATA_DSP48E2_U[1]_U_DATA[1]) - 0.047 1.547 r design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_M_DATA_INST/U_DATA[1] - net (fo=1, routed) 0.000 1.547 design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_M_DATA.U_DATA<1> - DSP48E2_X3Y22 DSP_ALU (Prop_DSP_ALU_DSP48E2_U_DATA[1]_ALU_OUT[1]) - 0.585 2.132 r design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_ALU_INST/ALU_OUT[1] - net (fo=1, routed) 0.000 2.132 design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_ALU.ALU_OUT<1> - DSP48E2_X3Y22 DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_ALU_OUT[1]_P[1]) - 0.109 2.241 f design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_OUTPUT_INST/P[1] - net (fo=1, routed) 0.694 2.935 design_1_i/ImgGen_0/inst/enemyY[23]4_n_104 - SLICE_X31Y55 LUT1 (Prop_A6LUT_SLICEM_I0_O) - 0.100 3.035 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6242/O - net (fo=1, routed) 0.013 3.048 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6242_n_0 - SLICE_X31Y55 CARRY8 (Prop_CARRY8_SLICEM_S[0]_O[7]) - 0.241 3.289 f design_1_i/ImgGen_0/inst/R[7]_INST_0_i_4812/O[7] - net (fo=4, routed) 0.401 3.690 design_1_i/ImgGen_0/inst/enemyY[23]4__0[8] - SLICE_X24Y57 LUT3 (Prop_B5LUT_SLICEM_I2_O) - 0.143 3.833 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6221/O - net (fo=2, routed) 0.468 4.301 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6221_n_0 - SLICE_X30Y56 CARRY8 (Prop_CARRY8_SLICEL_CI_CO[7]) - 0.151 4.452 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_7103/CO[7] - net (fo=1, routed) 0.026 4.478 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_7103_n_0 - SLICE_X30Y57 CARRY8 (Prop_CARRY8_SLICEL_CI_O[7]) - 0.116 4.594 f design_1_i/ImgGen_0/inst/R[7]_INST_0_i_7493/O[7] - net (fo=1, routed) 0.220 4.814 design_1_i/ImgGen_0/inst/enemyY[23]2[16] - SLICE_X29Y57 LUT2 (Prop_H6LUT_SLICEM_I1_O) - 0.152 4.966 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_7113/O - net (fo=1, routed) 0.015 4.981 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_7113_n_0 - SLICE_X29Y57 CARRY8 (Prop_CARRY8_SLICEM_S[7]_CO[7]) - 0.117 5.098 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6251/CO[7] - net (fo=1, routed) 0.026 5.124 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6251_n_0 - SLICE_X29Y58 CARRY8 (Prop_CARRY8_SLICEM_CI_O[5]) - 0.116 5.240 f design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6243/O[5] - net (fo=3, routed) 0.292 5.532 design_1_i/ImgGen_0/inst/enemyY[23]0[22] - SLICE_X27Y58 LUT2 (Prop_E6LUT_SLICEL_I1_O) - 0.147 5.679 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_4824/O - net (fo=1, routed) 0.007 5.686 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_4824_n_0 - SLICE_X27Y58 CARRY8 (Prop_CARRY8_SLICEL_S[4]_CO[7]) - 0.153 5.839 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_3170/CO[7] - net (fo=1, routed) 0.026 5.865 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_3170_n_0 - SLICE_X27Y59 CARRY8 (Prop_CARRY8_SLICEL_CI_O[5]) - 0.116 5.981 f design_1_i/ImgGen_0/inst/R[7]_INST_0_i_1695/O[5] - net (fo=2, routed) 0.248 6.229 design_1_i/ImgGen_0/inst/R4__0[31] - SLICE_X26Y58 LUT2 (Prop_H6LUT_SLICEL_I0_O) - 0.099 6.328 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_1696/O - net (fo=1, routed) 0.010 6.338 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_1696_n_0 - SLICE_X26Y58 CARRY8 (Prop_CARRY8_SLICEL_S[7]_CO[7]) - 0.122 6.460 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_737/CO[7] - net (fo=1, routed) 0.504 6.964 design_1_i/ImgGen_0/inst/R3 - SLICE_X35Y52 LUT5 (Prop_H6LUT_SLICEL_I1_O) - 0.150 7.114 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_239/O - net (fo=1, routed) 0.348 7.462 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_239_n_0 - SLICE_X35Y36 LUT6 (Prop_H6LUT_SLICEL_I5_O) - 0.124 7.586 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_53/O - net (fo=1, routed) 0.437 8.023 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_53_n_0 - SLICE_X22Y29 LUT4 (Prop_G6LUT_SLICEL_I1_O) - 0.149 8.172 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_15/O - net (fo=1, routed) 0.192 8.364 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_15_n_0 - SLICE_X23Y28 LUT6 (Prop_H6LUT_SLICEL_I4_O) - 0.099 8.463 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_3/O - net (fo=6, routed) 0.727 9.190 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_3_n_0 - SLICE_X32Y9 LUT6 (Prop_D6LUT_SLICEL_I5_O) - 0.099 9.289 r design_1_i/ImgGen_0/inst/R[1]_INST_0/O - net (fo=1, routed) 0.049 9.338 design_1_i/HDMI_TX_0/U0/i_wrap/R[1] - SLICE_X32Y9 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.519 0.598 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.638 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.638 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.333 0.971 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - 0.630 1.601 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.214 1.815 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.024 1.839 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.822 3.661 design_1_i/HDMI_TX_0/U0/i_wrap/pxClk - SLICE_X32Y9 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[1]/C - -Slack: inf - Source: design_1_i/EnemyController_0/inst/enemies_reg[23][R][1]/C - (rising edge-triggered cell FDCE) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[6]/D - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 9.157ns (logic 4.010ns (43.790%) route 5.147ns (56.210%)) - Logic Levels: 25 (CARRY8=8 DSP_A_B_DATA=1 DSP_ALU=1 DSP_M_DATA=1 DSP_MULTIPLIER=1 DSP_OUTPUT=1 DSP_PREADD_DATA=1 FDCE=1 LUT1=1 LUT2=3 LUT3=1 LUT4=1 LUT5=1 LUT6=3) - Clock Uncertainty: 0.163ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.085ns - Clock Net Delay (Destination): 1.830ns (routing 1.063ns, distribution 0.767ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X34Y51 FDCE 0.000 0.000 r design_1_i/EnemyController_0/inst/enemies_reg[23][R][1]/C - SLICE_X34Y51 FDCE (Prop_DFF_SLICEM_C_Q) - 0.078 0.078 f design_1_i/EnemyController_0/inst/enemies_reg[23][R][1]/Q - net (fo=9, routed) 0.649 0.727 design_1_i/ImgGen_0/inst/enemyY[23]4/A[1] - DSP48E2_X3Y22 DSP_A_B_DATA (Prop_DSP_A_B_DATA_DSP48E2_A[1]_A2_DATA[1]) - 0.192 0.919 r design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_A_B_DATA_INST/A2_DATA[1] - net (fo=1, routed) 0.000 0.919 design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_A_B_DATA.A2_DATA<1> - DSP48E2_X3Y22 DSP_PREADD_DATA (Prop_DSP_PREADD_DATA_DSP48E2_A2_DATA[1]_A2A1[1]) - 0.076 0.995 r design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_PREADD_DATA_INST/A2A1[1] - net (fo=1, routed) 0.000 0.995 design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_PREADD_DATA.A2A1<1> - DSP48E2_X3Y22 DSP_MULTIPLIER (Prop_DSP_MULTIPLIER_DSP48E2_A2A1[1]_U[1]) - 0.505 1.500 f design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_MULTIPLIER_INST/U[1] - net (fo=1, routed) 0.000 1.500 design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_MULTIPLIER.U<1> - DSP48E2_X3Y22 DSP_M_DATA (Prop_DSP_M_DATA_DSP48E2_U[1]_U_DATA[1]) - 0.047 1.547 r design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_M_DATA_INST/U_DATA[1] - net (fo=1, routed) 0.000 1.547 design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_M_DATA.U_DATA<1> - DSP48E2_X3Y22 DSP_ALU (Prop_DSP_ALU_DSP48E2_U_DATA[1]_ALU_OUT[1]) - 0.585 2.132 r design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_ALU_INST/ALU_OUT[1] - net (fo=1, routed) 0.000 2.132 design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_ALU.ALU_OUT<1> - DSP48E2_X3Y22 DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_ALU_OUT[1]_P[1]) - 0.109 2.241 f design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_OUTPUT_INST/P[1] - net (fo=1, routed) 0.694 2.935 design_1_i/ImgGen_0/inst/enemyY[23]4_n_104 - SLICE_X31Y55 LUT1 (Prop_A6LUT_SLICEM_I0_O) - 0.100 3.035 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6242/O - net (fo=1, routed) 0.013 3.048 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6242_n_0 - SLICE_X31Y55 CARRY8 (Prop_CARRY8_SLICEM_S[0]_O[7]) - 0.241 3.289 f design_1_i/ImgGen_0/inst/R[7]_INST_0_i_4812/O[7] - net (fo=4, routed) 0.401 3.690 design_1_i/ImgGen_0/inst/enemyY[23]4__0[8] - SLICE_X24Y57 LUT3 (Prop_B5LUT_SLICEM_I2_O) - 0.143 3.833 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6221/O - net (fo=2, routed) 0.468 4.301 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6221_n_0 - SLICE_X30Y56 CARRY8 (Prop_CARRY8_SLICEL_CI_CO[7]) - 0.151 4.452 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_7103/CO[7] - net (fo=1, routed) 0.026 4.478 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_7103_n_0 - SLICE_X30Y57 CARRY8 (Prop_CARRY8_SLICEL_CI_O[7]) - 0.116 4.594 f design_1_i/ImgGen_0/inst/R[7]_INST_0_i_7493/O[7] - net (fo=1, routed) 0.220 4.814 design_1_i/ImgGen_0/inst/enemyY[23]2[16] - SLICE_X29Y57 LUT2 (Prop_H6LUT_SLICEM_I1_O) - 0.152 4.966 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_7113/O - net (fo=1, routed) 0.015 4.981 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_7113_n_0 - SLICE_X29Y57 CARRY8 (Prop_CARRY8_SLICEM_S[7]_CO[7]) - 0.117 5.098 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6251/CO[7] - net (fo=1, routed) 0.026 5.124 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6251_n_0 - SLICE_X29Y58 CARRY8 (Prop_CARRY8_SLICEM_CI_O[5]) - 0.116 5.240 f design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6243/O[5] - net (fo=3, routed) 0.292 5.532 design_1_i/ImgGen_0/inst/enemyY[23]0[22] - SLICE_X27Y58 LUT2 (Prop_E6LUT_SLICEL_I1_O) - 0.147 5.679 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_4824/O - net (fo=1, routed) 0.007 5.686 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_4824_n_0 - SLICE_X27Y58 CARRY8 (Prop_CARRY8_SLICEL_S[4]_CO[7]) - 0.153 5.839 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_3170/CO[7] - net (fo=1, routed) 0.026 5.865 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_3170_n_0 - SLICE_X27Y59 CARRY8 (Prop_CARRY8_SLICEL_CI_O[5]) - 0.116 5.981 f design_1_i/ImgGen_0/inst/R[7]_INST_0_i_1695/O[5] - net (fo=2, routed) 0.248 6.229 design_1_i/ImgGen_0/inst/R4__0[31] - SLICE_X26Y58 LUT2 (Prop_H6LUT_SLICEL_I0_O) - 0.099 6.328 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_1696/O - net (fo=1, routed) 0.010 6.338 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_1696_n_0 - SLICE_X26Y58 CARRY8 (Prop_CARRY8_SLICEL_S[7]_CO[7]) - 0.122 6.460 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_737/CO[7] - net (fo=1, routed) 0.504 6.964 design_1_i/ImgGen_0/inst/R3 - SLICE_X35Y52 LUT5 (Prop_H6LUT_SLICEL_I1_O) - 0.150 7.114 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_239/O - net (fo=1, routed) 0.348 7.462 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_239_n_0 - SLICE_X35Y36 LUT6 (Prop_H6LUT_SLICEL_I5_O) - 0.124 7.586 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_53/O - net (fo=1, routed) 0.437 8.023 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_53_n_0 - SLICE_X22Y29 LUT4 (Prop_G6LUT_SLICEL_I1_O) - 0.149 8.172 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_15/O - net (fo=1, routed) 0.192 8.364 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_15_n_0 - SLICE_X23Y28 LUT6 (Prop_H6LUT_SLICEL_I4_O) - 0.099 8.463 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_3/O - net (fo=6, routed) 0.505 8.968 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_3_n_0 - SLICE_X29Y7 LUT6 (Prop_C6LUT_SLICEM_I5_O) - 0.123 9.091 r design_1_i/ImgGen_0/inst/R[6]_INST_0/O - net (fo=1, routed) 0.066 9.157 design_1_i/HDMI_TX_0/U0/i_wrap/R[6] - SLICE_X29Y7 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.519 0.598 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.638 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.638 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.333 0.971 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - 0.630 1.601 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.214 1.815 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.024 1.839 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.830 3.669 design_1_i/HDMI_TX_0/U0/i_wrap/pxClk - SLICE_X29Y7 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[6]/C - -Slack: inf - Source: design_1_i/EnemyController_0/inst/enemies_reg[23][R][1]/C - (rising edge-triggered cell FDCE) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[4]/D - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 9.135ns (logic 4.035ns (44.173%) route 5.100ns (55.827%)) - Logic Levels: 25 (CARRY8=8 DSP_A_B_DATA=1 DSP_ALU=1 DSP_M_DATA=1 DSP_MULTIPLIER=1 DSP_OUTPUT=1 DSP_PREADD_DATA=1 FDCE=1 LUT1=1 LUT2=3 LUT3=1 LUT4=1 LUT5=1 LUT6=3) - Clock Uncertainty: 0.163ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.085ns - Clock Net Delay (Destination): 1.826ns (routing 1.063ns, distribution 0.763ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X34Y51 FDCE 0.000 0.000 r design_1_i/EnemyController_0/inst/enemies_reg[23][R][1]/C - SLICE_X34Y51 FDCE (Prop_DFF_SLICEM_C_Q) - 0.078 0.078 f design_1_i/EnemyController_0/inst/enemies_reg[23][R][1]/Q - net (fo=9, routed) 0.649 0.727 design_1_i/ImgGen_0/inst/enemyY[23]4/A[1] - DSP48E2_X3Y22 DSP_A_B_DATA (Prop_DSP_A_B_DATA_DSP48E2_A[1]_A2_DATA[1]) - 0.192 0.919 r design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_A_B_DATA_INST/A2_DATA[1] - net (fo=1, routed) 0.000 0.919 design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_A_B_DATA.A2_DATA<1> - DSP48E2_X3Y22 DSP_PREADD_DATA (Prop_DSP_PREADD_DATA_DSP48E2_A2_DATA[1]_A2A1[1]) - 0.076 0.995 r design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_PREADD_DATA_INST/A2A1[1] - net (fo=1, routed) 0.000 0.995 design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_PREADD_DATA.A2A1<1> - DSP48E2_X3Y22 DSP_MULTIPLIER (Prop_DSP_MULTIPLIER_DSP48E2_A2A1[1]_U[1]) - 0.505 1.500 f design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_MULTIPLIER_INST/U[1] - net (fo=1, routed) 0.000 1.500 design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_MULTIPLIER.U<1> - DSP48E2_X3Y22 DSP_M_DATA (Prop_DSP_M_DATA_DSP48E2_U[1]_U_DATA[1]) - 0.047 1.547 r design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_M_DATA_INST/U_DATA[1] - net (fo=1, routed) 0.000 1.547 design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_M_DATA.U_DATA<1> - DSP48E2_X3Y22 DSP_ALU (Prop_DSP_ALU_DSP48E2_U_DATA[1]_ALU_OUT[1]) - 0.585 2.132 r design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_ALU_INST/ALU_OUT[1] - net (fo=1, routed) 0.000 2.132 design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_ALU.ALU_OUT<1> - DSP48E2_X3Y22 DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_ALU_OUT[1]_P[1]) - 0.109 2.241 f design_1_i/ImgGen_0/inst/enemyY[23]4/DSP_OUTPUT_INST/P[1] - net (fo=1, routed) 0.694 2.935 design_1_i/ImgGen_0/inst/enemyY[23]4_n_104 - SLICE_X31Y55 LUT1 (Prop_A6LUT_SLICEM_I0_O) - 0.100 3.035 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6242/O - net (fo=1, routed) 0.013 3.048 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6242_n_0 - SLICE_X31Y55 CARRY8 (Prop_CARRY8_SLICEM_S[0]_O[7]) - 0.241 3.289 f design_1_i/ImgGen_0/inst/R[7]_INST_0_i_4812/O[7] - net (fo=4, routed) 0.401 3.690 design_1_i/ImgGen_0/inst/enemyY[23]4__0[8] - SLICE_X24Y57 LUT3 (Prop_B5LUT_SLICEM_I2_O) - 0.143 3.833 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6221/O - net (fo=2, routed) 0.468 4.301 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6221_n_0 - SLICE_X30Y56 CARRY8 (Prop_CARRY8_SLICEL_CI_CO[7]) - 0.151 4.452 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_7103/CO[7] - net (fo=1, routed) 0.026 4.478 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_7103_n_0 - SLICE_X30Y57 CARRY8 (Prop_CARRY8_SLICEL_CI_O[7]) - 0.116 4.594 f design_1_i/ImgGen_0/inst/R[7]_INST_0_i_7493/O[7] - net (fo=1, routed) 0.220 4.814 design_1_i/ImgGen_0/inst/enemyY[23]2[16] - SLICE_X29Y57 LUT2 (Prop_H6LUT_SLICEM_I1_O) - 0.152 4.966 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_7113/O - net (fo=1, routed) 0.015 4.981 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_7113_n_0 - SLICE_X29Y57 CARRY8 (Prop_CARRY8_SLICEM_S[7]_CO[7]) - 0.117 5.098 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6251/CO[7] - net (fo=1, routed) 0.026 5.124 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6251_n_0 - SLICE_X29Y58 CARRY8 (Prop_CARRY8_SLICEM_CI_O[5]) - 0.116 5.240 f design_1_i/ImgGen_0/inst/R[7]_INST_0_i_6243/O[5] - net (fo=3, routed) 0.292 5.532 design_1_i/ImgGen_0/inst/enemyY[23]0[22] - SLICE_X27Y58 LUT2 (Prop_E6LUT_SLICEL_I1_O) - 0.147 5.679 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_4824/O - net (fo=1, routed) 0.007 5.686 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_4824_n_0 - SLICE_X27Y58 CARRY8 (Prop_CARRY8_SLICEL_S[4]_CO[7]) - 0.153 5.839 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_3170/CO[7] - net (fo=1, routed) 0.026 5.865 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_3170_n_0 - SLICE_X27Y59 CARRY8 (Prop_CARRY8_SLICEL_CI_O[5]) - 0.116 5.981 f design_1_i/ImgGen_0/inst/R[7]_INST_0_i_1695/O[5] - net (fo=2, routed) 0.248 6.229 design_1_i/ImgGen_0/inst/R4__0[31] - SLICE_X26Y58 LUT2 (Prop_H6LUT_SLICEL_I0_O) - 0.099 6.328 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_1696/O - net (fo=1, routed) 0.010 6.338 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_1696_n_0 - SLICE_X26Y58 CARRY8 (Prop_CARRY8_SLICEL_S[7]_CO[7]) - 0.122 6.460 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_737/CO[7] - net (fo=1, routed) 0.504 6.964 design_1_i/ImgGen_0/inst/R3 - SLICE_X35Y52 LUT5 (Prop_H6LUT_SLICEL_I1_O) - 0.150 7.114 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_239/O - net (fo=1, routed) 0.348 7.462 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_239_n_0 - SLICE_X35Y36 LUT6 (Prop_H6LUT_SLICEL_I5_O) - 0.124 7.586 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_53/O - net (fo=1, routed) 0.437 8.023 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_53_n_0 - SLICE_X22Y29 LUT4 (Prop_G6LUT_SLICEL_I1_O) - 0.149 8.172 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_15/O - net (fo=1, routed) 0.192 8.364 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_15_n_0 - SLICE_X23Y28 LUT6 (Prop_H6LUT_SLICEL_I4_O) - 0.099 8.463 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_3/O - net (fo=6, routed) 0.474 8.938 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_3_n_0 - SLICE_X30Y7 LUT6 (Prop_B6LUT_SLICEL_I5_O) - 0.148 9.086 r design_1_i/ImgGen_0/inst/R[4]_INST_0/O - net (fo=1, routed) 0.049 9.135 design_1_i/HDMI_TX_0/U0/i_wrap/R[4] - SLICE_X30Y7 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[4]/D - ------------------------------------------------------------------- ------------------- - - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.519 0.598 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.638 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.638 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.333 0.971 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - 0.630 1.601 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.214 1.815 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.024 1.839 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.826 3.665 design_1_i/HDMI_TX_0/U0/i_wrap/pxClk - SLICE_X30Y7 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[4]/C - -Slack: inf - Source: PL_USER_PB0 - (input port) - Destination: design_1_i/angle_encoder_1/inst/rot_l_delayed_reg/CE - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 3.058ns (logic 0.642ns (20.997%) route 2.416ns (79.003%)) - Logic Levels: 3 (IBUFCTRL=1 INBUF=1 LUT1=1) - Clock Path Skew: 3.612ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 3.612ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.163ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.085ns - Clock Net Delay (Destination): 1.773ns (routing 1.063ns, distribution 0.710ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - AB6 0.000 0.000 f PL_USER_PB0 (IN) - net (fo=0) 0.000 0.000 PL_USER_PB0_IBUF_inst/I - AB6 INBUF (Prop_INBUF_HPIOB_M_PAD_O) - 0.592 0.592 f PL_USER_PB0_IBUF_inst/INBUF_INST/O - net (fo=1, routed) 0.000 0.592 PL_USER_PB0_IBUF_inst/OUT - AB6 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.592 f PL_USER_PB0_IBUF_inst/IBUFCTRL_INST/O - net (fo=283, routed) 2.242 2.834 design_1_i/angle_encoder_1/inst/RST - SLICE_X22Y3 LUT1 (Prop_C6LUT_SLICEL_I0_O) - 0.050 2.884 r design_1_i/angle_encoder_1/inst/rot_l_delayed_i_1/O - net (fo=2, routed) 0.174 3.058 design_1_i/angle_encoder_1/inst/rot_l_delayed_i_1_n_0 - SLICE_X22Y3 FDRE r design_1_i/angle_encoder_1/inst/rot_l_delayed_reg/CE - ------------------------------------------------------------------- ------------------- - - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.519 0.598 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.638 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.638 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.333 0.971 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - 0.630 1.601 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.214 1.815 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.024 1.839 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.773 3.612 design_1_i/angle_encoder_1/inst/CLK - SLICE_X22Y3 FDRE r design_1_i/angle_encoder_1/inst/rot_l_delayed_reg/C - -Slack: inf - Source: PL_USER_PB0 - (input port) - Destination: design_1_i/angle_encoder_1/inst/rot_r_delayed_reg/CE - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 3.058ns (logic 0.642ns (20.997%) route 2.416ns (79.003%)) - Logic Levels: 3 (IBUFCTRL=1 INBUF=1 LUT1=1) - Clock Path Skew: 3.612ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 3.612ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.163ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.085ns - Clock Net Delay (Destination): 1.773ns (routing 1.063ns, distribution 0.710ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - AB6 0.000 0.000 f PL_USER_PB0 (IN) - net (fo=0) 0.000 0.000 PL_USER_PB0_IBUF_inst/I - AB6 INBUF (Prop_INBUF_HPIOB_M_PAD_O) - 0.592 0.592 f PL_USER_PB0_IBUF_inst/INBUF_INST/O - net (fo=1, routed) 0.000 0.592 PL_USER_PB0_IBUF_inst/OUT - AB6 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.592 f PL_USER_PB0_IBUF_inst/IBUFCTRL_INST/O - net (fo=283, routed) 2.242 2.834 design_1_i/angle_encoder_1/inst/RST - SLICE_X22Y3 LUT1 (Prop_C6LUT_SLICEL_I0_O) - 0.050 2.884 r design_1_i/angle_encoder_1/inst/rot_l_delayed_i_1/O - net (fo=2, routed) 0.174 3.058 design_1_i/angle_encoder_1/inst/rot_l_delayed_i_1_n_0 - SLICE_X22Y3 FDRE r design_1_i/angle_encoder_1/inst/rot_r_delayed_reg/CE - ------------------------------------------------------------------- ------------------- - - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.079 0.079 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.519 0.598 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.040 0.638 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.638 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.333 0.971 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - 0.630 1.601 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.214 1.815 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.024 1.839 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.773 3.612 design_1_i/angle_encoder_1/inst/CLK - SLICE_X22Y3 FDRE r design_1_i/angle_encoder_1/inst/rot_r_delayed_reg/C - - - - - -Min Delay Paths --------------------------------------------------------------------------------------- -Slack: inf - Source: design_1_i/EnemyController_0/inst/hited_reg/C - (rising edge-triggered cell FDCE) - Destination: design_1_i/GameController_0/inst/health_reg_reg[0]/CE - (rising edge-triggered cell FDPE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 0.488ns (logic 0.039ns (7.986%) route 0.449ns (92.014%)) - Logic Levels: 1 (FDCE=1) - Clock Uncertainty: 0.163ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.085ns - Clock Net Delay (Destination): 1.337ns (routing 0.716ns, distribution 0.621ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X27Y30 FDCE 0.000 0.000 r design_1_i/EnemyController_0/inst/hited_reg/C - SLICE_X27Y30 FDCE (Prop_CFF_SLICEL_C_Q) - 0.039 0.039 r design_1_i/EnemyController_0/inst/hited_reg/Q - net (fo=3, routed) 0.449 0.488 design_1_i/GameController_0/inst/hit - SLICE_X48Y31 FDPE r design_1_i/GameController_0/inst/health_reg_reg[0]/CE - ------------------------------------------------------------------- ------------------- - - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.400 0.500 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.550 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.550 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.222 0.772 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - -0.295 0.477 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.165 0.642 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.019 0.661 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.337 1.998 design_1_i/GameController_0/inst/Clk - SLICE_X48Y31 FDPE r design_1_i/GameController_0/inst/health_reg_reg[0]/C - -Slack: inf - Source: design_1_i/EnemyController_0/inst/hited_reg/C - (rising edge-triggered cell FDCE) - Destination: design_1_i/GameController_0/inst/health_reg_reg[1]/CE - (rising edge-triggered cell FDPE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 0.488ns (logic 0.039ns (7.986%) route 0.449ns (92.014%)) - Logic Levels: 1 (FDCE=1) - Clock Uncertainty: 0.163ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.085ns - Clock Net Delay (Destination): 1.337ns (routing 0.716ns, distribution 0.621ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X27Y30 FDCE 0.000 0.000 r design_1_i/EnemyController_0/inst/hited_reg/C - SLICE_X27Y30 FDCE (Prop_CFF_SLICEL_C_Q) - 0.039 0.039 r design_1_i/EnemyController_0/inst/hited_reg/Q - net (fo=3, routed) 0.449 0.488 design_1_i/GameController_0/inst/hit - SLICE_X48Y31 FDPE r design_1_i/GameController_0/inst/health_reg_reg[1]/CE - ------------------------------------------------------------------- ------------------- - - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.400 0.500 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.550 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.550 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.222 0.772 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - -0.295 0.477 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.165 0.642 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.019 0.661 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.337 1.998 design_1_i/GameController_0/inst/Clk - SLICE_X48Y31 FDPE r design_1_i/GameController_0/inst/health_reg_reg[1]/C - -Slack: inf - Source: design_1_i/EnemyController_0/inst/hited_reg/C - (rising edge-triggered cell FDCE) - Destination: design_1_i/GameController_0/inst/health_reg_reg[2]/CE - (rising edge-triggered cell FDCE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 0.488ns (logic 0.039ns (7.986%) route 0.449ns (92.014%)) - Logic Levels: 1 (FDCE=1) - Clock Uncertainty: 0.163ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.085ns - Clock Net Delay (Destination): 1.337ns (routing 0.716ns, distribution 0.621ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X27Y30 FDCE 0.000 0.000 r design_1_i/EnemyController_0/inst/hited_reg/C - SLICE_X27Y30 FDCE (Prop_CFF_SLICEL_C_Q) - 0.039 0.039 r design_1_i/EnemyController_0/inst/hited_reg/Q - net (fo=3, routed) 0.449 0.488 design_1_i/GameController_0/inst/hit - SLICE_X48Y31 FDCE r design_1_i/GameController_0/inst/health_reg_reg[2]/CE - ------------------------------------------------------------------- ------------------- - - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.400 0.500 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.550 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.550 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.222 0.772 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - -0.295 0.477 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.165 0.642 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.019 0.661 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.337 1.998 design_1_i/GameController_0/inst/Clk - SLICE_X48Y31 FDCE r design_1_i/GameController_0/inst/health_reg_reg[2]/C - -Slack: inf - Source: design_1_i/EnemyController_0/inst/enemies_reg[20][is_active]/C - (rising edge-triggered cell FDCE) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[4]/D - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 0.746ns (logic 0.145ns (19.441%) route 0.601ns (80.559%)) - Logic Levels: 4 (FDCE=1 LUT6=3) - Clock Uncertainty: 0.163ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.085ns - Clock Net Delay (Destination): 1.283ns (routing 0.716ns, distribution 0.567ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X19Y52 FDCE 0.000 0.000 r design_1_i/EnemyController_0/inst/enemies_reg[20][is_active]/C - SLICE_X19Y52 FDCE (Prop_HFF2_SLICEM_C_Q) - 0.039 0.039 r design_1_i/EnemyController_0/inst/enemies_reg[20][is_active]/Q - net (fo=159, routed) 0.102 0.141 design_1_i/ImgGen_0/inst/Enemies_in[230] - SLICE_X19Y55 LUT6 (Prop_H6LUT_SLICEM_I4_O) - 0.023 0.164 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_11/O - net (fo=1, routed) 0.240 0.404 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_11_n_0 - SLICE_X23Y28 LUT6 (Prop_H6LUT_SLICEL_I0_O) - 0.023 0.427 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_3/O - net (fo=6, routed) 0.244 0.671 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_3_n_0 - SLICE_X30Y7 LUT6 (Prop_B6LUT_SLICEL_I5_O) - 0.060 0.731 r design_1_i/ImgGen_0/inst/R[4]_INST_0/O - net (fo=1, routed) 0.015 0.746 design_1_i/HDMI_TX_0/U0/i_wrap/R[4] - SLICE_X30Y7 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[4]/D - ------------------------------------------------------------------- ------------------- - - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.400 0.500 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.550 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.550 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.222 0.772 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - -0.295 0.477 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.165 0.642 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.019 0.661 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.283 1.944 design_1_i/HDMI_TX_0/U0/i_wrap/pxClk - SLICE_X30Y7 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[4]/C - -Slack: inf - Source: design_1_i/EnemyController_0/inst/enemies_reg[20][is_active]/C - (rising edge-triggered cell FDCE) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[6]/D - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 0.762ns (logic 0.135ns (17.720%) route 0.627ns (82.280%)) - Logic Levels: 4 (FDCE=1 LUT6=3) - Clock Uncertainty: 0.163ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.085ns - Clock Net Delay (Destination): 1.288ns (routing 0.716ns, distribution 0.572ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X19Y52 FDCE 0.000 0.000 r design_1_i/EnemyController_0/inst/enemies_reg[20][is_active]/C - SLICE_X19Y52 FDCE (Prop_HFF2_SLICEM_C_Q) - 0.039 0.039 r design_1_i/EnemyController_0/inst/enemies_reg[20][is_active]/Q - net (fo=159, routed) 0.102 0.141 design_1_i/ImgGen_0/inst/Enemies_in[230] - SLICE_X19Y55 LUT6 (Prop_H6LUT_SLICEM_I4_O) - 0.023 0.164 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_11/O - net (fo=1, routed) 0.240 0.404 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_11_n_0 - SLICE_X23Y28 LUT6 (Prop_H6LUT_SLICEL_I0_O) - 0.023 0.427 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_3/O - net (fo=6, routed) 0.261 0.688 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_3_n_0 - SLICE_X29Y7 LUT6 (Prop_C6LUT_SLICEM_I5_O) - 0.050 0.738 r design_1_i/ImgGen_0/inst/R[6]_INST_0/O - net (fo=1, routed) 0.024 0.762 design_1_i/HDMI_TX_0/U0/i_wrap/R[6] - SLICE_X29Y7 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.400 0.500 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.550 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.550 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.222 0.772 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - -0.295 0.477 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.165 0.642 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.019 0.661 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.288 1.949 design_1_i/HDMI_TX_0/U0/i_wrap/pxClk - SLICE_X29Y7 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[6]/C - -Slack: inf - Source: design_1_i/EnemyController_0/inst/enemies_reg[20][is_active]/C - (rising edge-triggered cell FDCE) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[1]/D - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 0.855ns (logic 0.126ns (14.737%) route 0.729ns (85.263%)) - Logic Levels: 4 (FDCE=1 LUT6=3) - Clock Uncertainty: 0.163ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.085ns - Clock Net Delay (Destination): 1.281ns (routing 0.716ns, distribution 0.565ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X19Y52 FDCE 0.000 0.000 r design_1_i/EnemyController_0/inst/enemies_reg[20][is_active]/C - SLICE_X19Y52 FDCE (Prop_HFF2_SLICEM_C_Q) - 0.039 0.039 r design_1_i/EnemyController_0/inst/enemies_reg[20][is_active]/Q - net (fo=159, routed) 0.102 0.141 design_1_i/ImgGen_0/inst/Enemies_in[230] - SLICE_X19Y55 LUT6 (Prop_H6LUT_SLICEM_I4_O) - 0.023 0.164 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_11/O - net (fo=1, routed) 0.240 0.404 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_11_n_0 - SLICE_X23Y28 LUT6 (Prop_H6LUT_SLICEL_I0_O) - 0.023 0.427 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_3/O - net (fo=6, routed) 0.371 0.798 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_3_n_0 - SLICE_X32Y9 LUT6 (Prop_D6LUT_SLICEL_I5_O) - 0.041 0.839 r design_1_i/ImgGen_0/inst/R[1]_INST_0/O - net (fo=1, routed) 0.016 0.855 design_1_i/HDMI_TX_0/U0/i_wrap/R[1] - SLICE_X32Y9 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.400 0.500 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.550 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.550 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.222 0.772 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - -0.295 0.477 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.165 0.642 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.019 0.661 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.281 1.942 design_1_i/HDMI_TX_0/U0/i_wrap/pxClk - SLICE_X32Y9 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[1]/C - -Slack: inf - Source: design_1_i/EnemyController_0/inst/enemies_reg[20][is_active]/C - (rising edge-triggered cell FDCE) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[2]/D - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 0.872ns (logic 0.134ns (15.365%) route 0.738ns (84.635%)) - Logic Levels: 5 (FDCE=1 LUT2=1 LUT6=3) - Clock Uncertainty: 0.163ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.085ns - Clock Net Delay (Destination): 1.307ns (routing 0.716ns, distribution 0.591ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X19Y52 FDCE 0.000 0.000 r design_1_i/EnemyController_0/inst/enemies_reg[20][is_active]/C - SLICE_X19Y52 FDCE (Prop_HFF2_SLICEM_C_Q) - 0.039 0.039 r design_1_i/EnemyController_0/inst/enemies_reg[20][is_active]/Q - net (fo=159, routed) 0.102 0.141 design_1_i/ImgGen_0/inst/Enemies_in[230] - SLICE_X19Y55 LUT6 (Prop_H6LUT_SLICEM_I4_O) - 0.023 0.164 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_11/O - net (fo=1, routed) 0.240 0.404 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_11_n_0 - SLICE_X23Y28 LUT6 (Prop_H6LUT_SLICEL_I0_O) - 0.023 0.427 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_3/O - net (fo=6, routed) 0.351 0.778 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_3_n_0 - SLICE_X36Y9 LUT2 (Prop_A6LUT_SLICEL_I0_O) - 0.035 0.813 r design_1_i/ImgGen_0/inst/R[5]_INST_0_i_4/O - net (fo=2, routed) 0.028 0.841 design_1_i/ImgGen_0/inst/R[5]_INST_0_i_4_n_0 - SLICE_X36Y9 LUT6 (Prop_C6LUT_SLICEL_I5_O) - 0.014 0.855 r design_1_i/ImgGen_0/inst/R[2]_INST_0/O - net (fo=1, routed) 0.017 0.872 design_1_i/HDMI_TX_0/U0/i_wrap/R[2] - SLICE_X36Y9 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.400 0.500 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.550 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.550 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.222 0.772 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - -0.295 0.477 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.165 0.642 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.019 0.661 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.307 1.968 design_1_i/HDMI_TX_0/U0/i_wrap/pxClk - SLICE_X36Y9 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[2]/C - -Slack: inf - Source: design_1_i/EnemyController_0/inst/enemies_reg[20][is_active]/C - (rising edge-triggered cell FDCE) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[7]/D - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 0.911ns (logic 0.117ns (12.837%) route 0.794ns (87.163%)) - Logic Levels: 4 (FDCE=1 LUT3=1 LUT6=2) - Clock Uncertainty: 0.163ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.085ns - Clock Net Delay (Destination): 1.311ns (routing 0.716ns, distribution 0.595ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X19Y52 FDCE 0.000 0.000 r design_1_i/EnemyController_0/inst/enemies_reg[20][is_active]/C - SLICE_X19Y52 FDCE (Prop_HFF2_SLICEM_C_Q) - 0.039 0.039 r design_1_i/EnemyController_0/inst/enemies_reg[20][is_active]/Q - net (fo=159, routed) 0.102 0.141 design_1_i/ImgGen_0/inst/Enemies_in[230] - SLICE_X19Y55 LUT6 (Prop_H6LUT_SLICEM_I4_O) - 0.023 0.164 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_11/O - net (fo=1, routed) 0.240 0.404 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_11_n_0 - SLICE_X23Y28 LUT6 (Prop_H6LUT_SLICEL_I0_O) - 0.023 0.427 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_3/O - net (fo=6, routed) 0.351 0.778 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_3_n_0 - SLICE_X36Y9 LUT3 (Prop_A5LUT_SLICEL_I2_O) - 0.032 0.810 r design_1_i/ImgGen_0/inst/R[7]_INST_0/O - net (fo=1, routed) 0.101 0.911 design_1_i/HDMI_TX_0/U0/i_wrap/R[7] - SLICE_X36Y9 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[7]/D - ------------------------------------------------------------------- ------------------- - - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.400 0.500 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.550 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.550 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.222 0.772 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - -0.295 0.477 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.165 0.642 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.019 0.661 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.311 1.972 design_1_i/HDMI_TX_0/U0/i_wrap/pxClk - SLICE_X36Y9 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[7]/C - -Slack: inf - Source: design_1_i/EnemyController_0/inst/enemies_reg[20][is_active]/C - (rising edge-triggered cell FDCE) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[5]/D - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 0.939ns (logic 0.134ns (14.278%) route 0.805ns (85.722%)) - Logic Levels: 5 (FDCE=1 LUT2=1 LUT6=3) - Clock Uncertainty: 0.163ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.085ns - Clock Net Delay (Destination): 1.291ns (routing 0.716ns, distribution 0.575ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X19Y52 FDCE 0.000 0.000 r design_1_i/EnemyController_0/inst/enemies_reg[20][is_active]/C - SLICE_X19Y52 FDCE (Prop_HFF2_SLICEM_C_Q) - 0.039 0.039 r design_1_i/EnemyController_0/inst/enemies_reg[20][is_active]/Q - net (fo=159, routed) 0.102 0.141 design_1_i/ImgGen_0/inst/Enemies_in[230] - SLICE_X19Y55 LUT6 (Prop_H6LUT_SLICEM_I4_O) - 0.023 0.164 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_11/O - net (fo=1, routed) 0.240 0.404 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_11_n_0 - SLICE_X23Y28 LUT6 (Prop_H6LUT_SLICEL_I0_O) - 0.023 0.427 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_3/O - net (fo=6, routed) 0.351 0.778 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_3_n_0 - SLICE_X36Y9 LUT2 (Prop_A6LUT_SLICEL_I0_O) - 0.035 0.813 r design_1_i/ImgGen_0/inst/R[5]_INST_0_i_4/O - net (fo=2, routed) 0.095 0.909 design_1_i/ImgGen_0/inst/R[5]_INST_0_i_4_n_0 - SLICE_X35Y10 LUT6 (Prop_D6LUT_SLICEL_I5_O) - 0.014 0.923 r design_1_i/ImgGen_0/inst/R[5]_INST_0/O - net (fo=1, routed) 0.016 0.939 design_1_i/HDMI_TX_0/U0/i_wrap/R[5] - SLICE_X35Y10 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[5]/D - ------------------------------------------------------------------- ------------------- - - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.400 0.500 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.550 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.550 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.222 0.772 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - -0.295 0.477 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.165 0.642 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.019 0.661 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.291 1.952 design_1_i/HDMI_TX_0/U0/i_wrap/pxClk - SLICE_X35Y10 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[5]/C - -Slack: inf - Source: design_1_i/EnemyController_0/inst/enemies_reg[20][is_active]/C - (rising edge-triggered cell FDCE) - Destination: design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[0]/D - (rising edge-triggered cell FDRE clocked by clk25_design_1_clk_wiz_0_0 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 1.127ns (logic 0.107ns (9.498%) route 1.020ns (90.502%)) - Logic Levels: 4 (FDCE=1 LUT6=3) - Clock Uncertainty: 0.163ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.148ns - Phase Error (PE): 0.085ns - Clock Net Delay (Destination): 1.307ns (routing 0.716ns, distribution 0.591ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X19Y52 FDCE 0.000 0.000 r design_1_i/EnemyController_0/inst/enemies_reg[20][is_active]/C - SLICE_X19Y52 FDCE (Prop_HFF2_SLICEM_C_Q) - 0.039 0.039 r design_1_i/EnemyController_0/inst/enemies_reg[20][is_active]/Q - net (fo=159, routed) 0.102 0.141 design_1_i/ImgGen_0/inst/Enemies_in[230] - SLICE_X19Y55 LUT6 (Prop_H6LUT_SLICEM_I4_O) - 0.023 0.164 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_11/O - net (fo=1, routed) 0.240 0.404 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_11_n_0 - SLICE_X23Y28 LUT6 (Prop_H6LUT_SLICEL_I0_O) - 0.023 0.427 r design_1_i/ImgGen_0/inst/R[7]_INST_0_i_3/O - net (fo=6, routed) 0.421 0.849 design_1_i/ImgGen_0/inst/R[7]_INST_0_i_3_n_0 - SLICE_X30Y10 LUT6 (Prop_G6LUT_SLICEL_I5_O) - 0.022 0.871 r design_1_i/ImgGen_0/inst/R[0]_INST_0/O - net (fo=2, routed) 0.256 1.127 design_1_i/HDMI_TX_0/U0/i_wrap/R[0] - SLICE_X36Y6 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock clk25_design_1_clk_wiz_0_0 rise edge) - 0.000 0.000 r - D7 0.000 0.000 r clk_100mhz_clk_p (IN) - net (fo=0) 0.100 0.100 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I - HPIOBDIFFINBUF_X0Y60 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O) - 0.400 0.500 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O - net (fo=1, routed) 0.050 0.550 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT - D7 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O) - 0.000 0.550 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O - net (fo=1, routed) 0.222 0.772 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0 - MMCM_X0Y2 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0) - -0.295 0.477 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0 - net (fo=1, routed) 0.165 0.642 design_1_i/clk_wiz_0/inst/clk25_design_1_clk_wiz_0_0 - BUFGCE_X0Y68 BUFGCE (Prop_BUFCE_BUFGCE_I_O) - 0.019 0.661 r design_1_i/clk_wiz_0/inst/clkout1_buf/O - X0Y0 (CLOCK_ROOT) net (fo=99, routed) 1.307 1.968 design_1_i/HDMI_TX_0/U0/i_wrap/pxClk - SLICE_X36Y6 FDRE r design_1_i/HDMI_TX_0/U0/i_wrap/TMDS_2/i_Enc/qD_reg[0]/C - - - - - diff --git a/SW2.runs/impl_1/design_1_wrapper_timing_summary_routed.rpx b/SW2.runs/impl_1/design_1_wrapper_timing_summary_routed.rpx deleted file mode 100644 index 26b6dcf..0000000 Binary files a/SW2.runs/impl_1/design_1_wrapper_timing_summary_routed.rpx and /dev/null differ diff --git a/SW2.runs/impl_1/design_1_wrapper_utilization_placed.pb b/SW2.runs/impl_1/design_1_wrapper_utilization_placed.pb deleted file mode 100644 index 8b0cf6e..0000000 Binary files a/SW2.runs/impl_1/design_1_wrapper_utilization_placed.pb and /dev/null differ diff --git a/SW2.runs/impl_1/design_1_wrapper_utilization_placed.rpt b/SW2.runs/impl_1/design_1_wrapper_utilization_placed.rpt deleted file mode 100644 index 4bcf240..0000000 --- a/SW2.runs/impl_1/design_1_wrapper_utilization_placed.rpt +++ /dev/null @@ -1,257 +0,0 @@ -Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. ---------------------------------------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2025.1 (win64) Build 6140274 Thu May 22 00:12:29 MDT 2025 -| Date : Tue Jun 9 14:07:42 2026 -| Host : Lab016-04 running 64-bit major release (build 9200) -| Command : report_utilization -file design_1_wrapper_utilization_placed.rpt -pb design_1_wrapper_utilization_placed.pb -| Design : design_1_wrapper -| Device : xczu3eg-sfvc784-2-e -| Speed File : -2 -| Design State : Fully Placed ---------------------------------------------------------------------------------------------------------------------------------------------- - -Utilization Design Information - -Table of Contents ------------------ -1. CLB Logic -1.1 Summary of Registers by Type -2. CLB Logic Distribution -3. BLOCKRAM -4. ARITHMETIC -5. I/O -6. CLOCK -7. ADVANCED -8. CONFIGURATION -9. Primitives -10. Black Boxes -11. Instantiated Netlists - -1. CLB Logic ------------- - -+-------------------------+------+-------+------------+-----------+-------+ -| Site Type | Used | Fixed | Prohibited | Available | Util% | -+-------------------------+------+-------+------------+-----------+-------+ -| CLB LUTs | 7211 | 0 | 0 | 70560 | 10.22 | -| LUT as Logic | 7211 | 0 | 0 | 70560 | 10.22 | -| LUT as Memory | 0 | 0 | 0 | 28800 | 0.00 | -| CLB Registers | 401 | 0 | 0 | 141120 | 0.28 | -| Register as Flip Flop | 401 | 0 | 0 | 141120 | 0.28 | -| Register as Latch | 0 | 0 | 0 | 141120 | 0.00 | -| CARRY8 | 763 | 0 | 0 | 8820 | 8.65 | -| F7 Muxes | 18 | 0 | 0 | 35280 | 0.05 | -| F8 Muxes | 1 | 0 | 0 | 17640 | <0.01 | -| F9 Muxes | 0 | 0 | 0 | 8820 | 0.00 | -+-------------------------+------+-------+------------+-----------+-------+ -* Warning! LUT value is adjusted to account for LUT combining. - - -1.1 Summary of Registers by Type --------------------------------- - -+-------+--------------+-------------+--------------+ -| Total | Clock Enable | Synchronous | Asynchronous | -+-------+--------------+-------------+--------------+ -| 0 | _ | - | - | -| 0 | _ | - | Set | -| 0 | _ | - | Reset | -| 0 | _ | Set | - | -| 0 | _ | Reset | - | -| 0 | Yes | - | - | -| 10 | Yes | - | Set | -| 270 | Yes | - | Reset | -| 0 | Yes | Set | - | -| 121 | Yes | Reset | - | -+-------+--------------+-------------+--------------+ - - -2. CLB Logic Distribution -------------------------- - -+--------------------------------------------+------+-------+------------+-----------+-------+ -| Site Type | Used | Fixed | Prohibited | Available | Util% | -+--------------------------------------------+------+-------+------------+-----------+-------+ -| CLB | 1147 | 0 | 0 | 8820 | 13.00 | -| CLBL | 691 | 0 | | | | -| CLBM | 456 | 0 | | | | -| LUT as Logic | 7211 | 0 | 0 | 70560 | 10.22 | -| using O5 output only | 52 | | | | | -| using O6 output only | 5585 | | | | | -| using O5 and O6 | 1574 | | | | | -| LUT as Memory | 0 | 0 | 0 | 28800 | 0.00 | -| LUT as Distributed RAM | 0 | 0 | | | | -| using O5 output only | 0 | | | | | -| using O6 output only | 0 | | | | | -| using O5 and O6 | 0 | | | | | -| LUT as Shift Register | 0 | 0 | | | | -| using O5 output only | 0 | | | | | -| using O6 output only | 0 | | | | | -| using O5 and O6 | 0 | | | | | -| CLB Registers | 401 | 0 | 0 | 141120 | 0.28 | -| Register driven from within the CLB | 346 | | | | | -| Register driven from outside the CLB | 55 | | | | | -| LUT in front of the register is unused | 40 | | | | | -| LUT in front of the register is used | 15 | | | | | -| Unique Control Sets | 39 | | 0 | 17640 | 0.22 | -+--------------------------------------------+------+-------+------------+-----------+-------+ -* * Note: Available Control Sets calculated as Slices * 2, Review the Control Sets Report for more information regarding control sets. - - -3. BLOCKRAM ------------ - -+----------------+------+-------+------------+-----------+-------+ -| Site Type | Used | Fixed | Prohibited | Available | Util% | -+----------------+------+-------+------------+-----------+-------+ -| Block RAM Tile | 0 | 0 | 0 | 216 | 0.00 | -| RAMB36/FIFO* | 0 | 0 | 0 | 216 | 0.00 | -| RAMB18 | 0 | 0 | 0 | 432 | 0.00 | -+----------------+------+-------+------------+-----------+-------+ -* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E2 or one FIFO18E2. However, if a FIFO18E2 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E2 - - -4. ARITHMETIC -------------- - -+----------------+------+-------+------------+-----------+-------+ -| Site Type | Used | Fixed | Prohibited | Available | Util% | -+----------------+------+-------+------------+-----------+-------+ -| DSPs | 38 | 0 | 0 | 360 | 10.56 | -| DSP48E2 only | 38 | | | | | -+----------------+------+-------+------------+-----------+-------+ - - -5. I/O ------- - -+------------------+------+-------+------------+-----------+-------+ -| Site Type | Used | Fixed | Prohibited | Available | Util% | -+------------------+------+-------+------------+-----------+-------+ -| Bonded IOB | 16 | 16 | 0 | 252 | 6.35 | -| HPIOB_M | 3 | 3 | 0 | 72 | 4.17 | -| INPUT | 2 | | | | | -| OUTPUT | 1 | | | | | -| BIDIR | 0 | | | | | -| HPIOB_S | 3 | 3 | 0 | 72 | 4.17 | -| INPUT | 1 | | | | | -| OUTPUT | 2 | | | | | -| BIDIR | 0 | | | | | -| HDIOB_M | 5 | 5 | 0 | 48 | 10.42 | -| INPUT | 1 | | | | | -| OUTPUT | 4 | | | | | -| BIDIR | 0 | | | | | -| HDIOB_S | 5 | 5 | 0 | 48 | 10.42 | -| INPUT | 1 | | | | | -| OUTPUT | 4 | | | | | -| BIDIR | 0 | | | | | -| HPIOB_SNGL | 0 | 0 | 0 | 12 | 0.00 | -| HPIOBDIFFINBUF | 1 | 1 | 0 | 72 | 1.39 | -| DIFFINBUF | 1 | 1 | | | | -| HPIOBDIFFOUTBUF | 0 | 0 | 0 | 72 | 0.00 | -| HDIOBDIFFINBUF | 0 | 0 | 0 | 48 | 0.00 | -| BITSLICE_CONTROL | 0 | 0 | 0 | 24 | 0.00 | -| BITSLICE_RX_TX | 0 | 0 | 0 | 936 | 0.00 | -| BITSLICE_TX | 0 | 0 | 0 | 24 | 0.00 | -| RIU_OR | 0 | 0 | 0 | 12 | 0.00 | -+------------------+------+-------+------------+-----------+-------+ - - -6. CLOCK --------- - -+------------+------+-------+------------+-----------+-------+ -| Site Type | Used | Fixed | Prohibited | Available | Util% | -+------------+------+-------+------------+-----------+-------+ -| BUFGCE | 3 | 0 | 0 | 88 | 3.41 | -| BUFGCE_DIV | 0 | 0 | 0 | 12 | 0.00 | -| BUFG_PS | 0 | 0 | 0 | 72 | 0.00 | -| BUFGCTRL* | 0 | 0 | 0 | 24 | 0.00 | -| PLL | 0 | 0 | 0 | 6 | 0.00 | -| MMCM | 1 | 0 | 0 | 3 | 33.33 | -+------------+------+-------+------------+-----------+-------+ -* Note: Each used BUFGCTRL counts as two GLOBAL CLOCK BUFFERs. This table does not include global clocking resources, only buffer cell usage. See the Clock Utilization Report (report_clock_utilization) for detailed accounting of global clocking resource availability. - - -7. ADVANCED ------------ - -+-----------+------+-------+------------+-----------+-------+ -| Site Type | Used | Fixed | Prohibited | Available | Util% | -+-----------+------+-------+------------+-----------+-------+ -| PS8 | 0 | 0 | 0 | 1 | 0.00 | -| SYSMONE4 | 0 | 0 | 0 | 1 | 0.00 | -+-----------+------+-------+------------+-----------+-------+ - - -8. CONFIGURATION ----------------- - -+-------------+------+-------+------------+-----------+-------+ -| Site Type | Used | Fixed | Prohibited | Available | Util% | -+-------------+------+-------+------------+-----------+-------+ -| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 | -| DNA_PORTE2 | 0 | 0 | 0 | 1 | 0.00 | -| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 | -| FRAME_ECCE4 | 0 | 0 | 0 | 1 | 0.00 | -| ICAPE3 | 0 | 0 | 0 | 2 | 0.00 | -| MASTER_JTAG | 0 | 0 | 0 | 1 | 0.00 | -| STARTUPE3 | 0 | 0 | 0 | 1 | 0.00 | -+-------------+------+-------+------------+-----------+-------+ - - -9. Primitives -------------- - -+------------+------+---------------------+ -| Ref Name | Used | Functional Category | -+------------+------+---------------------+ -| LUT2 | 4052 | CLB | -| LUT6 | 1443 | CLB | -| LUT1 | 1259 | CLB | -| CARRY8 | 763 | CLB | -| LUT4 | 689 | CLB | -| LUT3 | 689 | CLB | -| LUT5 | 653 | CLB | -| FDCE | 270 | Register | -| FDRE | 121 | Register | -| DSP48E2 | 38 | Arithmetic | -| MUXF7 | 18 | CLB | -| OBUF | 11 | I/O | -| FDPE | 10 | Register | -| OSERDESE3 | 8 | I/O | -| IBUFCTRL | 4 | Others | -| INBUF | 3 | I/O | -| BUFGCE | 3 | Clock | -| MUXF8 | 1 | CLB | -| MMCME4_ADV | 1 | Clock | -| DIFFINBUF | 1 | I/O | -+------------+------+---------------------+ - - -10. Black Boxes ---------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - -11. Instantiated Netlists -------------------------- - -+------------------------------+------+ -| Ref Name | Used | -+------------------------------+------+ -| design_1_clk_wiz_0_0 | 1 | -| design_1_angle_encoder_1_0 | 1 | -| design_1_VideoTiming_0_0 | 1 | -| design_1_TickGenerator_0_0 | 1 | -| design_1_RotaryEnc_0_0 | 1 | -| design_1_ImgGen_0_0 | 1 | -| design_1_HDMI_TX_0_0 | 1 | -| design_1_GameController_0_0 | 1 | -| design_1_EnemyController_0_0 | 1 | -+------------------------------+------+ - - diff --git a/SW2.runs/impl_1/dfx_runtime.txt b/SW2.runs/impl_1/dfx_runtime.txt deleted file mode 100644 index 2db32f0..0000000 --- a/SW2.runs/impl_1/dfx_runtime.txt +++ /dev/null @@ -1,2 +0,0 @@ -DFXRuntime Profile Report: -Total Application(DFX) Runtime : CPU : 0:0:34 WALL : 0:0:0 0.00 % diff --git a/SW2.runs/impl_1/gen_run.xml b/SW2.runs/impl_1/gen_run.xml deleted file mode 100644 index a9c6fad..0000000 --- a/SW2.runs/impl_1/gen_run.xml +++ /dev/null @@ -1,238 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/SW2.runs/impl_1/htr.txt b/SW2.runs/impl_1/htr.txt deleted file mode 100644 index 478bbd0..0000000 --- a/SW2.runs/impl_1/htr.txt +++ /dev/null @@ -1,10 +0,0 @@ -REM -REM Vivado(TM) -REM htr.txt: a Vivado-generated description of how-to-repeat the -REM the basic steps of a run. Note that runme.bat/sh needs -REM to be invoked for Vivado to track run status. -REM Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -REM Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. -REM - -vivado -log design_1_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source design_1_wrapper.tcl -notrace diff --git a/SW2.runs/impl_1/init_design.pb b/SW2.runs/impl_1/init_design.pb deleted file mode 100644 index 071c251..0000000 Binary files a/SW2.runs/impl_1/init_design.pb and /dev/null differ diff --git a/SW2.runs/impl_1/opt_design.pb b/SW2.runs/impl_1/opt_design.pb deleted file mode 100644 index 8c23e38..0000000 Binary files a/SW2.runs/impl_1/opt_design.pb and /dev/null differ diff --git a/SW2.runs/impl_1/phys_opt_design.pb b/SW2.runs/impl_1/phys_opt_design.pb deleted file mode 100644 index b35237b..0000000 Binary files a/SW2.runs/impl_1/phys_opt_design.pb and /dev/null differ diff --git a/SW2.runs/impl_1/place_design.pb b/SW2.runs/impl_1/place_design.pb deleted file mode 100644 index ea938a0..0000000 Binary files a/SW2.runs/impl_1/place_design.pb and /dev/null differ diff --git a/SW2.runs/impl_1/route_design.pb b/SW2.runs/impl_1/route_design.pb deleted file mode 100644 index 456c3b7..0000000 Binary files a/SW2.runs/impl_1/route_design.pb and /dev/null differ diff --git a/SW2.runs/impl_1/rundef.js b/SW2.runs/impl_1/rundef.js deleted file mode 100644 index 81a95ac..0000000 --- a/SW2.runs/impl_1/rundef.js +++ /dev/null @@ -1,41 +0,0 @@ -// -// Vivado(TM) -// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 -// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. -// - -var WshShell = new ActiveXObject( "WScript.Shell" ); -var ProcEnv = WshShell.Environment( "Process" ); -var PathVal = ProcEnv("PATH"); -if ( PathVal.length == 0 ) { - PathVal = "C:/Xilinx/2025.1/Vitis/bin;C:/Xilinx/2025.1/Vivado/ids_lite/ISE/bin/nt64;C:/Xilinx/2025.1/Vivado/ids_lite/ISE/lib/nt64;C:/Xilinx/2025.1/Vivado/bin;"; -} else { - PathVal = "C:/Xilinx/2025.1/Vitis/bin;C:/Xilinx/2025.1/Vivado/ids_lite/ISE/bin/nt64;C:/Xilinx/2025.1/Vivado/ids_lite/ISE/lib/nt64;C:/Xilinx/2025.1/Vivado/bin;" + PathVal; -} - -ProcEnv("PATH") = PathVal; - -var RDScrFP = WScript.ScriptFullName; -var RDScrN = WScript.ScriptName; -var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); -var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; -eval( EAInclude(ISEJScriptLib) ); - - -// pre-commands: -ISETouchFile( "init_design", "begin" ); -ISEStep( "vivado", - "-log design_1_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source design_1_wrapper.tcl -notrace" ); - - - - - -function EAInclude( EAInclFilename ) { - var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); - var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); - var EAIFContents = EAInclFile.ReadAll(); - EAInclFile.Close(); - return EAIFContents; -} diff --git a/SW2.runs/impl_1/runme.bat b/SW2.runs/impl_1/runme.bat deleted file mode 100644 index bb72db7..0000000 --- a/SW2.runs/impl_1/runme.bat +++ /dev/null @@ -1,11 +0,0 @@ -@echo off - -rem Vivado (TM) -rem runme.bat: a Vivado-generated Script -rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -rem Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. - - -set HD_SDIR=%~dp0 -cd /d "%HD_SDIR%" -cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/SW2.runs/impl_1/runme.log b/SW2.runs/impl_1/runme.log deleted file mode 100644 index fd21033..0000000 --- a/SW2.runs/impl_1/runme.log +++ /dev/null @@ -1,822 +0,0 @@ - -*** Running vivado - with args -log design_1_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source design_1_wrapper.tcl -notrace - - - -****** Vivado v2025.1 (64-bit) - **** SW Build 6140274 on Thu May 22 00:12:29 MDT 2025 - **** IP Build 6138677 on Thu May 22 03:10:11 MDT 2025 - **** SharedData Build 6139179 on Tue May 20 17:58:58 MDT 2025 - **** Start of session at: Tue Jun 9 14:05:43 2026 - ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. - ** Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. - -Sourcing tcl script 'C:/Users/lab/AppData/Roaming/Xilinx/Vivado/Vivado_init.tcl' -source design_1_wrapper.tcl -notrace -create_project: Time (s): cpu = 00:00:21 ; elapsed = 00:00:05 . Memory (MB): peak = 512.504 ; gain = 232.082 -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Xilinx/IP_Repo'. -WARNING: [IP_Flow 19-3685] Ignored loading user repository 'c:/Xilinx/IP_Repo/OLED_ASCII'. The path is contained within another repository. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/2025.1/Vivado/data/ip'. -Command: link_design -top design_1_wrapper -part xczu3eg-sfvc784-2-e -Design is defaulting to srcset: sources_1 -Design is defaulting to constrset: constrs_1 -INFO: [Device 21-403] Loading part xczu3eg-sfvc784-2-e -INFO: [Project 1-5699] Read binary netlist with skipMacroContent - 1 -INFO: [Project 1-454] Reading design checkpoint 'c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_EnemyController_0_0/design_1_EnemyController_0_0.dcp' for cell 'design_1_i/EnemyController_0' -INFO: [Project 1-454] Reading design checkpoint 'c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_GameController_0_0/design_1_GameController_0_0.dcp' for cell 'design_1_i/GameController_0' -INFO: [Project 1-454] Reading design checkpoint 'c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_HDMI_TX_0_0/design_1_HDMI_TX_0_0.dcp' for cell 'design_1_i/HDMI_TX_0' -INFO: [Project 1-454] Reading design checkpoint 'c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_ImgGen_0_0/design_1_ImgGen_0_0.dcp' for cell 'design_1_i/ImgGen_0' -INFO: [Project 1-454] Reading design checkpoint 'c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_RotaryEnc_0_0/design_1_RotaryEnc_0_0.dcp' for cell 'design_1_i/RotaryEnc_0' -INFO: [Project 1-454] Reading design checkpoint 'c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_TickGenerator_0_0/design_1_TickGenerator_0_0.dcp' for cell 'design_1_i/TickGenerator_0' -INFO: [Project 1-454] Reading design checkpoint 'c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_VideoTiming_0_0/design_1_VideoTiming_0_0.dcp' for cell 'design_1_i/VideoTiming_0' -INFO: [Project 1-454] Reading design checkpoint 'c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_angle_encoder_1_0/design_1_angle_encoder_1_0.dcp' for cell 'design_1_i/angle_encoder_1' -INFO: [Project 1-454] Reading design checkpoint 'c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.dcp' for cell 'design_1_i/clk_wiz_0' -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.073 . Memory (MB): peak = 1480.551 ; gain = 0.000 -INFO: [Netlist 29-17] Analyzing 825 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds -WARNING: [Netlist 29-43] Netlist 'design_1_wrapper' is not ideal for floorplanning, since the cellview 'design_1_ImgGen_0_0_ImgGen' defined in file 'design_1_ImgGen_0_0.edf' contains large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. -INFO: [Project 1-479] Netlist was created with Vivado 2025.1 -INFO: [Project 1-570] Preparing netlist for logic optimization -Parsing XDC File [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0_board.xdc] for cell 'design_1_i/clk_wiz_0/inst' -Finished Parsing XDC File [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0_board.xdc] for cell 'design_1_i/clk_wiz_0/inst' -Parsing XDC File [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.xdc] for cell 'design_1_i/clk_wiz_0/inst' -create_clock: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1480.551 ; gain = 0.000 -INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.xdc:54] -INFO: [Timing 38-2] Deriving generated clocks [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.xdc:54] -get_clocks: Time (s): cpu = 00:00:13 ; elapsed = 00:00:10 . Memory (MB): peak = 2248.008 ; gain = 767.457 -Finished Parsing XDC File [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.xdc] for cell 'design_1_i/clk_wiz_0/inst' -Parsing XDC File [C:/Users/lab/Documents/GitHub/SW2/SW2.srcs/constrs_1/new/mainconstraint.xdc] -Finished Parsing XDC File [C:/Users/lab/Documents/GitHub/SW2/SW2.srcs/constrs_1/new/mainconstraint.xdc] -Parsing XDC File [C:/Users/lab/Documents/GitHub/SW2/SW2.srcs/constrs_1/new/sideconstraint.xdc] -Finished Parsing XDC File [C:/Users/lab/Documents/GitHub/SW2/SW2.srcs/constrs_1/new/sideconstraint.xdc] -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 2248.008 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: - A total of 42 instances were transformed. - DSP48E2 => DSP48E2 (DSP_ALU, DSP_A_B_DATA, DSP_C_DATA, DSP_MULTIPLIER, DSP_M_DATA, DSP_OUTPUT, DSP_PREADD, DSP_PREADD_DATA): 38 instances - IBUF => IBUF (IBUFCTRL, INBUF): 3 instances - IBUFDS => IBUFDS (DIFFINBUF, IBUFCTRL): 1 instance - -22 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. -link_design completed successfully -link_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:26 . Memory (MB): peak = 2248.008 ; gain = 1690.215 -Command: opt_design -Attempting to get a license for feature 'Implementation' and/or device 'xczu3eg' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu3eg' -Running DRC as a precondition to command opt_design - -Starting DRC Task -INFO: [DRC 23-27] Running DRC with 6 threads -INFO: [Project 1-461] DRC finished with 0 Errors -INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.923 . Memory (MB): peak = 2272.395 ; gain = 24.387 - -Starting Cache Timing Information Task -INFO: [Timing 38-35] Done setting XDC timing constraints. -Ending Cache Timing Information Task | Checksum: 24df1c074 - -Time (s): cpu = 00:00:04 ; elapsed = 00:00:00.940 . Memory (MB): peak = 2298.988 ; gain = 26.594 - -Starting Logic Optimization Task - -Phase 1 Initialization - -Phase 1.1 Core Generation And Design Setup -Phase 1.1 Core Generation And Design Setup | Checksum: 24df1c074 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 2711.895 ; gain = 0.000 - -Phase 1.2 Setup Constraints And Sort Netlist -Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 24df1c074 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 2711.895 ; gain = 0.000 -Phase 1 Initialization | Checksum: 24df1c074 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 2711.895 ; gain = 0.000 - -Phase 2 Timer Update And Timing Data Collection - -Phase 2.1 Timer Update -Phase 2.1 Timer Update | Checksum: 24df1c074 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.238 . Memory (MB): peak = 2711.895 ; gain = 0.000 - -Phase 2.2 Timing Data Collection -Phase 2.2 Timing Data Collection | Checksum: 24df1c074 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.258 . Memory (MB): peak = 2711.895 ; gain = 0.000 -Phase 2 Timer Update And Timing Data Collection | Checksum: 24df1c074 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.261 . Memory (MB): peak = 2711.895 ; gain = 0.000 - -Phase 3 Retarget -INFO: [Opt 31-1851] Number of loadless carry chains removed were: 0 -INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0 -INFO: [Opt 31-138] Pushed 5 inverter(s) to 60 load pin(s). -INFO: [Opt 31-49] Retargeted 0 cell(s). -Phase 3 Retarget | Checksum: 134a93b52 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.620 . Memory (MB): peak = 2711.895 ; gain = 0.000 -Retarget | Checksum: 134a93b52 -INFO: [Opt 31-389] Phase Retarget created 103 cells and removed 109 cells - -Phase 4 Constant propagation -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Phase 4 Constant propagation | Checksum: 15768403c - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.722 . Memory (MB): peak = 2711.895 ; gain = 0.000 -Constant propagation | Checksum: 15768403c -INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells - -Phase 5 Sweep -INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 -Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 2711.895 ; gain = 0.000 -INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 -Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 2711.895 ; gain = 0.000 -Phase 5 Sweep | Checksum: 1678a9b00 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.926 . Memory (MB): peak = 2711.895 ; gain = 0.000 -Sweep | Checksum: 1678a9b00 -INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells - -Phase 6 BUFG optimization -INFO: [Opt 31-194] Inserted BUFG design_1_i/TickGenerator_0/inst/FrameTick_BUFG_inst to drive 257 load(s) on clock net design_1_i/TickGenerator_0/inst/FrameTick_BUFGCE -INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets -INFO: [Opt 31-1077] Phase BUFG optimization inserted 0 global clock buffer(s) for CLOCK_LOW_FANOUT. -Phase 6 BUFG optimization | Checksum: d6cd27d7 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2711.895 ; gain = 0.000 -BUFG optimization | Checksum: d6cd27d7 -INFO: [Opt 31-662] Phase BUFG optimization created 1 cells of which 1 are BUFGs and removed 0 cells. - -Phase 7 Shift Register Optimization -INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs -Phase 7 Shift Register Optimization | Checksum: d6cd27d7 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2711.895 ; gain = 0.000 -Shift Register Optimization | Checksum: d6cd27d7 -INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells - -Phase 8 Post Processing Netlist -Phase 8 Post Processing Netlist | Checksum: d6cd27d7 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2711.895 ; gain = 0.000 -Post Processing Netlist | Checksum: d6cd27d7 -INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells - -Phase 9 Finalization - -Phase 9.1 Finalizing Design Cores and Updating Shapes -Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 1b5b5f3a9 - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2711.895 ; gain = 0.000 - -Phase 9.2 Verifying Netlist Connectivity - -Starting Connectivity Check Task - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 2711.895 ; gain = 0.000 -Phase 9.2 Verifying Netlist Connectivity | Checksum: 1b5b5f3a9 - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2711.895 ; gain = 0.000 -Phase 9 Finalization | Checksum: 1b5b5f3a9 - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2711.895 ; gain = 0.000 -Opt_design Change Summary -========================= - - -------------------------------------------------------------------------------------------------------------------------- -| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | -------------------------------------------------------------------------------------------------------------------------- -| Retarget | 103 | 109 | 0 | -| Constant propagation | 0 | 0 | 0 | -| Sweep | 0 | 0 | 0 | -| BUFG optimization | 1 | 0 | 0 | -| Shift Register Optimization | 0 | 0 | 0 | -| Post Processing Netlist | 0 | 0 | 0 | -------------------------------------------------------------------------------------------------------------------------- - - -Ending Logic Optimization Task | Checksum: 1b5b5f3a9 - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2711.895 ; gain = 0.000 - -Starting Power Optimization Task -INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. -Ending Power Optimization Task | Checksum: 1b5b5f3a9 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 2711.895 ; gain = 0.000 - -Starting Final Cleanup Task -Ending Final Cleanup Task | Checksum: 1b5b5f3a9 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 2711.895 ; gain = 0.000 - -Starting Netlist Obfuscation Task -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 2711.895 ; gain = 0.000 -Ending Netlist Obfuscation Task | Checksum: 1b5b5f3a9 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 2711.895 ; gain = 0.000 -INFO: [Common 17-83] Releasing license: Implementation -46 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. -opt_design completed successfully -opt_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:07 . Memory (MB): peak = 2711.895 ; gain = 463.887 -INFO: [Vivado 12-24828] Executing command : report_drc -file design_1_wrapper_drc_opted.rpt -pb design_1_wrapper_drc_opted.pb -rpx design_1_wrapper_drc_opted.rpx -Command: report_drc -file design_1_wrapper_drc_opted.rpt -pb design_1_wrapper_drc_opted.pb -rpx design_1_wrapper_drc_opted.rpx -INFO: [IP_Flow 19-1839] IP Catalog is up to date. -INFO: [DRC 23-27] Running DRC with 6 threads -INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/lab/Documents/GitHub/SW2/SW2.runs/impl_1/design_1_wrapper_drc_opted.rpt. -report_drc completed successfully -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [Timing 38-480] Writing timing data to binary archive. -Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 2722.973 ; gain = 0.000 -Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2722.973 ; gain = 0.000 -Writing XDEF routing. -Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.036 . Memory (MB): peak = 2722.973 ; gain = 0.000 -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.077 . Memory (MB): peak = 2723.781 ; gain = 0.809 -Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2723.781 ; gain = 0.000 -Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 2723.781 ; gain = 0.000 -Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.123 . Memory (MB): peak = 2723.781 ; gain = 0.809 -INFO: [Common 17-1381] The checkpoint 'C:/Users/lab/Documents/GitHub/SW2/SW2.runs/impl_1/design_1_wrapper_opt.dcp' has been generated. -Command: place_design -Attempting to get a license for feature 'Implementation' and/or device 'xczu3eg' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu3eg' -INFO: [Common 17-83] Releasing license: Implementation -INFO: [DRC 23-27] Running DRC with 6 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. -Running DRC as a precondition to command place_design -INFO: [DRC 23-27] Running DRC with 6 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. -INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 6 CPUs - -Starting Placer Task - -Phase 1 Placer Initialization - -Phase 1.1 Placer Initialization Netlist Sorting -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 2811.082 ; gain = 0.000 -Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d46e90ed - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 2811.082 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 2811.082 ; gain = 0.000 - -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 14d29efb1 - -Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 3805.191 ; gain = 994.109 - -Phase 1.3 Build Placer Netlist Model -Phase 1.3 Build Placer Netlist Model | Checksum: 198108b5a - -Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 3805.191 ; gain = 994.109 - -Phase 1.4 Constrain Clocks/Macros -Phase 1.4 Constrain Clocks/Macros | Checksum: 198108b5a - -Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 3805.191 ; gain = 994.109 -Phase 1 Placer Initialization | Checksum: 198108b5a - -Time (s): cpu = 00:00:18 ; elapsed = 00:00:14 . Memory (MB): peak = 3805.191 ; gain = 994.109 - -Phase 2 Global Placement - -Phase 2.1 Floorplanning - -Phase 2.1.1 Partition Driven Placement - -Phase 2.1.1.1 PBP: Partition Driven Placement -Phase 2.1.1.1 PBP: Partition Driven Placement | Checksum: 1d3ec0eae - -Time (s): cpu = 00:00:20 ; elapsed = 00:00:15 . Memory (MB): peak = 3805.191 ; gain = 994.109 - -Phase 2.1.1.2 PBP: Clock Region Placement -INFO: [Place 30-3162] Check ILP status : ILP-based clock placer completed successfully. -Phase 2.1.1.2 PBP: Clock Region Placement | Checksum: 2346510b9 - -Time (s): cpu = 00:00:20 ; elapsed = 00:00:15 . Memory (MB): peak = 3805.191 ; gain = 994.109 - -Phase 2.1.1.3 PBP: Compute Congestion -Phase 2.1.1.3 PBP: Compute Congestion | Checksum: 2346510b9 - -Time (s): cpu = 00:00:32 ; elapsed = 00:00:19 . Memory (MB): peak = 3892.230 ; gain = 1081.148 - -Phase 2.1.1.4 PBP: UpdateTiming -Phase 2.1.1.4 PBP: UpdateTiming | Checksum: 25bf084b3 - -Time (s): cpu = 00:00:32 ; elapsed = 00:00:19 . Memory (MB): peak = 3892.230 ; gain = 1081.148 - -Phase 2.1.1.5 PBP: Add part constraints -Phase 2.1.1.5 PBP: Add part constraints | Checksum: 25bf084b3 - -Time (s): cpu = 00:00:32 ; elapsed = 00:00:19 . Memory (MB): peak = 3892.230 ; gain = 1081.148 -Phase 2.1.1 Partition Driven Placement | Checksum: 25bf084b3 - -Time (s): cpu = 00:00:32 ; elapsed = 00:00:19 . Memory (MB): peak = 3892.230 ; gain = 1081.148 -Phase 2.1 Floorplanning | Checksum: 1fe4adc70 - -Time (s): cpu = 00:00:32 ; elapsed = 00:00:19 . Memory (MB): peak = 3892.230 ; gain = 1081.148 - -Phase 2.2 Update Timing before SLR Path Opt -Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1fe4adc70 - -Time (s): cpu = 00:00:32 ; elapsed = 00:00:19 . Memory (MB): peak = 3892.230 ; gain = 1081.148 - -Phase 2.3 Post-Processing in Floorplanning -Phase 2.3 Post-Processing in Floorplanning | Checksum: 1fe4adc70 - -Time (s): cpu = 00:00:32 ; elapsed = 00:00:19 . Memory (MB): peak = 3892.230 ; gain = 1081.148 - -Phase 2.4 Global Place Phase1 -Phase 2.4 Global Place Phase1 | Checksum: 22c2badca - -Time (s): cpu = 00:01:20 ; elapsed = 00:00:31 . Memory (MB): peak = 3951.840 ; gain = 1140.758 - -Phase 2.5 Global Place Phase2 - -Phase 2.5.1 UpdateTiming Before Physical Synthesis -Phase 2.5.1 UpdateTiming Before Physical Synthesis | Checksum: 258367ef3 - -Time (s): cpu = 00:01:22 ; elapsed = 00:00:32 . Memory (MB): peak = 3951.840 ; gain = 1140.758 - -Phase 2.5.2 Physical Synthesis In Placer -INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 107 LUT instances to create LUTNM shape -INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0 -INFO: [Physopt 32-1138] End 1 Pass. Optimized 49 nets or LUTs. Breaked 0 LUT, combined 49 existing LUTs and moved 0 existing LUT -INFO: [Physopt 32-670] No setup violation found. Equivalent Driver Rewiring was not performed. -INFO: [Physopt 32-65] No nets found for high-fanout optimization. -INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. -INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. -INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed. -INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. -INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. -INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed. -INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication -INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 3951.840 ; gain = 0.000 - -Summary of Physical Synthesis Optimizations -============================================ - - ------------------------------------------------------------------------------------------------------------------------------------------------------------ -| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ------------------------------------------------------------------------------------------------------------------------------------------------------------ -| LUT Combining | 0 | 49 | 49 | 0 | 1 | 00:00:00 | -| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| Equivalent Driver Rewiring | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| Total | 0 | 49 | 49 | 0 | 4 | 00:00:00 | ------------------------------------------------------------------------------------------------------------------------------------------------------------ - - -Phase 2.5.2 Physical Synthesis In Placer | Checksum: 1af5f8213 - -Time (s): cpu = 00:01:24 ; elapsed = 00:00:33 . Memory (MB): peak = 3951.840 ; gain = 1140.758 -Phase 2.5 Global Place Phase2 | Checksum: 11685d894 - -Time (s): cpu = 00:01:38 ; elapsed = 00:00:36 . Memory (MB): peak = 3951.914 ; gain = 1140.832 -Phase 2 Global Placement | Checksum: 11685d894 - -Time (s): cpu = 00:01:38 ; elapsed = 00:00:36 . Memory (MB): peak = 3951.914 ; gain = 1140.832 - -Phase 3 Detail Placement - -Phase 3.1 Commit Multi Column Macros -Phase 3.1 Commit Multi Column Macros | Checksum: 15d8d1590 - -Time (s): cpu = 00:01:51 ; elapsed = 00:00:40 . Memory (MB): peak = 3953.625 ; gain = 1142.543 - -Phase 3.2 Commit Most Macros & LUTRAMs -Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 147c52846 - -Time (s): cpu = 00:01:52 ; elapsed = 00:00:40 . Memory (MB): peak = 3953.625 ; gain = 1142.543 - -Phase 3.3 Small Shape DP - -Phase 3.3.1 Small Shape Clustering -Phase 3.3.1 Small Shape Clustering | Checksum: 108962473 - -Time (s): cpu = 00:02:17 ; elapsed = 00:00:47 . Memory (MB): peak = 4012.648 ; gain = 1201.566 - -Phase 3.3.2 Slice Area Swap - -Phase 3.3.2.1 Slice Area Swap Initial -Phase 3.3.2.1 Slice Area Swap Initial | Checksum: aecf74b9 - -Time (s): cpu = 00:02:30 ; elapsed = 00:00:51 . Memory (MB): peak = 4018.648 ; gain = 1207.566 -Phase 3.3.2 Slice Area Swap | Checksum: aecf74b9 - -Time (s): cpu = 00:02:30 ; elapsed = 00:00:51 . Memory (MB): peak = 4018.648 ; gain = 1207.566 -Phase 3.3 Small Shape DP | Checksum: 11b9d9446 - -Time (s): cpu = 00:02:56 ; elapsed = 00:00:58 . Memory (MB): peak = 4024.910 ; gain = 1213.828 - -Phase 3.4 Re-assign LUT pins -Phase 3.4 Re-assign LUT pins | Checksum: 1be97277b - -Time (s): cpu = 00:02:57 ; elapsed = 00:00:59 . Memory (MB): peak = 4024.910 ; gain = 1213.828 - -Phase 3.5 Pipeline Register Optimization -Phase 3.5 Pipeline Register Optimization | Checksum: 12742c475 - -Time (s): cpu = 00:02:57 ; elapsed = 00:00:59 . Memory (MB): peak = 4024.910 ; gain = 1213.828 -Phase 3 Detail Placement | Checksum: 12742c475 - -Time (s): cpu = 00:02:57 ; elapsed = 00:00:59 . Memory (MB): peak = 4024.910 ; gain = 1213.828 - -Phase 4 Post Placement Optimization and Clean-Up - -Phase 4.1 Post Commit Optimization -INFO: [Timing 38-35] Done setting XDC timing constraints. - -Phase 4.1.1 Post Placement Optimization -Post Placement Optimization Initialization | Checksum: 1cf884ade - -Phase 4.1.1.1 BUFG Insertion - -Starting Physical Synthesis Task - -Phase 1 Physical Synthesis Initialization -INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 6 CPUs -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=4.299 | TNS=0.000 | -Phase 1 Physical Synthesis Initialization | Checksum: 1d5195f83 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.102 . Memory (MB): peak = 4024.910 ; gain = 0.000 -INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. -Ending Physical Synthesis Task | Checksum: 2960f3b91 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.145 . Memory (MB): peak = 4024.910 ; gain = 0.000 -Phase 4.1.1.1 BUFG Insertion | Checksum: 1cf884ade - -Time (s): cpu = 00:03:17 ; elapsed = 00:01:04 . Memory (MB): peak = 4024.910 ; gain = 1213.828 - -Phase 4.1.1.2 Post Placement Timing Optimization -INFO: [Place 30-746] Post Placement Timing Summary WNS=4.299. For the most accurate timing information please run report_timing. -Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 26eac437e - -Time (s): cpu = 00:03:17 ; elapsed = 00:01:04 . Memory (MB): peak = 4024.910 ; gain = 1213.828 - -Time (s): cpu = 00:03:17 ; elapsed = 00:01:04 . Memory (MB): peak = 4024.910 ; gain = 1213.828 -Phase 4.1 Post Commit Optimization | Checksum: 26eac437e - -Time (s): cpu = 00:03:18 ; elapsed = 00:01:04 . Memory (MB): peak = 4024.910 ; gain = 1213.828 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 4064.852 ; gain = 0.000 - -Phase 4.2 Post Placement Cleanup -Phase 4.2 Post Placement Cleanup | Checksum: 2aa7c0893 - -Time (s): cpu = 00:03:33 ; elapsed = 00:01:10 . Memory (MB): peak = 4064.852 ; gain = 1253.770 - -Phase 4.3 Placer Reporting - -Phase 4.3.1 Print Estimated Congestion -INFO: [Place 30-612] Post-Placement Estimated Congestion - ________________________________________________________________________ -| | Global Congestion | Long Congestion | Short Congestion | -| Direction | Region Size | Region Size | Region Size | -|___________|___________________|___________________|___________________| -| North| 1x1| 1x1| 1x1| -|___________|___________________|___________________|___________________| -| South| 1x1| 1x1| 1x1| -|___________|___________________|___________________|___________________| -| East| 1x1| 1x1| 2x2| -|___________|___________________|___________________|___________________| -| West| 1x1| 1x1| 1x1| -|___________|___________________|___________________|___________________| - -Phase 4.3.1 Print Estimated Congestion | Checksum: 2aa7c0893 - -Time (s): cpu = 00:03:33 ; elapsed = 00:01:10 . Memory (MB): peak = 4064.852 ; gain = 1253.770 -Phase 4.3 Placer Reporting | Checksum: 2aa7c0893 - -Time (s): cpu = 00:03:33 ; elapsed = 00:01:10 . Memory (MB): peak = 4064.852 ; gain = 1253.770 - -Phase 4.4 Final Placement Cleanup -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 4064.852 ; gain = 0.000 - -Time (s): cpu = 00:03:33 ; elapsed = 00:01:10 . Memory (MB): peak = 4064.852 ; gain = 1253.770 -Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1f5317f71 - -Time (s): cpu = 00:03:33 ; elapsed = 00:01:10 . Memory (MB): peak = 4064.852 ; gain = 1253.770 -Ending Placer Task | Checksum: 13b4d14c8 - -Time (s): cpu = 00:03:33 ; elapsed = 00:01:10 . Memory (MB): peak = 4064.852 ; gain = 1253.770 -83 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. -place_design completed successfully -place_design: Time (s): cpu = 00:03:40 ; elapsed = 00:01:11 . Memory (MB): peak = 4064.852 ; gain = 1341.070 -INFO: [Vivado 12-24838] Running report commands "report_control_sets, report_io, report_utilization" in parallel. -Running report generation with 3 threads. -INFO: [Vivado 12-24828] Executing command : report_control_sets -verbose -file design_1_wrapper_control_sets_placed.rpt -report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 4064.852 ; gain = 0.000 -INFO: [Vivado 12-24828] Executing command : report_utilization -file design_1_wrapper_utilization_placed.rpt -pb design_1_wrapper_utilization_placed.pb -INFO: [Vivado 12-24828] Executing command : report_io -file design_1_wrapper_io_placed.rpt -report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.122 . Memory (MB): peak = 4064.852 ; gain = 0.000 -INFO: [Timing 38-480] Writing timing data to binary archive. -Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 4064.852 ; gain = 0.000 -Wrote PlaceDB: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.815 . Memory (MB): peak = 4064.852 ; gain = 0.000 -Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4064.852 ; gain = 0.000 -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.069 . Memory (MB): peak = 4064.852 ; gain = 0.000 -Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 4064.852 ; gain = 0.000 -Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 4064.852 ; gain = 0.000 -Write Physdb Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.967 . Memory (MB): peak = 4064.852 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/lab/Documents/GitHub/SW2/SW2.runs/impl_1/design_1_wrapper_placed.dcp' has been generated. -Command: phys_opt_design -Attempting to get a license for feature 'Implementation' and/or device 'xczu3eg' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu3eg' - -Starting Initial Update Timing Task - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.808 . Memory (MB): peak = 4064.852 ; gain = 0.000 -INFO: [Vivado_Tcl 4-2279] Estimated Timing Summary | WNS= 4.295 | TNS= 0.000 | -INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. All physical synthesis setup optimizations will be skipped. -INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified. -INFO: [Common 17-83] Releasing license: Implementation -94 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. -phys_opt_design completed successfully -INFO: [Timing 38-480] Writing timing data to binary archive. -Write ShapeDB Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.041 . Memory (MB): peak = 4064.852 ; gain = 0.000 -Wrote PlaceDB: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.910 . Memory (MB): peak = 4064.852 ; gain = 0.000 -Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4064.852 ; gain = 0.000 -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.069 . Memory (MB): peak = 4064.852 ; gain = 0.000 -Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 4064.852 ; gain = 0.000 -Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 4064.852 ; gain = 0.000 -Write Physdb Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 4064.852 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/lab/Documents/GitHub/SW2/SW2.runs/impl_1/design_1_wrapper_physopt.dcp' has been generated. -Command: route_design -Attempting to get a license for feature 'Implementation' and/or device 'xczu3eg' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu3eg' - - -Starting Routing Task -INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 6 CPUs - -Phase 1 Build RT Design -Checksum: PlaceDB: bc23d659 ConstDB: 0 ShapeSum: 23c7019c RouteDB: 5b623cd3 -Nodegraph reading from file. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.729 . Memory (MB): peak = 4064.852 ; gain = 0.000 -Post Restoration Checksum: NetGraph: d4785557 | NumContArr: 92fc82eb | Constraints: e45a4556 | Timing: c2a8fa9d -Phase 1 Build RT Design | Checksum: 30e781835 - -Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 4064.852 ; gain = 0.000 - -Phase 2 Router Initialization - -Phase 2.1 Fix Topology Constraints -Phase 2.1 Fix Topology Constraints | Checksum: 30e781835 - -Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 4064.852 ; gain = 0.000 - -Phase 2.2 Pre Route Cleanup -Phase 2.2 Pre Route Cleanup | Checksum: 30e781835 - -Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 4064.852 ; gain = 0.000 - -Phase 2.3 Global Clock Net Routing - Number of Nodes with overlaps = 0 -Phase 2.3 Global Clock Net Routing | Checksum: 1f9cd8a09 - -Time (s): cpu = 00:00:08 ; elapsed = 00:00:04 . Memory (MB): peak = 4096.516 ; gain = 31.664 - -Phase 2.4 Update Timing -Phase 2.4 Update Timing | Checksum: 219f9736e - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:04 . Memory (MB): peak = 4096.516 ; gain = 31.664 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=4.416 | TNS=0.000 | WHS=-0.197 | THS=-2.104 | - - -Phase 2.5 Soft Constraint Pins - Fast Budgeting -Phase 2.5 Soft Constraint Pins - Fast Budgeting | Checksum: 23f7209fc - -Time (s): cpu = 00:00:12 ; elapsed = 00:00:05 . Memory (MB): peak = 4110.000 ; gain = 45.148 - -Router Utilization Summary - Global Vertical Routing Utilization = 0.000317857 % - Global Horizontal Routing Utilization = 0 % - Routable Net Status* - *Does not include unroutable nets such as driverless and loadless. - Run report_route_status for detailed report. - Number of Failed Nets = 7355 - (Failed Nets is the sum of unrouted and partially routed nets) - Number of Unrouted Nets = 6012 - Number of Partially Routed Nets = 1343 - Number of Node Overlaps = 0 - -Phase 2 Router Initialization | Checksum: 27ce55b57 - -Time (s): cpu = 00:00:13 ; elapsed = 00:00:05 . Memory (MB): peak = 4110.000 ; gain = 45.148 - -Phase 3 Global Routing -Phase 3 Global Routing | Checksum: 27ce55b57 - -Time (s): cpu = 00:00:13 ; elapsed = 00:00:05 . Memory (MB): peak = 4110.000 ; gain = 45.148 - -Phase 4 Initial Routing - -Phase 4.1 Initial Net Routing Pass -Phase 4.1 Initial Net Routing Pass | Checksum: 184807e4d - -Time (s): cpu = 00:00:15 ; elapsed = 00:00:06 . Memory (MB): peak = 4110.000 ; gain = 45.148 -Phase 4 Initial Routing | Checksum: 22bee22de - -Time (s): cpu = 00:00:15 ; elapsed = 00:00:06 . Memory (MB): peak = 4110.000 ; gain = 45.148 - -Phase 5 Rip-up And Reroute - -Phase 5.1 Global Iteration 0 - Number of Nodes with overlaps = 861 - Number of Nodes with overlaps = 13 - Number of Nodes with overlaps = 1 - Number of Nodes with overlaps = 0 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=4.171 | TNS=0.000 | WHS=0.041 | THS=0.000 | - -Phase 5.1 Global Iteration 0 | Checksum: 246954b5a - -Time (s): cpu = 00:00:21 ; elapsed = 00:00:09 . Memory (MB): peak = 4110.000 ; gain = 45.148 - -Phase 5.2 Additional Iteration for Hold -Phase 5.2 Additional Iteration for Hold | Checksum: 2645350d1 - -Time (s): cpu = 00:00:21 ; elapsed = 00:00:09 . Memory (MB): peak = 4110.000 ; gain = 45.148 -Phase 5 Rip-up And Reroute | Checksum: 2645350d1 - -Time (s): cpu = 00:00:21 ; elapsed = 00:00:09 . Memory (MB): peak = 4110.000 ; gain = 45.148 - -Phase 6 Delay and Skew Optimization - -Phase 6.1 Delay CleanUp -Phase 6.1 Delay CleanUp | Checksum: 31fc1c383 - -Time (s): cpu = 00:00:21 ; elapsed = 00:00:09 . Memory (MB): peak = 4110.000 ; gain = 45.148 - -Phase 6.2 Clock Skew Optimization -Phase 6.2 Clock Skew Optimization | Checksum: 31fc1c383 - -Time (s): cpu = 00:00:21 ; elapsed = 00:00:09 . Memory (MB): peak = 4110.000 ; gain = 45.148 -Phase 6 Delay and Skew Optimization | Checksum: 31fc1c383 - -Time (s): cpu = 00:00:21 ; elapsed = 00:00:09 . Memory (MB): peak = 4110.000 ; gain = 45.148 - -Phase 7 Post Hold Fix - -Phase 7.1 Hold Fix Iter -INFO: [Route 35-416] Intermediate Timing Summary | WNS=4.171 | TNS=0.000 | WHS=0.041 | THS=0.000 | - -Phase 7.1 Hold Fix Iter | Checksum: 2ed986476 - -Time (s): cpu = 00:00:23 ; elapsed = 00:00:09 . Memory (MB): peak = 4110.000 ; gain = 45.148 -Phase 7 Post Hold Fix | Checksum: 2ed986476 - -Time (s): cpu = 00:00:23 ; elapsed = 00:00:09 . Memory (MB): peak = 4110.000 ; gain = 45.148 - -Phase 8 Route finalize - -Router Utilization Summary - Global Vertical Routing Utilization = 0.943518 % - Global Horizontal Routing Utilization = 1.17801 % - Routable Net Status* - *Does not include unroutable nets such as driverless and loadless. - Run report_route_status for detailed report. - Number of Failed Nets = 0 - (Failed Nets is the sum of unrouted and partially routed nets) - Number of Unrouted Nets = 0 - Number of Partially Routed Nets = 0 - Number of Node Overlaps = 0 - -Phase 8 Route finalize | Checksum: 2ed986476 - -Time (s): cpu = 00:00:23 ; elapsed = 00:00:09 . Memory (MB): peak = 4110.000 ; gain = 45.148 - -Phase 9 Verifying routed nets - - Verification completed successfully -Phase 9 Verifying routed nets | Checksum: 2ed986476 - -Time (s): cpu = 00:00:23 ; elapsed = 00:00:09 . Memory (MB): peak = 4110.000 ; gain = 45.148 - -Phase 10 Depositing Routes -Phase 10 Depositing Routes | Checksum: 2ed986476 - -Time (s): cpu = 00:00:24 ; elapsed = 00:00:10 . Memory (MB): peak = 4110.000 ; gain = 45.148 - -Phase 11 Resolve XTalk -Phase 11 Resolve XTalk | Checksum: 2ed986476 - -Time (s): cpu = 00:00:24 ; elapsed = 00:00:10 . Memory (MB): peak = 4110.000 ; gain = 45.148 - -Phase 12 Post Process Routing -Phase 12 Post Process Routing | Checksum: 2ed986476 - -Time (s): cpu = 00:00:24 ; elapsed = 00:00:10 . Memory (MB): peak = 4110.000 ; gain = 45.148 - -Phase 13 Post Router Timing -INFO: [Route 35-57] Estimated Timing Summary | WNS=4.171 | TNS=0.000 | WHS=0.041 | THS=0.000 | - -INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. -Phase 13 Post Router Timing | Checksum: 2ed986476 - -Time (s): cpu = 00:00:24 ; elapsed = 00:00:10 . Memory (MB): peak = 4110.000 ; gain = 45.148 -Total Elapsed time in route_design: 10.05 secs - -Phase 14 Post-Route Event Processing -Phase 14 Post-Route Event Processing | Checksum: 100f46cce - -Time (s): cpu = 00:00:25 ; elapsed = 00:00:10 . Memory (MB): peak = 4110.000 ; gain = 45.148 -INFO: [Route 35-16] Router Completed Successfully -Ending Routing Task | Checksum: 100f46cce - -Time (s): cpu = 00:00:25 ; elapsed = 00:00:10 . Memory (MB): peak = 4110.000 ; gain = 45.148 - -Routing Is Done. -INFO: [Common 17-83] Releasing license: Implementation -105 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. -route_design completed successfully -route_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:10 . Memory (MB): peak = 4110.000 ; gain = 45.148 -INFO: [Vivado 12-24828] Executing command : report_drc -file design_1_wrapper_drc_routed.rpt -pb design_1_wrapper_drc_routed.pb -rpx design_1_wrapper_drc_routed.rpx -Command: report_drc -file design_1_wrapper_drc_routed.rpt -pb design_1_wrapper_drc_routed.pb -rpx design_1_wrapper_drc_routed.rpx -INFO: [IP_Flow 19-1839] IP Catalog is up to date. -INFO: [DRC 23-27] Running DRC with 6 threads -INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/lab/Documents/GitHub/SW2/SW2.runs/impl_1/design_1_wrapper_drc_routed.rpt. -report_drc completed successfully -INFO: [Vivado 12-24828] Executing command : report_methodology -file design_1_wrapper_methodology_drc_routed.rpt -pb design_1_wrapper_methodology_drc_routed.pb -rpx design_1_wrapper_methodology_drc_routed.rpx -Command: report_methodology -file design_1_wrapper_methodology_drc_routed.rpt -pb design_1_wrapper_methodology_drc_routed.pb -rpx design_1_wrapper_methodology_drc_routed.rpx -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [DRC 23-133] Running Methodology with 6 threads -INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file C:/Users/lab/Documents/GitHub/SW2/SW2.runs/impl_1/design_1_wrapper_methodology_drc_routed.rpt. -report_methodology completed successfully -INFO: [Vivado 12-24828] Executing command : report_timing_summary -max_paths 10 -routable_nets -report_unconstrained -file design_1_wrapper_timing_summary_routed.rpt -pb design_1_wrapper_timing_summary_routed.pb -rpx design_1_wrapper_timing_summary_routed.rpx -warn_on_violation -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Temperature grade: E, Delay Type: min_max. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 6 CPUs -INFO: [Vivado 12-24838] Running report commands "report_incremental_reuse, report_route_status" in parallel. -Running report generation with 2 threads. -INFO: [Vivado 12-24828] Executing command : report_incremental_reuse -file design_1_wrapper_incremental_reuse_routed.rpt -INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. -INFO: [Vivado 12-24828] Executing command : report_route_status -file design_1_wrapper_route_status.rpt -pb design_1_wrapper_route_status.pb -INFO: [Vivado 12-24828] Executing command : report_power -file design_1_wrapper_power_routed.rpt -pb design_1_wrapper_power_summary_routed.pb -rpx design_1_wrapper_power_routed.rpx -Command: report_power -file design_1_wrapper_power_routed.rpt -pb design_1_wrapper_power_summary_routed.pb -rpx design_1_wrapper_power_routed.rpx -Running Vector-less Activity Propagation... - -Finished Running Vector-less Activity Propagation -122 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. -report_power completed successfully -report_power: Time (s): cpu = 00:00:10 ; elapsed = 00:00:05 . Memory (MB): peak = 4142.480 ; gain = 0.000 -INFO: [Vivado 12-24828] Executing command : report_clock_utilization -file design_1_wrapper_clock_utilization_routed.rpt -INFO: [Vivado 12-24828] Executing command : report_bus_skew -warn_on_violation -file design_1_wrapper_bus_skew_routed.rpt -pb design_1_wrapper_bus_skew_routed.pb -rpx design_1_wrapper_bus_skew_routed.rpx -INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Temperature grade: E, Delay Type: min_max. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 6 CPUs -generate_parallel_reports: Time (s): cpu = 00:00:37 ; elapsed = 00:00:14 . Memory (MB): peak = 4142.480 ; gain = 32.480 -INFO: [Timing 38-480] Writing timing data to binary archive. -Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.040 . Memory (MB): peak = 4142.480 ; gain = 0.000 -Wrote PlaceDB: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.822 . Memory (MB): peak = 4142.480 ; gain = 0.000 -Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4142.480 ; gain = 0.000 -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Wrote RouteStorage: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.165 . Memory (MB): peak = 4142.480 ; gain = 0.000 -Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.026 . Memory (MB): peak = 4142.480 ; gain = 0.000 -Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 4142.480 ; gain = 0.000 -Write Physdb Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 4142.480 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/lab/Documents/GitHub/SW2/SW2.runs/impl_1/design_1_wrapper_routed.dcp' has been generated. -Command: write_bitstream -force design_1_wrapper.bit -Attempting to get a license for feature 'Implementation' and/or device 'xczu3eg' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu3eg' -Running DRC as a precondition to command write_bitstream -INFO: [IP_Flow 19-1839] IP Catalog is up to date. -INFO: [DRC 23-27] Running DRC with 6 threads -INFO: [Vivado 12-3199] DRC finished with 0 Errors -INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. -INFO: [Designutils 20-2272] Running write_bitstream with 6 threads. -Loading data files... -Loading site data... -Loading route data... -Processing options... -Creating bitmap... -Creating bitstream... -Bitstream compression saved 24912672 bits. -Writing bitstream ./design_1_wrapper.bit... -INFO: [Vivado 12-1842] Bitgen Completed Successfully. -INFO: [Common 17-83] Releasing license: Implementation -136 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. -write_bitstream completed successfully -write_bitstream: Time (s): cpu = 00:00:25 ; elapsed = 00:00:14 . Memory (MB): peak = 4143.785 ; gain = 1.305 -INFO: [Common 17-206] Exiting Vivado at Tue Jun 9 14:08:29 2026... diff --git a/SW2.runs/impl_1/runme.sh b/SW2.runs/impl_1/runme.sh deleted file mode 100644 index b3e4a04..0000000 --- a/SW2.runs/impl_1/runme.sh +++ /dev/null @@ -1,48 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# runme.sh: a Vivado-generated Runs Script for UNIX -# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. -# - -echo "This script was generated under a different operating system." -echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" -exit - -if [ -z "$PATH" ]; then - PATH=C:/Xilinx/2025.1/Vitis/bin;C:/Xilinx/2025.1/Vivado/ids_lite/ISE/bin/nt64;C:/Xilinx/2025.1/Vivado/ids_lite/ISE/lib/nt64:C:/Xilinx/2025.1/Vivado/bin -else - PATH=C:/Xilinx/2025.1/Vitis/bin;C:/Xilinx/2025.1/Vivado/ids_lite/ISE/bin/nt64;C:/Xilinx/2025.1/Vivado/ids_lite/ISE/lib/nt64:C:/Xilinx/2025.1/Vivado/bin:$PATH -fi -export PATH - -if [ -z "$LD_LIBRARY_PATH" ]; then - LD_LIBRARY_PATH= -else - LD_LIBRARY_PATH=:$LD_LIBRARY_PATH -fi -export LD_LIBRARY_PATH - -HD_PWD='C:/Users/lab/Documents/GitHub/SW2/SW2.runs/impl_1' -cd "$HD_PWD" - -HD_LOG=runme.log -/bin/touch $HD_LOG - -ISEStep="./ISEWrap.sh" -EAStep() -{ - $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 - if [ $? -ne 0 ] - then - exit - fi -} - -# pre-commands: -/bin/touch .init_design.begin.rst -EAStep vivado -log design_1_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source design_1_wrapper.tcl -notrace - - diff --git a/SW2.runs/impl_1/vivado.jou b/SW2.runs/impl_1/vivado.jou deleted file mode 100644 index 3ab8c62..0000000 --- a/SW2.runs/impl_1/vivado.jou +++ /dev/null @@ -1,24 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2025.1 (64-bit) -# SW Build 6140274 on Thu May 22 00:12:29 MDT 2025 -# IP Build 6138677 on Thu May 22 03:10:11 MDT 2025 -# SharedData Build 6139179 on Tue May 20 17:58:58 MDT 2025 -# Start of session at: Tue Jun 9 14:05:43 2026 -# Process ID : 8876 -# Current directory : C:/Users/lab/Documents/GitHub/SW2/SW2.runs/impl_1 -# Command line : vivado.exe -log design_1_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source design_1_wrapper.tcl -notrace -# Log file : C:/Users/lab/Documents/GitHub/SW2/SW2.runs/impl_1/design_1_wrapper.vdi -# Journal file : C:/Users/lab/Documents/GitHub/SW2/SW2.runs/impl_1\vivado.jou -# Running On : Lab016-04 -# Platform : Windows Server 2016 or Windows 10 -# Operating System : 19045 -# Processor Detail : Intel(R) Core(TM) i7-8700 CPU @ 3.20GHz -# CPU Frequency : 3192 MHz -# CPU Physical cores : 6 -# CPU Logical cores : 12 -# Host memory : 17030 MB -# Swap memory : 2550 MB -# Total Virtual : 19580 MB -# Available Virtual : 12132 MB -#----------------------------------------------------------- -source design_1_wrapper.tcl -notrace diff --git a/SW2.runs/impl_1/vivado.pb b/SW2.runs/impl_1/vivado.pb deleted file mode 100644 index bcf37c9..0000000 Binary files a/SW2.runs/impl_1/vivado.pb and /dev/null differ diff --git a/SW2.runs/impl_1/vivado_2556.backup.jou b/SW2.runs/impl_1/vivado_2556.backup.jou deleted file mode 100644 index f783069..0000000 --- a/SW2.runs/impl_1/vivado_2556.backup.jou +++ /dev/null @@ -1,24 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2025.1 (64-bit) -# SW Build 6140274 on Thu May 22 00:12:29 MDT 2025 -# IP Build 6138677 on Thu May 22 03:10:11 MDT 2025 -# SharedData Build 6139179 on Tue May 20 17:58:58 MDT 2025 -# Start of session at: Tue Jun 2 14:49:53 2026 -# Process ID : 2556 -# Current directory : C:/Users/lab/Documents/GitHub/SW2/SW2.runs/impl_1 -# Command line : vivado.exe -log design_1_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source design_1_wrapper.tcl -notrace -# Log file : C:/Users/lab/Documents/GitHub/SW2/SW2.runs/impl_1/design_1_wrapper.vdi -# Journal file : C:/Users/lab/Documents/GitHub/SW2/SW2.runs/impl_1\vivado.jou -# Running On : Lab016-09 -# Platform : Windows Server 2016 or Windows 10 -# Operating System : 19045 -# Processor Detail : Intel(R) Core(TM) i7-8700 CPU @ 3.20GHz -# CPU Frequency : 3192 MHz -# CPU Physical cores : 6 -# CPU Logical cores : 12 -# Host memory : 17030 MB -# Swap memory : 2550 MB -# Total Virtual : 19580 MB -# Available Virtual : 12670 MB -#----------------------------------------------------------- -source design_1_wrapper.tcl -notrace diff --git a/SW2.runs/impl_1/vivado_2980.backup.jou b/SW2.runs/impl_1/vivado_2980.backup.jou deleted file mode 100644 index 05b9a76..0000000 --- a/SW2.runs/impl_1/vivado_2980.backup.jou +++ /dev/null @@ -1,24 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2025.1 (64-bit) -# SW Build 6140274 on Thu May 22 00:12:29 MDT 2025 -# IP Build 6138677 on Thu May 22 03:10:11 MDT 2025 -# SharedData Build 6139179 on Tue May 20 17:58:58 MDT 2025 -# Start of session at: Tue Jun 9 13:56:43 2026 -# Process ID : 2980 -# Current directory : C:/Users/lab/Documents/GitHub/SW2/SW2.runs/impl_1 -# Command line : vivado.exe -log design_1_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source design_1_wrapper.tcl -notrace -# Log file : C:/Users/lab/Documents/GitHub/SW2/SW2.runs/impl_1/design_1_wrapper.vdi -# Journal file : C:/Users/lab/Documents/GitHub/SW2/SW2.runs/impl_1\vivado.jou -# Running On : Lab016-04 -# Platform : Windows Server 2016 or Windows 10 -# Operating System : 19045 -# Processor Detail : Intel(R) Core(TM) i7-8700 CPU @ 3.20GHz -# CPU Frequency : 3192 MHz -# CPU Physical cores : 6 -# CPU Logical cores : 12 -# Host memory : 17030 MB -# Swap memory : 2550 MB -# Total Virtual : 19580 MB -# Available Virtual : 12572 MB -#----------------------------------------------------------- -source design_1_wrapper.tcl -notrace diff --git a/SW2.runs/impl_1/vivado_4920.backup.jou b/SW2.runs/impl_1/vivado_4920.backup.jou deleted file mode 100644 index d45801a..0000000 --- a/SW2.runs/impl_1/vivado_4920.backup.jou +++ /dev/null @@ -1,24 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2025.1 (64-bit) -# SW Build 6140274 on Thu May 22 00:12:29 MDT 2025 -# IP Build 6138677 on Thu May 22 03:10:11 MDT 2025 -# SharedData Build 6139179 on Tue May 20 17:58:58 MDT 2025 -# Start of session at: Tue Jun 9 13:59:28 2026 -# Process ID : 4920 -# Current directory : C:/Users/lab/Documents/GitHub/SW2/SW2.runs/impl_1 -# Command line : vivado.exe -log design_1_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source design_1_wrapper.tcl -notrace -# Log file : C:/Users/lab/Documents/GitHub/SW2/SW2.runs/impl_1/design_1_wrapper.vdi -# Journal file : C:/Users/lab/Documents/GitHub/SW2/SW2.runs/impl_1\vivado.jou -# Running On : Lab016-04 -# Platform : Windows Server 2016 or Windows 10 -# Operating System : 19045 -# Processor Detail : Intel(R) Core(TM) i7-8700 CPU @ 3.20GHz -# CPU Frequency : 3192 MHz -# CPU Physical cores : 6 -# CPU Logical cores : 12 -# Host memory : 17030 MB -# Swap memory : 2550 MB -# Total Virtual : 19580 MB -# Available Virtual : 12579 MB -#----------------------------------------------------------- -source design_1_wrapper.tcl -notrace diff --git a/SW2.runs/impl_1/write_bitstream.pb b/SW2.runs/impl_1/write_bitstream.pb deleted file mode 100644 index 132aff7..0000000 Binary files a/SW2.runs/impl_1/write_bitstream.pb and /dev/null differ diff --git a/SW2.runs/synth_1/.Xil/design_1_wrapper_propImpl.xdc b/SW2.runs/synth_1/.Xil/design_1_wrapper_propImpl.xdc index 17ad9fe..3d92227 100644 --- a/SW2.runs/synth_1/.Xil/design_1_wrapper_propImpl.xdc +++ b/SW2.runs/synth_1/.Xil/design_1_wrapper_propImpl.xdc @@ -1,5 +1,5 @@ -set_property SRC_FILE_INFO {cfile:C:/Users/lab/Documents/GitHub/SW2/SW2.srcs/constrs_1/new/mainconstraint.xdc rfile:../../../SW2.srcs/constrs_1/new/mainconstraint.xdc id:1} [current_design] -set_property SRC_FILE_INFO {cfile:C:/Users/lab/Documents/GitHub/SW2/SW2.srcs/constrs_1/new/sideconstraint.xdc rfile:../../../SW2.srcs/constrs_1/new/sideconstraint.xdc id:2} [current_design] +set_property SRC_FILE_INFO {cfile:D:/GitHub/SW2/SW2.srcs/constrs_1/new/mainconstraint.xdc rfile:../../../SW2.srcs/constrs_1/new/mainconstraint.xdc id:1} [current_design] +set_property SRC_FILE_INFO {cfile:D:/GitHub/SW2/SW2.srcs/constrs_1/new/sideconstraint.xdc rfile:../../../SW2.srcs/constrs_1/new/sideconstraint.xdc id:2} [current_design] set_property src_info {type:XDC file:1 line:9 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN AA8 [get_ports {ROT_A}] set_property src_info {type:XDC file:1 line:10 export:INPUT save:INPUT read:READ} [current_design] diff --git a/SW2.runs/synth_1/.vivado.begin.rst b/SW2.runs/synth_1/.vivado.begin.rst index 7cdb35f..b7c9a8f 100644 --- a/SW2.runs/synth_1/.vivado.begin.rst +++ b/SW2.runs/synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/SW2.runs/synth_1/ISEWrap.sh b/SW2.runs/synth_1/ISEWrap.sh index 05d5381..e085d18 100644 --- a/SW2.runs/synth_1/ISEWrap.sh +++ b/SW2.runs/synth_1/ISEWrap.sh @@ -1,4 +1,4 @@ -#!/bin/sh +#!/bin/bash # # Vivado(TM) diff --git a/SW2.runs/synth_1/design_1_wrapper.dcp b/SW2.runs/synth_1/design_1_wrapper.dcp index fe47363..4fdbd41 100644 Binary files a/SW2.runs/synth_1/design_1_wrapper.dcp and b/SW2.runs/synth_1/design_1_wrapper.dcp differ diff --git a/SW2.runs/synth_1/design_1_wrapper.tcl b/SW2.runs/synth_1/design_1_wrapper.tcl index 21daa7f..7e191b8 100644 --- a/SW2.runs/synth_1/design_1_wrapper.tcl +++ b/SW2.runs/synth_1/design_1_wrapper.tcl @@ -4,7 +4,7 @@ set TIME_start [clock seconds] namespace eval ::optrace { - variable script "C:/Users/lab/Documents/GitHub/SW2/SW2.runs/synth_1/design_1_wrapper.tcl" + variable script "D:/GitHub/SW2/SW2.runs/synth_1/design_1_wrapper.tcl" variable category "vivado_synth" } @@ -56,10 +56,7 @@ if {$::dispatch::connected} { } OPTRACE "synth_1" START { ROLLUP_AUTO } -set_param general.maxThreads 6 -set_param chipscope.maxJobs 3 set_param general.usePosixSpawnForFork 1 -set_param xicom.use_bs_reader 1 OPTRACE "Creating in-memory project" START { } create_project -in_memory -part xczu3eg-sfvc784-2-e @@ -67,28 +64,26 @@ set_param project.singleFileAddWarning.threshold 0 set_param project.compositeFile.enableAutoGeneration 0 set_param synth.vivado.isSynthRun true set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir C:/Users/lab/Documents/GitHub/SW2/SW2.cache/wt [current_project] -set_property parent.project_path C:/Users/lab/Documents/GitHub/SW2/SW2.xpr [current_project] +set_property webtalk.parent_dir D:/GitHub/SW2/SW2.cache/wt [current_project] +set_property parent.project_path D:/GitHub/SW2/SW2.xpr [current_project] set_property XPM_LIBRARIES XPM_CDC [current_project] set_property default_lib xil_defaultlib [current_project] set_property target_language Verilog [current_project] -set_property board_part_repo_paths {C:/Xilinx/Board_repo} [current_project] -set_property board_part realdigital.org:aup-zu3-8gb:part0:1.0 [current_project] set_property ip_repo_paths { - c:/Xilinx/IP_Repo - c:/Xilinx/IP_Repo/OLED_ASCII + ../Xilinx/IP_Repo + ../Xilinx/IP_Repo/OLED_ASCII } [current_project] update_ip_catalog -set_property ip_output_repo c:/Users/lab/Documents/GitHub/SW2/SW2.cache/ip [current_project] +set_property ip_output_repo d:/GitHub/SW2/SW2.cache/ip [current_project] set_property ip_cache_permissions {read write} [current_project] OPTRACE "Creating in-memory project" END { } OPTRACE "Adding files" START { } -read_verilog -library xil_defaultlib C:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v -add_files C:/Users/lab/Documents/GitHub/SW2/SW2.srcs/sources_1/bd/design_1/design_1.bd -set_property used_in_implementation false [get_files -all c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0_board.xdc] -set_property used_in_implementation false [get_files -all c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.xdc] -set_property used_in_implementation false [get_files -all c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0_ooc.xdc] -set_property used_in_implementation false [get_files -all c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/design_1_ooc.xdc] +read_verilog -library xil_defaultlib D:/GitHub/SW2/SW2.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v +add_files D:/GitHub/SW2/SW2.srcs/sources_1/bd/design_1/design_1.bd +set_property used_in_implementation false [get_files -all d:/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0_board.xdc] +set_property used_in_implementation false [get_files -all d:/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.xdc] +set_property used_in_implementation false [get_files -all d:/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0_ooc.xdc] +set_property used_in_implementation false [get_files -all d:/GitHub/SW2/SW2.gen/sources_1/bd/design_1/design_1_ooc.xdc] OPTRACE "Adding files" END { } # Mark all dcp files as not used in implementation to prevent them from being @@ -99,17 +94,17 @@ OPTRACE "Adding files" END { } foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { set_property used_in_implementation false $dcp } -read_xdc C:/Users/lab/Documents/GitHub/SW2/SW2.srcs/constrs_1/new/mainconstraint.xdc -set_property used_in_implementation false [get_files C:/Users/lab/Documents/GitHub/SW2/SW2.srcs/constrs_1/new/mainconstraint.xdc] +read_xdc D:/GitHub/SW2/SW2.srcs/constrs_1/new/mainconstraint.xdc +set_property used_in_implementation false [get_files D:/GitHub/SW2/SW2.srcs/constrs_1/new/mainconstraint.xdc] -read_xdc C:/Users/lab/Documents/GitHub/SW2/SW2.srcs/constrs_1/new/sideconstraint.xdc -set_property used_in_implementation false [get_files C:/Users/lab/Documents/GitHub/SW2/SW2.srcs/constrs_1/new/sideconstraint.xdc] +read_xdc D:/GitHub/SW2/SW2.srcs/constrs_1/new/sideconstraint.xdc +set_property used_in_implementation false [get_files D:/GitHub/SW2/SW2.srcs/constrs_1/new/sideconstraint.xdc] read_xdc dont_touch.xdc set_property used_in_implementation false [get_files dont_touch.xdc] set_param ips.enableIPCacheLiteLoad 1 -read_checkpoint -auto_incremental -incremental C:/Users/lab/Documents/GitHub/SW2/SW2.srcs/utils_1/imports/synth_1/ImgGen.dcp +read_checkpoint -auto_incremental -incremental D:/GitHub/SW2/SW2.srcs/utils_1/imports/synth_1/ImgGen.dcp close [open __synthesis_is_running__ w] OPTRACE "synth_design" START { } diff --git a/SW2.runs/synth_1/design_1_wrapper.vds b/SW2.runs/synth_1/design_1_wrapper.vds index cd36297..67d00fe 100644 --- a/SW2.runs/synth_1/design_1_wrapper.vds +++ b/SW2.runs/synth_1/design_1_wrapper.vds @@ -1,128 +1,135 @@ #----------------------------------------------------------- -# Vivado v2025.1 (64-bit) -# SW Build 6140274 on Thu May 22 00:12:29 MDT 2025 -# IP Build 6138677 on Thu May 22 03:10:11 MDT 2025 -# SharedData Build 6139179 on Tue May 20 17:58:58 MDT 2025 -# Start of session at: Tue Jun 9 14:04:36 2026 -# Process ID : 12296 -# Current directory : C:/Users/lab/Documents/GitHub/SW2/SW2.runs/synth_1 +# Vivado v2025.2 (64-bit) +# SW Build 6299465 on Fri Nov 14 19:35:11 GMT 2025 +# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025 +# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025 +# Start of session at: Mon Jun 22 10:04:16 2026 +# Process ID : 25072 +# Current directory : D:/GitHub/SW2/SW2.runs/synth_1 # Command line : vivado.exe -log design_1_wrapper.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source design_1_wrapper.tcl -# Log file : C:/Users/lab/Documents/GitHub/SW2/SW2.runs/synth_1/design_1_wrapper.vds -# Journal file : C:/Users/lab/Documents/GitHub/SW2/SW2.runs/synth_1\vivado.jou -# Running On : Lab016-04 +# Log file : D:/GitHub/SW2/SW2.runs/synth_1/design_1_wrapper.vds +# Journal file : D:/GitHub/SW2/SW2.runs/synth_1\vivado.jou +# Running On : DESKTOP-FMR4U99 # Platform : Windows Server 2016 or Windows 10 -# Operating System : 19045 -# Processor Detail : Intel(R) Core(TM) i7-8700 CPU @ 3.20GHz -# CPU Frequency : 3192 MHz -# CPU Physical cores : 6 -# CPU Logical cores : 12 -# Host memory : 17030 MB -# Swap memory : 2550 MB -# Total Virtual : 19580 MB -# Available Virtual : 12243 MB +# Operating System : 26200 +# Processor Detail : Intel(R) Core(TM) i3-8130U CPU @ 2.20GHz +# CPU Frequency : 2208 MHz +# CPU Physical cores : 2 +# CPU Logical cores : 4 +# Host memory : 12781 MB +# Swap memory : 3418 MB +# Total Virtual : 16200 MB +# Available Virtual : 4088 MB #----------------------------------------------------------- -Sourcing tcl script 'C:/Users/lab/AppData/Roaming/Xilinx/Vivado/Vivado_init.tcl' source design_1_wrapper.tcl -notrace -create_project: Time (s): cpu = 00:00:22 ; elapsed = 00:00:05 . Memory (MB): peak = 507.602 ; gain = 227.941 +create_project: Time (s): cpu = 00:00:21 ; elapsed = 00:00:15 . Memory (MB): peak = 530.863 ; gain = 219.363 INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Xilinx/IP_Repo'. -WARNING: [IP_Flow 19-3685] Ignored loading user repository 'c:/Xilinx/IP_Repo/OLED_ASCII'. The path is contained within another repository. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/2025.1/Vivado/data/ip'. -Command: read_checkpoint -auto_incremental -incremental C:/Users/lab/Documents/GitHub/SW2/SW2.srcs/utils_1/imports/synth_1/ImgGen.dcp -INFO: [Vivado 12-5825] Read reference checkpoint from C:/Users/lab/Documents/GitHub/SW2/SW2.srcs/utils_1/imports/synth_1/ImgGen.dcp for incremental synthesis +WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'd:/GitHub/SW2/SW2.runs/Xilinx/IP_Repo'; Can't find the specified path. +If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. +WARNING: [IP_Flow 19-3685] Ignored loading user repository 'd:/GitHub/SW2/SW2.runs/Xilinx/IP_Repo/OLED_ASCII'. The path is contained within another repository. +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Pobrane/AMDDesignTools/2025.2/Vivado/data/ip'. +WARNING: [BD 41-1661] One or more IPs have been locked in the design 'design_1.bd'. Please run report_ip_status for more details and recommendations on how to fix this issue. +List of locked IPs: +design_1_HDMI_TX_0_0 +design_1_clk_wiz_0_0 +design_1_RotaryEnc_0_0 + +Command: read_checkpoint -auto_incremental -incremental D:/GitHub/SW2/SW2.srcs/utils_1/imports/synth_1/ImgGen.dcp +INFO: [Vivado 12-5825] Read reference checkpoint from D:/GitHub/SW2/SW2.srcs/utils_1/imports/synth_1/ImgGen.dcp for incremental synthesis INFO: [Vivado 12-7989] Please ensure there are no constraint changes Command: synth_design -top design_1_wrapper -part xczu3eg-sfvc784-2-e Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xczu3eg' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xczu3eg' +WARNING: [Vivado_Tcl 4-1809] The reference checkpoint is from an old version of Vivado; A full resynthesis flow will be run INFO: [Device 21-403] Loading part xczu3eg-sfvc784-2-e INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} -INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 6 processes. +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes -INFO: [Synth 8-7075] Helper process launched with PID 9840 ---------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1681.172 ; gain = 201.156 ---------------------------------------------------------------------------------- -INFO: [Synth 8-6157] synthesizing module 'design_1_wrapper' [C:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v:13] -INFO: [Synth 8-6157] synthesizing module 'design_1' [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/synth/design_1.v:13] -INFO: [Synth 8-6157] synthesizing module 'design_1_EnemyController_0_0' [C:/Users/lab/Documents/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-12296-Lab016-04/realtime/design_1_EnemyController_0_0_stub.v:6] -INFO: [Synth 8-6155] done synthesizing module 'design_1_EnemyController_0_0' (0#1) [C:/Users/lab/Documents/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-12296-Lab016-04/realtime/design_1_EnemyController_0_0_stub.v:6] -INFO: [Synth 8-6157] synthesizing module 'design_1_GameController_0_0' [C:/Users/lab/Documents/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-12296-Lab016-04/realtime/design_1_GameController_0_0_stub.v:6] -INFO: [Synth 8-6155] done synthesizing module 'design_1_GameController_0_0' (0#1) [C:/Users/lab/Documents/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-12296-Lab016-04/realtime/design_1_GameController_0_0_stub.v:6] -INFO: [Synth 8-6157] synthesizing module 'design_1_HDMI_TX_0_0' [C:/Users/lab/Documents/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-12296-Lab016-04/realtime/design_1_HDMI_TX_0_0_stub.v:6] -INFO: [Synth 8-6155] done synthesizing module 'design_1_HDMI_TX_0_0' (0#1) [C:/Users/lab/Documents/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-12296-Lab016-04/realtime/design_1_HDMI_TX_0_0_stub.v:6] -INFO: [Synth 8-6157] synthesizing module 'design_1_ImgGen_0_0' [C:/Users/lab/Documents/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-12296-Lab016-04/realtime/design_1_ImgGen_0_0_stub.v:6] -INFO: [Synth 8-6155] done synthesizing module 'design_1_ImgGen_0_0' (0#1) [C:/Users/lab/Documents/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-12296-Lab016-04/realtime/design_1_ImgGen_0_0_stub.v:6] -INFO: [Synth 8-6157] synthesizing module 'design_1_RotaryEnc_0_0' [C:/Users/lab/Documents/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-12296-Lab016-04/realtime/design_1_RotaryEnc_0_0_stub.v:6] -INFO: [Synth 8-6155] done synthesizing module 'design_1_RotaryEnc_0_0' (0#1) [C:/Users/lab/Documents/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-12296-Lab016-04/realtime/design_1_RotaryEnc_0_0_stub.v:6] -INFO: [Synth 8-6157] synthesizing module 'design_1_TickGenerator_0_0' [C:/Users/lab/Documents/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-12296-Lab016-04/realtime/design_1_TickGenerator_0_0_stub.v:6] -INFO: [Synth 8-6155] done synthesizing module 'design_1_TickGenerator_0_0' (0#1) [C:/Users/lab/Documents/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-12296-Lab016-04/realtime/design_1_TickGenerator_0_0_stub.v:6] -INFO: [Synth 8-6157] synthesizing module 'design_1_VideoTiming_0_0' [C:/Users/lab/Documents/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-12296-Lab016-04/realtime/design_1_VideoTiming_0_0_stub.v:6] -INFO: [Synth 8-6155] done synthesizing module 'design_1_VideoTiming_0_0' (0#1) [C:/Users/lab/Documents/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-12296-Lab016-04/realtime/design_1_VideoTiming_0_0_stub.v:6] -INFO: [Synth 8-6157] synthesizing module 'design_1_angle_encoder_1_0' [C:/Users/lab/Documents/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-12296-Lab016-04/realtime/design_1_angle_encoder_1_0_stub.v:6] -INFO: [Synth 8-6155] done synthesizing module 'design_1_angle_encoder_1_0' (0#1) [C:/Users/lab/Documents/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-12296-Lab016-04/realtime/design_1_angle_encoder_1_0_stub.v:6] -INFO: [Synth 8-6157] synthesizing module 'design_1_clk_wiz_0_0' [C:/Users/lab/Documents/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-12296-Lab016-04/realtime/design_1_clk_wiz_0_0_stub.v:6] -INFO: [Synth 8-6155] done synthesizing module 'design_1_clk_wiz_0_0' (0#1) [C:/Users/lab/Documents/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-12296-Lab016-04/realtime/design_1_clk_wiz_0_0_stub.v:6] -INFO: [Synth 8-6155] done synthesizing module 'design_1' (0#1) [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/synth/design_1.v:13] -INFO: [Synth 8-6155] done synthesizing module 'design_1_wrapper' (0#1) [C:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v:13] ---------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1788.441 ; gain = 308.426 +INFO: [Synth 8-7075] Helper process launched with PID 19304 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1787.391 ; gain = 205.809 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'design_1_wrapper' [D:/GitHub/SW2/SW2.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v:13] +INFO: [Synth 8-6157] synthesizing module 'design_1' [d:/GitHub/SW2/SW2.gen/sources_1/bd/design_1/synth/design_1.v:13] +INFO: [Synth 8-6157] synthesizing module 'design_1_EnemyController_0_0' [D:/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-25072-DESKTOP-FMR4U99/realtime/design_1_EnemyController_0_0_stub.v:6] +INFO: [Synth 8-6155] done synthesizing module 'design_1_EnemyController_0_0' (0#1) [D:/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-25072-DESKTOP-FMR4U99/realtime/design_1_EnemyController_0_0_stub.v:6] +INFO: [Synth 8-6157] synthesizing module 'design_1_GameController_0_0' [D:/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-25072-DESKTOP-FMR4U99/realtime/design_1_GameController_0_0_stub.v:6] +INFO: [Synth 8-6155] done synthesizing module 'design_1_GameController_0_0' (0#1) [D:/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-25072-DESKTOP-FMR4U99/realtime/design_1_GameController_0_0_stub.v:6] +INFO: [Synth 8-6157] synthesizing module 'design_1_HDMI_TX_0_0' [D:/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-25072-DESKTOP-FMR4U99/realtime/design_1_HDMI_TX_0_0_stub.v:6] +INFO: [Synth 8-6155] done synthesizing module 'design_1_HDMI_TX_0_0' (0#1) [D:/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-25072-DESKTOP-FMR4U99/realtime/design_1_HDMI_TX_0_0_stub.v:6] +INFO: [Synth 8-6157] synthesizing module 'design_1_ImgGen_0_0' [D:/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-25072-DESKTOP-FMR4U99/realtime/design_1_ImgGen_0_0_stub.v:6] +INFO: [Synth 8-6155] done synthesizing module 'design_1_ImgGen_0_0' (0#1) [D:/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-25072-DESKTOP-FMR4U99/realtime/design_1_ImgGen_0_0_stub.v:6] +INFO: [Synth 8-6157] synthesizing module 'design_1_RotaryEnc_0_0' [D:/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-25072-DESKTOP-FMR4U99/realtime/design_1_RotaryEnc_0_0_stub.v:6] +INFO: [Synth 8-6155] done synthesizing module 'design_1_RotaryEnc_0_0' (0#1) [D:/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-25072-DESKTOP-FMR4U99/realtime/design_1_RotaryEnc_0_0_stub.v:6] +INFO: [Synth 8-6157] synthesizing module 'design_1_TickGenerator_0_0' [D:/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-25072-DESKTOP-FMR4U99/realtime/design_1_TickGenerator_0_0_stub.v:6] +INFO: [Synth 8-6155] done synthesizing module 'design_1_TickGenerator_0_0' (0#1) [D:/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-25072-DESKTOP-FMR4U99/realtime/design_1_TickGenerator_0_0_stub.v:6] +INFO: [Synth 8-6157] synthesizing module 'design_1_VideoTiming_0_0' [D:/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-25072-DESKTOP-FMR4U99/realtime/design_1_VideoTiming_0_0_stub.v:6] +INFO: [Synth 8-6155] done synthesizing module 'design_1_VideoTiming_0_0' (0#1) [D:/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-25072-DESKTOP-FMR4U99/realtime/design_1_VideoTiming_0_0_stub.v:6] +INFO: [Synth 8-6157] synthesizing module 'design_1_angle_encoder_1_0' [D:/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-25072-DESKTOP-FMR4U99/realtime/design_1_angle_encoder_1_0_stub.v:6] +INFO: [Synth 8-6155] done synthesizing module 'design_1_angle_encoder_1_0' (0#1) [D:/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-25072-DESKTOP-FMR4U99/realtime/design_1_angle_encoder_1_0_stub.v:6] +INFO: [Synth 8-6157] synthesizing module 'design_1_clk_wiz_0_0' [D:/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-25072-DESKTOP-FMR4U99/realtime/design_1_clk_wiz_0_0_stub.v:6] +INFO: [Synth 8-6155] done synthesizing module 'design_1_clk_wiz_0_0' (0#1) [D:/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-25072-DESKTOP-FMR4U99/realtime/design_1_clk_wiz_0_0_stub.v:6] +INFO: [Synth 8-6155] done synthesizing module 'design_1' (0#1) [d:/GitHub/SW2/SW2.gen/sources_1/bd/design_1/synth/design_1.v:13] +INFO: [Synth 8-6155] done synthesizing module 'design_1_wrapper' (0#1) [D:/GitHub/SW2/SW2.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v:13] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1907.453 ; gain = 325.871 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1788.441 ; gain = 308.426 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 1907.453 ; gain = 325.871 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1788.441 ; gain = 308.426 +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 1907.453 ; gain = 325.871 --------------------------------------------------------------------------------- -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1788.441 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1907.453 ; gain = 0.000 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine -Parsing XDC File [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0_in_context.xdc] for cell 'design_1_i/clk_wiz_0' -create_clock: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1811.898 ; gain = 13.551 -Finished Parsing XDC File [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0_in_context.xdc] for cell 'design_1_i/clk_wiz_0' -Parsing XDC File [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_HDMI_TX_0_0/design_1_HDMI_TX_0_0/design_1_HDMI_TX_0_0_in_context.xdc] for cell 'design_1_i/HDMI_TX_0' -Finished Parsing XDC File [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_HDMI_TX_0_0/design_1_HDMI_TX_0_0/design_1_HDMI_TX_0_0_in_context.xdc] for cell 'design_1_i/HDMI_TX_0' -Parsing XDC File [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_VideoTiming_0_0/design_1_VideoTiming_0_0/design_1_VideoTiming_0_0_in_context.xdc] for cell 'design_1_i/VideoTiming_0' -Finished Parsing XDC File [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_VideoTiming_0_0/design_1_VideoTiming_0_0/design_1_VideoTiming_0_0_in_context.xdc] for cell 'design_1_i/VideoTiming_0' -Parsing XDC File [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_ImgGen_0_0/design_1_ImgGen_0_0/design_1_ImgGen_0_0_in_context.xdc] for cell 'design_1_i/ImgGen_0' -Finished Parsing XDC File [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_ImgGen_0_0/design_1_ImgGen_0_0/design_1_ImgGen_0_0_in_context.xdc] for cell 'design_1_i/ImgGen_0' -Parsing XDC File [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_RotaryEnc_0_0/design_1_RotaryEnc_0_0/design_1_RotaryEnc_0_0_in_context.xdc] for cell 'design_1_i/RotaryEnc_0' -Finished Parsing XDC File [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_RotaryEnc_0_0/design_1_RotaryEnc_0_0/design_1_RotaryEnc_0_0_in_context.xdc] for cell 'design_1_i/RotaryEnc_0' -Parsing XDC File [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_angle_encoder_1_0/design_1_angle_encoder_1_0/design_1_angle_encoder_1_0_in_context.xdc] for cell 'design_1_i/angle_encoder_1' -Finished Parsing XDC File [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_angle_encoder_1_0/design_1_angle_encoder_1_0/design_1_angle_encoder_1_0_in_context.xdc] for cell 'design_1_i/angle_encoder_1' -Parsing XDC File [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_EnemyController_0_0/design_1_EnemyController_0_0/design_1_EnemyController_0_0_in_context.xdc] for cell 'design_1_i/EnemyController_0' -Finished Parsing XDC File [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_EnemyController_0_0/design_1_EnemyController_0_0/design_1_EnemyController_0_0_in_context.xdc] for cell 'design_1_i/EnemyController_0' -Parsing XDC File [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_TickGenerator_0_0/design_1_TickGenerator_0_0/design_1_TickGenerator_0_0_in_context.xdc] for cell 'design_1_i/TickGenerator_0' -Finished Parsing XDC File [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_TickGenerator_0_0/design_1_TickGenerator_0_0/design_1_TickGenerator_0_0_in_context.xdc] for cell 'design_1_i/TickGenerator_0' -Parsing XDC File [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_GameController_0_0/design_1_GameController_0_0/design_1_GameController_0_0_in_context.xdc] for cell 'design_1_i/GameController_0' -Finished Parsing XDC File [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_GameController_0_0/design_1_GameController_0_0/design_1_GameController_0_0_in_context.xdc] for cell 'design_1_i/GameController_0' -Parsing XDC File [C:/Users/lab/Documents/GitHub/SW2/SW2.srcs/constrs_1/new/mainconstraint.xdc] -Finished Parsing XDC File [C:/Users/lab/Documents/GitHub/SW2/SW2.srcs/constrs_1/new/mainconstraint.xdc] -INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/lab/Documents/GitHub/SW2/SW2.srcs/constrs_1/new/mainconstraint.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc]. +Parsing XDC File [d:/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0_in_context.xdc] for cell 'design_1_i/clk_wiz_0' +create_clock: Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1919.059 ; gain = 11.605 +Finished Parsing XDC File [d:/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0_in_context.xdc] for cell 'design_1_i/clk_wiz_0' +Parsing XDC File [d:/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_HDMI_TX_0_0/design_1_HDMI_TX_0_0/design_1_HDMI_TX_0_0_in_context.xdc] for cell 'design_1_i/HDMI_TX_0' +Finished Parsing XDC File [d:/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_HDMI_TX_0_0/design_1_HDMI_TX_0_0/design_1_HDMI_TX_0_0_in_context.xdc] for cell 'design_1_i/HDMI_TX_0' +Parsing XDC File [d:/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_VideoTiming_0_0/design_1_VideoTiming_0_0/design_1_VideoTiming_0_0_in_context.xdc] for cell 'design_1_i/VideoTiming_0' +Finished Parsing XDC File [d:/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_VideoTiming_0_0/design_1_VideoTiming_0_0/design_1_VideoTiming_0_0_in_context.xdc] for cell 'design_1_i/VideoTiming_0' +Parsing XDC File [d:/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_ImgGen_0_0/design_1_ImgGen_0_0/design_1_ImgGen_0_0_in_context.xdc] for cell 'design_1_i/ImgGen_0' +Finished Parsing XDC File [d:/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_ImgGen_0_0/design_1_ImgGen_0_0/design_1_ImgGen_0_0_in_context.xdc] for cell 'design_1_i/ImgGen_0' +Parsing XDC File [d:/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_RotaryEnc_0_0/design_1_RotaryEnc_0_0/design_1_RotaryEnc_0_0_in_context.xdc] for cell 'design_1_i/RotaryEnc_0' +Finished Parsing XDC File [d:/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_RotaryEnc_0_0/design_1_RotaryEnc_0_0/design_1_RotaryEnc_0_0_in_context.xdc] for cell 'design_1_i/RotaryEnc_0' +Parsing XDC File [d:/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_angle_encoder_1_0/design_1_angle_encoder_1_0/design_1_angle_encoder_1_0_in_context.xdc] for cell 'design_1_i/angle_encoder_1' +Finished Parsing XDC File [d:/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_angle_encoder_1_0/design_1_angle_encoder_1_0/design_1_angle_encoder_1_0_in_context.xdc] for cell 'design_1_i/angle_encoder_1' +Parsing XDC File [d:/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_EnemyController_0_0/design_1_EnemyController_0_0/design_1_EnemyController_0_0_in_context.xdc] for cell 'design_1_i/EnemyController_0' +Finished Parsing XDC File [d:/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_EnemyController_0_0/design_1_EnemyController_0_0/design_1_EnemyController_0_0_in_context.xdc] for cell 'design_1_i/EnemyController_0' +Parsing XDC File [d:/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_TickGenerator_0_0/design_1_TickGenerator_0_0/design_1_TickGenerator_0_0_in_context.xdc] for cell 'design_1_i/TickGenerator_0' +Finished Parsing XDC File [d:/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_TickGenerator_0_0/design_1_TickGenerator_0_0/design_1_TickGenerator_0_0_in_context.xdc] for cell 'design_1_i/TickGenerator_0' +Parsing XDC File [d:/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_GameController_0_0/design_1_GameController_0_0/design_1_GameController_0_0_in_context.xdc] for cell 'design_1_i/GameController_0' +Finished Parsing XDC File [d:/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_GameController_0_0/design_1_GameController_0_0/design_1_GameController_0_0_in_context.xdc] for cell 'design_1_i/GameController_0' +Parsing XDC File [D:/GitHub/SW2/SW2.srcs/constrs_1/new/mainconstraint.xdc] +Finished Parsing XDC File [D:/GitHub/SW2/SW2.srcs/constrs_1/new/mainconstraint.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/GitHub/SW2/SW2.srcs/constrs_1/new/mainconstraint.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. -Parsing XDC File [C:/Users/lab/Documents/GitHub/SW2/SW2.srcs/constrs_1/new/sideconstraint.xdc] -Finished Parsing XDC File [C:/Users/lab/Documents/GitHub/SW2/SW2.srcs/constrs_1/new/sideconstraint.xdc] -INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/lab/Documents/GitHub/SW2/SW2.srcs/constrs_1/new/sideconstraint.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc]. +Parsing XDC File [D:/GitHub/SW2/SW2.srcs/constrs_1/new/sideconstraint.xdc] +Finished Parsing XDC File [D:/GitHub/SW2/SW2.srcs/constrs_1/new/sideconstraint.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/GitHub/SW2/SW2.srcs/constrs_1/new/sideconstraint.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. -Parsing XDC File [C:/Users/lab/Documents/GitHub/SW2/SW2.runs/synth_1/dont_touch.xdc] -Finished Parsing XDC File [C:/Users/lab/Documents/GitHub/SW2/SW2.runs/synth_1/dont_touch.xdc] +Parsing XDC File [D:/GitHub/SW2/SW2.runs/synth_1/dont_touch.xdc] +Finished Parsing XDC File [D:/GitHub/SW2/SW2.runs/synth_1/dont_touch.xdc] Completed Processing XDC Constraints -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1811.898 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1919.059 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1811.898 ; gain = 0.000 +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1919.059 ; gain = 0.000 INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 1811.898 ; gain = 331.883 +Finished Constraint Validation : Time (s): cpu = 00:00:56 ; elapsed = 00:01:06 . Memory (MB): peak = 1919.059 ; gain = 337.477 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information @@ -130,16 +137,16 @@ Start Loading Part and Timing Information Loading part: xczu3eg-sfvc784-2-e INFO: [Synth 8-6742] Reading net delay rules and data --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 1811.898 ; gain = 331.883 +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:56 ; elapsed = 00:01:06 . Memory (MB): peak = 1919.059 ; gain = 337.477 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 1811.898 ; gain = 331.883 +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:56 ; elapsed = 00:01:06 . Memory (MB): peak = 1919.059 ; gain = 337.477 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 1811.898 ; gain = 331.883 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:56 ; elapsed = 00:01:06 . Memory (MB): peak = 1919.059 ; gain = 337.477 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics @@ -160,27 +167,26 @@ Finished Part Resource Summary --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- -WARNING: [Synth 8-7080] Parallel synthesis criteria is not met --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 1811.898 ; gain = 331.883 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:00 ; elapsed = 00:01:10 . Memory (MB): peak = 1919.059 ; gain = 337.477 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:33 ; elapsed = 00:00:35 . Memory (MB): peak = 2517.480 ; gain = 1037.465 +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:18 ; elapsed = 00:01:29 . Memory (MB): peak = 2623.102 ; gain = 1041.520 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:35 . Memory (MB): peak = 2517.480 ; gain = 1037.465 +Finished Timing Optimization : Time (s): cpu = 00:01:18 ; elapsed = 00:01:29 . Memory (MB): peak = 2623.102 ; gain = 1041.520 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:33 ; elapsed = 00:00:35 . Memory (MB): peak = 2527.320 ; gain = 1047.305 +Finished Technology Mapping : Time (s): cpu = 00:01:18 ; elapsed = 00:01:29 . Memory (MB): peak = 2632.875 ; gain = 1051.293 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion @@ -198,37 +204,37 @@ Start Final Netlist Cleanup Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:38 ; elapsed = 00:00:39 . Memory (MB): peak = 2762.801 ; gain = 1282.785 +Finished IO Insertion : Time (s): cpu = 00:01:25 ; elapsed = 00:01:37 . Memory (MB): peak = 2883.344 ; gain = 1301.762 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:38 ; elapsed = 00:00:39 . Memory (MB): peak = 2762.801 ; gain = 1282.785 +Finished Renaming Generated Instances : Time (s): cpu = 00:01:25 ; elapsed = 00:01:37 . Memory (MB): peak = 2883.344 ; gain = 1301.762 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:38 ; elapsed = 00:00:39 . Memory (MB): peak = 2762.801 ; gain = 1282.785 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:25 ; elapsed = 00:01:37 . Memory (MB): peak = 2883.344 ; gain = 1301.762 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:38 ; elapsed = 00:00:39 . Memory (MB): peak = 2762.801 ; gain = 1282.785 +Finished Renaming Generated Ports : Time (s): cpu = 00:01:25 ; elapsed = 00:01:37 . Memory (MB): peak = 2883.344 ; gain = 1301.762 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:38 ; elapsed = 00:00:39 . Memory (MB): peak = 2762.801 ; gain = 1282.785 +Finished Handling Custom Attributes : Time (s): cpu = 00:01:25 ; elapsed = 00:01:37 . Memory (MB): peak = 2883.344 ; gain = 1301.762 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:38 ; elapsed = 00:00:39 . Memory (MB): peak = 2762.801 ; gain = 1282.785 +Finished Renaming Generated Nets : Time (s): cpu = 00:01:25 ; elapsed = 00:01:37 . Memory (MB): peak = 2883.344 ; gain = 1301.762 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -266,28 +272,28 @@ Report Cell Usage: |11 |OBUF | 11| +------+---------------------------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:38 ; elapsed = 00:00:39 . Memory (MB): peak = 2762.801 ; gain = 1282.785 +Finished Writing Synthesis Report : Time (s): cpu = 00:01:25 ; elapsed = 00:01:37 . Memory (MB): peak = 2883.344 ; gain = 1301.762 --------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 1 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 2762.801 ; gain = 1259.328 -Synthesis Optimization Complete : Time (s): cpu = 00:00:38 ; elapsed = 00:00:40 . Memory (MB): peak = 2762.801 ; gain = 1282.785 +Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:42 ; elapsed = 00:01:16 . Memory (MB): peak = 2883.344 ; gain = 1290.156 +Synthesis Optimization Complete : Time (s): cpu = 00:01:25 ; elapsed = 00:01:37 . Memory (MB): peak = 2883.344 ; gain = 1301.762 INFO: [Project 1-571] Translating synthesized netlist -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 2762.801 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 2883.344 ; gain = 0.000 INFO: [Netlist 29-17] Analyzing 3 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2762.801 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2883.344 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: A total of 3 instances were transformed. IBUF => IBUF (IBUFCTRL, INBUF): 3 instances Synth Design complete | Checksum: c2a7d55c INFO: [Common 17-83] Releasing license: Synthesis -48 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. +47 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:51 . Memory (MB): peak = 2762.801 ; gain = 2205.805 -Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2762.801 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/lab/Documents/GitHub/SW2/SW2.runs/synth_1/design_1_wrapper.dcp' has been generated. +synth_design: Time (s): cpu = 00:01:41 ; elapsed = 00:02:00 . Memory (MB): peak = 2883.344 ; gain = 2296.492 +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2883.344 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'D:/GitHub/SW2/SW2.runs/synth_1/design_1_wrapper.dcp' has been generated. INFO: [Vivado 12-24828] Executing command : report_utilization -file design_1_wrapper_utilization_synth.rpt -pb design_1_wrapper_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Tue Jun 9 14:05:37 2026... +INFO: [Common 17-206] Exiting Vivado at Mon Jun 22 10:06:47 2026... diff --git a/SW2.runs/synth_1/design_1_wrapper_utilization_synth.pb b/SW2.runs/synth_1/design_1_wrapper_utilization_synth.pb index 80e025f..a77becf 100644 Binary files a/SW2.runs/synth_1/design_1_wrapper_utilization_synth.pb and b/SW2.runs/synth_1/design_1_wrapper_utilization_synth.pb differ diff --git a/SW2.runs/synth_1/design_1_wrapper_utilization_synth.rpt b/SW2.runs/synth_1/design_1_wrapper_utilization_synth.rpt index d172b07..7536b25 100644 --- a/SW2.runs/synth_1/design_1_wrapper_utilization_synth.rpt +++ b/SW2.runs/synth_1/design_1_wrapper_utilization_synth.rpt @@ -1,8 +1,8 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2025.1 (win64) Build 6140274 Thu May 22 00:12:29 MDT 2025 -| Date : Tue Jun 9 14:05:37 2026 -| Host : Lab016-04 running 64-bit major release (build 9200) +| Tool Version : Vivado v.2025.2 (win64) Build 6299465 Fri Nov 14 19:35:11 GMT 2025 +| Date : Mon Jun 22 10:06:47 2026 +| Host : DESKTOP-FMR4U99 running 64-bit major release (build 9200) | Command : report_utilization -file design_1_wrapper_utilization_synth.rpt -pb design_1_wrapper_utilization_synth.pb | Design : design_1_wrapper | Device : xczu3eg-sfvc784-2-e @@ -42,10 +42,12 @@ Table of Contents | F7 Muxes | 0 | 0 | 0 | 35280 | 0.00 | | F8 Muxes | 0 | 0 | 0 | 17640 | 0.00 | | F9 Muxes | 0 | 0 | 0 | 8820 | 0.00 | +| Unique Control Sets | 0 | | 0 | 17640 | 0.00 | +-------------------------+------+-------+------------+-----------+-------+ * Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. Warning! LUT value is adjusted to account for LUT combining. Warning! For any ECO changes, please run place_design if there are unplaced instances +** Note: Available Control Sets calculated as Slices * 2, Review the Control Sets Report for more information regarding control sets. 1.1 Summary of Registers by Type diff --git a/SW2.runs/synth_1/dfx_runtime.txt b/SW2.runs/synth_1/dfx_runtime.txt index 82250fc..e83fb3e 100644 --- a/SW2.runs/synth_1/dfx_runtime.txt +++ b/SW2.runs/synth_1/dfx_runtime.txt @@ -1,2 +1,2 @@ DFXRuntime Profile Report: -Total Application(DFX) Runtime : CPU : 0:0:6 WALL : 0:0:0 0.00 % +Total Application(DFX) Runtime : CPU : 0:0:15 WALL : 0:0:0 0.00 % diff --git a/SW2.runs/synth_1/dont_touch.xdc b/SW2.runs/synth_1/dont_touch.xdc index ff94725..7613c60 100644 --- a/SW2.runs/synth_1/dont_touch.xdc +++ b/SW2.runs/synth_1/dont_touch.xdc @@ -35,4 +35,4 @@ set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_1_Ti # IP: bd/design_1/ip/design_1_GameController_0_0/design_1_GameController_0_0.xci set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_1_GameController_0_0 || ORIG_REF_NAME==design_1_GameController_0_0} -quiet] -quiet -# XDC: c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/design_1_ooc.xdc +# XDC: d:/GitHub/SW2/SW2.gen/sources_1/bd/design_1/design_1_ooc.xdc diff --git a/SW2.runs/synth_1/gen_run.xml b/SW2.runs/synth_1/gen_run.xml index c5da21f..6e9e48e 100644 --- a/SW2.runs/synth_1/gen_run.xml +++ b/SW2.runs/synth_1/gen_run.xml @@ -1,5 +1,5 @@ - + diff --git a/SW2.runs/synth_1/incr_synth_reason.pb b/SW2.runs/synth_1/incr_synth_reason.pb index 4cb4ed4..d9eb4a2 100644 --- a/SW2.runs/synth_1/incr_synth_reason.pb +++ b/SW2.runs/synth_1/incr_synth_reason.pb @@ -1 +1 @@ - 6No compile time benefit to using incremental synthesis \ No newline at end of file + jNo compile time benfit as the reference checkpoint is from an old version of Vivado. Synthesis will re-run \ No newline at end of file diff --git a/SW2.runs/impl_1/project.wdf b/SW2.runs/synth_1/project.wdf similarity index 92% rename from SW2.runs/impl_1/project.wdf rename to SW2.runs/synth_1/project.wdf index 2db9452..0705b62 100644 --- a/SW2.runs/impl_1/project.wdf +++ b/SW2.runs/synth_1/project.wdf @@ -15,13 +15,13 @@ version:1 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c456e656d79436f6e74726f6c6c65725f76315f305f315c64657369676e5f315f456e656d79436f6e74726f6c6c65725f305f30:636f72655f636f6e7461696e6572:66616c7365:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c47616d65436f6e74726f6c6c65725f76315f305f315c64657369676e5f315f47616d65436f6e74726f6c6c65725f305f30:636f72655f636f6e7461696e6572:66616c7365:00:00 -70726f6a656374:69705f636f72655f636f6e7461696e65725c48444d495f54585f76315f305f325c64657369676e5f315f48444d495f54585f305f30:636f72655f636f6e7461696e6572:66616c7365:00:00 +70726f6a656374:69705f636f72655f636f6e7461696e65725c3c6970636f72656e616d653e5c64657369676e5f315f48444d495f54585f305f30:636f72655f636f6e7461696e6572:66616c7365:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c496d6747656e5f76315f305f315c64657369676e5f315f496d6747656e5f305f30:636f72655f636f6e7461696e6572:66616c7365:00:00 -70726f6a656374:69705f636f72655f636f6e7461696e65725c526f74617279456e635f76315f305f325c64657369676e5f315f526f74617279456e635f305f30:636f72655f636f6e7461696e6572:66616c7365:00:00 +70726f6a656374:69705f636f72655f636f6e7461696e65725c3c6970636f72656e616d653e5c64657369676e5f315f526f74617279456e635f305f30:636f72655f636f6e7461696e6572:66616c7365:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c5469636b47656e657261746f725f76315f305f315c64657369676e5f315f5469636b47656e657261746f725f305f30:636f72655f636f6e7461696e6572:66616c7365:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c566964656f54696d696e675f76315f305f315c64657369676e5f315f566964656f54696d696e675f305f30:636f72655f636f6e7461696e6572:66616c7365:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c616e676c655f656e636f6465725f76315f305f315c64657369676e5f315f616e676c655f656e636f6465725f315f30:636f72655f636f6e7461696e6572:66616c7365:00:00 -70726f6a656374:69705f636f72655f636f6e7461696e65725c636c6b5f77697a5f76365f305f31365c64657369676e5f315f636c6b5f77697a5f305f30:636f72655f636f6e7461696e6572:66616c7365:00:00 +70726f6a656374:69705f636f72655f636f6e7461696e65725c636c6b5f77697a5f76365f305f31375c64657369676e5f315f636c6b5f77697a5f305f30:636f72655f636f6e7461696e6572:66616c7365:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00 @@ -37,4 +37,4 @@ version:1 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3035336130333030646433653466373961373565336532313065663264323435:506172656e742050412070726f6a656374204944:00 -eof:3944841604 +eof:2441052501 diff --git a/SW2.runs/synth_1/rundef.js b/SW2.runs/synth_1/rundef.js index e63439b..ecd61d5 100644 --- a/SW2.runs/synth_1/rundef.js +++ b/SW2.runs/synth_1/rundef.js @@ -9,9 +9,9 @@ var WshShell = new ActiveXObject( "WScript.Shell" ); var ProcEnv = WshShell.Environment( "Process" ); var PathVal = ProcEnv("PATH"); if ( PathVal.length == 0 ) { - PathVal = "C:/Xilinx/2025.1/Vitis/bin;C:/Xilinx/2025.1/Vivado/ids_lite/ISE/bin/nt64;C:/Xilinx/2025.1/Vivado/ids_lite/ISE/lib/nt64;C:/Xilinx/2025.1/Vivado/bin;"; + PathVal = "D:/Pobrane/AMDDesignTools/2025.2/Vitis/bin;D:/Pobrane/AMDDesignTools/2025.2/Vivado/bin;"; } else { - PathVal = "C:/Xilinx/2025.1/Vitis/bin;C:/Xilinx/2025.1/Vivado/ids_lite/ISE/bin/nt64;C:/Xilinx/2025.1/Vivado/ids_lite/ISE/lib/nt64;C:/Xilinx/2025.1/Vivado/bin;" + PathVal; + PathVal = "D:/Pobrane/AMDDesignTools/2025.2/Vitis/bin;D:/Pobrane/AMDDesignTools/2025.2/Vivado/bin;" + PathVal; } ProcEnv("PATH") = PathVal; diff --git a/SW2.runs/synth_1/runme.log b/SW2.runs/synth_1/runme.log index 55deebf..de1cd79 100644 --- a/SW2.runs/synth_1/runme.log +++ b/SW2.runs/synth_1/runme.log @@ -1,122 +1,126 @@ -*** Halting run - EA reset detected *** - - *** Running vivado with args -log design_1_wrapper.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source design_1_wrapper.tcl -****** Vivado v2025.1 (64-bit) - **** SW Build 6140274 on Thu May 22 00:12:29 MDT 2025 - **** IP Build 6138677 on Thu May 22 03:10:11 MDT 2025 - **** SharedData Build 6139179 on Tue May 20 17:58:58 MDT 2025 - **** Start of session at: Tue Jun 9 14:04:36 2026 +****** Vivado v2025.2 (64-bit) + **** SW Build 6299465 on Fri Nov 14 19:35:11 GMT 2025 + **** IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025 + **** SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025 + **** Start of session at: Mon Jun 22 10:04:16 2026 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ** Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. -Sourcing tcl script 'C:/Users/lab/AppData/Roaming/Xilinx/Vivado/Vivado_init.tcl' source design_1_wrapper.tcl -notrace -create_project: Time (s): cpu = 00:00:22 ; elapsed = 00:00:05 . Memory (MB): peak = 507.602 ; gain = 227.941 +create_project: Time (s): cpu = 00:00:21 ; elapsed = 00:00:15 . Memory (MB): peak = 530.863 ; gain = 219.363 INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Xilinx/IP_Repo'. -WARNING: [IP_Flow 19-3685] Ignored loading user repository 'c:/Xilinx/IP_Repo/OLED_ASCII'. The path is contained within another repository. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/2025.1/Vivado/data/ip'. -Command: read_checkpoint -auto_incremental -incremental C:/Users/lab/Documents/GitHub/SW2/SW2.srcs/utils_1/imports/synth_1/ImgGen.dcp -INFO: [Vivado 12-5825] Read reference checkpoint from C:/Users/lab/Documents/GitHub/SW2/SW2.srcs/utils_1/imports/synth_1/ImgGen.dcp for incremental synthesis +WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'd:/GitHub/SW2/SW2.runs/Xilinx/IP_Repo'; Can't find the specified path. +If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. +WARNING: [IP_Flow 19-3685] Ignored loading user repository 'd:/GitHub/SW2/SW2.runs/Xilinx/IP_Repo/OLED_ASCII'. The path is contained within another repository. +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Pobrane/AMDDesignTools/2025.2/Vivado/data/ip'. +WARNING: [BD 41-1661] One or more IPs have been locked in the design 'design_1.bd'. Please run report_ip_status for more details and recommendations on how to fix this issue. +List of locked IPs: +design_1_HDMI_TX_0_0 +design_1_clk_wiz_0_0 +design_1_RotaryEnc_0_0 + +Command: read_checkpoint -auto_incremental -incremental D:/GitHub/SW2/SW2.srcs/utils_1/imports/synth_1/ImgGen.dcp +INFO: [Vivado 12-5825] Read reference checkpoint from D:/GitHub/SW2/SW2.srcs/utils_1/imports/synth_1/ImgGen.dcp for incremental synthesis INFO: [Vivado 12-7989] Please ensure there are no constraint changes Command: synth_design -top design_1_wrapper -part xczu3eg-sfvc784-2-e Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xczu3eg' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xczu3eg' +WARNING: [Vivado_Tcl 4-1809] The reference checkpoint is from an old version of Vivado; A full resynthesis flow will be run INFO: [Device 21-403] Loading part xczu3eg-sfvc784-2-e INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} -INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 6 processes. +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes -INFO: [Synth 8-7075] Helper process launched with PID 9840 ---------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1681.172 ; gain = 201.156 ---------------------------------------------------------------------------------- -INFO: [Synth 8-6157] synthesizing module 'design_1_wrapper' [C:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v:13] -INFO: [Synth 8-6157] synthesizing module 'design_1' [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/synth/design_1.v:13] -INFO: [Synth 8-6157] synthesizing module 'design_1_EnemyController_0_0' [C:/Users/lab/Documents/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-12296-Lab016-04/realtime/design_1_EnemyController_0_0_stub.v:6] -INFO: [Synth 8-6155] done synthesizing module 'design_1_EnemyController_0_0' (0#1) [C:/Users/lab/Documents/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-12296-Lab016-04/realtime/design_1_EnemyController_0_0_stub.v:6] -INFO: [Synth 8-6157] synthesizing module 'design_1_GameController_0_0' [C:/Users/lab/Documents/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-12296-Lab016-04/realtime/design_1_GameController_0_0_stub.v:6] -INFO: [Synth 8-6155] done synthesizing module 'design_1_GameController_0_0' (0#1) [C:/Users/lab/Documents/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-12296-Lab016-04/realtime/design_1_GameController_0_0_stub.v:6] -INFO: [Synth 8-6157] synthesizing module 'design_1_HDMI_TX_0_0' [C:/Users/lab/Documents/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-12296-Lab016-04/realtime/design_1_HDMI_TX_0_0_stub.v:6] -INFO: [Synth 8-6155] done synthesizing module 'design_1_HDMI_TX_0_0' (0#1) [C:/Users/lab/Documents/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-12296-Lab016-04/realtime/design_1_HDMI_TX_0_0_stub.v:6] -INFO: [Synth 8-6157] synthesizing module 'design_1_ImgGen_0_0' [C:/Users/lab/Documents/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-12296-Lab016-04/realtime/design_1_ImgGen_0_0_stub.v:6] -INFO: [Synth 8-6155] done synthesizing module 'design_1_ImgGen_0_0' (0#1) [C:/Users/lab/Documents/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-12296-Lab016-04/realtime/design_1_ImgGen_0_0_stub.v:6] -INFO: [Synth 8-6157] synthesizing module 'design_1_RotaryEnc_0_0' [C:/Users/lab/Documents/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-12296-Lab016-04/realtime/design_1_RotaryEnc_0_0_stub.v:6] -INFO: [Synth 8-6155] done synthesizing module 'design_1_RotaryEnc_0_0' (0#1) [C:/Users/lab/Documents/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-12296-Lab016-04/realtime/design_1_RotaryEnc_0_0_stub.v:6] -INFO: [Synth 8-6157] synthesizing module 'design_1_TickGenerator_0_0' [C:/Users/lab/Documents/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-12296-Lab016-04/realtime/design_1_TickGenerator_0_0_stub.v:6] -INFO: [Synth 8-6155] done synthesizing module 'design_1_TickGenerator_0_0' (0#1) [C:/Users/lab/Documents/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-12296-Lab016-04/realtime/design_1_TickGenerator_0_0_stub.v:6] -INFO: [Synth 8-6157] synthesizing module 'design_1_VideoTiming_0_0' [C:/Users/lab/Documents/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-12296-Lab016-04/realtime/design_1_VideoTiming_0_0_stub.v:6] -INFO: [Synth 8-6155] done synthesizing module 'design_1_VideoTiming_0_0' (0#1) [C:/Users/lab/Documents/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-12296-Lab016-04/realtime/design_1_VideoTiming_0_0_stub.v:6] -INFO: [Synth 8-6157] synthesizing module 'design_1_angle_encoder_1_0' [C:/Users/lab/Documents/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-12296-Lab016-04/realtime/design_1_angle_encoder_1_0_stub.v:6] -INFO: [Synth 8-6155] done synthesizing module 'design_1_angle_encoder_1_0' (0#1) [C:/Users/lab/Documents/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-12296-Lab016-04/realtime/design_1_angle_encoder_1_0_stub.v:6] -INFO: [Synth 8-6157] synthesizing module 'design_1_clk_wiz_0_0' [C:/Users/lab/Documents/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-12296-Lab016-04/realtime/design_1_clk_wiz_0_0_stub.v:6] -INFO: [Synth 8-6155] done synthesizing module 'design_1_clk_wiz_0_0' (0#1) [C:/Users/lab/Documents/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-12296-Lab016-04/realtime/design_1_clk_wiz_0_0_stub.v:6] -INFO: [Synth 8-6155] done synthesizing module 'design_1' (0#1) [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/synth/design_1.v:13] -INFO: [Synth 8-6155] done synthesizing module 'design_1_wrapper' (0#1) [C:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v:13] ---------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1788.441 ; gain = 308.426 +INFO: [Synth 8-7075] Helper process launched with PID 19304 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1787.391 ; gain = 205.809 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'design_1_wrapper' [D:/GitHub/SW2/SW2.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v:13] +INFO: [Synth 8-6157] synthesizing module 'design_1' [d:/GitHub/SW2/SW2.gen/sources_1/bd/design_1/synth/design_1.v:13] +INFO: [Synth 8-6157] synthesizing module 'design_1_EnemyController_0_0' [D:/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-25072-DESKTOP-FMR4U99/realtime/design_1_EnemyController_0_0_stub.v:6] +INFO: [Synth 8-6155] done synthesizing module 'design_1_EnemyController_0_0' (0#1) [D:/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-25072-DESKTOP-FMR4U99/realtime/design_1_EnemyController_0_0_stub.v:6] +INFO: [Synth 8-6157] synthesizing module 'design_1_GameController_0_0' [D:/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-25072-DESKTOP-FMR4U99/realtime/design_1_GameController_0_0_stub.v:6] +INFO: [Synth 8-6155] done synthesizing module 'design_1_GameController_0_0' (0#1) [D:/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-25072-DESKTOP-FMR4U99/realtime/design_1_GameController_0_0_stub.v:6] +INFO: [Synth 8-6157] synthesizing module 'design_1_HDMI_TX_0_0' [D:/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-25072-DESKTOP-FMR4U99/realtime/design_1_HDMI_TX_0_0_stub.v:6] +INFO: [Synth 8-6155] done synthesizing module 'design_1_HDMI_TX_0_0' (0#1) [D:/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-25072-DESKTOP-FMR4U99/realtime/design_1_HDMI_TX_0_0_stub.v:6] +INFO: [Synth 8-6157] synthesizing module 'design_1_ImgGen_0_0' [D:/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-25072-DESKTOP-FMR4U99/realtime/design_1_ImgGen_0_0_stub.v:6] +INFO: [Synth 8-6155] done synthesizing module 'design_1_ImgGen_0_0' (0#1) [D:/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-25072-DESKTOP-FMR4U99/realtime/design_1_ImgGen_0_0_stub.v:6] +INFO: [Synth 8-6157] synthesizing module 'design_1_RotaryEnc_0_0' [D:/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-25072-DESKTOP-FMR4U99/realtime/design_1_RotaryEnc_0_0_stub.v:6] +INFO: [Synth 8-6155] done synthesizing module 'design_1_RotaryEnc_0_0' (0#1) [D:/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-25072-DESKTOP-FMR4U99/realtime/design_1_RotaryEnc_0_0_stub.v:6] +INFO: [Synth 8-6157] synthesizing module 'design_1_TickGenerator_0_0' [D:/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-25072-DESKTOP-FMR4U99/realtime/design_1_TickGenerator_0_0_stub.v:6] +INFO: [Synth 8-6155] done synthesizing module 'design_1_TickGenerator_0_0' (0#1) [D:/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-25072-DESKTOP-FMR4U99/realtime/design_1_TickGenerator_0_0_stub.v:6] +INFO: [Synth 8-6157] synthesizing module 'design_1_VideoTiming_0_0' [D:/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-25072-DESKTOP-FMR4U99/realtime/design_1_VideoTiming_0_0_stub.v:6] +INFO: [Synth 8-6155] done synthesizing module 'design_1_VideoTiming_0_0' (0#1) [D:/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-25072-DESKTOP-FMR4U99/realtime/design_1_VideoTiming_0_0_stub.v:6] +INFO: [Synth 8-6157] synthesizing module 'design_1_angle_encoder_1_0' [D:/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-25072-DESKTOP-FMR4U99/realtime/design_1_angle_encoder_1_0_stub.v:6] +INFO: [Synth 8-6155] done synthesizing module 'design_1_angle_encoder_1_0' (0#1) [D:/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-25072-DESKTOP-FMR4U99/realtime/design_1_angle_encoder_1_0_stub.v:6] +INFO: [Synth 8-6157] synthesizing module 'design_1_clk_wiz_0_0' [D:/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-25072-DESKTOP-FMR4U99/realtime/design_1_clk_wiz_0_0_stub.v:6] +INFO: [Synth 8-6155] done synthesizing module 'design_1_clk_wiz_0_0' (0#1) [D:/GitHub/SW2/SW2.runs/synth_1/.Xil/Vivado-25072-DESKTOP-FMR4U99/realtime/design_1_clk_wiz_0_0_stub.v:6] +INFO: [Synth 8-6155] done synthesizing module 'design_1' (0#1) [d:/GitHub/SW2/SW2.gen/sources_1/bd/design_1/synth/design_1.v:13] +INFO: [Synth 8-6155] done synthesizing module 'design_1_wrapper' (0#1) [D:/GitHub/SW2/SW2.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v:13] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1907.453 ; gain = 325.871 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1788.441 ; gain = 308.426 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 1907.453 ; gain = 325.871 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1788.441 ; gain = 308.426 +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 1907.453 ; gain = 325.871 --------------------------------------------------------------------------------- -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1788.441 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1907.453 ; gain = 0.000 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine -Parsing XDC File [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0_in_context.xdc] for cell 'design_1_i/clk_wiz_0' -create_clock: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1811.898 ; gain = 13.551 -Finished Parsing XDC File [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0_in_context.xdc] for cell 'design_1_i/clk_wiz_0' -Parsing XDC File [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_HDMI_TX_0_0/design_1_HDMI_TX_0_0/design_1_HDMI_TX_0_0_in_context.xdc] for cell 'design_1_i/HDMI_TX_0' -Finished Parsing XDC File [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_HDMI_TX_0_0/design_1_HDMI_TX_0_0/design_1_HDMI_TX_0_0_in_context.xdc] for cell 'design_1_i/HDMI_TX_0' -Parsing XDC File [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_VideoTiming_0_0/design_1_VideoTiming_0_0/design_1_VideoTiming_0_0_in_context.xdc] for cell 'design_1_i/VideoTiming_0' -Finished Parsing XDC File [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_VideoTiming_0_0/design_1_VideoTiming_0_0/design_1_VideoTiming_0_0_in_context.xdc] for cell 'design_1_i/VideoTiming_0' -Parsing XDC File [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_ImgGen_0_0/design_1_ImgGen_0_0/design_1_ImgGen_0_0_in_context.xdc] for cell 'design_1_i/ImgGen_0' -Finished Parsing XDC File [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_ImgGen_0_0/design_1_ImgGen_0_0/design_1_ImgGen_0_0_in_context.xdc] for cell 'design_1_i/ImgGen_0' -Parsing XDC File [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_RotaryEnc_0_0/design_1_RotaryEnc_0_0/design_1_RotaryEnc_0_0_in_context.xdc] for cell 'design_1_i/RotaryEnc_0' -Finished Parsing XDC File [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_RotaryEnc_0_0/design_1_RotaryEnc_0_0/design_1_RotaryEnc_0_0_in_context.xdc] for cell 'design_1_i/RotaryEnc_0' -Parsing XDC File [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_angle_encoder_1_0/design_1_angle_encoder_1_0/design_1_angle_encoder_1_0_in_context.xdc] for cell 'design_1_i/angle_encoder_1' -Finished Parsing XDC File [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_angle_encoder_1_0/design_1_angle_encoder_1_0/design_1_angle_encoder_1_0_in_context.xdc] for cell 'design_1_i/angle_encoder_1' -Parsing XDC File [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_EnemyController_0_0/design_1_EnemyController_0_0/design_1_EnemyController_0_0_in_context.xdc] for cell 'design_1_i/EnemyController_0' -Finished Parsing XDC File [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_EnemyController_0_0/design_1_EnemyController_0_0/design_1_EnemyController_0_0_in_context.xdc] for cell 'design_1_i/EnemyController_0' -Parsing XDC File [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_TickGenerator_0_0/design_1_TickGenerator_0_0/design_1_TickGenerator_0_0_in_context.xdc] for cell 'design_1_i/TickGenerator_0' -Finished Parsing XDC File [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_TickGenerator_0_0/design_1_TickGenerator_0_0/design_1_TickGenerator_0_0_in_context.xdc] for cell 'design_1_i/TickGenerator_0' -Parsing XDC File [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_GameController_0_0/design_1_GameController_0_0/design_1_GameController_0_0_in_context.xdc] for cell 'design_1_i/GameController_0' -Finished Parsing XDC File [c:/Users/lab/Documents/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_GameController_0_0/design_1_GameController_0_0/design_1_GameController_0_0_in_context.xdc] for cell 'design_1_i/GameController_0' -Parsing XDC File [C:/Users/lab/Documents/GitHub/SW2/SW2.srcs/constrs_1/new/mainconstraint.xdc] -Finished Parsing XDC File [C:/Users/lab/Documents/GitHub/SW2/SW2.srcs/constrs_1/new/mainconstraint.xdc] -INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/lab/Documents/GitHub/SW2/SW2.srcs/constrs_1/new/mainconstraint.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc]. +Parsing XDC File [d:/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0_in_context.xdc] for cell 'design_1_i/clk_wiz_0' +create_clock: Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1919.059 ; gain = 11.605 +Finished Parsing XDC File [d:/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0_in_context.xdc] for cell 'design_1_i/clk_wiz_0' +Parsing XDC File [d:/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_HDMI_TX_0_0/design_1_HDMI_TX_0_0/design_1_HDMI_TX_0_0_in_context.xdc] for cell 'design_1_i/HDMI_TX_0' +Finished Parsing XDC File [d:/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_HDMI_TX_0_0/design_1_HDMI_TX_0_0/design_1_HDMI_TX_0_0_in_context.xdc] for cell 'design_1_i/HDMI_TX_0' +Parsing XDC File [d:/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_VideoTiming_0_0/design_1_VideoTiming_0_0/design_1_VideoTiming_0_0_in_context.xdc] for cell 'design_1_i/VideoTiming_0' +Finished Parsing XDC File [d:/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_VideoTiming_0_0/design_1_VideoTiming_0_0/design_1_VideoTiming_0_0_in_context.xdc] for cell 'design_1_i/VideoTiming_0' +Parsing XDC File [d:/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_ImgGen_0_0/design_1_ImgGen_0_0/design_1_ImgGen_0_0_in_context.xdc] for cell 'design_1_i/ImgGen_0' +Finished Parsing XDC File [d:/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_ImgGen_0_0/design_1_ImgGen_0_0/design_1_ImgGen_0_0_in_context.xdc] for cell 'design_1_i/ImgGen_0' +Parsing XDC File [d:/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_RotaryEnc_0_0/design_1_RotaryEnc_0_0/design_1_RotaryEnc_0_0_in_context.xdc] for cell 'design_1_i/RotaryEnc_0' +Finished Parsing XDC File [d:/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_RotaryEnc_0_0/design_1_RotaryEnc_0_0/design_1_RotaryEnc_0_0_in_context.xdc] for cell 'design_1_i/RotaryEnc_0' +Parsing XDC File [d:/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_angle_encoder_1_0/design_1_angle_encoder_1_0/design_1_angle_encoder_1_0_in_context.xdc] for cell 'design_1_i/angle_encoder_1' +Finished Parsing XDC File [d:/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_angle_encoder_1_0/design_1_angle_encoder_1_0/design_1_angle_encoder_1_0_in_context.xdc] for cell 'design_1_i/angle_encoder_1' +Parsing XDC File [d:/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_EnemyController_0_0/design_1_EnemyController_0_0/design_1_EnemyController_0_0_in_context.xdc] for cell 'design_1_i/EnemyController_0' +Finished Parsing XDC File [d:/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_EnemyController_0_0/design_1_EnemyController_0_0/design_1_EnemyController_0_0_in_context.xdc] for cell 'design_1_i/EnemyController_0' +Parsing XDC File [d:/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_TickGenerator_0_0/design_1_TickGenerator_0_0/design_1_TickGenerator_0_0_in_context.xdc] for cell 'design_1_i/TickGenerator_0' +Finished Parsing XDC File [d:/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_TickGenerator_0_0/design_1_TickGenerator_0_0/design_1_TickGenerator_0_0_in_context.xdc] for cell 'design_1_i/TickGenerator_0' +Parsing XDC File [d:/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_GameController_0_0/design_1_GameController_0_0/design_1_GameController_0_0_in_context.xdc] for cell 'design_1_i/GameController_0' +Finished Parsing XDC File [d:/GitHub/SW2/SW2.gen/sources_1/bd/design_1/ip/design_1_GameController_0_0/design_1_GameController_0_0/design_1_GameController_0_0_in_context.xdc] for cell 'design_1_i/GameController_0' +Parsing XDC File [D:/GitHub/SW2/SW2.srcs/constrs_1/new/mainconstraint.xdc] +Finished Parsing XDC File [D:/GitHub/SW2/SW2.srcs/constrs_1/new/mainconstraint.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/GitHub/SW2/SW2.srcs/constrs_1/new/mainconstraint.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. -Parsing XDC File [C:/Users/lab/Documents/GitHub/SW2/SW2.srcs/constrs_1/new/sideconstraint.xdc] -Finished Parsing XDC File [C:/Users/lab/Documents/GitHub/SW2/SW2.srcs/constrs_1/new/sideconstraint.xdc] -INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/lab/Documents/GitHub/SW2/SW2.srcs/constrs_1/new/sideconstraint.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc]. +Parsing XDC File [D:/GitHub/SW2/SW2.srcs/constrs_1/new/sideconstraint.xdc] +Finished Parsing XDC File [D:/GitHub/SW2/SW2.srcs/constrs_1/new/sideconstraint.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/GitHub/SW2/SW2.srcs/constrs_1/new/sideconstraint.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. -Parsing XDC File [C:/Users/lab/Documents/GitHub/SW2/SW2.runs/synth_1/dont_touch.xdc] -Finished Parsing XDC File [C:/Users/lab/Documents/GitHub/SW2/SW2.runs/synth_1/dont_touch.xdc] +Parsing XDC File [D:/GitHub/SW2/SW2.runs/synth_1/dont_touch.xdc] +Finished Parsing XDC File [D:/GitHub/SW2/SW2.runs/synth_1/dont_touch.xdc] Completed Processing XDC Constraints -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1811.898 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1919.059 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1811.898 ; gain = 0.000 +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1919.059 ; gain = 0.000 INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 1811.898 ; gain = 331.883 +Finished Constraint Validation : Time (s): cpu = 00:00:56 ; elapsed = 00:01:06 . Memory (MB): peak = 1919.059 ; gain = 337.477 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information @@ -124,16 +128,16 @@ Start Loading Part and Timing Information Loading part: xczu3eg-sfvc784-2-e INFO: [Synth 8-6742] Reading net delay rules and data --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 1811.898 ; gain = 331.883 +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:56 ; elapsed = 00:01:06 . Memory (MB): peak = 1919.059 ; gain = 337.477 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 1811.898 ; gain = 331.883 +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:56 ; elapsed = 00:01:06 . Memory (MB): peak = 1919.059 ; gain = 337.477 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 1811.898 ; gain = 331.883 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:56 ; elapsed = 00:01:06 . Memory (MB): peak = 1919.059 ; gain = 337.477 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics @@ -154,27 +158,26 @@ Finished Part Resource Summary --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- -WARNING: [Synth 8-7080] Parallel synthesis criteria is not met --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 1811.898 ; gain = 331.883 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:00 ; elapsed = 00:01:10 . Memory (MB): peak = 1919.059 ; gain = 337.477 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:33 ; elapsed = 00:00:35 . Memory (MB): peak = 2517.480 ; gain = 1037.465 +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:18 ; elapsed = 00:01:29 . Memory (MB): peak = 2623.102 ; gain = 1041.520 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:35 . Memory (MB): peak = 2517.480 ; gain = 1037.465 +Finished Timing Optimization : Time (s): cpu = 00:01:18 ; elapsed = 00:01:29 . Memory (MB): peak = 2623.102 ; gain = 1041.520 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:33 ; elapsed = 00:00:35 . Memory (MB): peak = 2527.320 ; gain = 1047.305 +Finished Technology Mapping : Time (s): cpu = 00:01:18 ; elapsed = 00:01:29 . Memory (MB): peak = 2632.875 ; gain = 1051.293 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion @@ -192,37 +195,37 @@ Start Final Netlist Cleanup Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:38 ; elapsed = 00:00:39 . Memory (MB): peak = 2762.801 ; gain = 1282.785 +Finished IO Insertion : Time (s): cpu = 00:01:25 ; elapsed = 00:01:37 . Memory (MB): peak = 2883.344 ; gain = 1301.762 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:38 ; elapsed = 00:00:39 . Memory (MB): peak = 2762.801 ; gain = 1282.785 +Finished Renaming Generated Instances : Time (s): cpu = 00:01:25 ; elapsed = 00:01:37 . Memory (MB): peak = 2883.344 ; gain = 1301.762 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:38 ; elapsed = 00:00:39 . Memory (MB): peak = 2762.801 ; gain = 1282.785 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:25 ; elapsed = 00:01:37 . Memory (MB): peak = 2883.344 ; gain = 1301.762 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:38 ; elapsed = 00:00:39 . Memory (MB): peak = 2762.801 ; gain = 1282.785 +Finished Renaming Generated Ports : Time (s): cpu = 00:01:25 ; elapsed = 00:01:37 . Memory (MB): peak = 2883.344 ; gain = 1301.762 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:38 ; elapsed = 00:00:39 . Memory (MB): peak = 2762.801 ; gain = 1282.785 +Finished Handling Custom Attributes : Time (s): cpu = 00:01:25 ; elapsed = 00:01:37 . Memory (MB): peak = 2883.344 ; gain = 1301.762 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:38 ; elapsed = 00:00:39 . Memory (MB): peak = 2762.801 ; gain = 1282.785 +Finished Renaming Generated Nets : Time (s): cpu = 00:01:25 ; elapsed = 00:01:37 . Memory (MB): peak = 2883.344 ; gain = 1301.762 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -260,28 +263,28 @@ Report Cell Usage: |11 |OBUF | 11| +------+---------------------------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:38 ; elapsed = 00:00:39 . Memory (MB): peak = 2762.801 ; gain = 1282.785 +Finished Writing Synthesis Report : Time (s): cpu = 00:01:25 ; elapsed = 00:01:37 . Memory (MB): peak = 2883.344 ; gain = 1301.762 --------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 1 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 2762.801 ; gain = 1259.328 -Synthesis Optimization Complete : Time (s): cpu = 00:00:38 ; elapsed = 00:00:40 . Memory (MB): peak = 2762.801 ; gain = 1282.785 +Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:42 ; elapsed = 00:01:16 . Memory (MB): peak = 2883.344 ; gain = 1290.156 +Synthesis Optimization Complete : Time (s): cpu = 00:01:25 ; elapsed = 00:01:37 . Memory (MB): peak = 2883.344 ; gain = 1301.762 INFO: [Project 1-571] Translating synthesized netlist -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 2762.801 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 2883.344 ; gain = 0.000 INFO: [Netlist 29-17] Analyzing 3 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2762.801 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2883.344 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: A total of 3 instances were transformed. IBUF => IBUF (IBUFCTRL, INBUF): 3 instances Synth Design complete | Checksum: c2a7d55c INFO: [Common 17-83] Releasing license: Synthesis -48 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. +47 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:51 . Memory (MB): peak = 2762.801 ; gain = 2205.805 -Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2762.801 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/lab/Documents/GitHub/SW2/SW2.runs/synth_1/design_1_wrapper.dcp' has been generated. +synth_design: Time (s): cpu = 00:01:41 ; elapsed = 00:02:00 . Memory (MB): peak = 2883.344 ; gain = 2296.492 +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2883.344 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'D:/GitHub/SW2/SW2.runs/synth_1/design_1_wrapper.dcp' has been generated. INFO: [Vivado 12-24828] Executing command : report_utilization -file design_1_wrapper_utilization_synth.rpt -pb design_1_wrapper_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Tue Jun 9 14:05:37 2026... +INFO: [Common 17-206] Exiting Vivado at Mon Jun 22 10:06:47 2026... diff --git a/SW2.runs/synth_1/runme.sh b/SW2.runs/synth_1/runme.sh index 2394a03..6ff1134 100644 --- a/SW2.runs/synth_1/runme.sh +++ b/SW2.runs/synth_1/runme.sh @@ -1,4 +1,4 @@ -#!/bin/sh +#!/bin/bash # # Vivado(TM) @@ -12,9 +12,9 @@ echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executi exit if [ -z "$PATH" ]; then - PATH=C:/Xilinx/2025.1/Vitis/bin;C:/Xilinx/2025.1/Vivado/ids_lite/ISE/bin/nt64;C:/Xilinx/2025.1/Vivado/ids_lite/ISE/lib/nt64:C:/Xilinx/2025.1/Vivado/bin + PATH=D:/Pobrane/AMDDesignTools/2025.2/Vitis/bin:D:/Pobrane/AMDDesignTools/2025.2/Vivado/bin else - PATH=C:/Xilinx/2025.1/Vitis/bin;C:/Xilinx/2025.1/Vivado/ids_lite/ISE/bin/nt64;C:/Xilinx/2025.1/Vivado/ids_lite/ISE/lib/nt64:C:/Xilinx/2025.1/Vivado/bin:$PATH + PATH=D:/Pobrane/AMDDesignTools/2025.2/Vitis/bin:D:/Pobrane/AMDDesignTools/2025.2/Vivado/bin:$PATH fi export PATH @@ -25,7 +25,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='C:/Users/lab/Documents/GitHub/SW2/SW2.runs/synth_1' +HD_PWD='D:/GitHub/SW2/SW2.runs/synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/SW2.runs/synth_1/vivado.jou b/SW2.runs/synth_1/vivado.jou index d0796d1..6812ca3 100644 --- a/SW2.runs/synth_1/vivado.jou +++ b/SW2.runs/synth_1/vivado.jou @@ -1,24 +1,24 @@ #----------------------------------------------------------- -# Vivado v2025.1 (64-bit) -# SW Build 6140274 on Thu May 22 00:12:29 MDT 2025 -# IP Build 6138677 on Thu May 22 03:10:11 MDT 2025 -# SharedData Build 6139179 on Tue May 20 17:58:58 MDT 2025 -# Start of session at: Tue Jun 9 14:04:36 2026 -# Process ID : 12296 -# Current directory : C:/Users/lab/Documents/GitHub/SW2/SW2.runs/synth_1 +# Vivado v2025.2 (64-bit) +# SW Build 6299465 on Fri Nov 14 19:35:11 GMT 2025 +# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025 +# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025 +# Start of session at: Mon Jun 22 10:04:16 2026 +# Process ID : 25072 +# Current directory : D:/GitHub/SW2/SW2.runs/synth_1 # Command line : vivado.exe -log design_1_wrapper.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source design_1_wrapper.tcl -# Log file : C:/Users/lab/Documents/GitHub/SW2/SW2.runs/synth_1/design_1_wrapper.vds -# Journal file : C:/Users/lab/Documents/GitHub/SW2/SW2.runs/synth_1\vivado.jou -# Running On : Lab016-04 +# Log file : D:/GitHub/SW2/SW2.runs/synth_1/design_1_wrapper.vds +# Journal file : D:/GitHub/SW2/SW2.runs/synth_1\vivado.jou +# Running On : DESKTOP-FMR4U99 # Platform : Windows Server 2016 or Windows 10 -# Operating System : 19045 -# Processor Detail : Intel(R) Core(TM) i7-8700 CPU @ 3.20GHz -# CPU Frequency : 3192 MHz -# CPU Physical cores : 6 -# CPU Logical cores : 12 -# Host memory : 17030 MB -# Swap memory : 2550 MB -# Total Virtual : 19580 MB -# Available Virtual : 12243 MB +# Operating System : 26200 +# Processor Detail : Intel(R) Core(TM) i3-8130U CPU @ 2.20GHz +# CPU Frequency : 2208 MHz +# CPU Physical cores : 2 +# CPU Logical cores : 4 +# Host memory : 12781 MB +# Swap memory : 3418 MB +# Total Virtual : 16200 MB +# Available Virtual : 4088 MB #----------------------------------------------------------- source design_1_wrapper.tcl -notrace diff --git a/SW2.runs/synth_1/vivado.pb b/SW2.runs/synth_1/vivado.pb index 45a85fb..ace1db0 100644 Binary files a/SW2.runs/synth_1/vivado.pb and b/SW2.runs/synth_1/vivado.pb differ diff --git a/SW2.srcs/sources_1/new/EnemyController.vhd b/SW2.srcs/sources_1/new/EnemyController.vhd index cc27f6f..e8c5094 100644 --- a/SW2.srcs/sources_1/new/EnemyController.vhd +++ b/SW2.srcs/sources_1/new/EnemyController.vhd @@ -32,7 +32,7 @@ begin variable rand_angle : integer range 0 to 23; variable feedback : std_logic; begin - if RstN = '1' + if RstN = '0' then lfsr <= x"ACE1"; for i in 0 to 23 loop diff --git a/SW2.srcs/sources_1/new/GameController.vhd b/SW2.srcs/sources_1/new/GameController.vhd index df48e59..600de81 100644 --- a/SW2.srcs/sources_1/new/GameController.vhd +++ b/SW2.srcs/sources_1/new/GameController.vhd @@ -1,46 +1,52 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; -- Dodane do łatwych operacji matematycznych (odejmowanie) +use IEEE.NUMERIC_STD.ALL; entity GameController is Port ( Clk : in STD_LOGIC; - RstN : in STD_LOGIC; -- Reset aktywny stanem niskim - hit : in STD_LOGIC; -- Impuls uderzenia z EnemyController - Health : out STD_LOGIC_VECTOR (2 downto 0) -- Wyjście na wyświetlacz/grafikę + RstN : in STD_LOGIC; + hit : in STD_LOGIC; + Health : out STD_LOGIC_VECTOR (2 downto 0) -- 3 bity idące prosto do PL_USER_LED ); end GameController; architecture Behavioral of GameController is - -- Rejestr przechowujący aktualną liczbę żyć (np. startujemy od 3, max 7 przy 3 bitach) signal health_reg : unsigned(2 downto 0); + signal hit_delayed : STD_LOGIC := '0'; - constant MAX_HEALTH : unsigned(2 downto 0) := "011"; -- Startowe 3 życia (w binarnym) + constant MAX_HEALTH : unsigned(2 downto 0) := "011"; -- Startowe 3 życia (liczbowo 3) begin + -- 1. Proces zarządzania logiką gry (odejmowanie żyć) process(Clk, RstN) begin - -- 1. Resetowanie stanu gry (np. po przegranej lub uruchomieniu) if RstN = '0' then health_reg <= MAX_HEALTH; + hit_delayed <= '0'; - -- 2. Logika synchroniczna z zegarem elsif rising_edge(Clk) then + hit_delayed <= hit; - -- Reagujemy na impuls 'hit' - if hit = '1' then + -- Reagujemy na moment uderzenia (zbocze narastające) + if hit = '1' and hit_delayed = '0' then if health_reg > 0 then - health_reg <= health_reg - 1; -- Zmniejsz życie o 1 - else - -- Opcjonalnie: Gracz ma już 0 żyć (Game Over) - health_reg <= "000"; -- Zabezpieczenie przed przepełnieniem (underflow) + health_reg <= health_reg - 1; end if; end if; end if; end process; - -- Przypisanie rejestru do portu wyjściowego z rzutowaniem na STD_LOGIC_VECTOR - Health <= std_logic_vector(health_reg); + -- 2. Proces kombinacyjny: Zapalanie odpowiedniej liczby diod (pasek zdrowia) + process(health_reg) + begin + case health_reg is + when "011" => Health <= "111"; -- 3 życia = świecą się 3 diody + when "010" => Health <= "011"; -- 2 życia = świecą się 2 diody + when "001" => Health <= "001"; -- 1 życie = świeci się 1 dioda + when others => Health <= "000"; -- 0 żyć = wszystkie diody zgaszone (Game Over) + end case; + end process; end Behavioral; \ No newline at end of file diff --git a/SW2.srcs/utils_1/imports/synth_1/ImgGen.dcp b/SW2.srcs/utils_1/imports/synth_1/ImgGen.dcp index daac235..fe47363 100644 Binary files a/SW2.srcs/utils_1/imports/synth_1/ImgGen.dcp and b/SW2.srcs/utils_1/imports/synth_1/ImgGen.dcp differ diff --git a/SW2.xpr b/SW2.xpr index 3a305af..8c34cb0 100644 --- a/SW2.xpr +++ b/SW2.xpr @@ -1,10 +1,10 @@ - + - + @@ -225,6 +224,14 @@