feat: SystemVerilog / Verilog / UVM support — structural graph with composition + TLM#382
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Recognize .sv/.svh/.v/.vh and build a deterministic HDL knowledge graph capturing the RTL module hierarchy and, for UVM, the component composition tree (Type::type_id::create) and the TLM data path (a.b.connect(c.d)) — so a UVM testbench renders as one test-rooted tree, not disconnected inheritance fan-out. - languages/configs/systemverilog.ts: language config + HDL/UVM concepts - plugins/parsers/systemverilog-parser.ts: zero-dep regex AnalyzerPlugin (structural backend + fallback when the WASM grammar is unavailable) - plugins/parsers/systemverilog-treesitter.ts: tree-sitter-systemverilog backend — accurate AST extraction, same HdlAnalysis shape - analyzer/hdl-graph.ts: parser-agnostic assembler emitting module/class/ function nodes + contains/depends_on/inherits/publishes edges and layers - scripts/analyze-hdl.mjs: CLI (tree-sitter primary, regex fallback) - tests + a self-contained 15-file uvm_demo fixture asserting the testbench converges into a single tree rooted at the UVM test Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
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Summary
Adds recognition of SystemVerilog/Verilog (
.sv.svh.v.vh) and a deterministic HDL knowledge graph. For RTL it captures the module instantiation hierarchy; for UVM it extracts the component composition tree (Type::type_id::create(...)) and the TLM data path (a.b.connect(c.d)), so a UVM testbench renders as one tree rooted at the test instead of a disconnected inheritance fan-out.Two parser backends behind one
HdlAnalysisshape:.wasmgrammar, loaded exactly like the existing grammars.AnalyzerPluginfor the standard structural pipeline; used when the WASM grammar can't load.The deterministic assembler (
assembleHdlGraph) is parser-agnostic — both backends produce an identical graph. Reuses existing edge types:contains,depends_on(instantiation + composition),inherits,publishes(TLM).Linked issue(s)
None — happy to open a tracking issue if you'd prefer to discuss the approach first.
How I tested this
pnpm lintpnpm --filter @understand-anything/core test— 720 passing, incl. SV parser/assembler unit tests, a tree-sitter↔regex equivalence integration test, and a self-contained 15-fileuvm_demofixture whose test asserts (by graph traversal) that the whole testbench is reachable fromdut_base_testvia composition.pnpm test— the only failures locally are 9 pre-existing, env-specific ones unrelated to this change (worktree path separators / a Python merge script / tree-sitter init on Windows). CI will confirm on Linux.node scripts/analyze-hdl.mjs <uvm_project>→ 57 nodes / 55 edges; the UVM layer shows the fulldut_base_test → env → agent → {driver, monitor, sequencer}+ scoreboard tree, plus TLMmonitor→scoreboard/driver→sequencer. The tree-sitter and regex backends produce identical graphs.Versioning
Notes for review
This adds a deterministic HDL assembler (
buildHdlGraph/buildHdlGraphTreeSitter) alongside the existingGraphBuilder, so the SV/UVM design edges (instantiation, inheritance, UVM composition, TLM) can be produced and asserted without an LLM run. The parser sits behind a seam (regex ↔ tree-sitter) and the assembler is parser-agnostic. Happy to adjust the architecture to your taste — e.g. fold the extraction into the existing tree-sitterLanguageExtractorpipeline, or drop the regex fallback.🤖 Generated with Claude Code