memory_array.vhd

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

ENTITY memory_arr IS
    PORT (
        clk      : IN  std_logic;
        we       : IN  std_logic;
        addre1   : IN  std_logic_vector(2 DOWNTO 0);
        addre2   : IN  std_logic_vector(2 DOWNTO 0);
        addwe    : IN  std_logic_vector(2 DOWNTO 0);
        datain   : IN  std_logic_vector(7 DOWNTO 0);
        portout1 : OUT std_logic_vector(7 DOWNTO 0);
        portout2 : OUT std_logic_vector(7 DOWNTO 0)
    );
END ENTITY memory_arr;

ARCHITECTURE sync_memory_arr OF memory_arr IS
    TYPE memory_type IS ARRAY(0 TO 7) OF std_logic_vector(7 DOWNTO 0);
    SIGNAL memory : memory_type;
BEGIN
    PROCESS(clk)
    BEGIN
        IF rising_edge(clk) THEN
            IF we = '1' THEN
                memory(to_integer(unsigned(addwe))) <= datain;
            END IF;
        END IF;
    END PROCESS;

    portout1 <= memory(to_integer(unsigned(addre1)));
    portout2 <= memory(to_integer(unsigned(addre2)));
END ARCHITECTURE sync_memory_arr;