diff --git a/img2col.sv b/img2col.sv
deleted file mode 100644
index 81e3cb9..0000000
--- a/img2col.sv
+++ /dev/null
@@ -1,10 +0,0 @@
-module img2col(
-    
-);
-    
-
-
-
-
-
-endmodule
\ No newline at end of file
diff --git a/rtl/PU_CTRL.sv b/rtl/PU_CTRL.sv
new file mode 100644
index 0000000..a8fd43a
--- /dev/null
+++ b/rtl/PU_CTRL.sv
@@ -0,0 +1,254 @@
+module PU_CTRL
+  #(parameter pooling_units = 32,
+    parameter H = 5)
+   (
+     input logic clk, nrst,
+     input logic [2:0] pooling_inst, start_pool, array_dim,
+     output logic in_pipe_en, out_pipe_en, max_avg, done,
+     output logic [4:0] address [3:0]
+   );
+
+  enum logic [1:0] {start       = 2'b00,
+                    data_adress = 2'b01,
+                    pipe_ip     = 2'b10,
+                    finish      = 2'b11} next_state, current_state;
+
+  // inst   max/avg     |  pooling instruction
+  //         1 / 0      |         01
+  logic [2:0] inst;
+  logic [4:0] temp_add [3:0];
+  logic [3:0] current_count, next_count;
+
+  always_ff @(posedge clk, negedge nrst)
+  begin
+    if(!nrst)
+    begin
+      current_state <= start;
+      inst <= '0;
+      current_count <= '0;
+      temp_add <= '{default:5'h00};
+    end
+    else
+    begin
+      current_state <= next_state;
+      current_count <= next_count;
+      if(start_pool)
+    	begin
+        inst <= pooling_inst;
+        temp_add <= address;
+	    end
+      else
+        inst <= inst;
+    end
+  end
+
+
+  // next state logic
+  always_comb
+  begin
+    in_pipe_en  = 0;
+    out_pipe_en = 0;
+    max_avg     = 1;
+    next_state  = current_state;
+    next_count  = current_count;
+    address     = temp_add;
+
+    unique case (current_state)
+             start:
+             begin
+               if(start_pool)
+               begin
+                 next_count = '0;
+                 next_state = data_adress;
+               end
+               else
+               begin
+                 next_count = '0;
+                 next_state = current_state;
+               end
+             end
+
+             data_adress:
+             begin
+               // here we will generate data addresses
+
+               next_state = pipe_ip;
+               if (current_count > 0)
+               begin
+                 out_pipe_en = 1;
+                 case (current_count)
+                   4'h1:
+                   begin
+                     address[0] = address[0] + 2;
+                     address[2] = address[0] + array_dim;
+                     if (array_dim == 3'h3) begin
+                       address[1] = 5'd31;
+                       address[3] = 5'd31;
+                     end 
+                     else begin
+                     address[1] = address[0] + 1;
+                     address[3] = address[0] + array_dim + 1;  
+                     end
+                   end
+
+
+                   4'h2:
+                   begin
+                     case (array_dim)
+                      3'h3:
+                      begin
+                        address[0] = address[0] + 4;
+                        address[1] = address[0] + 1;
+                        address[2] = 5'd31;
+                        address[3] = 5'd31;
+                      end
+
+                      3'h4:
+                      begin
+                        address[0] = address[0] + 6;
+                        address[1] = address[0] + 1;
+                        address[2] = address[0] + array_dim;
+                        address[3] = address[0] + array_dim + 1;
+                      end
+
+
+                      3'h5:
+                      begin
+                        address[0] = address[0] + 2;
+                        address[1] = 5'd31;
+                        address[2] = address[0] + array_dim;
+                        address[3] = 5'd31;
+                      end 
+                    endcase
+                   end
+
+
+                   4'h3:
+                   begin
+                     case (array_dim)
+                       3'h3:
+                       begin
+                        address[0] = address[0] + 2;
+                        address[1] = 5'd31;
+                        address[2] = 5'd31;
+                        address[3] = 5'd31;
+                       end
+                       3'h4:
+                       begin
+                        address[0] = address[0] + 2;
+                        address[1] = address[0] + 1;
+                        address[2] = address[0] + array_dim;
+                        address[3] = address[0] + array_dim + 1;
+                       end
+
+                       3'h5:
+                       begin
+                        address[0] = address[0] + 6;
+                        address[1] = address[0] + 1;
+                        address[2] = address[0] + array_dim;
+                        address[3] = address[0] + array_dim + 1;
+                        end
+                     endcase
+                   end
+
+
+                   4'h4:
+                   begin
+                    address[0] = address[0] + 2;
+                    address[1] = address[0] + 1;
+                    address[2] = address[0] + array_dim;
+                    address[3] = address[0] + array_dim + 1;
+                   end
+
+
+                   4'h5:
+                   begin
+                    address[0] = address[0] + 2;
+                    address[1] = 5'd31;
+                    address[2] = address[0] + array_dim;
+                    address[3] = 5'd31;
+                   end
+                   4'h6:
+                   begin
+                    address[0] = address[0] + 6;
+                    address[1] = address[0] + 1;
+                    address[2] = 5'd31;
+                    address[3] = 5'd31;
+                   end
+                   4'h7:
+                   begin
+                    address[0] = address[0] + 2;
+                    address[1] = address[0] + 1;
+                    address[2] = 5'd31;
+                    address[3] = 5'd31;
+                   end
+                   4'h8:
+                   begin
+                    address[0] = address[0] + 2;
+                    address[1] = 5'd31;
+                    address[2] = 5'd31;
+                    address[3] = 5'd31;
+                   end
+                 endcase
+               end
+               else
+               begin
+                 out_pipe_en = 0;
+                 address[0] = 5'b0;
+                 address[1] = address[0] + 1;
+                 address[2] = address[0] + array_dim;
+                 address[3] = address[0] + array_dim + 1;
+               end
+              end
+
+             pipe_ip:
+             begin
+               in_pipe_en = 1;
+               max_avg    = inst[2];
+               //next_count = current_count + 1;
+               unique case (array_dim)
+                 3'h3, 3'h4:
+                   if (current_count == 4'h3)
+                   begin
+                     next_state = finish;
+                     next_count = '0;
+                   end
+                   else
+                   begin
+                     next_state = data_adress;
+                     next_count = current_count + 1;
+                   end
+
+                 3'h5:
+                   if (current_count == 4'h8)
+                   begin
+                     next_state = finish;
+                     next_count = '0;
+                   end
+                   else
+                   begin
+                     next_state = data_adress;
+                     next_count = current_count + 1;
+                   end
+               endcase
+             end
+
+             finish:
+             begin
+               next_state = start;
+               out_pipe_en = 0;
+               in_pipe_en = 0;
+               done = 1;
+             end
+             default:
+             begin
+               next_state = start;
+               next_count = '0;
+             end
+
+           endcase
+         end
+
+
+endmodule
+
diff --git a/rtl/col2img.sv b/rtl/col2img.sv
new file mode 100644
index 0000000..4ca24b8
--- /dev/null
+++ b/rtl/col2img.sv
@@ -0,0 +1,33 @@
+module col2img#
+    (parameter  data_width = 8 
+     parameter in_vec_size =28 )(
+    input logic clk, 
+    input logic nrst , 
+    output logic [data_width-1:0] out_img [in_vec_size-1:0][in_vec_size-1:0] ,
+    input logic in_valid  , 
+    input logic [data_width:0] cols [(in_vec_size^2)-1:0] 
+    );
+  
+
+    always_comb begin
+
+        if(nrst)
+            begin
+            generate genvar i , j ;
+                for (i=0 , i < in_vec_size , i = i+1 ) ;
+                    begin
+                        for (j=0 , j < in_vec_size , j = i+1 ) ;
+                            begin
+                                out_img[i][j]= cols[i*in_vec_size+j] ;  
+                                 
+                            end
+                    end
+                    
+            endgenerate      
+
+           end     
+        else begin
+           out_img=0; 
+        end
+
+    end
diff --git a/rtl/img2col.sv b/rtl/img2col.sv
new file mode 100644
index 0000000..4cac7f9
--- /dev/null
+++ b/rtl/img2col.sv
@@ -0,0 +1,45 @@
+module img2col#
+    (parameter  data_width = 8 
+     parameter img_size = 5 )(
+    input logic clk, 
+    input logic nrst , 
+    input logic [2:0] k , 
+    input logic stride ,
+    input logic [data_width-1:0] img [img_size-1:0][img_size-1:0] ,
+    input logic in_valid  , 
+        output logic [7:0] out_cols [31:0] 
+    );
+  
+    
+
+    always_comb begin
+
+        if(nrst)
+            begin
+            generate genvar i , j ;
+                for (i=0 , i < 5 , i = i+1 ) ;
+                    begin
+                        for (j=0 , j < 5 , j = i+1 ) ;
+                            begin
+                                out_cols[i*5+j] = img[i][j] ;  
+                                 
+                            end
+                    end
+                    
+            endgenerate      
+             out_cols[25:31]=0;      
+            end     
+        else begin
+           out_cols=0; 
+        end
+
+    end
+
+
+
+
+
+
+
+
+endmodule
diff --git a/rtl/output_buffer.sv b/rtl/output_buffer.sv
index f0da501..86f2a0e 100644
--- a/rtl/output_buffer.sv
+++ b/rtl/output_buffer.sv
@@ -4,7 +4,7 @@ module output_buffer
   )
   (
     input logic clk, nrst,
-    input logic Wr_ctrl [width-1:0],
+    input logic Wr_ctrl [width-1:0], en [width-1:0], 
     input logic [data_width-1:0] in [width-1:0],
     input logic [4:0] add_1 [width-1:0],
     input logic [4:0] add_2 [width-1:0],
@@ -23,6 +23,7 @@ module output_buffer
     for (i=0; i<width; i=i+1)
       Register_File RF(
                         .clk(clk), .nrst(nrst),
+                        .en(en[i]),
                         .Wr_ctrl(Wr_ctrl[i]),
                         .in(in[i]),
                         .add_1(add_1[i]),
diff --git a/rtl/parameter_calc.sv b/rtl/parameter_calc.sv
new file mode 100644
index 0000000..c2cac36
--- /dev/null
+++ b/rtl/parameter_calc.sv
@@ -0,0 +1,13 @@
+module parameter_calc(
+    input logic stride , input logic 
+);
+    
+
+always_comb begin
+    
+
+
+
+end
+
+endmodule
\ No newline at end of file
diff --git a/rtl/pooling_layer.sv b/rtl/pooling_layer.sv
index fe16b60..b657ad2 100644
--- a/rtl/pooling_layer.sv
+++ b/rtl/pooling_layer.sv
@@ -6,7 +6,7 @@ module pooling_layer
      parameter K = 2
    )
    (
-     input logic clk, nrst, ctrl_pool, start_pool,
+     input logic clk, nrst, ctrl_pool, in_pipe_en, out_pipe_en,
      input logic [data_width-1:0] pooling_in [pooling_units-1:0] [(K*S)-1:0],
      output logic [data_width-1:0] pooling_out [pooling_units-1:0]
    );
@@ -18,7 +18,7 @@ module pooling_layer
   begin: input_data_pipe
     if(!nrst)
       data_in <= '{default:0};
-    else if(start_pool)
+    else if(in_pipe_en)
       data_in <=  pooling_in;
     else
       data_in <= data_in;
@@ -42,8 +42,10 @@ module pooling_layer
   begin: out_data_pipe
     if(!nrst)
       pooling_out <= '{default:0};
-    else
+    else if (out_pipe_en)
       pooling_out <= data_out;
+    else
+      pooling_out <= pooling_out;
   end: out_data_pipe
 
 endmodule
diff --git a/rtl/regfile.sv b/rtl/regfile.sv
index 105f477..b157e45 100644
--- a/rtl/regfile.sv
+++ b/rtl/regfile.sv
@@ -3,7 +3,7 @@ module Register_File
      parameter data_width = 8
    )
   (
-    input logic clk, nrst, Wr_ctrl,
+    input logic clk, nrst, Wr_ctrl, en,
     input logic [data_width-1:0] in,
     input logic [4:0] add_1, add_2, add_3, add_4, add_in, //address bus
     output logic [data_width-1:0] out1, out2, out3, out4
@@ -15,8 +15,21 @@ module Register_File
   assign out3 = registers[add_3];
   assign out4 = registers[add_4];
 
-  always @ (posedge clk, negedge nrst) 
+  always_ff @ (posedge clk, negedge nrst) 
   begin
-  registers[add_in] = (Wr_ctrl) ? in : registers[add_in];
+    case (en)
+      0: registers[add_in] <= registers[add_in];
+      1: begin
+          if (!nrst)
+            begin
+            for (int i = 0; i < 32; i = i + 1)
+            registers[i] <= 32'h0;      // clear register file
+            end
+		      else
+          begin
+          registers[add_in] <= (Wr_ctrl) ? in : registers[add_in];
+          end
+        end
+    endcase
   end
-endmodule
\ No newline at end of file
+endmodule
diff --git a/rtl/testbench.sv b/rtl/testbench.sv
index a216d73..be49148 100644
--- a/rtl/testbench.sv
+++ b/rtl/testbench.sv
@@ -7,7 +7,7 @@ module pooling_layer_tb();
             S = 2;
 
   localparam T = 20; // clk period
-  logic clk, nrst, ctrl_pool, start_pool;
+  logic clk, nrst, ctrl_pool, in_pipe_en, out_pipe_en;
 
   logic [data_width-1:0] pooling_in [pooling_units-1:0] [(K*S)-1:0];
   logic [data_width-1:0] pooling_out [pooling_units-1:0];
@@ -38,18 +38,22 @@ module pooling_layer_tb();
   begin
     // initial inputs
     ctrl_pool = 1'b1;
-    start_pool = 1'b0;
+    in_pipe_en  = 1'b0;
+    out_pipe_en = 1'b0;
     pooling_in = '{default:8'h00};
     @(posedge nrst);
     @(negedge clk);
 
     // test max pooling
     ctrl_pool = 1'b1;
-    start_pool = 1'b1;
+    in_pipe_en = 1'b1;
     pooling_in = '{'{8'd1, 8'd5, 8'd6, 8'd7},
                    '{8'd2, 8'd1, 8'd8, 8'd9},
                    '{8'd3, 8'd1, 8'd2, 8'd4},
                    '{8'd4, 8'd5 ,8'd0 ,8'd1}};
+                   
+    @(negedge clk);
+    out_pipe_en = 1'b1;
 
     repeat(3) @(negedge clk);
     if (pooling_out[3] != 8'd7)