From a58c762468c19f88924560efa377ae66a8c94f16 Mon Sep 17 00:00:00 2001
From: marwan ibrahim zaki <50636605+marwanibrahim546@users.noreply.github.com>
Date: Sat, 2 Oct 2021 20:38:36 +0200
Subject: [PATCH 01/12] ,,

---
 img2col.sv | 10 ----------
 1 file changed, 10 deletions(-)
 delete mode 100644 img2col.sv

diff --git a/img2col.sv b/img2col.sv
deleted file mode 100644
index 81e3cb9..0000000
--- a/img2col.sv
+++ /dev/null
@@ -1,10 +0,0 @@
-module img2col(
-    
-);
-    
-
-
-
-
-
-endmodule
\ No newline at end of file

From 373e677521328b8aa65a104e4a5b642678be902a Mon Sep 17 00:00:00 2001
From: marwan ibrahim zaki <50636605+marwanibrahim546@users.noreply.github.com>
Date: Sat, 2 Oct 2021 20:39:25 +0200
Subject: [PATCH 02/12] ..

---
 rtl/img2col.sv | 5 +++++
 1 file changed, 5 insertions(+)
 create mode 100644 rtl/img2col.sv

diff --git a/rtl/img2col.sv b/rtl/img2col.sv
new file mode 100644
index 0000000..b0bd1ce
--- /dev/null
+++ b/rtl/img2col.sv
@@ -0,0 +1,5 @@
+module img2col(
+    
+);
+    
+endmodule
\ No newline at end of file

From 72781e1e98f67e1c1f08b2f0447e213b790677d9 Mon Sep 17 00:00:00 2001
From: marwan ibrahim zaki <50636605+marwanibrahim546@users.noreply.github.com>
Date: Sun, 3 Oct 2021 00:25:27 +0200
Subject: [PATCH 03/12] mmmmm

---
 rtl/col2img.sv        |  0
 rtl/img2col.sv        | 44 +++++++++++++++++++++++++++++++++++++++++--
 rtl/parameter_calc.sv | 13 +++++++++++++
 3 files changed, 55 insertions(+), 2 deletions(-)
 create mode 100644 rtl/col2img.sv
 create mode 100644 rtl/parameter_calc.sv

diff --git a/rtl/col2img.sv b/rtl/col2img.sv
new file mode 100644
index 0000000..e69de29
diff --git a/rtl/img2col.sv b/rtl/img2col.sv
index b0bd1ce..c8bb26f 100644
--- a/rtl/img2col.sv
+++ b/rtl/img2col.sv
@@ -1,5 +1,45 @@
-module img2col(
+module img2col#(parameter  data_width = 8 )(
+    input logic clk, 
+    input logic nrst , 
+    input logic [2:0] k , 
+    input logic stride ,
+    input logic [data_width-1:0] img [4:0][4:0] ,
+    input logic in_valid  , 
+    output logic [data_width-1 : 0 ] out_cols [31:0] 
     
-);
+    );
     
+    int counter = 0 ; 
+
+
+    always_comb begin
+
+        if(nrst)
+            begin
+            generate genvar i , j ;
+                for (i=0 , i < 5 , i = i+1 ) ;
+                    begin
+                        for (j=0 , j < 5 , j = i+1 ) ;
+                            begin
+                               out_cols[counter] = img[i][j] ;  
+                               counter++ ;   
+                            end
+                    end
+                if (counter == 24) counter = 0  ;     
+            endgenerate      
+
+           end     
+        else begin
+            // the output will bel zero 
+        end
+
+    end
+
+
+
+
+
+
+
+
 endmodule
\ No newline at end of file
diff --git a/rtl/parameter_calc.sv b/rtl/parameter_calc.sv
new file mode 100644
index 0000000..c2cac36
--- /dev/null
+++ b/rtl/parameter_calc.sv
@@ -0,0 +1,13 @@
+module parameter_calc(
+    input logic stride , input logic 
+);
+    
+
+always_comb begin
+    
+
+
+
+end
+
+endmodule
\ No newline at end of file

From 68e79e4fe6212cd1b041b9bb88c9123f97e03084 Mon Sep 17 00:00:00 2001
From: youssef mehdawy <82276385+youssefmehdawy99@users.noreply.github.com>
Date: Sun, 3 Oct 2021 23:43:13 +0200
Subject: [PATCH 04/12] Update img2col.sv

---
 rtl/img2col.sv | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/rtl/img2col.sv b/rtl/img2col.sv
index c8bb26f..785945a 100644
--- a/rtl/img2col.sv
+++ b/rtl/img2col.sv
@@ -9,8 +9,7 @@ module img2col#(parameter  data_width = 8 )(
     
     );
     
-    int counter = 0 ; 
-
+  
 
     always_comb begin
 
@@ -21,11 +20,11 @@ module img2col#(parameter  data_width = 8 )(
                     begin
                         for (j=0 , j < 5 , j = i+1 ) ;
                             begin
-                               out_cols[counter] = img[i][j] ;  
-                               counter++ ;   
+                                out_cols[i*5+j] = img[i][j] ;  
+                                 
                             end
                     end
-                if (counter == 24) counter = 0  ;     
+                    
             endgenerate      
 
            end     
@@ -42,4 +41,4 @@ module img2col#(parameter  data_width = 8 )(
 
 
 
-endmodule
\ No newline at end of file
+endmodule

From 0668f0fa1de3eb5a6a3c3caef7b771a02f90f316 Mon Sep 17 00:00:00 2001
From: marwan ibrahim zaki <50636605+marwanibrahim546@users.noreply.github.com>
Date: Sun, 3 Oct 2021 23:48:08 +0200
Subject: [PATCH 05/12] sss

---
 rtl/img2col.sv | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/rtl/img2col.sv b/rtl/img2col.sv
index 785945a..ff2e48b 100644
--- a/rtl/img2col.sv
+++ b/rtl/img2col.sv
@@ -1,14 +1,14 @@
-module img2col#(parameter  data_width = 8 )(
+module img2col#
+    (parameter  data_width = 8 
+     parameter img_size = 5 )(
     input logic clk, 
     input logic nrst , 
     input logic [2:0] k , 
     input logic stride ,
-    input logic [data_width-1:0] img [4:0][4:0] ,
+    input logic [data_width-1:0] img [img_size-1:0][img_size-1:0] ,
     input logic in_valid  , 
-    output logic [data_width-1 : 0 ] out_cols [31:0] 
-    
+    output logic [7:0] out_cols [24:0] 
     );
-    
   
 
     always_comb begin

From 6ba4567e31b831f4a695931d69126129e87b143f Mon Sep 17 00:00:00 2001
From: Raneem Alaa <raneemalaa55@gmail.com>
Date: Mon, 4 Oct 2021 20:02:53 +0200
Subject: [PATCH 06/12] adding reset and enable

---
 rtl/output_buffer.sv |  3 ++-
 rtl/regfile.sv       | 21 +++++++++++++++++----
 2 files changed, 19 insertions(+), 5 deletions(-)

diff --git a/rtl/output_buffer.sv b/rtl/output_buffer.sv
index f0da501..86f2a0e 100644
--- a/rtl/output_buffer.sv
+++ b/rtl/output_buffer.sv
@@ -4,7 +4,7 @@ module output_buffer
   )
   (
     input logic clk, nrst,
-    input logic Wr_ctrl [width-1:0],
+    input logic Wr_ctrl [width-1:0], en [width-1:0], 
     input logic [data_width-1:0] in [width-1:0],
     input logic [4:0] add_1 [width-1:0],
     input logic [4:0] add_2 [width-1:0],
@@ -23,6 +23,7 @@ module output_buffer
     for (i=0; i<width; i=i+1)
       Register_File RF(
                         .clk(clk), .nrst(nrst),
+                        .en(en[i]),
                         .Wr_ctrl(Wr_ctrl[i]),
                         .in(in[i]),
                         .add_1(add_1[i]),
diff --git a/rtl/regfile.sv b/rtl/regfile.sv
index 105f477..b157e45 100644
--- a/rtl/regfile.sv
+++ b/rtl/regfile.sv
@@ -3,7 +3,7 @@ module Register_File
      parameter data_width = 8
    )
   (
-    input logic clk, nrst, Wr_ctrl,
+    input logic clk, nrst, Wr_ctrl, en,
     input logic [data_width-1:0] in,
     input logic [4:0] add_1, add_2, add_3, add_4, add_in, //address bus
     output logic [data_width-1:0] out1, out2, out3, out4
@@ -15,8 +15,21 @@ module Register_File
   assign out3 = registers[add_3];
   assign out4 = registers[add_4];
 
-  always @ (posedge clk, negedge nrst) 
+  always_ff @ (posedge clk, negedge nrst) 
   begin
-  registers[add_in] = (Wr_ctrl) ? in : registers[add_in];
+    case (en)
+      0: registers[add_in] <= registers[add_in];
+      1: begin
+          if (!nrst)
+            begin
+            for (int i = 0; i < 32; i = i + 1)
+            registers[i] <= 32'h0;      // clear register file
+            end
+		      else
+          begin
+          registers[add_in] <= (Wr_ctrl) ? in : registers[add_in];
+          end
+        end
+    endcase
   end
-endmodule
\ No newline at end of file
+endmodule

From 4e18cf5c63d6e473469f38dff3b67df97ce51502 Mon Sep 17 00:00:00 2001
From: Moustafa Darwish <e.moustafa2@gmail.com>
Date: Sun, 10 Oct 2021 23:16:38 +0200
Subject: [PATCH 07/12] Pooling unit control

---
 rtl/PU_CTRL.sv       | 122 +++++++++++++++++++++++++++++++++++++++++++
 rtl/pooling_layer.sv |   8 +--
 rtl/testbench.sv     |  10 ++--
 3 files changed, 134 insertions(+), 6 deletions(-)
 create mode 100644 rtl/PU_CTRL.sv

diff --git a/rtl/PU_CTRL.sv b/rtl/PU_CTRL.sv
new file mode 100644
index 0000000..0435891
--- /dev/null
+++ b/rtl/PU_CTRL.sv
@@ -0,0 +1,122 @@
+module PU_CTRL
+  #(parameter pooling_units = 32,
+    parameter H = 5)
+   (
+     input logic clk, nrst,
+     input logic [2:0] pooling_inst, start_pool, array_dim,
+     output logic in_pipe_en, out_pipe_en, max_avg, done,
+     output logic [4:0] address [pooling_units-1:0]
+   );
+
+  enum logic [1:0] {start       = 2'b00,
+                    data_adress = 2'b01,
+                    pipe_ip     = 2'b10,
+                    finish      = 2'b11} next_state, current_state;
+
+  // inst   max/avg     |  pooling instruction
+  //         1 / 0      |         01
+  logic [2:0] inst, current_count, next_count;
+
+  always_ff @(posedge clk, negedge nrst)
+  begin
+    if(!nrst)
+    begin
+      current_state <= start;
+      inst <= '0;
+      current_count <= '0;
+    end
+    else
+    begin
+      current_state <= next_state;
+      current_count <= next_count;
+      if(start_pool)
+        inst <= pooling_inst;
+      else
+        inst <= inst;
+    end
+  end
+
+
+  // next state logic
+  always_comb
+  begin
+    in_pipe_en  = 0;
+    out_pipe_en = 0;
+    next_state  = current_state;
+    next_count  = current_count;
+
+    unique case (current_state)
+             start:
+             begin
+               if(start_pool)
+               begin
+                 next_count = '0;
+                 next_state = data_adress;
+               end
+               else
+               begin
+                 next_count = '0;
+                 next_state = current_state;
+               end
+             end
+
+             data_adress:
+             begin
+               // here we will generate data addresses
+               next_state = pipe_ip;
+               if (current_count > 0)
+                 out_pipe_en = 1;
+               else
+                 out_pipe_en = 0;
+             end
+
+             pipe_ip:
+             begin
+               in_pipe_en = 1;
+               //next_count = current_count + 1;
+               unique case (array_dim)
+                 3'h3, 3'h4:
+                   if (current_count == 3'h3)
+                   begin
+                     next_state = finish;
+                     next_count = '0;
+                   end
+                   else
+                   begin
+                     next_state = data_adress;
+                     next_count = current_count + 1;
+                   end
+
+                 3'h5:
+                   if (current_count == 3'h8)
+                   begin
+                     next_state = finish;
+                     next_count = '0;
+                   end
+                   else
+                   begin
+                     next_state = data_adress;
+                     next_count = current_count + 1;
+                   end
+               endcase
+             end
+
+             finish:
+             begin
+               next_state = start;
+               out_pipe_en = 0;
+               in_pipe_en = 0;
+               done = 1;
+             end
+             default:
+             begin
+               next_state = start;
+               next_count = '0;
+             end
+
+           endcase
+         end
+
+
+endmodule
+
diff --git a/rtl/pooling_layer.sv b/rtl/pooling_layer.sv
index fe16b60..b657ad2 100644
--- a/rtl/pooling_layer.sv
+++ b/rtl/pooling_layer.sv
@@ -6,7 +6,7 @@ module pooling_layer
      parameter K = 2
    )
    (
-     input logic clk, nrst, ctrl_pool, start_pool,
+     input logic clk, nrst, ctrl_pool, in_pipe_en, out_pipe_en,
      input logic [data_width-1:0] pooling_in [pooling_units-1:0] [(K*S)-1:0],
      output logic [data_width-1:0] pooling_out [pooling_units-1:0]
    );
@@ -18,7 +18,7 @@ module pooling_layer
   begin: input_data_pipe
     if(!nrst)
       data_in <= '{default:0};
-    else if(start_pool)
+    else if(in_pipe_en)
       data_in <=  pooling_in;
     else
       data_in <= data_in;
@@ -42,8 +42,10 @@ module pooling_layer
   begin: out_data_pipe
     if(!nrst)
       pooling_out <= '{default:0};
-    else
+    else if (out_pipe_en)
       pooling_out <= data_out;
+    else
+      pooling_out <= pooling_out;
   end: out_data_pipe
 
 endmodule
diff --git a/rtl/testbench.sv b/rtl/testbench.sv
index a216d73..be49148 100644
--- a/rtl/testbench.sv
+++ b/rtl/testbench.sv
@@ -7,7 +7,7 @@ module pooling_layer_tb();
             S = 2;
 
   localparam T = 20; // clk period
-  logic clk, nrst, ctrl_pool, start_pool;
+  logic clk, nrst, ctrl_pool, in_pipe_en, out_pipe_en;
 
   logic [data_width-1:0] pooling_in [pooling_units-1:0] [(K*S)-1:0];
   logic [data_width-1:0] pooling_out [pooling_units-1:0];
@@ -38,18 +38,22 @@ module pooling_layer_tb();
   begin
     // initial inputs
     ctrl_pool = 1'b1;
-    start_pool = 1'b0;
+    in_pipe_en  = 1'b0;
+    out_pipe_en = 1'b0;
     pooling_in = '{default:8'h00};
     @(posedge nrst);
     @(negedge clk);
 
     // test max pooling
     ctrl_pool = 1'b1;
-    start_pool = 1'b1;
+    in_pipe_en = 1'b1;
     pooling_in = '{'{8'd1, 8'd5, 8'd6, 8'd7},
                    '{8'd2, 8'd1, 8'd8, 8'd9},
                    '{8'd3, 8'd1, 8'd2, 8'd4},
                    '{8'd4, 8'd5 ,8'd0 ,8'd1}};
+                   
+    @(negedge clk);
+    out_pipe_en = 1'b1;
 
     repeat(3) @(negedge clk);
     if (pooling_out[3] != 8'd7)

From 953e8ac3e11361e9827973a642ef7cac0f918ca2 Mon Sep 17 00:00:00 2001
From: Raneem Alaa <raneemalaa55@gmail.com>
Date: Tue, 12 Oct 2021 05:11:31 +0200
Subject: [PATCH 08/12] generating data addresses

---
 rtl/PU_CTRL.sv | 140 +++++++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 135 insertions(+), 5 deletions(-)

diff --git a/rtl/PU_CTRL.sv b/rtl/PU_CTRL.sv
index 0435891..7161d0f 100644
--- a/rtl/PU_CTRL.sv
+++ b/rtl/PU_CTRL.sv
@@ -5,7 +5,7 @@ module PU_CTRL
      input logic clk, nrst,
      input logic [2:0] pooling_inst, start_pool, array_dim,
      output logic in_pipe_en, out_pipe_en, max_avg, done,
-     output logic [4:0] address [pooling_units-1:0]
+     output logic [4:0] address [3:0]
    );
 
   enum logic [1:0] {start       = 2'b00,
@@ -15,7 +15,9 @@ module PU_CTRL
 
   // inst   max/avg     |  pooling instruction
   //         1 / 0      |         01
-  logic [2:0] inst, current_count, next_count;
+  logic [2:0] inst;
+  logic [4:0] temp_add [3:0];
+  logic [3:0] current_count, next_count;
 
   always_ff @(posedge clk, negedge nrst)
   begin
@@ -24,13 +26,17 @@ module PU_CTRL
       current_state <= start;
       inst <= '0;
       current_count <= '0;
+      temp_add <= '{default:5'h00};
     end
     else
     begin
       current_state <= next_state;
       current_count <= next_count;
       if(start_pool)
+    	begin
         inst <= pooling_inst;
+        temp_add <= address;
+	    end
       else
         inst <= inst;
     end
@@ -44,6 +50,7 @@ module PU_CTRL
     out_pipe_en = 0;
     next_state  = current_state;
     next_count  = current_count;
+    address     = temp_add;
 
     unique case (current_state)
              start:
@@ -63,12 +70,135 @@ module PU_CTRL
              data_adress:
              begin
                // here we will generate data addresses
+
                next_state = pipe_ip;
                if (current_count > 0)
+               begin
                  out_pipe_en = 1;
+                 case (current_count)
+                   4'h1:
+                   begin
+                     address[0] = address[0] + 2;
+                     address[2] = address[0] + array_dim;
+                     if (array_dim == 3'h3) begin
+                       address[1] = 5'd31;
+                       address[3] = 5'd31;
+                     end 
+                     else begin
+                     address[1] = address[0] + 1;
+                     address[3] = address[0] + array_dim + 1;  
+                     end
+                   end
+
+
+                   4'h2:
+                   begin
+                     case (array_dim)
+                      3'h3:
+                      begin
+                        address[0] = address[0] + 4;
+                        address[1] = address[0] + 1;
+                        address[2] = 5'd31;
+                        address[3] = 5'd31;
+                      end
+
+                      3'h4:
+                      begin
+                        address[0] = address[0] + 6;
+                        address[1] = address[0] + 1;
+                        address[2] = address[0] + array_dim;
+                        address[3] = address[0] + array_dim + 1;
+                      end
+
+
+                      3'h5:
+                      begin
+                        address[0] = address[0] + 2;
+                        address[1] = 5'd31;
+                        address[2] = address[0] + array_dim;
+                        address[3] = 5'd31;
+                      end 
+                    endcase
+                   end
+
+
+                   4'h3:
+                   begin
+                     case (array_dim)
+                       3'h3:
+                       begin
+                        address[0] = address[0] + 2;
+                        address[1] = 5'd31;
+                        address[2] = 5'd31;
+                        address[3] = 5'd31;
+                       end
+                       3'h4:
+                       begin
+                        address[0] = address[0] + 2;
+                        address[1] = address[0] + 1;
+                        address[2] = address[0] + array_dim;
+                        address[3] = address[0] + array_dim + 1;
+                       end
+
+                       3'h5:
+                       begin
+                        address[0] = address[0] + 6;
+                        address[1] = address[0] + 1;
+                        address[2] = address[0] + array_dim;
+                        address[3] = address[0] + array_dim + 1;
+                        end
+                     endcase
+                   end
+
+
+                   4'h4:
+                   begin
+                    address[0] = address[0] + 2;
+                    address[1] = address[0] + 1;
+                    address[2] = address[0] + array_dim;
+                    address[3] = address[0] + array_dim + 1;
+                   end
+
+
+                   4'h5:
+                   begin
+                    address[0] = address[0] + 2;
+                    address[1] = 5'd31;
+                    address[2] = address[0] + array_dim;
+                    address[3] = 5'd31;
+                   end
+                   4'h6:
+                   begin
+                    address[0] = address[0] + 6;
+                    address[1] = address[0] + 1;
+                    address[2] = 5'd31;
+                    address[3] = 5'd31;
+                   end
+                   4'h7:
+                   begin
+                    address[0] = address[0] + 2;
+                    address[1] = address[0] + 1;
+                    address[2] = 5'd31;
+                    address[3] = 5'd31;
+                   end
+                   4'h8:
+                   begin
+                    address[0] = address[0] + 2;
+                    address[1] = 5'd31;
+                    address[2] = 5'd31;
+                    address[3] = 5'd31;
+                   end
+                 endcase
+               end
                else
+               begin
                  out_pipe_en = 0;
-             end
+                 address[0] = 5'b0;
+                 address[1] = address[0] + 1;
+                 address[2] = address[0] + array_dim;
+                 address[3] = address[0] + array_dim + 1;
+               end
+              end
 
              pipe_ip:
              begin
@@ -76,7 +206,7 @@ module PU_CTRL
                //next_count = current_count + 1;
                unique case (array_dim)
                  3'h3, 3'h4:
-                   if (current_count == 3'h3)
+                   if (current_count == 4'h3)
                    begin
                      next_state = finish;
                      next_count = '0;
@@ -88,7 +218,7 @@ module PU_CTRL
                    end
 
                  3'h5:
-                   if (current_count == 3'h8)
+                   if (current_count == 4'h8)
                    begin
                      next_state = finish;
                      next_count = '0;

From 7b2e3056239b1eb731f28170edaeac94b88c157f Mon Sep 17 00:00:00 2001
From: Moustafa Darwish <e.moustafa2@gmail.com>
Date: Wed, 13 Oct 2021 15:06:20 +0200
Subject: [PATCH 09/12] max_avg control output added

---
 rtl/PU_CTRL.sv | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/rtl/PU_CTRL.sv b/rtl/PU_CTRL.sv
index 7161d0f..a8fd43a 100644
--- a/rtl/PU_CTRL.sv
+++ b/rtl/PU_CTRL.sv
@@ -48,6 +48,7 @@ module PU_CTRL
   begin
     in_pipe_en  = 0;
     out_pipe_en = 0;
+    max_avg     = 1;
     next_state  = current_state;
     next_count  = current_count;
     address     = temp_add;
@@ -203,6 +204,7 @@ module PU_CTRL
              pipe_ip:
              begin
                in_pipe_en = 1;
+               max_avg    = inst[2];
                //next_count = current_count + 1;
                unique case (array_dim)
                  3'h3, 3'h4:

From 1e45fa5603f902b2d9348dea6853f1d5aea64e65 Mon Sep 17 00:00:00 2001
From: hego2022 <89414095+hego2022@users.noreply.github.com>
Date: Thu, 21 Oct 2021 16:23:40 +0200
Subject: [PATCH 10/12] Update col2img.sv

---
 rtl/col2img.sv | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/rtl/col2img.sv b/rtl/col2img.sv
index e69de29..4ca24b8 100644
--- a/rtl/col2img.sv
+++ b/rtl/col2img.sv
@@ -0,0 +1,33 @@
+module col2img#
+    (parameter  data_width = 8 
+     parameter in_vec_size =28 )(
+    input logic clk, 
+    input logic nrst , 
+    output logic [data_width-1:0] out_img [in_vec_size-1:0][in_vec_size-1:0] ,
+    input logic in_valid  , 
+    input logic [data_width:0] cols [(in_vec_size^2)-1:0] 
+    );
+  
+
+    always_comb begin
+
+        if(nrst)
+            begin
+            generate genvar i , j ;
+                for (i=0 , i < in_vec_size , i = i+1 ) ;
+                    begin
+                        for (j=0 , j < in_vec_size , j = i+1 ) ;
+                            begin
+                                out_img[i][j]= cols[i*in_vec_size+j] ;  
+                                 
+                            end
+                    end
+                    
+            endgenerate      
+
+           end     
+        else begin
+           out_img=0; 
+        end
+
+    end

From 3736fb6ea480785b468f559a4ccccb523e77880a Mon Sep 17 00:00:00 2001
From: hego2022 <89414095+hego2022@users.noreply.github.com>
Date: Thu, 21 Oct 2021 16:28:05 +0200
Subject: [PATCH 11/12] Update img2col.sv

---
 rtl/img2col.sv | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/rtl/img2col.sv b/rtl/img2col.sv
index ff2e48b..a40b2d8 100644
--- a/rtl/img2col.sv
+++ b/rtl/img2col.sv
@@ -7,7 +7,7 @@ module img2col#
     input logic stride ,
     input logic [data_width-1:0] img [img_size-1:0][img_size-1:0] ,
     input logic in_valid  , 
-    output logic [7:0] out_cols [24:0] 
+        output logic [7:0] out_cols [31:0] 
     );
   
 
@@ -26,10 +26,10 @@ module img2col#
                     end
                     
             endgenerate      
-
-           end     
+             out_cols[25:31]=0;      
+            end     
         else begin
-            // the output will bel zero 
+           out_cols=0; 
         end
 
     end

From d0907b3f9aded1a809505cbd9ba0acef6cf15b68 Mon Sep 17 00:00:00 2001
From: marwan ibrahim zaki <50636605+marwanibrahim546@users.noreply.github.com>
Date: Mon, 1 Nov 2021 02:48:56 +0200
Subject: [PATCH 12/12] .

---
 rtl/img2col.sv | 1 +
 1 file changed, 1 insertion(+)

diff --git a/rtl/img2col.sv b/rtl/img2col.sv
index a40b2d8..4cac7f9 100644
--- a/rtl/img2col.sv
+++ b/rtl/img2col.sv
@@ -10,6 +10,7 @@ module img2col#
         output logic [7:0] out_cols [31:0] 
     );
   
+    
 
     always_comb begin