diff --git a/.github/CODEOWNERS b/.github/CODEOWNERS new file mode 100644 index 00000000..50f054b8 --- /dev/null +++ b/.github/CODEOWNERS @@ -0,0 +1,10 @@ +# These owners will be the default owners for everything in +# the repo. Unless a later match takes precedence, +# they will be requested for review when someone opens a pull request. +* @ederjc @jaenrig-ifx @LinjingZhang @dineshgit411 + +# Owners for specific paths/files. +cores/ @jaenrig-ifx @LinjingZhang @dineshgit411 +libraries/ @jaenrig-ifx @LinjingZhang @dineshgit411 +variants/ @jaenrig-ifx @LinjingZhang @dineshgit411 +tools/ @jaenrig-ifx @LinjingZhang @dineshgit411 \ No newline at end of file diff --git a/.github/scripts/release.py b/.github/scripts/release.py deleted file mode 100755 index 5809e723..00000000 --- a/.github/scripts/release.py +++ /dev/null @@ -1,154 +0,0 @@ - -import argparse, copy, hashlib, json, re, requests, os, shutil - -version = '0.2.1' - -xmc_ino_root_path = os.path.relpath(os.path.join(os.path.join(os.getcwd(), os.pardir), os.pardir)) -build_dir_name = 'pkg_build' -pkg_assets_build_path = os.path.join(xmc_ino_root_path , build_dir_name) - -def strip_prefix_from_version(version): - return re.sub(r'[vV]', '', version) - -def mkdir_package_dir(version): - semver = strip_prefix_from_version(version) - pkg_name = "XMC_IFX_" + semver - pkg_build_path = os.path.join(pkg_assets_build_path, pkg_name) - os.mkdir(pkg_build_path) - - return pkg_name - -def build_package(pkg_name): - pkg_build_path = os.path.join(pkg_assets_build_path, pkg_name) - - dirs_to_copy = [ - 'cores', - 'libraries', - 'tools', - 'variants' - ] - - files_to_copy = [ - 'boards.txt', - 'keywords.txt', - 'package.json', - 'platform.txt', - 'LICENSE.md', - 'README.md' - ] - - ignore_pattern = shutil.ignore_patterns() - - for dir in dirs_to_copy: - if dir == 'libraries': - ignore_pattern = shutil.ignore_patterns('Makefile', 'Makefile.test', 'test') - shutil.copytree(os.path.join(xmc_ino_root_path, dir), os.path.join(pkg_build_path, dir), ignore=ignore_pattern) - - for file in files_to_copy: - shutil.copyfile(os.path.join(xmc_ino_root_path, file), os.path.join(pkg_build_path, file)) - -def zip_package(pkg_name): - pkg_build_path = os.path.join(pkg_assets_build_path, pkg_name) - shutil.make_archive(pkg_build_path, 'zip', pkg_assets_build_path, pkg_name) - -def get_package_size(pkg): - return os.path.getsize(pkg) - -def get_package_sha256(pkg): - with open(pkg,"rb") as f: - bytes = f.read() - hash = hashlib.sha256(bytes).hexdigest() - - return hash - -def get_latest_package_index_json(): - return requests.get('https://github.com/Infineon/XMC-for-Arduino/releases/latest/download/package_infineon_index.json').json() - -def get_local_package_index_json(): - with open(os.path.join(xmc_ino_root_path, 'package/package_infineon_index.template.json'), 'r') as f: - data = json.load(f) - return data - -def get_platform_data_struct_copy(pkg_index): - return copy.deepcopy(pkg_index['packages'][0]['platforms']) - -def set_new_platform_data_fields(platform_data_index, pkg_name, version, repository): - semver = strip_prefix_from_version(version) - platform_data = platform_data_index['packages'][0]['platforms'][0] - platform_data['version'] = str(semver) - archive_file_name = str(pkg_name) + ".zip" - platform_data['archiveFileName'] = archive_file_name - platform_data['url'] = "https://github.com/" + str(repository) + "/releases/download/" + str(version) + "/" + str(archive_file_name) - platform_data['checksum'] ="SHA-256:" + str(get_package_sha256(os.path.join(pkg_assets_build_path, archive_file_name))) - platform_data['size'] = str(get_package_size(os.path.join(pkg_assets_build_path, archive_file_name))) - -def add_platform_to_package_index(pkg_index, platform): - pkg_index['packages'][0]['platforms'].extend(platform) - -def make_package_index_file(pkg_index): - pkg_index_json_obj = json.dumps(pkg_index, indent=2) - pkg_index_w_path = os.path.join(pkg_assets_build_path, "package_infineon_index.json") - with open(pkg_index_w_path, "w") as pkg_file: - pkg_file.write(pkg_index_json_obj) - -def build_package_index_json(pkg_name, version, repository): - # get online package index json - latest_package_index = get_latest_package_index_json() - # get local package index template - local_package_index = get_local_package_index_json() - # set data field in local template for newest package - set_new_platform_data_fields(local_package_index, pkg_name, version, repository) - # get old package array - old_platform_data = get_platform_data_struct_copy(latest_package_index) - # append to local package index - add_platform_to_package_index(local_package_index, old_platform_data) - make_package_index_file(local_package_index) - -def build_release_assets(version, repository): - if os.path.exists(pkg_assets_build_path): - shutil.rmtree(pkg_assets_build_path) - os.mkdir(pkg_assets_build_path) - pkg_name = mkdir_package_dir(version) - build_package(pkg_name) - zip_package(pkg_name) - build_package_index_json(pkg_name, version, repository) - -def parser(): - - def main_parser_func(args): - parser.print_help() - - def parser_build_release_assets_func(args): - global xmc_ino_root_path - global pkg_build_path - xmc_ino_root_path = args.root_path - pkg_build_path = args.build_path - build_release_assets(args.version, args.repository) - - class ver_action(argparse.Action): - def __init__(self, option_strings, dest, **kwargs): - return super().__init__(option_strings, dest, nargs=0, default=argparse.SUPPRESS, **kwargs) - - def __call__(self, parser, namespace, values, option_string, **kwargs): - print('xmc-release version: ' + version) - parser.exit() - - # General parser - parser = argparse.ArgumentParser(description="xmc-release tool") - parser.add_argument('-v','--version', action=ver_action, help='xmc-release version') - subparser = parser.add_subparsers() - parser.set_defaults(func=main_parser_func) - - # Release parser - parser_release = subparser.add_parser('build-release', description='Build package release assets') - parser_release.add_argument('repository', type=str, help='Repository name') - parser_release.add_argument('version', type=str, help='Package release version (format: Vx.y.z)') - parser_release.add_argument('-r','--root-path', type=str, default=xmc_ino_root_path, help='Path to the XMC-for-Arduino root path') - parser_release.add_argument('-b','--build-path', type=str, default=pkg_assets_build_path, help='Path to build package') - parser_release.set_defaults(func=parser_build_release_assets_func) - - args = parser.parse_args() - args.func(args) - -if __name__ == "__main__": - parser() \ No newline at end of file diff --git a/.github/workflows/check_links.yml b/.github/workflows/check_links.yml new file mode 100644 index 00000000..e4d8a03d --- /dev/null +++ b/.github/workflows/check_links.yml @@ -0,0 +1,17 @@ +name: Check links + +on: + workflow_dispatch: + push: + branches: + - master + - main + tags: + - '*' + pull_request: + schedule: + - cron: '30 3 * * 5' # Run every Friday at 3:30 AM UTC + +jobs: + linkChecker: + uses: Infineon/makers-devops/.github/workflows/check_links.yml@main \ No newline at end of file diff --git a/.github/workflows/compile-examples.yml b/.github/workflows/compile-examples.yml new file mode 100644 index 00000000..920dd429 --- /dev/null +++ b/.github/workflows/compile-examples.yml @@ -0,0 +1,12 @@ +name: Compile examples + +on: + push: + +jobs: + compile-examples: + uses: Infineon/arduino-devops/.github/workflows/compile-examples.yml@latest + with: + core-setup-script: bash ./tools/dev-setup.sh + ci-setup-script: git submodule update --init extras/arduino-examples + secrets: inherit \ No newline at end of file diff --git a/.github/workflows/compile-platform-examples.yml b/.github/workflows/compile-platform-examples.yml deleted file mode 100644 index 64ba263a..00000000 --- a/.github/workflows/compile-platform-examples.yml +++ /dev/null @@ -1,207 +0,0 @@ - -name: Compile Examples - -# See: https://docs.github.com/en/actions/reference/events-that-trigger-workflows -on: - push: - paths: - - ".github/workflows/compile-platform-examples.ya?ml" - - "cores/**" - - "libraries/**" - - "variants/**" - - "boards.txt" - - "platform.txt" - pull_request: - paths: - - ".github/workflows/compile-platform-examples.ya?ml" - - "cores/**" - - "libraries/**" - - "variants/**" - - "boards.txt" - - "platform.txt" - workflow_dispatch: - repository_dispatch: - -jobs: - build: - name: ${{ matrix.board.fqbn }} - runs-on: ubuntu-latest - - env: - SKETCHES_REPORTS_PATH: sketches-reports - - strategy: - fail-fast: false - - matrix: - board: - - fqbn: Infineon:xmc:XMC1100_Boot_Kit - i2s: true - dieTemp: true - heapMem: true - sleep1100: true - sleep4700 : false - stackMem: true - dma: false - alarmRtc: false - can: false - - fqbn: Infineon:xmc:XMC1100_XMC2GO - i2s: true - dieTemp: true - heapMem: true - sleep1100: true - sleep4700 : false - stackMem: true - dma: false - alarmRtc: false - can: false - - fqbn: Infineon:xmc:XMC1300_Boot_Kit - i2s: false - dieTemp: true - heapMem: true - sleep1100: true - sleep4700 : false - stackMem: true - multiSerial: false - dma: false - alarmRtc: false - can: false - - fqbn: Infineon:xmc:XMC4200_Platform2GO - i2s: false - dieTemp: false - heapMem: false - sleep1100: false - sleep4700 : false - stackMem: true - multiSerial: false - dma: false - alarmRtc: true - can: true - - fqbn: Infineon:xmc:XMC4400_Platform2GO - i2s: false - dieTemp: false - heapMem: false - sleep1100: false - sleep4700 : false - stackMem: true - dma: false - alarmRtc: false - can: true - - fqbn: Infineon:xmc:XMC4700_Relax_Kit - i2s: true - dieTemp: true - heapMem: true - sleep1100: false - sleep4700 : true - stackMem: true - multiSerial: true - dma: true - alarmRtc: true - can: true - - fqbn: Infineon:xmc:XMC1400_XMC2GO - i2s: true - dieTemp: true - heapMem: true - sleep1100: true - sleep4700 : false - stackMem: false - dma: false - alarmRtc: false - can: true - - fqbn: Infineon:xmc:XMC1400_Arduino_Kit - i2s: false - dieTemp: true - heapMem: true - sleep1100: true - sleep4700 : false - stackMem: false - multiSerial: false - dma: false - alarmRtc: false - can: false - - # Make board type-specific customizations to the matrix jobs - include: - - board: - i2s: true - i2s-sketch-paths: | - - libraries/I2S - - board: - dieTemp: true - dieTemp-sketch-paths: | - - libraries/DeviceControlXMC/examples/DieTemperatureMeasurement - - board: - heapMem: true - heapMem-sketch-paths: | - - libraries/DeviceControlXMC/examples/HeapMemoryMeasurement - - board: - sleep1100: true - sleep1100-sketch-paths: | - - libraries/DeviceControlXMC/examples/SleepModeXMC1100 - - board: - sleep4700: true - sleep4700-sketch-paths: | - - libraries/DeviceControlXMC/examples/SleepModeXMC4700 - - board: - stackMem: true - stackMem-sketch-paths: | - - libraries/DeviceControlXMC/examples/StackMemoryMeasurement - - board: - dma: true - dma-sketch-paths: | - - libraries/DMA - - board: - alarmRtc: true - alarmRtc-sketch-paths: | - - libraries/RTC/examples/AlarmRTC - - board: - can: true - can-sketch-paths: | - - libraries/CAN/examples - steps: - - name: Checkout repository - uses: actions/checkout@v4 - - - name: Compile examples - uses: arduino/compile-sketches@v1.1.1 - with: - github-token: ${{ secrets.GITHUB_TOKEN }} - fqbn: ${{ matrix.board.fqbn }} - platforms: | - # Use Boards Manager to install the latest release of the platform to get the toolchain. - - name: Infineon:xmc - source-url: https://github.com/${{ github.repository }}/releases/latest/download/package_infineon_index.json - - - source-path: ./ - name: Infineon:xmc - sketch-paths: | - # Compile these sketches for all boards - - libraries/LED - - libraries/RTC/examples/SimpleRTC - - libraries/SPI - - libraries/Wire - # Board-specific sketches - ${{ matrix.i2s-sketch-paths }} - ${{ matrix.dieTemp-sketch-paths }} - ${{ matrix.heapMem-sketch-paths }} - ${{ matrix.sleep1100-sketch-paths }} - ${{ matrix.sleep4700-sketch-paths }} - ${{ matrix.stackMem-sketch-paths }} - ${{ matrix.multiSerial-sketch-paths }} - ${{ matrix.dma-sketch-paths }} - ${{ matrix.alarmRtc-sketch-paths }} - ${{ matrix.can-sketch-paths }} - enable-deltas-report: false - sketches-report-path: ${{ env.SKETCHES_REPORTS_PATH }} - - - name: Modify the environment variable - run: | - BOARD_NAME=$(echo ${{ matrix.board.fqbn }} | sed 's/:/-/g') - echo "BOARD_NAME=$BOARD_NAME" >> $GITHUB_ENV - - - name: Save sketches report as workflow artifact - uses: actions/upload-artifact@v4 - with: - if-no-files-found: error - name: ${{ env.SKETCHES_REPORTS_PATH }}-${{ env.BOARD_NAME }} - path: ${{ env.SKETCHES_REPORTS_PATH }} diff --git a/.github/workflows/hil-unity-checks.yml b/.github/workflows/hil-unity-checks.yml deleted file mode 100644 index 3e1aa01b..00000000 --- a/.github/workflows/hil-unity-checks.yml +++ /dev/null @@ -1,237 +0,0 @@ -name: Hil unity library checks - -# on which event should we start push, pull request or schedule dispatches -on: - - push - -env: - TEST_VERSION: 1.0.0 - -permissions: - contents: write - -# This template runes multiple workflows -jobs: - - - ############################################################################# - # This action sets common variables for the flow and - # identifies the libs to compile - setup: - - # we run this on self hosted runner, use labels to be more specific - # add specific names if there are some, otherwise self-hosted, X64, Linux are the default ones - runs-on: - - self-hosted - - X64 - - Linux - - steps: - # checkout the latest github action code - - name: Checkout actions - uses: actions/checkout@v4 - with: - token: ${{ secrets.UNITY_TOKEN }} - submodules: recursive - - # checkout the latest arduino-cli compiler - - name: Setup Arduino CLI - uses: arduino/setup-arduino-cli@master - - # Update the arduino code. Attention this does not setup XMC packages as this are set inside the self hosted runner - # the arduino board support packages can be updated automatically - # the XMC board support package is only linked inside the self hosted runner, which allows - # to use none official and beta versions - # arduino-cli core install "infineon:xmc" - - name: Install/Update Arduino Platform - run: | - arduino-cli core update-index - arduino-cli core install "arduino:avr" - - # Fetch variables and move them to the GITHUB_OUTPUT and fetch HIL information - - id: startup - run: | - # switch on the HIL - cd /opt/runner_support/ - REPO="$(basename "$GITHUB_REPOSITORY")" - ./py_checkusb.py --switch repo --namelist $REPO --onoff on - - # set the hil-unity-checks - hil=$(./py_checkusb.py --readyaml $GITHUB_WORKSPACE/tests/hil-unity-checklist.yaml --json) - echo "hil=${hil}" >> $GITHUB_OUTPUT - - # fetch unity libraries - readarray -t data < <(echo $hil | jq -r '.|keys[]') - export dev=$(jq --compact-output --null-input '$ARGS.positional' --args -- "${data[@]}") - echo "devices=${dev}" >> $GITHUB_OUTPUT - echo "devices=${dev}" - - # Connect the GITHUB_OUTPUT to the variables and the workflow output mechanism - outputs: - hil: ${{ steps.startup.outputs.hil }} - devices: ${{ steps.startup.outputs.devices }} - - - ############################################################################# - # This step allows HIL (Hardware in the loop), therefore - # is searches for the given board/sensor combination and tries to find the actual port - # on the self hosted runner. (see documentation for the board2port finder) - flash: - - # We need a successful build before we can run the deploy - needs: [setup] - - # we run this on self hosted runner, use labels to be more specific - # add specific names if there are some, otherwise self-hosted, X64, Linux are the default ones - runs-on: - - self-hosted - - X64 - - Linux - - # do not stop if a single job fails - continue-on-error: true - - strategy: - - # the code to flash - matrix: - # the serials of the hardware boards - device: ${{ fromJson(needs.setup.outputs.devices) }} - - # These are the steps which should run for each combination of fqbn and lib code - steps: - # checkout the latest github action code - - name: Checkout actions - uses: actions/checkout@v4 - with: - token: ${{ secrets.UNITY_TOKEN }} - submodules: recursive - - # setup environment - - name: Environment - run: | - cd $HOME - rm -rf ~/.arduino15/packages/Infineon/hardware/xmc/* - ln -s $GITHUB_WORKSPACE ~/.arduino15/packages/Infineon/hardware/xmc/$TEST_VERSION - - hil=${{ toJson(needs.setup.outputs.hil) }} - REPO="$(basename "$GITHUB_REPOSITORY")" - DEVICE="$(basename ${{ matrix.device }} )" - LIBRARY=$(echo $hil | jq ".\"${DEVICE}\"" -r --compact-output) - FQBN=`tr '.' ':' <<<"${DEVICE}"` - - echo "repo=$REPO" >> $GITHUB_ENV - echo "device=$DEVICE" >> $GITHUB_ENV - echo "version=$TEST_VERSION" >> $GITHUB_ENV - echo "library=$LIBRARY" >> $GITHUB_ENV - echo "fqbn=$FQBN" >> $GITHUB_ENV - - echo "Repo " $REPO - echo "Device " $DEVICE - echo "Library " $LIBRARY - echo "FQBN " $FQBN - echo "Version " ${TEST_VERSION} - - # Build the test code with make and flash it to the board - # runs via nested loops: - # - first loop over the libraries mentioned for a device in the yaml file - # - selects the serial ids and ports for all devices connected with this device and library - # - second loop over the examples mentioned below the selected device for a library in the yaml file - # - third loop over the tests mentioned below the selected example for a device and library in the yaml file - # - fourth loop over the make commands mentioned below the selected test for a device, example and library in the yaml file - - - name: Build - run: | - export TMPDIR=$HOME/tmp - mkdir -p $TMPDIR - rm -rf $HOME/artefact - mkdir -p $HOME/artefact - - lib=${{ toJson(env.library) }} - readarray -t LIBS < <(echo ${lib} | jq ".|keys[]" -r --compact-output) - - # loop over all libs in the unity test yaml - for LIB in "${LIBS[@]}"; do - cd /opt/runner_support/ - readarray -t SERIALS < <(echo $(./py_checkusb.py --type ${LIB} --json) | jq ".\"${LIB}\".\"${{ env.device }}\"|keys[]" -r) - - # check if we have one or more serial numbers for this lib or stop here - if [[ -z $SERIALS ]]; then - echo "No serial or library information found" - exit 0 - fi - - # loop over all serials and fetch the ports - declare -a PORTS - for SERIAL in "${SERIALS[@]}"; do - PORTS+=($(/opt/runner_support/find_usb.sh $SERIAL)) - done - - # loop over all examples for one library - readarray -t EXAMPLES < <(echo $lib | jq ".\"${LIB}\"|keys[]" -r --compact-output) - for EXAMPLE in "${EXAMPLES[@]}"; do - echo "==============================================================================================================" - echo "Run for EXAMPLE: ${EXAMPLE} under LIB: ${LIB}" - echo "==============================================================================================================" - - # loop over all tests for one example and compile7flash the devices - readarray -t TESTS < <(echo $lib | jq ".\"${LIB}\".\"${EXAMPLE}\"[]" -r --compact-output) - for ((idx=0; idx<${#TESTS[@]}; ++idx)); do - cd $GITHUB_WORKSPACE/tests/arduino-core-tests/ - echo "==============================================================================================================" - echo "Run on index $idx for TEST: ${TESTS[idx]} under EXAMPLE: ${EXAMPLE} and LIB: ${LIB} on port: ${PORTS[idx]}" - echo "==============================================================================================================" - make FQBN=${{ env.fqbn }} PORT=${PORTS[idx]} UNITY_PATH=/opt/Unity ${TESTS[idx]} - mkdir -p ~/artefact/${LIB}/${EXAMPLE}/${TESTS[idx]}/ - mv ./build/build/* ~/artefact/${LIB}/${EXAMPLE}/${TESTS[idx]}/. - echo "==============================================================================================================" - done # end of TEST loop flash - - # loop over all tests for one example and monitor the serial output - for ((idx=0; idx<${#TESTS[@]}; ++idx)); do - echo "==============================================================================================================" - echo "Monitor on index $idx for TEST: ${TESTS[idx]} under EXAMPLE: ${EXAMPLE} and LIB: ${LIB}" - timeout 1m \ - /opt/runner_support/py_console.py \ - --port ${PORTS[idx]} \ - --baud 115200 \ - --report ~/artefact/${LIB}/${EXAMPLE}/${TESTS[idx]}/${{ env.device }}/report.json - - echo "==============================================================================================================" - done # end of TEST loop monitor - - done # end of EXAMPLE loop - done # end of LIB loop - - # Upload the compiled HEX files to the GitHub server - - name: Artefact - uses: actions/upload-artifact@v4 - with: - name: ${{ env.device }} - path: ~/artefact/* - if-no-files-found: ignore - - - ############################################################################# - # Switch off the HIL after all tests are done - post: - - # we run this no matter if before fails - if: always() - # wait on first setup run before starting main function - needs: [setup, flash] - - # we run this on self hosted runner, use labels to be more specific - # add specific names if there are some, otherwise self-hosted, X64, Linux are the default ones - runs-on: - - self-hosted - - X64 - - Linux - - steps: - - name: Switch off HIL - run: | - cd /opt/runner_support/ - REPO="$(basename "$GITHUB_REPOSITORY")" - ./py_checkusb.py --switch repo --namelist $REPO --onoff off - diff --git a/.github/workflows/hil_checks.yml b/.github/workflows/hil_checks.yml new file mode 100644 index 00000000..2c7c2731 --- /dev/null +++ b/.github/workflows/hil_checks.yml @@ -0,0 +1,17 @@ +name: HIL Checks + +on: + pull_request: + paths-ignore: + - '**/*.md' + - '**/docs/**' + - 'tools/verifygitlog.py' + + +jobs: + makers-devops: + uses: Infineon/makers-devops/.github/workflows/hil_checks.yml@main + with: + project-yaml: config/project.yml + user-yaml: config/user.yml + secrets: inherit \ No newline at end of file diff --git a/.github/workflows/pre-commit.yaml b/.github/workflows/pre-commit.yaml index 9be2af1d..7c853ef6 100644 --- a/.github/workflows/pre-commit.yaml +++ b/.github/workflows/pre-commit.yaml @@ -4,9 +4,10 @@ on: push: branches: - master + - 4.0.0-pre-release pull_request: branches: - - master + - 4.0.0-pre-release jobs: pre-commit: diff --git a/.github/workflows/release.yml b/.github/workflows/release.yml index ecb094d2..5527e557 100644 --- a/.github/workflows/release.yml +++ b/.github/workflows/release.yml @@ -1,39 +1,25 @@ -name: XMC-for-Arduino Release Automation +name: Release on: - release: - types: published push: tags: - - 'v*.*.*' - - 'V*.*.*' -jobs: - release: - runs-on: ubuntu-latest - if: startsWith(github.ref, 'refs/tags/V') - steps: - - uses: actions/checkout@v3 - - uses: actions/setup-python@v4 - with: - python-version: '3.x' - - run: pip install requests - - - name: Build release changelog - id: build_changelog - uses: mikepenz/release-changelog-builder-action@v3 - env: - GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} + - '[0-9]+.[0-9]+.[0-9]+**' + workflow_dispatch: + inputs: + version: + description: 'Release version' + required: true + default: '' + type: choice + options: + - patch + - minor + - major - - name: Build release assets - run: | - cd .github/scripts - python release.py build-release ${{ github.repository }} ${{ github.ref_name }} - - - name: Upload assets - uses: softprops/action-gh-release@v1 - with: - name: XMC-for-Arduino ${{ github.ref_name }} - files: | - pkg_build/*.zip - pkg_build/package_infineon_index.json - body: ${{steps.build_changelog.outputs.changelog}} \ No newline at end of file +jobs: + arduino-devops: + uses: Infineon/arduino-devops/.github/workflows/release.yml@latest + with: + setup-script: bash ./tools/dev-setup.sh + version: ${{ inputs.version }} + secrets: inherit \ No newline at end of file diff --git a/.gitignore b/.gitignore index be93e381..08197b70 100644 --- a/.gitignore +++ b/.gitignore @@ -25,5 +25,7 @@ err.xml # Ignore docs build (Sphinx) docs/build docs/source/_build -__pycache__/ -_build/ \ No newline at end of file +_build/ + +# Arduino core api symlinked +cores/xmc/api diff --git a/.gitmodules b/.gitmodules index 743eb3c3..d5a1cf7b 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,3 +1,15 @@ [submodule "arduino-core-tests"] - path = tests/arduino-core-tests + path = extras/arduino-core-tests url = https://github.com/Infineon/arduino-core-tests.git +[submodule "cores/arduino-core-api"] + path = extras/arduino-core-api + url = https://github.com/arduino/ArduinoCore-API.git +[submodule "extras/arduino-examples"] + path = extras/arduino-examples + url = https://github.com/arduino/arduino-examples.git +[submodule "extras/arduino-devops"] + path = extras/arduino-devops + url = https://github.com/Infineon/arduino-devops.git +[submodule "extras/makers-devops"] + path = extras/makers-devops + url = https://github.com/Infineon/makers-devops.git diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml index 4c6e921a..03c365f2 100644 --- a/.pre-commit-config.yaml +++ b/.pre-commit-config.yaml @@ -4,7 +4,7 @@ repos: hooks: - id: clang-format args: ["-style=file:config/clang-format/.clang-format"] - exclude: ^cores/(avr|usblib|xmc_lib)/ + exclude: ^cores/xmc/(avr|usblib|xmc_lib)/ files: \.(c|cpp|h|hpp)$ - repo: local hooks: diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index 2985ab1d..aaaba7b9 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -7,8 +7,8 @@ Please contribute and raise issues via the [github repository](https://github.co - Start your contribution by creating a [fork](https://github.com/Infineon/XMC-for-Arduino/fork) of this repository. - It's recommended to create a separate branch for your contribution in your fork. -- Once your contribution is ready & tested, please create a [Pull Request](https://github.com/Infineon/XMC-for-Arduino/compare) to the master branch. We have some automated tests, so make sure you've browsed our [CODE CONVENTION](CODE_CONVENTION.md) and [development instructions](https://xmc-arduino.readthedocs.io/en/latest/development-instructions.html) +- Once your contribution is ready & tested, please create a [Pull Request](https://github.com/Infineon/XMC-for-Arduino/compare) to the master branch. We have some automated tests, so make sure you've browsed our [CODE CONVENTIONS](CODE_CONVENTIONS.md) and [development instructions](https://xmc-arduino.readthedocs.io/en/latest/development-instructions.html) - Once we merged your changes to the master branch, they are automatically included in the next release. ## Development -Please check [development instructions](https://xmc-arduino.readthedocs.io/en/latest/development-instructions.html) section in our documentation for more information on how to set up your development enviroment and start developing XMC4Arduino! \ No newline at end of file +Please check [development instructions](https://xmc-arduino.readthedocs.io/en/latest/development-instructions.html) section in our documentation for more information on how to set up your development enviroment and start developing XMC4Arduino! diff --git a/README.md b/README.md index 9748f32f..7cbeb6a7 100644 --- a/README.md +++ b/README.md @@ -2,9 +2,10 @@ ![Compilation Status](https://github.com/Infineon/XMC-for-Arduino/actions/workflows/compile-platform-examples.yml/badge.svg) [![Documentation Status](https://readthedocs.org/projects/xmc-arduino/badge/?version=latest)](https://xmc-arduino.readthedocs.io/en/latest/?badge=latest) -[![Hil unity library checks](https://github.com/Infineon/XMC-for-Arduino/actions/workflows/hil-unity-checks.yml/badge.svg)](https://github.com/Infineon/XMC-for-Arduino/actions/workflows/hil-unity-checks.yml) +[![On-target Tests](https://github.com/Infineon/XMC-for-Arduino/actions/workflows/hil_checks.yml/badge.svg)](https://github.com/Infineon/XMC-for-Arduino/actions/workflows/hil_checks.yml) +[![Link Checks](https://github.com/Infineon/XMC-for-Arduino/actions/workflows/check_links.yml/badge.svg)](https://github.com/Infineon/XMC-for-Arduino/actions/workflows/check_links.yml) -This project integrates Infineon's 32-bit XMC™ Industrial Arm® Cortex®-M Microcontroller into the [Arduino](https://www.arduino.cc/en/Guide/Introduction) ecosystem. +This project integrates Infineon's 32-bit XMC™ Industrial Arm® Cortex®-M Microcontroller into the [Arduino](https://www.arduino.cc/) ecosystem. The [XMC™ microcontroller family](https://www.infineon.com/cms/de/product/microcontroller/32-bit-industrial-microcontroller-based-on-arm-cortex-m/) from Infineon is a powerful and versatile platform for embedded system development. The XMC for Arduino core provides a comprehensive set of APIs, examples, and tools for developing a wide range of applications, allowing developers to leverage the ease of use and flexibility of the Arduino platform while harnessing the advanced features and performance of the XMC™ microcontrollers. @@ -12,30 +13,41 @@ The [XMC™ microcontroller family](https://www.infineon.com/cms/de/product/micr - - + + + + + + + + +
KIT_XMC14_2GO KIT_XMC11_BOOT_001 KIT_XMC1400_ARDUINO KIT_XMC13_BOOT_001
KIT_XMC14_2GOKIT_XMC47_RELAX
+ +More information about supported boards can be found [here](https://xmc-arduino.readthedocs.io/en/latest/hw-platforms.html). + +## Supported Microcontroller Boards until V3.x + + - -
KIT_XMC_PLT2GO_XMC4200 KIT_XMC_PLT2GO_XMC4400KIT_XMC47_RELAX_5V_AD_V1
-More information about supported boards can be found [here](https://xmc-arduino.readthedocs.io/en/latest/hw-platforms.html). +More information about the boards in V3.x can be found [here](https://xmc-arduino.readthedocs.io/en/latest-3.x/hw-platforms.html). ## Getting Started diff --git a/boards.txt b/boards.txt index a8139ec0..dbb8420c 100644 --- a/boards.txt +++ b/boards.txt @@ -3,345 +3,266 @@ menu.UART=Serial Output Selection menu.LIB=Additional Libraries #################################################### -XMC1100_Boot_Kit.name=XMC1100 Boot Kit -XMC1100_Boot_Kit.upload.tool=xmcflasher -XMC1100_Boot_Kit.upload.speed=115200 -XMC1100_Boot_Kit.upload.resetmethod=ck -XMC1100_Boot_Kit.upload.maximum_size=65536 -XMC1100_Boot_Kit.upload.wait_for_upload_port=true - -XMC1100_Boot_Kit.communication=usb -XMC1100_Boot_Kit.protocol=dragon_isp -XMC1100_Boot_Kit.program.protocol=dragon_isp -XMC1100_Boot_Kit.program.tool=xmcflasher -XMC1100_Boot_Kit.program.extra_params=-Pusb - -XMC1100_Boot_Kit.serial.disableDTR=true -XMC1100_Boot_Kit.serial.disableRTS=true - -XMC1100_Boot_Kit.build.mcu=cortex-m0 -XMC1100_Boot_Kit.build.f_cpu=32000000L -XMC1100_Boot_Kit.build.board=ARM_XMC -XMC1100_Boot_Kit.build.board.version=1100 -XMC1100_Boot_Kit.build.board.type=T038x0064 -XMC1100_Boot_Kit.build.board.v=0064 -XMC1100_Boot_Kit.build.core=./ -XMC1100_Boot_Kit.build.variant=XMC1100 -XMC1100_Boot_Kit.build.board_variant=XMC1100_Boot_Kit -XMC1100_Boot_Kit.build.flash_size=64K -XMC1100_Boot_Kit.build.flash_ld=linker_script.ld -XMC1100_Boot_Kit.build.extra_flags=-DARM_MATH_CM0 -DXMC1_SERIES - -XMC1100_Boot_Kit.menu.UART.debug=PC -XMC1100_Boot_Kit.menu.UART.debug.uart.selected=-DSERIAL_HOSTPC -XMC1100_Boot_Kit.menu.UART.onBoard=On Board -XMC1100_Boot_Kit.menu.UART.onBoard.uart.selected=-DSERIAL_ONBOARD - -XMC1100_Boot_Kit.menu.LIB.NONE=None -XMC1100_Boot_Kit.menu.LIB.NONE.library.selected= -XMC1100_Boot_Kit.menu.LIB.NN=ARM NN Framework -XMC1100_Boot_Kit.menu.LIB.NN.library.selected=-DARM_LIB_CMSIS_NN -XMC1100_Boot_Kit.menu.LIB.DSP=ARM DSP -XMC1100_Boot_Kit.menu.LIB.DSP.library.selected=-DARM_LIB_CMSIS_DSP -XMC1100_Boot_Kit.menu.LIB.DSPNN=ARM DSP / ARM NN Framework -XMC1100_Boot_Kit.menu.LIB.DSPNN.library.selected=-DARM_LIB_CMSIS_DSP -DARM_LIB_CMSIS_NN +kit_xmc11_boot_001.name=KIT_XMC11_BOOT_001 +kit_xmc11_boot_001.upload.tool=xmcflasher +kit_xmc11_boot_001.upload.speed=115200 +kit_xmc11_boot_001.upload.resetmethod=ck +kit_xmc11_boot_001.upload.maximum_size=65536 +kit_xmc11_boot_001.upload.wait_for_upload_port=true + +kit_xmc11_boot_001.communication=usb +kit_xmc11_boot_001.protocol=dragon_isp +kit_xmc11_boot_001.program.protocol=dragon_isp +kit_xmc11_boot_001.program.tool=xmcflasher +kit_xmc11_boot_001.program.extra_params=-Pusb + +kit_xmc11_boot_001.serial.disableDTR=true +kit_xmc11_boot_001.serial.disableRTS=true + +kit_xmc11_boot_001.build.mcu=cortex-m0 +kit_xmc11_boot_001.build.f_cpu=32000000L +kit_xmc11_boot_001.build.board=ARM_XMC +kit_xmc11_boot_001.build.board.version=1100 +kit_xmc11_boot_001.build.board.type=T038x0064 +kit_xmc11_boot_001.build.board.v=0064 +kit_xmc11_boot_001.build.core=xmc +kit_xmc11_boot_001.build.variant=XMC1100 +kit_xmc11_boot_001.build.board_variant_old=XMC1100_Boot_Kit +kit_xmc11_boot_001.build.board_variant=KIT_XMC11_BOOT_001 +kit_xmc11_boot_001.build.flash_size=64K +kit_xmc11_boot_001.build.flash_ld=linker_script.ld +kit_xmc11_boot_001.build.extra_flags=-DARM_MATH_CM0 -DXMC1_SERIES + +kit_xmc11_boot_001.menu.UART.debug=PC +kit_xmc11_boot_001.menu.UART.debug.uart.selected=-DSERIAL_HOSTPC +kit_xmc11_boot_001.menu.UART.onBoard=On Board +kit_xmc11_boot_001.menu.UART.onBoard.uart.selected=-DSERIAL_ONBOARD + +kit_xmc11_boot_001.menu.LIB.NONE=None +kit_xmc11_boot_001.menu.LIB.NONE.library.selected= +kit_xmc11_boot_001.menu.LIB.NN=ARM NN Framework +kit_xmc11_boot_001.menu.LIB.NN.library.selected=-DARM_LIB_CMSIS_NN +kit_xmc11_boot_001.menu.LIB.DSP=ARM DSP +kit_xmc11_boot_001.menu.LIB.DSP.library.selected=-DARM_LIB_CMSIS_DSP +kit_xmc11_boot_001.menu.LIB.DSPNN=ARM DSP / ARM NN Framework +kit_xmc11_boot_001.menu.LIB.DSPNN.library.selected=-DARM_LIB_CMSIS_DSP -DARM_LIB_CMSIS_NN #################################################### -XMC1100_XMC2GO.name=XMC1100 XMC2Go -XMC1100_XMC2GO.upload.tool=xmcflasher -XMC1100_XMC2GO.upload.speed=115200 -XMC1100_XMC2GO.upload.resetmethod=ck -XMC1100_XMC2GO.upload.maximum_size=65536 -XMC1100_XMC2GO.upload.wait_for_upload_port=true - -XMC1100_XMC2GO.communication=usb -XMC1100_XMC2GO.protocol=dragon_isp -XMC1100_XMC2GO.program.protocol=dragon_isp -XMC1100_XMC2GO.program.tool=xmcflasher -XMC1100_XMC2GO.program.extra_params=-Pusb - -XMC1100_XMC2GO.serial.disableDTR=true -XMC1100_XMC2GO.serial.disableRTS=true - -XMC1100_XMC2GO.build.mcu=cortex-m0 -XMC1100_XMC2GO.build.f_cpu=32000000L -XMC1100_XMC2GO.build.board=ARM_XMC -XMC1100_XMC2GO.build.board.version=1100 -XMC1100_XMC2GO.build.board.type=Q024x0064 -XMC1100_XMC2GO.build.board.v=0064 -XMC1100_XMC2GO.build.core=./ -XMC1100_XMC2GO.build.variant=XMC1100 -XMC1100_XMC2GO.build.board_variant=XMC1100_XMC2GO -XMC1100_XMC2GO.build.flash_size=64K -XMC1100_XMC2GO.build.flash_ld=linker_script.ld -XMC1100_XMC2GO.build.extra_flags=-DARM_MATH_CM0 -DXMC1_SERIES - -XMC1100_XMC2GO.menu.UART.debug=PC -XMC1100_XMC2GO.menu.UART.debug.uart.selected=-DSERIAL_HOSTPC -XMC1100_XMC2GO.menu.UART.onBoard=On Board -XMC1100_XMC2GO.menu.UART.onBoard.uart.selected=-DSERIAL_ONBOARD - -XMC1100_XMC2GO.menu.LIB.NONE=None -XMC1100_XMC2GO.menu.LIB.NONE.library.selected= -XMC1100_XMC2GO.menu.LIB.NN=ARM NN Framework -XMC1100_XMC2GO.menu.LIB.NN.library.selected=-DARM_LIB_CMSIS_NN -XMC1100_XMC2GO.menu.LIB.DSP=ARM DSP -XMC1100_XMC2GO.menu.LIB.DSP.library.selected=-DARM_LIB_CMSIS_DSP -XMC1100_XMC2GO.menu.LIB.DSPNN=ARM DSP / ARM NN Framework -XMC1100_XMC2GO.menu.LIB.DSPNN.library.selected=-DARM_LIB_CMSIS_DSP -DARM_LIB_CMSIS_NN +kit_xmc_2go_xmc1100_v1.name=KIT_XMC_2GO_XMC1100_V1 +kit_xmc_2go_xmc1100_v1.upload.tool=xmcflasher +kit_xmc_2go_xmc1100_v1.upload.speed=115200 +kit_xmc_2go_xmc1100_v1.upload.resetmethod=ck +kit_xmc_2go_xmc1100_v1.upload.maximum_size=65536 +kit_xmc_2go_xmc1100_v1.upload.wait_for_upload_port=true + +kit_xmc_2go_xmc1100_v1.communication=usb +kit_xmc_2go_xmc1100_v1.protocol=dragon_isp +kit_xmc_2go_xmc1100_v1.program.protocol=dragon_isp +kit_xmc_2go_xmc1100_v1.program.tool=xmcflasher +kit_xmc_2go_xmc1100_v1.program.extra_params=-Pusb + +kit_xmc_2go_xmc1100_v1.serial.disableDTR=true +kit_xmc_2go_xmc1100_v1.serial.disableRTS=true + +kit_xmc_2go_xmc1100_v1.build.mcu=cortex-m0 +kit_xmc_2go_xmc1100_v1.build.f_cpu=32000000L +kit_xmc_2go_xmc1100_v1.build.board=ARM_XMC +kit_xmc_2go_xmc1100_v1.build.board.version=1100 +kit_xmc_2go_xmc1100_v1.build.board.type=Q024x0064 +kit_xmc_2go_xmc1100_v1.build.board.v=0064 +kit_xmc_2go_xmc1100_v1.build.core=xmc +kit_xmc_2go_xmc1100_v1.build.variant=XMC1100 +kit_xmc_2go_xmc1100_v1.build.board_variant_old=XMC1100_XMC2GO +kit_xmc_2go_xmc1100_v1.build.board_variant=KIT_XMC_2GO_XMC1100_V1 +kit_xmc_2go_xmc1100_v1.build.flash_size=64K +kit_xmc_2go_xmc1100_v1.build.flash_ld=linker_script.ld +kit_xmc_2go_xmc1100_v1.build.extra_flags=-DARM_MATH_CM0 -DXMC1_SERIES + +kit_xmc_2go_xmc1100_v1.menu.UART.debug=PC +kit_xmc_2go_xmc1100_v1.menu.UART.debug.uart.selected=-DSERIAL_HOSTPC +kit_xmc_2go_xmc1100_v1.menu.UART.onBoard=On Board +kit_xmc_2go_xmc1100_v1.menu.UART.onBoard.uart.selected=-DSERIAL_ONBOARD + +kit_xmc_2go_xmc1100_v1.menu.LIB.NONE=None +kit_xmc_2go_xmc1100_v1.menu.LIB.NONE.library.selected= +kit_xmc_2go_xmc1100_v1.menu.LIB.NN=ARM NN Framework +kit_xmc_2go_xmc1100_v1.menu.LIB.NN.library.selected=-DARM_LIB_CMSIS_NN +kit_xmc_2go_xmc1100_v1.menu.LIB.DSP=ARM DSP +kit_xmc_2go_xmc1100_v1.menu.LIB.DSP.library.selected=-DARM_LIB_CMSIS_DSP +kit_xmc_2go_xmc1100_v1.menu.LIB.DSPNN=ARM DSP / ARM NN Framework +kit_xmc_2go_xmc1100_v1.menu.LIB.DSPNN.library.selected=-DARM_LIB_CMSIS_DSP -DARM_LIB_CMSIS_NN #################################################### -XMC1300_Boot_Kit.name=XMC1300 Boot Kit -XMC1300_Boot_Kit.upload.tool=xmcflasher -XMC1300_Boot_Kit.upload.speed=115200 -XMC1300_Boot_Kit.upload.resetmethod=ck -XMC1300_Boot_Kit.upload.maximum_size=204800 -XMC1300_Boot_Kit.upload.wait_for_upload_port=true - -XMC1300_Boot_Kit.communication=usb -XMC1300_Boot_Kit.protocol=dragon_isp -XMC1300_Boot_Kit.program.protocol=dragon_isp -XMC1300_Boot_Kit.program.tool=xmcflasher -XMC1300_Boot_Kit.program.extra_params=-Pusb - -XMC1300_Boot_Kit.serial.disableDTR=true -XMC1300_Boot_Kit.serial.disableRTS=true - -XMC1300_Boot_Kit.build.mcu=cortex-m0 -XMC1300_Boot_Kit.build.f_cpu=32000000L -XMC1300_Boot_Kit.build.board=ARM_XMC -XMC1300_Boot_Kit.build.board.version=1302 -XMC1300_Boot_Kit.build.board.type=T038x0200 -XMC1300_Boot_Kit.build.board.v=0200 -XMC1300_Boot_Kit.build.core=./ -XMC1300_Boot_Kit.build.variant=XMC1300 -XMC1300_Boot_Kit.build.board_variant=XMC1300_Boot_Kit -XMC1300_Boot_Kit.build.flash_size=200K -XMC1300_Boot_Kit.build.flash_ld=linker_script_200k.ld -XMC1300_Boot_Kit.build.extra_flags=-DARM_MATH_CM0 -DXMC1_SERIES - -XMC1300_Boot_Kit.menu.UART.debug=PC -XMC1300_Boot_Kit.menu.UART.debug.uart.selected=-DSERIAL_HOSTPC -XMC1300_Boot_Kit.menu.UART.onBoard=On Board -XMC1300_Boot_Kit.menu.UART.onBoard.uart.selected=-DSERIAL_ONBOARD - -XMC1300_Boot_Kit.menu.LIB.NONE=None -XMC1300_Boot_Kit.menu.LIB.NONE.library.selected= -XMC1300_Boot_Kit.menu.LIB.NN=ARM NN Framework -XMC1300_Boot_Kit.menu.LIB.NN.library.selected=-DARM_LIB_CMSIS_NN -XMC1300_Boot_Kit.menu.LIB.DSP=ARM DSP -XMC1300_Boot_Kit.menu.LIB.DSP.library.selected=-DARM_LIB_CMSIS_DSP -XMC1300_Boot_Kit.menu.LIB.DSPNN=ARM DSP / ARM NN Framework -XMC1300_Boot_Kit.menu.LIB.DSPNN.library.selected=-DARM_LIB_CMSIS_DSP -DARM_LIB_CMSIS_NN +kit_xmc13_boot_001.name=KIT_XMC13_BOOT_001 +kit_xmc13_boot_001.upload.tool=xmcflasher +kit_xmc13_boot_001.upload.speed=115200 +kit_xmc13_boot_001.upload.resetmethod=ck +kit_xmc13_boot_001.upload.maximum_size=204800 +kit_xmc13_boot_001.upload.wait_for_upload_port=true + +kit_xmc13_boot_001.communication=usb +kit_xmc13_boot_001.protocol=dragon_isp +kit_xmc13_boot_001.program.protocol=dragon_isp +kit_xmc13_boot_001.program.tool=xmcflasher +kit_xmc13_boot_001.program.extra_params=-Pusb + +kit_xmc13_boot_001.serial.disableDTR=true +kit_xmc13_boot_001.serial.disableRTS=true + +kit_xmc13_boot_001.build.mcu=cortex-m0 +kit_xmc13_boot_001.build.f_cpu=32000000L +kit_xmc13_boot_001.build.board=ARM_XMC +kit_xmc13_boot_001.build.board.version=1302 +kit_xmc13_boot_001.build.board.type=T038x0200 +kit_xmc13_boot_001.build.board.v=0200 +kit_xmc13_boot_001.build.core=xmc +kit_xmc13_boot_001.build.variant=XMC1300 +kit_xmc13_boot_001.build.board_variant_old=XMC1300_Boot_Kit +kit_xmc13_boot_001.build.board_variant=KIT_XMC13_BOOT_001 +kit_xmc13_boot_001.build.flash_size=200K +kit_xmc13_boot_001.build.flash_ld=linker_script_200k.ld +kit_xmc13_boot_001.build.extra_flags=-DARM_MATH_CM0 -DXMC1_SERIES + +kit_xmc13_boot_001.menu.UART.debug=PC +kit_xmc13_boot_001.menu.UART.debug.uart.selected=-DSERIAL_HOSTPC +kit_xmc13_boot_001.menu.UART.onBoard=On Board +kit_xmc13_boot_001.menu.UART.onBoard.uart.selected=-DSERIAL_ONBOARD + +kit_xmc13_boot_001.menu.LIB.NONE=None +kit_xmc13_boot_001.menu.LIB.NONE.library.selected= +kit_xmc13_boot_001.menu.LIB.NN=ARM NN Framework +kit_xmc13_boot_001.menu.LIB.NN.library.selected=-DARM_LIB_CMSIS_NN +kit_xmc13_boot_001.menu.LIB.DSP=ARM DSP +kit_xmc13_boot_001.menu.LIB.DSP.library.selected=-DARM_LIB_CMSIS_DSP +kit_xmc13_boot_001.menu.LIB.DSPNN=ARM DSP / ARM NN Framework +kit_xmc13_boot_001.menu.LIB.DSPNN.library.selected=-DARM_LIB_CMSIS_DSP -DARM_LIB_CMSIS_NN #################################################### -XMC1400_XMC2GO.name=XMC1400 XMC2GO -XMC1400_XMC2GO.upload.tool=xmcflasher -XMC1400_XMC2GO.upload.speed=115200 -XMC1400_XMC2GO.upload.resetmethod=ck -XMC1400_XMC2GO.upload.maximum_size=65536 -XMC1400_XMC2GO.upload.wait_for_upload_port=true - -XMC1400_XMC2GO.communication=usb -XMC1400_XMC2GO.protocol=dragon_isp -XMC1400_XMC2GO.program.protocol=dragon_isp -XMC1400_XMC2GO.program.tool=xmcflasher -XMC1400_XMC2GO.program.extra_params=-Pusb - -XMC1400_XMC2GO.serial.disableDTR=true -XMC1400_XMC2GO.serial.disableRTS=true - -XMC1400_XMC2GO.build.mcu=cortex-m0 -XMC1400_XMC2GO.build.f_cpu=48000000L -XMC1400_XMC2GO.build.board=ARM_XMC -XMC1400_XMC2GO.build.board.version=1404 -XMC1400_XMC2GO.build.board.type=Q040x0200 -XMC1400_XMC2GO.build.board.v=0200 -XMC1400_XMC2GO.build.core=./ -XMC1400_XMC2GO.build.variant=XMC1400 -XMC1400_XMC2GO.build.board_variant=XMC1400_XMC2GO -XMC1400_XMC2GO.build.flash_size=200K -XMC1400_XMC2GO.build.flash_ld=linker_script_200k.ld -XMC1400_XMC2GO.build.extra_flags=-DARM_MATH_CM0 -DXMC1_SERIES - -XMC1400_XMC2GO.menu.UART.debug=PC -XMC1400_XMC2GO.menu.UART.debug.uart.selected=-DSERIAL_HOSTPC -XMC1400_XMC2GO.menu.UART.onBoard=On Board -XMC1400_XMC2GO.menu.UART.onBoard.uart.selected=-DSERIAL_ONBOARD - -XMC1400_XMC2GO.menu.LIB.NONE=None -XMC1400_XMC2GO.menu.LIB.NONE.library.selected= -XMC1400_XMC2GO.menu.LIB.NN=ARM NN Framework -XMC1400_XMC2GO.menu.LIB.NN.library.selected=-DARM_LIB_CMSIS_NN -XMC1400_XMC2GO.menu.LIB.DSP=ARM DSP -XMC1400_XMC2GO.menu.LIB.DSP.library.selected=-DARM_LIB_CMSIS_DSP -XMC1400_XMC2GO.menu.LIB.DSPNN=ARM DSP / ARM NN Framework -XMC1400_XMC2GO.menu.LIB.DSPNN.library.selected=-DARM_LIB_CMSIS_DSP -DARM_LIB_CMSIS_NN +kit_xmc14_2go.name=KIT_XMC14_2GO +kit_xmc14_2go.upload.tool=xmcflasher +kit_xmc14_2go.upload.speed=115200 +kit_xmc14_2go.upload.resetmethod=ck +kit_xmc14_2go.upload.maximum_size=65536 +kit_xmc14_2go.upload.wait_for_upload_port=true + +kit_xmc14_2go.communication=usb +kit_xmc14_2go.protocol=dragon_isp +kit_xmc14_2go.program.protocol=dragon_isp +kit_xmc14_2go.program.tool=xmcflasher +kit_xmc14_2go.program.extra_params=-Pusb + +kit_xmc14_2go.serial.disableDTR=true +kit_xmc14_2go.serial.disableRTS=true + +kit_xmc14_2go.build.mcu=cortex-m0 +kit_xmc14_2go.build.f_cpu=48000000L +kit_xmc14_2go.build.board=ARM_XMC +kit_xmc14_2go.build.board.version=1404 +kit_xmc14_2go.build.board.type=Q040x0200 +kit_xmc14_2go.build.board.v=0200 +kit_xmc14_2go.build.core=xmc +kit_xmc14_2go.build.variant=XMC1400 +kit_xmc14_2go.build.board_variant_old=XMC1400_XMC2GO +kit_xmc14_2go.build.board_variant=KIT_XMC14_2GO +kit_xmc14_2go.build.flash_size=200K +kit_xmc14_2go.build.flash_ld=linker_script_200k.ld +kit_xmc14_2go.build.extra_flags=-DARM_MATH_CM0 -DXMC1_SERIES + +kit_xmc14_2go.menu.UART.debug=PC +kit_xmc14_2go.menu.UART.debug.uart.selected=-DSERIAL_HOSTPC +kit_xmc14_2go.menu.UART.onBoard=On Board +kit_xmc14_2go.menu.UART.onBoard.uart.selected=-DSERIAL_ONBOARD + +kit_xmc14_2go.menu.LIB.NONE=None +kit_xmc14_2go.menu.LIB.NONE.library.selected= +kit_xmc14_2go.menu.LIB.NN=ARM NN Framework +kit_xmc14_2go.menu.LIB.NN.library.selected=-DARM_LIB_CMSIS_NN +kit_xmc14_2go.menu.LIB.DSP=ARM DSP +kit_xmc14_2go.menu.LIB.DSP.library.selected=-DARM_LIB_CMSIS_DSP +kit_xmc14_2go.menu.LIB.DSPNN=ARM DSP / ARM NN Framework +kit_xmc14_2go.menu.LIB.DSPNN.library.selected=-DARM_LIB_CMSIS_DSP -DARM_LIB_CMSIS_NN #################################################### -XMC1400_Arduino_Kit.name=XMC1400 Kit for Arduino -XMC1400_Arduino_Kit.upload.tool=xmcflasher -XMC1400_Arduino_Kit.upload.speed=115200 -XMC1400_Arduino_Kit.upload.resetmethod=ck -XMC1400_Arduino_Kit.upload.maximum_size=204800 -XMC1400_Arduino_Kit.upload.wait_for_upload_port=true - -XMC1400_Arduino_Kit.communication=usb -XMC1400_Arduino_Kit.protocol=dragon_isp -XMC1400_Arduino_Kit.program.protocol=dragon_isp -XMC1400_Arduino_Kit.program.tool=xmcflasher -XMC1400_Arduino_Kit.program.extra_params=-Pusb - -XMC1400_Arduino_Kit.serial.disableDTR=true -XMC1400_Arduino_Kit.serial.disableRTS=true - -XMC1400_Arduino_Kit.build.mcu=cortex-m0 -XMC1400_Arduino_Kit.build.f_cpu=48000000L -XMC1400_Arduino_Kit.build.board=ARM_XMC -XMC1400_Arduino_Kit.build.board.version=1402 -XMC1400_Arduino_Kit.build.board.type=T038x0200 -XMC1400_Arduino_Kit.build.board.v=0200 -XMC1400_Arduino_Kit.build.core=./ -XMC1400_Arduino_Kit.build.variant=XMC1400 -XMC1400_Arduino_Kit.build.board_variant=XMC1400_Arduino_Kit -XMC1400_Arduino_Kit.build.flash_size=200K -XMC1400_Arduino_Kit.build.flash_ld=linker_script_200k.ld -XMC1400_Arduino_Kit.build.extra_flags=-DARM_MATH_CM0 -DXMC1_SERIES - -XMC1400_Arduino_Kit.menu.UART.debug=PC -XMC1400_Arduino_Kit.menu.UART.debug.uart.selected=-DSERIAL_HOSTPC -XMC1400_Arduino_Kit.menu.UART.onBoard=On Board -XMC1400_Arduino_Kit.menu.UART.onBoard.uart.selected=-DSERIAL_ONBOARD - -XMC1400_Arduino_Kit.menu.LIB.NONE=None -XMC1400_Arduino_Kit.menu.LIB.NONE.library.selected= -XMC1400_Arduino_Kit.menu.LIB.NN=ARM NN Framework -XMC1400_Arduino_Kit.menu.LIB.NN.library.selected=-DARM_LIB_CMSIS_NN -XMC1400_Arduino_Kit.menu.LIB.DSP=ARM DSP -XMC1400_Arduino_Kit.menu.LIB.DSP.library.selected=-DARM_LIB_CMSIS_DSP -XMC1400_Arduino_Kit.menu.LIB.DSPNN=ARM DSP / ARM NN Framework -XMC1400_Arduino_Kit.menu.LIB.DSPNN.library.selected=-DARM_LIB_CMSIS_DSP -DARM_LIB_CMSIS_NN +kit_xmc1400_arduino.name=KIT_XMC1400_ARDUINO +kit_xmc1400_arduino.upload.tool=xmcflasher +kit_xmc1400_arduino.upload.speed=115200 +kit_xmc1400_arduino.upload.resetmethod=ck +kit_xmc1400_arduino.upload.maximum_size=204800 +kit_xmc1400_arduino.upload.wait_for_upload_port=true + +kit_xmc1400_arduino.communication=usb +kit_xmc1400_arduino.protocol=dragon_isp +kit_xmc1400_arduino.program.protocol=dragon_isp +kit_xmc1400_arduino.program.tool=xmcflasher +kit_xmc1400_arduino.program.extra_params=-Pusb + +kit_xmc1400_arduino.serial.disableDTR=true +kit_xmc1400_arduino.serial.disableRTS=true + +kit_xmc1400_arduino.build.mcu=cortex-m0 +kit_xmc1400_arduino.build.f_cpu=48000000L +kit_xmc1400_arduino.build.board=ARM_XMC +kit_xmc1400_arduino.build.board.version=1402 +kit_xmc1400_arduino.build.board.type=T038x0200 +kit_xmc1400_arduino.build.board.v=0200 +kit_xmc1400_arduino.build.core=xmc +kit_xmc1400_arduino.build.variant=XMC1400 +kit_xmc1400_arduino.build.board_variant_old=XMC1400_Arduino_Kit +kit_xmc1400_arduino.build.board_variant=KIT_XMC1400_ARDUINO +kit_xmc1400_arduino.build.flash_size=200K +kit_xmc1400_arduino.build.flash_ld=linker_script_200k.ld +kit_xmc1400_arduino.build.extra_flags=-DARM_MATH_CM0 -DXMC1_SERIES + +kit_xmc1400_arduino.menu.UART.debug=PC +kit_xmc1400_arduino.menu.UART.debug.uart.selected=-DSERIAL_HOSTPC +kit_xmc1400_arduino.menu.UART.onBoard=On Board +kit_xmc1400_arduino.menu.UART.onBoard.uart.selected=-DSERIAL_ONBOARD + +kit_xmc1400_arduino.menu.LIB.NONE=None +kit_xmc1400_arduino.menu.LIB.NONE.library.selected= +kit_xmc1400_arduino.menu.LIB.NN=ARM NN Framework +kit_xmc1400_arduino.menu.LIB.NN.library.selected=-DARM_LIB_CMSIS_NN +kit_xmc1400_arduino.menu.LIB.DSP=ARM DSP +kit_xmc1400_arduino.menu.LIB.DSP.library.selected=-DARM_LIB_CMSIS_DSP +kit_xmc1400_arduino.menu.LIB.DSPNN=ARM DSP / ARM NN Framework +kit_xmc1400_arduino.menu.LIB.DSPNN.library.selected=-DARM_LIB_CMSIS_DSP -DARM_LIB_CMSIS_NN #################################################### -XMC4200_Platform2GO.name=XMC4200 Platform 2GO -XMC4200_Platform2GO.upload.tool=xmcflasher -XMC4200_Platform2GO.upload.speed=115200 -XMC4200_Platform2GO.upload.resetmethod=ck -XMC4200_Platform2GO.upload.maximum_size=262144 -XMC4200_Platform2GO.upload.wait_for_upload_port=true - -XMC4200_Platform2GO.communication=usb -XMC4200_Platform2GO.protocol=dragon_isp -XMC4200_Platform2GO.program.protocol=dragon_isp -XMC4200_Platform2GO.program.tool=xmcflasher -XMC4200_Platform2GO.program.extra_params=-Pusb - -XMC4200_Platform2GO.serial.disableDTR=true -XMC4200_Platform2GO.serial.disableRTS=true - -XMC4200_Platform2GO.build.mcu=cortex-m4 -XMC4200_Platform2GO.build.f_cpu=80000000L -XMC4200_Platform2GO.build.board=ARM_XMC -XMC4200_Platform2GO.build.board.version=4200 -XMC4200_Platform2GO.build.board.type=F64x256 -XMC4200_Platform2GO.build.board.v=256 -XMC4200_Platform2GO.build.core=./ -XMC4200_Platform2GO.build.variant=XMC4200 -XMC4200_Platform2GO.build.board_variant=XMC4200_Platform2GO -XMC4200_Platform2GO.build.flash_size=256K -XMC4200_Platform2GO.build.flash_ld=linker_script.ld -XMC4200_Platform2GO.build.extra_flags=-DARM_MATH_CM4 -DARM_MATH_DSP -DINTERRUPT_USE_ERU -#-DUSB0 - -XMC4200_Platform2GO.menu.LIB.NONE=None -XMC4200_Platform2GO.menu.LIB.NONE.library.selected= -XMC4200_Platform2GO.menu.LIB.DSPNN=ARM DSP / ARM NN Framework -XMC4200_Platform2GO.menu.LIB.DSPNN.library.selected=-DARM_LIB_CMSIS_DSP -DARM_LIB_CMSIS_NN -XMC4200_Platform2GO.menu.LIB.NN=ARM NN Framework -XMC4200_Platform2GO.menu.LIB.NN.library.selected=-DARM_LIB_CMSIS_NN -XMC4200_Platform2GO.menu.LIB.DSP=ARM DSP -XMC4200_Platform2GO.menu.LIB.DSP.library.selected=-DARM_LIB_CMSIS_DSP - -#################################################### -XMC4400_Platform2GO.name=XMC4400 Platform 2GO -XMC4400_Platform2GO.upload.tool=xmcflasher -XMC4400_Platform2GO.upload.speed=115200 -XMC4400_Platform2GO.upload.resetmethod=ck -XMC4400_Platform2GO.upload.maximum_size=512000 -XMC4400_Platform2GO.upload.wait_for_upload_port=true - -XMC4400_Platform2GO.communication=usb -XMC4400_Platform2GO.protocol=dragon_isp -XMC4400_Platform2GO.program.protocol=dragon_isp -XMC4400_Platform2GO.program.tool=xmcflasher -XMC4400_Platform2GO.program.extra_params=-Pusb - -XMC4400_Platform2GO.serial.disableDTR=true -XMC4400_Platform2GO.serial.disableRTS=true - -XMC4400_Platform2GO.build.mcu=cortex-m4 -XMC4400_Platform2GO.build.f_cpu=144000000L -XMC4400_Platform2GO.build.board=ARM_XMC -XMC4400_Platform2GO.build.board.version=4400 -XMC4400_Platform2GO.build.board.type=F100x512 -XMC4400_Platform2GO.build.board.v=512 -XMC4400_Platform2GO.build.core=./ -XMC4400_Platform2GO.build.variant=XMC4400 -XMC4400_Platform2GO.build.board_variant=XMC4400_Platform2GO -XMC4400_Platform2GO.build.flash_size=500K -XMC4400_Platform2GO.build.flash_ld=linker_script.ld -XMC4400_Platform2GO.build.extra_flags=-DARM_MATH_CM4 -DARM_MATH_DSP -#-DUSB0 - -XMC4400_Platform2GO.menu.UART.debug=PC -XMC4400_Platform2GO.menu.UART.debug.uart.selected=-DSERIAL_HOSTPC -XMC4400_Platform2GO.menu.UART.onBoard=On Board -XMC4400_Platform2GO.menu.UART.onBoard.uart.selected=-DSERIAL_ONBOARD - -XMC4400_Platform2GO.menu.LIB.NONE=None -XMC4400_Platform2GO.menu.LIB.NONE.library.selected= -XMC4400_Platform2GO.menu.LIB.DSPNN=ARM DSP / ARM NN Framework -XMC4400_Platform2GO.menu.LIB.DSPNN.library.selected=-DARM_LIB_CMSIS_DSP -DARM_LIB_CMSIS_NN -XMC4400_Platform2GO.menu.LIB.NN=ARM NN Framework -XMC4400_Platform2GO.menu.LIB.NN.library.selected=-DARM_LIB_CMSIS_NN -XMC4400_Platform2GO.menu.LIB.DSP=ARM DSP -XMC4400_Platform2GO.menu.LIB.DSP.library.selected=-DARM_LIB_CMSIS_DSP - -#################################################### -XMC4700_Relax_Kit.name=XMC4700 Relax Kit -XMC4700_Relax_Kit.upload.tool=xmcflasher -XMC4700_Relax_Kit.upload.speed=115200 -XMC4700_Relax_Kit.upload.resetmethod=ck -XMC4700_Relax_Kit.upload.maximum_size=2048000 -XMC4700_Relax_Kit.upload.wait_for_upload_port=true - -XMC4700_Relax_Kit.communication=usb -XMC4700_Relax_Kit.protocol=dragon_isp -XMC4700_Relax_Kit.program.protocol=dragon_isp -XMC4700_Relax_Kit.program.tool=xmcflasher -XMC4700_Relax_Kit.program.extra_params=-Pusb - -XMC4700_Relax_Kit.serial.disableDTR=true -XMC4700_Relax_Kit.serial.disableRTS=true - -XMC4700_Relax_Kit.build.mcu=cortex-m4 -XMC4700_Relax_Kit.build.f_cpu=144000000L -XMC4700_Relax_Kit.build.board=ARM_XMC -XMC4700_Relax_Kit.build.board.version=4700 -XMC4700_Relax_Kit.build.board.type=F144x2048 -XMC4700_Relax_Kit.build.board.v=2048 -XMC4700_Relax_Kit.build.core=./ -XMC4700_Relax_Kit.build.variant=XMC4700 -XMC4700_Relax_Kit.build.board_variant=XMC4700_Relax_Kit -XMC4700_Relax_Kit.build.flash_size=2000K -XMC4700_Relax_Kit.build.flash_ld=linker_script.ld -XMC4700_Relax_Kit.build.extra_flags=-DARM_MATH_CM4 -DXMC4_SERIES - -XMC4700_Relax_Kit.menu.LIB.DSPNN=ARM DSP / ARM NN Framework -XMC4700_Relax_Kit.menu.LIB.DSPNN.library.selected=-DARM_LIB_CMSIS_DSP -DARM_LIB_CMSIS_NN -XMC4700_Relax_Kit.menu.LIB.NONE=None -XMC4700_Relax_Kit.menu.LIB.NONE.library.selected= -XMC4700_Relax_Kit.menu.LIB.NN=ARM NN Framework -XMC4700_Relax_Kit.menu.LIB.NN.library.selected=-DARM_LIB_CMSIS_NN -XMC4700_Relax_Kit.menu.LIB.DSP=ARM DSP -XMC4700_Relax_Kit.menu.LIB.DSP.library.selected=-DARM_LIB_CMSIS_DSP \ No newline at end of file +kit_xmc47_relax.name=KIT_XMC47_RELAX +kit_xmc47_relax.upload.tool=xmcflasher +kit_xmc47_relax.upload.speed=115200 +kit_xmc47_relax.upload.resetmethod=ck +kit_xmc47_relax.upload.maximum_size=2048000 +kit_xmc47_relax.upload.wait_for_upload_port=true + +kit_xmc47_relax.communication=usb +kit_xmc47_relax.protocol=dragon_isp +kit_xmc47_relax.program.protocol=dragon_isp +kit_xmc47_relax.program.tool=xmcflasher +kit_xmc47_relax.program.extra_params=-Pusb + +kit_xmc47_relax.serial.disableDTR=true +kit_xmc47_relax.serial.disableRTS=true + +kit_xmc47_relax.build.mcu=cortex-m4 +kit_xmc47_relax.build.f_cpu=144000000L +kit_xmc47_relax.build.board=ARM_XMC +kit_xmc47_relax.build.board.version=4700 +kit_xmc47_relax.build.board.type=F144x2048 +kit_xmc47_relax.build.board.v=2048 +kit_xmc47_relax.build.core=xmc +kit_xmc47_relax.build.variant=XMC4700 +kit_xmc47_relax.build.board_variant_old=XMC4700_Relax_Kit +kit_xmc47_relax.build.board_variant=KIT_XMC47_RELAX +kit_xmc47_relax.build.flash_size=2000K +kit_xmc47_relax.build.flash_ld=linker_script.ld +kit_xmc47_relax.build.extra_flags=-DARM_MATH_CM4 -DXMC4_SERIES + +kit_xmc47_relax.menu.LIB.DSPNN=ARM DSP / ARM NN Framework +kit_xmc47_relax.menu.LIB.DSPNN.library.selected=-DARM_LIB_CMSIS_DSP -DARM_LIB_CMSIS_NN +kit_xmc47_relax.menu.LIB.NONE=None +kit_xmc47_relax.menu.LIB.NONE.library.selected= +kit_xmc47_relax.menu.LIB.NN=ARM NN Framework +kit_xmc47_relax.menu.LIB.NN.library.selected=-DARM_LIB_CMSIS_NN +kit_xmc47_relax.menu.LIB.DSP=ARM DSP +kit_xmc47_relax.menu.LIB.DSP.library.selected=-DARM_LIB_CMSIS_DSP \ No newline at end of file diff --git a/ci-matrix-config.yml b/ci-matrix-config.yml new file mode 100644 index 00000000..3e31969c --- /dev/null +++ b/ci-matrix-config.yml @@ -0,0 +1,100 @@ +# This is the matrix copied from 3.x +# Each components needs to be gradually enabled as +# the core and libraries support them + +sketch: + - extras/arduino-examples/examples/01.Basics/BareMinimum/BareMinimum.ino + - extras/arduino-examples/examples/01.Basics/Blink/Blink.ino + - extras/arduino-examples/examples/01.Basics/DigitalReadSerial/DigitalReadSerial.ino + - extras/arduino-examples/examples/01.Basics/AnalogReadSerial/AnalogReadSerial.ino + - extras/arduino-examples/examples/01.Basics/Fade/Fade.ino + - extras/arduino-examples/examples/02.Digital/BlinkWithoutDelay/BlinkWithoutDelay.ino + - extras/arduino-examples/examples/02.Digital/Button/Button.ino + - extras/arduino-examples/examples/02.Digital/Debounce/Debounce.ino + - extras/arduino-examples/examples/02.Digital/DigitalInputPullup/DigitalInputPullup.ino + - extras/arduino-examples/examples/02.Digital/StateChangeDetection/StateChangeDetection.ino + - extras/arduino-examples/examples/02.Digital/toneKeyboard/toneKeyboard.ino + - extras/arduino-examples/examples/02.Digital/toneMelody/toneMelody.ino + - extras/arduino-examples/examples/02.Digital/toneMultiple/toneMultiple.ino + - extras/arduino-examples/examples/02.Digital/tonePitchFollower/tonePitchFollower.ino + - extras/arduino-examples/examples/03.Analog/AnalogInOutSerial/AnalogInOutSerial.ino + - extras/arduino-examples/examples/03.Analog/AnalogInput/AnalogInput.ino + - extras/arduino-examples/examples/03.Analog/Calibration/Calibration.ino + - extras/arduino-examples/examples/03.Analog/Fading/Fading.ino + - extras/arduino-examples/examples/03.Analog/Smoothing/Smoothing.ino + - extras/arduino-examples/examples/04.Communication/ASCIITable/ASCIITable.ino + - extras/arduino-examples/examples/04.Communication/MultiSerial/MultiSerial.ino + - extras/arduino-examples/examples/04.Communication/PhysicalPixel/PhysicalPixel.ino + - extras/arduino-examples/examples/04.Communication/SerialEvent/SerialEvent.ino + - extras/arduino-examples/examples/05.Control/ForLoopIteration/ForLoopIteration.ino + +fqbn: + - infineon:xmc:kit_xmc11_boot_001 + - infineon:xmc:kit_xmc13_boot_001 + - infineon:xmc:kit_xmc1400_arduino + - infineon:xmc:kit_xmc14_2go + - infineon:xmc:kit_xmc47_relax + - infineon:xmc:kit_xmc_2go_xmc1100_v1 + +sketch: + - libraries/LED + - libraries/RTC/examples/SimpleRTC + - libraries/SPI + - libraries/Wire + - libraries/DeviceControlXMC/examples/DieTemperatureMeasurement/DieTemperatureMeasurement.ino + - libraries/DeviceControlXMC/examples/HeapMemoryMeasurement/HeapMemoryMeasurement.ino + - libraries/DeviceControlXMC/examples/StackMemoryMeasurement/StackMemoryMeasurement.ino + +include: + - fqbn: infineon:xmc:kit_xmc11_boot_001 + sketch: + - libraries/I2S + - libraries/DeviceControlXMC/examples/SleepModeXMC1100/SleepModeXMC1100.ino + - fqbn: infineon:xmc:kit_xmc_2go_xmc1100_v1 + sketch: + - libraries/I2S + - libraries/DeviceControlXMC/examples/SleepModeXMC1100/SleepModeXMC1100.ino + - fqbn: infineon:xmc:kit_xmc13_boot_001 + sketch: + - libraries/DeviceControlXMC/examples/SleepModeXMC1100/SleepModeXMC1100.ino + - fqbn: infineon:xmc:kit_xmc14_2go + sketch: + - libraries/I2S + - libraries/DeviceControlXMC/examples/SleepModeXMC1100/SleepModeXMC1100.ino + - libraries/CAN + - fqbn: infineon:xmc:kit_xmc1400_arduino + sketch: + - libraries/DeviceControlXMC/examples/SleepModeXMC1100/SleepModeXMC1100.ino + - fqbn: infineon:xmc:kit_xmc47_relax + sketch: + - libraries/I2S + - libraries/DeviceControlXMC/examples/SleepModeXMC4700/SleepModeXMC4700.ino + - libraries/DMA + - libraries/RTC/examples/AlarmRTC/AlarmRTC.ino + - libraries/CAN + +exclude: +- fqbn: infineon:xmc:kit_xmc11_boot_001 + sketch: + - extras/arduino-examples/examples/04.Communication/MultiSerial/MultiSerial.ino +- fqbn: infineon:xmc:kit_xmc_2go_xmc1100_v1 + sketch: + - extras/arduino-examples/examples/04.Communication/MultiSerial/MultiSerial.ino +- fqbn: infineon:xmc:kit_xmc13_boot_001 + sketch: + - extras/arduino-examples/examples/04.Communication/MultiSerial/MultiSerial.ino +- fqbn: infineon:xmc:kit_xmc14_2go + sketch: + - libraries/DeviceControlXMC/examples/StackMemoryMeasurement/StackMemoryMeasurement.ino + - extras/arduino-examples/examples/04.Communication/MultiSerial/MultiSerial.ino + - extras/arduino-examples/examples/04.Communication/SerialEvent/SerialEvent.ino + +- fqbn: infineon:xmc:kit_xmc1400_arduino + sketch: + - libraries/DeviceControlXMC/examples/StackMemoryMeasurement/StackMemoryMeasurement.ino + - extras/arduino-examples/examples/04.Communication/MultiSerial/MultiSerial.ino + - extras/arduino-examples/examples/04.Communication/SerialEvent/SerialEvent.ino + + + + diff --git a/config/project.yml b/config/project.yml new file mode 100644 index 00000000..f73e214c --- /dev/null +++ b/config/project.yml @@ -0,0 +1,404 @@ +# options: +# USE_CORE: +# name: infineon:xmc@3.5.0 +# url: https://github.com/Infineon/XMC-for-Arduino/releases/latest/download/package_infineon_index.json +options: + USE_CORE: + name: local + SEND_JOB_START_TOKEN: true +# # INCLUDE: + # - filename + +compile: + compile-xmc-kit_xmc47_relax: + description: Compiling test_digitalio_single.cpp for XMC platform + command: make -f Makefile.arduino.mk test_digitalio_single compile + fqbns: [infineon:xmc:kit_xmc47_relax] + working_dir: tests/arduino-core-tests + +code-quality: + source-code-quality-clang-tidy: + description: clang-tidy check sources + tool: clang-tidy + command: extras/makers-devops/src/python/code_checks/run_clang_tidy.sh ./cores/xmc/* ./libraries/* + + source-code-quality-cppcheck: + description: cppcheck check sources + tool: cppcheck + command: extras/makers-devops/src/python/code_checks/run_cppcheck.sh ./cores/xmc/* + | -I extras/arduino-core-api/api/ -I cores/xmc/xmc_lib/XMCLib/inc/ -I variants/XMC1400/config/KIT_XMC14_2GO + | -I variants/XMC1400 -I cores/xmc/avr -I cores/xmc/usblib -I cores/xmc/xmc_lib/inc + | -I /cores/xmc + | -i cores/xmc/xmc_lib/ -i cores/xmc/api/ --suppress=*:cores/xmc/xmc_lib/* + | --suppress=*:extras/arduino-core-api/api/* --suppress=*:cores/xmc/api/* + +# test-code-quality-clang-tidy: +# description: clang-tidy check tests +# tool: clang-tidy +# command: extras/makers-devops/tools/code_checks/run_clang_tidy.sh ./tests/arduino-core-tests/src/* + +# test-code-quality-cppcheck: +# description: cppcheck check tests +# tool: cppcheck +# command: extras/makers-devops/tools/code_checks/run_cppcheck.sh ./tests/arduino-core-tests/src/* +# | -I extras/arduino-core-api/api/ -I variants/CY8CKIT-062S2-AI/mtb-bsp -I extras/mtb-libs/core-lib/include +# | -I libraries/WiFi/src -I libraries/Wire/src -I libraries/SPI/src -I extras/mtb-libs/mtb-hal-cat1/include +# | -I extras/mtb-libs/wifi-connection-manager/include --suppress=*:extras/mtb-libs/wifi-connection-manager/include* +# | -I tests/arduino-core-tests/Unity/src --suppress=*:tests/arduino-core-tests/Unity/src/* +# | -I variants/CY8CKIT-062S2-AI -I cores/psoc6 --suppress=*:variants/CY8CKIT-062S2-AI/* --suppress=*:extras/mtb-libs/mtb-hal-cat1/include/* +# | --suppress=*:extras/arduino-core-api/api/* --suppress=*:cores/psoc6/api/* --suppress=*:variants/CY8CKIT-062S2-AI/mtb-bsp/* --suppress=*:extras/mtb-libs/core-lib/include/* + +# code-quality-clang-format: +# description: clang-tidy check sources +# tool: clang-format +# command: extras/makers-devops/tools/code_checks/run_clang_format.sh ./cores/psoc6/* ./libraries/* + +# code-quality-black-format: +# description: clang-tidy check sources +# tool: black-format +# command: extras/makers-devops/tools/code_checks/run_black.sh ./extras/makers-devops/tools/* + + + +unit-test: + unit-test-digital-io-4700: + - description: Compiling, flashing and monitoring digital IO unit test. + command: make test_digitalio_single + query: digital_io_single_board == '1:1' + working_dir: extras/arduino-core-tests + + unit-test-tone-4700: + - description: Compiling, flashing and monitoring tone, no-tone unit test. + command: make test_tone_no_tone + query: tone_no_tone_single_board == '1:1' + working_dir: extras/arduino-core-tests + + unit-test-interrupts-4700: + - description: Compiling, flashing and monitoring Interrupts unit test. + command: make test_interrupts_single + query: interrupts_single_board == '1:1' + working_dir: extras/arduino-core-tests + + unit-test-random-4700: + - description: Compiling, flashing and monitoring random unit test. + command: make test_random + query: random_single_board == '1:1' + working_dir: extras/arduino-core-tests + + unit-test-time-4700: + - description: Compiling, flashing and monitoring timer unit test. + command: make test_time_single + query: time_single_board == '1:1' + working_dir: extras/arduino-core-tests + + unit-test-analog-io-pwm-4700: + - description: Compiling, flashing and monitoring timer unit test. + command: make test_analogio_pwm + query: analogio_pwm_single_board == '1:1' + working_dir: extras/arduino-core-tests + + unit-test-analog-io-adc-4700: + - description: Compiling, flashing and monitoring ADC unit test. + command: make test_analogio_adc + query: analogio_adc_single_board == '1:1' + working_dir: extras/arduino-core-tests + + unit-test-analog-io-dac-4700: + - description: Compiling, flashing and monitoring DAC unit test. + command: make test_analogio_dac + query: analogio_adc_single_board == '1:1' + working_dir: extras/arduino-core-tests + + unit-test-iic-4700: + - description: Compiling, flashing and monitoring timer unit test. + command: make test_wire_connected1_pingpong + query: iic_ping_pong_single_board == '1:1' + working_dir: extras/arduino-core-tests + + unit-test-iic-pingpong-4700: + - description: Compiling, flashing and monitoring I2C pingpong slave unit test. + command: make test_wire_connected2_slavepingpong + query: iic_ping_pong_multiple_boards_slave == '1:1' + working_dir: extras/arduino-core-tests + + - description: Compiling, flashing and monitoring I2C pingpong master unit test. + command: make test_wire_connected2_masterpingpong + query: iic_ping_pong_multiple_boards_master == '1:1' + working_dir: extras/arduino-core-tests + + unit-test-uart-connected2-4700: + - description: Compiling, flashing and monitoring uart rx unit test. + command: make test_uart_connected2_rx ENABLE_SYNC=0 + query: uart_multiple_boards_rx == '1:1' + working_dir: extras/arduino-core-tests + options: + SEND_JOB_START_TOKEN: False + + - description: Compiling, flashing and monitoring uart tx unit test. + command: make test_uart_connected2_tx ENABLE_SYNC=0 + query: uart_multiple_boards_tx == '1:1' + working_dir: extras/arduino-core-tests + options: + SEND_JOB_START_TOKEN: False + + unit-test-uart-4700: + - description: Compiling, flashing and monitoring uart rx unit test. + command: make test_uart_rx ENABLE_SYNC=0 + query: uart_multiple_boards_rx == '1:1' + working_dir: extras/arduino-core-tests + options: + SEND_JOB_START_TOKEN: False + + - description: Compiling, flashing and monitoring uart tx unit test. + command: make test_uart_tx ENABLE_SYNC=0 + query: uart_multiple_boards_tx == '1:1' + working_dir: extras/arduino-core-tests + options: + SEND_JOB_START_TOKEN: False + + unit-test-pulse-4700: + - description: Compiling, flashing and monitoring pulse board1 unit test. + command: make test_pulse_board1 + query: adv_io_pulse_board1 == '1:1' + working_dir: extras/arduino-core-tests + + - description: Compiling, flashing and monitoring pulse board2 unit test. + command: make test_pulse_board2 + query: adv_io_pulse_board2 == '1:1' + working_dir: extras/arduino-core-tests + + unit-test-spi-pingpong-4700: + - description: Compiling, flashing and monitoring SPI pingpong slave unit test. + command: make test_spi_connected2_slavepingpong + query: spi_ping_pong_multiple_boards_slave == '1:1' + working_dir: extras/arduino-core-tests + options: + USE_CORE: + name: infineon:psoc6@0.8.1 + url: https://github.com/Infineon/arduino-core-psoc6/releases/latest/download/package_psoc6_index.json + + - description: Compiling, flashing and monitoring SPI pingpong master unit test. + command: make test_spi_connected2_masterpingpong + query: spi_ping_pong_multiple_boards_master == '1:1' + working_dir: extras/arduino-core-tests + + unit-test-spi-single-pingpong-4700: + - description: Compiling, flasging and monitoring SPI pingpong single_board. + command: make test_spi_connected1_loopback + query: spi_ping_pong_single_board == '1:1' + working_dir: extras/arduino-core-tests + + unit-test-onewire-DS18x20-4700: + - description: Compiling, flashing and monitoring OneWire sensor DS18B20 data. + command: make test_onewire_DS18x20 + query: onewire_DS18x20_board == '1:1' + working_dir: extras/arduino-core-tests + +########################################################################################## + unit-test-digital-io-1400: + - description: Compiling, flashing and monitoring digital IO unit test. + command: make test_digitalio_single ENABLE_SYNC=0 + query: digital_io_single_board == '2:1' + working_dir: extras/arduino-core-tests + options: + SEND_JOB_START_TOKEN: False + + unit-test-tone-1400: + - description: Compiling, flashing and monitoring tone, no-tone unit test. + command: make test_tone_no_tone + query: tone_no_tone_single_board == '2:1' + working_dir: extras/arduino-core-tests + + unit-test-interrupts-1400: + - description: Compiling, flashing and monitoring Interrupts unit test. + command: make test_interrupts_single + query: interrupts_single_board == '2:1' + working_dir: extras/arduino-core-tests + + unit-test-random-1400: + - description: Compiling, flashing and monitoring random unit test. + command: make test_random + query: random_single_board == '2:1' + working_dir: extras/arduino-core-tests + + unit-test-time-1400: + - description: Compiling, flashing and monitoring timer unit test. + command: make test_time_single + query: time_single_board == '2:1' + working_dir: extras/arduino-core-tests + + unit-test-analog-io-pwm-1400: + - description: Compiling, flashing and monitoring timer unit test. + command: make test_analogio_pwm + query: analogio_pwm_single_board == '2:1' + working_dir: extras/arduino-core-tests + + unit-test-analog-io-adc-1400: + - description: Compiling, flashing and monitoring ADC unit test. + command: make test_analogio_adc + query: analogio_adc_single_board == '2:1' + working_dir: extras/arduino-core-tests + + unit-test-iic-pingpong-1400: + - description: Compiling, flashing and monitoring I2C pingpong slave unit test. + command: make test_wire_connected2_slavepingpong + query: iic_ping_pong_multiple_boards_slave == '2:1' + working_dir: extras/arduino-core-tests + + - description: Compiling, flashing and monitoring I2C pingpong master unit test. + command: make test_wire_connected2_masterpingpong + query: iic_ping_pong_multiple_boards_master == '2:1' + working_dir: extras/arduino-core-tests + + unit-test-pulse-1400: + - description: Compiling, flashing and monitoring pulse board1 unit test. + command: make test_pulse_board1 + query: adv_io_pulse_board1 == '2:1' + working_dir: extras/arduino-core-tests + + - description: Compiling, flashing and monitoring pulse board2 unit test. + command: make test_pulse_board2 + query: adv_io_pulse_board2 == '2:1' + working_dir: extras/arduino-core-tests + + unit-test-spi-single-pingpong-1400: + - description: Compiling, flashing and monitoring SPI pingpong single_board. + command: make test_spi_connected1_loopback + query: spi_ping_pong_single_board == '2:1' + working_dir: extras/arduino-core-tests + + unit-test-onewire-DS18x20-1400: + - description: Compiling, flashing and monitoring OneWire sensor DS18B20 data. + command: make test_onewire_DS18x20 + query: onewire_DS18x20_board == '2:1' + working_dir: extras/arduino-core-tests + + unit-test-spi-pingpong-1400: + - description: Compiling, flashing and monitoring SPI pingpong slave unit test. + command: make test_spi_connected2_slavepingpong + query: spi_ping_pong_multiple_boards_slave == '1:1' + working_dir: extras/arduino-core-tests + options: + USE_CORE: + name: infineon:psoc6@0.8.1 + url: https://github.com/Infineon/arduino-core-psoc6/releases/latest/download/package_psoc6_index.json + + - description: Compiling, flashing and monitoring SPI pingpong master unit test. + command: make test_spi_connected2_masterpingpong + query: spi_ping_pong_multiple_boards_master == '2:1' + working_dir: extras/arduino-core-tests + + +######################################################################################### + unit-test-digital-io-1100: + - description: Compiling, flashing and monitoring digital IO unit test. + command: make test_digitalio_single ENABLE_SYNC=0 + query: digital_io_single_board == '3:1' + working_dir: extras/arduino-core-tests + options: + SEND_JOB_START_TOKEN: False + + unit-test-tone-1100: + - description: Compiling, flashing and monitoring tone, no-tone unit test. + command: make test_tone_no_tone + query: tone_no_tone_single_board == '3:1' + working_dir: extras/arduino-core-tests + + unit-test-interrupts-1100: + - description: Compiling, flashing and monitoring Interrupts unit test. + command: make test_interrupts_single + query: interrupts_single_board == '3:1' + working_dir: extras/arduino-core-tests + + unit-test-random-1100: + - description: Compiling, flashing and monitoring random unit test. + command: make test_random + query: random_single_board == '3:1' + working_dir: extras/arduino-core-tests + + unit-test-time-1100: + - description: Compiling, flashing and monitoring timer unit test. + command: make test_time_single + query: time_single_board == '3:1' + working_dir: extras/arduino-core-tests + + unit-test-analog-io-pwm-1100: + - description: Compiling, flashing and monitoring timer unit test. + command: make test_analogio_pwm + query: analogio_pwm_single_board == '3:1' + working_dir: extras/arduino-core-tests + + unit-test-analog-io-adc-1100: + - description: Compiling, flashing and monitoring ADC unit test. + command: make test_analogio_adc + query: analogio_adc_single_board == '3:1' + working_dir: extras/arduino-core-tests + + unit-test-iic-pingpong-1100: + - description: Compiling, flashing and monitoring I2C pingpong slave unit test. + command: make test_wire_connected2_slavepingpong + query: iic_ping_pong_multiple_boards_slave == '3:1' + working_dir: extras/arduino-core-tests + + - description: Compiling, flashing and monitoring I2C pingpong master unit test. + command: make test_wire_connected2_masterpingpong + query: iic_ping_pong_multiple_boards_master == '3:1' + working_dir: extras/arduino-core-tests + + unit-test-pulse-1100: + - description: Compiling, flashing and monitoring pulse board1 unit test. + command: make test_pulse_board1 + query: adv_io_pulse_board1 == '3:1' + working_dir: extras/arduino-core-tests + + - description: Compiling, flashing and monitoring pulse board2 unit test. + command: make test_pulse_board2 + query: adv_io_pulse_board2 == '3:1' + working_dir: extras/arduino-core-tests + + unit-test-spi-single-pingpong-1100: + - description: Compiling, flashing and monitoring SPI pingpong single_board. + command: make test_spi_connected1_loopback + query: spi_ping_pong_single_board == '3:1' + working_dir: extras/arduino-core-tests + + unit-test-onewire-DS18x20-1100: + - description: Compiling, flashing and monitoring OneWire sensor DS18B20 data. + command: make test_onewire_DS18x20 + query: onewire_DS18x20_board == '3:1' + working_dir: extras/arduino-core-tests + + unit-test-spi-pingpong-1100: + - description: Compiling, flashing and monitoring SPI pingpong slave unit test. + command: make test_spi_connected2_slavepingpong + query: spi_ping_pong_multiple_boards_slave == '1:1' + working_dir: extras/arduino-core-tests + options: + USE_CORE: + name: infineon:psoc6@0.8.1 + url: https://github.com/Infineon/arduino-core-psoc6/releases/latest/download/package_psoc6_index.json + + - description: Compiling, flashing and monitoring SPI pingpong master unit test. + command: make test_spi_connected2_masterpingpong + query: spi_ping_pong_multiple_boards_master == '3:1' + working_dir: extras/arduino-core-tests + +########################################################################################## + unit-test-can-1400-2go: + - description: Compiling, flashing and monitoring CAN unit test. + command: make test_can_single + query: can_single_board == '1:1' + working_dir: extras/arduino-core-tests + + unit-test-can-multi-1400-2go: + - description: Compiling, flashing and monitoring can node 1 test. + command: make test_can_connected2_node1 + query: can_multiple_boards_node1 == '1:1' + working_dir: extras/arduino-core-tests + + - description: Compiling, flashing and monitoring can node 2 test. + command: make test_can_connected2_node2 + query: can_multiple_boards_node2 == '1:1' + working_dir: extras/arduino-core-tests + + \ No newline at end of file diff --git a/config/user.yml b/config/user.yml new file mode 100644 index 00000000..356d2a0d --- /dev/null +++ b/config/user.yml @@ -0,0 +1,58 @@ +# code-quality: +# - source-code-quality-clang-tidy +# - source-code-quality-cppcheck +# - test-code-quality-clang-tidy +# - test-code-quality-cppcheck +# - code-quality-clang-format +# - code-quality-black-format + +# compile: +# - compile-psoc6-cy8ckit_062s2_ai + + +unit-test: + - unit-test-digital-io-4700 + - unit-test-tone-4700 + - unit-test-iic-pingpong-4700 + - unit-test-interrupts-4700 + - unit-test-random-4700 + - unit-test-uart-connected2-4700 + - unit-test-spi-pingpong-4700 + - unit-test-analog-io-pwm-4700 + - unit-test-pulse-4700 + - unit-test-time-4700 + - unit-test-iic-4700 + - unit-test-analog-io-adc-4700 + - unit-test-analog-io-dac-4700 + - unit-test-uart-4700 + - unit-test-spi-single-pingpong-4700 + - unit-test-onewire-DS18x20-4700 + + - unit-test-digital-io-1400 + - unit-test-tone-1400 + - unit-test-iic-pingpong-1400 + - unit-test-interrupts-1400 + - unit-test-random-1400 + - unit-test-spi-single-pingpong-1400 + - unit-test-pulse-1400 + - unit-test-time-1400 + - unit-test-onewire-DS18x20-1400 + - unit-test-analog-io-adc-1400 + - unit-test-analog-io-pwm-1400 + # - unit-test-spi-pingpong-1400 # disable because of current shared spi slave + + - unit-test-digital-io-1100 + - unit-test-tone-1100 + - unit-test-iic-pingpong-1100 + - unit-test-interrupts-1100 + - unit-test-random-1100 + - unit-test-spi-single-pingpong-1100 + - unit-test-pulse-1100 + - unit-test-time-1100 + - unit-test-onewire-DS18x20-1100 + - unit-test-analog-io-adc-1100 + - unit-test-analog-io-pwm-1100 + # - unit-test-spi-pingpong-1100 # disable because of current shared spi slave + + - unit-test-can-1400-2go + - unit-test-can-multi-1400-2go \ No newline at end of file diff --git a/cores/Client.h b/cores/Client.h deleted file mode 100644 index 111f335d..00000000 --- a/cores/Client.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - Copyright (c) 2011 Arduino. All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#ifndef client_h -#define client_h - -//**************************************************************************** -// @Project Includes -//**************************************************************************** -#include "Print.h" -#include "Stream.h" -#include "IPAddress.h" - -//**************************************************************************** -// @Class Definitions -//**************************************************************************** -class Client : public Stream { - -public: - virtual int connect(IPAddress ip, uint16_t port) = 0; - virtual int connect(const char *host, uint16_t port) = 0; - virtual size_t write(uint8_t) = 0; - virtual size_t write(const uint8_t *buf, size_t size) = 0; - virtual int available() = 0; - virtual int read() = 0; - virtual int read(uint8_t *buf, size_t size) = 0; - virtual int peek() = 0; - virtual void flush() = 0; - virtual void stop() = 0; - virtual uint8_t connected() = 0; - virtual operator bool() = 0; - -protected: - uint8_t *rawIPAddress(IPAddress &addr) { return addr.raw_address(); }; -}; - -#endif /* client_h */ diff --git a/cores/HardwareSerial.cpp b/cores/HardwareSerial.cpp deleted file mode 100644 index 685f0558..00000000 --- a/cores/HardwareSerial.cpp +++ /dev/null @@ -1,239 +0,0 @@ -/* - Copyright (c) 2011 Arduino. All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -//**************************************************************************** -// @Project Includes -//**************************************************************************** -#include "Arduino.h" - -//**************************************************************************** -// @Local Functions -//**************************************************************************** - -// Constructors //////////////////////////////////////////////////////////////// - -HardwareSerial::HardwareSerial(XMC_UART_t *xmc_uart_config, - RingBuffer *rx_buffer, - RingBuffer *tx_buffer) { - _XMC_UART_config = xmc_uart_config; - _rx_buffer = rx_buffer; - _tx_buffer = tx_buffer; -} - -// Public Methods ////////////////////////////////////////////////////////////// - -void HardwareSerial::begin(uint32_t speed) { begin(speed, SERIAL_8N1); } - -void HardwareSerial::begin(uint32_t speed, XMC_UART_MODE_t config) { - XMC_UART_CH_CONFIG_t uart_ch_config; - uart_ch_config.oversampling = 0; // Must be 0 or valid oversample for baud rate calculations - uart_ch_config.baudrate = speed; - uart_ch_config.data_bits = (uint8_t)(config & 0x00fU); - uart_ch_config.frame_length = uart_ch_config.data_bits; // Set same as data bits length - uart_ch_config.parity_mode = (XMC_USIC_CH_PARITY_MODE_t)(config & ~0xffU); - uart_ch_config.stop_bits = (uint8_t)((config & 0x0f0U) >> 4); - - XMC_UART_CH_Init(_XMC_UART_config->channel, &uart_ch_config); - - // dx0 is UART RX: source must be set - XMC_USIC_CH_SetInputSource(_XMC_UART_config->channel, XMC_USIC_CH_INPUT_DX0, - _XMC_UART_config->input_source_dx0); - - // Additional input multiplexing - // Check if dx1 is used - if (_XMC_UART_config->input_source_dx1 != XMC_INPUT_INVALID) - XMC_USIC_CH_SetInputSource(_XMC_UART_config->channel, XMC_USIC_CH_INPUT_DX1, - _XMC_UART_config->input_source_dx1); - - // Check if dx2 is used - if (_XMC_UART_config->input_source_dx2 != XMC_INPUT_INVALID) - XMC_USIC_CH_SetInputSource(_XMC_UART_config->channel, XMC_USIC_CH_INPUT_DX2, - _XMC_UART_config->input_source_dx2); - - // Check if dx3 is used - if (_XMC_UART_config->input_source_dx3 != XMC_INPUT_INVALID) - XMC_USIC_CH_SetInputSource(_XMC_UART_config->channel, XMC_USIC_CH_INPUT_DX3, - _XMC_UART_config->input_source_dx3); - - XMC_UART_CH_EnableEvent(_XMC_UART_config->channel, XMC_UART_CH_EVENT_ALTERNATIVE_RECEIVE | - XMC_UART_CH_EVENT_STANDARD_RECEIVE); - XMC_USIC_CH_SetInterruptNodePointer(_XMC_UART_config->channel, - XMC_USIC_CH_INTERRUPT_NODE_POINTER_RECEIVE, - _XMC_UART_config->irq_service_request); - XMC_USIC_CH_SetInterruptNodePointer(_XMC_UART_config->channel, - XMC_USIC_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE, - _XMC_UART_config->irq_service_request); - XMC_USIC_CH_SetInterruptNodePointer(_XMC_UART_config->channel, - XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER, - _XMC_UART_config->irq_service_request); - NVIC_SetPriority(_XMC_UART_config->irq_num, 3); - NVIC_EnableIRQ(_XMC_UART_config->irq_num); - - XMC_UART_CH_Start(_XMC_UART_config->channel); - - // TX pin setup put here to avoid startup corrupted characters being first sent - XMC_GPIO_Init(_XMC_UART_config->tx.port, _XMC_UART_config->tx.pin, - &(_XMC_UART_config->tx_config)); - - XMC_GPIO_Init(_XMC_UART_config->rx.port, _XMC_UART_config->rx.pin, - &(_XMC_UART_config->rx_config)); -} - -void HardwareSerial::end(void) { - // Wait for any outstanding data to be sent - flush(); - // Disable UART interrupt in NVIC - NVIC_DisableIRQ(_XMC_UART_config->irq_num); - // Clear any received data after stopping interrupts - _rx_buffer->_iHead = _rx_buffer->_iTail; -} - -void HardwareSerial::setInterruptPriority(uint32_t priority) { - NVIC_SetPriority(_XMC_UART_config->irq_num, priority & 0x03); -} - -uint32_t HardwareSerial::getInterruptPriority() { - return NVIC_GetPriority(_XMC_UART_config->irq_num); -} - -int HardwareSerial::available(void) { - int head = _rx_buffer->_iHead; // Snapshot index affected by irq - if (head >= _rx_buffer->_iTail) - return head - _rx_buffer->_iTail; - return SERIAL_BUFFER_SIZE - _rx_buffer->_iTail + head; -} - -int HardwareSerial::availableForWrite(void) { - int tail = _tx_buffer->_iTail; // Snapshot index affected by irq - if (_tx_buffer->_iHead >= tail) - return SERIAL_BUFFER_SIZE - 1 - _tx_buffer->_iHead + tail; - return tail - _tx_buffer->_iHead - 1; -} - -int HardwareSerial::peek(void) { - if (_rx_buffer->_iHead == _rx_buffer->_iTail) - return -1; - return _rx_buffer->_aucBuffer[_rx_buffer->_iTail]; -} - -int HardwareSerial::read(void) { - // if the head isn't ahead of the tail, we don't have any characters - if (_rx_buffer->_iHead == _rx_buffer->_iTail) - return -1; - - uint8_t uc = _rx_buffer->_aucBuffer[_rx_buffer->_iTail]; - _rx_buffer->_iTail++; - if (_rx_buffer->_iTail >= SERIAL_BUFFER_SIZE) - _rx_buffer->_iTail = 0; - return uc; -} - -void HardwareSerial::flush(void) { - while (_tx_buffer->_iHead != _tx_buffer->_iTail) - ; // wait for transmit data to be sent - - while (XMC_USIC_CH_GetTransmitBufferStatus(_XMC_UART_config->channel) == - XMC_USIC_CH_TBUF_STATUS_BUSY) - ; -} - -size_t HardwareSerial::write(const uint8_t uc_data) { -// Is the hardware currently busy? -#if defined(SERIAL_USE_U1C1) - if (_tx_buffer->_iTail != _tx_buffer->_iHead) -#else - if ((XMC_USIC_CH_GetTransmitBufferStatus(_XMC_UART_config->channel) == - XMC_USIC_CH_TBUF_STATUS_BUSY) || - (_tx_buffer->_iTail != _tx_buffer->_iHead)) -#endif - { - // If busy we buffer - int nextWrite = _tx_buffer->_iHead + 1; - if (nextWrite >= SERIAL_BUFFER_SIZE) - nextWrite = 0; - - // This should always be false but in case transmission is completed before buffer, we need - // to reenable IRQ - if (XMC_USIC_CH_GetTransmitBufferStatus(_XMC_UART_config->channel) != - XMC_USIC_CH_TBUF_STATUS_BUSY) { - XMC_UART_CH_EnableEvent(_XMC_UART_config->channel, XMC_UART_CH_EVENT_TRANSMIT_BUFFER); - XMC_UART_CH_Transmit(_XMC_UART_config->channel, - _tx_buffer->_aucBuffer[_tx_buffer->_iTail]); - _tx_buffer->_iTail++; - if (_tx_buffer->_iTail >= SERIAL_BUFFER_SIZE) - _tx_buffer->_iTail %= SERIAL_BUFFER_SIZE; // If iTail is larger than Serial Buffer - // Size calculate the correct index value - } - - unsigned long startTime = millis(); - while (_tx_buffer->_iTail == nextWrite) { - if (millis() - startTime > 1000) { - return 0; // Spin locks if we're about to overwrite the buffer. This continues once - // the data is - // sent - } - } - - _tx_buffer->_aucBuffer[_tx_buffer->_iHead] = uc_data; - _tx_buffer->_iHead = nextWrite; - } else { - // Make sure TX interrupt is enabled - XMC_UART_CH_EnableEvent(_XMC_UART_config->channel, XMC_UART_CH_EVENT_TRANSMIT_BUFFER); - // Bypass buffering and send character directly - XMC_UART_CH_Transmit(_XMC_UART_config->channel, uc_data); - } - return 1; -} - -void HardwareSerial::IrqHandler(void) { - uint32_t status = XMC_UART_CH_GetStatusFlag(_XMC_UART_config->channel); - - // Did we receive data? - if ((status & (XMC_UART_CH_STATUS_FLAG_ALTERNATIVE_RECEIVE_INDICATION | - XMC_UART_CH_STATUS_FLAG_RECEIVE_INDICATION)) != 0U) { - XMC_UART_CH_ClearStatusFlag(_XMC_UART_config->channel, - (XMC_UART_CH_STATUS_FLAG_ALTERNATIVE_RECEIVE_INDICATION | - XMC_UART_CH_STATUS_FLAG_RECEIVE_INDICATION)); - - while (_XMC_UART_config->channel->RBUFSR & - (USIC_CH_RBUFSR_RDV0_Msk | USIC_CH_RBUFSR_RDV1_Msk)) - _rx_buffer->store_char(XMC_UART_CH_GetReceivedData(_XMC_UART_config->channel)); - } - - // Do we need to keep sending data? - if ((status & XMC_UART_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION) != 0U) { - XMC_UART_CH_ClearStatusFlag(_XMC_UART_config->channel, - XMC_UART_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION); - - if (_tx_buffer->_iTail != _tx_buffer->_iHead) { - XMC_UART_CH_Transmit(_XMC_UART_config->channel, - _tx_buffer->_aucBuffer[_tx_buffer->_iTail]); - _tx_buffer->_iTail++; - if (_tx_buffer->_iTail >= SERIAL_BUFFER_SIZE) - _tx_buffer->_iTail %= SERIAL_BUFFER_SIZE; // If iTail is larger than Serial Buffer - // Size calculate the correct index value - } else { - // Mask off transmit interrupt so we don't get it any more - XMC_UART_CH_DisableEvent(_XMC_UART_config->channel, XMC_UART_CH_EVENT_TRANSMIT_BUFFER); - } - } -} - -//**************************************************************************** -// END OF FILE -//**************************************************************************** \ No newline at end of file diff --git a/cores/IPAddress.cpp b/cores/IPAddress.cpp deleted file mode 100644 index 6b0fe4df..00000000 --- a/cores/IPAddress.cpp +++ /dev/null @@ -1,112 +0,0 @@ -/* - Copyright (c) 2011 Arduino. All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -//**************************************************************************** -// @Project Includes -//**************************************************************************** -#include -#include - -//**************************************************************************** -// @Local Functions -//**************************************************************************** - -// Constructors //////////////////////////////////////////////////////////////// - -IPAddress::IPAddress() { _address.dword = 0; } - -// Public Methods ////////////////////////////////////////////////////////////// - -IPAddress::IPAddress(uint8_t first_octet, - uint8_t second_octet, - uint8_t third_octet, - uint8_t fourth_octet) { - _address.bytes[0] = first_octet; - _address.bytes[1] = second_octet; - _address.bytes[2] = third_octet; - _address.bytes[3] = fourth_octet; -} - -IPAddress::IPAddress(uint32_t address) { _address.dword = address; } - -IPAddress::IPAddress(const uint8_t *address) { - memcpy(_address.bytes, address, sizeof(_address.bytes)); -} - -bool IPAddress::fromString(const char *address) { - // TODO: add support for "a", "a.b", "a.b.c" formats - - uint16_t acc = 0; // Accumulator - uint8_t dots = 0; - - while (*address) { - char c = *address++; - if (c >= '0' && c <= '9') { - acc = acc * 10 + (c - '0'); - if (acc > 255) { - // Value out of [0..255] range - return false; - } - } else if (c == '.') { - if (dots == 3) { - // Too much dots (there must be 3 dots) - return false; - } - _address.bytes[dots++] = acc; - acc = 0; - } else { - // Invalid char - return false; - } - } - - if (dots != 3) { - // Too few dots (there must be 3 dots) - return false; - } - _address.bytes[3] = acc; - return true; -} - -IPAddress &IPAddress::operator=(const uint8_t *address) { - memcpy(_address.bytes, address, sizeof(_address.bytes)); - return *this; -} - -IPAddress &IPAddress::operator=(uint32_t address) { - _address.dword = address; - return *this; -} - -bool IPAddress::operator==(const uint8_t *addr) const { - return memcmp(addr, _address.bytes, sizeof(_address.bytes)) == 0; -} - -size_t IPAddress::printTo(Print &p) const { - size_t n = 0; - for (int i = 0; i < 3; i++) { - n += p.print(_address.bytes[i], DEC); - n += p.print('.'); - } - n += p.print(_address.bytes[3], DEC); - return n; -} - -//**************************************************************************** -// END OF FILE -//**************************************************************************** diff --git a/cores/IPAddress.h b/cores/IPAddress.h deleted file mode 100644 index aa68ab30..00000000 --- a/cores/IPAddress.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - Copyright (c) 2011 Arduino. All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#ifndef IPAddress_h -#define IPAddress_h - -//**************************************************************************** -// @Project Includes -//**************************************************************************** -#include -#include "Printable.h" -#include "WString.h" - -//**************************************************************************** -// @Class Definitions -//**************************************************************************** -class IPAddress : public Printable { -private: - union { - uint8_t bytes[4]; // IPv4 address - uint32_t dword; - } _address; - - // Access the raw byte array containing the address. Because this returns a pointer - // to the internal structure rather than a copy of the address this function should only - // be used when you know that the usage of the returned uint8_t* will be transient and not - // stored. - uint8_t *raw_address() { return _address.bytes; }; - -public: - // Constructors - IPAddress(); - IPAddress(uint8_t first_octet, uint8_t second_octet, uint8_t third_octet, uint8_t fourth_octet); - IPAddress(uint32_t address); - IPAddress(const uint8_t *address); - - bool fromString(const char *address); - - bool fromString(const String &address) { return fromString(address.c_str()); } - - // Overloaded cast operator to allow IPAddress objects to be used where a pointer - // to a four-byte uint8_t array is expected - operator uint32_t() const { return _address.dword; }; - - bool operator==(const IPAddress &addr) const { return _address.dword == addr._address.dword; }; - - bool operator==(const uint8_t *addr) const; - - // Overloaded index operator to allow getting and setting individual octets of the address - uint8_t operator[](int index) const { return _address.bytes[index]; }; - - uint8_t &operator[](int index) { return _address.bytes[index]; }; - - // Overloaded copy operators to allow initialisation of IPAddress objects from other types - IPAddress &operator=(const uint8_t *address); - IPAddress &operator=(uint32_t address); - - virtual size_t printTo(Print &p) const; - - friend class EthernetClass; - friend class UDP; - friend class Client; - friend class Server; - friend class DhcpClass; - friend class DNSClient; -}; - -const IPAddress INADDR_NONE(0, 0, 0, 0); - -#endif diff --git a/cores/Print.cpp b/cores/Print.cpp deleted file mode 100644 index 8d61cba2..00000000 --- a/cores/Print.cpp +++ /dev/null @@ -1,230 +0,0 @@ -/* - Copyright (c) 2011 Arduino. All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -//**************************************************************************** -// @Project Includes -//**************************************************************************** -#include -#include -#include -#include -#include "Arduino.h" - -// Public Methods ////////////////////////////////////////////////////////////// - -/* default implementation: may be overridden */ -size_t Print::write(const uint8_t *buffer, size_t size) { - size_t n = 0; - while (size--) { - if (write(*buffer++)) { - n++; - } else { - break; - } - } - return n; -} - -size_t Print::print(const __FlashStringHelper *ifsh) { - return print(reinterpret_cast(ifsh)); -} - -size_t Print::print(const String &s) { return write(s.c_str(), s.length()); } - -size_t Print::print(const char str[]) { return write(str); } - -size_t Print::print(char c) { return write(c); } - -size_t Print::print(unsigned char b, int base) { return print((unsigned long)b, base); } - -size_t Print::print(int n, int base) { return print((long)n, base); } - -size_t Print::print(unsigned int n, int base) { return print((unsigned long)n, base); } - -size_t Print::print(long n, int base) { - if (base == 0) { - return write(n); - } else if (base == 10) { - if (n < 0) { - int t = print('-'); - n = -n; - return printNumber(n, 10) + t; - } - return printNumber(n, 10); - } else { - return printNumber(n, base); - } -} - -size_t Print::print(unsigned long n, int base) { - if (base == 0) { - return write(n); - } else { - return printNumber(n, base); - } -} - -size_t Print::print(double n, int digits) { return printFloat(n, digits); } - -size_t Print::println(const __FlashStringHelper *ifsh) { - size_t n = print(ifsh); - n += println(); - return n; -} - -size_t Print::print(const Printable &x) { return x.printTo(*this); } - -size_t Print::println(void) { return write("\r\n"); } - -size_t Print::println(const String &s) { - size_t n = print(s); - n += println(); - return n; -} - -size_t Print::println(const char c[]) { - size_t n = print(c); - n += println(); - return n; -} - -size_t Print::println(char c) { - size_t n = print(c); - n += println(); - return n; -} - -size_t Print::println(unsigned char b, int base) { - size_t n = print(b, base); - n += println(); - return n; -} - -size_t Print::println(int num, int base) { - size_t n = print(num, base); - n += println(); - return n; -} - -size_t Print::println(unsigned int num, int base) { - size_t n = print(num, base); - n += println(); - return n; -} - -size_t Print::println(long num, int base) { - size_t n = print(num, base); - n += println(); - return n; -} - -size_t Print::println(unsigned long num, int base) { - size_t n = print(num, base); - n += println(); - return n; -} - -size_t Print::println(double num, int digits) { - size_t n = print(num, digits); - n += println(); - return n; -} - -size_t Print::println(const Printable &x) { - size_t n = print(x); - n += println(); - return n; -} - -// Private Methods ///////////////////////////////////////////////////////////// - -size_t Print::printNumber(unsigned long n, uint8_t base) { - char buf[8 * sizeof(long) + 1]; // Assumes 8-bit chars plus zero byte. - char *str = &buf[sizeof(buf) - 1]; - - *str = '\0'; - - // prevent crash if called with base == 1 - if (base < 2) { - base = 10; - } - - do { - char c = n % base; - n /= base; - - *--str = c < 10 ? c + '0' : c + 'A' - 10; - } while (n); - - return write(str); -} - -size_t Print::printFloat(double number, uint8_t digits) { - size_t n = 0; - - if (isnan(number)) { - return print("nan"); - } - if (isinf(number)) { - return print("inf"); - } - if (number > 4294967040.0) { - return print("ovf"); // constant determined empirically - } - if (number < -4294967040.0) { - return print("ovf"); // constant determined empirically - } - - // Handle negative numbers - if (number < 0.0) { - n += print('-'); - number = -number; - } - - // Round correctly so that print(1.999, 2) prints as "2.00" - double rounding = 0.5; - for (uint8_t i = 0; i < digits; ++i) { - rounding /= 10.0; - } - - number += rounding; - - // Extract the integer part of the number and print it - unsigned long int_part = (unsigned long)number; - double remainder = number - (double)int_part; - n += print(int_part); - - // Print the decimal point, but only if there are digits beyond - if (digits > 0) { - n += print("."); - } - - // Extract digits from the remainder one at a time - while (digits-- > 0) { - remainder *= 10.0; - unsigned int toPrint = (unsigned int)remainder; - n += print(toPrint); - remainder -= toPrint; - } - - return n; -} - -//**************************************************************************** -// END OF FILE -//**************************************************************************** diff --git a/cores/Print.h b/cores/Print.h deleted file mode 100644 index e879c5ab..00000000 --- a/cores/Print.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - Copyright (c) 2011 Arduino. All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#ifndef PRINT_H_ -#define PRINT_H_ - -#ifdef __cplusplus - - //**************************************************************************** - // @Project Includes - //**************************************************************************** - #include - #include // for size_t - #include "WString.h" - #include "Printable.h" - - //**************************************************************************** - // @Defines - //**************************************************************************** - #define DEC 10 - #define HEX 16 - #define OCT 8 - #define BIN 2 - -//**************************************************************************** -// @Class Definitions -//**************************************************************************** -class Print { -private: - int write_error; - size_t printNumber(unsigned long, uint8_t); - size_t printFloat(double, uint8_t); - -protected: - void setWriteError(int err = 1) { write_error = err; } - -public: - Print() - : write_error(0) {} - - int getWriteError() { return write_error; } - - void clearWriteError() { setWriteError(0); } - - virtual size_t write(uint8_t) = 0; - - size_t write(const char *str) { - if (str == NULL) { - return 0; - } - return write((const uint8_t *)str, strlen(str)); - } - - virtual size_t write(const uint8_t *buffer, size_t size); - - size_t write(const char *buffer, size_t size) { return write((const uint8_t *)buffer, size); } - - size_t print(const __FlashStringHelper *); - size_t print(const uint8_t *buffer, size_t size); - size_t print(const String &); - size_t print(const char[]); - size_t print(char); - size_t print(unsigned char, int = DEC); - size_t print(int, int = DEC); - size_t print(unsigned int, int = DEC); - size_t print(long, int = DEC); - size_t print(unsigned long, int = DEC); - size_t print(double, int = 2); - size_t print(const Printable &); - - size_t println(const __FlashStringHelper *); - size_t println(const uint8_t *buffer, size_t size); - size_t println(const String &s); - size_t println(const char[]); - size_t println(char); - size_t println(unsigned char, int = DEC); - size_t println(int, int = DEC); - size_t println(unsigned int, int = DEC); - size_t println(long, int = DEC); - size_t println(unsigned long, int = DEC); - size_t println(double, int = 2); - size_t println(const Printable &); - size_t println(void); -}; - -// extern Print Serial; -#endif // __cplusplus - -#endif /* PRINT_H_ */ diff --git a/cores/Printable.h b/cores/Printable.h deleted file mode 100644 index 3f7395bf..00000000 --- a/cores/Printable.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - Copyright (c) 2011 Arduino. All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#ifndef Printable_h -#define Printable_h - -#ifdef __cplusplus - - //**************************************************************************** - // @Project Includes - //**************************************************************************** - #include - -//**************************************************************************** -// @Class Definitions -//**************************************************************************** -class Print; - -/** The Printable class provides a way for new classes to allow themselves to be printed. - By deriving from Printable and implementing the printTo method, it will then be possible - for users to print out instances of this class by passing them into the usual - Print::print and Print::println methods. -*/ -class Printable { -public: - virtual size_t printTo(Print &p) const = 0; -}; - -#endif // __cplusplus - -#endif diff --git a/cores/RingBuffer.cpp b/cores/RingBuffer.cpp deleted file mode 100644 index 0d7ff8ad..00000000 --- a/cores/RingBuffer.cpp +++ /dev/null @@ -1,52 +0,0 @@ -/* - Copyright (c) 2011 Arduino. All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -//**************************************************************************** -// @Project Includes -//**************************************************************************** -#include "RingBuffer.h" -#include - -//**************************************************************************** -// @Local Functions -//**************************************************************************** - -// Constructors //////////////////////////////////////////////////////////////// - -RingBuffer::RingBuffer(void) { - memset((void *)_aucBuffer, 0, SERIAL_BUFFER_SIZE); - _iHead = 0; - _iTail = 0; -} - -void RingBuffer::store_char(uint8_t c) { - int i = (uint32_t)(_iHead + 1) % SERIAL_BUFFER_SIZE; - - // if we should be storing the received character into the location - // just before the tail (meaning that the head would advance to the - // current location of the tail), we're about to overflow the buffer - // and so we don't write the character or advance the head. - if (i != _iTail) { - _aucBuffer[_iHead] = c; - _iHead = i; - } -} - -//**************************************************************************** -// END OF FILE -//**************************************************************************** diff --git a/cores/RingBuffer.h b/cores/RingBuffer.h deleted file mode 100644 index 3b7e94e5..00000000 --- a/cores/RingBuffer.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - Copyright (c) 2011 Arduino. All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#ifndef _RING_BUFFER_ -#define _RING_BUFFER_ - -#include - -// Define constants and variables for buffering incoming serial data. We're -// using a ring buffer, in which head is the index of the location -// to which to write the next incoming character and tail is the index of the -// location from which to read. -#define SERIAL_BUFFER_SIZE 128 - -class RingBuffer { -public: - volatile uint8_t _aucBuffer[SERIAL_BUFFER_SIZE]; - volatile int _iHead; - volatile int _iTail; - -public: - RingBuffer(void); - void store_char(uint8_t c); -}; - -#endif /* _RING_BUFFER_ */ diff --git a/cores/Server.h b/cores/Server.h deleted file mode 100644 index 64053f57..00000000 --- a/cores/Server.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - Copyright (c) 2011 Arduino. All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#ifndef server_h -#define server_h - -//**************************************************************************** -// @Project Includes -//**************************************************************************** -#include "Print.h" - -//**************************************************************************** -// @Class Definitions -//**************************************************************************** -class Server : public Print { -public: - virtual void begin() = 0; -}; - -#endif /* server_h */ diff --git a/cores/Stream.cpp b/cores/Stream.cpp deleted file mode 100644 index 1963dc16..00000000 --- a/cores/Stream.cpp +++ /dev/null @@ -1,332 +0,0 @@ -/* - Copyright (c) 2011 Arduino. All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -//**************************************************************************** -// @Project Includes -//**************************************************************************** -#include "Arduino.h" - -//**************************************************************************** -// @Defines -//**************************************************************************** -#define PARSE_TIMEOUT 1000 // default number of milli-seconds to wait - -//**************************************************************************** -// @Local Functions -//**************************************************************************** - -// Private Methods ////////////////////////////////////////////////////////////// - -// private method to read stream with timeout -int Stream::timedRead() { - int c; - _startMillis = millis(); - do { - c = read(); - if (c >= 0) { - return c; - } - } while (millis() - _startMillis < _timeout); - return -1; // -1 indicates timeout -} - -// private method to peek stream with timeout -int Stream::timedPeek() { - int c; - _startMillis = millis(); - do { - c = peek(); - if (c >= 0) { - return c; - } - } while (millis() - _startMillis < _timeout); - return -1; // -1 indicates timeout -} - -// returns peek of the next digit in the stream or -1 if timeout -// discards non-numeric characters -int Stream::peekNextDigit(LookaheadMode lookahead, bool detectDecimal) { - int c; - while (1) { - c = timedPeek(); - - if (c < 0 || c == '-' || (c >= '0' && c <= '9') || (detectDecimal && c == '.')) { - return c; - } - - switch (lookahead) { - case SKIP_NONE: - return -1; // Fail code. - case SKIP_WHITESPACE: - switch (c) { - case ' ': - case '\t': - case '\r': - case '\n': - break; - default: - return -1; // Fail code. - } - case SKIP_ALL: - break; - } - read(); // discard non-numeric - } -} - -// Public Methods ////////////////////////////////////////////////////////////// - -void Stream::setTimeout(unsigned long timeout) // sets the maximum number of milliseconds to wait -{ - _timeout = timeout; -} - -// find returns true if the target string is found -bool Stream::find(char *target) { return findUntil(target, strlen(target), NULL, 0); } - -// reads data from the stream until the target string of given length is found -// returns true if target string is found, false if timed out -bool Stream::find(char *target, size_t length) { return findUntil(target, length, NULL, 0); } - -// as find but search ends if the terminator string is found -bool Stream::findUntil(char *target, char *terminator) { - return findUntil(target, strlen(target), terminator, strlen(terminator)); -} - -// reads data from the stream until the target string of the given length is found -// search terminated if the terminator string is found -// returns true if target string is found, false if terminated or timed out -bool Stream::findUntil(char *target, size_t targetLen, char *terminator, size_t termLen) { - if (terminator == NULL) { - MultiTarget t[1] = {{target, targetLen, 0}}; - return findMulti(t, 1) == 0 ? true : false; - } else { - MultiTarget t[2] = {{target, targetLen, 0}, {terminator, termLen, 0}}; - return findMulti(t, 2) == 0 ? true : false; - } -} - -// returns the first valid (long) integer value from the current position. -// lookahead determines how parseInt looks ahead in the stream. -// See LookaheadMode enumeration at the top of the file. -// Lookahead is terminated by the first character that is not a valid part of an integer. -// Once parsing commences, 'ignore' will be skipped in the stream. -long Stream::parseInt(LookaheadMode lookahead, char ignore) { - bool isNegative = false; - long value = 0; - int c; - - c = peekNextDigit(lookahead, false); - // ignore non numeric leading characters - if (c < 0) { - return 0; // zero returned if timeout - } - - do { - if (c == ignore) - ; // ignore this character - else if (c == '-') { - isNegative = true; - } else if (c >= '0' && c <= '9') // is c a digit? - { - value = value * 10 + c - '0'; - } - read(); // consume the character we got with peek - c = timedPeek(); - } while ((c >= '0' && c <= '9') || c == ignore); - - if (isNegative) { - value = -value; - } - return value; -} - -// as parseInt but returns a floating point value -float Stream::parseFloat(LookaheadMode lookahead, char ignore) { - bool isNegative = false; - bool isFraction = false; - long value = 0; - int c; - float fraction = 1.0; - - c = peekNextDigit(lookahead, true); - // ignore non numeric leading characters - if (c < 0) { - return 0; // zero returned if timeout - } - - do { - if (c == ignore) - ; // ignore - else if (c == '-') { - isNegative = true; - } else if (c == '.') { - isFraction = true; - } else if (c >= '0' && c <= '9') // is c a digit? - { - value = value * 10 + c - '0'; - if (isFraction) { - fraction *= 0.1; - } - } - read(); // consume the character we got with peek - c = timedPeek(); - } while ((c >= '0' && c <= '9') || (c == '.' && !isFraction) || c == ignore); - - if (isNegative) { - value = -value; - } - if (isFraction) { - return value * fraction; - } else { - return value; - } -} - -// read characters from stream into buffer -// terminates if length characters have been read, or timeout (see setTimeout) -// returns the number of characters placed in the buffer -// the buffer is NOT null terminated. -// -size_t Stream::readBytes(char *buffer, size_t length) { - size_t count = 0; - while (count < length) { - int c = timedRead(); - if (c < 0) { - break; - } - *buffer++ = (char)c; - count++; - } - return count; -} - -// as readBytes with terminator character -// terminates if length characters have been read, timeout, or if the terminator character detected -// returns the number of characters placed in the buffer (0 means no valid data found) - -size_t Stream::readBytesUntil(char terminator, char *buffer, size_t length) { - if (length < 1) { - return 0; - } - size_t index = 0; - while (index < length) { - int c = timedRead(); - if (c < 0 || c == terminator) { - break; - } - *buffer++ = (char)c; - index++; - } - return index; // return number of characters, not including null terminator -} - -String Stream::readString() { - String ret; - int c = timedRead(); - while (c >= 0) { - ret += (char)c; - c = timedRead(); - } - return ret; -} - -String Stream::readStringUntil(char terminator) { - String ret; - int c = timedRead(); - while (c >= 0 && c != terminator) { - ret += (char)c; - c = timedRead(); - } - return ret; -} - -int Stream::findMulti(struct Stream::MultiTarget *targets, int tCount) { - // any zero length target string automatically matches and would make - // a mess of the rest of the algorithm. - for (struct MultiTarget *t = targets; t < targets + tCount; ++t) { - if (t->len <= 0) { - return t - targets; - } - } - - while (1) { - int c = timedRead(); - if (c < 0) { - return -1; - } - - for (struct MultiTarget *t = targets; t < targets + tCount; ++t) { - // the simple case is if we match, deal with that first. - if (c == t->str[t->index]) { - if (++t->index == t->len) { - return t - targets; - } else { - continue; - } - } - - // if not we need to walk back and see if we could have matched further - // down the stream (ie '1112' doesn't match the first position in '11112' - // but it will match the second position so we can't just reset the current - // index to 0 when we find a mismatch. - if (t->index == 0) { - continue; - } - - int origIndex = t->index; - do { - --t->index; - // first check if current char works against the new current index - if (c != t->str[t->index]) { - continue; - } - - // if it's the only char then we're good, nothing more to check - if (t->index == 0) { - t->index++; - break; - } - - // otherwise we need to check the rest of the found string - int diff = origIndex - t->index; - size_t i; - for (i = 0; i < t->index; ++i) { - if (t->str[i] != t->str[i + diff]) { - break; - } - } - - // if we successfully got through the previous loop then our current - // index is good. - if (i == t->index) { - t->index++; - break; - } - - // otherwise we just try the next index - } while (t->index); - } - } - // unreachable - return -1; -} - -//**************************************************************************** -// END OF FILE -//**************************************************************************** diff --git a/cores/Stream.h b/cores/Stream.h deleted file mode 100644 index 4a4da9c3..00000000 --- a/cores/Stream.h +++ /dev/null @@ -1,171 +0,0 @@ -/* - Copyright (c) 2011 Arduino. All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#ifndef Stream_h -#define Stream_h - -//**************************************************************************** -// @Project Includes -//**************************************************************************** -#include -#include "Print.h" - -//**************************************************************************** -// @Defines -//**************************************************************************** - -// compatability macros for testing -/* -#define getInt() parseInt() -#define getInt(ignore) parseInt(ignore) -#define getFloat() parseFloat() -#define getFloat(ignore) parseFloat(ignore) -#define getString( pre_string, post_string, buffer, length) -readBytesBetween( pre_string, terminator, buffer, length) -*/ - -#define NO_IGNORE_CHAR '\x01' // a char not found in a valid ASCII numeric field - -//**************************************************************************** -// @Typedefs -//**************************************************************************** - -// This enumeration provides the lookahead options for parseInt(), parseFloat() -// The rules set out here are used until either the first valid character is found -// or a time out occurs due to lack of input. -enum LookaheadMode { - SKIP_ALL, // All invalid characters are ignored. - SKIP_NONE, // Nothing is skipped, and the stream is not touched unless the first waiting - // character is valid. - SKIP_WHITESPACE // Only tabs, spaces, line feeds & carriage returns are skipped. -}; - -//**************************************************************************** -// @Class Definitions -//**************************************************************************** -class Stream : public Print { -protected: - unsigned long - _timeout; // number of milliseconds to wait for the next char before aborting timed read - unsigned long _startMillis; // used for timeout measurement - int timedRead(); // private method to read stream with timeout - int timedPeek(); // private method to peek stream with timeout - int peekNextDigit( - LookaheadMode lookahead, - bool detectDecimal); // returns the next numeric digit in the stream or -1 if timeout - -public: - virtual int available() = 0; - virtual int read() = 0; - virtual int peek() = 0; - virtual void flush() = 0; - - Stream() { _timeout = 1000; } - - // parsing methods - - void setTimeout(unsigned long timeout); // sets maximum milliseconds to wait for stream data, - // default is 1 second - - unsigned long getTimeout(void) { return _timeout; } - - bool find(char *target); // reads data from the stream until the target string is found - - bool find(uint8_t *target) { return find((char *)target); } - - // returns true if target string is found, false if timed out (see setTimeout) - - bool find(char *target, size_t length); // reads data from the stream until the target string of - // given length is found - - bool find(uint8_t *target, size_t length) { return find((char *)target, length); } - - // returns true if target string is found, false if timed out - - bool find(char target) { return find(&target, 1); } - - bool findUntil(char *target, - char *terminator); // as find but search ends if the terminator string is found - - bool findUntil(uint8_t *target, char *terminator) { - return findUntil((char *)target, terminator); - } - - bool findUntil(char *target, - size_t targetLen, - char *terminate, - size_t termLen); // as above but search ends if the terminate string is found - - bool findUntil(uint8_t *target, size_t targetLen, char *terminate, size_t termLen) { - return findUntil((char *)target, targetLen, terminate, termLen); - } - - long parseInt(LookaheadMode lookahead = SKIP_ALL, char ignore = NO_IGNORE_CHAR); - // returns the first valid (long) integer value from the current position. - // lookahead determines how parseInt looks ahead in the stream. - // See LookaheadMode enumeration at the top of the file. - // Lookahead is terminated by the first character that is not a valid part of an integer. - // Once parsing commences, 'ignore' will be skipped in the stream. - - float parseFloat(LookaheadMode lookahead = SKIP_ALL, char ignore = NO_IGNORE_CHAR); - // float version of parseInt - - size_t readBytes(char *buffer, size_t length); // read chars from stream into buffer - - size_t readBytes(uint8_t *buffer, size_t length) { return readBytes((char *)buffer, length); } - - // terminates if length characters have been read or timeout (see setTimeout) - // returns the number of characters placed in the buffer (0 means no valid data found) - - size_t readBytesUntil(char terminator, - char *buffer, - size_t length); // as readBytes with terminator character - - size_t readBytesUntil(char terminator, uint8_t *buffer, size_t length) { - return readBytesUntil(terminator, (char *)buffer, length); - } - - // terminates if length characters have been read, timeout, or if the terminator character - // detected returns the number of characters placed in the buffer (0 means no valid data found) - - // Arduino String functions to be added here - String readString(); - String readStringUntil(char terminator); - -protected: - long parseInt(char ignore) { return parseInt(SKIP_ALL, ignore); } - - float parseFloat(char ignore) { return parseFloat(SKIP_ALL, ignore); } - - // These overload exists for compatibility with any class that has derived - // Stream and used parseFloat/Int with a custom ignore character. To keep - // the public API simple, these overload remains protected. - - struct MultiTarget { - const char *str; // string you're searching for - size_t len; // length of string you're searching for - size_t index; // index used by the search routine. - }; - - // This allows you to search for an arbitrary number of strings. - // Returns index of the target that is found first or -1 if timeout occurs. - int findMulti(struct MultiTarget *targets, int tCount); -}; - -#undef NO_IGNORE_CHAR -#endif /* Stream_h */ diff --git a/cores/Tone.h b/cores/Tone.h deleted file mode 100644 index 5551f152..00000000 --- a/cores/Tone.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - Copyright (c) 2011 Arduino. All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - - Copyright (c) 2018 Infineon Technologies AG - This file has been modified for the XMC microcontroller series. -*/ -#ifndef _WIRING_TONE_ -#define _WIRING_TONE_ - -//**************************************************************************** -// @External Prototypes -//**************************************************************************** -extern void tone(uint8_t, unsigned int, unsigned long = 0); -#ifdef __cplusplus -extern "C" { -#endif -extern void noTone(uint8_t); -extern int tone_irq_action(int, int16_t); -#ifdef __cplusplus -} -#endif - -#endif /* _WIRING_TONE_ */ diff --git a/cores/Udp.h b/cores/Udp.h deleted file mode 100644 index 6788a84f..00000000 --- a/cores/Udp.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - Copyright (c) 2011 Arduino. All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#ifndef udp_h -#define udp_h - -//**************************************************************************** -// @Project Includes -//**************************************************************************** -#include - -//**************************************************************************** -// @Class Definitions -//**************************************************************************** -class UDP : public Stream { - -public: - virtual uint8_t - begin(uint16_t) = 0; // initialize, start listening on specified port. Returns 1 if - // successful, 0 if there are no sockets available to use - virtual void stop() = 0; // Finish with the UDP socket - - // Sending UDP packets - - // Start building up a packet to send to the remote host specific in ip and port - // Returns 1 if successful, 0 if there was a problem with the supplied IP address or port - virtual int beginPacket(IPAddress ip, uint16_t port) = 0; - // Start building up a packet to send to the remote host specific in host and port - // Returns 1 if successful, 0 if there was a problem resolving the hostname or port - virtual int beginPacket(const char *host, uint16_t port) = 0; - // Finish off this packet and send it - // Returns 1 if the packet was sent successfully, 0 if there was an error - virtual int endPacket() = 0; - // Write a single byte into the packet - virtual size_t write(uint8_t) = 0; - // Write size bytes from buffer into the packet - virtual size_t write(const uint8_t *buffer, size_t size) = 0; - - // Start processing the next available incoming packet - // Returns the size of the packet in bytes, or 0 if no packets are available - virtual int parsePacket() = 0; - // Number of bytes remaining in the current packet - virtual int available() = 0; - // Read a single byte from the current packet - virtual int read() = 0; - // Read up to len bytes from the current packet and place them into buffer - // Returns the number of bytes read, or 0 if none are available - virtual int read(unsigned char *buffer, size_t len) = 0; - // Read up to len characters from the current packet and place them into buffer - // Returns the number of characters read, or 0 if none are available - virtual int read(char *buffer, size_t len) = 0; - // Return the next byte from the current packet without moving on to the next byte - virtual int peek() = 0; - virtual void flush() = 0; // Finish reading the current packet - - // Return the IP address of the host who sent the current incoming packet - virtual IPAddress remoteIP() = 0; - // Return the port of the host who sent the current incoming packet - virtual uint16_t remotePort() = 0; - -protected: - uint8_t *rawIPAddress(IPAddress &addr) { return addr.raw_address(); }; -}; - -#endif /* udp_h */ diff --git a/cores/WCharacter.h b/cores/WCharacter.h deleted file mode 100644 index 2d36d1c6..00000000 --- a/cores/WCharacter.h +++ /dev/null @@ -1,127 +0,0 @@ -/* - Copyright (c) 2011 Arduino. All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#ifndef Character_h -#define Character_h - -//**************************************************************************** -// @Project Includes -//**************************************************************************** -#include - -//**************************************************************************** -// @External Prototypes -//**************************************************************************** - -#ifdef __cplusplus -extern "C" { -#endif - -// WCharacter.h prototypes -#if defined(__GNUC__) -inline boolean isAlphaNumeric(int c) __attribute__((always_inline)); -inline boolean isAlpha(int c) __attribute__((always_inline)); -inline boolean isAscii(int c) __attribute__((always_inline)); -inline boolean isWhitespace(int c) __attribute__((always_inline)); -inline boolean isControl(int c) __attribute__((always_inline)); -inline boolean isDigit(int c) __attribute__((always_inline)); -inline boolean isGraph(int c) __attribute__((always_inline)); -inline boolean isLowerCase(int c) __attribute__((always_inline)); -inline boolean isPrintable(int c) __attribute__((always_inline)); -inline boolean isPunct(int c) __attribute__((always_inline)); -inline boolean isSpace(int c) __attribute__((always_inline)); -inline boolean isUpperCase(int c) __attribute__((always_inline)); -inline boolean isHexadecimalDigit(int c) __attribute__((always_inline)); -inline int toAscii(int c) __attribute__((always_inline)); -inline int toLowerCase(int c) __attribute__((always_inline)); -inline int toUpperCase(int c) __attribute__((always_inline)); -#elif defined(__ICCARM__) -#endif - -// Checks for an alphanumeric character. -// It is equivalent to (isalpha(c) || isdigit(c)). -inline boolean isAlphaNumeric(int c) { return (isalnum(c) == 0 ? false : true); } - -// Checks for an alphabetic character. -// It is equivalent to (isupper(c) || islower(c)). -inline boolean isAlpha(int c) { return (isalpha(c) == 0 ? false : true); } - -// Checks whether c is a 7-bit unsigned char value -// that fits into the ASCII character set. -inline boolean isAscii(int c) { - /* return ( isascii(c) == 0 ? false : true); */ - return ((c & ~0x7f) != 0 ? false : true); -} - -// Checks for a blank character, that is, a space or a tab. -inline boolean isWhitespace(int c) { return (isblank(c) == 0 ? false : true); } - -// Checks for a control character. -inline boolean isControl(int c) { return (iscntrl(c) == 0 ? false : true); } - -// Checks for a digit (0 through 9). -inline boolean isDigit(int c) { return (isdigit(c) == 0 ? false : true); } - -// Checks for any printable character except space. -inline boolean isGraph(int c) { return (isgraph(c) == 0 ? false : true); } - -// Checks for a lower-case character. -inline boolean isLowerCase(int c) { return (islower(c) == 0 ? false : true); } - -// Checks for any printable character including space. -inline boolean isPrintable(int c) { return (isprint(c) == 0 ? false : true); } - -// Checks for any printable character which is not a space -// or an alphanumeric character. -inline boolean isPunct(int c) { return (ispunct(c) == 0 ? false : true); } - -// Checks for white-space characters. For the avr-libc library, -// these are: space, formfeed ('\f'), newline ('\n'), carriage -// return ('\r'), horizontal tab ('\t'), and vertical tab ('\v'). -inline boolean isSpace(int c) { return (isspace(c) == 0 ? false : true); } - -// Checks for an uppercase letter. -inline boolean isUpperCase(int c) { return (isupper(c) == 0 ? false : true); } - -// Checks for a hexadecimal digits, i.e. one of 0 1 2 3 4 5 6 7 -// 8 9 a b c d e f A B C D E F. -inline boolean isHexadecimalDigit(int c) { return (isxdigit(c) == 0 ? false : true); } - -// Converts c to a 7-bit unsigned char value that fits into the -// ASCII character set, by clearing the high-order bits. -inline int toAscii(int c) { - /* return toascii (c); */ - return (c & 0x7f); -} - -// Warning: -// Many people will be unhappy if you use this function. -// This function will convert accented letters into random -// characters. - -// Converts the letter c to lower case, if possible. -inline int toLowerCase(int c) { return tolower(c); } - -// Converts the letter c to upper case, if possible. -inline int toUpperCase(int c) { return toupper(c); } - -#ifdef __cplusplus -} -#endif - -#endif /* Character_h */ diff --git a/cores/WInterrupts.c b/cores/WInterrupts.c deleted file mode 100644 index 9b6d8460..00000000 --- a/cores/WInterrupts.c +++ /dev/null @@ -1,217 +0,0 @@ -/* - Copyright (c) 2011 Arduino. All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - - Copyright (c) 2018 Infineon Technologies AG - This file has been modified for the XMC microcontroller series. -*/ - -//**************************************************************************** -// @Project Includes -//**************************************************************************** -#include "Arduino.h" - -//**************************************************************************** -// @Prototypes Of Local Functions -//**************************************************************************** -static interrupt_cb_t interrupt_0_cb = NULL; -static interrupt_cb_t interrupt_1_cb = NULL; - -//**************************************************************************** -// @Local Functions -//**************************************************************************** -#if defined(INTERRUPT_USE_ERU) -void ERU0_3_IRQHandler(void) { - if (interrupt_0_cb) { - interrupt_0_cb(); - } -} - - #if defined(XMC4200_Platform2GO) -void ERU0_0_IRQHandler(void) { - if (interrupt_1_cb) { - interrupt_1_cb(); - } -} - #else -void ERU1_0_IRQHandler(void) { - if (interrupt_1_cb) { - interrupt_1_cb(); - } -} - #endif - -#else -void CCU40_0_IRQHandler(void) { - if (interrupt_0_cb) { - interrupt_0_cb(); - } -} - -void CCU40_1_IRQHandler(void) { - if (interrupt_1_cb) { - interrupt_1_cb(); - } -} -#endif - -void attachInterrupt(uint32_t interrupt_num, interrupt_cb_t callback, uint32_t mode) { - if (interrupt_num < NUM_INTERRUPT) { - XMC_PIN_INTERRUPT_t pin_irq = mapping_interrupt[interrupt_num]; -#if defined(INTERRUPT_USE_ERU) - XMC_ERU_ETL_EDGE_DETECTION_t event_config = 0; - - switch (mode) { - case CHANGE: - event_config = XMC_ERU_ETL_EDGE_DETECTION_BOTH; - break; - - case RISING: - event_config = XMC_ERU_ETL_EDGE_DETECTION_RISING; - break; - - case FALLING: - event_config = XMC_ERU_ETL_EDGE_DETECTION_FALLING; - break; - - default: - event_config = XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_NONE; - break; - } - - XMC_ERU_Enable(pin_irq.eru); - XMC_ERU_ETL_SetInput(pin_irq.eru, pin_irq.etl, pin_irq.input_a, pin_irq.input_b); - XMC_ERU_ETL_SetEdgeDetection(pin_irq.eru, pin_irq.etl, event_config); - XMC_ERU_ETL_SetSource(pin_irq.eru, pin_irq.etl, XMC_ERU_ETL_SOURCE_B); - XMC_ERU_ETL_EnableOutputTrigger(pin_irq.eru, pin_irq.etl, pin_irq.ogu); - XMC_ERU_OGU_SetServiceRequestMode(pin_irq.eru, pin_irq.ogu, - XMC_ERU_OGU_SERVICE_REQUEST_ON_TRIGGER); - - if (pin_irq.irq_num == 0) { - NVIC_SetPriority(ERU0_3_IRQn, 3); - interrupt_0_cb = callback; - NVIC_EnableIRQ(ERU0_3_IRQn); - } else if (pin_irq.irq_num == 1) { - #if defined(XMC4200_Platform2GO) - NVIC_SetPriority(ERU0_0_IRQn, 3); - interrupt_1_cb = callback; - NVIC_EnableIRQ(ERU0_0_IRQn); - #else - NVIC_SetPriority(ERU1_0_IRQn, 3); - interrupt_1_cb = callback; - NVIC_EnableIRQ(ERU1_0_IRQn); - #endif - } -#else - XMC_CCU4_SLICE_EVENT_CONFIG_t event_config = {0}; - - switch (mode) { - case CHANGE: - event_config.edge = XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_DUAL_EDGE; - break; - - case RISING: - event_config.edge = XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_RISING_EDGE; - break; - - case FALLING: - event_config.edge = XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_FALLING_EDGE; - break; - - default: - event_config.edge = XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_NONE; - break; - } - - XMC_CCU4_Init(pin_irq.ccu, XMC_CCU4_SLICE_MCMS_ACTION_TRANSFER_PR_CR); - XMC_CCU4_EnableClock(pin_irq.ccu, pin_irq.slice_num); - - if (pin_irq.irq_num == 0) { - #if defined(XMC1100_Boot_Kit) || defined(XMC1400_Arduino_Kit) || defined(XMC1400_XMC2GO) - /* P1_4 external interrupt goes through USIC to CCU4 */ - XMC_USIC_CH_Enable(XMC_USIC0_CH0); - XMC_USIC_CH_SetInputSource(XMC_USIC0_CH0, XMC_USIC_CH_INPUT_DX5, USIC0_C0_DX5_P1_4); - XMC_USIC_CH_SetInputSource(XMC_USIC0_CH0, XMC_USIC_CH_INPUT_DX2, USIC0_C0_DX2_DX5INS); - #endif - XMC_CCU4_SLICE_EnableMultipleEvents(pin_irq.slice, XMC_CCU4_SLICE_MULTI_IRQ_ID_EVENT0); - XMC_CCU4_SLICE_SetInterruptNode(pin_irq.slice, XMC_CCU4_SLICE_IRQ_ID_EVENT0, 0); - NVIC_SetPriority(CCU40_0_IRQn, 3); - - event_config.mapped_input = pin_irq.input; - XMC_CCU4_SLICE_ConfigureEvent(pin_irq.slice, XMC_CCU4_SLICE_EVENT_0, &event_config); - - interrupt_0_cb = callback; - NVIC_EnableIRQ(CCU40_0_IRQn); - } else if (pin_irq.irq_num == 1) { - #if defined(XMC1300_Boot_Kit) - /* P0_13 external interrupt goes through USIC to CCU4 */ - XMC_USIC_CH_Enable(XMC_USIC0_CH0); - XMC_USIC_CH_SetInputSource(XMC_USIC0_CH0, XMC_USIC_CH_INPUT_DX2, USIC0_C0_DX2_P0_13); - #endif - #if defined(XMC1400_Arduino_Kit) - /* P1_1 external interrupt goes through USIC to CCU4 */ - XMC_USIC_CH_Enable(XMC_USIC0_CH1); - XMC_USIC_CH_SetInputSource(XMC_USIC0_CH1, XMC_USIC_CH_INPUT_DX2, USIC0_C1_DX2_P1_1); - #endif - XMC_CCU4_SLICE_EnableMultipleEvents(pin_irq.slice, XMC_CCU4_SLICE_MULTI_IRQ_ID_EVENT1); - XMC_CCU4_SLICE_SetInterruptNode(pin_irq.slice, XMC_CCU4_SLICE_IRQ_ID_EVENT1, 1); - NVIC_SetPriority(CCU40_1_IRQn, 3); - - event_config.mapped_input = pin_irq.input; - XMC_CCU4_SLICE_ConfigureEvent(pin_irq.slice, XMC_CCU4_SLICE_EVENT_1, &event_config); - - interrupt_1_cb = callback; - NVIC_EnableIRQ(CCU40_1_IRQn); - } -#endif - } -} - -void detachInterrupt(uint32_t interrupt_num) { - if (interrupt_num < NUM_INTERRUPT) { -#if defined(INTERRUPT_USE_ERU) - XMC_PIN_INTERRUPT_t pin_irq = mapping_interrupt[interrupt_num]; - switch (pin_irq.irq_num) { - case 0: - NVIC_DisableIRQ(ERU0_3_IRQn); - break; - - case 1: - #if defined(XMC4200_Platform2GO) - NVIC_DisableIRQ(ERU0_0_IRQn); - #else - NVIC_DisableIRQ(ERU1_0_IRQn); - #endif - break; -#else - switch (interrupt_num) { - case 0: - NVIC_DisableIRQ(CCU40_0_IRQn); - break; - - case 1: - NVIC_DisableIRQ(CCU40_1_IRQn); - break; -#endif - default: - break; - } - } -} - -//**************************************************************************** -// END OF FILE -//**************************************************************************** diff --git a/cores/WInterrupts.h b/cores/WInterrupts.h deleted file mode 100644 index db61c505..00000000 --- a/cores/WInterrupts.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - Copyright (c) 2011 Arduino. All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - - Copyright (c) 2018 Infineon Technologies AG - This file has been modified for the XMC microcontroller series. -*/ - -#ifndef W_INTERRUPTS_H -#define W_INTERRUPTS_H - -//**************************************************************************** -// @Project Includes -//**************************************************************************** -#include - -//**************************************************************************** -// @Defines -//**************************************************************************** -#define INT0 0 -#define INT1 1 - -#define PIN_INTERRUPT_NO_MODE 5 -#define FALLING 0 // same define as for LOW -#define RISING 1 // same define as for HIGH -#define CHANGE 2 - -//**************************************************************************** -// @Typedefs -//**************************************************************************** -typedef void (*interrupt_cb_t)(void); - -//**************************************************************************** -// @External Prototypes -//**************************************************************************** -void attachInterrupt(uint32_t, interrupt_cb_t, uint32_t); -void detachInterrupt(uint32_t); - -#endif /* W_INTERRUPTS_H */ diff --git a/cores/WMath.h b/cores/WMath.h deleted file mode 100644 index 1c188fc4..00000000 --- a/cores/WMath.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - Copyright (c) 2011 Arduino. All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#ifndef _WIRING_MATH_ -#define _WIRING_MATH_ - -//**************************************************************************** -// @External Prototypes -//**************************************************************************** -extern long random(long); -extern long random(long, long); -extern void randomSeed(uint32_t dwSeed); - -extern uint16_t makeWord(uint16_t w); -extern uint16_t makeWord(uint8_t h, uint8_t l); - -//**************************************************************************** -// @Defines -//**************************************************************************** -#define word(...) makeWord(__VA_ARGS__) - -#endif /* _WIRING_MATH_ */ diff --git a/cores/WString.cpp b/cores/WString.cpp deleted file mode 100644 index 7fb9b6bf..00000000 --- a/cores/WString.cpp +++ /dev/null @@ -1,704 +0,0 @@ -/* - Copyright (c) 2011 Arduino. All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -//**************************************************************************** -// @Project Includes -//**************************************************************************** -#define _STDBOOL_H 1 -#include "Arduino.h" -#include "itoa.h" -#include "dtostrf.h" -#include -#include -#include - -//**************************************************************************** -// @Local Functions -//**************************************************************************** - -// Constructors //////////////////////////////////////////////////////////////// - -String::String(const char *cstr) { - init(); - if (cstr) { - copy(cstr, strlen(cstr)); - } -} - -String::String(const String &value) { - init(); - *this = value; -} - -String::String(char c) { - init(); - char buf[2]; - buf[0] = c; - buf[1] = 0; - *this = buf; -} - -String::String(unsigned char value, unsigned char base) { - init(); - char buf[9]; - utoa(value, buf, base); - *this = buf; -} - -String::String(int value, unsigned char base) { - init(); - char buf[18]; - itoa(value, buf, base); - *this = buf; -} - -String::String(unsigned int value, unsigned char base) { - init(); - char buf[17]; - utoa(value, buf, base); - *this = buf; -} - -String::String(long value, unsigned char base) { - init(); - char buf[34]; - ltoa(value, buf, base); - *this = buf; -} - -String::String(unsigned long value, unsigned char base) { - init(); - char buf[33]; - ultoa(value, buf, base); - *this = buf; -} - -String::String(float value, unsigned char decimalPlaces) { - init(); - char buf[33]; - *this = dtostrf(value, (decimalPlaces + 2), decimalPlaces, buf); -} - -String::String(double value, unsigned char decimalPlaces) { - init(); - char buf[33]; - *this = dtostrf(value, (decimalPlaces + 2), decimalPlaces, buf); -} - -String::~String() { free(buffer); } - -// Public Methods ////////////////////////////////////////////////////////////// - -/*********************************************/ -/* Memory Management */ -/*********************************************/ - -inline void String::init(void) { - buffer = NULL; - capacity = 0; - len = 0; -} - -void String::invalidate(void) { - if (buffer) { - free(buffer); - } - buffer = NULL; - capacity = len = 0; -} - -unsigned char String::reserve(unsigned int size) { - if (buffer && capacity >= size) { - return 1; - } - if (changeBuffer(size)) { - if (len == 0) { - buffer[0] = 0; - } - return 1; - } - return 0; -} - -unsigned char String::changeBuffer(unsigned int maxStrLen) { - char *newbuffer = (char *)realloc(buffer, maxStrLen + 1); - if (newbuffer) { - buffer = newbuffer; - capacity = maxStrLen; - return 1; - } - return 0; -} - -/*********************************************/ -/* Copy and Move */ -/*********************************************/ - -String &String::copy(const char *cstr, unsigned int length) { - if (!reserve(length)) { - invalidate(); - return *this; - } - len = length; - strcpy(buffer, cstr); - return *this; -} - -String &String::operator=(const String &rhs) { - if (this == &rhs) { - return *this; - } - - if (rhs.buffer) { - copy(rhs.buffer, rhs.len); - } else { - invalidate(); - } - - return *this; -} - -String &String::operator=(const char *cstr) { - if (cstr) { - copy(cstr, strlen(cstr)); - } else { - invalidate(); - } - - return *this; -} - -/*********************************************/ -/* concat */ -/*********************************************/ - -unsigned char String::concat(const String &s) { return concat(s.buffer, s.len); } - -unsigned char String::concat(const char *cstr, unsigned int length) { - unsigned int newlen = len + length; - if (!cstr) { - return 0; - } - if (length == 0) { - return 1; - } - if (!reserve(newlen)) { - return 0; - } - strcpy(buffer + len, cstr); - len = newlen; - return 1; -} - -unsigned char String::concat(const char *cstr) { - if (!cstr) { - return 0; - } - return concat(cstr, strlen(cstr)); -} - -unsigned char String::concat(char c) { - char buf[2]; - buf[0] = c; - buf[1] = 0; - return concat(buf, 1); -} - -unsigned char String::concat(unsigned char num) { - char buf[4]; - itoa(num, buf, 10); - return concat(buf, strlen(buf)); -} - -unsigned char String::concat(int num) { - char buf[12]; - itoa(num, buf, 10); - return concat(buf, strlen(buf)); -} - -unsigned char String::concat(unsigned int num) { - char buf[11]; - utoa(num, buf, 10); - return concat(buf, strlen(buf)); -} - -unsigned char String::concat(long num) { - char buf[12]; - ltoa(num, buf, 10); - return concat(buf, strlen(buf)); -} - -unsigned char String::concat(unsigned long num) { - char buf[11]; - ultoa(num, buf, 10); - return concat(buf, strlen(buf)); -} - -unsigned char String::concat(float num) { - char buf[20]; - char *string = dtostrf(num, 4, 2, buf); - return concat(string, strlen(string)); -} - -unsigned char String::concat(double num) { - char buf[20]; - char *string = dtostrf(num, 4, 2, buf); - return concat(string, strlen(string)); -} - -/*********************************************/ -/* Concatenate */ -/*********************************************/ - -StringSumHelper &operator+(const StringSumHelper &lhs, const String &rhs) { - StringSumHelper &a = const_cast(lhs); - if (!a.concat(rhs.buffer, rhs.len)) { - a.invalidate(); - } - return a; -} - -StringSumHelper &operator+(const StringSumHelper &lhs, const char *cstr) { - StringSumHelper &a = const_cast(lhs); - if (!cstr || !a.concat(cstr, strlen(cstr))) { - a.invalidate(); - } - return a; -} - -StringSumHelper &operator+(const StringSumHelper &lhs, char c) { - StringSumHelper &a = const_cast(lhs); - if (!a.concat(c)) { - a.invalidate(); - } - return a; -} - -StringSumHelper &operator+(const StringSumHelper &lhs, unsigned char num) { - StringSumHelper &a = const_cast(lhs); - if (!a.concat(num)) { - a.invalidate(); - } - return a; -} - -StringSumHelper &operator+(const StringSumHelper &lhs, int num) { - StringSumHelper &a = const_cast(lhs); - if (!a.concat(num)) { - a.invalidate(); - } - return a; -} - -StringSumHelper &operator+(const StringSumHelper &lhs, unsigned int num) { - StringSumHelper &a = const_cast(lhs); - if (!a.concat(num)) { - a.invalidate(); - } - return a; -} - -StringSumHelper &operator+(const StringSumHelper &lhs, long num) { - StringSumHelper &a = const_cast(lhs); - if (!a.concat(num)) { - a.invalidate(); - } - return a; -} - -StringSumHelper &operator+(const StringSumHelper &lhs, unsigned long num) { - StringSumHelper &a = const_cast(lhs); - if (!a.concat(num)) { - a.invalidate(); - } - return a; -} - -StringSumHelper &operator+(const StringSumHelper &lhs, float num) { - StringSumHelper &a = const_cast(lhs); - if (!a.concat(num)) { - a.invalidate(); - } - return a; -} - -StringSumHelper &operator+(const StringSumHelper &lhs, double num) { - StringSumHelper &a = const_cast(lhs); - if (!a.concat(num)) { - a.invalidate(); - } - return a; -} - -/*********************************************/ -/* Comparison */ -/*********************************************/ - -int String::compareTo(const String &s) const { - if (!buffer || !s.buffer) { - if (s.buffer && s.len > 0) { - return 0 - *(unsigned char *)s.buffer; - } - if (buffer && len > 0) { - return *(unsigned char *)buffer; - } - return 0; - } - return strcmp(buffer, s.buffer); -} - -unsigned char String::equals(const String &s2) const { - return (len == s2.len && compareTo(s2) == 0); -} - -unsigned char String::equals(const char *cstr) const { - if (len == 0) { - return (cstr == NULL || *cstr == 0); - } - if (cstr == NULL) { - return buffer[0] == 0; - } - return strcmp(buffer, cstr) == 0; -} - -unsigned char String::operator<(const String &rhs) const { return compareTo(rhs) < 0; } - -unsigned char String::operator>(const String &rhs) const { return compareTo(rhs) > 0; } - -unsigned char String::operator<=(const String &rhs) const { return compareTo(rhs) <= 0; } - -unsigned char String::operator>=(const String &rhs) const { return compareTo(rhs) >= 0; } - -unsigned char String::equalsIgnoreCase(const String &s2) const { - if (this == &s2) { - return 1; - } - if (len != s2.len) { - return 0; - } - if (len == 0) { - return 1; - } - const char *p1 = buffer; - const char *p2 = s2.buffer; - while (*p1) { - if (tolower(*p1++) != tolower(*p2++)) { - return 0; - } - } - return 1; -} - -unsigned char String::startsWith(const String &s2) const { - if (len < s2.len) { - return 0; - } - return startsWith(s2, 0); -} - -unsigned char String::startsWith(const String &s2, unsigned int offset) const { - if (offset > len - s2.len || !buffer || !s2.buffer) { - return 0; - } - return strncmp(&buffer[offset], s2.buffer, s2.len) == 0; -} - -unsigned char String::endsWith(const String &s2) const { - if (len < s2.len || !buffer || !s2.buffer) { - return 0; - } - return strcmp(&buffer[len - s2.len], s2.buffer) == 0; -} - -/*********************************************/ -/* Character Access */ -/*********************************************/ - -char String::charAt(unsigned int loc) const { return operator[](loc); } - -void String::setCharAt(unsigned int loc, char c) { - if (loc < len) { - buffer[loc] = c; - } -} - -char &String::operator[](unsigned int index) { - static char dummy_writable_char; - if (index >= len || !buffer) { - dummy_writable_char = 0; - return dummy_writable_char; - } - return buffer[index]; -} - -char String::operator[](unsigned int index) const { - if (index >= len || !buffer) { - return 0; - } - return buffer[index]; -} - -void String::getBytes(unsigned char *buf, unsigned int bufsize, unsigned int index) const { - if (!bufsize || !buf) { - return; - } - if (index >= len) { - buf[0] = 0; - return; - } - unsigned int n = bufsize - 1; - if (n > len - index) { - n = len - index; - } - strncpy((char *)buf, buffer + index, n); - buf[n] = 0; -} - -/*********************************************/ -/* Search */ -/*********************************************/ - -int String::indexOf(char c) const { return indexOf(c, 0); } - -int String::indexOf(char ch, unsigned int fromIndex) const { - if (fromIndex >= len) { - return -1; - } - const char *temp = strchr(buffer + fromIndex, ch); - if (temp == NULL) { - return -1; - } - return temp - buffer; -} - -int String::indexOf(const String &s2) const { return indexOf(s2, 0); } - -int String::indexOf(const String &s2, unsigned int fromIndex) const { - if (fromIndex >= len) { - return -1; - } - const char *found = strstr(buffer + fromIndex, s2.buffer); - if (found == NULL) { - return -1; - } - return found - buffer; -} - -int String::lastIndexOf(char theChar) const { return lastIndexOf(theChar, len - 1); } - -int String::lastIndexOf(char ch, unsigned int fromIndex) const { - if (fromIndex >= len) { - return -1; - } - char tempchar = buffer[fromIndex + 1]; - buffer[fromIndex + 1] = '\0'; - char *temp = strrchr(buffer, ch); - buffer[fromIndex + 1] = tempchar; - if (temp == NULL) { - return -1; - } - return temp - buffer; -} - -int String::lastIndexOf(const String &s2) const { return lastIndexOf(s2, len - s2.len); } - -int String::lastIndexOf(const String &s2, unsigned int fromIndex) const { - if (s2.len == 0 || len == 0 || s2.len > len) { - return -1; - } - if (fromIndex >= len) { - fromIndex = len - 1; - } - int found = -1; - for (char *p = buffer; p <= buffer + fromIndex; p++) { - p = strstr(p, s2.buffer); - if (!p) { - break; - } - if ((unsigned int)(p - buffer) <= fromIndex) { - found = p - buffer; - } - } - return found; -} - -String String::substring(unsigned int left, unsigned int right) const { - if (left > right) { - unsigned int temp = right; - right = left; - left = temp; - } - String out; - if (left > len) { - return out; - } - if (right > len) { - right = len; - } - char temp = buffer[right]; // save the replaced character - buffer[right] = '\0'; - out = buffer + left; // pointer arithmetic - buffer[right] = temp; // restore character - return out; -} - -/*********************************************/ -/* Modification */ -/*********************************************/ - -void String::replace(char find, char replace) { - if (!buffer) { - return; - } - for (char *p = buffer; *p; p++) { - if (*p == find) { - *p = replace; - } - } -} - -void String::replace(const String &find, const String &replace) { - if (len == 0 || find.len == 0) { - return; - } - int diff = replace.len - find.len; - char *readFrom = buffer; - char *foundAt; - if (diff == 0) { - while ((foundAt = strstr(readFrom, find.buffer)) != NULL) { - memcpy(foundAt, replace.buffer, replace.len); - readFrom = foundAt + replace.len; - } - } else if (diff < 0) { - char *writeTo = buffer; - while ((foundAt = strstr(readFrom, find.buffer)) != NULL) { - unsigned int n = foundAt - readFrom; - memcpy(writeTo, readFrom, n); - writeTo += n; - memcpy(writeTo, replace.buffer, replace.len); - writeTo += replace.len; - readFrom = foundAt + find.len; - len += diff; - } - strcpy(writeTo, readFrom); - } else { - unsigned int size = len; // compute size needed for result - while ((foundAt = strstr(readFrom, find.buffer)) != NULL) { - readFrom = foundAt + find.len; - size += diff; - } - if (size == len) { - return; - } - if (size > capacity && !changeBuffer(size)) { - return; // XXX: tell user! - } - int index = len - 1; - while (index >= 0 && (index = lastIndexOf(find, index)) >= 0) { - readFrom = buffer + index + find.len; - memmove(readFrom + diff, readFrom, len - (readFrom - buffer)); - len += diff; - buffer[len] = 0; - memcpy(buffer + index, replace.buffer, replace.len); - index--; - } - } -} - -void String::remove(unsigned int index) { - if (index >= len) { - return; - } - int count = len - index; - remove(index, count); -} - -void String::remove(unsigned int index, unsigned int count) { - if (index >= len) { - return; - } - if (count <= 0) { - return; - } - if (index + count > len) { - count = len - index; - } - char *writeTo = buffer + index; - len = len - count; - strncpy(writeTo, buffer + index + count, len - index); - buffer[len] = 0; -} - -void String::toLowerCase(void) { - if (!buffer) { - return; - } - for (char *p = buffer; *p; p++) { - *p = tolower(*p); - } -} - -void String::toUpperCase(void) { - if (!buffer) { - return; - } - for (char *p = buffer; *p; p++) { - *p = toupper(*p); - } -} - -void String::trim(void) { - if (!buffer || len == 0) { - return; - } - char *begin = buffer; - while (isspace(*begin)) { - begin++; - } - char *end = buffer + len - 1; - while (isspace(*end) && end >= begin) { - end--; - } - len = end + 1 - begin; - if (begin > buffer) { - memcpy(buffer, begin, len); - } - buffer[len] = 0; -} - -/*********************************************/ -/* Parsing / Conversion */ -/*********************************************/ - -long String::toInt(void) const { - if (buffer) { - return atol(buffer); - } - return 0; -} - -float String::toFloat(void) const { - if (buffer) { - return float(atof(buffer)); - } - return 0; -} - -//**************************************************************************** -// END OF FILE -//**************************************************************************** diff --git a/cores/WString.h b/cores/WString.h deleted file mode 100644 index d724a681..00000000 --- a/cores/WString.h +++ /dev/null @@ -1,288 +0,0 @@ -/* - Copyright (c) 2011 Arduino. All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#ifndef String_class_h -#define String_class_h -#ifdef __cplusplus - - //**************************************************************************** - // @Project Includes - //**************************************************************************** - #include - #include - #include - #include "dtostrf.h" - -// When compiling programs with this class, the following gcc parameters -// dramatically increase performance and memory (RAM) efficiency, typically -// with little or no increase in code size. -// -felide-constructors -// -std=c++0x - -//**************************************************************************** -// @Class Definitions -//**************************************************************************** -class __FlashStringHelper; - #define F(string_literal) (reinterpret_cast(PSTR(string_literal))) - -// An inherited class for holding the result of a concatenation. These -// result objects are assumed to be writable by subsequent concatenations. -class StringSumHelper; - -// The string class -class String { - // use a function pointer to allow for "if (s)" without the - // complications of an operator bool(). for more information, see: - // http://www.artima.com/cppsource/safebool.html - typedef void (String::*StringIfHelperType)() const; - - void StringIfHelper() const {} - -public: - // constructors - // creates a copy of the initial value. - // if the initial value is null or invalid, or if memory allocation - // fails, the string will be marked as invalid (i.e. "if (s)" will - // be false). - String(const char *cstr = ""); - String(const String &str); - String(const __FlashStringHelper *str); - explicit String(char c); - explicit String(unsigned char, unsigned char base = 10); - explicit String(int, unsigned char base = 10); - explicit String(unsigned int, unsigned char base = 10); - explicit String(long, unsigned char base = 10); - explicit String(unsigned long, unsigned char base = 10); - explicit String(float, unsigned char decimalPlaces = 2); - explicit String(double, unsigned char decimalPlaces = 2); - ~String(void); - - // memory management - // return true on success, false on failure (in which case, the string - // is left unchanged). reserve(0), if successful, will validate an - // invalid string (i.e., "if (s)" will be true afterwards) - unsigned char reserve(unsigned int size); - - inline unsigned int length(void) const { return len; } - - // creates a copy of the assigned value. if the value is null or - // invalid, or if the memory allocation fails, the string will be - // marked as invalid ("if (s)" will be false). - String &operator=(const String &rhs); - String &operator=(const char *cstr); - String &operator=(const __FlashStringHelper *str); - - // concatenate (works w/ built-in types) - - // returns true on success, false on failure (in which case, the string - // is left unchanged). if the argument is null or invalid, the - // concatenation is considered unsucessful. - unsigned char concat(const String &str); - unsigned char concat(const char *cstr); - unsigned char concat(char c); - unsigned char concat(unsigned char c); - unsigned char concat(int num); - unsigned char concat(unsigned int num); - unsigned char concat(long num); - unsigned char concat(unsigned long num); - unsigned char concat(float num); - unsigned char concat(double num); - unsigned char concat(const __FlashStringHelper *str); - - // if there's not enough memory for the concatenated value, the string - // will be left unchanged (but this isn't signalled in any way) - String &operator+=(const String &rhs) { - concat(rhs); - return (*this); - } - - String &operator+=(const char *cstr) { - concat(cstr); - return (*this); - } - - String &operator+=(char c) { - concat(c); - return (*this); - } - - String &operator+=(unsigned char num) { - concat(num); - return (*this); - } - - String &operator+=(int num) { - concat(num); - return (*this); - } - - String &operator+=(unsigned int num) { - concat(num); - return (*this); - } - - String &operator+=(long num) { - concat(num); - return (*this); - } - - String &operator+=(unsigned long num) { - concat(num); - return (*this); - } - - String &operator+=(float num) { - concat(num); - return (*this); - } - - String &operator+=(double num) { - concat(num); - return (*this); - } - - String &operator+=(const __FlashStringHelper *str) { - concat(str); - return (*this); - } - - friend StringSumHelper &operator+(const StringSumHelper &lhs, const String &rhs); - friend StringSumHelper &operator+(const StringSumHelper &lhs, const char *cstr); - friend StringSumHelper &operator+(const StringSumHelper &lhs, char c); - friend StringSumHelper &operator+(const StringSumHelper &lhs, unsigned char num); - friend StringSumHelper &operator+(const StringSumHelper &lhs, int num); - friend StringSumHelper &operator+(const StringSumHelper &lhs, unsigned int num); - friend StringSumHelper &operator+(const StringSumHelper &lhs, long num); - friend StringSumHelper &operator+(const StringSumHelper &lhs, unsigned long num); - friend StringSumHelper &operator+(const StringSumHelper &lhs, float num); - friend StringSumHelper &operator+(const StringSumHelper &lhs, double num); - friend StringSumHelper &operator+(const StringSumHelper &lhs, const __FlashStringHelper *rhs); - - // comparison (only works w/ Strings and "strings") - operator StringIfHelperType() const { return buffer ? &String::StringIfHelper : 0; } - - int compareTo(const String &s) const; - unsigned char equals(const String &s) const; - unsigned char equals(const char *cstr) const; - - unsigned char operator==(const String &rhs) const { return equals(rhs); } - - unsigned char operator==(const char *cstr) const { return equals(cstr); } - - unsigned char operator!=(const String &rhs) const { return !equals(rhs); } - - unsigned char operator!=(const char *cstr) const { return !equals(cstr); } - - unsigned char operator<(const String &rhs) const; - unsigned char operator>(const String &rhs) const; - unsigned char operator<=(const String &rhs) const; - unsigned char operator>=(const String &rhs) const; - unsigned char equalsIgnoreCase(const String &s) const; - unsigned char startsWith(const String &prefix) const; - unsigned char startsWith(const String &prefix, unsigned int offset) const; - unsigned char endsWith(const String &suffix) const; - - // character acccess - char charAt(unsigned int index) const; - void setCharAt(unsigned int index, char c); - char operator[](unsigned int index) const; - char &operator[](unsigned int index); - void getBytes(unsigned char *buf, unsigned int bufsize, unsigned int index = 0) const; - - void toCharArray(char *buf, unsigned int bufsize, unsigned int index = 0) const { - getBytes((unsigned char *)buf, bufsize, index); - } - - const char *c_str() const { return buffer; } - - // search - int indexOf(char ch) const; - int indexOf(char ch, unsigned int fromIndex) const; - int indexOf(const String &str) const; - int indexOf(const String &str, unsigned int fromIndex) const; - int lastIndexOf(char ch) const; - int lastIndexOf(char ch, unsigned int fromIndex) const; - int lastIndexOf(const String &str) const; - int lastIndexOf(const String &str, unsigned int fromIndex) const; - - String substring(unsigned int beginIndex) const { return substring(beginIndex, len); }; - - String substring(unsigned int beginIndex, unsigned int endIndex) const; - - // modification - void replace(char find, char replace); - void replace(const String &find, const String &replace); - void remove(unsigned int index); - void remove(unsigned int index, unsigned int count); - void toLowerCase(void); - void toUpperCase(void); - void trim(void); - - // parsing/conversion - long toInt(void) const; - float toFloat(void) const; - - char *buffer; // the actual char array - unsigned int capacity; // the array length minus one (for the '\0') - unsigned int len; // the String length (not counting the '\0') - - void init(void); - void invalidate(void); - unsigned char changeBuffer(unsigned int maxStrLen); - unsigned char concat(const char *cstr, unsigned int length); - - // copy and move - String ©(const char *cstr, unsigned int length); - String ©(const __FlashStringHelper *pstr, unsigned int length); -}; - -class StringSumHelper : public String { -public: - StringSumHelper(const String &s) - : String(s) {} - - StringSumHelper(const char *p) - : String(p) {} - - StringSumHelper(char c) - : String(c) {} - - StringSumHelper(unsigned char num) - : String(num) {} - - StringSumHelper(int num) - : String(num) {} - - StringSumHelper(unsigned int num) - : String(num) {} - - StringSumHelper(long num) - : String(num) {} - - StringSumHelper(unsigned long num) - : String(num) {} - - StringSumHelper(float num) - : String(num) {} - - StringSumHelper(double num) - : String(num) {} -}; - -#endif // __cplusplus -#endif // String_class_h diff --git a/cores/Wprogram.h b/cores/Wprogram.h deleted file mode 100644 index 56ea2fef..00000000 --- a/cores/Wprogram.h +++ /dev/null @@ -1,31 +0,0 @@ -/* -Copyright (c) 2011 Arduino. All right reserved. - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -See the GNU Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#ifndef WPROGRAM_H_ -#define WPROGRAM_H_ - -//**************************************************************************** -// @Defines -//**************************************************************************** -#define _STDBOOL_H - -//**************************************************************************** -// @Project Includes -//**************************************************************************** - -#endif /* WPROGRAM_H_ */ diff --git a/cores/abi.cpp b/cores/abi.cpp deleted file mode 100644 index a9567602..00000000 --- a/cores/abi.cpp +++ /dev/null @@ -1,49 +0,0 @@ -/* - Copyright (c) 2011 Arduino. All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -//**************************************************************************** -// @Project Includes -//**************************************************************************** -#include - -//**************************************************************************** -// @External Prototypes -//**************************************************************************** -extern "C" void __cxa_pure_virtual(void) __attribute__((__noreturn__)); -extern "C" void __cxa_deleted_virtual(void) __attribute__((__noreturn__)); - -//**************************************************************************** -// @Local Functions -//**************************************************************************** -void __cxa_pure_virtual(void) { - // We might want to write some diagnostics to uart in this case - // std::terminate(); - while (1) - ; -} - -void __cxa_deleted_virtual(void) { - // We might want to write some diagnostics to uart in this case - // std::terminate(); - while (1) - ; -} - -//**************************************************************************** -// END OF FILE -//**************************************************************************** diff --git a/cores/avr/dtostrf.c b/cores/avr/dtostrf.c deleted file mode 100644 index 906a8960..00000000 --- a/cores/avr/dtostrf.c +++ /dev/null @@ -1,116 +0,0 @@ -/* - Copyright (c) 2011 Arduino. All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -//**************************************************************************** -// @Project Includes -//**************************************************************************** -#include "dtostrf.h" -#include -#include -#include -#include - -//**************************************************************************** -// @Local Functions -//**************************************************************************** - -char * dtostrf(double number, signed int width, unsigned int prec, char *s) { - bool negative = false; - - if (isnan(number)) { - strcpy(s, "nan"); - return s; - } - if (isinf(number)) { - strcpy(s, "inf"); - return s; - } - - char* out = s; - - int fillme = width; // how many cells to fill for the integer part - if (prec > 0) { - fillme -= (prec+1); - } - - // Handle negative numbers - if (number < 0.0) { - negative = true; - fillme--; - number = -number; - } - - // Round correctly so that print(1.999, 2) prints as "2.00" - // I optimized out most of the divisions - double rounding = 2.0; - for (unsigned int i = 0; i < prec; ++i) - rounding *= 10.0; - rounding = 1.0 / rounding; - - number += rounding; - - // Figure out how big our number really is - double tenpow = 1.0; - unsigned int digitcount = 1; - while (number >= 10.0 * tenpow) { - tenpow *= 10.0; - digitcount++; - } - - number /= tenpow; - fillme -= digitcount; - - // Pad unused cells with spaces - while (fillme-- > 0) { - *out++ = ' '; - } - - // Handle negative sign - if (negative) *out++ = '-'; - - // Print the digits, and if necessary, the decimal point - digitcount += prec; - int8_t digit = 0; - while (digitcount-- > 0) { - digit = (int8_t)number; - if (digit > 9) digit = 9; // insurance - *out++ = (char)('0' | digit); - if ((digitcount == prec) && (prec > 0)) { - *out++ = '.'; - } - number -= digit; - number *= 10.0; - } - - // make sure the string is terminated - *out = 0; - return s; -} - - - -//**************************************************************************** -// @Local Functions -//**************************************************************************** - - - -//**************************************************************************** -// END OF FILE -//**************************************************************************** - diff --git a/cores/avr/dtostrf.h b/cores/avr/dtostrf.h deleted file mode 100644 index 41d874bf..00000000 --- a/cores/avr/dtostrf.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - Copyright (c) 2011 Arduino. All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - - -#ifndef DTOSTRF_H_ -#define DTOSTRF_H_ - -//**************************************************************************** -// @External Prototypes -//**************************************************************************** - -/* - * \brief Converts a double into string.. - * - * \param val The double value to convert - * \param width Number of digits before the "." - * \param prec Number of digits after the "." - * \param s Resultant output string - */ - -char* dtostrf (double val, signed int width, unsigned int prec, char *s); - - -#endif /* DTOSTRF_H_ */ diff --git a/cores/avr/interrupt.h b/cores/avr/interrupt.h deleted file mode 100644 index 950509dd..00000000 --- a/cores/avr/interrupt.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - Copyright (c) 2015 Arduino LCC. All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -/* - Empty file. - This file is here to allow compatibility with sketches (made for AVR) - that includes -*/ diff --git a/cores/avr/io.h b/cores/avr/io.h deleted file mode 100644 index eb7ac22f..00000000 --- a/cores/avr/io.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - io.h - Definitions for compatibility with AVR io macros - - Copyright (c) 2016 Arduino LLC - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to deal - in the Software without restriction, including without limitation the rights - to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included in - all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - THE SOFTWARE -*/ - -//#ifndef _IO_H_ -//#define _IO_H_ -// -//#define RAMSTART (HMCRAMC0_ADDR) -//#define RAMSIZE (HMCRAMC0_SIZE) -//#define RAMEND (RAMSTART + RAMSIZE - 1) -// -//#endif - -/* - Empty file. - This file is here to allow compatibility with sketches (made for AVR) - that includes -*/ \ No newline at end of file diff --git a/cores/avr/pgmspace.h b/cores/avr/pgmspace.h deleted file mode 100644 index 46bc6504..00000000 --- a/cores/avr/pgmspace.h +++ /dev/null @@ -1,134 +0,0 @@ -/* - pgmspace.h - Definitions for compatibility with AVR pgmspace macros - - Copyright (c) 2015 Arduino LLC - - Based on work of Paul Stoffregen on Teensy 3 (http://pjrc.com) - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to deal - in the Software without restriction, including without limitation the rights - to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included in - all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - THE SOFTWARE -*/ - -#ifndef __PGMSPACE_H_ -#define __PGMSPACE_H_ 1 - -//**************************************************************************** -// @Project Includes -//**************************************************************************** -#include - -//**************************************************************************** -// @Defines -//**************************************************************************** -#define PROGMEM -#define PGM_P const char * -#define PSTR(str) (str) - -#define _SFR_BYTE(n) (n) - -//**************************************************************************** -// @Typedefs -//**************************************************************************** -typedef void prog_void; -typedef char prog_char; -typedef unsigned char prog_uchar; -typedef int8_t prog_int8_t; -typedef uint8_t prog_uint8_t; -typedef int16_t prog_int16_t; -typedef uint16_t prog_uint16_t; -typedef int32_t prog_int32_t; -typedef uint32_t prog_uint32_t; -typedef int64_t prog_int64_t; -typedef uint64_t prog_uint64_t; - -typedef const void* int_farptr_t; -typedef const void* uint_farptr_t; - -//**************************************************************************** -// @Macros -//**************************************************************************** -#define memchr_P(s, c, n) memchr((s), (c), (n)) -#define memcmp_P(s1, s2, n) memcmp((s1), (s2), (n)) -#define memccpy_P(dest, src, c, n) memccpy((dest), (src), (c), (n)) -#define memcpy_P(dest, src, n) memcpy((dest), (src), (n)) -#define memmem_P(haystack, haystacklen, needle, needlelen) memmem((haystack), (haystacklen), (needle), (needlelen)) -#define memrchr_P(s, c, n) memrchr((s), (c), (n)) -#define strcat_P(dest, src) strcat((dest), (src)) -#define strchr_P(s, c) strchr((s), (c)) -#define strchrnul_P(s, c) strchrnul((s), (c)) -#define strcmp_P(a, b) strcmp((a), (b)) -#define strcpy_P(dest, src) strcpy((dest), (src)) -#define strcasecmp_P(s1, s2) strcasecmp((s1), (s2)) -#define strcasestr_P(haystack, needle) strcasestr((haystack), (needle)) -#define strcspn_P(s, accept) strcspn((s), (accept)) -#define strlcat_P(s1, s2, n) strlcat((s1), (s2), (n)) -#define strlcpy_P(s1, s2, n) strlcpy((s1), (s2), (n)) -#define strlen_P(a) strlen((a)) -#define strnlen_P(s, n) strnlen((s), (n)) -#define strncmp_P(s1, s2, n) strncmp((s1), (s2), (n)) -#define strncasecmp_P(s1, s2, n) strncasecmp((s1), (s2), (n)) -#define strncat_P(s1, s2, n) strncat((s1), (s2), (n)) -#define strncpy_P(s1, s2, n) strncpy((s1), (s2), (n)) -#define strpbrk_P(s, accept) strpbrk((s), (accept)) -#define strrchr_P(s, c) strrchr((s), (c)) -#define strsep_P(sp, delim) strsep((sp), (delim)) -#define strspn_P(s, accept) strspn((s), (accept)) -#define strstr_P(a, b) strstr((a), (b)) -#define strtok_P(s, delim) strtok((s), (delim)) -#define strtok_rP(s, delim, last) strtok((s), (delim), (last)) - -#define strlen_PF(a) strlen((a)) -#define strnlen_PF(src, len) strnlen((src), (len)) -#define memcpy_PF(dest, src, len) memcpy((dest), (src), (len)) -#define strcpy_PF(dest, src) strcpy((dest), (src)) -#define strncpy_PF(dest, src, len) strncpy((dest), (src), (len)) -#define strcat_PF(dest, src) strcat((dest), (src)) -#define strlcat_PF(dest, src, len) strlcat((dest), (src), (len)) -#define strncat_PF(dest, src, len) strncat((dest), (src), (len)) -#define strcmp_PF(s1, s2) strcmp((s1), (s2)) -#define strncmp_PF(s1, s2, n) strncmp((s1), (s2), (n)) -#define strcasecmp_PF(s1, s2) strcasecmp((s1), (s2)) -#define strncasecmp_PF(s1, s2, n) strncasecmp((s1), (s2), (n)) -#define strstr_PF(s1, s2) strstr((s1), (s2)) -#define strlcpy_PF(dest, src, n) strlcpy((dest), (src), (n)) -#define memcmp_PF(s1, s2, n) memcmp((s1), (s2), (n)) - -#define sprintf_P(s, f, ...) sprintf((s), (f), __VA_ARGS__) -#define snprintf_P(s, f, ...) snprintf((s), (f), __VA_ARGS__) - -#define pgm_read_byte(addr) (*(const unsigned char *)(addr)) -#define pgm_read_word(addr) (*(const unsigned short *)(addr)) -#define pgm_read_dword(addr) (*(const unsigned long *)(addr)) -#define pgm_read_float(addr) (*(const float *)(addr)) -#define pgm_read_ptr(addr) (*(const void *)(addr)) - -#define pgm_read_byte_near(addr) pgm_read_byte(addr) -#define pgm_read_word_near(addr) pgm_read_word(addr) -#define pgm_read_dword_near(addr) pgm_read_dword(addr) -#define pgm_read_float_near(addr) pgm_read_float(addr) -#define pgm_read_ptr_near(addr) pgm_read_ptr(addr) - -#define pgm_read_byte_far(addr) pgm_read_byte(addr) -#define pgm_read_word_far(addr) pgm_read_word(addr) -#define pgm_read_dword_far(addr) pgm_read_dword(addr) -#define pgm_read_float_far(addr) pgm_read_float(addr) -#define pgm_read_ptr_far(addr) pgm_read_ptr(addr) - -#define pgm_get_far_address(addr) (&(addr)) - -#endif /* __PGMSPACE_H_ */ diff --git a/cores/binary.h b/cores/binary.h deleted file mode 100644 index 07dacad3..00000000 --- a/cores/binary.h +++ /dev/null @@ -1,536 +0,0 @@ -/* - Copyright (c) 2011 Arduino. All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#ifndef Binary_h -#define Binary_h - -//**************************************************************************** -// @Defines -//**************************************************************************** -#define B0 0 -#define B00 0 -#define B000 0 -#define B0000 0 -#define B00000 0 -#define B000000 0 -#define B0000000 0 -#define B00000000 0 -#define B1 1 -#define B01 1 -#define B001 1 -#define B0001 1 -#define B00001 1 -#define B000001 1 -#define B0000001 1 -#define B00000001 1 -#define B10 2 -#define B010 2 -#define B0010 2 -#define B00010 2 -#define B000010 2 -#define B0000010 2 -#define B00000010 2 -#define B11 3 -#define B011 3 -#define B0011 3 -#define B00011 3 -#define B000011 3 -#define B0000011 3 -#define B00000011 3 -#define B100 4 -#define B0100 4 -#define B00100 4 -#define B000100 4 -#define B0000100 4 -#define B00000100 4 -#define B101 5 -#define B0101 5 -#define B00101 5 -#define B000101 5 -#define B0000101 5 -#define B00000101 5 -#define B110 6 -#define B0110 6 -#define B00110 6 -#define B000110 6 -#define B0000110 6 -#define B00000110 6 -#define B111 7 -#define B0111 7 -#define B00111 7 -#define B000111 7 -#define B0000111 7 -#define B00000111 7 -#define B1000 8 -#define B01000 8 -#define B001000 8 -#define B0001000 8 -#define B00001000 8 -#define B1001 9 -#define B01001 9 -#define B001001 9 -#define B0001001 9 -#define B00001001 9 -#define B1010 10 -#define B01010 10 -#define B001010 10 -#define B0001010 10 -#define B00001010 10 -#define B1011 11 -#define B01011 11 -#define B001011 11 -#define B0001011 11 -#define B00001011 11 -#define B1100 12 -#define B01100 12 -#define B001100 12 -#define B0001100 12 -#define B00001100 12 -#define B1101 13 -#define B01101 13 -#define B001101 13 -#define B0001101 13 -#define B00001101 13 -#define B1110 14 -#define B01110 14 -#define B001110 14 -#define B0001110 14 -#define B00001110 14 -#define B1111 15 -#define B01111 15 -#define B001111 15 -#define B0001111 15 -#define B00001111 15 -#define B10000 16 -#define B010000 16 -#define B0010000 16 -#define B00010000 16 -#define B10001 17 -#define B010001 17 -#define B0010001 17 -#define B00010001 17 -#define B10010 18 -#define B010010 18 -#define B0010010 18 -#define B00010010 18 -#define B10011 19 -#define B010011 19 -#define B0010011 19 -#define B00010011 19 -#define B10100 20 -#define B010100 20 -#define B0010100 20 -#define B00010100 20 -#define B10101 21 -#define B010101 21 -#define B0010101 21 -#define B00010101 21 -#define B10110 22 -#define B010110 22 -#define B0010110 22 -#define B00010110 22 -#define B10111 23 -#define B010111 23 -#define B0010111 23 -#define B00010111 23 -#define B11000 24 -#define B011000 24 -#define B0011000 24 -#define B00011000 24 -#define B11001 25 -#define B011001 25 -#define B0011001 25 -#define B00011001 25 -#define B11010 26 -#define B011010 26 -#define B0011010 26 -#define B00011010 26 -#define B11011 27 -#define B011011 27 -#define B0011011 27 -#define B00011011 27 -#define B11100 28 -#define B011100 28 -#define B0011100 28 -#define B00011100 28 -#define B11101 29 -#define B011101 29 -#define B0011101 29 -#define B00011101 29 -#define B11110 30 -#define B011110 30 -#define B0011110 30 -#define B00011110 30 -#define B11111 31 -#define B011111 31 -#define B0011111 31 -#define B00011111 31 -#define B100000 32 -#define B0100000 32 -#define B00100000 32 -#define B100001 33 -#define B0100001 33 -#define B00100001 33 -#define B100010 34 -#define B0100010 34 -#define B00100010 34 -#define B100011 35 -#define B0100011 35 -#define B00100011 35 -#define B100100 36 -#define B0100100 36 -#define B00100100 36 -#define B100101 37 -#define B0100101 37 -#define B00100101 37 -#define B100110 38 -#define B0100110 38 -#define B00100110 38 -#define B100111 39 -#define B0100111 39 -#define B00100111 39 -#define B101000 40 -#define B0101000 40 -#define B00101000 40 -#define B101001 41 -#define B0101001 41 -#define B00101001 41 -#define B101010 42 -#define B0101010 42 -#define B00101010 42 -#define B101011 43 -#define B0101011 43 -#define B00101011 43 -#define B101100 44 -#define B0101100 44 -#define B00101100 44 -#define B101101 45 -#define B0101101 45 -#define B00101101 45 -#define B101110 46 -#define B0101110 46 -#define B00101110 46 -#define B101111 47 -#define B0101111 47 -#define B00101111 47 -#define B110000 48 -#define B0110000 48 -#define B00110000 48 -#define B110001 49 -#define B0110001 49 -#define B00110001 49 -#define B110010 50 -#define B0110010 50 -#define B00110010 50 -#define B110011 51 -#define B0110011 51 -#define B00110011 51 -#define B110100 52 -#define B0110100 52 -#define B00110100 52 -#define B110101 53 -#define B0110101 53 -#define B00110101 53 -#define B110110 54 -#define B0110110 54 -#define B00110110 54 -#define B110111 55 -#define B0110111 55 -#define B00110111 55 -#define B111000 56 -#define B0111000 56 -#define B00111000 56 -#define B111001 57 -#define B0111001 57 -#define B00111001 57 -#define B111010 58 -#define B0111010 58 -#define B00111010 58 -#define B111011 59 -#define B0111011 59 -#define B00111011 59 -#define B111100 60 -#define B0111100 60 -#define B00111100 60 -#define B111101 61 -#define B0111101 61 -#define B00111101 61 -#define B111110 62 -#define B0111110 62 -#define B00111110 62 -#define B111111 63 -#define B0111111 63 -#define B00111111 63 -#define B1000000 64 -#define B01000000 64 -#define B1000001 65 -#define B01000001 65 -#define B1000010 66 -#define B01000010 66 -#define B1000011 67 -#define B01000011 67 -#define B1000100 68 -#define B01000100 68 -#define B1000101 69 -#define B01000101 69 -#define B1000110 70 -#define B01000110 70 -#define B1000111 71 -#define B01000111 71 -#define B1001000 72 -#define B01001000 72 -#define B1001001 73 -#define B01001001 73 -#define B1001010 74 -#define B01001010 74 -#define B1001011 75 -#define B01001011 75 -#define B1001100 76 -#define B01001100 76 -#define B1001101 77 -#define B01001101 77 -#define B1001110 78 -#define B01001110 78 -#define B1001111 79 -#define B01001111 79 -#define B1010000 80 -#define B01010000 80 -#define B1010001 81 -#define B01010001 81 -#define B1010010 82 -#define B01010010 82 -#define B1010011 83 -#define B01010011 83 -#define B1010100 84 -#define B01010100 84 -#define B1010101 85 -#define B01010101 85 -#define B1010110 86 -#define B01010110 86 -#define B1010111 87 -#define B01010111 87 -#define B1011000 88 -#define B01011000 88 -#define B1011001 89 -#define B01011001 89 -#define B1011010 90 -#define B01011010 90 -#define B1011011 91 -#define B01011011 91 -#define B1011100 92 -#define B01011100 92 -#define B1011101 93 -#define B01011101 93 -#define B1011110 94 -#define B01011110 94 -#define B1011111 95 -#define B01011111 95 -#define B1100000 96 -#define B01100000 96 -#define B1100001 97 -#define B01100001 97 -#define B1100010 98 -#define B01100010 98 -#define B1100011 99 -#define B01100011 99 -#define B1100100 100 -#define B01100100 100 -#define B1100101 101 -#define B01100101 101 -#define B1100110 102 -#define B01100110 102 -#define B1100111 103 -#define B01100111 103 -#define B1101000 104 -#define B01101000 104 -#define B1101001 105 -#define B01101001 105 -#define B1101010 106 -#define B01101010 106 -#define B1101011 107 -#define B01101011 107 -#define B1101100 108 -#define B01101100 108 -#define B1101101 109 -#define B01101101 109 -#define B1101110 110 -#define B01101110 110 -#define B1101111 111 -#define B01101111 111 -#define B1110000 112 -#define B01110000 112 -#define B1110001 113 -#define B01110001 113 -#define B1110010 114 -#define B01110010 114 -#define B1110011 115 -#define B01110011 115 -#define B1110100 116 -#define B01110100 116 -#define B1110101 117 -#define B01110101 117 -#define B1110110 118 -#define B01110110 118 -#define B1110111 119 -#define B01110111 119 -#define B1111000 120 -#define B01111000 120 -#define B1111001 121 -#define B01111001 121 -#define B1111010 122 -#define B01111010 122 -#define B1111011 123 -#define B01111011 123 -#define B1111100 124 -#define B01111100 124 -#define B1111101 125 -#define B01111101 125 -#define B1111110 126 -#define B01111110 126 -#define B1111111 127 -#define B01111111 127 -#define B10000000 128 -#define B10000001 129 -#define B10000010 130 -#define B10000011 131 -#define B10000100 132 -#define B10000101 133 -#define B10000110 134 -#define B10000111 135 -#define B10001000 136 -#define B10001001 137 -#define B10001010 138 -#define B10001011 139 -#define B10001100 140 -#define B10001101 141 -#define B10001110 142 -#define B10001111 143 -#define B10010000 144 -#define B10010001 145 -#define B10010010 146 -#define B10010011 147 -#define B10010100 148 -#define B10010101 149 -#define B10010110 150 -#define B10010111 151 -#define B10011000 152 -#define B10011001 153 -#define B10011010 154 -#define B10011011 155 -#define B10011100 156 -#define B10011101 157 -#define B10011110 158 -#define B10011111 159 -#define B10100000 160 -#define B10100001 161 -#define B10100010 162 -#define B10100011 163 -#define B10100100 164 -#define B10100101 165 -#define B10100110 166 -#define B10100111 167 -#define B10101000 168 -#define B10101001 169 -#define B10101010 170 -#define B10101011 171 -#define B10101100 172 -#define B10101101 173 -#define B10101110 174 -#define B10101111 175 -#define B10110000 176 -#define B10110001 177 -#define B10110010 178 -#define B10110011 179 -#define B10110100 180 -#define B10110101 181 -#define B10110110 182 -#define B10110111 183 -#define B10111000 184 -#define B10111001 185 -#define B10111010 186 -#define B10111011 187 -#define B10111100 188 -#define B10111101 189 -#define B10111110 190 -#define B10111111 191 -#define B11000000 192 -#define B11000001 193 -#define B11000010 194 -#define B11000011 195 -#define B11000100 196 -#define B11000101 197 -#define B11000110 198 -#define B11000111 199 -#define B11001000 200 -#define B11001001 201 -#define B11001010 202 -#define B11001011 203 -#define B11001100 204 -#define B11001101 205 -#define B11001110 206 -#define B11001111 207 -#define B11010000 208 -#define B11010001 209 -#define B11010010 210 -#define B11010011 211 -#define B11010100 212 -#define B11010101 213 -#define B11010110 214 -#define B11010111 215 -#define B11011000 216 -#define B11011001 217 -#define B11011010 218 -#define B11011011 219 -#define B11011100 220 -#define B11011101 221 -#define B11011110 222 -#define B11011111 223 -#define B11100000 224 -#define B11100001 225 -#define B11100010 226 -#define B11100011 227 -#define B11100100 228 -#define B11100101 229 -#define B11100110 230 -#define B11100111 231 -#define B11101000 232 -#define B11101001 233 -#define B11101010 234 -#define B11101011 235 -#define B11101100 236 -#define B11101101 237 -#define B11101110 238 -#define B11101111 239 -#define B11110000 240 -#define B11110001 241 -#define B11110010 242 -#define B11110011 243 -#define B11110100 244 -#define B11110101 245 -#define B11110110 246 -#define B11110111 247 -#define B11111000 248 -#define B11111001 249 -#define B11111010 250 -#define B11111011 251 -#define B11111100 252 -#define B11111101 253 -#define B11111110 254 -#define B11111111 255 - -#endif /* Binary_h */ diff --git a/cores/hooks.c b/cores/hooks.c deleted file mode 100644 index 3fd476f1..00000000 --- a/cores/hooks.c +++ /dev/null @@ -1,32 +0,0 @@ -/* - Copyright (c) 2012 Arduino. All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -/** - * Empty yield() hook. - * - * This function is intended to be used by library writers to build - * libraries or sketches that supports cooperative threads. - * - * Its defined as a weak symbol and it can be redefined to implement a - * real cooperative scheduler. - */ -static void __empty() { - // Empty -} - -void yield(void) __attribute__((weak, alias("__empty"))); diff --git a/cores/itoa.c b/cores/itoa.c deleted file mode 100644 index d0698dcb..00000000 --- a/cores/itoa.c +++ /dev/null @@ -1,172 +0,0 @@ -/* - Copyright (c) 2011 Arduino. All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -//**************************************************************************** -// @Project Includes -//**************************************************************************** -#include "itoa.h" -#include - -//**************************************************************************** -// @Local Functions -//**************************************************************************** - -#ifdef __cplusplus -extern "C" { -#endif // __cplusplus - -#if 0 - /* reverse: reverse string s in place */ - static void reverse( char s[] ) - { - int i, j ; - char c ; - - for ( i = 0, j = strlen(s) - 1 ; i < j ; i++, j-- ) - { - c = s[i] ; - s[i] = s[j] ; - s[j] = c ; - } - } - - /* itoa: convert n to characters in s */ - extern void itoa( int n, char s[] ) - { - int i, sign ; - - if ( (sign = n) < 0 ) /* record sign */ - { - n = -n; /* make n positive */ - } - - i = 0; - do - { - /* generate digits in reverse order */ - s[i++] = n % 10 + '0'; /* get next digit */ - } - while ((n /= 10) > 0) ; /* delete it */ - - if (sign < 0 ) - { - s[i++] = '-'; - } - - s[i] = '\0'; - - reverse( s ) ; - } - -#else - -extern char *itoa(int value, char *string, int radix) { return ltoa(value, string, radix); } - -extern char *ltoa(long value, char *string, int radix) { - char tmp[33]; - char *tp = tmp; - long i; - unsigned long v; - int sign; - char *sp; - - if (string == NULL) { - return 0; - } - - if (radix > 36 || radix <= 1) { - return 0; - } - - sign = (radix == 10 && value < 0); - if (sign) { - v = -value; - } else { - v = (unsigned long)value; - } - - while (v || tp == tmp) { - i = v % radix; - v = v / radix; - if (i < 10) { - *tp++ = i + '0'; - } else { - *tp++ = i + 'a' - 10; - } - } - - sp = string; - - if (sign) { - *sp++ = '-'; - } - while (tp > tmp) { - *sp++ = *--tp; - } - *sp = 0; - - return string; -} - -extern char *utoa(unsigned int value, char *string, int radix) { - return ultoa(value, string, radix); -} - -extern char *ultoa(unsigned long value, char *string, int radix) { - char tmp[33]; - char *tp = tmp; - long i; - unsigned long v = value; - char *sp; - - if (string == NULL) { - return 0; - } - - if (radix > 36 || radix <= 1) { - return 0; - } - - while (v || tp == tmp) { - i = v % radix; - v = v / radix; - if (i < 10) { - *tp++ = i + '0'; - } else { - *tp++ = i + 'a' - 10; - } - } - - sp = string; - - while (tp > tmp) { - *sp++ = *--tp; - } - *sp = 0; - - return string; -} -#endif /* 0 */ - -#ifdef __cplusplus -} // extern "C" -#endif // __cplusplus - -//**************************************************************************** -// END OF FILE -//**************************************************************************** diff --git a/cores/itoa.h b/cores/itoa.h deleted file mode 100644 index 0a065793..00000000 --- a/cores/itoa.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - Copyright (c) 2011 Arduino. All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#ifndef _ITOA_ -#define _ITOA_ - -//**************************************************************************** -// @External Prototypes -//**************************************************************************** - -#ifdef __cplusplus -extern "C" { -#endif // __cplusplus - -#if 0 - - extern void itoa( int n, char s[] ) ; - -#else - -extern char *itoa(int value, char *string, int radix); -extern char *ltoa(long value, char *string, int radix); -extern char *utoa(unsigned int value, char *string, int radix); -extern char *ultoa(unsigned long value, char *string, int radix); -#endif /* 0 */ - -#ifdef __cplusplus -} // extern "C" -#endif // __cplusplus - -#endif // _ITOA_ diff --git a/cores/new.cpp b/cores/new.cpp deleted file mode 100644 index 969e0294..00000000 --- a/cores/new.cpp +++ /dev/null @@ -1,38 +0,0 @@ -/* - Copyright (c) 2011 Arduino. All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -//**************************************************************************** -// @Project Includes -//**************************************************************************** -#include - -//**************************************************************************** -// @Local Functions -//**************************************************************************** - -void *operator new(size_t size) { return malloc(size); } - -void *operator new[](size_t size) { return malloc(size); } - -void operator delete(void *ptr) { free(ptr); } - -void operator delete[](void *ptr) { free(ptr); } - -//**************************************************************************** -// END OF FILE -//**************************************************************************** diff --git a/cores/usblib/Class/CDCClass.h b/cores/usblib/Class/CDCClass.h deleted file mode 100644 index 3afbbdb9..00000000 --- a/cores/usblib/Class/CDCClass.h +++ /dev/null @@ -1,85 +0,0 @@ -#ifdef XMC4_SERIES - -/* - LUFA Library - Copyright (C) Dean Camera, 2014. - - dean [at] fourwalledcubicle [dot] com - www.lufa-lib.org -*/ - -/* - Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com) - - Permission to use, copy, modify, distribute, and sell this - software and its documentation for any purpose is hereby granted - without fee, provided that the above copyright notice appear in - all copies and that both that the copyright notice and this - permission notice and warranty disclaimer appear in supporting - documentation, and that the name of the author not be used in - advertising or publicity pertaining to distribution of the - software without specific, written prior permission. - - The author disclaims all warranties with regard to this - software, including all implied warranties of merchantability - and fitness. In no event shall the author be liable for any - special, indirect or consequential damages or any damages - whatsoever resulting from loss of use, data or profits, whether - in an action of contract, negligence or other tortious action, - arising out of or in connection with the use or performance of - this software. -*/ - -/** \file - * \brief Master include file for the library USB CDC-ACM Class driver. - * - * Master include file for the library USB CDC Class driver, for both host and device modes, where available. - * - * This file should be included in all user projects making use of this optional class driver, instead of - * including any headers in the USB/ClassDriver/Device, USB/ClassDriver/Host or USB/ClassDriver/Common subdirectories. - */ - -/** \ingroup Group_USBClassDrivers - * \defgroup Group_USBClassCDC CDC-ACM (Virtual Serial) Class Driver - * \brief USB class driver for the USB-IF CDC-ACM (Virtual Serial) class standard. - * - * \section Sec_USBClassCDC_Dependencies Module Source Dependencies - * The following files must be built with any user project that uses this module: - * - LUFA/Drivers/USB/Class/Device/CDCClassDevice.c (Makefile source module name: LUFA_SRC_USBCLASS) - * - LUFA/Drivers/USB/Class/Host/CDCClassHost.c (Makefile source module name: LUFA_SRC_USBCLASS) - * - * \section Sec_USBClassCDC_ModDescription Module Description - * CDC Class Driver module. This module contains an internal implementation of the USB CDC-ACM class Virtual Serial - * Ports, for both Device and Host USB modes. User applications can use this class driver instead of implementing the - * CDC class manually via the low-level LUFA APIs. - * - * This module is designed to simplify the user code by exposing only the required interface needed to interface with - * Hosts or Devices using the USB CDC Class. - * - * @{ - */ - -#ifndef _CDC_CLASS_H_ -#define _CDC_CLASS_H_ -#if defined(USB0) - /* Macros: */ - #define __INCLUDE_FROM_USB_DRIVER - #define __INCLUDE_FROM_CDC_DRIVER - - /* Includes: */ - #include <../Core/USBMode.h> - - #if defined(USB_CAN_BE_DEVICE) - #include - #endif - - #if defined(USB_CAN_BE_HOST) - #include - #endif - -#endif -#endif -/** @} */ - - -#endif /* UC_FAMILY == XMC4 */ diff --git a/cores/usblib/Class/Common/CDCClassCommon.h b/cores/usblib/Class/Common/CDCClassCommon.h deleted file mode 100644 index fc310c26..00000000 --- a/cores/usblib/Class/Common/CDCClassCommon.h +++ /dev/null @@ -1,395 +0,0 @@ -#ifdef XMC4_SERIES - -/* - LUFA Library - Copyright (C) Dean Camera, 2014. - - dean [at] fourwalledcubicle [dot] com - www.lufa-lib.org -*/ - -/* - Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com) - - Permission to use, copy, modify, distribute, and sell this - software and its documentation for any purpose is hereby granted - without fee, provided that the above copyright notice appear in - all copies and that both that the copyright notice and this - permission notice and warranty disclaimer appear in supporting - documentation, and that the name of the author not be used in - advertising or publicity pertaining to distribution of the - software without specific, written prior permission. - - The author disclaims all warranties with regard to this - software, including all implied warranties of merchantability - and fitness. In no event shall the author be liable for any - special, indirect or consequential damages or any damages - whatsoever resulting from loss of use, data or profits, whether - in an action of contract, negligence or other tortious action, - arising out of or in connection with the use or performance of - this software. -*/ - -/** \file - * \brief Common definitions and declarations for the library USB CDC Class driver. - * - * Common definitions and declarations for the library USB CDC Class driver. - * - * \note This file should not be included directly. It is automatically included as needed by the USB module driver - * dispatch header located in LUFA/Drivers/USB.h. - */ - -/** \ingroup Group_USBClassCDC - * \defgroup Group_USBClassCDCCommon Common Class Definitions - * - * \section Sec_USBClassCDCCommon_ModDescription Module Description - * Constants, Types and Enum definitions that are common to both Device and Host modes for the USB - * CDC Class. - * - * @{ - */ - -#ifndef _CDC_CLASS_COMMON_H_ -#define _CDC_CLASS_COMMON_H_ - - /* Includes: */ - #include <../../Core/StdDescriptors.h> - - /* Enable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - extern "C" { - #endif - - /* Preprocessor Checks: */ - #if !defined(__INCLUDE_FROM_CDC_DRIVER) - #error Do not include this file directly. Include LUFA/Drivers/USB.h instead. - #endif - - /* Macros: */ - /** \name Virtual Control Line Masks */ - //@{ - /** Mask for the DTR handshake line for use with the \ref CDC_REQ_SetControlLineState class-specific request - * from the host, to indicate that the DTR line state should be high. - */ - #define CDC_CONTROL_LINE_OUT_DTR (1 << 0) - - /** Mask for the RTS handshake line for use with the \ref CDC_REQ_SetControlLineState class-specific request - * from the host, to indicate that the RTS line state should be high. - */ - #define CDC_CONTROL_LINE_OUT_RTS (1 << 1) - - /** Mask for the DCD handshake line for use with the \ref CDC_NOTIF_SerialState class-specific notification - * from the device to the host, to indicate that the DCD line state is currently high. - */ - #define CDC_CONTROL_LINE_IN_DCD (1 << 0) - - /** Mask for the DSR handshake line for use with the \ref CDC_NOTIF_SerialState class-specific notification - * from the device to the host, to indicate that the DSR line state is currently high. - */ - #define CDC_CONTROL_LINE_IN_DSR (1 << 1) - - /** Mask for the BREAK handshake line for use with the \ref CDC_NOTIF_SerialState class-specific notification - * from the device to the host, to indicate that the BREAK line state is currently high. - */ - #define CDC_CONTROL_LINE_IN_BREAK (1 << 2) - - /** Mask for the RING handshake line for use with the \ref CDC_NOTIF_SerialState class-specific notification - * from the device to the host, to indicate that the RING line state is currently high. - */ - #define CDC_CONTROL_LINE_IN_RING (1 << 3) - - /** Mask for use with the \ref CDC_NOTIF_SerialState class-specific notification from the device to the host, - * to indicate that a framing error has occurred on the virtual serial port. - */ - #define CDC_CONTROL_LINE_IN_FRAMEERROR (1 << 4) - - /** Mask for use with the \ref CDC_NOTIF_SerialState class-specific notification from the device to the host, - * to indicate that a parity error has occurred on the virtual serial port. - */ - #define CDC_CONTROL_LINE_IN_PARITYERROR (1 << 5) - - /** Mask for use with the \ref CDC_NOTIF_SerialState class-specific notification from the device to the host, - * to indicate that a data overrun error has occurred on the virtual serial port. - */ - #define CDC_CONTROL_LINE_IN_OVERRUNERROR (1 << 6) - //@} - - /** Macro to define a CDC class-specific functional descriptor. CDC functional descriptors have a - * uniform structure but variable sized data payloads, thus cannot be represented accurately by - * a single \c typedef \c struct. A macro is used instead so that functional descriptors can be created - * easily by specifying the size of the payload. This allows \c sizeof() to work correctly. - * - * \param[in] DataSize Size in bytes of the CDC functional descriptor's data payload. - */ - #define CDC_FUNCTIONAL_DESCRIPTOR(DataSize) \ - struct \ - { \ - USB_Descriptor_Header_t Header; \ - uint8_t SubType; \ - uint8_t Data[DataSize]; \ - } - - /* Enums: */ - /** Enum for possible Class, Subclass and Protocol values of device and interface descriptors relating to the CDC - * device class. - */ - enum CDC_Descriptor_ClassSubclassProtocol_t - { - CDC_CSCP_CDCClass = 0x02, /**< Descriptor Class value indicating that the device or interface - * belongs to the CDC class. - */ - CDC_CSCP_NoSpecificSubclass = 0x00, /**< Descriptor Subclass value indicating that the device or interface - * belongs to no specific subclass of the CDC class. - */ - CDC_CSCP_ACMSubclass = 0x02, /**< Descriptor Subclass value indicating that the device or interface - * belongs to the Abstract Control Model CDC subclass. - */ - CDC_CSCP_ATCommandProtocol = 0x01, /**< Descriptor Protocol value indicating that the device or interface - * belongs to the AT Command protocol of the CDC class. - */ - CDC_CSCP_NoSpecificProtocol = 0x00, /**< Descriptor Protocol value indicating that the device or interface - * belongs to no specific protocol of the CDC class. - */ - CDC_CSCP_VendorSpecificProtocol = 0xFF, /**< Descriptor Protocol value indicating that the device or interface - * belongs to a vendor-specific protocol of the CDC class. - */ - CDC_CSCP_CDCDataClass = 0x0A, /**< Descriptor Class value indicating that the device or interface - * belongs to the CDC Data class. - */ - CDC_CSCP_NoDataSubclass = 0x00, /**< Descriptor Subclass value indicating that the device or interface - * belongs to no specific subclass of the CDC data class. - */ - CDC_CSCP_NoDataProtocol = 0x00, /**< Descriptor Protocol value indicating that the device or interface - * belongs to no specific protocol of the CDC data class. - */ - }; - - /** Enum for the CDC class specific control requests that can be issued by the USB bus host. */ - enum CDC_ClassRequests_t - { - CDC_REQ_SendEncapsulatedCommand = 0x00, /**< CDC class-specific request to send an encapsulated command to the device. */ - CDC_REQ_GetEncapsulatedResponse = 0x01, /**< CDC class-specific request to retrieve an encapsulated command response from the device. */ - CDC_REQ_SetLineEncoding = 0x20, /**< CDC class-specific request to set the current virtual serial port configuration settings. */ - CDC_REQ_GetLineEncoding = 0x21, /**< CDC class-specific request to get the current virtual serial port configuration settings. */ - CDC_REQ_SetControlLineState = 0x22, /**< CDC class-specific request to set the current virtual serial port handshake line states. */ - CDC_REQ_SendBreak = 0x23, /**< CDC class-specific request to send a break to the receiver via the carrier channel. */ - }; - - /** Enum for the CDC class specific notification requests that can be issued by a CDC device to a host. */ - enum CDC_ClassNotifications_t - { - CDC_NOTIF_SerialState = 0x20, /**< Notification type constant for a change in the virtual serial port - * handshake line states, for use with a \ref USB_Request_Header_t - * notification structure when sent to the host via the CDC notification - * endpoint. - */ - }; - - /** Enum for the CDC class specific interface descriptor subtypes. */ - enum CDC_DescriptorSubtypes_t - { - CDC_DSUBTYPE_CSInterface_Header = 0x00, /**< CDC class-specific Header functional descriptor. */ - CDC_DSUBTYPE_CSInterface_CallManagement = 0x01, /**< CDC class-specific Call Management functional descriptor. */ - CDC_DSUBTYPE_CSInterface_ACM = 0x02, /**< CDC class-specific Abstract Control Model functional descriptor. */ - CDC_DSUBTYPE_CSInterface_DirectLine = 0x03, /**< CDC class-specific Direct Line functional descriptor. */ - CDC_DSUBTYPE_CSInterface_TelephoneRinger = 0x04, /**< CDC class-specific Telephone Ringer functional descriptor. */ - CDC_DSUBTYPE_CSInterface_TelephoneCall = 0x05, /**< CDC class-specific Telephone Call functional descriptor. */ - CDC_DSUBTYPE_CSInterface_Union = 0x06, /**< CDC class-specific Union functional descriptor. */ - CDC_DSUBTYPE_CSInterface_CountrySelection = 0x07, /**< CDC class-specific Country Selection functional descriptor. */ - CDC_DSUBTYPE_CSInterface_TelephoneOpModes = 0x08, /**< CDC class-specific Telephone Operation Modes functional descriptor. */ - CDC_DSUBTYPE_CSInterface_USBTerminal = 0x09, /**< CDC class-specific USB Terminal functional descriptor. */ - CDC_DSUBTYPE_CSInterface_NetworkChannel = 0x0A, /**< CDC class-specific Network Channel functional descriptor. */ - CDC_DSUBTYPE_CSInterface_ProtocolUnit = 0x0B, /**< CDC class-specific Protocol Unit functional descriptor. */ - CDC_DSUBTYPE_CSInterface_ExtensionUnit = 0x0C, /**< CDC class-specific Extension Unit functional descriptor. */ - CDC_DSUBTYPE_CSInterface_MultiChannel = 0x0D, /**< CDC class-specific Multi-Channel Management functional descriptor. */ - CDC_DSUBTYPE_CSInterface_CAPI = 0x0E, /**< CDC class-specific Common ISDN API functional descriptor. */ - CDC_DSUBTYPE_CSInterface_Ethernet = 0x0F, /**< CDC class-specific Ethernet functional descriptor. */ - CDC_DSUBTYPE_CSInterface_ATM = 0x10, /**< CDC class-specific Asynchronous Transfer Mode functional descriptor. */ - }; - - /** Enum for the possible line encoding formats of a virtual serial port. */ - enum CDC_LineEncodingFormats_t - { - CDC_LINEENCODING_OneStopBit = 0, /**< Each frame contains one stop bit. */ - CDC_LINEENCODING_OneAndAHalfStopBits = 1, /**< Each frame contains one and a half stop bits. */ - CDC_LINEENCODING_TwoStopBits = 2, /**< Each frame contains two stop bits. */ - }; - - /** Enum for the possible line encoding parity settings of a virtual serial port. */ - enum CDC_LineEncodingParity_t - { - CDC_PARITY_None = 0, /**< No parity bit mode on each frame. */ - CDC_PARITY_Odd = 1, /**< Odd parity bit mode on each frame. */ - CDC_PARITY_Even = 2, /**< Even parity bit mode on each frame. */ - CDC_PARITY_Mark = 3, /**< Mark parity bit mode on each frame. */ - CDC_PARITY_Space = 4, /**< Space parity bit mode on each frame. */ - }; - - /* Type Defines: */ - /** \brief CDC class-specific Functional Header Descriptor (LUFA naming conventions). - * - * Type define for a CDC class-specific functional header descriptor. This indicates to the host that the device - * contains one or more CDC functional data descriptors, which give the CDC interface's capabilities and configuration. - * See the CDC class specification for more details. - * - * \see \ref USB_CDC_StdDescriptor_FunctionalHeader_t for the version of this type with standard element names. - * - * \note Regardless of CPU architecture, these values should be stored as little endian. - */ - typedef ATTR_IAR_PACKED struct - { - USB_Descriptor_Header_t Header; /**< Regular descriptor header containing the descriptor's type and length. */ - uint8_t Subtype; /**< Sub type value used to distinguish between CDC class-specific descriptors, - * must be \ref CDC_DSUBTYPE_CSInterface_Header. - */ - uint16_t CDCSpecification; /**< Version number of the CDC specification implemented by the device, - * encoded in BCD format. - * - * \see \ref VERSION_BCD() utility macro. - */ - } ATTR_PACKED USB_CDC_Descriptor_FunctionalHeader_t; - - /** \brief CDC class-specific Functional Header Descriptor (USB-IF naming conventions). - * - * Type define for a CDC class-specific functional header descriptor. This indicates to the host that the device - * contains one or more CDC functional data descriptors, which give the CDC interface's capabilities and configuration. - * See the CDC class specification for more details. - * - * \see \ref USB_CDC_Descriptor_FunctionalHeader_t for the version of this type with non-standard LUFA specific - * element names. - * - * \note Regardless of CPU architecture, these values should be stored as little endian. - */ - typedef ATTR_IAR_PACKED struct - { - uint8_t bFunctionLength; /**< Size of the descriptor, in bytes. */ - uint8_t bDescriptorType; /**< Type of the descriptor, either a value in \ref USB_DescriptorTypes_t or a value - * given by the specific class. - */ - uint8_t bDescriptorSubType; /**< Sub type value used to distinguish between CDC class-specific descriptors, - * must be \ref CDC_DSUBTYPE_CSInterface_Header. - */ - uint16_t bcdCDC; /**< Version number of the CDC specification implemented by the device, encoded in BCD format. - * - * \see \ref VERSION_BCD() utility macro. - */ - } ATTR_PACKED USB_CDC_StdDescriptor_FunctionalHeader_t; - - /** \brief CDC class-specific Functional ACM Descriptor (LUFA naming conventions). - * - * Type define for a CDC class-specific functional ACM descriptor. This indicates to the host that the CDC interface - * supports the CDC ACM subclass of the CDC specification. See the CDC class specification for more details. - * - * \see \ref USB_CDC_StdDescriptor_FunctionalACM_t for the version of this type with standard element names. - * - * \note Regardless of CPU architecture, these values should be stored as little endian. - */ - typedef ATTR_IAR_PACKED struct - { - USB_Descriptor_Header_t Header; /**< Regular descriptor header containing the descriptor's type and length. */ - uint8_t Subtype; /**< Sub type value used to distinguish between CDC class-specific descriptors, - * must be \ref CDC_DSUBTYPE_CSInterface_ACM. - */ - uint8_t Capabilities; /**< Capabilities of the ACM interface, given as a bit mask. For most devices, - * this should be set to a fixed value of \c 0x06 - for other capabilities, refer - * to the CDC ACM specification. - */ - } ATTR_PACKED USB_CDC_Descriptor_FunctionalACM_t; - - /** \brief CDC class-specific Functional ACM Descriptor (USB-IF naming conventions). - * - * Type define for a CDC class-specific functional ACM descriptor. This indicates to the host that the CDC interface - * supports the CDC ACM subclass of the CDC specification. See the CDC class specification for more details. - * - * \see \ref USB_CDC_Descriptor_FunctionalACM_t for the version of this type with non-standard LUFA specific - * element names. - * - * \note Regardless of CPU architecture, these values should be stored as little endian. - */ - typedef ATTR_IAR_PACKED struct - { - uint8_t bFunctionLength; /**< Size of the descriptor, in bytes. */ - uint8_t bDescriptorType; /**< Type of the descriptor, either a value in \ref USB_DescriptorTypes_t or a value - * given by the specific class. - */ - uint8_t bDescriptorSubType; /**< Sub type value used to distinguish between CDC class-specific descriptors, - * must be \ref CDC_DSUBTYPE_CSInterface_ACM. - */ - uint8_t bmCapabilities; /**< Capabilities of the ACM interface, given as a bit mask. For most devices, - * this should be set to a fixed value of 0x06 - for other capabilities, refer - * to the CDC ACM specification. - */ - } ATTR_PACKED USB_CDC_StdDescriptor_FunctionalACM_t; - - /** \brief CDC class-specific Functional Union Descriptor (LUFA naming conventions). - * - * Type define for a CDC class-specific functional Union descriptor. This indicates to the host that specific - * CDC control and data interfaces are related. See the CDC class specification for more details. - * - * \see \ref USB_CDC_StdDescriptor_FunctionalUnion_t for the version of this type with standard element names. - * - * \note Regardless of CPU architecture, these values should be stored as little endian. - */ - typedef ATTR_IAR_PACKED struct - { - USB_Descriptor_Header_t Header; /**< Regular descriptor header containing the descriptor's type and length. */ - uint8_t Subtype; /**< Sub type value used to distinguish between CDC class-specific descriptors, - * must be \ref CDC_DSUBTYPE_CSInterface_Union. - */ - uint8_t MasterInterfaceNumber; /**< Interface number of the CDC Control interface. */ - uint8_t SlaveInterfaceNumber; /**< Interface number of the CDC Data interface. */ - } ATTR_PACKED USB_CDC_Descriptor_FunctionalUnion_t; - - /** \brief CDC class-specific Functional Union Descriptor (USB-IF naming conventions). - * - * Type define for a CDC class-specific functional Union descriptor. This indicates to the host that specific - * CDC control and data interfaces are related. See the CDC class specification for more details. - * - * \see \ref USB_CDC_Descriptor_FunctionalUnion_t for the version of this type with non-standard LUFA specific - * element names. - * - * \note Regardless of CPU architecture, these values should be stored as little endian. - */ - typedef ATTR_IAR_PACKED struct - { - uint8_t bFunctionLength; /**< Size of the descriptor, in bytes. */ - uint8_t bDescriptorType; /**< Type of the descriptor, either a value in \ref USB_DescriptorTypes_t or a value - * given by the specific class. - */ - uint8_t bDescriptorSubType; /**< Sub type value used to distinguish between CDC class-specific descriptors, - * must be \ref CDC_DSUBTYPE_CSInterface_Union. - */ - uint8_t bMasterInterface; /**< Interface number of the CDC Control interface. */ - uint8_t bSlaveInterface0; /**< Interface number of the CDC Data interface. */ - } ATTR_PACKED USB_CDC_StdDescriptor_FunctionalUnion_t; - - /** \brief CDC Virtual Serial Port Line Encoding Settings Structure. - * - * Type define for a CDC Line Encoding structure, used to hold the various encoding parameters for a virtual - * serial port. - * - * \note Regardless of CPU architecture, these values should be stored as little endian. - */ - typedef ATTR_IAR_PACKED struct - { - uint32_t BaudRateBPS; /**< Baud rate of the virtual serial port, in bits per second. */ - uint8_t CharFormat; /**< Character format of the virtual serial port, a value from the - * \ref CDC_LineEncodingFormats_t enum. - */ - uint8_t ParityType; /**< Parity setting of the virtual serial port, a value from the - * \ref CDC_LineEncodingParity_t enum. - */ - uint8_t DataBits; /**< Bits of data per character of the virtual serial port. */ - } ATTR_PACKED CDC_LineEncoding_t; - - /* Disable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - } - #endif - -#endif - -/** @} */ - - -#endif /* UC_FAMILY == XMC4 */ diff --git a/cores/usblib/Class/Common/HIDClassCommon.h b/cores/usblib/Class/Common/HIDClassCommon.h deleted file mode 100644 index 45cf2368..00000000 --- a/cores/usblib/Class/Common/HIDClassCommon.h +++ /dev/null @@ -1,686 +0,0 @@ -#ifdef XMC4_SERIES - -/* - LUFA Library - Copyright (C) Dean Camera, 2014. - - dean [at] fourwalledcubicle [dot] com - www.lufa-lib.org -*/ - -/* - Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com) - - Permission to use, copy, modify, distribute, and sell this - software and its documentation for any purpose is hereby granted - without fee, provided that the above copyright notice appear in - all copies and that both that the copyright notice and this - permission notice and warranty disclaimer appear in supporting - documentation, and that the name of the author not be used in - advertising or publicity pertaining to distribution of the - software without specific, written prior permission. - - The author disclaims all warranties with regard to this - software, including all implied warranties of merchantability - and fitness. In no event shall the author be liable for any - special, indirect or consequential damages or any damages - whatsoever resulting from loss of use, data or profits, whether - in an action of contract, negligence or other tortious action, - arising out of or in connection with the use or performance of - this software. -*/ - -/** \file - * \brief Common definitions and declarations for the library USB HID Class driver. - * - * Common definitions and declarations for the library USB HID Class driver. - * - * \note This file should not be included directly. It is automatically included as needed by the USB module driver - * dispatch header located in LUFA/Drivers/USB.h. - */ - -/** \ingroup Group_USBClassHID - * \defgroup Group_USBClassHIDCommon Common Class Definitions - * - * \section Sec_USBClassHIDCommon_ModDescription Module Description - * Constants, Types and Enum definitions that are common to both Device and Host modes for the USB - * HID Class. - * - * @{ - */ - -#ifndef _HID_CLASS_COMMON_H_ -#define _HID_CLASS_COMMON_H_ - - /* Includes: */ - #include <../../Core/StdDescriptors.h> - #include "HIDParser.h" - - /* Enable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - extern "C" { - #endif - - /* Preprocessor Checks: */ - #if !defined(__INCLUDE_FROM_HID_DRIVER) - #error Do not include this file directly. Include LUFA/Drivers/USB.h instead. - #endif - - /* Macros: */ - /** \name Keyboard Standard Report Modifier Masks */ - //@{ - /** Constant for a keyboard report modifier byte, indicating that the keyboard's left control key is currently pressed. */ - #define HID_KEYBOARD_MODIFIER_LEFTCTRL (1 << 0) - - /** Constant for a keyboard report modifier byte, indicating that the keyboard's left shift key is currently pressed. */ - #define HID_KEYBOARD_MODIFIER_LEFTSHIFT (1 << 1) - - /** Constant for a keyboard report modifier byte, indicating that the keyboard's left alt key is currently pressed. */ - #define HID_KEYBOARD_MODIFIER_LEFTALT (1 << 2) - - /** Constant for a keyboard report modifier byte, indicating that the keyboard's left GUI key is currently pressed. */ - #define HID_KEYBOARD_MODIFIER_LEFTGUI (1 << 3) - - /** Constant for a keyboard report modifier byte, indicating that the keyboard's right control key is currently pressed. */ - #define HID_KEYBOARD_MODIFIER_RIGHTCTRL (1 << 4) - - /** Constant for a keyboard report modifier byte, indicating that the keyboard's right shift key is currently pressed. */ - #define HID_KEYBOARD_MODIFIER_RIGHTSHIFT (1 << 5) - - /** Constant for a keyboard report modifier byte, indicating that the keyboard's right alt key is currently pressed. */ - #define HID_KEYBOARD_MODIFIER_RIGHTALT (1 << 6) - - /** Constant for a keyboard report modifier byte, indicating that the keyboard's right GUI key is currently pressed. */ - #define HID_KEYBOARD_MODIFIER_RIGHTGUI (1 << 7) - //@} - - /** \name Keyboard Standard Report LED Masks */ - //@{ - /** Constant for a keyboard output report LED byte, indicating that the host's NUM LOCK mode is currently set. */ - #define HID_KEYBOARD_LED_NUMLOCK (1 << 0) - - /** Constant for a keyboard output report LED byte, indicating that the host's CAPS LOCK mode is currently set. */ - #define HID_KEYBOARD_LED_CAPSLOCK (1 << 1) - - /** Constant for a keyboard output report LED byte, indicating that the host's SCROLL LOCK mode is currently set. */ - #define HID_KEYBOARD_LED_SCROLLLOCK (1 << 2) - - /** Constant for a keyboard output report LED byte, indicating that the host's COMPOSE mode is currently set. */ - #define HID_KEYBOARD_LED_COMPOSE (1 << 3) - - /** Constant for a keyboard output report LED byte, indicating that the host's KANA mode is currently set. */ - #define HID_KEYBOARD_LED_KANA (1 << 4) - //@} - - /** \name Keyboard Standard Report Key Scan-codes */ - //@{ - #define HID_KEYBOARD_SC_ERROR_ROLLOVER 0x01 - #define HID_KEYBOARD_SC_POST_FAIL 0x02 - #define HID_KEYBOARD_SC_ERROR_UNDEFINED 0x03 - #define HID_KEYBOARD_SC_A 0x04 - #define HID_KEYBOARD_SC_B 0x05 - #define HID_KEYBOARD_SC_C 0x06 - #define HID_KEYBOARD_SC_D 0x07 - #define HID_KEYBOARD_SC_E 0x08 - #define HID_KEYBOARD_SC_F 0x09 - #define HID_KEYBOARD_SC_G 0x0A - #define HID_KEYBOARD_SC_H 0x0B - #define HID_KEYBOARD_SC_I 0x0C - #define HID_KEYBOARD_SC_J 0x0D - #define HID_KEYBOARD_SC_K 0x0E - #define HID_KEYBOARD_SC_L 0x0F - #define HID_KEYBOARD_SC_M 0x10 - #define HID_KEYBOARD_SC_N 0x11 - #define HID_KEYBOARD_SC_O 0x12 - #define HID_KEYBOARD_SC_P 0x13 - #define HID_KEYBOARD_SC_Q 0x14 - #define HID_KEYBOARD_SC_R 0x15 - #define HID_KEYBOARD_SC_S 0x16 - #define HID_KEYBOARD_SC_T 0x17 - #define HID_KEYBOARD_SC_U 0x18 - #define HID_KEYBOARD_SC_V 0x19 - #define HID_KEYBOARD_SC_W 0x1A - #define HID_KEYBOARD_SC_X 0x1B - #define HID_KEYBOARD_SC_Y 0x1C - #define HID_KEYBOARD_SC_Z 0x1D - #define HID_KEYBOARD_SC_1_AND_EXCLAMATION 0x1E - #define HID_KEYBOARD_SC_2_AND_AT 0x1F - #define HID_KEYBOARD_SC_3_AND_HASHMARK 0x20 - #define HID_KEYBOARD_SC_4_AND_DOLLAR 0x21 - #define HID_KEYBOARD_SC_5_AND_PERCENTAGE 0x22 - #define HID_KEYBOARD_SC_6_AND_CARET 0x23 - #define HID_KEYBOARD_SC_7_AND_AMPERSAND 0x24 - #define HID_KEYBOARD_SC_8_AND_ASTERISK 0x25 - #define HID_KEYBOARD_SC_9_AND_OPENING_PARENTHESIS 0x26 - #define HID_KEYBOARD_SC_0_AND_CLOSING_PARENTHESIS 0x27 - #define HID_KEYBOARD_SC_ENTER 0x28 - #define HID_KEYBOARD_SC_ESCAPE 0x29 - #define HID_KEYBOARD_SC_BACKSPACE 0x2A - #define HID_KEYBOARD_SC_TAB 0x2B - #define HID_KEYBOARD_SC_SPACE 0x2C - #define HID_KEYBOARD_SC_MINUS_AND_UNDERSCORE 0x2D - #define HID_KEYBOARD_SC_EQUAL_AND_PLUS 0x2E - #define HID_KEYBOARD_SC_OPENING_BRACKET_AND_OPENING_BRACE 0x2F - #define HID_KEYBOARD_SC_CLOSING_BRACKET_AND_CLOSING_BRACE 0x30 - #define HID_KEYBOARD_SC_BACKSLASH_AND_PIPE 0x31 - #define HID_KEYBOARD_SC_NON_US_HASHMARK_AND_TILDE 0x32 - #define HID_KEYBOARD_SC_SEMICOLON_AND_COLON 0x33 - #define HID_KEYBOARD_SC_APOSTROPHE_AND_QUOTE 0x34 - #define HID_KEYBOARD_SC_GRAVE_ACCENT_AND_TILDE 0x35 - #define HID_KEYBOARD_SC_COMMA_AND_LESS_THAN_SIGN 0x36 - #define HID_KEYBOARD_SC_DOT_AND_GREATER_THAN_SIGN 0x37 - #define HID_KEYBOARD_SC_SLASH_AND_QUESTION_MARK 0x38 - #define HID_KEYBOARD_SC_CAPS_LOCK 0x39 - #define HID_KEYBOARD_SC_F1 0x3A - #define HID_KEYBOARD_SC_F2 0x3B - #define HID_KEYBOARD_SC_F3 0x3C - #define HID_KEYBOARD_SC_F4 0x3D - #define HID_KEYBOARD_SC_F5 0x3E - #define HID_KEYBOARD_SC_F6 0x3F - #define HID_KEYBOARD_SC_F7 0x40 - #define HID_KEYBOARD_SC_F8 0x41 - #define HID_KEYBOARD_SC_F9 0x42 - #define HID_KEYBOARD_SC_F10 0x43 - #define HID_KEYBOARD_SC_F11 0x44 - #define HID_KEYBOARD_SC_F12 0x45 - #define HID_KEYBOARD_SC_PRINT_SCREEN 0x46 - #define HID_KEYBOARD_SC_SCROLL_LOCK 0x47 - #define HID_KEYBOARD_SC_PAUSE 0x48 - #define HID_KEYBOARD_SC_INSERT 0x49 - #define HID_KEYBOARD_SC_HOME 0x4A - #define HID_KEYBOARD_SC_PAGE_UP 0x4B - #define HID_KEYBOARD_SC_DELETE 0x4C - #define HID_KEYBOARD_SC_END 0x4D - #define HID_KEYBOARD_SC_PAGE_DOWN 0x4E - #define HID_KEYBOARD_SC_RIGHT_ARROW 0x4F - #define HID_KEYBOARD_SC_LEFT_ARROW 0x50 - #define HID_KEYBOARD_SC_DOWN_ARROW 0x51 - #define HID_KEYBOARD_SC_UP_ARROW 0x52 - #define HID_KEYBOARD_SC_NUM_LOCK 0x53 - #define HID_KEYBOARD_SC_KEYPAD_SLASH 0x54 - #define HID_KEYBOARD_SC_KEYPAD_ASTERISK 0x55 - #define HID_KEYBOARD_SC_KEYPAD_MINUS 0x56 - #define HID_KEYBOARD_SC_KEYPAD_PLUS 0x57 - #define HID_KEYBOARD_SC_KEYPAD_ENTER 0x58 - #define HID_KEYBOARD_SC_KEYPAD_1_AND_END 0x59 - #define HID_KEYBOARD_SC_KEYPAD_2_AND_DOWN_ARROW 0x5A - #define HID_KEYBOARD_SC_KEYPAD_3_AND_PAGE_DOWN 0x5B - #define HID_KEYBOARD_SC_KEYPAD_4_AND_LEFT_ARROW 0x5C - #define HID_KEYBOARD_SC_KEYPAD_5 0x5D - #define HID_KEYBOARD_SC_KEYPAD_6_AND_RIGHT_ARROW 0x5E - #define HID_KEYBOARD_SC_KEYPAD_7_AND_HOME 0x5F - #define HID_KEYBOARD_SC_KEYPAD_8_AND_UP_ARROW 0x60 - #define HID_KEYBOARD_SC_KEYPAD_9_AND_PAGE_UP 0x61 - #define HID_KEYBOARD_SC_KEYPAD_0_AND_INSERT 0x62 - #define HID_KEYBOARD_SC_KEYPAD_DOT_AND_DELETE 0x63 - #define HID_KEYBOARD_SC_NON_US_BACKSLASH_AND_PIPE 0x64 - #define HID_KEYBOARD_SC_APPLICATION 0x65 - #define HID_KEYBOARD_SC_POWER 0x66 - #define HID_KEYBOARD_SC_KEYPAD_EQUAL_SIGN 0x67 - #define HID_KEYBOARD_SC_F13 0x68 - #define HID_KEYBOARD_SC_F14 0x69 - #define HID_KEYBOARD_SC_F15 0x6A - #define HID_KEYBOARD_SC_F16 0x6B - #define HID_KEYBOARD_SC_F17 0x6C - #define HID_KEYBOARD_SC_F18 0x6D - #define HID_KEYBOARD_SC_F19 0x6E - #define HID_KEYBOARD_SC_F20 0x6F - #define HID_KEYBOARD_SC_F21 0x70 - #define HID_KEYBOARD_SC_F22 0x71 - #define HID_KEYBOARD_SC_F23 0x72 - #define HID_KEYBOARD_SC_F24 0x73 - #define HID_KEYBOARD_SC_EXECUTE 0x74 - #define HID_KEYBOARD_SC_HELP 0x75 - #define HID_KEYBOARD_SC_MENU 0x76 - #define HID_KEYBOARD_SC_SELECT 0x77 - #define HID_KEYBOARD_SC_STOP 0x78 - #define HID_KEYBOARD_SC_AGAIN 0x79 - #define HID_KEYBOARD_SC_UNDO 0x7A - #define HID_KEYBOARD_SC_CUT 0x7B - #define HID_KEYBOARD_SC_COPY 0x7C - #define HID_KEYBOARD_SC_PASTE 0x7D - #define HID_KEYBOARD_SC_FIND 0x7E - #define HID_KEYBOARD_SC_MUTE 0x7F - #define HID_KEYBOARD_SC_VOLUME_UP 0x80 - #define HID_KEYBOARD_SC_VOLUME_DOWN 0x81 - #define HID_KEYBOARD_SC_LOCKING_CAPS_LOCK 0x82 - #define HID_KEYBOARD_SC_LOCKING_NUM_LOCK 0x83 - #define HID_KEYBOARD_SC_LOCKING_SCROLL_LOCK 0x84 - #define HID_KEYBOARD_SC_KEYPAD_COMMA 0x85 - #define HID_KEYBOARD_SC_KEYPAD_EQUAL_SIGN_AS400 0x86 - #define HID_KEYBOARD_SC_INTERNATIONAL1 0x87 - #define HID_KEYBOARD_SC_INTERNATIONAL2 0x88 - #define HID_KEYBOARD_SC_INTERNATIONAL3 0x89 - #define HID_KEYBOARD_SC_INTERNATIONAL4 0x8A - #define HID_KEYBOARD_SC_INTERNATIONAL5 0x8B - #define HID_KEYBOARD_SC_INTERNATIONAL6 0x8C - #define HID_KEYBOARD_SC_INTERNATIONAL7 0x8D - #define HID_KEYBOARD_SC_INTERNATIONAL8 0x8E - #define HID_KEYBOARD_SC_INTERNATIONAL9 0x8F - #define HID_KEYBOARD_SC_LANG1 0x90 - #define HID_KEYBOARD_SC_LANG2 0x91 - #define HID_KEYBOARD_SC_LANG3 0x92 - #define HID_KEYBOARD_SC_LANG4 0x93 - #define HID_KEYBOARD_SC_LANG5 0x94 - #define HID_KEYBOARD_SC_LANG6 0x95 - #define HID_KEYBOARD_SC_LANG7 0x96 - #define HID_KEYBOARD_SC_LANG8 0x97 - #define HID_KEYBOARD_SC_LANG9 0x98 - #define HID_KEYBOARD_SC_ALTERNATE_ERASE 0x99 - #define HID_KEYBOARD_SC_SYSREQ 0x9A - #define HID_KEYBOARD_SC_CANCEL 0x9B - #define HID_KEYBOARD_SC_CLEAR 0x9C - #define HID_KEYBOARD_SC_PRIOR 0x9D - #define HID_KEYBOARD_SC_RETURN 0x9E - #define HID_KEYBOARD_SC_SEPARATOR 0x9F - #define HID_KEYBOARD_SC_OUT 0xA0 - #define HID_KEYBOARD_SC_OPER 0xA1 - #define HID_KEYBOARD_SC_CLEAR_AND_AGAIN 0xA2 - #define HID_KEYBOARD_SC_CRSEL_AND_PROPS 0xA3 - #define HID_KEYBOARD_SC_EXSEL 0xA4 - #define HID_KEYBOARD_SC_KEYPAD_00 0xB0 - #define HID_KEYBOARD_SC_KEYPAD_000 0xB1 - #define HID_KEYBOARD_SC_THOUSANDS_SEPARATOR 0xB2 - #define HID_KEYBOARD_SC_DECIMAL_SEPARATOR 0xB3 - #define HID_KEYBOARD_SC_CURRENCY_UNIT 0xB4 - #define HID_KEYBOARD_SC_CURRENCY_SUB_UNIT 0xB5 - #define HID_KEYBOARD_SC_KEYPAD_OPENING_PARENTHESIS 0xB6 - #define HID_KEYBOARD_SC_KEYPAD_CLOSING_PARENTHESIS 0xB7 - #define HID_KEYBOARD_SC_KEYPAD_OPENING_BRACE 0xB8 - #define HID_KEYBOARD_SC_KEYPAD_CLOSING_BRACE 0xB9 - #define HID_KEYBOARD_SC_KEYPAD_TAB 0xBA - #define HID_KEYBOARD_SC_KEYPAD_BACKSPACE 0xBB - #define HID_KEYBOARD_SC_KEYPAD_A 0xBC - #define HID_KEYBOARD_SC_KEYPAD_B 0xBD - #define HID_KEYBOARD_SC_KEYPAD_C 0xBE - #define HID_KEYBOARD_SC_KEYPAD_D 0xBF - #define HID_KEYBOARD_SC_KEYPAD_E 0xC0 - #define HID_KEYBOARD_SC_KEYPAD_F 0xC1 - #define HID_KEYBOARD_SC_KEYPAD_XOR 0xC2 - #define HID_KEYBOARD_SC_KEYPAD_CARET 0xC3 - #define HID_KEYBOARD_SC_KEYPAD_PERCENTAGE 0xC4 - #define HID_KEYBOARD_SC_KEYPAD_LESS_THAN_SIGN 0xC5 - #define HID_KEYBOARD_SC_KEYPAD_GREATER_THAN_SIGN 0xC6 - #define HID_KEYBOARD_SC_KEYPAD_AMP 0xC7 - #define HID_KEYBOARD_SC_KEYPAD_AMP_AMP 0xC8 - #define HID_KEYBOARD_SC_KEYPAD_PIPE 0xC9 - #define HID_KEYBOARD_SC_KEYPAD_PIPE_PIPE 0xCA - #define HID_KEYBOARD_SC_KEYPAD_COLON 0xCB - #define HID_KEYBOARD_SC_KEYPAD_HASHMARK 0xCC - #define HID_KEYBOARD_SC_KEYPAD_SPACE 0xCD - #define HID_KEYBOARD_SC_KEYPAD_AT 0xCE - #define HID_KEYBOARD_SC_KEYPAD_EXCLAMATION_SIGN 0xCF - #define HID_KEYBOARD_SC_KEYPAD_MEMORY_STORE 0xD0 - #define HID_KEYBOARD_SC_KEYPAD_MEMORY_RECALL 0xD1 - #define HID_KEYBOARD_SC_KEYPAD_MEMORY_CLEAR 0xD2 - #define HID_KEYBOARD_SC_KEYPAD_MEMORY_ADD 0xD3 - #define HID_KEYBOARD_SC_KEYPAD_MEMORY_SUBTRACT 0xD4 - #define HID_KEYBOARD_SC_KEYPAD_MEMORY_MULTIPLY 0xD5 - #define HID_KEYBOARD_SC_KEYPAD_MEMORY_DIVIDE 0xD6 - #define HID_KEYBOARD_SC_KEYPAD_PLUS_AND_MINUS 0xD7 - #define HID_KEYBOARD_SC_KEYPAD_CLEAR 0xD8 - #define HID_KEYBOARD_SC_KEYPAD_CLEAR_ENTRY 0xD9 - #define HID_KEYBOARD_SC_KEYPAD_BINARY 0xDA - #define HID_KEYBOARD_SC_KEYPAD_OCTAL 0xDB - #define HID_KEYBOARD_SC_KEYPAD_DECIMAL 0xDC - #define HID_KEYBOARD_SC_KEYPAD_HEXADECIMAL 0xDD - #define HID_KEYBOARD_SC_LEFT_CONTROL 0xE0 - #define HID_KEYBOARD_SC_LEFT_SHIFT 0xE1 - #define HID_KEYBOARD_SC_LEFT_ALT 0xE2 - #define HID_KEYBOARD_SC_LEFT_GUI 0xE3 - #define HID_KEYBOARD_SC_RIGHT_CONTROL 0xE4 - #define HID_KEYBOARD_SC_RIGHT_SHIFT 0xE5 - #define HID_KEYBOARD_SC_RIGHT_ALT 0xE6 - #define HID_KEYBOARD_SC_RIGHT_GUI 0xE7 - #define HID_KEYBOARD_SC_MEDIA_PLAY 0xE8 - #define HID_KEYBOARD_SC_MEDIA_STOP 0xE9 - #define HID_KEYBOARD_SC_MEDIA_PREVIOUS_TRACK 0xEA - #define HID_KEYBOARD_SC_MEDIA_NEXT_TRACK 0xEB - #define HID_KEYBOARD_SC_MEDIA_EJECT 0xEC - #define HID_KEYBOARD_SC_MEDIA_VOLUME_UP 0xED - #define HID_KEYBOARD_SC_MEDIA_VOLUME_DOWN 0xEE - #define HID_KEYBOARD_SC_MEDIA_MUTE 0xEF - #define HID_KEYBOARD_SC_MEDIA_WWW 0xF0 - #define HID_KEYBOARD_SC_MEDIA_BACKWARD 0xF1 - #define HID_KEYBOARD_SC_MEDIA_FORWARD 0xF2 - #define HID_KEYBOARD_SC_MEDIA_CANCEL 0xF3 - #define HID_KEYBOARD_SC_MEDIA_SEARCH 0xF4 - #define HID_KEYBOARD_SC_MEDIA_SLEEP 0xF8 - #define HID_KEYBOARD_SC_MEDIA_LOCK 0xF9 - #define HID_KEYBOARD_SC_MEDIA_RELOAD 0xFA - #define HID_KEYBOARD_SC_MEDIA_CALCULATOR 0xFB - //@} - - /** \name Common HID Device Report Descriptors */ - //@{ - /** \hideinitializer - * A list of HID report item array elements that describe a typical HID USB Joystick. The resulting report - * descriptor is structured according to the following layout: - * - * \code - * struct - * { - * intA_t X; // Signed X axis value - * intA_t Y; // Signed Y axis value - * intA_t Z; // Signed Z axis value - * uintB_t Buttons; // Pressed buttons bitmask - * } Joystick_Report; - * \endcode - * - * Where \c uintA_t is a type large enough to hold the ranges of the signed \c MinAxisVal and \c MaxAxisVal values, - * and \c intB_t is a type large enough to hold one bit per button. - * - * \param[in] MinAxisVal Minimum logical axis value (16-bit). - * \param[in] MaxAxisVal Maximum logical axis value (16-bit). - * \param[in] MinPhysicalVal Minimum physical axis value, for movement resolution calculations (16-bit). - * \param[in] MaxPhysicalVal Maximum physical axis value, for movement resolution calculations (16-bit). - * \param[in] Buttons Total number of buttons in the device (8-bit). - */ - #define HID_DESCRIPTOR_JOYSTICK(MinAxisVal, MaxAxisVal, MinPhysicalVal, MaxPhysicalVal, Buttons) \ - HID_RI_USAGE_PAGE(8, 0x01), \ - HID_RI_USAGE(8, 0x04), \ - HID_RI_COLLECTION(8, 0x01), \ - HID_RI_USAGE(8, 0x01), \ - HID_RI_COLLECTION(8, 0x00), \ - HID_RI_USAGE(8, 0x30), \ - HID_RI_USAGE(8, 0x31), \ - HID_RI_USAGE(8, 0x32), \ - HID_RI_LOGICAL_MINIMUM(16, MinAxisVal), \ - HID_RI_LOGICAL_MAXIMUM(16, MaxAxisVal), \ - HID_RI_PHYSICAL_MINIMUM(16, MinPhysicalVal), \ - HID_RI_PHYSICAL_MAXIMUM(16, MaxPhysicalVal), \ - HID_RI_REPORT_COUNT(8, 3), \ - HID_RI_REPORT_SIZE(8, (((MinAxisVal >= -128) && (MaxAxisVal <= 127)) ? 8 : 16)), \ - HID_RI_INPUT(8, HID_IOF_DATA | HID_IOF_VARIABLE | HID_IOF_ABSOLUTE), \ - HID_RI_END_COLLECTION(0), \ - HID_RI_USAGE_PAGE(8, 0x09), \ - HID_RI_USAGE_MINIMUM(8, 0x01), \ - HID_RI_USAGE_MAXIMUM(8, Buttons), \ - HID_RI_LOGICAL_MINIMUM(8, 0x00), \ - HID_RI_LOGICAL_MAXIMUM(8, 0x01), \ - HID_RI_REPORT_SIZE(8, 0x01), \ - HID_RI_REPORT_COUNT(8, Buttons), \ - HID_RI_INPUT(8, HID_IOF_DATA | HID_IOF_VARIABLE | HID_IOF_ABSOLUTE), \ - HID_RI_REPORT_SIZE(8, (Buttons % 8) ? (8 - (Buttons % 8)) : 0), \ - HID_RI_REPORT_COUNT(8, 0x01), \ - HID_RI_INPUT(8, HID_IOF_CONSTANT), \ - HID_RI_END_COLLECTION(0) - - /** \hideinitializer - * A list of HID report item array elements that describe a typical HID USB keyboard. The resulting report descriptor - * is compatible with \ref USB_KeyboardReport_Data_t when \c MaxKeys is equal to 6. For other values, the report will - * be structured according to the following layout: - * - * \code - * struct - * { - * uint8_t Modifier; // Keyboard modifier byte indicating pressed modifier keys (\c HID_KEYBOARD_MODIFER_* masks) - * uint8_t Reserved; // Reserved for OEM use, always set to 0. - * uint8_t KeyCode[MaxKeys]; // Length determined by the number of keys that can be reported - * } Keyboard_Report; - * \endcode - * - * \param[in] MaxKeys Number of simultaneous keys that can be reported at the one time (8-bit). - */ - #define HID_DESCRIPTOR_KEYBOARD(MaxKeys) \ - HID_RI_USAGE_PAGE(8, 0x01), \ - HID_RI_USAGE(8, 0x06), \ - HID_RI_COLLECTION(8, 0x01), \ - HID_RI_USAGE_PAGE(8, 0x07), \ - HID_RI_USAGE_MINIMUM(8, 0xE0), \ - HID_RI_USAGE_MAXIMUM(8, 0xE7), \ - HID_RI_LOGICAL_MINIMUM(8, 0x00), \ - HID_RI_LOGICAL_MAXIMUM(8, 0x01), \ - HID_RI_REPORT_SIZE(8, 0x01), \ - HID_RI_REPORT_COUNT(8, 0x08), \ - HID_RI_INPUT(8, HID_IOF_DATA | HID_IOF_VARIABLE | HID_IOF_ABSOLUTE), \ - HID_RI_REPORT_COUNT(8, 0x01), \ - HID_RI_REPORT_SIZE(8, 0x08), \ - HID_RI_INPUT(8, HID_IOF_CONSTANT), \ - HID_RI_USAGE_PAGE(8, 0x08), \ - HID_RI_USAGE_MINIMUM(8, 0x01), \ - HID_RI_USAGE_MAXIMUM(8, 0x05), \ - HID_RI_REPORT_COUNT(8, 0x05), \ - HID_RI_REPORT_SIZE(8, 0x01), \ - HID_RI_OUTPUT(8, HID_IOF_DATA | HID_IOF_VARIABLE | HID_IOF_ABSOLUTE | HID_IOF_NON_VOLATILE), \ - HID_RI_REPORT_COUNT(8, 0x01), \ - HID_RI_REPORT_SIZE(8, 0x03), \ - HID_RI_OUTPUT(8, HID_IOF_CONSTANT), \ - HID_RI_LOGICAL_MINIMUM(8, 0x00), \ - HID_RI_LOGICAL_MAXIMUM(8, 0xFF), \ - HID_RI_USAGE_PAGE(8, 0x07), \ - HID_RI_USAGE_MINIMUM(8, 0x00), \ - HID_RI_USAGE_MAXIMUM(8, 0xFF), \ - HID_RI_REPORT_COUNT(8, MaxKeys), \ - HID_RI_REPORT_SIZE(8, 0x08), \ - HID_RI_INPUT(8, HID_IOF_DATA | HID_IOF_ARRAY | HID_IOF_ABSOLUTE), \ - HID_RI_END_COLLECTION(0) - - /** \hideinitializer - * A list of HID report item array elements that describe a typical HID USB mouse. The resulting report descriptor - * is compatible with \ref USB_MouseReport_Data_t if the \c MinAxisVal and \c MaxAxisVal values fit within a \c int8_t range - * and the number of Buttons is less than 8. For other values, the report is structured according to the following layout: - * - * \code - * struct - * { - * uintA_t Buttons; // Pressed buttons bitmask - * intB_t X; // X axis value - * intB_t Y; // Y axis value - * } Mouse_Report; - * \endcode - * - * Where \c intA_t is a type large enough to hold one bit per button, and \c intB_t is a type large enough to hold the - * ranges of the signed \c MinAxisVal and \c MaxAxisVal values. - * - * \param[in] MinAxisVal Minimum X/Y logical axis value (16-bit). - * \param[in] MaxAxisVal Maximum X/Y logical axis value (16-bit). - * \param[in] MinPhysicalVal Minimum X/Y physical axis value, for movement resolution calculations (16-bit). - * \param[in] MaxPhysicalVal Maximum X/Y physical axis value, for movement resolution calculations (16-bit). - * \param[in] Buttons Total number of buttons in the device (8-bit). - * \param[in] AbsoluteCoords Boolean \c true to use absolute X/Y coordinates (e.g. touchscreen). - */ - #define HID_DESCRIPTOR_MOUSE(MinAxisVal, MaxAxisVal, MinPhysicalVal, MaxPhysicalVal, Buttons, AbsoluteCoords) \ - HID_RI_USAGE_PAGE(8, 0x01), \ - HID_RI_USAGE(8, 0x02), \ - HID_RI_COLLECTION(8, 0x01), \ - HID_RI_USAGE(8, 0x01), \ - HID_RI_COLLECTION(8, 0x00), \ - HID_RI_USAGE_PAGE(8, 0x09), \ - HID_RI_USAGE_MINIMUM(8, 0x01), \ - HID_RI_USAGE_MAXIMUM(8, Buttons), \ - HID_RI_LOGICAL_MINIMUM(8, 0x00), \ - HID_RI_LOGICAL_MAXIMUM(8, 0x01), \ - HID_RI_REPORT_COUNT(8, Buttons), \ - HID_RI_REPORT_SIZE(8, 0x01), \ - HID_RI_INPUT(8, HID_IOF_DATA | HID_IOF_VARIABLE | HID_IOF_ABSOLUTE), \ - HID_RI_REPORT_COUNT(8, 0x01), \ - HID_RI_REPORT_SIZE(8, (Buttons % 8) ? (8 - (Buttons % 8)) : 0), \ - HID_RI_INPUT(8, HID_IOF_CONSTANT), \ - HID_RI_USAGE_PAGE(8, 0x01), \ - HID_RI_USAGE(8, 0x30), \ - HID_RI_USAGE(8, 0x31), \ - HID_RI_LOGICAL_MINIMUM(16, MinAxisVal), \ - HID_RI_LOGICAL_MAXIMUM(16, MaxAxisVal), \ - HID_RI_PHYSICAL_MINIMUM(16, MinPhysicalVal), \ - HID_RI_PHYSICAL_MAXIMUM(16, MaxPhysicalVal), \ - HID_RI_REPORT_COUNT(8, 0x02), \ - HID_RI_REPORT_SIZE(8, (((MinAxisVal >= -128) && (MaxAxisVal <= 127)) ? 8 : 16)), \ - HID_RI_INPUT(8, HID_IOF_DATA | HID_IOF_VARIABLE | (AbsoluteCoords ? HID_IOF_ABSOLUTE : HID_IOF_RELATIVE)), \ - HID_RI_END_COLLECTION(0), \ - HID_RI_END_COLLECTION(0) - - /** \hideinitializer - * A list of HID report item array elements that describe a typical Vendor Defined byte array HID report descriptor, - * used for transporting arbitrary data between the USB host and device via HID reports. The resulting report should be - * a \c uint8_t byte array of the specified length in both Device to Host (IN) and Host to Device (OUT) directions. - * - * \param[in] VendorPageNum Vendor Defined HID Usage Page index, ranging from 0x00 to 0xFF. - * \param[in] CollectionUsage Vendor Usage for the encompassing report IN and OUT collection, ranging from 0x00 to 0xFF. - * \param[in] DataINUsage Vendor Usage for the IN report data, ranging from 0x00 to 0xFF. - * \param[in] DataOUTUsage Vendor Usage for the OUT report data, ranging from 0x00 to 0xFF. - * \param[in] NumBytes Length of the data IN and OUT reports. - */ - #define HID_DESCRIPTOR_VENDOR(VendorPageNum, CollectionUsage, DataINUsage, DataOUTUsage, NumBytes) \ - HID_RI_USAGE_PAGE(16, (0xFF00 | VendorPageNum)), \ - HID_RI_USAGE(8, CollectionUsage), \ - HID_RI_COLLECTION(8, 0x01), \ - HID_RI_USAGE(8, DataINUsage), \ - HID_RI_LOGICAL_MINIMUM(8, 0x00), \ - HID_RI_LOGICAL_MAXIMUM(8, 0xFF), \ - HID_RI_REPORT_SIZE(8, 0x08), \ - HID_RI_REPORT_COUNT(8, NumBytes), \ - HID_RI_INPUT(8, HID_IOF_DATA | HID_IOF_VARIABLE | HID_IOF_ABSOLUTE), \ - HID_RI_USAGE(8, DataOUTUsage), \ - HID_RI_LOGICAL_MINIMUM(8, 0x00), \ - HID_RI_LOGICAL_MAXIMUM(8, 0xFF), \ - HID_RI_REPORT_SIZE(8, 0x08), \ - HID_RI_REPORT_COUNT(8, NumBytes), \ - HID_RI_OUTPUT(8, HID_IOF_DATA | HID_IOF_VARIABLE | HID_IOF_ABSOLUTE | HID_IOF_NON_VOLATILE), \ - HID_RI_END_COLLECTION(0) - //@} - - /* Type Defines: */ - /** Enum for possible Class, Subclass and Protocol values of device and interface descriptors relating to the HID - * device class. - */ - enum HID_Descriptor_ClassSubclassProtocol_t - { - HID_CSCP_HIDClass = 0x03, /**< Descriptor Class value indicating that the device or interface - * belongs to the HID class. - */ - HID_CSCP_NonBootSubclass = 0x00, /**< Descriptor Subclass value indicating that the device or interface - * does not implement a HID boot protocol. - */ - HID_CSCP_BootSubclass = 0x01, /**< Descriptor Subclass value indicating that the device or interface - * implements a HID boot protocol. - */ - HID_CSCP_NonBootProtocol = 0x00, /**< Descriptor Protocol value indicating that the device or interface - * does not belong to a HID boot protocol. - */ - HID_CSCP_KeyboardBootProtocol = 0x01, /**< Descriptor Protocol value indicating that the device or interface - * belongs to the Keyboard HID boot protocol. - */ - HID_CSCP_MouseBootProtocol = 0x02, /**< Descriptor Protocol value indicating that the device or interface - * belongs to the Mouse HID boot protocol. - */ - }; - - /** Enum for the HID class specific control requests that can be issued by the USB bus host. */ - enum HID_ClassRequests_t - { - HID_REQ_GetReport = 0x01, /**< HID class-specific Request to get the current HID report from the device. */ - HID_REQ_GetIdle = 0x02, /**< HID class-specific Request to get the current device idle count. */ - HID_REQ_GetProtocol = 0x03, /**< HID class-specific Request to get the current HID report protocol mode. */ - HID_REQ_SetReport = 0x09, /**< HID class-specific Request to set the current HID report to the device. */ - HID_REQ_SetIdle = 0x0A, /**< HID class-specific Request to set the device's idle count. */ - HID_REQ_SetProtocol = 0x0B, /**< HID class-specific Request to set the current HID report protocol mode. */ - }; - - /** Enum for the HID class specific descriptor types. */ - enum HID_DescriptorTypes_t - { - HID_DTYPE_HID = 0x21, /**< Descriptor header type value, to indicate a HID class HID descriptor. */ - HID_DTYPE_Report = 0x22, /**< Descriptor header type value, to indicate a HID class HID report descriptor. */ - }; - - /** Enum for the different types of HID reports. */ - enum HID_ReportItemTypes_t - { - HID_REPORT_ITEM_In = 0, /**< Indicates that the item is an IN report type. */ - HID_REPORT_ITEM_Out = 1, /**< Indicates that the item is an OUT report type. */ - HID_REPORT_ITEM_Feature = 2, /**< Indicates that the item is a FEATURE report type. */ - }; - - /** \brief HID class-specific HID Descriptor (LUFA naming conventions). - * - * Type define for the HID class-specific HID descriptor, to describe the HID device's specifications. Refer to the HID - * specification for details on the structure elements. - * - * \see \ref USB_HID_StdDescriptor_HID_t for the version of this type with standard element names. - * - * \note Regardless of CPU architecture, these values should be stored as little endian. - */ - typedef ATTR_IAR_PACKED struct - { - USB_Descriptor_Header_t Header; /**< Regular descriptor header containing the descriptor's type and length. */ - - uint16_t HIDSpec; /**< BCD encoded version that the HID descriptor and device complies to. - * - * \see \ref VERSION_BCD() utility macro. - */ - uint8_t CountryCode; /**< Country code of the localized device, or zero if universal. */ - - uint8_t TotalReportDescriptors; /**< Total number of HID report descriptors for the interface. */ - - uint8_t HIDReportType; /**< Type of HID report, set to \ref HID_DTYPE_Report. */ - uint16_t HIDReportLength; /**< Length of the associated HID report descriptor, in bytes. */ - } ATTR_PACKED USB_HID_Descriptor_HID_t; - - /** \brief HID class-specific HID Descriptor (USB-IF naming conventions). - * - * Type define for the HID class-specific HID descriptor, to describe the HID device's specifications. Refer to the HID - * specification for details on the structure elements. - * - * \see \ref USB_HID_Descriptor_HID_t for the version of this type with non-standard LUFA specific - * element names. - * - * \note Regardless of CPU architecture, these values should be stored as little endian. - */ - typedef ATTR_IAR_PACKED struct - { - uint8_t bLength; /**< Size of the descriptor, in bytes. */ - uint8_t bDescriptorType; /**< Type of the descriptor, either a value in \ref USB_DescriptorTypes_t or a value - * given by the specific class. - */ - - uint16_t bcdHID; /**< BCD encoded version that the HID descriptor and device complies to. - * - * \see \ref VERSION_BCD() utility macro. - */ - uint8_t bCountryCode; /**< Country code of the localized device, or zero if universal. */ - - uint8_t bNumDescriptors; /**< Total number of HID report descriptors for the interface. */ - - uint8_t bDescriptorType2; /**< Type of HID report, set to \ref HID_DTYPE_Report. */ - uint16_t wDescriptorLength; /**< Length of the associated HID report descriptor, in bytes. */ - } ATTR_PACKED USB_HID_StdDescriptor_HID_t; - - /** \brief Standard HID Boot Protocol Mouse Report. - * - * Type define for a standard Boot Protocol Mouse report - */ - typedef ATTR_IAR_PACKED struct - { - uint8_t Button; /**< Button mask for currently pressed buttons in the mouse. */ - int8_t X; /**< Current delta X movement of the mouse. */ - int8_t Y; /**< Current delta Y movement on the mouse. */ - } ATTR_PACKED USB_MouseReport_Data_t; - - /** \brief Standard HID Boot Protocol Keyboard Report. - * - * Type define for a standard Boot Protocol Keyboard report - */ - typedef ATTR_IAR_PACKED struct - { - uint8_t Modifier; /**< Keyboard modifier byte, indicating pressed modifier keys (a combination of - * \c HID_KEYBOARD_MODIFER_* masks). - */ - uint8_t Reserved; /**< Reserved for OEM use, always set to 0. */ - uint8_t KeyCode[6]; /**< Key codes of the currently pressed keys. */ - } ATTR_PACKED USB_KeyboardReport_Data_t; - - /** Type define for the data type used to store HID report descriptor elements. */ - typedef uint8_t USB_Descriptor_HIDReport_Datatype_t; - - /* Disable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - } - #endif - -#endif - -/** @} */ - - -#endif /* UC_FAMILY == XMC4 */ diff --git a/cores/usblib/Class/Common/HIDParser.h b/cores/usblib/Class/Common/HIDParser.h deleted file mode 100644 index 36f0b13e..00000000 --- a/cores/usblib/Class/Common/HIDParser.h +++ /dev/null @@ -1,118 +0,0 @@ -#ifdef XMC4_SERIES - -/* - LUFA Library - Copyright (C) Dean Camera, 2014. - - dean [at] fourwalledcubicle [dot] com - www.lufa-lib.org -*/ - -/* - Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com) - - Permission to use, copy, modify, distribute, and sell this - software and its documentation for any purpose is hereby granted - without fee, provided that the above copyright notice appear in - all copies and that both that the copyright notice and this - permission notice and warranty disclaimer appear in supporting - documentation, and that the name of the author not be used in - advertising or publicity pertaining to distribution of the - software without specific, written prior permission. - - The author disclaims all warranties with regard to this - software, including all implied warranties of merchantability - and fitness. In no event shall the author be liable for any - special, indirect or consequential damages or any damages - whatsoever resulting from loss of use, data or profits, whether - in an action of contract, negligence or other tortious action, - arising out of or in connection with the use or performance of - this software. -*/ - -/** \file - * \brief USB Human Interface Device (HID) Class report descriptor parser. - * - * This file allows for the easy parsing of complex HID report descriptors, which describes the data that - * a HID device transmits to the host. It also provides an easy API for extracting and processing the data - * elements inside a HID report sent from an attached HID device. - */ - -/** \ingroup Group_USB - * \defgroup Group_HIDParser HID Report Parser - * \brief USB Human Interface Device (HID) Class report descriptor parser. - * - * \section Sec_HIDParser_Dependencies Module Source Dependencies - * The following files must be built with any user project that uses this module: - * - LUFA/Drivers/USB/Class/Host/HIDParser.c (Makefile source module name: LUFA_SRC_USB) - * - * \section Sec_HIDParser_ModDescription Module Description - * Human Interface Device (HID) class report descriptor parser. This module implements a parser than is - * capable of processing a complete HID report descriptor, and outputting a flat structure containing the - * contents of the report in an a more friendly format. The parsed data may then be further processed and used - * within an application to process sent and received HID reports to and from an attached HID device. - * - * A HID report descriptor consists of a set of HID report items, which describe the function and layout - * of data exchanged between a HID device and a host, including both the physical encoding of each item - * (such as a button, key press or joystick axis) in the sent and received data packets - known as "reports" - - * as well as other information about each item such as the usages, data range, physical location and other - * characteristics. In this way a HID device can retain a high degree of flexibility in its capabilities, as it - * is not forced to comply with a given report layout or feature-set. - * - * This module also contains routines for the processing of data in an actual HID report, using the parsed report - * descriptor data as a guide for the encoding. - * - * @{ - */ - -#ifndef __HIDPARSER_H__ -#define __HIDPARSER_H__ - - /* Includes: */ - #include <../../Common/Common.h> - - #include "HIDReportData.h" - #include "HIDClassCommon.h" - - /* Enable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - extern "C" { - #endif - - - - #if !defined(HID_MAX_REPORT_IDS) || defined(__DOXYGEN__) - /** Constant indicating the maximum number of unique report IDs that can be processed in the report item - * descriptor for the report size information array in the user HID Report Info structure. A large value - * allows for more report ID report sizes to be stored, but consumes more memory. By default this is set - * to 10 items, but this can be overridden by defining \c HID_MAX_REPORT_IDS to another value in the user project - * makefile, and passing the define to the compiler using the -D compiler switch. Note that IN, OUT and FEATURE - * items sharing the same report ID consume only one size item in the array. - */ - #define HID_MAX_REPORT_IDS 10 - #endif - - /** Returns the value a given HID report item (once its value has been fetched via \ref USB_GetHIDReportItemInfo()) - * left-aligned to the given data type. This allows for signed data to be interpreted correctly, by shifting the data - * leftwards until the data's sign bit is in the correct position. - * - * \param[in] ReportItem HID Report Item whose retrieved value is to be aligned. - * \param[in] Type Data type to align the HID report item's value to. - * - * \return Left-aligned data of the given report item's pre-retrieved value for the given datatype. - */ - #define HID_ALIGN_DATA(ReportItem, Type) ((Type)(ReportItem->Value << ((8 * sizeof(Type)) - ReportItem->Attributes.BitSize))) - - - - /* Disable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - } - #endif - -#endif - -/** @} */ - - -#endif /* UC_FAMILY == XMC4 */ diff --git a/cores/usblib/Class/Common/HIDReportData.h b/cores/usblib/Class/Common/HIDReportData.h deleted file mode 100644 index 21026db1..00000000 --- a/cores/usblib/Class/Common/HIDReportData.h +++ /dev/null @@ -1,130 +0,0 @@ -#ifdef XMC4_SERIES - -/* - LUFA Library - Copyright (C) Dean Camera, 2014. - - dean [at] fourwalledcubicle [dot] com - www.lufa-lib.org -*/ - -/* - Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com) - - Permission to use, copy, modify, distribute, and sell this - software and its documentation for any purpose is hereby granted - without fee, provided that the above copyright notice appear in - all copies and that both that the copyright notice and this - permission notice and warranty disclaimer appear in supporting - documentation, and that the name of the author not be used in - advertising or publicity pertaining to distribution of the - software without specific, written prior permission. - - The author disclaims all warranties with regard to this - software, including all implied warranties of merchantability - and fitness. In no event shall the author be liable for any - special, indirect or consequential damages or any damages - whatsoever resulting from loss of use, data or profits, whether - in an action of contract, negligence or other tortious action, - arising out of or in connection with the use or performance of - this software. -*/ - -/** \file - * \brief Constants for HID report item attributes. - * - * HID report item constants for report item attributes. Refer to the HID specification for - * details on each flag's meaning when applied to an IN, OUT or FEATURE item. - */ - -/** \ingroup Group_HIDParser - * \defgroup Group_HIDReportItemConst HID Report Descriptor Item Constants - * - * General HID constant definitions for HID Report Descriptor elements. - * - * @{ - */ - -#ifndef __HIDREPORTDATA_H__ -#define __HIDREPORTDATA_H__ - - /* Private Interface - For use in library only: */ - #if !defined(__DOXYGEN__) - /* Macros: */ - #define HID_RI_DATA_SIZE_MASK 0x03 - #define HID_RI_TYPE_MASK 0x0C - #define HID_RI_TAG_MASK 0xF0 - - #define HID_RI_TYPE_MAIN 0x00 - #define HID_RI_TYPE_GLOBAL 0x04 - #define HID_RI_TYPE_LOCAL 0x08 - - #define HID_RI_DATA_BITS_0 0x00 - #define HID_RI_DATA_BITS_8 0x01 - #define HID_RI_DATA_BITS_16 0x02 - #define HID_RI_DATA_BITS_32 0x03 - #define HID_RI_DATA_BITS(DataBits) CONCAT_EXPANDED(HID_RI_DATA_BITS_, DataBits) - - #define _HID_RI_ENCODE_0(Data) - #define _HID_RI_ENCODE_8(Data) , (Data & 0xFF) - #define _HID_RI_ENCODE_16(Data) _HID_RI_ENCODE_8(Data) _HID_RI_ENCODE_8(Data >> 8) - #define _HID_RI_ENCODE_32(Data) _HID_RI_ENCODE_16(Data) _HID_RI_ENCODE_16(Data >> 16) - #define _HID_RI_ENCODE(DataBits, ...) CONCAT_EXPANDED(_HID_RI_ENCODE_, DataBits(__VA_ARGS__)) - - #define _HID_RI_ENTRY(Type, Tag, DataBits, ...) (Type | Tag | HID_RI_DATA_BITS(DataBits)) _HID_RI_ENCODE(DataBits, (__VA_ARGS__)) - #endif - - /* Public Interface - May be used in end-application: */ - /* Macros: */ - /** \name HID Input, Output and Feature Report Descriptor Item Flags */ - //@{ - #define HID_IOF_CONSTANT (1 << 0) - #define HID_IOF_DATA (0 << 0) - #define HID_IOF_VARIABLE (1 << 1) - #define HID_IOF_ARRAY (0 << 1) - #define HID_IOF_RELATIVE (1 << 2) - #define HID_IOF_ABSOLUTE (0 << 2) - #define HID_IOF_WRAP (1 << 3) - #define HID_IOF_NO_WRAP (0 << 3) - #define HID_IOF_NON_LINEAR (1 << 4) - #define HID_IOF_LINEAR (0 << 4) - #define HID_IOF_NO_PREFERRED_STATE (1 << 5) - #define HID_IOF_PREFERRED_STATE (0 << 5) - #define HID_IOF_NULLSTATE (1 << 6) - #define HID_IOF_NO_NULL_POSITION (0 << 6) - #define HID_IOF_VOLATILE (1 << 7) - #define HID_IOF_NON_VOLATILE (0 << 7) - #define HID_IOF_BUFFERED_BYTES (1 << 8) - #define HID_IOF_BITFIELD (0 << 8) - //@} - - /** \name HID Report Descriptor Item Macros */ - //@{ - #define HID_RI_INPUT(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_MAIN , 0x80, DataBits, __VA_ARGS__) - #define HID_RI_OUTPUT(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_MAIN , 0x90, DataBits, __VA_ARGS__) - #define HID_RI_COLLECTION(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_MAIN , 0xA0, DataBits, __VA_ARGS__) - #define HID_RI_FEATURE(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_MAIN , 0xB0, DataBits, __VA_ARGS__) - #define HID_RI_END_COLLECTION(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_MAIN , 0xC0, DataBits, __VA_ARGS__) - #define HID_RI_USAGE_PAGE(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_GLOBAL, 0x00, DataBits, __VA_ARGS__) - #define HID_RI_LOGICAL_MINIMUM(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_GLOBAL, 0x10, DataBits, __VA_ARGS__) - #define HID_RI_LOGICAL_MAXIMUM(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_GLOBAL, 0x20, DataBits, __VA_ARGS__) - #define HID_RI_PHYSICAL_MINIMUM(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_GLOBAL, 0x30, DataBits, __VA_ARGS__) - #define HID_RI_PHYSICAL_MAXIMUM(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_GLOBAL, 0x40, DataBits, __VA_ARGS__) - #define HID_RI_UNIT_EXPONENT(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_GLOBAL, 0x50, DataBits, __VA_ARGS__) - #define HID_RI_UNIT(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_GLOBAL, 0x60, DataBits, __VA_ARGS__) - #define HID_RI_REPORT_SIZE(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_GLOBAL, 0x70, DataBits, __VA_ARGS__) - #define HID_RI_REPORT_ID(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_GLOBAL, 0x80, DataBits, __VA_ARGS__) - #define HID_RI_REPORT_COUNT(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_GLOBAL, 0x90, DataBits, __VA_ARGS__) - #define HID_RI_PUSH(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_GLOBAL, 0xA0, DataBits, __VA_ARGS__) - #define HID_RI_POP(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_GLOBAL, 0xB0, DataBits, __VA_ARGS__) - #define HID_RI_USAGE(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_LOCAL , 0x00, DataBits, __VA_ARGS__) - #define HID_RI_USAGE_MINIMUM(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_LOCAL , 0x10, DataBits, __VA_ARGS__) - #define HID_RI_USAGE_MAXIMUM(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_LOCAL , 0x20, DataBits, __VA_ARGS__) - //@} - -/** @} */ - -#endif - - -#endif /* UC_FAMILY == XMC4 */ diff --git a/cores/usblib/Class/Common/MassStorageClassCommon.h b/cores/usblib/Class/Common/MassStorageClassCommon.h deleted file mode 100644 index 6904acec..00000000 --- a/cores/usblib/Class/Common/MassStorageClassCommon.h +++ /dev/null @@ -1,372 +0,0 @@ -#ifdef XMC4_SERIES - -/* - LUFA Library - Copyright (C) Dean Camera, 2014. - - dean [at] fourwalledcubicle [dot] com - www.lufa-lib.org -*/ - -/* - Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com) - - Permission to use, copy, modify, distribute, and sell this - software and its documentation for any purpose is hereby granted - without fee, provided that the above copyright notice appear in - all copies and that both that the copyright notice and this - permission notice and warranty disclaimer appear in supporting - documentation, and that the name of the author not be used in - advertising or publicity pertaining to distribution of the - software without specific, written prior permission. - - The author disclaims all warranties with regard to this - software, including all implied warranties of merchantability - and fitness. In no event shall the author be liable for any - special, indirect or consequential damages or any damages - whatsoever resulting from loss of use, data or profits, whether - in an action of contract, negligence or other tortious action, - arising out of or in connection with the use or performance of - this software. -*/ - -/** \file - * \brief Common definitions and declarations for the library USB Mass Storage Class driver. - * - * Common definitions and declarations for the library USB Mass Storage Class driver. - * - * \note This file should not be included directly. It is automatically included as needed by the USB module driver - * dispatch header located in LUFA/Drivers/USB.h. - */ - -/** \ingroup Group_USBClassMS - * \defgroup Group_USBClassMSCommon Common Class Definitions - * - * \section Sec_USBClassMSCommon_ModDescription Module Description - * Constants, Types and Enum definitions that are common to both Device and Host modes for the USB - * Mass Storage Class. - * - * @{ - */ - -#ifndef _MS_CLASS_COMMON_H_ -#define _MS_CLASS_COMMON_H_ - - /* Includes: */ - #include <../../Core/StdDescriptors.h> - - /* Enable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - extern "C" { - #endif - - /* Preprocessor Checks: */ - #if !defined(__INCLUDE_FROM_MS_DRIVER) - #error Do not include this file directly. Include LUFA/Drivers/USB.h instead. - #endif - - /* Macros: */ - /** Magic signature for a Command Block Wrapper used in the Mass Storage Bulk-Only transport protocol. */ - #define MS_CBW_SIGNATURE 0x43425355UL - - /** Magic signature for a Command Status Wrapper used in the Mass Storage Bulk-Only transport protocol. */ - #define MS_CSW_SIGNATURE 0x53425355UL - - /** Mask for a Command Block Wrapper's flags attribute to specify a command with data sent from host-to-device. */ - #define MS_COMMAND_DIR_DATA_OUT (0 << 7) - - /** Mask for a Command Block Wrapper's flags attribute to specify a command with data sent from device-to-host. */ - #define MS_COMMAND_DIR_DATA_IN (1 << 7) - - /** \name SCSI Commands*/ - //@{ - /** SCSI Command Code for an INQUIRY command. */ - #define SCSI_CMD_INQUIRY 0x12 - - /** SCSI Command Code for a REQUEST SENSE command. */ - #define SCSI_CMD_REQUEST_SENSE 0x03 - - /** SCSI Command Code for a TEST UNIT READY command. */ - #define SCSI_CMD_TEST_UNIT_READY 0x00 - - /** SCSI Command Code for a READ CAPACITY (10) command. */ - #define SCSI_CMD_READ_CAPACITY_10 0x25 - - /** SCSI Command Code for a START STOP UNIT command. */ - #define SCSI_CMD_START_STOP_UNIT 0x1B - - /** SCSI Command Code for a SEND DIAGNOSTIC command. */ - #define SCSI_CMD_SEND_DIAGNOSTIC 0x1D - - /** SCSI Command Code for a PREVENT ALLOW MEDIUM REMOVAL command. */ - #define SCSI_CMD_PREVENT_ALLOW_MEDIUM_REMOVAL 0x1E - - /** SCSI Command Code for a WRITE (10) command. */ - #define SCSI_CMD_WRITE_10 0x2A - - /** SCSI Command Code for a READ (10) command. */ - #define SCSI_CMD_READ_10 0x28 - - /** SCSI Command Code for a WRITE (6) command. */ - #define SCSI_CMD_WRITE_6 0x0A - - /** SCSI Command Code for a READ (6) command. */ - #define SCSI_CMD_READ_6 0x08 - - /** SCSI Command Code for a VERIFY (10) command. */ - #define SCSI_CMD_VERIFY_10 0x2F - - /** SCSI Command Code for a MODE SENSE (6) command. */ - #define SCSI_CMD_MODE_SENSE_6 0x1A - - /** SCSI Command Code for a MODE SENSE (10) command. */ - #define SCSI_CMD_MODE_SENSE_10 0x5A - //@} - - /** \name SCSI Sense Key Values */ - //@{ - /** SCSI Sense Code to indicate no error has occurred. */ - #define SCSI_SENSE_KEY_GOOD 0x00 - - /** SCSI Sense Code to indicate that the device has recovered from an error. */ - #define SCSI_SENSE_KEY_RECOVERED_ERROR 0x01 - - /** SCSI Sense Code to indicate that the device is not ready for a new command. */ - #define SCSI_SENSE_KEY_NOT_READY 0x02 - - /** SCSI Sense Code to indicate an error whilst accessing the medium. */ - #define SCSI_SENSE_KEY_MEDIUM_ERROR 0x03 - - /** SCSI Sense Code to indicate a hardware error has occurred. */ - #define SCSI_SENSE_KEY_HARDWARE_ERROR 0x04 - - /** SCSI Sense Code to indicate that an illegal request has been issued. */ - #define SCSI_SENSE_KEY_ILLEGAL_REQUEST 0x05 - - /** SCSI Sense Code to indicate that the unit requires attention from the host to indicate - * a reset event, medium removal or other condition. - */ - #define SCSI_SENSE_KEY_UNIT_ATTENTION 0x06 - - /** SCSI Sense Code to indicate that a write attempt on a protected block has been made. */ - #define SCSI_SENSE_KEY_DATA_PROTECT 0x07 - - /** SCSI Sense Code to indicate an error while trying to write to a write-once medium. */ - #define SCSI_SENSE_KEY_BLANK_CHECK 0x08 - - /** SCSI Sense Code to indicate a vendor specific error has occurred. */ - #define SCSI_SENSE_KEY_VENDOR_SPECIFIC 0x09 - - /** SCSI Sense Code to indicate that an EXTENDED COPY command has aborted due to an error. */ - #define SCSI_SENSE_KEY_COPY_ABORTED 0x0A - - /** SCSI Sense Code to indicate that the device has aborted the issued command. */ - #define SCSI_SENSE_KEY_ABORTED_COMMAND 0x0B - - /** SCSI Sense Code to indicate an attempt to write past the end of a partition has been made. */ - #define SCSI_SENSE_KEY_VOLUME_OVERFLOW 0x0D - - /** SCSI Sense Code to indicate that the source data did not match the data read from the medium. */ - #define SCSI_SENSE_KEY_MISCOMPARE 0x0E - //@} - - /** \name SCSI Additional Sense Codes */ - //@{ - /** SCSI Additional Sense Code to indicate no additional sense information is available. */ - #define SCSI_ASENSE_NO_ADDITIONAL_INFORMATION 0x00 - - /** SCSI Additional Sense Code to indicate that the logical unit (LUN) addressed is not ready. */ - #define SCSI_ASENSE_LOGICAL_UNIT_NOT_READY 0x04 - - /** SCSI Additional Sense Code to indicate an invalid field was encountered while processing the issued command. */ - #define SCSI_ASENSE_INVALID_FIELD_IN_CDB 0x24 - - /** SCSI Additional Sense Code to indicate that a medium that was previously indicated as not ready has now - * become ready for use. - */ - #define SCSI_ASENSE_NOT_READY_TO_READY_CHANGE 0x28 - - /** SCSI Additional Sense Code to indicate that an attempt to write to a protected area was made. */ - #define SCSI_ASENSE_WRITE_PROTECTED 0x27 - - /** SCSI Additional Sense Code to indicate an error whilst formatting the device medium. */ - #define SCSI_ASENSE_FORMAT_ERROR 0x31 - - /** SCSI Additional Sense Code to indicate an invalid command was issued. */ - #define SCSI_ASENSE_INVALID_COMMAND 0x20 - - /** SCSI Additional Sense Code to indicate a write to a block out outside of the medium's range was issued. */ - #define SCSI_ASENSE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE 0x21 - - /** SCSI Additional Sense Code to indicate that no removable medium is inserted into the device. */ - #define SCSI_ASENSE_MEDIUM_NOT_PRESENT 0x3A - //@} - - /** \name SCSI Additional Sense Key Code Qualifiers */ - //@{ - /** SCSI Additional Sense Qualifier Code to indicate no additional sense qualifier information is available. */ - #define SCSI_ASENSEQ_NO_QUALIFIER 0x00 - - /** SCSI Additional Sense Qualifier Code to indicate that a medium format command failed to complete. */ - #define SCSI_ASENSEQ_FORMAT_COMMAND_FAILED 0x01 - - /** SCSI Additional Sense Qualifier Code to indicate that an initializing command must be issued before the issued - * command can be executed. - */ - #define SCSI_ASENSEQ_INITIALIZING_COMMAND_REQUIRED 0x02 - - /** SCSI Additional Sense Qualifier Code to indicate that an operation is currently in progress. */ - #define SCSI_ASENSEQ_OPERATION_IN_PROGRESS 0x07 - //@} - - /* Enums: */ - /** Enum for possible Class, Subclass and Protocol values of device and interface descriptors relating to the Mass - * Storage device class. - */ - enum MS_Descriptor_ClassSubclassProtocol_t - { - MS_CSCP_MassStorageClass = 0x08, /**< Descriptor Class value indicating that the device or interface - * belongs to the Mass Storage class. - */ - MS_CSCP_SCSITransparentSubclass = 0x06, /**< Descriptor Subclass value indicating that the device or interface - * belongs to the SCSI Transparent Command Set subclass of the Mass - * storage class. - */ - MS_CSCP_BulkOnlyTransportProtocol = 0x50, /**< Descriptor Protocol value indicating that the device or interface - * belongs to the Bulk Only Transport protocol of the Mass Storage class. - */ - }; - - /** Enum for the Mass Storage class specific control requests that can be issued by the USB bus host. */ - enum MS_ClassRequests_t - { - MS_REQ_GetMaxLUN = 0xFE, /**< Mass Storage class-specific request to retrieve the total number of Logical - * Units (drives) in the SCSI device. - */ - MS_REQ_MassStorageReset = 0xFF, /**< Mass Storage class-specific request to reset the Mass Storage interface, - * ready for the next command. - */ - }; - - /** Enum for the possible command status wrapper return status codes. */ - enum MS_CommandStatusCodes_t - { - MS_SCSI_COMMAND_Pass = 0, /**< Command completed with no error */ - MS_SCSI_COMMAND_Fail = 1, /**< Command failed to complete - host may check the exact error via a - * SCSI REQUEST SENSE command. - */ - MS_SCSI_COMMAND_PhaseError = 2, /**< Command failed due to being invalid in the current phase. */ - }; - - /* Type Defines: */ - /** \brief Mass Storage Class Command Block Wrapper. - * - * Type define for a Command Block Wrapper, used in the Mass Storage Bulk-Only Transport protocol. - * - * \note Regardless of CPU architecture, these values should be stored as little endian. - */ - typedef ATTR_IAR_PACKED struct - { - uint32_t Signature; /**< Command block signature, must be \ref MS_CBW_SIGNATURE to indicate a valid Command Block. */ - uint32_t Tag; /**< Unique command ID value, to associate a command block wrapper with its command status wrapper. */ - uint32_t DataTransferLength; /**< Length of the optional data portion of the issued command, in bytes. */ - uint8_t Flags; /**< Command block flags, indicating command data direction. */ - uint8_t LUN; /**< Logical Unit number this command is issued to. */ - uint8_t SCSICommandLength; /**< Length of the issued SCSI command within the SCSI command data array. */ - uint8_t SCSICommandData[16]; /**< Issued SCSI command in the Command Block. */ - } ATTR_PACKED MS_CommandBlockWrapper_t; - - /** \brief Mass Storage Class Command Status Wrapper. - * - * Type define for a Command Status Wrapper, used in the Mass Storage Bulk-Only Transport protocol. - * - * \note Regardless of CPU architecture, these values should be stored as little endian. - */ - typedef ATTR_IAR_PACKED struct - { - uint32_t Signature; /**< Status block signature, must be \ref MS_CSW_SIGNATURE to indicate a valid Command Status. */ - uint32_t Tag; /**< Unique command ID value, to associate a command block wrapper with its command status wrapper. */ - uint32_t DataTransferResidue; /**< Number of bytes of data not processed in the SCSI command. */ - uint8_t Status; /**< Status code of the issued command - a value from the \ref MS_CommandStatusCodes_t enum. */ - } ATTR_PACKED MS_CommandStatusWrapper_t; - - /** \brief Mass Storage Class SCSI Sense Structure - * - * Type define for a SCSI Sense structure. Structures of this type are filled out by the - * device via the \ref MS_Host_RequestSense() function, indicating the current sense data of the - * device (giving explicit error codes for the last issued command). For details of the - * structure contents, refer to the SCSI specifications. - */ - typedef ATTR_IAR_PACKED struct - { - uint8_t ResponseCode; - - uint8_t SegmentNumber; - - unsigned SenseKey : 4; - unsigned Reserved : 1; - unsigned ILI : 1; - unsigned EOM : 1; - unsigned FileMark : 1; - - uint8_t Information[4]; - uint8_t AdditionalLength; - uint8_t CmdSpecificInformation[4]; - uint8_t AdditionalSenseCode; - uint8_t AdditionalSenseQualifier; - uint8_t FieldReplaceableUnitCode; - uint8_t SenseKeySpecific[3]; - } ATTR_PACKED SCSI_Request_Sense_Response_t; - - /** \brief Mass Storage Class SCSI Inquiry Structure. - * - * Type define for a SCSI Inquiry structure. Structures of this type are filled out by the - * device via the \ref MS_Host_GetInquiryData() function, retrieving the attached device's - * information. - * - * For details of the structure contents, refer to the SCSI specifications. - */ - typedef ATTR_IAR_PACKED struct - { - unsigned DeviceType : 5; - unsigned PeripheralQualifier : 3; - - unsigned Reserved : 7; - unsigned Removable : 1; - - uint8_t Version; - - unsigned ResponseDataFormat : 4; - unsigned Reserved2 : 1; - unsigned NormACA : 1; - unsigned TrmTsk : 1; - unsigned AERC : 1; - - uint8_t AdditionalLength; - uint8_t Reserved3[2]; - - unsigned SoftReset : 1; - unsigned CmdQue : 1; - unsigned Reserved4 : 1; - unsigned Linked : 1; - unsigned Sync : 1; - unsigned WideBus16Bit : 1; - unsigned WideBus32Bit : 1; - unsigned RelAddr : 1; - - uint8_t VendorID[8]; - uint8_t ProductID[16]; - uint8_t RevisionID[4]; - } ATTR_PACKED SCSI_Inquiry_Response_t; - - /* Disable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - } - #endif - -#endif - -/** @} */ - - -#endif /* UC_FAMILY == XMC4 */ diff --git a/cores/usblib/Class/Device/CDCClassDevice.c b/cores/usblib/Class/Device/CDCClassDevice.c deleted file mode 100644 index 5aa7d282..00000000 --- a/cores/usblib/Class/Device/CDCClassDevice.c +++ /dev/null @@ -1,354 +0,0 @@ -#ifdef XMC4_SERIES - -/* - LUFA Library - Copyright (C) Dean Camera, 2014. - - dean [at] fourwalledcubicle [dot] com - www.lufa-lib.org -*/ - -/* - Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com) - - Permission to use, copy, modify, distribute, and sell this - software and its documentation for any purpose is hereby granted - without fee, provided that the above copyright notice appear in - all copies and that both that the copyright notice and this - permission notice and warranty disclaimer appear in supporting - documentation, and that the name of the author not be used in - advertising or publicity pertaining to distribution of the - software without specific, written prior permission. - - The author disclaims all warranties with regard to this - software, including all implied warranties of merchantability - and fitness. In no event shall the author be liable for any - special, indirect or consequential damages or any damages - whatsoever resulting from loss of use, data or profits, whether - in an action of contract, negligence or other tortious action, - arising out of or in connection with the use or performance of - this software. -*/ -#if defined(USB0) -#define __INCLUDE_FROM_USB_DRIVER -#include <../../Core/USBMode.h> - -#if defined(USB_CAN_BE_DEVICE) - -#define __INCLUDE_FROM_CDC_DRIVER -#define __INCLUDE_FROM_CDC_DEVICE_C -#include - -void CDC_Device_ProcessControlRequest(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo) -{ - if (!(Endpoint_IsSETUPReceived())) - return; - - if (USB_ControlRequest.wIndex != CDCInterfaceInfo->Config.ControlInterfaceNumber) - return; - - switch (USB_ControlRequest.bRequest) - { - case CDC_REQ_GetLineEncoding: - if (USB_ControlRequest.bmRequestType == (REQDIR_DEVICETOHOST | REQTYPE_CLASS | REQREC_INTERFACE)) - { - Endpoint_ClearSETUP(); - - while (!(Endpoint_IsINReady())); - - Endpoint_Write_32_LE(CDCInterfaceInfo->State.LineEncoding.BaudRateBPS); - Endpoint_Write_8(CDCInterfaceInfo->State.LineEncoding.CharFormat); - Endpoint_Write_8(CDCInterfaceInfo->State.LineEncoding.ParityType); - Endpoint_Write_8(CDCInterfaceInfo->State.LineEncoding.DataBits); - - Endpoint_ClearIN(); - Endpoint_ClearStatusStage(); - } - - break; - case CDC_REQ_SetLineEncoding: - if (USB_ControlRequest.bmRequestType == (REQDIR_HOSTTODEVICE | REQTYPE_CLASS | REQREC_INTERFACE)) - { - Endpoint_ClearSETUP(); - - while (!(Endpoint_IsOUTReceived())) - { - if (USB_DeviceState == DEVICE_STATE_Unattached) - return; - } - - CDCInterfaceInfo->State.LineEncoding.BaudRateBPS = Endpoint_Read_32_LE(); - CDCInterfaceInfo->State.LineEncoding.CharFormat = Endpoint_Read_8(); - CDCInterfaceInfo->State.LineEncoding.ParityType = Endpoint_Read_8(); - CDCInterfaceInfo->State.LineEncoding.DataBits = Endpoint_Read_8(); - - Endpoint_ClearOUT(); - Endpoint_ClearStatusStage(); - - EVENT_CDC_Device_LineEncodingChanged(CDCInterfaceInfo); - } - - break; - case CDC_REQ_SetControlLineState: - if (USB_ControlRequest.bmRequestType == (REQDIR_HOSTTODEVICE | REQTYPE_CLASS | REQREC_INTERFACE)) - { - Endpoint_ClearSETUP(); - Endpoint_ClearStatusStage(); - - CDCInterfaceInfo->State.ControlLineStates.HostToDevice = USB_ControlRequest.wValue; - - EVENT_CDC_Device_ControLineStateChanged(CDCInterfaceInfo); - } - - break; - case CDC_REQ_SendBreak: - if (USB_ControlRequest.bmRequestType == (REQDIR_HOSTTODEVICE | REQTYPE_CLASS | REQREC_INTERFACE)) - { - Endpoint_ClearSETUP(); - Endpoint_ClearStatusStage(); - - EVENT_CDC_Device_BreakSent(CDCInterfaceInfo, (uint8_t)USB_ControlRequest.wValue); - } - - break; - } -} - -bool CDC_Device_ConfigureEndpoints(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo) -{ - memset(&CDCInterfaceInfo->State, 0x00, sizeof(CDCInterfaceInfo->State)); - - CDCInterfaceInfo->Config.DataINEndpoint.Type = EP_TYPE_BULK; - CDCInterfaceInfo->Config.DataOUTEndpoint.Type = EP_TYPE_BULK; - CDCInterfaceInfo->Config.NotificationEndpoint.Type = EP_TYPE_INTERRUPT; - - if (!(Endpoint_ConfigureEndpointTable(&CDCInterfaceInfo->Config.DataINEndpoint, 1))) - return false; - - if (!(Endpoint_ConfigureEndpointTable(&CDCInterfaceInfo->Config.DataOUTEndpoint, 1))) - return false; - - if (!(Endpoint_ConfigureEndpointTable(&CDCInterfaceInfo->Config.NotificationEndpoint, 1))) - return false; - - return true; -} - -void CDC_Device_USBTask(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo) -{ - if ((USB_DeviceState != DEVICE_STATE_Configured) || !(CDCInterfaceInfo->State.LineEncoding.BaudRateBPS)) - return; - - #if !defined(NO_CLASS_DRIVER_AUTOFLUSH) - Endpoint_SelectEndpoint(CDCInterfaceInfo->Config.DataINEndpoint.Address); - - if (Endpoint_IsINReady()) - CDC_Device_Flush(CDCInterfaceInfo); - #endif -} - -uint8_t CDC_Device_SendString(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo, - const char* const String) -{ - if ((USB_DeviceState != DEVICE_STATE_Configured) || !(CDCInterfaceInfo->State.LineEncoding.BaudRateBPS)) - return ENDPOINT_RWSTREAM_DeviceDisconnected; - - Endpoint_SelectEndpoint(CDCInterfaceInfo->Config.DataINEndpoint.Address); - return Endpoint_Write_Stream_LE(String, strlen(String), NULL); -} - -uint8_t CDC_Device_SendData(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo, - const void* const Buffer, - const uint16_t Length) -{ - if ((USB_DeviceState != DEVICE_STATE_Configured) || !(CDCInterfaceInfo->State.LineEncoding.BaudRateBPS)) - return ENDPOINT_RWSTREAM_DeviceDisconnected; - - Endpoint_SelectEndpoint(CDCInterfaceInfo->Config.DataINEndpoint.Address); - return Endpoint_Write_Stream_LE(Buffer, Length, NULL); -} - -uint8_t CDC_Device_SendByte(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo, - const uint8_t Data) -{ - if ((USB_DeviceState != DEVICE_STATE_Configured) || !(CDCInterfaceInfo->State.LineEncoding.BaudRateBPS)) - return ENDPOINT_RWSTREAM_DeviceDisconnected; - - Endpoint_SelectEndpoint(CDCInterfaceInfo->Config.DataINEndpoint.Address); - - if (!(Endpoint_IsReadWriteAllowed())) - { - Endpoint_ClearIN(); - - uint8_t ErrorCode; - - if ((ErrorCode = Endpoint_WaitUntilReady()) != ENDPOINT_READYWAIT_NoError) - return ErrorCode; - } - - Endpoint_Write_8(Data); - return ENDPOINT_READYWAIT_NoError; -} - -uint8_t CDC_Device_Flush(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo) -{ - if ((USB_DeviceState != DEVICE_STATE_Configured) || !(CDCInterfaceInfo->State.LineEncoding.BaudRateBPS)) - return ENDPOINT_RWSTREAM_DeviceDisconnected; - - uint8_t ErrorCode; - - Endpoint_SelectEndpoint(CDCInterfaceInfo->Config.DataINEndpoint.Address); - - if (!(Endpoint_BytesInEndpoint())) - return ENDPOINT_READYWAIT_NoError; - - bool BankFull = !(Endpoint_IsReadWriteAllowed()); - - Endpoint_ClearIN(); - - if (BankFull) - { - if ((ErrorCode = Endpoint_WaitUntilReady()) != ENDPOINT_READYWAIT_NoError) - return ErrorCode; - - Endpoint_ClearIN(); - } - - return ENDPOINT_READYWAIT_NoError; -} - -uint16_t CDC_Device_BytesReceived(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo) -{ - if ((USB_DeviceState != DEVICE_STATE_Configured) || !(CDCInterfaceInfo->State.LineEncoding.BaudRateBPS)) - return 0; - - Endpoint_SelectEndpoint(CDCInterfaceInfo->Config.DataOUTEndpoint.Address); - - if (Endpoint_IsOUTReceived()) - { - if (!(Endpoint_BytesInEndpoint())) - { - Endpoint_ClearOUT(); - return 0; - } - else - { - return Endpoint_BytesInEndpoint(); - } - } - else - { - return 0; - } -} - -int16_t CDC_Device_ReceiveByte(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo) -{ - if ((USB_DeviceState != DEVICE_STATE_Configured) || !(CDCInterfaceInfo->State.LineEncoding.BaudRateBPS)) - return -1; - - int16_t ReceivedByte = -1; - - Endpoint_SelectEndpoint(CDCInterfaceInfo->Config.DataOUTEndpoint.Address); - - if (Endpoint_IsOUTReceived()) - { - if (Endpoint_BytesInEndpoint()) - ReceivedByte = Endpoint_Read_8(); - - if (!(Endpoint_BytesInEndpoint())) - Endpoint_ClearOUT(); - } - - return ReceivedByte; -} - -void CDC_Device_SendControlLineStateChange(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo) -{ - if ((USB_DeviceState != DEVICE_STATE_Configured) || !(CDCInterfaceInfo->State.LineEncoding.BaudRateBPS)) - return; - - Endpoint_SelectEndpoint(CDCInterfaceInfo->Config.NotificationEndpoint.Address); - - USB_Request_Header_t Notification = (USB_Request_Header_t) - { - .bmRequestType = (REQDIR_DEVICETOHOST | REQTYPE_CLASS | REQREC_INTERFACE), - .bRequest = CDC_NOTIF_SerialState, - .wValue = CPU_TO_LE16(0), - .wIndex = CPU_TO_LE16(0), - .wLength = CPU_TO_LE16(sizeof(CDCInterfaceInfo->State.ControlLineStates.DeviceToHost)), - }; - - Endpoint_Write_Stream_LE(&Notification, sizeof(USB_Request_Header_t), NULL); - Endpoint_Write_Stream_LE(&CDCInterfaceInfo->State.ControlLineStates.DeviceToHost, - sizeof(CDCInterfaceInfo->State.ControlLineStates.DeviceToHost), - NULL); - Endpoint_ClearIN(); -} - -#if defined(FDEV_SETUP_STREAM) -void CDC_Device_CreateStream(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo, - FILE* const Stream) -{ - *Stream = (FILE)FDEV_SETUP_STREAM(CDC_Device_putchar, CDC_Device_getchar, _FDEV_SETUP_RW); - fdev_set_udata(Stream, CDCInterfaceInfo); -} - -void CDC_Device_CreateBlockingStream(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo, - FILE* const Stream) -{ - *Stream = (FILE)FDEV_SETUP_STREAM(CDC_Device_putchar, CDC_Device_getchar_Blocking, _FDEV_SETUP_RW); - fdev_set_udata(Stream, CDCInterfaceInfo); -} - -static int CDC_Device_putchar(char c, - FILE* Stream) -{ - return CDC_Device_SendByte((USB_ClassInfo_CDC_Device_t*)fdev_get_udata(Stream), c) ? _FDEV_ERR : 0; -} - -static int CDC_Device_getchar(FILE* Stream) -{ - int16_t ReceivedByte = CDC_Device_ReceiveByte((USB_ClassInfo_CDC_Device_t*)fdev_get_udata(Stream)); - - if (ReceivedByte < 0) - return _FDEV_EOF; - - return ReceivedByte; -} - -static int CDC_Device_getchar_Blocking(FILE* Stream) -{ - int16_t ReceivedByte; - - while ((ReceivedByte = CDC_Device_ReceiveByte((USB_ClassInfo_CDC_Device_t*)fdev_get_udata(Stream))) < 0) - { - if (USB_DeviceState == DEVICE_STATE_Unattached) - return _FDEV_EOF; - - CDC_Device_USBTask((USB_ClassInfo_CDC_Device_t*)fdev_get_udata(Stream)); - USB_USBTask(); - } - - return ReceivedByte; -} -#endif - -__WEAK void EVENT_CDC_Device_LineEncodingChanged(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo) -{ -} - -__WEAK void EVENT_CDC_Device_ControLineStateChanged(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo) -{ -} - -__WEAK void EVENT_CDC_Device_BreakSent(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo, - const uint8_t Duration) -{ -} - - -#endif -#endif - -#endif /* UC_FAMILY == XMC4 */ diff --git a/cores/usblib/Class/Device/CDCClassDevice.h b/cores/usblib/Class/Device/CDCClassDevice.h deleted file mode 100644 index 8643f6b5..00000000 --- a/cores/usblib/Class/Device/CDCClassDevice.h +++ /dev/null @@ -1,351 +0,0 @@ -#ifdef XMC4_SERIES - -/* - LUFA Library - Copyright (C) Dean Camera, 2014. - - dean [at] fourwalledcubicle [dot] com - www.lufa-lib.org -*/ - -/* - Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com) - - Permission to use, copy, modify, distribute, and sell this - software and its documentation for any purpose is hereby granted - without fee, provided that the above copyright notice appear in - all copies and that both that the copyright notice and this - permission notice and warranty disclaimer appear in supporting - documentation, and that the name of the author not be used in - advertising or publicity pertaining to distribution of the - software without specific, written prior permission. - - The author disclaims all warranties with regard to this - software, including all implied warranties of merchantability - and fitness. In no event shall the author be liable for any - special, indirect or consequential damages or any damages - whatsoever resulting from loss of use, data or profits, whether - in an action of contract, negligence or other tortious action, - arising out of or in connection with the use or performance of - this software. -*/ - -/** \file - * \brief Device mode driver for the library USB CDC Class driver. - * - * Device mode driver for the library USB CDC Class driver. - * - * \note This file should not be included directly. It is automatically included as needed by the USB module driver - * dispatch header located in LUFA/Drivers/USB.h. - */ - -/** \ingroup Group_USBClassCDC - * \defgroup Group_USBClassCDCDevice CDC Class Device Mode Driver - * - * \section Sec_USBClassCDCDevice_Dependencies Module Source Dependencies - * The following files must be built with any user project that uses this module: - * - LUFA/Drivers/USB/Class/Device/CDCClassDevice.c (Makefile source module name: LUFA_SRC_USBCLASS) - * - * \section Sec_USBClassCDCDevice_ModDescription Module Description - * Device Mode USB Class driver framework interface, for the CDC USB Class driver. - * - * \note There are several major drawbacks to the CDC-ACM standard USB class, however - * it is very standardized and thus usually available as a built-in driver on - * most platforms, and so is a better choice than a proprietary serial class. - * - * One major issue with CDC-ACM is that it requires two Interface descriptors, - * which will upset most hosts when part of a multi-function "Composite" USB - * device. This is because each interface will be loaded into a separate driver - * instance, causing the two interfaces be become unlinked. To prevent this, you - * should use the "Interface Association Descriptor" addendum to the USB 2.0 standard - * which is available on most OSes when creating Composite devices. - * - * Another major oversight is that there is no mechanism for the host to notify the - * device that there is a data sink on the host side ready to accept data. This - * means that the device may try to send data while the host isn't listening, causing - * lengthy blocking timeouts in the transmission routines. It is thus highly recommended - * that the virtual serial line DTR (Data Terminal Ready) signal be used where possible - * to determine if a host application is ready for data. - * - * @{ - */ - -#ifndef _CDC_CLASS_DEVICE_H_ -#define _CDC_CLASS_DEVICE_H_ -#if defined(USB0) - /* Includes: */ - #include <../../usblib.h> - #include <../Common/CDCClassCommon.h> - - #include - - /* Enable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - extern "C" { - #endif - - /* Preprocessor Checks: */ - #if !defined(__INCLUDE_FROM_CDC_DRIVER) - #error Do not include this file directly. Include LUFA/Drivers/USB.h instead. - #endif - - /* Public Interface - May be used in end-application: */ - /* Type Defines: */ - /** \brief CDC Class Device Mode Configuration and State Structure. - * - * Class state structure. An instance of this structure should be made for each CDC interface - * within the user application, and passed to each of the CDC class driver functions as the - * CDCInterfaceInfo parameter. This stores each CDC interface's configuration and state information. - */ - typedef struct - { - struct - { - uint8_t ControlInterfaceNumber; /**< Interface number of the CDC control interface within the device. */ - - USB_Endpoint_Table_t DataINEndpoint; /**< Data IN endpoint configuration table. */ - USB_Endpoint_Table_t DataOUTEndpoint; /**< Data OUT endpoint configuration table. */ - USB_Endpoint_Table_t NotificationEndpoint; /**< Notification IN Endpoint configuration table. */ - } Config; /**< Config data for the USB class interface within the device. All elements in this section - * must be set or the interface will fail to enumerate and operate correctly. - */ - struct - { - struct - { - uint16_t HostToDevice; /**< Control line states from the host to device, as a set of \c CDC_CONTROL_LINE_OUT_* - * masks. This value is updated each time \ref CDC_Device_USBTask() is called. - */ - uint16_t DeviceToHost; /**< Control line states from the device to host, as a set of \c CDC_CONTROL_LINE_IN_* - * masks - to notify the host of changes to these values, call the - * \ref CDC_Device_SendControlLineStateChange() function. - */ - } ControlLineStates; /**< Current states of the virtual serial port's control lines between the device and host. */ - - CDC_LineEncoding_t LineEncoding; /**< Line encoding used in the virtual serial port, for the device's information. - * This is generally only used if the virtual serial port data is to be - * reconstructed on a physical UART. - */ - } State; /**< State data for the USB class interface within the device. All elements in this section - * are reset to their defaults when the interface is enumerated. - */ - } USB_ClassInfo_CDC_Device_t; - - /* Function Prototypes: */ - /** Configures the endpoints of a given CDC interface, ready for use. This should be linked to the library - * \ref EVENT_USB_Device_ConfigurationChanged() event so that the endpoints are configured when the configuration containing - * the given CDC interface is selected. - * - * \param[in,out] CDCInterfaceInfo Pointer to a structure containing a CDC Class configuration and state. - * - * \return Boolean \c true if the endpoints were successfully configured, \c false otherwise. - */ - bool CDC_Device_ConfigureEndpoints(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1); - - /** Processes incoming control requests from the host, that are directed to the given CDC class interface. This should be - * linked to the library \ref EVENT_USB_Device_ControlRequest() event. - * - * \param[in,out] CDCInterfaceInfo Pointer to a structure containing a CDC Class configuration and state. - */ - void CDC_Device_ProcessControlRequest(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1); - - /** General management task for a given CDC class interface, required for the correct operation of the interface. This should - * be called frequently in the main program loop, before the master USB management task \ref USB_USBTask(). - * - * \param[in,out] CDCInterfaceInfo Pointer to a structure containing a CDC Class configuration and state. - */ - void CDC_Device_USBTask(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1); - - /** CDC class driver event for a line encoding change on a CDC interface. This event fires each time the host requests a - * line encoding change (containing the serial parity, baud and other configuration information) and may be hooked in the - * user program by declaring a handler function with the same name and parameters listed here. The new line encoding - * settings are available in the \c LineEncoding structure inside the CDC interface structure passed as a parameter. - * - * \param[in,out] CDCInterfaceInfo Pointer to a structure containing a CDC Class configuration and state. - */ - void EVENT_CDC_Device_LineEncodingChanged(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1); - - /** CDC class driver event for a control line state change on a CDC interface. This event fires each time the host requests a - * control line state change (containing the virtual serial control line states, such as DTR) and may be hooked in the - * user program by declaring a handler function with the same name and parameters listed here. The new control line states - * are available in the \c ControlLineStates.HostToDevice value inside the CDC interface structure passed as a parameter, set as - * a mask of \c CDC_CONTROL_LINE_OUT_* masks. - * - * \param[in,out] CDCInterfaceInfo Pointer to a structure containing a CDC Class configuration and state. - */ - void EVENT_CDC_Device_ControLineStateChanged(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1); - - /** CDC class driver event for a send break request sent to the device from the host. This is generally used to separate - * data or to indicate a special condition to the receiving device. - * - * \param[in,out] CDCInterfaceInfo Pointer to a structure containing a CDC Class configuration and state. - * \param[in] Duration Duration of the break that has been sent by the host, in milliseconds. - */ - void EVENT_CDC_Device_BreakSent(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo, - const uint8_t Duration) ATTR_NON_NULL_PTR_ARG(1); - - /** Sends a given data buffer to the attached USB host, if connected. If a host is not connected when the function is - * called, the string is discarded. Bytes will be queued for transmission to the host until either the endpoint bank - * becomes full, or the \ref CDC_Device_Flush() function is called to flush the pending data to the host. This allows - * for multiple bytes to be packed into a single endpoint packet, increasing data throughput. - * - * \pre This function must only be called when the Device state machine is in the \ref DEVICE_STATE_Configured state or - * the call will fail. - * - * \param[in,out] CDCInterfaceInfo Pointer to a structure containing a CDC Class configuration and state. - * \param[in] Buffer Pointer to a buffer containing the data to send to the device. - * \param[in] Length Length of the data to send to the host. - * - * \return A value from the \ref Endpoint_Stream_RW_ErrorCodes_t enum. - */ - uint8_t CDC_Device_SendData(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo, - const void* const Buffer, - const uint16_t Length) ATTR_NON_NULL_PTR_ARG(1) ATTR_NON_NULL_PTR_ARG(2); - - /** Sends a given null terminated string to the attached USB host, if connected. If a host is not connected when - * the function is called, the string is discarded. Bytes will be queued for transmission to the host until either - * the endpoint bank becomes full, or the \ref CDC_Device_Flush() function is called to flush the pending data to - * the host. This allows for multiple bytes to be packed into a single endpoint packet, increasing data throughput. - * - * \pre This function must only be called when the Device state machine is in the \ref DEVICE_STATE_Configured state or - * the call will fail. - * - * \param[in,out] CDCInterfaceInfo Pointer to a structure containing a CDC Class configuration and state. - * \param[in] String Pointer to the null terminated string to send to the host. - * - * \return A value from the \ref Endpoint_Stream_RW_ErrorCodes_t enum. - */ - uint8_t CDC_Device_SendString(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo, - const char* const String) ATTR_NON_NULL_PTR_ARG(1) ATTR_NON_NULL_PTR_ARG(2); - - /** Sends a given byte to the attached USB host, if connected. If a host is not connected when the function is called, the - * byte is discarded. Bytes will be queued for transmission to the host until either the endpoint bank becomes full, or the - * \ref CDC_Device_Flush() function is called to flush the pending data to the host. This allows for multiple bytes to be - * packed into a single endpoint packet, increasing data throughput. - * - * \pre This function must only be called when the Device state machine is in the \ref DEVICE_STATE_Configured state or - * the call will fail. - * - * \param[in,out] CDCInterfaceInfo Pointer to a structure containing a CDC Class configuration and state. - * \param[in] Data Byte of data to send to the host. - * - * \return A value from the \ref Endpoint_WaitUntilReady_ErrorCodes_t enum. - */ - uint8_t CDC_Device_SendByte(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo, - const uint8_t Data) ATTR_NON_NULL_PTR_ARG(1); - - /** Determines the number of bytes received by the CDC interface from the host, waiting to be read. This indicates the number - * of bytes in the OUT endpoint bank only, and thus the number of calls to \ref CDC_Device_ReceiveByte() which are guaranteed to - * succeed immediately. If multiple bytes are to be received, they should be buffered by the user application, as the endpoint - * bank will not be released back to the USB controller until all bytes are read. - * - * \pre This function must only be called when the Device state machine is in the \ref DEVICE_STATE_Configured state or - * the call will fail. - * - * \param[in,out] CDCInterfaceInfo Pointer to a structure containing a CDC Class configuration and state. - * - * \return Total number of buffered bytes received from the host. - */ - uint16_t CDC_Device_BytesReceived(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1); - - /** Reads a byte of data from the host. If no data is waiting to be read of if a USB host is not connected, the function - * returns a negative value. The \ref CDC_Device_BytesReceived() function may be queried in advance to determine how many - * bytes are currently buffered in the CDC interface's data receive endpoint bank, and thus how many repeated calls to this - * function which are guaranteed to succeed. - * - * \pre This function must only be called when the Device state machine is in the \ref DEVICE_STATE_Configured state or - * the call will fail. - * - * \param[in,out] CDCInterfaceInfo Pointer to a structure containing a CDC Class configuration and state. - * - * \return Next received byte from the host, or a negative value if no data received. - */ - int16_t CDC_Device_ReceiveByte(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1); - - /** Flushes any data waiting to be sent, ensuring that the send buffer is cleared. - * - * \pre This function must only be called when the Device state machine is in the \ref DEVICE_STATE_Configured state or - * the call will fail. - * - * \param[in,out] CDCInterfaceInfo Pointer to a structure containing a CDC Class configuration and state. - * - * \return A value from the \ref Endpoint_WaitUntilReady_ErrorCodes_t enum. - */ - uint8_t CDC_Device_Flush(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1); - - /** Sends a Serial Control Line State Change notification to the host. This should be called when the virtual serial - * control lines (DCD, DSR, etc.) have changed states, or to give BREAK notifications to the host. Line states persist - * until they are cleared via a second notification. This should be called each time the CDC class driver's - * \c ControlLineStates.DeviceToHost value is updated to push the new states to the USB host. - * - * \pre This function must only be called when the Device state machine is in the \ref DEVICE_STATE_Configured state or - * the call will fail. - * - * \param[in,out] CDCInterfaceInfo Pointer to a structure containing a CDC Class configuration and state. - */ - void CDC_Device_SendControlLineStateChange(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1); - - #if defined(FDEV_SETUP_STREAM) || defined(__DOXYGEN__) - /** Creates a standard character stream for the given CDC Device instance so that it can be used with all the regular - * functions in the standard library that accept a \c FILE stream as a destination (e.g. \c fprintf()). The created - * stream is bidirectional and can be used for both input and output functions. - * - * Reading data from this stream is non-blocking, i.e. in most instances, complete strings cannot be read in by a single - * fetch, as the endpoint will not be ready at some point in the transmission, aborting the transfer. However, this may - * be used when the read data is processed byte-per-bye (via \c getc()) or when the user application will implement its own - * line buffering. - * - * \note The created stream can be given as \c stdout if desired to direct the standard output from all \c functions - * to the given CDC interface. - * \n\n - * - * \note This function is not available on all microcontroller architectures. - * - * \param[in,out] CDCInterfaceInfo Pointer to a structure containing a CDC Class configuration and state. - * \param[in,out] Stream Pointer to a FILE structure where the created stream should be placed. - */ - void CDC_Device_CreateStream(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo, - FILE* const Stream) ATTR_NON_NULL_PTR_ARG(1) ATTR_NON_NULL_PTR_ARG(2); - - /** Identical to \ref CDC_Device_CreateStream(), except that reads are blocking until the calling stream function terminates - * the transfer. While blocking, the USB and CDC service tasks are called repeatedly to maintain USB communications. - * - * \note This function is not available on all microcontroller architectures. - * - * \param[in,out] CDCInterfaceInfo Pointer to a structure containing a CDC Class configuration and state. - * \param[in,out] Stream Pointer to a FILE structure where the created stream should be placed. - */ - void CDC_Device_CreateBlockingStream(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo, - FILE* const Stream) ATTR_NON_NULL_PTR_ARG(1) ATTR_NON_NULL_PTR_ARG(2); - #endif - - /* Private Interface - For use in library only: */ - #if !defined(__DOXYGEN__) - /* Function Prototypes: */ - #if defined(__INCLUDE_FROM_CDC_DEVICE_C) - #if defined(FDEV_SETUP_STREAM) - static int CDC_Device_putchar(char c, - FILE* Stream) ATTR_NON_NULL_PTR_ARG(2); - static int CDC_Device_getchar(FILE* Stream) ATTR_NON_NULL_PTR_ARG(1); - static int CDC_Device_getchar_Blocking(FILE* Stream) ATTR_NON_NULL_PTR_ARG(1); - #endif - - void EVENT_CDC_Device_LineEncodingChanged(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo); - void EVENT_CDC_Device_ControLineStateChanged(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo); - void EVENT_CDC_Device_BreakSent(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo, - const uint8_t Duration); - #endif - - #endif - - /* Disable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - } - #endif - -#endif -#endif -/** @} */ - - -#endif /* UC_FAMILY == XMC4 */ diff --git a/cores/usblib/Class/Device/HIDClassDevice.c b/cores/usblib/Class/Device/HIDClassDevice.c deleted file mode 100644 index ddf002b8..00000000 --- a/cores/usblib/Class/Device/HIDClassDevice.c +++ /dev/null @@ -1,217 +0,0 @@ -#ifdef XMC4_SERIES - -/* - LUFA Library - Copyright (C) Dean Camera, 2014. - - dean [at] fourwalledcubicle [dot] com - www.lufa-lib.org -*/ - -/* - Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com) - - Permission to use, copy, modify, distribute, and sell this - software and its documentation for any purpose is hereby granted - without fee, provided that the above copyright notice appear in - all copies and that both that the copyright notice and this - permission notice and warranty disclaimer appear in supporting - documentation, and that the name of the author not be used in - advertising or publicity pertaining to distribution of the - software without specific, written prior permission. - - The author disclaims all warranties with regard to this - software, including all implied warranties of merchantability - and fitness. In no event shall the author be liable for any - special, indirect or consequential damages or any damages - whatsoever resulting from loss of use, data or profits, whether - in an action of contract, negligence or other tortious action, - arising out of or in connection with the use or performance of - this software. -*/ -#if defined(USB0) -#define __INCLUDE_FROM_USB_DRIVER -#include <../../Core/USBMode.h> - -#if defined(USB_CAN_BE_DEVICE) - -#define __INCLUDE_FROM_HID_DRIVER -#define __INCLUDE_FROM_HID_DEVICE_C -#include - -void HID_Device_ProcessControlRequest(USB_ClassInfo_HID_Device_t* const HIDInterfaceInfo) -{ - if (!(Endpoint_IsSETUPReceived())) - return; - - if (USB_ControlRequest.wIndex != HIDInterfaceInfo->Config.InterfaceNumber) - return; - - switch (USB_ControlRequest.bRequest) - { - case HID_REQ_GetReport: - if (USB_ControlRequest.bmRequestType == (REQDIR_DEVICETOHOST | REQTYPE_CLASS | REQREC_INTERFACE)) - { - uint16_t ReportSize = 0; - uint8_t ReportID = (USB_ControlRequest.wValue & 0xFF); - uint8_t ReportType = (USB_ControlRequest.wValue >> 8) - 1; - uint8_t ReportData[HIDInterfaceInfo->Config.PrevReportINBufferSize]; - - memset(ReportData, 0, sizeof(ReportData)); - - //CALLBACK_HID_Device_CreateHIDReport(HIDInterfaceInfo, &ReportID, ReportType, ReportData, &ReportSize); - - if (HIDInterfaceInfo->Config.PrevReportINBuffer != NULL) - { - MEMCPY(HIDInterfaceInfo->Config.PrevReportINBuffer, ReportData, - HIDInterfaceInfo->Config.PrevReportINBufferSize); - } - - Endpoint_SelectEndpoint(ENDPOINT_CONTROLEP); - - Endpoint_ClearSETUP(); - - if (ReportID) - Endpoint_Write_8(ReportID); - - Endpoint_Write_Control_Stream_LE(ReportData, ReportSize); - Endpoint_ClearOUT(); - } - - break; - case HID_REQ_SetReport: - if (USB_ControlRequest.bmRequestType == (REQDIR_HOSTTODEVICE | REQTYPE_CLASS | REQREC_INTERFACE)) - { - uint16_t ReportSize = USB_ControlRequest.wLength; - uint8_t ReportID = (USB_ControlRequest.wValue & 0xFF); - uint8_t ReportType = (USB_ControlRequest.wValue >> 8) - 1; - uint8_t ReportData[ReportSize]; - - Endpoint_ClearSETUP(); - Endpoint_Read_Control_Stream_LE(ReportData, ReportSize); - Endpoint_ClearIN(); - - CALLBACK_HID_Device_ProcessHIDReport(HIDInterfaceInfo, ReportID, ReportType, - &ReportData[ReportID ? 1 : 0], ReportSize - (ReportID ? 1 : 0)); - } - - break; - case HID_REQ_GetProtocol: - if (USB_ControlRequest.bmRequestType == (REQDIR_DEVICETOHOST | REQTYPE_CLASS | REQREC_INTERFACE)) - { - Endpoint_ClearSETUP(); - while (!(Endpoint_IsINReady())); - Endpoint_Write_8(HIDInterfaceInfo->State.UsingReportProtocol); - Endpoint_ClearIN(); - Endpoint_ClearStatusStage(); - } - - break; - case HID_REQ_SetProtocol: - if (USB_ControlRequest.bmRequestType == (REQDIR_HOSTTODEVICE | REQTYPE_CLASS | REQREC_INTERFACE)) - { - Endpoint_ClearSETUP(); - Endpoint_ClearStatusStage(); - - HIDInterfaceInfo->State.UsingReportProtocol = ((USB_ControlRequest.wValue & 0xFF) != 0x00); - } - - break; - case HID_REQ_SetIdle: - if (USB_ControlRequest.bmRequestType == (REQDIR_HOSTTODEVICE | REQTYPE_CLASS | REQREC_INTERFACE)) - { - Endpoint_ClearSETUP(); - Endpoint_ClearStatusStage(); - - HIDInterfaceInfo->State.IdleCount = ((USB_ControlRequest.wValue & 0xFF00) >> 6); - } - - break; - case HID_REQ_GetIdle: - if (USB_ControlRequest.bmRequestType == (REQDIR_DEVICETOHOST | REQTYPE_CLASS | REQREC_INTERFACE)) - { - Endpoint_ClearSETUP(); - while (!(Endpoint_IsINReady())); - Endpoint_Write_8(HIDInterfaceInfo->State.IdleCount >> 2); - Endpoint_ClearIN(); - Endpoint_ClearStatusStage(); - } - - break; - } -} - -bool HID_Device_ConfigureEndpoints(USB_ClassInfo_HID_Device_t* const HIDInterfaceInfo) -{ - memset(&HIDInterfaceInfo->State, 0x00, sizeof(HIDInterfaceInfo->State)); - HIDInterfaceInfo->State.UsingReportProtocol = true; - HIDInterfaceInfo->State.IdleCount = 750; - - HIDInterfaceInfo->Config.ReportINEndpoint.Type = EP_TYPE_INTERRUPT; - - if (!(Endpoint_ConfigureEndpointTable(&HIDInterfaceInfo->Config.ReportINEndpoint, 1))) - return false; - - return true; -} -void HID_Device_USBTask(USB_ClassInfo_HID_Device_t* const HIDInterfaceInfo, int8_t _ReportINData[], uint8_t _ReportID, uint16_t _ReportINSize, bool ForceSend ) -//void HID_Device_USBTask(USB_ClassInfo_HID_Device_t* const HIDInterfaceInfo) -{ - if (USB_DeviceState != DEVICE_STATE_Configured) - return; - - if (HIDInterfaceInfo->State.PrevFrameNum == USB_Device_GetFrameNumber()) - { - #if defined(USB_DEVICE_OPT_LOWSPEED) - if (!(USB_Options & USB_DEVICE_OPT_LOWSPEED)) - return; - #else - return; - #endif - } - - Endpoint_SelectEndpoint(HIDInterfaceInfo->Config.ReportINEndpoint.Address); - - if (Endpoint_IsReadWriteAllowed()) - { - uint8_t ReportINData[HIDInterfaceInfo->Config.PrevReportINBufferSize]; - uint8_t ReportID =0;// _ReportID; - uint16_t ReportINSize =0;// _ReportINSize; - - memset(ReportINData, 0, sizeof(ReportINData)); - memcpy(ReportINData, _ReportINData, sizeof(ReportINData)); - - // ForceSend = CALLBACK_HID_Device_CreateHIDReport(HIDInterfaceInfo, &ReportID,HID_REPORT_ITEM_In, ReportINData, &ReportINSize); - ReportID = _ReportID; - ReportINSize = _ReportINSize; - bool StatesChanged = false; - bool IdlePeriodElapsed = (HIDInterfaceInfo->State.IdleCount && !(HIDInterfaceInfo->State.IdleMSRemaining)); - - if (HIDInterfaceInfo->Config.PrevReportINBuffer != NULL) - { - StatesChanged = (memcmp(ReportINData, HIDInterfaceInfo->Config.PrevReportINBuffer, ReportINSize) != 0); - MEMCPY(HIDInterfaceInfo->Config.PrevReportINBuffer, ReportINData, HIDInterfaceInfo->Config.PrevReportINBufferSize); - } - - if (ReportINSize && (ForceSend || StatesChanged || IdlePeriodElapsed)) - { - HIDInterfaceInfo->State.IdleMSRemaining = HIDInterfaceInfo->State.IdleCount; - - Endpoint_SelectEndpoint(HIDInterfaceInfo->Config.ReportINEndpoint.Address); - - if (ReportID) - Endpoint_Write_8(ReportID); - - Endpoint_Write_Stream_LE(ReportINData, ReportINSize, NULL); - - Endpoint_ClearIN(); - } - - HIDInterfaceInfo->State.PrevFrameNum = USB_Device_GetFrameNumber(); - } -} - -#endif -#endif - -#endif /* UC_FAMILY == XMC4 */ diff --git a/cores/usblib/Class/Device/HIDClassDevice.h b/cores/usblib/Class/Device/HIDClassDevice.h deleted file mode 100644 index 345d09b3..00000000 --- a/cores/usblib/Class/Device/HIDClassDevice.h +++ /dev/null @@ -1,213 +0,0 @@ -#ifdef XMC4_SERIES - -/* - LUFA Library - Copyright (C) Dean Camera, 2014. - - dean [at] fourwalledcubicle [dot] com - www.lufa-lib.org -*/ - -/* - Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com) - - Permission to use, copy, modify, distribute, and sell this - software and its documentation for any purpose is hereby granted - without fee, provided that the above copyright notice appear in - all copies and that both that the copyright notice and this - permission notice and warranty disclaimer appear in supporting - documentation, and that the name of the author not be used in - advertising or publicity pertaining to distribution of the - software without specific, written prior permission. - - The author disclaims all warranties with regard to this - software, including all implied warranties of merchantability - and fitness. In no event shall the author be liable for any - special, indirect or consequential damages or any damages - whatsoever resulting from loss of use, data or profits, whether - in an action of contract, negligence or other tortious action, - arising out of or in connection with the use or performance of - this software. -*/ - -/** \file - * \brief Device mode driver for the library USB HID Class driver. - * - * Device mode driver for the library USB HID Class driver. - * - * \note This file should not be included directly. It is automatically included as needed by the USB module driver - * dispatch header located in LUFA/Drivers/USB.h. - */ - -/** \ingroup Group_USBClassHID - * \defgroup Group_USBClassHIDDevice HID Class Device Mode Driver - * - * \section Sec_USBClassHIDDevice_Dependencies Module Source Dependencies - * The following files must be built with any user project that uses this module: - * - LUFA/Drivers/USB/Class/Device/HIDClassDevice.c (Makefile source module name: LUFA_SRC_USBCLASS) - * - * \section Sec_USBClassHIDDevice_ModDescription Module Description - * Device Mode USB Class driver framework interface, for the HID USB Class driver. - * - * @{ - */ - -#ifndef _HID_CLASS_DEVICE_H_ -#define _HID_CLASS_DEVICE_H_ -#if defined(USB0) - /* Includes: */ - #include <../../usblib.h> - #include <../Common/HIDClassCommon.h> - /* Enable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - extern "C" { - #endif - - /* Preprocessor Checks: */ - #if !defined(__INCLUDE_FROM_HID_DRIVER) - #error Do not include this file directly. Include LUFA/Drivers/USB.h instead. - #endif - /* Public Interface - May be used in end-application: */ - /* Type Defines: */ - /** \brief HID Class Device Mode Configuration and State Structure. - * - * Class state structure. An instance of this structure should be made for each HID interface - * within the user application, and passed to each of the HID class driver functions as the - * \c HIDInterfaceInfo parameter. This stores each HID interface's configuration and state information. - * - * \note Due to technical limitations, the HID device class driver does not utilize a separate OUT - * endpoint for host->device communications. Instead, the host->device data (if any) is sent to - * the device via the control endpoint. - */ - typedef struct - { - struct - { - uint8_t InterfaceNumber; /**< Interface number of the HID interface within the device. */ - - USB_Endpoint_Table_t ReportINEndpoint; /**< Data IN HID report endpoint configuration table. */ - - void* PrevReportINBuffer; /**< Pointer to a buffer where the previously created HID input report can be - * stored by the driver, for comparison purposes to detect report changes that - * must be sent immediately to the host. This should point to a buffer big enough - * to hold the largest HID input report sent from the HID interface. If this is set - * to \c NULL, it is up to the user to force transfers when needed in the - * \ref CALLBACK_HID_Device_CreateHIDReport() callback function. - * - * \note Due to the single buffer, the internal driver can only correctly compare - * subsequent reports with identical report IDs. In multiple report devices, - * this buffer should be set to \c NULL and the decision to send reports made - * by the user application instead. - */ - uint8_t PrevReportINBufferSize; /**< Size in bytes of the given input report buffer. This is used to create a - * second buffer of the same size within the driver so that subsequent reports - * can be compared. If the user app is to determine when reports are to be sent - * exclusively (i.e. \c PrevReportINBuffer is \c NULL) this value must still be - * set to the size of the largest report the device can issue to the host. - */ - } Config; /**< Config data for the USB class interface within the device. All elements in this section - * must be set or the interface will fail to enumerate and operate correctly. - */ - struct - { - bool UsingReportProtocol; /**< Indicates if the HID interface is set to Boot or Report protocol mode. */ - uint16_t PrevFrameNum; /**< Frame number of the previous HID report packet opportunity. */ - uint16_t IdleCount; /**< Report idle period, in milliseconds, set by the host. */ - uint16_t IdleMSRemaining; /**< Total number of milliseconds remaining before the idle period elapsed - this - * should be decremented by the user application if non-zero each millisecond. */ - } State; /**< State data for the USB class interface within the device. All elements in this section - * are reset to their defaults when the interface is enumerated. - */ - } USB_ClassInfo_HID_Device_t; - - /* Function Prototypes: */ - /** Configures the endpoints of a given HID interface, ready for use. This should be linked to the library - * \ref EVENT_USB_Device_ConfigurationChanged() event so that the endpoints are configured when the configuration - * containing the given HID interface is selected. - * - * \param[in,out] HIDInterfaceInfo Pointer to a structure containing a HID Class configuration and state. - * - * \return Boolean \c true if the endpoints were successfully configured, \c false otherwise. - */ - bool HID_Device_ConfigureEndpoints(USB_ClassInfo_HID_Device_t* const HIDInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1); - - /** Processes incoming control requests from the host, that are directed to the given HID class interface. This should be - * linked to the library \ref EVENT_USB_Device_ControlRequest() event. - * - * \param[in,out] HIDInterfaceInfo Pointer to a structure containing a HID Class configuration and state. - */ - void HID_Device_ProcessControlRequest(USB_ClassInfo_HID_Device_t* const HIDInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1); - - /** General management task for a given HID class interface, required for the correct operation of the interface. This should - * be called frequently in the main program loop, before the master USB management task \ref USB_USBTask(). - * - * \param[in,out] HIDInterfaceInfo Pointer to a structure containing a HID Class configuration and state. - */ - void HID_Device_USBTask(USB_ClassInfo_HID_Device_t* const HIDInterfaceInfo, int8_t _ReportINData[], uint8_t _ReportID, uint16_t _ReportINSize, bool ForceSend ) ATTR_NON_NULL_PTR_ARG(1); - - //void HID_Device_USBTask(USB_ClassInfo_HID_Device_t* const HIDInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1); - - /** HID class driver callback for the user creation of a HID IN report. This callback may fire in response to either - * HID class control requests from the host, or by the normal HID endpoint polling procedure. Inside this callback the - * user is responsible for the creation of the next HID input report to be sent to the host. - * - * \param[in,out] HIDInterfaceInfo Pointer to a structure containing a HID Class configuration and state. - * \param[in,out] ReportID If preset to a non-zero value, this is the report ID being requested by the host. If zero, - * this should be set to the report ID of the generated HID input report (if any). If multiple - * reports are not sent via the given HID interface, this parameter should be ignored. - * \param[in] ReportType Type of HID report to generate, either \ref HID_REPORT_ITEM_In or \ref HID_REPORT_ITEM_Feature. - * \param[out] ReportData Pointer to a buffer where the generated HID report should be stored. - * \param[out] ReportSize Number of bytes in the generated input report, or zero if no report is to be sent. - * - * \return Boolean \c true to force the sending of the report even if it is identical to the previous report and still within - * the idle period (useful for devices which report relative movement), \c false otherwise. - */ - bool CALLBACK_HID_Device_CreateHIDReport(USB_ClassInfo_HID_Device_t* const HIDInterfaceInfo, - uint8_t* const ReportID, - const uint8_t ReportType, - void* ReportData, - uint16_t* const ReportSize) ATTR_NON_NULL_PTR_ARG(1) - ATTR_NON_NULL_PTR_ARG(2) ATTR_NON_NULL_PTR_ARG(4) ATTR_NON_NULL_PTR_ARG(5); - - /** HID class driver callback for the user processing of a received HID OUT report. This callback may fire in response to - * either HID class control requests from the host, or by the normal HID endpoint polling procedure. Inside this callback - * the user is responsible for the processing of the received HID output report from the host. - * - * \param[in,out] HIDInterfaceInfo Pointer to a structure containing a HID Class configuration and state. - * \param[in] ReportID Report ID of the received output report. If multiple reports are not received via the given HID - * interface, this parameter should be ignored. - * \param[in] ReportType Type of received HID report, either \ref HID_REPORT_ITEM_Out or \ref HID_REPORT_ITEM_Feature. - * \param[in] ReportData Pointer to a buffer where the received HID report is stored. - * \param[in] ReportSize Size in bytes of the received report from the host. - */ - void CALLBACK_HID_Device_ProcessHIDReport(USB_ClassInfo_HID_Device_t* const HIDInterfaceInfo, - const uint8_t ReportID, - const uint8_t ReportType, - const void* ReportData, - const uint16_t ReportSize) ATTR_NON_NULL_PTR_ARG(1) ATTR_NON_NULL_PTR_ARG(4); - - /* Inline Functions: */ - /** Indicates that a millisecond of idle time has elapsed on the given HID interface, and the interface's idle count should be - * decremented. This should be called once per millisecond so that hardware key-repeats function correctly. It is recommended - * that this be called by the \ref EVENT_USB_Device_StartOfFrame() event, once SOF events have been enabled via - * \ref USB_Device_EnableSOFEvents(). - * - * \param[in,out] HIDInterfaceInfo Pointer to a structure containing a HID Class configuration and state. - */ - static inline void HID_Device_MillisecondElapsed(USB_ClassInfo_HID_Device_t* const HIDInterfaceInfo) ATTR_ALWAYS_INLINE ATTR_NON_NULL_PTR_ARG(1); - static inline void HID_Device_MillisecondElapsed(USB_ClassInfo_HID_Device_t* const HIDInterfaceInfo) - { - if (HIDInterfaceInfo->State.IdleMSRemaining) - HIDInterfaceInfo->State.IdleMSRemaining--; - } - - /* Disable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - } - #endif -#endif -#endif -/** @} */ - - -#endif /* UC_FAMILY == XMC4 */ diff --git a/cores/usblib/Class/Device/MassStorageClassDevice.c b/cores/usblib/Class/Device/MassStorageClassDevice.c deleted file mode 100644 index 1a39ef60..00000000 --- a/cores/usblib/Class/Device/MassStorageClassDevice.c +++ /dev/null @@ -1,220 +0,0 @@ -#ifdef XMC4_SERIES - -/* - LUFA Library - Copyright (C) Dean Camera, 2014. - - dean [at] fourwalledcubicle [dot] com - www.lufa-lib.org -*/ - -/* - Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com) - - Permission to use, copy, modify, distribute, and sell this - software and its documentation for any purpose is hereby granted - without fee, provided that the above copyright notice appear in - all copies and that both that the copyright notice and this - permission notice and warranty disclaimer appear in supporting - documentation, and that the name of the author not be used in - advertising or publicity pertaining to distribution of the - software without specific, written prior permission. - - The author disclaims all warranties with regard to this - software, including all implied warranties of merchantability - and fitness. In no event shall the author be liable for any - special, indirect or consequential damages or any damages - whatsoever resulting from loss of use, data or profits, whether - in an action of contract, negligence or other tortious action, - arising out of or in connection with the use or performance of - this software. -*/ -#if defined(USB0) -#define __INCLUDE_FROM_USB_DRIVER -#include <../../Core/USBMode.h> - -#if defined(USB_CAN_BE_DEVICE) - -#define __INCLUDE_FROM_MS_DRIVER -#define __INCLUDE_FROM_MASSSTORAGE_DEVICE_C -#define INTERRUPT_CONTROL_ENDPOINT -#include - -void MS_Device_ProcessControlRequest(USB_ClassInfo_MS_Device_t* const MSInterfaceInfo) -{ - if (!(Endpoint_IsSETUPReceived())) - return; - - if (USB_ControlRequest.wIndex != MSInterfaceInfo->Config.InterfaceNumber) - return; - - switch (USB_ControlRequest.bRequest) - { - case MS_REQ_MassStorageReset: - if (USB_ControlRequest.bmRequestType == (REQDIR_HOSTTODEVICE | REQTYPE_CLASS | REQREC_INTERFACE)) - { - Endpoint_ClearSETUP(); - Endpoint_ClearStatusStage(); - - MSInterfaceInfo->State.IsMassStoreReset = true; - } - - break; - case MS_REQ_GetMaxLUN: - if (USB_ControlRequest.bmRequestType == (REQDIR_DEVICETOHOST | REQTYPE_CLASS | REQREC_INTERFACE)) - { - Endpoint_ClearSETUP(); - while (!(Endpoint_IsINReady())); - Endpoint_Write_8(MSInterfaceInfo->Config.TotalLUNs - 1); - Endpoint_ClearIN(); - Endpoint_ClearStatusStage(); - } - - break; - } -} - -bool MS_Device_ConfigureEndpoints(USB_ClassInfo_MS_Device_t* const MSInterfaceInfo) -{ - memset(&MSInterfaceInfo->State, 0x00, sizeof(MSInterfaceInfo->State)); - - MSInterfaceInfo->Config.DataINEndpoint.Type = EP_TYPE_BULK; - MSInterfaceInfo->Config.DataOUTEndpoint.Type = EP_TYPE_BULK; - - if (!(Endpoint_ConfigureEndpointTable(&MSInterfaceInfo->Config.DataINEndpoint, 1))) - return false; - - if (!(Endpoint_ConfigureEndpointTable(&MSInterfaceInfo->Config.DataOUTEndpoint, 1))) - return false; - - return true; -} - -void MS_Device_USBTask(USB_ClassInfo_MS_Device_t* const MSInterfaceInfo) -{ - if (USB_DeviceState != DEVICE_STATE_Configured) - return; - - Endpoint_SelectEndpoint(MSInterfaceInfo->Config.DataOUTEndpoint.Address); - - if (Endpoint_IsOUTReceived()) - { - if (MS_Device_ReadInCommandBlock(MSInterfaceInfo)) - { - if (MSInterfaceInfo->State.CommandBlock.Flags & MS_COMMAND_DIR_DATA_IN) - Endpoint_SelectEndpoint(MSInterfaceInfo->Config.DataINEndpoint.Address); - - bool SCSICommandResult = CALLBACK_MS_Device_SCSICommandReceived(MSInterfaceInfo); - - MSInterfaceInfo->State.CommandStatus.Status = (SCSICommandResult) ? MS_SCSI_COMMAND_Pass : MS_SCSI_COMMAND_Fail; - MSInterfaceInfo->State.CommandStatus.Signature = CPU_TO_LE32(MS_CSW_SIGNATURE); - MSInterfaceInfo->State.CommandStatus.Tag = MSInterfaceInfo->State.CommandBlock.Tag; - MSInterfaceInfo->State.CommandStatus.DataTransferResidue = MSInterfaceInfo->State.CommandBlock.DataTransferLength; - - if (!(SCSICommandResult) && (le32_to_cpu(MSInterfaceInfo->State.CommandStatus.DataTransferResidue))) - Endpoint_StallTransaction(); - - MS_Device_ReturnCommandStatus(MSInterfaceInfo); - } - } - - if (MSInterfaceInfo->State.IsMassStoreReset) - { - Endpoint_ResetEndpoint(MSInterfaceInfo->Config.DataOUTEndpoint.Address); - Endpoint_ResetEndpoint(MSInterfaceInfo->Config.DataINEndpoint.Address); - - Endpoint_SelectEndpoint(MSInterfaceInfo->Config.DataOUTEndpoint.Address); - Endpoint_ClearStall(); - Endpoint_ResetDataToggle(); - Endpoint_SelectEndpoint(MSInterfaceInfo->Config.DataINEndpoint.Address); - Endpoint_ClearStall(); - Endpoint_ResetDataToggle(); - - MSInterfaceInfo->State.IsMassStoreReset = false; - } -} - -static bool MS_Device_ReadInCommandBlock(USB_ClassInfo_MS_Device_t* const MSInterfaceInfo) -{ - uint16_t BytesProcessed; - - Endpoint_SelectEndpoint(MSInterfaceInfo->Config.DataOUTEndpoint.Address); - - BytesProcessed = 0; - while (Endpoint_Read_Stream_LE(&MSInterfaceInfo->State.CommandBlock, - (sizeof(MS_CommandBlockWrapper_t) - 16), &BytesProcessed) == - ENDPOINT_RWSTREAM_IncompleteTransfer) - { - if (MSInterfaceInfo->State.IsMassStoreReset) - return false; - } - - if ((MSInterfaceInfo->State.CommandBlock.Signature != CPU_TO_LE32(MS_CBW_SIGNATURE)) || - (MSInterfaceInfo->State.CommandBlock.LUN >= MSInterfaceInfo->Config.TotalLUNs) || - (MSInterfaceInfo->State.CommandBlock.Flags & 0x1F) || - (MSInterfaceInfo->State.CommandBlock.SCSICommandLength == 0) || - (MSInterfaceInfo->State.CommandBlock.SCSICommandLength > 16)) - { - Endpoint_StallTransaction(); - Endpoint_SelectEndpoint(MSInterfaceInfo->Config.DataINEndpoint.Address); - Endpoint_StallTransaction(); - - return false; - } - - BytesProcessed = 0; - while (Endpoint_Read_Stream_LE(&MSInterfaceInfo->State.CommandBlock.SCSICommandData, - MSInterfaceInfo->State.CommandBlock.SCSICommandLength, &BytesProcessed) == - ENDPOINT_RWSTREAM_IncompleteTransfer) - { - if (MSInterfaceInfo->State.IsMassStoreReset) - return false; - } - - Endpoint_ClearOUT(); - - return true; -} - -static void MS_Device_ReturnCommandStatus(USB_ClassInfo_MS_Device_t* const MSInterfaceInfo) -{ - Endpoint_SelectEndpoint(MSInterfaceInfo->Config.DataOUTEndpoint.Address); - - while (Endpoint_IsStalled()) - { - #if !defined(INTERRUPT_CONTROL_ENDPOINT) - USB_USBTask(); - #endif - - if (MSInterfaceInfo->State.IsMassStoreReset) - return; - } - - Endpoint_SelectEndpoint(MSInterfaceInfo->Config.DataINEndpoint.Address); - - while (Endpoint_IsStalled()) - { - #if !defined(INTERRUPT_CONTROL_ENDPOINT) - USB_USBTask(); - #endif - - if (MSInterfaceInfo->State.IsMassStoreReset) - return; - } - - uint16_t BytesProcessed = 0; - while (Endpoint_Write_Stream_LE(&MSInterfaceInfo->State.CommandStatus, - sizeof(MS_CommandStatusWrapper_t), &BytesProcessed) == - ENDPOINT_RWSTREAM_IncompleteTransfer) - { - if (MSInterfaceInfo->State.IsMassStoreReset) - return; - } - - Endpoint_ClearIN(); -} -#endif -#endif - - -#endif /* UC_FAMILY == XMC4 */ diff --git a/cores/usblib/Class/Device/MassStorageClassDevice.h b/cores/usblib/Class/Device/MassStorageClassDevice.h deleted file mode 100644 index 81f0d13e..00000000 --- a/cores/usblib/Class/Device/MassStorageClassDevice.h +++ /dev/null @@ -1,165 +0,0 @@ -#ifdef XMC4_SERIES - -/* - LUFA Library - Copyright (C) Dean Camera, 2014. - - dean [at] fourwalledcubicle [dot] com - www.lufa-lib.org -*/ - -/* - Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com) - - Permission to use, copy, modify, distribute, and sell this - software and its documentation for any purpose is hereby granted - without fee, provided that the above copyright notice appear in - all copies and that both that the copyright notice and this - permission notice and warranty disclaimer appear in supporting - documentation, and that the name of the author not be used in - advertising or publicity pertaining to distribution of the - software without specific, written prior permission. - - The author disclaims all warranties with regard to this - software, including all implied warranties of merchantability - and fitness. In no event shall the author be liable for any - special, indirect or consequential damages or any damages - whatsoever resulting from loss of use, data or profits, whether - in an action of contract, negligence or other tortious action, - arising out of or in connection with the use or performance of - this software. -*/ - -/** \file - * \brief Device mode driver for the library USB Mass Storage Class driver. - * - * Device mode driver for the library USB Mass Storage Class driver. - * - * \note This file should not be included directly. It is automatically included as needed by the USB module driver - * dispatch header located in LUFA/Drivers/USB.h. - */ - -/** \ingroup Group_USBClassMS - * \defgroup Group_USBClassMSDevice Mass Storage Class Device Mode Driver - * - * \section Sec_USBClassMSDevice_Dependencies Module Source Dependencies - * The following files must be built with any user project that uses this module: - * - LUFA/Drivers/USB/Class/Device/MassStorageClassDevice.c (Makefile source module name: LUFA_SRC_USBCLASS) - * - * \section Sec_USBClassMSDevice_ModDescription Module Description - * Device Mode USB Class driver framework interface, for the Mass Storage USB Class driver. - * - * @{ - */ - -#ifndef _MS_CLASS_DEVICE_H_ -#define _MS_CLASS_DEVICE_H_ -#if defined(USB0) - /* Includes: */ - #include <../../usblib.h> - #include <../Common/MassStorageClassCommon.h> - - /* Enable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - extern "C" { - #endif - - /* Preprocessor Checks: */ - #if !defined(__INCLUDE_FROM_MS_DRIVER) - #error Do not include this file directly. Include LUFA/Drivers/USB.h instead. - #endif - - /* Public Interface - May be used in end-application: */ - /* Type Defines: */ - /** \brief Mass Storage Class Device Mode Configuration and State Structure. - * - * Class state structure. An instance of this structure should be made for each Mass Storage interface - * within the user application, and passed to each of the Mass Storage class driver functions as the - * \c MSInterfaceInfo parameter. This stores each Mass Storage interface's configuration and state information. - */ - typedef struct - { - struct - { - uint8_t InterfaceNumber; /**< Interface number of the Mass Storage interface within the device. */ - - USB_Endpoint_Table_t DataINEndpoint; /**< Data IN endpoint configuration table. */ - USB_Endpoint_Table_t DataOUTEndpoint; /**< Data OUT endpoint configuration table. */ - - uint8_t TotalLUNs; /**< Total number of logical drives in the Mass Storage interface. */ - } Config; /**< Config data for the USB class interface within the device. All elements in this section - * must be set or the interface will fail to enumerate and operate correctly. - */ - struct - { - MS_CommandBlockWrapper_t CommandBlock; /**< Mass Storage class command block structure, stores the received SCSI - * command from the host which is to be processed. - */ - MS_CommandStatusWrapper_t CommandStatus; /**< Mass Storage class command status structure, set elements to indicate - * the issued command's success or failure to the host. - */ - volatile bool IsMassStoreReset; /**< Flag indicating that the host has requested that the Mass Storage interface be reset - * and that all current Mass Storage operations should immediately abort. - */ - } State; /**< State data for the USB class interface within the device. All elements in this section - * are reset to their defaults when the interface is enumerated. - */ - } USB_ClassInfo_MS_Device_t; - - /* Function Prototypes: */ - /** Configures the endpoints of a given Mass Storage interface, ready for use. This should be linked to the library - * \ref EVENT_USB_Device_ConfigurationChanged() event so that the endpoints are configured when the configuration - * containing the given Mass Storage interface is selected. - * - * \param[in,out] MSInterfaceInfo Pointer to a structure containing a Mass Storage Class configuration and state. - * - * \return Boolean \c true if the endpoints were successfully configured, \c false otherwise. - */ - bool MS_Device_ConfigureEndpoints(USB_ClassInfo_MS_Device_t* const MSInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1); - - /** Processes incoming control requests from the host, that are directed to the given Mass Storage class interface. This should be - * linked to the library \ref EVENT_USB_Device_ControlRequest() event. - * - * \param[in,out] MSInterfaceInfo Pointer to a structure containing a Mass Storage Class configuration and state. - */ - void MS_Device_ProcessControlRequest(USB_ClassInfo_MS_Device_t* const MSInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1); - - /** General management task for a given Mass Storage class interface, required for the correct operation of the interface. This should - * be called frequently in the main program loop, before the master USB management task \ref USB_USBTask(). - * - * \param[in,out] MSInterfaceInfo Pointer to a structure containing a Mass Storage configuration and state. - */ - void MS_Device_USBTask(USB_ClassInfo_MS_Device_t* const MSInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1); - - /** Mass Storage class driver callback for the user processing of a received SCSI command. This callback will fire each time the - * host sends a SCSI command which requires processing by the user application. Inside this callback the user is responsible - * for the processing of the received SCSI command from the host. The SCSI command is available in the CommandBlock structure - * inside the Mass Storage class state structure passed as a parameter to the callback function. - * - * \param[in,out] MSInterfaceInfo Pointer to a structure containing a Mass Storage Class configuration and state. - * - * \return Boolean \c true if the SCSI command was successfully processed, \c false otherwise. - */ - bool CALLBACK_MS_Device_SCSICommandReceived(USB_ClassInfo_MS_Device_t* const MSInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1); - - /* Private Interface - For use in library only: */ - #if !defined(__DOXYGEN__) - /* Function Prototypes: */ - #if defined(__INCLUDE_FROM_MASSSTORAGE_DEVICE_C) - static void MS_Device_ReturnCommandStatus(USB_ClassInfo_MS_Device_t* const MSInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1); - static bool MS_Device_ReadInCommandBlock(USB_ClassInfo_MS_Device_t* const MSInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1); - #endif - - #endif - - /* Disable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - } - #endif - -#endif -#endif -/** @} */ - - -#endif /* UC_FAMILY == XMC4 */ diff --git a/cores/usblib/Class/HIDClass.h b/cores/usblib/Class/HIDClass.h deleted file mode 100644 index df0451e2..00000000 --- a/cores/usblib/Class/HIDClass.h +++ /dev/null @@ -1,86 +0,0 @@ -#ifdef XMC4_SERIES - -/* - LUFA Library - Copyright (C) Dean Camera, 2014. - - dean [at] fourwalledcubicle [dot] com - www.lufa-lib.org -*/ - -/* - Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com) - - Permission to use, copy, modify, distribute, and sell this - software and its documentation for any purpose is hereby granted - without fee, provided that the above copyright notice appear in - all copies and that both that the copyright notice and this - permission notice and warranty disclaimer appear in supporting - documentation, and that the name of the author not be used in - advertising or publicity pertaining to distribution of the - software without specific, written prior permission. - - The author disclaims all warranties with regard to this - software, including all implied warranties of merchantability - and fitness. In no event shall the author be liable for any - special, indirect or consequential damages or any damages - whatsoever resulting from loss of use, data or profits, whether - in an action of contract, negligence or other tortious action, - arising out of or in connection with the use or performance of - this software. -*/ - -/** \file - * \brief Master include file for the library USB HID Class driver. - * - * Master include file for the library USB HID Class driver, for both host and device modes, where available. - * - * This file should be included in all user projects making use of this optional class driver, instead of - * including any headers in the USB/ClassDriver/Device, USB/ClassDriver/Host or USB/ClassDriver/Common subdirectories. - */ - -/** \ingroup Group_USBClassDrivers - * \defgroup Group_USBClassHID HID Class Driver - * \brief USB class driver for the USB-IF Human Interface Device (HID) class standard. - * - * \section Sec_USBClassHID_Dependencies Module Source Dependencies - * The following files must be built with any user project that uses this module: - * - LUFA/Drivers/USB/Class/Device/HIDClassDevice.c (Makefile source module name: LUFA_SRC_USBCLASS) - * - LUFA/Drivers/USB/Class/Host/HIDClassHost.c (Makefile source module name: LUFA_SRC_USBCLASS) - * - LUFA/Drivers/USB/Class/Host/HIDParser.c (Makefile source module name: LUFA_SRC_USB) - * - * \section Sec_USBClassHID_ModDescription Module Description - * HID Class Driver module. This module contains an internal implementation of the USB HID Class, for both Device - * and Host USB modes. User applications can use this class driver instead of implementing the HID class manually - * via the low-level LUFA APIs. - * - * This module is designed to simplify the user code by exposing only the required interface needed to interface with - * Hosts or Devices using the USB HID Class. - * - * @{ - */ - -#ifndef _HID_CLASS_H_ -#define _HID_CLASS_H_ -#if defined(USB0) - /* Macros: */ - #define __INCLUDE_FROM_USB_DRIVER - #define __INCLUDE_FROM_HID_DRIVER - - /* Includes: */ - #include <../Core/USBMode.h> - - #if defined(USB_CAN_BE_DEVICE) - #include - #endif - - #if defined(USB_CAN_BE_HOST) - #include - #endif - -#endif -#endif -/** @} */ - - -#endif /* UC_FAMILY == XMC4 */ diff --git a/cores/usblib/Class/MassStorageClass.h b/cores/usblib/Class/MassStorageClass.h deleted file mode 100644 index 15513a8a..00000000 --- a/cores/usblib/Class/MassStorageClass.h +++ /dev/null @@ -1,85 +0,0 @@ -#ifdef XMC4_SERIES - -/* - LUFA Library - Copyright (C) Dean Camera, 2014. - - dean [at] fourwalledcubicle [dot] com - www.lufa-lib.org -*/ - -/* - Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com) - - Permission to use, copy, modify, distribute, and sell this - software and its documentation for any purpose is hereby granted - without fee, provided that the above copyright notice appear in - all copies and that both that the copyright notice and this - permission notice and warranty disclaimer appear in supporting - documentation, and that the name of the author not be used in - advertising or publicity pertaining to distribution of the - software without specific, written prior permission. - - The author disclaims all warranties with regard to this - software, including all implied warranties of merchantability - and fitness. In no event shall the author be liable for any - special, indirect or consequential damages or any damages - whatsoever resulting from loss of use, data or profits, whether - in an action of contract, negligence or other tortious action, - arising out of or in connection with the use or performance of - this software. -*/ - -/** \file - * \brief Master include file for the library USB Mass Storage Class driver. - * - * Master include file for the library USB Mass Storage Class driver, for both host and device modes, where available. - * - * This file should be included in all user projects making use of this optional class driver, instead of - * including any headers in the USB/ClassDriver/Device, USB/ClassDriver/Host or USB/ClassDriver/Common subdirectories. - */ - -/** \ingroup Group_USBClassDrivers - * \defgroup Group_USBClassMS Mass Storage Class Driver - * \brief USB class driver for the USB-IF Bulk-Only Transport Mass Storage class standard. - * - * \section Sec_USBClassMS_Dependencies Module Source Dependencies - * The following files must be built with any user project that uses this module: - * - LUFA/Drivers/USB/Class/Device/MassStorageClassDevice.c (Makefile source module name: LUFA_SRC_USBCLASS) - * - LUFA/Drivers/USB/Class/Host/MassStorageClassHost.c (Makefile source module name: LUFA_SRC_USBCLASS) - * - * \section Sec_USBClassMS_ModDescription Module Description - * Mass Storage Class Driver module. This module contains an internal implementation of the USB Mass Storage Class, for both - * Device and Host USB modes. User applications can use this class driver instead of implementing the Mass Storage class - * manually via the low-level LUFA APIs. - * - * This module is designed to simplify the user code by exposing only the required interface needed to interface with - * Hosts or Devices using the USB Mass Storage Class. - * - * @{ - */ - -#ifndef _MS_CLASS_H_ -#define _MS_CLASS_H_ -#if defined(USB0) - /* Macros: */ - #define __INCLUDE_FROM_USB_DRIVER - #define __INCLUDE_FROM_MS_DRIVER - - /* Includes: */ - #include <../Core/USBMode.h> - - #if defined(USB_CAN_BE_DEVICE) - #include - #endif - - #if defined(USB_CAN_BE_HOST) - #include - #endif - -#endif -#endif -/** @} */ - - -#endif /* UC_FAMILY == XMC4 */ diff --git a/cores/usblib/Common/ArchitectureSpecific.h b/cores/usblib/Common/ArchitectureSpecific.h deleted file mode 100644 index b808cdfd..00000000 --- a/cores/usblib/Common/ArchitectureSpecific.h +++ /dev/null @@ -1,79 +0,0 @@ -#ifdef XMC4_SERIES - -/* - LUFA Library - Copyright (C) Dean Camera, 2014. - - dean [at] fourwalledcubicle [dot] com - www.lufa-lib.org -*/ - -/* - Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com) - - Permission to use, copy, modify, distribute, and sell this - software and its documentation for any purpose is hereby granted - without fee, provided that the above copyright notice appear in - all copies and that both that the copyright notice and this - permission notice and warranty disclaimer appear in supporting - documentation, and that the name of the author not be used in - advertising or publicity pertaining to distribution of the - software without specific, written prior permission. - - The author disclaims all warranties with regard to this - software, including all implied warranties of merchantability - and fitness. In no event shall the author be liable for any - special, indirect or consequential damages or any damages - whatsoever resulting from loss of use, data or profits, whether - in an action of contract, negligence or other tortious action, - arising out of or in connection with the use or performance of - this software. -*/ - -/** \file - * \brief Architecture specific definitions relating to specific processor architectures. - * - * \copydetails Group_ArchitectureSpecific - * - * \note Do not include this file directly, rather include the Common.h header file instead to gain this file's - * functionality. - */ - -/** \ingroup Group_Common - * \defgroup Group_ArchitectureSpecific Architecture Specific Definitions - * \brief Architecture specific definitions relating to specific processor architectures. - * - * Architecture specific macros, functions and other definitions, which relate to specific architectures. This - * definitions may or may not be available in some form on other architectures, and thus should be protected by - * preprocessor checks in portable code to prevent compile errors. - * - * @{ - */ - -#ifndef __LUFA_ARCHSPEC_H__ -#define __LUFA_ARCHSPEC_H__ - - /* Preprocessor Checks: */ - #if !defined(__INCLUDE_FROM_COMMON_H) - #error Do not include this file directly. Include LUFA/Common/Common.h instead to gain this functionality. - #endif - - /* Enable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - extern "C" { - #endif - - /* Public Interface - May be used in end-application: */ - /* Macros: */ - - /* Disable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - } - #endif - -#endif - -/** @} */ - - -#endif /* UC_FAMILY == XMC4 */ diff --git a/cores/usblib/Common/Architectures.h b/cores/usblib/Common/Architectures.h deleted file mode 100644 index 048c649b..00000000 --- a/cores/usblib/Common/Architectures.h +++ /dev/null @@ -1,72 +0,0 @@ -#ifdef XMC4_SERIES - -/* - LUFA Library - Copyright (C) Dean Camera, 2014. - - dean [at] fourwalledcubicle [dot] com - www.lufa-lib.org -*/ - -/* - Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com) - - Permission to use, copy, modify, distribute, and sell this - software and its documentation for any purpose is hereby granted - without fee, provided that the above copyright notice appear in - all copies and that both that the copyright notice and this - permission notice and warranty disclaimer appear in supporting - documentation, and that the name of the author not be used in - advertising or publicity pertaining to distribution of the - software without specific, written prior permission. - - The author disclaims all warranties with regard to this - software, including all implied warranties of merchantability - and fitness. In no event shall the author be liable for any - special, indirect or consequential damages or any damages - whatsoever resulting from loss of use, data or profits, whether - in an action of contract, negligence or other tortious action, - arising out of or in connection with the use or performance of - this software. -*/ - -/** \file - * \brief Supported library architecture defines. - * - * \copydetails Group_Architectures - * - * \note Do not include this file directly, rather include the Common.h header file instead to gain this file's - * functionality. - */ - -/** \ingroup Group_Common - * \defgroup Group_Architectures Hardware Architectures - * \brief Supported library architecture defines. - * - * Architecture macros for selecting the desired target microcontroller architecture. One of these values should be - * defined as the value of \c ARCH in the user project makefile via the \c -D compiler switch to GCC, to select the - * target architecture. - * - * The selected architecture should remain consistent with the makefile \c ARCH value, which is used to select the - * underlying driver source files for each architecture. - * - * @{ - */ - -#ifndef __LUFA_ARCHITECTURES_H__ -#define __LUFA_ARCHITECTURES_H__ - - /* Preprocessor Checks: */ - #if !defined(__INCLUDE_FROM_COMMON_H) - #error Do not include this file directly. Include LUFA/Common/Common.h instead to gain this functionality. - #endif - - /* Public Interface - May be used in end-application: */ - /* Macros: */ - -#endif - -/** @} */ - - -#endif /* UC_FAMILY == XMC4 */ diff --git a/cores/usblib/Common/Attributes.h b/cores/usblib/Common/Attributes.h deleted file mode 100644 index 8237ce0d..00000000 --- a/cores/usblib/Common/Attributes.h +++ /dev/null @@ -1,208 +0,0 @@ -#ifdef XMC4_SERIES - -/* - LUFA Library - Copyright (C) Dean Camera, 2014. - - dean [at] fourwalledcubicle [dot] com - www.lufa-lib.org -*/ - -/* - Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com) - - Permission to use, copy, modify, distribute, and sell this - software and its documentation for any purpose is hereby granted - without fee, provided that the above copyright notice appear in - all copies and that both that the copyright notice and this - permission notice and warranty disclaimer appear in supporting - documentation, and that the name of the author not be used in - advertising or publicity pertaining to distribution of the - software without specific, written prior permission. - - The author disclaims all warranties with regard to this - software, including all implied warranties of merchantability - and fitness. In no event shall the author be liable for any - special, indirect or consequential damages or any damages - whatsoever resulting from loss of use, data or profits, whether - in an action of contract, negligence or other tortious action, - arising out of or in connection with the use or performance of - this software. -*/ - -/** \file - * \brief Special function/variable attribute macros. - * - * \copydetails Group_FuncVarAttributes - * - * \note Do not include this file directly, rather include the Common.h header file instead to gain this file's - * functionality. - */ - -/** \ingroup Group_Common - * \defgroup Group_FuncVarAttributes Function/Variable Attributes - * \brief Special function/variable attribute macros. - * - * This module contains macros for applying specific attributes to functions and variables to control various - * optimizer and code generation features of the compiler. Attributes may be placed in the function prototype - * or variable declaration in any order, and multiple attributes can be specified for a single item via a space - * separated list. - * - * On incompatible versions of GCC or on other compilers, these macros evaluate to nothing unless they are - * critical to the code's function and thus must throw a compile error when used. - * - * @{ - */ - -#ifndef __LUFA_ATTR_H__ -#define __LUFA_ATTR_H__ - - /* Preprocessor Checks: */ - #if !defined(__INCLUDE_FROM_COMMON_H) - #error Do not include this file directly. Include LUFA/Common/Common.h instead to gain this functionality. - #endif - - /* Public Interface - May be used in end-application: */ - /* Macros: */ - #if defined(__GNUC__) || defined(__DOXYGEN__) - /** Indicates to the compiler that the function can not ever return, so that any stack restoring or - * return code may be omitted by the compiler in the resulting binary. - */ - #define ATTR_NO_RETURN __attribute__ ((noreturn)) - - /** Indicates that the function returns a value which should not be ignored by the user code. When - * applied, any ignored return value from calling the function will produce a compiler warning. - */ - #define ATTR_WARN_UNUSED_RESULT __attribute__ ((warn_unused_result)) - - /** Indicates that the specified parameters of the function are pointers which should never be \c NULL. - * When applied as a 1-based comma separated list the compiler will emit a warning if the specified - * parameters are known at compiler time to be \c NULL at the point of calling the function. - */ - #define ATTR_NON_NULL_PTR_ARG(...) __attribute__ ((nonnull (__VA_ARGS__))) - - /** Removes any preamble or postamble from the function. When used, the function will not have any - * register or stack saving code. This should be used with caution, and when used the programmer - * is responsible for maintaining stack and register integrity. - */ - #define ATTR_NAKED __attribute__ ((naked)) - - /** Prevents the compiler from considering a specified function for in-lining. When applied, the given - * function will not be in-lined under any circumstances. - */ - #define ATTR_NO_INLINE __attribute__ ((noinline)) - - /** Forces the compiler to inline the specified function. When applied, the given function will be - * in-lined under all circumstances. - */ - #define ATTR_ALWAYS_INLINE __attribute__ ((always_inline)) - - /** Indicates that the specified function is pure, in that it has no side-effects other than global - * or parameter variable access. - */ - #define ATTR_PURE __attribute__ ((pure)) - - /** Indicates that the specified function is constant, in that it has no side effects other than - * parameter access. - */ - #define ATTR_CONST __attribute__ ((const)) - - /** Marks a given function as deprecated, which produces a warning if the function is called. */ - #define ATTR_DEPRECATED __attribute__ ((deprecated)) - - /** Marks a function as a weak reference, which can be overridden by other functions with an - * identical name (in which case the weak reference is discarded at link time). - */ - #define ATTR_WEAK - - /** Forces the compiler to not automatically zero the given global variable on startup, so that the - * current RAM contents is retained. Under most conditions this value will be random due to the - * behavior of volatile memory once power is removed, but may be used in some specific circumstances, - * like the passing of values back after a system watchdog reset. - */ - #define ATTR_NO_INIT __attribute__ ((section (".noinit"))) - - /** Places the function in one of the initialization sections, which execute before the main function - * of the application. Refer to the avr-libc manual for more information on the initialization sections. - * - * \param[in] SectionIndex Initialization section number where the function should be placed. - */ - #define ATTR_INIT_SECTION(SectionIndex) __attribute__ ((used, naked, section (".init" #SectionIndex ))) - - /** Marks a function as an alias for another function. - * - * \param[in] Func Name of the function which the given function name should alias. - */ - #define ATTR_ALIAS(Func) - - /** Marks a variable or struct element for packing into the smallest space available, omitting any - * alignment bytes usually added between fields to optimize field accesses. - */ - #define ATTR_PACKED __attribute__ ((packed)) - #define ATTR_IAR_PACKED - - /** Indicates the minimum alignment in bytes for a variable or struct element. - * - * \param[in] Bytes Minimum number of bytes the item should be aligned to. - */ - #define ATTR_ALIGNED(Bytes) __attribute__ ((aligned(Bytes))) - - #elif defined(__ICCARM__) - #define ATTR_NO_RETURN - #define ATTR_WARN_UNUSED_RESULT - #define ATTR_NON_NULL_PTR_ARG(...) - #define ATTR_NAKED - #define ATTR_NO_INLINE - #define ATTR_ALWAYS_INLINE - #define ATTR_PURE - #define ATTR_CONST - #define ATTR_DEPRECATED - #define ATTR_WEAK - #define ATTR_NO_INIT - #define ATTR_INIT_SECTION(SectionIndex) - #define ATTR_ALIAS(Func) - #define ATTR_PACKED - #define ATTR_IAR_PACKED __packed - #define ATTR_ALIGNED(Bytes) - #elif defined ( __CC_ARM ) - #define ATTR_NO_RETURN - #define ATTR_WARN_UNUSED_RESULT - #define ATTR_NON_NULL_PTR_ARG(...) - #define ATTR_NAKED - #define ATTR_NO_INLINE - #define ATTR_ALWAYS_INLINE - #define ATTR_PURE - #define ATTR_CONST - #define ATTR_DEPRECATED - #define ATTR_WEAK - #define ATTR_NO_INIT - #define ATTR_INIT_SECTION(SectionIndex) - #define ATTR_ALIAS(Func) - #define ATTR_PACKED __attribute__((packed)) - #define ATTR_IAR_PACKED - #define ATTR_ALIGNED(Bytes) - #elif defined ( __TASKING__ ) - #define ATTR_NO_RETURN - #define ATTR_WARN_UNUSED_RESULT - #define ATTR_NON_NULL_PTR_ARG(...) - #define ATTR_NAKED - #define ATTR_NO_INLINE - #define ATTR_ALWAYS_INLINE - #define ATTR_PURE - #define ATTR_CONST - #define ATTR_DEPRECATED - #define ATTR_WEAK - #define ATTR_NO_INIT - #define ATTR_INIT_SECTION(SectionIndex) - #define ATTR_ALIAS(Func) - #define ATTR_PACKED __packed__ - #define ATTR_IAR_PACKED - #define ATTR_ALIGNED(Bytes) - #endif - -#endif - -/** @} */ - - -#endif /* UC_FAMILY == XMC4 */ diff --git a/cores/usblib/Common/BoardTypes.h b/cores/usblib/Common/BoardTypes.h deleted file mode 100644 index ca2c97f8..00000000 --- a/cores/usblib/Common/BoardTypes.h +++ /dev/null @@ -1,261 +0,0 @@ -#ifdef XMC4_SERIES - -/* - LUFA Library - Copyright (C) Dean Camera, 2014. - - dean [at] fourwalledcubicle [dot] com - www.lufa-lib.org -*/ - -/* - Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com) - - Permission to use, copy, modify, distribute, and sell this - software and its documentation for any purpose is hereby granted - without fee, provided that the above copyright notice appear in - all copies and that both that the copyright notice and this - permission notice and warranty disclaimer appear in supporting - documentation, and that the name of the author not be used in - advertising or publicity pertaining to distribution of the - software without specific, written prior permission. - - The author disclaims all warranties with regard to this - software, including all implied warranties of merchantability - and fitness. In no event shall the author be liable for any - special, indirect or consequential damages or any damages - whatsoever resulting from loss of use, data or profits, whether - in an action of contract, negligence or other tortious action, - arising out of or in connection with the use or performance of - this software. -*/ - -/** \file - * \brief Supported pre-made board hardware defines. - * - * \copydetails Group_BoardTypes - * - * \note Do not include this file directly, rather include the Common.h header file instead to gain this file's - * functionality. - */ - -/** \ingroup Group_Common - * \defgroup Group_BoardTypes Board Types - * \brief Supported pre-made board hardware defines. - * - * Board macros for indicating the chosen physical board hardware to the library. These macros should be used when - * defining the \c BOARD token to the chosen hardware via the \c -D switch in the project makefile. If a custom - * board is used, the \ref BOARD_NONE or \ref BOARD_USER values should be selected. - * - * @{ - */ - -#ifndef __LUFA_BOARDTYPES_H__ -#define __LUFA_BOARDTYPES_H__ - - /* Preprocessor Checks: */ - #if !defined(__INCLUDE_FROM_COMMON_H) - #error Do not include this file directly. Include LUFA/Common/Common.h instead to gain this functionality. - #endif - - /* Public Interface - May be used in end-application: */ - /* Macros: */ - /** Selects the user-defined board drivers, which should be placed in the user project's folder - * under a directory named \c /Board/. Each board driver should be named identically to the LUFA - * master board driver (i.e., driver in the \c LUFA/Drivers/Board directory) so that the library - * can correctly identify it. - */ - #define BOARD_USER 0 - - /** Disables board drivers when operation will not be adversely affected (e.g. LEDs) - use of board drivers - * such as the Joystick driver, where the removal would adversely affect the code's operation is still disallowed. */ - #define BOARD_NONE 1 - - /** Selects the USBKEY specific board drivers, including Temperature, Button, Dataflash, Joystick and LED drivers. */ - #define BOARD_USBKEY 2 - - /** Selects the STK525 specific board drivers, including Temperature, Button, Dataflash, Joystick and LED drivers. */ - #define BOARD_STK525 3 - - /** Selects the STK526 specific board drivers, including Temperature, Button, Dataflash, Joystick and LED drivers. */ - #define BOARD_STK526 4 - - /** Selects the RZUSBSTICK specific board drivers, including the driver for the boards LEDs. */ - #define BOARD_RZUSBSTICK 5 - - /** Selects the ATAVRUSBRF01 specific board drivers, including the driver for the board LEDs. */ - #define BOARD_ATAVRUSBRF01 6 - - /** Selects the BUMBLEB specific board drivers, using the officially recommended peripheral layout. */ - #define BOARD_BUMBLEB 7 - - /** Selects the XPLAIN (Revision 2 or newer) specific board drivers, including LED and Dataflash drivers. */ - #define BOARD_XPLAIN 8 - - /** Selects the XPLAIN (Revision 1) specific board drivers, including LED and Dataflash drivers. */ - #define BOARD_XPLAIN_REV1 9 - - /** Selects the EVK527 specific board drivers, including Temperature, Button, Dataflash, Joystick and LED drivers. */ - #define BOARD_EVK527 10 - - /** Selects the Teensy version 1.x specific board drivers, including the driver for the board LEDs. */ - #define BOARD_TEENSY 11 - - /** Selects the USBTINY MKII specific board drivers, including the Button and LEDs drivers. */ - #define BOARD_USBTINYMKII 12 - - /** Selects the Benito specific board drivers, including the Button and LEDs drivers. */ - #define BOARD_BENITO 13 - - /** Selects the JM-DB-U2 specific board drivers, including the Button and LEDs drivers. */ - #define BOARD_JMDBU2 14 - - /** Selects the Olimex AVR-USB-162 specific board drivers, including the Button and LEDs drivers. */ - #define BOARD_OLIMEX162 15 - - /** Selects the UDIP specific board drivers, including the Button and LEDs drivers. */ - #define BOARD_UDIP 16 - - /** Selects the BUI specific board drivers, including the driver for the board LEDs. */ - #define BOARD_BUI 17 - - /** Selects the Arduino Uno specific board drivers, including the driver for the board LEDs. */ - #define BOARD_UNO 18 - - /** Selects the Busware CUL V3 specific board drivers, including the Button and LEDs drivers. */ - #define BOARD_CULV3 19 - - /** Selects the Blackcat USB JTAG specific board drivers, including the driver for the board LEDs. */ - #define BOARD_BLACKCAT 20 - - /** Selects the Maximus specific board drivers, including the driver for the board LEDs. */ - #define BOARD_MAXIMUS 21 - - /** Selects the Minimus specific board drivers, including the Button and LEDs drivers. */ - #define BOARD_MINIMUS 22 - - /** Selects the Adafruit U4 specific board drivers, including the Button driver. */ - #define BOARD_ADAFRUITU4 23 - - /** Selects the Microsin AVR-USB162 specific board drivers, including the Button and LEDs drivers. */ - #define BOARD_MICROSIN162 24 - - /** Selects the Kernel Concepts USBFOO specific board drivers, including the Button and LEDs drivers. */ - #define BOARD_USBFOO 25 - - /** Selects the Sparkfun ATMEGA8U2 specific board drivers, including the driver for the board LEDs. */ - #define BOARD_SPARKFUN8U2 26 - - /** Selects the Atmel EVK1101 specific board drivers, including the Button, Joystick and LED drivers. */ - #define BOARD_EVK1101 27 - - /** Selects the Busware TUL specific board drivers, including the Button and LED drivers. */ - #define BOARD_TUL 28 - - /** Selects the Atmel EVK1100 specific board drivers, including the Button, Joystick and LED drivers. */ - #define BOARD_EVK1100 29 - - /** Selects the Atmel EVK1104 specific board drivers, including the Button and LED drivers. */ - #define BOARD_EVK1104 30 - - /** Selects the Atmel XMEGA A3BU Xplained specific board drivers, including Dataflash, Button and LED drivers. */ - #define BOARD_A3BU_XPLAINED 31 - - /** Selects the Teensy version 2.x specific board drivers, including the driver for the board LEDs. */ - #define BOARD_TEENSY2 32 - - /** Selects the USB2AX version 1 and 2 specific board drivers, including the Button and LEDs drivers. */ - #define BOARD_USB2AX 33 - - /** Selects the USB2AX version 3 specific board drivers, including the Button and LEDs drivers. */ - #define BOARD_USB2AX_V3 34 - - /** Selects the Micropendous 32U2 specific board drivers, including the Button and LED drivers. */ - #define BOARD_MICROPENDOUS_32U2 35 - - /** Selects the Micropendous A specific board drivers, including the driver for the board Button. */ - #define BOARD_MICROPENDOUS_A 36 - - /** Selects the Micropendous 1 specific board drivers, including the driver for the board Button. */ - #define BOARD_MICROPENDOUS_1 37 - - /** Selects the Micropendous 2 specific board drivers, including the driver for the board Button. */ - #define BOARD_MICROPENDOUS_2 38 - - /** Selects the Micropendous 3 specific board drivers, including the driver for the board Button. */ - #define BOARD_MICROPENDOUS_3 39 - - /** Selects the Micropendous 4 specific board drivers, including the driver for the board Button. */ - #define BOARD_MICROPENDOUS_4 40 - - /** Selects the Micropendous DIP specific board drivers, including the driver for the board Button. */ - #define BOARD_MICROPENDOUS_DIP 41 - - /** Selects the Micropendous (Arduino-like) revision 1 specific board drivers, including the Button and LED drivers. */ - #define BOARD_MICROPENDOUS_REV1 42 - - /** Selects the Micropendous (Arduino-like) revision 2 specific board drivers, including the Button and LED drivers. */ - #define BOARD_MICROPENDOUS_REV2 43 - - /** Selects the XMEGA B1 Xplained specific board drivers, including the Button and LED drivers. */ - #define BOARD_B1_XPLAINED 44 - - /** Selects the Bitwizard Multio specific board drivers, including the driver for the board LEDs. */ - #define BOARD_MULTIO 45 - - /** Selects the Bitwizard Big-Multio specific board drivers, including the driver for the board LEDs. */ - #define BOARD_BIGMULTIO 46 - - /** Selects the DorkbotPDX Duce specific board drivers, including the driver for the board LEDs. */ - #define BOARD_DUCE 47 - - /** Selects the Olimex AVR-USB-32U4 specific board drivers, including the Button and LED drivers. */ - #define BOARD_OLIMEX32U4 48 - - /** Selects the Olimex AVR-USB-T32U4 specific board drivers, including the Button and LED drivers. */ - #define BOARD_OLIMEXT32U4 49 - - /** Selects the Olimex AVR-ISP-MK2 specific board drivers, including the Button and LED drivers. */ - #define BOARD_OLIMEXISPMK2 50 - - /** Selects the Arduino Leonardo specific board drivers, including the driver for the board LEDs. */ - #define BOARD_LEONARDO 51 - - /** Selects the UC3-A3 Xplained specific board drivers, including the Button and LED drivers. */ - #define BOARD_UC3A3_XPLAINED 52 - - /** Selects the USB2AX version 3.1 specific board drivers, including the Button and LEDs drivers. */ - #define BOARD_USB2AX_V31 53 - - /** Selects the Stange-ISP specific board drivers, including the Button and LEDs drivers. */ - #define BOARD_STANGE_ISP 54 - - /** Selects the XMEGA C3 XPLAINED specific board drivers, including the Button and LEDs drivers. */ - #define BOARD_C3_XPLAINED 55 - - /** Selects the U2S specific board drivers, including the Button and LEDs drivers. */ - #define BOARD_U2S 56 - - /** Selects the Arduino YUN specific board drivers, including the driver for the board LEDs. */ - #define BOARD_YUN 57 - - /** Selects the Arduino Micro specific board drivers, including the driver for the board LEDs. */ - #define BOARD_MICRO 58 - - /** Selects the Atmel Xplained-MINI specific board drivers, including the driver for the board LEDs. */ - #define BOARD_XPLAINED_MINI 59 - - #if !defined(__DOXYGEN__) - #define BOARD_ BOARD_NONE - - #if !defined(BOARD) - #define BOARD BOARD_NONE - #endif - #endif - -#endif - -/** @} */ - - -#endif /* UC_FAMILY == XMC4 */ diff --git a/cores/usblib/Common/Common.h b/cores/usblib/Common/Common.h deleted file mode 100644 index 68240e8b..00000000 --- a/cores/usblib/Common/Common.h +++ /dev/null @@ -1,226 +0,0 @@ -#ifdef XMC4_SERIES - -/* - LUFA Library - Copyright (C) Dean Camera, 2014. - - dean [at] fourwalledcubicle [dot] com - www.lufa-lib.org -*/ - -/* - Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com) - - Permission to use, copy, modify, distribute, and sell this - software and its documentation for any purpose is hereby granted - without fee, provided that the above copyright notice appear in - all copies and that both that the copyright notice and this - permission notice and warranty disclaimer appear in supporting - documentation, and that the name of the author not be used in - advertising or publicity pertaining to distribution of the - software without specific, written prior permission. - - The author disclaims all warranties with regard to this - software, including all implied warranties of merchantability - and fitness. In no event shall the author be liable for any - special, indirect or consequential damages or any damages - whatsoever resulting from loss of use, data or profits, whether - in an action of contract, negligence or other tortious action, - arising out of or in connection with the use or performance of - this software. -*/ - -/** \dir - * \brief Common library header files. - * - * This folder contains header files which are common to all parts of the LUFA library. They may be used freely in - * user applications. - */ - -/** \file - * \brief Common library convenience headers, macros and functions. - * - * \copydetails Group_Common - */ - -/** \defgroup Group_Common Common Utility Headers - LUFA/Drivers/Common/Common.h - * \brief Common library convenience headers, macros and functions. - * - * Common utility headers containing macros, functions, enums and types which are common to all - * aspects of the library. - * - * @{ - */ - -/** \defgroup Group_GlobalInt Global Interrupt Macros - * \brief Convenience macros for the management of interrupts globally within the device. - * - * Macros and functions to create and control global interrupts within the device. - */ - -#ifndef __LUFA_COMMON_H__ -#define __LUFA_COMMON_H__ - - /* Macros: */ - #define __INCLUDE_FROM_COMMON_H - - /* Includes: */ - #include - #include - #include - #include - - #include - #include - #include - #include - #include - - #if defined(USE_LUFA_CONFIG_HEADER) - #include - #endif - - /* Enable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - extern "C" { - #endif - - /* Architecture specific utility includes: */ - #if defined(__DOXYGEN__) - /** Type define for an unsigned integer the same width as the selected architecture's machine register. - * This is distinct from the non-specific standard int data type, whose width is machine dependant but - * which may not reflect the actual machine register width on some targets (e.g. AVR8). - */ - typedef MACHINE_REG_t uint_reg_t; - #else - #include - - #define ARCH_LITTLE_ENDIAN - #include - - #endif - - /* Public Interface - May be used in end-application: */ - /* Macros: */ - #if !defined(__DOXYGEN__) - // Obsolete, retained for compatibility with user code - #define MACROS do - #define MACROE while (0) - #endif - - /** Convenience macro to determine the larger of two values. - * - * \attention This macro should only be used with operands that do not have side effects from being evaluated - * multiple times. - * - * \param[in] x First value to compare - * \param[in] y First value to compare - * - * \return The larger of the two input parameters - */ - #if !defined(MAX) || defined(__DOXYGEN__) - #define MAX(x, y) (((x) > (y)) ? (x) : (y)) - #endif - - /** Convenience macro to determine the smaller of two values. - * - * \attention This macro should only be used with operands that do not have side effects from being evaluated - * multiple times. - * - * \param[in] x First value to compare. - * \param[in] y First value to compare. - * - * \return The smaller of the two input parameters - */ - #if !defined(MIN) || defined(__DOXYGEN__) - #define MIN(x, y) (((x) < (y)) ? (x) : (y)) - #endif - - #if !defined(STRINGIFY) || defined(__DOXYGEN__) - /** Converts the given input into a string, via the C Preprocessor. This macro puts literal quotation - * marks around the input, converting the source into a string literal. - * - * \param[in] x Input to convert into a string literal. - * - * \return String version of the input. - */ - #define STRINGIFY(x) #x - - /** Converts the given input into a string after macro expansion, via the C Preprocessor. This macro puts - * literal quotation marks around the expanded input, converting the source into a string literal. - * - * \param[in] x Input to expand and convert into a string literal. - * - * \return String version of the expanded input. - */ - #define STRINGIFY_EXPANDED(x) STRINGIFY(x) - #endif - - #if !defined(CONCAT) || defined(__DOXYGEN__) - /** Concatenates the given input into a single token, via the C Preprocessor. - * - * \param[in] x First item to concatenate. - * \param[in] y Second item to concatenate. - * - * \return Concatenated version of the input. - */ - #define CONCAT(x, y) x ## y - - /** CConcatenates the given input into a single token after macro expansion, via the C Preprocessor. - * - * \param[in] x First item to concatenate. - * \param[in] y Second item to concatenate. - * - * \return Concatenated version of the expanded input. - */ - #define CONCAT_EXPANDED(x, y) CONCAT(x, y) - #endif - - #if !defined(ISR) || defined(__DOXYGEN__) - /** Macro for the definition of interrupt service routines, so that the compiler can insert the required - * prologue and epilogue code to properly manage the interrupt routine without affecting the main thread's - * state with unintentional side-effects. - * - * Interrupt handlers written using this macro may still need to be registered with the microcontroller's - * Interrupt Controller (if present) before they will properly handle incoming interrupt events. - * - * \note This macro is only supplied on some architectures, where the standard library does not include a valid - * definition. If an existing definition exists, the alternative definition here will be ignored. - * - * \ingroup Group_GlobalInt - * - * \param[in] Name Unique name of the interrupt service routine. - */ - #define ISR(Name, ...) void Name (void) __attribute__((__interrupt__)) __VA_ARGS__; void Name (void) - #endif - - /* Inline Functions: */ - /** Function to reverse the individual bits in a byte - i.e. bit 7 is moved to bit 0, bit 6 to bit 1, - * etc. - * - * \param[in] Byte Byte of data whose bits are to be reversed. - * - * \return Input data with the individual bits reversed (mirrored). - */ - static inline uint8_t BitReverse(uint8_t Byte) ATTR_WARN_UNUSED_RESULT ATTR_CONST; - static inline uint8_t BitReverse(uint8_t Byte) - { - Byte = (((Byte & 0xF0) >> 4) | ((Byte & 0x0F) << 4)); - Byte = (((Byte & 0xCC) >> 2) | ((Byte & 0x33) << 2)); - Byte = (((Byte & 0xAA) >> 1) | ((Byte & 0x55) << 1)); - - return Byte; - } - - - /* Disable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - } - #endif - -#endif - -/** @} */ - - -#endif /* UC_FAMILY == XMC4 */ diff --git a/cores/usblib/Common/CompilerSpecific.h b/cores/usblib/Common/CompilerSpecific.h deleted file mode 100644 index cfd4f5b4..00000000 --- a/cores/usblib/Common/CompilerSpecific.h +++ /dev/null @@ -1,105 +0,0 @@ -#ifdef XMC4_SERIES - -/* - LUFA Library - Copyright (C) Dean Camera, 2014. - - dean [at] fourwalledcubicle [dot] com - www.lufa-lib.org -*/ - -/* - Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com) - - Permission to use, copy, modify, distribute, and sell this - software and its documentation for any purpose is hereby granted - without fee, provided that the above copyright notice appear in - all copies and that both that the copyright notice and this - permission notice and warranty disclaimer appear in supporting - documentation, and that the name of the author not be used in - advertising or publicity pertaining to distribution of the - software without specific, written prior permission. - - The author disclaims all warranties with regard to this - software, including all implied warranties of merchantability - and fitness. In no event shall the author be liable for any - special, indirect or consequential damages or any damages - whatsoever resulting from loss of use, data or profits, whether - in an action of contract, negligence or other tortious action, - arising out of or in connection with the use or performance of - this software. -*/ - -/** \file - * \brief Compiler specific definitions for code optimization and correctness. - * - * \copydetails Group_CompilerSpecific - * - * \note Do not include this file directly, rather include the Common.h header file instead to gain this file's - * functionality. - */ - -/** \ingroup Group_Common - * \defgroup Group_CompilerSpecific Compiler Specific Definitions - * \brief Compiler specific definitions for code optimization and correctness. - * - * Compiler specific definitions to expose certain compiler features which may increase the level of code optimization - * for a specific compiler, or correct certain issues that may be present such as memory barriers for use in conjunction - * with atomic variable access. - * - * Where possible, on alternative compilers, these macros will either have no effect, or default to returning a sane value - * so that they can be used in existing code without the need for extra compiler checks in the user application code. - * - * @{ - */ - -#ifndef __LUFA_COMPILERSPEC_H__ -#define __LUFA_COMPILERSPEC_H__ - - /* Preprocessor Checks: */ - #if !defined(__INCLUDE_FROM_COMMON_H) - #error Do not include this file directly. Include LUFA/Common/Common.h instead to gain this functionality. - #endif - - /* Public Interface - May be used in end-application: */ - /* Macros: */ - #if defined(__GNUC__) || defined(__DOXYGEN__) - /** Forces GCC to use pointer indirection (via the device's pointer register pairs) when accessing the given - * struct pointer. In some cases GCC will emit non-optimal assembly code when accessing a structure through - * a pointer, resulting in a larger binary. When this macro is used on a (non \c const) structure pointer before - * use, it will force GCC to use pointer indirection on the elements rather than direct store and load - * instructions. - * - * \param[in, out] StructPtr Pointer to a structure which is to be forced into indirect access mode. - */ - #define GCC_FORCE_POINTER_ACCESS(StructPtr) __asm__ __volatile__("" : "=b" (StructPtr) : "0" (StructPtr)) - - /** Forces GCC to create a memory barrier, ensuring that memory accesses are not reordered past the barrier point. - * This can be used before ordering-critical operations, to ensure that the compiler does not re-order the resulting - * assembly output in an unexpected manner on sections of code that are ordering-specific. - */ - #define GCC_MEMORY_BARRIER() __asm__ __volatile__("" ::: "memory"); - - /** Determines if the specified value can be determined at compile-time to be a constant value when compiling under GCC. - * - * \param[in] x Value to check compile-time constantness of. - * - * \return Boolean \c true if the given value is known to be a compile time constant, \c false otherwise. - */ - #define GCC_IS_COMPILE_CONST(x) __builtin_constant_p(x) - - #define MEMCPY(dst,src,len) thumb2_memcpy(dst,src,len) - void* thumb2_memcpy(void* pDest, const void* pSource, size_t length); - #else - #define GCC_FORCE_POINTER_ACCESS(StructPtr) - #define GCC_MEMORY_BARRIER() - #define GCC_IS_COMPILE_CONST(x) 0 - #define MEMCPY(dst,src,len) memcpy(dst,src,len) - #endif - -#endif - -/** @} */ - - -#endif /* UC_FAMILY == XMC4 */ diff --git a/cores/usblib/Common/Endianness.h b/cores/usblib/Common/Endianness.h deleted file mode 100644 index 05f5359e..00000000 --- a/cores/usblib/Common/Endianness.h +++ /dev/null @@ -1,465 +0,0 @@ -#ifdef XMC4_SERIES - -/* - LUFA Library - Copyright (C) Dean Camera, 2014. - - dean [at] fourwalledcubicle [dot] com - www.lufa-lib.org -*/ - -/* - Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com) - - Permission to use, copy, modify, distribute, and sell this - software and its documentation for any purpose is hereby granted - without fee, provided that the above copyright notice appear in - all copies and that both that the copyright notice and this - permission notice and warranty disclaimer appear in supporting - documentation, and that the name of the author not be used in - advertising or publicity pertaining to distribution of the - software without specific, written prior permission. - - The author disclaims all warranties with regard to this - software, including all implied warranties of merchantability - and fitness. In no event shall the author be liable for any - special, indirect or consequential damages or any damages - whatsoever resulting from loss of use, data or profits, whether - in an action of contract, negligence or other tortious action, - arising out of or in connection with the use or performance of - this software. -*/ - -/** \file - * \brief Endianness and Byte Ordering macros and functions. - * - * \copydetails Group_Endianness - */ - -/** \ingroup Group_Endianness - * \defgroup Group_ByteSwapping Byte Reordering - * \brief Macros and functions for forced byte reordering. - */ - -/** \ingroup Group_Endianness - * \defgroup Group_EndianConversion Endianness Conversion - * \brief Macros and functions for automatic endianness conversion. - */ - -/** \ingroup Group_Common - * \defgroup Group_Endianness Endianness and Byte Ordering - * \brief Convenience macros and functions relating to byte (re-)ordering - * - * Common library convenience macros and functions relating to byte (re-)ordering. - * - * @{ - */ - -#ifndef __LUFA_ENDIANNESS_H__ -#define __LUFA_ENDIANNESS_H__ - - /* Enable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - extern "C" { - #endif - - /* Preprocessor Checks: */ - #if !defined(__INCLUDE_FROM_COMMON_H) - #error Do not include this file directly. Include LUFA/Common/Common.h instead to gain this functionality. - #endif - - #if !(defined(ARCH_BIG_ENDIAN) || defined(ARCH_LITTLE_ENDIAN)) - #error ARCH_BIG_ENDIAN or ARCH_LITTLE_ENDIAN not set for the specified architecture. - #endif - - /* Public Interface - May be used in end-application: */ - /* Macros: */ - /** Swaps the byte ordering of a 16-bit value at compile-time. Do not use this macro for swapping byte orderings - * of dynamic values computed at runtime, use \ref SwapEndian_16() instead. The result of this macro can be used - * inside struct or other variable initializers outside of a function, something that is not possible with the - * inline function variant. - * - * \hideinitializer - * - * \ingroup Group_ByteSwapping - * - * \param[in] x 16-bit value whose byte ordering is to be swapped. - * - * \return Input value with the byte ordering reversed. - */ - #define SWAPENDIAN_16(x) (uint16_t)((((x) & 0xFF00) >> 8) | (((x) & 0x00FF) << 8)) - - /** Swaps the byte ordering of a 32-bit value at compile-time. Do not use this macro for swapping byte orderings - * of dynamic values computed at runtime- use \ref SwapEndian_32() instead. The result of this macro can be used - * inside struct or other variable initializers outside of a function, something that is not possible with the - * inline function variant. - * - * \hideinitializer - * - * \ingroup Group_ByteSwapping - * - * \param[in] x 32-bit value whose byte ordering is to be swapped. - * - * \return Input value with the byte ordering reversed. - */ - #define SWAPENDIAN_32(x) (uint32_t)((((x) & 0xFF000000UL) >> 24UL) | (((x) & 0x00FF0000UL) >> 8UL) | \ - (((x) & 0x0000FF00UL) << 8UL) | (((x) & 0x000000FFUL) << 24UL)) - - #if defined(ARCH_BIG_ENDIAN) && !defined(le16_to_cpu) - #define le16_to_cpu(x) SwapEndian_16(x) - #define le32_to_cpu(x) SwapEndian_32(x) - #define be16_to_cpu(x) (x) - #define be32_to_cpu(x) (x) - #define cpu_to_le16(x) SwapEndian_16(x) - #define cpu_to_le32(x) SwapEndian_32(x) - #define cpu_to_be16(x) (x) - #define cpu_to_be32(x) (x) - #define LE16_TO_CPU(x) SWAPENDIAN_16(x) - #define LE32_TO_CPU(x) SWAPENDIAN_32(x) - #define BE16_TO_CPU(x) (x) - #define BE32_TO_CPU(x) (x) - #define CPU_TO_LE16(x) SWAPENDIAN_16(x) - #define CPU_TO_LE32(x) SWAPENDIAN_32(x) - #define CPU_TO_BE16(x) (x) - #define CPU_TO_BE32(x) (x) - #elif !defined(le16_to_cpu) - /** \name Run-time endianness conversion */ - //@{ - - /** Performs a conversion between a Little Endian encoded 16-bit piece of data and the - * Endianness of the currently selected CPU architecture. - * - * On little endian architectures, this macro does nothing. - * - * \note This macro is designed for run-time conversion of data - for compile-time endianness - * conversion, use \ref LE16_TO_CPU instead. - * - * \ingroup Group_EndianConversion - * - * \param[in] x Data to perform the endianness conversion on. - * - * \return Endian corrected version of the input value. - */ - #define le16_to_cpu(x) (x) - - /** Performs a conversion between a Little Endian encoded 32-bit piece of data and the - * Endianness of the currently selected CPU architecture. - * - * On little endian architectures, this macro does nothing. - * - * \note This macro is designed for run-time conversion of data - for compile-time endianness - * conversion, use \ref LE32_TO_CPU instead. - * - * \ingroup Group_EndianConversion - * - * \param[in] x Data to perform the endianness conversion on. - * - * \return Endian corrected version of the input value. - */ - #define le32_to_cpu(x) (x) - - /** Performs a conversion between a Big Endian encoded 16-bit piece of data and the - * Endianness of the currently selected CPU architecture. - * - * On big endian architectures, this macro does nothing. - * - * \note This macro is designed for run-time conversion of data - for compile-time endianness - * conversion, use \ref BE16_TO_CPU instead. - * - * \ingroup Group_EndianConversion - * - * \param[in] x Data to perform the endianness conversion on. - * - * \return Endian corrected version of the input value. - */ - #define be16_to_cpu(x) SwapEndian_16(x) - - /** Performs a conversion between a Big Endian encoded 32-bit piece of data and the - * Endianness of the currently selected CPU architecture. - * - * On big endian architectures, this macro does nothing. - * - * \note This macro is designed for run-time conversion of data - for compile-time endianness - * conversion, use \ref BE32_TO_CPU instead. - * - * \ingroup Group_EndianConversion - * - * \param[in] x Data to perform the endianness conversion on. - * - * \return Endian corrected version of the input value. - */ - #define be32_to_cpu(x) SwapEndian_32(x) - - /** Performs a conversion on a natively encoded 16-bit piece of data to ensure that it - * is in Little Endian format regardless of the currently selected CPU architecture. - * - * On little endian architectures, this macro does nothing. - * - * \note This macro is designed for run-time conversion of data - for compile-time endianness - * conversion, use \ref CPU_TO_LE16 instead. - * - * \ingroup Group_EndianConversion - * - * \param[in] x Data to perform the endianness conversion on. - * - * \return Endian corrected version of the input value. - */ - #define cpu_to_le16(x) (x) - - /** Performs a conversion on a natively encoded 32-bit piece of data to ensure that it - * is in Little Endian format regardless of the currently selected CPU architecture. - * - * On little endian architectures, this macro does nothing. - * - * \note This macro is designed for run-time conversion of data - for compile-time endianness - * conversion, use \ref CPU_TO_LE32 instead. - * - * \ingroup Group_EndianConversion - * - * \param[in] x Data to perform the endianness conversion on. - * - * \return Endian corrected version of the input value. - */ - #define cpu_to_le32(x) (x) - - /** Performs a conversion on a natively encoded 16-bit piece of data to ensure that it - * is in Big Endian format regardless of the currently selected CPU architecture. - * - * On big endian architectures, this macro does nothing. - * - * \note This macro is designed for run-time conversion of data - for compile-time endianness - * conversion, use \ref CPU_TO_BE16 instead. - * - * \ingroup Group_EndianConversion - * - * \param[in] x Data to perform the endianness conversion on. - * - * \return Endian corrected version of the input value. - */ - #define cpu_to_be16(x) SwapEndian_16(x) - - /** Performs a conversion on a natively encoded 32-bit piece of data to ensure that it - * is in Big Endian format regardless of the currently selected CPU architecture. - * - * On big endian architectures, this macro does nothing. - * - * \note This macro is designed for run-time conversion of data - for compile-time endianness - * conversion, use \ref CPU_TO_BE32 instead. - * - * \ingroup Group_EndianConversion - * - * \param[in] x Data to perform the endianness conversion on. - * - * \return Endian corrected version of the input value. - */ - #define cpu_to_be32(x) SwapEndian_32(x) - - //@} - - /** \name Compile-time endianness conversion */ - //@{ - - /** Performs a conversion between a Little Endian encoded 16-bit piece of data and the - * Endianness of the currently selected CPU architecture. - * - * On little endian architectures, this macro does nothing. - * - * \note This macro is designed for compile-time conversion of data - for run time endianness - * conversion, use \ref le16_to_cpu instead. - * - * \ingroup Group_EndianConversion - * - * \param[in] x Data to perform the endianness conversion on. - * - * \return Endian corrected version of the input value. - */ - #define LE16_TO_CPU(x) (x) - - /** Performs a conversion between a Little Endian encoded 32-bit piece of data and the - * Endianness of the currently selected CPU architecture. - * - * On little endian architectures, this macro does nothing. - * - * \note This macro is designed for compile-time conversion of data - for run time endianness - * conversion, use \ref le32_to_cpu instead. - * - * \ingroup Group_EndianConversion - * - * \param[in] x Data to perform the endianness conversion on. - * - * \return Endian corrected version of the input value. - */ - #define LE32_TO_CPU(x) (x) - - /** Performs a conversion between a Big Endian encoded 16-bit piece of data and the - * Endianness of the currently selected CPU architecture. - * - * On big endian architectures, this macro does nothing. - * - * \note This macro is designed for compile-time conversion of data - for run-time endianness - * conversion, use \ref be16_to_cpu instead. - * - * \ingroup Group_EndianConversion - * - * \param[in] x Data to perform the endianness conversion on. - * - * \return Endian corrected version of the input value. - */ - #define BE16_TO_CPU(x) SWAPENDIAN_16(x) - - /** Performs a conversion between a Big Endian encoded 32-bit piece of data and the - * Endianness of the currently selected CPU architecture. - * - * On big endian architectures, this macro does nothing. - * - * \note This macro is designed for compile-time conversion of data - for run-time endianness - * conversion, use \ref be32_to_cpu instead. - * - * \ingroup Group_EndianConversion - * - * \param[in] x Data to perform the endianness conversion on. - * - * \return Endian corrected version of the input value. - */ - #define BE32_TO_CPU(x) SWAPENDIAN_32(x) - - /** Performs a conversion on a natively encoded 16-bit piece of data to ensure that it - * is in Little Endian format regardless of the currently selected CPU architecture. - * - * On little endian architectures, this macro does nothing. - * - * \note This macro is designed for compile-time conversion of data - for run-time endianness - * conversion, use \ref cpu_to_le16 instead. - * - * \ingroup Group_EndianConversion - * - * \param[in] x Data to perform the endianness conversion on. - * - * \return Endian corrected version of the input value. - */ - #define CPU_TO_LE16(x) (x) - - /** Performs a conversion on a natively encoded 32-bit piece of data to ensure that it - * is in Little Endian format regardless of the currently selected CPU architecture. - * - * On little endian architectures, this macro does nothing. - * - * \note This macro is designed for compile-time conversion of data - for run-time endianness - * conversion, use \ref cpu_to_le32 instead. - * - * \ingroup Group_EndianConversion - * - * \param[in] x Data to perform the endianness conversion on. - * - * \return Endian corrected version of the input value. - */ - #define CPU_TO_LE32(x) (x) - - /** Performs a conversion on a natively encoded 16-bit piece of data to ensure that it - * is in Big Endian format regardless of the currently selected CPU architecture. - * - * On big endian architectures, this macro does nothing. - * - * \note This macro is designed for compile-time conversion of data - for run-time endianness - * conversion, use \ref cpu_to_be16 instead. - * - * \ingroup Group_EndianConversion - * - * \param[in] x Data to perform the endianness conversion on. - * - * \return Endian corrected version of the input value. - */ - #define CPU_TO_BE16(x) SWAPENDIAN_16(x) - - /** Performs a conversion on a natively encoded 32-bit piece of data to ensure that it - * is in Big Endian format regardless of the currently selected CPU architecture. - * - * On big endian architectures, this macro does nothing. - * - * \note This macro is designed for compile-time conversion of data - for run-time endianness - * conversion, use \ref cpu_to_be32 instead. - * - * \ingroup Group_EndianConversion - * - * \param[in] x Data to perform the endianness conversion on. - * - * \return Endian corrected version of the input value. - */ - #define CPU_TO_BE32(x) SWAPENDIAN_32(x) - - //! @} - #endif - - /* Inline Functions: */ - /** Function to reverse the byte ordering of the individual bytes in a 16 bit value. - * - * \ingroup Group_ByteSwapping - * - * \param[in] Word Word of data whose bytes are to be swapped. - * - * \return Input data with the individual bytes reversed. - */ - static inline uint16_t SwapEndian_16(const uint16_t Word) ATTR_WARN_UNUSED_RESULT ATTR_CONST ATTR_ALWAYS_INLINE; - static inline uint16_t SwapEndian_16(const uint16_t Word) - { - if (GCC_IS_COMPILE_CONST(Word)) - return SWAPENDIAN_16(Word); - - return __REV16(Word); - } - - /** Function to reverse the byte ordering of the individual bytes in a 32 bit value. - * - * \ingroup Group_ByteSwapping - * - * \param[in] DWord Double word of data whose bytes are to be swapped. - * - * \return Input data with the individual bytes reversed. - */ - static inline uint32_t SwapEndian_32(const uint32_t DWord) ATTR_WARN_UNUSED_RESULT ATTR_CONST ATTR_ALWAYS_INLINE; - static inline uint32_t SwapEndian_32(const uint32_t DWord) - { - if (GCC_IS_COMPILE_CONST(DWord)) - return SWAPENDIAN_32(DWord); - - return __REV(DWord); - } - - /** Function to reverse the byte ordering of the individual bytes in a n byte value. - * - * \ingroup Group_ByteSwapping - * - * \param[in,out] Data Pointer to a number containing an even number of bytes to be reversed. - * \param[in] Length Length of the data in bytes. - * - * \return Input data with the individual bytes reversed. - */ - static inline void SwapEndian_n(void* const Data, - uint8_t Length) ATTR_NON_NULL_PTR_ARG(1); - static inline void SwapEndian_n(void* const Data, - uint8_t Length) - { - uint8_t* CurrDataPos = (uint8_t*)Data; - - while (Length > 1) - { - uint8_t Temp = *CurrDataPos; - *CurrDataPos = *(CurrDataPos + Length - 1); - *(CurrDataPos + Length - 1) = Temp; - - CurrDataPos++; - Length -= 2; - } - } - - /* Disable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - } - #endif - -#endif - -/** @} */ - - -#endif /* UC_FAMILY == XMC4 */ diff --git a/cores/usblib/Common/memcpy.c b/cores/usblib/Common/memcpy.c deleted file mode 100644 index 1acda9d9..00000000 --- a/cores/usblib/Common/memcpy.c +++ /dev/null @@ -1,62 +0,0 @@ -#ifdef XMC4_SERIES - -/* Copyright (C) 2013 - Adam Green (https://github.com/adamgreen) - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -#if defined(USB0) -#include - -#if defined(__GNUC__) -/* This is a hand written Thumb-2 assembly language version of the - standard C memcpy() function that can be used by the lwIP networking - stack to improve its performance. It copies 4 bytes at a time and - unrolls the loop to perform 4 of these copies per loop iteration. -*/ -__attribute__((naked)) void thumb2_memcpy(void* pDest, const void* pSource, size_t length) -{ - __asm ( - ".syntax unified\n" - ".thumb\n" - - // Copy 16 bytes at a time first. - " lsrs r3, r2, #4\n" - " beq.n 2$\n" - "1$: ldr r12, [r1], #4\n" - " str r12, [r0], #4\n" - " ldr r12, [r1], #4\n" - " str r12, [r0], #4\n" - " ldr r12, [r1], #4\n" - " str r12, [r0], #4\n" - " ldr r12, [r1], #4\n" - " str r12, [r0], #4\n" - " subs r3, #1\n" - " bne 1$\n" - - // Copy byte by byte for what is left. - "2$:\n" - " ands r3, r2, #0xf\n" - " beq.n 4$\n" - "3$: ldrb r12, [r1], #1\n" - " strb r12, [r0], #1\n" - " subs r3, #1\n" - " bne 3$\n" - - // Return to caller. - "4$: bx lr\n" - ); -} -#endif - -#endif -#endif /* UC_FAMILY == XMC4 */ diff --git a/cores/usblib/Core/ConfigDescriptors.c b/cores/usblib/Core/ConfigDescriptors.c deleted file mode 100644 index 2dc10cd6..00000000 --- a/cores/usblib/Core/ConfigDescriptors.c +++ /dev/null @@ -1,149 +0,0 @@ -#ifdef XMC4_SERIES - -/* - LUFA Library - Copyright (C) Dean Camera, 2014. - - dean [at] fourwalledcubicle [dot] com - www.lufa-lib.org -*/ - -/* - Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com) - - Permission to use, copy, modify, distribute, and sell this - software and its documentation for any purpose is hereby granted - without fee, provided that the above copyright notice appear in - all copies and that both that the copyright notice and this - permission notice and warranty disclaimer appear in supporting - documentation, and that the name of the author not be used in - advertising or publicity pertaining to distribution of the - software without specific, written prior permission. - - The author disclaims all warranties with regard to this - software, including all implied warranties of merchantability - and fitness. In no event shall the author be liable for any - special, indirect or consequential damages or any damages - whatsoever resulting from loss of use, data or profits, whether - in an action of contract, negligence or other tortious action, - arising out of or in connection with the use or performance of - this software. -*/ - -#define __INCLUDE_FROM_USB_DRIVER -#include - -#if defined(USB_CAN_BE_HOST) -uint8_t USB_Host_GetDeviceConfigDescriptor(const uint8_t ConfigNumber, - uint16_t* const ConfigSizePtr, - void* const BufferPtr, - const uint16_t BufferSize) -{ - uint8_t ErrorCode; - uint8_t ConfigHeader[sizeof(USB_Descriptor_Configuration_Header_t)]; - - USB_ControlRequest = (USB_Request_Header_t) - { - .bmRequestType = (REQDIR_DEVICETOHOST | REQTYPE_STANDARD | REQREC_DEVICE), - .bRequest = REQ_GetDescriptor, - .wValue = ((DTYPE_Configuration << 8) | (ConfigNumber - 1)), - .wIndex = 0, - .wLength = sizeof(USB_Descriptor_Configuration_Header_t), - }; - - Pipe_SelectPipe(PIPE_CONTROLPIPE); - - if ((ErrorCode = USB_Host_SendControlRequest(ConfigHeader)) != HOST_SENDCONTROL_Successful) - return ErrorCode; - - *ConfigSizePtr = le16_to_cpu(DESCRIPTOR_PCAST(ConfigHeader, USB_Descriptor_Configuration_Header_t)->TotalConfigurationSize); - - if (*ConfigSizePtr > BufferSize) - return HOST_GETCONFIG_BuffOverflow; - - USB_ControlRequest.wLength = *ConfigSizePtr; - - if ((ErrorCode = USB_Host_SendControlRequest(BufferPtr)) != HOST_SENDCONTROL_Successful) - return ErrorCode; - - if (DESCRIPTOR_TYPE(BufferPtr) != DTYPE_Configuration) - return HOST_GETCONFIG_InvalidData; - - return HOST_GETCONFIG_Successful; -} -#endif - -void USB_GetNextDescriptorOfType(uint16_t* const BytesRem, - void** const CurrConfigLoc, - const uint8_t Type) -{ - while (*BytesRem) - { - USB_GetNextDescriptor(BytesRem, CurrConfigLoc); - - if (DESCRIPTOR_TYPE(*CurrConfigLoc) == Type) - return; - } -} - -void USB_GetNextDescriptorOfTypeBefore(uint16_t* const BytesRem, - void** const CurrConfigLoc, - const uint8_t Type, - const uint8_t BeforeType) -{ - while (*BytesRem) - { - USB_GetNextDescriptor(BytesRem, CurrConfigLoc); - - if (DESCRIPTOR_TYPE(*CurrConfigLoc) == Type) - { - return; - } - else if (DESCRIPTOR_TYPE(*CurrConfigLoc) == BeforeType) - { - *BytesRem = 0; - return; - } - } -} - -void USB_GetNextDescriptorOfTypeAfter(uint16_t* const BytesRem, - void** const CurrConfigLoc, - const uint8_t Type, - const uint8_t AfterType) -{ - USB_GetNextDescriptorOfType(BytesRem, CurrConfigLoc, AfterType); - - if (*BytesRem) - USB_GetNextDescriptorOfType(BytesRem, CurrConfigLoc, Type); -} - -uint8_t USB_GetNextDescriptorComp(uint16_t* const BytesRem, - void** const CurrConfigLoc, - ConfigComparatorPtr_t const ComparatorRoutine) -{ - uint8_t ErrorCode; - - while (*BytesRem) - { - uint8_t* PrevDescLoc = *CurrConfigLoc; - uint16_t PrevBytesRem = *BytesRem; - - USB_GetNextDescriptor(BytesRem, CurrConfigLoc); - - if ((ErrorCode = ComparatorRoutine(*CurrConfigLoc)) != DESCRIPTOR_SEARCH_NotFound) - { - if (ErrorCode == DESCRIPTOR_SEARCH_Fail) - { - *CurrConfigLoc = PrevDescLoc; - *BytesRem = PrevBytesRem; - } - - return ErrorCode; - } - } - - return DESCRIPTOR_SEARCH_COMP_EndOfDescriptor; -} - -#endif /* UC_FAMILY == XMC4 */ diff --git a/cores/usblib/Core/ConfigDescriptors.h b/cores/usblib/Core/ConfigDescriptors.h deleted file mode 100644 index 13abdb9a..00000000 --- a/cores/usblib/Core/ConfigDescriptors.h +++ /dev/null @@ -1,290 +0,0 @@ -#ifdef XMC4_SERIES - -/* - LUFA Library - Copyright (C) Dean Camera, 2014. - - dean [at] fourwalledcubicle [dot] com - www.lufa-lib.org -*/ - -/* - Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com) - - Permission to use, copy, modify, distribute, and sell this - software and its documentation for any purpose is hereby granted - without fee, provided that the above copyright notice appear in - all copies and that both that the copyright notice and this - permission notice and warranty disclaimer appear in supporting - documentation, and that the name of the author not be used in - advertising or publicity pertaining to distribution of the - software without specific, written prior permission. - - The author disclaims all warranties with regard to this - software, including all implied warranties of merchantability - and fitness. In no event shall the author be liable for any - special, indirect or consequential damages or any damages - whatsoever resulting from loss of use, data or profits, whether - in an action of contract, negligence or other tortious action, - arising out of or in connection with the use or performance of - this software. -*/ - -/** \file - * \brief USB Configuration Descriptor definitions. - * \copydetails Group_ConfigDescriptorParser - * - * \note This file should not be included directly. It is automatically included as needed by the USB driver - * dispatch header located in LUFA/Drivers/USB/USB.h. - */ - -/** \ingroup Group_StdDescriptors - * \defgroup Group_ConfigDescriptorParser Configuration Descriptor Parser - * \brief USB Configuration Descriptor definitions. - * - * This section of the library gives a friendly API which can be used in host applications to easily - * parse an attached device's configuration descriptor so that endpoint, interface and other descriptor - * data can be extracted and used as needed. - * - * @{ - */ - -#ifndef __CONFIGDESCRIPTORS_H__ -#define __CONFIGDESCRIPTORS_H__ - - /* Includes: */ - #include <../Common/Common.h> - #include - #include - - /* Enable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - extern "C" { - #endif - - /* Preprocessor Checks: */ - #if !defined(__INCLUDE_FROM_USB_DRIVER) - #error Do not include this file directly. Include LUFA/Drivers/USB/USB.h instead. - #endif - - /* Public Interface - May be used in end-application: */ - /* Macros: */ - /** Casts a pointer to a descriptor inside the configuration descriptor into a pointer to the given - * descriptor type. - * - * Usage Example: - * \code - * uint8_t* CurrDescriptor = &ConfigDescriptor[0]; // Pointing to the configuration header - * USB_Descriptor_Configuration_Header_t* ConfigHeaderPtr = DESCRIPTOR_PCAST(CurrDescriptor, - * USB_Descriptor_Configuration_Header_t); - * - * // Can now access elements of the configuration header struct using the -> indirection operator - * \endcode - */ - #define DESCRIPTOR_PCAST(DescriptorPtr, Type) ((Type*)(DescriptorPtr)) - - /** Casts a pointer to a descriptor inside the configuration descriptor into the given descriptor - * type (as an actual struct instance rather than a pointer to a struct). - * - * Usage Example: - * \code - * uint8_t* CurrDescriptor = &ConfigDescriptor[0]; // Pointing to the configuration header - * USB_Descriptor_Configuration_Header_t ConfigHeader = DESCRIPTOR_CAST(CurrDescriptor, - * USB_Descriptor_Configuration_Header_t); - * - * // Can now access elements of the configuration header struct using the . operator - * \endcode - */ - #define DESCRIPTOR_CAST(DescriptorPtr, Type) (*DESCRIPTOR_PCAST(DescriptorPtr, Type)) - - /** Returns the descriptor's type, expressed as the 8-bit type value in the header of the descriptor. - * This value's meaning depends on the descriptor's placement in the descriptor, but standard type - * values can be accessed in the \ref USB_DescriptorTypes_t enum. - */ - #define DESCRIPTOR_TYPE(DescriptorPtr) DESCRIPTOR_PCAST(DescriptorPtr, USB_Descriptor_Header_t)->Type - - /** Returns the descriptor's size, expressed as the 8-bit value indicating the number of bytes. */ - #define DESCRIPTOR_SIZE(DescriptorPtr) DESCRIPTOR_PCAST(DescriptorPtr, USB_Descriptor_Header_t)->Size - - /* Type Defines: */ - /** Type define for a Configuration Descriptor comparator function (function taking a pointer to an array - * of type void, returning a uint8_t value). - * - * \see \ref USB_GetNextDescriptorComp function for more details. - */ - typedef uint8_t (* ConfigComparatorPtr_t)(void*); - - /* Enums: */ - /** Enum for the possible return codes of the \ref USB_Host_GetDeviceConfigDescriptor() function. */ - enum USB_Host_GetConfigDescriptor_ErrorCodes_t - { - HOST_GETCONFIG_Successful = 0, /**< No error occurred while retrieving the configuration descriptor. */ - HOST_GETCONFIG_DeviceDisconnect = 1, /**< The attached device was disconnected while retrieving the configuration - * descriptor. - */ - HOST_GETCONFIG_PipeError = 2, /**< An error occurred in the pipe while sending the request. */ - HOST_GETCONFIG_SetupStalled = 3, /**< The attached device stalled the request to retrieve the configuration - * descriptor. - */ - HOST_GETCONFIG_SoftwareTimeOut = 4, /**< The request or data transfer timed out. */ - HOST_GETCONFIG_BuffOverflow = 5, /**< The device's configuration descriptor is too large to fit into the allocated - * buffer. - */ - HOST_GETCONFIG_InvalidData = 6, /**< The device returned invalid configuration descriptor data. */ - }; - - /** Enum for return values of a descriptor comparator function. */ - enum DSearch_Return_ErrorCodes_t - { - DESCRIPTOR_SEARCH_Found = 0, /**< Current descriptor matches comparator criteria. */ - DESCRIPTOR_SEARCH_Fail = 1, /**< No further descriptor could possibly match criteria, fail the search. */ - DESCRIPTOR_SEARCH_NotFound = 2, /**< Current descriptor does not match comparator criteria. */ - }; - - /** Enum for return values of \ref USB_GetNextDescriptorComp(). */ - enum DSearch_Comp_Return_ErrorCodes_t - { - DESCRIPTOR_SEARCH_COMP_Found = 0, /**< Configuration descriptor now points to descriptor which matches - * search criteria of the given comparator function. */ - DESCRIPTOR_SEARCH_COMP_Fail = 1, /**< Comparator function returned \ref DESCRIPTOR_SEARCH_Fail. */ - DESCRIPTOR_SEARCH_COMP_EndOfDescriptor = 2, /**< End of configuration descriptor reached before match found. */ - }; - - /* Function Prototypes: */ - /** Retrieves the configuration descriptor data from an attached device via a standard request into a buffer, - * including validity and size checking to prevent a buffer overflow. - * - * \param[in] ConfigNumber Device configuration descriptor number to fetch from the device (usually set to 1 for - * single configuration devices). - * \param[in,out] ConfigSizePtr Pointer to a location for storing the retrieved configuration descriptor size. - * \param[out] BufferPtr Pointer to the buffer for storing the configuration descriptor data. - * \param[out] BufferSize Size of the allocated buffer where the configuration descriptor is to be stored. - * - * \return A value from the \ref USB_Host_GetConfigDescriptor_ErrorCodes_t enum. - */ - uint8_t USB_Host_GetDeviceConfigDescriptor(const uint8_t ConfigNumber, - uint16_t* const ConfigSizePtr, - void* const BufferPtr, - const uint16_t BufferSize) ATTR_NON_NULL_PTR_ARG(2) ATTR_NON_NULL_PTR_ARG(3); - - /** Skips to the next sub-descriptor inside the configuration descriptor of the specified type value. - * The bytes remaining value is automatically decremented. - * - * \param[in,out] BytesRem Pointer to the number of bytes remaining of the configuration descriptor. - * \param[in,out] CurrConfigLoc Pointer to the current descriptor inside the configuration descriptor. - * \param[in] Type Descriptor type value to search for. - */ - void USB_GetNextDescriptorOfType(uint16_t* const BytesRem, - void** const CurrConfigLoc, - const uint8_t Type) - ATTR_NON_NULL_PTR_ARG(1) ATTR_NON_NULL_PTR_ARG(2); - - /** Skips to the next sub-descriptor inside the configuration descriptor of the specified type value, - * which must come before a descriptor of the second given type value. If the BeforeType type - * descriptor is reached first, the number of bytes remaining to process is set to zero and the - * function exits. The bytes remaining value is automatically decremented. - * - * \param[in,out] BytesRem Pointer to the number of bytes remaining of the configuration descriptor. - * \param[in,out] CurrConfigLoc Pointer to the current descriptor inside the configuration descriptor. - * \param[in] Type Descriptor type value to search for. - * \param[in] BeforeType Descriptor type value which must not be reached before the given Type descriptor. - */ - void USB_GetNextDescriptorOfTypeBefore(uint16_t* const BytesRem, - void** const CurrConfigLoc, - const uint8_t Type, - const uint8_t BeforeType) - ATTR_NON_NULL_PTR_ARG(1) ATTR_NON_NULL_PTR_ARG(2); - - /** Skips to the next sub-descriptor inside the configuration descriptor of the specified type value, - * which must come after a descriptor of the second given type value. The bytes remaining value is - * automatically decremented. - * - * \param[in,out] BytesRem Pointer to the number of bytes remaining of the configuration descriptor. - * \param[in,out] CurrConfigLoc Pointer to the current descriptor inside the configuration descriptor. - * \param[in] Type Descriptor type value to search for. - * \param[in] AfterType Descriptor type value which must be reached before the given Type descriptor. - */ - void USB_GetNextDescriptorOfTypeAfter(uint16_t* const BytesRem, - void** const CurrConfigLoc, - const uint8_t Type, - const uint8_t AfterType) - ATTR_NON_NULL_PTR_ARG(1) ATTR_NON_NULL_PTR_ARG(2); - - /** Searches for the next descriptor in the given configuration descriptor using a pre-made comparator - * function. The routine updates the position and remaining configuration descriptor bytes values - * automatically. If a comparator routine fails a search, the descriptor pointer is retreated back - * so that the next descriptor search invocation will start from the descriptor which first caused the - * original search to fail. This behavior allows for one comparator to be used immediately after another - * has failed, starting the second search from the descriptor which failed the first. - * - * Comparator functions should be standard functions which accept a pointer to the header of the current - * descriptor inside the configuration descriptor which is being compared, and should return a value from - * the \ref DSearch_Return_ErrorCodes_t enum as a uint8_t value. - * - * \note This function is available in USB Host mode only. - * - * \param[in,out] BytesRem Pointer to an int storing the remaining bytes in the configuration descriptor. - * \param[in,out] CurrConfigLoc Pointer to the current position in the configuration descriptor. - * \param[in] ComparatorRoutine Name of the comparator search function to use on the configuration descriptor. - * - * \return Value of one of the members of the \ref DSearch_Comp_Return_ErrorCodes_t enum. - * - * Usage Example: - * \code - * uint8_t EndpointSearcher(void* CurrentDescriptor); // Comparator Prototype - * - * uint8_t EndpointSearcher(void* CurrentDescriptor) - * { - * if (DESCRIPTOR_TYPE(CurrentDescriptor) == DTYPE_Endpoint) - * return DESCRIPTOR_SEARCH_Found; - * else - * return DESCRIPTOR_SEARCH_NotFound; - * } - * - * //... - * - * // After retrieving configuration descriptor: - * if (USB_Host_GetNextDescriptorComp(&BytesRemaining, &CurrentConfigLoc, EndpointSearcher) == - * Descriptor_Search_Comp_Found) - * { - * // Do something with the endpoint descriptor - * } - * \endcode - */ - uint8_t USB_GetNextDescriptorComp(uint16_t* const BytesRem, - void** const CurrConfigLoc, - ConfigComparatorPtr_t const ComparatorRoutine) ATTR_NON_NULL_PTR_ARG(1) - ATTR_NON_NULL_PTR_ARG(2) ATTR_NON_NULL_PTR_ARG(3); - - /* Inline Functions: */ - /** Skips over the current sub-descriptor inside the configuration descriptor, so that the pointer then - points to the next sub-descriptor. The bytes remaining value is automatically decremented. - * - * \param[in,out] BytesRem Pointer to the number of bytes remaining of the configuration descriptor. - * \param[in,out] CurrConfigLoc Pointer to the current descriptor inside the configuration descriptor. - */ - static inline void USB_GetNextDescriptor(uint16_t* const BytesRem, - void** CurrConfigLoc) ATTR_NON_NULL_PTR_ARG(1) ATTR_NON_NULL_PTR_ARG(2); - static inline void USB_GetNextDescriptor(uint16_t* const BytesRem, - void** CurrConfigLoc) - { - uint16_t CurrDescriptorSize = DESCRIPTOR_CAST(*CurrConfigLoc, USB_Descriptor_Header_t).Size; - - if (*BytesRem < CurrDescriptorSize) - CurrDescriptorSize = *BytesRem; - - *CurrConfigLoc = (void*)((uintptr_t)*CurrConfigLoc + CurrDescriptorSize); - *BytesRem -= CurrDescriptorSize; - } - - /* Disable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - } - #endif - -#endif - -/** @} */ - - -#endif /* UC_FAMILY == XMC4 */ diff --git a/cores/usblib/Core/Device.h b/cores/usblib/Core/Device.h deleted file mode 100644 index 36e012dc..00000000 --- a/cores/usblib/Core/Device.h +++ /dev/null @@ -1,157 +0,0 @@ -#ifdef XMC4_SERIES - -/* - LUFA Library - Copyright (C) Dean Camera, 2014. - - dean [at] fourwalledcubicle [dot] com - www.lufa-lib.org -*/ - -/* - Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com) - - Permission to use, copy, modify, distribute, and sell this - software and its documentation for any purpose is hereby granted - without fee, provided that the above copyright notice appear in - all copies and that both that the copyright notice and this - permission notice and warranty disclaimer appear in supporting - documentation, and that the name of the author not be used in - advertising or publicity pertaining to distribution of the - software without specific, written prior permission. - - The author disclaims all warranties with regard to this - software, including all implied warranties of merchantability - and fitness. In no event shall the author be liable for any - special, indirect or consequential damages or any damages - whatsoever resulting from loss of use, data or profits, whether - in an action of contract, negligence or other tortious action, - arising out of or in connection with the use or performance of - this software. -*/ - -/** \file - * \brief Common USB Device definitions for all architectures. - * \copydetails Group_Device - * - * \note This file should not be included directly. It is automatically included as needed by the USB driver - * dispatch header located in LUFA/Drivers/USB/USB.h. - */ - -/** \ingroup Group_USB - * \defgroup Group_Device Device Management - * \brief USB Device management definitions for USB device mode. - * - * USB Device mode related definitions common to all architectures. This module contains definitions which - * are used when the USB controller is initialized in device mode. - * - * @{ - */ - -#ifndef __USBDEVICE_H__ -#define __USBDEVICE_H__ - - /* Includes: */ - #include <../Common/Common.h> - #include - #include - #include - #include - - /* Enable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - extern "C" { - #endif - - /* Preprocessor Checks: */ - #if !defined(__INCLUDE_FROM_USB_DRIVER) - #error Do not include this file directly. Include USB/USB.h instead. - #endif - - /* Public Interface - May be used in end-application: */ - /* Enums: */ - /** Enum for the various states of the USB Device state machine. Only some states are - * implemented in the LUFA library - other states are left to the user to implement. - * - * For information on each possible USB device state, refer to the USB 2.0 specification. - * - * \see \ref USB_DeviceState, which stores the current device state machine state. - */ - enum USB_Device_States_t - { - DEVICE_STATE_Unattached = 0, /**< Internally implemented by the library. This state indicates - * that the device is not currently connected to a host. - */ - DEVICE_STATE_Powered = 1, /**< Internally implemented by the library. This state indicates - * that the device is connected to a host, but enumeration has not - * yet begun. - */ - DEVICE_STATE_Default = 2, /**< Internally implemented by the library. This state indicates - * that the device's USB bus has been reset by the host and it is - * now waiting for the host to begin the enumeration process. - */ - DEVICE_STATE_Addressed = 3, /**< Internally implemented by the library. This state indicates - * that the device has been addressed by the USB Host, but is not - * yet configured. - */ - DEVICE_STATE_Configured = 4, /**< May be implemented by the user project. This state indicates - * that the device has been enumerated by the host and is ready - * for USB communications to begin. - */ - DEVICE_STATE_Suspended = 5, /**< May be implemented by the user project. This state indicates - * that the USB bus has been suspended by the host, and the device - * should power down to a minimal power level until the bus is - * resumed. - */ - }; - - /* Function Prototypes: */ - /** Function to retrieve a given descriptor's size and memory location from the given descriptor type value, - * index and language ID. This function MUST be overridden in the user application (added with full, identical - * prototype and name so that the library can call it to retrieve descriptor data. - * - * \param[in] wValue The type of the descriptor to retrieve in the upper byte, and the index in the - * lower byte (when more than one descriptor of the given type exists, such as the - * case of string descriptors). The type may be one of the standard types defined - * in the DescriptorTypes_t enum, or may be a class-specific descriptor type value. - * \param[in] wIndex The language ID of the string to return if the \c wValue type indicates - * \ref DTYPE_String, otherwise zero for standard descriptors, or as defined in a - * class-specific standards. - * \param[out] DescriptorAddress Pointer to the descriptor in memory. This should be set by the routine to - * the address of the descriptor. - * \param[out] DescriptorMemorySpace A value from the \ref USB_DescriptorMemorySpaces_t enum to indicate the memory - * space in which the descriptor is stored. This parameter does not exist when one - * of the \c USE_*_DESCRIPTORS compile time options is used, or on architectures which - * use a unified address space. - * - * \note By default, the library expects all descriptors to be located in flash memory via the \c PROGMEM attribute. - * If descriptors should be located in RAM or EEPROM instead (to speed up access in the case of RAM, or to - * allow the descriptors to be changed dynamically at runtime) either the \c USE_RAM_DESCRIPTORS or the - * \c USE_EEPROM_DESCRIPTORS tokens may be defined in the project makefile and passed to the compiler by the -D - * switch. - * - * \return Size in bytes of the descriptor if it exists, zero or \ref NO_DESCRIPTOR otherwise. - */ - uint16_t CALLBACK_USB_GetDescriptor(const uint16_t wValue, - const uint8_t wIndex, - const void** const DescriptorAddress - #if (defined(ARCH_HAS_MULTI_ADDRESS_SPACE) || defined(__DOXYGEN__)) && \ - !(defined(USE_FLASH_DESCRIPTORS) || defined(USE_EEPROM_DESCRIPTORS) || defined(USE_RAM_DESCRIPTORS)) - , uint8_t* const DescriptorMemorySpace - #endif - ) ATTR_WARN_UNUSED_RESULT ATTR_NON_NULL_PTR_ARG(3); - - /* Architecture Includes: */ - #include - - /* Disable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - } - #endif - -#endif - -/** @} */ - - -#endif /* UC_FAMILY == XMC4 */ diff --git a/cores/usblib/Core/DeviceStandardReq.h b/cores/usblib/Core/DeviceStandardReq.h deleted file mode 100644 index 34d90577..00000000 --- a/cores/usblib/Core/DeviceStandardReq.h +++ /dev/null @@ -1,162 +0,0 @@ -#ifdef XMC4_SERIES - -/* - LUFA Library - Copyright (C) Dean Camera, 2014. - - dean [at] fourwalledcubicle [dot] com - www.lufa-lib.org -*/ - -/* - Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com) - - Permission to use, copy, modify, distribute, and sell this - software and its documentation for any purpose is hereby granted - without fee, provided that the above copyright notice appear in - all copies and that both that the copyright notice and this - permission notice and warranty disclaimer appear in supporting - documentation, and that the name of the author not be used in - advertising or publicity pertaining to distribution of the - software without specific, written prior permission. - - The author disclaims all warranties with regard to this - software, including all implied warranties of merchantability - and fitness. In no event shall the author be liable for any - special, indirect or consequential damages or any damages - whatsoever resulting from loss of use, data or profits, whether - in an action of contract, negligence or other tortious action, - arising out of or in connection with the use or performance of - this software. -*/ - -/** \file - * \brief USB device standard request management. - * - * This file contains the function prototypes necessary for the processing of incoming standard control requests - * when the library is in USB device mode. - * - * \note This file should not be included directly. It is automatically included as needed by the USB driver - * dispatch header located in LUFA/Drivers/USB/USB.h. - */ - -#ifndef __DEVICESTDREQ_H__ -#define __DEVICESTDREQ_H__ - - /* Includes: */ - #include <../Common/Common.h> - #include - #include - #include - #include - #include - #include - - /* Enable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - extern "C" { - #endif - - /* Preprocessor Checks: */ - #if !defined(__INCLUDE_FROM_USB_DRIVER) - #error Do not include this file directly. Include LUFA/Drivers/USB/USB.h instead. - #endif - - /* Public Interface - May be used in end-application: */ - /* Enums: */ - #if defined(ARCH_HAS_MULTI_ADDRESS_SPACE) || defined(__DOXYGEN__) - /** Enum for the possible descriptor memory spaces, for the \c MemoryAddressSpace parameter of the - * \ref CALLBACK_USB_GetDescriptor() function. This can be used when none of the \c USE_*_DESCRIPTORS - * compile time options are used, to indicate in which memory space the descriptor is stored. - * - * \ingroup Group_Device - */ - enum USB_DescriptorMemorySpaces_t - { - #if defined(ARCH_HAS_FLASH_ADDRESS_SPACE) || defined(__DOXYGEN__) - MEMSPACE_FLASH = 0, /**< Indicates the requested descriptor is located in FLASH memory. */ - #endif - #if defined(ARCH_HAS_EEPROM_ADDRESS_SPACE) || defined(__DOXYGEN__) - MEMSPACE_EEPROM = 1, /**< Indicates the requested descriptor is located in EEPROM memory. */ - #endif - MEMSPACE_RAM = 2, /**< Indicates the requested descriptor is located in RAM memory. */ - }; - #endif - - /* Global Variables: */ - /** Indicates the currently set configuration number of the device. USB devices may have several - * different configurations which the host can select between; this indicates the currently selected - * value, or 0 if no configuration has been selected. - * - * \attention This variable should be treated as read-only in the user application, and never manually - * changed in value. - * - * \ingroup Group_Device - */ - extern uint8_t USB_Device_ConfigurationNumber; - - #if !defined(NO_DEVICE_REMOTE_WAKEUP) - /** Indicates if the host is currently allowing the device to issue remote wakeup events. If this - * flag is cleared, the device should not issue remote wakeup events to the host. - * - * \attention This variable should be treated as read-only in the user application, and never manually - * changed in value. - * - * \note To reduce FLASH usage of the compiled applications where Remote Wakeup is not supported, - * this global and the underlying management code can be disabled by defining the - * \c NO_DEVICE_REMOTE_WAKEUP token in the project makefile and passing it to the compiler via - * the -D switch. - * - * \ingroup Group_Device - */ - extern bool USB_Device_RemoteWakeupEnabled; - #endif - - #if !defined(NO_DEVICE_SELF_POWER) - /** Indicates if the device is currently being powered by its own power supply, rather than being - * powered by the host's USB supply. This flag should remain cleared if the device does not - * support self powered mode, as indicated in the device descriptors. - * - * \ingroup Group_Device - */ - extern bool USB_Device_CurrentlySelfPowered; - #endif - - /* Private Interface - For use in library only: */ - #if !defined(__DOXYGEN__) - #if defined(USE_RAM_DESCRIPTORS) && defined(USE_EEPROM_DESCRIPTORS) - #error USE_RAM_DESCRIPTORS and USE_EEPROM_DESCRIPTORS are mutually exclusive. - #elif defined(USE_RAM_DESCRIPTORS) && defined(USE_FLASH_DESCRIPTORS) - #error USE_RAM_DESCRIPTORS and USE_FLASH_DESCRIPTORS are mutually exclusive. - #elif defined(USE_FLASH_DESCRIPTORS) && defined(USE_EEPROM_DESCRIPTORS) - #error USE_FLASH_DESCRIPTORS and USE_EEPROM_DESCRIPTORS are mutually exclusive. - #elif defined(USE_FLASH_DESCRIPTORS) && defined(USE_EEPROM_DESCRIPTORS) && defined(USE_RAM_DESCRIPTORS) - #error Only one of the USE_*_DESCRIPTORS modes should be selected. - #endif - - /* Function Prototypes: */ - void USB_Device_ProcessControlRequest(void); - - #if defined(__INCLUDE_FROM_DEVICESTDREQ_C) - static void USB_Device_SetAddress(void); - static void USB_Device_SetConfiguration(void); - static void USB_Device_GetConfiguration(void); - static void USB_Device_GetDescriptor(void); - static void USB_Device_GetStatus(void); - static void USB_Device_ClearSetFeature(void); - - #if !defined(NO_INTERNAL_SERIAL) && (USE_INTERNAL_SERIAL != NO_DESCRIPTOR) - static void USB_Device_GetInternalSerialDescriptor(void); - #endif - #endif - #endif - - /* Disable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - } - #endif - -#endif - - -#endif /* UC_FAMILY == XMC4 */ diff --git a/cores/usblib/Core/EndPoint.h b/cores/usblib/Core/EndPoint.h deleted file mode 100644 index 68eba1c9..00000000 --- a/cores/usblib/Core/EndPoint.h +++ /dev/null @@ -1,128 +0,0 @@ -#ifdef XMC4_SERIES - -/* - LUFA Library - Copyright (C) Dean Camera, 2014. - - dean [at] fourwalledcubicle [dot] com - www.lufa-lib.org -*/ - -/* - Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com) - - Permission to use, copy, modify, distribute, and sell this - software and its documentation for any purpose is hereby granted - without fee, provided that the above copyright notice appear in - all copies and that both that the copyright notice and this - permission notice and warranty disclaimer appear in supporting - documentation, and that the name of the author not be used in - advertising or publicity pertaining to distribution of the - software without specific, written prior permission. - - The author disclaims all warranties with regard to this - software, including all implied warranties of merchantability - and fitness. In no event shall the author be liable for any - special, indirect or consequential damages or any damages - whatsoever resulting from loss of use, data or profits, whether - in an action of contract, negligence or other tortious action, - arising out of or in connection with the use or performance of - this software. -*/ - -/** \file - * \brief USB Endpoint definitions for all architectures. - * \copydetails Group_EndpointManagement - * - * \note This file should not be included directly. It is automatically included as needed by the USB driver - * dispatch header located in LUFA/Drivers/USB/USB.h. - */ - -/** \ingroup Group_EndpointManagement - * \defgroup Group_EndpointRW Endpoint Data Reading and Writing - * \brief Endpoint data read/write definitions. - * - * Functions, macros, variables, enums and types related to data reading and writing from and to endpoints. - */ - -/** \ingroup Group_EndpointRW - * \defgroup Group_EndpointPrimitiveRW Read/Write of Primitive Data Types - * \brief Endpoint data primitive read/write definitions. - * - * Functions, macros, variables, enums and types related to data reading and writing of primitive data types - * from and to endpoints. - */ - -/** \ingroup Group_EndpointManagement - * \defgroup Group_EndpointPacketManagement Endpoint Packet Management - * \brief USB Endpoint package management definitions. - * - * Functions, macros, variables, enums and types related to packet management of endpoints. - */ - -/** \ingroup Group_USB - * \defgroup Group_EndpointManagement Endpoint Management - * \brief Endpoint management definitions. - * - * Functions, macros and enums related to endpoint management when in USB Device mode. This - * module contains the endpoint management macros, as well as endpoint interrupt and data - * send/receive functions for various data types. - * - * @{ - */ - -#ifndef __ENDPOINT_H__ -#define __ENDPOINT_H__ - - /* Includes: */ - #include <../Common/Common.h> - #include - - /* Enable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - extern "C" { - #endif - - /* Preprocessor Checks: */ - #if !defined(__INCLUDE_FROM_USB_DRIVER) - #error Do not include this file directly. Include USB/USB.h instead. - #endif - - /* Public Interface - May be used in end-application: */ - /* Type Defines: */ - /** Type define for a endpoint table entry, used to configure endpoints in groups via - * \ref Endpoint_ConfigureEndpointTable(). - */ - typedef struct - { - uint8_t Address; /**< Address of the endpoint to configure, or zero if the table entry is to be unused. */ - uint16_t Size; /**< Size of the endpoint bank, in bytes. */ - uint8_t Type; /**< Type of the endpoint, a \c EP_TYPE_* mask. */ - uint8_t Banks; /**< Number of hardware banks to use for the endpoint. */ - } USB_Endpoint_Table_t; - - /* Macros: */ - /** Endpoint number mask, for masking against endpoint addresses to retrieve the endpoint's - * numerical address in the device. - */ - #define ENDPOINT_EPNUM_MASK 0x0F - - /** Endpoint address for the default control endpoint, which always resides in address 0. This is - * defined for convenience to give more readable code when used with the endpoint macros. - */ - #define ENDPOINT_CONTROLEP 0 - - /* Architecture Includes: */ - #include - - /* Disable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - } - #endif - -#endif - -/** @} */ - - -#endif /* UC_FAMILY == XMC4 */ diff --git a/cores/usblib/Core/EndpointStream.h b/cores/usblib/Core/EndpointStream.h deleted file mode 100644 index e73e9beb..00000000 --- a/cores/usblib/Core/EndpointStream.h +++ /dev/null @@ -1,122 +0,0 @@ -#ifdef XMC4_SERIES - -/* - LUFA Library - Copyright (C) Dean Camera, 2014. - - dean [at] fourwalledcubicle [dot] com - www.lufa-lib.org -*/ - -/* - Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com) - - Permission to use, copy, modify, distribute, and sell this - software and its documentation for any purpose is hereby granted - without fee, provided that the above copyright notice appear in - all copies and that both that the copyright notice and this - permission notice and warranty disclaimer appear in supporting - documentation, and that the name of the author not be used in - advertising or publicity pertaining to distribution of the - software without specific, written prior permission. - - The author disclaims all warranties with regard to this - software, including all implied warranties of merchantability - and fitness. In no event shall the author be liable for any - special, indirect or consequential damages or any damages - whatsoever resulting from loss of use, data or profits, whether - in an action of contract, negligence or other tortious action, - arising out of or in connection with the use or performance of - this software. -*/ - -/** \file - * \brief Endpoint data stream transmission and reception management. - * \copydetails Group_EndpointStreamRW - * - * \note This file should not be included directly. It is automatically included as needed by the USB driver - * dispatch header located in LUFA/Drivers/USB/USB.h. - */ - -/** \ingroup Group_EndpointRW - * \defgroup Group_EndpointStreamRW Read/Write of Multi-Byte Streams - * \brief Endpoint data stream transmission and reception management. - * - * Functions, macros, variables, enums and types related to data reading and writing of data streams from - * and to endpoints. - * - * @{ - */ - -#ifndef __ENDPOINT_STREAM_H__ -#define __ENDPOINT_STREAM_H__ - - /* Includes: */ - #include <../Common/Common.h> - #include - - /* Enable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - extern "C" { - #endif - - /* Preprocessor Checks: */ - #if !defined(__INCLUDE_FROM_USB_DRIVER) - #error Do not include this file directly. Include LUFA/Drivers/USB/USB.h instead. - #endif - - /* Public Interface - May be used in end-application: */ - /* Enums: */ - /** Enum for the possible error return codes of the \c Endpoint_*_Stream_* functions. */ - enum Endpoint_Stream_RW_ErrorCodes_t - { - ENDPOINT_RWSTREAM_NoError = 0, /**< Command completed successfully, no error. */ - ENDPOINT_RWSTREAM_EndpointStalled = 1, /**< The endpoint was stalled during the stream - * transfer by the host or device. - */ - ENDPOINT_RWSTREAM_DeviceDisconnected = 2, /**< Device was disconnected from the host during - * the transfer. - */ - ENDPOINT_RWSTREAM_BusSuspended = 3, /**< The USB bus has been suspended by the host and - * no USB endpoint traffic can occur until the bus - * has resumed. - */ - ENDPOINT_RWSTREAM_Timeout = 4, /**< The host failed to accept or send the next packet - * within the software timeout period set by the - * \ref USB_STREAM_TIMEOUT_MS macro. - */ - ENDPOINT_RWSTREAM_IncompleteTransfer = 5, /**< Indicates that the endpoint bank became full or empty before - * the complete contents of the current stream could be - * transferred. The endpoint stream function should be called - * again to process the next chunk of data in the transfer. - */ - }; - - /** Enum for the possible error return codes of the \c Endpoint_*_Control_Stream_* functions. */ - enum Endpoint_ControlStream_RW_ErrorCodes_t - { - ENDPOINT_RWCSTREAM_NoError = 0, /**< Command completed successfully, no error. */ - ENDPOINT_RWCSTREAM_HostAborted = 1, /**< The aborted the transfer prematurely. */ - ENDPOINT_RWCSTREAM_DeviceDisconnected = 2, /**< Device was disconnected from the host during - * the transfer. - */ - ENDPOINT_RWCSTREAM_BusSuspended = 3, /**< The USB bus has been suspended by the host and - * no USB endpoint traffic can occur until the bus - * has resumed. - */ - }; - - /* Architecture Includes: */ - #include - - /* Disable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - } - #endif - -#endif - -/** @} */ - - -#endif /* UC_FAMILY == XMC4 */ diff --git a/cores/usblib/Core/Events.c b/cores/usblib/Core/Events.c deleted file mode 100644 index 351ef48d..00000000 --- a/cores/usblib/Core/Events.c +++ /dev/null @@ -1,43 +0,0 @@ -#ifdef XMC4_SERIES - -/* - LUFA Library - Copyright (C) Dean Camera, 2014. - - dean [at] fourwalledcubicle [dot] com - www.lufa-lib.org -*/ - -/* - Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com) - - Permission to use, copy, modify, distribute, and sell this - software and its documentation for any purpose is hereby granted - without fee, provided that the above copyright notice appear in - all copies and that both that the copyright notice and this - permission notice and warranty disclaimer appear in supporting - documentation, and that the name of the author not be used in - advertising or publicity pertaining to distribution of the - software without specific, written prior permission. - - The author disclaims all warranties with regard to this - software, including all implied warranties of merchantability - and fitness. In no event shall the author be liable for any - special, indirect or consequential damages or any damages - whatsoever resulting from loss of use, data or profits, whether - in an action of contract, negligence or other tortious action, - arising out of or in connection with the use or performance of - this software. -*/ - -#define __INCLUDE_FROM_EVENTS_C -#define __INCLUDE_FROM_USB_DRIVER -#include - -void USB_Event_Stub(void) -{ - -} - - -#endif /* UC_FAMILY == XMC4 */ diff --git a/cores/usblib/Core/Events.h b/cores/usblib/Core/Events.h deleted file mode 100644 index eed31804..00000000 --- a/cores/usblib/Core/Events.h +++ /dev/null @@ -1,390 +0,0 @@ -#ifdef XMC4_SERIES - -/* - LUFA Library - Copyright (C) Dean Camera, 2014. - - dean [at] fourwalledcubicle [dot] com - www.lufa-lib.org -*/ - -/* - Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com) - - Permission to use, copy, modify, distribute, and sell this - software and its documentation for any purpose is hereby granted - without fee, provided that the above copyright notice appear in - all copies and that both that the copyright notice and this - permission notice and warranty disclaimer appear in supporting - documentation, and that the name of the author not be used in - advertising or publicity pertaining to distribution of the - software without specific, written prior permission. - - The author disclaims all warranties with regard to this - software, including all implied warranties of merchantability - and fitness. In no event shall the author be liable for any - special, indirect or consequential damages or any damages - whatsoever resulting from loss of use, data or profits, whether - in an action of contract, negligence or other tortious action, - arising out of or in connection with the use or performance of - this software. -*/ - -/** \file - * \brief USB Event management definitions. - * \copydetails Group_Events - * - * \note This file should not be included directly. It is automatically included as needed by the USB driver - * dispatch header located in LUFA/Drivers/USB/USB.h. - */ - -/** \ingroup Group_USB - * \defgroup Group_Events USB Events - * \brief USB Event management definitions. - * - * This module contains macros and functions relating to the management of library events, which are small - * pieces of code similar to ISRs which are run when a given condition is met. Each event can be fired from - * multiple places in the user or library code, which may or may not be inside an ISR, thus each handler - * should be written to be as small and fast as possible to prevent possible problems. - * - * Events can be hooked by the user application by declaring a handler function with the same name and parameters - * listed here. If an event with no user-associated handler is fired within the library, it by default maps to an - * internal empty stub function. - * - * Each event must only have one associated event handler, but can be raised by multiple sources by calling the - * event handler function (with any required event parameters). - * - * @{ - */ - -#ifndef __USBEVENTS_H__ -#define __USBEVENTS_H__ - - /* Includes: */ - #include <../Common/Common.h> - #include - - /* Enable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - extern "C" { - #endif - - /* Preprocessor Checks: */ - #if !defined(__INCLUDE_FROM_USB_DRIVER) - #error Do not include this file directly. Include LUFA/Drivers/USB/USB.h instead. - #endif - - /* Public Interface - May be used in end-application: */ - /* Pseudo-Functions for Doxygen: */ - #if !defined(__INCLUDE_FROM_EVENTS_C) || defined(__DOXYGEN__) - /** Event for USB mode pin level change. This event fires when the USB interface is set to dual role - * mode, and the UID pin level has changed to indicate a new mode (device or host). This event fires - * before the mode is switched to the newly indicated mode but after the \ref EVENT_USB_Device_Disconnect - * event has fired (if disconnected before the role change). - * - * \note This event only exists on microcontrollers that support dual role USB modes. - * \n\n - * - * \note This event does not exist if the \c USB_DEVICE_ONLY or \c USB_HOST_ONLY tokens have been supplied - * to the compiler (see \ref Group_USBManagement documentation). - */ - void EVENT_USB_UIDChange(void); - - /** Event for USB host error. This event fires when a hardware fault has occurred whilst the USB - * interface is in host mode. - * - * \param[in] ErrorCode Error code indicating the failure reason, a value in \ref USB_Host_ErrorCodes_t. - * - * \note This event only exists on microcontrollers that supports USB host mode. - * \n\n - * - * \note This event does not exist if the \c USB_DEVICE_ONLY token is supplied to the compiler (see - * \ref Group_USBManagement documentation). - */ - void EVENT_USB_Host_HostError(const uint8_t ErrorCode); - - /** Event for USB device attachment. This event fires when a the USB interface is in host mode, and - * a USB device has been connected to the USB interface. This is interrupt driven, thus fires before - * the standard \ref EVENT_USB_Device_Connect() event and so can be used to programmatically start the USB - * management task to reduce CPU consumption. - * - * \note This event only exists on microcontrollers that supports USB host mode. - * \n\n - * - * \note This event does not exist if the \c USB_DEVICE_ONLY token is supplied to the compiler (see - * \ref Group_USBManagement documentation). - * - * \see \ref USB_USBTask() for more information on the USB management task and reducing CPU usage. - */ - void EVENT_USB_Host_DeviceAttached(void); - - /** Event for USB device removal. This event fires when a the USB interface is in host mode, and - * a USB device has been removed the USB interface whether or not it has been enumerated. This - * can be used to programmatically stop the USB management task to reduce CPU consumption. - * - * \note This event only exists on microcontrollers that supports USB host mode. - * \n\n - * - * \note This event does not exist if the \c USB_DEVICE_ONLY token is supplied to the compiler (see - * \ref Group_USBManagement documentation). - * - * \see \ref USB_USBTask() for more information on the USB management task and reducing CPU usage. - */ - void EVENT_USB_Host_DeviceUnattached(void); - - /** Event for USB device enumeration failure. This event fires when a the USB interface is - * in host mode, and an attached USB device has failed to enumerate completely. - * - * \param[in] ErrorCode Error code indicating the failure reason, a value in - * \ref USB_Host_EnumerationErrorCodes_t. - * - * \param[in] SubErrorCode Sub error code indicating the reason for failure - for example, if the - * ErrorCode parameter indicates a control error, this will give the error - * code returned by the \ref USB_Host_SendControlRequest() function. - * - * \note This event only exists on microcontrollers that supports USB host mode. - * \n\n - * - * \note This event does not exist if the \c USB_DEVICE_ONLY token is supplied to the compiler (see - * \ref Group_USBManagement documentation). - */ - void EVENT_USB_Host_DeviceEnumerationFailed(const uint8_t ErrorCode, - const uint8_t SubErrorCode); - - /** Event for USB device enumeration completion. This event fires when a the USB interface is - * in host mode and an attached USB device has been completely enumerated and is ready to be - * controlled by the user application. - * - * This event is time-critical; exceeding OS-specific delays within this event handler (typically of around - * 1 second) when a transaction is waiting to be processed by the device will prevent break communications - * and cause the host to reset the USB bus. - * - * \note This event only exists on microcontrollers that supports USB host mode. - * \n\n - * - * \note This event does not exist if the \c USB_DEVICE_ONLY token is supplied to the compiler (see - * \ref Group_USBManagement documentation). - */ - void EVENT_USB_Host_DeviceEnumerationComplete(void); - - /** Event for USB Start Of Frame detection, when enabled. This event fires at the start of each USB - * frame, once per millisecond, and is synchronized to the USB bus. This can be used as an accurate - * millisecond timer source when the USB bus is not suspended while in host mode. - * - * This event is time-critical; it is run once per millisecond and thus long handlers will significantly - * degrade device performance. This event should only be enabled when needed to reduce device wake-ups. - * - * \note This event is not normally active - it must be manually enabled and disabled via the - * \ref USB_Host_EnableSOFEvents() and \ref USB_Host_DisableSOFEvents() commands after enumeration of - * a USB device. - * \n\n - * - * \note This event does not exist if the \c USB_DEVICE_ONLY token is supplied to the compiler (see - * \ref Group_USBManagement documentation). - */ - void EVENT_USB_Host_StartOfFrame(void); - - /** Event for USB device connection. This event fires when the microcontroller is in USB Device mode - * and the device is connected to a USB host, beginning the enumeration process measured by a rising - * level on the microcontroller's VBUS sense pin. - * - * This event is time-critical; exceeding OS-specific delays within this event handler (typically of around - * two seconds) will prevent the device from enumerating correctly. - * - * \attention This event may fire multiple times during device enumeration on the microcontrollers with limited USB controllers - * if \c NO_LIMITED_CONTROLLER_CONNECT is not defined. - * - * \note For the microcontrollers with limited USB controller functionality, VBUS sensing is not available. - * this means that the current connection state is derived from the bus suspension and wake up events by default, - * which is not always accurate (host may suspend the bus while still connected). If the actual connection state - * needs to be determined, VBUS should be routed to an external pin, and the auto-detect behavior turned off by - * passing the \c NO_LIMITED_CONTROLLER_CONNECT token to the compiler via the -D switch at compile time. The connection - * and disconnection events may be manually fired, and the \ref USB_DeviceState global changed manually. - * \n\n - * - * \see \ref Group_USBManagement for more information on the USB management task and reducing CPU usage. - */ - void EVENT_USB_Device_Connect(void); - - /** Event for USB device disconnection. This event fires when the microcontroller is in USB Device mode and the device is - * disconnected from a host, measured by a falling level on the microcontroller's VBUS sense pin. - * - * \attention This event may fire multiple times during device enumeration on the microcontrollers with limited USB controllers - * if \c NO_LIMITED_CONTROLLER_CONNECT is not defined. - * - * \note For the microcontrollers with limited USB controllers, VBUS sense is not available to the USB controller. - * this means that the current connection state is derived from the bus suspension and wake up events by default, - * which is not always accurate (host may suspend the bus while still connected). If the actual connection state - * needs to be determined, VBUS should be routed to an external pin, and the auto-detect behavior turned off by - * passing the \c NO_LIMITED_CONTROLLER_CONNECT token to the compiler via the -D switch at compile time. The connection - * and disconnection events may be manually fired, and the \ref USB_DeviceState global changed manually. - * \n\n - * - * \see \ref Group_USBManagement for more information on the USB management task and reducing CPU usage. - */ - void EVENT_USB_Device_Disconnect(void); - - /** Event for control requests. This event fires when a the USB host issues a control request - * to the mandatory device control endpoint (of address 0). This may either be a standard - * request that the library may have a handler code for internally, or a class specific request - * issued to the device which must be handled appropriately. If a request is not processed in the - * user application via this event, it will be passed to the library for processing internally - * if a suitable handler exists. - * - * This event is time-critical; each packet within the request transaction must be acknowledged or - * sent within 50ms or the host will abort the transfer. - * - * The library internally handles all standard control requests with the exceptions of SYNC FRAME, - * SET DESCRIPTOR and SET INTERFACE. These and all other non-standard control requests will be left - * for the user to process via this event if desired. If not handled in the user application or by - * the library internally, unknown requests are automatically STALLed. - * - * \note This event does not exist if the \c USB_HOST_ONLY token is supplied to the compiler (see - * \ref Group_USBManagement documentation). - * \n\n - * - * \note Requests should be handled in the same manner as described in the USB 2.0 Specification, - * or appropriate class specification. In all instances, the library has already read the - * request SETUP parameters into the \ref USB_ControlRequest structure which should then be used - * by the application to determine how to handle the issued request. - */ - void EVENT_USB_Device_ControlRequest(void); - - /** Event for USB configuration number changed. This event fires when a the USB host changes the - * selected configuration number while in device mode. This event should be hooked in device - * applications to create the endpoints and configure the device for the selected configuration. - * - * This event is time-critical; exceeding OS-specific delays within this event handler (typically of around - * one second) will prevent the device from enumerating correctly. - * - * This event fires after the value of \ref USB_Device_ConfigurationNumber has been changed. - * - * \note This event does not exist if the \c USB_HOST_ONLY token is supplied to the compiler (see - * \ref Group_USBManagement documentation). - */ - void EVENT_USB_Device_ConfigurationChanged(void); - - /** Event for USB suspend. This event fires when a the USB host suspends the device by halting its - * transmission of Start Of Frame pulses to the device. This is generally hooked in order to move - * the device over to a low power state until the host wakes up the device. If the USB interface is - * enumerated with the \ref USB_OPT_AUTO_PLL option set, the library will automatically suspend the - * USB PLL before the event is fired to save power. - * - * \note This event does not exist if the \c USB_HOST_ONLY token is supplied to the compiler (see - * \ref Group_USBManagement documentation). - * \n\n - * - * \note This event does not exist on the microcontrollers with limited USB VBUS sensing abilities - * when the \c NO_LIMITED_CONTROLLER_CONNECT compile time token is not set - see - * \ref EVENT_USB_Device_Disconnect. - * - * \see \ref EVENT_USB_Device_WakeUp() event for accompanying Wake Up event. - */ - void EVENT_USB_Device_Suspend(void); - - /** Event for USB wake up. This event fires when a the USB interface is suspended while in device - * mode, and the host wakes up the device by supplying Start Of Frame pulses. This is generally - * hooked to pull the user application out of a low power state and back into normal operating - * mode. If the USB interface is enumerated with the \ref USB_OPT_AUTO_PLL option set, the library - * will automatically restart the USB PLL before the event is fired. - * - * \note This event does not exist if the \c USB_HOST_ONLY token is supplied to the compiler (see - * \ref Group_USBManagement documentation). - * \n\n - * - * \note This event does not exist on the microcontrollers with limited USB VBUS sensing abilities - * when the \c NO_LIMITED_CONTROLLER_CONNECT compile time token is not set - see - * \ref EVENT_USB_Device_Disconnect. - * - * \see \ref EVENT_USB_Device_Suspend() event for accompanying Suspend event. - */ - void EVENT_USB_Device_WakeUp(void); - - /** Event for USB interface reset. This event fires when the USB interface is in device mode, and - * a the USB host requests that the device reset its interface. This event fires after the control - * endpoint has been automatically configured by the library. - * - * This event is time-critical; exceeding OS-specific delays within this event handler (typically of around - * two seconds) will prevent the device from enumerating correctly. - * - * \note This event does not exist if the \c USB_HOST_ONLY token is supplied to the compiler (see - * \ref Group_USBManagement documentation). - */ - void EVENT_USB_Device_Reset(void); - - /** Event for USB Start Of Frame detection, when enabled. This event fires at the start of each USB - * frame, once per millisecond, and is synchronized to the USB bus. This can be used as an accurate - * millisecond timer source when the USB bus is enumerated in device mode to a USB host. - * - * This event is time-critical; it is run once per millisecond and thus long handlers will significantly - * degrade device performance. This event should only be enabled when needed to reduce device wake-ups. - * - * \pre This event is not normally active - it must be manually enabled and disabled via the - * \ref USB_Device_EnableSOFEvents() and \ref USB_Device_DisableSOFEvents() commands after enumeration. - * \n\n - * - * \note This event does not exist if the \c USB_HOST_ONLY token is supplied to the compiler (see - * \ref Group_USBManagement documentation). - */ - void EVENT_USB_Device_StartOfFrame(void); - #endif - - /* Private Interface - For use in library only: */ - #if !defined(__DOXYGEN__) - /* Function Prototypes: */ - #if defined(__INCLUDE_FROM_EVENTS_C) - void USB_Event_Stub(void) ATTR_CONST; - - #if defined(USB_CAN_BE_BOTH) - void EVENT_USB_UIDChange(void) ATTR_WEAK ATTR_ALIAS(USB_Event_Stub); - #endif - - #if defined(USB_CAN_BE_HOST) - #pragma weak EVENT_USB_Host_HostError=USB_Event_Stub - void EVENT_USB_Host_HostError(const uint8_t ErrorCode) ATTR_WEAK ATTR_ALIAS(USB_Event_Stub); - #pragma weak EVENT_USB_Host_DeviceAttached=USB_Event_Stub - void EVENT_USB_Host_DeviceAttached(void) ATTR_WEAK ATTR_ALIAS(USB_Event_Stub); - #pragma weak EVENT_USB_Host_DeviceUnattached=USB_Event_Stub - void EVENT_USB_Host_DeviceUnattached(void) ATTR_WEAK ATTR_ALIAS(USB_Event_Stub); - #pragma weak EVENT_USB_Host_DeviceEnumerationComplete=USB_Event_Stub - void EVENT_USB_Host_DeviceEnumerationComplete(void) ATTR_WEAK ATTR_ALIAS(USB_Event_Stub); - #pragma weak EVENT_USB_Host_DeviceEnumerationFailed=USB_Event_Stub - void EVENT_USB_Host_DeviceEnumerationFailed(const uint8_t ErrorCode, - const uint8_t SubErrorCode) - ATTR_WEAK ATTR_ALIAS(USB_Event_Stub); - #pragma weak EVENT_USB_Host_StartOfFrame=USB_Event_Stub - void EVENT_USB_Host_StartOfFrame(void) ATTR_WEAK ATTR_ALIAS(USB_Event_Stub); - #endif - - #if defined(USB_CAN_BE_DEVICE) - #pragma weak EVENT_USB_Device_Connect=USB_Event_Stub - void EVENT_USB_Device_Connect(void) ATTR_WEAK ATTR_ALIAS(USB_Event_Stub); - #pragma weak EVENT_USB_Device_Disconnect=USB_Event_Stub - void EVENT_USB_Device_Disconnect(void) ATTR_WEAK ATTR_ALIAS(USB_Event_Stub); - #pragma weak EVENT_USB_Device_ControlRequest=USB_Event_Stub - void EVENT_USB_Device_ControlRequest(void) ATTR_WEAK ATTR_ALIAS(USB_Event_Stub); - #pragma weak EVENT_USB_Device_ConfigurationChanged=USB_Event_Stub - void EVENT_USB_Device_ConfigurationChanged(void) ATTR_WEAK ATTR_ALIAS(USB_Event_Stub); - #pragma weak EVENT_USB_Device_Suspend=USB_Event_Stub - void EVENT_USB_Device_Suspend(void) ATTR_WEAK ATTR_ALIAS(USB_Event_Stub); - #pragma weak EVENT_USB_Device_WakeUp=USB_Event_Stub - void EVENT_USB_Device_WakeUp(void) ATTR_WEAK ATTR_ALIAS(USB_Event_Stub); - #pragma weak EVENT_USB_Device_Reset=USB_Event_Stub - void EVENT_USB_Device_Reset(void) ATTR_WEAK ATTR_ALIAS(USB_Event_Stub); - #pragma weak EVENT_USB_Device_StartOfFrame=USB_Event_Stub - void EVENT_USB_Device_StartOfFrame(void) ATTR_WEAK ATTR_ALIAS(USB_Event_Stub); - #endif - #endif - #endif - - /* Disable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - } - #endif - -#endif - -/** @} */ - - -#endif /* UC_FAMILY == XMC4 */ diff --git a/cores/usblib/Core/Host.h b/cores/usblib/Core/Host.h deleted file mode 100644 index 8cadfc56..00000000 --- a/cores/usblib/Core/Host.h +++ /dev/null @@ -1,143 +0,0 @@ -#ifdef XMC4_SERIES - -/* - LUFA Library - Copyright (C) Dean Camera, 2014. - - dean [at] fourwalledcubicle [dot] com - www.lufa-lib.org -*/ - -/* - Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com) - - Permission to use, copy, modify, distribute, and sell this - software and its documentation for any purpose is hereby granted - without fee, provided that the above copyright notice appear in - all copies and that both that the copyright notice and this - permission notice and warranty disclaimer appear in supporting - documentation, and that the name of the author not be used in - advertising or publicity pertaining to distribution of the - software without specific, written prior permission. - - The author disclaims all warranties with regard to this - software, including all implied warranties of merchantability - and fitness. In no event shall the author be liable for any - special, indirect or consequential damages or any damages - whatsoever resulting from loss of use, data or profits, whether - in an action of contract, negligence or other tortious action, - arising out of or in connection with the use or performance of - this software. -*/ - -/** \file - * \brief Common USB Host definitions for all architectures. - * \copydetails Group_Host - * - * \note This file should not be included directly. It is automatically included as needed by the USB driver - * dispatch header located in LUFA/Drivers/USB/USB.h. - */ - -/** \ingroup Group_USB - * \defgroup Group_Host Host Management - * \brief USB Host management definitions for USB host mode. - * - * USB Host mode related macros and enums. This module contains macros and enums which are used when - * the USB controller is initialized in host mode. - * - * @{ - */ - -#ifndef __USBHOST_H__ -#define __USBHOST_H__ - - /* Includes: */ - #include <../../../Common/Common.h> - #include - - /* Enable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - extern "C" { - #endif - - /* Preprocessor Checks: */ - #if !defined(__INCLUDE_FROM_USB_DRIVER) - #error Do not include this file directly. Include LUFA/Drivers/USB/USB.h instead. - #endif - - /* Public Interface - May be used in end-application: */ - /* Enums: */ - /** Enum for the various states of the USB Host state machine. - * - * For information on each possible USB host state, refer to the USB 2.0 specification. - * Several of the USB host states are broken up further into multiple smaller sub-states, - * so that they can be internally implemented inside the library in an efficient manner. - * - * \see \ref USB_HostState, which stores the current host state machine state. - */ - enum USB_Host_States_t - { - HOST_STATE_WaitForDevice = 0, /**< This state indicates that the stack is waiting for an interval - * to elapse before continuing with the next step of the device - * enumeration process. - */ - HOST_STATE_Unattached = 1, /**< This state indicates that the host state machine is waiting for - * a device to be attached so that it can start the enumeration process. - */ - HOST_STATE_Powered = 2, /**< This state indicates that a device has been attached, and the - * library's internals are being configured to begin the enumeration - * process. - */ - HOST_STATE_Powered_WaitForDeviceSettle = 3, /**< This state indicates that the stack is waiting for the initial - * settling period to elapse before beginning the enumeration process. - */ - HOST_STATE_Powered_WaitForConnect = 4, /**< This state indicates that the stack is waiting for a connection event - * from the USB controller to indicate a valid USB device has been attached - * to the bus and is ready to be enumerated. - */ - HOST_STATE_Powered_DoReset = 5, /**< This state indicates that a valid USB device has been attached, and that - * it will now be reset to ensure it is ready for enumeration. - */ - HOST_STATE_Powered_ConfigPipe = 6, /**< This state indicates that the attached device is currently powered and - * reset, and that the control pipe is now being configured by the stack. - */ - HOST_STATE_Default = 7, /**< This state indicates that the stack is currently retrieving the control - * endpoint's size from the device, so that the control pipe can be altered - * to match. - */ - HOST_STATE_Default_PostReset = 8, /**< This state indicates that the control pipe is being reconfigured to match - * the retrieved control endpoint size from the device, and the device's USB - * bus address is being set. - */ - HOST_STATE_Default_PostAddressSet = 9, /**< This state indicates that the device's address has now been set, and the - * stack is has now completed the device enumeration process. This state causes - * the stack to change the current USB device address to that set for the - * connected device, before progressing to the \ref HOST_STATE_Addressed state - * ready for use in the user application. - */ - HOST_STATE_Addressed = 10, /**< Indicates that the device has been enumerated and addressed, and is now waiting - * for the user application to configure the device ready for use. - */ - HOST_STATE_Configured = 11, /**< Indicates that the device has been configured into a valid device configuration, - * ready for general use by the user application. - */ - }; - - /* Architecture Includes: */ - #if (ARCH == ARCH_AVR8) - #include - #elif (ARCH == ARCH_UC3) - #include - #endif - - /* Disable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - } - #endif - -#endif - -/** @} */ - - -#endif /* UC_FAMILY == XMC4 */ diff --git a/cores/usblib/Core/HostStandardReq.c b/cores/usblib/Core/HostStandardReq.c deleted file mode 100644 index ac409159..00000000 --- a/cores/usblib/Core/HostStandardReq.c +++ /dev/null @@ -1,326 +0,0 @@ -#ifdef XMC4_SERIES - -/* - LUFA Library - Copyright (C) Dean Camera, 2014. - - dean [at] fourwalledcubicle [dot] com - www.lufa-lib.org -*/ - -/* - Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com) - - Permission to use, copy, modify, distribute, and sell this - software and its documentation for any purpose is hereby granted - without fee, provided that the above copyright notice appear in - all copies and that both that the copyright notice and this - permission notice and warranty disclaimer appear in supporting - documentation, and that the name of the author not be used in - advertising or publicity pertaining to distribution of the - software without specific, written prior permission. - - The author disclaims all warranties with regard to this - software, including all implied warranties of merchantability - and fitness. In no event shall the author be liable for any - special, indirect or consequential damages or any damages - whatsoever resulting from loss of use, data or profits, whether - in an action of contract, negligence or other tortious action, - arising out of or in connection with the use or performance of - this software. -*/ - -#define __INCLUDE_FROM_USB_DRIVER -#include - -#if defined(USB_CAN_BE_HOST) - -#define __INCLUDE_FROM_HOSTSTDREQ_C -#include - -uint8_t USB_Host_ConfigurationNumber; - -static uint8_t USB_Host_SendControlRequest_PRV(void* const BufferPtr) -{ - uint8_t* DataStream = (uint8_t*)BufferPtr; - uint8_t ReturnStatus = HOST_SENDCONTROL_Successful; - uint16_t DataLen = USB_ControlRequest.wLength; - - USB_Host_ResumeBus(); - - if ((ReturnStatus = USB_Host_WaitMS(1)) != HOST_WAITERROR_Successful) - return ReturnStatus; - - Pipe_SetPipeToken(PIPE_TOKEN_SETUP); - Pipe_ClearError(); - - Pipe_Unfreeze(); - - #if defined(ARCH_BIG_ENDIAN) - Pipe_Write_8(USB_ControlRequest.bmRequestType); - Pipe_Write_8(USB_ControlRequest.bRequest); - Pipe_Write_16_LE(USB_ControlRequest.wValue); - Pipe_Write_16_LE(USB_ControlRequest.wIndex); - Pipe_Write_16_LE(USB_ControlRequest.wLength); - #else - uint8_t* HeaderStream = (uint8_t*)&USB_ControlRequest; - - for (uint8_t HeaderByte = 0; HeaderByte < sizeof(USB_Request_Header_t); HeaderByte++) - Pipe_Write_8(*(HeaderStream++)); - #endif - - Pipe_ClearSETUP(); - - if ((ReturnStatus = USB_Host_WaitForIOS(USB_HOST_WAITFOR_SetupSent)) != HOST_SENDCONTROL_Successful) - return ReturnStatus; - - Pipe_Freeze(); - - if ((ReturnStatus = USB_Host_WaitMS(1)) != HOST_WAITERROR_Successful) - return ReturnStatus; - - if ((USB_ControlRequest.bmRequestType & CONTROL_REQTYPE_DIRECTION) == REQDIR_DEVICETOHOST) - { - Pipe_SetPipeToken(PIPE_TOKEN_IN); - - if (DataStream != NULL) - { - while (DataLen) - { - Pipe_Unfreeze(); - - if ((ReturnStatus = USB_Host_WaitForIOS(USB_HOST_WAITFOR_InReceived)) != HOST_SENDCONTROL_Successful) - return ReturnStatus; - - if (!(Pipe_BytesInPipe())) - DataLen = 0; - - while (Pipe_BytesInPipe() && DataLen) - { - *(DataStream++) = Pipe_Read_8(); - DataLen--; - } - - Pipe_Freeze(); - Pipe_ClearIN(); - } - } - - Pipe_SetPipeToken(PIPE_TOKEN_OUT); - Pipe_Unfreeze(); - - if ((ReturnStatus = USB_Host_WaitForIOS(USB_HOST_WAITFOR_OutReady)) != HOST_SENDCONTROL_Successful) - return ReturnStatus; - - Pipe_ClearOUT(); - - if ((ReturnStatus = USB_Host_WaitForIOS(USB_HOST_WAITFOR_OutReady)) != HOST_SENDCONTROL_Successful) - return ReturnStatus; - } - else - { - if (DataStream != NULL) - { - Pipe_SetPipeToken(PIPE_TOKEN_OUT); - Pipe_Unfreeze(); - - while (DataLen) - { - if ((ReturnStatus = USB_Host_WaitForIOS(USB_HOST_WAITFOR_OutReady)) != HOST_SENDCONTROL_Successful) - return ReturnStatus; - - while (DataLen && (Pipe_BytesInPipe() < USB_Host_ControlPipeSize)) - { - Pipe_Write_8(*(DataStream++)); - DataLen--; - } - - Pipe_ClearOUT(); - } - - if ((ReturnStatus = USB_Host_WaitForIOS(USB_HOST_WAITFOR_OutReady)) != HOST_SENDCONTROL_Successful) - return ReturnStatus; - - Pipe_Freeze(); - } - - Pipe_SetPipeToken(PIPE_TOKEN_IN); - Pipe_Unfreeze(); - - if ((ReturnStatus = USB_Host_WaitForIOS(USB_HOST_WAITFOR_InReceived)) != HOST_SENDCONTROL_Successful) - return ReturnStatus; - - Pipe_ClearIN(); - } - - return ReturnStatus; -} - -static uint8_t USB_Host_WaitForIOS(const uint8_t WaitType) -{ - #if (USB_HOST_TIMEOUT_MS < 0xFF) - uint8_t TimeoutCounter = USB_HOST_TIMEOUT_MS; - #else - uint16_t TimeoutCounter = USB_HOST_TIMEOUT_MS; - #endif - - while (!(((WaitType == USB_HOST_WAITFOR_SetupSent) && Pipe_IsSETUPSent()) || - ((WaitType == USB_HOST_WAITFOR_InReceived) && Pipe_IsINReceived()) || - ((WaitType == USB_HOST_WAITFOR_OutReady) && Pipe_IsOUTReady()))) - { - uint8_t ErrorCode; - - if ((ErrorCode = USB_Host_WaitMS(1)) != HOST_WAITERROR_Successful) - return ErrorCode; - - if (!(TimeoutCounter--)) - return HOST_SENDCONTROL_SoftwareTimeOut; - } - - return HOST_SENDCONTROL_Successful; -} - -uint8_t USB_Host_SendControlRequest(void* const BufferPtr) -{ - bool BusSuspended = USB_Host_IsBusSuspended(); - uint8_t ReturnStatus = USB_Host_SendControlRequest_PRV(BufferPtr); - - Pipe_Freeze(); - - if (BusSuspended) - USB_Host_SuspendBus(); - - Pipe_ResetPipe(PIPE_CONTROLPIPE); - - return ReturnStatus; -} - -uint8_t USB_Host_SetDeviceConfiguration(const uint8_t ConfigNumber) -{ - uint8_t ErrorCode; - - USB_ControlRequest = (USB_Request_Header_t) - { - .bmRequestType = (REQDIR_HOSTTODEVICE | REQTYPE_STANDARD | REQREC_DEVICE), - .bRequest = REQ_SetConfiguration, - .wValue = ConfigNumber, - .wIndex = 0, - .wLength = 0, - }; - - Pipe_SelectPipe(PIPE_CONTROLPIPE); - - if ((ErrorCode = USB_Host_SendControlRequest(NULL)) == HOST_SENDCONTROL_Successful) - { - USB_Host_ConfigurationNumber = ConfigNumber; - USB_HostState = (ConfigNumber) ? HOST_STATE_Configured : HOST_STATE_Addressed; - } - - return ErrorCode; -} - -uint8_t USB_Host_GetDeviceConfiguration(uint8_t* const ConfigNumber) -{ - USB_ControlRequest = (USB_Request_Header_t) - { - .bmRequestType = (REQDIR_DEVICETOHOST | REQTYPE_STANDARD | REQREC_DEVICE), - .bRequest = REQ_GetConfiguration, - .wValue = 0, - .wIndex = 0, - .wLength = sizeof(uint8_t), - }; - - Pipe_SelectPipe(PIPE_CONTROLPIPE); - - return USB_Host_SendControlRequest(ConfigNumber); -} - -uint8_t USB_Host_GetDescriptor(const uint8_t Type, - const uint8_t Index, - void* const Buffer, - const uint8_t BufferLength) -{ - USB_ControlRequest = (USB_Request_Header_t) - { - .bmRequestType = (REQDIR_DEVICETOHOST | REQTYPE_STANDARD | REQREC_DEVICE), - .bRequest = REQ_GetDescriptor, - .wValue = (((uint16_t)Type << 8) | Index), - .wIndex = 0, - .wLength = BufferLength, - }; - - Pipe_SelectPipe(PIPE_CONTROLPIPE); - - return USB_Host_SendControlRequest(Buffer); -} - -uint8_t USB_Host_GetDeviceStatus(uint8_t* const FeatureStatus) -{ - USB_ControlRequest = (USB_Request_Header_t) - { - .bmRequestType = (REQDIR_DEVICETOHOST | REQTYPE_STANDARD | REQREC_DEVICE), - .bRequest = REQ_GetStatus, - .wValue = 0, - .wIndex = 0, - .wLength = 0, - }; - - Pipe_SelectPipe(PIPE_CONTROLPIPE); - - return USB_Host_SendControlRequest(FeatureStatus); -} - -uint8_t USB_Host_ClearEndpointStall(const uint8_t EndpointAddress) -{ - USB_ControlRequest = (USB_Request_Header_t) - { - .bmRequestType = (REQDIR_HOSTTODEVICE | REQTYPE_STANDARD | REQREC_ENDPOINT), - .bRequest = REQ_ClearFeature, - .wValue = FEATURE_SEL_EndpointHalt, - .wIndex = EndpointAddress, - .wLength = 0, - }; - - Pipe_SelectPipe(PIPE_CONTROLPIPE); - - return USB_Host_SendControlRequest(NULL); -} - -uint8_t USB_Host_SetInterfaceAltSetting(const uint8_t InterfaceIndex, - const uint8_t AltSetting) -{ - USB_ControlRequest = (USB_Request_Header_t) - { - .bmRequestType = (REQDIR_HOSTTODEVICE | REQTYPE_STANDARD | REQREC_INTERFACE), - .bRequest = REQ_SetInterface, - .wValue = AltSetting, - .wIndex = InterfaceIndex, - .wLength = 0, - }; - - Pipe_SelectPipe(PIPE_CONTROLPIPE); - - return USB_Host_SendControlRequest(NULL); -} - -uint8_t USB_Host_GetInterfaceAltSetting(const uint8_t InterfaceIndex, - uint8_t* const AltSetting) -{ - USB_ControlRequest = (USB_Request_Header_t) - { - .bmRequestType = (REQDIR_DEVICETOHOST | REQTYPE_STANDARD | REQREC_INTERFACE), - .bRequest = REQ_GetInterface, - .wValue = 0, - .wIndex = InterfaceIndex, - .wLength = sizeof(uint8_t), - }; - - Pipe_SelectPipe(PIPE_CONTROLPIPE); - - return USB_Host_SendControlRequest(AltSetting); -} - -#endif - - -#endif /* UC_FAMILY == XMC4 */ diff --git a/cores/usblib/Core/HostStandardReq.h b/cores/usblib/Core/HostStandardReq.h deleted file mode 100644 index 2684af18..00000000 --- a/cores/usblib/Core/HostStandardReq.h +++ /dev/null @@ -1,296 +0,0 @@ -#ifdef XMC4_SERIES - -/* - LUFA Library - Copyright (C) Dean Camera, 2014. - - dean [at] fourwalledcubicle [dot] com - www.lufa-lib.org -*/ - -/* - Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com) - - Permission to use, copy, modify, distribute, and sell this - software and its documentation for any purpose is hereby granted - without fee, provided that the above copyright notice appear in - all copies and that both that the copyright notice and this - permission notice and warranty disclaimer appear in supporting - documentation, and that the name of the author not be used in - advertising or publicity pertaining to distribution of the - software without specific, written prior permission. - - The author disclaims all warranties with regard to this - software, including all implied warranties of merchantability - and fitness. In no event shall the author be liable for any - special, indirect or consequential damages or any damages - whatsoever resulting from loss of use, data or profits, whether - in an action of contract, negligence or other tortious action, - arising out of or in connection with the use or performance of - this software. -*/ - -/** \file - * \brief USB host standard request management. - * - * This file contains the function prototypes necessary for the issuing of outgoing standard control requests - * when the library is in USB host mode. - * - * \note This file should not be included directly. It is automatically included as needed by the USB driver - * dispatch header located in LUFA/Drivers/USB/USB.h. - */ - -#ifndef __HOSTSTDREQ_H__ -#define __HOSTSTDREQ_H__ - - /* Includes: */ - #include <../Common/Common.h> - #include - #include - #include - - /* Enable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - extern "C" { - #endif - - /* Preprocessor Checks: */ - #if !defined(__INCLUDE_FROM_USB_DRIVER) - #error Do not include this file directly. Include LUFA/Drivers/USB/USB.h instead. - #endif - - /* Public Interface - May be used in end-application: */ - /* Macros: */ - #if !defined(USB_HOST_TIMEOUT_MS) || defined(__DOXYGEN__) - /** Constant for the maximum software timeout period of sent USB control transactions to an attached - * device. If a device fails to respond to a sent control request within this period, the - * library will return a timeout error code. - * - * This value may be overridden in the user project makefile as the value of the - * \ref USB_HOST_TIMEOUT_MS token, and passed to the compiler using the -D switch. - */ - #define USB_HOST_TIMEOUT_MS 1000 - #endif - - /* Enums: */ - /** Enum for the \ref USB_Host_SendControlRequest() return code, indicating the reason for the error - * if the transfer of the request is unsuccessful. - * - * \ingroup Group_PipeControlReq - */ - enum USB_Host_SendControlErrorCodes_t - { - HOST_SENDCONTROL_Successful = 0, /**< No error occurred in the request transfer. */ - HOST_SENDCONTROL_DeviceDisconnected = 1, /**< The attached device was disconnected during the - * request transfer. - */ - HOST_SENDCONTROL_PipeError = 2, /**< An error occurred in the pipe while sending the request. */ - HOST_SENDCONTROL_SetupStalled = 3, /**< The attached device stalled the request, usually - * indicating that the request is unsupported on the device. - */ - HOST_SENDCONTROL_SoftwareTimeOut = 4, /**< The request or data transfer timed out. */ - }; - - /* Global Variables: */ - /** Indicates the currently set configuration number of the attached device. This indicates the currently - * selected configuration value if one has been set successfully, or 0 if no configuration has been selected. - * - * To set a device configuration, call the \ref USB_Host_SetDeviceConfiguration() function. - * - * \attention This variable should be treated as read-only in the user application, and never manually - * changed in value. - * - * \ingroup Group_Host - */ - extern uint8_t USB_Host_ConfigurationNumber; - - /* Function Prototypes: */ - /** Sends the request stored in the \ref USB_ControlRequest global structure to the attached device, - * and transfers the data stored in the buffer to the device, or from the device to the buffer - * as requested. The transfer is made on the currently selected pipe. - * - * \ingroup Group_PipeControlReq - * - * \param[in] BufferPtr Pointer to the start of the data buffer if the request has a data stage, or - * \c NULL if the request transfers no data to or from the device. - * - * \return A value from the \ref USB_Host_SendControlErrorCodes_t enum to indicate the result. - */ - uint8_t USB_Host_SendControlRequest(void* const BufferPtr); - - /** Sends a SET CONFIGURATION standard request to the attached device, with the given configuration index. - * - * This routine will automatically update the \ref USB_HostState and \ref USB_Host_ConfigurationNumber - * state variables according to the given function parameters and the result of the request. - * - * \note After this routine returns, the control pipe will be selected. - * - * \ingroup Group_PipeControlReq - * - * \param[in] ConfigNumber Configuration index to send to the device. - * - * \return A value from the \ref USB_Host_SendControlErrorCodes_t enum to indicate the result. - */ - uint8_t USB_Host_SetDeviceConfiguration(const uint8_t ConfigNumber); - - /** Sends a GET CONFIGURATION standard request to the attached device, to retrieve the currently selected - * device configuration index. - * - * \note After this routine returns, the control pipe will be selected. - * - * \ingroup Group_PipeControlReq - * - * \param[out] ConfigNumber Pointer to a location where the retrieved configuration index should be stored. - * - * \return A value from the \ref USB_Host_SendControlErrorCodes_t enum to indicate the result. - */ - uint8_t USB_Host_GetDeviceConfiguration(uint8_t* const ConfigNumber) ATTR_NON_NULL_PTR_ARG(1); - - /** Sends a GET DESCRIPTOR standard request to the attached device, requesting the descriptor of the - * specified type and index. - * - * \note After this routine returns, the control pipe will be selected. - * - * \ingroup Group_PipeControlReq - * - * \param[in] Type Type of descriptor to retrieve, a value from the \ref USB_DescriptorTypes_t enum. - * \param[in] Index Index of the descriptor to retrieve. - * \param[out] Buffer Pointer to the destination buffer where the retrieved string descriptor is to be stored. - * \param[in] BufferLength Maximum size of the string descriptor which can be stored into the buffer. - * - * \return A value from the \ref USB_Host_SendControlErrorCodes_t enum to indicate the result. - */ - uint8_t USB_Host_GetDescriptor(const uint8_t Type, - const uint8_t Index, - void* const Buffer, - const uint8_t BufferLength) ATTR_NON_NULL_PTR_ARG(3); - - /** Retrieves the current feature status of the attached device, via a GET STATUS standard request. The - * retrieved feature status can then be examined by masking the retrieved value with the various - * \c FEATURE_* masks for bus/self power information and remote wakeup support. - * - * \note After this routine returns, the control pipe will be selected. - * - * \ingroup Group_PipeControlReq - * - * \param[out] FeatureStatus Location where the retrieved feature status should be stored. - * - * \return A value from the \ref USB_Host_SendControlErrorCodes_t enum to indicate the result. - */ - uint8_t USB_Host_GetDeviceStatus(uint8_t* const FeatureStatus) ATTR_NON_NULL_PTR_ARG(1); - - /** Clears a stall condition on the given pipe, via a CLEAR FEATURE standard request to the attached device. - * - * \note After this routine returns, the control pipe will be selected. - * - * \ingroup Group_PipeControlReq - * - * \param[in] EndpointAddress Address of the endpoint to clear, including the endpoint's direction. - * - * \return A value from the \ref USB_Host_SendControlErrorCodes_t enum to indicate the result. - */ - uint8_t USB_Host_ClearEndpointStall(const uint8_t EndpointAddress); - - /** Selects a given alternative setting for the specified interface, via a SET INTERFACE standard request to - * the attached device. - * - * \note After this routine returns, the control pipe will be selected. - * - * \ingroup Group_PipeControlReq - * - * \param[in] InterfaceIndex Index of the interface whose alternative setting is to be altered. - * \param[in] AltSetting Index of the interface's alternative setting which is to be selected. - * - * \return A value from the \ref USB_Host_SendControlErrorCodes_t enum to indicate the result. - */ - uint8_t USB_Host_SetInterfaceAltSetting(const uint8_t InterfaceIndex, - const uint8_t AltSetting); - - - /** Retrieves the current alternative setting for the specified interface, via a GET INTERFACE standard request to - * the attached device. - * - * \note After this routine returns, the control pipe will be selected. - * - * \ingroup Group_PipeControlReq - * - * \param[in] InterfaceIndex Index of the interface whose alternative setting is to be altered. - * \param[out] AltSetting Pointer to a location where the retrieved alternative setting value should be stored. - * - * \return A value from the \ref USB_Host_SendControlErrorCodes_t enum to indicate the result. - */ - uint8_t USB_Host_GetInterfaceAltSetting(const uint8_t InterfaceIndex, - uint8_t* const AltSetting) ATTR_NON_NULL_PTR_ARG(2); - - /* Inline Functions: */ - /** Sends a GET DESCRIPTOR standard request to the attached device, requesting the device descriptor. - * This can be used to easily retrieve information about the device such as its VID, PID and power - * requirements. This is a convenience wrapper for \ref USB_Host_GetDescriptor(). - * - * \note After this routine returns, the control pipe will be selected. - * - * \ingroup Group_PipeControlReq - * - * \param[out] DeviceDescriptorPtr Pointer to the destination device descriptor structure where - * the read data is to be stored. - * - * \return A value from the \ref USB_Host_SendControlErrorCodes_t enum to indicate the result. - */ - static inline uint8_t USB_Host_GetDeviceDescriptor(USB_Descriptor_Device_t* const DeviceDescriptorPtr) ATTR_NON_NULL_PTR_ARG(1); - static inline uint8_t USB_Host_GetDeviceDescriptor(USB_Descriptor_Device_t* const DeviceDescriptorPtr) - { - return USB_Host_GetDescriptor(DTYPE_Device, 0, DeviceDescriptorPtr, sizeof(USB_Descriptor_Device_t)); - } - - /** Sends a GET DESCRIPTOR standard request to the attached device, requesting the string descriptor - * of the specified index. This can be used to easily retrieve string descriptors from the device by - * index, after the index is obtained from the Device or Configuration descriptors. This is a convenience - * wrapper for \ref USB_Host_GetDescriptor(). - * - * \note After this routine returns, the control pipe will be selected. - * - * \ingroup Group_PipeControlReq - * - * \param[in] Index Index of the string descriptor to retrieve. - * \param[out] Buffer Pointer to the destination buffer where the retrieved string descriptor is - * to be stored. - * \param[in] BufferLength Maximum size of the string descriptor which can be stored into the buffer. - * - * \return A value from the \ref USB_Host_SendControlErrorCodes_t enum to indicate the result. - */ - static inline uint8_t USB_Host_GetDeviceStringDescriptor(const uint8_t Index, - void* const Buffer, - const uint8_t BufferLength) ATTR_NON_NULL_PTR_ARG(2); - static inline uint8_t USB_Host_GetDeviceStringDescriptor(const uint8_t Index, - void* const Buffer, - const uint8_t BufferLength) - { - return USB_Host_GetDescriptor(DTYPE_String, Index, Buffer, BufferLength); - } - - /* Private Interface - For use in library only: */ - #if !defined(__DOXYGEN__) - /* Enums: */ - enum USB_WaitForTypes_t - { - USB_HOST_WAITFOR_SetupSent, - USB_HOST_WAITFOR_InReceived, - USB_HOST_WAITFOR_OutReady, - }; - - /* Function Prototypes: */ - #if defined(__INCLUDE_FROM_HOSTSTDREQ_C) - static uint8_t USB_Host_SendControlRequest_PRV(void* const BufferPtr); - static uint8_t USB_Host_WaitForIOS(const uint8_t WaitType); - #endif - #endif - - /* Disable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - } - #endif - -#endif - - -#endif /* UC_FAMILY == XMC4 */ diff --git a/cores/usblib/Core/OTG.h b/cores/usblib/Core/OTG.h deleted file mode 100644 index 7281c433..00000000 --- a/cores/usblib/Core/OTG.h +++ /dev/null @@ -1,79 +0,0 @@ -#ifdef XMC4_SERIES - -/* - LUFA Library - Copyright (C) Dean Camera, 2014. - - dean [at] fourwalledcubicle [dot] com - www.lufa-lib.org -*/ - -/* - Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com) - - Permission to use, copy, modify, distribute, and sell this - software and its documentation for any purpose is hereby granted - without fee, provided that the above copyright notice appear in - all copies and that both that the copyright notice and this - permission notice and warranty disclaimer appear in supporting - documentation, and that the name of the author not be used in - advertising or publicity pertaining to distribution of the - software without specific, written prior permission. - - The author disclaims all warranties with regard to this - software, including all implied warranties of merchantability - and fitness. In no event shall the author be liable for any - special, indirect or consequential damages or any damages - whatsoever resulting from loss of use, data or profits, whether - in an action of contract, negligence or other tortious action, - arising out of or in connection with the use or performance of - this software. -*/ - -/** \file - * \brief Common USB OTG definitions for all architectures. - * \copydetails Group_OTG - * - * \note This file should not be included directly. It is automatically included as needed by the USB driver - * dispatch header located in LUFA/Drivers/USB/USB.h. - */ - -/** \ingroup Group_USB - * \defgroup Group_OTG USB On The Go (OTG) Management - * \brief USB OTG management definitions. - * - * This module contains macros for embedded USB hosts with dual role On The Go capabilities, for managing role - * exchange. OTG is a way for two USB dual role devices to talk to one another directly without fixed device/host - * roles. - * - * @{ - */ - -#ifndef __USBOTG_H__ -#define __USBOTG_H__ - - /* Includes: */ - #include <../Common/Common.h> - #include - - /* Enable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - extern "C" { - #endif - - /* Preprocessor Checks: */ - #if !defined(__INCLUDE_FROM_USB_DRIVER) - #error Do not include this file directly. Include LUFA/Drivers/USB/USB.h instead. - #endif - - /* Disable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - } - #endif - -#endif - -/** @} */ - - -#endif /* UC_FAMILY == XMC4 */ diff --git a/cores/usblib/Core/Pipe.h b/cores/usblib/Core/Pipe.h deleted file mode 100644 index a45a98ba..00000000 --- a/cores/usblib/Core/Pipe.h +++ /dev/null @@ -1,143 +0,0 @@ -#ifdef XMC4_SERIES - -/* - LUFA Library - Copyright (C) Dean Camera, 2014. - - dean [at] fourwalledcubicle [dot] com - www.lufa-lib.org -*/ - -/* - Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com) - - Permission to use, copy, modify, distribute, and sell this - software and its documentation for any purpose is hereby granted - without fee, provided that the above copyright notice appear in - all copies and that both that the copyright notice and this - permission notice and warranty disclaimer appear in supporting - documentation, and that the name of the author not be used in - advertising or publicity pertaining to distribution of the - software without specific, written prior permission. - - The author disclaims all warranties with regard to this - software, including all implied warranties of merchantability - and fitness. In no event shall the author be liable for any - special, indirect or consequential damages or any damages - whatsoever resulting from loss of use, data or profits, whether - in an action of contract, negligence or other tortious action, - arising out of or in connection with the use or performance of - this software. -*/ - -/** \file - * \brief Common USB Pipe definitions for all architectures. - * \copydetails Group_PipeManagement - * - * \note This file should not be included directly. It is automatically included as needed by the USB driver - * dispatch header located in USB/USB.h. - */ - -/** \ingroup Group_PipeManagement - * \defgroup Group_PipeRW Pipe Data Reading and Writing - * \brief Pipe data read/write definitions. - * - * Functions, macros, variables, enums and types related to data reading and writing from and to pipes. - */ - -/** \ingroup Group_PipeRW - * \defgroup Group_PipePrimitiveRW Read/Write of Primitive Data Types - * \brief Pipe data primitive read/write definitions. - * - * Functions, macros, variables, enums and types related to data reading and writing of primitive data types - * from and to pipes. - */ - -/** \ingroup Group_PipeManagement - * \defgroup Group_PipePacketManagement Pipe Packet Management - * \brief Pipe packet management definitions. - * - * Functions, macros, variables, enums and types related to packet management of pipes. - */ - -/** \ingroup Group_PipeManagement - * \defgroup Group_PipeControlReq Pipe Control Request Management - * \brief Pipe control request definitions. - * - * Module for host mode request processing. This module allows for the transmission of standard, class and - * vendor control requests to the default control endpoint of an attached device while in host mode. - * - * \see Chapter 9 of the USB 2.0 specification. - */ - -/** \ingroup Group_USB - * \defgroup Group_PipeManagement Pipe Management - * \brief Pipe management definitions. - * - * This module contains functions, macros and enums related to pipe management when in USB Host mode. This - * module contains the pipe management macros, as well as pipe interrupt and data send/receive functions - * for various data types. - * - * @{ - */ - -#ifndef __PIPE_H__ -#define __PIPE_H__ - - /* Includes: */ - #include <../Common/Common.h> - #include - - /* Enable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - extern "C" { - #endif - - /* Preprocessor Checks: */ - #if !defined(__INCLUDE_FROM_USB_DRIVER) - #error Do not include this file directly. Include LUFA/Drivers/USB/USB.h instead. - #endif - - /* Public Interface - May be used in end-application: */ - /* Type Defines: */ - /** Type define for a pipe table entry, used to configure pipes in groups via - * \ref Pipe_ConfigurePipeTable(). - */ - typedef struct - { - uint8_t Address; /**< Address of the pipe to configure, or zero if the table entry is to be unused. */ - uint16_t Size; /**< Size of the pipe bank, in bytes. */ - uint8_t EndpointAddress; /**< Address of the endpoint in the connected device. */ - uint8_t Type; /**< Type of the endpoint, a \c EP_TYPE_* mask. */ - uint8_t Banks; /**< Number of hardware banks to use for the pipe. */ - } USB_Pipe_Table_t; - - /* Macros: */ - /** Pipe address for the default control pipe, which always resides in address 0. This is - * defined for convenience to give more readable code when used with the pipe macros. - */ - #define PIPE_CONTROLPIPE 0 - - /** Pipe number mask, for masking against pipe addresses to retrieve the pipe's numerical address - * in the device. - */ - #define PIPE_PIPENUM_MASK 0x0F - - /** Endpoint number mask, for masking against endpoint addresses to retrieve the endpoint's - * numerical address in the attached device. - */ - #define PIPE_EPNUM_MASK 0x0F - - /* Architecture Includes: */ - - /* Disable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - } - #endif - -#endif - -/** @} */ - - -#endif /* UC_FAMILY == XMC4 */ diff --git a/cores/usblib/Core/PipeStream.h b/cores/usblib/Core/PipeStream.h deleted file mode 100644 index 3b5f69c8..00000000 --- a/cores/usblib/Core/PipeStream.h +++ /dev/null @@ -1,99 +0,0 @@ -#ifdef XMC4_SERIES - -/* - LUFA Library - Copyright (C) Dean Camera, 2014. - - dean [at] fourwalledcubicle [dot] com - www.lufa-lib.org -*/ - -/* - Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com) - - Permission to use, copy, modify, distribute, and sell this - software and its documentation for any purpose is hereby granted - without fee, provided that the above copyright notice appear in - all copies and that both that the copyright notice and this - permission notice and warranty disclaimer appear in supporting - documentation, and that the name of the author not be used in - advertising or publicity pertaining to distribution of the - software without specific, written prior permission. - - The author disclaims all warranties with regard to this - software, including all implied warranties of merchantability - and fitness. In no event shall the author be liable for any - special, indirect or consequential damages or any damages - whatsoever resulting from loss of use, data or profits, whether - in an action of contract, negligence or other tortious action, - arising out of or in connection with the use or performance of - this software. -*/ - -/** \file - * \brief Pipe data stream transmission and reception management. - * \copydetails Group_PipeStreamRW - * - * \note This file should not be included directly. It is automatically included as needed by the USB driver - * dispatch header located in LUFA/Drivers/USB/USB.h. - */ - -/** \ingroup Group_PipeRW - * \defgroup Group_PipeStreamRW Read/Write of Multi-Byte Streams - * \brief Pipe data stream transmission and reception management. - * - * Functions, macros, variables, enums and types related to data reading and writing of data streams from - * and to pipes. - * - * @{ - */ - -#ifndef __PIPE_STREAM_H__ -#define __PIPE_STREAM_H__ - - /* Includes: */ - #include <../Common/Common.h> - #include - - /* Enable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - extern "C" { - #endif - - /* Preprocessor Checks: */ - #if !defined(__INCLUDE_FROM_USB_DRIVER) - #error Do not include this file directly. Include LUFA/Drivers/USB/USB.h instead. - #endif - - /* Public Interface - May be used in end-application: */ - /* Enums: */ - /** Enum for the possible error return codes of the Pipe_*_Stream_* functions. */ - enum Pipe_Stream_RW_ErrorCodes_t - { - PIPE_RWSTREAM_NoError = 0, /**< Command completed successfully, no error. */ - PIPE_RWSTREAM_PipeStalled = 1, /**< The device stalled the pipe during the transfer. */ - PIPE_RWSTREAM_DeviceDisconnected = 2, /**< Device was disconnected from the host during - * the transfer. - */ - PIPE_RWSTREAM_Timeout = 3, /**< The device failed to accept or send the next packet - * within the software timeout period set by the - * \ref USB_STREAM_TIMEOUT_MS macro. - */ - PIPE_RWSTREAM_IncompleteTransfer = 4, /**< Indicates that the pipe bank became full/empty before the - * complete contents of the stream could be transferred. - */ - }; - - /* Architecture Includes: */ - - /* Disable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - } - #endif - -#endif - -/** @} */ - - -#endif /* UC_FAMILY == XMC4 */ diff --git a/cores/usblib/Core/StdDescriptors.h b/cores/usblib/Core/StdDescriptors.h deleted file mode 100644 index 977b0762..00000000 --- a/cores/usblib/Core/StdDescriptors.h +++ /dev/null @@ -1,775 +0,0 @@ -#ifdef XMC4_SERIES - -/* - LUFA Library - Copyright (C) Dean Camera, 2014. - - dean [at] fourwalledcubicle [dot] com - www.lufa-lib.org -*/ - -/* - Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com) - - Permission to use, copy, modify, distribute, and sell this - software and its documentation for any purpose is hereby granted - without fee, provided that the above copyright notice appear in - all copies and that both that the copyright notice and this - permission notice and warranty disclaimer appear in supporting - documentation, and that the name of the author not be used in - advertising or publicity pertaining to distribution of the - software without specific, written prior permission. - - The author disclaims all warranties with regard to this - software, including all implied warranties of merchantability - and fitness. In no event shall the author be liable for any - special, indirect or consequential damages or any damages - whatsoever resulting from loss of use, data or profits, whether - in an action of contract, negligence or other tortious action, - arising out of or in connection with the use or performance of - this software. -*/ - -/** \file - * \brief Common standard USB Descriptor definitions for all architectures. - * \copydetails Group_StdDescriptors - * - * \note This file should not be included directly. It is automatically included as needed by the USB driver - * dispatch header located in LUFA/Drivers/USB/USB.h. - */ - -/** \ingroup Group_USB - * \defgroup Group_StdDescriptors USB Descriptors - * \brief Standard USB Descriptor definitions. - * - * Standard USB device descriptor defines and retrieval routines, for USB devices. This module contains - * structures and macros for the easy creation of standard USB descriptors in USB device projects. - * - * @{ - */ - -#ifndef __USBDESCRIPTORS_H__ -#define __USBDESCRIPTORS_H__ - - /* Includes: */ - #include <../Common/Common.h> - #include - #include - - /* Enable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - extern "C" { - #endif - - /* Preprocessor Checks: */ - #if !defined(__INCLUDE_FROM_USB_DRIVER) - #error Do not include this file directly. Include LUFA/Drivers/USB/USB.h instead. - #endif - - /* Public Interface - May be used in end-application: */ - /* Macros: */ - /** Indicates that a given descriptor does not exist in the device. This can be used inside descriptors - * for string descriptor indexes, or may be use as a return value for GetDescriptor when the specified - * descriptor does not exist. - */ - #define NO_DESCRIPTOR 0 - - /** Macro to calculate the power value for the configuration descriptor, from a given number of milliamperes. - * - * \param[in] mA Maximum number of milliamps the device consumes when the given configuration is selected. - */ - #define USB_CONFIG_POWER_MA(mA) ((mA) >> 1) - - /** Macro to calculate the Unicode length of a string with a given number of Unicode characters. - * Should be used in string descriptor's headers for giving the string descriptor's byte length. - * - * \param[in] UnicodeChars Number of Unicode characters in the string text. - */ - #define USB_STRING_LEN(UnicodeChars) (sizeof(USB_Descriptor_Header_t) + ((UnicodeChars) << 1)) - - /** Convenience macro to easily create \ref USB_Descriptor_String_t instances from a wide character string. - * - * \note This macro is for little-endian systems only. - * - * \param[in] String String to initialize a USB String Descriptor structure with. - */ - #define USB_STRING_DESCRIPTOR(String) { .Header = {.Size = sizeof(USB_Descriptor_Header_t) + (sizeof(String) - 2), .Type = DTYPE_String}, .UnicodeString = String } - - /** Convenience macro to easily create \ref USB_Descriptor_String_t instances from an array of characters. - * - * \param[in] ... Characters to initialize a USB String Descriptor structure with. - */ - #define USB_STRING_DESCRIPTOR_ARRAY(...) { .Header = {.Size = sizeof(USB_Descriptor_Header_t) + sizeof((uint16_t){__VA_ARGS__}), .Type = DTYPE_String}, .UnicodeString = {__VA_ARGS__} } - - /** Macro to encode a given major/minor/revision version number into Binary Coded Decimal format for descriptor - * fields requiring BCD encoding, such as the USB version number in the standard device descriptor. - * - * \note This value is automatically converted into Little Endian, suitable for direct use inside device - * descriptors on all architectures without endianness conversion macros. - * - * \param[in] Major Major version number to encode. - * \param[in] Minor Minor version number to encode. - * \param[in] Revision Revision version number to encode. - */ - #define VERSION_BCD(Major, Minor, Revision) \ - CPU_TO_LE16( ((Major & 0xFF) << 8) | \ - ((Minor & 0x0F) << 4) | \ - (Revision & 0x0F) ) - - /** String language ID for the English language. Should be used in \ref USB_Descriptor_String_t descriptors - * to indicate that the English language is supported by the device in its string descriptors. - */ - #define LANGUAGE_ID_ENG 0x0409 - - /** \name USB Configuration Descriptor Attribute Masks */ - //@{ - /** Mask for the reserved bit in the Configuration Descriptor's \c ConfigAttributes field, which must be set on all - * devices for historical purposes. - */ - #define USB_CONFIG_ATTR_RESERVED 0x80 - - /** Can be masked with other configuration descriptor attributes for a \ref USB_Descriptor_Configuration_Header_t - * descriptor's \c ConfigAttributes value to indicate that the specified configuration can draw its power - * from the device's own power source. - */ - #define USB_CONFIG_ATTR_SELFPOWERED 0x40 - - /** Can be masked with other configuration descriptor attributes for a \ref USB_Descriptor_Configuration_Header_t - * descriptor's \c ConfigAttributes value to indicate that the specified configuration supports the - * remote wakeup feature of the USB standard, allowing a suspended USB device to wake up the host upon - * request. - */ - #define USB_CONFIG_ATTR_REMOTEWAKEUP 0x20 - //@} - - /** \name Endpoint Descriptor Attribute Masks */ - //@{ - /** Can be masked with other endpoint descriptor attributes for a \ref USB_Descriptor_Endpoint_t descriptor's - * \c Attributes value to indicate that the specified endpoint is not synchronized. - * - * \see The USB specification for more details on the possible Endpoint attributes. - */ - #define ENDPOINT_ATTR_NO_SYNC (0 << 2) - - /** Can be masked with other endpoint descriptor attributes for a \ref USB_Descriptor_Endpoint_t descriptor's - * \c Attributes value to indicate that the specified endpoint is asynchronous. - * - * \see The USB specification for more details on the possible Endpoint attributes. - */ - #define ENDPOINT_ATTR_ASYNC (1 << 2) - - /** Can be masked with other endpoint descriptor attributes for a \ref USB_Descriptor_Endpoint_t descriptor's - * \c Attributes value to indicate that the specified endpoint is adaptive. - * - * \see The USB specification for more details on the possible Endpoint attributes. - */ - #define ENDPOINT_ATTR_ADAPTIVE (2 << 2) - - /** Can be masked with other endpoint descriptor attributes for a \ref USB_Descriptor_Endpoint_t descriptor's - * \c Attributes value to indicate that the specified endpoint is synchronized. - * - * \see The USB specification for more details on the possible Endpoint attributes. - */ - #define ENDPOINT_ATTR_SYNC (3 << 2) - //@} - - /** \name Endpoint Descriptor Usage Masks */ - //@{ - /** Can be masked with other endpoint descriptor attributes for a \ref USB_Descriptor_Endpoint_t descriptor's - * \c Attributes value to indicate that the specified endpoint is used for data transfers. - * - * \see The USB specification for more details on the possible Endpoint usage attributes. - */ - #define ENDPOINT_USAGE_DATA (0 << 4) - - /** Can be masked with other endpoint descriptor attributes for a \ref USB_Descriptor_Endpoint_t descriptor's - * \c Attributes value to indicate that the specified endpoint is used for feedback. - * - * \see The USB specification for more details on the possible Endpoint usage attributes. - */ - #define ENDPOINT_USAGE_FEEDBACK (1 << 4) - - /** Can be masked with other endpoint descriptor attributes for a \ref USB_Descriptor_Endpoint_t descriptor's - * \c Attributes value to indicate that the specified endpoint is used for implicit feedback. - * - * \see The USB specification for more details on the possible Endpoint usage attributes. - */ - #define ENDPOINT_USAGE_IMPLICIT_FEEDBACK (2 << 4) - //@} - - /* Enums: */ - /** Enum for the possible standard descriptor types, as given in each descriptor's header. */ - enum USB_DescriptorTypes_t - { - DTYPE_Device = 0x01, /**< Indicates that the descriptor is a device descriptor. */ - DTYPE_Configuration = 0x02, /**< Indicates that the descriptor is a configuration descriptor. */ - DTYPE_String = 0x03, /**< Indicates that the descriptor is a string descriptor. */ - DTYPE_Interface = 0x04, /**< Indicates that the descriptor is an interface descriptor. */ - DTYPE_Endpoint = 0x05, /**< Indicates that the descriptor is an endpoint descriptor. */ - DTYPE_DeviceQualifier = 0x06, /**< Indicates that the descriptor is a device qualifier descriptor. */ - DTYPE_Other = 0x07, /**< Indicates that the descriptor is of other type. */ - DTYPE_InterfacePower = 0x08, /**< Indicates that the descriptor is an interface power descriptor. */ - DTYPE_InterfaceAssociation = 0x0B, /**< Indicates that the descriptor is an interface association descriptor. */ - DTYPE_CSInterface = 0x24, /**< Indicates that the descriptor is a class specific interface descriptor. */ - DTYPE_CSEndpoint = 0x25, /**< Indicates that the descriptor is a class specific endpoint descriptor. */ - }; - - /** Enum for possible Class, Subclass and Protocol values of device and interface descriptors. */ - enum USB_Descriptor_ClassSubclassProtocol_t - { - USB_CSCP_NoDeviceClass = 0x00, /**< Descriptor Class value indicating that the device does not belong - * to a particular class at the device level. - */ - USB_CSCP_NoDeviceSubclass = 0x00, /**< Descriptor Subclass value indicating that the device does not belong - * to a particular subclass at the device level. - */ - USB_CSCP_NoDeviceProtocol = 0x00, /**< Descriptor Protocol value indicating that the device does not belong - * to a particular protocol at the device level. - */ - USB_CSCP_VendorSpecificClass = 0xFF, /**< Descriptor Class value indicating that the device/interface belongs - * to a vendor specific class. - */ - USB_CSCP_VendorSpecificSubclass = 0xFF, /**< Descriptor Subclass value indicating that the device/interface belongs - * to a vendor specific subclass. - */ - USB_CSCP_VendorSpecificProtocol = 0xFF, /**< Descriptor Protocol value indicating that the device/interface belongs - * to a vendor specific protocol. - */ - USB_CSCP_IADDeviceClass = 0xEF, /**< Descriptor Class value indicating that the device belongs to the - * Interface Association Descriptor class. - */ - USB_CSCP_IADDeviceSubclass = 0x02, /**< Descriptor Subclass value indicating that the device belongs to the - * Interface Association Descriptor subclass. - */ - USB_CSCP_IADDeviceProtocol = 0x01, /**< Descriptor Protocol value indicating that the device belongs to the - * Interface Association Descriptor protocol. - */ - }; - - /* Type Defines: */ - /** \brief Standard USB Descriptor Header (LUFA naming conventions). - * - * Type define for all descriptors' standard header, indicating the descriptor's length and type. This structure - * uses LUFA-specific element names to make each element's purpose clearer. - * - * \see \ref USB_StdDescriptor_Header_t for the version of this type with standard element names. - * - * \note Regardless of CPU architecture, these values should be stored as little endian. - */ - typedef ATTR_IAR_PACKED struct - { - uint8_t Size; /**< Size of the descriptor, in bytes. */ - uint8_t Type; /**< Type of the descriptor, either a value in \ref USB_DescriptorTypes_t or a value - * given by the specific class. - */ - } ATTR_PACKED USB_Descriptor_Header_t; - - /** \brief Standard USB Descriptor Header (USB-IF naming conventions). - * - * Type define for all descriptors' standard header, indicating the descriptor's length and type. This structure - * uses the relevant standard's given element names to ensure compatibility with the standard. - * - * \see \ref USB_Descriptor_Header_t for the version of this type with non-standard LUFA specific element names. - * - * \note Regardless of CPU architecture, these values should be stored as little endian. - */ - typedef ATTR_IAR_PACKED struct - { - uint8_t bLength; /**< Size of the descriptor, in bytes. */ - uint8_t bDescriptorType; /**< Type of the descriptor, either a value in \ref USB_DescriptorTypes_t or a value - * given by the specific class. - */ - } ATTR_PACKED USB_StdDescriptor_Header_t; - - /** \brief Standard USB Device Descriptor (LUFA naming conventions). - * - * Type define for a standard Device Descriptor. This structure uses LUFA-specific element names to make each - * element's purpose clearer. - * - * \see \ref USB_StdDescriptor_Device_t for the version of this type with standard element names. - * - * \note Regardless of CPU architecture, these values should be stored as little endian. - */ - typedef ATTR_IAR_PACKED struct - { - USB_Descriptor_Header_t Header; /**< Descriptor header, including type and size. */ - - uint16_t USBSpecification; /**< BCD of the supported USB specification. - * - * \see \ref VERSION_BCD() utility macro. - */ - uint8_t Class; /**< USB device class. */ - uint8_t SubClass; /**< USB device subclass. */ - uint8_t Protocol; /**< USB device protocol. */ - - uint8_t Endpoint0Size; /**< Size of the control (address 0) endpoint's bank in bytes. */ - - uint16_t VendorID; /**< Vendor ID for the USB product. */ - uint16_t ProductID; /**< Unique product ID for the USB product. */ - uint16_t ReleaseNumber; /**< Product release (version) number. - * - * \see \ref VERSION_BCD() utility macro. - */ - uint8_t ManufacturerStrIndex; /**< String index for the manufacturer's name. The - * host will request this string via a separate - * control request for the string descriptor. - * - * \note If no string supplied, use \ref NO_DESCRIPTOR. - */ - uint8_t ProductStrIndex; /**< String index for the product name/details. - * - * \see ManufacturerStrIndex structure entry. - */ - uint8_t SerialNumStrIndex; /**< String index for the product's globally unique hexadecimal - * serial number, in uppercase Unicode ASCII. - * - * \note On some microcontroller models, there is an embedded serial number - * in the chip which can be used for the device serial number. - * To use this serial number, set this to \c USE_INTERNAL_SERIAL. - * On unsupported devices, this will evaluate to \ref NO_DESCRIPTOR - * and will cause the host to generate a pseudo-unique value for the - * device upon insertion. - * - * \see \c ManufacturerStrIndex structure entry. - */ - uint8_t NumberOfConfigurations; /**< Total number of configurations supported by - * the device. - */ - } ATTR_PACKED USB_Descriptor_Device_t; - - /** \brief Standard USB Device Descriptor (USB-IF naming conventions). - * - * Type define for a standard Device Descriptor. This structure uses the relevant standard's given element names - * to ensure compatibility with the standard. - * - * \see \ref USB_Descriptor_Device_t for the version of this type with non-standard LUFA specific element names. - * - * \note Regardless of CPU architecture, these values should be stored as little endian. - */ - typedef ATTR_IAR_PACKED struct - { - uint8_t bLength; /**< Size of the descriptor, in bytes. */ - uint8_t bDescriptorType; /**< Type of the descriptor, either a value in \ref USB_DescriptorTypes_t or a value - * given by the specific class. - */ - uint16_t bcdUSB; /**< BCD of the supported USB specification. - * - * \see \ref VERSION_BCD() utility macro. - */ - uint8_t bDeviceClass; /**< USB device class. */ - uint8_t bDeviceSubClass; /**< USB device subclass. */ - uint8_t bDeviceProtocol; /**< USB device protocol. */ - uint8_t bMaxPacketSize0; /**< Size of the control (address 0) endpoint's bank in bytes. */ - uint16_t idVendor; /**< Vendor ID for the USB product. */ - uint16_t idProduct; /**< Unique product ID for the USB product. */ - uint16_t bcdDevice; /**< Product release (version) number. - * - * \see \ref VERSION_BCD() utility macro. - */ - uint8_t iManufacturer; /**< String index for the manufacturer's name. The - * host will request this string via a separate - * control request for the string descriptor. - * - * \note If no string supplied, use \ref NO_DESCRIPTOR. - */ - uint8_t iProduct; /**< String index for the product name/details. - * - * \see ManufacturerStrIndex structure entry. - */ - uint8_t iSerialNumber; /**< String index for the product's globally unique hexadecimal - * serial number, in uppercase Unicode ASCII. - * - * \note On some microcontroller models, there is an embedded serial number - * in the chip which can be used for the device serial number. - * To use this serial number, set this to \c USE_INTERNAL_SERIAL. - * On unsupported devices, this will evaluate to \ref NO_DESCRIPTOR - * and will cause the host to generate a pseudo-unique value for the - * device upon insertion. - * - * \see \c ManufacturerStrIndex structure entry. - */ - uint8_t bNumConfigurations; /**< Total number of configurations supported by - * the device. - */ - } ATTR_PACKED USB_StdDescriptor_Device_t; - - /** \brief Standard USB Device Qualifier Descriptor (LUFA naming conventions). - * - * Type define for a standard Device Qualifier Descriptor. This structure uses LUFA-specific element names - * to make each element's purpose clearer. - * - * \see \ref USB_StdDescriptor_DeviceQualifier_t for the version of this type with standard element names. - */ - typedef ATTR_IAR_PACKED struct - { - USB_Descriptor_Header_t Header; /**< Descriptor header, including type and size. */ - - uint16_t USBSpecification; /**< BCD of the supported USB specification. - * - * \see \ref VERSION_BCD() utility macro. - */ - uint8_t Class; /**< USB device class. */ - uint8_t SubClass; /**< USB device subclass. */ - uint8_t Protocol; /**< USB device protocol. */ - - uint8_t Endpoint0Size; /**< Size of the control (address 0) endpoint's bank in bytes. */ - uint8_t NumberOfConfigurations; /**< Total number of configurations supported by - * the device. - */ - uint8_t Reserved; /**< Reserved for future use, must be 0. */ - } ATTR_PACKED USB_Descriptor_DeviceQualifier_t; - - /** \brief Standard USB Device Qualifier Descriptor (USB-IF naming conventions). - * - * Type define for a standard Device Qualifier Descriptor. This structure uses the relevant standard's given element names - * to ensure compatibility with the standard. - * - * \see \ref USB_Descriptor_DeviceQualifier_t for the version of this type with non-standard LUFA specific element names. - */ - typedef ATTR_IAR_PACKED struct - { - uint8_t bLength; /**< Size of the descriptor, in bytes. */ - uint8_t bDescriptorType; /**< Type of the descriptor, either a value in \ref USB_DescriptorTypes_t or a value - * given by the specific class. - */ - uint16_t bcdUSB; /**< BCD of the supported USB specification. - * - * \see \ref VERSION_BCD() utility macro. - */ - uint8_t bDeviceClass; /**< USB device class. */ - uint8_t bDeviceSubClass; /**< USB device subclass. */ - uint8_t bDeviceProtocol; /**< USB device protocol. */ - uint8_t bMaxPacketSize0; /**< Size of the control (address 0) endpoint's bank in bytes. */ - uint8_t bNumConfigurations; /**< Total number of configurations supported by - * the device. - */ - uint8_t bReserved; /**< Reserved for future use, must be 0. */ - } ATTR_PACKED USB_StdDescriptor_DeviceQualifier_t; - - /** \brief Standard USB Configuration Descriptor (LUFA naming conventions). - * - * Type define for a standard Configuration Descriptor header. This structure uses LUFA-specific element names - * to make each element's purpose clearer. - * - * \see \ref USB_StdDescriptor_Configuration_Header_t for the version of this type with standard element names. - * - * \note Regardless of CPU architecture, these values should be stored as little endian. - */ - typedef ATTR_IAR_PACKED struct - { - USB_Descriptor_Header_t Header; /**< Descriptor header, including type and size. */ - - uint16_t TotalConfigurationSize; /**< Size of the configuration descriptor header, - * and all sub descriptors inside the configuration. - */ - uint8_t TotalInterfaces; /**< Total number of interfaces in the configuration. */ - - uint8_t ConfigurationNumber; /**< Configuration index of the current configuration. */ - uint8_t ConfigurationStrIndex; /**< Index of a string descriptor describing the configuration. */ - - uint8_t ConfigAttributes; /**< Configuration attributes, comprised of a mask of \c USB_CONFIG_ATTR_* masks. - * On all devices, this should include USB_CONFIG_ATTR_RESERVED at a minimum. - */ - - uint8_t MaxPowerConsumption; /**< Maximum power consumption of the device while in the - * current configuration, calculated by the \ref USB_CONFIG_POWER_MA() - * macro. - */ - } ATTR_PACKED USB_Descriptor_Configuration_Header_t; - - /** \brief Standard USB Configuration Descriptor (USB-IF naming conventions). - * - * Type define for a standard Configuration Descriptor header. This structure uses the relevant standard's given element names - * to ensure compatibility with the standard. - * - * \see \ref USB_Descriptor_Device_t for the version of this type with non-standard LUFA specific element names. - * - * \note Regardless of CPU architecture, these values should be stored as little endian. - */ - typedef ATTR_IAR_PACKED struct - { - uint8_t bLength; /**< Size of the descriptor, in bytes. */ - uint8_t bDescriptorType; /**< Type of the descriptor, either a value in \ref USB_DescriptorTypes_t or a value - * given by the specific class. - */ - uint16_t wTotalLength; /**< Size of the configuration descriptor header, - * and all sub descriptors inside the configuration. - */ - uint8_t bNumInterfaces; /**< Total number of interfaces in the configuration. */ - uint8_t bConfigurationValue; /**< Configuration index of the current configuration. */ - uint8_t iConfiguration; /**< Index of a string descriptor describing the configuration. */ - uint8_t bmAttributes; /**< Configuration attributes, comprised of a mask of \c USB_CONFIG_ATTR_* masks. - * On all devices, this should include USB_CONFIG_ATTR_RESERVED at a minimum. - */ - uint8_t bMaxPower; /**< Maximum power consumption of the device while in the - * current configuration, calculated by the \ref USB_CONFIG_POWER_MA() - * macro. - */ - } ATTR_PACKED USB_StdDescriptor_Configuration_Header_t; - - /** \brief Standard USB Interface Descriptor (LUFA naming conventions). - * - * Type define for a standard Interface Descriptor. This structure uses LUFA-specific element names - * to make each element's purpose clearer. - * - * \see \ref USB_StdDescriptor_Interface_t for the version of this type with standard element names. - * - * \note Regardless of CPU architecture, these values should be stored as little endian. - */ - typedef ATTR_IAR_PACKED struct - { - USB_Descriptor_Header_t Header; /**< Descriptor header, including type and size. */ - - uint8_t InterfaceNumber; /**< Index of the interface in the current configuration. */ - uint8_t AlternateSetting; /**< Alternate setting for the interface number. The same - * interface number can have multiple alternate settings - * with different endpoint configurations, which can be - * selected by the host. - */ - uint8_t TotalEndpoints; /**< Total number of endpoints in the interface. */ - - uint8_t Class; /**< Interface class ID. */ - uint8_t SubClass; /**< Interface subclass ID. */ - uint8_t Protocol; /**< Interface protocol ID. */ - - uint8_t InterfaceStrIndex; /**< Index of the string descriptor describing the interface. */ - } ATTR_PACKED USB_Descriptor_Interface_t; - - /** \brief Standard USB Interface Descriptor (USB-IF naming conventions). - * - * Type define for a standard Interface Descriptor. This structure uses the relevant standard's given element names - * to ensure compatibility with the standard. - * - * \see \ref USB_Descriptor_Interface_t for the version of this type with non-standard LUFA specific element names. - * - * \note Regardless of CPU architecture, these values should be stored as little endian. - */ - typedef ATTR_IAR_PACKED struct - { - uint8_t bLength; /**< Size of the descriptor, in bytes. */ - uint8_t bDescriptorType; /**< Type of the descriptor, either a value in \ref USB_DescriptorTypes_t or a value - * given by the specific class. - */ - uint8_t bInterfaceNumber; /**< Index of the interface in the current configuration. */ - uint8_t bAlternateSetting; /**< Alternate setting for the interface number. The same - * interface number can have multiple alternate settings - * with different endpoint configurations, which can be - * selected by the host. - */ - uint8_t bNumEndpoints; /**< Total number of endpoints in the interface. */ - uint8_t bInterfaceClass; /**< Interface class ID. */ - uint8_t bInterfaceSubClass; /**< Interface subclass ID. */ - uint8_t bInterfaceProtocol; /**< Interface protocol ID. */ - uint8_t iInterface; /**< Index of the string descriptor describing the - * interface. - */ - } ATTR_PACKED USB_StdDescriptor_Interface_t; - - /** \brief Standard USB Interface Association Descriptor (LUFA naming conventions). - * - * Type define for a standard Interface Association Descriptor. This structure uses LUFA-specific element names - * to make each element's purpose clearer. - * - * This descriptor has been added as a supplement to the USB2.0 standard, in the ECN located at - * http://www.usb.org/developers/docs/InterfaceAssociationDescriptor_ecn.pdf. It allows composite - * devices with multiple interfaces related to the same function to have the multiple interfaces bound - * together at the point of enumeration, loading one generic driver for all the interfaces in the single - * function. Read the ECN for more information. - * - * \see \ref USB_StdDescriptor_Interface_Association_t for the version of this type with standard element names. - * - * \note Regardless of CPU architecture, these values should be stored as little endian. - */ - typedef ATTR_IAR_PACKED struct - { - USB_Descriptor_Header_t Header; /**< Descriptor header, including type and size. */ - - uint8_t FirstInterfaceIndex; /**< Index of the first associated interface. */ - uint8_t TotalInterfaces; /**< Total number of associated interfaces. */ - - uint8_t Class; /**< Interface class ID. */ - uint8_t SubClass; /**< Interface subclass ID. */ - uint8_t Protocol; /**< Interface protocol ID. */ - - uint8_t IADStrIndex; /**< Index of the string descriptor describing the - * interface association. - */ - } ATTR_PACKED USB_Descriptor_Interface_Association_t; - - /** \brief Standard USB Interface Association Descriptor (USB-IF naming conventions). - * - * Type define for a standard Interface Association Descriptor. This structure uses the relevant standard's given - * element names to ensure compatibility with the standard. - * - * This descriptor has been added as a supplement to the USB2.0 standard, in the ECN located at - * http://www.usb.org/developers/docs/InterfaceAssociationDescriptor_ecn.pdf. It allows composite - * devices with multiple interfaces related to the same function to have the multiple interfaces bound - * together at the point of enumeration, loading one generic driver for all the interfaces in the single - * function. Read the ECN for more information. - * - * \see \ref USB_Descriptor_Interface_Association_t for the version of this type with non-standard LUFA specific - * element names. - * - * \note Regardless of CPU architecture, these values should be stored as little endian. - */ - typedef ATTR_IAR_PACKED struct - { - uint8_t bLength; /**< Size of the descriptor, in bytes. */ - uint8_t bDescriptorType; /**< Type of the descriptor, either a value in \ref USB_DescriptorTypes_t or a value - * given by the specific class. - */ - uint8_t bFirstInterface; /**< Index of the first associated interface. */ - uint8_t bInterfaceCount; /**< Total number of associated interfaces. */ - uint8_t bFunctionClass; /**< Interface class ID. */ - uint8_t bFunctionSubClass; /**< Interface subclass ID. */ - uint8_t bFunctionProtocol; /**< Interface protocol ID. */ - uint8_t iFunction; /**< Index of the string descriptor describing the - * interface association. - */ - } ATTR_PACKED USB_StdDescriptor_Interface_Association_t; - - /** \brief Standard USB Endpoint Descriptor (LUFA naming conventions). - * - * Type define for a standard Endpoint Descriptor. This structure uses LUFA-specific element names - * to make each element's purpose clearer. - * - * \see \ref USB_StdDescriptor_Endpoint_t for the version of this type with standard element names. - * - * \note Regardless of CPU architecture, these values should be stored as little endian. - */ - typedef ATTR_IAR_PACKED struct - { - USB_Descriptor_Header_t Header; /**< Descriptor header, including type and size. */ - - uint8_t EndpointAddress; /**< Logical address of the endpoint within the device for the current - * configuration, including direction mask. - */ - uint8_t Attributes; /**< Endpoint attributes, comprised of a mask of the endpoint type (EP_TYPE_*) - * and attributes (ENDPOINT_ATTR_*) masks. - */ - uint16_t EndpointSize; /**< Size of the endpoint bank, in bytes. This indicates the maximum packet - * size that the endpoint can receive at a time. - */ - uint8_t PollingIntervalMS; /**< Polling interval in milliseconds for the endpoint if it is an INTERRUPT - * or ISOCHRONOUS type. - */ - } ATTR_PACKED USB_Descriptor_Endpoint_t; - - /** \brief Standard USB Endpoint Descriptor (USB-IF naming conventions). - * - * Type define for a standard Endpoint Descriptor. This structure uses the relevant standard's given - * element names to ensure compatibility with the standard. - * - * \see \ref USB_Descriptor_Endpoint_t for the version of this type with non-standard LUFA specific - * element names. - * - * \note Regardless of CPU architecture, these values should be stored as little endian. - */ - typedef ATTR_IAR_PACKED struct - { - uint8_t bLength; /**< Size of the descriptor, in bytes. */ - uint8_t bDescriptorType; /**< Type of the descriptor, either a value in \ref USB_DescriptorTypes_t or a - * value given by the specific class. - */ - uint8_t bEndpointAddress; /**< Logical address of the endpoint within the device for the current - * configuration, including direction mask. - */ - uint8_t bmAttributes; /**< Endpoint attributes, comprised of a mask of the endpoint type (EP_TYPE_*) - * and attributes (ENDPOINT_ATTR_*) masks. - */ - uint16_t wMaxPacketSize; /**< Size of the endpoint bank, in bytes. This indicates the maximum packet size - * that the endpoint can receive at a time. - */ - uint8_t bInterval; /**< Polling interval in milliseconds for the endpoint if it is an INTERRUPT or - * ISOCHRONOUS type. - */ - } ATTR_PACKED USB_StdDescriptor_Endpoint_t; - - /** \brief Standard USB String Descriptor (LUFA naming conventions). - * - * Type define for a standard string descriptor. Unlike other standard descriptors, the length - * of the descriptor for placement in the descriptor header must be determined by the \ref USB_STRING_LEN() - * macro rather than by the size of the descriptor structure, as the length is not fixed. - * - * This structure should also be used for string index 0, which contains the supported language IDs for - * the device as an array. - * - * This structure uses LUFA-specific element names to make each element's purpose clearer. - * - * \see \ref USB_StdDescriptor_String_t for the version of this type with standard element names. - * - * \note Regardless of CPU architecture, these values should be stored as little endian. - */ - typedef ATTR_IAR_PACKED struct - { - USB_Descriptor_Header_t Header; /**< Descriptor header, including type and size. */ - - #if defined(__CC_ARM) - #define MAX_ALLOC 256 - #else - #define MAX_ALLOC - #endif - - #if (!defined(__DOXYGEN__)) - wchar_t UnicodeString[MAX_ALLOC]; - #else - uint16_t UnicodeString[MAX_ALLOC]; /**< String data, as unicode characters (alternatively, - * string language IDs). If normal ASCII characters are - * to be used, they must be added as an array of characters - * rather than a normal C string so that they are widened to - * Unicode size. - * - * Under GCC, strings prefixed with the "L" character (before - * the opening string quotation mark) are considered to be - * Unicode strings, and may be used instead of an explicit - * array of ASCII characters on little endian devices with - * UTF-16-LE \c wchar_t encoding. - */ - #endif - } ATTR_PACKED USB_Descriptor_String_t; - - /** \brief Standard USB String Descriptor (USB-IF naming conventions). - * - * Type define for a standard string descriptor. Unlike other standard descriptors, the length - * of the descriptor for placement in the descriptor header must be determined by the \ref USB_STRING_LEN() - * macro rather than by the size of the descriptor structure, as the length is not fixed. - * - * This structure should also be used for string index 0, which contains the supported language IDs for - * the device as an array. - * - * This structure uses the relevant standard's given element names to ensure compatibility with the standard. - * - * \see \ref USB_Descriptor_String_t for the version of this type with with non-standard LUFA specific - * element names. - * - * \note Regardless of CPU architecture, these values should be stored as little endian. - */ - typedef ATTR_IAR_PACKED struct - { - uint8_t bLength; /**< Size of the descriptor, in bytes. */ - uint8_t bDescriptorType; /**< Type of the descriptor, either a value in \ref USB_DescriptorTypes_t - * or a value given by the specific class. - */ - uint16_t bString[]; /**< String data, as unicode characters (alternatively, string language IDs). - * If normal ASCII characters are to be used, they must be added as an array - * of characters rather than a normal C string so that they are widened to - * Unicode size. - * - * Under GCC, strings prefixed with the "L" character (before the opening string - * quotation mark) are considered to be Unicode strings, and may be used instead - * of an explicit array of ASCII characters. - */ - } ATTR_PACKED USB_StdDescriptor_String_t; - - - /* Disable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - } - #endif - -#endif - -/** @} */ - - -#endif /* UC_FAMILY == XMC4 */ diff --git a/cores/usblib/Core/StdRequestType.h b/cores/usblib/Core/StdRequestType.h deleted file mode 100644 index 0523b040..00000000 --- a/cores/usblib/Core/StdRequestType.h +++ /dev/null @@ -1,262 +0,0 @@ -#ifdef XMC4_SERIES - -/* - LUFA Library - Copyright (C) Dean Camera, 2014. - - dean [at] fourwalledcubicle [dot] com - www.lufa-lib.org -*/ - -/* - Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com) - - Permission to use, copy, modify, distribute, and sell this - software and its documentation for any purpose is hereby granted - without fee, provided that the above copyright notice appear in - all copies and that both that the copyright notice and this - permission notice and warranty disclaimer appear in supporting - documentation, and that the name of the author not be used in - advertising or publicity pertaining to distribution of the - software without specific, written prior permission. - - The author disclaims all warranties with regard to this - software, including all implied warranties of merchantability - and fitness. In no event shall the author be liable for any - special, indirect or consequential damages or any damages - whatsoever resulting from loss of use, data or profits, whether - in an action of contract, negligence or other tortious action, - arising out of or in connection with the use or performance of - this software. -*/ - -/** \file - * \brief USB control endpoint request definitions. - * \copydetails Group_StdRequest - * - * \note This file should not be included directly. It is automatically included as needed by the USB driver - * dispatch header located in LUFA/Drivers/USB/USB.h. - */ - -/** \ingroup Group_USB - * \defgroup Group_StdRequest Standard USB Requests - * \brief USB control endpoint request definitions. - * - * This module contains definitions for the various control request parameters, so that the request - * details (such as data direction, request recipient, etc.) can be extracted via masking. - * - * @{ - */ - -#ifndef __STDREQTYPE_H__ -#define __STDREQTYPE_H__ - - /* Includes: */ - #include <../Common/Common.h> - #include - - /* Enable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - extern "C" { - #endif - - /* Preprocessor Checks: */ - #if !defined(__INCLUDE_FROM_USB_DRIVER) - #error Do not include this file directly. Include LUFA/Drivers/USB/USB.h instead. - #endif - - /* Public Interface - May be used in end-application: */ - /* Macros: */ - /** Mask for the request type parameter, to indicate the direction of the request data (Host to Device - * or Device to Host). The result of this mask should then be compared to the request direction masks. - * - * \see \c REQDIR_* macros for masks indicating the request data direction. - */ - #define CONTROL_REQTYPE_DIRECTION 0x80 - - /** Mask for the request type parameter, to indicate the type of request (Device, Class or Vendor - * Specific). The result of this mask should then be compared to the request type masks. - * - * \see \c REQTYPE_* macros for masks indicating the request type. - */ - #define CONTROL_REQTYPE_TYPE 0x60 - - /** Mask for the request type parameter, to indicate the recipient of the request (Device, Interface - * Endpoint or Other). The result of this mask should then be compared to the request recipient - * masks. - * - * \see \c REQREC_* macros for masks indicating the request recipient. - */ - #define CONTROL_REQTYPE_RECIPIENT 0x1F - - /** \name Control Request Data Direction Masks */ - //@{ - /** Request data direction mask, indicating that the request data will flow from host to device. - * - * \see \ref CONTROL_REQTYPE_DIRECTION macro. - */ - #define REQDIR_HOSTTODEVICE (0 << 7) - - /** Request data direction mask, indicating that the request data will flow from device to host. - * - * \see \ref CONTROL_REQTYPE_DIRECTION macro. - */ - #define REQDIR_DEVICETOHOST (1 << 7) - //@} - - /** \name Control Request Type Masks */ - //@{ - /** Request type mask, indicating that the request is a standard request. - * - * \see \ref CONTROL_REQTYPE_TYPE macro. - */ - #define REQTYPE_STANDARD (0 << 5) - - /** Request type mask, indicating that the request is a class-specific request. - * - * \see \ref CONTROL_REQTYPE_TYPE macro. - */ - #define REQTYPE_CLASS (1 << 5) - - /** Request type mask, indicating that the request is a vendor specific request. - * - * \see \ref CONTROL_REQTYPE_TYPE macro. - */ - #define REQTYPE_VENDOR (2 << 5) - //@} - - /** \name Control Request Recipient Masks */ - //@{ - /** Request recipient mask, indicating that the request is to be issued to the device as a whole. - * - * \see \ref CONTROL_REQTYPE_RECIPIENT macro. - */ - #define REQREC_DEVICE (0 << 0) - - /** Request recipient mask, indicating that the request is to be issued to an interface in the - * currently selected configuration. - * - * \see \ref CONTROL_REQTYPE_RECIPIENT macro. - */ - #define REQREC_INTERFACE (1 << 0) - - /** Request recipient mask, indicating that the request is to be issued to an endpoint in the - * currently selected configuration. - * - * \see \ref CONTROL_REQTYPE_RECIPIENT macro. - */ - #define REQREC_ENDPOINT (2 << 0) - - /** Request recipient mask, indicating that the request is to be issued to an unspecified element - * in the currently selected configuration. - * - * \see \ref CONTROL_REQTYPE_RECIPIENT macro. - */ - #define REQREC_OTHER (3 << 0) - //@} - - /* Type Defines: */ - /** \brief Standard USB Control Request - * - * Type define for a standard USB control request. - * - * \see The USB 2.0 specification for more information on standard control requests. - */ - typedef ATTR_IAR_PACKED struct - { - uint8_t bmRequestType; /**< Type of the request. */ - uint8_t bRequest; /**< Request command code. */ - uint16_t wValue; /**< wValue parameter of the request. */ - uint16_t wIndex; /**< wIndex parameter of the request. */ - uint16_t wLength; /**< Length of the data to transfer in bytes. */ - } ATTR_PACKED USB_Request_Header_t; - - /* Enums: */ - /** Enumeration for the various standard request commands. These commands are applicable when the - * request type is \ref REQTYPE_STANDARD (with the exception of \ref REQ_GetDescriptor, which is always - * handled regardless of the request type value). - * - * \see Chapter 9 of the USB 2.0 Specification. - */ - enum USB_Control_Request_t - { - REQ_GetStatus = 0, /**< Implemented in the library for device and endpoint recipients. Passed - * to the user application for other recipients via the - * \ref EVENT_USB_Device_ControlRequest() event when received in - * device mode. */ - REQ_ClearFeature = 1, /**< Implemented in the library for device and endpoint recipients. Passed - * to the user application for other recipients via the - * \ref EVENT_USB_Device_ControlRequest() event when received in - * device mode. */ - REQ_SetFeature = 3, /**< Implemented in the library for device and endpoint recipients. Passed - * to the user application for other recipients via the - * \ref EVENT_USB_Device_ControlRequest() event when received in - * device mode. */ - REQ_SetAddress = 5, /**< Implemented in the library for the device recipient. Passed - * to the user application for other recipients via the - * \ref EVENT_USB_Device_ControlRequest() event when received in - * device mode. */ - REQ_GetDescriptor = 6, /**< Implemented in the library for device and interface recipients. Passed to the - * user application for other recipients via the - * \ref EVENT_USB_Device_ControlRequest() event when received in - * device mode. */ - REQ_SetDescriptor = 7, /**< Not implemented in the library, passed to the user application - * via the \ref EVENT_USB_Device_ControlRequest() event when received in - * device mode. */ - REQ_GetConfiguration = 8, /**< Implemented in the library for the device recipient. Passed - * to the user application for other recipients via the - * \ref EVENT_USB_Device_ControlRequest() event when received in - * device mode. */ - REQ_SetConfiguration = 9, /**< Implemented in the library for the device recipient. Passed - * to the user application for other recipients via the - * \ref EVENT_USB_Device_ControlRequest() event when received in - * device mode. */ - REQ_GetInterface = 10, /**< Not implemented in the library, passed to the user application - * via the \ref EVENT_USB_Device_ControlRequest() event when received in - * device mode. */ - REQ_SetInterface = 11, /**< Not implemented in the library, passed to the user application - * via the \ref EVENT_USB_Device_ControlRequest() event when received in - * device mode. */ - REQ_SynchFrame = 12, /**< Not implemented in the library, passed to the user application - * via the \ref EVENT_USB_Device_ControlRequest() event when received in - * device mode. */ - }; - - /** Feature Selector values for Set Feature and Clear Feature standard control requests directed to the device, interface - * and endpoint recipients. - */ - enum USB_Feature_Selectors_t - { - FEATURE_SEL_EndpointHalt = 0x00, /**< Feature selector for Clear Feature or Set Feature commands. When - * used in a Set Feature or Clear Feature request this indicates that an - * endpoint (whose address is given elsewhere in the request) should have - * its stall condition changed. - */ - FEATURE_SEL_DeviceRemoteWakeup = 0x01, /**< Feature selector for Device level Remote Wakeup enable set or clear. - * This feature can be controlled by the host on devices which indicate - * remote wakeup support in their descriptors to selectively disable or - * enable remote wakeup. - */ - FEATURE_SEL_TestMode = 0x02, /**< Feature selector for Test Mode features, used to test the USB controller - * to check for incorrect operation. - */ - }; - - /* Private Interface - For use in library only: */ - #if !defined(__DOXYGEN__) - /* Macros: */ - #define FEATURE_SELFPOWERED_ENABLED (1 << 0) - #define FEATURE_REMOTE_WAKEUP_ENABLED (1 << 1) - #endif - - /* Disable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - } - #endif - -#endif - -/** @} */ - - -#endif /* UC_FAMILY == XMC4 */ diff --git a/cores/usblib/Core/USBController.h b/cores/usblib/Core/USBController.h deleted file mode 100644 index 78370f84..00000000 --- a/cores/usblib/Core/USBController.h +++ /dev/null @@ -1,163 +0,0 @@ -#ifdef XMC4_SERIES - -/* - LUFA Library - Copyright (C) Dean Camera, 2014. - - dean [at] fourwalledcubicle [dot] com - www.lufa-lib.org -*/ - -/* - Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com) - - Permission to use, copy, modify, distribute, and sell this - software and its documentation for any purpose is hereby granted - without fee, provided that the above copyright notice appear in - all copies and that both that the copyright notice and this - permission notice and warranty disclaimer appear in supporting - documentation, and that the name of the author not be used in - advertising or publicity pertaining to distribution of the - software without specific, written prior permission. - - The author disclaims all warranties with regard to this - software, including all implied warranties of merchantability - and fitness. In no event shall the author be liable for any - special, indirect or consequential damages or any damages - whatsoever resulting from loss of use, data or profits, whether - in an action of contract, negligence or other tortious action, - arising out of or in connection with the use or performance of - this software. -*/ - -/** \file - * \brief Common USB Controller definitions for all architectures. - * \copydetails Group_USBManagement - * - * \note This file should not be included directly. It is automatically included as needed by the USB driver - * dispatch header located in LUFA/Drivers/USB/USB.h. - */ - -/** \ingroup Group_USB - * \defgroup Group_USBManagement USB Interface Management - * \brief USB Controller definitions for general USB controller management. - * - * Functions, macros, variables, enums and types related to the setup and management of the USB interface. - * - * @{ - */ - -#ifndef __USBCONTROLLER_H__ -#define __USBCONTROLLER_H__ - - /* Includes: */ - #include <../Common/Common.h> - #include - - /* Enable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - extern "C" { - #endif - - /* Preprocessor Checks and Defines: */ - #if !defined(__INCLUDE_FROM_USB_DRIVER) - #error Do not include this file directly. Include LUFA/Drivers/USB/USB.h instead. - #endif - - /* Defines: */ - /** \name Endpoint Direction Masks */ - //@{ - /** Endpoint direction mask, for masking against endpoint addresses to retrieve the endpoint's - * direction for comparing with the \c ENDPOINT_DIR_* masks. - */ - #define ENDPOINT_DIR_MASK 0x80 - - /** Endpoint address direction mask for an OUT direction (Host to Device) endpoint. This may be ORed with - * the index of the address within a device to obtain the full endpoint address. - */ - #define ENDPOINT_DIR_OUT 0x00 - - /** Endpoint address direction mask for an IN direction (Device to Host) endpoint. This may be ORed with - * the index of the address within a device to obtain the full endpoint address. - */ - #define ENDPOINT_DIR_IN 0x80 - //@} - - /** \name Pipe Direction Masks */ - //@{ - /** Pipe direction mask, for masking against pipe addresses to retrieve the pipe's - * direction for comparing with the \c PIPE_DIR_* masks. - */ - #define PIPE_DIR_MASK 0x80 - - /** Endpoint address direction mask for an OUT direction (Host to Device) endpoint. This may be ORed with - * the index of the address within a device to obtain the full endpoint address. - */ - #define PIPE_DIR_OUT 0x00 - - /** Endpoint address direction mask for an IN direction (Device to Host) endpoint. This may be ORed with - * the index of the address within a device to obtain the full endpoint address. - */ - #define PIPE_DIR_IN 0x80 - //@} - - /** \name Endpoint/Pipe Type Masks */ - //@{ - /** Mask for determining the type of an endpoint from an endpoint descriptor. This should then be compared - * with the \c EP_TYPE_* masks to determine the exact type of the endpoint. - */ - #define EP_TYPE_MASK 0x03 - - /** Mask for a CONTROL type endpoint or pipe. - * - * \note See \ref Group_EndpointManagement and \ref Group_PipeManagement for endpoint/pipe functions. - */ - #define EP_TYPE_CONTROL 0x00 - - /** Mask for an ISOCHRONOUS type endpoint or pipe. - * - * \note See \ref Group_EndpointManagement and \ref Group_PipeManagement for endpoint/pipe functions. - */ - #define EP_TYPE_ISOCHRONOUS 0x01 - - /** Mask for a BULK type endpoint or pipe. - * - * \note See \ref Group_EndpointManagement and \ref Group_PipeManagement for endpoint/pipe functions. - */ - #define EP_TYPE_BULK 0x02 - - /** Mask for an INTERRUPT type endpoint or pipe. - * - * \note See \ref Group_EndpointManagement and \ref Group_PipeManagement for endpoint/pipe functions. - */ - #define EP_TYPE_INTERRUPT 0x03 - //@} - - /* Enums: */ - /** Enum for the possible USB controller modes, for initialization via \ref USB_Init() and indication back to the - * user application via \ref USB_CurrentMode. - */ - enum USB_Modes_t - { - USB_MODE_None = 0, /**< Indicates that the controller is currently not initialized in any specific USB mode. */ - USB_MODE_Device = 1, /**< Indicates that the controller is currently initialized in USB Device mode. */ - USB_MODE_Host = 2, /**< Indicates that the controller is currently initialized in USB Host mode. */ - USB_MODE_UID = 3, /**< Indicates that the controller should determine the USB mode from the UID pin of the - * USB connector. - */ - }; - - /* Architecture Includes: */ - #include - - /* Disable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - } - #endif - -#endif - -/** @} */ - - -#endif /* UC_FAMILY == XMC4 */ diff --git a/cores/usblib/Core/USBInterrupt.h b/cores/usblib/Core/USBInterrupt.h deleted file mode 100644 index ab9fa933..00000000 --- a/cores/usblib/Core/USBInterrupt.h +++ /dev/null @@ -1,70 +0,0 @@ -#ifdef XMC4_SERIES - -/* - LUFA Library - Copyright (C) Dean Camera, 2014. - - dean [at] fourwalledcubicle [dot] com - www.lufa-lib.org -*/ - -/* - Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com) - - Permission to use, copy, modify, distribute, and sell this - software and its documentation for any purpose is hereby granted - without fee, provided that the above copyright notice appear in - all copies and that both that the copyright notice and this - permission notice and warranty disclaimer appear in supporting - documentation, and that the name of the author not be used in - advertising or publicity pertaining to distribution of the - software without specific, written prior permission. - - The author disclaims all warranties with regard to this - software, including all implied warranties of merchantability - and fitness. In no event shall the author be liable for any - special, indirect or consequential damages or any damages - whatsoever resulting from loss of use, data or profits, whether - in an action of contract, negligence or other tortious action, - arising out of or in connection with the use or performance of - this software. -*/ - -/** \file - * \brief USB controller interrupt service routine management. - * - * This file contains definitions required for the correct handling of low level USB service routine interrupts - * from the USB controller. - * - * \note This file should not be included directly. It is automatically included as needed by the USB driver - * dispatch header located in LUFA/Drivers/USB/USB.h. - */ - -#ifndef __USBINTERRUPT_H__ -#define __USBINTERRUPT_H__ - - /* Includes: */ - #include <../Common/Common.h> - #include - - /* Enable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - extern "C" { - #endif - - /* Preprocessor Checks: */ - #if !defined(__INCLUDE_FROM_USB_DRIVER) - #error Do not include this file directly. Include USB/USB.h instead. - #endif - - /* Architecture Includes: */ - - /* Disable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - } - #endif - -#endif - - -#endif /* UC_FAMILY == XMC4 */ diff --git a/cores/usblib/Core/USBMode.h b/cores/usblib/Core/USBMode.h deleted file mode 100644 index f3e2e947..00000000 --- a/cores/usblib/Core/USBMode.h +++ /dev/null @@ -1,125 +0,0 @@ -#ifdef XMC4_SERIES - -/* - LUFA Library - Copyright (C) Dean Camera, 2014. - - dean [at] fourwalledcubicle [dot] com - www.lufa-lib.org -*/ - -/* - Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com) - - Permission to use, copy, modify, distribute, and sell this - software and its documentation for any purpose is hereby granted - without fee, provided that the above copyright notice appear in - all copies and that both that the copyright notice and this - permission notice and warranty disclaimer appear in supporting - documentation, and that the name of the author not be used in - advertising or publicity pertaining to distribution of the - software without specific, written prior permission. - - The author disclaims all warranties with regard to this - software, including all implied warranties of merchantability - and fitness. In no event shall the author be liable for any - special, indirect or consequential damages or any damages - whatsoever resulting from loss of use, data or profits, whether - in an action of contract, negligence or other tortious action, - arising out of or in connection with the use or performance of - this software. -*/ - -/** \file - * \brief USB mode and feature support definitions. - * \copydetails Group_USBMode - * - * \note This file should not be included directly. It is automatically included as needed by the USB driver - * dispatch header located in LUFA/Drivers/USB/USB.h. - */ - -/** \ingroup Group_USB - * \defgroup Group_USBMode USB Mode Tokens - * \brief USB mode and feature support definitions. - * - * This file defines macros indicating the type of USB controller the library is being compiled for, and its - * capabilities. These macros may then be referenced in the user application to selectively enable or disable - * code sections depending on if they are defined or not. - * - * After the inclusion of the master USB driver header, one or more of the following tokens may be defined, to - * allow the user code to conditionally enable or disable code based on the USB controller family and allowable - * USB modes. These tokens may be tested against to eliminate code relating to a USB mode which is not enabled for - * the given compilation. - * - * @{ - */ - -#ifndef __USBMODE_H__ -#define __USBMODE_H__ - - /* Enable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - extern "C" { - #endif - - /* Preprocessor Checks: */ - #if !defined(__INCLUDE_FROM_USB_DRIVER) - #error Do not include this file directly. Include LUFA/Drivers/USB/USB.h instead. - #endif - - /* Includes: */ - #include <../Common/Common.h> - - /* Public Interface - May be used in end-application: */ - #if defined(__DOXYGEN__) - /** Indicates that the target microcontroller and compilation settings allow for the - * target to be configured in USB Device mode when defined. - */ - #define USB_CAN_BE_DEVICE - - /** Indicates that the target microcontroller and compilation settings allow for the - * target to be configured in USB Host mode when defined. - */ - #define USB_CAN_BE_HOST - - #else - /* Macros: */ - #define USB_CAN_BE_DEVICE - //#define USB_CAN_BE_HOST - - #if (defined(USB_HOST_ONLY) && defined(USB_DEVICE_ONLY)) - #error USB_HOST_ONLY and USB_DEVICE_ONLY are mutually exclusive. - #elif defined(USB_HOST_ONLY) - #if !defined(USB_CAN_BE_HOST) - #error USB_HOST_ONLY is not available for the currently selected microcontroller model. - #else - #undef USB_CAN_BE_DEVICE - #endif - #elif defined(USB_DEVICE_ONLY) - #if !defined(USB_CAN_BE_DEVICE) - #error USB_DEVICE_ONLY is not available for the currently selected microcontroller model. - #else - #undef USB_CAN_BE_HOST - #endif - #endif - - #if (defined(USB_CAN_BE_DEVICE) && defined(USB_CAN_BE_HOST)) - #define USB_CAN_BE_BOTH - #endif - - #if (!defined(USB_CAN_BE_DEVICE) && !defined(USB_CAN_BE_HOST)) - #error The currently selected device, USB mode or architecture is not supported. - #endif - #endif - - /* Disable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - } - #endif - -#endif - -/** @} */ - - -#endif /* UC_FAMILY == XMC4 */ diff --git a/cores/usblib/Core/USBTask.c b/cores/usblib/Core/USBTask.c deleted file mode 100644 index 267ae56b..00000000 --- a/cores/usblib/Core/USBTask.c +++ /dev/null @@ -1,93 +0,0 @@ -#ifdef XMC4_SERIES - -/* - LUFA Library - Copyright (C) Dean Camera, 2014. - - dean [at] fourwalledcubicle [dot] com - www.lufa-lib.org -*/ - -/* - Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com) - - Permission to use, copy, modify, distribute, and sell this - software and its documentation for any purpose is hereby granted - without fee, provided that the above copyright notice appear in - all copies and that both that the copyright notice and this - permission notice and warranty disclaimer appear in supporting - documentation, and that the name of the author not be used in - advertising or publicity pertaining to distribution of the - software without specific, written prior permission. - - The author disclaims all warranties with regard to this - software, including all implied warranties of merchantability - and fitness. In no event shall the author be liable for any - special, indirect or consequential damages or any damages - whatsoever resulting from loss of use, data or profits, whether - in an action of contract, negligence or other tortious action, - arising out of or in connection with the use or performance of - this software. -*/ -#if defined(USB0) -#define __INCLUDE_FROM_USBTASK_C -#define __INCLUDE_FROM_USB_DRIVER -#include - -volatile bool USB_IsInitialized; -USB_Request_Header_t USB_ControlRequest; - -#if defined(USB_CAN_BE_HOST) && !defined(HOST_STATE_AS_GPIOR) -volatile uint8_t USB_HostState; -#endif - -#if defined(USB_CAN_BE_DEVICE) && !defined(DEVICE_STATE_AS_GPIOR) -volatile uint8_t USB_DeviceState; -#endif - -void USB_USBTask(void) -{ - #if defined(USB_CAN_BE_BOTH) - if (USB_CurrentMode == USB_MODE_Device) - USB_DeviceTask(); - else if (USB_CurrentMode == USB_MODE_Host) - USB_HostTask(); - #elif defined(USB_CAN_BE_HOST) - USB_HostTask(); - #elif defined(USB_CAN_BE_DEVICE) - USB_DeviceTask(); - #endif -} - -#if defined(USB_CAN_BE_DEVICE) -static void USB_DeviceTask(void) -{ - if (USB_DeviceState == DEVICE_STATE_Unattached) - return; - - uint8_t PrevEndpoint = Endpoint_GetCurrentEndpoint(); - - Endpoint_SelectEndpoint(ENDPOINT_CONTROLEP); - - if (Endpoint_IsSETUPReceived()) - USB_Device_ProcessControlRequest(); - - Endpoint_SelectEndpoint(PrevEndpoint); -} -#endif - -#if defined(USB_CAN_BE_HOST) -static void USB_HostTask(void) -{ - uint8_t PrevPipe = Pipe_GetCurrentPipe(); - - Pipe_SelectPipe(PIPE_CONTROLPIPE); - - USB_Host_ProcessNextHostState(); - - Pipe_SelectPipe(PrevPipe); -} -#endif - -#endif -#endif /* UC_FAMILY == XMC4 */ diff --git a/cores/usblib/Core/USBTask.h b/cores/usblib/Core/USBTask.h deleted file mode 100644 index 90cc154d..00000000 --- a/cores/usblib/Core/USBTask.h +++ /dev/null @@ -1,194 +0,0 @@ -#ifdef XMC4_SERIES - -/* - LUFA Library - Copyright (C) Dean Camera, 2014. - - dean [at] fourwalledcubicle [dot] com - www.lufa-lib.org -*/ - -/* - Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com) - - Permission to use, copy, modify, distribute, and sell this - software and its documentation for any purpose is hereby granted - without fee, provided that the above copyright notice appear in - all copies and that both that the copyright notice and this - permission notice and warranty disclaimer appear in supporting - documentation, and that the name of the author not be used in - advertising or publicity pertaining to distribution of the - software without specific, written prior permission. - - The author disclaims all warranties with regard to this - software, including all implied warranties of merchantability - and fitness. In no event shall the author be liable for any - special, indirect or consequential damages or any damages - whatsoever resulting from loss of use, data or profits, whether - in an action of contract, negligence or other tortious action, - arising out of or in connection with the use or performance of - this software. -*/ - -/** \file - * \brief Main USB service task management. - * - * This file contains the function definitions required for the main USB service task, which must be called - * from the user application to ensure that the USB connection to or from a connected USB device is maintained. - * - * \note This file should not be included directly. It is automatically included as needed by the USB driver - * dispatch header located in LUFA/Drivers/USB/USB.h. - */ - -#ifndef __USBTASK_H__ -#define __USBTASK_H__ -#if defined(USB0) - /* Includes: */ - #include <../Common/Common.h> - #include - #include - #include - #include - #include - - #if defined(USB_CAN_BE_DEVICE) - #include - #endif - - #if defined(USB_CAN_BE_HOST) - #include - #endif - - /* Enable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - extern "C" { - #endif - - /* Preprocessor Checks: */ - #if !defined(__INCLUDE_FROM_USB_DRIVER) - #error Do not include this file directly. Include LUFA/Drivers/USB/USB.h instead. - #endif - - /* Public Interface - May be used in end-application: */ - /* Global Variables: */ - /** Indicates if the USB interface is currently initialized but not necessarily connected to a host - * or device (i.e. if \ref USB_Init() has been run). If this is false, all other library globals related - * to the USB driver are invalid. - * - * \attention This variable should be treated as read-only in the user application, and never manually - * changed in value. - * - * \ingroup Group_USBManagement - */ - extern volatile bool USB_IsInitialized; - - /** Structure containing the last received Control request when in Device mode (for use in user-applications - * inside of the \ref EVENT_USB_Device_ControlRequest() event, or for filling up with a control request to - * issue when in Host mode before calling \ref USB_Host_SendControlRequest(). - * - * \note The contents of this structure is automatically endian-corrected for the current CPU architecture. - * - * \ingroup Group_USBManagement - */ - extern USB_Request_Header_t USB_ControlRequest; - - #if defined(USB_CAN_BE_HOST) || defined(__DOXYGEN__) - #if !defined(HOST_STATE_AS_GPIOR) || defined(__DOXYGEN__) - /** Indicates the current host state machine state. When in host mode, this indicates the state - * via one of the values of the \ref USB_Host_States_t enum values. - * - * This value should not be altered by the user application as it is handled automatically by the - * library. - * - * - * \note This global is only present if the user application can be a USB host. - * - * \see \ref USB_Host_States_t for a list of possible device states. - * - * \ingroup Group_Host - */ - extern volatile uint8_t USB_HostState; - #else - #define USB_HostState CONCAT_EXPANDED(GPIOR, HOST_STATE_AS_GPIOR) - #endif - #endif - - #if defined(USB_CAN_BE_DEVICE) || defined(__DOXYGEN__) - #if !defined(DEVICE_STATE_AS_GPIOR) || defined(__DOXYGEN__) - /** Indicates the current device state machine state. When in device mode, this indicates the state - * via one of the values of the \ref USB_Device_States_t enum values. - * - * This value should not be altered by the user application as it is handled automatically by the - * library. The only exception to this rule is if the NO_LIMITED_CONTROLLER_CONNECT token is used - * (see \ref EVENT_USB_Device_Connect() and \ref EVENT_USB_Device_Disconnect() events). - * - * - * \attention This variable should be treated as read-only in the user application, and never manually - * changed in value except in the circumstances outlined above. - * - * \note This global is only present if the user application can be a USB device. - * \n\n - * - * \see \ref USB_Device_States_t for a list of possible device states. - * - * \ingroup Group_Device - */ - extern volatile uint8_t USB_DeviceState; - #else - #define USB_DeviceState CONCAT_EXPANDED(GPIOR, DEVICE_STATE_AS_GPIOR) - #endif - #endif - - /* Function Prototypes: */ - /** This is the main USB management task. The USB driver requires this task to be executed - * continuously when the USB system is active (device attached in host mode, or attached to a host - * in device mode) in order to manage USB communications. This task may be executed inside an RTOS, - * fast timer ISR or the main user application loop. - * - * The USB task must be serviced within 30ms while in device mode, or within 1ms while in host mode. - * The task may be serviced at all times, or (for minimum CPU consumption): - * - * - In device mode, it may be disabled at start-up, enabled on the firing of the \ref EVENT_USB_Device_Connect() - * event and disabled again on the firing of the \ref EVENT_USB_Device_Disconnect() event. - * - * - In host mode, it may be disabled at start-up, enabled on the firing of the \ref EVENT_USB_Host_DeviceAttached() - * event and disabled again on the firing of the \ref EVENT_USB_Host_DeviceEnumerationComplete() or - * \ref EVENT_USB_Host_DeviceEnumerationFailed() events. - * - * If in device mode (only), the control endpoint can instead be managed via interrupts entirely by the library - * by defining the INTERRUPT_CONTROL_ENDPOINT token and passing it to the compiler via the -D switch. - * - * \see \ref Group_Events for more information on the USB events. - * - * \ingroup Group_USBManagement - */ - void USB_USBTask(void); - - /* Private Interface - For use in library only: */ - #if !defined(__DOXYGEN__) - /* Function Prototypes: */ - #if defined(__INCLUDE_FROM_USBTASK_C) - #if defined(USB_CAN_BE_HOST) - static void USB_HostTask(void); - #endif - - #if defined(USB_CAN_BE_DEVICE) - static void USB_DeviceTask(void); - #endif - #endif - - /* Macros: */ - #define HOST_TASK_NONBLOCK_WAIT(Duration, NextState) do { USB_HostState = HOST_STATE_WaitForDevice; \ - WaitMSRemaining = (Duration); \ - PostWaitState = (NextState); } while (0) - #endif - - /* Disable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - } - #endif -#endif -#endif - - -#endif /* UC_FAMILY == XMC4 */ diff --git a/cores/usblib/Core/XMC4000/Device_XMC4000.h b/cores/usblib/Core/XMC4000/Device_XMC4000.h deleted file mode 100644 index 9e8c6e41..00000000 --- a/cores/usblib/Core/XMC4000/Device_XMC4000.h +++ /dev/null @@ -1,135 +0,0 @@ -#ifdef XMC4_SERIES - -/* - LUFA Library - Copyright (C) Dean Camera, 2014. - - dean [at] fourwalledcubicle [dot] com - www.lufa-lib.org -*/ - -/* - Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com) - - Permission to use, copy, modify, distribute, and sell this - software and its documentation for any purpose is hereby granted - without fee, provided that the above copyright notice appear in - all copies and that both that the copyright notice and this - permission notice and warranty disclaimer appear in supporting - documentation, and that the name of the author not be used in - advertising or publicity pertaining to distribution of the - software without specific, written prior permission. - - The author disclaims all warranties with regard to this - software, including all implied warranties of merchantability - and fitness. In no event shall the author be liable for any - special, indirect or consequential damages or any damages - whatsoever resulting from loss of use, data or profits, whether - in an action of contract, negligence or other tortious action, - arising out of or in connection with the use or performance of - this software. -*/ - -/* - * Copyright (C) 2015 Infineon Technologies AG. All rights Reserved bits. - * - * Infineon Technologies AG (Infineon) is supplying this software for use with - * Infineon's microcontrollers. - * This file can be freely distributed within development tools that are - * supporting such microcontrollers. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, - * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - */ - -/** \file - * \brief USB Device definitions for the Infineon XMC4000 microcontrollers. - * \copydetails Group_Device_XMC - * - * \note This file should not be included directly. It is automatically included as needed by the USB driver - * dispatch header located in LUFA/Drivers/USB/USB.h. - */ - -/** \ingroup Group_Device - * \defgroup Group_Device_XMC Device Management (XMC) - * \brief USB Device definitions for the Infineon XMC4000 microcontrollers. - * - * Architecture specific USB Device definitions for the Infineon XMC4000 microcontrollers. - * - * @{ - */ - -#ifndef __USBDEVICE_XMC4000_H__ -#define __USBDEVICE_XMC4000_H__ -#if defined(USB0) - /* Includes: */ - #include <../../Common/Common.h> - #include <../USBController.h> - #include <../StdDescriptors.h> - #include <../USBInterrupt.h> - #include <../EndPoint.h> - - /* Enable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - extern "C" { - #endif - - /* Preprocessor Checks: */ - #if !defined(__INCLUDE_FROM_USB_DRIVER) - #error Do not include this file directly. USB/USB.h instead. - #endif - - /* Public Interface - May be used in end-application: */ - /* Macros: */ - - #define USE_INTERNAL_SERIAL NO_DESCRIPTOR - - #define INTERNAL_SERIAL_LENGTH_BITS 0 - #define INTERNAL_SERIAL_START_ADDRESS 0 - - /* Inline Functions: */ - static inline void USB_Device_SetDeviceAddress(const uint8_t Address) ATTR_ALWAYS_INLINE; - static inline void USB_Device_SetDeviceAddress(const uint8_t Address) - { - (void)Address; - } - - static inline void USB_Device_EnableDeviceAddress(const uint8_t Address) ATTR_ALWAYS_INLINE; - static inline void USB_Device_EnableDeviceAddress(const uint8_t Address) - { - device.Driver->DeviceSetAddress(Address, XMC_USBD_SET_ADDRESS_STAGE_SETUP); - } - - static inline bool USB_Device_IsAddressSet(void) ATTR_ALWAYS_INLINE ATTR_WARN_UNUSED_RESULT; - static inline bool USB_Device_IsAddressSet(void) - { - dcfg_data_t data; - data.d32 = xmc_device.device_register->dcfg; - return ((data.b.devaddr != 0) ? true : false); - } - - /** Returns the current USB frame number, when in device mode. Every millisecond the USB bus is active (i.e. enumerated to a host) - * the frame number is incremented by one. - * - * \return Current USB frame number from the USB controller. - */ - - static inline uint16_t USB_Device_GetFrameNumber(void) ATTR_ALWAYS_INLINE; - static inline uint16_t USB_Device_GetFrameNumber(void) { - return device.Driver->GetFrameNumber(); - } - - /* Disable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - } - #endif - -#endif /* __USBDEVICE_XMC4000_H__ */ -#endif -/** @} */ - - -#endif /* UC_FAMILY == XMC4 */ diff --git a/cores/usblib/Core/XMC4000/EndpointStream_XMC4000.c b/cores/usblib/Core/XMC4000/EndpointStream_XMC4000.c deleted file mode 100644 index 71bf2b7a..00000000 --- a/cores/usblib/Core/XMC4000/EndpointStream_XMC4000.c +++ /dev/null @@ -1,310 +0,0 @@ -#ifdef XMC4_SERIES - -/******************************************************************************* - Copyright (c) 2013, Infineon Technologies AG ** - All rights reserved. ** - ** - Redistribution and use in source and binary forms, with or without ** - modification,are permitted provided that the following conditions are met: ** - ** - *Redistributions of source code must retain the above copyright notice, ** - this list of conditions and the following disclaimer. ** - *Redistributions in binary form must reproduce the above copyright notice, ** - this list of conditions and the following disclaimer in the documentation ** - and/or other materials provided with the distribution. ** - *Neither the name of the copyright holders nor the names of its contributors ** - may be used to endorse or promote products derived from this software without** - specific prior written permission. ** - ** - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ** - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ** - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ** - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE ** - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ** - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ** - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ** - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ** - CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ** - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ** - POSSIBILITY OF SUCH DAMAGE. ** - ** - To improve the quality of the software, users are encouraged to share ** - modifications, enhancements or bug fixes with Infineon Technologies AG ** - dave@infineon.com). ** - ** -********************************************************************************/ -/** - * @file - * - * @App Version internal release for evaluation, no public release! - * - * @brief Source file for LUFA Endpoint Streaming functions - */ -#if defined(USB0) -#include <../../Common/Common.h> - -#define __INCLUDE_FROM_USB_DRIVER -#include <../USBMode.h> - -/*Flag to indicate the zlp to be sent or not*/ -volatile uint8_t zlp_flag = 0; - -#if defined(USB_CAN_BE_DEVICE) - -#include - -uint8_t Endpoint_Write_Stream_LE (const void *const Buffer, uint16_t Length, uint16_t *const BytesProcessed) { - USBD_Endpoint_t* ep = &device.Endpoints[device.CurrentEndpoint]; - uint16_t Bytes = 0; - uint16_t BytesTransfered = 0; - uint8_t ErrorCode; - uint16_t prev_length = 0; - if (BytesProcessed!=NULL) { - Length -= *BytesProcessed; - BytesTransfered = *BytesProcessed; - } - - while (Length) { - if (ep->InInUse) - continue; - if (Endpoint_IsReadWriteAllowed()) { - Bytes = ep->InBufferLength - ep->InBytesAvailable > Length ? Length : ep->InBufferLength - ep->InBytesAvailable; - MEMCPY((void *)((uint32_t)ep->InBuffer + (uint32_t)ep->InBytesAvailable), (void *)((uint32_t)Buffer + (uint32_t)BytesTransfered), Bytes); - ep->InBytesAvailable += Bytes; - BytesTransfered += Bytes; - prev_length = Length; - Length -= Bytes; - } - else { - Endpoint_ClearIN(); - if (BytesProcessed!=NULL) { - *BytesProcessed = BytesTransfered; - return ENDPOINT_RWSTREAM_IncompleteTransfer; - } - - if ((ErrorCode = Endpoint_WaitUntilReady()) != 0) { - return ErrorCode; - } - - - } - } - - if((Length == 0) && (prev_length == ep->MaxPacketSize)) - { - zlp_flag = true; - } - return ENDPOINT_RWSTREAM_NoError; -} - -void SwapCopy(void *const Dest, const void *const Src,uint32_t Length) { - uint32_t i = 0; - while(iInInUse) - continue; - if (Endpoint_IsReadWriteAllowed()) { - Bytes = ep->InBufferLength - ep->InBytesAvailable > Length ? Length : ep->InBufferLength - ep->InBytesAvailable; - SwapCopy((void *)((uint32_t)ep->InBuffer + (uint32_t)ep->InBytesAvailable),(void *)((uint32_t)Buffer + (uint32_t)BytesTransfered), Bytes); - ep->InBytesAvailable += Bytes; - BytesTransfered += Bytes; - Length -= Bytes; - } - else { - Endpoint_ClearIN(); - if (BytesProcessed!=NULL) { - *BytesProcessed = BytesTransfered; - return ENDPOINT_RWSTREAM_IncompleteTransfer; - } - - if ((ErrorCode = Endpoint_WaitUntilReady()) != 0) { - return ErrorCode; - } - - - } - } - return ENDPOINT_RWSTREAM_NoError; -} - -uint8_t Endpoint_Read_Stream_LE (void *const Buffer, uint16_t Length, uint16_t *const BytesProcessed) { - USBD_Endpoint_t* ep = &device.Endpoints[device.CurrentEndpoint]; - uint16_t Bytes = 0; - uint16_t BytesTransfered = 0; - uint8_t ErrorCode; - - if (BytesProcessed!=NULL) { - Length -= *BytesProcessed; - BytesTransfered = *BytesProcessed; - } - - while (Length) { - if (ep->OutInUse) - continue; - if (Endpoint_IsReadWriteAllowed()) { - Bytes = ep->OutBytesAvailable > Length ? Length : ep->OutBytesAvailable; - MEMCPY((void *)((uint32_t)Buffer + (uint32_t)BytesTransfered), (void *)((uint32_t)ep->OutBuffer + (uint32_t)ep->OutOffset), Bytes); - ep->OutBytesAvailable -= Bytes; - ep->OutOffset += Bytes; - BytesTransfered += Bytes; - Length -= Bytes; - } - else { - Endpoint_ClearOUT(); - if (BytesProcessed!=NULL) { - *BytesProcessed = BytesTransfered; - return ENDPOINT_RWSTREAM_IncompleteTransfer; - } - - if ((ErrorCode = Endpoint_WaitUntilReady()) != 0) { - return ErrorCode; - } - - } - } - return ENDPOINT_RWSTREAM_NoError; -} - -uint8_t Endpoint_Read_Stream_BE (void *const Buffer, uint16_t Length, uint16_t *const BytesProcessed) { - USBD_Endpoint_t* ep = &device.Endpoints[device.CurrentEndpoint]; - uint16_t Bytes = 0; - uint16_t BytesTransfered = 0; - uint8_t ErrorCode; - - if (BytesProcessed!=NULL) { - Length -= *BytesProcessed; - BytesTransfered = *BytesProcessed; - } - - while (Length) { - if (ep->InInUse) - continue; - if (Endpoint_IsReadWriteAllowed()) { - Bytes = ep->OutBytesAvailable > Length ? Length : ep->OutBytesAvailable; - SwapCopy((void *)((uint32_t)Buffer + (uint32_t)BytesTransfered), (void *)((uint32_t)ep->OutBuffer + (uint32_t)ep->OutOffset), Bytes); - ep->OutBytesAvailable -= Bytes; - ep->OutOffset += Bytes; - BytesTransfered += Bytes; - Length -= Bytes; - } - else { - Endpoint_ClearOUT(); - if (BytesProcessed!=NULL) { - *BytesProcessed = BytesTransfered; - return ENDPOINT_RWSTREAM_IncompleteTransfer; - } - - if ((ErrorCode = Endpoint_WaitUntilReady()) != 0) { - return ErrorCode; - } - - - } - } - return ENDPOINT_RWSTREAM_NoError; -} - -uint8_t Endpoint_Write_Control_Stream_LE (const void *const Buffer, uint16_t Length) { - USBD_Endpoint_t *EndPoint = &device.Endpoints[0]; - uint16_t Bytes; - - while (Length) { - if (!EndPoint->InInUse) { - if (EndPoint->InBufferLength > Length) { - Bytes = Length; - } else { - Bytes = EndPoint->InBufferLength; - } - MEMCPY(EndPoint->InBuffer,Buffer,Bytes); - EndPoint->InBytesAvailable += Bytes; - Length -= Bytes; - - Endpoint_ClearIN(); - } - } - return ENDPOINT_RWCSTREAM_NoError; -} - -uint8_t Endpoint_Write_Control_Stream_BE (const void *const Buffer, uint16_t Length) { - return Endpoint_Write_Control_Stream_LE(Buffer,Length); -} - -uint8_t Endpoint_Read_Control_Stream_LE (void *const Buffer, uint16_t Length) { - USBD_Endpoint_t *EndPoint = &device.Endpoints[0]; - uint16_t Bytes; - - while (Length) { - if (EndPoint->IsOutRecieved) { - Bytes = EndPoint->OutBytesAvailable > Length - ? Length : EndPoint->OutBytesAvailable; - MEMCPY(Buffer,EndPoint->OutBuffer,Bytes); - EndPoint->OutBytesAvailable -= Bytes; - Length -= Bytes; - - Endpoint_ClearOUT(); - } - } - return ENDPOINT_RWCSTREAM_NoError; -} - -uint8_t Endpoint_Read_Control_Stream_BE (void *const Buffer, uint16_t Length) { - return Endpoint_Read_Control_Stream_LE(Buffer,Length); -} - -uint8_t Endpoint_Null_Stream(uint16_t Length, - uint16_t* const BytesProcessed) { - USBD_Endpoint_t* ep = &device.Endpoints[device.CurrentEndpoint]; - uint16_t Bytes = 0; - uint16_t BytesTransfered = 0; - uint8_t ErrorCode; - - if (BytesProcessed!=NULL) { - Length -= *BytesProcessed; - BytesTransfered = *BytesProcessed; - } - - while (Length) { - if (ep->InInUse) - continue; - if (Endpoint_IsReadWriteAllowed()) { - Bytes = ep->InBufferLength - ep->InBytesAvailable > Length ? Length : ep->InBufferLength - ep->InBytesAvailable; - memset(ep->InBuffer + ep->InBytesAvailable,0x0,Bytes); - ep->InBytesAvailable += Bytes; - BytesTransfered += Bytes; - Length -= Bytes; - } - else { - Endpoint_ClearIN(); - if (BytesProcessed!=NULL) { - *BytesProcessed = BytesTransfered; - return ENDPOINT_RWSTREAM_IncompleteTransfer; - } - - if ((ErrorCode = Endpoint_WaitUntilReady()) != 0) { - return ErrorCode; - } - - - } - } - return ENDPOINT_RWSTREAM_NoError; -} -#endif -#endif - -#endif /* UC_FAMILY == XMC4 */ diff --git a/cores/usblib/Core/XMC4000/EndpointStream_XMC4000.h b/cores/usblib/Core/XMC4000/EndpointStream_XMC4000.h deleted file mode 100644 index 36dba3d7..00000000 --- a/cores/usblib/Core/XMC4000/EndpointStream_XMC4000.h +++ /dev/null @@ -1,443 +0,0 @@ -#ifdef XMC4_SERIES - -/* - LUFA Library - Copyright (C) Dean Camera, 2013. - - dean [at] fourwalledcubicle [dot] com - www.lufa-lib.org -*/ - -/* - Copyright 2013 Dean Camera (dean [at] fourwalledcubicle [dot] com) - - Permission to use, copy, modify, distribute, and sell this - software and its documentation for any purpose is hereby granted - without fee, provided that the above copyright notice appear in - all copies and that both that the copyright notice and this - permission notice and warranty disclaimer appear in supporting - documentation, and that the name of the author not be used in - advertising or publicity pertaining to distribution of the - software without specific, written prior permission. - - The author disclaims all warranties with regard to this - software, including all implied warranties of merchantability - and fitness. In no event shall the author be liable for any - special, indirect or consequential damages or any damages - whatsoever resulting from loss of use, data or profits, whether - in an action of contract, negligence or other tortious action, - arising out of or in connection with the use or performance of - this software. -*/ -/******************************************************************************* - * - * Copyright (C) 2013 Infineon Technologies AG. All rights reserved. - * - * Infineon Technologies AG (Infineon) is supplying this software for use with - * Infineon's microcontrollers. - * This file can be freely distributed within development tools that are - * supporting such microcontrollers. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, - * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * -********************************************************************************/ - - - -/** \file - * \brief Endpoint data stream transmission and reception management for the XMC microcontrollers. - * \copydetails Group_EndpointStreamRW - * - * \note This file should not be included directly. It is automatically included as needed by the USB driver - * dispatch header located in LUFA/Drivers/USB/USB.h. - */ - -/** \ingroup Group_EndpointStreamRW - * \defgroup Group_EndpointStreamRW Read/Write of Multi-Byte Streams - * \brief Endpoint data stream transmission and reception management for the Infineon XMC architecture. - * - * Functions, macros, variables, enums and types related to data reading and writing of data streams from - * and to endpoints. - * - * @{ - */ - -#ifndef ENDPOINTSTREAM_XMC4000_H_ -#define ENDPOINTSTREAM_XMC4000_H_ -#if defined(USB0) - #include <../../Common/Common.h> - #include <../USBMode.h> - #include <../USBTask.h> - -#if defined(__cplusplus) - extern "C" { -#endif - - /* Preprocessor Checks: */ - #if !defined(__INCLUDE_FROM_USB_DRIVER) - #error Do not include this file directly. Include LUFA/Drivers/USB/USB.h instead. - #endif - - /** \name Stream functions for null data */ - //@{ - - /** Reads and discards the given number of bytes from the currently selected endpoint's bank, - * discarding fully read packets from the host as needed. The last packet is not automatically - * discarded once the remaining bytes has been read; the user is responsible for manually - * discarding the last packet from the host via the \ref Endpoint_ClearOUT() macro. - * - * If the BytesProcessed parameter is \c NULL, the entire stream transfer is attempted at once, - * failing or succeeding as a single unit. If the BytesProcessed parameter points to a valid - * storage location, the transfer will instead be performed as a series of chunks. Each time - * the endpoint bank becomes empty while there is still data to process (and after the current - * packet has been acknowledged) the BytesProcessed location will be updated with the total number - * of bytes processed in the stream, and the function will exit with an error code of - * \ref ENDPOINT_RWSTREAM_IncompleteTransfer. This allows for any abort checking to be performed - * in the user code - to continue the transfer, call the function again with identical parameters - * and it will resume until the BytesProcessed value reaches the total transfer length. - * - * Single Stream Transfer Example: - * \code - * uint8_t ErrorCode; - * - * if ((ErrorCode = Endpoint_Discard_Stream(512, NULL)) != ENDPOINT_RWSTREAM_NoError) - * { - * // Stream failed to complete - check ErrorCode here - * } - * \endcode - * - * Partial Stream Transfers Example: - * \code - * uint8_t ErrorCode; - * uint16_t BytesProcessed; - * - * BytesProcessed = 0; - * while ((ErrorCode = Endpoint_Discard_Stream(512, &BytesProcessed)) == ENDPOINT_RWSTREAM_IncompleteTransfer) - * { - * // Stream not yet complete - do other actions here, abort if required - * } - * - * if (ErrorCode != ENDPOINT_RWSTREAM_NoError) - * { - * // Stream failed to complete - check ErrorCode here - * } - * \endcode - * - * \note This routine should not be used on CONTROL type endpoints. - * - * \param[in] Length Number of bytes to discard via the currently selected endpoint. - * \param[in] BytesProcessed Pointer to a location where the total number of bytes processed in the current - * transaction should be updated, \c NULL if the entire stream should be read at once. - * - * \return A value from the \ref Endpoint_Stream_RW_ErrorCodes_t enum. - */ - uint8_t Endpoint_Discard_Stream(uint16_t Length, - uint16_t* const BytesProcessed); - - /** Writes a given number of zeroed bytes to the currently selected endpoint's bank, sending - * full packets to the host as needed. The last packet is not automatically sent once the - * remaining bytes have been written; the user is responsible for manually sending the last - * packet to the host via the \ref Endpoint_ClearIN() macro. - * - * If the BytesProcessed parameter is \c NULL, the entire stream transfer is attempted at once, - * failing or succeeding as a single unit. If the BytesProcessed parameter points to a valid - * storage location, the transfer will instead be performed as a series of chunks. Each time - * the endpoint bank becomes full while there is still data to process (and after the current - * packet transmission has been initiated) the BytesProcessed location will be updated with the - * total number of bytes processed in the stream, and the function will exit with an error code of - * \ref ENDPOINT_RWSTREAM_IncompleteTransfer. This allows for any abort checking to be performed - * in the user code - to continue the transfer, call the function again with identical parameters - * and it will resume until the BytesProcessed value reaches the total transfer length. - * - * Single Stream Transfer Example: - * \code - * uint8_t ErrorCode; - * - * if ((ErrorCode = Endpoint_Null_Stream(512, NULL)) != ENDPOINT_RWSTREAM_NoError) - * { - * // Stream failed to complete - check ErrorCode here - * } - * \endcode - * - * Partial Stream Transfers Example: - * \code - * uint8_t ErrorCode; - * uint16_t BytesProcessed; - * - * BytesProcessed = 0; - * while ((ErrorCode = Endpoint_Null_Stream(512, &BytesProcessed)) == ENDPOINT_RWSTREAM_IncompleteTransfer) - * { - * // Stream not yet complete - do other actions here, abort if required - * } - * - * if (ErrorCode != ENDPOINT_RWSTREAM_NoError) - * { - * // Stream failed to complete - check ErrorCode here - * } - * \endcode - * - * \note This routine should not be used on CONTROL type endpoints. - * - * \param[in] Length Number of zero bytes to send via the currently selected endpoint. - * \param[in] BytesProcessed Pointer to a location where the total number of bytes processed in the current - * transaction should be updated, \c NULL if the entire stream should be read at once. - * - * \return A value from the \ref Endpoint_Stream_RW_ErrorCodes_t enum. - */ - uint8_t Endpoint_Null_Stream(uint16_t Length, - uint16_t* const BytesProcessed); - - //@} - - /** \name Stream functions for RAM source/destination data */ - //@{ - - /** Writes the given number of bytes to the endpoint from the given buffer in little endian, - * sending full packets to the host as needed. The last packet filled is not automatically sent; - * the user is responsible for manually sending the last written packet to the host via the - * \ref Endpoint_ClearIN() macro. - * - * If the BytesProcessed parameter is \c NULL, the entire stream transfer is attempted at once, - * failing or succeeding as a single unit. If the BytesProcessed parameter points to a valid - * storage location, the transfer will instead be performed as a series of chunks. Each time - * the endpoint bank becomes full while there is still data to process (and after the current - * packet transmission has been initiated) the BytesProcessed location will be updated with the - * total number of bytes processed in the stream, and the function will exit with an error code of - * \ref ENDPOINT_RWSTREAM_IncompleteTransfer. This allows for any abort checking to be performed - * in the user code - to continue the transfer, call the function again with identical parameters - * and it will resume until the BytesProcessed value reaches the total transfer length. - * - * Single Stream Transfer Example: - * \code - * uint8_t DataStream[512]; - * uint8_t ErrorCode; - * - * if ((ErrorCode = Endpoint_Write_Stream_LE(DataStream, sizeof(DataStream), - * NULL)) != ENDPOINT_RWSTREAM_NoError) - * { - * // Stream failed to complete - check ErrorCode here - * } - * \endcode - * - * Partial Stream Transfers Example: - * \code - * uint8_t DataStream[512]; - * uint8_t ErrorCode; - * uint16_t BytesProcessed; - * - * BytesProcessed = 0; - * while ((ErrorCode = Endpoint_Write_Stream_LE(DataStream, sizeof(DataStream), - * &BytesProcessed)) == ENDPOINT_RWSTREAM_IncompleteTransfer) - * { - * // Stream not yet complete - do other actions here, abort if required - * } - * - * if (ErrorCode != ENDPOINT_RWSTREAM_NoError) - * { - * // Stream failed to complete - check ErrorCode here - * } - * \endcode - * - * \note This routine should not be used on CONTROL type endpoints. - * - * \param[in] Buffer Pointer to the source data buffer to read from. - * \param[in] Length Number of bytes to read for the currently selected endpoint into the buffer. - * \param[in] BytesProcessed Pointer to a location where the total number of bytes processed in the current - * transaction should be updated, \c NULL if the entire stream should be written at once. - * - * \return A value from the \ref Endpoint_Stream_RW_ErrorCodes_t enum. - */ - uint8_t Endpoint_Write_Stream_LE (const void *const Buffer, uint16_t Length, uint16_t *const BytesProcessed) ATTR_NON_NULL_PTR_ARG(1); - - /** Writes the given number of bytes to the endpoint from the given buffer in big endian, - * sending full packets to the host as needed. The last packet filled is not automatically sent; - * the user is responsible for manually sending the last written packet to the host via the - * \ref Endpoint_ClearIN() macro. - * - * \note This routine should not be used on CONTROL type endpoints. - * - * \param[in] Buffer Pointer to the source data buffer to read from. - * \param[in] Length Number of bytes to read for the currently selected endpoint into the buffer. - * \param[in] BytesProcessed Pointer to a location where the total number of bytes processed in the current - * transaction should be updated, \c NULL if the entire stream should be written at once. - * - * \return A value from the \ref Endpoint_Stream_RW_ErrorCodes_t enum. - */ - uint8_t Endpoint_Write_Stream_BE (const void *const Buffer, uint16_t Length, uint16_t *const BytesProcessed) ATTR_NON_NULL_PTR_ARG(1); - - /** Reads the given number of bytes from the endpoint from the given buffer in little endian, - * discarding fully read packets from the host as needed. The last packet is not automatically - * discarded once the remaining bytes has been read; the user is responsible for manually - * discarding the last packet from the host via the \ref Endpoint_ClearOUT() macro. - * - * If the BytesProcessed parameter is \c NULL, the entire stream transfer is attempted at once, - * failing or succeeding as a single unit. If the BytesProcessed parameter points to a valid - * storage location, the transfer will instead be performed as a series of chunks. Each time - * the endpoint bank becomes empty while there is still data to process (and after the current - * packet has been acknowledged) the BytesProcessed location will be updated with the total number - * of bytes processed in the stream, and the function will exit with an error code of - * \ref ENDPOINT_RWSTREAM_IncompleteTransfer. This allows for any abort checking to be performed - * in the user code - to continue the transfer, call the function again with identical parameters - * and it will resume until the BytesProcessed value reaches the total transfer length. - * - * Single Stream Transfer Example: - * \code - * uint8_t DataStream[512]; - * uint8_t ErrorCode; - * - * if ((ErrorCode = Endpoint_Read_Stream_LE(DataStream, sizeof(DataStream), - * NULL)) != ENDPOINT_RWSTREAM_NoError) - * { - * // Stream failed to complete - check ErrorCode here - * } - * \endcode - * - * Partial Stream Transfers Example: - * \code - * uint8_t DataStream[512]; - * uint8_t ErrorCode; - * uint16_t BytesProcessed; - * - * BytesProcessed = 0; - * while ((ErrorCode = Endpoint_Read_Stream_LE(DataStream, sizeof(DataStream), - * &BytesProcessed)) == ENDPOINT_RWSTREAM_IncompleteTransfer) - * { - * // Stream not yet complete - do other actions here, abort if required - * } - * - * if (ErrorCode != ENDPOINT_RWSTREAM_NoError) - * { - * // Stream failed to complete - check ErrorCode here - * } - * \endcode - * - * \note This routine should not be used on CONTROL type endpoints. - * - * \param[out] Buffer Pointer to the destination data buffer to write to. - * \param[in] Length Number of bytes to send via the currently selected endpoint. - * \param[in] BytesProcessed Pointer to a location where the total number of bytes processed in the current - * transaction should be updated, \c NULL if the entire stream should be read at once. - * - * \return A value from the \ref Endpoint_Stream_RW_ErrorCodes_t enum. - */ - uint8_t Endpoint_Read_Stream_LE (void *const Buffer, uint16_t Length, uint16_t *const BytesProcessed) ATTR_NON_NULL_PTR_ARG(1); - - /** Reads the given number of bytes from the endpoint from the given buffer in big endian, - * discarding fully read packets from the host as needed. The last packet is not automatically - * discarded once the remaining bytes has been read; the user is responsible for manually - * discarding the last packet from the host via the \ref Endpoint_ClearOUT() macro. - * - * \note This routine should not be used on CONTROL type endpoints. - * - * \param[out] Buffer Pointer to the destination data buffer to write to. - * \param[in] Length Number of bytes to send via the currently selected endpoint. - * \param[in] BytesProcessed Pointer to a location where the total number of bytes processed in the current - * transaction should be updated, \c NULL if the entire stream should be read at once. - * - * \return A value from the \ref Endpoint_Stream_RW_ErrorCodes_t enum. - */ - uint8_t Endpoint_Read_Stream_BE (void *const Buffer, uint16_t Length, uint16_t *const BytesProcessed) ATTR_NON_NULL_PTR_ARG(1); - - /** Writes the given number of bytes to the CONTROL type endpoint from the given buffer in little endian, - * sending full packets to the host as needed. The host OUT acknowledgement is not automatically cleared - * in both failure and success states; the user is responsible for manually clearing the status OUT packet - * to finalize the transfer's status stage via the \ref Endpoint_ClearOUT() macro. - * - * \note This function automatically sends the last packet in the data stage of the transaction; when the - * function returns, the user is responsible for clearing the status stage of the transaction. - * Note that the status stage packet is sent or received in the opposite direction of the data flow. - * \n\n - * - * \note This routine should only be used on CONTROL type endpoints. - * - * \warning Unlike the standard stream read/write commands, the control stream commands cannot be chained - * together; i.e. the entire stream data must be read or written at the one time. - * - * \param[in] Buffer Pointer to the source data buffer to read from. - * \param[in] Length Number of bytes to read for the currently selected endpoint into the buffer. - * - * \return A value from the \ref Endpoint_ControlStream_RW_ErrorCodes_t enum. - */ - uint8_t Endpoint_Write_Control_Stream_LE (const void *const Buffer, uint16_t Length) ATTR_NON_NULL_PTR_ARG(1); - - /** Writes the given number of bytes to the CONTROL type endpoint from the given buffer in big endian, - * sending full packets to the host as needed. The host OUT acknowledgement is not automatically cleared - * in both failure and success states; the user is responsible for manually clearing the status OUT packet - * to finalize the transfer's status stage via the \ref Endpoint_ClearOUT() macro. - * - * \note This function automatically sends the last packet in the data stage of the transaction; when the - * function returns, the user is responsible for clearing the status stage of the transaction. - * Note that the status stage packet is sent or received in the opposite direction of the data flow. - * \n\n - * - * \note This routine should only be used on CONTROL type endpoints. - * - * \warning Unlike the standard stream read/write commands, the control stream commands cannot be chained - * together; i.e. the entire stream data must be read or written at the one time. - * - * \param[in] Buffer Pointer to the source data buffer to read from. - * \param[in] Length Number of bytes to read for the currently selected endpoint into the buffer. - * - * \return A value from the \ref Endpoint_ControlStream_RW_ErrorCodes_t enum. - */ - uint8_t Endpoint_Write_Control_Stream_BE (const void *const Buffer, uint16_t Length) ATTR_NON_NULL_PTR_ARG(1); - - /** Reads the given number of bytes from the CONTROL endpoint from the given buffer in little endian, - * discarding fully read packets from the host as needed. The device IN acknowledgement is not - * automatically sent after success or failure states; the user is responsible for manually sending the - * status IN packet to finalize the transfer's status stage via the \ref Endpoint_ClearIN() macro. - * - * \note This function automatically sends the last packet in the data stage of the transaction; when the - * function returns, the user is responsible for clearing the status stage of the transaction. - * Note that the status stage packet is sent or received in the opposite direction of the data flow. - * \n\n - * - * \note This routine should only be used on CONTROL type endpoints. - * - * \warning Unlike the standard stream read/write commands, the control stream commands cannot be chained - * together; i.e. the entire stream data must be read or written at the one time. - * - * \param[out] Buffer Pointer to the destination data buffer to write to. - * \param[in] Length Number of bytes to send via the currently selected endpoint. - * - * \return A value from the \ref Endpoint_ControlStream_RW_ErrorCodes_t enum. - */ - uint8_t Endpoint_Read_Control_Stream_LE (void *const Buffer, uint16_t Length) ATTR_NON_NULL_PTR_ARG(1); - - /** Reads the given number of bytes from the CONTROL endpoint from the given buffer in big endian, - * discarding fully read packets from the host as needed. The device IN acknowledgement is not - * automatically sent after success or failure states; the user is responsible for manually sending the - * status IN packet to finalize the transfer's status stage via the \ref Endpoint_ClearIN() macro. - * - * \note This function automatically sends the last packet in the data stage of the transaction; when the - * function returns, the user is responsible for clearing the status stage of the transaction. - * Note that the status stage packet is sent or received in the opposite direction of the data flow. - * \n\n - * - * \note This routine should only be used on CONTROL type endpoints. - * - * \warning Unlike the standard stream read/write commands, the control stream commands cannot be chained - * together; i.e. the entire stream data must be read or written at the one time. - * - * \param[out] Buffer Pointer to the destination data buffer to write to. - * \param[in] Length Number of bytes to send via the currently selected endpoint. - * - * \return A value from the \ref Endpoint_ControlStream_RW_ErrorCodes_t enum. - */ - uint8_t Endpoint_Read_Control_Stream_BE (void *const Buffer, uint16_t Length) ATTR_NON_NULL_PTR_ARG(1); - - //@} - -#if defined(__cplusplus) - } -#endif - -#endif /* USBD_ENDPOINTSTREAM_XMC4000_H_ */ -#endif -/** @} */ - -#endif /* UC_FAMILY == XMC4 */ diff --git a/cores/usblib/Core/XMC4000/Endpoint_XMC4000.c b/cores/usblib/Core/XMC4000/Endpoint_XMC4000.c deleted file mode 100644 index b8cd6050..00000000 --- a/cores/usblib/Core/XMC4000/Endpoint_XMC4000.c +++ /dev/null @@ -1,254 +0,0 @@ -#ifdef XMC4_SERIES - -/******************************************************************************* - Copyright (c) 2013, Infineon Technologies AG ** - All rights reserved. ** - ** - Redistribution and use in source and binary forms, with or without ** - modification,are permitted provided that the following conditions are met: ** - ** - *Redistributions of source code must retain the above copyright notice, ** - this list of conditions and the following disclaimer. ** - *Redistributions in binary form must reproduce the above copyright notice, ** - this list of conditions and the following disclaimer in the documentation ** - and/or other materials provided with the distribution. ** - *Neither the name of the copyright holders nor the names of its contributors ** - may be used to endorse or promote products derived from this software without** - specific prior written permission. ** - ** - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ** - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ** - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ** - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE ** - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ** - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ** - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ** - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ** - CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ** - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ** - POSSIBILITY OF SUCH DAMAGE. ** - ** - To improve the quality of the software, users are encouraged to share ** - modifications, enhancements or bug fixes with Infineon Technologies AG ** - dave@infineon.com). ** - ** -********************************************************************************/ -/** - * @file - * - * @App Version internal release for evaluation, no public release! - * - * @brief Source file for LUFA endpoint functions - */ -#if defined(USB0) -#include <../../Common/Common.h> -#define __INCLUDE_FROM_USB_DRIVER -#include <../USBMode.h> - -#if defined(USB_CAN_BE_DEVICE) - -#include <../EndPoint.h> - - -#define USB_STREAM_TIMEOUT_MS 100 - -extern volatile uint8_t zlp_flag; - -uint8_t Endpoint_WaitUntilReady(void) -{ - #if (USB_STREAM_TIMEOUT_MS < 0xFF) - uint8_t TimeoutMSRem = USB_STREAM_TIMEOUT_MS; - #else - uint16_t TimeoutMSRem = USB_STREAM_TIMEOUT_MS; - #endif - - uint16_t PreviousFrameNumber = USB_Device_GetFrameNumber(); - - for (;;) - { - if (Endpoint_GetEndpointDirection() == ENDPOINT_DIR_IN) - { - if (Endpoint_IsINReady()) - return ENDPOINT_READYWAIT_NoError; - } - else - { - if (Endpoint_IsOUTReceived()) - return ENDPOINT_READYWAIT_NoError; - } - - uint8_t USB_DeviceState_LCL = USB_DeviceState; - - if (USB_DeviceState_LCL == DEVICE_STATE_Unattached) - return ENDPOINT_READYWAIT_DeviceDisconnected; - else if (USB_DeviceState_LCL == DEVICE_STATE_Suspended) - return ENDPOINT_READYWAIT_BusSuspended; - else if (Endpoint_IsStalled()) - return ENDPOINT_READYWAIT_EndpointStalled; - - uint16_t CurrentFrameNumber = USB_Device_GetFrameNumber(); - - if (CurrentFrameNumber != PreviousFrameNumber) - { - PreviousFrameNumber = CurrentFrameNumber; - - if (!(TimeoutMSRem--)) - return ENDPOINT_READYWAIT_Timeout; - } - } -} - -void Endpoint_ClearOUT(void) { - USBD_Endpoint_t *ep = &device.Endpoints[device.CurrentEndpoint]; - /* if we have data left which isn't read yet, we leave this routine to not override it */ - if (ep->IsEnabled == 0) - return; - /* First Check whether we have data in the driver */ - ep->OutBytesAvailable = device.Driver->EndpointRead(ep->Address,ep->OutBuffer,ep->OutBufferLength); - ep->OutOffset = 0; - /* If we didn't request new data and all data has been read, request new */ - if (!ep->OutInUse && !ep->OutBytesAvailable) { - ep->OutInUse = true; - ep->IsOutRecieved = 0; - device.Driver->EndpointReadStart(ep->Address, - ep->OutBufferLength); - } -} - -void Endpoint_ClearIN(void) -{ - USBD_Endpoint_t *ep = &device.Endpoints[device.CurrentEndpoint]; - int32_t data_count; - /* don't clear if in use or not enabled */ - if (ep->InInUse == 1 || ep->IsEnabled == 0) - return; - ep->InInUse = true; - /* store transfer information to loop over, if underlying is smaller */ - ep->InDataBuffer = ep->InBuffer; - ep->InDataLeft = ep->InBytesAvailable; - ep->InBytesAvailable = 0; - /* make next 3 operations atomic. Do not get interrupted.*/ - NVIC_DisableIRQ(USB0_0_IRQn); - data_count = device.Driver->EndpointWrite(ep->Address, - ep->InDataBuffer,ep->InDataLeft); - ep->InDataBuffer += data_count; - ep->InDataLeft -= data_count; - NVIC_EnableIRQ(USB0_0_IRQn); - if((zlp_flag == true) && (ep->Number != 0)) - { - /*Send a ZLP from here*/ - while(ep->InInUse) - { - ; - } - ep->InInUse = true; - device.Driver->EndpointWrite(ep->Address, - ep->InDataBuffer,0); - zlp_flag = false; - } -} - -bool Endpoint_IsReadWriteAllowed(void) { - USBD_Endpoint_t *EndPoint = &device.Endpoints[device.CurrentEndpoint]; - bool Retval = false; - - if(EndPoint->Direction) - { - Retval = (EndPoint->InBytesAvailable < EndPoint->InBufferLength) ? true : false; - } - else - { - Retval = (EndPoint->OutBytesAvailable > 0) ? true : false; - } - return Retval; -} - -void Endpoint_Write_8(const uint8_t Data) { - USBD_Endpoint_t *EndPoint = &device.Endpoints[device.CurrentEndpoint]; - bool Success = false; - - do - { - if(EndPoint->InBytesAvailable < EndPoint->InBufferLength) - { - EndPoint->InBuffer[EndPoint->InBytesAvailable] = Data; - EndPoint->InBytesAvailable++; - - Success = true; - } - }while(!Success); -} - -uint8_t Endpoint_Read_8(void) { - USBD_Endpoint_t *EndPoint = &device.Endpoints[device.CurrentEndpoint]; - bool Success = false; - uint8_t data = 0; - do - { - if(EndPoint->OutBytesAvailable > 0) - { - data = EndPoint->OutBuffer[EndPoint->OutOffset]; - EndPoint->OutOffset++; - EndPoint->OutBytesAvailable--; - Success = true; - } - }while(!Success); - return data; -} - -void Endpoint_Write_32_LE(const uint32_t Data) { - USBD_Endpoint_t *EndPoint = &device.Endpoints[device.CurrentEndpoint]; - bool Success = false; - - do { - if(EndPoint->InBytesAvailable < (EndPoint->InBufferLength - 3)) { - *(uint32_t*)(EndPoint->InBuffer + EndPoint->InBytesAvailable) = Data; - EndPoint->InBytesAvailable+=4; - - Success = true; - } - }while(!Success); -} - -uint32_t Endpoint_Read_32_LE(void) { - USBD_Endpoint_t *EndPoint = &device.Endpoints[device.CurrentEndpoint]; - bool Success = false; - uint32_t data = 0; - - do { - if(EndPoint->OutBytesAvailable > 3) { - data = *(uint32_t*)(EndPoint->OutBuffer + EndPoint->OutOffset); - EndPoint->OutOffset+=4; - EndPoint->OutBytesAvailable-=4; - - Success = true; - } - } while(!Success); - return data; -} - -bool Endpoint_ConfigureEndpointTable(const USB_Endpoint_Table_t* const Table, - const uint8_t Entries) { - uint8_t i; - uint8_t Number; - for (i=0;iEndpointConfigure(Table[i].Address, (XMC_USBD_ENDPOINT_TYPE_t)Table[i].Type, Table[i].Size) != XMC_USBD_STATUS_OK) - return false; - /* Set device core values */ - device.Endpoints[Number].Address = Table[i].Address; - device.Endpoints[Number].MaxPacketSize = Table[i].Size; - device.Endpoints[Number].IsConfigured = 1; - device.Endpoints[Number].IsEnabled = 1; - /* Start read for out endpoints */ - if (!(Table[i].Address & ENDPOINT_DIR_MASK)) - device.Driver->EndpointReadStart(Table[i].Address, - device.Endpoints[Number].OutBufferLength); - } - return true; -} - -#endif -#endif -#endif /* UC_FAMILY == XMC4 */ diff --git a/cores/usblib/Core/XMC4000/Endpoint_XMC4000.h b/cores/usblib/Core/XMC4000/Endpoint_XMC4000.h deleted file mode 100644 index 52ba064e..00000000 --- a/cores/usblib/Core/XMC4000/Endpoint_XMC4000.h +++ /dev/null @@ -1,413 +0,0 @@ -#ifdef XMC4_SERIES - -/* - LUFA Library - Copyright (C) Dean Camera, 2013. - - dean [at] fourwalledcubicle [dot] com - www.lufa-lib.org -*/ - -/* - Copyright 2013 Dean Camera (dean [at] fourwalledcubicle [dot] com) - - Permission to use, copy, modify, distribute, and sell this - software and its documentation for any purpose is hereby granted - without fee, provided that the above copyright notice appear in - all copies and that both that the copyright notice and this - permission notice and warranty disclaimer appear in supporting - documentation, and that the name of the author not be used in - advertising or publicity pertaining to distribution of the - software without specific, written prior permission. - - The author disclaims all warranties with regard to this - software, including all implied warranties of merchantability - and fitness. In no event shall the author be liable for any - special, indirect or consequential damages or any damages - whatsoever resulting from loss of use, data or profits, whether - in an action of contract, negligence or other tortious action, - arising out of or in connection with the use or performance of - this software. -*/ -/******************************************************************************* - * - * Copyright (C) 2013 Infineon Technologies AG. All rights reserved. - * - * Infineon Technologies AG (Infineon) is supplying this software for use with - * Infineon's microcontrollers. - * This file can be freely distributed within development tools that are - * supporting such microcontrollers. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, - * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - */ - -/** \file - * - * Functions, macros, variables, enums and types related to data reading and writing of primitive data types - * from and to endpoints. - */ - -/** \ingroup Group_EndpointPacketManagement - * - * Functions, macros, variables, enums and types related to packet management of endpoints. - */ - -/** \ingroup Group_EndpointManagement - * Functions, macros and enums related to endpoint management when in USB Device mode. This - * module contains the endpoint management macros, as well as endpoint interrupt and data - * send/receive functions for various data types. - * - * @{ - */ - -#ifndef ENDPOINT_XMC4000_H_ -#define ENDPOINT_XMC4000_H_ -#if defined(USB0) - #include <../../Common/Common.h> - #include <../USBTask.h> - #include <../USBInterrupt.h> - #include <../USBController.h> - -/* Enable C linkage for C++ Compilers: */ -#if defined(__cplusplus) - extern "C" { -#endif - - /* Preprocessor Checks: */ - #if !defined(__INCLUDE_FROM_USB_DRIVER) - #error Do not include this file directly. Include LUFA/Drivers/USB/USB.h instead. - #endif - - /* Public Interface - May be used in end-application: */ - - /** Enum for the possible error return codes of the \ref Endpoint_WaitUntilReady() function. - * - * \ingroup Group_EndpointRW - */ - enum Endpoint_WaitUntilReady_ErrorCodes_t - { - ENDPOINT_READYWAIT_NoError = 0, /**< Endpoint is ready for next packet, no error. */ - ENDPOINT_READYWAIT_EndpointStalled = 1, /**< The endpoint was stalled during the stream - * transfer by the host or device. - */ - ENDPOINT_READYWAIT_DeviceDisconnected = 2, /**< Device was disconnected from the host while - * waiting for the endpoint to become ready. - */ - ENDPOINT_READYWAIT_BusSuspended = 3, /**< The USB bus has been suspended by the host and - * no USB endpoint traffic can occur until the bus - * has resumed. - */ - ENDPOINT_READYWAIT_Timeout = 4, /**< The host failed to accept or send the next packet - * within the software timeout period set by the - * \ref USB_STREAM_TIMEOUT_MS macro. - */ - }; - - /** Get the endpoint address of the currently selected endpoint. This is typically used to save - * the currently selected endpoint so that it can be restored after another endpoint has been - * manipulated. - * - * \return Index of the currently selected endpoint. - */ - static inline uint8_t Endpoint_GetCurrentEndpoint(void) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE; - static inline uint8_t Endpoint_GetCurrentEndpoint(void) - { - return device.CurrentDirection | device.CurrentEndpoint; - } - - /** Selects the given endpoint address. - * - * Any endpoint operations which do not require the endpoint address to be indicated will operate on - * the currently selected endpoint. - * - * \param[in] Address Endpoint address to select. - */ - static inline void Endpoint_SelectEndpoint(const uint8_t Address) ATTR_ALWAYS_INLINE; - static inline void Endpoint_SelectEndpoint(const uint8_t Address) - { - device.CurrentEndpoint = Address & ENDPOINT_EPNUM_MASK; - device.CurrentDirection = (Address & ENDPOINT_DIR_MASK); - } - - /** Determines if the current CONTROL type endpoint has received a SETUP packet. - * - * \ingroup Group_EndpointPacketManagement - * - * \return Boolean \c true if the selected endpoint has received a SETUP packet, \c false otherwise. - */ - static inline bool Endpoint_IsSETUPReceived(void) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE; - static inline bool Endpoint_IsSETUPReceived(void) - { - return device.IsSetupRecieved; - } - - - /** Clears a received SETUP packet on the currently selected CONTROL type endpoint, freeing up the - * endpoint for the next packet. - * - * \ingroup Group_EndpointPacketManagement - * - * \note This is not applicable for non CONTROL type endpoints. - */ - static inline void Endpoint_ClearSETUP(void) ATTR_ALWAYS_INLINE; - static inline void Endpoint_ClearSETUP(void) - { - device.IsSetupRecieved = 0; - } - - /** Nothing done in this function - * - */ - static inline void Endpoint_ClearStatusStage(void) ATTR_ALWAYS_INLINE; - static inline void Endpoint_ClearStatusStage(void) - { - - } - - /** Determines if the selected IN endpoint is ready for a new packet to be sent to the host. - * - * \ingroup Group_EndpointPacketManagement - * - * \return Boolean \c true if the current endpoint is ready for an IN packet, \c false otherwise. - */ - static inline bool Endpoint_IsINReady(void) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE; - static inline bool Endpoint_IsINReady(void) - { - USBD_Endpoint_t *ep = &device.Endpoints[device.CurrentEndpoint]; - return ep->InInUse == 0 && ep->IsEnabled; - } - - /** Determines if the selected OUT endpoint has received new packet from the host. - * - * \ingroup Group_EndpointPacketManagement - * - * \return Boolean \c true if current endpoint is has received an OUT packet, \c false otherwise. - */ - static inline bool Endpoint_IsOUTReceived(void) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE; - static inline bool Endpoint_IsOUTReceived(void) - { - USBD_Endpoint_t *ep = &device.Endpoints[device.CurrentEndpoint]; - return ep->IsOutRecieved; - } - - /** Determines the currently selected endpoint's direction. - * - * \return The currently selected endpoint's direction, as a \c ENDPOINT_DIR_* mask. - */ - static inline uint8_t Endpoint_GetEndpointDirection(void) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE; - static inline uint8_t Endpoint_GetEndpointDirection(void) - { - USBD_Endpoint_t *ep = &device.Endpoints[device.CurrentEndpoint]; - return ep->Address & ENDPOINT_DIR_MASK; - } - - /** Indicates the number of bytes currently stored in the current endpoint's selected bank. - * - * \ingroup Group_EndpointRW - * - * \return Total number of bytes in the currently selected Endpoint's FIFO buffer. - */ - static inline uint16_t Endpoint_BytesInEndpoint(void) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE; - static inline uint16_t Endpoint_BytesInEndpoint(void) - { - USBD_Endpoint_t *ep = &device.Endpoints[device.CurrentEndpoint]; - if (ep->Direction) - return ep->InBytesAvailable; - else - return ep->OutBytesAvailable; - } - - /** Acknowledges an OUT packet to the host on the currently selected endpoint, freeing up the endpoint - * for the next packet and switching to the alternative endpoint bank if double banked. - * - * \ingroup Group_EndpointPacketManagement - */ - void Endpoint_ClearOUT(void); - - /** Sends an IN packet to the host on the currently selected endpoint, freeing up the endpoint for the - * next packet and switching to the alternative endpoint bank if double banked. - * - * \ingroup Group_EndpointPacketManagement - */ - void Endpoint_ClearIN(void); - - /** Determines if the currently selected endpoint may be read from (if data is waiting in the endpoint - * bank and the endpoint is an OUT direction, or if the bank is not yet full if the endpoint is an IN - * direction). This function will return false if an error has occurred in the endpoint, if the endpoint - * is an OUT direction and no packet (or an empty packet) has been received, or if the endpoint is an IN - * direction and the endpoint bank is full. - * - * \ingroup Group_EndpointPacketManagement - * - * \return Boolean \c true if the currently selected endpoint may be read from or written to, depending - * on its direction. - */ - bool Endpoint_IsReadWriteAllowed(void); - - /** Stalls the current endpoint, indicating to the host that a logical problem occurred with the - * indicated endpoint and that the current transfer sequence should be aborted. This provides a - * way for devices to indicate invalid commands to the host so that the current transfer can be - * aborted and the host can begin its own recovery sequence. - * - * The currently selected endpoint remains stalled until either the \ref Endpoint_ClearStall() macro - * is called, or the host issues a CLEAR FEATURE request to the device for the currently selected - * endpoint. - * - * \ingroup Group_EndpointPacketManagement - */ - static inline void Endpoint_StallTransaction(void) ATTR_ALWAYS_INLINE; - static inline void Endpoint_StallTransaction(void) - { - device.Endpoints[device.CurrentEndpoint].IsHalted = 1; - device.Driver->EndpointStall(device.CurrentDirection | device.CurrentEndpoint,1); - } - - /** Clears the STALL condition on the currently selected endpoint. - * - * \ingroup Group_EndpointPacketManagement - */ - static inline void Endpoint_ClearStall(void) ATTR_ALWAYS_INLINE; - static inline void Endpoint_ClearStall(void) - { - device.Endpoints[device.CurrentEndpoint].IsHalted = 0; - device.Driver->EndpointStall(device.CurrentDirection | device.CurrentEndpoint,0); - } - - /** Determines if the currently selected endpoint is stalled, \c false otherwise. - * - * \ingroup Group_EndpointPacketManagement - * - * \return Boolean \c true if the currently selected endpoint is stalled, \c false otherwise. - */ - static inline bool Endpoint_IsStalled(void) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE; - static inline bool Endpoint_IsStalled(void) - { - return device.Endpoints[device.CurrentEndpoint].IsHalted == 1 ? true : false; - } - - /** Resets the endpoint bank FIFO. This clears all the endpoint banks and resets the USB controller's - * data In and Out pointers to the bank's contents. - * - * \param[in] Address Endpoint address whose FIFO buffers are to be reset. - */ - static inline void Endpoint_ResetEndpoint(const uint8_t Address) ATTR_ALWAYS_INLINE; - static inline void Endpoint_ResetEndpoint(const uint8_t Address) - { - device.Driver->EndpointAbort(device.CurrentDirection | device.CurrentEndpoint); - USBD_Endpoint_t *ep = &device.Endpoints[device.CurrentEndpoint]; - ep->IsHalted = 0; - ep->IsOutRecieved = 0; - ep->InBytesAvailable = 0; - ep->InDataLeft = 0; - ep->InInUse = 0; - ep->OutBytesAvailable = 0; - ep->OutOffset = 0; - ep->OutInUse = 0; - } - - /** Resets the data toggle of the currently selected endpoint. */ - static inline void Endpoint_ResetDataToggle(void) ATTR_ALWAYS_INLINE; - static inline void Endpoint_ResetDataToggle(void) - { - xmc_device.endpoint_in_register[device.CurrentEndpoint]->diepctl |= (1<<28); - } - - - /** Configures a table of endpoint descriptions, in sequence. This function can be used to configure multiple - * endpoints at the same time. - * - * \note Endpoints with a zero address will be ignored, thus this function cannot be used to configure the - * control endpoint. - * - * \param[in] Table Pointer to a table of endpoint descriptions. - * \param[in] Entries Number of entries in the endpoint table to configure. - * - * \return Boolean \c true if all endpoints configured successfully, \c false otherwise. - */ - bool Endpoint_ConfigureEndpointTable(const USB_Endpoint_Table_t* const Table, - const uint8_t Entries); - - /** Spin-loops until the currently selected non-control endpoint is ready for the next packet of data - * to be read or written to it. - * - * \note This routine should not be called on CONTROL type endpoints. - * - * \ingroup Group_EndpointRW - * - * \return A value from the \ref Endpoint_WaitUntilReady_ErrorCodes_t enum. - */ - uint8_t Endpoint_WaitUntilReady(void); - - /** Reads one byte from the currently selected endpoint's bank, for OUT direction endpoints. - * - * \ingroup Group_EndpointPrimitiveRW - * - * \return Next byte in the currently selected endpoint's FIFO buffer. - */ - uint8_t Endpoint_Read_8(void); - - /** Writes one byte to the currently selected endpoint's bank, for IN direction endpoints. - * - * \ingroup Group_EndpointPrimitiveRW - * - * \param[in] Data Data to write into the the currently selected endpoint's FIFO buffer. - */ - void Endpoint_Write_8(const uint8_t data); - - /** Writes four bytes to the currently selected endpoint's bank in little endian format, for IN - * direction endpoints. - * - * \ingroup Group_EndpointPrimitiveRW - * - * \param[in] Data Data to write to the currently selected endpoint's FIFO buffer. - */ - void Endpoint_Write_32_LE(const uint32_t Data); - - /** Reads four bytes from the currently selected endpoint's bank in little endian format, for OUT - * direction endpoints. - * - * \ingroup Group_EndpointPrimitiveRW - * - * \return Next four bytes in the currently selected endpoint's FIFO buffer. - */ - uint32_t Endpoint_Read_32_LE(void); - - /** Writes two bytes to the currently selected endpoint's bank in little endian format, for IN - * direction endpoints. - * - * \ingroup Group_EndpointPrimitiveRW - * - * \param[in] Data Data to write to the currently selected endpoint's FIFO buffer. - */ - static inline void Endpoint_Write_16_LE(const uint16_t Data) ATTR_ALWAYS_INLINE; - static inline void Endpoint_Write_16_LE(const uint16_t Data) - { - Endpoint_Write_8(Data & 0xFF); - Endpoint_Write_8(Data >> 8); - } - - /** Determines if the currently selected endpoint is enabled, but not necessarily configured. - * - * \return Boolean \c true if the currently selected endpoint is enabled, \c false otherwise. - */ - static inline bool Endpoint_IsEnabled(void) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE; - static inline bool Endpoint_IsEnabled(void) - { - return true; - } - - /* Disable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - } - #endif - -/** @} */ - -#endif /* ENDPOINT_XMC4000_H_ */ -#endif -#endif /* UC_FAMILY == XMC4 */ diff --git a/cores/usblib/Core/XMC4000/USBController_XMC4000.c b/cores/usblib/Core/XMC4000/USBController_XMC4000.c deleted file mode 100644 index a31e1adc..00000000 --- a/cores/usblib/Core/XMC4000/USBController_XMC4000.c +++ /dev/null @@ -1,564 +0,0 @@ -#ifdef XMC4_SERIES - -/* - LUFA Library - Copyright (C) Dean Camera, 2014. - - dean [at] fourwalledcubicle [dot] com - www.lufa-lib.org -*/ - -/* - Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com) - - Permission to use, copy, modify, distribute, and sell this - software and its documentation for any purpose is hereby granted - without fee, provided that the above copyright notice appear in - all copies and that both that the copyright notice and this - permission notice and warranty disclaimer appear in supporting - documentation, and that the name of the author not be used in - advertising or publicity pertaining to distribution of the - software without specific, written prior permission. - - The author disclaims all warranties with regard to this - software, including all implied warranties of merchantability - and fitness. In no event shall the author be liable for any - special, indirect or consequential damages or any damages - whatsoever resulting from loss of use, data or profits, whether - in an action of contract, negligence or other tortious action, - arising out of or in connection with the use or performance of - this software. -*/ -#if defined(USB0) -#include <../../Common/Common.h> - -#define __INCLUDE_FROM_USB_DRIVER -#define __INCLUDE_FROM_USB_CONTROLLER_C -#include <../USBController.h> - -USB_Device_t device; - -uint8_t endpoint0_in_buffer[256]; -uint8_t endpoint0_out_buffer[256]; - -/** - * \ingroup USBD_Core_Driver - * \defgroup EP0_Handling Handling of EP0 Control Request - * \brief - * @{ - */ - -/** - * \brief Handle protocol stall on EP0 - * - * Stalls EP0 and then restarts a new transfer including setting state to \ref IDLE. - */ -void USBD_HandleEP0_Stall() { - /* When we stall ep0 as protocol stall, we go back into idle state and start a new read */ - device.Driver->EndpointStall(ENDPOINT_DIR_IN | 0,1); - device.EP0_State = IDLE; - device.Driver->EndpointReadStart(0,24); -} - -/** - * \brief Handle device request on endpoint 0 - * - * By default any USB device has to support a subset of device control request defiened by - * the USB specification. All request required by the spec are handle within this function. - * Before a handling of the request is done by this function, it dispatches it to the - * \ref EVENT_USB_Device_ControlRequest function. There the user has the chance to complete - * some custom request or override the handling of this function. If the user has handled the - * request, he has to call \ref Endpoint_ClearSETUP. - * - */ -void USB_Device_ProcessControlRequest() { - uint32_t length = 0,ret; - uint16_t status = 0; - void *buffer; - uint8_t Value; - uint16_t Index; - - Value = USB_ControlRequest.wValue & 0x00FF; - - /* Handling of descriptors */ - EVENT_USB_Device_ControlRequest(); - if (!device.IsSetupRecieved) - return; - - /* default request handling */ - switch (USB_ControlRequest.bRequest) { - case REQ_ClearFeature: - if ((USB_ControlRequest.bmRequestType & 0x3) == REQREC_ENDPOINT) { - Index = USB_ControlRequest.wIndex & ENDPOINT_EPNUM_MASK; - if ((USB_DeviceState == DEVICE_STATE_Configured || USB_ControlRequest.wIndex==0) && - device.Endpoints[Index].IsConfigured==1) { - device.Endpoints[Index].IsHalted = 0; - device.Driver->EndpointStall(USB_ControlRequest.wIndex,0); - } else { - USBD_HandleEP0_Stall(); - } - break; - } - if ((USB_ControlRequest.bmRequestType & 0x3) == REQREC_DEVICE) { - device.RemoteWakeUp = 0; - break; - } - USBD_HandleEP0_Stall(); - break; - - case REQ_GetConfiguration: - device.Driver->EndpointWrite(0,&device.Configuration,1); - break; - - case REQ_GetDescriptor: - length = CALLBACK_USB_GetDescriptor(USB_ControlRequest.wValue,USB_ControlRequest.wIndex,(void*)&buffer); - if (length==0) - USBD_HandleEP0_Stall(); - else { - length = length < USB_ControlRequest.wLength ? - length : USB_ControlRequest.wLength; - ret = device.Driver->EndpointWrite(0,buffer,length); - device.Endpoints[0].InDataLeft = length - ret; - device.Endpoints[0].InDataBuffer = (uint8_t *)((uint32_t)buffer + ret); - } - break; - - case REQ_GetInterface: - if (USB_DeviceState == DEVICE_STATE_Configured) { - device.Driver->EndpointWrite(0,&device.InterfaceSettings[USB_ControlRequest.wIndex],1); - break; - } - if (USB_DeviceState == DEVICE_STATE_Addressed) { - USBD_HandleEP0_Stall(); - break; - } - break; - - case REQ_GetStatus: - if ((USB_ControlRequest.bmRequestType & 0x3) == REQREC_DEVICE) { - status = device.RemoteWakeUp << 1 | device.SelfPowered; - device.Driver->EndpointWrite(0,(uint8_t*)&status,2); - break; - } - if ((USB_ControlRequest.bmRequestType & 0x3) == REQREC_INTERFACE && USB_DeviceState == DEVICE_STATE_Configured) { - status = 0; - device.Driver->EndpointWrite(0,(uint8_t*)&status,2); - break; - } - /* print endpoint status only when(or): - * - Device_Address_state and ep == 0 - * - Device_configured_state and ep is configured - */ - if ((USB_ControlRequest.bmRequestType & 0x3) == REQREC_ENDPOINT) { - Index = USB_ControlRequest.wIndex & 0xFF & ENDPOINT_EPNUM_MASK; - if ((USB_DeviceState == DEVICE_STATE_Configured || USB_ControlRequest.wIndex==0) && - device.Endpoints[Index].IsConfigured==1) { - status = device.Endpoints[Index].IsHalted; - device.Driver->EndpointWrite(0,(uint8_t*)&status,2); - break; - } - } - /* default stall */ - USBD_HandleEP0_Stall(); - break; - - case REQ_SetAddress: - if (Value == 0) - USB_DeviceState = DEVICE_STATE_Default; - else - USB_DeviceState = DEVICE_STATE_Addressed; - device.Driver->DeviceSetAddress(Value,XMC_USBD_SET_ADDRESS_STAGE_SETUP); - break; - - case REQ_SetConfiguration: - /* Regardless the state update the configuration to unconfigure endpoints */ - device.Configuration = Value; - EVENT_USB_Device_ConfigurationChanged(); - /* when config 0 is choosen, we are back in address state */ - if (Value == 0) { - USB_DeviceState = DEVICE_STATE_Addressed; - break; - } - /* go ahead only with vailid config. (must be set in event) */ - if (device.IsConfigured == 1) - USB_DeviceState = DEVICE_STATE_Configured; - else - USBD_HandleEP0_Stall(); - break; - - case REQ_SetDescriptor: - /* Set Descriptor not supported, so stall */ - USBD_HandleEP0_Stall(); - break; - - case REQ_SetInterface: - if (USB_DeviceState == DEVICE_STATE_Configured) { - /* TODO: Check if interface and altsetting exists and configuration is allowed, else stall */ - device.InterfaceSettings[USB_ControlRequest.wIndex] = USB_ControlRequest.wValue; - break; - } - if (USB_DeviceState == DEVICE_STATE_Addressed) { - USBD_HandleEP0_Stall(); - break; - } - break; - - case REQ_SetFeature: - /* we do not support test mode */ - if (Value == FEATURE_SEL_TestMode) { - USBD_HandleEP0_Stall(); - break; - } - /* configured state */ - if (USB_DeviceState == DEVICE_STATE_Configured) { - switch (Value) { - case FEATURE_SEL_DeviceRemoteWakeup: - device.RemoteWakeUp = 1; - break; - case FEATURE_SEL_EndpointHalt: - Index = USB_ControlRequest.wIndex & 0xFF & (uint8_t)XMC_USBD_ENDPOINT_NUMBER_MASK; - if (device.Endpoints[Index].IsConfigured == 0) - USBD_HandleEP0_Stall(); - else { - device.Endpoints[Index].IsHalted = 1; - device.Driver->EndpointStall(USB_ControlRequest.wIndex,1); - } - break; - } - break; - } - /* when addressed, only ep0 can be halted */ - if (USB_DeviceState == DEVICE_STATE_Addressed) { - if (Value == FEATURE_SEL_EndpointHalt && - (USB_ControlRequest.bmRequestType & 0x3) == REQREC_ENDPOINT && - (USB_ControlRequest.wIndex & 0x00FF) == 0x0) { - device.Endpoints[0].IsHalted = 1; - USBD_HandleEP0_Stall(); - break; - } - } - /* default behaviour is stall */ - USBD_HandleEP0_Stall(); - break; - - case REQ_SynchFrame: - /* Not yet supported */ - USBD_HandleEP0_Stall(); - break; - - default: - USBD_HandleEP0_Stall(); - } - device.IsSetupRecieved = 0; -} - -/** - * \brief Handle complete IN transfer on EP0 - * - * In \ref IN_DATA state it starts a receive and switches to \ref OUT_STATUS state. - * In \ref IN_STATUS state its starts a new read of setup packets and switches to \ref IDLE. - */ -void USBD_HandleEP0_IN() { - if (device.EP0_State == IN_DATA) { - /* Read zero length out data packet */ - device.Driver->EndpointReadStart(0,0); - device.EP0_State = OUT_STATUS; - } - if (device.EP0_State == IN_STATUS) { - /* Request new setup packet */ - device.Driver->EndpointReadStart(device.Endpoints[0].Address,24); - device.EP0_State = IDLE; - } -} - - -/** - * \brief Handle complete OUT transfer on EP0 - * - * Handles the OUT packet based on the state of endpoint 0. Starts a new read for new SETUP packets, when in \ref OUT_STATUS. - * When endpoint 0 is in \ref OUT_DATA state, it handles the received data and starts a write transaction for \ref IN_STATUS. - */ -void USBD_HandleEP0_OUT() { - if (device.EP0_State == OUT_DATA) { - /* Now we have the data for handling the request */ - USB_Device_ProcessControlRequest(); - /* Zero length packet for status stage */ - device.Driver->EndpointWrite(ENDPOINT_DIR_MASK & 0,0,0); - device.EP0_State = IN_STATUS; - } - if (device.EP0_State == OUT_STATUS) { - /* Request new setup packet */ - device.Driver->EndpointReadStart(device.Endpoints[0].Address,24); - device.EP0_State = IDLE; - } -} - -/** - * \brief Handle SETUP packet on EP0 - * - * Handles the setup package an switches to correct state. If data is send from host to device it switches into \ref OUT_DATA state. - * When the hosts sends all data within the setup package and \ref wLength equals zero, starts processing the request and sends a - * in status reponse including the switch to \ref IN_STATUS. - * When the host expects data from the device, the function processes the control request and switches to \ref IN_DATA state. - */ -void USBD_HandleEP0_SETUP() { - /* read setup package from ep0 */ - int32_t ret_val = device.Driver->EndpointRead(0,(void*)&USB_ControlRequest,8); -#if NO_COPY_DRIVER - MEMCPY(&USB_ControlRequest,device.Endpoints[0].OutBuffer,sizeof(USB_ControlRequest)); -#endif - device.IsSetupRecieved = true; - if (ret_val != 8 ) - return; - - /* preprocess */ - /* if length is zero we have only a in_status phase */ - if (USB_ControlRequest.wLength==0) { - device.EP0_State = IN_STATUS; - USB_Device_ProcessControlRequest(); - device.Driver->EndpointWrite(0,0,0); - } else { - if (USB_ControlRequest.bmRequestType & CONTROL_REQTYPE_DIRECTION) { - device.EP0_State = IN_DATA; - USB_Device_ProcessControlRequest(); - } - else { - device.EP0_State = OUT_DATA; - /* Do not process request here, first read data */ - device.Driver->EndpointReadStart(0,USB_ControlRequest.wLength); - } - } -} - -/** - * @} - */ - -/** - * \brief Device event handler for XMC Driver - * - * The device can have several events, where it notifies the application about. - * - * \note Not all events are available on all chip series. (Power Events are only supported on XMC4500) - * \see USB_USBD_EVENT - */ -void USBD_SignalDeviceEventHandler(XMC_USBD_EVENT_t event) { - int i; - switch (event) { - case XMC_USBD_EVENT_RESET: - USB_DeviceState = DEVICE_STATE_Default; - device.EP0_State = IDLE; - device.RemoteWakeUp = 0; - /* Reset endpoints and configuration */ - for (i=0;i<(uint8_t)XMC_USBD_NUM_EPS; i++) { - device.Endpoints[i].InInUse = 0; - device.Endpoints[i].OutInUse = 0; - device.Endpoints[i].IsHalted = 0; - if (i!=0 && device.Endpoints[i].IsConfigured) { - device.Driver->EndpointUnconfigure(device.Endpoints[i].Address); - device.Endpoints[i].IsConfigured = 0; - device.Endpoints[i].IsEnabled = 0; - } - } - device.Configuration = 0; - for (i=0;iEndpointReadStart(device.Endpoints[0].Address,24); - break; - case XMC_USBD_EVENT_SOF: - EVENT_USB_Device_StartOfFrame(); - break; - case XMC_USBD_EVENT_CONNECT: - EVENT_USB_Device_Connect(); - break; - case XMC_USBD_EVENT_DISCONNECT: - USB_DeviceState = DEVICE_STATE_Powered; - EVENT_USB_Device_Disconnect(); - break; - case XMC_USBD_EVENT_POWER_OFF: - USB_DeviceState = DEVICE_STATE_Unattached; - device.Driver->EndpointUnconfigure(0); - break; - case XMC_USBD_EVENT_POWER_ON: - USB_DeviceState = DEVICE_STATE_Powered; - memset(&device,0x0,sizeof(USB_Device_t)); - device.Driver = &Driver_USBD0; - device.EP0_State = IDLE; - device.Endpoints[0].InBuffer = endpoint0_in_buffer; - device.Endpoints[0].InBufferLength = 256; - device.Endpoints[0].OutBuffer = endpoint0_out_buffer; - device.Endpoints[0].OutBufferLength = 256; - device.Endpoints[0].Direction = 0; - device.Endpoints[0].IsConfigured = 1; - device.Endpoints[0].IsEnabled = 1; - device.Endpoints[0].MaxPacketSize = 64; - - /* then configure endpoint 0 */ - device.Driver->EndpointConfigure(0,XMC_USBD_ENDPOINT_TYPE_CONTROL, - (uint8_t)XMC_USBD_MAX_PACKET_SIZE); - - break; - case XMC_USBD_EVENT_REMOTE_WAKEUP: - break; - case XMC_USBD_EVENT_RESUME: - USB_DeviceState = device.PreSuspendDeviceState; - EVENT_USB_Device_WakeUp(); - break; - case XMC_USBD_EVENT_SUSPEND: - device.PreSuspendDeviceState = USB_DeviceState; - USB_DeviceState = DEVICE_STATE_Suspended; - EVENT_USB_Device_Suspend(); - break; - default: - return; - } -} - -/** - * \brief Endpoint event handler for the XMC driver - * - * If the driver detects an event (See \ref USB_USBD_EP_EVENT) for a specified endpoint it - * calls this function. Based on the event some further action is taken, e.g. process control - * request or update transfer information and read data from the driver into the core buffer. - * - * \param[in] ep_addr Endpoint address - * \param[in] ep_event Endpoint event type - * - */ -void USBD_SignalEndpointEvent_Handler (uint8_t ep_addr, XMC_USBD_EP_EVENT_t ep_event) { - USBD_Endpoint_t *ep = &device.Endpoints[ep_addr & ENDPOINT_EPNUM_MASK]; - uint8_t temp_num,temp_dir; - int32_t data_count; - /* store CurrentEndpoint and direction for restore after handling */ - temp_num = device.CurrentEndpoint; - temp_dir = device.CurrentDirection; - /* select the given endpoint */ - device.CurrentEndpoint = ep_addr & ENDPOINT_EPNUM_MASK; - device.CurrentDirection = ep_addr & ENDPOINT_DIR_MASK; - /* choose what to do based on the event */ - switch (ep_event) { - case XMC_USBD_EP_EVENT_SETUP: - ep->OutInUse = 0; - switch(device.CurrentEndpoint) { - case 0: - USBD_HandleEP0_SETUP(); - break; - default: - break; - } - break; - case XMC_USBD_EP_EVENT_OUT: - ep->IsOutRecieved = 1; - if (ep->OutBytesAvailable == 0) { - ep->OutOffset = 0; /* clear offset, new data is there */ - ep->OutBytesAvailable = device.Driver->EndpointRead(ep->Address,ep->OutBuffer,ep->OutBufferLength); - } - ep->OutInUse = 0; - switch(device.CurrentEndpoint) { - case 0: - USBD_HandleEP0_OUT(); - break; - default: - break; - } - break; - case XMC_USBD_EP_EVENT_IN: - /* loop write transfers */ - if (ep->InDataLeft> 0) { - data_count = device.Driver->EndpointWrite(ep->Address,ep->InDataBuffer,ep->InDataLeft); - ep->InDataLeft -= data_count; - ep->InDataBuffer+= data_count; - return; - } else if (ep->Number == 0 && ep->InBytesAvailable > 0 && ep->InBytesAvailable!=USB_ControlRequest.wLength && ep->InBytesAvailable % ep->MaxPacketSize == 0) { - /* if the amount of data for endpoint 0 is exact the requested amount, then no zlp has to be send */ - device.Driver->EndpointWrite(ep->Address,0,0); - } - ep->InBytesAvailable = 0; - ep->InInUse = 0; - switch(device.CurrentEndpoint) { - case 0: - USBD_HandleEP0_IN(); - break; - default: - break; - } - break; - } - device.CurrentEndpoint = temp_num; - device.CurrentDirection = temp_dir; -} - -/** - * \brief Initialize driver core and driver - * - * Intializes the USB driver core data structures and sets it into default state. Afterwards - * it initializes the USB device controller driver and prepare it for connection via \ref USBD_Connect. - */ -int USBD_Initialize(XMC_USBD_t *usb_init) { - int32_t status = 0; - memset(&device,0x0,sizeof(USB_Device_t)); - USB_DeviceState = DEVICE_STATE_Unattached; - device.Driver = &Driver_USBD0; - device.EP0_State = IDLE; - device.Endpoints[0].InBuffer = endpoint0_in_buffer; - device.Endpoints[0].InBufferLength = 256; - device.Endpoints[0].OutBuffer = endpoint0_out_buffer; - device.Endpoints[0].OutBufferLength = 256; - device.Endpoints[0].Direction = 0; - device.Endpoints[0].IsConfigured = 1; - device.Endpoints[0].IsEnabled = 1; - device.Endpoints[0].MaxPacketSize = 64; - - /* First initalize the device */ - status = device.Driver->Initialize(usb_init); - if (status != XMC_USBD_STATUS_OK) - return -1; - - /* then configure endpoint 0 */ - device.Driver->EndpointConfigure(0,XMC_USBD_ENDPOINT_TYPE_CONTROL, - (uint8_t)XMC_USBD_MAX_PACKET_SIZE); - if (status != XMC_USBD_STATUS_OK) { - device.Driver->Uninitialize(); - return -1; - } - - return 0; -} - -/** - * \brief Is the enumeration finished? - * - * Tell the USB device controller driver if the enumeration interrupt have been reached - */ -int USB_IsEnumDone(void){ - if (device.Driver->IsEnumDone()) - return 1; - else - return 0; - } - - -/** - * \brief Set the buffer for an endpoint - * - * The user has to ensure the an endpoint has a valid buffer set - * in order to ensure proper work. - * - * \param[in] addr Endpoint address - * \param[in] buf Buffer pointer - * \param[in] len Buffer length - */ -void USBD_SetEndpointBuffer(uint8_t addr,uint8_t *buf,uint16_t len) { - uint8_t number = addr & ENDPOINT_EPNUM_MASK; - if (addr & ENDPOINT_DIR_MASK) { - device.Endpoints[number].InBuffer = buf; - device.Endpoints[number].InBufferLength = len; - } else { - device.Endpoints[number].OutBuffer = buf; - device.Endpoints[number].OutBufferLength = len; - } -} - -#endif -#endif /* UC_FAMILY == XMC4 */ diff --git a/cores/usblib/Core/XMC4000/USBController_XMC4000.h b/cores/usblib/Core/XMC4000/USBController_XMC4000.h deleted file mode 100644 index 90947c4b..00000000 --- a/cores/usblib/Core/XMC4000/USBController_XMC4000.h +++ /dev/null @@ -1,291 +0,0 @@ -#ifdef XMC4_SERIES - -/* - LUFA Library - Copyright (C) Dean Camera, 2014. - - dean [at] fourwalledcubicle [dot] com - www.lufa-lib.org -*/ - -/* - Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com) - - Permission to use, copy, modify, distribute, and sell this - software and its documentation for any purpose is hereby granted - without fee, provided that the above copyright notice appear in - all copies and that both that the copyright notice and this - permission notice and warranty disclaimer appear in supporting - documentation, and that the name of the author not be used in - advertising or publicity pertaining to distribution of the - software without specific, written prior permission. - - The author disclaims all warranties with regard to this - software, including all implied warranties of merchantability - and fitness. In no event shall the author be liable for any - special, indirect or consequential damages or any damages - whatsoever resulting from loss of use, data or profits, whether - in an action of contract, negligence or other tortious action, - arising out of or in connection with the use or performance of - this software. -*/ - -/** \file - * \brief USB Controller definitions for the Infineon XMC4000 microcontrollers. - * \copydetails Group_USBManagement_XMC4000 - * - * \note This file should not be included directly. It is automatically included as needed by the USB driver - * dispatch header located in USB/USB.h. - */ - -/** \ingroup Group_USBManagement - * \defgroup Group_USBManagement_XMC4000 USB Interface Management (XMC4000) - * \brief USB Controller definitions for the Infineon XMC4000 microcontrollers. - * - * Functions, macros, variables, enums and types related to the setup and management of the USB interface. - * - * @{ - */ - -#ifndef __USBCONTROLLER_XMC4000_H__ -#define __USBCONTROLLER_XMC4000_H__ -#if defined(USB0) - /* Includes: */ - #include - - #include <../../Common/Common.h> - #include <../USBMode.h> - #include <../Events.h> - #include <../USBTask.h> - #include <../USBInterrupt.h> - - /* Enable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - extern "C" { - #endif - - /* Preprocessor Checks and Defines: */ - #if !defined(__INCLUDE_FROM_USB_DRIVER) - #error Do not include this file directly. Include USB/USB.h instead. - #endif - - /* Public Interface - May be used in end-application: */ - /* Macros: */ - #define NO_COPY_DRIVER 0 - - #define NUM_INTERFACES 1 - - /* Macros: */ - #if (!defined(MAX_ENDPOINT_INDEX) && !defined(CONTROL_ONLY_DEVICE)) || defined(__DOXYGEN__) - /** Total number of endpoints (including the default control endpoint at address 0) which may - * be used in the device. - */ - #define ENDPOINT_TOTAL_ENDPOINTS 7 - #else - #if defined(CONTROL_ONLY_DEVICE) - #define ENDPOINT_TOTAL_ENDPOINTS 1 - #else - #define ENDPOINT_TOTAL_ENDPOINTS (MAX_ENDPOINT_INDEX + 1) - #endif - #endif - - /** - * \brief State machine of Endpoint 0 - */ - typedef enum EP0_State - { - DISCONNECT, /**< Device is disconnected */ - IDLE, /**< Endpoint 0 is in IDLE state */ - IN_DATA, /**< Endpoint 0 is sending data */ - IN_STATUS, /**< Endpoint 0 sends a acknowledge to the host */ - OUT_DATA, /**< Endpoint 0 is reading data from the host */ - OUT_STATUS /**< Endpoint 0 waits for an acknowledge from the host */ - } EP0_State_t; - - /* Anonymous structure/union guard start */ - #if defined (__CC_ARM) - #pragma push - #pragma anon_unions - #elif defined (__TASKING__) - #pragma warning 586 - #endif - - /** - * \brief USBD Endpoint - * - * Type define for a USBD Enpoint. This structure represents an endpoint. It contains all necessary data to: - * - control the state of the endpoint - * - manage the data buffer - * - */ - typedef struct USBD_Endpoint - { - /** - * \name Endpoint Parameters - */ - /*@{*/ - union { - uint32_t Address:8; /**< Full device address (including direction) */ - struct { - uint32_t Number:4; /**< Endpoint number */ - uint32_t :3; - uint32_t Direction:1; /**< Endpoint direction */ - }; - - }; - - /* Endpoint flags */ - uint32_t IsConfigured:1; /**< Flag showing that the endpoint is configured */ - uint32_t IsEnabled:1; /**< Flag showing that the endpoint is enabled */ - uint32_t IsHalted:1; /**< Flag showing that the endpoint is halted */ - volatile uint32_t OutInUse:1; /**< Flag showing that the endpoint is in use as out */ - volatile uint32_t InInUse:1; /**< Flag showing that the endpoint is in use as in */ - volatile uint32_t IsOutRecieved:1; /**< Flag showing that an out packet has been received for that endpoint */ - uint32_t MaxPacketSize:7; /**< Maximum packet size for the endpoint */ - /*@}*/ - - /** - * \name Out endpoint buffer management - */ - /*@{*/ - uint32_t OutBytesAvailable; /**< Amount of data in the out buffer */ - uint32_t OutOffset; /**< Amount of data that have been read from the buffer */ - uint8_t *OutBuffer; /**< Address of the out buffer */ - uint32_t OutBufferLength; /**< Length of the out buffer */ - /*@}*/ - - /** - * \name In endpoint buffer management - */ - /*@{*/ - uint32_t InBytesAvailable; /**< Amount of data written into the buffer */ - uint8_t *InBuffer; /**< Address of in Buffer */ - uint32_t InBufferLength; /**< Length of the in buffer */ - uint32_t InDataLeft; /**< Data left in the in buffer to send */ - uint8_t* InDataBuffer; /**< Current start address of the in buffer */ - /*@}*/ - } USBD_Endpoint_t; - - /** \brief USBD Device - * - * Type define for an USB Device. This structure contains the all data of the device for the USB Device Core Driver. - * Especially the data of the endpoints are stored inside. - */ - typedef struct USBD_Device - { - XMC_USBD_DRIVER_t *Driver; /**< USB device controller driver structure */ - USBD_Endpoint_t Endpoints[ENDPOINT_TOTAL_ENDPOINTS]; /**< Endpoint structures describing each endpoint of the device */ - - uint8_t InterfaceSettings[NUM_INTERFACES]; /**< Array of the currently selected AlternativeSetting of an interface */ - uint8_t Configuration; /**< Current USB device configuration */ - uint8_t PreSuspendDeviceState; /**< Device State bevor suspend is recieved to restore the old state, when resume is received */ - EP0_State_t EP0_State; /**< Endpoint 0 state */ - uint8_t CurrentEndpoint; /**< Endpoint selected for the LUFA stack */ - uint8_t CurrentDirection; /**< Direction selected for the LUFA stack */ - uint8_t IsConfigured:1; /**< Flag showing if the device was successfully configured */ - volatile uint8_t IsSetupRecieved:1; /**< Flag showing if a setup packet is received */ - uint8_t RemoteWakeUp:1; /**< Flag for feature Remote WakeUP signaling */ - uint8_t SelfPowered:1; /**< Flag for feature Self Powered */ - } USB_Device_t; - - /* Anonymous structure/union guard end */ - #if defined (__CC_ARM) - #pragma pop - #elif defined (__TASKING__) - #pragma warning restore - #endif - - /* Global Variables: */ - extern USB_Device_t device; - - /* Inline Functions: */ - /** Detaches the device from the USB bus. This has the effect of removing the device from any - * attached host, ceasing USB communications. If no host is present, this prevents any host from - * enumerating the device once attached until \ref USB_Attach() is called. - */ - static inline void USB_Detach(void) ATTR_ALWAYS_INLINE; - static inline void USB_Detach(void) - { - device.Driver->DeviceDisconnect(); - } - - /** Attaches the device to the USB bus. This announces the device's presence to any attached - * USB host, starting the enumeration process. If no host is present, attaching the device - * will allow for enumeration once a host is connected to the device. - * - * This is inexplicably also required for proper operation while in host mode, to enable the - * attachment of a device to the host. This is despite the bit being located in the device-mode - * register and despite the datasheet making no mention of its requirement in host mode. - */ - static inline void USB_Attach(void) ATTR_ALWAYS_INLINE; - static inline void USB_Attach(void) - { - device.Driver->DeviceConnect(); - } - - /* Function Prototypes: */ - /** - * \brief Initialize the USB device core driver - * - * In preparation for using the USB device this function initializes the device core driver and the device controller driver. - * It executes all necessary tasks to start working as USB device and handle request from the host. - * - * \note To start working you need to call \ref USBD_Connect to connect to the host. - */ - int USBD_Initialize(XMC_USBD_t *usb_init); - - - /* Private Interface - For use in library only: */ - #if !defined(__DOXYGEN__) - /** - * \brief Device Event Handler for the device controller driver - * - * Handles device events send by the device controller driver. See \ref USBD_SignalDeviceEvent - */ - void USBD_SignalDeviceEventHandler(XMC_USBD_EVENT_t event); - - /** - * \brief Endpoint Event Handler for the device controller driver - * - * Handles endpoint events send by the device controller driver. See \ref USBD_SignalEndpointEvent_Handler - */ - void USBD_SignalEndpointEvent_Handler (uint8_t ep_addr, XMC_USBD_EP_EVENT_t ep_event); - - /** - * \brief Is the enumeration done? - * - * Returns 1 if the enumeration is done. - */ - int USB_IsEnumDone(void); - - /** \brief Configure an USBD Endpoint - * - * Convenience function to configure an endpoint. It sets the address, the transfer buffer and its size - * and the maximum packet size. - * \param[in] Address Endpoint address - * \param[in] Buffer Endpoint buffer - * \param[in] Length Buffer size - */ - void USBD_SetEndpointBuffer(uint8_t Address,uint8_t *Buffer,uint16_t Length); - - #endif - - /* Includes: */ - #if defined(USB_CAN_BE_DEVICE) || defined(__DOXYGEN__) - #include <../Device.h> - #include <../EndPoint.h> - #include <../DeviceStandardReq.h> - #include <../EndpointStream.h> - #endif - - /* Disable C linkage for C++ Compilers: */ - #if defined(__cplusplus) - } - #endif -#endif -#endif - -/** @} */ - - -#endif /* UC_FAMILY == XMC4 */ diff --git a/cores/usblib/usblib.h b/cores/usblib/usblib.h deleted file mode 100644 index 11d2fb15..00000000 --- a/cores/usblib/usblib.h +++ /dev/null @@ -1,419 +0,0 @@ -#ifdef XMC4_SERIES - -/* - LUFA Library - Copyright (C) Dean Camera, 2014. - - dean [at] fourwalledcubicle [dot] com - www.lufa-lib.org -*/ - -/* - Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com) - - Permission to use, copy, modify, distribute, and sell this - software and its documentation for any purpose is hereby granted - without fee, provided that the above copyright notice appear in - all copies and that both that the copyright notice and this - permission notice and warranty disclaimer appear in supporting - documentation, and that the name of the author not be used in - advertising or publicity pertaining to distribution of the - software without specific, written prior permission. - - The author disclaims all warranties with regard to this - software, including all implied warranties of merchantability - and fitness. In no event shall the author be liable for any - special, indirect or consequential damages or any damages - whatsoever resulting from loss of use, data or profits, whether - in an action of contract, negligence or other tortious action, - arising out of or in connection with the use or performance of - this software. -*/ - -/** \file - * \brief Master include file for the library USB functionality. - * - * Master include file for the library USB functionality. - * - * This file should be included in all user projects making use of the USB portions of the library, instead of - * the individual USB driver submodule headers. - */ - -/** \defgroup Group_USB USB Core - LUFA/Drivers/USB/USB.h - * - * \brief Core driver for the microcontroller hardware USB module - * - * \section Sec_USB_Dependencies Module Source Dependencies - * The following files must be built with any user project that uses this module: - * - LUFA/Drivers/USB/Core/ConfigDescriptors.c (Makefile source module name: LUFA_SRC_USB) - * - LUFA/Drivers/USB/Core/DeviceStandardReq.c (Makefile source module name: LUFA_SRC_USB) - * - LUFA/Drivers/USB/Core/Events.c (Makefile source module name: LUFA_SRC_USB) - * - LUFA/Drivers/USB/Core/HostStandardReq.c (Makefile source module name: LUFA_SRC_USB) - * - LUFA/Drivers/USB/Core/USBTask.c (Makefile source module name: LUFA_SRC_USB) - * - LUFA/Drivers/USB/Core/ARCH/Device_ARCH.c (Makefile source module name: LUFA_SRC_USB) - * - LUFA/Drivers/USB/Core/ARCH/Endpoint_ARCH.c (Makefile source module name: LUFA_SRC_USB) - * - LUFA/Drivers/USB/Core/ARCH/EndpointStream_ARCH.c (Makefile source module name: LUFA_SRC_USB) - * - LUFA/Drivers/USB/Core/ARCH/Host_ARCH.c (Makefile source module name: LUFA_SRC_USB) - * - LUFA/Drivers/USB/Core/ARCH/Pipe_ARCH.c (Makefile source module name: LUFA_SRC_USB) - * - LUFA/Drivers/USB/Core/ARCH/PipeStream_ARCH.c (Makefile source module name: LUFA_SRC_USB) - * - LUFA/Drivers/USB/Core/ARCH/USBController_ARCH.c (Makefile source module name: LUFA_SRC_USB) - * - LUFA/Drivers/USB/Core/ARCH/USBInterrupt_ARCH.c (Makefile source module name: LUFA_SRC_USB) - * - LUFA/Drivers/USB/Class/Common/HIDParser.c (Makefile source module name: LUFA_SRC_USB) - * - * \section Sec_USB_ModDescription Module Description - * Driver and framework for the USB controller of the selected architecture and microcontroller model. This module - * consists of many submodules, and is designed to provide an easy way to configure and control USB host, device - * or OTG mode USB applications. - * - * The USB stack requires the sole control over the USB controller in the microcontroller only; i.e. it does not - * require any additional timers or other peripherals to operate. This ensures that the USB stack requires as few - * resources as possible. - * - * The USB stack can be used in Device Mode for connections to USB Hosts (see \ref Group_Device), in Host mode for - * hosting of other USB devices (see \ref Group_Host), or as a dual role device which can either act as a USB host - * or device depending on what peripheral is connected (see \ref Group_OTG). Both modes also require a common set - * of USB management functions found \ref Group_USBManagement. - */ - -/** \defgroup Group_USBClassDrivers USB Class Drivers - * - * \brief Drivers for the various standardized USB device classes - * - * Drivers for both host and device mode of the standard USB classes, for rapid application development. - * Class drivers give a framework which sits on top of the low level library API, allowing for standard - * USB classes to be implemented in a project with minimal user code. These drivers can be used in - * conjunction with the library low level APIs to implement interfaces both via the class drivers and via - * the standard library APIs. - * - * Multiple device mode class drivers can be used within a project, including multiple instances of the - * same class driver. In this way, USB Hosts and Devices can be made quickly using the internal class drivers - * so that more time and effort can be put into the end application instead of the USB protocol. - * - * The available class drivers and their modes are listed below. - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
USB ClassDevice ModeHost Mode
Android Open AccessoryNoYes
Audio 1.0YesYes
CDC-ACMYesYes
HIDYesYes
MIDIYesYes
Mass StorageYesYes
PrinterYesYes
RNDISYesYes
Still ImageNoYes
- * - * - * \section Sec_USB_UsingClassDrivers Using the Class Drivers - * To make the Class drivers easy to integrate into a user application, they all implement a standardized - * design with similarly named/used function, enums, defines and types. The two different modes are implemented - * slightly differently, and thus will be explained separately. For information on a specific class driver, read - * the class driver's module documentation. - * - * \subsection Sec_USB_ClassDriverDevice Device Mode Class Drivers - * Implementing a Device Mode Class Driver in a user application requires a number of steps to be followed. Firstly, - * the module configuration and state structure must be added to the project source. These structures are named in a - * similar manner between classes, that of USB_ClassInfo_{Class Name}_Device_t, and are used to hold the - * complete state and configuration for each class instance. Multiple class instances is where the power of the class - * drivers lie; multiple interfaces of the same class simply require more instances of the Class Driver's \c USB_ClassInfo_* - * structure. - * - * Inside the ClassInfo structure lies two sections, a \c Config section, and a \c State section. The \c Config - * section contains the instance's configuration parameters, and must have all fields set by the user application - * before the class driver is used. Each Device mode Class driver typically contains a set of configuration parameters - * for the endpoint size/number of the associated logical USB interface, plus any class-specific configuration parameters. - * - * The following is an example of a properly initialized instance of the Audio Class Driver structure: - * - * \code - * USB_ClassInfo_Audio_Device_t My_Audio_Interface = - * { - * .Config = - * { - * .StreamingInterfaceNumber = 1, - * .DataINEndpoint = - * { - * .Address = (ENDPOINT_DIR_IN | 1), - * .Size = 64, - * .Banks = 1, - * }, - * }, - * }; - * \endcode - * - * \note The class driver's configuration parameters should match those used in the device's descriptors that are - * sent to the host. - * - * To initialize the Class driver instance, the driver's {Class Name}_Device_ConfigureEndpoints() function - * should be called in response to the \ref EVENT_USB_Device_ConfigurationChanged() event. This function will return a - * boolean true value if the driver successfully initialized the instance. Like all the class driver functions, this function - * takes in the address of the specific instance you wish to initialize - in this manner, multiple separate instances of - * the same class type can be initialized like this: - * - * \code - * void EVENT_USB_Device_ConfigurationChanged(void) - * { - * LEDs_SetAllLEDs(LEDMASK_USB_READY); - * - * if (!(Audio_Device_ConfigureEndpoints(&My_Audio_Interface))) - * LEDs_SetAllLEDs(LEDMASK_USB_ERROR); - * } - * \endcode - * - * Once initialized, it is important to maintain the class driver's state by repeatedly calling the Class Driver's - * {Class Name}_Device_USBTask() function in the main program loop. The exact implementation of this - * function varies between class drivers, and can be used for any internal class driver purpose to maintain each - * instance. Again, this function uses the address of the instance to operate on, and thus needs to be called for each - * separate instance, just like the main USB maintenance routine \ref USB_USBTask(): - * - * \code - * int main(void) - * { - * SetupHardware(); - * - * LEDs_SetAllLEDs(LEDMASK_USB_NOTREADY); - * - * for (;;) - * { - * if (USB_DeviceState != DEVICE_STATE_Configured) - * Create_And_Process_Samples(); - * - * Audio_Device_USBTask(&My_Audio_Interface); - * USB_USBTask(); - * } - * } - * \endcode - * - * The final standardized Device Class Driver function is the Control Request handler function - * {Class Name}_Device_ProcessControlRequest(), which should be called when the - * \ref EVENT_USB_Device_ControlRequest() event fires. This function should also be called for - * each class driver instance, using the address of the instance to operate on as the function's - * parameter. The request handler will abort if it is determined that the current request is not - * targeted at the given class driver instance, thus these methods can safely be called - * one-after-another in the event handler with no form of error checking: - * - * \code - * void EVENT_USB_Device_ControlRequest(void) - * { - * Audio_Device_ProcessControlRequest(&My_Audio_Interface); - * } - * \endcode - * - * Each class driver may also define a set of callback functions (which are prefixed by \c CALLBACK_* - * in the function's name) which must also be added to the user application - refer to each - * individual class driver's documentation for mandatory callbacks. In addition, each class driver may - * also define a set of events (identifiable by their prefix of \c EVENT_* in the function's name), which - * the user application may choose to implement, or ignore if not needed. - * - * The individual Device Mode Class Driver documentation contains more information on the non-standardized, - * class-specific functions which the user application can then use on the driver instances, such as data - * read and write routines. See each driver's individual documentation for more information on the - * class-specific functions. - * - * \subsection Sec_USB_ClassDriverHost Host Mode Class Drivers - * Implementing a Host Mode Class Driver in a user application requires a number of steps to be followed. Firstly, - * the module configuration and state structure must be added to the project source. These structures are named in a - * similar manner between classes, that of USB_ClassInfo_{Class Name}_Host_t, and are used to hold the - * complete state and configuration for each class instance. Multiple class instances is where the power of the class - * drivers lie; multiple interfaces of the same class simply require more instances of the Class Driver's \c USB_ClassInfo_* - * structure. - * - * Inside the \c USB_ClassInfo_* structure lies two sections, a \c Config section, and a \c State section. The \c Config - * section contains the instance's configuration parameters, and must have all fields set by the user application - * before the class driver is used. Each Device mode Class driver typically contains a set of configuration parameters - * for the endpoint size/number of the associated logical USB interface, plus any class-specific configuration parameters. - * - * The following is an example of a properly initialized instance of the MIDI Host Class Driver structure: - * - * \code - * USB_ClassInfo_MIDI_Host_t My_MIDI_Interface = - * { - * .Config = - * { - * .DataINPipe = - * { - * .Address = (PIPE_DIR_IN | 1), - * .Size = 64, - * .Banks = 1, - * }, - * .DataOUTPipe = - * { - * .Address = (PIPE_DIR_OUT | 2), - * .Size = 64, - * .Banks = 1, - * }, - * }, - * }; - * \endcode - * - * To initialize the Class driver instance, the driver's {Class Name}_Host_ConfigurePipes() function - * should be called in response to the \c EVENT_USB_Host_DeviceEnumerationComplete() event firing. This function will - * will return an error code from the class driver's {Class Name}_EnumerationFailure_ErrorCodes_t enum - * to indicate if the driver successfully initialized the instance and bound it to an interface in the attached device. - * Like all the class driver functions, this function takes in the address of the specific instance you wish to initialize - - * in this manner, multiple separate instances of the same class type can be initialized. A fragment of a Class Driver - * based Host mode application may look like the following: - * - * \code - * void EVENT_USB_Host_DeviceEnumerationComplete(void) - * { - * LEDs_SetAllLEDs(LEDMASK_USB_ENUMERATING); - * - * uint16_t ConfigDescriptorSize; - * uint8_t ConfigDescriptorData[512]; - * - * if (USB_Host_GetDeviceConfigDescriptor(1, &ConfigDescriptorSize, ConfigDescriptorData, - * sizeof(ConfigDescriptorData)) != HOST_GETCONFIG_Successful) - * { - * LEDs_SetAllLEDs(LEDMASK_USB_ERROR); - * return; - * } - * - * if (MIDI_Host_ConfigurePipes(&Keyboard_MIDI_Interface, - * ConfigDescriptorSize, ConfigDescriptorData) != MIDI_ENUMERROR_NoError) - * { - * LEDs_SetAllLEDs(LEDMASK_USB_ERROR); - * return; - * } - * - * if (USB_Host_SetDeviceConfiguration(1) != HOST_SENDCONTROL_Successful) - * { - * LEDs_SetAllLEDs(LEDMASK_USB_ERROR); - * return; - * } - * - * LEDs_SetAllLEDs(LEDMASK_USB_READY); - * } - * \endcode - * - * Note that the function also requires the device's configuration descriptor so that it can determine which interface - * in the device to bind to - this can be retrieved as shown in the above fragment using the - * \ref USB_Host_GetDeviceConfigDescriptor() function. If the device does not implement the interface the class driver - * is looking for, if all the matching interfaces are already bound to class driver instances or if an error occurs while - * binding to a device interface (for example, a device endpoint bank larger that the maximum supported bank size is used) - * the configuration will fail. - * - * To complete the device enumeration after binding the host mode Class Drivers to the attached device, a call to - * \c USB_Host_SetDeviceConfiguration() must be made. If the device configuration is not set within the - * \c EVENT_USB_Host_DeviceEnumerationComplete() event, the host still will assume the device enumeration has failed. - * - * Once initialized, it is important to maintain the class driver's state by repeatedly calling the Class Driver's - * {Class Name}_Host_USBTask() function in the main program loop. The exact implementation of this - * function varies between class drivers, and can be used for any internal class driver purpose to maintain each - * instance. Again, this function uses the address of the instance to operate on, and thus needs to be called for each - * separate instance, just like the main USB maintenance routine \ref USB_USBTask(): - * - * \code - * int main(void) - * { - * SetupHardware(); - * - * LEDs_SetAllLEDs(LEDMASK_USB_NOTREADY); - * - * for (;;) - * { - * if (USB_HostState != HOST_STATE_Configured) - * Create_And_Process_Samples(); - * - * MIDI_Host_USBTask(&My_Audio_Interface); - * USB_USBTask(); - * } - * } - * \endcode - * - * Each class driver may also define a set of callback functions (which are prefixed by \c CALLBACK_* - * in the function's name) which must also be added to the user application - refer to each - * individual class driver's documentation for mandatory callbacks. In addition, each class driver may - * also define a set of events (identifiable by their prefix of \c EVENT_* in the function's name), which - * the user application may choose to implement, or ignore if not needed. - * - * The individual Host Mode Class Driver documentation contains more information on the non-standardized, - * class-specific functions which the user application can then use on the driver instances, such as data - * read and write routines. See each driver's individual documentation for more information on the - * class-specific functions. - */ - -#ifndef __USB_H__ -#define __USB_H__ -#if defined(USB0) - /* Macros: */ - #define __INCLUDE_FROM_USB_DRIVER - - /* Includes: */ - #include - #include - - /* Includes: */ - #include - #include - #include - #include - #include - - #if defined(USB_CAN_BE_HOST) || defined(__DOXYGEN__) - #include - #include - #include - #include - #endif - - #if defined(USB_CAN_BE_DEVICE) || defined(__DOXYGEN__) - #include - #include - #include - #include - #endif - - #if defined(USB_CAN_BE_BOTH) || defined(__DOXYGEN__) - #include - #endif - - #include - #include - #include - -#endif -#endif - -#endif /* UC_FAMILY == XMC4 */ diff --git a/cores/wiring_analog.c b/cores/wiring_analog.c deleted file mode 100644 index a362c3ff..00000000 --- a/cores/wiring_analog.c +++ /dev/null @@ -1,473 +0,0 @@ -/* - Copyright (c) 2011 Arduino. All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - - Copyright (c) 2018 Infineon Technologies AG - This file has been modified for the XMC microcontroller series. -*/ -/* Paul Carpenter March-2019 - Several fixes to remove redundant code - Fix prescaler bug for CCU8 in analogWriteFrequency - analogWrite - Improvements, extra safety and more documentation - analogRead - Change return to 0xFFFFFFFF (an invalid value) for invalid channel - wiring_analog_init - Add dummy reading so background scanning starts on ALL - possible channels meaning first user reading will be valid -*/ -/* Paul Carpenter September-2019 - Add definition ADC_MIN_RESOLUTION for error checking parameters - Add maximum resolution values for helper functions - On errors where possible nothing changed or read - Add helper functions for Read and Write resolution settings for other modules - especially using PWM on analogWrite to scale parameters correctly - getAnaolgReadBits, getAnaolgWriteBits, getAnaolgReadMaximum, getAnaolgWriteMaximum - Add more return values for error trapping - - analogWrite - Change error values for invalid and separate invalid frequency -*/ -//**************************************************************************** -// @Project Includes -//**************************************************************************** -#include "Arduino.h" -#include - -//**************************************************************************** -// @Defines -//**************************************************************************** -#define ADC_CONVERSION_GROUP 0 -#define ADC_MIN_RESOLUTION 8 -#define ADC_MAX_READ_RESOLUTION 12 -#define ANALOG_MAX_WRITE_RESOLUTION 16 - -//**************************************************************************** -// @Global Variables -//**************************************************************************** -static uint8_t _readResolution = 10; -static uint8_t _writeResolution = 8; -uint16_t _readMaximum = 1023; -uint16_t _writeMaximum = 255; - -void wiring_analog_init(void) { - /* Initialization data of VADC Global resources */ - XMC_VADC_GLOBAL_CONFIG_t vadc_global_config; - memset(&vadc_global_config, 0, sizeof(XMC_VADC_GLOBAL_CONFIG_t)); - vadc_global_config.class0.conversion_mode_standard = XMC_VADC_CONVMODE_12BIT; - vadc_global_config.class1.conversion_mode_standard = XMC_VADC_CONVMODE_12BIT; - - XMC_VADC_BACKGROUND_CONFIG_t vadc_background_config = {0}; - - /* Provide clock to VADC and initialize the VADC global registers. */ - XMC_VADC_GLOBAL_Init(VADC, &vadc_global_config); - -#if (XMC_VADC_GROUP_AVAILABLE == 1U) - // ADC grouping - XMC_VADC_GROUP_CONFIG_t vadc_group_config; - memset(&vadc_group_config, 0, sizeof(XMC_VADC_GROUP_CONFIG_t)); - vadc_group_config.class0.conversion_mode_standard = XMC_VADC_CONVMODE_12BIT; - vadc_group_config.class1.conversion_mode_standard = XMC_VADC_CONVMODE_12BIT; - - /* Initialize Group */ - XMC_VADC_GROUP_Init(VADC_G0, &vadc_group_config); - XMC_VADC_GROUP_Init(VADC_G1, &vadc_group_config); - - /* Switch on the converter of the Group*/ - XMC_VADC_GROUP_SetPowerMode(VADC_G0, XMC_VADC_GROUP_POWERMODE_NORMAL); - XMC_VADC_GROUP_SetPowerMode(VADC_G1, XMC_VADC_GROUP_POWERMODE_NORMAL); - - #if (XMC_VADC_MAXIMUM_NUM_GROUPS > 2) - /* Initialize Group */ - XMC_VADC_GROUP_Init(VADC_G2, &vadc_group_config); - XMC_VADC_GROUP_Init(VADC_G3, &vadc_group_config); - - /* Switch on the converter of the Group*/ - XMC_VADC_GROUP_SetPowerMode(VADC_G2, XMC_VADC_GROUP_POWERMODE_NORMAL); - XMC_VADC_GROUP_SetPowerMode(VADC_G3, XMC_VADC_GROUP_POWERMODE_NORMAL); - #endif - -#endif - /* Calibrate the VADC. Make sure you do this after all used VADC groups - are set to normal operation mode. */ - XMC_VADC_GLOBAL_StartupCalibration(VADC); - - /* Initialize the background source hardware. The gating mode is set to - ignore to pass external triggers unconditionally.*/ - XMC_VADC_GLOBAL_BackgroundInit(VADC, &vadc_background_config); - - /* PC Mar-2019 - Dummy read of ALL analogue inputs to ensure ALL analogue channels are - started in background scanning mode, otherwise first readings at least - will always be zero on reading an analogue input. */ - for (uint8_t chan = 0; chan < NUM_ANALOG_INPUTS; chan++) - analogRead(chan); - - // Additional Initialization of DAC starting here -} - -/* Set the resolution of analogRead return values in number of bits. - Default is 10 bits (range from 0 to 1023) - Maximum is 12 bits (range from 0 to 4095) - -PC Sept-2019 Change flow to trap invalid input first and leave at old setting if - Invalid and return valid value or 255 for error, else return setting used - - Add set maximum value for resolution -*/ -uint8_t analogReadResolution(uint8_t res) { - if (res > ADC_MAX_READ_RESOLUTION || res < ADC_MIN_RESOLUTION) - return 255; - - _readResolution = res; - _readMaximum = (uint16_t)(((uint32_t)1U << res) - 1); - return res; -} - -/* Set the resolution of analogWrite parameters in number of bits. - - Default (minimum) is 8 bits (range from 0 to 255). - Maximum is 16 bits (range 0 to 65535) - -PC Sept-2019 Change flow to trap invalid input first and leave at old setting if - Invalid and return valid value or 255 for error, else return setting used - - Add set maximum value for resolution - */ -uint8_t analogWriteResolution(uint8_t res) { - if (res > ANALOG_MAX_WRITE_RESOLUTION || res < ADC_MIN_RESOLUTION) - return 255; - - _writeResolution = res; - _writeMaximum = (uint16_t)(((uint32_t)1U << res) - 1); - return res; -} - -// This appears to be a dummy function and variable not used elsewhere -uint8_t analog_reference = DEFAULT; - -void analogReference(uint8_t ulMode) { analog_reference = ulMode; } - -/* analogRead takes parameter of ADC channel number - return 0xFFFFFFFF for invalid channel */ -uint32_t analogRead(uint8_t channel) { - uint32_t value; - - value = 0xFFFFFFFF; - if (channel < NUM_ANALOG_INPUTS) { - XMC_ADC_t *adc = &mapping_adc[channel]; - -#if (XMC_VADC_GROUP_AVAILABLE == 1U) - // ADC grouping - if (!(adc->enabled)) { - XMC_VADC_CHANNEL_CONFIG_t vadc_gobal_channel_config; - memset(&vadc_gobal_channel_config, 0, sizeof(XMC_VADC_CHANNEL_CONFIG_t)); - vadc_gobal_channel_config.input_class = XMC_VADC_CHANNEL_CONV_GROUP_CLASS1; - vadc_gobal_channel_config.result_reg_number = adc->result_reg_num; - vadc_gobal_channel_config.alias_channel = XMC_VADC_CHANNEL_ALIAS_DISABLED; - - XMC_VADC_RESULT_CONFIG_t vadc_gobal_result_config = {.g_rcr = 0}; - /* Configure a channel belonging to the aforesaid conversion kernel */ - XMC_VADC_GROUP_ChannelInit(adc->group, adc->channel_num, &vadc_gobal_channel_config); - /* Configure a result resource belonging to the aforesaid conversion kernel */ - XMC_VADC_GROUP_ResultInit(adc->group, adc->result_reg_num, &vadc_gobal_result_config); - /* Add channel into the Background Request Source Channel Select Register */ - XMC_VADC_GLOBAL_BackgroundAddChannelToSequence(VADC, (uint32_t)adc->group_num, - (uint32_t)adc->channel_num); - } - /* Start conversion manually using load event trigger*/ - XMC_VADC_GLOBAL_BackgroundTriggerConversion(VADC); - value = XMC_VADC_GROUP_GetResult(adc->group, adc->result_reg_num); -#else - // XMC1100 no ADC grouping - if (!(adc->enabled)) - /* Add a channel to the background source. */ - VADC->BRSSEL[ADC_CONVERSION_GROUP] = (uint32_t)(1U << adc->channel_num); - // Generates conversion request - XMC_VADC_GLOBAL_BackgroundTriggerConversion(VADC); - - // Wait until conversion is ready - while (((value = XMC_VADC_GLOBAL_GetDetailedResult(VADC)) & VADC_GLOBRES_VF_Msk) == 0u) - ; -#endif - value = ((value & VADC_GLOBRES_RESULT_Msk) >> (ADC_MAX_READ_RESOLUTION - _readResolution)); - } - return value; -} - -/* analogRead_variableGain takes parameter of ADC channel number and gain value - return 0xFFFFFFFF for invalid channel - - gain value gain factor - 0 1 - 1 3 - 2 6 - 3 12 - Also, refer to macros in wiring_analog.h -*/ - -uint32_t analogRead_variableGain(uint8_t channel, uint8_t gain_value) { -#if (XMC_VADC_SHS_AVAILABLE == 1U) - uint32_t value; - - value = 0xFFFFFFFF; - if (channel < NUM_ANALOG_INPUTS) { - XMC_ADC_t *adc = &mapping_adc[channel]; - - #if (XMC_VADC_GROUP_AVAILABLE == 1U) - // ADC grouping - if (!(adc->enabled)) { - XMC_VADC_CHANNEL_CONFIG_t vadc_gobal_channel_config; - memset(&vadc_gobal_channel_config, 0, sizeof(XMC_VADC_CHANNEL_CONFIG_t)); - vadc_gobal_channel_config.input_class = XMC_VADC_CHANNEL_CONV_GROUP_CLASS1; - vadc_gobal_channel_config.result_reg_number = adc->result_reg_num; - vadc_gobal_channel_config.alias_channel = XMC_VADC_CHANNEL_ALIAS_DISABLED; - - XMC_VADC_RESULT_CONFIG_t vadc_gobal_result_config = {.g_rcr = 0}; - /* Configure a channel belonging to the aforesaid conversion kernel */ - XMC_VADC_GROUP_ChannelInit(adc->group, adc->channel_num, &vadc_gobal_channel_config); - /* Configure a result resource belonging to the aforesaid conversion kernel */ - XMC_VADC_GROUP_ResultInit(adc->group, adc->result_reg_num, &vadc_gobal_result_config); - /* Add channel into the Background Request Source Channel Select Register */ - XMC_VADC_GLOBAL_BackgroundAddChannelToSequence(VADC, (uint32_t)adc->group_num, - (uint32_t)adc->channel_num); - /* Set the gain factor of the Sample and hold module*/ - XMC_VADC_GLOBAL_SHS_SetGainFactor(SHS0, gain_value, (uint32_t)adc->group_num, - (uint32_t)adc->channel_num); - } - /* Start conversion manually using load event trigger*/ - XMC_VADC_GLOBAL_BackgroundTriggerConversion(VADC); - value = XMC_VADC_GROUP_GetResult(adc->group, adc->result_reg_num); - #else - // XMC1100 no ADC grouping - if (!(adc->enabled)) - /* Add a channel to the background source. */ - VADC->BRSSEL[ADC_CONVERSION_GROUP] = (uint32_t)(1U << adc->channel_num); - /* Set the gain factor of the Sample and hold module */ - XMC_VADC_GLOBAL_SHS_SetGainFactor(SHS0, gain_value, XMC_VADC_GROUP_INDEX_0, - (uint32_t)adc->channel_num); - // Generates conversion request - XMC_VADC_GLOBAL_BackgroundTriggerConversion(VADC); - - // Wait until conversion is ready - while (((value = XMC_VADC_GLOBAL_GetDetailedResult(VADC)) & VADC_GLOBRES_VF_Msk) == 0u) - ; - #endif - value = ((value & VADC_GLOBRES_RESULT_Msk) >> (ADC_MAX_READ_RESOLUTION - _readResolution)); - return value; - } -#endif -} - -/* Helper function for analogWrite and setAnalogWriteFrequency to scan - mapping tables to determine for a given pin which PWM4, PWM8 or DAC - channel to use - Returns valid channel index or -1 for not listed - reading first column as 255 denotes end of table - See pins_arduino.h for table layout -*/ -int16_t scan_map_table(const uint8_t table[][2], uint8_t pin) { - int16_t i; - - i = 0; - while (table[i][0] != 255) { - if (table[i][0] == pin) - break; - i++; - } - if (table[i][0] != 255) - return table[i][1]; - return -1; -} - -/* Writes an analogue value to a DAC or PWM wave to a pin. - DAC is straight write to DAC (if present on that pin) - - PWM depends on analogWriteResolution() - Effect of value is the duty cycle for PWM output to be HIGH - Valid values are - Write resolution (bits) - Value 8 10 12 16 - OFF 0 0 0 0 - ON always 255 1023 4095 65535 - - Values in between these values vary the duty cycle - - Returns 0 = success - -1 = invalid value - -2 = wrong pin -*/ -int16_t analogWrite(uint8_t pin, uint16_t value) { - uint32_t compare_reg = 0; - int16_t resource; - - if (value > _writeMaximum) - return -1; - - if ((resource = scan_map_table(mapping_pin_PWM4, pin)) >= 0) { - XMC_PWM4_t *pwm4 = &mapping_pwm4[resource]; - - if (!(pwm4->enabled)) { - // Slice not yet initialized - XMC_CCU4_SLICE_COMPARE_CONFIG_t pwm_config; - memset(&pwm_config, 0, sizeof(XMC_CCU4_SLICE_COMPARE_CONFIG_t)); - pwm_config.passive_level = XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL_HIGH; - pwm_config.prescaler_initval = pwm4->prescaler; - - XMC_CCU4_Init(pwm4->ccu, XMC_CCU4_SLICE_MCMS_ACTION_TRANSFER_PR_CR); - XMC_CCU4_SLICE_CompareInit(pwm4->slice, &pwm_config); - XMC_CCU4_EnableClock(pwm4->ccu, pwm4->slice_num); - XMC_CCU4_SLICE_SetTimerPeriodMatch(pwm4->slice, pwm4->period_timer_val); - - pwm4->enabled = ENABLED; - } - - if (value != 0) - compare_reg = ((value + 1) * (pwm4->period_timer_val + 1)) >> _writeResolution; - - XMC_CCU4_SLICE_SetTimerCompareMatch(pwm4->slice, compare_reg); - XMC_CCU4_EnableShadowTransfer(pwm4->ccu, (CCU4_GCSS_S0SE_Msk << (4 * pwm4->slice_num))); - XMC_GPIO_SetMode(pwm4->port_pin.port, pwm4->port_pin.pin, - (XMC_GPIO_MODE_OUTPUT_PUSH_PULL | pwm4->port_mode)); - XMC_CCU4_SLICE_StartTimer(pwm4->slice); - } -#if defined(CCU8V2) || defined(CCU8V1) - else if ((resource = scan_map_table(mapping_pin_PWM8, pin)) >= 0) { - XMC_PWM8_t *pwm8 = &mapping_pwm8[resource]; - - if (!(pwm8->enabled)) { - // Slice not yet initialized - XMC_CCU8_SLICE_COMPARE_CONFIG_t pwm_config; - memset(&pwm_config, 0, sizeof(XMC_CCU8_SLICE_COMPARE_CONFIG_t)); - pwm_config.passive_level_out0 = XMC_CCU8_SLICE_OUTPUT_PASSIVE_LEVEL_HIGH; - pwm_config.passive_level_out1 = XMC_CCU8_SLICE_OUTPUT_PASSIVE_LEVEL_HIGH; - pwm_config.passive_level_out2 = XMC_CCU8_SLICE_OUTPUT_PASSIVE_LEVEL_HIGH; - pwm_config.passive_level_out3 = XMC_CCU8_SLICE_OUTPUT_PASSIVE_LEVEL_HIGH; - pwm_config.prescaler_initval = pwm8->prescaler; - - XMC_CCU8_Init(pwm8->ccu, XMC_CCU8_SLICE_MCMS_ACTION_TRANSFER_PR_CR); - XMC_CCU8_SLICE_CompareInit(pwm8->slice, &pwm_config); - XMC_CCU8_EnableClock(pwm8->ccu, pwm8->slice_num); - XMC_CCU8_SLICE_SetTimerPeriodMatch(pwm8->slice, pwm8->period_timer_val); - pwm8->enabled = ENABLED; - } - - if (value != 0) - compare_reg = ((value + 1) * (pwm8->period_timer_val + 1)) >> _writeResolution; - - XMC_CCU8_SLICE_SetTimerCompareMatch(pwm8->slice, pwm8->slice_channel, compare_reg); - XMC_CCU8_EnableShadowTransfer(pwm8->ccu, CCU8_GCSS_S0SE_Msk << (4 * pwm8->slice_num)); - XMC_GPIO_SetMode(pwm8->port_pin.port, pwm8->port_pin.pin, - XMC_GPIO_MODE_OUTPUT_PUSH_PULL | pwm8->port_mode); - XMC_CCU8_SLICE_StartTimer(pwm8->slice); - } -#endif -#ifdef DAC - else if ((resource = scan_map_table(mapping_pin_DAC, pin)) >= 0) { - XMC_ARD_DAC_t *dac = &(mapping_dac[resource]); - XMC_DAC_Enable(dac->group); - XMC_DAC_CH_EnableOutput(dac->group, dac->channel); - XMC_DAC_CH_StartSingleValueMode(dac->group, dac->channel); - uint16_t dacValue = - map(value, 0, (0b10 << _writeResolution) - 1, 0, (0b10 << dac->resolution) - 1); - XMC_DAC_CH_Write(dac->group, dac->channel, dacValue); - } -#endif - else - return -2; - return 0; -} - -/* Sets the frequency for analogWrite PWM. - - Parameters pin - frequency in Hz - - Returns -2 invalid pin - -1 invalid frequency - 0 Success -*/ -int16_t setAnalogWriteFrequency(uint8_t pin, uint32_t frequency) { - int16_t ret = -1; - uint16_t prescaler = 0U; - int16_t resource; - uint16_t period; - - if (frequency < PCLK) { - do { - if (frequency > (PCLK / ((1U << prescaler) * 65536U))) - break; - prescaler++; - } while (prescaler < 15); // Prescaler must never be > 15 - - // Calculate 16 bit timer end value - period = (PCLK / ((1U << prescaler) * frequency)) - 1; - - if ((resource = scan_map_table(mapping_pin_PWM4, pin)) >= 0) { - XMC_PWM4_t *pwm4 = &mapping_pwm4[resource]; - - pwm4->prescaler = prescaler; - pwm4->period_timer_val = period; - if (pwm4->enabled == ENABLED) { - // Disable pwm output - pwm4->enabled = DISABLED; - XMC_CCU4_SLICE_StartTimer(pwm4->slice); - } - ret = 0; - } -#if defined(CCU8V2) || defined(CCU8V1) - else if ((resource = scan_map_table(mapping_pin_PWM8, pin)) >= 0) { - XMC_PWM8_t *pwm8 = &mapping_pwm8[resource]; - - pwm8->prescaler = prescaler; - pwm8->period_timer_val = period; - if (pwm8->enabled == ENABLED) { - // Disable pwm output - pwm8->enabled = DISABLED; - XMC_CCU8_SLICE_StartTimer(pwm8->slice); - } - ret = 0; - } -#endif - if (ret == -1) // Catch pin not found - ret = -2; - } - return ret; -} - -/* PC Sept-2019 - Add helper functions to get Read and Write resolution as bits or maximum value -*/ -/* Get the current resolution of analogRead in number of bits. - Return Current resolution in bits (8 to 12) - */ -uint8_t getAnalogReadBits() { return _readResolution; } - -/* Get the current resolution of analogWrite in number of bits. - Return Current resolution in bits (8 to 16) - */ -uint8_t getAnalogWriteBits() { return _writeResolution; } - -/* Get the maximum value for current resolution for analogRead. - Default is 1023 - Maximum is 4095 - */ -uint16_t getAnalogReadMaximum() { return _readMaximum; } - -/* Get the maximum value for current resolution for analogWrite. - Default is 255 - Maximum is 65535 - */ -uint16_t getAnalogWriteMaximum() { return _writeMaximum; } - -//**************************************************************************** -// END OF FILE -//**************************************************************************** diff --git a/cores/wiring_analog.h b/cores/wiring_analog.h deleted file mode 100644 index cb1098f3..00000000 --- a/cores/wiring_analog.h +++ /dev/null @@ -1,175 +0,0 @@ -/* - Copyright (c) 2011 Arduino. All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - - Copyright (c) 2018 Infineon Technologies AG - This file has been modified for the XMC microcontroller series. -*/ - -#ifndef _WIRING_ANALOG_ -#define _WIRING_ANALOG_ - -#ifdef __cplusplus -extern "C" { -#endif - -/********************************************************************************************************************* - * MACROS - ********************************************************************************************************************/ -// ADC gain macros -#define ADC_VAR_GAIN_FACTOR_1 0 -#define ADC_VAR_GAIN_FACTOR_3 1 -#define ADC_VAR_GAIN_FACTOR_6 2 -#define ADC_VAR_GAIN_FACTOR_12 3 - -//**************************************************************************** -// @External Prototypes -//**************************************************************************** - -/* - * \brief Configures the reference voltage used for analog input (i.e. the value used as the top of - * the input range). This function is kept only for compatibility with existing AVR based API. - * - * \param ulMmode Should be set to DEFAULT. - * - */ -extern void analogReference(uint8_t ulMode); - -/* - * \brief Writes an analogue value to a DAC or PWM wave to a pin. - * DAC is straight write to DAC (if present on that pin) - * - * PWM depends on analogWriteResolution() - * Effect of value is the duty cycle for PWM output to be HIGH - * Valid values are - * Write resolution (bits) - * Value 8 10 12 16 - * OFF 0 0 0 0 - * ON always 255 1023 4095 65535 - * - * Values in between these values vary the duty cycle - * - * \param pin - * \param value must be 0 to max value for ADC WRITE resolution - * - * \return 0 = success, -1 = invalid value, -2 = wrong pin - */ -extern int16_t analogWrite(uint8_t pin, uint16_t value); - -/* - * \brief Sets the frequency for analogWrite PWM. - * - * Returns -2 invalid pin - * -1 invalid frequency - * 0 success - * - * \note Default value is 490 Hz - * - * \param pin - * \param frequency in Hz - * - * \return 0 = success, -1 = invalid frequency, -2 = wrong pin - */ -extern int16_t setAnalogWriteFrequency(uint8_t pin, uint32_t frequency); - -/* - * \brief Reads the value from the specified analogue channel. - * - * \param channel - * - * \return Read value from selected channel, or 0xFFFFFFFF for error. - */ -extern uint32_t analogRead(uint8_t channel); - -/* - * \brief Reads the value from the specified analogue channel and add variable gain at input. - * - * \param channel - * \param gain_factor - * - * gain value gain factor - * 0 1 - * 1 3 - * 2 6 - * 3 12 - * - * \return Read value from selected channel, or 0xFFFFFFFF for error. - */ -extern uint32_t analogRead_variableGain(uint8_t channel, uint8_t gain_value); - -/* - * \brief Set the resolution of analogRead return values in number of bits. - * \note Default is 10 bits (range from 0 to 1023). - * - * \param res - range 8 to 12 - * - * \return valid bits set (8 to 12) or 255 for error - */ -extern uint8_t analogReadResolution(uint8_t res); - -/* - * \brief Set the resolution of analogWrite parameters in number of bits. - * \note Default (minimum) is 8 bits (range from 0 to 16). - * Maximum is 16 bits (range 0 to 65535) - * - * \param res - range 8 to 16 - * - * \return valid bits set (8 to 16) or 255 for error - */ -extern uint8_t analogWriteResolution(uint8_t res); - -extern void wiring_analog_init(); - -/********************************************************* - \brief Additional helper functions for other libraries -**********************************************************/ -/* - * \brief Get the current resolution of analogRead in number of bits. - * - * \return Current resolution in bits (8 to 12) - */ -extern uint8_t getAnalogReadBits(); - -/* - * \brief Get the current resolution of analogWrite in number of bits. - * - * \return Current resolution in bits (8 to 16) - */ -extern uint8_t getAnalogWriteBits(); - -/* - * \brief Get the maximum value for current resolution for analogRead. - * \note Default is 1023 - * \note Maximum is 4095 - * - * \return Current maximum value - */ -extern uint16_t getAnalogReadMaximum(); - -/* - * \brief Get the maximum value for current resolution for analogWrite. - * \note Default is 255 - * \note Maximum is 65535 - * - * \return Current maximum value - */ -extern uint16_t getAnalogWriteMaximum(); - -#ifdef __cplusplus -} -#endif - -#endif /* _WIRING_ANALOG_ */ diff --git a/cores/wiring_constants.h b/cores/wiring_constants.h deleted file mode 100644 index 3dd0c7fe..00000000 --- a/cores/wiring_constants.h +++ /dev/null @@ -1,109 +0,0 @@ -/* - Copyright (c) 2011 Arduino. All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - - Copyright (c) 2018 Infineon Technologies AG - This file has been modified for the XMC microcontroller series. -*/ - -#ifndef _WIRING_CONSTANTS_ -#define _WIRING_CONSTANTS_ - -#ifdef __cplusplus -extern "C" { -#endif // __cplusplus - -//**************************************************************************** -// @Defines -//**************************************************************************** -/* Arduino wiring macros and bit defines */ -#define HIGH 1 -#define LOW 0 -#define ENABLED 1 -#define DISABLED 0 -#define INPUT XMC_GPIO_MODE_INPUT_TRISTATE -#define OUTPUT XMC_GPIO_MODE_OUTPUT_PUSH_PULL -#define INPUT_PULLUP XMC_GPIO_MODE_INPUT_PULL_UP -#define INPUT_PULLDOWN XMC_GPIO_MODE_INPUT_PULL_DOWN -#define OUTPUT_OPENDRAIN XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN - -#define PI 3.1415926535897932384626433832795 -#define HALF_PI 1.5707963267948966192313216916398 -#define TWO_PI 6.283185307179586476925286766559 -#define DEG_TO_RAD 0.017453292519943295769236907684886 -#define RAD_TO_DEG 57.295779513082320876798154814105 -#define EULER 2.718281828459045235360287471352 - -#define SERIAL 0x0 -#define DISPLAY 0x1 - -enum BitOrder { LSBFIRST = 0, MSBFIRST = 1 }; - -#define DEFAULT 0 -#define EXTERNAL 1 -#define INTERNAL 2 - -#define NOT_A_PIN -1 -#define NOT_A_PORT -1 -#define NOT_AN_INTERRUPT -1 - -// undefine stdlib's abs if encountered -#ifdef abs - #undef abs -#endif // abs - -#ifndef min - #define min(a, b) ((a) < (b) ? (a) : (b)) -#endif // min - -#ifndef max - #define max(a, b) ((a) > (b) ? (a) : (b)) -#endif // max - -#define abs(x) ((x) > 0 ? (x) : -(x)) -#define constrain(amt, low, high) ((amt) < (low) ? (low) : ((amt) > (high) ? (high) : (amt))) -#define round(x) ((x) >= 0 ? (long)((x) + 0.5) : (long)((x) - 0.5)) -#define radians(deg) ((deg) * DEG_TO_RAD) -#define degrees(rad) ((rad) * RAD_TO_DEG) -#define sq(x) ((x) * (x)) - -#define map(x, in_min, in_max, out_min, out_max) \ - (((x - in_min) * (out_max - out_min)) / (in_max - in_min) + out_min) - -#define interrupts() __enable_irq() -#define noInterrupts() __disable_irq() - -#define lowByte(w) ((uint8_t)((w) & 0xff)) -#define highByte(w) ((uint8_t)((w) >> 8)) - -#define bitRead(value, bit) (((value) >> (bit)) & 0x01) -#define bitSet(value, bit) ((value) |= (1UL << (bit))) -#define bitClear(value, bit) ((value) &= ~(1UL << (bit))) -#define bitWrite(value, bit, bitvalue) (bitvalue ? bitSet(value, bit) : bitClear(value, bit)) -#define bit(b) (1UL << (b)) - -//**************************************************************************** -// @Typedefs -//**************************************************************************** -typedef bool boolean; -typedef uint8_t byte; -typedef uint8_t word; - -#ifdef __cplusplus -} // extern "C" -#endif // __cplusplus - -#endif /* _WIRING_CONSTANTS_ */ diff --git a/cores/wiring_digital.c b/cores/wiring_digital.c deleted file mode 100644 index abd07d53..00000000 --- a/cores/wiring_digital.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - Copyright (c) 2011 Arduino. All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - - Copyright (c) 2018 Infineon Technologies AG - This file has been modified for the XMC microcontroller series. - */ - -//**************************************************************************** -// @Project Includes -//**************************************************************************** -#include "Arduino.h" - -void pinMode(uint8_t pin, uint8_t mode) { - XMC_GPIO_CONFIG_t gpio_conf; - gpio_conf.mode = mode; - gpio_conf.output_level = XMC_GPIO_OUTPUT_LEVEL_LOW; -#if UC_FAMILY == XMC1 - gpio_conf.input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_LARGE; -#endif - XMC_GPIO_Init(mapping_port_pin[pin].port, mapping_port_pin[pin].pin, &gpio_conf); -} - -uint8_t digitalRead(uint8_t pin) { - return ((pin == GND) - ? LOW - : XMC_GPIO_GetInput(mapping_port_pin[pin].port, mapping_port_pin[pin].pin)); -} - -void digitalWrite(uint8_t pin, uint8_t value) { - XMC_GPIO_SetOutputLevel(mapping_port_pin[pin].port, mapping_port_pin[pin].pin, - (value == LOW) ? XMC_GPIO_OUTPUT_LEVEL_LOW - : XMC_GPIO_OUTPUT_LEVEL_HIGH); -} - -void digitalToggle(uint8_t pin) { - XMC_GPIO_ToggleOutput(mapping_port_pin[pin].port, mapping_port_pin[pin].pin); -} - -//**************************************************************************** -// END OF FILE -//**************************************************************************** diff --git a/cores/wiring_digital.h b/cores/wiring_digital.h deleted file mode 100644 index 8c6dc5b8..00000000 --- a/cores/wiring_digital.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - Copyright (c) 2011 Arduino. All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - - Copyright (c) 2018 Infineon Technologies AG - This file has been modified for the XMC microcontroller series. -*/ - -#ifndef _WIRING_DIGITAL_ -#define _WIRING_DIGITAL_ - -#ifdef __cplusplus -extern "C" { -#endif - -//**************************************************************************** -// @External Prototypes -//**************************************************************************** - -/* - * \brief Configures the specified pin to behave either as an input or an output. See the - * description of digital pins for details. - * - * \param pin The number of the pin whose mode you wish to set - * \param mode Either INPUT, INPUT_PULLUP, INPUT_PULLDOWN or OUTPUT - */ -void pinMode(uint8_t pin, uint8_t mode); - -/* - * \brief Reads the value from a specified digital pin, either HIGH or LOW. - * - * \param pin The number of the digital pin you want to read (int) - * - * \return HIGH or LOW - */ -extern uint8_t digitalRead(uint8_t pin); - -/* - * \brief Write a HIGH or a LOW value to a digital pin. - * - * If the pin has been configured as an OUTPUT with pinMode(), its voltage will be set to the - * corresponding value: 5V (or 3.3V on 3.3V boards) for HIGH, 0V (ground) for LOW. - * - * If the pin is configured as an INPUT, writing a HIGH value with digitalWrite() will enable an - * internal 20K pullup resistor (see the tutorial on digital pins). Writing LOW will disable the - * pullup. The pullup resistor is enough to light an LED dimly, so if LEDs appear to work, but very - * dimly, this is a likely cause. The remedy is to set the pin to an output with the pinMode() - * function. - * - * \note Digital pin PIN_LED is harder to use as a digital input than the other digital pins because - * it has an LED and resistor attached to it that's soldered to the board on most boards. If you - * enable its internal 20k pull-up resistor, it will hang at around 1.7 V instead of the expected 5V - * because the onboard LED and series resistor pull the voltage level down, meaning it always - * returns LOW. If you must use pin PIN_LED as a digital input, use an external pull down resistor. - * - * \param pin the pin number - * \param value HIGH or LOW - */ -extern void digitalWrite(uint8_t pin, uint8_t value); - -/* - * \brief Toggles output signal of a digital pin. - * - * \param pin The number of the pin who you want to toggle - */ -extern void digitalToggle(uint8_t pin); - -#ifdef __cplusplus -} -#endif - -#endif /* _WIRING_DIGITAL_ */ \ No newline at end of file diff --git a/cores/wiring_pulse.h b/cores/wiring_pulse.h deleted file mode 100644 index 3d8d1e11..00000000 --- a/cores/wiring_pulse.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - Copyright (c) 2011 Arduino. All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#ifndef _WIRING_PULSE_ -#define _WIRING_PULSE_ - -#ifdef __cplusplus -extern "C" { -#endif - -//**************************************************************************** -// @External Prototypes -//**************************************************************************** - -/* - * \brief Measures the length (in microseconds) of a pulse on the pin; state is HIGH - * or LOW, the type of pulse to measure. Works on pulses from 2-3 microseconds - * to 3 minutes in length, but must be called at least a few dozen microseconds - * before the start of the pulse. - */ -uint32_t pulseIn(uint32_t pin, uint32_t state, uint32_t timeout); - -#ifdef __cplusplus -// Provides a version of pulseIn with a default argument (C++ only) -uint32_t pulseIn(uint32_t pin, uint32_t state, uint32_t timeout = 1000000L); - -} // extern "C" -#endif - -#endif /* _WIRING_PULSE_ */ diff --git a/cores/wiring_shift.c b/cores/wiring_shift.c deleted file mode 100644 index a721775a..00000000 --- a/cores/wiring_shift.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - Copyright (c) 2011 Arduino. All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -//**************************************************************************** -// @Project Includes -//**************************************************************************** -#include "Arduino.h" - -//**************************************************************************** -// @Local Functions -//**************************************************************************** - -void shiftOut(uint32_t ulDataPin, uint32_t ulClockPin, uint32_t ulBitOrder, uint32_t ulVal) { - uint8_t i; - - for (i = 0; i < 8; i++) { - if (ulBitOrder == LSBFIRST) { - digitalWrite(ulDataPin, !!(ulVal & (1 << i))); - } else { - digitalWrite(ulDataPin, !!(ulVal & (1 << (7 - i)))); - } - - digitalWrite(ulClockPin, HIGH); - digitalWrite(ulClockPin, LOW); - } -} - -uint32_t shiftIn(uint32_t ulDataPin, uint32_t ulClockPin, uint32_t ulBitOrder) { - uint8_t value = 0; - uint8_t i; - - for (i = 0; i < 8; ++i) { - digitalWrite(ulClockPin, HIGH); - - if (ulBitOrder == LSBFIRST) { - value |= digitalRead(ulDataPin) << i; - } else { - value |= digitalRead(ulDataPin) << (7 - i); - } - - digitalWrite(ulClockPin, LOW); - } - - return value; -} - -//**************************************************************************** -// END OF FILE -//**************************************************************************** diff --git a/cores/wiring_shift.h b/cores/wiring_shift.h deleted file mode 100644 index 1e449985..00000000 --- a/cores/wiring_shift.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - Copyright (c) 2011 Arduino. All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#ifndef WIRING_SHIFT_H_ -#define WIRING_SHIFT_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -//**************************************************************************** -// @External Prototypes -//**************************************************************************** - -/* - * \brief - */ -extern uint32_t shiftIn(uint32_t ulDataPin, uint32_t ulClockPin, uint32_t ulBitOrder); - -/* - * \brief - */ -extern void shiftOut(uint32_t ulDataPin, uint32_t ulClockPin, uint32_t ulBitOrder, uint32_t ulVal); - -#ifdef __cplusplus -} -#endif - -#endif /* WIRING_SHIFT_H_ */ diff --git a/cores/Arduino.h b/cores/xmc/Arduino.h similarity index 84% rename from cores/Arduino.h rename to cores/xmc/Arduino.h index 87c1ad4c..431f325c 100644 --- a/cores/Arduino.h +++ b/cores/xmc/Arduino.h @@ -1,5 +1,6 @@ /* - Copyright (c) 2011 Arduino. All right reserved. + Arduino.h - Main include file for the Arduino SDK + Copyright (c) 2005-2013 Arduino Team. All right reserved. This library is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General Public @@ -8,8 +9,8 @@ This library is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. You should have received a copy of the GNU Lesser General Public License along with this library; if not, write to the Free Software @@ -21,7 +22,12 @@ #ifndef _ARDUINO_H_ #define _ARDUINO_H_ +#include "api/ArduinoAPI.h" +#include "api/deprecated-avr-comp/avr/pgmspace.h" +#include "api/deprecated-avr-comp/avr/dtostrf.h" + #ifdef __cplusplus +using namespace arduino; extern "C" { #endif @@ -34,7 +40,6 @@ extern "C" { #include #include #include -#include //**************************************************************************** // @XMC Lib Includes @@ -66,6 +71,13 @@ extern "C" { // used by XMC_I2S #define BUFFER_SIZE 512 +#define interrupts() __enable_irq() +#define noInterrupts() __disable_irq() +#define ENABLED 1 +#define DISABLED 0 + +#define DEFAULT XMC_VADC_CHANNEL_REF_INTREF /*< Default ADC reference voltage type */ + //**************************************************************************** // @Typedefs //**************************************************************************** @@ -124,10 +136,11 @@ typedef struct { XMC_GPIO_MODE_t port_mode; XMC_CCU4_SLICE_PRESCALER_t prescaler; uint32_t period_timer_val; + int d_cycle_val; bool enabled; } XMC_PWM4_t; -#if defined(CCU8V2) || defined(CCU8V3) || defined(CCU8V1) +#if defined(CCU8V3) || defined(CCU8V2) || defined(CCU8V1) /* * XMC PWM type (CCU8) */ @@ -140,6 +153,7 @@ typedef struct { XMC_GPIO_MODE_t port_mode; XMC_CCU8_SLICE_PRESCALER_t prescaler; uint32_t period_timer_val; + int d_cycle_val; bool enabled; } XMC_PWM8_t; #endif @@ -269,6 +283,7 @@ extern const XMC_PIN_INTERRUPT_t mapping_interrupt[]; extern const uint8_t mapping_pin_PWM4[][2]; extern XMC_PWM4_t mapping_pwm4[]; extern XMC_ADC_t mapping_adc[]; +extern bool gpio_current_value[]; #if defined(CCU8V2) || defined(CCU8V3) || defined(CCU8V1) extern const uint8_t mapping_pin_PWM8[][2]; extern XMC_PWM8_t mapping_pwm8[]; @@ -281,12 +296,12 @@ extern XMC_UART_t XMC_UART_debug; extern XMC_UART_t XMC_UART_on_board; extern XMC_SPI_t XMC_SPI_0; -// Some boards for eg. XMC4700 Relax Kit has more than one SPI instance +// Some boards eg. KIT_XMC47_RELAX has more than one SPI instance extern XMC_SPI_t XMC_SPI_1; extern XMC_SPI_t XMC_SPI_2; extern XMC_I2C_t XMC_I2C_0; -// Some boards for eg. XMC4700 Relax Kit has more than one I2C instance +// Some boards eg. KIT_XMC47_RELAX has more than one I2C instance extern XMC_I2C_t XMC_I2C_1; extern XMC_I2S_t i2s_config; @@ -313,34 +328,54 @@ extern void setup(void); */ extern void loop(void); +/* + * \brief Set the resolution of analogRead return values. Default is 10 bits (range from 0 to 1023). + * + * \param res + */ +extern void analogReadResolution(int res); + +/* + * \brief Set the resolution of analogWrite parameters. Default is 8 bits (range from 0 to 255). + * + * \param res + */ +extern void analogWriteResolution(int res); + +/* + * \brief Sets the frequency for analogWrite PWM. + * \note Default value is 490 Hz + * + * \param pin + * \param frequency in Hz + * + * \return 0 = success, -1 = invalid frequency, -2 = wrong pin + */ +extern int16_t setAnalogWriteFrequency(pin_size_t pin, uint32_t frequency); //**************************************************************************** // @Arduino Core Includes //**************************************************************************** -#include "wiring_constants.h" -#include "binary.h" -#include "wiring_digital.h" -#include "wiring_analog.h" -#include "wiring_shift.h" #include "wiring_time.h" + +/*#include "wiring_shift.h" #include "wiring_pulse.h" -#include "itoa.h" -#include "dtostrf.h" -#include "WCharacter.h" -#include "WInterrupts.h" +#include "WInterrupts.h" +*/ //**************************************************************************** // @Infineon Core Includes //**************************************************************************** + #include "reset.h" #ifdef __cplusplus } // extern "C" #include "Tone.h" - #include "WMath.h" + // #include "WMath.h" + #include "Uart.h" #endif // __cplusplus -#include "Print.h" -#include "HardwareSerial.h" +// #include "Print.h" //**************************************************************************** // @Board Variant Includes diff --git a/cores/wiring_pulse.c b/cores/xmc/Pulse.cpp similarity index 67% rename from cores/wiring_pulse.c rename to cores/xmc/Pulse.cpp index 0201da2b..d11427df 100644 --- a/cores/wiring_pulse.c +++ b/cores/xmc/Pulse.cpp @@ -1,24 +1,3 @@ -/* - Copyright (c) 2011 Arduino. All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -//**************************************************************************** -// @Project Includes -//**************************************************************************** #include "Arduino.h" // Ensure we do not wait here forever by setting maximum and default @@ -62,7 +41,7 @@ uint32_t end_time; // start time of measured pulse * Use of SysTick hardware timer and micros( ) function makes the function * more portable across various micros and CPU clock frequencies. * - * Assumptions] + * Assumptions: * As per AVR Arduino PulseIn pin is expected to be in input mode already * No major interrupt activity while measurement is taken (including Serial) * @@ -70,11 +49,12 @@ uint32_t end_time; // start time of measured pulse * to any operations. * To improve accuracy beyond this will probably need hard coded assembler */ -uint32_t pulseIn(uint32_t pin, uint32_t state, uint32_t timeout) { +unsigned long pulseIn(pin_size_t pin, uint8_t state, unsigned long timeout) { // check pin is valid by NUM_DIGITAL_PINS, return 0 if invalid #ifdef NUM_DIGITAL_PINS - if (pin >= NUM_DIGITAL_PINS) + if (pin >= NUM_DIGITAL_PINS) { return 0; + } #endif // Set up pin details for faster port read in loops @@ -84,11 +64,11 @@ uint32_t pulseIn(uint32_t pin, uint32_t state, uint32_t timeout) { // Check timeout is NOT too small or > Maximum // if so use default 1 second or MAX respectively - if (timeout < 6) + if (timeout < 6) { timeout = DEF_PULSE_TIMEOUT; - else if (timeout > MAX_PULSE_TIMEOUT) + } else if (timeout > MAX_PULSE_TIMEOUT) { timeout = MAX_PULSE_TIMEOUT; - + } // Initialise conditions pulse_state = (state) ? mask : 0; // level to measure @@ -96,26 +76,31 @@ uint32_t pulseIn(uint32_t pin, uint32_t state, uint32_t timeout) { // If already at measurement level we have a problem // So wait for pulse to go to OPPOSITE level required (idle) first - while (((pulsePort->IN & mask) == pulse_state)) - if (micros() > timeout) + while (((pulsePort->IN & mask) == pulse_state)) { + if (micros() > timeout) { return 0; - + } + } // Wait for pulse to go to level required - while (((pulsePort->IN & mask) != pulse_state)) - if (micros() > timeout) + while (((pulsePort->IN & mask) != pulse_state)) { + if (micros() > timeout) { return 0; + } + } // measure pulse length of required level start_time = micros(); - while (((pulsePort->IN & mask) == pulse_state)) - if (micros() > timeout) + while (((pulsePort->IN & mask) == pulse_state)) { + if (micros() > timeout) { return 0; + } + } end_time = micros(); // Return time difference return (end_time - start_time); } -//**************************************************************************** -// END OF FILE -//**************************************************************************** \ No newline at end of file +unsigned long pulseInLong(pin_size_t pin, uint8_t state, unsigned long timeout) { + return pulseIn(pin, state, timeout); +} diff --git a/cores/xmc/Shift.cpp b/cores/xmc/Shift.cpp new file mode 100644 index 00000000..d9966c6f --- /dev/null +++ b/cores/xmc/Shift.cpp @@ -0,0 +1,35 @@ +#include "Arduino.h" + +void shiftOut(pin_size_t ulDataPin, pin_size_t ulClockPin, BitOrder ulBitOrder, uint8_t ulVal) { + uint8_t i; + + for (i = 0; i < 8; i++) { + if (ulBitOrder == LSBFIRST) { + digitalWrite(ulDataPin, !!(ulVal & (1 << i))); + } else { + digitalWrite(ulDataPin, !!(ulVal & (1 << (7 - i)))); + } + + digitalWrite(ulClockPin, HIGH); + digitalWrite(ulClockPin, LOW); + } +} + +uint8_t shiftIn(pin_size_t ulDataPin, pin_size_t ulClockPin, BitOrder ulBitOrder) { + uint8_t value = 0; + uint8_t i; + + for (i = 0; i < 8; ++i) { + digitalWrite(ulClockPin, HIGH); + + if (ulBitOrder == LSBFIRST) { + value |= digitalRead(ulDataPin) << i; + } else { + value |= digitalRead(ulDataPin) << (7 - i); + } + + digitalWrite(ulClockPin, LOW); + } + + return value; +} diff --git a/cores/Tone.cpp b/cores/xmc/Tone.cpp similarity index 71% rename from cores/Tone.cpp rename to cores/xmc/Tone.cpp index 8df48269..c157b7bc 100644 --- a/cores/Tone.cpp +++ b/cores/xmc/Tone.cpp @@ -1,26 +1,3 @@ -/* - Copyright (c) 2011 Arduino. All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ -/* Tones are Systick timer event related not hardware timer related - So take care in selecting frequencies range of 1 - 500 Hz supported */ - -//**************************************************************************** -// @Project Includes -//**************************************************************************** #include "Arduino.h" //**************************************************************************** @@ -48,6 +25,10 @@ uint8_t tone_init = 0; // @Local Functions //**************************************************************************** +void digitalToggle(uint8_t pin) { + XMC_GPIO_ToggleOutput(mapping_port_pin[pin].port, mapping_port_pin[pin].pin); +} + static int8_t toneBegin(uint8_t _pin) { int8_t i; @@ -61,18 +42,20 @@ static int8_t toneBegin(uint8_t _pin) { // Once initialised // if we're already using the pin, the timer should be configured. - for (i = 0; i < NUM_TONE_PINS; i++) - if (tone_pins[i] == _pin) + for (i = 0; i < NUM_TONE_PINS; i++) { + if (tone_pins[i] == _pin) { return i; + } + } // search for an unused timer. - for (i = 0; i < NUM_TONE_PINS; i++) + for (i = 0; i < NUM_TONE_PINS; i++) { if (tone_pins[i] == 255) { tone_pins[i] = _pin; pinMode(_pin, OUTPUT); break; } - + } return (i < NUM_TONE_PINS) ? i : -1; } @@ -83,17 +66,17 @@ static int8_t toneBegin(uint8_t _pin) { // Timer task ID is tone pin index _timer void tone(uint8_t _pin, unsigned int frequency, unsigned long duration) { int8_t _timer; - // Check valid frequency range first if (frequency > 0 && frequency <= 500) { _timer = toneBegin(_pin); if (_timer >= 0 && _timer < NUM_TONE_PINS) { // Calculate the toggle count - if (duration > 0) + if (duration > 0) { timer_toggle_count[_timer] = 2 * frequency * duration / 1000; - else + } else { timer_toggle_count[_timer] = -1; // Continuous + } // Set internal task parameters setParam(_timer, _timer); setInterval(_timer, (unsigned int)FREQUENCY_TO_MILLIS(frequency)); @@ -105,13 +88,6 @@ void tone(uint8_t _pin, unsigned int frequency, unsigned long duration) { // Stops tone at next 1ms Systick void noTone(uint8_t _pin) { int8_t i; - - for (i = 0; i < NUM_TONE_PINS; i++) - if (tone_pins[i] == _pin) { - tone_pins[i] = 255; - break; - } - if (i < NUM_TONE_PINS) // Only if found set to stop at max next Systick event { noInterrupts(); // Interrupt disable guard to be safe @@ -128,8 +104,9 @@ void noTone(uint8_t _pin) { int tone_irq_action(int ID, int16_t tone) { if (timer_toggle_count[tone]) { digitalToggle(tone_pins[tone]); - if (timer_toggle_count[tone] > 0) + if (timer_toggle_count[tone] > 0) { timer_toggle_count[tone]--; + } } else { setInterval(ID, 0); // no longer wanted to run digitalWrite(tone_pins[tone], LOW); @@ -140,4 +117,4 @@ int tone_irq_action(int ID, int16_t tone) { //**************************************************************************** // END OF FILE -//**************************************************************************** +//**************************************************************************** \ No newline at end of file diff --git a/cores/xmc/Tone.h b/cores/xmc/Tone.h new file mode 100644 index 00000000..fda48732 --- /dev/null +++ b/cores/xmc/Tone.h @@ -0,0 +1,16 @@ +#ifndef _WIRING_TONE_ +#define _WIRING_TONE_ + +//**************************************************************************** +// @External Prototypes +//**************************************************************************** +void digitalToggle(uint8_t pin); +#ifdef __cplusplus +extern "C" { +#endif +extern int tone_irq_action(int, int16_t); +#ifdef __cplusplus +} +#endif + +#endif /* _WIRING_TONE_ */ \ No newline at end of file diff --git a/cores/xmc/Uart.cpp b/cores/xmc/Uart.cpp new file mode 100644 index 00000000..bda4aa40 --- /dev/null +++ b/cores/xmc/Uart.cpp @@ -0,0 +1,145 @@ + +#include "Uart.h" +#include "Arduino.h" + +// Constructors //////////////////////////////////////////////////////////////// + +Uart::Uart(XMC_UART_t *xmc_uart_config) { _XMC_UART_config = xmc_uart_config; } + +// Public Methods ////////////////////////////////////////////////////////////// + +void Uart::begin(unsigned long baud) { begin(baud, SERIAL_8N1); } + +void Uart::begin(unsigned long baud, unsigned short config) { + begin(baud, static_cast(config)); +} + +void Uart::begin(unsigned long baud, XMC_UART_MODE_t config) { + XMC_UART_CH_CONFIG_t uart_ch_config; + uart_ch_config.oversampling = 0; // Must be 0 or valid oversample for baud rate calculations + uart_ch_config.baudrate = baud; + uart_ch_config.data_bits = (uint8_t)(config & 0x00fU); + uart_ch_config.frame_length = uart_ch_config.data_bits; // Set same as data bits length + uart_ch_config.parity_mode = (XMC_USIC_CH_PARITY_MODE_t)(config & ~0xffU); + uart_ch_config.stop_bits = (uint8_t)((config & 0x0f0U) >> 4); + + XMC_UART_CH_Init(_XMC_UART_config->channel, &uart_ch_config); + + // dx0 is UART RX: source must be set + XMC_USIC_CH_SetInputSource(_XMC_UART_config->channel, XMC_USIC_CH_INPUT_DX0, + _XMC_UART_config->input_source_dx0); + + // Additional input multiplexing + // Check if dx1 is used + if (_XMC_UART_config->input_source_dx1 != XMC_INPUT_INVALID) + XMC_USIC_CH_SetInputSource(_XMC_UART_config->channel, XMC_USIC_CH_INPUT_DX1, + _XMC_UART_config->input_source_dx1); + + // Check if dx2 is used + if (_XMC_UART_config->input_source_dx2 != XMC_INPUT_INVALID) + XMC_USIC_CH_SetInputSource(_XMC_UART_config->channel, XMC_USIC_CH_INPUT_DX2, + _XMC_UART_config->input_source_dx2); + + // Check if dx3 is used + if (_XMC_UART_config->input_source_dx3 != XMC_INPUT_INVALID) + XMC_USIC_CH_SetInputSource(_XMC_UART_config->channel, XMC_USIC_CH_INPUT_DX3, + _XMC_UART_config->input_source_dx3); + + XMC_UART_CH_EnableEvent(_XMC_UART_config->channel, XMC_UART_CH_EVENT_ALTERNATIVE_RECEIVE | + XMC_UART_CH_EVENT_STANDARD_RECEIVE); + XMC_USIC_CH_SetInterruptNodePointer(_XMC_UART_config->channel, + XMC_USIC_CH_INTERRUPT_NODE_POINTER_RECEIVE, + _XMC_UART_config->irq_service_request); + XMC_USIC_CH_SetInterruptNodePointer(_XMC_UART_config->channel, + XMC_USIC_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE, + _XMC_UART_config->irq_service_request); + XMC_USIC_CH_SetInterruptNodePointer(_XMC_UART_config->channel, + XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER, + _XMC_UART_config->irq_service_request); + NVIC_SetPriority(_XMC_UART_config->irq_num, 3); + NVIC_EnableIRQ(_XMC_UART_config->irq_num); + + XMC_UART_CH_Start(_XMC_UART_config->channel); + + // TX pin setup put here to avoid startup corrupted characters being first sent + XMC_GPIO_Init(_XMC_UART_config->tx.port, _XMC_UART_config->tx.pin, + &(_XMC_UART_config->tx_config)); + + XMC_GPIO_Init(_XMC_UART_config->rx.port, _XMC_UART_config->rx.pin, + &(_XMC_UART_config->rx_config)); + serial_ready = true; +} + +void Uart::end(void) { + // Wait for any outstanding data to be sent + flush(); + // Disable UART interrupt in NVIC + NVIC_DisableIRQ(_XMC_UART_config->irq_num); + // Clear any received data after stopping interrupts + _rx_buffer.clear(); + serial_ready = false; +} + +void Uart::setInterruptPriority(uint32_t priority) { + NVIC_SetPriority(_XMC_UART_config->irq_num, priority & 0x03); +} + +uint32_t Uart::getInterruptPriority() { return NVIC_GetPriority(_XMC_UART_config->irq_num); } + +int Uart::available(void) { return _rx_buffer.available(); } + +int Uart::availableForWrite(void) { + return 1; +} // TODO: there are no tx buffer so we awaly have 1 byte available + +int Uart::peek(void) { return _rx_buffer.peek(); } + +int Uart::read(void) { return _rx_buffer.read_char(); } + +void Uart::flush(void) { + while (XMC_USIC_CH_GetTransmitBufferStatus(_XMC_UART_config->channel) == + XMC_USIC_CH_TBUF_STATUS_BUSY) { + }; +} + +size_t Uart::write(const uint8_t uc_data) { + // For sending, write immediately + // This API already have a check for available buffer + XMC_UART_CH_Transmit(_XMC_UART_config->channel, uc_data); + return 1; +} + +size_t Uart::write(const uint8_t *buffer, size_t size) { + // Check if the length is valid + if ((size == 0) || (buffer == nullptr)) { + return 0; + } + // For sending, write immediately + for (size_t i = 0; i < size; i++) { + XMC_UART_CH_Transmit(_XMC_UART_config->channel, buffer[i]); + } + return size; +} + +Uart::operator bool() { return serial_ready; } + +void Uart::IrqHandler(void) { + // Receive data Interrupt handler + uint32_t status = XMC_UART_CH_GetStatusFlag(_XMC_UART_config->channel); + + // Did we receive data? + if ((status & (XMC_UART_CH_STATUS_FLAG_ALTERNATIVE_RECEIVE_INDICATION | + XMC_UART_CH_STATUS_FLAG_RECEIVE_INDICATION)) != 0U) { + XMC_UART_CH_ClearStatusFlag(_XMC_UART_config->channel, + (XMC_UART_CH_STATUS_FLAG_ALTERNATIVE_RECEIVE_INDICATION | + XMC_UART_CH_STATUS_FLAG_RECEIVE_INDICATION)); + + while (_XMC_UART_config->channel->RBUFSR & + (USIC_CH_RBUFSR_RDV0_Msk | USIC_CH_RBUFSR_RDV1_Msk)) + _rx_buffer.store_char(XMC_UART_CH_GetReceivedData(_XMC_UART_config->channel)); + } +} + +//**************************************************************************** +// END OF FILE +//**************************************************************************** \ No newline at end of file diff --git a/cores/HardwareSerial.h b/cores/xmc/Uart.h similarity index 52% rename from cores/HardwareSerial.h rename to cores/xmc/Uart.h index ccb6f92a..fb8702e1 100644 --- a/cores/HardwareSerial.h +++ b/cores/xmc/Uart.h @@ -1,38 +1,44 @@ -/* - Copyright (c) 2011 Arduino. All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#ifndef HardwareSerial_h -#define HardwareSerial_h - +#pragma once //**************************************************************************** // @External Prototypes //**************************************************************************** -#ifdef __cplusplus - //**************************************************************************** - // @Project Includes - //**************************************************************************** - #include "RingBuffer.h" - #include "Stream.h" +#include "Arduino.h" +//**************************************************************************** +// @Project Includes +//**************************************************************************** +#include "api/HardwareSerial.h" +#include "api/RingBuffer.h" //**************************************************************************** // @Typedefs //**************************************************************************** +// Define config for Serial.begin(baud, config); +#undef SERIAL_5N1 +#undef SERIAL_6N1 +#undef SERIAL_7N1 +#undef SERIAL_8N1 +#undef SERIAL_5N2 +#undef SERIAL_6N2 +#undef SERIAL_7N2 +#undef SERIAL_8N2 +#undef SERIAL_5E1 +#undef SERIAL_6E1 +#undef SERIAL_7E1 +#undef SERIAL_8E1 +#undef SERIAL_5E2 +#undef SERIAL_6E2 +#undef SERIAL_7E2 +#undef SERIAL_8E2 +#undef SERIAL_5O1 +#undef SERIAL_6O1 +#undef SERIAL_7O1 +#undef SERIAL_8O1 +#undef SERIAL_5O2 +#undef SERIAL_6O2 +#undef SERIAL_7O2 +#undef SERIAL_8O2 + typedef enum XMC_UART_MODE { SERIAL_5N1 = 0x15 | XMC_USIC_CH_PARITY_MODE_NONE, SERIAL_6N1 = 0x16 | XMC_USIC_CH_PARITY_MODE_NONE, @@ -61,40 +67,27 @@ typedef enum XMC_UART_MODE { } XMC_UART_MODE_t; //**************************************************************************** -// @Class Definitions +// @Class Definitionsw //**************************************************************************** -class HardwareSerial : public Stream { +class Uart : public HardwareSerial { public: XMC_UART_t *_XMC_UART_config; - - HardwareSerial(XMC_UART_t *xmc_uart_config, RingBuffer *rx_buffer, RingBuffer *tx_buffer); - - void begin(uint32_t speed); - void begin(uint32_t speed, XMC_UART_MODE_t config); - void end(void); + Uart(XMC_UART_t *xmc_uart_config); + void begin(unsigned long); + void begin(unsigned long baudrate, uint16_t config) override; + void begin(unsigned long, XMC_UART_MODE_t config); + void end(); int available(void); int availableForWrite(void); int peek(void); - void flush(void); int read(void); - - // virtual size_t readBytes(char *buffer, size_t length) ; // read chars from stream into buffer - // virtual size_t readBytes(uint8_t *buffer, size_t length) ; + void flush(void); size_t write(const uint8_t); - - // virtual size_t write(const uint8_t *buffer, size_t size) ; - inline size_t write(unsigned long n) { return write((uint8_t)n); } - - inline size_t write(long n) { return write((uint8_t)n); } - - inline size_t write(unsigned int n) { return write((uint8_t)n); } - - inline size_t write(int n) { return write((uint8_t)n); } - + size_t write(const uint8_t *buffer, size_t size); using Print::write; // pull in write(str) and write(buf, size) from Print - operator bool() { return true; } + operator bool(); void setInterruptPriority(uint32_t priority); uint32_t getInterruptPriority(); @@ -102,9 +95,10 @@ class HardwareSerial : public Stream { void IrqHandler(void); private: - RingBuffer *_rx_buffer; - RingBuffer *_tx_buffer; + static constexpr size_t BUF_LENGTH = 512; + RingBufferN _rx_buffer; + bool serial_ready = false; }; -#endif /* cplusplus */ -#endif /* HardwareSerial_h */ +extern Uart Serial; +extern Uart Serial1; diff --git a/cores/xmc/WInterrupts.c b/cores/xmc/WInterrupts.c new file mode 100644 index 00000000..a81831fd --- /dev/null +++ b/cores/xmc/WInterrupts.c @@ -0,0 +1,204 @@ +//**************************************************************************** +// @Project Includes +//**************************************************************************** +#include "Arduino.h" +#ifdef __cplusplus +extern "C" { +#endif +//**************************************************************************** +// @Prototypes Of Local Functions +//**************************************************************************** +static voidFuncPtr interrupt_0_cb = NULL; +static voidFuncPtr interrupt_1_cb = NULL; + +//**************************************************************************** +// @Local Functions +//**************************************************************************** +#if defined(INTERRUPT_USE_ERU) +void ERU0_3_IRQHandler(void) { + if (interrupt_0_cb) { + interrupt_0_cb(); + } +} + +void ERU1_0_IRQHandler(void) { + if (interrupt_1_cb) { + interrupt_1_cb(); + } +} + +#else +void CCU40_0_IRQHandler(void) { + if (interrupt_0_cb) { + interrupt_0_cb(); + } +} + +void CCU40_1_IRQHandler(void) { + if (interrupt_1_cb) { + interrupt_1_cb(); + } +} +#endif + +void attachInterrupt(pin_size_t interrupt_num, voidFuncPtr callback, PinStatus mode) { + if (interrupt_num >= NUM_INTERRUPT) { + return; + } + if (mode != CHANGE && mode != RISING && mode != FALLING) { + switch (interrupt_num) { + case 0: + NVIC_DisableIRQ(CCU40_0_IRQn); + interrupt_0_cb = NULL; + break; + + case 1: + NVIC_DisableIRQ(CCU40_1_IRQn); + interrupt_1_cb = NULL; + break; + default: + break; + } + return; + } + XMC_PIN_INTERRUPT_t pin_irq = mapping_interrupt[interrupt_num]; +#if defined(INTERRUPT_USE_ERU) + XMC_ERU_ETL_EDGE_DETECTION_t event_config = 0; + + switch (mode) { + case CHANGE: + event_config = XMC_ERU_ETL_EDGE_DETECTION_BOTH; + break; + + case RISING: + event_config = XMC_ERU_ETL_EDGE_DETECTION_RISING; + break; + + case FALLING: + event_config = XMC_ERU_ETL_EDGE_DETECTION_FALLING; + break; + + default: + event_config = XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_NONE; + break; + } + + XMC_ERU_Enable(pin_irq.eru); + XMC_ERU_ETL_SetInput(pin_irq.eru, pin_irq.etl, pin_irq.input_a, pin_irq.input_b); + XMC_ERU_ETL_SetEdgeDetection(pin_irq.eru, pin_irq.etl, event_config); + XMC_ERU_ETL_SetSource(pin_irq.eru, pin_irq.etl, XMC_ERU_ETL_SOURCE_B); + XMC_ERU_ETL_EnableOutputTrigger(pin_irq.eru, pin_irq.etl, pin_irq.ogu); + XMC_ERU_OGU_SetServiceRequestMode(pin_irq.eru, pin_irq.ogu, + XMC_ERU_OGU_SERVICE_REQUEST_ON_TRIGGER); + + if (pin_irq.irq_num == 0) { + NVIC_SetPriority(ERU0_3_IRQn, 3); + interrupt_0_cb = callback; + NVIC_EnableIRQ(ERU0_3_IRQn); + } else if (pin_irq.irq_num == 1) { + NVIC_SetPriority(ERU1_0_IRQn, 3); + interrupt_1_cb = callback; + NVIC_EnableIRQ(ERU1_0_IRQn); + } +#else + XMC_CCU4_SLICE_EVENT_CONFIG_t event_config = {0}; + + switch (mode) { + case CHANGE: + event_config.edge = XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_DUAL_EDGE; + break; + + case RISING: + event_config.edge = XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_RISING_EDGE; + break; + + case FALLING: + event_config.edge = XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_FALLING_EDGE; + break; + + default: + event_config.edge = XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_NONE; + break; + } + + XMC_CCU4_Init(pin_irq.ccu, XMC_CCU4_SLICE_MCMS_ACTION_TRANSFER_PR_CR); + XMC_CCU4_EnableClock(pin_irq.ccu, pin_irq.slice_num); + + if (pin_irq.irq_num == 0) { + #if defined(KIT_XMC14_2GO) + /* P1_4 external interrupt goes through USIC to CCU4 */ + XMC_USIC_CH_Enable(XMC_USIC0_CH1); + XMC_USIC_CH_SetInputSource(XMC_USIC0_CH1, XMC_USIC_CH_INPUT_DX5, USIC0_C0_DX5_P1_4); + XMC_USIC_CH_SetInputSource(XMC_USIC0_CH1, XMC_USIC_CH_INPUT_DX2, USIC0_C0_DX2_DX5INS); + #endif + #if defined(KIT_XMC11_BOOT_001) || defined(KIT_XMC1400_ARDUINO) + XMC_USIC_CH_Enable(XMC_USIC0_CH0); + XMC_USIC_CH_SetInputSource(XMC_USIC0_CH0, XMC_USIC_CH_INPUT_DX5, USIC0_C0_DX5_P1_4); + XMC_USIC_CH_SetInputSource(XMC_USIC0_CH0, XMC_USIC_CH_INPUT_DX2, USIC0_C0_DX2_DX5INS); + #endif + XMC_CCU4_SLICE_EnableMultipleEvents(pin_irq.slice, XMC_CCU4_SLICE_MULTI_IRQ_ID_EVENT0); + XMC_CCU4_SLICE_SetInterruptNode(pin_irq.slice, XMC_CCU4_SLICE_IRQ_ID_EVENT0, 0); + NVIC_SetPriority(CCU40_0_IRQn, 3); + + event_config.mapped_input = pin_irq.input; + XMC_CCU4_SLICE_ConfigureEvent(pin_irq.slice, XMC_CCU4_SLICE_EVENT_0, &event_config); + + interrupt_0_cb = callback; + NVIC_EnableIRQ(CCU40_0_IRQn); + } else if (pin_irq.irq_num == 1) { + #if defined(KIT_XMC13_BOOT_001) || defined(KIT_XMC1400_ARDUINO) + /* P0_13 external interrupt goes through USIC to CCU4 */ + XMC_USIC_CH_Enable(XMC_USIC0_CH0); + XMC_USIC_CH_SetInputSource(XMC_USIC0_CH0, XMC_USIC_CH_INPUT_DX2, USIC0_C0_DX2_P0_13); + #endif + XMC_CCU4_SLICE_EnableMultipleEvents(pin_irq.slice, XMC_CCU4_SLICE_MULTI_IRQ_ID_EVENT1); + XMC_CCU4_SLICE_SetInterruptNode(pin_irq.slice, XMC_CCU4_SLICE_IRQ_ID_EVENT1, 1); + NVIC_SetPriority(CCU40_1_IRQn, 3); + + event_config.mapped_input = pin_irq.input; + XMC_CCU4_SLICE_ConfigureEvent(pin_irq.slice, XMC_CCU4_SLICE_EVENT_1, &event_config); + + interrupt_1_cb = callback; + NVIC_EnableIRQ(CCU40_1_IRQn); + } +#endif +} + +void detachInterrupt(pin_size_t interrupt_num) { + + if (interrupt_num >= NUM_INTERRUPT) { + return; + } +#if defined(INTERRUPT_USE_ERU) + XMC_PIN_INTERRUPT_t pin_irq = mapping_interrupt[interrupt_num]; + switch (pin_irq.irq_num) { + case 0: + NVIC_DisableIRQ(ERU0_3_IRQn); + break; + + case 1: + NVIC_DisableIRQ(ERU1_0_IRQn); + break; + default: + break; + } +#else + switch (interrupt_num) { + case 0: + NVIC_DisableIRQ(CCU40_0_IRQn); + break; + + case 1: + NVIC_DisableIRQ(CCU40_1_IRQn); + break; + default: + break; + } +#endif +} +#ifdef __cplusplus +} +#endif +//**************************************************************************** +// END OF FILE +//**************************************************************************** \ No newline at end of file diff --git a/cores/WMath.cpp b/cores/xmc/WMath.cpp similarity index 91% rename from cores/WMath.cpp rename to cores/xmc/WMath.cpp index b6128522..b71bc28f 100644 --- a/cores/WMath.cpp +++ b/cores/xmc/WMath.cpp @@ -24,8 +24,6 @@ extern "C" { #include "stdint.h" } -#include "WMath.h" - //**************************************************************************** // @Local Functions //**************************************************************************** @@ -54,10 +52,6 @@ long random(long howsmall, long howbig) { return random(diff) + howsmall; } -extern uint16_t makeWord(uint16_t w) { return w; } - -uint16_t makeWord(uint8_t h, uint8_t l) { return (h << 8) | l; } - //**************************************************************************** // END OF FILE -//**************************************************************************** +//**************************************************************************** \ No newline at end of file diff --git a/cores/Main.cpp b/cores/xmc/main.cpp similarity index 83% rename from cores/Main.cpp rename to cores/xmc/main.cpp index 39865cf9..144aee4f 100644 --- a/cores/Main.cpp +++ b/cores/xmc/main.cpp @@ -32,14 +32,20 @@ void dummy_sbrk_caller() __attribute__((__used__)); void dummy_sbrk_caller() { _sbrk(0); } +// Weak empty variant initialization function. +// May be redefined by variant files. +void initVariant() __attribute__((weak)); + +void initVariant() {} + int main(void) { /* * Initialization Time first to get closer to startup time accuracy */ wiring_time_init(); - wiring_analog_init(); -// Initialize the reset pin for the XMC1100 Boot Kit series and XMC1400 Kit for Arduino as they are -// based on Arduino form-factor Hence, a dedicated reset pin is required. + +// Initialize the reset pin for the KIT_XMC11_BOOT_001 series and KIT_XMC1400_ARDUINO as they are +// based on Arduino Uno form-factor. Hence a dedicated reset pin is required. #ifdef HAS_GPIO_RESET reset_init(); #endif @@ -48,7 +54,7 @@ int main(void) { setup(); while (1) { loop(); - serialEventRun(); + ::serialEventRun(); } } diff --git a/cores/reset.c b/cores/xmc/reset.c similarity index 99% rename from cores/reset.c rename to cores/xmc/reset.c index 4539fc17..52c9b393 100644 --- a/cores/reset.c +++ b/cores/xmc/reset.c @@ -67,4 +67,4 @@ void reset_init(void) { NVIC_SetPriority(ERU0_0_IRQn, 3U); NVIC_EnableIRQ(ERU0_0_IRQn); } -#endif +#endif \ No newline at end of file diff --git a/cores/reset.h b/cores/xmc/reset.h similarity index 99% rename from cores/reset.h rename to cores/xmc/reset.h index 030f7f25..286524b8 100644 --- a/cores/reset.h +++ b/cores/xmc/reset.h @@ -41,4 +41,4 @@ */ extern void reset_init(void); -#endif +#endif \ No newline at end of file diff --git a/cores/xmc/wiring_analog.cpp b/cores/xmc/wiring_analog.cpp new file mode 100644 index 00000000..31023745 --- /dev/null +++ b/cores/xmc/wiring_analog.cpp @@ -0,0 +1,364 @@ +//**************************************************************************** +// @File: wiring_analog.cpp +// @Brief: Analog and PWM/DAC API implementation for XMC Arduino core +//**************************************************************************** +#include "Arduino.h" + +//**************************************************************************** +// @Defines +//**************************************************************************** +#define ADC_CONVERSION_GROUP 0 +#define ADC_MIN_RESOLUTION 8 +#define ADC_MAX_READ_RESOLUTION 12 +#define ANALOG_MAX_WRITE_RESOLUTION 16 + +//**************************************************************************** +// @Global Variables +//**************************************************************************** +static XMC_VADC_CHANNEL_REF_t analog_reference = DEFAULT; +static uint8_t _readResolution = 10; +static uint8_t _writeResolution = 8; +uint16_t _readMaximum = 1023; +uint16_t _writeMaximum = 255; +static bool vadc_inited = false; + +//**************************************************************************** +// @Function: scan_map_table +// @Brief: Lookup table for pin to resource mapping +//**************************************************************************** +int16_t scan_map_table(const uint8_t table[][2], uint8_t pin) { + int16_t i = 0; + while (table[i][0] != 255) { + if (table[i][0] == pin) + break; + i++; + } + if (table[i][0] != 255) + return table[i][1]; + return -1; +} + +//**************************************************************************** +// @Function: analogReference +// @Brief: Sets the ADC reference voltage type. Only default (Varef = Vdda) is available. +//**************************************************************************** +void analogReference(uint8_t mode) { + switch (mode) { + case DEFAULT: + analog_reference = XMC_VADC_CHANNEL_REF_INTREF; + break; + default: + // Invalid mode, do nothing + break; + } +} + +//**************************************************************************** +// @Function: analogWriteResolution +// @Brief: Sets the resolution for analogWrite (PWM/DAC) +//**************************************************************************** +void analogWriteResolution(int res) { + if (res > ANALOG_MAX_WRITE_RESOLUTION) { + _writeResolution = ANALOG_MAX_WRITE_RESOLUTION; + } else if (res < ADC_MIN_RESOLUTION) { + _writeResolution = ADC_MIN_RESOLUTION; + } else { + _writeResolution = res; + } + _writeMaximum = (uint16_t)(((uint32_t)1U << _writeResolution) - 1); +} + +//**************************************************************************** +// @Function: analogWrite +// @Brief: Outputs PWM or DAC value to the specified pin +//**************************************************************************** +void analogWrite(pin_size_t pinNumber, int value) { + uint32_t compare_reg = 0; + int16_t resource; + if (value < 0 || value > _writeMaximum) + return; + // Check if the pin supports PWM4 + resource = scan_map_table(mapping_pin_PWM4, pinNumber); + if (resource >= 0) { + XMC_PWM4_t *pwm4 = &mapping_pwm4[resource]; + if (!(pwm4->enabled)) { + // Slice not yet initialized + XMC_CCU4_SLICE_COMPARE_CONFIG_t pwm_config; + memset(&pwm_config, 0, sizeof(XMC_CCU4_SLICE_COMPARE_CONFIG_t)); + pwm_config.passive_level = XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL_HIGH; + pwm_config.prescaler_initval = pwm4->prescaler; + XMC_CCU4_Init(pwm4->ccu, XMC_CCU4_SLICE_MCMS_ACTION_TRANSFER_PR_CR); + XMC_CCU4_SLICE_CompareInit(pwm4->slice, &pwm_config); + XMC_CCU4_EnableClock(pwm4->ccu, pwm4->slice_num); + XMC_CCU4_SLICE_SetTimerPeriodMatch(pwm4->slice, pwm4->period_timer_val); + pwm4->enabled = true; + } + if (value != 0) + compare_reg = ((value + 1) * (pwm4->period_timer_val + 1)) >> _writeResolution; + XMC_CCU4_SLICE_SetTimerCompareMatch(pwm4->slice, compare_reg); + XMC_CCU4_EnableShadowTransfer(pwm4->ccu, (CCU4_GCSS_S0SE_Msk << (4 * pwm4->slice_num))); + XMC_GPIO_SetMode(pwm4->port_pin.port, pwm4->port_pin.pin, + (XMC_GPIO_MODE_t)(XMC_GPIO_MODE_OUTPUT_PUSH_PULL | pwm4->port_mode)); + XMC_CCU4_SLICE_StartTimer(pwm4->slice); + pwm4->d_cycle_val = value; + return; + } +#if defined(CCU8V3) || defined(CCU8V2) || defined(CCU8V1) + // Check if the pin supports PWM8 + else if ((resource = scan_map_table(mapping_pin_PWM8, pinNumber)) >= 0) { + XMC_PWM8_t *pwm8 = &mapping_pwm8[resource]; + if (!(pwm8->enabled)) { + // Slice not yet initialized + XMC_CCU8_SLICE_COMPARE_CONFIG_t pwm_config; + memset(&pwm_config, 0, sizeof(XMC_CCU8_SLICE_COMPARE_CONFIG_t)); + pwm_config.passive_level_out0 = XMC_CCU8_SLICE_OUTPUT_PASSIVE_LEVEL_HIGH; + pwm_config.passive_level_out1 = XMC_CCU8_SLICE_OUTPUT_PASSIVE_LEVEL_HIGH; + pwm_config.passive_level_out2 = XMC_CCU8_SLICE_OUTPUT_PASSIVE_LEVEL_HIGH; + pwm_config.passive_level_out3 = XMC_CCU8_SLICE_OUTPUT_PASSIVE_LEVEL_HIGH; + pwm_config.prescaler_initval = pwm8->prescaler; + XMC_CCU8_Init(pwm8->ccu, XMC_CCU8_SLICE_MCMS_ACTION_TRANSFER_PR_CR); + XMC_CCU8_SLICE_CompareInit(pwm8->slice, &pwm_config); + XMC_CCU8_EnableClock(pwm8->ccu, pwm8->slice_num); + XMC_CCU8_SLICE_SetTimerPeriodMatch(pwm8->slice, pwm8->period_timer_val); + pwm8->enabled = true; + } + if (value != 0) + compare_reg = ((value + 1) * (pwm8->period_timer_val + 1)) >> _writeResolution; + XMC_CCU8_SLICE_SetTimerCompareMatch(pwm8->slice, pwm8->slice_channel, compare_reg); + XMC_CCU8_EnableShadowTransfer(pwm8->ccu, CCU8_GCSS_S0SE_Msk << (4 * pwm8->slice_num)); + XMC_GPIO_SetMode(pwm8->port_pin.port, pwm8->port_pin.pin, + (XMC_GPIO_MODE_t)(XMC_GPIO_MODE_OUTPUT_PUSH_PULL | pwm8->port_mode)); + XMC_CCU8_SLICE_StartTimer(pwm8->slice); + pwm8->d_cycle_val = value; + return; + } +#endif +#ifdef DAC + // Check if the pin supports DAC + else if ((resource = scan_map_table(mapping_pin_DAC, pinNumber)) >= 0) { + XMC_ARD_DAC_t *dac = &(mapping_dac[resource]); + XMC_DAC_Enable(dac->group); + XMC_DAC_CH_EnableOutput(dac->group, dac->channel); + XMC_DAC_CH_StartSingleValueMode(dac->group, dac->channel); + uint16_t dacValue = + map(value, 0, (0b10 << _writeResolution) - 1, 0, (0b10 << dac->resolution) - 1); + XMC_DAC_CH_Write(dac->group, dac->channel, dacValue); + return; + } +#endif + // If not found, do nothing + return; +} + +//**************************************************************************** +// @Function: wiring_analog_init +// @Brief: Initializes VADC and related analog resources (runs only once) +//**************************************************************************** +void wiring_analog_init(void) { + if (vadc_inited) + return; + vadc_inited = true; + /* Initialization data of VADC Global resources */ + XMC_VADC_GLOBAL_CONFIG_t vadc_global_config; + memset(&vadc_global_config, 0, sizeof(XMC_VADC_GLOBAL_CONFIG_t)); + vadc_global_config.class0.conversion_mode_standard = XMC_VADC_CONVMODE_12BIT; + vadc_global_config.class1.conversion_mode_standard = XMC_VADC_CONVMODE_12BIT; + + XMC_VADC_BACKGROUND_CONFIG_t vadc_background_config = {0}; + + /* Provide clock to VADC and initialize the VADC global registers. */ + XMC_VADC_GLOBAL_Init(VADC, &vadc_global_config); + +#if (XMC_VADC_GROUP_AVAILABLE == 1U) + // ADC grouping + XMC_VADC_GROUP_CONFIG_t vadc_group_config; + memset(&vadc_group_config, 0, sizeof(XMC_VADC_GROUP_CONFIG_t)); + vadc_group_config.class0.conversion_mode_standard = XMC_VADC_CONVMODE_12BIT; + vadc_group_config.class1.conversion_mode_standard = XMC_VADC_CONVMODE_12BIT; + + /* Initialize Group */ + XMC_VADC_GROUP_Init(VADC_G0, &vadc_group_config); + XMC_VADC_GROUP_Init(VADC_G1, &vadc_group_config); + + /* Switch on the converter of the Group*/ + XMC_VADC_GROUP_SetPowerMode(VADC_G0, XMC_VADC_GROUP_POWERMODE_NORMAL); + XMC_VADC_GROUP_SetPowerMode(VADC_G1, XMC_VADC_GROUP_POWERMODE_NORMAL); + + #if (XMC_VADC_MAXIMUM_NUM_GROUPS > 2) + /* Initialize Group */ + XMC_VADC_GROUP_Init(VADC_G2, &vadc_group_config); + XMC_VADC_GROUP_Init(VADC_G3, &vadc_group_config); + + /* Switch on the converter of the Group*/ + XMC_VADC_GROUP_SetPowerMode(VADC_G2, XMC_VADC_GROUP_POWERMODE_NORMAL); + XMC_VADC_GROUP_SetPowerMode(VADC_G3, XMC_VADC_GROUP_POWERMODE_NORMAL); + #endif + +#endif + /* Calibrate the VADC. Make sure you do this after all used VADC groups + are set to normal operation mode. */ + XMC_VADC_GLOBAL_StartupCalibration(VADC); + + /* Initialize the background source hardware. The gating mode is set to + ignore to pass external triggers unconditionally.*/ + XMC_VADC_GLOBAL_BackgroundInit(VADC, &vadc_background_config); + + /* Dummy read of ALL analogue inputs to ensure ALL analogue channels are + started in background scanning mode, otherwise first readings at least + will always be zero on reading an analogue input. */ + for (uint8_t chan = 0; chan < NUM_ANALOG_INPUTS; chan++) + analogRead(chan); + + // Additional Initialization of DAC starting here +} + +//**************************************************************************** +// @Function: analogReadResolution +// @Brief: Sets the resolution for analogRead (ADC) +//**************************************************************************** +void analogReadResolution(int res) { + if (res > ADC_MAX_READ_RESOLUTION) { + _readResolution = ADC_MAX_READ_RESOLUTION; + } else if (res < ADC_MIN_RESOLUTION) { + _readResolution = ADC_MIN_RESOLUTION; + } else { + _readResolution = res; + } + _readMaximum = (uint16_t)(((uint32_t)1U << _readResolution) - 1); +} + +//**************************************************************************** +// @Function: analogRead +// @Brief: Reads the analog value from the specified pin +//**************************************************************************** +int analogRead(pin_size_t pinNumber) { + + wiring_analog_init(); + uint32_t value; + + value = 0xFFFFFFFF; + if (pinNumber < NUM_ANALOG_INPUTS) { + XMC_ADC_t *adc = &mapping_adc[pinNumber]; + +#if (XMC_VADC_GROUP_AVAILABLE == 1U) + // ADC grouping + if (!(adc->enabled)) { + XMC_VADC_CHANNEL_CONFIG_t vadc_gobal_channel_config; + memset(&vadc_gobal_channel_config, 0, sizeof(XMC_VADC_CHANNEL_CONFIG_t)); + vadc_gobal_channel_config.input_class = XMC_VADC_CHANNEL_CONV_GROUP_CLASS1; + vadc_gobal_channel_config.result_reg_number = adc->result_reg_num; + vadc_gobal_channel_config.alias_channel = XMC_VADC_CHANNEL_ALIAS_DISABLED; + + XMC_VADC_RESULT_CONFIG_t vadc_gobal_result_config = {.g_rcr = 0}; + /* Configure a channel belonging to the aforesaid conversion kernel */ + XMC_VADC_GROUP_ChannelInit(adc->group, adc->channel_num, &vadc_gobal_channel_config); + /* Configure a result resource belonging to the aforesaid conversion kernel */ + XMC_VADC_GROUP_ResultInit(adc->group, adc->result_reg_num, &vadc_gobal_result_config); + /* Add channel into the Background Request Source Channel Select Register */ + XMC_VADC_GLOBAL_BackgroundAddChannelToSequence(VADC, (uint32_t)adc->group_num, + (uint32_t)adc->channel_num); + } + /* Start conversion manually using load event trigger*/ + XMC_VADC_GLOBAL_BackgroundTriggerConversion(VADC); + value = XMC_VADC_GROUP_GetResult(adc->group, adc->result_reg_num); +#else + // XMC1100 no ADC grouping + if (!(adc->enabled)) + /* Add a channel to the background source. */ + VADC->BRSSEL[ADC_CONVERSION_GROUP] = (uint32_t)(1U << adc->channel_num); + // Generates conversion request + XMC_VADC_GLOBAL_BackgroundTriggerConversion(VADC); + + // Wait until conversion is ready + while (((value = XMC_VADC_GLOBAL_GetDetailedResult(VADC)) & VADC_GLOBRES_VF_Msk) == 0u) + ; +#endif + value = ((value & VADC_GLOBRES_RESULT_Msk) >> (ADC_MAX_READ_RESOLUTION - _readResolution)); + } + return value; +} + +//**************************************************************************** +// @Function: setAnalogWriteFrequency +// @Brief: Sets the frequency for analogWrite PWM. +// @Param: pin - The pin number +// @Param: frequency - Frequency in Hz +// @Return: -2 if invalid pin, -1 if invalid frequency, 0 on success +//**************************************************************************** +int16_t setAnalogWriteFrequency(pin_size_t pin, uint32_t frequency) { + // Constants for return codes + constexpr int16_t SUCCESS = 0; + constexpr int16_t ERROR_INVALID_FREQUENCY = -1; + constexpr int16_t ERROR_NO_PWM_RESOURCE = -2; + constexpr uint32_t MAX_16BIT_TIMER_COUNT = 65536U; + + // Variables for computation + uint16_t prescaler = 0U; + uint16_t period; + int16_t resource; + + // Check if frequency is within a valid range + if (frequency == 0 || frequency >= PCLK) { + return ERROR_INVALID_FREQUENCY; // Frequency too high, cannot configure + } + + // Calculate prescaler value + while (prescaler <= + XMC_CCU4_SLICE_PRESCALER_32768) { // As same as XMC_CCU8_SLICE_PRESCALER_32768 + if (frequency > (PCLK / ((1U << prescaler) * MAX_16BIT_TIMER_COUNT))) { + break; + } + prescaler++; + } + + // Calculate timer period + period = (PCLK / ((1U << prescaler) * frequency)) - 1; + + // Attempt to configure PWM4 + resource = scan_map_table(mapping_pin_PWM4, pin); + if (resource >= 0) { + XMC_PWM4_t *pwm4 = &mapping_pwm4[resource]; + + pwm4->prescaler = static_cast(prescaler); + pwm4->period_timer_val = period; + + // If PWM is already enabled, disable and restart it + if (pwm4->enabled) { + // Disable to reset the compare value + pwm4->enabled = false; + XMC_CCU4_SLICE_StopClearTimer(pwm4->slice); + // Reconfigure and restart PWM + analogWrite(pin, pwm4->d_cycle_val); // Use the saved duty cycle value + } + + return SUCCESS; // Configuration successful + } + +#if defined(CCU8V2) || defined(CCU8V1) + // Attempt to configure PWM8 + resource = scan_map_table(mapping_pin_PWM8, pin); + if (resource >= 0) { + XMC_PWM8_t *pwm8 = &mapping_pwm8[resource]; + + pwm8->prescaler = static_cast(prescaler); + pwm8->period_timer_val = period; + + // If PWM is already enabled, disable and restart it + if (pwm8->enabled) { + pwm8->enabled = false; + XMC_CCU8_SLICE_StopClearTimer(pwm8->slice); + // Reconfigure and restart PWM + analogWrite(pin, pwm8->d_cycle_val); // Use the saved duty cycle value + } + + return SUCCESS; // Configuration successful + } +#endif + + // No matching PWM resource found + return ERROR_NO_PWM_RESOURCE; +} + +//**************************************************************************** +// END OF FILE +//**************************************************************************** diff --git a/cores/xmc/wiring_digital.c b/cores/xmc/wiring_digital.c new file mode 100644 index 00000000..e138fa98 --- /dev/null +++ b/cores/xmc/wiring_digital.c @@ -0,0 +1,67 @@ +#include "Arduino.h" +#ifdef __cplusplus +extern "C" { +#endif +void pinMode(pin_size_t pin, PinMode mode) { + XMC_GPIO_CONFIG_t gpio_conf; + bool gpio_init_value = false; + + switch (mode) { + case INPUT: + gpio_conf.mode = XMC_GPIO_MODE_INPUT_TRISTATE; + gpio_conf.output_level = XMC_GPIO_OUTPUT_LEVEL_LOW; + break; + + case INPUT_PULLUP: + gpio_conf.mode = XMC_GPIO_MODE_INPUT_PULL_UP; + gpio_conf.output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH; + break; + + case INPUT_PULLDOWN: + gpio_conf.mode = XMC_GPIO_MODE_INPUT_PULL_DOWN; + gpio_conf.output_level = XMC_GPIO_OUTPUT_LEVEL_LOW; + break; + + case OUTPUT: + gpio_conf.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL; + gpio_conf.output_level = XMC_GPIO_OUTPUT_LEVEL_LOW; + break; + case OUTPUT_OPENDRAIN: + gpio_conf.mode = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN; + gpio_conf.output_level = XMC_GPIO_OUTPUT_LEVEL_LOW; + break; + + default: + return; + } + +#if UC_FAMILY == XMC1 + gpio_conf.input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_LARGE; +#endif + XMC_GPIO_Init(mapping_port_pin[pin].port, mapping_port_pin[pin].pin, &gpio_conf); + gpio_current_value[pin] = gpio_init_value; +} + +PinStatus digitalRead(pin_size_t pin) { + gpio_current_value[pin] = + XMC_GPIO_GetInput(mapping_port_pin[pin].port, mapping_port_pin[pin].pin) ? HIGH : LOW; + return gpio_current_value[pin]; +} + +void digitalWrite(pin_size_t pin, PinStatus status) { + XMC_GPIO_SetOutputLevel(mapping_port_pin[pin].port, mapping_port_pin[pin].pin, + (status == LOW) ? XMC_GPIO_OUTPUT_LEVEL_LOW + : XMC_GPIO_OUTPUT_LEVEL_HIGH); + if (status == LOW) { + gpio_current_value[pin] = false; + } else { + gpio_current_value[pin] = true; + } +} + +#ifdef __cplusplus +} +#endif +//**************************************************************************** +// END OF FILE +//**************************************************************************** \ No newline at end of file diff --git a/cores/wiring_time.c b/cores/xmc/wiring_time.c similarity index 90% rename from cores/wiring_time.c rename to cores/xmc/wiring_time.c index 617b587f..d4811037 100644 --- a/cores/wiring_time.c +++ b/cores/xmc/wiring_time.c @@ -126,7 +126,7 @@ findID Get ID of first task from task address // @Project Includes //**************************************************************************** #include "Arduino.h" -extern int tone_irq_action(int, int16_t); +extern int tone_irq_action(int, int16_t); // TODO: not needed for timer yet. //**************************************************************************** // @Macros @@ -135,8 +135,6 @@ extern int tone_irq_action(int, int16_t); #define _MAX_TASKS NUM_TASKS_VARIANT #define SYSTIMER_PRIORITY (4U) -/* Millisecond to Microsecond ratio */ -#define TIMER_1mSec 1000 //**************************************************************************** // @Global Variables @@ -199,17 +197,47 @@ void wiring_time_init(void) { for (int i = 0; i < _MAX_TASKS; i++) { taskTable[i].param = i; // Preset user parameter to task number // Fill with call back function addresses - if (i < NUM_TONE_PINS) - tasks[i] = tone_irq_action; // Tone callbacks - else + if (i < NUM_TONE_PINS) { + tasks[i] = tone_irq_action; + } else { tasks[i] = NULL; // Special case delay() ms callback + } } - /* setting of First SW Timer period is always and sub-priority value for XMC4000 devices */ /* setting of priority value for XMC1000 devices */ NVIC_SetPriority(SysTick_IRQn, SYSTIMER_PRIORITY); } +/* + * \brief Returns the number of milliseconds since the Arduino board began running the current + * program. + * + * This number will overflow (go back to zero), after approximately 50 days. + * + * \return Number of milliseconds since the program started (uint32_t) + */ + +unsigned long millis() { return (g_systick_count); } + +/* + * \brief Returns the number of microseconds since the Arduino board began running the current + program. + * + * This number will overflow (go back to zero), after approximately 70 minutes. + * On XMC boards the returned value has resolution of 1 microsecond as it is + * calculated from a hardware timer running counting clock cycles to produce + * 1 millisecond interval interrupts. + * + * \note There are 1,000 microseconds in a millisecond and 1,000,000 microseconds in a second. + + get micro seconds since power up + Read milli seconds (in microseconds) and convert Systick counter to microseconds to add to it + remember SysTick->VAL counts DOWN to zero */ +unsigned long micros() { + return (((SYSTICK_MS - SysTick->VAL) / SYSTICK_US) + + (g_systick_count * SYSTIMER_TICK_PERIOD_US)); +} + /* delay - milliseconds * This function uses SysTick Exception for controlling the timer list. Call back function * registered through this function will be called in SysTick exception when the timer is expired. @@ -230,6 +258,20 @@ void delay(uint32_t dwMs) { delay_timer_expired = FALSE; } +/* + * \brief Pauses the program for the amount of time (in microseconds) specified as parameter. + * + * \param dwUs the number of microseconds to pause (uint32_t) + */ +void delayMicroseconds(unsigned int usec) { + if (usec == 0) + return; + else + do + NOPS_FOR_USEC() // NOP loop to generate delay + while (--usec); +} + /* Handler function called from SysTick event handler. - Task scheduling loop diff --git a/cores/wiring_time.h b/cores/xmc/wiring_time.h similarity index 86% rename from cores/wiring_time.h rename to cores/xmc/wiring_time.h index 6045683f..e7f5bd12 100644 --- a/cores/wiring_time.h +++ b/cores/xmc/wiring_time.h @@ -348,63 +348,6 @@ extern volatile uint32_t g_systick_count; */ extern void wiring_time_init(void); -/* - * \brief Returns the number of milliseconds since the Arduino board began running the current - * program. - * - * This number will overflow (go back to zero), after approximately 50 days. - * - * \return Number of milliseconds since the program started (uint32_t) - */ -static inline uint32_t millis() __attribute__((always_inline)); - -static inline uint32_t millis() { return (g_systick_count); } - -/* - * \brief Returns the number of microseconds since the Arduino board began running the current - program. - * - * This number will overflow (go back to zero), after approximately 70 minutes. - * On XMC boards the returned value has resolution of 1 microsecond as it is - * calculated from a hardware timer running counting clock cycles to produce - * 1 millisecond interval interrupts. - * - * \note There are 1,000 microseconds in a millisecond and 1,000,000 microseconds in a second. - - get micro seconds since power up - Read milli seconds (in microseconds) and convert Systick counter to microseconds to add to it - remember SysTick->VAL counts DOWN to zero */ -static inline uint32_t micros() __attribute__((always_inline)); - -static inline uint32_t micros() { - return (((SYSTICK_MS - SysTick->VAL) / SYSTICK_US) + - (g_systick_count * SYSTIMER_TICK_PERIOD_US)); -} - -/* - * \brief Pauses the program for the amount of time (in milliseconds) specified as parameter. - * (There are 1000 milliseconds in a second.) - * - * \param dwMs the number of milliseconds to pause (uint32_t) - */ -extern void delay(uint32_t dwMs); - -/* - * \brief Pauses the program for the amount of time (in microseconds) specified as parameter. - * - * \param dwUs the number of microseconds to pause (uint32_t) - */ -static inline void delayMicroseconds(uint32_t) __attribute__((always_inline)); - -static inline void delayMicroseconds(uint32_t usec) { - if (usec == 0) - return; - else - do - NOPS_FOR_USEC() // NOP loop to generate delay - while (--usec); -} - extern int setInterval(int, uint32_t); extern uint32_t getInterval(int); extern int setParam(int, int16_t); diff --git a/cores/xmc_lib/CMSIS/DSP/Include/arm_common_tables.h b/cores/xmc/xmc_lib/CMSIS/DSP/Include/arm_common_tables.h similarity index 100% rename from cores/xmc_lib/CMSIS/DSP/Include/arm_common_tables.h rename to cores/xmc/xmc_lib/CMSIS/DSP/Include/arm_common_tables.h diff --git a/cores/xmc_lib/CMSIS/DSP/Include/arm_const_structs.h b/cores/xmc/xmc_lib/CMSIS/DSP/Include/arm_const_structs.h similarity index 100% rename from cores/xmc_lib/CMSIS/DSP/Include/arm_const_structs.h rename to cores/xmc/xmc_lib/CMSIS/DSP/Include/arm_const_structs.h diff --git a/cores/xmc_lib/CMSIS/DSP/Include/arm_math.h b/cores/xmc/xmc_lib/CMSIS/DSP/Include/arm_math.h similarity index 100% rename from cores/xmc_lib/CMSIS/DSP/Include/arm_math.h rename to cores/xmc/xmc_lib/CMSIS/DSP/Include/arm_math.h diff --git a/cores/xmc_lib/CMSIS/DSP/Source/arm_abs_f32.c b/cores/xmc/xmc_lib/CMSIS/DSP/Source/arm_abs_f32.c similarity index 100% rename from cores/xmc_lib/CMSIS/DSP/Source/arm_abs_f32.c rename to cores/xmc/xmc_lib/CMSIS/DSP/Source/arm_abs_f32.c diff --git a/cores/xmc_lib/CMSIS/DSP/Source/arm_bitreversal.c b/cores/xmc/xmc_lib/CMSIS/DSP/Source/arm_bitreversal.c similarity index 100% rename from cores/xmc_lib/CMSIS/DSP/Source/arm_bitreversal.c rename to cores/xmc/xmc_lib/CMSIS/DSP/Source/arm_bitreversal.c diff --git a/cores/xmc_lib/CMSIS/DSP/Source/arm_bitreversal2.S b/cores/xmc/xmc_lib/CMSIS/DSP/Source/arm_bitreversal2.S similarity index 100% rename from cores/xmc_lib/CMSIS/DSP/Source/arm_bitreversal2.S rename to cores/xmc/xmc_lib/CMSIS/DSP/Source/arm_bitreversal2.S diff --git a/cores/xmc_lib/CMSIS/DSP/Source/arm_cfft_f32.c b/cores/xmc/xmc_lib/CMSIS/DSP/Source/arm_cfft_f32.c similarity index 100% rename from cores/xmc_lib/CMSIS/DSP/Source/arm_cfft_f32.c rename to cores/xmc/xmc_lib/CMSIS/DSP/Source/arm_cfft_f32.c diff --git a/cores/xmc_lib/CMSIS/DSP/Source/arm_cfft_radix8_f32.c b/cores/xmc/xmc_lib/CMSIS/DSP/Source/arm_cfft_radix8_f32.c similarity index 100% rename from cores/xmc_lib/CMSIS/DSP/Source/arm_cfft_radix8_f32.c rename to cores/xmc/xmc_lib/CMSIS/DSP/Source/arm_cfft_radix8_f32.c diff --git a/cores/xmc_lib/CMSIS/DSP/Source/arm_common_tables.c b/cores/xmc/xmc_lib/CMSIS/DSP/Source/arm_common_tables.c similarity index 100% rename from cores/xmc_lib/CMSIS/DSP/Source/arm_common_tables.c rename to cores/xmc/xmc_lib/CMSIS/DSP/Source/arm_common_tables.c diff --git a/cores/xmc_lib/CMSIS/DSP/Source/arm_const_structs.c b/cores/xmc/xmc_lib/CMSIS/DSP/Source/arm_const_structs.c similarity index 100% rename from cores/xmc_lib/CMSIS/DSP/Source/arm_const_structs.c rename to cores/xmc/xmc_lib/CMSIS/DSP/Source/arm_const_structs.c diff --git a/cores/xmc_lib/CMSIS/DSP/Source/arm_copy_q7.c b/cores/xmc/xmc_lib/CMSIS/DSP/Source/arm_copy_q7.c similarity index 100% rename from cores/xmc_lib/CMSIS/DSP/Source/arm_copy_q7.c rename to cores/xmc/xmc_lib/CMSIS/DSP/Source/arm_copy_q7.c diff --git a/cores/xmc_lib/CMSIS/DSP/Source/arm_mean_f32.c b/cores/xmc/xmc_lib/CMSIS/DSP/Source/arm_mean_f32.c similarity index 100% rename from cores/xmc_lib/CMSIS/DSP/Source/arm_mean_f32.c rename to cores/xmc/xmc_lib/CMSIS/DSP/Source/arm_mean_f32.c diff --git a/cores/xmc_lib/CMSIS/DSP/Source/arm_mean_q15.c b/cores/xmc/xmc_lib/CMSIS/DSP/Source/arm_mean_q15.c similarity index 100% rename from cores/xmc_lib/CMSIS/DSP/Source/arm_mean_q15.c rename to cores/xmc/xmc_lib/CMSIS/DSP/Source/arm_mean_q15.c diff --git a/cores/xmc_lib/CMSIS/DSP/Source/arm_mean_q31.c b/cores/xmc/xmc_lib/CMSIS/DSP/Source/arm_mean_q31.c similarity index 100% rename from cores/xmc_lib/CMSIS/DSP/Source/arm_mean_q31.c rename to cores/xmc/xmc_lib/CMSIS/DSP/Source/arm_mean_q31.c diff --git a/cores/xmc_lib/CMSIS/DSP/Source/arm_rfft_fast_f32.c b/cores/xmc/xmc_lib/CMSIS/DSP/Source/arm_rfft_fast_f32.c similarity index 100% rename from cores/xmc_lib/CMSIS/DSP/Source/arm_rfft_fast_f32.c rename to cores/xmc/xmc_lib/CMSIS/DSP/Source/arm_rfft_fast_f32.c diff --git a/cores/xmc_lib/CMSIS/DSP/Source/arm_rfft_fast_init_f32.c b/cores/xmc/xmc_lib/CMSIS/DSP/Source/arm_rfft_fast_init_f32.c similarity index 100% rename from cores/xmc_lib/CMSIS/DSP/Source/arm_rfft_fast_init_f32.c rename to cores/xmc/xmc_lib/CMSIS/DSP/Source/arm_rfft_fast_init_f32.c diff --git a/cores/xmc_lib/CMSIS/DSP/Source/arm_var_f32.c b/cores/xmc/xmc_lib/CMSIS/DSP/Source/arm_var_f32.c similarity index 100% rename from cores/xmc_lib/CMSIS/DSP/Source/arm_var_f32.c rename to cores/xmc/xmc_lib/CMSIS/DSP/Source/arm_var_f32.c diff --git a/cores/xmc_lib/CMSIS/Include/cmsis_compiler.h b/cores/xmc/xmc_lib/CMSIS/Include/cmsis_compiler.h similarity index 100% rename from cores/xmc_lib/CMSIS/Include/cmsis_compiler.h rename to cores/xmc/xmc_lib/CMSIS/Include/cmsis_compiler.h diff --git a/cores/xmc_lib/CMSIS/Include/cmsis_gcc.h b/cores/xmc/xmc_lib/CMSIS/Include/cmsis_gcc.h similarity index 100% rename from cores/xmc_lib/CMSIS/Include/cmsis_gcc.h rename to cores/xmc/xmc_lib/CMSIS/Include/cmsis_gcc.h diff --git a/cores/xmc_lib/CMSIS/Include/cmsis_version.h b/cores/xmc/xmc_lib/CMSIS/Include/cmsis_version.h similarity index 100% rename from cores/xmc_lib/CMSIS/Include/cmsis_version.h rename to cores/xmc/xmc_lib/CMSIS/Include/cmsis_version.h diff --git a/cores/xmc_lib/CMSIS/Include/core_cm0.h b/cores/xmc/xmc_lib/CMSIS/Include/core_cm0.h similarity index 100% rename from cores/xmc_lib/CMSIS/Include/core_cm0.h rename to cores/xmc/xmc_lib/CMSIS/Include/core_cm0.h diff --git a/cores/xmc_lib/CMSIS/Include/core_cm4.h b/cores/xmc/xmc_lib/CMSIS/Include/core_cm4.h similarity index 100% rename from cores/xmc_lib/CMSIS/Include/core_cm4.h rename to cores/xmc/xmc_lib/CMSIS/Include/core_cm4.h diff --git a/cores/xmc_lib/CMSIS/Include/mpu_armv7.h b/cores/xmc/xmc_lib/CMSIS/Include/mpu_armv7.h similarity index 100% rename from cores/xmc_lib/CMSIS/Include/mpu_armv7.h rename to cores/xmc/xmc_lib/CMSIS/Include/mpu_armv7.h diff --git a/cores/xmc_lib/CMSIS/NN/Include/arm_nn_tables.h b/cores/xmc/xmc_lib/CMSIS/NN/Include/arm_nn_tables.h similarity index 100% rename from cores/xmc_lib/CMSIS/NN/Include/arm_nn_tables.h rename to cores/xmc/xmc_lib/CMSIS/NN/Include/arm_nn_tables.h diff --git a/cores/xmc_lib/CMSIS/NN/Include/arm_nnfunctions.h b/cores/xmc/xmc_lib/CMSIS/NN/Include/arm_nnfunctions.h similarity index 100% rename from cores/xmc_lib/CMSIS/NN/Include/arm_nnfunctions.h rename to cores/xmc/xmc_lib/CMSIS/NN/Include/arm_nnfunctions.h diff --git a/cores/xmc_lib/CMSIS/NN/Include/arm_nnsupportfunctions.h b/cores/xmc/xmc_lib/CMSIS/NN/Include/arm_nnsupportfunctions.h similarity index 100% rename from cores/xmc_lib/CMSIS/NN/Include/arm_nnsupportfunctions.h rename to cores/xmc/xmc_lib/CMSIS/NN/Include/arm_nnsupportfunctions.h diff --git a/cores/xmc_lib/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q15.c b/cores/xmc/xmc_lib/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q15.c similarity index 100% rename from cores/xmc_lib/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q15.c rename to cores/xmc/xmc_lib/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q15.c diff --git a/cores/xmc_lib/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q7.c b/cores/xmc/xmc_lib/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q7.c similarity index 100% rename from cores/xmc_lib/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q7.c rename to cores/xmc/xmc_lib/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q7.c diff --git a/cores/xmc_lib/CMSIS/NN/Source/ActivationFunctions/arm_relu_q15.c b/cores/xmc/xmc_lib/CMSIS/NN/Source/ActivationFunctions/arm_relu_q15.c similarity index 100% rename from cores/xmc_lib/CMSIS/NN/Source/ActivationFunctions/arm_relu_q15.c rename to cores/xmc/xmc_lib/CMSIS/NN/Source/ActivationFunctions/arm_relu_q15.c diff --git a/cores/xmc_lib/CMSIS/NN/Source/ActivationFunctions/arm_relu_q7.c b/cores/xmc/xmc_lib/CMSIS/NN/Source/ActivationFunctions/arm_relu_q7.c similarity index 100% rename from cores/xmc_lib/CMSIS/NN/Source/ActivationFunctions/arm_relu_q7.c rename to cores/xmc/xmc_lib/CMSIS/NN/Source/ActivationFunctions/arm_relu_q7.c diff --git a/cores/xmc_lib/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1x1_HWC_q7_fast_nonsquare.c b/cores/xmc/xmc_lib/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1x1_HWC_q7_fast_nonsquare.c similarity index 100% rename from cores/xmc_lib/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1x1_HWC_q7_fast_nonsquare.c rename to cores/xmc/xmc_lib/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1x1_HWC_q7_fast_nonsquare.c diff --git a/cores/xmc_lib/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_basic.c b/cores/xmc/xmc_lib/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_basic.c similarity index 100% rename from cores/xmc_lib/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_basic.c rename to cores/xmc/xmc_lib/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_basic.c diff --git a/cores/xmc_lib/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast.c b/cores/xmc/xmc_lib/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast.c similarity index 100% rename from cores/xmc_lib/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast.c rename to cores/xmc/xmc_lib/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast.c diff --git a/cores/xmc_lib/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_RGB.c b/cores/xmc/xmc_lib/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_RGB.c similarity index 100% rename from cores/xmc_lib/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_RGB.c rename to cores/xmc/xmc_lib/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_RGB.c diff --git a/cores/xmc_lib/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic.c b/cores/xmc/xmc_lib/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic.c similarity index 100% rename from cores/xmc_lib/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic.c rename to cores/xmc/xmc_lib/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic.c diff --git a/cores/xmc_lib/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast.c b/cores/xmc/xmc_lib/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast.c similarity index 100% rename from cores/xmc_lib/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast.c rename to cores/xmc/xmc_lib/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast.c diff --git a/cores/xmc_lib/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast_nonsquare.c b/cores/xmc/xmc_lib/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast_nonsquare.c similarity index 100% rename from cores/xmc_lib/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast_nonsquare.c rename to cores/xmc/xmc_lib/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast_nonsquare.c diff --git a/cores/xmc_lib/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7.c b/cores/xmc/xmc_lib/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7.c similarity index 100% rename from cores/xmc_lib/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7.c rename to cores/xmc/xmc_lib/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7.c diff --git a/cores/xmc_lib/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7_nonsquare.c b/cores/xmc/xmc_lib/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7_nonsquare.c similarity index 100% rename from cores/xmc_lib/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7_nonsquare.c rename to cores/xmc/xmc_lib/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7_nonsquare.c diff --git a/cores/xmc_lib/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15.c b/cores/xmc/xmc_lib/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15.c similarity index 100% rename from cores/xmc_lib/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15.c rename to cores/xmc/xmc_lib/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15.c diff --git a/cores/xmc_lib/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15_reordered.c b/cores/xmc/xmc_lib/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15_reordered.c similarity index 100% rename from cores/xmc_lib/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15_reordered.c rename to cores/xmc/xmc_lib/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15_reordered.c diff --git a/cores/xmc_lib/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15.c b/cores/xmc/xmc_lib/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15.c similarity index 100% rename from cores/xmc_lib/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15.c rename to cores/xmc/xmc_lib/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15.c diff --git a/cores/xmc_lib/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15_opt.c b/cores/xmc/xmc_lib/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15_opt.c similarity index 100% rename from cores/xmc_lib/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15_opt.c rename to cores/xmc/xmc_lib/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15_opt.c diff --git a/cores/xmc_lib/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15.c b/cores/xmc/xmc_lib/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15.c similarity index 100% rename from cores/xmc_lib/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15.c rename to cores/xmc/xmc_lib/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15.c diff --git a/cores/xmc_lib/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15_opt.c b/cores/xmc/xmc_lib/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15_opt.c similarity index 100% rename from cores/xmc_lib/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15_opt.c rename to cores/xmc/xmc_lib/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15_opt.c diff --git a/cores/xmc_lib/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7.c b/cores/xmc/xmc_lib/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7.c similarity index 100% rename from cores/xmc_lib/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7.c rename to cores/xmc/xmc_lib/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7.c diff --git a/cores/xmc_lib/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7_opt.c b/cores/xmc/xmc_lib/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7_opt.c similarity index 100% rename from cores/xmc_lib/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7_opt.c rename to cores/xmc/xmc_lib/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7_opt.c diff --git a/cores/xmc_lib/CMSIS/NN/Source/NNSupportFunctions/arm_nntables.c b/cores/xmc/xmc_lib/CMSIS/NN/Source/NNSupportFunctions/arm_nntables.c similarity index 100% rename from cores/xmc_lib/CMSIS/NN/Source/NNSupportFunctions/arm_nntables.c rename to cores/xmc/xmc_lib/CMSIS/NN/Source/NNSupportFunctions/arm_nntables.c diff --git a/cores/xmc_lib/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_no_shift.c b/cores/xmc/xmc_lib/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_no_shift.c similarity index 100% rename from cores/xmc_lib/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_no_shift.c rename to cores/xmc/xmc_lib/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_no_shift.c diff --git a/cores/xmc_lib/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_reordered_no_shift.c b/cores/xmc/xmc_lib/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_reordered_no_shift.c similarity index 100% rename from cores/xmc_lib/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_reordered_no_shift.c rename to cores/xmc/xmc_lib/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_reordered_no_shift.c diff --git a/cores/xmc_lib/CMSIS/NN/Source/PoolingFunctions/arm_pool_q7_HWC.c b/cores/xmc/xmc_lib/CMSIS/NN/Source/PoolingFunctions/arm_pool_q7_HWC.c similarity index 100% rename from cores/xmc_lib/CMSIS/NN/Source/PoolingFunctions/arm_pool_q7_HWC.c rename to cores/xmc/xmc_lib/CMSIS/NN/Source/PoolingFunctions/arm_pool_q7_HWC.c diff --git a/cores/xmc_lib/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q15.c b/cores/xmc/xmc_lib/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q15.c similarity index 100% rename from cores/xmc_lib/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q15.c rename to cores/xmc/xmc_lib/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q15.c diff --git a/cores/xmc_lib/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q7.c b/cores/xmc/xmc_lib/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q7.c similarity index 100% rename from cores/xmc_lib/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q7.c rename to cores/xmc/xmc_lib/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q7.c diff --git a/cores/xmc_lib/LIBS/syscalls.c b/cores/xmc/xmc_lib/LIBS/syscalls.c similarity index 100% rename from cores/xmc_lib/LIBS/syscalls.c rename to cores/xmc/xmc_lib/LIBS/syscalls.c diff --git a/cores/xmc_lib/LIBS/types.h b/cores/xmc/xmc_lib/LIBS/types.h similarity index 100% rename from cores/xmc_lib/LIBS/types.h rename to cores/xmc/xmc_lib/LIBS/types.h diff --git a/cores/xmc_lib/README.md b/cores/xmc/xmc_lib/README.md similarity index 100% rename from cores/xmc_lib/README.md rename to cores/xmc/xmc_lib/README.md diff --git a/cores/xmc_lib/XMCLib/License.txt b/cores/xmc/xmc_lib/XMCLib/License.txt similarity index 100% rename from cores/xmc_lib/XMCLib/License.txt rename to cores/xmc/xmc_lib/XMCLib/License.txt diff --git a/cores/xmc_lib/XMCLib/inc/xmc1_ccu4_map.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc1_ccu4_map.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc1_ccu4_map.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc1_ccu4_map.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc1_ccu8_map.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc1_ccu8_map.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc1_ccu8_map.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc1_ccu8_map.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc1_eru_map.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc1_eru_map.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc1_eru_map.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc1_eru_map.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc1_flash.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc1_flash.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc1_flash.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc1_flash.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc1_gpio.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc1_gpio.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc1_gpio.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc1_gpio.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc1_gpio_map.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc1_gpio_map.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc1_gpio_map.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc1_gpio_map.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc1_rtc.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc1_rtc.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc1_rtc.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc1_rtc.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc1_scu.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc1_scu.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc1_scu.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc1_scu.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc1_usic_map.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc1_usic_map.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc1_usic_map.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc1_usic_map.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc4_ccu4_map.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc4_ccu4_map.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc4_ccu4_map.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc4_ccu4_map.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc4_ccu8_map.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc4_ccu8_map.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc4_ccu8_map.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc4_ccu8_map.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc4_eru_map.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc4_eru_map.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc4_eru_map.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc4_eru_map.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc4_flash.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc4_flash.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc4_flash.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc4_flash.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc4_gpio.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc4_gpio.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc4_gpio.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc4_gpio.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc4_gpio_map.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc4_gpio_map.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc4_gpio_map.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc4_gpio_map.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc4_rtc.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc4_rtc.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc4_rtc.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc4_rtc.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc4_scu.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc4_scu.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc4_scu.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc4_scu.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc4_usic_map.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc4_usic_map.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc4_usic_map.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc4_usic_map.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc_acmp.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc_acmp.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc_acmp.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc_acmp.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc_bccu.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc_bccu.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc_bccu.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc_bccu.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc_can.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc_can.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc_can.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc_can.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc_can_map.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc_can_map.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc_can_map.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc_can_map.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc_ccu4.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc_ccu4.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc_ccu4.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc_ccu4.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc_ccu8.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc_ccu8.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc_ccu8.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc_ccu8.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc_common.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc_common.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc_common.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc_common.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc_dac.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc_dac.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc_dac.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc_dac.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc_device.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc_device.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc_device.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc_device.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc_dma.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc_dma.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc_dma.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc_dma.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc_dma_map.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc_dma_map.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc_dma_map.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc_dma_map.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc_dsd.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc_dsd.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc_dsd.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc_dsd.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc_ebu.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc_ebu.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc_ebu.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc_ebu.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc_ecat.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc_ecat.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc_ecat.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc_ecat.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc_ecat_map.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc_ecat_map.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc_ecat_map.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc_ecat_map.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc_eru.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc_eru.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc_eru.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc_eru.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc_eth_mac.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc_eth_mac.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc_eth_mac.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc_eth_mac.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc_eth_mac_map.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc_eth_mac_map.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc_eth_mac_map.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc_eth_mac_map.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc_eth_phy.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc_eth_phy.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc_eth_phy.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc_eth_phy.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc_fce.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc_fce.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc_fce.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc_fce.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc_flash.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc_flash.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc_flash.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc_flash.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc_gpio.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc_gpio.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc_gpio.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc_gpio.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc_hrpwm.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc_hrpwm.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc_hrpwm.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc_hrpwm.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc_hrpwm_map.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc_hrpwm_map.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc_hrpwm_map.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc_hrpwm_map.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc_i2c.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc_i2c.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc_i2c.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc_i2c.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc_i2s.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc_i2s.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc_i2s.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc_i2s.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc_ledts.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc_ledts.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc_ledts.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc_ledts.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc_math.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc_math.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc_math.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc_math.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc_pau.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc_pau.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc_pau.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc_pau.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc_posif.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc_posif.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc_posif.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc_posif.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc_posif_map.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc_posif_map.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc_posif_map.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc_posif_map.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc_prng.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc_prng.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc_prng.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc_prng.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc_rtc.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc_rtc.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc_rtc.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc_rtc.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc_scu.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc_scu.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc_scu.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc_scu.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc_sdmmc.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc_sdmmc.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc_sdmmc.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc_sdmmc.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc_spi.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc_spi.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc_spi.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc_spi.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc_uart.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc_uart.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc_uart.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc_uart.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc_usbd.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc_usbd.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc_usbd.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc_usbd.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc_usbd_regs.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc_usbd_regs.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc_usbd_regs.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc_usbd_regs.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc_usbh.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc_usbh.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc_usbh.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc_usbh.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc_usic.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc_usic.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc_usic.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc_usic.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc_vadc.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc_vadc.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc_vadc.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc_vadc.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc_vadc_map.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc_vadc_map.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc_vadc_map.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc_vadc_map.h diff --git a/cores/xmc_lib/XMCLib/inc/xmc_wdt.h b/cores/xmc/xmc_lib/XMCLib/inc/xmc_wdt.h similarity index 100% rename from cores/xmc_lib/XMCLib/inc/xmc_wdt.h rename to cores/xmc/xmc_lib/XMCLib/inc/xmc_wdt.h diff --git a/cores/xmc_lib/XMCLib/src/COMPONENT_CM0/TOOLCHAIN_ARM/xmc_common_mdk.s b/cores/xmc/xmc_lib/XMCLib/src/COMPONENT_CM0/TOOLCHAIN_ARM/xmc_common_mdk.s similarity index 100% rename from cores/xmc_lib/XMCLib/src/COMPONENT_CM0/TOOLCHAIN_ARM/xmc_common_mdk.s rename to cores/xmc/xmc_lib/XMCLib/src/COMPONENT_CM0/TOOLCHAIN_ARM/xmc_common_mdk.s diff --git a/cores/xmc_lib/XMCLib/src/COMPONENT_CM0/TOOLCHAIN_GCC_ARM/xmc_common_gcc.S b/cores/xmc/xmc_lib/XMCLib/src/COMPONENT_CM0/TOOLCHAIN_GCC_ARM/xmc_common_gcc.S similarity index 100% rename from cores/xmc_lib/XMCLib/src/COMPONENT_CM0/TOOLCHAIN_GCC_ARM/xmc_common_gcc.S rename to cores/xmc/xmc_lib/XMCLib/src/COMPONENT_CM0/TOOLCHAIN_GCC_ARM/xmc_common_gcc.S diff --git a/cores/xmc_lib/XMCLib/src/COMPONENT_CM0/TOOLCHAIN_IAR/xmc_common_iar.s b/cores/xmc/xmc_lib/XMCLib/src/COMPONENT_CM0/TOOLCHAIN_IAR/xmc_common_iar.s similarity index 100% rename from cores/xmc_lib/XMCLib/src/COMPONENT_CM0/TOOLCHAIN_IAR/xmc_common_iar.s rename to cores/xmc/xmc_lib/XMCLib/src/COMPONENT_CM0/TOOLCHAIN_IAR/xmc_common_iar.s diff --git a/cores/xmc_lib/XMCLib/src/COMPONENT_CM4/TOOLCHAIN_ARM/xmc_common_mdk.s b/cores/xmc/xmc_lib/XMCLib/src/COMPONENT_CM4/TOOLCHAIN_ARM/xmc_common_mdk.s similarity index 100% rename from cores/xmc_lib/XMCLib/src/COMPONENT_CM4/TOOLCHAIN_ARM/xmc_common_mdk.s rename to cores/xmc/xmc_lib/XMCLib/src/COMPONENT_CM4/TOOLCHAIN_ARM/xmc_common_mdk.s diff --git a/cores/xmc_lib/XMCLib/src/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/xmc_common_gcc.S b/cores/xmc/xmc_lib/XMCLib/src/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/xmc_common_gcc.S similarity index 100% rename from cores/xmc_lib/XMCLib/src/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/xmc_common_gcc.S rename to cores/xmc/xmc_lib/XMCLib/src/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/xmc_common_gcc.S diff --git a/cores/xmc_lib/XMCLib/src/COMPONENT_CM4/TOOLCHAIN_IAR/xmc_common_iar.s b/cores/xmc/xmc_lib/XMCLib/src/COMPONENT_CM4/TOOLCHAIN_IAR/xmc_common_iar.s similarity index 100% rename from cores/xmc_lib/XMCLib/src/COMPONENT_CM4/TOOLCHAIN_IAR/xmc_common_iar.s rename to cores/xmc/xmc_lib/XMCLib/src/COMPONENT_CM4/TOOLCHAIN_IAR/xmc_common_iar.s diff --git a/cores/xmc_lib/XMCLib/src/xmc1_eru.c b/cores/xmc/xmc_lib/XMCLib/src/xmc1_eru.c similarity index 100% rename from cores/xmc_lib/XMCLib/src/xmc1_eru.c rename to cores/xmc/xmc_lib/XMCLib/src/xmc1_eru.c diff --git a/cores/xmc_lib/XMCLib/src/xmc1_flash.c b/cores/xmc/xmc_lib/XMCLib/src/xmc1_flash.c similarity index 100% rename from cores/xmc_lib/XMCLib/src/xmc1_flash.c rename to cores/xmc/xmc_lib/XMCLib/src/xmc1_flash.c diff --git a/cores/xmc_lib/XMCLib/src/xmc1_gpio.c b/cores/xmc/xmc_lib/XMCLib/src/xmc1_gpio.c similarity index 100% rename from cores/xmc_lib/XMCLib/src/xmc1_gpio.c rename to cores/xmc/xmc_lib/XMCLib/src/xmc1_gpio.c diff --git a/cores/xmc_lib/XMCLib/src/xmc1_rtc.c b/cores/xmc/xmc_lib/XMCLib/src/xmc1_rtc.c similarity index 100% rename from cores/xmc_lib/XMCLib/src/xmc1_rtc.c rename to cores/xmc/xmc_lib/XMCLib/src/xmc1_rtc.c diff --git a/cores/xmc_lib/XMCLib/src/xmc1_scu.c b/cores/xmc/xmc_lib/XMCLib/src/xmc1_scu.c similarity index 100% rename from cores/xmc_lib/XMCLib/src/xmc1_scu.c rename to cores/xmc/xmc_lib/XMCLib/src/xmc1_scu.c diff --git a/cores/xmc_lib/XMCLib/src/xmc4_eru.c b/cores/xmc/xmc_lib/XMCLib/src/xmc4_eru.c similarity index 100% rename from cores/xmc_lib/XMCLib/src/xmc4_eru.c rename to cores/xmc/xmc_lib/XMCLib/src/xmc4_eru.c diff --git a/cores/xmc_lib/XMCLib/src/xmc4_flash.c b/cores/xmc/xmc_lib/XMCLib/src/xmc4_flash.c similarity index 100% rename from cores/xmc_lib/XMCLib/src/xmc4_flash.c rename to cores/xmc/xmc_lib/XMCLib/src/xmc4_flash.c diff --git a/cores/xmc_lib/XMCLib/src/xmc4_gpio.c b/cores/xmc/xmc_lib/XMCLib/src/xmc4_gpio.c similarity index 100% rename from cores/xmc_lib/XMCLib/src/xmc4_gpio.c rename to cores/xmc/xmc_lib/XMCLib/src/xmc4_gpio.c diff --git a/cores/xmc_lib/XMCLib/src/xmc4_rtc.c b/cores/xmc/xmc_lib/XMCLib/src/xmc4_rtc.c similarity index 100% rename from cores/xmc_lib/XMCLib/src/xmc4_rtc.c rename to cores/xmc/xmc_lib/XMCLib/src/xmc4_rtc.c diff --git a/cores/xmc_lib/XMCLib/src/xmc4_scu.c b/cores/xmc/xmc_lib/XMCLib/src/xmc4_scu.c similarity index 100% rename from cores/xmc_lib/XMCLib/src/xmc4_scu.c rename to cores/xmc/xmc_lib/XMCLib/src/xmc4_scu.c diff --git a/cores/xmc_lib/XMCLib/src/xmc_acmp.c b/cores/xmc/xmc_lib/XMCLib/src/xmc_acmp.c similarity index 100% rename from cores/xmc_lib/XMCLib/src/xmc_acmp.c rename to cores/xmc/xmc_lib/XMCLib/src/xmc_acmp.c diff --git a/cores/xmc_lib/XMCLib/src/xmc_bccu.c b/cores/xmc/xmc_lib/XMCLib/src/xmc_bccu.c similarity index 100% rename from cores/xmc_lib/XMCLib/src/xmc_bccu.c rename to cores/xmc/xmc_lib/XMCLib/src/xmc_bccu.c diff --git a/cores/xmc_lib/XMCLib/src/xmc_can.c b/cores/xmc/xmc_lib/XMCLib/src/xmc_can.c similarity index 100% rename from cores/xmc_lib/XMCLib/src/xmc_can.c rename to cores/xmc/xmc_lib/XMCLib/src/xmc_can.c diff --git a/cores/xmc_lib/XMCLib/src/xmc_ccu4.c b/cores/xmc/xmc_lib/XMCLib/src/xmc_ccu4.c similarity index 100% rename from cores/xmc_lib/XMCLib/src/xmc_ccu4.c rename to cores/xmc/xmc_lib/XMCLib/src/xmc_ccu4.c diff --git a/cores/xmc_lib/XMCLib/src/xmc_ccu8.c b/cores/xmc/xmc_lib/XMCLib/src/xmc_ccu8.c similarity index 100% rename from cores/xmc_lib/XMCLib/src/xmc_ccu8.c rename to cores/xmc/xmc_lib/XMCLib/src/xmc_ccu8.c diff --git a/cores/xmc_lib/XMCLib/src/xmc_common.c b/cores/xmc/xmc_lib/XMCLib/src/xmc_common.c similarity index 100% rename from cores/xmc_lib/XMCLib/src/xmc_common.c rename to cores/xmc/xmc_lib/XMCLib/src/xmc_common.c diff --git a/cores/xmc_lib/XMCLib/src/xmc_dac.c b/cores/xmc/xmc_lib/XMCLib/src/xmc_dac.c similarity index 100% rename from cores/xmc_lib/XMCLib/src/xmc_dac.c rename to cores/xmc/xmc_lib/XMCLib/src/xmc_dac.c diff --git a/cores/xmc_lib/XMCLib/src/xmc_dma.c b/cores/xmc/xmc_lib/XMCLib/src/xmc_dma.c similarity index 100% rename from cores/xmc_lib/XMCLib/src/xmc_dma.c rename to cores/xmc/xmc_lib/XMCLib/src/xmc_dma.c diff --git a/cores/xmc_lib/XMCLib/src/xmc_dsd.c b/cores/xmc/xmc_lib/XMCLib/src/xmc_dsd.c similarity index 100% rename from cores/xmc_lib/XMCLib/src/xmc_dsd.c rename to cores/xmc/xmc_lib/XMCLib/src/xmc_dsd.c diff --git a/cores/xmc_lib/XMCLib/src/xmc_ebu.c b/cores/xmc/xmc_lib/XMCLib/src/xmc_ebu.c similarity index 100% rename from cores/xmc_lib/XMCLib/src/xmc_ebu.c rename to cores/xmc/xmc_lib/XMCLib/src/xmc_ebu.c diff --git a/cores/xmc_lib/XMCLib/src/xmc_ecat.c b/cores/xmc/xmc_lib/XMCLib/src/xmc_ecat.c similarity index 100% rename from cores/xmc_lib/XMCLib/src/xmc_ecat.c rename to cores/xmc/xmc_lib/XMCLib/src/xmc_ecat.c diff --git a/cores/xmc_lib/XMCLib/src/xmc_eru.c b/cores/xmc/xmc_lib/XMCLib/src/xmc_eru.c similarity index 100% rename from cores/xmc_lib/XMCLib/src/xmc_eru.c rename to cores/xmc/xmc_lib/XMCLib/src/xmc_eru.c diff --git a/cores/xmc_lib/XMCLib/src/xmc_eth_mac.c b/cores/xmc/xmc_lib/XMCLib/src/xmc_eth_mac.c similarity index 100% rename from cores/xmc_lib/XMCLib/src/xmc_eth_mac.c rename to cores/xmc/xmc_lib/XMCLib/src/xmc_eth_mac.c diff --git a/cores/xmc_lib/XMCLib/src/xmc_eth_phy_dp83848.c b/cores/xmc/xmc_lib/XMCLib/src/xmc_eth_phy_dp83848.c similarity index 100% rename from cores/xmc_lib/XMCLib/src/xmc_eth_phy_dp83848.c rename to cores/xmc/xmc_lib/XMCLib/src/xmc_eth_phy_dp83848.c diff --git a/cores/xmc_lib/XMCLib/src/xmc_eth_phy_ksz8031rnl.c b/cores/xmc/xmc_lib/XMCLib/src/xmc_eth_phy_ksz8031rnl.c similarity index 100% rename from cores/xmc_lib/XMCLib/src/xmc_eth_phy_ksz8031rnl.c rename to cores/xmc/xmc_lib/XMCLib/src/xmc_eth_phy_ksz8031rnl.c diff --git a/cores/xmc_lib/XMCLib/src/xmc_eth_phy_ksz8081rnb.c b/cores/xmc/xmc_lib/XMCLib/src/xmc_eth_phy_ksz8081rnb.c similarity index 100% rename from cores/xmc_lib/XMCLib/src/xmc_eth_phy_ksz8081rnb.c rename to cores/xmc/xmc_lib/XMCLib/src/xmc_eth_phy_ksz8081rnb.c diff --git a/cores/xmc_lib/XMCLib/src/xmc_fce.c b/cores/xmc/xmc_lib/XMCLib/src/xmc_fce.c similarity index 100% rename from cores/xmc_lib/XMCLib/src/xmc_fce.c rename to cores/xmc/xmc_lib/XMCLib/src/xmc_fce.c diff --git a/cores/xmc_lib/XMCLib/src/xmc_gpio.c b/cores/xmc/xmc_lib/XMCLib/src/xmc_gpio.c similarity index 100% rename from cores/xmc_lib/XMCLib/src/xmc_gpio.c rename to cores/xmc/xmc_lib/XMCLib/src/xmc_gpio.c diff --git a/cores/xmc_lib/XMCLib/src/xmc_hrpwm.c b/cores/xmc/xmc_lib/XMCLib/src/xmc_hrpwm.c similarity index 100% rename from cores/xmc_lib/XMCLib/src/xmc_hrpwm.c rename to cores/xmc/xmc_lib/XMCLib/src/xmc_hrpwm.c diff --git a/cores/xmc_lib/XMCLib/src/xmc_i2c.c b/cores/xmc/xmc_lib/XMCLib/src/xmc_i2c.c similarity index 100% rename from cores/xmc_lib/XMCLib/src/xmc_i2c.c rename to cores/xmc/xmc_lib/XMCLib/src/xmc_i2c.c diff --git a/cores/xmc_lib/XMCLib/src/xmc_i2s.c b/cores/xmc/xmc_lib/XMCLib/src/xmc_i2s.c similarity index 100% rename from cores/xmc_lib/XMCLib/src/xmc_i2s.c rename to cores/xmc/xmc_lib/XMCLib/src/xmc_i2s.c diff --git a/cores/xmc_lib/XMCLib/src/xmc_ledts.c b/cores/xmc/xmc_lib/XMCLib/src/xmc_ledts.c similarity index 100% rename from cores/xmc_lib/XMCLib/src/xmc_ledts.c rename to cores/xmc/xmc_lib/XMCLib/src/xmc_ledts.c diff --git a/cores/xmc_lib/XMCLib/src/xmc_math.c b/cores/xmc/xmc_lib/XMCLib/src/xmc_math.c similarity index 100% rename from cores/xmc_lib/XMCLib/src/xmc_math.c rename to cores/xmc/xmc_lib/XMCLib/src/xmc_math.c diff --git a/cores/xmc_lib/XMCLib/src/xmc_pau.c b/cores/xmc/xmc_lib/XMCLib/src/xmc_pau.c similarity index 100% rename from cores/xmc_lib/XMCLib/src/xmc_pau.c rename to cores/xmc/xmc_lib/XMCLib/src/xmc_pau.c diff --git a/cores/xmc_lib/XMCLib/src/xmc_posif.c b/cores/xmc/xmc_lib/XMCLib/src/xmc_posif.c similarity index 100% rename from cores/xmc_lib/XMCLib/src/xmc_posif.c rename to cores/xmc/xmc_lib/XMCLib/src/xmc_posif.c diff --git a/cores/xmc_lib/XMCLib/src/xmc_prng.c b/cores/xmc/xmc_lib/XMCLib/src/xmc_prng.c similarity index 100% rename from cores/xmc_lib/XMCLib/src/xmc_prng.c rename to cores/xmc/xmc_lib/XMCLib/src/xmc_prng.c diff --git a/cores/xmc_lib/XMCLib/src/xmc_rtc.c b/cores/xmc/xmc_lib/XMCLib/src/xmc_rtc.c similarity index 100% rename from cores/xmc_lib/XMCLib/src/xmc_rtc.c rename to cores/xmc/xmc_lib/XMCLib/src/xmc_rtc.c diff --git a/cores/xmc_lib/XMCLib/src/xmc_sdmmc.c b/cores/xmc/xmc_lib/XMCLib/src/xmc_sdmmc.c similarity index 100% rename from cores/xmc_lib/XMCLib/src/xmc_sdmmc.c rename to cores/xmc/xmc_lib/XMCLib/src/xmc_sdmmc.c diff --git a/cores/xmc_lib/XMCLib/src/xmc_spi.c b/cores/xmc/xmc_lib/XMCLib/src/xmc_spi.c similarity index 100% rename from cores/xmc_lib/XMCLib/src/xmc_spi.c rename to cores/xmc/xmc_lib/XMCLib/src/xmc_spi.c diff --git a/cores/xmc_lib/XMCLib/src/xmc_uart.c b/cores/xmc/xmc_lib/XMCLib/src/xmc_uart.c similarity index 100% rename from cores/xmc_lib/XMCLib/src/xmc_uart.c rename to cores/xmc/xmc_lib/XMCLib/src/xmc_uart.c diff --git a/cores/xmc_lib/XMCLib/src/xmc_usbd.c b/cores/xmc/xmc_lib/XMCLib/src/xmc_usbd.c similarity index 100% rename from cores/xmc_lib/XMCLib/src/xmc_usbd.c rename to cores/xmc/xmc_lib/XMCLib/src/xmc_usbd.c diff --git a/cores/xmc_lib/XMCLib/src/xmc_usbh.c b/cores/xmc/xmc_lib/XMCLib/src/xmc_usbh.c similarity index 100% rename from cores/xmc_lib/XMCLib/src/xmc_usbh.c rename to cores/xmc/xmc_lib/XMCLib/src/xmc_usbh.c diff --git a/cores/xmc_lib/XMCLib/src/xmc_usic.c b/cores/xmc/xmc_lib/XMCLib/src/xmc_usic.c similarity index 100% rename from cores/xmc_lib/XMCLib/src/xmc_usic.c rename to cores/xmc/xmc_lib/XMCLib/src/xmc_usic.c diff --git a/cores/xmc_lib/XMCLib/src/xmc_vadc.c b/cores/xmc/xmc_lib/XMCLib/src/xmc_vadc.c similarity index 100% rename from cores/xmc_lib/XMCLib/src/xmc_vadc.c rename to cores/xmc/xmc_lib/XMCLib/src/xmc_vadc.c diff --git a/cores/xmc_lib/XMCLib/src/xmc_wdt.c b/cores/xmc/xmc_lib/XMCLib/src/xmc_wdt.c similarity index 100% rename from cores/xmc_lib/XMCLib/src/xmc_wdt.c rename to cores/xmc/xmc_lib/XMCLib/src/xmc_wdt.c diff --git a/cores/yield.c b/cores/xmc/yield.c similarity index 100% rename from cores/yield.c rename to cores/xmc/yield.c diff --git a/docs/arduino-deviations.rst b/docs/arduino-deviations.rst index 2d8e5f2e..aa264266 100644 --- a/docs/arduino-deviations.rst +++ b/docs/arduino-deviations.rst @@ -43,6 +43,12 @@ like Serial or in INPUT mode. On XMC boards the inputs are UNDEFINED, you MUST specify every pin to be in INPUT Mode that needs Inputs. +Interrupt ++++++++++ + +XMC1400 Kit for Arduino - Interrupt 1 pin allocated to pin number - **7** +.. code-block:: + const byte interruptPin = 7; // for interrupt-1 Wire/I2C Differences ++++++++++++++++++++ @@ -68,125 +74,38 @@ must be Slave mode configuration and sets the I2C configuration differently. Tone ++++ -Number of Tone pins is determined by pins_arduino.h define NUM_TONE_PINS. -This allows for use in other modules and for variations between boards as ->100MHz boards can obviously handle more tone pins. +Number of Tone pins is determined by pins_arduino.h define NUM_TONE_PINS. This allows for use in other modules and for variations between boards as >100MHz boards can obviously handle more tone pins. The default for XMC1xxx is 4 with a change XMC4xxxx should be 16 Tone has frequency range of maximum = 500 Hz minimum = 1 Hz -This is due to the fact that the tone frequency is software derived from -the Systick handler, Systick has a time period of 1 ms. At maximum each -handler event for Systick toggles a GPIO pin, so at minimum period of 1 ms -the output is toggled, so TWO events produce one square wave cycle, therefore -the maximum output frequency is 500Hz. +Due to the Systick periodicity, only discrete frequencies are supported as listed below: +[1, 2, 4, 5, 10, 20, 25, 50, 100, 125, 250, 500] -The minimum is due to the fact that tone function only accepts an unsigned -integer (32 bit) for the frequency, so the minimum usable frequency is 1. +This is due to the fact that the tone frequency is software derived from the Systick handler, Systick has a time period of 1 ms. At maximum each handler event for Systick toggles a GPIO pin, so at minimum period of 1 ms the output is toggled, so TWO events produce one square wave cycle, therefore the maximum output frequency is 500Hz. -Standard Arduino boards use hardware timers (the few that are available) to -generate tones and at least one timer can interfere with other functions. +The minimum is due to the fact that tone function only accepts an unsigned integer (32 bit) for the frequency, so the minimum usable frequency is 1. -However this does mean you can have more tone pins, just much lower frequency range. +Standard Arduino boards use hardware timers (the few that are available) to generate tones and at least one timer can interfere with other functions. +However this does mean you can have more tone pins, just much lower frequency range. -Analog Functions and improvements +Analog Functions ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -wiring_analog after V1.2.1 ------------------------------ -Analog functions like analogRead and analogWrite etc. have changed after -V1.2.1 to have extra safety measures to ensure invalid settings cannot be -done and report errors. - -Additionally extra getter functions have been added so other libraries can -access the resolution of read and write functions as number of bits and -current maximum value possible. - - -Extra functions ---------------- - -These functions return the analogue resolution as number of bits - -* uint8_t getAnalogReadBits( ) - range 8 to 12 -* uint8_t getAnalogWriteBits( ) - range 8 to 16 - -These functions return the analogue resolution as its maximum value - -* uint16_t getAnalogReadMaximum( ) - range 255 to 4095 -* uint16_t getAnalogWriteMaximum( ) - range 255 to 65535 - -This function enables the analog amplifiers at the ADC inputs with -adjustible gain (for XMC1000 series) - -* uint32_t analogRead_variableGain( uint8_t channel, uint8_t gain_value ) - -The gain factor values can be found :ref:`here `. - - -Default Values +Resolution -------------- -Read resolution default is 10 bits (0 to 1023) - -Write resolution default is 8 bits (0 to 255) - +Read resolution default is **10 bits (0 to 1023)** +You can set the read resolution to 8, 9, 10, 11 or 12 bits using the +:command:`analogReadResolution( bits )` function, where bits is the number of bits +you want to set the resolution to. -Error and Return Codes by Function ----------------------------------- +Write resolution default is **8 bits (0 to 255)** +You can set the write resolution to 8, 9, 10, 11, 12, 13, 14, 15 or 16 bits using the +:command:`analogWriteResolution( bits )` function, where bits is the number of bits +you want to set the resolution to. -Where possible functions do :command:`NOT` action invalid parameters passed in. - -Functions return error codes or valid values so be sure which error -code you are looking for as some functions can return 0 as a valid -value (e.g. analogRead) so an out of range value is returned instead. - -.. list-table:: - :header-rows: 1 - - * - Function - - Valid Return - - Errors - * - analogReadResolution - - | 8 to 12 - | as passed in - - 255 - * - getAnalogReadBits - - 8 to 12 - - none - * - getanalogReadMaximum - - 255 to 4095 - - none - * - analogWriteResolution - - | 8 to 16 - | as passed in - - 255 - * - getAnalogWriteBits - - 8 to 16 - - none - * - getanalogWriteMaximum - - 255 to 65535 - - none - * - analogRead - - 0 to Maximum for Resolution - - | 0xFFFFFFFF usually - | invalid channel - * - analogWrite - - 0 success - - | -1 = invalid value - | -2 = wrong pin - * - setAnalogWriteFrequency - - 0 success - - | -1 = invalid frequency - | -2 = wrong pin - * - analogReference - - none - - NULL function see below - -This should enable checks in software for valid operation -and debugging problem code. AREF Analogue Reference ----------------------- @@ -195,50 +114,56 @@ On all boards the Analogue Reference is set to use the internal power supply (however noisy), so the AREF pin is an :command:`OUTPUT` of the AREF in use. Do :command:`NOT` connect any external voltage source to this pin, or use shields that change this voltage. +This pin :command:`CANNOT` be reassigned as GPIO (pinMode has no effect). -:command:`CAUTION` any shorts on this pin especially to 0V (GND) will bring +|:warning:| :command:`CAUTION` any shorts on this pin especially to 0V (GND) will bring down the supply of the chip. -The pin voltage is the current supply voltage to AREF for analogue conversions. +:command:`analogReference( )` -This pin :command:`CANNOT` be reassigned as GPIO (pinMode has no effect). +This function has only one defalut mode **DEFAULT** = 3.3V and will not match any call on parameters +passed in with other libraries or examples that use this call. Any shields and examples that try to +change this, will :command:`NOT` function +the same on these boards. -:command:`analogReference( )` +DAC Analog Output +----------------------- +:command:`analogWrite( )` -This function has NO operation and will not match any call on parameters -passed in with other libraries or examples that use this call. +This API usually Writes an analog value (PWM wave) to a pin. Some XMC4 boards have true analog output +capabilities on the DAC enabled pins. -Any shields and examples that try to change this, will :command:`NOT` function -the same on these boards. +The DAC output voltage range for the XMC4000 series is limited to a **minimum** of **0.3V** and a **maximum** of **2.5V**. -Analog amplifiers at the ADC inputs with adjustible gain --------------------------------------------------------- -Each analog input channel can be configured to be amplified by an adjustable -gain factor, for XMC1000 series. To configure the gain, the gain value is to -be selected in the analogRead_variableGain() function which translates to a -gain factor as per the following table: + .. note:: + The following example formula can be used to convert the target voltage to a digital control value (dec_target) + suitable for the 12-bit DAC input range: -.. _gain_factor: + .. math:: -.. list-table:: - :header-rows: 1 + dec\_target = \frac{(V_{target} - 0.3V)}{2.5V} \times 4095 + + In this formula, 0.3V is the minimum voltage, 2.5V is the maximum voltage, and 4095 is the maximum value for a 12-bit DAC. + +Analog pins for XMC14_2GO +------------------------- + +On the **XMC14_2GO board**, **pins 12 and 13 are incorrectly named** - * - Gain value - - Gain factor - * - 0 - - 1 - * - 1 - - 3 - * - 2 - - 6 - * - 3 - - 12 +- Correct mapping: -For more information, please refer to the application note -`here `_. + - pin 12 -> 'A1' + - pin 13 -> 'A0' + +**Correct Usage:** + +Use the analog pin defintions instead of 12 and 13 numbers:: + + analogRead(A0); //Instead of using pin 12 + analogRead(A1); //Instead of using pin 13 I2C Analog pins ^^^^^^^^^^^^^^^ @@ -258,25 +183,24 @@ function, or other case as described below. * - Board - Functionality - Note - * - XMC1100 Boot Kit + * - KIT_XMC11_BOOT_001 - NOT supported - | A4 + A5 are separate | A6 + A7 are alternate pin | configurations to I2C - * - XMC1300 Boot Kit + * - KIT_XMC13_BOOT_001 - | NOT same pin format | as Arduino Uno R3 - | A10 + A11 are alternate pin | configurations to I2C - * - XMC1400 Arduino Kit - - Alternate pin function - - Matches Arduino Uno - * - XMC4400 Platform 2Go - - External hard wired pins + * - KIT_XMC1400_ARDUINO + - | Alternate pin function + | Matches Arduino Uno + | External hard wired pins - | For 3V3 boards set I2C pins to tristate or open drain to use - | For 5V boards refer to [this section](https://xmc-arduino.readthedocs.io/en/latest/hw-platforms.html#connected-i2s-and-analog-pins) on track cuts to enable A4 and A5 to work + | For 5V boards refer to `this section `_ on track cuts to enable A4 and A5 to work | Level shifter on the 5V board could interfere with tristate/open drain setting - * - XMC4700 Relax Kit (and variants) + * - KIT_XMC47_RELAX (and variants) - External hard wired pins - | For 3V3 boards set I2C pins to tristate or open drain to use | For 5V boards see [this section](https://xmc-arduino.readthedocs.io/en/latest/hw-platforms.html#connected-i2s-and-analog-pins) board page on track cuts to enable A4 and A5 to work @@ -301,8 +225,8 @@ via the Tools menu as shown in the picture below. :width: 600 This is generally the case for most of the XMC boards. However, for boards -such as the :ref:`xmc4200-platform2go` and the :ref:`xmc4700-relax`, both the serial -output modes are simultaneously active and neednot be selected or enabled from the menu. +such as the :ref:`KIT_XMC47_RELAX`, both the serial +output modes are simultaneously active and need not be selected or enabled from the menu. Note: Please note that the sketch must be recompiled when a different serial output is selected. diff --git a/docs/builtin-libraries.rst b/docs/builtin-libraries.rst index c8700739..2d5d2897 100644 --- a/docs/builtin-libraries.rst +++ b/docs/builtin-libraries.rst @@ -18,41 +18,37 @@ Examples Supported - Boards - Description * - DieTemperatureMeasurement - - | XMC1100 XMC 2GO - | XMC1100 Boot Kit - | XMC1100 H-Bridge 2GO - | XMC1300 Boot Kit - | XMC1400 2GO Kit - | XMC1400 Arduino Kit - | XMC4400 Platform 2Go - | XMC4700 Relax Kit + - | KIT_XMC_2GO_XMC1100_V1 + | KIT_XMC11_BOOT_001 + | KIT_XMC13_BOOT_001 + | KIT_XMC14_2GO + | KIT_XMC1400_ARDUINO + | KIT_XMC47_RELAX - | Simple die temperature measurement | for XMC devices which demonstrates | themeasure temperature of die using | sensor. * - HeapMemoryMeasurement - - | XMC1100 XMC 2GO - | XMC1100 Boot Kit - | XMC1100 H-Bridge 2GO - | XMC1300 Boot Kit - | XMC1400 2GO Kit - | XMC1400 Arduino Kit - | XMC4700 Relax Kit + - | KIT_XMC_2GO_XMC1100_V1 + | KIT_XMC11_BOOT_001 + | KIT_XMC13_BOOT_001 + | KIT_XMC14_2GO + | KIT_XMC1400_ARDUINO + | KIT_XMC47_RELAX - | Simple example to check heap memory | during run time for XMC devices which | demonstrates the ability to check on | free heap memory. * - SleepModeXMC1100 - - | XMC1100 XMC 2GO - | XMC1100 Boot Kit - | XMC1100 H-Bridge 2GO - | XMC1300 Boot Kit - | XMC1400 2GO Kit - | XMC1400 Arduino Kit + - | KIT_XMC_2GO_XMC1100_V1 + | KIT_XMC11_BOOT_001 + | KIT_XMC13_BOOT_001 + | KIT_XMC14_2GO + | KIT_XMC1400_ARDUINO - | Demonstrates the use of an alarm to | wake up an xmc1100 from sleep mode. * - SleepModeXMC4700 - - | XMC4700 Relax Kit + - | KIT_XMC47_RELAX - | Simple Sleep Mode for XMC4700 | Relax Kit V1 demonstrates the use of | an alarm to wake up an XMC4700 from @@ -64,12 +60,10 @@ Examples Supported | mode, LED2 will stop blinking, until | device wakes up. * - StackMemoryMeasurement - - | XMC1100 XMC 2GO - | XMC1100 Boot Kit - | XMC1100 H-Bridge 2GO - | XMC1300 Boot Kit - | XMC4400 Platform 2Go - | XMC4700 Relax Kit + - | KIT_XMC_2GO_XMC1100_V1 + | KIT_XMC11_BOOT_001 + | KIT_XMC13_BOOT_001 + | KIT_XMC47_RELAX - | Simple example to check stack memory | during run time for XMC devices which | demonstrates the ability to check on @@ -88,11 +82,11 @@ Examples Supported - Boards - Description * - DMA_Memory - - | XMC4700 Relax Kit + - | KIT_XMC47_RELAX - | Demonstrates how to setup an DMA, to transfer | data between two places in memory. * - DMA_UART - - | XMC4700 Relax Kit + - | KIT_XMC47_RELAX - | Demonstrates how to setup an DMA, to transfer | data between two places in memory. @@ -108,11 +102,11 @@ RTC Library - Boards - Description * - AlarmRTC - - XMC4700 Relax Kit + - KIT_XMC47_RELAX - | Demonstrates how to set an RTC alarm for the - | XMC4700 Relax Kit V1. + | KIT_XMC47_RELAX. * - SimpleRTC - - XMC4700 Relax Kit + - KIT_XMC47_RELAX - Demonstrates the use of the RTC library for the XMC4700. @@ -127,14 +121,12 @@ SPI Library - Description * - | SPI_MOSI_to_MISO | _SameDevice - - | XMC1100 XMC 2GO - | XMC1100 Boot Kit - | XMC1100 H-Bridge 2GO - | XMC1300 Boot Kit - | XMC1400 2GO Kit - | XMC1400 Arduino Kit - | XMC4400 Platform 2Go - | XMC4700 Relax Kit + - | KIT_XMC_2GO_XMC1100_V1 + | KIT_XMC11_BOOT_001 + | KIT_XMC13_BOOT_001 + | KIT_XMC14_2GO + | KIT_XMC1400_ARDUINO + | KIT_XMC47_RELAX - | SPI example which communicates between the | MOSI and MISO pin of the same board. Connect | the MOSI pin to the MOSI pin as hardware @@ -151,14 +143,12 @@ Wire Library - Boards - Description * - master_reader - - | XMC1100 XMC 2GO - | XMC1100 Boot Kit - | XMC1100 H-Bridge 2GO - | XMC1300 Boot Kit - | XMC1400 2GO Kit - | XMC1400 Arduino Kit - | XMC4400 Platform 2Go - | XMC4700 Relax Kit + - | KIT_XMC_2GO_XMC1100_V1 + | KIT_XMC11_BOOT_001 + | KIT_XMC13_BOOT_001 + | KIT_XMC14_2GO + | KIT_XMC1400_ARDUINO + | KIT_XMC47_RELAX - | Demonstrates use of the Wire library. Reads data | from an I2C/TWI slave device. Refer to the "Wire Slave | Sender" example for use with this. Then it @@ -167,14 +157,12 @@ Wire Library | pins of one board to the SDA and SCL pin of the | other board. * - master_writer - - | XMC1100 XMC 2GO - | XMC1100 Boot Kit - | XMC1100 H-Bridge 2GO - | XMC1300 Boot Kit - | XMC1400 2GO Kit - | XMC1400 Arduino Kit - | XMC4400 Platform 2Go - | XMC4700 Relax Kit + - | KIT_XMC_2GO_XMC1100_V1 + | KIT_XMC11_BOOT_001 + | KIT_XMC13_BOOT_001 + | KIT_XMC14_2GO + | KIT_XMC1400_ARDUINO + | KIT_XMC47_RELAX - | Demonstrates use of the Wire library. Writes data to | an I2C/TWI slave device. Refer to the "Wire Slave | Receiver" example for use with this. Then it @@ -183,14 +171,12 @@ Wire Library | pins of one board to the SDA and SCL pin of the | other board. * - slave_receiver - - | XMC1100 XMC 2GO - | XMC1100 Boot Kit - | XMC1100 H-Bridge 2GO - | XMC1300 Boot Kit - | XMC1400 2GO Kit - | XMC1400 Arduino Kit - | XMC4400 Platform 2Go - | XMC4700 Relax Kit + - | KIT_XMC_2GO_XMC1100_V1 + | KIT_XMC11_BOOT_001 + | KIT_XMC13_BOOT_001 + | KIT_XMC14_2GO + | KIT_XMC1400_ARDUINO + | KIT_XMC47_RELAX - | Demonstrates use of the Wire library. Receives data as | an I2C/TWI slave device. Refer to the "Wire Slave | Writer" example for use with this. Then it @@ -199,14 +185,12 @@ Wire Library | pins of one board to the SDA and SCL pin of the | other board. * - slave_sender - - | XMC1100 XMC 2GO - | XMC1100 Boot Kit - | XMC1100 H-Bridge 2GO - | XMC1300 Boot Kit - | XMC1400 2GO Kit - | XMC1400 Arduino Kit - | XMC4400 Platform 2Go - | XMC4700 Relax Kit + - | KIT_XMC_2GO_XMC1100_V1 + | KIT_XMC11_BOOT_001 + | KIT_XMC13_BOOT_001 + | KIT_XMC14_2GO + | KIT_XMC1400_ARDUINO + | KIT_XMC47_RELAX - | Demonstrates use of the Wire library. Receives data as | an I2C/TWI slave device. Refer to the "Wire Master | Reader" example for use with this. Then it @@ -219,7 +203,7 @@ Wire Library I2S Library ^^^^^^^^^^^ -This library has been tested with the IM69D130 Microphone Shield2Go with both XMC4700 Relax Kit and XMC1100 XMC2Go. +This library has been tested with the IM69D130 Microphone Shield2Go with both KIT_XMC47_RELAX and KIT_XMC_2GO_XMC1100_V1. Please refer to the `README.md `_ of the I2S library for pin connections. @@ -245,7 +229,7 @@ This library provides support for the CAN protocol. For further details, please - Boards - Description * - CANSender - - XMC1400 2GO + - KIT_XMC14_2GO - | This example demonstrates how to send a CAN message. | It supports two different message/frame formats: | standard and extended. The CAN standard frame uses @@ -253,7 +237,7 @@ This library provides support for the CAN protocol. For further details, please | uses a 29-bit identifier. * - | CANReceiver/ | CANReceiverCallback - - XMC1400 2GO + - KIT_XMC14_2GO - | This example demonstrates how to receive a CAN | message. There are two methods for receiving messages: | the default method runs a loop that continuously @@ -264,7 +248,7 @@ This library provides support for the CAN protocol. For further details, please | be received. Additionally, messages can be filtered for | specific IDs using the ``filter()`` function. * - CANLoopBack - - XMC1400 2GO + - KIT_XMC14_2GO - | This example demonstrates the loopback mode of CAN. | In this mode, the CAN transmitter is internally connected | to its receiver, allowing the message to be sent and diff --git a/docs/development-instructions.rst b/docs/development-instructions.rst index bce7eeff..7046757c 100644 --- a/docs/development-instructions.rst +++ b/docs/development-instructions.rst @@ -20,6 +20,7 @@ Environment Setup * Install `Arduino IDE (2.0 or higher) `_ * Or Install `Arduino CLI (1.0.0 or higher) `_ * Python + * Follow the :doc:`installation-instructions` #. Create a ``/hardware/arduino-git`` folder. Where ```` is the location of your Arduino sketchbook. The ```` default is OS-dependent: @@ -113,7 +114,7 @@ If you are developing a new built-in library, please refer to ``libraries\CAN\Ma Automated Build Checks ^^^^^^^^^^^^^^^^^^^^^^^^ Currently a GitHub Action workflow is used for automatic compilation checking. -Workflows are defined `here `_. +Workflows are defined `here `_. Validation Test ^^^^^^^^^^^^^^^^ @@ -123,9 +124,32 @@ Tests are located in ``tests/arduino-core-tests`` and included as submodule in t If you need to run these tests locally, you'll also need to download `GNU Make `_ . +Debugging (VS Code) +^^^^^^^^^^^^^^^^^^^^ +Debugging support described here is for Visual Studio Code. The Arduino IDE already provides a built-in debugger for supported boards. + +#. Install the `Cortex-Debug` extension in VS Code. +#. Copy the `task_xmc.json` file from `tools/vscode-profile` to the `.vscode` directory and rename to `tasks.json` in your project root. +#. In VS Code, run the task: **Generate launch.json for debug (XMC)**. +#. Required parameters for this task: + * **fqbn**: Fully Qualified Board Name (e.g., `arduino-git:xmc:kit_xmc47_relax`) + * **build path**: Directory where the `.elf` file will be placed + * **example path**: Path to the sketch (`.ino` file) to debug (for arduino-core-tests make sure it has been built at least once to generate the required build.ino) +#. Optional parameters: + * **boards.txt path**: Path to a custom `boards.txt` file + * **gdb path**: Path to a custom GDB executable + +Refer to the documentation of your chosen debugger and scripts in the `tools/` folder for more details. + +.. note:: + If you encounter an error indicating that ``libncurses.so.5`` or a similar library cannot be found, please search online and install the appropriate package for your environment. + Release --------- -Add a git tag in the format `Vx.y.z` (e.g. V3.3.0) to trigger the release process. +Add a git tag in the format `x.y.z` (e.g. 3.3.0) to trigger the release process. + +For detailed steps on how to release the package, refer to the +`Release Process Documentation `_. Creating and Maintaining Third Party Libraries diff --git a/docs/hw-platforms.rst b/docs/hw-platforms.rst index 24b394e7..e8e2f8a5 100644 --- a/docs/hw-platforms.rst +++ b/docs/hw-platforms.rst @@ -26,35 +26,24 @@ The following XMC microcontroller boards are supported by XMC for Arduino: - :ref:`KIT_XMC1400_ARDUINO` - XMC1402 - Arduino Uno - * - .. image:: img/KIT_XMC_PLT2GO_XMC4200.jpg - - :ref:`KIT_XMC_PLT2GO_XMC4200` - - XMC4200 - - Arduino Uno, Shield2Go, mikroBUS - * - .. image:: img/KIT_XMC_PLT2GO_XMC4400.jpg - - :ref:`KIT_XMC_PLT2GO_XMC4400` - - XMC4400 - - Arduino Uno, Shield2Go, mikroBUS - * - .. image:: img/KIT_XMC47_RELAX_5V_AD_V1.jpg - - :ref:`KIT_XMC47_RELAX_5V_AD_V1` + * - .. image:: img/KIT_XMC47_RELAX.jpg + - :ref:`KIT_XMC47_RELAX` variants - XMC4700 - Arduino Uno .. note:: - For all Kit 2Go or MS 2Go sensor boards please select ``XMC1100 XMC2Go`` in the Arduino IDE. + For all Kit 2Go or MS 2Go sensor boards please select ``KIT_XMC_2GO_XMC1100_V1`` in the Arduino IDE. .. _KIT_XMC11_BOOT_001: KIT_XMC11_BOOT_001 ------------------ -* Name in Arduino IDE: ``XMC1100 Boot Kit`` -* `Product Page `__ - .. image:: img/KIT_XMC11_BOOT_001.jpg :width: 400 -The XMC1100 Boot Kit board consists of a XMC1100 microcontroller with a debugger implemented by a XMC4200 microcontroller. -The board shares the same power supply and board shape as other shields for Arduino. +The `KIT_XMC11_BOOT_001 `__ board consists of a XMC1100 microcontroller with a debugger implemented by a XMC4200 microcontroller. +The board shares the same power supply and board shape as other boards for Arduino. Pinout Diagram ^^^^^^^^^^^^^^ @@ -71,13 +60,20 @@ nor share the same pins/resources. This is different from the original Arduino U KIT_XMC13_BOOT_001 ------------------ -* Name in Arduino IDE: ``XMC1300 Boot Kit`` -* `Product Page `__ - .. image:: img/KIT_XMC13_BOOT_001.jpg :width: 400 -XMC1302 Microcontroller in TSSOP-38 with 200KB Flash and full peripheral set of XMC1300 series. +The `KIT_XMC13_BOOT_001 `__ features a XMC1302 microcontroller in TSSOP-38 with 200KB flash and detachable SEGGER J-Link. + +Known Issues +^^^^^^^^^^^^ + +**Serial Communication Garbled Output** + +Some board versions may display garbled characters in serial output. To resolve this: + +1. **Update J-Link firmware** to the latest version. `J-Link-Firmware `__ +2. **Reduce baud rate** if your application allows (e.g., from 115200 to 9600) ----------------------------------------------------------------------- @@ -86,13 +82,10 @@ XMC1302 Microcontroller in TSSOP-38 with 200KB Flash and full peripheral set of KIT_XMC14_2GO ------------- -* Name in Arduino IDE: ``XMC1400 XMC2GO`` -* `Product Page `__ - .. image:: img/KIT_XMC14_2GO.png :width: 400 -The XMC1400 Kit 2Go provides an easy way to evaluate almost all capabilities of the XMC1400 microcontroller. +The `KIT_XMC14_2GO `__ provides an easy way to evaluate almost all capabilities of the XMC1400 microcontroller. The kit is powered via USB, interfaces to other Infineon sensor boards and provides multiple interfaces including a CAN bus. The software development is supported via ModusToolbox™ and the Arduino IDE. @@ -109,19 +102,16 @@ Pinout Diagram KIT_XMC1400_ARDUINO ------------------- -* Name in Arduino IDE: ``XMC1400 Kit for Arduino`` -* `Product Page `__ - .. image:: img/KIT_XMC1400_ARDUINO.jpg :width: 400 -The XMC1400 Kit for Arduino consists of a XMC1400 microcontroller with a debugger implemented by a XMC4200 microcontroller. -The board shares the same power supply and board shape as other shields for Arduino. +The `KIT_XMC1400_ARDUINO `__ consists of a XMC1400 microcontroller with a debugger implemented by a XMC4200 microcontroller. +The board shares the same power supply and board shape as other boards for Arduino. Pinout Diagram ^^^^^^^^^^^^^^ Please note that pins ``P1.4`` and ``P0.5`` are swapped on the board and are not consistent with the silkscreen. As a result, interrupt 0 ``INT0`` -occurs as Arduino pin ``3`` and interrupt 1 ``INT1`` is located at Arduino pin ``25``. This is different from the original +occurs as Arduino pin ``25`` and interrupt 1 ``INT1`` is located at Arduino pin ``3``. This is different from the original Arduino UNO Rev3 implementation. Please look at the pinout diagram for more information. .. image:: img/KIT_XMC1400_ARDUINO_pinout.png @@ -129,79 +119,28 @@ Arduino UNO Rev3 implementation. Please look at the pinout diagram for more info ----------------------------------------------------------------------- -.. _KIT_XMC_PLT2GO_XMC4200: - -KIT_XMC_PLT2GO_XMC4200 ----------------------- - -* Name in Arduino IDE: ``XMC4200 Platform 2GO`` -* `Product Page `__ - -.. image:: img/KIT_XMC_PLT2GO_XMC4200.jpg - :width: 400 - -The XMC4200 Platform 2Go evaluation board consists of a XMC4200 microcontroller with a debugger implemented by a XMC4200 microcontroller. -Please note that there exist versions with 5V and 3.3V. Please be careful which version you have and use with your respective shields. -The one described here is the 5V version as this one is compatible with Arduino shields designed for 5V systems. -This kit is equipped with an ARM® Cortex®-M4 based XMC4200 microcontroller with on-board debugger, Ethernet, CAN and footprints for Arduino, -MikroBUS and Shield2Go form factors. - -Pinout Diagram -^^^^^^^^^^^^^^ -.. image:: img/KIT_XMC_PLT2GO_XMC4200_pinout.png - :width: 700 - -Please note that Arduino pin number ``15`` & ``21`` (``SCL`` & ``A5``) and Arduino pin number ``14`` & ``20`` (``SDA`` & ``A4``) are connected with each other -on the board itself. If you want to use them check out the subsection :ref:`connected_pins`. - ------------------------------------------------------------------------ - -.. _KIT_XMC_PLT2GO_XMC4400: - -KIT_XMC_PLT2GO_XMC4400 ----------------------- - -* Name in Arduino IDE: ``XMC4400 Platform 2GO`` -* `Product Page `__ - -.. image:: img/KIT_XMC_PLT2GO_XMC4400.jpg - :width: 400 - -The XMC4400 Platform 2Go evaluation board consists of a XMC4400 microcontroller with a debugger implemented by a XMC4200 microcontroller. -Please note that there exist versions with 5V and 3.3V. Please be careful which version you have and use with your respective shields. -The one described here is the 5V version as this one is compatible with Arduino shields designed for 5V systems. -This kit is equipped with an ARM® Cortex®-M4 based XMC4400 microcontroller with on-board debugger, Ethernet, CAN and footprints for Arduino, -MikroBUS and Shield2Go form factors. - -Pinout Diagram -^^^^^^^^^^^^^^ -.. image:: img/KIT_XMC_PLT2GO_XMC4400_pinout.png - :width: 700 - -Please note that Arduino pin number ``15`` & ``21`` (``SCL`` & ``A5``) and Arduino pin number ``14`` & ``20`` (``SDA`` & ``A4``) are connected with each other -on the board itself. If you want to use them check out the subsection :ref:`connected_pins`. - ------------------------------------------------------------------------ - -.. _KIT_XMC47_RELAX_5V_AD_V1: +.. _KIT_XMC47_RELAX: -KIT_XMC47_RELAX_5V_AD_V1 +KIT_XMC47_RELAX ------------------------ -* Name in Arduino IDE: ``XMC4700 Relax Kit`` -* `Product Page `__ +Supported Variants +^^^^^^^^^^^^^^^^^^ +* `KIT_XMC47_RELAX_V1 `__ +* `KIT_XMC47_RELAX_LITE_V1 `__ +* `KIT_XMC47_RELAX_5V_AD_V1 `__ -.. image:: img/KIT_XMC47_RELAX_5V_AD_V1.jpg +.. image:: img/KIT_XMC47_RELAX.jpg :width: 400 -The XMC4700 Relax Kit board consists of a XMC4700 microcontroller with a debugger implemented by a XMC4200 microcontroller. +The KIT_XMC47_RELAX board variants consists of a XMC4700 microcontroller with a debugger implemented by a XMC4200 microcontroller. Please note that there exist versions with 5V and 3.3V. Please be careful which version you have and use with your respective shields. The one described here is the 5V version as this one is compatible with Arduino shields designed for 5V systems. Pinout Diagram ^^^^^^^^^^^^^^ -.. image:: img/KIT_XMC47_RELAX_5V_AD_V1_pinout.png +.. image:: img/KIT_XMC47_RELAX_pinout.png :width: 700 Please note that Arduino pin number ``15`` & ``21`` (``SCL`` & ``A5``) and Arduino pin number ``14`` & ``20`` (``SDA`` & ``A4``) are connected with each other @@ -212,13 +151,12 @@ on the board itself. If you want to use them check out the subsection :ref:`conn .. _connected_pins: Connected I2S and Analog pins ------------------------------ +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -For the ``KIT_XMC_PLT2GO_XMC4200``, ``KIT_XMC_PLT2GO_XMC4400`` and ``KIT_XMC47_RELAX_5V_AD_V1`` the Arduino pin number ``15`` & ``21`` (``SCL`` & ``A5``) and Arduino +For the ``KIT_XMC47_RELAX`` the Arduino pin number ``15`` & ``21`` (``SCL`` & ``A5``) and Arduino pin number ``14`` & ``20`` (``SDA`` & ``A4``) are connected with each other on the board itself. Although they are different physical pins of the microcontroller, they are connected with each other on the board to comply with the original Arduino UNO Rev3 pin connections. This influences analog measurements on -``A4`` and ``A5`` if you are using I2C simultaneously. Details of the connection can also be found in the schematics in the user manual of the board here: -`KIT_XMC_PLT2GO_XMC4200 user manual`_, `KIT_XMC_PLT2GO_XMC4400 user manual`_ and `KIT_XMC47_RELAX_5V_AD_V1 user manual`_. +``A4`` and ``A5`` if you are using I2C simultaneously. Details of the connection can also be found in the schematics in the user manual of the board here: `KIT_XMC47_RELAX user manual`_. The user manual shows on: @@ -232,24 +170,12 @@ but the open drain method is preferable. These functions are using the pin mode You can also cut the physical connection on the board itself. -For ``KIT_XMC_PLT2GO_XMC4200`` remove the resistor ``R104`` and ``R105``: - -.. image:: img/kit_xmc_plt2go_xmc4200_remove_resistors.png - :width: 300 - -For the ``KIT_XMC_PLT2GO_XMC4400`` by cutting the marked blue routes on the back side of the PCB: - -.. image:: img/kit_xmc_plt2go_xmc4400_cut_routes.png - :width: 300 - -For the ``KIT_XMC47_RELAX_5V_AD_V1`` cut the blue routes on the back side of the PCB as indicated here: +For the ``KIT_XMC47_RELAX`` cut the blue routes on the back side of the PCB as indicated here: .. image:: img/kit_xmc47_relax_cut_routes.jpg :width: 300 -.. _KIT_XMC_PLT2GO_XMC4200 user manual: https://www.infineon.com/dgdl/Infineon-XMC4200_Platform2Go-UserManual-v01_00-EN.pdf?fileId=5546d4626f229553016f8fca76c12c96 -.. _KIT_XMC_PLT2GO_XMC4400 user manual: https://www.infineon.com/dgdl/Infineon-XMC4400_Platform2Go-UserManual-v01_00-EN.pdf?fileId=5546d4626f229553016f8fc159482c94 -.. _KIT_XMC47_RELAX_5V_AD_V1 user manual: https://www.infineon.com/dgdl/Infineon-Board_User_Manual_XMC4700_XMC4800_Relax_Kit_Series-UM-v01_02-EN.pdf?fileId=5546d46250cc1fdf01513f8e052d07fc +.. _KIT_XMC47_RELAX user manual: https://www.infineon.com/dgdl/Infineon-Board_User_Manual_XMC4700_XMC4800_Relax_Kit_Series-UM-v01_02-EN.pdf?fileId=5546d46250cc1fdf01513f8e052d07fc ----------------------------------------------------------------------- @@ -275,10 +201,19 @@ Legacy Microcontroller Boards - :ref:`XMC1300 Sense2GoL` - XMC1300 - Proprietary + * - v3.x + - :ref:`KIT_XMC_PLT2GO_XMC4200` + - XMC4200 + - Arduino Uno, Shield2Go, mikroBUS + * - v3.x + - :ref:`KIT_XMC_PLT2GO_XMC4400` + - XMC4400 + - Arduino Uno, Shield2Go, mikroBUS * - v1.7.0 - :ref:`XMC4700 Radar Baseboard` - XMC4700 - Proprietary + .. _KIT_XMC_2GO_XMC1100_V1: @@ -286,7 +221,6 @@ KIT_XMC_2GO_XMC1100_V1 ---------------------- * Replaced by :ref:`KIT_XMC14_2GO` -* Name in Arduino IDE: ``XMC1100 XMC2Go`` The XMC1100 2Go board consists of a XMC1100 microcontroller with a debugger implemented by a XMC4200 microcontroller. @@ -328,6 +262,60 @@ and XMC1300 32-bit ARM® Cortex®-M0 MCU series. ----------------------------------------------------------------------- +.. _KIT_XMC_PLT2GO_XMC4200: + +KIT_XMC_PLT2GO_XMC4200 +---------------------- + +* Name in Arduino IDE: ``XMC4200 Platform 2GO`` +* `Product Page `__ + +.. image:: img/KIT_XMC_PLT2GO_XMC4200.jpg + :width: 400 + +The XMC4200 Platform 2Go evaluation board consists of a XMC4200 microcontroller with a debugger implemented by a XMC4200 microcontroller. +Please note that there exist versions with 5V and 3.3V. Please be careful which version you have and use with your respective shields. +The one described here is the 5V version as this one is compatible with Arduino shields designed for 5V systems. +This kit is equipped with an ARM® Cortex®-M4 based XMC4200 microcontroller with on-board debugger, Ethernet, CAN and footprints for Arduino, +MikroBUS and Shield2Go form factors. + +Pinout Diagram +^^^^^^^^^^^^^^ +.. image:: img/KIT_XMC_PLT2GO_XMC4200_pinout.png + :width: 700 + +Please note that Arduino pin number ``15`` & ``21`` (``SCL`` & ``A5``) and Arduino pin number ``14`` & ``20`` (``SDA`` & ``A4``) are connected with each other +on the board itself. If you want to use them check out the subsection :ref:`connected_pins`. + +----------------------------------------------------------------------- + +.. _KIT_XMC_PLT2GO_XMC4400: + +KIT_XMC_PLT2GO_XMC4400 +---------------------- + +* Name in Arduino IDE: ``XMC4400 Platform 2GO`` +* `Product Page `__ + +.. image:: img/KIT_XMC_PLT2GO_XMC4400.jpg + :width: 400 + +The XMC4400 Platform 2Go evaluation board consists of a XMC4400 microcontroller with a debugger implemented by a XMC4200 microcontroller. +Please note that there exist versions with 5V and 3.3V. Please be careful which version you have and use with your respective shields. +The one described here is the 5V version as this one is compatible with Arduino shields designed for 5V systems. +This kit is equipped with an ARM® Cortex®-M4 based XMC4400 microcontroller with on-board debugger, Ethernet, CAN and footprints for Arduino, +MikroBUS and Shield2Go form factors. + +Pinout Diagram +^^^^^^^^^^^^^^ +.. image:: img/KIT_XMC_PLT2GO_XMC4400_pinout.png + :width: 700 + +Please note that Arduino pin number ``15`` & ``21`` (``SCL`` & ``A5``) and Arduino pin number ``14`` & ``20`` (``SDA`` & ``A4``) are connected with each other +on the board itself. If you want to use them check out the subsection :ref:`connected_pins`. + +----------------------------------------------------------------------- + .. _XMC4700 Radar Baseboard: XMC4700 Radar Baseboard diff --git a/docs/img/KIT_XMC1400_ARDUINO_pinout.png b/docs/img/KIT_XMC1400_ARDUINO_pinout.png index 8041c38f..9f5f5af7 100644 Binary files a/docs/img/KIT_XMC1400_ARDUINO_pinout.png and b/docs/img/KIT_XMC1400_ARDUINO_pinout.png differ diff --git a/docs/img/KIT_XMC47_RELAX_5V_AD_V1.jpg b/docs/img/KIT_XMC47_RELAX.jpg similarity index 100% rename from docs/img/KIT_XMC47_RELAX_5V_AD_V1.jpg rename to docs/img/KIT_XMC47_RELAX.jpg diff --git a/docs/img/KIT_XMC47_RELAX_5V_AD_V1_pinout.png b/docs/img/KIT_XMC47_RELAX_pinout.png similarity index 100% rename from docs/img/KIT_XMC47_RELAX_5V_AD_V1_pinout.png rename to docs/img/KIT_XMC47_RELAX_pinout.png diff --git a/docs/index.rst b/docs/index.rst index e1077c85..0f6963b5 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -9,7 +9,7 @@ Welcome to Infineon's XMC Microcontroller Boards for Arduino! .. image:: img/KIT_XMC11_BOOT_001.jpg :width: 200 -.. image:: img/KIT_XMC47_RELAX_5V_AD_V1.jpg +.. image:: img/KIT_XMC47_RELAX.jpg :width: 200 The XMC microcontroller family from Infineon offers a powerful and versatile platform for embedded system development. diff --git a/docs/installation-instructions.rst b/docs/installation-instructions.rst index 75bcfec7..5f414391 100644 --- a/docs/installation-instructions.rst +++ b/docs/installation-instructions.rst @@ -53,7 +53,7 @@ Paste the following URL into the *Additional boards manager URLs* input field un :: - https://github.com/Infineon/XMC-for-Arduino/releases/latest/download/package_infineon_index.json + https://github.com/Infineon/XMC-for-Arduino/releases/latest/download/package_xmc_index.json .. image:: img/arduino_ide_preferences_menu.png :width: 600 diff --git a/docs/requirements.txt b/docs/requirements.txt index 779f6572..74ecfd94 100644 --- a/docs/requirements.txt +++ b/docs/requirements.txt @@ -1,7 +1,7 @@ # This is a list of python packages used to generate documentation. This file is used with pip: # pip install --user -r requirements.txt # -sphinx>=7.2.6 +sphinx>=7.2.6,<9.0.0 sphinx-tabs sphinxemoji sphinx-rtd-theme diff --git a/extras/arduino-core-api b/extras/arduino-core-api new file mode 160000 index 00000000..cd91833d --- /dev/null +++ b/extras/arduino-core-api @@ -0,0 +1 @@ +Subproject commit cd91833d90b4fe50e428021ba5051e2b7ceafc84 diff --git a/extras/arduino-core-tests b/extras/arduino-core-tests new file mode 160000 index 00000000..1db61ef0 --- /dev/null +++ b/extras/arduino-core-tests @@ -0,0 +1 @@ +Subproject commit 1db61ef0f25234b4efbc3d6fb8c8aa7027013089 diff --git a/extras/arduino-devops b/extras/arduino-devops new file mode 160000 index 00000000..b086dd5a --- /dev/null +++ b/extras/arduino-devops @@ -0,0 +1 @@ +Subproject commit b086dd5a1d1ef117677cb292b6b0821628eed7de diff --git a/extras/arduino-examples b/extras/arduino-examples new file mode 160000 index 00000000..f2bf63b4 --- /dev/null +++ b/extras/arduino-examples @@ -0,0 +1 @@ +Subproject commit f2bf63b4499fdd984891b6dff074732f3e9effaf diff --git a/extras/makers-devops b/extras/makers-devops new file mode 160000 index 00000000..3a753bcd --- /dev/null +++ b/extras/makers-devops @@ -0,0 +1 @@ +Subproject commit 3a753bcd52246396b2c51c3392c13deb42f0216e diff --git a/libraries/CAN/README.md b/libraries/CAN/README.md index a77d8d53..e6bebd8d 100644 --- a/libraries/CAN/README.md +++ b/libraries/CAN/README.md @@ -4,15 +4,18 @@ Based on [Arduino CAN library](https://www.arduino.cc/reference/en/libraries/can # Hardware Setup -XMC boards with CAN support (CAN transceiver on board and CAN controller module): XMC4200 Platform2GO, XMC4400 Platform2GO, XMC4700 Relax Kit and XMC1400 XMC2GO. +XMC boards with CAN support (CAN transceiver on board and CAN controller module): KIT_XMC47_RELAX and KIT_XMC14_2GO. -:warning: There is a 120 ohm terminal resistor on the XMC4200 Platform2GO and XMC1400 XMC2Go boards, not on the XMC4400 Platform2GO and XMC4700 Relax Kit. Please remove or add resistors as needed. +| Board Name | Onboard CAN | Termination Resistor | +|--------------------------|-------------|-----------------------| +| KIT_XMC14_2GO | Yes | Yes (120 ohm) | +| KIT_XMC47_RELAX | Yes | No | All CAN nodes should be connected using the (twisted) pair cable for the CAN_H and CAN_L # Software Usage -There are [examples](libraries/CAN/examples). See the API definition below for more details. +There are [examples](examples). See the API definition below for more details. # CAN API @@ -46,7 +49,7 @@ Here the API definition is based on: ## :warning: XMC specification -Due to the different behavior of xmc4 series and xmc1 series, the library and provided examples was tested primarily on **xmc1400 2go**. +Due to the different behavior of xmc4000 series and xmc1000 series, the library and provided examples was tested primarily on **KIT_XMC14_2GO**. The known difference is that the XMC4 is unable to receive CAN messages for all IDs. Therefore, it is necessary to define the device ID using the following function: diff --git a/libraries/DMA/examples/DMA_Memory/DMA_Memory.ino b/libraries/DMA/examples/DMA_Memory/DMA_Memory.ino index 9f79133c..15997002 100644 --- a/libraries/DMA/examples/DMA_Memory/DMA_Memory.ino +++ b/libraries/DMA/examples/DMA_Memory/DMA_Memory.ino @@ -1,5 +1,5 @@ /* - * Simple DMA example for XMC4700 Relax Kit V1 + * Simple DMA example for KIT_XMC47_RELAX * Demonstrates how to setup an DMA, to transfer data between two places in memory. * Prints the message in Serial port. */ diff --git a/libraries/DMA/examples/DMA_UART/DMA_UART.ino b/libraries/DMA/examples/DMA_UART/DMA_UART.ino index 39618d0c..4e8056e6 100644 --- a/libraries/DMA/examples/DMA_UART/DMA_UART.ino +++ b/libraries/DMA/examples/DMA_UART/DMA_UART.ino @@ -1,5 +1,5 @@ /* - * Simple DMA example for XMC4700 Relax Kit V1 + * Simple DMA example for KIT_XMC47_RELAX * Demonstrates how to setup an DMA, between memory and UART module. * Prints the message in Serial port. */ diff --git a/libraries/DMA/src/DMA.cpp b/libraries/DMA/src/DMA.cpp index c7602c12..4db1e8b3 100644 --- a/libraries/DMA/src/DMA.cpp +++ b/libraries/DMA/src/DMA.cpp @@ -35,7 +35,7 @@ #include #include "DMA.h" -static interrupt_cb_t event_handler = NULL; +static voidFuncPtr event_handler = NULL; event_t event; void DMA::beginDMA(XMC_DMA_t *const dma) { @@ -217,7 +217,7 @@ void DMA::configDMA_P2P(XMC_DMA_t *const dma, void DMA::attachDMAInterrupt(XMC_DMA_t *const dma, uint8_t channel, - interrupt_cb_t _event_handler, + voidFuncPtr _event_handler, event_t _event) { event = _event; XMC_DMA_CH_EnableEvent(dma, channel, event); diff --git a/libraries/DMA/src/DMA.h b/libraries/DMA/src/DMA.h index 3eb31e8e..c57d9312 100644 --- a/libraries/DMA/src/DMA.h +++ b/libraries/DMA/src/DMA.h @@ -156,7 +156,7 @@ class DMA { // Interrupt configuration void attachDMAInterrupt(XMC_DMA_t *const dma, uint8_t channel, - interrupt_cb_t _event_handler, + voidFuncPtr _event_handler, event_t event); void detachDMAInterrupt(XMC_DMA_t *const dma, uint8_t channel, XMC_DMA_CH_EVENT_t event); diff --git a/libraries/DeviceControlXMC/examples/SleepModeXMC4700/SleepModeXMC4700.ino b/libraries/DeviceControlXMC/examples/SleepModeXMC4700/SleepModeXMC4700.ino index b76c63d5..96f4391d 100644 --- a/libraries/DeviceControlXMC/examples/SleepModeXMC4700/SleepModeXMC4700.ino +++ b/libraries/DeviceControlXMC/examples/SleepModeXMC4700/SleepModeXMC4700.ino @@ -1,5 +1,5 @@ /* - Simple Sleep Mode for XMC4700 Relax Kit V1 + Simple Sleep Mode for KIT_XMC47_RELAX Demonstrates the ability to control peripherals on sleep mode. LED2 will blink fast on active mode. If CCU4 is ON in sleep mode, LED2 will blink slower (because of slower clock) while in sleep mode. If CCU is OFF in sleep mode, LED2 will stop blinking, until device wakes up. diff --git a/libraries/I2S/README.md b/libraries/I2S/README.md index 404c75c6..0e01a22a 100644 --- a/libraries/I2S/README.md +++ b/libraries/I2S/README.md @@ -6,9 +6,9 @@ the master device and read audio input from another device such as a microphone. Be aware that only reading is possible for the time being - no I2S output is supported. ## Wiring -The library has been tested with the XMC4700 Relax Kit, XMC1100 XMC 2Go, and XMC1100 Boot Kit in combination with the IM69D130 Microphone Shield2Go. +The library has been tested with the KIT_XMC47_RELAX, XMC1100 XMC 2Go, and KIT_XMC11_BOOT_001 in combination with the IM69D130 Microphone Shield2Go. -* For the XMC4700 Relax Kit, following ports/pins should be connected: +* For the KIT_XMC47_RELAX, following ports/pins should be connected: - BCLK -- P3.10 - DATA -- P3.7 - CLK -- P3.9 @@ -26,14 +26,14 @@ The library has been tested with the XMC4700 Relax Kit, XMC1100 XMC 2Go, and XMC `No level shifting needed as the XMC 2Go board runs at 3.3 V.` -* For the XMC1100 Boot Kit board the ports/pins connection should be as follows: +* For the KIT_XMC11_BOOT_001 board the ports/pins connection should be as follows: - BCLK -- P0.9 - DATA -- P1.0 - CLK -- P0.7 - GND -- GND (VSS) - 3.3V -- 3.3V (VDD) -`Ensure that level shifting is in place as the microphone board has 3.3 V logic level, XMC1100 Boot Kit has 5 V by default.` +`Ensure that level shifting is in place as the microphone board has 3.3 V logic level, KIT_XMC11_BOOT_001 has 5 V by default.` This configuration is defined in the respective board configuration files `pins_arduino.h`. @@ -66,7 +66,7 @@ Please refer to the data sheet of your specific microphone for the sampling rate If you are using XMC1000 family boards, the recommended sampling rate is 12 kHz as higher values might interfere with the microcontroller speed. Since both `Serial` and `I2S` use USIC interrupts, there could be a problem with processing remaining code as the processor could get locked out via interrupts. -However, if you are using an XMC4000 board such as a XMC4700 Relax Kit, you shouldn't have to worry about these issues in particular. +However, if you are using an XMC4000 board such as a KIT_XMC47_RELAX, you shouldn't have to worry about these issues in particular. ### Data delay Sometimes, it also makes sense to adjust the data delay, which is the delay between a changing WA/LRCL edge and the start of a sample depending on the microphone of your choice. Please be aware that there are different `I2S.begin()` functions which allow to set the parameters very precisely. Have a look in the I2S.h file for more information. diff --git a/libraries/I2S/src/I2S.cpp b/libraries/I2S/src/I2S.cpp index 853da3c8..61daf46f 100644 --- a/libraries/I2S/src/I2S.cpp +++ b/libraries/I2S/src/I2S.cpp @@ -415,11 +415,11 @@ void I2SClass::_onSampleReceived() { } extern "C" { -#if defined(XMC4700_Relax_Kit) +#if defined(KIT_XMC47_RELAX) void USIC2_2_IRQHandler() { I2S._onSampleReceived(); } -#elif defined(XMC1100_XMC2GO) || defined(XMC1100_Boot_Kit) +#elif defined(KIT_XMC_2GO_XMC1100_V1) || defined(KIT_XMC11_BOOT_001) void USIC0_2_IRQHandler() { I2S._onSampleReceived(); } -#elif defined(XMC1400_XMC2GO) +#elif defined(KIT_XMC14_2GO) void USIC1_2_IRQHandler() { I2S._onSampleReceived(); } #endif } diff --git a/libraries/I2S/src/I2S.h b/libraries/I2S/src/I2S.h index fda4d4d4..fffdd17f 100644 --- a/libraries/I2S/src/I2S.h +++ b/libraries/I2S/src/I2S.h @@ -37,9 +37,10 @@ *and read audio input from another device such as a microphone. * * @section Wiring - * The library has been tested with the XMC4700 Relax Kit/XMC1100 XMC2G0/XMC1100 Boot Kit. - *interfacing an Infineon IM69D130 Microphone Shield2Go. For the XMC4700 relax board, following - *ports should be connected: LRCL -- 3.10 DOUT -- 3.7 SCLK -- 3.9 GND -- GND 3.3V -- 3.3V + * The library has been tested with the + *KIT_XMC47_RELAX/KIT_XMC_2GO_XMC1100_V1/KIT_XMC11_BOOT_001. interfacing an Infineon + *IM69D130 Microphone Shield2Go. For the XMC4700 relax board, following ports should be connected: + *LRCL -- 3.10 DOUT -- 3.7 SCLK -- 3.9 GND -- GND 3.3V -- 3.3V * * For the XMC1100 boards the connection should be the following: * LRCL -- 0.9 diff --git a/libraries/LED/Readme.md b/libraries/LED/Readme.md index 082ca67b..11d7cd68 100644 --- a/libraries/LED/Readme.md +++ b/libraries/LED/Readme.md @@ -38,16 +38,13 @@ models of board so we end up with | Board | Normal LEDs
ON state | LED_BUILTIN
Separate | LED_BUILTIN
ON state | :---- | :---: | :---: | :---: | - XMC1100 Boot Kit | Low | Yes | High - XMC1100 XMC2GO | High | No | High - XMC1100 XMC H Bridge2GO | High| No | High - XMC1300 Boot Kit | Low | No | Low - XMC1300 Sense2GO | Low| No | Low - XMC1400 Arduino Kit | Low | Yes | High - XMC4200 Platform2Go | High| No | High - XMC4400 Platform2Go | High| No | High - XMC4700 Relax Kit | High| No | High - XMC4700 Relax Kit Lite | High| No | High +| KIT_XMC11_BOOT_001 | Low | Yes | High | +| KIT_XMC_2GO_XMC1100_V1 | High | No | High | +| XMC1100 XMC H Bridge2GO | High | No | High | +| KIT_XMC13_BOOT_001 | Low | No | Low | +| XMC1300 Sense2GO | Low | No | Low | +| KIT_XMC1400_ARDUINO | Low | Yes | High | +| KIT_XMC47_RELAX | High | No | High | ** NOTE ** After Version 2.0 of XMC-for-Arduino, some boards were dropped (e.g. XMC1300 Sense2GO) they are still shown here for those using old versions of XMC-for-Arduino, and for history. diff --git a/libraries/OneWire/Readme.MD b/libraries/OneWire/Readme.MD deleted file mode 100644 index e5436c4a..00000000 --- a/libraries/OneWire/Readme.MD +++ /dev/null @@ -1,6 +0,0 @@ -# OneWire Library for XMC - -OneWire library lets you access 1-wire devices. - -## Additional Information -See also our [documentation](https://xmc-arduino.readthedocs.io/en/latest/builtin-libraries.html). \ No newline at end of file diff --git a/libraries/OneWire/examples/DS18x20_Temperature/DS18x20_Temperature.ino b/libraries/OneWire/examples/DS18x20_Temperature/DS18x20_Temperature.ino deleted file mode 100644 index 68ca1943..00000000 --- a/libraries/OneWire/examples/DS18x20_Temperature/DS18x20_Temperature.ino +++ /dev/null @@ -1,112 +0,0 @@ -#include - -// OneWire DS18S20, DS18B20, DS1822 Temperature Example -// -// http://www.pjrc.com/teensy/td_libs_OneWire.html -// -// The DallasTemperature library can do all this work for you! -// http://milesburton.com/Dallas_Temperature_Control_Library - -OneWire ds(10); // on pin 10 (a 4.7K resistor is necessary) - -void setup(void) { - Serial.begin(9600); -} - -void loop(void) { - byte i; - byte present = 0; - byte type_s; - byte data[12]; - byte addr[8]; - float celsius, fahrenheit; - - if ( !ds.search(addr)) { - Serial.println("No more addresses."); - Serial.println(); - ds.reset_search(); - delay(250); - return; - } - - Serial.print("ROM ="); - for( i = 0; i < 8; i++) { - Serial.write(' '); - Serial.print(addr[i], HEX); - } - - if (OneWire::crc8(addr, 7) != addr[7]) { - Serial.println("CRC is not valid!"); - return; - } - Serial.println(); - - // the first ROM byte indicates which chip - switch (addr[0]) { - case 0x10: - Serial.println(" Chip = DS18S20"); // or old DS1820 - type_s = 1; - break; - case 0x28: - Serial.println(" Chip = DS18B20"); - type_s = 0; - break; - case 0x22: - Serial.println(" Chip = DS1822"); - type_s = 0; - break; - default: - Serial.println("Device is not a DS18x20 family device."); - return; - } - - ds.reset(); - ds.select(addr); - ds.write(0x44, 1); // start conversion, with parasite power on at the end - - delay(1000); // maybe 750ms is enough, maybe not - // we might do a ds.depower() here, but the reset will take care of it. - - present = ds.reset(); - ds.select(addr); - ds.write(0xBE); // Read Scratchpad - - Serial.print(" Data = "); - Serial.print(present, HEX); - Serial.print(" "); - for ( i = 0; i < 9; i++) { // we need 9 bytes - data[i] = ds.read(); - Serial.print(data[i], HEX); - Serial.print(" "); - } - Serial.print(" CRC="); - Serial.print(OneWire::crc8(data, 8), HEX); - Serial.println(); - - // Convert the data to actual temperature - // because the result is a 16 bit signed integer, it should - // be stored to an "int16_t" type, which is always 16 bits - // even when compiled on a 32 bit processor. - int16_t raw = (data[1] << 8) | data[0]; - if (type_s) { - raw = raw << 3; // 9 bit resolution default - if (data[7] == 0x10) { - // "count remain" gives full 12 bit resolution - raw = (raw & 0xFFF0) + 12 - data[6]; - } - } else { - byte cfg = (data[4] & 0x60); - // at lower res, the low bits are undefined, so let's zero them - if (cfg == 0x00) raw = raw & ~7; // 9 bit resolution, 93.75 ms - else if (cfg == 0x20) raw = raw & ~3; // 10 bit res, 187.5 ms - else if (cfg == 0x40) raw = raw & ~1; // 11 bit res, 375 ms - //// default is 12 bit resolution, 750 ms conversion time - } - celsius = (float)raw / 16.0; - fahrenheit = celsius * 1.8 + 32.0; - Serial.print(" Temperature = "); - Serial.print(celsius); - Serial.print(" Celsius, "); - Serial.print(fahrenheit); - Serial.println(" Fahrenheit"); -} diff --git a/libraries/OneWire/examples/DS2408_Switch/DS2408_Switch.ino b/libraries/OneWire/examples/DS2408_Switch/DS2408_Switch.ino deleted file mode 100644 index d171f9ba..00000000 --- a/libraries/OneWire/examples/DS2408_Switch/DS2408_Switch.ino +++ /dev/null @@ -1,77 +0,0 @@ -#include - -/* - * DS2408 8-Channel Addressable Switch - * - * Writte by Glenn Trewitt, glenn at trewitt dot org - * - * Some notes about the DS2408: - * - Unlike most input/output ports, the DS2408 doesn't have mode bits to - * set whether the pins are input or output. If you issue a read command, - * they're inputs. If you write to them, they're outputs. - * - For reading from a switch, you should use 10K pull-up resisters. - */ - -void PrintBytes(uint8_t* addr, uint8_t count, bool newline=0) { - for (uint8_t i = 0; i < count; i++) { - Serial.print(addr[i]>>4, HEX); - Serial.print(addr[i]&0x0f, HEX); - } - if (newline) - Serial.println(); -} - -void ReadAndReport(OneWire* net, uint8_t* addr) { - Serial.print(" Reading DS2408 "); - PrintBytes(addr, 8); - Serial.println(); - - uint8_t buf[13]; // Put everything in the buffer so we can compute CRC easily. - buf[0] = 0xF0; // Read PIO Registers - buf[1] = 0x88; // LSB address - buf[2] = 0x00; // MSB address - net->write_bytes(buf, 3); - net->read_bytes(buf+3, 10); // 3 cmd bytes, 6 data bytes, 2 0xFF, 2 CRC16 - net->reset(); - - if (!OneWire::check_crc16(buf, 11, &buf[11])) { - Serial.print("CRC failure in DS2408 at "); - PrintBytes(addr, 8, true); - return; - } - Serial.print(" DS2408 data = "); - // First 3 bytes contain command, register address. - Serial.println(buf[3], BIN); -} - -OneWire net(10); // on pin 10 - -void setup(void) { - Serial.begin(9600); -} - -void loop(void) { - byte i; - byte present = 0; - byte addr[8]; - - if (!net.search(addr)) { - Serial.print("No more addresses.\n"); - net.reset_search(); - delay(1000); - return; - } - - if (OneWire::crc8(addr, 7) != addr[7]) { - Serial.print("CRC is not valid!\n"); - return; - } - - if (addr[0] != 0x29) { - PrintBytes(addr, 8); - Serial.print(" is not a DS2408.\n"); - return; - } - - ReadAndReport(&net, addr); -} diff --git a/libraries/OneWire/examples/DS250x_PROM/DS250x_PROM.ino b/libraries/OneWire/examples/DS250x_PROM/DS250x_PROM.ino deleted file mode 100644 index a85b1c29..00000000 --- a/libraries/OneWire/examples/DS250x_PROM/DS250x_PROM.ino +++ /dev/null @@ -1,90 +0,0 @@ -/* -DS250x add-only programmable memory reader w/SKIP ROM. - - The DS250x is a 512/1024bit add-only PROM(you can add data but cannot change the old one) that's used mainly for device identification purposes - like serial number, mfgr data, unique identifiers, etc. It uses the Maxim 1-wire bus. - - This sketch will use the SKIP ROM function that skips the 1-Wire search phase since we only have one device connected in the bus on digital pin 6. - If more than one device is connected to the bus, it will fail. - Sketch will not verify if device connected is from the DS250x family since the skip rom function effectively skips the family-id byte readout. - thus it is possible to run this sketch with any Maxim OneWire device in which case the command CRC will most likely fail. - Sketch will only read the first page of memory(32bits) starting from the lower address(0000h), if more than 1 device is present, then use the sketch with search functions. - Remember to put a 4.7K pullup resistor between pin 6 and +Vcc - - To change the range or ammount of data to read, simply change the data array size, LSB/MSB addresses and for loop iterations - - This example code is in the public domain and is provided AS-IS. - - Built with Arduino 0022 and PJRC OneWire 2.0 library http://www.pjrc.com/teensy/td_libs_OneWire.html - - created by Guillermo Lovato - march/2011 - - */ - -#include -OneWire ds(6); // OneWire bus on digital pin 6 -void setup() { - Serial.begin (9600); -} - -void loop() { - byte i; // This is for the for loops - boolean present; // device present var - byte data[32]; // container for the data from device - byte leemem[3] = { // array with the commands to initiate a read, DS250x devices expect 3 bytes to start a read: command,LSB&MSB adresses - 0xF0 , 0x00 , 0x00 }; // 0xF0 is the Read Data command, followed by 00h 00h as starting address(the beginning, 0000h) - byte ccrc; // Variable to store the command CRC - byte ccrc_calc; - - present = ds.reset(); // OneWire bus reset, always needed to start operation on the bus, returns a 1/TRUE if there's a device present. - ds.skip(); // Skip ROM search - - if (present == TRUE){ // We only try to read the data if there's a device present - Serial.println("DS250x device present"); - ds.write(leemem[0],1); // Read data command, leave ghost power on - ds.write(leemem[1],1); // LSB starting address, leave ghost power on - ds.write(leemem[2],1); // MSB starting address, leave ghost power on - - ccrc = ds.read(); // DS250x generates a CRC for the command we sent, we assign a read slot and store it's value - ccrc_calc = OneWire::crc8(leemem, 3); // We calculate the CRC of the commands we sent using the library function and store it - - if ( ccrc_calc != ccrc) { // Then we compare it to the value the ds250x calculated, if it fails, we print debug messages and abort - Serial.println("Invalid command CRC!"); - Serial.print("Calculated CRC:"); - Serial.println(ccrc_calc,HEX); // HEX makes it easier to observe and compare - Serial.print("DS250x readback CRC:"); - Serial.println(ccrc,HEX); - return; // Since CRC failed, we abort the rest of the loop and start over - } - Serial.println("Data is: "); // For the printout of the data - for ( i = 0; i < 32; i++) { // Now it's time to read the PROM data itself, each page is 32 bytes so we need 32 read commands - data[i] = ds.read(); // we store each read byte to a different position in the data array - Serial.print(data[i]); // printout in ASCII - Serial.print(" "); // blank space - } - Serial.println(); - delay(5000); // Delay so we don't saturate the serial output - } - else { // Nothing is connected in the bus - Serial.println("Nothing connected"); - delay(3000); - } -} - - - - - - - - - - - - - - - - - diff --git a/libraries/OneWire/keywords.txt b/libraries/OneWire/keywords.txt deleted file mode 100644 index bee5d90b..00000000 --- a/libraries/OneWire/keywords.txt +++ /dev/null @@ -1,38 +0,0 @@ -####################################### -# Syntax Coloring Map For OneWire -####################################### - -####################################### -# Datatypes (KEYWORD1) -####################################### - -OneWire KEYWORD1 - -####################################### -# Methods and Functions (KEYWORD2) -####################################### - -reset KEYWORD2 -write_bit KEYWORD2 -read_bit KEYWORD2 -write KEYWORD2 -write_bytes KEYWORD2 -read KEYWORD2 -read_bytes KEYWORD2 -select KEYWORD2 -skip KEYWORD2 -depower KEYWORD2 -reset_search KEYWORD2 -search KEYWORD2 -crc8 KEYWORD2 -crc16 KEYWORD2 -check_crc16 KEYWORD2 - -####################################### -# Instances (KEYWORD2) -####################################### - - -####################################### -# Constants (LITERAL1) -####################################### diff --git a/libraries/OneWire/library.json b/libraries/OneWire/library.json deleted file mode 100644 index 1e95e2e9..00000000 --- a/libraries/OneWire/library.json +++ /dev/null @@ -1,61 +0,0 @@ -{ - "name": "OneWire", - "description": "Control 1-Wire protocol (DS18S20, DS18B20, DS2408 and etc)", - "keywords": "onewire, 1-wire, bus, sensor, temperature, ibutton", - "authors": [ - { - "name": "Paul Stoffregen", - "email": "paul@pjrc.com", - "url": "http://www.pjrc.com", - "maintainer": true - }, - { - "name": "Jim Studt" - }, - { - "name": "Tom Pollard", - "email": "pollard@alum.mit.edu" - }, - { - "name": "Derek Yerger" - }, - { - "name": "Josh Larios" - }, - { - "name": "Robin James" - }, - { - "name": "Glenn Trewitt" - }, - { - "name": "Jason Dangel", - "email": "dangel.jason AT gmail.com" - }, - { - "name": "Guillermo Lovato" - }, - { - "name": "Ken Butcher" - }, - { - "name": "Mark Tillotson" - }, - { - "name": "Bertrik Sikken" - }, - { - "name": "Scott Roberts" - } - ], - "repository": { - "type": "git", - "url": "https://github.com/PaulStoffregen/OneWire" - }, - "version": "2.3.2", - "homepage": "https://www.pjrc.com/teensy/td_libs_OneWire.html", - "frameworks": "Arduino", - "examples": [ - "examples/*/*.pde" - ] -} diff --git a/libraries/OneWire/library.properties b/libraries/OneWire/library.properties deleted file mode 100644 index 6842e122..00000000 --- a/libraries/OneWire/library.properties +++ /dev/null @@ -1,10 +0,0 @@ -name=OneWire -version=2.3.4 -author=Jim Studt, Tom Pollard, Robin James, Glenn Trewitt, Jason Dangel, Guillermo Lovato, Paul Stoffregen, Scott Roberts, Bertrik Sikken, Mark Tillotson, Ken Butcher, Roger Clark, Love Nystrom -maintainer=Paul Stoffregen -sentence=Access 1-wire temperature sensors, memory and other chips. -paragraph=Add Dallas one wire interface for single wire peripherals like DS18B20 (temperature), memory and other devices -category=Communication -url=http://www.pjrc.com/teensy/td_libs_OneWire.html -architectures=xmc - diff --git a/libraries/OneWire/src/OneWire.cpp b/libraries/OneWire/src/OneWire.cpp deleted file mode 100644 index 0a32a18d..00000000 --- a/libraries/OneWire/src/OneWire.cpp +++ /dev/null @@ -1,263 +0,0 @@ -/* Copyright (c) 2007, Jim Studt (original old version - many contributors since) - -The latest version of this library may be found at: - http://www.pjrc.com/teensy/td_libs_OneWire.html - -OneWire has been maintained by Paul Stoffregen (paul@pjrc.com) since -January 2010. - -DO NOT EMAIL for technical support, especially not for ESP chips! -All project support questions must be posted on public forums -relevant to the board or chips used. If using Arduino, post on -Arduino's forum. If using ESP, post on the ESP community forums. -There is ABSOLUTELY NO TECH SUPPORT BY PRIVATE EMAIL! - -Github's issue tracker for OneWire should be used only to report -specific bugs. DO NOT request project support via Github. All -project and tech support questions must be posted on forums, not -github issues. If you experience a problem and you are not -absolutely sure it's an issue with the library, ask on a forum -first. Only use github to report issues after experts have -confirmed the issue is with OneWire rather than your project. - -Back in 2010, OneWire was in need of many bug fixes, but had -been abandoned the original author (Jim Studt). None of the known -contributors were interested in maintaining OneWire. Paul typically -works on OneWire every 6 to 12 months. Patches usually wait that -long. If anyone is interested in more actively maintaining OneWire, -please contact Paul (this is pretty much the only reason to use -private email about OneWire). - -OneWire is now very mature code. No changes other than adding -definitions for newer hardware support are anticipated.*/ -/* -Version 2.3: - Unknown chip fallback mode, Roger Clark - Teensy-LC compatibility, Paul Stoffregen - Search bug fix, Love Nystrom - -Version 2.2: - Teensy 3.0 compatibility, Paul Stoffregen, paul@pjrc.com - Arduino Due compatibility, http://arduino.cc/forum/index.php?topic=141030 - Fix DS18B20 example negative temperature - Fix DS18B20 example's low res modes, Ken Butcher - Improve reset timing, Mark Tillotson - Add const qualifiers, Bertrik Sikken - Add initial value input to crc16, Bertrik Sikken - Add target_search() function, Scott Roberts - -Version 2.1: - Arduino 1.0 compatibility, Paul Stoffregen - Improve temperature example, Paul Stoffregen - DS250x_PROM example, Guillermo Lovato - PIC32 (chipKit) compatibility, Jason Dangel, dangel.jason AT gmail.com - Improvements from Glenn Trewitt: - - crc16() now works - - check_crc16() does all of calculation/checking work. - - Added read_bytes() and write_bytes(), to reduce tedious loops. - - Added ds2408 example. - Delete very old, out-of-date readme file (info is here) - -Version 2.0: Modifications by Paul Stoffregen, January 2010: -http://www.pjrc.com/teensy/td_libs_OneWire.html - Search fix from Robin James - http://www.arduino.cc/cgi-bin/yabb2/YaBB.pl?num=1238032295/27#27 - Use direct optimized I/O in all cases - Disable interrupts during timing critical sections - (this solves many random communication errors) - Disable interrupts during read-modify-write I/O - Reduce RAM consumption by eliminating unnecessary - variables and trimming many to 8 bits - Optimize both crc8 - table version moved to flash - -Modified to work with larger numbers of devices - avoids loop. -Tested in Arduino 11 alpha with 12 sensors. -26 Sept 2008 -- Robin James -http://www.arduino.cc/cgi-bin/yabb2/YaBB.pl?num=1238032295/27#27 - -Updated to work with arduino-0008 and to include skip() as of -2007/07/06. --RJL20 - -Modified to calculate the 8-bit CRC directly, avoiding the need for -the 256-byte lookup table to be loaded in RAM. Tested in arduino-0010 --- Tom Pollard, Jan 23, 2008 - -Jim Studt's original library was modified by Josh Larios. - -Tom Pollard, pollard@alum.mit.edu, contributed around May 20, 2008 -*/ -/* Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice shall be -included in all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -Much of the code was inspired by Derek Yerger's code, though I don't -think much of that remains. In any event that was.. - (copyleft) 2006 by Derek Yerger - Free to distribute freely. - -The CRC code was excerpted and inspired by the Dallas Semiconductor -sample code bearing this copyright. */ -/*--------------------------------------------------------------------------- -// Copyright (C) 2000 Dallas Semiconductor Corporation, All Rights Reserved. -// -// Permission is hereby granted, free of charge, to any person obtaining a -// copy of this software and associated documentation files (the "Software"), -// to deal in the Software without restriction, including without limitation -// the rights to use, copy, modify, merge, publish, distribute, sublicense, -// and/or sell copies of the Software, and to permit persons to whom the -// Software is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included -// in all copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS -// OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -// IN NO EVENT SHALL DALLAS SEMICONDUCTOR BE LIABLE FOR ANY CLAIM, DAMAGES -// OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, -// ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -// OTHER DEALINGS IN THE SOFTWARE. -// -// Except as contained in this notice, the name of Dallas Semiconductor -// shall not be used except as stated in the Dallas Semiconductor -// Branding Policy. -//-------------------------------------------------------------------------- -*/ -#include -#include "OneWire.h" -#include "util/OneWireConf.h" - -OneWire::OneWire(uint8_t pin, - const onewire::Timing_t *timing /*= &(onewire::timingStd)*/, - uint8_t forceSW /*= 0*/) { - if ((forceSW == 0) && PIN_HAS_ONEWIRE_HW(pin)) { - mImplementation = - new onewire::OneWireHW(&(onewire::mappingHW[PIN_TO_ONEWIRE_HW(pin)]), timing); - } else { - mImplementation = new onewire::OneWireSW(pin, timing); - } - - mImplementation->begin(); -} - -OneWire::~OneWire() { delete mImplementation; } - -// Perform the onewire reset function. We will wait up to 250uS for -// the bus to come high, if it doesn't then it is broken or shorted -// and we return a 0; -// -// Returns 1 if a device asserted a presence pulse, 0 otherwise. -// -uint8_t OneWire::reset(void) { mImplementation->reset(); } - -// -// Write a bit. Port and bit is used to cut lookup time and provide -// more certain timing. -// -void OneWire::write_bit(uint8_t v) { mImplementation->write_bit(v); } - -// -// Read a bit. Port and bit is used to cut lookup time and provide -// more certain timing. -// -uint8_t OneWire::read_bit(void) { return mImplementation->read_bit(); } - -// -// Write a byte. The writing code uses the active drivers to raise the -// pin high, if you need power after the write (e.g. DS18S20 in -// parasite power mode) then set 'power' to 1, otherwise the pin will -// go tri-state at the end of the write to avoid heating in a short or -// other mishap. -// -void OneWire::write(uint8_t v, uint8_t power /* = 0 */) { mImplementation->write(v, power); } - -void OneWire::write_bytes(const uint8_t *buf, uint16_t count, bool power /* = 0 */) { - mImplementation->write_bytes(buf, count, power); -} - -// -// Read a byte -// -uint8_t OneWire::read() { return mImplementation->read(); } - -void OneWire::read_bytes(uint8_t *buf, uint16_t count) { mImplementation->read_bytes(buf, count); } - -// -// Do a ROM select -// -void OneWire::select(const uint8_t rom[8]) { mImplementation->select(rom); } - -// -// Do a ROM skip -// -void OneWire::skip() { mImplementation->skip(); } - -void OneWire::depower() { mImplementation->depower(); } - -#if ONEWIRE_SEARCH -// You need to use this function to start a search again from the beginning. -// You do not need to do it for the first search, though you could. -// -void OneWire::reset_search() { mImplementation->reset_search(); } - -// Setup the search to find the device type 'family_code' on the next call -// to search(*newAddr) if it is present. -// -void OneWire::target_search(uint8_t family_code) { mImplementation->target_search(family_code); } - -// Perform a search. If this function returns a '1' then it has -// enumerated the next device and you may retrieve the ROM from the -// OneWire::address variable. If there are no devices, no further -// devices, or something horrible happens in the middle of the -// enumeration then a 0 is returned. If a new device is found then -// its address is copied to newAddr. Use OneWire::reset_search() to -// start over. -// -// --- Replaced by the one from the Dallas Semiconductor web site --- -//-------------------------------------------------------------------------- -// Perform the 1-Wire Search Algorithm on the 1-Wire bus using the existing -// search state. -// Return TRUE : device found, ROM number in ROM_NO buffer -// FALSE : device not found, end of search -// -uint8_t OneWire::search(uint8_t *newAddr, bool search_mode /* = true */) { - mImplementation->search(newAddr, search_mode); -} -#endif - -#if ONEWIRE_CRC -// The 1-Wire CRC scheme is described in Maxim Application Note 27: -// "Understanding and Using Cyclic Redundancy Checks with Maxim iButton Products" -// -uint8_t OneWire::crc8(const uint8_t *addr, uint8_t len) { - return onewire::OneWireImpl::crc8(addr, len); -} - - #if ONEWIRE_CRC16 -bool OneWire::check_crc16(const uint8_t *input, - uint16_t len, - const uint8_t *inverted_crc, - uint16_t crc) { - return onewire::OneWireImpl::check_crc16(input, len, inverted_crc, crc); -} - -uint16_t OneWire::crc16(const uint8_t *input, uint16_t len, uint16_t crc) { - return onewire::OneWireImpl::crc16(input, len, crc); -} - #endif - -#endif diff --git a/libraries/OneWire/src/OneWire.h b/libraries/OneWire/src/OneWire.h deleted file mode 100644 index 0d68fb2e..00000000 --- a/libraries/OneWire/src/OneWire.h +++ /dev/null @@ -1,87 +0,0 @@ -#ifndef OneWire_h -#define OneWire_h - -#include "SPI.h" -#include "util/OneWireImpl.h" -#include "util/OneWireTiming.h" -#include "util/OneWireSW.h" -#include "util/OneWireHW.h" - -class OneWire { -private: - onewire::OneWireImpl *mImplementation; - -public: - OneWire(uint8_t pin, - const onewire::Timing_t *timing = &(onewire::timingStd), - uint8_t forceSW = 0); - ~OneWire(); - // Perform a 1-Wire reset cycle. Returns 1 if a device responds - // with a presence pulse. Returns 0 if there is no device or the - // bus is shorted or otherwise held low for more than 250uS - uint8_t reset(void); - - // Issue a 1-Wire rom select command, you do the reset first. - void select(const uint8_t rom[8]); - - // Issue a 1-Wire rom skip command, to address all on bus. - void skip(void); - - // Write a byte. If 'power' is one then the wire is held high at - // the end for parasitically powered devices. You are responsible - // for eventually depowering it by calling depower() or doing - // another read or write. - void write(uint8_t v, uint8_t power = 0); - - void write_bytes(const uint8_t *buf, uint16_t count, bool power = 0); - - // Read a byte. - uint8_t read(void); - - void read_bytes(uint8_t *buf, uint16_t count); - - // Write a bit. The bus is always left powered at the end, see - // note in write() about that. - void write_bit(uint8_t v); - - // Read a bit. - uint8_t read_bit(void); - - // Stop forcing power onto the bus. You only need to do this if - // you used the 'power' flag to write() or used a write_bit() call - // and aren't about to do another read or write. You would rather - // not leave this powered if you don't have to, just in case - // someone shorts your bus. - void depower(void); - -#if ONEWIRE_SEARCH - // Clear the search state so that if will start from the beginning again. - void reset_search(); - - // Setup the search to find the device type 'family_code' on the next call - // to search(*newAddr) if it is present. - void target_search(uint8_t family_code); - - // Look for the next device. Returns 1 if a new address has been - // returned. A zero might mean that the bus is shorted, there are - // no devices, or you have already retrieved all of them. It - // might be a good idea to check the CRC to make sure you didn't - // get garbage. The order is deterministic. You will always get - // the same devices in the same order. - uint8_t search(uint8_t *newAddr, bool search_mode = true); -#endif - -#if ONEWIRE_CRC - // Compute a Dallas Semiconductor 8 bit CRC, these are used in the - // ROM and scratchpad registers. - static uint8_t crc8(const uint8_t *addr, uint8_t len); - #if ONEWIRE_CRC16 - // Compute the 1-Wire CRC16 and compare it against the received CRC. - static bool - check_crc16(const uint8_t *input, uint16_t len, const uint8_t *inverted_crc, uint16_t crc = 0); - // Compute a Dallas Semiconductor 16 bit CRC. - static uint16_t crc16(const uint8_t *input, uint16_t len, uint16_t crc = 0); - #endif -#endif -}; -#endif diff --git a/libraries/OneWire/src/util/OneWireConf.h b/libraries/OneWire/src/util/OneWireConf.h deleted file mode 100644 index eeb7fe21..00000000 --- a/libraries/OneWire/src/util/OneWireConf.h +++ /dev/null @@ -1,302 +0,0 @@ -#ifndef ONEWIRE_CONF_H -#define ONEWIRE_CONF_H - -#include - -namespace onewire { - -#if defined(XMC1100_XMC2GO) - #define NUM_ONEWIRE_HW 4 - #define PIN_HAS_ONEWIRE_HW(pin) ((pin == 0) || (pin == 1) || (pin == 10) || (pin == 11)) - #define PIN_TO_ONEWIRE_HW(pin) \ - ((pin == 0) ? 0 : ((pin == 1) ? 1 : ((pin == 10) ? 2 : ((pin == 11) ? 3 : -1)))) - -XMC_SPI_t mappingHW[] = { - {// DONE tested with -O0 - .channel = XMC_SPI0_CH1, - .channel_config = {.baudrate = 15984375U, - .bus_mode = (XMC_SPI_CH_BUS_MODE_t)XMC_SPI_CH_BUS_MODE_MASTER, - .selo_inversion = XMC_SPI_CH_SLAVE_SEL_INV_TO_MSLS, - .parity_mode = XMC_USIC_CH_PARITY_MODE_NONE}, - .mosi = {.port = (XMC_GPIO_PORT_t *)PORT0_BASE, .pin = (uint8_t)6}, - .mosi_config = {.mode = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT7, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD}, - .miso = {.port = (XMC_GPIO_PORT_t *)PORT0_BASE, .pin = (uint8_t)6}, - .miso_config = {.mode = XMC_GPIO_MODE_INPUT_TRISTATE, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD}, - .input_source = XMC_INPUT_C, - .sclkout = {.port = (XMC_GPIO_PORT_t *)PORT0_BASE, .pin = (uint8_t)6}, - .sclkout_config = {.mode = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT7, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD}}, - {.channel = XMC_SPI0_CH1, - .channel_config = {.baudrate = 15984375U, - .bus_mode = (XMC_SPI_CH_BUS_MODE_t)XMC_SPI_CH_BUS_MODE_MASTER, - .selo_inversion = XMC_SPI_CH_SLAVE_SEL_INV_TO_MSLS, - .parity_mode = XMC_USIC_CH_PARITY_MODE_NONE}, - .mosi = {.port = (XMC_GPIO_PORT_t *)PORT0_BASE, .pin = (uint8_t)7}, - .mosi_config = {.mode = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT7, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD}, - .miso = {.port = (XMC_GPIO_PORT_t *)PORT0_BASE, .pin = (uint8_t)7}, - .miso_config = {.mode = XMC_GPIO_MODE_INPUT_TRISTATE, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD}, - .input_source = XMC_INPUT_D, - .sclkout = {.port = (XMC_GPIO_PORT_t *)PORT0_BASE, .pin = (uint8_t)7}, - .sclkout_config = {.mode = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT7, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD}}, - {.channel = XMC_SPI0_CH1, - .channel_config = {.baudrate = 15984375U, - .bus_mode = (XMC_SPI_CH_BUS_MODE_t)XMC_SPI_CH_BUS_MODE_MASTER, - .selo_inversion = XMC_SPI_CH_SLAVE_SEL_INV_TO_MSLS, - .parity_mode = XMC_USIC_CH_PARITY_MODE_NONE}, - .mosi = {.port = (XMC_GPIO_PORT_t *)PORT2_BASE, .pin = (uint8_t)11}, - .mosi_config = {.mode = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT7, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD}, - .miso = {.port = (XMC_GPIO_PORT_t *)PORT2_BASE, .pin = (uint8_t)11}, - .miso_config = {.mode = XMC_GPIO_MODE_INPUT_TRISTATE, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD}, - .input_source = XMC_INPUT_F, - .sclkout = {.port = (XMC_GPIO_PORT_t *)PORT2_BASE, .pin = (uint8_t)11}, - .sclkout_config = {.mode = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT7, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD}}, - {.channel = XMC_SPI0_CH1, - .channel_config = {.baudrate = 15984375U, - .bus_mode = (XMC_SPI_CH_BUS_MODE_t)XMC_SPI_CH_BUS_MODE_MASTER, - .selo_inversion = XMC_SPI_CH_SLAVE_SEL_INV_TO_MSLS, - .parity_mode = XMC_USIC_CH_PARITY_MODE_NONE}, - .mosi = {.port = (XMC_GPIO_PORT_t *)PORT2_BASE, .pin = (uint8_t)10}, - .mosi_config = {.mode = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT7, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD}, - .miso = {.port = (XMC_GPIO_PORT_t *)PORT2_BASE, .pin = (uint8_t)10}, - .miso_config = {.mode = XMC_GPIO_MODE_INPUT_TRISTATE, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD}, - .input_source = XMC_INPUT_E, - .sclkout = {.port = (XMC_GPIO_PORT_t *)PORT2_BASE, .pin = (uint8_t)10}, - .sclkout_config = {.mode = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT7, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD}}}; - -#elif defined(XMC1100_Boot_Kit) - #define NUM_ONEWIRE_HW 3 - #define PIN_HAS_ONEWIRE_HW(pin) ((pin == 11) || (pin == 15) || (pin == 16)) - #define PIN_TO_ONEWIRE_HW(pin) ((pin == 11) ? 0 : ((pin == 15) ? 1 : ((pin == 16) ? 2 : -1))) - -XMC_SPI_t mappingHW[] = { - {.channel = XMC_SPI0_CH0, - .channel_config = {.baudrate = 15984375U, - .bus_mode = (XMC_SPI_CH_BUS_MODE_t)XMC_SPI_CH_BUS_MODE_MASTER, - .selo_inversion = XMC_SPI_CH_SLAVE_SEL_INV_TO_MSLS, - .parity_mode = XMC_USIC_CH_PARITY_MODE_NONE}, - .mosi = {.port = (XMC_GPIO_PORT_t *)PORT1_BASE, .pin = (uint8_t)1}, - .mosi_config = {.mode = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT6, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD}, - .miso = {.port = (XMC_GPIO_PORT_t *)PORT1_BASE, .pin = (uint8_t)1}, - .miso_config = {.mode = XMC_GPIO_MODE_INPUT_TRISTATE, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD}, - .input_source = XMC_INPUT_D, - .sclkout = {.port = (XMC_GPIO_PORT_t *)PORT1_BASE, .pin = (uint8_t)1}, - .sclkout_config = {.mode = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT6, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD}}, - {.channel = XMC_SPI0_CH0, - .channel_config = {.baudrate = 15984375U, - .bus_mode = (XMC_SPI_CH_BUS_MODE_t)XMC_SPI_CH_BUS_MODE_MASTER, - .selo_inversion = XMC_SPI_CH_SLAVE_SEL_INV_TO_MSLS, - .parity_mode = XMC_USIC_CH_PARITY_MODE_NONE}, - .mosi = {.port = (XMC_GPIO_PORT_t *)PORT2_BASE, .pin = (uint8_t)1}, - .mosi_config = {.mode = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT6, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD}, - .miso = {.port = (XMC_GPIO_PORT_t *)PORT2_BASE, .pin = (uint8_t)1}, - .miso_config = {.mode = XMC_GPIO_MODE_INPUT_TRISTATE, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD}, - .input_source = XMC_INPUT_F, - .sclkout = {.port = (XMC_GPIO_PORT_t *)PORT2_BASE, .pin = (uint8_t)1}, - .sclkout_config = {.mode = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT6, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD}}, - {.channel = XMC_SPI0_CH0, - .channel_config = {.baudrate = 15984375U, - .bus_mode = (XMC_SPI_CH_BUS_MODE_t)XMC_SPI_CH_BUS_MODE_MASTER, - .selo_inversion = XMC_SPI_CH_SLAVE_SEL_INV_TO_MSLS, - .parity_mode = XMC_USIC_CH_PARITY_MODE_NONE}, - .mosi = {.port = (XMC_GPIO_PORT_t *)PORT2_BASE, .pin = (uint8_t)0}, - .mosi_config = {.mode = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT6, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD}, - .miso = {.port = (XMC_GPIO_PORT_t *)PORT2_BASE, .pin = (uint8_t)0}, - .miso_config = {.mode = XMC_GPIO_MODE_INPUT_TRISTATE, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD}, - .input_source = XMC_INPUT_E, - .sclkout = {.port = (XMC_GPIO_PORT_t *)PORT2_BASE, .pin = (uint8_t)0}, - .sclkout_config = {.mode = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT6, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD}}}; - -#elif defined(XMC4700_Relax_Kit) - #define NUM_ONEWIRE_HW 6 - #define PIN_HAS_ONEWIRE_HW(pin) \ - ((pin == 1) || (pin == 15) || (pin == 29) || (pin == 37) || (pin == 70) || (pin == 88)) - #define PIN_TO_ONEWIRE_HW(pin) \ - ((pin == 1) \ - ? 0 \ - : ((pin == 15) \ - ? 1 \ - : ((pin == 29) \ - ? 2 \ - : ((pin == 37) ? 3 : ((pin == 70) ? 4 : ((pin == 88) ? 5 : -1)))))) - -XMC_SPI_t - mappingHW[] = - {{ - // DONE tested with -O0 - .channel = XMC_SPI1_CH0, - .channel_config = {.baudrate = 20003906U, - .bus_mode = (XMC_SPI_CH_BUS_MODE_t)XMC_SPI_CH_BUS_MODE_MASTER, - .selo_inversion = XMC_SPI_CH_SLAVE_SEL_INV_TO_MSLS, - .parity_mode = XMC_USIC_CH_PARITY_MODE_NONE}, - .mosi = {.port = (XMC_GPIO_PORT_t *)PORT2_BASE, .pin = (uint8_t)14}, - .mosi_config = {.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT2, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .output_strength = XMC_GPIO_OUTPUT_STRENGTH_MEDIUM}, - .miso = {.port = (XMC_GPIO_PORT_t *)PORT2_BASE, .pin = (uint8_t)14}, - .miso_config = - { - .mode = XMC_GPIO_MODE_INPUT_TRISTATE, - }, - .input_source = XMC_INPUT_B, - .sclkout = {.port = (XMC_GPIO_PORT_t *)PORT2_BASE, .pin = (uint8_t)14}, - .sclkout_config = {.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT2, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .output_strength = XMC_GPIO_OUTPUT_STRENGTH_MEDIUM}, - }, - { - .channel = XMC_SPI1_CH1, - .channel_config = {.baudrate = 20003906U, - .bus_mode = (XMC_SPI_CH_BUS_MODE_t)XMC_SPI_CH_BUS_MODE_MASTER, - .selo_inversion = XMC_SPI_CH_SLAVE_SEL_INV_TO_MSLS, - .parity_mode = XMC_USIC_CH_PARITY_MODE_NONE}, - .mosi = {.port = (XMC_GPIO_PORT_t *)PORT3_BASE, .pin = (uint8_t)15}, - .mosi_config = {.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT2, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .output_strength = XMC_GPIO_OUTPUT_STRENGTH_MEDIUM}, - .miso = {.port = (XMC_GPIO_PORT_t *)PORT3_BASE, .pin = (uint8_t)15}, - .miso_config = - { - .mode = XMC_GPIO_MODE_INPUT_TRISTATE, - }, - .input_source = XMC_INPUT_A, - .sclkout = {.port = (XMC_GPIO_PORT_t *)PORT3_BASE, .pin = (uint8_t)15}, - .sclkout_config = {.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT2, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .output_strength = XMC_GPIO_OUTPUT_STRENGTH_MEDIUM}, - }, - { - .channel = XMC_SPI2_CH1, - .channel_config = {.baudrate = 20003906U, - .bus_mode = (XMC_SPI_CH_BUS_MODE_t)XMC_SPI_CH_BUS_MODE_MASTER, - .selo_inversion = XMC_SPI_CH_SLAVE_SEL_INV_TO_MSLS, - .parity_mode = XMC_USIC_CH_PARITY_MODE_NONE}, - .mosi = {.port = (XMC_GPIO_PORT_t *)PORT3_BASE, .pin = (uint8_t)5}, - .mosi_config = {.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT1, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .output_strength = XMC_GPIO_OUTPUT_STRENGTH_MEDIUM}, - .miso = {.port = (XMC_GPIO_PORT_t *)PORT3_BASE, .pin = (uint8_t)5}, - .miso_config = - { - .mode = XMC_GPIO_MODE_INPUT_TRISTATE, - }, - .input_source = XMC_INPUT_A, - .sclkout = {.port = (XMC_GPIO_PORT_t *)PORT3_BASE, .pin = (uint8_t)5}, - .sclkout_config = {.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT1, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .output_strength = XMC_GPIO_OUTPUT_STRENGTH_MEDIUM}, - }, - { - .channel = XMC_SPI1_CH0, - .channel_config = {.baudrate = 20003906U, - .bus_mode = (XMC_SPI_CH_BUS_MODE_t)XMC_SPI_CH_BUS_MODE_MASTER, - .selo_inversion = XMC_SPI_CH_SLAVE_SEL_INV_TO_MSLS, - .parity_mode = XMC_USIC_CH_PARITY_MODE_NONE}, - .mosi = {.port = (XMC_GPIO_PORT_t *)PORT0_BASE, .pin = (uint8_t)5}, - .mosi_config = {.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT2, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .output_strength = XMC_GPIO_OUTPUT_STRENGTH_MEDIUM}, - .miso = {.port = (XMC_GPIO_PORT_t *)PORT0_BASE, .pin = (uint8_t)5}, - .miso_config = - { - .mode = XMC_GPIO_MODE_INPUT_TRISTATE, - }, - .input_source = XMC_INPUT_B, - .sclkout = {.port = (XMC_GPIO_PORT_t *)PORT0_BASE, .pin = (uint8_t)5}, - .sclkout_config = {.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT2, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .output_strength = XMC_GPIO_OUTPUT_STRENGTH_MEDIUM}, - }, - { - .channel = XMC_SPI0_CH1, - .channel_config = {.baudrate = 20003906U, - .bus_mode = (XMC_SPI_CH_BUS_MODE_t)XMC_SPI_CH_BUS_MODE_MASTER, - .selo_inversion = XMC_SPI_CH_SLAVE_SEL_INV_TO_MSLS, - .parity_mode = XMC_USIC_CH_PARITY_MODE_NONE}, - .mosi = {.port = (XMC_GPIO_PORT_t *)PORT3_BASE, .pin = (uint8_t)13}, - .mosi_config = {.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT2, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .output_strength = XMC_GPIO_OUTPUT_STRENGTH_MEDIUM}, - .miso = {.port = (XMC_GPIO_PORT_t *)PORT3_BASE, .pin = (uint8_t)13}, - .miso_config = - { - .mode = XMC_GPIO_MODE_INPUT_TRISTATE, - }, - .input_source = XMC_INPUT_D, - .sclkout = {.port = (XMC_GPIO_PORT_t *)PORT3_BASE, .pin = (uint8_t)13}, - .sclkout_config = {.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT2, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .output_strength = XMC_GPIO_OUTPUT_STRENGTH_MEDIUM}, - }, - { - .channel = XMC_SPI2_CH0, - .channel_config = {.baudrate = 20003906U, - .bus_mode = (XMC_SPI_CH_BUS_MODE_t)XMC_SPI_CH_BUS_MODE_MASTER, - .selo_inversion = XMC_SPI_CH_SLAVE_SEL_INV_TO_MSLS, - .parity_mode = XMC_USIC_CH_PARITY_MODE_NONE}, - .mosi = {.port = (XMC_GPIO_PORT_t *)PORT5_BASE, .pin = (uint8_t)0}, - .mosi_config = {.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT1, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .output_strength = XMC_GPIO_OUTPUT_STRENGTH_MEDIUM}, - .miso = {.port = (XMC_GPIO_PORT_t *)PORT5_BASE, .pin = (uint8_t)0}, - .miso_config = - { - .mode = XMC_GPIO_MODE_INPUT_TRISTATE, - }, - .input_source = XMC_INPUT_B, - .sclkout = {.port = (XMC_GPIO_PORT_t *)PORT5_BASE, .pin = (uint8_t)0}, - .sclkout_config = {.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT1, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .output_strength = XMC_GPIO_OUTPUT_STRENGTH_MEDIUM}, - }}; -#else - // unknown device used - #define NUM_ONEWIRE_HW 0 - #define PIN_HAS_ONEWIRE_HW(pin) 0 - #define PIN_TO_ONEWIRE_HW(pin) -1 - -XMC_SPI_t mappingHW[1]; -#endif - -} /* namespace onewire */ -#endif \ No newline at end of file diff --git a/libraries/OneWire/src/util/OneWireHW.cpp b/libraries/OneWire/src/util/OneWireHW.cpp deleted file mode 100644 index 70a85f7f..00000000 --- a/libraries/OneWire/src/util/OneWireHW.cpp +++ /dev/null @@ -1,106 +0,0 @@ -#include -#include "OneWireHW.h" - -// SPI frequency to transmit 1 byte per microsecond -// this means 1 onewire bit per microsecond -#define ONEWIRE_1BIT_PER_MICROSSEC 8000000 - -namespace onewire { -// these are patterns for low-pulses with different lengths -// the index equals the length of the low-pulse in bits (0 and 8 is forbidden and repalced by 1 and -// 7) -uint8_t pulses[9] = {0x7F, 0x7F, 0x3F, 0x1F, 0x0F, 0x07, 0x03, 0x01, 0x01}; - -OneWireHW::OneWireHW(XMC_SPI_t *spiConf, const Timing_t *timing) - : OneWireImpl() { - if (!isValid(timing)) { - timing = &timingStd; - } - mSpiHW = SPIClass(spiConf); - mSpiConf = SPISettings(ONEWIRE_1BIT_PER_MICROSSEC / timing->bitDuration, MSBFIRST, SPI_MODE3); - mSpiCodes[0] = pulses[(timing->lowtimeLong << 3) / timing->bitDuration]; - mSpiCodes[1] = pulses[(timing->lowtimeShort << 3) / timing->bitDuration]; - mSpiResetTime = timing->resetDuration / timing->bitDuration + 1; -} - -void OneWireHW::begin(void) { - mSpiHW.begin(); - mSpiHW.beginTransaction(mSpiConf); - // reset(); -} - -OneWireHW::~OneWireHW() { end(); } - -void OneWireHW::end(void) { mSpiHW.end(); } - -uint8_t OneWireHW::reset(void) { - noInterrupts(); - for (uint8_t i = 0; i < mSpiResetTime; i++) { - mSpiHW.transfer(0x00); - } - // test if slave sends a low pulse to indicate presence - uint8_t ret = (mSpiHW.transfer(0xFF) != 0xFF); - interrupts(); - // wait for the maximum presence pulse time - for (uint8_t i = 1; i < (mSpiResetTime / 2); i++) { - mSpiHW.transfer(0xFF); - } - // bus should already have come up - // wait some more time to be sure - // if it does not come up return 0 to indicate a short circuit - if ((mSpiHW.transfer(0xFF) & (0x01))) { - // return 1 if slave has indicated presence, 0 otherwise - return ret; - } else { - return 0; - } -} - -void OneWireHW::write(uint8_t v, uint8_t power /*= 0*/) { - for (uint8_t i = 0; i < 8; i++) { - mByteBuffer[i] = mSpiCodes[v & (0x01 << i)]; - } - mSpiHW.transfer(mByteBuffer, 8); - // We don't have to care about powering and depowering on XMC controllers - // We are using open-drain outputs with pull-ups to prevent short circuits. -} - -void OneWireHW::write_bytes(const uint8_t *buf, uint16_t count, bool power /*= 0*/) { - for (uint16_t i = 0; i < count; i++) { - write(buf[i], power); - } - // We don't have to care about powering and depowering on XMC controllers - // We are using open-drain outputs with pull-ups to prevent short circuits. -} - -uint8_t OneWireHW::read(void) { - uint8_t i, ret = 0; - for (i = 0; i < 8; i++) { - mByteBuffer[i] = mSpiCodes[1]; - } - mSpiHW.transfer(mByteBuffer, 8); - for (i = 0; i < 8; i++) { - ret |= (mByteBuffer[i] == mSpiCodes[1]) << i; - } - return ret; -} - -void OneWireHW::read_bytes(uint8_t *buf, uint16_t count) { - for (uint16_t i = 0; i < count; i++) { - buf[i] = read(); - } -} - -void OneWireHW::write_bit(uint8_t v) { mSpiHW.transfer(mSpiCodes[v & 0x01]); } - -uint8_t OneWireHW::read_bit(void) { - // if we get something else than we have sent, slave has held down the line(sent 0) - return (mSpiHW.transfer(mSpiCodes[1]) == mSpiCodes[1]); -} - -void OneWireHW::depower(void) { - // We don't have to care about powering and depowering on XMC controllers - // We are using open-drain outputs with pull-ups to prevent short circuits. -} - -} // namespace onewire diff --git a/libraries/OneWire/src/util/OneWireHW.h b/libraries/OneWire/src/util/OneWireHW.h deleted file mode 100644 index edf6dec8..00000000 --- a/libraries/OneWire/src/util/OneWireHW.h +++ /dev/null @@ -1,34 +0,0 @@ -#ifndef ONEWIRE_HW_H -#define ONEWIRE_HW_H - -#include "OneWireTiming.h" -#include "OneWireImpl.h" -#include "SPI.h" - -namespace onewire { -class OneWireHW : public OneWireImpl { -private: - SPISettings mSpiConf; - SPIClass mSpiHW; - uint8_t mSpiCodes[2]; - uint8_t mSpiResetTime; - uint8_t mByteBuffer[8]; - -public: - OneWireHW(XMC_SPI_t *spiConf, const Timing_t *timing); - ~OneWireHW(); - // begin and end do not appear in the original version - // they are called automatically in our implementation - virtual void begin(void) override; - virtual void end(void) override; - virtual uint8_t reset(void) override; - virtual void write(uint8_t v, uint8_t power = 0) override; - virtual void write_bytes(const uint8_t *buf, uint16_t count, bool power = 0) override; - virtual uint8_t read(void) override; - virtual void read_bytes(uint8_t *buf, uint16_t count) override; - virtual void write_bit(uint8_t v) override; - virtual uint8_t read_bit(void) override; - virtual void depower(void) override; -}; -} // namespace onewire -#endif \ No newline at end of file diff --git a/libraries/OneWire/src/util/OneWireImpl.cpp b/libraries/OneWire/src/util/OneWireImpl.cpp deleted file mode 100644 index cd200522..00000000 --- a/libraries/OneWire/src/util/OneWireImpl.cpp +++ /dev/null @@ -1,253 +0,0 @@ -#include -#include "OneWireImpl.h" - -namespace onewire { -OneWireImpl::OneWireImpl(void) { -#if ONEWIRE_SEARCH - reset_search(); -#endif -} - -OneWireImpl::~OneWireImpl() {} - -void OneWireImpl::select(const uint8_t rom[8]) { - write(0x55); // Choose ROM - for (uint8_t i = 0; i < 8; i++) { - write(rom[i]); - } -} - -void OneWireImpl::skip(void) { - write(0xCC); // Skip ROM -} - -#if ONEWIRE_SEARCH - -void OneWireImpl::reset_search() { - // reset the search state - LastDiscrepancy = 0; - LastDeviceFlag = FALSE; - LastFamilyDiscrepancy = 0; - for (uint8_t i = 7; i > 0; i--) { - ROM_NO[i] = 0; - } -} - -void OneWireImpl::target_search(uint8_t family_code) { - // set the search state to find SearchFamily type devices - ROM_NO[0] = family_code; - for (uint8_t i = 1; i < 8; i++) { - ROM_NO[i] = 0; - } - LastDiscrepancy = 64; - LastFamilyDiscrepancy = 0; - LastDeviceFlag = FALSE; -} - -uint8_t OneWireImpl::search(uint8_t *newAddr, bool search_mode /*= true*/) { - uint8_t id_bit_number; - uint8_t last_zero, rom_byte_number, search_result; - uint8_t id_bit, cmp_id_bit; - unsigned char rom_byte_mask, search_direction; - // initialize for search - id_bit_number = 1; - last_zero = 0; - rom_byte_number = 0; - rom_byte_mask = 1; - search_result = 0; - // if the last call was not the last one - if (!LastDeviceFlag) { - // 1-Wire reset - if (!reset()) { - // reset the search - LastDiscrepancy = 0; - LastDeviceFlag = FALSE; - LastFamilyDiscrepancy = 0; - return FALSE; - } - - // issue the search command - if (search_mode == true) { - write(0xF0); // NORMAL SEARCH - } else { - write(0xEC); // CONDITIONAL SEARCH - } - - // loop to do the search - do { - // read a bit and its complement - id_bit = read_bit(); - cmp_id_bit = read_bit(); - // check for no devices on 1-wire - if ((id_bit == 1) && (cmp_id_bit == 1)) { - break; - } else { - // all devices coupled have 0 or 1 - if (id_bit != cmp_id_bit) { - search_direction = id_bit; // bit write value for search - } else { - // if this discrepancy if before the Last Discrepancy - // on a previous next then pick the same as last time - if (id_bit_number < LastDiscrepancy) { - search_direction = ((ROM_NO[rom_byte_number] & rom_byte_mask) > 0); - } else { - // if equal to last pick 1, if not then pick 0 - search_direction = (id_bit_number == LastDiscrepancy); - } - // if 0 was picked then record its position in LastZero - if (search_direction == 0) { - last_zero = id_bit_number; - // check for Last discrepancy in family - if (last_zero < 9) { - LastFamilyDiscrepancy = last_zero; - } - } - } - - // set or clear the bit in the ROM byte rom_byte_number - // with mask rom_byte_mask - if (search_direction == 1) { - ROM_NO[rom_byte_number] |= rom_byte_mask; - } else { - ROM_NO[rom_byte_number] &= ~rom_byte_mask; - } - - // serial number search direction write bit - write_bit(search_direction); - - // increment the byte counter id_bit_number - // and shift the mask rom_byte_mask - id_bit_number++; - rom_byte_mask <<= 1; - - // if the mask is 0 then go to new SerialNum byte rom_byte_number and reset mask - if (rom_byte_mask == 0) { - rom_byte_number++; - rom_byte_mask = 1; - } - } - } while (rom_byte_number < 8); // loop until through all ROM bytes 0-7 - - // if the search was successful then - if (!(id_bit_number < 65)) { - // search successful so set LastDiscrepancy,LastDeviceFlag,search_result - LastDiscrepancy = last_zero; - // check for last device - if (LastDiscrepancy == 0) { - LastDeviceFlag = TRUE; - } - search_result = TRUE; - } - } - - // if no device found then reset counters so next 'search' will be like a first - if (!search_result || !ROM_NO[0]) { - LastDiscrepancy = 0; - LastDeviceFlag = FALSE; - LastFamilyDiscrepancy = 0; - search_result = FALSE; - } else { - for (int i = 0; i < 8; i++) { - newAddr[i] = ROM_NO[i]; - } - } - return search_result; -} - -#endif - -#if ONEWIRE_CRC - // The 1-Wire CRC scheme is described in Maxim Application Note 27: - // "Understanding and Using Cyclic Redundancy Checks with Maxim iButton Products" - // - #if ONEWIRE_CRC8_TABLE -// This table comes from Dallas sample code where it is freely reusable, -// though Copyright (C) 2000 Dallas Semiconductor Corporation -static const uint8_t PROGMEM dscrc_table[] = { - 0, 94, 188, 226, 97, 63, 221, 131, 194, 156, 126, 32, 163, 253, 31, 65, 157, 195, 33, - 127, 252, 162, 64, 30, 95, 1, 227, 189, 62, 96, 130, 220, 35, 125, 159, 193, 66, 28, - 254, 160, 225, 191, 93, 3, 128, 222, 60, 98, 190, 224, 2, 92, 223, 129, 99, 61, 124, - 34, 192, 158, 29, 67, 161, 255, 70, 24, 250, 164, 39, 121, 155, 197, 132, 218, 56, 102, - 229, 187, 89, 7, 219, 133, 103, 57, 186, 228, 6, 88, 25, 71, 165, 251, 120, 38, 196, - 154, 101, 59, 217, 135, 4, 90, 184, 230, 167, 249, 27, 69, 198, 152, 122, 36, 248, 166, - 68, 26, 153, 199, 37, 123, 58, 100, 134, 216, 91, 5, 231, 185, 140, 210, 48, 110, 237, - 179, 81, 15, 78, 16, 242, 172, 47, 113, 147, 205, 17, 79, 173, 243, 112, 46, 204, 146, - 211, 141, 111, 49, 178, 236, 14, 80, 175, 241, 19, 77, 206, 144, 114, 44, 109, 51, 209, - 143, 12, 82, 176, 238, 50, 108, 142, 208, 83, 13, 239, 177, 240, 174, 76, 18, 145, 207, - 45, 115, 202, 148, 118, 40, 171, 245, 23, 73, 8, 86, 180, 234, 105, 55, 213, 139, 87, - 9, 235, 181, 54, 104, 138, 212, 149, 203, 41, 119, 244, 170, 72, 22, 233, 183, 85, 11, - 136, 214, 52, 106, 43, 117, 151, 201, 74, 20, 246, 168, 116, 42, 200, 150, 21, 75, 169, - 247, 182, 232, 10, 84, 215, 137, 107, 53}; - -// -// Compute a Dallas Semiconductor 8 bit CRC. These show up in the ROM -// and the registers. (note: this might better be done without to -// table, it would probably be smaller and certainly fast enough -// compared to all those delayMicrosecond() calls. But I got -// confused, so I use this table from the examples.) -// -uint8_t OneWireImpl::crc8(const uint8_t *addr, uint8_t len) { - uint8_t crc = 0; - - while (len--) { - crc = pgm_read_byte(dscrc_table + (crc ^ *addr++)); - } - return crc; -} - #else -// -// Compute a Dallas Semiconductor 8 bit CRC directly. -// this is much slower, but much smaller, than the lookup table. -// -uint8_t OneWireImpl::crc8(const uint8_t *addr, uint8_t len) { - uint8_t crc = 0; - - while (len--) { - uint8_t inbyte = *addr++; - for (uint8_t i = 8; i; i--) { - uint8_t mix = (crc ^ inbyte) & 0x01; - crc >>= 1; - if (mix) - crc ^= 0x8C; - inbyte >>= 1; - } - } - return crc; -} - #endif - - #if ONEWIRE_CRC16 -bool OneWireImpl::check_crc16(const uint8_t *input, - uint16_t len, - const uint8_t *inverted_crc, - uint16_t crc /*= 0*/) { - crc = ~crc16(input, len, crc); - return (crc & 0xFF) == inverted_crc[0] && (crc >> 8) == inverted_crc[1]; -} - -uint16_t OneWireImpl::crc16(const uint8_t *input, uint16_t len, uint16_t crc /*= 0*/) { - static const uint8_t oddparity[16] = {0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0}; - - for (uint16_t i = 0; i < len; i++) { - // Even though we're just copying a byte from the input, - // we'll be doing 16-bit computation with it. - uint16_t cdata = input[i]; - cdata = (cdata ^ crc) & 0xff; - crc >>= 8; - - if (oddparity[cdata & 0x0F] ^ oddparity[cdata >> 4]) { - crc ^= 0xC001; - } - - cdata <<= 6; - crc ^= cdata; - cdata <<= 1; - crc ^= cdata; - } - return crc; -} - - #endif -#endif - -} // namespace onewire diff --git a/libraries/OneWire/src/util/OneWireImpl.h b/libraries/OneWire/src/util/OneWireImpl.h deleted file mode 100644 index 087761a1..00000000 --- a/libraries/OneWire/src/util/OneWireImpl.h +++ /dev/null @@ -1,68 +0,0 @@ -#ifndef ONEWIRE_IMPL_H -#define ONEWIRE_IMPL_H - -#include "SPI.h" -#include "OneWireSettings.h" - -namespace onewire { -class OneWireImpl { -private: -#if ONEWIRE_SEARCH - // global search state - unsigned char ROM_NO[8]; - uint8_t LastDiscrepancy; - uint8_t LastFamilyDiscrepancy; - uint8_t LastDeviceFlag; -#endif - -public: - OneWireImpl(void); - virtual ~OneWireImpl(); - virtual void begin(void) = 0; - virtual void end(void) = 0; - virtual uint8_t reset(void) = 0; - virtual void write(uint8_t v, uint8_t power = 0) = 0; - virtual void write_bytes(const uint8_t *buf, uint16_t count, bool power = 0) = 0; - virtual uint8_t read(void) = 0; - virtual void read_bytes(uint8_t *buf, uint16_t count) = 0; - virtual void write_bit(uint8_t v) = 0; - virtual uint8_t read_bit(void) = 0; - virtual void depower(void) = 0; - - // Issue a 1-Wire rom select command, you do the reset first. - void select(const uint8_t rom[8]); - // Issue a 1-Wire rom skip command, to address all on bus. - void skip(void); - -#if ONEWIRE_SEARCH - // Clear the search state so that if will start from the beginning again. - void reset_search(); - - // Setup the search to find the device type 'family_code' on the next call - // to search(*newAddr) if it is present. - void target_search(uint8_t family_code); - - // Look for the next device. Returns 1 if a new address has been - // returned. A zero might mean that the bus is shorted, there are - // no devices, or you have already retrieved all of them. It - // might be a good idea to check the CRC to make sure you didn't - // get garbage. The order is deterministic. You will always get - // the same devices in the same order. - uint8_t search(uint8_t *newAddr, bool search_mode = true); -#endif - -#if ONEWIRE_CRC - // Compute a Dallas Semiconductor 8 bit CRC, these are used in the - // ROM and scratchpad registers. - static uint8_t crc8(const uint8_t *addr, uint8_t len); - #if ONEWIRE_CRC16 - // Compute the 1-Wire CRC16 and compare it against the received CRC. - static bool - check_crc16(const uint8_t *input, uint16_t len, const uint8_t *inverted_crc, uint16_t crc = 0); - // Compute a Dallas Semiconductor 16 bit CRC. - static uint16_t crc16(const uint8_t *input, uint16_t len, uint16_t crc = 0); - #endif -#endif -}; -} // namespace onewire -#endif \ No newline at end of file diff --git a/libraries/OneWire/src/util/OneWireSW.cpp b/libraries/OneWire/src/util/OneWireSW.cpp deleted file mode 100644 index 8be992a3..00000000 --- a/libraries/OneWire/src/util/OneWireSW.cpp +++ /dev/null @@ -1,137 +0,0 @@ -#include -#include "OneWireSW.h" - -#define IFX_ONEWIRE_MODE_OD 0xC0C0C0C0 -#define IFX_ONEWIRE_PINOUTPUT *mPortModeReg |= mPinModeMask & IFX_ONEWIRE_MODE_OD -#define IFX_ONEWIRE_PININPUT *mPortModeReg &= ~mPinModeMask -#define IFX_ONEWIRE_PINOUTLOW *mPortOutReg &= ~mPinMask -#define IFX_ONEWIRE_PINOUTHIGH *mPortOutReg |= mPinMask -#define IFX_ONEWIRE_PINREAD ((*mPortInReg & mPinMask) > 0) - -namespace onewire { - -OneWireSW::OneWireSW(uint8_t pin, const Timing_t *timing) - : OneWireImpl() { - if (!isValid(timing)) { - timing = &timingStd; - } - mLowtimeShort = timing->lowtimeShort; - mHightimeShort = timing->bitDuration - timing->lowtimeShort; - mLowtimeLong = timing->lowtimeLong; - mHightimeLong = timing->bitDuration - timing->lowtimeLong; - mWaitBeforeCheck = timing->checkAfter - timing->lowtimeShort; - mWaitAfterCheck = timing->bitDuration - timing->checkAfter; - mResetDuration = timing->resetDuration; - - mActive = FALSE; - mPortOutReg = &(mapping_port_pin[pin].port->OUT); - mPortInReg = &(mapping_port_pin[pin].port->IN); - mPortModeReg = &(mapping_port_pin[pin].port->IOCR[mapping_port_pin[pin].pin >> 2]); - mPinMask = 1 << mapping_port_pin[pin].pin; - mPinModeMask = 0xF8 << ((mapping_port_pin[pin].pin & 0x03) << 3); -} - -OneWireSW::~OneWireSW() { end(); } - -void OneWireSW::begin(void) { - IFX_ONEWIRE_PININPUT; - IFX_ONEWIRE_PINOUTHIGH; - IFX_ONEWIRE_PINOUTPUT; - mActive = TRUE; - // reset(); -} - -void OneWireSW::end(void) { - IFX_ONEWIRE_PININPUT; - mActive = FALSE; -} - -uint8_t OneWireSW::reset(void) { - noInterrupts(); - IFX_ONEWIRE_PINOUTLOW; - delayMicroseconds(mResetDuration); - IFX_ONEWIRE_PINOUTHIGH; - delayMicroseconds(mHightimeShort + mWaitBeforeCheck); - // test if slave holds the line down to indicate presence - uint8_t ret = !IFX_ONEWIRE_PINREAD; - // wait for the end of the presence pulse - delayMicroseconds(mResetDuration / 2); - interrupts(); - // bus should already have come up - // if it does not come up return 0 to indicate a short circuit - if (IFX_ONEWIRE_PINREAD) { - // return 1 if slave has indicated presence, 0 otherwise - return ret; - } else { - return 0; - } -} - -void OneWireSW::write(uint8_t v, uint8_t power /* = 0 */) { - for (uint8_t i = 0x01; i > 0; i <<= 1) { - write_bit((v & i) ? 1 : 0); - } - // We don't have to care about powering and depowering on XMC controllers - // We are using open-drain outputs with pull-ups to prevent short circuits. -} - -void OneWireSW::write_bytes(const uint8_t *buf, uint16_t count, bool power /* = 0 */) { - for (uint8_t i = 0; i < count; i++) { - write(buf[i]); - } - // We don't have to care about powering and depowering on XMC controllers - // We are using open-drain outputs with pull-ups to prevent short circuits. -} - -uint8_t OneWireSW::read(void) { - uint8_t ret = 0; - for (uint8_t i = 0x01; i > 0; i <<= 1) { - if (read_bit()) { - ret |= i; - } - } - return ret; -} - -void OneWireSW::read_bytes(uint8_t *buf, uint16_t count) { - for (uint8_t i = 0; i < count; i++) { - buf[i] = read(); - } -} - -void OneWireSW::write_bit(uint8_t v) { - noInterrupts(); - if (v & 0x01) { - IFX_ONEWIRE_PINOUTLOW; - delayMicroseconds(mLowtimeShort); - IFX_ONEWIRE_PINOUTHIGH; - delayMicroseconds(mHightimeShort); - } else { - IFX_ONEWIRE_PINOUTLOW; - delayMicroseconds(mLowtimeLong); - IFX_ONEWIRE_PINOUTHIGH; - delayMicroseconds(mHightimeLong); - } - interrupts(); -} - -uint8_t OneWireSW::read_bit(void) { - uint8_t ret; - noInterrupts(); - IFX_ONEWIRE_PINOUTLOW; - delayMicroseconds(mLowtimeShort); - IFX_ONEWIRE_PINOUTHIGH; - delayMicroseconds(mWaitBeforeCheck); - // test if slave holds the line down to send a 0 - ret = IFX_ONEWIRE_PINREAD; - delayMicroseconds(mWaitAfterCheck); - interrupts(); - return ret; -} - -void OneWireSW::depower(void) { - // We don't have to care about powering and depowering on XMC controllers - // We are using open-drain outputs with pull-ups to prevent short circuits. -} - -} // namespace onewire diff --git a/libraries/OneWire/src/util/OneWireSW.h b/libraries/OneWire/src/util/OneWireSW.h deleted file mode 100644 index d0fb6f28..00000000 --- a/libraries/OneWire/src/util/OneWireSW.h +++ /dev/null @@ -1,44 +0,0 @@ -#ifndef ONEWIRE_SW_H -#define ONEWIRE_SW_H - -#include "OneWireTiming.h" -#include "OneWireImpl.h" - -namespace onewire { -class OneWireSW : public OneWireImpl { -private: - // implementation-specific pin description - uint8_t mActive; - uint32_t mPinMask; - volatile uint32_t *mPortInReg; - volatile uint32_t *mPortOutReg; - volatile uint32_t *mPortModeReg; - uint32_t mPinModeMask; - - // implementation-specific timing description - uint16_t mLowtimeShort; - uint16_t mHightimeShort; - uint16_t mLowtimeLong; - uint16_t mHightimeLong; - uint16_t mWaitBeforeCheck; - uint16_t mWaitAfterCheck; - uint16_t mResetDuration; - -public: - OneWireSW(uint8_t pin, const Timing_t *timing); - ~OneWireSW(); - // begin and end do not appear in the original version - // they are called automatically in our implementation - virtual void begin(void) override; - virtual void end(void) override; - virtual uint8_t reset(void) override; - virtual void write(uint8_t v, uint8_t power = 0) override; - virtual void write_bytes(const uint8_t *buf, uint16_t count, bool power = 0) override; - virtual uint8_t read(void) override; - virtual void read_bytes(uint8_t *buf, uint16_t count) override; - virtual void write_bit(uint8_t v) override; - virtual uint8_t read_bit(void) override; - virtual void depower(void) override; -}; -} // namespace onewire -#endif \ No newline at end of file diff --git a/libraries/OneWire/src/util/OneWireSettings.h b/libraries/OneWire/src/util/OneWireSettings.h deleted file mode 100644 index eacb4da3..00000000 --- a/libraries/OneWire/src/util/OneWireSettings.h +++ /dev/null @@ -1,46 +0,0 @@ -#ifndef ONEWIRE_SETTINGS_H -#define ONEWIRE_SETTINGS_H - -// You can exclude certain features from OneWire. In theory, this -// might save some space. In practice, the compiler automatically -// removes unused code (technically, the linker, using -fdata-sections -// and -ffunction-sections when compiling, and Wl,--gc-sections -// when linking), so most of these will not result in any code size -// reduction. Well, unless you try to use the missing features -// and redesign your program to not need them! ONEWIRE_CRC8_TABLE -// is the exception, because it selects a fast but large algorithm -// or a small but slow algorithm. - -// you can exclude onewire_search by defining that to 0 -#ifndef ONEWIRE_SEARCH - #define ONEWIRE_SEARCH 1 -#endif - -// You can exclude CRC checks altogether by defining this to 0 -#ifndef ONEWIRE_CRC - #define ONEWIRE_CRC 1 -#endif - -// Select the table-lookup method of computing the 8-bit CRC -// by setting this to 1. The lookup table enlarges code size by -// about 250 bytes. It does NOT consume RAM (but did in very -// old versions of OneWire). If you disable this, a slower -// but very compact algorithm is used. -#ifndef ONEWIRE_CRC8_TABLE - #define ONEWIRE_CRC8_TABLE 1 -#endif - -// You can allow 16-bit CRC checks by defining this to 1 -// (Note that ONEWIRE_CRC must also be 1.) -#ifndef ONEWIRE_CRC16 - #define ONEWIRE_CRC16 1 -#endif - -#ifndef FALSE - #define FALSE 0 -#endif -#ifndef TRUE - #define TRUE 1 -#endif - -#endif /*ONEWIRE_SETTINGS_H*/ \ No newline at end of file diff --git a/libraries/OneWire/src/util/OneWireTiming.cpp b/libraries/OneWire/src/util/OneWireTiming.cpp deleted file mode 100644 index c6777869..00000000 --- a/libraries/OneWire/src/util/OneWireTiming.cpp +++ /dev/null @@ -1,18 +0,0 @@ -#include -#include "OneWireTiming.h" - -namespace onewire { - -uint8_t isValid(const Timing_t *timing) { - if (timing->lowtimeShort < timing->checkAfter && timing->checkAfter < timing->lowtimeLong && - timing->lowtimeLong < timing->bitDuration && timing->bitDuration < timing->resetDuration) { - return TRUE; - } else { - return FALSE; - } -} - -Timing_t timingStd = {10, 65, 20, 70, 480}; -Timing_t timingOverdrive = {1, 8, 5, 15, 52}; - -} // namespace onewire \ No newline at end of file diff --git a/libraries/OneWire/src/util/OneWireTiming.h b/libraries/OneWire/src/util/OneWireTiming.h deleted file mode 100644 index 2e889ef2..00000000 --- a/libraries/OneWire/src/util/OneWireTiming.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef ONEWIRE_TIMING_H -#define ONEWIRE_TIMING_H - -namespace onewire { -typedef struct { - uint16_t lowtimeShort; - uint16_t lowtimeLong; - uint16_t checkAfter; - uint16_t bitDuration; - uint16_t resetDuration; -} Timing_t; - -uint8_t isValid(const Timing_t *timing); - -extern Timing_t timingStd; -extern Timing_t timingOverdrive; -} // namespace onewire -#endif \ No newline at end of file diff --git a/libraries/RTC/examples/AlarmRTC/AlarmRTC.ino b/libraries/RTC/examples/AlarmRTC/AlarmRTC.ino index 4552074e..4d6da3c6 100644 --- a/libraries/RTC/examples/AlarmRTC/AlarmRTC.ino +++ b/libraries/RTC/examples/AlarmRTC/AlarmRTC.ino @@ -1,15 +1,15 @@ /* Simple RTC Alarm for XMC Boards - Demonstrates how to set an RTC alarm for the XMC4700 Relax Kit V1 + Demonstrates how to set an RTC alarm for the KIT_XMC47_RELAX */ /* Board Check - This library can currently only be used with the XMC4700 Relax Kit + This library can currently only be used with the KIT_XMC47_RELAX If you modify the library to work with other XMC versions, remove the following lines */ #if (UC_FAMILY != XMC4) -#error This XMC board is not supported, only XMC4700 Relax Kit is supported +#error This XMC board is not supported, only KIT_XMC47_RELAX is supported #endif // End of Board Check diff --git a/libraries/RTC/examples/SimpleRTC/SimpleRTC.ino b/libraries/RTC/examples/SimpleRTC/SimpleRTC.ino index 8ecc97c1..d15d1abc 100644 --- a/libraries/RTC/examples/SimpleRTC/SimpleRTC.ino +++ b/libraries/RTC/examples/SimpleRTC/SimpleRTC.ino @@ -1,5 +1,5 @@ /* - Simple RTC for XMC4700 Relax Kit V1 + Simple RTC for KIT_XMC47_RELAX Demonstrates the use of the RTC library for the XMC4700 */ diff --git a/libraries/SPI/examples/SPI_MOSI_to_MISO_SameDevice/SPI_MOSI_to_MISO_SameDevice.ino b/libraries/SPI/examples/SPI_MOSI_to_MISO_SameDevice/SPI_MOSI_to_MISO_SameDevice.ino index 126086f1..c1c602d8 100644 --- a/libraries/SPI/examples/SPI_MOSI_to_MISO_SameDevice/SPI_MOSI_to_MISO_SameDevice.ino +++ b/libraries/SPI/examples/SPI_MOSI_to_MISO_SameDevice/SPI_MOSI_to_MISO_SameDevice.ino @@ -28,4 +28,4 @@ void loop() digitalWrite(LED1, LOW); delay(1000); -} +} \ No newline at end of file diff --git a/libraries/SPI/examples/spi_master/spi_master.ino b/libraries/SPI/examples/spi_master/spi_master.ino new file mode 100644 index 00000000..df5788e0 --- /dev/null +++ b/libraries/SPI/examples/spi_master/spi_master.ino @@ -0,0 +1,33 @@ +#include + +void setup() { + // Start the SPI bus as a master with default settings: (1 MHz, MSBFIRST, SPI_MODE0) + SPI.begin(); + Serial.begin(9600); + pinMode(SS, OUTPUT); + + // Optional: Set SPI settings + SPI.beginTransaction(SPISettings(1000000, MSBFIRST, SPI_MODE0)); + digitalWrite(SS, HIGH); + Serial.println("SPI Master Started"); +} + +void loop() { + uint8_t dataToSend = 99; + uint8_t receivedData; + + // Make a transfer and get the response from the slave + digitalWrite(SS, LOW); + delayMicroseconds(10); + receivedData = SPI.transfer(dataToSend); + delayMicroseconds(10); + + digitalWrite(SS, HIGH); + + Serial.print("Data Sent: "); + Serial.println(dataToSend); + Serial.print("Data Received: "); + Serial.println(receivedData); + + delay(1000); +} \ No newline at end of file diff --git a/libraries/SPI/src/HW_SPI.cpp b/libraries/SPI/src/HW_SPI.cpp index 40a67bc1..8093deee 100644 --- a/libraries/SPI/src/HW_SPI.cpp +++ b/libraries/SPI/src/HW_SPI.cpp @@ -1,40 +1,17 @@ -/* - * SPI Master library. - * Copyright (c) 2015 Arduino LLC - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * Copyright (c) 2018 Infineon Technologies AG - * This library has been modified for the XMC microcontroller series. - */ - -//**************************************************************************** -// @Project Includes -//**************************************************************************** #include "SPI.h" +#include + #if !defined(USE_SW_SPI) #include "Wire.h" // swap SPI_default and SPI_for_xmc_SD if desired by user #if defined(USE_XMC_RELAX_KIT_SD) && defined(XMC_SPI_for_xmc_SD) -SPIClass SPI(&XMC_SPI_default); -SPIClass SPI1(&XMC_SPI_for_xmc_SD); +XMCSPIClass SPI(&XMC_SPI_default); +XMCSPIClass SPI1(&XMC_SPI_for_xmc_SD); #else // normal behaviour -SPIClass SPI(&XMC_SPI_default); +XMCSPIClass SPI(&XMC_SPI_default); #if (NUM_SPI > 1) -SPIClass SPI1(&XMC_SPI_1); +XMCSPIClass SPI1(&XMC_SPI_1); #endif #endif uint8_t SS = PIN_SPI_SS; @@ -43,24 +20,30 @@ uint8_t MISO = PIN_SPI_MISO; uint8_t SCK = PIN_SPI_SCK; #if (NUM_SPI > 2) -SPIClass SPI2(&XMC_SPI_2); +XMCSPIClass SPI2(&XMC_SPI_2); #if (NUM_SPI > 3) -SPIClass SPI3(&XMC_SPI_3); +XMCSPIClass SPI3(&XMC_SPI_3); #if (NUM_SPI > 4) -SPIClass SPI4(&XMC_SPI_4); +XMCSPIClass SPI4(&XMC_SPI_4); #endif #endif #endif -SPISettings DEFAULT_SPI_SETTINGS; - //**************************************************************************** // @Local Functions //**************************************************************************** // Public Methods ////////////////////////////////////////////////////////////// +XMCSPIClass::XMCSPIClass(XMC_SPI_t *conf) + : XMC_SPI_config(conf), + initialized(false), + interruptMode(SPI_IMODE_NONE), + interruptSave(0), + interruptMask(0) {} -void SPIClass::begin() { +XMCSPIClass::~XMCSPIClass() { end(); } + +void XMCSPIClass::begin() { // Check if desire USIC channel is already in use if ((XMC_SPI_config->channel->CCR & USIC_CH_CCR_MODE_Msk) == XMC_USIC_CH_OPERATING_MODE_I2C) { Wire.end(); @@ -68,14 +51,14 @@ void SPIClass::begin() { init(); - setBitOrder(DEFAULT_SPI_SETTINGS.bitOrder); + setBitOrder(_settings.getBitOrder()); - setDataMode(DEFAULT_SPI_SETTINGS.dataMode); + setDataMode(_settings.getDataMode()); - XMC_SPI_CH_SetBaudrate(XMC_SPI_config->channel, DEFAULT_SPI_SETTINGS.clockFreq); + XMC_SPI_CH_SetBaudrate(XMC_SPI_config->channel, _settings.getClockFreq()); } -void SPIClass::init() { +void XMCSPIClass::init() { if (initialized) { return; } @@ -108,7 +91,7 @@ void SPIClass::init() { initialized = true; } -void SPIClass::end() { +void XMCSPIClass::end() { // Only disable HW when USIC is used for SPI if ((XMC_SPI_config->channel->CCR & USIC_CH_CCR_MODE_Msk) == XMC_USIC_CH_OPERATING_MODE_SPI) { XMC_SPI_CH_Stop(XMC_SPI_config->channel); @@ -123,31 +106,29 @@ void SPIClass::end() { initialized = false; } -/* // Function not used here -void SPIClass::usingInterrupt(int interruptNumber) -{ +void XMCSPIClass::usingInterrupt(int interruptNumber) {} -} -*/ +void XMCSPIClass::notUsingInterrupt(int interruptNumber) {} -void SPIClass::beginTransaction(SPISettings settings) { +void XMCSPIClass::beginTransaction(arduino::SPISettings settings) { // Check if desire USIC channel is already in use if ((XMC_SPI_config->channel->CCR & USIC_CH_CCR_MODE_Msk) != XMC_USIC_CH_OPERATING_MODE_SPI) { SPI.begin(); } - setBitOrder(settings.bitOrder); - setDataMode(settings.dataMode); - XMC_SPI_CH_SetBaudrate(XMC_SPI_config->channel, settings.clockFreq); + _settings = settings; + setBitOrder(settings.getBitOrder()); + setDataMode(static_cast(settings.getDataMode())); + XMC_SPI_CH_SetBaudrate(XMC_SPI_config->channel, settings.getClockFreq()); // TODO: Do sth with SS? } -void SPIClass::endTransaction(void) { +void XMCSPIClass::endTransaction(void) { // TODO: inTransactionFlag and interrupt not use } -void SPIClass::setBitOrder(uint8_t order) { +void XMCSPIClass::setBitOrder(BitOrder order) { if (order == LSBFIRST) { XMC_SPI_CH_SetBitOrderLsbFirst(XMC_SPI_config->channel); } else { @@ -155,7 +136,7 @@ void SPIClass::setBitOrder(uint8_t order) { } } -void SPIClass::setDataMode(uint8_t mode) { +void XMCSPIClass::setDataMode(uint8_t mode) { switch (mode) { case SPI_MODE0: // Low if inactive, transmit on falling clock, receive on raising clock edge @@ -190,7 +171,7 @@ void SPIClass::setDataMode(uint8_t mode) { } } -void SPIClass::setClockDivider(uint8_t div) { +void XMCSPIClass::setClockDivider(uint8_t div) { switch (div) { case SPI_CLOCK_DIV2: XMC_SPI_CH_SetBaudrate(XMC_SPI_config->channel, 8000000U); @@ -225,7 +206,7 @@ void SPIClass::setClockDivider(uint8_t div) { } } -uint8_t SPIClass::transfer(uint8_t data_out) { +byte XMCSPIClass::transfer(uint8_t data_out) { uint8_t data_in = 0; /* Clear RBF0 */ @@ -255,11 +236,44 @@ uint8_t SPIClass::transfer(uint8_t data_out) { return data_in; } -void SPIClass::attachInterrupt() { +void XMCSPIClass::transfer(void *buf, size_t count) { + uint8_t *buffer = reinterpret_cast(buf); + for (size_t index = 0; index < count; index++) { + *buffer = transfer(*buffer); + buffer++; + } +} + +uint16_t XMCSPIClass::transfer16(uint16_t data) { + union { + uint16_t val; + + struct { + uint8_t lsb; + uint8_t msb; + }; + } data_in_out; + + // Split 16-bit word into two bytes: + data_in_out.val = data; + + if (_settings.getBitOrder() == LSBFIRST) { + data_in_out.lsb = transfer(data_in_out.lsb); + data_in_out.msb = transfer(data_in_out.msb); + } else { + data_in_out.msb = transfer(data_in_out.msb); + data_in_out.lsb = transfer(data_in_out.lsb); + } + + // Combine the two received bytes into a 16-bit word: + return data_in_out.val; +} + +void XMCSPIClass::attachInterrupt() { // Should be enableInterrupt() } -void SPIClass::detachInterrupt() { +void XMCSPIClass::detachInterrupt() { // Should be disableInterrupt() } @@ -267,4 +281,4 @@ void SPIClass::detachInterrupt() { //**************************************************************************** // END OF FILE -//**************************************************************************** +//**************************************************************************** \ No newline at end of file diff --git a/libraries/SPI/src/SPI.h b/libraries/SPI/src/SPI.h index aa83462e..ff6209d0 100644 --- a/libraries/SPI/src/SPI.h +++ b/libraries/SPI/src/SPI.h @@ -1,31 +1,11 @@ -/* - * SPI Master library. - * Copyright (c) 2015 Arduino LLC - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * Copyright (c) 2018 Infineon Technologies AG - * This library has been modified for the XMC microcontroller series. - */ - #ifndef _SPI_H_INCLUDED #define _SPI_H_INCLUDED //**************************************************************************** // @Project Includes //**************************************************************************** +#include "api/HardwareSPI.h" +#include "xmc_spi.h" #include //**************************************************************************** @@ -34,22 +14,8 @@ // Define USE_SW_SPI to use the software SPI(not verified) // #define USE_SW_SPI -// Define USE_XMC_RELAX_KIT_SD allows to use the SD Lib to communicate with a SD Card over -// the on-board SD Card Slot. This feature is only available on XMC4700 RelaxKits. -#if defined(XMC4700_Relax_Kit) - #define USE_XMC_RELAX_KIT_SD -#endif - -#define SPI_MODE0 0x00 -#define SPI_MODE1 0x01 -#define SPI_MODE2 0x02 -#define SPI_MODE3 0x03 - #define SPI_IMODE_NONE 0x00 -#define MSBFIRST 0x00 -#define LSBFIRST 0x01 - #define ARDUINO_SPI_CLOCK 16000000U #define SPI_CLOCK_DIV2 2 @@ -64,50 +30,15 @@ #include "SW_SPI.h" #endif -// #define pin_cs 10 -// -// #if defined(XMC1100_XMC2GO) || defined(XMC1100_H_BRIDGE2GO) -// #define pin_cs 3 - -// #elif defined(XMC4400_Platform2GO) -/// #define pin_cs_slot_1 95 -// #define pin_cs_slot_2 96 - -// #endif - -//**************************************************************************** -// @Class Definitions -//**************************************************************************** -class SPISettings { -public: - SPISettings(uint32_t cF, uint8_t bO, uint8_t dM) { - clockFreq = cF; - bitOrder = bO; - dataMode = dM; - } - - SPISettings() { - clockFreq = 4000000; - bitOrder = MSBFIRST; - dataMode = SPI_MODE0; - } - - uint32_t clockFreq; - uint8_t bitOrder; - uint8_t dataMode; -}; - -class SPIClass { +class XMCSPIClass : public arduino::HardwareSPI { public: // Constructors for HW SPI #if !defined(USE_SW_SPI) - SPIClass() { - // default SPI - XMC_SPI_config = &XMC_SPI_default; - } - - SPIClass(XMC_SPI_t *conf) { XMC_SPI_config = conf; } + XMCSPIClass() + : XMCSPIClass(&XMC_SPI_default) {} + XMCSPIClass(XMC_SPI_t *conf); + ~XMCSPIClass(); // Constructors for SW SPI #else SPIClass() { @@ -136,27 +67,27 @@ class SPIClass { } #endif - uint8_t transfer(uint8_t data); - inline uint16_t transfer16(uint16_t data); - inline void transfer(void *buf, size_t count); + virtual byte transfer(uint8_t data); + virtual uint16_t transfer16(uint16_t data); + virtual void transfer(void *buf, size_t count); // Transaction Functions // Function not used here // void usingInterrupt(int interruptNumber); - void beginTransaction(SPISettings settings); - void endTransaction(void); + virtual void beginTransaction(SPISettings settings); + virtual void endTransaction(void); // SPI Configuration methods - void attachInterrupt(); - void detachInterrupt(); + virtual void attachInterrupt(); + virtual void detachInterrupt(); - static void usingInterrupt(uint8_t interruptNumber) {}; - static void notUsingInterrupt(uint8_t interruptNumber) {}; + virtual void usingInterrupt(int interruptNumber); + virtual void notUsingInterrupt(int interruptNumber); - void begin(); - void end(); + virtual void begin(); + virtual void end(); - void setBitOrder(uint8_t order); + void setBitOrder(BitOrder order); void setDataMode(uint8_t mode); void setClockDivider(uint8_t div); @@ -166,7 +97,10 @@ class SPIClass { #if !defined(USE_SW_SPI) XMC_SPI_t *XMC_SPI_config; + arduino::SPISettings const DEFAULT_SPI_SETTINGS = + arduino::SPISettings(ARDUINO_SPI_CLOCK, MSBFIRST, SPI_MODE0); + arduino::SPISettings _settings = arduino::SPISettings(); // Config for SW SPI #else uint8_t mosi_pin; @@ -182,35 +116,18 @@ class SPIClass { uint32_t interruptMask; }; -extern SPIClass SPI; +extern XMCSPIClass SPI; #if (NUM_SPI > 1) -extern SPIClass SPI1; +extern XMCSPIClass SPI1; #if (NUM_SPI > 2) -extern SPIClass SPI2; +extern XMCSPIClass SPI2; #if (NUM_SPI > 3) -extern SPIClass SPI3; +extern XMCSPIClass SPI3; #if (NUM_SPI > 4) -extern SPIClass SPI4; +extern XMCSPIClass SPI4; #endif #endif #endif #endif -void SPIClass::transfer(void *buf, size_t count) { - uint8_t *buffer = (uint8_t *)buf; - for (size_t index = 0; index < count; index++) { - buffer[index] = transfer(buffer[index]); - } -} - -uint16_t SPIClass::transfer16(uint16_t data) { - uint8_t data_out_msb = (uint8_t)((data >> 8) & 0xFF); - uint8_t data_out_lsb = (uint8_t)(data & 0xFF); - - uint8_t data_in_msb = transfer(data_out_msb); - uint8_t data_in_lsb = transfer(data_out_lsb); - - return (uint16_t)(((uint16_t)data_in_msb << 8) | (data_in_lsb)); -} - -#endif /* _SPI_H_INCLUDED */ +#endif /* _SPI_H_INCLUDED */ \ No newline at end of file diff --git a/libraries/Wire/src/Wire.cpp b/libraries/Wire/src/Wire.cpp index 1ab8ecf8..a23c7d2f 100644 --- a/libraries/Wire/src/Wire.cpp +++ b/libraries/Wire/src/Wire.cpp @@ -1,51 +1,6 @@ -/* - * TwoWire.h - TWI/I2C library for Arduino & Wiring - * Copyright (c) 2006 Nicholas Zambetti. All right reserved. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * Modified 2012 by Todd Krein (todd@krein.org) to implement repeated starts - * - * Copyright (c) 2018 Infineon Technologies AG - * This library has been modified for the XMC microcontroller series. - */ - -//**************************************************************************** -// @Project Includes -//**************************************************************************** -extern "C" { -#include -#include -#include -#include "xmc_gpio.h" -} - +#include "Arduino.h" #include "Wire.h" -#include "SPI.h" -//**************************************************************************** -// @Global Variables -//**************************************************************************** - -// Initialize Class Variables ////////////////////////////////////////////////// - -//**************************************************************************** -// @Local Functions -//**************************************************************************** - -// Constructors //////////////////////////////////////////////////////////////// TwoWire::TwoWire(XMC_I2C_t *conf) { XMC_I2C_config = conf; @@ -59,35 +14,31 @@ TwoWire::TwoWire(XMC_I2C_t *conf) { slaveAddress = 0; txAddress = 0; - rxBufferIndex = 0; - rxBufferLength = 0; - txBufferIndex = 0; - txBufferLength = 0; - pre_rxBufferCount = 0; + user_onReceive = nullptr; + user_onRequest = nullptr; + rx_ringBuffer.clear(); + tx_ringBuffer.clear(); + pre_rx_ringBuffer.clear(); } -// Public Methods ////////////////////////////////////////////////////////////// - void TwoWire::begin(void) { + // To-Do for future work need to check // Check if desire USIC channel is already in use - if ((XMC_I2C_config->channel->CCR & USIC_CH_CCR_MODE_Msk) == XMC_USIC_CH_OPERATING_MODE_SPI) { - SPI.end(); - } - + // if ((XMC_I2C_config->channel->CCR & USIC_CH_CCR_MODE_Msk) == XMC_USIC_CH_OPERATING_MODE_SPI) + // { + // SPI.end(); + // } hasError = false; isMaster = true; XMC_I2C_CH_Init(XMC_I2C_config->channel, &(XMC_I2C_config->channel_config)); - XMC_USIC_CH_SetInputSource(XMC_I2C_config->channel, XMC_USIC_CH_INPUT_DX0, XMC_I2C_config->input_source_dx0); XMC_USIC_CH_SetInputSource(XMC_I2C_config->channel, XMC_USIC_CH_INPUT_DX1, XMC_I2C_config->input_source_dx1); - /* configure i2c tx fifo */ XMC_USIC_CH_TXFIFO_Configure(XMC_I2C_config->channel, 16, XMC_USIC_CH_FIFO_SIZE_16WORDS, (uint32_t)15); - /* configure i2c rx fifo */ XMC_USIC_CH_RXFIFO_Configure(XMC_I2C_config->channel, 0, XMC_USIC_CH_FIFO_SIZE_16WORDS, (uint32_t)(15)); @@ -95,6 +46,7 @@ void TwoWire::begin(void) { XMC_USIC_CH_SetInterruptNodePointer(XMC_I2C_config->channel, XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL, XMC_I2C_config->protocol_irq_service_request); + NVIC_SetPriority((IRQn_Type)XMC_I2C_config->protocol_irq_num, 3U); NVIC_EnableIRQ((IRQn_Type)XMC_I2C_config->protocol_irq_num); @@ -111,15 +63,16 @@ void TwoWire::begin(void) { } void TwoWire::begin(uint8_t address) { - // Check if desire USIC channel is already in use - if ((XMC_I2C_config->channel->CCR & USIC_CH_CCR_MODE_Msk) == XMC_USIC_CH_OPERATING_MODE_SPI) { - SPI.end(); - } + // To-Do for future work need to check + // Check if desire USIC channel is already in use + // if ((XMC_I2C_config->channel->CCR & USIC_CH_CCR_MODE_Msk) == XMC_USIC_CH_OPERATING_MODE_SPI) + // { + // SPI.end(); + // } isMaster = false; slaveAddress = address; XMC_I2C_CH_Init(XMC_I2C_config->channel, &(XMC_I2C_config->channel_config)); - XMC_USIC_CH_SetInputSource(XMC_I2C_config->channel, XMC_USIC_CH_INPUT_DX0, XMC_I2C_config->input_source_dx0); XMC_USIC_CH_SetInputSource(XMC_I2C_config->channel, XMC_USIC_CH_INPUT_DX1, @@ -134,13 +87,13 @@ void TwoWire::begin(uint8_t address) { XMC_USIC_CH_SetInterruptNodePointer(XMC_I2C_config->channel, XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL, XMC_I2C_config->protocol_irq_service_request); + NVIC_SetPriority((IRQn_Type)XMC_I2C_config->slave_receive_irq_num, 3U); NVIC_EnableIRQ((IRQn_Type)XMC_I2C_config->slave_receive_irq_num); NVIC_SetPriority((IRQn_Type)XMC_I2C_config->protocol_irq_num, 3U); NVIC_EnableIRQ((IRQn_Type)XMC_I2C_config->protocol_irq_num); XMC_I2C_CH_SetSlaveAddress(XMC_I2C_config->channel, (address << 1)); - /*Flush receive buffer*/ (void)XMC_I2C_CH_GetReceivedData(XMC_I2C_config->channel); (void)XMC_I2C_CH_GetReceivedData(XMC_I2C_config->channel); @@ -163,10 +116,7 @@ void TwoWire::begin(uint8_t address) { &(XMC_I2C_config->scl_config)); } -void TwoWire::begin(int address) { begin((uint8_t)address); } - void TwoWire::end(void) { - // Only disable HW when USIC is used for I2C if ((XMC_I2C_config->channel->CCR & USIC_CH_CCR_MODE_Msk) == XMC_USIC_CH_OPERATING_MODE_I2C) { XMC_I2C_CH_Stop(XMC_I2C_config->channel); @@ -183,7 +133,6 @@ void TwoWire::end(void) { XMC_I2C_CH_DisableEvent(XMC_I2C_config->channel, (uint32_t)((uint32_t)XMC_I2C_CH_EVENT_SLAVE_READ_REQUEST | (uint32_t)XMC_I2C_CH_EVENT_STOP_CONDITION_RECEIVED)); - NVIC_DisableIRQ((IRQn_Type)XMC_I2C_config->slave_receive_irq_num); XMC_I2C_CH_DisableEvent(XMC_I2C_config->channel, (uint32_t)((uint32_t)XMC_I2C_CH_EVENT_STANDARD_RECEIVE | @@ -191,7 +140,6 @@ void TwoWire::end(void) { } flush(); - /* Disable i2c tx fifo */ XMC_USIC_CH_TXFIFO_Configure(XMC_I2C_config->channel, 16, XMC_USIC_CH_FIFO_DISABLED, (uint32_t)15); @@ -204,35 +152,19 @@ void TwoWire::end(void) { void TwoWire::setClock(uint32_t clock) { XMC_I2C_CH_SetBaudrate(XMC_I2C_config->channel, clock); } -uint8_t TwoWire::requestFrom( - uint8_t address, uint8_t quantity, uint32_t iaddress, uint8_t isize, uint8_t sendStop) { - uint32_t StatusFlag; - beginTransmission(address); - - // clamp to buffer length +size_t TwoWire::requestFrom(uint8_t address, size_t quantity, bool sendStop) { + if (quantity == 0) { + if (sendStop) { + XMC_I2C_CH_MasterStop(XMC_I2C_config->channel); + } + return 0; + } if (quantity > BUFFER_LENGTH) { quantity = BUFFER_LENGTH; } - // send internal address; this mode allows sending a repeated start to access - // some devices' internal registers. This function is executed by the hardware - // TWI module on other processors (for example Due's TWI_IADR and TWI_MMR registers) - if (isize > 0) { - - // the maximum size of internal address is 3 bytes - if (isize > 3) { - isize = 3; - } - - // write internal register address - most significant byte first - while (isize-- > 0) { - write((uint8_t)(iaddress >> (isize * 8))); - } - endTransmission(false); - - XMC_I2C_CH_MasterRepeatedStart(XMC_I2C_config->channel, (txAddress << 1), - XMC_I2C_CH_CMD_READ); - } else if (inRepStart) { + rx_ringBuffer.clear(); + if (inRepStart) { XMC_I2C_CH_MasterRepeatedStart(XMC_I2C_config->channel, (txAddress << 1), XMC_I2C_CH_CMD_READ); inRepStart = false; @@ -240,104 +172,78 @@ uint8_t TwoWire::requestFrom( XMC_I2C_CH_MasterStart(XMC_I2C_config->channel, (txAddress << 1), XMC_I2C_CH_CMD_READ); } - timeout = WIRE_COMMUNICATION_TIMEOUT; - // wait for ACK or timeout incase no ACK is received, a time-based wait-state is added since XMC - // devices run at variable frequencies - while (((XMC_I2C_CH_GetStatusFlag(XMC_I2C_config->channel) & - XMC_I2C_CH_STATUS_FLAG_ACK_RECEIVED) == 0U)) { - delay(1); - timeout--; - if (timeout == 0) { - break; + uint32_t start = millis(); + while (!(XMC_I2C_CH_GetStatusFlag(XMC_I2C_config->channel) & + XMC_I2C_CH_STATUS_FLAG_ACK_RECEIVED)) { + if (millis() - start > timeout || hasError) { + flush(); + return 0; } } for (uint8_t count = 0; count < (quantity - 1); count++) { XMC_I2C_CH_MasterReceiveAck(XMC_I2C_config->channel); - timeout = WIRE_COMMUNICATION_TIMEOUT; + start = millis(); // Wait for Receive, leave when NACK is detected - do { - StatusFlag = XMC_I2C_CH_GetStatusFlag(XMC_I2C_config->channel); - - // Check for NACK, indicates that no slave with desired address is on the bus - if (this->hasError == true || timeout == 0) { - this->hasError = false; + while (!(XMC_I2C_CH_GetStatusFlag(XMC_I2C_config->channel) & + (XMC_I2C_CH_STATUS_FLAG_RECEIVE_INDICATION | + XMC_I2C_CH_STATUS_FLAG_ALTERNATIVE_RECEIVE_INDICATION))) { + if (millis() - start > timeout || hasError) { flush(); - return 0; + return count; } - timeout--; - } while ((StatusFlag & (XMC_I2C_CH_STATUS_FLAG_RECEIVE_INDICATION | - XMC_I2C_CH_STATUS_FLAG_ALTERNATIVE_RECEIVE_INDICATION)) == 0U); + } XMC_I2C_CH_ClearStatusFlag(XMC_I2C_config->channel, XMC_I2C_CH_STATUS_FLAG_RECEIVE_INDICATION | XMC_I2C_CH_STATUS_FLAG_ALTERNATIVE_RECEIVE_INDICATION); - - rxBuffer[count] = XMC_I2C_CH_GetReceivedData(XMC_I2C_config->channel); + uint8_t data = XMC_I2C_CH_GetReceivedData(XMC_I2C_config->channel); + if (rx_ringBuffer.isFull()) { + flush(); + return count; + } + rx_ringBuffer.store_char(data); } - XMC_I2C_CH_MasterReceiveNack(XMC_I2C_config->channel); - timeout = WIRE_COMMUNICATION_TIMEOUT; + start = millis(); // Wait for Receive, leave when NACK is detected - do { - StatusFlag = XMC_I2C_CH_GetStatusFlag(XMC_I2C_config->channel); - - // Check for NACK, indicates that no slave with desired address is on the bus - if (this->hasError == true || timeout == 0) { - this->hasError = false; + while (!(XMC_I2C_CH_GetStatusFlag(XMC_I2C_config->channel) & + (XMC_I2C_CH_STATUS_FLAG_RECEIVE_INDICATION | + XMC_I2C_CH_STATUS_FLAG_ALTERNATIVE_RECEIVE_INDICATION))) { + if (millis() - start > timeout || hasError) { flush(); - return 0; + return quantity - 1; } - timeout--; - } while ((StatusFlag & (XMC_I2C_CH_STATUS_FLAG_RECEIVE_INDICATION | - XMC_I2C_CH_STATUS_FLAG_ALTERNATIVE_RECEIVE_INDICATION)) == 0U); + } XMC_I2C_CH_ClearStatusFlag(XMC_I2C_config->channel, XMC_I2C_CH_STATUS_FLAG_RECEIVE_INDICATION | XMC_I2C_CH_STATUS_FLAG_ALTERNATIVE_RECEIVE_INDICATION); - - rxBuffer[quantity - 1] = XMC_I2C_CH_GetReceivedData(XMC_I2C_config->channel); + uint8_t data = XMC_I2C_CH_GetReceivedData(XMC_I2C_config->channel); + if (rx_ringBuffer.isFull()) { + flush(); + return quantity - 1; + } + rx_ringBuffer.store_char(data); if (sendStop) { XMC_I2C_CH_MasterStop(XMC_I2C_config->channel); - - timeout = WIRE_COMMUNICATION_TIMEOUT; + start = millis(); while (XMC_USIC_CH_GetTransmitBufferStatus(XMC_I2C_config->channel) == XMC_USIC_CH_TBUF_STATUS_BUSY) { - if (this->hasError == true || timeout == 0) { - this->hasError = false; + if (this->hasError == true || (millis() - start > timeout)) { inRepStart = false; flush(); - return 1; + return quantity - 1; // return the number of bytes received before timeout } - timeout--; } } - - // set rx buffer iterator vars - rxBufferIndex = 0; - rxBufferLength = quantity; // indicate that we are done transmitting - transmitting = 0; - - return quantity; -} - -uint8_t TwoWire::requestFrom(uint8_t address, uint8_t quantity, uint8_t sendStop) { - return requestFrom((uint8_t)address, (uint8_t)quantity, (uint32_t)0, (uint8_t)0, - (uint8_t)sendStop); + return rx_ringBuffer.available(); } -uint8_t TwoWire::requestFrom(uint8_t address, uint8_t quantity) { - return requestFrom((uint8_t)address, (uint8_t)quantity, (uint8_t) true); -} - -uint8_t TwoWire::requestFrom(int address, int quantity) { - return requestFrom((uint8_t)address, (uint8_t)quantity, (uint8_t) true); -} - -uint8_t TwoWire::requestFrom(int address, int quantity, int sendStop) { - return requestFrom((uint8_t)address, (uint8_t)quantity, (uint8_t)sendStop); +size_t TwoWire::requestFrom(uint8_t address, size_t quantity) { + return requestFrom((uint8_t)address, quantity, true); } void TwoWire::beginTransmission(uint8_t address) { @@ -348,210 +254,145 @@ void TwoWire::beginTransmission(uint8_t address) { Wire.begin(slaveAddress); } } - // indicate that we are transmitting transmitting = 1; // set address of targeted slave txAddress = address; // reset tx buffer iterator vars - txBufferIndex = 0; - txBufferLength = 0; + tx_ringBuffer.clear(); // Clear all Status Flags XMC_I2C_CH_ClearStatusFlag(XMC_I2C_config->channel, 0xFFFFFFFF); } -void TwoWire::beginTransmission(int address) { beginTransmission((uint8_t)address); } - -// -// Originally, 'endTransmission' was an f(void) function. -// It has been modified to take one parameter indicating -// whether or not a STOP should be performed on the bus. -// Calling endTransmission(false) allows a sketch to -// perform a repeated start. -// -// WARNING: Nothing in the library keeps track of whether -// the bus tenure has been properly ended with a STOP. It -// is very possible to leave the bus in a hung state if -// no call to endTransmission(true) is made. Some I2C -// devices will behave oddly if they do not see a STOP. -// -uint8_t TwoWire::endTransmission(uint8_t sendStop) { +uint8_t TwoWire::endTransmission(bool sendStop) { uint32_t StatusFlag; - XMC_I2C_CH_MasterStart(XMC_I2C_config->channel, (txAddress << 1), XMC_I2C_CH_CMD_WRITE); - - for (uint8_t count = 0; count < txBufferLength; count++) { - XMC_I2C_CH_MasterTransmit(XMC_I2C_config->channel, txBuffer[count]); - - timeout = WIRE_COMMUNICATION_TIMEOUT; + while (tx_ringBuffer.available() > 0) { + uint8_t data = tx_ringBuffer.read_char(); + XMC_I2C_CH_MasterTransmit(XMC_I2C_config->channel, data); + uint32_t start = millis(); // Wait for ACK, leave when NACK is detected do { StatusFlag = XMC_I2C_CH_GetStatusFlag(XMC_I2C_config->channel); - // Check for NACK, indicates that no slave with desired address is on the bus - if (this->hasError == true || timeout == 0) { - this->hasError = false; - inRepStart = false; + if (hasError || (millis() - start > timeout)) { flush(); - return 1; + return 5; // NACK received } - timeout--; - } while ((StatusFlag & XMC_I2C_CH_STATUS_FLAG_ACK_RECEIVED) == 0U); + } while (!(StatusFlag & XMC_I2C_CH_STATUS_FLAG_ACK_RECEIVED)); + + if (StatusFlag & XMC_I2C_CH_STATUS_FLAG_NACK_RECEIVED) { + // NACK received, slave is not present + flush(); + return 2; // NACK received + } XMC_I2C_CH_ClearStatusFlag(XMC_I2C_config->channel, XMC_I2C_CH_STATUS_FLAG_ACK_RECEIVED); } if (sendStop) { + delay(1); // Allow time for the I2C Scan XMC_I2C_CH_MasterStop(XMC_I2C_config->channel); - timeout = WIRE_COMMUNICATION_TIMEOUT; + uint32_t start = millis(); while (XMC_USIC_CH_GetTransmitBufferStatus(XMC_I2C_config->channel) == XMC_USIC_CH_TBUF_STATUS_BUSY) { - if (this->hasError == true || timeout == 0) { - this->hasError = false; - inRepStart = false; + if (this->hasError == true || (millis() - start > timeout)) { flush(); - return 1; + return 5; } - timeout--; } inRepStart = false; } else { inRepStart = true; } - - // reset tx buffer iterator vars - txBufferIndex = 0; - txBufferLength = 0; // indicate that we are done transmitting transmitting = 0; return 0; } -// This provides backwards compatibility with the original -// definition, and expected behaviour, of endTransmission -// uint8_t TwoWire::endTransmission(void) { return endTransmission(true); } -// must be called in: -// slave tx event callback -// or after beginTransmission(address) size_t TwoWire::write(uint8_t data) { if (transmitting) { - // in master transmitter mode - // don't bother if buffer is full - if (txBufferLength >= BUFFER_LENGTH) { - // TODO: setWriteError(); + if (tx_ringBuffer.isFull()) { return 0; } - // put byte in tx buffer - txBuffer[txBufferIndex] = data; - ++txBufferIndex; - // update amount in buffer - txBufferLength = txBufferIndex; - } else { - // in slave send mode - // reply to master - if ((XMC_I2C_config->channel->CCR & USIC_CH_CCR_MODE_Msk) != - XMC_USIC_CH_OPERATING_MODE_I2C) { - if (isMaster) { - Wire.begin(); - } else { - Wire.begin(slaveAddress); - } + tx_ringBuffer.store_char(data); + return 1; + } + // in slave send mode + // reply to master + if ((XMC_I2C_config->channel->CCR & USIC_CH_CCR_MODE_Msk) != XMC_USIC_CH_OPERATING_MODE_I2C) { + if (isMaster) { + Wire.begin(); + } else { + Wire.begin(slaveAddress); } - - XMC_I2C_CH_SlaveTransmit(XMC_I2C_config->channel, data); - - timeout = WIRE_COMMUNICATION_TIMEOUT; - while (XMC_USIC_CH_GetTransmitBufferStatus(XMC_I2C_config->channel) == - XMC_USIC_CH_TBUF_STATUS_BUSY) { - if (this->hasError == true || timeout == 0) { - this->hasError = false; - inRepStart = false; - flush(); - return 0; - } - timeout--; + } + XMC_I2C_CH_SlaveTransmit(XMC_I2C_config->channel, data); + uint32_t start = millis(); + while (XMC_USIC_CH_GetTransmitBufferStatus(XMC_I2C_config->channel) == + XMC_USIC_CH_TBUF_STATUS_BUSY) { + if (this->hasError == true || (millis() - start > timeout)) { + flush(); + return 0; } } return 1; } -// must be called in: -// slave tx event callback -// or after beginTransmission(address) size_t TwoWire::write(const uint8_t *data, size_t quantity) { if (transmitting) { - // in master transmitter mode + size_t written = 0; for (size_t i = 0; i < quantity; ++i) { - write(data[i]); - } - } else { - // in slave send mode - // reply to master - if ((XMC_I2C_config->channel->CCR & USIC_CH_CCR_MODE_Msk) != - XMC_USIC_CH_OPERATING_MODE_I2C) { - if (isMaster) { - Wire.begin(); - } else { - Wire.begin(slaveAddress); + if (!write(data[i])) { + break; } + written++; } - - for (uint8_t c = 0; c < quantity; c++) { - XMC_I2C_CH_SlaveTransmit(XMC_I2C_config->channel, data[c]); + return written; + } + // in slave send mode + // reply to master + if ((XMC_I2C_config->channel->CCR & USIC_CH_CCR_MODE_Msk) != XMC_USIC_CH_OPERATING_MODE_I2C) { + if (isMaster) { + Wire.begin(); + } else { + Wire.begin(slaveAddress); } - - timeout = WIRE_COMMUNICATION_TIMEOUT; - while (XMC_USIC_CH_GetTransmitBufferStatus(XMC_I2C_config->channel) == - XMC_USIC_CH_TBUF_STATUS_BUSY) { - if (this->hasError == true || timeout == 0) { - this->hasError = false; - inRepStart = false; - flush(); - return 0; - } - timeout--; + } + for (uint8_t c = 0; c < quantity; c++) { + XMC_I2C_CH_SlaveTransmit(XMC_I2C_config->channel, data[c]); + } + uint32_t start = millis(); + while (XMC_USIC_CH_GetTransmitBufferStatus(XMC_I2C_config->channel) == + XMC_USIC_CH_TBUF_STATUS_BUSY) { + if (this->hasError == true || (millis() - start > timeout)) { + flush(); + return 0; } } return quantity; } -// must be called in: -// slave rx event callback -// or after requestFrom(address, numBytes) -int TwoWire::available(void) { return rxBufferLength - rxBufferIndex; } +int TwoWire::available(void) { return rx_ringBuffer.available(); } -// must be called in: -// slave rx event callback -// or after requestFrom(address, numBytes) int TwoWire::read(void) { - int value = -1; - - // get each successive byte on each call - if (rxBufferIndex < rxBufferLength) { - value = rxBuffer[rxBufferIndex]; - ++rxBufferIndex; + if (rx_ringBuffer.available() == 0) { + return -1; } - - return value; + return rx_ringBuffer.read_char(); } -// must be called in: -// slave rx event callback -// or after requestFrom(address, numBytes) int TwoWire::peek(void) { - int value = -1; - - if (rxBufferIndex < rxBufferLength) { - value = rxBuffer[rxBufferIndex]; + if (rx_ringBuffer.available() == 0) { + return -1; } - - return value; + return rx_ringBuffer.peek(); } void TwoWire::flush(void) { // Reset buffer and clear all Status Flags - if (isMaster == true) { + if (isMaster) { XMC_USIC_CH_TXFIFO_Flush(XMC_I2C_config->channel); XMC_USIC_CH_RXFIFO_Flush(XMC_I2C_config->channel); XMC_USIC_CH_SetTransmitBufferStatus(XMC_I2C_config->channel, @@ -562,16 +403,25 @@ void TwoWire::flush(void) { (void)XMC_I2C_CH_GetReceivedData(XMC_I2C_config->channel); } XMC_I2C_CH_ClearStatusFlag(XMC_I2C_config->channel, 0xFFFFFFFF); + rx_ringBuffer.clear(); + tx_ringBuffer.clear(); + pre_rx_ringBuffer.clear(); + transmitting = 0; + inRepStart = false; + hasError = false; } -// behind the scenes function that is called after each received byte void TwoWire::ReceiveHandler(void) { - // no stop or read request - pre_rxBuffer[pre_rxBufferCount] = XMC_I2C_CH_GetReceivedData(XMC_I2C_config->channel); - pre_rxBufferCount++; + uint32_t data = XMC_I2C_CH_GetReceivedData(XMC_I2C_config->channel); + noInterrupts(); + if (pre_rx_ringBuffer.isFull()) { + hasError = true; + } else { + pre_rx_ringBuffer.store_char(data); + } + interrupts(); } -// behind the scenes function that is called after receiving stop or read request void TwoWire::ProtocolHandler(void) { uint32_t flag_status = XMC_I2C_CH_GetStatusFlag(XMC_I2C_config->channel); if (isMaster) { @@ -594,75 +444,48 @@ void TwoWire::ProtocolHandler(void) { XMC_I2C_CH_STATUS_FLAG_ERROR | XMC_I2C_CH_STATUS_FLAG_DATA_LOST_INDICATION)); hasError = true; - } else if (flag_status & (uint32_t)XMC_I2C_CH_STATUS_FLAG_SLAVE_READ_REQUESTED) { + } + if (flag_status & (uint32_t)XMC_I2C_CH_STATUS_FLAG_SLAVE_READ_REQUESTED) { XMC_I2C_CH_ClearStatusFlag(XMC_I2C_config->channel, XMC_I2C_CH_STATUS_FLAG_SLAVE_READ_REQUESTED); - uint8_t numBytes = pre_rxBufferCount; - - pre_rxBufferCount = 0; - - OnReceiveService(pre_rxBuffer, numBytes); + noInterrupts(); + while (pre_rx_ringBuffer.available()) { + rx_ringBuffer.store_char(pre_rx_ringBuffer.read_char()); + } + interrupts(); + OnReceiveService(rx_ringBuffer.available()); OnRequestService(); - } else if (flag_status & (uint32_t)XMC_I2C_CH_STATUS_FLAG_STOP_CONDITION_RECEIVED) { + } + if (flag_status & (uint32_t)XMC_I2C_CH_STATUS_FLAG_STOP_CONDITION_RECEIVED) { XMC_I2C_CH_ClearStatusFlag(XMC_I2C_config->channel, XMC_I2C_CH_STATUS_FLAG_STOP_CONDITION_RECEIVED); - uint8_t numBytes = pre_rxBufferCount; - - pre_rxBufferCount = 0; - OnReceiveService(pre_rxBuffer, numBytes); + noInterrupts(); + while (pre_rx_ringBuffer.available()) { + rx_ringBuffer.store_char(pre_rx_ringBuffer.read_char()); + } + interrupts(); + OnReceiveService(rx_ringBuffer.available()); } } } -// behind the scenes callback function that is called when a data block is received -void TwoWire::OnReceiveService(uint8_t *inBytes, uint8_t numBytes) { - // don't bother if user hasn't registered a callback - if (!user_onReceive) { - return; - } - // don't bother if rx buffer is in use by a master requestFrom() op - // i know this drops data, but it allows for slight stupidity - // meaning, they may not have read all the master requestFrom() data yet - if (rxBufferIndex < rxBufferLength) { - return; +void TwoWire::OnReceiveService(uint8_t numBytes) { + if (user_onReceive && numBytes > 0) { + user_onReceive(numBytes); } - - // copy twi rx buffer into local read buffer - // this enables new reads to happen in parallel - for (uint8_t i = 0; i < numBytes; ++i) { - rxBuffer[i] = inBytes[i]; - } - // set rx iterator vars - rxBufferIndex = 0; - rxBufferLength = numBytes; - // alert user program - user_onReceive(numBytes); - - /*Flush receive buffer*/ - (void)XMC_I2C_CH_GetReceivedData(XMC_I2C_config->channel); - (void)XMC_I2C_CH_GetReceivedData(XMC_I2C_config->channel); } -// behind the scenes function that is called when data is requested void TwoWire::OnRequestService(void) { - // don't bother if user hasn't registered a callback - if (!user_onRequest) { - return; + if (user_onRequest) { + tx_ringBuffer.clear(); + user_onRequest(); } - // reset tx buffer iterator vars - // !!! this will kill any pending pre-master sendTo() activity - txBufferIndex = 0; - txBufferLength = 0; - // alert user program - user_onRequest(); } -// sets function called on slave write void TwoWire::onReceive(void (*function)(int)) { user_onReceive = function; } -// sets function called on slave read void TwoWire::onRequest(void (*function)(void)) { user_onRequest = function; } /* @@ -676,19 +499,13 @@ void USIC0_4_IRQHandler() { Wire.ReceiveHandler(); } void USIC0_5_IRQHandler() { Wire.ProtocolHandler(); } - #if defined(XMC1100_XMC2GO) || defined(XMC1100_H_BRIDGE2GO) + #if defined(KIT_XMC_2GO_XMC1100_V1) || defined(XMC1100_H_BRIDGE2GO) void USIC0_2_IRQHandler() { Wire1.ReceiveHandler(); } void USIC0_3_IRQHandler() { Wire1.ProtocolHandler(); } #endif - #if defined(XMC4400_Platform2GO) -void USIC1_1_IRQHandler() { Wire.ReceiveHandler(); } - -void USIC1_2_IRQHandler() { Wire.ProtocolHandler(); } - #endif - -#elif defined(XMC4700_Relax_Kit) +#elif defined(KIT_XMC47_RELAX) void USIC1_1_IRQHandler() { Wire.ReceiveHandler(); } void USIC1_2_IRQHandler() { Wire.ProtocolHandler(); } @@ -699,8 +516,6 @@ void USIC1_4_IRQHandler() { Wire1.ProtocolHandler(); } #endif } // extern "C" -// Preinstantiate Objects ////////////////////////////////////////////////////// - TwoWire Wire = TwoWire(&XMC_I2C_default); #if (NUM_I2C > 1) TwoWire Wire1 = TwoWire(&XMC_I2C_1); diff --git a/libraries/Wire/src/Wire.h b/libraries/Wire/src/Wire.h index dce62e8b..13ed81e0 100644 --- a/libraries/Wire/src/Wire.h +++ b/libraries/Wire/src/Wire.h @@ -1,111 +1,58 @@ -/* - * TwoWire.h - TWI/I2C library for Arduino & Wiring - * Copyright (c) 2006 Nicholas Zambetti. All right reserved. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * Modified 2012 by Todd Krein (todd@krein.org) to implement repeated starts - * - * Copyright (c) 2018 Infineon Technologies AG - * This library has been modified for the XMC microcontroller series. - */ - #ifndef TwoWire_h #define TwoWire_h -//**************************************************************************** -// @Project Includes -//**************************************************************************** #include - -//**************************************************************************** -// @Defines -//**************************************************************************** -#define BUFFER_LENGTH 32 -// WIRE_HAS_END means Wire has end() -#define WIRE_HAS_END 1 +#include "api/RingBuffer.h" +#include "api/HardwareI2C.h" #define WIRE_COMMUNICATION_TIMEOUT 5000u +#define BUFFER_LENGTH 256 +#define WIRE_HAS_END 1 -//**************************************************************************** -// @Class Definitions -//**************************************************************************** -class TwoWire : public Stream { -private: - XMC_I2C_t *XMC_I2C_config; - - bool isMaster; - bool inRepStart; - uint8_t transmitting; - uint16_t timeout; - - uint8_t rxBuffer[BUFFER_LENGTH]; - uint8_t rxBufferIndex; - uint8_t rxBufferLength; - - uint8_t slaveAddress; - uint8_t txAddress; - uint8_t txBuffer[BUFFER_LENGTH]; - uint8_t txBufferIndex; - uint8_t txBufferLength; - - uint8_t pre_rxBuffer[BUFFER_LENGTH]; - uint8_t pre_rxBufferCount; - - void (*user_onRequest)(void); - void (*user_onReceive)(int); - void OnRequestService(void); - void OnReceiveService(uint8_t *, uint8_t); - +class TwoWire : public arduino::HardwareI2C { public: bool volatile hasError; TwoWire(XMC_I2C_t *conf); void begin(); void begin(uint8_t); - void begin(int); void end(); void setClock(uint32_t); void beginTransmission(uint8_t); - void beginTransmission(int); uint8_t endTransmission(void); - uint8_t endTransmission(uint8_t); - uint8_t requestFrom(uint8_t, uint8_t); - uint8_t requestFrom(uint8_t, uint8_t, uint8_t); - uint8_t requestFrom(uint8_t, uint8_t, uint32_t, uint8_t, uint8_t); - uint8_t requestFrom(int, int); - uint8_t requestFrom(int, int, int); + uint8_t endTransmission(bool); + size_t requestFrom(uint8_t, size_t); + size_t requestFrom(uint8_t, size_t, bool); virtual size_t write(uint8_t); virtual size_t write(const uint8_t *, size_t); - virtual int available(void); - virtual int read(void); - virtual int peek(void); - virtual void flush(void); + int available(void); + int read(void); + int peek(void); + void flush(void); void onReceive(void (*)(int)); void onRequest(void (*)(void)); void ReceiveHandler(void); void ProtocolHandler(void); - inline size_t write(unsigned long n) { return write((uint8_t)n); } + using Print::write; - inline size_t write(long n) { return write((uint8_t)n); } +private: + XMC_I2C_t *XMC_I2C_config; - inline size_t write(unsigned int n) { return write((uint8_t)n); } + bool isMaster; + bool inRepStart; + uint8_t transmitting; + uint16_t timeout; + arduino::RingBufferN rx_ringBuffer; + arduino::RingBufferN tx_ringBuffer; + arduino::RingBufferN pre_rx_ringBuffer; - inline size_t write(int n) { return write((uint8_t)n); } + uint8_t slaveAddress; + uint8_t txAddress; - using Print::write; + void (*user_onRequest)(void); + void (*user_onReceive)(int); + void OnRequestService(void); + void OnReceiveService(uint8_t numBytes); }; extern TwoWire Wire; diff --git a/package/config.yml b/package/config.yml new file mode 100644 index 00000000..af52c4ba --- /dev/null +++ b/package/config.yml @@ -0,0 +1,18 @@ +package-name: xmc-for-arduino +include: + - cores + - libraries + - tools + - variants + - boards.txt + - keywords.txt + - LICENSE.md + - package.json + - platform.txt + - programmers.txt + - README.md +index-name: package_xmc_index +server: + type: github + owner: Infineon + repo: XMC-for-Arduino \ No newline at end of file diff --git a/package/package_infineon_index.template.json b/package/package_xmc_index.template.json similarity index 77% rename from package/package_infineon_index.template.json rename to package/package_xmc_index.template.json index e39fc7f5..cae00042 100644 --- a/package/package_infineon_index.template.json +++ b/package/package_xmc_index.template.json @@ -1,16 +1,13 @@ { "packages": [ { - "name": "Infineon", + "name": "infineon", "maintainer": "Infineon Technologies AG", - "websiteURL": "https://github.com/Infineon/xmc-for-arduino", - "email": "", - "help": { - "online": "https://xmc-arduino.readthedocs.io/en/latest/index.html" - }, + "websiteURL": "https://xmc-arduino.readthedocs.io/en/latest/index.html", + "email": "maker@infineon.com", "platforms": [ { - "name": "Infineon's XMC Microcontroller", + "name": "Infineon XMC Boards", "architecture": "xmc", "version": "", "category": "Contributed", @@ -19,37 +16,31 @@ "checksum": "", "size": "", "help": { - "online": "https://xmc-arduino.readthedocs.io/en/latest/index.html" + "online": "" }, "boards": [ { - "name": "XMC1100 Boot Kit" + "name": "KIT_XMC11_BOOT_001" }, { - "name": "XMC1100 XMC2Go" + "name": "KIT_XMC_2GO_XMC1100_V1" }, { - "name": "XMC1300 Boot Kit" + "name": "KIT_XMC13_BOOT_001" }, { - "name": "XMC1400 Kit for Arduino" + "name": "KIT_XMC1400_ARDUINO" }, { - "name": "XMC1400 XMC2Go" + "name": "KIT_XMC14_2GO" }, { - "name": "XMC4200 Platform 2Go" - }, - { - "name": "XMC4400 Platform 2Go" - }, - { - "name": "XMC4700 Relax Kit" + "name": "KIT_XMC47_RELAX" } ], "toolsDependencies": [ { - "packager": "Infineon", + "packager": "infineon", "name": "arm-none-eabi-gcc", "version": "10.3-2021.10" } @@ -64,20 +55,20 @@ { "host": "i686-mingw32", "archiveFileName": "gcc-arm-none-eabi-10.3-2021.10-win32.zip", - "url": "https://developer.arm.com/-/media/Files/downloads/gnu-rm/10.3-2021.10/gcc-arm-none-eabi-10.3-2021.10-win32.zip", + "url": "https://armkeil.blob.core.windows.net/developer/Files/downloads/gnu-rm/10.3-2021.10/gcc-arm-none-eabi-10.3-2021.10-win32.zip", "checksum": "SHA-256:d287439b3090843f3f4e29c7c41f81d958a5323aecefcf705c203bfd8ae3f2e7", "size": "200578763" }, { "host": "x86_64-apple-darwin", - "url": "https://developer.arm.com/-/media/Files/downloads/gnu-rm/10.3-2021.10/gcc-arm-none-eabi-10.3-2021.10-mac.tar.bz2", + "url": "https://armkeil.blob.core.windows.net/developer/Files/downloads/gnu-rm/10.3-2021.10/gcc-arm-none-eabi-10.3-2021.10-mac.tar.bz2", "archiveFileName": "gcc-arm-none-eabi-10.3-2021.10-mac.tar.bz2", "checksum": "SHA-256:fb613dacb25149f140f73fe9ff6c380bb43328e6bf813473986e9127e2bc283b", "size": "158961466" }, { "host": "x86_64-pc-linux-gnu", - "url": "https://developer.arm.com/-/media/Files/downloads/gnu-rm/10.3-2021.10/gcc-arm-none-eabi-10.3-2021.10-x86_64-linux.tar.bz2", + "url": "https://armkeil.blob.core.windows.net/developer/Files/downloads/gnu-rm/10.3-2021.10/gcc-arm-none-eabi-10.3-2021.10-x86_64-linux.tar.bz2", "archiveFileName": "gcc-arm-none-eabi-10.3-2021.10-x86_64-linux.tar.bz2", "checksum": "SHA-256:97dbb4f019ad1650b732faffcc881689cedc14e2b7ee863d390e0a41ef16c9a3", "size": "157089706" diff --git a/platform.txt b/platform.txt index 5435906c..d844c9fa 100644 --- a/platform.txt +++ b/platform.txt @@ -5,12 +5,14 @@ # The information about this Arduino compatible environment # --------- -name=XMC Family -version=3.0.0 +name=Infineon XMC Boards +# The version field is automatically added during +# the core release packaging. Leave empty. +version= # Build related core definitions # --------- -build.core.path ={runtime.platform.path}/core +build.core.path ={runtime.platform.path}/cores/xmc build.variant.path ={runtime.platform.path}/variants/{build.variant} build.variant.config_path ={runtime.platform.path}/variants/{build.variant}/config/{build.board_variant} build.flash_ld_path ={build.variant.path}/{build.flash_ld} @@ -42,11 +44,16 @@ compiler.warning_flags=-w compiler.define=-DARDUINO= # Compiler include paths for include files -compiler.xmclib_include.path={runtime.platform.path}/cores/xmc_lib +compiler.xmclib_include.path={runtime.platform.path}/cores/xmc/xmc_lib compiler.cmsis_include.path={compiler.xmclib_include.path}/CMSIS/Include compiler.nn_include.path={compiler.xmclib_include.path}/CMSIS/NN/Include compiler.dsp_include.path={compiler.xmclib_include.path}/CMSIS/DSP/Include +compiler.arduino_core.path={runtime.platform.path}/cores/xmc/api +compiler.arduino_core_dep.path={compiler.arduino_core.path}/deprecated +compiler.arduino_core_dep_avr.path={compiler.arduino_core.path}/deprecated-avr-comp/avr +compiler.arduino_core_api.path= "-I{compiler.arduino_core_dep_avr.path}" "-I{compiler.arduino_core_dep.path}" + compiler.arm.cmsis.path= "-I{compiler.xmclib_include.path}/XMCLib/inc" "-I{compiler.dsp_include.path}" "-I{compiler.nn_include.path}" "-I{compiler.cmsis_include.path}" "-I{compiler.xmclib_include.path}/LIBS" "-I{build.variant.path}" "-I{build.variant.config_path}" compiler.avr_support.path= "-I{build.core.path}/avr" compiler.usb.path = "-I{runtime.platform.path}/cores/usblib" "-I{runtime.platform.path}/cores/usblib/Common" "-I{runtime.platform.path}/cores/usblib/Class" "-I{runtime.platform.path}/cores/usblib/Class/Common" "-I{runtime.platform.path}/cores/usblib/Class/Device" "-I{runtime.platform.path}/cores/usblib/Core" "-I{runtime.platform.path}/cores/usblib/Core/XMC4000" @@ -60,7 +67,7 @@ build.usb_manufacturer="Unknown" compiler.c.flags=-mcpu={build.mcu} -mthumb -c -g -Os {compiler.warning_flags} -std=gnu11 -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -MMD #compiler.c.extra_flags=-ftime-report compiler.c.extra_flags= -compiler.libraries.ldflags= +compiler.libraries.ldflags= -lstdc++ compiler.c.elf.flags=-Os -Wl,--gc-sections -save-temps compiler.c.elf.extra_flags= @@ -84,14 +91,17 @@ compiler.elf2hex.extra_flags= # Compile patterns # ---------------- +# Includes +includes=-I{runtime.platform.path}/cores/xmc + ## Compile C files -recipe.c.o.pattern="{compiler.path}{compiler.c.cmd}" {compiler.c.flags} -DXMC{build.board.version}_{build.board.type} -D{build.board_variant} -DF_CPU={build.f_cpu} -DARDUINO={build.board.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.c.extra_flags} {build.extra_flags} {build.menu_flags} {compiler.arm.cmsis.path} {compiler.avr_support.path} {compiler.usb.path} {includes} "{source_file}" -o "{object_file}" +recipe.c.o.pattern="{compiler.path}{compiler.c.cmd}" {compiler.c.flags} -DXMC{build.board.version}_{build.board.type} -D{build.board_variant} -D{build.board_variant_old} -DF_CPU={build.f_cpu} -DARDUINO={build.board.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.c.extra_flags} {build.extra_flags} {build.menu_flags} {compiler.arm.cmsis.path} {compiler.avr_support.path} {compiler.usb.path} {compiler.arduino_core_api.path} {includes} "{source_file}" -o "{object_file}" ## Compile C++ files -recipe.cpp.o.pattern="{compiler.path}{compiler.cpp.cmd}" {compiler.cpp.flags} -DXMC{build.board.version}_{build.board.type} -D{build.board_variant} -DF_CPU={build.f_cpu} -DARDUINO={build.board.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.cpp.extra_flags} {build.extra_flags} {build.menu_flags} {compiler.arm.cmsis.path} {compiler.avr_support.path} {compiler.usb.path} {includes} "{source_file}" -o "{object_file}" +recipe.cpp.o.pattern="{compiler.path}{compiler.cpp.cmd}" {compiler.cpp.flags} -DXMC{build.board.version}_{build.board.type} -D{build.board_variant} -D{build.board_variant_old} -DF_CPU={build.f_cpu} -DARDUINO={build.board.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.cpp.extra_flags} {build.extra_flags} {build.menu_flags} {compiler.arm.cmsis.path} {compiler.avr_support.path} {compiler.usb.path} {compiler.arduino_core_api.path} {includes} "{source_file}" -o "{object_file}" ## Compile S files -recipe.S.o.pattern="{compiler.path}{compiler.S.cmd}" {compiler.S.flags} -DXMC{build.board.version}_{build.board.type} -D{build.board_variant} -DF_CPU={build.f_cpu} -DARDUINO={build.board.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.S.extra_flags} {build.extra_flags} {build.menu_flags} {compiler.arm.cmsis.path} {compiler.avr_support.path} {compiler.usb.path} {includes} "{source_file}" -o "{object_file}" +recipe.S.o.pattern="{compiler.path}{compiler.S.cmd}" {compiler.S.flags} -DXMC{build.board.version}_{build.board.type} -D{build.board_variant} -D{build.board_variant_old} -DF_CPU={build.f_cpu} -DARDUINO={build.board.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.S.extra_flags} {build.extra_flags} {build.menu_flags} {compiler.arm.cmsis.path} {compiler.avr_support.path} {compiler.usb.path} {compiler.arduino_core_api.path} {includes} "{source_file}" -o "{object_file}" # Linker patterns # ---------------- @@ -103,6 +113,7 @@ recipe.c.combine.pattern="{compiler.path}{compiler.c.elf.cmd}" -mthumb --specs=n # ---------------- # Archive_file_path is needed for backwards compatibility with IDE 1.6.5 or older, IDE 1.6.6 or newer overrides this value + archive_file_path={build.path}/{archive_file} recipe.ar.pattern="{compiler.path}{compiler.ar.cmd}" {compiler.ar.flags} {compiler.ar.extra_flags} "{archive_file_path}" "{object_file}" @@ -151,8 +162,9 @@ tools.xmcflasher.erase.params=-d XMC{build.board.version}-{build.board.v} -p {up tools.xmcflasher.erase.pattern=python3 {cmd.path} erase {erase.params} tools.xmcflasher.erase.pattern.windows=python {cmd.path} erase {erase.params} tools.xmcflasher.upload.protocol= +tools.xmcflasher.upload.custom_flag= tools.xmcflasher.upload.params.verbose=--verbose tools.xmcflasher.upload.params.quiet= -tools.xmcflasher.upload.params=-d XMC{build.board.version}-{build.board.v} -p {upload.port.address} -f {build.path}/{build.project_name}.hex {upload.verbose} +tools.xmcflasher.upload.params=-d XMC{build.board.version}-{build.board.v} -p {upload.port.address} -f {build.path}/{build.project_name}.hex {upload.verbose} {upload.custom_flag} tools.xmcflasher.upload.pattern=python3 {cmd.path} upload {upload.params} tools.xmcflasher.upload.pattern.windows=python {cmd.path} upload {upload.params} diff --git a/tests/Makefile.test b/tests/Makefile.test index 1804ba1c..cc272277 100644 --- a/tests/Makefile.test +++ b/tests/Makefile.test @@ -1,29 +1,28 @@ ### Build commands -### ! Please note that you need to change the port and path of Unity as appropriate ! ### Unit tests -##CAN +## CAN # 1 board, no wire -make FQBN=Infineon:xmc:XMC1400_XMC2GO PORT=COM42 UNITY_PATH=\Unity test_can_single monitor +make FQBN=infineon:xmc:kit_xmc14_2go PORT=COM42 test_can_single monitor # 2 boards -make FQBN=Infineon:xmc:XMC1400_XMC2GO PORT=COM42 UNITY_PATH=\Unity test_can_connected2_node2 monitor -make FQBN=Infineon:xmc:XMC1400_XMC2GO PORT=COM41 UNITY_PATH=\Unity test_can_connected2_node1 monitor +make FQBN=infineon:xmc:kit_xmc14_2go PORT=COM42 test_can_connected2_node2 monitor +make FQBN=infineon:xmc:kit_xmc14_2go PORT=COM41 test_can_connected2_node1 monitor ## IIC # 1 board "talking to itself", wire needed -make FQBN=Infineon:xmc:XMC4700_Relax_Kit PORT=COM28 UNITY_PATH=\Unity test_wire_connected1_pingpong monitor +make FQBN=infineon:xmc:kit_xmc47_relax PORT=COM28 test_wire_connected1_pingpong monitor # 2 boards -make FQBN=Infineon:xmc:XMC4700_Relax_Kit PORT=COM85 test_wire_connected2_masterpingpong monitor -make FQBN=Infineon:xmc:XMC4700_Relax_Kit PORT=COM28 test_wire_connected2_slavepingpong monitor +make FQBN=infineon:xmc:kit_xmc47_relax PORT=COM85 test_wire_connected2_masterpingpong monitor +make FQBN=infineon:xmc:kit_xmc47_relax PORT=COM28 test_wire_connected2_slavepingpong monitor ## UART # 2 boards -make FQBN=Infineon:xmc:XMC4700_Relax_Kit PORT=COM71 test_uart_connected2_tx monitor -make FQBN=Infineon:xmc:XMC4700_Relax_Kit PORT=COM28 test_uart_connected2_rx monitor \ No newline at end of file +make FQBN=infineon:xmc:kit_xmc47_relax PORT=COM71 test_uart_connected2_tx monitor +make FQBN=infineon:xmc:kit_xmc47_relax PORT=COM28 test_uart_connected2_rx monitor \ No newline at end of file diff --git a/tests/arduino-core-tests b/tests/arduino-core-tests deleted file mode 160000 index 0052b910..00000000 --- a/tests/arduino-core-tests +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 0052b910df063e45f351575220f53b0cec295eec diff --git a/tests/hil-unity-checklist.yaml b/tests/hil-unity-checklist.yaml index e56a53cd..0e1af5d3 100644 --- a/tests/hil-unity-checklist.yaml +++ b/tests/hil-unity-checklist.yaml @@ -1,4 +1,4 @@ -Infineon.xmc.XMC4700_Relax_Kit: +infineon.xmc.kit_xmc47_relax: CAN: 1: - "test_can_connected2_node2" @@ -19,7 +19,7 @@ Infineon.xmc.XMC4700_Relax_Kit: - "test_uart_connected2_rx" -Infineon.xmc.XMC1400_XMC2GO: +infineon.xmc.kit_xmc14_2go: CAN: 1: - "test_can_connected2_node2" @@ -33,7 +33,7 @@ Infineon.xmc.XMC1400_XMC2GO: - "test_wire_connected2_masterpingpong" -Infineon.xmc.XMC1100_XMC2GO: +infineon.xmc.kit_xmc_2go_xmc1100_v1: Wire: 1: - "test_wire_connected2_slavepingpong" diff --git a/tests/manual/PCLKTest/PCLKTest.ino b/tests/manual/PCLKTest/PCLKTest.ino index aa8aff9f..e3fe904e 100644 --- a/tests/manual/PCLKTest/PCLKTest.ino +++ b/tests/manual/PCLKTest/PCLKTest.ino @@ -7,15 +7,16 @@ If both LED1 and LED2 are permanently ON then an invalid pin for PWM has been attempted to be attached to a invalid pin Wiring - Default PWM pin are 3 - - Some Board variant PWM Pins - XMC1100 Boot Kit 3, 4, 6, 9 - XMC1100 XMC2Go 8, 3, 2, 1 - XMC1300 Boot Kit 31, 26, 32, 33 - XMC4700 Relax 3, 10, 11, 95, 72, 96, 63, 36, 78, 90, 91, - 5, 6, 9, 53, 39, 64, 38, 68, 79, 83, 82, 81 - */ + Default PWM pin are 3 + + Some Board variant PWM Pins + KIT_XMC11_BOOT_001 3, 4, 6, 9 + KIT_XMC_2GO_XMC1100_V1 8, 3, 2, 1 + KIT_XMC13_BOOT_001 31, 26, 32, 33 + KIT_XMC47_RELAX 3, 10, 11, 95, 72, 96, 63, 36, 78, 90, 91, + 5, 6, 9, 53, 39, 64, 38, 68, 79, 83, 82, 81 + +*/ #include #include @@ -26,7 +27,7 @@ Wiring // Adjust the following defines to match your setup // Pins for Servos and pot //#define PWM_A_PIN 3 -// XMC1300 Boot Kit pins +// KIT_XMC13_BOOT_001 pins #define PWM_A_PIN 31 #define RESOLUTION 16 diff --git a/tests/manual/PWMtest/PWMtest.ino b/tests/manual/PWMtest/PWMtest.ino index 65a5d464..7c098959 100644 --- a/tests/manual/PWMtest/PWMtest.ino +++ b/tests/manual/PWMtest/PWMtest.ino @@ -11,19 +11,20 @@ Default PWM pins are 3 and 4 Some Board variant PWM Pins - XMC1100 Boot Kit 3, 4, 6, 9 - XMC1100 XMC2Go 8, 3, 2, 1 - XMC1300 Boot Kit 31, 26, 32, 33 - XMC4700 Relax 3, 10, 11, 95, 72, 96, 63, 36, 78, 90, 91, - 5, 6, 9, 53, 39, 64, 38, 68, 79, 83, 82, 81 - */ + KIT_XMC11_BOOT_001 3, 4, 6, 9 + KIT_XMC_2GO_XMC1100_V1 8, 3, 2, 1 + KIT_XMC13_BOOT_001 31, 26, 32, 33 + KIT_XMC47_RELAX 3, 10, 11, 95, 72, 96, 63, 36, 78, 90, 91, + 5, 6, 9, 53, 39, 64, 38, 68, 79, 83, 82, 81 + +*/ #include // Adjust the following defines to match your setup // Pins for Servos and pot //#define PWM_A_PIN 3 //#define PWM_B_PIN 4 -// XMC1300 Boot Kit pins +// KIT_XMC13_BOOT_001 pins #define PWM_A_PIN 31 #define PWM_B_PIN 26 diff --git a/tests/manual/Servotest/Servotest.ino b/tests/manual/Servotest/Servotest.ino index e892af3a..66484b79 100644 --- a/tests/manual/Servotest/Servotest.ino +++ b/tests/manual/Servotest/Servotest.ino @@ -16,16 +16,17 @@ Wiring Pot is connected to analogue input A1 - (XMC1300 Boot Kit has on-board pot on this pin) + (KIT_XMC13_BOOT_001 has on-board pot on this pin) Default PWM pins are 3 and 4 Some Board variant PWM Pins - XMC1100 Boot Kit 3, 4, 6, 9 - XMC1100 XMC2Go 8, 3, 2, 1 - XMC1300 Boot Kit 31, 26, 32, 33 - XMC4700 Relax 3, 10, 11, 95, 72, 96, 63, 36, 78, 90, 91, - 5, 6, 9, 53, 39, 64, 38, 68, 79, 83, 82, 81 - */ + KIT_XMC11_BOOT_001 3, 4, 6, 9 + KIT_XMC_2GO_XMC1100_V1 8, 3, 2, 1 + KIT_XMC13_BOOT_001 31, 26, 32, 33 + KIT_XMC47_RELAX 3, 10, 11, 95, 72, 96, 63, 36, 78, 90, 91, + 5, 6, 9, 53, 39, 64, 38, 68, 79, 83, 82, 81 + +*/ #include #include diff --git a/tests/manual/analogwritetest/analogwritetest.ino b/tests/manual/analogwritetest/analogwritetest.ino index 3934c38b..148a7ff8 100644 --- a/tests/manual/analogwritetest/analogwritetest.ino +++ b/tests/manual/analogwritetest/analogwritetest.ino @@ -18,7 +18,7 @@ void setup() { -#if defined ( XMC1100_XMC2GO ) +#if defined ( KIT_XMC_2GO_XMC1100_V1 ) analogWrite( 8, 32 ); // all PWM4 analogWrite( 1, 64 ); analogWrite( 2, 96 ); @@ -27,21 +27,21 @@ analogWrite( 3, 128 ); #if defined ( XMC1100_H_BRIDGE2GO ) analogWrite( 8, 32 ); // PWM4 #endif -#if defined ( XMC1100_Boot_Kit ) || defined ( XMC1400_Boot_Kit ) || defined ( XMC1300_Sense2GoL ) -// XMC1100 Boot Kit or XMC1400 Boot Kit or XMC1300 Sense2GoL +#if defined ( KIT_XMC11_BOOT_001 ) || defined ( KIT_XMC1400_ARDUINO ) || defined ( XMC1300_Sense2GoL ) +// KIT_XMC11_BOOT_001 or XMC1400 Boot Kit or XMC1300 Sense2GoL analogWrite( 3, 32 ); // all PWM4 analogWrite( 4, 64 ); analogWrite( 6, 96 ); analogWrite( 9, 128 ); #endif -#if defined ( XMC1300_Boot_Kit ) -// XMC1300 Boot Kit +#if defined ( KIT_XMC13_BOOT_001 ) +// KIT_XMC13_BOOT_001 analogWrite( 31, 32 ); // PWM4 analogWrite( 26, 64 ); analogWrite( 32, 96 ); // PWM8 analogWrite( 33, 128 ); #endif -#if defined ( XMC4700_Relax_Kit ) || defined( XMC4700_Radar_Baseboard ) +#if defined ( KIT_XMC47_RELAX ) || defined( XMC4700_Radar_Baseboard ) analogWrite( 3, 32 ); // PWM4 analogWrite( 5, 64 ); // PWM8 rest relax kit only analogWrite( 6, 96 ); diff --git a/tests/manual/tonetest/tonetest.ino b/tests/manual/tonetest/tonetest.ino index e6f8e0e8..a8b824ba 100644 --- a/tests/manual/tonetest/tonetest.ino +++ b/tests/manual/tonetest/tonetest.ino @@ -71,7 +71,7 @@ Serial.println( "PC Services Tone Test V2" ); tone( LED1, 1 ); tone( LED2, 2, 20000 ); -#if defined( XMC1100_Boot_Kit ) || defined( XMC1300_Boot_Kit ) +#if defined( KIT_XMC11_BOOT_001 ) || defined( KIT_XMC13_BOOT_001 ) tone( LED5, 4, 1000 ); tone( LED6, 8, 6000 ); #elif defined( XMC1300_Sense2GoL ) diff --git a/tests/test_config.cpp b/tests/test_config.cpp new file mode 100644 index 00000000..238f2773 --- /dev/null +++ b/tests/test_config.cpp @@ -0,0 +1,14 @@ +/** + * @file test_config.cpp + * @brief Implementation file for board-specific test configuration variables. + * + */ + +#include "test_config.h" +#include + +// TODO: Need SPI definition of PSOC6 for spi slave test. It should be managed more effectively. +#if defined(ARDUINO_ARCH_PSOC6) +// Define the SPI master and slave instances +SPIClassPSOC SPI1 = SPIClassPSOC(PIN_SPI_MOSI, PIN_SPI_MISO, PIN_SPI_SCK, TEST_PIN_SPI_SSEL, true); +#endif // ARDUINO_ARCH_PSOC6 diff --git a/tests/test_config.h b/tests/test_config.h new file mode 100644 index 00000000..d9f41427 --- /dev/null +++ b/tests/test_config.h @@ -0,0 +1,86 @@ +/** + * @file test_config.h + * @brief Configuration file for board-specific test pin definitions. + * + * This header file contains the definitions of the pins used for testing + * purposes on the specific board. These pins are configured as output and + * input pins for various test scenarios. + * + */ +#ifndef TEST_CONFIG_H +#define TEST_CONFIG_H + +#include +#include + +#if defined(ARDUINO_ARCH_XMC) + + #define SPI_TRANSFER_DELAY_US 2000 + // Test Pin Definitions + #define TEST_PIN_SPI_SSEL 10 // IO_0 + #define TEST_PIN_ONEWIRE 7 + + #if defined(KIT_XMC47_RELAX) + #define TEST_PIN_DIGITAL_IO_OUTPUT 3 // IO_4 + #define TEST_PIN_DIGITAL_IO_INPUT 2 // IO_3 + #define TEST_PIN_PULSE 5 // IO_2 + #define TEST_PIN_SYNC_IO 4 // IO_1 + #define PWM_FREQUENCY_HZ 490 // PWM Frequency in Hz + #define TEST_PIN_ANALOG_IO_VREF A2 // Pin connected to Vdd + #define TEST_PIN_ANALOG_IO_DIVIDER A1 // Pin connected to voltage divider + #define TEST_PIN_ANALOG_IO_GND A0 // Pin connected to Ground + #define TEST_ADC_MAX_VALUE 1023 + #define TEST_ADC_RESOLUTION 10 // ADC resolution + + #define TEST_PIN_ANALOG_IO_DAC 53 + #define TEST_PIN_ANALOG_IO_DAC_INPUT A3 +static const float test_pwm_frequencies[] = {1, 50, 5000, 50000}; + #elif defined(KIT_XMC1400_ARDUINO) + #define TEST_PIN_DIGITAL_IO_OUTPUT 4 + #define TEST_PIN_DIGITAL_IO_INPUT 25 + #define TEST_PIN_PULSE 6 + #define TEST_PIN_SYNC_SPI 5 + #define TEST_PIN_SYNC_IO 4 // IO_1 + #define PWM_FREQUENCY_HZ 490 // PWM Frequency in Hz + #define TEST_PIN_ANALOG_IO_VREF A2 // Pin connected to Vdd + #define TEST_PIN_ANALOG_IO_DIVIDER A1 // Pin connected to voltage divider + #define TEST_PIN_ANALOG_IO_GND A0 // Pin connected to Ground + #define TEST_ADC_MAX_VALUE 1023 + #define TEST_ADC_RESOLUTION 10 // ADC resolution +static const float test_pwm_frequencies[] = {1, 50, 5000, 20000}; + #elif defined(KIT_XMC11_BOOT_001) + #define TEST_PIN_DIGITAL_IO_OUTPUT 3 // IO_4 + #define TEST_PIN_DIGITAL_IO_INPUT 2 // IO_3 + #define TEST_PIN_PULSE 6 // IO_2 + #define TEST_PIN_SYNC_SPI 5 + #define TEST_PIN_SYNC_IO 4 // IO_1 + #define PWM_FREQUENCY_HZ 490 // PWM Frequency in Hz + #define TEST_PIN_ANALOG_IO_VREF A2 // Pin connected to Vdd + #define TEST_PIN_ANALOG_IO_DIVIDER A1 // Pin connected to voltage divider + #define TEST_PIN_ANALOG_IO_GND A0 // Pin connected to Ground + #define TEST_ADC_MAX_VALUE 1023 + #define TEST_ADC_RESOLUTION 10 // ADC resolution +static const float test_pwm_frequencies[] = {1, 50, 5000, 10000}; + #elif defined(KIT_XMC14_2GO) + #define PWM_FREQUENCY_HZ 490 // PWM Frequency in Hz + #define TEST_PIN_ANALOG_IO_VREF A0 // Pin connected to Vdd + #define TEST_PIN_ANALOG_IO_DIVIDER A1 // Pin connected to voltage divider + #define TEST_ADC_MAX_VALUE 1023 + #define TEST_ADC_RESOLUTION 10 // ADC resolution + #endif +extern XMCSPIClass SPI; +#endif // ARDUINO_ARCH_XMC + +// TODO: Need definition of PSOC6 for spi slave test. It should be managed more effectively. +#if defined(ARDUINO_ARCH_PSOC6) +static const float test_pwm_frequencies[] = {1, 50, 5000, 50000}; + + // Test Pin Definitions + #define TEST_PIN_SYNC_IO 4 // IO_1 + #define TEST_PIN_SPI_SSEL 3 // IO_0 + +// Forward declarations for SPI instances +extern SPIClassPSOC SPI1; +#endif // ARDUINO_ARCH_PSOC6 + +#endif // TEST_CONFIG_H diff --git a/tools/ci.sh b/tools/ci.sh index 1bc76c90..e4e53891 100644 --- a/tools/ci.sh +++ b/tools/ci.sh @@ -18,6 +18,6 @@ function ci_commit_formatting_run { # If the common ancestor commit hasn't been found, fetch more. git merge-base upstream/master HEAD || git fetch upstream master # For a PR, upstream/master..HEAD ends with a merge commit into master, exclude that one. - python tools/verifygitlog.py -v upstream/master..HEAD --no-merges + python tools/verifygitlog.py --ignore-rebase -v upstream/master..HEAD --no-merges } diff --git a/tools/dev-setup.sh b/tools/dev-setup.sh new file mode 100644 index 00000000..82989356 --- /dev/null +++ b/tools/dev-setup.sh @@ -0,0 +1,39 @@ +#!/bin/bash + +# Change dir to the directory where this script is located +cd $(dirname $0) +echo ${PWD} + +function git_submodule_setup { + git submodule update --init --recursive +} + +function core_api_setup { + + cores_xmc_dir="${PWD}/../cores/xmc" + core_api_submodule_dir="${PWD}/../extras/arduino-core-api" + + # Create symbolic link (overwrite) to the api/ + # folder of ArduinoCore-API submodule. + # Note: Symlinks might not work without full paths + # https://stackoverflow.com/questions/8601988/symlinks-not-working-when-link-is-made-in-another-directory + if [ ! -d "$cores_xmc_dir" ]; then + mkdir -p "$cores_xmc_dir" + echo "Directory created: $cores_xmc_dir" + fi + ln -s ${core_api_submodule_dir}/api ${cores_xmc_dir} +} + + +# Check if a function name is passed as an argument +if [ $# -gt 0 ]; then + if declare -f "$1" > /dev/null; then + "$1" + else + echo "Function $1 not found" + exit 1 + fi +else + git_submodule_setup + core_api_setup +fi diff --git a/tools/gen_launch.sh b/tools/gen_launch.sh new file mode 100755 index 00000000..b522f6e4 --- /dev/null +++ b/tools/gen_launch.sh @@ -0,0 +1,149 @@ +#!/bin/bash +# gen_launch.sh: Compile and generate launch.json for XMC or PSoC6 boards +# Usage: ./gen_launch.sh [boards.txt] [gdb_path] +# : Fully Qualified Board Name (e.g. infineon:psoc6:CY8CKIT_062S2_AI or arduino-git:xmc:kit_xmc47_relax) +# : Directory where the .elf file will be placed +# : Path to the sketch (.ino) file +# [boards.txt] : (Optional) Path to boards.txt (default: inferred based on device) +# [gdb_path] : (Optional) Path to GDB executable (default: inferred based on device) + +set -e + +FQBN_FULL="$1" +BUILD_PATH="$2" +SKETCH_PATH="$3" + +if [[ -z "$FQBN_FULL" || -z "$BUILD_PATH" || -z "$SKETCH_PATH" ]]; then + echo "Usage: $0 [boards.txt] [gdb_path]" + exit 1 +fi + +# Get the script directory and package root +SCRIPT_DIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)" +PACKAGE_DIR="$(dirname "$SCRIPT_DIR")" + +# Detect device type based on FQBN +if [[ "$FQBN_FULL" == infineon:psoc6:* ]]; then + DEVICE_TYPE="psoc6" + BOARDS_TXT="${4:-$PACKAGE_DIR/boards.txt}" + GDB_PATH="${5:-$HOME/.arduino15/packages/infineon/tools/mtb-gcc-arm-none-eabi/11.3.1.67/bin/arm-none-eabi-gdb}" +elif [[ "$FQBN_FULL" == arduino-git:xmc:* ]]; then + DEVICE_TYPE="xmc" + XMC_DIR="$(dirname "$SCRIPT_DIR")" + BOARDS_TXT="${4:-$XMC_DIR/boards.txt}" + GDB_PATH="${5:-$HOME/.arduino15/packages/infineon/tools/arm-none-eabi-gcc/10.3-2021.10/bin/arm-none-eabi-gdb}" +else + echo "Unsupported device type in FQBN: $FQBN_FULL" + exit 1 +fi + +# Extract board name from FQBN +BOARD_NAME=$(echo "$FQBN_FULL" | awk -F: '{print $NF}') + +# Compile the sketch +arduino-cli compile -b "${FQBN_FULL}" --build-path "${BUILD_PATH}" "${SKETCH_PATH}" || exit 1 + +# Parse boards.txt for variant and other parameters +VARIANT=$(grep "^${BOARD_NAME}\.build\.variant=" "$BOARDS_TXT" | cut -d= -f2) +if [[ -z "$VARIANT" ]]; then + echo "Could not find variant for $BOARD_NAME in $BOARDS_TXT" + exit 2 +fi + +if [[ "$DEVICE_TYPE" == "xmc" ]]; then + BOARD_V=$(grep "^${BOARD_NAME}\.build\.board\.v=" "$BOARDS_TXT" | cut -d= -f2) + if [[ -z "$BOARD_V" ]]; then + echo "Could not find board.v for $BOARD_NAME in $BOARDS_TXT" + exit 2 + fi + DEVICE="${VARIANT}-${BOARD_V}" +else + DEVICE="${VARIANT}" +fi + +# Find the .elf executable +EXECUTABLE=$(find "${BUILD_PATH}" -maxdepth 1 -type f -name "*.elf" | head -n 1) +if [[ -z "$EXECUTABLE" ]]; then + echo "No .elf executable found in $BUILD_PATH." + exit 3 +fi + +# Create the .vscode directory and generate launch.json +LAUNCH_DIR="$PACKAGE_DIR/.vscode" +if [ ! -d "$LAUNCH_DIR" ]; then + mkdir -p "$LAUNCH_DIR" +fi +if [ -f "$LAUNCH_DIR/launch.json" ]; then + rm "$LAUNCH_DIR/launch.json" +fi + +if [[ "$DEVICE_TYPE" == "psoc6" ]]; then + # Generate launch.json for PSoC6 + cat > "$LAUNCH_DIR/launch.json" < "$LAUNCH_DIR/launch.json" <= 76 and "://" not in line: err.error("Message lines should be 75 or less characters: " + line) - if not raw_body[-1].startswith("Signed-off-by: ") or "@" not in raw_body[-1]: - err.error('Message must be signed-off. Use "git commit -s".') - def run(args): verbose("run", *args) diff --git a/tools/vscode_profile/task_xmc.json b/tools/vscode_profile/task_xmc.json new file mode 100644 index 00000000..4e08fee6 --- /dev/null +++ b/tools/vscode_profile/task_xmc.json @@ -0,0 +1,114 @@ +{ + "version": "2.0.0", + "tasks": [ + { + "label": "Arduino Build", + "type": "shell", + "command": "arduino-cli", + "args": [ + "compile", + "--fqbn", "${input:boardFqbn}", + "${input:examplePath}" + ], + "group": { + "kind": "build", + "isDefault": false + }, + "problemMatcher": [] + }, + { + "label": "Arduino Upload", + "type": "shell", + "command": "arduino-cli", + "args": [ + "upload", + "-p", "${input:port}", + "--fqbn", "${input:boardFqbn}", + "${input:examplePath}" + ], + "dependsOn": "Arduino Build", + "group": { + "kind": "build", + "isDefault": true + }, + "problemMatcher": [] + }, + { + "label": "Generate lauch.json for debug (XMC)", + "type": "shell", + "command": "${workspaceFolder}/tools/gen_launch.sh", + "args": [ + "${input:boardFqbn}", + "${input:debugBuildPath}", + + "${input:examplePath}", + "${input:boardsTxtPath}", + "${input:gdbPath}" + ], + "group": { + "kind": "build", + "isDefault": false + }, + "problemMatcher": [], + "presentation": { + "echo": true, + "reveal": "always", + "focus": false, + "panel": "shared" + } + }, + { + "label": "Arduino Monitor", + "type": "shell", + "command": "arduino-cli", + "args": [ + "monitor", + "-p", "${input:port}", + "-c", "baudrate=115200" + ], + "group": { + "kind": "build", + "isDefault": false + }, + "problemMatcher": [] + } + ], + "inputs": [ + { + "id": "boardFqbn", + "type": "promptString", + "description": "Enter the FQBN (Fully Qualified Board Name) for the Arduino board", + "default": "arduino-git:xmc:kit_xmc47_relax" + }, + { + "id": "debugBuildPath", + "type": "promptString", + "description": "Enter the build path where the .elf file would be placed", + "default": "${workspaceFolder}/extras/arduino-core-tests/build/output" + }, + { + "id": "examplePath", + "type": "promptString", + "description": "Enter the path to the Arduino example sketch", + "default": "${workspaceFolder}/examples/bug/bug.ino" + }, + { + "id": "port", + "type": "promptString", + "description": "Enter the port for the Arduino board", + "default": "/dev/ttyACM0" + }, + { + "id": "boardsTxtPath", + "type": "promptString", + "description": "(Optional) Enter the path to boards.txt, or leave blank for default", + "default": "" + }, + { + "id": "gdbPath", + "type": "promptString", + "description": "(Optional) Enter the path to arm-none-eabi-gdb, or leave blank for default", + "default": "" + } + ] + } \ No newline at end of file diff --git a/tools/xmc-flasher.py b/tools/xmc-flasher.py index 9f7d276b..56d47050 100755 --- a/tools/xmc-flasher.py +++ b/tools/xmc-flasher.py @@ -1,4 +1,4 @@ -import argparse, subprocess, os, sys, re, warnings, tempfile +import argparse, subprocess, os, sys, re, tempfile, logging from serial.tools.list_ports import comports from xmc_data import xmc_master_data @@ -43,7 +43,7 @@ def discover_jlink_devices(): jlink_pattern = r'[Jj][-\s]?[Ll][Ii][Nn][Kk]' for p in ports: if re.search(jlink_pattern, p.description): - port_sn_list.append((p.device, p.serial_number)) + port_sn_list.append((p.device, p.serial_number, p.description)) return port_sn_list @@ -54,25 +54,31 @@ def get_device_serial_number(port): return device[1] return None -def create_jlink_loadbin_command_file(binfile): - cmd_load_bin = 'loadbin ' + binfile + ' 0x0\n' +def create_jlink_loadbin_command_file(binfile, enable_update): + lines = [] + if not enable_update: + lines.append('exec DisableAutoUpdateFW\n') + lines += ['r\n', 'h\n', f'loadbin {binfile} 0x0\n', 'r\n', 'g\n', 'exit\n'] with open(cmd_jlink,'w') as f: - f.writelines(['r\n', 'h\n', cmd_load_bin, 'r\n', 'g\n', 'exit\n']) - + f.writelines(lines) return cmd_jlink -def create_jlink_mem_read_command_file(addr, bytes): - #cmd_log_enable - cmd_mem_read = 'mem ' + addr +', '+ bytes + '\n' # todo: store register maps, bytes in file +def create_jlink_mem_read_command_file(addr, bytes, enable_update): + lines = [] + if not enable_update: + lines.append('exec DisableAutoUpdateFW\n') + lines += [f'mem {addr}, {bytes}\n', 'r\n', 'g\n', 'exit\n'] with open(cmd_jlink,'w') as f: - f.writelines([cmd_mem_read, 'r\n', 'g\n', 'exit\n']) - + f.writelines(lines) return cmd_jlink -def create_jlink_erase_command_file(): +def create_jlink_erase_command_file(enable_update): + lines = [] + if not enable_update: + lines.append('exec DisableAutoUpdateFW\n') + lines += ['r\n', 'h\n', 'erase\n', 'exit\n'] with open(cmd_jlink,'w') as f: - f.writelines(['r\n', 'h\n', 'erase\n', 'exit\n']) - + f.writelines(lines) return cmd_jlink def remove_jlink_command_file(cmd_file): @@ -94,7 +100,7 @@ def remove_backspaces(input_str): return ''.join(result) def jlink_commander(device, serial_num, cmd_file, console_output=False): - jlink_cmd = [jlinkexe, '-autoconnect', '1','-exitonerror', '1', '-nogui', '1', '-device', device, '-selectemubysn', serial_num, '-if', 'swd', '-speed', '4000', '-commandfile', cmd_file] + jlink_cmd = [jlinkexe, '-autoconnect', '1','-exitonerror', '1', '-nogui', '1', '-device', device, '-SelectEmuBySN', serial_num, '-if', 'swd', '-speed', '4000', '-commandfile', cmd_file] #if console_output is True: #jlink_cmd.append('-log ') #todo: pipe this in a better way @@ -125,31 +131,28 @@ def check_serial_number(serial_num): if serial_num == None: raise Exception("Device not found! Please check the serial port") -def get_mem_contents(addr, bytes, device, port): +def get_mem_contents(addr, bytes, device, port, enable_update): try: serial_num = get_device_serial_number(port) check_serial_number(serial_num) except ValueError as e: - print(e) - jlink_cmd_file = create_jlink_mem_read_command_file(addr, bytes) # todo: comes from proper metafile + logging.error(e) + jlink_cmd_file = create_jlink_mem_read_command_file(addr, bytes, enable_update) # todo: comes from proper metafile jlink_commander(device, serial_num, jlink_cmd_file, True) remove_jlink_command_file(jlink_cmd_file) - with open(console_out,'r') as f: lines = f.readlines() lines[0].split('\n') - remove_console_output_file(console_out) - reg_contents = "" for line in lines : + logging.debug(f"JLink Log: {line.strip()}") if addr in line and '=' in line: reg_contents = re.findall('[0-9,A-F]+', line) break - if not reg_contents: + logging.error(f"Wrong COM Port selected! {port}") raise Exception(f"Wrong COM Port selected! {port}\n") - reg_contents.remove(addr) # remove the addr from the list, just keep reg contents reg_contents.reverse() # jlink returns LSB first, so reverse it to get MSB on the left side reg_contents = ''.join(reg_contents) @@ -165,125 +168,124 @@ def find_device_by_value(value): return device return None -def check_device(device, port): - +def check_device(device, port, enable_update): master_data = read_master_data() # get value from reg - device_value = get_mem_contents(master_data[device]['IDCHIP']['addr'], master_data[device]['IDCHIP']['size'], device, port) + device_value = get_mem_contents(master_data[device]['IDCHIP']['addr'], master_data[device]['IDCHIP']['size'], device, port, enable_update) device_value_masked = (int('0x'+device_value,16)) & (int('0x'+master_data[device]['IDCHIP']['mask'],16)) # take only those bits which are needed device_value_masked = f'{device_value_masked:x}' device_value_masked = device_value_masked.zfill(int(master_data[device]['IDCHIP']['size'])*2) - - print(f"Selected Device is: {device}.") - + logging.info(f"Selected Device is: {device}.") real_device = find_device_by_value(device_value_masked) #compare with stored master data if not real_device == device: if real_device != None: - print(f"Connected Device is: {real_device}.") - raise Exception(f"Device connected on port {port} does not match the selected device to flash") + logging.info(f"Connected Device is: {real_device}.") + logging.error(f"Device connected on port {port} does not match the selected device {device}.") + raise Exception("Device connection mismatch.") -def check_mem(device, port): - +def check_mem(device, port, enable_update): if "XMC1" in device: master_data = read_master_data() # get value from reg - device_value = get_mem_contents(master_data[device]['FLSIZE']['addr'], master_data[device]['FLSIZE']['size'], device, port) + device_value = get_mem_contents(master_data[device]['FLSIZE']['addr'], master_data[device]['FLSIZE']['size'], device, port, enable_update) device_value = int('0x'+device_value,16) & int('0x0003f000',16) # bit 17 to bit 12 are needed device_value = device_value >> int(master_data[device]['FLSIZE']['bitposition_LSB']) flash_size = (device_value-1)*4 #flash size given by (ADDR-1)*4 flash_size = str(flash_size).zfill(4) - - print(f"Flash size is: {int(flash_size)}kB.") - + logging.info(f"Flash size is: {int(flash_size)}kB.") # special case for XMC2GO-32kB variant, bypass check if "XMC1100" in device and int(flash_size) == 32: - warnings.warn("XMC2GO 32kB varaint detected!") + logging.warning("XMC2GO 32kB variant detected!") return - #compare with selected device if not flash_size == device.split('-')[1]: - raise Exception("Memory size of device connected does not match that of the selected device to flash") - + logging.error(f"Memory size of device connected {flash_size} does not match that of the selected device to flash: {device.split('-')[1]}") + raise Exception("Memory size mismatch.") else: #XMC4 series master_data = read_master_data() # get value from reg - device_value = get_mem_contents(master_data[device]['FLASH0_ID']['addr'], master_data[device]['FLASH0_ID']['size'], device, port) + device_value = get_mem_contents(master_data[device]['FLASH0_ID']['addr'], master_data[device]['FLASH0_ID']['size'], device, port, enable_update) device_value_masked = (int('0x'+device_value,16)) & (int('0x'+master_data[device]['FLASH0_ID']['mask'],16)) # take only those bits which are needed device_value_masked = f'{device_value_masked:x}' device_value_masked = device_value_masked.zfill(int(master_data[device]['FLASH0_ID']['size'])*2) - #compare with stored master data if not device_value_masked.upper() == master_data[device]['FLASH0_ID']['value']: - raise Exception("Memory size of device connected does not match that of the selected device to flash") + logging.error(f"Memory size of device connected {flash_size} does not match that of the selected device to flash: {device.split('-')[1]}") + raise Exception("Memory size mismatch.") -def get_default_port(port): +def check_port(port): serial_num = get_device_serial_number(port) if serial_num == None or port == None: port_sn_list = discover_jlink_devices() for port_sn in port_sn_list: if port_sn[1] != None: real_port = port_sn[0] - print(f"Device found on port: {real_port}, not on the selected port: {port}.") - print(f"Automatically selecting port {real_port}...") - return real_port + logging.error(f"Device found:{port_sn_list}. You select {port}. Please select the correct port.") + raise Exception("Wrong COM Port selected.") else: - return port + return - -def upload(device, port, binfile, enable_jlink_log): +def upload(device, port, binfile, enable_jlink_log, enable_update): serial_num = get_device_serial_number(port) - jlink_cmd_file = create_jlink_loadbin_command_file(binfile) - jlink_commander(device, serial_num, jlink_cmd_file, console_output=not enable_jlink_log) # console_output = true will store the log to file instead of printing + jlink_cmd_file = create_jlink_loadbin_command_file(binfile, enable_update) + jlink_commander(device, serial_num, jlink_cmd_file, console_output=not enable_jlink_log) remove_jlink_command_file(jlink_cmd_file) -def erase(device, port): +def erase(device, port, enable_update): serial_num = get_device_serial_number(port) - jlink_cmd_file = create_jlink_erase_command_file() + jlink_cmd_file = create_jlink_erase_command_file(enable_update) jlink_commander(device, serial_num, jlink_cmd_file) remove_jlink_command_file(jlink_cmd_file) def debug(device, port, elfile): pass #TBD +def setup_logger(verbose=False): + if verbose: + level = logging.DEBUG + else: + level = logging.INFO + logging.basicConfig( + level=level, + format="%(asctime)s [%(levelname)s] %(message)s", + datefmt="%H:%M:%S" + ) + def parser(): def main_parser_func(args): parser.print_help() def parser_upload_func(args): - check_device(args.device, args.port) - check_mem(args.device, args.port) - upload(args.device, args.port, args.binfile, args.verbose) - # remove console output file if verbose is not enabled + + check_port(args.port) + check_device(args.device, args.port, args.fw_jlink_update) + check_mem(args.device, args.port, args.fw_jlink_update) + upload(args.device, args.port, args.binfile, args.verbose, args.fw_jlink_update) if not args.verbose: - # check if upload was successful by parsing the console output with open(console_out, 'r') as f: found_loadbin = False for line in f: if "J-Link>loadbin" in line: found_loadbin = True elif found_loadbin and "O.K." in line: - print("Upload successful.") + logging.info("Upload successful.") break else: - print("Upload failed.") + logging.error("Upload failed.") remove_console_output_file(console_out) - - # Log if the port value has changed - if args.port != original_port: - print(f"Please select port {args.port} for using the Serial Monitor or Plotter.") def parser_erase_func(args): - erase(args.device, args.port) + erase(args.device, args.port, args.fw_jlink_update) class ver_action(argparse.Action): def __init__(self, option_strings, dest, **kwargs): return super().__init__(option_strings, dest, nargs=0, default=argparse.SUPPRESS, **kwargs) def __call__(self, parser, namespace, values, option_string, **kwargs): - print('xmc-flasher version: ' + version) + logging.info('xmc-flasher version: ' + version) parser.exit() # General parser @@ -299,6 +301,8 @@ def __call__(self, parser, namespace, values, option_string, **kwargs): required_upload.add_argument('-p','--port', type=str, nargs='?', const='', help='serial port') required_upload.add_argument('-f','--binfile', type=str, help='binary file to upload', required=True) required_upload.add_argument('--verbose', action='store_true', help='Enable verbose logging') + parser_upload.add_argument('--no-fw-update', dest='fw_jlink_update', action='store_false', help='Disable JLink firmware update (default: enabled)') + parser_upload.set_defaults(fw_jlink_update=True) parser_upload.set_defaults(func=parser_upload_func) # Erase parser @@ -306,6 +310,8 @@ def __call__(self, parser, namespace, values, option_string, **kwargs): required_erase = parser_erase.add_argument_group('required arguments') required_erase.add_argument('-d','--device', type=str, help='jlink device name', required=True) required_erase.add_argument('-p','--port', type=str, help='serial port', required=True) + parser_erase.add_argument('--no-fw-update', dest='fw_jlink_update', action='store_false', help='Disable JLink firmware update (default: enabled)') + parser_erase.set_defaults(fw_jlink_update=True) parser_erase.set_defaults(func=parser_erase_func) # debug_parser. @@ -313,18 +319,14 @@ def __call__(self, parser, namespace, values, option_string, **kwargs): # Parse arguments args = parser.parse_args() - # Set traceback limit based on the --verbose argument + + # Logging option + setup_logger(verbose=args.verbose) if args.verbose: sys.tracebacklimit = None # Enable full traceback else: sys.tracebacklimit = 0 # Disable traceback - # Store the original port value - original_port = args.port - - # Select default port if not provided/ or device not found on the selected port - args.port = get_default_port(args.port) - # Parser call args.func(args) diff --git a/variants/XMC1100/config/XMC1100_Boot_Kit/pins_arduino.h b/variants/XMC1100/config/KIT_XMC11_BOOT_001/pins_arduino.h similarity index 93% rename from variants/XMC1100/config/XMC1100_Boot_Kit/pins_arduino.h rename to variants/XMC1100/config/KIT_XMC11_BOOT_001/pins_arduino.h index 0b450106..0d113b26 100644 --- a/variants/XMC1100/config/XMC1100_Boot_Kit/pins_arduino.h +++ b/variants/XMC1100/config/KIT_XMC11_BOOT_001/pins_arduino.h @@ -18,6 +18,9 @@ Public License along with this library; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + Copyright (c) 2018 Infineon Technologies AG + This file has been modified for the XMC microcontroller series. */ #ifndef PINS_ARDUINO_H_ #define PINS_ARDUINO_H_ @@ -33,7 +36,7 @@ // XMC_BOARD for stringifying into serial or other text outputs/logs // Note the actual name XMC and number MUST have a character between // to avoid issues with other defined macros e.g. XMC1100 -#define XMC_BOARD XMC 1100 Boot Kit +#define XMC_BOARD KIT_XMC11_BOOT_001 /* On board LED is ON when digital output is 0, LOW, False, OFF */ #define XMC_LED_ON 0 @@ -135,7 +138,7 @@ extern uint8_t SCK; #define LED5 2 #define LED6 30 -#define digitalPinToInterrupt(p) ((p) == 2 ? 0 : ((p) == 3 ? 1 : NOT_AN_INTERRUPT)) +#define digitalPinToInterrupt(p) ((p) == 2 ? 0 : ((p) == 3 ? 1 : -1)) #ifdef ARDUINO_MAIN // Mapping of digital pins and comments @@ -174,6 +177,7 @@ const XMC_PORT_PIN_t mapping_port_pin[] = { }; const uint8_t GND = (sizeof(mapping_port_pin) / sizeof(XMC_PORT_PIN_t)); const uint8_t NUM_DIGITAL = (sizeof(mapping_port_pin) / sizeof(XMC_PORT_PIN_t)); +bool gpio_current_value[NUM_DIGITAL] = {false}; ; const XMC_PIN_INTERRUPT_t mapping_interrupt[] = { @@ -192,35 +196,28 @@ const uint8_t mapping_pin_PWM4[][2] = {{3, 0}, {4, 1}, {6, 2}, {9, 3}, /* Configurations of PWM channels for CCU4 type */ XMC_PWM4_t mapping_pwm4[] = { {CCU40, CCU40_CC40, 0, mapping_port_pin[3], P0_0_AF_CCU40_OUT0, XMC_CCU4_SLICE_PRESCALER_64, - PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 3 P0.0 + PWM4_TIMER_PERIOD, 0, false}, // PWM disabled 3 P0.0 {CCU40, CCU40_CC41, 1, mapping_port_pin[4], P0_1_AF_CCU40_OUT1, XMC_CCU4_SLICE_PRESCALER_64, - PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 4 P0.1 + PWM4_TIMER_PERIOD, 0, false}, // PWM disabled 4 P0.1 {CCU40, CCU40_CC43, 3, mapping_port_pin[6], P0_3_AF_CCU40_OUT3, XMC_CCU4_SLICE_PRESCALER_64, - PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 6 P0.3 + PWM4_TIMER_PERIOD, 0, false}, // PWM disabled 6 P0.3 {CCU40, CCU40_CC42, 2, mapping_port_pin[9], P0_8_AF_CCU40_OUT2, XMC_CCU4_SLICE_PRESCALER_64, - PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 9 P0.8 + PWM4_TIMER_PERIOD, 0, false}, // PWM disabled 9 P0.8 {CCU40, CCU40_CC43, 3, mapping_port_pin[10], P0_9_AF_CCU40_OUT3, XMC_CCU4_SLICE_PRESCALER_64, - PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 10 P0.9 + PWM4_TIMER_PERIOD, 0, false}, // PWM disabled 10 P0.9 {CCU40, CCU40_CC41, 1, mapping_port_pin[11], P1_1_AF_CCU40_OUT1, XMC_CCU4_SLICE_PRESCALER_64, - PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 11 P1.1 + PWM4_TIMER_PERIOD, 0, false}, // PWM disabled 11 P1.1 {CCU40, CCU40_CC42, 2, mapping_port_pin[20], P2_10_AF_CCU40_OUT2, XMC_CCU4_SLICE_PRESCALER_64, - PWM4_TIMER_PERIOD, DISABLED} // PWM disabled 20 P2.10 + PWM4_TIMER_PERIOD, 0, false} // PWM disabled 20 P2.10 }; const uint8_t NUM_PWM = (sizeof(mapping_pwm4) / sizeof(XMC_PWM4_t)); const uint8_t NUM_PWM4 = (sizeof(mapping_pwm4) / sizeof(XMC_PWM4_t)); /* Analog Pin mappings and configurations */ -XMC_ADC_t mapping_adc[] = {{VADC, 0, DISABLED}, {VADC, 1, DISABLED}, {VADC, 2, DISABLED}, - {VADC, 3, DISABLED}, {VADC, 4, DISABLED}, {VADC, 7, DISABLED}, - {VADC, 5, DISABLED}, {VADC, 6, DISABLED}}; +XMC_ADC_t mapping_adc[] = {{VADC, 0, false}, {VADC, 1, false}, {VADC, 2, false}, {VADC, 3, false}, + {VADC, 4, false}, {VADC, 7, false}, {VADC, 5, false}, {VADC, 6, false}}; const uint8_t NUM_ANALOG_INPUTS = (sizeof(mapping_adc) / sizeof(XMC_ADC_t)); -/* - * UART objects - */ -RingBuffer rx_buffer_0; -RingBuffer tx_buffer_0; - /* First UART channel pins are swapped between debug and normal use */ XMC_UART_t XMC_UART_0 = {.channel = XMC_UART0_CH1, .rx = {.port = (XMC_GPIO_PORT_t *)PORT1_BASE, @@ -254,7 +251,7 @@ XMC_UART_t XMC_UART_0 = {.channel = XMC_UART0_CH1, .irq_num = USIC0_0_IRQn, .irq_service_request = 0}; -HardwareSerial Serial(&XMC_UART_0, &rx_buffer_0, &tx_buffer_0); +Uart Serial(&XMC_UART_0); // SPI instance XMC_SPI_t XMC_SPI_0 = { @@ -341,8 +338,4 @@ void USIC0_0_IRQHandler() { Serial.IrqHandler(); } #endif #endif /* ARDUINO_MAIN */ -#ifdef __cplusplus -extern HardwareSerial Serial; -#endif /* cplusplus */ - -#endif // PINS_ARDUINO_H_ +#endif /* PINS_ARDUINO_H_ */ diff --git a/variants/XMC1100/config/XMC1100_XMC2GO/pins_arduino.h b/variants/XMC1100/config/KIT_XMC_2GO_XMC1100_V1/pins_arduino.h similarity index 95% rename from variants/XMC1100/config/XMC1100_XMC2GO/pins_arduino.h rename to variants/XMC1100/config/KIT_XMC_2GO_XMC1100_V1/pins_arduino.h index 66e4df8e..4051f1ba 100644 --- a/variants/XMC1100/config/XMC1100_XMC2GO/pins_arduino.h +++ b/variants/XMC1100/config/KIT_XMC_2GO_XMC1100_V1/pins_arduino.h @@ -36,7 +36,7 @@ // XMC_BOARD for stringifying into serial or other text outputs/logs // Note the actual name XMC and number MUST have a character between // to avoid issues with other defined macros e.g. XMC1100 -#define XMC_BOARD XMC 1100 XMC2GO +#define XMC_BOARD KIT_XMC_2GO_XMC1100_V1 /* On board LED is ON when digital output is 1, HIGH, TRUE, ON */ #define XMC_LED_ON 1 @@ -105,7 +105,7 @@ extern uint8_t SCK; #define LED2 15 #define LED_BUILTIN LED1 -#define digitalPinToInterrupt(p) (((p) == 9) ? 0 : NOT_AN_INTERRUPT) +#define digitalPinToInterrupt(p) (((p) == 9) ? 0 : -1) #ifdef ARDUINO_MAIN // Mapping of digital pins and comments @@ -131,6 +131,7 @@ const XMC_PORT_PIN_t mapping_port_pin[] = { }; const uint8_t GND = (sizeof(mapping_port_pin) / sizeof(XMC_PORT_PIN_t)); const uint8_t NUM_DIGITAL = (sizeof(mapping_port_pin) / sizeof(XMC_PORT_PIN_t)); +bool gpio_current_value[NUM_DIGITAL] = {false}; ; const XMC_PIN_INTERRUPT_t mapping_interrupt[] = { @@ -147,28 +148,21 @@ const uint8_t mapping_pin_PWM4[][2] = {{8, 0}, {1, 1}, {2, 2}, {3, 3}, {255, 255 /* Configurations of PWM channels for CCU4 type */ XMC_PWM4_t mapping_pwm4[] = { {CCU40, CCU40_CC40, 0, mapping_port_pin[8], P0_5_AF_CCU40_OUT0, XMC_CCU4_SLICE_PRESCALER_64, - PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 8 P0.5 + PWM4_TIMER_PERIOD, 0, false}, // PWM disabled 8 P0.5 {CCU40, CCU40_CC41, 1, mapping_port_pin[1], P0_7_AF_CCU40_OUT1, XMC_CCU4_SLICE_PRESCALER_64, - PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 1 P0.7 + PWM4_TIMER_PERIOD, 0, false}, // PWM disabled 1 P0.7 {CCU40, CCU40_CC42, 2, mapping_port_pin[2], P0_8_AF_CCU40_OUT2, XMC_CCU4_SLICE_PRESCALER_64, - PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 2 P0.8 + PWM4_TIMER_PERIOD, 0, false}, // PWM disabled 2 P0.8 {CCU40, CCU40_CC43, 3, mapping_port_pin[3], P0_9_AF_CCU40_OUT3, XMC_CCU4_SLICE_PRESCALER_64, - PWM4_TIMER_PERIOD, DISABLED} // PWM disabled 3 P0.9 + PWM4_TIMER_PERIOD, 0, false} // PWM disabled 3 P0.9 }; const uint8_t NUM_PWM = (sizeof(mapping_pwm4) / sizeof(XMC_PWM4_t)); const uint8_t NUM_PWM4 = (sizeof(mapping_pwm4) / sizeof(XMC_PWM4_t)); /* Analog Pin mappings and configurations */ -XMC_ADC_t mapping_adc[] = { - {VADC, 1, DISABLED}, {VADC, 2, DISABLED}, {VADC, 3, DISABLED}, {VADC, 4, DISABLED}}; +XMC_ADC_t mapping_adc[] = {{VADC, 1, false}, {VADC, 2, false}, {VADC, 3, false}, {VADC, 4, false}}; const uint8_t NUM_ANALOG_INPUTS = (sizeof(mapping_adc) / sizeof(XMC_ADC_t)); -/* - * UART objects - */ -RingBuffer rx_buffer_0; -RingBuffer tx_buffer_0; - /* First UART channel pins are swapped between debug and normal use */ XMC_UART_t XMC_UART_0 = {.channel = XMC_UART0_CH0, .rx = {.port = (XMC_GPIO_PORT_t *)PORT2_BASE, @@ -206,7 +200,7 @@ XMC_UART_t XMC_UART_0 = {.channel = XMC_UART0_CH0, .irq_num = USIC0_0_IRQn, .irq_service_request = 0}; -HardwareSerial Serial(&XMC_UART_0, &rx_buffer_0, &tx_buffer_0); +Uart Serial(&XMC_UART_0); // SPI instance XMC_SPI_t XMC_SPI_0 = { @@ -313,9 +307,4 @@ void USIC0_0_IRQHandler() { Serial.IrqHandler(); } } #endif #endif /* ARDUINO_MAIN */ - -#ifdef __cplusplus -extern HardwareSerial Serial; -#endif /* cplusplus */ - #endif // PINS_ARDUINO_H_ diff --git a/variants/XMC1300/config/XMC1300_Boot_Kit/pins_arduino.h b/variants/XMC1300/config/KIT_XMC13_BOOT_001/pins_arduino.h old mode 100755 new mode 100644 similarity index 90% rename from variants/XMC1300/config/XMC1300_Boot_Kit/pins_arduino.h rename to variants/XMC1300/config/KIT_XMC13_BOOT_001/pins_arduino.h index b30a91dc..07b93ee6 --- a/variants/XMC1300/config/XMC1300_Boot_Kit/pins_arduino.h +++ b/variants/XMC1300/config/KIT_XMC13_BOOT_001/pins_arduino.h @@ -5,7 +5,7 @@ Copyright (c) 2007 David A. Mellis This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public< + modify it under the terms of the GNU Lesser General Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) any later version. @@ -36,7 +36,7 @@ // XMC_BOARD for stringifying into serial or other text outputs/logs // Note the actual name XMC and number MUST have a character between // to avoid issues with other defined macros e.g. XMC1300 -#define XMC_BOARD XMC 1300 Boot Kit +#define XMC_BOARD KIT_XMC13_BOOT_001 /* On board LED is ON when digital output is 0, LOW, False, OFF */ #define XMC_LED_ON 0 @@ -121,7 +121,7 @@ extern uint8_t SCK; #define LED6 28 #define LED_BUILTIN LED1 -#define digitalPinToInterrupt(p) ((p) == 14 ? 0 : ((p) == 15 ? 1 : NOT_AN_INTERRUPT)) +#define digitalPinToInterrupt(p) ((p) == 14 ? 0 : ((p) == 15 ? 1 : -1)) #ifdef ARDUINO_MAIN // Mapping of digital pins and comments @@ -163,6 +163,7 @@ const XMC_PORT_PIN_t mapping_port_pin[] = { }; const uint8_t GND = (sizeof(mapping_port_pin) / sizeof(XMC_PORT_PIN_t)); const uint8_t NUM_DIGITAL = (sizeof(mapping_port_pin) / sizeof(XMC_PORT_PIN_t)); +bool gpio_current_value[NUM_DIGITAL] = {false}; ; const XMC_PIN_INTERRUPT_t mapping_interrupt[] = { @@ -180,9 +181,9 @@ const uint8_t mapping_pin_PWM4[][2] = {{31, 0}, {26, 1}, {255, 255}}; /* Configurations of PWM channels for CCU4 type */ XMC_PWM4_t mapping_pwm4[] = { {CCU40, CCU40_CC41, 1, mapping_port_pin[31], P0_4_AF_CCU40_OUT1, XMC_CCU4_SLICE_PRESCALER_64, - PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 31 P0.4 + PWM4_TIMER_PERIOD, 0, false}, // PWM disabled 31 P0.4 {CCU40, CCU40_CC42, 2, mapping_port_pin[26], P0_2_AF_CCU40_OUT2, XMC_CCU4_SLICE_PRESCALER_64, - PWM4_TIMER_PERIOD, DISABLED} // PWM disabled 26 P0.2 + PWM4_TIMER_PERIOD, 0, false} // PWM disabled 26 P0.2 }; const uint8_t NUM_PWM4 = (sizeof(mapping_pwm4) / sizeof(XMC_PWM4_t)); @@ -192,38 +193,32 @@ const uint8_t mapping_pin_PWM8[][2] = {{32, 0}, {33, 1}, {255, 255}}; /* Configurations of PWM channels for CCU8 type */ XMC_PWM8_t mapping_pwm8[] = { {CCU80, CCU80_CC81, 1, XMC_CCU8_SLICE_COMPARE_CHANNEL_2, mapping_port_pin[32], - P0_5_AF_CCU80_OUT12, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, - DISABLED}, // PWM disabled 32 P0.5 + P0_5_AF_CCU80_OUT12, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, 0, + false}, // PWM disabled 32 P0.5 {CCU80, CCU80_CC80, 0, XMC_CCU8_SLICE_COMPARE_CHANNEL_2, mapping_port_pin[33], - P0_3_AF_CCU80_OUT03, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, - DISABLED} // PWM disabled 33 P0.3 + P0_3_AF_CCU80_OUT03, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, 0, + false} // PWM disabled 33 P0.3 }; const uint8_t NUM_PWM8 = (sizeof(mapping_pwm8) / sizeof(XMC_PWM8_t)); const uint8_t NUM_PWM = (sizeof(mapping_pwm4) / sizeof(XMC_PWM4_t)) + (sizeof(mapping_pwm8) / sizeof(XMC_PWM8_t)); /* Analog Pin mappings and configurations */ -XMC_ADC_t mapping_adc[] = {{VADC, 6, VADC_G1, 1, 4, DISABLED}, - {VADC, 7, VADC_G1, 1, 11, DISABLED}, - {VADC, 0, VADC_G0, 0, 9, DISABLED}, - {VADC, 1, VADC_G1, 1, 12, DISABLED}, - {VADC, 1, VADC_G0, 0, 10, DISABLED}, - {VADC, 2, VADC_G0, 0, 7, DISABLED}, +XMC_ADC_t mapping_adc[] = {{VADC, 6, VADC_G1, 1, 4, false}, + {VADC, 7, VADC_G1, 1, 11, false}, + {VADC, 0, VADC_G0, 0, 9, false}, + {VADC, 1, VADC_G1, 1, 12, false}, + {VADC, 1, VADC_G0, 0, 10, false}, + {VADC, 2, VADC_G0, 0, 7, false}, // Additional channels added here - {VADC, 3, VADC_G0, 0, 5, DISABLED}, - {VADC, 4, VADC_G0, 0, 1, DISABLED}, - {VADC, 5, VADC_G1, 1, 2, DISABLED}, - {VADC, 7, VADC_G0, 0, 3, DISABLED}, - {VADC, 6, VADC_G0, 0, 6, DISABLED}, - {VADC, 5, VADC_G0, 0, 8, DISABLED}}; + {VADC, 3, VADC_G0, 0, 5, false}, + {VADC, 4, VADC_G0, 0, 1, false}, + {VADC, 5, VADC_G1, 1, 2, false}, + {VADC, 7, VADC_G0, 0, 3, false}, + {VADC, 6, VADC_G0, 0, 6, false}, + {VADC, 5, VADC_G0, 0, 8, false}}; const uint8_t NUM_ANALOG_INPUTS = (sizeof(mapping_adc) / sizeof(XMC_ADC_t)); -/* - * UART objects - */ -RingBuffer rx_buffer_0; -RingBuffer tx_buffer_0; - /* First UART channel pins are swapped between debug and normal use */ XMC_UART_t XMC_UART_0 = {.channel = XMC_UART0_CH1, .rx = {.port = (XMC_GPIO_PORT_t *)PORT1_BASE, @@ -259,9 +254,9 @@ XMC_UART_t XMC_UART_0 = {.channel = XMC_UART0_CH1, .irq_num = USIC0_0_IRQn, .irq_service_request = 0}; -HardwareSerial Serial(&XMC_UART_0, &rx_buffer_0, &tx_buffer_0); +Uart Serial(&XMC_UART_0); -// SPI instance +// // SPI instance XMC_SPI_t XMC_SPI_0 = { .channel = XMC_SPI0_CH0, .channel_config = {.baudrate = 15984375U, @@ -327,8 +322,4 @@ void USIC0_0_IRQHandler() { Serial.IrqHandler(); } #endif #endif /* ARDUINO_MAIN */ -#ifdef __cplusplus -extern HardwareSerial Serial; -#endif /* cplusplus */ - -#endif // PINS_ARDUINO_H_ +#endif /* PINS_ARDUINO_H_ */ diff --git a/variants/XMC1400/config/XMC1400_Arduino_Kit/pins_arduino.h b/variants/XMC1400/config/KIT_XMC1400_ARDUINO/pins_arduino.h similarity index 88% rename from variants/XMC1400/config/XMC1400_Arduino_Kit/pins_arduino.h rename to variants/XMC1400/config/KIT_XMC1400_ARDUINO/pins_arduino.h index fd9d81ae..63837ae9 100644 --- a/variants/XMC1400/config/XMC1400_Arduino_Kit/pins_arduino.h +++ b/variants/XMC1400/config/KIT_XMC1400_ARDUINO/pins_arduino.h @@ -18,6 +18,9 @@ Public License along with this library; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + Copyright (c) 2018 Infineon Technologies AG + This file has been modified for the XMC microcontroller series. */ #ifndef PINS_ARDUINO_H_ #define PINS_ARDUINO_H_ @@ -33,8 +36,7 @@ // XMC_BOARD for stringifying into serial or other text outputs/logs // Note the actual name XMC and number MUST have a character between // to avoid issues with other defined macros e.g. XMC1400 -#define XMC_BOARD XMC 1400 Kit for Arduino - +#define XMC_BOARD KIT_XMC1400_ARDUINO /* On board LED is ON when digital output is 0, LOW, FALSE, OFF */ #define XMC_LED_ON 0 @@ -78,6 +80,10 @@ extern const uint8_t NUM_ANALOG_INPUTS; #define PIN_SPI_MOSI 11 #define PIN_SPI_MISO 12 #define PIN_SPI_SCK 13 +extern uint8_t SS; +extern uint8_t MOSI; +extern uint8_t MISO; +extern uint8_t SCK; #define A0 0 #define A1 1 @@ -103,10 +109,10 @@ extern const uint8_t NUM_ANALOG_INPUTS; #define LED3 26 #define LED_BUILTIN LED1 -#define EXT_INTR_0 3 -#define EXT_INTR_1 25 +#define EXT_INTR_0 25 +#define EXT_INTR_1 7 -#define digitalPinToInterrupt(p) ((p) == 3 ? 0 : ((p) == 25 ? 1 : NOT_AN_INTERRUPT)) +#define digitalPinToInterrupt(p) ((p) == 25 ? 0 : ((p) == 7 ? 1 : -1)) /* Mapping interrupt handlers. Notice that XMC1400 can have interrupt handlers working in 3 modes, the defines below assumes the mode A. For details refer to assembly file and reference manual. @@ -120,6 +126,9 @@ extern const uint8_t NUM_ANALOG_INPUTS; #define CCU40_1_IRQHandler IRQ22_Handler // interrupt 0 #define CCU40_1_IRQn IRQ22_IRQn +#define CCU40_3_IRQHandler IRQ24_Handler +#define CCU40_3_IRQn IRQ24_IRQn + #define USIC0_4_IRQHandler IRQ13_Handler // I2C #define USIC0_4_IRQn IRQ13_IRQn @@ -167,11 +176,12 @@ const XMC_PORT_PIN_t mapping_port_pin[] = { const uint8_t GND = (sizeof(mapping_port_pin) / sizeof(XMC_PORT_PIN_t)); const uint8_t NUM_DIGITAL = (sizeof(mapping_port_pin) / sizeof(XMC_PORT_PIN_t)); +bool gpio_current_value[NUM_DIGITAL] = {false}; ; const XMC_PIN_INTERRUPT_t mapping_interrupt[] = { - /* 0 */ {CCU40, CCU40_CC41, 1, 1, CCU40_IN1_U0C1_DX2INS}, - /* 1 */ {CCU40, CCU40_CC40, 0, 0, CCU40_IN0_U0C0_DX2INS}}; + /* 0 */ {CCU40, CCU40_CC40, 0, 0, CCU40_IN0_U0C0_DX2INS}, + /* 1 */ {CCU40, CCU40_CC40, 0, 1, CCU40_IN1_U0C1_DX2INS}}; const uint8_t NUM_INTERRUPT = (sizeof(mapping_interrupt) / sizeof(XMC_PIN_INTERRUPT_t)); /* Mapping of Arduino Pins to PWM4 channels as pin and index in PWM4 channel @@ -185,46 +195,44 @@ const uint8_t mapping_pin_PWM4[][2] = {{3, 0}, {4, 1}, {6, 2}, {9, 3}, /* Configurations of PWM channels for CCU4 type */ XMC_PWM4_t mapping_pwm4[] = { {CCU40, CCU40_CC41, 1, mapping_port_pin[3], P1_1_AF_CCU40_OUT1, XMC_CCU4_SLICE_PRESCALER_64, - PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 4 + PWM4_TIMER_PERIOD, 0, false}, // PWM disabled 4 {CCU40, CCU40_CC40, 0, mapping_port_pin[4], P1_0_AF_CCU40_OUT0, XMC_CCU4_SLICE_PRESCALER_64, - PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 4 + PWM4_TIMER_PERIOD, 0, false}, // PWM disabled 4 {CCU41, CCU41_CC40, 0, mapping_port_pin[6], P0_6_AF_CCU41_OUT0, XMC_CCU4_SLICE_PRESCALER_64, - PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 4 + PWM4_TIMER_PERIOD, 0, false}, // PWM disabled 4 {CCU40, CCU40_CC41, 1, mapping_port_pin[9], P0_7_AF_CCU40_OUT1, XMC_CCU4_SLICE_PRESCALER_64, - PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 4 + PWM4_TIMER_PERIOD, 0, false}, // PWM disabled 4 {CCU40, CCU40_CC41, 1, mapping_port_pin[10], P0_4_AF_CCU40_OUT1, XMC_CCU4_SLICE_PRESCALER_64, - PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 4 + PWM4_TIMER_PERIOD, 0, false}, // PWM disabled 4 {CCU40, CCU40_CC41, 1, mapping_port_pin[11], P0_1_AF_CCU40_OUT1, XMC_CCU4_SLICE_PRESCALER_64, - PWM4_TIMER_PERIOD, DISABLED} // PWM disabled 4 + PWM4_TIMER_PERIOD, 0, false} // PWM disabled 4 }; - const uint8_t NUM_PWM4 = (sizeof(mapping_pwm4) / sizeof(XMC_PWM4_t)); -const uint8_t NUM_PWM = (sizeof(mapping_pwm4) / sizeof(XMC_PWM4_t)); + +/* Configurations of PWM channels for CCU8 type */ +const uint8_t mapping_pin_PWM8[][2] = {{255, 255}}; +XMC_PWM8_t mapping_pwm8[] = {}; // Empty for now, no CCU8 channels defined + +const uint8_t NUM_PWM = NUM_PWM4; // Currently only PWM4 channels are defined /* Analog Pin mappings and configurations */ // ADC grouping for XMC 1400 series. XMC_ADC_t mapping_adc[] = { - {VADC, 0, VADC_G0, 0, 4, DISABLED}, // A0 - {VADC, 1, VADC_G0, 0, 11, DISABLED}, // A1 - {VADC, 2, VADC_G0, 0, 9, DISABLED}, // A2 - {VADC, 3, VADC_G0, 0, 12, DISABLED}, // A3 - {VADC, 6, VADC_G0, 0, 7, DISABLED}, // A4 - {VADC, 5, VADC_G0, 0, 10, DISABLED}, // A5 + {VADC, 0, VADC_G0, 0, 4, false}, // A0 + {VADC, 1, VADC_G0, 0, 11, false}, // A1 + {VADC, 2, VADC_G0, 0, 9, false}, // A2 + {VADC, 3, VADC_G0, 0, 12, false}, // A3 + {VADC, 6, VADC_G0, 0, 7, false}, // A4 + {VADC, 5, VADC_G0, 0, 10, false}, // A5 // Additional channels added here - {VADC, 4, VADC_G0, 0, 5, DISABLED}, // AUX 21 - {VADC, 1, VADC_G1, 1, 1, DISABLED}, // AUX 22 - {VADC, 7, VADC_G1, 1, 2, DISABLED}, // AUX 23 - {VADC, 7, VADC_G0, 0, 3, DISABLED} // AUX 24 + {VADC, 4, VADC_G0, 0, 5, false}, // AUX 21 + {VADC, 1, VADC_G1, 1, 1, false}, // AUX 22 + {VADC, 7, VADC_G1, 1, 2, false}, // AUX 23 + {VADC, 7, VADC_G0, 0, 3, false} // AUX 24 }; const uint8_t NUM_ANALOG_INPUTS = (sizeof(mapping_adc) / sizeof(XMC_ADC_t)); -/* - * UART objects - */ -RingBuffer rx_buffer_0; -RingBuffer tx_buffer_0; - /* First UART channel pins are swapped between debug and normal use */ XMC_UART_t XMC_UART_0 = {.channel = XMC_UART0_CH1, .rx = {.port = (XMC_GPIO_PORT_t *)PORT1_BASE, @@ -258,9 +266,9 @@ XMC_UART_t XMC_UART_0 = {.channel = XMC_UART0_CH1, .irq_num = USIC0_0_IRQn, .irq_service_request = 0}; -HardwareSerial Serial(&XMC_UART_0, &rx_buffer_0, &tx_buffer_0); +Uart Serial(&XMC_UART_0); -// SPI instance +// // SPI instance XMC_SPI_t XMC_SPI_0 = { .channel = XMC_SPI1_CH1, .channel_config = {.baudrate = 15984375U, @@ -325,9 +333,4 @@ void USIC0_0_IRQHandler() { Serial.IrqHandler(); } } #endif #endif /* ARDUINO_MAIN */ - -#ifdef __cplusplus -extern HardwareSerial Serial; -#endif /* cplusplus */ - #endif // PINS_ARDUINO_H_ diff --git a/variants/XMC1400/config/XMC1400_XMC2GO/pins_arduino.h b/variants/XMC1400/config/KIT_XMC14_2GO/pins_arduino.h similarity index 88% rename from variants/XMC1400/config/XMC1400_XMC2GO/pins_arduino.h rename to variants/XMC1400/config/KIT_XMC14_2GO/pins_arduino.h index 9642842c..1a2864c3 100644 --- a/variants/XMC1400/config/XMC1400_XMC2GO/pins_arduino.h +++ b/variants/XMC1400/config/KIT_XMC14_2GO/pins_arduino.h @@ -36,7 +36,7 @@ // XMC_BOARD for stringifying into serial or other text outputs/logs // Note the actual name XMC and number MUST have a character between // to avoid issues with other defined macros e.g. XMC1100 -#define XMC_BOARD XMC 1400 XMC2GO +#define XMC_BOARD KIT_XMC14_2GO /* On board LED is ON when digital output is 1, HIGH, TRUE, ON */ #define XMC_LED_ON 1 @@ -51,14 +51,13 @@ extern const uint8_t NUM_INTERRUPT; extern const uint8_t NUM_ANALOG_INPUTS; #define NUM_LEDS 2 #define NUM_SERIAL 1 -#define NUM_TONE_PINS 4 // PWM Pins +#define NUM_TONE_PINS 4 #define NUM_TASKS_VARIANT 8 #define NUM_SPI 1 #define NUM_I2C 1 // Indicate unit has RTC/Alarm #define HAS_RTC 1 - // Indicate variant has a GPIO pin used for Reset pin #define HAS_GPIO_RESET 1 @@ -75,6 +74,8 @@ extern const uint8_t NUM_ANALOG_INPUTS; // Generate 490Hz @fCCU=1MHz #define PWM4_TIMER_PERIOD (2041U) +// Generate 490Hz @fCCU=1MHz +#define PWM8_TIMER_PERIOD (2041U) // PCLK = 2 * MCLK #define PCLK 96000000u @@ -85,6 +86,10 @@ extern const uint8_t NUM_ANALOG_INPUTS; #define PIN_SPI_MISO 0 #define PIN_SPI_SCK 2 +extern uint8_t SS; +extern uint8_t MOSI; +extern uint8_t MISO; +extern uint8_t SCK; // Define analog pin #define A0 0 #define A1 1 @@ -141,7 +146,7 @@ extern const uint8_t NUM_ANALOG_INPUTS; #define CAN0_3_IRQHandler IRQ7_Handler // CAN #define CAN0_3_IRQn IRQ7_IRQn -#define digitalPinToInterrupt(p) (((p) == 9) ? 0 : NOT_AN_INTERRUPT) +#define digitalPinToInterrupt(p) (((p) == 9) ? 0 : -1) #ifdef ARDUINO_MAIN // Mapping of digital pins and comments @@ -170,10 +175,11 @@ const XMC_PORT_PIN_t mapping_port_pin[] = { }; const uint8_t GND = (sizeof(mapping_port_pin) / sizeof(XMC_PORT_PIN_t)); const uint8_t NUM_DIGITAL = (sizeof(mapping_port_pin) / sizeof(XMC_PORT_PIN_t)); +bool gpio_current_value[NUM_DIGITAL] = {false}; /* Configurations of Interrupt */ const XMC_PIN_INTERRUPT_t mapping_interrupt[] = { - /* 0 */ {CCU40, CCU40_CC40, 0, 0, CCU40_IN0_U0C0_DX2INS}}; + /* 0 */ {CCU40, CCU40_CC41, 1, 0, CCU40_IN0_U0C0_DX2INS}}; const uint8_t NUM_INTERRUPT = (sizeof(mapping_interrupt) / sizeof(XMC_PIN_INTERRUPT_t)); /* Mapping of Arduino Pins to PWM4 channels as pin and index in PWM4 channel @@ -186,43 +192,52 @@ const uint8_t mapping_pin_PWM4[][2] = {{1, 0}, {2, 1}, {3, 2}, {8, 3}, {9, 4}, { /* Configurations of PWM channels for CCU4 type */ XMC_PWM4_t mapping_pwm4[] = { {CCU40, CCU40_CC41, 1, mapping_port_pin[1], P0_1_AF_CCU40_OUT1, XMC_CCU4_SLICE_PRESCALER_64, - PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 1 P0.1 + PWM4_TIMER_PERIOD, 0, false}, // PWM disabled 1 P0.1 {CCU40, CCU40_CC43, 3, mapping_port_pin[2], P0_3_AF_CCU40_OUT3, XMC_CCU4_SLICE_PRESCALER_64, - PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 2 P0.3 + PWM4_TIMER_PERIOD, 0, false}, // PWM disabled 2 P0.3 {CCU40, CCU40_CC41, 1, mapping_port_pin[3], P0_4_AF_CCU40_OUT1, XMC_CCU4_SLICE_PRESCALER_64, - PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 3 P0.4 + PWM4_TIMER_PERIOD, 0, false}, // PWM disabled 3 P0.4 {CCU40, CCU40_CC40, 0, mapping_port_pin[8], P0_5_AF_CCU40_OUT0, XMC_CCU4_SLICE_PRESCALER_64, - PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 8 P0.5 + PWM4_TIMER_PERIOD, 0, false}, // PWM disabled 8 P0.5 {CCU41, CCU41_CC40, 0, mapping_port_pin[9], P1_4_AF_CCU41_OUT0, XMC_CCU4_SLICE_PRESCALER_64, - PWM4_TIMER_PERIOD, DISABLED} // PWM disabled 9 P1.4 + PWM4_TIMER_PERIOD, 0, false} // PWM disabled 9 P1.4 }; -const uint8_t NUM_PWM = (sizeof(mapping_pwm4) / sizeof(XMC_PWM4_t)); const uint8_t NUM_PWM4 = (sizeof(mapping_pwm4) / sizeof(XMC_PWM4_t)); +/* Mapping in same manner as PWM4 for PWM8 channels */ +const uint8_t mapping_pin_PWM8[][2] = {{4, 0}, {5, 1}, {255, 255}}; + +/* Configurations of PWM channels for CCU8 type */ +XMC_PWM8_t mapping_pwm8[] = { + {CCU80, CCU80_CC83, 3, XMC_CCU8_SLICE_COMPARE_CHANNEL_1, mapping_port_pin[4], + P0_14_AF_CCU80_OUT31, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, + false}, // PWM disabled 4 P0.14 + {CCU80, CCU80_CC83, 3, XMC_CCU8_SLICE_COMPARE_CHANNEL_1, mapping_port_pin[5], + P0_15_AF_CCU80_OUT30, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, + false} // PWM disabled 5 P0.15 +}; +const uint8_t NUM_PWM8 = (sizeof(mapping_pwm8) / sizeof(XMC_PWM8_t)); +const uint8_t NUM_PWM = + (sizeof(mapping_pwm4) / sizeof(XMC_PWM4_t)) + (sizeof(mapping_pwm8) / sizeof(XMC_PWM8_t)); + /* Analog Pin mappings and configurations */ // XMC_ADC_t mapping_adc[] = // { -// { VADC, 1, DISABLED }, //A0 P2.8 -// { VADC, 2, DISABLED }, //A1 P2.9 -// { VADC, 3, DISABLED }, //A2 P2.10 -// { VADC, 4, DISABLED }, //A3 P2.11 +// { VADC, 1, false }, //A0 P2.8 +// { VADC, 2, false }, //A1 P2.9 +// { VADC, 3, false }, //A2 P2.10 +// { VADC, 4, false }, //A3 P2.11 // }; XMC_ADC_t mapping_adc[] = { - {VADC, 1, VADC_G0, 0, 1, DISABLED}, // A0 P2.8 - {VADC, 2, VADC_G0, 0, 2, DISABLED}, // A1 P2.9 - {VADC, 3, VADC_G0, 0, 3, DISABLED}, // A2 P2.10 - {VADC, 4, VADC_G0, 0, 4, DISABLED}, // A3 P2.11 + {VADC, 1, VADC_G0, 0, 1, false}, // A0 P2.8 + {VADC, 2, VADC_G0, 0, 2, false}, // A1 P2.9 + {VADC, 3, VADC_G0, 0, 3, false}, // A2 P2.10 + {VADC, 4, VADC_G0, 0, 4, false}, // A3 P2.11 }; const uint8_t NUM_ANALOG_INPUTS = (sizeof(mapping_adc) / sizeof(XMC_ADC_t)); -/* - * UART objects - */ -RingBuffer rx_buffer_0; -RingBuffer tx_buffer_0; - /* First UART channel pins are swapped between debug and normal use */ XMC_UART_t XMC_UART_0 = {.channel = XMC_UART0_CH0, .rx = {.port = (XMC_GPIO_PORT_t *)PORT2_BASE, // RX P2.6 @@ -260,9 +275,9 @@ XMC_UART_t XMC_UART_0 = {.channel = XMC_UART0_CH0, .irq_num = USIC0_0_IRQn, .irq_service_request = 0}; -HardwareSerial Serial(&XMC_UART_0, &rx_buffer_0, &tx_buffer_0); +Uart Serial(&XMC_UART_0); -// SPI instance +// // SPI instance XMC_SPI_t XMC_SPI_0 = { .channel = XMC_SPI1_CH1, .channel_config = {.baudrate = 15984375U, @@ -367,9 +382,4 @@ void USIC0_0_IRQHandler() { Serial.IrqHandler(); } } #endif #endif /* ARDUINO_MAIN */ - -#ifdef __cplusplus -extern HardwareSerial Serial; -#endif /* cplusplus */ - #endif // PINS_ARDUINO_H_ diff --git a/variants/XMC4200/XMC4200.h b/variants/XMC4200/XMC4200.h deleted file mode 100644 index 44694417..00000000 --- a/variants/XMC4200/XMC4200.h +++ /dev/null @@ -1,21635 +0,0 @@ -/********************************************************************************************************************* - * Copyright (c) 2011-2020, Infineon Technologies AG - * All rights reserved. - * - * Boost Software License - Version 1.0 - August 17th, 2003 - * - * Permission is hereby granted, free of charge, to any person or organization - * obtaining a copy of the software and accompanying documentation covered by - * this license (the "Software") to use, reproduce, display, distribute, - * execute, and transmit the Software, and to prepare derivative works of the - * Software, and to permit third-parties to whom the Software is furnished to - * do so, all subject to the following: - * - * The copyright notices in the Software and this entire statement, including - * the above license grant, this restriction and the following disclaimer, - * must be included in all copies of the Software, in whole or in part, and - * all derivative works of the Software, unless such copies or derivative - * works are solely in the form of machine-executable object code generated by - * a source language processor. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT - * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE - * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * To improve the quality of the software, users are encouraged to share - * modifications, enhancements or bug fixes with Infineon Technologies AG - * at XMCSupport@infineon.com. - *********************************************************************************************************************/ - -/****************************************************************************************************/ /** - * @file XMC4200.h - * - * @brief CMSIS Cortex-M4 Peripheral Access Layer Header File for - * XMC4200 from Infineon. - * - * @version V1.6.2 (Reference Manual v1.6) - * @date 01. Sep 2020 - * - * @note Generated with SVDConv V2.87l - * from CMSIS SVD File 'XMC4200_Processed_SVD.xml' Version 1.6.0 (Reference Manual v1.6), - * added support for ARM Compiler 6 (armclang) - *******************************************************************************************************/ - -/** @addtogroup Infineon - * @{ - */ - -/** @addtogroup XMC4200 - * @{ - */ - -#ifndef XMC4200_H -#define XMC4200_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -typedef enum { - /* ------------------- Cortex-M4 Processor Exceptions Numbers ------------------- */ - Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ - NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ - HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ - MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access - Violation and No Match */ - BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory - related Fault */ - UsageFault_IRQn = - -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ - SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ - DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ - PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ - SysTick_IRQn = -1, /*!< 15 System Tick Timer */ - /* --------------------- XMC4200 Specific Interrupt Numbers --------------------- */ - SCU_0_IRQn = 0, /*!< 0 System Control */ - ERU0_0_IRQn = 1, /*!< 1 External Request Unit 0 */ - ERU0_1_IRQn = 2, /*!< 2 External Request Unit 0 */ - ERU0_2_IRQn = 3, /*!< 3 External Request Unit 0 */ - ERU0_3_IRQn = 4, /*!< 4 External Request Unit 0 */ - ERU1_0_IRQn = 5, /*!< 5 External Request Unit 1 */ - ERU1_1_IRQn = 6, /*!< 6 External Request Unit 1 */ - ERU1_2_IRQn = 7, /*!< 7 External Request Unit 1 */ - ERU1_3_IRQn = 8, /*!< 8 External Request Unit 1 */ - PMU0_0_IRQn = 12, /*!< 12 Program Management Unit */ - VADC0_C0_0_IRQn = 14, /*!< 14 Analog to Digital Converter Common Block 0 */ - VADC0_C0_1_IRQn = 15, /*!< 15 Analog to Digital Converter Common Block 0 */ - VADC0_C0_2_IRQn = 16, /*!< 16 Analog to Digital Converter Common Block 0 */ - VADC0_C0_3_IRQn = 17, /*!< 17 Analog to Digital Converter Common Block 0 */ - VADC0_G0_0_IRQn = 18, /*!< 18 Analog to Digital Converter Group 0 */ - VADC0_G0_1_IRQn = 19, /*!< 19 Analog to Digital Converter Group 0 */ - VADC0_G0_2_IRQn = 20, /*!< 20 Analog to Digital Converter Group 0 */ - VADC0_G0_3_IRQn = 21, /*!< 21 Analog to Digital Converter Group 0 */ - VADC0_G1_0_IRQn = 22, /*!< 22 Analog to Digital Converter Group 1 */ - VADC0_G1_1_IRQn = 23, /*!< 23 Analog to Digital Converter Group 1 */ - VADC0_G1_2_IRQn = 24, /*!< 24 Analog to Digital Converter Group 1 */ - VADC0_G1_3_IRQn = 25, /*!< 25 Analog to Digital Converter Group 1 */ - DAC0_0_IRQn = 42, /*!< 42 Digital to Analog Converter */ - DAC0_1_IRQn = 43, /*!< 43 Digital to Analog Converter */ - CCU40_0_IRQn = 44, /*!< 44 Capture Compare Unit 4 (Module 0) */ - CCU40_1_IRQn = 45, /*!< 45 Capture Compare Unit 4 (Module 0) */ - CCU40_2_IRQn = 46, /*!< 46 Capture Compare Unit 4 (Module 0) */ - CCU40_3_IRQn = 47, /*!< 47 Capture Compare Unit 4 (Module 0) */ - CCU41_0_IRQn = 48, /*!< 48 Capture Compare Unit 4 (Module 1) */ - CCU41_1_IRQn = 49, /*!< 49 Capture Compare Unit 4 (Module 1) */ - CCU41_2_IRQn = 50, /*!< 50 Capture Compare Unit 4 (Module 1) */ - CCU41_3_IRQn = 51, /*!< 51 Capture Compare Unit 4 (Module 1) */ - CCU80_0_IRQn = 60, /*!< 60 Capture Compare Unit 8 (Module 0) */ - CCU80_1_IRQn = 61, /*!< 61 Capture Compare Unit 8 (Module 0) */ - CCU80_2_IRQn = 62, /*!< 62 Capture Compare Unit 8 (Module 0) */ - CCU80_3_IRQn = 63, /*!< 63 Capture Compare Unit 8 (Module 0) */ - POSIF0_0_IRQn = 68, /*!< 68 Position Interface (Module 0) */ - POSIF0_1_IRQn = 69, /*!< 69 Position Interface (Module 0) */ - HRPWM_0_IRQn = 72, /*!< 72 High Resolution Pulse Width Modulation (Module 0) */ - HRPWM_1_IRQn = 73, /*!< 73 High Resolution Pulse Width Modulation (Module 0) */ - HRPWM_2_IRQn = 74, /*!< 74 High Resolution Pulse Width Modulation (Module 0) */ - HRPWM_3_IRQn = 75, /*!< 75 High Resolution Pulse Width Modulation (Module 0) */ - CAN0_0_IRQn = 76, /*!< 76 MultiCAN */ - CAN0_1_IRQn = 77, /*!< 77 MultiCAN */ - CAN0_2_IRQn = 78, /*!< 78 MultiCAN */ - CAN0_3_IRQn = 79, /*!< 79 MultiCAN */ - CAN0_4_IRQn = 80, /*!< 80 MultiCAN */ - CAN0_5_IRQn = 81, /*!< 81 MultiCAN */ - CAN0_6_IRQn = 82, /*!< 82 MultiCAN */ - CAN0_7_IRQn = 83, /*!< 83 MultiCAN */ - USIC0_0_IRQn = 84, /*!< 84 Universal Serial Interface Channel (Module 0) */ - USIC0_1_IRQn = 85, /*!< 85 Universal Serial Interface Channel (Module 0) */ - USIC0_2_IRQn = 86, /*!< 86 Universal Serial Interface Channel (Module 0) */ - USIC0_3_IRQn = 87, /*!< 87 Universal Serial Interface Channel (Module 0) */ - USIC0_4_IRQn = 88, /*!< 88 Universal Serial Interface Channel (Module 0) */ - USIC0_5_IRQn = 89, /*!< 89 Universal Serial Interface Channel (Module 0) */ - USIC1_0_IRQn = 90, /*!< 90 Universal Serial Interface Channel (Module 1) */ - USIC1_1_IRQn = 91, /*!< 91 Universal Serial Interface Channel (Module 1) */ - USIC1_2_IRQn = 92, /*!< 92 Universal Serial Interface Channel (Module 1) */ - USIC1_3_IRQn = 93, /*!< 93 Universal Serial Interface Channel (Module 1) */ - USIC1_4_IRQn = 94, /*!< 94 Universal Serial Interface Channel (Module 1) */ - USIC1_5_IRQn = 95, /*!< 95 Universal Serial Interface Channel (Module 1) */ - LEDTS0_0_IRQn = 102, /*!< 102 LED and Touch Sense Control Unit (Module 0) */ - FCE0_0_IRQn = 104, /*!< 104 Flexible CRC Engine */ - GPDMA0_0_IRQn = 105, /*!< 105 General Purpose DMA Unit 0 */ - USB0_0_IRQn = 107 /*!< 107 Universal Serial Bus (Module 0) */ -} IRQn_Type; - -/** @addtogroup Configuration_of_CMSIS - * @{ - */ - -/* ================================================================================ */ -/* ================ Processor and Core Peripheral Section ================ */ -/* ================================================================================ */ - -/* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */ -#define __CM4_REV \ - 0x0200 /*!< Cortex-M4 Core Revision */ -#define __MPU_PRESENT \ - 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS \ - 6 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig \ - 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT \ - 1 /*!< FPU present or not */ -/** @} */ /* End of group Configuration_of_CMSIS */ - -#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */ -#include "system_XMC4200.h" /*!< XMC4200 System */ - -/* ================================================================================ */ -/* ================ Device Specific Peripheral Section ================ */ -/* ================================================================================ */ -/* Macro to modify desired bitfields of a register */ -#define WR_REG(reg, mask, pos, val) \ - reg = (((uint32_t)val << pos) & ((uint32_t)mask)) | (reg & ((uint32_t) ~((uint32_t)mask))) - -/* Macro to modify desired bitfields of a register */ -#define WR_REG_SIZE(reg, mask, pos, val, size) \ - { \ - uint##size##_t VAL1 = (uint##size##_t)((uint##size##_t)val << pos); \ - uint##size##_t VAL2 = (uint##size##_t)(VAL1 & (uint##size##_t)mask); \ - uint##size##_t VAL3 = (uint##size##_t) ~((uint##size##_t)mask); \ - uint##size##_t VAL4 = (uint##size##_t)((uint##size##_t)reg & VAL3); \ - reg = (uint##size##_t)(VAL2 | VAL4); \ - } - -/** Macro to read bitfields from a register */ -#define RD_REG(reg, mask, pos) (((uint32_t)reg & (uint32_t)mask) >> pos) - -/** Macro to read bitfields from a register */ -#define RD_REG_SIZE(reg, mask, pos, size) \ - ((uint##size##_t)(((uint32_t)reg & (uint32_t)mask) >> pos)) - -/** Macro to set a bit in register */ -#define SET_BIT(reg, pos) (reg |= ((uint32_t)1 << pos)) - -/** Macro to clear a bit in register */ -#define CLR_BIT(reg, pos) (reg = reg & (uint32_t)(~((uint32_t)1 << pos))) -/* - * ========================================================================== - * ---------- Interrupt Handler Definition ---------------------------------- - * ========================================================================== - */ -#define IRQ_Hdlr_0 SCU_0_IRQHandler -#define IRQ_Hdlr_1 ERU0_0_IRQHandler -#define IRQ_Hdlr_2 ERU0_1_IRQHandler -#define IRQ_Hdlr_3 ERU0_2_IRQHandler -#define IRQ_Hdlr_4 ERU0_3_IRQHandler -#define IRQ_Hdlr_5 ERU1_0_IRQHandler -#define IRQ_Hdlr_6 ERU1_1_IRQHandler -#define IRQ_Hdlr_7 ERU1_2_IRQHandler -#define IRQ_Hdlr_8 ERU1_3_IRQHandler -#define IRQ_Hdlr_12 PMU0_0_IRQHandler -#define IRQ_Hdlr_14 VADC0_C0_0_IRQHandler -#define IRQ_Hdlr_15 VADC0_C0_1_IRQHandler -#define IRQ_Hdlr_16 VADC0_C0_2_IRQHandler -#define IRQ_Hdlr_17 VADC0_C0_3_IRQHandler -#define IRQ_Hdlr_18 VADC0_G0_0_IRQHandler -#define IRQ_Hdlr_19 VADC0_G0_1_IRQHandler -#define IRQ_Hdlr_20 VADC0_G0_2_IRQHandler -#define IRQ_Hdlr_21 VADC0_G0_3_IRQHandler -#define IRQ_Hdlr_22 VADC0_G1_0_IRQHandler -#define IRQ_Hdlr_23 VADC0_G1_1_IRQHandler -#define IRQ_Hdlr_24 VADC0_G1_2_IRQHandler -#define IRQ_Hdlr_25 VADC0_G1_3_IRQHandler -#define IRQ_Hdlr_42 DAC0_0_IRQHandler -#define IRQ_Hdlr_43 DAC0_1_IRQHandler -#define IRQ_Hdlr_44 CCU40_0_IRQHandler -#define IRQ_Hdlr_45 CCU40_1_IRQHandler -#define IRQ_Hdlr_46 CCU40_2_IRQHandler -#define IRQ_Hdlr_47 CCU40_3_IRQHandler -#define IRQ_Hdlr_48 CCU41_0_IRQHandler -#define IRQ_Hdlr_49 CCU41_1_IRQHandler -#define IRQ_Hdlr_50 CCU41_2_IRQHandler -#define IRQ_Hdlr_51 CCU41_3_IRQHandler -#define IRQ_Hdlr_60 CCU80_0_IRQHandler -#define IRQ_Hdlr_61 CCU80_1_IRQHandler -#define IRQ_Hdlr_62 CCU80_2_IRQHandler -#define IRQ_Hdlr_63 CCU80_3_IRQHandler -#define IRQ_Hdlr_68 POSIF0_0_IRQHandler -#define IRQ_Hdlr_69 POSIF0_1_IRQHandler -#define IRQ_Hdlr_72 HRPWM_0_IRQHandler -#define IRQ_Hdlr_73 HRPWM_1_IRQHandler -#define IRQ_Hdlr_74 HRPWM_2_IRQHandler -#define IRQ_Hdlr_75 HRPWM_3_IRQHandler -#define IRQ_Hdlr_76 CAN0_0_IRQHandler -#define IRQ_Hdlr_77 CAN0_1_IRQHandler -#define IRQ_Hdlr_78 CAN0_2_IRQHandler -#define IRQ_Hdlr_79 CAN0_3_IRQHandler -#define IRQ_Hdlr_80 CAN0_4_IRQHandler -#define IRQ_Hdlr_81 CAN0_5_IRQHandler -#define IRQ_Hdlr_82 CAN0_6_IRQHandler -#define IRQ_Hdlr_83 CAN0_7_IRQHandler -#define IRQ_Hdlr_84 USIC0_0_IRQHandler -#define IRQ_Hdlr_85 USIC0_1_IRQHandler -#define IRQ_Hdlr_86 USIC0_2_IRQHandler -#define IRQ_Hdlr_87 USIC0_3_IRQHandler -#define IRQ_Hdlr_88 USIC0_4_IRQHandler -#define IRQ_Hdlr_89 USIC0_5_IRQHandler -#define IRQ_Hdlr_90 USIC1_0_IRQHandler -#define IRQ_Hdlr_91 USIC1_1_IRQHandler -#define IRQ_Hdlr_92 USIC1_2_IRQHandler -#define IRQ_Hdlr_93 USIC1_3_IRQHandler -#define IRQ_Hdlr_94 USIC1_4_IRQHandler -#define IRQ_Hdlr_95 USIC1_5_IRQHandler -#define IRQ_Hdlr_102 LEDTS0_0_IRQHandler -#define IRQ_Hdlr_104 FCE0_0_IRQHandler -#define IRQ_Hdlr_105 GPDMA0_0_IRQHandler -#define IRQ_Hdlr_107 USB0_0_IRQHandler - -/* - * ========================================================================== - * ---------- Interrupt Handler retrieval macro ----------------------------- - * ========================================================================== - */ -#define GET_IRQ_HANDLER(N) IRQ_Hdlr_##N - -/** @addtogroup Device_Peripheral_Registers - * @{ - */ - -/* ------------------- Start of section using anonymous unions ------------------ */ -#if defined(__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wc11-extensions" - #pragma clang diagnostic ignored "-Wreserved-id-macro" -#elif defined(__ICCARM__) - #pragma language = extended -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__TMS470__) -/* anonymous unions are enabled by default */ -#elif defined(__TASKING__) - #pragma warning 586 -#else - #warning Not supported compiler type -#endif - -/* ================================================================================ */ -/* ================ PPB ================ */ -/* ================================================================================ */ - -/** - * @brief Cortex-M4 Private Peripheral Block (PPB) - */ - -typedef struct { /*!< (@ 0xE000E000) PPB Structure */ - __I uint32_t RESERVED[2]; - __IO uint32_t ACTLR; /*!< (@ 0xE000E008) Auxiliary Control Register */ - __I uint32_t RESERVED1; - __IO uint32_t SYST_CSR; /*!< (@ 0xE000E010) SysTick Control and Status Register */ - __IO uint32_t SYST_RVR; /*!< (@ 0xE000E014) SysTick Reload Value Register */ - __IO uint32_t SYST_CVR; /*!< (@ 0xE000E018) SysTick Current Value Register */ - __IO uint32_t SYST_CALIB; /*!< (@ 0xE000E01C) SysTick Calibration Value Register r */ - __I uint32_t RESERVED2[56]; - __IO uint32_t NVIC_ISER0; /*!< (@ 0xE000E100) Interrupt Set-enable Register 0 */ - __IO uint32_t NVIC_ISER1; /*!< (@ 0xE000E104) Interrupt Set-enable Register 1 */ - __IO uint32_t NVIC_ISER2; /*!< (@ 0xE000E108) Interrupt Set-enable Register 2 */ - __IO uint32_t NVIC_ISER3; /*!< (@ 0xE000E10C) Interrupt Set-enable Register 3 */ - __I uint32_t RESERVED3[28]; - __IO uint32_t NVIC_ICER0; /*!< (@ 0xE000E180) Interrupt Clear-enable Register 0 */ - __IO uint32_t NVIC_ICER1; /*!< (@ 0xE000E184) Interrupt Clear-enable Register 1 */ - __IO uint32_t NVIC_ICER2; /*!< (@ 0xE000E188) Interrupt Clear-enable Register 2 */ - __IO uint32_t NVIC_ICER3; /*!< (@ 0xE000E18C) Interrupt Clear-enable Register 3 */ - __I uint32_t RESERVED4[28]; - __IO uint32_t NVIC_ISPR0; /*!< (@ 0xE000E200) Interrupt Set-pending Register 0 */ - __IO uint32_t NVIC_ISPR1; /*!< (@ 0xE000E204) Interrupt Set-pending Register 1 */ - __IO uint32_t NVIC_ISPR2; /*!< (@ 0xE000E208) Interrupt Set-pending Register 2 */ - __IO uint32_t NVIC_ISPR3; /*!< (@ 0xE000E20C) Interrupt Set-pending Register 3 */ - __I uint32_t RESERVED5[28]; - __IO uint32_t NVIC_ICPR0; /*!< (@ 0xE000E280) Interrupt Clear-pending Register 0 */ - __IO uint32_t NVIC_ICPR1; /*!< (@ 0xE000E284) Interrupt Clear-pending Register 1 */ - __IO uint32_t NVIC_ICPR2; /*!< (@ 0xE000E288) Interrupt Clear-pending Register 2 */ - __IO uint32_t NVIC_ICPR3; /*!< (@ 0xE000E28C) Interrupt Clear-pending Register 3 */ - __I uint32_t RESERVED6[28]; - __IO uint32_t NVIC_IABR0; /*!< (@ 0xE000E300) Interrupt Active Bit Register 0 */ - __IO uint32_t NVIC_IABR1; /*!< (@ 0xE000E304) Interrupt Active Bit Register 1 */ - __IO uint32_t NVIC_IABR2; /*!< (@ 0xE000E308) Interrupt Active Bit Register 2 */ - __IO uint32_t NVIC_IABR3; /*!< (@ 0xE000E30C) Interrupt Active Bit Register 3 */ - __I uint32_t RESERVED7[60]; - __IO uint32_t NVIC_IPR0; /*!< (@ 0xE000E400) Interrupt Priority Register 0 */ - __IO uint32_t NVIC_IPR1; /*!< (@ 0xE000E404) Interrupt Priority Register 1 */ - __IO uint32_t NVIC_IPR2; /*!< (@ 0xE000E408) Interrupt Priority Register 2 */ - __IO uint32_t NVIC_IPR3; /*!< (@ 0xE000E40C) Interrupt Priority Register 3 */ - __IO uint32_t NVIC_IPR4; /*!< (@ 0xE000E410) Interrupt Priority Register 4 */ - __IO uint32_t NVIC_IPR5; /*!< (@ 0xE000E414) Interrupt Priority Register 5 */ - __IO uint32_t NVIC_IPR6; /*!< (@ 0xE000E418) Interrupt Priority Register 6 */ - __IO uint32_t NVIC_IPR7; /*!< (@ 0xE000E41C) Interrupt Priority Register 7 */ - __IO uint32_t NVIC_IPR8; /*!< (@ 0xE000E420) Interrupt Priority Register 8 */ - __IO uint32_t NVIC_IPR9; /*!< (@ 0xE000E424) Interrupt Priority Register 9 */ - __IO uint32_t NVIC_IPR10; /*!< (@ 0xE000E428) Interrupt Priority Register 10 */ - __IO uint32_t NVIC_IPR11; /*!< (@ 0xE000E42C) Interrupt Priority Register 11 */ - __IO uint32_t NVIC_IPR12; /*!< (@ 0xE000E430) Interrupt Priority Register 12 */ - __IO uint32_t NVIC_IPR13; /*!< (@ 0xE000E434) Interrupt Priority Register 13 */ - __IO uint32_t NVIC_IPR14; /*!< (@ 0xE000E438) Interrupt Priority Register 14 */ - __IO uint32_t NVIC_IPR15; /*!< (@ 0xE000E43C) Interrupt Priority Register 15 */ - __IO uint32_t NVIC_IPR16; /*!< (@ 0xE000E440) Interrupt Priority Register 16 */ - __IO uint32_t NVIC_IPR17; /*!< (@ 0xE000E444) Interrupt Priority Register 17 */ - __IO uint32_t NVIC_IPR18; /*!< (@ 0xE000E448) Interrupt Priority Register 18 */ - __IO uint32_t NVIC_IPR19; /*!< (@ 0xE000E44C) Interrupt Priority Register 19 */ - __IO uint32_t NVIC_IPR20; /*!< (@ 0xE000E450) Interrupt Priority Register 20 */ - __IO uint32_t NVIC_IPR21; /*!< (@ 0xE000E454) Interrupt Priority Register 21 */ - __IO uint32_t NVIC_IPR22; /*!< (@ 0xE000E458) Interrupt Priority Register 22 */ - __IO uint32_t NVIC_IPR23; /*!< (@ 0xE000E45C) Interrupt Priority Register 23 */ - __IO uint32_t NVIC_IPR24; /*!< (@ 0xE000E460) Interrupt Priority Register 24 */ - __IO uint32_t NVIC_IPR25; /*!< (@ 0xE000E464) Interrupt Priority Register 25 */ - __IO uint32_t NVIC_IPR26; /*!< (@ 0xE000E468) Interrupt Priority Register 26 */ - __IO uint32_t NVIC_IPR27; /*!< (@ 0xE000E46C) Interrupt Priority Register 27 */ - __I uint32_t RESERVED8[548]; - __I uint32_t CPUID; /*!< (@ 0xE000ED00) CPUID Base Register */ - __IO uint32_t ICSR; /*!< (@ 0xE000ED04) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< (@ 0xE000ED08) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< (@ 0xE000ED0C) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< (@ 0xE000ED10) System Control Register */ - __IO uint32_t CCR; /*!< (@ 0xE000ED14) Configuration and Control Register */ - __IO uint32_t SHPR1; /*!< (@ 0xE000ED18) System Handler Priority Register 1 */ - __IO uint32_t SHPR2; /*!< (@ 0xE000ED1C) System Handler Priority Register 2 */ - __IO uint32_t SHPR3; /*!< (@ 0xE000ED20) System Handler Priority Register 3 */ - __IO uint32_t SHCSR; /*!< (@ 0xE000ED24) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< (@ 0xE000ED28) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< (@ 0xE000ED2C) HardFault Status Register */ - __I uint32_t RESERVED9; - __IO uint32_t MMFAR; /*!< (@ 0xE000ED34) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< (@ 0xE000ED38) BusFault Address Register */ - __IO uint32_t AFSR; /*!< (@ 0xE000ED3C) Auxiliary Fault Status Register */ - __I uint32_t RESERVED10[18]; - __IO uint32_t CPACR; /*!< (@ 0xE000ED88) Coprocessor Access Control Register */ - __I uint32_t RESERVED11; - __I uint32_t MPU_TYPE; /*!< (@ 0xE000ED90) MPU Type Register */ - __IO uint32_t MPU_CTRL; /*!< (@ 0xE000ED94) MPU Control Register */ - __IO uint32_t MPU_RNR; /*!< (@ 0xE000ED98) MPU Region Number Register */ - __IO uint32_t MPU_RBAR; /*!< (@ 0xE000ED9C) MPU Region Base Address Register */ - __IO uint32_t MPU_RASR; /*!< (@ 0xE000EDA0) MPU Region Attribute and Size Register */ - __IO uint32_t MPU_RBAR_A1; /*!< (@ 0xE000EDA4) MPU Region Base Address Register A1 */ - __IO uint32_t MPU_RASR_A1; /*!< (@ 0xE000EDA8) MPU Region Attribute and Size Register A1 */ - __IO uint32_t MPU_RBAR_A2; /*!< (@ 0xE000EDAC) MPU Region Base Address Register A2 */ - __IO uint32_t MPU_RASR_A2; /*!< (@ 0xE000EDB0) MPU Region Attribute and Size Register A2 */ - __IO uint32_t MPU_RBAR_A3; /*!< (@ 0xE000EDB4) MPU Region Base Address Register A3 */ - __IO uint32_t MPU_RASR_A3; /*!< (@ 0xE000EDB8) MPU Region Attribute and Size Register A3 */ - __I uint32_t RESERVED12[81]; - __O uint32_t STIR; /*!< (@ 0xE000EF00) Software Trigger Interrupt Register */ - __I uint32_t RESERVED13[12]; - __IO uint32_t FPCCR; /*!< (@ 0xE000EF34) Floating-point Context Control Register */ - __IO uint32_t FPCAR; /*!< (@ 0xE000EF38) Floating-point Context Address Register */ - __IO uint32_t FPDSCR; /*!< (@ 0xE000EF3C) Floating-point Default Status Control Register */ -} PPB_Type; - -/* ================================================================================ */ -/* ================ DLR ================ */ -/* ================================================================================ */ - -/** - * @brief DMA Line Router (DLR) - */ - -typedef struct { /*!< (@ 0x50004900) DLR Structure */ - __I uint32_t OVRSTAT; /*!< (@ 0x50004900) Overrun Status */ - __O uint32_t OVRCLR; /*!< (@ 0x50004904) Overrun Clear */ - __IO uint32_t SRSEL0; /*!< (@ 0x50004908) Service Request Selection 0 */ - __I uint32_t RESERVED; - __IO uint32_t LNEN; /*!< (@ 0x50004910) Line Enable */ -} DLR_GLOBAL_TypeDef; - -/* ================================================================================ */ -/* ================ ERU [ERU0] ================ */ -/* ================================================================================ */ - -/** - * @brief Event Request Unit 0 (ERU) - */ - -typedef struct { /*!< (@ 0x50004800) ERU Structure */ - __IO uint32_t EXISEL; /*!< (@ 0x50004800) Event Input Select */ - __I uint32_t RESERVED[3]; - __IO uint32_t EXICON[4]; /*!< (@ 0x50004810) Event Input Control */ - __IO uint32_t EXOCON[4]; /*!< (@ 0x50004820) Event Output Trigger Control */ -} ERU_GLOBAL_TypeDef; - -/* ================================================================================ */ -/* ================ GPDMA0 ================ */ -/* ================================================================================ */ - -/** - * @brief General Purpose DMA Unit 0 (GPDMA0) - */ - -typedef struct { /*!< (@ 0x500142C0) GPDMA0 Structure */ - __IO uint32_t RAWTFR; /*!< (@ 0x500142C0) Raw IntTfr Status */ - __I uint32_t RESERVED; - __IO uint32_t RAWBLOCK; /*!< (@ 0x500142C8) Raw IntBlock Status */ - __I uint32_t RESERVED1; - __IO uint32_t RAWSRCTRAN; /*!< (@ 0x500142D0) Raw IntSrcTran Status */ - __I uint32_t RESERVED2; - __IO uint32_t RAWDSTTRAN; /*!< (@ 0x500142D8) Raw IntBlock Status */ - __I uint32_t RESERVED3; - __IO uint32_t RAWERR; /*!< (@ 0x500142E0) Raw IntErr Status */ - __I uint32_t RESERVED4; - __I uint32_t STATUSTFR; /*!< (@ 0x500142E8) IntTfr Status */ - __I uint32_t RESERVED5; - __I uint32_t STATUSBLOCK; /*!< (@ 0x500142F0) IntBlock Status */ - __I uint32_t RESERVED6; - __I uint32_t STATUSSRCTRAN; /*!< (@ 0x500142F8) IntSrcTran Status */ - __I uint32_t RESERVED7; - __I uint32_t STATUSDSTTRAN; /*!< (@ 0x50014300) IntBlock Status */ - __I uint32_t RESERVED8; - __I uint32_t STATUSERR; /*!< (@ 0x50014308) IntErr Status */ - __I uint32_t RESERVED9; - __IO uint32_t MASKTFR; /*!< (@ 0x50014310) Mask for Raw IntTfr Status */ - __I uint32_t RESERVED10; - __IO uint32_t MASKBLOCK; /*!< (@ 0x50014318) Mask for Raw IntBlock Status */ - __I uint32_t RESERVED11; - __IO uint32_t MASKSRCTRAN; /*!< (@ 0x50014320) Mask for Raw IntSrcTran Status */ - __I uint32_t RESERVED12; - __IO uint32_t MASKDSTTRAN; /*!< (@ 0x50014328) Mask for Raw IntBlock Status */ - __I uint32_t RESERVED13; - __IO uint32_t MASKERR; /*!< (@ 0x50014330) Mask for Raw IntErr Status */ - __I uint32_t RESERVED14; - __O uint32_t CLEARTFR; /*!< (@ 0x50014338) IntTfr Status */ - __I uint32_t RESERVED15; - __O uint32_t CLEARBLOCK; /*!< (@ 0x50014340) IntBlock Status */ - __I uint32_t RESERVED16; - __O uint32_t CLEARSRCTRAN; /*!< (@ 0x50014348) IntSrcTran Status */ - __I uint32_t RESERVED17; - __O uint32_t CLEARDSTTRAN; /*!< (@ 0x50014350) IntBlock Status */ - __I uint32_t RESERVED18; - __O uint32_t CLEARERR; /*!< (@ 0x50014358) IntErr Status */ - __I uint32_t RESERVED19; - __I uint32_t STATUSINT; /*!< (@ 0x50014360) Combined Interrupt Status Register */ - __I uint32_t RESERVED20; - __IO uint32_t REQSRCREG; /*!< (@ 0x50014368) Source Software Transaction Request Register */ - __I uint32_t RESERVED21; - __IO uint32_t - REQDSTREG; /*!< (@ 0x50014370) Destination Software Transaction Request Register */ - __I uint32_t RESERVED22; - __IO uint32_t SGLREQSRCREG; /*!< (@ 0x50014378) Single Source Transaction Request Register */ - __I uint32_t RESERVED23; - __IO uint32_t - SGLREQDSTREG; /*!< (@ 0x50014380) Single Destination Transaction Request Register */ - __I uint32_t RESERVED24; - __IO uint32_t LSTSRCREG; /*!< (@ 0x50014388) Last Source Transaction Request Register */ - __I uint32_t RESERVED25; - __IO uint32_t LSTDSTREG; /*!< (@ 0x50014390) Last Destination Transaction Request Register */ - __I uint32_t RESERVED26; - __IO uint32_t DMACFGREG; /*!< (@ 0x50014398) GPDMA Configuration Register */ - __I uint32_t RESERVED27; - __IO uint32_t CHENREG; /*!< (@ 0x500143A0) GPDMA Channel Enable Register */ - __I uint32_t RESERVED28; - __I uint32_t ID; /*!< (@ 0x500143A8) GPDMA0 ID Register */ - __I uint32_t RESERVED29[19]; - __I uint32_t TYPE; /*!< (@ 0x500143F8) GPDMA Component Type */ - __I uint32_t VERSION; /*!< (@ 0x500143FC) DMA Component Version */ -} GPDMA0_GLOBAL_TypeDef; - -/* ================================================================================ */ -/* ================ GPDMA0_CH0_1 [GPDMA0_CH0] ================ */ -/* ================================================================================ */ - -/** - * @brief General Purpose DMA Unit 0 (GPDMA0_CH0_1) - */ - -typedef struct { /*!< (@ 0x50014000) GPDMA0_CH0_1 Structure */ - __IO uint32_t SAR; /*!< (@ 0x50014000) Source Address Register */ - __I uint32_t RESERVED; - __IO uint32_t DAR; /*!< (@ 0x50014008) Destination Address Register */ - __I uint32_t RESERVED1; - __IO uint32_t LLP; /*!< (@ 0x50014010) Linked List Pointer Register */ - __I uint32_t RESERVED2; - __IO uint32_t CTLL; /*!< (@ 0x50014018) Control Register Low */ - __IO uint32_t CTLH; /*!< (@ 0x5001401C) Control Register High */ - __IO uint32_t SSTAT; /*!< (@ 0x50014020) Source Status Register */ - __I uint32_t RESERVED3; - __IO uint32_t DSTAT; /*!< (@ 0x50014028) Destination Status Register */ - __I uint32_t RESERVED4; - __IO uint32_t SSTATAR; /*!< (@ 0x50014030) Source Status Address Register */ - __I uint32_t RESERVED5; - __IO uint32_t DSTATAR; /*!< (@ 0x50014038) Destination Status Address Register */ - __I uint32_t RESERVED6; - __IO uint32_t CFGL; /*!< (@ 0x50014040) Configuration Register Low */ - __IO uint32_t CFGH; /*!< (@ 0x50014044) Configuration Register High */ - __IO uint32_t SGR; /*!< (@ 0x50014048) Source Gather Register */ - __I uint32_t RESERVED7; - __IO uint32_t DSR; /*!< (@ 0x50014050) Destination Scatter Register */ -} GPDMA0_CH_TypeDef; - -/* ================================================================================ */ -/* ================ GPDMA0_CH2_7 [GPDMA0_CH2] ================ */ -/* ================================================================================ */ - -/** - * @brief General Purpose DMA Unit 0 (GPDMA0_CH2_7) - */ - -typedef struct { /*!< (@ 0x500140B0) GPDMA0_CH2_7 Structure */ - __IO uint32_t SAR; /*!< (@ 0x500140B0) Source Address Register */ - __I uint32_t RESERVED; - __IO uint32_t DAR; /*!< (@ 0x500140B8) Destination Address Register */ - __I uint32_t RESERVED1[3]; - __IO uint32_t CTLL; /*!< (@ 0x500140C8) Control Register Low */ - __IO uint32_t CTLH; /*!< (@ 0x500140CC) Control Register High */ - __I uint32_t RESERVED2[8]; - __IO uint32_t CFGL; /*!< (@ 0x500140F0) Configuration Register Low */ - __IO uint32_t CFGH; /*!< (@ 0x500140F4) Configuration Register High */ -} GPDMA0_CH2_7_Type; - -/* ================================================================================ */ -/* ================ FCE ================ */ -/* ================================================================================ */ - -/** - * @brief Flexible CRC Engine (FCE) - */ - -typedef struct { /*!< (@ 0x50020000) FCE Structure */ - __IO uint32_t CLC; /*!< (@ 0x50020000) Clock Control Register */ - __I uint32_t RESERVED; - __I uint32_t ID; /*!< (@ 0x50020008) Module Identification Register */ -} FCE_GLOBAL_TypeDef; - -/* ================================================================================ */ -/* ================ FCE_KE [FCE_KE0] ================ */ -/* ================================================================================ */ - -/** - * @brief Flexible CRC Engine (FCE_KE) - */ - -typedef struct { /*!< (@ 0x50020020) FCE_KE Structure */ - __IO uint32_t IR; /*!< (@ 0x50020020) Input Register */ - __I uint32_t RES; /*!< (@ 0x50020024) CRC Result Register */ - __IO uint32_t CFG; /*!< (@ 0x50020028) CRC Configuration Register */ - __IO uint32_t STS; /*!< (@ 0x5002002C) CRC Status Register */ - __IO uint32_t LENGTH; /*!< (@ 0x50020030) CRC Length Register */ - __IO uint32_t CHECK; /*!< (@ 0x50020034) CRC Check Register */ - __IO uint32_t CRC; /*!< (@ 0x50020038) CRC Register */ - __IO uint32_t CTR; /*!< (@ 0x5002003C) CRC Test Register */ -} FCE_KE_TypeDef; - -/* ================================================================================ */ -/* ================ PBA [PBA0] ================ */ -/* ================================================================================ */ - -/** - * @brief Peripheral Bridge AHB 0 (PBA) - */ - -typedef struct { /*!< (@ 0x40000000) PBA Structure */ - __IO uint32_t STS; /*!< (@ 0x40000000) Peripheral Bridge Status Register */ - __I uint32_t WADDR; /*!< (@ 0x40000004) PBA Write Error Address Register */ -} PBA_GLOBAL_TypeDef; - -/* ================================================================================ */ -/* ================ FLASH [FLASH0] ================ */ -/* ================================================================================ */ - -/** - * @brief Flash Memory Controller (FLASH) - */ - -typedef struct { /*!< (@ 0x58001000) FLASH Structure */ - __I uint32_t RESERVED[1026]; - __I uint32_t ID; /*!< (@ 0x58002008) Flash Module Identification Register */ - __I uint32_t RESERVED1; - __I uint32_t FSR; /*!< (@ 0x58002010) Flash Status Register */ - __IO uint32_t FCON; /*!< (@ 0x58002014) Flash Configuration Register */ - __IO uint32_t MARP; /*!< (@ 0x58002018) Margin Control Register PFLASH */ - __I uint32_t RESERVED2; - __I uint32_t PROCON0; /*!< (@ 0x58002020) Flash Protection Configuration Register User - 0 */ - __I uint32_t PROCON1; /*!< (@ 0x58002024) Flash Protection Configuration Register User - 1 */ - __I uint32_t PROCON2; /*!< (@ 0x58002028) Flash Protection Configuration Register User - 2 */ -} FLASH0_GLOBAL_TypeDef; - -/* ================================================================================ */ -/* ================ PREF ================ */ -/* ================================================================================ */ - -/** - * @brief Prefetch Unit (PREF) - */ - -typedef struct { /*!< (@ 0x58004000) PREF Structure */ - __IO uint32_t PCON; /*!< (@ 0x58004000) Prefetch Configuration Register */ -} PREF_GLOBAL_TypeDef; - -/* ================================================================================ */ -/* ================ PMU [PMU0] ================ */ -/* ================================================================================ */ - -/** - * @brief Program Management Unit (PMU) - */ - -typedef struct { /*!< (@ 0x58000508) PMU Structure */ - __I uint32_t ID; /*!< (@ 0x58000508) PMU0 Identification Register */ -} PMU0_GLOBAL_TypeDef; - -/* ================================================================================ */ -/* ================ WDT ================ */ -/* ================================================================================ */ - -/** - * @brief Watch Dog Timer (WDT) - */ - -typedef struct { /*!< (@ 0x50008000) WDT Structure */ - __I uint32_t ID; /*!< (@ 0x50008000) WDT ID Register */ - __IO uint32_t CTR; /*!< (@ 0x50008004) WDT Control Register */ - __O uint32_t SRV; /*!< (@ 0x50008008) WDT Service Register */ - __I uint32_t TIM; /*!< (@ 0x5000800C) WDT Timer Register */ - __IO uint32_t WLB; /*!< (@ 0x50008010) WDT Window Lower Bound Register */ - __IO uint32_t WUB; /*!< (@ 0x50008014) WDT Window Upper Bound Register */ - __I uint32_t WDTSTS; /*!< (@ 0x50008018) WDT Status Register */ - __O uint32_t WDTCLR; /*!< (@ 0x5000801C) WDT Clear Register */ -} WDT_GLOBAL_TypeDef; - -/* ================================================================================ */ -/* ================ RTC ================ */ -/* ================================================================================ */ - -/** - * @brief Real Time Clock (RTC) - */ - -typedef struct { /*!< (@ 0x50004A00) RTC Structure */ - __I uint32_t ID; /*!< (@ 0x50004A00) RTC ID Register */ - __IO uint32_t CTR; /*!< (@ 0x50004A04) RTC Control Register */ - __I uint32_t RAWSTAT; /*!< (@ 0x50004A08) RTC Raw Service Request Register */ - __I uint32_t STSSR; /*!< (@ 0x50004A0C) RTC Service Request Status Register */ - __IO uint32_t MSKSR; /*!< (@ 0x50004A10) RTC Service Request Mask Register */ - __O uint32_t CLRSR; /*!< (@ 0x50004A14) RTC Clear Service Request Register */ - __IO uint32_t ATIM0; /*!< (@ 0x50004A18) RTC Alarm Time Register 0 */ - __IO uint32_t ATIM1; /*!< (@ 0x50004A1C) RTC Alarm Time Register 1 */ - __IO uint32_t TIM0; /*!< (@ 0x50004A20) RTC Time Register 0 */ - __IO uint32_t TIM1; /*!< (@ 0x50004A24) RTC Time Register 1 */ -} RTC_GLOBAL_TypeDef; - -/* ================================================================================ */ -/* ================ SCU_CLK ================ */ -/* ================================================================================ */ - -/** - * @brief System Control Unit (SCU_CLK) - */ - -typedef struct { /*!< (@ 0x50004600) SCU_CLK Structure */ - __I uint32_t CLKSTAT; /*!< (@ 0x50004600) Clock Status Register */ - __O uint32_t CLKSET; /*!< (@ 0x50004604) CLK Set Register */ - __O uint32_t CLKCLR; /*!< (@ 0x50004608) CLK Clear Register */ - __IO uint32_t SYSCLKCR; /*!< (@ 0x5000460C) System Clock Control Register */ - __IO uint32_t CPUCLKCR; /*!< (@ 0x50004610) CPU Clock Control Register */ - __IO uint32_t PBCLKCR; /*!< (@ 0x50004614) Peripheral Bus Clock Control Register */ - __IO uint32_t USBCLKCR; /*!< (@ 0x50004618) USB Clock Control Register */ - __I uint32_t RESERVED; - __IO uint32_t CCUCLKCR; /*!< (@ 0x50004620) CCU Clock Control Register */ - __IO uint32_t WDTCLKCR; /*!< (@ 0x50004624) WDT Clock Control Register */ - __IO uint32_t EXTCLKCR; /*!< (@ 0x50004628) External Clock Control */ - __IO uint32_t MLINKCLKCR; /*!< (@ 0x5000462C) Multi-Link Clock Control */ - __IO uint32_t SLEEPCR; /*!< (@ 0x50004630) Sleep Control Register */ - __IO uint32_t DSLEEPCR; /*!< (@ 0x50004634) Deep Sleep Control Register */ - __I uint32_t RESERVED1[2]; - __I uint32_t CGATSTAT0; /*!< (@ 0x50004640) Peripheral 0 Clock Gating Status */ - __O uint32_t CGATSET0; /*!< (@ 0x50004644) Peripheral 0 Clock Gating Set */ - __O uint32_t CGATCLR0; /*!< (@ 0x50004648) Peripheral 0 Clock Gating Clear */ - __I uint32_t CGATSTAT1; /*!< (@ 0x5000464C) Peripheral 1 Clock Gating Status */ - __O uint32_t CGATSET1; /*!< (@ 0x50004650) Peripheral 1 Clock Gating Set */ - __O uint32_t CGATCLR1; /*!< (@ 0x50004654) Peripheral 1 Clock Gating Clear */ - __I uint32_t CGATSTAT2; /*!< (@ 0x50004658) Peripheral 2 Clock Gating Status */ - __O uint32_t CGATSET2; /*!< (@ 0x5000465C) Peripheral 2 Clock Gating Set */ - __O uint32_t CGATCLR2; /*!< (@ 0x50004660) Peripheral 2 Clock Gating Clear */ -} SCU_CLK_TypeDef; - -/* ================================================================================ */ -/* ================ SCU_OSC ================ */ -/* ================================================================================ */ - -/** - * @brief System Control Unit (SCU_OSC) - */ - -typedef struct { /*!< (@ 0x50004700) SCU_OSC Structure */ - __I uint32_t OSCHPSTAT; /*!< (@ 0x50004700) OSC_HP Status Register */ - __IO uint32_t OSCHPCTRL; /*!< (@ 0x50004704) OSC_HP Control Register */ - __I uint32_t RESERVED; - __IO uint32_t CLKCALCONST; /*!< (@ 0x5000470C) Clock Calibration Constant Register */ -} SCU_OSC_TypeDef; - -/* ================================================================================ */ -/* ================ SCU_PLL ================ */ -/* ================================================================================ */ - -/** - * @brief System Control Unit (SCU_PLL) - */ - -typedef struct { /*!< (@ 0x50004710) SCU_PLL Structure */ - __I uint32_t PLLSTAT; /*!< (@ 0x50004710) PLL Status Register */ - __IO uint32_t PLLCON0; /*!< (@ 0x50004714) PLL Configuration 0 Register */ - __IO uint32_t PLLCON1; /*!< (@ 0x50004718) PLL Configuration 1 Register */ - __IO uint32_t PLLCON2; /*!< (@ 0x5000471C) PLL Configuration 2 Register */ - __I uint32_t USBPLLSTAT; /*!< (@ 0x50004720) USB PLL Status Register */ - __IO uint32_t USBPLLCON; /*!< (@ 0x50004724) USB PLL Configuration Register */ - __I uint32_t RESERVED[4]; - __I uint32_t CLKMXSTAT; /*!< (@ 0x50004738) Clock Multiplexing Status Register */ -} SCU_PLL_TypeDef; - -/* ================================================================================ */ -/* ================ SCU_GENERAL ================ */ -/* ================================================================================ */ - -/** - * @brief System Control Unit (SCU_GENERAL) - */ - -typedef struct { /*!< (@ 0x50004000) SCU_GENERAL Structure */ - __I uint32_t ID; /*!< (@ 0x50004000) SCU Module ID Register */ - __I uint32_t IDCHIP; /*!< (@ 0x50004004) Chip ID Register */ - __I uint32_t IDMANUF; /*!< (@ 0x50004008) Manufactory ID Register */ - __I uint32_t RESERVED; - __IO uint32_t STCON; /*!< (@ 0x50004010) Startup Configuration Register */ - __I uint32_t RESERVED1[6]; - __IO uint32_t GPR[2]; /*!< (@ 0x5000402C) General Purpose Register 0 */ - __I uint32_t RESERVED2[6]; - __IO uint32_t CCUCON; /*!< (@ 0x5000404C) CCU Control Register */ - __I uint32_t RESERVED3[15]; - __IO uint32_t DTSCON; /*!< (@ 0x5000408C) Die Temperature Sensor Control Register */ - __I uint32_t DTSSTAT; /*!< (@ 0x50004090) Die Temperature Sensor Status Register */ - __I uint32_t RESERVED4[3]; - __IO uint32_t GORCEN[2]; /*!< (@ 0x500040A0) Out of Range Comparator Enable Register 0 */ - __IO uint32_t DTEMPLIM; /*!< (@ 0x500040A8) Die Temperature Sensor Limit Register */ - __I uint32_t DTEMPALARM; /*!< (@ 0x500040AC) Die Temperature Sensor Alarm Register */ - __I uint32_t RESERVED5[5]; - __I uint32_t MIRRSTS; /*!< (@ 0x500040C4) Mirror Write Status Register */ - __IO uint32_t RMACR; /*!< (@ 0x500040C8) Retention Memory Access Control Register */ - __IO uint32_t RMDATA; /*!< (@ 0x500040CC) Retention Memory Access Data Register */ - __I uint32_t MIRRALLSTAT; /*!< (@ 0x500040D0) Mirror All Status */ - __O uint32_t MIRRALLREQ; /*!< (@ 0x500040D4) Mirror All Request */ -} SCU_GENERAL_TypeDef; - -/* ================================================================================ */ -/* ================ SCU_INTERRUPT ================ */ -/* ================================================================================ */ - -/** - * @brief System Control Unit (SCU_INTERRUPT) - */ - -typedef struct { /*!< (@ 0x50004074) SCU_INTERRUPT Structure */ - __I uint32_t SRSTAT; /*!< (@ 0x50004074) SCU Service Request Status */ - __I uint32_t SRRAW; /*!< (@ 0x50004078) SCU Raw Service Request Status */ - __IO uint32_t SRMSK; /*!< (@ 0x5000407C) SCU Service Request Mask */ - __O uint32_t SRCLR; /*!< (@ 0x50004080) SCU Service Request Clear */ - __O uint32_t SRSET; /*!< (@ 0x50004084) SCU Service Request Set */ - __IO uint32_t NMIREQEN; /*!< (@ 0x50004088) SCU Service Request Mask */ -} SCU_INTERRUPT_TypeDef; - -/* ================================================================================ */ -/* ================ SCU_PARITY ================ */ -/* ================================================================================ */ - -/** - * @brief System Control Unit (SCU_PARITY) - */ - -typedef struct { /*!< (@ 0x5000413C) SCU_PARITY Structure */ - __IO uint32_t PEEN; /*!< (@ 0x5000413C) Parity Error Enable Register */ - __IO uint32_t MCHKCON; /*!< (@ 0x50004140) Memory Checking Control Register */ - __IO uint32_t PETE; /*!< (@ 0x50004144) Parity Error Trap Enable Register */ - __IO uint32_t PERSTEN; /*!< (@ 0x50004148) Parity Error Reset Enable Register */ - __I uint32_t RESERVED; - __IO uint32_t PEFLAG; /*!< (@ 0x50004150) Parity Error Flag Register */ - __IO uint32_t PMTPR; /*!< (@ 0x50004154) Parity Memory Test Pattern Register */ - __IO uint32_t PMTSR; /*!< (@ 0x50004158) Parity Memory Test Select Register */ -} SCU_PARITY_TypeDef; - -/* ================================================================================ */ -/* ================ SCU_TRAP ================ */ -/* ================================================================================ */ - -/** - * @brief System Control Unit (SCU_TRAP) - */ - -typedef struct { /*!< (@ 0x50004160) SCU_TRAP Structure */ - __I uint32_t TRAPSTAT; /*!< (@ 0x50004160) Trap Status Register */ - __I uint32_t TRAPRAW; /*!< (@ 0x50004164) Trap Raw Status Register */ - __IO uint32_t TRAPDIS; /*!< (@ 0x50004168) Trap Disable Register */ - __O uint32_t TRAPCLR; /*!< (@ 0x5000416C) Trap Clear Register */ - __O uint32_t TRAPSET; /*!< (@ 0x50004170) Trap Set Register */ -} SCU_TRAP_TypeDef; - -/* ================================================================================ */ -/* ================ SCU_HIBERNATE ================ */ -/* ================================================================================ */ - -/** - * @brief System Control Unit (SCU_HIBERNATE) - */ - -typedef struct { /*!< (@ 0x50004300) SCU_HIBERNATE Structure */ - __I uint32_t HDSTAT; /*!< (@ 0x50004300) Hibernate Domain Status Register */ - __O uint32_t HDCLR; /*!< (@ 0x50004304) Hibernate Domain Status Clear Register */ - __O uint32_t HDSET; /*!< (@ 0x50004308) Hibernate Domain Status Set Register */ - __IO uint32_t HDCR; /*!< (@ 0x5000430C) Hibernate Domain Control Register */ - __I uint32_t RESERVED; - __IO uint32_t OSCSICTRL; /*!< (@ 0x50004314) fOSI Control Register */ - __I uint32_t OSCULSTAT; /*!< (@ 0x50004318) OSC_ULP Status Register */ - __IO uint32_t OSCULCTRL; /*!< (@ 0x5000431C) OSC_ULP Control Register */ - __IO uint32_t LPACCONF; /*!< (@ 0x50004320) Analog Wake-up Configuration Register */ - __IO uint32_t LPACTH0; /*!< (@ 0x50004324) LPAC Threshold Register 0 */ - __IO uint32_t LPACTH1; /*!< (@ 0x50004328) LPAC Threshold Register 1 */ - __I uint32_t LPACST; /*!< (@ 0x5000432C) Hibernate Analog Control State Register */ - __O uint32_t LPACCLR; /*!< (@ 0x50004330) LPAC Control Clear Register */ - __O uint32_t LPACSET; /*!< (@ 0x50004334) LPAC Control Set Register */ - __I uint32_t HINTST; /*!< (@ 0x50004338) Hibernate Internal Control State Register */ - __O uint32_t HINTCLR; /*!< (@ 0x5000433C) Hibernate Internal Control Clear Register */ - __O uint32_t HINTSET; /*!< (@ 0x50004340) Hibernate Internal Control Set Register */ -} SCU_HIBERNATE_TypeDef; - -/* ================================================================================ */ -/* ================ SCU_POWER ================ */ -/* ================================================================================ */ - -/** - * @brief System Control Unit (SCU_POWER) - */ - -typedef struct { /*!< (@ 0x50004200) SCU_POWER Structure */ - __I uint32_t PWRSTAT; /*!< (@ 0x50004200) PCU Status Register */ - __O uint32_t PWRSET; /*!< (@ 0x50004204) PCU Set Control Register */ - __O uint32_t PWRCLR; /*!< (@ 0x50004208) PCU Clear Control Register */ - __I uint32_t RESERVED; - __I uint32_t EVRSTAT; /*!< (@ 0x50004210) EVR Status Register */ - __I uint32_t EVRVADCSTAT; /*!< (@ 0x50004214) EVR VADC Status Register */ - __I uint32_t RESERVED1[5]; - __IO uint32_t PWRMON; /*!< (@ 0x5000422C) Power Monitor Control */ -} SCU_POWER_TypeDef; - -/* ================================================================================ */ -/* ================ SCU_RESET ================ */ -/* ================================================================================ */ - -/** - * @brief System Control Unit (SCU_RESET) - */ - -typedef struct { /*!< (@ 0x50004400) SCU_RESET Structure */ - __I uint32_t RSTSTAT; /*!< (@ 0x50004400) RCU Reset Status */ - __O uint32_t RSTSET; /*!< (@ 0x50004404) RCU Reset Set Register */ - __O uint32_t RSTCLR; /*!< (@ 0x50004408) RCU Reset Clear Register */ - __I uint32_t PRSTAT0; /*!< (@ 0x5000440C) RCU Peripheral 0 Reset Status */ - __O uint32_t PRSET0; /*!< (@ 0x50004410) RCU Peripheral 0 Reset Set */ - __O uint32_t PRCLR0; /*!< (@ 0x50004414) RCU Peripheral 0 Reset Clear */ - __I uint32_t PRSTAT1; /*!< (@ 0x50004418) RCU Peripheral 1 Reset Status */ - __O uint32_t PRSET1; /*!< (@ 0x5000441C) RCU Peripheral 1 Reset Set */ - __O uint32_t PRCLR1; /*!< (@ 0x50004420) RCU Peripheral 1 Reset Clear */ - __I uint32_t PRSTAT2; /*!< (@ 0x50004424) RCU Peripheral 2 Reset Status */ - __O uint32_t PRSET2; /*!< (@ 0x50004428) RCU Peripheral 2 Reset Set */ - __O uint32_t PRCLR2; /*!< (@ 0x5000442C) RCU Peripheral 2 Reset Clear */ -} SCU_RESET_TypeDef; - -/* ================================================================================ */ -/* ================ LEDTS [LEDTS0] ================ */ -/* ================================================================================ */ - -/** - * @brief LED and Touch Sense Unit 0 (LEDTS) - */ - -typedef struct { /*!< (@ 0x48010000) LEDTS Structure */ - __I uint32_t ID; /*!< (@ 0x48010000) Module Identification Register */ - __IO uint32_t GLOBCTL; /*!< (@ 0x48010004) Global Control Register */ - __IO uint32_t FNCTL; /*!< (@ 0x48010008) Function Control Register */ - __O uint32_t EVFR; /*!< (@ 0x4801000C) Event Flag Register */ - __IO uint32_t TSVAL; /*!< (@ 0x48010010) Touch-sense TS-Counter Value */ - __IO uint32_t LINE0; /*!< (@ 0x48010014) Line Pattern Register 0 */ - __IO uint32_t LINE1; /*!< (@ 0x48010018) Line Pattern Register 1 */ - __IO uint32_t LDCMP0; /*!< (@ 0x4801001C) LED Compare Register 0 */ - __IO uint32_t LDCMP1; /*!< (@ 0x48010020) LED Compare Register 1 */ - __IO uint32_t TSCMP0; /*!< (@ 0x48010024) Touch-sense Compare Register 0 */ - __IO uint32_t TSCMP1; /*!< (@ 0x48010028) Touch-sense Compare Register 1 */ -} LEDTS0_GLOBAL_TypeDef; - -/* ================================================================================ */ -/* ================ USB [USB0] ================ */ -/* ================================================================================ */ - -/** - * @brief Universal Serial Bus (USB) - */ - -typedef struct { /*!< (@ 0x50040000) USB Structure */ - __I uint32_t RESERVED[2]; - __IO uint32_t GAHBCFG; /*!< (@ 0x50040008) AHB Configuration Register */ - __IO uint32_t GUSBCFG; /*!< (@ 0x5004000C) USB Configuration Register */ - __IO uint32_t GRSTCTL; /*!< (@ 0x50040010) Reset Register */ - __IO uint32_t GINTSTS; /*!< (@ 0x50040014) Interrupt Register */ - __IO uint32_t GINTMSK; /*!< (@ 0x50040018) Interrupt Mask Register */ - __I uint32_t GRXSTSR; /*!< (@ 0x5004001C) Receive Status Debug Read Register */ - __I uint32_t GRXSTSP; /*!< (@ 0x50040020) Receive Status Read and Pop Register */ - __IO uint32_t GRXFSIZ; /*!< (@ 0x50040024) Receive FIFO Size Register */ - __IO uint32_t GNPTXFSIZ; /*!< (@ 0x50040028) Non-Periodic Transmit FIFO Size Register */ - __I uint32_t RESERVED1[4]; - __IO uint32_t GUID; /*!< (@ 0x5004003C) USB Module Identification Register */ - __I uint32_t RESERVED2[7]; - __IO uint32_t GDFIFOCFG; /*!< (@ 0x5004005C) Global DFIFO Software Config Register */ - __I uint32_t RESERVED3[41]; - __IO uint32_t DIEPTXF1; /*!< (@ 0x50040104) Device IN Endpoint 1 Transmit FIFO Size Register */ - __IO uint32_t DIEPTXF2; /*!< (@ 0x50040108) Device IN Endpoint 2 Transmit FIFO Size Register */ - __IO uint32_t DIEPTXF3; /*!< (@ 0x5004010C) Device IN Endpoint 3 Transmit FIFO Size Register */ - __IO uint32_t DIEPTXF4; /*!< (@ 0x50040110) Device IN Endpoint 4 Transmit FIFO Size Register */ - __IO uint32_t DIEPTXF5; /*!< (@ 0x50040114) Device IN Endpoint 5 Transmit FIFO Size Register */ - __IO uint32_t DIEPTXF6; /*!< (@ 0x50040118) Device IN Endpoint 6 Transmit FIFO Size Register */ - __I uint32_t RESERVED4[441]; - __IO uint32_t DCFG; /*!< (@ 0x50040800) Device Configuration Register */ - __IO uint32_t DCTL; /*!< (@ 0x50040804) Device Control Register */ - __I uint32_t DSTS; /*!< (@ 0x50040808) Device Status Register */ - __I uint32_t RESERVED5; - __IO uint32_t DIEPMSK; /*!< (@ 0x50040810) Device IN Endpoint Common Interrupt Mask Register */ - __IO uint32_t DOEPMSK; /*!< (@ 0x50040814) Device OUT Endpoint Common Interrupt Mask Register */ - __I uint32_t DAINT; /*!< (@ 0x50040818) Device All Endpoints Interrupt Register */ - __IO uint32_t DAINTMSK; /*!< (@ 0x5004081C) Device All Endpoints Interrupt Mask Register */ - __I uint32_t RESERVED6[2]; - __IO uint32_t DVBUSDIS; /*!< (@ 0x50040828) Device VBUS Discharge Time Register */ - __IO uint32_t DVBUSPULSE; /*!< (@ 0x5004082C) Device VBUS Pulsing Time Register */ - __I uint32_t RESERVED7; - __IO uint32_t DIEPEMPMSK; /*!< (@ 0x50040834) Device IN Endpoint FIFO Empty Interrupt Mask - Register */ - __I uint32_t RESERVED8[370]; - __IO uint32_t PCGCCTL; /*!< (@ 0x50040E00) Power and Clock Gating Control Register */ -} USB0_GLOBAL_TypeDef; - -/* ================================================================================ */ -/* ================ USB0_EP0 ================ */ -/* ================================================================================ */ - -/** - * @brief Universal Serial Bus (USB0_EP0) - */ - -typedef struct { /*!< (@ 0x50040900) USB0_EP0 Structure */ - __IO uint32_t DIEPCTL0; /*!< (@ 0x50040900) Device Control IN Endpoint Control Register */ - __I uint32_t RESERVED; - __IO uint32_t DIEPINT0; /*!< (@ 0x50040908) Device Endpoint Interrupt Register */ - __I uint32_t RESERVED1; - __IO uint32_t DIEPTSIZ0; /*!< (@ 0x50040910) Device IN Endpoint Transfer Size Register */ - __IO uint32_t DIEPDMA0; /*!< (@ 0x50040914) Device Endpoint DMA Address Register */ - __I uint32_t DTXFSTS0; /*!< (@ 0x50040918) Device IN Endpoint Transmit FIFO Status Register */ - __I uint32_t DIEPDMAB0; /*!< (@ 0x5004091C) Device Endpoint DMA Buffer Address Register */ - __I uint32_t RESERVED2[120]; - __IO uint32_t DOEPCTL0; /*!< (@ 0x50040B00) Device Control OUT Endpoint Control Register */ - __I uint32_t RESERVED3; - __IO uint32_t DOEPINT0; /*!< (@ 0x50040B08) Device Endpoint Interrupt Register */ - __I uint32_t RESERVED4; - __IO uint32_t DOEPTSIZ0; /*!< (@ 0x50040B10) Device OUT Endpoint Transfer Size Register */ - __IO uint32_t DOEPDMA0; /*!< (@ 0x50040B14) Device Endpoint DMA Address Register */ - __I uint32_t RESERVED5; - __I uint32_t DOEPDMAB0; /*!< (@ 0x50040B1C) Device Endpoint DMA Buffer Address Register */ -} USB0_EP0_TypeDef; - -/* ================================================================================ */ -/* ================ USB_EP [USB0_EP1] ================ */ -/* ================================================================================ */ - -/** - * @brief Universal Serial Bus (USB_EP) - */ - -typedef struct { /*!< (@ 0x50040920) USB_EP Structure */ - - union { - __IO uint32_t - DIEPCTL_INTBULK; /*!< (@ 0x50040920) Device Endpoint Control Register [INTBULK] */ - __IO uint32_t - DIEPCTL_ISOCONT; /*!< (@ 0x50040920) Device Endpoint Control Register [ISOCONT] */ - }; - - __I uint32_t RESERVED; - __IO uint32_t DIEPINT; /*!< (@ 0x50040928) Device Endpoint Interrupt Register */ - __I uint32_t RESERVED1; - __IO uint32_t DIEPTSIZ; /*!< (@ 0x50040930) Device Endpoint Transfer Size Register */ - __IO uint32_t DIEPDMA; /*!< (@ 0x50040934) Device Endpoint DMA Address Register */ - __I uint32_t DTXFSTS; /*!< (@ 0x50040938) Device IN Endpoint Transmit FIFO Status Register */ - __I uint32_t DIEPDMAB; /*!< (@ 0x5004093C) Device Endpoint DMA Buffer Address Register */ - __I uint32_t RESERVED2[120]; - - union { - __IO uint32_t - DOEPCTL_INTBULK; /*!< (@ 0x50040B20) Device Endpoint Control Register [INTBULK] */ - __IO uint32_t - DOEPCTL_ISOCONT; /*!< (@ 0x50040B20) Device Endpoint Control Register [ISOCONT] */ - }; - - __I uint32_t RESERVED3; - __IO uint32_t DOEPINT; /*!< (@ 0x50040B28) Device Endpoint Interrupt Register */ - __I uint32_t RESERVED4; - - union { - __IO uint32_t - DOEPTSIZ_CONTROL; /*!< (@ 0x50040B30) Device Endpoint Transfer Size Register [CONT] */ - __IO uint32_t - DOEPTSIZ_ISO; /*!< (@ 0x50040B30) Device Endpoint Transfer Size Register [ISO] */ - }; - - __IO uint32_t DOEPDMA; /*!< (@ 0x50040B34) Device Endpoint DMA Address Register */ - __I uint32_t RESERVED5; - __I uint32_t DOEPDMAB; /*!< (@ 0x50040B3C) Device Endpoint DMA Buffer Address Register */ -} USB0_EP_TypeDef; - -/* ================================================================================ */ -/* ================ USIC [USIC0] ================ */ -/* ================================================================================ */ - -/** - * @brief Universal Serial Interface Controller 0 (USIC) - */ - -typedef struct { /*!< (@ 0x40030008) USIC Structure */ - __I uint32_t ID; /*!< (@ 0x40030008) Module Identification Register */ -} USIC_GLOBAL_TypeDef; - -/* ================================================================================ */ -/* ================ USIC_CH [USIC0_CH0] ================ */ -/* ================================================================================ */ - -/** - * @brief Universal Serial Interface Controller 0 (USIC_CH) - */ - -typedef struct { /*!< (@ 0x40030000) USIC_CH Structure */ - __I uint32_t RESERVED; - __I uint32_t CCFG; /*!< (@ 0x40030004) Channel Configuration Register */ - __I uint32_t RESERVED1; - __IO uint32_t KSCFG; /*!< (@ 0x4003000C) Kernel State Configuration Register */ - __IO uint32_t FDR; /*!< (@ 0x40030010) Fractional Divider Register */ - __IO uint32_t BRG; /*!< (@ 0x40030014) Baud Rate Generator Register */ - __IO uint32_t INPR; /*!< (@ 0x40030018) Interrupt Node Pointer Register */ - __IO uint32_t DX0CR; /*!< (@ 0x4003001C) Input Control Register 0 */ - __IO uint32_t DX1CR; /*!< (@ 0x40030020) Input Control Register 1 */ - __IO uint32_t DX2CR; /*!< (@ 0x40030024) Input Control Register 2 */ - __IO uint32_t DX3CR; /*!< (@ 0x40030028) Input Control Register 3 */ - __IO uint32_t DX4CR; /*!< (@ 0x4003002C) Input Control Register 4 */ - __IO uint32_t DX5CR; /*!< (@ 0x40030030) Input Control Register 5 */ - __IO uint32_t SCTR; /*!< (@ 0x40030034) Shift Control Register */ - __IO uint32_t TCSR; /*!< (@ 0x40030038) Transmit Control/Status Register */ - - union { - __IO uint32_t PCR_IICMode; /*!< (@ 0x4003003C) Protocol Control Register [IIC Mode] */ - __IO uint32_t PCR_IISMode; /*!< (@ 0x4003003C) Protocol Control Register [IIS Mode] */ - __IO uint32_t PCR_SSCMode; /*!< (@ 0x4003003C) Protocol Control Register [SSC Mode] */ - __IO uint32_t PCR; /*!< (@ 0x4003003C) Protocol Control Register */ - __IO uint32_t PCR_ASCMode; /*!< (@ 0x4003003C) Protocol Control Register [ASC Mode] */ - }; - - __IO uint32_t CCR; /*!< (@ 0x40030040) Channel Control Register */ - __IO uint32_t CMTR; /*!< (@ 0x40030044) Capture Mode Timer Register */ - - union { - __IO uint32_t PSR_IICMode; /*!< (@ 0x40030048) Protocol Status Register [IIC Mode] */ - __IO uint32_t PSR_IISMode; /*!< (@ 0x40030048) Protocol Status Register [IIS Mode] */ - __IO uint32_t PSR_SSCMode; /*!< (@ 0x40030048) Protocol Status Register [SSC Mode] */ - __IO uint32_t PSR; /*!< (@ 0x40030048) Protocol Status Register */ - __IO uint32_t PSR_ASCMode; /*!< (@ 0x40030048) Protocol Status Register [ASC Mode] */ - }; - - __O uint32_t PSCR; /*!< (@ 0x4003004C) Protocol Status Clear Register */ - __I uint32_t RBUFSR; /*!< (@ 0x40030050) Receiver Buffer Status Register */ - __I uint32_t RBUF; /*!< (@ 0x40030054) Receiver Buffer Register */ - __I uint32_t RBUFD; /*!< (@ 0x40030058) Receiver Buffer Register for Debugger */ - __I uint32_t RBUF0; /*!< (@ 0x4003005C) Receiver Buffer Register 0 */ - __I uint32_t RBUF1; /*!< (@ 0x40030060) Receiver Buffer Register 1 */ - __I uint32_t RBUF01SR; /*!< (@ 0x40030064) Receiver Buffer 01 Status Register */ - __O uint32_t FMR; /*!< (@ 0x40030068) Flag Modification Register */ - __I uint32_t RESERVED2[5]; - __IO uint32_t TBUF[32]; /*!< (@ 0x40030080) Transmit Buffer */ - __IO uint32_t BYP; /*!< (@ 0x40030100) Bypass Data Register */ - __IO uint32_t BYPCR; /*!< (@ 0x40030104) Bypass Control Register */ - __IO uint32_t TBCTR; /*!< (@ 0x40030108) Transmitter Buffer Control Register */ - __IO uint32_t RBCTR; /*!< (@ 0x4003010C) Receiver Buffer Control Register */ - __I uint32_t TRBPTR; /*!< (@ 0x40030110) Transmit/Receive Buffer Pointer Register */ - __IO uint32_t TRBSR; /*!< (@ 0x40030114) Transmit/Receive Buffer Status Register */ - __O uint32_t TRBSCR; /*!< (@ 0x40030118) Transmit/Receive Buffer Status Clear Register */ - __I uint32_t OUTR; /*!< (@ 0x4003011C) Receiver Buffer Output Register */ - __I uint32_t OUTDR; /*!< (@ 0x40030120) Receiver Buffer Output Register L for Debugger */ - __I uint32_t RESERVED3[23]; - __O uint32_t IN[32]; /*!< (@ 0x40030180) Transmit FIFO Buffer */ -} USIC_CH_TypeDef; - -/* ================================================================================ */ -/* ================ CAN ================ */ -/* ================================================================================ */ - -/** - * @brief Controller Area Networks (CAN) - */ - -typedef struct { /*!< (@ 0x48014000) CAN Structure */ - __IO uint32_t CLC; /*!< (@ 0x48014000) CAN Clock Control Register */ - __I uint32_t RESERVED; - __I uint32_t ID; /*!< (@ 0x48014008) Module Identification Register */ - __IO uint32_t FDR; /*!< (@ 0x4801400C) CAN Fractional Divider Register */ - __I uint32_t RESERVED1[60]; - __I uint32_t LIST[8]; /*!< (@ 0x48014100) List Register */ - __I uint32_t RESERVED2[8]; - __IO uint32_t MSPND[8]; /*!< (@ 0x48014140) Message Pending Register */ - __I uint32_t RESERVED3[8]; - __I uint32_t MSID[8]; /*!< (@ 0x48014180) Message Index Register */ - __I uint32_t RESERVED4[8]; - __IO uint32_t MSIMASK; /*!< (@ 0x480141C0) Message Index Mask Register */ - __IO uint32_t PANCTR; /*!< (@ 0x480141C4) Panel Control Register */ - __IO uint32_t MCR; /*!< (@ 0x480141C8) Module Control Register */ - __O uint32_t MITR; /*!< (@ 0x480141CC) Module Interrupt Trigger Register */ -} CAN_GLOBAL_TypeDef; - -/* ================================================================================ */ -/* ================ CAN_NODE [CAN_NODE0] ================ */ -/* ================================================================================ */ - -/** - * @brief Controller Area Networks (CAN_NODE) - */ - -typedef struct { /*!< (@ 0x48014200) CAN_NODE Structure */ - __IO uint32_t NCR; /*!< (@ 0x48014200) Node Control Register */ - __IO uint32_t NSR; /*!< (@ 0x48014204) Node Status Register */ - __IO uint32_t NIPR; /*!< (@ 0x48014208) Node Interrupt Pointer Register */ - __IO uint32_t NPCR; /*!< (@ 0x4801420C) Node Port Control Register */ - __IO uint32_t NBTR; /*!< (@ 0x48014210) Node Bit Timing Register */ - __IO uint32_t NECNT; /*!< (@ 0x48014214) Node Error Counter Register */ - __IO uint32_t NFCR; /*!< (@ 0x48014218) Node Frame Counter Register */ -} CAN_NODE_TypeDef; - -/* ================================================================================ */ -/* ================ CAN_MO [CAN_MO0] ================ */ -/* ================================================================================ */ - -/** - * @brief Controller Area Networks (CAN_MO) - */ - -typedef struct { /*!< (@ 0x48015000) CAN_MO Structure */ - __IO uint32_t MOFCR; /*!< (@ 0x48015000) Message Object Function Control Register */ - __IO uint32_t MOFGPR; /*!< (@ 0x48015004) Message Object FIFO/Gateway Pointer Register */ - __IO uint32_t MOIPR; /*!< (@ 0x48015008) Message Object Interrupt Pointer Register */ - __IO uint32_t MOAMR; /*!< (@ 0x4801500C) Message Object Acceptance Mask Register */ - __IO uint32_t MODATAL; /*!< (@ 0x48015010) Message Object Data Register Low */ - __IO uint32_t MODATAH; /*!< (@ 0x48015014) Message Object Data Register High */ - __IO uint32_t MOAR; /*!< (@ 0x48015018) Message Object Arbitration Register */ - - union { - __I uint32_t MOSTAT; /*!< (@ 0x4801501C) Message Object Status Register */ - __O uint32_t MOCTR; /*!< (@ 0x4801501C) Message Object Control Register */ - }; -} CAN_MO_TypeDef; - -/* ================================================================================ */ -/* ================ VADC ================ */ -/* ================================================================================ */ - -/** - * @brief Analog to Digital Converter (VADC) - */ - -typedef struct { /*!< (@ 0x40004000) VADC Structure */ - __IO uint32_t CLC; /*!< (@ 0x40004000) Clock Control Register */ - __I uint32_t RESERVED; - __I uint32_t ID; /*!< (@ 0x40004008) Module Identification Register */ - __I uint32_t RESERVED1[7]; - __IO uint32_t OCS; /*!< (@ 0x40004028) OCDS Control and Status Register */ - __I uint32_t RESERVED2[21]; - __IO uint32_t GLOBCFG; /*!< (@ 0x40004080) Global Configuration Register */ - __I uint32_t RESERVED3[7]; - __IO uint32_t GLOBICLASS[2]; /*!< (@ 0x400040A0) Input Class Register, Global */ - __I uint32_t RESERVED4[4]; - __IO uint32_t GLOBBOUND; /*!< (@ 0x400040B8) Global Boundary Select Register */ - __I uint32_t RESERVED5[9]; - __IO uint32_t GLOBEFLAG; /*!< (@ 0x400040E0) Global Event Flag Register */ - __I uint32_t RESERVED6[23]; - __IO uint32_t GLOBEVNP; /*!< (@ 0x40004140) Global Event Node Pointer Register */ - __I uint32_t RESERVED7[7]; - __IO uint32_t GLOBTF; /*!< (@ 0x40004160) Global Test Functions Register */ - __I uint32_t RESERVED8[7]; - __IO uint32_t - BRSSEL[4]; /*!< (@ 0x40004180) Background Request Source Channel Select Register */ - __I uint32_t RESERVED9[12]; - __IO uint32_t BRSPND[4]; /*!< (@ 0x400041C0) Background Request Source Pending Register */ - __I uint32_t RESERVED10[12]; - __IO uint32_t BRSCTRL; /*!< (@ 0x40004200) Background Request Source Control Register */ - __IO uint32_t BRSMR; /*!< (@ 0x40004204) Background Request Source Mode Register */ - __I uint32_t RESERVED11[30]; - __IO uint32_t GLOBRCR; /*!< (@ 0x40004280) Global Result Control Register */ - __I uint32_t RESERVED12[31]; - __IO uint32_t GLOBRES; /*!< (@ 0x40004300) Global Result Register */ - __I uint32_t RESERVED13[31]; - __IO uint32_t GLOBRESD; /*!< (@ 0x40004380) Global Result Register, Debug */ - __I uint32_t RESERVED14[27]; - __IO uint32_t EMUXSEL; /*!< (@ 0x400043F0) External Multiplexer Select Register */ -} VADC_GLOBAL_TypeDef; - -/* ================================================================================ */ -/* ================ VADC_G [VADC_G0] ================ */ -/* ================================================================================ */ - -/** - * @brief Analog to Digital Converter (VADC_G) - */ - -typedef struct { /*!< (@ 0x40004400) VADC_G Structure */ - __I uint32_t RESERVED[32]; - __IO uint32_t ARBCFG; /*!< (@ 0x40004480) Arbitration Configuration Register */ - __IO uint32_t ARBPR; /*!< (@ 0x40004484) Arbitration Priority Register */ - __IO uint32_t CHASS; /*!< (@ 0x40004488) Channel Assignment Register */ - __I uint32_t RESERVED1[5]; - __IO uint32_t ICLASS[2]; /*!< (@ 0x400044A0) Input Class Register */ - __I uint32_t RESERVED2[2]; - __IO uint32_t ALIAS; /*!< (@ 0x400044B0) Alias Register */ - __I uint32_t RESERVED3; - __IO uint32_t BOUND; /*!< (@ 0x400044B8) Boundary Select Register */ - __I uint32_t RESERVED4; - __IO uint32_t SYNCTR; /*!< (@ 0x400044C0) Synchronization Control Register */ - __I uint32_t RESERVED5; - __IO uint32_t BFL; /*!< (@ 0x400044C8) Boundary Flag Register */ - __O uint32_t BFLS; /*!< (@ 0x400044CC) Boundary Flag Software Register */ - __IO uint32_t BFLC; /*!< (@ 0x400044D0) Boundary Flag Control Register */ - __IO uint32_t BFLNP; /*!< (@ 0x400044D4) Boundary Flag Node Pointer Register */ - __I uint32_t RESERVED6[10]; - __IO uint32_t QCTRL0; /*!< (@ 0x40004500) Queue 0 Source Control Register */ - __IO uint32_t QMR0; /*!< (@ 0x40004504) Queue 0 Mode Register */ - __I uint32_t QSR0; /*!< (@ 0x40004508) Queue 0 Status Register */ - __I uint32_t Q0R0; /*!< (@ 0x4000450C) Queue 0 Register 0 */ - - union { - __I uint32_t QBUR0; /*!< (@ 0x40004510) Queue 0 Backup Register */ - __O uint32_t QINR0; /*!< (@ 0x40004510) Queue 0 Input Register */ - }; - - __I uint32_t RESERVED7[3]; - __IO uint32_t ASCTRL; /*!< (@ 0x40004520) Autoscan Source Control Register */ - __IO uint32_t ASMR; /*!< (@ 0x40004524) Autoscan Source Mode Register */ - __IO uint32_t ASSEL; /*!< (@ 0x40004528) Autoscan Source Channel Select Register */ - __IO uint32_t ASPND; /*!< (@ 0x4000452C) Autoscan Source Pending Register */ - __I uint32_t RESERVED8[20]; - __IO uint32_t CEFLAG; /*!< (@ 0x40004580) Channel Event Flag Register */ - __IO uint32_t REFLAG; /*!< (@ 0x40004584) Result Event Flag Register */ - __IO uint32_t SEFLAG; /*!< (@ 0x40004588) Source Event Flag Register */ - __I uint32_t RESERVED9; - __O uint32_t CEFCLR; /*!< (@ 0x40004590) Channel Event Flag Clear Register */ - __O uint32_t REFCLR; /*!< (@ 0x40004594) Result Event Flag Clear Register */ - __O uint32_t SEFCLR; /*!< (@ 0x40004598) Source Event Flag Clear Register */ - __I uint32_t RESERVED10; - __IO uint32_t CEVNP0; /*!< (@ 0x400045A0) Channel Event Node Pointer Register 0 */ - __I uint32_t RESERVED11[3]; - __IO uint32_t REVNP0; /*!< (@ 0x400045B0) Result Event Node Pointer Register 0 */ - __IO uint32_t REVNP1; /*!< (@ 0x400045B4) Result Event Node Pointer Register 1 */ - __I uint32_t RESERVED12[2]; - __IO uint32_t SEVNP; /*!< (@ 0x400045C0) Source Event Node Pointer Register */ - __I uint32_t RESERVED13; - __O uint32_t SRACT; /*!< (@ 0x400045C8) Service Request Software Activation Trigger */ - __I uint32_t RESERVED14[9]; - __IO uint32_t EMUXCTR; /*!< (@ 0x400045F0) External Multiplexer Control Register */ - __I uint32_t RESERVED15; - __IO uint32_t VFR; /*!< (@ 0x400045F8) Valid Flag Register */ - __I uint32_t RESERVED16; - __IO uint32_t CHCTR[8]; /*!< (@ 0x40004600) Channel Ctrl. Reg. */ - __I uint32_t RESERVED17[24]; - __IO uint32_t RCR[16]; /*!< (@ 0x40004680) Result Control Register */ - __I uint32_t RESERVED18[16]; - __IO uint32_t RES[16]; /*!< (@ 0x40004700) Result Register */ - __I uint32_t RESERVED19[16]; - __I uint32_t RESD[16]; /*!< (@ 0x40004780) Result Register, Debug */ -} VADC_G_TypeDef; - -/* ================================================================================ */ -/* ================ DAC ================ */ -/* ================================================================================ */ - -/** - * @brief Digital to Analog Converter (DAC) - */ - -typedef struct { /*!< (@ 0x48018000) DAC Structure */ - __I uint32_t ID; /*!< (@ 0x48018000) Module Identification Register */ - __IO uint32_t DAC0CFG0; /*!< (@ 0x48018004) DAC0 Configuration Register 0 */ - __IO uint32_t DAC0CFG1; /*!< (@ 0x48018008) DAC0 Configuration Register 1 */ - __IO uint32_t DAC1CFG0; /*!< (@ 0x4801800C) DAC1 Configuration Register 0 */ - __IO uint32_t DAC1CFG1; /*!< (@ 0x48018010) DAC1 Configuration Register 1 */ - __IO uint32_t DAC0DATA; /*!< (@ 0x48018014) DAC0 Data Register */ - __IO uint32_t DAC1DATA; /*!< (@ 0x48018018) DAC1 Data Register */ - __IO uint32_t DAC01DATA; /*!< (@ 0x4801801C) DAC01 Data Register */ - __IO uint32_t DAC0PATL; /*!< (@ 0x48018020) DAC0 Lower Pattern Register */ - __IO uint32_t DAC0PATH; /*!< (@ 0x48018024) DAC0 Higher Pattern Register */ - __IO uint32_t DAC1PATL; /*!< (@ 0x48018028) DAC1 Lower Pattern Register */ - __IO uint32_t DAC1PATH; /*!< (@ 0x4801802C) DAC1 Higher Pattern Register */ -} DAC_GLOBAL_TypeDef; - -/* ================================================================================ */ -/* ================ CCU4 [CCU40] ================ */ -/* ================================================================================ */ - -/** - * @brief Capture Compare Unit 4 - Unit 0 (CCU4) - */ - -typedef struct { /*!< (@ 0x4000C000) CCU4 Structure */ - __IO uint32_t GCTRL; /*!< (@ 0x4000C000) Global Control Register */ - __I uint32_t GSTAT; /*!< (@ 0x4000C004) Global Status Register */ - __O uint32_t GIDLS; /*!< (@ 0x4000C008) Global Idle Set */ - __O uint32_t GIDLC; /*!< (@ 0x4000C00C) Global Idle Clear */ - __O uint32_t GCSS; /*!< (@ 0x4000C010) Global Channel Set */ - __O uint32_t GCSC; /*!< (@ 0x4000C014) Global Channel Clear */ - __I uint32_t GCST; /*!< (@ 0x4000C018) Global Channel Status */ - __I uint32_t RESERVED[13]; - __I uint32_t ECRD; /*!< (@ 0x4000C050) Extended Capture Mode Read */ - __I uint32_t RESERVED1[11]; - __I uint32_t MIDR; /*!< (@ 0x4000C080) Module Identification */ -} CCU4_GLOBAL_TypeDef; - -/* ================================================================================ */ -/* ================ CCU4_CC4 [CCU40_CC40] ================ */ -/* ================================================================================ */ - -/** - * @brief Capture Compare Unit 4 - Unit 0 (CCU4_CC4) - */ - -typedef struct { /*!< (@ 0x4000C100) CCU4_CC4 Structure */ - __IO uint32_t INS; /*!< (@ 0x4000C100) Input Selector Configuration */ - __IO uint32_t CMC; /*!< (@ 0x4000C104) Connection Matrix Control */ - __I uint32_t TCST; /*!< (@ 0x4000C108) Slice Timer Status */ - __O uint32_t TCSET; /*!< (@ 0x4000C10C) Slice Timer Run Set */ - __O uint32_t TCCLR; /*!< (@ 0x4000C110) Slice Timer Clear */ - __IO uint32_t TC; /*!< (@ 0x4000C114) Slice Timer Control */ - __IO uint32_t PSL; /*!< (@ 0x4000C118) Passive Level Config */ - __I uint32_t DIT; /*!< (@ 0x4000C11C) Dither Config */ - __IO uint32_t DITS; /*!< (@ 0x4000C120) Dither Shadow Register */ - __IO uint32_t PSC; /*!< (@ 0x4000C124) Prescaler Control */ - __IO uint32_t FPC; /*!< (@ 0x4000C128) Floating Prescaler Control */ - __IO uint32_t FPCS; /*!< (@ 0x4000C12C) Floating Prescaler Shadow */ - __I uint32_t PR; /*!< (@ 0x4000C130) Timer Period Value */ - __IO uint32_t PRS; /*!< (@ 0x4000C134) Timer Shadow Period Value */ - __I uint32_t CR; /*!< (@ 0x4000C138) Timer Compare Value */ - __IO uint32_t CRS; /*!< (@ 0x4000C13C) Timer Shadow Compare Value */ - __I uint32_t RESERVED[12]; - __IO uint32_t TIMER; /*!< (@ 0x4000C170) Timer Value */ - __I uint32_t CV[4]; /*!< (@ 0x4000C174) Capture Register 0 */ - __I uint32_t RESERVED1[7]; - __I uint32_t INTS; /*!< (@ 0x4000C1A0) Interrupt Status */ - __IO uint32_t INTE; /*!< (@ 0x4000C1A4) Interrupt Enable Control */ - __IO uint32_t SRS; /*!< (@ 0x4000C1A8) Service Request Selector */ - __O uint32_t SWS; /*!< (@ 0x4000C1AC) Interrupt Status Set */ - __O uint32_t SWR; /*!< (@ 0x4000C1B0) Interrupt Status Clear */ -} CCU4_CC4_TypeDef; - -/* ================================================================================ */ -/* ================ CCU8 [CCU80] ================ */ -/* ================================================================================ */ - -/** - * @brief Capture Compare Unit 8 - Unit 0 (CCU8) - */ - -typedef struct { /*!< (@ 0x40020000) CCU8 Structure */ - __IO uint32_t GCTRL; /*!< (@ 0x40020000) Global Control Register */ - __I uint32_t GSTAT; /*!< (@ 0x40020004) Global Status Register */ - __O uint32_t GIDLS; /*!< (@ 0x40020008) Global Idle Set */ - __O uint32_t GIDLC; /*!< (@ 0x4002000C) Global Idle Clear */ - __O uint32_t GCSS; /*!< (@ 0x40020010) Global Channel Set */ - __O uint32_t GCSC; /*!< (@ 0x40020014) Global Channel Clear */ - __I uint32_t GCST; /*!< (@ 0x40020018) Global Channel status */ - __IO uint32_t GPCHK; /*!< (@ 0x4002001C) Parity Checker Configuration */ - __I uint32_t RESERVED[12]; - __I uint32_t ECRD; /*!< (@ 0x40020050) Extended Capture Mode Read */ - __I uint32_t RESERVED1[11]; - __I uint32_t MIDR; /*!< (@ 0x40020080) Module Identification */ -} CCU8_GLOBAL_TypeDef; - -/* ================================================================================ */ -/* ================ CCU8_CC8 [CCU80_CC80] ================ */ -/* ================================================================================ */ - -/** - * @brief Capture Compare Unit 8 - Unit 0 (CCU8_CC8) - */ - -typedef struct { /*!< (@ 0x40020100) CCU8_CC8 Structure */ - __IO uint32_t INS; /*!< (@ 0x40020100) Input Selector Configuration */ - __IO uint32_t CMC; /*!< (@ 0x40020104) Connection Matrix Control */ - __I uint32_t TCST; /*!< (@ 0x40020108) Slice Timer Status */ - __O uint32_t TCSET; /*!< (@ 0x4002010C) Slice Timer Run Set */ - __O uint32_t TCCLR; /*!< (@ 0x40020110) Slice Timer Clear */ - __IO uint32_t TC; /*!< (@ 0x40020114) Slice Timer Control */ - __IO uint32_t PSL; /*!< (@ 0x40020118) Passive Level Config */ - __I uint32_t DIT; /*!< (@ 0x4002011C) Dither Config */ - __IO uint32_t DITS; /*!< (@ 0x40020120) Dither Shadow Register */ - __IO uint32_t PSC; /*!< (@ 0x40020124) Prescaler Control */ - __IO uint32_t FPC; /*!< (@ 0x40020128) Floating Prescaler Control */ - __IO uint32_t FPCS; /*!< (@ 0x4002012C) Floating Prescaler Shadow */ - __I uint32_t PR; /*!< (@ 0x40020130) Timer Period Value */ - __IO uint32_t PRS; /*!< (@ 0x40020134) Timer Shadow Period Value */ - __I uint32_t CR1; /*!< (@ 0x40020138) Channel 1 Compare Value */ - __IO uint32_t CR1S; /*!< (@ 0x4002013C) Channel 1 Compare Shadow Value */ - __I uint32_t CR2; /*!< (@ 0x40020140) Channel 2 Compare Value */ - __IO uint32_t CR2S; /*!< (@ 0x40020144) Channel 2 Compare Shadow Value */ - __IO uint32_t CHC; /*!< (@ 0x40020148) Channel Control */ - __IO uint32_t DTC; /*!< (@ 0x4002014C) Dead Time Control */ - __IO uint32_t DC1R; /*!< (@ 0x40020150) Channel 1 Dead Time Values */ - __IO uint32_t DC2R; /*!< (@ 0x40020154) Channel 2 Dead Time Values */ - __I uint32_t RESERVED[6]; - __IO uint32_t TIMER; /*!< (@ 0x40020170) Timer Value */ - __I uint32_t CV[4]; /*!< (@ 0x40020174) Capture Register 0 */ - __I uint32_t RESERVED1[7]; - __I uint32_t INTS; /*!< (@ 0x400201A0) Interrupt Status */ - __IO uint32_t INTE; /*!< (@ 0x400201A4) Interrupt Enable Control */ - __IO uint32_t SRS; /*!< (@ 0x400201A8) Service Request Selector */ - __O uint32_t SWS; /*!< (@ 0x400201AC) Interrupt Status Set */ - __O uint32_t SWR; /*!< (@ 0x400201B0) Interrupt Status Clear */ - __IO uint32_t STC; /*!< (@ 0x400201B4) Shadow transfer control */ -} CCU8_CC8_TypeDef; - -/* ================================================================================ */ -/* ================ HRPWM0 ================ */ -/* ================================================================================ */ - -/** - * @brief High Resolution PWM Unit (HRPWM0) - */ - -typedef struct { /*!< (@ 0x40020900) HRPWM0 Structure */ - __IO uint32_t HRBSC; /*!< (@ 0x40020900) Bias and suspend configuration */ - __I uint32_t RESERVED; - __I uint32_t MIDR; /*!< (@ 0x40020908) Module identification register */ - __I uint32_t RESERVED1[2]; - __IO uint32_t GLBANA; /*!< (@ 0x40020914) Global Analog Configuration */ - __I uint32_t RESERVED2[2]; - __IO uint32_t CSGCFG; /*!< (@ 0x40020920) Global CSG configuration */ - __O uint32_t CSGSETG; /*!< (@ 0x40020924) Global CSG run bit set */ - __O uint32_t CSGCLRG; /*!< (@ 0x40020928) Global CSG run bit clear */ - __I uint32_t CSGSTATG; /*!< (@ 0x4002092C) Global CSG run bit status */ - __O uint32_t CSGFCG; /*!< (@ 0x40020930) Global CSG slope/prescaler control */ - __I uint32_t CSGFSG; /*!< (@ 0x40020934) Global CSG slope/prescaler status */ - __O uint32_t CSGTRG; /*!< (@ 0x40020938) Global CSG shadow/switch trigger */ - __O uint32_t CSGTRC; /*!< (@ 0x4002093C) Global CSG shadow trigger clear */ - __I uint32_t CSGTRSG; /*!< (@ 0x40020940) Global CSG shadow/switch status */ - __I uint32_t RESERVED3[7]; - __IO uint32_t HRCCFG; /*!< (@ 0x40020960) Global HRC configuration */ - __O uint32_t HRCSTRG; /*!< (@ 0x40020964) Global HRC shadow trigger set */ - __O uint32_t HRCCTRG; /*!< (@ 0x40020968) Global HRC shadow trigger clear */ - __I uint32_t HRCSTSG; /*!< (@ 0x4002096C) Global HRC shadow transfer status */ - __I uint32_t HRGHRS; /*!< (@ 0x40020970) High Resolution Generation Status */ -} HRPWM0_Type; - -/* ================================================================================ */ -/* ================ HRPWM0_CSG [HRPWM0_CSG0] ================ */ -/* ================================================================================ */ - -/** - * @brief High Resolution PWM Unit (HRPWM0_CSG) - */ - -typedef struct { /*!< (@ 0x40020A00) HRPWM0_CSG Structure */ - __IO uint32_t DCI; /*!< (@ 0x40020A00) External input selection */ - __IO uint32_t IES; /*!< (@ 0x40020A04) External input selection */ - __IO uint32_t SC; /*!< (@ 0x40020A08) Slope generation control */ - __I uint32_t PC; /*!< (@ 0x40020A0C) Pulse swallow configuration */ - __I uint32_t DSV1; /*!< (@ 0x40020A10) DAC reference value 1 */ - __IO uint32_t DSV2; /*!< (@ 0x40020A14) DAC reference value 1 */ - __IO uint32_t SDSV1; /*!< (@ 0x40020A18) Shadow reference value 1 */ - __IO uint32_t SPC; /*!< (@ 0x40020A1C) Shadow Pulse swallow value */ - __IO uint32_t CC; /*!< (@ 0x40020A20) Comparator configuration */ - __IO uint32_t PLC; /*!< (@ 0x40020A24) Passive level configuration */ - __IO uint32_t BLV; /*!< (@ 0x40020A28) Comparator blanking value */ - __IO uint32_t SRE; /*!< (@ 0x40020A2C) Service request enable */ - __IO uint32_t SRS; /*!< (@ 0x40020A30) Service request line selector */ - __O uint32_t SWS; /*!< (@ 0x40020A34) Service request SW set */ - __O uint32_t SWC; /*!< (@ 0x40020A38) Service request SW clear */ - __I uint32_t ISTAT; /*!< (@ 0x40020A3C) Service request status */ -} HRPWM0_CSG_Type; - -/* ================================================================================ */ -/* ================ HRPWM0_HRC [HRPWM0_HRC0] ================ */ -/* ================================================================================ */ - -/** - * @brief High Resolution PWM Unit (HRPWM0_HRC) - */ - -typedef struct { /*!< (@ 0x40021300) HRPWM0_HRC Structure */ - __IO uint32_t GC; /*!< (@ 0x40021300) HRC mode configuration */ - __IO uint32_t PL; /*!< (@ 0x40021304) HRC output passive level */ - __IO uint32_t GSEL; /*!< (@ 0x40021308) HRC global control selection */ - __IO uint32_t TSEL; /*!< (@ 0x4002130C) HRC timer selection */ - __I uint32_t SC; /*!< (@ 0x40021310) HRC current source for shadow */ - __I uint32_t DCR; /*!< (@ 0x40021314) HRC dead time rising value */ - __I uint32_t DCF; /*!< (@ 0x40021318) HRC dead time falling value */ - __I uint32_t CR1; /*!< (@ 0x4002131C) HRC rising edge value */ - __I uint32_t CR2; /*!< (@ 0x40021320) HRC falling edge value */ - __IO uint32_t SSC; /*!< (@ 0x40021324) HRC next source for shadow */ - __IO uint32_t SDCR; /*!< (@ 0x40021328) HRC shadow dead time rising */ - __IO uint32_t SDCF; /*!< (@ 0x4002132C) HRC shadow dead time falling */ - __IO uint32_t SCR1; /*!< (@ 0x40021330) HRC shadow rising edge value */ - __IO uint32_t SCR2; /*!< (@ 0x40021334) HRC shadow falling edge value */ -} HRPWM0_HRC_Type; - -/* ================================================================================ */ -/* ================ POSIF [POSIF0] ================ */ -/* ================================================================================ */ - -/** - * @brief Position Interface 0 (POSIF) - */ - -typedef struct { /*!< (@ 0x40028000) POSIF Structure */ - __IO uint32_t PCONF; /*!< (@ 0x40028000) Service Request Processing configuration */ - __IO uint32_t PSUS; /*!< (@ 0x40028004) Service Request Processing Suspend Config */ - __O uint32_t PRUNS; /*!< (@ 0x40028008) Service Request Processing Run Bit Set */ - __O uint32_t PRUNC; /*!< (@ 0x4002800C) Service Request Processing Run Bit Clear */ - __I uint32_t PRUN; /*!< (@ 0x40028010) Service Request Processing Run Bit Status */ - __I uint32_t RESERVED[3]; - __I uint32_t MIDR; /*!< (@ 0x40028020) Module Identification register */ - __I uint32_t RESERVED1[3]; - __I uint32_t HALP; /*!< (@ 0x40028030) Hall Sensor Patterns */ - __IO uint32_t HALPS; /*!< (@ 0x40028034) Hall Sensor Shadow Patterns */ - __I uint32_t RESERVED2[2]; - __I uint32_t MCM; /*!< (@ 0x40028040) Multi-Channel Pattern */ - __IO uint32_t MCSM; /*!< (@ 0x40028044) Multi-Channel Shadow Pattern */ - __O uint32_t MCMS; /*!< (@ 0x40028048) Multi-Channel Pattern Control set */ - __O uint32_t MCMC; /*!< (@ 0x4002804C) Multi-Channel Pattern Control clear */ - __I uint32_t MCMF; /*!< (@ 0x40028050) Multi-Channel Pattern Control flag */ - __I uint32_t RESERVED3[3]; - __IO uint32_t QDC; /*!< (@ 0x40028060) Quadrature Decoder Control */ - __I uint32_t RESERVED4[3]; - __I uint32_t PFLG; /*!< (@ 0x40028070) Service Request Processing Interrupt Flags */ - __IO uint32_t PFLGE; /*!< (@ 0x40028074) Service Request Processing Interrupt Enable */ - __O uint32_t SPFLG; /*!< (@ 0x40028078) Service Request Processing Interrupt Set */ - __O uint32_t RPFLG; /*!< (@ 0x4002807C) Service Request Processing Interrupt Clear */ - __I uint32_t RESERVED5[32]; - __I uint32_t PDBG; /*!< (@ 0x40028100) POSIF Debug register */ -} POSIF_GLOBAL_TypeDef; - -/* ================================================================================ */ -/* ================ PORT0 ================ */ -/* ================================================================================ */ - -/** - * @brief Port 0 (PORT0) - */ - -typedef struct { /*!< (@ 0x48028000) PORT0 Structure */ - __IO uint32_t OUT; /*!< (@ 0x48028000) Port 0 Output Register */ - __O uint32_t OMR; /*!< (@ 0x48028004) Port 0 Output Modification Register */ - __I uint32_t RESERVED[2]; - __IO uint32_t IOCR0; /*!< (@ 0x48028010) Port 0 Input/Output Control Register 0 */ - __IO uint32_t IOCR4; /*!< (@ 0x48028014) Port 0 Input/Output Control Register 4 */ - __IO uint32_t IOCR8; /*!< (@ 0x48028018) Port 0 Input/Output Control Register 8 */ - __I uint32_t RESERVED1[2]; - __I uint32_t IN; /*!< (@ 0x48028024) Port 0 Input Register */ - __I uint32_t RESERVED2[6]; - __IO uint32_t PDR0; /*!< (@ 0x48028040) Port 0 Pad Driver Mode 0 Register */ - __IO uint32_t PDR1; /*!< (@ 0x48028044) Port 0 Pad Driver Mode 1 Register */ - __I uint32_t RESERVED3[6]; - __I uint32_t PDISC; /*!< (@ 0x48028060) Port 0 Pin Function Decision Control Register */ - __I uint32_t RESERVED4[3]; - __IO uint32_t PPS; /*!< (@ 0x48028070) Port 0 Pin Power Save Register */ - __IO uint32_t HWSEL; /*!< (@ 0x48028074) Port 0 Pin Hardware Select Register */ -} PORT0_Type; - -/* ================================================================================ */ -/* ================ PORT1 ================ */ -/* ================================================================================ */ - -/** - * @brief Port 1 (PORT1) - */ - -typedef struct { /*!< (@ 0x48028100) PORT1 Structure */ - __IO uint32_t OUT; /*!< (@ 0x48028100) Port 1 Output Register */ - __O uint32_t OMR; /*!< (@ 0x48028104) Port 1 Output Modification Register */ - __I uint32_t RESERVED[2]; - __IO uint32_t IOCR0; /*!< (@ 0x48028110) Port 1 Input/Output Control Register 0 */ - __IO uint32_t IOCR4; /*!< (@ 0x48028114) Port 1 Input/Output Control Register 4 */ - __IO uint32_t IOCR8; /*!< (@ 0x48028118) Port 1 Input/Output Control Register 8 */ - __IO uint32_t IOCR12; /*!< (@ 0x4802811C) Port 1 Input/Output Control Register 12 */ - __I uint32_t RESERVED1; - __I uint32_t IN; /*!< (@ 0x48028124) Port 1 Input Register */ - __I uint32_t RESERVED2[6]; - __IO uint32_t PDR0; /*!< (@ 0x48028140) Port 1 Pad Driver Mode 0 Register */ - __IO uint32_t PDR1; /*!< (@ 0x48028144) Port 1 Pad Driver Mode 1 Register */ - __I uint32_t RESERVED3[6]; - __I uint32_t PDISC; /*!< (@ 0x48028160) Port 1 Pin Function Decision Control Register */ - __I uint32_t RESERVED4[3]; - __IO uint32_t PPS; /*!< (@ 0x48028170) Port 1 Pin Power Save Register */ - __IO uint32_t HWSEL; /*!< (@ 0x48028174) Port 1 Pin Hardware Select Register */ -} PORT1_Type; - -/* ================================================================================ */ -/* ================ PORT2 ================ */ -/* ================================================================================ */ - -/** - * @brief Port 2 (PORT2) - */ - -typedef struct { /*!< (@ 0x48028200) PORT2 Structure */ - __IO uint32_t OUT; /*!< (@ 0x48028200) Port 2 Output Register */ - __O uint32_t OMR; /*!< (@ 0x48028204) Port 2 Output Modification Register */ - __I uint32_t RESERVED[2]; - __IO uint32_t IOCR0; /*!< (@ 0x48028210) Port 2 Input/Output Control Register 0 */ - __IO uint32_t IOCR4; /*!< (@ 0x48028214) Port 2 Input/Output Control Register 4 */ - __IO uint32_t IOCR8; /*!< (@ 0x48028218) Port 2 Input/Output Control Register 8 */ - __IO uint32_t IOCR12; /*!< (@ 0x4802821C) Port 2 Input/Output Control Register 12 */ - __I uint32_t RESERVED1; - __I uint32_t IN; /*!< (@ 0x48028224) Port 2 Input Register */ - __I uint32_t RESERVED2[6]; - __IO uint32_t PDR0; /*!< (@ 0x48028240) Port 2 Pad Driver Mode 0 Register */ - __IO uint32_t PDR1; /*!< (@ 0x48028244) Port 2 Pad Driver Mode 1 Register */ - __I uint32_t RESERVED3[6]; - __I uint32_t PDISC; /*!< (@ 0x48028260) Port 2 Pin Function Decision Control Register */ - __I uint32_t RESERVED4[3]; - __IO uint32_t PPS; /*!< (@ 0x48028270) Port 2 Pin Power Save Register */ - __IO uint32_t HWSEL; /*!< (@ 0x48028274) Port 2 Pin Hardware Select Register */ -} PORT2_Type; - -/* ================================================================================ */ -/* ================ PORT3 ================ */ -/* ================================================================================ */ - -/** - * @brief Port 3 (PORT3) - */ - -typedef struct { /*!< (@ 0x48028300) PORT3 Structure */ - __IO uint32_t OUT; /*!< (@ 0x48028300) Port 3 Output Register */ - __O uint32_t OMR; /*!< (@ 0x48028304) Port 3 Output Modification Register */ - __I uint32_t RESERVED[2]; - __IO uint32_t IOCR0; /*!< (@ 0x48028310) Port 3 Input/Output Control Register 0 */ - __I uint32_t RESERVED1[4]; - __I uint32_t IN; /*!< (@ 0x48028324) Port 3 Input Register */ - __I uint32_t RESERVED2[6]; - __IO uint32_t PDR0; /*!< (@ 0x48028340) Port 3 Pad Driver Mode 0 Register */ - __I uint32_t RESERVED3[7]; - __I uint32_t PDISC; /*!< (@ 0x48028360) Port 3 Pin Function Decision Control Register */ - __I uint32_t RESERVED4[3]; - __IO uint32_t PPS; /*!< (@ 0x48028370) Port 3 Pin Power Save Register */ - __IO uint32_t HWSEL; /*!< (@ 0x48028374) Port 3 Pin Hardware Select Register */ -} PORT3_Type; - -/* ================================================================================ */ -/* ================ PORT14 ================ */ -/* ================================================================================ */ - -/** - * @brief Port 14 (PORT14) - */ - -typedef struct { /*!< (@ 0x48028E00) PORT14 Structure */ - __IO uint32_t OUT; /*!< (@ 0x48028E00) Port 14 Output Register */ - __O uint32_t OMR; /*!< (@ 0x48028E04) Port 14 Output Modification Register */ - __I uint32_t RESERVED[2]; - __IO uint32_t IOCR0; /*!< (@ 0x48028E10) Port 14 Input/Output Control Register 0 */ - __IO uint32_t IOCR4; /*!< (@ 0x48028E14) Port 14 Input/Output Control Register 4 */ - __IO uint32_t IOCR8; /*!< (@ 0x48028E18) Port 14 Input/Output Control Register 8 */ - __IO uint32_t IOCR12; /*!< (@ 0x48028E1C) Port 14 Input/Output Control Register 12 */ - __I uint32_t RESERVED1; - __I uint32_t IN; /*!< (@ 0x48028E24) Port 14 Input Register */ - __I uint32_t RESERVED2[14]; - __IO uint32_t PDISC; /*!< (@ 0x48028E60) Port 14 Pin Function Decision Control Register */ - __I uint32_t RESERVED3[3]; - __IO uint32_t PPS; /*!< (@ 0x48028E70) Port 14 Pin Power Save Register */ - __IO uint32_t HWSEL; /*!< (@ 0x48028E74) Port 14 Pin Hardware Select Register */ -} PORT14_Type; - -/* -------------------- End of section using anonymous unions ------------------- */ -#if defined(__CC_ARM) - #pragma pop -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#elif defined(__ICCARM__) - /* leave anonymous unions enabled */ -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined(__TASKING__) - #pragma warning restore -#else - #warning Not supported compiler type -#endif - -/* ================================================================================ */ -/* ================ struct 'PPB' Position & Mask ================ */ -/* ================================================================================ */ - -/* ---------------------------------- PPB_ACTLR --------------------------------- */ -#define PPB_ACTLR_DISMCYCINT_Pos \ - (0UL) /*!< PPB ACTLR: DISMCYCINT (Bit 0) */ -#define PPB_ACTLR_DISMCYCINT_Msk \ - (0x1UL) /*!< PPB ACTLR: DISMCYCINT (Bitfield-Mask: 0x01) */ -#define PPB_ACTLR_DISDEFWBUF_Pos \ - (1UL) /*!< PPB ACTLR: DISDEFWBUF (Bit 1) */ -#define PPB_ACTLR_DISDEFWBUF_Msk \ - (0x2UL) /*!< PPB ACTLR: DISDEFWBUF (Bitfield-Mask: 0x01) */ -#define PPB_ACTLR_DISFOLD_Pos \ - (2UL) /*!< PPB ACTLR: DISFOLD (Bit 2) */ -#define PPB_ACTLR_DISFOLD_Msk \ - (0x4UL) /*!< PPB ACTLR: DISFOLD (Bitfield-Mask: 0x01) */ -#define PPB_ACTLR_DISFPCA_Pos \ - (8UL) /*!< PPB ACTLR: DISFPCA (Bit 8) */ -#define PPB_ACTLR_DISFPCA_Msk \ - (0x100UL) /*!< PPB ACTLR: DISFPCA (Bitfield-Mask: 0x01) */ -#define PPB_ACTLR_DISOOFP_Pos \ - (9UL) /*!< PPB ACTLR: DISOOFP (Bit 9) */ -#define PPB_ACTLR_DISOOFP_Msk \ - (0x200UL) /*!< PPB ACTLR: DISOOFP (Bitfield-Mask: 0x01) */ - -/* -------------------------------- PPB_SYST_CSR -------------------------------- */ -#define PPB_SYST_CSR_ENABLE_Pos \ - (0UL) /*!< PPB SYST_CSR: ENABLE (Bit 0) */ -#define PPB_SYST_CSR_ENABLE_Msk \ - (0x1UL) /*!< PPB SYST_CSR: ENABLE (Bitfield-Mask: 0x01) */ -#define PPB_SYST_CSR_TICKINT_Pos \ - (1UL) /*!< PPB SYST_CSR: TICKINT (Bit 1) */ -#define PPB_SYST_CSR_TICKINT_Msk \ - (0x2UL) /*!< PPB SYST_CSR: TICKINT (Bitfield-Mask: 0x01) */ -#define PPB_SYST_CSR_CLKSOURCE_Pos \ - (2UL) /*!< PPB SYST_CSR: CLKSOURCE (Bit 2) */ -#define PPB_SYST_CSR_CLKSOURCE_Msk \ - (0x4UL) /*!< PPB SYST_CSR: CLKSOURCE (Bitfield-Mask: 0x01) */ -#define PPB_SYST_CSR_COUNTFLAG_Pos \ - (16UL) /*!< PPB SYST_CSR: COUNTFLAG (Bit 16) */ -#define PPB_SYST_CSR_COUNTFLAG_Msk \ - (0x10000UL) /*!< PPB SYST_CSR: COUNTFLAG (Bitfield-Mask: 0x01) */ - -/* -------------------------------- PPB_SYST_RVR -------------------------------- */ -#define PPB_SYST_RVR_RELOAD_Pos \ - (0UL) /*!< PPB SYST_RVR: RELOAD (Bit 0) */ -#define PPB_SYST_RVR_RELOAD_Msk \ - (0xffffffUL) /*!< PPB SYST_RVR: RELOAD (Bitfield-Mask: 0xffffff) */ - -/* -------------------------------- PPB_SYST_CVR -------------------------------- */ -#define PPB_SYST_CVR_CURRENT_Pos \ - (0UL) /*!< PPB SYST_CVR: CURRENT (Bit 0) */ -#define PPB_SYST_CVR_CURRENT_Msk \ - (0xffffffUL) /*!< PPB SYST_CVR: CURRENT (Bitfield-Mask: 0xffffff) */ - -/* ------------------------------- PPB_SYST_CALIB ------------------------------- */ -#define PPB_SYST_CALIB_TENMS_Pos \ - (0UL) /*!< PPB SYST_CALIB: TENMS (Bit 0) */ -#define PPB_SYST_CALIB_TENMS_Msk \ - (0xffffffUL) /*!< PPB SYST_CALIB: TENMS (Bitfield-Mask: 0xffffff) */ -#define PPB_SYST_CALIB_SKEW_Pos \ - (30UL) /*!< PPB SYST_CALIB: SKEW (Bit 30) */ -#define PPB_SYST_CALIB_SKEW_Msk \ - (0x40000000UL) /*!< PPB SYST_CALIB: SKEW (Bitfield-Mask: 0x01) */ -#define PPB_SYST_CALIB_NOREF_Pos \ - (31UL) /*!< PPB SYST_CALIB: NOREF (Bit 31) */ -#define PPB_SYST_CALIB_NOREF_Msk \ - (0x80000000UL) /*!< PPB SYST_CALIB: NOREF (Bitfield-Mask: 0x01) */ - -/* ------------------------------- PPB_NVIC_ISER0 ------------------------------- */ -#define PPB_NVIC_ISER0_SETENA_Pos \ - (0UL) /*!< PPB NVIC_ISER0: SETENA (Bit 0) */ -#define PPB_NVIC_ISER0_SETENA_Msk \ - (0xffffffffUL) /*!< PPB NVIC_ISER0: SETENA (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------- PPB_NVIC_ISER1 ------------------------------- */ -#define PPB_NVIC_ISER1_SETENA_Pos \ - (0UL) /*!< PPB NVIC_ISER1: SETENA (Bit 0) */ -#define PPB_NVIC_ISER1_SETENA_Msk \ - (0xffffffffUL) /*!< PPB NVIC_ISER1: SETENA (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------- PPB_NVIC_ISER2 ------------------------------- */ -#define PPB_NVIC_ISER2_SETENA_Pos \ - (0UL) /*!< PPB NVIC_ISER2: SETENA (Bit 0) */ -#define PPB_NVIC_ISER2_SETENA_Msk \ - (0xffffffffUL) /*!< PPB NVIC_ISER2: SETENA (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------- PPB_NVIC_ISER3 ------------------------------- */ -#define PPB_NVIC_ISER3_SETENA_Pos \ - (0UL) /*!< PPB NVIC_ISER3: SETENA (Bit 0) */ -#define PPB_NVIC_ISER3_SETENA_Msk \ - (0xffffffffUL) /*!< PPB NVIC_ISER3: SETENA (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------- PPB_NVIC_ICER0 ------------------------------- */ -#define PPB_NVIC_ICER0_CLRENA_Pos \ - (0UL) /*!< PPB NVIC_ICER0: CLRENA (Bit 0) */ -#define PPB_NVIC_ICER0_CLRENA_Msk \ - (0xffffffffUL) /*!< PPB NVIC_ICER0: CLRENA (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------- PPB_NVIC_ICER1 ------------------------------- */ -#define PPB_NVIC_ICER1_CLRENA_Pos \ - (0UL) /*!< PPB NVIC_ICER1: CLRENA (Bit 0) */ -#define PPB_NVIC_ICER1_CLRENA_Msk \ - (0xffffffffUL) /*!< PPB NVIC_ICER1: CLRENA (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------- PPB_NVIC_ICER2 ------------------------------- */ -#define PPB_NVIC_ICER2_CLRENA_Pos \ - (0UL) /*!< PPB NVIC_ICER2: CLRENA (Bit 0) */ -#define PPB_NVIC_ICER2_CLRENA_Msk \ - (0xffffffffUL) /*!< PPB NVIC_ICER2: CLRENA (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------- PPB_NVIC_ICER3 ------------------------------- */ -#define PPB_NVIC_ICER3_CLRENA_Pos \ - (0UL) /*!< PPB NVIC_ICER3: CLRENA (Bit 0) */ -#define PPB_NVIC_ICER3_CLRENA_Msk \ - (0xffffffffUL) /*!< PPB NVIC_ICER3: CLRENA (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------- PPB_NVIC_ISPR0 ------------------------------- */ -#define PPB_NVIC_ISPR0_SETPEND_Pos \ - (0UL) /*!< PPB NVIC_ISPR0: SETPEND (Bit 0) */ -#define PPB_NVIC_ISPR0_SETPEND_Msk \ - (0xffffffffUL) /*!< PPB NVIC_ISPR0: SETPEND (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------- PPB_NVIC_ISPR1 ------------------------------- */ -#define PPB_NVIC_ISPR1_SETPEND_Pos \ - (0UL) /*!< PPB NVIC_ISPR1: SETPEND (Bit 0) */ -#define PPB_NVIC_ISPR1_SETPEND_Msk \ - (0xffffffffUL) /*!< PPB NVIC_ISPR1: SETPEND (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------- PPB_NVIC_ISPR2 ------------------------------- */ -#define PPB_NVIC_ISPR2_SETPEND_Pos \ - (0UL) /*!< PPB NVIC_ISPR2: SETPEND (Bit 0) */ -#define PPB_NVIC_ISPR2_SETPEND_Msk \ - (0xffffffffUL) /*!< PPB NVIC_ISPR2: SETPEND (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------- PPB_NVIC_ISPR3 ------------------------------- */ -#define PPB_NVIC_ISPR3_SETPEND_Pos \ - (0UL) /*!< PPB NVIC_ISPR3: SETPEND (Bit 0) */ -#define PPB_NVIC_ISPR3_SETPEND_Msk \ - (0xffffffffUL) /*!< PPB NVIC_ISPR3: SETPEND (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------- PPB_NVIC_ICPR0 ------------------------------- */ -#define PPB_NVIC_ICPR0_CLRPEND_Pos \ - (0UL) /*!< PPB NVIC_ICPR0: CLRPEND (Bit 0) */ -#define PPB_NVIC_ICPR0_CLRPEND_Msk \ - (0xffffffffUL) /*!< PPB NVIC_ICPR0: CLRPEND (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------- PPB_NVIC_ICPR1 ------------------------------- */ -#define PPB_NVIC_ICPR1_CLRPEND_Pos \ - (0UL) /*!< PPB NVIC_ICPR1: CLRPEND (Bit 0) */ -#define PPB_NVIC_ICPR1_CLRPEND_Msk \ - (0xffffffffUL) /*!< PPB NVIC_ICPR1: CLRPEND (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------- PPB_NVIC_ICPR2 ------------------------------- */ -#define PPB_NVIC_ICPR2_CLRPEND_Pos \ - (0UL) /*!< PPB NVIC_ICPR2: CLRPEND (Bit 0) */ -#define PPB_NVIC_ICPR2_CLRPEND_Msk \ - (0xffffffffUL) /*!< PPB NVIC_ICPR2: CLRPEND (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------- PPB_NVIC_ICPR3 ------------------------------- */ -#define PPB_NVIC_ICPR3_CLRPEND_Pos \ - (0UL) /*!< PPB NVIC_ICPR3: CLRPEND (Bit 0) */ -#define PPB_NVIC_ICPR3_CLRPEND_Msk \ - (0xffffffffUL) /*!< PPB NVIC_ICPR3: CLRPEND (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------- PPB_NVIC_IABR0 ------------------------------- */ -#define PPB_NVIC_IABR0_ACTIVE_Pos \ - (0UL) /*!< PPB NVIC_IABR0: ACTIVE (Bit 0) */ -#define PPB_NVIC_IABR0_ACTIVE_Msk \ - (0xffffffffUL) /*!< PPB NVIC_IABR0: ACTIVE (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------- PPB_NVIC_IABR1 ------------------------------- */ -#define PPB_NVIC_IABR1_ACTIVE_Pos \ - (0UL) /*!< PPB NVIC_IABR1: ACTIVE (Bit 0) */ -#define PPB_NVIC_IABR1_ACTIVE_Msk \ - (0xffffffffUL) /*!< PPB NVIC_IABR1: ACTIVE (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------- PPB_NVIC_IABR2 ------------------------------- */ -#define PPB_NVIC_IABR2_ACTIVE_Pos \ - (0UL) /*!< PPB NVIC_IABR2: ACTIVE (Bit 0) */ -#define PPB_NVIC_IABR2_ACTIVE_Msk \ - (0xffffffffUL) /*!< PPB NVIC_IABR2: ACTIVE (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------- PPB_NVIC_IABR3 ------------------------------- */ -#define PPB_NVIC_IABR3_ACTIVE_Pos \ - (0UL) /*!< PPB NVIC_IABR3: ACTIVE (Bit 0) */ -#define PPB_NVIC_IABR3_ACTIVE_Msk \ - (0xffffffffUL) /*!< PPB NVIC_IABR3: ACTIVE (Bitfield-Mask: 0xffffffff) */ - -/* -------------------------------- PPB_NVIC_IPR0 ------------------------------- */ -#define PPB_NVIC_IPR0_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR0: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR0_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR0: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR0_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR0: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR0_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR0: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR0_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR0: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR0_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR0: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR0_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR0: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR0_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR0: PRI_3 (Bitfield-Mask: 0xff) */ - -/* -------------------------------- PPB_NVIC_IPR1 ------------------------------- */ -#define PPB_NVIC_IPR1_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR1: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR1_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR1: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR1_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR1: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR1_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR1: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR1_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR1: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR1_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR1: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR1_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR1: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR1_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR1: PRI_3 (Bitfield-Mask: 0xff) */ - -/* -------------------------------- PPB_NVIC_IPR2 ------------------------------- */ -#define PPB_NVIC_IPR2_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR2: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR2_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR2: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR2_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR2: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR2_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR2: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR2_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR2: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR2_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR2: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR2_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR2: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR2_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR2: PRI_3 (Bitfield-Mask: 0xff) */ - -/* -------------------------------- PPB_NVIC_IPR3 ------------------------------- */ -#define PPB_NVIC_IPR3_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR3: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR3_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR3: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR3_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR3: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR3_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR3: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR3_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR3: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR3_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR3: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR3_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR3: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR3_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR3: PRI_3 (Bitfield-Mask: 0xff) */ - -/* -------------------------------- PPB_NVIC_IPR4 ------------------------------- */ -#define PPB_NVIC_IPR4_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR4: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR4_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR4: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR4_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR4: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR4_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR4: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR4_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR4: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR4_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR4: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR4_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR4: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR4_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR4: PRI_3 (Bitfield-Mask: 0xff) */ - -/* -------------------------------- PPB_NVIC_IPR5 ------------------------------- */ -#define PPB_NVIC_IPR5_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR5: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR5_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR5: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR5_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR5: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR5_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR5: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR5_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR5: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR5_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR5: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR5_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR5: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR5_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR5: PRI_3 (Bitfield-Mask: 0xff) */ - -/* -------------------------------- PPB_NVIC_IPR6 ------------------------------- */ -#define PPB_NVIC_IPR6_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR6: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR6_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR6: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR6_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR6: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR6_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR6: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR6_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR6: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR6_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR6: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR6_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR6: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR6_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR6: PRI_3 (Bitfield-Mask: 0xff) */ - -/* -------------------------------- PPB_NVIC_IPR7 ------------------------------- */ -#define PPB_NVIC_IPR7_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR7: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR7_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR7: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR7_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR7: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR7_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR7: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR7_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR7: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR7_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR7: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR7_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR7: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR7_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR7: PRI_3 (Bitfield-Mask: 0xff) */ - -/* -------------------------------- PPB_NVIC_IPR8 ------------------------------- */ -#define PPB_NVIC_IPR8_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR8: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR8_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR8: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR8_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR8: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR8_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR8: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR8_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR8: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR8_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR8: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR8_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR8: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR8_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR8: PRI_3 (Bitfield-Mask: 0xff) */ - -/* -------------------------------- PPB_NVIC_IPR9 ------------------------------- */ -#define PPB_NVIC_IPR9_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR9: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR9_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR9: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR9_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR9: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR9_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR9: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR9_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR9: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR9_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR9: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR9_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR9: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR9_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR9: PRI_3 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- PPB_NVIC_IPR10 ------------------------------- */ -#define PPB_NVIC_IPR10_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR10: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR10_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR10: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR10_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR10: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR10_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR10: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR10_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR10: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR10_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR10: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR10_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR10: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR10_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR10: PRI_3 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- PPB_NVIC_IPR11 ------------------------------- */ -#define PPB_NVIC_IPR11_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR11: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR11_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR11: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR11_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR11: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR11_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR11: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR11_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR11: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR11_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR11: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR11_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR11: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR11_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR11: PRI_3 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- PPB_NVIC_IPR12 ------------------------------- */ -#define PPB_NVIC_IPR12_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR12: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR12_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR12: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR12_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR12: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR12_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR12: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR12_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR12: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR12_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR12: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR12_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR12: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR12_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR12: PRI_3 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- PPB_NVIC_IPR13 ------------------------------- */ -#define PPB_NVIC_IPR13_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR13: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR13_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR13: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR13_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR13: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR13_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR13: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR13_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR13: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR13_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR13: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR13_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR13: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR13_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR13: PRI_3 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- PPB_NVIC_IPR14 ------------------------------- */ -#define PPB_NVIC_IPR14_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR14: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR14_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR14: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR14_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR14: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR14_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR14: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR14_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR14: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR14_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR14: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR14_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR14: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR14_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR14: PRI_3 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- PPB_NVIC_IPR15 ------------------------------- */ -#define PPB_NVIC_IPR15_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR15: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR15_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR15: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR15_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR15: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR15_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR15: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR15_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR15: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR15_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR15: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR15_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR15: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR15_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR15: PRI_3 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- PPB_NVIC_IPR16 ------------------------------- */ -#define PPB_NVIC_IPR16_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR16: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR16_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR16: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR16_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR16: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR16_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR16: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR16_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR16: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR16_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR16: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR16_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR16: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR16_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR16: PRI_3 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- PPB_NVIC_IPR17 ------------------------------- */ -#define PPB_NVIC_IPR17_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR17: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR17_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR17: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR17_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR17: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR17_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR17: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR17_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR17: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR17_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR17: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR17_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR17: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR17_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR17: PRI_3 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- PPB_NVIC_IPR18 ------------------------------- */ -#define PPB_NVIC_IPR18_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR18: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR18_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR18: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR18_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR18: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR18_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR18: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR18_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR18: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR18_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR18: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR18_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR18: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR18_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR18: PRI_3 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- PPB_NVIC_IPR19 ------------------------------- */ -#define PPB_NVIC_IPR19_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR19: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR19_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR19: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR19_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR19: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR19_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR19: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR19_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR19: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR19_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR19: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR19_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR19: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR19_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR19: PRI_3 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- PPB_NVIC_IPR20 ------------------------------- */ -#define PPB_NVIC_IPR20_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR20: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR20_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR20: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR20_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR20: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR20_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR20: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR20_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR20: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR20_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR20: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR20_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR20: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR20_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR20: PRI_3 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- PPB_NVIC_IPR21 ------------------------------- */ -#define PPB_NVIC_IPR21_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR21: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR21_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR21: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR21_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR21: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR21_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR21: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR21_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR21: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR21_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR21: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR21_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR21: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR21_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR21: PRI_3 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- PPB_NVIC_IPR22 ------------------------------- */ -#define PPB_NVIC_IPR22_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR22: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR22_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR22: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR22_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR22: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR22_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR22: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR22_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR22: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR22_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR22: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR22_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR22: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR22_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR22: PRI_3 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- PPB_NVIC_IPR23 ------------------------------- */ -#define PPB_NVIC_IPR23_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR23: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR23_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR23: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR23_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR23: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR23_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR23: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR23_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR23: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR23_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR23: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR23_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR23: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR23_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR23: PRI_3 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- PPB_NVIC_IPR24 ------------------------------- */ -#define PPB_NVIC_IPR24_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR24: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR24_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR24: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR24_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR24: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR24_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR24: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR24_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR24: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR24_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR24: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR24_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR24: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR24_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR24: PRI_3 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- PPB_NVIC_IPR25 ------------------------------- */ -#define PPB_NVIC_IPR25_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR25: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR25_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR25: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR25_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR25: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR25_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR25: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR25_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR25: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR25_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR25: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR25_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR25: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR25_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR25: PRI_3 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- PPB_NVIC_IPR26 ------------------------------- */ -#define PPB_NVIC_IPR26_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR26: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR26_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR26: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR26_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR26: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR26_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR26: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR26_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR26: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR26_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR26: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR26_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR26: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR26_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR26: PRI_3 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- PPB_NVIC_IPR27 ------------------------------- */ -#define PPB_NVIC_IPR27_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR27: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR27_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR27: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR27_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR27: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR27_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR27: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR27_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR27: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR27_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR27: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR27_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR27: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR27_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR27: PRI_3 (Bitfield-Mask: 0xff) */ - -/* ---------------------------------- PPB_CPUID --------------------------------- */ -#define PPB_CPUID_Revision_Pos \ - (0UL) /*!< PPB CPUID: Revision (Bit 0) */ -#define PPB_CPUID_Revision_Msk \ - (0xfUL) /*!< PPB CPUID: Revision (Bitfield-Mask: 0x0f) */ -#define PPB_CPUID_PartNo_Pos \ - (4UL) /*!< PPB CPUID: PartNo (Bit 4) */ -#define PPB_CPUID_PartNo_Msk \ - (0xfff0UL) /*!< PPB CPUID: PartNo (Bitfield-Mask: 0xfff) */ -#define PPB_CPUID_Constant_Pos \ - (16UL) /*!< PPB CPUID: Constant (Bit 16) */ -#define PPB_CPUID_Constant_Msk \ - (0xf0000UL) /*!< PPB CPUID: Constant (Bitfield-Mask: 0x0f) */ -#define PPB_CPUID_Variant_Pos \ - (20UL) /*!< PPB CPUID: Variant (Bit 20) */ -#define PPB_CPUID_Variant_Msk \ - (0xf00000UL) /*!< PPB CPUID: Variant (Bitfield-Mask: 0x0f) */ -#define PPB_CPUID_Implementer_Pos \ - (24UL) /*!< PPB CPUID: Implementer (Bit 24) */ -#define PPB_CPUID_Implementer_Msk \ - (0xff000000UL) /*!< PPB CPUID: Implementer (Bitfield-Mask: 0xff) */ - -/* ---------------------------------- PPB_ICSR ---------------------------------- */ -#define PPB_ICSR_VECTACTIVE_Pos \ - (0UL) /*!< PPB ICSR: VECTACTIVE (Bit 0) */ -#define PPB_ICSR_VECTACTIVE_Msk \ - (0x1ffUL) /*!< PPB ICSR: VECTACTIVE (Bitfield-Mask: 0x1ff) */ -#define PPB_ICSR_RETTOBASE_Pos \ - (11UL) /*!< PPB ICSR: RETTOBASE (Bit 11) */ -#define PPB_ICSR_RETTOBASE_Msk \ - (0x800UL) /*!< PPB ICSR: RETTOBASE (Bitfield-Mask: 0x01) */ -#define PPB_ICSR_VECTPENDING_Pos \ - (12UL) /*!< PPB ICSR: VECTPENDING (Bit 12) */ -#define PPB_ICSR_VECTPENDING_Msk \ - (0x3f000UL) /*!< PPB ICSR: VECTPENDING (Bitfield-Mask: 0x3f) */ -#define PPB_ICSR_ISRPENDING_Pos \ - (22UL) /*!< PPB ICSR: ISRPENDING (Bit 22) */ -#define PPB_ICSR_ISRPENDING_Msk \ - (0x400000UL) /*!< PPB ICSR: ISRPENDING (Bitfield-Mask: 0x01) */ -#define PPB_ICSR_PENDSTCLR_Pos \ - (25UL) /*!< PPB ICSR: PENDSTCLR (Bit 25) */ -#define PPB_ICSR_PENDSTCLR_Msk \ - (0x2000000UL) /*!< PPB ICSR: PENDSTCLR (Bitfield-Mask: 0x01) */ -#define PPB_ICSR_PENDSTSET_Pos \ - (26UL) /*!< PPB ICSR: PENDSTSET (Bit 26) */ -#define PPB_ICSR_PENDSTSET_Msk \ - (0x4000000UL) /*!< PPB ICSR: PENDSTSET (Bitfield-Mask: 0x01) */ -#define PPB_ICSR_PENDSVCLR_Pos \ - (27UL) /*!< PPB ICSR: PENDSVCLR (Bit 27) */ -#define PPB_ICSR_PENDSVCLR_Msk \ - (0x8000000UL) /*!< PPB ICSR: PENDSVCLR (Bitfield-Mask: 0x01) */ -#define PPB_ICSR_PENDSVSET_Pos \ - (28UL) /*!< PPB ICSR: PENDSVSET (Bit 28) */ -#define PPB_ICSR_PENDSVSET_Msk \ - (0x10000000UL) /*!< PPB ICSR: PENDSVSET (Bitfield-Mask: 0x01) */ -#define PPB_ICSR_NMIPENDSET_Pos \ - (31UL) /*!< PPB ICSR: NMIPENDSET (Bit 31) */ -#define PPB_ICSR_NMIPENDSET_Msk \ - (0x80000000UL) /*!< PPB ICSR: NMIPENDSET (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- PPB_VTOR ---------------------------------- */ -#define PPB_VTOR_TBLOFF_Pos \ - (10UL) /*!< PPB VTOR: TBLOFF (Bit 10) */ -#define PPB_VTOR_TBLOFF_Msk \ - (0xfffffc00UL) /*!< PPB VTOR: TBLOFF (Bitfield-Mask: 0x3fffff) */ - -/* ---------------------------------- PPB_AIRCR --------------------------------- */ -#define PPB_AIRCR_VECTRESET_Pos \ - (0UL) /*!< PPB AIRCR: VECTRESET (Bit 0) */ -#define PPB_AIRCR_VECTRESET_Msk \ - (0x1UL) /*!< PPB AIRCR: VECTRESET (Bitfield-Mask: 0x01) */ -#define PPB_AIRCR_VECTCLRACTIVE_Pos \ - (1UL) /*!< PPB AIRCR: VECTCLRACTIVE (Bit 1) */ -#define PPB_AIRCR_VECTCLRACTIVE_Msk \ - (0x2UL) /*!< PPB AIRCR: VECTCLRACTIVE (Bitfield-Mask: 0x01) */ -#define PPB_AIRCR_SYSRESETREQ_Pos \ - (2UL) /*!< PPB AIRCR: SYSRESETREQ (Bit 2) */ -#define PPB_AIRCR_SYSRESETREQ_Msk \ - (0x4UL) /*!< PPB AIRCR: SYSRESETREQ (Bitfield-Mask: 0x01) */ -#define PPB_AIRCR_PRIGROUP_Pos \ - (8UL) /*!< PPB AIRCR: PRIGROUP (Bit 8) */ -#define PPB_AIRCR_PRIGROUP_Msk \ - (0x700UL) /*!< PPB AIRCR: PRIGROUP (Bitfield-Mask: 0x07) */ -#define PPB_AIRCR_ENDIANNESS_Pos \ - (15UL) /*!< PPB AIRCR: ENDIANNESS (Bit 15) */ -#define PPB_AIRCR_ENDIANNESS_Msk \ - (0x8000UL) /*!< PPB AIRCR: ENDIANNESS (Bitfield-Mask: 0x01) */ -#define PPB_AIRCR_VECTKEY_Pos \ - (16UL) /*!< PPB AIRCR: VECTKEY (Bit 16) */ -#define PPB_AIRCR_VECTKEY_Msk \ - (0xffff0000UL) /*!< PPB AIRCR: VECTKEY (Bitfield-Mask: 0xffff) */ - -/* ----------------------------------- PPB_SCR ---------------------------------- */ -#define PPB_SCR_SLEEPONEXIT_Pos \ - (1UL) /*!< PPB SCR: SLEEPONEXIT (Bit 1) */ -#define PPB_SCR_SLEEPONEXIT_Msk \ - (0x2UL) /*!< PPB SCR: SLEEPONEXIT (Bitfield-Mask: 0x01) */ -#define PPB_SCR_SLEEPDEEP_Pos \ - (2UL) /*!< PPB SCR: SLEEPDEEP (Bit 2) */ -#define PPB_SCR_SLEEPDEEP_Msk \ - (0x4UL) /*!< PPB SCR: SLEEPDEEP (Bitfield-Mask: 0x01) */ -#define PPB_SCR_SEVONPEND_Pos \ - (4UL) /*!< PPB SCR: SEVONPEND (Bit 4) */ -#define PPB_SCR_SEVONPEND_Msk \ - (0x10UL) /*!< PPB SCR: SEVONPEND (Bitfield-Mask: 0x01) */ - -/* ----------------------------------- PPB_CCR ---------------------------------- */ -#define PPB_CCR_NONBASETHRDENA_Pos \ - (0UL) /*!< PPB CCR: NONBASETHRDENA (Bit 0) */ -#define PPB_CCR_NONBASETHRDENA_Msk \ - (0x1UL) /*!< PPB CCR: NONBASETHRDENA (Bitfield-Mask: 0x01) */ -#define PPB_CCR_USERSETMPEND_Pos \ - (1UL) /*!< PPB CCR: USERSETMPEND (Bit 1) */ -#define PPB_CCR_USERSETMPEND_Msk \ - (0x2UL) /*!< PPB CCR: USERSETMPEND (Bitfield-Mask: 0x01) */ -#define PPB_CCR_UNALIGN_TRP_Pos \ - (3UL) /*!< PPB CCR: UNALIGN_TRP (Bit 3) */ -#define PPB_CCR_UNALIGN_TRP_Msk \ - (0x8UL) /*!< PPB CCR: UNALIGN_TRP (Bitfield-Mask: 0x01) */ -#define PPB_CCR_DIV_0_TRP_Pos \ - (4UL) /*!< PPB CCR: DIV_0_TRP (Bit 4) */ -#define PPB_CCR_DIV_0_TRP_Msk \ - (0x10UL) /*!< PPB CCR: DIV_0_TRP (Bitfield-Mask: 0x01) */ -#define PPB_CCR_BFHFNMIGN_Pos \ - (8UL) /*!< PPB CCR: BFHFNMIGN (Bit 8) */ -#define PPB_CCR_BFHFNMIGN_Msk \ - (0x100UL) /*!< PPB CCR: BFHFNMIGN (Bitfield-Mask: 0x01) */ -#define PPB_CCR_STKALIGN_Pos \ - (9UL) /*!< PPB CCR: STKALIGN (Bit 9) */ -#define PPB_CCR_STKALIGN_Msk \ - (0x200UL) /*!< PPB CCR: STKALIGN (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- PPB_SHPR1 --------------------------------- */ -#define PPB_SHPR1_PRI_4_Pos \ - (0UL) /*!< PPB SHPR1: PRI_4 (Bit 0) */ -#define PPB_SHPR1_PRI_4_Msk \ - (0xffUL) /*!< PPB SHPR1: PRI_4 (Bitfield-Mask: 0xff) */ -#define PPB_SHPR1_PRI_5_Pos \ - (8UL) /*!< PPB SHPR1: PRI_5 (Bit 8) */ -#define PPB_SHPR1_PRI_5_Msk \ - (0xff00UL) /*!< PPB SHPR1: PRI_5 (Bitfield-Mask: 0xff) */ -#define PPB_SHPR1_PRI_6_Pos \ - (16UL) /*!< PPB SHPR1: PRI_6 (Bit 16) */ -#define PPB_SHPR1_PRI_6_Msk \ - (0xff0000UL) /*!< PPB SHPR1: PRI_6 (Bitfield-Mask: 0xff) */ - -/* ---------------------------------- PPB_SHPR2 --------------------------------- */ -#define PPB_SHPR2_PRI_11_Pos \ - (24UL) /*!< PPB SHPR2: PRI_11 (Bit 24) */ -#define PPB_SHPR2_PRI_11_Msk \ - (0xff000000UL) /*!< PPB SHPR2: PRI_11 (Bitfield-Mask: 0xff) */ - -/* ---------------------------------- PPB_SHPR3 --------------------------------- */ -#define PPB_SHPR3_PRI_14_Pos \ - (16UL) /*!< PPB SHPR3: PRI_14 (Bit 16) */ -#define PPB_SHPR3_PRI_14_Msk \ - (0xff0000UL) /*!< PPB SHPR3: PRI_14 (Bitfield-Mask: 0xff) */ -#define PPB_SHPR3_PRI_15_Pos \ - (24UL) /*!< PPB SHPR3: PRI_15 (Bit 24) */ -#define PPB_SHPR3_PRI_15_Msk \ - (0xff000000UL) /*!< PPB SHPR3: PRI_15 (Bitfield-Mask: 0xff) */ - -/* ---------------------------------- PPB_SHCSR --------------------------------- */ -#define PPB_SHCSR_MEMFAULTACT_Pos \ - (0UL) /*!< PPB SHCSR: MEMFAULTACT (Bit 0) */ -#define PPB_SHCSR_MEMFAULTACT_Msk \ - (0x1UL) /*!< PPB SHCSR: MEMFAULTACT (Bitfield-Mask: 0x01) */ -#define PPB_SHCSR_BUSFAULTACT_Pos \ - (1UL) /*!< PPB SHCSR: BUSFAULTACT (Bit 1) */ -#define PPB_SHCSR_BUSFAULTACT_Msk \ - (0x2UL) /*!< PPB SHCSR: BUSFAULTACT (Bitfield-Mask: 0x01) */ -#define PPB_SHCSR_USGFAULTACT_Pos \ - (3UL) /*!< PPB SHCSR: USGFAULTACT (Bit 3) */ -#define PPB_SHCSR_USGFAULTACT_Msk \ - (0x8UL) /*!< PPB SHCSR: USGFAULTACT (Bitfield-Mask: 0x01) */ -#define PPB_SHCSR_SVCALLACT_Pos \ - (7UL) /*!< PPB SHCSR: SVCALLACT (Bit 7) */ -#define PPB_SHCSR_SVCALLACT_Msk \ - (0x80UL) /*!< PPB SHCSR: SVCALLACT (Bitfield-Mask: 0x01) */ -#define PPB_SHCSR_MONITORACT_Pos \ - (8UL) /*!< PPB SHCSR: MONITORACT (Bit 8) */ -#define PPB_SHCSR_MONITORACT_Msk \ - (0x100UL) /*!< PPB SHCSR: MONITORACT (Bitfield-Mask: 0x01) */ -#define PPB_SHCSR_PENDSVACT_Pos \ - (10UL) /*!< PPB SHCSR: PENDSVACT (Bit 10) */ -#define PPB_SHCSR_PENDSVACT_Msk \ - (0x400UL) /*!< PPB SHCSR: PENDSVACT (Bitfield-Mask: 0x01) */ -#define PPB_SHCSR_SYSTICKACT_Pos \ - (11UL) /*!< PPB SHCSR: SYSTICKACT (Bit 11) */ -#define PPB_SHCSR_SYSTICKACT_Msk \ - (0x800UL) /*!< PPB SHCSR: SYSTICKACT (Bitfield-Mask: 0x01) */ -#define PPB_SHCSR_USGFAULTPENDED_Pos \ - (12UL) /*!< PPB SHCSR: USGFAULTPENDED (Bit 12) */ -#define PPB_SHCSR_USGFAULTPENDED_Msk \ - (0x1000UL) /*!< PPB SHCSR: USGFAULTPENDED (Bitfield-Mask: 0x01) */ -#define PPB_SHCSR_MEMFAULTPENDED_Pos \ - (13UL) /*!< PPB SHCSR: MEMFAULTPENDED (Bit 13) */ -#define PPB_SHCSR_MEMFAULTPENDED_Msk \ - (0x2000UL) /*!< PPB SHCSR: MEMFAULTPENDED (Bitfield-Mask: 0x01) */ -#define PPB_SHCSR_BUSFAULTPENDED_Pos \ - (14UL) /*!< PPB SHCSR: BUSFAULTPENDED (Bit 14) */ -#define PPB_SHCSR_BUSFAULTPENDED_Msk \ - (0x4000UL) /*!< PPB SHCSR: BUSFAULTPENDED (Bitfield-Mask: 0x01) */ -#define PPB_SHCSR_SVCALLPENDED_Pos \ - (15UL) /*!< PPB SHCSR: SVCALLPENDED (Bit 15) */ -#define PPB_SHCSR_SVCALLPENDED_Msk \ - (0x8000UL) /*!< PPB SHCSR: SVCALLPENDED (Bitfield-Mask: 0x01) */ -#define PPB_SHCSR_MEMFAULTENA_Pos \ - (16UL) /*!< PPB SHCSR: MEMFAULTENA (Bit 16) */ -#define PPB_SHCSR_MEMFAULTENA_Msk \ - (0x10000UL) /*!< PPB SHCSR: MEMFAULTENA (Bitfield-Mask: 0x01) */ -#define PPB_SHCSR_BUSFAULTENA_Pos \ - (17UL) /*!< PPB SHCSR: BUSFAULTENA (Bit 17) */ -#define PPB_SHCSR_BUSFAULTENA_Msk \ - (0x20000UL) /*!< PPB SHCSR: BUSFAULTENA (Bitfield-Mask: 0x01) */ -#define PPB_SHCSR_USGFAULTENA_Pos \ - (18UL) /*!< PPB SHCSR: USGFAULTENA (Bit 18) */ -#define PPB_SHCSR_USGFAULTENA_Msk \ - (0x40000UL) /*!< PPB SHCSR: USGFAULTENA (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- PPB_CFSR ---------------------------------- */ -#define PPB_CFSR_IACCVIOL_Pos \ - (0UL) /*!< PPB CFSR: IACCVIOL (Bit 0) */ -#define PPB_CFSR_IACCVIOL_Msk \ - (0x1UL) /*!< PPB CFSR: IACCVIOL (Bitfield-Mask: 0x01) */ -#define PPB_CFSR_DACCVIOL_Pos \ - (1UL) /*!< PPB CFSR: DACCVIOL (Bit 1) */ -#define PPB_CFSR_DACCVIOL_Msk \ - (0x2UL) /*!< PPB CFSR: DACCVIOL (Bitfield-Mask: 0x01) */ -#define PPB_CFSR_MUNSTKERR_Pos \ - (3UL) /*!< PPB CFSR: MUNSTKERR (Bit 3) */ -#define PPB_CFSR_MUNSTKERR_Msk \ - (0x8UL) /*!< PPB CFSR: MUNSTKERR (Bitfield-Mask: 0x01) */ -#define PPB_CFSR_MSTKERR_Pos \ - (4UL) /*!< PPB CFSR: MSTKERR (Bit 4) */ -#define PPB_CFSR_MSTKERR_Msk \ - (0x10UL) /*!< PPB CFSR: MSTKERR (Bitfield-Mask: 0x01) */ -#define PPB_CFSR_MLSPERR_Pos \ - (5UL) /*!< PPB CFSR: MLSPERR (Bit 5) */ -#define PPB_CFSR_MLSPERR_Msk \ - (0x20UL) /*!< PPB CFSR: MLSPERR (Bitfield-Mask: 0x01) */ -#define PPB_CFSR_MMARVALID_Pos \ - (7UL) /*!< PPB CFSR: MMARVALID (Bit 7) */ -#define PPB_CFSR_MMARVALID_Msk \ - (0x80UL) /*!< PPB CFSR: MMARVALID (Bitfield-Mask: 0x01) */ -#define PPB_CFSR_IBUSERR_Pos \ - (8UL) /*!< PPB CFSR: IBUSERR (Bit 8) */ -#define PPB_CFSR_IBUSERR_Msk \ - (0x100UL) /*!< PPB CFSR: IBUSERR (Bitfield-Mask: 0x01) */ -#define PPB_CFSR_PRECISERR_Pos \ - (9UL) /*!< PPB CFSR: PRECISERR (Bit 9) */ -#define PPB_CFSR_PRECISERR_Msk \ - (0x200UL) /*!< PPB CFSR: PRECISERR (Bitfield-Mask: 0x01) */ -#define PPB_CFSR_IMPRECISERR_Pos \ - (10UL) /*!< PPB CFSR: IMPRECISERR (Bit 10) */ -#define PPB_CFSR_IMPRECISERR_Msk \ - (0x400UL) /*!< PPB CFSR: IMPRECISERR (Bitfield-Mask: 0x01) */ -#define PPB_CFSR_UNSTKERR_Pos \ - (11UL) /*!< PPB CFSR: UNSTKERR (Bit 11) */ -#define PPB_CFSR_UNSTKERR_Msk \ - (0x800UL) /*!< PPB CFSR: UNSTKERR (Bitfield-Mask: 0x01) */ -#define PPB_CFSR_STKERR_Pos \ - (12UL) /*!< PPB CFSR: STKERR (Bit 12) */ -#define PPB_CFSR_STKERR_Msk \ - (0x1000UL) /*!< PPB CFSR: STKERR (Bitfield-Mask: 0x01) */ -#define PPB_CFSR_LSPERR_Pos \ - (13UL) /*!< PPB CFSR: LSPERR (Bit 13) */ -#define PPB_CFSR_LSPERR_Msk \ - (0x2000UL) /*!< PPB CFSR: LSPERR (Bitfield-Mask: 0x01) */ -#define PPB_CFSR_BFARVALID_Pos \ - (15UL) /*!< PPB CFSR: BFARVALID (Bit 15) */ -#define PPB_CFSR_BFARVALID_Msk \ - (0x8000UL) /*!< PPB CFSR: BFARVALID (Bitfield-Mask: 0x01) */ -#define PPB_CFSR_UNDEFINSTR_Pos \ - (16UL) /*!< PPB CFSR: UNDEFINSTR (Bit 16) */ -#define PPB_CFSR_UNDEFINSTR_Msk \ - (0x10000UL) /*!< PPB CFSR: UNDEFINSTR (Bitfield-Mask: 0x01) */ -#define PPB_CFSR_INVSTATE_Pos \ - (17UL) /*!< PPB CFSR: INVSTATE (Bit 17) */ -#define PPB_CFSR_INVSTATE_Msk \ - (0x20000UL) /*!< PPB CFSR: INVSTATE (Bitfield-Mask: 0x01) */ -#define PPB_CFSR_INVPC_Pos \ - (18UL) /*!< PPB CFSR: INVPC (Bit 18) */ -#define PPB_CFSR_INVPC_Msk \ - (0x40000UL) /*!< PPB CFSR: INVPC (Bitfield-Mask: 0x01) */ -#define PPB_CFSR_NOCP_Pos (19UL) /*!< PPB CFSR: NOCP (Bit 19) */ -#define PPB_CFSR_NOCP_Msk \ - (0x80000UL) /*!< PPB CFSR: NOCP (Bitfield-Mask: 0x01) */ -#define PPB_CFSR_UNALIGNED_Pos \ - (24UL) /*!< PPB CFSR: UNALIGNED (Bit 24) */ -#define PPB_CFSR_UNALIGNED_Msk \ - (0x1000000UL) /*!< PPB CFSR: UNALIGNED (Bitfield-Mask: 0x01) */ -#define PPB_CFSR_DIVBYZERO_Pos \ - (25UL) /*!< PPB CFSR: DIVBYZERO (Bit 25) */ -#define PPB_CFSR_DIVBYZERO_Msk \ - (0x2000000UL) /*!< PPB CFSR: DIVBYZERO (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- PPB_HFSR ---------------------------------- */ -#define PPB_HFSR_VECTTBL_Pos \ - (1UL) /*!< PPB HFSR: VECTTBL (Bit 1) */ -#define PPB_HFSR_VECTTBL_Msk \ - (0x2UL) /*!< PPB HFSR: VECTTBL (Bitfield-Mask: 0x01) */ -#define PPB_HFSR_FORCED_Pos \ - (30UL) /*!< PPB HFSR: FORCED (Bit 30) */ -#define PPB_HFSR_FORCED_Msk \ - (0x40000000UL) /*!< PPB HFSR: FORCED (Bitfield-Mask: 0x01) */ -#define PPB_HFSR_DEBUGEVT_Pos \ - (31UL) /*!< PPB HFSR: DEBUGEVT (Bit 31) */ -#define PPB_HFSR_DEBUGEVT_Msk \ - (0x80000000UL) /*!< PPB HFSR: DEBUGEVT (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- PPB_MMFAR --------------------------------- */ -#define PPB_MMFAR_ADDRESS_Pos \ - (0UL) /*!< PPB MMFAR: ADDRESS (Bit 0) */ -#define PPB_MMFAR_ADDRESS_Msk \ - (0xffffffffUL) /*!< PPB MMFAR: ADDRESS (Bitfield-Mask: 0xffffffff) */ - -/* ---------------------------------- PPB_BFAR ---------------------------------- */ -#define PPB_BFAR_ADDRESS_Pos \ - (0UL) /*!< PPB BFAR: ADDRESS (Bit 0) */ -#define PPB_BFAR_ADDRESS_Msk \ - (0xffffffffUL) /*!< PPB BFAR: ADDRESS (Bitfield-Mask: 0xffffffff) */ - -/* ---------------------------------- PPB_AFSR ---------------------------------- */ -#define PPB_AFSR_VALUE_Pos (0UL) /*!< PPB AFSR: VALUE (Bit 0) */ -#define PPB_AFSR_VALUE_Msk \ - (0xffffffffUL) /*!< PPB AFSR: VALUE (Bitfield-Mask: 0xffffffff) */ - -/* ---------------------------------- PPB_CPACR --------------------------------- */ -#define PPB_CPACR_CP10_Pos \ - (20UL) /*!< PPB CPACR: CP10 (Bit 20) */ -#define PPB_CPACR_CP10_Msk \ - (0x300000UL) /*!< PPB CPACR: CP10 (Bitfield-Mask: 0x03) */ -#define PPB_CPACR_CP11_Pos \ - (22UL) /*!< PPB CPACR: CP11 (Bit 22) */ -#define PPB_CPACR_CP11_Msk \ - (0xc00000UL) /*!< PPB CPACR: CP11 (Bitfield-Mask: 0x03) */ - -/* -------------------------------- PPB_MPU_TYPE -------------------------------- */ -#define PPB_MPU_TYPE_SEPARATE_Pos \ - (0UL) /*!< PPB MPU_TYPE: SEPARATE (Bit 0) */ -#define PPB_MPU_TYPE_SEPARATE_Msk \ - (0x1UL) /*!< PPB MPU_TYPE: SEPARATE (Bitfield-Mask: 0x01) */ -#define PPB_MPU_TYPE_DREGION_Pos \ - (8UL) /*!< PPB MPU_TYPE: DREGION (Bit 8) */ -#define PPB_MPU_TYPE_DREGION_Msk \ - (0xff00UL) /*!< PPB MPU_TYPE: DREGION (Bitfield-Mask: 0xff) */ -#define PPB_MPU_TYPE_IREGION_Pos \ - (16UL) /*!< PPB MPU_TYPE: IREGION (Bit 16) */ -#define PPB_MPU_TYPE_IREGION_Msk \ - (0xff0000UL) /*!< PPB MPU_TYPE: IREGION (Bitfield-Mask: 0xff) */ - -/* -------------------------------- PPB_MPU_CTRL -------------------------------- */ -#define PPB_MPU_CTRL_ENABLE_Pos \ - (0UL) /*!< PPB MPU_CTRL: ENABLE (Bit 0) */ -#define PPB_MPU_CTRL_ENABLE_Msk \ - (0x1UL) /*!< PPB MPU_CTRL: ENABLE (Bitfield-Mask: 0x01) */ -#define PPB_MPU_CTRL_HFNMIENA_Pos \ - (1UL) /*!< PPB MPU_CTRL: HFNMIENA (Bit 1) */ -#define PPB_MPU_CTRL_HFNMIENA_Msk \ - (0x2UL) /*!< PPB MPU_CTRL: HFNMIENA (Bitfield-Mask: 0x01) */ -#define PPB_MPU_CTRL_PRIVDEFENA_Pos \ - (2UL) /*!< PPB MPU_CTRL: PRIVDEFENA (Bit 2) */ -#define PPB_MPU_CTRL_PRIVDEFENA_Msk \ - (0x4UL) /*!< PPB MPU_CTRL: PRIVDEFENA (Bitfield-Mask: 0x01) */ - -/* --------------------------------- PPB_MPU_RNR -------------------------------- */ -#define PPB_MPU_RNR_REGION_Pos \ - (0UL) /*!< PPB MPU_RNR: REGION (Bit 0) */ -#define PPB_MPU_RNR_REGION_Msk \ - (0xffUL) /*!< PPB MPU_RNR: REGION (Bitfield-Mask: 0xff) */ - -/* -------------------------------- PPB_MPU_RBAR -------------------------------- */ -#define PPB_MPU_RBAR_REGION_Pos \ - (0UL) /*!< PPB MPU_RBAR: REGION (Bit 0) */ -#define PPB_MPU_RBAR_REGION_Msk \ - (0xfUL) /*!< PPB MPU_RBAR: REGION (Bitfield-Mask: 0x0f) */ -#define PPB_MPU_RBAR_VALID_Pos \ - (4UL) /*!< PPB MPU_RBAR: VALID (Bit 4) */ -#define PPB_MPU_RBAR_VALID_Msk \ - (0x10UL) /*!< PPB MPU_RBAR: VALID (Bitfield-Mask: 0x01) */ -#define PPB_MPU_RBAR_ADDR_Pos \ - (9UL) /*!< PPB MPU_RBAR: ADDR (Bit 9) */ -#define PPB_MPU_RBAR_ADDR_Msk \ - (0xfffffe00UL) /*!< PPB MPU_RBAR: ADDR (Bitfield-Mask: 0x7fffff) */ - -/* -------------------------------- PPB_MPU_RASR -------------------------------- */ -#define PPB_MPU_RASR_ENABLE_Pos \ - (0UL) /*!< PPB MPU_RASR: ENABLE (Bit 0) */ -#define PPB_MPU_RASR_ENABLE_Msk \ - (0x1UL) /*!< PPB MPU_RASR: ENABLE (Bitfield-Mask: 0x01) */ -#define PPB_MPU_RASR_SIZE_Pos \ - (1UL) /*!< PPB MPU_RASR: SIZE (Bit 1) */ -#define PPB_MPU_RASR_SIZE_Msk \ - (0x3eUL) /*!< PPB MPU_RASR: SIZE (Bitfield-Mask: 0x1f) */ -#define PPB_MPU_RASR_SRD_Pos \ - (8UL) /*!< PPB MPU_RASR: SRD (Bit 8) */ -#define PPB_MPU_RASR_SRD_Msk \ - (0xff00UL) /*!< PPB MPU_RASR: SRD (Bitfield-Mask: 0xff) */ -#define PPB_MPU_RASR_B_Pos \ - (16UL) /*!< PPB MPU_RASR: B (Bit 16) */ -#define PPB_MPU_RASR_B_Msk \ - (0x10000UL) /*!< PPB MPU_RASR: B (Bitfield-Mask: 0x01) */ -#define PPB_MPU_RASR_C_Pos \ - (17UL) /*!< PPB MPU_RASR: C (Bit 17) */ -#define PPB_MPU_RASR_C_Msk \ - (0x20000UL) /*!< PPB MPU_RASR: C (Bitfield-Mask: 0x01) */ -#define PPB_MPU_RASR_S_Pos \ - (18UL) /*!< PPB MPU_RASR: S (Bit 18) */ -#define PPB_MPU_RASR_S_Msk \ - (0x40000UL) /*!< PPB MPU_RASR: S (Bitfield-Mask: 0x01) */ -#define PPB_MPU_RASR_TEX_Pos \ - (19UL) /*!< PPB MPU_RASR: TEX (Bit 19) */ -#define PPB_MPU_RASR_TEX_Msk \ - (0x380000UL) /*!< PPB MPU_RASR: TEX (Bitfield-Mask: 0x07) */ -#define PPB_MPU_RASR_AP_Pos \ - (24UL) /*!< PPB MPU_RASR: AP (Bit 24) */ -#define PPB_MPU_RASR_AP_Msk \ - (0x7000000UL) /*!< PPB MPU_RASR: AP (Bitfield-Mask: 0x07) */ -#define PPB_MPU_RASR_XN_Pos \ - (28UL) /*!< PPB MPU_RASR: XN (Bit 28) */ -#define PPB_MPU_RASR_XN_Msk \ - (0x10000000UL) /*!< PPB MPU_RASR: XN (Bitfield-Mask: 0x01) */ - -/* ------------------------------- PPB_MPU_RBAR_A1 ------------------------------ */ -#define PPB_MPU_RBAR_A1_REGION_Pos \ - (0UL) /*!< PPB MPU_RBAR_A1: REGION (Bit 0) */ -#define PPB_MPU_RBAR_A1_REGION_Msk \ - (0xfUL) /*!< PPB MPU_RBAR_A1: REGION (Bitfield-Mask: 0x0f) */ -#define PPB_MPU_RBAR_A1_VALID_Pos \ - (4UL) /*!< PPB MPU_RBAR_A1: VALID (Bit 4) */ -#define PPB_MPU_RBAR_A1_VALID_Msk \ - (0x10UL) /*!< PPB MPU_RBAR_A1: VALID (Bitfield-Mask: 0x01) */ -#define PPB_MPU_RBAR_A1_ADDR_Pos \ - (9UL) /*!< PPB MPU_RBAR_A1: ADDR (Bit 9) */ -#define PPB_MPU_RBAR_A1_ADDR_Msk \ - (0xfffffe00UL) /*!< PPB MPU_RBAR_A1: ADDR (Bitfield-Mask: 0x7fffff) */ - -/* ------------------------------- PPB_MPU_RASR_A1 ------------------------------ */ -#define PPB_MPU_RASR_A1_ENABLE_Pos \ - (0UL) /*!< PPB MPU_RASR_A1: ENABLE (Bit 0) */ -#define PPB_MPU_RASR_A1_ENABLE_Msk \ - (0x1UL) /*!< PPB MPU_RASR_A1: ENABLE (Bitfield-Mask: 0x01) */ -#define PPB_MPU_RASR_A1_SIZE_Pos \ - (1UL) /*!< PPB MPU_RASR_A1: SIZE (Bit 1) */ -#define PPB_MPU_RASR_A1_SIZE_Msk \ - (0x3eUL) /*!< PPB MPU_RASR_A1: SIZE (Bitfield-Mask: 0x1f) */ -#define PPB_MPU_RASR_A1_SRD_Pos \ - (8UL) /*!< PPB MPU_RASR_A1: SRD (Bit 8) */ -#define PPB_MPU_RASR_A1_SRD_Msk \ - (0xff00UL) /*!< PPB MPU_RASR_A1: SRD (Bitfield-Mask: 0xff) */ -#define PPB_MPU_RASR_A1_B_Pos \ - (16UL) /*!< PPB MPU_RASR_A1: B (Bit 16) */ -#define PPB_MPU_RASR_A1_B_Msk \ - (0x10000UL) /*!< PPB MPU_RASR_A1: B (Bitfield-Mask: 0x01) */ -#define PPB_MPU_RASR_A1_C_Pos \ - (17UL) /*!< PPB MPU_RASR_A1: C (Bit 17) */ -#define PPB_MPU_RASR_A1_C_Msk \ - (0x20000UL) /*!< PPB MPU_RASR_A1: C (Bitfield-Mask: 0x01) */ -#define PPB_MPU_RASR_A1_S_Pos \ - (18UL) /*!< PPB MPU_RASR_A1: S (Bit 18) */ -#define PPB_MPU_RASR_A1_S_Msk \ - (0x40000UL) /*!< PPB MPU_RASR_A1: S (Bitfield-Mask: 0x01) */ -#define PPB_MPU_RASR_A1_TEX_Pos \ - (19UL) /*!< PPB MPU_RASR_A1: TEX (Bit 19) */ -#define PPB_MPU_RASR_A1_TEX_Msk \ - (0x380000UL) /*!< PPB MPU_RASR_A1: TEX (Bitfield-Mask: 0x07) */ -#define PPB_MPU_RASR_A1_AP_Pos \ - (24UL) /*!< PPB MPU_RASR_A1: AP (Bit 24) */ -#define PPB_MPU_RASR_A1_AP_Msk \ - (0x7000000UL) /*!< PPB MPU_RASR_A1: AP (Bitfield-Mask: 0x07) */ -#define PPB_MPU_RASR_A1_XN_Pos \ - (28UL) /*!< PPB MPU_RASR_A1: XN (Bit 28) */ -#define PPB_MPU_RASR_A1_XN_Msk \ - (0x10000000UL) /*!< PPB MPU_RASR_A1: XN (Bitfield-Mask: 0x01) */ - -/* ------------------------------- PPB_MPU_RBAR_A2 ------------------------------ */ -#define PPB_MPU_RBAR_A2_REGION_Pos \ - (0UL) /*!< PPB MPU_RBAR_A2: REGION (Bit 0) */ -#define PPB_MPU_RBAR_A2_REGION_Msk \ - (0xfUL) /*!< PPB MPU_RBAR_A2: REGION (Bitfield-Mask: 0x0f) */ -#define PPB_MPU_RBAR_A2_VALID_Pos \ - (4UL) /*!< PPB MPU_RBAR_A2: VALID (Bit 4) */ -#define PPB_MPU_RBAR_A2_VALID_Msk \ - (0x10UL) /*!< PPB MPU_RBAR_A2: VALID (Bitfield-Mask: 0x01) */ -#define PPB_MPU_RBAR_A2_ADDR_Pos \ - (9UL) /*!< PPB MPU_RBAR_A2: ADDR (Bit 9) */ -#define PPB_MPU_RBAR_A2_ADDR_Msk \ - (0xfffffe00UL) /*!< PPB MPU_RBAR_A2: ADDR (Bitfield-Mask: 0x7fffff) */ - -/* ------------------------------- PPB_MPU_RASR_A2 ------------------------------ */ -#define PPB_MPU_RASR_A2_ENABLE_Pos \ - (0UL) /*!< PPB MPU_RASR_A2: ENABLE (Bit 0) */ -#define PPB_MPU_RASR_A2_ENABLE_Msk \ - (0x1UL) /*!< PPB MPU_RASR_A2: ENABLE (Bitfield-Mask: 0x01) */ -#define PPB_MPU_RASR_A2_SIZE_Pos \ - (1UL) /*!< PPB MPU_RASR_A2: SIZE (Bit 1) */ -#define PPB_MPU_RASR_A2_SIZE_Msk \ - (0x3eUL) /*!< PPB MPU_RASR_A2: SIZE (Bitfield-Mask: 0x1f) */ -#define PPB_MPU_RASR_A2_SRD_Pos \ - (8UL) /*!< PPB MPU_RASR_A2: SRD (Bit 8) */ -#define PPB_MPU_RASR_A2_SRD_Msk \ - (0xff00UL) /*!< PPB MPU_RASR_A2: SRD (Bitfield-Mask: 0xff) */ -#define PPB_MPU_RASR_A2_B_Pos \ - (16UL) /*!< PPB MPU_RASR_A2: B (Bit 16) */ -#define PPB_MPU_RASR_A2_B_Msk \ - (0x10000UL) /*!< PPB MPU_RASR_A2: B (Bitfield-Mask: 0x01) */ -#define PPB_MPU_RASR_A2_C_Pos \ - (17UL) /*!< PPB MPU_RASR_A2: C (Bit 17) */ -#define PPB_MPU_RASR_A2_C_Msk \ - (0x20000UL) /*!< PPB MPU_RASR_A2: C (Bitfield-Mask: 0x01) */ -#define PPB_MPU_RASR_A2_S_Pos \ - (18UL) /*!< PPB MPU_RASR_A2: S (Bit 18) */ -#define PPB_MPU_RASR_A2_S_Msk \ - (0x40000UL) /*!< PPB MPU_RASR_A2: S (Bitfield-Mask: 0x01) */ -#define PPB_MPU_RASR_A2_TEX_Pos \ - (19UL) /*!< PPB MPU_RASR_A2: TEX (Bit 19) */ -#define PPB_MPU_RASR_A2_TEX_Msk \ - (0x380000UL) /*!< PPB MPU_RASR_A2: TEX (Bitfield-Mask: 0x07) */ -#define PPB_MPU_RASR_A2_AP_Pos \ - (24UL) /*!< PPB MPU_RASR_A2: AP (Bit 24) */ -#define PPB_MPU_RASR_A2_AP_Msk \ - (0x7000000UL) /*!< PPB MPU_RASR_A2: AP (Bitfield-Mask: 0x07) */ -#define PPB_MPU_RASR_A2_XN_Pos \ - (28UL) /*!< PPB MPU_RASR_A2: XN (Bit 28) */ -#define PPB_MPU_RASR_A2_XN_Msk \ - (0x10000000UL) /*!< PPB MPU_RASR_A2: XN (Bitfield-Mask: 0x01) */ - -/* ------------------------------- PPB_MPU_RBAR_A3 ------------------------------ */ -#define PPB_MPU_RBAR_A3_REGION_Pos \ - (0UL) /*!< PPB MPU_RBAR_A3: REGION (Bit 0) */ -#define PPB_MPU_RBAR_A3_REGION_Msk \ - (0xfUL) /*!< PPB MPU_RBAR_A3: REGION (Bitfield-Mask: 0x0f) */ -#define PPB_MPU_RBAR_A3_VALID_Pos \ - (4UL) /*!< PPB MPU_RBAR_A3: VALID (Bit 4) */ -#define PPB_MPU_RBAR_A3_VALID_Msk \ - (0x10UL) /*!< PPB MPU_RBAR_A3: VALID (Bitfield-Mask: 0x01) */ -#define PPB_MPU_RBAR_A3_ADDR_Pos \ - (9UL) /*!< PPB MPU_RBAR_A3: ADDR (Bit 9) */ -#define PPB_MPU_RBAR_A3_ADDR_Msk \ - (0xfffffe00UL) /*!< PPB MPU_RBAR_A3: ADDR (Bitfield-Mask: 0x7fffff) */ - -/* ------------------------------- PPB_MPU_RASR_A3 ------------------------------ */ -#define PPB_MPU_RASR_A3_ENABLE_Pos \ - (0UL) /*!< PPB MPU_RASR_A3: ENABLE (Bit 0) */ -#define PPB_MPU_RASR_A3_ENABLE_Msk \ - (0x1UL) /*!< PPB MPU_RASR_A3: ENABLE (Bitfield-Mask: 0x01) */ -#define PPB_MPU_RASR_A3_SIZE_Pos \ - (1UL) /*!< PPB MPU_RASR_A3: SIZE (Bit 1) */ -#define PPB_MPU_RASR_A3_SIZE_Msk \ - (0x3eUL) /*!< PPB MPU_RASR_A3: SIZE (Bitfield-Mask: 0x1f) */ -#define PPB_MPU_RASR_A3_SRD_Pos \ - (8UL) /*!< PPB MPU_RASR_A3: SRD (Bit 8) */ -#define PPB_MPU_RASR_A3_SRD_Msk \ - (0xff00UL) /*!< PPB MPU_RASR_A3: SRD (Bitfield-Mask: 0xff) */ -#define PPB_MPU_RASR_A3_B_Pos \ - (16UL) /*!< PPB MPU_RASR_A3: B (Bit 16) */ -#define PPB_MPU_RASR_A3_B_Msk \ - (0x10000UL) /*!< PPB MPU_RASR_A3: B (Bitfield-Mask: 0x01) */ -#define PPB_MPU_RASR_A3_C_Pos \ - (17UL) /*!< PPB MPU_RASR_A3: C (Bit 17) */ -#define PPB_MPU_RASR_A3_C_Msk \ - (0x20000UL) /*!< PPB MPU_RASR_A3: C (Bitfield-Mask: 0x01) */ -#define PPB_MPU_RASR_A3_S_Pos \ - (18UL) /*!< PPB MPU_RASR_A3: S (Bit 18) */ -#define PPB_MPU_RASR_A3_S_Msk \ - (0x40000UL) /*!< PPB MPU_RASR_A3: S (Bitfield-Mask: 0x01) */ -#define PPB_MPU_RASR_A3_TEX_Pos \ - (19UL) /*!< PPB MPU_RASR_A3: TEX (Bit 19) */ -#define PPB_MPU_RASR_A3_TEX_Msk \ - (0x380000UL) /*!< PPB MPU_RASR_A3: TEX (Bitfield-Mask: 0x07) */ -#define PPB_MPU_RASR_A3_AP_Pos \ - (24UL) /*!< PPB MPU_RASR_A3: AP (Bit 24) */ -#define PPB_MPU_RASR_A3_AP_Msk \ - (0x7000000UL) /*!< PPB MPU_RASR_A3: AP (Bitfield-Mask: 0x07) */ -#define PPB_MPU_RASR_A3_XN_Pos \ - (28UL) /*!< PPB MPU_RASR_A3: XN (Bit 28) */ -#define PPB_MPU_RASR_A3_XN_Msk \ - (0x10000000UL) /*!< PPB MPU_RASR_A3: XN (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- PPB_STIR ---------------------------------- */ -#define PPB_STIR_INTID_Pos (0UL) /*!< PPB STIR: INTID (Bit 0) */ -#define PPB_STIR_INTID_Msk \ - (0x1ffUL) /*!< PPB STIR: INTID (Bitfield-Mask: 0x1ff) */ - -/* ---------------------------------- PPB_FPCCR --------------------------------- */ -#define PPB_FPCCR_LSPACT_Pos \ - (0UL) /*!< PPB FPCCR: LSPACT (Bit 0) */ -#define PPB_FPCCR_LSPACT_Msk \ - (0x1UL) /*!< PPB FPCCR: LSPACT (Bitfield-Mask: 0x01) */ -#define PPB_FPCCR_USER_Pos (1UL) /*!< PPB FPCCR: USER (Bit 1) */ -#define PPB_FPCCR_USER_Msk \ - (0x2UL) /*!< PPB FPCCR: USER (Bitfield-Mask: 0x01) */ -#define PPB_FPCCR_THREAD_Pos \ - (3UL) /*!< PPB FPCCR: THREAD (Bit 3) */ -#define PPB_FPCCR_THREAD_Msk \ - (0x8UL) /*!< PPB FPCCR: THREAD (Bitfield-Mask: 0x01) */ -#define PPB_FPCCR_HFRDY_Pos \ - (4UL) /*!< PPB FPCCR: HFRDY (Bit 4) */ -#define PPB_FPCCR_HFRDY_Msk \ - (0x10UL) /*!< PPB FPCCR: HFRDY (Bitfield-Mask: 0x01) */ -#define PPB_FPCCR_MMRDY_Pos \ - (5UL) /*!< PPB FPCCR: MMRDY (Bit 5) */ -#define PPB_FPCCR_MMRDY_Msk \ - (0x20UL) /*!< PPB FPCCR: MMRDY (Bitfield-Mask: 0x01) */ -#define PPB_FPCCR_BFRDY_Pos \ - (6UL) /*!< PPB FPCCR: BFRDY (Bit 6) */ -#define PPB_FPCCR_BFRDY_Msk \ - (0x40UL) /*!< PPB FPCCR: BFRDY (Bitfield-Mask: 0x01) */ -#define PPB_FPCCR_MONRDY_Pos \ - (8UL) /*!< PPB FPCCR: MONRDY (Bit 8) */ -#define PPB_FPCCR_MONRDY_Msk \ - (0x100UL) /*!< PPB FPCCR: MONRDY (Bitfield-Mask: 0x01) */ -#define PPB_FPCCR_LSPEN_Pos \ - (30UL) /*!< PPB FPCCR: LSPEN (Bit 30) */ -#define PPB_FPCCR_LSPEN_Msk \ - (0x40000000UL) /*!< PPB FPCCR: LSPEN (Bitfield-Mask: 0x01) */ -#define PPB_FPCCR_ASPEN_Pos \ - (31UL) /*!< PPB FPCCR: ASPEN (Bit 31) */ -#define PPB_FPCCR_ASPEN_Msk \ - (0x80000000UL) /*!< PPB FPCCR: ASPEN (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- PPB_FPCAR --------------------------------- */ -#define PPB_FPCAR_ADDRESS_Pos \ - (3UL) /*!< PPB FPCAR: ADDRESS (Bit 3) */ -#define PPB_FPCAR_ADDRESS_Msk \ - (0xfffffff8UL) /*!< PPB FPCAR: ADDRESS (Bitfield-Mask: 0x1fffffff) */ - -/* --------------------------------- PPB_FPDSCR --------------------------------- */ -#define PPB_FPDSCR_RMode_Pos \ - (22UL) /*!< PPB FPDSCR: RMode (Bit 22) */ -#define PPB_FPDSCR_RMode_Msk \ - (0xc00000UL) /*!< PPB FPDSCR: RMode (Bitfield-Mask: 0x03) */ -#define PPB_FPDSCR_FZ_Pos (24UL) /*!< PPB FPDSCR: FZ (Bit 24) */ -#define PPB_FPDSCR_FZ_Msk \ - (0x1000000UL) /*!< PPB FPDSCR: FZ (Bitfield-Mask: 0x01) */ -#define PPB_FPDSCR_DN_Pos (25UL) /*!< PPB FPDSCR: DN (Bit 25) */ -#define PPB_FPDSCR_DN_Msk \ - (0x2000000UL) /*!< PPB FPDSCR: DN (Bitfield-Mask: 0x01) */ -#define PPB_FPDSCR_AHP_Pos \ - (26UL) /*!< PPB FPDSCR: AHP (Bit 26) */ -#define PPB_FPDSCR_AHP_Msk \ - (0x4000000UL) /*!< PPB FPDSCR: AHP (Bitfield-Mask: 0x01) */ - -/* ================================================================================ */ -/* ================ struct 'DLR' Position & Mask ================ */ -/* ================================================================================ */ - -/* --------------------------------- DLR_OVRSTAT -------------------------------- */ -#define DLR_OVRSTAT_LN0_Pos \ - (0UL) /*!< DLR OVRSTAT: LN0 (Bit 0) */ -#define DLR_OVRSTAT_LN0_Msk \ - (0x1UL) /*!< DLR OVRSTAT: LN0 (Bitfield-Mask: 0x01) */ -#define DLR_OVRSTAT_LN1_Pos \ - (1UL) /*!< DLR OVRSTAT: LN1 (Bit 1) */ -#define DLR_OVRSTAT_LN1_Msk \ - (0x2UL) /*!< DLR OVRSTAT: LN1 (Bitfield-Mask: 0x01) */ -#define DLR_OVRSTAT_LN2_Pos \ - (2UL) /*!< DLR OVRSTAT: LN2 (Bit 2) */ -#define DLR_OVRSTAT_LN2_Msk \ - (0x4UL) /*!< DLR OVRSTAT: LN2 (Bitfield-Mask: 0x01) */ -#define DLR_OVRSTAT_LN3_Pos \ - (3UL) /*!< DLR OVRSTAT: LN3 (Bit 3) */ -#define DLR_OVRSTAT_LN3_Msk \ - (0x8UL) /*!< DLR OVRSTAT: LN3 (Bitfield-Mask: 0x01) */ -#define DLR_OVRSTAT_LN4_Pos \ - (4UL) /*!< DLR OVRSTAT: LN4 (Bit 4) */ -#define DLR_OVRSTAT_LN4_Msk \ - (0x10UL) /*!< DLR OVRSTAT: LN4 (Bitfield-Mask: 0x01) */ -#define DLR_OVRSTAT_LN5_Pos \ - (5UL) /*!< DLR OVRSTAT: LN5 (Bit 5) */ -#define DLR_OVRSTAT_LN5_Msk \ - (0x20UL) /*!< DLR OVRSTAT: LN5 (Bitfield-Mask: 0x01) */ -#define DLR_OVRSTAT_LN6_Pos \ - (6UL) /*!< DLR OVRSTAT: LN6 (Bit 6) */ -#define DLR_OVRSTAT_LN6_Msk \ - (0x40UL) /*!< DLR OVRSTAT: LN6 (Bitfield-Mask: 0x01) */ -#define DLR_OVRSTAT_LN7_Pos \ - (7UL) /*!< DLR OVRSTAT: LN7 (Bit 7) */ -#define DLR_OVRSTAT_LN7_Msk \ - (0x80UL) /*!< DLR OVRSTAT: LN7 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- DLR_OVRCLR --------------------------------- */ -#define DLR_OVRCLR_LN0_Pos (0UL) /*!< DLR OVRCLR: LN0 (Bit 0) */ -#define DLR_OVRCLR_LN0_Msk \ - (0x1UL) /*!< DLR OVRCLR: LN0 (Bitfield-Mask: 0x01) */ -#define DLR_OVRCLR_LN1_Pos (1UL) /*!< DLR OVRCLR: LN1 (Bit 1) */ -#define DLR_OVRCLR_LN1_Msk \ - (0x2UL) /*!< DLR OVRCLR: LN1 (Bitfield-Mask: 0x01) */ -#define DLR_OVRCLR_LN2_Pos (2UL) /*!< DLR OVRCLR: LN2 (Bit 2) */ -#define DLR_OVRCLR_LN2_Msk \ - (0x4UL) /*!< DLR OVRCLR: LN2 (Bitfield-Mask: 0x01) */ -#define DLR_OVRCLR_LN3_Pos (3UL) /*!< DLR OVRCLR: LN3 (Bit 3) */ -#define DLR_OVRCLR_LN3_Msk \ - (0x8UL) /*!< DLR OVRCLR: LN3 (Bitfield-Mask: 0x01) */ -#define DLR_OVRCLR_LN4_Pos (4UL) /*!< DLR OVRCLR: LN4 (Bit 4) */ -#define DLR_OVRCLR_LN4_Msk \ - (0x10UL) /*!< DLR OVRCLR: LN4 (Bitfield-Mask: 0x01) */ -#define DLR_OVRCLR_LN5_Pos (5UL) /*!< DLR OVRCLR: LN5 (Bit 5) */ -#define DLR_OVRCLR_LN5_Msk \ - (0x20UL) /*!< DLR OVRCLR: LN5 (Bitfield-Mask: 0x01) */ -#define DLR_OVRCLR_LN6_Pos (6UL) /*!< DLR OVRCLR: LN6 (Bit 6) */ -#define DLR_OVRCLR_LN6_Msk \ - (0x40UL) /*!< DLR OVRCLR: LN6 (Bitfield-Mask: 0x01) */ -#define DLR_OVRCLR_LN7_Pos (7UL) /*!< DLR OVRCLR: LN7 (Bit 7) */ -#define DLR_OVRCLR_LN7_Msk \ - (0x80UL) /*!< DLR OVRCLR: LN7 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- DLR_SRSEL0 --------------------------------- */ -#define DLR_SRSEL0_RS0_Pos (0UL) /*!< DLR SRSEL0: RS0 (Bit 0) */ -#define DLR_SRSEL0_RS0_Msk \ - (0xfUL) /*!< DLR SRSEL0: RS0 (Bitfield-Mask: 0x0f) */ -#define DLR_SRSEL0_RS1_Pos (4UL) /*!< DLR SRSEL0: RS1 (Bit 4) */ -#define DLR_SRSEL0_RS1_Msk \ - (0xf0UL) /*!< DLR SRSEL0: RS1 (Bitfield-Mask: 0x0f) */ -#define DLR_SRSEL0_RS2_Pos (8UL) /*!< DLR SRSEL0: RS2 (Bit 8) */ -#define DLR_SRSEL0_RS2_Msk \ - (0xf00UL) /*!< DLR SRSEL0: RS2 (Bitfield-Mask: 0x0f) */ -#define DLR_SRSEL0_RS3_Pos \ - (12UL) /*!< DLR SRSEL0: RS3 (Bit 12) */ -#define DLR_SRSEL0_RS3_Msk \ - (0xf000UL) /*!< DLR SRSEL0: RS3 (Bitfield-Mask: 0x0f) */ -#define DLR_SRSEL0_RS4_Pos \ - (16UL) /*!< DLR SRSEL0: RS4 (Bit 16) */ -#define DLR_SRSEL0_RS4_Msk \ - (0xf0000UL) /*!< DLR SRSEL0: RS4 (Bitfield-Mask: 0x0f) */ -#define DLR_SRSEL0_RS5_Pos \ - (20UL) /*!< DLR SRSEL0: RS5 (Bit 20) */ -#define DLR_SRSEL0_RS5_Msk \ - (0xf00000UL) /*!< DLR SRSEL0: RS5 (Bitfield-Mask: 0x0f) */ -#define DLR_SRSEL0_RS6_Pos \ - (24UL) /*!< DLR SRSEL0: RS6 (Bit 24) */ -#define DLR_SRSEL0_RS6_Msk \ - (0xf000000UL) /*!< DLR SRSEL0: RS6 (Bitfield-Mask: 0x0f) */ -#define DLR_SRSEL0_RS7_Pos \ - (28UL) /*!< DLR SRSEL0: RS7 (Bit 28) */ -#define DLR_SRSEL0_RS7_Msk \ - (0xf0000000UL) /*!< DLR SRSEL0: RS7 (Bitfield-Mask: 0x0f) */ - -/* ---------------------------------- DLR_LNEN ---------------------------------- */ -#define DLR_LNEN_LN0_Pos (0UL) /*!< DLR LNEN: LN0 (Bit 0) */ -#define DLR_LNEN_LN0_Msk (0x1UL) /*!< DLR LNEN: LN0 (Bitfield-Mask: 0x01) */ -#define DLR_LNEN_LN1_Pos (1UL) /*!< DLR LNEN: LN1 (Bit 1) */ -#define DLR_LNEN_LN1_Msk (0x2UL) /*!< DLR LNEN: LN1 (Bitfield-Mask: 0x01) */ -#define DLR_LNEN_LN2_Pos (2UL) /*!< DLR LNEN: LN2 (Bit 2) */ -#define DLR_LNEN_LN2_Msk (0x4UL) /*!< DLR LNEN: LN2 (Bitfield-Mask: 0x01) */ -#define DLR_LNEN_LN3_Pos (3UL) /*!< DLR LNEN: LN3 (Bit 3) */ -#define DLR_LNEN_LN3_Msk (0x8UL) /*!< DLR LNEN: LN3 (Bitfield-Mask: 0x01) */ -#define DLR_LNEN_LN4_Pos (4UL) /*!< DLR LNEN: LN4 (Bit 4) */ -#define DLR_LNEN_LN4_Msk \ - (0x10UL) /*!< DLR LNEN: LN4 (Bitfield-Mask: 0x01) */ -#define DLR_LNEN_LN5_Pos (5UL) /*!< DLR LNEN: LN5 (Bit 5) */ -#define DLR_LNEN_LN5_Msk \ - (0x20UL) /*!< DLR LNEN: LN5 (Bitfield-Mask: 0x01) */ -#define DLR_LNEN_LN6_Pos (6UL) /*!< DLR LNEN: LN6 (Bit 6) */ -#define DLR_LNEN_LN6_Msk \ - (0x40UL) /*!< DLR LNEN: LN6 (Bitfield-Mask: 0x01) */ -#define DLR_LNEN_LN7_Pos (7UL) /*!< DLR LNEN: LN7 (Bit 7) */ -#define DLR_LNEN_LN7_Msk \ - (0x80UL) /*!< DLR LNEN: LN7 (Bitfield-Mask: 0x01) */ - -/* ================================================================================ */ -/* ================ Group 'ERU' Position & Mask ================ */ -/* ================================================================================ */ - -/* --------------------------------- ERU_EXISEL --------------------------------- */ -#define ERU_EXISEL_EXS0A_Pos \ - (0UL) /*!< ERU EXISEL: EXS0A (Bit 0) */ -#define ERU_EXISEL_EXS0A_Msk \ - (0x3UL) /*!< ERU EXISEL: EXS0A (Bitfield-Mask: 0x03) */ -#define ERU_EXISEL_EXS0B_Pos \ - (2UL) /*!< ERU EXISEL: EXS0B (Bit 2) */ -#define ERU_EXISEL_EXS0B_Msk \ - (0xcUL) /*!< ERU EXISEL: EXS0B (Bitfield-Mask: 0x03) */ -#define ERU_EXISEL_EXS1A_Pos \ - (4UL) /*!< ERU EXISEL: EXS1A (Bit 4) */ -#define ERU_EXISEL_EXS1A_Msk \ - (0x30UL) /*!< ERU EXISEL: EXS1A (Bitfield-Mask: 0x03) */ -#define ERU_EXISEL_EXS1B_Pos \ - (6UL) /*!< ERU EXISEL: EXS1B (Bit 6) */ -#define ERU_EXISEL_EXS1B_Msk \ - (0xc0UL) /*!< ERU EXISEL: EXS1B (Bitfield-Mask: 0x03) */ -#define ERU_EXISEL_EXS2A_Pos \ - (8UL) /*!< ERU EXISEL: EXS2A (Bit 8) */ -#define ERU_EXISEL_EXS2A_Msk \ - (0x300UL) /*!< ERU EXISEL: EXS2A (Bitfield-Mask: 0x03) */ -#define ERU_EXISEL_EXS2B_Pos \ - (10UL) /*!< ERU EXISEL: EXS2B (Bit 10) */ -#define ERU_EXISEL_EXS2B_Msk \ - (0xc00UL) /*!< ERU EXISEL: EXS2B (Bitfield-Mask: 0x03) */ -#define ERU_EXISEL_EXS3A_Pos \ - (12UL) /*!< ERU EXISEL: EXS3A (Bit 12) */ -#define ERU_EXISEL_EXS3A_Msk \ - (0x3000UL) /*!< ERU EXISEL: EXS3A (Bitfield-Mask: 0x03) */ -#define ERU_EXISEL_EXS3B_Pos \ - (14UL) /*!< ERU EXISEL: EXS3B (Bit 14) */ -#define ERU_EXISEL_EXS3B_Msk \ - (0xc000UL) /*!< ERU EXISEL: EXS3B (Bitfield-Mask: 0x03) */ - -/* --------------------------------- ERU_EXICON --------------------------------- */ -#define ERU_EXICON_PE_Pos (0UL) /*!< ERU EXICON: PE (Bit 0) */ -#define ERU_EXICON_PE_Msk \ - (0x1UL) /*!< ERU EXICON: PE (Bitfield-Mask: 0x01) */ -#define ERU_EXICON_LD_Pos (1UL) /*!< ERU EXICON: LD (Bit 1) */ -#define ERU_EXICON_LD_Msk \ - (0x2UL) /*!< ERU EXICON: LD (Bitfield-Mask: 0x01) */ -#define ERU_EXICON_RE_Pos (2UL) /*!< ERU EXICON: RE (Bit 2) */ -#define ERU_EXICON_RE_Msk \ - (0x4UL) /*!< ERU EXICON: RE (Bitfield-Mask: 0x01) */ -#define ERU_EXICON_FE_Pos (3UL) /*!< ERU EXICON: FE (Bit 3) */ -#define ERU_EXICON_FE_Msk \ - (0x8UL) /*!< ERU EXICON: FE (Bitfield-Mask: 0x01) */ -#define ERU_EXICON_OCS_Pos (4UL) /*!< ERU EXICON: OCS (Bit 4) */ -#define ERU_EXICON_OCS_Msk \ - (0x70UL) /*!< ERU EXICON: OCS (Bitfield-Mask: 0x07) */ -#define ERU_EXICON_FL_Pos (7UL) /*!< ERU EXICON: FL (Bit 7) */ -#define ERU_EXICON_FL_Msk \ - (0x80UL) /*!< ERU EXICON: FL (Bitfield-Mask: 0x01) */ -#define ERU_EXICON_SS_Pos (8UL) /*!< ERU EXICON: SS (Bit 8) */ -#define ERU_EXICON_SS_Msk \ - (0x300UL) /*!< ERU EXICON: SS (Bitfield-Mask: 0x03) */ -#define ERU_EXICON_NA_Pos (10UL) /*!< ERU EXICON: NA (Bit 10) */ -#define ERU_EXICON_NA_Msk \ - (0x400UL) /*!< ERU EXICON: NA (Bitfield-Mask: 0x01) */ -#define ERU_EXICON_NB_Pos (11UL) /*!< ERU EXICON: NB (Bit 11) */ -#define ERU_EXICON_NB_Msk \ - (0x800UL) /*!< ERU EXICON: NB (Bitfield-Mask: 0x01) */ - -/* --------------------------------- ERU_EXOCON --------------------------------- */ -#define ERU_EXOCON_ISS_Pos (0UL) /*!< ERU EXOCON: ISS (Bit 0) */ -#define ERU_EXOCON_ISS_Msk \ - (0x3UL) /*!< ERU EXOCON: ISS (Bitfield-Mask: 0x03) */ -#define ERU_EXOCON_GEEN_Pos \ - (2UL) /*!< ERU EXOCON: GEEN (Bit 2) */ -#define ERU_EXOCON_GEEN_Msk \ - (0x4UL) /*!< ERU EXOCON: GEEN (Bitfield-Mask: 0x01) */ -#define ERU_EXOCON_PDR_Pos (3UL) /*!< ERU EXOCON: PDR (Bit 3) */ -#define ERU_EXOCON_PDR_Msk \ - (0x8UL) /*!< ERU EXOCON: PDR (Bitfield-Mask: 0x01) */ -#define ERU_EXOCON_GP_Pos (4UL) /*!< ERU EXOCON: GP (Bit 4) */ -#define ERU_EXOCON_GP_Msk \ - (0x30UL) /*!< ERU EXOCON: GP (Bitfield-Mask: 0x03) */ -#define ERU_EXOCON_IPEN0_Pos \ - (12UL) /*!< ERU EXOCON: IPEN0 (Bit 12) */ -#define ERU_EXOCON_IPEN0_Msk \ - (0x1000UL) /*!< ERU EXOCON: IPEN0 (Bitfield-Mask: 0x01) */ -#define ERU_EXOCON_IPEN1_Pos \ - (13UL) /*!< ERU EXOCON: IPEN1 (Bit 13) */ -#define ERU_EXOCON_IPEN1_Msk \ - (0x2000UL) /*!< ERU EXOCON: IPEN1 (Bitfield-Mask: 0x01) */ -#define ERU_EXOCON_IPEN2_Pos \ - (14UL) /*!< ERU EXOCON: IPEN2 (Bit 14) */ -#define ERU_EXOCON_IPEN2_Msk \ - (0x4000UL) /*!< ERU EXOCON: IPEN2 (Bitfield-Mask: 0x01) */ -#define ERU_EXOCON_IPEN3_Pos \ - (15UL) /*!< ERU EXOCON: IPEN3 (Bit 15) */ -#define ERU_EXOCON_IPEN3_Msk \ - (0x8000UL) /*!< ERU EXOCON: IPEN3 (Bitfield-Mask: 0x01) */ - -/* ================================================================================ */ -/* ================ struct 'GPDMA0' Position & Mask ================ */ -/* ================================================================================ */ - -/* -------------------------------- GPDMA0_RAWTFR ------------------------------- */ -#define GPDMA0_RAWTFR_CH0_Pos \ - (0UL) /*!< GPDMA0 RAWTFR: CH0 (Bit 0) */ -#define GPDMA0_RAWTFR_CH0_Msk \ - (0x1UL) /*!< GPDMA0 RAWTFR: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWTFR_CH1_Pos \ - (1UL) /*!< GPDMA0 RAWTFR: CH1 (Bit 1) */ -#define GPDMA0_RAWTFR_CH1_Msk \ - (0x2UL) /*!< GPDMA0 RAWTFR: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWTFR_CH2_Pos \ - (2UL) /*!< GPDMA0 RAWTFR: CH2 (Bit 2) */ -#define GPDMA0_RAWTFR_CH2_Msk \ - (0x4UL) /*!< GPDMA0 RAWTFR: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWTFR_CH3_Pos \ - (3UL) /*!< GPDMA0 RAWTFR: CH3 (Bit 3) */ -#define GPDMA0_RAWTFR_CH3_Msk \ - (0x8UL) /*!< GPDMA0 RAWTFR: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWTFR_CH4_Pos \ - (4UL) /*!< GPDMA0 RAWTFR: CH4 (Bit 4) */ -#define GPDMA0_RAWTFR_CH4_Msk \ - (0x10UL) /*!< GPDMA0 RAWTFR: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWTFR_CH5_Pos \ - (5UL) /*!< GPDMA0 RAWTFR: CH5 (Bit 5) */ -#define GPDMA0_RAWTFR_CH5_Msk \ - (0x20UL) /*!< GPDMA0 RAWTFR: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWTFR_CH6_Pos \ - (6UL) /*!< GPDMA0 RAWTFR: CH6 (Bit 6) */ -#define GPDMA0_RAWTFR_CH6_Msk \ - (0x40UL) /*!< GPDMA0 RAWTFR: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWTFR_CH7_Pos \ - (7UL) /*!< GPDMA0 RAWTFR: CH7 (Bit 7) */ -#define GPDMA0_RAWTFR_CH7_Msk \ - (0x80UL) /*!< GPDMA0 RAWTFR: CH7 (Bitfield-Mask: 0x01) */ - -/* ------------------------------- GPDMA0_RAWBLOCK ------------------------------ */ -#define GPDMA0_RAWBLOCK_CH0_Pos \ - (0UL) /*!< GPDMA0 RAWBLOCK: CH0 (Bit 0) */ -#define GPDMA0_RAWBLOCK_CH0_Msk \ - (0x1UL) /*!< GPDMA0 RAWBLOCK: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWBLOCK_CH1_Pos \ - (1UL) /*!< GPDMA0 RAWBLOCK: CH1 (Bit 1) */ -#define GPDMA0_RAWBLOCK_CH1_Msk \ - (0x2UL) /*!< GPDMA0 RAWBLOCK: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWBLOCK_CH2_Pos \ - (2UL) /*!< GPDMA0 RAWBLOCK: CH2 (Bit 2) */ -#define GPDMA0_RAWBLOCK_CH2_Msk \ - (0x4UL) /*!< GPDMA0 RAWBLOCK: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWBLOCK_CH3_Pos \ - (3UL) /*!< GPDMA0 RAWBLOCK: CH3 (Bit 3) */ -#define GPDMA0_RAWBLOCK_CH3_Msk \ - (0x8UL) /*!< GPDMA0 RAWBLOCK: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWBLOCK_CH4_Pos \ - (4UL) /*!< GPDMA0 RAWBLOCK: CH4 (Bit 4) */ -#define GPDMA0_RAWBLOCK_CH4_Msk \ - (0x10UL) /*!< GPDMA0 RAWBLOCK: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWBLOCK_CH5_Pos \ - (5UL) /*!< GPDMA0 RAWBLOCK: CH5 (Bit 5) */ -#define GPDMA0_RAWBLOCK_CH5_Msk \ - (0x20UL) /*!< GPDMA0 RAWBLOCK: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWBLOCK_CH6_Pos \ - (6UL) /*!< GPDMA0 RAWBLOCK: CH6 (Bit 6) */ -#define GPDMA0_RAWBLOCK_CH6_Msk \ - (0x40UL) /*!< GPDMA0 RAWBLOCK: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWBLOCK_CH7_Pos \ - (7UL) /*!< GPDMA0 RAWBLOCK: CH7 (Bit 7) */ -#define GPDMA0_RAWBLOCK_CH7_Msk \ - (0x80UL) /*!< GPDMA0 RAWBLOCK: CH7 (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPDMA0_RAWSRCTRAN ----------------------------- */ -#define GPDMA0_RAWSRCTRAN_CH0_Pos \ - (0UL) /*!< GPDMA0 RAWSRCTRAN: CH0 (Bit 0) */ -#define GPDMA0_RAWSRCTRAN_CH0_Msk \ - (0x1UL) /*!< GPDMA0 RAWSRCTRAN: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWSRCTRAN_CH1_Pos \ - (1UL) /*!< GPDMA0 RAWSRCTRAN: CH1 (Bit 1) */ -#define GPDMA0_RAWSRCTRAN_CH1_Msk \ - (0x2UL) /*!< GPDMA0 RAWSRCTRAN: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWSRCTRAN_CH2_Pos \ - (2UL) /*!< GPDMA0 RAWSRCTRAN: CH2 (Bit 2) */ -#define GPDMA0_RAWSRCTRAN_CH2_Msk \ - (0x4UL) /*!< GPDMA0 RAWSRCTRAN: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWSRCTRAN_CH3_Pos \ - (3UL) /*!< GPDMA0 RAWSRCTRAN: CH3 (Bit 3) */ -#define GPDMA0_RAWSRCTRAN_CH3_Msk \ - (0x8UL) /*!< GPDMA0 RAWSRCTRAN: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWSRCTRAN_CH4_Pos \ - (4UL) /*!< GPDMA0 RAWSRCTRAN: CH4 (Bit 4) */ -#define GPDMA0_RAWSRCTRAN_CH4_Msk \ - (0x10UL) /*!< GPDMA0 RAWSRCTRAN: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWSRCTRAN_CH5_Pos \ - (5UL) /*!< GPDMA0 RAWSRCTRAN: CH5 (Bit 5) */ -#define GPDMA0_RAWSRCTRAN_CH5_Msk \ - (0x20UL) /*!< GPDMA0 RAWSRCTRAN: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWSRCTRAN_CH6_Pos \ - (6UL) /*!< GPDMA0 RAWSRCTRAN: CH6 (Bit 6) */ -#define GPDMA0_RAWSRCTRAN_CH6_Msk \ - (0x40UL) /*!< GPDMA0 RAWSRCTRAN: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWSRCTRAN_CH7_Pos \ - (7UL) /*!< GPDMA0 RAWSRCTRAN: CH7 (Bit 7) */ -#define GPDMA0_RAWSRCTRAN_CH7_Msk \ - (0x80UL) /*!< GPDMA0 RAWSRCTRAN: CH7 (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPDMA0_RAWDSTTRAN ----------------------------- */ -#define GPDMA0_RAWDSTTRAN_CH0_Pos \ - (0UL) /*!< GPDMA0 RAWDSTTRAN: CH0 (Bit 0) */ -#define GPDMA0_RAWDSTTRAN_CH0_Msk \ - (0x1UL) /*!< GPDMA0 RAWDSTTRAN: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWDSTTRAN_CH1_Pos \ - (1UL) /*!< GPDMA0 RAWDSTTRAN: CH1 (Bit 1) */ -#define GPDMA0_RAWDSTTRAN_CH1_Msk \ - (0x2UL) /*!< GPDMA0 RAWDSTTRAN: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWDSTTRAN_CH2_Pos \ - (2UL) /*!< GPDMA0 RAWDSTTRAN: CH2 (Bit 2) */ -#define GPDMA0_RAWDSTTRAN_CH2_Msk \ - (0x4UL) /*!< GPDMA0 RAWDSTTRAN: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWDSTTRAN_CH3_Pos \ - (3UL) /*!< GPDMA0 RAWDSTTRAN: CH3 (Bit 3) */ -#define GPDMA0_RAWDSTTRAN_CH3_Msk \ - (0x8UL) /*!< GPDMA0 RAWDSTTRAN: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWDSTTRAN_CH4_Pos \ - (4UL) /*!< GPDMA0 RAWDSTTRAN: CH4 (Bit 4) */ -#define GPDMA0_RAWDSTTRAN_CH4_Msk \ - (0x10UL) /*!< GPDMA0 RAWDSTTRAN: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWDSTTRAN_CH5_Pos \ - (5UL) /*!< GPDMA0 RAWDSTTRAN: CH5 (Bit 5) */ -#define GPDMA0_RAWDSTTRAN_CH5_Msk \ - (0x20UL) /*!< GPDMA0 RAWDSTTRAN: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWDSTTRAN_CH6_Pos \ - (6UL) /*!< GPDMA0 RAWDSTTRAN: CH6 (Bit 6) */ -#define GPDMA0_RAWDSTTRAN_CH6_Msk \ - (0x40UL) /*!< GPDMA0 RAWDSTTRAN: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWDSTTRAN_CH7_Pos \ - (7UL) /*!< GPDMA0 RAWDSTTRAN: CH7 (Bit 7) */ -#define GPDMA0_RAWDSTTRAN_CH7_Msk \ - (0x80UL) /*!< GPDMA0 RAWDSTTRAN: CH7 (Bitfield-Mask: 0x01) */ - -/* -------------------------------- GPDMA0_RAWERR ------------------------------- */ -#define GPDMA0_RAWERR_CH0_Pos \ - (0UL) /*!< GPDMA0 RAWERR: CH0 (Bit 0) */ -#define GPDMA0_RAWERR_CH0_Msk \ - (0x1UL) /*!< GPDMA0 RAWERR: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWERR_CH1_Pos \ - (1UL) /*!< GPDMA0 RAWERR: CH1 (Bit 1) */ -#define GPDMA0_RAWERR_CH1_Msk \ - (0x2UL) /*!< GPDMA0 RAWERR: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWERR_CH2_Pos \ - (2UL) /*!< GPDMA0 RAWERR: CH2 (Bit 2) */ -#define GPDMA0_RAWERR_CH2_Msk \ - (0x4UL) /*!< GPDMA0 RAWERR: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWERR_CH3_Pos \ - (3UL) /*!< GPDMA0 RAWERR: CH3 (Bit 3) */ -#define GPDMA0_RAWERR_CH3_Msk \ - (0x8UL) /*!< GPDMA0 RAWERR: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWERR_CH4_Pos \ - (4UL) /*!< GPDMA0 RAWERR: CH4 (Bit 4) */ -#define GPDMA0_RAWERR_CH4_Msk \ - (0x10UL) /*!< GPDMA0 RAWERR: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWERR_CH5_Pos \ - (5UL) /*!< GPDMA0 RAWERR: CH5 (Bit 5) */ -#define GPDMA0_RAWERR_CH5_Msk \ - (0x20UL) /*!< GPDMA0 RAWERR: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWERR_CH6_Pos \ - (6UL) /*!< GPDMA0 RAWERR: CH6 (Bit 6) */ -#define GPDMA0_RAWERR_CH6_Msk \ - (0x40UL) /*!< GPDMA0 RAWERR: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWERR_CH7_Pos \ - (7UL) /*!< GPDMA0 RAWERR: CH7 (Bit 7) */ -#define GPDMA0_RAWERR_CH7_Msk \ - (0x80UL) /*!< GPDMA0 RAWERR: CH7 (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPDMA0_STATUSTFR ------------------------------ */ -#define GPDMA0_STATUSTFR_CH0_Pos \ - (0UL) /*!< GPDMA0 STATUSTFR: CH0 (Bit 0) */ -#define GPDMA0_STATUSTFR_CH0_Msk \ - (0x1UL) /*!< GPDMA0 STATUSTFR: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSTFR_CH1_Pos \ - (1UL) /*!< GPDMA0 STATUSTFR: CH1 (Bit 1) */ -#define GPDMA0_STATUSTFR_CH1_Msk \ - (0x2UL) /*!< GPDMA0 STATUSTFR: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSTFR_CH2_Pos \ - (2UL) /*!< GPDMA0 STATUSTFR: CH2 (Bit 2) */ -#define GPDMA0_STATUSTFR_CH2_Msk \ - (0x4UL) /*!< GPDMA0 STATUSTFR: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSTFR_CH3_Pos \ - (3UL) /*!< GPDMA0 STATUSTFR: CH3 (Bit 3) */ -#define GPDMA0_STATUSTFR_CH3_Msk \ - (0x8UL) /*!< GPDMA0 STATUSTFR: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSTFR_CH4_Pos \ - (4UL) /*!< GPDMA0 STATUSTFR: CH4 (Bit 4) */ -#define GPDMA0_STATUSTFR_CH4_Msk \ - (0x10UL) /*!< GPDMA0 STATUSTFR: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSTFR_CH5_Pos \ - (5UL) /*!< GPDMA0 STATUSTFR: CH5 (Bit 5) */ -#define GPDMA0_STATUSTFR_CH5_Msk \ - (0x20UL) /*!< GPDMA0 STATUSTFR: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSTFR_CH6_Pos \ - (6UL) /*!< GPDMA0 STATUSTFR: CH6 (Bit 6) */ -#define GPDMA0_STATUSTFR_CH6_Msk \ - (0x40UL) /*!< GPDMA0 STATUSTFR: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSTFR_CH7_Pos \ - (7UL) /*!< GPDMA0 STATUSTFR: CH7 (Bit 7) */ -#define GPDMA0_STATUSTFR_CH7_Msk \ - (0x80UL) /*!< GPDMA0 STATUSTFR: CH7 (Bitfield-Mask: 0x01) */ - -/* ----------------------------- GPDMA0_STATUSBLOCK ----------------------------- */ -#define GPDMA0_STATUSBLOCK_CH0_Pos \ - (0UL) /*!< GPDMA0 STATUSBLOCK: CH0 (Bit 0) */ -#define GPDMA0_STATUSBLOCK_CH0_Msk \ - (0x1UL) /*!< GPDMA0 STATUSBLOCK: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSBLOCK_CH1_Pos \ - (1UL) /*!< GPDMA0 STATUSBLOCK: CH1 (Bit 1) */ -#define GPDMA0_STATUSBLOCK_CH1_Msk \ - (0x2UL) /*!< GPDMA0 STATUSBLOCK: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSBLOCK_CH2_Pos \ - (2UL) /*!< GPDMA0 STATUSBLOCK: CH2 (Bit 2) */ -#define GPDMA0_STATUSBLOCK_CH2_Msk \ - (0x4UL) /*!< GPDMA0 STATUSBLOCK: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSBLOCK_CH3_Pos \ - (3UL) /*!< GPDMA0 STATUSBLOCK: CH3 (Bit 3) */ -#define GPDMA0_STATUSBLOCK_CH3_Msk \ - (0x8UL) /*!< GPDMA0 STATUSBLOCK: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSBLOCK_CH4_Pos \ - (4UL) /*!< GPDMA0 STATUSBLOCK: CH4 (Bit 4) */ -#define GPDMA0_STATUSBLOCK_CH4_Msk \ - (0x10UL) /*!< GPDMA0 STATUSBLOCK: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSBLOCK_CH5_Pos \ - (5UL) /*!< GPDMA0 STATUSBLOCK: CH5 (Bit 5) */ -#define GPDMA0_STATUSBLOCK_CH5_Msk \ - (0x20UL) /*!< GPDMA0 STATUSBLOCK: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSBLOCK_CH6_Pos \ - (6UL) /*!< GPDMA0 STATUSBLOCK: CH6 (Bit 6) */ -#define GPDMA0_STATUSBLOCK_CH6_Msk \ - (0x40UL) /*!< GPDMA0 STATUSBLOCK: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSBLOCK_CH7_Pos \ - (7UL) /*!< GPDMA0 STATUSBLOCK: CH7 (Bit 7) */ -#define GPDMA0_STATUSBLOCK_CH7_Msk \ - (0x80UL) /*!< GPDMA0 STATUSBLOCK: CH7 (Bitfield-Mask: 0x01) */ - -/* ---------------------------- GPDMA0_STATUSSRCTRAN ---------------------------- */ -#define GPDMA0_STATUSSRCTRAN_CH0_Pos \ - (0UL) /*!< GPDMA0 STATUSSRCTRAN: CH0 (Bit 0) */ -#define GPDMA0_STATUSSRCTRAN_CH0_Msk \ - (0x1UL) /*!< GPDMA0 STATUSSRCTRAN: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSSRCTRAN_CH1_Pos \ - (1UL) /*!< GPDMA0 STATUSSRCTRAN: CH1 (Bit 1) */ -#define GPDMA0_STATUSSRCTRAN_CH1_Msk \ - (0x2UL) /*!< GPDMA0 STATUSSRCTRAN: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSSRCTRAN_CH2_Pos \ - (2UL) /*!< GPDMA0 STATUSSRCTRAN: CH2 (Bit 2) */ -#define GPDMA0_STATUSSRCTRAN_CH2_Msk \ - (0x4UL) /*!< GPDMA0 STATUSSRCTRAN: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSSRCTRAN_CH3_Pos \ - (3UL) /*!< GPDMA0 STATUSSRCTRAN: CH3 (Bit 3) */ -#define GPDMA0_STATUSSRCTRAN_CH3_Msk \ - (0x8UL) /*!< GPDMA0 STATUSSRCTRAN: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSSRCTRAN_CH4_Pos \ - (4UL) /*!< GPDMA0 STATUSSRCTRAN: CH4 (Bit 4) */ -#define GPDMA0_STATUSSRCTRAN_CH4_Msk \ - (0x10UL) /*!< GPDMA0 STATUSSRCTRAN: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSSRCTRAN_CH5_Pos \ - (5UL) /*!< GPDMA0 STATUSSRCTRAN: CH5 (Bit 5) */ -#define GPDMA0_STATUSSRCTRAN_CH5_Msk \ - (0x20UL) /*!< GPDMA0 STATUSSRCTRAN: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSSRCTRAN_CH6_Pos \ - (6UL) /*!< GPDMA0 STATUSSRCTRAN: CH6 (Bit 6) */ -#define GPDMA0_STATUSSRCTRAN_CH6_Msk \ - (0x40UL) /*!< GPDMA0 STATUSSRCTRAN: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSSRCTRAN_CH7_Pos \ - (7UL) /*!< GPDMA0 STATUSSRCTRAN: CH7 (Bit 7) */ -#define GPDMA0_STATUSSRCTRAN_CH7_Msk \ - (0x80UL) /*!< GPDMA0 STATUSSRCTRAN: CH7 (Bitfield-Mask: 0x01) */ - -/* ---------------------------- GPDMA0_STATUSDSTTRAN ---------------------------- */ -#define GPDMA0_STATUSDSTTRAN_CH0_Pos \ - (0UL) /*!< GPDMA0 STATUSDSTTRAN: CH0 (Bit 0) */ -#define GPDMA0_STATUSDSTTRAN_CH0_Msk \ - (0x1UL) /*!< GPDMA0 STATUSDSTTRAN: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSDSTTRAN_CH1_Pos \ - (1UL) /*!< GPDMA0 STATUSDSTTRAN: CH1 (Bit 1) */ -#define GPDMA0_STATUSDSTTRAN_CH1_Msk \ - (0x2UL) /*!< GPDMA0 STATUSDSTTRAN: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSDSTTRAN_CH2_Pos \ - (2UL) /*!< GPDMA0 STATUSDSTTRAN: CH2 (Bit 2) */ -#define GPDMA0_STATUSDSTTRAN_CH2_Msk \ - (0x4UL) /*!< GPDMA0 STATUSDSTTRAN: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSDSTTRAN_CH3_Pos \ - (3UL) /*!< GPDMA0 STATUSDSTTRAN: CH3 (Bit 3) */ -#define GPDMA0_STATUSDSTTRAN_CH3_Msk \ - (0x8UL) /*!< GPDMA0 STATUSDSTTRAN: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSDSTTRAN_CH4_Pos \ - (4UL) /*!< GPDMA0 STATUSDSTTRAN: CH4 (Bit 4) */ -#define GPDMA0_STATUSDSTTRAN_CH4_Msk \ - (0x10UL) /*!< GPDMA0 STATUSDSTTRAN: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSDSTTRAN_CH5_Pos \ - (5UL) /*!< GPDMA0 STATUSDSTTRAN: CH5 (Bit 5) */ -#define GPDMA0_STATUSDSTTRAN_CH5_Msk \ - (0x20UL) /*!< GPDMA0 STATUSDSTTRAN: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSDSTTRAN_CH6_Pos \ - (6UL) /*!< GPDMA0 STATUSDSTTRAN: CH6 (Bit 6) */ -#define GPDMA0_STATUSDSTTRAN_CH6_Msk \ - (0x40UL) /*!< GPDMA0 STATUSDSTTRAN: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSDSTTRAN_CH7_Pos \ - (7UL) /*!< GPDMA0 STATUSDSTTRAN: CH7 (Bit 7) */ -#define GPDMA0_STATUSDSTTRAN_CH7_Msk \ - (0x80UL) /*!< GPDMA0 STATUSDSTTRAN: CH7 (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPDMA0_STATUSERR ------------------------------ */ -#define GPDMA0_STATUSERR_CH0_Pos \ - (0UL) /*!< GPDMA0 STATUSERR: CH0 (Bit 0) */ -#define GPDMA0_STATUSERR_CH0_Msk \ - (0x1UL) /*!< GPDMA0 STATUSERR: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSERR_CH1_Pos \ - (1UL) /*!< GPDMA0 STATUSERR: CH1 (Bit 1) */ -#define GPDMA0_STATUSERR_CH1_Msk \ - (0x2UL) /*!< GPDMA0 STATUSERR: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSERR_CH2_Pos \ - (2UL) /*!< GPDMA0 STATUSERR: CH2 (Bit 2) */ -#define GPDMA0_STATUSERR_CH2_Msk \ - (0x4UL) /*!< GPDMA0 STATUSERR: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSERR_CH3_Pos \ - (3UL) /*!< GPDMA0 STATUSERR: CH3 (Bit 3) */ -#define GPDMA0_STATUSERR_CH3_Msk \ - (0x8UL) /*!< GPDMA0 STATUSERR: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSERR_CH4_Pos \ - (4UL) /*!< GPDMA0 STATUSERR: CH4 (Bit 4) */ -#define GPDMA0_STATUSERR_CH4_Msk \ - (0x10UL) /*!< GPDMA0 STATUSERR: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSERR_CH5_Pos \ - (5UL) /*!< GPDMA0 STATUSERR: CH5 (Bit 5) */ -#define GPDMA0_STATUSERR_CH5_Msk \ - (0x20UL) /*!< GPDMA0 STATUSERR: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSERR_CH6_Pos \ - (6UL) /*!< GPDMA0 STATUSERR: CH6 (Bit 6) */ -#define GPDMA0_STATUSERR_CH6_Msk \ - (0x40UL) /*!< GPDMA0 STATUSERR: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSERR_CH7_Pos \ - (7UL) /*!< GPDMA0 STATUSERR: CH7 (Bit 7) */ -#define GPDMA0_STATUSERR_CH7_Msk \ - (0x80UL) /*!< GPDMA0 STATUSERR: CH7 (Bitfield-Mask: 0x01) */ - -/* ------------------------------- GPDMA0_MASKTFR ------------------------------- */ -#define GPDMA0_MASKTFR_CH0_Pos \ - (0UL) /*!< GPDMA0 MASKTFR: CH0 (Bit 0) */ -#define GPDMA0_MASKTFR_CH0_Msk \ - (0x1UL) /*!< GPDMA0 MASKTFR: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKTFR_CH1_Pos \ - (1UL) /*!< GPDMA0 MASKTFR: CH1 (Bit 1) */ -#define GPDMA0_MASKTFR_CH1_Msk \ - (0x2UL) /*!< GPDMA0 MASKTFR: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKTFR_CH2_Pos \ - (2UL) /*!< GPDMA0 MASKTFR: CH2 (Bit 2) */ -#define GPDMA0_MASKTFR_CH2_Msk \ - (0x4UL) /*!< GPDMA0 MASKTFR: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKTFR_CH3_Pos \ - (3UL) /*!< GPDMA0 MASKTFR: CH3 (Bit 3) */ -#define GPDMA0_MASKTFR_CH3_Msk \ - (0x8UL) /*!< GPDMA0 MASKTFR: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKTFR_CH4_Pos \ - (4UL) /*!< GPDMA0 MASKTFR: CH4 (Bit 4) */ -#define GPDMA0_MASKTFR_CH4_Msk \ - (0x10UL) /*!< GPDMA0 MASKTFR: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKTFR_CH5_Pos \ - (5UL) /*!< GPDMA0 MASKTFR: CH5 (Bit 5) */ -#define GPDMA0_MASKTFR_CH5_Msk \ - (0x20UL) /*!< GPDMA0 MASKTFR: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKTFR_CH6_Pos \ - (6UL) /*!< GPDMA0 MASKTFR: CH6 (Bit 6) */ -#define GPDMA0_MASKTFR_CH6_Msk \ - (0x40UL) /*!< GPDMA0 MASKTFR: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKTFR_CH7_Pos \ - (7UL) /*!< GPDMA0 MASKTFR: CH7 (Bit 7) */ -#define GPDMA0_MASKTFR_CH7_Msk \ - (0x80UL) /*!< GPDMA0 MASKTFR: CH7 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKTFR_WE_CH0_Pos \ - (8UL) /*!< GPDMA0 MASKTFR: WE_CH0 (Bit 8) */ -#define GPDMA0_MASKTFR_WE_CH0_Msk \ - (0x100UL) /*!< GPDMA0 MASKTFR: WE_CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKTFR_WE_CH1_Pos \ - (9UL) /*!< GPDMA0 MASKTFR: WE_CH1 (Bit 9) */ -#define GPDMA0_MASKTFR_WE_CH1_Msk \ - (0x200UL) /*!< GPDMA0 MASKTFR: WE_CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKTFR_WE_CH2_Pos \ - (10UL) /*!< GPDMA0 MASKTFR: WE_CH2 (Bit 10) */ -#define GPDMA0_MASKTFR_WE_CH2_Msk \ - (0x400UL) /*!< GPDMA0 MASKTFR: WE_CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKTFR_WE_CH3_Pos \ - (11UL) /*!< GPDMA0 MASKTFR: WE_CH3 (Bit 11) */ -#define GPDMA0_MASKTFR_WE_CH3_Msk \ - (0x800UL) /*!< GPDMA0 MASKTFR: WE_CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKTFR_WE_CH4_Pos \ - (12UL) /*!< GPDMA0 MASKTFR: WE_CH4 (Bit 12) */ -#define GPDMA0_MASKTFR_WE_CH4_Msk \ - (0x1000UL) /*!< GPDMA0 MASKTFR: WE_CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKTFR_WE_CH5_Pos \ - (13UL) /*!< GPDMA0 MASKTFR: WE_CH5 (Bit 13) */ -#define GPDMA0_MASKTFR_WE_CH5_Msk \ - (0x2000UL) /*!< GPDMA0 MASKTFR: WE_CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKTFR_WE_CH6_Pos \ - (14UL) /*!< GPDMA0 MASKTFR: WE_CH6 (Bit 14) */ -#define GPDMA0_MASKTFR_WE_CH6_Msk \ - (0x4000UL) /*!< GPDMA0 MASKTFR: WE_CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKTFR_WE_CH7_Pos \ - (15UL) /*!< GPDMA0 MASKTFR: WE_CH7 (Bit 15) */ -#define GPDMA0_MASKTFR_WE_CH7_Msk \ - (0x8000UL) /*!< GPDMA0 MASKTFR: WE_CH7 (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPDMA0_MASKBLOCK ------------------------------ */ -#define GPDMA0_MASKBLOCK_CH0_Pos \ - (0UL) /*!< GPDMA0 MASKBLOCK: CH0 (Bit 0) */ -#define GPDMA0_MASKBLOCK_CH0_Msk \ - (0x1UL) /*!< GPDMA0 MASKBLOCK: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKBLOCK_CH1_Pos \ - (1UL) /*!< GPDMA0 MASKBLOCK: CH1 (Bit 1) */ -#define GPDMA0_MASKBLOCK_CH1_Msk \ - (0x2UL) /*!< GPDMA0 MASKBLOCK: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKBLOCK_CH2_Pos \ - (2UL) /*!< GPDMA0 MASKBLOCK: CH2 (Bit 2) */ -#define GPDMA0_MASKBLOCK_CH2_Msk \ - (0x4UL) /*!< GPDMA0 MASKBLOCK: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKBLOCK_CH3_Pos \ - (3UL) /*!< GPDMA0 MASKBLOCK: CH3 (Bit 3) */ -#define GPDMA0_MASKBLOCK_CH3_Msk \ - (0x8UL) /*!< GPDMA0 MASKBLOCK: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKBLOCK_CH4_Pos \ - (4UL) /*!< GPDMA0 MASKBLOCK: CH4 (Bit 4) */ -#define GPDMA0_MASKBLOCK_CH4_Msk \ - (0x10UL) /*!< GPDMA0 MASKBLOCK: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKBLOCK_CH5_Pos \ - (5UL) /*!< GPDMA0 MASKBLOCK: CH5 (Bit 5) */ -#define GPDMA0_MASKBLOCK_CH5_Msk \ - (0x20UL) /*!< GPDMA0 MASKBLOCK: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKBLOCK_CH6_Pos \ - (6UL) /*!< GPDMA0 MASKBLOCK: CH6 (Bit 6) */ -#define GPDMA0_MASKBLOCK_CH6_Msk \ - (0x40UL) /*!< GPDMA0 MASKBLOCK: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKBLOCK_CH7_Pos \ - (7UL) /*!< GPDMA0 MASKBLOCK: CH7 (Bit 7) */ -#define GPDMA0_MASKBLOCK_CH7_Msk \ - (0x80UL) /*!< GPDMA0 MASKBLOCK: CH7 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKBLOCK_WE_CH0_Pos \ - (8UL) /*!< GPDMA0 MASKBLOCK: WE_CH0 (Bit 8) */ -#define GPDMA0_MASKBLOCK_WE_CH0_Msk \ - (0x100UL) /*!< GPDMA0 MASKBLOCK: WE_CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKBLOCK_WE_CH1_Pos \ - (9UL) /*!< GPDMA0 MASKBLOCK: WE_CH1 (Bit 9) */ -#define GPDMA0_MASKBLOCK_WE_CH1_Msk \ - (0x200UL) /*!< GPDMA0 MASKBLOCK: WE_CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKBLOCK_WE_CH2_Pos \ - (10UL) /*!< GPDMA0 MASKBLOCK: WE_CH2 (Bit 10) */ -#define GPDMA0_MASKBLOCK_WE_CH2_Msk \ - (0x400UL) /*!< GPDMA0 MASKBLOCK: WE_CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKBLOCK_WE_CH3_Pos \ - (11UL) /*!< GPDMA0 MASKBLOCK: WE_CH3 (Bit 11) */ -#define GPDMA0_MASKBLOCK_WE_CH3_Msk \ - (0x800UL) /*!< GPDMA0 MASKBLOCK: WE_CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKBLOCK_WE_CH4_Pos \ - (12UL) /*!< GPDMA0 MASKBLOCK: WE_CH4 (Bit 12) */ -#define GPDMA0_MASKBLOCK_WE_CH4_Msk \ - (0x1000UL) /*!< GPDMA0 MASKBLOCK: WE_CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKBLOCK_WE_CH5_Pos \ - (13UL) /*!< GPDMA0 MASKBLOCK: WE_CH5 (Bit 13) */ -#define GPDMA0_MASKBLOCK_WE_CH5_Msk \ - (0x2000UL) /*!< GPDMA0 MASKBLOCK: WE_CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKBLOCK_WE_CH6_Pos \ - (14UL) /*!< GPDMA0 MASKBLOCK: WE_CH6 (Bit 14) */ -#define GPDMA0_MASKBLOCK_WE_CH6_Msk \ - (0x4000UL) /*!< GPDMA0 MASKBLOCK: WE_CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKBLOCK_WE_CH7_Pos \ - (15UL) /*!< GPDMA0 MASKBLOCK: WE_CH7 (Bit 15) */ -#define GPDMA0_MASKBLOCK_WE_CH7_Msk \ - (0x8000UL) /*!< GPDMA0 MASKBLOCK: WE_CH7 (Bitfield-Mask: 0x01) */ - -/* ----------------------------- GPDMA0_MASKSRCTRAN ----------------------------- */ -#define GPDMA0_MASKSRCTRAN_CH0_Pos \ - (0UL) /*!< GPDMA0 MASKSRCTRAN: CH0 (Bit 0) */ -#define GPDMA0_MASKSRCTRAN_CH0_Msk \ - (0x1UL) /*!< GPDMA0 MASKSRCTRAN: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKSRCTRAN_CH1_Pos \ - (1UL) /*!< GPDMA0 MASKSRCTRAN: CH1 (Bit 1) */ -#define GPDMA0_MASKSRCTRAN_CH1_Msk \ - (0x2UL) /*!< GPDMA0 MASKSRCTRAN: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKSRCTRAN_CH2_Pos \ - (2UL) /*!< GPDMA0 MASKSRCTRAN: CH2 (Bit 2) */ -#define GPDMA0_MASKSRCTRAN_CH2_Msk \ - (0x4UL) /*!< GPDMA0 MASKSRCTRAN: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKSRCTRAN_CH3_Pos \ - (3UL) /*!< GPDMA0 MASKSRCTRAN: CH3 (Bit 3) */ -#define GPDMA0_MASKSRCTRAN_CH3_Msk \ - (0x8UL) /*!< GPDMA0 MASKSRCTRAN: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKSRCTRAN_CH4_Pos \ - (4UL) /*!< GPDMA0 MASKSRCTRAN: CH4 (Bit 4) */ -#define GPDMA0_MASKSRCTRAN_CH4_Msk \ - (0x10UL) /*!< GPDMA0 MASKSRCTRAN: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKSRCTRAN_CH5_Pos \ - (5UL) /*!< GPDMA0 MASKSRCTRAN: CH5 (Bit 5) */ -#define GPDMA0_MASKSRCTRAN_CH5_Msk \ - (0x20UL) /*!< GPDMA0 MASKSRCTRAN: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKSRCTRAN_CH6_Pos \ - (6UL) /*!< GPDMA0 MASKSRCTRAN: CH6 (Bit 6) */ -#define GPDMA0_MASKSRCTRAN_CH6_Msk \ - (0x40UL) /*!< GPDMA0 MASKSRCTRAN: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKSRCTRAN_CH7_Pos \ - (7UL) /*!< GPDMA0 MASKSRCTRAN: CH7 (Bit 7) */ -#define GPDMA0_MASKSRCTRAN_CH7_Msk \ - (0x80UL) /*!< GPDMA0 MASKSRCTRAN: CH7 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKSRCTRAN_WE_CH0_Pos \ - (8UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH0 (Bit 8) */ -#define GPDMA0_MASKSRCTRAN_WE_CH0_Msk \ - (0x100UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKSRCTRAN_WE_CH1_Pos \ - (9UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH1 (Bit 9) */ -#define GPDMA0_MASKSRCTRAN_WE_CH1_Msk \ - (0x200UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKSRCTRAN_WE_CH2_Pos \ - (10UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH2 (Bit 10) */ -#define GPDMA0_MASKSRCTRAN_WE_CH2_Msk \ - (0x400UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKSRCTRAN_WE_CH3_Pos \ - (11UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH3 (Bit 11) */ -#define GPDMA0_MASKSRCTRAN_WE_CH3_Msk \ - (0x800UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKSRCTRAN_WE_CH4_Pos \ - (12UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH4 (Bit 12) */ -#define GPDMA0_MASKSRCTRAN_WE_CH4_Msk \ - (0x1000UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKSRCTRAN_WE_CH5_Pos \ - (13UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH5 (Bit 13) */ -#define GPDMA0_MASKSRCTRAN_WE_CH5_Msk \ - (0x2000UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKSRCTRAN_WE_CH6_Pos \ - (14UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH6 (Bit 14) */ -#define GPDMA0_MASKSRCTRAN_WE_CH6_Msk \ - (0x4000UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKSRCTRAN_WE_CH7_Pos \ - (15UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH7 (Bit 15) */ -#define GPDMA0_MASKSRCTRAN_WE_CH7_Msk \ - (0x8000UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH7 (Bitfield-Mask: 0x01) */ - -/* ----------------------------- GPDMA0_MASKDSTTRAN ----------------------------- */ -#define GPDMA0_MASKDSTTRAN_CH0_Pos \ - (0UL) /*!< GPDMA0 MASKDSTTRAN: CH0 (Bit 0) */ -#define GPDMA0_MASKDSTTRAN_CH0_Msk \ - (0x1UL) /*!< GPDMA0 MASKDSTTRAN: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKDSTTRAN_CH1_Pos \ - (1UL) /*!< GPDMA0 MASKDSTTRAN: CH1 (Bit 1) */ -#define GPDMA0_MASKDSTTRAN_CH1_Msk \ - (0x2UL) /*!< GPDMA0 MASKDSTTRAN: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKDSTTRAN_CH2_Pos \ - (2UL) /*!< GPDMA0 MASKDSTTRAN: CH2 (Bit 2) */ -#define GPDMA0_MASKDSTTRAN_CH2_Msk \ - (0x4UL) /*!< GPDMA0 MASKDSTTRAN: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKDSTTRAN_CH3_Pos \ - (3UL) /*!< GPDMA0 MASKDSTTRAN: CH3 (Bit 3) */ -#define GPDMA0_MASKDSTTRAN_CH3_Msk \ - (0x8UL) /*!< GPDMA0 MASKDSTTRAN: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKDSTTRAN_CH4_Pos \ - (4UL) /*!< GPDMA0 MASKDSTTRAN: CH4 (Bit 4) */ -#define GPDMA0_MASKDSTTRAN_CH4_Msk \ - (0x10UL) /*!< GPDMA0 MASKDSTTRAN: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKDSTTRAN_CH5_Pos \ - (5UL) /*!< GPDMA0 MASKDSTTRAN: CH5 (Bit 5) */ -#define GPDMA0_MASKDSTTRAN_CH5_Msk \ - (0x20UL) /*!< GPDMA0 MASKDSTTRAN: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKDSTTRAN_CH6_Pos \ - (6UL) /*!< GPDMA0 MASKDSTTRAN: CH6 (Bit 6) */ -#define GPDMA0_MASKDSTTRAN_CH6_Msk \ - (0x40UL) /*!< GPDMA0 MASKDSTTRAN: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKDSTTRAN_CH7_Pos \ - (7UL) /*!< GPDMA0 MASKDSTTRAN: CH7 (Bit 7) */ -#define GPDMA0_MASKDSTTRAN_CH7_Msk \ - (0x80UL) /*!< GPDMA0 MASKDSTTRAN: CH7 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKDSTTRAN_WE_CH0_Pos \ - (8UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH0 (Bit 8) */ -#define GPDMA0_MASKDSTTRAN_WE_CH0_Msk \ - (0x100UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKDSTTRAN_WE_CH1_Pos \ - (9UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH1 (Bit 9) */ -#define GPDMA0_MASKDSTTRAN_WE_CH1_Msk \ - (0x200UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKDSTTRAN_WE_CH2_Pos \ - (10UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH2 (Bit 10) */ -#define GPDMA0_MASKDSTTRAN_WE_CH2_Msk \ - (0x400UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKDSTTRAN_WE_CH3_Pos \ - (11UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH3 (Bit 11) */ -#define GPDMA0_MASKDSTTRAN_WE_CH3_Msk \ - (0x800UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKDSTTRAN_WE_CH4_Pos \ - (12UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH4 (Bit 12) */ -#define GPDMA0_MASKDSTTRAN_WE_CH4_Msk \ - (0x1000UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKDSTTRAN_WE_CH5_Pos \ - (13UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH5 (Bit 13) */ -#define GPDMA0_MASKDSTTRAN_WE_CH5_Msk \ - (0x2000UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKDSTTRAN_WE_CH6_Pos \ - (14UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH6 (Bit 14) */ -#define GPDMA0_MASKDSTTRAN_WE_CH6_Msk \ - (0x4000UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKDSTTRAN_WE_CH7_Pos \ - (15UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH7 (Bit 15) */ -#define GPDMA0_MASKDSTTRAN_WE_CH7_Msk \ - (0x8000UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH7 (Bitfield-Mask: 0x01) */ - -/* ------------------------------- GPDMA0_MASKERR ------------------------------- */ -#define GPDMA0_MASKERR_CH0_Pos \ - (0UL) /*!< GPDMA0 MASKERR: CH0 (Bit 0) */ -#define GPDMA0_MASKERR_CH0_Msk \ - (0x1UL) /*!< GPDMA0 MASKERR: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKERR_CH1_Pos \ - (1UL) /*!< GPDMA0 MASKERR: CH1 (Bit 1) */ -#define GPDMA0_MASKERR_CH1_Msk \ - (0x2UL) /*!< GPDMA0 MASKERR: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKERR_CH2_Pos \ - (2UL) /*!< GPDMA0 MASKERR: CH2 (Bit 2) */ -#define GPDMA0_MASKERR_CH2_Msk \ - (0x4UL) /*!< GPDMA0 MASKERR: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKERR_CH3_Pos \ - (3UL) /*!< GPDMA0 MASKERR: CH3 (Bit 3) */ -#define GPDMA0_MASKERR_CH3_Msk \ - (0x8UL) /*!< GPDMA0 MASKERR: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKERR_CH4_Pos \ - (4UL) /*!< GPDMA0 MASKERR: CH4 (Bit 4) */ -#define GPDMA0_MASKERR_CH4_Msk \ - (0x10UL) /*!< GPDMA0 MASKERR: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKERR_CH5_Pos \ - (5UL) /*!< GPDMA0 MASKERR: CH5 (Bit 5) */ -#define GPDMA0_MASKERR_CH5_Msk \ - (0x20UL) /*!< GPDMA0 MASKERR: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKERR_CH6_Pos \ - (6UL) /*!< GPDMA0 MASKERR: CH6 (Bit 6) */ -#define GPDMA0_MASKERR_CH6_Msk \ - (0x40UL) /*!< GPDMA0 MASKERR: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKERR_CH7_Pos \ - (7UL) /*!< GPDMA0 MASKERR: CH7 (Bit 7) */ -#define GPDMA0_MASKERR_CH7_Msk \ - (0x80UL) /*!< GPDMA0 MASKERR: CH7 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKERR_WE_CH0_Pos \ - (8UL) /*!< GPDMA0 MASKERR: WE_CH0 (Bit 8) */ -#define GPDMA0_MASKERR_WE_CH0_Msk \ - (0x100UL) /*!< GPDMA0 MASKERR: WE_CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKERR_WE_CH1_Pos \ - (9UL) /*!< GPDMA0 MASKERR: WE_CH1 (Bit 9) */ -#define GPDMA0_MASKERR_WE_CH1_Msk \ - (0x200UL) /*!< GPDMA0 MASKERR: WE_CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKERR_WE_CH2_Pos \ - (10UL) /*!< GPDMA0 MASKERR: WE_CH2 (Bit 10) */ -#define GPDMA0_MASKERR_WE_CH2_Msk \ - (0x400UL) /*!< GPDMA0 MASKERR: WE_CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKERR_WE_CH3_Pos \ - (11UL) /*!< GPDMA0 MASKERR: WE_CH3 (Bit 11) */ -#define GPDMA0_MASKERR_WE_CH3_Msk \ - (0x800UL) /*!< GPDMA0 MASKERR: WE_CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKERR_WE_CH4_Pos \ - (12UL) /*!< GPDMA0 MASKERR: WE_CH4 (Bit 12) */ -#define GPDMA0_MASKERR_WE_CH4_Msk \ - (0x1000UL) /*!< GPDMA0 MASKERR: WE_CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKERR_WE_CH5_Pos \ - (13UL) /*!< GPDMA0 MASKERR: WE_CH5 (Bit 13) */ -#define GPDMA0_MASKERR_WE_CH5_Msk \ - (0x2000UL) /*!< GPDMA0 MASKERR: WE_CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKERR_WE_CH6_Pos \ - (14UL) /*!< GPDMA0 MASKERR: WE_CH6 (Bit 14) */ -#define GPDMA0_MASKERR_WE_CH6_Msk \ - (0x4000UL) /*!< GPDMA0 MASKERR: WE_CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKERR_WE_CH7_Pos \ - (15UL) /*!< GPDMA0 MASKERR: WE_CH7 (Bit 15) */ -#define GPDMA0_MASKERR_WE_CH7_Msk \ - (0x8000UL) /*!< GPDMA0 MASKERR: WE_CH7 (Bitfield-Mask: 0x01) */ - -/* ------------------------------- GPDMA0_CLEARTFR ------------------------------ */ -#define GPDMA0_CLEARTFR_CH0_Pos \ - (0UL) /*!< GPDMA0 CLEARTFR: CH0 (Bit 0) */ -#define GPDMA0_CLEARTFR_CH0_Msk \ - (0x1UL) /*!< GPDMA0 CLEARTFR: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARTFR_CH1_Pos \ - (1UL) /*!< GPDMA0 CLEARTFR: CH1 (Bit 1) */ -#define GPDMA0_CLEARTFR_CH1_Msk \ - (0x2UL) /*!< GPDMA0 CLEARTFR: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARTFR_CH2_Pos \ - (2UL) /*!< GPDMA0 CLEARTFR: CH2 (Bit 2) */ -#define GPDMA0_CLEARTFR_CH2_Msk \ - (0x4UL) /*!< GPDMA0 CLEARTFR: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARTFR_CH3_Pos \ - (3UL) /*!< GPDMA0 CLEARTFR: CH3 (Bit 3) */ -#define GPDMA0_CLEARTFR_CH3_Msk \ - (0x8UL) /*!< GPDMA0 CLEARTFR: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARTFR_CH4_Pos \ - (4UL) /*!< GPDMA0 CLEARTFR: CH4 (Bit 4) */ -#define GPDMA0_CLEARTFR_CH4_Msk \ - (0x10UL) /*!< GPDMA0 CLEARTFR: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARTFR_CH5_Pos \ - (5UL) /*!< GPDMA0 CLEARTFR: CH5 (Bit 5) */ -#define GPDMA0_CLEARTFR_CH5_Msk \ - (0x20UL) /*!< GPDMA0 CLEARTFR: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARTFR_CH6_Pos \ - (6UL) /*!< GPDMA0 CLEARTFR: CH6 (Bit 6) */ -#define GPDMA0_CLEARTFR_CH6_Msk \ - (0x40UL) /*!< GPDMA0 CLEARTFR: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARTFR_CH7_Pos \ - (7UL) /*!< GPDMA0 CLEARTFR: CH7 (Bit 7) */ -#define GPDMA0_CLEARTFR_CH7_Msk \ - (0x80UL) /*!< GPDMA0 CLEARTFR: CH7 (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPDMA0_CLEARBLOCK ----------------------------- */ -#define GPDMA0_CLEARBLOCK_CH0_Pos \ - (0UL) /*!< GPDMA0 CLEARBLOCK: CH0 (Bit 0) */ -#define GPDMA0_CLEARBLOCK_CH0_Msk \ - (0x1UL) /*!< GPDMA0 CLEARBLOCK: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARBLOCK_CH1_Pos \ - (1UL) /*!< GPDMA0 CLEARBLOCK: CH1 (Bit 1) */ -#define GPDMA0_CLEARBLOCK_CH1_Msk \ - (0x2UL) /*!< GPDMA0 CLEARBLOCK: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARBLOCK_CH2_Pos \ - (2UL) /*!< GPDMA0 CLEARBLOCK: CH2 (Bit 2) */ -#define GPDMA0_CLEARBLOCK_CH2_Msk \ - (0x4UL) /*!< GPDMA0 CLEARBLOCK: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARBLOCK_CH3_Pos \ - (3UL) /*!< GPDMA0 CLEARBLOCK: CH3 (Bit 3) */ -#define GPDMA0_CLEARBLOCK_CH3_Msk \ - (0x8UL) /*!< GPDMA0 CLEARBLOCK: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARBLOCK_CH4_Pos \ - (4UL) /*!< GPDMA0 CLEARBLOCK: CH4 (Bit 4) */ -#define GPDMA0_CLEARBLOCK_CH4_Msk \ - (0x10UL) /*!< GPDMA0 CLEARBLOCK: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARBLOCK_CH5_Pos \ - (5UL) /*!< GPDMA0 CLEARBLOCK: CH5 (Bit 5) */ -#define GPDMA0_CLEARBLOCK_CH5_Msk \ - (0x20UL) /*!< GPDMA0 CLEARBLOCK: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARBLOCK_CH6_Pos \ - (6UL) /*!< GPDMA0 CLEARBLOCK: CH6 (Bit 6) */ -#define GPDMA0_CLEARBLOCK_CH6_Msk \ - (0x40UL) /*!< GPDMA0 CLEARBLOCK: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARBLOCK_CH7_Pos \ - (7UL) /*!< GPDMA0 CLEARBLOCK: CH7 (Bit 7) */ -#define GPDMA0_CLEARBLOCK_CH7_Msk \ - (0x80UL) /*!< GPDMA0 CLEARBLOCK: CH7 (Bitfield-Mask: 0x01) */ - -/* ----------------------------- GPDMA0_CLEARSRCTRAN ---------------------------- */ -#define GPDMA0_CLEARSRCTRAN_CH0_Pos \ - (0UL) /*!< GPDMA0 CLEARSRCTRAN: CH0 (Bit 0) */ -#define GPDMA0_CLEARSRCTRAN_CH0_Msk \ - (0x1UL) /*!< GPDMA0 CLEARSRCTRAN: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARSRCTRAN_CH1_Pos \ - (1UL) /*!< GPDMA0 CLEARSRCTRAN: CH1 (Bit 1) */ -#define GPDMA0_CLEARSRCTRAN_CH1_Msk \ - (0x2UL) /*!< GPDMA0 CLEARSRCTRAN: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARSRCTRAN_CH2_Pos \ - (2UL) /*!< GPDMA0 CLEARSRCTRAN: CH2 (Bit 2) */ -#define GPDMA0_CLEARSRCTRAN_CH2_Msk \ - (0x4UL) /*!< GPDMA0 CLEARSRCTRAN: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARSRCTRAN_CH3_Pos \ - (3UL) /*!< GPDMA0 CLEARSRCTRAN: CH3 (Bit 3) */ -#define GPDMA0_CLEARSRCTRAN_CH3_Msk \ - (0x8UL) /*!< GPDMA0 CLEARSRCTRAN: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARSRCTRAN_CH4_Pos \ - (4UL) /*!< GPDMA0 CLEARSRCTRAN: CH4 (Bit 4) */ -#define GPDMA0_CLEARSRCTRAN_CH4_Msk \ - (0x10UL) /*!< GPDMA0 CLEARSRCTRAN: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARSRCTRAN_CH5_Pos \ - (5UL) /*!< GPDMA0 CLEARSRCTRAN: CH5 (Bit 5) */ -#define GPDMA0_CLEARSRCTRAN_CH5_Msk \ - (0x20UL) /*!< GPDMA0 CLEARSRCTRAN: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARSRCTRAN_CH6_Pos \ - (6UL) /*!< GPDMA0 CLEARSRCTRAN: CH6 (Bit 6) */ -#define GPDMA0_CLEARSRCTRAN_CH6_Msk \ - (0x40UL) /*!< GPDMA0 CLEARSRCTRAN: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARSRCTRAN_CH7_Pos \ - (7UL) /*!< GPDMA0 CLEARSRCTRAN: CH7 (Bit 7) */ -#define GPDMA0_CLEARSRCTRAN_CH7_Msk \ - (0x80UL) /*!< GPDMA0 CLEARSRCTRAN: CH7 (Bitfield-Mask: 0x01) */ - -/* ----------------------------- GPDMA0_CLEARDSTTRAN ---------------------------- */ -#define GPDMA0_CLEARDSTTRAN_CH0_Pos \ - (0UL) /*!< GPDMA0 CLEARDSTTRAN: CH0 (Bit 0) */ -#define GPDMA0_CLEARDSTTRAN_CH0_Msk \ - (0x1UL) /*!< GPDMA0 CLEARDSTTRAN: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARDSTTRAN_CH1_Pos \ - (1UL) /*!< GPDMA0 CLEARDSTTRAN: CH1 (Bit 1) */ -#define GPDMA0_CLEARDSTTRAN_CH1_Msk \ - (0x2UL) /*!< GPDMA0 CLEARDSTTRAN: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARDSTTRAN_CH2_Pos \ - (2UL) /*!< GPDMA0 CLEARDSTTRAN: CH2 (Bit 2) */ -#define GPDMA0_CLEARDSTTRAN_CH2_Msk \ - (0x4UL) /*!< GPDMA0 CLEARDSTTRAN: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARDSTTRAN_CH3_Pos \ - (3UL) /*!< GPDMA0 CLEARDSTTRAN: CH3 (Bit 3) */ -#define GPDMA0_CLEARDSTTRAN_CH3_Msk \ - (0x8UL) /*!< GPDMA0 CLEARDSTTRAN: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARDSTTRAN_CH4_Pos \ - (4UL) /*!< GPDMA0 CLEARDSTTRAN: CH4 (Bit 4) */ -#define GPDMA0_CLEARDSTTRAN_CH4_Msk \ - (0x10UL) /*!< GPDMA0 CLEARDSTTRAN: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARDSTTRAN_CH5_Pos \ - (5UL) /*!< GPDMA0 CLEARDSTTRAN: CH5 (Bit 5) */ -#define GPDMA0_CLEARDSTTRAN_CH5_Msk \ - (0x20UL) /*!< GPDMA0 CLEARDSTTRAN: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARDSTTRAN_CH6_Pos \ - (6UL) /*!< GPDMA0 CLEARDSTTRAN: CH6 (Bit 6) */ -#define GPDMA0_CLEARDSTTRAN_CH6_Msk \ - (0x40UL) /*!< GPDMA0 CLEARDSTTRAN: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARDSTTRAN_CH7_Pos \ - (7UL) /*!< GPDMA0 CLEARDSTTRAN: CH7 (Bit 7) */ -#define GPDMA0_CLEARDSTTRAN_CH7_Msk \ - (0x80UL) /*!< GPDMA0 CLEARDSTTRAN: CH7 (Bitfield-Mask: 0x01) */ - -/* ------------------------------- GPDMA0_CLEARERR ------------------------------ */ -#define GPDMA0_CLEARERR_CH0_Pos \ - (0UL) /*!< GPDMA0 CLEARERR: CH0 (Bit 0) */ -#define GPDMA0_CLEARERR_CH0_Msk \ - (0x1UL) /*!< GPDMA0 CLEARERR: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARERR_CH1_Pos \ - (1UL) /*!< GPDMA0 CLEARERR: CH1 (Bit 1) */ -#define GPDMA0_CLEARERR_CH1_Msk \ - (0x2UL) /*!< GPDMA0 CLEARERR: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARERR_CH2_Pos \ - (2UL) /*!< GPDMA0 CLEARERR: CH2 (Bit 2) */ -#define GPDMA0_CLEARERR_CH2_Msk \ - (0x4UL) /*!< GPDMA0 CLEARERR: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARERR_CH3_Pos \ - (3UL) /*!< GPDMA0 CLEARERR: CH3 (Bit 3) */ -#define GPDMA0_CLEARERR_CH3_Msk \ - (0x8UL) /*!< GPDMA0 CLEARERR: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARERR_CH4_Pos \ - (4UL) /*!< GPDMA0 CLEARERR: CH4 (Bit 4) */ -#define GPDMA0_CLEARERR_CH4_Msk \ - (0x10UL) /*!< GPDMA0 CLEARERR: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARERR_CH5_Pos \ - (5UL) /*!< GPDMA0 CLEARERR: CH5 (Bit 5) */ -#define GPDMA0_CLEARERR_CH5_Msk \ - (0x20UL) /*!< GPDMA0 CLEARERR: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARERR_CH6_Pos \ - (6UL) /*!< GPDMA0 CLEARERR: CH6 (Bit 6) */ -#define GPDMA0_CLEARERR_CH6_Msk \ - (0x40UL) /*!< GPDMA0 CLEARERR: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARERR_CH7_Pos \ - (7UL) /*!< GPDMA0 CLEARERR: CH7 (Bit 7) */ -#define GPDMA0_CLEARERR_CH7_Msk \ - (0x80UL) /*!< GPDMA0 CLEARERR: CH7 (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPDMA0_STATUSINT ------------------------------ */ -#define GPDMA0_STATUSINT_TFR_Pos \ - (0UL) /*!< GPDMA0 STATUSINT: TFR (Bit 0) */ -#define GPDMA0_STATUSINT_TFR_Msk \ - (0x1UL) /*!< GPDMA0 STATUSINT: TFR (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSINT_BLOCK_Pos \ - (1UL) /*!< GPDMA0 STATUSINT: BLOCK (Bit 1) */ -#define GPDMA0_STATUSINT_BLOCK_Msk \ - (0x2UL) /*!< GPDMA0 STATUSINT: BLOCK (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSINT_SRCT_Pos \ - (2UL) /*!< GPDMA0 STATUSINT: SRCT (Bit 2) */ -#define GPDMA0_STATUSINT_SRCT_Msk \ - (0x4UL) /*!< GPDMA0 STATUSINT: SRCT (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSINT_DSTT_Pos \ - (3UL) /*!< GPDMA0 STATUSINT: DSTT (Bit 3) */ -#define GPDMA0_STATUSINT_DSTT_Msk \ - (0x8UL) /*!< GPDMA0 STATUSINT: DSTT (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSINT_ERR_Pos \ - (4UL) /*!< GPDMA0 STATUSINT: ERR (Bit 4) */ -#define GPDMA0_STATUSINT_ERR_Msk \ - (0x10UL) /*!< GPDMA0 STATUSINT: ERR (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPDMA0_REQSRCREG ------------------------------ */ -#define GPDMA0_REQSRCREG_CH0_Pos \ - (0UL) /*!< GPDMA0 REQSRCREG: CH0 (Bit 0) */ -#define GPDMA0_REQSRCREG_CH0_Msk \ - (0x1UL) /*!< GPDMA0 REQSRCREG: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQSRCREG_CH1_Pos \ - (1UL) /*!< GPDMA0 REQSRCREG: CH1 (Bit 1) */ -#define GPDMA0_REQSRCREG_CH1_Msk \ - (0x2UL) /*!< GPDMA0 REQSRCREG: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQSRCREG_CH2_Pos \ - (2UL) /*!< GPDMA0 REQSRCREG: CH2 (Bit 2) */ -#define GPDMA0_REQSRCREG_CH2_Msk \ - (0x4UL) /*!< GPDMA0 REQSRCREG: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQSRCREG_CH3_Pos \ - (3UL) /*!< GPDMA0 REQSRCREG: CH3 (Bit 3) */ -#define GPDMA0_REQSRCREG_CH3_Msk \ - (0x8UL) /*!< GPDMA0 REQSRCREG: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQSRCREG_CH4_Pos \ - (4UL) /*!< GPDMA0 REQSRCREG: CH4 (Bit 4) */ -#define GPDMA0_REQSRCREG_CH4_Msk \ - (0x10UL) /*!< GPDMA0 REQSRCREG: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQSRCREG_CH5_Pos \ - (5UL) /*!< GPDMA0 REQSRCREG: CH5 (Bit 5) */ -#define GPDMA0_REQSRCREG_CH5_Msk \ - (0x20UL) /*!< GPDMA0 REQSRCREG: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQSRCREG_CH6_Pos \ - (6UL) /*!< GPDMA0 REQSRCREG: CH6 (Bit 6) */ -#define GPDMA0_REQSRCREG_CH6_Msk \ - (0x40UL) /*!< GPDMA0 REQSRCREG: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQSRCREG_CH7_Pos \ - (7UL) /*!< GPDMA0 REQSRCREG: CH7 (Bit 7) */ -#define GPDMA0_REQSRCREG_CH7_Msk \ - (0x80UL) /*!< GPDMA0 REQSRCREG: CH7 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQSRCREG_WE_CH0_Pos \ - (8UL) /*!< GPDMA0 REQSRCREG: WE_CH0 (Bit 8) */ -#define GPDMA0_REQSRCREG_WE_CH0_Msk \ - (0x100UL) /*!< GPDMA0 REQSRCREG: WE_CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQSRCREG_WE_CH1_Pos \ - (9UL) /*!< GPDMA0 REQSRCREG: WE_CH1 (Bit 9) */ -#define GPDMA0_REQSRCREG_WE_CH1_Msk \ - (0x200UL) /*!< GPDMA0 REQSRCREG: WE_CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQSRCREG_WE_CH2_Pos \ - (10UL) /*!< GPDMA0 REQSRCREG: WE_CH2 (Bit 10) */ -#define GPDMA0_REQSRCREG_WE_CH2_Msk \ - (0x400UL) /*!< GPDMA0 REQSRCREG: WE_CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQSRCREG_WE_CH3_Pos \ - (11UL) /*!< GPDMA0 REQSRCREG: WE_CH3 (Bit 11) */ -#define GPDMA0_REQSRCREG_WE_CH3_Msk \ - (0x800UL) /*!< GPDMA0 REQSRCREG: WE_CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQSRCREG_WE_CH4_Pos \ - (12UL) /*!< GPDMA0 REQSRCREG: WE_CH4 (Bit 12) */ -#define GPDMA0_REQSRCREG_WE_CH4_Msk \ - (0x1000UL) /*!< GPDMA0 REQSRCREG: WE_CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQSRCREG_WE_CH5_Pos \ - (13UL) /*!< GPDMA0 REQSRCREG: WE_CH5 (Bit 13) */ -#define GPDMA0_REQSRCREG_WE_CH5_Msk \ - (0x2000UL) /*!< GPDMA0 REQSRCREG: WE_CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQSRCREG_WE_CH6_Pos \ - (14UL) /*!< GPDMA0 REQSRCREG: WE_CH6 (Bit 14) */ -#define GPDMA0_REQSRCREG_WE_CH6_Msk \ - (0x4000UL) /*!< GPDMA0 REQSRCREG: WE_CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQSRCREG_WE_CH7_Pos \ - (15UL) /*!< GPDMA0 REQSRCREG: WE_CH7 (Bit 15) */ -#define GPDMA0_REQSRCREG_WE_CH7_Msk \ - (0x8000UL) /*!< GPDMA0 REQSRCREG: WE_CH7 (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPDMA0_REQDSTREG ------------------------------ */ -#define GPDMA0_REQDSTREG_CH0_Pos \ - (0UL) /*!< GPDMA0 REQDSTREG: CH0 (Bit 0) */ -#define GPDMA0_REQDSTREG_CH0_Msk \ - (0x1UL) /*!< GPDMA0 REQDSTREG: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQDSTREG_CH1_Pos \ - (1UL) /*!< GPDMA0 REQDSTREG: CH1 (Bit 1) */ -#define GPDMA0_REQDSTREG_CH1_Msk \ - (0x2UL) /*!< GPDMA0 REQDSTREG: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQDSTREG_CH2_Pos \ - (2UL) /*!< GPDMA0 REQDSTREG: CH2 (Bit 2) */ -#define GPDMA0_REQDSTREG_CH2_Msk \ - (0x4UL) /*!< GPDMA0 REQDSTREG: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQDSTREG_CH3_Pos \ - (3UL) /*!< GPDMA0 REQDSTREG: CH3 (Bit 3) */ -#define GPDMA0_REQDSTREG_CH3_Msk \ - (0x8UL) /*!< GPDMA0 REQDSTREG: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQDSTREG_CH4_Pos \ - (4UL) /*!< GPDMA0 REQDSTREG: CH4 (Bit 4) */ -#define GPDMA0_REQDSTREG_CH4_Msk \ - (0x10UL) /*!< GPDMA0 REQDSTREG: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQDSTREG_CH5_Pos \ - (5UL) /*!< GPDMA0 REQDSTREG: CH5 (Bit 5) */ -#define GPDMA0_REQDSTREG_CH5_Msk \ - (0x20UL) /*!< GPDMA0 REQDSTREG: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQDSTREG_CH6_Pos \ - (6UL) /*!< GPDMA0 REQDSTREG: CH6 (Bit 6) */ -#define GPDMA0_REQDSTREG_CH6_Msk \ - (0x40UL) /*!< GPDMA0 REQDSTREG: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQDSTREG_CH7_Pos \ - (7UL) /*!< GPDMA0 REQDSTREG: CH7 (Bit 7) */ -#define GPDMA0_REQDSTREG_CH7_Msk \ - (0x80UL) /*!< GPDMA0 REQDSTREG: CH7 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQDSTREG_WE_CH0_Pos \ - (8UL) /*!< GPDMA0 REQDSTREG: WE_CH0 (Bit 8) */ -#define GPDMA0_REQDSTREG_WE_CH0_Msk \ - (0x100UL) /*!< GPDMA0 REQDSTREG: WE_CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQDSTREG_WE_CH1_Pos \ - (9UL) /*!< GPDMA0 REQDSTREG: WE_CH1 (Bit 9) */ -#define GPDMA0_REQDSTREG_WE_CH1_Msk \ - (0x200UL) /*!< GPDMA0 REQDSTREG: WE_CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQDSTREG_WE_CH2_Pos \ - (10UL) /*!< GPDMA0 REQDSTREG: WE_CH2 (Bit 10) */ -#define GPDMA0_REQDSTREG_WE_CH2_Msk \ - (0x400UL) /*!< GPDMA0 REQDSTREG: WE_CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQDSTREG_WE_CH3_Pos \ - (11UL) /*!< GPDMA0 REQDSTREG: WE_CH3 (Bit 11) */ -#define GPDMA0_REQDSTREG_WE_CH3_Msk \ - (0x800UL) /*!< GPDMA0 REQDSTREG: WE_CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQDSTREG_WE_CH4_Pos \ - (12UL) /*!< GPDMA0 REQDSTREG: WE_CH4 (Bit 12) */ -#define GPDMA0_REQDSTREG_WE_CH4_Msk \ - (0x1000UL) /*!< GPDMA0 REQDSTREG: WE_CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQDSTREG_WE_CH5_Pos \ - (13UL) /*!< GPDMA0 REQDSTREG: WE_CH5 (Bit 13) */ -#define GPDMA0_REQDSTREG_WE_CH5_Msk \ - (0x2000UL) /*!< GPDMA0 REQDSTREG: WE_CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQDSTREG_WE_CH6_Pos \ - (14UL) /*!< GPDMA0 REQDSTREG: WE_CH6 (Bit 14) */ -#define GPDMA0_REQDSTREG_WE_CH6_Msk \ - (0x4000UL) /*!< GPDMA0 REQDSTREG: WE_CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQDSTREG_WE_CH7_Pos \ - (15UL) /*!< GPDMA0 REQDSTREG: WE_CH7 (Bit 15) */ -#define GPDMA0_REQDSTREG_WE_CH7_Msk \ - (0x8000UL) /*!< GPDMA0 REQDSTREG: WE_CH7 (Bitfield-Mask: 0x01) */ - -/* ----------------------------- GPDMA0_SGLREQSRCREG ---------------------------- */ -#define GPDMA0_SGLREQSRCREG_CH0_Pos \ - (0UL) /*!< GPDMA0 SGLREQSRCREG: CH0 (Bit 0) */ -#define GPDMA0_SGLREQSRCREG_CH0_Msk \ - (0x1UL) /*!< GPDMA0 SGLREQSRCREG: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQSRCREG_CH1_Pos \ - (1UL) /*!< GPDMA0 SGLREQSRCREG: CH1 (Bit 1) */ -#define GPDMA0_SGLREQSRCREG_CH1_Msk \ - (0x2UL) /*!< GPDMA0 SGLREQSRCREG: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQSRCREG_CH2_Pos \ - (2UL) /*!< GPDMA0 SGLREQSRCREG: CH2 (Bit 2) */ -#define GPDMA0_SGLREQSRCREG_CH2_Msk \ - (0x4UL) /*!< GPDMA0 SGLREQSRCREG: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQSRCREG_CH3_Pos \ - (3UL) /*!< GPDMA0 SGLREQSRCREG: CH3 (Bit 3) */ -#define GPDMA0_SGLREQSRCREG_CH3_Msk \ - (0x8UL) /*!< GPDMA0 SGLREQSRCREG: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQSRCREG_CH4_Pos \ - (4UL) /*!< GPDMA0 SGLREQSRCREG: CH4 (Bit 4) */ -#define GPDMA0_SGLREQSRCREG_CH4_Msk \ - (0x10UL) /*!< GPDMA0 SGLREQSRCREG: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQSRCREG_CH5_Pos \ - (5UL) /*!< GPDMA0 SGLREQSRCREG: CH5 (Bit 5) */ -#define GPDMA0_SGLREQSRCREG_CH5_Msk \ - (0x20UL) /*!< GPDMA0 SGLREQSRCREG: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQSRCREG_CH6_Pos \ - (6UL) /*!< GPDMA0 SGLREQSRCREG: CH6 (Bit 6) */ -#define GPDMA0_SGLREQSRCREG_CH6_Msk \ - (0x40UL) /*!< GPDMA0 SGLREQSRCREG: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQSRCREG_CH7_Pos \ - (7UL) /*!< GPDMA0 SGLREQSRCREG: CH7 (Bit 7) */ -#define GPDMA0_SGLREQSRCREG_CH7_Msk \ - (0x80UL) /*!< GPDMA0 SGLREQSRCREG: CH7 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQSRCREG_WE_CH0_Pos \ - (8UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH0 (Bit 8) */ -#define GPDMA0_SGLREQSRCREG_WE_CH0_Msk \ - (0x100UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQSRCREG_WE_CH1_Pos \ - (9UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH1 (Bit 9) */ -#define GPDMA0_SGLREQSRCREG_WE_CH1_Msk \ - (0x200UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQSRCREG_WE_CH2_Pos \ - (10UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH2 (Bit 10) */ -#define GPDMA0_SGLREQSRCREG_WE_CH2_Msk \ - (0x400UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQSRCREG_WE_CH3_Pos \ - (11UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH3 (Bit 11) */ -#define GPDMA0_SGLREQSRCREG_WE_CH3_Msk \ - (0x800UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQSRCREG_WE_CH4_Pos \ - (12UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH4 (Bit 12) */ -#define GPDMA0_SGLREQSRCREG_WE_CH4_Msk \ - (0x1000UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQSRCREG_WE_CH5_Pos \ - (13UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH5 (Bit 13) */ -#define GPDMA0_SGLREQSRCREG_WE_CH5_Msk \ - (0x2000UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQSRCREG_WE_CH6_Pos \ - (14UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH6 (Bit 14) */ -#define GPDMA0_SGLREQSRCREG_WE_CH6_Msk \ - (0x4000UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQSRCREG_WE_CH7_Pos \ - (15UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH7 (Bit 15) */ -#define GPDMA0_SGLREQSRCREG_WE_CH7_Msk \ - (0x8000UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH7 (Bitfield-Mask: 0x01) */ - -/* ----------------------------- GPDMA0_SGLREQDSTREG ---------------------------- */ -#define GPDMA0_SGLREQDSTREG_CH0_Pos \ - (0UL) /*!< GPDMA0 SGLREQDSTREG: CH0 (Bit 0) */ -#define GPDMA0_SGLREQDSTREG_CH0_Msk \ - (0x1UL) /*!< GPDMA0 SGLREQDSTREG: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQDSTREG_CH1_Pos \ - (1UL) /*!< GPDMA0 SGLREQDSTREG: CH1 (Bit 1) */ -#define GPDMA0_SGLREQDSTREG_CH1_Msk \ - (0x2UL) /*!< GPDMA0 SGLREQDSTREG: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQDSTREG_CH2_Pos \ - (2UL) /*!< GPDMA0 SGLREQDSTREG: CH2 (Bit 2) */ -#define GPDMA0_SGLREQDSTREG_CH2_Msk \ - (0x4UL) /*!< GPDMA0 SGLREQDSTREG: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQDSTREG_CH3_Pos \ - (3UL) /*!< GPDMA0 SGLREQDSTREG: CH3 (Bit 3) */ -#define GPDMA0_SGLREQDSTREG_CH3_Msk \ - (0x8UL) /*!< GPDMA0 SGLREQDSTREG: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQDSTREG_CH4_Pos \ - (4UL) /*!< GPDMA0 SGLREQDSTREG: CH4 (Bit 4) */ -#define GPDMA0_SGLREQDSTREG_CH4_Msk \ - (0x10UL) /*!< GPDMA0 SGLREQDSTREG: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQDSTREG_CH5_Pos \ - (5UL) /*!< GPDMA0 SGLREQDSTREG: CH5 (Bit 5) */ -#define GPDMA0_SGLREQDSTREG_CH5_Msk \ - (0x20UL) /*!< GPDMA0 SGLREQDSTREG: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQDSTREG_CH6_Pos \ - (6UL) /*!< GPDMA0 SGLREQDSTREG: CH6 (Bit 6) */ -#define GPDMA0_SGLREQDSTREG_CH6_Msk \ - (0x40UL) /*!< GPDMA0 SGLREQDSTREG: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQDSTREG_CH7_Pos \ - (7UL) /*!< GPDMA0 SGLREQDSTREG: CH7 (Bit 7) */ -#define GPDMA0_SGLREQDSTREG_CH7_Msk \ - (0x80UL) /*!< GPDMA0 SGLREQDSTREG: CH7 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQDSTREG_WE_CH0_Pos \ - (8UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH0 (Bit 8) */ -#define GPDMA0_SGLREQDSTREG_WE_CH0_Msk \ - (0x100UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQDSTREG_WE_CH1_Pos \ - (9UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH1 (Bit 9) */ -#define GPDMA0_SGLREQDSTREG_WE_CH1_Msk \ - (0x200UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQDSTREG_WE_CH2_Pos \ - (10UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH2 (Bit 10) */ -#define GPDMA0_SGLREQDSTREG_WE_CH2_Msk \ - (0x400UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQDSTREG_WE_CH3_Pos \ - (11UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH3 (Bit 11) */ -#define GPDMA0_SGLREQDSTREG_WE_CH3_Msk \ - (0x800UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQDSTREG_WE_CH4_Pos \ - (12UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH4 (Bit 12) */ -#define GPDMA0_SGLREQDSTREG_WE_CH4_Msk \ - (0x1000UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQDSTREG_WE_CH5_Pos \ - (13UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH5 (Bit 13) */ -#define GPDMA0_SGLREQDSTREG_WE_CH5_Msk \ - (0x2000UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQDSTREG_WE_CH6_Pos \ - (14UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH6 (Bit 14) */ -#define GPDMA0_SGLREQDSTREG_WE_CH6_Msk \ - (0x4000UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQDSTREG_WE_CH7_Pos \ - (15UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH7 (Bit 15) */ -#define GPDMA0_SGLREQDSTREG_WE_CH7_Msk \ - (0x8000UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH7 (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPDMA0_LSTSRCREG ------------------------------ */ -#define GPDMA0_LSTSRCREG_CH0_Pos \ - (0UL) /*!< GPDMA0 LSTSRCREG: CH0 (Bit 0) */ -#define GPDMA0_LSTSRCREG_CH0_Msk \ - (0x1UL) /*!< GPDMA0 LSTSRCREG: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTSRCREG_CH1_Pos \ - (1UL) /*!< GPDMA0 LSTSRCREG: CH1 (Bit 1) */ -#define GPDMA0_LSTSRCREG_CH1_Msk \ - (0x2UL) /*!< GPDMA0 LSTSRCREG: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTSRCREG_CH2_Pos \ - (2UL) /*!< GPDMA0 LSTSRCREG: CH2 (Bit 2) */ -#define GPDMA0_LSTSRCREG_CH2_Msk \ - (0x4UL) /*!< GPDMA0 LSTSRCREG: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTSRCREG_CH3_Pos \ - (3UL) /*!< GPDMA0 LSTSRCREG: CH3 (Bit 3) */ -#define GPDMA0_LSTSRCREG_CH3_Msk \ - (0x8UL) /*!< GPDMA0 LSTSRCREG: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTSRCREG_CH4_Pos \ - (4UL) /*!< GPDMA0 LSTSRCREG: CH4 (Bit 4) */ -#define GPDMA0_LSTSRCREG_CH4_Msk \ - (0x10UL) /*!< GPDMA0 LSTSRCREG: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTSRCREG_CH5_Pos \ - (5UL) /*!< GPDMA0 LSTSRCREG: CH5 (Bit 5) */ -#define GPDMA0_LSTSRCREG_CH5_Msk \ - (0x20UL) /*!< GPDMA0 LSTSRCREG: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTSRCREG_CH6_Pos \ - (6UL) /*!< GPDMA0 LSTSRCREG: CH6 (Bit 6) */ -#define GPDMA0_LSTSRCREG_CH6_Msk \ - (0x40UL) /*!< GPDMA0 LSTSRCREG: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTSRCREG_CH7_Pos \ - (7UL) /*!< GPDMA0 LSTSRCREG: CH7 (Bit 7) */ -#define GPDMA0_LSTSRCREG_CH7_Msk \ - (0x80UL) /*!< GPDMA0 LSTSRCREG: CH7 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTSRCREG_WE_CH0_Pos \ - (8UL) /*!< GPDMA0 LSTSRCREG: WE_CH0 (Bit 8) */ -#define GPDMA0_LSTSRCREG_WE_CH0_Msk \ - (0x100UL) /*!< GPDMA0 LSTSRCREG: WE_CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTSRCREG_WE_CH1_Pos \ - (9UL) /*!< GPDMA0 LSTSRCREG: WE_CH1 (Bit 9) */ -#define GPDMA0_LSTSRCREG_WE_CH1_Msk \ - (0x200UL) /*!< GPDMA0 LSTSRCREG: WE_CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTSRCREG_WE_CH2_Pos \ - (10UL) /*!< GPDMA0 LSTSRCREG: WE_CH2 (Bit 10) */ -#define GPDMA0_LSTSRCREG_WE_CH2_Msk \ - (0x400UL) /*!< GPDMA0 LSTSRCREG: WE_CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTSRCREG_WE_CH3_Pos \ - (11UL) /*!< GPDMA0 LSTSRCREG: WE_CH3 (Bit 11) */ -#define GPDMA0_LSTSRCREG_WE_CH3_Msk \ - (0x800UL) /*!< GPDMA0 LSTSRCREG: WE_CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTSRCREG_WE_CH4_Pos \ - (12UL) /*!< GPDMA0 LSTSRCREG: WE_CH4 (Bit 12) */ -#define GPDMA0_LSTSRCREG_WE_CH4_Msk \ - (0x1000UL) /*!< GPDMA0 LSTSRCREG: WE_CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTSRCREG_WE_CH5_Pos \ - (13UL) /*!< GPDMA0 LSTSRCREG: WE_CH5 (Bit 13) */ -#define GPDMA0_LSTSRCREG_WE_CH5_Msk \ - (0x2000UL) /*!< GPDMA0 LSTSRCREG: WE_CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTSRCREG_WE_CH6_Pos \ - (14UL) /*!< GPDMA0 LSTSRCREG: WE_CH6 (Bit 14) */ -#define GPDMA0_LSTSRCREG_WE_CH6_Msk \ - (0x4000UL) /*!< GPDMA0 LSTSRCREG: WE_CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTSRCREG_WE_CH7_Pos \ - (15UL) /*!< GPDMA0 LSTSRCREG: WE_CH7 (Bit 15) */ -#define GPDMA0_LSTSRCREG_WE_CH7_Msk \ - (0x8000UL) /*!< GPDMA0 LSTSRCREG: WE_CH7 (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPDMA0_LSTDSTREG ------------------------------ */ -#define GPDMA0_LSTDSTREG_CH0_Pos \ - (0UL) /*!< GPDMA0 LSTDSTREG: CH0 (Bit 0) */ -#define GPDMA0_LSTDSTREG_CH0_Msk \ - (0x1UL) /*!< GPDMA0 LSTDSTREG: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTDSTREG_CH1_Pos \ - (1UL) /*!< GPDMA0 LSTDSTREG: CH1 (Bit 1) */ -#define GPDMA0_LSTDSTREG_CH1_Msk \ - (0x2UL) /*!< GPDMA0 LSTDSTREG: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTDSTREG_CH2_Pos \ - (2UL) /*!< GPDMA0 LSTDSTREG: CH2 (Bit 2) */ -#define GPDMA0_LSTDSTREG_CH2_Msk \ - (0x4UL) /*!< GPDMA0 LSTDSTREG: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTDSTREG_CH3_Pos \ - (3UL) /*!< GPDMA0 LSTDSTREG: CH3 (Bit 3) */ -#define GPDMA0_LSTDSTREG_CH3_Msk \ - (0x8UL) /*!< GPDMA0 LSTDSTREG: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTDSTREG_CH4_Pos \ - (4UL) /*!< GPDMA0 LSTDSTREG: CH4 (Bit 4) */ -#define GPDMA0_LSTDSTREG_CH4_Msk \ - (0x10UL) /*!< GPDMA0 LSTDSTREG: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTDSTREG_CH5_Pos \ - (5UL) /*!< GPDMA0 LSTDSTREG: CH5 (Bit 5) */ -#define GPDMA0_LSTDSTREG_CH5_Msk \ - (0x20UL) /*!< GPDMA0 LSTDSTREG: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTDSTREG_CH6_Pos \ - (6UL) /*!< GPDMA0 LSTDSTREG: CH6 (Bit 6) */ -#define GPDMA0_LSTDSTREG_CH6_Msk \ - (0x40UL) /*!< GPDMA0 LSTDSTREG: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTDSTREG_CH7_Pos \ - (7UL) /*!< GPDMA0 LSTDSTREG: CH7 (Bit 7) */ -#define GPDMA0_LSTDSTREG_CH7_Msk \ - (0x80UL) /*!< GPDMA0 LSTDSTREG: CH7 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTDSTREG_WE_CH0_Pos \ - (8UL) /*!< GPDMA0 LSTDSTREG: WE_CH0 (Bit 8) */ -#define GPDMA0_LSTDSTREG_WE_CH0_Msk \ - (0x100UL) /*!< GPDMA0 LSTDSTREG: WE_CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTDSTREG_WE_CH1_Pos \ - (9UL) /*!< GPDMA0 LSTDSTREG: WE_CH1 (Bit 9) */ -#define GPDMA0_LSTDSTREG_WE_CH1_Msk \ - (0x200UL) /*!< GPDMA0 LSTDSTREG: WE_CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTDSTREG_WE_CH2_Pos \ - (10UL) /*!< GPDMA0 LSTDSTREG: WE_CH2 (Bit 10) */ -#define GPDMA0_LSTDSTREG_WE_CH2_Msk \ - (0x400UL) /*!< GPDMA0 LSTDSTREG: WE_CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTDSTREG_WE_CH3_Pos \ - (11UL) /*!< GPDMA0 LSTDSTREG: WE_CH3 (Bit 11) */ -#define GPDMA0_LSTDSTREG_WE_CH3_Msk \ - (0x800UL) /*!< GPDMA0 LSTDSTREG: WE_CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTDSTREG_WE_CH4_Pos \ - (12UL) /*!< GPDMA0 LSTDSTREG: WE_CH4 (Bit 12) */ -#define GPDMA0_LSTDSTREG_WE_CH4_Msk \ - (0x1000UL) /*!< GPDMA0 LSTDSTREG: WE_CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTDSTREG_WE_CH5_Pos \ - (13UL) /*!< GPDMA0 LSTDSTREG: WE_CH5 (Bit 13) */ -#define GPDMA0_LSTDSTREG_WE_CH5_Msk \ - (0x2000UL) /*!< GPDMA0 LSTDSTREG: WE_CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTDSTREG_WE_CH6_Pos \ - (14UL) /*!< GPDMA0 LSTDSTREG: WE_CH6 (Bit 14) */ -#define GPDMA0_LSTDSTREG_WE_CH6_Msk \ - (0x4000UL) /*!< GPDMA0 LSTDSTREG: WE_CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTDSTREG_WE_CH7_Pos \ - (15UL) /*!< GPDMA0 LSTDSTREG: WE_CH7 (Bit 15) */ -#define GPDMA0_LSTDSTREG_WE_CH7_Msk \ - (0x8000UL) /*!< GPDMA0 LSTDSTREG: WE_CH7 (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPDMA0_DMACFGREG ------------------------------ */ -#define GPDMA0_DMACFGREG_DMA_EN_Pos \ - (0UL) /*!< GPDMA0 DMACFGREG: DMA_EN (Bit 0) */ -#define GPDMA0_DMACFGREG_DMA_EN_Msk \ - (0x1UL) /*!< GPDMA0 DMACFGREG: DMA_EN (Bitfield-Mask: 0x01) */ - -/* ------------------------------- GPDMA0_CHENREG ------------------------------- */ -#define GPDMA0_CHENREG_CH_Pos \ - (0UL) /*!< GPDMA0 CHENREG: CH (Bit 0) */ -#define GPDMA0_CHENREG_CH_Msk \ - (0xffUL) /*!< GPDMA0 CHENREG: CH (Bitfield-Mask: 0xff) */ -#define GPDMA0_CHENREG_WE_CH_Pos \ - (8UL) /*!< GPDMA0 CHENREG: WE_CH (Bit 8) */ -#define GPDMA0_CHENREG_WE_CH_Msk \ - (0xff00UL) /*!< GPDMA0 CHENREG: WE_CH (Bitfield-Mask: 0xff) */ - -/* ---------------------------------- GPDMA0_ID --------------------------------- */ -#define GPDMA0_ID_VALUE_Pos \ - (0UL) /*!< GPDMA0 ID: VALUE (Bit 0) */ -#define GPDMA0_ID_VALUE_Msk \ - (0xffffffffUL) /*!< GPDMA0 ID: VALUE (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------------- GPDMA0_TYPE -------------------------------- */ -#define GPDMA0_TYPE_VALUE_Pos \ - (0UL) /*!< GPDMA0 TYPE: VALUE (Bit 0) */ -#define GPDMA0_TYPE_VALUE_Msk \ - (0xffffffffUL) /*!< GPDMA0 TYPE: VALUE (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------- GPDMA0_VERSION ------------------------------- */ -#define GPDMA0_VERSION_VALUE_Pos \ - (0UL) /*!< GPDMA0 VERSION: VALUE (Bit 0) */ -#define GPDMA0_VERSION_VALUE_Msk \ - (0xffffffffUL) /*!< GPDMA0 VERSION: VALUE (Bitfield-Mask: 0xffffffff) */ - -/* ================================================================================ */ -/* ================ Group 'GPDMA0_CH0_1' Position & Mask ================ */ -/* ================================================================================ */ - -/* ------------------------------ GPDMA0_CH_SAR ------------------------------ */ -#define GPDMA0_CH_SAR_SAR_Pos \ - (0UL) /*!< GPDMA0_CH0_1 SAR: SAR (Bit 0) */ -#define GPDMA0_CH_SAR_SAR_Msk \ - (0xffffffffUL) /*!< GPDMA0_CH0_1 SAR: SAR (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------ GPDMA0_CH_DAR ------------------------------ */ -#define GPDMA0_CH_DAR_DAR_Pos \ - (0UL) /*!< GPDMA0_CH0_1 DAR: DAR (Bit 0) */ -#define GPDMA0_CH_DAR_DAR_Msk \ - (0xffffffffUL) /*!< GPDMA0_CH0_1 DAR: DAR (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------ GPDMA0_CH_LLP ------------------------------ */ -#define GPDMA0_CH_LLP_LOC_Pos \ - (2UL) /*!< GPDMA0_CH0_1 LLP: LOC (Bit 2) */ -#define GPDMA0_CH_LLP_LOC_Msk \ - (0xfffffffcUL) /*!< GPDMA0_CH0_1 LLP: LOC (Bitfield-Mask: 0x3fffffff) */ - -/* ------------------------------ GPDMA0_CH_CTLL ----------------------------- */ -#define GPDMA0_CH_CTLL_INT_EN_Pos \ - (0UL) /*!< GPDMA0_CH0_1 CTLL: INT_EN (Bit 0) */ -#define GPDMA0_CH_CTLL_INT_EN_Msk \ - (0x1UL) /*!< GPDMA0_CH0_1 CTLL: INT_EN (Bitfield-Mask: 0x01) */ -#define GPDMA0_CH_CTLL_DST_TR_WIDTH_Pos \ - (1UL) /*!< GPDMA0_CH0_1 CTLL: DST_TR_WIDTH (Bit 1) */ -#define GPDMA0_CH_CTLL_DST_TR_WIDTH_Msk \ - (0xeUL) /*!< GPDMA0_CH0_1 CTLL: DST_TR_WIDTH (Bitfield-Mask: 0x07) */ -#define GPDMA0_CH_CTLL_SRC_TR_WIDTH_Pos \ - (4UL) /*!< GPDMA0_CH0_1 CTLL: SRC_TR_WIDTH (Bit 4) */ -#define GPDMA0_CH_CTLL_SRC_TR_WIDTH_Msk \ - (0x70UL) /*!< GPDMA0_CH0_1 CTLL: SRC_TR_WIDTH (Bitfield-Mask: 0x07) */ -#define GPDMA0_CH_CTLL_DINC_Pos \ - (7UL) /*!< GPDMA0_CH0_1 CTLL: DINC (Bit 7) */ -#define GPDMA0_CH_CTLL_DINC_Msk \ - (0x180UL) /*!< GPDMA0_CH0_1 CTLL: DINC (Bitfield-Mask: 0x03) */ -#define GPDMA0_CH_CTLL_SINC_Pos \ - (9UL) /*!< GPDMA0_CH0_1 CTLL: SINC (Bit 9) */ -#define GPDMA0_CH_CTLL_SINC_Msk \ - (0x600UL) /*!< GPDMA0_CH0_1 CTLL: SINC (Bitfield-Mask: 0x03) */ -#define GPDMA0_CH_CTLL_DEST_MSIZE_Pos \ - (11UL) /*!< GPDMA0_CH0_1 CTLL: DEST_MSIZE (Bit 11) */ -#define GPDMA0_CH_CTLL_DEST_MSIZE_Msk \ - (0x3800UL) /*!< GPDMA0_CH0_1 CTLL: DEST_MSIZE (Bitfield-Mask: 0x07) */ -#define GPDMA0_CH_CTLL_SRC_MSIZE_Pos \ - (14UL) /*!< GPDMA0_CH0_1 CTLL: SRC_MSIZE (Bit 14) */ -#define GPDMA0_CH_CTLL_SRC_MSIZE_Msk \ - (0x1c000UL) /*!< GPDMA0_CH0_1 CTLL: SRC_MSIZE (Bitfield-Mask: 0x07) */ -#define GPDMA0_CH_CTLL_SRC_GATHER_EN_Pos \ - (17UL) /*!< GPDMA0_CH0_1 CTLL: SRC_GATHER_EN (Bit 17) */ -#define GPDMA0_CH_CTLL_SRC_GATHER_EN_Msk \ - (0x20000UL) /*!< GPDMA0_CH0_1 CTLL: SRC_GATHER_EN (Bitfield-Mask: 0x01) */ -#define GPDMA0_CH_CTLL_DST_SCATTER_EN_Pos \ - (18UL) /*!< GPDMA0_CH0_1 CTLL: DST_SCATTER_EN (Bit 18) */ -#define GPDMA0_CH_CTLL_DST_SCATTER_EN_Msk \ - (0x40000UL) /*!< GPDMA0_CH0_1 CTLL: DST_SCATTER_EN (Bitfield-Mask: 0x01) */ -#define GPDMA0_CH_CTLL_TT_FC_Pos \ - (20UL) /*!< GPDMA0_CH0_1 CTLL: TT_FC (Bit 20) */ -#define GPDMA0_CH_CTLL_TT_FC_Msk \ - (0x700000UL) /*!< GPDMA0_CH0_1 CTLL: TT_FC (Bitfield-Mask: 0x07) */ -#define GPDMA0_CH_CTLL_LLP_DST_EN_Pos \ - (27UL) /*!< GPDMA0_CH0_1 CTLL: LLP_DST_EN (Bit 27) */ -#define GPDMA0_CH_CTLL_LLP_DST_EN_Msk \ - (0x8000000UL) /*!< GPDMA0_CH0_1 CTLL: LLP_DST_EN (Bitfield-Mask: 0x01) */ -#define GPDMA0_CH_CTLL_LLP_SRC_EN_Pos \ - (28UL) /*!< GPDMA0_CH0_1 CTLL: LLP_SRC_EN (Bit 28) */ -#define GPDMA0_CH_CTLL_LLP_SRC_EN_Msk \ - (0x10000000UL) /*!< GPDMA0_CH0_1 CTLL: LLP_SRC_EN (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPDMA0_CH_CTLH ----------------------------- */ -#define GPDMA0_CH_CTLH_BLOCK_TS_Pos \ - (0UL) /*!< GPDMA0_CH0_1 CTLH: BLOCK_TS (Bit 0) */ -#define GPDMA0_CH_CTLH_BLOCK_TS_Msk \ - (0xfffUL) /*!< GPDMA0_CH0_1 CTLH: BLOCK_TS (Bitfield-Mask: 0xfff) */ -#define GPDMA0_CH_CTLH_DONE_Pos \ - (12UL) /*!< GPDMA0_CH0_1 CTLH: DONE (Bit 12) */ -#define GPDMA0_CH_CTLH_DONE_Msk \ - (0x1000UL) /*!< GPDMA0_CH0_1 CTLH: DONE (Bitfield-Mask: 0x01) */ - -/* ----------------------------- GPDMA0_CH_SSTAT ----------------------------- */ -#define GPDMA0_CH_SSTAT_SSTAT_Pos \ - (0UL) /*!< GPDMA0_CH0_1 SSTAT: SSTAT (Bit 0) */ -#define GPDMA0_CH_SSTAT_SSTAT_Msk \ - (0xffffffffUL) /*!< GPDMA0_CH0_1 SSTAT: SSTAT (Bitfield-Mask: 0xffffffff) */ - -/* ----------------------------- GPDMA0_CH_DSTAT ----------------------------- */ -#define GPDMA0_CH_DSTAT_DSTAT_Pos \ - (0UL) /*!< GPDMA0_CH0_1 DSTAT: DSTAT (Bit 0) */ -#define GPDMA0_CH_DSTAT_DSTAT_Msk \ - (0xffffffffUL) /*!< GPDMA0_CH0_1 DSTAT: DSTAT (Bitfield-Mask: 0xffffffff) */ - -/* ---------------------------- GPDMA0_CH_SSTATAR ---------------------------- */ -#define GPDMA0_CH_SSTATAR_SSTATAR_Pos \ - (0UL) /*!< GPDMA0_CH0_1 SSTATAR: SSTATAR (Bit 0) */ -#define GPDMA0_CH_SSTATAR_SSTATAR_Msk \ - (0xffffffffUL) /*!< GPDMA0_CH0_1 SSTATAR: SSTATAR (Bitfield-Mask: 0xffffffff) */ - -/* ---------------------------- GPDMA0_CH_DSTATAR ---------------------------- */ -#define GPDMA0_CH_DSTATAR_DSTATAR_Pos \ - (0UL) /*!< GPDMA0_CH0_1 DSTATAR: DSTATAR (Bit 0) */ -#define GPDMA0_CH_DSTATAR_DSTATAR_Msk \ - (0xffffffffUL) /*!< GPDMA0_CH0_1 DSTATAR: DSTATAR (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------ GPDMA0_CH_CFGL ----------------------------- */ -#define GPDMA0_CH_CFGL_CH_PRIOR_Pos \ - (5UL) /*!< GPDMA0_CH0_1 CFGL: CH_PRIOR (Bit 5) */ -#define GPDMA0_CH_CFGL_CH_PRIOR_Msk \ - (0xe0UL) /*!< GPDMA0_CH0_1 CFGL: CH_PRIOR (Bitfield-Mask: 0x07) */ -#define GPDMA0_CH_CFGL_CH_SUSP_Pos \ - (8UL) /*!< GPDMA0_CH0_1 CFGL: CH_SUSP (Bit 8) */ -#define GPDMA0_CH_CFGL_CH_SUSP_Msk \ - (0x100UL) /*!< GPDMA0_CH0_1 CFGL: CH_SUSP (Bitfield-Mask: 0x01) */ -#define GPDMA0_CH_CFGL_FIFO_EMPTY_Pos \ - (9UL) /*!< GPDMA0_CH0_1 CFGL: FIFO_EMPTY (Bit 9) */ -#define GPDMA0_CH_CFGL_FIFO_EMPTY_Msk \ - (0x200UL) /*!< GPDMA0_CH0_1 CFGL: FIFO_EMPTY (Bitfield-Mask: 0x01) */ -#define GPDMA0_CH_CFGL_HS_SEL_DST_Pos \ - (10UL) /*!< GPDMA0_CH0_1 CFGL: HS_SEL_DST (Bit 10) */ -#define GPDMA0_CH_CFGL_HS_SEL_DST_Msk \ - (0x400UL) /*!< GPDMA0_CH0_1 CFGL: HS_SEL_DST (Bitfield-Mask: 0x01) */ -#define GPDMA0_CH_CFGL_HS_SEL_SRC_Pos \ - (11UL) /*!< GPDMA0_CH0_1 CFGL: HS_SEL_SRC (Bit 11) */ -#define GPDMA0_CH_CFGL_HS_SEL_SRC_Msk \ - (0x800UL) /*!< GPDMA0_CH0_1 CFGL: HS_SEL_SRC (Bitfield-Mask: 0x01) */ -#define GPDMA0_CH_CFGL_LOCK_CH_L_Pos \ - (12UL) /*!< GPDMA0_CH0_1 CFGL: LOCK_CH_L (Bit 12) */ -#define GPDMA0_CH_CFGL_LOCK_CH_L_Msk \ - (0x3000UL) /*!< GPDMA0_CH0_1 CFGL: LOCK_CH_L (Bitfield-Mask: 0x03) */ -#define GPDMA0_CH_CFGL_LOCK_B_L_Pos \ - (14UL) /*!< GPDMA0_CH0_1 CFGL: LOCK_B_L (Bit 14) */ -#define GPDMA0_CH_CFGL_LOCK_B_L_Msk \ - (0xc000UL) /*!< GPDMA0_CH0_1 CFGL: LOCK_B_L (Bitfield-Mask: 0x03) */ -#define GPDMA0_CH_CFGL_LOCK_CH_Pos \ - (16UL) /*!< GPDMA0_CH0_1 CFGL: LOCK_CH (Bit 16) */ -#define GPDMA0_CH_CFGL_LOCK_CH_Msk \ - (0x10000UL) /*!< GPDMA0_CH0_1 CFGL: LOCK_CH (Bitfield-Mask: 0x01) */ -#define GPDMA0_CH_CFGL_LOCK_B_Pos \ - (17UL) /*!< GPDMA0_CH0_1 CFGL: LOCK_B (Bit 17) */ -#define GPDMA0_CH_CFGL_LOCK_B_Msk \ - (0x20000UL) /*!< GPDMA0_CH0_1 CFGL: LOCK_B (Bitfield-Mask: 0x01) */ -#define GPDMA0_CH_CFGL_DST_HS_POL_Pos \ - (18UL) /*!< GPDMA0_CH0_1 CFGL: DST_HS_POL (Bit 18) */ -#define GPDMA0_CH_CFGL_DST_HS_POL_Msk \ - (0x40000UL) /*!< GPDMA0_CH0_1 CFGL: DST_HS_POL (Bitfield-Mask: 0x01) */ -#define GPDMA0_CH_CFGL_SRC_HS_POL_Pos \ - (19UL) /*!< GPDMA0_CH0_1 CFGL: SRC_HS_POL (Bit 19) */ -#define GPDMA0_CH_CFGL_SRC_HS_POL_Msk \ - (0x80000UL) /*!< GPDMA0_CH0_1 CFGL: SRC_HS_POL (Bitfield-Mask: 0x01) */ -#define GPDMA0_CH_CFGL_MAX_ABRST_Pos \ - (20UL) /*!< GPDMA0_CH0_1 CFGL: MAX_ABRST (Bit 20) */ -#define GPDMA0_CH_CFGL_MAX_ABRST_Msk \ - (0x3ff00000UL) /*!< GPDMA0_CH0_1 CFGL: MAX_ABRST (Bitfield-Mask: 0x3ff) */ -#define GPDMA0_CH_CFGL_RELOAD_SRC_Pos \ - (30UL) /*!< GPDMA0_CH0_1 CFGL: RELOAD_SRC (Bit 30) */ -#define GPDMA0_CH_CFGL_RELOAD_SRC_Msk \ - (0x40000000UL) /*!< GPDMA0_CH0_1 CFGL: RELOAD_SRC (Bitfield-Mask: 0x01) */ -#define GPDMA0_CH_CFGL_RELOAD_DST_Pos \ - (31UL) /*!< GPDMA0_CH0_1 CFGL: RELOAD_DST (Bit 31) */ -#define GPDMA0_CH_CFGL_RELOAD_DST_Msk \ - (0x80000000UL) /*!< GPDMA0_CH0_1 CFGL: RELOAD_DST (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPDMA0_CH_CFGH ----------------------------- */ -#define GPDMA0_CH_CFGH_FCMODE_Pos \ - (0UL) /*!< GPDMA0_CH0_1 CFGH: FCMODE (Bit 0) */ -#define GPDMA0_CH_CFGH_FCMODE_Msk \ - (0x1UL) /*!< GPDMA0_CH0_1 CFGH: FCMODE (Bitfield-Mask: 0x01) */ -#define GPDMA0_CH_CFGH_FIFO_MODE_Pos \ - (1UL) /*!< GPDMA0_CH0_1 CFGH: FIFO_MODE (Bit 1) */ -#define GPDMA0_CH_CFGH_FIFO_MODE_Msk \ - (0x2UL) /*!< GPDMA0_CH0_1 CFGH: FIFO_MODE (Bitfield-Mask: 0x01) */ -#define GPDMA0_CH_CFGH_PROTCTL_Pos \ - (2UL) /*!< GPDMA0_CH0_1 CFGH: PROTCTL (Bit 2) */ -#define GPDMA0_CH_CFGH_PROTCTL_Msk \ - (0x1cUL) /*!< GPDMA0_CH0_1 CFGH: PROTCTL (Bitfield-Mask: 0x07) */ -#define GPDMA0_CH_CFGH_DS_UPD_EN_Pos \ - (5UL) /*!< GPDMA0_CH0_1 CFGH: DS_UPD_EN (Bit 5) */ -#define GPDMA0_CH_CFGH_DS_UPD_EN_Msk \ - (0x20UL) /*!< GPDMA0_CH0_1 CFGH: DS_UPD_EN (Bitfield-Mask: 0x01) */ -#define GPDMA0_CH_CFGH_SS_UPD_EN_Pos \ - (6UL) /*!< GPDMA0_CH0_1 CFGH: SS_UPD_EN (Bit 6) */ -#define GPDMA0_CH_CFGH_SS_UPD_EN_Msk \ - (0x40UL) /*!< GPDMA0_CH0_1 CFGH: SS_UPD_EN (Bitfield-Mask: 0x01) */ -#define GPDMA0_CH_CFGH_SRC_PER_Pos \ - (7UL) /*!< GPDMA0_CH0_1 CFGH: SRC_PER (Bit 7) */ -#define GPDMA0_CH_CFGH_SRC_PER_Msk \ - (0x780UL) /*!< GPDMA0_CH0_1 CFGH: SRC_PER (Bitfield-Mask: 0x0f) */ -#define GPDMA0_CH_CFGH_DEST_PER_Pos \ - (11UL) /*!< GPDMA0_CH0_1 CFGH: DEST_PER (Bit 11) */ -#define GPDMA0_CH_CFGH_DEST_PER_Msk \ - (0x7800UL) /*!< GPDMA0_CH0_1 CFGH: DEST_PER (Bitfield-Mask: 0x0f) */ - -/* ------------------------------ GPDMA0_CH_SGR ------------------------------ */ -#define GPDMA0_CH_SGR_SGI_Pos \ - (0UL) /*!< GPDMA0_CH0_1 SGR: SGI (Bit 0) */ -#define GPDMA0_CH_SGR_SGI_Msk \ - (0xfffffUL) /*!< GPDMA0_CH0_1 SGR: SGI (Bitfield-Mask: 0xfffff) */ -#define GPDMA0_CH_SGR_SGC_Pos \ - (20UL) /*!< GPDMA0_CH0_1 SGR: SGC (Bit 20) */ -#define GPDMA0_CH_SGR_SGC_Msk \ - (0xfff00000UL) /*!< GPDMA0_CH0_1 SGR: SGC (Bitfield-Mask: 0xfff) */ - -/* ------------------------------ GPDMA0_CH_DSR ------------------------------ */ -#define GPDMA0_CH_DSR_DSI_Pos \ - (0UL) /*!< GPDMA0_CH0_1 DSR: DSI (Bit 0) */ -#define GPDMA0_CH_DSR_DSI_Msk \ - (0xfffffUL) /*!< GPDMA0_CH0_1 DSR: DSI (Bitfield-Mask: 0xfffff) */ -#define GPDMA0_CH_DSR_DSC_Pos \ - (20UL) /*!< GPDMA0_CH0_1 DSR: DSC (Bit 20) */ -#define GPDMA0_CH_DSR_DSC_Msk \ - (0xfff00000UL) /*!< GPDMA0_CH0_1 DSR: DSC (Bitfield-Mask: 0xfff) */ - -/* ================================================================================ */ -/* ================ struct 'FCE' Position & Mask ================ */ -/* ================================================================================ */ - -/* ----------------------------------- FCE_CLC ---------------------------------- */ -#define FCE_CLC_DISR_Pos (0UL) /*!< FCE CLC: DISR (Bit 0) */ -#define FCE_CLC_DISR_Msk (0x1UL) /*!< FCE CLC: DISR (Bitfield-Mask: 0x01) */ -#define FCE_CLC_DISS_Pos (1UL) /*!< FCE CLC: DISS (Bit 1) */ -#define FCE_CLC_DISS_Msk (0x2UL) /*!< FCE CLC: DISS (Bitfield-Mask: 0x01) */ - -/* ----------------------------------- FCE_ID ----------------------------------- */ -#define FCE_ID_MOD_REV_Pos (0UL) /*!< FCE ID: MOD_REV (Bit 0) */ -#define FCE_ID_MOD_REV_Msk \ - (0xffUL) /*!< FCE ID: MOD_REV (Bitfield-Mask: 0xff) */ -#define FCE_ID_MOD_TYPE_Pos \ - (8UL) /*!< FCE ID: MOD_TYPE (Bit 8) */ -#define FCE_ID_MOD_TYPE_Msk \ - (0xff00UL) /*!< FCE ID: MOD_TYPE (Bitfield-Mask: 0xff) */ -#define FCE_ID_MOD_NUMBER_Pos \ - (16UL) /*!< FCE ID: MOD_NUMBER (Bit 16) */ -#define FCE_ID_MOD_NUMBER_Msk \ - (0xffff0000UL) /*!< FCE ID: MOD_NUMBER (Bitfield-Mask: 0xffff) */ - -/* ================================================================================ */ -/* ================ Group 'FCE_KE' Position & Mask ================ */ -/* ================================================================================ */ - -/* ---------------------------------- FCE_KE_IR --------------------------------- */ -#define FCE_KE_IR_IR_Pos (0UL) /*!< FCE_KE IR: IR (Bit 0) */ -#define FCE_KE_IR_IR_Msk \ - (0xffffffffUL) /*!< FCE_KE IR: IR (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------------- FCE_KE_RES --------------------------------- */ -#define FCE_KE_RES_RES_Pos (0UL) /*!< FCE_KE RES: RES (Bit 0) */ -#define FCE_KE_RES_RES_Msk \ - (0xffffffffUL) /*!< FCE_KE RES: RES (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------------- FCE_KE_CFG --------------------------------- */ -#define FCE_KE_CFG_CMI_Pos (0UL) /*!< FCE_KE CFG: CMI (Bit 0) */ -#define FCE_KE_CFG_CMI_Msk \ - (0x1UL) /*!< FCE_KE CFG: CMI (Bitfield-Mask: 0x01) */ -#define FCE_KE_CFG_CEI_Pos (1UL) /*!< FCE_KE CFG: CEI (Bit 1) */ -#define FCE_KE_CFG_CEI_Msk \ - (0x2UL) /*!< FCE_KE CFG: CEI (Bitfield-Mask: 0x01) */ -#define FCE_KE_CFG_LEI_Pos (2UL) /*!< FCE_KE CFG: LEI (Bit 2) */ -#define FCE_KE_CFG_LEI_Msk \ - (0x4UL) /*!< FCE_KE CFG: LEI (Bitfield-Mask: 0x01) */ -#define FCE_KE_CFG_BEI_Pos (3UL) /*!< FCE_KE CFG: BEI (Bit 3) */ -#define FCE_KE_CFG_BEI_Msk \ - (0x8UL) /*!< FCE_KE CFG: BEI (Bitfield-Mask: 0x01) */ -#define FCE_KE_CFG_CCE_Pos (4UL) /*!< FCE_KE CFG: CCE (Bit 4) */ -#define FCE_KE_CFG_CCE_Msk \ - (0x10UL) /*!< FCE_KE CFG: CCE (Bitfield-Mask: 0x01) */ -#define FCE_KE_CFG_ALR_Pos (5UL) /*!< FCE_KE CFG: ALR (Bit 5) */ -#define FCE_KE_CFG_ALR_Msk \ - (0x20UL) /*!< FCE_KE CFG: ALR (Bitfield-Mask: 0x01) */ -#define FCE_KE_CFG_REFIN_Pos \ - (8UL) /*!< FCE_KE CFG: REFIN (Bit 8) */ -#define FCE_KE_CFG_REFIN_Msk \ - (0x100UL) /*!< FCE_KE CFG: REFIN (Bitfield-Mask: 0x01) */ -#define FCE_KE_CFG_REFOUT_Pos \ - (9UL) /*!< FCE_KE CFG: REFOUT (Bit 9) */ -#define FCE_KE_CFG_REFOUT_Msk \ - (0x200UL) /*!< FCE_KE CFG: REFOUT (Bitfield-Mask: 0x01) */ -#define FCE_KE_CFG_XSEL_Pos \ - (10UL) /*!< FCE_KE CFG: XSEL (Bit 10) */ -#define FCE_KE_CFG_XSEL_Msk \ - (0x400UL) /*!< FCE_KE CFG: XSEL (Bitfield-Mask: 0x01) */ - -/* --------------------------------- FCE_KE_STS --------------------------------- */ -#define FCE_KE_STS_CMF_Pos (0UL) /*!< FCE_KE STS: CMF (Bit 0) */ -#define FCE_KE_STS_CMF_Msk \ - (0x1UL) /*!< FCE_KE STS: CMF (Bitfield-Mask: 0x01) */ -#define FCE_KE_STS_CEF_Pos (1UL) /*!< FCE_KE STS: CEF (Bit 1) */ -#define FCE_KE_STS_CEF_Msk \ - (0x2UL) /*!< FCE_KE STS: CEF (Bitfield-Mask: 0x01) */ -#define FCE_KE_STS_LEF_Pos (2UL) /*!< FCE_KE STS: LEF (Bit 2) */ -#define FCE_KE_STS_LEF_Msk \ - (0x4UL) /*!< FCE_KE STS: LEF (Bitfield-Mask: 0x01) */ -#define FCE_KE_STS_BEF_Pos (3UL) /*!< FCE_KE STS: BEF (Bit 3) */ -#define FCE_KE_STS_BEF_Msk \ - (0x8UL) /*!< FCE_KE STS: BEF (Bitfield-Mask: 0x01) */ - -/* -------------------------------- FCE_KE_LENGTH ------------------------------- */ -#define FCE_KE_LENGTH_LENGTH_Pos \ - (0UL) /*!< FCE_KE LENGTH: LENGTH (Bit 0) */ -#define FCE_KE_LENGTH_LENGTH_Msk \ - (0xffffUL) /*!< FCE_KE LENGTH: LENGTH (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- FCE_KE_CHECK -------------------------------- */ -#define FCE_KE_CHECK_CHECK_Pos \ - (0UL) /*!< FCE_KE CHECK: CHECK (Bit 0) */ -#define FCE_KE_CHECK_CHECK_Msk \ - (0xffffffffUL) /*!< FCE_KE CHECK: CHECK (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------------- FCE_KE_CRC --------------------------------- */ -#define FCE_KE_CRC_CRC_Pos (0UL) /*!< FCE_KE CRC: CRC (Bit 0) */ -#define FCE_KE_CRC_CRC_Msk \ - (0xffffffffUL) /*!< FCE_KE CRC: CRC (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------------- FCE_KE_CTR --------------------------------- */ -#define FCE_KE_CTR_FCM_Pos (0UL) /*!< FCE_KE CTR: FCM (Bit 0) */ -#define FCE_KE_CTR_FCM_Msk \ - (0x1UL) /*!< FCE_KE CTR: FCM (Bitfield-Mask: 0x01) */ -#define FCE_KE_CTR_FRM_CFG_Pos \ - (1UL) /*!< FCE_KE CTR: FRM_CFG (Bit 1) */ -#define FCE_KE_CTR_FRM_CFG_Msk \ - (0x2UL) /*!< FCE_KE CTR: FRM_CFG (Bitfield-Mask: 0x01) */ -#define FCE_KE_CTR_FRM_CHECK_Pos \ - (2UL) /*!< FCE_KE CTR: FRM_CHECK (Bit 2) */ -#define FCE_KE_CTR_FRM_CHECK_Msk \ - (0x4UL) /*!< FCE_KE CTR: FRM_CHECK (Bitfield-Mask: 0x01) */ - -/* ================================================================================ */ -/* ================ Group 'PBA' Position & Mask ================ */ -/* ================================================================================ */ - -/* ----------------------------------- PBA_STS ---------------------------------- */ -#define PBA_STS_WERR_Pos (0UL) /*!< PBA STS: WERR (Bit 0) */ -#define PBA_STS_WERR_Msk (0x1UL) /*!< PBA STS: WERR (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- PBA_WADDR --------------------------------- */ -#define PBA_WADDR_WADDR_Pos \ - (0UL) /*!< PBA WADDR: WADDR (Bit 0) */ -#define PBA_WADDR_WADDR_Msk \ - (0xffffffffUL) /*!< PBA WADDR: WADDR (Bitfield-Mask: 0xffffffff) */ - -/* ================================================================================ */ -/* ================ Group 'FLASH' Position & Mask ================ */ -/* ================================================================================ */ - -/* ---------------------------------- FLASH_ID ---------------------------------- */ -#define FLASH_ID_MOD_REV_Pos \ - (0UL) /*!< FLASH ID: MOD_REV (Bit 0) */ -#define FLASH_ID_MOD_REV_Msk \ - (0xffUL) /*!< FLASH ID: MOD_REV (Bitfield-Mask: 0xff) */ -#define FLASH_ID_MOD_TYPE_Pos \ - (8UL) /*!< FLASH ID: MOD_TYPE (Bit 8) */ -#define FLASH_ID_MOD_TYPE_Msk \ - (0xff00UL) /*!< FLASH ID: MOD_TYPE (Bitfield-Mask: 0xff) */ -#define FLASH_ID_MOD_NUMBER_Pos \ - (16UL) /*!< FLASH ID: MOD_NUMBER (Bit 16) */ -#define FLASH_ID_MOD_NUMBER_Msk \ - (0xffff0000UL) /*!< FLASH ID: MOD_NUMBER (Bitfield-Mask: 0xffff) */ - -/* ---------------------------------- FLASH_FSR --------------------------------- */ -#define FLASH_FSR_PBUSY_Pos \ - (0UL) /*!< FLASH FSR: PBUSY (Bit 0) */ -#define FLASH_FSR_PBUSY_Msk \ - (0x1UL) /*!< FLASH FSR: PBUSY (Bitfield-Mask: 0x01) */ -#define FLASH_FSR_FABUSY_Pos \ - (1UL) /*!< FLASH FSR: FABUSY (Bit 1) */ -#define FLASH_FSR_FABUSY_Msk \ - (0x2UL) /*!< FLASH FSR: FABUSY (Bitfield-Mask: 0x01) */ -#define FLASH_FSR_PROG_Pos (4UL) /*!< FLASH FSR: PROG (Bit 4) */ -#define FLASH_FSR_PROG_Msk \ - (0x10UL) /*!< FLASH FSR: PROG (Bitfield-Mask: 0x01) */ -#define FLASH_FSR_ERASE_Pos \ - (5UL) /*!< FLASH FSR: ERASE (Bit 5) */ -#define FLASH_FSR_ERASE_Msk \ - (0x20UL) /*!< FLASH FSR: ERASE (Bitfield-Mask: 0x01) */ -#define FLASH_FSR_PFPAGE_Pos \ - (6UL) /*!< FLASH FSR: PFPAGE (Bit 6) */ -#define FLASH_FSR_PFPAGE_Msk \ - (0x40UL) /*!< FLASH FSR: PFPAGE (Bitfield-Mask: 0x01) */ -#define FLASH_FSR_PFOPER_Pos \ - (8UL) /*!< FLASH FSR: PFOPER (Bit 8) */ -#define FLASH_FSR_PFOPER_Msk \ - (0x100UL) /*!< FLASH FSR: PFOPER (Bitfield-Mask: 0x01) */ -#define FLASH_FSR_SQER_Pos \ - (10UL) /*!< FLASH FSR: SQER (Bit 10) */ -#define FLASH_FSR_SQER_Msk \ - (0x400UL) /*!< FLASH FSR: SQER (Bitfield-Mask: 0x01) */ -#define FLASH_FSR_PROER_Pos \ - (11UL) /*!< FLASH FSR: PROER (Bit 11) */ -#define FLASH_FSR_PROER_Msk \ - (0x800UL) /*!< FLASH FSR: PROER (Bitfield-Mask: 0x01) */ -#define FLASH_FSR_PFSBER_Pos \ - (12UL) /*!< FLASH FSR: PFSBER (Bit 12) */ -#define FLASH_FSR_PFSBER_Msk \ - (0x1000UL) /*!< FLASH FSR: PFSBER (Bitfield-Mask: 0x01) */ -#define FLASH_FSR_PFDBER_Pos \ - (14UL) /*!< FLASH FSR: PFDBER (Bit 14) */ -#define FLASH_FSR_PFDBER_Msk \ - (0x4000UL) /*!< FLASH FSR: PFDBER (Bitfield-Mask: 0x01) */ -#define FLASH_FSR_PROIN_Pos \ - (16UL) /*!< FLASH FSR: PROIN (Bit 16) */ -#define FLASH_FSR_PROIN_Msk \ - (0x10000UL) /*!< FLASH FSR: PROIN (Bitfield-Mask: 0x01) */ -#define FLASH_FSR_RPROIN_Pos \ - (18UL) /*!< FLASH FSR: RPROIN (Bit 18) */ -#define FLASH_FSR_RPROIN_Msk \ - (0x40000UL) /*!< FLASH FSR: RPROIN (Bitfield-Mask: 0x01) */ -#define FLASH_FSR_RPRODIS_Pos \ - (19UL) /*!< FLASH FSR: RPRODIS (Bit 19) */ -#define FLASH_FSR_RPRODIS_Msk \ - (0x80000UL) /*!< FLASH FSR: RPRODIS (Bitfield-Mask: 0x01) */ -#define FLASH_FSR_WPROIN0_Pos \ - (21UL) /*!< FLASH FSR: WPROIN0 (Bit 21) */ -#define FLASH_FSR_WPROIN0_Msk \ - (0x200000UL) /*!< FLASH FSR: WPROIN0 (Bitfield-Mask: 0x01) */ -#define FLASH_FSR_WPROIN1_Pos \ - (22UL) /*!< FLASH FSR: WPROIN1 (Bit 22) */ -#define FLASH_FSR_WPROIN1_Msk \ - (0x400000UL) /*!< FLASH FSR: WPROIN1 (Bitfield-Mask: 0x01) */ -#define FLASH_FSR_WPROIN2_Pos \ - (23UL) /*!< FLASH FSR: WPROIN2 (Bit 23) */ -#define FLASH_FSR_WPROIN2_Msk \ - (0x800000UL) /*!< FLASH FSR: WPROIN2 (Bitfield-Mask: 0x01) */ -#define FLASH_FSR_WPRODIS0_Pos \ - (25UL) /*!< FLASH FSR: WPRODIS0 (Bit 25) */ -#define FLASH_FSR_WPRODIS0_Msk \ - (0x2000000UL) /*!< FLASH FSR: WPRODIS0 (Bitfield-Mask: 0x01) */ -#define FLASH_FSR_WPRODIS1_Pos \ - (26UL) /*!< FLASH FSR: WPRODIS1 (Bit 26) */ -#define FLASH_FSR_WPRODIS1_Msk \ - (0x4000000UL) /*!< FLASH FSR: WPRODIS1 (Bitfield-Mask: 0x01) */ -#define FLASH_FSR_SLM_Pos (28UL) /*!< FLASH FSR: SLM (Bit 28) */ -#define FLASH_FSR_SLM_Msk \ - (0x10000000UL) /*!< FLASH FSR: SLM (Bitfield-Mask: 0x01) */ -#define FLASH_FSR_VER_Pos (31UL) /*!< FLASH FSR: VER (Bit 31) */ -#define FLASH_FSR_VER_Msk \ - (0x80000000UL) /*!< FLASH FSR: VER (Bitfield-Mask: 0x01) */ - -/* --------------------------------- FLASH_FCON --------------------------------- */ -#define FLASH_FCON_WSPFLASH_Pos \ - (0UL) /*!< FLASH FCON: WSPFLASH (Bit 0) */ -#define FLASH_FCON_WSPFLASH_Msk \ - (0xfUL) /*!< FLASH FCON: WSPFLASH (Bitfield-Mask: 0x0f) */ -#define FLASH_FCON_WSECPF_Pos \ - (4UL) /*!< FLASH FCON: WSECPF (Bit 4) */ -#define FLASH_FCON_WSECPF_Msk \ - (0x10UL) /*!< FLASH FCON: WSECPF (Bitfield-Mask: 0x01) */ -#define FLASH_FCON_IDLE_Pos \ - (13UL) /*!< FLASH FCON: IDLE (Bit 13) */ -#define FLASH_FCON_IDLE_Msk \ - (0x2000UL) /*!< FLASH FCON: IDLE (Bitfield-Mask: 0x01) */ -#define FLASH_FCON_ESLDIS_Pos \ - (14UL) /*!< FLASH FCON: ESLDIS (Bit 14) */ -#define FLASH_FCON_ESLDIS_Msk \ - (0x4000UL) /*!< FLASH FCON: ESLDIS (Bitfield-Mask: 0x01) */ -#define FLASH_FCON_SLEEP_Pos \ - (15UL) /*!< FLASH FCON: SLEEP (Bit 15) */ -#define FLASH_FCON_SLEEP_Msk \ - (0x8000UL) /*!< FLASH FCON: SLEEP (Bitfield-Mask: 0x01) */ -#define FLASH_FCON_RPA_Pos \ - (16UL) /*!< FLASH FCON: RPA (Bit 16) */ -#define FLASH_FCON_RPA_Msk \ - (0x10000UL) /*!< FLASH FCON: RPA (Bitfield-Mask: 0x01) */ -#define FLASH_FCON_DCF_Pos \ - (17UL) /*!< FLASH FCON: DCF (Bit 17) */ -#define FLASH_FCON_DCF_Msk \ - (0x20000UL) /*!< FLASH FCON: DCF (Bitfield-Mask: 0x01) */ -#define FLASH_FCON_DDF_Pos \ - (18UL) /*!< FLASH FCON: DDF (Bit 18) */ -#define FLASH_FCON_DDF_Msk \ - (0x40000UL) /*!< FLASH FCON: DDF (Bitfield-Mask: 0x01) */ -#define FLASH_FCON_VOPERM_Pos \ - (24UL) /*!< FLASH FCON: VOPERM (Bit 24) */ -#define FLASH_FCON_VOPERM_Msk \ - (0x1000000UL) /*!< FLASH FCON: VOPERM (Bitfield-Mask: 0x01) */ -#define FLASH_FCON_SQERM_Pos \ - (25UL) /*!< FLASH FCON: SQERM (Bit 25) */ -#define FLASH_FCON_SQERM_Msk \ - (0x2000000UL) /*!< FLASH FCON: SQERM (Bitfield-Mask: 0x01) */ -#define FLASH_FCON_PROERM_Pos \ - (26UL) /*!< FLASH FCON: PROERM (Bit 26) */ -#define FLASH_FCON_PROERM_Msk \ - (0x4000000UL) /*!< FLASH FCON: PROERM (Bitfield-Mask: 0x01) */ -#define FLASH_FCON_PFSBERM_Pos \ - (27UL) /*!< FLASH FCON: PFSBERM (Bit 27) */ -#define FLASH_FCON_PFSBERM_Msk \ - (0x8000000UL) /*!< FLASH FCON: PFSBERM (Bitfield-Mask: 0x01) */ -#define FLASH_FCON_PFDBERM_Pos \ - (29UL) /*!< FLASH FCON: PFDBERM (Bit 29) */ -#define FLASH_FCON_PFDBERM_Msk \ - (0x20000000UL) /*!< FLASH FCON: PFDBERM (Bitfield-Mask: 0x01) */ -#define FLASH_FCON_EOBM_Pos \ - (31UL) /*!< FLASH FCON: EOBM (Bit 31) */ -#define FLASH_FCON_EOBM_Msk \ - (0x80000000UL) /*!< FLASH FCON: EOBM (Bitfield-Mask: 0x01) */ - -/* --------------------------------- FLASH_MARP --------------------------------- */ -#define FLASH_MARP_MARGIN_Pos \ - (0UL) /*!< FLASH MARP: MARGIN (Bit 0) */ -#define FLASH_MARP_MARGIN_Msk \ - (0xfUL) /*!< FLASH MARP: MARGIN (Bitfield-Mask: 0x0f) */ -#define FLASH_MARP_TRAPDIS_Pos \ - (15UL) /*!< FLASH MARP: TRAPDIS (Bit 15) */ -#define FLASH_MARP_TRAPDIS_Msk \ - (0x8000UL) /*!< FLASH MARP: TRAPDIS (Bitfield-Mask: 0x01) */ - -/* -------------------------------- FLASH_PROCON0 ------------------------------- */ -#define FLASH_PROCON0_S0L_Pos \ - (0UL) /*!< FLASH PROCON0: S0L (Bit 0) */ -#define FLASH_PROCON0_S0L_Msk \ - (0x1UL) /*!< FLASH PROCON0: S0L (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON0_S1L_Pos \ - (1UL) /*!< FLASH PROCON0: S1L (Bit 1) */ -#define FLASH_PROCON0_S1L_Msk \ - (0x2UL) /*!< FLASH PROCON0: S1L (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON0_S2L_Pos \ - (2UL) /*!< FLASH PROCON0: S2L (Bit 2) */ -#define FLASH_PROCON0_S2L_Msk \ - (0x4UL) /*!< FLASH PROCON0: S2L (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON0_S3L_Pos \ - (3UL) /*!< FLASH PROCON0: S3L (Bit 3) */ -#define FLASH_PROCON0_S3L_Msk \ - (0x8UL) /*!< FLASH PROCON0: S3L (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON0_S4L_Pos \ - (4UL) /*!< FLASH PROCON0: S4L (Bit 4) */ -#define FLASH_PROCON0_S4L_Msk \ - (0x10UL) /*!< FLASH PROCON0: S4L (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON0_S5L_Pos \ - (5UL) /*!< FLASH PROCON0: S5L (Bit 5) */ -#define FLASH_PROCON0_S5L_Msk \ - (0x20UL) /*!< FLASH PROCON0: S5L (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON0_S6L_Pos \ - (6UL) /*!< FLASH PROCON0: S6L (Bit 6) */ -#define FLASH_PROCON0_S6L_Msk \ - (0x40UL) /*!< FLASH PROCON0: S6L (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON0_S7L_Pos \ - (7UL) /*!< FLASH PROCON0: S7L (Bit 7) */ -#define FLASH_PROCON0_S7L_Msk \ - (0x80UL) /*!< FLASH PROCON0: S7L (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON0_S8L_Pos \ - (8UL) /*!< FLASH PROCON0: S8L (Bit 8) */ -#define FLASH_PROCON0_S8L_Msk \ - (0x100UL) /*!< FLASH PROCON0: S8L (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON0_RPRO_Pos \ - (15UL) /*!< FLASH PROCON0: RPRO (Bit 15) */ -#define FLASH_PROCON0_RPRO_Msk \ - (0x8000UL) /*!< FLASH PROCON0: RPRO (Bitfield-Mask: 0x01) */ - -/* -------------------------------- FLASH_PROCON1 ------------------------------- */ -#define FLASH_PROCON1_S0L_Pos \ - (0UL) /*!< FLASH PROCON1: S0L (Bit 0) */ -#define FLASH_PROCON1_S0L_Msk \ - (0x1UL) /*!< FLASH PROCON1: S0L (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON1_S1L_Pos \ - (1UL) /*!< FLASH PROCON1: S1L (Bit 1) */ -#define FLASH_PROCON1_S1L_Msk \ - (0x2UL) /*!< FLASH PROCON1: S1L (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON1_S2L_Pos \ - (2UL) /*!< FLASH PROCON1: S2L (Bit 2) */ -#define FLASH_PROCON1_S2L_Msk \ - (0x4UL) /*!< FLASH PROCON1: S2L (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON1_S3L_Pos \ - (3UL) /*!< FLASH PROCON1: S3L (Bit 3) */ -#define FLASH_PROCON1_S3L_Msk \ - (0x8UL) /*!< FLASH PROCON1: S3L (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON1_S4L_Pos \ - (4UL) /*!< FLASH PROCON1: S4L (Bit 4) */ -#define FLASH_PROCON1_S4L_Msk \ - (0x10UL) /*!< FLASH PROCON1: S4L (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON1_S5L_Pos \ - (5UL) /*!< FLASH PROCON1: S5L (Bit 5) */ -#define FLASH_PROCON1_S5L_Msk \ - (0x20UL) /*!< FLASH PROCON1: S5L (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON1_S6L_Pos \ - (6UL) /*!< FLASH PROCON1: S6L (Bit 6) */ -#define FLASH_PROCON1_S6L_Msk \ - (0x40UL) /*!< FLASH PROCON1: S6L (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON1_S7L_Pos \ - (7UL) /*!< FLASH PROCON1: S7L (Bit 7) */ -#define FLASH_PROCON1_S7L_Msk \ - (0x80UL) /*!< FLASH PROCON1: S7L (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON1_S8L_Pos \ - (8UL) /*!< FLASH PROCON1: S8L (Bit 8) */ -#define FLASH_PROCON1_S8L_Msk \ - (0x100UL) /*!< FLASH PROCON1: S8L (Bitfield-Mask: 0x01) */ - -/* -------------------------------- FLASH_PROCON2 ------------------------------- */ -#define FLASH_PROCON2_S0ROM_Pos \ - (0UL) /*!< FLASH PROCON2: S0ROM (Bit 0) */ -#define FLASH_PROCON2_S0ROM_Msk \ - (0x1UL) /*!< FLASH PROCON2: S0ROM (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON2_S1ROM_Pos \ - (1UL) /*!< FLASH PROCON2: S1ROM (Bit 1) */ -#define FLASH_PROCON2_S1ROM_Msk \ - (0x2UL) /*!< FLASH PROCON2: S1ROM (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON2_S2ROM_Pos \ - (2UL) /*!< FLASH PROCON2: S2ROM (Bit 2) */ -#define FLASH_PROCON2_S2ROM_Msk \ - (0x4UL) /*!< FLASH PROCON2: S2ROM (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON2_S3ROM_Pos \ - (3UL) /*!< FLASH PROCON2: S3ROM (Bit 3) */ -#define FLASH_PROCON2_S3ROM_Msk \ - (0x8UL) /*!< FLASH PROCON2: S3ROM (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON2_S4ROM_Pos \ - (4UL) /*!< FLASH PROCON2: S4ROM (Bit 4) */ -#define FLASH_PROCON2_S4ROM_Msk \ - (0x10UL) /*!< FLASH PROCON2: S4ROM (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON2_S5ROM_Pos \ - (5UL) /*!< FLASH PROCON2: S5ROM (Bit 5) */ -#define FLASH_PROCON2_S5ROM_Msk \ - (0x20UL) /*!< FLASH PROCON2: S5ROM (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON2_S6ROM_Pos \ - (6UL) /*!< FLASH PROCON2: S6ROM (Bit 6) */ -#define FLASH_PROCON2_S6ROM_Msk \ - (0x40UL) /*!< FLASH PROCON2: S6ROM (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON2_S7ROM_Pos \ - (7UL) /*!< FLASH PROCON2: S7ROM (Bit 7) */ -#define FLASH_PROCON2_S7ROM_Msk \ - (0x80UL) /*!< FLASH PROCON2: S7ROM (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON2_S8ROM_Pos \ - (8UL) /*!< FLASH PROCON2: S8ROM (Bit 8) */ -#define FLASH_PROCON2_S8ROM_Msk \ - (0x100UL) /*!< FLASH PROCON2: S8ROM (Bitfield-Mask: 0x01) */ - -/* ================================================================================ */ -/* ================ struct 'PREF' Position & Mask ================ */ -/* ================================================================================ */ - -/* ---------------------------------- PREF_PCON --------------------------------- */ -#define PREF_PCON_IBYP_Pos (0UL) /*!< PREF PCON: IBYP (Bit 0) */ -#define PREF_PCON_IBYP_Msk \ - (0x1UL) /*!< PREF PCON: IBYP (Bitfield-Mask: 0x01) */ -#define PREF_PCON_IINV_Pos (1UL) /*!< PREF PCON: IINV (Bit 1) */ -#define PREF_PCON_IINV_Msk \ - (0x2UL) /*!< PREF PCON: IINV (Bitfield-Mask: 0x01) */ -#define PREF_PCON_DBYP_Pos (4UL) /*!< PREF PCON: DBYP (Bit 4) */ -#define PREF_PCON_DBYP_Msk \ - (0x10UL) /*!< PREF PCON: DBYP (Bitfield-Mask: 0x01) */ - -/* ================================================================================ */ -/* ================ Group 'PMU' Position & Mask ================ */ -/* ================================================================================ */ - -/* ----------------------------------- PMU_ID ----------------------------------- */ -#define PMU_ID_MOD_REV_Pos (0UL) /*!< PMU ID: MOD_REV (Bit 0) */ -#define PMU_ID_MOD_REV_Msk \ - (0xffUL) /*!< PMU ID: MOD_REV (Bitfield-Mask: 0xff) */ -#define PMU_ID_MOD_TYPE_Pos \ - (8UL) /*!< PMU ID: MOD_TYPE (Bit 8) */ -#define PMU_ID_MOD_TYPE_Msk \ - (0xff00UL) /*!< PMU ID: MOD_TYPE (Bitfield-Mask: 0xff) */ -#define PMU_ID_MOD_NUMBER_Pos \ - (16UL) /*!< PMU ID: MOD_NUMBER (Bit 16) */ -#define PMU_ID_MOD_NUMBER_Msk \ - (0xffff0000UL) /*!< PMU ID: MOD_NUMBER (Bitfield-Mask: 0xffff) */ - -/* ================================================================================ */ -/* ================ struct 'WDT' Position & Mask ================ */ -/* ================================================================================ */ - -/* ----------------------------------- WDT_ID ----------------------------------- */ -#define WDT_ID_MOD_REV_Pos (0UL) /*!< WDT ID: MOD_REV (Bit 0) */ -#define WDT_ID_MOD_REV_Msk \ - (0xffUL) /*!< WDT ID: MOD_REV (Bitfield-Mask: 0xff) */ -#define WDT_ID_MOD_TYPE_Pos \ - (8UL) /*!< WDT ID: MOD_TYPE (Bit 8) */ -#define WDT_ID_MOD_TYPE_Msk \ - (0xff00UL) /*!< WDT ID: MOD_TYPE (Bitfield-Mask: 0xff) */ -#define WDT_ID_MOD_NUMBER_Pos \ - (16UL) /*!< WDT ID: MOD_NUMBER (Bit 16) */ -#define WDT_ID_MOD_NUMBER_Msk \ - (0xffff0000UL) /*!< WDT ID: MOD_NUMBER (Bitfield-Mask: 0xffff) */ - -/* ----------------------------------- WDT_CTR ---------------------------------- */ -#define WDT_CTR_ENB_Pos (0UL) /*!< WDT CTR: ENB (Bit 0) */ -#define WDT_CTR_ENB_Msk (0x1UL) /*!< WDT CTR: ENB (Bitfield-Mask: 0x01) */ -#define WDT_CTR_PRE_Pos (1UL) /*!< WDT CTR: PRE (Bit 1) */ -#define WDT_CTR_PRE_Msk (0x2UL) /*!< WDT CTR: PRE (Bitfield-Mask: 0x01) */ -#define WDT_CTR_DSP_Pos (4UL) /*!< WDT CTR: DSP (Bit 4) */ -#define WDT_CTR_DSP_Msk (0x10UL) /*!< WDT CTR: DSP (Bitfield-Mask: 0x01) */ -#define WDT_CTR_SPW_Pos (8UL) /*!< WDT CTR: SPW (Bit 8) */ -#define WDT_CTR_SPW_Msk \ - (0xff00UL) /*!< WDT CTR: SPW (Bitfield-Mask: 0xff) */ - -/* ----------------------------------- WDT_SRV ---------------------------------- */ -#define WDT_SRV_SRV_Pos (0UL) /*!< WDT SRV: SRV (Bit 0) */ -#define WDT_SRV_SRV_Msk \ - (0xffffffffUL) /*!< WDT SRV: SRV (Bitfield-Mask: 0xffffffff) */ - -/* ----------------------------------- WDT_TIM ---------------------------------- */ -#define WDT_TIM_TIM_Pos (0UL) /*!< WDT TIM: TIM (Bit 0) */ -#define WDT_TIM_TIM_Msk \ - (0xffffffffUL) /*!< WDT TIM: TIM (Bitfield-Mask: 0xffffffff) */ - -/* ----------------------------------- WDT_WLB ---------------------------------- */ -#define WDT_WLB_WLB_Pos (0UL) /*!< WDT WLB: WLB (Bit 0) */ -#define WDT_WLB_WLB_Msk \ - (0xffffffffUL) /*!< WDT WLB: WLB (Bitfield-Mask: 0xffffffff) */ - -/* ----------------------------------- WDT_WUB ---------------------------------- */ -#define WDT_WUB_WUB_Pos (0UL) /*!< WDT WUB: WUB (Bit 0) */ -#define WDT_WUB_WUB_Msk \ - (0xffffffffUL) /*!< WDT WUB: WUB (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------------- WDT_WDTSTS --------------------------------- */ -#define WDT_WDTSTS_ALMS_Pos \ - (0UL) /*!< WDT WDTSTS: ALMS (Bit 0) */ -#define WDT_WDTSTS_ALMS_Msk \ - (0x1UL) /*!< WDT WDTSTS: ALMS (Bitfield-Mask: 0x01) */ - -/* --------------------------------- WDT_WDTCLR --------------------------------- */ -#define WDT_WDTCLR_ALMC_Pos \ - (0UL) /*!< WDT WDTCLR: ALMC (Bit 0) */ -#define WDT_WDTCLR_ALMC_Msk \ - (0x1UL) /*!< WDT WDTCLR: ALMC (Bitfield-Mask: 0x01) */ - -/* ================================================================================ */ -/* ================ struct 'RTC' Position & Mask ================ */ -/* ================================================================================ */ - -/* ----------------------------------- RTC_ID ----------------------------------- */ -#define RTC_ID_MOD_REV_Pos (0UL) /*!< RTC ID: MOD_REV (Bit 0) */ -#define RTC_ID_MOD_REV_Msk \ - (0xffUL) /*!< RTC ID: MOD_REV (Bitfield-Mask: 0xff) */ -#define RTC_ID_MOD_TYPE_Pos \ - (8UL) /*!< RTC ID: MOD_TYPE (Bit 8) */ -#define RTC_ID_MOD_TYPE_Msk \ - (0xff00UL) /*!< RTC ID: MOD_TYPE (Bitfield-Mask: 0xff) */ -#define RTC_ID_MOD_NUMBER_Pos \ - (16UL) /*!< RTC ID: MOD_NUMBER (Bit 16) */ -#define RTC_ID_MOD_NUMBER_Msk \ - (0xffff0000UL) /*!< RTC ID: MOD_NUMBER (Bitfield-Mask: 0xffff) */ - -/* ----------------------------------- RTC_CTR ---------------------------------- */ -#define RTC_CTR_ENB_Pos (0UL) /*!< RTC CTR: ENB (Bit 0) */ -#define RTC_CTR_ENB_Msk (0x1UL) /*!< RTC CTR: ENB (Bitfield-Mask: 0x01) */ -#define RTC_CTR_TAE_Pos (2UL) /*!< RTC CTR: TAE (Bit 2) */ -#define RTC_CTR_TAE_Msk (0x4UL) /*!< RTC CTR: TAE (Bitfield-Mask: 0x01) */ -#define RTC_CTR_ESEC_Pos (8UL) /*!< RTC CTR: ESEC (Bit 8) */ -#define RTC_CTR_ESEC_Msk \ - (0x100UL) /*!< RTC CTR: ESEC (Bitfield-Mask: 0x01) */ -#define RTC_CTR_EMIC_Pos (9UL) /*!< RTC CTR: EMIC (Bit 9) */ -#define RTC_CTR_EMIC_Msk \ - (0x200UL) /*!< RTC CTR: EMIC (Bitfield-Mask: 0x01) */ -#define RTC_CTR_EHOC_Pos (10UL) /*!< RTC CTR: EHOC (Bit 10) */ -#define RTC_CTR_EHOC_Msk \ - (0x400UL) /*!< RTC CTR: EHOC (Bitfield-Mask: 0x01) */ -#define RTC_CTR_EDAC_Pos (11UL) /*!< RTC CTR: EDAC (Bit 11) */ -#define RTC_CTR_EDAC_Msk \ - (0x800UL) /*!< RTC CTR: EDAC (Bitfield-Mask: 0x01) */ -#define RTC_CTR_EMOC_Pos (13UL) /*!< RTC CTR: EMOC (Bit 13) */ -#define RTC_CTR_EMOC_Msk \ - (0x2000UL) /*!< RTC CTR: EMOC (Bitfield-Mask: 0x01) */ -#define RTC_CTR_EYEC_Pos (14UL) /*!< RTC CTR: EYEC (Bit 14) */ -#define RTC_CTR_EYEC_Msk \ - (0x4000UL) /*!< RTC CTR: EYEC (Bitfield-Mask: 0x01) */ -#define RTC_CTR_DIV_Pos (16UL) /*!< RTC CTR: DIV (Bit 16) */ -#define RTC_CTR_DIV_Msk \ - (0xffff0000UL) /*!< RTC CTR: DIV (Bitfield-Mask: 0xffff) */ - -/* --------------------------------- RTC_RAWSTAT -------------------------------- */ -#define RTC_RAWSTAT_RPSE_Pos \ - (0UL) /*!< RTC RAWSTAT: RPSE (Bit 0) */ -#define RTC_RAWSTAT_RPSE_Msk \ - (0x1UL) /*!< RTC RAWSTAT: RPSE (Bitfield-Mask: 0x01) */ -#define RTC_RAWSTAT_RPMI_Pos \ - (1UL) /*!< RTC RAWSTAT: RPMI (Bit 1) */ -#define RTC_RAWSTAT_RPMI_Msk \ - (0x2UL) /*!< RTC RAWSTAT: RPMI (Bitfield-Mask: 0x01) */ -#define RTC_RAWSTAT_RPHO_Pos \ - (2UL) /*!< RTC RAWSTAT: RPHO (Bit 2) */ -#define RTC_RAWSTAT_RPHO_Msk \ - (0x4UL) /*!< RTC RAWSTAT: RPHO (Bitfield-Mask: 0x01) */ -#define RTC_RAWSTAT_RPDA_Pos \ - (3UL) /*!< RTC RAWSTAT: RPDA (Bit 3) */ -#define RTC_RAWSTAT_RPDA_Msk \ - (0x8UL) /*!< RTC RAWSTAT: RPDA (Bitfield-Mask: 0x01) */ -#define RTC_RAWSTAT_RPMO_Pos \ - (5UL) /*!< RTC RAWSTAT: RPMO (Bit 5) */ -#define RTC_RAWSTAT_RPMO_Msk \ - (0x20UL) /*!< RTC RAWSTAT: RPMO (Bitfield-Mask: 0x01) */ -#define RTC_RAWSTAT_RPYE_Pos \ - (6UL) /*!< RTC RAWSTAT: RPYE (Bit 6) */ -#define RTC_RAWSTAT_RPYE_Msk \ - (0x40UL) /*!< RTC RAWSTAT: RPYE (Bitfield-Mask: 0x01) */ -#define RTC_RAWSTAT_RAI_Pos \ - (8UL) /*!< RTC RAWSTAT: RAI (Bit 8) */ -#define RTC_RAWSTAT_RAI_Msk \ - (0x100UL) /*!< RTC RAWSTAT: RAI (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- RTC_STSSR --------------------------------- */ -#define RTC_STSSR_SPSE_Pos (0UL) /*!< RTC STSSR: SPSE (Bit 0) */ -#define RTC_STSSR_SPSE_Msk \ - (0x1UL) /*!< RTC STSSR: SPSE (Bitfield-Mask: 0x01) */ -#define RTC_STSSR_SPMI_Pos (1UL) /*!< RTC STSSR: SPMI (Bit 1) */ -#define RTC_STSSR_SPMI_Msk \ - (0x2UL) /*!< RTC STSSR: SPMI (Bitfield-Mask: 0x01) */ -#define RTC_STSSR_SPHO_Pos (2UL) /*!< RTC STSSR: SPHO (Bit 2) */ -#define RTC_STSSR_SPHO_Msk \ - (0x4UL) /*!< RTC STSSR: SPHO (Bitfield-Mask: 0x01) */ -#define RTC_STSSR_SPDA_Pos (3UL) /*!< RTC STSSR: SPDA (Bit 3) */ -#define RTC_STSSR_SPDA_Msk \ - (0x8UL) /*!< RTC STSSR: SPDA (Bitfield-Mask: 0x01) */ -#define RTC_STSSR_SPMO_Pos (5UL) /*!< RTC STSSR: SPMO (Bit 5) */ -#define RTC_STSSR_SPMO_Msk \ - (0x20UL) /*!< RTC STSSR: SPMO (Bitfield-Mask: 0x01) */ -#define RTC_STSSR_SPYE_Pos (6UL) /*!< RTC STSSR: SPYE (Bit 6) */ -#define RTC_STSSR_SPYE_Msk \ - (0x40UL) /*!< RTC STSSR: SPYE (Bitfield-Mask: 0x01) */ -#define RTC_STSSR_SAI_Pos (8UL) /*!< RTC STSSR: SAI (Bit 8) */ -#define RTC_STSSR_SAI_Msk \ - (0x100UL) /*!< RTC STSSR: SAI (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- RTC_MSKSR --------------------------------- */ -#define RTC_MSKSR_MPSE_Pos (0UL) /*!< RTC MSKSR: MPSE (Bit 0) */ -#define RTC_MSKSR_MPSE_Msk \ - (0x1UL) /*!< RTC MSKSR: MPSE (Bitfield-Mask: 0x01) */ -#define RTC_MSKSR_MPMI_Pos (1UL) /*!< RTC MSKSR: MPMI (Bit 1) */ -#define RTC_MSKSR_MPMI_Msk \ - (0x2UL) /*!< RTC MSKSR: MPMI (Bitfield-Mask: 0x01) */ -#define RTC_MSKSR_MPHO_Pos (2UL) /*!< RTC MSKSR: MPHO (Bit 2) */ -#define RTC_MSKSR_MPHO_Msk \ - (0x4UL) /*!< RTC MSKSR: MPHO (Bitfield-Mask: 0x01) */ -#define RTC_MSKSR_MPDA_Pos (3UL) /*!< RTC MSKSR: MPDA (Bit 3) */ -#define RTC_MSKSR_MPDA_Msk \ - (0x8UL) /*!< RTC MSKSR: MPDA (Bitfield-Mask: 0x01) */ -#define RTC_MSKSR_MPMO_Pos (5UL) /*!< RTC MSKSR: MPMO (Bit 5) */ -#define RTC_MSKSR_MPMO_Msk \ - (0x20UL) /*!< RTC MSKSR: MPMO (Bitfield-Mask: 0x01) */ -#define RTC_MSKSR_MPYE_Pos (6UL) /*!< RTC MSKSR: MPYE (Bit 6) */ -#define RTC_MSKSR_MPYE_Msk \ - (0x40UL) /*!< RTC MSKSR: MPYE (Bitfield-Mask: 0x01) */ -#define RTC_MSKSR_MAI_Pos (8UL) /*!< RTC MSKSR: MAI (Bit 8) */ -#define RTC_MSKSR_MAI_Msk \ - (0x100UL) /*!< RTC MSKSR: MAI (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- RTC_CLRSR --------------------------------- */ -#define RTC_CLRSR_RPSE_Pos (0UL) /*!< RTC CLRSR: RPSE (Bit 0) */ -#define RTC_CLRSR_RPSE_Msk \ - (0x1UL) /*!< RTC CLRSR: RPSE (Bitfield-Mask: 0x01) */ -#define RTC_CLRSR_RPMI_Pos (1UL) /*!< RTC CLRSR: RPMI (Bit 1) */ -#define RTC_CLRSR_RPMI_Msk \ - (0x2UL) /*!< RTC CLRSR: RPMI (Bitfield-Mask: 0x01) */ -#define RTC_CLRSR_RPHO_Pos (2UL) /*!< RTC CLRSR: RPHO (Bit 2) */ -#define RTC_CLRSR_RPHO_Msk \ - (0x4UL) /*!< RTC CLRSR: RPHO (Bitfield-Mask: 0x01) */ -#define RTC_CLRSR_RPDA_Pos (3UL) /*!< RTC CLRSR: RPDA (Bit 3) */ -#define RTC_CLRSR_RPDA_Msk \ - (0x8UL) /*!< RTC CLRSR: RPDA (Bitfield-Mask: 0x01) */ -#define RTC_CLRSR_RPMO_Pos (5UL) /*!< RTC CLRSR: RPMO (Bit 5) */ -#define RTC_CLRSR_RPMO_Msk \ - (0x20UL) /*!< RTC CLRSR: RPMO (Bitfield-Mask: 0x01) */ -#define RTC_CLRSR_RPYE_Pos (6UL) /*!< RTC CLRSR: RPYE (Bit 6) */ -#define RTC_CLRSR_RPYE_Msk \ - (0x40UL) /*!< RTC CLRSR: RPYE (Bitfield-Mask: 0x01) */ -#define RTC_CLRSR_RAI_Pos (8UL) /*!< RTC CLRSR: RAI (Bit 8) */ -#define RTC_CLRSR_RAI_Msk \ - (0x100UL) /*!< RTC CLRSR: RAI (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- RTC_ATIM0 --------------------------------- */ -#define RTC_ATIM0_ASE_Pos (0UL) /*!< RTC ATIM0: ASE (Bit 0) */ -#define RTC_ATIM0_ASE_Msk \ - (0x3fUL) /*!< RTC ATIM0: ASE (Bitfield-Mask: 0x3f) */ -#define RTC_ATIM0_AMI_Pos (8UL) /*!< RTC ATIM0: AMI (Bit 8) */ -#define RTC_ATIM0_AMI_Msk \ - (0x3f00UL) /*!< RTC ATIM0: AMI (Bitfield-Mask: 0x3f) */ -#define RTC_ATIM0_AHO_Pos (16UL) /*!< RTC ATIM0: AHO (Bit 16) */ -#define RTC_ATIM0_AHO_Msk \ - (0x1f0000UL) /*!< RTC ATIM0: AHO (Bitfield-Mask: 0x1f) */ -#define RTC_ATIM0_ADA_Pos (24UL) /*!< RTC ATIM0: ADA (Bit 24) */ -#define RTC_ATIM0_ADA_Msk \ - (0x1f000000UL) /*!< RTC ATIM0: ADA (Bitfield-Mask: 0x1f) */ - -/* ---------------------------------- RTC_ATIM1 --------------------------------- */ -#define RTC_ATIM1_AMO_Pos (8UL) /*!< RTC ATIM1: AMO (Bit 8) */ -#define RTC_ATIM1_AMO_Msk \ - (0xf00UL) /*!< RTC ATIM1: AMO (Bitfield-Mask: 0x0f) */ -#define RTC_ATIM1_AYE_Pos (16UL) /*!< RTC ATIM1: AYE (Bit 16) */ -#define RTC_ATIM1_AYE_Msk \ - (0xffff0000UL) /*!< RTC ATIM1: AYE (Bitfield-Mask: 0xffff) */ - -/* ---------------------------------- RTC_TIM0 ---------------------------------- */ -#define RTC_TIM0_SE_Pos (0UL) /*!< RTC TIM0: SE (Bit 0) */ -#define RTC_TIM0_SE_Msk (0x3fUL) /*!< RTC TIM0: SE (Bitfield-Mask: 0x3f) */ -#define RTC_TIM0_MI_Pos (8UL) /*!< RTC TIM0: MI (Bit 8) */ -#define RTC_TIM0_MI_Msk \ - (0x3f00UL) /*!< RTC TIM0: MI (Bitfield-Mask: 0x3f) */ -#define RTC_TIM0_HO_Pos (16UL) /*!< RTC TIM0: HO (Bit 16) */ -#define RTC_TIM0_HO_Msk \ - (0x1f0000UL) /*!< RTC TIM0: HO (Bitfield-Mask: 0x1f) */ -#define RTC_TIM0_DA_Pos (24UL) /*!< RTC TIM0: DA (Bit 24) */ -#define RTC_TIM0_DA_Msk \ - (0x1f000000UL) /*!< RTC TIM0: DA (Bitfield-Mask: 0x1f) */ - -/* ---------------------------------- RTC_TIM1 ---------------------------------- */ -#define RTC_TIM1_DAWE_Pos (0UL) /*!< RTC TIM1: DAWE (Bit 0) */ -#define RTC_TIM1_DAWE_Msk \ - (0x7UL) /*!< RTC TIM1: DAWE (Bitfield-Mask: 0x07) */ -#define RTC_TIM1_MO_Pos (8UL) /*!< RTC TIM1: MO (Bit 8) */ -#define RTC_TIM1_MO_Msk \ - (0xf00UL) /*!< RTC TIM1: MO (Bitfield-Mask: 0x0f) */ -#define RTC_TIM1_YE_Pos (16UL) /*!< RTC TIM1: YE (Bit 16) */ -#define RTC_TIM1_YE_Msk \ - (0xffff0000UL) /*!< RTC TIM1: YE (Bitfield-Mask: 0xffff) */ - -/* ================================================================================ */ -/* ================ struct 'SCU_CLK' Position & Mask ================ */ -/* ================================================================================ */ - -/* ------------------------------- SCU_CLK_CLKSTAT ------------------------------ */ -#define SCU_CLK_CLKSTAT_USBCST_Pos \ - (0UL) /*!< SCU_CLK CLKSTAT: USBCST (Bit 0) */ -#define SCU_CLK_CLKSTAT_USBCST_Msk \ - (0x1UL) /*!< SCU_CLK CLKSTAT: USBCST (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CLKSTAT_CCUCST_Pos \ - (4UL) /*!< SCU_CLK CLKSTAT: CCUCST (Bit 4) */ -#define SCU_CLK_CLKSTAT_CCUCST_Msk \ - (0x10UL) /*!< SCU_CLK CLKSTAT: CCUCST (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CLKSTAT_WDTCST_Pos \ - (5UL) /*!< SCU_CLK CLKSTAT: WDTCST (Bit 5) */ -#define SCU_CLK_CLKSTAT_WDTCST_Msk \ - (0x20UL) /*!< SCU_CLK CLKSTAT: WDTCST (Bitfield-Mask: 0x01) */ - -/* ------------------------------- SCU_CLK_CLKSET ------------------------------- */ -#define SCU_CLK_CLKSET_USBCEN_Pos \ - (0UL) /*!< SCU_CLK CLKSET: USBCEN (Bit 0) */ -#define SCU_CLK_CLKSET_USBCEN_Msk \ - (0x1UL) /*!< SCU_CLK CLKSET: USBCEN (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CLKSET_CCUCEN_Pos \ - (4UL) /*!< SCU_CLK CLKSET: CCUCEN (Bit 4) */ -#define SCU_CLK_CLKSET_CCUCEN_Msk \ - (0x10UL) /*!< SCU_CLK CLKSET: CCUCEN (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CLKSET_WDTCEN_Pos \ - (5UL) /*!< SCU_CLK CLKSET: WDTCEN (Bit 5) */ -#define SCU_CLK_CLKSET_WDTCEN_Msk \ - (0x20UL) /*!< SCU_CLK CLKSET: WDTCEN (Bitfield-Mask: 0x01) */ - -/* ------------------------------- SCU_CLK_CLKCLR ------------------------------- */ -#define SCU_CLK_CLKCLR_USBCDI_Pos \ - (0UL) /*!< SCU_CLK CLKCLR: USBCDI (Bit 0) */ -#define SCU_CLK_CLKCLR_USBCDI_Msk \ - (0x1UL) /*!< SCU_CLK CLKCLR: USBCDI (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CLKCLR_CCUCDI_Pos \ - (4UL) /*!< SCU_CLK CLKCLR: CCUCDI (Bit 4) */ -#define SCU_CLK_CLKCLR_CCUCDI_Msk \ - (0x10UL) /*!< SCU_CLK CLKCLR: CCUCDI (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CLKCLR_WDTCDI_Pos \ - (5UL) /*!< SCU_CLK CLKCLR: WDTCDI (Bit 5) */ -#define SCU_CLK_CLKCLR_WDTCDI_Msk \ - (0x20UL) /*!< SCU_CLK CLKCLR: WDTCDI (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_CLK_SYSCLKCR ------------------------------ */ -#define SCU_CLK_SYSCLKCR_SYSDIV_Pos \ - (0UL) /*!< SCU_CLK SYSCLKCR: SYSDIV (Bit 0) */ -#define SCU_CLK_SYSCLKCR_SYSDIV_Msk \ - (0xffUL) /*!< SCU_CLK SYSCLKCR: SYSDIV (Bitfield-Mask: 0xff) */ -#define SCU_CLK_SYSCLKCR_SYSSEL_Pos \ - (16UL) /*!< SCU_CLK SYSCLKCR: SYSSEL (Bit 16) */ -#define SCU_CLK_SYSCLKCR_SYSSEL_Msk \ - (0x10000UL) /*!< SCU_CLK SYSCLKCR: SYSSEL (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_CLK_CPUCLKCR ------------------------------ */ -#define SCU_CLK_CPUCLKCR_CPUDIV_Pos \ - (0UL) /*!< SCU_CLK CPUCLKCR: CPUDIV (Bit 0) */ -#define SCU_CLK_CPUCLKCR_CPUDIV_Msk \ - (0x1UL) /*!< SCU_CLK CPUCLKCR: CPUDIV (Bitfield-Mask: 0x01) */ - -/* ------------------------------- SCU_CLK_PBCLKCR ------------------------------ */ -#define SCU_CLK_PBCLKCR_PBDIV_Pos \ - (0UL) /*!< SCU_CLK PBCLKCR: PBDIV (Bit 0) */ -#define SCU_CLK_PBCLKCR_PBDIV_Msk \ - (0x1UL) /*!< SCU_CLK PBCLKCR: PBDIV (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_CLK_USBCLKCR ------------------------------ */ -#define SCU_CLK_USBCLKCR_USBDIV_Pos \ - (0UL) /*!< SCU_CLK USBCLKCR: USBDIV (Bit 0) */ -#define SCU_CLK_USBCLKCR_USBDIV_Msk \ - (0x7UL) /*!< SCU_CLK USBCLKCR: USBDIV (Bitfield-Mask: 0x07) */ -#define SCU_CLK_USBCLKCR_USBSEL_Pos \ - (16UL) /*!< SCU_CLK USBCLKCR: USBSEL (Bit 16) */ -#define SCU_CLK_USBCLKCR_USBSEL_Msk \ - (0x10000UL) /*!< SCU_CLK USBCLKCR: USBSEL (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_CLK_CCUCLKCR ------------------------------ */ -#define SCU_CLK_CCUCLKCR_CCUDIV_Pos \ - (0UL) /*!< SCU_CLK CCUCLKCR: CCUDIV (Bit 0) */ -#define SCU_CLK_CCUCLKCR_CCUDIV_Msk \ - (0x1UL) /*!< SCU_CLK CCUCLKCR: CCUDIV (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_CLK_WDTCLKCR ------------------------------ */ -#define SCU_CLK_WDTCLKCR_WDTDIV_Pos \ - (0UL) /*!< SCU_CLK WDTCLKCR: WDTDIV (Bit 0) */ -#define SCU_CLK_WDTCLKCR_WDTDIV_Msk \ - (0xffUL) /*!< SCU_CLK WDTCLKCR: WDTDIV (Bitfield-Mask: 0xff) */ -#define SCU_CLK_WDTCLKCR_WDTSEL_Pos \ - (16UL) /*!< SCU_CLK WDTCLKCR: WDTSEL (Bit 16) */ -#define SCU_CLK_WDTCLKCR_WDTSEL_Msk \ - (0x30000UL) /*!< SCU_CLK WDTCLKCR: WDTSEL (Bitfield-Mask: 0x03) */ - -/* ------------------------------ SCU_CLK_EXTCLKCR ------------------------------ */ -#define SCU_CLK_EXTCLKCR_ECKSEL_Pos \ - (0UL) /*!< SCU_CLK EXTCLKCR: ECKSEL (Bit 0) */ -#define SCU_CLK_EXTCLKCR_ECKSEL_Msk \ - (0x7UL) /*!< SCU_CLK EXTCLKCR: ECKSEL (Bitfield-Mask: 0x07) */ -#define SCU_CLK_EXTCLKCR_ECKDIV_Pos \ - (16UL) /*!< SCU_CLK EXTCLKCR: ECKDIV (Bit 16) */ -#define SCU_CLK_EXTCLKCR_ECKDIV_Msk \ - (0x1ff0000UL) /*!< SCU_CLK EXTCLKCR: ECKDIV (Bitfield-Mask: 0x1ff) */ - -/* ----------------------------- SCU_CLK_MLINKCLKCR ----------------------------- */ -#define SCU_CLK_MLINKCLKCR_SYSDIV_Pos \ - (0UL) /*!< SCU_CLK MLINKCLKCR: SYSDIV (Bit 0) */ -#define SCU_CLK_MLINKCLKCR_SYSDIV_Msk \ - (0xffUL) /*!< SCU_CLK MLINKCLKCR: SYSDIV (Bitfield-Mask: 0xff) */ -#define SCU_CLK_MLINKCLKCR_SYSSEL_Pos \ - (8UL) /*!< SCU_CLK MLINKCLKCR: SYSSEL (Bit 8) */ -#define SCU_CLK_MLINKCLKCR_SYSSEL_Msk \ - (0x100UL) /*!< SCU_CLK MLINKCLKCR: SYSSEL (Bitfield-Mask: 0x01) */ -#define SCU_CLK_MLINKCLKCR_CPUDIV_Pos \ - (10UL) /*!< SCU_CLK MLINKCLKCR: CPUDIV (Bit 10) */ -#define SCU_CLK_MLINKCLKCR_CPUDIV_Msk \ - (0x400UL) /*!< SCU_CLK MLINKCLKCR: CPUDIV (Bitfield-Mask: 0x01) */ -#define SCU_CLK_MLINKCLKCR_PBDIV_Pos \ - (12UL) /*!< SCU_CLK MLINKCLKCR: PBDIV (Bit 12) */ -#define SCU_CLK_MLINKCLKCR_PBDIV_Msk \ - (0x1000UL) /*!< SCU_CLK MLINKCLKCR: PBDIV (Bitfield-Mask: 0x01) */ -#define SCU_CLK_MLINKCLKCR_CCUDIV_Pos \ - (14UL) /*!< SCU_CLK MLINKCLKCR: CCUDIV (Bit 14) */ -#define SCU_CLK_MLINKCLKCR_CCUDIV_Msk \ - (0x4000UL) /*!< SCU_CLK MLINKCLKCR: CCUDIV (Bitfield-Mask: 0x01) */ -#define SCU_CLK_MLINKCLKCR_WDTDIV_Pos \ - (16UL) /*!< SCU_CLK MLINKCLKCR: WDTDIV (Bit 16) */ -#define SCU_CLK_MLINKCLKCR_WDTDIV_Msk \ - (0xff0000UL) /*!< SCU_CLK MLINKCLKCR: WDTDIV (Bitfield-Mask: 0xff) */ -#define SCU_CLK_MLINKCLKCR_WDTSEL_Pos \ - (24UL) /*!< SCU_CLK MLINKCLKCR: WDTSEL (Bit 24) */ -#define SCU_CLK_MLINKCLKCR_WDTSEL_Msk \ - (0x3000000UL) /*!< SCU_CLK MLINKCLKCR: WDTSEL (Bitfield-Mask: 0x03) */ - -/* ------------------------------- SCU_CLK_SLEEPCR ------------------------------ */ -#define SCU_CLK_SLEEPCR_SYSSEL_Pos \ - (0UL) /*!< SCU_CLK SLEEPCR: SYSSEL (Bit 0) */ -#define SCU_CLK_SLEEPCR_SYSSEL_Msk \ - (0x1UL) /*!< SCU_CLK SLEEPCR: SYSSEL (Bitfield-Mask: 0x01) */ -#define SCU_CLK_SLEEPCR_USBCR_Pos \ - (16UL) /*!< SCU_CLK SLEEPCR: USBCR (Bit 16) */ -#define SCU_CLK_SLEEPCR_USBCR_Msk \ - (0x10000UL) /*!< SCU_CLK SLEEPCR: USBCR (Bitfield-Mask: 0x01) */ -#define SCU_CLK_SLEEPCR_CCUCR_Pos \ - (20UL) /*!< SCU_CLK SLEEPCR: CCUCR (Bit 20) */ -#define SCU_CLK_SLEEPCR_CCUCR_Msk \ - (0x100000UL) /*!< SCU_CLK SLEEPCR: CCUCR (Bitfield-Mask: 0x01) */ -#define SCU_CLK_SLEEPCR_WDTCR_Pos \ - (21UL) /*!< SCU_CLK SLEEPCR: WDTCR (Bit 21) */ -#define SCU_CLK_SLEEPCR_WDTCR_Msk \ - (0x200000UL) /*!< SCU_CLK SLEEPCR: WDTCR (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_CLK_DSLEEPCR ------------------------------ */ -#define SCU_CLK_DSLEEPCR_SYSSEL_Pos \ - (0UL) /*!< SCU_CLK DSLEEPCR: SYSSEL (Bit 0) */ -#define SCU_CLK_DSLEEPCR_SYSSEL_Msk \ - (0x1UL) /*!< SCU_CLK DSLEEPCR: SYSSEL (Bitfield-Mask: 0x01) */ -#define SCU_CLK_DSLEEPCR_FPDN_Pos \ - (11UL) /*!< SCU_CLK DSLEEPCR: FPDN (Bit 11) */ -#define SCU_CLK_DSLEEPCR_FPDN_Msk \ - (0x800UL) /*!< SCU_CLK DSLEEPCR: FPDN (Bitfield-Mask: 0x01) */ -#define SCU_CLK_DSLEEPCR_PLLPDN_Pos \ - (12UL) /*!< SCU_CLK DSLEEPCR: PLLPDN (Bit 12) */ -#define SCU_CLK_DSLEEPCR_PLLPDN_Msk \ - (0x1000UL) /*!< SCU_CLK DSLEEPCR: PLLPDN (Bitfield-Mask: 0x01) */ -#define SCU_CLK_DSLEEPCR_VCOPDN_Pos \ - (13UL) /*!< SCU_CLK DSLEEPCR: VCOPDN (Bit 13) */ -#define SCU_CLK_DSLEEPCR_VCOPDN_Msk \ - (0x2000UL) /*!< SCU_CLK DSLEEPCR: VCOPDN (Bitfield-Mask: 0x01) */ -#define SCU_CLK_DSLEEPCR_USBCR_Pos \ - (16UL) /*!< SCU_CLK DSLEEPCR: USBCR (Bit 16) */ -#define SCU_CLK_DSLEEPCR_USBCR_Msk \ - (0x10000UL) /*!< SCU_CLK DSLEEPCR: USBCR (Bitfield-Mask: 0x01) */ -#define SCU_CLK_DSLEEPCR_CCUCR_Pos \ - (20UL) /*!< SCU_CLK DSLEEPCR: CCUCR (Bit 20) */ -#define SCU_CLK_DSLEEPCR_CCUCR_Msk \ - (0x100000UL) /*!< SCU_CLK DSLEEPCR: CCUCR (Bitfield-Mask: 0x01) */ -#define SCU_CLK_DSLEEPCR_WDTCR_Pos \ - (21UL) /*!< SCU_CLK DSLEEPCR: WDTCR (Bit 21) */ -#define SCU_CLK_DSLEEPCR_WDTCR_Msk \ - (0x200000UL) /*!< SCU_CLK DSLEEPCR: WDTCR (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_CLK_CGATSTAT0 ----------------------------- */ -#define SCU_CLK_CGATSTAT0_VADC_Pos \ - (0UL) /*!< SCU_CLK CGATSTAT0: VADC (Bit 0) */ -#define SCU_CLK_CGATSTAT0_VADC_Msk \ - (0x1UL) /*!< SCU_CLK CGATSTAT0: VADC (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSTAT0_CCU40_Pos \ - (2UL) /*!< SCU_CLK CGATSTAT0: CCU40 (Bit 2) */ -#define SCU_CLK_CGATSTAT0_CCU40_Msk \ - (0x4UL) /*!< SCU_CLK CGATSTAT0: CCU40 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSTAT0_CCU41_Pos \ - (3UL) /*!< SCU_CLK CGATSTAT0: CCU41 (Bit 3) */ -#define SCU_CLK_CGATSTAT0_CCU41_Msk \ - (0x8UL) /*!< SCU_CLK CGATSTAT0: CCU41 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSTAT0_CCU80_Pos \ - (7UL) /*!< SCU_CLK CGATSTAT0: CCU80 (Bit 7) */ -#define SCU_CLK_CGATSTAT0_CCU80_Msk \ - (0x80UL) /*!< SCU_CLK CGATSTAT0: CCU80 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSTAT0_POSIF0_Pos \ - (9UL) /*!< SCU_CLK CGATSTAT0: POSIF0 (Bit 9) */ -#define SCU_CLK_CGATSTAT0_POSIF0_Msk \ - (0x200UL) /*!< SCU_CLK CGATSTAT0: POSIF0 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSTAT0_USIC0_Pos \ - (11UL) /*!< SCU_CLK CGATSTAT0: USIC0 (Bit 11) */ -#define SCU_CLK_CGATSTAT0_USIC0_Msk \ - (0x800UL) /*!< SCU_CLK CGATSTAT0: USIC0 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSTAT0_ERU1_Pos \ - (16UL) /*!< SCU_CLK CGATSTAT0: ERU1 (Bit 16) */ -#define SCU_CLK_CGATSTAT0_ERU1_Msk \ - (0x10000UL) /*!< SCU_CLK CGATSTAT0: ERU1 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSTAT0_HRPWM0_Pos \ - (23UL) /*!< SCU_CLK CGATSTAT0: HRPWM0 (Bit 23) */ -#define SCU_CLK_CGATSTAT0_HRPWM0_Msk \ - (0x800000UL) /*!< SCU_CLK CGATSTAT0: HRPWM0 (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_CLK_CGATSET0 ------------------------------ */ -#define SCU_CLK_CGATSET0_VADC_Pos \ - (0UL) /*!< SCU_CLK CGATSET0: VADC (Bit 0) */ -#define SCU_CLK_CGATSET0_VADC_Msk \ - (0x1UL) /*!< SCU_CLK CGATSET0: VADC (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSET0_CCU40_Pos \ - (2UL) /*!< SCU_CLK CGATSET0: CCU40 (Bit 2) */ -#define SCU_CLK_CGATSET0_CCU40_Msk \ - (0x4UL) /*!< SCU_CLK CGATSET0: CCU40 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSET0_CCU41_Pos \ - (3UL) /*!< SCU_CLK CGATSET0: CCU41 (Bit 3) */ -#define SCU_CLK_CGATSET0_CCU41_Msk \ - (0x8UL) /*!< SCU_CLK CGATSET0: CCU41 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSET0_CCU80_Pos \ - (7UL) /*!< SCU_CLK CGATSET0: CCU80 (Bit 7) */ -#define SCU_CLK_CGATSET0_CCU80_Msk \ - (0x80UL) /*!< SCU_CLK CGATSET0: CCU80 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSET0_POSIF0_Pos \ - (9UL) /*!< SCU_CLK CGATSET0: POSIF0 (Bit 9) */ -#define SCU_CLK_CGATSET0_POSIF0_Msk \ - (0x200UL) /*!< SCU_CLK CGATSET0: POSIF0 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSET0_USIC0_Pos \ - (11UL) /*!< SCU_CLK CGATSET0: USIC0 (Bit 11) */ -#define SCU_CLK_CGATSET0_USIC0_Msk \ - (0x800UL) /*!< SCU_CLK CGATSET0: USIC0 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSET0_ERU1_Pos \ - (16UL) /*!< SCU_CLK CGATSET0: ERU1 (Bit 16) */ -#define SCU_CLK_CGATSET0_ERU1_Msk \ - (0x10000UL) /*!< SCU_CLK CGATSET0: ERU1 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSET0_HRPWM0_Pos \ - (23UL) /*!< SCU_CLK CGATSET0: HRPWM0 (Bit 23) */ -#define SCU_CLK_CGATSET0_HRPWM0_Msk \ - (0x800000UL) /*!< SCU_CLK CGATSET0: HRPWM0 (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_CLK_CGATCLR0 ------------------------------ */ -#define SCU_CLK_CGATCLR0_VADC_Pos \ - (0UL) /*!< SCU_CLK CGATCLR0: VADC (Bit 0) */ -#define SCU_CLK_CGATCLR0_VADC_Msk \ - (0x1UL) /*!< SCU_CLK CGATCLR0: VADC (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATCLR0_CCU40_Pos \ - (2UL) /*!< SCU_CLK CGATCLR0: CCU40 (Bit 2) */ -#define SCU_CLK_CGATCLR0_CCU40_Msk \ - (0x4UL) /*!< SCU_CLK CGATCLR0: CCU40 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATCLR0_CCU41_Pos \ - (3UL) /*!< SCU_CLK CGATCLR0: CCU41 (Bit 3) */ -#define SCU_CLK_CGATCLR0_CCU41_Msk \ - (0x8UL) /*!< SCU_CLK CGATCLR0: CCU41 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATCLR0_CCU80_Pos \ - (7UL) /*!< SCU_CLK CGATCLR0: CCU80 (Bit 7) */ -#define SCU_CLK_CGATCLR0_CCU80_Msk \ - (0x80UL) /*!< SCU_CLK CGATCLR0: CCU80 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATCLR0_POSIF0_Pos \ - (9UL) /*!< SCU_CLK CGATCLR0: POSIF0 (Bit 9) */ -#define SCU_CLK_CGATCLR0_POSIF0_Msk \ - (0x200UL) /*!< SCU_CLK CGATCLR0: POSIF0 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATCLR0_USIC0_Pos \ - (11UL) /*!< SCU_CLK CGATCLR0: USIC0 (Bit 11) */ -#define SCU_CLK_CGATCLR0_USIC0_Msk \ - (0x800UL) /*!< SCU_CLK CGATCLR0: USIC0 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATCLR0_ERU1_Pos \ - (16UL) /*!< SCU_CLK CGATCLR0: ERU1 (Bit 16) */ -#define SCU_CLK_CGATCLR0_ERU1_Msk \ - (0x10000UL) /*!< SCU_CLK CGATCLR0: ERU1 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATCLR0_HRPWM0_Pos \ - (23UL) /*!< SCU_CLK CGATCLR0: HRPWM0 (Bit 23) */ -#define SCU_CLK_CGATCLR0_HRPWM0_Msk \ - (0x800000UL) /*!< SCU_CLK CGATCLR0: HRPWM0 (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_CLK_CGATSTAT1 ----------------------------- */ -#define SCU_CLK_CGATSTAT1_LEDTSCU0_Pos \ - (3UL) /*!< SCU_CLK CGATSTAT1: LEDTSCU0 (Bit 3) */ -#define SCU_CLK_CGATSTAT1_LEDTSCU0_Msk \ - (0x8UL) /*!< SCU_CLK CGATSTAT1: LEDTSCU0 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSTAT1_MCAN0_Pos \ - (4UL) /*!< SCU_CLK CGATSTAT1: MCAN0 (Bit 4) */ -#define SCU_CLK_CGATSTAT1_MCAN0_Msk \ - (0x10UL) /*!< SCU_CLK CGATSTAT1: MCAN0 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSTAT1_DAC_Pos \ - (5UL) /*!< SCU_CLK CGATSTAT1: DAC (Bit 5) */ -#define SCU_CLK_CGATSTAT1_DAC_Msk \ - (0x20UL) /*!< SCU_CLK CGATSTAT1: DAC (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSTAT1_USIC1_Pos \ - (7UL) /*!< SCU_CLK CGATSTAT1: USIC1 (Bit 7) */ -#define SCU_CLK_CGATSTAT1_USIC1_Msk \ - (0x80UL) /*!< SCU_CLK CGATSTAT1: USIC1 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSTAT1_PPORTS_Pos \ - (9UL) /*!< SCU_CLK CGATSTAT1: PPORTS (Bit 9) */ -#define SCU_CLK_CGATSTAT1_PPORTS_Msk \ - (0x200UL) /*!< SCU_CLK CGATSTAT1: PPORTS (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_CLK_CGATSET1 ------------------------------ */ -#define SCU_CLK_CGATSET1_LEDTSCU0_Pos \ - (3UL) /*!< SCU_CLK CGATSET1: LEDTSCU0 (Bit 3) */ -#define SCU_CLK_CGATSET1_LEDTSCU0_Msk \ - (0x8UL) /*!< SCU_CLK CGATSET1: LEDTSCU0 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSET1_MCAN0_Pos \ - (4UL) /*!< SCU_CLK CGATSET1: MCAN0 (Bit 4) */ -#define SCU_CLK_CGATSET1_MCAN0_Msk \ - (0x10UL) /*!< SCU_CLK CGATSET1: MCAN0 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSET1_DAC_Pos \ - (5UL) /*!< SCU_CLK CGATSET1: DAC (Bit 5) */ -#define SCU_CLK_CGATSET1_DAC_Msk \ - (0x20UL) /*!< SCU_CLK CGATSET1: DAC (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSET1_USIC1_Pos \ - (7UL) /*!< SCU_CLK CGATSET1: USIC1 (Bit 7) */ -#define SCU_CLK_CGATSET1_USIC1_Msk \ - (0x80UL) /*!< SCU_CLK CGATSET1: USIC1 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSET1_PPORTS_Pos \ - (9UL) /*!< SCU_CLK CGATSET1: PPORTS (Bit 9) */ -#define SCU_CLK_CGATSET1_PPORTS_Msk \ - (0x200UL) /*!< SCU_CLK CGATSET1: PPORTS (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_CLK_CGATCLR1 ------------------------------ */ -#define SCU_CLK_CGATCLR1_LEDTSCU0_Pos \ - (3UL) /*!< SCU_CLK CGATCLR1: LEDTSCU0 (Bit 3) */ -#define SCU_CLK_CGATCLR1_LEDTSCU0_Msk \ - (0x8UL) /*!< SCU_CLK CGATCLR1: LEDTSCU0 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATCLR1_MCAN0_Pos \ - (4UL) /*!< SCU_CLK CGATCLR1: MCAN0 (Bit 4) */ -#define SCU_CLK_CGATCLR1_MCAN0_Msk \ - (0x10UL) /*!< SCU_CLK CGATCLR1: MCAN0 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATCLR1_DAC_Pos \ - (5UL) /*!< SCU_CLK CGATCLR1: DAC (Bit 5) */ -#define SCU_CLK_CGATCLR1_DAC_Msk \ - (0x20UL) /*!< SCU_CLK CGATCLR1: DAC (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATCLR1_USIC1_Pos \ - (7UL) /*!< SCU_CLK CGATCLR1: USIC1 (Bit 7) */ -#define SCU_CLK_CGATCLR1_USIC1_Msk \ - (0x80UL) /*!< SCU_CLK CGATCLR1: USIC1 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATCLR1_PPORTS_Pos \ - (9UL) /*!< SCU_CLK CGATCLR1: PPORTS (Bit 9) */ -#define SCU_CLK_CGATCLR1_PPORTS_Msk \ - (0x200UL) /*!< SCU_CLK CGATCLR1: PPORTS (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_CLK_CGATSTAT2 ----------------------------- */ -#define SCU_CLK_CGATSTAT2_WDT_Pos \ - (1UL) /*!< SCU_CLK CGATSTAT2: WDT (Bit 1) */ -#define SCU_CLK_CGATSTAT2_WDT_Msk \ - (0x2UL) /*!< SCU_CLK CGATSTAT2: WDT (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSTAT2_DMA0_Pos \ - (4UL) /*!< SCU_CLK CGATSTAT2: DMA0 (Bit 4) */ -#define SCU_CLK_CGATSTAT2_DMA0_Msk \ - (0x10UL) /*!< SCU_CLK CGATSTAT2: DMA0 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSTAT2_FCE_Pos \ - (6UL) /*!< SCU_CLK CGATSTAT2: FCE (Bit 6) */ -#define SCU_CLK_CGATSTAT2_FCE_Msk \ - (0x40UL) /*!< SCU_CLK CGATSTAT2: FCE (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSTAT2_USB_Pos \ - (7UL) /*!< SCU_CLK CGATSTAT2: USB (Bit 7) */ -#define SCU_CLK_CGATSTAT2_USB_Msk \ - (0x80UL) /*!< SCU_CLK CGATSTAT2: USB (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_CLK_CGATSET2 ------------------------------ */ -#define SCU_CLK_CGATSET2_WDT_Pos \ - (1UL) /*!< SCU_CLK CGATSET2: WDT (Bit 1) */ -#define SCU_CLK_CGATSET2_WDT_Msk \ - (0x2UL) /*!< SCU_CLK CGATSET2: WDT (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSET2_DMA0_Pos \ - (4UL) /*!< SCU_CLK CGATSET2: DMA0 (Bit 4) */ -#define SCU_CLK_CGATSET2_DMA0_Msk \ - (0x10UL) /*!< SCU_CLK CGATSET2: DMA0 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSET2_FCE_Pos \ - (6UL) /*!< SCU_CLK CGATSET2: FCE (Bit 6) */ -#define SCU_CLK_CGATSET2_FCE_Msk \ - (0x40UL) /*!< SCU_CLK CGATSET2: FCE (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSET2_USB_Pos \ - (7UL) /*!< SCU_CLK CGATSET2: USB (Bit 7) */ -#define SCU_CLK_CGATSET2_USB_Msk \ - (0x80UL) /*!< SCU_CLK CGATSET2: USB (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_CLK_CGATCLR2 ------------------------------ */ -#define SCU_CLK_CGATCLR2_WDT_Pos \ - (1UL) /*!< SCU_CLK CGATCLR2: WDT (Bit 1) */ -#define SCU_CLK_CGATCLR2_WDT_Msk \ - (0x2UL) /*!< SCU_CLK CGATCLR2: WDT (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATCLR2_DMA0_Pos \ - (4UL) /*!< SCU_CLK CGATCLR2: DMA0 (Bit 4) */ -#define SCU_CLK_CGATCLR2_DMA0_Msk \ - (0x10UL) /*!< SCU_CLK CGATCLR2: DMA0 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATCLR2_FCE_Pos \ - (6UL) /*!< SCU_CLK CGATCLR2: FCE (Bit 6) */ -#define SCU_CLK_CGATCLR2_FCE_Msk \ - (0x40UL) /*!< SCU_CLK CGATCLR2: FCE (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATCLR2_USB_Pos \ - (7UL) /*!< SCU_CLK CGATCLR2: USB (Bit 7) */ -#define SCU_CLK_CGATCLR2_USB_Msk \ - (0x80UL) /*!< SCU_CLK CGATCLR2: USB (Bitfield-Mask: 0x01) */ - -/* ================================================================================ */ -/* ================ struct 'SCU_OSC' Position & Mask ================ */ -/* ================================================================================ */ - -/* ------------------------------ SCU_OSC_OSCHPSTAT ----------------------------- */ -#define SCU_OSC_OSCHPSTAT_X1D_Pos \ - (0UL) /*!< SCU_OSC OSCHPSTAT: X1D (Bit 0) */ -#define SCU_OSC_OSCHPSTAT_X1D_Msk \ - (0x1UL) /*!< SCU_OSC OSCHPSTAT: X1D (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_OSC_OSCHPCTRL ----------------------------- */ -#define SCU_OSC_OSCHPCTRL_X1DEN_Pos \ - (0UL) /*!< SCU_OSC OSCHPCTRL: X1DEN (Bit 0) */ -#define SCU_OSC_OSCHPCTRL_X1DEN_Msk \ - (0x1UL) /*!< SCU_OSC OSCHPCTRL: X1DEN (Bitfield-Mask: 0x01) */ -#define SCU_OSC_OSCHPCTRL_SHBY_Pos \ - (1UL) /*!< SCU_OSC OSCHPCTRL: SHBY (Bit 1) */ -#define SCU_OSC_OSCHPCTRL_SHBY_Msk \ - (0x2UL) /*!< SCU_OSC OSCHPCTRL: SHBY (Bitfield-Mask: 0x01) */ -#define SCU_OSC_OSCHPCTRL_MODE_Pos \ - (4UL) /*!< SCU_OSC OSCHPCTRL: MODE (Bit 4) */ -#define SCU_OSC_OSCHPCTRL_MODE_Msk \ - (0x30UL) /*!< SCU_OSC OSCHPCTRL: MODE (Bitfield-Mask: 0x03) */ -#define SCU_OSC_OSCHPCTRL_OSCVAL_Pos \ - (16UL) /*!< SCU_OSC OSCHPCTRL: OSCVAL (Bit 16) */ -#define SCU_OSC_OSCHPCTRL_OSCVAL_Msk \ - (0xf0000UL) /*!< SCU_OSC OSCHPCTRL: OSCVAL (Bitfield-Mask: 0x0f) */ - -/* ----------------------------- SCU_OSC_CLKCALCONST ---------------------------- */ -#define SCU_OSC_CLKCALCONST_CALIBCONST_Pos \ - (0UL) /*!< SCU_OSC CLKCALCONST: CALIBCONST (Bit 0) */ -#define SCU_OSC_CLKCALCONST_CALIBCONST_Msk \ - (0xfUL) /*!< SCU_OSC CLKCALCONST: CALIBCONST (Bitfield-Mask: 0x0f) */ - -/* ================================================================================ */ -/* ================ struct 'SCU_PLL' Position & Mask ================ */ -/* ================================================================================ */ - -/* ------------------------------- SCU_PLL_PLLSTAT ------------------------------ */ -#define SCU_PLL_PLLSTAT_VCOBYST_Pos \ - (0UL) /*!< SCU_PLL PLLSTAT: VCOBYST (Bit 0) */ -#define SCU_PLL_PLLSTAT_VCOBYST_Msk \ - (0x1UL) /*!< SCU_PLL PLLSTAT: VCOBYST (Bitfield-Mask: 0x01) */ -#define SCU_PLL_PLLSTAT_PWDSTAT_Pos \ - (1UL) /*!< SCU_PLL PLLSTAT: PWDSTAT (Bit 1) */ -#define SCU_PLL_PLLSTAT_PWDSTAT_Msk \ - (0x2UL) /*!< SCU_PLL PLLSTAT: PWDSTAT (Bitfield-Mask: 0x01) */ -#define SCU_PLL_PLLSTAT_VCOLOCK_Pos \ - (2UL) /*!< SCU_PLL PLLSTAT: VCOLOCK (Bit 2) */ -#define SCU_PLL_PLLSTAT_VCOLOCK_Msk \ - (0x4UL) /*!< SCU_PLL PLLSTAT: VCOLOCK (Bitfield-Mask: 0x01) */ -#define SCU_PLL_PLLSTAT_K1RDY_Pos \ - (4UL) /*!< SCU_PLL PLLSTAT: K1RDY (Bit 4) */ -#define SCU_PLL_PLLSTAT_K1RDY_Msk \ - (0x10UL) /*!< SCU_PLL PLLSTAT: K1RDY (Bitfield-Mask: 0x01) */ -#define SCU_PLL_PLLSTAT_K2RDY_Pos \ - (5UL) /*!< SCU_PLL PLLSTAT: K2RDY (Bit 5) */ -#define SCU_PLL_PLLSTAT_K2RDY_Msk \ - (0x20UL) /*!< SCU_PLL PLLSTAT: K2RDY (Bitfield-Mask: 0x01) */ -#define SCU_PLL_PLLSTAT_BY_Pos \ - (6UL) /*!< SCU_PLL PLLSTAT: BY (Bit 6) */ -#define SCU_PLL_PLLSTAT_BY_Msk \ - (0x40UL) /*!< SCU_PLL PLLSTAT: BY (Bitfield-Mask: 0x01) */ -#define SCU_PLL_PLLSTAT_PLLLV_Pos \ - (7UL) /*!< SCU_PLL PLLSTAT: PLLLV (Bit 7) */ -#define SCU_PLL_PLLSTAT_PLLLV_Msk \ - (0x80UL) /*!< SCU_PLL PLLSTAT: PLLLV (Bitfield-Mask: 0x01) */ -#define SCU_PLL_PLLSTAT_PLLHV_Pos \ - (8UL) /*!< SCU_PLL PLLSTAT: PLLHV (Bit 8) */ -#define SCU_PLL_PLLSTAT_PLLHV_Msk \ - (0x100UL) /*!< SCU_PLL PLLSTAT: PLLHV (Bitfield-Mask: 0x01) */ -#define SCU_PLL_PLLSTAT_PLLSP_Pos \ - (9UL) /*!< SCU_PLL PLLSTAT: PLLSP (Bit 9) */ -#define SCU_PLL_PLLSTAT_PLLSP_Msk \ - (0x200UL) /*!< SCU_PLL PLLSTAT: PLLSP (Bitfield-Mask: 0x01) */ - -/* ------------------------------- SCU_PLL_PLLCON0 ------------------------------ */ -#define SCU_PLL_PLLCON0_VCOBYP_Pos \ - (0UL) /*!< SCU_PLL PLLCON0: VCOBYP (Bit 0) */ -#define SCU_PLL_PLLCON0_VCOBYP_Msk \ - (0x1UL) /*!< SCU_PLL PLLCON0: VCOBYP (Bitfield-Mask: 0x01) */ -#define SCU_PLL_PLLCON0_VCOPWD_Pos \ - (1UL) /*!< SCU_PLL PLLCON0: VCOPWD (Bit 1) */ -#define SCU_PLL_PLLCON0_VCOPWD_Msk \ - (0x2UL) /*!< SCU_PLL PLLCON0: VCOPWD (Bitfield-Mask: 0x01) */ -#define SCU_PLL_PLLCON0_VCOTR_Pos \ - (2UL) /*!< SCU_PLL PLLCON0: VCOTR (Bit 2) */ -#define SCU_PLL_PLLCON0_VCOTR_Msk \ - (0x4UL) /*!< SCU_PLL PLLCON0: VCOTR (Bitfield-Mask: 0x01) */ -#define SCU_PLL_PLLCON0_FINDIS_Pos \ - (4UL) /*!< SCU_PLL PLLCON0: FINDIS (Bit 4) */ -#define SCU_PLL_PLLCON0_FINDIS_Msk \ - (0x10UL) /*!< SCU_PLL PLLCON0: FINDIS (Bitfield-Mask: 0x01) */ -#define SCU_PLL_PLLCON0_OSCDISCDIS_Pos \ - (6UL) /*!< SCU_PLL PLLCON0: OSCDISCDIS (Bit 6) */ -#define SCU_PLL_PLLCON0_OSCDISCDIS_Msk \ - (0x40UL) /*!< SCU_PLL PLLCON0: OSCDISCDIS (Bitfield-Mask: 0x01) */ -#define SCU_PLL_PLLCON0_PLLPWD_Pos \ - (16UL) /*!< SCU_PLL PLLCON0: PLLPWD (Bit 16) */ -#define SCU_PLL_PLLCON0_PLLPWD_Msk \ - (0x10000UL) /*!< SCU_PLL PLLCON0: PLLPWD (Bitfield-Mask: 0x01) */ -#define SCU_PLL_PLLCON0_OSCRES_Pos \ - (17UL) /*!< SCU_PLL PLLCON0: OSCRES (Bit 17) */ -#define SCU_PLL_PLLCON0_OSCRES_Msk \ - (0x20000UL) /*!< SCU_PLL PLLCON0: OSCRES (Bitfield-Mask: 0x01) */ -#define SCU_PLL_PLLCON0_RESLD_Pos \ - (18UL) /*!< SCU_PLL PLLCON0: RESLD (Bit 18) */ -#define SCU_PLL_PLLCON0_RESLD_Msk \ - (0x40000UL) /*!< SCU_PLL PLLCON0: RESLD (Bitfield-Mask: 0x01) */ -#define SCU_PLL_PLLCON0_AOTREN_Pos \ - (19UL) /*!< SCU_PLL PLLCON0: AOTREN (Bit 19) */ -#define SCU_PLL_PLLCON0_AOTREN_Msk \ - (0x80000UL) /*!< SCU_PLL PLLCON0: AOTREN (Bitfield-Mask: 0x01) */ -#define SCU_PLL_PLLCON0_FOTR_Pos \ - (20UL) /*!< SCU_PLL PLLCON0: FOTR (Bit 20) */ -#define SCU_PLL_PLLCON0_FOTR_Msk \ - (0x100000UL) /*!< SCU_PLL PLLCON0: FOTR (Bitfield-Mask: 0x01) */ - -/* ------------------------------- SCU_PLL_PLLCON1 ------------------------------ */ -#define SCU_PLL_PLLCON1_K1DIV_Pos \ - (0UL) /*!< SCU_PLL PLLCON1: K1DIV (Bit 0) */ -#define SCU_PLL_PLLCON1_K1DIV_Msk \ - (0x7fUL) /*!< SCU_PLL PLLCON1: K1DIV (Bitfield-Mask: 0x7f) */ -#define SCU_PLL_PLLCON1_NDIV_Pos \ - (8UL) /*!< SCU_PLL PLLCON1: NDIV (Bit 8) */ -#define SCU_PLL_PLLCON1_NDIV_Msk \ - (0x7f00UL) /*!< SCU_PLL PLLCON1: NDIV (Bitfield-Mask: 0x7f) */ -#define SCU_PLL_PLLCON1_K2DIV_Pos \ - (16UL) /*!< SCU_PLL PLLCON1: K2DIV (Bit 16) */ -#define SCU_PLL_PLLCON1_K2DIV_Msk \ - (0x7f0000UL) /*!< SCU_PLL PLLCON1: K2DIV (Bitfield-Mask: 0x7f) */ -#define SCU_PLL_PLLCON1_PDIV_Pos \ - (24UL) /*!< SCU_PLL PLLCON1: PDIV (Bit 24) */ -#define SCU_PLL_PLLCON1_PDIV_Msk \ - (0xf000000UL) /*!< SCU_PLL PLLCON1: PDIV (Bitfield-Mask: 0x0f) */ - -/* ------------------------------- SCU_PLL_PLLCON2 ------------------------------ */ -#define SCU_PLL_PLLCON2_PINSEL_Pos \ - (0UL) /*!< SCU_PLL PLLCON2: PINSEL (Bit 0) */ -#define SCU_PLL_PLLCON2_PINSEL_Msk \ - (0x1UL) /*!< SCU_PLL PLLCON2: PINSEL (Bitfield-Mask: 0x01) */ -#define SCU_PLL_PLLCON2_K1INSEL_Pos \ - (8UL) /*!< SCU_PLL PLLCON2: K1INSEL (Bit 8) */ -#define SCU_PLL_PLLCON2_K1INSEL_Msk \ - (0x100UL) /*!< SCU_PLL PLLCON2: K1INSEL (Bitfield-Mask: 0x01) */ - -/* ----------------------------- SCU_PLL_USBPLLSTAT ----------------------------- */ -#define SCU_PLL_USBPLLSTAT_VCOBYST_Pos \ - (0UL) /*!< SCU_PLL USBPLLSTAT: VCOBYST (Bit 0) */ -#define SCU_PLL_USBPLLSTAT_VCOBYST_Msk \ - (0x1UL) /*!< SCU_PLL USBPLLSTAT: VCOBYST (Bitfield-Mask: 0x01) */ -#define SCU_PLL_USBPLLSTAT_PWDSTAT_Pos \ - (1UL) /*!< SCU_PLL USBPLLSTAT: PWDSTAT (Bit 1) */ -#define SCU_PLL_USBPLLSTAT_PWDSTAT_Msk \ - (0x2UL) /*!< SCU_PLL USBPLLSTAT: PWDSTAT (Bitfield-Mask: 0x01) */ -#define SCU_PLL_USBPLLSTAT_VCOLOCK_Pos \ - (2UL) /*!< SCU_PLL USBPLLSTAT: VCOLOCK (Bit 2) */ -#define SCU_PLL_USBPLLSTAT_VCOLOCK_Msk \ - (0x4UL) /*!< SCU_PLL USBPLLSTAT: VCOLOCK (Bitfield-Mask: 0x01) */ -#define SCU_PLL_USBPLLSTAT_BY_Pos \ - (6UL) /*!< SCU_PLL USBPLLSTAT: BY (Bit 6) */ -#define SCU_PLL_USBPLLSTAT_BY_Msk \ - (0x40UL) /*!< SCU_PLL USBPLLSTAT: BY (Bitfield-Mask: 0x01) */ -#define SCU_PLL_USBPLLSTAT_VCOLOCKED_Pos \ - (7UL) /*!< SCU_PLL USBPLLSTAT: VCOLOCKED (Bit 7) */ -#define SCU_PLL_USBPLLSTAT_VCOLOCKED_Msk \ - (0x80UL) /*!< SCU_PLL USBPLLSTAT: VCOLOCKED (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_PLL_USBPLLCON ----------------------------- */ -#define SCU_PLL_USBPLLCON_VCOBYP_Pos \ - (0UL) /*!< SCU_PLL USBPLLCON: VCOBYP (Bit 0) */ -#define SCU_PLL_USBPLLCON_VCOBYP_Msk \ - (0x1UL) /*!< SCU_PLL USBPLLCON: VCOBYP (Bitfield-Mask: 0x01) */ -#define SCU_PLL_USBPLLCON_VCOPWD_Pos \ - (1UL) /*!< SCU_PLL USBPLLCON: VCOPWD (Bit 1) */ -#define SCU_PLL_USBPLLCON_VCOPWD_Msk \ - (0x2UL) /*!< SCU_PLL USBPLLCON: VCOPWD (Bitfield-Mask: 0x01) */ -#define SCU_PLL_USBPLLCON_VCOTR_Pos \ - (2UL) /*!< SCU_PLL USBPLLCON: VCOTR (Bit 2) */ -#define SCU_PLL_USBPLLCON_VCOTR_Msk \ - (0x4UL) /*!< SCU_PLL USBPLLCON: VCOTR (Bitfield-Mask: 0x01) */ -#define SCU_PLL_USBPLLCON_FINDIS_Pos \ - (4UL) /*!< SCU_PLL USBPLLCON: FINDIS (Bit 4) */ -#define SCU_PLL_USBPLLCON_FINDIS_Msk \ - (0x10UL) /*!< SCU_PLL USBPLLCON: FINDIS (Bitfield-Mask: 0x01) */ -#define SCU_PLL_USBPLLCON_OSCDISCDIS_Pos \ - (6UL) /*!< SCU_PLL USBPLLCON: OSCDISCDIS (Bit 6) */ -#define SCU_PLL_USBPLLCON_OSCDISCDIS_Msk \ - (0x40UL) /*!< SCU_PLL USBPLLCON: OSCDISCDIS (Bitfield-Mask: 0x01) */ -#define SCU_PLL_USBPLLCON_NDIV_Pos \ - (8UL) /*!< SCU_PLL USBPLLCON: NDIV (Bit 8) */ -#define SCU_PLL_USBPLLCON_NDIV_Msk \ - (0x7f00UL) /*!< SCU_PLL USBPLLCON: NDIV (Bitfield-Mask: 0x7f) */ -#define SCU_PLL_USBPLLCON_PLLPWD_Pos \ - (16UL) /*!< SCU_PLL USBPLLCON: PLLPWD (Bit 16) */ -#define SCU_PLL_USBPLLCON_PLLPWD_Msk \ - (0x10000UL) /*!< SCU_PLL USBPLLCON: PLLPWD (Bitfield-Mask: 0x01) */ -#define SCU_PLL_USBPLLCON_RESLD_Pos \ - (18UL) /*!< SCU_PLL USBPLLCON: RESLD (Bit 18) */ -#define SCU_PLL_USBPLLCON_RESLD_Msk \ - (0x40000UL) /*!< SCU_PLL USBPLLCON: RESLD (Bitfield-Mask: 0x01) */ -#define SCU_PLL_USBPLLCON_PDIV_Pos \ - (24UL) /*!< SCU_PLL USBPLLCON: PDIV (Bit 24) */ -#define SCU_PLL_USBPLLCON_PDIV_Msk \ - (0xf000000UL) /*!< SCU_PLL USBPLLCON: PDIV (Bitfield-Mask: 0x0f) */ - -/* ------------------------------ SCU_PLL_CLKMXSTAT ----------------------------- */ -#define SCU_PLL_CLKMXSTAT_SYSCLKMUX_Pos \ - (0UL) /*!< SCU_PLL CLKMXSTAT: SYSCLKMUX (Bit 0) */ -#define SCU_PLL_CLKMXSTAT_SYSCLKMUX_Msk \ - (0x3UL) /*!< SCU_PLL CLKMXSTAT: SYSCLKMUX (Bitfield-Mask: 0x03) */ - -/* ================================================================================ */ -/* ================ struct 'SCU_GENERAL' Position & Mask ================ */ -/* ================================================================================ */ - -/* ------------------------------- SCU_GENERAL_ID ------------------------------- */ -#define SCU_GENERAL_ID_MOD_REV_Pos \ - (0UL) /*!< SCU_GENERAL ID: MOD_REV (Bit 0) */ -#define SCU_GENERAL_ID_MOD_REV_Msk \ - (0xffUL) /*!< SCU_GENERAL ID: MOD_REV (Bitfield-Mask: 0xff) */ -#define SCU_GENERAL_ID_MOD_TYPE_Pos \ - (8UL) /*!< SCU_GENERAL ID: MOD_TYPE (Bit 8) */ -#define SCU_GENERAL_ID_MOD_TYPE_Msk \ - (0xff00UL) /*!< SCU_GENERAL ID: MOD_TYPE (Bitfield-Mask: 0xff) */ -#define SCU_GENERAL_ID_MOD_NUMBER_Pos \ - (16UL) /*!< SCU_GENERAL ID: MOD_NUMBER (Bit 16) */ -#define SCU_GENERAL_ID_MOD_NUMBER_Msk \ - (0xffff0000UL) /*!< SCU_GENERAL ID: MOD_NUMBER (Bitfield-Mask: 0xffff) */ - -/* ----------------------------- SCU_GENERAL_IDCHIP ----------------------------- */ -#define SCU_GENERAL_IDCHIP_IDCHIP_Pos \ - (0UL) /*!< SCU_GENERAL IDCHIP: IDCHIP (Bit 0) */ -#define SCU_GENERAL_IDCHIP_IDCHIP_Msk \ - (0xffffffffUL) /*!< SCU_GENERAL IDCHIP: IDCHIP (Bitfield-Mask: 0xffffffff) */ - -/* ----------------------------- SCU_GENERAL_IDMANUF ---------------------------- */ -#define SCU_GENERAL_IDMANUF_DEPT_Pos \ - (0UL) /*!< SCU_GENERAL IDMANUF: DEPT (Bit 0) */ -#define SCU_GENERAL_IDMANUF_DEPT_Msk \ - (0x1fUL) /*!< SCU_GENERAL IDMANUF: DEPT (Bitfield-Mask: 0x1f) */ -#define SCU_GENERAL_IDMANUF_MANUF_Pos \ - (5UL) /*!< SCU_GENERAL IDMANUF: MANUF (Bit 5) */ -#define SCU_GENERAL_IDMANUF_MANUF_Msk \ - (0xffe0UL) /*!< SCU_GENERAL IDMANUF: MANUF (Bitfield-Mask: 0x7ff) */ - -/* ------------------------------ SCU_GENERAL_STCON ----------------------------- */ -#define SCU_GENERAL_STCON_HWCON_Pos \ - (0UL) /*!< SCU_GENERAL STCON: HWCON (Bit 0) */ -#define SCU_GENERAL_STCON_HWCON_Msk \ - (0x3UL) /*!< SCU_GENERAL STCON: HWCON (Bitfield-Mask: 0x03) */ -#define SCU_GENERAL_STCON_SWCON_Pos \ - (8UL) /*!< SCU_GENERAL STCON: SWCON (Bit 8) */ -#define SCU_GENERAL_STCON_SWCON_Msk \ - (0xf00UL) /*!< SCU_GENERAL STCON: SWCON (Bitfield-Mask: 0x0f) */ - -/* ------------------------------- SCU_GENERAL_GPR ------------------------------ */ -#define SCU_GENERAL_GPR_DAT_Pos \ - (0UL) /*!< SCU_GENERAL GPR: DAT (Bit 0) */ -#define SCU_GENERAL_GPR_DAT_Msk \ - (0xffffffffUL) /*!< SCU_GENERAL GPR: DAT (Bitfield-Mask: 0xffffffff) */ - -/* ----------------------------- SCU_GENERAL_CCUCON ----------------------------- */ -#define SCU_GENERAL_CCUCON_GSC40_Pos \ - (0UL) /*!< SCU_GENERAL CCUCON: GSC40 (Bit 0) */ -#define SCU_GENERAL_CCUCON_GSC40_Msk \ - (0x1UL) /*!< SCU_GENERAL CCUCON: GSC40 (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_CCUCON_GSC41_Pos \ - (1UL) /*!< SCU_GENERAL CCUCON: GSC41 (Bit 1) */ -#define SCU_GENERAL_CCUCON_GSC41_Msk \ - (0x2UL) /*!< SCU_GENERAL CCUCON: GSC41 (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_CCUCON_GSC80_Pos \ - (8UL) /*!< SCU_GENERAL CCUCON: GSC80 (Bit 8) */ -#define SCU_GENERAL_CCUCON_GSC80_Msk \ - (0x100UL) /*!< SCU_GENERAL CCUCON: GSC80 (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_CCUCON_GSHR0_Pos \ - (24UL) /*!< SCU_GENERAL CCUCON: GSHR0 (Bit 24) */ -#define SCU_GENERAL_CCUCON_GSHR0_Msk \ - (0x1000000UL) /*!< SCU_GENERAL CCUCON: GSHR0 (Bitfield-Mask: 0x01) */ - -/* ----------------------------- SCU_GENERAL_DTSCON ----------------------------- */ -#define SCU_GENERAL_DTSCON_PWD_Pos \ - (0UL) /*!< SCU_GENERAL DTSCON: PWD (Bit 0) */ -#define SCU_GENERAL_DTSCON_PWD_Msk \ - (0x1UL) /*!< SCU_GENERAL DTSCON: PWD (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_DTSCON_START_Pos \ - (1UL) /*!< SCU_GENERAL DTSCON: START (Bit 1) */ -#define SCU_GENERAL_DTSCON_START_Msk \ - (0x2UL) /*!< SCU_GENERAL DTSCON: START (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_DTSCON_OFFSET_Pos \ - (4UL) /*!< SCU_GENERAL DTSCON: OFFSET (Bit 4) */ -#define SCU_GENERAL_DTSCON_OFFSET_Msk \ - (0x7f0UL) /*!< SCU_GENERAL DTSCON: OFFSET (Bitfield-Mask: 0x7f) */ -#define SCU_GENERAL_DTSCON_GAIN_Pos \ - (11UL) /*!< SCU_GENERAL DTSCON: GAIN (Bit 11) */ -#define SCU_GENERAL_DTSCON_GAIN_Msk \ - (0x1f800UL) /*!< SCU_GENERAL DTSCON: GAIN (Bitfield-Mask: 0x3f) */ -#define SCU_GENERAL_DTSCON_REFTRIM_Pos \ - (17UL) /*!< SCU_GENERAL DTSCON: REFTRIM (Bit 17) */ -#define SCU_GENERAL_DTSCON_REFTRIM_Msk \ - (0xe0000UL) /*!< SCU_GENERAL DTSCON: REFTRIM (Bitfield-Mask: 0x07) */ -#define SCU_GENERAL_DTSCON_BGTRIM_Pos \ - (20UL) /*!< SCU_GENERAL DTSCON: BGTRIM (Bit 20) */ -#define SCU_GENERAL_DTSCON_BGTRIM_Msk \ - (0xf00000UL) /*!< SCU_GENERAL DTSCON: BGTRIM (Bitfield-Mask: 0x0f) */ - -/* ----------------------------- SCU_GENERAL_DTSSTAT ---------------------------- */ -#define SCU_GENERAL_DTSSTAT_RESULT_Pos \ - (0UL) /*!< SCU_GENERAL DTSSTAT: RESULT (Bit 0) */ -#define SCU_GENERAL_DTSSTAT_RESULT_Msk \ - (0x3ffUL) /*!< SCU_GENERAL DTSSTAT: RESULT (Bitfield-Mask: 0x3ff) */ -#define SCU_GENERAL_DTSSTAT_RDY_Pos \ - (14UL) /*!< SCU_GENERAL DTSSTAT: RDY (Bit 14) */ -#define SCU_GENERAL_DTSSTAT_RDY_Msk \ - (0x4000UL) /*!< SCU_GENERAL DTSSTAT: RDY (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_DTSSTAT_BUSY_Pos \ - (15UL) /*!< SCU_GENERAL DTSSTAT: BUSY (Bit 15) */ -#define SCU_GENERAL_DTSSTAT_BUSY_Msk \ - (0x8000UL) /*!< SCU_GENERAL DTSSTAT: BUSY (Bitfield-Mask: 0x01) */ - -/* ----------------------------- SCU_GENERAL_GORCEN ----------------------------- */ -#define SCU_GENERAL_GORCEN_ENORC6_Pos \ - (6UL) /*!< SCU_GENERAL GORCEN: ENORC6 (Bit 6) */ -#define SCU_GENERAL_GORCEN_ENORC6_Msk \ - (0x40UL) /*!< SCU_GENERAL GORCEN: ENORC6 (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_GORCEN_ENORC7_Pos \ - (7UL) /*!< SCU_GENERAL GORCEN: ENORC7 (Bit 7) */ -#define SCU_GENERAL_GORCEN_ENORC7_Msk \ - (0x80UL) /*!< SCU_GENERAL GORCEN: ENORC7 (Bitfield-Mask: 0x01) */ - -/* ---------------------------- SCU_GENERAL_DTEMPLIM ---------------------------- */ -#define SCU_GENERAL_DTEMPLIM_LOWER_Pos \ - (0UL) /*!< SCU_GENERAL DTEMPLIM: LOWER (Bit 0) */ -#define SCU_GENERAL_DTEMPLIM_LOWER_Msk \ - (0x3ffUL) /*!< SCU_GENERAL DTEMPLIM: LOWER (Bitfield-Mask: 0x3ff) */ -#define SCU_GENERAL_DTEMPLIM_UPPER_Pos \ - (16UL) /*!< SCU_GENERAL DTEMPLIM: UPPER (Bit 16) */ -#define SCU_GENERAL_DTEMPLIM_UPPER_Msk \ - (0x3ff0000UL) /*!< SCU_GENERAL DTEMPLIM: UPPER (Bitfield-Mask: 0x3ff) */ - -/* --------------------------- SCU_GENERAL_DTEMPALARM --------------------------- */ -#define SCU_GENERAL_DTEMPALARM_UNDERFL_Pos \ - (0UL) /*!< SCU_GENERAL DTEMPALARM: UNDERFL (Bit 0) */ -#define SCU_GENERAL_DTEMPALARM_UNDERFL_Msk \ - (0x1UL) /*!< SCU_GENERAL DTEMPALARM: UNDERFL (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_DTEMPALARM_OVERFL_Pos \ - (16UL) /*!< SCU_GENERAL DTEMPALARM: OVERFL (Bit 16) */ -#define SCU_GENERAL_DTEMPALARM_OVERFL_Msk \ - (0x10000UL) /*!< SCU_GENERAL DTEMPALARM: OVERFL (Bitfield-Mask: 0x01) */ - -/* ----------------------------- SCU_GENERAL_MIRRSTS ---------------------------- */ -#define SCU_GENERAL_MIRRSTS_HDCLR_Pos \ - (1UL) /*!< SCU_GENERAL MIRRSTS: HDCLR (Bit 1) */ -#define SCU_GENERAL_MIRRSTS_HDCLR_Msk \ - (0x2UL) /*!< SCU_GENERAL MIRRSTS: HDCLR (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_MIRRSTS_HDSET_Pos \ - (2UL) /*!< SCU_GENERAL MIRRSTS: HDSET (Bit 2) */ -#define SCU_GENERAL_MIRRSTS_HDSET_Msk \ - (0x4UL) /*!< SCU_GENERAL MIRRSTS: HDSET (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_MIRRSTS_HDCR_Pos \ - (3UL) /*!< SCU_GENERAL MIRRSTS: HDCR (Bit 3) */ -#define SCU_GENERAL_MIRRSTS_HDCR_Msk \ - (0x8UL) /*!< SCU_GENERAL MIRRSTS: HDCR (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_MIRRSTS_OSCSICTRL_Pos \ - (5UL) /*!< SCU_GENERAL MIRRSTS: OSCSICTRL (Bit 5) */ -#define SCU_GENERAL_MIRRSTS_OSCSICTRL_Msk \ - (0x20UL) /*!< SCU_GENERAL MIRRSTS: OSCSICTRL (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_MIRRSTS_OSCULCTRL_Pos \ - (7UL) /*!< SCU_GENERAL MIRRSTS: OSCULCTRL (Bit 7) */ -#define SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk \ - (0x80UL) /*!< SCU_GENERAL MIRRSTS: OSCULCTRL (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_MIRRSTS_RTC_CTR_Pos \ - (8UL) /*!< SCU_GENERAL MIRRSTS: RTC_CTR (Bit 8) */ -#define SCU_GENERAL_MIRRSTS_RTC_CTR_Msk \ - (0x100UL) /*!< SCU_GENERAL MIRRSTS: RTC_CTR (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_MIRRSTS_RTC_ATIM0_Pos \ - (9UL) /*!< SCU_GENERAL MIRRSTS: RTC_ATIM0 (Bit 9) */ -#define SCU_GENERAL_MIRRSTS_RTC_ATIM0_Msk \ - (0x200UL) /*!< SCU_GENERAL MIRRSTS: RTC_ATIM0 (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_MIRRSTS_RTC_ATIM1_Pos \ - (10UL) /*!< SCU_GENERAL MIRRSTS: RTC_ATIM1 (Bit 10) */ -#define SCU_GENERAL_MIRRSTS_RTC_ATIM1_Msk \ - (0x400UL) /*!< SCU_GENERAL MIRRSTS: RTC_ATIM1 (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_MIRRSTS_RTC_TIM0_Pos \ - (11UL) /*!< SCU_GENERAL MIRRSTS: RTC_TIM0 (Bit 11) */ -#define SCU_GENERAL_MIRRSTS_RTC_TIM0_Msk \ - (0x800UL) /*!< SCU_GENERAL MIRRSTS: RTC_TIM0 (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_MIRRSTS_RTC_TIM1_Pos \ - (12UL) /*!< SCU_GENERAL MIRRSTS: RTC_TIM1 (Bit 12) */ -#define SCU_GENERAL_MIRRSTS_RTC_TIM1_Msk \ - (0x1000UL) /*!< SCU_GENERAL MIRRSTS: RTC_TIM1 (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_MIRRSTS_RMX_Pos \ - (13UL) /*!< SCU_GENERAL MIRRSTS: RMX (Bit 13) */ -#define SCU_GENERAL_MIRRSTS_RMX_Msk \ - (0x2000UL) /*!< SCU_GENERAL MIRRSTS: RMX (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_MIRRSTS_RTC_MSKSR_Pos \ - (14UL) /*!< SCU_GENERAL MIRRSTS: RTC_MSKSR (Bit 14) */ -#define SCU_GENERAL_MIRRSTS_RTC_MSKSR_Msk \ - (0x4000UL) /*!< SCU_GENERAL MIRRSTS: RTC_MSKSR (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_MIRRSTS_RTC_CLRSR_Pos \ - (15UL) /*!< SCU_GENERAL MIRRSTS: RTC_CLRSR (Bit 15) */ -#define SCU_GENERAL_MIRRSTS_RTC_CLRSR_Msk \ - (0x8000UL) /*!< SCU_GENERAL MIRRSTS: RTC_CLRSR (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_MIRRSTS_LPACCONF_Pos \ - (16UL) /*!< SCU_GENERAL MIRRSTS: LPACCONF (Bit 16) */ -#define SCU_GENERAL_MIRRSTS_LPACCONF_Msk \ - (0x10000UL) /*!< SCU_GENERAL MIRRSTS: LPACCONF (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_MIRRSTS_LPACTH0_Pos \ - (17UL) /*!< SCU_GENERAL MIRRSTS: LPACTH0 (Bit 17) */ -#define SCU_GENERAL_MIRRSTS_LPACTH0_Msk \ - (0x20000UL) /*!< SCU_GENERAL MIRRSTS: LPACTH0 (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_MIRRSTS_LPACTH1_Pos \ - (18UL) /*!< SCU_GENERAL MIRRSTS: LPACTH1 (Bit 18) */ -#define SCU_GENERAL_MIRRSTS_LPACTH1_Msk \ - (0x40000UL) /*!< SCU_GENERAL MIRRSTS: LPACTH1 (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_MIRRSTS_LPACCLR_Pos \ - (20UL) /*!< SCU_GENERAL MIRRSTS: LPACCLR (Bit 20) */ -#define SCU_GENERAL_MIRRSTS_LPACCLR_Msk \ - (0x100000UL) /*!< SCU_GENERAL MIRRSTS: LPACCLR (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_MIRRSTS_LPACSET_Pos \ - (21UL) /*!< SCU_GENERAL MIRRSTS: LPACSET (Bit 21) */ -#define SCU_GENERAL_MIRRSTS_LPACSET_Msk \ - (0x200000UL) /*!< SCU_GENERAL MIRRSTS: LPACSET (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_MIRRSTS_HINTCLR_Pos \ - (23UL) /*!< SCU_GENERAL MIRRSTS: HINTCLR (Bit 23) */ -#define SCU_GENERAL_MIRRSTS_HINTCLR_Msk \ - (0x800000UL) /*!< SCU_GENERAL MIRRSTS: HINTCLR (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_MIRRSTS_HINTSET_Pos \ - (24UL) /*!< SCU_GENERAL MIRRSTS: HINTSET (Bit 24) */ -#define SCU_GENERAL_MIRRSTS_HINTSET_Msk \ - (0x1000000UL) /*!< SCU_GENERAL MIRRSTS: HINTSET (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_GENERAL_RMACR ----------------------------- */ -#define SCU_GENERAL_RMACR_RDWR_Pos \ - (0UL) /*!< SCU_GENERAL RMACR: RDWR (Bit 0) */ -#define SCU_GENERAL_RMACR_RDWR_Msk \ - (0x1UL) /*!< SCU_GENERAL RMACR: RDWR (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_RMACR_ADDR_Pos \ - (16UL) /*!< SCU_GENERAL RMACR: ADDR (Bit 16) */ -#define SCU_GENERAL_RMACR_ADDR_Msk \ - (0xf0000UL) /*!< SCU_GENERAL RMACR: ADDR (Bitfield-Mask: 0x0f) */ - -/* ----------------------------- SCU_GENERAL_RMDATA ----------------------------- */ -#define SCU_GENERAL_RMDATA_DATA_Pos \ - (0UL) /*!< SCU_GENERAL RMDATA: DATA (Bit 0) */ -#define SCU_GENERAL_RMDATA_DATA_Msk \ - (0xffffffffUL) /*!< SCU_GENERAL RMDATA: DATA (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------- SCU_GENERAL_MIRRALLSTAT -------------------------- */ -#define SCU_GENERAL_MIRRALLSTAT_BUSY_Pos \ - (0UL) /*!< SCU_GENERAL MIRRALLSTAT: BUSY (Bit 0) */ -#define SCU_GENERAL_MIRRALLSTAT_BUSY_Msk \ - (0x1UL) /*!< SCU_GENERAL MIRRALLSTAT: BUSY (Bitfield-Mask: 0x01) */ - -/* --------------------------- SCU_GENERAL_MIRRALLREQ --------------------------- */ -#define SCU_GENERAL_MIRRALLREQ_REQ_Pos \ - (0UL) /*!< SCU_GENERAL MIRRALLREQ: REQ (Bit 0) */ -#define SCU_GENERAL_MIRRALLREQ_REQ_Msk \ - (0x1UL) /*!< SCU_GENERAL MIRRALLREQ: REQ (Bitfield-Mask: 0x01) */ - -/* ================================================================================ */ -/* ================ struct 'SCU_INTERRUPT' Position & Mask ================ */ -/* ================================================================================ */ - -/* ---------------------------- SCU_INTERRUPT_SRSTAT ---------------------------- */ -#define SCU_INTERRUPT_SRSTAT_PRWARN_Pos \ - (0UL) /*!< SCU_INTERRUPT SRSTAT: PRWARN (Bit 0) */ -#define SCU_INTERRUPT_SRSTAT_PRWARN_Msk \ - (0x1UL) /*!< SCU_INTERRUPT SRSTAT: PRWARN (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSTAT_PI_Pos \ - (1UL) /*!< SCU_INTERRUPT SRSTAT: PI (Bit 1) */ -#define SCU_INTERRUPT_SRSTAT_PI_Msk \ - (0x2UL) /*!< SCU_INTERRUPT SRSTAT: PI (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSTAT_AI_Pos \ - (2UL) /*!< SCU_INTERRUPT SRSTAT: AI (Bit 2) */ -#define SCU_INTERRUPT_SRSTAT_AI_Msk \ - (0x4UL) /*!< SCU_INTERRUPT SRSTAT: AI (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSTAT_DLROVR_Pos \ - (3UL) /*!< SCU_INTERRUPT SRSTAT: DLROVR (Bit 3) */ -#define SCU_INTERRUPT_SRSTAT_DLROVR_Msk \ - (0x8UL) /*!< SCU_INTERRUPT SRSTAT: DLROVR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSTAT_LPACCR_Pos \ - (6UL) /*!< SCU_INTERRUPT SRSTAT: LPACCR (Bit 6) */ -#define SCU_INTERRUPT_SRSTAT_LPACCR_Msk \ - (0x40UL) /*!< SCU_INTERRUPT SRSTAT: LPACCR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSTAT_LPACTH0_Pos \ - (7UL) /*!< SCU_INTERRUPT SRSTAT: LPACTH0 (Bit 7) */ -#define SCU_INTERRUPT_SRSTAT_LPACTH0_Msk \ - (0x80UL) /*!< SCU_INTERRUPT SRSTAT: LPACTH0 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSTAT_LPACTH1_Pos \ - (8UL) /*!< SCU_INTERRUPT SRSTAT: LPACTH1 (Bit 8) */ -#define SCU_INTERRUPT_SRSTAT_LPACTH1_Msk \ - (0x100UL) /*!< SCU_INTERRUPT SRSTAT: LPACTH1 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSTAT_LPACST_Pos \ - (9UL) /*!< SCU_INTERRUPT SRSTAT: LPACST (Bit 9) */ -#define SCU_INTERRUPT_SRSTAT_LPACST_Msk \ - (0x200UL) /*!< SCU_INTERRUPT SRSTAT: LPACST (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSTAT_LPACCLR_Pos \ - (10UL) /*!< SCU_INTERRUPT SRSTAT: LPACCLR (Bit 10) */ -#define SCU_INTERRUPT_SRSTAT_LPACCLR_Msk \ - (0x400UL) /*!< SCU_INTERRUPT SRSTAT: LPACCLR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSTAT_LPACSET_Pos \ - (11UL) /*!< SCU_INTERRUPT SRSTAT: LPACSET (Bit 11) */ -#define SCU_INTERRUPT_SRSTAT_LPACSET_Msk \ - (0x800UL) /*!< SCU_INTERRUPT SRSTAT: LPACSET (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSTAT_HINTST_Pos \ - (12UL) /*!< SCU_INTERRUPT SRSTAT: HINTST (Bit 12) */ -#define SCU_INTERRUPT_SRSTAT_HINTST_Msk \ - (0x1000UL) /*!< SCU_INTERRUPT SRSTAT: HINTST (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSTAT_HINTCLR_Pos \ - (13UL) /*!< SCU_INTERRUPT SRSTAT: HINTCLR (Bit 13) */ -#define SCU_INTERRUPT_SRSTAT_HINTCLR_Msk \ - (0x2000UL) /*!< SCU_INTERRUPT SRSTAT: HINTCLR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSTAT_HINTSET_Pos \ - (14UL) /*!< SCU_INTERRUPT SRSTAT: HINTSET (Bit 14) */ -#define SCU_INTERRUPT_SRSTAT_HINTSET_Msk \ - (0x4000UL) /*!< SCU_INTERRUPT SRSTAT: HINTSET (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSTAT_HDCLR_Pos \ - (17UL) /*!< SCU_INTERRUPT SRSTAT: HDCLR (Bit 17) */ -#define SCU_INTERRUPT_SRSTAT_HDCLR_Msk \ - (0x20000UL) /*!< SCU_INTERRUPT SRSTAT: HDCLR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSTAT_HDSET_Pos \ - (18UL) /*!< SCU_INTERRUPT SRSTAT: HDSET (Bit 18) */ -#define SCU_INTERRUPT_SRSTAT_HDSET_Msk \ - (0x40000UL) /*!< SCU_INTERRUPT SRSTAT: HDSET (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSTAT_HDCR_Pos \ - (19UL) /*!< SCU_INTERRUPT SRSTAT: HDCR (Bit 19) */ -#define SCU_INTERRUPT_SRSTAT_HDCR_Msk \ - (0x80000UL) /*!< SCU_INTERRUPT SRSTAT: HDCR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSTAT_OSCSICTRL_Pos \ - (21UL) /*!< SCU_INTERRUPT SRSTAT: OSCSICTRL (Bit 21) */ -#define SCU_INTERRUPT_SRSTAT_OSCSICTRL_Msk \ - (0x200000UL) /*!< SCU_INTERRUPT SRSTAT: OSCSICTRL (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSTAT_OSCULCTRL_Pos \ - (23UL) /*!< SCU_INTERRUPT SRSTAT: OSCULCTRL (Bit 23) */ -#define SCU_INTERRUPT_SRSTAT_OSCULCTRL_Msk \ - (0x800000UL) /*!< SCU_INTERRUPT SRSTAT: OSCULCTRL (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSTAT_RTC_CTR_Pos \ - (24UL) /*!< SCU_INTERRUPT SRSTAT: RTC_CTR (Bit 24) */ -#define SCU_INTERRUPT_SRSTAT_RTC_CTR_Msk \ - (0x1000000UL) /*!< SCU_INTERRUPT SRSTAT: RTC_CTR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSTAT_RTC_ATIM0_Pos \ - (25UL) /*!< SCU_INTERRUPT SRSTAT: RTC_ATIM0 (Bit 25) */ -#define SCU_INTERRUPT_SRSTAT_RTC_ATIM0_Msk \ - (0x2000000UL) /*!< SCU_INTERRUPT SRSTAT: RTC_ATIM0 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSTAT_RTC_ATIM1_Pos \ - (26UL) /*!< SCU_INTERRUPT SRSTAT: RTC_ATIM1 (Bit 26) */ -#define SCU_INTERRUPT_SRSTAT_RTC_ATIM1_Msk \ - (0x4000000UL) /*!< SCU_INTERRUPT SRSTAT: RTC_ATIM1 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSTAT_RTC_TIM0_Pos \ - (27UL) /*!< SCU_INTERRUPT SRSTAT: RTC_TIM0 (Bit 27) */ -#define SCU_INTERRUPT_SRSTAT_RTC_TIM0_Msk \ - (0x8000000UL) /*!< SCU_INTERRUPT SRSTAT: RTC_TIM0 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSTAT_RTC_TIM1_Pos \ - (28UL) /*!< SCU_INTERRUPT SRSTAT: RTC_TIM1 (Bit 28) */ -#define SCU_INTERRUPT_SRSTAT_RTC_TIM1_Msk \ - (0x10000000UL) /*!< SCU_INTERRUPT SRSTAT: RTC_TIM1 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSTAT_RMX_Pos \ - (29UL) /*!< SCU_INTERRUPT SRSTAT: RMX (Bit 29) */ -#define SCU_INTERRUPT_SRSTAT_RMX_Msk \ - (0x20000000UL) /*!< SCU_INTERRUPT SRSTAT: RMX (Bitfield-Mask: 0x01) */ - -/* ----------------------------- SCU_INTERRUPT_SRRAW ---------------------------- */ -#define SCU_INTERRUPT_SRRAW_PRWARN_Pos \ - (0UL) /*!< SCU_INTERRUPT SRRAW: PRWARN (Bit 0) */ -#define SCU_INTERRUPT_SRRAW_PRWARN_Msk \ - (0x1UL) /*!< SCU_INTERRUPT SRRAW: PRWARN (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRRAW_PI_Pos \ - (1UL) /*!< SCU_INTERRUPT SRRAW: PI (Bit 1) */ -#define SCU_INTERRUPT_SRRAW_PI_Msk \ - (0x2UL) /*!< SCU_INTERRUPT SRRAW: PI (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRRAW_AI_Pos \ - (2UL) /*!< SCU_INTERRUPT SRRAW: AI (Bit 2) */ -#define SCU_INTERRUPT_SRRAW_AI_Msk \ - (0x4UL) /*!< SCU_INTERRUPT SRRAW: AI (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRRAW_DLROVR_Pos \ - (3UL) /*!< SCU_INTERRUPT SRRAW: DLROVR (Bit 3) */ -#define SCU_INTERRUPT_SRRAW_DLROVR_Msk \ - (0x8UL) /*!< SCU_INTERRUPT SRRAW: DLROVR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRRAW_LPACCR_Pos \ - (6UL) /*!< SCU_INTERRUPT SRRAW: LPACCR (Bit 6) */ -#define SCU_INTERRUPT_SRRAW_LPACCR_Msk \ - (0x40UL) /*!< SCU_INTERRUPT SRRAW: LPACCR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRRAW_LPACTH0_Pos \ - (7UL) /*!< SCU_INTERRUPT SRRAW: LPACTH0 (Bit 7) */ -#define SCU_INTERRUPT_SRRAW_LPACTH0_Msk \ - (0x80UL) /*!< SCU_INTERRUPT SRRAW: LPACTH0 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRRAW_LPACTH1_Pos \ - (8UL) /*!< SCU_INTERRUPT SRRAW: LPACTH1 (Bit 8) */ -#define SCU_INTERRUPT_SRRAW_LPACTH1_Msk \ - (0x100UL) /*!< SCU_INTERRUPT SRRAW: LPACTH1 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRRAW_LPACST_Pos \ - (9UL) /*!< SCU_INTERRUPT SRRAW: LPACST (Bit 9) */ -#define SCU_INTERRUPT_SRRAW_LPACST_Msk \ - (0x200UL) /*!< SCU_INTERRUPT SRRAW: LPACST (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRRAW_LPACCLR_Pos \ - (10UL) /*!< SCU_INTERRUPT SRRAW: LPACCLR (Bit 10) */ -#define SCU_INTERRUPT_SRRAW_LPACCLR_Msk \ - (0x400UL) /*!< SCU_INTERRUPT SRRAW: LPACCLR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRRAW_LPACSET_Pos \ - (11UL) /*!< SCU_INTERRUPT SRRAW: LPACSET (Bit 11) */ -#define SCU_INTERRUPT_SRRAW_LPACSET_Msk \ - (0x800UL) /*!< SCU_INTERRUPT SRRAW: LPACSET (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRRAW_HINTST_Pos \ - (12UL) /*!< SCU_INTERRUPT SRRAW: HINTST (Bit 12) */ -#define SCU_INTERRUPT_SRRAW_HINTST_Msk \ - (0x1000UL) /*!< SCU_INTERRUPT SRRAW: HINTST (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRRAW_HINTCLR_Pos \ - (13UL) /*!< SCU_INTERRUPT SRRAW: HINTCLR (Bit 13) */ -#define SCU_INTERRUPT_SRRAW_HINTCLR_Msk \ - (0x2000UL) /*!< SCU_INTERRUPT SRRAW: HINTCLR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRRAW_HINTSET_Pos \ - (14UL) /*!< SCU_INTERRUPT SRRAW: HINTSET (Bit 14) */ -#define SCU_INTERRUPT_SRRAW_HINTSET_Msk \ - (0x4000UL) /*!< SCU_INTERRUPT SRRAW: HINTSET (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRRAW_HDCLR_Pos \ - (17UL) /*!< SCU_INTERRUPT SRRAW: HDCLR (Bit 17) */ -#define SCU_INTERRUPT_SRRAW_HDCLR_Msk \ - (0x20000UL) /*!< SCU_INTERRUPT SRRAW: HDCLR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRRAW_HDSET_Pos \ - (18UL) /*!< SCU_INTERRUPT SRRAW: HDSET (Bit 18) */ -#define SCU_INTERRUPT_SRRAW_HDSET_Msk \ - (0x40000UL) /*!< SCU_INTERRUPT SRRAW: HDSET (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRRAW_HDCR_Pos \ - (19UL) /*!< SCU_INTERRUPT SRRAW: HDCR (Bit 19) */ -#define SCU_INTERRUPT_SRRAW_HDCR_Msk \ - (0x80000UL) /*!< SCU_INTERRUPT SRRAW: HDCR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRRAW_OSCSICTRL_Pos \ - (21UL) /*!< SCU_INTERRUPT SRRAW: OSCSICTRL (Bit 21) */ -#define SCU_INTERRUPT_SRRAW_OSCSICTRL_Msk \ - (0x200000UL) /*!< SCU_INTERRUPT SRRAW: OSCSICTRL (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRRAW_OSCULCTRL_Pos \ - (23UL) /*!< SCU_INTERRUPT SRRAW: OSCULCTRL (Bit 23) */ -#define SCU_INTERRUPT_SRRAW_OSCULCTRL_Msk \ - (0x800000UL) /*!< SCU_INTERRUPT SRRAW: OSCULCTRL (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRRAW_RTC_CTR_Pos \ - (24UL) /*!< SCU_INTERRUPT SRRAW: RTC_CTR (Bit 24) */ -#define SCU_INTERRUPT_SRRAW_RTC_CTR_Msk \ - (0x1000000UL) /*!< SCU_INTERRUPT SRRAW: RTC_CTR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRRAW_RTC_ATIM0_Pos \ - (25UL) /*!< SCU_INTERRUPT SRRAW: RTC_ATIM0 (Bit 25) */ -#define SCU_INTERRUPT_SRRAW_RTC_ATIM0_Msk \ - (0x2000000UL) /*!< SCU_INTERRUPT SRRAW: RTC_ATIM0 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRRAW_RTC_ATIM1_Pos \ - (26UL) /*!< SCU_INTERRUPT SRRAW: RTC_ATIM1 (Bit 26) */ -#define SCU_INTERRUPT_SRRAW_RTC_ATIM1_Msk \ - (0x4000000UL) /*!< SCU_INTERRUPT SRRAW: RTC_ATIM1 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRRAW_RTC_TIM0_Pos \ - (27UL) /*!< SCU_INTERRUPT SRRAW: RTC_TIM0 (Bit 27) */ -#define SCU_INTERRUPT_SRRAW_RTC_TIM0_Msk \ - (0x8000000UL) /*!< SCU_INTERRUPT SRRAW: RTC_TIM0 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRRAW_RTC_TIM1_Pos \ - (28UL) /*!< SCU_INTERRUPT SRRAW: RTC_TIM1 (Bit 28) */ -#define SCU_INTERRUPT_SRRAW_RTC_TIM1_Msk \ - (0x10000000UL) /*!< SCU_INTERRUPT SRRAW: RTC_TIM1 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRRAW_RMX_Pos \ - (29UL) /*!< SCU_INTERRUPT SRRAW: RMX (Bit 29) */ -#define SCU_INTERRUPT_SRRAW_RMX_Msk \ - (0x20000000UL) /*!< SCU_INTERRUPT SRRAW: RMX (Bitfield-Mask: 0x01) */ - -/* ----------------------------- SCU_INTERRUPT_SRMSK ---------------------------- */ -#define SCU_INTERRUPT_SRMSK_PRWARN_Pos \ - (0UL) /*!< SCU_INTERRUPT SRMSK: PRWARN (Bit 0) */ -#define SCU_INTERRUPT_SRMSK_PRWARN_Msk \ - (0x1UL) /*!< SCU_INTERRUPT SRMSK: PRWARN (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRMSK_PI_Pos \ - (1UL) /*!< SCU_INTERRUPT SRMSK: PI (Bit 1) */ -#define SCU_INTERRUPT_SRMSK_PI_Msk \ - (0x2UL) /*!< SCU_INTERRUPT SRMSK: PI (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRMSK_AI_Pos \ - (2UL) /*!< SCU_INTERRUPT SRMSK: AI (Bit 2) */ -#define SCU_INTERRUPT_SRMSK_AI_Msk \ - (0x4UL) /*!< SCU_INTERRUPT SRMSK: AI (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRMSK_DLROVR_Pos \ - (3UL) /*!< SCU_INTERRUPT SRMSK: DLROVR (Bit 3) */ -#define SCU_INTERRUPT_SRMSK_DLROVR_Msk \ - (0x8UL) /*!< SCU_INTERRUPT SRMSK: DLROVR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRMSK_LPACCR_Pos \ - (6UL) /*!< SCU_INTERRUPT SRMSK: LPACCR (Bit 6) */ -#define SCU_INTERRUPT_SRMSK_LPACCR_Msk \ - (0x40UL) /*!< SCU_INTERRUPT SRMSK: LPACCR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRMSK_LPACTH0_Pos \ - (7UL) /*!< SCU_INTERRUPT SRMSK: LPACTH0 (Bit 7) */ -#define SCU_INTERRUPT_SRMSK_LPACTH0_Msk \ - (0x80UL) /*!< SCU_INTERRUPT SRMSK: LPACTH0 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRMSK_LPACTH1_Pos \ - (8UL) /*!< SCU_INTERRUPT SRMSK: LPACTH1 (Bit 8) */ -#define SCU_INTERRUPT_SRMSK_LPACTH1_Msk \ - (0x100UL) /*!< SCU_INTERRUPT SRMSK: LPACTH1 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRMSK_LPACST_Pos \ - (9UL) /*!< SCU_INTERRUPT SRMSK: LPACST (Bit 9) */ -#define SCU_INTERRUPT_SRMSK_LPACST_Msk \ - (0x200UL) /*!< SCU_INTERRUPT SRMSK: LPACST (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRMSK_LPACCLR_Pos \ - (10UL) /*!< SCU_INTERRUPT SRMSK: LPACCLR (Bit 10) */ -#define SCU_INTERRUPT_SRMSK_LPACCLR_Msk \ - (0x400UL) /*!< SCU_INTERRUPT SRMSK: LPACCLR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRMSK_LPACSET_Pos \ - (11UL) /*!< SCU_INTERRUPT SRMSK: LPACSET (Bit 11) */ -#define SCU_INTERRUPT_SRMSK_LPACSET_Msk \ - (0x800UL) /*!< SCU_INTERRUPT SRMSK: LPACSET (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRMSK_HINTST_Pos \ - (12UL) /*!< SCU_INTERRUPT SRMSK: HINTST (Bit 12) */ -#define SCU_INTERRUPT_SRMSK_HINTST_Msk \ - (0x1000UL) /*!< SCU_INTERRUPT SRMSK: HINTST (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRMSK_HINTCLR_Pos \ - (13UL) /*!< SCU_INTERRUPT SRMSK: HINTCLR (Bit 13) */ -#define SCU_INTERRUPT_SRMSK_HINTCLR_Msk \ - (0x2000UL) /*!< SCU_INTERRUPT SRMSK: HINTCLR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRMSK_HINTSET_Pos \ - (14UL) /*!< SCU_INTERRUPT SRMSK: HINTSET (Bit 14) */ -#define SCU_INTERRUPT_SRMSK_HINTSET_Msk \ - (0x4000UL) /*!< SCU_INTERRUPT SRMSK: HINTSET (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRMSK_HDCLR_Pos \ - (17UL) /*!< SCU_INTERRUPT SRMSK: HDCLR (Bit 17) */ -#define SCU_INTERRUPT_SRMSK_HDCLR_Msk \ - (0x20000UL) /*!< SCU_INTERRUPT SRMSK: HDCLR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRMSK_HDSET_Pos \ - (18UL) /*!< SCU_INTERRUPT SRMSK: HDSET (Bit 18) */ -#define SCU_INTERRUPT_SRMSK_HDSET_Msk \ - (0x40000UL) /*!< SCU_INTERRUPT SRMSK: HDSET (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRMSK_HDCR_Pos \ - (19UL) /*!< SCU_INTERRUPT SRMSK: HDCR (Bit 19) */ -#define SCU_INTERRUPT_SRMSK_HDCR_Msk \ - (0x80000UL) /*!< SCU_INTERRUPT SRMSK: HDCR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRMSK_OSCSICTRL_Pos \ - (21UL) /*!< SCU_INTERRUPT SRMSK: OSCSICTRL (Bit 21) */ -#define SCU_INTERRUPT_SRMSK_OSCSICTRL_Msk \ - (0x200000UL) /*!< SCU_INTERRUPT SRMSK: OSCSICTRL (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRMSK_OSCULCTRL_Pos \ - (23UL) /*!< SCU_INTERRUPT SRMSK: OSCULCTRL (Bit 23) */ -#define SCU_INTERRUPT_SRMSK_OSCULCTRL_Msk \ - (0x800000UL) /*!< SCU_INTERRUPT SRMSK: OSCULCTRL (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRMSK_RTC_CTR_Pos \ - (24UL) /*!< SCU_INTERRUPT SRMSK: RTC_CTR (Bit 24) */ -#define SCU_INTERRUPT_SRMSK_RTC_CTR_Msk \ - (0x1000000UL) /*!< SCU_INTERRUPT SRMSK: RTC_CTR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRMSK_RTC_ATIM0_Pos \ - (25UL) /*!< SCU_INTERRUPT SRMSK: RTC_ATIM0 (Bit 25) */ -#define SCU_INTERRUPT_SRMSK_RTC_ATIM0_Msk \ - (0x2000000UL) /*!< SCU_INTERRUPT SRMSK: RTC_ATIM0 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRMSK_RTC_ATIM1_Pos \ - (26UL) /*!< SCU_INTERRUPT SRMSK: RTC_ATIM1 (Bit 26) */ -#define SCU_INTERRUPT_SRMSK_RTC_ATIM1_Msk \ - (0x4000000UL) /*!< SCU_INTERRUPT SRMSK: RTC_ATIM1 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRMSK_RTC_TIM0_Pos \ - (27UL) /*!< SCU_INTERRUPT SRMSK: RTC_TIM0 (Bit 27) */ -#define SCU_INTERRUPT_SRMSK_RTC_TIM0_Msk \ - (0x8000000UL) /*!< SCU_INTERRUPT SRMSK: RTC_TIM0 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRMSK_RTC_TIM1_Pos \ - (28UL) /*!< SCU_INTERRUPT SRMSK: RTC_TIM1 (Bit 28) */ -#define SCU_INTERRUPT_SRMSK_RTC_TIM1_Msk \ - (0x10000000UL) /*!< SCU_INTERRUPT SRMSK: RTC_TIM1 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRMSK_RMX_Pos \ - (29UL) /*!< SCU_INTERRUPT SRMSK: RMX (Bit 29) */ -#define SCU_INTERRUPT_SRMSK_RMX_Msk \ - (0x20000000UL) /*!< SCU_INTERRUPT SRMSK: RMX (Bitfield-Mask: 0x01) */ - -/* ----------------------------- SCU_INTERRUPT_SRCLR ---------------------------- */ -#define SCU_INTERRUPT_SRCLR_PRWARN_Pos \ - (0UL) /*!< SCU_INTERRUPT SRCLR: PRWARN (Bit 0) */ -#define SCU_INTERRUPT_SRCLR_PRWARN_Msk \ - (0x1UL) /*!< SCU_INTERRUPT SRCLR: PRWARN (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRCLR_PI_Pos \ - (1UL) /*!< SCU_INTERRUPT SRCLR: PI (Bit 1) */ -#define SCU_INTERRUPT_SRCLR_PI_Msk \ - (0x2UL) /*!< SCU_INTERRUPT SRCLR: PI (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRCLR_AI_Pos \ - (2UL) /*!< SCU_INTERRUPT SRCLR: AI (Bit 2) */ -#define SCU_INTERRUPT_SRCLR_AI_Msk \ - (0x4UL) /*!< SCU_INTERRUPT SRCLR: AI (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRCLR_DLROVR_Pos \ - (3UL) /*!< SCU_INTERRUPT SRCLR: DLROVR (Bit 3) */ -#define SCU_INTERRUPT_SRCLR_DLROVR_Msk \ - (0x8UL) /*!< SCU_INTERRUPT SRCLR: DLROVR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRCLR_LPACCR_Pos \ - (6UL) /*!< SCU_INTERRUPT SRCLR: LPACCR (Bit 6) */ -#define SCU_INTERRUPT_SRCLR_LPACCR_Msk \ - (0x40UL) /*!< SCU_INTERRUPT SRCLR: LPACCR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRCLR_LPACTH0_Pos \ - (7UL) /*!< SCU_INTERRUPT SRCLR: LPACTH0 (Bit 7) */ -#define SCU_INTERRUPT_SRCLR_LPACTH0_Msk \ - (0x80UL) /*!< SCU_INTERRUPT SRCLR: LPACTH0 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRCLR_LPACTH1_Pos \ - (8UL) /*!< SCU_INTERRUPT SRCLR: LPACTH1 (Bit 8) */ -#define SCU_INTERRUPT_SRCLR_LPACTH1_Msk \ - (0x100UL) /*!< SCU_INTERRUPT SRCLR: LPACTH1 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRCLR_LPACST_Pos \ - (9UL) /*!< SCU_INTERRUPT SRCLR: LPACST (Bit 9) */ -#define SCU_INTERRUPT_SRCLR_LPACST_Msk \ - (0x200UL) /*!< SCU_INTERRUPT SRCLR: LPACST (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRCLR_LPACCLR_Pos \ - (10UL) /*!< SCU_INTERRUPT SRCLR: LPACCLR (Bit 10) */ -#define SCU_INTERRUPT_SRCLR_LPACCLR_Msk \ - (0x400UL) /*!< SCU_INTERRUPT SRCLR: LPACCLR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRCLR_LPACSET_Pos \ - (11UL) /*!< SCU_INTERRUPT SRCLR: LPACSET (Bit 11) */ -#define SCU_INTERRUPT_SRCLR_LPACSET_Msk \ - (0x800UL) /*!< SCU_INTERRUPT SRCLR: LPACSET (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRCLR_HINTST_Pos \ - (12UL) /*!< SCU_INTERRUPT SRCLR: HINTST (Bit 12) */ -#define SCU_INTERRUPT_SRCLR_HINTST_Msk \ - (0x1000UL) /*!< SCU_INTERRUPT SRCLR: HINTST (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRCLR_HINTCLR_Pos \ - (13UL) /*!< SCU_INTERRUPT SRCLR: HINTCLR (Bit 13) */ -#define SCU_INTERRUPT_SRCLR_HINTCLR_Msk \ - (0x2000UL) /*!< SCU_INTERRUPT SRCLR: HINTCLR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRCLR_HINTSET_Pos \ - (14UL) /*!< SCU_INTERRUPT SRCLR: HINTSET (Bit 14) */ -#define SCU_INTERRUPT_SRCLR_HINTSET_Msk \ - (0x4000UL) /*!< SCU_INTERRUPT SRCLR: HINTSET (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRCLR_HDCLR_Pos \ - (17UL) /*!< SCU_INTERRUPT SRCLR: HDCLR (Bit 17) */ -#define SCU_INTERRUPT_SRCLR_HDCLR_Msk \ - (0x20000UL) /*!< SCU_INTERRUPT SRCLR: HDCLR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRCLR_HDSET_Pos \ - (18UL) /*!< SCU_INTERRUPT SRCLR: HDSET (Bit 18) */ -#define SCU_INTERRUPT_SRCLR_HDSET_Msk \ - (0x40000UL) /*!< SCU_INTERRUPT SRCLR: HDSET (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRCLR_HDCR_Pos \ - (19UL) /*!< SCU_INTERRUPT SRCLR: HDCR (Bit 19) */ -#define SCU_INTERRUPT_SRCLR_HDCR_Msk \ - (0x80000UL) /*!< SCU_INTERRUPT SRCLR: HDCR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRCLR_OSCSICTRL_Pos \ - (21UL) /*!< SCU_INTERRUPT SRCLR: OSCSICTRL (Bit 21) */ -#define SCU_INTERRUPT_SRCLR_OSCSICTRL_Msk \ - (0x200000UL) /*!< SCU_INTERRUPT SRCLR: OSCSICTRL (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRCLR_OSCULCTRL_Pos \ - (23UL) /*!< SCU_INTERRUPT SRCLR: OSCULCTRL (Bit 23) */ -#define SCU_INTERRUPT_SRCLR_OSCULCTRL_Msk \ - (0x800000UL) /*!< SCU_INTERRUPT SRCLR: OSCULCTRL (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRCLR_RTC_CTR_Pos \ - (24UL) /*!< SCU_INTERRUPT SRCLR: RTC_CTR (Bit 24) */ -#define SCU_INTERRUPT_SRCLR_RTC_CTR_Msk \ - (0x1000000UL) /*!< SCU_INTERRUPT SRCLR: RTC_CTR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRCLR_RTC_ATIM0_Pos \ - (25UL) /*!< SCU_INTERRUPT SRCLR: RTC_ATIM0 (Bit 25) */ -#define SCU_INTERRUPT_SRCLR_RTC_ATIM0_Msk \ - (0x2000000UL) /*!< SCU_INTERRUPT SRCLR: RTC_ATIM0 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRCLR_RTC_ATIM1_Pos \ - (26UL) /*!< SCU_INTERRUPT SRCLR: RTC_ATIM1 (Bit 26) */ -#define SCU_INTERRUPT_SRCLR_RTC_ATIM1_Msk \ - (0x4000000UL) /*!< SCU_INTERRUPT SRCLR: RTC_ATIM1 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRCLR_RTC_TIM0_Pos \ - (27UL) /*!< SCU_INTERRUPT SRCLR: RTC_TIM0 (Bit 27) */ -#define SCU_INTERRUPT_SRCLR_RTC_TIM0_Msk \ - (0x8000000UL) /*!< SCU_INTERRUPT SRCLR: RTC_TIM0 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRCLR_RTC_TIM1_Pos \ - (28UL) /*!< SCU_INTERRUPT SRCLR: RTC_TIM1 (Bit 28) */ -#define SCU_INTERRUPT_SRCLR_RTC_TIM1_Msk \ - (0x10000000UL) /*!< SCU_INTERRUPT SRCLR: RTC_TIM1 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRCLR_RMX_Pos \ - (29UL) /*!< SCU_INTERRUPT SRCLR: RMX (Bit 29) */ -#define SCU_INTERRUPT_SRCLR_RMX_Msk \ - (0x20000000UL) /*!< SCU_INTERRUPT SRCLR: RMX (Bitfield-Mask: 0x01) */ - -/* ----------------------------- SCU_INTERRUPT_SRSET ---------------------------- */ -#define SCU_INTERRUPT_SRSET_PRWARN_Pos \ - (0UL) /*!< SCU_INTERRUPT SRSET: PRWARN (Bit 0) */ -#define SCU_INTERRUPT_SRSET_PRWARN_Msk \ - (0x1UL) /*!< SCU_INTERRUPT SRSET: PRWARN (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSET_PI_Pos \ - (1UL) /*!< SCU_INTERRUPT SRSET: PI (Bit 1) */ -#define SCU_INTERRUPT_SRSET_PI_Msk \ - (0x2UL) /*!< SCU_INTERRUPT SRSET: PI (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSET_AI_Pos \ - (2UL) /*!< SCU_INTERRUPT SRSET: AI (Bit 2) */ -#define SCU_INTERRUPT_SRSET_AI_Msk \ - (0x4UL) /*!< SCU_INTERRUPT SRSET: AI (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSET_DLROVR_Pos \ - (3UL) /*!< SCU_INTERRUPT SRSET: DLROVR (Bit 3) */ -#define SCU_INTERRUPT_SRSET_DLROVR_Msk \ - (0x8UL) /*!< SCU_INTERRUPT SRSET: DLROVR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSET_LPACCR_Pos \ - (6UL) /*!< SCU_INTERRUPT SRSET: LPACCR (Bit 6) */ -#define SCU_INTERRUPT_SRSET_LPACCR_Msk \ - (0x40UL) /*!< SCU_INTERRUPT SRSET: LPACCR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSET_LPACTH0_Pos \ - (7UL) /*!< SCU_INTERRUPT SRSET: LPACTH0 (Bit 7) */ -#define SCU_INTERRUPT_SRSET_LPACTH0_Msk \ - (0x80UL) /*!< SCU_INTERRUPT SRSET: LPACTH0 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSET_LPACTH1_Pos \ - (8UL) /*!< SCU_INTERRUPT SRSET: LPACTH1 (Bit 8) */ -#define SCU_INTERRUPT_SRSET_LPACTH1_Msk \ - (0x100UL) /*!< SCU_INTERRUPT SRSET: LPACTH1 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSET_LPACST_Pos \ - (9UL) /*!< SCU_INTERRUPT SRSET: LPACST (Bit 9) */ -#define SCU_INTERRUPT_SRSET_LPACST_Msk \ - (0x200UL) /*!< SCU_INTERRUPT SRSET: LPACST (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSET_LPACCLR_Pos \ - (10UL) /*!< SCU_INTERRUPT SRSET: LPACCLR (Bit 10) */ -#define SCU_INTERRUPT_SRSET_LPACCLR_Msk \ - (0x400UL) /*!< SCU_INTERRUPT SRSET: LPACCLR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSET_LPACSET_Pos \ - (11UL) /*!< SCU_INTERRUPT SRSET: LPACSET (Bit 11) */ -#define SCU_INTERRUPT_SRSET_LPACSET_Msk \ - (0x800UL) /*!< SCU_INTERRUPT SRSET: LPACSET (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSET_HINTST_Pos \ - (12UL) /*!< SCU_INTERRUPT SRSET: HINTST (Bit 12) */ -#define SCU_INTERRUPT_SRSET_HINTST_Msk \ - (0x1000UL) /*!< SCU_INTERRUPT SRSET: HINTST (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSET_HINTCLR_Pos \ - (13UL) /*!< SCU_INTERRUPT SRSET: HINTCLR (Bit 13) */ -#define SCU_INTERRUPT_SRSET_HINTCLR_Msk \ - (0x2000UL) /*!< SCU_INTERRUPT SRSET: HINTCLR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSET_HINTSET_Pos \ - (14UL) /*!< SCU_INTERRUPT SRSET: HINTSET (Bit 14) */ -#define SCU_INTERRUPT_SRSET_HINTSET_Msk \ - (0x4000UL) /*!< SCU_INTERRUPT SRSET: HINTSET (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSET_HDCRCLR_Pos \ - (17UL) /*!< SCU_INTERRUPT SRSET: HDCRCLR (Bit 17) */ -#define SCU_INTERRUPT_SRSET_HDCRCLR_Msk \ - (0x20000UL) /*!< SCU_INTERRUPT SRSET: HDCRCLR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSET_HDCRSET_Pos \ - (18UL) /*!< SCU_INTERRUPT SRSET: HDCRSET (Bit 18) */ -#define SCU_INTERRUPT_SRSET_HDCRSET_Msk \ - (0x40000UL) /*!< SCU_INTERRUPT SRSET: HDCRSET (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSET_HDCR_Pos \ - (19UL) /*!< SCU_INTERRUPT SRSET: HDCR (Bit 19) */ -#define SCU_INTERRUPT_SRSET_HDCR_Msk \ - (0x80000UL) /*!< SCU_INTERRUPT SRSET: HDCR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSET_OSCSICTRL_Pos \ - (21UL) /*!< SCU_INTERRUPT SRSET: OSCSICTRL (Bit 21) */ -#define SCU_INTERRUPT_SRSET_OSCSICTRL_Msk \ - (0x200000UL) /*!< SCU_INTERRUPT SRSET: OSCSICTRL (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSET_OSCULCTRL_Pos \ - (23UL) /*!< SCU_INTERRUPT SRSET: OSCULCTRL (Bit 23) */ -#define SCU_INTERRUPT_SRSET_OSCULCTRL_Msk \ - (0x800000UL) /*!< SCU_INTERRUPT SRSET: OSCULCTRL (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSET_RTC_CTR_Pos \ - (24UL) /*!< SCU_INTERRUPT SRSET: RTC_CTR (Bit 24) */ -#define SCU_INTERRUPT_SRSET_RTC_CTR_Msk \ - (0x1000000UL) /*!< SCU_INTERRUPT SRSET: RTC_CTR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSET_RTC_ATIM0_Pos \ - (25UL) /*!< SCU_INTERRUPT SRSET: RTC_ATIM0 (Bit 25) */ -#define SCU_INTERRUPT_SRSET_RTC_ATIM0_Msk \ - (0x2000000UL) /*!< SCU_INTERRUPT SRSET: RTC_ATIM0 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSET_RTC_ATIM1_Pos \ - (26UL) /*!< SCU_INTERRUPT SRSET: RTC_ATIM1 (Bit 26) */ -#define SCU_INTERRUPT_SRSET_RTC_ATIM1_Msk \ - (0x4000000UL) /*!< SCU_INTERRUPT SRSET: RTC_ATIM1 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSET_RTC_TIM0_Pos \ - (27UL) /*!< SCU_INTERRUPT SRSET: RTC_TIM0 (Bit 27) */ -#define SCU_INTERRUPT_SRSET_RTC_TIM0_Msk \ - (0x8000000UL) /*!< SCU_INTERRUPT SRSET: RTC_TIM0 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSET_RTC_TIM1_Pos \ - (28UL) /*!< SCU_INTERRUPT SRSET: RTC_TIM1 (Bit 28) */ -#define SCU_INTERRUPT_SRSET_RTC_TIM1_Msk \ - (0x10000000UL) /*!< SCU_INTERRUPT SRSET: RTC_TIM1 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSET_RMX_Pos \ - (29UL) /*!< SCU_INTERRUPT SRSET: RMX (Bit 29) */ -#define SCU_INTERRUPT_SRSET_RMX_Msk \ - (0x20000000UL) /*!< SCU_INTERRUPT SRSET: RMX (Bitfield-Mask: 0x01) */ - -/* --------------------------- SCU_INTERRUPT_NMIREQEN --------------------------- */ -#define SCU_INTERRUPT_NMIREQEN_PRWARN_Pos \ - (0UL) /*!< SCU_INTERRUPT NMIREQEN: PRWARN (Bit 0) */ -#define SCU_INTERRUPT_NMIREQEN_PRWARN_Msk \ - (0x1UL) /*!< SCU_INTERRUPT NMIREQEN: PRWARN (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_NMIREQEN_PI_Pos \ - (1UL) /*!< SCU_INTERRUPT NMIREQEN: PI (Bit 1) */ -#define SCU_INTERRUPT_NMIREQEN_PI_Msk \ - (0x2UL) /*!< SCU_INTERRUPT NMIREQEN: PI (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_NMIREQEN_AI_Pos \ - (2UL) /*!< SCU_INTERRUPT NMIREQEN: AI (Bit 2) */ -#define SCU_INTERRUPT_NMIREQEN_AI_Msk \ - (0x4UL) /*!< SCU_INTERRUPT NMIREQEN: AI (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_NMIREQEN_ERU00_Pos \ - (16UL) /*!< SCU_INTERRUPT NMIREQEN: ERU00 (Bit 16) */ -#define SCU_INTERRUPT_NMIREQEN_ERU00_Msk \ - (0x10000UL) /*!< SCU_INTERRUPT NMIREQEN: ERU00 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_NMIREQEN_ERU01_Pos \ - (17UL) /*!< SCU_INTERRUPT NMIREQEN: ERU01 (Bit 17) */ -#define SCU_INTERRUPT_NMIREQEN_ERU01_Msk \ - (0x20000UL) /*!< SCU_INTERRUPT NMIREQEN: ERU01 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_NMIREQEN_ERU02_Pos \ - (18UL) /*!< SCU_INTERRUPT NMIREQEN: ERU02 (Bit 18) */ -#define SCU_INTERRUPT_NMIREQEN_ERU02_Msk \ - (0x40000UL) /*!< SCU_INTERRUPT NMIREQEN: ERU02 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_NMIREQEN_ERU03_Pos \ - (19UL) /*!< SCU_INTERRUPT NMIREQEN: ERU03 (Bit 19) */ -#define SCU_INTERRUPT_NMIREQEN_ERU03_Msk \ - (0x80000UL) /*!< SCU_INTERRUPT NMIREQEN: ERU03 (Bitfield-Mask: 0x01) */ - -/* ================================================================================ */ -/* ================ struct 'SCU_PARITY' Position & Mask ================ */ -/* ================================================================================ */ - -/* ------------------------------- SCU_PARITY_PEEN ------------------------------ */ -#define SCU_PARITY_PEEN_PEENPS_Pos \ - (0UL) /*!< SCU_PARITY PEEN: PEENPS (Bit 0) */ -#define SCU_PARITY_PEEN_PEENPS_Msk \ - (0x1UL) /*!< SCU_PARITY PEEN: PEENPS (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PEEN_PEENDS1_Pos \ - (1UL) /*!< SCU_PARITY PEEN: PEENDS1 (Bit 1) */ -#define SCU_PARITY_PEEN_PEENDS1_Msk \ - (0x2UL) /*!< SCU_PARITY PEEN: PEENDS1 (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PEEN_PEENU0_Pos \ - (8UL) /*!< SCU_PARITY PEEN: PEENU0 (Bit 8) */ -#define SCU_PARITY_PEEN_PEENU0_Msk \ - (0x100UL) /*!< SCU_PARITY PEEN: PEENU0 (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PEEN_PEENU1_Pos \ - (9UL) /*!< SCU_PARITY PEEN: PEENU1 (Bit 9) */ -#define SCU_PARITY_PEEN_PEENU1_Msk \ - (0x200UL) /*!< SCU_PARITY PEEN: PEENU1 (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PEEN_PEENMC_Pos \ - (12UL) /*!< SCU_PARITY PEEN: PEENMC (Bit 12) */ -#define SCU_PARITY_PEEN_PEENMC_Msk \ - (0x1000UL) /*!< SCU_PARITY PEEN: PEENMC (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PEEN_PEENPPRF_Pos \ - (13UL) /*!< SCU_PARITY PEEN: PEENPPRF (Bit 13) */ -#define SCU_PARITY_PEEN_PEENPPRF_Msk \ - (0x2000UL) /*!< SCU_PARITY PEEN: PEENPPRF (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PEEN_PEENUSB_Pos \ - (16UL) /*!< SCU_PARITY PEEN: PEENUSB (Bit 16) */ -#define SCU_PARITY_PEEN_PEENUSB_Msk \ - (0x10000UL) /*!< SCU_PARITY PEEN: PEENUSB (Bitfield-Mask: 0x01) */ - -/* ----------------------------- SCU_PARITY_MCHKCON ----------------------------- */ -#define SCU_PARITY_MCHKCON_SELPS_Pos \ - (0UL) /*!< SCU_PARITY MCHKCON: SELPS (Bit 0) */ -#define SCU_PARITY_MCHKCON_SELPS_Msk \ - (0x1UL) /*!< SCU_PARITY MCHKCON: SELPS (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_MCHKCON_SELDS1_Pos \ - (1UL) /*!< SCU_PARITY MCHKCON: SELDS1 (Bit 1) */ -#define SCU_PARITY_MCHKCON_SELDS1_Msk \ - (0x2UL) /*!< SCU_PARITY MCHKCON: SELDS1 (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_MCHKCON_USIC0DRA_Pos \ - (8UL) /*!< SCU_PARITY MCHKCON: USIC0DRA (Bit 8) */ -#define SCU_PARITY_MCHKCON_USIC0DRA_Msk \ - (0x100UL) /*!< SCU_PARITY MCHKCON: USIC0DRA (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_MCHKCON_USIC1DRA_Pos \ - (9UL) /*!< SCU_PARITY MCHKCON: USIC1DRA (Bit 9) */ -#define SCU_PARITY_MCHKCON_USIC1DRA_Msk \ - (0x200UL) /*!< SCU_PARITY MCHKCON: USIC1DRA (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_MCHKCON_MCANDRA_Pos \ - (12UL) /*!< SCU_PARITY MCHKCON: MCANDRA (Bit 12) */ -#define SCU_PARITY_MCHKCON_MCANDRA_Msk \ - (0x1000UL) /*!< SCU_PARITY MCHKCON: MCANDRA (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_MCHKCON_PPRFDRA_Pos \ - (13UL) /*!< SCU_PARITY MCHKCON: PPRFDRA (Bit 13) */ -#define SCU_PARITY_MCHKCON_PPRFDRA_Msk \ - (0x2000UL) /*!< SCU_PARITY MCHKCON: PPRFDRA (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_MCHKCON_SELUSB_Pos \ - (16UL) /*!< SCU_PARITY MCHKCON: SELUSB (Bit 16) */ -#define SCU_PARITY_MCHKCON_SELUSB_Msk \ - (0x10000UL) /*!< SCU_PARITY MCHKCON: SELUSB (Bitfield-Mask: 0x01) */ - -/* ------------------------------- SCU_PARITY_PETE ------------------------------ */ -#define SCU_PARITY_PETE_PETEPS_Pos \ - (0UL) /*!< SCU_PARITY PETE: PETEPS (Bit 0) */ -#define SCU_PARITY_PETE_PETEPS_Msk \ - (0x1UL) /*!< SCU_PARITY PETE: PETEPS (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PETE_PETEDS1_Pos \ - (1UL) /*!< SCU_PARITY PETE: PETEDS1 (Bit 1) */ -#define SCU_PARITY_PETE_PETEDS1_Msk \ - (0x2UL) /*!< SCU_PARITY PETE: PETEDS1 (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PETE_PETEU0_Pos \ - (8UL) /*!< SCU_PARITY PETE: PETEU0 (Bit 8) */ -#define SCU_PARITY_PETE_PETEU0_Msk \ - (0x100UL) /*!< SCU_PARITY PETE: PETEU0 (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PETE_PETEU1_Pos \ - (9UL) /*!< SCU_PARITY PETE: PETEU1 (Bit 9) */ -#define SCU_PARITY_PETE_PETEU1_Msk \ - (0x200UL) /*!< SCU_PARITY PETE: PETEU1 (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PETE_PETEMC_Pos \ - (12UL) /*!< SCU_PARITY PETE: PETEMC (Bit 12) */ -#define SCU_PARITY_PETE_PETEMC_Msk \ - (0x1000UL) /*!< SCU_PARITY PETE: PETEMC (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PETE_PETEPPRF_Pos \ - (13UL) /*!< SCU_PARITY PETE: PETEPPRF (Bit 13) */ -#define SCU_PARITY_PETE_PETEPPRF_Msk \ - (0x2000UL) /*!< SCU_PARITY PETE: PETEPPRF (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PETE_PETEUSB_Pos \ - (16UL) /*!< SCU_PARITY PETE: PETEUSB (Bit 16) */ -#define SCU_PARITY_PETE_PETEUSB_Msk \ - (0x10000UL) /*!< SCU_PARITY PETE: PETEUSB (Bitfield-Mask: 0x01) */ - -/* ----------------------------- SCU_PARITY_PERSTEN ----------------------------- */ -#define SCU_PARITY_PERSTEN_RSEN_Pos \ - (0UL) /*!< SCU_PARITY PERSTEN: RSEN (Bit 0) */ -#define SCU_PARITY_PERSTEN_RSEN_Msk \ - (0x1UL) /*!< SCU_PARITY PERSTEN: RSEN (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_PARITY_PEFLAG ----------------------------- */ -#define SCU_PARITY_PEFLAG_PEFPS_Pos \ - (0UL) /*!< SCU_PARITY PEFLAG: PEFPS (Bit 0) */ -#define SCU_PARITY_PEFLAG_PEFPS_Msk \ - (0x1UL) /*!< SCU_PARITY PEFLAG: PEFPS (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PEFLAG_PEFDS1_Pos \ - (1UL) /*!< SCU_PARITY PEFLAG: PEFDS1 (Bit 1) */ -#define SCU_PARITY_PEFLAG_PEFDS1_Msk \ - (0x2UL) /*!< SCU_PARITY PEFLAG: PEFDS1 (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PEFLAG_PEFU0_Pos \ - (8UL) /*!< SCU_PARITY PEFLAG: PEFU0 (Bit 8) */ -#define SCU_PARITY_PEFLAG_PEFU0_Msk \ - (0x100UL) /*!< SCU_PARITY PEFLAG: PEFU0 (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PEFLAG_PEFU1_Pos \ - (9UL) /*!< SCU_PARITY PEFLAG: PEFU1 (Bit 9) */ -#define SCU_PARITY_PEFLAG_PEFU1_Msk \ - (0x200UL) /*!< SCU_PARITY PEFLAG: PEFU1 (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PEFLAG_PEFMC_Pos \ - (12UL) /*!< SCU_PARITY PEFLAG: PEFMC (Bit 12) */ -#define SCU_PARITY_PEFLAG_PEFMC_Msk \ - (0x1000UL) /*!< SCU_PARITY PEFLAG: PEFMC (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PEFLAG_PEFPPRF_Pos \ - (13UL) /*!< SCU_PARITY PEFLAG: PEFPPRF (Bit 13) */ -#define SCU_PARITY_PEFLAG_PEFPPRF_Msk \ - (0x2000UL) /*!< SCU_PARITY PEFLAG: PEFPPRF (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PEFLAG_PEUSB_Pos \ - (16UL) /*!< SCU_PARITY PEFLAG: PEUSB (Bit 16) */ -#define SCU_PARITY_PEFLAG_PEUSB_Msk \ - (0x10000UL) /*!< SCU_PARITY PEFLAG: PEUSB (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_PARITY_PMTPR ------------------------------ */ -#define SCU_PARITY_PMTPR_PWR_Pos \ - (0UL) /*!< SCU_PARITY PMTPR: PWR (Bit 0) */ -#define SCU_PARITY_PMTPR_PWR_Msk \ - (0xffUL) /*!< SCU_PARITY PMTPR: PWR (Bitfield-Mask: 0xff) */ -#define SCU_PARITY_PMTPR_PRD_Pos \ - (8UL) /*!< SCU_PARITY PMTPR: PRD (Bit 8) */ -#define SCU_PARITY_PMTPR_PRD_Msk \ - (0xff00UL) /*!< SCU_PARITY PMTPR: PRD (Bitfield-Mask: 0xff) */ - -/* ------------------------------ SCU_PARITY_PMTSR ------------------------------ */ -#define SCU_PARITY_PMTSR_MTENPS_Pos \ - (0UL) /*!< SCU_PARITY PMTSR: MTENPS (Bit 0) */ -#define SCU_PARITY_PMTSR_MTENPS_Msk \ - (0x1UL) /*!< SCU_PARITY PMTSR: MTENPS (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PMTSR_MTENDS1_Pos \ - (1UL) /*!< SCU_PARITY PMTSR: MTENDS1 (Bit 1) */ -#define SCU_PARITY_PMTSR_MTENDS1_Msk \ - (0x2UL) /*!< SCU_PARITY PMTSR: MTENDS1 (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PMTSR_MTEU0_Pos \ - (8UL) /*!< SCU_PARITY PMTSR: MTEU0 (Bit 8) */ -#define SCU_PARITY_PMTSR_MTEU0_Msk \ - (0x100UL) /*!< SCU_PARITY PMTSR: MTEU0 (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PMTSR_MTEU1_Pos \ - (9UL) /*!< SCU_PARITY PMTSR: MTEU1 (Bit 9) */ -#define SCU_PARITY_PMTSR_MTEU1_Msk \ - (0x200UL) /*!< SCU_PARITY PMTSR: MTEU1 (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PMTSR_MTEMC_Pos \ - (12UL) /*!< SCU_PARITY PMTSR: MTEMC (Bit 12) */ -#define SCU_PARITY_PMTSR_MTEMC_Msk \ - (0x1000UL) /*!< SCU_PARITY PMTSR: MTEMC (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PMTSR_MTEPPRF_Pos \ - (13UL) /*!< SCU_PARITY PMTSR: MTEPPRF (Bit 13) */ -#define SCU_PARITY_PMTSR_MTEPPRF_Msk \ - (0x2000UL) /*!< SCU_PARITY PMTSR: MTEPPRF (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PMTSR_MTUSB_Pos \ - (16UL) /*!< SCU_PARITY PMTSR: MTUSB (Bit 16) */ -#define SCU_PARITY_PMTSR_MTUSB_Msk \ - (0x10000UL) /*!< SCU_PARITY PMTSR: MTUSB (Bitfield-Mask: 0x01) */ - -/* ================================================================================ */ -/* ================ struct 'SCU_TRAP' Position & Mask ================ */ -/* ================================================================================ */ - -/* ------------------------------ SCU_TRAP_TRAPSTAT ----------------------------- */ -#define SCU_TRAP_TRAPSTAT_SOSCWDGT_Pos \ - (0UL) /*!< SCU_TRAP TRAPSTAT: SOSCWDGT (Bit 0) */ -#define SCU_TRAP_TRAPSTAT_SOSCWDGT_Msk \ - (0x1UL) /*!< SCU_TRAP TRAPSTAT: SOSCWDGT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPSTAT_SVCOLCKT_Pos \ - (2UL) /*!< SCU_TRAP TRAPSTAT: SVCOLCKT (Bit 2) */ -#define SCU_TRAP_TRAPSTAT_SVCOLCKT_Msk \ - (0x4UL) /*!< SCU_TRAP TRAPSTAT: SVCOLCKT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPSTAT_UVCOLCKT_Pos \ - (3UL) /*!< SCU_TRAP TRAPSTAT: UVCOLCKT (Bit 3) */ -#define SCU_TRAP_TRAPSTAT_UVCOLCKT_Msk \ - (0x8UL) /*!< SCU_TRAP TRAPSTAT: UVCOLCKT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPSTAT_PET_Pos \ - (4UL) /*!< SCU_TRAP TRAPSTAT: PET (Bit 4) */ -#define SCU_TRAP_TRAPSTAT_PET_Msk \ - (0x10UL) /*!< SCU_TRAP TRAPSTAT: PET (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPSTAT_BRWNT_Pos \ - (5UL) /*!< SCU_TRAP TRAPSTAT: BRWNT (Bit 5) */ -#define SCU_TRAP_TRAPSTAT_BRWNT_Msk \ - (0x20UL) /*!< SCU_TRAP TRAPSTAT: BRWNT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPSTAT_ULPWDGT_Pos \ - (6UL) /*!< SCU_TRAP TRAPSTAT: ULPWDGT (Bit 6) */ -#define SCU_TRAP_TRAPSTAT_ULPWDGT_Msk \ - (0x40UL) /*!< SCU_TRAP TRAPSTAT: ULPWDGT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPSTAT_BWERR0T_Pos \ - (7UL) /*!< SCU_TRAP TRAPSTAT: BWERR0T (Bit 7) */ -#define SCU_TRAP_TRAPSTAT_BWERR0T_Msk \ - (0x80UL) /*!< SCU_TRAP TRAPSTAT: BWERR0T (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPSTAT_BWERR1T_Pos \ - (8UL) /*!< SCU_TRAP TRAPSTAT: BWERR1T (Bit 8) */ -#define SCU_TRAP_TRAPSTAT_BWERR1T_Msk \ - (0x100UL) /*!< SCU_TRAP TRAPSTAT: BWERR1T (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPSTAT_TEMPHIT_Pos \ - (12UL) /*!< SCU_TRAP TRAPSTAT: TEMPHIT (Bit 12) */ -#define SCU_TRAP_TRAPSTAT_TEMPHIT_Msk \ - (0x1000UL) /*!< SCU_TRAP TRAPSTAT: TEMPHIT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPSTAT_TEMPLOT_Pos \ - (13UL) /*!< SCU_TRAP TRAPSTAT: TEMPLOT (Bit 13) */ -#define SCU_TRAP_TRAPSTAT_TEMPLOT_Msk \ - (0x2000UL) /*!< SCU_TRAP TRAPSTAT: TEMPLOT (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_TRAP_TRAPRAW ------------------------------ */ -#define SCU_TRAP_TRAPRAW_SOSCWDGT_Pos \ - (0UL) /*!< SCU_TRAP TRAPRAW: SOSCWDGT (Bit 0) */ -#define SCU_TRAP_TRAPRAW_SOSCWDGT_Msk \ - (0x1UL) /*!< SCU_TRAP TRAPRAW: SOSCWDGT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPRAW_SVCOLCKT_Pos \ - (2UL) /*!< SCU_TRAP TRAPRAW: SVCOLCKT (Bit 2) */ -#define SCU_TRAP_TRAPRAW_SVCOLCKT_Msk \ - (0x4UL) /*!< SCU_TRAP TRAPRAW: SVCOLCKT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPRAW_UVCOLCKT_Pos \ - (3UL) /*!< SCU_TRAP TRAPRAW: UVCOLCKT (Bit 3) */ -#define SCU_TRAP_TRAPRAW_UVCOLCKT_Msk \ - (0x8UL) /*!< SCU_TRAP TRAPRAW: UVCOLCKT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPRAW_PET_Pos \ - (4UL) /*!< SCU_TRAP TRAPRAW: PET (Bit 4) */ -#define SCU_TRAP_TRAPRAW_PET_Msk \ - (0x10UL) /*!< SCU_TRAP TRAPRAW: PET (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPRAW_BRWNT_Pos \ - (5UL) /*!< SCU_TRAP TRAPRAW: BRWNT (Bit 5) */ -#define SCU_TRAP_TRAPRAW_BRWNT_Msk \ - (0x20UL) /*!< SCU_TRAP TRAPRAW: BRWNT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPRAW_ULPWDGT_Pos \ - (6UL) /*!< SCU_TRAP TRAPRAW: ULPWDGT (Bit 6) */ -#define SCU_TRAP_TRAPRAW_ULPWDGT_Msk \ - (0x40UL) /*!< SCU_TRAP TRAPRAW: ULPWDGT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPRAW_BWERR0T_Pos \ - (7UL) /*!< SCU_TRAP TRAPRAW: BWERR0T (Bit 7) */ -#define SCU_TRAP_TRAPRAW_BWERR0T_Msk \ - (0x80UL) /*!< SCU_TRAP TRAPRAW: BWERR0T (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPRAW_BWERR1T_Pos \ - (8UL) /*!< SCU_TRAP TRAPRAW: BWERR1T (Bit 8) */ -#define SCU_TRAP_TRAPRAW_BWERR1T_Msk \ - (0x100UL) /*!< SCU_TRAP TRAPRAW: BWERR1T (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPRAW_TEMPHIT_Pos \ - (12UL) /*!< SCU_TRAP TRAPRAW: TEMPHIT (Bit 12) */ -#define SCU_TRAP_TRAPRAW_TEMPHIT_Msk \ - (0x1000UL) /*!< SCU_TRAP TRAPRAW: TEMPHIT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPRAW_TEMPLOT_Pos \ - (13UL) /*!< SCU_TRAP TRAPRAW: TEMPLOT (Bit 13) */ -#define SCU_TRAP_TRAPRAW_TEMPLOT_Msk \ - (0x2000UL) /*!< SCU_TRAP TRAPRAW: TEMPLOT (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_TRAP_TRAPDIS ------------------------------ */ -#define SCU_TRAP_TRAPDIS_SOSCWDGT_Pos \ - (0UL) /*!< SCU_TRAP TRAPDIS: SOSCWDGT (Bit 0) */ -#define SCU_TRAP_TRAPDIS_SOSCWDGT_Msk \ - (0x1UL) /*!< SCU_TRAP TRAPDIS: SOSCWDGT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPDIS_SVCOLCKT_Pos \ - (2UL) /*!< SCU_TRAP TRAPDIS: SVCOLCKT (Bit 2) */ -#define SCU_TRAP_TRAPDIS_SVCOLCKT_Msk \ - (0x4UL) /*!< SCU_TRAP TRAPDIS: SVCOLCKT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPDIS_UVCOLCKT_Pos \ - (3UL) /*!< SCU_TRAP TRAPDIS: UVCOLCKT (Bit 3) */ -#define SCU_TRAP_TRAPDIS_UVCOLCKT_Msk \ - (0x8UL) /*!< SCU_TRAP TRAPDIS: UVCOLCKT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPDIS_PET_Pos \ - (4UL) /*!< SCU_TRAP TRAPDIS: PET (Bit 4) */ -#define SCU_TRAP_TRAPDIS_PET_Msk \ - (0x10UL) /*!< SCU_TRAP TRAPDIS: PET (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPDIS_BRWNT_Pos \ - (5UL) /*!< SCU_TRAP TRAPDIS: BRWNT (Bit 5) */ -#define SCU_TRAP_TRAPDIS_BRWNT_Msk \ - (0x20UL) /*!< SCU_TRAP TRAPDIS: BRWNT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPDIS_ULPWDGT_Pos \ - (6UL) /*!< SCU_TRAP TRAPDIS: ULPWDGT (Bit 6) */ -#define SCU_TRAP_TRAPDIS_ULPWDGT_Msk \ - (0x40UL) /*!< SCU_TRAP TRAPDIS: ULPWDGT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPDIS_BWERR0T_Pos \ - (7UL) /*!< SCU_TRAP TRAPDIS: BWERR0T (Bit 7) */ -#define SCU_TRAP_TRAPDIS_BWERR0T_Msk \ - (0x80UL) /*!< SCU_TRAP TRAPDIS: BWERR0T (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPDIS_BWERR1T_Pos \ - (8UL) /*!< SCU_TRAP TRAPDIS: BWERR1T (Bit 8) */ -#define SCU_TRAP_TRAPDIS_BWERR1T_Msk \ - (0x100UL) /*!< SCU_TRAP TRAPDIS: BWERR1T (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPDIS_TEMPHIT_Pos \ - (12UL) /*!< SCU_TRAP TRAPDIS: TEMPHIT (Bit 12) */ -#define SCU_TRAP_TRAPDIS_TEMPHIT_Msk \ - (0x1000UL) /*!< SCU_TRAP TRAPDIS: TEMPHIT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPDIS_TEMPLOT_Pos \ - (13UL) /*!< SCU_TRAP TRAPDIS: TEMPLOT (Bit 13) */ -#define SCU_TRAP_TRAPDIS_TEMPLOT_Msk \ - (0x2000UL) /*!< SCU_TRAP TRAPDIS: TEMPLOT (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_TRAP_TRAPCLR ------------------------------ */ -#define SCU_TRAP_TRAPCLR_SOSCWDGT_Pos \ - (0UL) /*!< SCU_TRAP TRAPCLR: SOSCWDGT (Bit 0) */ -#define SCU_TRAP_TRAPCLR_SOSCWDGT_Msk \ - (0x1UL) /*!< SCU_TRAP TRAPCLR: SOSCWDGT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPCLR_SVCOLCKT_Pos \ - (2UL) /*!< SCU_TRAP TRAPCLR: SVCOLCKT (Bit 2) */ -#define SCU_TRAP_TRAPCLR_SVCOLCKT_Msk \ - (0x4UL) /*!< SCU_TRAP TRAPCLR: SVCOLCKT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPCLR_UVCOLCKT_Pos \ - (3UL) /*!< SCU_TRAP TRAPCLR: UVCOLCKT (Bit 3) */ -#define SCU_TRAP_TRAPCLR_UVCOLCKT_Msk \ - (0x8UL) /*!< SCU_TRAP TRAPCLR: UVCOLCKT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPCLR_PET_Pos \ - (4UL) /*!< SCU_TRAP TRAPCLR: PET (Bit 4) */ -#define SCU_TRAP_TRAPCLR_PET_Msk \ - (0x10UL) /*!< SCU_TRAP TRAPCLR: PET (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPCLR_BRWNT_Pos \ - (5UL) /*!< SCU_TRAP TRAPCLR: BRWNT (Bit 5) */ -#define SCU_TRAP_TRAPCLR_BRWNT_Msk \ - (0x20UL) /*!< SCU_TRAP TRAPCLR: BRWNT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPCLR_ULPWDGT_Pos \ - (6UL) /*!< SCU_TRAP TRAPCLR: ULPWDGT (Bit 6) */ -#define SCU_TRAP_TRAPCLR_ULPWDGT_Msk \ - (0x40UL) /*!< SCU_TRAP TRAPCLR: ULPWDGT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPCLR_BWERR0T_Pos \ - (7UL) /*!< SCU_TRAP TRAPCLR: BWERR0T (Bit 7) */ -#define SCU_TRAP_TRAPCLR_BWERR0T_Msk \ - (0x80UL) /*!< SCU_TRAP TRAPCLR: BWERR0T (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPCLR_BWERR1T_Pos \ - (8UL) /*!< SCU_TRAP TRAPCLR: BWERR1T (Bit 8) */ -#define SCU_TRAP_TRAPCLR_BWERR1T_Msk \ - (0x100UL) /*!< SCU_TRAP TRAPCLR: BWERR1T (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPCLR_TEMPHIT_Pos \ - (12UL) /*!< SCU_TRAP TRAPCLR: TEMPHIT (Bit 12) */ -#define SCU_TRAP_TRAPCLR_TEMPHIT_Msk \ - (0x1000UL) /*!< SCU_TRAP TRAPCLR: TEMPHIT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPCLR_TEMPLOT_Pos \ - (13UL) /*!< SCU_TRAP TRAPCLR: TEMPLOT (Bit 13) */ -#define SCU_TRAP_TRAPCLR_TEMPLOT_Msk \ - (0x2000UL) /*!< SCU_TRAP TRAPCLR: TEMPLOT (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_TRAP_TRAPSET ------------------------------ */ -#define SCU_TRAP_TRAPSET_SOSCWDGT_Pos \ - (0UL) /*!< SCU_TRAP TRAPSET: SOSCWDGT (Bit 0) */ -#define SCU_TRAP_TRAPSET_SOSCWDGT_Msk \ - (0x1UL) /*!< SCU_TRAP TRAPSET: SOSCWDGT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPSET_SVCOLCKT_Pos \ - (2UL) /*!< SCU_TRAP TRAPSET: SVCOLCKT (Bit 2) */ -#define SCU_TRAP_TRAPSET_SVCOLCKT_Msk \ - (0x4UL) /*!< SCU_TRAP TRAPSET: SVCOLCKT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPSET_UVCOLCKT_Pos \ - (3UL) /*!< SCU_TRAP TRAPSET: UVCOLCKT (Bit 3) */ -#define SCU_TRAP_TRAPSET_UVCOLCKT_Msk \ - (0x8UL) /*!< SCU_TRAP TRAPSET: UVCOLCKT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPSET_PET_Pos \ - (4UL) /*!< SCU_TRAP TRAPSET: PET (Bit 4) */ -#define SCU_TRAP_TRAPSET_PET_Msk \ - (0x10UL) /*!< SCU_TRAP TRAPSET: PET (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPSET_BRWNT_Pos \ - (5UL) /*!< SCU_TRAP TRAPSET: BRWNT (Bit 5) */ -#define SCU_TRAP_TRAPSET_BRWNT_Msk \ - (0x20UL) /*!< SCU_TRAP TRAPSET: BRWNT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPSET_ULPWDT_Pos \ - (6UL) /*!< SCU_TRAP TRAPSET: ULPWDT (Bit 6) */ -#define SCU_TRAP_TRAPSET_ULPWDT_Msk \ - (0x40UL) /*!< SCU_TRAP TRAPSET: ULPWDT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPSET_BWERR0T_Pos \ - (7UL) /*!< SCU_TRAP TRAPSET: BWERR0T (Bit 7) */ -#define SCU_TRAP_TRAPSET_BWERR0T_Msk \ - (0x80UL) /*!< SCU_TRAP TRAPSET: BWERR0T (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPSET_BWERR1T_Pos \ - (8UL) /*!< SCU_TRAP TRAPSET: BWERR1T (Bit 8) */ -#define SCU_TRAP_TRAPSET_BWERR1T_Msk \ - (0x100UL) /*!< SCU_TRAP TRAPSET: BWERR1T (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPSET_TEMPHIT_Pos \ - (12UL) /*!< SCU_TRAP TRAPSET: TEMPHIT (Bit 12) */ -#define SCU_TRAP_TRAPSET_TEMPHIT_Msk \ - (0x1000UL) /*!< SCU_TRAP TRAPSET: TEMPHIT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPSET_TEMPLOT_Pos \ - (13UL) /*!< SCU_TRAP TRAPSET: TEMPLOT (Bit 13) */ -#define SCU_TRAP_TRAPSET_TEMPLOT_Msk \ - (0x2000UL) /*!< SCU_TRAP TRAPSET: TEMPLOT (Bitfield-Mask: 0x01) */ - -/* ================================================================================ */ -/* ================ struct 'SCU_HIBERNATE' Position & Mask ================ */ -/* ================================================================================ */ - -/* ---------------------------- SCU_HIBERNATE_HDSTAT ---------------------------- */ -#define SCU_HIBERNATE_HDSTAT_EPEV_Pos \ - (0UL) /*!< SCU_HIBERNATE HDSTAT: EPEV (Bit 0) */ -#define SCU_HIBERNATE_HDSTAT_EPEV_Msk \ - (0x1UL) /*!< SCU_HIBERNATE HDSTAT: EPEV (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDSTAT_ENEV_Pos \ - (1UL) /*!< SCU_HIBERNATE HDSTAT: ENEV (Bit 1) */ -#define SCU_HIBERNATE_HDSTAT_ENEV_Msk \ - (0x2UL) /*!< SCU_HIBERNATE HDSTAT: ENEV (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDSTAT_RTCEV_Pos \ - (2UL) /*!< SCU_HIBERNATE HDSTAT: RTCEV (Bit 2) */ -#define SCU_HIBERNATE_HDSTAT_RTCEV_Msk \ - (0x4UL) /*!< SCU_HIBERNATE HDSTAT: RTCEV (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDSTAT_ULPWDG_Pos \ - (3UL) /*!< SCU_HIBERNATE HDSTAT: ULPWDG (Bit 3) */ -#define SCU_HIBERNATE_HDSTAT_ULPWDG_Msk \ - (0x8UL) /*!< SCU_HIBERNATE HDSTAT: ULPWDG (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDSTAT_HIBNOUT_Pos \ - (4UL) /*!< SCU_HIBERNATE HDSTAT: HIBNOUT (Bit 4) */ -#define SCU_HIBERNATE_HDSTAT_HIBNOUT_Msk \ - (0x10UL) /*!< SCU_HIBERNATE HDSTAT: HIBNOUT (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDSTAT_VBATPEV_Pos \ - (8UL) /*!< SCU_HIBERNATE HDSTAT: VBATPEV (Bit 8) */ -#define SCU_HIBERNATE_HDSTAT_VBATPEV_Msk \ - (0x100UL) /*!< SCU_HIBERNATE HDSTAT: VBATPEV (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDSTAT_VBATNEV_Pos \ - (9UL) /*!< SCU_HIBERNATE HDSTAT: VBATNEV (Bit 9) */ -#define SCU_HIBERNATE_HDSTAT_VBATNEV_Msk \ - (0x200UL) /*!< SCU_HIBERNATE HDSTAT: VBATNEV (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDSTAT_AHIBIO0PEV_Pos \ - (10UL) /*!< SCU_HIBERNATE HDSTAT: AHIBIO0PEV (Bit 10) */ -#define SCU_HIBERNATE_HDSTAT_AHIBIO0PEV_Msk \ - (0x400UL) /*!< SCU_HIBERNATE HDSTAT: AHIBIO0PEV (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDSTAT_AHIBIO0NEV_Pos \ - (11UL) /*!< SCU_HIBERNATE HDSTAT: AHIBIO0NEV (Bit 11) */ -#define SCU_HIBERNATE_HDSTAT_AHIBIO0NEV_Msk \ - (0x800UL) /*!< SCU_HIBERNATE HDSTAT: AHIBIO0NEV (Bitfield-Mask: 0x01) */ - -/* ----------------------------- SCU_HIBERNATE_HDCLR ---------------------------- */ -#define SCU_HIBERNATE_HDCLR_EPEV_Pos \ - (0UL) /*!< SCU_HIBERNATE HDCLR: EPEV (Bit 0) */ -#define SCU_HIBERNATE_HDCLR_EPEV_Msk \ - (0x1UL) /*!< SCU_HIBERNATE HDCLR: EPEV (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDCLR_ENEV_Pos \ - (1UL) /*!< SCU_HIBERNATE HDCLR: ENEV (Bit 1) */ -#define SCU_HIBERNATE_HDCLR_ENEV_Msk \ - (0x2UL) /*!< SCU_HIBERNATE HDCLR: ENEV (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDCLR_RTCEV_Pos \ - (2UL) /*!< SCU_HIBERNATE HDCLR: RTCEV (Bit 2) */ -#define SCU_HIBERNATE_HDCLR_RTCEV_Msk \ - (0x4UL) /*!< SCU_HIBERNATE HDCLR: RTCEV (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDCLR_ULPWDG_Pos \ - (3UL) /*!< SCU_HIBERNATE HDCLR: ULPWDG (Bit 3) */ -#define SCU_HIBERNATE_HDCLR_ULPWDG_Msk \ - (0x8UL) /*!< SCU_HIBERNATE HDCLR: ULPWDG (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDCLR_VBATPEV_Pos \ - (8UL) /*!< SCU_HIBERNATE HDCLR: VBATPEV (Bit 8) */ -#define SCU_HIBERNATE_HDCLR_VBATPEV_Msk \ - (0x100UL) /*!< SCU_HIBERNATE HDCLR: VBATPEV (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDCLR_VBATNEV_Pos \ - (9UL) /*!< SCU_HIBERNATE HDCLR: VBATNEV (Bit 9) */ -#define SCU_HIBERNATE_HDCLR_VBATNEV_Msk \ - (0x200UL) /*!< SCU_HIBERNATE HDCLR: VBATNEV (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDCLR_AHIBIO0PEV_Pos \ - (10UL) /*!< SCU_HIBERNATE HDCLR: AHIBIO0PEV (Bit 10) */ -#define SCU_HIBERNATE_HDCLR_AHIBIO0PEV_Msk \ - (0x400UL) /*!< SCU_HIBERNATE HDCLR: AHIBIO0PEV (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDCLR_AHIBIO0NEV_Pos \ - (11UL) /*!< SCU_HIBERNATE HDCLR: AHIBIO0NEV (Bit 11) */ -#define SCU_HIBERNATE_HDCLR_AHIBIO0NEV_Msk \ - (0x800UL) /*!< SCU_HIBERNATE HDCLR: AHIBIO0NEV (Bitfield-Mask: 0x01) */ - -/* ----------------------------- SCU_HIBERNATE_HDSET ---------------------------- */ -#define SCU_HIBERNATE_HDSET_EPEV_Pos \ - (0UL) /*!< SCU_HIBERNATE HDSET: EPEV (Bit 0) */ -#define SCU_HIBERNATE_HDSET_EPEV_Msk \ - (0x1UL) /*!< SCU_HIBERNATE HDSET: EPEV (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDSET_ENEV_Pos \ - (1UL) /*!< SCU_HIBERNATE HDSET: ENEV (Bit 1) */ -#define SCU_HIBERNATE_HDSET_ENEV_Msk \ - (0x2UL) /*!< SCU_HIBERNATE HDSET: ENEV (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDSET_RTCEV_Pos \ - (2UL) /*!< SCU_HIBERNATE HDSET: RTCEV (Bit 2) */ -#define SCU_HIBERNATE_HDSET_RTCEV_Msk \ - (0x4UL) /*!< SCU_HIBERNATE HDSET: RTCEV (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDSET_ULPWDG_Pos \ - (3UL) /*!< SCU_HIBERNATE HDSET: ULPWDG (Bit 3) */ -#define SCU_HIBERNATE_HDSET_ULPWDG_Msk \ - (0x8UL) /*!< SCU_HIBERNATE HDSET: ULPWDG (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDSET_VBATPEV_Pos \ - (8UL) /*!< SCU_HIBERNATE HDSET: VBATPEV (Bit 8) */ -#define SCU_HIBERNATE_HDSET_VBATPEV_Msk \ - (0x100UL) /*!< SCU_HIBERNATE HDSET: VBATPEV (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDSET_VBATNEV_Pos \ - (9UL) /*!< SCU_HIBERNATE HDSET: VBATNEV (Bit 9) */ -#define SCU_HIBERNATE_HDSET_VBATNEV_Msk \ - (0x200UL) /*!< SCU_HIBERNATE HDSET: VBATNEV (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDSET_AHIBIO0PEV_Pos \ - (10UL) /*!< SCU_HIBERNATE HDSET: AHIBIO0PEV (Bit 10) */ -#define SCU_HIBERNATE_HDSET_AHIBIO0PEV_Msk \ - (0x400UL) /*!< SCU_HIBERNATE HDSET: AHIBIO0PEV (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDSET_AHIBIO0NEV_Pos \ - (11UL) /*!< SCU_HIBERNATE HDSET: AHIBIO0NEV (Bit 11) */ -#define SCU_HIBERNATE_HDSET_AHIBIO0NEV_Msk \ - (0x800UL) /*!< SCU_HIBERNATE HDSET: AHIBIO0NEV (Bitfield-Mask: 0x01) */ - -/* ----------------------------- SCU_HIBERNATE_HDCR ----------------------------- */ -#define SCU_HIBERNATE_HDCR_WKPEP_Pos \ - (0UL) /*!< SCU_HIBERNATE HDCR: WKPEP (Bit 0) */ -#define SCU_HIBERNATE_HDCR_WKPEP_Msk \ - (0x1UL) /*!< SCU_HIBERNATE HDCR: WKPEP (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDCR_WKPEN_Pos \ - (1UL) /*!< SCU_HIBERNATE HDCR: WKPEN (Bit 1) */ -#define SCU_HIBERNATE_HDCR_WKPEN_Msk \ - (0x2UL) /*!< SCU_HIBERNATE HDCR: WKPEN (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDCR_RTCE_Pos \ - (2UL) /*!< SCU_HIBERNATE HDCR: RTCE (Bit 2) */ -#define SCU_HIBERNATE_HDCR_RTCE_Msk \ - (0x4UL) /*!< SCU_HIBERNATE HDCR: RTCE (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDCR_ULPWDGEN_Pos \ - (3UL) /*!< SCU_HIBERNATE HDCR: ULPWDGEN (Bit 3) */ -#define SCU_HIBERNATE_HDCR_ULPWDGEN_Msk \ - (0x8UL) /*!< SCU_HIBERNATE HDCR: ULPWDGEN (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDCR_HIB_Pos \ - (4UL) /*!< SCU_HIBERNATE HDCR: HIB (Bit 4) */ -#define SCU_HIBERNATE_HDCR_HIB_Msk \ - (0x10UL) /*!< SCU_HIBERNATE HDCR: HIB (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDCR_XTALGPI1SEL_Pos \ - (5UL) /*!< SCU_HIBERNATE HDCR: XTALGPI1SEL (Bit 5) */ -#define SCU_HIBERNATE_HDCR_XTALGPI1SEL_Msk \ - (0x20UL) /*!< SCU_HIBERNATE HDCR: XTALGPI1SEL (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDCR_RCS_Pos \ - (6UL) /*!< SCU_HIBERNATE HDCR: RCS (Bit 6) */ -#define SCU_HIBERNATE_HDCR_RCS_Msk \ - (0x40UL) /*!< SCU_HIBERNATE HDCR: RCS (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDCR_STDBYSEL_Pos \ - (7UL) /*!< SCU_HIBERNATE HDCR: STDBYSEL (Bit 7) */ -#define SCU_HIBERNATE_HDCR_STDBYSEL_Msk \ - (0x80UL) /*!< SCU_HIBERNATE HDCR: STDBYSEL (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDCR_WKUPSEL_Pos \ - (8UL) /*!< SCU_HIBERNATE HDCR: WKUPSEL (Bit 8) */ -#define SCU_HIBERNATE_HDCR_WKUPSEL_Msk \ - (0x100UL) /*!< SCU_HIBERNATE HDCR: WKUPSEL (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDCR_GPI0SEL_Pos \ - (10UL) /*!< SCU_HIBERNATE HDCR: GPI0SEL (Bit 10) */ -#define SCU_HIBERNATE_HDCR_GPI0SEL_Msk \ - (0x400UL) /*!< SCU_HIBERNATE HDCR: GPI0SEL (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDCR_HIBIO0POL_Pos \ - (12UL) /*!< SCU_HIBERNATE HDCR: HIBIO0POL (Bit 12) */ -#define SCU_HIBERNATE_HDCR_HIBIO0POL_Msk \ - (0x1000UL) /*!< SCU_HIBERNATE HDCR: HIBIO0POL (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDCR_ADIG0SEL_Pos \ - (14UL) /*!< SCU_HIBERNATE HDCR: ADIG0SEL (Bit 14) */ -#define SCU_HIBERNATE_HDCR_ADIG0SEL_Msk \ - (0x4000UL) /*!< SCU_HIBERNATE HDCR: ADIG0SEL (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDCR_HIBIO0SEL_Pos \ - (16UL) /*!< SCU_HIBERNATE HDCR: HIBIO0SEL (Bit 16) */ -#define SCU_HIBERNATE_HDCR_HIBIO0SEL_Msk \ - (0xf0000UL) /*!< SCU_HIBERNATE HDCR: HIBIO0SEL (Bitfield-Mask: 0x0f) */ -#define SCU_HIBERNATE_HDCR_VBATLO_Pos \ - (24UL) /*!< SCU_HIBERNATE HDCR: VBATLO (Bit 24) */ -#define SCU_HIBERNATE_HDCR_VBATLO_Msk \ - (0x1000000UL) /*!< SCU_HIBERNATE HDCR: VBATLO (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDCR_VBATHI_Pos \ - (25UL) /*!< SCU_HIBERNATE HDCR: VBATHI (Bit 25) */ -#define SCU_HIBERNATE_HDCR_VBATHI_Msk \ - (0x2000000UL) /*!< SCU_HIBERNATE HDCR: VBATHI (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDCR_AHIBIO0LO_Pos \ - (26UL) /*!< SCU_HIBERNATE HDCR: AHIBIO0LO (Bit 26) */ -#define SCU_HIBERNATE_HDCR_AHIBIO0LO_Msk \ - (0x4000000UL) /*!< SCU_HIBERNATE HDCR: AHIBIO0LO (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDCR_AHIBIO0HI_Pos \ - (27UL) /*!< SCU_HIBERNATE HDCR: AHIBIO0HI (Bit 27) */ -#define SCU_HIBERNATE_HDCR_AHIBIO0HI_Msk \ - (0x8000000UL) /*!< SCU_HIBERNATE HDCR: AHIBIO0HI (Bitfield-Mask: 0x01) */ - -/* --------------------------- SCU_HIBERNATE_OSCSICTRL -------------------------- */ -#define SCU_HIBERNATE_OSCSICTRL_PWD_Pos \ - (0UL) /*!< SCU_HIBERNATE OSCSICTRL: PWD (Bit 0) */ -#define SCU_HIBERNATE_OSCSICTRL_PWD_Msk \ - (0x1UL) /*!< SCU_HIBERNATE OSCSICTRL: PWD (Bitfield-Mask: 0x01) */ - -/* --------------------------- SCU_HIBERNATE_OSCULSTAT -------------------------- */ -#define SCU_HIBERNATE_OSCULSTAT_X1D_Pos \ - (0UL) /*!< SCU_HIBERNATE OSCULSTAT: X1D (Bit 0) */ -#define SCU_HIBERNATE_OSCULSTAT_X1D_Msk \ - (0x1UL) /*!< SCU_HIBERNATE OSCULSTAT: X1D (Bitfield-Mask: 0x01) */ - -/* --------------------------- SCU_HIBERNATE_OSCULCTRL -------------------------- */ -#define SCU_HIBERNATE_OSCULCTRL_X1DEN_Pos \ - (0UL) /*!< SCU_HIBERNATE OSCULCTRL: X1DEN (Bit 0) */ -#define SCU_HIBERNATE_OSCULCTRL_X1DEN_Msk \ - (0x1UL) /*!< SCU_HIBERNATE OSCULCTRL: X1DEN (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_OSCULCTRL_MODE_Pos \ - (4UL) /*!< SCU_HIBERNATE OSCULCTRL: MODE (Bit 4) */ -#define SCU_HIBERNATE_OSCULCTRL_MODE_Msk \ - (0x30UL) /*!< SCU_HIBERNATE OSCULCTRL: MODE (Bitfield-Mask: 0x03) */ - -/* --------------------------- SCU_HIBERNATE_LPACCONF --------------------------- */ -#define SCU_HIBERNATE_LPACCONF_CMPEN_Pos \ - (0UL) /*!< SCU_HIBERNATE LPACCONF: CMPEN (Bit 0) */ -#define SCU_HIBERNATE_LPACCONF_CMPEN_Msk \ - (0x7UL) /*!< SCU_HIBERNATE LPACCONF: CMPEN (Bitfield-Mask: 0x07) */ -#define SCU_HIBERNATE_LPACCONF_TRIGSEL_Pos \ - (4UL) /*!< SCU_HIBERNATE LPACCONF: TRIGSEL (Bit 4) */ -#define SCU_HIBERNATE_LPACCONF_TRIGSEL_Msk \ - (0x70UL) /*!< SCU_HIBERNATE LPACCONF: TRIGSEL (Bitfield-Mask: 0x07) */ -#define SCU_HIBERNATE_LPACCONF_CONVDEL_Pos \ - (12UL) /*!< SCU_HIBERNATE LPACCONF: CONVDEL (Bit 12) */ -#define SCU_HIBERNATE_LPACCONF_CONVDEL_Msk \ - (0x1000UL) /*!< SCU_HIBERNATE LPACCONF: CONVDEL (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_LPACCONF_INTERVCNT_Pos \ - (16UL) /*!< SCU_HIBERNATE LPACCONF: INTERVCNT (Bit 16) */ -#define SCU_HIBERNATE_LPACCONF_INTERVCNT_Msk \ - (0xfff0000UL) /*!< SCU_HIBERNATE LPACCONF: INTERVCNT (Bitfield-Mask: 0xfff) */ -#define SCU_HIBERNATE_LPACCONF_SETTLECNT_Pos \ - (28UL) /*!< SCU_HIBERNATE LPACCONF: SETTLECNT (Bit 28) */ -#define SCU_HIBERNATE_LPACCONF_SETTLECNT_Msk \ - (0xf0000000UL) /*!< SCU_HIBERNATE LPACCONF: SETTLECNT (Bitfield-Mask: 0x0f) */ - -/* ---------------------------- SCU_HIBERNATE_LPACTH0 --------------------------- */ -#define SCU_HIBERNATE_LPACTH0_VBATLO_Pos \ - (0UL) /*!< SCU_HIBERNATE LPACTH0: VBATLO (Bit 0) */ -#define SCU_HIBERNATE_LPACTH0_VBATLO_Msk \ - (0x3fUL) /*!< SCU_HIBERNATE LPACTH0: VBATLO (Bitfield-Mask: 0x3f) */ -#define SCU_HIBERNATE_LPACTH0_VBATHI_Pos \ - (8UL) /*!< SCU_HIBERNATE LPACTH0: VBATHI (Bit 8) */ -#define SCU_HIBERNATE_LPACTH0_VBATHI_Msk \ - (0x3f00UL) /*!< SCU_HIBERNATE LPACTH0: VBATHI (Bitfield-Mask: 0x3f) */ - -/* ---------------------------- SCU_HIBERNATE_LPACTH1 --------------------------- */ -#define SCU_HIBERNATE_LPACTH1_AHIBIO0LO_Pos \ - (0UL) /*!< SCU_HIBERNATE LPACTH1: AHIBIO0LO (Bit 0) */ -#define SCU_HIBERNATE_LPACTH1_AHIBIO0LO_Msk \ - (0x3fUL) /*!< SCU_HIBERNATE LPACTH1: AHIBIO0LO (Bitfield-Mask: 0x3f) */ -#define SCU_HIBERNATE_LPACTH1_AHIBIO0HI_Pos \ - (8UL) /*!< SCU_HIBERNATE LPACTH1: AHIBIO0HI (Bit 8) */ -#define SCU_HIBERNATE_LPACTH1_AHIBIO0HI_Msk \ - (0x3f00UL) /*!< SCU_HIBERNATE LPACTH1: AHIBIO0HI (Bitfield-Mask: 0x3f) */ - -/* ---------------------------- SCU_HIBERNATE_LPACST ---------------------------- */ -#define SCU_HIBERNATE_LPACST_VBATSCMP_Pos \ - (0UL) /*!< SCU_HIBERNATE LPACST: VBATSCMP (Bit 0) */ -#define SCU_HIBERNATE_LPACST_VBATSCMP_Msk \ - (0x1UL) /*!< SCU_HIBERNATE LPACST: VBATSCMP (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_LPACST_AHIBIO0SCMP_Pos \ - (1UL) /*!< SCU_HIBERNATE LPACST: AHIBIO0SCMP (Bit 1) */ -#define SCU_HIBERNATE_LPACST_AHIBIO0SCMP_Msk \ - (0x2UL) /*!< SCU_HIBERNATE LPACST: AHIBIO0SCMP (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_LPACST_VBATVAL_Pos \ - (16UL) /*!< SCU_HIBERNATE LPACST: VBATVAL (Bit 16) */ -#define SCU_HIBERNATE_LPACST_VBATVAL_Msk \ - (0x10000UL) /*!< SCU_HIBERNATE LPACST: VBATVAL (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_LPACST_AHIBIO0VAL_Pos \ - (17UL) /*!< SCU_HIBERNATE LPACST: AHIBIO0VAL (Bit 17) */ -#define SCU_HIBERNATE_LPACST_AHIBIO0VAL_Msk \ - (0x20000UL) /*!< SCU_HIBERNATE LPACST: AHIBIO0VAL (Bitfield-Mask: 0x01) */ - -/* ---------------------------- SCU_HIBERNATE_LPACCLR --------------------------- */ -#define SCU_HIBERNATE_LPACCLR_VBATSCMP_Pos \ - (0UL) /*!< SCU_HIBERNATE LPACCLR: VBATSCMP (Bit 0) */ -#define SCU_HIBERNATE_LPACCLR_VBATSCMP_Msk \ - (0x1UL) /*!< SCU_HIBERNATE LPACCLR: VBATSCMP (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_LPACCLR_AHIBIO0SCMP_Pos \ - (1UL) /*!< SCU_HIBERNATE LPACCLR: AHIBIO0SCMP (Bit 1) */ -#define SCU_HIBERNATE_LPACCLR_AHIBIO0SCMP_Msk \ - (0x2UL) /*!< SCU_HIBERNATE LPACCLR: AHIBIO0SCMP (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_LPACCLR_VBATVAL_Pos \ - (16UL) /*!< SCU_HIBERNATE LPACCLR: VBATVAL (Bit 16) */ -#define SCU_HIBERNATE_LPACCLR_VBATVAL_Msk \ - (0x10000UL) /*!< SCU_HIBERNATE LPACCLR: VBATVAL (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_LPACCLR_AHIBIO0VAL_Pos \ - (17UL) /*!< SCU_HIBERNATE LPACCLR: AHIBIO0VAL (Bit 17) */ -#define SCU_HIBERNATE_LPACCLR_AHIBIO0VAL_Msk \ - (0x20000UL) /*!< SCU_HIBERNATE LPACCLR: AHIBIO0VAL (Bitfield-Mask: 0x01) */ - -/* ---------------------------- SCU_HIBERNATE_LPACSET --------------------------- */ -#define SCU_HIBERNATE_LPACSET_VBATSCMP_Pos \ - (0UL) /*!< SCU_HIBERNATE LPACSET: VBATSCMP (Bit 0) */ -#define SCU_HIBERNATE_LPACSET_VBATSCMP_Msk \ - (0x1UL) /*!< SCU_HIBERNATE LPACSET: VBATSCMP (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_LPACSET_AHIBIO0SCMP_Pos \ - (1UL) /*!< SCU_HIBERNATE LPACSET: AHIBIO0SCMP (Bit 1) */ -#define SCU_HIBERNATE_LPACSET_AHIBIO0SCMP_Msk \ - (0x2UL) /*!< SCU_HIBERNATE LPACSET: AHIBIO0SCMP (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_LPACSET_VBATVAL_Pos \ - (16UL) /*!< SCU_HIBERNATE LPACSET: VBATVAL (Bit 16) */ -#define SCU_HIBERNATE_LPACSET_VBATVAL_Msk \ - (0x10000UL) /*!< SCU_HIBERNATE LPACSET: VBATVAL (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_LPACSET_AHIBIO0VAL_Pos \ - (17UL) /*!< SCU_HIBERNATE LPACSET: AHIBIO0VAL (Bit 17) */ -#define SCU_HIBERNATE_LPACSET_AHIBIO0VAL_Msk \ - (0x20000UL) /*!< SCU_HIBERNATE LPACSET: AHIBIO0VAL (Bitfield-Mask: 0x01) */ - -/* ---------------------------- SCU_HIBERNATE_HINTST ---------------------------- */ -#define SCU_HIBERNATE_HINTST_HIBNINT_Pos \ - (0UL) /*!< SCU_HIBERNATE HINTST: HIBNINT (Bit 0) */ -#define SCU_HIBERNATE_HINTST_HIBNINT_Msk \ - (0x1UL) /*!< SCU_HIBERNATE HINTST: HIBNINT (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HINTST_FLASHOFF_Pos \ - (2UL) /*!< SCU_HIBERNATE HINTST: FLASHOFF (Bit 2) */ -#define SCU_HIBERNATE_HINTST_FLASHOFF_Msk \ - (0x4UL) /*!< SCU_HIBERNATE HINTST: FLASHOFF (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HINTST_FLASHPD_Pos \ - (3UL) /*!< SCU_HIBERNATE HINTST: FLASHPD (Bit 3) */ -#define SCU_HIBERNATE_HINTST_FLASHPD_Msk \ - (0x8UL) /*!< SCU_HIBERNATE HINTST: FLASHPD (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HINTST_POFFD_Pos \ - (4UL) /*!< SCU_HIBERNATE HINTST: POFFD (Bit 4) */ -#define SCU_HIBERNATE_HINTST_POFFD_Msk \ - (0x10UL) /*!< SCU_HIBERNATE HINTST: POFFD (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HINTST_PPODEL_Pos \ - (16UL) /*!< SCU_HIBERNATE HINTST: PPODEL (Bit 16) */ -#define SCU_HIBERNATE_HINTST_PPODEL_Msk \ - (0x30000UL) /*!< SCU_HIBERNATE HINTST: PPODEL (Bitfield-Mask: 0x03) */ -#define SCU_HIBERNATE_HINTST_POFFH_Pos \ - (20UL) /*!< SCU_HIBERNATE HINTST: POFFH (Bit 20) */ -#define SCU_HIBERNATE_HINTST_POFFH_Msk \ - (0x100000UL) /*!< SCU_HIBERNATE HINTST: POFFH (Bitfield-Mask: 0x01) */ - -/* ---------------------------- SCU_HIBERNATE_HINTCLR --------------------------- */ -#define SCU_HIBERNATE_HINTCLR_HIBNINT_Pos \ - (0UL) /*!< SCU_HIBERNATE HINTCLR: HIBNINT (Bit 0) */ -#define SCU_HIBERNATE_HINTCLR_HIBNINT_Msk \ - (0x1UL) /*!< SCU_HIBERNATE HINTCLR: HIBNINT (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HINTCLR_FLASHOFF_Pos \ - (2UL) /*!< SCU_HIBERNATE HINTCLR: FLASHOFF (Bit 2) */ -#define SCU_HIBERNATE_HINTCLR_FLASHOFF_Msk \ - (0x4UL) /*!< SCU_HIBERNATE HINTCLR: FLASHOFF (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HINTCLR_FLASHPD_Pos \ - (3UL) /*!< SCU_HIBERNATE HINTCLR: FLASHPD (Bit 3) */ -#define SCU_HIBERNATE_HINTCLR_FLASHPD_Msk \ - (0x8UL) /*!< SCU_HIBERNATE HINTCLR: FLASHPD (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HINTCLR_POFFD_Pos \ - (4UL) /*!< SCU_HIBERNATE HINTCLR: POFFD (Bit 4) */ -#define SCU_HIBERNATE_HINTCLR_POFFD_Msk \ - (0x10UL) /*!< SCU_HIBERNATE HINTCLR: POFFD (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HINTCLR_PPODEL_Pos \ - (16UL) /*!< SCU_HIBERNATE HINTCLR: PPODEL (Bit 16) */ -#define SCU_HIBERNATE_HINTCLR_PPODEL_Msk \ - (0x30000UL) /*!< SCU_HIBERNATE HINTCLR: PPODEL (Bitfield-Mask: 0x03) */ -#define SCU_HIBERNATE_HINTCLR_POFFH_Pos \ - (20UL) /*!< SCU_HIBERNATE HINTCLR: POFFH (Bit 20) */ -#define SCU_HIBERNATE_HINTCLR_POFFH_Msk \ - (0x100000UL) /*!< SCU_HIBERNATE HINTCLR: POFFH (Bitfield-Mask: 0x01) */ - -/* ---------------------------- SCU_HIBERNATE_HINTSET --------------------------- */ -#define SCU_HIBERNATE_HINTSET_HIBNINT_Pos \ - (0UL) /*!< SCU_HIBERNATE HINTSET: HIBNINT (Bit 0) */ -#define SCU_HIBERNATE_HINTSET_HIBNINT_Msk \ - (0x1UL) /*!< SCU_HIBERNATE HINTSET: HIBNINT (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HINTSET_VCOREOFF_Pos \ - (1UL) /*!< SCU_HIBERNATE HINTSET: VCOREOFF (Bit 1) */ -#define SCU_HIBERNATE_HINTSET_VCOREOFF_Msk \ - (0x2UL) /*!< SCU_HIBERNATE HINTSET: VCOREOFF (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HINTSET_FLASHOFF_Pos \ - (2UL) /*!< SCU_HIBERNATE HINTSET: FLASHOFF (Bit 2) */ -#define SCU_HIBERNATE_HINTSET_FLASHOFF_Msk \ - (0x4UL) /*!< SCU_HIBERNATE HINTSET: FLASHOFF (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HINTSET_FLASHPD_Pos \ - (3UL) /*!< SCU_HIBERNATE HINTSET: FLASHPD (Bit 3) */ -#define SCU_HIBERNATE_HINTSET_FLASHPD_Msk \ - (0x8UL) /*!< SCU_HIBERNATE HINTSET: FLASHPD (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HINTSET_POFFD_Pos \ - (4UL) /*!< SCU_HIBERNATE HINTSET: POFFD (Bit 4) */ -#define SCU_HIBERNATE_HINTSET_POFFD_Msk \ - (0x10UL) /*!< SCU_HIBERNATE HINTSET: POFFD (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HINTSET_PPODEL_Pos \ - (16UL) /*!< SCU_HIBERNATE HINTSET: PPODEL (Bit 16) */ -#define SCU_HIBERNATE_HINTSET_PPODEL_Msk \ - (0x30000UL) /*!< SCU_HIBERNATE HINTSET: PPODEL (Bitfield-Mask: 0x03) */ -#define SCU_HIBERNATE_HINTSET_POFFH_Pos \ - (20UL) /*!< SCU_HIBERNATE HINTSET: POFFH (Bit 20) */ -#define SCU_HIBERNATE_HINTSET_POFFH_Msk \ - (0x100000UL) /*!< SCU_HIBERNATE HINTSET: POFFH (Bitfield-Mask: 0x01) */ - -/* ================================================================================ */ -/* ================ struct 'SCU_POWER' Position & Mask ================ */ -/* ================================================================================ */ - -/* ------------------------------ SCU_POWER_PWRSTAT ----------------------------- */ -#define SCU_POWER_PWRSTAT_HIBEN_Pos \ - (0UL) /*!< SCU_POWER PWRSTAT: HIBEN (Bit 0) */ -#define SCU_POWER_PWRSTAT_HIBEN_Msk \ - (0x1UL) /*!< SCU_POWER PWRSTAT: HIBEN (Bitfield-Mask: 0x01) */ -#define SCU_POWER_PWRSTAT_USBPHYPDQ_Pos \ - (16UL) /*!< SCU_POWER PWRSTAT: USBPHYPDQ (Bit 16) */ -#define SCU_POWER_PWRSTAT_USBPHYPDQ_Msk \ - (0x10000UL) /*!< SCU_POWER PWRSTAT: USBPHYPDQ (Bitfield-Mask: 0x01) */ -#define SCU_POWER_PWRSTAT_USBPUWQ_Pos \ - (18UL) /*!< SCU_POWER PWRSTAT: USBPUWQ (Bit 18) */ -#define SCU_POWER_PWRSTAT_USBPUWQ_Msk \ - (0x40000UL) /*!< SCU_POWER PWRSTAT: USBPUWQ (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_POWER_PWRSET ------------------------------ */ -#define SCU_POWER_PWRSET_HIB_Pos \ - (0UL) /*!< SCU_POWER PWRSET: HIB (Bit 0) */ -#define SCU_POWER_PWRSET_HIB_Msk \ - (0x1UL) /*!< SCU_POWER PWRSET: HIB (Bitfield-Mask: 0x01) */ -#define SCU_POWER_PWRSET_USBPHYPDQ_Pos \ - (16UL) /*!< SCU_POWER PWRSET: USBPHYPDQ (Bit 16) */ -#define SCU_POWER_PWRSET_USBPHYPDQ_Msk \ - (0x10000UL) /*!< SCU_POWER PWRSET: USBPHYPDQ (Bitfield-Mask: 0x01) */ -#define SCU_POWER_PWRSET_USBPUWQ_Pos \ - (18UL) /*!< SCU_POWER PWRSET: USBPUWQ (Bit 18) */ -#define SCU_POWER_PWRSET_USBPUWQ_Msk \ - (0x40000UL) /*!< SCU_POWER PWRSET: USBPUWQ (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_POWER_PWRCLR ------------------------------ */ -#define SCU_POWER_PWRCLR_HIB_Pos \ - (0UL) /*!< SCU_POWER PWRCLR: HIB (Bit 0) */ -#define SCU_POWER_PWRCLR_HIB_Msk \ - (0x1UL) /*!< SCU_POWER PWRCLR: HIB (Bitfield-Mask: 0x01) */ -#define SCU_POWER_PWRCLR_USBPHYPDQ_Pos \ - (16UL) /*!< SCU_POWER PWRCLR: USBPHYPDQ (Bit 16) */ -#define SCU_POWER_PWRCLR_USBPHYPDQ_Msk \ - (0x10000UL) /*!< SCU_POWER PWRCLR: USBPHYPDQ (Bitfield-Mask: 0x01) */ -#define SCU_POWER_PWRCLR_USBPUWQ_Pos \ - (18UL) /*!< SCU_POWER PWRCLR: USBPUWQ (Bit 18) */ -#define SCU_POWER_PWRCLR_USBPUWQ_Msk \ - (0x40000UL) /*!< SCU_POWER PWRCLR: USBPUWQ (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_POWER_EVRSTAT ----------------------------- */ -#define SCU_POWER_EVRSTAT_OV13_Pos \ - (1UL) /*!< SCU_POWER EVRSTAT: OV13 (Bit 1) */ -#define SCU_POWER_EVRSTAT_OV13_Msk \ - (0x2UL) /*!< SCU_POWER EVRSTAT: OV13 (Bitfield-Mask: 0x01) */ - -/* ---------------------------- SCU_POWER_EVRVADCSTAT --------------------------- */ -#define SCU_POWER_EVRVADCSTAT_VADC13V_Pos \ - (0UL) /*!< SCU_POWER EVRVADCSTAT: VADC13V (Bit 0) */ -#define SCU_POWER_EVRVADCSTAT_VADC13V_Msk \ - (0xffUL) /*!< SCU_POWER EVRVADCSTAT: VADC13V (Bitfield-Mask: 0xff) */ -#define SCU_POWER_EVRVADCSTAT_VADC33V_Pos \ - (8UL) /*!< SCU_POWER EVRVADCSTAT: VADC33V (Bit 8) */ -#define SCU_POWER_EVRVADCSTAT_VADC33V_Msk \ - (0xff00UL) /*!< SCU_POWER EVRVADCSTAT: VADC33V (Bitfield-Mask: 0xff) */ - -/* ------------------------------ SCU_POWER_PWRMON ------------------------------ */ -#define SCU_POWER_PWRMON_THRS_Pos \ - (0UL) /*!< SCU_POWER PWRMON: THRS (Bit 0) */ -#define SCU_POWER_PWRMON_THRS_Msk \ - (0xffUL) /*!< SCU_POWER PWRMON: THRS (Bitfield-Mask: 0xff) */ -#define SCU_POWER_PWRMON_INTV_Pos \ - (8UL) /*!< SCU_POWER PWRMON: INTV (Bit 8) */ -#define SCU_POWER_PWRMON_INTV_Msk \ - (0xff00UL) /*!< SCU_POWER PWRMON: INTV (Bitfield-Mask: 0xff) */ -#define SCU_POWER_PWRMON_ENB_Pos \ - (16UL) /*!< SCU_POWER PWRMON: ENB (Bit 16) */ -#define SCU_POWER_PWRMON_ENB_Msk \ - (0x10000UL) /*!< SCU_POWER PWRMON: ENB (Bitfield-Mask: 0x01) */ - -/* ================================================================================ */ -/* ================ struct 'SCU_RESET' Position & Mask ================ */ -/* ================================================================================ */ - -/* ------------------------------ SCU_RESET_RSTSTAT ----------------------------- */ -#define SCU_RESET_RSTSTAT_RSTSTAT_Pos \ - (0UL) /*!< SCU_RESET RSTSTAT: RSTSTAT (Bit 0) */ -#define SCU_RESET_RSTSTAT_RSTSTAT_Msk \ - (0xffUL) /*!< SCU_RESET RSTSTAT: RSTSTAT (Bitfield-Mask: 0xff) */ -#define SCU_RESET_RSTSTAT_HIBWK_Pos \ - (8UL) /*!< SCU_RESET RSTSTAT: HIBWK (Bit 8) */ -#define SCU_RESET_RSTSTAT_HIBWK_Msk \ - (0x100UL) /*!< SCU_RESET RSTSTAT: HIBWK (Bitfield-Mask: 0x01) */ -#define SCU_RESET_RSTSTAT_HIBRS_Pos \ - (9UL) /*!< SCU_RESET RSTSTAT: HIBRS (Bit 9) */ -#define SCU_RESET_RSTSTAT_HIBRS_Msk \ - (0x200UL) /*!< SCU_RESET RSTSTAT: HIBRS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_RSTSTAT_LCKEN_Pos \ - (10UL) /*!< SCU_RESET RSTSTAT: LCKEN (Bit 10) */ -#define SCU_RESET_RSTSTAT_LCKEN_Msk \ - (0x400UL) /*!< SCU_RESET RSTSTAT: LCKEN (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_RESET_RSTSET ------------------------------ */ -#define SCU_RESET_RSTSET_HIBWK_Pos \ - (8UL) /*!< SCU_RESET RSTSET: HIBWK (Bit 8) */ -#define SCU_RESET_RSTSET_HIBWK_Msk \ - (0x100UL) /*!< SCU_RESET RSTSET: HIBWK (Bitfield-Mask: 0x01) */ -#define SCU_RESET_RSTSET_HIBRS_Pos \ - (9UL) /*!< SCU_RESET RSTSET: HIBRS (Bit 9) */ -#define SCU_RESET_RSTSET_HIBRS_Msk \ - (0x200UL) /*!< SCU_RESET RSTSET: HIBRS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_RSTSET_LCKEN_Pos \ - (10UL) /*!< SCU_RESET RSTSET: LCKEN (Bit 10) */ -#define SCU_RESET_RSTSET_LCKEN_Msk \ - (0x400UL) /*!< SCU_RESET RSTSET: LCKEN (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_RESET_RSTCLR ------------------------------ */ -#define SCU_RESET_RSTCLR_RSCLR_Pos \ - (0UL) /*!< SCU_RESET RSTCLR: RSCLR (Bit 0) */ -#define SCU_RESET_RSTCLR_RSCLR_Msk \ - (0x1UL) /*!< SCU_RESET RSTCLR: RSCLR (Bitfield-Mask: 0x01) */ -#define SCU_RESET_RSTCLR_HIBWK_Pos \ - (8UL) /*!< SCU_RESET RSTCLR: HIBWK (Bit 8) */ -#define SCU_RESET_RSTCLR_HIBWK_Msk \ - (0x100UL) /*!< SCU_RESET RSTCLR: HIBWK (Bitfield-Mask: 0x01) */ -#define SCU_RESET_RSTCLR_HIBRS_Pos \ - (9UL) /*!< SCU_RESET RSTCLR: HIBRS (Bit 9) */ -#define SCU_RESET_RSTCLR_HIBRS_Msk \ - (0x200UL) /*!< SCU_RESET RSTCLR: HIBRS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_RSTCLR_LCKEN_Pos \ - (10UL) /*!< SCU_RESET RSTCLR: LCKEN (Bit 10) */ -#define SCU_RESET_RSTCLR_LCKEN_Msk \ - (0x400UL) /*!< SCU_RESET RSTCLR: LCKEN (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_RESET_PRSTAT0 ----------------------------- */ -#define SCU_RESET_PRSTAT0_VADCRS_Pos \ - (0UL) /*!< SCU_RESET PRSTAT0: VADCRS (Bit 0) */ -#define SCU_RESET_PRSTAT0_VADCRS_Msk \ - (0x1UL) /*!< SCU_RESET PRSTAT0: VADCRS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSTAT0_CCU40RS_Pos \ - (2UL) /*!< SCU_RESET PRSTAT0: CCU40RS (Bit 2) */ -#define SCU_RESET_PRSTAT0_CCU40RS_Msk \ - (0x4UL) /*!< SCU_RESET PRSTAT0: CCU40RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSTAT0_CCU41RS_Pos \ - (3UL) /*!< SCU_RESET PRSTAT0: CCU41RS (Bit 3) */ -#define SCU_RESET_PRSTAT0_CCU41RS_Msk \ - (0x8UL) /*!< SCU_RESET PRSTAT0: CCU41RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSTAT0_CCU80RS_Pos \ - (7UL) /*!< SCU_RESET PRSTAT0: CCU80RS (Bit 7) */ -#define SCU_RESET_PRSTAT0_CCU80RS_Msk \ - (0x80UL) /*!< SCU_RESET PRSTAT0: CCU80RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSTAT0_POSIF0RS_Pos \ - (9UL) /*!< SCU_RESET PRSTAT0: POSIF0RS (Bit 9) */ -#define SCU_RESET_PRSTAT0_POSIF0RS_Msk \ - (0x200UL) /*!< SCU_RESET PRSTAT0: POSIF0RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSTAT0_USIC0RS_Pos \ - (11UL) /*!< SCU_RESET PRSTAT0: USIC0RS (Bit 11) */ -#define SCU_RESET_PRSTAT0_USIC0RS_Msk \ - (0x800UL) /*!< SCU_RESET PRSTAT0: USIC0RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSTAT0_ERU1RS_Pos \ - (16UL) /*!< SCU_RESET PRSTAT0: ERU1RS (Bit 16) */ -#define SCU_RESET_PRSTAT0_ERU1RS_Msk \ - (0x10000UL) /*!< SCU_RESET PRSTAT0: ERU1RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSTAT0_HRPWM0RS_Pos \ - (23UL) /*!< SCU_RESET PRSTAT0: HRPWM0RS (Bit 23) */ -#define SCU_RESET_PRSTAT0_HRPWM0RS_Msk \ - (0x800000UL) /*!< SCU_RESET PRSTAT0: HRPWM0RS (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_RESET_PRSET0 ------------------------------ */ -#define SCU_RESET_PRSET0_VADCRS_Pos \ - (0UL) /*!< SCU_RESET PRSET0: VADCRS (Bit 0) */ -#define SCU_RESET_PRSET0_VADCRS_Msk \ - (0x1UL) /*!< SCU_RESET PRSET0: VADCRS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSET0_CCU40RS_Pos \ - (2UL) /*!< SCU_RESET PRSET0: CCU40RS (Bit 2) */ -#define SCU_RESET_PRSET0_CCU40RS_Msk \ - (0x4UL) /*!< SCU_RESET PRSET0: CCU40RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSET0_CCU41RS_Pos \ - (3UL) /*!< SCU_RESET PRSET0: CCU41RS (Bit 3) */ -#define SCU_RESET_PRSET0_CCU41RS_Msk \ - (0x8UL) /*!< SCU_RESET PRSET0: CCU41RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSET0_CCU80RS_Pos \ - (7UL) /*!< SCU_RESET PRSET0: CCU80RS (Bit 7) */ -#define SCU_RESET_PRSET0_CCU80RS_Msk \ - (0x80UL) /*!< SCU_RESET PRSET0: CCU80RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSET0_POSIF0RS_Pos \ - (9UL) /*!< SCU_RESET PRSET0: POSIF0RS (Bit 9) */ -#define SCU_RESET_PRSET0_POSIF0RS_Msk \ - (0x200UL) /*!< SCU_RESET PRSET0: POSIF0RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSET0_USIC0RS_Pos \ - (11UL) /*!< SCU_RESET PRSET0: USIC0RS (Bit 11) */ -#define SCU_RESET_PRSET0_USIC0RS_Msk \ - (0x800UL) /*!< SCU_RESET PRSET0: USIC0RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSET0_ERU1RS_Pos \ - (16UL) /*!< SCU_RESET PRSET0: ERU1RS (Bit 16) */ -#define SCU_RESET_PRSET0_ERU1RS_Msk \ - (0x10000UL) /*!< SCU_RESET PRSET0: ERU1RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSET0_HRPWM0RS_Pos \ - (23UL) /*!< SCU_RESET PRSET0: HRPWM0RS (Bit 23) */ -#define SCU_RESET_PRSET0_HRPWM0RS_Msk \ - (0x800000UL) /*!< SCU_RESET PRSET0: HRPWM0RS (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_RESET_PRCLR0 ------------------------------ */ -#define SCU_RESET_PRCLR0_VADCRS_Pos \ - (0UL) /*!< SCU_RESET PRCLR0: VADCRS (Bit 0) */ -#define SCU_RESET_PRCLR0_VADCRS_Msk \ - (0x1UL) /*!< SCU_RESET PRCLR0: VADCRS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRCLR0_CCU40RS_Pos \ - (2UL) /*!< SCU_RESET PRCLR0: CCU40RS (Bit 2) */ -#define SCU_RESET_PRCLR0_CCU40RS_Msk \ - (0x4UL) /*!< SCU_RESET PRCLR0: CCU40RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRCLR0_CCU41RS_Pos \ - (3UL) /*!< SCU_RESET PRCLR0: CCU41RS (Bit 3) */ -#define SCU_RESET_PRCLR0_CCU41RS_Msk \ - (0x8UL) /*!< SCU_RESET PRCLR0: CCU41RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRCLR0_CCU80RS_Pos \ - (7UL) /*!< SCU_RESET PRCLR0: CCU80RS (Bit 7) */ -#define SCU_RESET_PRCLR0_CCU80RS_Msk \ - (0x80UL) /*!< SCU_RESET PRCLR0: CCU80RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRCLR0_POSIF0RS_Pos \ - (9UL) /*!< SCU_RESET PRCLR0: POSIF0RS (Bit 9) */ -#define SCU_RESET_PRCLR0_POSIF0RS_Msk \ - (0x200UL) /*!< SCU_RESET PRCLR0: POSIF0RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRCLR0_USIC0RS_Pos \ - (11UL) /*!< SCU_RESET PRCLR0: USIC0RS (Bit 11) */ -#define SCU_RESET_PRCLR0_USIC0RS_Msk \ - (0x800UL) /*!< SCU_RESET PRCLR0: USIC0RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRCLR0_ERU1RS_Pos \ - (16UL) /*!< SCU_RESET PRCLR0: ERU1RS (Bit 16) */ -#define SCU_RESET_PRCLR0_ERU1RS_Msk \ - (0x10000UL) /*!< SCU_RESET PRCLR0: ERU1RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRCLR0_HRPWM0RS_Pos \ - (23UL) /*!< SCU_RESET PRCLR0: HRPWM0RS (Bit 23) */ -#define SCU_RESET_PRCLR0_HRPWM0RS_Msk \ - (0x800000UL) /*!< SCU_RESET PRCLR0: HRPWM0RS (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_RESET_PRSTAT1 ----------------------------- */ -#define SCU_RESET_PRSTAT1_LEDTSCU0RS_Pos \ - (3UL) /*!< SCU_RESET PRSTAT1: LEDTSCU0RS (Bit 3) */ -#define SCU_RESET_PRSTAT1_LEDTSCU0RS_Msk \ - (0x8UL) /*!< SCU_RESET PRSTAT1: LEDTSCU0RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSTAT1_MCAN0RS_Pos \ - (4UL) /*!< SCU_RESET PRSTAT1: MCAN0RS (Bit 4) */ -#define SCU_RESET_PRSTAT1_MCAN0RS_Msk \ - (0x10UL) /*!< SCU_RESET PRSTAT1: MCAN0RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSTAT1_DACRS_Pos \ - (5UL) /*!< SCU_RESET PRSTAT1: DACRS (Bit 5) */ -#define SCU_RESET_PRSTAT1_DACRS_Msk \ - (0x20UL) /*!< SCU_RESET PRSTAT1: DACRS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSTAT1_USIC1RS_Pos \ - (7UL) /*!< SCU_RESET PRSTAT1: USIC1RS (Bit 7) */ -#define SCU_RESET_PRSTAT1_USIC1RS_Msk \ - (0x80UL) /*!< SCU_RESET PRSTAT1: USIC1RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSTAT1_PPORTSRS_Pos \ - (9UL) /*!< SCU_RESET PRSTAT1: PPORTSRS (Bit 9) */ -#define SCU_RESET_PRSTAT1_PPORTSRS_Msk \ - (0x200UL) /*!< SCU_RESET PRSTAT1: PPORTSRS (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_RESET_PRSET1 ------------------------------ */ -#define SCU_RESET_PRSET1_LEDTSCU0RS_Pos \ - (3UL) /*!< SCU_RESET PRSET1: LEDTSCU0RS (Bit 3) */ -#define SCU_RESET_PRSET1_LEDTSCU0RS_Msk \ - (0x8UL) /*!< SCU_RESET PRSET1: LEDTSCU0RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSET1_MCAN0RS_Pos \ - (4UL) /*!< SCU_RESET PRSET1: MCAN0RS (Bit 4) */ -#define SCU_RESET_PRSET1_MCAN0RS_Msk \ - (0x10UL) /*!< SCU_RESET PRSET1: MCAN0RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSET1_DACRS_Pos \ - (5UL) /*!< SCU_RESET PRSET1: DACRS (Bit 5) */ -#define SCU_RESET_PRSET1_DACRS_Msk \ - (0x20UL) /*!< SCU_RESET PRSET1: DACRS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSET1_USIC1RS_Pos \ - (7UL) /*!< SCU_RESET PRSET1: USIC1RS (Bit 7) */ -#define SCU_RESET_PRSET1_USIC1RS_Msk \ - (0x80UL) /*!< SCU_RESET PRSET1: USIC1RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSET1_PPORTSRS_Pos \ - (9UL) /*!< SCU_RESET PRSET1: PPORTSRS (Bit 9) */ -#define SCU_RESET_PRSET1_PPORTSRS_Msk \ - (0x200UL) /*!< SCU_RESET PRSET1: PPORTSRS (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_RESET_PRCLR1 ------------------------------ */ -#define SCU_RESET_PRCLR1_LEDTSCU0RS_Pos \ - (3UL) /*!< SCU_RESET PRCLR1: LEDTSCU0RS (Bit 3) */ -#define SCU_RESET_PRCLR1_LEDTSCU0RS_Msk \ - (0x8UL) /*!< SCU_RESET PRCLR1: LEDTSCU0RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRCLR1_MCAN0RS_Pos \ - (4UL) /*!< SCU_RESET PRCLR1: MCAN0RS (Bit 4) */ -#define SCU_RESET_PRCLR1_MCAN0RS_Msk \ - (0x10UL) /*!< SCU_RESET PRCLR1: MCAN0RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRCLR1_DACRS_Pos \ - (5UL) /*!< SCU_RESET PRCLR1: DACRS (Bit 5) */ -#define SCU_RESET_PRCLR1_DACRS_Msk \ - (0x20UL) /*!< SCU_RESET PRCLR1: DACRS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRCLR1_USIC1RS_Pos \ - (7UL) /*!< SCU_RESET PRCLR1: USIC1RS (Bit 7) */ -#define SCU_RESET_PRCLR1_USIC1RS_Msk \ - (0x80UL) /*!< SCU_RESET PRCLR1: USIC1RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRCLR1_PPORTSRS_Pos \ - (9UL) /*!< SCU_RESET PRCLR1: PPORTSRS (Bit 9) */ -#define SCU_RESET_PRCLR1_PPORTSRS_Msk \ - (0x200UL) /*!< SCU_RESET PRCLR1: PPORTSRS (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_RESET_PRSTAT2 ----------------------------- */ -#define SCU_RESET_PRSTAT2_WDTRS_Pos \ - (1UL) /*!< SCU_RESET PRSTAT2: WDTRS (Bit 1) */ -#define SCU_RESET_PRSTAT2_WDTRS_Msk \ - (0x2UL) /*!< SCU_RESET PRSTAT2: WDTRS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSTAT2_DMA0RS_Pos \ - (4UL) /*!< SCU_RESET PRSTAT2: DMA0RS (Bit 4) */ -#define SCU_RESET_PRSTAT2_DMA0RS_Msk \ - (0x10UL) /*!< SCU_RESET PRSTAT2: DMA0RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSTAT2_FCERS_Pos \ - (6UL) /*!< SCU_RESET PRSTAT2: FCERS (Bit 6) */ -#define SCU_RESET_PRSTAT2_FCERS_Msk \ - (0x40UL) /*!< SCU_RESET PRSTAT2: FCERS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSTAT2_USBRS_Pos \ - (7UL) /*!< SCU_RESET PRSTAT2: USBRS (Bit 7) */ -#define SCU_RESET_PRSTAT2_USBRS_Msk \ - (0x80UL) /*!< SCU_RESET PRSTAT2: USBRS (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_RESET_PRSET2 ------------------------------ */ -#define SCU_RESET_PRSET2_WDTRS_Pos \ - (1UL) /*!< SCU_RESET PRSET2: WDTRS (Bit 1) */ -#define SCU_RESET_PRSET2_WDTRS_Msk \ - (0x2UL) /*!< SCU_RESET PRSET2: WDTRS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSET2_DMA0RS_Pos \ - (4UL) /*!< SCU_RESET PRSET2: DMA0RS (Bit 4) */ -#define SCU_RESET_PRSET2_DMA0RS_Msk \ - (0x10UL) /*!< SCU_RESET PRSET2: DMA0RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSET2_FCERS_Pos \ - (6UL) /*!< SCU_RESET PRSET2: FCERS (Bit 6) */ -#define SCU_RESET_PRSET2_FCERS_Msk \ - (0x40UL) /*!< SCU_RESET PRSET2: FCERS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSET2_USBRS_Pos \ - (7UL) /*!< SCU_RESET PRSET2: USBRS (Bit 7) */ -#define SCU_RESET_PRSET2_USBRS_Msk \ - (0x80UL) /*!< SCU_RESET PRSET2: USBRS (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_RESET_PRCLR2 ------------------------------ */ -#define SCU_RESET_PRCLR2_WDTRS_Pos \ - (1UL) /*!< SCU_RESET PRCLR2: WDTRS (Bit 1) */ -#define SCU_RESET_PRCLR2_WDTRS_Msk \ - (0x2UL) /*!< SCU_RESET PRCLR2: WDTRS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRCLR2_DMA0RS_Pos \ - (4UL) /*!< SCU_RESET PRCLR2: DMA0RS (Bit 4) */ -#define SCU_RESET_PRCLR2_DMA0RS_Msk \ - (0x10UL) /*!< SCU_RESET PRCLR2: DMA0RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRCLR2_FCERS_Pos \ - (6UL) /*!< SCU_RESET PRCLR2: FCERS (Bit 6) */ -#define SCU_RESET_PRCLR2_FCERS_Msk \ - (0x40UL) /*!< SCU_RESET PRCLR2: FCERS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRCLR2_USBRS_Pos \ - (7UL) /*!< SCU_RESET PRCLR2: USBRS (Bit 7) */ -#define SCU_RESET_PRCLR2_USBRS_Msk \ - (0x80UL) /*!< SCU_RESET PRCLR2: USBRS (Bitfield-Mask: 0x01) */ - -/* ================================================================================ */ -/* ================ Group 'LEDTS' Position & Mask ================ */ -/* ================================================================================ */ - -/* ---------------------------------- LEDTS_ID ---------------------------------- */ -#define LEDTS_ID_MOD_REV_Pos \ - (0UL) /*!< LEDTS ID: MOD_REV (Bit 0) */ -#define LEDTS_ID_MOD_REV_Msk \ - (0xffUL) /*!< LEDTS ID: MOD_REV (Bitfield-Mask: 0xff) */ -#define LEDTS_ID_MOD_TYPE_Pos \ - (8UL) /*!< LEDTS ID: MOD_TYPE (Bit 8) */ -#define LEDTS_ID_MOD_TYPE_Msk \ - (0xff00UL) /*!< LEDTS ID: MOD_TYPE (Bitfield-Mask: 0xff) */ -#define LEDTS_ID_MOD_NUMBER_Pos \ - (16UL) /*!< LEDTS ID: MOD_NUMBER (Bit 16) */ -#define LEDTS_ID_MOD_NUMBER_Msk \ - (0xffff0000UL) /*!< LEDTS ID: MOD_NUMBER (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- LEDTS_GLOBCTL ------------------------------- */ -#define LEDTS_GLOBCTL_TS_EN_Pos \ - (0UL) /*!< LEDTS GLOBCTL: TS_EN (Bit 0) */ -#define LEDTS_GLOBCTL_TS_EN_Msk \ - (0x1UL) /*!< LEDTS GLOBCTL: TS_EN (Bitfield-Mask: 0x01) */ -#define LEDTS_GLOBCTL_LD_EN_Pos \ - (1UL) /*!< LEDTS GLOBCTL: LD_EN (Bit 1) */ -#define LEDTS_GLOBCTL_LD_EN_Msk \ - (0x2UL) /*!< LEDTS GLOBCTL: LD_EN (Bitfield-Mask: 0x01) */ -#define LEDTS_GLOBCTL_CMTR_Pos \ - (2UL) /*!< LEDTS GLOBCTL: CMTR (Bit 2) */ -#define LEDTS_GLOBCTL_CMTR_Msk \ - (0x4UL) /*!< LEDTS GLOBCTL: CMTR (Bitfield-Mask: 0x01) */ -#define LEDTS_GLOBCTL_ENSYNC_Pos \ - (3UL) /*!< LEDTS GLOBCTL: ENSYNC (Bit 3) */ -#define LEDTS_GLOBCTL_ENSYNC_Msk \ - (0x8UL) /*!< LEDTS GLOBCTL: ENSYNC (Bitfield-Mask: 0x01) */ -#define LEDTS_GLOBCTL_SUSCFG_Pos \ - (8UL) /*!< LEDTS GLOBCTL: SUSCFG (Bit 8) */ -#define LEDTS_GLOBCTL_SUSCFG_Msk \ - (0x100UL) /*!< LEDTS GLOBCTL: SUSCFG (Bitfield-Mask: 0x01) */ -#define LEDTS_GLOBCTL_MASKVAL_Pos \ - (9UL) /*!< LEDTS GLOBCTL: MASKVAL (Bit 9) */ -#define LEDTS_GLOBCTL_MASKVAL_Msk \ - (0xe00UL) /*!< LEDTS GLOBCTL: MASKVAL (Bitfield-Mask: 0x07) */ -#define LEDTS_GLOBCTL_FENVAL_Pos \ - (12UL) /*!< LEDTS GLOBCTL: FENVAL (Bit 12) */ -#define LEDTS_GLOBCTL_FENVAL_Msk \ - (0x1000UL) /*!< LEDTS GLOBCTL: FENVAL (Bitfield-Mask: 0x01) */ -#define LEDTS_GLOBCTL_ITS_EN_Pos \ - (13UL) /*!< LEDTS GLOBCTL: ITS_EN (Bit 13) */ -#define LEDTS_GLOBCTL_ITS_EN_Msk \ - (0x2000UL) /*!< LEDTS GLOBCTL: ITS_EN (Bitfield-Mask: 0x01) */ -#define LEDTS_GLOBCTL_ITF_EN_Pos \ - (14UL) /*!< LEDTS GLOBCTL: ITF_EN (Bit 14) */ -#define LEDTS_GLOBCTL_ITF_EN_Msk \ - (0x4000UL) /*!< LEDTS GLOBCTL: ITF_EN (Bitfield-Mask: 0x01) */ -#define LEDTS_GLOBCTL_ITP_EN_Pos \ - (15UL) /*!< LEDTS GLOBCTL: ITP_EN (Bit 15) */ -#define LEDTS_GLOBCTL_ITP_EN_Msk \ - (0x8000UL) /*!< LEDTS GLOBCTL: ITP_EN (Bitfield-Mask: 0x01) */ -#define LEDTS_GLOBCTL_CLK_PS_Pos \ - (16UL) /*!< LEDTS GLOBCTL: CLK_PS (Bit 16) */ -#define LEDTS_GLOBCTL_CLK_PS_Msk \ - (0xffff0000UL) /*!< LEDTS GLOBCTL: CLK_PS (Bitfield-Mask: 0xffff) */ - -/* --------------------------------- LEDTS_FNCTL -------------------------------- */ -#define LEDTS_FNCTL_PADT_Pos \ - (0UL) /*!< LEDTS FNCTL: PADT (Bit 0) */ -#define LEDTS_FNCTL_PADT_Msk \ - (0x7UL) /*!< LEDTS FNCTL: PADT (Bitfield-Mask: 0x07) */ -#define LEDTS_FNCTL_PADTSW_Pos \ - (3UL) /*!< LEDTS FNCTL: PADTSW (Bit 3) */ -#define LEDTS_FNCTL_PADTSW_Msk \ - (0x8UL) /*!< LEDTS FNCTL: PADTSW (Bitfield-Mask: 0x01) */ -#define LEDTS_FNCTL_EPULL_Pos \ - (4UL) /*!< LEDTS FNCTL: EPULL (Bit 4) */ -#define LEDTS_FNCTL_EPULL_Msk \ - (0x10UL) /*!< LEDTS FNCTL: EPULL (Bitfield-Mask: 0x01) */ -#define LEDTS_FNCTL_FNCOL_Pos \ - (5UL) /*!< LEDTS FNCTL: FNCOL (Bit 5) */ -#define LEDTS_FNCTL_FNCOL_Msk \ - (0xe0UL) /*!< LEDTS FNCTL: FNCOL (Bitfield-Mask: 0x07) */ -#define LEDTS_FNCTL_ACCCNT_Pos \ - (16UL) /*!< LEDTS FNCTL: ACCCNT (Bit 16) */ -#define LEDTS_FNCTL_ACCCNT_Msk \ - (0xf0000UL) /*!< LEDTS FNCTL: ACCCNT (Bitfield-Mask: 0x0f) */ -#define LEDTS_FNCTL_TSCCMP_Pos \ - (20UL) /*!< LEDTS FNCTL: TSCCMP (Bit 20) */ -#define LEDTS_FNCTL_TSCCMP_Msk \ - (0x100000UL) /*!< LEDTS FNCTL: TSCCMP (Bitfield-Mask: 0x01) */ -#define LEDTS_FNCTL_TSOEXT_Pos \ - (21UL) /*!< LEDTS FNCTL: TSOEXT (Bit 21) */ -#define LEDTS_FNCTL_TSOEXT_Msk \ - (0x600000UL) /*!< LEDTS FNCTL: TSOEXT (Bitfield-Mask: 0x03) */ -#define LEDTS_FNCTL_TSCTRR_Pos \ - (23UL) /*!< LEDTS FNCTL: TSCTRR (Bit 23) */ -#define LEDTS_FNCTL_TSCTRR_Msk \ - (0x800000UL) /*!< LEDTS FNCTL: TSCTRR (Bitfield-Mask: 0x01) */ -#define LEDTS_FNCTL_TSCTRSAT_Pos \ - (24UL) /*!< LEDTS FNCTL: TSCTRSAT (Bit 24) */ -#define LEDTS_FNCTL_TSCTRSAT_Msk \ - (0x1000000UL) /*!< LEDTS FNCTL: TSCTRSAT (Bitfield-Mask: 0x01) */ -#define LEDTS_FNCTL_NR_TSIN_Pos \ - (25UL) /*!< LEDTS FNCTL: NR_TSIN (Bit 25) */ -#define LEDTS_FNCTL_NR_TSIN_Msk \ - (0xe000000UL) /*!< LEDTS FNCTL: NR_TSIN (Bitfield-Mask: 0x07) */ -#define LEDTS_FNCTL_COLLEV_Pos \ - (28UL) /*!< LEDTS FNCTL: COLLEV (Bit 28) */ -#define LEDTS_FNCTL_COLLEV_Msk \ - (0x10000000UL) /*!< LEDTS FNCTL: COLLEV (Bitfield-Mask: 0x01) */ -#define LEDTS_FNCTL_NR_LEDCOL_Pos \ - (29UL) /*!< LEDTS FNCTL: NR_LEDCOL (Bit 29) */ -#define LEDTS_FNCTL_NR_LEDCOL_Msk \ - (0xe0000000UL) /*!< LEDTS FNCTL: NR_LEDCOL (Bitfield-Mask: 0x07) */ - -/* --------------------------------- LEDTS_EVFR --------------------------------- */ -#define LEDTS_EVFR_TSF_Pos (0UL) /*!< LEDTS EVFR: TSF (Bit 0) */ -#define LEDTS_EVFR_TSF_Msk \ - (0x1UL) /*!< LEDTS EVFR: TSF (Bitfield-Mask: 0x01) */ -#define LEDTS_EVFR_TFF_Pos (1UL) /*!< LEDTS EVFR: TFF (Bit 1) */ -#define LEDTS_EVFR_TFF_Msk \ - (0x2UL) /*!< LEDTS EVFR: TFF (Bitfield-Mask: 0x01) */ -#define LEDTS_EVFR_TPF_Pos (2UL) /*!< LEDTS EVFR: TPF (Bit 2) */ -#define LEDTS_EVFR_TPF_Msk \ - (0x4UL) /*!< LEDTS EVFR: TPF (Bitfield-Mask: 0x01) */ -#define LEDTS_EVFR_TSCTROVF_Pos \ - (3UL) /*!< LEDTS EVFR: TSCTROVF (Bit 3) */ -#define LEDTS_EVFR_TSCTROVF_Msk \ - (0x8UL) /*!< LEDTS EVFR: TSCTROVF (Bitfield-Mask: 0x01) */ -#define LEDTS_EVFR_CTSF_Pos \ - (16UL) /*!< LEDTS EVFR: CTSF (Bit 16) */ -#define LEDTS_EVFR_CTSF_Msk \ - (0x10000UL) /*!< LEDTS EVFR: CTSF (Bitfield-Mask: 0x01) */ -#define LEDTS_EVFR_CTFF_Pos \ - (17UL) /*!< LEDTS EVFR: CTFF (Bit 17) */ -#define LEDTS_EVFR_CTFF_Msk \ - (0x20000UL) /*!< LEDTS EVFR: CTFF (Bitfield-Mask: 0x01) */ -#define LEDTS_EVFR_CTPF_Pos \ - (18UL) /*!< LEDTS EVFR: CTPF (Bit 18) */ -#define LEDTS_EVFR_CTPF_Msk \ - (0x40000UL) /*!< LEDTS EVFR: CTPF (Bitfield-Mask: 0x01) */ - -/* --------------------------------- LEDTS_TSVAL -------------------------------- */ -#define LEDTS_TSVAL_TSCTRVALR_Pos \ - (0UL) /*!< LEDTS TSVAL: TSCTRVALR (Bit 0) */ -#define LEDTS_TSVAL_TSCTRVALR_Msk \ - (0xffffUL) /*!< LEDTS TSVAL: TSCTRVALR (Bitfield-Mask: 0xffff) */ -#define LEDTS_TSVAL_TSCTRVAL_Pos \ - (16UL) /*!< LEDTS TSVAL: TSCTRVAL (Bit 16) */ -#define LEDTS_TSVAL_TSCTRVAL_Msk \ - (0xffff0000UL) /*!< LEDTS TSVAL: TSCTRVAL (Bitfield-Mask: 0xffff) */ - -/* --------------------------------- LEDTS_LINE0 -------------------------------- */ -#define LEDTS_LINE0_LINE_0_Pos \ - (0UL) /*!< LEDTS LINE0: LINE_0 (Bit 0) */ -#define LEDTS_LINE0_LINE_0_Msk \ - (0xffUL) /*!< LEDTS LINE0: LINE_0 (Bitfield-Mask: 0xff) */ -#define LEDTS_LINE0_LINE_1_Pos \ - (8UL) /*!< LEDTS LINE0: LINE_1 (Bit 8) */ -#define LEDTS_LINE0_LINE_1_Msk \ - (0xff00UL) /*!< LEDTS LINE0: LINE_1 (Bitfield-Mask: 0xff) */ -#define LEDTS_LINE0_LINE_2_Pos \ - (16UL) /*!< LEDTS LINE0: LINE_2 (Bit 16) */ -#define LEDTS_LINE0_LINE_2_Msk \ - (0xff0000UL) /*!< LEDTS LINE0: LINE_2 (Bitfield-Mask: 0xff) */ -#define LEDTS_LINE0_LINE_3_Pos \ - (24UL) /*!< LEDTS LINE0: LINE_3 (Bit 24) */ -#define LEDTS_LINE0_LINE_3_Msk \ - (0xff000000UL) /*!< LEDTS LINE0: LINE_3 (Bitfield-Mask: 0xff) */ - -/* --------------------------------- LEDTS_LINE1 -------------------------------- */ -#define LEDTS_LINE1_LINE_4_Pos \ - (0UL) /*!< LEDTS LINE1: LINE_4 (Bit 0) */ -#define LEDTS_LINE1_LINE_4_Msk \ - (0xffUL) /*!< LEDTS LINE1: LINE_4 (Bitfield-Mask: 0xff) */ -#define LEDTS_LINE1_LINE_5_Pos \ - (8UL) /*!< LEDTS LINE1: LINE_5 (Bit 8) */ -#define LEDTS_LINE1_LINE_5_Msk \ - (0xff00UL) /*!< LEDTS LINE1: LINE_5 (Bitfield-Mask: 0xff) */ -#define LEDTS_LINE1_LINE_6_Pos \ - (16UL) /*!< LEDTS LINE1: LINE_6 (Bit 16) */ -#define LEDTS_LINE1_LINE_6_Msk \ - (0xff0000UL) /*!< LEDTS LINE1: LINE_6 (Bitfield-Mask: 0xff) */ -#define LEDTS_LINE1_LINE_A_Pos \ - (24UL) /*!< LEDTS LINE1: LINE_A (Bit 24) */ -#define LEDTS_LINE1_LINE_A_Msk \ - (0xff000000UL) /*!< LEDTS LINE1: LINE_A (Bitfield-Mask: 0xff) */ - -/* -------------------------------- LEDTS_LDCMP0 -------------------------------- */ -#define LEDTS_LDCMP0_CMP_LD0_Pos \ - (0UL) /*!< LEDTS LDCMP0: CMP_LD0 (Bit 0) */ -#define LEDTS_LDCMP0_CMP_LD0_Msk \ - (0xffUL) /*!< LEDTS LDCMP0: CMP_LD0 (Bitfield-Mask: 0xff) */ -#define LEDTS_LDCMP0_CMP_LD1_Pos \ - (8UL) /*!< LEDTS LDCMP0: CMP_LD1 (Bit 8) */ -#define LEDTS_LDCMP0_CMP_LD1_Msk \ - (0xff00UL) /*!< LEDTS LDCMP0: CMP_LD1 (Bitfield-Mask: 0xff) */ -#define LEDTS_LDCMP0_CMP_LD2_Pos \ - (16UL) /*!< LEDTS LDCMP0: CMP_LD2 (Bit 16) */ -#define LEDTS_LDCMP0_CMP_LD2_Msk \ - (0xff0000UL) /*!< LEDTS LDCMP0: CMP_LD2 (Bitfield-Mask: 0xff) */ -#define LEDTS_LDCMP0_CMP_LD3_Pos \ - (24UL) /*!< LEDTS LDCMP0: CMP_LD3 (Bit 24) */ -#define LEDTS_LDCMP0_CMP_LD3_Msk \ - (0xff000000UL) /*!< LEDTS LDCMP0: CMP_LD3 (Bitfield-Mask: 0xff) */ - -/* -------------------------------- LEDTS_LDCMP1 -------------------------------- */ -#define LEDTS_LDCMP1_CMP_LD4_Pos \ - (0UL) /*!< LEDTS LDCMP1: CMP_LD4 (Bit 0) */ -#define LEDTS_LDCMP1_CMP_LD4_Msk \ - (0xffUL) /*!< LEDTS LDCMP1: CMP_LD4 (Bitfield-Mask: 0xff) */ -#define LEDTS_LDCMP1_CMP_LD5_Pos \ - (8UL) /*!< LEDTS LDCMP1: CMP_LD5 (Bit 8) */ -#define LEDTS_LDCMP1_CMP_LD5_Msk \ - (0xff00UL) /*!< LEDTS LDCMP1: CMP_LD5 (Bitfield-Mask: 0xff) */ -#define LEDTS_LDCMP1_CMP_LD6_Pos \ - (16UL) /*!< LEDTS LDCMP1: CMP_LD6 (Bit 16) */ -#define LEDTS_LDCMP1_CMP_LD6_Msk \ - (0xff0000UL) /*!< LEDTS LDCMP1: CMP_LD6 (Bitfield-Mask: 0xff) */ -#define LEDTS_LDCMP1_CMP_LDA_TSCOM_Pos \ - (24UL) /*!< LEDTS LDCMP1: CMP_LDA_TSCOM (Bit 24) */ -#define LEDTS_LDCMP1_CMP_LDA_TSCOM_Msk \ - (0xff000000UL) /*!< LEDTS LDCMP1: CMP_LDA_TSCOM (Bitfield-Mask: 0xff) */ - -/* -------------------------------- LEDTS_TSCMP0 -------------------------------- */ -#define LEDTS_TSCMP0_CMP_TS0_Pos \ - (0UL) /*!< LEDTS TSCMP0: CMP_TS0 (Bit 0) */ -#define LEDTS_TSCMP0_CMP_TS0_Msk \ - (0xffUL) /*!< LEDTS TSCMP0: CMP_TS0 (Bitfield-Mask: 0xff) */ -#define LEDTS_TSCMP0_CMP_TS1_Pos \ - (8UL) /*!< LEDTS TSCMP0: CMP_TS1 (Bit 8) */ -#define LEDTS_TSCMP0_CMP_TS1_Msk \ - (0xff00UL) /*!< LEDTS TSCMP0: CMP_TS1 (Bitfield-Mask: 0xff) */ -#define LEDTS_TSCMP0_CMP_TS2_Pos \ - (16UL) /*!< LEDTS TSCMP0: CMP_TS2 (Bit 16) */ -#define LEDTS_TSCMP0_CMP_TS2_Msk \ - (0xff0000UL) /*!< LEDTS TSCMP0: CMP_TS2 (Bitfield-Mask: 0xff) */ -#define LEDTS_TSCMP0_CMP_TS3_Pos \ - (24UL) /*!< LEDTS TSCMP0: CMP_TS3 (Bit 24) */ -#define LEDTS_TSCMP0_CMP_TS3_Msk \ - (0xff000000UL) /*!< LEDTS TSCMP0: CMP_TS3 (Bitfield-Mask: 0xff) */ - -/* -------------------------------- LEDTS_TSCMP1 -------------------------------- */ -#define LEDTS_TSCMP1_CMP_TS4_Pos \ - (0UL) /*!< LEDTS TSCMP1: CMP_TS4 (Bit 0) */ -#define LEDTS_TSCMP1_CMP_TS4_Msk \ - (0xffUL) /*!< LEDTS TSCMP1: CMP_TS4 (Bitfield-Mask: 0xff) */ -#define LEDTS_TSCMP1_CMP_TS5_Pos \ - (8UL) /*!< LEDTS TSCMP1: CMP_TS5 (Bit 8) */ -#define LEDTS_TSCMP1_CMP_TS5_Msk \ - (0xff00UL) /*!< LEDTS TSCMP1: CMP_TS5 (Bitfield-Mask: 0xff) */ -#define LEDTS_TSCMP1_CMP_TS6_Pos \ - (16UL) /*!< LEDTS TSCMP1: CMP_TS6 (Bit 16) */ -#define LEDTS_TSCMP1_CMP_TS6_Msk \ - (0xff0000UL) /*!< LEDTS TSCMP1: CMP_TS6 (Bitfield-Mask: 0xff) */ -#define LEDTS_TSCMP1_CMP_TS7_Pos \ - (24UL) /*!< LEDTS TSCMP1: CMP_TS7 (Bit 24) */ -#define LEDTS_TSCMP1_CMP_TS7_Msk \ - (0xff000000UL) /*!< LEDTS TSCMP1: CMP_TS7 (Bitfield-Mask: 0xff) */ - -/* ================================================================================ */ -/* ================ Group 'USB' Position & Mask ================ */ -/* ================================================================================ */ - -/* --------------------------------- USB_GAHBCFG -------------------------------- */ -#define USB_GAHBCFG_GlblIntrMsk_Pos \ - (0UL) /*!< USB GAHBCFG: GlblIntrMsk (Bit 0) */ -#define USB_GAHBCFG_GlblIntrMsk_Msk \ - (0x1UL) /*!< USB GAHBCFG: GlblIntrMsk (Bitfield-Mask: 0x01) */ -#define USB_GAHBCFG_HBstLen_Pos \ - (1UL) /*!< USB GAHBCFG: HBstLen (Bit 1) */ -#define USB_GAHBCFG_HBstLen_Msk \ - (0x1eUL) /*!< USB GAHBCFG: HBstLen (Bitfield-Mask: 0x0f) */ -#define USB_GAHBCFG_DMAEn_Pos \ - (5UL) /*!< USB GAHBCFG: DMAEn (Bit 5) */ -#define USB_GAHBCFG_DMAEn_Msk \ - (0x20UL) /*!< USB GAHBCFG: DMAEn (Bitfield-Mask: 0x01) */ -#define USB_GAHBCFG_NPTxFEmpLvl_Pos \ - (7UL) /*!< USB GAHBCFG: NPTxFEmpLvl (Bit 7) */ -#define USB_GAHBCFG_NPTxFEmpLvl_Msk \ - (0x80UL) /*!< USB GAHBCFG: NPTxFEmpLvl (Bitfield-Mask: 0x01) */ -#define USB_GAHBCFG_AHBSingle_Pos \ - (23UL) /*!< USB GAHBCFG: AHBSingle (Bit 23) */ -#define USB_GAHBCFG_AHBSingle_Msk \ - (0x800000UL) /*!< USB GAHBCFG: AHBSingle (Bitfield-Mask: 0x01) */ - -/* --------------------------------- USB_GUSBCFG -------------------------------- */ -#define USB_GUSBCFG_TOutCal_Pos \ - (0UL) /*!< USB GUSBCFG: TOutCal (Bit 0) */ -#define USB_GUSBCFG_TOutCal_Msk \ - (0x7UL) /*!< USB GUSBCFG: TOutCal (Bitfield-Mask: 0x07) */ -#define USB_GUSBCFG_PHYSel_Pos \ - (6UL) /*!< USB GUSBCFG: PHYSel (Bit 6) */ -#define USB_GUSBCFG_PHYSel_Msk \ - (0x40UL) /*!< USB GUSBCFG: PHYSel (Bitfield-Mask: 0x01) */ -#define USB_GUSBCFG_USBTrdTim_Pos \ - (10UL) /*!< USB GUSBCFG: USBTrdTim (Bit 10) */ -#define USB_GUSBCFG_USBTrdTim_Msk \ - (0x3c00UL) /*!< USB GUSBCFG: USBTrdTim (Bitfield-Mask: 0x0f) */ -#define USB_GUSBCFG_TxEndDelay_Pos \ - (28UL) /*!< USB GUSBCFG: TxEndDelay (Bit 28) */ -#define USB_GUSBCFG_TxEndDelay_Msk \ - (0x10000000UL) /*!< USB GUSBCFG: TxEndDelay (Bitfield-Mask: 0x01) */ -#define USB_GUSBCFG_ForceDevMode_Pos \ - (30UL) /*!< USB GUSBCFG: ForceDevMode (Bit 30) */ -#define USB_GUSBCFG_ForceDevMode_Msk \ - (0x40000000UL) /*!< USB GUSBCFG: ForceDevMode (Bitfield-Mask: 0x01) */ -#define USB_GUSBCFG_CTP_Pos \ - (31UL) /*!< USB GUSBCFG: CTP (Bit 31) */ -#define USB_GUSBCFG_CTP_Msk \ - (0x80000000UL) /*!< USB GUSBCFG: CTP (Bitfield-Mask: 0x01) */ - -/* --------------------------------- USB_GRSTCTL -------------------------------- */ -#define USB_GRSTCTL_CSftRst_Pos \ - (0UL) /*!< USB GRSTCTL: CSftRst (Bit 0) */ -#define USB_GRSTCTL_CSftRst_Msk \ - (0x1UL) /*!< USB GRSTCTL: CSftRst (Bitfield-Mask: 0x01) */ -#define USB_GRSTCTL_RxFFlsh_Pos \ - (4UL) /*!< USB GRSTCTL: RxFFlsh (Bit 4) */ -#define USB_GRSTCTL_RxFFlsh_Msk \ - (0x10UL) /*!< USB GRSTCTL: RxFFlsh (Bitfield-Mask: 0x01) */ -#define USB_GRSTCTL_TxFFlsh_Pos \ - (5UL) /*!< USB GRSTCTL: TxFFlsh (Bit 5) */ -#define USB_GRSTCTL_TxFFlsh_Msk \ - (0x20UL) /*!< USB GRSTCTL: TxFFlsh (Bitfield-Mask: 0x01) */ -#define USB_GRSTCTL_TxFNum_Pos \ - (6UL) /*!< USB GRSTCTL: TxFNum (Bit 6) */ -#define USB_GRSTCTL_TxFNum_Msk \ - (0x7c0UL) /*!< USB GRSTCTL: TxFNum (Bitfield-Mask: 0x1f) */ -#define USB_GRSTCTL_DMAReq_Pos \ - (30UL) /*!< USB GRSTCTL: DMAReq (Bit 30) */ -#define USB_GRSTCTL_DMAReq_Msk \ - (0x40000000UL) /*!< USB GRSTCTL: DMAReq (Bitfield-Mask: 0x01) */ -#define USB_GRSTCTL_AHBIdle_Pos \ - (31UL) /*!< USB GRSTCTL: AHBIdle (Bit 31) */ -#define USB_GRSTCTL_AHBIdle_Msk \ - (0x80000000UL) /*!< USB GRSTCTL: AHBIdle (Bitfield-Mask: 0x01) */ - -/* --------------------------------- USB_GINTSTS -------------------------------- */ -#define USB_GINTSTS_CurMod_Pos \ - (0UL) /*!< USB GINTSTS: CurMod (Bit 0) */ -#define USB_GINTSTS_CurMod_Msk \ - (0x1UL) /*!< USB GINTSTS: CurMod (Bitfield-Mask: 0x01) */ -#define USB_GINTSTS_Sof_Pos \ - (3UL) /*!< USB GINTSTS: Sof (Bit 3) */ -#define USB_GINTSTS_Sof_Msk \ - (0x8UL) /*!< USB GINTSTS: Sof (Bitfield-Mask: 0x01) */ -#define USB_GINTSTS_RxFLvl_Pos \ - (4UL) /*!< USB GINTSTS: RxFLvl (Bit 4) */ -#define USB_GINTSTS_RxFLvl_Msk \ - (0x10UL) /*!< USB GINTSTS: RxFLvl (Bitfield-Mask: 0x01) */ -#define USB_GINTSTS_GINNakEff_Pos \ - (6UL) /*!< USB GINTSTS: GINNakEff (Bit 6) */ -#define USB_GINTSTS_GINNakEff_Msk \ - (0x40UL) /*!< USB GINTSTS: GINNakEff (Bitfield-Mask: 0x01) */ -#define USB_GINTSTS_GOUTNakEff_Pos \ - (7UL) /*!< USB GINTSTS: GOUTNakEff (Bit 7) */ -#define USB_GINTSTS_GOUTNakEff_Msk \ - (0x80UL) /*!< USB GINTSTS: GOUTNakEff (Bitfield-Mask: 0x01) */ -#define USB_GINTSTS_ErlySusp_Pos \ - (10UL) /*!< USB GINTSTS: ErlySusp (Bit 10) */ -#define USB_GINTSTS_ErlySusp_Msk \ - (0x400UL) /*!< USB GINTSTS: ErlySusp (Bitfield-Mask: 0x01) */ -#define USB_GINTSTS_USBSusp_Pos \ - (11UL) /*!< USB GINTSTS: USBSusp (Bit 11) */ -#define USB_GINTSTS_USBSusp_Msk \ - (0x800UL) /*!< USB GINTSTS: USBSusp (Bitfield-Mask: 0x01) */ -#define USB_GINTSTS_USBRst_Pos \ - (12UL) /*!< USB GINTSTS: USBRst (Bit 12) */ -#define USB_GINTSTS_USBRst_Msk \ - (0x1000UL) /*!< USB GINTSTS: USBRst (Bitfield-Mask: 0x01) */ -#define USB_GINTSTS_EnumDone_Pos \ - (13UL) /*!< USB GINTSTS: EnumDone (Bit 13) */ -#define USB_GINTSTS_EnumDone_Msk \ - (0x2000UL) /*!< USB GINTSTS: EnumDone (Bitfield-Mask: 0x01) */ -#define USB_GINTSTS_ISOOutDrop_Pos \ - (14UL) /*!< USB GINTSTS: ISOOutDrop (Bit 14) */ -#define USB_GINTSTS_ISOOutDrop_Msk \ - (0x4000UL) /*!< USB GINTSTS: ISOOutDrop (Bitfield-Mask: 0x01) */ -#define USB_GINTSTS_EOPF_Pos \ - (15UL) /*!< USB GINTSTS: EOPF (Bit 15) */ -#define USB_GINTSTS_EOPF_Msk \ - (0x8000UL) /*!< USB GINTSTS: EOPF (Bitfield-Mask: 0x01) */ -#define USB_GINTSTS_IEPInt_Pos \ - (18UL) /*!< USB GINTSTS: IEPInt (Bit 18) */ -#define USB_GINTSTS_IEPInt_Msk \ - (0x40000UL) /*!< USB GINTSTS: IEPInt (Bitfield-Mask: 0x01) */ -#define USB_GINTSTS_OEPInt_Pos \ - (19UL) /*!< USB GINTSTS: OEPInt (Bit 19) */ -#define USB_GINTSTS_OEPInt_Msk \ - (0x80000UL) /*!< USB GINTSTS: OEPInt (Bitfield-Mask: 0x01) */ -#define USB_GINTSTS_incompISOIN_Pos \ - (20UL) /*!< USB GINTSTS: incompISOIN (Bit 20) */ -#define USB_GINTSTS_incompISOIN_Msk \ - (0x100000UL) /*!< USB GINTSTS: incompISOIN (Bitfield-Mask: 0x01) */ -#define USB_GINTSTS_incomplSOOUT_Pos \ - (21UL) /*!< USB GINTSTS: incomplSOOUT (Bit 21) */ -#define USB_GINTSTS_incomplSOOUT_Msk \ - (0x200000UL) /*!< USB GINTSTS: incomplSOOUT (Bitfield-Mask: 0x01) */ -#define USB_GINTSTS_WkUpInt_Pos \ - (31UL) /*!< USB GINTSTS: WkUpInt (Bit 31) */ -#define USB_GINTSTS_WkUpInt_Msk \ - (0x80000000UL) /*!< USB GINTSTS: WkUpInt (Bitfield-Mask: 0x01) */ - -/* --------------------------------- USB_GINTMSK -------------------------------- */ -#define USB_GINTMSK_SofMsk_Pos \ - (3UL) /*!< USB GINTMSK: SofMsk (Bit 3) */ -#define USB_GINTMSK_SofMsk_Msk \ - (0x8UL) /*!< USB GINTMSK: SofMsk (Bitfield-Mask: 0x01) */ -#define USB_GINTMSK_RxFLvlMsk_Pos \ - (4UL) /*!< USB GINTMSK: RxFLvlMsk (Bit 4) */ -#define USB_GINTMSK_RxFLvlMsk_Msk \ - (0x10UL) /*!< USB GINTMSK: RxFLvlMsk (Bitfield-Mask: 0x01) */ -#define USB_GINTMSK_GINNakEffMsk_Pos \ - (6UL) /*!< USB GINTMSK: GINNakEffMsk (Bit 6) */ -#define USB_GINTMSK_GINNakEffMsk_Msk \ - (0x40UL) /*!< USB GINTMSK: GINNakEffMsk (Bitfield-Mask: 0x01) */ -#define USB_GINTMSK_GOUTNakEffMsk_Pos \ - (7UL) /*!< USB GINTMSK: GOUTNakEffMsk (Bit 7) */ -#define USB_GINTMSK_GOUTNakEffMsk_Msk \ - (0x80UL) /*!< USB GINTMSK: GOUTNakEffMsk (Bitfield-Mask: 0x01) */ -#define USB_GINTMSK_ErlySuspMsk_Pos \ - (10UL) /*!< USB GINTMSK: ErlySuspMsk (Bit 10) */ -#define USB_GINTMSK_ErlySuspMsk_Msk \ - (0x400UL) /*!< USB GINTMSK: ErlySuspMsk (Bitfield-Mask: 0x01) */ -#define USB_GINTMSK_USBSuspMsk_Pos \ - (11UL) /*!< USB GINTMSK: USBSuspMsk (Bit 11) */ -#define USB_GINTMSK_USBSuspMsk_Msk \ - (0x800UL) /*!< USB GINTMSK: USBSuspMsk (Bitfield-Mask: 0x01) */ -#define USB_GINTMSK_USBRstMsk_Pos \ - (12UL) /*!< USB GINTMSK: USBRstMsk (Bit 12) */ -#define USB_GINTMSK_USBRstMsk_Msk \ - (0x1000UL) /*!< USB GINTMSK: USBRstMsk (Bitfield-Mask: 0x01) */ -#define USB_GINTMSK_EnumDoneMsk_Pos \ - (13UL) /*!< USB GINTMSK: EnumDoneMsk (Bit 13) */ -#define USB_GINTMSK_EnumDoneMsk_Msk \ - (0x2000UL) /*!< USB GINTMSK: EnumDoneMsk (Bitfield-Mask: 0x01) */ -#define USB_GINTMSK_ISOOutDropMsk_Pos \ - (14UL) /*!< USB GINTMSK: ISOOutDropMsk (Bit 14) */ -#define USB_GINTMSK_ISOOutDropMsk_Msk \ - (0x4000UL) /*!< USB GINTMSK: ISOOutDropMsk (Bitfield-Mask: 0x01) */ -#define USB_GINTMSK_EOPFMsk_Pos \ - (15UL) /*!< USB GINTMSK: EOPFMsk (Bit 15) */ -#define USB_GINTMSK_EOPFMsk_Msk \ - (0x8000UL) /*!< USB GINTMSK: EOPFMsk (Bitfield-Mask: 0x01) */ -#define USB_GINTMSK_IEPIntMsk_Pos \ - (18UL) /*!< USB GINTMSK: IEPIntMsk (Bit 18) */ -#define USB_GINTMSK_IEPIntMsk_Msk \ - (0x40000UL) /*!< USB GINTMSK: IEPIntMsk (Bitfield-Mask: 0x01) */ -#define USB_GINTMSK_OEPIntMsk_Pos \ - (19UL) /*!< USB GINTMSK: OEPIntMsk (Bit 19) */ -#define USB_GINTMSK_OEPIntMsk_Msk \ - (0x80000UL) /*!< USB GINTMSK: OEPIntMsk (Bitfield-Mask: 0x01) */ -#define USB_GINTMSK_incompISOINMsk_Pos \ - (20UL) /*!< USB GINTMSK: incompISOINMsk (Bit 20) */ -#define USB_GINTMSK_incompISOINMsk_Msk \ - (0x100000UL) /*!< USB GINTMSK: incompISOINMsk (Bitfield-Mask: 0x01) */ -#define USB_GINTMSK_incomplSOOUTMsk_Pos \ - (21UL) /*!< USB GINTMSK: incomplSOOUTMsk (Bit 21) */ -#define USB_GINTMSK_incomplSOOUTMsk_Msk \ - (0x200000UL) /*!< USB GINTMSK: incomplSOOUTMsk (Bitfield-Mask: 0x01) */ -#define USB_GINTMSK_WkUpIntMsk_Pos \ - (31UL) /*!< USB GINTMSK: WkUpIntMsk (Bit 31) */ -#define USB_GINTMSK_WkUpIntMsk_Msk \ - (0x80000000UL) /*!< USB GINTMSK: WkUpIntMsk (Bitfield-Mask: 0x01) */ - -/* --------------------------------- USB_GRXSTSR -------------------------------- */ -#define USB_GRXSTSR_EPNum_Pos \ - (0UL) /*!< USB GRXSTSR: EPNum (Bit 0) */ -#define USB_GRXSTSR_EPNum_Msk \ - (0xfUL) /*!< USB GRXSTSR: EPNum (Bitfield-Mask: 0x0f) */ -#define USB_GRXSTSR_BCnt_Pos \ - (4UL) /*!< USB GRXSTSR: BCnt (Bit 4) */ -#define USB_GRXSTSR_BCnt_Msk \ - (0x7ff0UL) /*!< USB GRXSTSR: BCnt (Bitfield-Mask: 0x7ff) */ -#define USB_GRXSTSR_DPID_Pos \ - (15UL) /*!< USB GRXSTSR: DPID (Bit 15) */ -#define USB_GRXSTSR_DPID_Msk \ - (0x18000UL) /*!< USB GRXSTSR: DPID (Bitfield-Mask: 0x03) */ -#define USB_GRXSTSR_PktSts_Pos \ - (17UL) /*!< USB GRXSTSR: PktSts (Bit 17) */ -#define USB_GRXSTSR_PktSts_Msk \ - (0x1e0000UL) /*!< USB GRXSTSR: PktSts (Bitfield-Mask: 0x0f) */ -#define USB_GRXSTSR_FN_Pos \ - (21UL) /*!< USB GRXSTSR: FN (Bit 21) */ -#define USB_GRXSTSR_FN_Msk \ - (0x1e00000UL) /*!< USB GRXSTSR: FN (Bitfield-Mask: 0x0f) */ - -/* --------------------------------- USB_GRXSTSP -------------------------------- */ -#define USB_GRXSTSP_EPNum_Pos \ - (0UL) /*!< USB GRXSTSP: EPNum (Bit 0) */ -#define USB_GRXSTSP_EPNum_Msk \ - (0xfUL) /*!< USB GRXSTSP: EPNum (Bitfield-Mask: 0x0f) */ -#define USB_GRXSTSP_BCnt_Pos \ - (4UL) /*!< USB GRXSTSP: BCnt (Bit 4) */ -#define USB_GRXSTSP_BCnt_Msk \ - (0x7ff0UL) /*!< USB GRXSTSP: BCnt (Bitfield-Mask: 0x7ff) */ -#define USB_GRXSTSP_DPID_Pos \ - (15UL) /*!< USB GRXSTSP: DPID (Bit 15) */ -#define USB_GRXSTSP_DPID_Msk \ - (0x18000UL) /*!< USB GRXSTSP: DPID (Bitfield-Mask: 0x03) */ -#define USB_GRXSTSP_PktSts_Pos \ - (17UL) /*!< USB GRXSTSP: PktSts (Bit 17) */ -#define USB_GRXSTSP_PktSts_Msk \ - (0x1e0000UL) /*!< USB GRXSTSP: PktSts (Bitfield-Mask: 0x0f) */ -#define USB_GRXSTSP_FN_Pos \ - (21UL) /*!< USB GRXSTSP: FN (Bit 21) */ -#define USB_GRXSTSP_FN_Msk \ - (0x1e00000UL) /*!< USB GRXSTSP: FN (Bitfield-Mask: 0x0f) */ - -/* --------------------------------- USB_GRXFSIZ -------------------------------- */ -#define USB_GRXFSIZ_RxFDep_Pos \ - (0UL) /*!< USB GRXFSIZ: RxFDep (Bit 0) */ -#define USB_GRXFSIZ_RxFDep_Msk \ - (0xffffUL) /*!< USB GRXFSIZ: RxFDep (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- USB_GNPTXFSIZ ------------------------------- */ -#define USB_GNPTXFSIZ_INEPTxF0StAddr_Pos \ - (0UL) /*!< USB GNPTXFSIZ: INEPTxF0StAddr (Bit 0) */ -#define USB_GNPTXFSIZ_INEPTxF0StAddr_Msk \ - (0xffffUL) /*!< USB GNPTXFSIZ: INEPTxF0StAddr (Bitfield-Mask: 0xffff) */ -#define USB_GNPTXFSIZ_INEPTxF0Dep_Pos \ - (16UL) /*!< USB GNPTXFSIZ: INEPTxF0Dep (Bit 16) */ -#define USB_GNPTXFSIZ_INEPTxF0Dep_Msk \ - (0xffff0000UL) /*!< USB GNPTXFSIZ: INEPTxF0Dep (Bitfield-Mask: 0xffff) */ - -/* ---------------------------------- USB_GUID ---------------------------------- */ -#define USB_GUID_MOD_REV_Pos \ - (0UL) /*!< USB GUID: MOD_REV (Bit 0) */ -#define USB_GUID_MOD_REV_Msk \ - (0xffUL) /*!< USB GUID: MOD_REV (Bitfield-Mask: 0xff) */ -#define USB_GUID_MOD_TYPE_Pos \ - (8UL) /*!< USB GUID: MOD_TYPE (Bit 8) */ -#define USB_GUID_MOD_TYPE_Msk \ - (0xff00UL) /*!< USB GUID: MOD_TYPE (Bitfield-Mask: 0xff) */ -#define USB_GUID_MOD_NUMBER_Pos \ - (16UL) /*!< USB GUID: MOD_NUMBER (Bit 16) */ -#define USB_GUID_MOD_NUMBER_Msk \ - (0xffff0000UL) /*!< USB GUID: MOD_NUMBER (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- USB_GDFIFOCFG ------------------------------- */ -#define USB_GDFIFOCFG_GDFIFOCfg_Pos \ - (0UL) /*!< USB GDFIFOCFG: GDFIFOCfg (Bit 0) */ -#define USB_GDFIFOCFG_GDFIFOCfg_Msk \ - (0xffffUL) /*!< USB GDFIFOCFG: GDFIFOCfg (Bitfield-Mask: 0xffff) */ -#define USB_GDFIFOCFG_EPInfoBaseAddr_Pos \ - (16UL) /*!< USB GDFIFOCFG: EPInfoBaseAddr (Bit 16) */ -#define USB_GDFIFOCFG_EPInfoBaseAddr_Msk \ - (0xffff0000UL) /*!< USB GDFIFOCFG: EPInfoBaseAddr (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- USB_DIEPTXF1 -------------------------------- */ -#define USB_DIEPTXF1_INEPnTxFStAddr_Pos \ - (0UL) /*!< USB DIEPTXF1: INEPnTxFStAddr (Bit 0) */ -#define USB_DIEPTXF1_INEPnTxFStAddr_Msk \ - (0xffffUL) /*!< USB DIEPTXF1: INEPnTxFStAddr (Bitfield-Mask: 0xffff) */ -#define USB_DIEPTXF1_INEPnTxFDep_Pos \ - (16UL) /*!< USB DIEPTXF1: INEPnTxFDep (Bit 16) */ -#define USB_DIEPTXF1_INEPnTxFDep_Msk \ - (0xffff0000UL) /*!< USB DIEPTXF1: INEPnTxFDep (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- USB_DIEPTXF2 -------------------------------- */ -#define USB_DIEPTXF2_INEPnTxFStAddr_Pos \ - (0UL) /*!< USB DIEPTXF2: INEPnTxFStAddr (Bit 0) */ -#define USB_DIEPTXF2_INEPnTxFStAddr_Msk \ - (0xffffUL) /*!< USB DIEPTXF2: INEPnTxFStAddr (Bitfield-Mask: 0xffff) */ -#define USB_DIEPTXF2_INEPnTxFDep_Pos \ - (16UL) /*!< USB DIEPTXF2: INEPnTxFDep (Bit 16) */ -#define USB_DIEPTXF2_INEPnTxFDep_Msk \ - (0xffff0000UL) /*!< USB DIEPTXF2: INEPnTxFDep (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- USB_DIEPTXF3 -------------------------------- */ -#define USB_DIEPTXF3_INEPnTxFStAddr_Pos \ - (0UL) /*!< USB DIEPTXF3: INEPnTxFStAddr (Bit 0) */ -#define USB_DIEPTXF3_INEPnTxFStAddr_Msk \ - (0xffffUL) /*!< USB DIEPTXF3: INEPnTxFStAddr (Bitfield-Mask: 0xffff) */ -#define USB_DIEPTXF3_INEPnTxFDep_Pos \ - (16UL) /*!< USB DIEPTXF3: INEPnTxFDep (Bit 16) */ -#define USB_DIEPTXF3_INEPnTxFDep_Msk \ - (0xffff0000UL) /*!< USB DIEPTXF3: INEPnTxFDep (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- USB_DIEPTXF4 -------------------------------- */ -#define USB_DIEPTXF4_INEPnTxFStAddr_Pos \ - (0UL) /*!< USB DIEPTXF4: INEPnTxFStAddr (Bit 0) */ -#define USB_DIEPTXF4_INEPnTxFStAddr_Msk \ - (0xffffUL) /*!< USB DIEPTXF4: INEPnTxFStAddr (Bitfield-Mask: 0xffff) */ -#define USB_DIEPTXF4_INEPnTxFDep_Pos \ - (16UL) /*!< USB DIEPTXF4: INEPnTxFDep (Bit 16) */ -#define USB_DIEPTXF4_INEPnTxFDep_Msk \ - (0xffff0000UL) /*!< USB DIEPTXF4: INEPnTxFDep (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- USB_DIEPTXF5 -------------------------------- */ -#define USB_DIEPTXF5_INEPnTxFStAddr_Pos \ - (0UL) /*!< USB DIEPTXF5: INEPnTxFStAddr (Bit 0) */ -#define USB_DIEPTXF5_INEPnTxFStAddr_Msk \ - (0xffffUL) /*!< USB DIEPTXF5: INEPnTxFStAddr (Bitfield-Mask: 0xffff) */ -#define USB_DIEPTXF5_INEPnTxFDep_Pos \ - (16UL) /*!< USB DIEPTXF5: INEPnTxFDep (Bit 16) */ -#define USB_DIEPTXF5_INEPnTxFDep_Msk \ - (0xffff0000UL) /*!< USB DIEPTXF5: INEPnTxFDep (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- USB_DIEPTXF6 -------------------------------- */ -#define USB_DIEPTXF6_INEPnTxFStAddr_Pos \ - (0UL) /*!< USB DIEPTXF6: INEPnTxFStAddr (Bit 0) */ -#define USB_DIEPTXF6_INEPnTxFStAddr_Msk \ - (0xffffUL) /*!< USB DIEPTXF6: INEPnTxFStAddr (Bitfield-Mask: 0xffff) */ -#define USB_DIEPTXF6_INEPnTxFDep_Pos \ - (16UL) /*!< USB DIEPTXF6: INEPnTxFDep (Bit 16) */ -#define USB_DIEPTXF6_INEPnTxFDep_Msk \ - (0xffff0000UL) /*!< USB DIEPTXF6: INEPnTxFDep (Bitfield-Mask: 0xffff) */ - -/* ---------------------------------- USB_DCFG ---------------------------------- */ -#define USB_DCFG_DevSpd_Pos \ - (0UL) /*!< USB DCFG: DevSpd (Bit 0) */ -#define USB_DCFG_DevSpd_Msk \ - (0x3UL) /*!< USB DCFG: DevSpd (Bitfield-Mask: 0x03) */ -#define USB_DCFG_NZStsOUTHShk_Pos \ - (2UL) /*!< USB DCFG: NZStsOUTHShk (Bit 2) */ -#define USB_DCFG_NZStsOUTHShk_Msk \ - (0x4UL) /*!< USB DCFG: NZStsOUTHShk (Bitfield-Mask: 0x01) */ -#define USB_DCFG_DevAddr_Pos \ - (4UL) /*!< USB DCFG: DevAddr (Bit 4) */ -#define USB_DCFG_DevAddr_Msk \ - (0x7f0UL) /*!< USB DCFG: DevAddr (Bitfield-Mask: 0x7f) */ -#define USB_DCFG_PerFrInt_Pos \ - (11UL) /*!< USB DCFG: PerFrInt (Bit 11) */ -#define USB_DCFG_PerFrInt_Msk \ - (0x1800UL) /*!< USB DCFG: PerFrInt (Bitfield-Mask: 0x03) */ -#define USB_DCFG_DescDMA_Pos \ - (23UL) /*!< USB DCFG: DescDMA (Bit 23) */ -#define USB_DCFG_DescDMA_Msk \ - (0x800000UL) /*!< USB DCFG: DescDMA (Bitfield-Mask: 0x01) */ -#define USB_DCFG_PerSchIntvl_Pos \ - (24UL) /*!< USB DCFG: PerSchIntvl (Bit 24) */ -#define USB_DCFG_PerSchIntvl_Msk \ - (0x3000000UL) /*!< USB DCFG: PerSchIntvl (Bitfield-Mask: 0x03) */ - -/* ---------------------------------- USB_DCTL ---------------------------------- */ -#define USB_DCTL_RmtWkUpSig_Pos \ - (0UL) /*!< USB DCTL: RmtWkUpSig (Bit 0) */ -#define USB_DCTL_RmtWkUpSig_Msk \ - (0x1UL) /*!< USB DCTL: RmtWkUpSig (Bitfield-Mask: 0x01) */ -#define USB_DCTL_SftDiscon_Pos \ - (1UL) /*!< USB DCTL: SftDiscon (Bit 1) */ -#define USB_DCTL_SftDiscon_Msk \ - (0x2UL) /*!< USB DCTL: SftDiscon (Bitfield-Mask: 0x01) */ -#define USB_DCTL_GNPINNakSts_Pos \ - (2UL) /*!< USB DCTL: GNPINNakSts (Bit 2) */ -#define USB_DCTL_GNPINNakSts_Msk \ - (0x4UL) /*!< USB DCTL: GNPINNakSts (Bitfield-Mask: 0x01) */ -#define USB_DCTL_GOUTNakSts_Pos \ - (3UL) /*!< USB DCTL: GOUTNakSts (Bit 3) */ -#define USB_DCTL_GOUTNakSts_Msk \ - (0x8UL) /*!< USB DCTL: GOUTNakSts (Bitfield-Mask: 0x01) */ -#define USB_DCTL_SGNPInNak_Pos \ - (7UL) /*!< USB DCTL: SGNPInNak (Bit 7) */ -#define USB_DCTL_SGNPInNak_Msk \ - (0x80UL) /*!< USB DCTL: SGNPInNak (Bitfield-Mask: 0x01) */ -#define USB_DCTL_CGNPInNak_Pos \ - (8UL) /*!< USB DCTL: CGNPInNak (Bit 8) */ -#define USB_DCTL_CGNPInNak_Msk \ - (0x100UL) /*!< USB DCTL: CGNPInNak (Bitfield-Mask: 0x01) */ -#define USB_DCTL_SGOUTNak_Pos \ - (9UL) /*!< USB DCTL: SGOUTNak (Bit 9) */ -#define USB_DCTL_SGOUTNak_Msk \ - (0x200UL) /*!< USB DCTL: SGOUTNak (Bitfield-Mask: 0x01) */ -#define USB_DCTL_CGOUTNak_Pos \ - (10UL) /*!< USB DCTL: CGOUTNak (Bit 10) */ -#define USB_DCTL_CGOUTNak_Msk \ - (0x400UL) /*!< USB DCTL: CGOUTNak (Bitfield-Mask: 0x01) */ -#define USB_DCTL_GMC_Pos (13UL) /*!< USB DCTL: GMC (Bit 13) */ -#define USB_DCTL_GMC_Msk \ - (0x6000UL) /*!< USB DCTL: GMC (Bitfield-Mask: 0x03) */ -#define USB_DCTL_IgnrFrmNum_Pos \ - (15UL) /*!< USB DCTL: IgnrFrmNum (Bit 15) */ -#define USB_DCTL_IgnrFrmNum_Msk \ - (0x8000UL) /*!< USB DCTL: IgnrFrmNum (Bitfield-Mask: 0x01) */ -#define USB_DCTL_NakOnBble_Pos \ - (16UL) /*!< USB DCTL: NakOnBble (Bit 16) */ -#define USB_DCTL_NakOnBble_Msk \ - (0x10000UL) /*!< USB DCTL: NakOnBble (Bitfield-Mask: 0x01) */ -#define USB_DCTL_EnContOnBNA_Pos \ - (17UL) /*!< USB DCTL: EnContOnBNA (Bit 17) */ -#define USB_DCTL_EnContOnBNA_Msk \ - (0x20000UL) /*!< USB DCTL: EnContOnBNA (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- USB_DSTS ---------------------------------- */ -#define USB_DSTS_SuspSts_Pos \ - (0UL) /*!< USB DSTS: SuspSts (Bit 0) */ -#define USB_DSTS_SuspSts_Msk \ - (0x1UL) /*!< USB DSTS: SuspSts (Bitfield-Mask: 0x01) */ -#define USB_DSTS_EnumSpd_Pos \ - (1UL) /*!< USB DSTS: EnumSpd (Bit 1) */ -#define USB_DSTS_EnumSpd_Msk \ - (0x6UL) /*!< USB DSTS: EnumSpd (Bitfield-Mask: 0x03) */ -#define USB_DSTS_ErrticErr_Pos \ - (3UL) /*!< USB DSTS: ErrticErr (Bit 3) */ -#define USB_DSTS_ErrticErr_Msk \ - (0x8UL) /*!< USB DSTS: ErrticErr (Bitfield-Mask: 0x01) */ -#define USB_DSTS_SOFFN_Pos (8UL) /*!< USB DSTS: SOFFN (Bit 8) */ -#define USB_DSTS_SOFFN_Msk \ - (0x3fff00UL) /*!< USB DSTS: SOFFN (Bitfield-Mask: 0x3fff) */ - -/* --------------------------------- USB_DIEPMSK -------------------------------- */ -#define USB_DIEPMSK_XferComplMsk_Pos \ - (0UL) /*!< USB DIEPMSK: XferComplMsk (Bit 0) */ -#define USB_DIEPMSK_XferComplMsk_Msk \ - (0x1UL) /*!< USB DIEPMSK: XferComplMsk (Bitfield-Mask: 0x01) */ -#define USB_DIEPMSK_EPDisbldMsk_Pos \ - (1UL) /*!< USB DIEPMSK: EPDisbldMsk (Bit 1) */ -#define USB_DIEPMSK_EPDisbldMsk_Msk \ - (0x2UL) /*!< USB DIEPMSK: EPDisbldMsk (Bitfield-Mask: 0x01) */ -#define USB_DIEPMSK_AHBErrMsk_Pos \ - (2UL) /*!< USB DIEPMSK: AHBErrMsk (Bit 2) */ -#define USB_DIEPMSK_AHBErrMsk_Msk \ - (0x4UL) /*!< USB DIEPMSK: AHBErrMsk (Bitfield-Mask: 0x01) */ -#define USB_DIEPMSK_TimeOUTMsk_Pos \ - (3UL) /*!< USB DIEPMSK: TimeOUTMsk (Bit 3) */ -#define USB_DIEPMSK_TimeOUTMsk_Msk \ - (0x8UL) /*!< USB DIEPMSK: TimeOUTMsk (Bitfield-Mask: 0x01) */ -#define USB_DIEPMSK_INTknTXFEmpMsk_Pos \ - (4UL) /*!< USB DIEPMSK: INTknTXFEmpMsk (Bit 4) */ -#define USB_DIEPMSK_INTknTXFEmpMsk_Msk \ - (0x10UL) /*!< USB DIEPMSK: INTknTXFEmpMsk (Bitfield-Mask: 0x01) */ -#define USB_DIEPMSK_INEPNakEffMsk_Pos \ - (6UL) /*!< USB DIEPMSK: INEPNakEffMsk (Bit 6) */ -#define USB_DIEPMSK_INEPNakEffMsk_Msk \ - (0x40UL) /*!< USB DIEPMSK: INEPNakEffMsk (Bitfield-Mask: 0x01) */ -#define USB_DIEPMSK_TxfifoUndrnMsk_Pos \ - (8UL) /*!< USB DIEPMSK: TxfifoUndrnMsk (Bit 8) */ -#define USB_DIEPMSK_TxfifoUndrnMsk_Msk \ - (0x100UL) /*!< USB DIEPMSK: TxfifoUndrnMsk (Bitfield-Mask: 0x01) */ -#define USB_DIEPMSK_BNAInIntrMsk_Pos \ - (9UL) /*!< USB DIEPMSK: BNAInIntrMsk (Bit 9) */ -#define USB_DIEPMSK_BNAInIntrMsk_Msk \ - (0x200UL) /*!< USB DIEPMSK: BNAInIntrMsk (Bitfield-Mask: 0x01) */ -#define USB_DIEPMSK_NAKMsk_Pos \ - (13UL) /*!< USB DIEPMSK: NAKMsk (Bit 13) */ -#define USB_DIEPMSK_NAKMsk_Msk \ - (0x2000UL) /*!< USB DIEPMSK: NAKMsk (Bitfield-Mask: 0x01) */ - -/* --------------------------------- USB_DOEPMSK -------------------------------- */ -#define USB_DOEPMSK_XferComplMsk_Pos \ - (0UL) /*!< USB DOEPMSK: XferComplMsk (Bit 0) */ -#define USB_DOEPMSK_XferComplMsk_Msk \ - (0x1UL) /*!< USB DOEPMSK: XferComplMsk (Bitfield-Mask: 0x01) */ -#define USB_DOEPMSK_EPDisbldMsk_Pos \ - (1UL) /*!< USB DOEPMSK: EPDisbldMsk (Bit 1) */ -#define USB_DOEPMSK_EPDisbldMsk_Msk \ - (0x2UL) /*!< USB DOEPMSK: EPDisbldMsk (Bitfield-Mask: 0x01) */ -#define USB_DOEPMSK_AHBErrMsk_Pos \ - (2UL) /*!< USB DOEPMSK: AHBErrMsk (Bit 2) */ -#define USB_DOEPMSK_AHBErrMsk_Msk \ - (0x4UL) /*!< USB DOEPMSK: AHBErrMsk (Bitfield-Mask: 0x01) */ -#define USB_DOEPMSK_SetUPMsk_Pos \ - (3UL) /*!< USB DOEPMSK: SetUPMsk (Bit 3) */ -#define USB_DOEPMSK_SetUPMsk_Msk \ - (0x8UL) /*!< USB DOEPMSK: SetUPMsk (Bitfield-Mask: 0x01) */ -#define USB_DOEPMSK_OUTTknEPdisMsk_Pos \ - (4UL) /*!< USB DOEPMSK: OUTTknEPdisMsk (Bit 4) */ -#define USB_DOEPMSK_OUTTknEPdisMsk_Msk \ - (0x10UL) /*!< USB DOEPMSK: OUTTknEPdisMsk (Bitfield-Mask: 0x01) */ -#define USB_DOEPMSK_Back2BackSETup_Pos \ - (6UL) /*!< USB DOEPMSK: Back2BackSETup (Bit 6) */ -#define USB_DOEPMSK_Back2BackSETup_Msk \ - (0x40UL) /*!< USB DOEPMSK: Back2BackSETup (Bitfield-Mask: 0x01) */ -#define USB_DOEPMSK_OutPktErrMsk_Pos \ - (8UL) /*!< USB DOEPMSK: OutPktErrMsk (Bit 8) */ -#define USB_DOEPMSK_OutPktErrMsk_Msk \ - (0x100UL) /*!< USB DOEPMSK: OutPktErrMsk (Bitfield-Mask: 0x01) */ -#define USB_DOEPMSK_BnaOutIntrMsk_Pos \ - (9UL) /*!< USB DOEPMSK: BnaOutIntrMsk (Bit 9) */ -#define USB_DOEPMSK_BnaOutIntrMsk_Msk \ - (0x200UL) /*!< USB DOEPMSK: BnaOutIntrMsk (Bitfield-Mask: 0x01) */ -#define USB_DOEPMSK_BbleErrMsk_Pos \ - (12UL) /*!< USB DOEPMSK: BbleErrMsk (Bit 12) */ -#define USB_DOEPMSK_BbleErrMsk_Msk \ - (0x1000UL) /*!< USB DOEPMSK: BbleErrMsk (Bitfield-Mask: 0x01) */ -#define USB_DOEPMSK_NAKMsk_Pos \ - (13UL) /*!< USB DOEPMSK: NAKMsk (Bit 13) */ -#define USB_DOEPMSK_NAKMsk_Msk \ - (0x2000UL) /*!< USB DOEPMSK: NAKMsk (Bitfield-Mask: 0x01) */ -#define USB_DOEPMSK_NYETMsk_Pos \ - (14UL) /*!< USB DOEPMSK: NYETMsk (Bit 14) */ -#define USB_DOEPMSK_NYETMsk_Msk \ - (0x4000UL) /*!< USB DOEPMSK: NYETMsk (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- USB_DAINT --------------------------------- */ -#define USB_DAINT_InEpInt_Pos \ - (0UL) /*!< USB DAINT: InEpInt (Bit 0) */ -#define USB_DAINT_InEpInt_Msk \ - (0xffffUL) /*!< USB DAINT: InEpInt (Bitfield-Mask: 0xffff) */ -#define USB_DAINT_OutEPInt_Pos \ - (16UL) /*!< USB DAINT: OutEPInt (Bit 16) */ -#define USB_DAINT_OutEPInt_Msk \ - (0xffff0000UL) /*!< USB DAINT: OutEPInt (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- USB_DAINTMSK -------------------------------- */ -#define USB_DAINTMSK_InEpMsk_Pos \ - (0UL) /*!< USB DAINTMSK: InEpMsk (Bit 0) */ -#define USB_DAINTMSK_InEpMsk_Msk \ - (0xffffUL) /*!< USB DAINTMSK: InEpMsk (Bitfield-Mask: 0xffff) */ -#define USB_DAINTMSK_OutEpMsk_Pos \ - (16UL) /*!< USB DAINTMSK: OutEpMsk (Bit 16) */ -#define USB_DAINTMSK_OutEpMsk_Msk \ - (0xffff0000UL) /*!< USB DAINTMSK: OutEpMsk (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- USB_DVBUSDIS -------------------------------- */ -#define USB_DVBUSDIS_DVBUSDis_Pos \ - (0UL) /*!< USB DVBUSDIS: DVBUSDis (Bit 0) */ -#define USB_DVBUSDIS_DVBUSDis_Msk \ - (0xffffUL) /*!< USB DVBUSDIS: DVBUSDis (Bitfield-Mask: 0xffff) */ - -/* ------------------------------- USB_DVBUSPULSE ------------------------------- */ -#define USB_DVBUSPULSE_DVBUSPulse_Pos \ - (0UL) /*!< USB DVBUSPULSE: DVBUSPulse (Bit 0) */ -#define USB_DVBUSPULSE_DVBUSPulse_Msk \ - (0xfffUL) /*!< USB DVBUSPULSE: DVBUSPulse (Bitfield-Mask: 0xfff) */ - -/* ------------------------------- USB_DIEPEMPMSK ------------------------------- */ -#define USB_DIEPEMPMSK_InEpTxfEmpMsk_Pos \ - (0UL) /*!< USB DIEPEMPMSK: InEpTxfEmpMsk (Bit 0) */ -#define USB_DIEPEMPMSK_InEpTxfEmpMsk_Msk \ - (0xffffUL) /*!< USB DIEPEMPMSK: InEpTxfEmpMsk (Bitfield-Mask: 0xffff) */ - -/* --------------------------------- USB_PCGCCTL -------------------------------- */ -#define USB_PCGCCTL_StopPclk_Pos \ - (0UL) /*!< USB PCGCCTL: StopPclk (Bit 0) */ -#define USB_PCGCCTL_StopPclk_Msk \ - (0x1UL) /*!< USB PCGCCTL: StopPclk (Bitfield-Mask: 0x01) */ -#define USB_PCGCCTL_GateHclk_Pos \ - (1UL) /*!< USB PCGCCTL: GateHclk (Bit 1) */ -#define USB_PCGCCTL_GateHclk_Msk \ - (0x2UL) /*!< USB PCGCCTL: GateHclk (Bitfield-Mask: 0x01) */ - -/* ================================================================================ */ -/* ================ struct 'USB0_EP0' Position & Mask ================ */ -/* ================================================================================ */ - -/* ------------------------------ USB_EP_DIEPCTL0 ----------------------------- */ -#define USB_EP_DIEPCTL0_MPS_Pos \ - (0UL) /*!< USB0_EP0 DIEPCTL0: MPS (Bit 0) */ -#define USB_EP_DIEPCTL0_MPS_Msk \ - (0x3UL) /*!< USB0_EP0 DIEPCTL0: MPS (Bitfield-Mask: 0x03) */ -#define USB_EP_DIEPCTL0_USBActEP_Pos \ - (15UL) /*!< USB0_EP0 DIEPCTL0: USBActEP (Bit 15) */ -#define USB_EP_DIEPCTL0_USBActEP_Msk \ - (0x8000UL) /*!< USB0_EP0 DIEPCTL0: USBActEP (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL0_NAKSts_Pos \ - (17UL) /*!< USB0_EP0 DIEPCTL0: NAKSts (Bit 17) */ -#define USB_EP_DIEPCTL0_NAKSts_Msk \ - (0x20000UL) /*!< USB0_EP0 DIEPCTL0: NAKSts (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL0_EPType_Pos \ - (18UL) /*!< USB0_EP0 DIEPCTL0: EPType (Bit 18) */ -#define USB_EP_DIEPCTL0_EPType_Msk \ - (0xc0000UL) /*!< USB0_EP0 DIEPCTL0: EPType (Bitfield-Mask: 0x03) */ -#define USB_EP_DIEPCTL0_Stall_Pos \ - (21UL) /*!< USB0_EP0 DIEPCTL0: Stall (Bit 21) */ -#define USB_EP_DIEPCTL0_Stall_Msk \ - (0x200000UL) /*!< USB0_EP0 DIEPCTL0: Stall (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL0_TxFNum_Pos \ - (22UL) /*!< USB0_EP0 DIEPCTL0: TxFNum (Bit 22) */ -#define USB_EP_DIEPCTL0_TxFNum_Msk \ - (0x3c00000UL) /*!< USB0_EP0 DIEPCTL0: TxFNum (Bitfield-Mask: 0x0f) */ -#define USB_EP_DIEPCTL0_CNAK_Pos \ - (26UL) /*!< USB0_EP0 DIEPCTL0: CNAK (Bit 26) */ -#define USB_EP_DIEPCTL0_CNAK_Msk \ - (0x4000000UL) /*!< USB0_EP0 DIEPCTL0: CNAK (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL0_SNAK_Pos \ - (27UL) /*!< USB0_EP0 DIEPCTL0: SNAK (Bit 27) */ -#define USB_EP_DIEPCTL0_SNAK_Msk \ - (0x8000000UL) /*!< USB0_EP0 DIEPCTL0: SNAK (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL0_EPDis_Pos \ - (30UL) /*!< USB0_EP0 DIEPCTL0: EPDis (Bit 30) */ -#define USB_EP_DIEPCTL0_EPDis_Msk \ - (0x40000000UL) /*!< USB0_EP0 DIEPCTL0: EPDis (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL0_EPEna_Pos \ - (31UL) /*!< USB0_EP0 DIEPCTL0: EPEna (Bit 31) */ -#define USB_EP_DIEPCTL0_EPEna_Msk \ - (0x80000000UL) /*!< USB0_EP0 DIEPCTL0: EPEna (Bitfield-Mask: 0x01) */ - -/* ------------------------------ USB_EP_DIEPINT0 ----------------------------- */ -#define USB_EP_DIEPINT0_XferCompl_Pos \ - (0UL) /*!< USB0_EP0 DIEPINT0: XferCompl (Bit 0) */ -#define USB_EP_DIEPINT0_XferCompl_Msk \ - (0x1UL) /*!< USB0_EP0 DIEPINT0: XferCompl (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPINT0_EPDisbld_Pos \ - (1UL) /*!< USB0_EP0 DIEPINT0: EPDisbld (Bit 1) */ -#define USB_EP_DIEPINT0_EPDisbld_Msk \ - (0x2UL) /*!< USB0_EP0 DIEPINT0: EPDisbld (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPINT0_AHBErr_Pos \ - (2UL) /*!< USB0_EP0 DIEPINT0: AHBErr (Bit 2) */ -#define USB_EP_DIEPINT0_AHBErr_Msk \ - (0x4UL) /*!< USB0_EP0 DIEPINT0: AHBErr (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPINT0_TimeOUT_Pos \ - (3UL) /*!< USB0_EP0 DIEPINT0: TimeOUT (Bit 3) */ -#define USB_EP_DIEPINT0_TimeOUT_Msk \ - (0x8UL) /*!< USB0_EP0 DIEPINT0: TimeOUT (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPINT0_INTknTXFEmp_Pos \ - (4UL) /*!< USB0_EP0 DIEPINT0: INTknTXFEmp (Bit 4) */ -#define USB_EP_DIEPINT0_INTknTXFEmp_Msk \ - (0x10UL) /*!< USB0_EP0 DIEPINT0: INTknTXFEmp (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPINT0_INEPNakEff_Pos \ - (6UL) /*!< USB0_EP0 DIEPINT0: INEPNakEff (Bit 6) */ -#define USB_EP_DIEPINT0_INEPNakEff_Msk \ - (0x40UL) /*!< USB0_EP0 DIEPINT0: INEPNakEff (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPINT0_TxFEmp_Pos \ - (7UL) /*!< USB0_EP0 DIEPINT0: TxFEmp (Bit 7) */ -#define USB_EP_DIEPINT0_TxFEmp_Msk \ - (0x80UL) /*!< USB0_EP0 DIEPINT0: TxFEmp (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPINT0_BNAIntr_Pos \ - (9UL) /*!< USB0_EP0 DIEPINT0: BNAIntr (Bit 9) */ -#define USB_EP_DIEPINT0_BNAIntr_Msk \ - (0x200UL) /*!< USB0_EP0 DIEPINT0: BNAIntr (Bitfield-Mask: 0x01) */ - -/* ----------------------------- USB_EP_DIEPTSIZ0 ----------------------------- */ -#define USB_EP_DIEPTSIZ0_XferSize_Pos \ - (0UL) /*!< USB0_EP0 DIEPTSIZ0: XferSize (Bit 0) */ -#define USB_EP_DIEPTSIZ0_XferSize_Msk \ - (0x7fUL) /*!< USB0_EP0 DIEPTSIZ0: XferSize (Bitfield-Mask: 0x7f) */ -#define USB_EP_DIEPTSIZ0_PktCnt_Pos \ - (19UL) /*!< USB0_EP0 DIEPTSIZ0: PktCnt (Bit 19) */ -#define USB_EP_DIEPTSIZ0_PktCnt_Msk \ - (0x180000UL) /*!< USB0_EP0 DIEPTSIZ0: PktCnt (Bitfield-Mask: 0x03) */ - -/* ------------------------------ USB_EP_DIEPDMA0 ----------------------------- */ -#define USB_EP_DIEPDMA0_DMAAddr_Pos \ - (0UL) /*!< USB0_EP0 DIEPDMA0: DMAAddr (Bit 0) */ -#define USB_EP_DIEPDMA0_DMAAddr_Msk \ - (0xffffffffUL) /*!< USB0_EP0 DIEPDMA0: DMAAddr (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------ USB_EP_DTXFSTS0 ----------------------------- */ -#define USB_EP_DTXFSTS0_INEPTxFSpcAvail_Pos \ - (0UL) /*!< USB0_EP0 DTXFSTS0: INEPTxFSpcAvail (Bit 0) */ -#define USB_EP_DTXFSTS0_INEPTxFSpcAvail_Msk \ - (0xffffUL) /*!< USB0_EP0 DTXFSTS0: INEPTxFSpcAvail (Bitfield-Mask: 0xffff) */ - -/* ----------------------------- USB_EP_DIEPDMAB0 ----------------------------- */ -#define USB_EP_DIEPDMAB0_DMABufferAddr_Pos \ - (0UL) /*!< USB0_EP0 DIEPDMAB0: DMABufferAddr (Bit 0) */ -#define USB_EP_DIEPDMAB0_DMABufferAddr_Msk \ - (0xffffffffUL) /*!< USB0_EP0 DIEPDMAB0: DMABufferAddr (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------ USB_EP_DOEPCTL0 ----------------------------- */ -#define USB_EP_DOEPCTL0_MPS_Pos \ - (0UL) /*!< USB0_EP0 DOEPCTL0: MPS (Bit 0) */ -#define USB_EP_DOEPCTL0_MPS_Msk \ - (0x3UL) /*!< USB0_EP0 DOEPCTL0: MPS (Bitfield-Mask: 0x03) */ -#define USB_EP_DOEPCTL0_USBActEP_Pos \ - (15UL) /*!< USB0_EP0 DOEPCTL0: USBActEP (Bit 15) */ -#define USB_EP_DOEPCTL0_USBActEP_Msk \ - (0x8000UL) /*!< USB0_EP0 DOEPCTL0: USBActEP (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL0_NAKSts_Pos \ - (17UL) /*!< USB0_EP0 DOEPCTL0: NAKSts (Bit 17) */ -#define USB_EP_DOEPCTL0_NAKSts_Msk \ - (0x20000UL) /*!< USB0_EP0 DOEPCTL0: NAKSts (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL0_EPType_Pos \ - (18UL) /*!< USB0_EP0 DOEPCTL0: EPType (Bit 18) */ -#define USB_EP_DOEPCTL0_EPType_Msk \ - (0xc0000UL) /*!< USB0_EP0 DOEPCTL0: EPType (Bitfield-Mask: 0x03) */ -#define USB_EP_DOEPCTL0_Snp_Pos \ - (20UL) /*!< USB0_EP0 DOEPCTL0: Snp (Bit 20) */ -#define USB_EP_DOEPCTL0_Snp_Msk \ - (0x100000UL) /*!< USB0_EP0 DOEPCTL0: Snp (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL0_Stall_Pos \ - (21UL) /*!< USB0_EP0 DOEPCTL0: Stall (Bit 21) */ -#define USB_EP_DOEPCTL0_Stall_Msk \ - (0x200000UL) /*!< USB0_EP0 DOEPCTL0: Stall (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL0_CNAK_Pos \ - (26UL) /*!< USB0_EP0 DOEPCTL0: CNAK (Bit 26) */ -#define USB_EP_DOEPCTL0_CNAK_Msk \ - (0x4000000UL) /*!< USB0_EP0 DOEPCTL0: CNAK (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL0_SNAK_Pos \ - (27UL) /*!< USB0_EP0 DOEPCTL0: SNAK (Bit 27) */ -#define USB_EP_DOEPCTL0_SNAK_Msk \ - (0x8000000UL) /*!< USB0_EP0 DOEPCTL0: SNAK (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL0_EPDis_Pos \ - (30UL) /*!< USB0_EP0 DOEPCTL0: EPDis (Bit 30) */ -#define USB_EP_DOEPCTL0_EPDis_Msk \ - (0x40000000UL) /*!< USB0_EP0 DOEPCTL0: EPDis (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL0_EPEna_Pos \ - (31UL) /*!< USB0_EP0 DOEPCTL0: EPEna (Bit 31) */ -#define USB_EP_DOEPCTL0_EPEna_Msk \ - (0x80000000UL) /*!< USB0_EP0 DOEPCTL0: EPEna (Bitfield-Mask: 0x01) */ - -/* ------------------------------ USB_EP_DOEPINT0 ----------------------------- */ -#define USB_EP_DOEPINT0_XferCompl_Pos \ - (0UL) /*!< USB0_EP0 DOEPINT0: XferCompl (Bit 0) */ -#define USB_EP_DOEPINT0_XferCompl_Msk \ - (0x1UL) /*!< USB0_EP0 DOEPINT0: XferCompl (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPINT0_EPDisbld_Pos \ - (1UL) /*!< USB0_EP0 DOEPINT0: EPDisbld (Bit 1) */ -#define USB_EP_DOEPINT0_EPDisbld_Msk \ - (0x2UL) /*!< USB0_EP0 DOEPINT0: EPDisbld (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPINT0_AHBErr_Pos \ - (2UL) /*!< USB0_EP0 DOEPINT0: AHBErr (Bit 2) */ -#define USB_EP_DOEPINT0_AHBErr_Msk \ - (0x4UL) /*!< USB0_EP0 DOEPINT0: AHBErr (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPINT0_SetUp_Pos \ - (3UL) /*!< USB0_EP0 DOEPINT0: SetUp (Bit 3) */ -#define USB_EP_DOEPINT0_SetUp_Msk \ - (0x8UL) /*!< USB0_EP0 DOEPINT0: SetUp (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPINT0_OUTTknEPdis_Pos \ - (4UL) /*!< USB0_EP0 DOEPINT0: OUTTknEPdis (Bit 4) */ -#define USB_EP_DOEPINT0_OUTTknEPdis_Msk \ - (0x10UL) /*!< USB0_EP0 DOEPINT0: OUTTknEPdis (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPINT0_StsPhseRcvd_Pos \ - (5UL) /*!< USB0_EP0 DOEPINT0: StsPhseRcvd (Bit 5) */ -#define USB_EP_DOEPINT0_StsPhseRcvd_Msk \ - (0x20UL) /*!< USB0_EP0 DOEPINT0: StsPhseRcvd (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPINT0_Back2BackSETup_Pos \ - (6UL) /*!< USB0_EP0 DOEPINT0: Back2BackSETup (Bit 6) */ -#define USB_EP_DOEPINT0_Back2BackSETup_Msk \ - (0x40UL) /*!< USB0_EP0 DOEPINT0: Back2BackSETup (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPINT0_BNAIntr_Pos \ - (9UL) /*!< USB0_EP0 DOEPINT0: BNAIntr (Bit 9) */ -#define USB_EP_DOEPINT0_BNAIntr_Msk \ - (0x200UL) /*!< USB0_EP0 DOEPINT0: BNAIntr (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPINT0_PktDrpSts_Pos \ - (11UL) /*!< USB0_EP0 DOEPINT0: PktDrpSts (Bit 11) */ -#define USB_EP_DOEPINT0_PktDrpSts_Msk \ - (0x800UL) /*!< USB0_EP0 DOEPINT0: PktDrpSts (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPINT0_BbleErrIntrpt_Pos \ - (12UL) /*!< USB0_EP0 DOEPINT0: BbleErrIntrpt (Bit 12) */ -#define USB_EP_DOEPINT0_BbleErrIntrpt_Msk \ - (0x1000UL) /*!< USB0_EP0 DOEPINT0: BbleErrIntrpt (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPINT0_NAKIntrpt_Pos \ - (13UL) /*!< USB0_EP0 DOEPINT0: NAKIntrpt (Bit 13) */ -#define USB_EP_DOEPINT0_NAKIntrpt_Msk \ - (0x2000UL) /*!< USB0_EP0 DOEPINT0: NAKIntrpt (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPINT0_NYETIntrpt_Pos \ - (14UL) /*!< USB0_EP0 DOEPINT0: NYETIntrpt (Bit 14) */ -#define USB_EP_DOEPINT0_NYETIntrpt_Msk \ - (0x4000UL) /*!< USB0_EP0 DOEPINT0: NYETIntrpt (Bitfield-Mask: 0x01) */ - -/* ----------------------------- USB_EP_DOEPTSIZ0 ----------------------------- */ -#define USB_EP_DOEPTSIZ0_XferSize_Pos \ - (0UL) /*!< USB0_EP0 DOEPTSIZ0: XferSize (Bit 0) */ -#define USB_EP_DOEPTSIZ0_XferSize_Msk \ - (0x7fUL) /*!< USB0_EP0 DOEPTSIZ0: XferSize (Bitfield-Mask: 0x7f) */ -#define USB_EP_DOEPTSIZ0_PktCnt_Pos \ - (19UL) /*!< USB0_EP0 DOEPTSIZ0: PktCnt (Bit 19) */ -#define USB_EP_DOEPTSIZ0_PktCnt_Msk \ - (0x180000UL) /*!< USB0_EP0 DOEPTSIZ0: PktCnt (Bitfield-Mask: 0x03) */ -#define USB_EP_DOEPTSIZ0_SUPCnt_Pos \ - (29UL) /*!< USB0_EP0 DOEPTSIZ0: SUPCnt (Bit 29) */ -#define USB_EP_DOEPTSIZ0_SUPCnt_Msk \ - (0x60000000UL) /*!< USB0_EP0 DOEPTSIZ0: SUPCnt (Bitfield-Mask: 0x03) */ - -/* ------------------------------ USB_EP_DOEPDMA0 ----------------------------- */ -#define USB_EP_DOEPDMA0_DMAAddr_Pos \ - (0UL) /*!< USB0_EP0 DOEPDMA0: DMAAddr (Bit 0) */ -#define USB_EP_DOEPDMA0_DMAAddr_Msk \ - (0xffffffffUL) /*!< USB0_EP0 DOEPDMA0: DMAAddr (Bitfield-Mask: 0xffffffff) */ - -/* ----------------------------- USB_EP_DOEPDMAB0 ----------------------------- */ -#define USB_EP_DOEPDMAB0_DMABufferAddr_Pos \ - (0UL) /*!< USB0_EP0 DOEPDMAB0: DMABufferAddr (Bit 0) */ -#define USB_EP_DOEPDMAB0_DMABufferAddr_Msk \ - (0xffffffffUL) /*!< USB0_EP0 DOEPDMAB0: DMABufferAddr (Bitfield-Mask: 0xffffffff) */ - -/* ================================================================================ */ -/* ================ Group 'USB_EP' Position & Mask ================ */ -/* ================================================================================ */ - -/* --------------------------- USB_EP_DIEPCTL_ISOCONT --------------------------- */ -#define USB_EP_DIEPCTL_ISOCONT_MPS_Pos \ - (0UL) /*!< USB_EP DIEPCTL_ISOCONT: MPS (Bit 0) */ -#define USB_EP_DIEPCTL_ISOCONT_MPS_Msk \ - (0x7ffUL) /*!< USB_EP DIEPCTL_ISOCONT: MPS (Bitfield-Mask: 0x7ff) */ -#define USB_EP_DIEPCTL_ISOCONT_USBActEP_Pos \ - (15UL) /*!< USB_EP DIEPCTL_ISOCONT: USBActEP (Bit 15) */ -#define USB_EP_DIEPCTL_ISOCONT_USBActEP_Msk \ - (0x8000UL) /*!< USB_EP DIEPCTL_ISOCONT: USBActEP (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL_ISOCONT_EO_FrNum_Pos \ - (16UL) /*!< USB_EP DIEPCTL_ISOCONT: EO_FrNum (Bit 16) */ -#define USB_EP_DIEPCTL_ISOCONT_EO_FrNum_Msk \ - (0x10000UL) /*!< USB_EP DIEPCTL_ISOCONT: EO_FrNum (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL_ISOCONT_NAKSts_Pos \ - (17UL) /*!< USB_EP DIEPCTL_ISOCONT: NAKSts (Bit 17) */ -#define USB_EP_DIEPCTL_ISOCONT_NAKSts_Msk \ - (0x20000UL) /*!< USB_EP DIEPCTL_ISOCONT: NAKSts (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL_ISOCONT_EPType_Pos \ - (18UL) /*!< USB_EP DIEPCTL_ISOCONT: EPType (Bit 18) */ -#define USB_EP_DIEPCTL_ISOCONT_EPType_Msk \ - (0xc0000UL) /*!< USB_EP DIEPCTL_ISOCONT: EPType (Bitfield-Mask: 0x03) */ -#define USB_EP_DIEPCTL_ISOCONT_Snp_Pos \ - (20UL) /*!< USB_EP DIEPCTL_ISOCONT: Snp (Bit 20) */ -#define USB_EP_DIEPCTL_ISOCONT_Snp_Msk \ - (0x100000UL) /*!< USB_EP DIEPCTL_ISOCONT: Snp (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL_ISOCONT_Stall_Pos \ - (21UL) /*!< USB_EP DIEPCTL_ISOCONT: Stall (Bit 21) */ -#define USB_EP_DIEPCTL_ISOCONT_Stall_Msk \ - (0x200000UL) /*!< USB_EP DIEPCTL_ISOCONT: Stall (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL_ISOCONT_TxFNum_Pos \ - (22UL) /*!< USB_EP DIEPCTL_ISOCONT: TxFNum (Bit 22) */ -#define USB_EP_DIEPCTL_ISOCONT_TxFNum_Msk \ - (0x3c00000UL) /*!< USB_EP DIEPCTL_ISOCONT: TxFNum (Bitfield-Mask: 0x0f) */ -#define USB_EP_DIEPCTL_ISOCONT_CNAK_Pos \ - (26UL) /*!< USB_EP DIEPCTL_ISOCONT: CNAK (Bit 26) */ -#define USB_EP_DIEPCTL_ISOCONT_CNAK_Msk \ - (0x4000000UL) /*!< USB_EP DIEPCTL_ISOCONT: CNAK (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL_ISOCONT_SNAK_Pos \ - (27UL) /*!< USB_EP DIEPCTL_ISOCONT: SNAK (Bit 27) */ -#define USB_EP_DIEPCTL_ISOCONT_SNAK_Msk \ - (0x8000000UL) /*!< USB_EP DIEPCTL_ISOCONT: SNAK (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL_ISOCONT_SetEvenFr_Pos \ - (28UL) /*!< USB_EP DIEPCTL_ISOCONT: SetEvenFr (Bit 28) */ -#define USB_EP_DIEPCTL_ISOCONT_SetEvenFr_Msk \ - (0x10000000UL) /*!< USB_EP DIEPCTL_ISOCONT: SetEvenFr (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL_ISOCONT_SetOddFr_Pos \ - (29UL) /*!< USB_EP DIEPCTL_ISOCONT: SetOddFr (Bit 29) */ -#define USB_EP_DIEPCTL_ISOCONT_SetOddFr_Msk \ - (0x20000000UL) /*!< USB_EP DIEPCTL_ISOCONT: SetOddFr (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL_ISOCONT_EPDis_Pos \ - (30UL) /*!< USB_EP DIEPCTL_ISOCONT: EPDis (Bit 30) */ -#define USB_EP_DIEPCTL_ISOCONT_EPDis_Msk \ - (0x40000000UL) /*!< USB_EP DIEPCTL_ISOCONT: EPDis (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL_ISOCONT_EPEna_Pos \ - (31UL) /*!< USB_EP DIEPCTL_ISOCONT: EPEna (Bit 31) */ -#define USB_EP_DIEPCTL_ISOCONT_EPEna_Msk \ - (0x80000000UL) /*!< USB_EP DIEPCTL_ISOCONT: EPEna (Bitfield-Mask: 0x01) */ - -/* --------------------------- USB_EP_DIEPCTL_INTBULK --------------------------- */ -#define USB_EP_DIEPCTL_INTBULK_MPS_Pos \ - (0UL) /*!< USB_EP DIEPCTL_INTBULK: MPS (Bit 0) */ -#define USB_EP_DIEPCTL_INTBULK_MPS_Msk \ - (0x7ffUL) /*!< USB_EP DIEPCTL_INTBULK: MPS (Bitfield-Mask: 0x7ff) */ -#define USB_EP_DIEPCTL_INTBULK_USBActEP_Pos \ - (15UL) /*!< USB_EP DIEPCTL_INTBULK: USBActEP (Bit 15) */ -#define USB_EP_DIEPCTL_INTBULK_USBActEP_Msk \ - (0x8000UL) /*!< USB_EP DIEPCTL_INTBULK: USBActEP (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL_INTBULK_DPID_Pos \ - (16UL) /*!< USB_EP DIEPCTL_INTBULK: DPID (Bit 16) */ -#define USB_EP_DIEPCTL_INTBULK_DPID_Msk \ - (0x10000UL) /*!< USB_EP DIEPCTL_INTBULK: DPID (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL_INTBULK_NAKSts_Pos \ - (17UL) /*!< USB_EP DIEPCTL_INTBULK: NAKSts (Bit 17) */ -#define USB_EP_DIEPCTL_INTBULK_NAKSts_Msk \ - (0x20000UL) /*!< USB_EP DIEPCTL_INTBULK: NAKSts (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL_INTBULK_EPType_Pos \ - (18UL) /*!< USB_EP DIEPCTL_INTBULK: EPType (Bit 18) */ -#define USB_EP_DIEPCTL_INTBULK_EPType_Msk \ - (0xc0000UL) /*!< USB_EP DIEPCTL_INTBULK: EPType (Bitfield-Mask: 0x03) */ -#define USB_EP_DIEPCTL_INTBULK_Snp_Pos \ - (20UL) /*!< USB_EP DIEPCTL_INTBULK: Snp (Bit 20) */ -#define USB_EP_DIEPCTL_INTBULK_Snp_Msk \ - (0x100000UL) /*!< USB_EP DIEPCTL_INTBULK: Snp (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL_INTBULK_Stall_Pos \ - (21UL) /*!< USB_EP DIEPCTL_INTBULK: Stall (Bit 21) */ -#define USB_EP_DIEPCTL_INTBULK_Stall_Msk \ - (0x200000UL) /*!< USB_EP DIEPCTL_INTBULK: Stall (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL_INTBULK_TxFNum_Pos \ - (22UL) /*!< USB_EP DIEPCTL_INTBULK: TxFNum (Bit 22) */ -#define USB_EP_DIEPCTL_INTBULK_TxFNum_Msk \ - (0x3c00000UL) /*!< USB_EP DIEPCTL_INTBULK: TxFNum (Bitfield-Mask: 0x0f) */ -#define USB_EP_DIEPCTL_INTBULK_CNAK_Pos \ - (26UL) /*!< USB_EP DIEPCTL_INTBULK: CNAK (Bit 26) */ -#define USB_EP_DIEPCTL_INTBULK_CNAK_Msk \ - (0x4000000UL) /*!< USB_EP DIEPCTL_INTBULK: CNAK (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL_INTBULK_SNAK_Pos \ - (27UL) /*!< USB_EP DIEPCTL_INTBULK: SNAK (Bit 27) */ -#define USB_EP_DIEPCTL_INTBULK_SNAK_Msk \ - (0x8000000UL) /*!< USB_EP DIEPCTL_INTBULK: SNAK (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL_INTBULK_SetD0PID_Pos \ - (28UL) /*!< USB_EP DIEPCTL_INTBULK: SetD0PID (Bit 28) */ -#define USB_EP_DIEPCTL_INTBULK_SetD0PID_Msk \ - (0x10000000UL) /*!< USB_EP DIEPCTL_INTBULK: SetD0PID (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL_INTBULK_SetD1PID_Pos \ - (29UL) /*!< USB_EP DIEPCTL_INTBULK: SetD1PID (Bit 29) */ -#define USB_EP_DIEPCTL_INTBULK_SetD1PID_Msk \ - (0x20000000UL) /*!< USB_EP DIEPCTL_INTBULK: SetD1PID (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL_INTBULK_EPDis_Pos \ - (30UL) /*!< USB_EP DIEPCTL_INTBULK: EPDis (Bit 30) */ -#define USB_EP_DIEPCTL_INTBULK_EPDis_Msk \ - (0x40000000UL) /*!< USB_EP DIEPCTL_INTBULK: EPDis (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL_INTBULK_EPEna_Pos \ - (31UL) /*!< USB_EP DIEPCTL_INTBULK: EPEna (Bit 31) */ -#define USB_EP_DIEPCTL_INTBULK_EPEna_Msk \ - (0x80000000UL) /*!< USB_EP DIEPCTL_INTBULK: EPEna (Bitfield-Mask: 0x01) */ - -/* ------------------------------- USB_EP_DIEPINT ------------------------------- */ -#define USB_EP_DIEPINT_XferCompl_Pos \ - (0UL) /*!< USB_EP DIEPINT: XferCompl (Bit 0) */ -#define USB_EP_DIEPINT_XferCompl_Msk \ - (0x1UL) /*!< USB_EP DIEPINT: XferCompl (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPINT_EPDisbld_Pos \ - (1UL) /*!< USB_EP DIEPINT: EPDisbld (Bit 1) */ -#define USB_EP_DIEPINT_EPDisbld_Msk \ - (0x2UL) /*!< USB_EP DIEPINT: EPDisbld (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPINT_AHBErr_Pos \ - (2UL) /*!< USB_EP DIEPINT: AHBErr (Bit 2) */ -#define USB_EP_DIEPINT_AHBErr_Msk \ - (0x4UL) /*!< USB_EP DIEPINT: AHBErr (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPINT_TimeOUT_Pos \ - (3UL) /*!< USB_EP DIEPINT: TimeOUT (Bit 3) */ -#define USB_EP_DIEPINT_TimeOUT_Msk \ - (0x8UL) /*!< USB_EP DIEPINT: TimeOUT (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPINT_INTknTXFEmp_Pos \ - (4UL) /*!< USB_EP DIEPINT: INTknTXFEmp (Bit 4) */ -#define USB_EP_DIEPINT_INTknTXFEmp_Msk \ - (0x10UL) /*!< USB_EP DIEPINT: INTknTXFEmp (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPINT_INEPNakEff_Pos \ - (6UL) /*!< USB_EP DIEPINT: INEPNakEff (Bit 6) */ -#define USB_EP_DIEPINT_INEPNakEff_Msk \ - (0x40UL) /*!< USB_EP DIEPINT: INEPNakEff (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPINT_TxFEmp_Pos \ - (7UL) /*!< USB_EP DIEPINT: TxFEmp (Bit 7) */ -#define USB_EP_DIEPINT_TxFEmp_Msk \ - (0x80UL) /*!< USB_EP DIEPINT: TxFEmp (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPINT_BNAIntr_Pos \ - (9UL) /*!< USB_EP DIEPINT: BNAIntr (Bit 9) */ -#define USB_EP_DIEPINT_BNAIntr_Msk \ - (0x200UL) /*!< USB_EP DIEPINT: BNAIntr (Bitfield-Mask: 0x01) */ - -/* ------------------------------- USB_EP_DIEPTSIZ ------------------------------ */ -#define USB_EP_DIEPTSIZ_XferSize_Pos \ - (0UL) /*!< USB_EP DIEPTSIZ: XferSize (Bit 0) */ -#define USB_EP_DIEPTSIZ_XferSize_Msk \ - (0x7ffffUL) /*!< USB_EP DIEPTSIZ: XferSize (Bitfield-Mask: 0x7ffff) */ -#define USB_EP_DIEPTSIZ_PktCnt_Pos \ - (19UL) /*!< USB_EP DIEPTSIZ: PktCnt (Bit 19) */ -#define USB_EP_DIEPTSIZ_PktCnt_Msk \ - (0x1ff80000UL) /*!< USB_EP DIEPTSIZ: PktCnt (Bitfield-Mask: 0x3ff) */ - -/* ------------------------------- USB_EP_DIEPDMA ------------------------------- */ -#define USB_EP_DIEPDMA_DMAAddr_Pos \ - (0UL) /*!< USB_EP DIEPDMA: DMAAddr (Bit 0) */ -#define USB_EP_DIEPDMA_DMAAddr_Msk \ - (0xffffffffUL) /*!< USB_EP DIEPDMA: DMAAddr (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------- USB_EP_DTXFSTS ------------------------------- */ -#define USB_EP_DTXFSTS_INEPTxFSpcAvail_Pos \ - (0UL) /*!< USB_EP DTXFSTS: INEPTxFSpcAvail (Bit 0) */ -#define USB_EP_DTXFSTS_INEPTxFSpcAvail_Msk \ - (0xffffUL) /*!< USB_EP DTXFSTS: INEPTxFSpcAvail (Bitfield-Mask: 0xffff) */ - -/* ------------------------------- USB_EP_DIEPDMAB ------------------------------ */ -#define USB_EP_DIEPDMAB_DMABufferAddr_Pos \ - (0UL) /*!< USB_EP DIEPDMAB: DMABufferAddr (Bit 0) */ -#define USB_EP_DIEPDMAB_DMABufferAddr_Msk \ - (0xffffffffUL) /*!< USB_EP DIEPDMAB: DMABufferAddr (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------- USB_EP_DOEPCTL_ISOCONT --------------------------- */ -#define USB_EP_DOEPCTL_ISOCONT_MPS_Pos \ - (0UL) /*!< USB_EP DOEPCTL_ISOCONT: MPS (Bit 0) */ -#define USB_EP_DOEPCTL_ISOCONT_MPS_Msk \ - (0x7ffUL) /*!< USB_EP DOEPCTL_ISOCONT: MPS (Bitfield-Mask: 0x7ff) */ -#define USB_EP_DOEPCTL_ISOCONT_USBActEP_Pos \ - (15UL) /*!< USB_EP DOEPCTL_ISOCONT: USBActEP (Bit 15) */ -#define USB_EP_DOEPCTL_ISOCONT_USBActEP_Msk \ - (0x8000UL) /*!< USB_EP DOEPCTL_ISOCONT: USBActEP (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL_ISOCONT_EO_FrNum_Pos \ - (16UL) /*!< USB_EP DOEPCTL_ISOCONT: EO_FrNum (Bit 16) */ -#define USB_EP_DOEPCTL_ISOCONT_EO_FrNum_Msk \ - (0x10000UL) /*!< USB_EP DOEPCTL_ISOCONT: EO_FrNum (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL_ISOCONT_NAKSts_Pos \ - (17UL) /*!< USB_EP DOEPCTL_ISOCONT: NAKSts (Bit 17) */ -#define USB_EP_DOEPCTL_ISOCONT_NAKSts_Msk \ - (0x20000UL) /*!< USB_EP DOEPCTL_ISOCONT: NAKSts (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL_ISOCONT_EPType_Pos \ - (18UL) /*!< USB_EP DOEPCTL_ISOCONT: EPType (Bit 18) */ -#define USB_EP_DOEPCTL_ISOCONT_EPType_Msk \ - (0xc0000UL) /*!< USB_EP DOEPCTL_ISOCONT: EPType (Bitfield-Mask: 0x03) */ -#define USB_EP_DOEPCTL_ISOCONT_Snp_Pos \ - (20UL) /*!< USB_EP DOEPCTL_ISOCONT: Snp (Bit 20) */ -#define USB_EP_DOEPCTL_ISOCONT_Snp_Msk \ - (0x100000UL) /*!< USB_EP DOEPCTL_ISOCONT: Snp (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL_ISOCONT_Stall_Pos \ - (21UL) /*!< USB_EP DOEPCTL_ISOCONT: Stall (Bit 21) */ -#define USB_EP_DOEPCTL_ISOCONT_Stall_Msk \ - (0x200000UL) /*!< USB_EP DOEPCTL_ISOCONT: Stall (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL_ISOCONT_TxFNum_Pos \ - (22UL) /*!< USB_EP DOEPCTL_ISOCONT: TxFNum (Bit 22) */ -#define USB_EP_DOEPCTL_ISOCONT_TxFNum_Msk \ - (0x3c00000UL) /*!< USB_EP DOEPCTL_ISOCONT: TxFNum (Bitfield-Mask: 0x0f) */ -#define USB_EP_DOEPCTL_ISOCONT_CNAK_Pos \ - (26UL) /*!< USB_EP DOEPCTL_ISOCONT: CNAK (Bit 26) */ -#define USB_EP_DOEPCTL_ISOCONT_CNAK_Msk \ - (0x4000000UL) /*!< USB_EP DOEPCTL_ISOCONT: CNAK (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL_ISOCONT_SNAK_Pos \ - (27UL) /*!< USB_EP DOEPCTL_ISOCONT: SNAK (Bit 27) */ -#define USB_EP_DOEPCTL_ISOCONT_SNAK_Msk \ - (0x8000000UL) /*!< USB_EP DOEPCTL_ISOCONT: SNAK (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL_ISOCONT_SetEvenFr_Pos \ - (28UL) /*!< USB_EP DOEPCTL_ISOCONT: SetEvenFr (Bit 28) */ -#define USB_EP_DOEPCTL_ISOCONT_SetEvenFr_Msk \ - (0x10000000UL) /*!< USB_EP DOEPCTL_ISOCONT: SetEvenFr (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL_ISOCONT_SetOddFr_Pos \ - (29UL) /*!< USB_EP DOEPCTL_ISOCONT: SetOddFr (Bit 29) */ -#define USB_EP_DOEPCTL_ISOCONT_SetOddFr_Msk \ - (0x20000000UL) /*!< USB_EP DOEPCTL_ISOCONT: SetOddFr (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL_ISOCONT_EPDis_Pos \ - (30UL) /*!< USB_EP DOEPCTL_ISOCONT: EPDis (Bit 30) */ -#define USB_EP_DOEPCTL_ISOCONT_EPDis_Msk \ - (0x40000000UL) /*!< USB_EP DOEPCTL_ISOCONT: EPDis (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL_ISOCONT_EPEna_Pos \ - (31UL) /*!< USB_EP DOEPCTL_ISOCONT: EPEna (Bit 31) */ -#define USB_EP_DOEPCTL_ISOCONT_EPEna_Msk \ - (0x80000000UL) /*!< USB_EP DOEPCTL_ISOCONT: EPEna (Bitfield-Mask: 0x01) */ - -/* --------------------------- USB_EP_DOEPCTL_INTBULK --------------------------- */ -#define USB_EP_DOEPCTL_INTBULK_MPS_Pos \ - (0UL) /*!< USB_EP DOEPCTL_INTBULK: MPS (Bit 0) */ -#define USB_EP_DOEPCTL_INTBULK_MPS_Msk \ - (0x7ffUL) /*!< USB_EP DOEPCTL_INTBULK: MPS (Bitfield-Mask: 0x7ff) */ -#define USB_EP_DOEPCTL_INTBULK_USBActEP_Pos \ - (15UL) /*!< USB_EP DOEPCTL_INTBULK: USBActEP (Bit 15) */ -#define USB_EP_DOEPCTL_INTBULK_USBActEP_Msk \ - (0x8000UL) /*!< USB_EP DOEPCTL_INTBULK: USBActEP (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL_INTBULK_DPID_Pos \ - (16UL) /*!< USB_EP DOEPCTL_INTBULK: DPID (Bit 16) */ -#define USB_EP_DOEPCTL_INTBULK_DPID_Msk \ - (0x10000UL) /*!< USB_EP DOEPCTL_INTBULK: DPID (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL_INTBULK_NAKSts_Pos \ - (17UL) /*!< USB_EP DOEPCTL_INTBULK: NAKSts (Bit 17) */ -#define USB_EP_DOEPCTL_INTBULK_NAKSts_Msk \ - (0x20000UL) /*!< USB_EP DOEPCTL_INTBULK: NAKSts (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL_INTBULK_EPType_Pos \ - (18UL) /*!< USB_EP DOEPCTL_INTBULK: EPType (Bit 18) */ -#define USB_EP_DOEPCTL_INTBULK_EPType_Msk \ - (0xc0000UL) /*!< USB_EP DOEPCTL_INTBULK: EPType (Bitfield-Mask: 0x03) */ -#define USB_EP_DOEPCTL_INTBULK_Snp_Pos \ - (20UL) /*!< USB_EP DOEPCTL_INTBULK: Snp (Bit 20) */ -#define USB_EP_DOEPCTL_INTBULK_Snp_Msk \ - (0x100000UL) /*!< USB_EP DOEPCTL_INTBULK: Snp (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL_INTBULK_Stall_Pos \ - (21UL) /*!< USB_EP DOEPCTL_INTBULK: Stall (Bit 21) */ -#define USB_EP_DOEPCTL_INTBULK_Stall_Msk \ - (0x200000UL) /*!< USB_EP DOEPCTL_INTBULK: Stall (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL_INTBULK_TxFNum_Pos \ - (22UL) /*!< USB_EP DOEPCTL_INTBULK: TxFNum (Bit 22) */ -#define USB_EP_DOEPCTL_INTBULK_TxFNum_Msk \ - (0x3c00000UL) /*!< USB_EP DOEPCTL_INTBULK: TxFNum (Bitfield-Mask: 0x0f) */ -#define USB_EP_DOEPCTL_INTBULK_CNAK_Pos \ - (26UL) /*!< USB_EP DOEPCTL_INTBULK: CNAK (Bit 26) */ -#define USB_EP_DOEPCTL_INTBULK_CNAK_Msk \ - (0x4000000UL) /*!< USB_EP DOEPCTL_INTBULK: CNAK (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL_INTBULK_SNAK_Pos \ - (27UL) /*!< USB_EP DOEPCTL_INTBULK: SNAK (Bit 27) */ -#define USB_EP_DOEPCTL_INTBULK_SNAK_Msk \ - (0x8000000UL) /*!< USB_EP DOEPCTL_INTBULK: SNAK (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL_INTBULK_SetD0PID_Pos \ - (28UL) /*!< USB_EP DOEPCTL_INTBULK: SetD0PID (Bit 28) */ -#define USB_EP_DOEPCTL_INTBULK_SetD0PID_Msk \ - (0x10000000UL) /*!< USB_EP DOEPCTL_INTBULK: SetD0PID (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL_INTBULK_SetD1PID_Pos \ - (29UL) /*!< USB_EP DOEPCTL_INTBULK: SetD1PID (Bit 29) */ -#define USB_EP_DOEPCTL_INTBULK_SetD1PID_Msk \ - (0x20000000UL) /*!< USB_EP DOEPCTL_INTBULK: SetD1PID (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL_INTBULK_EPDis_Pos \ - (30UL) /*!< USB_EP DOEPCTL_INTBULK: EPDis (Bit 30) */ -#define USB_EP_DOEPCTL_INTBULK_EPDis_Msk \ - (0x40000000UL) /*!< USB_EP DOEPCTL_INTBULK: EPDis (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL_INTBULK_EPEna_Pos \ - (31UL) /*!< USB_EP DOEPCTL_INTBULK: EPEna (Bit 31) */ -#define USB_EP_DOEPCTL_INTBULK_EPEna_Msk \ - (0x80000000UL) /*!< USB_EP DOEPCTL_INTBULK: EPEna (Bitfield-Mask: 0x01) */ - -/* ------------------------------- USB_EP_DOEPINT ------------------------------- */ -#define USB_EP_DOEPINT_XferCompl_Pos \ - (0UL) /*!< USB_EP DOEPINT: XferCompl (Bit 0) */ -#define USB_EP_DOEPINT_XferCompl_Msk \ - (0x1UL) /*!< USB_EP DOEPINT: XferCompl (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPINT_EPDisbld_Pos \ - (1UL) /*!< USB_EP DOEPINT: EPDisbld (Bit 1) */ -#define USB_EP_DOEPINT_EPDisbld_Msk \ - (0x2UL) /*!< USB_EP DOEPINT: EPDisbld (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPINT_AHBErr_Pos \ - (2UL) /*!< USB_EP DOEPINT: AHBErr (Bit 2) */ -#define USB_EP_DOEPINT_AHBErr_Msk \ - (0x4UL) /*!< USB_EP DOEPINT: AHBErr (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPINT_SetUp_Pos \ - (3UL) /*!< USB_EP DOEPINT: SetUp (Bit 3) */ -#define USB_EP_DOEPINT_SetUp_Msk \ - (0x8UL) /*!< USB_EP DOEPINT: SetUp (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPINT_OUTTknEPdis_Pos \ - (4UL) /*!< USB_EP DOEPINT: OUTTknEPdis (Bit 4) */ -#define USB_EP_DOEPINT_OUTTknEPdis_Msk \ - (0x10UL) /*!< USB_EP DOEPINT: OUTTknEPdis (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPINT_StsPhseRcvd_Pos \ - (5UL) /*!< USB_EP DOEPINT: StsPhseRcvd (Bit 5) */ -#define USB_EP_DOEPINT_StsPhseRcvd_Msk \ - (0x20UL) /*!< USB_EP DOEPINT: StsPhseRcvd (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPINT_Back2BackSETup_Pos \ - (6UL) /*!< USB_EP DOEPINT: Back2BackSETup (Bit 6) */ -#define USB_EP_DOEPINT_Back2BackSETup_Msk \ - (0x40UL) /*!< USB_EP DOEPINT: Back2BackSETup (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPINT_BNAIntr_Pos \ - (9UL) /*!< USB_EP DOEPINT: BNAIntr (Bit 9) */ -#define USB_EP_DOEPINT_BNAIntr_Msk \ - (0x200UL) /*!< USB_EP DOEPINT: BNAIntr (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPINT_PktDrpSts_Pos \ - (11UL) /*!< USB_EP DOEPINT: PktDrpSts (Bit 11) */ -#define USB_EP_DOEPINT_PktDrpSts_Msk \ - (0x800UL) /*!< USB_EP DOEPINT: PktDrpSts (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPINT_BbleErrIntrpt_Pos \ - (12UL) /*!< USB_EP DOEPINT: BbleErrIntrpt (Bit 12) */ -#define USB_EP_DOEPINT_BbleErrIntrpt_Msk \ - (0x1000UL) /*!< USB_EP DOEPINT: BbleErrIntrpt (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPINT_NAKIntrpt_Pos \ - (13UL) /*!< USB_EP DOEPINT: NAKIntrpt (Bit 13) */ -#define USB_EP_DOEPINT_NAKIntrpt_Msk \ - (0x2000UL) /*!< USB_EP DOEPINT: NAKIntrpt (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPINT_NYETIntrpt_Pos \ - (14UL) /*!< USB_EP DOEPINT: NYETIntrpt (Bit 14) */ -#define USB_EP_DOEPINT_NYETIntrpt_Msk \ - (0x4000UL) /*!< USB_EP DOEPINT: NYETIntrpt (Bitfield-Mask: 0x01) */ - -/* ----------------------------- USB_EP_DOEPTSIZ_ISO ---------------------------- */ -#define USB_EP_DOEPTSIZ_ISO_XferSize_Pos \ - (0UL) /*!< USB_EP DOEPTSIZ_ISO: XferSize (Bit 0) */ -#define USB_EP_DOEPTSIZ_ISO_XferSize_Msk \ - (0x7ffffUL) /*!< USB_EP DOEPTSIZ_ISO: XferSize (Bitfield-Mask: 0x7ffff) */ -#define USB_EP_DOEPTSIZ_ISO_PktCnt_Pos \ - (19UL) /*!< USB_EP DOEPTSIZ_ISO: PktCnt (Bit 19) */ -#define USB_EP_DOEPTSIZ_ISO_PktCnt_Msk \ - (0x1ff80000UL) /*!< USB_EP DOEPTSIZ_ISO: PktCnt (Bitfield-Mask: 0x3ff) */ -#define USB_EP_DOEPTSIZ_ISO_RxDPID_Pos \ - (29UL) /*!< USB_EP DOEPTSIZ_ISO: RxDPID (Bit 29) */ -#define USB_EP_DOEPTSIZ_ISO_RxDPID_Msk \ - (0x60000000UL) /*!< USB_EP DOEPTSIZ_ISO: RxDPID (Bitfield-Mask: 0x03) */ - -/* --------------------------- USB_EP_DOEPTSIZ_CONTROL -------------------------- */ -#define USB_EP_DOEPTSIZ_CONTROL_XferSize_Pos \ - (0UL) /*!< USB_EP DOEPTSIZ_CONTROL: XferSize (Bit 0) */ -#define USB_EP_DOEPTSIZ_CONTROL_XferSize_Msk \ - (0x7ffffUL) /*!< USB_EP DOEPTSIZ_CONTROL: XferSize (Bitfield-Mask: 0x7ffff) */ -#define USB_EP_DOEPTSIZ_CONTROL_PktCnt_Pos \ - (19UL) /*!< USB_EP DOEPTSIZ_CONTROL: PktCnt (Bit 19) */ -#define USB_EP_DOEPTSIZ_CONTROL_PktCnt_Msk \ - (0x1ff80000UL) /*!< USB_EP DOEPTSIZ_CONTROL: PktCnt (Bitfield-Mask: 0x3ff) */ -#define USB_EP_DOEPTSIZ_CONTROL_SUPCnt_Pos \ - (29UL) /*!< USB_EP DOEPTSIZ_CONTROL: SUPCnt (Bit 29) */ -#define USB_EP_DOEPTSIZ_CONTROL_SUPCnt_Msk \ - (0x60000000UL) /*!< USB_EP DOEPTSIZ_CONTROL: SUPCnt (Bitfield-Mask: 0x03) */ - -/* ------------------------------- USB_EP_DOEPDMA ------------------------------- */ -#define USB_EP_DOEPDMA_DMAAddr_Pos \ - (0UL) /*!< USB_EP DOEPDMA: DMAAddr (Bit 0) */ -#define USB_EP_DOEPDMA_DMAAddr_Msk \ - (0xffffffffUL) /*!< USB_EP DOEPDMA: DMAAddr (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------- USB_EP_DOEPDMAB ------------------------------ */ -#define USB_EP_DOEPDMAB_DMABufferAddr_Pos \ - (0UL) /*!< USB_EP DOEPDMAB: DMABufferAddr (Bit 0) */ -#define USB_EP_DOEPDMAB_DMABufferAddr_Msk \ - (0xffffffffUL) /*!< USB_EP DOEPDMAB: DMABufferAddr (Bitfield-Mask: 0xffffffff) */ - -/* ================================================================================ */ -/* ================ Group 'USIC' Position & Mask ================ */ -/* ================================================================================ */ - -/* ----------------------------------- USIC_ID ---------------------------------- */ -#define USIC_ID_MOD_REV_Pos \ - (0UL) /*!< USIC ID: MOD_REV (Bit 0) */ -#define USIC_ID_MOD_REV_Msk \ - (0xffUL) /*!< USIC ID: MOD_REV (Bitfield-Mask: 0xff) */ -#define USIC_ID_MOD_TYPE_Pos \ - (8UL) /*!< USIC ID: MOD_TYPE (Bit 8) */ -#define USIC_ID_MOD_TYPE_Msk \ - (0xff00UL) /*!< USIC ID: MOD_TYPE (Bitfield-Mask: 0xff) */ -#define USIC_ID_MOD_NUMBER_Pos \ - (16UL) /*!< USIC ID: MOD_NUMBER (Bit 16) */ -#define USIC_ID_MOD_NUMBER_Msk \ - (0xffff0000UL) /*!< USIC ID: MOD_NUMBER (Bitfield-Mask: 0xffff) */ - -/* ================================================================================ */ -/* ================ Group 'USIC_CH' Position & Mask ================ */ -/* ================================================================================ */ - -/* -------------------------------- USIC_CH_CCFG -------------------------------- */ -#define USIC_CH_CCFG_SSC_Pos \ - (0UL) /*!< USIC_CH CCFG: SSC (Bit 0) */ -#define USIC_CH_CCFG_SSC_Msk \ - (0x1UL) /*!< USIC_CH CCFG: SSC (Bitfield-Mask: 0x01) */ -#define USIC_CH_CCFG_ASC_Pos \ - (1UL) /*!< USIC_CH CCFG: ASC (Bit 1) */ -#define USIC_CH_CCFG_ASC_Msk \ - (0x2UL) /*!< USIC_CH CCFG: ASC (Bitfield-Mask: 0x01) */ -#define USIC_CH_CCFG_IIC_Pos \ - (2UL) /*!< USIC_CH CCFG: IIC (Bit 2) */ -#define USIC_CH_CCFG_IIC_Msk \ - (0x4UL) /*!< USIC_CH CCFG: IIC (Bitfield-Mask: 0x01) */ -#define USIC_CH_CCFG_IIS_Pos \ - (3UL) /*!< USIC_CH CCFG: IIS (Bit 3) */ -#define USIC_CH_CCFG_IIS_Msk \ - (0x8UL) /*!< USIC_CH CCFG: IIS (Bitfield-Mask: 0x01) */ -#define USIC_CH_CCFG_RB_Pos \ - (6UL) /*!< USIC_CH CCFG: RB (Bit 6) */ -#define USIC_CH_CCFG_RB_Msk \ - (0x40UL) /*!< USIC_CH CCFG: RB (Bitfield-Mask: 0x01) */ -#define USIC_CH_CCFG_TB_Pos \ - (7UL) /*!< USIC_CH CCFG: TB (Bit 7) */ -#define USIC_CH_CCFG_TB_Msk \ - (0x80UL) /*!< USIC_CH CCFG: TB (Bitfield-Mask: 0x01) */ - -/* -------------------------------- USIC_CH_KSCFG ------------------------------- */ -#define USIC_CH_KSCFG_MODEN_Pos \ - (0UL) /*!< USIC_CH KSCFG: MODEN (Bit 0) */ -#define USIC_CH_KSCFG_MODEN_Msk \ - (0x1UL) /*!< USIC_CH KSCFG: MODEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_KSCFG_BPMODEN_Pos \ - (1UL) /*!< USIC_CH KSCFG: BPMODEN (Bit 1) */ -#define USIC_CH_KSCFG_BPMODEN_Msk \ - (0x2UL) /*!< USIC_CH KSCFG: BPMODEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_KSCFG_NOMCFG_Pos \ - (4UL) /*!< USIC_CH KSCFG: NOMCFG (Bit 4) */ -#define USIC_CH_KSCFG_NOMCFG_Msk \ - (0x30UL) /*!< USIC_CH KSCFG: NOMCFG (Bitfield-Mask: 0x03) */ -#define USIC_CH_KSCFG_BPNOM_Pos \ - (7UL) /*!< USIC_CH KSCFG: BPNOM (Bit 7) */ -#define USIC_CH_KSCFG_BPNOM_Msk \ - (0x80UL) /*!< USIC_CH KSCFG: BPNOM (Bitfield-Mask: 0x01) */ -#define USIC_CH_KSCFG_SUMCFG_Pos \ - (8UL) /*!< USIC_CH KSCFG: SUMCFG (Bit 8) */ -#define USIC_CH_KSCFG_SUMCFG_Msk \ - (0x300UL) /*!< USIC_CH KSCFG: SUMCFG (Bitfield-Mask: 0x03) */ -#define USIC_CH_KSCFG_BPSUM_Pos \ - (11UL) /*!< USIC_CH KSCFG: BPSUM (Bit 11) */ -#define USIC_CH_KSCFG_BPSUM_Msk \ - (0x800UL) /*!< USIC_CH KSCFG: BPSUM (Bitfield-Mask: 0x01) */ - -/* --------------------------------- USIC_CH_FDR -------------------------------- */ -#define USIC_CH_FDR_STEP_Pos \ - (0UL) /*!< USIC_CH FDR: STEP (Bit 0) */ -#define USIC_CH_FDR_STEP_Msk \ - (0x3ffUL) /*!< USIC_CH FDR: STEP (Bitfield-Mask: 0x3ff) */ -#define USIC_CH_FDR_DM_Pos \ - (14UL) /*!< USIC_CH FDR: DM (Bit 14) */ -#define USIC_CH_FDR_DM_Msk \ - (0xc000UL) /*!< USIC_CH FDR: DM (Bitfield-Mask: 0x03) */ -#define USIC_CH_FDR_RESULT_Pos \ - (16UL) /*!< USIC_CH FDR: RESULT (Bit 16) */ -#define USIC_CH_FDR_RESULT_Msk \ - (0x3ff0000UL) /*!< USIC_CH FDR: RESULT (Bitfield-Mask: 0x3ff) */ - -/* --------------------------------- USIC_CH_BRG -------------------------------- */ -#define USIC_CH_BRG_CLKSEL_Pos \ - (0UL) /*!< USIC_CH BRG: CLKSEL (Bit 0) */ -#define USIC_CH_BRG_CLKSEL_Msk \ - (0x3UL) /*!< USIC_CH BRG: CLKSEL (Bitfield-Mask: 0x03) */ -#define USIC_CH_BRG_TMEN_Pos \ - (3UL) /*!< USIC_CH BRG: TMEN (Bit 3) */ -#define USIC_CH_BRG_TMEN_Msk \ - (0x8UL) /*!< USIC_CH BRG: TMEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_BRG_PPPEN_Pos \ - (4UL) /*!< USIC_CH BRG: PPPEN (Bit 4) */ -#define USIC_CH_BRG_PPPEN_Msk \ - (0x10UL) /*!< USIC_CH BRG: PPPEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_BRG_CTQSEL_Pos \ - (6UL) /*!< USIC_CH BRG: CTQSEL (Bit 6) */ -#define USIC_CH_BRG_CTQSEL_Msk \ - (0xc0UL) /*!< USIC_CH BRG: CTQSEL (Bitfield-Mask: 0x03) */ -#define USIC_CH_BRG_PCTQ_Pos \ - (8UL) /*!< USIC_CH BRG: PCTQ (Bit 8) */ -#define USIC_CH_BRG_PCTQ_Msk \ - (0x300UL) /*!< USIC_CH BRG: PCTQ (Bitfield-Mask: 0x03) */ -#define USIC_CH_BRG_DCTQ_Pos \ - (10UL) /*!< USIC_CH BRG: DCTQ (Bit 10) */ -#define USIC_CH_BRG_DCTQ_Msk \ - (0x7c00UL) /*!< USIC_CH BRG: DCTQ (Bitfield-Mask: 0x1f) */ -#define USIC_CH_BRG_PDIV_Pos \ - (16UL) /*!< USIC_CH BRG: PDIV (Bit 16) */ -#define USIC_CH_BRG_PDIV_Msk \ - (0x3ff0000UL) /*!< USIC_CH BRG: PDIV (Bitfield-Mask: 0x3ff) */ -#define USIC_CH_BRG_SCLKOSEL_Pos \ - (28UL) /*!< USIC_CH BRG: SCLKOSEL (Bit 28) */ -#define USIC_CH_BRG_SCLKOSEL_Msk \ - (0x10000000UL) /*!< USIC_CH BRG: SCLKOSEL (Bitfield-Mask: 0x01) */ -#define USIC_CH_BRG_MCLKCFG_Pos \ - (29UL) /*!< USIC_CH BRG: MCLKCFG (Bit 29) */ -#define USIC_CH_BRG_MCLKCFG_Msk \ - (0x20000000UL) /*!< USIC_CH BRG: MCLKCFG (Bitfield-Mask: 0x01) */ -#define USIC_CH_BRG_SCLKCFG_Pos \ - (30UL) /*!< USIC_CH BRG: SCLKCFG (Bit 30) */ -#define USIC_CH_BRG_SCLKCFG_Msk \ - (0xc0000000UL) /*!< USIC_CH BRG: SCLKCFG (Bitfield-Mask: 0x03) */ - -/* -------------------------------- USIC_CH_INPR -------------------------------- */ -#define USIC_CH_INPR_TSINP_Pos \ - (0UL) /*!< USIC_CH INPR: TSINP (Bit 0) */ -#define USIC_CH_INPR_TSINP_Msk \ - (0x7UL) /*!< USIC_CH INPR: TSINP (Bitfield-Mask: 0x07) */ -#define USIC_CH_INPR_TBINP_Pos \ - (4UL) /*!< USIC_CH INPR: TBINP (Bit 4) */ -#define USIC_CH_INPR_TBINP_Msk \ - (0x70UL) /*!< USIC_CH INPR: TBINP (Bitfield-Mask: 0x07) */ -#define USIC_CH_INPR_RINP_Pos \ - (8UL) /*!< USIC_CH INPR: RINP (Bit 8) */ -#define USIC_CH_INPR_RINP_Msk \ - (0x700UL) /*!< USIC_CH INPR: RINP (Bitfield-Mask: 0x07) */ -#define USIC_CH_INPR_AINP_Pos \ - (12UL) /*!< USIC_CH INPR: AINP (Bit 12) */ -#define USIC_CH_INPR_AINP_Msk \ - (0x7000UL) /*!< USIC_CH INPR: AINP (Bitfield-Mask: 0x07) */ -#define USIC_CH_INPR_PINP_Pos \ - (16UL) /*!< USIC_CH INPR: PINP (Bit 16) */ -#define USIC_CH_INPR_PINP_Msk \ - (0x70000UL) /*!< USIC_CH INPR: PINP (Bitfield-Mask: 0x07) */ - -/* -------------------------------- USIC_CH_DX0CR ------------------------------- */ -#define USIC_CH_DX0CR_DSEL_Pos \ - (0UL) /*!< USIC_CH DX0CR: DSEL (Bit 0) */ -#define USIC_CH_DX0CR_DSEL_Msk \ - (0x7UL) /*!< USIC_CH DX0CR: DSEL (Bitfield-Mask: 0x07) */ -#define USIC_CH_DX0CR_INSW_Pos \ - (4UL) /*!< USIC_CH DX0CR: INSW (Bit 4) */ -#define USIC_CH_DX0CR_INSW_Msk \ - (0x10UL) /*!< USIC_CH DX0CR: INSW (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX0CR_DFEN_Pos \ - (5UL) /*!< USIC_CH DX0CR: DFEN (Bit 5) */ -#define USIC_CH_DX0CR_DFEN_Msk \ - (0x20UL) /*!< USIC_CH DX0CR: DFEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX0CR_DSEN_Pos \ - (6UL) /*!< USIC_CH DX0CR: DSEN (Bit 6) */ -#define USIC_CH_DX0CR_DSEN_Msk \ - (0x40UL) /*!< USIC_CH DX0CR: DSEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX0CR_DPOL_Pos \ - (8UL) /*!< USIC_CH DX0CR: DPOL (Bit 8) */ -#define USIC_CH_DX0CR_DPOL_Msk \ - (0x100UL) /*!< USIC_CH DX0CR: DPOL (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX0CR_SFSEL_Pos \ - (9UL) /*!< USIC_CH DX0CR: SFSEL (Bit 9) */ -#define USIC_CH_DX0CR_SFSEL_Msk \ - (0x200UL) /*!< USIC_CH DX0CR: SFSEL (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX0CR_CM_Pos \ - (10UL) /*!< USIC_CH DX0CR: CM (Bit 10) */ -#define USIC_CH_DX0CR_CM_Msk \ - (0xc00UL) /*!< USIC_CH DX0CR: CM (Bitfield-Mask: 0x03) */ -#define USIC_CH_DX0CR_DXS_Pos \ - (15UL) /*!< USIC_CH DX0CR: DXS (Bit 15) */ -#define USIC_CH_DX0CR_DXS_Msk \ - (0x8000UL) /*!< USIC_CH DX0CR: DXS (Bitfield-Mask: 0x01) */ - -/* -------------------------------- USIC_CH_DX1CR ------------------------------- */ -#define USIC_CH_DX1CR_DSEL_Pos \ - (0UL) /*!< USIC_CH DX1CR: DSEL (Bit 0) */ -#define USIC_CH_DX1CR_DSEL_Msk \ - (0x7UL) /*!< USIC_CH DX1CR: DSEL (Bitfield-Mask: 0x07) */ -#define USIC_CH_DX1CR_DCEN_Pos \ - (3UL) /*!< USIC_CH DX1CR: DCEN (Bit 3) */ -#define USIC_CH_DX1CR_DCEN_Msk \ - (0x8UL) /*!< USIC_CH DX1CR: DCEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX1CR_INSW_Pos \ - (4UL) /*!< USIC_CH DX1CR: INSW (Bit 4) */ -#define USIC_CH_DX1CR_INSW_Msk \ - (0x10UL) /*!< USIC_CH DX1CR: INSW (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX1CR_DFEN_Pos \ - (5UL) /*!< USIC_CH DX1CR: DFEN (Bit 5) */ -#define USIC_CH_DX1CR_DFEN_Msk \ - (0x20UL) /*!< USIC_CH DX1CR: DFEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX1CR_DSEN_Pos \ - (6UL) /*!< USIC_CH DX1CR: DSEN (Bit 6) */ -#define USIC_CH_DX1CR_DSEN_Msk \ - (0x40UL) /*!< USIC_CH DX1CR: DSEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX1CR_DPOL_Pos \ - (8UL) /*!< USIC_CH DX1CR: DPOL (Bit 8) */ -#define USIC_CH_DX1CR_DPOL_Msk \ - (0x100UL) /*!< USIC_CH DX1CR: DPOL (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX1CR_SFSEL_Pos \ - (9UL) /*!< USIC_CH DX1CR: SFSEL (Bit 9) */ -#define USIC_CH_DX1CR_SFSEL_Msk \ - (0x200UL) /*!< USIC_CH DX1CR: SFSEL (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX1CR_CM_Pos \ - (10UL) /*!< USIC_CH DX1CR: CM (Bit 10) */ -#define USIC_CH_DX1CR_CM_Msk \ - (0xc00UL) /*!< USIC_CH DX1CR: CM (Bitfield-Mask: 0x03) */ -#define USIC_CH_DX1CR_DXS_Pos \ - (15UL) /*!< USIC_CH DX1CR: DXS (Bit 15) */ -#define USIC_CH_DX1CR_DXS_Msk \ - (0x8000UL) /*!< USIC_CH DX1CR: DXS (Bitfield-Mask: 0x01) */ - -/* -------------------------------- USIC_CH_DX2CR ------------------------------- */ -#define USIC_CH_DX2CR_DSEL_Pos \ - (0UL) /*!< USIC_CH DX2CR: DSEL (Bit 0) */ -#define USIC_CH_DX2CR_DSEL_Msk \ - (0x7UL) /*!< USIC_CH DX2CR: DSEL (Bitfield-Mask: 0x07) */ -#define USIC_CH_DX2CR_INSW_Pos \ - (4UL) /*!< USIC_CH DX2CR: INSW (Bit 4) */ -#define USIC_CH_DX2CR_INSW_Msk \ - (0x10UL) /*!< USIC_CH DX2CR: INSW (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX2CR_DFEN_Pos \ - (5UL) /*!< USIC_CH DX2CR: DFEN (Bit 5) */ -#define USIC_CH_DX2CR_DFEN_Msk \ - (0x20UL) /*!< USIC_CH DX2CR: DFEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX2CR_DSEN_Pos \ - (6UL) /*!< USIC_CH DX2CR: DSEN (Bit 6) */ -#define USIC_CH_DX2CR_DSEN_Msk \ - (0x40UL) /*!< USIC_CH DX2CR: DSEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX2CR_DPOL_Pos \ - (8UL) /*!< USIC_CH DX2CR: DPOL (Bit 8) */ -#define USIC_CH_DX2CR_DPOL_Msk \ - (0x100UL) /*!< USIC_CH DX2CR: DPOL (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX2CR_SFSEL_Pos \ - (9UL) /*!< USIC_CH DX2CR: SFSEL (Bit 9) */ -#define USIC_CH_DX2CR_SFSEL_Msk \ - (0x200UL) /*!< USIC_CH DX2CR: SFSEL (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX2CR_CM_Pos \ - (10UL) /*!< USIC_CH DX2CR: CM (Bit 10) */ -#define USIC_CH_DX2CR_CM_Msk \ - (0xc00UL) /*!< USIC_CH DX2CR: CM (Bitfield-Mask: 0x03) */ -#define USIC_CH_DX2CR_DXS_Pos \ - (15UL) /*!< USIC_CH DX2CR: DXS (Bit 15) */ -#define USIC_CH_DX2CR_DXS_Msk \ - (0x8000UL) /*!< USIC_CH DX2CR: DXS (Bitfield-Mask: 0x01) */ - -/* -------------------------------- USIC_CH_DX3CR ------------------------------- */ -#define USIC_CH_DX3CR_DSEL_Pos \ - (0UL) /*!< USIC_CH DX3CR: DSEL (Bit 0) */ -#define USIC_CH_DX3CR_DSEL_Msk \ - (0x7UL) /*!< USIC_CH DX3CR: DSEL (Bitfield-Mask: 0x07) */ -#define USIC_CH_DX3CR_INSW_Pos \ - (4UL) /*!< USIC_CH DX3CR: INSW (Bit 4) */ -#define USIC_CH_DX3CR_INSW_Msk \ - (0x10UL) /*!< USIC_CH DX3CR: INSW (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX3CR_DFEN_Pos \ - (5UL) /*!< USIC_CH DX3CR: DFEN (Bit 5) */ -#define USIC_CH_DX3CR_DFEN_Msk \ - (0x20UL) /*!< USIC_CH DX3CR: DFEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX3CR_DSEN_Pos \ - (6UL) /*!< USIC_CH DX3CR: DSEN (Bit 6) */ -#define USIC_CH_DX3CR_DSEN_Msk \ - (0x40UL) /*!< USIC_CH DX3CR: DSEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX3CR_DPOL_Pos \ - (8UL) /*!< USIC_CH DX3CR: DPOL (Bit 8) */ -#define USIC_CH_DX3CR_DPOL_Msk \ - (0x100UL) /*!< USIC_CH DX3CR: DPOL (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX3CR_SFSEL_Pos \ - (9UL) /*!< USIC_CH DX3CR: SFSEL (Bit 9) */ -#define USIC_CH_DX3CR_SFSEL_Msk \ - (0x200UL) /*!< USIC_CH DX3CR: SFSEL (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX3CR_CM_Pos \ - (10UL) /*!< USIC_CH DX3CR: CM (Bit 10) */ -#define USIC_CH_DX3CR_CM_Msk \ - (0xc00UL) /*!< USIC_CH DX3CR: CM (Bitfield-Mask: 0x03) */ -#define USIC_CH_DX3CR_DXS_Pos \ - (15UL) /*!< USIC_CH DX3CR: DXS (Bit 15) */ -#define USIC_CH_DX3CR_DXS_Msk \ - (0x8000UL) /*!< USIC_CH DX3CR: DXS (Bitfield-Mask: 0x01) */ - -/* -------------------------------- USIC_CH_DX4CR ------------------------------- */ -#define USIC_CH_DX4CR_DSEL_Pos \ - (0UL) /*!< USIC_CH DX4CR: DSEL (Bit 0) */ -#define USIC_CH_DX4CR_DSEL_Msk \ - (0x7UL) /*!< USIC_CH DX4CR: DSEL (Bitfield-Mask: 0x07) */ -#define USIC_CH_DX4CR_INSW_Pos \ - (4UL) /*!< USIC_CH DX4CR: INSW (Bit 4) */ -#define USIC_CH_DX4CR_INSW_Msk \ - (0x10UL) /*!< USIC_CH DX4CR: INSW (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX4CR_DFEN_Pos \ - (5UL) /*!< USIC_CH DX4CR: DFEN (Bit 5) */ -#define USIC_CH_DX4CR_DFEN_Msk \ - (0x20UL) /*!< USIC_CH DX4CR: DFEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX4CR_DSEN_Pos \ - (6UL) /*!< USIC_CH DX4CR: DSEN (Bit 6) */ -#define USIC_CH_DX4CR_DSEN_Msk \ - (0x40UL) /*!< USIC_CH DX4CR: DSEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX4CR_DPOL_Pos \ - (8UL) /*!< USIC_CH DX4CR: DPOL (Bit 8) */ -#define USIC_CH_DX4CR_DPOL_Msk \ - (0x100UL) /*!< USIC_CH DX4CR: DPOL (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX4CR_SFSEL_Pos \ - (9UL) /*!< USIC_CH DX4CR: SFSEL (Bit 9) */ -#define USIC_CH_DX4CR_SFSEL_Msk \ - (0x200UL) /*!< USIC_CH DX4CR: SFSEL (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX4CR_CM_Pos \ - (10UL) /*!< USIC_CH DX4CR: CM (Bit 10) */ -#define USIC_CH_DX4CR_CM_Msk \ - (0xc00UL) /*!< USIC_CH DX4CR: CM (Bitfield-Mask: 0x03) */ -#define USIC_CH_DX4CR_DXS_Pos \ - (15UL) /*!< USIC_CH DX4CR: DXS (Bit 15) */ -#define USIC_CH_DX4CR_DXS_Msk \ - (0x8000UL) /*!< USIC_CH DX4CR: DXS (Bitfield-Mask: 0x01) */ - -/* -------------------------------- USIC_CH_DX5CR ------------------------------- */ -#define USIC_CH_DX5CR_DSEL_Pos \ - (0UL) /*!< USIC_CH DX5CR: DSEL (Bit 0) */ -#define USIC_CH_DX5CR_DSEL_Msk \ - (0x7UL) /*!< USIC_CH DX5CR: DSEL (Bitfield-Mask: 0x07) */ -#define USIC_CH_DX5CR_INSW_Pos \ - (4UL) /*!< USIC_CH DX5CR: INSW (Bit 4) */ -#define USIC_CH_DX5CR_INSW_Msk \ - (0x10UL) /*!< USIC_CH DX5CR: INSW (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX5CR_DFEN_Pos \ - (5UL) /*!< USIC_CH DX5CR: DFEN (Bit 5) */ -#define USIC_CH_DX5CR_DFEN_Msk \ - (0x20UL) /*!< USIC_CH DX5CR: DFEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX5CR_DSEN_Pos \ - (6UL) /*!< USIC_CH DX5CR: DSEN (Bit 6) */ -#define USIC_CH_DX5CR_DSEN_Msk \ - (0x40UL) /*!< USIC_CH DX5CR: DSEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX5CR_DPOL_Pos \ - (8UL) /*!< USIC_CH DX5CR: DPOL (Bit 8) */ -#define USIC_CH_DX5CR_DPOL_Msk \ - (0x100UL) /*!< USIC_CH DX5CR: DPOL (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX5CR_SFSEL_Pos \ - (9UL) /*!< USIC_CH DX5CR: SFSEL (Bit 9) */ -#define USIC_CH_DX5CR_SFSEL_Msk \ - (0x200UL) /*!< USIC_CH DX5CR: SFSEL (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX5CR_CM_Pos \ - (10UL) /*!< USIC_CH DX5CR: CM (Bit 10) */ -#define USIC_CH_DX5CR_CM_Msk \ - (0xc00UL) /*!< USIC_CH DX5CR: CM (Bitfield-Mask: 0x03) */ -#define USIC_CH_DX5CR_DXS_Pos \ - (15UL) /*!< USIC_CH DX5CR: DXS (Bit 15) */ -#define USIC_CH_DX5CR_DXS_Msk \ - (0x8000UL) /*!< USIC_CH DX5CR: DXS (Bitfield-Mask: 0x01) */ - -/* -------------------------------- USIC_CH_SCTR -------------------------------- */ -#define USIC_CH_SCTR_SDIR_Pos \ - (0UL) /*!< USIC_CH SCTR: SDIR (Bit 0) */ -#define USIC_CH_SCTR_SDIR_Msk \ - (0x1UL) /*!< USIC_CH SCTR: SDIR (Bitfield-Mask: 0x01) */ -#define USIC_CH_SCTR_PDL_Pos \ - (1UL) /*!< USIC_CH SCTR: PDL (Bit 1) */ -#define USIC_CH_SCTR_PDL_Msk \ - (0x2UL) /*!< USIC_CH SCTR: PDL (Bitfield-Mask: 0x01) */ -#define USIC_CH_SCTR_DSM_Pos \ - (2UL) /*!< USIC_CH SCTR: DSM (Bit 2) */ -#define USIC_CH_SCTR_DSM_Msk \ - (0xcUL) /*!< USIC_CH SCTR: DSM (Bitfield-Mask: 0x03) */ -#define USIC_CH_SCTR_HPCDIR_Pos \ - (4UL) /*!< USIC_CH SCTR: HPCDIR (Bit 4) */ -#define USIC_CH_SCTR_HPCDIR_Msk \ - (0x10UL) /*!< USIC_CH SCTR: HPCDIR (Bitfield-Mask: 0x01) */ -#define USIC_CH_SCTR_DOCFG_Pos \ - (6UL) /*!< USIC_CH SCTR: DOCFG (Bit 6) */ -#define USIC_CH_SCTR_DOCFG_Msk \ - (0xc0UL) /*!< USIC_CH SCTR: DOCFG (Bitfield-Mask: 0x03) */ -#define USIC_CH_SCTR_TRM_Pos \ - (8UL) /*!< USIC_CH SCTR: TRM (Bit 8) */ -#define USIC_CH_SCTR_TRM_Msk \ - (0x300UL) /*!< USIC_CH SCTR: TRM (Bitfield-Mask: 0x03) */ -#define USIC_CH_SCTR_FLE_Pos \ - (16UL) /*!< USIC_CH SCTR: FLE (Bit 16) */ -#define USIC_CH_SCTR_FLE_Msk \ - (0x3f0000UL) /*!< USIC_CH SCTR: FLE (Bitfield-Mask: 0x3f) */ -#define USIC_CH_SCTR_WLE_Pos \ - (24UL) /*!< USIC_CH SCTR: WLE (Bit 24) */ -#define USIC_CH_SCTR_WLE_Msk \ - (0xf000000UL) /*!< USIC_CH SCTR: WLE (Bitfield-Mask: 0x0f) */ - -/* -------------------------------- USIC_CH_TCSR -------------------------------- */ -#define USIC_CH_TCSR_WLEMD_Pos \ - (0UL) /*!< USIC_CH TCSR: WLEMD (Bit 0) */ -#define USIC_CH_TCSR_WLEMD_Msk \ - (0x1UL) /*!< USIC_CH TCSR: WLEMD (Bitfield-Mask: 0x01) */ -#define USIC_CH_TCSR_SELMD_Pos \ - (1UL) /*!< USIC_CH TCSR: SELMD (Bit 1) */ -#define USIC_CH_TCSR_SELMD_Msk \ - (0x2UL) /*!< USIC_CH TCSR: SELMD (Bitfield-Mask: 0x01) */ -#define USIC_CH_TCSR_FLEMD_Pos \ - (2UL) /*!< USIC_CH TCSR: FLEMD (Bit 2) */ -#define USIC_CH_TCSR_FLEMD_Msk \ - (0x4UL) /*!< USIC_CH TCSR: FLEMD (Bitfield-Mask: 0x01) */ -#define USIC_CH_TCSR_WAMD_Pos \ - (3UL) /*!< USIC_CH TCSR: WAMD (Bit 3) */ -#define USIC_CH_TCSR_WAMD_Msk \ - (0x8UL) /*!< USIC_CH TCSR: WAMD (Bitfield-Mask: 0x01) */ -#define USIC_CH_TCSR_HPCMD_Pos \ - (4UL) /*!< USIC_CH TCSR: HPCMD (Bit 4) */ -#define USIC_CH_TCSR_HPCMD_Msk \ - (0x10UL) /*!< USIC_CH TCSR: HPCMD (Bitfield-Mask: 0x01) */ -#define USIC_CH_TCSR_SOF_Pos \ - (5UL) /*!< USIC_CH TCSR: SOF (Bit 5) */ -#define USIC_CH_TCSR_SOF_Msk \ - (0x20UL) /*!< USIC_CH TCSR: SOF (Bitfield-Mask: 0x01) */ -#define USIC_CH_TCSR_EOF_Pos \ - (6UL) /*!< USIC_CH TCSR: EOF (Bit 6) */ -#define USIC_CH_TCSR_EOF_Msk \ - (0x40UL) /*!< USIC_CH TCSR: EOF (Bitfield-Mask: 0x01) */ -#define USIC_CH_TCSR_TDV_Pos \ - (7UL) /*!< USIC_CH TCSR: TDV (Bit 7) */ -#define USIC_CH_TCSR_TDV_Msk \ - (0x80UL) /*!< USIC_CH TCSR: TDV (Bitfield-Mask: 0x01) */ -#define USIC_CH_TCSR_TDSSM_Pos \ - (8UL) /*!< USIC_CH TCSR: TDSSM (Bit 8) */ -#define USIC_CH_TCSR_TDSSM_Msk \ - (0x100UL) /*!< USIC_CH TCSR: TDSSM (Bitfield-Mask: 0x01) */ -#define USIC_CH_TCSR_TDEN_Pos \ - (10UL) /*!< USIC_CH TCSR: TDEN (Bit 10) */ -#define USIC_CH_TCSR_TDEN_Msk \ - (0xc00UL) /*!< USIC_CH TCSR: TDEN (Bitfield-Mask: 0x03) */ -#define USIC_CH_TCSR_TDVTR_Pos \ - (12UL) /*!< USIC_CH TCSR: TDVTR (Bit 12) */ -#define USIC_CH_TCSR_TDVTR_Msk \ - (0x1000UL) /*!< USIC_CH TCSR: TDVTR (Bitfield-Mask: 0x01) */ -#define USIC_CH_TCSR_WA_Pos \ - (13UL) /*!< USIC_CH TCSR: WA (Bit 13) */ -#define USIC_CH_TCSR_WA_Msk \ - (0x2000UL) /*!< USIC_CH TCSR: WA (Bitfield-Mask: 0x01) */ -#define USIC_CH_TCSR_TSOF_Pos \ - (24UL) /*!< USIC_CH TCSR: TSOF (Bit 24) */ -#define USIC_CH_TCSR_TSOF_Msk \ - (0x1000000UL) /*!< USIC_CH TCSR: TSOF (Bitfield-Mask: 0x01) */ -#define USIC_CH_TCSR_TV_Pos \ - (26UL) /*!< USIC_CH TCSR: TV (Bit 26) */ -#define USIC_CH_TCSR_TV_Msk \ - (0x4000000UL) /*!< USIC_CH TCSR: TV (Bitfield-Mask: 0x01) */ -#define USIC_CH_TCSR_TVC_Pos \ - (27UL) /*!< USIC_CH TCSR: TVC (Bit 27) */ -#define USIC_CH_TCSR_TVC_Msk \ - (0x8000000UL) /*!< USIC_CH TCSR: TVC (Bitfield-Mask: 0x01) */ -#define USIC_CH_TCSR_TE_Pos \ - (28UL) /*!< USIC_CH TCSR: TE (Bit 28) */ -#define USIC_CH_TCSR_TE_Msk \ - (0x10000000UL) /*!< USIC_CH TCSR: TE (Bitfield-Mask: 0x01) */ - -/* --------------------------------- USIC_CH_PCR -------------------------------- */ -#define USIC_CH_PCR_CTR0_Pos \ - (0UL) /*!< USIC_CH PCR: CTR0 (Bit 0) */ -#define USIC_CH_PCR_CTR0_Msk \ - (0x1UL) /*!< USIC_CH PCR: CTR0 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR1_Pos \ - (1UL) /*!< USIC_CH PCR: CTR1 (Bit 1) */ -#define USIC_CH_PCR_CTR1_Msk \ - (0x2UL) /*!< USIC_CH PCR: CTR1 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR2_Pos \ - (2UL) /*!< USIC_CH PCR: CTR2 (Bit 2) */ -#define USIC_CH_PCR_CTR2_Msk \ - (0x4UL) /*!< USIC_CH PCR: CTR2 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR3_Pos \ - (3UL) /*!< USIC_CH PCR: CTR3 (Bit 3) */ -#define USIC_CH_PCR_CTR3_Msk \ - (0x8UL) /*!< USIC_CH PCR: CTR3 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR4_Pos \ - (4UL) /*!< USIC_CH PCR: CTR4 (Bit 4) */ -#define USIC_CH_PCR_CTR4_Msk \ - (0x10UL) /*!< USIC_CH PCR: CTR4 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR5_Pos \ - (5UL) /*!< USIC_CH PCR: CTR5 (Bit 5) */ -#define USIC_CH_PCR_CTR5_Msk \ - (0x20UL) /*!< USIC_CH PCR: CTR5 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR6_Pos \ - (6UL) /*!< USIC_CH PCR: CTR6 (Bit 6) */ -#define USIC_CH_PCR_CTR6_Msk \ - (0x40UL) /*!< USIC_CH PCR: CTR6 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR7_Pos \ - (7UL) /*!< USIC_CH PCR: CTR7 (Bit 7) */ -#define USIC_CH_PCR_CTR7_Msk \ - (0x80UL) /*!< USIC_CH PCR: CTR7 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR8_Pos \ - (8UL) /*!< USIC_CH PCR: CTR8 (Bit 8) */ -#define USIC_CH_PCR_CTR8_Msk \ - (0x100UL) /*!< USIC_CH PCR: CTR8 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR9_Pos \ - (9UL) /*!< USIC_CH PCR: CTR9 (Bit 9) */ -#define USIC_CH_PCR_CTR9_Msk \ - (0x200UL) /*!< USIC_CH PCR: CTR9 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR10_Pos \ - (10UL) /*!< USIC_CH PCR: CTR10 (Bit 10) */ -#define USIC_CH_PCR_CTR10_Msk \ - (0x400UL) /*!< USIC_CH PCR: CTR10 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR11_Pos \ - (11UL) /*!< USIC_CH PCR: CTR11 (Bit 11) */ -#define USIC_CH_PCR_CTR11_Msk \ - (0x800UL) /*!< USIC_CH PCR: CTR11 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR12_Pos \ - (12UL) /*!< USIC_CH PCR: CTR12 (Bit 12) */ -#define USIC_CH_PCR_CTR12_Msk \ - (0x1000UL) /*!< USIC_CH PCR: CTR12 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR13_Pos \ - (13UL) /*!< USIC_CH PCR: CTR13 (Bit 13) */ -#define USIC_CH_PCR_CTR13_Msk \ - (0x2000UL) /*!< USIC_CH PCR: CTR13 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR14_Pos \ - (14UL) /*!< USIC_CH PCR: CTR14 (Bit 14) */ -#define USIC_CH_PCR_CTR14_Msk \ - (0x4000UL) /*!< USIC_CH PCR: CTR14 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR15_Pos \ - (15UL) /*!< USIC_CH PCR: CTR15 (Bit 15) */ -#define USIC_CH_PCR_CTR15_Msk \ - (0x8000UL) /*!< USIC_CH PCR: CTR15 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR16_Pos \ - (16UL) /*!< USIC_CH PCR: CTR16 (Bit 16) */ -#define USIC_CH_PCR_CTR16_Msk \ - (0x10000UL) /*!< USIC_CH PCR: CTR16 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR17_Pos \ - (17UL) /*!< USIC_CH PCR: CTR17 (Bit 17) */ -#define USIC_CH_PCR_CTR17_Msk \ - (0x20000UL) /*!< USIC_CH PCR: CTR17 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR18_Pos \ - (18UL) /*!< USIC_CH PCR: CTR18 (Bit 18) */ -#define USIC_CH_PCR_CTR18_Msk \ - (0x40000UL) /*!< USIC_CH PCR: CTR18 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR19_Pos \ - (19UL) /*!< USIC_CH PCR: CTR19 (Bit 19) */ -#define USIC_CH_PCR_CTR19_Msk \ - (0x80000UL) /*!< USIC_CH PCR: CTR19 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR20_Pos \ - (20UL) /*!< USIC_CH PCR: CTR20 (Bit 20) */ -#define USIC_CH_PCR_CTR20_Msk \ - (0x100000UL) /*!< USIC_CH PCR: CTR20 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR21_Pos \ - (21UL) /*!< USIC_CH PCR: CTR21 (Bit 21) */ -#define USIC_CH_PCR_CTR21_Msk \ - (0x200000UL) /*!< USIC_CH PCR: CTR21 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR22_Pos \ - (22UL) /*!< USIC_CH PCR: CTR22 (Bit 22) */ -#define USIC_CH_PCR_CTR22_Msk \ - (0x400000UL) /*!< USIC_CH PCR: CTR22 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR23_Pos \ - (23UL) /*!< USIC_CH PCR: CTR23 (Bit 23) */ -#define USIC_CH_PCR_CTR23_Msk \ - (0x800000UL) /*!< USIC_CH PCR: CTR23 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR24_Pos \ - (24UL) /*!< USIC_CH PCR: CTR24 (Bit 24) */ -#define USIC_CH_PCR_CTR24_Msk \ - (0x1000000UL) /*!< USIC_CH PCR: CTR24 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR25_Pos \ - (25UL) /*!< USIC_CH PCR: CTR25 (Bit 25) */ -#define USIC_CH_PCR_CTR25_Msk \ - (0x2000000UL) /*!< USIC_CH PCR: CTR25 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR26_Pos \ - (26UL) /*!< USIC_CH PCR: CTR26 (Bit 26) */ -#define USIC_CH_PCR_CTR26_Msk \ - (0x4000000UL) /*!< USIC_CH PCR: CTR26 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR27_Pos \ - (27UL) /*!< USIC_CH PCR: CTR27 (Bit 27) */ -#define USIC_CH_PCR_CTR27_Msk \ - (0x8000000UL) /*!< USIC_CH PCR: CTR27 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR28_Pos \ - (28UL) /*!< USIC_CH PCR: CTR28 (Bit 28) */ -#define USIC_CH_PCR_CTR28_Msk \ - (0x10000000UL) /*!< USIC_CH PCR: CTR28 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR29_Pos \ - (29UL) /*!< USIC_CH PCR: CTR29 (Bit 29) */ -#define USIC_CH_PCR_CTR29_Msk \ - (0x20000000UL) /*!< USIC_CH PCR: CTR29 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR30_Pos \ - (30UL) /*!< USIC_CH PCR: CTR30 (Bit 30) */ -#define USIC_CH_PCR_CTR30_Msk \ - (0x40000000UL) /*!< USIC_CH PCR: CTR30 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR31_Pos \ - (31UL) /*!< USIC_CH PCR: CTR31 (Bit 31) */ -#define USIC_CH_PCR_CTR31_Msk \ - (0x80000000UL) /*!< USIC_CH PCR: CTR31 (Bitfield-Mask: 0x01) */ - -/* ----------------------------- USIC_CH_PCR_ASCMode ---------------------------- */ -#define USIC_CH_PCR_ASCMode_SMD_Pos \ - (0UL) /*!< USIC_CH PCR_ASCMode: SMD (Bit 0) */ -#define USIC_CH_PCR_ASCMode_SMD_Msk \ - (0x1UL) /*!< USIC_CH PCR_ASCMode: SMD (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_ASCMode_STPB_Pos \ - (1UL) /*!< USIC_CH PCR_ASCMode: STPB (Bit 1) */ -#define USIC_CH_PCR_ASCMode_STPB_Msk \ - (0x2UL) /*!< USIC_CH PCR_ASCMode: STPB (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_ASCMode_IDM_Pos \ - (2UL) /*!< USIC_CH PCR_ASCMode: IDM (Bit 2) */ -#define USIC_CH_PCR_ASCMode_IDM_Msk \ - (0x4UL) /*!< USIC_CH PCR_ASCMode: IDM (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_ASCMode_SBIEN_Pos \ - (3UL) /*!< USIC_CH PCR_ASCMode: SBIEN (Bit 3) */ -#define USIC_CH_PCR_ASCMode_SBIEN_Msk \ - (0x8UL) /*!< USIC_CH PCR_ASCMode: SBIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_ASCMode_CDEN_Pos \ - (4UL) /*!< USIC_CH PCR_ASCMode: CDEN (Bit 4) */ -#define USIC_CH_PCR_ASCMode_CDEN_Msk \ - (0x10UL) /*!< USIC_CH PCR_ASCMode: CDEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_ASCMode_RNIEN_Pos \ - (5UL) /*!< USIC_CH PCR_ASCMode: RNIEN (Bit 5) */ -#define USIC_CH_PCR_ASCMode_RNIEN_Msk \ - (0x20UL) /*!< USIC_CH PCR_ASCMode: RNIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_ASCMode_FEIEN_Pos \ - (6UL) /*!< USIC_CH PCR_ASCMode: FEIEN (Bit 6) */ -#define USIC_CH_PCR_ASCMode_FEIEN_Msk \ - (0x40UL) /*!< USIC_CH PCR_ASCMode: FEIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_ASCMode_FFIEN_Pos \ - (7UL) /*!< USIC_CH PCR_ASCMode: FFIEN (Bit 7) */ -#define USIC_CH_PCR_ASCMode_FFIEN_Msk \ - (0x80UL) /*!< USIC_CH PCR_ASCMode: FFIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_ASCMode_SP_Pos \ - (8UL) /*!< USIC_CH PCR_ASCMode: SP (Bit 8) */ -#define USIC_CH_PCR_ASCMode_SP_Msk \ - (0x1f00UL) /*!< USIC_CH PCR_ASCMode: SP (Bitfield-Mask: 0x1f) */ -#define USIC_CH_PCR_ASCMode_PL_Pos \ - (13UL) /*!< USIC_CH PCR_ASCMode: PL (Bit 13) */ -#define USIC_CH_PCR_ASCMode_PL_Msk \ - (0xe000UL) /*!< USIC_CH PCR_ASCMode: PL (Bitfield-Mask: 0x07) */ -#define USIC_CH_PCR_ASCMode_RSTEN_Pos \ - (16UL) /*!< USIC_CH PCR_ASCMode: RSTEN (Bit 16) */ -#define USIC_CH_PCR_ASCMode_RSTEN_Msk \ - (0x10000UL) /*!< USIC_CH PCR_ASCMode: RSTEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_ASCMode_TSTEN_Pos \ - (17UL) /*!< USIC_CH PCR_ASCMode: TSTEN (Bit 17) */ -#define USIC_CH_PCR_ASCMode_TSTEN_Msk \ - (0x20000UL) /*!< USIC_CH PCR_ASCMode: TSTEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_ASCMode_MCLK_Pos \ - (31UL) /*!< USIC_CH PCR_ASCMode: MCLK (Bit 31) */ -#define USIC_CH_PCR_ASCMode_MCLK_Msk \ - (0x80000000UL) /*!< USIC_CH PCR_ASCMode: MCLK (Bitfield-Mask: 0x01) */ - -/* ----------------------------- USIC_CH_PCR_SSCMode ---------------------------- */ -#define USIC_CH_PCR_SSCMode_MSLSEN_Pos \ - (0UL) /*!< USIC_CH PCR_SSCMode: MSLSEN (Bit 0) */ -#define USIC_CH_PCR_SSCMode_MSLSEN_Msk \ - (0x1UL) /*!< USIC_CH PCR_SSCMode: MSLSEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_SSCMode_SELCTR_Pos \ - (1UL) /*!< USIC_CH PCR_SSCMode: SELCTR (Bit 1) */ -#define USIC_CH_PCR_SSCMode_SELCTR_Msk \ - (0x2UL) /*!< USIC_CH PCR_SSCMode: SELCTR (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_SSCMode_SELINV_Pos \ - (2UL) /*!< USIC_CH PCR_SSCMode: SELINV (Bit 2) */ -#define USIC_CH_PCR_SSCMode_SELINV_Msk \ - (0x4UL) /*!< USIC_CH PCR_SSCMode: SELINV (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_SSCMode_FEM_Pos \ - (3UL) /*!< USIC_CH PCR_SSCMode: FEM (Bit 3) */ -#define USIC_CH_PCR_SSCMode_FEM_Msk \ - (0x8UL) /*!< USIC_CH PCR_SSCMode: FEM (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_SSCMode_CTQSEL1_Pos \ - (4UL) /*!< USIC_CH PCR_SSCMode: CTQSEL1 (Bit 4) */ -#define USIC_CH_PCR_SSCMode_CTQSEL1_Msk \ - (0x30UL) /*!< USIC_CH PCR_SSCMode: CTQSEL1 (Bitfield-Mask: 0x03) */ -#define USIC_CH_PCR_SSCMode_PCTQ1_Pos \ - (6UL) /*!< USIC_CH PCR_SSCMode: PCTQ1 (Bit 6) */ -#define USIC_CH_PCR_SSCMode_PCTQ1_Msk \ - (0xc0UL) /*!< USIC_CH PCR_SSCMode: PCTQ1 (Bitfield-Mask: 0x03) */ -#define USIC_CH_PCR_SSCMode_DCTQ1_Pos \ - (8UL) /*!< USIC_CH PCR_SSCMode: DCTQ1 (Bit 8) */ -#define USIC_CH_PCR_SSCMode_DCTQ1_Msk \ - (0x1f00UL) /*!< USIC_CH PCR_SSCMode: DCTQ1 (Bitfield-Mask: 0x1f) */ -#define USIC_CH_PCR_SSCMode_PARIEN_Pos \ - (13UL) /*!< USIC_CH PCR_SSCMode: PARIEN (Bit 13) */ -#define USIC_CH_PCR_SSCMode_PARIEN_Msk \ - (0x2000UL) /*!< USIC_CH PCR_SSCMode: PARIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_SSCMode_MSLSIEN_Pos \ - (14UL) /*!< USIC_CH PCR_SSCMode: MSLSIEN (Bit 14) */ -#define USIC_CH_PCR_SSCMode_MSLSIEN_Msk \ - (0x4000UL) /*!< USIC_CH PCR_SSCMode: MSLSIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_SSCMode_DX2TIEN_Pos \ - (15UL) /*!< USIC_CH PCR_SSCMode: DX2TIEN (Bit 15) */ -#define USIC_CH_PCR_SSCMode_DX2TIEN_Msk \ - (0x8000UL) /*!< USIC_CH PCR_SSCMode: DX2TIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_SSCMode_SELO_Pos \ - (16UL) /*!< USIC_CH PCR_SSCMode: SELO (Bit 16) */ -#define USIC_CH_PCR_SSCMode_SELO_Msk \ - (0xff0000UL) /*!< USIC_CH PCR_SSCMode: SELO (Bitfield-Mask: 0xff) */ -#define USIC_CH_PCR_SSCMode_TIWEN_Pos \ - (24UL) /*!< USIC_CH PCR_SSCMode: TIWEN (Bit 24) */ -#define USIC_CH_PCR_SSCMode_TIWEN_Msk \ - (0x1000000UL) /*!< USIC_CH PCR_SSCMode: TIWEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_SSCMode_SLPHSEL_Pos \ - (25UL) /*!< USIC_CH PCR_SSCMode: SLPHSEL (Bit 25) */ -#define USIC_CH_PCR_SSCMode_SLPHSEL_Msk \ - (0x2000000UL) /*!< USIC_CH PCR_SSCMode: SLPHSEL (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_SSCMode_MCLK_Pos \ - (31UL) /*!< USIC_CH PCR_SSCMode: MCLK (Bit 31) */ -#define USIC_CH_PCR_SSCMode_MCLK_Msk \ - (0x80000000UL) /*!< USIC_CH PCR_SSCMode: MCLK (Bitfield-Mask: 0x01) */ - -/* ----------------------------- USIC_CH_PCR_IICMode ---------------------------- */ -#define USIC_CH_PCR_IICMode_SLAD_Pos \ - (0UL) /*!< USIC_CH PCR_IICMode: SLAD (Bit 0) */ -#define USIC_CH_PCR_IICMode_SLAD_Msk \ - (0xffffUL) /*!< USIC_CH PCR_IICMode: SLAD (Bitfield-Mask: 0xffff) */ -#define USIC_CH_PCR_IICMode_ACK00_Pos \ - (16UL) /*!< USIC_CH PCR_IICMode: ACK00 (Bit 16) */ -#define USIC_CH_PCR_IICMode_ACK00_Msk \ - (0x10000UL) /*!< USIC_CH PCR_IICMode: ACK00 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_IICMode_STIM_Pos \ - (17UL) /*!< USIC_CH PCR_IICMode: STIM (Bit 17) */ -#define USIC_CH_PCR_IICMode_STIM_Msk \ - (0x20000UL) /*!< USIC_CH PCR_IICMode: STIM (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_IICMode_SCRIEN_Pos \ - (18UL) /*!< USIC_CH PCR_IICMode: SCRIEN (Bit 18) */ -#define USIC_CH_PCR_IICMode_SCRIEN_Msk \ - (0x40000UL) /*!< USIC_CH PCR_IICMode: SCRIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_IICMode_RSCRIEN_Pos \ - (19UL) /*!< USIC_CH PCR_IICMode: RSCRIEN (Bit 19) */ -#define USIC_CH_PCR_IICMode_RSCRIEN_Msk \ - (0x80000UL) /*!< USIC_CH PCR_IICMode: RSCRIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_IICMode_PCRIEN_Pos \ - (20UL) /*!< USIC_CH PCR_IICMode: PCRIEN (Bit 20) */ -#define USIC_CH_PCR_IICMode_PCRIEN_Msk \ - (0x100000UL) /*!< USIC_CH PCR_IICMode: PCRIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_IICMode_NACKIEN_Pos \ - (21UL) /*!< USIC_CH PCR_IICMode: NACKIEN (Bit 21) */ -#define USIC_CH_PCR_IICMode_NACKIEN_Msk \ - (0x200000UL) /*!< USIC_CH PCR_IICMode: NACKIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_IICMode_ARLIEN_Pos \ - (22UL) /*!< USIC_CH PCR_IICMode: ARLIEN (Bit 22) */ -#define USIC_CH_PCR_IICMode_ARLIEN_Msk \ - (0x400000UL) /*!< USIC_CH PCR_IICMode: ARLIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_IICMode_SRRIEN_Pos \ - (23UL) /*!< USIC_CH PCR_IICMode: SRRIEN (Bit 23) */ -#define USIC_CH_PCR_IICMode_SRRIEN_Msk \ - (0x800000UL) /*!< USIC_CH PCR_IICMode: SRRIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_IICMode_ERRIEN_Pos \ - (24UL) /*!< USIC_CH PCR_IICMode: ERRIEN (Bit 24) */ -#define USIC_CH_PCR_IICMode_ERRIEN_Msk \ - (0x1000000UL) /*!< USIC_CH PCR_IICMode: ERRIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_IICMode_SACKDIS_Pos \ - (25UL) /*!< USIC_CH PCR_IICMode: SACKDIS (Bit 25) */ -#define USIC_CH_PCR_IICMode_SACKDIS_Msk \ - (0x2000000UL) /*!< USIC_CH PCR_IICMode: SACKDIS (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_IICMode_HDEL_Pos \ - (26UL) /*!< USIC_CH PCR_IICMode: HDEL (Bit 26) */ -#define USIC_CH_PCR_IICMode_HDEL_Msk \ - (0x3c000000UL) /*!< USIC_CH PCR_IICMode: HDEL (Bitfield-Mask: 0x0f) */ -#define USIC_CH_PCR_IICMode_ACKIEN_Pos \ - (30UL) /*!< USIC_CH PCR_IICMode: ACKIEN (Bit 30) */ -#define USIC_CH_PCR_IICMode_ACKIEN_Msk \ - (0x40000000UL) /*!< USIC_CH PCR_IICMode: ACKIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_IICMode_MCLK_Pos \ - (31UL) /*!< USIC_CH PCR_IICMode: MCLK (Bit 31) */ -#define USIC_CH_PCR_IICMode_MCLK_Msk \ - (0x80000000UL) /*!< USIC_CH PCR_IICMode: MCLK (Bitfield-Mask: 0x01) */ - -/* ----------------------------- USIC_CH_PCR_IISMode ---------------------------- */ -#define USIC_CH_PCR_IISMode_WAGEN_Pos \ - (0UL) /*!< USIC_CH PCR_IISMode: WAGEN (Bit 0) */ -#define USIC_CH_PCR_IISMode_WAGEN_Msk \ - (0x1UL) /*!< USIC_CH PCR_IISMode: WAGEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_IISMode_DTEN_Pos \ - (1UL) /*!< USIC_CH PCR_IISMode: DTEN (Bit 1) */ -#define USIC_CH_PCR_IISMode_DTEN_Msk \ - (0x2UL) /*!< USIC_CH PCR_IISMode: DTEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_IISMode_SELINV_Pos \ - (2UL) /*!< USIC_CH PCR_IISMode: SELINV (Bit 2) */ -#define USIC_CH_PCR_IISMode_SELINV_Msk \ - (0x4UL) /*!< USIC_CH PCR_IISMode: SELINV (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_IISMode_WAFEIEN_Pos \ - (4UL) /*!< USIC_CH PCR_IISMode: WAFEIEN (Bit 4) */ -#define USIC_CH_PCR_IISMode_WAFEIEN_Msk \ - (0x10UL) /*!< USIC_CH PCR_IISMode: WAFEIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_IISMode_WAREIEN_Pos \ - (5UL) /*!< USIC_CH PCR_IISMode: WAREIEN (Bit 5) */ -#define USIC_CH_PCR_IISMode_WAREIEN_Msk \ - (0x20UL) /*!< USIC_CH PCR_IISMode: WAREIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_IISMode_ENDIEN_Pos \ - (6UL) /*!< USIC_CH PCR_IISMode: ENDIEN (Bit 6) */ -#define USIC_CH_PCR_IISMode_ENDIEN_Msk \ - (0x40UL) /*!< USIC_CH PCR_IISMode: ENDIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_IISMode_DX2TIEN_Pos \ - (15UL) /*!< USIC_CH PCR_IISMode: DX2TIEN (Bit 15) */ -#define USIC_CH_PCR_IISMode_DX2TIEN_Msk \ - (0x8000UL) /*!< USIC_CH PCR_IISMode: DX2TIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_IISMode_TDEL_Pos \ - (16UL) /*!< USIC_CH PCR_IISMode: TDEL (Bit 16) */ -#define USIC_CH_PCR_IISMode_TDEL_Msk \ - (0x3f0000UL) /*!< USIC_CH PCR_IISMode: TDEL (Bitfield-Mask: 0x3f) */ -#define USIC_CH_PCR_IISMode_MCLK_Pos \ - (31UL) /*!< USIC_CH PCR_IISMode: MCLK (Bit 31) */ -#define USIC_CH_PCR_IISMode_MCLK_Msk \ - (0x80000000UL) /*!< USIC_CH PCR_IISMode: MCLK (Bitfield-Mask: 0x01) */ - -/* --------------------------------- USIC_CH_CCR -------------------------------- */ -#define USIC_CH_CCR_MODE_Pos \ - (0UL) /*!< USIC_CH CCR: MODE (Bit 0) */ -#define USIC_CH_CCR_MODE_Msk \ - (0xfUL) /*!< USIC_CH CCR: MODE (Bitfield-Mask: 0x0f) */ -#define USIC_CH_CCR_HPCEN_Pos \ - (6UL) /*!< USIC_CH CCR: HPCEN (Bit 6) */ -#define USIC_CH_CCR_HPCEN_Msk \ - (0xc0UL) /*!< USIC_CH CCR: HPCEN (Bitfield-Mask: 0x03) */ -#define USIC_CH_CCR_PM_Pos (8UL) /*!< USIC_CH CCR: PM (Bit 8) */ -#define USIC_CH_CCR_PM_Msk \ - (0x300UL) /*!< USIC_CH CCR: PM (Bitfield-Mask: 0x03) */ -#define USIC_CH_CCR_RSIEN_Pos \ - (10UL) /*!< USIC_CH CCR: RSIEN (Bit 10) */ -#define USIC_CH_CCR_RSIEN_Msk \ - (0x400UL) /*!< USIC_CH CCR: RSIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_CCR_DLIEN_Pos \ - (11UL) /*!< USIC_CH CCR: DLIEN (Bit 11) */ -#define USIC_CH_CCR_DLIEN_Msk \ - (0x800UL) /*!< USIC_CH CCR: DLIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_CCR_TSIEN_Pos \ - (12UL) /*!< USIC_CH CCR: TSIEN (Bit 12) */ -#define USIC_CH_CCR_TSIEN_Msk \ - (0x1000UL) /*!< USIC_CH CCR: TSIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_CCR_TBIEN_Pos \ - (13UL) /*!< USIC_CH CCR: TBIEN (Bit 13) */ -#define USIC_CH_CCR_TBIEN_Msk \ - (0x2000UL) /*!< USIC_CH CCR: TBIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_CCR_RIEN_Pos \ - (14UL) /*!< USIC_CH CCR: RIEN (Bit 14) */ -#define USIC_CH_CCR_RIEN_Msk \ - (0x4000UL) /*!< USIC_CH CCR: RIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_CCR_AIEN_Pos \ - (15UL) /*!< USIC_CH CCR: AIEN (Bit 15) */ -#define USIC_CH_CCR_AIEN_Msk \ - (0x8000UL) /*!< USIC_CH CCR: AIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_CCR_BRGIEN_Pos \ - (16UL) /*!< USIC_CH CCR: BRGIEN (Bit 16) */ -#define USIC_CH_CCR_BRGIEN_Msk \ - (0x10000UL) /*!< USIC_CH CCR: BRGIEN (Bitfield-Mask: 0x01) */ - -/* -------------------------------- USIC_CH_CMTR -------------------------------- */ -#define USIC_CH_CMTR_CTV_Pos \ - (0UL) /*!< USIC_CH CMTR: CTV (Bit 0) */ -#define USIC_CH_CMTR_CTV_Msk \ - (0x3ffUL) /*!< USIC_CH CMTR: CTV (Bitfield-Mask: 0x3ff) */ - -/* --------------------------------- USIC_CH_PSR -------------------------------- */ -#define USIC_CH_PSR_ST0_Pos \ - (0UL) /*!< USIC_CH PSR: ST0 (Bit 0) */ -#define USIC_CH_PSR_ST0_Msk \ - (0x1UL) /*!< USIC_CH PSR: ST0 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_ST1_Pos \ - (1UL) /*!< USIC_CH PSR: ST1 (Bit 1) */ -#define USIC_CH_PSR_ST1_Msk \ - (0x2UL) /*!< USIC_CH PSR: ST1 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_ST2_Pos \ - (2UL) /*!< USIC_CH PSR: ST2 (Bit 2) */ -#define USIC_CH_PSR_ST2_Msk \ - (0x4UL) /*!< USIC_CH PSR: ST2 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_ST3_Pos \ - (3UL) /*!< USIC_CH PSR: ST3 (Bit 3) */ -#define USIC_CH_PSR_ST3_Msk \ - (0x8UL) /*!< USIC_CH PSR: ST3 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_ST4_Pos \ - (4UL) /*!< USIC_CH PSR: ST4 (Bit 4) */ -#define USIC_CH_PSR_ST4_Msk \ - (0x10UL) /*!< USIC_CH PSR: ST4 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_ST5_Pos \ - (5UL) /*!< USIC_CH PSR: ST5 (Bit 5) */ -#define USIC_CH_PSR_ST5_Msk \ - (0x20UL) /*!< USIC_CH PSR: ST5 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_ST6_Pos \ - (6UL) /*!< USIC_CH PSR: ST6 (Bit 6) */ -#define USIC_CH_PSR_ST6_Msk \ - (0x40UL) /*!< USIC_CH PSR: ST6 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_ST7_Pos \ - (7UL) /*!< USIC_CH PSR: ST7 (Bit 7) */ -#define USIC_CH_PSR_ST7_Msk \ - (0x80UL) /*!< USIC_CH PSR: ST7 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_ST8_Pos \ - (8UL) /*!< USIC_CH PSR: ST8 (Bit 8) */ -#define USIC_CH_PSR_ST8_Msk \ - (0x100UL) /*!< USIC_CH PSR: ST8 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_ST9_Pos \ - (9UL) /*!< USIC_CH PSR: ST9 (Bit 9) */ -#define USIC_CH_PSR_ST9_Msk \ - (0x200UL) /*!< USIC_CH PSR: ST9 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_RSIF_Pos \ - (10UL) /*!< USIC_CH PSR: RSIF (Bit 10) */ -#define USIC_CH_PSR_RSIF_Msk \ - (0x400UL) /*!< USIC_CH PSR: RSIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_DLIF_Pos \ - (11UL) /*!< USIC_CH PSR: DLIF (Bit 11) */ -#define USIC_CH_PSR_DLIF_Msk \ - (0x800UL) /*!< USIC_CH PSR: DLIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_TSIF_Pos \ - (12UL) /*!< USIC_CH PSR: TSIF (Bit 12) */ -#define USIC_CH_PSR_TSIF_Msk \ - (0x1000UL) /*!< USIC_CH PSR: TSIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_TBIF_Pos \ - (13UL) /*!< USIC_CH PSR: TBIF (Bit 13) */ -#define USIC_CH_PSR_TBIF_Msk \ - (0x2000UL) /*!< USIC_CH PSR: TBIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_RIF_Pos \ - (14UL) /*!< USIC_CH PSR: RIF (Bit 14) */ -#define USIC_CH_PSR_RIF_Msk \ - (0x4000UL) /*!< USIC_CH PSR: RIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_AIF_Pos \ - (15UL) /*!< USIC_CH PSR: AIF (Bit 15) */ -#define USIC_CH_PSR_AIF_Msk \ - (0x8000UL) /*!< USIC_CH PSR: AIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_BRGIF_Pos \ - (16UL) /*!< USIC_CH PSR: BRGIF (Bit 16) */ -#define USIC_CH_PSR_BRGIF_Msk \ - (0x10000UL) /*!< USIC_CH PSR: BRGIF (Bitfield-Mask: 0x01) */ - -/* ----------------------------- USIC_CH_PSR_ASCMode ---------------------------- */ -#define USIC_CH_PSR_ASCMode_TXIDLE_Pos \ - (0UL) /*!< USIC_CH PSR_ASCMode: TXIDLE (Bit 0) */ -#define USIC_CH_PSR_ASCMode_TXIDLE_Msk \ - (0x1UL) /*!< USIC_CH PSR_ASCMode: TXIDLE (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_ASCMode_RXIDLE_Pos \ - (1UL) /*!< USIC_CH PSR_ASCMode: RXIDLE (Bit 1) */ -#define USIC_CH_PSR_ASCMode_RXIDLE_Msk \ - (0x2UL) /*!< USIC_CH PSR_ASCMode: RXIDLE (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_ASCMode_SBD_Pos \ - (2UL) /*!< USIC_CH PSR_ASCMode: SBD (Bit 2) */ -#define USIC_CH_PSR_ASCMode_SBD_Msk \ - (0x4UL) /*!< USIC_CH PSR_ASCMode: SBD (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_ASCMode_COL_Pos \ - (3UL) /*!< USIC_CH PSR_ASCMode: COL (Bit 3) */ -#define USIC_CH_PSR_ASCMode_COL_Msk \ - (0x8UL) /*!< USIC_CH PSR_ASCMode: COL (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_ASCMode_RNS_Pos \ - (4UL) /*!< USIC_CH PSR_ASCMode: RNS (Bit 4) */ -#define USIC_CH_PSR_ASCMode_RNS_Msk \ - (0x10UL) /*!< USIC_CH PSR_ASCMode: RNS (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_ASCMode_FER0_Pos \ - (5UL) /*!< USIC_CH PSR_ASCMode: FER0 (Bit 5) */ -#define USIC_CH_PSR_ASCMode_FER0_Msk \ - (0x20UL) /*!< USIC_CH PSR_ASCMode: FER0 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_ASCMode_FER1_Pos \ - (6UL) /*!< USIC_CH PSR_ASCMode: FER1 (Bit 6) */ -#define USIC_CH_PSR_ASCMode_FER1_Msk \ - (0x40UL) /*!< USIC_CH PSR_ASCMode: FER1 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_ASCMode_RFF_Pos \ - (7UL) /*!< USIC_CH PSR_ASCMode: RFF (Bit 7) */ -#define USIC_CH_PSR_ASCMode_RFF_Msk \ - (0x80UL) /*!< USIC_CH PSR_ASCMode: RFF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_ASCMode_TFF_Pos \ - (8UL) /*!< USIC_CH PSR_ASCMode: TFF (Bit 8) */ -#define USIC_CH_PSR_ASCMode_TFF_Msk \ - (0x100UL) /*!< USIC_CH PSR_ASCMode: TFF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_ASCMode_BUSY_Pos \ - (9UL) /*!< USIC_CH PSR_ASCMode: BUSY (Bit 9) */ -#define USIC_CH_PSR_ASCMode_BUSY_Msk \ - (0x200UL) /*!< USIC_CH PSR_ASCMode: BUSY (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_ASCMode_RSIF_Pos \ - (10UL) /*!< USIC_CH PSR_ASCMode: RSIF (Bit 10) */ -#define USIC_CH_PSR_ASCMode_RSIF_Msk \ - (0x400UL) /*!< USIC_CH PSR_ASCMode: RSIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_ASCMode_DLIF_Pos \ - (11UL) /*!< USIC_CH PSR_ASCMode: DLIF (Bit 11) */ -#define USIC_CH_PSR_ASCMode_DLIF_Msk \ - (0x800UL) /*!< USIC_CH PSR_ASCMode: DLIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_ASCMode_TSIF_Pos \ - (12UL) /*!< USIC_CH PSR_ASCMode: TSIF (Bit 12) */ -#define USIC_CH_PSR_ASCMode_TSIF_Msk \ - (0x1000UL) /*!< USIC_CH PSR_ASCMode: TSIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_ASCMode_TBIF_Pos \ - (13UL) /*!< USIC_CH PSR_ASCMode: TBIF (Bit 13) */ -#define USIC_CH_PSR_ASCMode_TBIF_Msk \ - (0x2000UL) /*!< USIC_CH PSR_ASCMode: TBIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_ASCMode_RIF_Pos \ - (14UL) /*!< USIC_CH PSR_ASCMode: RIF (Bit 14) */ -#define USIC_CH_PSR_ASCMode_RIF_Msk \ - (0x4000UL) /*!< USIC_CH PSR_ASCMode: RIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_ASCMode_AIF_Pos \ - (15UL) /*!< USIC_CH PSR_ASCMode: AIF (Bit 15) */ -#define USIC_CH_PSR_ASCMode_AIF_Msk \ - (0x8000UL) /*!< USIC_CH PSR_ASCMode: AIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_ASCMode_BRGIF_Pos \ - (16UL) /*!< USIC_CH PSR_ASCMode: BRGIF (Bit 16) */ -#define USIC_CH_PSR_ASCMode_BRGIF_Msk \ - (0x10000UL) /*!< USIC_CH PSR_ASCMode: BRGIF (Bitfield-Mask: 0x01) */ - -/* ----------------------------- USIC_CH_PSR_SSCMode ---------------------------- */ -#define USIC_CH_PSR_SSCMode_MSLS_Pos \ - (0UL) /*!< USIC_CH PSR_SSCMode: MSLS (Bit 0) */ -#define USIC_CH_PSR_SSCMode_MSLS_Msk \ - (0x1UL) /*!< USIC_CH PSR_SSCMode: MSLS (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_SSCMode_DX2S_Pos \ - (1UL) /*!< USIC_CH PSR_SSCMode: DX2S (Bit 1) */ -#define USIC_CH_PSR_SSCMode_DX2S_Msk \ - (0x2UL) /*!< USIC_CH PSR_SSCMode: DX2S (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_SSCMode_MSLSEV_Pos \ - (2UL) /*!< USIC_CH PSR_SSCMode: MSLSEV (Bit 2) */ -#define USIC_CH_PSR_SSCMode_MSLSEV_Msk \ - (0x4UL) /*!< USIC_CH PSR_SSCMode: MSLSEV (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_SSCMode_DX2TEV_Pos \ - (3UL) /*!< USIC_CH PSR_SSCMode: DX2TEV (Bit 3) */ -#define USIC_CH_PSR_SSCMode_DX2TEV_Msk \ - (0x8UL) /*!< USIC_CH PSR_SSCMode: DX2TEV (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_SSCMode_PARERR_Pos \ - (4UL) /*!< USIC_CH PSR_SSCMode: PARERR (Bit 4) */ -#define USIC_CH_PSR_SSCMode_PARERR_Msk \ - (0x10UL) /*!< USIC_CH PSR_SSCMode: PARERR (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_SSCMode_RSIF_Pos \ - (10UL) /*!< USIC_CH PSR_SSCMode: RSIF (Bit 10) */ -#define USIC_CH_PSR_SSCMode_RSIF_Msk \ - (0x400UL) /*!< USIC_CH PSR_SSCMode: RSIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_SSCMode_DLIF_Pos \ - (11UL) /*!< USIC_CH PSR_SSCMode: DLIF (Bit 11) */ -#define USIC_CH_PSR_SSCMode_DLIF_Msk \ - (0x800UL) /*!< USIC_CH PSR_SSCMode: DLIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_SSCMode_TSIF_Pos \ - (12UL) /*!< USIC_CH PSR_SSCMode: TSIF (Bit 12) */ -#define USIC_CH_PSR_SSCMode_TSIF_Msk \ - (0x1000UL) /*!< USIC_CH PSR_SSCMode: TSIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_SSCMode_TBIF_Pos \ - (13UL) /*!< USIC_CH PSR_SSCMode: TBIF (Bit 13) */ -#define USIC_CH_PSR_SSCMode_TBIF_Msk \ - (0x2000UL) /*!< USIC_CH PSR_SSCMode: TBIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_SSCMode_RIF_Pos \ - (14UL) /*!< USIC_CH PSR_SSCMode: RIF (Bit 14) */ -#define USIC_CH_PSR_SSCMode_RIF_Msk \ - (0x4000UL) /*!< USIC_CH PSR_SSCMode: RIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_SSCMode_AIF_Pos \ - (15UL) /*!< USIC_CH PSR_SSCMode: AIF (Bit 15) */ -#define USIC_CH_PSR_SSCMode_AIF_Msk \ - (0x8000UL) /*!< USIC_CH PSR_SSCMode: AIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_SSCMode_BRGIF_Pos \ - (16UL) /*!< USIC_CH PSR_SSCMode: BRGIF (Bit 16) */ -#define USIC_CH_PSR_SSCMode_BRGIF_Msk \ - (0x10000UL) /*!< USIC_CH PSR_SSCMode: BRGIF (Bitfield-Mask: 0x01) */ - -/* ----------------------------- USIC_CH_PSR_IICMode ---------------------------- */ -#define USIC_CH_PSR_IICMode_SLSEL_Pos \ - (0UL) /*!< USIC_CH PSR_IICMode: SLSEL (Bit 0) */ -#define USIC_CH_PSR_IICMode_SLSEL_Msk \ - (0x1UL) /*!< USIC_CH PSR_IICMode: SLSEL (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IICMode_WTDF_Pos \ - (1UL) /*!< USIC_CH PSR_IICMode: WTDF (Bit 1) */ -#define USIC_CH_PSR_IICMode_WTDF_Msk \ - (0x2UL) /*!< USIC_CH PSR_IICMode: WTDF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IICMode_SCR_Pos \ - (2UL) /*!< USIC_CH PSR_IICMode: SCR (Bit 2) */ -#define USIC_CH_PSR_IICMode_SCR_Msk \ - (0x4UL) /*!< USIC_CH PSR_IICMode: SCR (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IICMode_RSCR_Pos \ - (3UL) /*!< USIC_CH PSR_IICMode: RSCR (Bit 3) */ -#define USIC_CH_PSR_IICMode_RSCR_Msk \ - (0x8UL) /*!< USIC_CH PSR_IICMode: RSCR (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IICMode_PCR_Pos \ - (4UL) /*!< USIC_CH PSR_IICMode: PCR (Bit 4) */ -#define USIC_CH_PSR_IICMode_PCR_Msk \ - (0x10UL) /*!< USIC_CH PSR_IICMode: PCR (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IICMode_NACK_Pos \ - (5UL) /*!< USIC_CH PSR_IICMode: NACK (Bit 5) */ -#define USIC_CH_PSR_IICMode_NACK_Msk \ - (0x20UL) /*!< USIC_CH PSR_IICMode: NACK (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IICMode_ARL_Pos \ - (6UL) /*!< USIC_CH PSR_IICMode: ARL (Bit 6) */ -#define USIC_CH_PSR_IICMode_ARL_Msk \ - (0x40UL) /*!< USIC_CH PSR_IICMode: ARL (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IICMode_SRR_Pos \ - (7UL) /*!< USIC_CH PSR_IICMode: SRR (Bit 7) */ -#define USIC_CH_PSR_IICMode_SRR_Msk \ - (0x80UL) /*!< USIC_CH PSR_IICMode: SRR (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IICMode_ERR_Pos \ - (8UL) /*!< USIC_CH PSR_IICMode: ERR (Bit 8) */ -#define USIC_CH_PSR_IICMode_ERR_Msk \ - (0x100UL) /*!< USIC_CH PSR_IICMode: ERR (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IICMode_ACK_Pos \ - (9UL) /*!< USIC_CH PSR_IICMode: ACK (Bit 9) */ -#define USIC_CH_PSR_IICMode_ACK_Msk \ - (0x200UL) /*!< USIC_CH PSR_IICMode: ACK (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IICMode_RSIF_Pos \ - (10UL) /*!< USIC_CH PSR_IICMode: RSIF (Bit 10) */ -#define USIC_CH_PSR_IICMode_RSIF_Msk \ - (0x400UL) /*!< USIC_CH PSR_IICMode: RSIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IICMode_DLIF_Pos \ - (11UL) /*!< USIC_CH PSR_IICMode: DLIF (Bit 11) */ -#define USIC_CH_PSR_IICMode_DLIF_Msk \ - (0x800UL) /*!< USIC_CH PSR_IICMode: DLIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IICMode_TSIF_Pos \ - (12UL) /*!< USIC_CH PSR_IICMode: TSIF (Bit 12) */ -#define USIC_CH_PSR_IICMode_TSIF_Msk \ - (0x1000UL) /*!< USIC_CH PSR_IICMode: TSIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IICMode_TBIF_Pos \ - (13UL) /*!< USIC_CH PSR_IICMode: TBIF (Bit 13) */ -#define USIC_CH_PSR_IICMode_TBIF_Msk \ - (0x2000UL) /*!< USIC_CH PSR_IICMode: TBIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IICMode_RIF_Pos \ - (14UL) /*!< USIC_CH PSR_IICMode: RIF (Bit 14) */ -#define USIC_CH_PSR_IICMode_RIF_Msk \ - (0x4000UL) /*!< USIC_CH PSR_IICMode: RIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IICMode_AIF_Pos \ - (15UL) /*!< USIC_CH PSR_IICMode: AIF (Bit 15) */ -#define USIC_CH_PSR_IICMode_AIF_Msk \ - (0x8000UL) /*!< USIC_CH PSR_IICMode: AIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IICMode_BRGIF_Pos \ - (16UL) /*!< USIC_CH PSR_IICMode: BRGIF (Bit 16) */ -#define USIC_CH_PSR_IICMode_BRGIF_Msk \ - (0x10000UL) /*!< USIC_CH PSR_IICMode: BRGIF (Bitfield-Mask: 0x01) */ - -/* ----------------------------- USIC_CH_PSR_IISMode ---------------------------- */ -#define USIC_CH_PSR_IISMode_WA_Pos \ - (0UL) /*!< USIC_CH PSR_IISMode: WA (Bit 0) */ -#define USIC_CH_PSR_IISMode_WA_Msk \ - (0x1UL) /*!< USIC_CH PSR_IISMode: WA (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IISMode_DX2S_Pos \ - (1UL) /*!< USIC_CH PSR_IISMode: DX2S (Bit 1) */ -#define USIC_CH_PSR_IISMode_DX2S_Msk \ - (0x2UL) /*!< USIC_CH PSR_IISMode: DX2S (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IISMode_DX2TEV_Pos \ - (3UL) /*!< USIC_CH PSR_IISMode: DX2TEV (Bit 3) */ -#define USIC_CH_PSR_IISMode_DX2TEV_Msk \ - (0x8UL) /*!< USIC_CH PSR_IISMode: DX2TEV (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IISMode_WAFE_Pos \ - (4UL) /*!< USIC_CH PSR_IISMode: WAFE (Bit 4) */ -#define USIC_CH_PSR_IISMode_WAFE_Msk \ - (0x10UL) /*!< USIC_CH PSR_IISMode: WAFE (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IISMode_WARE_Pos \ - (5UL) /*!< USIC_CH PSR_IISMode: WARE (Bit 5) */ -#define USIC_CH_PSR_IISMode_WARE_Msk \ - (0x20UL) /*!< USIC_CH PSR_IISMode: WARE (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IISMode_END_Pos \ - (6UL) /*!< USIC_CH PSR_IISMode: END (Bit 6) */ -#define USIC_CH_PSR_IISMode_END_Msk \ - (0x40UL) /*!< USIC_CH PSR_IISMode: END (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IISMode_RSIF_Pos \ - (10UL) /*!< USIC_CH PSR_IISMode: RSIF (Bit 10) */ -#define USIC_CH_PSR_IISMode_RSIF_Msk \ - (0x400UL) /*!< USIC_CH PSR_IISMode: RSIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IISMode_DLIF_Pos \ - (11UL) /*!< USIC_CH PSR_IISMode: DLIF (Bit 11) */ -#define USIC_CH_PSR_IISMode_DLIF_Msk \ - (0x800UL) /*!< USIC_CH PSR_IISMode: DLIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IISMode_TSIF_Pos \ - (12UL) /*!< USIC_CH PSR_IISMode: TSIF (Bit 12) */ -#define USIC_CH_PSR_IISMode_TSIF_Msk \ - (0x1000UL) /*!< USIC_CH PSR_IISMode: TSIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IISMode_TBIF_Pos \ - (13UL) /*!< USIC_CH PSR_IISMode: TBIF (Bit 13) */ -#define USIC_CH_PSR_IISMode_TBIF_Msk \ - (0x2000UL) /*!< USIC_CH PSR_IISMode: TBIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IISMode_RIF_Pos \ - (14UL) /*!< USIC_CH PSR_IISMode: RIF (Bit 14) */ -#define USIC_CH_PSR_IISMode_RIF_Msk \ - (0x4000UL) /*!< USIC_CH PSR_IISMode: RIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IISMode_AIF_Pos \ - (15UL) /*!< USIC_CH PSR_IISMode: AIF (Bit 15) */ -#define USIC_CH_PSR_IISMode_AIF_Msk \ - (0x8000UL) /*!< USIC_CH PSR_IISMode: AIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IISMode_BRGIF_Pos \ - (16UL) /*!< USIC_CH PSR_IISMode: BRGIF (Bit 16) */ -#define USIC_CH_PSR_IISMode_BRGIF_Msk \ - (0x10000UL) /*!< USIC_CH PSR_IISMode: BRGIF (Bitfield-Mask: 0x01) */ - -/* -------------------------------- USIC_CH_PSCR -------------------------------- */ -#define USIC_CH_PSCR_CST0_Pos \ - (0UL) /*!< USIC_CH PSCR: CST0 (Bit 0) */ -#define USIC_CH_PSCR_CST0_Msk \ - (0x1UL) /*!< USIC_CH PSCR: CST0 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSCR_CST1_Pos \ - (1UL) /*!< USIC_CH PSCR: CST1 (Bit 1) */ -#define USIC_CH_PSCR_CST1_Msk \ - (0x2UL) /*!< USIC_CH PSCR: CST1 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSCR_CST2_Pos \ - (2UL) /*!< USIC_CH PSCR: CST2 (Bit 2) */ -#define USIC_CH_PSCR_CST2_Msk \ - (0x4UL) /*!< USIC_CH PSCR: CST2 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSCR_CST3_Pos \ - (3UL) /*!< USIC_CH PSCR: CST3 (Bit 3) */ -#define USIC_CH_PSCR_CST3_Msk \ - (0x8UL) /*!< USIC_CH PSCR: CST3 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSCR_CST4_Pos \ - (4UL) /*!< USIC_CH PSCR: CST4 (Bit 4) */ -#define USIC_CH_PSCR_CST4_Msk \ - (0x10UL) /*!< USIC_CH PSCR: CST4 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSCR_CST5_Pos \ - (5UL) /*!< USIC_CH PSCR: CST5 (Bit 5) */ -#define USIC_CH_PSCR_CST5_Msk \ - (0x20UL) /*!< USIC_CH PSCR: CST5 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSCR_CST6_Pos \ - (6UL) /*!< USIC_CH PSCR: CST6 (Bit 6) */ -#define USIC_CH_PSCR_CST6_Msk \ - (0x40UL) /*!< USIC_CH PSCR: CST6 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSCR_CST7_Pos \ - (7UL) /*!< USIC_CH PSCR: CST7 (Bit 7) */ -#define USIC_CH_PSCR_CST7_Msk \ - (0x80UL) /*!< USIC_CH PSCR: CST7 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSCR_CST8_Pos \ - (8UL) /*!< USIC_CH PSCR: CST8 (Bit 8) */ -#define USIC_CH_PSCR_CST8_Msk \ - (0x100UL) /*!< USIC_CH PSCR: CST8 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSCR_CST9_Pos \ - (9UL) /*!< USIC_CH PSCR: CST9 (Bit 9) */ -#define USIC_CH_PSCR_CST9_Msk \ - (0x200UL) /*!< USIC_CH PSCR: CST9 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSCR_CRSIF_Pos \ - (10UL) /*!< USIC_CH PSCR: CRSIF (Bit 10) */ -#define USIC_CH_PSCR_CRSIF_Msk \ - (0x400UL) /*!< USIC_CH PSCR: CRSIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSCR_CDLIF_Pos \ - (11UL) /*!< USIC_CH PSCR: CDLIF (Bit 11) */ -#define USIC_CH_PSCR_CDLIF_Msk \ - (0x800UL) /*!< USIC_CH PSCR: CDLIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSCR_CTSIF_Pos \ - (12UL) /*!< USIC_CH PSCR: CTSIF (Bit 12) */ -#define USIC_CH_PSCR_CTSIF_Msk \ - (0x1000UL) /*!< USIC_CH PSCR: CTSIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSCR_CTBIF_Pos \ - (13UL) /*!< USIC_CH PSCR: CTBIF (Bit 13) */ -#define USIC_CH_PSCR_CTBIF_Msk \ - (0x2000UL) /*!< USIC_CH PSCR: CTBIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSCR_CRIF_Pos \ - (14UL) /*!< USIC_CH PSCR: CRIF (Bit 14) */ -#define USIC_CH_PSCR_CRIF_Msk \ - (0x4000UL) /*!< USIC_CH PSCR: CRIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSCR_CAIF_Pos \ - (15UL) /*!< USIC_CH PSCR: CAIF (Bit 15) */ -#define USIC_CH_PSCR_CAIF_Msk \ - (0x8000UL) /*!< USIC_CH PSCR: CAIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSCR_CBRGIF_Pos \ - (16UL) /*!< USIC_CH PSCR: CBRGIF (Bit 16) */ -#define USIC_CH_PSCR_CBRGIF_Msk \ - (0x10000UL) /*!< USIC_CH PSCR: CBRGIF (Bitfield-Mask: 0x01) */ - -/* ------------------------------- USIC_CH_RBUFSR ------------------------------- */ -#define USIC_CH_RBUFSR_WLEN_Pos \ - (0UL) /*!< USIC_CH RBUFSR: WLEN (Bit 0) */ -#define USIC_CH_RBUFSR_WLEN_Msk \ - (0xfUL) /*!< USIC_CH RBUFSR: WLEN (Bitfield-Mask: 0x0f) */ -#define USIC_CH_RBUFSR_SOF_Pos \ - (6UL) /*!< USIC_CH RBUFSR: SOF (Bit 6) */ -#define USIC_CH_RBUFSR_SOF_Msk \ - (0x40UL) /*!< USIC_CH RBUFSR: SOF (Bitfield-Mask: 0x01) */ -#define USIC_CH_RBUFSR_PAR_Pos \ - (8UL) /*!< USIC_CH RBUFSR: PAR (Bit 8) */ -#define USIC_CH_RBUFSR_PAR_Msk \ - (0x100UL) /*!< USIC_CH RBUFSR: PAR (Bitfield-Mask: 0x01) */ -#define USIC_CH_RBUFSR_PERR_Pos \ - (9UL) /*!< USIC_CH RBUFSR: PERR (Bit 9) */ -#define USIC_CH_RBUFSR_PERR_Msk \ - (0x200UL) /*!< USIC_CH RBUFSR: PERR (Bitfield-Mask: 0x01) */ -#define USIC_CH_RBUFSR_RDV0_Pos \ - (13UL) /*!< USIC_CH RBUFSR: RDV0 (Bit 13) */ -#define USIC_CH_RBUFSR_RDV0_Msk \ - (0x2000UL) /*!< USIC_CH RBUFSR: RDV0 (Bitfield-Mask: 0x01) */ -#define USIC_CH_RBUFSR_RDV1_Pos \ - (14UL) /*!< USIC_CH RBUFSR: RDV1 (Bit 14) */ -#define USIC_CH_RBUFSR_RDV1_Msk \ - (0x4000UL) /*!< USIC_CH RBUFSR: RDV1 (Bitfield-Mask: 0x01) */ -#define USIC_CH_RBUFSR_DS_Pos \ - (15UL) /*!< USIC_CH RBUFSR: DS (Bit 15) */ -#define USIC_CH_RBUFSR_DS_Msk \ - (0x8000UL) /*!< USIC_CH RBUFSR: DS (Bitfield-Mask: 0x01) */ - -/* -------------------------------- USIC_CH_RBUF -------------------------------- */ -#define USIC_CH_RBUF_DSR_Pos \ - (0UL) /*!< USIC_CH RBUF: DSR (Bit 0) */ -#define USIC_CH_RBUF_DSR_Msk \ - (0xffffUL) /*!< USIC_CH RBUF: DSR (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- USIC_CH_RBUFD ------------------------------- */ -#define USIC_CH_RBUFD_DSR_Pos \ - (0UL) /*!< USIC_CH RBUFD: DSR (Bit 0) */ -#define USIC_CH_RBUFD_DSR_Msk \ - (0xffffUL) /*!< USIC_CH RBUFD: DSR (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- USIC_CH_RBUF0 ------------------------------- */ -#define USIC_CH_RBUF0_DSR0_Pos \ - (0UL) /*!< USIC_CH RBUF0: DSR0 (Bit 0) */ -#define USIC_CH_RBUF0_DSR0_Msk \ - (0xffffUL) /*!< USIC_CH RBUF0: DSR0 (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- USIC_CH_RBUF1 ------------------------------- */ -#define USIC_CH_RBUF1_DSR1_Pos \ - (0UL) /*!< USIC_CH RBUF1: DSR1 (Bit 0) */ -#define USIC_CH_RBUF1_DSR1_Msk \ - (0xffffUL) /*!< USIC_CH RBUF1: DSR1 (Bitfield-Mask: 0xffff) */ - -/* ------------------------------ USIC_CH_RBUF01SR ------------------------------ */ -#define USIC_CH_RBUF01SR_WLEN0_Pos \ - (0UL) /*!< USIC_CH RBUF01SR: WLEN0 (Bit 0) */ -#define USIC_CH_RBUF01SR_WLEN0_Msk \ - (0xfUL) /*!< USIC_CH RBUF01SR: WLEN0 (Bitfield-Mask: 0x0f) */ -#define USIC_CH_RBUF01SR_SOF0_Pos \ - (6UL) /*!< USIC_CH RBUF01SR: SOF0 (Bit 6) */ -#define USIC_CH_RBUF01SR_SOF0_Msk \ - (0x40UL) /*!< USIC_CH RBUF01SR: SOF0 (Bitfield-Mask: 0x01) */ -#define USIC_CH_RBUF01SR_PAR0_Pos \ - (8UL) /*!< USIC_CH RBUF01SR: PAR0 (Bit 8) */ -#define USIC_CH_RBUF01SR_PAR0_Msk \ - (0x100UL) /*!< USIC_CH RBUF01SR: PAR0 (Bitfield-Mask: 0x01) */ -#define USIC_CH_RBUF01SR_PERR0_Pos \ - (9UL) /*!< USIC_CH RBUF01SR: PERR0 (Bit 9) */ -#define USIC_CH_RBUF01SR_PERR0_Msk \ - (0x200UL) /*!< USIC_CH RBUF01SR: PERR0 (Bitfield-Mask: 0x01) */ -#define USIC_CH_RBUF01SR_RDV00_Pos \ - (13UL) /*!< USIC_CH RBUF01SR: RDV00 (Bit 13) */ -#define USIC_CH_RBUF01SR_RDV00_Msk \ - (0x2000UL) /*!< USIC_CH RBUF01SR: RDV00 (Bitfield-Mask: 0x01) */ -#define USIC_CH_RBUF01SR_RDV01_Pos \ - (14UL) /*!< USIC_CH RBUF01SR: RDV01 (Bit 14) */ -#define USIC_CH_RBUF01SR_RDV01_Msk \ - (0x4000UL) /*!< USIC_CH RBUF01SR: RDV01 (Bitfield-Mask: 0x01) */ -#define USIC_CH_RBUF01SR_DS0_Pos \ - (15UL) /*!< USIC_CH RBUF01SR: DS0 (Bit 15) */ -#define USIC_CH_RBUF01SR_DS0_Msk \ - (0x8000UL) /*!< USIC_CH RBUF01SR: DS0 (Bitfield-Mask: 0x01) */ -#define USIC_CH_RBUF01SR_WLEN1_Pos \ - (16UL) /*!< USIC_CH RBUF01SR: WLEN1 (Bit 16) */ -#define USIC_CH_RBUF01SR_WLEN1_Msk \ - (0xf0000UL) /*!< USIC_CH RBUF01SR: WLEN1 (Bitfield-Mask: 0x0f) */ -#define USIC_CH_RBUF01SR_SOF1_Pos \ - (22UL) /*!< USIC_CH RBUF01SR: SOF1 (Bit 22) */ -#define USIC_CH_RBUF01SR_SOF1_Msk \ - (0x400000UL) /*!< USIC_CH RBUF01SR: SOF1 (Bitfield-Mask: 0x01) */ -#define USIC_CH_RBUF01SR_PAR1_Pos \ - (24UL) /*!< USIC_CH RBUF01SR: PAR1 (Bit 24) */ -#define USIC_CH_RBUF01SR_PAR1_Msk \ - (0x1000000UL) /*!< USIC_CH RBUF01SR: PAR1 (Bitfield-Mask: 0x01) */ -#define USIC_CH_RBUF01SR_PERR1_Pos \ - (25UL) /*!< USIC_CH RBUF01SR: PERR1 (Bit 25) */ -#define USIC_CH_RBUF01SR_PERR1_Msk \ - (0x2000000UL) /*!< USIC_CH RBUF01SR: PERR1 (Bitfield-Mask: 0x01) */ -#define USIC_CH_RBUF01SR_RDV10_Pos \ - (29UL) /*!< USIC_CH RBUF01SR: RDV10 (Bit 29) */ -#define USIC_CH_RBUF01SR_RDV10_Msk \ - (0x20000000UL) /*!< USIC_CH RBUF01SR: RDV10 (Bitfield-Mask: 0x01) */ -#define USIC_CH_RBUF01SR_RDV11_Pos \ - (30UL) /*!< USIC_CH RBUF01SR: RDV11 (Bit 30) */ -#define USIC_CH_RBUF01SR_RDV11_Msk \ - (0x40000000UL) /*!< USIC_CH RBUF01SR: RDV11 (Bitfield-Mask: 0x01) */ -#define USIC_CH_RBUF01SR_DS1_Pos \ - (31UL) /*!< USIC_CH RBUF01SR: DS1 (Bit 31) */ -#define USIC_CH_RBUF01SR_DS1_Msk \ - (0x80000000UL) /*!< USIC_CH RBUF01SR: DS1 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- USIC_CH_FMR -------------------------------- */ -#define USIC_CH_FMR_MTDV_Pos \ - (0UL) /*!< USIC_CH FMR: MTDV (Bit 0) */ -#define USIC_CH_FMR_MTDV_Msk \ - (0x3UL) /*!< USIC_CH FMR: MTDV (Bitfield-Mask: 0x03) */ -#define USIC_CH_FMR_ATVC_Pos \ - (4UL) /*!< USIC_CH FMR: ATVC (Bit 4) */ -#define USIC_CH_FMR_ATVC_Msk \ - (0x10UL) /*!< USIC_CH FMR: ATVC (Bitfield-Mask: 0x01) */ -#define USIC_CH_FMR_CRDV0_Pos \ - (14UL) /*!< USIC_CH FMR: CRDV0 (Bit 14) */ -#define USIC_CH_FMR_CRDV0_Msk \ - (0x4000UL) /*!< USIC_CH FMR: CRDV0 (Bitfield-Mask: 0x01) */ -#define USIC_CH_FMR_CRDV1_Pos \ - (15UL) /*!< USIC_CH FMR: CRDV1 (Bit 15) */ -#define USIC_CH_FMR_CRDV1_Msk \ - (0x8000UL) /*!< USIC_CH FMR: CRDV1 (Bitfield-Mask: 0x01) */ -#define USIC_CH_FMR_SIO0_Pos \ - (16UL) /*!< USIC_CH FMR: SIO0 (Bit 16) */ -#define USIC_CH_FMR_SIO0_Msk \ - (0x10000UL) /*!< USIC_CH FMR: SIO0 (Bitfield-Mask: 0x01) */ -#define USIC_CH_FMR_SIO1_Pos \ - (17UL) /*!< USIC_CH FMR: SIO1 (Bit 17) */ -#define USIC_CH_FMR_SIO1_Msk \ - (0x20000UL) /*!< USIC_CH FMR: SIO1 (Bitfield-Mask: 0x01) */ -#define USIC_CH_FMR_SIO2_Pos \ - (18UL) /*!< USIC_CH FMR: SIO2 (Bit 18) */ -#define USIC_CH_FMR_SIO2_Msk \ - (0x40000UL) /*!< USIC_CH FMR: SIO2 (Bitfield-Mask: 0x01) */ -#define USIC_CH_FMR_SIO3_Pos \ - (19UL) /*!< USIC_CH FMR: SIO3 (Bit 19) */ -#define USIC_CH_FMR_SIO3_Msk \ - (0x80000UL) /*!< USIC_CH FMR: SIO3 (Bitfield-Mask: 0x01) */ -#define USIC_CH_FMR_SIO4_Pos \ - (20UL) /*!< USIC_CH FMR: SIO4 (Bit 20) */ -#define USIC_CH_FMR_SIO4_Msk \ - (0x100000UL) /*!< USIC_CH FMR: SIO4 (Bitfield-Mask: 0x01) */ -#define USIC_CH_FMR_SIO5_Pos \ - (21UL) /*!< USIC_CH FMR: SIO5 (Bit 21) */ -#define USIC_CH_FMR_SIO5_Msk \ - (0x200000UL) /*!< USIC_CH FMR: SIO5 (Bitfield-Mask: 0x01) */ - -/* -------------------------------- USIC_CH_TBUF -------------------------------- */ -#define USIC_CH_TBUF_TDATA_Pos \ - (0UL) /*!< USIC_CH TBUF: TDATA (Bit 0) */ -#define USIC_CH_TBUF_TDATA_Msk \ - (0xffffUL) /*!< USIC_CH TBUF: TDATA (Bitfield-Mask: 0xffff) */ - -/* --------------------------------- USIC_CH_BYP -------------------------------- */ -#define USIC_CH_BYP_BDATA_Pos \ - (0UL) /*!< USIC_CH BYP: BDATA (Bit 0) */ -#define USIC_CH_BYP_BDATA_Msk \ - (0xffffUL) /*!< USIC_CH BYP: BDATA (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- USIC_CH_BYPCR ------------------------------- */ -#define USIC_CH_BYPCR_BWLE_Pos \ - (0UL) /*!< USIC_CH BYPCR: BWLE (Bit 0) */ -#define USIC_CH_BYPCR_BWLE_Msk \ - (0xfUL) /*!< USIC_CH BYPCR: BWLE (Bitfield-Mask: 0x0f) */ -#define USIC_CH_BYPCR_BDSSM_Pos \ - (8UL) /*!< USIC_CH BYPCR: BDSSM (Bit 8) */ -#define USIC_CH_BYPCR_BDSSM_Msk \ - (0x100UL) /*!< USIC_CH BYPCR: BDSSM (Bitfield-Mask: 0x01) */ -#define USIC_CH_BYPCR_BDEN_Pos \ - (10UL) /*!< USIC_CH BYPCR: BDEN (Bit 10) */ -#define USIC_CH_BYPCR_BDEN_Msk \ - (0xc00UL) /*!< USIC_CH BYPCR: BDEN (Bitfield-Mask: 0x03) */ -#define USIC_CH_BYPCR_BDVTR_Pos \ - (12UL) /*!< USIC_CH BYPCR: BDVTR (Bit 12) */ -#define USIC_CH_BYPCR_BDVTR_Msk \ - (0x1000UL) /*!< USIC_CH BYPCR: BDVTR (Bitfield-Mask: 0x01) */ -#define USIC_CH_BYPCR_BPRIO_Pos \ - (13UL) /*!< USIC_CH BYPCR: BPRIO (Bit 13) */ -#define USIC_CH_BYPCR_BPRIO_Msk \ - (0x2000UL) /*!< USIC_CH BYPCR: BPRIO (Bitfield-Mask: 0x01) */ -#define USIC_CH_BYPCR_BDV_Pos \ - (15UL) /*!< USIC_CH BYPCR: BDV (Bit 15) */ -#define USIC_CH_BYPCR_BDV_Msk \ - (0x8000UL) /*!< USIC_CH BYPCR: BDV (Bitfield-Mask: 0x01) */ -#define USIC_CH_BYPCR_BSELO_Pos \ - (16UL) /*!< USIC_CH BYPCR: BSELO (Bit 16) */ -#define USIC_CH_BYPCR_BSELO_Msk \ - (0x1f0000UL) /*!< USIC_CH BYPCR: BSELO (Bitfield-Mask: 0x1f) */ -#define USIC_CH_BYPCR_BHPC_Pos \ - (21UL) /*!< USIC_CH BYPCR: BHPC (Bit 21) */ -#define USIC_CH_BYPCR_BHPC_Msk \ - (0xe00000UL) /*!< USIC_CH BYPCR: BHPC (Bitfield-Mask: 0x07) */ - -/* -------------------------------- USIC_CH_TBCTR ------------------------------- */ -#define USIC_CH_TBCTR_DPTR_Pos \ - (0UL) /*!< USIC_CH TBCTR: DPTR (Bit 0) */ -#define USIC_CH_TBCTR_DPTR_Msk \ - (0x3fUL) /*!< USIC_CH TBCTR: DPTR (Bitfield-Mask: 0x3f) */ -#define USIC_CH_TBCTR_LIMIT_Pos \ - (8UL) /*!< USIC_CH TBCTR: LIMIT (Bit 8) */ -#define USIC_CH_TBCTR_LIMIT_Msk \ - (0x3f00UL) /*!< USIC_CH TBCTR: LIMIT (Bitfield-Mask: 0x3f) */ -#define USIC_CH_TBCTR_STBTM_Pos \ - (14UL) /*!< USIC_CH TBCTR: STBTM (Bit 14) */ -#define USIC_CH_TBCTR_STBTM_Msk \ - (0x4000UL) /*!< USIC_CH TBCTR: STBTM (Bitfield-Mask: 0x01) */ -#define USIC_CH_TBCTR_STBTEN_Pos \ - (15UL) /*!< USIC_CH TBCTR: STBTEN (Bit 15) */ -#define USIC_CH_TBCTR_STBTEN_Msk \ - (0x8000UL) /*!< USIC_CH TBCTR: STBTEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_TBCTR_STBINP_Pos \ - (16UL) /*!< USIC_CH TBCTR: STBINP (Bit 16) */ -#define USIC_CH_TBCTR_STBINP_Msk \ - (0x70000UL) /*!< USIC_CH TBCTR: STBINP (Bitfield-Mask: 0x07) */ -#define USIC_CH_TBCTR_ATBINP_Pos \ - (19UL) /*!< USIC_CH TBCTR: ATBINP (Bit 19) */ -#define USIC_CH_TBCTR_ATBINP_Msk \ - (0x380000UL) /*!< USIC_CH TBCTR: ATBINP (Bitfield-Mask: 0x07) */ -#define USIC_CH_TBCTR_SIZE_Pos \ - (24UL) /*!< USIC_CH TBCTR: SIZE (Bit 24) */ -#define USIC_CH_TBCTR_SIZE_Msk \ - (0x7000000UL) /*!< USIC_CH TBCTR: SIZE (Bitfield-Mask: 0x07) */ -#define USIC_CH_TBCTR_LOF_Pos \ - (28UL) /*!< USIC_CH TBCTR: LOF (Bit 28) */ -#define USIC_CH_TBCTR_LOF_Msk \ - (0x10000000UL) /*!< USIC_CH TBCTR: LOF (Bitfield-Mask: 0x01) */ -#define USIC_CH_TBCTR_STBIEN_Pos \ - (30UL) /*!< USIC_CH TBCTR: STBIEN (Bit 30) */ -#define USIC_CH_TBCTR_STBIEN_Msk \ - (0x40000000UL) /*!< USIC_CH TBCTR: STBIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_TBCTR_TBERIEN_Pos \ - (31UL) /*!< USIC_CH TBCTR: TBERIEN (Bit 31) */ -#define USIC_CH_TBCTR_TBERIEN_Msk \ - (0x80000000UL) /*!< USIC_CH TBCTR: TBERIEN (Bitfield-Mask: 0x01) */ - -/* -------------------------------- USIC_CH_RBCTR ------------------------------- */ -#define USIC_CH_RBCTR_DPTR_Pos \ - (0UL) /*!< USIC_CH RBCTR: DPTR (Bit 0) */ -#define USIC_CH_RBCTR_DPTR_Msk \ - (0x3fUL) /*!< USIC_CH RBCTR: DPTR (Bitfield-Mask: 0x3f) */ -#define USIC_CH_RBCTR_LIMIT_Pos \ - (8UL) /*!< USIC_CH RBCTR: LIMIT (Bit 8) */ -#define USIC_CH_RBCTR_LIMIT_Msk \ - (0x3f00UL) /*!< USIC_CH RBCTR: LIMIT (Bitfield-Mask: 0x3f) */ -#define USIC_CH_RBCTR_SRBTM_Pos \ - (14UL) /*!< USIC_CH RBCTR: SRBTM (Bit 14) */ -#define USIC_CH_RBCTR_SRBTM_Msk \ - (0x4000UL) /*!< USIC_CH RBCTR: SRBTM (Bitfield-Mask: 0x01) */ -#define USIC_CH_RBCTR_SRBTEN_Pos \ - (15UL) /*!< USIC_CH RBCTR: SRBTEN (Bit 15) */ -#define USIC_CH_RBCTR_SRBTEN_Msk \ - (0x8000UL) /*!< USIC_CH RBCTR: SRBTEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_RBCTR_SRBINP_Pos \ - (16UL) /*!< USIC_CH RBCTR: SRBINP (Bit 16) */ -#define USIC_CH_RBCTR_SRBINP_Msk \ - (0x70000UL) /*!< USIC_CH RBCTR: SRBINP (Bitfield-Mask: 0x07) */ -#define USIC_CH_RBCTR_ARBINP_Pos \ - (19UL) /*!< USIC_CH RBCTR: ARBINP (Bit 19) */ -#define USIC_CH_RBCTR_ARBINP_Msk \ - (0x380000UL) /*!< USIC_CH RBCTR: ARBINP (Bitfield-Mask: 0x07) */ -#define USIC_CH_RBCTR_RCIM_Pos \ - (22UL) /*!< USIC_CH RBCTR: RCIM (Bit 22) */ -#define USIC_CH_RBCTR_RCIM_Msk \ - (0xc00000UL) /*!< USIC_CH RBCTR: RCIM (Bitfield-Mask: 0x03) */ -#define USIC_CH_RBCTR_SIZE_Pos \ - (24UL) /*!< USIC_CH RBCTR: SIZE (Bit 24) */ -#define USIC_CH_RBCTR_SIZE_Msk \ - (0x7000000UL) /*!< USIC_CH RBCTR: SIZE (Bitfield-Mask: 0x07) */ -#define USIC_CH_RBCTR_RNM_Pos \ - (27UL) /*!< USIC_CH RBCTR: RNM (Bit 27) */ -#define USIC_CH_RBCTR_RNM_Msk \ - (0x8000000UL) /*!< USIC_CH RBCTR: RNM (Bitfield-Mask: 0x01) */ -#define USIC_CH_RBCTR_LOF_Pos \ - (28UL) /*!< USIC_CH RBCTR: LOF (Bit 28) */ -#define USIC_CH_RBCTR_LOF_Msk \ - (0x10000000UL) /*!< USIC_CH RBCTR: LOF (Bitfield-Mask: 0x01) */ -#define USIC_CH_RBCTR_ARBIEN_Pos \ - (29UL) /*!< USIC_CH RBCTR: ARBIEN (Bit 29) */ -#define USIC_CH_RBCTR_ARBIEN_Msk \ - (0x20000000UL) /*!< USIC_CH RBCTR: ARBIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_RBCTR_SRBIEN_Pos \ - (30UL) /*!< USIC_CH RBCTR: SRBIEN (Bit 30) */ -#define USIC_CH_RBCTR_SRBIEN_Msk \ - (0x40000000UL) /*!< USIC_CH RBCTR: SRBIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_RBCTR_RBERIEN_Pos \ - (31UL) /*!< USIC_CH RBCTR: RBERIEN (Bit 31) */ -#define USIC_CH_RBCTR_RBERIEN_Msk \ - (0x80000000UL) /*!< USIC_CH RBCTR: RBERIEN (Bitfield-Mask: 0x01) */ - -/* ------------------------------- USIC_CH_TRBPTR ------------------------------- */ -#define USIC_CH_TRBPTR_TDIPTR_Pos \ - (0UL) /*!< USIC_CH TRBPTR: TDIPTR (Bit 0) */ -#define USIC_CH_TRBPTR_TDIPTR_Msk \ - (0x3fUL) /*!< USIC_CH TRBPTR: TDIPTR (Bitfield-Mask: 0x3f) */ -#define USIC_CH_TRBPTR_TDOPTR_Pos \ - (8UL) /*!< USIC_CH TRBPTR: TDOPTR (Bit 8) */ -#define USIC_CH_TRBPTR_TDOPTR_Msk \ - (0x3f00UL) /*!< USIC_CH TRBPTR: TDOPTR (Bitfield-Mask: 0x3f) */ -#define USIC_CH_TRBPTR_RDIPTR_Pos \ - (16UL) /*!< USIC_CH TRBPTR: RDIPTR (Bit 16) */ -#define USIC_CH_TRBPTR_RDIPTR_Msk \ - (0x3f0000UL) /*!< USIC_CH TRBPTR: RDIPTR (Bitfield-Mask: 0x3f) */ -#define USIC_CH_TRBPTR_RDOPTR_Pos \ - (24UL) /*!< USIC_CH TRBPTR: RDOPTR (Bit 24) */ -#define USIC_CH_TRBPTR_RDOPTR_Msk \ - (0x3f000000UL) /*!< USIC_CH TRBPTR: RDOPTR (Bitfield-Mask: 0x3f) */ - -/* -------------------------------- USIC_CH_TRBSR ------------------------------- */ -#define USIC_CH_TRBSR_SRBI_Pos \ - (0UL) /*!< USIC_CH TRBSR: SRBI (Bit 0) */ -#define USIC_CH_TRBSR_SRBI_Msk \ - (0x1UL) /*!< USIC_CH TRBSR: SRBI (Bitfield-Mask: 0x01) */ -#define USIC_CH_TRBSR_RBERI_Pos \ - (1UL) /*!< USIC_CH TRBSR: RBERI (Bit 1) */ -#define USIC_CH_TRBSR_RBERI_Msk \ - (0x2UL) /*!< USIC_CH TRBSR: RBERI (Bitfield-Mask: 0x01) */ -#define USIC_CH_TRBSR_ARBI_Pos \ - (2UL) /*!< USIC_CH TRBSR: ARBI (Bit 2) */ -#define USIC_CH_TRBSR_ARBI_Msk \ - (0x4UL) /*!< USIC_CH TRBSR: ARBI (Bitfield-Mask: 0x01) */ -#define USIC_CH_TRBSR_REMPTY_Pos \ - (3UL) /*!< USIC_CH TRBSR: REMPTY (Bit 3) */ -#define USIC_CH_TRBSR_REMPTY_Msk \ - (0x8UL) /*!< USIC_CH TRBSR: REMPTY (Bitfield-Mask: 0x01) */ -#define USIC_CH_TRBSR_RFULL_Pos \ - (4UL) /*!< USIC_CH TRBSR: RFULL (Bit 4) */ -#define USIC_CH_TRBSR_RFULL_Msk \ - (0x10UL) /*!< USIC_CH TRBSR: RFULL (Bitfield-Mask: 0x01) */ -#define USIC_CH_TRBSR_RBUS_Pos \ - (5UL) /*!< USIC_CH TRBSR: RBUS (Bit 5) */ -#define USIC_CH_TRBSR_RBUS_Msk \ - (0x20UL) /*!< USIC_CH TRBSR: RBUS (Bitfield-Mask: 0x01) */ -#define USIC_CH_TRBSR_SRBT_Pos \ - (6UL) /*!< USIC_CH TRBSR: SRBT (Bit 6) */ -#define USIC_CH_TRBSR_SRBT_Msk \ - (0x40UL) /*!< USIC_CH TRBSR: SRBT (Bitfield-Mask: 0x01) */ -#define USIC_CH_TRBSR_STBI_Pos \ - (8UL) /*!< USIC_CH TRBSR: STBI (Bit 8) */ -#define USIC_CH_TRBSR_STBI_Msk \ - (0x100UL) /*!< USIC_CH TRBSR: STBI (Bitfield-Mask: 0x01) */ -#define USIC_CH_TRBSR_TBERI_Pos \ - (9UL) /*!< USIC_CH TRBSR: TBERI (Bit 9) */ -#define USIC_CH_TRBSR_TBERI_Msk \ - (0x200UL) /*!< USIC_CH TRBSR: TBERI (Bitfield-Mask: 0x01) */ -#define USIC_CH_TRBSR_TEMPTY_Pos \ - (11UL) /*!< USIC_CH TRBSR: TEMPTY (Bit 11) */ -#define USIC_CH_TRBSR_TEMPTY_Msk \ - (0x800UL) /*!< USIC_CH TRBSR: TEMPTY (Bitfield-Mask: 0x01) */ -#define USIC_CH_TRBSR_TFULL_Pos \ - (12UL) /*!< USIC_CH TRBSR: TFULL (Bit 12) */ -#define USIC_CH_TRBSR_TFULL_Msk \ - (0x1000UL) /*!< USIC_CH TRBSR: TFULL (Bitfield-Mask: 0x01) */ -#define USIC_CH_TRBSR_TBUS_Pos \ - (13UL) /*!< USIC_CH TRBSR: TBUS (Bit 13) */ -#define USIC_CH_TRBSR_TBUS_Msk \ - (0x2000UL) /*!< USIC_CH TRBSR: TBUS (Bitfield-Mask: 0x01) */ -#define USIC_CH_TRBSR_STBT_Pos \ - (14UL) /*!< USIC_CH TRBSR: STBT (Bit 14) */ -#define USIC_CH_TRBSR_STBT_Msk \ - (0x4000UL) /*!< USIC_CH TRBSR: STBT (Bitfield-Mask: 0x01) */ -#define USIC_CH_TRBSR_RBFLVL_Pos \ - (16UL) /*!< USIC_CH TRBSR: RBFLVL (Bit 16) */ -#define USIC_CH_TRBSR_RBFLVL_Msk \ - (0x7f0000UL) /*!< USIC_CH TRBSR: RBFLVL (Bitfield-Mask: 0x7f) */ -#define USIC_CH_TRBSR_TBFLVL_Pos \ - (24UL) /*!< USIC_CH TRBSR: TBFLVL (Bit 24) */ -#define USIC_CH_TRBSR_TBFLVL_Msk \ - (0x7f000000UL) /*!< USIC_CH TRBSR: TBFLVL (Bitfield-Mask: 0x7f) */ - -/* ------------------------------- USIC_CH_TRBSCR ------------------------------- */ -#define USIC_CH_TRBSCR_CSRBI_Pos \ - (0UL) /*!< USIC_CH TRBSCR: CSRBI (Bit 0) */ -#define USIC_CH_TRBSCR_CSRBI_Msk \ - (0x1UL) /*!< USIC_CH TRBSCR: CSRBI (Bitfield-Mask: 0x01) */ -#define USIC_CH_TRBSCR_CRBERI_Pos \ - (1UL) /*!< USIC_CH TRBSCR: CRBERI (Bit 1) */ -#define USIC_CH_TRBSCR_CRBERI_Msk \ - (0x2UL) /*!< USIC_CH TRBSCR: CRBERI (Bitfield-Mask: 0x01) */ -#define USIC_CH_TRBSCR_CARBI_Pos \ - (2UL) /*!< USIC_CH TRBSCR: CARBI (Bit 2) */ -#define USIC_CH_TRBSCR_CARBI_Msk \ - (0x4UL) /*!< USIC_CH TRBSCR: CARBI (Bitfield-Mask: 0x01) */ -#define USIC_CH_TRBSCR_CSTBI_Pos \ - (8UL) /*!< USIC_CH TRBSCR: CSTBI (Bit 8) */ -#define USIC_CH_TRBSCR_CSTBI_Msk \ - (0x100UL) /*!< USIC_CH TRBSCR: CSTBI (Bitfield-Mask: 0x01) */ -#define USIC_CH_TRBSCR_CTBERI_Pos \ - (9UL) /*!< USIC_CH TRBSCR: CTBERI (Bit 9) */ -#define USIC_CH_TRBSCR_CTBERI_Msk \ - (0x200UL) /*!< USIC_CH TRBSCR: CTBERI (Bitfield-Mask: 0x01) */ -#define USIC_CH_TRBSCR_CBDV_Pos \ - (10UL) /*!< USIC_CH TRBSCR: CBDV (Bit 10) */ -#define USIC_CH_TRBSCR_CBDV_Msk \ - (0x400UL) /*!< USIC_CH TRBSCR: CBDV (Bitfield-Mask: 0x01) */ -#define USIC_CH_TRBSCR_FLUSHRB_Pos \ - (14UL) /*!< USIC_CH TRBSCR: FLUSHRB (Bit 14) */ -#define USIC_CH_TRBSCR_FLUSHRB_Msk \ - (0x4000UL) /*!< USIC_CH TRBSCR: FLUSHRB (Bitfield-Mask: 0x01) */ -#define USIC_CH_TRBSCR_FLUSHTB_Pos \ - (15UL) /*!< USIC_CH TRBSCR: FLUSHTB (Bit 15) */ -#define USIC_CH_TRBSCR_FLUSHTB_Msk \ - (0x8000UL) /*!< USIC_CH TRBSCR: FLUSHTB (Bitfield-Mask: 0x01) */ - -/* -------------------------------- USIC_CH_OUTR -------------------------------- */ -#define USIC_CH_OUTR_DSR_Pos \ - (0UL) /*!< USIC_CH OUTR: DSR (Bit 0) */ -#define USIC_CH_OUTR_DSR_Msk \ - (0xffffUL) /*!< USIC_CH OUTR: DSR (Bitfield-Mask: 0xffff) */ -#define USIC_CH_OUTR_RCI_Pos \ - (16UL) /*!< USIC_CH OUTR: RCI (Bit 16) */ -#define USIC_CH_OUTR_RCI_Msk \ - (0x1f0000UL) /*!< USIC_CH OUTR: RCI (Bitfield-Mask: 0x1f) */ - -/* -------------------------------- USIC_CH_OUTDR ------------------------------- */ -#define USIC_CH_OUTDR_DSR_Pos \ - (0UL) /*!< USIC_CH OUTDR: DSR (Bit 0) */ -#define USIC_CH_OUTDR_DSR_Msk \ - (0xffffUL) /*!< USIC_CH OUTDR: DSR (Bitfield-Mask: 0xffff) */ -#define USIC_CH_OUTDR_RCI_Pos \ - (16UL) /*!< USIC_CH OUTDR: RCI (Bit 16) */ -#define USIC_CH_OUTDR_RCI_Msk \ - (0x1f0000UL) /*!< USIC_CH OUTDR: RCI (Bitfield-Mask: 0x1f) */ - -/* --------------------------------- USIC_CH_IN --------------------------------- */ -#define USIC_CH_IN_TDATA_Pos \ - (0UL) /*!< USIC_CH IN: TDATA (Bit 0) */ -#define USIC_CH_IN_TDATA_Msk \ - (0xffffUL) /*!< USIC_CH IN: TDATA (Bitfield-Mask: 0xffff) */ - -/* ================================================================================ */ -/* ================ struct 'CAN' Position & Mask ================ */ -/* ================================================================================ */ - -/* ----------------------------------- CAN_CLC ---------------------------------- */ -#define CAN_CLC_DISR_Pos (0UL) /*!< CAN CLC: DISR (Bit 0) */ -#define CAN_CLC_DISR_Msk (0x1UL) /*!< CAN CLC: DISR (Bitfield-Mask: 0x01) */ -#define CAN_CLC_DISS_Pos (1UL) /*!< CAN CLC: DISS (Bit 1) */ -#define CAN_CLC_DISS_Msk (0x2UL) /*!< CAN CLC: DISS (Bitfield-Mask: 0x01) */ -#define CAN_CLC_EDIS_Pos (3UL) /*!< CAN CLC: EDIS (Bit 3) */ -#define CAN_CLC_EDIS_Msk (0x8UL) /*!< CAN CLC: EDIS (Bitfield-Mask: 0x01) */ -#define CAN_CLC_SBWE_Pos (4UL) /*!< CAN CLC: SBWE (Bit 4) */ -#define CAN_CLC_SBWE_Msk \ - (0x10UL) /*!< CAN CLC: SBWE (Bitfield-Mask: 0x01) */ - -/* ----------------------------------- CAN_ID ----------------------------------- */ -#define CAN_ID_MOD_REV_Pos (0UL) /*!< CAN ID: MOD_REV (Bit 0) */ -#define CAN_ID_MOD_REV_Msk \ - (0xffUL) /*!< CAN ID: MOD_REV (Bitfield-Mask: 0xff) */ -#define CAN_ID_MOD_TYPE_Pos \ - (8UL) /*!< CAN ID: MOD_TYPE (Bit 8) */ -#define CAN_ID_MOD_TYPE_Msk \ - (0xff00UL) /*!< CAN ID: MOD_TYPE (Bitfield-Mask: 0xff) */ -#define CAN_ID_MOD_NUMBER_Pos \ - (16UL) /*!< CAN ID: MOD_NUMBER (Bit 16) */ -#define CAN_ID_MOD_NUMBER_Msk \ - (0xffff0000UL) /*!< CAN ID: MOD_NUMBER (Bitfield-Mask: 0xffff) */ - -/* ----------------------------------- CAN_FDR ---------------------------------- */ -#define CAN_FDR_STEP_Pos (0UL) /*!< CAN FDR: STEP (Bit 0) */ -#define CAN_FDR_STEP_Msk \ - (0x3ffUL) /*!< CAN FDR: STEP (Bitfield-Mask: 0x3ff) */ -#define CAN_FDR_SM_Pos (11UL) /*!< CAN FDR: SM (Bit 11) */ -#define CAN_FDR_SM_Msk (0x800UL) /*!< CAN FDR: SM (Bitfield-Mask: 0x01) */ -#define CAN_FDR_SC_Pos (12UL) /*!< CAN FDR: SC (Bit 12) */ -#define CAN_FDR_SC_Msk \ - (0x3000UL) /*!< CAN FDR: SC (Bitfield-Mask: 0x03) */ -#define CAN_FDR_DM_Pos (14UL) /*!< CAN FDR: DM (Bit 14) */ -#define CAN_FDR_DM_Msk \ - (0xc000UL) /*!< CAN FDR: DM (Bitfield-Mask: 0x03) */ -#define CAN_FDR_RESULT_Pos \ - (16UL) /*!< CAN FDR: RESULT (Bit 16) */ -#define CAN_FDR_RESULT_Msk \ - (0x3ff0000UL) /*!< CAN FDR: RESULT (Bitfield-Mask: 0x3ff) */ -#define CAN_FDR_SUSACK_Pos \ - (28UL) /*!< CAN FDR: SUSACK (Bit 28) */ -#define CAN_FDR_SUSACK_Msk \ - (0x10000000UL) /*!< CAN FDR: SUSACK (Bitfield-Mask: 0x01) */ -#define CAN_FDR_SUSREQ_Pos \ - (29UL) /*!< CAN FDR: SUSREQ (Bit 29) */ -#define CAN_FDR_SUSREQ_Msk \ - (0x20000000UL) /*!< CAN FDR: SUSREQ (Bitfield-Mask: 0x01) */ -#define CAN_FDR_ENHW_Pos (30UL) /*!< CAN FDR: ENHW (Bit 30) */ -#define CAN_FDR_ENHW_Msk \ - (0x40000000UL) /*!< CAN FDR: ENHW (Bitfield-Mask: 0x01) */ -#define CAN_FDR_DISCLK_Pos \ - (31UL) /*!< CAN FDR: DISCLK (Bit 31) */ -#define CAN_FDR_DISCLK_Msk \ - (0x80000000UL) /*!< CAN FDR: DISCLK (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- CAN_LIST ---------------------------------- */ -#define CAN_LIST_BEGIN_Pos (0UL) /*!< CAN LIST: BEGIN (Bit 0) */ -#define CAN_LIST_BEGIN_Msk \ - (0xffUL) /*!< CAN LIST: BEGIN (Bitfield-Mask: 0xff) */ -#define CAN_LIST_END_Pos (8UL) /*!< CAN LIST: END (Bit 8) */ -#define CAN_LIST_END_Msk \ - (0xff00UL) /*!< CAN LIST: END (Bitfield-Mask: 0xff) */ -#define CAN_LIST_SIZE_Pos (16UL) /*!< CAN LIST: SIZE (Bit 16) */ -#define CAN_LIST_SIZE_Msk \ - (0xff0000UL) /*!< CAN LIST: SIZE (Bitfield-Mask: 0xff) */ -#define CAN_LIST_EMPTY_Pos \ - (24UL) /*!< CAN LIST: EMPTY (Bit 24) */ -#define CAN_LIST_EMPTY_Msk \ - (0x1000000UL) /*!< CAN LIST: EMPTY (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- CAN_MSPND --------------------------------- */ -#define CAN_MSPND_PND_Pos (0UL) /*!< CAN MSPND: PND (Bit 0) */ -#define CAN_MSPND_PND_Msk \ - (0xffffffffUL) /*!< CAN MSPND: PND (Bitfield-Mask: 0xffffffff) */ - -/* ---------------------------------- CAN_MSID ---------------------------------- */ -#define CAN_MSID_INDEX_Pos (0UL) /*!< CAN MSID: INDEX (Bit 0) */ -#define CAN_MSID_INDEX_Msk \ - (0x3fUL) /*!< CAN MSID: INDEX (Bitfield-Mask: 0x3f) */ - -/* --------------------------------- CAN_MSIMASK -------------------------------- */ -#define CAN_MSIMASK_IM_Pos (0UL) /*!< CAN MSIMASK: IM (Bit 0) */ -#define CAN_MSIMASK_IM_Msk \ - (0xffffffffUL) /*!< CAN MSIMASK: IM (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------------- CAN_PANCTR --------------------------------- */ -#define CAN_PANCTR_PANCMD_Pos \ - (0UL) /*!< CAN PANCTR: PANCMD (Bit 0) */ -#define CAN_PANCTR_PANCMD_Msk \ - (0xffUL) /*!< CAN PANCTR: PANCMD (Bitfield-Mask: 0xff) */ -#define CAN_PANCTR_BUSY_Pos \ - (8UL) /*!< CAN PANCTR: BUSY (Bit 8) */ -#define CAN_PANCTR_BUSY_Msk \ - (0x100UL) /*!< CAN PANCTR: BUSY (Bitfield-Mask: 0x01) */ -#define CAN_PANCTR_RBUSY_Pos \ - (9UL) /*!< CAN PANCTR: RBUSY (Bit 9) */ -#define CAN_PANCTR_RBUSY_Msk \ - (0x200UL) /*!< CAN PANCTR: RBUSY (Bitfield-Mask: 0x01) */ -#define CAN_PANCTR_PANAR1_Pos \ - (16UL) /*!< CAN PANCTR: PANAR1 (Bit 16) */ -#define CAN_PANCTR_PANAR1_Msk \ - (0xff0000UL) /*!< CAN PANCTR: PANAR1 (Bitfield-Mask: 0xff) */ -#define CAN_PANCTR_PANAR2_Pos \ - (24UL) /*!< CAN PANCTR: PANAR2 (Bit 24) */ -#define CAN_PANCTR_PANAR2_Msk \ - (0xff000000UL) /*!< CAN PANCTR: PANAR2 (Bitfield-Mask: 0xff) */ - -/* ----------------------------------- CAN_MCR ---------------------------------- */ -#define CAN_MCR_MPSEL_Pos (12UL) /*!< CAN MCR: MPSEL (Bit 12) */ -#define CAN_MCR_MPSEL_Msk \ - (0xf000UL) /*!< CAN MCR: MPSEL (Bitfield-Mask: 0x0f) */ - -/* ---------------------------------- CAN_MITR ---------------------------------- */ -#define CAN_MITR_IT_Pos (0UL) /*!< CAN MITR: IT (Bit 0) */ -#define CAN_MITR_IT_Msk (0xffUL) /*!< CAN MITR: IT (Bitfield-Mask: 0xff) */ - -/* ================================================================================ */ -/* ================ Group 'CAN_NODE' Position & Mask ================ */ -/* ================================================================================ */ - -/* -------------------------------- CAN_NODE_NCR -------------------------------- */ -#define CAN_NODE_NCR_INIT_Pos \ - (0UL) /*!< CAN_NODE NCR: INIT (Bit 0) */ -#define CAN_NODE_NCR_INIT_Msk \ - (0x1UL) /*!< CAN_NODE NCR: INIT (Bitfield-Mask: 0x01) */ -#define CAN_NODE_NCR_TRIE_Pos \ - (1UL) /*!< CAN_NODE NCR: TRIE (Bit 1) */ -#define CAN_NODE_NCR_TRIE_Msk \ - (0x2UL) /*!< CAN_NODE NCR: TRIE (Bitfield-Mask: 0x01) */ -#define CAN_NODE_NCR_LECIE_Pos \ - (2UL) /*!< CAN_NODE NCR: LECIE (Bit 2) */ -#define CAN_NODE_NCR_LECIE_Msk \ - (0x4UL) /*!< CAN_NODE NCR: LECIE (Bitfield-Mask: 0x01) */ -#define CAN_NODE_NCR_ALIE_Pos \ - (3UL) /*!< CAN_NODE NCR: ALIE (Bit 3) */ -#define CAN_NODE_NCR_ALIE_Msk \ - (0x8UL) /*!< CAN_NODE NCR: ALIE (Bitfield-Mask: 0x01) */ -#define CAN_NODE_NCR_CANDIS_Pos \ - (4UL) /*!< CAN_NODE NCR: CANDIS (Bit 4) */ -#define CAN_NODE_NCR_CANDIS_Msk \ - (0x10UL) /*!< CAN_NODE NCR: CANDIS (Bitfield-Mask: 0x01) */ -#define CAN_NODE_NCR_CCE_Pos \ - (6UL) /*!< CAN_NODE NCR: CCE (Bit 6) */ -#define CAN_NODE_NCR_CCE_Msk \ - (0x40UL) /*!< CAN_NODE NCR: CCE (Bitfield-Mask: 0x01) */ -#define CAN_NODE_NCR_CALM_Pos \ - (7UL) /*!< CAN_NODE NCR: CALM (Bit 7) */ -#define CAN_NODE_NCR_CALM_Msk \ - (0x80UL) /*!< CAN_NODE NCR: CALM (Bitfield-Mask: 0x01) */ -#define CAN_NODE_NCR_SUSEN_Pos \ - (8UL) /*!< CAN_NODE NCR: SUSEN (Bit 8) */ -#define CAN_NODE_NCR_SUSEN_Msk \ - (0x100UL) /*!< CAN_NODE NCR: SUSEN (Bitfield-Mask: 0x01) */ - -/* -------------------------------- CAN_NODE_NSR -------------------------------- */ -#define CAN_NODE_NSR_LEC_Pos \ - (0UL) /*!< CAN_NODE NSR: LEC (Bit 0) */ -#define CAN_NODE_NSR_LEC_Msk \ - (0x7UL) /*!< CAN_NODE NSR: LEC (Bitfield-Mask: 0x07) */ -#define CAN_NODE_NSR_TXOK_Pos \ - (3UL) /*!< CAN_NODE NSR: TXOK (Bit 3) */ -#define CAN_NODE_NSR_TXOK_Msk \ - (0x8UL) /*!< CAN_NODE NSR: TXOK (Bitfield-Mask: 0x01) */ -#define CAN_NODE_NSR_RXOK_Pos \ - (4UL) /*!< CAN_NODE NSR: RXOK (Bit 4) */ -#define CAN_NODE_NSR_RXOK_Msk \ - (0x10UL) /*!< CAN_NODE NSR: RXOK (Bitfield-Mask: 0x01) */ -#define CAN_NODE_NSR_ALERT_Pos \ - (5UL) /*!< CAN_NODE NSR: ALERT (Bit 5) */ -#define CAN_NODE_NSR_ALERT_Msk \ - (0x20UL) /*!< CAN_NODE NSR: ALERT (Bitfield-Mask: 0x01) */ -#define CAN_NODE_NSR_EWRN_Pos \ - (6UL) /*!< CAN_NODE NSR: EWRN (Bit 6) */ -#define CAN_NODE_NSR_EWRN_Msk \ - (0x40UL) /*!< CAN_NODE NSR: EWRN (Bitfield-Mask: 0x01) */ -#define CAN_NODE_NSR_BOFF_Pos \ - (7UL) /*!< CAN_NODE NSR: BOFF (Bit 7) */ -#define CAN_NODE_NSR_BOFF_Msk \ - (0x80UL) /*!< CAN_NODE NSR: BOFF (Bitfield-Mask: 0x01) */ -#define CAN_NODE_NSR_LLE_Pos \ - (8UL) /*!< CAN_NODE NSR: LLE (Bit 8) */ -#define CAN_NODE_NSR_LLE_Msk \ - (0x100UL) /*!< CAN_NODE NSR: LLE (Bitfield-Mask: 0x01) */ -#define CAN_NODE_NSR_LOE_Pos \ - (9UL) /*!< CAN_NODE NSR: LOE (Bit 9) */ -#define CAN_NODE_NSR_LOE_Msk \ - (0x200UL) /*!< CAN_NODE NSR: LOE (Bitfield-Mask: 0x01) */ -#define CAN_NODE_NSR_SUSACK_Pos \ - (10UL) /*!< CAN_NODE NSR: SUSACK (Bit 10) */ -#define CAN_NODE_NSR_SUSACK_Msk \ - (0x400UL) /*!< CAN_NODE NSR: SUSACK (Bitfield-Mask: 0x01) */ - -/* -------------------------------- CAN_NODE_NIPR ------------------------------- */ -#define CAN_NODE_NIPR_ALINP_Pos \ - (0UL) /*!< CAN_NODE NIPR: ALINP (Bit 0) */ -#define CAN_NODE_NIPR_ALINP_Msk \ - (0x7UL) /*!< CAN_NODE NIPR: ALINP (Bitfield-Mask: 0x07) */ -#define CAN_NODE_NIPR_LECINP_Pos \ - (4UL) /*!< CAN_NODE NIPR: LECINP (Bit 4) */ -#define CAN_NODE_NIPR_LECINP_Msk \ - (0x70UL) /*!< CAN_NODE NIPR: LECINP (Bitfield-Mask: 0x07) */ -#define CAN_NODE_NIPR_TRINP_Pos \ - (8UL) /*!< CAN_NODE NIPR: TRINP (Bit 8) */ -#define CAN_NODE_NIPR_TRINP_Msk \ - (0x700UL) /*!< CAN_NODE NIPR: TRINP (Bitfield-Mask: 0x07) */ -#define CAN_NODE_NIPR_CFCINP_Pos \ - (12UL) /*!< CAN_NODE NIPR: CFCINP (Bit 12) */ -#define CAN_NODE_NIPR_CFCINP_Msk \ - (0x7000UL) /*!< CAN_NODE NIPR: CFCINP (Bitfield-Mask: 0x07) */ - -/* -------------------------------- CAN_NODE_NPCR ------------------------------- */ -#define CAN_NODE_NPCR_RXSEL_Pos \ - (0UL) /*!< CAN_NODE NPCR: RXSEL (Bit 0) */ -#define CAN_NODE_NPCR_RXSEL_Msk \ - (0x7UL) /*!< CAN_NODE NPCR: RXSEL (Bitfield-Mask: 0x07) */ -#define CAN_NODE_NPCR_LBM_Pos \ - (8UL) /*!< CAN_NODE NPCR: LBM (Bit 8) */ -#define CAN_NODE_NPCR_LBM_Msk \ - (0x100UL) /*!< CAN_NODE NPCR: LBM (Bitfield-Mask: 0x01) */ - -/* -------------------------------- CAN_NODE_NBTR ------------------------------- */ -#define CAN_NODE_NBTR_BRP_Pos \ - (0UL) /*!< CAN_NODE NBTR: BRP (Bit 0) */ -#define CAN_NODE_NBTR_BRP_Msk \ - (0x3fUL) /*!< CAN_NODE NBTR: BRP (Bitfield-Mask: 0x3f) */ -#define CAN_NODE_NBTR_SJW_Pos \ - (6UL) /*!< CAN_NODE NBTR: SJW (Bit 6) */ -#define CAN_NODE_NBTR_SJW_Msk \ - (0xc0UL) /*!< CAN_NODE NBTR: SJW (Bitfield-Mask: 0x03) */ -#define CAN_NODE_NBTR_TSEG1_Pos \ - (8UL) /*!< CAN_NODE NBTR: TSEG1 (Bit 8) */ -#define CAN_NODE_NBTR_TSEG1_Msk \ - (0xf00UL) /*!< CAN_NODE NBTR: TSEG1 (Bitfield-Mask: 0x0f) */ -#define CAN_NODE_NBTR_TSEG2_Pos \ - (12UL) /*!< CAN_NODE NBTR: TSEG2 (Bit 12) */ -#define CAN_NODE_NBTR_TSEG2_Msk \ - (0x7000UL) /*!< CAN_NODE NBTR: TSEG2 (Bitfield-Mask: 0x07) */ -#define CAN_NODE_NBTR_DIV8_Pos \ - (15UL) /*!< CAN_NODE NBTR: DIV8 (Bit 15) */ -#define CAN_NODE_NBTR_DIV8_Msk \ - (0x8000UL) /*!< CAN_NODE NBTR: DIV8 (Bitfield-Mask: 0x01) */ - -/* ------------------------------- CAN_NODE_NECNT ------------------------------- */ -#define CAN_NODE_NECNT_REC_Pos \ - (0UL) /*!< CAN_NODE NECNT: REC (Bit 0) */ -#define CAN_NODE_NECNT_REC_Msk \ - (0xffUL) /*!< CAN_NODE NECNT: REC (Bitfield-Mask: 0xff) */ -#define CAN_NODE_NECNT_TEC_Pos \ - (8UL) /*!< CAN_NODE NECNT: TEC (Bit 8) */ -#define CAN_NODE_NECNT_TEC_Msk \ - (0xff00UL) /*!< CAN_NODE NECNT: TEC (Bitfield-Mask: 0xff) */ -#define CAN_NODE_NECNT_EWRNLVL_Pos \ - (16UL) /*!< CAN_NODE NECNT: EWRNLVL (Bit 16) */ -#define CAN_NODE_NECNT_EWRNLVL_Msk \ - (0xff0000UL) /*!< CAN_NODE NECNT: EWRNLVL (Bitfield-Mask: 0xff) */ -#define CAN_NODE_NECNT_LETD_Pos \ - (24UL) /*!< CAN_NODE NECNT: LETD (Bit 24) */ -#define CAN_NODE_NECNT_LETD_Msk \ - (0x1000000UL) /*!< CAN_NODE NECNT: LETD (Bitfield-Mask: 0x01) */ -#define CAN_NODE_NECNT_LEINC_Pos \ - (25UL) /*!< CAN_NODE NECNT: LEINC (Bit 25) */ -#define CAN_NODE_NECNT_LEINC_Msk \ - (0x2000000UL) /*!< CAN_NODE NECNT: LEINC (Bitfield-Mask: 0x01) */ - -/* -------------------------------- CAN_NODE_NFCR ------------------------------- */ -#define CAN_NODE_NFCR_CFC_Pos \ - (0UL) /*!< CAN_NODE NFCR: CFC (Bit 0) */ -#define CAN_NODE_NFCR_CFC_Msk \ - (0xffffUL) /*!< CAN_NODE NFCR: CFC (Bitfield-Mask: 0xffff) */ -#define CAN_NODE_NFCR_CFSEL_Pos \ - (16UL) /*!< CAN_NODE NFCR: CFSEL (Bit 16) */ -#define CAN_NODE_NFCR_CFSEL_Msk \ - (0x70000UL) /*!< CAN_NODE NFCR: CFSEL (Bitfield-Mask: 0x07) */ -#define CAN_NODE_NFCR_CFMOD_Pos \ - (19UL) /*!< CAN_NODE NFCR: CFMOD (Bit 19) */ -#define CAN_NODE_NFCR_CFMOD_Msk \ - (0x180000UL) /*!< CAN_NODE NFCR: CFMOD (Bitfield-Mask: 0x03) */ -#define CAN_NODE_NFCR_CFCIE_Pos \ - (22UL) /*!< CAN_NODE NFCR: CFCIE (Bit 22) */ -#define CAN_NODE_NFCR_CFCIE_Msk \ - (0x400000UL) /*!< CAN_NODE NFCR: CFCIE (Bitfield-Mask: 0x01) */ -#define CAN_NODE_NFCR_CFCOV_Pos \ - (23UL) /*!< CAN_NODE NFCR: CFCOV (Bit 23) */ -#define CAN_NODE_NFCR_CFCOV_Msk \ - (0x800000UL) /*!< CAN_NODE NFCR: CFCOV (Bitfield-Mask: 0x01) */ - -/* ================================================================================ */ -/* ================ Group 'CAN_MO' Position & Mask ================ */ -/* ================================================================================ */ - -/* -------------------------------- CAN_MO_MOFCR -------------------------------- */ -#define CAN_MO_MOFCR_MMC_Pos \ - (0UL) /*!< CAN_MO MOFCR: MMC (Bit 0) */ -#define CAN_MO_MOFCR_MMC_Msk \ - (0xfUL) /*!< CAN_MO MOFCR: MMC (Bitfield-Mask: 0x0f) */ -#define CAN_MO_MOFCR_GDFS_Pos \ - (8UL) /*!< CAN_MO MOFCR: GDFS (Bit 8) */ -#define CAN_MO_MOFCR_GDFS_Msk \ - (0x100UL) /*!< CAN_MO MOFCR: GDFS (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOFCR_IDC_Pos \ - (9UL) /*!< CAN_MO MOFCR: IDC (Bit 9) */ -#define CAN_MO_MOFCR_IDC_Msk \ - (0x200UL) /*!< CAN_MO MOFCR: IDC (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOFCR_DLCC_Pos \ - (10UL) /*!< CAN_MO MOFCR: DLCC (Bit 10) */ -#define CAN_MO_MOFCR_DLCC_Msk \ - (0x400UL) /*!< CAN_MO MOFCR: DLCC (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOFCR_DATC_Pos \ - (11UL) /*!< CAN_MO MOFCR: DATC (Bit 11) */ -#define CAN_MO_MOFCR_DATC_Msk \ - (0x800UL) /*!< CAN_MO MOFCR: DATC (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOFCR_RXIE_Pos \ - (16UL) /*!< CAN_MO MOFCR: RXIE (Bit 16) */ -#define CAN_MO_MOFCR_RXIE_Msk \ - (0x10000UL) /*!< CAN_MO MOFCR: RXIE (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOFCR_TXIE_Pos \ - (17UL) /*!< CAN_MO MOFCR: TXIE (Bit 17) */ -#define CAN_MO_MOFCR_TXIE_Msk \ - (0x20000UL) /*!< CAN_MO MOFCR: TXIE (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOFCR_OVIE_Pos \ - (18UL) /*!< CAN_MO MOFCR: OVIE (Bit 18) */ -#define CAN_MO_MOFCR_OVIE_Msk \ - (0x40000UL) /*!< CAN_MO MOFCR: OVIE (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOFCR_FRREN_Pos \ - (20UL) /*!< CAN_MO MOFCR: FRREN (Bit 20) */ -#define CAN_MO_MOFCR_FRREN_Msk \ - (0x100000UL) /*!< CAN_MO MOFCR: FRREN (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOFCR_RMM_Pos \ - (21UL) /*!< CAN_MO MOFCR: RMM (Bit 21) */ -#define CAN_MO_MOFCR_RMM_Msk \ - (0x200000UL) /*!< CAN_MO MOFCR: RMM (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOFCR_SDT_Pos \ - (22UL) /*!< CAN_MO MOFCR: SDT (Bit 22) */ -#define CAN_MO_MOFCR_SDT_Msk \ - (0x400000UL) /*!< CAN_MO MOFCR: SDT (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOFCR_STT_Pos \ - (23UL) /*!< CAN_MO MOFCR: STT (Bit 23) */ -#define CAN_MO_MOFCR_STT_Msk \ - (0x800000UL) /*!< CAN_MO MOFCR: STT (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOFCR_DLC_Pos \ - (24UL) /*!< CAN_MO MOFCR: DLC (Bit 24) */ -#define CAN_MO_MOFCR_DLC_Msk \ - (0xf000000UL) /*!< CAN_MO MOFCR: DLC (Bitfield-Mask: 0x0f) */ - -/* -------------------------------- CAN_MO_MOFGPR ------------------------------- */ -#define CAN_MO_MOFGPR_BOT_Pos \ - (0UL) /*!< CAN_MO MOFGPR: BOT (Bit 0) */ -#define CAN_MO_MOFGPR_BOT_Msk \ - (0xffUL) /*!< CAN_MO MOFGPR: BOT (Bitfield-Mask: 0xff) */ -#define CAN_MO_MOFGPR_TOP_Pos \ - (8UL) /*!< CAN_MO MOFGPR: TOP (Bit 8) */ -#define CAN_MO_MOFGPR_TOP_Msk \ - (0xff00UL) /*!< CAN_MO MOFGPR: TOP (Bitfield-Mask: 0xff) */ -#define CAN_MO_MOFGPR_CUR_Pos \ - (16UL) /*!< CAN_MO MOFGPR: CUR (Bit 16) */ -#define CAN_MO_MOFGPR_CUR_Msk \ - (0xff0000UL) /*!< CAN_MO MOFGPR: CUR (Bitfield-Mask: 0xff) */ -#define CAN_MO_MOFGPR_SEL_Pos \ - (24UL) /*!< CAN_MO MOFGPR: SEL (Bit 24) */ -#define CAN_MO_MOFGPR_SEL_Msk \ - (0xff000000UL) /*!< CAN_MO MOFGPR: SEL (Bitfield-Mask: 0xff) */ - -/* -------------------------------- CAN_MO_MOIPR -------------------------------- */ -#define CAN_MO_MOIPR_RXINP_Pos \ - (0UL) /*!< CAN_MO MOIPR: RXINP (Bit 0) */ -#define CAN_MO_MOIPR_RXINP_Msk \ - (0x7UL) /*!< CAN_MO MOIPR: RXINP (Bitfield-Mask: 0x07) */ -#define CAN_MO_MOIPR_TXINP_Pos \ - (4UL) /*!< CAN_MO MOIPR: TXINP (Bit 4) */ -#define CAN_MO_MOIPR_TXINP_Msk \ - (0x70UL) /*!< CAN_MO MOIPR: TXINP (Bitfield-Mask: 0x07) */ -#define CAN_MO_MOIPR_MPN_Pos \ - (8UL) /*!< CAN_MO MOIPR: MPN (Bit 8) */ -#define CAN_MO_MOIPR_MPN_Msk \ - (0xff00UL) /*!< CAN_MO MOIPR: MPN (Bitfield-Mask: 0xff) */ -#define CAN_MO_MOIPR_CFCVAL_Pos \ - (16UL) /*!< CAN_MO MOIPR: CFCVAL (Bit 16) */ -#define CAN_MO_MOIPR_CFCVAL_Msk \ - (0xffff0000UL) /*!< CAN_MO MOIPR: CFCVAL (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- CAN_MO_MOAMR -------------------------------- */ -#define CAN_MO_MOAMR_AM_Pos \ - (0UL) /*!< CAN_MO MOAMR: AM (Bit 0) */ -#define CAN_MO_MOAMR_AM_Msk \ - (0x1fffffffUL) /*!< CAN_MO MOAMR: AM (Bitfield-Mask: 0x1fffffff) */ -#define CAN_MO_MOAMR_MIDE_Pos \ - (29UL) /*!< CAN_MO MOAMR: MIDE (Bit 29) */ -#define CAN_MO_MOAMR_MIDE_Msk \ - (0x20000000UL) /*!< CAN_MO MOAMR: MIDE (Bitfield-Mask: 0x01) */ - -/* ------------------------------- CAN_MO_MODATAL ------------------------------- */ -#define CAN_MO_MODATAL_DB0_Pos \ - (0UL) /*!< CAN_MO MODATAL: DB0 (Bit 0) */ -#define CAN_MO_MODATAL_DB0_Msk \ - (0xffUL) /*!< CAN_MO MODATAL: DB0 (Bitfield-Mask: 0xff) */ -#define CAN_MO_MODATAL_DB1_Pos \ - (8UL) /*!< CAN_MO MODATAL: DB1 (Bit 8) */ -#define CAN_MO_MODATAL_DB1_Msk \ - (0xff00UL) /*!< CAN_MO MODATAL: DB1 (Bitfield-Mask: 0xff) */ -#define CAN_MO_MODATAL_DB2_Pos \ - (16UL) /*!< CAN_MO MODATAL: DB2 (Bit 16) */ -#define CAN_MO_MODATAL_DB2_Msk \ - (0xff0000UL) /*!< CAN_MO MODATAL: DB2 (Bitfield-Mask: 0xff) */ -#define CAN_MO_MODATAL_DB3_Pos \ - (24UL) /*!< CAN_MO MODATAL: DB3 (Bit 24) */ -#define CAN_MO_MODATAL_DB3_Msk \ - (0xff000000UL) /*!< CAN_MO MODATAL: DB3 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- CAN_MO_MODATAH ------------------------------- */ -#define CAN_MO_MODATAH_DB4_Pos \ - (0UL) /*!< CAN_MO MODATAH: DB4 (Bit 0) */ -#define CAN_MO_MODATAH_DB4_Msk \ - (0xffUL) /*!< CAN_MO MODATAH: DB4 (Bitfield-Mask: 0xff) */ -#define CAN_MO_MODATAH_DB5_Pos \ - (8UL) /*!< CAN_MO MODATAH: DB5 (Bit 8) */ -#define CAN_MO_MODATAH_DB5_Msk \ - (0xff00UL) /*!< CAN_MO MODATAH: DB5 (Bitfield-Mask: 0xff) */ -#define CAN_MO_MODATAH_DB6_Pos \ - (16UL) /*!< CAN_MO MODATAH: DB6 (Bit 16) */ -#define CAN_MO_MODATAH_DB6_Msk \ - (0xff0000UL) /*!< CAN_MO MODATAH: DB6 (Bitfield-Mask: 0xff) */ -#define CAN_MO_MODATAH_DB7_Pos \ - (24UL) /*!< CAN_MO MODATAH: DB7 (Bit 24) */ -#define CAN_MO_MODATAH_DB7_Msk \ - (0xff000000UL) /*!< CAN_MO MODATAH: DB7 (Bitfield-Mask: 0xff) */ - -/* --------------------------------- CAN_MO_MOAR -------------------------------- */ -#define CAN_MO_MOAR_ID_Pos (0UL) /*!< CAN_MO MOAR: ID (Bit 0) */ -#define CAN_MO_MOAR_ID_Msk \ - (0x1fffffffUL) /*!< CAN_MO MOAR: ID (Bitfield-Mask: 0x1fffffff) */ -#define CAN_MO_MOAR_IDE_Pos \ - (29UL) /*!< CAN_MO MOAR: IDE (Bit 29) */ -#define CAN_MO_MOAR_IDE_Msk \ - (0x20000000UL) /*!< CAN_MO MOAR: IDE (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOAR_PRI_Pos \ - (30UL) /*!< CAN_MO MOAR: PRI (Bit 30) */ -#define CAN_MO_MOAR_PRI_Msk \ - (0xc0000000UL) /*!< CAN_MO MOAR: PRI (Bitfield-Mask: 0x03) */ - -/* -------------------------------- CAN_MO_MOCTR -------------------------------- */ -#define CAN_MO_MOCTR_RESRXPND_Pos \ - (0UL) /*!< CAN_MO MOCTR: RESRXPND (Bit 0) */ -#define CAN_MO_MOCTR_RESRXPND_Msk \ - (0x1UL) /*!< CAN_MO MOCTR: RESRXPND (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOCTR_RESTXPND_Pos \ - (1UL) /*!< CAN_MO MOCTR: RESTXPND (Bit 1) */ -#define CAN_MO_MOCTR_RESTXPND_Msk \ - (0x2UL) /*!< CAN_MO MOCTR: RESTXPND (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOCTR_RESRXUPD_Pos \ - (2UL) /*!< CAN_MO MOCTR: RESRXUPD (Bit 2) */ -#define CAN_MO_MOCTR_RESRXUPD_Msk \ - (0x4UL) /*!< CAN_MO MOCTR: RESRXUPD (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOCTR_RESNEWDAT_Pos \ - (3UL) /*!< CAN_MO MOCTR: RESNEWDAT (Bit 3) */ -#define CAN_MO_MOCTR_RESNEWDAT_Msk \ - (0x8UL) /*!< CAN_MO MOCTR: RESNEWDAT (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOCTR_RESMSGLST_Pos \ - (4UL) /*!< CAN_MO MOCTR: RESMSGLST (Bit 4) */ -#define CAN_MO_MOCTR_RESMSGLST_Msk \ - (0x10UL) /*!< CAN_MO MOCTR: RESMSGLST (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOCTR_RESMSGVAL_Pos \ - (5UL) /*!< CAN_MO MOCTR: RESMSGVAL (Bit 5) */ -#define CAN_MO_MOCTR_RESMSGVAL_Msk \ - (0x20UL) /*!< CAN_MO MOCTR: RESMSGVAL (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOCTR_RESRTSEL_Pos \ - (6UL) /*!< CAN_MO MOCTR: RESRTSEL (Bit 6) */ -#define CAN_MO_MOCTR_RESRTSEL_Msk \ - (0x40UL) /*!< CAN_MO MOCTR: RESRTSEL (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOCTR_RESRXEN_Pos \ - (7UL) /*!< CAN_MO MOCTR: RESRXEN (Bit 7) */ -#define CAN_MO_MOCTR_RESRXEN_Msk \ - (0x80UL) /*!< CAN_MO MOCTR: RESRXEN (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOCTR_RESTXRQ_Pos \ - (8UL) /*!< CAN_MO MOCTR: RESTXRQ (Bit 8) */ -#define CAN_MO_MOCTR_RESTXRQ_Msk \ - (0x100UL) /*!< CAN_MO MOCTR: RESTXRQ (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOCTR_RESTXEN0_Pos \ - (9UL) /*!< CAN_MO MOCTR: RESTXEN0 (Bit 9) */ -#define CAN_MO_MOCTR_RESTXEN0_Msk \ - (0x200UL) /*!< CAN_MO MOCTR: RESTXEN0 (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOCTR_RESTXEN1_Pos \ - (10UL) /*!< CAN_MO MOCTR: RESTXEN1 (Bit 10) */ -#define CAN_MO_MOCTR_RESTXEN1_Msk \ - (0x400UL) /*!< CAN_MO MOCTR: RESTXEN1 (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOCTR_RESDIR_Pos \ - (11UL) /*!< CAN_MO MOCTR: RESDIR (Bit 11) */ -#define CAN_MO_MOCTR_RESDIR_Msk \ - (0x800UL) /*!< CAN_MO MOCTR: RESDIR (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOCTR_SETRXPND_Pos \ - (16UL) /*!< CAN_MO MOCTR: SETRXPND (Bit 16) */ -#define CAN_MO_MOCTR_SETRXPND_Msk \ - (0x10000UL) /*!< CAN_MO MOCTR: SETRXPND (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOCTR_SETTXPND_Pos \ - (17UL) /*!< CAN_MO MOCTR: SETTXPND (Bit 17) */ -#define CAN_MO_MOCTR_SETTXPND_Msk \ - (0x20000UL) /*!< CAN_MO MOCTR: SETTXPND (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOCTR_SETRXUPD_Pos \ - (18UL) /*!< CAN_MO MOCTR: SETRXUPD (Bit 18) */ -#define CAN_MO_MOCTR_SETRXUPD_Msk \ - (0x40000UL) /*!< CAN_MO MOCTR: SETRXUPD (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOCTR_SETNEWDAT_Pos \ - (19UL) /*!< CAN_MO MOCTR: SETNEWDAT (Bit 19) */ -#define CAN_MO_MOCTR_SETNEWDAT_Msk \ - (0x80000UL) /*!< CAN_MO MOCTR: SETNEWDAT (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOCTR_SETMSGLST_Pos \ - (20UL) /*!< CAN_MO MOCTR: SETMSGLST (Bit 20) */ -#define CAN_MO_MOCTR_SETMSGLST_Msk \ - (0x100000UL) /*!< CAN_MO MOCTR: SETMSGLST (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOCTR_SETMSGVAL_Pos \ - (21UL) /*!< CAN_MO MOCTR: SETMSGVAL (Bit 21) */ -#define CAN_MO_MOCTR_SETMSGVAL_Msk \ - (0x200000UL) /*!< CAN_MO MOCTR: SETMSGVAL (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOCTR_SETRTSEL_Pos \ - (22UL) /*!< CAN_MO MOCTR: SETRTSEL (Bit 22) */ -#define CAN_MO_MOCTR_SETRTSEL_Msk \ - (0x400000UL) /*!< CAN_MO MOCTR: SETRTSEL (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOCTR_SETRXEN_Pos \ - (23UL) /*!< CAN_MO MOCTR: SETRXEN (Bit 23) */ -#define CAN_MO_MOCTR_SETRXEN_Msk \ - (0x800000UL) /*!< CAN_MO MOCTR: SETRXEN (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOCTR_SETTXRQ_Pos \ - (24UL) /*!< CAN_MO MOCTR: SETTXRQ (Bit 24) */ -#define CAN_MO_MOCTR_SETTXRQ_Msk \ - (0x1000000UL) /*!< CAN_MO MOCTR: SETTXRQ (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOCTR_SETTXEN0_Pos \ - (25UL) /*!< CAN_MO MOCTR: SETTXEN0 (Bit 25) */ -#define CAN_MO_MOCTR_SETTXEN0_Msk \ - (0x2000000UL) /*!< CAN_MO MOCTR: SETTXEN0 (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOCTR_SETTXEN1_Pos \ - (26UL) /*!< CAN_MO MOCTR: SETTXEN1 (Bit 26) */ -#define CAN_MO_MOCTR_SETTXEN1_Msk \ - (0x4000000UL) /*!< CAN_MO MOCTR: SETTXEN1 (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOCTR_SETDIR_Pos \ - (27UL) /*!< CAN_MO MOCTR: SETDIR (Bit 27) */ -#define CAN_MO_MOCTR_SETDIR_Msk \ - (0x8000000UL) /*!< CAN_MO MOCTR: SETDIR (Bitfield-Mask: 0x01) */ - -/* -------------------------------- CAN_MO_MOSTAT ------------------------------- */ -#define CAN_MO_MOSTAT_RXPND_Pos \ - (0UL) /*!< CAN_MO MOSTAT: RXPND (Bit 0) */ -#define CAN_MO_MOSTAT_RXPND_Msk \ - (0x1UL) /*!< CAN_MO MOSTAT: RXPND (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOSTAT_TXPND_Pos \ - (1UL) /*!< CAN_MO MOSTAT: TXPND (Bit 1) */ -#define CAN_MO_MOSTAT_TXPND_Msk \ - (0x2UL) /*!< CAN_MO MOSTAT: TXPND (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOSTAT_RXUPD_Pos \ - (2UL) /*!< CAN_MO MOSTAT: RXUPD (Bit 2) */ -#define CAN_MO_MOSTAT_RXUPD_Msk \ - (0x4UL) /*!< CAN_MO MOSTAT: RXUPD (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOSTAT_NEWDAT_Pos \ - (3UL) /*!< CAN_MO MOSTAT: NEWDAT (Bit 3) */ -#define CAN_MO_MOSTAT_NEWDAT_Msk \ - (0x8UL) /*!< CAN_MO MOSTAT: NEWDAT (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOSTAT_MSGLST_Pos \ - (4UL) /*!< CAN_MO MOSTAT: MSGLST (Bit 4) */ -#define CAN_MO_MOSTAT_MSGLST_Msk \ - (0x10UL) /*!< CAN_MO MOSTAT: MSGLST (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOSTAT_MSGVAL_Pos \ - (5UL) /*!< CAN_MO MOSTAT: MSGVAL (Bit 5) */ -#define CAN_MO_MOSTAT_MSGVAL_Msk \ - (0x20UL) /*!< CAN_MO MOSTAT: MSGVAL (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOSTAT_RTSEL_Pos \ - (6UL) /*!< CAN_MO MOSTAT: RTSEL (Bit 6) */ -#define CAN_MO_MOSTAT_RTSEL_Msk \ - (0x40UL) /*!< CAN_MO MOSTAT: RTSEL (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOSTAT_RXEN_Pos \ - (7UL) /*!< CAN_MO MOSTAT: RXEN (Bit 7) */ -#define CAN_MO_MOSTAT_RXEN_Msk \ - (0x80UL) /*!< CAN_MO MOSTAT: RXEN (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOSTAT_TXRQ_Pos \ - (8UL) /*!< CAN_MO MOSTAT: TXRQ (Bit 8) */ -#define CAN_MO_MOSTAT_TXRQ_Msk \ - (0x100UL) /*!< CAN_MO MOSTAT: TXRQ (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOSTAT_TXEN0_Pos \ - (9UL) /*!< CAN_MO MOSTAT: TXEN0 (Bit 9) */ -#define CAN_MO_MOSTAT_TXEN0_Msk \ - (0x200UL) /*!< CAN_MO MOSTAT: TXEN0 (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOSTAT_TXEN1_Pos \ - (10UL) /*!< CAN_MO MOSTAT: TXEN1 (Bit 10) */ -#define CAN_MO_MOSTAT_TXEN1_Msk \ - (0x400UL) /*!< CAN_MO MOSTAT: TXEN1 (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOSTAT_DIR_Pos \ - (11UL) /*!< CAN_MO MOSTAT: DIR (Bit 11) */ -#define CAN_MO_MOSTAT_DIR_Msk \ - (0x800UL) /*!< CAN_MO MOSTAT: DIR (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOSTAT_LIST_Pos \ - (12UL) /*!< CAN_MO MOSTAT: LIST (Bit 12) */ -#define CAN_MO_MOSTAT_LIST_Msk \ - (0xf000UL) /*!< CAN_MO MOSTAT: LIST (Bitfield-Mask: 0x0f) */ -#define CAN_MO_MOSTAT_PPREV_Pos \ - (16UL) /*!< CAN_MO MOSTAT: PPREV (Bit 16) */ -#define CAN_MO_MOSTAT_PPREV_Msk \ - (0xff0000UL) /*!< CAN_MO MOSTAT: PPREV (Bitfield-Mask: 0xff) */ -#define CAN_MO_MOSTAT_PNEXT_Pos \ - (24UL) /*!< CAN_MO MOSTAT: PNEXT (Bit 24) */ -#define CAN_MO_MOSTAT_PNEXT_Msk \ - (0xff000000UL) /*!< CAN_MO MOSTAT: PNEXT (Bitfield-Mask: 0xff) */ - -/* ================================================================================ */ -/* ================ struct 'VADC' Position & Mask ================ */ -/* ================================================================================ */ - -/* ---------------------------------- VADC_CLC ---------------------------------- */ -#define VADC_CLC_DISR_Pos (0UL) /*!< VADC CLC: DISR (Bit 0) */ -#define VADC_CLC_DISR_Msk \ - (0x1UL) /*!< VADC CLC: DISR (Bitfield-Mask: 0x01) */ -#define VADC_CLC_DISS_Pos (1UL) /*!< VADC CLC: DISS (Bit 1) */ -#define VADC_CLC_DISS_Msk \ - (0x2UL) /*!< VADC CLC: DISS (Bitfield-Mask: 0x01) */ -#define VADC_CLC_EDIS_Pos (3UL) /*!< VADC CLC: EDIS (Bit 3) */ -#define VADC_CLC_EDIS_Msk \ - (0x8UL) /*!< VADC CLC: EDIS (Bitfield-Mask: 0x01) */ - -/* ----------------------------------- VADC_ID ---------------------------------- */ -#define VADC_ID_MOD_REV_Pos \ - (0UL) /*!< VADC ID: MOD_REV (Bit 0) */ -#define VADC_ID_MOD_REV_Msk \ - (0xffUL) /*!< VADC ID: MOD_REV (Bitfield-Mask: 0xff) */ -#define VADC_ID_MOD_TYPE_Pos \ - (8UL) /*!< VADC ID: MOD_TYPE (Bit 8) */ -#define VADC_ID_MOD_TYPE_Msk \ - (0xff00UL) /*!< VADC ID: MOD_TYPE (Bitfield-Mask: 0xff) */ -#define VADC_ID_MOD_NUMBER_Pos \ - (16UL) /*!< VADC ID: MOD_NUMBER (Bit 16) */ -#define VADC_ID_MOD_NUMBER_Msk \ - (0xffff0000UL) /*!< VADC ID: MOD_NUMBER (Bitfield-Mask: 0xffff) */ - -/* ---------------------------------- VADC_OCS ---------------------------------- */ -#define VADC_OCS_TGS_Pos (0UL) /*!< VADC OCS: TGS (Bit 0) */ -#define VADC_OCS_TGS_Msk (0x3UL) /*!< VADC OCS: TGS (Bitfield-Mask: 0x03) */ -#define VADC_OCS_TGB_Pos (2UL) /*!< VADC OCS: TGB (Bit 2) */ -#define VADC_OCS_TGB_Msk (0x4UL) /*!< VADC OCS: TGB (Bitfield-Mask: 0x01) */ -#define VADC_OCS_TG_P_Pos (3UL) /*!< VADC OCS: TG_P (Bit 3) */ -#define VADC_OCS_TG_P_Msk \ - (0x8UL) /*!< VADC OCS: TG_P (Bitfield-Mask: 0x01) */ -#define VADC_OCS_SUS_Pos (24UL) /*!< VADC OCS: SUS (Bit 24) */ -#define VADC_OCS_SUS_Msk \ - (0xf000000UL) /*!< VADC OCS: SUS (Bitfield-Mask: 0x0f) */ -#define VADC_OCS_SUS_P_Pos \ - (28UL) /*!< VADC OCS: SUS_P (Bit 28) */ -#define VADC_OCS_SUS_P_Msk \ - (0x10000000UL) /*!< VADC OCS: SUS_P (Bitfield-Mask: 0x01) */ -#define VADC_OCS_SUSSTA_Pos \ - (29UL) /*!< VADC OCS: SUSSTA (Bit 29) */ -#define VADC_OCS_SUSSTA_Msk \ - (0x20000000UL) /*!< VADC OCS: SUSSTA (Bitfield-Mask: 0x01) */ - -/* -------------------------------- VADC_GLOBCFG -------------------------------- */ -#define VADC_GLOBCFG_DIVA_Pos \ - (0UL) /*!< VADC GLOBCFG: DIVA (Bit 0) */ -#define VADC_GLOBCFG_DIVA_Msk \ - (0x1fUL) /*!< VADC GLOBCFG: DIVA (Bitfield-Mask: 0x1f) */ -#define VADC_GLOBCFG_DCMSB_Pos \ - (7UL) /*!< VADC GLOBCFG: DCMSB (Bit 7) */ -#define VADC_GLOBCFG_DCMSB_Msk \ - (0x80UL) /*!< VADC GLOBCFG: DCMSB (Bitfield-Mask: 0x01) */ -#define VADC_GLOBCFG_DIVD_Pos \ - (8UL) /*!< VADC GLOBCFG: DIVD (Bit 8) */ -#define VADC_GLOBCFG_DIVD_Msk \ - (0x300UL) /*!< VADC GLOBCFG: DIVD (Bitfield-Mask: 0x03) */ -#define VADC_GLOBCFG_DIVWC_Pos \ - (15UL) /*!< VADC GLOBCFG: DIVWC (Bit 15) */ -#define VADC_GLOBCFG_DIVWC_Msk \ - (0x8000UL) /*!< VADC GLOBCFG: DIVWC (Bitfield-Mask: 0x01) */ -#define VADC_GLOBCFG_DPCAL0_Pos \ - (16UL) /*!< VADC GLOBCFG: DPCAL0 (Bit 16) */ -#define VADC_GLOBCFG_DPCAL0_Msk \ - (0x10000UL) /*!< VADC GLOBCFG: DPCAL0 (Bitfield-Mask: 0x01) */ -#define VADC_GLOBCFG_DPCAL1_Pos \ - (17UL) /*!< VADC GLOBCFG: DPCAL1 (Bit 17) */ -#define VADC_GLOBCFG_DPCAL1_Msk \ - (0x20000UL) /*!< VADC GLOBCFG: DPCAL1 (Bitfield-Mask: 0x01) */ -#define VADC_GLOBCFG_DPCAL2_Pos \ - (18UL) /*!< VADC GLOBCFG: DPCAL2 (Bit 18) */ -#define VADC_GLOBCFG_DPCAL2_Msk \ - (0x40000UL) /*!< VADC GLOBCFG: DPCAL2 (Bitfield-Mask: 0x01) */ -#define VADC_GLOBCFG_DPCAL3_Pos \ - (19UL) /*!< VADC GLOBCFG: DPCAL3 (Bit 19) */ -#define VADC_GLOBCFG_DPCAL3_Msk \ - (0x80000UL) /*!< VADC GLOBCFG: DPCAL3 (Bitfield-Mask: 0x01) */ -#define VADC_GLOBCFG_SUCAL_Pos \ - (31UL) /*!< VADC GLOBCFG: SUCAL (Bit 31) */ -#define VADC_GLOBCFG_SUCAL_Msk \ - (0x80000000UL) /*!< VADC GLOBCFG: SUCAL (Bitfield-Mask: 0x01) */ - -/* ------------------------------- VADC_GLOBICLASS ------------------------------ */ -#define VADC_GLOBICLASS_STCS_Pos \ - (0UL) /*!< VADC GLOBICLASS: STCS (Bit 0) */ -#define VADC_GLOBICLASS_STCS_Msk \ - (0x1fUL) /*!< VADC GLOBICLASS: STCS (Bitfield-Mask: 0x1f) */ -#define VADC_GLOBICLASS_CMS_Pos \ - (8UL) /*!< VADC GLOBICLASS: CMS (Bit 8) */ -#define VADC_GLOBICLASS_CMS_Msk \ - (0x700UL) /*!< VADC GLOBICLASS: CMS (Bitfield-Mask: 0x07) */ -#define VADC_GLOBICLASS_STCE_Pos \ - (16UL) /*!< VADC GLOBICLASS: STCE (Bit 16) */ -#define VADC_GLOBICLASS_STCE_Msk \ - (0x1f0000UL) /*!< VADC GLOBICLASS: STCE (Bitfield-Mask: 0x1f) */ -#define VADC_GLOBICLASS_CME_Pos \ - (24UL) /*!< VADC GLOBICLASS: CME (Bit 24) */ -#define VADC_GLOBICLASS_CME_Msk \ - (0x7000000UL) /*!< VADC GLOBICLASS: CME (Bitfield-Mask: 0x07) */ - -/* ------------------------------- VADC_GLOBBOUND ------------------------------- */ -#define VADC_GLOBBOUND_BOUNDARY0_Pos \ - (0UL) /*!< VADC GLOBBOUND: BOUNDARY0 (Bit 0) */ -#define VADC_GLOBBOUND_BOUNDARY0_Msk \ - (0xfffUL) /*!< VADC GLOBBOUND: BOUNDARY0 (Bitfield-Mask: 0xfff) */ -#define VADC_GLOBBOUND_BOUNDARY1_Pos \ - (16UL) /*!< VADC GLOBBOUND: BOUNDARY1 (Bit 16) */ -#define VADC_GLOBBOUND_BOUNDARY1_Msk \ - (0xfff0000UL) /*!< VADC GLOBBOUND: BOUNDARY1 (Bitfield-Mask: 0xfff) */ - -/* ------------------------------- VADC_GLOBEFLAG ------------------------------- */ -#define VADC_GLOBEFLAG_SEVGLB_Pos \ - (0UL) /*!< VADC GLOBEFLAG: SEVGLB (Bit 0) */ -#define VADC_GLOBEFLAG_SEVGLB_Msk \ - (0x1UL) /*!< VADC GLOBEFLAG: SEVGLB (Bitfield-Mask: 0x01) */ -#define VADC_GLOBEFLAG_REVGLB_Pos \ - (8UL) /*!< VADC GLOBEFLAG: REVGLB (Bit 8) */ -#define VADC_GLOBEFLAG_REVGLB_Msk \ - (0x100UL) /*!< VADC GLOBEFLAG: REVGLB (Bitfield-Mask: 0x01) */ -#define VADC_GLOBEFLAG_SEVGLBCLR_Pos \ - (16UL) /*!< VADC GLOBEFLAG: SEVGLBCLR (Bit 16) */ -#define VADC_GLOBEFLAG_SEVGLBCLR_Msk \ - (0x10000UL) /*!< VADC GLOBEFLAG: SEVGLBCLR (Bitfield-Mask: 0x01) */ -#define VADC_GLOBEFLAG_REVGLBCLR_Pos \ - (24UL) /*!< VADC GLOBEFLAG: REVGLBCLR (Bit 24) */ -#define VADC_GLOBEFLAG_REVGLBCLR_Msk \ - (0x1000000UL) /*!< VADC GLOBEFLAG: REVGLBCLR (Bitfield-Mask: 0x01) */ - -/* -------------------------------- VADC_GLOBEVNP ------------------------------- */ -#define VADC_GLOBEVNP_SEV0NP_Pos \ - (0UL) /*!< VADC GLOBEVNP: SEV0NP (Bit 0) */ -#define VADC_GLOBEVNP_SEV0NP_Msk \ - (0xfUL) /*!< VADC GLOBEVNP: SEV0NP (Bitfield-Mask: 0x0f) */ -#define VADC_GLOBEVNP_REV0NP_Pos \ - (16UL) /*!< VADC GLOBEVNP: REV0NP (Bit 16) */ -#define VADC_GLOBEVNP_REV0NP_Msk \ - (0xf0000UL) /*!< VADC GLOBEVNP: REV0NP (Bitfield-Mask: 0x0f) */ - -/* --------------------------------- VADC_GLOBTF -------------------------------- */ -#define VADC_GLOBTF_CDGR_Pos \ - (4UL) /*!< VADC GLOBTF: CDGR (Bit 4) */ -#define VADC_GLOBTF_CDGR_Msk \ - (0xf0UL) /*!< VADC GLOBTF: CDGR (Bitfield-Mask: 0x0f) */ -#define VADC_GLOBTF_CDEN_Pos \ - (8UL) /*!< VADC GLOBTF: CDEN (Bit 8) */ -#define VADC_GLOBTF_CDEN_Msk \ - (0x100UL) /*!< VADC GLOBTF: CDEN (Bitfield-Mask: 0x01) */ -#define VADC_GLOBTF_CDSEL_Pos \ - (9UL) /*!< VADC GLOBTF: CDSEL (Bit 9) */ -#define VADC_GLOBTF_CDSEL_Msk \ - (0x600UL) /*!< VADC GLOBTF: CDSEL (Bitfield-Mask: 0x03) */ -#define VADC_GLOBTF_CDWC_Pos \ - (15UL) /*!< VADC GLOBTF: CDWC (Bit 15) */ -#define VADC_GLOBTF_CDWC_Msk \ - (0x8000UL) /*!< VADC GLOBTF: CDWC (Bitfield-Mask: 0x01) */ -#define VADC_GLOBTF_PDD_Pos \ - (16UL) /*!< VADC GLOBTF: PDD (Bit 16) */ -#define VADC_GLOBTF_PDD_Msk \ - (0x10000UL) /*!< VADC GLOBTF: PDD (Bitfield-Mask: 0x01) */ -#define VADC_GLOBTF_MDWC_Pos \ - (23UL) /*!< VADC GLOBTF: MDWC (Bit 23) */ -#define VADC_GLOBTF_MDWC_Msk \ - (0x800000UL) /*!< VADC GLOBTF: MDWC (Bitfield-Mask: 0x01) */ - -/* --------------------------------- VADC_BRSSEL -------------------------------- */ -#define VADC_BRSSEL_CHSELG0_Pos \ - (0UL) /*!< VADC BRSSEL: CHSELG0 (Bit 0) */ -#define VADC_BRSSEL_CHSELG0_Msk \ - (0x1UL) /*!< VADC BRSSEL: CHSELG0 (Bitfield-Mask: 0x01) */ -#define VADC_BRSSEL_CHSELG1_Pos \ - (1UL) /*!< VADC BRSSEL: CHSELG1 (Bit 1) */ -#define VADC_BRSSEL_CHSELG1_Msk \ - (0x2UL) /*!< VADC BRSSEL: CHSELG1 (Bitfield-Mask: 0x01) */ -#define VADC_BRSSEL_CHSELG2_Pos \ - (2UL) /*!< VADC BRSSEL: CHSELG2 (Bit 2) */ -#define VADC_BRSSEL_CHSELG2_Msk \ - (0x4UL) /*!< VADC BRSSEL: CHSELG2 (Bitfield-Mask: 0x01) */ -#define VADC_BRSSEL_CHSELG3_Pos \ - (3UL) /*!< VADC BRSSEL: CHSELG3 (Bit 3) */ -#define VADC_BRSSEL_CHSELG3_Msk \ - (0x8UL) /*!< VADC BRSSEL: CHSELG3 (Bitfield-Mask: 0x01) */ -#define VADC_BRSSEL_CHSELG4_Pos \ - (4UL) /*!< VADC BRSSEL: CHSELG4 (Bit 4) */ -#define VADC_BRSSEL_CHSELG4_Msk \ - (0x10UL) /*!< VADC BRSSEL: CHSELG4 (Bitfield-Mask: 0x01) */ -#define VADC_BRSSEL_CHSELG5_Pos \ - (5UL) /*!< VADC BRSSEL: CHSELG5 (Bit 5) */ -#define VADC_BRSSEL_CHSELG5_Msk \ - (0x20UL) /*!< VADC BRSSEL: CHSELG5 (Bitfield-Mask: 0x01) */ -#define VADC_BRSSEL_CHSELG6_Pos \ - (6UL) /*!< VADC BRSSEL: CHSELG6 (Bit 6) */ -#define VADC_BRSSEL_CHSELG6_Msk \ - (0x40UL) /*!< VADC BRSSEL: CHSELG6 (Bitfield-Mask: 0x01) */ -#define VADC_BRSSEL_CHSELG7_Pos \ - (7UL) /*!< VADC BRSSEL: CHSELG7 (Bit 7) */ -#define VADC_BRSSEL_CHSELG7_Msk \ - (0x80UL) /*!< VADC BRSSEL: CHSELG7 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- VADC_BRSPND -------------------------------- */ -#define VADC_BRSPND_CHPNDG0_Pos \ - (0UL) /*!< VADC BRSPND: CHPNDG0 (Bit 0) */ -#define VADC_BRSPND_CHPNDG0_Msk \ - (0x1UL) /*!< VADC BRSPND: CHPNDG0 (Bitfield-Mask: 0x01) */ -#define VADC_BRSPND_CHPNDG1_Pos \ - (1UL) /*!< VADC BRSPND: CHPNDG1 (Bit 1) */ -#define VADC_BRSPND_CHPNDG1_Msk \ - (0x2UL) /*!< VADC BRSPND: CHPNDG1 (Bitfield-Mask: 0x01) */ -#define VADC_BRSPND_CHPNDG2_Pos \ - (2UL) /*!< VADC BRSPND: CHPNDG2 (Bit 2) */ -#define VADC_BRSPND_CHPNDG2_Msk \ - (0x4UL) /*!< VADC BRSPND: CHPNDG2 (Bitfield-Mask: 0x01) */ -#define VADC_BRSPND_CHPNDG3_Pos \ - (3UL) /*!< VADC BRSPND: CHPNDG3 (Bit 3) */ -#define VADC_BRSPND_CHPNDG3_Msk \ - (0x8UL) /*!< VADC BRSPND: CHPNDG3 (Bitfield-Mask: 0x01) */ -#define VADC_BRSPND_CHPNDG4_Pos \ - (4UL) /*!< VADC BRSPND: CHPNDG4 (Bit 4) */ -#define VADC_BRSPND_CHPNDG4_Msk \ - (0x10UL) /*!< VADC BRSPND: CHPNDG4 (Bitfield-Mask: 0x01) */ -#define VADC_BRSPND_CHPNDG5_Pos \ - (5UL) /*!< VADC BRSPND: CHPNDG5 (Bit 5) */ -#define VADC_BRSPND_CHPNDG5_Msk \ - (0x20UL) /*!< VADC BRSPND: CHPNDG5 (Bitfield-Mask: 0x01) */ -#define VADC_BRSPND_CHPNDG6_Pos \ - (6UL) /*!< VADC BRSPND: CHPNDG6 (Bit 6) */ -#define VADC_BRSPND_CHPNDG6_Msk \ - (0x40UL) /*!< VADC BRSPND: CHPNDG6 (Bitfield-Mask: 0x01) */ -#define VADC_BRSPND_CHPNDG7_Pos \ - (7UL) /*!< VADC BRSPND: CHPNDG7 (Bit 7) */ -#define VADC_BRSPND_CHPNDG7_Msk \ - (0x80UL) /*!< VADC BRSPND: CHPNDG7 (Bitfield-Mask: 0x01) */ - -/* -------------------------------- VADC_BRSCTRL -------------------------------- */ -#define VADC_BRSCTRL_SRCRESREG_Pos \ - (0UL) /*!< VADC BRSCTRL: SRCRESREG (Bit 0) */ -#define VADC_BRSCTRL_SRCRESREG_Msk \ - (0xfUL) /*!< VADC BRSCTRL: SRCRESREG (Bitfield-Mask: 0x0f) */ -#define VADC_BRSCTRL_XTSEL_Pos \ - (8UL) /*!< VADC BRSCTRL: XTSEL (Bit 8) */ -#define VADC_BRSCTRL_XTSEL_Msk \ - (0xf00UL) /*!< VADC BRSCTRL: XTSEL (Bitfield-Mask: 0x0f) */ -#define VADC_BRSCTRL_XTLVL_Pos \ - (12UL) /*!< VADC BRSCTRL: XTLVL (Bit 12) */ -#define VADC_BRSCTRL_XTLVL_Msk \ - (0x1000UL) /*!< VADC BRSCTRL: XTLVL (Bitfield-Mask: 0x01) */ -#define VADC_BRSCTRL_XTMODE_Pos \ - (13UL) /*!< VADC BRSCTRL: XTMODE (Bit 13) */ -#define VADC_BRSCTRL_XTMODE_Msk \ - (0x6000UL) /*!< VADC BRSCTRL: XTMODE (Bitfield-Mask: 0x03) */ -#define VADC_BRSCTRL_XTWC_Pos \ - (15UL) /*!< VADC BRSCTRL: XTWC (Bit 15) */ -#define VADC_BRSCTRL_XTWC_Msk \ - (0x8000UL) /*!< VADC BRSCTRL: XTWC (Bitfield-Mask: 0x01) */ -#define VADC_BRSCTRL_GTSEL_Pos \ - (16UL) /*!< VADC BRSCTRL: GTSEL (Bit 16) */ -#define VADC_BRSCTRL_GTSEL_Msk \ - (0xf0000UL) /*!< VADC BRSCTRL: GTSEL (Bitfield-Mask: 0x0f) */ -#define VADC_BRSCTRL_GTLVL_Pos \ - (20UL) /*!< VADC BRSCTRL: GTLVL (Bit 20) */ -#define VADC_BRSCTRL_GTLVL_Msk \ - (0x100000UL) /*!< VADC BRSCTRL: GTLVL (Bitfield-Mask: 0x01) */ -#define VADC_BRSCTRL_GTWC_Pos \ - (23UL) /*!< VADC BRSCTRL: GTWC (Bit 23) */ -#define VADC_BRSCTRL_GTWC_Msk \ - (0x800000UL) /*!< VADC BRSCTRL: GTWC (Bitfield-Mask: 0x01) */ - -/* --------------------------------- VADC_BRSMR --------------------------------- */ -#define VADC_BRSMR_ENGT_Pos \ - (0UL) /*!< VADC BRSMR: ENGT (Bit 0) */ -#define VADC_BRSMR_ENGT_Msk \ - (0x3UL) /*!< VADC BRSMR: ENGT (Bitfield-Mask: 0x03) */ -#define VADC_BRSMR_ENTR_Pos \ - (2UL) /*!< VADC BRSMR: ENTR (Bit 2) */ -#define VADC_BRSMR_ENTR_Msk \ - (0x4UL) /*!< VADC BRSMR: ENTR (Bitfield-Mask: 0x01) */ -#define VADC_BRSMR_ENSI_Pos \ - (3UL) /*!< VADC BRSMR: ENSI (Bit 3) */ -#define VADC_BRSMR_ENSI_Msk \ - (0x8UL) /*!< VADC BRSMR: ENSI (Bitfield-Mask: 0x01) */ -#define VADC_BRSMR_SCAN_Pos \ - (4UL) /*!< VADC BRSMR: SCAN (Bit 4) */ -#define VADC_BRSMR_SCAN_Msk \ - (0x10UL) /*!< VADC BRSMR: SCAN (Bitfield-Mask: 0x01) */ -#define VADC_BRSMR_LDM_Pos (5UL) /*!< VADC BRSMR: LDM (Bit 5) */ -#define VADC_BRSMR_LDM_Msk \ - (0x20UL) /*!< VADC BRSMR: LDM (Bitfield-Mask: 0x01) */ -#define VADC_BRSMR_REQGT_Pos \ - (7UL) /*!< VADC BRSMR: REQGT (Bit 7) */ -#define VADC_BRSMR_REQGT_Msk \ - (0x80UL) /*!< VADC BRSMR: REQGT (Bitfield-Mask: 0x01) */ -#define VADC_BRSMR_CLRPND_Pos \ - (8UL) /*!< VADC BRSMR: CLRPND (Bit 8) */ -#define VADC_BRSMR_CLRPND_Msk \ - (0x100UL) /*!< VADC BRSMR: CLRPND (Bitfield-Mask: 0x01) */ -#define VADC_BRSMR_LDEV_Pos \ - (9UL) /*!< VADC BRSMR: LDEV (Bit 9) */ -#define VADC_BRSMR_LDEV_Msk \ - (0x200UL) /*!< VADC BRSMR: LDEV (Bitfield-Mask: 0x01) */ -#define VADC_BRSMR_RPTDIS_Pos \ - (16UL) /*!< VADC BRSMR: RPTDIS (Bit 16) */ -#define VADC_BRSMR_RPTDIS_Msk \ - (0x10000UL) /*!< VADC BRSMR: RPTDIS (Bitfield-Mask: 0x01) */ - -/* -------------------------------- VADC_GLOBRCR -------------------------------- */ -#define VADC_GLOBRCR_DRCTR_Pos \ - (16UL) /*!< VADC GLOBRCR: DRCTR (Bit 16) */ -#define VADC_GLOBRCR_DRCTR_Msk \ - (0xf0000UL) /*!< VADC GLOBRCR: DRCTR (Bitfield-Mask: 0x0f) */ -#define VADC_GLOBRCR_WFR_Pos \ - (24UL) /*!< VADC GLOBRCR: WFR (Bit 24) */ -#define VADC_GLOBRCR_WFR_Msk \ - (0x1000000UL) /*!< VADC GLOBRCR: WFR (Bitfield-Mask: 0x01) */ -#define VADC_GLOBRCR_SRGEN_Pos \ - (31UL) /*!< VADC GLOBRCR: SRGEN (Bit 31) */ -#define VADC_GLOBRCR_SRGEN_Msk \ - (0x80000000UL) /*!< VADC GLOBRCR: SRGEN (Bitfield-Mask: 0x01) */ - -/* -------------------------------- VADC_GLOBRES -------------------------------- */ -#define VADC_GLOBRES_RESULT_Pos \ - (0UL) /*!< VADC GLOBRES: RESULT (Bit 0) */ -#define VADC_GLOBRES_RESULT_Msk \ - (0xffffUL) /*!< VADC GLOBRES: RESULT (Bitfield-Mask: 0xffff) */ -#define VADC_GLOBRES_GNR_Pos \ - (16UL) /*!< VADC GLOBRES: GNR (Bit 16) */ -#define VADC_GLOBRES_GNR_Msk \ - (0xf0000UL) /*!< VADC GLOBRES: GNR (Bitfield-Mask: 0x0f) */ -#define VADC_GLOBRES_CHNR_Pos \ - (20UL) /*!< VADC GLOBRES: CHNR (Bit 20) */ -#define VADC_GLOBRES_CHNR_Msk \ - (0x1f00000UL) /*!< VADC GLOBRES: CHNR (Bitfield-Mask: 0x1f) */ -#define VADC_GLOBRES_EMUX_Pos \ - (25UL) /*!< VADC GLOBRES: EMUX (Bit 25) */ -#define VADC_GLOBRES_EMUX_Msk \ - (0xe000000UL) /*!< VADC GLOBRES: EMUX (Bitfield-Mask: 0x07) */ -#define VADC_GLOBRES_CRS_Pos \ - (28UL) /*!< VADC GLOBRES: CRS (Bit 28) */ -#define VADC_GLOBRES_CRS_Msk \ - (0x30000000UL) /*!< VADC GLOBRES: CRS (Bitfield-Mask: 0x03) */ -#define VADC_GLOBRES_FCR_Pos \ - (30UL) /*!< VADC GLOBRES: FCR (Bit 30) */ -#define VADC_GLOBRES_FCR_Msk \ - (0x40000000UL) /*!< VADC GLOBRES: FCR (Bitfield-Mask: 0x01) */ -#define VADC_GLOBRES_VF_Pos \ - (31UL) /*!< VADC GLOBRES: VF (Bit 31) */ -#define VADC_GLOBRES_VF_Msk \ - (0x80000000UL) /*!< VADC GLOBRES: VF (Bitfield-Mask: 0x01) */ - -/* -------------------------------- VADC_GLOBRESD ------------------------------- */ -#define VADC_GLOBRESD_RESULT_Pos \ - (0UL) /*!< VADC GLOBRESD: RESULT (Bit 0) */ -#define VADC_GLOBRESD_RESULT_Msk \ - (0xffffUL) /*!< VADC GLOBRESD: RESULT (Bitfield-Mask: 0xffff) */ -#define VADC_GLOBRESD_GNR_Pos \ - (16UL) /*!< VADC GLOBRESD: GNR (Bit 16) */ -#define VADC_GLOBRESD_GNR_Msk \ - (0xf0000UL) /*!< VADC GLOBRESD: GNR (Bitfield-Mask: 0x0f) */ -#define VADC_GLOBRESD_CHNR_Pos \ - (20UL) /*!< VADC GLOBRESD: CHNR (Bit 20) */ -#define VADC_GLOBRESD_CHNR_Msk \ - (0x1f00000UL) /*!< VADC GLOBRESD: CHNR (Bitfield-Mask: 0x1f) */ -#define VADC_GLOBRESD_EMUX_Pos \ - (25UL) /*!< VADC GLOBRESD: EMUX (Bit 25) */ -#define VADC_GLOBRESD_EMUX_Msk \ - (0xe000000UL) /*!< VADC GLOBRESD: EMUX (Bitfield-Mask: 0x07) */ -#define VADC_GLOBRESD_CRS_Pos \ - (28UL) /*!< VADC GLOBRESD: CRS (Bit 28) */ -#define VADC_GLOBRESD_CRS_Msk \ - (0x30000000UL) /*!< VADC GLOBRESD: CRS (Bitfield-Mask: 0x03) */ -#define VADC_GLOBRESD_FCR_Pos \ - (30UL) /*!< VADC GLOBRESD: FCR (Bit 30) */ -#define VADC_GLOBRESD_FCR_Msk \ - (0x40000000UL) /*!< VADC GLOBRESD: FCR (Bitfield-Mask: 0x01) */ -#define VADC_GLOBRESD_VF_Pos \ - (31UL) /*!< VADC GLOBRESD: VF (Bit 31) */ -#define VADC_GLOBRESD_VF_Msk \ - (0x80000000UL) /*!< VADC GLOBRESD: VF (Bitfield-Mask: 0x01) */ - -/* -------------------------------- VADC_EMUXSEL -------------------------------- */ -#define VADC_EMUXSEL_EMUXGRP0_Pos \ - (0UL) /*!< VADC EMUXSEL: EMUXGRP0 (Bit 0) */ -#define VADC_EMUXSEL_EMUXGRP0_Msk \ - (0xfUL) /*!< VADC EMUXSEL: EMUXGRP0 (Bitfield-Mask: 0x0f) */ -#define VADC_EMUXSEL_EMUXGRP1_Pos \ - (4UL) /*!< VADC EMUXSEL: EMUXGRP1 (Bit 4) */ -#define VADC_EMUXSEL_EMUXGRP1_Msk \ - (0xf0UL) /*!< VADC EMUXSEL: EMUXGRP1 (Bitfield-Mask: 0x0f) */ - -/* ================================================================================ */ -/* ================ Group 'VADC_G' Position & Mask ================ */ -/* ================================================================================ */ - -/* -------------------------------- VADC_G_ARBCFG ------------------------------- */ -#define VADC_G_ARBCFG_ANONC_Pos \ - (0UL) /*!< VADC_G ARBCFG: ANONC (Bit 0) */ -#define VADC_G_ARBCFG_ANONC_Msk \ - (0x3UL) /*!< VADC_G ARBCFG: ANONC (Bitfield-Mask: 0x03) */ -#define VADC_G_ARBCFG_ARBRND_Pos \ - (4UL) /*!< VADC_G ARBCFG: ARBRND (Bit 4) */ -#define VADC_G_ARBCFG_ARBRND_Msk \ - (0x30UL) /*!< VADC_G ARBCFG: ARBRND (Bitfield-Mask: 0x03) */ -#define VADC_G_ARBCFG_ARBM_Pos \ - (7UL) /*!< VADC_G ARBCFG: ARBM (Bit 7) */ -#define VADC_G_ARBCFG_ARBM_Msk \ - (0x80UL) /*!< VADC_G ARBCFG: ARBM (Bitfield-Mask: 0x01) */ -#define VADC_G_ARBCFG_ANONS_Pos \ - (16UL) /*!< VADC_G ARBCFG: ANONS (Bit 16) */ -#define VADC_G_ARBCFG_ANONS_Msk \ - (0x30000UL) /*!< VADC_G ARBCFG: ANONS (Bitfield-Mask: 0x03) */ -#define VADC_G_ARBCFG_CAL_Pos \ - (28UL) /*!< VADC_G ARBCFG: CAL (Bit 28) */ -#define VADC_G_ARBCFG_CAL_Msk \ - (0x10000000UL) /*!< VADC_G ARBCFG: CAL (Bitfield-Mask: 0x01) */ -#define VADC_G_ARBCFG_BUSY_Pos \ - (30UL) /*!< VADC_G ARBCFG: BUSY (Bit 30) */ -#define VADC_G_ARBCFG_BUSY_Msk \ - (0x40000000UL) /*!< VADC_G ARBCFG: BUSY (Bitfield-Mask: 0x01) */ -#define VADC_G_ARBCFG_SAMPLE_Pos \ - (31UL) /*!< VADC_G ARBCFG: SAMPLE (Bit 31) */ -#define VADC_G_ARBCFG_SAMPLE_Msk \ - (0x80000000UL) /*!< VADC_G ARBCFG: SAMPLE (Bitfield-Mask: 0x01) */ - -/* -------------------------------- VADC_G_ARBPR -------------------------------- */ -#define VADC_G_ARBPR_PRIO0_Pos \ - (0UL) /*!< VADC_G ARBPR: PRIO0 (Bit 0) */ -#define VADC_G_ARBPR_PRIO0_Msk \ - (0x3UL) /*!< VADC_G ARBPR: PRIO0 (Bitfield-Mask: 0x03) */ -#define VADC_G_ARBPR_CSM0_Pos \ - (3UL) /*!< VADC_G ARBPR: CSM0 (Bit 3) */ -#define VADC_G_ARBPR_CSM0_Msk \ - (0x8UL) /*!< VADC_G ARBPR: CSM0 (Bitfield-Mask: 0x01) */ -#define VADC_G_ARBPR_PRIO1_Pos \ - (4UL) /*!< VADC_G ARBPR: PRIO1 (Bit 4) */ -#define VADC_G_ARBPR_PRIO1_Msk \ - (0x30UL) /*!< VADC_G ARBPR: PRIO1 (Bitfield-Mask: 0x03) */ -#define VADC_G_ARBPR_CSM1_Pos \ - (7UL) /*!< VADC_G ARBPR: CSM1 (Bit 7) */ -#define VADC_G_ARBPR_CSM1_Msk \ - (0x80UL) /*!< VADC_G ARBPR: CSM1 (Bitfield-Mask: 0x01) */ -#define VADC_G_ARBPR_PRIO2_Pos \ - (8UL) /*!< VADC_G ARBPR: PRIO2 (Bit 8) */ -#define VADC_G_ARBPR_PRIO2_Msk \ - (0x300UL) /*!< VADC_G ARBPR: PRIO2 (Bitfield-Mask: 0x03) */ -#define VADC_G_ARBPR_CSM2_Pos \ - (11UL) /*!< VADC_G ARBPR: CSM2 (Bit 11) */ -#define VADC_G_ARBPR_CSM2_Msk \ - (0x800UL) /*!< VADC_G ARBPR: CSM2 (Bitfield-Mask: 0x01) */ -#define VADC_G_ARBPR_ASEN0_Pos \ - (24UL) /*!< VADC_G ARBPR: ASEN0 (Bit 24) */ -#define VADC_G_ARBPR_ASEN0_Msk \ - (0x1000000UL) /*!< VADC_G ARBPR: ASEN0 (Bitfield-Mask: 0x01) */ -#define VADC_G_ARBPR_ASEN1_Pos \ - (25UL) /*!< VADC_G ARBPR: ASEN1 (Bit 25) */ -#define VADC_G_ARBPR_ASEN1_Msk \ - (0x2000000UL) /*!< VADC_G ARBPR: ASEN1 (Bitfield-Mask: 0x01) */ -#define VADC_G_ARBPR_ASEN2_Pos \ - (26UL) /*!< VADC_G ARBPR: ASEN2 (Bit 26) */ -#define VADC_G_ARBPR_ASEN2_Msk \ - (0x4000000UL) /*!< VADC_G ARBPR: ASEN2 (Bitfield-Mask: 0x01) */ - -/* -------------------------------- VADC_G_CHASS -------------------------------- */ -#define VADC_G_CHASS_ASSCH0_Pos \ - (0UL) /*!< VADC_G CHASS: ASSCH0 (Bit 0) */ -#define VADC_G_CHASS_ASSCH0_Msk \ - (0x1UL) /*!< VADC_G CHASS: ASSCH0 (Bitfield-Mask: 0x01) */ -#define VADC_G_CHASS_ASSCH1_Pos \ - (1UL) /*!< VADC_G CHASS: ASSCH1 (Bit 1) */ -#define VADC_G_CHASS_ASSCH1_Msk \ - (0x2UL) /*!< VADC_G CHASS: ASSCH1 (Bitfield-Mask: 0x01) */ -#define VADC_G_CHASS_ASSCH2_Pos \ - (2UL) /*!< VADC_G CHASS: ASSCH2 (Bit 2) */ -#define VADC_G_CHASS_ASSCH2_Msk \ - (0x4UL) /*!< VADC_G CHASS: ASSCH2 (Bitfield-Mask: 0x01) */ -#define VADC_G_CHASS_ASSCH3_Pos \ - (3UL) /*!< VADC_G CHASS: ASSCH3 (Bit 3) */ -#define VADC_G_CHASS_ASSCH3_Msk \ - (0x8UL) /*!< VADC_G CHASS: ASSCH3 (Bitfield-Mask: 0x01) */ -#define VADC_G_CHASS_ASSCH4_Pos \ - (4UL) /*!< VADC_G CHASS: ASSCH4 (Bit 4) */ -#define VADC_G_CHASS_ASSCH4_Msk \ - (0x10UL) /*!< VADC_G CHASS: ASSCH4 (Bitfield-Mask: 0x01) */ -#define VADC_G_CHASS_ASSCH5_Pos \ - (5UL) /*!< VADC_G CHASS: ASSCH5 (Bit 5) */ -#define VADC_G_CHASS_ASSCH5_Msk \ - (0x20UL) /*!< VADC_G CHASS: ASSCH5 (Bitfield-Mask: 0x01) */ -#define VADC_G_CHASS_ASSCH6_Pos \ - (6UL) /*!< VADC_G CHASS: ASSCH6 (Bit 6) */ -#define VADC_G_CHASS_ASSCH6_Msk \ - (0x40UL) /*!< VADC_G CHASS: ASSCH6 (Bitfield-Mask: 0x01) */ -#define VADC_G_CHASS_ASSCH7_Pos \ - (7UL) /*!< VADC_G CHASS: ASSCH7 (Bit 7) */ -#define VADC_G_CHASS_ASSCH7_Msk \ - (0x80UL) /*!< VADC_G CHASS: ASSCH7 (Bitfield-Mask: 0x01) */ - -/* -------------------------------- VADC_G_ICLASS ------------------------------- */ -#define VADC_G_ICLASS_STCS_Pos \ - (0UL) /*!< VADC_G ICLASS: STCS (Bit 0) */ -#define VADC_G_ICLASS_STCS_Msk \ - (0x1fUL) /*!< VADC_G ICLASS: STCS (Bitfield-Mask: 0x1f) */ -#define VADC_G_ICLASS_CMS_Pos \ - (8UL) /*!< VADC_G ICLASS: CMS (Bit 8) */ -#define VADC_G_ICLASS_CMS_Msk \ - (0x700UL) /*!< VADC_G ICLASS: CMS (Bitfield-Mask: 0x07) */ -#define VADC_G_ICLASS_STCE_Pos \ - (16UL) /*!< VADC_G ICLASS: STCE (Bit 16) */ -#define VADC_G_ICLASS_STCE_Msk \ - (0x1f0000UL) /*!< VADC_G ICLASS: STCE (Bitfield-Mask: 0x1f) */ -#define VADC_G_ICLASS_CME_Pos \ - (24UL) /*!< VADC_G ICLASS: CME (Bit 24) */ -#define VADC_G_ICLASS_CME_Msk \ - (0x7000000UL) /*!< VADC_G ICLASS: CME (Bitfield-Mask: 0x07) */ - -/* -------------------------------- VADC_G_ALIAS -------------------------------- */ -#define VADC_G_ALIAS_ALIAS0_Pos \ - (0UL) /*!< VADC_G ALIAS: ALIAS0 (Bit 0) */ -#define VADC_G_ALIAS_ALIAS0_Msk \ - (0x1fUL) /*!< VADC_G ALIAS: ALIAS0 (Bitfield-Mask: 0x1f) */ -#define VADC_G_ALIAS_ALIAS1_Pos \ - (8UL) /*!< VADC_G ALIAS: ALIAS1 (Bit 8) */ -#define VADC_G_ALIAS_ALIAS1_Msk \ - (0x1f00UL) /*!< VADC_G ALIAS: ALIAS1 (Bitfield-Mask: 0x1f) */ - -/* -------------------------------- VADC_G_BOUND -------------------------------- */ -#define VADC_G_BOUND_BOUNDARY0_Pos \ - (0UL) /*!< VADC_G BOUND: BOUNDARY0 (Bit 0) */ -#define VADC_G_BOUND_BOUNDARY0_Msk \ - (0xfffUL) /*!< VADC_G BOUND: BOUNDARY0 (Bitfield-Mask: 0xfff) */ -#define VADC_G_BOUND_BOUNDARY1_Pos \ - (16UL) /*!< VADC_G BOUND: BOUNDARY1 (Bit 16) */ -#define VADC_G_BOUND_BOUNDARY1_Msk \ - (0xfff0000UL) /*!< VADC_G BOUND: BOUNDARY1 (Bitfield-Mask: 0xfff) */ - -/* -------------------------------- VADC_G_SYNCTR ------------------------------- */ -#define VADC_G_SYNCTR_STSEL_Pos \ - (0UL) /*!< VADC_G SYNCTR: STSEL (Bit 0) */ -#define VADC_G_SYNCTR_STSEL_Msk \ - (0x3UL) /*!< VADC_G SYNCTR: STSEL (Bitfield-Mask: 0x03) */ -#define VADC_G_SYNCTR_EVALR1_Pos \ - (4UL) /*!< VADC_G SYNCTR: EVALR1 (Bit 4) */ -#define VADC_G_SYNCTR_EVALR1_Msk \ - (0x10UL) /*!< VADC_G SYNCTR: EVALR1 (Bitfield-Mask: 0x01) */ -#define VADC_G_SYNCTR_EVALR2_Pos \ - (5UL) /*!< VADC_G SYNCTR: EVALR2 (Bit 5) */ -#define VADC_G_SYNCTR_EVALR2_Msk \ - (0x20UL) /*!< VADC_G SYNCTR: EVALR2 (Bitfield-Mask: 0x01) */ -#define VADC_G_SYNCTR_EVALR3_Pos \ - (6UL) /*!< VADC_G SYNCTR: EVALR3 (Bit 6) */ -#define VADC_G_SYNCTR_EVALR3_Msk \ - (0x40UL) /*!< VADC_G SYNCTR: EVALR3 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- VADC_G_BFL --------------------------------- */ -#define VADC_G_BFL_BFL0_Pos \ - (0UL) /*!< VADC_G BFL: BFL0 (Bit 0) */ -#define VADC_G_BFL_BFL0_Msk \ - (0x1UL) /*!< VADC_G BFL: BFL0 (Bitfield-Mask: 0x01) */ -#define VADC_G_BFL_BFL1_Pos \ - (1UL) /*!< VADC_G BFL: BFL1 (Bit 1) */ -#define VADC_G_BFL_BFL1_Msk \ - (0x2UL) /*!< VADC_G BFL: BFL1 (Bitfield-Mask: 0x01) */ -#define VADC_G_BFL_BFL2_Pos \ - (2UL) /*!< VADC_G BFL: BFL2 (Bit 2) */ -#define VADC_G_BFL_BFL2_Msk \ - (0x4UL) /*!< VADC_G BFL: BFL2 (Bitfield-Mask: 0x01) */ -#define VADC_G_BFL_BFL3_Pos \ - (3UL) /*!< VADC_G BFL: BFL3 (Bit 3) */ -#define VADC_G_BFL_BFL3_Msk \ - (0x8UL) /*!< VADC_G BFL: BFL3 (Bitfield-Mask: 0x01) */ -#define VADC_G_BFL_BFA0_Pos \ - (8UL) /*!< VADC_G BFL: BFA0 (Bit 8) */ -#define VADC_G_BFL_BFA0_Msk \ - (0x100UL) /*!< VADC_G BFL: BFA0 (Bitfield-Mask: 0x01) */ -#define VADC_G_BFL_BFA1_Pos \ - (9UL) /*!< VADC_G BFL: BFA1 (Bit 9) */ -#define VADC_G_BFL_BFA1_Msk \ - (0x200UL) /*!< VADC_G BFL: BFA1 (Bitfield-Mask: 0x01) */ -#define VADC_G_BFL_BFA2_Pos \ - (10UL) /*!< VADC_G BFL: BFA2 (Bit 10) */ -#define VADC_G_BFL_BFA2_Msk \ - (0x400UL) /*!< VADC_G BFL: BFA2 (Bitfield-Mask: 0x01) */ -#define VADC_G_BFL_BFA3_Pos \ - (11UL) /*!< VADC_G BFL: BFA3 (Bit 11) */ -#define VADC_G_BFL_BFA3_Msk \ - (0x800UL) /*!< VADC_G BFL: BFA3 (Bitfield-Mask: 0x01) */ -#define VADC_G_BFL_BFI0_Pos \ - (16UL) /*!< VADC_G BFL: BFI0 (Bit 16) */ -#define VADC_G_BFL_BFI0_Msk \ - (0x10000UL) /*!< VADC_G BFL: BFI0 (Bitfield-Mask: 0x01) */ -#define VADC_G_BFL_BFI1_Pos \ - (17UL) /*!< VADC_G BFL: BFI1 (Bit 17) */ -#define VADC_G_BFL_BFI1_Msk \ - (0x20000UL) /*!< VADC_G BFL: BFI1 (Bitfield-Mask: 0x01) */ -#define VADC_G_BFL_BFI2_Pos \ - (18UL) /*!< VADC_G BFL: BFI2 (Bit 18) */ -#define VADC_G_BFL_BFI2_Msk \ - (0x40000UL) /*!< VADC_G BFL: BFI2 (Bitfield-Mask: 0x01) */ -#define VADC_G_BFL_BFI3_Pos \ - (19UL) /*!< VADC_G BFL: BFI3 (Bit 19) */ -#define VADC_G_BFL_BFI3_Msk \ - (0x80000UL) /*!< VADC_G BFL: BFI3 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- VADC_G_BFLS -------------------------------- */ -#define VADC_G_BFLS_BFC0_Pos \ - (0UL) /*!< VADC_G BFLS: BFC0 (Bit 0) */ -#define VADC_G_BFLS_BFC0_Msk \ - (0x1UL) /*!< VADC_G BFLS: BFC0 (Bitfield-Mask: 0x01) */ -#define VADC_G_BFLS_BFC1_Pos \ - (1UL) /*!< VADC_G BFLS: BFC1 (Bit 1) */ -#define VADC_G_BFLS_BFC1_Msk \ - (0x2UL) /*!< VADC_G BFLS: BFC1 (Bitfield-Mask: 0x01) */ -#define VADC_G_BFLS_BFC2_Pos \ - (2UL) /*!< VADC_G BFLS: BFC2 (Bit 2) */ -#define VADC_G_BFLS_BFC2_Msk \ - (0x4UL) /*!< VADC_G BFLS: BFC2 (Bitfield-Mask: 0x01) */ -#define VADC_G_BFLS_BFC3_Pos \ - (3UL) /*!< VADC_G BFLS: BFC3 (Bit 3) */ -#define VADC_G_BFLS_BFC3_Msk \ - (0x8UL) /*!< VADC_G BFLS: BFC3 (Bitfield-Mask: 0x01) */ -#define VADC_G_BFLS_BFS0_Pos \ - (16UL) /*!< VADC_G BFLS: BFS0 (Bit 16) */ -#define VADC_G_BFLS_BFS0_Msk \ - (0x10000UL) /*!< VADC_G BFLS: BFS0 (Bitfield-Mask: 0x01) */ -#define VADC_G_BFLS_BFS1_Pos \ - (17UL) /*!< VADC_G BFLS: BFS1 (Bit 17) */ -#define VADC_G_BFLS_BFS1_Msk \ - (0x20000UL) /*!< VADC_G BFLS: BFS1 (Bitfield-Mask: 0x01) */ -#define VADC_G_BFLS_BFS2_Pos \ - (18UL) /*!< VADC_G BFLS: BFS2 (Bit 18) */ -#define VADC_G_BFLS_BFS2_Msk \ - (0x40000UL) /*!< VADC_G BFLS: BFS2 (Bitfield-Mask: 0x01) */ -#define VADC_G_BFLS_BFS3_Pos \ - (19UL) /*!< VADC_G BFLS: BFS3 (Bit 19) */ -#define VADC_G_BFLS_BFS3_Msk \ - (0x80000UL) /*!< VADC_G BFLS: BFS3 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- VADC_G_BFLC -------------------------------- */ -#define VADC_G_BFLC_BFM0_Pos \ - (0UL) /*!< VADC_G BFLC: BFM0 (Bit 0) */ -#define VADC_G_BFLC_BFM0_Msk \ - (0xfUL) /*!< VADC_G BFLC: BFM0 (Bitfield-Mask: 0x0f) */ -#define VADC_G_BFLC_BFM1_Pos \ - (4UL) /*!< VADC_G BFLC: BFM1 (Bit 4) */ -#define VADC_G_BFLC_BFM1_Msk \ - (0xf0UL) /*!< VADC_G BFLC: BFM1 (Bitfield-Mask: 0x0f) */ -#define VADC_G_BFLC_BFM2_Pos \ - (8UL) /*!< VADC_G BFLC: BFM2 (Bit 8) */ -#define VADC_G_BFLC_BFM2_Msk \ - (0xf00UL) /*!< VADC_G BFLC: BFM2 (Bitfield-Mask: 0x0f) */ -#define VADC_G_BFLC_BFM3_Pos \ - (12UL) /*!< VADC_G BFLC: BFM3 (Bit 12) */ -#define VADC_G_BFLC_BFM3_Msk \ - (0xf000UL) /*!< VADC_G BFLC: BFM3 (Bitfield-Mask: 0x0f) */ - -/* -------------------------------- VADC_G_BFLNP -------------------------------- */ -#define VADC_G_BFLNP_BFL0NP_Pos \ - (0UL) /*!< VADC_G BFLNP: BFL0NP (Bit 0) */ -#define VADC_G_BFLNP_BFL0NP_Msk \ - (0xfUL) /*!< VADC_G BFLNP: BFL0NP (Bitfield-Mask: 0x0f) */ -#define VADC_G_BFLNP_BFL1NP_Pos \ - (4UL) /*!< VADC_G BFLNP: BFL1NP (Bit 4) */ -#define VADC_G_BFLNP_BFL1NP_Msk \ - (0xf0UL) /*!< VADC_G BFLNP: BFL1NP (Bitfield-Mask: 0x0f) */ -#define VADC_G_BFLNP_BFL2NP_Pos \ - (8UL) /*!< VADC_G BFLNP: BFL2NP (Bit 8) */ -#define VADC_G_BFLNP_BFL2NP_Msk \ - (0xf00UL) /*!< VADC_G BFLNP: BFL2NP (Bitfield-Mask: 0x0f) */ -#define VADC_G_BFLNP_BFL3NP_Pos \ - (12UL) /*!< VADC_G BFLNP: BFL3NP (Bit 12) */ -#define VADC_G_BFLNP_BFL3NP_Msk \ - (0xf000UL) /*!< VADC_G BFLNP: BFL3NP (Bitfield-Mask: 0x0f) */ - -/* -------------------------------- VADC_G_QCTRL0 ------------------------------- */ -#define VADC_G_QCTRL0_SRCRESREG_Pos \ - (0UL) /*!< VADC_G QCTRL0: SRCRESREG (Bit 0) */ -#define VADC_G_QCTRL0_SRCRESREG_Msk \ - (0xfUL) /*!< VADC_G QCTRL0: SRCRESREG (Bitfield-Mask: 0x0f) */ -#define VADC_G_QCTRL0_XTSEL_Pos \ - (8UL) /*!< VADC_G QCTRL0: XTSEL (Bit 8) */ -#define VADC_G_QCTRL0_XTSEL_Msk \ - (0xf00UL) /*!< VADC_G QCTRL0: XTSEL (Bitfield-Mask: 0x0f) */ -#define VADC_G_QCTRL0_XTLVL_Pos \ - (12UL) /*!< VADC_G QCTRL0: XTLVL (Bit 12) */ -#define VADC_G_QCTRL0_XTLVL_Msk \ - (0x1000UL) /*!< VADC_G QCTRL0: XTLVL (Bitfield-Mask: 0x01) */ -#define VADC_G_QCTRL0_XTMODE_Pos \ - (13UL) /*!< VADC_G QCTRL0: XTMODE (Bit 13) */ -#define VADC_G_QCTRL0_XTMODE_Msk \ - (0x6000UL) /*!< VADC_G QCTRL0: XTMODE (Bitfield-Mask: 0x03) */ -#define VADC_G_QCTRL0_XTWC_Pos \ - (15UL) /*!< VADC_G QCTRL0: XTWC (Bit 15) */ -#define VADC_G_QCTRL0_XTWC_Msk \ - (0x8000UL) /*!< VADC_G QCTRL0: XTWC (Bitfield-Mask: 0x01) */ -#define VADC_G_QCTRL0_GTSEL_Pos \ - (16UL) /*!< VADC_G QCTRL0: GTSEL (Bit 16) */ -#define VADC_G_QCTRL0_GTSEL_Msk \ - (0xf0000UL) /*!< VADC_G QCTRL0: GTSEL (Bitfield-Mask: 0x0f) */ -#define VADC_G_QCTRL0_GTLVL_Pos \ - (20UL) /*!< VADC_G QCTRL0: GTLVL (Bit 20) */ -#define VADC_G_QCTRL0_GTLVL_Msk \ - (0x100000UL) /*!< VADC_G QCTRL0: GTLVL (Bitfield-Mask: 0x01) */ -#define VADC_G_QCTRL0_GTWC_Pos \ - (23UL) /*!< VADC_G QCTRL0: GTWC (Bit 23) */ -#define VADC_G_QCTRL0_GTWC_Msk \ - (0x800000UL) /*!< VADC_G QCTRL0: GTWC (Bitfield-Mask: 0x01) */ -#define VADC_G_QCTRL0_TMEN_Pos \ - (28UL) /*!< VADC_G QCTRL0: TMEN (Bit 28) */ -#define VADC_G_QCTRL0_TMEN_Msk \ - (0x10000000UL) /*!< VADC_G QCTRL0: TMEN (Bitfield-Mask: 0x01) */ -#define VADC_G_QCTRL0_TMWC_Pos \ - (31UL) /*!< VADC_G QCTRL0: TMWC (Bit 31) */ -#define VADC_G_QCTRL0_TMWC_Msk \ - (0x80000000UL) /*!< VADC_G QCTRL0: TMWC (Bitfield-Mask: 0x01) */ - -/* --------------------------------- VADC_G_QMR0 -------------------------------- */ -#define VADC_G_QMR0_ENGT_Pos \ - (0UL) /*!< VADC_G QMR0: ENGT (Bit 0) */ -#define VADC_G_QMR0_ENGT_Msk \ - (0x3UL) /*!< VADC_G QMR0: ENGT (Bitfield-Mask: 0x03) */ -#define VADC_G_QMR0_ENTR_Pos \ - (2UL) /*!< VADC_G QMR0: ENTR (Bit 2) */ -#define VADC_G_QMR0_ENTR_Msk \ - (0x4UL) /*!< VADC_G QMR0: ENTR (Bitfield-Mask: 0x01) */ -#define VADC_G_QMR0_CLRV_Pos \ - (8UL) /*!< VADC_G QMR0: CLRV (Bit 8) */ -#define VADC_G_QMR0_CLRV_Msk \ - (0x100UL) /*!< VADC_G QMR0: CLRV (Bitfield-Mask: 0x01) */ -#define VADC_G_QMR0_TREV_Pos \ - (9UL) /*!< VADC_G QMR0: TREV (Bit 9) */ -#define VADC_G_QMR0_TREV_Msk \ - (0x200UL) /*!< VADC_G QMR0: TREV (Bitfield-Mask: 0x01) */ -#define VADC_G_QMR0_FLUSH_Pos \ - (10UL) /*!< VADC_G QMR0: FLUSH (Bit 10) */ -#define VADC_G_QMR0_FLUSH_Msk \ - (0x400UL) /*!< VADC_G QMR0: FLUSH (Bitfield-Mask: 0x01) */ -#define VADC_G_QMR0_CEV_Pos \ - (11UL) /*!< VADC_G QMR0: CEV (Bit 11) */ -#define VADC_G_QMR0_CEV_Msk \ - (0x800UL) /*!< VADC_G QMR0: CEV (Bitfield-Mask: 0x01) */ -#define VADC_G_QMR0_RPTDIS_Pos \ - (16UL) /*!< VADC_G QMR0: RPTDIS (Bit 16) */ -#define VADC_G_QMR0_RPTDIS_Msk \ - (0x10000UL) /*!< VADC_G QMR0: RPTDIS (Bitfield-Mask: 0x01) */ - -/* --------------------------------- VADC_G_QSR0 -------------------------------- */ -#define VADC_G_QSR0_FILL_Pos \ - (0UL) /*!< VADC_G QSR0: FILL (Bit 0) */ -#define VADC_G_QSR0_FILL_Msk \ - (0xfUL) /*!< VADC_G QSR0: FILL (Bitfield-Mask: 0x0f) */ -#define VADC_G_QSR0_EMPTY_Pos \ - (5UL) /*!< VADC_G QSR0: EMPTY (Bit 5) */ -#define VADC_G_QSR0_EMPTY_Msk \ - (0x20UL) /*!< VADC_G QSR0: EMPTY (Bitfield-Mask: 0x01) */ -#define VADC_G_QSR0_REQGT_Pos \ - (7UL) /*!< VADC_G QSR0: REQGT (Bit 7) */ -#define VADC_G_QSR0_REQGT_Msk \ - (0x80UL) /*!< VADC_G QSR0: REQGT (Bitfield-Mask: 0x01) */ -#define VADC_G_QSR0_EV_Pos (8UL) /*!< VADC_G QSR0: EV (Bit 8) */ -#define VADC_G_QSR0_EV_Msk \ - (0x100UL) /*!< VADC_G QSR0: EV (Bitfield-Mask: 0x01) */ - -/* --------------------------------- VADC_G_Q0R0 -------------------------------- */ -#define VADC_G_Q0R0_REQCHNR_Pos \ - (0UL) /*!< VADC_G Q0R0: REQCHNR (Bit 0) */ -#define VADC_G_Q0R0_REQCHNR_Msk \ - (0x1fUL) /*!< VADC_G Q0R0: REQCHNR (Bitfield-Mask: 0x1f) */ -#define VADC_G_Q0R0_RF_Pos (5UL) /*!< VADC_G Q0R0: RF (Bit 5) */ -#define VADC_G_Q0R0_RF_Msk \ - (0x20UL) /*!< VADC_G Q0R0: RF (Bitfield-Mask: 0x01) */ -#define VADC_G_Q0R0_ENSI_Pos \ - (6UL) /*!< VADC_G Q0R0: ENSI (Bit 6) */ -#define VADC_G_Q0R0_ENSI_Msk \ - (0x40UL) /*!< VADC_G Q0R0: ENSI (Bitfield-Mask: 0x01) */ -#define VADC_G_Q0R0_EXTR_Pos \ - (7UL) /*!< VADC_G Q0R0: EXTR (Bit 7) */ -#define VADC_G_Q0R0_EXTR_Msk \ - (0x80UL) /*!< VADC_G Q0R0: EXTR (Bitfield-Mask: 0x01) */ -#define VADC_G_Q0R0_V_Pos (8UL) /*!< VADC_G Q0R0: V (Bit 8) */ -#define VADC_G_Q0R0_V_Msk \ - (0x100UL) /*!< VADC_G Q0R0: V (Bitfield-Mask: 0x01) */ - -/* -------------------------------- VADC_G_QINR0 -------------------------------- */ -#define VADC_G_QINR0_REQCHNR_Pos \ - (0UL) /*!< VADC_G QINR0: REQCHNR (Bit 0) */ -#define VADC_G_QINR0_REQCHNR_Msk \ - (0x1fUL) /*!< VADC_G QINR0: REQCHNR (Bitfield-Mask: 0x1f) */ -#define VADC_G_QINR0_RF_Pos \ - (5UL) /*!< VADC_G QINR0: RF (Bit 5) */ -#define VADC_G_QINR0_RF_Msk \ - (0x20UL) /*!< VADC_G QINR0: RF (Bitfield-Mask: 0x01) */ -#define VADC_G_QINR0_ENSI_Pos \ - (6UL) /*!< VADC_G QINR0: ENSI (Bit 6) */ -#define VADC_G_QINR0_ENSI_Msk \ - (0x40UL) /*!< VADC_G QINR0: ENSI (Bitfield-Mask: 0x01) */ -#define VADC_G_QINR0_EXTR_Pos \ - (7UL) /*!< VADC_G QINR0: EXTR (Bit 7) */ -#define VADC_G_QINR0_EXTR_Msk \ - (0x80UL) /*!< VADC_G QINR0: EXTR (Bitfield-Mask: 0x01) */ - -/* -------------------------------- VADC_G_QBUR0 -------------------------------- */ -#define VADC_G_QBUR0_REQCHNR_Pos \ - (0UL) /*!< VADC_G QBUR0: REQCHNR (Bit 0) */ -#define VADC_G_QBUR0_REQCHNR_Msk \ - (0x1fUL) /*!< VADC_G QBUR0: REQCHNR (Bitfield-Mask: 0x1f) */ -#define VADC_G_QBUR0_RF_Pos \ - (5UL) /*!< VADC_G QBUR0: RF (Bit 5) */ -#define VADC_G_QBUR0_RF_Msk \ - (0x20UL) /*!< VADC_G QBUR0: RF (Bitfield-Mask: 0x01) */ -#define VADC_G_QBUR0_ENSI_Pos \ - (6UL) /*!< VADC_G QBUR0: ENSI (Bit 6) */ -#define VADC_G_QBUR0_ENSI_Msk \ - (0x40UL) /*!< VADC_G QBUR0: ENSI (Bitfield-Mask: 0x01) */ -#define VADC_G_QBUR0_EXTR_Pos \ - (7UL) /*!< VADC_G QBUR0: EXTR (Bit 7) */ -#define VADC_G_QBUR0_EXTR_Msk \ - (0x80UL) /*!< VADC_G QBUR0: EXTR (Bitfield-Mask: 0x01) */ -#define VADC_G_QBUR0_V_Pos (8UL) /*!< VADC_G QBUR0: V (Bit 8) */ -#define VADC_G_QBUR0_V_Msk \ - (0x100UL) /*!< VADC_G QBUR0: V (Bitfield-Mask: 0x01) */ - -/* -------------------------------- VADC_G_ASCTRL ------------------------------- */ -#define VADC_G_ASCTRL_SRCRESREG_Pos \ - (0UL) /*!< VADC_G ASCTRL: SRCRESREG (Bit 0) */ -#define VADC_G_ASCTRL_SRCRESREG_Msk \ - (0xfUL) /*!< VADC_G ASCTRL: SRCRESREG (Bitfield-Mask: 0x0f) */ -#define VADC_G_ASCTRL_XTSEL_Pos \ - (8UL) /*!< VADC_G ASCTRL: XTSEL (Bit 8) */ -#define VADC_G_ASCTRL_XTSEL_Msk \ - (0xf00UL) /*!< VADC_G ASCTRL: XTSEL (Bitfield-Mask: 0x0f) */ -#define VADC_G_ASCTRL_XTLVL_Pos \ - (12UL) /*!< VADC_G ASCTRL: XTLVL (Bit 12) */ -#define VADC_G_ASCTRL_XTLVL_Msk \ - (0x1000UL) /*!< VADC_G ASCTRL: XTLVL (Bitfield-Mask: 0x01) */ -#define VADC_G_ASCTRL_XTMODE_Pos \ - (13UL) /*!< VADC_G ASCTRL: XTMODE (Bit 13) */ -#define VADC_G_ASCTRL_XTMODE_Msk \ - (0x6000UL) /*!< VADC_G ASCTRL: XTMODE (Bitfield-Mask: 0x03) */ -#define VADC_G_ASCTRL_XTWC_Pos \ - (15UL) /*!< VADC_G ASCTRL: XTWC (Bit 15) */ -#define VADC_G_ASCTRL_XTWC_Msk \ - (0x8000UL) /*!< VADC_G ASCTRL: XTWC (Bitfield-Mask: 0x01) */ -#define VADC_G_ASCTRL_GTSEL_Pos \ - (16UL) /*!< VADC_G ASCTRL: GTSEL (Bit 16) */ -#define VADC_G_ASCTRL_GTSEL_Msk \ - (0xf0000UL) /*!< VADC_G ASCTRL: GTSEL (Bitfield-Mask: 0x0f) */ -#define VADC_G_ASCTRL_GTLVL_Pos \ - (20UL) /*!< VADC_G ASCTRL: GTLVL (Bit 20) */ -#define VADC_G_ASCTRL_GTLVL_Msk \ - (0x100000UL) /*!< VADC_G ASCTRL: GTLVL (Bitfield-Mask: 0x01) */ -#define VADC_G_ASCTRL_GTWC_Pos \ - (23UL) /*!< VADC_G ASCTRL: GTWC (Bit 23) */ -#define VADC_G_ASCTRL_GTWC_Msk \ - (0x800000UL) /*!< VADC_G ASCTRL: GTWC (Bitfield-Mask: 0x01) */ -#define VADC_G_ASCTRL_TMEN_Pos \ - (28UL) /*!< VADC_G ASCTRL: TMEN (Bit 28) */ -#define VADC_G_ASCTRL_TMEN_Msk \ - (0x10000000UL) /*!< VADC_G ASCTRL: TMEN (Bitfield-Mask: 0x01) */ -#define VADC_G_ASCTRL_TMWC_Pos \ - (31UL) /*!< VADC_G ASCTRL: TMWC (Bit 31) */ -#define VADC_G_ASCTRL_TMWC_Msk \ - (0x80000000UL) /*!< VADC_G ASCTRL: TMWC (Bitfield-Mask: 0x01) */ - -/* --------------------------------- VADC_G_ASMR -------------------------------- */ -#define VADC_G_ASMR_ENGT_Pos \ - (0UL) /*!< VADC_G ASMR: ENGT (Bit 0) */ -#define VADC_G_ASMR_ENGT_Msk \ - (0x3UL) /*!< VADC_G ASMR: ENGT (Bitfield-Mask: 0x03) */ -#define VADC_G_ASMR_ENTR_Pos \ - (2UL) /*!< VADC_G ASMR: ENTR (Bit 2) */ -#define VADC_G_ASMR_ENTR_Msk \ - (0x4UL) /*!< VADC_G ASMR: ENTR (Bitfield-Mask: 0x01) */ -#define VADC_G_ASMR_ENSI_Pos \ - (3UL) /*!< VADC_G ASMR: ENSI (Bit 3) */ -#define VADC_G_ASMR_ENSI_Msk \ - (0x8UL) /*!< VADC_G ASMR: ENSI (Bitfield-Mask: 0x01) */ -#define VADC_G_ASMR_SCAN_Pos \ - (4UL) /*!< VADC_G ASMR: SCAN (Bit 4) */ -#define VADC_G_ASMR_SCAN_Msk \ - (0x10UL) /*!< VADC_G ASMR: SCAN (Bitfield-Mask: 0x01) */ -#define VADC_G_ASMR_LDM_Pos \ - (5UL) /*!< VADC_G ASMR: LDM (Bit 5) */ -#define VADC_G_ASMR_LDM_Msk \ - (0x20UL) /*!< VADC_G ASMR: LDM (Bitfield-Mask: 0x01) */ -#define VADC_G_ASMR_REQGT_Pos \ - (7UL) /*!< VADC_G ASMR: REQGT (Bit 7) */ -#define VADC_G_ASMR_REQGT_Msk \ - (0x80UL) /*!< VADC_G ASMR: REQGT (Bitfield-Mask: 0x01) */ -#define VADC_G_ASMR_CLRPND_Pos \ - (8UL) /*!< VADC_G ASMR: CLRPND (Bit 8) */ -#define VADC_G_ASMR_CLRPND_Msk \ - (0x100UL) /*!< VADC_G ASMR: CLRPND (Bitfield-Mask: 0x01) */ -#define VADC_G_ASMR_LDEV_Pos \ - (9UL) /*!< VADC_G ASMR: LDEV (Bit 9) */ -#define VADC_G_ASMR_LDEV_Msk \ - (0x200UL) /*!< VADC_G ASMR: LDEV (Bitfield-Mask: 0x01) */ -#define VADC_G_ASMR_RPTDIS_Pos \ - (16UL) /*!< VADC_G ASMR: RPTDIS (Bit 16) */ -#define VADC_G_ASMR_RPTDIS_Msk \ - (0x10000UL) /*!< VADC_G ASMR: RPTDIS (Bitfield-Mask: 0x01) */ - -/* -------------------------------- VADC_G_ASSEL -------------------------------- */ -#define VADC_G_ASSEL_CHSEL0_Pos \ - (0UL) /*!< VADC_G ASSEL: CHSEL0 (Bit 0) */ -#define VADC_G_ASSEL_CHSEL0_Msk \ - (0x1UL) /*!< VADC_G ASSEL: CHSEL0 (Bitfield-Mask: 0x01) */ -#define VADC_G_ASSEL_CHSEL1_Pos \ - (1UL) /*!< VADC_G ASSEL: CHSEL1 (Bit 1) */ -#define VADC_G_ASSEL_CHSEL1_Msk \ - (0x2UL) /*!< VADC_G ASSEL: CHSEL1 (Bitfield-Mask: 0x01) */ -#define VADC_G_ASSEL_CHSEL2_Pos \ - (2UL) /*!< VADC_G ASSEL: CHSEL2 (Bit 2) */ -#define VADC_G_ASSEL_CHSEL2_Msk \ - (0x4UL) /*!< VADC_G ASSEL: CHSEL2 (Bitfield-Mask: 0x01) */ -#define VADC_G_ASSEL_CHSEL3_Pos \ - (3UL) /*!< VADC_G ASSEL: CHSEL3 (Bit 3) */ -#define VADC_G_ASSEL_CHSEL3_Msk \ - (0x8UL) /*!< VADC_G ASSEL: CHSEL3 (Bitfield-Mask: 0x01) */ -#define VADC_G_ASSEL_CHSEL4_Pos \ - (4UL) /*!< VADC_G ASSEL: CHSEL4 (Bit 4) */ -#define VADC_G_ASSEL_CHSEL4_Msk \ - (0x10UL) /*!< VADC_G ASSEL: CHSEL4 (Bitfield-Mask: 0x01) */ -#define VADC_G_ASSEL_CHSEL5_Pos \ - (5UL) /*!< VADC_G ASSEL: CHSEL5 (Bit 5) */ -#define VADC_G_ASSEL_CHSEL5_Msk \ - (0x20UL) /*!< VADC_G ASSEL: CHSEL5 (Bitfield-Mask: 0x01) */ -#define VADC_G_ASSEL_CHSEL6_Pos \ - (6UL) /*!< VADC_G ASSEL: CHSEL6 (Bit 6) */ -#define VADC_G_ASSEL_CHSEL6_Msk \ - (0x40UL) /*!< VADC_G ASSEL: CHSEL6 (Bitfield-Mask: 0x01) */ -#define VADC_G_ASSEL_CHSEL7_Pos \ - (7UL) /*!< VADC_G ASSEL: CHSEL7 (Bit 7) */ -#define VADC_G_ASSEL_CHSEL7_Msk \ - (0x80UL) /*!< VADC_G ASSEL: CHSEL7 (Bitfield-Mask: 0x01) */ - -/* -------------------------------- VADC_G_ASPND -------------------------------- */ -#define VADC_G_ASPND_CHPND0_Pos \ - (0UL) /*!< VADC_G ASPND: CHPND0 (Bit 0) */ -#define VADC_G_ASPND_CHPND0_Msk \ - (0x1UL) /*!< VADC_G ASPND: CHPND0 (Bitfield-Mask: 0x01) */ -#define VADC_G_ASPND_CHPND1_Pos \ - (1UL) /*!< VADC_G ASPND: CHPND1 (Bit 1) */ -#define VADC_G_ASPND_CHPND1_Msk \ - (0x2UL) /*!< VADC_G ASPND: CHPND1 (Bitfield-Mask: 0x01) */ -#define VADC_G_ASPND_CHPND2_Pos \ - (2UL) /*!< VADC_G ASPND: CHPND2 (Bit 2) */ -#define VADC_G_ASPND_CHPND2_Msk \ - (0x4UL) /*!< VADC_G ASPND: CHPND2 (Bitfield-Mask: 0x01) */ -#define VADC_G_ASPND_CHPND3_Pos \ - (3UL) /*!< VADC_G ASPND: CHPND3 (Bit 3) */ -#define VADC_G_ASPND_CHPND3_Msk \ - (0x8UL) /*!< VADC_G ASPND: CHPND3 (Bitfield-Mask: 0x01) */ -#define VADC_G_ASPND_CHPND4_Pos \ - (4UL) /*!< VADC_G ASPND: CHPND4 (Bit 4) */ -#define VADC_G_ASPND_CHPND4_Msk \ - (0x10UL) /*!< VADC_G ASPND: CHPND4 (Bitfield-Mask: 0x01) */ -#define VADC_G_ASPND_CHPND5_Pos \ - (5UL) /*!< VADC_G ASPND: CHPND5 (Bit 5) */ -#define VADC_G_ASPND_CHPND5_Msk \ - (0x20UL) /*!< VADC_G ASPND: CHPND5 (Bitfield-Mask: 0x01) */ -#define VADC_G_ASPND_CHPND6_Pos \ - (6UL) /*!< VADC_G ASPND: CHPND6 (Bit 6) */ -#define VADC_G_ASPND_CHPND6_Msk \ - (0x40UL) /*!< VADC_G ASPND: CHPND6 (Bitfield-Mask: 0x01) */ -#define VADC_G_ASPND_CHPND7_Pos \ - (7UL) /*!< VADC_G ASPND: CHPND7 (Bit 7) */ -#define VADC_G_ASPND_CHPND7_Msk \ - (0x80UL) /*!< VADC_G ASPND: CHPND7 (Bitfield-Mask: 0x01) */ - -/* -------------------------------- VADC_G_CEFLAG ------------------------------- */ -#define VADC_G_CEFLAG_CEV0_Pos \ - (0UL) /*!< VADC_G CEFLAG: CEV0 (Bit 0) */ -#define VADC_G_CEFLAG_CEV0_Msk \ - (0x1UL) /*!< VADC_G CEFLAG: CEV0 (Bitfield-Mask: 0x01) */ -#define VADC_G_CEFLAG_CEV1_Pos \ - (1UL) /*!< VADC_G CEFLAG: CEV1 (Bit 1) */ -#define VADC_G_CEFLAG_CEV1_Msk \ - (0x2UL) /*!< VADC_G CEFLAG: CEV1 (Bitfield-Mask: 0x01) */ -#define VADC_G_CEFLAG_CEV2_Pos \ - (2UL) /*!< VADC_G CEFLAG: CEV2 (Bit 2) */ -#define VADC_G_CEFLAG_CEV2_Msk \ - (0x4UL) /*!< VADC_G CEFLAG: CEV2 (Bitfield-Mask: 0x01) */ -#define VADC_G_CEFLAG_CEV3_Pos \ - (3UL) /*!< VADC_G CEFLAG: CEV3 (Bit 3) */ -#define VADC_G_CEFLAG_CEV3_Msk \ - (0x8UL) /*!< VADC_G CEFLAG: CEV3 (Bitfield-Mask: 0x01) */ -#define VADC_G_CEFLAG_CEV4_Pos \ - (4UL) /*!< VADC_G CEFLAG: CEV4 (Bit 4) */ -#define VADC_G_CEFLAG_CEV4_Msk \ - (0x10UL) /*!< VADC_G CEFLAG: CEV4 (Bitfield-Mask: 0x01) */ -#define VADC_G_CEFLAG_CEV5_Pos \ - (5UL) /*!< VADC_G CEFLAG: CEV5 (Bit 5) */ -#define VADC_G_CEFLAG_CEV5_Msk \ - (0x20UL) /*!< VADC_G CEFLAG: CEV5 (Bitfield-Mask: 0x01) */ -#define VADC_G_CEFLAG_CEV6_Pos \ - (6UL) /*!< VADC_G CEFLAG: CEV6 (Bit 6) */ -#define VADC_G_CEFLAG_CEV6_Msk \ - (0x40UL) /*!< VADC_G CEFLAG: CEV6 (Bitfield-Mask: 0x01) */ -#define VADC_G_CEFLAG_CEV7_Pos \ - (7UL) /*!< VADC_G CEFLAG: CEV7 (Bit 7) */ -#define VADC_G_CEFLAG_CEV7_Msk \ - (0x80UL) /*!< VADC_G CEFLAG: CEV7 (Bitfield-Mask: 0x01) */ - -/* -------------------------------- VADC_G_REFLAG ------------------------------- */ -#define VADC_G_REFLAG_REV0_Pos \ - (0UL) /*!< VADC_G REFLAG: REV0 (Bit 0) */ -#define VADC_G_REFLAG_REV0_Msk \ - (0x1UL) /*!< VADC_G REFLAG: REV0 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFLAG_REV1_Pos \ - (1UL) /*!< VADC_G REFLAG: REV1 (Bit 1) */ -#define VADC_G_REFLAG_REV1_Msk \ - (0x2UL) /*!< VADC_G REFLAG: REV1 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFLAG_REV2_Pos \ - (2UL) /*!< VADC_G REFLAG: REV2 (Bit 2) */ -#define VADC_G_REFLAG_REV2_Msk \ - (0x4UL) /*!< VADC_G REFLAG: REV2 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFLAG_REV3_Pos \ - (3UL) /*!< VADC_G REFLAG: REV3 (Bit 3) */ -#define VADC_G_REFLAG_REV3_Msk \ - (0x8UL) /*!< VADC_G REFLAG: REV3 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFLAG_REV4_Pos \ - (4UL) /*!< VADC_G REFLAG: REV4 (Bit 4) */ -#define VADC_G_REFLAG_REV4_Msk \ - (0x10UL) /*!< VADC_G REFLAG: REV4 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFLAG_REV5_Pos \ - (5UL) /*!< VADC_G REFLAG: REV5 (Bit 5) */ -#define VADC_G_REFLAG_REV5_Msk \ - (0x20UL) /*!< VADC_G REFLAG: REV5 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFLAG_REV6_Pos \ - (6UL) /*!< VADC_G REFLAG: REV6 (Bit 6) */ -#define VADC_G_REFLAG_REV6_Msk \ - (0x40UL) /*!< VADC_G REFLAG: REV6 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFLAG_REV7_Pos \ - (7UL) /*!< VADC_G REFLAG: REV7 (Bit 7) */ -#define VADC_G_REFLAG_REV7_Msk \ - (0x80UL) /*!< VADC_G REFLAG: REV7 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFLAG_REV8_Pos \ - (8UL) /*!< VADC_G REFLAG: REV8 (Bit 8) */ -#define VADC_G_REFLAG_REV8_Msk \ - (0x100UL) /*!< VADC_G REFLAG: REV8 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFLAG_REV9_Pos \ - (9UL) /*!< VADC_G REFLAG: REV9 (Bit 9) */ -#define VADC_G_REFLAG_REV9_Msk \ - (0x200UL) /*!< VADC_G REFLAG: REV9 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFLAG_REV10_Pos \ - (10UL) /*!< VADC_G REFLAG: REV10 (Bit 10) */ -#define VADC_G_REFLAG_REV10_Msk \ - (0x400UL) /*!< VADC_G REFLAG: REV10 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFLAG_REV11_Pos \ - (11UL) /*!< VADC_G REFLAG: REV11 (Bit 11) */ -#define VADC_G_REFLAG_REV11_Msk \ - (0x800UL) /*!< VADC_G REFLAG: REV11 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFLAG_REV12_Pos \ - (12UL) /*!< VADC_G REFLAG: REV12 (Bit 12) */ -#define VADC_G_REFLAG_REV12_Msk \ - (0x1000UL) /*!< VADC_G REFLAG: REV12 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFLAG_REV13_Pos \ - (13UL) /*!< VADC_G REFLAG: REV13 (Bit 13) */ -#define VADC_G_REFLAG_REV13_Msk \ - (0x2000UL) /*!< VADC_G REFLAG: REV13 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFLAG_REV14_Pos \ - (14UL) /*!< VADC_G REFLAG: REV14 (Bit 14) */ -#define VADC_G_REFLAG_REV14_Msk \ - (0x4000UL) /*!< VADC_G REFLAG: REV14 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFLAG_REV15_Pos \ - (15UL) /*!< VADC_G REFLAG: REV15 (Bit 15) */ -#define VADC_G_REFLAG_REV15_Msk \ - (0x8000UL) /*!< VADC_G REFLAG: REV15 (Bitfield-Mask: 0x01) */ - -/* -------------------------------- VADC_G_SEFLAG ------------------------------- */ -#define VADC_G_SEFLAG_SEV0_Pos \ - (0UL) /*!< VADC_G SEFLAG: SEV0 (Bit 0) */ -#define VADC_G_SEFLAG_SEV0_Msk \ - (0x1UL) /*!< VADC_G SEFLAG: SEV0 (Bitfield-Mask: 0x01) */ -#define VADC_G_SEFLAG_SEV1_Pos \ - (1UL) /*!< VADC_G SEFLAG: SEV1 (Bit 1) */ -#define VADC_G_SEFLAG_SEV1_Msk \ - (0x2UL) /*!< VADC_G SEFLAG: SEV1 (Bitfield-Mask: 0x01) */ - -/* -------------------------------- VADC_G_CEFCLR ------------------------------- */ -#define VADC_G_CEFCLR_CEV0_Pos \ - (0UL) /*!< VADC_G CEFCLR: CEV0 (Bit 0) */ -#define VADC_G_CEFCLR_CEV0_Msk \ - (0x1UL) /*!< VADC_G CEFCLR: CEV0 (Bitfield-Mask: 0x01) */ -#define VADC_G_CEFCLR_CEV1_Pos \ - (1UL) /*!< VADC_G CEFCLR: CEV1 (Bit 1) */ -#define VADC_G_CEFCLR_CEV1_Msk \ - (0x2UL) /*!< VADC_G CEFCLR: CEV1 (Bitfield-Mask: 0x01) */ -#define VADC_G_CEFCLR_CEV2_Pos \ - (2UL) /*!< VADC_G CEFCLR: CEV2 (Bit 2) */ -#define VADC_G_CEFCLR_CEV2_Msk \ - (0x4UL) /*!< VADC_G CEFCLR: CEV2 (Bitfield-Mask: 0x01) */ -#define VADC_G_CEFCLR_CEV3_Pos \ - (3UL) /*!< VADC_G CEFCLR: CEV3 (Bit 3) */ -#define VADC_G_CEFCLR_CEV3_Msk \ - (0x8UL) /*!< VADC_G CEFCLR: CEV3 (Bitfield-Mask: 0x01) */ -#define VADC_G_CEFCLR_CEV4_Pos \ - (4UL) /*!< VADC_G CEFCLR: CEV4 (Bit 4) */ -#define VADC_G_CEFCLR_CEV4_Msk \ - (0x10UL) /*!< VADC_G CEFCLR: CEV4 (Bitfield-Mask: 0x01) */ -#define VADC_G_CEFCLR_CEV5_Pos \ - (5UL) /*!< VADC_G CEFCLR: CEV5 (Bit 5) */ -#define VADC_G_CEFCLR_CEV5_Msk \ - (0x20UL) /*!< VADC_G CEFCLR: CEV5 (Bitfield-Mask: 0x01) */ -#define VADC_G_CEFCLR_CEV6_Pos \ - (6UL) /*!< VADC_G CEFCLR: CEV6 (Bit 6) */ -#define VADC_G_CEFCLR_CEV6_Msk \ - (0x40UL) /*!< VADC_G CEFCLR: CEV6 (Bitfield-Mask: 0x01) */ -#define VADC_G_CEFCLR_CEV7_Pos \ - (7UL) /*!< VADC_G CEFCLR: CEV7 (Bit 7) */ -#define VADC_G_CEFCLR_CEV7_Msk \ - (0x80UL) /*!< VADC_G CEFCLR: CEV7 (Bitfield-Mask: 0x01) */ - -/* -------------------------------- VADC_G_REFCLR ------------------------------- */ -#define VADC_G_REFCLR_REV0_Pos \ - (0UL) /*!< VADC_G REFCLR: REV0 (Bit 0) */ -#define VADC_G_REFCLR_REV0_Msk \ - (0x1UL) /*!< VADC_G REFCLR: REV0 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFCLR_REV1_Pos \ - (1UL) /*!< VADC_G REFCLR: REV1 (Bit 1) */ -#define VADC_G_REFCLR_REV1_Msk \ - (0x2UL) /*!< VADC_G REFCLR: REV1 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFCLR_REV2_Pos \ - (2UL) /*!< VADC_G REFCLR: REV2 (Bit 2) */ -#define VADC_G_REFCLR_REV2_Msk \ - (0x4UL) /*!< VADC_G REFCLR: REV2 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFCLR_REV3_Pos \ - (3UL) /*!< VADC_G REFCLR: REV3 (Bit 3) */ -#define VADC_G_REFCLR_REV3_Msk \ - (0x8UL) /*!< VADC_G REFCLR: REV3 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFCLR_REV4_Pos \ - (4UL) /*!< VADC_G REFCLR: REV4 (Bit 4) */ -#define VADC_G_REFCLR_REV4_Msk \ - (0x10UL) /*!< VADC_G REFCLR: REV4 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFCLR_REV5_Pos \ - (5UL) /*!< VADC_G REFCLR: REV5 (Bit 5) */ -#define VADC_G_REFCLR_REV5_Msk \ - (0x20UL) /*!< VADC_G REFCLR: REV5 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFCLR_REV6_Pos \ - (6UL) /*!< VADC_G REFCLR: REV6 (Bit 6) */ -#define VADC_G_REFCLR_REV6_Msk \ - (0x40UL) /*!< VADC_G REFCLR: REV6 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFCLR_REV7_Pos \ - (7UL) /*!< VADC_G REFCLR: REV7 (Bit 7) */ -#define VADC_G_REFCLR_REV7_Msk \ - (0x80UL) /*!< VADC_G REFCLR: REV7 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFCLR_REV8_Pos \ - (8UL) /*!< VADC_G REFCLR: REV8 (Bit 8) */ -#define VADC_G_REFCLR_REV8_Msk \ - (0x100UL) /*!< VADC_G REFCLR: REV8 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFCLR_REV9_Pos \ - (9UL) /*!< VADC_G REFCLR: REV9 (Bit 9) */ -#define VADC_G_REFCLR_REV9_Msk \ - (0x200UL) /*!< VADC_G REFCLR: REV9 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFCLR_REV10_Pos \ - (10UL) /*!< VADC_G REFCLR: REV10 (Bit 10) */ -#define VADC_G_REFCLR_REV10_Msk \ - (0x400UL) /*!< VADC_G REFCLR: REV10 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFCLR_REV11_Pos \ - (11UL) /*!< VADC_G REFCLR: REV11 (Bit 11) */ -#define VADC_G_REFCLR_REV11_Msk \ - (0x800UL) /*!< VADC_G REFCLR: REV11 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFCLR_REV12_Pos \ - (12UL) /*!< VADC_G REFCLR: REV12 (Bit 12) */ -#define VADC_G_REFCLR_REV12_Msk \ - (0x1000UL) /*!< VADC_G REFCLR: REV12 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFCLR_REV13_Pos \ - (13UL) /*!< VADC_G REFCLR: REV13 (Bit 13) */ -#define VADC_G_REFCLR_REV13_Msk \ - (0x2000UL) /*!< VADC_G REFCLR: REV13 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFCLR_REV14_Pos \ - (14UL) /*!< VADC_G REFCLR: REV14 (Bit 14) */ -#define VADC_G_REFCLR_REV14_Msk \ - (0x4000UL) /*!< VADC_G REFCLR: REV14 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFCLR_REV15_Pos \ - (15UL) /*!< VADC_G REFCLR: REV15 (Bit 15) */ -#define VADC_G_REFCLR_REV15_Msk \ - (0x8000UL) /*!< VADC_G REFCLR: REV15 (Bitfield-Mask: 0x01) */ - -/* -------------------------------- VADC_G_SEFCLR ------------------------------- */ -#define VADC_G_SEFCLR_SEV0_Pos \ - (0UL) /*!< VADC_G SEFCLR: SEV0 (Bit 0) */ -#define VADC_G_SEFCLR_SEV0_Msk \ - (0x1UL) /*!< VADC_G SEFCLR: SEV0 (Bitfield-Mask: 0x01) */ -#define VADC_G_SEFCLR_SEV1_Pos \ - (1UL) /*!< VADC_G SEFCLR: SEV1 (Bit 1) */ -#define VADC_G_SEFCLR_SEV1_Msk \ - (0x2UL) /*!< VADC_G SEFCLR: SEV1 (Bitfield-Mask: 0x01) */ - -/* -------------------------------- VADC_G_CEVNP0 ------------------------------- */ -#define VADC_G_CEVNP0_CEV0NP_Pos \ - (0UL) /*!< VADC_G CEVNP0: CEV0NP (Bit 0) */ -#define VADC_G_CEVNP0_CEV0NP_Msk \ - (0xfUL) /*!< VADC_G CEVNP0: CEV0NP (Bitfield-Mask: 0x0f) */ -#define VADC_G_CEVNP0_CEV1NP_Pos \ - (4UL) /*!< VADC_G CEVNP0: CEV1NP (Bit 4) */ -#define VADC_G_CEVNP0_CEV1NP_Msk \ - (0xf0UL) /*!< VADC_G CEVNP0: CEV1NP (Bitfield-Mask: 0x0f) */ -#define VADC_G_CEVNP0_CEV2NP_Pos \ - (8UL) /*!< VADC_G CEVNP0: CEV2NP (Bit 8) */ -#define VADC_G_CEVNP0_CEV2NP_Msk \ - (0xf00UL) /*!< VADC_G CEVNP0: CEV2NP (Bitfield-Mask: 0x0f) */ -#define VADC_G_CEVNP0_CEV3NP_Pos \ - (12UL) /*!< VADC_G CEVNP0: CEV3NP (Bit 12) */ -#define VADC_G_CEVNP0_CEV3NP_Msk \ - (0xf000UL) /*!< VADC_G CEVNP0: CEV3NP (Bitfield-Mask: 0x0f) */ -#define VADC_G_CEVNP0_CEV4NP_Pos \ - (16UL) /*!< VADC_G CEVNP0: CEV4NP (Bit 16) */ -#define VADC_G_CEVNP0_CEV4NP_Msk \ - (0xf0000UL) /*!< VADC_G CEVNP0: CEV4NP (Bitfield-Mask: 0x0f) */ -#define VADC_G_CEVNP0_CEV5NP_Pos \ - (20UL) /*!< VADC_G CEVNP0: CEV5NP (Bit 20) */ -#define VADC_G_CEVNP0_CEV5NP_Msk \ - (0xf00000UL) /*!< VADC_G CEVNP0: CEV5NP (Bitfield-Mask: 0x0f) */ -#define VADC_G_CEVNP0_CEV6NP_Pos \ - (24UL) /*!< VADC_G CEVNP0: CEV6NP (Bit 24) */ -#define VADC_G_CEVNP0_CEV6NP_Msk \ - (0xf000000UL) /*!< VADC_G CEVNP0: CEV6NP (Bitfield-Mask: 0x0f) */ -#define VADC_G_CEVNP0_CEV7NP_Pos \ - (28UL) /*!< VADC_G CEVNP0: CEV7NP (Bit 28) */ -#define VADC_G_CEVNP0_CEV7NP_Msk \ - (0xf0000000UL) /*!< VADC_G CEVNP0: CEV7NP (Bitfield-Mask: 0x0f) */ - -/* -------------------------------- VADC_G_REVNP0 ------------------------------- */ -#define VADC_G_REVNP0_REV0NP_Pos \ - (0UL) /*!< VADC_G REVNP0: REV0NP (Bit 0) */ -#define VADC_G_REVNP0_REV0NP_Msk \ - (0xfUL) /*!< VADC_G REVNP0: REV0NP (Bitfield-Mask: 0x0f) */ -#define VADC_G_REVNP0_REV1NP_Pos \ - (4UL) /*!< VADC_G REVNP0: REV1NP (Bit 4) */ -#define VADC_G_REVNP0_REV1NP_Msk \ - (0xf0UL) /*!< VADC_G REVNP0: REV1NP (Bitfield-Mask: 0x0f) */ -#define VADC_G_REVNP0_REV2NP_Pos \ - (8UL) /*!< VADC_G REVNP0: REV2NP (Bit 8) */ -#define VADC_G_REVNP0_REV2NP_Msk \ - (0xf00UL) /*!< VADC_G REVNP0: REV2NP (Bitfield-Mask: 0x0f) */ -#define VADC_G_REVNP0_REV3NP_Pos \ - (12UL) /*!< VADC_G REVNP0: REV3NP (Bit 12) */ -#define VADC_G_REVNP0_REV3NP_Msk \ - (0xf000UL) /*!< VADC_G REVNP0: REV3NP (Bitfield-Mask: 0x0f) */ -#define VADC_G_REVNP0_REV4NP_Pos \ - (16UL) /*!< VADC_G REVNP0: REV4NP (Bit 16) */ -#define VADC_G_REVNP0_REV4NP_Msk \ - (0xf0000UL) /*!< VADC_G REVNP0: REV4NP (Bitfield-Mask: 0x0f) */ -#define VADC_G_REVNP0_REV5NP_Pos \ - (20UL) /*!< VADC_G REVNP0: REV5NP (Bit 20) */ -#define VADC_G_REVNP0_REV5NP_Msk \ - (0xf00000UL) /*!< VADC_G REVNP0: REV5NP (Bitfield-Mask: 0x0f) */ -#define VADC_G_REVNP0_REV6NP_Pos \ - (24UL) /*!< VADC_G REVNP0: REV6NP (Bit 24) */ -#define VADC_G_REVNP0_REV6NP_Msk \ - (0xf000000UL) /*!< VADC_G REVNP0: REV6NP (Bitfield-Mask: 0x0f) */ -#define VADC_G_REVNP0_REV7NP_Pos \ - (28UL) /*!< VADC_G REVNP0: REV7NP (Bit 28) */ -#define VADC_G_REVNP0_REV7NP_Msk \ - (0xf0000000UL) /*!< VADC_G REVNP0: REV7NP (Bitfield-Mask: 0x0f) */ - -/* -------------------------------- VADC_G_REVNP1 ------------------------------- */ -#define VADC_G_REVNP1_REV8NP_Pos \ - (0UL) /*!< VADC_G REVNP1: REV8NP (Bit 0) */ -#define VADC_G_REVNP1_REV8NP_Msk \ - (0xfUL) /*!< VADC_G REVNP1: REV8NP (Bitfield-Mask: 0x0f) */ -#define VADC_G_REVNP1_REV9NP_Pos \ - (4UL) /*!< VADC_G REVNP1: REV9NP (Bit 4) */ -#define VADC_G_REVNP1_REV9NP_Msk \ - (0xf0UL) /*!< VADC_G REVNP1: REV9NP (Bitfield-Mask: 0x0f) */ -#define VADC_G_REVNP1_REV10NP_Pos \ - (8UL) /*!< VADC_G REVNP1: REV10NP (Bit 8) */ -#define VADC_G_REVNP1_REV10NP_Msk \ - (0xf00UL) /*!< VADC_G REVNP1: REV10NP (Bitfield-Mask: 0x0f) */ -#define VADC_G_REVNP1_REV11NP_Pos \ - (12UL) /*!< VADC_G REVNP1: REV11NP (Bit 12) */ -#define VADC_G_REVNP1_REV11NP_Msk \ - (0xf000UL) /*!< VADC_G REVNP1: REV11NP (Bitfield-Mask: 0x0f) */ -#define VADC_G_REVNP1_REV12NP_Pos \ - (16UL) /*!< VADC_G REVNP1: REV12NP (Bit 16) */ -#define VADC_G_REVNP1_REV12NP_Msk \ - (0xf0000UL) /*!< VADC_G REVNP1: REV12NP (Bitfield-Mask: 0x0f) */ -#define VADC_G_REVNP1_REV13NP_Pos \ - (20UL) /*!< VADC_G REVNP1: REV13NP (Bit 20) */ -#define VADC_G_REVNP1_REV13NP_Msk \ - (0xf00000UL) /*!< VADC_G REVNP1: REV13NP (Bitfield-Mask: 0x0f) */ -#define VADC_G_REVNP1_REV14NP_Pos \ - (24UL) /*!< VADC_G REVNP1: REV14NP (Bit 24) */ -#define VADC_G_REVNP1_REV14NP_Msk \ - (0xf000000UL) /*!< VADC_G REVNP1: REV14NP (Bitfield-Mask: 0x0f) */ -#define VADC_G_REVNP1_REV15NP_Pos \ - (28UL) /*!< VADC_G REVNP1: REV15NP (Bit 28) */ -#define VADC_G_REVNP1_REV15NP_Msk \ - (0xf0000000UL) /*!< VADC_G REVNP1: REV15NP (Bitfield-Mask: 0x0f) */ - -/* -------------------------------- VADC_G_SEVNP -------------------------------- */ -#define VADC_G_SEVNP_SEV0NP_Pos \ - (0UL) /*!< VADC_G SEVNP: SEV0NP (Bit 0) */ -#define VADC_G_SEVNP_SEV0NP_Msk \ - (0xfUL) /*!< VADC_G SEVNP: SEV0NP (Bitfield-Mask: 0x0f) */ -#define VADC_G_SEVNP_SEV1NP_Pos \ - (4UL) /*!< VADC_G SEVNP: SEV1NP (Bit 4) */ -#define VADC_G_SEVNP_SEV1NP_Msk \ - (0xf0UL) /*!< VADC_G SEVNP: SEV1NP (Bitfield-Mask: 0x0f) */ - -/* -------------------------------- VADC_G_SRACT -------------------------------- */ -#define VADC_G_SRACT_AGSR0_Pos \ - (0UL) /*!< VADC_G SRACT: AGSR0 (Bit 0) */ -#define VADC_G_SRACT_AGSR0_Msk \ - (0x1UL) /*!< VADC_G SRACT: AGSR0 (Bitfield-Mask: 0x01) */ -#define VADC_G_SRACT_AGSR1_Pos \ - (1UL) /*!< VADC_G SRACT: AGSR1 (Bit 1) */ -#define VADC_G_SRACT_AGSR1_Msk \ - (0x2UL) /*!< VADC_G SRACT: AGSR1 (Bitfield-Mask: 0x01) */ -#define VADC_G_SRACT_AGSR2_Pos \ - (2UL) /*!< VADC_G SRACT: AGSR2 (Bit 2) */ -#define VADC_G_SRACT_AGSR2_Msk \ - (0x4UL) /*!< VADC_G SRACT: AGSR2 (Bitfield-Mask: 0x01) */ -#define VADC_G_SRACT_AGSR3_Pos \ - (3UL) /*!< VADC_G SRACT: AGSR3 (Bit 3) */ -#define VADC_G_SRACT_AGSR3_Msk \ - (0x8UL) /*!< VADC_G SRACT: AGSR3 (Bitfield-Mask: 0x01) */ -#define VADC_G_SRACT_ASSR0_Pos \ - (8UL) /*!< VADC_G SRACT: ASSR0 (Bit 8) */ -#define VADC_G_SRACT_ASSR0_Msk \ - (0x100UL) /*!< VADC_G SRACT: ASSR0 (Bitfield-Mask: 0x01) */ -#define VADC_G_SRACT_ASSR1_Pos \ - (9UL) /*!< VADC_G SRACT: ASSR1 (Bit 9) */ -#define VADC_G_SRACT_ASSR1_Msk \ - (0x200UL) /*!< VADC_G SRACT: ASSR1 (Bitfield-Mask: 0x01) */ -#define VADC_G_SRACT_ASSR2_Pos \ - (10UL) /*!< VADC_G SRACT: ASSR2 (Bit 10) */ -#define VADC_G_SRACT_ASSR2_Msk \ - (0x400UL) /*!< VADC_G SRACT: ASSR2 (Bitfield-Mask: 0x01) */ -#define VADC_G_SRACT_ASSR3_Pos \ - (11UL) /*!< VADC_G SRACT: ASSR3 (Bit 11) */ -#define VADC_G_SRACT_ASSR3_Msk \ - (0x800UL) /*!< VADC_G SRACT: ASSR3 (Bitfield-Mask: 0x01) */ - -/* ------------------------------- VADC_G_EMUXCTR ------------------------------- */ -#define VADC_G_EMUXCTR_EMUXSET_Pos \ - (0UL) /*!< VADC_G EMUXCTR: EMUXSET (Bit 0) */ -#define VADC_G_EMUXCTR_EMUXSET_Msk \ - (0x7UL) /*!< VADC_G EMUXCTR: EMUXSET (Bitfield-Mask: 0x07) */ -#define VADC_G_EMUXCTR_EMUXACT_Pos \ - (8UL) /*!< VADC_G EMUXCTR: EMUXACT (Bit 8) */ -#define VADC_G_EMUXCTR_EMUXACT_Msk \ - (0x700UL) /*!< VADC_G EMUXCTR: EMUXACT (Bitfield-Mask: 0x07) */ -#define VADC_G_EMUXCTR_EMUXCH_Pos \ - (16UL) /*!< VADC_G EMUXCTR: EMUXCH (Bit 16) */ -#define VADC_G_EMUXCTR_EMUXCH_Msk \ - (0x3ff0000UL) /*!< VADC_G EMUXCTR: EMUXCH (Bitfield-Mask: 0x3ff) */ -#define VADC_G_EMUXCTR_EMUXMODE_Pos \ - (26UL) /*!< VADC_G EMUXCTR: EMUXMODE (Bit 26) */ -#define VADC_G_EMUXCTR_EMUXMODE_Msk \ - (0xc000000UL) /*!< VADC_G EMUXCTR: EMUXMODE (Bitfield-Mask: 0x03) */ -#define VADC_G_EMUXCTR_EMXCOD_Pos \ - (28UL) /*!< VADC_G EMUXCTR: EMXCOD (Bit 28) */ -#define VADC_G_EMUXCTR_EMXCOD_Msk \ - (0x10000000UL) /*!< VADC_G EMUXCTR: EMXCOD (Bitfield-Mask: 0x01) */ -#define VADC_G_EMUXCTR_EMXST_Pos \ - (29UL) /*!< VADC_G EMUXCTR: EMXST (Bit 29) */ -#define VADC_G_EMUXCTR_EMXST_Msk \ - (0x20000000UL) /*!< VADC_G EMUXCTR: EMXST (Bitfield-Mask: 0x01) */ -#define VADC_G_EMUXCTR_EMXCSS_Pos \ - (30UL) /*!< VADC_G EMUXCTR: EMXCSS (Bit 30) */ -#define VADC_G_EMUXCTR_EMXCSS_Msk \ - (0x40000000UL) /*!< VADC_G EMUXCTR: EMXCSS (Bitfield-Mask: 0x01) */ -#define VADC_G_EMUXCTR_EMXWC_Pos \ - (31UL) /*!< VADC_G EMUXCTR: EMXWC (Bit 31) */ -#define VADC_G_EMUXCTR_EMXWC_Msk \ - (0x80000000UL) /*!< VADC_G EMUXCTR: EMXWC (Bitfield-Mask: 0x01) */ - -/* --------------------------------- VADC_G_VFR --------------------------------- */ -#define VADC_G_VFR_VF0_Pos (0UL) /*!< VADC_G VFR: VF0 (Bit 0) */ -#define VADC_G_VFR_VF0_Msk \ - (0x1UL) /*!< VADC_G VFR: VF0 (Bitfield-Mask: 0x01) */ -#define VADC_G_VFR_VF1_Pos (1UL) /*!< VADC_G VFR: VF1 (Bit 1) */ -#define VADC_G_VFR_VF1_Msk \ - (0x2UL) /*!< VADC_G VFR: VF1 (Bitfield-Mask: 0x01) */ -#define VADC_G_VFR_VF2_Pos (2UL) /*!< VADC_G VFR: VF2 (Bit 2) */ -#define VADC_G_VFR_VF2_Msk \ - (0x4UL) /*!< VADC_G VFR: VF2 (Bitfield-Mask: 0x01) */ -#define VADC_G_VFR_VF3_Pos (3UL) /*!< VADC_G VFR: VF3 (Bit 3) */ -#define VADC_G_VFR_VF3_Msk \ - (0x8UL) /*!< VADC_G VFR: VF3 (Bitfield-Mask: 0x01) */ -#define VADC_G_VFR_VF4_Pos (4UL) /*!< VADC_G VFR: VF4 (Bit 4) */ -#define VADC_G_VFR_VF4_Msk \ - (0x10UL) /*!< VADC_G VFR: VF4 (Bitfield-Mask: 0x01) */ -#define VADC_G_VFR_VF5_Pos (5UL) /*!< VADC_G VFR: VF5 (Bit 5) */ -#define VADC_G_VFR_VF5_Msk \ - (0x20UL) /*!< VADC_G VFR: VF5 (Bitfield-Mask: 0x01) */ -#define VADC_G_VFR_VF6_Pos (6UL) /*!< VADC_G VFR: VF6 (Bit 6) */ -#define VADC_G_VFR_VF6_Msk \ - (0x40UL) /*!< VADC_G VFR: VF6 (Bitfield-Mask: 0x01) */ -#define VADC_G_VFR_VF7_Pos (7UL) /*!< VADC_G VFR: VF7 (Bit 7) */ -#define VADC_G_VFR_VF7_Msk \ - (0x80UL) /*!< VADC_G VFR: VF7 (Bitfield-Mask: 0x01) */ -#define VADC_G_VFR_VF8_Pos (8UL) /*!< VADC_G VFR: VF8 (Bit 8) */ -#define VADC_G_VFR_VF8_Msk \ - (0x100UL) /*!< VADC_G VFR: VF8 (Bitfield-Mask: 0x01) */ -#define VADC_G_VFR_VF9_Pos (9UL) /*!< VADC_G VFR: VF9 (Bit 9) */ -#define VADC_G_VFR_VF9_Msk \ - (0x200UL) /*!< VADC_G VFR: VF9 (Bitfield-Mask: 0x01) */ -#define VADC_G_VFR_VF10_Pos \ - (10UL) /*!< VADC_G VFR: VF10 (Bit 10) */ -#define VADC_G_VFR_VF10_Msk \ - (0x400UL) /*!< VADC_G VFR: VF10 (Bitfield-Mask: 0x01) */ -#define VADC_G_VFR_VF11_Pos \ - (11UL) /*!< VADC_G VFR: VF11 (Bit 11) */ -#define VADC_G_VFR_VF11_Msk \ - (0x800UL) /*!< VADC_G VFR: VF11 (Bitfield-Mask: 0x01) */ -#define VADC_G_VFR_VF12_Pos \ - (12UL) /*!< VADC_G VFR: VF12 (Bit 12) */ -#define VADC_G_VFR_VF12_Msk \ - (0x1000UL) /*!< VADC_G VFR: VF12 (Bitfield-Mask: 0x01) */ -#define VADC_G_VFR_VF13_Pos \ - (13UL) /*!< VADC_G VFR: VF13 (Bit 13) */ -#define VADC_G_VFR_VF13_Msk \ - (0x2000UL) /*!< VADC_G VFR: VF13 (Bitfield-Mask: 0x01) */ -#define VADC_G_VFR_VF14_Pos \ - (14UL) /*!< VADC_G VFR: VF14 (Bit 14) */ -#define VADC_G_VFR_VF14_Msk \ - (0x4000UL) /*!< VADC_G VFR: VF14 (Bitfield-Mask: 0x01) */ -#define VADC_G_VFR_VF15_Pos \ - (15UL) /*!< VADC_G VFR: VF15 (Bit 15) */ -#define VADC_G_VFR_VF15_Msk \ - (0x8000UL) /*!< VADC_G VFR: VF15 (Bitfield-Mask: 0x01) */ - -/* -------------------------------- VADC_G_CHCTR -------------------------------- */ -#define VADC_G_CHCTR_ICLSEL_Pos \ - (0UL) /*!< VADC_G CHCTR: ICLSEL (Bit 0) */ -#define VADC_G_CHCTR_ICLSEL_Msk \ - (0x3UL) /*!< VADC_G CHCTR: ICLSEL (Bitfield-Mask: 0x03) */ -#define VADC_G_CHCTR_BNDSELL_Pos \ - (4UL) /*!< VADC_G CHCTR: BNDSELL (Bit 4) */ -#define VADC_G_CHCTR_BNDSELL_Msk \ - (0x30UL) /*!< VADC_G CHCTR: BNDSELL (Bitfield-Mask: 0x03) */ -#define VADC_G_CHCTR_BNDSELU_Pos \ - (6UL) /*!< VADC_G CHCTR: BNDSELU (Bit 6) */ -#define VADC_G_CHCTR_BNDSELU_Msk \ - (0xc0UL) /*!< VADC_G CHCTR: BNDSELU (Bitfield-Mask: 0x03) */ -#define VADC_G_CHCTR_CHEVMODE_Pos \ - (8UL) /*!< VADC_G CHCTR: CHEVMODE (Bit 8) */ -#define VADC_G_CHCTR_CHEVMODE_Msk \ - (0x300UL) /*!< VADC_G CHCTR: CHEVMODE (Bitfield-Mask: 0x03) */ -#define VADC_G_CHCTR_SYNC_Pos \ - (10UL) /*!< VADC_G CHCTR: SYNC (Bit 10) */ -#define VADC_G_CHCTR_SYNC_Msk \ - (0x400UL) /*!< VADC_G CHCTR: SYNC (Bitfield-Mask: 0x01) */ -#define VADC_G_CHCTR_REFSEL_Pos \ - (11UL) /*!< VADC_G CHCTR: REFSEL (Bit 11) */ -#define VADC_G_CHCTR_REFSEL_Msk \ - (0x800UL) /*!< VADC_G CHCTR: REFSEL (Bitfield-Mask: 0x01) */ -#define VADC_G_CHCTR_RESREG_Pos \ - (16UL) /*!< VADC_G CHCTR: RESREG (Bit 16) */ -#define VADC_G_CHCTR_RESREG_Msk \ - (0xf0000UL) /*!< VADC_G CHCTR: RESREG (Bitfield-Mask: 0x0f) */ -#define VADC_G_CHCTR_RESTBS_Pos \ - (20UL) /*!< VADC_G CHCTR: RESTBS (Bit 20) */ -#define VADC_G_CHCTR_RESTBS_Msk \ - (0x100000UL) /*!< VADC_G CHCTR: RESTBS (Bitfield-Mask: 0x01) */ -#define VADC_G_CHCTR_RESPOS_Pos \ - (21UL) /*!< VADC_G CHCTR: RESPOS (Bit 21) */ -#define VADC_G_CHCTR_RESPOS_Msk \ - (0x200000UL) /*!< VADC_G CHCTR: RESPOS (Bitfield-Mask: 0x01) */ -#define VADC_G_CHCTR_BWDCH_Pos \ - (28UL) /*!< VADC_G CHCTR: BWDCH (Bit 28) */ -#define VADC_G_CHCTR_BWDCH_Msk \ - (0x30000000UL) /*!< VADC_G CHCTR: BWDCH (Bitfield-Mask: 0x03) */ -#define VADC_G_CHCTR_BWDEN_Pos \ - (30UL) /*!< VADC_G CHCTR: BWDEN (Bit 30) */ -#define VADC_G_CHCTR_BWDEN_Msk \ - (0x40000000UL) /*!< VADC_G CHCTR: BWDEN (Bitfield-Mask: 0x01) */ - -/* --------------------------------- VADC_G_RCR --------------------------------- */ -#define VADC_G_RCR_DRCTR_Pos \ - (16UL) /*!< VADC_G RCR: DRCTR (Bit 16) */ -#define VADC_G_RCR_DRCTR_Msk \ - (0xf0000UL) /*!< VADC_G RCR: DRCTR (Bitfield-Mask: 0x0f) */ -#define VADC_G_RCR_DMM_Pos \ - (20UL) /*!< VADC_G RCR: DMM (Bit 20) */ -#define VADC_G_RCR_DMM_Msk \ - (0x300000UL) /*!< VADC_G RCR: DMM (Bitfield-Mask: 0x03) */ -#define VADC_G_RCR_WFR_Pos \ - (24UL) /*!< VADC_G RCR: WFR (Bit 24) */ -#define VADC_G_RCR_WFR_Msk \ - (0x1000000UL) /*!< VADC_G RCR: WFR (Bitfield-Mask: 0x01) */ -#define VADC_G_RCR_FEN_Pos \ - (25UL) /*!< VADC_G RCR: FEN (Bit 25) */ -#define VADC_G_RCR_FEN_Msk \ - (0x6000000UL) /*!< VADC_G RCR: FEN (Bitfield-Mask: 0x03) */ -#define VADC_G_RCR_SRGEN_Pos \ - (31UL) /*!< VADC_G RCR: SRGEN (Bit 31) */ -#define VADC_G_RCR_SRGEN_Msk \ - (0x80000000UL) /*!< VADC_G RCR: SRGEN (Bitfield-Mask: 0x01) */ - -/* --------------------------------- VADC_G_RES --------------------------------- */ -#define VADC_G_RES_RESULT_Pos \ - (0UL) /*!< VADC_G RES: RESULT (Bit 0) */ -#define VADC_G_RES_RESULT_Msk \ - (0xffffUL) /*!< VADC_G RES: RESULT (Bitfield-Mask: 0xffff) */ -#define VADC_G_RES_DRC_Pos \ - (16UL) /*!< VADC_G RES: DRC (Bit 16) */ -#define VADC_G_RES_DRC_Msk \ - (0xf0000UL) /*!< VADC_G RES: DRC (Bitfield-Mask: 0x0f) */ -#define VADC_G_RES_CHNR_Pos \ - (20UL) /*!< VADC_G RES: CHNR (Bit 20) */ -#define VADC_G_RES_CHNR_Msk \ - (0x1f00000UL) /*!< VADC_G RES: CHNR (Bitfield-Mask: 0x1f) */ -#define VADC_G_RES_EMUX_Pos \ - (25UL) /*!< VADC_G RES: EMUX (Bit 25) */ -#define VADC_G_RES_EMUX_Msk \ - (0xe000000UL) /*!< VADC_G RES: EMUX (Bitfield-Mask: 0x07) */ -#define VADC_G_RES_CRS_Pos \ - (28UL) /*!< VADC_G RES: CRS (Bit 28) */ -#define VADC_G_RES_CRS_Msk \ - (0x30000000UL) /*!< VADC_G RES: CRS (Bitfield-Mask: 0x03) */ -#define VADC_G_RES_FCR_Pos \ - (30UL) /*!< VADC_G RES: FCR (Bit 30) */ -#define VADC_G_RES_FCR_Msk \ - (0x40000000UL) /*!< VADC_G RES: FCR (Bitfield-Mask: 0x01) */ -#define VADC_G_RES_VF_Pos (31UL) /*!< VADC_G RES: VF (Bit 31) */ -#define VADC_G_RES_VF_Msk \ - (0x80000000UL) /*!< VADC_G RES: VF (Bitfield-Mask: 0x01) */ - -/* --------------------------------- VADC_G_RESD -------------------------------- */ -#define VADC_G_RESD_RESULT_Pos \ - (0UL) /*!< VADC_G RESD: RESULT (Bit 0) */ -#define VADC_G_RESD_RESULT_Msk \ - (0xffffUL) /*!< VADC_G RESD: RESULT (Bitfield-Mask: 0xffff) */ -#define VADC_G_RESD_DRC_Pos \ - (16UL) /*!< VADC_G RESD: DRC (Bit 16) */ -#define VADC_G_RESD_DRC_Msk \ - (0xf0000UL) /*!< VADC_G RESD: DRC (Bitfield-Mask: 0x0f) */ -#define VADC_G_RESD_CHNR_Pos \ - (20UL) /*!< VADC_G RESD: CHNR (Bit 20) */ -#define VADC_G_RESD_CHNR_Msk \ - (0x1f00000UL) /*!< VADC_G RESD: CHNR (Bitfield-Mask: 0x1f) */ -#define VADC_G_RESD_EMUX_Pos \ - (25UL) /*!< VADC_G RESD: EMUX (Bit 25) */ -#define VADC_G_RESD_EMUX_Msk \ - (0xe000000UL) /*!< VADC_G RESD: EMUX (Bitfield-Mask: 0x07) */ -#define VADC_G_RESD_CRS_Pos \ - (28UL) /*!< VADC_G RESD: CRS (Bit 28) */ -#define VADC_G_RESD_CRS_Msk \ - (0x30000000UL) /*!< VADC_G RESD: CRS (Bitfield-Mask: 0x03) */ -#define VADC_G_RESD_FCR_Pos \ - (30UL) /*!< VADC_G RESD: FCR (Bit 30) */ -#define VADC_G_RESD_FCR_Msk \ - (0x40000000UL) /*!< VADC_G RESD: FCR (Bitfield-Mask: 0x01) */ -#define VADC_G_RESD_VF_Pos \ - (31UL) /*!< VADC_G RESD: VF (Bit 31) */ -#define VADC_G_RESD_VF_Msk \ - (0x80000000UL) /*!< VADC_G RESD: VF (Bitfield-Mask: 0x01) */ - -/* ================================================================================ */ -/* ================ struct 'DAC' Position & Mask ================ */ -/* ================================================================================ */ - -/* ----------------------------------- DAC_ID ----------------------------------- */ -#define DAC_ID_MODR_Pos (0UL) /*!< DAC ID: MODR (Bit 0) */ -#define DAC_ID_MODR_Msk (0xffUL) /*!< DAC ID: MODR (Bitfield-Mask: 0xff) */ -#define DAC_ID_MODT_Pos (8UL) /*!< DAC ID: MODT (Bit 8) */ -#define DAC_ID_MODT_Msk \ - (0xff00UL) /*!< DAC ID: MODT (Bitfield-Mask: 0xff) */ -#define DAC_ID_MODN_Pos (16UL) /*!< DAC ID: MODN (Bit 16) */ -#define DAC_ID_MODN_Msk \ - (0xffff0000UL) /*!< DAC ID: MODN (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- DAC_DAC0CFG0 -------------------------------- */ -#define DAC_DAC0CFG0_FREQ_Pos \ - (0UL) /*!< DAC DAC0CFG0: FREQ (Bit 0) */ -#define DAC_DAC0CFG0_FREQ_Msk \ - (0xfffffUL) /*!< DAC DAC0CFG0: FREQ (Bitfield-Mask: 0xfffff) */ -#define DAC_DAC0CFG0_MODE_Pos \ - (20UL) /*!< DAC DAC0CFG0: MODE (Bit 20) */ -#define DAC_DAC0CFG0_MODE_Msk \ - (0x700000UL) /*!< DAC DAC0CFG0: MODE (Bitfield-Mask: 0x07) */ -#define DAC_DAC0CFG0_SIGN_Pos \ - (23UL) /*!< DAC DAC0CFG0: SIGN (Bit 23) */ -#define DAC_DAC0CFG0_SIGN_Msk \ - (0x800000UL) /*!< DAC DAC0CFG0: SIGN (Bitfield-Mask: 0x01) */ -#define DAC_DAC0CFG0_FIFOIND_Pos \ - (24UL) /*!< DAC DAC0CFG0: FIFOIND (Bit 24) */ -#define DAC_DAC0CFG0_FIFOIND_Msk \ - (0x3000000UL) /*!< DAC DAC0CFG0: FIFOIND (Bitfield-Mask: 0x03) */ -#define DAC_DAC0CFG0_FIFOEMP_Pos \ - (26UL) /*!< DAC DAC0CFG0: FIFOEMP (Bit 26) */ -#define DAC_DAC0CFG0_FIFOEMP_Msk \ - (0x4000000UL) /*!< DAC DAC0CFG0: FIFOEMP (Bitfield-Mask: 0x01) */ -#define DAC_DAC0CFG0_FIFOFUL_Pos \ - (27UL) /*!< DAC DAC0CFG0: FIFOFUL (Bit 27) */ -#define DAC_DAC0CFG0_FIFOFUL_Msk \ - (0x8000000UL) /*!< DAC DAC0CFG0: FIFOFUL (Bitfield-Mask: 0x01) */ -#define DAC_DAC0CFG0_NEGATE_Pos \ - (28UL) /*!< DAC DAC0CFG0: NEGATE (Bit 28) */ -#define DAC_DAC0CFG0_NEGATE_Msk \ - (0x10000000UL) /*!< DAC DAC0CFG0: NEGATE (Bitfield-Mask: 0x01) */ -#define DAC_DAC0CFG0_SIGNEN_Pos \ - (29UL) /*!< DAC DAC0CFG0: SIGNEN (Bit 29) */ -#define DAC_DAC0CFG0_SIGNEN_Msk \ - (0x20000000UL) /*!< DAC DAC0CFG0: SIGNEN (Bitfield-Mask: 0x01) */ -#define DAC_DAC0CFG0_SREN_Pos \ - (30UL) /*!< DAC DAC0CFG0: SREN (Bit 30) */ -#define DAC_DAC0CFG0_SREN_Msk \ - (0x40000000UL) /*!< DAC DAC0CFG0: SREN (Bitfield-Mask: 0x01) */ -#define DAC_DAC0CFG0_RUN_Pos \ - (31UL) /*!< DAC DAC0CFG0: RUN (Bit 31) */ -#define DAC_DAC0CFG0_RUN_Msk \ - (0x80000000UL) /*!< DAC DAC0CFG0: RUN (Bitfield-Mask: 0x01) */ - -/* -------------------------------- DAC_DAC0CFG1 -------------------------------- */ -#define DAC_DAC0CFG1_SCALE_Pos \ - (0UL) /*!< DAC DAC0CFG1: SCALE (Bit 0) */ -#define DAC_DAC0CFG1_SCALE_Msk \ - (0x7UL) /*!< DAC DAC0CFG1: SCALE (Bitfield-Mask: 0x07) */ -#define DAC_DAC0CFG1_MULDIV_Pos \ - (3UL) /*!< DAC DAC0CFG1: MULDIV (Bit 3) */ -#define DAC_DAC0CFG1_MULDIV_Msk \ - (0x8UL) /*!< DAC DAC0CFG1: MULDIV (Bitfield-Mask: 0x01) */ -#define DAC_DAC0CFG1_OFFS_Pos \ - (4UL) /*!< DAC DAC0CFG1: OFFS (Bit 4) */ -#define DAC_DAC0CFG1_OFFS_Msk \ - (0xff0UL) /*!< DAC DAC0CFG1: OFFS (Bitfield-Mask: 0xff) */ -#define DAC_DAC0CFG1_TRIGSEL_Pos \ - (12UL) /*!< DAC DAC0CFG1: TRIGSEL (Bit 12) */ -#define DAC_DAC0CFG1_TRIGSEL_Msk \ - (0x7000UL) /*!< DAC DAC0CFG1: TRIGSEL (Bitfield-Mask: 0x07) */ -#define DAC_DAC0CFG1_DATMOD_Pos \ - (15UL) /*!< DAC DAC0CFG1: DATMOD (Bit 15) */ -#define DAC_DAC0CFG1_DATMOD_Msk \ - (0x8000UL) /*!< DAC DAC0CFG1: DATMOD (Bitfield-Mask: 0x01) */ -#define DAC_DAC0CFG1_SWTRIG_Pos \ - (16UL) /*!< DAC DAC0CFG1: SWTRIG (Bit 16) */ -#define DAC_DAC0CFG1_SWTRIG_Msk \ - (0x10000UL) /*!< DAC DAC0CFG1: SWTRIG (Bitfield-Mask: 0x01) */ -#define DAC_DAC0CFG1_TRIGMOD_Pos \ - (17UL) /*!< DAC DAC0CFG1: TRIGMOD (Bit 17) */ -#define DAC_DAC0CFG1_TRIGMOD_Msk \ - (0x60000UL) /*!< DAC DAC0CFG1: TRIGMOD (Bitfield-Mask: 0x03) */ -#define DAC_DAC0CFG1_ANACFG_Pos \ - (19UL) /*!< DAC DAC0CFG1: ANACFG (Bit 19) */ -#define DAC_DAC0CFG1_ANACFG_Msk \ - (0xf80000UL) /*!< DAC DAC0CFG1: ANACFG (Bitfield-Mask: 0x1f) */ -#define DAC_DAC0CFG1_ANAEN_Pos \ - (24UL) /*!< DAC DAC0CFG1: ANAEN (Bit 24) */ -#define DAC_DAC0CFG1_ANAEN_Msk \ - (0x1000000UL) /*!< DAC DAC0CFG1: ANAEN (Bitfield-Mask: 0x01) */ -#define DAC_DAC0CFG1_REFCFGL_Pos \ - (28UL) /*!< DAC DAC0CFG1: REFCFGL (Bit 28) */ -#define DAC_DAC0CFG1_REFCFGL_Msk \ - (0xf0000000UL) /*!< DAC DAC0CFG1: REFCFGL (Bitfield-Mask: 0x0f) */ - -/* -------------------------------- DAC_DAC1CFG0 -------------------------------- */ -#define DAC_DAC1CFG0_FREQ_Pos \ - (0UL) /*!< DAC DAC1CFG0: FREQ (Bit 0) */ -#define DAC_DAC1CFG0_FREQ_Msk \ - (0xfffffUL) /*!< DAC DAC1CFG0: FREQ (Bitfield-Mask: 0xfffff) */ -#define DAC_DAC1CFG0_MODE_Pos \ - (20UL) /*!< DAC DAC1CFG0: MODE (Bit 20) */ -#define DAC_DAC1CFG0_MODE_Msk \ - (0x700000UL) /*!< DAC DAC1CFG0: MODE (Bitfield-Mask: 0x07) */ -#define DAC_DAC1CFG0_SIGN_Pos \ - (23UL) /*!< DAC DAC1CFG0: SIGN (Bit 23) */ -#define DAC_DAC1CFG0_SIGN_Msk \ - (0x800000UL) /*!< DAC DAC1CFG0: SIGN (Bitfield-Mask: 0x01) */ -#define DAC_DAC1CFG0_FIFOIND_Pos \ - (24UL) /*!< DAC DAC1CFG0: FIFOIND (Bit 24) */ -#define DAC_DAC1CFG0_FIFOIND_Msk \ - (0x3000000UL) /*!< DAC DAC1CFG0: FIFOIND (Bitfield-Mask: 0x03) */ -#define DAC_DAC1CFG0_FIFOEMP_Pos \ - (26UL) /*!< DAC DAC1CFG0: FIFOEMP (Bit 26) */ -#define DAC_DAC1CFG0_FIFOEMP_Msk \ - (0x4000000UL) /*!< DAC DAC1CFG0: FIFOEMP (Bitfield-Mask: 0x01) */ -#define DAC_DAC1CFG0_FIFOFUL_Pos \ - (27UL) /*!< DAC DAC1CFG0: FIFOFUL (Bit 27) */ -#define DAC_DAC1CFG0_FIFOFUL_Msk \ - (0x8000000UL) /*!< DAC DAC1CFG0: FIFOFUL (Bitfield-Mask: 0x01) */ -#define DAC_DAC1CFG0_NEGATE_Pos \ - (28UL) /*!< DAC DAC1CFG0: NEGATE (Bit 28) */ -#define DAC_DAC1CFG0_NEGATE_Msk \ - (0x10000000UL) /*!< DAC DAC1CFG0: NEGATE (Bitfield-Mask: 0x01) */ -#define DAC_DAC1CFG0_SIGNEN_Pos \ - (29UL) /*!< DAC DAC1CFG0: SIGNEN (Bit 29) */ -#define DAC_DAC1CFG0_SIGNEN_Msk \ - (0x20000000UL) /*!< DAC DAC1CFG0: SIGNEN (Bitfield-Mask: 0x01) */ -#define DAC_DAC1CFG0_SREN_Pos \ - (30UL) /*!< DAC DAC1CFG0: SREN (Bit 30) */ -#define DAC_DAC1CFG0_SREN_Msk \ - (0x40000000UL) /*!< DAC DAC1CFG0: SREN (Bitfield-Mask: 0x01) */ -#define DAC_DAC1CFG0_RUN_Pos \ - (31UL) /*!< DAC DAC1CFG0: RUN (Bit 31) */ -#define DAC_DAC1CFG0_RUN_Msk \ - (0x80000000UL) /*!< DAC DAC1CFG0: RUN (Bitfield-Mask: 0x01) */ - -/* -------------------------------- DAC_DAC1CFG1 -------------------------------- */ -#define DAC_DAC1CFG1_SCALE_Pos \ - (0UL) /*!< DAC DAC1CFG1: SCALE (Bit 0) */ -#define DAC_DAC1CFG1_SCALE_Msk \ - (0x7UL) /*!< DAC DAC1CFG1: SCALE (Bitfield-Mask: 0x07) */ -#define DAC_DAC1CFG1_MULDIV_Pos \ - (3UL) /*!< DAC DAC1CFG1: MULDIV (Bit 3) */ -#define DAC_DAC1CFG1_MULDIV_Msk \ - (0x8UL) /*!< DAC DAC1CFG1: MULDIV (Bitfield-Mask: 0x01) */ -#define DAC_DAC1CFG1_OFFS_Pos \ - (4UL) /*!< DAC DAC1CFG1: OFFS (Bit 4) */ -#define DAC_DAC1CFG1_OFFS_Msk \ - (0xff0UL) /*!< DAC DAC1CFG1: OFFS (Bitfield-Mask: 0xff) */ -#define DAC_DAC1CFG1_TRIGSEL_Pos \ - (12UL) /*!< DAC DAC1CFG1: TRIGSEL (Bit 12) */ -#define DAC_DAC1CFG1_TRIGSEL_Msk \ - (0x7000UL) /*!< DAC DAC1CFG1: TRIGSEL (Bitfield-Mask: 0x07) */ -#define DAC_DAC1CFG1_SWTRIG_Pos \ - (16UL) /*!< DAC DAC1CFG1: SWTRIG (Bit 16) */ -#define DAC_DAC1CFG1_SWTRIG_Msk \ - (0x10000UL) /*!< DAC DAC1CFG1: SWTRIG (Bitfield-Mask: 0x01) */ -#define DAC_DAC1CFG1_TRIGMOD_Pos \ - (17UL) /*!< DAC DAC1CFG1: TRIGMOD (Bit 17) */ -#define DAC_DAC1CFG1_TRIGMOD_Msk \ - (0x60000UL) /*!< DAC DAC1CFG1: TRIGMOD (Bitfield-Mask: 0x03) */ -#define DAC_DAC1CFG1_ANACFG_Pos \ - (19UL) /*!< DAC DAC1CFG1: ANACFG (Bit 19) */ -#define DAC_DAC1CFG1_ANACFG_Msk \ - (0xf80000UL) /*!< DAC DAC1CFG1: ANACFG (Bitfield-Mask: 0x1f) */ -#define DAC_DAC1CFG1_ANAEN_Pos \ - (24UL) /*!< DAC DAC1CFG1: ANAEN (Bit 24) */ -#define DAC_DAC1CFG1_ANAEN_Msk \ - (0x1000000UL) /*!< DAC DAC1CFG1: ANAEN (Bitfield-Mask: 0x01) */ -#define DAC_DAC1CFG1_REFCFGH_Pos \ - (28UL) /*!< DAC DAC1CFG1: REFCFGH (Bit 28) */ -#define DAC_DAC1CFG1_REFCFGH_Msk \ - (0xf0000000UL) /*!< DAC DAC1CFG1: REFCFGH (Bitfield-Mask: 0x0f) */ - -/* -------------------------------- DAC_DAC0DATA -------------------------------- */ -#define DAC_DAC0DATA_DATA0_Pos \ - (0UL) /*!< DAC DAC0DATA: DATA0 (Bit 0) */ -#define DAC_DAC0DATA_DATA0_Msk \ - (0xfffUL) /*!< DAC DAC0DATA: DATA0 (Bitfield-Mask: 0xfff) */ - -/* -------------------------------- DAC_DAC1DATA -------------------------------- */ -#define DAC_DAC1DATA_DATA1_Pos \ - (0UL) /*!< DAC DAC1DATA: DATA1 (Bit 0) */ -#define DAC_DAC1DATA_DATA1_Msk \ - (0xfffUL) /*!< DAC DAC1DATA: DATA1 (Bitfield-Mask: 0xfff) */ - -/* -------------------------------- DAC_DAC01DATA ------------------------------- */ -#define DAC_DAC01DATA_DATA0_Pos \ - (0UL) /*!< DAC DAC01DATA: DATA0 (Bit 0) */ -#define DAC_DAC01DATA_DATA0_Msk \ - (0xfffUL) /*!< DAC DAC01DATA: DATA0 (Bitfield-Mask: 0xfff) */ -#define DAC_DAC01DATA_DATA1_Pos \ - (16UL) /*!< DAC DAC01DATA: DATA1 (Bit 16) */ -#define DAC_DAC01DATA_DATA1_Msk \ - (0xfff0000UL) /*!< DAC DAC01DATA: DATA1 (Bitfield-Mask: 0xfff) */ - -/* -------------------------------- DAC_DAC0PATL -------------------------------- */ -#define DAC_DAC0PATL_PAT0_Pos \ - (0UL) /*!< DAC DAC0PATL: PAT0 (Bit 0) */ -#define DAC_DAC0PATL_PAT0_Msk \ - (0x1fUL) /*!< DAC DAC0PATL: PAT0 (Bitfield-Mask: 0x1f) */ -#define DAC_DAC0PATL_PAT1_Pos \ - (5UL) /*!< DAC DAC0PATL: PAT1 (Bit 5) */ -#define DAC_DAC0PATL_PAT1_Msk \ - (0x3e0UL) /*!< DAC DAC0PATL: PAT1 (Bitfield-Mask: 0x1f) */ -#define DAC_DAC0PATL_PAT2_Pos \ - (10UL) /*!< DAC DAC0PATL: PAT2 (Bit 10) */ -#define DAC_DAC0PATL_PAT2_Msk \ - (0x7c00UL) /*!< DAC DAC0PATL: PAT2 (Bitfield-Mask: 0x1f) */ -#define DAC_DAC0PATL_PAT3_Pos \ - (15UL) /*!< DAC DAC0PATL: PAT3 (Bit 15) */ -#define DAC_DAC0PATL_PAT3_Msk \ - (0xf8000UL) /*!< DAC DAC0PATL: PAT3 (Bitfield-Mask: 0x1f) */ -#define DAC_DAC0PATL_PAT4_Pos \ - (20UL) /*!< DAC DAC0PATL: PAT4 (Bit 20) */ -#define DAC_DAC0PATL_PAT4_Msk \ - (0x1f00000UL) /*!< DAC DAC0PATL: PAT4 (Bitfield-Mask: 0x1f) */ -#define DAC_DAC0PATL_PAT5_Pos \ - (25UL) /*!< DAC DAC0PATL: PAT5 (Bit 25) */ -#define DAC_DAC0PATL_PAT5_Msk \ - (0x3e000000UL) /*!< DAC DAC0PATL: PAT5 (Bitfield-Mask: 0x1f) */ - -/* -------------------------------- DAC_DAC0PATH -------------------------------- */ -#define DAC_DAC0PATH_PAT6_Pos \ - (0UL) /*!< DAC DAC0PATH: PAT6 (Bit 0) */ -#define DAC_DAC0PATH_PAT6_Msk \ - (0x1fUL) /*!< DAC DAC0PATH: PAT6 (Bitfield-Mask: 0x1f) */ -#define DAC_DAC0PATH_PAT7_Pos \ - (5UL) /*!< DAC DAC0PATH: PAT7 (Bit 5) */ -#define DAC_DAC0PATH_PAT7_Msk \ - (0x3e0UL) /*!< DAC DAC0PATH: PAT7 (Bitfield-Mask: 0x1f) */ -#define DAC_DAC0PATH_PAT8_Pos \ - (10UL) /*!< DAC DAC0PATH: PAT8 (Bit 10) */ -#define DAC_DAC0PATH_PAT8_Msk \ - (0x7c00UL) /*!< DAC DAC0PATH: PAT8 (Bitfield-Mask: 0x1f) */ - -/* -------------------------------- DAC_DAC1PATL -------------------------------- */ -#define DAC_DAC1PATL_PAT0_Pos \ - (0UL) /*!< DAC DAC1PATL: PAT0 (Bit 0) */ -#define DAC_DAC1PATL_PAT0_Msk \ - (0x1fUL) /*!< DAC DAC1PATL: PAT0 (Bitfield-Mask: 0x1f) */ -#define DAC_DAC1PATL_PAT1_Pos \ - (5UL) /*!< DAC DAC1PATL: PAT1 (Bit 5) */ -#define DAC_DAC1PATL_PAT1_Msk \ - (0x3e0UL) /*!< DAC DAC1PATL: PAT1 (Bitfield-Mask: 0x1f) */ -#define DAC_DAC1PATL_PAT2_Pos \ - (10UL) /*!< DAC DAC1PATL: PAT2 (Bit 10) */ -#define DAC_DAC1PATL_PAT2_Msk \ - (0x7c00UL) /*!< DAC DAC1PATL: PAT2 (Bitfield-Mask: 0x1f) */ -#define DAC_DAC1PATL_PAT3_Pos \ - (15UL) /*!< DAC DAC1PATL: PAT3 (Bit 15) */ -#define DAC_DAC1PATL_PAT3_Msk \ - (0xf8000UL) /*!< DAC DAC1PATL: PAT3 (Bitfield-Mask: 0x1f) */ -#define DAC_DAC1PATL_PAT4_Pos \ - (20UL) /*!< DAC DAC1PATL: PAT4 (Bit 20) */ -#define DAC_DAC1PATL_PAT4_Msk \ - (0x1f00000UL) /*!< DAC DAC1PATL: PAT4 (Bitfield-Mask: 0x1f) */ -#define DAC_DAC1PATL_PAT5_Pos \ - (25UL) /*!< DAC DAC1PATL: PAT5 (Bit 25) */ -#define DAC_DAC1PATL_PAT5_Msk \ - (0x3e000000UL) /*!< DAC DAC1PATL: PAT5 (Bitfield-Mask: 0x1f) */ - -/* -------------------------------- DAC_DAC1PATH -------------------------------- */ -#define DAC_DAC1PATH_PAT6_Pos \ - (0UL) /*!< DAC DAC1PATH: PAT6 (Bit 0) */ -#define DAC_DAC1PATH_PAT6_Msk \ - (0x1fUL) /*!< DAC DAC1PATH: PAT6 (Bitfield-Mask: 0x1f) */ -#define DAC_DAC1PATH_PAT7_Pos \ - (5UL) /*!< DAC DAC1PATH: PAT7 (Bit 5) */ -#define DAC_DAC1PATH_PAT7_Msk \ - (0x3e0UL) /*!< DAC DAC1PATH: PAT7 (Bitfield-Mask: 0x1f) */ -#define DAC_DAC1PATH_PAT8_Pos \ - (10UL) /*!< DAC DAC1PATH: PAT8 (Bit 10) */ -#define DAC_DAC1PATH_PAT8_Msk \ - (0x7c00UL) /*!< DAC DAC1PATH: PAT8 (Bitfield-Mask: 0x1f) */ - -/* ================================================================================ */ -/* ================ Group 'CCU4' Position & Mask ================ */ -/* ================================================================================ */ - -/* --------------------------------- CCU4_GCTRL --------------------------------- */ -#define CCU4_GCTRL_PRBC_Pos \ - (0UL) /*!< CCU4 GCTRL: PRBC (Bit 0) */ -#define CCU4_GCTRL_PRBC_Msk \ - (0x7UL) /*!< CCU4 GCTRL: PRBC (Bitfield-Mask: 0x07) */ -#define CCU4_GCTRL_PCIS_Pos \ - (4UL) /*!< CCU4 GCTRL: PCIS (Bit 4) */ -#define CCU4_GCTRL_PCIS_Msk \ - (0x30UL) /*!< CCU4 GCTRL: PCIS (Bitfield-Mask: 0x03) */ -#define CCU4_GCTRL_SUSCFG_Pos \ - (8UL) /*!< CCU4 GCTRL: SUSCFG (Bit 8) */ -#define CCU4_GCTRL_SUSCFG_Msk \ - (0x300UL) /*!< CCU4 GCTRL: SUSCFG (Bitfield-Mask: 0x03) */ -#define CCU4_GCTRL_MSE0_Pos \ - (10UL) /*!< CCU4 GCTRL: MSE0 (Bit 10) */ -#define CCU4_GCTRL_MSE0_Msk \ - (0x400UL) /*!< CCU4 GCTRL: MSE0 (Bitfield-Mask: 0x01) */ -#define CCU4_GCTRL_MSE1_Pos \ - (11UL) /*!< CCU4 GCTRL: MSE1 (Bit 11) */ -#define CCU4_GCTRL_MSE1_Msk \ - (0x800UL) /*!< CCU4 GCTRL: MSE1 (Bitfield-Mask: 0x01) */ -#define CCU4_GCTRL_MSE2_Pos \ - (12UL) /*!< CCU4 GCTRL: MSE2 (Bit 12) */ -#define CCU4_GCTRL_MSE2_Msk \ - (0x1000UL) /*!< CCU4 GCTRL: MSE2 (Bitfield-Mask: 0x01) */ -#define CCU4_GCTRL_MSE3_Pos \ - (13UL) /*!< CCU4 GCTRL: MSE3 (Bit 13) */ -#define CCU4_GCTRL_MSE3_Msk \ - (0x2000UL) /*!< CCU4 GCTRL: MSE3 (Bitfield-Mask: 0x01) */ -#define CCU4_GCTRL_MSDE_Pos \ - (14UL) /*!< CCU4 GCTRL: MSDE (Bit 14) */ -#define CCU4_GCTRL_MSDE_Msk \ - (0xc000UL) /*!< CCU4 GCTRL: MSDE (Bitfield-Mask: 0x03) */ - -/* --------------------------------- CCU4_GSTAT --------------------------------- */ -#define CCU4_GSTAT_S0I_Pos (0UL) /*!< CCU4 GSTAT: S0I (Bit 0) */ -#define CCU4_GSTAT_S0I_Msk \ - (0x1UL) /*!< CCU4 GSTAT: S0I (Bitfield-Mask: 0x01) */ -#define CCU4_GSTAT_S1I_Pos (1UL) /*!< CCU4 GSTAT: S1I (Bit 1) */ -#define CCU4_GSTAT_S1I_Msk \ - (0x2UL) /*!< CCU4 GSTAT: S1I (Bitfield-Mask: 0x01) */ -#define CCU4_GSTAT_S2I_Pos (2UL) /*!< CCU4 GSTAT: S2I (Bit 2) */ -#define CCU4_GSTAT_S2I_Msk \ - (0x4UL) /*!< CCU4 GSTAT: S2I (Bitfield-Mask: 0x01) */ -#define CCU4_GSTAT_S3I_Pos (3UL) /*!< CCU4 GSTAT: S3I (Bit 3) */ -#define CCU4_GSTAT_S3I_Msk \ - (0x8UL) /*!< CCU4 GSTAT: S3I (Bitfield-Mask: 0x01) */ -#define CCU4_GSTAT_PRB_Pos (8UL) /*!< CCU4 GSTAT: PRB (Bit 8) */ -#define CCU4_GSTAT_PRB_Msk \ - (0x100UL) /*!< CCU4 GSTAT: PRB (Bitfield-Mask: 0x01) */ - -/* --------------------------------- CCU4_GIDLS --------------------------------- */ -#define CCU4_GIDLS_SS0I_Pos \ - (0UL) /*!< CCU4 GIDLS: SS0I (Bit 0) */ -#define CCU4_GIDLS_SS0I_Msk \ - (0x1UL) /*!< CCU4 GIDLS: SS0I (Bitfield-Mask: 0x01) */ -#define CCU4_GIDLS_SS1I_Pos \ - (1UL) /*!< CCU4 GIDLS: SS1I (Bit 1) */ -#define CCU4_GIDLS_SS1I_Msk \ - (0x2UL) /*!< CCU4 GIDLS: SS1I (Bitfield-Mask: 0x01) */ -#define CCU4_GIDLS_SS2I_Pos \ - (2UL) /*!< CCU4 GIDLS: SS2I (Bit 2) */ -#define CCU4_GIDLS_SS2I_Msk \ - (0x4UL) /*!< CCU4 GIDLS: SS2I (Bitfield-Mask: 0x01) */ -#define CCU4_GIDLS_SS3I_Pos \ - (3UL) /*!< CCU4 GIDLS: SS3I (Bit 3) */ -#define CCU4_GIDLS_SS3I_Msk \ - (0x8UL) /*!< CCU4 GIDLS: SS3I (Bitfield-Mask: 0x01) */ -#define CCU4_GIDLS_CPRB_Pos \ - (8UL) /*!< CCU4 GIDLS: CPRB (Bit 8) */ -#define CCU4_GIDLS_CPRB_Msk \ - (0x100UL) /*!< CCU4 GIDLS: CPRB (Bitfield-Mask: 0x01) */ -#define CCU4_GIDLS_PSIC_Pos \ - (9UL) /*!< CCU4 GIDLS: PSIC (Bit 9) */ -#define CCU4_GIDLS_PSIC_Msk \ - (0x200UL) /*!< CCU4 GIDLS: PSIC (Bitfield-Mask: 0x01) */ - -/* --------------------------------- CCU4_GIDLC --------------------------------- */ -#define CCU4_GIDLC_CS0I_Pos \ - (0UL) /*!< CCU4 GIDLC: CS0I (Bit 0) */ -#define CCU4_GIDLC_CS0I_Msk \ - (0x1UL) /*!< CCU4 GIDLC: CS0I (Bitfield-Mask: 0x01) */ -#define CCU4_GIDLC_CS1I_Pos \ - (1UL) /*!< CCU4 GIDLC: CS1I (Bit 1) */ -#define CCU4_GIDLC_CS1I_Msk \ - (0x2UL) /*!< CCU4 GIDLC: CS1I (Bitfield-Mask: 0x01) */ -#define CCU4_GIDLC_CS2I_Pos \ - (2UL) /*!< CCU4 GIDLC: CS2I (Bit 2) */ -#define CCU4_GIDLC_CS2I_Msk \ - (0x4UL) /*!< CCU4 GIDLC: CS2I (Bitfield-Mask: 0x01) */ -#define CCU4_GIDLC_CS3I_Pos \ - (3UL) /*!< CCU4 GIDLC: CS3I (Bit 3) */ -#define CCU4_GIDLC_CS3I_Msk \ - (0x8UL) /*!< CCU4 GIDLC: CS3I (Bitfield-Mask: 0x01) */ -#define CCU4_GIDLC_SPRB_Pos \ - (8UL) /*!< CCU4 GIDLC: SPRB (Bit 8) */ -#define CCU4_GIDLC_SPRB_Msk \ - (0x100UL) /*!< CCU4 GIDLC: SPRB (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- CCU4_GCSS --------------------------------- */ -#define CCU4_GCSS_S0SE_Pos (0UL) /*!< CCU4 GCSS: S0SE (Bit 0) */ -#define CCU4_GCSS_S0SE_Msk \ - (0x1UL) /*!< CCU4 GCSS: S0SE (Bitfield-Mask: 0x01) */ -#define CCU4_GCSS_S0DSE_Pos \ - (1UL) /*!< CCU4 GCSS: S0DSE (Bit 1) */ -#define CCU4_GCSS_S0DSE_Msk \ - (0x2UL) /*!< CCU4 GCSS: S0DSE (Bitfield-Mask: 0x01) */ -#define CCU4_GCSS_S0PSE_Pos \ - (2UL) /*!< CCU4 GCSS: S0PSE (Bit 2) */ -#define CCU4_GCSS_S0PSE_Msk \ - (0x4UL) /*!< CCU4 GCSS: S0PSE (Bitfield-Mask: 0x01) */ -#define CCU4_GCSS_S1SE_Pos (4UL) /*!< CCU4 GCSS: S1SE (Bit 4) */ -#define CCU4_GCSS_S1SE_Msk \ - (0x10UL) /*!< CCU4 GCSS: S1SE (Bitfield-Mask: 0x01) */ -#define CCU4_GCSS_S1DSE_Pos \ - (5UL) /*!< CCU4 GCSS: S1DSE (Bit 5) */ -#define CCU4_GCSS_S1DSE_Msk \ - (0x20UL) /*!< CCU4 GCSS: S1DSE (Bitfield-Mask: 0x01) */ -#define CCU4_GCSS_S1PSE_Pos \ - (6UL) /*!< CCU4 GCSS: S1PSE (Bit 6) */ -#define CCU4_GCSS_S1PSE_Msk \ - (0x40UL) /*!< CCU4 GCSS: S1PSE (Bitfield-Mask: 0x01) */ -#define CCU4_GCSS_S2SE_Pos (8UL) /*!< CCU4 GCSS: S2SE (Bit 8) */ -#define CCU4_GCSS_S2SE_Msk \ - (0x100UL) /*!< CCU4 GCSS: S2SE (Bitfield-Mask: 0x01) */ -#define CCU4_GCSS_S2DSE_Pos \ - (9UL) /*!< CCU4 GCSS: S2DSE (Bit 9) */ -#define CCU4_GCSS_S2DSE_Msk \ - (0x200UL) /*!< CCU4 GCSS: S2DSE (Bitfield-Mask: 0x01) */ -#define CCU4_GCSS_S2PSE_Pos \ - (10UL) /*!< CCU4 GCSS: S2PSE (Bit 10) */ -#define CCU4_GCSS_S2PSE_Msk \ - (0x400UL) /*!< CCU4 GCSS: S2PSE (Bitfield-Mask: 0x01) */ -#define CCU4_GCSS_S3SE_Pos \ - (12UL) /*!< CCU4 GCSS: S3SE (Bit 12) */ -#define CCU4_GCSS_S3SE_Msk \ - (0x1000UL) /*!< CCU4 GCSS: S3SE (Bitfield-Mask: 0x01) */ -#define CCU4_GCSS_S3DSE_Pos \ - (13UL) /*!< CCU4 GCSS: S3DSE (Bit 13) */ -#define CCU4_GCSS_S3DSE_Msk \ - (0x2000UL) /*!< CCU4 GCSS: S3DSE (Bitfield-Mask: 0x01) */ -#define CCU4_GCSS_S3PSE_Pos \ - (14UL) /*!< CCU4 GCSS: S3PSE (Bit 14) */ -#define CCU4_GCSS_S3PSE_Msk \ - (0x4000UL) /*!< CCU4 GCSS: S3PSE (Bitfield-Mask: 0x01) */ -#define CCU4_GCSS_S0STS_Pos \ - (16UL) /*!< CCU4 GCSS: S0STS (Bit 16) */ -#define CCU4_GCSS_S0STS_Msk \ - (0x10000UL) /*!< CCU4 GCSS: S0STS (Bitfield-Mask: 0x01) */ -#define CCU4_GCSS_S1STS_Pos \ - (17UL) /*!< CCU4 GCSS: S1STS (Bit 17) */ -#define CCU4_GCSS_S1STS_Msk \ - (0x20000UL) /*!< CCU4 GCSS: S1STS (Bitfield-Mask: 0x01) */ -#define CCU4_GCSS_S2STS_Pos \ - (18UL) /*!< CCU4 GCSS: S2STS (Bit 18) */ -#define CCU4_GCSS_S2STS_Msk \ - (0x40000UL) /*!< CCU4 GCSS: S2STS (Bitfield-Mask: 0x01) */ -#define CCU4_GCSS_S3STS_Pos \ - (19UL) /*!< CCU4 GCSS: S3STS (Bit 19) */ -#define CCU4_GCSS_S3STS_Msk \ - (0x80000UL) /*!< CCU4 GCSS: S3STS (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- CCU4_GCSC --------------------------------- */ -#define CCU4_GCSC_S0SC_Pos (0UL) /*!< CCU4 GCSC: S0SC (Bit 0) */ -#define CCU4_GCSC_S0SC_Msk \ - (0x1UL) /*!< CCU4 GCSC: S0SC (Bitfield-Mask: 0x01) */ -#define CCU4_GCSC_S0DSC_Pos \ - (1UL) /*!< CCU4 GCSC: S0DSC (Bit 1) */ -#define CCU4_GCSC_S0DSC_Msk \ - (0x2UL) /*!< CCU4 GCSC: S0DSC (Bitfield-Mask: 0x01) */ -#define CCU4_GCSC_S0PSC_Pos \ - (2UL) /*!< CCU4 GCSC: S0PSC (Bit 2) */ -#define CCU4_GCSC_S0PSC_Msk \ - (0x4UL) /*!< CCU4 GCSC: S0PSC (Bitfield-Mask: 0x01) */ -#define CCU4_GCSC_S1SC_Pos (4UL) /*!< CCU4 GCSC: S1SC (Bit 4) */ -#define CCU4_GCSC_S1SC_Msk \ - (0x10UL) /*!< CCU4 GCSC: S1SC (Bitfield-Mask: 0x01) */ -#define CCU4_GCSC_S1DSC_Pos \ - (5UL) /*!< CCU4 GCSC: S1DSC (Bit 5) */ -#define CCU4_GCSC_S1DSC_Msk \ - (0x20UL) /*!< CCU4 GCSC: S1DSC (Bitfield-Mask: 0x01) */ -#define CCU4_GCSC_S1PSC_Pos \ - (6UL) /*!< CCU4 GCSC: S1PSC (Bit 6) */ -#define CCU4_GCSC_S1PSC_Msk \ - (0x40UL) /*!< CCU4 GCSC: S1PSC (Bitfield-Mask: 0x01) */ -#define CCU4_GCSC_S2SC_Pos (8UL) /*!< CCU4 GCSC: S2SC (Bit 8) */ -#define CCU4_GCSC_S2SC_Msk \ - (0x100UL) /*!< CCU4 GCSC: S2SC (Bitfield-Mask: 0x01) */ -#define CCU4_GCSC_S2DSC_Pos \ - (9UL) /*!< CCU4 GCSC: S2DSC (Bit 9) */ -#define CCU4_GCSC_S2DSC_Msk \ - (0x200UL) /*!< CCU4 GCSC: S2DSC (Bitfield-Mask: 0x01) */ -#define CCU4_GCSC_S2PSC_Pos \ - (10UL) /*!< CCU4 GCSC: S2PSC (Bit 10) */ -#define CCU4_GCSC_S2PSC_Msk \ - (0x400UL) /*!< CCU4 GCSC: S2PSC (Bitfield-Mask: 0x01) */ -#define CCU4_GCSC_S3SC_Pos \ - (12UL) /*!< CCU4 GCSC: S3SC (Bit 12) */ -#define CCU4_GCSC_S3SC_Msk \ - (0x1000UL) /*!< CCU4 GCSC: S3SC (Bitfield-Mask: 0x01) */ -#define CCU4_GCSC_S3DSC_Pos \ - (13UL) /*!< CCU4 GCSC: S3DSC (Bit 13) */ -#define CCU4_GCSC_S3DSC_Msk \ - (0x2000UL) /*!< CCU4 GCSC: S3DSC (Bitfield-Mask: 0x01) */ -#define CCU4_GCSC_S3PSC_Pos \ - (14UL) /*!< CCU4 GCSC: S3PSC (Bit 14) */ -#define CCU4_GCSC_S3PSC_Msk \ - (0x4000UL) /*!< CCU4 GCSC: S3PSC (Bitfield-Mask: 0x01) */ -#define CCU4_GCSC_S0STC_Pos \ - (16UL) /*!< CCU4 GCSC: S0STC (Bit 16) */ -#define CCU4_GCSC_S0STC_Msk \ - (0x10000UL) /*!< CCU4 GCSC: S0STC (Bitfield-Mask: 0x01) */ -#define CCU4_GCSC_S1STC_Pos \ - (17UL) /*!< CCU4 GCSC: S1STC (Bit 17) */ -#define CCU4_GCSC_S1STC_Msk \ - (0x20000UL) /*!< CCU4 GCSC: S1STC (Bitfield-Mask: 0x01) */ -#define CCU4_GCSC_S2STC_Pos \ - (18UL) /*!< CCU4 GCSC: S2STC (Bit 18) */ -#define CCU4_GCSC_S2STC_Msk \ - (0x40000UL) /*!< CCU4 GCSC: S2STC (Bitfield-Mask: 0x01) */ -#define CCU4_GCSC_S3STC_Pos \ - (19UL) /*!< CCU4 GCSC: S3STC (Bit 19) */ -#define CCU4_GCSC_S3STC_Msk \ - (0x80000UL) /*!< CCU4 GCSC: S3STC (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- CCU4_GCST --------------------------------- */ -#define CCU4_GCST_S0SS_Pos (0UL) /*!< CCU4 GCST: S0SS (Bit 0) */ -#define CCU4_GCST_S0SS_Msk \ - (0x1UL) /*!< CCU4 GCST: S0SS (Bitfield-Mask: 0x01) */ -#define CCU4_GCST_S0DSS_Pos \ - (1UL) /*!< CCU4 GCST: S0DSS (Bit 1) */ -#define CCU4_GCST_S0DSS_Msk \ - (0x2UL) /*!< CCU4 GCST: S0DSS (Bitfield-Mask: 0x01) */ -#define CCU4_GCST_S0PSS_Pos \ - (2UL) /*!< CCU4 GCST: S0PSS (Bit 2) */ -#define CCU4_GCST_S0PSS_Msk \ - (0x4UL) /*!< CCU4 GCST: S0PSS (Bitfield-Mask: 0x01) */ -#define CCU4_GCST_S1SS_Pos (4UL) /*!< CCU4 GCST: S1SS (Bit 4) */ -#define CCU4_GCST_S1SS_Msk \ - (0x10UL) /*!< CCU4 GCST: S1SS (Bitfield-Mask: 0x01) */ -#define CCU4_GCST_S1DSS_Pos \ - (5UL) /*!< CCU4 GCST: S1DSS (Bit 5) */ -#define CCU4_GCST_S1DSS_Msk \ - (0x20UL) /*!< CCU4 GCST: S1DSS (Bitfield-Mask: 0x01) */ -#define CCU4_GCST_S1PSS_Pos \ - (6UL) /*!< CCU4 GCST: S1PSS (Bit 6) */ -#define CCU4_GCST_S1PSS_Msk \ - (0x40UL) /*!< CCU4 GCST: S1PSS (Bitfield-Mask: 0x01) */ -#define CCU4_GCST_S2SS_Pos (8UL) /*!< CCU4 GCST: S2SS (Bit 8) */ -#define CCU4_GCST_S2SS_Msk \ - (0x100UL) /*!< CCU4 GCST: S2SS (Bitfield-Mask: 0x01) */ -#define CCU4_GCST_S2DSS_Pos \ - (9UL) /*!< CCU4 GCST: S2DSS (Bit 9) */ -#define CCU4_GCST_S2DSS_Msk \ - (0x200UL) /*!< CCU4 GCST: S2DSS (Bitfield-Mask: 0x01) */ -#define CCU4_GCST_S2PSS_Pos \ - (10UL) /*!< CCU4 GCST: S2PSS (Bit 10) */ -#define CCU4_GCST_S2PSS_Msk \ - (0x400UL) /*!< CCU4 GCST: S2PSS (Bitfield-Mask: 0x01) */ -#define CCU4_GCST_S3SS_Pos \ - (12UL) /*!< CCU4 GCST: S3SS (Bit 12) */ -#define CCU4_GCST_S3SS_Msk \ - (0x1000UL) /*!< CCU4 GCST: S3SS (Bitfield-Mask: 0x01) */ -#define CCU4_GCST_S3DSS_Pos \ - (13UL) /*!< CCU4 GCST: S3DSS (Bit 13) */ -#define CCU4_GCST_S3DSS_Msk \ - (0x2000UL) /*!< CCU4 GCST: S3DSS (Bitfield-Mask: 0x01) */ -#define CCU4_GCST_S3PSS_Pos \ - (14UL) /*!< CCU4 GCST: S3PSS (Bit 14) */ -#define CCU4_GCST_S3PSS_Msk \ - (0x4000UL) /*!< CCU4 GCST: S3PSS (Bitfield-Mask: 0x01) */ -#define CCU4_GCST_CC40ST_Pos \ - (16UL) /*!< CCU4 GCST: CC40ST (Bit 16) */ -#define CCU4_GCST_CC40ST_Msk \ - (0x10000UL) /*!< CCU4 GCST: CC40ST (Bitfield-Mask: 0x01) */ -#define CCU4_GCST_CC41ST_Pos \ - (17UL) /*!< CCU4 GCST: CC41ST (Bit 17) */ -#define CCU4_GCST_CC41ST_Msk \ - (0x20000UL) /*!< CCU4 GCST: CC41ST (Bitfield-Mask: 0x01) */ -#define CCU4_GCST_CC42ST_Pos \ - (18UL) /*!< CCU4 GCST: CC42ST (Bit 18) */ -#define CCU4_GCST_CC42ST_Msk \ - (0x40000UL) /*!< CCU4 GCST: CC42ST (Bitfield-Mask: 0x01) */ -#define CCU4_GCST_CC43ST_Pos \ - (19UL) /*!< CCU4 GCST: CC43ST (Bit 19) */ -#define CCU4_GCST_CC43ST_Msk \ - (0x80000UL) /*!< CCU4 GCST: CC43ST (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- CCU4_ECRD --------------------------------- */ -#define CCU4_ECRD_CAPV_Pos (0UL) /*!< CCU4 ECRD: CAPV (Bit 0) */ -#define CCU4_ECRD_CAPV_Msk \ - (0xffffUL) /*!< CCU4 ECRD: CAPV (Bitfield-Mask: 0xffff) */ -#define CCU4_ECRD_FPCV_Pos \ - (16UL) /*!< CCU4 ECRD: FPCV (Bit 16) */ -#define CCU4_ECRD_FPCV_Msk \ - (0xf0000UL) /*!< CCU4 ECRD: FPCV (Bitfield-Mask: 0x0f) */ -#define CCU4_ECRD_SPTR_Pos \ - (20UL) /*!< CCU4 ECRD: SPTR (Bit 20) */ -#define CCU4_ECRD_SPTR_Msk \ - (0x300000UL) /*!< CCU4 ECRD: SPTR (Bitfield-Mask: 0x03) */ -#define CCU4_ECRD_VPTR_Pos \ - (22UL) /*!< CCU4 ECRD: VPTR (Bit 22) */ -#define CCU4_ECRD_VPTR_Msk \ - (0xc00000UL) /*!< CCU4 ECRD: VPTR (Bitfield-Mask: 0x03) */ -#define CCU4_ECRD_FFL_Pos (24UL) /*!< CCU4 ECRD: FFL (Bit 24) */ -#define CCU4_ECRD_FFL_Msk \ - (0x1000000UL) /*!< CCU4 ECRD: FFL (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- CCU4_MIDR --------------------------------- */ -#define CCU4_MIDR_MODR_Pos (0UL) /*!< CCU4 MIDR: MODR (Bit 0) */ -#define CCU4_MIDR_MODR_Msk \ - (0xffUL) /*!< CCU4 MIDR: MODR (Bitfield-Mask: 0xff) */ -#define CCU4_MIDR_MODT_Pos (8UL) /*!< CCU4 MIDR: MODT (Bit 8) */ -#define CCU4_MIDR_MODT_Msk \ - (0xff00UL) /*!< CCU4 MIDR: MODT (Bitfield-Mask: 0xff) */ -#define CCU4_MIDR_MODN_Pos \ - (16UL) /*!< CCU4 MIDR: MODN (Bit 16) */ -#define CCU4_MIDR_MODN_Msk \ - (0xffff0000UL) /*!< CCU4 MIDR: MODN (Bitfield-Mask: 0xffff) */ - -/* ================================================================================ */ -/* ================ Group 'CCU4_CC4' Position & Mask ================ */ -/* ================================================================================ */ - -/* -------------------------------- CCU4_CC4_INS -------------------------------- */ -#define CCU4_CC4_INS_EV0IS_Pos \ - (0UL) /*!< CCU4_CC4 INS: EV0IS (Bit 0) */ -#define CCU4_CC4_INS_EV0IS_Msk \ - (0xfUL) /*!< CCU4_CC4 INS: EV0IS (Bitfield-Mask: 0x0f) */ -#define CCU4_CC4_INS_EV1IS_Pos \ - (4UL) /*!< CCU4_CC4 INS: EV1IS (Bit 4) */ -#define CCU4_CC4_INS_EV1IS_Msk \ - (0xf0UL) /*!< CCU4_CC4 INS: EV1IS (Bitfield-Mask: 0x0f) */ -#define CCU4_CC4_INS_EV2IS_Pos \ - (8UL) /*!< CCU4_CC4 INS: EV2IS (Bit 8) */ -#define CCU4_CC4_INS_EV2IS_Msk \ - (0xf00UL) /*!< CCU4_CC4 INS: EV2IS (Bitfield-Mask: 0x0f) */ -#define CCU4_CC4_INS_EV0EM_Pos \ - (16UL) /*!< CCU4_CC4 INS: EV0EM (Bit 16) */ -#define CCU4_CC4_INS_EV0EM_Msk \ - (0x30000UL) /*!< CCU4_CC4 INS: EV0EM (Bitfield-Mask: 0x03) */ -#define CCU4_CC4_INS_EV1EM_Pos \ - (18UL) /*!< CCU4_CC4 INS: EV1EM (Bit 18) */ -#define CCU4_CC4_INS_EV1EM_Msk \ - (0xc0000UL) /*!< CCU4_CC4 INS: EV1EM (Bitfield-Mask: 0x03) */ -#define CCU4_CC4_INS_EV2EM_Pos \ - (20UL) /*!< CCU4_CC4 INS: EV2EM (Bit 20) */ -#define CCU4_CC4_INS_EV2EM_Msk \ - (0x300000UL) /*!< CCU4_CC4 INS: EV2EM (Bitfield-Mask: 0x03) */ -#define CCU4_CC4_INS_EV0LM_Pos \ - (22UL) /*!< CCU4_CC4 INS: EV0LM (Bit 22) */ -#define CCU4_CC4_INS_EV0LM_Msk \ - (0x400000UL) /*!< CCU4_CC4 INS: EV0LM (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_INS_EV1LM_Pos \ - (23UL) /*!< CCU4_CC4 INS: EV1LM (Bit 23) */ -#define CCU4_CC4_INS_EV1LM_Msk \ - (0x800000UL) /*!< CCU4_CC4 INS: EV1LM (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_INS_EV2LM_Pos \ - (24UL) /*!< CCU4_CC4 INS: EV2LM (Bit 24) */ -#define CCU4_CC4_INS_EV2LM_Msk \ - (0x1000000UL) /*!< CCU4_CC4 INS: EV2LM (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_INS_LPF0M_Pos \ - (25UL) /*!< CCU4_CC4 INS: LPF0M (Bit 25) */ -#define CCU4_CC4_INS_LPF0M_Msk \ - (0x6000000UL) /*!< CCU4_CC4 INS: LPF0M (Bitfield-Mask: 0x03) */ -#define CCU4_CC4_INS_LPF1M_Pos \ - (27UL) /*!< CCU4_CC4 INS: LPF1M (Bit 27) */ -#define CCU4_CC4_INS_LPF1M_Msk \ - (0x18000000UL) /*!< CCU4_CC4 INS: LPF1M (Bitfield-Mask: 0x03) */ -#define CCU4_CC4_INS_LPF2M_Pos \ - (29UL) /*!< CCU4_CC4 INS: LPF2M (Bit 29) */ -#define CCU4_CC4_INS_LPF2M_Msk \ - (0x60000000UL) /*!< CCU4_CC4 INS: LPF2M (Bitfield-Mask: 0x03) */ - -/* -------------------------------- CCU4_CC4_CMC -------------------------------- */ -#define CCU4_CC4_CMC_STRTS_Pos \ - (0UL) /*!< CCU4_CC4 CMC: STRTS (Bit 0) */ -#define CCU4_CC4_CMC_STRTS_Msk \ - (0x3UL) /*!< CCU4_CC4 CMC: STRTS (Bitfield-Mask: 0x03) */ -#define CCU4_CC4_CMC_ENDS_Pos \ - (2UL) /*!< CCU4_CC4 CMC: ENDS (Bit 2) */ -#define CCU4_CC4_CMC_ENDS_Msk \ - (0xcUL) /*!< CCU4_CC4 CMC: ENDS (Bitfield-Mask: 0x03) */ -#define CCU4_CC4_CMC_CAP0S_Pos \ - (4UL) /*!< CCU4_CC4 CMC: CAP0S (Bit 4) */ -#define CCU4_CC4_CMC_CAP0S_Msk \ - (0x30UL) /*!< CCU4_CC4 CMC: CAP0S (Bitfield-Mask: 0x03) */ -#define CCU4_CC4_CMC_CAP1S_Pos \ - (6UL) /*!< CCU4_CC4 CMC: CAP1S (Bit 6) */ -#define CCU4_CC4_CMC_CAP1S_Msk \ - (0xc0UL) /*!< CCU4_CC4 CMC: CAP1S (Bitfield-Mask: 0x03) */ -#define CCU4_CC4_CMC_GATES_Pos \ - (8UL) /*!< CCU4_CC4 CMC: GATES (Bit 8) */ -#define CCU4_CC4_CMC_GATES_Msk \ - (0x300UL) /*!< CCU4_CC4 CMC: GATES (Bitfield-Mask: 0x03) */ -#define CCU4_CC4_CMC_UDS_Pos \ - (10UL) /*!< CCU4_CC4 CMC: UDS (Bit 10) */ -#define CCU4_CC4_CMC_UDS_Msk \ - (0xc00UL) /*!< CCU4_CC4 CMC: UDS (Bitfield-Mask: 0x03) */ -#define CCU4_CC4_CMC_LDS_Pos \ - (12UL) /*!< CCU4_CC4 CMC: LDS (Bit 12) */ -#define CCU4_CC4_CMC_LDS_Msk \ - (0x3000UL) /*!< CCU4_CC4 CMC: LDS (Bitfield-Mask: 0x03) */ -#define CCU4_CC4_CMC_CNTS_Pos \ - (14UL) /*!< CCU4_CC4 CMC: CNTS (Bit 14) */ -#define CCU4_CC4_CMC_CNTS_Msk \ - (0xc000UL) /*!< CCU4_CC4 CMC: CNTS (Bitfield-Mask: 0x03) */ -#define CCU4_CC4_CMC_OFS_Pos \ - (16UL) /*!< CCU4_CC4 CMC: OFS (Bit 16) */ -#define CCU4_CC4_CMC_OFS_Msk \ - (0x10000UL) /*!< CCU4_CC4 CMC: OFS (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_CMC_TS_Pos \ - (17UL) /*!< CCU4_CC4 CMC: TS (Bit 17) */ -#define CCU4_CC4_CMC_TS_Msk \ - (0x20000UL) /*!< CCU4_CC4 CMC: TS (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_CMC_MOS_Pos \ - (18UL) /*!< CCU4_CC4 CMC: MOS (Bit 18) */ -#define CCU4_CC4_CMC_MOS_Msk \ - (0xc0000UL) /*!< CCU4_CC4 CMC: MOS (Bitfield-Mask: 0x03) */ -#define CCU4_CC4_CMC_TCE_Pos \ - (20UL) /*!< CCU4_CC4 CMC: TCE (Bit 20) */ -#define CCU4_CC4_CMC_TCE_Msk \ - (0x100000UL) /*!< CCU4_CC4 CMC: TCE (Bitfield-Mask: 0x01) */ - -/* -------------------------------- CCU4_CC4_TCST ------------------------------- */ -#define CCU4_CC4_TCST_TRB_Pos \ - (0UL) /*!< CCU4_CC4 TCST: TRB (Bit 0) */ -#define CCU4_CC4_TCST_TRB_Msk \ - (0x1UL) /*!< CCU4_CC4 TCST: TRB (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_TCST_CDIR_Pos \ - (1UL) /*!< CCU4_CC4 TCST: CDIR (Bit 1) */ -#define CCU4_CC4_TCST_CDIR_Msk \ - (0x2UL) /*!< CCU4_CC4 TCST: CDIR (Bitfield-Mask: 0x01) */ - -/* ------------------------------- CCU4_CC4_TCSET ------------------------------- */ -#define CCU4_CC4_TCSET_TRBS_Pos \ - (0UL) /*!< CCU4_CC4 TCSET: TRBS (Bit 0) */ -#define CCU4_CC4_TCSET_TRBS_Msk \ - (0x1UL) /*!< CCU4_CC4 TCSET: TRBS (Bitfield-Mask: 0x01) */ - -/* ------------------------------- CCU4_CC4_TCCLR ------------------------------- */ -#define CCU4_CC4_TCCLR_TRBC_Pos \ - (0UL) /*!< CCU4_CC4 TCCLR: TRBC (Bit 0) */ -#define CCU4_CC4_TCCLR_TRBC_Msk \ - (0x1UL) /*!< CCU4_CC4 TCCLR: TRBC (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_TCCLR_TCC_Pos \ - (1UL) /*!< CCU4_CC4 TCCLR: TCC (Bit 1) */ -#define CCU4_CC4_TCCLR_TCC_Msk \ - (0x2UL) /*!< CCU4_CC4 TCCLR: TCC (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_TCCLR_DITC_Pos \ - (2UL) /*!< CCU4_CC4 TCCLR: DITC (Bit 2) */ -#define CCU4_CC4_TCCLR_DITC_Msk \ - (0x4UL) /*!< CCU4_CC4 TCCLR: DITC (Bitfield-Mask: 0x01) */ - -/* --------------------------------- CCU4_CC4_TC -------------------------------- */ -#define CCU4_CC4_TC_TCM_Pos \ - (0UL) /*!< CCU4_CC4 TC: TCM (Bit 0) */ -#define CCU4_CC4_TC_TCM_Msk \ - (0x1UL) /*!< CCU4_CC4 TC: TCM (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_TC_TSSM_Pos \ - (1UL) /*!< CCU4_CC4 TC: TSSM (Bit 1) */ -#define CCU4_CC4_TC_TSSM_Msk \ - (0x2UL) /*!< CCU4_CC4 TC: TSSM (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_TC_CLST_Pos \ - (2UL) /*!< CCU4_CC4 TC: CLST (Bit 2) */ -#define CCU4_CC4_TC_CLST_Msk \ - (0x4UL) /*!< CCU4_CC4 TC: CLST (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_TC_CMOD_Pos \ - (3UL) /*!< CCU4_CC4 TC: CMOD (Bit 3) */ -#define CCU4_CC4_TC_CMOD_Msk \ - (0x8UL) /*!< CCU4_CC4 TC: CMOD (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_TC_ECM_Pos \ - (4UL) /*!< CCU4_CC4 TC: ECM (Bit 4) */ -#define CCU4_CC4_TC_ECM_Msk \ - (0x10UL) /*!< CCU4_CC4 TC: ECM (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_TC_CAPC_Pos \ - (5UL) /*!< CCU4_CC4 TC: CAPC (Bit 5) */ -#define CCU4_CC4_TC_CAPC_Msk \ - (0x60UL) /*!< CCU4_CC4 TC: CAPC (Bitfield-Mask: 0x03) */ -#define CCU4_CC4_TC_ENDM_Pos \ - (8UL) /*!< CCU4_CC4 TC: ENDM (Bit 8) */ -#define CCU4_CC4_TC_ENDM_Msk \ - (0x300UL) /*!< CCU4_CC4 TC: ENDM (Bitfield-Mask: 0x03) */ -#define CCU4_CC4_TC_STRM_Pos \ - (10UL) /*!< CCU4_CC4 TC: STRM (Bit 10) */ -#define CCU4_CC4_TC_STRM_Msk \ - (0x400UL) /*!< CCU4_CC4 TC: STRM (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_TC_SCE_Pos \ - (11UL) /*!< CCU4_CC4 TC: SCE (Bit 11) */ -#define CCU4_CC4_TC_SCE_Msk \ - (0x800UL) /*!< CCU4_CC4 TC: SCE (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_TC_CCS_Pos \ - (12UL) /*!< CCU4_CC4 TC: CCS (Bit 12) */ -#define CCU4_CC4_TC_CCS_Msk \ - (0x1000UL) /*!< CCU4_CC4 TC: CCS (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_TC_DITHE_Pos \ - (13UL) /*!< CCU4_CC4 TC: DITHE (Bit 13) */ -#define CCU4_CC4_TC_DITHE_Msk \ - (0x6000UL) /*!< CCU4_CC4 TC: DITHE (Bitfield-Mask: 0x03) */ -#define CCU4_CC4_TC_DIM_Pos \ - (15UL) /*!< CCU4_CC4 TC: DIM (Bit 15) */ -#define CCU4_CC4_TC_DIM_Msk \ - (0x8000UL) /*!< CCU4_CC4 TC: DIM (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_TC_FPE_Pos \ - (16UL) /*!< CCU4_CC4 TC: FPE (Bit 16) */ -#define CCU4_CC4_TC_FPE_Msk \ - (0x10000UL) /*!< CCU4_CC4 TC: FPE (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_TC_TRAPE_Pos \ - (17UL) /*!< CCU4_CC4 TC: TRAPE (Bit 17) */ -#define CCU4_CC4_TC_TRAPE_Msk \ - (0x20000UL) /*!< CCU4_CC4 TC: TRAPE (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_TC_TRPSE_Pos \ - (21UL) /*!< CCU4_CC4 TC: TRPSE (Bit 21) */ -#define CCU4_CC4_TC_TRPSE_Msk \ - (0x200000UL) /*!< CCU4_CC4 TC: TRPSE (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_TC_TRPSW_Pos \ - (22UL) /*!< CCU4_CC4 TC: TRPSW (Bit 22) */ -#define CCU4_CC4_TC_TRPSW_Msk \ - (0x400000UL) /*!< CCU4_CC4 TC: TRPSW (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_TC_EMS_Pos \ - (23UL) /*!< CCU4_CC4 TC: EMS (Bit 23) */ -#define CCU4_CC4_TC_EMS_Msk \ - (0x800000UL) /*!< CCU4_CC4 TC: EMS (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_TC_EMT_Pos \ - (24UL) /*!< CCU4_CC4 TC: EMT (Bit 24) */ -#define CCU4_CC4_TC_EMT_Msk \ - (0x1000000UL) /*!< CCU4_CC4 TC: EMT (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_TC_MCME_Pos \ - (25UL) /*!< CCU4_CC4 TC: MCME (Bit 25) */ -#define CCU4_CC4_TC_MCME_Msk \ - (0x2000000UL) /*!< CCU4_CC4 TC: MCME (Bitfield-Mask: 0x01) */ - -/* -------------------------------- CCU4_CC4_PSL -------------------------------- */ -#define CCU4_CC4_PSL_PSL_Pos \ - (0UL) /*!< CCU4_CC4 PSL: PSL (Bit 0) */ -#define CCU4_CC4_PSL_PSL_Msk \ - (0x1UL) /*!< CCU4_CC4 PSL: PSL (Bitfield-Mask: 0x01) */ - -/* -------------------------------- CCU4_CC4_DIT -------------------------------- */ -#define CCU4_CC4_DIT_DCV_Pos \ - (0UL) /*!< CCU4_CC4 DIT: DCV (Bit 0) */ -#define CCU4_CC4_DIT_DCV_Msk \ - (0xfUL) /*!< CCU4_CC4 DIT: DCV (Bitfield-Mask: 0x0f) */ -#define CCU4_CC4_DIT_DCNT_Pos \ - (8UL) /*!< CCU4_CC4 DIT: DCNT (Bit 8) */ -#define CCU4_CC4_DIT_DCNT_Msk \ - (0xf00UL) /*!< CCU4_CC4 DIT: DCNT (Bitfield-Mask: 0x0f) */ - -/* -------------------------------- CCU4_CC4_DITS ------------------------------- */ -#define CCU4_CC4_DITS_DCVS_Pos \ - (0UL) /*!< CCU4_CC4 DITS: DCVS (Bit 0) */ -#define CCU4_CC4_DITS_DCVS_Msk \ - (0xfUL) /*!< CCU4_CC4 DITS: DCVS (Bitfield-Mask: 0x0f) */ - -/* -------------------------------- CCU4_CC4_PSC -------------------------------- */ -#define CCU4_CC4_PSC_PSIV_Pos \ - (0UL) /*!< CCU4_CC4 PSC: PSIV (Bit 0) */ -#define CCU4_CC4_PSC_PSIV_Msk \ - (0xfUL) /*!< CCU4_CC4 PSC: PSIV (Bitfield-Mask: 0x0f) */ - -/* -------------------------------- CCU4_CC4_FPC -------------------------------- */ -#define CCU4_CC4_FPC_PCMP_Pos \ - (0UL) /*!< CCU4_CC4 FPC: PCMP (Bit 0) */ -#define CCU4_CC4_FPC_PCMP_Msk \ - (0xfUL) /*!< CCU4_CC4 FPC: PCMP (Bitfield-Mask: 0x0f) */ -#define CCU4_CC4_FPC_PVAL_Pos \ - (8UL) /*!< CCU4_CC4 FPC: PVAL (Bit 8) */ -#define CCU4_CC4_FPC_PVAL_Msk \ - (0xf00UL) /*!< CCU4_CC4 FPC: PVAL (Bitfield-Mask: 0x0f) */ - -/* -------------------------------- CCU4_CC4_FPCS ------------------------------- */ -#define CCU4_CC4_FPCS_PCMP_Pos \ - (0UL) /*!< CCU4_CC4 FPCS: PCMP (Bit 0) */ -#define CCU4_CC4_FPCS_PCMP_Msk \ - (0xfUL) /*!< CCU4_CC4 FPCS: PCMP (Bitfield-Mask: 0x0f) */ - -/* --------------------------------- CCU4_CC4_PR -------------------------------- */ -#define CCU4_CC4_PR_PR_Pos (0UL) /*!< CCU4_CC4 PR: PR (Bit 0) */ -#define CCU4_CC4_PR_PR_Msk \ - (0xffffUL) /*!< CCU4_CC4 PR: PR (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- CCU4_CC4_PRS -------------------------------- */ -#define CCU4_CC4_PRS_PRS_Pos \ - (0UL) /*!< CCU4_CC4 PRS: PRS (Bit 0) */ -#define CCU4_CC4_PRS_PRS_Msk \ - (0xffffUL) /*!< CCU4_CC4 PRS: PRS (Bitfield-Mask: 0xffff) */ - -/* --------------------------------- CCU4_CC4_CR -------------------------------- */ -#define CCU4_CC4_CR_CR_Pos (0UL) /*!< CCU4_CC4 CR: CR (Bit 0) */ -#define CCU4_CC4_CR_CR_Msk \ - (0xffffUL) /*!< CCU4_CC4 CR: CR (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- CCU4_CC4_CRS -------------------------------- */ -#define CCU4_CC4_CRS_CRS_Pos \ - (0UL) /*!< CCU4_CC4 CRS: CRS (Bit 0) */ -#define CCU4_CC4_CRS_CRS_Msk \ - (0xffffUL) /*!< CCU4_CC4 CRS: CRS (Bitfield-Mask: 0xffff) */ - -/* ------------------------------- CCU4_CC4_TIMER ------------------------------- */ -#define CCU4_CC4_TIMER_TVAL_Pos \ - (0UL) /*!< CCU4_CC4 TIMER: TVAL (Bit 0) */ -#define CCU4_CC4_TIMER_TVAL_Msk \ - (0xffffUL) /*!< CCU4_CC4 TIMER: TVAL (Bitfield-Mask: 0xffff) */ - -/* --------------------------------- CCU4_CC4_CV -------------------------------- */ -#define CCU4_CC4_CV_CAPTV_Pos \ - (0UL) /*!< CCU4_CC4 CV: CAPTV (Bit 0) */ -#define CCU4_CC4_CV_CAPTV_Msk \ - (0xffffUL) /*!< CCU4_CC4 CV: CAPTV (Bitfield-Mask: 0xffff) */ -#define CCU4_CC4_CV_FPCV_Pos \ - (16UL) /*!< CCU4_CC4 CV: FPCV (Bit 16) */ -#define CCU4_CC4_CV_FPCV_Msk \ - (0xf0000UL) /*!< CCU4_CC4 CV: FPCV (Bitfield-Mask: 0x0f) */ -#define CCU4_CC4_CV_FFL_Pos \ - (20UL) /*!< CCU4_CC4 CV: FFL (Bit 20) */ -#define CCU4_CC4_CV_FFL_Msk \ - (0x100000UL) /*!< CCU4_CC4 CV: FFL (Bitfield-Mask: 0x01) */ - -/* -------------------------------- CCU4_CC4_INTS ------------------------------- */ -#define CCU4_CC4_INTS_PMUS_Pos \ - (0UL) /*!< CCU4_CC4 INTS: PMUS (Bit 0) */ -#define CCU4_CC4_INTS_PMUS_Msk \ - (0x1UL) /*!< CCU4_CC4 INTS: PMUS (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_INTS_OMDS_Pos \ - (1UL) /*!< CCU4_CC4 INTS: OMDS (Bit 1) */ -#define CCU4_CC4_INTS_OMDS_Msk \ - (0x2UL) /*!< CCU4_CC4 INTS: OMDS (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_INTS_CMUS_Pos \ - (2UL) /*!< CCU4_CC4 INTS: CMUS (Bit 2) */ -#define CCU4_CC4_INTS_CMUS_Msk \ - (0x4UL) /*!< CCU4_CC4 INTS: CMUS (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_INTS_CMDS_Pos \ - (3UL) /*!< CCU4_CC4 INTS: CMDS (Bit 3) */ -#define CCU4_CC4_INTS_CMDS_Msk \ - (0x8UL) /*!< CCU4_CC4 INTS: CMDS (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_INTS_E0AS_Pos \ - (8UL) /*!< CCU4_CC4 INTS: E0AS (Bit 8) */ -#define CCU4_CC4_INTS_E0AS_Msk \ - (0x100UL) /*!< CCU4_CC4 INTS: E0AS (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_INTS_E1AS_Pos \ - (9UL) /*!< CCU4_CC4 INTS: E1AS (Bit 9) */ -#define CCU4_CC4_INTS_E1AS_Msk \ - (0x200UL) /*!< CCU4_CC4 INTS: E1AS (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_INTS_E2AS_Pos \ - (10UL) /*!< CCU4_CC4 INTS: E2AS (Bit 10) */ -#define CCU4_CC4_INTS_E2AS_Msk \ - (0x400UL) /*!< CCU4_CC4 INTS: E2AS (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_INTS_TRPF_Pos \ - (11UL) /*!< CCU4_CC4 INTS: TRPF (Bit 11) */ -#define CCU4_CC4_INTS_TRPF_Msk \ - (0x800UL) /*!< CCU4_CC4 INTS: TRPF (Bitfield-Mask: 0x01) */ - -/* -------------------------------- CCU4_CC4_INTE ------------------------------- */ -#define CCU4_CC4_INTE_PME_Pos \ - (0UL) /*!< CCU4_CC4 INTE: PME (Bit 0) */ -#define CCU4_CC4_INTE_PME_Msk \ - (0x1UL) /*!< CCU4_CC4 INTE: PME (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_INTE_OME_Pos \ - (1UL) /*!< CCU4_CC4 INTE: OME (Bit 1) */ -#define CCU4_CC4_INTE_OME_Msk \ - (0x2UL) /*!< CCU4_CC4 INTE: OME (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_INTE_CMUE_Pos \ - (2UL) /*!< CCU4_CC4 INTE: CMUE (Bit 2) */ -#define CCU4_CC4_INTE_CMUE_Msk \ - (0x4UL) /*!< CCU4_CC4 INTE: CMUE (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_INTE_CMDE_Pos \ - (3UL) /*!< CCU4_CC4 INTE: CMDE (Bit 3) */ -#define CCU4_CC4_INTE_CMDE_Msk \ - (0x8UL) /*!< CCU4_CC4 INTE: CMDE (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_INTE_E0AE_Pos \ - (8UL) /*!< CCU4_CC4 INTE: E0AE (Bit 8) */ -#define CCU4_CC4_INTE_E0AE_Msk \ - (0x100UL) /*!< CCU4_CC4 INTE: E0AE (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_INTE_E1AE_Pos \ - (9UL) /*!< CCU4_CC4 INTE: E1AE (Bit 9) */ -#define CCU4_CC4_INTE_E1AE_Msk \ - (0x200UL) /*!< CCU4_CC4 INTE: E1AE (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_INTE_E2AE_Pos \ - (10UL) /*!< CCU4_CC4 INTE: E2AE (Bit 10) */ -#define CCU4_CC4_INTE_E2AE_Msk \ - (0x400UL) /*!< CCU4_CC4 INTE: E2AE (Bitfield-Mask: 0x01) */ - -/* -------------------------------- CCU4_CC4_SRS -------------------------------- */ -#define CCU4_CC4_SRS_POSR_Pos \ - (0UL) /*!< CCU4_CC4 SRS: POSR (Bit 0) */ -#define CCU4_CC4_SRS_POSR_Msk \ - (0x3UL) /*!< CCU4_CC4 SRS: POSR (Bitfield-Mask: 0x03) */ -#define CCU4_CC4_SRS_CMSR_Pos \ - (2UL) /*!< CCU4_CC4 SRS: CMSR (Bit 2) */ -#define CCU4_CC4_SRS_CMSR_Msk \ - (0xcUL) /*!< CCU4_CC4 SRS: CMSR (Bitfield-Mask: 0x03) */ -#define CCU4_CC4_SRS_E0SR_Pos \ - (8UL) /*!< CCU4_CC4 SRS: E0SR (Bit 8) */ -#define CCU4_CC4_SRS_E0SR_Msk \ - (0x300UL) /*!< CCU4_CC4 SRS: E0SR (Bitfield-Mask: 0x03) */ -#define CCU4_CC4_SRS_E1SR_Pos \ - (10UL) /*!< CCU4_CC4 SRS: E1SR (Bit 10) */ -#define CCU4_CC4_SRS_E1SR_Msk \ - (0xc00UL) /*!< CCU4_CC4 SRS: E1SR (Bitfield-Mask: 0x03) */ -#define CCU4_CC4_SRS_E2SR_Pos \ - (12UL) /*!< CCU4_CC4 SRS: E2SR (Bit 12) */ -#define CCU4_CC4_SRS_E2SR_Msk \ - (0x3000UL) /*!< CCU4_CC4 SRS: E2SR (Bitfield-Mask: 0x03) */ - -/* -------------------------------- CCU4_CC4_SWS -------------------------------- */ -#define CCU4_CC4_SWS_SPM_Pos \ - (0UL) /*!< CCU4_CC4 SWS: SPM (Bit 0) */ -#define CCU4_CC4_SWS_SPM_Msk \ - (0x1UL) /*!< CCU4_CC4 SWS: SPM (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_SWS_SOM_Pos \ - (1UL) /*!< CCU4_CC4 SWS: SOM (Bit 1) */ -#define CCU4_CC4_SWS_SOM_Msk \ - (0x2UL) /*!< CCU4_CC4 SWS: SOM (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_SWS_SCMU_Pos \ - (2UL) /*!< CCU4_CC4 SWS: SCMU (Bit 2) */ -#define CCU4_CC4_SWS_SCMU_Msk \ - (0x4UL) /*!< CCU4_CC4 SWS: SCMU (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_SWS_SCMD_Pos \ - (3UL) /*!< CCU4_CC4 SWS: SCMD (Bit 3) */ -#define CCU4_CC4_SWS_SCMD_Msk \ - (0x8UL) /*!< CCU4_CC4 SWS: SCMD (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_SWS_SE0A_Pos \ - (8UL) /*!< CCU4_CC4 SWS: SE0A (Bit 8) */ -#define CCU4_CC4_SWS_SE0A_Msk \ - (0x100UL) /*!< CCU4_CC4 SWS: SE0A (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_SWS_SE1A_Pos \ - (9UL) /*!< CCU4_CC4 SWS: SE1A (Bit 9) */ -#define CCU4_CC4_SWS_SE1A_Msk \ - (0x200UL) /*!< CCU4_CC4 SWS: SE1A (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_SWS_SE2A_Pos \ - (10UL) /*!< CCU4_CC4 SWS: SE2A (Bit 10) */ -#define CCU4_CC4_SWS_SE2A_Msk \ - (0x400UL) /*!< CCU4_CC4 SWS: SE2A (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_SWS_STRPF_Pos \ - (11UL) /*!< CCU4_CC4 SWS: STRPF (Bit 11) */ -#define CCU4_CC4_SWS_STRPF_Msk \ - (0x800UL) /*!< CCU4_CC4 SWS: STRPF (Bitfield-Mask: 0x01) */ - -/* -------------------------------- CCU4_CC4_SWR -------------------------------- */ -#define CCU4_CC4_SWR_RPM_Pos \ - (0UL) /*!< CCU4_CC4 SWR: RPM (Bit 0) */ -#define CCU4_CC4_SWR_RPM_Msk \ - (0x1UL) /*!< CCU4_CC4 SWR: RPM (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_SWR_ROM_Pos \ - (1UL) /*!< CCU4_CC4 SWR: ROM (Bit 1) */ -#define CCU4_CC4_SWR_ROM_Msk \ - (0x2UL) /*!< CCU4_CC4 SWR: ROM (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_SWR_RCMU_Pos \ - (2UL) /*!< CCU4_CC4 SWR: RCMU (Bit 2) */ -#define CCU4_CC4_SWR_RCMU_Msk \ - (0x4UL) /*!< CCU4_CC4 SWR: RCMU (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_SWR_RCMD_Pos \ - (3UL) /*!< CCU4_CC4 SWR: RCMD (Bit 3) */ -#define CCU4_CC4_SWR_RCMD_Msk \ - (0x8UL) /*!< CCU4_CC4 SWR: RCMD (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_SWR_RE0A_Pos \ - (8UL) /*!< CCU4_CC4 SWR: RE0A (Bit 8) */ -#define CCU4_CC4_SWR_RE0A_Msk \ - (0x100UL) /*!< CCU4_CC4 SWR: RE0A (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_SWR_RE1A_Pos \ - (9UL) /*!< CCU4_CC4 SWR: RE1A (Bit 9) */ -#define CCU4_CC4_SWR_RE1A_Msk \ - (0x200UL) /*!< CCU4_CC4 SWR: RE1A (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_SWR_RE2A_Pos \ - (10UL) /*!< CCU4_CC4 SWR: RE2A (Bit 10) */ -#define CCU4_CC4_SWR_RE2A_Msk \ - (0x400UL) /*!< CCU4_CC4 SWR: RE2A (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_SWR_RTRPF_Pos \ - (11UL) /*!< CCU4_CC4 SWR: RTRPF (Bit 11) */ -#define CCU4_CC4_SWR_RTRPF_Msk \ - (0x800UL) /*!< CCU4_CC4 SWR: RTRPF (Bitfield-Mask: 0x01) */ - -/* ================================================================================ */ -/* ================ Group 'CCU8' Position & Mask ================ */ -/* ================================================================================ */ - -/* --------------------------------- CCU8_GCTRL --------------------------------- */ -#define CCU8_GCTRL_PRBC_Pos \ - (0UL) /*!< CCU8 GCTRL: PRBC (Bit 0) */ -#define CCU8_GCTRL_PRBC_Msk \ - (0x7UL) /*!< CCU8 GCTRL: PRBC (Bitfield-Mask: 0x07) */ -#define CCU8_GCTRL_PCIS_Pos \ - (4UL) /*!< CCU8 GCTRL: PCIS (Bit 4) */ -#define CCU8_GCTRL_PCIS_Msk \ - (0x30UL) /*!< CCU8 GCTRL: PCIS (Bitfield-Mask: 0x03) */ -#define CCU8_GCTRL_SUSCFG_Pos \ - (8UL) /*!< CCU8 GCTRL: SUSCFG (Bit 8) */ -#define CCU8_GCTRL_SUSCFG_Msk \ - (0x300UL) /*!< CCU8 GCTRL: SUSCFG (Bitfield-Mask: 0x03) */ -#define CCU8_GCTRL_MSE0_Pos \ - (10UL) /*!< CCU8 GCTRL: MSE0 (Bit 10) */ -#define CCU8_GCTRL_MSE0_Msk \ - (0x400UL) /*!< CCU8 GCTRL: MSE0 (Bitfield-Mask: 0x01) */ -#define CCU8_GCTRL_MSE1_Pos \ - (11UL) /*!< CCU8 GCTRL: MSE1 (Bit 11) */ -#define CCU8_GCTRL_MSE1_Msk \ - (0x800UL) /*!< CCU8 GCTRL: MSE1 (Bitfield-Mask: 0x01) */ -#define CCU8_GCTRL_MSE2_Pos \ - (12UL) /*!< CCU8 GCTRL: MSE2 (Bit 12) */ -#define CCU8_GCTRL_MSE2_Msk \ - (0x1000UL) /*!< CCU8 GCTRL: MSE2 (Bitfield-Mask: 0x01) */ -#define CCU8_GCTRL_MSE3_Pos \ - (13UL) /*!< CCU8 GCTRL: MSE3 (Bit 13) */ -#define CCU8_GCTRL_MSE3_Msk \ - (0x2000UL) /*!< CCU8 GCTRL: MSE3 (Bitfield-Mask: 0x01) */ -#define CCU8_GCTRL_MSDE_Pos \ - (14UL) /*!< CCU8 GCTRL: MSDE (Bit 14) */ -#define CCU8_GCTRL_MSDE_Msk \ - (0xc000UL) /*!< CCU8 GCTRL: MSDE (Bitfield-Mask: 0x03) */ - -/* --------------------------------- CCU8_GSTAT --------------------------------- */ -#define CCU8_GSTAT_S0I_Pos (0UL) /*!< CCU8 GSTAT: S0I (Bit 0) */ -#define CCU8_GSTAT_S0I_Msk \ - (0x1UL) /*!< CCU8 GSTAT: S0I (Bitfield-Mask: 0x01) */ -#define CCU8_GSTAT_S1I_Pos (1UL) /*!< CCU8 GSTAT: S1I (Bit 1) */ -#define CCU8_GSTAT_S1I_Msk \ - (0x2UL) /*!< CCU8 GSTAT: S1I (Bitfield-Mask: 0x01) */ -#define CCU8_GSTAT_S2I_Pos (2UL) /*!< CCU8 GSTAT: S2I (Bit 2) */ -#define CCU8_GSTAT_S2I_Msk \ - (0x4UL) /*!< CCU8 GSTAT: S2I (Bitfield-Mask: 0x01) */ -#define CCU8_GSTAT_S3I_Pos (3UL) /*!< CCU8 GSTAT: S3I (Bit 3) */ -#define CCU8_GSTAT_S3I_Msk \ - (0x8UL) /*!< CCU8 GSTAT: S3I (Bitfield-Mask: 0x01) */ -#define CCU8_GSTAT_PRB_Pos (8UL) /*!< CCU8 GSTAT: PRB (Bit 8) */ -#define CCU8_GSTAT_PRB_Msk \ - (0x100UL) /*!< CCU8 GSTAT: PRB (Bitfield-Mask: 0x01) */ -#define CCU8_GSTAT_PCRB_Pos \ - (10UL) /*!< CCU8 GSTAT: PCRB (Bit 10) */ -#define CCU8_GSTAT_PCRB_Msk \ - (0x400UL) /*!< CCU8 GSTAT: PCRB (Bitfield-Mask: 0x01) */ - -/* --------------------------------- CCU8_GIDLS --------------------------------- */ -#define CCU8_GIDLS_SS0I_Pos \ - (0UL) /*!< CCU8 GIDLS: SS0I (Bit 0) */ -#define CCU8_GIDLS_SS0I_Msk \ - (0x1UL) /*!< CCU8 GIDLS: SS0I (Bitfield-Mask: 0x01) */ -#define CCU8_GIDLS_SS1I_Pos \ - (1UL) /*!< CCU8 GIDLS: SS1I (Bit 1) */ -#define CCU8_GIDLS_SS1I_Msk \ - (0x2UL) /*!< CCU8 GIDLS: SS1I (Bitfield-Mask: 0x01) */ -#define CCU8_GIDLS_SS2I_Pos \ - (2UL) /*!< CCU8 GIDLS: SS2I (Bit 2) */ -#define CCU8_GIDLS_SS2I_Msk \ - (0x4UL) /*!< CCU8 GIDLS: SS2I (Bitfield-Mask: 0x01) */ -#define CCU8_GIDLS_SS3I_Pos \ - (3UL) /*!< CCU8 GIDLS: SS3I (Bit 3) */ -#define CCU8_GIDLS_SS3I_Msk \ - (0x8UL) /*!< CCU8 GIDLS: SS3I (Bitfield-Mask: 0x01) */ -#define CCU8_GIDLS_CPRB_Pos \ - (8UL) /*!< CCU8 GIDLS: CPRB (Bit 8) */ -#define CCU8_GIDLS_CPRB_Msk \ - (0x100UL) /*!< CCU8 GIDLS: CPRB (Bitfield-Mask: 0x01) */ -#define CCU8_GIDLS_PSIC_Pos \ - (9UL) /*!< CCU8 GIDLS: PSIC (Bit 9) */ -#define CCU8_GIDLS_PSIC_Msk \ - (0x200UL) /*!< CCU8 GIDLS: PSIC (Bitfield-Mask: 0x01) */ -#define CCU8_GIDLS_CPCH_Pos \ - (10UL) /*!< CCU8 GIDLS: CPCH (Bit 10) */ -#define CCU8_GIDLS_CPCH_Msk \ - (0x400UL) /*!< CCU8 GIDLS: CPCH (Bitfield-Mask: 0x01) */ - -/* --------------------------------- CCU8_GIDLC --------------------------------- */ -#define CCU8_GIDLC_CS0I_Pos \ - (0UL) /*!< CCU8 GIDLC: CS0I (Bit 0) */ -#define CCU8_GIDLC_CS0I_Msk \ - (0x1UL) /*!< CCU8 GIDLC: CS0I (Bitfield-Mask: 0x01) */ -#define CCU8_GIDLC_CS1I_Pos \ - (1UL) /*!< CCU8 GIDLC: CS1I (Bit 1) */ -#define CCU8_GIDLC_CS1I_Msk \ - (0x2UL) /*!< CCU8 GIDLC: CS1I (Bitfield-Mask: 0x01) */ -#define CCU8_GIDLC_CS2I_Pos \ - (2UL) /*!< CCU8 GIDLC: CS2I (Bit 2) */ -#define CCU8_GIDLC_CS2I_Msk \ - (0x4UL) /*!< CCU8 GIDLC: CS2I (Bitfield-Mask: 0x01) */ -#define CCU8_GIDLC_CS3I_Pos \ - (3UL) /*!< CCU8 GIDLC: CS3I (Bit 3) */ -#define CCU8_GIDLC_CS3I_Msk \ - (0x8UL) /*!< CCU8 GIDLC: CS3I (Bitfield-Mask: 0x01) */ -#define CCU8_GIDLC_SPRB_Pos \ - (8UL) /*!< CCU8 GIDLC: SPRB (Bit 8) */ -#define CCU8_GIDLC_SPRB_Msk \ - (0x100UL) /*!< CCU8 GIDLC: SPRB (Bitfield-Mask: 0x01) */ -#define CCU8_GIDLC_SPCH_Pos \ - (10UL) /*!< CCU8 GIDLC: SPCH (Bit 10) */ -#define CCU8_GIDLC_SPCH_Msk \ - (0x400UL) /*!< CCU8 GIDLC: SPCH (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- CCU8_GCSS --------------------------------- */ -#define CCU8_GCSS_S0SE_Pos (0UL) /*!< CCU8 GCSS: S0SE (Bit 0) */ -#define CCU8_GCSS_S0SE_Msk \ - (0x1UL) /*!< CCU8 GCSS: S0SE (Bitfield-Mask: 0x01) */ -#define CCU8_GCSS_S0DSE_Pos \ - (1UL) /*!< CCU8 GCSS: S0DSE (Bit 1) */ -#define CCU8_GCSS_S0DSE_Msk \ - (0x2UL) /*!< CCU8 GCSS: S0DSE (Bitfield-Mask: 0x01) */ -#define CCU8_GCSS_S0PSE_Pos \ - (2UL) /*!< CCU8 GCSS: S0PSE (Bit 2) */ -#define CCU8_GCSS_S0PSE_Msk \ - (0x4UL) /*!< CCU8 GCSS: S0PSE (Bitfield-Mask: 0x01) */ -#define CCU8_GCSS_S1SE_Pos (4UL) /*!< CCU8 GCSS: S1SE (Bit 4) */ -#define CCU8_GCSS_S1SE_Msk \ - (0x10UL) /*!< CCU8 GCSS: S1SE (Bitfield-Mask: 0x01) */ -#define CCU8_GCSS_S1DSE_Pos \ - (5UL) /*!< CCU8 GCSS: S1DSE (Bit 5) */ -#define CCU8_GCSS_S1DSE_Msk \ - (0x20UL) /*!< CCU8 GCSS: S1DSE (Bitfield-Mask: 0x01) */ -#define CCU8_GCSS_S1PSE_Pos \ - (6UL) /*!< CCU8 GCSS: S1PSE (Bit 6) */ -#define CCU8_GCSS_S1PSE_Msk \ - (0x40UL) /*!< CCU8 GCSS: S1PSE (Bitfield-Mask: 0x01) */ -#define CCU8_GCSS_S2SE_Pos (8UL) /*!< CCU8 GCSS: S2SE (Bit 8) */ -#define CCU8_GCSS_S2SE_Msk \ - (0x100UL) /*!< CCU8 GCSS: S2SE (Bitfield-Mask: 0x01) */ -#define CCU8_GCSS_S2DSE_Pos \ - (9UL) /*!< CCU8 GCSS: S2DSE (Bit 9) */ -#define CCU8_GCSS_S2DSE_Msk \ - (0x200UL) /*!< CCU8 GCSS: S2DSE (Bitfield-Mask: 0x01) */ -#define CCU8_GCSS_S2PSE_Pos \ - (10UL) /*!< CCU8 GCSS: S2PSE (Bit 10) */ -#define CCU8_GCSS_S2PSE_Msk \ - (0x400UL) /*!< CCU8 GCSS: S2PSE (Bitfield-Mask: 0x01) */ -#define CCU8_GCSS_S3SE_Pos \ - (12UL) /*!< CCU8 GCSS: S3SE (Bit 12) */ -#define CCU8_GCSS_S3SE_Msk \ - (0x1000UL) /*!< CCU8 GCSS: S3SE (Bitfield-Mask: 0x01) */ -#define CCU8_GCSS_S3DSE_Pos \ - (13UL) /*!< CCU8 GCSS: S3DSE (Bit 13) */ -#define CCU8_GCSS_S3DSE_Msk \ - (0x2000UL) /*!< CCU8 GCSS: S3DSE (Bitfield-Mask: 0x01) */ -#define CCU8_GCSS_S3PSE_Pos \ - (14UL) /*!< CCU8 GCSS: S3PSE (Bit 14) */ -#define CCU8_GCSS_S3PSE_Msk \ - (0x4000UL) /*!< CCU8 GCSS: S3PSE (Bitfield-Mask: 0x01) */ -#define CCU8_GCSS_S0ST1S_Pos \ - (16UL) /*!< CCU8 GCSS: S0ST1S (Bit 16) */ -#define CCU8_GCSS_S0ST1S_Msk \ - (0x10000UL) /*!< CCU8 GCSS: S0ST1S (Bitfield-Mask: 0x01) */ -#define CCU8_GCSS_S1ST1S_Pos \ - (17UL) /*!< CCU8 GCSS: S1ST1S (Bit 17) */ -#define CCU8_GCSS_S1ST1S_Msk \ - (0x20000UL) /*!< CCU8 GCSS: S1ST1S (Bitfield-Mask: 0x01) */ -#define CCU8_GCSS_S2ST1S_Pos \ - (18UL) /*!< CCU8 GCSS: S2ST1S (Bit 18) */ -#define CCU8_GCSS_S2ST1S_Msk \ - (0x40000UL) /*!< CCU8 GCSS: S2ST1S (Bitfield-Mask: 0x01) */ -#define CCU8_GCSS_S3ST1S_Pos \ - (19UL) /*!< CCU8 GCSS: S3ST1S (Bit 19) */ -#define CCU8_GCSS_S3ST1S_Msk \ - (0x80000UL) /*!< CCU8 GCSS: S3ST1S (Bitfield-Mask: 0x01) */ -#define CCU8_GCSS_S0ST2S_Pos \ - (20UL) /*!< CCU8 GCSS: S0ST2S (Bit 20) */ -#define CCU8_GCSS_S0ST2S_Msk \ - (0x100000UL) /*!< CCU8 GCSS: S0ST2S (Bitfield-Mask: 0x01) */ -#define CCU8_GCSS_S1ST2S_Pos \ - (21UL) /*!< CCU8 GCSS: S1ST2S (Bit 21) */ -#define CCU8_GCSS_S1ST2S_Msk \ - (0x200000UL) /*!< CCU8 GCSS: S1ST2S (Bitfield-Mask: 0x01) */ -#define CCU8_GCSS_S2ST2S_Pos \ - (22UL) /*!< CCU8 GCSS: S2ST2S (Bit 22) */ -#define CCU8_GCSS_S2ST2S_Msk \ - (0x400000UL) /*!< CCU8 GCSS: S2ST2S (Bitfield-Mask: 0x01) */ -#define CCU8_GCSS_S3ST2S_Pos \ - (23UL) /*!< CCU8 GCSS: S3ST2S (Bit 23) */ -#define CCU8_GCSS_S3ST2S_Msk \ - (0x800000UL) /*!< CCU8 GCSS: S3ST2S (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- CCU8_GCSC --------------------------------- */ -#define CCU8_GCSC_S0SC_Pos (0UL) /*!< CCU8 GCSC: S0SC (Bit 0) */ -#define CCU8_GCSC_S0SC_Msk \ - (0x1UL) /*!< CCU8 GCSC: S0SC (Bitfield-Mask: 0x01) */ -#define CCU8_GCSC_S0DSC_Pos \ - (1UL) /*!< CCU8 GCSC: S0DSC (Bit 1) */ -#define CCU8_GCSC_S0DSC_Msk \ - (0x2UL) /*!< CCU8 GCSC: S0DSC (Bitfield-Mask: 0x01) */ -#define CCU8_GCSC_S0PSC_Pos \ - (2UL) /*!< CCU8 GCSC: S0PSC (Bit 2) */ -#define CCU8_GCSC_S0PSC_Msk \ - (0x4UL) /*!< CCU8 GCSC: S0PSC (Bitfield-Mask: 0x01) */ -#define CCU8_GCSC_S1SC_Pos (4UL) /*!< CCU8 GCSC: S1SC (Bit 4) */ -#define CCU8_GCSC_S1SC_Msk \ - (0x10UL) /*!< CCU8 GCSC: S1SC (Bitfield-Mask: 0x01) */ -#define CCU8_GCSC_S1DSC_Pos \ - (5UL) /*!< CCU8 GCSC: S1DSC (Bit 5) */ -#define CCU8_GCSC_S1DSC_Msk \ - (0x20UL) /*!< CCU8 GCSC: S1DSC (Bitfield-Mask: 0x01) */ -#define CCU8_GCSC_S1PSC_Pos \ - (6UL) /*!< CCU8 GCSC: S1PSC (Bit 6) */ -#define CCU8_GCSC_S1PSC_Msk \ - (0x40UL) /*!< CCU8 GCSC: S1PSC (Bitfield-Mask: 0x01) */ -#define CCU8_GCSC_S2SC_Pos (8UL) /*!< CCU8 GCSC: S2SC (Bit 8) */ -#define CCU8_GCSC_S2SC_Msk \ - (0x100UL) /*!< CCU8 GCSC: S2SC (Bitfield-Mask: 0x01) */ -#define CCU8_GCSC_S2DSC_Pos \ - (9UL) /*!< CCU8 GCSC: S2DSC (Bit 9) */ -#define CCU8_GCSC_S2DSC_Msk \ - (0x200UL) /*!< CCU8 GCSC: S2DSC (Bitfield-Mask: 0x01) */ -#define CCU8_GCSC_S2PSC_Pos \ - (10UL) /*!< CCU8 GCSC: S2PSC (Bit 10) */ -#define CCU8_GCSC_S2PSC_Msk \ - (0x400UL) /*!< CCU8 GCSC: S2PSC (Bitfield-Mask: 0x01) */ -#define CCU8_GCSC_S3SC_Pos \ - (12UL) /*!< CCU8 GCSC: S3SC (Bit 12) */ -#define CCU8_GCSC_S3SC_Msk \ - (0x1000UL) /*!< CCU8 GCSC: S3SC (Bitfield-Mask: 0x01) */ -#define CCU8_GCSC_S3DSC_Pos \ - (13UL) /*!< CCU8 GCSC: S3DSC (Bit 13) */ -#define CCU8_GCSC_S3DSC_Msk \ - (0x2000UL) /*!< CCU8 GCSC: S3DSC (Bitfield-Mask: 0x01) */ -#define CCU8_GCSC_S3PSC_Pos \ - (14UL) /*!< CCU8 GCSC: S3PSC (Bit 14) */ -#define CCU8_GCSC_S3PSC_Msk \ - (0x4000UL) /*!< CCU8 GCSC: S3PSC (Bitfield-Mask: 0x01) */ -#define CCU8_GCSC_S0ST1C_Pos \ - (16UL) /*!< CCU8 GCSC: S0ST1C (Bit 16) */ -#define CCU8_GCSC_S0ST1C_Msk \ - (0x10000UL) /*!< CCU8 GCSC: S0ST1C (Bitfield-Mask: 0x01) */ -#define CCU8_GCSC_S1ST1C_Pos \ - (17UL) /*!< CCU8 GCSC: S1ST1C (Bit 17) */ -#define CCU8_GCSC_S1ST1C_Msk \ - (0x20000UL) /*!< CCU8 GCSC: S1ST1C (Bitfield-Mask: 0x01) */ -#define CCU8_GCSC_S2ST1C_Pos \ - (18UL) /*!< CCU8 GCSC: S2ST1C (Bit 18) */ -#define CCU8_GCSC_S2ST1C_Msk \ - (0x40000UL) /*!< CCU8 GCSC: S2ST1C (Bitfield-Mask: 0x01) */ -#define CCU8_GCSC_S3ST1C_Pos \ - (19UL) /*!< CCU8 GCSC: S3ST1C (Bit 19) */ -#define CCU8_GCSC_S3ST1C_Msk \ - (0x80000UL) /*!< CCU8 GCSC: S3ST1C (Bitfield-Mask: 0x01) */ -#define CCU8_GCSC_S0ST2C_Pos \ - (20UL) /*!< CCU8 GCSC: S0ST2C (Bit 20) */ -#define CCU8_GCSC_S0ST2C_Msk \ - (0x100000UL) /*!< CCU8 GCSC: S0ST2C (Bitfield-Mask: 0x01) */ -#define CCU8_GCSC_S1ST2C_Pos \ - (21UL) /*!< CCU8 GCSC: S1ST2C (Bit 21) */ -#define CCU8_GCSC_S1ST2C_Msk \ - (0x200000UL) /*!< CCU8 GCSC: S1ST2C (Bitfield-Mask: 0x01) */ -#define CCU8_GCSC_S2ST2C_Pos \ - (22UL) /*!< CCU8 GCSC: S2ST2C (Bit 22) */ -#define CCU8_GCSC_S2ST2C_Msk \ - (0x400000UL) /*!< CCU8 GCSC: S2ST2C (Bitfield-Mask: 0x01) */ -#define CCU8_GCSC_S3ST2C_Pos \ - (23UL) /*!< CCU8 GCSC: S3ST2C (Bit 23) */ -#define CCU8_GCSC_S3ST2C_Msk \ - (0x800000UL) /*!< CCU8 GCSC: S3ST2C (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- CCU8_GCST --------------------------------- */ -#define CCU8_GCST_S0SS_Pos (0UL) /*!< CCU8 GCST: S0SS (Bit 0) */ -#define CCU8_GCST_S0SS_Msk \ - (0x1UL) /*!< CCU8 GCST: S0SS (Bitfield-Mask: 0x01) */ -#define CCU8_GCST_S0DSS_Pos \ - (1UL) /*!< CCU8 GCST: S0DSS (Bit 1) */ -#define CCU8_GCST_S0DSS_Msk \ - (0x2UL) /*!< CCU8 GCST: S0DSS (Bitfield-Mask: 0x01) */ -#define CCU8_GCST_S0PSS_Pos \ - (2UL) /*!< CCU8 GCST: S0PSS (Bit 2) */ -#define CCU8_GCST_S0PSS_Msk \ - (0x4UL) /*!< CCU8 GCST: S0PSS (Bitfield-Mask: 0x01) */ -#define CCU8_GCST_S1SS_Pos (4UL) /*!< CCU8 GCST: S1SS (Bit 4) */ -#define CCU8_GCST_S1SS_Msk \ - (0x10UL) /*!< CCU8 GCST: S1SS (Bitfield-Mask: 0x01) */ -#define CCU8_GCST_S1DSS_Pos \ - (5UL) /*!< CCU8 GCST: S1DSS (Bit 5) */ -#define CCU8_GCST_S1DSS_Msk \ - (0x20UL) /*!< CCU8 GCST: S1DSS (Bitfield-Mask: 0x01) */ -#define CCU8_GCST_S1PSS_Pos \ - (6UL) /*!< CCU8 GCST: S1PSS (Bit 6) */ -#define CCU8_GCST_S1PSS_Msk \ - (0x40UL) /*!< CCU8 GCST: S1PSS (Bitfield-Mask: 0x01) */ -#define CCU8_GCST_S2SS_Pos (8UL) /*!< CCU8 GCST: S2SS (Bit 8) */ -#define CCU8_GCST_S2SS_Msk \ - (0x100UL) /*!< CCU8 GCST: S2SS (Bitfield-Mask: 0x01) */ -#define CCU8_GCST_S2DSS_Pos \ - (9UL) /*!< CCU8 GCST: S2DSS (Bit 9) */ -#define CCU8_GCST_S2DSS_Msk \ - (0x200UL) /*!< CCU8 GCST: S2DSS (Bitfield-Mask: 0x01) */ -#define CCU8_GCST_S2PSS_Pos \ - (10UL) /*!< CCU8 GCST: S2PSS (Bit 10) */ -#define CCU8_GCST_S2PSS_Msk \ - (0x400UL) /*!< CCU8 GCST: S2PSS (Bitfield-Mask: 0x01) */ -#define CCU8_GCST_S3SS_Pos \ - (12UL) /*!< CCU8 GCST: S3SS (Bit 12) */ -#define CCU8_GCST_S3SS_Msk \ - (0x1000UL) /*!< CCU8 GCST: S3SS (Bitfield-Mask: 0x01) */ -#define CCU8_GCST_S3DSS_Pos \ - (13UL) /*!< CCU8 GCST: S3DSS (Bit 13) */ -#define CCU8_GCST_S3DSS_Msk \ - (0x2000UL) /*!< CCU8 GCST: S3DSS (Bitfield-Mask: 0x01) */ -#define CCU8_GCST_S3PSS_Pos \ - (14UL) /*!< CCU8 GCST: S3PSS (Bit 14) */ -#define CCU8_GCST_S3PSS_Msk \ - (0x4000UL) /*!< CCU8 GCST: S3PSS (Bitfield-Mask: 0x01) */ -#define CCU8_GCST_CC80ST1_Pos \ - (16UL) /*!< CCU8 GCST: CC80ST1 (Bit 16) */ -#define CCU8_GCST_CC80ST1_Msk \ - (0x10000UL) /*!< CCU8 GCST: CC80ST1 (Bitfield-Mask: 0x01) */ -#define CCU8_GCST_CC81ST1_Pos \ - (17UL) /*!< CCU8 GCST: CC81ST1 (Bit 17) */ -#define CCU8_GCST_CC81ST1_Msk \ - (0x20000UL) /*!< CCU8 GCST: CC81ST1 (Bitfield-Mask: 0x01) */ -#define CCU8_GCST_CC82ST1_Pos \ - (18UL) /*!< CCU8 GCST: CC82ST1 (Bit 18) */ -#define CCU8_GCST_CC82ST1_Msk \ - (0x40000UL) /*!< CCU8 GCST: CC82ST1 (Bitfield-Mask: 0x01) */ -#define CCU8_GCST_CC83ST1_Pos \ - (19UL) /*!< CCU8 GCST: CC83ST1 (Bit 19) */ -#define CCU8_GCST_CC83ST1_Msk \ - (0x80000UL) /*!< CCU8 GCST: CC83ST1 (Bitfield-Mask: 0x01) */ -#define CCU8_GCST_CC80ST2_Pos \ - (20UL) /*!< CCU8 GCST: CC80ST2 (Bit 20) */ -#define CCU8_GCST_CC80ST2_Msk \ - (0x100000UL) /*!< CCU8 GCST: CC80ST2 (Bitfield-Mask: 0x01) */ -#define CCU8_GCST_CC81ST2_Pos \ - (21UL) /*!< CCU8 GCST: CC81ST2 (Bit 21) */ -#define CCU8_GCST_CC81ST2_Msk \ - (0x200000UL) /*!< CCU8 GCST: CC81ST2 (Bitfield-Mask: 0x01) */ -#define CCU8_GCST_CC82ST2_Pos \ - (22UL) /*!< CCU8 GCST: CC82ST2 (Bit 22) */ -#define CCU8_GCST_CC82ST2_Msk \ - (0x400000UL) /*!< CCU8 GCST: CC82ST2 (Bitfield-Mask: 0x01) */ -#define CCU8_GCST_CC83ST2_Pos \ - (23UL) /*!< CCU8 GCST: CC83ST2 (Bit 23) */ -#define CCU8_GCST_CC83ST2_Msk \ - (0x800000UL) /*!< CCU8 GCST: CC83ST2 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- CCU8_GPCHK --------------------------------- */ -#define CCU8_GPCHK_PASE_Pos \ - (0UL) /*!< CCU8 GPCHK: PASE (Bit 0) */ -#define CCU8_GPCHK_PASE_Msk \ - (0x1UL) /*!< CCU8 GPCHK: PASE (Bitfield-Mask: 0x01) */ -#define CCU8_GPCHK_PACS_Pos \ - (1UL) /*!< CCU8 GPCHK: PACS (Bit 1) */ -#define CCU8_GPCHK_PACS_Msk \ - (0x6UL) /*!< CCU8 GPCHK: PACS (Bitfield-Mask: 0x03) */ -#define CCU8_GPCHK_PISEL_Pos \ - (3UL) /*!< CCU8 GPCHK: PISEL (Bit 3) */ -#define CCU8_GPCHK_PISEL_Msk \ - (0x18UL) /*!< CCU8 GPCHK: PISEL (Bitfield-Mask: 0x03) */ -#define CCU8_GPCHK_PCDS_Pos \ - (5UL) /*!< CCU8 GPCHK: PCDS (Bit 5) */ -#define CCU8_GPCHK_PCDS_Msk \ - (0x60UL) /*!< CCU8 GPCHK: PCDS (Bitfield-Mask: 0x03) */ -#define CCU8_GPCHK_PCTS_Pos \ - (7UL) /*!< CCU8 GPCHK: PCTS (Bit 7) */ -#define CCU8_GPCHK_PCTS_Msk \ - (0x80UL) /*!< CCU8 GPCHK: PCTS (Bitfield-Mask: 0x01) */ -#define CCU8_GPCHK_PCST_Pos \ - (15UL) /*!< CCU8 GPCHK: PCST (Bit 15) */ -#define CCU8_GPCHK_PCST_Msk \ - (0x8000UL) /*!< CCU8 GPCHK: PCST (Bitfield-Mask: 0x01) */ -#define CCU8_GPCHK_PCSEL0_Pos \ - (16UL) /*!< CCU8 GPCHK: PCSEL0 (Bit 16) */ -#define CCU8_GPCHK_PCSEL0_Msk \ - (0xf0000UL) /*!< CCU8 GPCHK: PCSEL0 (Bitfield-Mask: 0x0f) */ -#define CCU8_GPCHK_PCSEL1_Pos \ - (20UL) /*!< CCU8 GPCHK: PCSEL1 (Bit 20) */ -#define CCU8_GPCHK_PCSEL1_Msk \ - (0xf00000UL) /*!< CCU8 GPCHK: PCSEL1 (Bitfield-Mask: 0x0f) */ -#define CCU8_GPCHK_PCSEL2_Pos \ - (24UL) /*!< CCU8 GPCHK: PCSEL2 (Bit 24) */ -#define CCU8_GPCHK_PCSEL2_Msk \ - (0xf000000UL) /*!< CCU8 GPCHK: PCSEL2 (Bitfield-Mask: 0x0f) */ -#define CCU8_GPCHK_PCSEL3_Pos \ - (28UL) /*!< CCU8 GPCHK: PCSEL3 (Bit 28) */ -#define CCU8_GPCHK_PCSEL3_Msk \ - (0xf0000000UL) /*!< CCU8 GPCHK: PCSEL3 (Bitfield-Mask: 0x0f) */ - -/* ---------------------------------- CCU8_ECRD --------------------------------- */ -#define CCU8_ECRD_CAPV_Pos (0UL) /*!< CCU8 ECRD: CAPV (Bit 0) */ -#define CCU8_ECRD_CAPV_Msk \ - (0xffffUL) /*!< CCU8 ECRD: CAPV (Bitfield-Mask: 0xffff) */ -#define CCU8_ECRD_FPCV_Pos \ - (16UL) /*!< CCU8 ECRD: FPCV (Bit 16) */ -#define CCU8_ECRD_FPCV_Msk \ - (0xf0000UL) /*!< CCU8 ECRD: FPCV (Bitfield-Mask: 0x0f) */ -#define CCU8_ECRD_SPTR_Pos \ - (20UL) /*!< CCU8 ECRD: SPTR (Bit 20) */ -#define CCU8_ECRD_SPTR_Msk \ - (0x300000UL) /*!< CCU8 ECRD: SPTR (Bitfield-Mask: 0x03) */ -#define CCU8_ECRD_VPTR_Pos \ - (22UL) /*!< CCU8 ECRD: VPTR (Bit 22) */ -#define CCU8_ECRD_VPTR_Msk \ - (0xc00000UL) /*!< CCU8 ECRD: VPTR (Bitfield-Mask: 0x03) */ -#define CCU8_ECRD_FFL_Pos (24UL) /*!< CCU8 ECRD: FFL (Bit 24) */ -#define CCU8_ECRD_FFL_Msk \ - (0x1000000UL) /*!< CCU8 ECRD: FFL (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- CCU8_MIDR --------------------------------- */ -#define CCU8_MIDR_MODR_Pos (0UL) /*!< CCU8 MIDR: MODR (Bit 0) */ -#define CCU8_MIDR_MODR_Msk \ - (0xffUL) /*!< CCU8 MIDR: MODR (Bitfield-Mask: 0xff) */ -#define CCU8_MIDR_MODT_Pos (8UL) /*!< CCU8 MIDR: MODT (Bit 8) */ -#define CCU8_MIDR_MODT_Msk \ - (0xff00UL) /*!< CCU8 MIDR: MODT (Bitfield-Mask: 0xff) */ -#define CCU8_MIDR_MODN_Pos \ - (16UL) /*!< CCU8 MIDR: MODN (Bit 16) */ -#define CCU8_MIDR_MODN_Msk \ - (0xffff0000UL) /*!< CCU8 MIDR: MODN (Bitfield-Mask: 0xffff) */ - -/* ================================================================================ */ -/* ================ Group 'CCU8_CC8' Position & Mask ================ */ -/* ================================================================================ */ - -/* -------------------------------- CCU8_CC8_INS -------------------------------- */ -#define CCU8_CC8_INS_EV0IS_Pos \ - (0UL) /*!< CCU8_CC8 INS: EV0IS (Bit 0) */ -#define CCU8_CC8_INS_EV0IS_Msk \ - (0xfUL) /*!< CCU8_CC8 INS: EV0IS (Bitfield-Mask: 0x0f) */ -#define CCU8_CC8_INS_EV1IS_Pos \ - (4UL) /*!< CCU8_CC8 INS: EV1IS (Bit 4) */ -#define CCU8_CC8_INS_EV1IS_Msk \ - (0xf0UL) /*!< CCU8_CC8 INS: EV1IS (Bitfield-Mask: 0x0f) */ -#define CCU8_CC8_INS_EV2IS_Pos \ - (8UL) /*!< CCU8_CC8 INS: EV2IS (Bit 8) */ -#define CCU8_CC8_INS_EV2IS_Msk \ - (0xf00UL) /*!< CCU8_CC8 INS: EV2IS (Bitfield-Mask: 0x0f) */ -#define CCU8_CC8_INS_EV0EM_Pos \ - (16UL) /*!< CCU8_CC8 INS: EV0EM (Bit 16) */ -#define CCU8_CC8_INS_EV0EM_Msk \ - (0x30000UL) /*!< CCU8_CC8 INS: EV0EM (Bitfield-Mask: 0x03) */ -#define CCU8_CC8_INS_EV1EM_Pos \ - (18UL) /*!< CCU8_CC8 INS: EV1EM (Bit 18) */ -#define CCU8_CC8_INS_EV1EM_Msk \ - (0xc0000UL) /*!< CCU8_CC8 INS: EV1EM (Bitfield-Mask: 0x03) */ -#define CCU8_CC8_INS_EV2EM_Pos \ - (20UL) /*!< CCU8_CC8 INS: EV2EM (Bit 20) */ -#define CCU8_CC8_INS_EV2EM_Msk \ - (0x300000UL) /*!< CCU8_CC8 INS: EV2EM (Bitfield-Mask: 0x03) */ -#define CCU8_CC8_INS_EV0LM_Pos \ - (22UL) /*!< CCU8_CC8 INS: EV0LM (Bit 22) */ -#define CCU8_CC8_INS_EV0LM_Msk \ - (0x400000UL) /*!< CCU8_CC8 INS: EV0LM (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_INS_EV1LM_Pos \ - (23UL) /*!< CCU8_CC8 INS: EV1LM (Bit 23) */ -#define CCU8_CC8_INS_EV1LM_Msk \ - (0x800000UL) /*!< CCU8_CC8 INS: EV1LM (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_INS_EV2LM_Pos \ - (24UL) /*!< CCU8_CC8 INS: EV2LM (Bit 24) */ -#define CCU8_CC8_INS_EV2LM_Msk \ - (0x1000000UL) /*!< CCU8_CC8 INS: EV2LM (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_INS_LPF0M_Pos \ - (25UL) /*!< CCU8_CC8 INS: LPF0M (Bit 25) */ -#define CCU8_CC8_INS_LPF0M_Msk \ - (0x6000000UL) /*!< CCU8_CC8 INS: LPF0M (Bitfield-Mask: 0x03) */ -#define CCU8_CC8_INS_LPF1M_Pos \ - (27UL) /*!< CCU8_CC8 INS: LPF1M (Bit 27) */ -#define CCU8_CC8_INS_LPF1M_Msk \ - (0x18000000UL) /*!< CCU8_CC8 INS: LPF1M (Bitfield-Mask: 0x03) */ -#define CCU8_CC8_INS_LPF2M_Pos \ - (29UL) /*!< CCU8_CC8 INS: LPF2M (Bit 29) */ -#define CCU8_CC8_INS_LPF2M_Msk \ - (0x60000000UL) /*!< CCU8_CC8 INS: LPF2M (Bitfield-Mask: 0x03) */ - -/* -------------------------------- CCU8_CC8_CMC -------------------------------- */ -#define CCU8_CC8_CMC_STRTS_Pos \ - (0UL) /*!< CCU8_CC8 CMC: STRTS (Bit 0) */ -#define CCU8_CC8_CMC_STRTS_Msk \ - (0x3UL) /*!< CCU8_CC8 CMC: STRTS (Bitfield-Mask: 0x03) */ -#define CCU8_CC8_CMC_ENDS_Pos \ - (2UL) /*!< CCU8_CC8 CMC: ENDS (Bit 2) */ -#define CCU8_CC8_CMC_ENDS_Msk \ - (0xcUL) /*!< CCU8_CC8 CMC: ENDS (Bitfield-Mask: 0x03) */ -#define CCU8_CC8_CMC_CAP0S_Pos \ - (4UL) /*!< CCU8_CC8 CMC: CAP0S (Bit 4) */ -#define CCU8_CC8_CMC_CAP0S_Msk \ - (0x30UL) /*!< CCU8_CC8 CMC: CAP0S (Bitfield-Mask: 0x03) */ -#define CCU8_CC8_CMC_CAP1S_Pos \ - (6UL) /*!< CCU8_CC8 CMC: CAP1S (Bit 6) */ -#define CCU8_CC8_CMC_CAP1S_Msk \ - (0xc0UL) /*!< CCU8_CC8 CMC: CAP1S (Bitfield-Mask: 0x03) */ -#define CCU8_CC8_CMC_GATES_Pos \ - (8UL) /*!< CCU8_CC8 CMC: GATES (Bit 8) */ -#define CCU8_CC8_CMC_GATES_Msk \ - (0x300UL) /*!< CCU8_CC8 CMC: GATES (Bitfield-Mask: 0x03) */ -#define CCU8_CC8_CMC_UDS_Pos \ - (10UL) /*!< CCU8_CC8 CMC: UDS (Bit 10) */ -#define CCU8_CC8_CMC_UDS_Msk \ - (0xc00UL) /*!< CCU8_CC8 CMC: UDS (Bitfield-Mask: 0x03) */ -#define CCU8_CC8_CMC_LDS_Pos \ - (12UL) /*!< CCU8_CC8 CMC: LDS (Bit 12) */ -#define CCU8_CC8_CMC_LDS_Msk \ - (0x3000UL) /*!< CCU8_CC8 CMC: LDS (Bitfield-Mask: 0x03) */ -#define CCU8_CC8_CMC_CNTS_Pos \ - (14UL) /*!< CCU8_CC8 CMC: CNTS (Bit 14) */ -#define CCU8_CC8_CMC_CNTS_Msk \ - (0xc000UL) /*!< CCU8_CC8 CMC: CNTS (Bitfield-Mask: 0x03) */ -#define CCU8_CC8_CMC_OFS_Pos \ - (16UL) /*!< CCU8_CC8 CMC: OFS (Bit 16) */ -#define CCU8_CC8_CMC_OFS_Msk \ - (0x10000UL) /*!< CCU8_CC8 CMC: OFS (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_CMC_TS_Pos \ - (17UL) /*!< CCU8_CC8 CMC: TS (Bit 17) */ -#define CCU8_CC8_CMC_TS_Msk \ - (0x20000UL) /*!< CCU8_CC8 CMC: TS (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_CMC_MOS_Pos \ - (18UL) /*!< CCU8_CC8 CMC: MOS (Bit 18) */ -#define CCU8_CC8_CMC_MOS_Msk \ - (0xc0000UL) /*!< CCU8_CC8 CMC: MOS (Bitfield-Mask: 0x03) */ -#define CCU8_CC8_CMC_TCE_Pos \ - (20UL) /*!< CCU8_CC8 CMC: TCE (Bit 20) */ -#define CCU8_CC8_CMC_TCE_Msk \ - (0x100000UL) /*!< CCU8_CC8 CMC: TCE (Bitfield-Mask: 0x01) */ - -/* -------------------------------- CCU8_CC8_TCST ------------------------------- */ -#define CCU8_CC8_TCST_TRB_Pos \ - (0UL) /*!< CCU8_CC8 TCST: TRB (Bit 0) */ -#define CCU8_CC8_TCST_TRB_Msk \ - (0x1UL) /*!< CCU8_CC8 TCST: TRB (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TCST_CDIR_Pos \ - (1UL) /*!< CCU8_CC8 TCST: CDIR (Bit 1) */ -#define CCU8_CC8_TCST_CDIR_Msk \ - (0x2UL) /*!< CCU8_CC8 TCST: CDIR (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TCST_DTR1_Pos \ - (3UL) /*!< CCU8_CC8 TCST: DTR1 (Bit 3) */ -#define CCU8_CC8_TCST_DTR1_Msk \ - (0x8UL) /*!< CCU8_CC8 TCST: DTR1 (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TCST_DTR2_Pos \ - (4UL) /*!< CCU8_CC8 TCST: DTR2 (Bit 4) */ -#define CCU8_CC8_TCST_DTR2_Msk \ - (0x10UL) /*!< CCU8_CC8 TCST: DTR2 (Bitfield-Mask: 0x01) */ - -/* ------------------------------- CCU8_CC8_TCSET ------------------------------- */ -#define CCU8_CC8_TCSET_TRBS_Pos \ - (0UL) /*!< CCU8_CC8 TCSET: TRBS (Bit 0) */ -#define CCU8_CC8_TCSET_TRBS_Msk \ - (0x1UL) /*!< CCU8_CC8 TCSET: TRBS (Bitfield-Mask: 0x01) */ - -/* ------------------------------- CCU8_CC8_TCCLR ------------------------------- */ -#define CCU8_CC8_TCCLR_TRBC_Pos \ - (0UL) /*!< CCU8_CC8 TCCLR: TRBC (Bit 0) */ -#define CCU8_CC8_TCCLR_TRBC_Msk \ - (0x1UL) /*!< CCU8_CC8 TCCLR: TRBC (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TCCLR_TCC_Pos \ - (1UL) /*!< CCU8_CC8 TCCLR: TCC (Bit 1) */ -#define CCU8_CC8_TCCLR_TCC_Msk \ - (0x2UL) /*!< CCU8_CC8 TCCLR: TCC (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TCCLR_DITC_Pos \ - (2UL) /*!< CCU8_CC8 TCCLR: DITC (Bit 2) */ -#define CCU8_CC8_TCCLR_DITC_Msk \ - (0x4UL) /*!< CCU8_CC8 TCCLR: DITC (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TCCLR_DTC1C_Pos \ - (3UL) /*!< CCU8_CC8 TCCLR: DTC1C (Bit 3) */ -#define CCU8_CC8_TCCLR_DTC1C_Msk \ - (0x8UL) /*!< CCU8_CC8 TCCLR: DTC1C (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TCCLR_DTC2C_Pos \ - (4UL) /*!< CCU8_CC8 TCCLR: DTC2C (Bit 4) */ -#define CCU8_CC8_TCCLR_DTC2C_Msk \ - (0x10UL) /*!< CCU8_CC8 TCCLR: DTC2C (Bitfield-Mask: 0x01) */ - -/* --------------------------------- CCU8_CC8_TC -------------------------------- */ -#define CCU8_CC8_TC_TCM_Pos \ - (0UL) /*!< CCU8_CC8 TC: TCM (Bit 0) */ -#define CCU8_CC8_TC_TCM_Msk \ - (0x1UL) /*!< CCU8_CC8 TC: TCM (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TC_TSSM_Pos \ - (1UL) /*!< CCU8_CC8 TC: TSSM (Bit 1) */ -#define CCU8_CC8_TC_TSSM_Msk \ - (0x2UL) /*!< CCU8_CC8 TC: TSSM (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TC_CLST_Pos \ - (2UL) /*!< CCU8_CC8 TC: CLST (Bit 2) */ -#define CCU8_CC8_TC_CLST_Msk \ - (0x4UL) /*!< CCU8_CC8 TC: CLST (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TC_CMOD_Pos \ - (3UL) /*!< CCU8_CC8 TC: CMOD (Bit 3) */ -#define CCU8_CC8_TC_CMOD_Msk \ - (0x8UL) /*!< CCU8_CC8 TC: CMOD (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TC_ECM_Pos \ - (4UL) /*!< CCU8_CC8 TC: ECM (Bit 4) */ -#define CCU8_CC8_TC_ECM_Msk \ - (0x10UL) /*!< CCU8_CC8 TC: ECM (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TC_CAPC_Pos \ - (5UL) /*!< CCU8_CC8 TC: CAPC (Bit 5) */ -#define CCU8_CC8_TC_CAPC_Msk \ - (0x60UL) /*!< CCU8_CC8 TC: CAPC (Bitfield-Mask: 0x03) */ -#define CCU8_CC8_TC_TLS_Pos \ - (7UL) /*!< CCU8_CC8 TC: TLS (Bit 7) */ -#define CCU8_CC8_TC_TLS_Msk \ - (0x80UL) /*!< CCU8_CC8 TC: TLS (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TC_ENDM_Pos \ - (8UL) /*!< CCU8_CC8 TC: ENDM (Bit 8) */ -#define CCU8_CC8_TC_ENDM_Msk \ - (0x300UL) /*!< CCU8_CC8 TC: ENDM (Bitfield-Mask: 0x03) */ -#define CCU8_CC8_TC_STRM_Pos \ - (10UL) /*!< CCU8_CC8 TC: STRM (Bit 10) */ -#define CCU8_CC8_TC_STRM_Msk \ - (0x400UL) /*!< CCU8_CC8 TC: STRM (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TC_SCE_Pos \ - (11UL) /*!< CCU8_CC8 TC: SCE (Bit 11) */ -#define CCU8_CC8_TC_SCE_Msk \ - (0x800UL) /*!< CCU8_CC8 TC: SCE (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TC_CCS_Pos \ - (12UL) /*!< CCU8_CC8 TC: CCS (Bit 12) */ -#define CCU8_CC8_TC_CCS_Msk \ - (0x1000UL) /*!< CCU8_CC8 TC: CCS (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TC_DITHE_Pos \ - (13UL) /*!< CCU8_CC8 TC: DITHE (Bit 13) */ -#define CCU8_CC8_TC_DITHE_Msk \ - (0x6000UL) /*!< CCU8_CC8 TC: DITHE (Bitfield-Mask: 0x03) */ -#define CCU8_CC8_TC_DIM_Pos \ - (15UL) /*!< CCU8_CC8 TC: DIM (Bit 15) */ -#define CCU8_CC8_TC_DIM_Msk \ - (0x8000UL) /*!< CCU8_CC8 TC: DIM (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TC_FPE_Pos \ - (16UL) /*!< CCU8_CC8 TC: FPE (Bit 16) */ -#define CCU8_CC8_TC_FPE_Msk \ - (0x10000UL) /*!< CCU8_CC8 TC: FPE (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TC_TRAPE0_Pos \ - (17UL) /*!< CCU8_CC8 TC: TRAPE0 (Bit 17) */ -#define CCU8_CC8_TC_TRAPE0_Msk \ - (0x20000UL) /*!< CCU8_CC8 TC: TRAPE0 (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TC_TRAPE1_Pos \ - (18UL) /*!< CCU8_CC8 TC: TRAPE1 (Bit 18) */ -#define CCU8_CC8_TC_TRAPE1_Msk \ - (0x40000UL) /*!< CCU8_CC8 TC: TRAPE1 (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TC_TRAPE2_Pos \ - (19UL) /*!< CCU8_CC8 TC: TRAPE2 (Bit 19) */ -#define CCU8_CC8_TC_TRAPE2_Msk \ - (0x80000UL) /*!< CCU8_CC8 TC: TRAPE2 (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TC_TRAPE3_Pos \ - (20UL) /*!< CCU8_CC8 TC: TRAPE3 (Bit 20) */ -#define CCU8_CC8_TC_TRAPE3_Msk \ - (0x100000UL) /*!< CCU8_CC8 TC: TRAPE3 (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TC_TRPSE_Pos \ - (21UL) /*!< CCU8_CC8 TC: TRPSE (Bit 21) */ -#define CCU8_CC8_TC_TRPSE_Msk \ - (0x200000UL) /*!< CCU8_CC8 TC: TRPSE (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TC_TRPSW_Pos \ - (22UL) /*!< CCU8_CC8 TC: TRPSW (Bit 22) */ -#define CCU8_CC8_TC_TRPSW_Msk \ - (0x400000UL) /*!< CCU8_CC8 TC: TRPSW (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TC_EMS_Pos \ - (23UL) /*!< CCU8_CC8 TC: EMS (Bit 23) */ -#define CCU8_CC8_TC_EMS_Msk \ - (0x800000UL) /*!< CCU8_CC8 TC: EMS (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TC_EMT_Pos \ - (24UL) /*!< CCU8_CC8 TC: EMT (Bit 24) */ -#define CCU8_CC8_TC_EMT_Msk \ - (0x1000000UL) /*!< CCU8_CC8 TC: EMT (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TC_MCME1_Pos \ - (25UL) /*!< CCU8_CC8 TC: MCME1 (Bit 25) */ -#define CCU8_CC8_TC_MCME1_Msk \ - (0x2000000UL) /*!< CCU8_CC8 TC: MCME1 (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TC_MCME2_Pos \ - (26UL) /*!< CCU8_CC8 TC: MCME2 (Bit 26) */ -#define CCU8_CC8_TC_MCME2_Msk \ - (0x4000000UL) /*!< CCU8_CC8 TC: MCME2 (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TC_EME_Pos \ - (27UL) /*!< CCU8_CC8 TC: EME (Bit 27) */ -#define CCU8_CC8_TC_EME_Msk \ - (0x18000000UL) /*!< CCU8_CC8 TC: EME (Bitfield-Mask: 0x03) */ -#define CCU8_CC8_TC_STOS_Pos \ - (29UL) /*!< CCU8_CC8 TC: STOS (Bit 29) */ -#define CCU8_CC8_TC_STOS_Msk \ - (0x60000000UL) /*!< CCU8_CC8 TC: STOS (Bitfield-Mask: 0x03) */ - -/* -------------------------------- CCU8_CC8_PSL -------------------------------- */ -#define CCU8_CC8_PSL_PSL11_Pos \ - (0UL) /*!< CCU8_CC8 PSL: PSL11 (Bit 0) */ -#define CCU8_CC8_PSL_PSL11_Msk \ - (0x1UL) /*!< CCU8_CC8 PSL: PSL11 (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_PSL_PSL12_Pos \ - (1UL) /*!< CCU8_CC8 PSL: PSL12 (Bit 1) */ -#define CCU8_CC8_PSL_PSL12_Msk \ - (0x2UL) /*!< CCU8_CC8 PSL: PSL12 (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_PSL_PSL21_Pos \ - (2UL) /*!< CCU8_CC8 PSL: PSL21 (Bit 2) */ -#define CCU8_CC8_PSL_PSL21_Msk \ - (0x4UL) /*!< CCU8_CC8 PSL: PSL21 (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_PSL_PSL22_Pos \ - (3UL) /*!< CCU8_CC8 PSL: PSL22 (Bit 3) */ -#define CCU8_CC8_PSL_PSL22_Msk \ - (0x8UL) /*!< CCU8_CC8 PSL: PSL22 (Bitfield-Mask: 0x01) */ - -/* -------------------------------- CCU8_CC8_DIT -------------------------------- */ -#define CCU8_CC8_DIT_DCV_Pos \ - (0UL) /*!< CCU8_CC8 DIT: DCV (Bit 0) */ -#define CCU8_CC8_DIT_DCV_Msk \ - (0xfUL) /*!< CCU8_CC8 DIT: DCV (Bitfield-Mask: 0x0f) */ -#define CCU8_CC8_DIT_DCNT_Pos \ - (8UL) /*!< CCU8_CC8 DIT: DCNT (Bit 8) */ -#define CCU8_CC8_DIT_DCNT_Msk \ - (0xf00UL) /*!< CCU8_CC8 DIT: DCNT (Bitfield-Mask: 0x0f) */ - -/* -------------------------------- CCU8_CC8_DITS ------------------------------- */ -#define CCU8_CC8_DITS_DCVS_Pos \ - (0UL) /*!< CCU8_CC8 DITS: DCVS (Bit 0) */ -#define CCU8_CC8_DITS_DCVS_Msk \ - (0xfUL) /*!< CCU8_CC8 DITS: DCVS (Bitfield-Mask: 0x0f) */ - -/* -------------------------------- CCU8_CC8_PSC -------------------------------- */ -#define CCU8_CC8_PSC_PSIV_Pos \ - (0UL) /*!< CCU8_CC8 PSC: PSIV (Bit 0) */ -#define CCU8_CC8_PSC_PSIV_Msk \ - (0xfUL) /*!< CCU8_CC8 PSC: PSIV (Bitfield-Mask: 0x0f) */ - -/* -------------------------------- CCU8_CC8_FPC -------------------------------- */ -#define CCU8_CC8_FPC_PCMP_Pos \ - (0UL) /*!< CCU8_CC8 FPC: PCMP (Bit 0) */ -#define CCU8_CC8_FPC_PCMP_Msk \ - (0xfUL) /*!< CCU8_CC8 FPC: PCMP (Bitfield-Mask: 0x0f) */ -#define CCU8_CC8_FPC_PVAL_Pos \ - (8UL) /*!< CCU8_CC8 FPC: PVAL (Bit 8) */ -#define CCU8_CC8_FPC_PVAL_Msk \ - (0xf00UL) /*!< CCU8_CC8 FPC: PVAL (Bitfield-Mask: 0x0f) */ - -/* -------------------------------- CCU8_CC8_FPCS ------------------------------- */ -#define CCU8_CC8_FPCS_PCMP_Pos \ - (0UL) /*!< CCU8_CC8 FPCS: PCMP (Bit 0) */ -#define CCU8_CC8_FPCS_PCMP_Msk \ - (0xfUL) /*!< CCU8_CC8 FPCS: PCMP (Bitfield-Mask: 0x0f) */ - -/* --------------------------------- CCU8_CC8_PR -------------------------------- */ -#define CCU8_CC8_PR_PR_Pos (0UL) /*!< CCU8_CC8 PR: PR (Bit 0) */ -#define CCU8_CC8_PR_PR_Msk \ - (0xffffUL) /*!< CCU8_CC8 PR: PR (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- CCU8_CC8_PRS -------------------------------- */ -#define CCU8_CC8_PRS_PRS_Pos \ - (0UL) /*!< CCU8_CC8 PRS: PRS (Bit 0) */ -#define CCU8_CC8_PRS_PRS_Msk \ - (0xffffUL) /*!< CCU8_CC8 PRS: PRS (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- CCU8_CC8_CR1 -------------------------------- */ -#define CCU8_CC8_CR1_CR1_Pos \ - (0UL) /*!< CCU8_CC8 CR1: CR1 (Bit 0) */ -#define CCU8_CC8_CR1_CR1_Msk \ - (0xffffUL) /*!< CCU8_CC8 CR1: CR1 (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- CCU8_CC8_CR1S ------------------------------- */ -#define CCU8_CC8_CR1S_CR1S_Pos \ - (0UL) /*!< CCU8_CC8 CR1S: CR1S (Bit 0) */ -#define CCU8_CC8_CR1S_CR1S_Msk \ - (0xffffUL) /*!< CCU8_CC8 CR1S: CR1S (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- CCU8_CC8_CR2 -------------------------------- */ -#define CCU8_CC8_CR2_CR2_Pos \ - (0UL) /*!< CCU8_CC8 CR2: CR2 (Bit 0) */ -#define CCU8_CC8_CR2_CR2_Msk \ - (0xffffUL) /*!< CCU8_CC8 CR2: CR2 (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- CCU8_CC8_CR2S ------------------------------- */ -#define CCU8_CC8_CR2S_CR2S_Pos \ - (0UL) /*!< CCU8_CC8 CR2S: CR2S (Bit 0) */ -#define CCU8_CC8_CR2S_CR2S_Msk \ - (0xffffUL) /*!< CCU8_CC8 CR2S: CR2S (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- CCU8_CC8_CHC -------------------------------- */ -#define CCU8_CC8_CHC_ASE_Pos \ - (0UL) /*!< CCU8_CC8 CHC: ASE (Bit 0) */ -#define CCU8_CC8_CHC_ASE_Msk \ - (0x1UL) /*!< CCU8_CC8 CHC: ASE (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_CHC_OCS1_Pos \ - (1UL) /*!< CCU8_CC8 CHC: OCS1 (Bit 1) */ -#define CCU8_CC8_CHC_OCS1_Msk \ - (0x2UL) /*!< CCU8_CC8 CHC: OCS1 (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_CHC_OCS2_Pos \ - (2UL) /*!< CCU8_CC8 CHC: OCS2 (Bit 2) */ -#define CCU8_CC8_CHC_OCS2_Msk \ - (0x4UL) /*!< CCU8_CC8 CHC: OCS2 (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_CHC_OCS3_Pos \ - (3UL) /*!< CCU8_CC8 CHC: OCS3 (Bit 3) */ -#define CCU8_CC8_CHC_OCS3_Msk \ - (0x8UL) /*!< CCU8_CC8 CHC: OCS3 (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_CHC_OCS4_Pos \ - (4UL) /*!< CCU8_CC8 CHC: OCS4 (Bit 4) */ -#define CCU8_CC8_CHC_OCS4_Msk \ - (0x10UL) /*!< CCU8_CC8 CHC: OCS4 (Bitfield-Mask: 0x01) */ - -/* -------------------------------- CCU8_CC8_DTC -------------------------------- */ -#define CCU8_CC8_DTC_DTE1_Pos \ - (0UL) /*!< CCU8_CC8 DTC: DTE1 (Bit 0) */ -#define CCU8_CC8_DTC_DTE1_Msk \ - (0x1UL) /*!< CCU8_CC8 DTC: DTE1 (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_DTC_DTE2_Pos \ - (1UL) /*!< CCU8_CC8 DTC: DTE2 (Bit 1) */ -#define CCU8_CC8_DTC_DTE2_Msk \ - (0x2UL) /*!< CCU8_CC8 DTC: DTE2 (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_DTC_DCEN1_Pos \ - (2UL) /*!< CCU8_CC8 DTC: DCEN1 (Bit 2) */ -#define CCU8_CC8_DTC_DCEN1_Msk \ - (0x4UL) /*!< CCU8_CC8 DTC: DCEN1 (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_DTC_DCEN2_Pos \ - (3UL) /*!< CCU8_CC8 DTC: DCEN2 (Bit 3) */ -#define CCU8_CC8_DTC_DCEN2_Msk \ - (0x8UL) /*!< CCU8_CC8 DTC: DCEN2 (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_DTC_DCEN3_Pos \ - (4UL) /*!< CCU8_CC8 DTC: DCEN3 (Bit 4) */ -#define CCU8_CC8_DTC_DCEN3_Msk \ - (0x10UL) /*!< CCU8_CC8 DTC: DCEN3 (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_DTC_DCEN4_Pos \ - (5UL) /*!< CCU8_CC8 DTC: DCEN4 (Bit 5) */ -#define CCU8_CC8_DTC_DCEN4_Msk \ - (0x20UL) /*!< CCU8_CC8 DTC: DCEN4 (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_DTC_DTCC_Pos \ - (6UL) /*!< CCU8_CC8 DTC: DTCC (Bit 6) */ -#define CCU8_CC8_DTC_DTCC_Msk \ - (0xc0UL) /*!< CCU8_CC8 DTC: DTCC (Bitfield-Mask: 0x03) */ - -/* -------------------------------- CCU8_CC8_DC1R ------------------------------- */ -#define CCU8_CC8_DC1R_DT1R_Pos \ - (0UL) /*!< CCU8_CC8 DC1R: DT1R (Bit 0) */ -#define CCU8_CC8_DC1R_DT1R_Msk \ - (0xffUL) /*!< CCU8_CC8 DC1R: DT1R (Bitfield-Mask: 0xff) */ -#define CCU8_CC8_DC1R_DT1F_Pos \ - (8UL) /*!< CCU8_CC8 DC1R: DT1F (Bit 8) */ -#define CCU8_CC8_DC1R_DT1F_Msk \ - (0xff00UL) /*!< CCU8_CC8 DC1R: DT1F (Bitfield-Mask: 0xff) */ - -/* -------------------------------- CCU8_CC8_DC2R ------------------------------- */ -#define CCU8_CC8_DC2R_DT2R_Pos \ - (0UL) /*!< CCU8_CC8 DC2R: DT2R (Bit 0) */ -#define CCU8_CC8_DC2R_DT2R_Msk \ - (0xffUL) /*!< CCU8_CC8 DC2R: DT2R (Bitfield-Mask: 0xff) */ -#define CCU8_CC8_DC2R_DT2F_Pos \ - (8UL) /*!< CCU8_CC8 DC2R: DT2F (Bit 8) */ -#define CCU8_CC8_DC2R_DT2F_Msk \ - (0xff00UL) /*!< CCU8_CC8 DC2R: DT2F (Bitfield-Mask: 0xff) */ - -/* ------------------------------- CCU8_CC8_TIMER ------------------------------- */ -#define CCU8_CC8_TIMER_TVAL_Pos \ - (0UL) /*!< CCU8_CC8 TIMER: TVAL (Bit 0) */ -#define CCU8_CC8_TIMER_TVAL_Msk \ - (0xffffUL) /*!< CCU8_CC8 TIMER: TVAL (Bitfield-Mask: 0xffff) */ - -/* --------------------------------- CCU8_CC8_CV -------------------------------- */ -#define CCU8_CC8_CV_CAPTV_Pos \ - (0UL) /*!< CCU8_CC8 CV: CAPTV (Bit 0) */ -#define CCU8_CC8_CV_CAPTV_Msk \ - (0xffffUL) /*!< CCU8_CC8 CV: CAPTV (Bitfield-Mask: 0xffff) */ -#define CCU8_CC8_CV_FPCV_Pos \ - (16UL) /*!< CCU8_CC8 CV: FPCV (Bit 16) */ -#define CCU8_CC8_CV_FPCV_Msk \ - (0xf0000UL) /*!< CCU8_CC8 CV: FPCV (Bitfield-Mask: 0x0f) */ -#define CCU8_CC8_CV_FFL_Pos \ - (20UL) /*!< CCU8_CC8 CV: FFL (Bit 20) */ -#define CCU8_CC8_CV_FFL_Msk \ - (0x100000UL) /*!< CCU8_CC8 CV: FFL (Bitfield-Mask: 0x01) */ - -/* -------------------------------- CCU8_CC8_INTS ------------------------------- */ -#define CCU8_CC8_INTS_PMUS_Pos \ - (0UL) /*!< CCU8_CC8 INTS: PMUS (Bit 0) */ -#define CCU8_CC8_INTS_PMUS_Msk \ - (0x1UL) /*!< CCU8_CC8 INTS: PMUS (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_INTS_OMDS_Pos \ - (1UL) /*!< CCU8_CC8 INTS: OMDS (Bit 1) */ -#define CCU8_CC8_INTS_OMDS_Msk \ - (0x2UL) /*!< CCU8_CC8 INTS: OMDS (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_INTS_CMU1S_Pos \ - (2UL) /*!< CCU8_CC8 INTS: CMU1S (Bit 2) */ -#define CCU8_CC8_INTS_CMU1S_Msk \ - (0x4UL) /*!< CCU8_CC8 INTS: CMU1S (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_INTS_CMD1S_Pos \ - (3UL) /*!< CCU8_CC8 INTS: CMD1S (Bit 3) */ -#define CCU8_CC8_INTS_CMD1S_Msk \ - (0x8UL) /*!< CCU8_CC8 INTS: CMD1S (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_INTS_CMU2S_Pos \ - (4UL) /*!< CCU8_CC8 INTS: CMU2S (Bit 4) */ -#define CCU8_CC8_INTS_CMU2S_Msk \ - (0x10UL) /*!< CCU8_CC8 INTS: CMU2S (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_INTS_CMD2S_Pos \ - (5UL) /*!< CCU8_CC8 INTS: CMD2S (Bit 5) */ -#define CCU8_CC8_INTS_CMD2S_Msk \ - (0x20UL) /*!< CCU8_CC8 INTS: CMD2S (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_INTS_E0AS_Pos \ - (8UL) /*!< CCU8_CC8 INTS: E0AS (Bit 8) */ -#define CCU8_CC8_INTS_E0AS_Msk \ - (0x100UL) /*!< CCU8_CC8 INTS: E0AS (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_INTS_E1AS_Pos \ - (9UL) /*!< CCU8_CC8 INTS: E1AS (Bit 9) */ -#define CCU8_CC8_INTS_E1AS_Msk \ - (0x200UL) /*!< CCU8_CC8 INTS: E1AS (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_INTS_E2AS_Pos \ - (10UL) /*!< CCU8_CC8 INTS: E2AS (Bit 10) */ -#define CCU8_CC8_INTS_E2AS_Msk \ - (0x400UL) /*!< CCU8_CC8 INTS: E2AS (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_INTS_TRPF_Pos \ - (11UL) /*!< CCU8_CC8 INTS: TRPF (Bit 11) */ -#define CCU8_CC8_INTS_TRPF_Msk \ - (0x800UL) /*!< CCU8_CC8 INTS: TRPF (Bitfield-Mask: 0x01) */ - -/* -------------------------------- CCU8_CC8_INTE ------------------------------- */ -#define CCU8_CC8_INTE_PME_Pos \ - (0UL) /*!< CCU8_CC8 INTE: PME (Bit 0) */ -#define CCU8_CC8_INTE_PME_Msk \ - (0x1UL) /*!< CCU8_CC8 INTE: PME (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_INTE_OME_Pos \ - (1UL) /*!< CCU8_CC8 INTE: OME (Bit 1) */ -#define CCU8_CC8_INTE_OME_Msk \ - (0x2UL) /*!< CCU8_CC8 INTE: OME (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_INTE_CMU1E_Pos \ - (2UL) /*!< CCU8_CC8 INTE: CMU1E (Bit 2) */ -#define CCU8_CC8_INTE_CMU1E_Msk \ - (0x4UL) /*!< CCU8_CC8 INTE: CMU1E (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_INTE_CMD1E_Pos \ - (3UL) /*!< CCU8_CC8 INTE: CMD1E (Bit 3) */ -#define CCU8_CC8_INTE_CMD1E_Msk \ - (0x8UL) /*!< CCU8_CC8 INTE: CMD1E (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_INTE_CMU2E_Pos \ - (4UL) /*!< CCU8_CC8 INTE: CMU2E (Bit 4) */ -#define CCU8_CC8_INTE_CMU2E_Msk \ - (0x10UL) /*!< CCU8_CC8 INTE: CMU2E (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_INTE_CMD2E_Pos \ - (5UL) /*!< CCU8_CC8 INTE: CMD2E (Bit 5) */ -#define CCU8_CC8_INTE_CMD2E_Msk \ - (0x20UL) /*!< CCU8_CC8 INTE: CMD2E (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_INTE_E0AE_Pos \ - (8UL) /*!< CCU8_CC8 INTE: E0AE (Bit 8) */ -#define CCU8_CC8_INTE_E0AE_Msk \ - (0x100UL) /*!< CCU8_CC8 INTE: E0AE (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_INTE_E1AE_Pos \ - (9UL) /*!< CCU8_CC8 INTE: E1AE (Bit 9) */ -#define CCU8_CC8_INTE_E1AE_Msk \ - (0x200UL) /*!< CCU8_CC8 INTE: E1AE (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_INTE_E2AE_Pos \ - (10UL) /*!< CCU8_CC8 INTE: E2AE (Bit 10) */ -#define CCU8_CC8_INTE_E2AE_Msk \ - (0x400UL) /*!< CCU8_CC8 INTE: E2AE (Bitfield-Mask: 0x01) */ - -/* -------------------------------- CCU8_CC8_SRS -------------------------------- */ -#define CCU8_CC8_SRS_POSR_Pos \ - (0UL) /*!< CCU8_CC8 SRS: POSR (Bit 0) */ -#define CCU8_CC8_SRS_POSR_Msk \ - (0x3UL) /*!< CCU8_CC8 SRS: POSR (Bitfield-Mask: 0x03) */ -#define CCU8_CC8_SRS_CM1SR_Pos \ - (2UL) /*!< CCU8_CC8 SRS: CM1SR (Bit 2) */ -#define CCU8_CC8_SRS_CM1SR_Msk \ - (0xcUL) /*!< CCU8_CC8 SRS: CM1SR (Bitfield-Mask: 0x03) */ -#define CCU8_CC8_SRS_CM2SR_Pos \ - (4UL) /*!< CCU8_CC8 SRS: CM2SR (Bit 4) */ -#define CCU8_CC8_SRS_CM2SR_Msk \ - (0x30UL) /*!< CCU8_CC8 SRS: CM2SR (Bitfield-Mask: 0x03) */ -#define CCU8_CC8_SRS_E0SR_Pos \ - (8UL) /*!< CCU8_CC8 SRS: E0SR (Bit 8) */ -#define CCU8_CC8_SRS_E0SR_Msk \ - (0x300UL) /*!< CCU8_CC8 SRS: E0SR (Bitfield-Mask: 0x03) */ -#define CCU8_CC8_SRS_E1SR_Pos \ - (10UL) /*!< CCU8_CC8 SRS: E1SR (Bit 10) */ -#define CCU8_CC8_SRS_E1SR_Msk \ - (0xc00UL) /*!< CCU8_CC8 SRS: E1SR (Bitfield-Mask: 0x03) */ -#define CCU8_CC8_SRS_E2SR_Pos \ - (12UL) /*!< CCU8_CC8 SRS: E2SR (Bit 12) */ -#define CCU8_CC8_SRS_E2SR_Msk \ - (0x3000UL) /*!< CCU8_CC8 SRS: E2SR (Bitfield-Mask: 0x03) */ - -/* -------------------------------- CCU8_CC8_SWS -------------------------------- */ -#define CCU8_CC8_SWS_SPM_Pos \ - (0UL) /*!< CCU8_CC8 SWS: SPM (Bit 0) */ -#define CCU8_CC8_SWS_SPM_Msk \ - (0x1UL) /*!< CCU8_CC8 SWS: SPM (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_SWS_SOM_Pos \ - (1UL) /*!< CCU8_CC8 SWS: SOM (Bit 1) */ -#define CCU8_CC8_SWS_SOM_Msk \ - (0x2UL) /*!< CCU8_CC8 SWS: SOM (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_SWS_SCM1U_Pos \ - (2UL) /*!< CCU8_CC8 SWS: SCM1U (Bit 2) */ -#define CCU8_CC8_SWS_SCM1U_Msk \ - (0x4UL) /*!< CCU8_CC8 SWS: SCM1U (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_SWS_SCM1D_Pos \ - (3UL) /*!< CCU8_CC8 SWS: SCM1D (Bit 3) */ -#define CCU8_CC8_SWS_SCM1D_Msk \ - (0x8UL) /*!< CCU8_CC8 SWS: SCM1D (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_SWS_SCM2U_Pos \ - (4UL) /*!< CCU8_CC8 SWS: SCM2U (Bit 4) */ -#define CCU8_CC8_SWS_SCM2U_Msk \ - (0x10UL) /*!< CCU8_CC8 SWS: SCM2U (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_SWS_SCM2D_Pos \ - (5UL) /*!< CCU8_CC8 SWS: SCM2D (Bit 5) */ -#define CCU8_CC8_SWS_SCM2D_Msk \ - (0x20UL) /*!< CCU8_CC8 SWS: SCM2D (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_SWS_SE0A_Pos \ - (8UL) /*!< CCU8_CC8 SWS: SE0A (Bit 8) */ -#define CCU8_CC8_SWS_SE0A_Msk \ - (0x100UL) /*!< CCU8_CC8 SWS: SE0A (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_SWS_SE1A_Pos \ - (9UL) /*!< CCU8_CC8 SWS: SE1A (Bit 9) */ -#define CCU8_CC8_SWS_SE1A_Msk \ - (0x200UL) /*!< CCU8_CC8 SWS: SE1A (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_SWS_SE2A_Pos \ - (10UL) /*!< CCU8_CC8 SWS: SE2A (Bit 10) */ -#define CCU8_CC8_SWS_SE2A_Msk \ - (0x400UL) /*!< CCU8_CC8 SWS: SE2A (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_SWS_STRPF_Pos \ - (11UL) /*!< CCU8_CC8 SWS: STRPF (Bit 11) */ -#define CCU8_CC8_SWS_STRPF_Msk \ - (0x800UL) /*!< CCU8_CC8 SWS: STRPF (Bitfield-Mask: 0x01) */ - -/* -------------------------------- CCU8_CC8_SWR -------------------------------- */ -#define CCU8_CC8_SWR_RPM_Pos \ - (0UL) /*!< CCU8_CC8 SWR: RPM (Bit 0) */ -#define CCU8_CC8_SWR_RPM_Msk \ - (0x1UL) /*!< CCU8_CC8 SWR: RPM (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_SWR_ROM_Pos \ - (1UL) /*!< CCU8_CC8 SWR: ROM (Bit 1) */ -#define CCU8_CC8_SWR_ROM_Msk \ - (0x2UL) /*!< CCU8_CC8 SWR: ROM (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_SWR_RCM1U_Pos \ - (2UL) /*!< CCU8_CC8 SWR: RCM1U (Bit 2) */ -#define CCU8_CC8_SWR_RCM1U_Msk \ - (0x4UL) /*!< CCU8_CC8 SWR: RCM1U (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_SWR_RCM1D_Pos \ - (3UL) /*!< CCU8_CC8 SWR: RCM1D (Bit 3) */ -#define CCU8_CC8_SWR_RCM1D_Msk \ - (0x8UL) /*!< CCU8_CC8 SWR: RCM1D (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_SWR_RCM2U_Pos \ - (4UL) /*!< CCU8_CC8 SWR: RCM2U (Bit 4) */ -#define CCU8_CC8_SWR_RCM2U_Msk \ - (0x10UL) /*!< CCU8_CC8 SWR: RCM2U (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_SWR_RCM2D_Pos \ - (5UL) /*!< CCU8_CC8 SWR: RCM2D (Bit 5) */ -#define CCU8_CC8_SWR_RCM2D_Msk \ - (0x20UL) /*!< CCU8_CC8 SWR: RCM2D (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_SWR_RE0A_Pos \ - (8UL) /*!< CCU8_CC8 SWR: RE0A (Bit 8) */ -#define CCU8_CC8_SWR_RE0A_Msk \ - (0x100UL) /*!< CCU8_CC8 SWR: RE0A (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_SWR_RE1A_Pos \ - (9UL) /*!< CCU8_CC8 SWR: RE1A (Bit 9) */ -#define CCU8_CC8_SWR_RE1A_Msk \ - (0x200UL) /*!< CCU8_CC8 SWR: RE1A (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_SWR_RE2A_Pos \ - (10UL) /*!< CCU8_CC8 SWR: RE2A (Bit 10) */ -#define CCU8_CC8_SWR_RE2A_Msk \ - (0x400UL) /*!< CCU8_CC8 SWR: RE2A (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_SWR_RTRPF_Pos \ - (11UL) /*!< CCU8_CC8 SWR: RTRPF (Bit 11) */ -#define CCU8_CC8_SWR_RTRPF_Msk \ - (0x800UL) /*!< CCU8_CC8 SWR: RTRPF (Bitfield-Mask: 0x01) */ - -/* -------------------------------- CCU8_CC8_STC -------------------------------- */ -#define CCU8_CC8_STC_CSE_Pos \ - (0UL) /*!< CCU8_CC8 STC: CSE (Bit 0) */ -#define CCU8_CC8_STC_CSE_Msk \ - (0x1UL) /*!< CCU8_CC8 STC: CSE (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_STC_STM_Pos \ - (1UL) /*!< CCU8_CC8 STC: STM (Bit 1) */ -#define CCU8_CC8_STC_STM_Msk \ - (0x6UL) /*!< CCU8_CC8 STC: STM (Bitfield-Mask: 0x03) */ - -/* ================================================================================ */ -/* ================ struct 'HRPWM0' Position & Mask ================ */ -/* ================================================================================ */ - -/* -------------------------------- HRPWM0_HRBSC -------------------------------- */ -#define HRPWM0_HRBSC_SUSCFG_Pos \ - (0UL) /*!< HRPWM0 HRBSC: SUSCFG (Bit 0) */ -#define HRPWM0_HRBSC_SUSCFG_Msk \ - (0x7UL) /*!< HRPWM0 HRBSC: SUSCFG (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRBSC_HRBE_Pos \ - (8UL) /*!< HRPWM0 HRBSC: HRBE (Bit 8) */ -#define HRPWM0_HRBSC_HRBE_Msk \ - (0x100UL) /*!< HRPWM0 HRBSC: HRBE (Bitfield-Mask: 0x01) */ - -/* --------------------------------- HRPWM0_MIDR -------------------------------- */ -#define HRPWM0_MIDR_MODR_Pos \ - (0UL) /*!< HRPWM0 MIDR: MODR (Bit 0) */ -#define HRPWM0_MIDR_MODR_Msk \ - (0xffUL) /*!< HRPWM0 MIDR: MODR (Bitfield-Mask: 0xff) */ -#define HRPWM0_MIDR_MODT_Pos \ - (8UL) /*!< HRPWM0 MIDR: MODT (Bit 8) */ -#define HRPWM0_MIDR_MODT_Msk \ - (0xff00UL) /*!< HRPWM0 MIDR: MODT (Bitfield-Mask: 0xff) */ -#define HRPWM0_MIDR_MODN_Pos \ - (16UL) /*!< HRPWM0 MIDR: MODN (Bit 16) */ -#define HRPWM0_MIDR_MODN_Msk \ - (0xffff0000UL) /*!< HRPWM0 MIDR: MODN (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- HRPWM0_GLBANA ------------------------------- */ -#define HRPWM0_GLBANA_SLDLY_Pos \ - (0UL) /*!< HRPWM0 GLBANA: SLDLY (Bit 0) */ -#define HRPWM0_GLBANA_SLDLY_Msk \ - (0x3UL) /*!< HRPWM0 GLBANA: SLDLY (Bitfield-Mask: 0x03) */ -#define HRPWM0_GLBANA_FUP_Pos \ - (2UL) /*!< HRPWM0 GLBANA: FUP (Bit 2) */ -#define HRPWM0_GLBANA_FUP_Msk \ - (0x4UL) /*!< HRPWM0 GLBANA: FUP (Bitfield-Mask: 0x01) */ -#define HRPWM0_GLBANA_FDN_Pos \ - (3UL) /*!< HRPWM0 GLBANA: FDN (Bit 3) */ -#define HRPWM0_GLBANA_FDN_Msk \ - (0x8UL) /*!< HRPWM0 GLBANA: FDN (Bitfield-Mask: 0x01) */ -#define HRPWM0_GLBANA_SLCP_Pos \ - (6UL) /*!< HRPWM0 GLBANA: SLCP (Bit 6) */ -#define HRPWM0_GLBANA_SLCP_Msk \ - (0x1c0UL) /*!< HRPWM0 GLBANA: SLCP (Bitfield-Mask: 0x07) */ -#define HRPWM0_GLBANA_SLIBLDO_Pos \ - (9UL) /*!< HRPWM0 GLBANA: SLIBLDO (Bit 9) */ -#define HRPWM0_GLBANA_SLIBLDO_Msk \ - (0x600UL) /*!< HRPWM0 GLBANA: SLIBLDO (Bitfield-Mask: 0x03) */ -#define HRPWM0_GLBANA_SLIBLF_Pos \ - (11UL) /*!< HRPWM0 GLBANA: SLIBLF (Bit 11) */ -#define HRPWM0_GLBANA_SLIBLF_Msk \ - (0x1800UL) /*!< HRPWM0 GLBANA: SLIBLF (Bitfield-Mask: 0x03) */ -#define HRPWM0_GLBANA_SLVREF_Pos \ - (13UL) /*!< HRPWM0 GLBANA: SLVREF (Bit 13) */ -#define HRPWM0_GLBANA_SLVREF_Msk \ - (0xe000UL) /*!< HRPWM0 GLBANA: SLVREF (Bitfield-Mask: 0x07) */ -#define HRPWM0_GLBANA_TRIBIAS_Pos \ - (16UL) /*!< HRPWM0 GLBANA: TRIBIAS (Bit 16) */ -#define HRPWM0_GLBANA_TRIBIAS_Msk \ - (0x30000UL) /*!< HRPWM0 GLBANA: TRIBIAS (Bitfield-Mask: 0x03) */ -#define HRPWM0_GLBANA_GHREN_Pos \ - (18UL) /*!< HRPWM0 GLBANA: GHREN (Bit 18) */ -#define HRPWM0_GLBANA_GHREN_Msk \ - (0x40000UL) /*!< HRPWM0 GLBANA: GHREN (Bitfield-Mask: 0x01) */ - -/* -------------------------------- HRPWM0_CSGCFG ------------------------------- */ -#define HRPWM0_CSGCFG_C0PM_Pos \ - (0UL) /*!< HRPWM0 CSGCFG: C0PM (Bit 0) */ -#define HRPWM0_CSGCFG_C0PM_Msk \ - (0x3UL) /*!< HRPWM0 CSGCFG: C0PM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSGCFG_C1PM_Pos \ - (2UL) /*!< HRPWM0 CSGCFG: C1PM (Bit 2) */ -#define HRPWM0_CSGCFG_C1PM_Msk \ - (0xcUL) /*!< HRPWM0 CSGCFG: C1PM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSGCFG_C2PM_Pos \ - (4UL) /*!< HRPWM0 CSGCFG: C2PM (Bit 4) */ -#define HRPWM0_CSGCFG_C2PM_Msk \ - (0x30UL) /*!< HRPWM0 CSGCFG: C2PM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSGCFG_C0CD_Pos \ - (16UL) /*!< HRPWM0 CSGCFG: C0CD (Bit 16) */ -#define HRPWM0_CSGCFG_C0CD_Msk \ - (0x10000UL) /*!< HRPWM0 CSGCFG: C0CD (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGCFG_C1CD_Pos \ - (17UL) /*!< HRPWM0 CSGCFG: C1CD (Bit 17) */ -#define HRPWM0_CSGCFG_C1CD_Msk \ - (0x20000UL) /*!< HRPWM0 CSGCFG: C1CD (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGCFG_C2CD_Pos \ - (18UL) /*!< HRPWM0 CSGCFG: C2CD (Bit 18) */ -#define HRPWM0_CSGCFG_C2CD_Msk \ - (0x40000UL) /*!< HRPWM0 CSGCFG: C2CD (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_CSGSETG ------------------------------- */ -#define HRPWM0_CSGSETG_SD0R_Pos \ - (0UL) /*!< HRPWM0 CSGSETG: SD0R (Bit 0) */ -#define HRPWM0_CSGSETG_SD0R_Msk \ - (0x1UL) /*!< HRPWM0 CSGSETG: SD0R (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGSETG_SC0R_Pos \ - (1UL) /*!< HRPWM0 CSGSETG: SC0R (Bit 1) */ -#define HRPWM0_CSGSETG_SC0R_Msk \ - (0x2UL) /*!< HRPWM0 CSGSETG: SC0R (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGSETG_SC0P_Pos \ - (2UL) /*!< HRPWM0 CSGSETG: SC0P (Bit 2) */ -#define HRPWM0_CSGSETG_SC0P_Msk \ - (0x4UL) /*!< HRPWM0 CSGSETG: SC0P (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGSETG_SD1R_Pos \ - (4UL) /*!< HRPWM0 CSGSETG: SD1R (Bit 4) */ -#define HRPWM0_CSGSETG_SD1R_Msk \ - (0x10UL) /*!< HRPWM0 CSGSETG: SD1R (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGSETG_SC1R_Pos \ - (5UL) /*!< HRPWM0 CSGSETG: SC1R (Bit 5) */ -#define HRPWM0_CSGSETG_SC1R_Msk \ - (0x20UL) /*!< HRPWM0 CSGSETG: SC1R (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGSETG_SC1P_Pos \ - (6UL) /*!< HRPWM0 CSGSETG: SC1P (Bit 6) */ -#define HRPWM0_CSGSETG_SC1P_Msk \ - (0x40UL) /*!< HRPWM0 CSGSETG: SC1P (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGSETG_SD2R_Pos \ - (8UL) /*!< HRPWM0 CSGSETG: SD2R (Bit 8) */ -#define HRPWM0_CSGSETG_SD2R_Msk \ - (0x100UL) /*!< HRPWM0 CSGSETG: SD2R (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGSETG_SC2R_Pos \ - (9UL) /*!< HRPWM0 CSGSETG: SC2R (Bit 9) */ -#define HRPWM0_CSGSETG_SC2R_Msk \ - (0x200UL) /*!< HRPWM0 CSGSETG: SC2R (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGSETG_SC2P_Pos \ - (10UL) /*!< HRPWM0 CSGSETG: SC2P (Bit 10) */ -#define HRPWM0_CSGSETG_SC2P_Msk \ - (0x400UL) /*!< HRPWM0 CSGSETG: SC2P (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_CSGCLRG ------------------------------- */ -#define HRPWM0_CSGCLRG_CD0R_Pos \ - (0UL) /*!< HRPWM0 CSGCLRG: CD0R (Bit 0) */ -#define HRPWM0_CSGCLRG_CD0R_Msk \ - (0x1UL) /*!< HRPWM0 CSGCLRG: CD0R (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGCLRG_CC0R_Pos \ - (1UL) /*!< HRPWM0 CSGCLRG: CC0R (Bit 1) */ -#define HRPWM0_CSGCLRG_CC0R_Msk \ - (0x2UL) /*!< HRPWM0 CSGCLRG: CC0R (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGCLRG_CC0P_Pos \ - (2UL) /*!< HRPWM0 CSGCLRG: CC0P (Bit 2) */ -#define HRPWM0_CSGCLRG_CC0P_Msk \ - (0x4UL) /*!< HRPWM0 CSGCLRG: CC0P (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGCLRG_CD1R_Pos \ - (4UL) /*!< HRPWM0 CSGCLRG: CD1R (Bit 4) */ -#define HRPWM0_CSGCLRG_CD1R_Msk \ - (0x10UL) /*!< HRPWM0 CSGCLRG: CD1R (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGCLRG_CC1R_Pos \ - (5UL) /*!< HRPWM0 CSGCLRG: CC1R (Bit 5) */ -#define HRPWM0_CSGCLRG_CC1R_Msk \ - (0x20UL) /*!< HRPWM0 CSGCLRG: CC1R (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGCLRG_CC1P_Pos \ - (6UL) /*!< HRPWM0 CSGCLRG: CC1P (Bit 6) */ -#define HRPWM0_CSGCLRG_CC1P_Msk \ - (0x40UL) /*!< HRPWM0 CSGCLRG: CC1P (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGCLRG_CD2R_Pos \ - (8UL) /*!< HRPWM0 CSGCLRG: CD2R (Bit 8) */ -#define HRPWM0_CSGCLRG_CD2R_Msk \ - (0x100UL) /*!< HRPWM0 CSGCLRG: CD2R (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGCLRG_CC2R_Pos \ - (9UL) /*!< HRPWM0 CSGCLRG: CC2R (Bit 9) */ -#define HRPWM0_CSGCLRG_CC2R_Msk \ - (0x200UL) /*!< HRPWM0 CSGCLRG: CC2R (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGCLRG_CC2P_Pos \ - (10UL) /*!< HRPWM0 CSGCLRG: CC2P (Bit 10) */ -#define HRPWM0_CSGCLRG_CC2P_Msk \ - (0x400UL) /*!< HRPWM0 CSGCLRG: CC2P (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_CSGSTATG ------------------------------ */ -#define HRPWM0_CSGSTATG_D0RB_Pos \ - (0UL) /*!< HRPWM0 CSGSTATG: D0RB (Bit 0) */ -#define HRPWM0_CSGSTATG_D0RB_Msk \ - (0x1UL) /*!< HRPWM0 CSGSTATG: D0RB (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGSTATG_C0RB_Pos \ - (1UL) /*!< HRPWM0 CSGSTATG: C0RB (Bit 1) */ -#define HRPWM0_CSGSTATG_C0RB_Msk \ - (0x2UL) /*!< HRPWM0 CSGSTATG: C0RB (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGSTATG_PSLS0_Pos \ - (2UL) /*!< HRPWM0 CSGSTATG: PSLS0 (Bit 2) */ -#define HRPWM0_CSGSTATG_PSLS0_Msk \ - (0x4UL) /*!< HRPWM0 CSGSTATG: PSLS0 (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGSTATG_D1RB_Pos \ - (4UL) /*!< HRPWM0 CSGSTATG: D1RB (Bit 4) */ -#define HRPWM0_CSGSTATG_D1RB_Msk \ - (0x10UL) /*!< HRPWM0 CSGSTATG: D1RB (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGSTATG_C1RB_Pos \ - (5UL) /*!< HRPWM0 CSGSTATG: C1RB (Bit 5) */ -#define HRPWM0_CSGSTATG_C1RB_Msk \ - (0x20UL) /*!< HRPWM0 CSGSTATG: C1RB (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGSTATG_PSLS1_Pos \ - (6UL) /*!< HRPWM0 CSGSTATG: PSLS1 (Bit 6) */ -#define HRPWM0_CSGSTATG_PSLS1_Msk \ - (0x40UL) /*!< HRPWM0 CSGSTATG: PSLS1 (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGSTATG_D2RB_Pos \ - (8UL) /*!< HRPWM0 CSGSTATG: D2RB (Bit 8) */ -#define HRPWM0_CSGSTATG_D2RB_Msk \ - (0x100UL) /*!< HRPWM0 CSGSTATG: D2RB (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGSTATG_C2RB_Pos \ - (9UL) /*!< HRPWM0 CSGSTATG: C2RB (Bit 9) */ -#define HRPWM0_CSGSTATG_C2RB_Msk \ - (0x200UL) /*!< HRPWM0 CSGSTATG: C2RB (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGSTATG_PSLS2_Pos \ - (10UL) /*!< HRPWM0 CSGSTATG: PSLS2 (Bit 10) */ -#define HRPWM0_CSGSTATG_PSLS2_Msk \ - (0x400UL) /*!< HRPWM0 CSGSTATG: PSLS2 (Bitfield-Mask: 0x01) */ - -/* -------------------------------- HRPWM0_CSGFCG ------------------------------- */ -#define HRPWM0_CSGFCG_S0STR_Pos \ - (0UL) /*!< HRPWM0 CSGFCG: S0STR (Bit 0) */ -#define HRPWM0_CSGFCG_S0STR_Msk \ - (0x1UL) /*!< HRPWM0 CSGFCG: S0STR (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGFCG_S0STP_Pos \ - (1UL) /*!< HRPWM0 CSGFCG: S0STP (Bit 1) */ -#define HRPWM0_CSGFCG_S0STP_Msk \ - (0x2UL) /*!< HRPWM0 CSGFCG: S0STP (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGFCG_PS0STR_Pos \ - (2UL) /*!< HRPWM0 CSGFCG: PS0STR (Bit 2) */ -#define HRPWM0_CSGFCG_PS0STR_Msk \ - (0x4UL) /*!< HRPWM0 CSGFCG: PS0STR (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGFCG_PS0STP_Pos \ - (3UL) /*!< HRPWM0 CSGFCG: PS0STP (Bit 3) */ -#define HRPWM0_CSGFCG_PS0STP_Msk \ - (0x8UL) /*!< HRPWM0 CSGFCG: PS0STP (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGFCG_PS0CLR_Pos \ - (4UL) /*!< HRPWM0 CSGFCG: PS0CLR (Bit 4) */ -#define HRPWM0_CSGFCG_PS0CLR_Msk \ - (0x10UL) /*!< HRPWM0 CSGFCG: PS0CLR (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGFCG_S1STR_Pos \ - (8UL) /*!< HRPWM0 CSGFCG: S1STR (Bit 8) */ -#define HRPWM0_CSGFCG_S1STR_Msk \ - (0x100UL) /*!< HRPWM0 CSGFCG: S1STR (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGFCG_S1STP_Pos \ - (9UL) /*!< HRPWM0 CSGFCG: S1STP (Bit 9) */ -#define HRPWM0_CSGFCG_S1STP_Msk \ - (0x200UL) /*!< HRPWM0 CSGFCG: S1STP (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGFCG_PS1STR_Pos \ - (10UL) /*!< HRPWM0 CSGFCG: PS1STR (Bit 10) */ -#define HRPWM0_CSGFCG_PS1STR_Msk \ - (0x400UL) /*!< HRPWM0 CSGFCG: PS1STR (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGFCG_PS1STP_Pos \ - (11UL) /*!< HRPWM0 CSGFCG: PS1STP (Bit 11) */ -#define HRPWM0_CSGFCG_PS1STP_Msk \ - (0x800UL) /*!< HRPWM0 CSGFCG: PS1STP (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGFCG_PS1CLR_Pos \ - (12UL) /*!< HRPWM0 CSGFCG: PS1CLR (Bit 12) */ -#define HRPWM0_CSGFCG_PS1CLR_Msk \ - (0x1000UL) /*!< HRPWM0 CSGFCG: PS1CLR (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGFCG_S2STR_Pos \ - (16UL) /*!< HRPWM0 CSGFCG: S2STR (Bit 16) */ -#define HRPWM0_CSGFCG_S2STR_Msk \ - (0x10000UL) /*!< HRPWM0 CSGFCG: S2STR (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGFCG_S2STP_Pos \ - (17UL) /*!< HRPWM0 CSGFCG: S2STP (Bit 17) */ -#define HRPWM0_CSGFCG_S2STP_Msk \ - (0x20000UL) /*!< HRPWM0 CSGFCG: S2STP (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGFCG_PS2STR_Pos \ - (18UL) /*!< HRPWM0 CSGFCG: PS2STR (Bit 18) */ -#define HRPWM0_CSGFCG_PS2STR_Msk \ - (0x40000UL) /*!< HRPWM0 CSGFCG: PS2STR (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGFCG_PS2STP_Pos \ - (19UL) /*!< HRPWM0 CSGFCG: PS2STP (Bit 19) */ -#define HRPWM0_CSGFCG_PS2STP_Msk \ - (0x80000UL) /*!< HRPWM0 CSGFCG: PS2STP (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGFCG_PS2CLR_Pos \ - (20UL) /*!< HRPWM0 CSGFCG: PS2CLR (Bit 20) */ -#define HRPWM0_CSGFCG_PS2CLR_Msk \ - (0x100000UL) /*!< HRPWM0 CSGFCG: PS2CLR (Bitfield-Mask: 0x01) */ - -/* -------------------------------- HRPWM0_CSGFSG ------------------------------- */ -#define HRPWM0_CSGFSG_S0RB_Pos \ - (0UL) /*!< HRPWM0 CSGFSG: S0RB (Bit 0) */ -#define HRPWM0_CSGFSG_S0RB_Msk \ - (0x1UL) /*!< HRPWM0 CSGFSG: S0RB (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGFSG_P0RB_Pos \ - (1UL) /*!< HRPWM0 CSGFSG: P0RB (Bit 1) */ -#define HRPWM0_CSGFSG_P0RB_Msk \ - (0x2UL) /*!< HRPWM0 CSGFSG: P0RB (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGFSG_S1RB_Pos \ - (8UL) /*!< HRPWM0 CSGFSG: S1RB (Bit 8) */ -#define HRPWM0_CSGFSG_S1RB_Msk \ - (0x100UL) /*!< HRPWM0 CSGFSG: S1RB (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGFSG_P1RB_Pos \ - (9UL) /*!< HRPWM0 CSGFSG: P1RB (Bit 9) */ -#define HRPWM0_CSGFSG_P1RB_Msk \ - (0x200UL) /*!< HRPWM0 CSGFSG: P1RB (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGFSG_S2RB_Pos \ - (16UL) /*!< HRPWM0 CSGFSG: S2RB (Bit 16) */ -#define HRPWM0_CSGFSG_S2RB_Msk \ - (0x10000UL) /*!< HRPWM0 CSGFSG: S2RB (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGFSG_P2RB_Pos \ - (17UL) /*!< HRPWM0 CSGFSG: P2RB (Bit 17) */ -#define HRPWM0_CSGFSG_P2RB_Msk \ - (0x20000UL) /*!< HRPWM0 CSGFSG: P2RB (Bitfield-Mask: 0x01) */ - -/* -------------------------------- HRPWM0_CSGTRG ------------------------------- */ -#define HRPWM0_CSGTRG_D0SES_Pos \ - (0UL) /*!< HRPWM0 CSGTRG: D0SES (Bit 0) */ -#define HRPWM0_CSGTRG_D0SES_Msk \ - (0x1UL) /*!< HRPWM0 CSGTRG: D0SES (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGTRG_D0SVS_Pos \ - (1UL) /*!< HRPWM0 CSGTRG: D0SVS (Bit 1) */ -#define HRPWM0_CSGTRG_D0SVS_Msk \ - (0x2UL) /*!< HRPWM0 CSGTRG: D0SVS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGTRG_D1SES_Pos \ - (4UL) /*!< HRPWM0 CSGTRG: D1SES (Bit 4) */ -#define HRPWM0_CSGTRG_D1SES_Msk \ - (0x10UL) /*!< HRPWM0 CSGTRG: D1SES (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGTRG_D1SVS_Pos \ - (5UL) /*!< HRPWM0 CSGTRG: D1SVS (Bit 5) */ -#define HRPWM0_CSGTRG_D1SVS_Msk \ - (0x20UL) /*!< HRPWM0 CSGTRG: D1SVS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGTRG_D2SES_Pos \ - (8UL) /*!< HRPWM0 CSGTRG: D2SES (Bit 8) */ -#define HRPWM0_CSGTRG_D2SES_Msk \ - (0x100UL) /*!< HRPWM0 CSGTRG: D2SES (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGTRG_D2SVS_Pos \ - (9UL) /*!< HRPWM0 CSGTRG: D2SVS (Bit 9) */ -#define HRPWM0_CSGTRG_D2SVS_Msk \ - (0x200UL) /*!< HRPWM0 CSGTRG: D2SVS (Bitfield-Mask: 0x01) */ - -/* -------------------------------- HRPWM0_CSGTRC ------------------------------- */ -#define HRPWM0_CSGTRC_D0SEC_Pos \ - (0UL) /*!< HRPWM0 CSGTRC: D0SEC (Bit 0) */ -#define HRPWM0_CSGTRC_D0SEC_Msk \ - (0x1UL) /*!< HRPWM0 CSGTRC: D0SEC (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGTRC_D1SEC_Pos \ - (4UL) /*!< HRPWM0 CSGTRC: D1SEC (Bit 4) */ -#define HRPWM0_CSGTRC_D1SEC_Msk \ - (0x10UL) /*!< HRPWM0 CSGTRC: D1SEC (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGTRC_D2SEC_Pos \ - (8UL) /*!< HRPWM0 CSGTRC: D2SEC (Bit 8) */ -#define HRPWM0_CSGTRC_D2SEC_Msk \ - (0x100UL) /*!< HRPWM0 CSGTRC: D2SEC (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_CSGTRSG ------------------------------- */ -#define HRPWM0_CSGTRSG_D0STE_Pos \ - (0UL) /*!< HRPWM0 CSGTRSG: D0STE (Bit 0) */ -#define HRPWM0_CSGTRSG_D0STE_Msk \ - (0x1UL) /*!< HRPWM0 CSGTRSG: D0STE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGTRSG_SW0ST_Pos \ - (1UL) /*!< HRPWM0 CSGTRSG: SW0ST (Bit 1) */ -#define HRPWM0_CSGTRSG_SW0ST_Msk \ - (0x2UL) /*!< HRPWM0 CSGTRSG: SW0ST (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGTRSG_D1STE_Pos \ - (4UL) /*!< HRPWM0 CSGTRSG: D1STE (Bit 4) */ -#define HRPWM0_CSGTRSG_D1STE_Msk \ - (0x10UL) /*!< HRPWM0 CSGTRSG: D1STE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGTRSG_SW1ST_Pos \ - (5UL) /*!< HRPWM0 CSGTRSG: SW1ST (Bit 5) */ -#define HRPWM0_CSGTRSG_SW1ST_Msk \ - (0x20UL) /*!< HRPWM0 CSGTRSG: SW1ST (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGTRSG_D2STE_Pos \ - (8UL) /*!< HRPWM0 CSGTRSG: D2STE (Bit 8) */ -#define HRPWM0_CSGTRSG_D2STE_Msk \ - (0x100UL) /*!< HRPWM0 CSGTRSG: D2STE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGTRSG_SW2ST_Pos \ - (9UL) /*!< HRPWM0 CSGTRSG: SW2ST (Bit 9) */ -#define HRPWM0_CSGTRSG_SW2ST_Msk \ - (0x200UL) /*!< HRPWM0 CSGTRSG: SW2ST (Bitfield-Mask: 0x01) */ - -/* -------------------------------- HRPWM0_HRCCFG ------------------------------- */ -#define HRPWM0_HRCCFG_HRCPM_Pos \ - (0UL) /*!< HRPWM0 HRCCFG: HRCPM (Bit 0) */ -#define HRPWM0_HRCCFG_HRCPM_Msk \ - (0x1UL) /*!< HRPWM0 HRCCFG: HRCPM (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCCFG_HRC0E_Pos \ - (4UL) /*!< HRPWM0 HRCCFG: HRC0E (Bit 4) */ -#define HRPWM0_HRCCFG_HRC0E_Msk \ - (0x10UL) /*!< HRPWM0 HRCCFG: HRC0E (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCCFG_HRC1E_Pos \ - (5UL) /*!< HRPWM0 HRCCFG: HRC1E (Bit 5) */ -#define HRPWM0_HRCCFG_HRC1E_Msk \ - (0x20UL) /*!< HRPWM0 HRCCFG: HRC1E (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCCFG_HRC2E_Pos \ - (6UL) /*!< HRPWM0 HRCCFG: HRC2E (Bit 6) */ -#define HRPWM0_HRCCFG_HRC2E_Msk \ - (0x40UL) /*!< HRPWM0 HRCCFG: HRC2E (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCCFG_HRC3E_Pos \ - (7UL) /*!< HRPWM0 HRCCFG: HRC3E (Bit 7) */ -#define HRPWM0_HRCCFG_HRC3E_Msk \ - (0x80UL) /*!< HRPWM0 HRCCFG: HRC3E (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCCFG_CLKC_Pos \ - (16UL) /*!< HRPWM0 HRCCFG: CLKC (Bit 16) */ -#define HRPWM0_HRCCFG_CLKC_Msk \ - (0x70000UL) /*!< HRPWM0 HRCCFG: CLKC (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRCCFG_LRC0E_Pos \ - (20UL) /*!< HRPWM0 HRCCFG: LRC0E (Bit 20) */ -#define HRPWM0_HRCCFG_LRC0E_Msk \ - (0x100000UL) /*!< HRPWM0 HRCCFG: LRC0E (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCCFG_LRC1E_Pos \ - (21UL) /*!< HRPWM0 HRCCFG: LRC1E (Bit 21) */ -#define HRPWM0_HRCCFG_LRC1E_Msk \ - (0x200000UL) /*!< HRPWM0 HRCCFG: LRC1E (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCCFG_LRC2E_Pos \ - (22UL) /*!< HRPWM0 HRCCFG: LRC2E (Bit 22) */ -#define HRPWM0_HRCCFG_LRC2E_Msk \ - (0x400000UL) /*!< HRPWM0 HRCCFG: LRC2E (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCCFG_LRC3E_Pos \ - (23UL) /*!< HRPWM0 HRCCFG: LRC3E (Bit 23) */ -#define HRPWM0_HRCCFG_LRC3E_Msk \ - (0x800000UL) /*!< HRPWM0 HRCCFG: LRC3E (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_HRCSTRG ------------------------------- */ -#define HRPWM0_HRCSTRG_H0ES_Pos \ - (0UL) /*!< HRPWM0 HRCSTRG: H0ES (Bit 0) */ -#define HRPWM0_HRCSTRG_H0ES_Msk \ - (0x1UL) /*!< HRPWM0 HRCSTRG: H0ES (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCSTRG_H0DES_Pos \ - (1UL) /*!< HRPWM0 HRCSTRG: H0DES (Bit 1) */ -#define HRPWM0_HRCSTRG_H0DES_Msk \ - (0x2UL) /*!< HRPWM0 HRCSTRG: H0DES (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCSTRG_H1ES_Pos \ - (4UL) /*!< HRPWM0 HRCSTRG: H1ES (Bit 4) */ -#define HRPWM0_HRCSTRG_H1ES_Msk \ - (0x10UL) /*!< HRPWM0 HRCSTRG: H1ES (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCSTRG_H1DES_Pos \ - (5UL) /*!< HRPWM0 HRCSTRG: H1DES (Bit 5) */ -#define HRPWM0_HRCSTRG_H1DES_Msk \ - (0x20UL) /*!< HRPWM0 HRCSTRG: H1DES (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCSTRG_H2ES_Pos \ - (8UL) /*!< HRPWM0 HRCSTRG: H2ES (Bit 8) */ -#define HRPWM0_HRCSTRG_H2ES_Msk \ - (0x100UL) /*!< HRPWM0 HRCSTRG: H2ES (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCSTRG_H2DES_Pos \ - (9UL) /*!< HRPWM0 HRCSTRG: H2DES (Bit 9) */ -#define HRPWM0_HRCSTRG_H2DES_Msk \ - (0x200UL) /*!< HRPWM0 HRCSTRG: H2DES (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCSTRG_H3ES_Pos \ - (12UL) /*!< HRPWM0 HRCSTRG: H3ES (Bit 12) */ -#define HRPWM0_HRCSTRG_H3ES_Msk \ - (0x1000UL) /*!< HRPWM0 HRCSTRG: H3ES (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCSTRG_H3DES_Pos \ - (13UL) /*!< HRPWM0 HRCSTRG: H3DES (Bit 13) */ -#define HRPWM0_HRCSTRG_H3DES_Msk \ - (0x2000UL) /*!< HRPWM0 HRCSTRG: H3DES (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_HRCCTRG ------------------------------- */ -#define HRPWM0_HRCCTRG_H0EC_Pos \ - (0UL) /*!< HRPWM0 HRCCTRG: H0EC (Bit 0) */ -#define HRPWM0_HRCCTRG_H0EC_Msk \ - (0x1UL) /*!< HRPWM0 HRCCTRG: H0EC (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCCTRG_H0DEC_Pos \ - (1UL) /*!< HRPWM0 HRCCTRG: H0DEC (Bit 1) */ -#define HRPWM0_HRCCTRG_H0DEC_Msk \ - (0x2UL) /*!< HRPWM0 HRCCTRG: H0DEC (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCCTRG_H1EC_Pos \ - (4UL) /*!< HRPWM0 HRCCTRG: H1EC (Bit 4) */ -#define HRPWM0_HRCCTRG_H1EC_Msk \ - (0x10UL) /*!< HRPWM0 HRCCTRG: H1EC (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCCTRG_H1DEC_Pos \ - (5UL) /*!< HRPWM0 HRCCTRG: H1DEC (Bit 5) */ -#define HRPWM0_HRCCTRG_H1DEC_Msk \ - (0x20UL) /*!< HRPWM0 HRCCTRG: H1DEC (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCCTRG_H2CEC_Pos \ - (8UL) /*!< HRPWM0 HRCCTRG: H2CEC (Bit 8) */ -#define HRPWM0_HRCCTRG_H2CEC_Msk \ - (0x100UL) /*!< HRPWM0 HRCCTRG: H2CEC (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCCTRG_H2DEC_Pos \ - (9UL) /*!< HRPWM0 HRCCTRG: H2DEC (Bit 9) */ -#define HRPWM0_HRCCTRG_H2DEC_Msk \ - (0x200UL) /*!< HRPWM0 HRCCTRG: H2DEC (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCCTRG_H3EC_Pos \ - (12UL) /*!< HRPWM0 HRCCTRG: H3EC (Bit 12) */ -#define HRPWM0_HRCCTRG_H3EC_Msk \ - (0x1000UL) /*!< HRPWM0 HRCCTRG: H3EC (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCCTRG_H3DEC_Pos \ - (13UL) /*!< HRPWM0 HRCCTRG: H3DEC (Bit 13) */ -#define HRPWM0_HRCCTRG_H3DEC_Msk \ - (0x2000UL) /*!< HRPWM0 HRCCTRG: H3DEC (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_HRCSTSG ------------------------------- */ -#define HRPWM0_HRCSTSG_H0STE_Pos \ - (0UL) /*!< HRPWM0 HRCSTSG: H0STE (Bit 0) */ -#define HRPWM0_HRCSTSG_H0STE_Msk \ - (0x1UL) /*!< HRPWM0 HRCSTSG: H0STE (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCSTSG_H0DSTE_Pos \ - (1UL) /*!< HRPWM0 HRCSTSG: H0DSTE (Bit 1) */ -#define HRPWM0_HRCSTSG_H0DSTE_Msk \ - (0x2UL) /*!< HRPWM0 HRCSTSG: H0DSTE (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCSTSG_H1STE_Pos \ - (4UL) /*!< HRPWM0 HRCSTSG: H1STE (Bit 4) */ -#define HRPWM0_HRCSTSG_H1STE_Msk \ - (0x10UL) /*!< HRPWM0 HRCSTSG: H1STE (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCSTSG_H1DSTE_Pos \ - (5UL) /*!< HRPWM0 HRCSTSG: H1DSTE (Bit 5) */ -#define HRPWM0_HRCSTSG_H1DSTE_Msk \ - (0x20UL) /*!< HRPWM0 HRCSTSG: H1DSTE (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCSTSG_H2STE_Pos \ - (8UL) /*!< HRPWM0 HRCSTSG: H2STE (Bit 8) */ -#define HRPWM0_HRCSTSG_H2STE_Msk \ - (0x100UL) /*!< HRPWM0 HRCSTSG: H2STE (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCSTSG_H2DSTE_Pos \ - (9UL) /*!< HRPWM0 HRCSTSG: H2DSTE (Bit 9) */ -#define HRPWM0_HRCSTSG_H2DSTE_Msk \ - (0x200UL) /*!< HRPWM0 HRCSTSG: H2DSTE (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCSTSG_H3STE_Pos \ - (12UL) /*!< HRPWM0 HRCSTSG: H3STE (Bit 12) */ -#define HRPWM0_HRCSTSG_H3STE_Msk \ - (0x1000UL) /*!< HRPWM0 HRCSTSG: H3STE (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCSTSG_H3DSTE_Pos \ - (13UL) /*!< HRPWM0 HRCSTSG: H3DSTE (Bit 13) */ -#define HRPWM0_HRCSTSG_H3DSTE_Msk \ - (0x2000UL) /*!< HRPWM0 HRCSTSG: H3DSTE (Bitfield-Mask: 0x01) */ - -/* -------------------------------- HRPWM0_HRGHRS ------------------------------- */ -#define HRPWM0_HRGHRS_HRGR_Pos \ - (0UL) /*!< HRPWM0 HRGHRS: HRGR (Bit 0) */ -#define HRPWM0_HRGHRS_HRGR_Msk \ - (0x1UL) /*!< HRPWM0 HRGHRS: HRGR (Bitfield-Mask: 0x01) */ - -/* ================================================================================ */ -/* ================ Group 'HRPWM0_CSG' Position & Mask ================ */ -/* ================================================================================ */ - -/* ------------------------------- HRPWM0_CSG_DCI ------------------------------- */ -#define HRPWM0_CSG_DCI_SVIS_Pos \ - (0UL) /*!< HRPWM0_CSG DCI: SVIS (Bit 0) */ -#define HRPWM0_CSG_DCI_SVIS_Msk \ - (0xfUL) /*!< HRPWM0_CSG DCI: SVIS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG_DCI_STRIS_Pos \ - (4UL) /*!< HRPWM0_CSG DCI: STRIS (Bit 4) */ -#define HRPWM0_CSG_DCI_STRIS_Msk \ - (0xf0UL) /*!< HRPWM0_CSG DCI: STRIS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG_DCI_STPIS_Pos \ - (8UL) /*!< HRPWM0_CSG DCI: STPIS (Bit 8) */ -#define HRPWM0_CSG_DCI_STPIS_Msk \ - (0xf00UL) /*!< HRPWM0_CSG DCI: STPIS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG_DCI_TRGIS_Pos \ - (12UL) /*!< HRPWM0_CSG DCI: TRGIS (Bit 12) */ -#define HRPWM0_CSG_DCI_TRGIS_Msk \ - (0xf000UL) /*!< HRPWM0_CSG DCI: TRGIS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG_DCI_STIS_Pos \ - (16UL) /*!< HRPWM0_CSG DCI: STIS (Bit 16) */ -#define HRPWM0_CSG_DCI_STIS_Msk \ - (0xf0000UL) /*!< HRPWM0_CSG DCI: STIS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG_DCI_SCS_Pos \ - (20UL) /*!< HRPWM0_CSG DCI: SCS (Bit 20) */ -#define HRPWM0_CSG_DCI_SCS_Msk \ - (0x300000UL) /*!< HRPWM0_CSG DCI: SCS (Bitfield-Mask: 0x03) */ - -/* ------------------------------- HRPWM0_CSG_IES ------------------------------- */ -#define HRPWM0_CSG_IES_SVLS_Pos \ - (0UL) /*!< HRPWM0_CSG IES: SVLS (Bit 0) */ -#define HRPWM0_CSG_IES_SVLS_Msk \ - (0x3UL) /*!< HRPWM0_CSG IES: SVLS (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG_IES_STRES_Pos \ - (2UL) /*!< HRPWM0_CSG IES: STRES (Bit 2) */ -#define HRPWM0_CSG_IES_STRES_Msk \ - (0xcUL) /*!< HRPWM0_CSG IES: STRES (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG_IES_STPES_Pos \ - (4UL) /*!< HRPWM0_CSG IES: STPES (Bit 4) */ -#define HRPWM0_CSG_IES_STPES_Msk \ - (0x30UL) /*!< HRPWM0_CSG IES: STPES (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG_IES_TRGES_Pos \ - (6UL) /*!< HRPWM0_CSG IES: TRGES (Bit 6) */ -#define HRPWM0_CSG_IES_TRGES_Msk \ - (0xc0UL) /*!< HRPWM0_CSG IES: TRGES (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG_IES_STES_Pos \ - (8UL) /*!< HRPWM0_CSG IES: STES (Bit 8) */ -#define HRPWM0_CSG_IES_STES_Msk \ - (0x300UL) /*!< HRPWM0_CSG IES: STES (Bitfield-Mask: 0x03) */ - -/* -------------------------------- HRPWM0_CSG_SC ------------------------------- */ -#define HRPWM0_CSG_SC_PSRM_Pos \ - (0UL) /*!< HRPWM0_CSG SC: PSRM (Bit 0) */ -#define HRPWM0_CSG_SC_PSRM_Msk \ - (0x3UL) /*!< HRPWM0_CSG SC: PSRM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG_SC_PSTM_Pos \ - (2UL) /*!< HRPWM0_CSG SC: PSTM (Bit 2) */ -#define HRPWM0_CSG_SC_PSTM_Msk \ - (0xcUL) /*!< HRPWM0_CSG SC: PSTM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG_SC_FPD_Pos \ - (4UL) /*!< HRPWM0_CSG SC: FPD (Bit 4) */ -#define HRPWM0_CSG_SC_FPD_Msk \ - (0x10UL) /*!< HRPWM0_CSG SC: FPD (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SC_PSV_Pos \ - (5UL) /*!< HRPWM0_CSG SC: PSV (Bit 5) */ -#define HRPWM0_CSG_SC_PSV_Msk \ - (0x60UL) /*!< HRPWM0_CSG SC: PSV (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG_SC_SCM_Pos \ - (8UL) /*!< HRPWM0_CSG SC: SCM (Bit 8) */ -#define HRPWM0_CSG_SC_SCM_Msk \ - (0x300UL) /*!< HRPWM0_CSG SC: SCM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG_SC_SSRM_Pos \ - (10UL) /*!< HRPWM0_CSG SC: SSRM (Bit 10) */ -#define HRPWM0_CSG_SC_SSRM_Msk \ - (0xc00UL) /*!< HRPWM0_CSG SC: SSRM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG_SC_SSTM_Pos \ - (12UL) /*!< HRPWM0_CSG SC: SSTM (Bit 12) */ -#define HRPWM0_CSG_SC_SSTM_Msk \ - (0x3000UL) /*!< HRPWM0_CSG SC: SSTM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG_SC_SVSC_Pos \ - (14UL) /*!< HRPWM0_CSG SC: SVSC (Bit 14) */ -#define HRPWM0_CSG_SC_SVSC_Msk \ - (0xc000UL) /*!< HRPWM0_CSG SC: SVSC (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG_SC_SWSM_Pos \ - (16UL) /*!< HRPWM0_CSG SC: SWSM (Bit 16) */ -#define HRPWM0_CSG_SC_SWSM_Msk \ - (0x30000UL) /*!< HRPWM0_CSG SC: SWSM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG_SC_GCFG_Pos \ - (18UL) /*!< HRPWM0_CSG SC: GCFG (Bit 18) */ -#define HRPWM0_CSG_SC_GCFG_Msk \ - (0xc0000UL) /*!< HRPWM0_CSG SC: GCFG (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG_SC_IST_Pos \ - (20UL) /*!< HRPWM0_CSG SC: IST (Bit 20) */ -#define HRPWM0_CSG_SC_IST_Msk \ - (0x100000UL) /*!< HRPWM0_CSG SC: IST (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SC_PSE_Pos \ - (21UL) /*!< HRPWM0_CSG SC: PSE (Bit 21) */ -#define HRPWM0_CSG_SC_PSE_Msk \ - (0x200000UL) /*!< HRPWM0_CSG SC: PSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SC_PSWM_Pos \ - (24UL) /*!< HRPWM0_CSG SC: PSWM (Bit 24) */ -#define HRPWM0_CSG_SC_PSWM_Msk \ - (0x3000000UL) /*!< HRPWM0_CSG SC: PSWM (Bitfield-Mask: 0x03) */ - -/* -------------------------------- HRPWM0_CSG_PC ------------------------------- */ -#define HRPWM0_CSG_PC_PSWV_Pos \ - (0UL) /*!< HRPWM0_CSG PC: PSWV (Bit 0) */ -#define HRPWM0_CSG_PC_PSWV_Msk \ - (0x3fUL) /*!< HRPWM0_CSG PC: PSWV (Bitfield-Mask: 0x3f) */ - -/* ------------------------------- HRPWM0_CSG_DSV1 ------------------------------ */ -#define HRPWM0_CSG_DSV1_DSV1_Pos \ - (0UL) /*!< HRPWM0_CSG DSV1: DSV1 (Bit 0) */ -#define HRPWM0_CSG_DSV1_DSV1_Msk \ - (0x3ffUL) /*!< HRPWM0_CSG DSV1: DSV1 (Bitfield-Mask: 0x3ff) */ - -/* ------------------------------- HRPWM0_CSG_DSV2 ------------------------------ */ -#define HRPWM0_CSG_DSV2_DSV2_Pos \ - (0UL) /*!< HRPWM0_CSG DSV2: DSV2 (Bit 0) */ -#define HRPWM0_CSG_DSV2_DSV2_Msk \ - (0x3ffUL) /*!< HRPWM0_CSG DSV2: DSV2 (Bitfield-Mask: 0x3ff) */ - -/* ------------------------------ HRPWM0_CSG_SDSV1 ------------------------------ */ -#define HRPWM0_CSG_SDSV1_SDSV1_Pos \ - (0UL) /*!< HRPWM0_CSG SDSV1: SDSV1 (Bit 0) */ -#define HRPWM0_CSG_SDSV1_SDSV1_Msk \ - (0x3ffUL) /*!< HRPWM0_CSG SDSV1: SDSV1 (Bitfield-Mask: 0x3ff) */ - -/* ------------------------------- HRPWM0_CSG_SPC ------------------------------- */ -#define HRPWM0_CSG_SPC_SPSWV_Pos \ - (0UL) /*!< HRPWM0_CSG SPC: SPSWV (Bit 0) */ -#define HRPWM0_CSG_SPC_SPSWV_Msk \ - (0x3fUL) /*!< HRPWM0_CSG SPC: SPSWV (Bitfield-Mask: 0x3f) */ - -/* -------------------------------- HRPWM0_CSG_CC ------------------------------- */ -#define HRPWM0_CSG_CC_IBS_Pos \ - (0UL) /*!< HRPWM0_CSG CC: IBS (Bit 0) */ -#define HRPWM0_CSG_CC_IBS_Msk \ - (0xfUL) /*!< HRPWM0_CSG CC: IBS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG_CC_IMCS_Pos \ - (8UL) /*!< HRPWM0_CSG CC: IMCS (Bit 8) */ -#define HRPWM0_CSG_CC_IMCS_Msk \ - (0x100UL) /*!< HRPWM0_CSG CC: IMCS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_CC_IMCC_Pos \ - (9UL) /*!< HRPWM0_CSG CC: IMCC (Bit 9) */ -#define HRPWM0_CSG_CC_IMCC_Msk \ - (0x600UL) /*!< HRPWM0_CSG CC: IMCC (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG_CC_ESE_Pos \ - (11UL) /*!< HRPWM0_CSG CC: ESE (Bit 11) */ -#define HRPWM0_CSG_CC_ESE_Msk \ - (0x800UL) /*!< HRPWM0_CSG CC: ESE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_CC_OIE_Pos \ - (12UL) /*!< HRPWM0_CSG CC: OIE (Bit 12) */ -#define HRPWM0_CSG_CC_OIE_Msk \ - (0x1000UL) /*!< HRPWM0_CSG CC: OIE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_CC_OSE_Pos \ - (13UL) /*!< HRPWM0_CSG CC: OSE (Bit 13) */ -#define HRPWM0_CSG_CC_OSE_Msk \ - (0x2000UL) /*!< HRPWM0_CSG CC: OSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_CC_BLMC_Pos \ - (14UL) /*!< HRPWM0_CSG CC: BLMC (Bit 14) */ -#define HRPWM0_CSG_CC_BLMC_Msk \ - (0xc000UL) /*!< HRPWM0_CSG CC: BLMC (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG_CC_EBE_Pos \ - (16UL) /*!< HRPWM0_CSG CC: EBE (Bit 16) */ -#define HRPWM0_CSG_CC_EBE_Msk \ - (0x10000UL) /*!< HRPWM0_CSG CC: EBE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_CC_COFE_Pos \ - (17UL) /*!< HRPWM0_CSG CC: COFE (Bit 17) */ -#define HRPWM0_CSG_CC_COFE_Msk \ - (0x20000UL) /*!< HRPWM0_CSG CC: COFE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_CC_COFM_Pos \ - (18UL) /*!< HRPWM0_CSG CC: COFM (Bit 18) */ -#define HRPWM0_CSG_CC_COFM_Msk \ - (0x3c0000UL) /*!< HRPWM0_CSG CC: COFM (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG_CC_COFC_Pos \ - (24UL) /*!< HRPWM0_CSG CC: COFC (Bit 24) */ -#define HRPWM0_CSG_CC_COFC_Msk \ - (0x3000000UL) /*!< HRPWM0_CSG CC: COFC (Bitfield-Mask: 0x03) */ - -/* ------------------------------- HRPWM0_CSG_PLC ------------------------------- */ -#define HRPWM0_CSG_PLC_IPLS_Pos \ - (0UL) /*!< HRPWM0_CSG PLC: IPLS (Bit 0) */ -#define HRPWM0_CSG_PLC_IPLS_Msk \ - (0xfUL) /*!< HRPWM0_CSG PLC: IPLS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG_PLC_PLCL_Pos \ - (8UL) /*!< HRPWM0_CSG PLC: PLCL (Bit 8) */ -#define HRPWM0_CSG_PLC_PLCL_Msk \ - (0x300UL) /*!< HRPWM0_CSG PLC: PLCL (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG_PLC_PSL_Pos \ - (10UL) /*!< HRPWM0_CSG PLC: PSL (Bit 10) */ -#define HRPWM0_CSG_PLC_PSL_Msk \ - (0x400UL) /*!< HRPWM0_CSG PLC: PSL (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_PLC_PLSW_Pos \ - (11UL) /*!< HRPWM0_CSG PLC: PLSW (Bit 11) */ -#define HRPWM0_CSG_PLC_PLSW_Msk \ - (0x800UL) /*!< HRPWM0_CSG PLC: PLSW (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_PLC_PLEC_Pos \ - (12UL) /*!< HRPWM0_CSG PLC: PLEC (Bit 12) */ -#define HRPWM0_CSG_PLC_PLEC_Msk \ - (0x3000UL) /*!< HRPWM0_CSG PLC: PLEC (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG_PLC_PLXC_Pos \ - (14UL) /*!< HRPWM0_CSG PLC: PLXC (Bit 14) */ -#define HRPWM0_CSG_PLC_PLXC_Msk \ - (0xc000UL) /*!< HRPWM0_CSG PLC: PLXC (Bitfield-Mask: 0x03) */ - -/* ------------------------------- HRPWM0_CSG_BLV ------------------------------- */ -#define HRPWM0_CSG_BLV_BLV_Pos \ - (0UL) /*!< HRPWM0_CSG BLV: BLV (Bit 0) */ -#define HRPWM0_CSG_BLV_BLV_Msk \ - (0xffUL) /*!< HRPWM0_CSG BLV: BLV (Bitfield-Mask: 0xff) */ - -/* ------------------------------- HRPWM0_CSG_SRE ------------------------------- */ -#define HRPWM0_CSG_SRE_VLS1E_Pos \ - (0UL) /*!< HRPWM0_CSG SRE: VLS1E (Bit 0) */ -#define HRPWM0_CSG_SRE_VLS1E_Msk \ - (0x1UL) /*!< HRPWM0_CSG SRE: VLS1E (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SRE_VLS2E_Pos \ - (1UL) /*!< HRPWM0_CSG SRE: VLS2E (Bit 1) */ -#define HRPWM0_CSG_SRE_VLS2E_Msk \ - (0x2UL) /*!< HRPWM0_CSG SRE: VLS2E (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SRE_TRGSE_Pos \ - (2UL) /*!< HRPWM0_CSG SRE: TRGSE (Bit 2) */ -#define HRPWM0_CSG_SRE_TRGSE_Msk \ - (0x4UL) /*!< HRPWM0_CSG SRE: TRGSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SRE_STRSE_Pos \ - (3UL) /*!< HRPWM0_CSG SRE: STRSE (Bit 3) */ -#define HRPWM0_CSG_SRE_STRSE_Msk \ - (0x8UL) /*!< HRPWM0_CSG SRE: STRSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SRE_STPSE_Pos \ - (4UL) /*!< HRPWM0_CSG SRE: STPSE (Bit 4) */ -#define HRPWM0_CSG_SRE_STPSE_Msk \ - (0x10UL) /*!< HRPWM0_CSG SRE: STPSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SRE_STDE_Pos \ - (5UL) /*!< HRPWM0_CSG SRE: STDE (Bit 5) */ -#define HRPWM0_CSG_SRE_STDE_Msk \ - (0x20UL) /*!< HRPWM0_CSG SRE: STDE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SRE_CRSE_Pos \ - (6UL) /*!< HRPWM0_CSG SRE: CRSE (Bit 6) */ -#define HRPWM0_CSG_SRE_CRSE_Msk \ - (0x40UL) /*!< HRPWM0_CSG SRE: CRSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SRE_CFSE_Pos \ - (7UL) /*!< HRPWM0_CSG SRE: CFSE (Bit 7) */ -#define HRPWM0_CSG_SRE_CFSE_Msk \ - (0x80UL) /*!< HRPWM0_CSG SRE: CFSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SRE_CSEE_Pos \ - (8UL) /*!< HRPWM0_CSG SRE: CSEE (Bit 8) */ -#define HRPWM0_CSG_SRE_CSEE_Msk \ - (0x100UL) /*!< HRPWM0_CSG SRE: CSEE (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_CSG_SRS ------------------------------- */ -#define HRPWM0_CSG_SRS_VLS1S_Pos \ - (0UL) /*!< HRPWM0_CSG SRS: VLS1S (Bit 0) */ -#define HRPWM0_CSG_SRS_VLS1S_Msk \ - (0x3UL) /*!< HRPWM0_CSG SRS: VLS1S (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG_SRS_VLS2S_Pos \ - (2UL) /*!< HRPWM0_CSG SRS: VLS2S (Bit 2) */ -#define HRPWM0_CSG_SRS_VLS2S_Msk \ - (0xcUL) /*!< HRPWM0_CSG SRS: VLS2S (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG_SRS_TRLS_Pos \ - (4UL) /*!< HRPWM0_CSG SRS: TRLS (Bit 4) */ -#define HRPWM0_CSG_SRS_TRLS_Msk \ - (0x30UL) /*!< HRPWM0_CSG SRS: TRLS (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG_SRS_SSLS_Pos \ - (6UL) /*!< HRPWM0_CSG SRS: SSLS (Bit 6) */ -#define HRPWM0_CSG_SRS_SSLS_Msk \ - (0xc0UL) /*!< HRPWM0_CSG SRS: SSLS (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG_SRS_STLS_Pos \ - (8UL) /*!< HRPWM0_CSG SRS: STLS (Bit 8) */ -#define HRPWM0_CSG_SRS_STLS_Msk \ - (0x300UL) /*!< HRPWM0_CSG SRS: STLS (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG_SRS_CRFLS_Pos \ - (10UL) /*!< HRPWM0_CSG SRS: CRFLS (Bit 10) */ -#define HRPWM0_CSG_SRS_CRFLS_Msk \ - (0xc00UL) /*!< HRPWM0_CSG SRS: CRFLS (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG_SRS_CSLS_Pos \ - (12UL) /*!< HRPWM0_CSG SRS: CSLS (Bit 12) */ -#define HRPWM0_CSG_SRS_CSLS_Msk \ - (0x3000UL) /*!< HRPWM0_CSG SRS: CSLS (Bitfield-Mask: 0x03) */ - -/* ------------------------------- HRPWM0_CSG_SWS ------------------------------- */ -#define HRPWM0_CSG_SWS_SVLS1_Pos \ - (0UL) /*!< HRPWM0_CSG SWS: SVLS1 (Bit 0) */ -#define HRPWM0_CSG_SWS_SVLS1_Msk \ - (0x1UL) /*!< HRPWM0_CSG SWS: SVLS1 (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SWS_SVLS2_Pos \ - (1UL) /*!< HRPWM0_CSG SWS: SVLS2 (Bit 1) */ -#define HRPWM0_CSG_SWS_SVLS2_Msk \ - (0x2UL) /*!< HRPWM0_CSG SWS: SVLS2 (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SWS_STRGS_Pos \ - (2UL) /*!< HRPWM0_CSG SWS: STRGS (Bit 2) */ -#define HRPWM0_CSG_SWS_STRGS_Msk \ - (0x4UL) /*!< HRPWM0_CSG SWS: STRGS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SWS_SSTRS_Pos \ - (3UL) /*!< HRPWM0_CSG SWS: SSTRS (Bit 3) */ -#define HRPWM0_CSG_SWS_SSTRS_Msk \ - (0x8UL) /*!< HRPWM0_CSG SWS: SSTRS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SWS_SSTPS_Pos \ - (4UL) /*!< HRPWM0_CSG SWS: SSTPS (Bit 4) */ -#define HRPWM0_CSG_SWS_SSTPS_Msk \ - (0x10UL) /*!< HRPWM0_CSG SWS: SSTPS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SWS_SSTD_Pos \ - (5UL) /*!< HRPWM0_CSG SWS: SSTD (Bit 5) */ -#define HRPWM0_CSG_SWS_SSTD_Msk \ - (0x20UL) /*!< HRPWM0_CSG SWS: SSTD (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SWS_SCRS_Pos \ - (6UL) /*!< HRPWM0_CSG SWS: SCRS (Bit 6) */ -#define HRPWM0_CSG_SWS_SCRS_Msk \ - (0x40UL) /*!< HRPWM0_CSG SWS: SCRS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SWS_SCFS_Pos \ - (7UL) /*!< HRPWM0_CSG SWS: SCFS (Bit 7) */ -#define HRPWM0_CSG_SWS_SCFS_Msk \ - (0x80UL) /*!< HRPWM0_CSG SWS: SCFS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SWS_SCSS_Pos \ - (8UL) /*!< HRPWM0_CSG SWS: SCSS (Bit 8) */ -#define HRPWM0_CSG_SWS_SCSS_Msk \ - (0x100UL) /*!< HRPWM0_CSG SWS: SCSS (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_CSG_SWC ------------------------------- */ -#define HRPWM0_CSG_SWC_CVLS1_Pos \ - (0UL) /*!< HRPWM0_CSG SWC: CVLS1 (Bit 0) */ -#define HRPWM0_CSG_SWC_CVLS1_Msk \ - (0x1UL) /*!< HRPWM0_CSG SWC: CVLS1 (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SWC_CVLS2_Pos \ - (1UL) /*!< HRPWM0_CSG SWC: CVLS2 (Bit 1) */ -#define HRPWM0_CSG_SWC_CVLS2_Msk \ - (0x2UL) /*!< HRPWM0_CSG SWC: CVLS2 (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SWC_CTRGS_Pos \ - (2UL) /*!< HRPWM0_CSG SWC: CTRGS (Bit 2) */ -#define HRPWM0_CSG_SWC_CTRGS_Msk \ - (0x4UL) /*!< HRPWM0_CSG SWC: CTRGS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SWC_CSTRS_Pos \ - (3UL) /*!< HRPWM0_CSG SWC: CSTRS (Bit 3) */ -#define HRPWM0_CSG_SWC_CSTRS_Msk \ - (0x8UL) /*!< HRPWM0_CSG SWC: CSTRS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SWC_CSTPS_Pos \ - (4UL) /*!< HRPWM0_CSG SWC: CSTPS (Bit 4) */ -#define HRPWM0_CSG_SWC_CSTPS_Msk \ - (0x10UL) /*!< HRPWM0_CSG SWC: CSTPS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SWC_CSTD_Pos \ - (5UL) /*!< HRPWM0_CSG SWC: CSTD (Bit 5) */ -#define HRPWM0_CSG_SWC_CSTD_Msk \ - (0x20UL) /*!< HRPWM0_CSG SWC: CSTD (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SWC_CCRS_Pos \ - (6UL) /*!< HRPWM0_CSG SWC: CCRS (Bit 6) */ -#define HRPWM0_CSG_SWC_CCRS_Msk \ - (0x40UL) /*!< HRPWM0_CSG SWC: CCRS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SWC_CCFS_Pos \ - (7UL) /*!< HRPWM0_CSG SWC: CCFS (Bit 7) */ -#define HRPWM0_CSG_SWC_CCFS_Msk \ - (0x80UL) /*!< HRPWM0_CSG SWC: CCFS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SWC_CCSS_Pos \ - (8UL) /*!< HRPWM0_CSG SWC: CCSS (Bit 8) */ -#define HRPWM0_CSG_SWC_CCSS_Msk \ - (0x100UL) /*!< HRPWM0_CSG SWC: CCSS (Bitfield-Mask: 0x01) */ - -/* ------------------------------ HRPWM0_CSG_ISTAT ------------------------------ */ -#define HRPWM0_CSG_ISTAT_VLS1S_Pos \ - (0UL) /*!< HRPWM0_CSG ISTAT: VLS1S (Bit 0) */ -#define HRPWM0_CSG_ISTAT_VLS1S_Msk \ - (0x1UL) /*!< HRPWM0_CSG ISTAT: VLS1S (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_ISTAT_VLS2S_Pos \ - (1UL) /*!< HRPWM0_CSG ISTAT: VLS2S (Bit 1) */ -#define HRPWM0_CSG_ISTAT_VLS2S_Msk \ - (0x2UL) /*!< HRPWM0_CSG ISTAT: VLS2S (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_ISTAT_TRGSS_Pos \ - (2UL) /*!< HRPWM0_CSG ISTAT: TRGSS (Bit 2) */ -#define HRPWM0_CSG_ISTAT_TRGSS_Msk \ - (0x4UL) /*!< HRPWM0_CSG ISTAT: TRGSS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_ISTAT_STRSS_Pos \ - (3UL) /*!< HRPWM0_CSG ISTAT: STRSS (Bit 3) */ -#define HRPWM0_CSG_ISTAT_STRSS_Msk \ - (0x8UL) /*!< HRPWM0_CSG ISTAT: STRSS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_ISTAT_STPSS_Pos \ - (4UL) /*!< HRPWM0_CSG ISTAT: STPSS (Bit 4) */ -#define HRPWM0_CSG_ISTAT_STPSS_Msk \ - (0x10UL) /*!< HRPWM0_CSG ISTAT: STPSS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_ISTAT_STDS_Pos \ - (5UL) /*!< HRPWM0_CSG ISTAT: STDS (Bit 5) */ -#define HRPWM0_CSG_ISTAT_STDS_Msk \ - (0x20UL) /*!< HRPWM0_CSG ISTAT: STDS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_ISTAT_CRSS_Pos \ - (6UL) /*!< HRPWM0_CSG ISTAT: CRSS (Bit 6) */ -#define HRPWM0_CSG_ISTAT_CRSS_Msk \ - (0x40UL) /*!< HRPWM0_CSG ISTAT: CRSS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_ISTAT_CFSS_Pos \ - (7UL) /*!< HRPWM0_CSG ISTAT: CFSS (Bit 7) */ -#define HRPWM0_CSG_ISTAT_CFSS_Msk \ - (0x80UL) /*!< HRPWM0_CSG ISTAT: CFSS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_ISTAT_CSES_Pos \ - (8UL) /*!< HRPWM0_CSG ISTAT: CSES (Bit 8) */ -#define HRPWM0_CSG_ISTAT_CSES_Msk \ - (0x100UL) /*!< HRPWM0_CSG ISTAT: CSES (Bitfield-Mask: 0x01) */ - -/* ================================================================================ */ -/* ================ struct 'HRPWM0_CSG0' Position & Mask ================ */ -/* ================================================================================ */ - -/* ------------------------------- HRPWM0_CSG0_DCI ------------------------------ */ -#define HRPWM0_CSG0_DCI_SVIS_Pos \ - (0UL) /*!< HRPWM0_CSG0 DCI: SVIS (Bit 0) */ -#define HRPWM0_CSG0_DCI_SVIS_Msk \ - (0xfUL) /*!< HRPWM0_CSG0 DCI: SVIS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG0_DCI_STRIS_Pos \ - (4UL) /*!< HRPWM0_CSG0 DCI: STRIS (Bit 4) */ -#define HRPWM0_CSG0_DCI_STRIS_Msk \ - (0xf0UL) /*!< HRPWM0_CSG0 DCI: STRIS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG0_DCI_STPIS_Pos \ - (8UL) /*!< HRPWM0_CSG0 DCI: STPIS (Bit 8) */ -#define HRPWM0_CSG0_DCI_STPIS_Msk \ - (0xf00UL) /*!< HRPWM0_CSG0 DCI: STPIS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG0_DCI_TRGIS_Pos \ - (12UL) /*!< HRPWM0_CSG0 DCI: TRGIS (Bit 12) */ -#define HRPWM0_CSG0_DCI_TRGIS_Msk \ - (0xf000UL) /*!< HRPWM0_CSG0 DCI: TRGIS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG0_DCI_STIS_Pos \ - (16UL) /*!< HRPWM0_CSG0 DCI: STIS (Bit 16) */ -#define HRPWM0_CSG0_DCI_STIS_Msk \ - (0xf0000UL) /*!< HRPWM0_CSG0 DCI: STIS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG0_DCI_SCS_Pos \ - (20UL) /*!< HRPWM0_CSG0 DCI: SCS (Bit 20) */ -#define HRPWM0_CSG0_DCI_SCS_Msk \ - (0x300000UL) /*!< HRPWM0_CSG0 DCI: SCS (Bitfield-Mask: 0x03) */ - -/* ------------------------------- HRPWM0_CSG0_IES ------------------------------ */ -#define HRPWM0_CSG0_IES_SVLS_Pos \ - (0UL) /*!< HRPWM0_CSG0 IES: SVLS (Bit 0) */ -#define HRPWM0_CSG0_IES_SVLS_Msk \ - (0x3UL) /*!< HRPWM0_CSG0 IES: SVLS (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG0_IES_STRES_Pos \ - (2UL) /*!< HRPWM0_CSG0 IES: STRES (Bit 2) */ -#define HRPWM0_CSG0_IES_STRES_Msk \ - (0xcUL) /*!< HRPWM0_CSG0 IES: STRES (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG0_IES_STPES_Pos \ - (4UL) /*!< HRPWM0_CSG0 IES: STPES (Bit 4) */ -#define HRPWM0_CSG0_IES_STPES_Msk \ - (0x30UL) /*!< HRPWM0_CSG0 IES: STPES (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG0_IES_TRGES_Pos \ - (6UL) /*!< HRPWM0_CSG0 IES: TRGES (Bit 6) */ -#define HRPWM0_CSG0_IES_TRGES_Msk \ - (0xc0UL) /*!< HRPWM0_CSG0 IES: TRGES (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG0_IES_STES_Pos \ - (8UL) /*!< HRPWM0_CSG0 IES: STES (Bit 8) */ -#define HRPWM0_CSG0_IES_STES_Msk \ - (0x300UL) /*!< HRPWM0_CSG0 IES: STES (Bitfield-Mask: 0x03) */ - -/* ------------------------------- HRPWM0_CSG0_SC ------------------------------- */ -#define HRPWM0_CSG0_SC_PSRM_Pos \ - (0UL) /*!< HRPWM0_CSG0 SC: PSRM (Bit 0) */ -#define HRPWM0_CSG0_SC_PSRM_Msk \ - (0x3UL) /*!< HRPWM0_CSG0 SC: PSRM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG0_SC_PSTM_Pos \ - (2UL) /*!< HRPWM0_CSG0 SC: PSTM (Bit 2) */ -#define HRPWM0_CSG0_SC_PSTM_Msk \ - (0xcUL) /*!< HRPWM0_CSG0 SC: PSTM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG0_SC_FPD_Pos \ - (4UL) /*!< HRPWM0_CSG0 SC: FPD (Bit 4) */ -#define HRPWM0_CSG0_SC_FPD_Msk \ - (0x10UL) /*!< HRPWM0_CSG0 SC: FPD (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SC_PSV_Pos \ - (5UL) /*!< HRPWM0_CSG0 SC: PSV (Bit 5) */ -#define HRPWM0_CSG0_SC_PSV_Msk \ - (0x60UL) /*!< HRPWM0_CSG0 SC: PSV (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG0_SC_SCM_Pos \ - (8UL) /*!< HRPWM0_CSG0 SC: SCM (Bit 8) */ -#define HRPWM0_CSG0_SC_SCM_Msk \ - (0x300UL) /*!< HRPWM0_CSG0 SC: SCM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG0_SC_SSRM_Pos \ - (10UL) /*!< HRPWM0_CSG0 SC: SSRM (Bit 10) */ -#define HRPWM0_CSG0_SC_SSRM_Msk \ - (0xc00UL) /*!< HRPWM0_CSG0 SC: SSRM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG0_SC_SSTM_Pos \ - (12UL) /*!< HRPWM0_CSG0 SC: SSTM (Bit 12) */ -#define HRPWM0_CSG0_SC_SSTM_Msk \ - (0x3000UL) /*!< HRPWM0_CSG0 SC: SSTM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG0_SC_SVSC_Pos \ - (14UL) /*!< HRPWM0_CSG0 SC: SVSC (Bit 14) */ -#define HRPWM0_CSG0_SC_SVSC_Msk \ - (0xc000UL) /*!< HRPWM0_CSG0 SC: SVSC (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG0_SC_SWSM_Pos \ - (16UL) /*!< HRPWM0_CSG0 SC: SWSM (Bit 16) */ -#define HRPWM0_CSG0_SC_SWSM_Msk \ - (0x30000UL) /*!< HRPWM0_CSG0 SC: SWSM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG0_SC_GCFG_Pos \ - (18UL) /*!< HRPWM0_CSG0 SC: GCFG (Bit 18) */ -#define HRPWM0_CSG0_SC_GCFG_Msk \ - (0xc0000UL) /*!< HRPWM0_CSG0 SC: GCFG (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG0_SC_IST_Pos \ - (20UL) /*!< HRPWM0_CSG0 SC: IST (Bit 20) */ -#define HRPWM0_CSG0_SC_IST_Msk \ - (0x100000UL) /*!< HRPWM0_CSG0 SC: IST (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SC_PSE_Pos \ - (21UL) /*!< HRPWM0_CSG0 SC: PSE (Bit 21) */ -#define HRPWM0_CSG0_SC_PSE_Msk \ - (0x200000UL) /*!< HRPWM0_CSG0 SC: PSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SC_PSWM_Pos \ - (24UL) /*!< HRPWM0_CSG0 SC: PSWM (Bit 24) */ -#define HRPWM0_CSG0_SC_PSWM_Msk \ - (0x3000000UL) /*!< HRPWM0_CSG0 SC: PSWM (Bitfield-Mask: 0x03) */ - -/* ------------------------------- HRPWM0_CSG0_PC ------------------------------- */ -#define HRPWM0_CSG0_PC_PSWV_Pos \ - (0UL) /*!< HRPWM0_CSG0 PC: PSWV (Bit 0) */ -#define HRPWM0_CSG0_PC_PSWV_Msk \ - (0x3fUL) /*!< HRPWM0_CSG0 PC: PSWV (Bitfield-Mask: 0x3f) */ - -/* ------------------------------ HRPWM0_CSG0_DSV1 ------------------------------ */ -#define HRPWM0_CSG0_DSV1_DSV1_Pos \ - (0UL) /*!< HRPWM0_CSG0 DSV1: DSV1 (Bit 0) */ -#define HRPWM0_CSG0_DSV1_DSV1_Msk \ - (0x3ffUL) /*!< HRPWM0_CSG0 DSV1: DSV1 (Bitfield-Mask: 0x3ff) */ - -/* ------------------------------ HRPWM0_CSG0_DSV2 ------------------------------ */ -#define HRPWM0_CSG0_DSV2_DSV2_Pos \ - (0UL) /*!< HRPWM0_CSG0 DSV2: DSV2 (Bit 0) */ -#define HRPWM0_CSG0_DSV2_DSV2_Msk \ - (0x3ffUL) /*!< HRPWM0_CSG0 DSV2: DSV2 (Bitfield-Mask: 0x3ff) */ - -/* ------------------------------ HRPWM0_CSG0_SDSV1 ----------------------------- */ -#define HRPWM0_CSG0_SDSV1_SDSV1_Pos \ - (0UL) /*!< HRPWM0_CSG0 SDSV1: SDSV1 (Bit 0) */ -#define HRPWM0_CSG0_SDSV1_SDSV1_Msk \ - (0x3ffUL) /*!< HRPWM0_CSG0 SDSV1: SDSV1 (Bitfield-Mask: 0x3ff) */ - -/* ------------------------------- HRPWM0_CSG0_SPC ------------------------------ */ -#define HRPWM0_CSG0_SPC_SPSWV_Pos \ - (0UL) /*!< HRPWM0_CSG0 SPC: SPSWV (Bit 0) */ -#define HRPWM0_CSG0_SPC_SPSWV_Msk \ - (0x3fUL) /*!< HRPWM0_CSG0 SPC: SPSWV (Bitfield-Mask: 0x3f) */ - -/* ------------------------------- HRPWM0_CSG0_CC ------------------------------- */ -#define HRPWM0_CSG0_CC_IBS_Pos \ - (0UL) /*!< HRPWM0_CSG0 CC: IBS (Bit 0) */ -#define HRPWM0_CSG0_CC_IBS_Msk \ - (0xfUL) /*!< HRPWM0_CSG0 CC: IBS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG0_CC_IMCS_Pos \ - (8UL) /*!< HRPWM0_CSG0 CC: IMCS (Bit 8) */ -#define HRPWM0_CSG0_CC_IMCS_Msk \ - (0x100UL) /*!< HRPWM0_CSG0 CC: IMCS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_CC_IMCC_Pos \ - (9UL) /*!< HRPWM0_CSG0 CC: IMCC (Bit 9) */ -#define HRPWM0_CSG0_CC_IMCC_Msk \ - (0x600UL) /*!< HRPWM0_CSG0 CC: IMCC (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG0_CC_ESE_Pos \ - (11UL) /*!< HRPWM0_CSG0 CC: ESE (Bit 11) */ -#define HRPWM0_CSG0_CC_ESE_Msk \ - (0x800UL) /*!< HRPWM0_CSG0 CC: ESE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_CC_OIE_Pos \ - (12UL) /*!< HRPWM0_CSG0 CC: OIE (Bit 12) */ -#define HRPWM0_CSG0_CC_OIE_Msk \ - (0x1000UL) /*!< HRPWM0_CSG0 CC: OIE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_CC_OSE_Pos \ - (13UL) /*!< HRPWM0_CSG0 CC: OSE (Bit 13) */ -#define HRPWM0_CSG0_CC_OSE_Msk \ - (0x2000UL) /*!< HRPWM0_CSG0 CC: OSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_CC_BLMC_Pos \ - (14UL) /*!< HRPWM0_CSG0 CC: BLMC (Bit 14) */ -#define HRPWM0_CSG0_CC_BLMC_Msk \ - (0xc000UL) /*!< HRPWM0_CSG0 CC: BLMC (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG0_CC_EBE_Pos \ - (16UL) /*!< HRPWM0_CSG0 CC: EBE (Bit 16) */ -#define HRPWM0_CSG0_CC_EBE_Msk \ - (0x10000UL) /*!< HRPWM0_CSG0 CC: EBE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_CC_COFE_Pos \ - (17UL) /*!< HRPWM0_CSG0 CC: COFE (Bit 17) */ -#define HRPWM0_CSG0_CC_COFE_Msk \ - (0x20000UL) /*!< HRPWM0_CSG0 CC: COFE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_CC_COFM_Pos \ - (18UL) /*!< HRPWM0_CSG0 CC: COFM (Bit 18) */ -#define HRPWM0_CSG0_CC_COFM_Msk \ - (0x3c0000UL) /*!< HRPWM0_CSG0 CC: COFM (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG0_CC_COFC_Pos \ - (24UL) /*!< HRPWM0_CSG0 CC: COFC (Bit 24) */ -#define HRPWM0_CSG0_CC_COFC_Msk \ - (0x3000000UL) /*!< HRPWM0_CSG0 CC: COFC (Bitfield-Mask: 0x03) */ - -/* ------------------------------- HRPWM0_CSG0_PLC ------------------------------ */ -#define HRPWM0_CSG0_PLC_IPLS_Pos \ - (0UL) /*!< HRPWM0_CSG0 PLC: IPLS (Bit 0) */ -#define HRPWM0_CSG0_PLC_IPLS_Msk \ - (0xfUL) /*!< HRPWM0_CSG0 PLC: IPLS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG0_PLC_PLCL_Pos \ - (8UL) /*!< HRPWM0_CSG0 PLC: PLCL (Bit 8) */ -#define HRPWM0_CSG0_PLC_PLCL_Msk \ - (0x300UL) /*!< HRPWM0_CSG0 PLC: PLCL (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG0_PLC_PSL_Pos \ - (10UL) /*!< HRPWM0_CSG0 PLC: PSL (Bit 10) */ -#define HRPWM0_CSG0_PLC_PSL_Msk \ - (0x400UL) /*!< HRPWM0_CSG0 PLC: PSL (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_PLC_PLSW_Pos \ - (11UL) /*!< HRPWM0_CSG0 PLC: PLSW (Bit 11) */ -#define HRPWM0_CSG0_PLC_PLSW_Msk \ - (0x800UL) /*!< HRPWM0_CSG0 PLC: PLSW (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_PLC_PLEC_Pos \ - (12UL) /*!< HRPWM0_CSG0 PLC: PLEC (Bit 12) */ -#define HRPWM0_CSG0_PLC_PLEC_Msk \ - (0x3000UL) /*!< HRPWM0_CSG0 PLC: PLEC (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG0_PLC_PLXC_Pos \ - (14UL) /*!< HRPWM0_CSG0 PLC: PLXC (Bit 14) */ -#define HRPWM0_CSG0_PLC_PLXC_Msk \ - (0xc000UL) /*!< HRPWM0_CSG0 PLC: PLXC (Bitfield-Mask: 0x03) */ - -/* ------------------------------- HRPWM0_CSG0_BLV ------------------------------ */ -#define HRPWM0_CSG0_BLV_BLV_Pos \ - (0UL) /*!< HRPWM0_CSG0 BLV: BLV (Bit 0) */ -#define HRPWM0_CSG0_BLV_BLV_Msk \ - (0xffUL) /*!< HRPWM0_CSG0 BLV: BLV (Bitfield-Mask: 0xff) */ - -/* ------------------------------- HRPWM0_CSG0_SRE ------------------------------ */ -#define HRPWM0_CSG0_SRE_VLS1E_Pos \ - (0UL) /*!< HRPWM0_CSG0 SRE: VLS1E (Bit 0) */ -#define HRPWM0_CSG0_SRE_VLS1E_Msk \ - (0x1UL) /*!< HRPWM0_CSG0 SRE: VLS1E (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SRE_VLS2E_Pos \ - (1UL) /*!< HRPWM0_CSG0 SRE: VLS2E (Bit 1) */ -#define HRPWM0_CSG0_SRE_VLS2E_Msk \ - (0x2UL) /*!< HRPWM0_CSG0 SRE: VLS2E (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SRE_TRGSE_Pos \ - (2UL) /*!< HRPWM0_CSG0 SRE: TRGSE (Bit 2) */ -#define HRPWM0_CSG0_SRE_TRGSE_Msk \ - (0x4UL) /*!< HRPWM0_CSG0 SRE: TRGSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SRE_STRSE_Pos \ - (3UL) /*!< HRPWM0_CSG0 SRE: STRSE (Bit 3) */ -#define HRPWM0_CSG0_SRE_STRSE_Msk \ - (0x8UL) /*!< HRPWM0_CSG0 SRE: STRSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SRE_STPSE_Pos \ - (4UL) /*!< HRPWM0_CSG0 SRE: STPSE (Bit 4) */ -#define HRPWM0_CSG0_SRE_STPSE_Msk \ - (0x10UL) /*!< HRPWM0_CSG0 SRE: STPSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SRE_STDE_Pos \ - (5UL) /*!< HRPWM0_CSG0 SRE: STDE (Bit 5) */ -#define HRPWM0_CSG0_SRE_STDE_Msk \ - (0x20UL) /*!< HRPWM0_CSG0 SRE: STDE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SRE_CRSE_Pos \ - (6UL) /*!< HRPWM0_CSG0 SRE: CRSE (Bit 6) */ -#define HRPWM0_CSG0_SRE_CRSE_Msk \ - (0x40UL) /*!< HRPWM0_CSG0 SRE: CRSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SRE_CFSE_Pos \ - (7UL) /*!< HRPWM0_CSG0 SRE: CFSE (Bit 7) */ -#define HRPWM0_CSG0_SRE_CFSE_Msk \ - (0x80UL) /*!< HRPWM0_CSG0 SRE: CFSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SRE_CSEE_Pos \ - (8UL) /*!< HRPWM0_CSG0 SRE: CSEE (Bit 8) */ -#define HRPWM0_CSG0_SRE_CSEE_Msk \ - (0x100UL) /*!< HRPWM0_CSG0 SRE: CSEE (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_CSG0_SRS ------------------------------ */ -#define HRPWM0_CSG0_SRS_VLS1S_Pos \ - (0UL) /*!< HRPWM0_CSG0 SRS: VLS1S (Bit 0) */ -#define HRPWM0_CSG0_SRS_VLS1S_Msk \ - (0x3UL) /*!< HRPWM0_CSG0 SRS: VLS1S (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG0_SRS_VLS2S_Pos \ - (2UL) /*!< HRPWM0_CSG0 SRS: VLS2S (Bit 2) */ -#define HRPWM0_CSG0_SRS_VLS2S_Msk \ - (0xcUL) /*!< HRPWM0_CSG0 SRS: VLS2S (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG0_SRS_TRLS_Pos \ - (4UL) /*!< HRPWM0_CSG0 SRS: TRLS (Bit 4) */ -#define HRPWM0_CSG0_SRS_TRLS_Msk \ - (0x30UL) /*!< HRPWM0_CSG0 SRS: TRLS (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG0_SRS_SSLS_Pos \ - (6UL) /*!< HRPWM0_CSG0 SRS: SSLS (Bit 6) */ -#define HRPWM0_CSG0_SRS_SSLS_Msk \ - (0xc0UL) /*!< HRPWM0_CSG0 SRS: SSLS (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG0_SRS_STLS_Pos \ - (8UL) /*!< HRPWM0_CSG0 SRS: STLS (Bit 8) */ -#define HRPWM0_CSG0_SRS_STLS_Msk \ - (0x300UL) /*!< HRPWM0_CSG0 SRS: STLS (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG0_SRS_CRFLS_Pos \ - (10UL) /*!< HRPWM0_CSG0 SRS: CRFLS (Bit 10) */ -#define HRPWM0_CSG0_SRS_CRFLS_Msk \ - (0xc00UL) /*!< HRPWM0_CSG0 SRS: CRFLS (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG0_SRS_CSLS_Pos \ - (12UL) /*!< HRPWM0_CSG0 SRS: CSLS (Bit 12) */ -#define HRPWM0_CSG0_SRS_CSLS_Msk \ - (0x3000UL) /*!< HRPWM0_CSG0 SRS: CSLS (Bitfield-Mask: 0x03) */ - -/* ------------------------------- HRPWM0_CSG0_SWS ------------------------------ */ -#define HRPWM0_CSG0_SWS_SVLS1_Pos \ - (0UL) /*!< HRPWM0_CSG0 SWS: SVLS1 (Bit 0) */ -#define HRPWM0_CSG0_SWS_SVLS1_Msk \ - (0x1UL) /*!< HRPWM0_CSG0 SWS: SVLS1 (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SWS_SVLS2_Pos \ - (1UL) /*!< HRPWM0_CSG0 SWS: SVLS2 (Bit 1) */ -#define HRPWM0_CSG0_SWS_SVLS2_Msk \ - (0x2UL) /*!< HRPWM0_CSG0 SWS: SVLS2 (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SWS_STRGS_Pos \ - (2UL) /*!< HRPWM0_CSG0 SWS: STRGS (Bit 2) */ -#define HRPWM0_CSG0_SWS_STRGS_Msk \ - (0x4UL) /*!< HRPWM0_CSG0 SWS: STRGS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SWS_SSTRS_Pos \ - (3UL) /*!< HRPWM0_CSG0 SWS: SSTRS (Bit 3) */ -#define HRPWM0_CSG0_SWS_SSTRS_Msk \ - (0x8UL) /*!< HRPWM0_CSG0 SWS: SSTRS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SWS_SSTPS_Pos \ - (4UL) /*!< HRPWM0_CSG0 SWS: SSTPS (Bit 4) */ -#define HRPWM0_CSG0_SWS_SSTPS_Msk \ - (0x10UL) /*!< HRPWM0_CSG0 SWS: SSTPS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SWS_SSTD_Pos \ - (5UL) /*!< HRPWM0_CSG0 SWS: SSTD (Bit 5) */ -#define HRPWM0_CSG0_SWS_SSTD_Msk \ - (0x20UL) /*!< HRPWM0_CSG0 SWS: SSTD (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SWS_SCRS_Pos \ - (6UL) /*!< HRPWM0_CSG0 SWS: SCRS (Bit 6) */ -#define HRPWM0_CSG0_SWS_SCRS_Msk \ - (0x40UL) /*!< HRPWM0_CSG0 SWS: SCRS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SWS_SCFS_Pos \ - (7UL) /*!< HRPWM0_CSG0 SWS: SCFS (Bit 7) */ -#define HRPWM0_CSG0_SWS_SCFS_Msk \ - (0x80UL) /*!< HRPWM0_CSG0 SWS: SCFS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SWS_SCSS_Pos \ - (8UL) /*!< HRPWM0_CSG0 SWS: SCSS (Bit 8) */ -#define HRPWM0_CSG0_SWS_SCSS_Msk \ - (0x100UL) /*!< HRPWM0_CSG0 SWS: SCSS (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_CSG0_SWC ------------------------------ */ -#define HRPWM0_CSG0_SWC_CVLS1_Pos \ - (0UL) /*!< HRPWM0_CSG0 SWC: CVLS1 (Bit 0) */ -#define HRPWM0_CSG0_SWC_CVLS1_Msk \ - (0x1UL) /*!< HRPWM0_CSG0 SWC: CVLS1 (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SWC_CVLS2_Pos \ - (1UL) /*!< HRPWM0_CSG0 SWC: CVLS2 (Bit 1) */ -#define HRPWM0_CSG0_SWC_CVLS2_Msk \ - (0x2UL) /*!< HRPWM0_CSG0 SWC: CVLS2 (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SWC_CTRGS_Pos \ - (2UL) /*!< HRPWM0_CSG0 SWC: CTRGS (Bit 2) */ -#define HRPWM0_CSG0_SWC_CTRGS_Msk \ - (0x4UL) /*!< HRPWM0_CSG0 SWC: CTRGS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SWC_CSTRS_Pos \ - (3UL) /*!< HRPWM0_CSG0 SWC: CSTRS (Bit 3) */ -#define HRPWM0_CSG0_SWC_CSTRS_Msk \ - (0x8UL) /*!< HRPWM0_CSG0 SWC: CSTRS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SWC_CSTPS_Pos \ - (4UL) /*!< HRPWM0_CSG0 SWC: CSTPS (Bit 4) */ -#define HRPWM0_CSG0_SWC_CSTPS_Msk \ - (0x10UL) /*!< HRPWM0_CSG0 SWC: CSTPS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SWC_CSTD_Pos \ - (5UL) /*!< HRPWM0_CSG0 SWC: CSTD (Bit 5) */ -#define HRPWM0_CSG0_SWC_CSTD_Msk \ - (0x20UL) /*!< HRPWM0_CSG0 SWC: CSTD (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SWC_CCRS_Pos \ - (6UL) /*!< HRPWM0_CSG0 SWC: CCRS (Bit 6) */ -#define HRPWM0_CSG0_SWC_CCRS_Msk \ - (0x40UL) /*!< HRPWM0_CSG0 SWC: CCRS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SWC_CCFS_Pos \ - (7UL) /*!< HRPWM0_CSG0 SWC: CCFS (Bit 7) */ -#define HRPWM0_CSG0_SWC_CCFS_Msk \ - (0x80UL) /*!< HRPWM0_CSG0 SWC: CCFS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SWC_CCSS_Pos \ - (8UL) /*!< HRPWM0_CSG0 SWC: CCSS (Bit 8) */ -#define HRPWM0_CSG0_SWC_CCSS_Msk \ - (0x100UL) /*!< HRPWM0_CSG0 SWC: CCSS (Bitfield-Mask: 0x01) */ - -/* ------------------------------ HRPWM0_CSG0_ISTAT ----------------------------- */ -#define HRPWM0_CSG0_ISTAT_VLS1S_Pos \ - (0UL) /*!< HRPWM0_CSG0 ISTAT: VLS1S (Bit 0) */ -#define HRPWM0_CSG0_ISTAT_VLS1S_Msk \ - (0x1UL) /*!< HRPWM0_CSG0 ISTAT: VLS1S (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_ISTAT_VLS2S_Pos \ - (1UL) /*!< HRPWM0_CSG0 ISTAT: VLS2S (Bit 1) */ -#define HRPWM0_CSG0_ISTAT_VLS2S_Msk \ - (0x2UL) /*!< HRPWM0_CSG0 ISTAT: VLS2S (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_ISTAT_TRGSS_Pos \ - (2UL) /*!< HRPWM0_CSG0 ISTAT: TRGSS (Bit 2) */ -#define HRPWM0_CSG0_ISTAT_TRGSS_Msk \ - (0x4UL) /*!< HRPWM0_CSG0 ISTAT: TRGSS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_ISTAT_STRSS_Pos \ - (3UL) /*!< HRPWM0_CSG0 ISTAT: STRSS (Bit 3) */ -#define HRPWM0_CSG0_ISTAT_STRSS_Msk \ - (0x8UL) /*!< HRPWM0_CSG0 ISTAT: STRSS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_ISTAT_STPSS_Pos \ - (4UL) /*!< HRPWM0_CSG0 ISTAT: STPSS (Bit 4) */ -#define HRPWM0_CSG0_ISTAT_STPSS_Msk \ - (0x10UL) /*!< HRPWM0_CSG0 ISTAT: STPSS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_ISTAT_STDS_Pos \ - (5UL) /*!< HRPWM0_CSG0 ISTAT: STDS (Bit 5) */ -#define HRPWM0_CSG0_ISTAT_STDS_Msk \ - (0x20UL) /*!< HRPWM0_CSG0 ISTAT: STDS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_ISTAT_CRSS_Pos \ - (6UL) /*!< HRPWM0_CSG0 ISTAT: CRSS (Bit 6) */ -#define HRPWM0_CSG0_ISTAT_CRSS_Msk \ - (0x40UL) /*!< HRPWM0_CSG0 ISTAT: CRSS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_ISTAT_CFSS_Pos \ - (7UL) /*!< HRPWM0_CSG0 ISTAT: CFSS (Bit 7) */ -#define HRPWM0_CSG0_ISTAT_CFSS_Msk \ - (0x80UL) /*!< HRPWM0_CSG0 ISTAT: CFSS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_ISTAT_CSES_Pos \ - (8UL) /*!< HRPWM0_CSG0 ISTAT: CSES (Bit 8) */ -#define HRPWM0_CSG0_ISTAT_CSES_Msk \ - (0x100UL) /*!< HRPWM0_CSG0 ISTAT: CSES (Bitfield-Mask: 0x01) */ - -/* ================================================================================ */ -/* ================ struct 'HRPWM0_CSG1' Position & Mask ================ */ -/* ================================================================================ */ - -/* ------------------------------- HRPWM0_CSG1_DCI ------------------------------ */ -#define HRPWM0_CSG1_DCI_SVIS_Pos \ - (0UL) /*!< HRPWM0_CSG1 DCI: SVIS (Bit 0) */ -#define HRPWM0_CSG1_DCI_SVIS_Msk \ - (0xfUL) /*!< HRPWM0_CSG1 DCI: SVIS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG1_DCI_STRIS_Pos \ - (4UL) /*!< HRPWM0_CSG1 DCI: STRIS (Bit 4) */ -#define HRPWM0_CSG1_DCI_STRIS_Msk \ - (0xf0UL) /*!< HRPWM0_CSG1 DCI: STRIS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG1_DCI_STPIS_Pos \ - (8UL) /*!< HRPWM0_CSG1 DCI: STPIS (Bit 8) */ -#define HRPWM0_CSG1_DCI_STPIS_Msk \ - (0xf00UL) /*!< HRPWM0_CSG1 DCI: STPIS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG1_DCI_TRGIS_Pos \ - (12UL) /*!< HRPWM0_CSG1 DCI: TRGIS (Bit 12) */ -#define HRPWM0_CSG1_DCI_TRGIS_Msk \ - (0xf000UL) /*!< HRPWM0_CSG1 DCI: TRGIS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG1_DCI_STIS_Pos \ - (16UL) /*!< HRPWM0_CSG1 DCI: STIS (Bit 16) */ -#define HRPWM0_CSG1_DCI_STIS_Msk \ - (0xf0000UL) /*!< HRPWM0_CSG1 DCI: STIS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG1_DCI_SCS_Pos \ - (20UL) /*!< HRPWM0_CSG1 DCI: SCS (Bit 20) */ -#define HRPWM0_CSG1_DCI_SCS_Msk \ - (0x300000UL) /*!< HRPWM0_CSG1 DCI: SCS (Bitfield-Mask: 0x03) */ - -/* ------------------------------- HRPWM0_CSG1_IES ------------------------------ */ -#define HRPWM0_CSG1_IES_SVLS_Pos \ - (0UL) /*!< HRPWM0_CSG1 IES: SVLS (Bit 0) */ -#define HRPWM0_CSG1_IES_SVLS_Msk \ - (0x3UL) /*!< HRPWM0_CSG1 IES: SVLS (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG1_IES_STRES_Pos \ - (2UL) /*!< HRPWM0_CSG1 IES: STRES (Bit 2) */ -#define HRPWM0_CSG1_IES_STRES_Msk \ - (0xcUL) /*!< HRPWM0_CSG1 IES: STRES (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG1_IES_STPES_Pos \ - (4UL) /*!< HRPWM0_CSG1 IES: STPES (Bit 4) */ -#define HRPWM0_CSG1_IES_STPES_Msk \ - (0x30UL) /*!< HRPWM0_CSG1 IES: STPES (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG1_IES_TRGES_Pos \ - (6UL) /*!< HRPWM0_CSG1 IES: TRGES (Bit 6) */ -#define HRPWM0_CSG1_IES_TRGES_Msk \ - (0xc0UL) /*!< HRPWM0_CSG1 IES: TRGES (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG1_IES_STES_Pos \ - (8UL) /*!< HRPWM0_CSG1 IES: STES (Bit 8) */ -#define HRPWM0_CSG1_IES_STES_Msk \ - (0x300UL) /*!< HRPWM0_CSG1 IES: STES (Bitfield-Mask: 0x03) */ - -/* ------------------------------- HRPWM0_CSG1_SC ------------------------------- */ -#define HRPWM0_CSG1_SC_PSRM_Pos \ - (0UL) /*!< HRPWM0_CSG1 SC: PSRM (Bit 0) */ -#define HRPWM0_CSG1_SC_PSRM_Msk \ - (0x3UL) /*!< HRPWM0_CSG1 SC: PSRM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG1_SC_PSTM_Pos \ - (2UL) /*!< HRPWM0_CSG1 SC: PSTM (Bit 2) */ -#define HRPWM0_CSG1_SC_PSTM_Msk \ - (0xcUL) /*!< HRPWM0_CSG1 SC: PSTM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG1_SC_FPD_Pos \ - (4UL) /*!< HRPWM0_CSG1 SC: FPD (Bit 4) */ -#define HRPWM0_CSG1_SC_FPD_Msk \ - (0x10UL) /*!< HRPWM0_CSG1 SC: FPD (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SC_PSV_Pos \ - (5UL) /*!< HRPWM0_CSG1 SC: PSV (Bit 5) */ -#define HRPWM0_CSG1_SC_PSV_Msk \ - (0x60UL) /*!< HRPWM0_CSG1 SC: PSV (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG1_SC_SCM_Pos \ - (8UL) /*!< HRPWM0_CSG1 SC: SCM (Bit 8) */ -#define HRPWM0_CSG1_SC_SCM_Msk \ - (0x300UL) /*!< HRPWM0_CSG1 SC: SCM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG1_SC_SSRM_Pos \ - (10UL) /*!< HRPWM0_CSG1 SC: SSRM (Bit 10) */ -#define HRPWM0_CSG1_SC_SSRM_Msk \ - (0xc00UL) /*!< HRPWM0_CSG1 SC: SSRM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG1_SC_SSTM_Pos \ - (12UL) /*!< HRPWM0_CSG1 SC: SSTM (Bit 12) */ -#define HRPWM0_CSG1_SC_SSTM_Msk \ - (0x3000UL) /*!< HRPWM0_CSG1 SC: SSTM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG1_SC_SVSC_Pos \ - (14UL) /*!< HRPWM0_CSG1 SC: SVSC (Bit 14) */ -#define HRPWM0_CSG1_SC_SVSC_Msk \ - (0xc000UL) /*!< HRPWM0_CSG1 SC: SVSC (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG1_SC_SWSM_Pos \ - (16UL) /*!< HRPWM0_CSG1 SC: SWSM (Bit 16) */ -#define HRPWM0_CSG1_SC_SWSM_Msk \ - (0x30000UL) /*!< HRPWM0_CSG1 SC: SWSM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG1_SC_GCFG_Pos \ - (18UL) /*!< HRPWM0_CSG1 SC: GCFG (Bit 18) */ -#define HRPWM0_CSG1_SC_GCFG_Msk \ - (0xc0000UL) /*!< HRPWM0_CSG1 SC: GCFG (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG1_SC_IST_Pos \ - (20UL) /*!< HRPWM0_CSG1 SC: IST (Bit 20) */ -#define HRPWM0_CSG1_SC_IST_Msk \ - (0x100000UL) /*!< HRPWM0_CSG1 SC: IST (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SC_PSE_Pos \ - (21UL) /*!< HRPWM0_CSG1 SC: PSE (Bit 21) */ -#define HRPWM0_CSG1_SC_PSE_Msk \ - (0x200000UL) /*!< HRPWM0_CSG1 SC: PSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SC_PSWM_Pos \ - (24UL) /*!< HRPWM0_CSG1 SC: PSWM (Bit 24) */ -#define HRPWM0_CSG1_SC_PSWM_Msk \ - (0x3000000UL) /*!< HRPWM0_CSG1 SC: PSWM (Bitfield-Mask: 0x03) */ - -/* ------------------------------- HRPWM0_CSG1_PC ------------------------------- */ -#define HRPWM0_CSG1_PC_PSWV_Pos \ - (0UL) /*!< HRPWM0_CSG1 PC: PSWV (Bit 0) */ -#define HRPWM0_CSG1_PC_PSWV_Msk \ - (0x3fUL) /*!< HRPWM0_CSG1 PC: PSWV (Bitfield-Mask: 0x3f) */ - -/* ------------------------------ HRPWM0_CSG1_DSV1 ------------------------------ */ -#define HRPWM0_CSG1_DSV1_DSV1_Pos \ - (0UL) /*!< HRPWM0_CSG1 DSV1: DSV1 (Bit 0) */ -#define HRPWM0_CSG1_DSV1_DSV1_Msk \ - (0x3ffUL) /*!< HRPWM0_CSG1 DSV1: DSV1 (Bitfield-Mask: 0x3ff) */ - -/* ------------------------------ HRPWM0_CSG1_DSV2 ------------------------------ */ -#define HRPWM0_CSG1_DSV2_DSV2_Pos \ - (0UL) /*!< HRPWM0_CSG1 DSV2: DSV2 (Bit 0) */ -#define HRPWM0_CSG1_DSV2_DSV2_Msk \ - (0x3ffUL) /*!< HRPWM0_CSG1 DSV2: DSV2 (Bitfield-Mask: 0x3ff) */ - -/* ------------------------------ HRPWM0_CSG1_SDSV1 ----------------------------- */ -#define HRPWM0_CSG1_SDSV1_SDSV1_Pos \ - (0UL) /*!< HRPWM0_CSG1 SDSV1: SDSV1 (Bit 0) */ -#define HRPWM0_CSG1_SDSV1_SDSV1_Msk \ - (0x3ffUL) /*!< HRPWM0_CSG1 SDSV1: SDSV1 (Bitfield-Mask: 0x3ff) */ - -/* ------------------------------- HRPWM0_CSG1_SPC ------------------------------ */ -#define HRPWM0_CSG1_SPC_SPSWV_Pos \ - (0UL) /*!< HRPWM0_CSG1 SPC: SPSWV (Bit 0) */ -#define HRPWM0_CSG1_SPC_SPSWV_Msk \ - (0x3fUL) /*!< HRPWM0_CSG1 SPC: SPSWV (Bitfield-Mask: 0x3f) */ - -/* ------------------------------- HRPWM0_CSG1_CC ------------------------------- */ -#define HRPWM0_CSG1_CC_IBS_Pos \ - (0UL) /*!< HRPWM0_CSG1 CC: IBS (Bit 0) */ -#define HRPWM0_CSG1_CC_IBS_Msk \ - (0xfUL) /*!< HRPWM0_CSG1 CC: IBS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG1_CC_IMCS_Pos \ - (8UL) /*!< HRPWM0_CSG1 CC: IMCS (Bit 8) */ -#define HRPWM0_CSG1_CC_IMCS_Msk \ - (0x100UL) /*!< HRPWM0_CSG1 CC: IMCS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_CC_IMCC_Pos \ - (9UL) /*!< HRPWM0_CSG1 CC: IMCC (Bit 9) */ -#define HRPWM0_CSG1_CC_IMCC_Msk \ - (0x600UL) /*!< HRPWM0_CSG1 CC: IMCC (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG1_CC_ESE_Pos \ - (11UL) /*!< HRPWM0_CSG1 CC: ESE (Bit 11) */ -#define HRPWM0_CSG1_CC_ESE_Msk \ - (0x800UL) /*!< HRPWM0_CSG1 CC: ESE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_CC_OIE_Pos \ - (12UL) /*!< HRPWM0_CSG1 CC: OIE (Bit 12) */ -#define HRPWM0_CSG1_CC_OIE_Msk \ - (0x1000UL) /*!< HRPWM0_CSG1 CC: OIE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_CC_OSE_Pos \ - (13UL) /*!< HRPWM0_CSG1 CC: OSE (Bit 13) */ -#define HRPWM0_CSG1_CC_OSE_Msk \ - (0x2000UL) /*!< HRPWM0_CSG1 CC: OSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_CC_BLMC_Pos \ - (14UL) /*!< HRPWM0_CSG1 CC: BLMC (Bit 14) */ -#define HRPWM0_CSG1_CC_BLMC_Msk \ - (0xc000UL) /*!< HRPWM0_CSG1 CC: BLMC (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG1_CC_EBE_Pos \ - (16UL) /*!< HRPWM0_CSG1 CC: EBE (Bit 16) */ -#define HRPWM0_CSG1_CC_EBE_Msk \ - (0x10000UL) /*!< HRPWM0_CSG1 CC: EBE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_CC_COFE_Pos \ - (17UL) /*!< HRPWM0_CSG1 CC: COFE (Bit 17) */ -#define HRPWM0_CSG1_CC_COFE_Msk \ - (0x20000UL) /*!< HRPWM0_CSG1 CC: COFE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_CC_COFM_Pos \ - (18UL) /*!< HRPWM0_CSG1 CC: COFM (Bit 18) */ -#define HRPWM0_CSG1_CC_COFM_Msk \ - (0x3c0000UL) /*!< HRPWM0_CSG1 CC: COFM (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG1_CC_COFC_Pos \ - (24UL) /*!< HRPWM0_CSG1 CC: COFC (Bit 24) */ -#define HRPWM0_CSG1_CC_COFC_Msk \ - (0x3000000UL) /*!< HRPWM0_CSG1 CC: COFC (Bitfield-Mask: 0x03) */ - -/* ------------------------------- HRPWM0_CSG1_PLC ------------------------------ */ -#define HRPWM0_CSG1_PLC_IPLS_Pos \ - (0UL) /*!< HRPWM0_CSG1 PLC: IPLS (Bit 0) */ -#define HRPWM0_CSG1_PLC_IPLS_Msk \ - (0xfUL) /*!< HRPWM0_CSG1 PLC: IPLS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG1_PLC_PLCL_Pos \ - (8UL) /*!< HRPWM0_CSG1 PLC: PLCL (Bit 8) */ -#define HRPWM0_CSG1_PLC_PLCL_Msk \ - (0x300UL) /*!< HRPWM0_CSG1 PLC: PLCL (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG1_PLC_PSL_Pos \ - (10UL) /*!< HRPWM0_CSG1 PLC: PSL (Bit 10) */ -#define HRPWM0_CSG1_PLC_PSL_Msk \ - (0x400UL) /*!< HRPWM0_CSG1 PLC: PSL (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_PLC_PLSW_Pos \ - (11UL) /*!< HRPWM0_CSG1 PLC: PLSW (Bit 11) */ -#define HRPWM0_CSG1_PLC_PLSW_Msk \ - (0x800UL) /*!< HRPWM0_CSG1 PLC: PLSW (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_PLC_PLEC_Pos \ - (12UL) /*!< HRPWM0_CSG1 PLC: PLEC (Bit 12) */ -#define HRPWM0_CSG1_PLC_PLEC_Msk \ - (0x3000UL) /*!< HRPWM0_CSG1 PLC: PLEC (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG1_PLC_PLXC_Pos \ - (14UL) /*!< HRPWM0_CSG1 PLC: PLXC (Bit 14) */ -#define HRPWM0_CSG1_PLC_PLXC_Msk \ - (0xc000UL) /*!< HRPWM0_CSG1 PLC: PLXC (Bitfield-Mask: 0x03) */ - -/* ------------------------------- HRPWM0_CSG1_BLV ------------------------------ */ -#define HRPWM0_CSG1_BLV_BLV_Pos \ - (0UL) /*!< HRPWM0_CSG1 BLV: BLV (Bit 0) */ -#define HRPWM0_CSG1_BLV_BLV_Msk \ - (0xffUL) /*!< HRPWM0_CSG1 BLV: BLV (Bitfield-Mask: 0xff) */ - -/* ------------------------------- HRPWM0_CSG1_SRE ------------------------------ */ -#define HRPWM0_CSG1_SRE_VLS1E_Pos \ - (0UL) /*!< HRPWM0_CSG1 SRE: VLS1E (Bit 0) */ -#define HRPWM0_CSG1_SRE_VLS1E_Msk \ - (0x1UL) /*!< HRPWM0_CSG1 SRE: VLS1E (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SRE_VLS2E_Pos \ - (1UL) /*!< HRPWM0_CSG1 SRE: VLS2E (Bit 1) */ -#define HRPWM0_CSG1_SRE_VLS2E_Msk \ - (0x2UL) /*!< HRPWM0_CSG1 SRE: VLS2E (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SRE_TRGSE_Pos \ - (2UL) /*!< HRPWM0_CSG1 SRE: TRGSE (Bit 2) */ -#define HRPWM0_CSG1_SRE_TRGSE_Msk \ - (0x4UL) /*!< HRPWM0_CSG1 SRE: TRGSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SRE_STRSE_Pos \ - (3UL) /*!< HRPWM0_CSG1 SRE: STRSE (Bit 3) */ -#define HRPWM0_CSG1_SRE_STRSE_Msk \ - (0x8UL) /*!< HRPWM0_CSG1 SRE: STRSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SRE_STPSE_Pos \ - (4UL) /*!< HRPWM0_CSG1 SRE: STPSE (Bit 4) */ -#define HRPWM0_CSG1_SRE_STPSE_Msk \ - (0x10UL) /*!< HRPWM0_CSG1 SRE: STPSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SRE_STDE_Pos \ - (5UL) /*!< HRPWM0_CSG1 SRE: STDE (Bit 5) */ -#define HRPWM0_CSG1_SRE_STDE_Msk \ - (0x20UL) /*!< HRPWM0_CSG1 SRE: STDE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SRE_CRSE_Pos \ - (6UL) /*!< HRPWM0_CSG1 SRE: CRSE (Bit 6) */ -#define HRPWM0_CSG1_SRE_CRSE_Msk \ - (0x40UL) /*!< HRPWM0_CSG1 SRE: CRSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SRE_CFSE_Pos \ - (7UL) /*!< HRPWM0_CSG1 SRE: CFSE (Bit 7) */ -#define HRPWM0_CSG1_SRE_CFSE_Msk \ - (0x80UL) /*!< HRPWM0_CSG1 SRE: CFSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SRE_CSEE_Pos \ - (8UL) /*!< HRPWM0_CSG1 SRE: CSEE (Bit 8) */ -#define HRPWM0_CSG1_SRE_CSEE_Msk \ - (0x100UL) /*!< HRPWM0_CSG1 SRE: CSEE (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_CSG1_SRS ------------------------------ */ -#define HRPWM0_CSG1_SRS_VLS1S_Pos \ - (0UL) /*!< HRPWM0_CSG1 SRS: VLS1S (Bit 0) */ -#define HRPWM0_CSG1_SRS_VLS1S_Msk \ - (0x3UL) /*!< HRPWM0_CSG1 SRS: VLS1S (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG1_SRS_VLS2S_Pos \ - (2UL) /*!< HRPWM0_CSG1 SRS: VLS2S (Bit 2) */ -#define HRPWM0_CSG1_SRS_VLS2S_Msk \ - (0xcUL) /*!< HRPWM0_CSG1 SRS: VLS2S (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG1_SRS_TRLS_Pos \ - (4UL) /*!< HRPWM0_CSG1 SRS: TRLS (Bit 4) */ -#define HRPWM0_CSG1_SRS_TRLS_Msk \ - (0x30UL) /*!< HRPWM0_CSG1 SRS: TRLS (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG1_SRS_SSLS_Pos \ - (6UL) /*!< HRPWM0_CSG1 SRS: SSLS (Bit 6) */ -#define HRPWM0_CSG1_SRS_SSLS_Msk \ - (0xc0UL) /*!< HRPWM0_CSG1 SRS: SSLS (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG1_SRS_STLS_Pos \ - (8UL) /*!< HRPWM0_CSG1 SRS: STLS (Bit 8) */ -#define HRPWM0_CSG1_SRS_STLS_Msk \ - (0x300UL) /*!< HRPWM0_CSG1 SRS: STLS (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG1_SRS_CRFLS_Pos \ - (10UL) /*!< HRPWM0_CSG1 SRS: CRFLS (Bit 10) */ -#define HRPWM0_CSG1_SRS_CRFLS_Msk \ - (0xc00UL) /*!< HRPWM0_CSG1 SRS: CRFLS (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG1_SRS_CSLS_Pos \ - (12UL) /*!< HRPWM0_CSG1 SRS: CSLS (Bit 12) */ -#define HRPWM0_CSG1_SRS_CSLS_Msk \ - (0x3000UL) /*!< HRPWM0_CSG1 SRS: CSLS (Bitfield-Mask: 0x03) */ - -/* ------------------------------- HRPWM0_CSG1_SWS ------------------------------ */ -#define HRPWM0_CSG1_SWS_SVLS1_Pos \ - (0UL) /*!< HRPWM0_CSG1 SWS: SVLS1 (Bit 0) */ -#define HRPWM0_CSG1_SWS_SVLS1_Msk \ - (0x1UL) /*!< HRPWM0_CSG1 SWS: SVLS1 (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SWS_SVLS2_Pos \ - (1UL) /*!< HRPWM0_CSG1 SWS: SVLS2 (Bit 1) */ -#define HRPWM0_CSG1_SWS_SVLS2_Msk \ - (0x2UL) /*!< HRPWM0_CSG1 SWS: SVLS2 (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SWS_STRGS_Pos \ - (2UL) /*!< HRPWM0_CSG1 SWS: STRGS (Bit 2) */ -#define HRPWM0_CSG1_SWS_STRGS_Msk \ - (0x4UL) /*!< HRPWM0_CSG1 SWS: STRGS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SWS_SSTRS_Pos \ - (3UL) /*!< HRPWM0_CSG1 SWS: SSTRS (Bit 3) */ -#define HRPWM0_CSG1_SWS_SSTRS_Msk \ - (0x8UL) /*!< HRPWM0_CSG1 SWS: SSTRS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SWS_SSTPS_Pos \ - (4UL) /*!< HRPWM0_CSG1 SWS: SSTPS (Bit 4) */ -#define HRPWM0_CSG1_SWS_SSTPS_Msk \ - (0x10UL) /*!< HRPWM0_CSG1 SWS: SSTPS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SWS_SSTD_Pos \ - (5UL) /*!< HRPWM0_CSG1 SWS: SSTD (Bit 5) */ -#define HRPWM0_CSG1_SWS_SSTD_Msk \ - (0x20UL) /*!< HRPWM0_CSG1 SWS: SSTD (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SWS_SCRS_Pos \ - (6UL) /*!< HRPWM0_CSG1 SWS: SCRS (Bit 6) */ -#define HRPWM0_CSG1_SWS_SCRS_Msk \ - (0x40UL) /*!< HRPWM0_CSG1 SWS: SCRS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SWS_SCFS_Pos \ - (7UL) /*!< HRPWM0_CSG1 SWS: SCFS (Bit 7) */ -#define HRPWM0_CSG1_SWS_SCFS_Msk \ - (0x80UL) /*!< HRPWM0_CSG1 SWS: SCFS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SWS_SCSS_Pos \ - (8UL) /*!< HRPWM0_CSG1 SWS: SCSS (Bit 8) */ -#define HRPWM0_CSG1_SWS_SCSS_Msk \ - (0x100UL) /*!< HRPWM0_CSG1 SWS: SCSS (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_CSG1_SWC ------------------------------ */ -#define HRPWM0_CSG1_SWC_CVLS1_Pos \ - (0UL) /*!< HRPWM0_CSG1 SWC: CVLS1 (Bit 0) */ -#define HRPWM0_CSG1_SWC_CVLS1_Msk \ - (0x1UL) /*!< HRPWM0_CSG1 SWC: CVLS1 (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SWC_CVLS2_Pos \ - (1UL) /*!< HRPWM0_CSG1 SWC: CVLS2 (Bit 1) */ -#define HRPWM0_CSG1_SWC_CVLS2_Msk \ - (0x2UL) /*!< HRPWM0_CSG1 SWC: CVLS2 (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SWC_CTRGS_Pos \ - (2UL) /*!< HRPWM0_CSG1 SWC: CTRGS (Bit 2) */ -#define HRPWM0_CSG1_SWC_CTRGS_Msk \ - (0x4UL) /*!< HRPWM0_CSG1 SWC: CTRGS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SWC_CSTRS_Pos \ - (3UL) /*!< HRPWM0_CSG1 SWC: CSTRS (Bit 3) */ -#define HRPWM0_CSG1_SWC_CSTRS_Msk \ - (0x8UL) /*!< HRPWM0_CSG1 SWC: CSTRS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SWC_CSTPS_Pos \ - (4UL) /*!< HRPWM0_CSG1 SWC: CSTPS (Bit 4) */ -#define HRPWM0_CSG1_SWC_CSTPS_Msk \ - (0x10UL) /*!< HRPWM0_CSG1 SWC: CSTPS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SWC_CSTD_Pos \ - (5UL) /*!< HRPWM0_CSG1 SWC: CSTD (Bit 5) */ -#define HRPWM0_CSG1_SWC_CSTD_Msk \ - (0x20UL) /*!< HRPWM0_CSG1 SWC: CSTD (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SWC_CCRS_Pos \ - (6UL) /*!< HRPWM0_CSG1 SWC: CCRS (Bit 6) */ -#define HRPWM0_CSG1_SWC_CCRS_Msk \ - (0x40UL) /*!< HRPWM0_CSG1 SWC: CCRS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SWC_CCFS_Pos \ - (7UL) /*!< HRPWM0_CSG1 SWC: CCFS (Bit 7) */ -#define HRPWM0_CSG1_SWC_CCFS_Msk \ - (0x80UL) /*!< HRPWM0_CSG1 SWC: CCFS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SWC_CCSS_Pos \ - (8UL) /*!< HRPWM0_CSG1 SWC: CCSS (Bit 8) */ -#define HRPWM0_CSG1_SWC_CCSS_Msk \ - (0x100UL) /*!< HRPWM0_CSG1 SWC: CCSS (Bitfield-Mask: 0x01) */ - -/* ------------------------------ HRPWM0_CSG1_ISTAT ----------------------------- */ -#define HRPWM0_CSG1_ISTAT_VLS1S_Pos \ - (0UL) /*!< HRPWM0_CSG1 ISTAT: VLS1S (Bit 0) */ -#define HRPWM0_CSG1_ISTAT_VLS1S_Msk \ - (0x1UL) /*!< HRPWM0_CSG1 ISTAT: VLS1S (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_ISTAT_VLS2S_Pos \ - (1UL) /*!< HRPWM0_CSG1 ISTAT: VLS2S (Bit 1) */ -#define HRPWM0_CSG1_ISTAT_VLS2S_Msk \ - (0x2UL) /*!< HRPWM0_CSG1 ISTAT: VLS2S (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_ISTAT_TRGSS_Pos \ - (2UL) /*!< HRPWM0_CSG1 ISTAT: TRGSS (Bit 2) */ -#define HRPWM0_CSG1_ISTAT_TRGSS_Msk \ - (0x4UL) /*!< HRPWM0_CSG1 ISTAT: TRGSS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_ISTAT_STRSS_Pos \ - (3UL) /*!< HRPWM0_CSG1 ISTAT: STRSS (Bit 3) */ -#define HRPWM0_CSG1_ISTAT_STRSS_Msk \ - (0x8UL) /*!< HRPWM0_CSG1 ISTAT: STRSS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_ISTAT_STPSS_Pos \ - (4UL) /*!< HRPWM0_CSG1 ISTAT: STPSS (Bit 4) */ -#define HRPWM0_CSG1_ISTAT_STPSS_Msk \ - (0x10UL) /*!< HRPWM0_CSG1 ISTAT: STPSS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_ISTAT_STDS_Pos \ - (5UL) /*!< HRPWM0_CSG1 ISTAT: STDS (Bit 5) */ -#define HRPWM0_CSG1_ISTAT_STDS_Msk \ - (0x20UL) /*!< HRPWM0_CSG1 ISTAT: STDS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_ISTAT_CRSS_Pos \ - (6UL) /*!< HRPWM0_CSG1 ISTAT: CRSS (Bit 6) */ -#define HRPWM0_CSG1_ISTAT_CRSS_Msk \ - (0x40UL) /*!< HRPWM0_CSG1 ISTAT: CRSS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_ISTAT_CFSS_Pos \ - (7UL) /*!< HRPWM0_CSG1 ISTAT: CFSS (Bit 7) */ -#define HRPWM0_CSG1_ISTAT_CFSS_Msk \ - (0x80UL) /*!< HRPWM0_CSG1 ISTAT: CFSS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_ISTAT_CSES_Pos \ - (8UL) /*!< HRPWM0_CSG1 ISTAT: CSES (Bit 8) */ -#define HRPWM0_CSG1_ISTAT_CSES_Msk \ - (0x100UL) /*!< HRPWM0_CSG1 ISTAT: CSES (Bitfield-Mask: 0x01) */ - -/* ================================================================================ */ -/* ================ struct 'HRPWM0_CSG2' Position & Mask ================ */ -/* ================================================================================ */ - -/* ------------------------------- HRPWM0_CSG2_DCI ------------------------------ */ -#define HRPWM0_CSG2_DCI_SVIS_Pos \ - (0UL) /*!< HRPWM0_CSG2 DCI: SVIS (Bit 0) */ -#define HRPWM0_CSG2_DCI_SVIS_Msk \ - (0xfUL) /*!< HRPWM0_CSG2 DCI: SVIS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG2_DCI_STRIS_Pos \ - (4UL) /*!< HRPWM0_CSG2 DCI: STRIS (Bit 4) */ -#define HRPWM0_CSG2_DCI_STRIS_Msk \ - (0xf0UL) /*!< HRPWM0_CSG2 DCI: STRIS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG2_DCI_STPIS_Pos \ - (8UL) /*!< HRPWM0_CSG2 DCI: STPIS (Bit 8) */ -#define HRPWM0_CSG2_DCI_STPIS_Msk \ - (0xf00UL) /*!< HRPWM0_CSG2 DCI: STPIS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG2_DCI_TRGIS_Pos \ - (12UL) /*!< HRPWM0_CSG2 DCI: TRGIS (Bit 12) */ -#define HRPWM0_CSG2_DCI_TRGIS_Msk \ - (0xf000UL) /*!< HRPWM0_CSG2 DCI: TRGIS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG2_DCI_STIS_Pos \ - (16UL) /*!< HRPWM0_CSG2 DCI: STIS (Bit 16) */ -#define HRPWM0_CSG2_DCI_STIS_Msk \ - (0xf0000UL) /*!< HRPWM0_CSG2 DCI: STIS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG2_DCI_SCS_Pos \ - (20UL) /*!< HRPWM0_CSG2 DCI: SCS (Bit 20) */ -#define HRPWM0_CSG2_DCI_SCS_Msk \ - (0x300000UL) /*!< HRPWM0_CSG2 DCI: SCS (Bitfield-Mask: 0x03) */ - -/* ------------------------------- HRPWM0_CSG2_IES ------------------------------ */ -#define HRPWM0_CSG2_IES_SVLS_Pos \ - (0UL) /*!< HRPWM0_CSG2 IES: SVLS (Bit 0) */ -#define HRPWM0_CSG2_IES_SVLS_Msk \ - (0x3UL) /*!< HRPWM0_CSG2 IES: SVLS (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG2_IES_STRES_Pos \ - (2UL) /*!< HRPWM0_CSG2 IES: STRES (Bit 2) */ -#define HRPWM0_CSG2_IES_STRES_Msk \ - (0xcUL) /*!< HRPWM0_CSG2 IES: STRES (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG2_IES_STPES_Pos \ - (4UL) /*!< HRPWM0_CSG2 IES: STPES (Bit 4) */ -#define HRPWM0_CSG2_IES_STPES_Msk \ - (0x30UL) /*!< HRPWM0_CSG2 IES: STPES (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG2_IES_TRGES_Pos \ - (6UL) /*!< HRPWM0_CSG2 IES: TRGES (Bit 6) */ -#define HRPWM0_CSG2_IES_TRGES_Msk \ - (0xc0UL) /*!< HRPWM0_CSG2 IES: TRGES (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG2_IES_STES_Pos \ - (8UL) /*!< HRPWM0_CSG2 IES: STES (Bit 8) */ -#define HRPWM0_CSG2_IES_STES_Msk \ - (0x300UL) /*!< HRPWM0_CSG2 IES: STES (Bitfield-Mask: 0x03) */ - -/* ------------------------------- HRPWM0_CSG2_SC ------------------------------- */ -#define HRPWM0_CSG2_SC_PSRM_Pos \ - (0UL) /*!< HRPWM0_CSG2 SC: PSRM (Bit 0) */ -#define HRPWM0_CSG2_SC_PSRM_Msk \ - (0x3UL) /*!< HRPWM0_CSG2 SC: PSRM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG2_SC_PSTM_Pos \ - (2UL) /*!< HRPWM0_CSG2 SC: PSTM (Bit 2) */ -#define HRPWM0_CSG2_SC_PSTM_Msk \ - (0xcUL) /*!< HRPWM0_CSG2 SC: PSTM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG2_SC_FPD_Pos \ - (4UL) /*!< HRPWM0_CSG2 SC: FPD (Bit 4) */ -#define HRPWM0_CSG2_SC_FPD_Msk \ - (0x10UL) /*!< HRPWM0_CSG2 SC: FPD (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SC_PSV_Pos \ - (5UL) /*!< HRPWM0_CSG2 SC: PSV (Bit 5) */ -#define HRPWM0_CSG2_SC_PSV_Msk \ - (0x60UL) /*!< HRPWM0_CSG2 SC: PSV (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG2_SC_SCM_Pos \ - (8UL) /*!< HRPWM0_CSG2 SC: SCM (Bit 8) */ -#define HRPWM0_CSG2_SC_SCM_Msk \ - (0x300UL) /*!< HRPWM0_CSG2 SC: SCM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG2_SC_SSRM_Pos \ - (10UL) /*!< HRPWM0_CSG2 SC: SSRM (Bit 10) */ -#define HRPWM0_CSG2_SC_SSRM_Msk \ - (0xc00UL) /*!< HRPWM0_CSG2 SC: SSRM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG2_SC_SSTM_Pos \ - (12UL) /*!< HRPWM0_CSG2 SC: SSTM (Bit 12) */ -#define HRPWM0_CSG2_SC_SSTM_Msk \ - (0x3000UL) /*!< HRPWM0_CSG2 SC: SSTM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG2_SC_SVSC_Pos \ - (14UL) /*!< HRPWM0_CSG2 SC: SVSC (Bit 14) */ -#define HRPWM0_CSG2_SC_SVSC_Msk \ - (0xc000UL) /*!< HRPWM0_CSG2 SC: SVSC (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG2_SC_SWSM_Pos \ - (16UL) /*!< HRPWM0_CSG2 SC: SWSM (Bit 16) */ -#define HRPWM0_CSG2_SC_SWSM_Msk \ - (0x30000UL) /*!< HRPWM0_CSG2 SC: SWSM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG2_SC_GCFG_Pos \ - (18UL) /*!< HRPWM0_CSG2 SC: GCFG (Bit 18) */ -#define HRPWM0_CSG2_SC_GCFG_Msk \ - (0xc0000UL) /*!< HRPWM0_CSG2 SC: GCFG (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG2_SC_IST_Pos \ - (20UL) /*!< HRPWM0_CSG2 SC: IST (Bit 20) */ -#define HRPWM0_CSG2_SC_IST_Msk \ - (0x100000UL) /*!< HRPWM0_CSG2 SC: IST (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SC_PSE_Pos \ - (21UL) /*!< HRPWM0_CSG2 SC: PSE (Bit 21) */ -#define HRPWM0_CSG2_SC_PSE_Msk \ - (0x200000UL) /*!< HRPWM0_CSG2 SC: PSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SC_PSWM_Pos \ - (24UL) /*!< HRPWM0_CSG2 SC: PSWM (Bit 24) */ -#define HRPWM0_CSG2_SC_PSWM_Msk \ - (0x3000000UL) /*!< HRPWM0_CSG2 SC: PSWM (Bitfield-Mask: 0x03) */ - -/* ------------------------------- HRPWM0_CSG2_PC ------------------------------- */ -#define HRPWM0_CSG2_PC_PSWV_Pos \ - (0UL) /*!< HRPWM0_CSG2 PC: PSWV (Bit 0) */ -#define HRPWM0_CSG2_PC_PSWV_Msk \ - (0x3fUL) /*!< HRPWM0_CSG2 PC: PSWV (Bitfield-Mask: 0x3f) */ - -/* ------------------------------ HRPWM0_CSG2_DSV1 ------------------------------ */ -#define HRPWM0_CSG2_DSV1_DSV1_Pos \ - (0UL) /*!< HRPWM0_CSG2 DSV1: DSV1 (Bit 0) */ -#define HRPWM0_CSG2_DSV1_DSV1_Msk \ - (0x3ffUL) /*!< HRPWM0_CSG2 DSV1: DSV1 (Bitfield-Mask: 0x3ff) */ - -/* ------------------------------ HRPWM0_CSG2_DSV2 ------------------------------ */ -#define HRPWM0_CSG2_DSV2_DSV2_Pos \ - (0UL) /*!< HRPWM0_CSG2 DSV2: DSV2 (Bit 0) */ -#define HRPWM0_CSG2_DSV2_DSV2_Msk \ - (0x3ffUL) /*!< HRPWM0_CSG2 DSV2: DSV2 (Bitfield-Mask: 0x3ff) */ - -/* ------------------------------ HRPWM0_CSG2_SDSV1 ----------------------------- */ -#define HRPWM0_CSG2_SDSV1_SDSV1_Pos \ - (0UL) /*!< HRPWM0_CSG2 SDSV1: SDSV1 (Bit 0) */ -#define HRPWM0_CSG2_SDSV1_SDSV1_Msk \ - (0x3ffUL) /*!< HRPWM0_CSG2 SDSV1: SDSV1 (Bitfield-Mask: 0x3ff) */ - -/* ------------------------------- HRPWM0_CSG2_SPC ------------------------------ */ -#define HRPWM0_CSG2_SPC_SPSWV_Pos \ - (0UL) /*!< HRPWM0_CSG2 SPC: SPSWV (Bit 0) */ -#define HRPWM0_CSG2_SPC_SPSWV_Msk \ - (0x3fUL) /*!< HRPWM0_CSG2 SPC: SPSWV (Bitfield-Mask: 0x3f) */ - -/* ------------------------------- HRPWM0_CSG2_CC ------------------------------- */ -#define HRPWM0_CSG2_CC_IBS_Pos \ - (0UL) /*!< HRPWM0_CSG2 CC: IBS (Bit 0) */ -#define HRPWM0_CSG2_CC_IBS_Msk \ - (0xfUL) /*!< HRPWM0_CSG2 CC: IBS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG2_CC_IMCS_Pos \ - (8UL) /*!< HRPWM0_CSG2 CC: IMCS (Bit 8) */ -#define HRPWM0_CSG2_CC_IMCS_Msk \ - (0x100UL) /*!< HRPWM0_CSG2 CC: IMCS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_CC_IMCC_Pos \ - (9UL) /*!< HRPWM0_CSG2 CC: IMCC (Bit 9) */ -#define HRPWM0_CSG2_CC_IMCC_Msk \ - (0x600UL) /*!< HRPWM0_CSG2 CC: IMCC (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG2_CC_ESE_Pos \ - (11UL) /*!< HRPWM0_CSG2 CC: ESE (Bit 11) */ -#define HRPWM0_CSG2_CC_ESE_Msk \ - (0x800UL) /*!< HRPWM0_CSG2 CC: ESE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_CC_OIE_Pos \ - (12UL) /*!< HRPWM0_CSG2 CC: OIE (Bit 12) */ -#define HRPWM0_CSG2_CC_OIE_Msk \ - (0x1000UL) /*!< HRPWM0_CSG2 CC: OIE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_CC_OSE_Pos \ - (13UL) /*!< HRPWM0_CSG2 CC: OSE (Bit 13) */ -#define HRPWM0_CSG2_CC_OSE_Msk \ - (0x2000UL) /*!< HRPWM0_CSG2 CC: OSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_CC_BLMC_Pos \ - (14UL) /*!< HRPWM0_CSG2 CC: BLMC (Bit 14) */ -#define HRPWM0_CSG2_CC_BLMC_Msk \ - (0xc000UL) /*!< HRPWM0_CSG2 CC: BLMC (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG2_CC_EBE_Pos \ - (16UL) /*!< HRPWM0_CSG2 CC: EBE (Bit 16) */ -#define HRPWM0_CSG2_CC_EBE_Msk \ - (0x10000UL) /*!< HRPWM0_CSG2 CC: EBE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_CC_COFE_Pos \ - (17UL) /*!< HRPWM0_CSG2 CC: COFE (Bit 17) */ -#define HRPWM0_CSG2_CC_COFE_Msk \ - (0x20000UL) /*!< HRPWM0_CSG2 CC: COFE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_CC_COFM_Pos \ - (18UL) /*!< HRPWM0_CSG2 CC: COFM (Bit 18) */ -#define HRPWM0_CSG2_CC_COFM_Msk \ - (0x3c0000UL) /*!< HRPWM0_CSG2 CC: COFM (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG2_CC_COFC_Pos \ - (24UL) /*!< HRPWM0_CSG2 CC: COFC (Bit 24) */ -#define HRPWM0_CSG2_CC_COFC_Msk \ - (0x3000000UL) /*!< HRPWM0_CSG2 CC: COFC (Bitfield-Mask: 0x03) */ - -/* ------------------------------- HRPWM0_CSG2_PLC ------------------------------ */ -#define HRPWM0_CSG2_PLC_IPLS_Pos \ - (0UL) /*!< HRPWM0_CSG2 PLC: IPLS (Bit 0) */ -#define HRPWM0_CSG2_PLC_IPLS_Msk \ - (0xfUL) /*!< HRPWM0_CSG2 PLC: IPLS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG2_PLC_PLCL_Pos \ - (8UL) /*!< HRPWM0_CSG2 PLC: PLCL (Bit 8) */ -#define HRPWM0_CSG2_PLC_PLCL_Msk \ - (0x300UL) /*!< HRPWM0_CSG2 PLC: PLCL (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG2_PLC_PSL_Pos \ - (10UL) /*!< HRPWM0_CSG2 PLC: PSL (Bit 10) */ -#define HRPWM0_CSG2_PLC_PSL_Msk \ - (0x400UL) /*!< HRPWM0_CSG2 PLC: PSL (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_PLC_PLSW_Pos \ - (11UL) /*!< HRPWM0_CSG2 PLC: PLSW (Bit 11) */ -#define HRPWM0_CSG2_PLC_PLSW_Msk \ - (0x800UL) /*!< HRPWM0_CSG2 PLC: PLSW (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_PLC_PLEC_Pos \ - (12UL) /*!< HRPWM0_CSG2 PLC: PLEC (Bit 12) */ -#define HRPWM0_CSG2_PLC_PLEC_Msk \ - (0x3000UL) /*!< HRPWM0_CSG2 PLC: PLEC (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG2_PLC_PLXC_Pos \ - (14UL) /*!< HRPWM0_CSG2 PLC: PLXC (Bit 14) */ -#define HRPWM0_CSG2_PLC_PLXC_Msk \ - (0xc000UL) /*!< HRPWM0_CSG2 PLC: PLXC (Bitfield-Mask: 0x03) */ - -/* ------------------------------- HRPWM0_CSG2_BLV ------------------------------ */ -#define HRPWM0_CSG2_BLV_BLV_Pos \ - (0UL) /*!< HRPWM0_CSG2 BLV: BLV (Bit 0) */ -#define HRPWM0_CSG2_BLV_BLV_Msk \ - (0xffUL) /*!< HRPWM0_CSG2 BLV: BLV (Bitfield-Mask: 0xff) */ - -/* ------------------------------- HRPWM0_CSG2_SRE ------------------------------ */ -#define HRPWM0_CSG2_SRE_VLS1E_Pos \ - (0UL) /*!< HRPWM0_CSG2 SRE: VLS1E (Bit 0) */ -#define HRPWM0_CSG2_SRE_VLS1E_Msk \ - (0x1UL) /*!< HRPWM0_CSG2 SRE: VLS1E (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SRE_VLS2E_Pos \ - (1UL) /*!< HRPWM0_CSG2 SRE: VLS2E (Bit 1) */ -#define HRPWM0_CSG2_SRE_VLS2E_Msk \ - (0x2UL) /*!< HRPWM0_CSG2 SRE: VLS2E (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SRE_TRGSE_Pos \ - (2UL) /*!< HRPWM0_CSG2 SRE: TRGSE (Bit 2) */ -#define HRPWM0_CSG2_SRE_TRGSE_Msk \ - (0x4UL) /*!< HRPWM0_CSG2 SRE: TRGSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SRE_STRSE_Pos \ - (3UL) /*!< HRPWM0_CSG2 SRE: STRSE (Bit 3) */ -#define HRPWM0_CSG2_SRE_STRSE_Msk \ - (0x8UL) /*!< HRPWM0_CSG2 SRE: STRSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SRE_STPSE_Pos \ - (4UL) /*!< HRPWM0_CSG2 SRE: STPSE (Bit 4) */ -#define HRPWM0_CSG2_SRE_STPSE_Msk \ - (0x10UL) /*!< HRPWM0_CSG2 SRE: STPSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SRE_STDE_Pos \ - (5UL) /*!< HRPWM0_CSG2 SRE: STDE (Bit 5) */ -#define HRPWM0_CSG2_SRE_STDE_Msk \ - (0x20UL) /*!< HRPWM0_CSG2 SRE: STDE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SRE_CRSE_Pos \ - (6UL) /*!< HRPWM0_CSG2 SRE: CRSE (Bit 6) */ -#define HRPWM0_CSG2_SRE_CRSE_Msk \ - (0x40UL) /*!< HRPWM0_CSG2 SRE: CRSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SRE_CFSE_Pos \ - (7UL) /*!< HRPWM0_CSG2 SRE: CFSE (Bit 7) */ -#define HRPWM0_CSG2_SRE_CFSE_Msk \ - (0x80UL) /*!< HRPWM0_CSG2 SRE: CFSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SRE_CSEE_Pos \ - (8UL) /*!< HRPWM0_CSG2 SRE: CSEE (Bit 8) */ -#define HRPWM0_CSG2_SRE_CSEE_Msk \ - (0x100UL) /*!< HRPWM0_CSG2 SRE: CSEE (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_CSG2_SRS ------------------------------ */ -#define HRPWM0_CSG2_SRS_VLS1S_Pos \ - (0UL) /*!< HRPWM0_CSG2 SRS: VLS1S (Bit 0) */ -#define HRPWM0_CSG2_SRS_VLS1S_Msk \ - (0x3UL) /*!< HRPWM0_CSG2 SRS: VLS1S (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG2_SRS_VLS2S_Pos \ - (2UL) /*!< HRPWM0_CSG2 SRS: VLS2S (Bit 2) */ -#define HRPWM0_CSG2_SRS_VLS2S_Msk \ - (0xcUL) /*!< HRPWM0_CSG2 SRS: VLS2S (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG2_SRS_TRLS_Pos \ - (4UL) /*!< HRPWM0_CSG2 SRS: TRLS (Bit 4) */ -#define HRPWM0_CSG2_SRS_TRLS_Msk \ - (0x30UL) /*!< HRPWM0_CSG2 SRS: TRLS (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG2_SRS_SSLS_Pos \ - (6UL) /*!< HRPWM0_CSG2 SRS: SSLS (Bit 6) */ -#define HRPWM0_CSG2_SRS_SSLS_Msk \ - (0xc0UL) /*!< HRPWM0_CSG2 SRS: SSLS (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG2_SRS_STLS_Pos \ - (8UL) /*!< HRPWM0_CSG2 SRS: STLS (Bit 8) */ -#define HRPWM0_CSG2_SRS_STLS_Msk \ - (0x300UL) /*!< HRPWM0_CSG2 SRS: STLS (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG2_SRS_CRFLS_Pos \ - (10UL) /*!< HRPWM0_CSG2 SRS: CRFLS (Bit 10) */ -#define HRPWM0_CSG2_SRS_CRFLS_Msk \ - (0xc00UL) /*!< HRPWM0_CSG2 SRS: CRFLS (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG2_SRS_CSLS_Pos \ - (12UL) /*!< HRPWM0_CSG2 SRS: CSLS (Bit 12) */ -#define HRPWM0_CSG2_SRS_CSLS_Msk \ - (0x3000UL) /*!< HRPWM0_CSG2 SRS: CSLS (Bitfield-Mask: 0x03) */ - -/* ------------------------------- HRPWM0_CSG2_SWS ------------------------------ */ -#define HRPWM0_CSG2_SWS_SVLS1_Pos \ - (0UL) /*!< HRPWM0_CSG2 SWS: SVLS1 (Bit 0) */ -#define HRPWM0_CSG2_SWS_SVLS1_Msk \ - (0x1UL) /*!< HRPWM0_CSG2 SWS: SVLS1 (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SWS_SVLS2_Pos \ - (1UL) /*!< HRPWM0_CSG2 SWS: SVLS2 (Bit 1) */ -#define HRPWM0_CSG2_SWS_SVLS2_Msk \ - (0x2UL) /*!< HRPWM0_CSG2 SWS: SVLS2 (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SWS_STRGS_Pos \ - (2UL) /*!< HRPWM0_CSG2 SWS: STRGS (Bit 2) */ -#define HRPWM0_CSG2_SWS_STRGS_Msk \ - (0x4UL) /*!< HRPWM0_CSG2 SWS: STRGS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SWS_SSTRS_Pos \ - (3UL) /*!< HRPWM0_CSG2 SWS: SSTRS (Bit 3) */ -#define HRPWM0_CSG2_SWS_SSTRS_Msk \ - (0x8UL) /*!< HRPWM0_CSG2 SWS: SSTRS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SWS_SSTPS_Pos \ - (4UL) /*!< HRPWM0_CSG2 SWS: SSTPS (Bit 4) */ -#define HRPWM0_CSG2_SWS_SSTPS_Msk \ - (0x10UL) /*!< HRPWM0_CSG2 SWS: SSTPS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SWS_SSTD_Pos \ - (5UL) /*!< HRPWM0_CSG2 SWS: SSTD (Bit 5) */ -#define HRPWM0_CSG2_SWS_SSTD_Msk \ - (0x20UL) /*!< HRPWM0_CSG2 SWS: SSTD (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SWS_SCRS_Pos \ - (6UL) /*!< HRPWM0_CSG2 SWS: SCRS (Bit 6) */ -#define HRPWM0_CSG2_SWS_SCRS_Msk \ - (0x40UL) /*!< HRPWM0_CSG2 SWS: SCRS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SWS_SCFS_Pos \ - (7UL) /*!< HRPWM0_CSG2 SWS: SCFS (Bit 7) */ -#define HRPWM0_CSG2_SWS_SCFS_Msk \ - (0x80UL) /*!< HRPWM0_CSG2 SWS: SCFS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SWS_SCSS_Pos \ - (8UL) /*!< HRPWM0_CSG2 SWS: SCSS (Bit 8) */ -#define HRPWM0_CSG2_SWS_SCSS_Msk \ - (0x100UL) /*!< HRPWM0_CSG2 SWS: SCSS (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_CSG2_SWC ------------------------------ */ -#define HRPWM0_CSG2_SWC_CVLS1_Pos \ - (0UL) /*!< HRPWM0_CSG2 SWC: CVLS1 (Bit 0) */ -#define HRPWM0_CSG2_SWC_CVLS1_Msk \ - (0x1UL) /*!< HRPWM0_CSG2 SWC: CVLS1 (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SWC_CVLS2_Pos \ - (1UL) /*!< HRPWM0_CSG2 SWC: CVLS2 (Bit 1) */ -#define HRPWM0_CSG2_SWC_CVLS2_Msk \ - (0x2UL) /*!< HRPWM0_CSG2 SWC: CVLS2 (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SWC_CTRGS_Pos \ - (2UL) /*!< HRPWM0_CSG2 SWC: CTRGS (Bit 2) */ -#define HRPWM0_CSG2_SWC_CTRGS_Msk \ - (0x4UL) /*!< HRPWM0_CSG2 SWC: CTRGS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SWC_CSTRS_Pos \ - (3UL) /*!< HRPWM0_CSG2 SWC: CSTRS (Bit 3) */ -#define HRPWM0_CSG2_SWC_CSTRS_Msk \ - (0x8UL) /*!< HRPWM0_CSG2 SWC: CSTRS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SWC_CSTPS_Pos \ - (4UL) /*!< HRPWM0_CSG2 SWC: CSTPS (Bit 4) */ -#define HRPWM0_CSG2_SWC_CSTPS_Msk \ - (0x10UL) /*!< HRPWM0_CSG2 SWC: CSTPS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SWC_CSTD_Pos \ - (5UL) /*!< HRPWM0_CSG2 SWC: CSTD (Bit 5) */ -#define HRPWM0_CSG2_SWC_CSTD_Msk \ - (0x20UL) /*!< HRPWM0_CSG2 SWC: CSTD (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SWC_CCRS_Pos \ - (6UL) /*!< HRPWM0_CSG2 SWC: CCRS (Bit 6) */ -#define HRPWM0_CSG2_SWC_CCRS_Msk \ - (0x40UL) /*!< HRPWM0_CSG2 SWC: CCRS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SWC_CCFS_Pos \ - (7UL) /*!< HRPWM0_CSG2 SWC: CCFS (Bit 7) */ -#define HRPWM0_CSG2_SWC_CCFS_Msk \ - (0x80UL) /*!< HRPWM0_CSG2 SWC: CCFS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SWC_CCSS_Pos \ - (8UL) /*!< HRPWM0_CSG2 SWC: CCSS (Bit 8) */ -#define HRPWM0_CSG2_SWC_CCSS_Msk \ - (0x100UL) /*!< HRPWM0_CSG2 SWC: CCSS (Bitfield-Mask: 0x01) */ - -/* ------------------------------ HRPWM0_CSG2_ISTAT ----------------------------- */ -#define HRPWM0_CSG2_ISTAT_VLS1S_Pos \ - (0UL) /*!< HRPWM0_CSG2 ISTAT: VLS1S (Bit 0) */ -#define HRPWM0_CSG2_ISTAT_VLS1S_Msk \ - (0x1UL) /*!< HRPWM0_CSG2 ISTAT: VLS1S (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_ISTAT_VLS2S_Pos \ - (1UL) /*!< HRPWM0_CSG2 ISTAT: VLS2S (Bit 1) */ -#define HRPWM0_CSG2_ISTAT_VLS2S_Msk \ - (0x2UL) /*!< HRPWM0_CSG2 ISTAT: VLS2S (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_ISTAT_TRGSS_Pos \ - (2UL) /*!< HRPWM0_CSG2 ISTAT: TRGSS (Bit 2) */ -#define HRPWM0_CSG2_ISTAT_TRGSS_Msk \ - (0x4UL) /*!< HRPWM0_CSG2 ISTAT: TRGSS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_ISTAT_STRSS_Pos \ - (3UL) /*!< HRPWM0_CSG2 ISTAT: STRSS (Bit 3) */ -#define HRPWM0_CSG2_ISTAT_STRSS_Msk \ - (0x8UL) /*!< HRPWM0_CSG2 ISTAT: STRSS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_ISTAT_STPSS_Pos \ - (4UL) /*!< HRPWM0_CSG2 ISTAT: STPSS (Bit 4) */ -#define HRPWM0_CSG2_ISTAT_STPSS_Msk \ - (0x10UL) /*!< HRPWM0_CSG2 ISTAT: STPSS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_ISTAT_STDS_Pos \ - (5UL) /*!< HRPWM0_CSG2 ISTAT: STDS (Bit 5) */ -#define HRPWM0_CSG2_ISTAT_STDS_Msk \ - (0x20UL) /*!< HRPWM0_CSG2 ISTAT: STDS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_ISTAT_CRSS_Pos \ - (6UL) /*!< HRPWM0_CSG2 ISTAT: CRSS (Bit 6) */ -#define HRPWM0_CSG2_ISTAT_CRSS_Msk \ - (0x40UL) /*!< HRPWM0_CSG2 ISTAT: CRSS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_ISTAT_CFSS_Pos \ - (7UL) /*!< HRPWM0_CSG2 ISTAT: CFSS (Bit 7) */ -#define HRPWM0_CSG2_ISTAT_CFSS_Msk \ - (0x80UL) /*!< HRPWM0_CSG2 ISTAT: CFSS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_ISTAT_CSES_Pos \ - (8UL) /*!< HRPWM0_CSG2 ISTAT: CSES (Bit 8) */ -#define HRPWM0_CSG2_ISTAT_CSES_Msk \ - (0x100UL) /*!< HRPWM0_CSG2 ISTAT: CSES (Bitfield-Mask: 0x01) */ - -/* ================================================================================ */ -/* ================ Group 'HRPWM0_HRC' Position & Mask ================ */ -/* ================================================================================ */ - -/* -------------------------------- HRPWM0_HRC_GC ------------------------------- */ -#define HRPWM0_HRC_GC_HRM0_Pos \ - (0UL) /*!< HRPWM0_HRC GC: HRM0 (Bit 0) */ -#define HRPWM0_HRC_GC_HRM0_Msk \ - (0x3UL) /*!< HRPWM0_HRC GC: HRM0 (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC_GC_HRM1_Pos \ - (2UL) /*!< HRPWM0_HRC GC: HRM1 (Bit 2) */ -#define HRPWM0_HRC_GC_HRM1_Msk \ - (0xcUL) /*!< HRPWM0_HRC GC: HRM1 (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC_GC_DTE_Pos \ - (8UL) /*!< HRPWM0_HRC GC: DTE (Bit 8) */ -#define HRPWM0_HRC_GC_DTE_Msk \ - (0x100UL) /*!< HRPWM0_HRC GC: DTE (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC_GC_TR0E_Pos \ - (9UL) /*!< HRPWM0_HRC GC: TR0E (Bit 9) */ -#define HRPWM0_HRC_GC_TR0E_Msk \ - (0x200UL) /*!< HRPWM0_HRC GC: TR0E (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC_GC_TR1E_Pos \ - (10UL) /*!< HRPWM0_HRC GC: TR1E (Bit 10) */ -#define HRPWM0_HRC_GC_TR1E_Msk \ - (0x400UL) /*!< HRPWM0_HRC GC: TR1E (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC_GC_STC_Pos \ - (11UL) /*!< HRPWM0_HRC GC: STC (Bit 11) */ -#define HRPWM0_HRC_GC_STC_Msk \ - (0x800UL) /*!< HRPWM0_HRC GC: STC (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC_GC_DSTC_Pos \ - (12UL) /*!< HRPWM0_HRC GC: DSTC (Bit 12) */ -#define HRPWM0_HRC_GC_DSTC_Msk \ - (0x1000UL) /*!< HRPWM0_HRC GC: DSTC (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC_GC_OCS0_Pos \ - (13UL) /*!< HRPWM0_HRC GC: OCS0 (Bit 13) */ -#define HRPWM0_HRC_GC_OCS0_Msk \ - (0x2000UL) /*!< HRPWM0_HRC GC: OCS0 (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC_GC_OCS1_Pos \ - (14UL) /*!< HRPWM0_HRC GC: OCS1 (Bit 14) */ -#define HRPWM0_HRC_GC_OCS1_Msk \ - (0x4000UL) /*!< HRPWM0_HRC GC: OCS1 (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC_GC_DTUS_Pos \ - (16UL) /*!< HRPWM0_HRC GC: DTUS (Bit 16) */ -#define HRPWM0_HRC_GC_DTUS_Msk \ - (0x10000UL) /*!< HRPWM0_HRC GC: DTUS (Bitfield-Mask: 0x01) */ - -/* -------------------------------- HRPWM0_HRC_PL ------------------------------- */ -#define HRPWM0_HRC_PL_PSL0_Pos \ - (0UL) /*!< HRPWM0_HRC PL: PSL0 (Bit 0) */ -#define HRPWM0_HRC_PL_PSL0_Msk \ - (0x1UL) /*!< HRPWM0_HRC PL: PSL0 (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC_PL_PSL1_Pos \ - (1UL) /*!< HRPWM0_HRC PL: PSL1 (Bit 1) */ -#define HRPWM0_HRC_PL_PSL1_Msk \ - (0x2UL) /*!< HRPWM0_HRC PL: PSL1 (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_HRC_GSEL ------------------------------ */ -#define HRPWM0_HRC_GSEL_C0SS_Pos \ - (0UL) /*!< HRPWM0_HRC GSEL: C0SS (Bit 0) */ -#define HRPWM0_HRC_GSEL_C0SS_Msk \ - (0x7UL) /*!< HRPWM0_HRC GSEL: C0SS (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC_GSEL_C0CS_Pos \ - (3UL) /*!< HRPWM0_HRC GSEL: C0CS (Bit 3) */ -#define HRPWM0_HRC_GSEL_C0CS_Msk \ - (0x38UL) /*!< HRPWM0_HRC GSEL: C0CS (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC_GSEL_S0M_Pos \ - (6UL) /*!< HRPWM0_HRC GSEL: S0M (Bit 6) */ -#define HRPWM0_HRC_GSEL_S0M_Msk \ - (0xc0UL) /*!< HRPWM0_HRC GSEL: S0M (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC_GSEL_C0M_Pos \ - (8UL) /*!< HRPWM0_HRC GSEL: C0M (Bit 8) */ -#define HRPWM0_HRC_GSEL_C0M_Msk \ - (0x300UL) /*!< HRPWM0_HRC GSEL: C0M (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC_GSEL_S0ES_Pos \ - (10UL) /*!< HRPWM0_HRC GSEL: S0ES (Bit 10) */ -#define HRPWM0_HRC_GSEL_S0ES_Msk \ - (0xc00UL) /*!< HRPWM0_HRC GSEL: S0ES (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC_GSEL_C0ES_Pos \ - (12UL) /*!< HRPWM0_HRC GSEL: C0ES (Bit 12) */ -#define HRPWM0_HRC_GSEL_C0ES_Msk \ - (0x3000UL) /*!< HRPWM0_HRC GSEL: C0ES (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC_GSEL_C1SS_Pos \ - (16UL) /*!< HRPWM0_HRC GSEL: C1SS (Bit 16) */ -#define HRPWM0_HRC_GSEL_C1SS_Msk \ - (0x70000UL) /*!< HRPWM0_HRC GSEL: C1SS (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC_GSEL_C1CS_Pos \ - (19UL) /*!< HRPWM0_HRC GSEL: C1CS (Bit 19) */ -#define HRPWM0_HRC_GSEL_C1CS_Msk \ - (0x380000UL) /*!< HRPWM0_HRC GSEL: C1CS (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC_GSEL_S1M_Pos \ - (22UL) /*!< HRPWM0_HRC GSEL: S1M (Bit 22) */ -#define HRPWM0_HRC_GSEL_S1M_Msk \ - (0xc00000UL) /*!< HRPWM0_HRC GSEL: S1M (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC_GSEL_C1M_Pos \ - (24UL) /*!< HRPWM0_HRC GSEL: C1M (Bit 24) */ -#define HRPWM0_HRC_GSEL_C1M_Msk \ - (0x3000000UL) /*!< HRPWM0_HRC GSEL: C1M (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC_GSEL_S1ES_Pos \ - (26UL) /*!< HRPWM0_HRC GSEL: S1ES (Bit 26) */ -#define HRPWM0_HRC_GSEL_S1ES_Msk \ - (0xc000000UL) /*!< HRPWM0_HRC GSEL: S1ES (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC_GSEL_C1ES_Pos \ - (28UL) /*!< HRPWM0_HRC GSEL: C1ES (Bit 28) */ -#define HRPWM0_HRC_GSEL_C1ES_Msk \ - (0x30000000UL) /*!< HRPWM0_HRC GSEL: C1ES (Bitfield-Mask: 0x03) */ - -/* ------------------------------- HRPWM0_HRC_TSEL ------------------------------ */ -#define HRPWM0_HRC_TSEL_TSEL0_Pos \ - (0UL) /*!< HRPWM0_HRC TSEL: TSEL0 (Bit 0) */ -#define HRPWM0_HRC_TSEL_TSEL0_Msk \ - (0x7UL) /*!< HRPWM0_HRC TSEL: TSEL0 (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC_TSEL_TSEL1_Pos \ - (3UL) /*!< HRPWM0_HRC TSEL: TSEL1 (Bit 3) */ -#define HRPWM0_HRC_TSEL_TSEL1_Msk \ - (0x38UL) /*!< HRPWM0_HRC TSEL: TSEL1 (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC_TSEL_TS0E_Pos \ - (16UL) /*!< HRPWM0_HRC TSEL: TS0E (Bit 16) */ -#define HRPWM0_HRC_TSEL_TS0E_Msk \ - (0x10000UL) /*!< HRPWM0_HRC TSEL: TS0E (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC_TSEL_TS1E_Pos \ - (17UL) /*!< HRPWM0_HRC TSEL: TS1E (Bit 17) */ -#define HRPWM0_HRC_TSEL_TS1E_Msk \ - (0x20000UL) /*!< HRPWM0_HRC TSEL: TS1E (Bitfield-Mask: 0x01) */ - -/* -------------------------------- HRPWM0_HRC_SC ------------------------------- */ -#define HRPWM0_HRC_SC_ST_Pos \ - (0UL) /*!< HRPWM0_HRC SC: ST (Bit 0) */ -#define HRPWM0_HRC_SC_ST_Msk \ - (0x1UL) /*!< HRPWM0_HRC SC: ST (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_HRC_DCR ------------------------------- */ -#define HRPWM0_HRC_DCR_DTRV_Pos \ - (0UL) /*!< HRPWM0_HRC DCR: DTRV (Bit 0) */ -#define HRPWM0_HRC_DCR_DTRV_Msk \ - (0xffffUL) /*!< HRPWM0_HRC DCR: DTRV (Bitfield-Mask: 0xffff) */ - -/* ------------------------------- HRPWM0_HRC_DCF ------------------------------- */ -#define HRPWM0_HRC_DCF_DTFV_Pos \ - (0UL) /*!< HRPWM0_HRC DCF: DTFV (Bit 0) */ -#define HRPWM0_HRC_DCF_DTFV_Msk \ - (0xffffUL) /*!< HRPWM0_HRC DCF: DTFV (Bitfield-Mask: 0xffff) */ - -/* ------------------------------- HRPWM0_HRC_CR1 ------------------------------- */ -#define HRPWM0_HRC_CR1_CR1_Pos \ - (0UL) /*!< HRPWM0_HRC CR1: CR1 (Bit 0) */ -#define HRPWM0_HRC_CR1_CR1_Msk \ - (0xffUL) /*!< HRPWM0_HRC CR1: CR1 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- HRPWM0_HRC_CR2 ------------------------------- */ -#define HRPWM0_HRC_CR2_CR2_Pos \ - (0UL) /*!< HRPWM0_HRC CR2: CR2 (Bit 0) */ -#define HRPWM0_HRC_CR2_CR2_Msk \ - (0xffUL) /*!< HRPWM0_HRC CR2: CR2 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- HRPWM0_HRC_SSC ------------------------------- */ -#define HRPWM0_HRC_SSC_SST_Pos \ - (0UL) /*!< HRPWM0_HRC SSC: SST (Bit 0) */ -#define HRPWM0_HRC_SSC_SST_Msk \ - (0x1UL) /*!< HRPWM0_HRC SSC: SST (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_HRC_SDCR ------------------------------ */ -#define HRPWM0_HRC_SDCR_SDTRV_Pos \ - (0UL) /*!< HRPWM0_HRC SDCR: SDTRV (Bit 0) */ -#define HRPWM0_HRC_SDCR_SDTRV_Msk \ - (0xffffUL) /*!< HRPWM0_HRC SDCR: SDTRV (Bitfield-Mask: 0xffff) */ - -/* ------------------------------- HRPWM0_HRC_SDCF ------------------------------ */ -#define HRPWM0_HRC_SDCF_SDTFV_Pos \ - (0UL) /*!< HRPWM0_HRC SDCF: SDTFV (Bit 0) */ -#define HRPWM0_HRC_SDCF_SDTFV_Msk \ - (0xffffUL) /*!< HRPWM0_HRC SDCF: SDTFV (Bitfield-Mask: 0xffff) */ - -/* ------------------------------- HRPWM0_HRC_SCR1 ------------------------------ */ -#define HRPWM0_HRC_SCR1_SCR1_Pos \ - (0UL) /*!< HRPWM0_HRC SCR1: SCR1 (Bit 0) */ -#define HRPWM0_HRC_SCR1_SCR1_Msk \ - (0xffUL) /*!< HRPWM0_HRC SCR1: SCR1 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- HRPWM0_HRC_SCR2 ------------------------------ */ -#define HRPWM0_HRC_SCR2_SCR2_Pos \ - (0UL) /*!< HRPWM0_HRC SCR2: SCR2 (Bit 0) */ -#define HRPWM0_HRC_SCR2_SCR2_Msk \ - (0xffUL) /*!< HRPWM0_HRC SCR2: SCR2 (Bitfield-Mask: 0xff) */ - -/* ================================================================================ */ -/* ================ struct 'HRPWM0_HRC0' Position & Mask ================ */ -/* ================================================================================ */ - -/* ------------------------------- HRPWM0_HRC0_GC ------------------------------- */ -#define HRPWM0_HRC0_GC_HRM0_Pos \ - (0UL) /*!< HRPWM0_HRC0 GC: HRM0 (Bit 0) */ -#define HRPWM0_HRC0_GC_HRM0_Msk \ - (0x3UL) /*!< HRPWM0_HRC0 GC: HRM0 (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC0_GC_HRM1_Pos \ - (2UL) /*!< HRPWM0_HRC0 GC: HRM1 (Bit 2) */ -#define HRPWM0_HRC0_GC_HRM1_Msk \ - (0xcUL) /*!< HRPWM0_HRC0 GC: HRM1 (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC0_GC_DTE_Pos \ - (8UL) /*!< HRPWM0_HRC0 GC: DTE (Bit 8) */ -#define HRPWM0_HRC0_GC_DTE_Msk \ - (0x100UL) /*!< HRPWM0_HRC0 GC: DTE (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC0_GC_TR0E_Pos \ - (9UL) /*!< HRPWM0_HRC0 GC: TR0E (Bit 9) */ -#define HRPWM0_HRC0_GC_TR0E_Msk \ - (0x200UL) /*!< HRPWM0_HRC0 GC: TR0E (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC0_GC_TR1E_Pos \ - (10UL) /*!< HRPWM0_HRC0 GC: TR1E (Bit 10) */ -#define HRPWM0_HRC0_GC_TR1E_Msk \ - (0x400UL) /*!< HRPWM0_HRC0 GC: TR1E (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC0_GC_STC_Pos \ - (11UL) /*!< HRPWM0_HRC0 GC: STC (Bit 11) */ -#define HRPWM0_HRC0_GC_STC_Msk \ - (0x800UL) /*!< HRPWM0_HRC0 GC: STC (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC0_GC_DSTC_Pos \ - (12UL) /*!< HRPWM0_HRC0 GC: DSTC (Bit 12) */ -#define HRPWM0_HRC0_GC_DSTC_Msk \ - (0x1000UL) /*!< HRPWM0_HRC0 GC: DSTC (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC0_GC_OCS0_Pos \ - (13UL) /*!< HRPWM0_HRC0 GC: OCS0 (Bit 13) */ -#define HRPWM0_HRC0_GC_OCS0_Msk \ - (0x2000UL) /*!< HRPWM0_HRC0 GC: OCS0 (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC0_GC_OCS1_Pos \ - (14UL) /*!< HRPWM0_HRC0 GC: OCS1 (Bit 14) */ -#define HRPWM0_HRC0_GC_OCS1_Msk \ - (0x4000UL) /*!< HRPWM0_HRC0 GC: OCS1 (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC0_GC_DTUS_Pos \ - (16UL) /*!< HRPWM0_HRC0 GC: DTUS (Bit 16) */ -#define HRPWM0_HRC0_GC_DTUS_Msk \ - (0x10000UL) /*!< HRPWM0_HRC0 GC: DTUS (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_HRC0_PL ------------------------------- */ -#define HRPWM0_HRC0_PL_PSL0_Pos \ - (0UL) /*!< HRPWM0_HRC0 PL: PSL0 (Bit 0) */ -#define HRPWM0_HRC0_PL_PSL0_Msk \ - (0x1UL) /*!< HRPWM0_HRC0 PL: PSL0 (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC0_PL_PSL1_Pos \ - (1UL) /*!< HRPWM0_HRC0 PL: PSL1 (Bit 1) */ -#define HRPWM0_HRC0_PL_PSL1_Msk \ - (0x2UL) /*!< HRPWM0_HRC0 PL: PSL1 (Bitfield-Mask: 0x01) */ - -/* ------------------------------ HRPWM0_HRC0_GSEL ------------------------------ */ -#define HRPWM0_HRC0_GSEL_C0SS_Pos \ - (0UL) /*!< HRPWM0_HRC0 GSEL: C0SS (Bit 0) */ -#define HRPWM0_HRC0_GSEL_C0SS_Msk \ - (0x7UL) /*!< HRPWM0_HRC0 GSEL: C0SS (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC0_GSEL_C0CS_Pos \ - (3UL) /*!< HRPWM0_HRC0 GSEL: C0CS (Bit 3) */ -#define HRPWM0_HRC0_GSEL_C0CS_Msk \ - (0x38UL) /*!< HRPWM0_HRC0 GSEL: C0CS (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC0_GSEL_S0M_Pos \ - (6UL) /*!< HRPWM0_HRC0 GSEL: S0M (Bit 6) */ -#define HRPWM0_HRC0_GSEL_S0M_Msk \ - (0xc0UL) /*!< HRPWM0_HRC0 GSEL: S0M (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC0_GSEL_C0M_Pos \ - (8UL) /*!< HRPWM0_HRC0 GSEL: C0M (Bit 8) */ -#define HRPWM0_HRC0_GSEL_C0M_Msk \ - (0x300UL) /*!< HRPWM0_HRC0 GSEL: C0M (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC0_GSEL_S0ES_Pos \ - (10UL) /*!< HRPWM0_HRC0 GSEL: S0ES (Bit 10) */ -#define HRPWM0_HRC0_GSEL_S0ES_Msk \ - (0xc00UL) /*!< HRPWM0_HRC0 GSEL: S0ES (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC0_GSEL_C0ES_Pos \ - (12UL) /*!< HRPWM0_HRC0 GSEL: C0ES (Bit 12) */ -#define HRPWM0_HRC0_GSEL_C0ES_Msk \ - (0x3000UL) /*!< HRPWM0_HRC0 GSEL: C0ES (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC0_GSEL_C1SS_Pos \ - (16UL) /*!< HRPWM0_HRC0 GSEL: C1SS (Bit 16) */ -#define HRPWM0_HRC0_GSEL_C1SS_Msk \ - (0x70000UL) /*!< HRPWM0_HRC0 GSEL: C1SS (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC0_GSEL_C1CS_Pos \ - (19UL) /*!< HRPWM0_HRC0 GSEL: C1CS (Bit 19) */ -#define HRPWM0_HRC0_GSEL_C1CS_Msk \ - (0x380000UL) /*!< HRPWM0_HRC0 GSEL: C1CS (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC0_GSEL_S1M_Pos \ - (22UL) /*!< HRPWM0_HRC0 GSEL: S1M (Bit 22) */ -#define HRPWM0_HRC0_GSEL_S1M_Msk \ - (0xc00000UL) /*!< HRPWM0_HRC0 GSEL: S1M (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC0_GSEL_C1M_Pos \ - (24UL) /*!< HRPWM0_HRC0 GSEL: C1M (Bit 24) */ -#define HRPWM0_HRC0_GSEL_C1M_Msk \ - (0x3000000UL) /*!< HRPWM0_HRC0 GSEL: C1M (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC0_GSEL_S1ES_Pos \ - (26UL) /*!< HRPWM0_HRC0 GSEL: S1ES (Bit 26) */ -#define HRPWM0_HRC0_GSEL_S1ES_Msk \ - (0xc000000UL) /*!< HRPWM0_HRC0 GSEL: S1ES (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC0_GSEL_C1ES_Pos \ - (28UL) /*!< HRPWM0_HRC0 GSEL: C1ES (Bit 28) */ -#define HRPWM0_HRC0_GSEL_C1ES_Msk \ - (0x30000000UL) /*!< HRPWM0_HRC0 GSEL: C1ES (Bitfield-Mask: 0x03) */ - -/* ------------------------------ HRPWM0_HRC0_TSEL ------------------------------ */ -#define HRPWM0_HRC0_TSEL_TSEL0_Pos \ - (0UL) /*!< HRPWM0_HRC0 TSEL: TSEL0 (Bit 0) */ -#define HRPWM0_HRC0_TSEL_TSEL0_Msk \ - (0x7UL) /*!< HRPWM0_HRC0 TSEL: TSEL0 (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC0_TSEL_TSEL1_Pos \ - (3UL) /*!< HRPWM0_HRC0 TSEL: TSEL1 (Bit 3) */ -#define HRPWM0_HRC0_TSEL_TSEL1_Msk \ - (0x38UL) /*!< HRPWM0_HRC0 TSEL: TSEL1 (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC0_TSEL_TS0E_Pos \ - (16UL) /*!< HRPWM0_HRC0 TSEL: TS0E (Bit 16) */ -#define HRPWM0_HRC0_TSEL_TS0E_Msk \ - (0x10000UL) /*!< HRPWM0_HRC0 TSEL: TS0E (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC0_TSEL_TS1E_Pos \ - (17UL) /*!< HRPWM0_HRC0 TSEL: TS1E (Bit 17) */ -#define HRPWM0_HRC0_TSEL_TS1E_Msk \ - (0x20000UL) /*!< HRPWM0_HRC0 TSEL: TS1E (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_HRC0_SC ------------------------------- */ -#define HRPWM0_HRC0_SC_ST_Pos \ - (0UL) /*!< HRPWM0_HRC0 SC: ST (Bit 0) */ -#define HRPWM0_HRC0_SC_ST_Msk \ - (0x1UL) /*!< HRPWM0_HRC0 SC: ST (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_HRC0_DCR ------------------------------ */ -#define HRPWM0_HRC0_DCR_DTRV_Pos \ - (0UL) /*!< HRPWM0_HRC0 DCR: DTRV (Bit 0) */ -#define HRPWM0_HRC0_DCR_DTRV_Msk \ - (0xffffUL) /*!< HRPWM0_HRC0 DCR: DTRV (Bitfield-Mask: 0xffff) */ - -/* ------------------------------- HRPWM0_HRC0_DCF ------------------------------ */ -#define HRPWM0_HRC0_DCF_DTFV_Pos \ - (0UL) /*!< HRPWM0_HRC0 DCF: DTFV (Bit 0) */ -#define HRPWM0_HRC0_DCF_DTFV_Msk \ - (0xffffUL) /*!< HRPWM0_HRC0 DCF: DTFV (Bitfield-Mask: 0xffff) */ - -/* ------------------------------- HRPWM0_HRC0_CR1 ------------------------------ */ -#define HRPWM0_HRC0_CR1_CR1_Pos \ - (0UL) /*!< HRPWM0_HRC0 CR1: CR1 (Bit 0) */ -#define HRPWM0_HRC0_CR1_CR1_Msk \ - (0xffUL) /*!< HRPWM0_HRC0 CR1: CR1 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- HRPWM0_HRC0_CR2 ------------------------------ */ -#define HRPWM0_HRC0_CR2_CR2_Pos \ - (0UL) /*!< HRPWM0_HRC0 CR2: CR2 (Bit 0) */ -#define HRPWM0_HRC0_CR2_CR2_Msk \ - (0xffUL) /*!< HRPWM0_HRC0 CR2: CR2 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- HRPWM0_HRC0_SSC ------------------------------ */ -#define HRPWM0_HRC0_SSC_SST_Pos \ - (0UL) /*!< HRPWM0_HRC0 SSC: SST (Bit 0) */ -#define HRPWM0_HRC0_SSC_SST_Msk \ - (0x1UL) /*!< HRPWM0_HRC0 SSC: SST (Bitfield-Mask: 0x01) */ - -/* ------------------------------ HRPWM0_HRC0_SDCR ------------------------------ */ -#define HRPWM0_HRC0_SDCR_SDTRV_Pos \ - (0UL) /*!< HRPWM0_HRC0 SDCR: SDTRV (Bit 0) */ -#define HRPWM0_HRC0_SDCR_SDTRV_Msk \ - (0xffffUL) /*!< HRPWM0_HRC0 SDCR: SDTRV (Bitfield-Mask: 0xffff) */ - -/* ------------------------------ HRPWM0_HRC0_SDCF ------------------------------ */ -#define HRPWM0_HRC0_SDCF_SDTFV_Pos \ - (0UL) /*!< HRPWM0_HRC0 SDCF: SDTFV (Bit 0) */ -#define HRPWM0_HRC0_SDCF_SDTFV_Msk \ - (0xffffUL) /*!< HRPWM0_HRC0 SDCF: SDTFV (Bitfield-Mask: 0xffff) */ - -/* ------------------------------ HRPWM0_HRC0_SCR1 ------------------------------ */ -#define HRPWM0_HRC0_SCR1_SCR1_Pos \ - (0UL) /*!< HRPWM0_HRC0 SCR1: SCR1 (Bit 0) */ -#define HRPWM0_HRC0_SCR1_SCR1_Msk \ - (0xffUL) /*!< HRPWM0_HRC0 SCR1: SCR1 (Bitfield-Mask: 0xff) */ - -/* ------------------------------ HRPWM0_HRC0_SCR2 ------------------------------ */ -#define HRPWM0_HRC0_SCR2_SCR2_Pos \ - (0UL) /*!< HRPWM0_HRC0 SCR2: SCR2 (Bit 0) */ -#define HRPWM0_HRC0_SCR2_SCR2_Msk \ - (0xffUL) /*!< HRPWM0_HRC0 SCR2: SCR2 (Bitfield-Mask: 0xff) */ - -/* ================================================================================ */ -/* ================ struct 'HRPWM0_HRC1' Position & Mask ================ */ -/* ================================================================================ */ - -/* ------------------------------- HRPWM0_HRC1_GC ------------------------------- */ -#define HRPWM0_HRC1_GC_HRM0_Pos \ - (0UL) /*!< HRPWM0_HRC1 GC: HRM0 (Bit 0) */ -#define HRPWM0_HRC1_GC_HRM0_Msk \ - (0x3UL) /*!< HRPWM0_HRC1 GC: HRM0 (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC1_GC_HRM1_Pos \ - (2UL) /*!< HRPWM0_HRC1 GC: HRM1 (Bit 2) */ -#define HRPWM0_HRC1_GC_HRM1_Msk \ - (0xcUL) /*!< HRPWM0_HRC1 GC: HRM1 (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC1_GC_DTE_Pos \ - (8UL) /*!< HRPWM0_HRC1 GC: DTE (Bit 8) */ -#define HRPWM0_HRC1_GC_DTE_Msk \ - (0x100UL) /*!< HRPWM0_HRC1 GC: DTE (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC1_GC_TR0E_Pos \ - (9UL) /*!< HRPWM0_HRC1 GC: TR0E (Bit 9) */ -#define HRPWM0_HRC1_GC_TR0E_Msk \ - (0x200UL) /*!< HRPWM0_HRC1 GC: TR0E (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC1_GC_TR1E_Pos \ - (10UL) /*!< HRPWM0_HRC1 GC: TR1E (Bit 10) */ -#define HRPWM0_HRC1_GC_TR1E_Msk \ - (0x400UL) /*!< HRPWM0_HRC1 GC: TR1E (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC1_GC_STC_Pos \ - (11UL) /*!< HRPWM0_HRC1 GC: STC (Bit 11) */ -#define HRPWM0_HRC1_GC_STC_Msk \ - (0x800UL) /*!< HRPWM0_HRC1 GC: STC (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC1_GC_DSTC_Pos \ - (12UL) /*!< HRPWM0_HRC1 GC: DSTC (Bit 12) */ -#define HRPWM0_HRC1_GC_DSTC_Msk \ - (0x1000UL) /*!< HRPWM0_HRC1 GC: DSTC (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC1_GC_OCS0_Pos \ - (13UL) /*!< HRPWM0_HRC1 GC: OCS0 (Bit 13) */ -#define HRPWM0_HRC1_GC_OCS0_Msk \ - (0x2000UL) /*!< HRPWM0_HRC1 GC: OCS0 (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC1_GC_OCS1_Pos \ - (14UL) /*!< HRPWM0_HRC1 GC: OCS1 (Bit 14) */ -#define HRPWM0_HRC1_GC_OCS1_Msk \ - (0x4000UL) /*!< HRPWM0_HRC1 GC: OCS1 (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC1_GC_DTUS_Pos \ - (16UL) /*!< HRPWM0_HRC1 GC: DTUS (Bit 16) */ -#define HRPWM0_HRC1_GC_DTUS_Msk \ - (0x10000UL) /*!< HRPWM0_HRC1 GC: DTUS (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_HRC1_PL ------------------------------- */ -#define HRPWM0_HRC1_PL_PSL0_Pos \ - (0UL) /*!< HRPWM0_HRC1 PL: PSL0 (Bit 0) */ -#define HRPWM0_HRC1_PL_PSL0_Msk \ - (0x1UL) /*!< HRPWM0_HRC1 PL: PSL0 (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC1_PL_PSL1_Pos \ - (1UL) /*!< HRPWM0_HRC1 PL: PSL1 (Bit 1) */ -#define HRPWM0_HRC1_PL_PSL1_Msk \ - (0x2UL) /*!< HRPWM0_HRC1 PL: PSL1 (Bitfield-Mask: 0x01) */ - -/* ------------------------------ HRPWM0_HRC1_GSEL ------------------------------ */ -#define HRPWM0_HRC1_GSEL_C0SS_Pos \ - (0UL) /*!< HRPWM0_HRC1 GSEL: C0SS (Bit 0) */ -#define HRPWM0_HRC1_GSEL_C0SS_Msk \ - (0x7UL) /*!< HRPWM0_HRC1 GSEL: C0SS (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC1_GSEL_C0CS_Pos \ - (3UL) /*!< HRPWM0_HRC1 GSEL: C0CS (Bit 3) */ -#define HRPWM0_HRC1_GSEL_C0CS_Msk \ - (0x38UL) /*!< HRPWM0_HRC1 GSEL: C0CS (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC1_GSEL_S0M_Pos \ - (6UL) /*!< HRPWM0_HRC1 GSEL: S0M (Bit 6) */ -#define HRPWM0_HRC1_GSEL_S0M_Msk \ - (0xc0UL) /*!< HRPWM0_HRC1 GSEL: S0M (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC1_GSEL_C0M_Pos \ - (8UL) /*!< HRPWM0_HRC1 GSEL: C0M (Bit 8) */ -#define HRPWM0_HRC1_GSEL_C0M_Msk \ - (0x300UL) /*!< HRPWM0_HRC1 GSEL: C0M (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC1_GSEL_S0ES_Pos \ - (10UL) /*!< HRPWM0_HRC1 GSEL: S0ES (Bit 10) */ -#define HRPWM0_HRC1_GSEL_S0ES_Msk \ - (0xc00UL) /*!< HRPWM0_HRC1 GSEL: S0ES (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC1_GSEL_C0ES_Pos \ - (12UL) /*!< HRPWM0_HRC1 GSEL: C0ES (Bit 12) */ -#define HRPWM0_HRC1_GSEL_C0ES_Msk \ - (0x3000UL) /*!< HRPWM0_HRC1 GSEL: C0ES (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC1_GSEL_C1SS_Pos \ - (16UL) /*!< HRPWM0_HRC1 GSEL: C1SS (Bit 16) */ -#define HRPWM0_HRC1_GSEL_C1SS_Msk \ - (0x70000UL) /*!< HRPWM0_HRC1 GSEL: C1SS (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC1_GSEL_C1CS_Pos \ - (19UL) /*!< HRPWM0_HRC1 GSEL: C1CS (Bit 19) */ -#define HRPWM0_HRC1_GSEL_C1CS_Msk \ - (0x380000UL) /*!< HRPWM0_HRC1 GSEL: C1CS (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC1_GSEL_S1M_Pos \ - (22UL) /*!< HRPWM0_HRC1 GSEL: S1M (Bit 22) */ -#define HRPWM0_HRC1_GSEL_S1M_Msk \ - (0xc00000UL) /*!< HRPWM0_HRC1 GSEL: S1M (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC1_GSEL_C1M_Pos \ - (24UL) /*!< HRPWM0_HRC1 GSEL: C1M (Bit 24) */ -#define HRPWM0_HRC1_GSEL_C1M_Msk \ - (0x3000000UL) /*!< HRPWM0_HRC1 GSEL: C1M (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC1_GSEL_S1ES_Pos \ - (26UL) /*!< HRPWM0_HRC1 GSEL: S1ES (Bit 26) */ -#define HRPWM0_HRC1_GSEL_S1ES_Msk \ - (0xc000000UL) /*!< HRPWM0_HRC1 GSEL: S1ES (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC1_GSEL_C1ES_Pos \ - (28UL) /*!< HRPWM0_HRC1 GSEL: C1ES (Bit 28) */ -#define HRPWM0_HRC1_GSEL_C1ES_Msk \ - (0x30000000UL) /*!< HRPWM0_HRC1 GSEL: C1ES (Bitfield-Mask: 0x03) */ - -/* ------------------------------ HRPWM0_HRC1_TSEL ------------------------------ */ -#define HRPWM0_HRC1_TSEL_TSEL0_Pos \ - (0UL) /*!< HRPWM0_HRC1 TSEL: TSEL0 (Bit 0) */ -#define HRPWM0_HRC1_TSEL_TSEL0_Msk \ - (0x7UL) /*!< HRPWM0_HRC1 TSEL: TSEL0 (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC1_TSEL_TSEL1_Pos \ - (3UL) /*!< HRPWM0_HRC1 TSEL: TSEL1 (Bit 3) */ -#define HRPWM0_HRC1_TSEL_TSEL1_Msk \ - (0x38UL) /*!< HRPWM0_HRC1 TSEL: TSEL1 (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC1_TSEL_TS0E_Pos \ - (16UL) /*!< HRPWM0_HRC1 TSEL: TS0E (Bit 16) */ -#define HRPWM0_HRC1_TSEL_TS0E_Msk \ - (0x10000UL) /*!< HRPWM0_HRC1 TSEL: TS0E (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC1_TSEL_TS1E_Pos \ - (17UL) /*!< HRPWM0_HRC1 TSEL: TS1E (Bit 17) */ -#define HRPWM0_HRC1_TSEL_TS1E_Msk \ - (0x20000UL) /*!< HRPWM0_HRC1 TSEL: TS1E (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_HRC1_SC ------------------------------- */ -#define HRPWM0_HRC1_SC_ST_Pos \ - (0UL) /*!< HRPWM0_HRC1 SC: ST (Bit 0) */ -#define HRPWM0_HRC1_SC_ST_Msk \ - (0x1UL) /*!< HRPWM0_HRC1 SC: ST (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_HRC1_DCR ------------------------------ */ -#define HRPWM0_HRC1_DCR_DTRV_Pos \ - (0UL) /*!< HRPWM0_HRC1 DCR: DTRV (Bit 0) */ -#define HRPWM0_HRC1_DCR_DTRV_Msk \ - (0xffffUL) /*!< HRPWM0_HRC1 DCR: DTRV (Bitfield-Mask: 0xffff) */ - -/* ------------------------------- HRPWM0_HRC1_DCF ------------------------------ */ -#define HRPWM0_HRC1_DCF_DTFV_Pos \ - (0UL) /*!< HRPWM0_HRC1 DCF: DTFV (Bit 0) */ -#define HRPWM0_HRC1_DCF_DTFV_Msk \ - (0xffffUL) /*!< HRPWM0_HRC1 DCF: DTFV (Bitfield-Mask: 0xffff) */ - -/* ------------------------------- HRPWM0_HRC1_CR1 ------------------------------ */ -#define HRPWM0_HRC1_CR1_CR1_Pos \ - (0UL) /*!< HRPWM0_HRC1 CR1: CR1 (Bit 0) */ -#define HRPWM0_HRC1_CR1_CR1_Msk \ - (0xffUL) /*!< HRPWM0_HRC1 CR1: CR1 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- HRPWM0_HRC1_CR2 ------------------------------ */ -#define HRPWM0_HRC1_CR2_CR2_Pos \ - (0UL) /*!< HRPWM0_HRC1 CR2: CR2 (Bit 0) */ -#define HRPWM0_HRC1_CR2_CR2_Msk \ - (0xffUL) /*!< HRPWM0_HRC1 CR2: CR2 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- HRPWM0_HRC1_SSC ------------------------------ */ -#define HRPWM0_HRC1_SSC_SST_Pos \ - (0UL) /*!< HRPWM0_HRC1 SSC: SST (Bit 0) */ -#define HRPWM0_HRC1_SSC_SST_Msk \ - (0x1UL) /*!< HRPWM0_HRC1 SSC: SST (Bitfield-Mask: 0x01) */ - -/* ------------------------------ HRPWM0_HRC1_SDCR ------------------------------ */ -#define HRPWM0_HRC1_SDCR_SDTRV_Pos \ - (0UL) /*!< HRPWM0_HRC1 SDCR: SDTRV (Bit 0) */ -#define HRPWM0_HRC1_SDCR_SDTRV_Msk \ - (0xffffUL) /*!< HRPWM0_HRC1 SDCR: SDTRV (Bitfield-Mask: 0xffff) */ - -/* ------------------------------ HRPWM0_HRC1_SDCF ------------------------------ */ -#define HRPWM0_HRC1_SDCF_SDTFV_Pos \ - (0UL) /*!< HRPWM0_HRC1 SDCF: SDTFV (Bit 0) */ -#define HRPWM0_HRC1_SDCF_SDTFV_Msk \ - (0xffffUL) /*!< HRPWM0_HRC1 SDCF: SDTFV (Bitfield-Mask: 0xffff) */ - -/* ------------------------------ HRPWM0_HRC1_SCR1 ------------------------------ */ -#define HRPWM0_HRC1_SCR1_SCR1_Pos \ - (0UL) /*!< HRPWM0_HRC1 SCR1: SCR1 (Bit 0) */ -#define HRPWM0_HRC1_SCR1_SCR1_Msk \ - (0xffUL) /*!< HRPWM0_HRC1 SCR1: SCR1 (Bitfield-Mask: 0xff) */ - -/* ------------------------------ HRPWM0_HRC1_SCR2 ------------------------------ */ -#define HRPWM0_HRC1_SCR2_SCR2_Pos \ - (0UL) /*!< HRPWM0_HRC1 SCR2: SCR2 (Bit 0) */ -#define HRPWM0_HRC1_SCR2_SCR2_Msk \ - (0xffUL) /*!< HRPWM0_HRC1 SCR2: SCR2 (Bitfield-Mask: 0xff) */ - -/* ================================================================================ */ -/* ================ struct 'HRPWM0_HRC2' Position & Mask ================ */ -/* ================================================================================ */ - -/* ------------------------------- HRPWM0_HRC2_GC ------------------------------- */ -#define HRPWM0_HRC2_GC_HRM0_Pos \ - (0UL) /*!< HRPWM0_HRC2 GC: HRM0 (Bit 0) */ -#define HRPWM0_HRC2_GC_HRM0_Msk \ - (0x3UL) /*!< HRPWM0_HRC2 GC: HRM0 (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC2_GC_HRM1_Pos \ - (2UL) /*!< HRPWM0_HRC2 GC: HRM1 (Bit 2) */ -#define HRPWM0_HRC2_GC_HRM1_Msk \ - (0xcUL) /*!< HRPWM0_HRC2 GC: HRM1 (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC2_GC_DTE_Pos \ - (8UL) /*!< HRPWM0_HRC2 GC: DTE (Bit 8) */ -#define HRPWM0_HRC2_GC_DTE_Msk \ - (0x100UL) /*!< HRPWM0_HRC2 GC: DTE (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC2_GC_TR0E_Pos \ - (9UL) /*!< HRPWM0_HRC2 GC: TR0E (Bit 9) */ -#define HRPWM0_HRC2_GC_TR0E_Msk \ - (0x200UL) /*!< HRPWM0_HRC2 GC: TR0E (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC2_GC_TR1E_Pos \ - (10UL) /*!< HRPWM0_HRC2 GC: TR1E (Bit 10) */ -#define HRPWM0_HRC2_GC_TR1E_Msk \ - (0x400UL) /*!< HRPWM0_HRC2 GC: TR1E (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC2_GC_STC_Pos \ - (11UL) /*!< HRPWM0_HRC2 GC: STC (Bit 11) */ -#define HRPWM0_HRC2_GC_STC_Msk \ - (0x800UL) /*!< HRPWM0_HRC2 GC: STC (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC2_GC_DSTC_Pos \ - (12UL) /*!< HRPWM0_HRC2 GC: DSTC (Bit 12) */ -#define HRPWM0_HRC2_GC_DSTC_Msk \ - (0x1000UL) /*!< HRPWM0_HRC2 GC: DSTC (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC2_GC_OCS0_Pos \ - (13UL) /*!< HRPWM0_HRC2 GC: OCS0 (Bit 13) */ -#define HRPWM0_HRC2_GC_OCS0_Msk \ - (0x2000UL) /*!< HRPWM0_HRC2 GC: OCS0 (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC2_GC_OCS1_Pos \ - (14UL) /*!< HRPWM0_HRC2 GC: OCS1 (Bit 14) */ -#define HRPWM0_HRC2_GC_OCS1_Msk \ - (0x4000UL) /*!< HRPWM0_HRC2 GC: OCS1 (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC2_GC_DTUS_Pos \ - (16UL) /*!< HRPWM0_HRC2 GC: DTUS (Bit 16) */ -#define HRPWM0_HRC2_GC_DTUS_Msk \ - (0x10000UL) /*!< HRPWM0_HRC2 GC: DTUS (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_HRC2_PL ------------------------------- */ -#define HRPWM0_HRC2_PL_PSL0_Pos \ - (0UL) /*!< HRPWM0_HRC2 PL: PSL0 (Bit 0) */ -#define HRPWM0_HRC2_PL_PSL0_Msk \ - (0x1UL) /*!< HRPWM0_HRC2 PL: PSL0 (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC2_PL_PSL1_Pos \ - (1UL) /*!< HRPWM0_HRC2 PL: PSL1 (Bit 1) */ -#define HRPWM0_HRC2_PL_PSL1_Msk \ - (0x2UL) /*!< HRPWM0_HRC2 PL: PSL1 (Bitfield-Mask: 0x01) */ - -/* ------------------------------ HRPWM0_HRC2_GSEL ------------------------------ */ -#define HRPWM0_HRC2_GSEL_C0SS_Pos \ - (0UL) /*!< HRPWM0_HRC2 GSEL: C0SS (Bit 0) */ -#define HRPWM0_HRC2_GSEL_C0SS_Msk \ - (0x7UL) /*!< HRPWM0_HRC2 GSEL: C0SS (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC2_GSEL_C0CS_Pos \ - (3UL) /*!< HRPWM0_HRC2 GSEL: C0CS (Bit 3) */ -#define HRPWM0_HRC2_GSEL_C0CS_Msk \ - (0x38UL) /*!< HRPWM0_HRC2 GSEL: C0CS (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC2_GSEL_S0M_Pos \ - (6UL) /*!< HRPWM0_HRC2 GSEL: S0M (Bit 6) */ -#define HRPWM0_HRC2_GSEL_S0M_Msk \ - (0xc0UL) /*!< HRPWM0_HRC2 GSEL: S0M (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC2_GSEL_C0M_Pos \ - (8UL) /*!< HRPWM0_HRC2 GSEL: C0M (Bit 8) */ -#define HRPWM0_HRC2_GSEL_C0M_Msk \ - (0x300UL) /*!< HRPWM0_HRC2 GSEL: C0M (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC2_GSEL_S0ES_Pos \ - (10UL) /*!< HRPWM0_HRC2 GSEL: S0ES (Bit 10) */ -#define HRPWM0_HRC2_GSEL_S0ES_Msk \ - (0xc00UL) /*!< HRPWM0_HRC2 GSEL: S0ES (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC2_GSEL_C0ES_Pos \ - (12UL) /*!< HRPWM0_HRC2 GSEL: C0ES (Bit 12) */ -#define HRPWM0_HRC2_GSEL_C0ES_Msk \ - (0x3000UL) /*!< HRPWM0_HRC2 GSEL: C0ES (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC2_GSEL_C1SS_Pos \ - (16UL) /*!< HRPWM0_HRC2 GSEL: C1SS (Bit 16) */ -#define HRPWM0_HRC2_GSEL_C1SS_Msk \ - (0x70000UL) /*!< HRPWM0_HRC2 GSEL: C1SS (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC2_GSEL_C1CS_Pos \ - (19UL) /*!< HRPWM0_HRC2 GSEL: C1CS (Bit 19) */ -#define HRPWM0_HRC2_GSEL_C1CS_Msk \ - (0x380000UL) /*!< HRPWM0_HRC2 GSEL: C1CS (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC2_GSEL_S1M_Pos \ - (22UL) /*!< HRPWM0_HRC2 GSEL: S1M (Bit 22) */ -#define HRPWM0_HRC2_GSEL_S1M_Msk \ - (0xc00000UL) /*!< HRPWM0_HRC2 GSEL: S1M (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC2_GSEL_C1M_Pos \ - (24UL) /*!< HRPWM0_HRC2 GSEL: C1M (Bit 24) */ -#define HRPWM0_HRC2_GSEL_C1M_Msk \ - (0x3000000UL) /*!< HRPWM0_HRC2 GSEL: C1M (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC2_GSEL_S1ES_Pos \ - (26UL) /*!< HRPWM0_HRC2 GSEL: S1ES (Bit 26) */ -#define HRPWM0_HRC2_GSEL_S1ES_Msk \ - (0xc000000UL) /*!< HRPWM0_HRC2 GSEL: S1ES (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC2_GSEL_C1ES_Pos \ - (28UL) /*!< HRPWM0_HRC2 GSEL: C1ES (Bit 28) */ -#define HRPWM0_HRC2_GSEL_C1ES_Msk \ - (0x30000000UL) /*!< HRPWM0_HRC2 GSEL: C1ES (Bitfield-Mask: 0x03) */ - -/* ------------------------------ HRPWM0_HRC2_TSEL ------------------------------ */ -#define HRPWM0_HRC2_TSEL_TSEL0_Pos \ - (0UL) /*!< HRPWM0_HRC2 TSEL: TSEL0 (Bit 0) */ -#define HRPWM0_HRC2_TSEL_TSEL0_Msk \ - (0x7UL) /*!< HRPWM0_HRC2 TSEL: TSEL0 (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC2_TSEL_TSEL1_Pos \ - (3UL) /*!< HRPWM0_HRC2 TSEL: TSEL1 (Bit 3) */ -#define HRPWM0_HRC2_TSEL_TSEL1_Msk \ - (0x38UL) /*!< HRPWM0_HRC2 TSEL: TSEL1 (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC2_TSEL_TS0E_Pos \ - (16UL) /*!< HRPWM0_HRC2 TSEL: TS0E (Bit 16) */ -#define HRPWM0_HRC2_TSEL_TS0E_Msk \ - (0x10000UL) /*!< HRPWM0_HRC2 TSEL: TS0E (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC2_TSEL_TS1E_Pos \ - (17UL) /*!< HRPWM0_HRC2 TSEL: TS1E (Bit 17) */ -#define HRPWM0_HRC2_TSEL_TS1E_Msk \ - (0x20000UL) /*!< HRPWM0_HRC2 TSEL: TS1E (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_HRC2_SC ------------------------------- */ -#define HRPWM0_HRC2_SC_ST_Pos \ - (0UL) /*!< HRPWM0_HRC2 SC: ST (Bit 0) */ -#define HRPWM0_HRC2_SC_ST_Msk \ - (0x1UL) /*!< HRPWM0_HRC2 SC: ST (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_HRC2_DCR ------------------------------ */ -#define HRPWM0_HRC2_DCR_DTRV_Pos \ - (0UL) /*!< HRPWM0_HRC2 DCR: DTRV (Bit 0) */ -#define HRPWM0_HRC2_DCR_DTRV_Msk \ - (0xffffUL) /*!< HRPWM0_HRC2 DCR: DTRV (Bitfield-Mask: 0xffff) */ - -/* ------------------------------- HRPWM0_HRC2_DCF ------------------------------ */ -#define HRPWM0_HRC2_DCF_DTFV_Pos \ - (0UL) /*!< HRPWM0_HRC2 DCF: DTFV (Bit 0) */ -#define HRPWM0_HRC2_DCF_DTFV_Msk \ - (0xffffUL) /*!< HRPWM0_HRC2 DCF: DTFV (Bitfield-Mask: 0xffff) */ - -/* ------------------------------- HRPWM0_HRC2_CR1 ------------------------------ */ -#define HRPWM0_HRC2_CR1_CR1_Pos \ - (0UL) /*!< HRPWM0_HRC2 CR1: CR1 (Bit 0) */ -#define HRPWM0_HRC2_CR1_CR1_Msk \ - (0xffUL) /*!< HRPWM0_HRC2 CR1: CR1 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- HRPWM0_HRC2_CR2 ------------------------------ */ -#define HRPWM0_HRC2_CR2_CR2_Pos \ - (0UL) /*!< HRPWM0_HRC2 CR2: CR2 (Bit 0) */ -#define HRPWM0_HRC2_CR2_CR2_Msk \ - (0xffUL) /*!< HRPWM0_HRC2 CR2: CR2 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- HRPWM0_HRC2_SSC ------------------------------ */ -#define HRPWM0_HRC2_SSC_SST_Pos \ - (0UL) /*!< HRPWM0_HRC2 SSC: SST (Bit 0) */ -#define HRPWM0_HRC2_SSC_SST_Msk \ - (0x1UL) /*!< HRPWM0_HRC2 SSC: SST (Bitfield-Mask: 0x01) */ - -/* ------------------------------ HRPWM0_HRC2_SDCR ------------------------------ */ -#define HRPWM0_HRC2_SDCR_SDTRV_Pos \ - (0UL) /*!< HRPWM0_HRC2 SDCR: SDTRV (Bit 0) */ -#define HRPWM0_HRC2_SDCR_SDTRV_Msk \ - (0xffffUL) /*!< HRPWM0_HRC2 SDCR: SDTRV (Bitfield-Mask: 0xffff) */ - -/* ------------------------------ HRPWM0_HRC2_SDCF ------------------------------ */ -#define HRPWM0_HRC2_SDCF_SDTFV_Pos \ - (0UL) /*!< HRPWM0_HRC2 SDCF: SDTFV (Bit 0) */ -#define HRPWM0_HRC2_SDCF_SDTFV_Msk \ - (0xffffUL) /*!< HRPWM0_HRC2 SDCF: SDTFV (Bitfield-Mask: 0xffff) */ - -/* ------------------------------ HRPWM0_HRC2_SCR1 ------------------------------ */ -#define HRPWM0_HRC2_SCR1_SCR1_Pos \ - (0UL) /*!< HRPWM0_HRC2 SCR1: SCR1 (Bit 0) */ -#define HRPWM0_HRC2_SCR1_SCR1_Msk \ - (0xffUL) /*!< HRPWM0_HRC2 SCR1: SCR1 (Bitfield-Mask: 0xff) */ - -/* ------------------------------ HRPWM0_HRC2_SCR2 ------------------------------ */ -#define HRPWM0_HRC2_SCR2_SCR2_Pos \ - (0UL) /*!< HRPWM0_HRC2 SCR2: SCR2 (Bit 0) */ -#define HRPWM0_HRC2_SCR2_SCR2_Msk \ - (0xffUL) /*!< HRPWM0_HRC2 SCR2: SCR2 (Bitfield-Mask: 0xff) */ - -/* ================================================================================ */ -/* ================ struct 'HRPWM0_HRC3' Position & Mask ================ */ -/* ================================================================================ */ - -/* ------------------------------- HRPWM0_HRC3_GC ------------------------------- */ -#define HRPWM0_HRC3_GC_HRM0_Pos \ - (0UL) /*!< HRPWM0_HRC3 GC: HRM0 (Bit 0) */ -#define HRPWM0_HRC3_GC_HRM0_Msk \ - (0x3UL) /*!< HRPWM0_HRC3 GC: HRM0 (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC3_GC_HRM1_Pos \ - (2UL) /*!< HRPWM0_HRC3 GC: HRM1 (Bit 2) */ -#define HRPWM0_HRC3_GC_HRM1_Msk \ - (0xcUL) /*!< HRPWM0_HRC3 GC: HRM1 (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC3_GC_DTE_Pos \ - (8UL) /*!< HRPWM0_HRC3 GC: DTE (Bit 8) */ -#define HRPWM0_HRC3_GC_DTE_Msk \ - (0x100UL) /*!< HRPWM0_HRC3 GC: DTE (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC3_GC_TR0E_Pos \ - (9UL) /*!< HRPWM0_HRC3 GC: TR0E (Bit 9) */ -#define HRPWM0_HRC3_GC_TR0E_Msk \ - (0x200UL) /*!< HRPWM0_HRC3 GC: TR0E (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC3_GC_TR1E_Pos \ - (10UL) /*!< HRPWM0_HRC3 GC: TR1E (Bit 10) */ -#define HRPWM0_HRC3_GC_TR1E_Msk \ - (0x400UL) /*!< HRPWM0_HRC3 GC: TR1E (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC3_GC_STC_Pos \ - (11UL) /*!< HRPWM0_HRC3 GC: STC (Bit 11) */ -#define HRPWM0_HRC3_GC_STC_Msk \ - (0x800UL) /*!< HRPWM0_HRC3 GC: STC (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC3_GC_DSTC_Pos \ - (12UL) /*!< HRPWM0_HRC3 GC: DSTC (Bit 12) */ -#define HRPWM0_HRC3_GC_DSTC_Msk \ - (0x1000UL) /*!< HRPWM0_HRC3 GC: DSTC (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC3_GC_OCS0_Pos \ - (13UL) /*!< HRPWM0_HRC3 GC: OCS0 (Bit 13) */ -#define HRPWM0_HRC3_GC_OCS0_Msk \ - (0x2000UL) /*!< HRPWM0_HRC3 GC: OCS0 (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC3_GC_OCS1_Pos \ - (14UL) /*!< HRPWM0_HRC3 GC: OCS1 (Bit 14) */ -#define HRPWM0_HRC3_GC_OCS1_Msk \ - (0x4000UL) /*!< HRPWM0_HRC3 GC: OCS1 (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC3_GC_DTUS_Pos \ - (16UL) /*!< HRPWM0_HRC3 GC: DTUS (Bit 16) */ -#define HRPWM0_HRC3_GC_DTUS_Msk \ - (0x10000UL) /*!< HRPWM0_HRC3 GC: DTUS (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_HRC3_PL ------------------------------- */ -#define HRPWM0_HRC3_PL_PSL0_Pos \ - (0UL) /*!< HRPWM0_HRC3 PL: PSL0 (Bit 0) */ -#define HRPWM0_HRC3_PL_PSL0_Msk \ - (0x1UL) /*!< HRPWM0_HRC3 PL: PSL0 (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC3_PL_PSL1_Pos \ - (1UL) /*!< HRPWM0_HRC3 PL: PSL1 (Bit 1) */ -#define HRPWM0_HRC3_PL_PSL1_Msk \ - (0x2UL) /*!< HRPWM0_HRC3 PL: PSL1 (Bitfield-Mask: 0x01) */ - -/* ------------------------------ HRPWM0_HRC3_GSEL ------------------------------ */ -#define HRPWM0_HRC3_GSEL_C0SS_Pos \ - (0UL) /*!< HRPWM0_HRC3 GSEL: C0SS (Bit 0) */ -#define HRPWM0_HRC3_GSEL_C0SS_Msk \ - (0x7UL) /*!< HRPWM0_HRC3 GSEL: C0SS (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC3_GSEL_C0CS_Pos \ - (3UL) /*!< HRPWM0_HRC3 GSEL: C0CS (Bit 3) */ -#define HRPWM0_HRC3_GSEL_C0CS_Msk \ - (0x38UL) /*!< HRPWM0_HRC3 GSEL: C0CS (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC3_GSEL_S0M_Pos \ - (6UL) /*!< HRPWM0_HRC3 GSEL: S0M (Bit 6) */ -#define HRPWM0_HRC3_GSEL_S0M_Msk \ - (0xc0UL) /*!< HRPWM0_HRC3 GSEL: S0M (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC3_GSEL_C0M_Pos \ - (8UL) /*!< HRPWM0_HRC3 GSEL: C0M (Bit 8) */ -#define HRPWM0_HRC3_GSEL_C0M_Msk \ - (0x300UL) /*!< HRPWM0_HRC3 GSEL: C0M (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC3_GSEL_S0ES_Pos \ - (10UL) /*!< HRPWM0_HRC3 GSEL: S0ES (Bit 10) */ -#define HRPWM0_HRC3_GSEL_S0ES_Msk \ - (0xc00UL) /*!< HRPWM0_HRC3 GSEL: S0ES (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC3_GSEL_C0ES_Pos \ - (12UL) /*!< HRPWM0_HRC3 GSEL: C0ES (Bit 12) */ -#define HRPWM0_HRC3_GSEL_C0ES_Msk \ - (0x3000UL) /*!< HRPWM0_HRC3 GSEL: C0ES (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC3_GSEL_C1SS_Pos \ - (16UL) /*!< HRPWM0_HRC3 GSEL: C1SS (Bit 16) */ -#define HRPWM0_HRC3_GSEL_C1SS_Msk \ - (0x70000UL) /*!< HRPWM0_HRC3 GSEL: C1SS (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC3_GSEL_C1CS_Pos \ - (19UL) /*!< HRPWM0_HRC3 GSEL: C1CS (Bit 19) */ -#define HRPWM0_HRC3_GSEL_C1CS_Msk \ - (0x380000UL) /*!< HRPWM0_HRC3 GSEL: C1CS (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC3_GSEL_S1M_Pos \ - (22UL) /*!< HRPWM0_HRC3 GSEL: S1M (Bit 22) */ -#define HRPWM0_HRC3_GSEL_S1M_Msk \ - (0xc00000UL) /*!< HRPWM0_HRC3 GSEL: S1M (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC3_GSEL_C1M_Pos \ - (24UL) /*!< HRPWM0_HRC3 GSEL: C1M (Bit 24) */ -#define HRPWM0_HRC3_GSEL_C1M_Msk \ - (0x3000000UL) /*!< HRPWM0_HRC3 GSEL: C1M (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC3_GSEL_S1ES_Pos \ - (26UL) /*!< HRPWM0_HRC3 GSEL: S1ES (Bit 26) */ -#define HRPWM0_HRC3_GSEL_S1ES_Msk \ - (0xc000000UL) /*!< HRPWM0_HRC3 GSEL: S1ES (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC3_GSEL_C1ES_Pos \ - (28UL) /*!< HRPWM0_HRC3 GSEL: C1ES (Bit 28) */ -#define HRPWM0_HRC3_GSEL_C1ES_Msk \ - (0x30000000UL) /*!< HRPWM0_HRC3 GSEL: C1ES (Bitfield-Mask: 0x03) */ - -/* ------------------------------ HRPWM0_HRC3_TSEL ------------------------------ */ -#define HRPWM0_HRC3_TSEL_TSEL0_Pos \ - (0UL) /*!< HRPWM0_HRC3 TSEL: TSEL0 (Bit 0) */ -#define HRPWM0_HRC3_TSEL_TSEL0_Msk \ - (0x7UL) /*!< HRPWM0_HRC3 TSEL: TSEL0 (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC3_TSEL_TSEL1_Pos \ - (3UL) /*!< HRPWM0_HRC3 TSEL: TSEL1 (Bit 3) */ -#define HRPWM0_HRC3_TSEL_TSEL1_Msk \ - (0x38UL) /*!< HRPWM0_HRC3 TSEL: TSEL1 (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC3_TSEL_TS0E_Pos \ - (16UL) /*!< HRPWM0_HRC3 TSEL: TS0E (Bit 16) */ -#define HRPWM0_HRC3_TSEL_TS0E_Msk \ - (0x10000UL) /*!< HRPWM0_HRC3 TSEL: TS0E (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC3_TSEL_TS1E_Pos \ - (17UL) /*!< HRPWM0_HRC3 TSEL: TS1E (Bit 17) */ -#define HRPWM0_HRC3_TSEL_TS1E_Msk \ - (0x20000UL) /*!< HRPWM0_HRC3 TSEL: TS1E (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_HRC3_SC ------------------------------- */ -#define HRPWM0_HRC3_SC_ST_Pos \ - (0UL) /*!< HRPWM0_HRC3 SC: ST (Bit 0) */ -#define HRPWM0_HRC3_SC_ST_Msk \ - (0x1UL) /*!< HRPWM0_HRC3 SC: ST (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_HRC3_DCR ------------------------------ */ -#define HRPWM0_HRC3_DCR_DTRV_Pos \ - (0UL) /*!< HRPWM0_HRC3 DCR: DTRV (Bit 0) */ -#define HRPWM0_HRC3_DCR_DTRV_Msk \ - (0xffffUL) /*!< HRPWM0_HRC3 DCR: DTRV (Bitfield-Mask: 0xffff) */ - -/* ------------------------------- HRPWM0_HRC3_DCF ------------------------------ */ -#define HRPWM0_HRC3_DCF_DTFV_Pos \ - (0UL) /*!< HRPWM0_HRC3 DCF: DTFV (Bit 0) */ -#define HRPWM0_HRC3_DCF_DTFV_Msk \ - (0xffffUL) /*!< HRPWM0_HRC3 DCF: DTFV (Bitfield-Mask: 0xffff) */ - -/* ------------------------------- HRPWM0_HRC3_CR1 ------------------------------ */ -#define HRPWM0_HRC3_CR1_CR1_Pos \ - (0UL) /*!< HRPWM0_HRC3 CR1: CR1 (Bit 0) */ -#define HRPWM0_HRC3_CR1_CR1_Msk \ - (0xffUL) /*!< HRPWM0_HRC3 CR1: CR1 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- HRPWM0_HRC3_CR2 ------------------------------ */ -#define HRPWM0_HRC3_CR2_CR2_Pos \ - (0UL) /*!< HRPWM0_HRC3 CR2: CR2 (Bit 0) */ -#define HRPWM0_HRC3_CR2_CR2_Msk \ - (0xffUL) /*!< HRPWM0_HRC3 CR2: CR2 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- HRPWM0_HRC3_SSC ------------------------------ */ -#define HRPWM0_HRC3_SSC_SST_Pos \ - (0UL) /*!< HRPWM0_HRC3 SSC: SST (Bit 0) */ -#define HRPWM0_HRC3_SSC_SST_Msk \ - (0x1UL) /*!< HRPWM0_HRC3 SSC: SST (Bitfield-Mask: 0x01) */ - -/* ------------------------------ HRPWM0_HRC3_SDCR ------------------------------ */ -#define HRPWM0_HRC3_SDCR_SDTRV_Pos \ - (0UL) /*!< HRPWM0_HRC3 SDCR: SDTRV (Bit 0) */ -#define HRPWM0_HRC3_SDCR_SDTRV_Msk \ - (0xffffUL) /*!< HRPWM0_HRC3 SDCR: SDTRV (Bitfield-Mask: 0xffff) */ - -/* ------------------------------ HRPWM0_HRC3_SDCF ------------------------------ */ -#define HRPWM0_HRC3_SDCF_SDTFV_Pos \ - (0UL) /*!< HRPWM0_HRC3 SDCF: SDTFV (Bit 0) */ -#define HRPWM0_HRC3_SDCF_SDTFV_Msk \ - (0xffffUL) /*!< HRPWM0_HRC3 SDCF: SDTFV (Bitfield-Mask: 0xffff) */ - -/* ------------------------------ HRPWM0_HRC3_SCR1 ------------------------------ */ -#define HRPWM0_HRC3_SCR1_SCR1_Pos \ - (0UL) /*!< HRPWM0_HRC3 SCR1: SCR1 (Bit 0) */ -#define HRPWM0_HRC3_SCR1_SCR1_Msk \ - (0xffUL) /*!< HRPWM0_HRC3 SCR1: SCR1 (Bitfield-Mask: 0xff) */ - -/* ------------------------------ HRPWM0_HRC3_SCR2 ------------------------------ */ -#define HRPWM0_HRC3_SCR2_SCR2_Pos \ - (0UL) /*!< HRPWM0_HRC3 SCR2: SCR2 (Bit 0) */ -#define HRPWM0_HRC3_SCR2_SCR2_Msk \ - (0xffUL) /*!< HRPWM0_HRC3 SCR2: SCR2 (Bitfield-Mask: 0xff) */ - -/* ================================================================================ */ -/* ================ Group 'POSIF' Position & Mask ================ */ -/* ================================================================================ */ - -/* --------------------------------- POSIF_PCONF -------------------------------- */ -#define POSIF_PCONF_FSEL_Pos \ - (0UL) /*!< POSIF PCONF: FSEL (Bit 0) */ -#define POSIF_PCONF_FSEL_Msk \ - (0x3UL) /*!< POSIF PCONF: FSEL (Bitfield-Mask: 0x03) */ -#define POSIF_PCONF_QDCM_Pos \ - (2UL) /*!< POSIF PCONF: QDCM (Bit 2) */ -#define POSIF_PCONF_QDCM_Msk \ - (0x4UL) /*!< POSIF PCONF: QDCM (Bitfield-Mask: 0x01) */ -#define POSIF_PCONF_HIDG_Pos \ - (4UL) /*!< POSIF PCONF: HIDG (Bit 4) */ -#define POSIF_PCONF_HIDG_Msk \ - (0x10UL) /*!< POSIF PCONF: HIDG (Bitfield-Mask: 0x01) */ -#define POSIF_PCONF_MCUE_Pos \ - (5UL) /*!< POSIF PCONF: MCUE (Bit 5) */ -#define POSIF_PCONF_MCUE_Msk \ - (0x20UL) /*!< POSIF PCONF: MCUE (Bitfield-Mask: 0x01) */ -#define POSIF_PCONF_INSEL0_Pos \ - (8UL) /*!< POSIF PCONF: INSEL0 (Bit 8) */ -#define POSIF_PCONF_INSEL0_Msk \ - (0x300UL) /*!< POSIF PCONF: INSEL0 (Bitfield-Mask: 0x03) */ -#define POSIF_PCONF_INSEL1_Pos \ - (10UL) /*!< POSIF PCONF: INSEL1 (Bit 10) */ -#define POSIF_PCONF_INSEL1_Msk \ - (0xc00UL) /*!< POSIF PCONF: INSEL1 (Bitfield-Mask: 0x03) */ -#define POSIF_PCONF_INSEL2_Pos \ - (12UL) /*!< POSIF PCONF: INSEL2 (Bit 12) */ -#define POSIF_PCONF_INSEL2_Msk \ - (0x3000UL) /*!< POSIF PCONF: INSEL2 (Bitfield-Mask: 0x03) */ -#define POSIF_PCONF_DSEL_Pos \ - (16UL) /*!< POSIF PCONF: DSEL (Bit 16) */ -#define POSIF_PCONF_DSEL_Msk \ - (0x10000UL) /*!< POSIF PCONF: DSEL (Bitfield-Mask: 0x01) */ -#define POSIF_PCONF_SPES_Pos \ - (17UL) /*!< POSIF PCONF: SPES (Bit 17) */ -#define POSIF_PCONF_SPES_Msk \ - (0x20000UL) /*!< POSIF PCONF: SPES (Bitfield-Mask: 0x01) */ -#define POSIF_PCONF_MSETS_Pos \ - (18UL) /*!< POSIF PCONF: MSETS (Bit 18) */ -#define POSIF_PCONF_MSETS_Msk \ - (0x1c0000UL) /*!< POSIF PCONF: MSETS (Bitfield-Mask: 0x07) */ -#define POSIF_PCONF_MSES_Pos \ - (21UL) /*!< POSIF PCONF: MSES (Bit 21) */ -#define POSIF_PCONF_MSES_Msk \ - (0x200000UL) /*!< POSIF PCONF: MSES (Bitfield-Mask: 0x01) */ -#define POSIF_PCONF_MSYNS_Pos \ - (22UL) /*!< POSIF PCONF: MSYNS (Bit 22) */ -#define POSIF_PCONF_MSYNS_Msk \ - (0xc00000UL) /*!< POSIF PCONF: MSYNS (Bitfield-Mask: 0x03) */ -#define POSIF_PCONF_EWIS_Pos \ - (24UL) /*!< POSIF PCONF: EWIS (Bit 24) */ -#define POSIF_PCONF_EWIS_Msk \ - (0x3000000UL) /*!< POSIF PCONF: EWIS (Bitfield-Mask: 0x03) */ -#define POSIF_PCONF_EWIE_Pos \ - (26UL) /*!< POSIF PCONF: EWIE (Bit 26) */ -#define POSIF_PCONF_EWIE_Msk \ - (0x4000000UL) /*!< POSIF PCONF: EWIE (Bitfield-Mask: 0x01) */ -#define POSIF_PCONF_EWIL_Pos \ - (27UL) /*!< POSIF PCONF: EWIL (Bit 27) */ -#define POSIF_PCONF_EWIL_Msk \ - (0x8000000UL) /*!< POSIF PCONF: EWIL (Bitfield-Mask: 0x01) */ -#define POSIF_PCONF_LPC_Pos \ - (28UL) /*!< POSIF PCONF: LPC (Bit 28) */ -#define POSIF_PCONF_LPC_Msk \ - (0x70000000UL) /*!< POSIF PCONF: LPC (Bitfield-Mask: 0x07) */ - -/* --------------------------------- POSIF_PSUS --------------------------------- */ -#define POSIF_PSUS_QSUS_Pos \ - (0UL) /*!< POSIF PSUS: QSUS (Bit 0) */ -#define POSIF_PSUS_QSUS_Msk \ - (0x3UL) /*!< POSIF PSUS: QSUS (Bitfield-Mask: 0x03) */ -#define POSIF_PSUS_MSUS_Pos \ - (2UL) /*!< POSIF PSUS: MSUS (Bit 2) */ -#define POSIF_PSUS_MSUS_Msk \ - (0xcUL) /*!< POSIF PSUS: MSUS (Bitfield-Mask: 0x03) */ - -/* --------------------------------- POSIF_PRUNS -------------------------------- */ -#define POSIF_PRUNS_SRB_Pos \ - (0UL) /*!< POSIF PRUNS: SRB (Bit 0) */ -#define POSIF_PRUNS_SRB_Msk \ - (0x1UL) /*!< POSIF PRUNS: SRB (Bitfield-Mask: 0x01) */ - -/* --------------------------------- POSIF_PRUNC -------------------------------- */ -#define POSIF_PRUNC_CRB_Pos \ - (0UL) /*!< POSIF PRUNC: CRB (Bit 0) */ -#define POSIF_PRUNC_CRB_Msk \ - (0x1UL) /*!< POSIF PRUNC: CRB (Bitfield-Mask: 0x01) */ -#define POSIF_PRUNC_CSM_Pos \ - (1UL) /*!< POSIF PRUNC: CSM (Bit 1) */ -#define POSIF_PRUNC_CSM_Msk \ - (0x2UL) /*!< POSIF PRUNC: CSM (Bitfield-Mask: 0x01) */ - -/* --------------------------------- POSIF_PRUN --------------------------------- */ -#define POSIF_PRUN_RB_Pos (0UL) /*!< POSIF PRUN: RB (Bit 0) */ -#define POSIF_PRUN_RB_Msk \ - (0x1UL) /*!< POSIF PRUN: RB (Bitfield-Mask: 0x01) */ - -/* --------------------------------- POSIF_MIDR --------------------------------- */ -#define POSIF_MIDR_MODR_Pos \ - (0UL) /*!< POSIF MIDR: MODR (Bit 0) */ -#define POSIF_MIDR_MODR_Msk \ - (0xffUL) /*!< POSIF MIDR: MODR (Bitfield-Mask: 0xff) */ -#define POSIF_MIDR_MODT_Pos \ - (8UL) /*!< POSIF MIDR: MODT (Bit 8) */ -#define POSIF_MIDR_MODT_Msk \ - (0xff00UL) /*!< POSIF MIDR: MODT (Bitfield-Mask: 0xff) */ -#define POSIF_MIDR_MODN_Pos \ - (16UL) /*!< POSIF MIDR: MODN (Bit 16) */ -#define POSIF_MIDR_MODN_Msk \ - (0xffff0000UL) /*!< POSIF MIDR: MODN (Bitfield-Mask: 0xffff) */ - -/* --------------------------------- POSIF_HALP --------------------------------- */ -#define POSIF_HALP_HCP_Pos (0UL) /*!< POSIF HALP: HCP (Bit 0) */ -#define POSIF_HALP_HCP_Msk \ - (0x7UL) /*!< POSIF HALP: HCP (Bitfield-Mask: 0x07) */ -#define POSIF_HALP_HEP_Pos (3UL) /*!< POSIF HALP: HEP (Bit 3) */ -#define POSIF_HALP_HEP_Msk \ - (0x38UL) /*!< POSIF HALP: HEP (Bitfield-Mask: 0x07) */ - -/* --------------------------------- POSIF_HALPS -------------------------------- */ -#define POSIF_HALPS_HCPS_Pos \ - (0UL) /*!< POSIF HALPS: HCPS (Bit 0) */ -#define POSIF_HALPS_HCPS_Msk \ - (0x7UL) /*!< POSIF HALPS: HCPS (Bitfield-Mask: 0x07) */ -#define POSIF_HALPS_HEPS_Pos \ - (3UL) /*!< POSIF HALPS: HEPS (Bit 3) */ -#define POSIF_HALPS_HEPS_Msk \ - (0x38UL) /*!< POSIF HALPS: HEPS (Bitfield-Mask: 0x07) */ - -/* ---------------------------------- POSIF_MCM --------------------------------- */ -#define POSIF_MCM_MCMP_Pos (0UL) /*!< POSIF MCM: MCMP (Bit 0) */ -#define POSIF_MCM_MCMP_Msk \ - (0xffffUL) /*!< POSIF MCM: MCMP (Bitfield-Mask: 0xffff) */ - -/* --------------------------------- POSIF_MCSM --------------------------------- */ -#define POSIF_MCSM_MCMPS_Pos \ - (0UL) /*!< POSIF MCSM: MCMPS (Bit 0) */ -#define POSIF_MCSM_MCMPS_Msk \ - (0xffffUL) /*!< POSIF MCSM: MCMPS (Bitfield-Mask: 0xffff) */ - -/* --------------------------------- POSIF_MCMS --------------------------------- */ -#define POSIF_MCMS_MNPS_Pos \ - (0UL) /*!< POSIF MCMS: MNPS (Bit 0) */ -#define POSIF_MCMS_MNPS_Msk \ - (0x1UL) /*!< POSIF MCMS: MNPS (Bitfield-Mask: 0x01) */ -#define POSIF_MCMS_STHR_Pos \ - (1UL) /*!< POSIF MCMS: STHR (Bit 1) */ -#define POSIF_MCMS_STHR_Msk \ - (0x2UL) /*!< POSIF MCMS: STHR (Bitfield-Mask: 0x01) */ -#define POSIF_MCMS_STMR_Pos \ - (2UL) /*!< POSIF MCMS: STMR (Bit 2) */ -#define POSIF_MCMS_STMR_Msk \ - (0x4UL) /*!< POSIF MCMS: STMR (Bitfield-Mask: 0x01) */ - -/* --------------------------------- POSIF_MCMC --------------------------------- */ -#define POSIF_MCMC_MNPC_Pos \ - (0UL) /*!< POSIF MCMC: MNPC (Bit 0) */ -#define POSIF_MCMC_MNPC_Msk \ - (0x1UL) /*!< POSIF MCMC: MNPC (Bitfield-Mask: 0x01) */ -#define POSIF_MCMC_MPC_Pos (1UL) /*!< POSIF MCMC: MPC (Bit 1) */ -#define POSIF_MCMC_MPC_Msk \ - (0x2UL) /*!< POSIF MCMC: MPC (Bitfield-Mask: 0x01) */ - -/* --------------------------------- POSIF_MCMF --------------------------------- */ -#define POSIF_MCMF_MSS_Pos (0UL) /*!< POSIF MCMF: MSS (Bit 0) */ -#define POSIF_MCMF_MSS_Msk \ - (0x1UL) /*!< POSIF MCMF: MSS (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- POSIF_QDC --------------------------------- */ -#define POSIF_QDC_PALS_Pos (0UL) /*!< POSIF QDC: PALS (Bit 0) */ -#define POSIF_QDC_PALS_Msk \ - (0x1UL) /*!< POSIF QDC: PALS (Bitfield-Mask: 0x01) */ -#define POSIF_QDC_PBLS_Pos (1UL) /*!< POSIF QDC: PBLS (Bit 1) */ -#define POSIF_QDC_PBLS_Msk \ - (0x2UL) /*!< POSIF QDC: PBLS (Bitfield-Mask: 0x01) */ -#define POSIF_QDC_PHS_Pos (2UL) /*!< POSIF QDC: PHS (Bit 2) */ -#define POSIF_QDC_PHS_Msk \ - (0x4UL) /*!< POSIF QDC: PHS (Bitfield-Mask: 0x01) */ -#define POSIF_QDC_ICM_Pos (4UL) /*!< POSIF QDC: ICM (Bit 4) */ -#define POSIF_QDC_ICM_Msk \ - (0x30UL) /*!< POSIF QDC: ICM (Bitfield-Mask: 0x03) */ -#define POSIF_QDC_DVAL_Pos (8UL) /*!< POSIF QDC: DVAL (Bit 8) */ -#define POSIF_QDC_DVAL_Msk \ - (0x100UL) /*!< POSIF QDC: DVAL (Bitfield-Mask: 0x01) */ - -/* --------------------------------- POSIF_PFLG --------------------------------- */ -#define POSIF_PFLG_CHES_Pos \ - (0UL) /*!< POSIF PFLG: CHES (Bit 0) */ -#define POSIF_PFLG_CHES_Msk \ - (0x1UL) /*!< POSIF PFLG: CHES (Bitfield-Mask: 0x01) */ -#define POSIF_PFLG_WHES_Pos \ - (1UL) /*!< POSIF PFLG: WHES (Bit 1) */ -#define POSIF_PFLG_WHES_Msk \ - (0x2UL) /*!< POSIF PFLG: WHES (Bitfield-Mask: 0x01) */ -#define POSIF_PFLG_HIES_Pos \ - (2UL) /*!< POSIF PFLG: HIES (Bit 2) */ -#define POSIF_PFLG_HIES_Msk \ - (0x4UL) /*!< POSIF PFLG: HIES (Bitfield-Mask: 0x01) */ -#define POSIF_PFLG_MSTS_Pos \ - (4UL) /*!< POSIF PFLG: MSTS (Bit 4) */ -#define POSIF_PFLG_MSTS_Msk \ - (0x10UL) /*!< POSIF PFLG: MSTS (Bitfield-Mask: 0x01) */ -#define POSIF_PFLG_INDXS_Pos \ - (8UL) /*!< POSIF PFLG: INDXS (Bit 8) */ -#define POSIF_PFLG_INDXS_Msk \ - (0x100UL) /*!< POSIF PFLG: INDXS (Bitfield-Mask: 0x01) */ -#define POSIF_PFLG_ERRS_Pos \ - (9UL) /*!< POSIF PFLG: ERRS (Bit 9) */ -#define POSIF_PFLG_ERRS_Msk \ - (0x200UL) /*!< POSIF PFLG: ERRS (Bitfield-Mask: 0x01) */ -#define POSIF_PFLG_CNTS_Pos \ - (10UL) /*!< POSIF PFLG: CNTS (Bit 10) */ -#define POSIF_PFLG_CNTS_Msk \ - (0x400UL) /*!< POSIF PFLG: CNTS (Bitfield-Mask: 0x01) */ -#define POSIF_PFLG_DIRS_Pos \ - (11UL) /*!< POSIF PFLG: DIRS (Bit 11) */ -#define POSIF_PFLG_DIRS_Msk \ - (0x800UL) /*!< POSIF PFLG: DIRS (Bitfield-Mask: 0x01) */ -#define POSIF_PFLG_PCLKS_Pos \ - (12UL) /*!< POSIF PFLG: PCLKS (Bit 12) */ -#define POSIF_PFLG_PCLKS_Msk \ - (0x1000UL) /*!< POSIF PFLG: PCLKS (Bitfield-Mask: 0x01) */ - -/* --------------------------------- POSIF_PFLGE -------------------------------- */ -#define POSIF_PFLGE_ECHE_Pos \ - (0UL) /*!< POSIF PFLGE: ECHE (Bit 0) */ -#define POSIF_PFLGE_ECHE_Msk \ - (0x1UL) /*!< POSIF PFLGE: ECHE (Bitfield-Mask: 0x01) */ -#define POSIF_PFLGE_EWHE_Pos \ - (1UL) /*!< POSIF PFLGE: EWHE (Bit 1) */ -#define POSIF_PFLGE_EWHE_Msk \ - (0x2UL) /*!< POSIF PFLGE: EWHE (Bitfield-Mask: 0x01) */ -#define POSIF_PFLGE_EHIE_Pos \ - (2UL) /*!< POSIF PFLGE: EHIE (Bit 2) */ -#define POSIF_PFLGE_EHIE_Msk \ - (0x4UL) /*!< POSIF PFLGE: EHIE (Bitfield-Mask: 0x01) */ -#define POSIF_PFLGE_EMST_Pos \ - (4UL) /*!< POSIF PFLGE: EMST (Bit 4) */ -#define POSIF_PFLGE_EMST_Msk \ - (0x10UL) /*!< POSIF PFLGE: EMST (Bitfield-Mask: 0x01) */ -#define POSIF_PFLGE_EINDX_Pos \ - (8UL) /*!< POSIF PFLGE: EINDX (Bit 8) */ -#define POSIF_PFLGE_EINDX_Msk \ - (0x100UL) /*!< POSIF PFLGE: EINDX (Bitfield-Mask: 0x01) */ -#define POSIF_PFLGE_EERR_Pos \ - (9UL) /*!< POSIF PFLGE: EERR (Bit 9) */ -#define POSIF_PFLGE_EERR_Msk \ - (0x200UL) /*!< POSIF PFLGE: EERR (Bitfield-Mask: 0x01) */ -#define POSIF_PFLGE_ECNT_Pos \ - (10UL) /*!< POSIF PFLGE: ECNT (Bit 10) */ -#define POSIF_PFLGE_ECNT_Msk \ - (0x400UL) /*!< POSIF PFLGE: ECNT (Bitfield-Mask: 0x01) */ -#define POSIF_PFLGE_EDIR_Pos \ - (11UL) /*!< POSIF PFLGE: EDIR (Bit 11) */ -#define POSIF_PFLGE_EDIR_Msk \ - (0x800UL) /*!< POSIF PFLGE: EDIR (Bitfield-Mask: 0x01) */ -#define POSIF_PFLGE_EPCLK_Pos \ - (12UL) /*!< POSIF PFLGE: EPCLK (Bit 12) */ -#define POSIF_PFLGE_EPCLK_Msk \ - (0x1000UL) /*!< POSIF PFLGE: EPCLK (Bitfield-Mask: 0x01) */ -#define POSIF_PFLGE_CHESEL_Pos \ - (16UL) /*!< POSIF PFLGE: CHESEL (Bit 16) */ -#define POSIF_PFLGE_CHESEL_Msk \ - (0x10000UL) /*!< POSIF PFLGE: CHESEL (Bitfield-Mask: 0x01) */ -#define POSIF_PFLGE_WHESEL_Pos \ - (17UL) /*!< POSIF PFLGE: WHESEL (Bit 17) */ -#define POSIF_PFLGE_WHESEL_Msk \ - (0x20000UL) /*!< POSIF PFLGE: WHESEL (Bitfield-Mask: 0x01) */ -#define POSIF_PFLGE_HIESEL_Pos \ - (18UL) /*!< POSIF PFLGE: HIESEL (Bit 18) */ -#define POSIF_PFLGE_HIESEL_Msk \ - (0x40000UL) /*!< POSIF PFLGE: HIESEL (Bitfield-Mask: 0x01) */ -#define POSIF_PFLGE_MSTSEL_Pos \ - (20UL) /*!< POSIF PFLGE: MSTSEL (Bit 20) */ -#define POSIF_PFLGE_MSTSEL_Msk \ - (0x100000UL) /*!< POSIF PFLGE: MSTSEL (Bitfield-Mask: 0x01) */ -#define POSIF_PFLGE_INDSEL_Pos \ - (24UL) /*!< POSIF PFLGE: INDSEL (Bit 24) */ -#define POSIF_PFLGE_INDSEL_Msk \ - (0x1000000UL) /*!< POSIF PFLGE: INDSEL (Bitfield-Mask: 0x01) */ -#define POSIF_PFLGE_ERRSEL_Pos \ - (25UL) /*!< POSIF PFLGE: ERRSEL (Bit 25) */ -#define POSIF_PFLGE_ERRSEL_Msk \ - (0x2000000UL) /*!< POSIF PFLGE: ERRSEL (Bitfield-Mask: 0x01) */ -#define POSIF_PFLGE_CNTSEL_Pos \ - (26UL) /*!< POSIF PFLGE: CNTSEL (Bit 26) */ -#define POSIF_PFLGE_CNTSEL_Msk \ - (0x4000000UL) /*!< POSIF PFLGE: CNTSEL (Bitfield-Mask: 0x01) */ -#define POSIF_PFLGE_DIRSEL_Pos \ - (27UL) /*!< POSIF PFLGE: DIRSEL (Bit 27) */ -#define POSIF_PFLGE_DIRSEL_Msk \ - (0x8000000UL) /*!< POSIF PFLGE: DIRSEL (Bitfield-Mask: 0x01) */ -#define POSIF_PFLGE_PCLSEL_Pos \ - (28UL) /*!< POSIF PFLGE: PCLSEL (Bit 28) */ -#define POSIF_PFLGE_PCLSEL_Msk \ - (0x10000000UL) /*!< POSIF PFLGE: PCLSEL (Bitfield-Mask: 0x01) */ - -/* --------------------------------- POSIF_SPFLG -------------------------------- */ -#define POSIF_SPFLG_SCHE_Pos \ - (0UL) /*!< POSIF SPFLG: SCHE (Bit 0) */ -#define POSIF_SPFLG_SCHE_Msk \ - (0x1UL) /*!< POSIF SPFLG: SCHE (Bitfield-Mask: 0x01) */ -#define POSIF_SPFLG_SWHE_Pos \ - (1UL) /*!< POSIF SPFLG: SWHE (Bit 1) */ -#define POSIF_SPFLG_SWHE_Msk \ - (0x2UL) /*!< POSIF SPFLG: SWHE (Bitfield-Mask: 0x01) */ -#define POSIF_SPFLG_SHIE_Pos \ - (2UL) /*!< POSIF SPFLG: SHIE (Bit 2) */ -#define POSIF_SPFLG_SHIE_Msk \ - (0x4UL) /*!< POSIF SPFLG: SHIE (Bitfield-Mask: 0x01) */ -#define POSIF_SPFLG_SMST_Pos \ - (4UL) /*!< POSIF SPFLG: SMST (Bit 4) */ -#define POSIF_SPFLG_SMST_Msk \ - (0x10UL) /*!< POSIF SPFLG: SMST (Bitfield-Mask: 0x01) */ -#define POSIF_SPFLG_SINDX_Pos \ - (8UL) /*!< POSIF SPFLG: SINDX (Bit 8) */ -#define POSIF_SPFLG_SINDX_Msk \ - (0x100UL) /*!< POSIF SPFLG: SINDX (Bitfield-Mask: 0x01) */ -#define POSIF_SPFLG_SERR_Pos \ - (9UL) /*!< POSIF SPFLG: SERR (Bit 9) */ -#define POSIF_SPFLG_SERR_Msk \ - (0x200UL) /*!< POSIF SPFLG: SERR (Bitfield-Mask: 0x01) */ -#define POSIF_SPFLG_SCNT_Pos \ - (10UL) /*!< POSIF SPFLG: SCNT (Bit 10) */ -#define POSIF_SPFLG_SCNT_Msk \ - (0x400UL) /*!< POSIF SPFLG: SCNT (Bitfield-Mask: 0x01) */ -#define POSIF_SPFLG_SDIR_Pos \ - (11UL) /*!< POSIF SPFLG: SDIR (Bit 11) */ -#define POSIF_SPFLG_SDIR_Msk \ - (0x800UL) /*!< POSIF SPFLG: SDIR (Bitfield-Mask: 0x01) */ -#define POSIF_SPFLG_SPCLK_Pos \ - (12UL) /*!< POSIF SPFLG: SPCLK (Bit 12) */ -#define POSIF_SPFLG_SPCLK_Msk \ - (0x1000UL) /*!< POSIF SPFLG: SPCLK (Bitfield-Mask: 0x01) */ - -/* --------------------------------- POSIF_RPFLG -------------------------------- */ -#define POSIF_RPFLG_RCHE_Pos \ - (0UL) /*!< POSIF RPFLG: RCHE (Bit 0) */ -#define POSIF_RPFLG_RCHE_Msk \ - (0x1UL) /*!< POSIF RPFLG: RCHE (Bitfield-Mask: 0x01) */ -#define POSIF_RPFLG_RWHE_Pos \ - (1UL) /*!< POSIF RPFLG: RWHE (Bit 1) */ -#define POSIF_RPFLG_RWHE_Msk \ - (0x2UL) /*!< POSIF RPFLG: RWHE (Bitfield-Mask: 0x01) */ -#define POSIF_RPFLG_RHIE_Pos \ - (2UL) /*!< POSIF RPFLG: RHIE (Bit 2) */ -#define POSIF_RPFLG_RHIE_Msk \ - (0x4UL) /*!< POSIF RPFLG: RHIE (Bitfield-Mask: 0x01) */ -#define POSIF_RPFLG_RMST_Pos \ - (4UL) /*!< POSIF RPFLG: RMST (Bit 4) */ -#define POSIF_RPFLG_RMST_Msk \ - (0x10UL) /*!< POSIF RPFLG: RMST (Bitfield-Mask: 0x01) */ -#define POSIF_RPFLG_RINDX_Pos \ - (8UL) /*!< POSIF RPFLG: RINDX (Bit 8) */ -#define POSIF_RPFLG_RINDX_Msk \ - (0x100UL) /*!< POSIF RPFLG: RINDX (Bitfield-Mask: 0x01) */ -#define POSIF_RPFLG_RERR_Pos \ - (9UL) /*!< POSIF RPFLG: RERR (Bit 9) */ -#define POSIF_RPFLG_RERR_Msk \ - (0x200UL) /*!< POSIF RPFLG: RERR (Bitfield-Mask: 0x01) */ -#define POSIF_RPFLG_RCNT_Pos \ - (10UL) /*!< POSIF RPFLG: RCNT (Bit 10) */ -#define POSIF_RPFLG_RCNT_Msk \ - (0x400UL) /*!< POSIF RPFLG: RCNT (Bitfield-Mask: 0x01) */ -#define POSIF_RPFLG_RDIR_Pos \ - (11UL) /*!< POSIF RPFLG: RDIR (Bit 11) */ -#define POSIF_RPFLG_RDIR_Msk \ - (0x800UL) /*!< POSIF RPFLG: RDIR (Bitfield-Mask: 0x01) */ -#define POSIF_RPFLG_RPCLK_Pos \ - (12UL) /*!< POSIF RPFLG: RPCLK (Bit 12) */ -#define POSIF_RPFLG_RPCLK_Msk \ - (0x1000UL) /*!< POSIF RPFLG: RPCLK (Bitfield-Mask: 0x01) */ - -/* --------------------------------- POSIF_PDBG --------------------------------- */ -#define POSIF_PDBG_QCSV_Pos \ - (0UL) /*!< POSIF PDBG: QCSV (Bit 0) */ -#define POSIF_PDBG_QCSV_Msk \ - (0x3UL) /*!< POSIF PDBG: QCSV (Bitfield-Mask: 0x03) */ -#define POSIF_PDBG_QPSV_Pos \ - (2UL) /*!< POSIF PDBG: QPSV (Bit 2) */ -#define POSIF_PDBG_QPSV_Msk \ - (0xcUL) /*!< POSIF PDBG: QPSV (Bitfield-Mask: 0x03) */ -#define POSIF_PDBG_IVAL_Pos \ - (4UL) /*!< POSIF PDBG: IVAL (Bit 4) */ -#define POSIF_PDBG_IVAL_Msk \ - (0x10UL) /*!< POSIF PDBG: IVAL (Bitfield-Mask: 0x01) */ -#define POSIF_PDBG_HSP_Pos (5UL) /*!< POSIF PDBG: HSP (Bit 5) */ -#define POSIF_PDBG_HSP_Msk \ - (0xe0UL) /*!< POSIF PDBG: HSP (Bitfield-Mask: 0x07) */ -#define POSIF_PDBG_LPP0_Pos \ - (8UL) /*!< POSIF PDBG: LPP0 (Bit 8) */ -#define POSIF_PDBG_LPP0_Msk \ - (0x3f00UL) /*!< POSIF PDBG: LPP0 (Bitfield-Mask: 0x3f) */ -#define POSIF_PDBG_LPP1_Pos \ - (16UL) /*!< POSIF PDBG: LPP1 (Bit 16) */ -#define POSIF_PDBG_LPP1_Msk \ - (0x3f0000UL) /*!< POSIF PDBG: LPP1 (Bitfield-Mask: 0x3f) */ -#define POSIF_PDBG_LPP2_Pos \ - (22UL) /*!< POSIF PDBG: LPP2 (Bit 22) */ -#define POSIF_PDBG_LPP2_Msk \ - (0xfc00000UL) /*!< POSIF PDBG: LPP2 (Bitfield-Mask: 0x3f) */ - -/* ================================================================================ */ -/* ================ struct 'PORT0' Position & Mask ================ */ -/* ================================================================================ */ - -/* ---------------------------------- PORT0_OUT --------------------------------- */ -#define PORT0_OUT_P0_Pos (0UL) /*!< PORT0 OUT: P0 (Bit 0) */ -#define PORT0_OUT_P0_Msk (0x1UL) /*!< PORT0 OUT: P0 (Bitfield-Mask: 0x01) */ -#define PORT0_OUT_P1_Pos (1UL) /*!< PORT0 OUT: P1 (Bit 1) */ -#define PORT0_OUT_P1_Msk (0x2UL) /*!< PORT0 OUT: P1 (Bitfield-Mask: 0x01) */ -#define PORT0_OUT_P2_Pos (2UL) /*!< PORT0 OUT: P2 (Bit 2) */ -#define PORT0_OUT_P2_Msk (0x4UL) /*!< PORT0 OUT: P2 (Bitfield-Mask: 0x01) */ -#define PORT0_OUT_P3_Pos (3UL) /*!< PORT0 OUT: P3 (Bit 3) */ -#define PORT0_OUT_P3_Msk (0x8UL) /*!< PORT0 OUT: P3 (Bitfield-Mask: 0x01) */ -#define PORT0_OUT_P4_Pos (4UL) /*!< PORT0 OUT: P4 (Bit 4) */ -#define PORT0_OUT_P4_Msk \ - (0x10UL) /*!< PORT0 OUT: P4 (Bitfield-Mask: 0x01) */ -#define PORT0_OUT_P5_Pos (5UL) /*!< PORT0 OUT: P5 (Bit 5) */ -#define PORT0_OUT_P5_Msk \ - (0x20UL) /*!< PORT0 OUT: P5 (Bitfield-Mask: 0x01) */ -#define PORT0_OUT_P6_Pos (6UL) /*!< PORT0 OUT: P6 (Bit 6) */ -#define PORT0_OUT_P6_Msk \ - (0x40UL) /*!< PORT0 OUT: P6 (Bitfield-Mask: 0x01) */ -#define PORT0_OUT_P7_Pos (7UL) /*!< PORT0 OUT: P7 (Bit 7) */ -#define PORT0_OUT_P7_Msk \ - (0x80UL) /*!< PORT0 OUT: P7 (Bitfield-Mask: 0x01) */ -#define PORT0_OUT_P8_Pos (8UL) /*!< PORT0 OUT: P8 (Bit 8) */ -#define PORT0_OUT_P8_Msk \ - (0x100UL) /*!< PORT0 OUT: P8 (Bitfield-Mask: 0x01) */ -#define PORT0_OUT_P9_Pos (9UL) /*!< PORT0 OUT: P9 (Bit 9) */ -#define PORT0_OUT_P9_Msk \ - (0x200UL) /*!< PORT0 OUT: P9 (Bitfield-Mask: 0x01) */ -#define PORT0_OUT_P10_Pos (10UL) /*!< PORT0 OUT: P10 (Bit 10) */ -#define PORT0_OUT_P10_Msk \ - (0x400UL) /*!< PORT0 OUT: P10 (Bitfield-Mask: 0x01) */ -#define PORT0_OUT_P11_Pos (11UL) /*!< PORT0 OUT: P11 (Bit 11) */ -#define PORT0_OUT_P11_Msk \ - (0x800UL) /*!< PORT0 OUT: P11 (Bitfield-Mask: 0x01) */ -#define PORT0_OUT_P12_Pos (12UL) /*!< PORT0 OUT: P12 (Bit 12) */ -#define PORT0_OUT_P12_Msk \ - (0x1000UL) /*!< PORT0 OUT: P12 (Bitfield-Mask: 0x01) */ -#define PORT0_OUT_P13_Pos (13UL) /*!< PORT0 OUT: P13 (Bit 13) */ -#define PORT0_OUT_P13_Msk \ - (0x2000UL) /*!< PORT0 OUT: P13 (Bitfield-Mask: 0x01) */ -#define PORT0_OUT_P14_Pos (14UL) /*!< PORT0 OUT: P14 (Bit 14) */ -#define PORT0_OUT_P14_Msk \ - (0x4000UL) /*!< PORT0 OUT: P14 (Bitfield-Mask: 0x01) */ -#define PORT0_OUT_P15_Pos (15UL) /*!< PORT0 OUT: P15 (Bit 15) */ -#define PORT0_OUT_P15_Msk \ - (0x8000UL) /*!< PORT0 OUT: P15 (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- PORT0_OMR --------------------------------- */ -#define PORT0_OMR_PS0_Pos (0UL) /*!< PORT0 OMR: PS0 (Bit 0) */ -#define PORT0_OMR_PS0_Msk \ - (0x1UL) /*!< PORT0 OMR: PS0 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PS1_Pos (1UL) /*!< PORT0 OMR: PS1 (Bit 1) */ -#define PORT0_OMR_PS1_Msk \ - (0x2UL) /*!< PORT0 OMR: PS1 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PS2_Pos (2UL) /*!< PORT0 OMR: PS2 (Bit 2) */ -#define PORT0_OMR_PS2_Msk \ - (0x4UL) /*!< PORT0 OMR: PS2 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PS3_Pos (3UL) /*!< PORT0 OMR: PS3 (Bit 3) */ -#define PORT0_OMR_PS3_Msk \ - (0x8UL) /*!< PORT0 OMR: PS3 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PS4_Pos (4UL) /*!< PORT0 OMR: PS4 (Bit 4) */ -#define PORT0_OMR_PS4_Msk \ - (0x10UL) /*!< PORT0 OMR: PS4 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PS5_Pos (5UL) /*!< PORT0 OMR: PS5 (Bit 5) */ -#define PORT0_OMR_PS5_Msk \ - (0x20UL) /*!< PORT0 OMR: PS5 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PS6_Pos (6UL) /*!< PORT0 OMR: PS6 (Bit 6) */ -#define PORT0_OMR_PS6_Msk \ - (0x40UL) /*!< PORT0 OMR: PS6 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PS7_Pos (7UL) /*!< PORT0 OMR: PS7 (Bit 7) */ -#define PORT0_OMR_PS7_Msk \ - (0x80UL) /*!< PORT0 OMR: PS7 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PS8_Pos (8UL) /*!< PORT0 OMR: PS8 (Bit 8) */ -#define PORT0_OMR_PS8_Msk \ - (0x100UL) /*!< PORT0 OMR: PS8 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PS9_Pos (9UL) /*!< PORT0 OMR: PS9 (Bit 9) */ -#define PORT0_OMR_PS9_Msk \ - (0x200UL) /*!< PORT0 OMR: PS9 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PS10_Pos \ - (10UL) /*!< PORT0 OMR: PS10 (Bit 10) */ -#define PORT0_OMR_PS10_Msk \ - (0x400UL) /*!< PORT0 OMR: PS10 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PS11_Pos \ - (11UL) /*!< PORT0 OMR: PS11 (Bit 11) */ -#define PORT0_OMR_PS11_Msk \ - (0x800UL) /*!< PORT0 OMR: PS11 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PS12_Pos \ - (12UL) /*!< PORT0 OMR: PS12 (Bit 12) */ -#define PORT0_OMR_PS12_Msk \ - (0x1000UL) /*!< PORT0 OMR: PS12 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PS13_Pos \ - (13UL) /*!< PORT0 OMR: PS13 (Bit 13) */ -#define PORT0_OMR_PS13_Msk \ - (0x2000UL) /*!< PORT0 OMR: PS13 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PS14_Pos \ - (14UL) /*!< PORT0 OMR: PS14 (Bit 14) */ -#define PORT0_OMR_PS14_Msk \ - (0x4000UL) /*!< PORT0 OMR: PS14 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PS15_Pos \ - (15UL) /*!< PORT0 OMR: PS15 (Bit 15) */ -#define PORT0_OMR_PS15_Msk \ - (0x8000UL) /*!< PORT0 OMR: PS15 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PR0_Pos (16UL) /*!< PORT0 OMR: PR0 (Bit 16) */ -#define PORT0_OMR_PR0_Msk \ - (0x10000UL) /*!< PORT0 OMR: PR0 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PR1_Pos (17UL) /*!< PORT0 OMR: PR1 (Bit 17) */ -#define PORT0_OMR_PR1_Msk \ - (0x20000UL) /*!< PORT0 OMR: PR1 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PR2_Pos (18UL) /*!< PORT0 OMR: PR2 (Bit 18) */ -#define PORT0_OMR_PR2_Msk \ - (0x40000UL) /*!< PORT0 OMR: PR2 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PR3_Pos (19UL) /*!< PORT0 OMR: PR3 (Bit 19) */ -#define PORT0_OMR_PR3_Msk \ - (0x80000UL) /*!< PORT0 OMR: PR3 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PR4_Pos (20UL) /*!< PORT0 OMR: PR4 (Bit 20) */ -#define PORT0_OMR_PR4_Msk \ - (0x100000UL) /*!< PORT0 OMR: PR4 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PR5_Pos (21UL) /*!< PORT0 OMR: PR5 (Bit 21) */ -#define PORT0_OMR_PR5_Msk \ - (0x200000UL) /*!< PORT0 OMR: PR5 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PR6_Pos (22UL) /*!< PORT0 OMR: PR6 (Bit 22) */ -#define PORT0_OMR_PR6_Msk \ - (0x400000UL) /*!< PORT0 OMR: PR6 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PR7_Pos (23UL) /*!< PORT0 OMR: PR7 (Bit 23) */ -#define PORT0_OMR_PR7_Msk \ - (0x800000UL) /*!< PORT0 OMR: PR7 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PR8_Pos (24UL) /*!< PORT0 OMR: PR8 (Bit 24) */ -#define PORT0_OMR_PR8_Msk \ - (0x1000000UL) /*!< PORT0 OMR: PR8 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PR9_Pos (25UL) /*!< PORT0 OMR: PR9 (Bit 25) */ -#define PORT0_OMR_PR9_Msk \ - (0x2000000UL) /*!< PORT0 OMR: PR9 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PR10_Pos \ - (26UL) /*!< PORT0 OMR: PR10 (Bit 26) */ -#define PORT0_OMR_PR10_Msk \ - (0x4000000UL) /*!< PORT0 OMR: PR10 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PR11_Pos \ - (27UL) /*!< PORT0 OMR: PR11 (Bit 27) */ -#define PORT0_OMR_PR11_Msk \ - (0x8000000UL) /*!< PORT0 OMR: PR11 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PR12_Pos \ - (28UL) /*!< PORT0 OMR: PR12 (Bit 28) */ -#define PORT0_OMR_PR12_Msk \ - (0x10000000UL) /*!< PORT0 OMR: PR12 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PR13_Pos \ - (29UL) /*!< PORT0 OMR: PR13 (Bit 29) */ -#define PORT0_OMR_PR13_Msk \ - (0x20000000UL) /*!< PORT0 OMR: PR13 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PR14_Pos \ - (30UL) /*!< PORT0 OMR: PR14 (Bit 30) */ -#define PORT0_OMR_PR14_Msk \ - (0x40000000UL) /*!< PORT0 OMR: PR14 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PR15_Pos \ - (31UL) /*!< PORT0 OMR: PR15 (Bit 31) */ -#define PORT0_OMR_PR15_Msk \ - (0x80000000UL) /*!< PORT0 OMR: PR15 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- PORT0_IOCR0 -------------------------------- */ -#define PORT0_IOCR0_PC0_Pos \ - (3UL) /*!< PORT0 IOCR0: PC0 (Bit 3) */ -#define PORT0_IOCR0_PC0_Msk \ - (0xf8UL) /*!< PORT0 IOCR0: PC0 (Bitfield-Mask: 0x1f) */ -#define PORT0_IOCR0_PC1_Pos \ - (11UL) /*!< PORT0 IOCR0: PC1 (Bit 11) */ -#define PORT0_IOCR0_PC1_Msk \ - (0xf800UL) /*!< PORT0 IOCR0: PC1 (Bitfield-Mask: 0x1f) */ -#define PORT0_IOCR0_PC2_Pos \ - (19UL) /*!< PORT0 IOCR0: PC2 (Bit 19) */ -#define PORT0_IOCR0_PC2_Msk \ - (0xf80000UL) /*!< PORT0 IOCR0: PC2 (Bitfield-Mask: 0x1f) */ -#define PORT0_IOCR0_PC3_Pos \ - (27UL) /*!< PORT0 IOCR0: PC3 (Bit 27) */ -#define PORT0_IOCR0_PC3_Msk \ - (0xf8000000UL) /*!< PORT0 IOCR0: PC3 (Bitfield-Mask: 0x1f) */ - -/* --------------------------------- PORT0_IOCR4 -------------------------------- */ -#define PORT0_IOCR4_PC4_Pos \ - (3UL) /*!< PORT0 IOCR4: PC4 (Bit 3) */ -#define PORT0_IOCR4_PC4_Msk \ - (0xf8UL) /*!< PORT0 IOCR4: PC4 (Bitfield-Mask: 0x1f) */ -#define PORT0_IOCR4_PC5_Pos \ - (11UL) /*!< PORT0 IOCR4: PC5 (Bit 11) */ -#define PORT0_IOCR4_PC5_Msk \ - (0xf800UL) /*!< PORT0 IOCR4: PC5 (Bitfield-Mask: 0x1f) */ -#define PORT0_IOCR4_PC6_Pos \ - (19UL) /*!< PORT0 IOCR4: PC6 (Bit 19) */ -#define PORT0_IOCR4_PC6_Msk \ - (0xf80000UL) /*!< PORT0 IOCR4: PC6 (Bitfield-Mask: 0x1f) */ -#define PORT0_IOCR4_PC7_Pos \ - (27UL) /*!< PORT0 IOCR4: PC7 (Bit 27) */ -#define PORT0_IOCR4_PC7_Msk \ - (0xf8000000UL) /*!< PORT0 IOCR4: PC7 (Bitfield-Mask: 0x1f) */ - -/* --------------------------------- PORT0_IOCR8 -------------------------------- */ -#define PORT0_IOCR8_PC8_Pos \ - (3UL) /*!< PORT0 IOCR8: PC8 (Bit 3) */ -#define PORT0_IOCR8_PC8_Msk \ - (0xf8UL) /*!< PORT0 IOCR8: PC8 (Bitfield-Mask: 0x1f) */ -#define PORT0_IOCR8_PC9_Pos \ - (11UL) /*!< PORT0 IOCR8: PC9 (Bit 11) */ -#define PORT0_IOCR8_PC9_Msk \ - (0xf800UL) /*!< PORT0 IOCR8: PC9 (Bitfield-Mask: 0x1f) */ -#define PORT0_IOCR8_PC10_Pos \ - (19UL) /*!< PORT0 IOCR8: PC10 (Bit 19) */ -#define PORT0_IOCR8_PC10_Msk \ - (0xf80000UL) /*!< PORT0 IOCR8: PC10 (Bitfield-Mask: 0x1f) */ -#define PORT0_IOCR8_PC11_Pos \ - (27UL) /*!< PORT0 IOCR8: PC11 (Bit 27) */ -#define PORT0_IOCR8_PC11_Msk \ - (0xf8000000UL) /*!< PORT0 IOCR8: PC11 (Bitfield-Mask: 0x1f) */ - -/* ---------------------------------- PORT0_IN ---------------------------------- */ -#define PORT0_IN_P0_Pos (0UL) /*!< PORT0 IN: P0 (Bit 0) */ -#define PORT0_IN_P0_Msk (0x1UL) /*!< PORT0 IN: P0 (Bitfield-Mask: 0x01) */ -#define PORT0_IN_P1_Pos (1UL) /*!< PORT0 IN: P1 (Bit 1) */ -#define PORT0_IN_P1_Msk (0x2UL) /*!< PORT0 IN: P1 (Bitfield-Mask: 0x01) */ -#define PORT0_IN_P2_Pos (2UL) /*!< PORT0 IN: P2 (Bit 2) */ -#define PORT0_IN_P2_Msk (0x4UL) /*!< PORT0 IN: P2 (Bitfield-Mask: 0x01) */ -#define PORT0_IN_P3_Pos (3UL) /*!< PORT0 IN: P3 (Bit 3) */ -#define PORT0_IN_P3_Msk (0x8UL) /*!< PORT0 IN: P3 (Bitfield-Mask: 0x01) */ -#define PORT0_IN_P4_Pos (4UL) /*!< PORT0 IN: P4 (Bit 4) */ -#define PORT0_IN_P4_Msk (0x10UL) /*!< PORT0 IN: P4 (Bitfield-Mask: 0x01) */ -#define PORT0_IN_P5_Pos (5UL) /*!< PORT0 IN: P5 (Bit 5) */ -#define PORT0_IN_P5_Msk (0x20UL) /*!< PORT0 IN: P5 (Bitfield-Mask: 0x01) */ -#define PORT0_IN_P6_Pos (6UL) /*!< PORT0 IN: P6 (Bit 6) */ -#define PORT0_IN_P6_Msk (0x40UL) /*!< PORT0 IN: P6 (Bitfield-Mask: 0x01) */ -#define PORT0_IN_P7_Pos (7UL) /*!< PORT0 IN: P7 (Bit 7) */ -#define PORT0_IN_P7_Msk (0x80UL) /*!< PORT0 IN: P7 (Bitfield-Mask: 0x01) */ -#define PORT0_IN_P8_Pos (8UL) /*!< PORT0 IN: P8 (Bit 8) */ -#define PORT0_IN_P8_Msk \ - (0x100UL) /*!< PORT0 IN: P8 (Bitfield-Mask: 0x01) */ -#define PORT0_IN_P9_Pos (9UL) /*!< PORT0 IN: P9 (Bit 9) */ -#define PORT0_IN_P9_Msk \ - (0x200UL) /*!< PORT0 IN: P9 (Bitfield-Mask: 0x01) */ -#define PORT0_IN_P10_Pos (10UL) /*!< PORT0 IN: P10 (Bit 10) */ -#define PORT0_IN_P10_Msk \ - (0x400UL) /*!< PORT0 IN: P10 (Bitfield-Mask: 0x01) */ -#define PORT0_IN_P11_Pos (11UL) /*!< PORT0 IN: P11 (Bit 11) */ -#define PORT0_IN_P11_Msk \ - (0x800UL) /*!< PORT0 IN: P11 (Bitfield-Mask: 0x01) */ -#define PORT0_IN_P12_Pos (12UL) /*!< PORT0 IN: P12 (Bit 12) */ -#define PORT0_IN_P12_Msk \ - (0x1000UL) /*!< PORT0 IN: P12 (Bitfield-Mask: 0x01) */ -#define PORT0_IN_P13_Pos (13UL) /*!< PORT0 IN: P13 (Bit 13) */ -#define PORT0_IN_P13_Msk \ - (0x2000UL) /*!< PORT0 IN: P13 (Bitfield-Mask: 0x01) */ -#define PORT0_IN_P14_Pos (14UL) /*!< PORT0 IN: P14 (Bit 14) */ -#define PORT0_IN_P14_Msk \ - (0x4000UL) /*!< PORT0 IN: P14 (Bitfield-Mask: 0x01) */ -#define PORT0_IN_P15_Pos (15UL) /*!< PORT0 IN: P15 (Bit 15) */ -#define PORT0_IN_P15_Msk \ - (0x8000UL) /*!< PORT0 IN: P15 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- PORT0_PDR0 --------------------------------- */ -#define PORT0_PDR0_PD0_Pos (0UL) /*!< PORT0 PDR0: PD0 (Bit 0) */ -#define PORT0_PDR0_PD0_Msk \ - (0x7UL) /*!< PORT0 PDR0: PD0 (Bitfield-Mask: 0x07) */ -#define PORT0_PDR0_PD1_Pos (4UL) /*!< PORT0 PDR0: PD1 (Bit 4) */ -#define PORT0_PDR0_PD1_Msk \ - (0x70UL) /*!< PORT0 PDR0: PD1 (Bitfield-Mask: 0x07) */ -#define PORT0_PDR0_PD2_Pos (8UL) /*!< PORT0 PDR0: PD2 (Bit 8) */ -#define PORT0_PDR0_PD2_Msk \ - (0x700UL) /*!< PORT0 PDR0: PD2 (Bitfield-Mask: 0x07) */ -#define PORT0_PDR0_PD3_Pos \ - (12UL) /*!< PORT0 PDR0: PD3 (Bit 12) */ -#define PORT0_PDR0_PD3_Msk \ - (0x7000UL) /*!< PORT0 PDR0: PD3 (Bitfield-Mask: 0x07) */ -#define PORT0_PDR0_PD4_Pos \ - (16UL) /*!< PORT0 PDR0: PD4 (Bit 16) */ -#define PORT0_PDR0_PD4_Msk \ - (0x70000UL) /*!< PORT0 PDR0: PD4 (Bitfield-Mask: 0x07) */ -#define PORT0_PDR0_PD5_Pos \ - (20UL) /*!< PORT0 PDR0: PD5 (Bit 20) */ -#define PORT0_PDR0_PD5_Msk \ - (0x700000UL) /*!< PORT0 PDR0: PD5 (Bitfield-Mask: 0x07) */ -#define PORT0_PDR0_PD6_Pos \ - (24UL) /*!< PORT0 PDR0: PD6 (Bit 24) */ -#define PORT0_PDR0_PD6_Msk \ - (0x7000000UL) /*!< PORT0 PDR0: PD6 (Bitfield-Mask: 0x07) */ -#define PORT0_PDR0_PD7_Pos \ - (28UL) /*!< PORT0 PDR0: PD7 (Bit 28) */ -#define PORT0_PDR0_PD7_Msk \ - (0x70000000UL) /*!< PORT0 PDR0: PD7 (Bitfield-Mask: 0x07) */ - -/* --------------------------------- PORT0_PDR1 --------------------------------- */ -#define PORT0_PDR1_PD8_Pos (0UL) /*!< PORT0 PDR1: PD8 (Bit 0) */ -#define PORT0_PDR1_PD8_Msk \ - (0x7UL) /*!< PORT0 PDR1: PD8 (Bitfield-Mask: 0x07) */ -#define PORT0_PDR1_PD9_Pos (4UL) /*!< PORT0 PDR1: PD9 (Bit 4) */ -#define PORT0_PDR1_PD9_Msk \ - (0x70UL) /*!< PORT0 PDR1: PD9 (Bitfield-Mask: 0x07) */ -#define PORT0_PDR1_PD10_Pos \ - (8UL) /*!< PORT0 PDR1: PD10 (Bit 8) */ -#define PORT0_PDR1_PD10_Msk \ - (0x700UL) /*!< PORT0 PDR1: PD10 (Bitfield-Mask: 0x07) */ -#define PORT0_PDR1_PD11_Pos \ - (12UL) /*!< PORT0 PDR1: PD11 (Bit 12) */ -#define PORT0_PDR1_PD11_Msk \ - (0x7000UL) /*!< PORT0 PDR1: PD11 (Bitfield-Mask: 0x07) */ -#define PORT0_PDR1_PD12_Pos \ - (16UL) /*!< PORT0 PDR1: PD12 (Bit 16) */ -#define PORT0_PDR1_PD12_Msk \ - (0x70000UL) /*!< PORT0 PDR1: PD12 (Bitfield-Mask: 0x07) */ -#define PORT0_PDR1_PD13_Pos \ - (20UL) /*!< PORT0 PDR1: PD13 (Bit 20) */ -#define PORT0_PDR1_PD13_Msk \ - (0x700000UL) /*!< PORT0 PDR1: PD13 (Bitfield-Mask: 0x07) */ -#define PORT0_PDR1_PD14_Pos \ - (24UL) /*!< PORT0 PDR1: PD14 (Bit 24) */ -#define PORT0_PDR1_PD14_Msk \ - (0x7000000UL) /*!< PORT0 PDR1: PD14 (Bitfield-Mask: 0x07) */ -#define PORT0_PDR1_PD15_Pos \ - (28UL) /*!< PORT0 PDR1: PD15 (Bit 28) */ -#define PORT0_PDR1_PD15_Msk \ - (0x70000000UL) /*!< PORT0 PDR1: PD15 (Bitfield-Mask: 0x07) */ - -/* --------------------------------- PORT0_PDISC -------------------------------- */ -#define PORT0_PDISC_PDIS0_Pos \ - (0UL) /*!< PORT0 PDISC: PDIS0 (Bit 0) */ -#define PORT0_PDISC_PDIS0_Msk \ - (0x1UL) /*!< PORT0 PDISC: PDIS0 (Bitfield-Mask: 0x01) */ -#define PORT0_PDISC_PDIS1_Pos \ - (1UL) /*!< PORT0 PDISC: PDIS1 (Bit 1) */ -#define PORT0_PDISC_PDIS1_Msk \ - (0x2UL) /*!< PORT0 PDISC: PDIS1 (Bitfield-Mask: 0x01) */ -#define PORT0_PDISC_PDIS2_Pos \ - (2UL) /*!< PORT0 PDISC: PDIS2 (Bit 2) */ -#define PORT0_PDISC_PDIS2_Msk \ - (0x4UL) /*!< PORT0 PDISC: PDIS2 (Bitfield-Mask: 0x01) */ -#define PORT0_PDISC_PDIS3_Pos \ - (3UL) /*!< PORT0 PDISC: PDIS3 (Bit 3) */ -#define PORT0_PDISC_PDIS3_Msk \ - (0x8UL) /*!< PORT0 PDISC: PDIS3 (Bitfield-Mask: 0x01) */ -#define PORT0_PDISC_PDIS4_Pos \ - (4UL) /*!< PORT0 PDISC: PDIS4 (Bit 4) */ -#define PORT0_PDISC_PDIS4_Msk \ - (0x10UL) /*!< PORT0 PDISC: PDIS4 (Bitfield-Mask: 0x01) */ -#define PORT0_PDISC_PDIS5_Pos \ - (5UL) /*!< PORT0 PDISC: PDIS5 (Bit 5) */ -#define PORT0_PDISC_PDIS5_Msk \ - (0x20UL) /*!< PORT0 PDISC: PDIS5 (Bitfield-Mask: 0x01) */ -#define PORT0_PDISC_PDIS6_Pos \ - (6UL) /*!< PORT0 PDISC: PDIS6 (Bit 6) */ -#define PORT0_PDISC_PDIS6_Msk \ - (0x40UL) /*!< PORT0 PDISC: PDIS6 (Bitfield-Mask: 0x01) */ -#define PORT0_PDISC_PDIS7_Pos \ - (7UL) /*!< PORT0 PDISC: PDIS7 (Bit 7) */ -#define PORT0_PDISC_PDIS7_Msk \ - (0x80UL) /*!< PORT0 PDISC: PDIS7 (Bitfield-Mask: 0x01) */ -#define PORT0_PDISC_PDIS8_Pos \ - (8UL) /*!< PORT0 PDISC: PDIS8 (Bit 8) */ -#define PORT0_PDISC_PDIS8_Msk \ - (0x100UL) /*!< PORT0 PDISC: PDIS8 (Bitfield-Mask: 0x01) */ -#define PORT0_PDISC_PDIS9_Pos \ - (9UL) /*!< PORT0 PDISC: PDIS9 (Bit 9) */ -#define PORT0_PDISC_PDIS9_Msk \ - (0x200UL) /*!< PORT0 PDISC: PDIS9 (Bitfield-Mask: 0x01) */ -#define PORT0_PDISC_PDIS10_Pos \ - (10UL) /*!< PORT0 PDISC: PDIS10 (Bit 10) */ -#define PORT0_PDISC_PDIS10_Msk \ - (0x400UL) /*!< PORT0 PDISC: PDIS10 (Bitfield-Mask: 0x01) */ -#define PORT0_PDISC_PDIS11_Pos \ - (11UL) /*!< PORT0 PDISC: PDIS11 (Bit 11) */ -#define PORT0_PDISC_PDIS11_Msk \ - (0x800UL) /*!< PORT0 PDISC: PDIS11 (Bitfield-Mask: 0x01) */ -#define PORT0_PDISC_PDIS12_Pos \ - (12UL) /*!< PORT0 PDISC: PDIS12 (Bit 12) */ -#define PORT0_PDISC_PDIS12_Msk \ - (0x1000UL) /*!< PORT0 PDISC: PDIS12 (Bitfield-Mask: 0x01) */ -#define PORT0_PDISC_PDIS13_Pos \ - (13UL) /*!< PORT0 PDISC: PDIS13 (Bit 13) */ -#define PORT0_PDISC_PDIS13_Msk \ - (0x2000UL) /*!< PORT0 PDISC: PDIS13 (Bitfield-Mask: 0x01) */ -#define PORT0_PDISC_PDIS14_Pos \ - (14UL) /*!< PORT0 PDISC: PDIS14 (Bit 14) */ -#define PORT0_PDISC_PDIS14_Msk \ - (0x4000UL) /*!< PORT0 PDISC: PDIS14 (Bitfield-Mask: 0x01) */ -#define PORT0_PDISC_PDIS15_Pos \ - (15UL) /*!< PORT0 PDISC: PDIS15 (Bit 15) */ -#define PORT0_PDISC_PDIS15_Msk \ - (0x8000UL) /*!< PORT0 PDISC: PDIS15 (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- PORT0_PPS --------------------------------- */ -#define PORT0_PPS_PPS0_Pos (0UL) /*!< PORT0 PPS: PPS0 (Bit 0) */ -#define PORT0_PPS_PPS0_Msk \ - (0x1UL) /*!< PORT0 PPS: PPS0 (Bitfield-Mask: 0x01) */ -#define PORT0_PPS_PPS1_Pos (1UL) /*!< PORT0 PPS: PPS1 (Bit 1) */ -#define PORT0_PPS_PPS1_Msk \ - (0x2UL) /*!< PORT0 PPS: PPS1 (Bitfield-Mask: 0x01) */ -#define PORT0_PPS_PPS2_Pos (2UL) /*!< PORT0 PPS: PPS2 (Bit 2) */ -#define PORT0_PPS_PPS2_Msk \ - (0x4UL) /*!< PORT0 PPS: PPS2 (Bitfield-Mask: 0x01) */ -#define PORT0_PPS_PPS3_Pos (3UL) /*!< PORT0 PPS: PPS3 (Bit 3) */ -#define PORT0_PPS_PPS3_Msk \ - (0x8UL) /*!< PORT0 PPS: PPS3 (Bitfield-Mask: 0x01) */ -#define PORT0_PPS_PPS4_Pos (4UL) /*!< PORT0 PPS: PPS4 (Bit 4) */ -#define PORT0_PPS_PPS4_Msk \ - (0x10UL) /*!< PORT0 PPS: PPS4 (Bitfield-Mask: 0x01) */ -#define PORT0_PPS_PPS5_Pos (5UL) /*!< PORT0 PPS: PPS5 (Bit 5) */ -#define PORT0_PPS_PPS5_Msk \ - (0x20UL) /*!< PORT0 PPS: PPS5 (Bitfield-Mask: 0x01) */ -#define PORT0_PPS_PPS6_Pos (6UL) /*!< PORT0 PPS: PPS6 (Bit 6) */ -#define PORT0_PPS_PPS6_Msk \ - (0x40UL) /*!< PORT0 PPS: PPS6 (Bitfield-Mask: 0x01) */ -#define PORT0_PPS_PPS7_Pos (7UL) /*!< PORT0 PPS: PPS7 (Bit 7) */ -#define PORT0_PPS_PPS7_Msk \ - (0x80UL) /*!< PORT0 PPS: PPS7 (Bitfield-Mask: 0x01) */ -#define PORT0_PPS_PPS8_Pos (8UL) /*!< PORT0 PPS: PPS8 (Bit 8) */ -#define PORT0_PPS_PPS8_Msk \ - (0x100UL) /*!< PORT0 PPS: PPS8 (Bitfield-Mask: 0x01) */ -#define PORT0_PPS_PPS9_Pos (9UL) /*!< PORT0 PPS: PPS9 (Bit 9) */ -#define PORT0_PPS_PPS9_Msk \ - (0x200UL) /*!< PORT0 PPS: PPS9 (Bitfield-Mask: 0x01) */ -#define PORT0_PPS_PPS10_Pos \ - (10UL) /*!< PORT0 PPS: PPS10 (Bit 10) */ -#define PORT0_PPS_PPS10_Msk \ - (0x400UL) /*!< PORT0 PPS: PPS10 (Bitfield-Mask: 0x01) */ -#define PORT0_PPS_PPS11_Pos \ - (11UL) /*!< PORT0 PPS: PPS11 (Bit 11) */ -#define PORT0_PPS_PPS11_Msk \ - (0x800UL) /*!< PORT0 PPS: PPS11 (Bitfield-Mask: 0x01) */ -#define PORT0_PPS_PPS12_Pos \ - (12UL) /*!< PORT0 PPS: PPS12 (Bit 12) */ -#define PORT0_PPS_PPS12_Msk \ - (0x1000UL) /*!< PORT0 PPS: PPS12 (Bitfield-Mask: 0x01) */ -#define PORT0_PPS_PPS13_Pos \ - (13UL) /*!< PORT0 PPS: PPS13 (Bit 13) */ -#define PORT0_PPS_PPS13_Msk \ - (0x2000UL) /*!< PORT0 PPS: PPS13 (Bitfield-Mask: 0x01) */ -#define PORT0_PPS_PPS14_Pos \ - (14UL) /*!< PORT0 PPS: PPS14 (Bit 14) */ -#define PORT0_PPS_PPS14_Msk \ - (0x4000UL) /*!< PORT0 PPS: PPS14 (Bitfield-Mask: 0x01) */ -#define PORT0_PPS_PPS15_Pos \ - (15UL) /*!< PORT0 PPS: PPS15 (Bit 15) */ -#define PORT0_PPS_PPS15_Msk \ - (0x8000UL) /*!< PORT0 PPS: PPS15 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- PORT0_HWSEL -------------------------------- */ -#define PORT0_HWSEL_HW0_Pos \ - (0UL) /*!< PORT0 HWSEL: HW0 (Bit 0) */ -#define PORT0_HWSEL_HW0_Msk \ - (0x3UL) /*!< PORT0 HWSEL: HW0 (Bitfield-Mask: 0x03) */ -#define PORT0_HWSEL_HW1_Pos \ - (2UL) /*!< PORT0 HWSEL: HW1 (Bit 2) */ -#define PORT0_HWSEL_HW1_Msk \ - (0xcUL) /*!< PORT0 HWSEL: HW1 (Bitfield-Mask: 0x03) */ -#define PORT0_HWSEL_HW2_Pos \ - (4UL) /*!< PORT0 HWSEL: HW2 (Bit 4) */ -#define PORT0_HWSEL_HW2_Msk \ - (0x30UL) /*!< PORT0 HWSEL: HW2 (Bitfield-Mask: 0x03) */ -#define PORT0_HWSEL_HW3_Pos \ - (6UL) /*!< PORT0 HWSEL: HW3 (Bit 6) */ -#define PORT0_HWSEL_HW3_Msk \ - (0xc0UL) /*!< PORT0 HWSEL: HW3 (Bitfield-Mask: 0x03) */ -#define PORT0_HWSEL_HW4_Pos \ - (8UL) /*!< PORT0 HWSEL: HW4 (Bit 8) */ -#define PORT0_HWSEL_HW4_Msk \ - (0x300UL) /*!< PORT0 HWSEL: HW4 (Bitfield-Mask: 0x03) */ -#define PORT0_HWSEL_HW5_Pos \ - (10UL) /*!< PORT0 HWSEL: HW5 (Bit 10) */ -#define PORT0_HWSEL_HW5_Msk \ - (0xc00UL) /*!< PORT0 HWSEL: HW5 (Bitfield-Mask: 0x03) */ -#define PORT0_HWSEL_HW6_Pos \ - (12UL) /*!< PORT0 HWSEL: HW6 (Bit 12) */ -#define PORT0_HWSEL_HW6_Msk \ - (0x3000UL) /*!< PORT0 HWSEL: HW6 (Bitfield-Mask: 0x03) */ -#define PORT0_HWSEL_HW7_Pos \ - (14UL) /*!< PORT0 HWSEL: HW7 (Bit 14) */ -#define PORT0_HWSEL_HW7_Msk \ - (0xc000UL) /*!< PORT0 HWSEL: HW7 (Bitfield-Mask: 0x03) */ -#define PORT0_HWSEL_HW8_Pos \ - (16UL) /*!< PORT0 HWSEL: HW8 (Bit 16) */ -#define PORT0_HWSEL_HW8_Msk \ - (0x30000UL) /*!< PORT0 HWSEL: HW8 (Bitfield-Mask: 0x03) */ -#define PORT0_HWSEL_HW9_Pos \ - (18UL) /*!< PORT0 HWSEL: HW9 (Bit 18) */ -#define PORT0_HWSEL_HW9_Msk \ - (0xc0000UL) /*!< PORT0 HWSEL: HW9 (Bitfield-Mask: 0x03) */ -#define PORT0_HWSEL_HW10_Pos \ - (20UL) /*!< PORT0 HWSEL: HW10 (Bit 20) */ -#define PORT0_HWSEL_HW10_Msk \ - (0x300000UL) /*!< PORT0 HWSEL: HW10 (Bitfield-Mask: 0x03) */ -#define PORT0_HWSEL_HW11_Pos \ - (22UL) /*!< PORT0 HWSEL: HW11 (Bit 22) */ -#define PORT0_HWSEL_HW11_Msk \ - (0xc00000UL) /*!< PORT0 HWSEL: HW11 (Bitfield-Mask: 0x03) */ -#define PORT0_HWSEL_HW12_Pos \ - (24UL) /*!< PORT0 HWSEL: HW12 (Bit 24) */ -#define PORT0_HWSEL_HW12_Msk \ - (0x3000000UL) /*!< PORT0 HWSEL: HW12 (Bitfield-Mask: 0x03) */ -#define PORT0_HWSEL_HW13_Pos \ - (26UL) /*!< PORT0 HWSEL: HW13 (Bit 26) */ -#define PORT0_HWSEL_HW13_Msk \ - (0xc000000UL) /*!< PORT0 HWSEL: HW13 (Bitfield-Mask: 0x03) */ -#define PORT0_HWSEL_HW14_Pos \ - (28UL) /*!< PORT0 HWSEL: HW14 (Bit 28) */ -#define PORT0_HWSEL_HW14_Msk \ - (0x30000000UL) /*!< PORT0 HWSEL: HW14 (Bitfield-Mask: 0x03) */ -#define PORT0_HWSEL_HW15_Pos \ - (30UL) /*!< PORT0 HWSEL: HW15 (Bit 30) */ -#define PORT0_HWSEL_HW15_Msk \ - (0xc0000000UL) /*!< PORT0 HWSEL: HW15 (Bitfield-Mask: 0x03) */ - -/* ================================================================================ */ -/* ================ struct 'PORT1' Position & Mask ================ */ -/* ================================================================================ */ - -/* ---------------------------------- PORT1_OUT --------------------------------- */ -#define PORT1_OUT_P0_Pos (0UL) /*!< PORT1 OUT: P0 (Bit 0) */ -#define PORT1_OUT_P0_Msk (0x1UL) /*!< PORT1 OUT: P0 (Bitfield-Mask: 0x01) */ -#define PORT1_OUT_P1_Pos (1UL) /*!< PORT1 OUT: P1 (Bit 1) */ -#define PORT1_OUT_P1_Msk (0x2UL) /*!< PORT1 OUT: P1 (Bitfield-Mask: 0x01) */ -#define PORT1_OUT_P2_Pos (2UL) /*!< PORT1 OUT: P2 (Bit 2) */ -#define PORT1_OUT_P2_Msk (0x4UL) /*!< PORT1 OUT: P2 (Bitfield-Mask: 0x01) */ -#define PORT1_OUT_P3_Pos (3UL) /*!< PORT1 OUT: P3 (Bit 3) */ -#define PORT1_OUT_P3_Msk (0x8UL) /*!< PORT1 OUT: P3 (Bitfield-Mask: 0x01) */ -#define PORT1_OUT_P4_Pos (4UL) /*!< PORT1 OUT: P4 (Bit 4) */ -#define PORT1_OUT_P4_Msk \ - (0x10UL) /*!< PORT1 OUT: P4 (Bitfield-Mask: 0x01) */ -#define PORT1_OUT_P5_Pos (5UL) /*!< PORT1 OUT: P5 (Bit 5) */ -#define PORT1_OUT_P5_Msk \ - (0x20UL) /*!< PORT1 OUT: P5 (Bitfield-Mask: 0x01) */ -#define PORT1_OUT_P6_Pos (6UL) /*!< PORT1 OUT: P6 (Bit 6) */ -#define PORT1_OUT_P6_Msk \ - (0x40UL) /*!< PORT1 OUT: P6 (Bitfield-Mask: 0x01) */ -#define PORT1_OUT_P7_Pos (7UL) /*!< PORT1 OUT: P7 (Bit 7) */ -#define PORT1_OUT_P7_Msk \ - (0x80UL) /*!< PORT1 OUT: P7 (Bitfield-Mask: 0x01) */ -#define PORT1_OUT_P8_Pos (8UL) /*!< PORT1 OUT: P8 (Bit 8) */ -#define PORT1_OUT_P8_Msk \ - (0x100UL) /*!< PORT1 OUT: P8 (Bitfield-Mask: 0x01) */ -#define PORT1_OUT_P9_Pos (9UL) /*!< PORT1 OUT: P9 (Bit 9) */ -#define PORT1_OUT_P9_Msk \ - (0x200UL) /*!< PORT1 OUT: P9 (Bitfield-Mask: 0x01) */ -#define PORT1_OUT_P10_Pos (10UL) /*!< PORT1 OUT: P10 (Bit 10) */ -#define PORT1_OUT_P10_Msk \ - (0x400UL) /*!< PORT1 OUT: P10 (Bitfield-Mask: 0x01) */ -#define PORT1_OUT_P11_Pos (11UL) /*!< PORT1 OUT: P11 (Bit 11) */ -#define PORT1_OUT_P11_Msk \ - (0x800UL) /*!< PORT1 OUT: P11 (Bitfield-Mask: 0x01) */ -#define PORT1_OUT_P12_Pos (12UL) /*!< PORT1 OUT: P12 (Bit 12) */ -#define PORT1_OUT_P12_Msk \ - (0x1000UL) /*!< PORT1 OUT: P12 (Bitfield-Mask: 0x01) */ -#define PORT1_OUT_P13_Pos (13UL) /*!< PORT1 OUT: P13 (Bit 13) */ -#define PORT1_OUT_P13_Msk \ - (0x2000UL) /*!< PORT1 OUT: P13 (Bitfield-Mask: 0x01) */ -#define PORT1_OUT_P14_Pos (14UL) /*!< PORT1 OUT: P14 (Bit 14) */ -#define PORT1_OUT_P14_Msk \ - (0x4000UL) /*!< PORT1 OUT: P14 (Bitfield-Mask: 0x01) */ -#define PORT1_OUT_P15_Pos (15UL) /*!< PORT1 OUT: P15 (Bit 15) */ -#define PORT1_OUT_P15_Msk \ - (0x8000UL) /*!< PORT1 OUT: P15 (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- PORT1_OMR --------------------------------- */ -#define PORT1_OMR_PS0_Pos (0UL) /*!< PORT1 OMR: PS0 (Bit 0) */ -#define PORT1_OMR_PS0_Msk \ - (0x1UL) /*!< PORT1 OMR: PS0 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PS1_Pos (1UL) /*!< PORT1 OMR: PS1 (Bit 1) */ -#define PORT1_OMR_PS1_Msk \ - (0x2UL) /*!< PORT1 OMR: PS1 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PS2_Pos (2UL) /*!< PORT1 OMR: PS2 (Bit 2) */ -#define PORT1_OMR_PS2_Msk \ - (0x4UL) /*!< PORT1 OMR: PS2 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PS3_Pos (3UL) /*!< PORT1 OMR: PS3 (Bit 3) */ -#define PORT1_OMR_PS3_Msk \ - (0x8UL) /*!< PORT1 OMR: PS3 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PS4_Pos (4UL) /*!< PORT1 OMR: PS4 (Bit 4) */ -#define PORT1_OMR_PS4_Msk \ - (0x10UL) /*!< PORT1 OMR: PS4 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PS5_Pos (5UL) /*!< PORT1 OMR: PS5 (Bit 5) */ -#define PORT1_OMR_PS5_Msk \ - (0x20UL) /*!< PORT1 OMR: PS5 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PS6_Pos (6UL) /*!< PORT1 OMR: PS6 (Bit 6) */ -#define PORT1_OMR_PS6_Msk \ - (0x40UL) /*!< PORT1 OMR: PS6 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PS7_Pos (7UL) /*!< PORT1 OMR: PS7 (Bit 7) */ -#define PORT1_OMR_PS7_Msk \ - (0x80UL) /*!< PORT1 OMR: PS7 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PS8_Pos (8UL) /*!< PORT1 OMR: PS8 (Bit 8) */ -#define PORT1_OMR_PS8_Msk \ - (0x100UL) /*!< PORT1 OMR: PS8 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PS9_Pos (9UL) /*!< PORT1 OMR: PS9 (Bit 9) */ -#define PORT1_OMR_PS9_Msk \ - (0x200UL) /*!< PORT1 OMR: PS9 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PS10_Pos \ - (10UL) /*!< PORT1 OMR: PS10 (Bit 10) */ -#define PORT1_OMR_PS10_Msk \ - (0x400UL) /*!< PORT1 OMR: PS10 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PS11_Pos \ - (11UL) /*!< PORT1 OMR: PS11 (Bit 11) */ -#define PORT1_OMR_PS11_Msk \ - (0x800UL) /*!< PORT1 OMR: PS11 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PS12_Pos \ - (12UL) /*!< PORT1 OMR: PS12 (Bit 12) */ -#define PORT1_OMR_PS12_Msk \ - (0x1000UL) /*!< PORT1 OMR: PS12 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PS13_Pos \ - (13UL) /*!< PORT1 OMR: PS13 (Bit 13) */ -#define PORT1_OMR_PS13_Msk \ - (0x2000UL) /*!< PORT1 OMR: PS13 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PS14_Pos \ - (14UL) /*!< PORT1 OMR: PS14 (Bit 14) */ -#define PORT1_OMR_PS14_Msk \ - (0x4000UL) /*!< PORT1 OMR: PS14 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PS15_Pos \ - (15UL) /*!< PORT1 OMR: PS15 (Bit 15) */ -#define PORT1_OMR_PS15_Msk \ - (0x8000UL) /*!< PORT1 OMR: PS15 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PR0_Pos (16UL) /*!< PORT1 OMR: PR0 (Bit 16) */ -#define PORT1_OMR_PR0_Msk \ - (0x10000UL) /*!< PORT1 OMR: PR0 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PR1_Pos (17UL) /*!< PORT1 OMR: PR1 (Bit 17) */ -#define PORT1_OMR_PR1_Msk \ - (0x20000UL) /*!< PORT1 OMR: PR1 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PR2_Pos (18UL) /*!< PORT1 OMR: PR2 (Bit 18) */ -#define PORT1_OMR_PR2_Msk \ - (0x40000UL) /*!< PORT1 OMR: PR2 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PR3_Pos (19UL) /*!< PORT1 OMR: PR3 (Bit 19) */ -#define PORT1_OMR_PR3_Msk \ - (0x80000UL) /*!< PORT1 OMR: PR3 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PR4_Pos (20UL) /*!< PORT1 OMR: PR4 (Bit 20) */ -#define PORT1_OMR_PR4_Msk \ - (0x100000UL) /*!< PORT1 OMR: PR4 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PR5_Pos (21UL) /*!< PORT1 OMR: PR5 (Bit 21) */ -#define PORT1_OMR_PR5_Msk \ - (0x200000UL) /*!< PORT1 OMR: PR5 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PR6_Pos (22UL) /*!< PORT1 OMR: PR6 (Bit 22) */ -#define PORT1_OMR_PR6_Msk \ - (0x400000UL) /*!< PORT1 OMR: PR6 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PR7_Pos (23UL) /*!< PORT1 OMR: PR7 (Bit 23) */ -#define PORT1_OMR_PR7_Msk \ - (0x800000UL) /*!< PORT1 OMR: PR7 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PR8_Pos (24UL) /*!< PORT1 OMR: PR8 (Bit 24) */ -#define PORT1_OMR_PR8_Msk \ - (0x1000000UL) /*!< PORT1 OMR: PR8 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PR9_Pos (25UL) /*!< PORT1 OMR: PR9 (Bit 25) */ -#define PORT1_OMR_PR9_Msk \ - (0x2000000UL) /*!< PORT1 OMR: PR9 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PR10_Pos \ - (26UL) /*!< PORT1 OMR: PR10 (Bit 26) */ -#define PORT1_OMR_PR10_Msk \ - (0x4000000UL) /*!< PORT1 OMR: PR10 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PR11_Pos \ - (27UL) /*!< PORT1 OMR: PR11 (Bit 27) */ -#define PORT1_OMR_PR11_Msk \ - (0x8000000UL) /*!< PORT1 OMR: PR11 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PR12_Pos \ - (28UL) /*!< PORT1 OMR: PR12 (Bit 28) */ -#define PORT1_OMR_PR12_Msk \ - (0x10000000UL) /*!< PORT1 OMR: PR12 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PR13_Pos \ - (29UL) /*!< PORT1 OMR: PR13 (Bit 29) */ -#define PORT1_OMR_PR13_Msk \ - (0x20000000UL) /*!< PORT1 OMR: PR13 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PR14_Pos \ - (30UL) /*!< PORT1 OMR: PR14 (Bit 30) */ -#define PORT1_OMR_PR14_Msk \ - (0x40000000UL) /*!< PORT1 OMR: PR14 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PR15_Pos \ - (31UL) /*!< PORT1 OMR: PR15 (Bit 31) */ -#define PORT1_OMR_PR15_Msk \ - (0x80000000UL) /*!< PORT1 OMR: PR15 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- PORT1_IOCR0 -------------------------------- */ -#define PORT1_IOCR0_PC0_Pos \ - (3UL) /*!< PORT1 IOCR0: PC0 (Bit 3) */ -#define PORT1_IOCR0_PC0_Msk \ - (0xf8UL) /*!< PORT1 IOCR0: PC0 (Bitfield-Mask: 0x1f) */ -#define PORT1_IOCR0_PC1_Pos \ - (11UL) /*!< PORT1 IOCR0: PC1 (Bit 11) */ -#define PORT1_IOCR0_PC1_Msk \ - (0xf800UL) /*!< PORT1 IOCR0: PC1 (Bitfield-Mask: 0x1f) */ -#define PORT1_IOCR0_PC2_Pos \ - (19UL) /*!< PORT1 IOCR0: PC2 (Bit 19) */ -#define PORT1_IOCR0_PC2_Msk \ - (0xf80000UL) /*!< PORT1 IOCR0: PC2 (Bitfield-Mask: 0x1f) */ -#define PORT1_IOCR0_PC3_Pos \ - (27UL) /*!< PORT1 IOCR0: PC3 (Bit 27) */ -#define PORT1_IOCR0_PC3_Msk \ - (0xf8000000UL) /*!< PORT1 IOCR0: PC3 (Bitfield-Mask: 0x1f) */ - -/* --------------------------------- PORT1_IOCR4 -------------------------------- */ -#define PORT1_IOCR4_PC4_Pos \ - (3UL) /*!< PORT1 IOCR4: PC4 (Bit 3) */ -#define PORT1_IOCR4_PC4_Msk \ - (0xf8UL) /*!< PORT1 IOCR4: PC4 (Bitfield-Mask: 0x1f) */ -#define PORT1_IOCR4_PC5_Pos \ - (11UL) /*!< PORT1 IOCR4: PC5 (Bit 11) */ -#define PORT1_IOCR4_PC5_Msk \ - (0xf800UL) /*!< PORT1 IOCR4: PC5 (Bitfield-Mask: 0x1f) */ -#define PORT1_IOCR4_PC6_Pos \ - (19UL) /*!< PORT1 IOCR4: PC6 (Bit 19) */ -#define PORT1_IOCR4_PC6_Msk \ - (0xf80000UL) /*!< PORT1 IOCR4: PC6 (Bitfield-Mask: 0x1f) */ -#define PORT1_IOCR4_PC7_Pos \ - (27UL) /*!< PORT1 IOCR4: PC7 (Bit 27) */ -#define PORT1_IOCR4_PC7_Msk \ - (0xf8000000UL) /*!< PORT1 IOCR4: PC7 (Bitfield-Mask: 0x1f) */ - -/* --------------------------------- PORT1_IOCR8 -------------------------------- */ -#define PORT1_IOCR8_PC8_Pos \ - (3UL) /*!< PORT1 IOCR8: PC8 (Bit 3) */ -#define PORT1_IOCR8_PC8_Msk \ - (0xf8UL) /*!< PORT1 IOCR8: PC8 (Bitfield-Mask: 0x1f) */ -#define PORT1_IOCR8_PC9_Pos \ - (11UL) /*!< PORT1 IOCR8: PC9 (Bit 11) */ -#define PORT1_IOCR8_PC9_Msk \ - (0xf800UL) /*!< PORT1 IOCR8: PC9 (Bitfield-Mask: 0x1f) */ -#define PORT1_IOCR8_PC10_Pos \ - (19UL) /*!< PORT1 IOCR8: PC10 (Bit 19) */ -#define PORT1_IOCR8_PC10_Msk \ - (0xf80000UL) /*!< PORT1 IOCR8: PC10 (Bitfield-Mask: 0x1f) */ -#define PORT1_IOCR8_PC11_Pos \ - (27UL) /*!< PORT1 IOCR8: PC11 (Bit 27) */ -#define PORT1_IOCR8_PC11_Msk \ - (0xf8000000UL) /*!< PORT1 IOCR8: PC11 (Bitfield-Mask: 0x1f) */ - -/* -------------------------------- PORT1_IOCR12 -------------------------------- */ -#define PORT1_IOCR12_PC12_Pos \ - (3UL) /*!< PORT1 IOCR12: PC12 (Bit 3) */ -#define PORT1_IOCR12_PC12_Msk \ - (0xf8UL) /*!< PORT1 IOCR12: PC12 (Bitfield-Mask: 0x1f) */ -#define PORT1_IOCR12_PC13_Pos \ - (11UL) /*!< PORT1 IOCR12: PC13 (Bit 11) */ -#define PORT1_IOCR12_PC13_Msk \ - (0xf800UL) /*!< PORT1 IOCR12: PC13 (Bitfield-Mask: 0x1f) */ -#define PORT1_IOCR12_PC14_Pos \ - (19UL) /*!< PORT1 IOCR12: PC14 (Bit 19) */ -#define PORT1_IOCR12_PC14_Msk \ - (0xf80000UL) /*!< PORT1 IOCR12: PC14 (Bitfield-Mask: 0x1f) */ -#define PORT1_IOCR12_PC15_Pos \ - (27UL) /*!< PORT1 IOCR12: PC15 (Bit 27) */ -#define PORT1_IOCR12_PC15_Msk \ - (0xf8000000UL) /*!< PORT1 IOCR12: PC15 (Bitfield-Mask: 0x1f) */ - -/* ---------------------------------- PORT1_IN ---------------------------------- */ -#define PORT1_IN_P0_Pos (0UL) /*!< PORT1 IN: P0 (Bit 0) */ -#define PORT1_IN_P0_Msk (0x1UL) /*!< PORT1 IN: P0 (Bitfield-Mask: 0x01) */ -#define PORT1_IN_P1_Pos (1UL) /*!< PORT1 IN: P1 (Bit 1) */ -#define PORT1_IN_P1_Msk (0x2UL) /*!< PORT1 IN: P1 (Bitfield-Mask: 0x01) */ -#define PORT1_IN_P2_Pos (2UL) /*!< PORT1 IN: P2 (Bit 2) */ -#define PORT1_IN_P2_Msk (0x4UL) /*!< PORT1 IN: P2 (Bitfield-Mask: 0x01) */ -#define PORT1_IN_P3_Pos (3UL) /*!< PORT1 IN: P3 (Bit 3) */ -#define PORT1_IN_P3_Msk (0x8UL) /*!< PORT1 IN: P3 (Bitfield-Mask: 0x01) */ -#define PORT1_IN_P4_Pos (4UL) /*!< PORT1 IN: P4 (Bit 4) */ -#define PORT1_IN_P4_Msk (0x10UL) /*!< PORT1 IN: P4 (Bitfield-Mask: 0x01) */ -#define PORT1_IN_P5_Pos (5UL) /*!< PORT1 IN: P5 (Bit 5) */ -#define PORT1_IN_P5_Msk (0x20UL) /*!< PORT1 IN: P5 (Bitfield-Mask: 0x01) */ -#define PORT1_IN_P6_Pos (6UL) /*!< PORT1 IN: P6 (Bit 6) */ -#define PORT1_IN_P6_Msk (0x40UL) /*!< PORT1 IN: P6 (Bitfield-Mask: 0x01) */ -#define PORT1_IN_P7_Pos (7UL) /*!< PORT1 IN: P7 (Bit 7) */ -#define PORT1_IN_P7_Msk (0x80UL) /*!< PORT1 IN: P7 (Bitfield-Mask: 0x01) */ -#define PORT1_IN_P8_Pos (8UL) /*!< PORT1 IN: P8 (Bit 8) */ -#define PORT1_IN_P8_Msk \ - (0x100UL) /*!< PORT1 IN: P8 (Bitfield-Mask: 0x01) */ -#define PORT1_IN_P9_Pos (9UL) /*!< PORT1 IN: P9 (Bit 9) */ -#define PORT1_IN_P9_Msk \ - (0x200UL) /*!< PORT1 IN: P9 (Bitfield-Mask: 0x01) */ -#define PORT1_IN_P10_Pos (10UL) /*!< PORT1 IN: P10 (Bit 10) */ -#define PORT1_IN_P10_Msk \ - (0x400UL) /*!< PORT1 IN: P10 (Bitfield-Mask: 0x01) */ -#define PORT1_IN_P11_Pos (11UL) /*!< PORT1 IN: P11 (Bit 11) */ -#define PORT1_IN_P11_Msk \ - (0x800UL) /*!< PORT1 IN: P11 (Bitfield-Mask: 0x01) */ -#define PORT1_IN_P12_Pos (12UL) /*!< PORT1 IN: P12 (Bit 12) */ -#define PORT1_IN_P12_Msk \ - (0x1000UL) /*!< PORT1 IN: P12 (Bitfield-Mask: 0x01) */ -#define PORT1_IN_P13_Pos (13UL) /*!< PORT1 IN: P13 (Bit 13) */ -#define PORT1_IN_P13_Msk \ - (0x2000UL) /*!< PORT1 IN: P13 (Bitfield-Mask: 0x01) */ -#define PORT1_IN_P14_Pos (14UL) /*!< PORT1 IN: P14 (Bit 14) */ -#define PORT1_IN_P14_Msk \ - (0x4000UL) /*!< PORT1 IN: P14 (Bitfield-Mask: 0x01) */ -#define PORT1_IN_P15_Pos (15UL) /*!< PORT1 IN: P15 (Bit 15) */ -#define PORT1_IN_P15_Msk \ - (0x8000UL) /*!< PORT1 IN: P15 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- PORT1_PDR0 --------------------------------- */ -#define PORT1_PDR0_PD0_Pos (0UL) /*!< PORT1 PDR0: PD0 (Bit 0) */ -#define PORT1_PDR0_PD0_Msk \ - (0x7UL) /*!< PORT1 PDR0: PD0 (Bitfield-Mask: 0x07) */ -#define PORT1_PDR0_PD1_Pos (4UL) /*!< PORT1 PDR0: PD1 (Bit 4) */ -#define PORT1_PDR0_PD1_Msk \ - (0x70UL) /*!< PORT1 PDR0: PD1 (Bitfield-Mask: 0x07) */ -#define PORT1_PDR0_PD2_Pos (8UL) /*!< PORT1 PDR0: PD2 (Bit 8) */ -#define PORT1_PDR0_PD2_Msk \ - (0x700UL) /*!< PORT1 PDR0: PD2 (Bitfield-Mask: 0x07) */ -#define PORT1_PDR0_PD3_Pos \ - (12UL) /*!< PORT1 PDR0: PD3 (Bit 12) */ -#define PORT1_PDR0_PD3_Msk \ - (0x7000UL) /*!< PORT1 PDR0: PD3 (Bitfield-Mask: 0x07) */ -#define PORT1_PDR0_PD4_Pos \ - (16UL) /*!< PORT1 PDR0: PD4 (Bit 16) */ -#define PORT1_PDR0_PD4_Msk \ - (0x70000UL) /*!< PORT1 PDR0: PD4 (Bitfield-Mask: 0x07) */ -#define PORT1_PDR0_PD5_Pos \ - (20UL) /*!< PORT1 PDR0: PD5 (Bit 20) */ -#define PORT1_PDR0_PD5_Msk \ - (0x700000UL) /*!< PORT1 PDR0: PD5 (Bitfield-Mask: 0x07) */ -#define PORT1_PDR0_PD6_Pos \ - (24UL) /*!< PORT1 PDR0: PD6 (Bit 24) */ -#define PORT1_PDR0_PD6_Msk \ - (0x7000000UL) /*!< PORT1 PDR0: PD6 (Bitfield-Mask: 0x07) */ -#define PORT1_PDR0_PD7_Pos \ - (28UL) /*!< PORT1 PDR0: PD7 (Bit 28) */ -#define PORT1_PDR0_PD7_Msk \ - (0x70000000UL) /*!< PORT1 PDR0: PD7 (Bitfield-Mask: 0x07) */ - -/* --------------------------------- PORT1_PDR1 --------------------------------- */ -#define PORT1_PDR1_PD8_Pos (0UL) /*!< PORT1 PDR1: PD8 (Bit 0) */ -#define PORT1_PDR1_PD8_Msk \ - (0x7UL) /*!< PORT1 PDR1: PD8 (Bitfield-Mask: 0x07) */ -#define PORT1_PDR1_PD9_Pos (4UL) /*!< PORT1 PDR1: PD9 (Bit 4) */ -#define PORT1_PDR1_PD9_Msk \ - (0x70UL) /*!< PORT1 PDR1: PD9 (Bitfield-Mask: 0x07) */ -#define PORT1_PDR1_PD10_Pos \ - (8UL) /*!< PORT1 PDR1: PD10 (Bit 8) */ -#define PORT1_PDR1_PD10_Msk \ - (0x700UL) /*!< PORT1 PDR1: PD10 (Bitfield-Mask: 0x07) */ -#define PORT1_PDR1_PD11_Pos \ - (12UL) /*!< PORT1 PDR1: PD11 (Bit 12) */ -#define PORT1_PDR1_PD11_Msk \ - (0x7000UL) /*!< PORT1 PDR1: PD11 (Bitfield-Mask: 0x07) */ -#define PORT1_PDR1_PD12_Pos \ - (16UL) /*!< PORT1 PDR1: PD12 (Bit 16) */ -#define PORT1_PDR1_PD12_Msk \ - (0x70000UL) /*!< PORT1 PDR1: PD12 (Bitfield-Mask: 0x07) */ -#define PORT1_PDR1_PD13_Pos \ - (20UL) /*!< PORT1 PDR1: PD13 (Bit 20) */ -#define PORT1_PDR1_PD13_Msk \ - (0x700000UL) /*!< PORT1 PDR1: PD13 (Bitfield-Mask: 0x07) */ -#define PORT1_PDR1_PD14_Pos \ - (24UL) /*!< PORT1 PDR1: PD14 (Bit 24) */ -#define PORT1_PDR1_PD14_Msk \ - (0x7000000UL) /*!< PORT1 PDR1: PD14 (Bitfield-Mask: 0x07) */ -#define PORT1_PDR1_PD15_Pos \ - (28UL) /*!< PORT1 PDR1: PD15 (Bit 28) */ -#define PORT1_PDR1_PD15_Msk \ - (0x70000000UL) /*!< PORT1 PDR1: PD15 (Bitfield-Mask: 0x07) */ - -/* --------------------------------- PORT1_PDISC -------------------------------- */ -#define PORT1_PDISC_PDIS0_Pos \ - (0UL) /*!< PORT1 PDISC: PDIS0 (Bit 0) */ -#define PORT1_PDISC_PDIS0_Msk \ - (0x1UL) /*!< PORT1 PDISC: PDIS0 (Bitfield-Mask: 0x01) */ -#define PORT1_PDISC_PDIS1_Pos \ - (1UL) /*!< PORT1 PDISC: PDIS1 (Bit 1) */ -#define PORT1_PDISC_PDIS1_Msk \ - (0x2UL) /*!< PORT1 PDISC: PDIS1 (Bitfield-Mask: 0x01) */ -#define PORT1_PDISC_PDIS2_Pos \ - (2UL) /*!< PORT1 PDISC: PDIS2 (Bit 2) */ -#define PORT1_PDISC_PDIS2_Msk \ - (0x4UL) /*!< PORT1 PDISC: PDIS2 (Bitfield-Mask: 0x01) */ -#define PORT1_PDISC_PDIS3_Pos \ - (3UL) /*!< PORT1 PDISC: PDIS3 (Bit 3) */ -#define PORT1_PDISC_PDIS3_Msk \ - (0x8UL) /*!< PORT1 PDISC: PDIS3 (Bitfield-Mask: 0x01) */ -#define PORT1_PDISC_PDIS4_Pos \ - (4UL) /*!< PORT1 PDISC: PDIS4 (Bit 4) */ -#define PORT1_PDISC_PDIS4_Msk \ - (0x10UL) /*!< PORT1 PDISC: PDIS4 (Bitfield-Mask: 0x01) */ -#define PORT1_PDISC_PDIS5_Pos \ - (5UL) /*!< PORT1 PDISC: PDIS5 (Bit 5) */ -#define PORT1_PDISC_PDIS5_Msk \ - (0x20UL) /*!< PORT1 PDISC: PDIS5 (Bitfield-Mask: 0x01) */ -#define PORT1_PDISC_PDIS6_Pos \ - (6UL) /*!< PORT1 PDISC: PDIS6 (Bit 6) */ -#define PORT1_PDISC_PDIS6_Msk \ - (0x40UL) /*!< PORT1 PDISC: PDIS6 (Bitfield-Mask: 0x01) */ -#define PORT1_PDISC_PDIS7_Pos \ - (7UL) /*!< PORT1 PDISC: PDIS7 (Bit 7) */ -#define PORT1_PDISC_PDIS7_Msk \ - (0x80UL) /*!< PORT1 PDISC: PDIS7 (Bitfield-Mask: 0x01) */ -#define PORT1_PDISC_PDIS8_Pos \ - (8UL) /*!< PORT1 PDISC: PDIS8 (Bit 8) */ -#define PORT1_PDISC_PDIS8_Msk \ - (0x100UL) /*!< PORT1 PDISC: PDIS8 (Bitfield-Mask: 0x01) */ -#define PORT1_PDISC_PDIS9_Pos \ - (9UL) /*!< PORT1 PDISC: PDIS9 (Bit 9) */ -#define PORT1_PDISC_PDIS9_Msk \ - (0x200UL) /*!< PORT1 PDISC: PDIS9 (Bitfield-Mask: 0x01) */ -#define PORT1_PDISC_PDIS10_Pos \ - (10UL) /*!< PORT1 PDISC: PDIS10 (Bit 10) */ -#define PORT1_PDISC_PDIS10_Msk \ - (0x400UL) /*!< PORT1 PDISC: PDIS10 (Bitfield-Mask: 0x01) */ -#define PORT1_PDISC_PDIS11_Pos \ - (11UL) /*!< PORT1 PDISC: PDIS11 (Bit 11) */ -#define PORT1_PDISC_PDIS11_Msk \ - (0x800UL) /*!< PORT1 PDISC: PDIS11 (Bitfield-Mask: 0x01) */ -#define PORT1_PDISC_PDIS12_Pos \ - (12UL) /*!< PORT1 PDISC: PDIS12 (Bit 12) */ -#define PORT1_PDISC_PDIS12_Msk \ - (0x1000UL) /*!< PORT1 PDISC: PDIS12 (Bitfield-Mask: 0x01) */ -#define PORT1_PDISC_PDIS13_Pos \ - (13UL) /*!< PORT1 PDISC: PDIS13 (Bit 13) */ -#define PORT1_PDISC_PDIS13_Msk \ - (0x2000UL) /*!< PORT1 PDISC: PDIS13 (Bitfield-Mask: 0x01) */ -#define PORT1_PDISC_PDIS14_Pos \ - (14UL) /*!< PORT1 PDISC: PDIS14 (Bit 14) */ -#define PORT1_PDISC_PDIS14_Msk \ - (0x4000UL) /*!< PORT1 PDISC: PDIS14 (Bitfield-Mask: 0x01) */ -#define PORT1_PDISC_PDIS15_Pos \ - (15UL) /*!< PORT1 PDISC: PDIS15 (Bit 15) */ -#define PORT1_PDISC_PDIS15_Msk \ - (0x8000UL) /*!< PORT1 PDISC: PDIS15 (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- PORT1_PPS --------------------------------- */ -#define PORT1_PPS_PPS0_Pos (0UL) /*!< PORT1 PPS: PPS0 (Bit 0) */ -#define PORT1_PPS_PPS0_Msk \ - (0x1UL) /*!< PORT1 PPS: PPS0 (Bitfield-Mask: 0x01) */ -#define PORT1_PPS_PPS1_Pos (1UL) /*!< PORT1 PPS: PPS1 (Bit 1) */ -#define PORT1_PPS_PPS1_Msk \ - (0x2UL) /*!< PORT1 PPS: PPS1 (Bitfield-Mask: 0x01) */ -#define PORT1_PPS_PPS2_Pos (2UL) /*!< PORT1 PPS: PPS2 (Bit 2) */ -#define PORT1_PPS_PPS2_Msk \ - (0x4UL) /*!< PORT1 PPS: PPS2 (Bitfield-Mask: 0x01) */ -#define PORT1_PPS_PPS3_Pos (3UL) /*!< PORT1 PPS: PPS3 (Bit 3) */ -#define PORT1_PPS_PPS3_Msk \ - (0x8UL) /*!< PORT1 PPS: PPS3 (Bitfield-Mask: 0x01) */ -#define PORT1_PPS_PPS4_Pos (4UL) /*!< PORT1 PPS: PPS4 (Bit 4) */ -#define PORT1_PPS_PPS4_Msk \ - (0x10UL) /*!< PORT1 PPS: PPS4 (Bitfield-Mask: 0x01) */ -#define PORT1_PPS_PPS5_Pos (5UL) /*!< PORT1 PPS: PPS5 (Bit 5) */ -#define PORT1_PPS_PPS5_Msk \ - (0x20UL) /*!< PORT1 PPS: PPS5 (Bitfield-Mask: 0x01) */ -#define PORT1_PPS_PPS6_Pos (6UL) /*!< PORT1 PPS: PPS6 (Bit 6) */ -#define PORT1_PPS_PPS6_Msk \ - (0x40UL) /*!< PORT1 PPS: PPS6 (Bitfield-Mask: 0x01) */ -#define PORT1_PPS_PPS7_Pos (7UL) /*!< PORT1 PPS: PPS7 (Bit 7) */ -#define PORT1_PPS_PPS7_Msk \ - (0x80UL) /*!< PORT1 PPS: PPS7 (Bitfield-Mask: 0x01) */ -#define PORT1_PPS_PPS8_Pos (8UL) /*!< PORT1 PPS: PPS8 (Bit 8) */ -#define PORT1_PPS_PPS8_Msk \ - (0x100UL) /*!< PORT1 PPS: PPS8 (Bitfield-Mask: 0x01) */ -#define PORT1_PPS_PPS9_Pos (9UL) /*!< PORT1 PPS: PPS9 (Bit 9) */ -#define PORT1_PPS_PPS9_Msk \ - (0x200UL) /*!< PORT1 PPS: PPS9 (Bitfield-Mask: 0x01) */ -#define PORT1_PPS_PPS10_Pos \ - (10UL) /*!< PORT1 PPS: PPS10 (Bit 10) */ -#define PORT1_PPS_PPS10_Msk \ - (0x400UL) /*!< PORT1 PPS: PPS10 (Bitfield-Mask: 0x01) */ -#define PORT1_PPS_PPS11_Pos \ - (11UL) /*!< PORT1 PPS: PPS11 (Bit 11) */ -#define PORT1_PPS_PPS11_Msk \ - (0x800UL) /*!< PORT1 PPS: PPS11 (Bitfield-Mask: 0x01) */ -#define PORT1_PPS_PPS12_Pos \ - (12UL) /*!< PORT1 PPS: PPS12 (Bit 12) */ -#define PORT1_PPS_PPS12_Msk \ - (0x1000UL) /*!< PORT1 PPS: PPS12 (Bitfield-Mask: 0x01) */ -#define PORT1_PPS_PPS13_Pos \ - (13UL) /*!< PORT1 PPS: PPS13 (Bit 13) */ -#define PORT1_PPS_PPS13_Msk \ - (0x2000UL) /*!< PORT1 PPS: PPS13 (Bitfield-Mask: 0x01) */ -#define PORT1_PPS_PPS14_Pos \ - (14UL) /*!< PORT1 PPS: PPS14 (Bit 14) */ -#define PORT1_PPS_PPS14_Msk \ - (0x4000UL) /*!< PORT1 PPS: PPS14 (Bitfield-Mask: 0x01) */ -#define PORT1_PPS_PPS15_Pos \ - (15UL) /*!< PORT1 PPS: PPS15 (Bit 15) */ -#define PORT1_PPS_PPS15_Msk \ - (0x8000UL) /*!< PORT1 PPS: PPS15 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- PORT1_HWSEL -------------------------------- */ -#define PORT1_HWSEL_HW0_Pos \ - (0UL) /*!< PORT1 HWSEL: HW0 (Bit 0) */ -#define PORT1_HWSEL_HW0_Msk \ - (0x3UL) /*!< PORT1 HWSEL: HW0 (Bitfield-Mask: 0x03) */ -#define PORT1_HWSEL_HW1_Pos \ - (2UL) /*!< PORT1 HWSEL: HW1 (Bit 2) */ -#define PORT1_HWSEL_HW1_Msk \ - (0xcUL) /*!< PORT1 HWSEL: HW1 (Bitfield-Mask: 0x03) */ -#define PORT1_HWSEL_HW2_Pos \ - (4UL) /*!< PORT1 HWSEL: HW2 (Bit 4) */ -#define PORT1_HWSEL_HW2_Msk \ - (0x30UL) /*!< PORT1 HWSEL: HW2 (Bitfield-Mask: 0x03) */ -#define PORT1_HWSEL_HW3_Pos \ - (6UL) /*!< PORT1 HWSEL: HW3 (Bit 6) */ -#define PORT1_HWSEL_HW3_Msk \ - (0xc0UL) /*!< PORT1 HWSEL: HW3 (Bitfield-Mask: 0x03) */ -#define PORT1_HWSEL_HW4_Pos \ - (8UL) /*!< PORT1 HWSEL: HW4 (Bit 8) */ -#define PORT1_HWSEL_HW4_Msk \ - (0x300UL) /*!< PORT1 HWSEL: HW4 (Bitfield-Mask: 0x03) */ -#define PORT1_HWSEL_HW5_Pos \ - (10UL) /*!< PORT1 HWSEL: HW5 (Bit 10) */ -#define PORT1_HWSEL_HW5_Msk \ - (0xc00UL) /*!< PORT1 HWSEL: HW5 (Bitfield-Mask: 0x03) */ -#define PORT1_HWSEL_HW6_Pos \ - (12UL) /*!< PORT1 HWSEL: HW6 (Bit 12) */ -#define PORT1_HWSEL_HW6_Msk \ - (0x3000UL) /*!< PORT1 HWSEL: HW6 (Bitfield-Mask: 0x03) */ -#define PORT1_HWSEL_HW7_Pos \ - (14UL) /*!< PORT1 HWSEL: HW7 (Bit 14) */ -#define PORT1_HWSEL_HW7_Msk \ - (0xc000UL) /*!< PORT1 HWSEL: HW7 (Bitfield-Mask: 0x03) */ -#define PORT1_HWSEL_HW8_Pos \ - (16UL) /*!< PORT1 HWSEL: HW8 (Bit 16) */ -#define PORT1_HWSEL_HW8_Msk \ - (0x30000UL) /*!< PORT1 HWSEL: HW8 (Bitfield-Mask: 0x03) */ -#define PORT1_HWSEL_HW9_Pos \ - (18UL) /*!< PORT1 HWSEL: HW9 (Bit 18) */ -#define PORT1_HWSEL_HW9_Msk \ - (0xc0000UL) /*!< PORT1 HWSEL: HW9 (Bitfield-Mask: 0x03) */ -#define PORT1_HWSEL_HW10_Pos \ - (20UL) /*!< PORT1 HWSEL: HW10 (Bit 20) */ -#define PORT1_HWSEL_HW10_Msk \ - (0x300000UL) /*!< PORT1 HWSEL: HW10 (Bitfield-Mask: 0x03) */ -#define PORT1_HWSEL_HW11_Pos \ - (22UL) /*!< PORT1 HWSEL: HW11 (Bit 22) */ -#define PORT1_HWSEL_HW11_Msk \ - (0xc00000UL) /*!< PORT1 HWSEL: HW11 (Bitfield-Mask: 0x03) */ -#define PORT1_HWSEL_HW12_Pos \ - (24UL) /*!< PORT1 HWSEL: HW12 (Bit 24) */ -#define PORT1_HWSEL_HW12_Msk \ - (0x3000000UL) /*!< PORT1 HWSEL: HW12 (Bitfield-Mask: 0x03) */ -#define PORT1_HWSEL_HW13_Pos \ - (26UL) /*!< PORT1 HWSEL: HW13 (Bit 26) */ -#define PORT1_HWSEL_HW13_Msk \ - (0xc000000UL) /*!< PORT1 HWSEL: HW13 (Bitfield-Mask: 0x03) */ -#define PORT1_HWSEL_HW14_Pos \ - (28UL) /*!< PORT1 HWSEL: HW14 (Bit 28) */ -#define PORT1_HWSEL_HW14_Msk \ - (0x30000000UL) /*!< PORT1 HWSEL: HW14 (Bitfield-Mask: 0x03) */ -#define PORT1_HWSEL_HW15_Pos \ - (30UL) /*!< PORT1 HWSEL: HW15 (Bit 30) */ -#define PORT1_HWSEL_HW15_Msk \ - (0xc0000000UL) /*!< PORT1 HWSEL: HW15 (Bitfield-Mask: 0x03) */ - -/* ================================================================================ */ -/* ================ struct 'PORT2' Position & Mask ================ */ -/* ================================================================================ */ - -/* ---------------------------------- PORT2_OUT --------------------------------- */ -#define PORT2_OUT_P0_Pos (0UL) /*!< PORT2 OUT: P0 (Bit 0) */ -#define PORT2_OUT_P0_Msk (0x1UL) /*!< PORT2 OUT: P0 (Bitfield-Mask: 0x01) */ -#define PORT2_OUT_P1_Pos (1UL) /*!< PORT2 OUT: P1 (Bit 1) */ -#define PORT2_OUT_P1_Msk (0x2UL) /*!< PORT2 OUT: P1 (Bitfield-Mask: 0x01) */ -#define PORT2_OUT_P2_Pos (2UL) /*!< PORT2 OUT: P2 (Bit 2) */ -#define PORT2_OUT_P2_Msk (0x4UL) /*!< PORT2 OUT: P2 (Bitfield-Mask: 0x01) */ -#define PORT2_OUT_P3_Pos (3UL) /*!< PORT2 OUT: P3 (Bit 3) */ -#define PORT2_OUT_P3_Msk (0x8UL) /*!< PORT2 OUT: P3 (Bitfield-Mask: 0x01) */ -#define PORT2_OUT_P4_Pos (4UL) /*!< PORT2 OUT: P4 (Bit 4) */ -#define PORT2_OUT_P4_Msk \ - (0x10UL) /*!< PORT2 OUT: P4 (Bitfield-Mask: 0x01) */ -#define PORT2_OUT_P5_Pos (5UL) /*!< PORT2 OUT: P5 (Bit 5) */ -#define PORT2_OUT_P5_Msk \ - (0x20UL) /*!< PORT2 OUT: P5 (Bitfield-Mask: 0x01) */ -#define PORT2_OUT_P6_Pos (6UL) /*!< PORT2 OUT: P6 (Bit 6) */ -#define PORT2_OUT_P6_Msk \ - (0x40UL) /*!< PORT2 OUT: P6 (Bitfield-Mask: 0x01) */ -#define PORT2_OUT_P7_Pos (7UL) /*!< PORT2 OUT: P7 (Bit 7) */ -#define PORT2_OUT_P7_Msk \ - (0x80UL) /*!< PORT2 OUT: P7 (Bitfield-Mask: 0x01) */ -#define PORT2_OUT_P8_Pos (8UL) /*!< PORT2 OUT: P8 (Bit 8) */ -#define PORT2_OUT_P8_Msk \ - (0x100UL) /*!< PORT2 OUT: P8 (Bitfield-Mask: 0x01) */ -#define PORT2_OUT_P9_Pos (9UL) /*!< PORT2 OUT: P9 (Bit 9) */ -#define PORT2_OUT_P9_Msk \ - (0x200UL) /*!< PORT2 OUT: P9 (Bitfield-Mask: 0x01) */ -#define PORT2_OUT_P10_Pos (10UL) /*!< PORT2 OUT: P10 (Bit 10) */ -#define PORT2_OUT_P10_Msk \ - (0x400UL) /*!< PORT2 OUT: P10 (Bitfield-Mask: 0x01) */ -#define PORT2_OUT_P11_Pos (11UL) /*!< PORT2 OUT: P11 (Bit 11) */ -#define PORT2_OUT_P11_Msk \ - (0x800UL) /*!< PORT2 OUT: P11 (Bitfield-Mask: 0x01) */ -#define PORT2_OUT_P12_Pos (12UL) /*!< PORT2 OUT: P12 (Bit 12) */ -#define PORT2_OUT_P12_Msk \ - (0x1000UL) /*!< PORT2 OUT: P12 (Bitfield-Mask: 0x01) */ -#define PORT2_OUT_P13_Pos (13UL) /*!< PORT2 OUT: P13 (Bit 13) */ -#define PORT2_OUT_P13_Msk \ - (0x2000UL) /*!< PORT2 OUT: P13 (Bitfield-Mask: 0x01) */ -#define PORT2_OUT_P14_Pos (14UL) /*!< PORT2 OUT: P14 (Bit 14) */ -#define PORT2_OUT_P14_Msk \ - (0x4000UL) /*!< PORT2 OUT: P14 (Bitfield-Mask: 0x01) */ -#define PORT2_OUT_P15_Pos (15UL) /*!< PORT2 OUT: P15 (Bit 15) */ -#define PORT2_OUT_P15_Msk \ - (0x8000UL) /*!< PORT2 OUT: P15 (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- PORT2_OMR --------------------------------- */ -#define PORT2_OMR_PS0_Pos (0UL) /*!< PORT2 OMR: PS0 (Bit 0) */ -#define PORT2_OMR_PS0_Msk \ - (0x1UL) /*!< PORT2 OMR: PS0 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PS1_Pos (1UL) /*!< PORT2 OMR: PS1 (Bit 1) */ -#define PORT2_OMR_PS1_Msk \ - (0x2UL) /*!< PORT2 OMR: PS1 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PS2_Pos (2UL) /*!< PORT2 OMR: PS2 (Bit 2) */ -#define PORT2_OMR_PS2_Msk \ - (0x4UL) /*!< PORT2 OMR: PS2 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PS3_Pos (3UL) /*!< PORT2 OMR: PS3 (Bit 3) */ -#define PORT2_OMR_PS3_Msk \ - (0x8UL) /*!< PORT2 OMR: PS3 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PS4_Pos (4UL) /*!< PORT2 OMR: PS4 (Bit 4) */ -#define PORT2_OMR_PS4_Msk \ - (0x10UL) /*!< PORT2 OMR: PS4 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PS5_Pos (5UL) /*!< PORT2 OMR: PS5 (Bit 5) */ -#define PORT2_OMR_PS5_Msk \ - (0x20UL) /*!< PORT2 OMR: PS5 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PS6_Pos (6UL) /*!< PORT2 OMR: PS6 (Bit 6) */ -#define PORT2_OMR_PS6_Msk \ - (0x40UL) /*!< PORT2 OMR: PS6 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PS7_Pos (7UL) /*!< PORT2 OMR: PS7 (Bit 7) */ -#define PORT2_OMR_PS7_Msk \ - (0x80UL) /*!< PORT2 OMR: PS7 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PS8_Pos (8UL) /*!< PORT2 OMR: PS8 (Bit 8) */ -#define PORT2_OMR_PS8_Msk \ - (0x100UL) /*!< PORT2 OMR: PS8 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PS9_Pos (9UL) /*!< PORT2 OMR: PS9 (Bit 9) */ -#define PORT2_OMR_PS9_Msk \ - (0x200UL) /*!< PORT2 OMR: PS9 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PS10_Pos \ - (10UL) /*!< PORT2 OMR: PS10 (Bit 10) */ -#define PORT2_OMR_PS10_Msk \ - (0x400UL) /*!< PORT2 OMR: PS10 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PS11_Pos \ - (11UL) /*!< PORT2 OMR: PS11 (Bit 11) */ -#define PORT2_OMR_PS11_Msk \ - (0x800UL) /*!< PORT2 OMR: PS11 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PS12_Pos \ - (12UL) /*!< PORT2 OMR: PS12 (Bit 12) */ -#define PORT2_OMR_PS12_Msk \ - (0x1000UL) /*!< PORT2 OMR: PS12 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PS13_Pos \ - (13UL) /*!< PORT2 OMR: PS13 (Bit 13) */ -#define PORT2_OMR_PS13_Msk \ - (0x2000UL) /*!< PORT2 OMR: PS13 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PS14_Pos \ - (14UL) /*!< PORT2 OMR: PS14 (Bit 14) */ -#define PORT2_OMR_PS14_Msk \ - (0x4000UL) /*!< PORT2 OMR: PS14 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PS15_Pos \ - (15UL) /*!< PORT2 OMR: PS15 (Bit 15) */ -#define PORT2_OMR_PS15_Msk \ - (0x8000UL) /*!< PORT2 OMR: PS15 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PR0_Pos (16UL) /*!< PORT2 OMR: PR0 (Bit 16) */ -#define PORT2_OMR_PR0_Msk \ - (0x10000UL) /*!< PORT2 OMR: PR0 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PR1_Pos (17UL) /*!< PORT2 OMR: PR1 (Bit 17) */ -#define PORT2_OMR_PR1_Msk \ - (0x20000UL) /*!< PORT2 OMR: PR1 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PR2_Pos (18UL) /*!< PORT2 OMR: PR2 (Bit 18) */ -#define PORT2_OMR_PR2_Msk \ - (0x40000UL) /*!< PORT2 OMR: PR2 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PR3_Pos (19UL) /*!< PORT2 OMR: PR3 (Bit 19) */ -#define PORT2_OMR_PR3_Msk \ - (0x80000UL) /*!< PORT2 OMR: PR3 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PR4_Pos (20UL) /*!< PORT2 OMR: PR4 (Bit 20) */ -#define PORT2_OMR_PR4_Msk \ - (0x100000UL) /*!< PORT2 OMR: PR4 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PR5_Pos (21UL) /*!< PORT2 OMR: PR5 (Bit 21) */ -#define PORT2_OMR_PR5_Msk \ - (0x200000UL) /*!< PORT2 OMR: PR5 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PR6_Pos (22UL) /*!< PORT2 OMR: PR6 (Bit 22) */ -#define PORT2_OMR_PR6_Msk \ - (0x400000UL) /*!< PORT2 OMR: PR6 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PR7_Pos (23UL) /*!< PORT2 OMR: PR7 (Bit 23) */ -#define PORT2_OMR_PR7_Msk \ - (0x800000UL) /*!< PORT2 OMR: PR7 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PR8_Pos (24UL) /*!< PORT2 OMR: PR8 (Bit 24) */ -#define PORT2_OMR_PR8_Msk \ - (0x1000000UL) /*!< PORT2 OMR: PR8 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PR9_Pos (25UL) /*!< PORT2 OMR: PR9 (Bit 25) */ -#define PORT2_OMR_PR9_Msk \ - (0x2000000UL) /*!< PORT2 OMR: PR9 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PR10_Pos \ - (26UL) /*!< PORT2 OMR: PR10 (Bit 26) */ -#define PORT2_OMR_PR10_Msk \ - (0x4000000UL) /*!< PORT2 OMR: PR10 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PR11_Pos \ - (27UL) /*!< PORT2 OMR: PR11 (Bit 27) */ -#define PORT2_OMR_PR11_Msk \ - (0x8000000UL) /*!< PORT2 OMR: PR11 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PR12_Pos \ - (28UL) /*!< PORT2 OMR: PR12 (Bit 28) */ -#define PORT2_OMR_PR12_Msk \ - (0x10000000UL) /*!< PORT2 OMR: PR12 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PR13_Pos \ - (29UL) /*!< PORT2 OMR: PR13 (Bit 29) */ -#define PORT2_OMR_PR13_Msk \ - (0x20000000UL) /*!< PORT2 OMR: PR13 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PR14_Pos \ - (30UL) /*!< PORT2 OMR: PR14 (Bit 30) */ -#define PORT2_OMR_PR14_Msk \ - (0x40000000UL) /*!< PORT2 OMR: PR14 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PR15_Pos \ - (31UL) /*!< PORT2 OMR: PR15 (Bit 31) */ -#define PORT2_OMR_PR15_Msk \ - (0x80000000UL) /*!< PORT2 OMR: PR15 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- PORT2_IOCR0 -------------------------------- */ -#define PORT2_IOCR0_PC0_Pos \ - (3UL) /*!< PORT2 IOCR0: PC0 (Bit 3) */ -#define PORT2_IOCR0_PC0_Msk \ - (0xf8UL) /*!< PORT2 IOCR0: PC0 (Bitfield-Mask: 0x1f) */ -#define PORT2_IOCR0_PC1_Pos \ - (11UL) /*!< PORT2 IOCR0: PC1 (Bit 11) */ -#define PORT2_IOCR0_PC1_Msk \ - (0xf800UL) /*!< PORT2 IOCR0: PC1 (Bitfield-Mask: 0x1f) */ -#define PORT2_IOCR0_PC2_Pos \ - (19UL) /*!< PORT2 IOCR0: PC2 (Bit 19) */ -#define PORT2_IOCR0_PC2_Msk \ - (0xf80000UL) /*!< PORT2 IOCR0: PC2 (Bitfield-Mask: 0x1f) */ -#define PORT2_IOCR0_PC3_Pos \ - (27UL) /*!< PORT2 IOCR0: PC3 (Bit 27) */ -#define PORT2_IOCR0_PC3_Msk \ - (0xf8000000UL) /*!< PORT2 IOCR0: PC3 (Bitfield-Mask: 0x1f) */ - -/* --------------------------------- PORT2_IOCR4 -------------------------------- */ -#define PORT2_IOCR4_PC4_Pos \ - (3UL) /*!< PORT2 IOCR4: PC4 (Bit 3) */ -#define PORT2_IOCR4_PC4_Msk \ - (0xf8UL) /*!< PORT2 IOCR4: PC4 (Bitfield-Mask: 0x1f) */ -#define PORT2_IOCR4_PC5_Pos \ - (11UL) /*!< PORT2 IOCR4: PC5 (Bit 11) */ -#define PORT2_IOCR4_PC5_Msk \ - (0xf800UL) /*!< PORT2 IOCR4: PC5 (Bitfield-Mask: 0x1f) */ -#define PORT2_IOCR4_PC6_Pos \ - (19UL) /*!< PORT2 IOCR4: PC6 (Bit 19) */ -#define PORT2_IOCR4_PC6_Msk \ - (0xf80000UL) /*!< PORT2 IOCR4: PC6 (Bitfield-Mask: 0x1f) */ -#define PORT2_IOCR4_PC7_Pos \ - (27UL) /*!< PORT2 IOCR4: PC7 (Bit 27) */ -#define PORT2_IOCR4_PC7_Msk \ - (0xf8000000UL) /*!< PORT2 IOCR4: PC7 (Bitfield-Mask: 0x1f) */ - -/* --------------------------------- PORT2_IOCR8 -------------------------------- */ -#define PORT2_IOCR8_PC8_Pos \ - (3UL) /*!< PORT2 IOCR8: PC8 (Bit 3) */ -#define PORT2_IOCR8_PC8_Msk \ - (0xf8UL) /*!< PORT2 IOCR8: PC8 (Bitfield-Mask: 0x1f) */ -#define PORT2_IOCR8_PC9_Pos \ - (11UL) /*!< PORT2 IOCR8: PC9 (Bit 11) */ -#define PORT2_IOCR8_PC9_Msk \ - (0xf800UL) /*!< PORT2 IOCR8: PC9 (Bitfield-Mask: 0x1f) */ -#define PORT2_IOCR8_PC10_Pos \ - (19UL) /*!< PORT2 IOCR8: PC10 (Bit 19) */ -#define PORT2_IOCR8_PC10_Msk \ - (0xf80000UL) /*!< PORT2 IOCR8: PC10 (Bitfield-Mask: 0x1f) */ -#define PORT2_IOCR8_PC11_Pos \ - (27UL) /*!< PORT2 IOCR8: PC11 (Bit 27) */ -#define PORT2_IOCR8_PC11_Msk \ - (0xf8000000UL) /*!< PORT2 IOCR8: PC11 (Bitfield-Mask: 0x1f) */ - -/* -------------------------------- PORT2_IOCR12 -------------------------------- */ -#define PORT2_IOCR12_PC12_Pos \ - (3UL) /*!< PORT2 IOCR12: PC12 (Bit 3) */ -#define PORT2_IOCR12_PC12_Msk \ - (0xf8UL) /*!< PORT2 IOCR12: PC12 (Bitfield-Mask: 0x1f) */ -#define PORT2_IOCR12_PC13_Pos \ - (11UL) /*!< PORT2 IOCR12: PC13 (Bit 11) */ -#define PORT2_IOCR12_PC13_Msk \ - (0xf800UL) /*!< PORT2 IOCR12: PC13 (Bitfield-Mask: 0x1f) */ -#define PORT2_IOCR12_PC14_Pos \ - (19UL) /*!< PORT2 IOCR12: PC14 (Bit 19) */ -#define PORT2_IOCR12_PC14_Msk \ - (0xf80000UL) /*!< PORT2 IOCR12: PC14 (Bitfield-Mask: 0x1f) */ -#define PORT2_IOCR12_PC15_Pos \ - (27UL) /*!< PORT2 IOCR12: PC15 (Bit 27) */ -#define PORT2_IOCR12_PC15_Msk \ - (0xf8000000UL) /*!< PORT2 IOCR12: PC15 (Bitfield-Mask: 0x1f) */ - -/* ---------------------------------- PORT2_IN ---------------------------------- */ -#define PORT2_IN_P0_Pos (0UL) /*!< PORT2 IN: P0 (Bit 0) */ -#define PORT2_IN_P0_Msk (0x1UL) /*!< PORT2 IN: P0 (Bitfield-Mask: 0x01) */ -#define PORT2_IN_P1_Pos (1UL) /*!< PORT2 IN: P1 (Bit 1) */ -#define PORT2_IN_P1_Msk (0x2UL) /*!< PORT2 IN: P1 (Bitfield-Mask: 0x01) */ -#define PORT2_IN_P2_Pos (2UL) /*!< PORT2 IN: P2 (Bit 2) */ -#define PORT2_IN_P2_Msk (0x4UL) /*!< PORT2 IN: P2 (Bitfield-Mask: 0x01) */ -#define PORT2_IN_P3_Pos (3UL) /*!< PORT2 IN: P3 (Bit 3) */ -#define PORT2_IN_P3_Msk (0x8UL) /*!< PORT2 IN: P3 (Bitfield-Mask: 0x01) */ -#define PORT2_IN_P4_Pos (4UL) /*!< PORT2 IN: P4 (Bit 4) */ -#define PORT2_IN_P4_Msk (0x10UL) /*!< PORT2 IN: P4 (Bitfield-Mask: 0x01) */ -#define PORT2_IN_P5_Pos (5UL) /*!< PORT2 IN: P5 (Bit 5) */ -#define PORT2_IN_P5_Msk (0x20UL) /*!< PORT2 IN: P5 (Bitfield-Mask: 0x01) */ -#define PORT2_IN_P6_Pos (6UL) /*!< PORT2 IN: P6 (Bit 6) */ -#define PORT2_IN_P6_Msk (0x40UL) /*!< PORT2 IN: P6 (Bitfield-Mask: 0x01) */ -#define PORT2_IN_P7_Pos (7UL) /*!< PORT2 IN: P7 (Bit 7) */ -#define PORT2_IN_P7_Msk (0x80UL) /*!< PORT2 IN: P7 (Bitfield-Mask: 0x01) */ -#define PORT2_IN_P8_Pos (8UL) /*!< PORT2 IN: P8 (Bit 8) */ -#define PORT2_IN_P8_Msk \ - (0x100UL) /*!< PORT2 IN: P8 (Bitfield-Mask: 0x01) */ -#define PORT2_IN_P9_Pos (9UL) /*!< PORT2 IN: P9 (Bit 9) */ -#define PORT2_IN_P9_Msk \ - (0x200UL) /*!< PORT2 IN: P9 (Bitfield-Mask: 0x01) */ -#define PORT2_IN_P10_Pos (10UL) /*!< PORT2 IN: P10 (Bit 10) */ -#define PORT2_IN_P10_Msk \ - (0x400UL) /*!< PORT2 IN: P10 (Bitfield-Mask: 0x01) */ -#define PORT2_IN_P11_Pos (11UL) /*!< PORT2 IN: P11 (Bit 11) */ -#define PORT2_IN_P11_Msk \ - (0x800UL) /*!< PORT2 IN: P11 (Bitfield-Mask: 0x01) */ -#define PORT2_IN_P12_Pos (12UL) /*!< PORT2 IN: P12 (Bit 12) */ -#define PORT2_IN_P12_Msk \ - (0x1000UL) /*!< PORT2 IN: P12 (Bitfield-Mask: 0x01) */ -#define PORT2_IN_P13_Pos (13UL) /*!< PORT2 IN: P13 (Bit 13) */ -#define PORT2_IN_P13_Msk \ - (0x2000UL) /*!< PORT2 IN: P13 (Bitfield-Mask: 0x01) */ -#define PORT2_IN_P14_Pos (14UL) /*!< PORT2 IN: P14 (Bit 14) */ -#define PORT2_IN_P14_Msk \ - (0x4000UL) /*!< PORT2 IN: P14 (Bitfield-Mask: 0x01) */ -#define PORT2_IN_P15_Pos (15UL) /*!< PORT2 IN: P15 (Bit 15) */ -#define PORT2_IN_P15_Msk \ - (0x8000UL) /*!< PORT2 IN: P15 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- PORT2_PDR0 --------------------------------- */ -#define PORT2_PDR0_PD0_Pos (0UL) /*!< PORT2 PDR0: PD0 (Bit 0) */ -#define PORT2_PDR0_PD0_Msk \ - (0x7UL) /*!< PORT2 PDR0: PD0 (Bitfield-Mask: 0x07) */ -#define PORT2_PDR0_PD1_Pos (4UL) /*!< PORT2 PDR0: PD1 (Bit 4) */ -#define PORT2_PDR0_PD1_Msk \ - (0x70UL) /*!< PORT2 PDR0: PD1 (Bitfield-Mask: 0x07) */ -#define PORT2_PDR0_PD2_Pos (8UL) /*!< PORT2 PDR0: PD2 (Bit 8) */ -#define PORT2_PDR0_PD2_Msk \ - (0x700UL) /*!< PORT2 PDR0: PD2 (Bitfield-Mask: 0x07) */ -#define PORT2_PDR0_PD3_Pos \ - (12UL) /*!< PORT2 PDR0: PD3 (Bit 12) */ -#define PORT2_PDR0_PD3_Msk \ - (0x7000UL) /*!< PORT2 PDR0: PD3 (Bitfield-Mask: 0x07) */ -#define PORT2_PDR0_PD4_Pos \ - (16UL) /*!< PORT2 PDR0: PD4 (Bit 16) */ -#define PORT2_PDR0_PD4_Msk \ - (0x70000UL) /*!< PORT2 PDR0: PD4 (Bitfield-Mask: 0x07) */ -#define PORT2_PDR0_PD5_Pos \ - (20UL) /*!< PORT2 PDR0: PD5 (Bit 20) */ -#define PORT2_PDR0_PD5_Msk \ - (0x700000UL) /*!< PORT2 PDR0: PD5 (Bitfield-Mask: 0x07) */ -#define PORT2_PDR0_PD6_Pos \ - (24UL) /*!< PORT2 PDR0: PD6 (Bit 24) */ -#define PORT2_PDR0_PD6_Msk \ - (0x7000000UL) /*!< PORT2 PDR0: PD6 (Bitfield-Mask: 0x07) */ -#define PORT2_PDR0_PD7_Pos \ - (28UL) /*!< PORT2 PDR0: PD7 (Bit 28) */ -#define PORT2_PDR0_PD7_Msk \ - (0x70000000UL) /*!< PORT2 PDR0: PD7 (Bitfield-Mask: 0x07) */ - -/* --------------------------------- PORT2_PDR1 --------------------------------- */ -#define PORT2_PDR1_PD8_Pos (0UL) /*!< PORT2 PDR1: PD8 (Bit 0) */ -#define PORT2_PDR1_PD8_Msk \ - (0x7UL) /*!< PORT2 PDR1: PD8 (Bitfield-Mask: 0x07) */ -#define PORT2_PDR1_PD9_Pos (4UL) /*!< PORT2 PDR1: PD9 (Bit 4) */ -#define PORT2_PDR1_PD9_Msk \ - (0x70UL) /*!< PORT2 PDR1: PD9 (Bitfield-Mask: 0x07) */ -#define PORT2_PDR1_PD10_Pos \ - (8UL) /*!< PORT2 PDR1: PD10 (Bit 8) */ -#define PORT2_PDR1_PD10_Msk \ - (0x700UL) /*!< PORT2 PDR1: PD10 (Bitfield-Mask: 0x07) */ -#define PORT2_PDR1_PD11_Pos \ - (12UL) /*!< PORT2 PDR1: PD11 (Bit 12) */ -#define PORT2_PDR1_PD11_Msk \ - (0x7000UL) /*!< PORT2 PDR1: PD11 (Bitfield-Mask: 0x07) */ -#define PORT2_PDR1_PD12_Pos \ - (16UL) /*!< PORT2 PDR1: PD12 (Bit 16) */ -#define PORT2_PDR1_PD12_Msk \ - (0x70000UL) /*!< PORT2 PDR1: PD12 (Bitfield-Mask: 0x07) */ -#define PORT2_PDR1_PD13_Pos \ - (20UL) /*!< PORT2 PDR1: PD13 (Bit 20) */ -#define PORT2_PDR1_PD13_Msk \ - (0x700000UL) /*!< PORT2 PDR1: PD13 (Bitfield-Mask: 0x07) */ -#define PORT2_PDR1_PD14_Pos \ - (24UL) /*!< PORT2 PDR1: PD14 (Bit 24) */ -#define PORT2_PDR1_PD14_Msk \ - (0x7000000UL) /*!< PORT2 PDR1: PD14 (Bitfield-Mask: 0x07) */ -#define PORT2_PDR1_PD15_Pos \ - (28UL) /*!< PORT2 PDR1: PD15 (Bit 28) */ -#define PORT2_PDR1_PD15_Msk \ - (0x70000000UL) /*!< PORT2 PDR1: PD15 (Bitfield-Mask: 0x07) */ - -/* --------------------------------- PORT2_PDISC -------------------------------- */ -#define PORT2_PDISC_PDIS0_Pos \ - (0UL) /*!< PORT2 PDISC: PDIS0 (Bit 0) */ -#define PORT2_PDISC_PDIS0_Msk \ - (0x1UL) /*!< PORT2 PDISC: PDIS0 (Bitfield-Mask: 0x01) */ -#define PORT2_PDISC_PDIS1_Pos \ - (1UL) /*!< PORT2 PDISC: PDIS1 (Bit 1) */ -#define PORT2_PDISC_PDIS1_Msk \ - (0x2UL) /*!< PORT2 PDISC: PDIS1 (Bitfield-Mask: 0x01) */ -#define PORT2_PDISC_PDIS2_Pos \ - (2UL) /*!< PORT2 PDISC: PDIS2 (Bit 2) */ -#define PORT2_PDISC_PDIS2_Msk \ - (0x4UL) /*!< PORT2 PDISC: PDIS2 (Bitfield-Mask: 0x01) */ -#define PORT2_PDISC_PDIS3_Pos \ - (3UL) /*!< PORT2 PDISC: PDIS3 (Bit 3) */ -#define PORT2_PDISC_PDIS3_Msk \ - (0x8UL) /*!< PORT2 PDISC: PDIS3 (Bitfield-Mask: 0x01) */ -#define PORT2_PDISC_PDIS4_Pos \ - (4UL) /*!< PORT2 PDISC: PDIS4 (Bit 4) */ -#define PORT2_PDISC_PDIS4_Msk \ - (0x10UL) /*!< PORT2 PDISC: PDIS4 (Bitfield-Mask: 0x01) */ -#define PORT2_PDISC_PDIS5_Pos \ - (5UL) /*!< PORT2 PDISC: PDIS5 (Bit 5) */ -#define PORT2_PDISC_PDIS5_Msk \ - (0x20UL) /*!< PORT2 PDISC: PDIS5 (Bitfield-Mask: 0x01) */ -#define PORT2_PDISC_PDIS6_Pos \ - (6UL) /*!< PORT2 PDISC: PDIS6 (Bit 6) */ -#define PORT2_PDISC_PDIS6_Msk \ - (0x40UL) /*!< PORT2 PDISC: PDIS6 (Bitfield-Mask: 0x01) */ -#define PORT2_PDISC_PDIS7_Pos \ - (7UL) /*!< PORT2 PDISC: PDIS7 (Bit 7) */ -#define PORT2_PDISC_PDIS7_Msk \ - (0x80UL) /*!< PORT2 PDISC: PDIS7 (Bitfield-Mask: 0x01) */ -#define PORT2_PDISC_PDIS8_Pos \ - (8UL) /*!< PORT2 PDISC: PDIS8 (Bit 8) */ -#define PORT2_PDISC_PDIS8_Msk \ - (0x100UL) /*!< PORT2 PDISC: PDIS8 (Bitfield-Mask: 0x01) */ -#define PORT2_PDISC_PDIS9_Pos \ - (9UL) /*!< PORT2 PDISC: PDIS9 (Bit 9) */ -#define PORT2_PDISC_PDIS9_Msk \ - (0x200UL) /*!< PORT2 PDISC: PDIS9 (Bitfield-Mask: 0x01) */ -#define PORT2_PDISC_PDIS10_Pos \ - (10UL) /*!< PORT2 PDISC: PDIS10 (Bit 10) */ -#define PORT2_PDISC_PDIS10_Msk \ - (0x400UL) /*!< PORT2 PDISC: PDIS10 (Bitfield-Mask: 0x01) */ -#define PORT2_PDISC_PDIS11_Pos \ - (11UL) /*!< PORT2 PDISC: PDIS11 (Bit 11) */ -#define PORT2_PDISC_PDIS11_Msk \ - (0x800UL) /*!< PORT2 PDISC: PDIS11 (Bitfield-Mask: 0x01) */ -#define PORT2_PDISC_PDIS12_Pos \ - (12UL) /*!< PORT2 PDISC: PDIS12 (Bit 12) */ -#define PORT2_PDISC_PDIS12_Msk \ - (0x1000UL) /*!< PORT2 PDISC: PDIS12 (Bitfield-Mask: 0x01) */ -#define PORT2_PDISC_PDIS13_Pos \ - (13UL) /*!< PORT2 PDISC: PDIS13 (Bit 13) */ -#define PORT2_PDISC_PDIS13_Msk \ - (0x2000UL) /*!< PORT2 PDISC: PDIS13 (Bitfield-Mask: 0x01) */ -#define PORT2_PDISC_PDIS14_Pos \ - (14UL) /*!< PORT2 PDISC: PDIS14 (Bit 14) */ -#define PORT2_PDISC_PDIS14_Msk \ - (0x4000UL) /*!< PORT2 PDISC: PDIS14 (Bitfield-Mask: 0x01) */ -#define PORT2_PDISC_PDIS15_Pos \ - (15UL) /*!< PORT2 PDISC: PDIS15 (Bit 15) */ -#define PORT2_PDISC_PDIS15_Msk \ - (0x8000UL) /*!< PORT2 PDISC: PDIS15 (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- PORT2_PPS --------------------------------- */ -#define PORT2_PPS_PPS0_Pos (0UL) /*!< PORT2 PPS: PPS0 (Bit 0) */ -#define PORT2_PPS_PPS0_Msk \ - (0x1UL) /*!< PORT2 PPS: PPS0 (Bitfield-Mask: 0x01) */ -#define PORT2_PPS_PPS1_Pos (1UL) /*!< PORT2 PPS: PPS1 (Bit 1) */ -#define PORT2_PPS_PPS1_Msk \ - (0x2UL) /*!< PORT2 PPS: PPS1 (Bitfield-Mask: 0x01) */ -#define PORT2_PPS_PPS2_Pos (2UL) /*!< PORT2 PPS: PPS2 (Bit 2) */ -#define PORT2_PPS_PPS2_Msk \ - (0x4UL) /*!< PORT2 PPS: PPS2 (Bitfield-Mask: 0x01) */ -#define PORT2_PPS_PPS3_Pos (3UL) /*!< PORT2 PPS: PPS3 (Bit 3) */ -#define PORT2_PPS_PPS3_Msk \ - (0x8UL) /*!< PORT2 PPS: PPS3 (Bitfield-Mask: 0x01) */ -#define PORT2_PPS_PPS4_Pos (4UL) /*!< PORT2 PPS: PPS4 (Bit 4) */ -#define PORT2_PPS_PPS4_Msk \ - (0x10UL) /*!< PORT2 PPS: PPS4 (Bitfield-Mask: 0x01) */ -#define PORT2_PPS_PPS5_Pos (5UL) /*!< PORT2 PPS: PPS5 (Bit 5) */ -#define PORT2_PPS_PPS5_Msk \ - (0x20UL) /*!< PORT2 PPS: PPS5 (Bitfield-Mask: 0x01) */ -#define PORT2_PPS_PPS6_Pos (6UL) /*!< PORT2 PPS: PPS6 (Bit 6) */ -#define PORT2_PPS_PPS6_Msk \ - (0x40UL) /*!< PORT2 PPS: PPS6 (Bitfield-Mask: 0x01) */ -#define PORT2_PPS_PPS7_Pos (7UL) /*!< PORT2 PPS: PPS7 (Bit 7) */ -#define PORT2_PPS_PPS7_Msk \ - (0x80UL) /*!< PORT2 PPS: PPS7 (Bitfield-Mask: 0x01) */ -#define PORT2_PPS_PPS8_Pos (8UL) /*!< PORT2 PPS: PPS8 (Bit 8) */ -#define PORT2_PPS_PPS8_Msk \ - (0x100UL) /*!< PORT2 PPS: PPS8 (Bitfield-Mask: 0x01) */ -#define PORT2_PPS_PPS9_Pos (9UL) /*!< PORT2 PPS: PPS9 (Bit 9) */ -#define PORT2_PPS_PPS9_Msk \ - (0x200UL) /*!< PORT2 PPS: PPS9 (Bitfield-Mask: 0x01) */ -#define PORT2_PPS_PPS10_Pos \ - (10UL) /*!< PORT2 PPS: PPS10 (Bit 10) */ -#define PORT2_PPS_PPS10_Msk \ - (0x400UL) /*!< PORT2 PPS: PPS10 (Bitfield-Mask: 0x01) */ -#define PORT2_PPS_PPS11_Pos \ - (11UL) /*!< PORT2 PPS: PPS11 (Bit 11) */ -#define PORT2_PPS_PPS11_Msk \ - (0x800UL) /*!< PORT2 PPS: PPS11 (Bitfield-Mask: 0x01) */ -#define PORT2_PPS_PPS12_Pos \ - (12UL) /*!< PORT2 PPS: PPS12 (Bit 12) */ -#define PORT2_PPS_PPS12_Msk \ - (0x1000UL) /*!< PORT2 PPS: PPS12 (Bitfield-Mask: 0x01) */ -#define PORT2_PPS_PPS13_Pos \ - (13UL) /*!< PORT2 PPS: PPS13 (Bit 13) */ -#define PORT2_PPS_PPS13_Msk \ - (0x2000UL) /*!< PORT2 PPS: PPS13 (Bitfield-Mask: 0x01) */ -#define PORT2_PPS_PPS14_Pos \ - (14UL) /*!< PORT2 PPS: PPS14 (Bit 14) */ -#define PORT2_PPS_PPS14_Msk \ - (0x4000UL) /*!< PORT2 PPS: PPS14 (Bitfield-Mask: 0x01) */ -#define PORT2_PPS_PPS15_Pos \ - (15UL) /*!< PORT2 PPS: PPS15 (Bit 15) */ -#define PORT2_PPS_PPS15_Msk \ - (0x8000UL) /*!< PORT2 PPS: PPS15 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- PORT2_HWSEL -------------------------------- */ -#define PORT2_HWSEL_HW0_Pos \ - (0UL) /*!< PORT2 HWSEL: HW0 (Bit 0) */ -#define PORT2_HWSEL_HW0_Msk \ - (0x3UL) /*!< PORT2 HWSEL: HW0 (Bitfield-Mask: 0x03) */ -#define PORT2_HWSEL_HW1_Pos \ - (2UL) /*!< PORT2 HWSEL: HW1 (Bit 2) */ -#define PORT2_HWSEL_HW1_Msk \ - (0xcUL) /*!< PORT2 HWSEL: HW1 (Bitfield-Mask: 0x03) */ -#define PORT2_HWSEL_HW2_Pos \ - (4UL) /*!< PORT2 HWSEL: HW2 (Bit 4) */ -#define PORT2_HWSEL_HW2_Msk \ - (0x30UL) /*!< PORT2 HWSEL: HW2 (Bitfield-Mask: 0x03) */ -#define PORT2_HWSEL_HW3_Pos \ - (6UL) /*!< PORT2 HWSEL: HW3 (Bit 6) */ -#define PORT2_HWSEL_HW3_Msk \ - (0xc0UL) /*!< PORT2 HWSEL: HW3 (Bitfield-Mask: 0x03) */ -#define PORT2_HWSEL_HW4_Pos \ - (8UL) /*!< PORT2 HWSEL: HW4 (Bit 8) */ -#define PORT2_HWSEL_HW4_Msk \ - (0x300UL) /*!< PORT2 HWSEL: HW4 (Bitfield-Mask: 0x03) */ -#define PORT2_HWSEL_HW5_Pos \ - (10UL) /*!< PORT2 HWSEL: HW5 (Bit 10) */ -#define PORT2_HWSEL_HW5_Msk \ - (0xc00UL) /*!< PORT2 HWSEL: HW5 (Bitfield-Mask: 0x03) */ -#define PORT2_HWSEL_HW6_Pos \ - (12UL) /*!< PORT2 HWSEL: HW6 (Bit 12) */ -#define PORT2_HWSEL_HW6_Msk \ - (0x3000UL) /*!< PORT2 HWSEL: HW6 (Bitfield-Mask: 0x03) */ -#define PORT2_HWSEL_HW7_Pos \ - (14UL) /*!< PORT2 HWSEL: HW7 (Bit 14) */ -#define PORT2_HWSEL_HW7_Msk \ - (0xc000UL) /*!< PORT2 HWSEL: HW7 (Bitfield-Mask: 0x03) */ -#define PORT2_HWSEL_HW8_Pos \ - (16UL) /*!< PORT2 HWSEL: HW8 (Bit 16) */ -#define PORT2_HWSEL_HW8_Msk \ - (0x30000UL) /*!< PORT2 HWSEL: HW8 (Bitfield-Mask: 0x03) */ -#define PORT2_HWSEL_HW9_Pos \ - (18UL) /*!< PORT2 HWSEL: HW9 (Bit 18) */ -#define PORT2_HWSEL_HW9_Msk \ - (0xc0000UL) /*!< PORT2 HWSEL: HW9 (Bitfield-Mask: 0x03) */ -#define PORT2_HWSEL_HW10_Pos \ - (20UL) /*!< PORT2 HWSEL: HW10 (Bit 20) */ -#define PORT2_HWSEL_HW10_Msk \ - (0x300000UL) /*!< PORT2 HWSEL: HW10 (Bitfield-Mask: 0x03) */ -#define PORT2_HWSEL_HW11_Pos \ - (22UL) /*!< PORT2 HWSEL: HW11 (Bit 22) */ -#define PORT2_HWSEL_HW11_Msk \ - (0xc00000UL) /*!< PORT2 HWSEL: HW11 (Bitfield-Mask: 0x03) */ -#define PORT2_HWSEL_HW12_Pos \ - (24UL) /*!< PORT2 HWSEL: HW12 (Bit 24) */ -#define PORT2_HWSEL_HW12_Msk \ - (0x3000000UL) /*!< PORT2 HWSEL: HW12 (Bitfield-Mask: 0x03) */ -#define PORT2_HWSEL_HW13_Pos \ - (26UL) /*!< PORT2 HWSEL: HW13 (Bit 26) */ -#define PORT2_HWSEL_HW13_Msk \ - (0xc000000UL) /*!< PORT2 HWSEL: HW13 (Bitfield-Mask: 0x03) */ -#define PORT2_HWSEL_HW14_Pos \ - (28UL) /*!< PORT2 HWSEL: HW14 (Bit 28) */ -#define PORT2_HWSEL_HW14_Msk \ - (0x30000000UL) /*!< PORT2 HWSEL: HW14 (Bitfield-Mask: 0x03) */ -#define PORT2_HWSEL_HW15_Pos \ - (30UL) /*!< PORT2 HWSEL: HW15 (Bit 30) */ -#define PORT2_HWSEL_HW15_Msk \ - (0xc0000000UL) /*!< PORT2 HWSEL: HW15 (Bitfield-Mask: 0x03) */ - -/* ================================================================================ */ -/* ================ struct 'PORT3' Position & Mask ================ */ -/* ================================================================================ */ - -/* ---------------------------------- PORT3_OUT --------------------------------- */ -#define PORT3_OUT_P0_Pos (0UL) /*!< PORT3 OUT: P0 (Bit 0) */ -#define PORT3_OUT_P0_Msk (0x1UL) /*!< PORT3 OUT: P0 (Bitfield-Mask: 0x01) */ -#define PORT3_OUT_P1_Pos (1UL) /*!< PORT3 OUT: P1 (Bit 1) */ -#define PORT3_OUT_P1_Msk (0x2UL) /*!< PORT3 OUT: P1 (Bitfield-Mask: 0x01) */ -#define PORT3_OUT_P2_Pos (2UL) /*!< PORT3 OUT: P2 (Bit 2) */ -#define PORT3_OUT_P2_Msk (0x4UL) /*!< PORT3 OUT: P2 (Bitfield-Mask: 0x01) */ -#define PORT3_OUT_P3_Pos (3UL) /*!< PORT3 OUT: P3 (Bit 3) */ -#define PORT3_OUT_P3_Msk (0x8UL) /*!< PORT3 OUT: P3 (Bitfield-Mask: 0x01) */ -#define PORT3_OUT_P4_Pos (4UL) /*!< PORT3 OUT: P4 (Bit 4) */ -#define PORT3_OUT_P4_Msk \ - (0x10UL) /*!< PORT3 OUT: P4 (Bitfield-Mask: 0x01) */ -#define PORT3_OUT_P5_Pos (5UL) /*!< PORT3 OUT: P5 (Bit 5) */ -#define PORT3_OUT_P5_Msk \ - (0x20UL) /*!< PORT3 OUT: P5 (Bitfield-Mask: 0x01) */ -#define PORT3_OUT_P6_Pos (6UL) /*!< PORT3 OUT: P6 (Bit 6) */ -#define PORT3_OUT_P6_Msk \ - (0x40UL) /*!< PORT3 OUT: P6 (Bitfield-Mask: 0x01) */ -#define PORT3_OUT_P7_Pos (7UL) /*!< PORT3 OUT: P7 (Bit 7) */ -#define PORT3_OUT_P7_Msk \ - (0x80UL) /*!< PORT3 OUT: P7 (Bitfield-Mask: 0x01) */ -#define PORT3_OUT_P8_Pos (8UL) /*!< PORT3 OUT: P8 (Bit 8) */ -#define PORT3_OUT_P8_Msk \ - (0x100UL) /*!< PORT3 OUT: P8 (Bitfield-Mask: 0x01) */ -#define PORT3_OUT_P9_Pos (9UL) /*!< PORT3 OUT: P9 (Bit 9) */ -#define PORT3_OUT_P9_Msk \ - (0x200UL) /*!< PORT3 OUT: P9 (Bitfield-Mask: 0x01) */ -#define PORT3_OUT_P10_Pos (10UL) /*!< PORT3 OUT: P10 (Bit 10) */ -#define PORT3_OUT_P10_Msk \ - (0x400UL) /*!< PORT3 OUT: P10 (Bitfield-Mask: 0x01) */ -#define PORT3_OUT_P11_Pos (11UL) /*!< PORT3 OUT: P11 (Bit 11) */ -#define PORT3_OUT_P11_Msk \ - (0x800UL) /*!< PORT3 OUT: P11 (Bitfield-Mask: 0x01) */ -#define PORT3_OUT_P12_Pos (12UL) /*!< PORT3 OUT: P12 (Bit 12) */ -#define PORT3_OUT_P12_Msk \ - (0x1000UL) /*!< PORT3 OUT: P12 (Bitfield-Mask: 0x01) */ -#define PORT3_OUT_P13_Pos (13UL) /*!< PORT3 OUT: P13 (Bit 13) */ -#define PORT3_OUT_P13_Msk \ - (0x2000UL) /*!< PORT3 OUT: P13 (Bitfield-Mask: 0x01) */ -#define PORT3_OUT_P14_Pos (14UL) /*!< PORT3 OUT: P14 (Bit 14) */ -#define PORT3_OUT_P14_Msk \ - (0x4000UL) /*!< PORT3 OUT: P14 (Bitfield-Mask: 0x01) */ -#define PORT3_OUT_P15_Pos (15UL) /*!< PORT3 OUT: P15 (Bit 15) */ -#define PORT3_OUT_P15_Msk \ - (0x8000UL) /*!< PORT3 OUT: P15 (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- PORT3_OMR --------------------------------- */ -#define PORT3_OMR_PS0_Pos (0UL) /*!< PORT3 OMR: PS0 (Bit 0) */ -#define PORT3_OMR_PS0_Msk \ - (0x1UL) /*!< PORT3 OMR: PS0 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PS1_Pos (1UL) /*!< PORT3 OMR: PS1 (Bit 1) */ -#define PORT3_OMR_PS1_Msk \ - (0x2UL) /*!< PORT3 OMR: PS1 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PS2_Pos (2UL) /*!< PORT3 OMR: PS2 (Bit 2) */ -#define PORT3_OMR_PS2_Msk \ - (0x4UL) /*!< PORT3 OMR: PS2 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PS3_Pos (3UL) /*!< PORT3 OMR: PS3 (Bit 3) */ -#define PORT3_OMR_PS3_Msk \ - (0x8UL) /*!< PORT3 OMR: PS3 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PS4_Pos (4UL) /*!< PORT3 OMR: PS4 (Bit 4) */ -#define PORT3_OMR_PS4_Msk \ - (0x10UL) /*!< PORT3 OMR: PS4 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PS5_Pos (5UL) /*!< PORT3 OMR: PS5 (Bit 5) */ -#define PORT3_OMR_PS5_Msk \ - (0x20UL) /*!< PORT3 OMR: PS5 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PS6_Pos (6UL) /*!< PORT3 OMR: PS6 (Bit 6) */ -#define PORT3_OMR_PS6_Msk \ - (0x40UL) /*!< PORT3 OMR: PS6 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PS7_Pos (7UL) /*!< PORT3 OMR: PS7 (Bit 7) */ -#define PORT3_OMR_PS7_Msk \ - (0x80UL) /*!< PORT3 OMR: PS7 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PS8_Pos (8UL) /*!< PORT3 OMR: PS8 (Bit 8) */ -#define PORT3_OMR_PS8_Msk \ - (0x100UL) /*!< PORT3 OMR: PS8 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PS9_Pos (9UL) /*!< PORT3 OMR: PS9 (Bit 9) */ -#define PORT3_OMR_PS9_Msk \ - (0x200UL) /*!< PORT3 OMR: PS9 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PS10_Pos \ - (10UL) /*!< PORT3 OMR: PS10 (Bit 10) */ -#define PORT3_OMR_PS10_Msk \ - (0x400UL) /*!< PORT3 OMR: PS10 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PS11_Pos \ - (11UL) /*!< PORT3 OMR: PS11 (Bit 11) */ -#define PORT3_OMR_PS11_Msk \ - (0x800UL) /*!< PORT3 OMR: PS11 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PS12_Pos \ - (12UL) /*!< PORT3 OMR: PS12 (Bit 12) */ -#define PORT3_OMR_PS12_Msk \ - (0x1000UL) /*!< PORT3 OMR: PS12 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PS13_Pos \ - (13UL) /*!< PORT3 OMR: PS13 (Bit 13) */ -#define PORT3_OMR_PS13_Msk \ - (0x2000UL) /*!< PORT3 OMR: PS13 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PS14_Pos \ - (14UL) /*!< PORT3 OMR: PS14 (Bit 14) */ -#define PORT3_OMR_PS14_Msk \ - (0x4000UL) /*!< PORT3 OMR: PS14 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PS15_Pos \ - (15UL) /*!< PORT3 OMR: PS15 (Bit 15) */ -#define PORT3_OMR_PS15_Msk \ - (0x8000UL) /*!< PORT3 OMR: PS15 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PR0_Pos (16UL) /*!< PORT3 OMR: PR0 (Bit 16) */ -#define PORT3_OMR_PR0_Msk \ - (0x10000UL) /*!< PORT3 OMR: PR0 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PR1_Pos (17UL) /*!< PORT3 OMR: PR1 (Bit 17) */ -#define PORT3_OMR_PR1_Msk \ - (0x20000UL) /*!< PORT3 OMR: PR1 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PR2_Pos (18UL) /*!< PORT3 OMR: PR2 (Bit 18) */ -#define PORT3_OMR_PR2_Msk \ - (0x40000UL) /*!< PORT3 OMR: PR2 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PR3_Pos (19UL) /*!< PORT3 OMR: PR3 (Bit 19) */ -#define PORT3_OMR_PR3_Msk \ - (0x80000UL) /*!< PORT3 OMR: PR3 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PR4_Pos (20UL) /*!< PORT3 OMR: PR4 (Bit 20) */ -#define PORT3_OMR_PR4_Msk \ - (0x100000UL) /*!< PORT3 OMR: PR4 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PR5_Pos (21UL) /*!< PORT3 OMR: PR5 (Bit 21) */ -#define PORT3_OMR_PR5_Msk \ - (0x200000UL) /*!< PORT3 OMR: PR5 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PR6_Pos (22UL) /*!< PORT3 OMR: PR6 (Bit 22) */ -#define PORT3_OMR_PR6_Msk \ - (0x400000UL) /*!< PORT3 OMR: PR6 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PR7_Pos (23UL) /*!< PORT3 OMR: PR7 (Bit 23) */ -#define PORT3_OMR_PR7_Msk \ - (0x800000UL) /*!< PORT3 OMR: PR7 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PR8_Pos (24UL) /*!< PORT3 OMR: PR8 (Bit 24) */ -#define PORT3_OMR_PR8_Msk \ - (0x1000000UL) /*!< PORT3 OMR: PR8 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PR9_Pos (25UL) /*!< PORT3 OMR: PR9 (Bit 25) */ -#define PORT3_OMR_PR9_Msk \ - (0x2000000UL) /*!< PORT3 OMR: PR9 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PR10_Pos \ - (26UL) /*!< PORT3 OMR: PR10 (Bit 26) */ -#define PORT3_OMR_PR10_Msk \ - (0x4000000UL) /*!< PORT3 OMR: PR10 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PR11_Pos \ - (27UL) /*!< PORT3 OMR: PR11 (Bit 27) */ -#define PORT3_OMR_PR11_Msk \ - (0x8000000UL) /*!< PORT3 OMR: PR11 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PR12_Pos \ - (28UL) /*!< PORT3 OMR: PR12 (Bit 28) */ -#define PORT3_OMR_PR12_Msk \ - (0x10000000UL) /*!< PORT3 OMR: PR12 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PR13_Pos \ - (29UL) /*!< PORT3 OMR: PR13 (Bit 29) */ -#define PORT3_OMR_PR13_Msk \ - (0x20000000UL) /*!< PORT3 OMR: PR13 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PR14_Pos \ - (30UL) /*!< PORT3 OMR: PR14 (Bit 30) */ -#define PORT3_OMR_PR14_Msk \ - (0x40000000UL) /*!< PORT3 OMR: PR14 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PR15_Pos \ - (31UL) /*!< PORT3 OMR: PR15 (Bit 31) */ -#define PORT3_OMR_PR15_Msk \ - (0x80000000UL) /*!< PORT3 OMR: PR15 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- PORT3_IOCR0 -------------------------------- */ -#define PORT3_IOCR0_PC0_Pos \ - (3UL) /*!< PORT3 IOCR0: PC0 (Bit 3) */ -#define PORT3_IOCR0_PC0_Msk \ - (0xf8UL) /*!< PORT3 IOCR0: PC0 (Bitfield-Mask: 0x1f) */ -#define PORT3_IOCR0_PC1_Pos \ - (11UL) /*!< PORT3 IOCR0: PC1 (Bit 11) */ -#define PORT3_IOCR0_PC1_Msk \ - (0xf800UL) /*!< PORT3 IOCR0: PC1 (Bitfield-Mask: 0x1f) */ -#define PORT3_IOCR0_PC2_Pos \ - (19UL) /*!< PORT3 IOCR0: PC2 (Bit 19) */ -#define PORT3_IOCR0_PC2_Msk \ - (0xf80000UL) /*!< PORT3 IOCR0: PC2 (Bitfield-Mask: 0x1f) */ -#define PORT3_IOCR0_PC3_Pos \ - (27UL) /*!< PORT3 IOCR0: PC3 (Bit 27) */ -#define PORT3_IOCR0_PC3_Msk \ - (0xf8000000UL) /*!< PORT3 IOCR0: PC3 (Bitfield-Mask: 0x1f) */ - -/* ---------------------------------- PORT3_IN ---------------------------------- */ -#define PORT3_IN_P0_Pos (0UL) /*!< PORT3 IN: P0 (Bit 0) */ -#define PORT3_IN_P0_Msk (0x1UL) /*!< PORT3 IN: P0 (Bitfield-Mask: 0x01) */ -#define PORT3_IN_P1_Pos (1UL) /*!< PORT3 IN: P1 (Bit 1) */ -#define PORT3_IN_P1_Msk (0x2UL) /*!< PORT3 IN: P1 (Bitfield-Mask: 0x01) */ -#define PORT3_IN_P2_Pos (2UL) /*!< PORT3 IN: P2 (Bit 2) */ -#define PORT3_IN_P2_Msk (0x4UL) /*!< PORT3 IN: P2 (Bitfield-Mask: 0x01) */ -#define PORT3_IN_P3_Pos (3UL) /*!< PORT3 IN: P3 (Bit 3) */ -#define PORT3_IN_P3_Msk (0x8UL) /*!< PORT3 IN: P3 (Bitfield-Mask: 0x01) */ -#define PORT3_IN_P4_Pos (4UL) /*!< PORT3 IN: P4 (Bit 4) */ -#define PORT3_IN_P4_Msk (0x10UL) /*!< PORT3 IN: P4 (Bitfield-Mask: 0x01) */ -#define PORT3_IN_P5_Pos (5UL) /*!< PORT3 IN: P5 (Bit 5) */ -#define PORT3_IN_P5_Msk (0x20UL) /*!< PORT3 IN: P5 (Bitfield-Mask: 0x01) */ -#define PORT3_IN_P6_Pos (6UL) /*!< PORT3 IN: P6 (Bit 6) */ -#define PORT3_IN_P6_Msk (0x40UL) /*!< PORT3 IN: P6 (Bitfield-Mask: 0x01) */ -#define PORT3_IN_P7_Pos (7UL) /*!< PORT3 IN: P7 (Bit 7) */ -#define PORT3_IN_P7_Msk (0x80UL) /*!< PORT3 IN: P7 (Bitfield-Mask: 0x01) */ -#define PORT3_IN_P8_Pos (8UL) /*!< PORT3 IN: P8 (Bit 8) */ -#define PORT3_IN_P8_Msk \ - (0x100UL) /*!< PORT3 IN: P8 (Bitfield-Mask: 0x01) */ -#define PORT3_IN_P9_Pos (9UL) /*!< PORT3 IN: P9 (Bit 9) */ -#define PORT3_IN_P9_Msk \ - (0x200UL) /*!< PORT3 IN: P9 (Bitfield-Mask: 0x01) */ -#define PORT3_IN_P10_Pos (10UL) /*!< PORT3 IN: P10 (Bit 10) */ -#define PORT3_IN_P10_Msk \ - (0x400UL) /*!< PORT3 IN: P10 (Bitfield-Mask: 0x01) */ -#define PORT3_IN_P11_Pos (11UL) /*!< PORT3 IN: P11 (Bit 11) */ -#define PORT3_IN_P11_Msk \ - (0x800UL) /*!< PORT3 IN: P11 (Bitfield-Mask: 0x01) */ -#define PORT3_IN_P12_Pos (12UL) /*!< PORT3 IN: P12 (Bit 12) */ -#define PORT3_IN_P12_Msk \ - (0x1000UL) /*!< PORT3 IN: P12 (Bitfield-Mask: 0x01) */ -#define PORT3_IN_P13_Pos (13UL) /*!< PORT3 IN: P13 (Bit 13) */ -#define PORT3_IN_P13_Msk \ - (0x2000UL) /*!< PORT3 IN: P13 (Bitfield-Mask: 0x01) */ -#define PORT3_IN_P14_Pos (14UL) /*!< PORT3 IN: P14 (Bit 14) */ -#define PORT3_IN_P14_Msk \ - (0x4000UL) /*!< PORT3 IN: P14 (Bitfield-Mask: 0x01) */ -#define PORT3_IN_P15_Pos (15UL) /*!< PORT3 IN: P15 (Bit 15) */ -#define PORT3_IN_P15_Msk \ - (0x8000UL) /*!< PORT3 IN: P15 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- PORT3_PDR0 --------------------------------- */ -#define PORT3_PDR0_PD0_Pos (0UL) /*!< PORT3 PDR0: PD0 (Bit 0) */ -#define PORT3_PDR0_PD0_Msk \ - (0x7UL) /*!< PORT3 PDR0: PD0 (Bitfield-Mask: 0x07) */ -#define PORT3_PDR0_PD1_Pos (4UL) /*!< PORT3 PDR0: PD1 (Bit 4) */ -#define PORT3_PDR0_PD1_Msk \ - (0x70UL) /*!< PORT3 PDR0: PD1 (Bitfield-Mask: 0x07) */ -#define PORT3_PDR0_PD2_Pos (8UL) /*!< PORT3 PDR0: PD2 (Bit 8) */ -#define PORT3_PDR0_PD2_Msk \ - (0x700UL) /*!< PORT3 PDR0: PD2 (Bitfield-Mask: 0x07) */ -#define PORT3_PDR0_PD3_Pos \ - (12UL) /*!< PORT3 PDR0: PD3 (Bit 12) */ -#define PORT3_PDR0_PD3_Msk \ - (0x7000UL) /*!< PORT3 PDR0: PD3 (Bitfield-Mask: 0x07) */ -#define PORT3_PDR0_PD4_Pos \ - (16UL) /*!< PORT3 PDR0: PD4 (Bit 16) */ -#define PORT3_PDR0_PD4_Msk \ - (0x70000UL) /*!< PORT3 PDR0: PD4 (Bitfield-Mask: 0x07) */ -#define PORT3_PDR0_PD5_Pos \ - (20UL) /*!< PORT3 PDR0: PD5 (Bit 20) */ -#define PORT3_PDR0_PD5_Msk \ - (0x700000UL) /*!< PORT3 PDR0: PD5 (Bitfield-Mask: 0x07) */ -#define PORT3_PDR0_PD6_Pos \ - (24UL) /*!< PORT3 PDR0: PD6 (Bit 24) */ -#define PORT3_PDR0_PD6_Msk \ - (0x7000000UL) /*!< PORT3 PDR0: PD6 (Bitfield-Mask: 0x07) */ -#define PORT3_PDR0_PD7_Pos \ - (28UL) /*!< PORT3 PDR0: PD7 (Bit 28) */ -#define PORT3_PDR0_PD7_Msk \ - (0x70000000UL) /*!< PORT3 PDR0: PD7 (Bitfield-Mask: 0x07) */ - -/* --------------------------------- PORT3_PDISC -------------------------------- */ -#define PORT3_PDISC_PDIS0_Pos \ - (0UL) /*!< PORT3 PDISC: PDIS0 (Bit 0) */ -#define PORT3_PDISC_PDIS0_Msk \ - (0x1UL) /*!< PORT3 PDISC: PDIS0 (Bitfield-Mask: 0x01) */ -#define PORT3_PDISC_PDIS1_Pos \ - (1UL) /*!< PORT3 PDISC: PDIS1 (Bit 1) */ -#define PORT3_PDISC_PDIS1_Msk \ - (0x2UL) /*!< PORT3 PDISC: PDIS1 (Bitfield-Mask: 0x01) */ -#define PORT3_PDISC_PDIS2_Pos \ - (2UL) /*!< PORT3 PDISC: PDIS2 (Bit 2) */ -#define PORT3_PDISC_PDIS2_Msk \ - (0x4UL) /*!< PORT3 PDISC: PDIS2 (Bitfield-Mask: 0x01) */ -#define PORT3_PDISC_PDIS3_Pos \ - (3UL) /*!< PORT3 PDISC: PDIS3 (Bit 3) */ -#define PORT3_PDISC_PDIS3_Msk \ - (0x8UL) /*!< PORT3 PDISC: PDIS3 (Bitfield-Mask: 0x01) */ -#define PORT3_PDISC_PDIS4_Pos \ - (4UL) /*!< PORT3 PDISC: PDIS4 (Bit 4) */ -#define PORT3_PDISC_PDIS4_Msk \ - (0x10UL) /*!< PORT3 PDISC: PDIS4 (Bitfield-Mask: 0x01) */ -#define PORT3_PDISC_PDIS5_Pos \ - (5UL) /*!< PORT3 PDISC: PDIS5 (Bit 5) */ -#define PORT3_PDISC_PDIS5_Msk \ - (0x20UL) /*!< PORT3 PDISC: PDIS5 (Bitfield-Mask: 0x01) */ -#define PORT3_PDISC_PDIS6_Pos \ - (6UL) /*!< PORT3 PDISC: PDIS6 (Bit 6) */ -#define PORT3_PDISC_PDIS6_Msk \ - (0x40UL) /*!< PORT3 PDISC: PDIS6 (Bitfield-Mask: 0x01) */ -#define PORT3_PDISC_PDIS7_Pos \ - (7UL) /*!< PORT3 PDISC: PDIS7 (Bit 7) */ -#define PORT3_PDISC_PDIS7_Msk \ - (0x80UL) /*!< PORT3 PDISC: PDIS7 (Bitfield-Mask: 0x01) */ -#define PORT3_PDISC_PDIS8_Pos \ - (8UL) /*!< PORT3 PDISC: PDIS8 (Bit 8) */ -#define PORT3_PDISC_PDIS8_Msk \ - (0x100UL) /*!< PORT3 PDISC: PDIS8 (Bitfield-Mask: 0x01) */ -#define PORT3_PDISC_PDIS9_Pos \ - (9UL) /*!< PORT3 PDISC: PDIS9 (Bit 9) */ -#define PORT3_PDISC_PDIS9_Msk \ - (0x200UL) /*!< PORT3 PDISC: PDIS9 (Bitfield-Mask: 0x01) */ -#define PORT3_PDISC_PDIS10_Pos \ - (10UL) /*!< PORT3 PDISC: PDIS10 (Bit 10) */ -#define PORT3_PDISC_PDIS10_Msk \ - (0x400UL) /*!< PORT3 PDISC: PDIS10 (Bitfield-Mask: 0x01) */ -#define PORT3_PDISC_PDIS11_Pos \ - (11UL) /*!< PORT3 PDISC: PDIS11 (Bit 11) */ -#define PORT3_PDISC_PDIS11_Msk \ - (0x800UL) /*!< PORT3 PDISC: PDIS11 (Bitfield-Mask: 0x01) */ -#define PORT3_PDISC_PDIS12_Pos \ - (12UL) /*!< PORT3 PDISC: PDIS12 (Bit 12) */ -#define PORT3_PDISC_PDIS12_Msk \ - (0x1000UL) /*!< PORT3 PDISC: PDIS12 (Bitfield-Mask: 0x01) */ -#define PORT3_PDISC_PDIS13_Pos \ - (13UL) /*!< PORT3 PDISC: PDIS13 (Bit 13) */ -#define PORT3_PDISC_PDIS13_Msk \ - (0x2000UL) /*!< PORT3 PDISC: PDIS13 (Bitfield-Mask: 0x01) */ -#define PORT3_PDISC_PDIS14_Pos \ - (14UL) /*!< PORT3 PDISC: PDIS14 (Bit 14) */ -#define PORT3_PDISC_PDIS14_Msk \ - (0x4000UL) /*!< PORT3 PDISC: PDIS14 (Bitfield-Mask: 0x01) */ -#define PORT3_PDISC_PDIS15_Pos \ - (15UL) /*!< PORT3 PDISC: PDIS15 (Bit 15) */ -#define PORT3_PDISC_PDIS15_Msk \ - (0x8000UL) /*!< PORT3 PDISC: PDIS15 (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- PORT3_PPS --------------------------------- */ -#define PORT3_PPS_PPS0_Pos (0UL) /*!< PORT3 PPS: PPS0 (Bit 0) */ -#define PORT3_PPS_PPS0_Msk \ - (0x1UL) /*!< PORT3 PPS: PPS0 (Bitfield-Mask: 0x01) */ -#define PORT3_PPS_PPS1_Pos (1UL) /*!< PORT3 PPS: PPS1 (Bit 1) */ -#define PORT3_PPS_PPS1_Msk \ - (0x2UL) /*!< PORT3 PPS: PPS1 (Bitfield-Mask: 0x01) */ -#define PORT3_PPS_PPS2_Pos (2UL) /*!< PORT3 PPS: PPS2 (Bit 2) */ -#define PORT3_PPS_PPS2_Msk \ - (0x4UL) /*!< PORT3 PPS: PPS2 (Bitfield-Mask: 0x01) */ -#define PORT3_PPS_PPS3_Pos (3UL) /*!< PORT3 PPS: PPS3 (Bit 3) */ -#define PORT3_PPS_PPS3_Msk \ - (0x8UL) /*!< PORT3 PPS: PPS3 (Bitfield-Mask: 0x01) */ -#define PORT3_PPS_PPS4_Pos (4UL) /*!< PORT3 PPS: PPS4 (Bit 4) */ -#define PORT3_PPS_PPS4_Msk \ - (0x10UL) /*!< PORT3 PPS: PPS4 (Bitfield-Mask: 0x01) */ -#define PORT3_PPS_PPS5_Pos (5UL) /*!< PORT3 PPS: PPS5 (Bit 5) */ -#define PORT3_PPS_PPS5_Msk \ - (0x20UL) /*!< PORT3 PPS: PPS5 (Bitfield-Mask: 0x01) */ -#define PORT3_PPS_PPS6_Pos (6UL) /*!< PORT3 PPS: PPS6 (Bit 6) */ -#define PORT3_PPS_PPS6_Msk \ - (0x40UL) /*!< PORT3 PPS: PPS6 (Bitfield-Mask: 0x01) */ -#define PORT3_PPS_PPS7_Pos (7UL) /*!< PORT3 PPS: PPS7 (Bit 7) */ -#define PORT3_PPS_PPS7_Msk \ - (0x80UL) /*!< PORT3 PPS: PPS7 (Bitfield-Mask: 0x01) */ -#define PORT3_PPS_PPS8_Pos (8UL) /*!< PORT3 PPS: PPS8 (Bit 8) */ -#define PORT3_PPS_PPS8_Msk \ - (0x100UL) /*!< PORT3 PPS: PPS8 (Bitfield-Mask: 0x01) */ -#define PORT3_PPS_PPS9_Pos (9UL) /*!< PORT3 PPS: PPS9 (Bit 9) */ -#define PORT3_PPS_PPS9_Msk \ - (0x200UL) /*!< PORT3 PPS: PPS9 (Bitfield-Mask: 0x01) */ -#define PORT3_PPS_PPS10_Pos \ - (10UL) /*!< PORT3 PPS: PPS10 (Bit 10) */ -#define PORT3_PPS_PPS10_Msk \ - (0x400UL) /*!< PORT3 PPS: PPS10 (Bitfield-Mask: 0x01) */ -#define PORT3_PPS_PPS11_Pos \ - (11UL) /*!< PORT3 PPS: PPS11 (Bit 11) */ -#define PORT3_PPS_PPS11_Msk \ - (0x800UL) /*!< PORT3 PPS: PPS11 (Bitfield-Mask: 0x01) */ -#define PORT3_PPS_PPS12_Pos \ - (12UL) /*!< PORT3 PPS: PPS12 (Bit 12) */ -#define PORT3_PPS_PPS12_Msk \ - (0x1000UL) /*!< PORT3 PPS: PPS12 (Bitfield-Mask: 0x01) */ -#define PORT3_PPS_PPS13_Pos \ - (13UL) /*!< PORT3 PPS: PPS13 (Bit 13) */ -#define PORT3_PPS_PPS13_Msk \ - (0x2000UL) /*!< PORT3 PPS: PPS13 (Bitfield-Mask: 0x01) */ -#define PORT3_PPS_PPS14_Pos \ - (14UL) /*!< PORT3 PPS: PPS14 (Bit 14) */ -#define PORT3_PPS_PPS14_Msk \ - (0x4000UL) /*!< PORT3 PPS: PPS14 (Bitfield-Mask: 0x01) */ -#define PORT3_PPS_PPS15_Pos \ - (15UL) /*!< PORT3 PPS: PPS15 (Bit 15) */ -#define PORT3_PPS_PPS15_Msk \ - (0x8000UL) /*!< PORT3 PPS: PPS15 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- PORT3_HWSEL -------------------------------- */ -#define PORT3_HWSEL_HW0_Pos \ - (0UL) /*!< PORT3 HWSEL: HW0 (Bit 0) */ -#define PORT3_HWSEL_HW0_Msk \ - (0x3UL) /*!< PORT3 HWSEL: HW0 (Bitfield-Mask: 0x03) */ -#define PORT3_HWSEL_HW1_Pos \ - (2UL) /*!< PORT3 HWSEL: HW1 (Bit 2) */ -#define PORT3_HWSEL_HW1_Msk \ - (0xcUL) /*!< PORT3 HWSEL: HW1 (Bitfield-Mask: 0x03) */ -#define PORT3_HWSEL_HW2_Pos \ - (4UL) /*!< PORT3 HWSEL: HW2 (Bit 4) */ -#define PORT3_HWSEL_HW2_Msk \ - (0x30UL) /*!< PORT3 HWSEL: HW2 (Bitfield-Mask: 0x03) */ -#define PORT3_HWSEL_HW3_Pos \ - (6UL) /*!< PORT3 HWSEL: HW3 (Bit 6) */ -#define PORT3_HWSEL_HW3_Msk \ - (0xc0UL) /*!< PORT3 HWSEL: HW3 (Bitfield-Mask: 0x03) */ -#define PORT3_HWSEL_HW4_Pos \ - (8UL) /*!< PORT3 HWSEL: HW4 (Bit 8) */ -#define PORT3_HWSEL_HW4_Msk \ - (0x300UL) /*!< PORT3 HWSEL: HW4 (Bitfield-Mask: 0x03) */ -#define PORT3_HWSEL_HW5_Pos \ - (10UL) /*!< PORT3 HWSEL: HW5 (Bit 10) */ -#define PORT3_HWSEL_HW5_Msk \ - (0xc00UL) /*!< PORT3 HWSEL: HW5 (Bitfield-Mask: 0x03) */ -#define PORT3_HWSEL_HW6_Pos \ - (12UL) /*!< PORT3 HWSEL: HW6 (Bit 12) */ -#define PORT3_HWSEL_HW6_Msk \ - (0x3000UL) /*!< PORT3 HWSEL: HW6 (Bitfield-Mask: 0x03) */ -#define PORT3_HWSEL_HW7_Pos \ - (14UL) /*!< PORT3 HWSEL: HW7 (Bit 14) */ -#define PORT3_HWSEL_HW7_Msk \ - (0xc000UL) /*!< PORT3 HWSEL: HW7 (Bitfield-Mask: 0x03) */ -#define PORT3_HWSEL_HW8_Pos \ - (16UL) /*!< PORT3 HWSEL: HW8 (Bit 16) */ -#define PORT3_HWSEL_HW8_Msk \ - (0x30000UL) /*!< PORT3 HWSEL: HW8 (Bitfield-Mask: 0x03) */ -#define PORT3_HWSEL_HW9_Pos \ - (18UL) /*!< PORT3 HWSEL: HW9 (Bit 18) */ -#define PORT3_HWSEL_HW9_Msk \ - (0xc0000UL) /*!< PORT3 HWSEL: HW9 (Bitfield-Mask: 0x03) */ -#define PORT3_HWSEL_HW10_Pos \ - (20UL) /*!< PORT3 HWSEL: HW10 (Bit 20) */ -#define PORT3_HWSEL_HW10_Msk \ - (0x300000UL) /*!< PORT3 HWSEL: HW10 (Bitfield-Mask: 0x03) */ -#define PORT3_HWSEL_HW11_Pos \ - (22UL) /*!< PORT3 HWSEL: HW11 (Bit 22) */ -#define PORT3_HWSEL_HW11_Msk \ - (0xc00000UL) /*!< PORT3 HWSEL: HW11 (Bitfield-Mask: 0x03) */ -#define PORT3_HWSEL_HW12_Pos \ - (24UL) /*!< PORT3 HWSEL: HW12 (Bit 24) */ -#define PORT3_HWSEL_HW12_Msk \ - (0x3000000UL) /*!< PORT3 HWSEL: HW12 (Bitfield-Mask: 0x03) */ -#define PORT3_HWSEL_HW13_Pos \ - (26UL) /*!< PORT3 HWSEL: HW13 (Bit 26) */ -#define PORT3_HWSEL_HW13_Msk \ - (0xc000000UL) /*!< PORT3 HWSEL: HW13 (Bitfield-Mask: 0x03) */ -#define PORT3_HWSEL_HW14_Pos \ - (28UL) /*!< PORT3 HWSEL: HW14 (Bit 28) */ -#define PORT3_HWSEL_HW14_Msk \ - (0x30000000UL) /*!< PORT3 HWSEL: HW14 (Bitfield-Mask: 0x03) */ -#define PORT3_HWSEL_HW15_Pos \ - (30UL) /*!< PORT3 HWSEL: HW15 (Bit 30) */ -#define PORT3_HWSEL_HW15_Msk \ - (0xc0000000UL) /*!< PORT3 HWSEL: HW15 (Bitfield-Mask: 0x03) */ - -/* ================================================================================ */ -/* ================ struct 'PORT14' Position & Mask ================ */ -/* ================================================================================ */ - -/* --------------------------------- PORT14_OUT --------------------------------- */ -#define PORT14_OUT_P0_Pos (0UL) /*!< PORT14 OUT: P0 (Bit 0) */ -#define PORT14_OUT_P0_Msk \ - (0x1UL) /*!< PORT14 OUT: P0 (Bitfield-Mask: 0x01) */ -#define PORT14_OUT_P1_Pos (1UL) /*!< PORT14 OUT: P1 (Bit 1) */ -#define PORT14_OUT_P1_Msk \ - (0x2UL) /*!< PORT14 OUT: P1 (Bitfield-Mask: 0x01) */ -#define PORT14_OUT_P2_Pos (2UL) /*!< PORT14 OUT: P2 (Bit 2) */ -#define PORT14_OUT_P2_Msk \ - (0x4UL) /*!< PORT14 OUT: P2 (Bitfield-Mask: 0x01) */ -#define PORT14_OUT_P3_Pos (3UL) /*!< PORT14 OUT: P3 (Bit 3) */ -#define PORT14_OUT_P3_Msk \ - (0x8UL) /*!< PORT14 OUT: P3 (Bitfield-Mask: 0x01) */ -#define PORT14_OUT_P4_Pos (4UL) /*!< PORT14 OUT: P4 (Bit 4) */ -#define PORT14_OUT_P4_Msk \ - (0x10UL) /*!< PORT14 OUT: P4 (Bitfield-Mask: 0x01) */ -#define PORT14_OUT_P5_Pos (5UL) /*!< PORT14 OUT: P5 (Bit 5) */ -#define PORT14_OUT_P5_Msk \ - (0x20UL) /*!< PORT14 OUT: P5 (Bitfield-Mask: 0x01) */ -#define PORT14_OUT_P6_Pos (6UL) /*!< PORT14 OUT: P6 (Bit 6) */ -#define PORT14_OUT_P6_Msk \ - (0x40UL) /*!< PORT14 OUT: P6 (Bitfield-Mask: 0x01) */ -#define PORT14_OUT_P7_Pos (7UL) /*!< PORT14 OUT: P7 (Bit 7) */ -#define PORT14_OUT_P7_Msk \ - (0x80UL) /*!< PORT14 OUT: P7 (Bitfield-Mask: 0x01) */ -#define PORT14_OUT_P8_Pos (8UL) /*!< PORT14 OUT: P8 (Bit 8) */ -#define PORT14_OUT_P8_Msk \ - (0x100UL) /*!< PORT14 OUT: P8 (Bitfield-Mask: 0x01) */ -#define PORT14_OUT_P9_Pos (9UL) /*!< PORT14 OUT: P9 (Bit 9) */ -#define PORT14_OUT_P9_Msk \ - (0x200UL) /*!< PORT14 OUT: P9 (Bitfield-Mask: 0x01) */ -#define PORT14_OUT_P10_Pos \ - (10UL) /*!< PORT14 OUT: P10 (Bit 10) */ -#define PORT14_OUT_P10_Msk \ - (0x400UL) /*!< PORT14 OUT: P10 (Bitfield-Mask: 0x01) */ -#define PORT14_OUT_P11_Pos \ - (11UL) /*!< PORT14 OUT: P11 (Bit 11) */ -#define PORT14_OUT_P11_Msk \ - (0x800UL) /*!< PORT14 OUT: P11 (Bitfield-Mask: 0x01) */ -#define PORT14_OUT_P12_Pos \ - (12UL) /*!< PORT14 OUT: P12 (Bit 12) */ -#define PORT14_OUT_P12_Msk \ - (0x1000UL) /*!< PORT14 OUT: P12 (Bitfield-Mask: 0x01) */ -#define PORT14_OUT_P13_Pos \ - (13UL) /*!< PORT14 OUT: P13 (Bit 13) */ -#define PORT14_OUT_P13_Msk \ - (0x2000UL) /*!< PORT14 OUT: P13 (Bitfield-Mask: 0x01) */ -#define PORT14_OUT_P14_Pos \ - (14UL) /*!< PORT14 OUT: P14 (Bit 14) */ -#define PORT14_OUT_P14_Msk \ - (0x4000UL) /*!< PORT14 OUT: P14 (Bitfield-Mask: 0x01) */ -#define PORT14_OUT_P15_Pos \ - (15UL) /*!< PORT14 OUT: P15 (Bit 15) */ -#define PORT14_OUT_P15_Msk \ - (0x8000UL) /*!< PORT14 OUT: P15 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- PORT14_OMR --------------------------------- */ -#define PORT14_OMR_PS0_Pos (0UL) /*!< PORT14 OMR: PS0 (Bit 0) */ -#define PORT14_OMR_PS0_Msk \ - (0x1UL) /*!< PORT14 OMR: PS0 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PS1_Pos (1UL) /*!< PORT14 OMR: PS1 (Bit 1) */ -#define PORT14_OMR_PS1_Msk \ - (0x2UL) /*!< PORT14 OMR: PS1 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PS2_Pos (2UL) /*!< PORT14 OMR: PS2 (Bit 2) */ -#define PORT14_OMR_PS2_Msk \ - (0x4UL) /*!< PORT14 OMR: PS2 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PS3_Pos (3UL) /*!< PORT14 OMR: PS3 (Bit 3) */ -#define PORT14_OMR_PS3_Msk \ - (0x8UL) /*!< PORT14 OMR: PS3 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PS4_Pos (4UL) /*!< PORT14 OMR: PS4 (Bit 4) */ -#define PORT14_OMR_PS4_Msk \ - (0x10UL) /*!< PORT14 OMR: PS4 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PS5_Pos (5UL) /*!< PORT14 OMR: PS5 (Bit 5) */ -#define PORT14_OMR_PS5_Msk \ - (0x20UL) /*!< PORT14 OMR: PS5 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PS6_Pos (6UL) /*!< PORT14 OMR: PS6 (Bit 6) */ -#define PORT14_OMR_PS6_Msk \ - (0x40UL) /*!< PORT14 OMR: PS6 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PS7_Pos (7UL) /*!< PORT14 OMR: PS7 (Bit 7) */ -#define PORT14_OMR_PS7_Msk \ - (0x80UL) /*!< PORT14 OMR: PS7 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PS8_Pos (8UL) /*!< PORT14 OMR: PS8 (Bit 8) */ -#define PORT14_OMR_PS8_Msk \ - (0x100UL) /*!< PORT14 OMR: PS8 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PS9_Pos (9UL) /*!< PORT14 OMR: PS9 (Bit 9) */ -#define PORT14_OMR_PS9_Msk \ - (0x200UL) /*!< PORT14 OMR: PS9 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PS10_Pos \ - (10UL) /*!< PORT14 OMR: PS10 (Bit 10) */ -#define PORT14_OMR_PS10_Msk \ - (0x400UL) /*!< PORT14 OMR: PS10 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PS11_Pos \ - (11UL) /*!< PORT14 OMR: PS11 (Bit 11) */ -#define PORT14_OMR_PS11_Msk \ - (0x800UL) /*!< PORT14 OMR: PS11 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PS12_Pos \ - (12UL) /*!< PORT14 OMR: PS12 (Bit 12) */ -#define PORT14_OMR_PS12_Msk \ - (0x1000UL) /*!< PORT14 OMR: PS12 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PS13_Pos \ - (13UL) /*!< PORT14 OMR: PS13 (Bit 13) */ -#define PORT14_OMR_PS13_Msk \ - (0x2000UL) /*!< PORT14 OMR: PS13 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PS14_Pos \ - (14UL) /*!< PORT14 OMR: PS14 (Bit 14) */ -#define PORT14_OMR_PS14_Msk \ - (0x4000UL) /*!< PORT14 OMR: PS14 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PS15_Pos \ - (15UL) /*!< PORT14 OMR: PS15 (Bit 15) */ -#define PORT14_OMR_PS15_Msk \ - (0x8000UL) /*!< PORT14 OMR: PS15 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PR0_Pos \ - (16UL) /*!< PORT14 OMR: PR0 (Bit 16) */ -#define PORT14_OMR_PR0_Msk \ - (0x10000UL) /*!< PORT14 OMR: PR0 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PR1_Pos \ - (17UL) /*!< PORT14 OMR: PR1 (Bit 17) */ -#define PORT14_OMR_PR1_Msk \ - (0x20000UL) /*!< PORT14 OMR: PR1 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PR2_Pos \ - (18UL) /*!< PORT14 OMR: PR2 (Bit 18) */ -#define PORT14_OMR_PR2_Msk \ - (0x40000UL) /*!< PORT14 OMR: PR2 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PR3_Pos \ - (19UL) /*!< PORT14 OMR: PR3 (Bit 19) */ -#define PORT14_OMR_PR3_Msk \ - (0x80000UL) /*!< PORT14 OMR: PR3 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PR4_Pos \ - (20UL) /*!< PORT14 OMR: PR4 (Bit 20) */ -#define PORT14_OMR_PR4_Msk \ - (0x100000UL) /*!< PORT14 OMR: PR4 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PR5_Pos \ - (21UL) /*!< PORT14 OMR: PR5 (Bit 21) */ -#define PORT14_OMR_PR5_Msk \ - (0x200000UL) /*!< PORT14 OMR: PR5 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PR6_Pos \ - (22UL) /*!< PORT14 OMR: PR6 (Bit 22) */ -#define PORT14_OMR_PR6_Msk \ - (0x400000UL) /*!< PORT14 OMR: PR6 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PR7_Pos \ - (23UL) /*!< PORT14 OMR: PR7 (Bit 23) */ -#define PORT14_OMR_PR7_Msk \ - (0x800000UL) /*!< PORT14 OMR: PR7 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PR8_Pos \ - (24UL) /*!< PORT14 OMR: PR8 (Bit 24) */ -#define PORT14_OMR_PR8_Msk \ - (0x1000000UL) /*!< PORT14 OMR: PR8 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PR9_Pos \ - (25UL) /*!< PORT14 OMR: PR9 (Bit 25) */ -#define PORT14_OMR_PR9_Msk \ - (0x2000000UL) /*!< PORT14 OMR: PR9 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PR10_Pos \ - (26UL) /*!< PORT14 OMR: PR10 (Bit 26) */ -#define PORT14_OMR_PR10_Msk \ - (0x4000000UL) /*!< PORT14 OMR: PR10 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PR11_Pos \ - (27UL) /*!< PORT14 OMR: PR11 (Bit 27) */ -#define PORT14_OMR_PR11_Msk \ - (0x8000000UL) /*!< PORT14 OMR: PR11 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PR12_Pos \ - (28UL) /*!< PORT14 OMR: PR12 (Bit 28) */ -#define PORT14_OMR_PR12_Msk \ - (0x10000000UL) /*!< PORT14 OMR: PR12 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PR13_Pos \ - (29UL) /*!< PORT14 OMR: PR13 (Bit 29) */ -#define PORT14_OMR_PR13_Msk \ - (0x20000000UL) /*!< PORT14 OMR: PR13 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PR14_Pos \ - (30UL) /*!< PORT14 OMR: PR14 (Bit 30) */ -#define PORT14_OMR_PR14_Msk \ - (0x40000000UL) /*!< PORT14 OMR: PR14 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PR15_Pos \ - (31UL) /*!< PORT14 OMR: PR15 (Bit 31) */ -#define PORT14_OMR_PR15_Msk \ - (0x80000000UL) /*!< PORT14 OMR: PR15 (Bitfield-Mask: 0x01) */ - -/* -------------------------------- PORT14_IOCR0 -------------------------------- */ -#define PORT14_IOCR0_PC0_Pos \ - (3UL) /*!< PORT14 IOCR0: PC0 (Bit 3) */ -#define PORT14_IOCR0_PC0_Msk \ - (0xf8UL) /*!< PORT14 IOCR0: PC0 (Bitfield-Mask: 0x1f) */ -#define PORT14_IOCR0_PC1_Pos \ - (11UL) /*!< PORT14 IOCR0: PC1 (Bit 11) */ -#define PORT14_IOCR0_PC1_Msk \ - (0xf800UL) /*!< PORT14 IOCR0: PC1 (Bitfield-Mask: 0x1f) */ -#define PORT14_IOCR0_PC2_Pos \ - (19UL) /*!< PORT14 IOCR0: PC2 (Bit 19) */ -#define PORT14_IOCR0_PC2_Msk \ - (0xf80000UL) /*!< PORT14 IOCR0: PC2 (Bitfield-Mask: 0x1f) */ -#define PORT14_IOCR0_PC3_Pos \ - (27UL) /*!< PORT14 IOCR0: PC3 (Bit 27) */ -#define PORT14_IOCR0_PC3_Msk \ - (0xf8000000UL) /*!< PORT14 IOCR0: PC3 (Bitfield-Mask: 0x1f) */ - -/* -------------------------------- PORT14_IOCR4 -------------------------------- */ -#define PORT14_IOCR4_PC4_Pos \ - (3UL) /*!< PORT14 IOCR4: PC4 (Bit 3) */ -#define PORT14_IOCR4_PC4_Msk \ - (0xf8UL) /*!< PORT14 IOCR4: PC4 (Bitfield-Mask: 0x1f) */ -#define PORT14_IOCR4_PC5_Pos \ - (11UL) /*!< PORT14 IOCR4: PC5 (Bit 11) */ -#define PORT14_IOCR4_PC5_Msk \ - (0xf800UL) /*!< PORT14 IOCR4: PC5 (Bitfield-Mask: 0x1f) */ -#define PORT14_IOCR4_PC6_Pos \ - (19UL) /*!< PORT14 IOCR4: PC6 (Bit 19) */ -#define PORT14_IOCR4_PC6_Msk \ - (0xf80000UL) /*!< PORT14 IOCR4: PC6 (Bitfield-Mask: 0x1f) */ -#define PORT14_IOCR4_PC7_Pos \ - (27UL) /*!< PORT14 IOCR4: PC7 (Bit 27) */ -#define PORT14_IOCR4_PC7_Msk \ - (0xf8000000UL) /*!< PORT14 IOCR4: PC7 (Bitfield-Mask: 0x1f) */ - -/* -------------------------------- PORT14_IOCR8 -------------------------------- */ -#define PORT14_IOCR8_PC8_Pos \ - (3UL) /*!< PORT14 IOCR8: PC8 (Bit 3) */ -#define PORT14_IOCR8_PC8_Msk \ - (0xf8UL) /*!< PORT14 IOCR8: PC8 (Bitfield-Mask: 0x1f) */ -#define PORT14_IOCR8_PC9_Pos \ - (11UL) /*!< PORT14 IOCR8: PC9 (Bit 11) */ -#define PORT14_IOCR8_PC9_Msk \ - (0xf800UL) /*!< PORT14 IOCR8: PC9 (Bitfield-Mask: 0x1f) */ -#define PORT14_IOCR8_PC10_Pos \ - (19UL) /*!< PORT14 IOCR8: PC10 (Bit 19) */ -#define PORT14_IOCR8_PC10_Msk \ - (0xf80000UL) /*!< PORT14 IOCR8: PC10 (Bitfield-Mask: 0x1f) */ -#define PORT14_IOCR8_PC11_Pos \ - (27UL) /*!< PORT14 IOCR8: PC11 (Bit 27) */ -#define PORT14_IOCR8_PC11_Msk \ - (0xf8000000UL) /*!< PORT14 IOCR8: PC11 (Bitfield-Mask: 0x1f) */ - -/* -------------------------------- PORT14_IOCR12 ------------------------------- */ -#define PORT14_IOCR12_PC12_Pos \ - (3UL) /*!< PORT14 IOCR12: PC12 (Bit 3) */ -#define PORT14_IOCR12_PC12_Msk \ - (0xf8UL) /*!< PORT14 IOCR12: PC12 (Bitfield-Mask: 0x1f) */ -#define PORT14_IOCR12_PC13_Pos \ - (11UL) /*!< PORT14 IOCR12: PC13 (Bit 11) */ -#define PORT14_IOCR12_PC13_Msk \ - (0xf800UL) /*!< PORT14 IOCR12: PC13 (Bitfield-Mask: 0x1f) */ -#define PORT14_IOCR12_PC14_Pos \ - (19UL) /*!< PORT14 IOCR12: PC14 (Bit 19) */ -#define PORT14_IOCR12_PC14_Msk \ - (0xf80000UL) /*!< PORT14 IOCR12: PC14 (Bitfield-Mask: 0x1f) */ -#define PORT14_IOCR12_PC15_Pos \ - (27UL) /*!< PORT14 IOCR12: PC15 (Bit 27) */ -#define PORT14_IOCR12_PC15_Msk \ - (0xf8000000UL) /*!< PORT14 IOCR12: PC15 (Bitfield-Mask: 0x1f) */ - -/* ---------------------------------- PORT14_IN --------------------------------- */ -#define PORT14_IN_P0_Pos (0UL) /*!< PORT14 IN: P0 (Bit 0) */ -#define PORT14_IN_P0_Msk (0x1UL) /*!< PORT14 IN: P0 (Bitfield-Mask: 0x01) */ -#define PORT14_IN_P1_Pos (1UL) /*!< PORT14 IN: P1 (Bit 1) */ -#define PORT14_IN_P1_Msk (0x2UL) /*!< PORT14 IN: P1 (Bitfield-Mask: 0x01) */ -#define PORT14_IN_P2_Pos (2UL) /*!< PORT14 IN: P2 (Bit 2) */ -#define PORT14_IN_P2_Msk (0x4UL) /*!< PORT14 IN: P2 (Bitfield-Mask: 0x01) */ -#define PORT14_IN_P3_Pos (3UL) /*!< PORT14 IN: P3 (Bit 3) */ -#define PORT14_IN_P3_Msk (0x8UL) /*!< PORT14 IN: P3 (Bitfield-Mask: 0x01) */ -#define PORT14_IN_P4_Pos (4UL) /*!< PORT14 IN: P4 (Bit 4) */ -#define PORT14_IN_P4_Msk \ - (0x10UL) /*!< PORT14 IN: P4 (Bitfield-Mask: 0x01) */ -#define PORT14_IN_P5_Pos (5UL) /*!< PORT14 IN: P5 (Bit 5) */ -#define PORT14_IN_P5_Msk \ - (0x20UL) /*!< PORT14 IN: P5 (Bitfield-Mask: 0x01) */ -#define PORT14_IN_P6_Pos (6UL) /*!< PORT14 IN: P6 (Bit 6) */ -#define PORT14_IN_P6_Msk \ - (0x40UL) /*!< PORT14 IN: P6 (Bitfield-Mask: 0x01) */ -#define PORT14_IN_P7_Pos (7UL) /*!< PORT14 IN: P7 (Bit 7) */ -#define PORT14_IN_P7_Msk \ - (0x80UL) /*!< PORT14 IN: P7 (Bitfield-Mask: 0x01) */ -#define PORT14_IN_P8_Pos (8UL) /*!< PORT14 IN: P8 (Bit 8) */ -#define PORT14_IN_P8_Msk \ - (0x100UL) /*!< PORT14 IN: P8 (Bitfield-Mask: 0x01) */ -#define PORT14_IN_P9_Pos (9UL) /*!< PORT14 IN: P9 (Bit 9) */ -#define PORT14_IN_P9_Msk \ - (0x200UL) /*!< PORT14 IN: P9 (Bitfield-Mask: 0x01) */ -#define PORT14_IN_P10_Pos (10UL) /*!< PORT14 IN: P10 (Bit 10) */ -#define PORT14_IN_P10_Msk \ - (0x400UL) /*!< PORT14 IN: P10 (Bitfield-Mask: 0x01) */ -#define PORT14_IN_P11_Pos (11UL) /*!< PORT14 IN: P11 (Bit 11) */ -#define PORT14_IN_P11_Msk \ - (0x800UL) /*!< PORT14 IN: P11 (Bitfield-Mask: 0x01) */ -#define PORT14_IN_P12_Pos (12UL) /*!< PORT14 IN: P12 (Bit 12) */ -#define PORT14_IN_P12_Msk \ - (0x1000UL) /*!< PORT14 IN: P12 (Bitfield-Mask: 0x01) */ -#define PORT14_IN_P13_Pos (13UL) /*!< PORT14 IN: P13 (Bit 13) */ -#define PORT14_IN_P13_Msk \ - (0x2000UL) /*!< PORT14 IN: P13 (Bitfield-Mask: 0x01) */ -#define PORT14_IN_P14_Pos (14UL) /*!< PORT14 IN: P14 (Bit 14) */ -#define PORT14_IN_P14_Msk \ - (0x4000UL) /*!< PORT14 IN: P14 (Bitfield-Mask: 0x01) */ -#define PORT14_IN_P15_Pos (15UL) /*!< PORT14 IN: P15 (Bit 15) */ -#define PORT14_IN_P15_Msk \ - (0x8000UL) /*!< PORT14 IN: P15 (Bitfield-Mask: 0x01) */ - -/* -------------------------------- PORT14_PDISC -------------------------------- */ -#define PORT14_PDISC_PDIS0_Pos \ - (0UL) /*!< PORT14 PDISC: PDIS0 (Bit 0) */ -#define PORT14_PDISC_PDIS0_Msk \ - (0x1UL) /*!< PORT14 PDISC: PDIS0 (Bitfield-Mask: 0x01) */ -#define PORT14_PDISC_PDIS1_Pos \ - (1UL) /*!< PORT14 PDISC: PDIS1 (Bit 1) */ -#define PORT14_PDISC_PDIS1_Msk \ - (0x2UL) /*!< PORT14 PDISC: PDIS1 (Bitfield-Mask: 0x01) */ -#define PORT14_PDISC_PDIS2_Pos \ - (2UL) /*!< PORT14 PDISC: PDIS2 (Bit 2) */ -#define PORT14_PDISC_PDIS2_Msk \ - (0x4UL) /*!< PORT14 PDISC: PDIS2 (Bitfield-Mask: 0x01) */ -#define PORT14_PDISC_PDIS3_Pos \ - (3UL) /*!< PORT14 PDISC: PDIS3 (Bit 3) */ -#define PORT14_PDISC_PDIS3_Msk \ - (0x8UL) /*!< PORT14 PDISC: PDIS3 (Bitfield-Mask: 0x01) */ -#define PORT14_PDISC_PDIS4_Pos \ - (4UL) /*!< PORT14 PDISC: PDIS4 (Bit 4) */ -#define PORT14_PDISC_PDIS4_Msk \ - (0x10UL) /*!< PORT14 PDISC: PDIS4 (Bitfield-Mask: 0x01) */ -#define PORT14_PDISC_PDIS5_Pos \ - (5UL) /*!< PORT14 PDISC: PDIS5 (Bit 5) */ -#define PORT14_PDISC_PDIS5_Msk \ - (0x20UL) /*!< PORT14 PDISC: PDIS5 (Bitfield-Mask: 0x01) */ -#define PORT14_PDISC_PDIS6_Pos \ - (6UL) /*!< PORT14 PDISC: PDIS6 (Bit 6) */ -#define PORT14_PDISC_PDIS6_Msk \ - (0x40UL) /*!< PORT14 PDISC: PDIS6 (Bitfield-Mask: 0x01) */ -#define PORT14_PDISC_PDIS7_Pos \ - (7UL) /*!< PORT14 PDISC: PDIS7 (Bit 7) */ -#define PORT14_PDISC_PDIS7_Msk \ - (0x80UL) /*!< PORT14 PDISC: PDIS7 (Bitfield-Mask: 0x01) */ -#define PORT14_PDISC_PDIS8_Pos \ - (8UL) /*!< PORT14 PDISC: PDIS8 (Bit 8) */ -#define PORT14_PDISC_PDIS8_Msk \ - (0x100UL) /*!< PORT14 PDISC: PDIS8 (Bitfield-Mask: 0x01) */ -#define PORT14_PDISC_PDIS9_Pos \ - (9UL) /*!< PORT14 PDISC: PDIS9 (Bit 9) */ -#define PORT14_PDISC_PDIS9_Msk \ - (0x200UL) /*!< PORT14 PDISC: PDIS9 (Bitfield-Mask: 0x01) */ -#define PORT14_PDISC_PDIS10_Pos \ - (10UL) /*!< PORT14 PDISC: PDIS10 (Bit 10) */ -#define PORT14_PDISC_PDIS10_Msk \ - (0x400UL) /*!< PORT14 PDISC: PDIS10 (Bitfield-Mask: 0x01) */ -#define PORT14_PDISC_PDIS11_Pos \ - (11UL) /*!< PORT14 PDISC: PDIS11 (Bit 11) */ -#define PORT14_PDISC_PDIS11_Msk \ - (0x800UL) /*!< PORT14 PDISC: PDIS11 (Bitfield-Mask: 0x01) */ -#define PORT14_PDISC_PDIS12_Pos \ - (12UL) /*!< PORT14 PDISC: PDIS12 (Bit 12) */ -#define PORT14_PDISC_PDIS12_Msk \ - (0x1000UL) /*!< PORT14 PDISC: PDIS12 (Bitfield-Mask: 0x01) */ -#define PORT14_PDISC_PDIS13_Pos \ - (13UL) /*!< PORT14 PDISC: PDIS13 (Bit 13) */ -#define PORT14_PDISC_PDIS13_Msk \ - (0x2000UL) /*!< PORT14 PDISC: PDIS13 (Bitfield-Mask: 0x01) */ -#define PORT14_PDISC_PDIS14_Pos \ - (14UL) /*!< PORT14 PDISC: PDIS14 (Bit 14) */ -#define PORT14_PDISC_PDIS14_Msk \ - (0x4000UL) /*!< PORT14 PDISC: PDIS14 (Bitfield-Mask: 0x01) */ -#define PORT14_PDISC_PDIS15_Pos \ - (15UL) /*!< PORT14 PDISC: PDIS15 (Bit 15) */ -#define PORT14_PDISC_PDIS15_Msk \ - (0x8000UL) /*!< PORT14 PDISC: PDIS15 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- PORT14_PPS --------------------------------- */ -#define PORT14_PPS_PPS0_Pos \ - (0UL) /*!< PORT14 PPS: PPS0 (Bit 0) */ -#define PORT14_PPS_PPS0_Msk \ - (0x1UL) /*!< PORT14 PPS: PPS0 (Bitfield-Mask: 0x01) */ -#define PORT14_PPS_PPS1_Pos \ - (1UL) /*!< PORT14 PPS: PPS1 (Bit 1) */ -#define PORT14_PPS_PPS1_Msk \ - (0x2UL) /*!< PORT14 PPS: PPS1 (Bitfield-Mask: 0x01) */ -#define PORT14_PPS_PPS2_Pos \ - (2UL) /*!< PORT14 PPS: PPS2 (Bit 2) */ -#define PORT14_PPS_PPS2_Msk \ - (0x4UL) /*!< PORT14 PPS: PPS2 (Bitfield-Mask: 0x01) */ -#define PORT14_PPS_PPS3_Pos \ - (3UL) /*!< PORT14 PPS: PPS3 (Bit 3) */ -#define PORT14_PPS_PPS3_Msk \ - (0x8UL) /*!< PORT14 PPS: PPS3 (Bitfield-Mask: 0x01) */ -#define PORT14_PPS_PPS4_Pos \ - (4UL) /*!< PORT14 PPS: PPS4 (Bit 4) */ -#define PORT14_PPS_PPS4_Msk \ - (0x10UL) /*!< PORT14 PPS: PPS4 (Bitfield-Mask: 0x01) */ -#define PORT14_PPS_PPS5_Pos \ - (5UL) /*!< PORT14 PPS: PPS5 (Bit 5) */ -#define PORT14_PPS_PPS5_Msk \ - (0x20UL) /*!< PORT14 PPS: PPS5 (Bitfield-Mask: 0x01) */ -#define PORT14_PPS_PPS6_Pos \ - (6UL) /*!< PORT14 PPS: PPS6 (Bit 6) */ -#define PORT14_PPS_PPS6_Msk \ - (0x40UL) /*!< PORT14 PPS: PPS6 (Bitfield-Mask: 0x01) */ -#define PORT14_PPS_PPS7_Pos \ - (7UL) /*!< PORT14 PPS: PPS7 (Bit 7) */ -#define PORT14_PPS_PPS7_Msk \ - (0x80UL) /*!< PORT14 PPS: PPS7 (Bitfield-Mask: 0x01) */ -#define PORT14_PPS_PPS8_Pos \ - (8UL) /*!< PORT14 PPS: PPS8 (Bit 8) */ -#define PORT14_PPS_PPS8_Msk \ - (0x100UL) /*!< PORT14 PPS: PPS8 (Bitfield-Mask: 0x01) */ -#define PORT14_PPS_PPS9_Pos \ - (9UL) /*!< PORT14 PPS: PPS9 (Bit 9) */ -#define PORT14_PPS_PPS9_Msk \ - (0x200UL) /*!< PORT14 PPS: PPS9 (Bitfield-Mask: 0x01) */ -#define PORT14_PPS_PPS10_Pos \ - (10UL) /*!< PORT14 PPS: PPS10 (Bit 10) */ -#define PORT14_PPS_PPS10_Msk \ - (0x400UL) /*!< PORT14 PPS: PPS10 (Bitfield-Mask: 0x01) */ -#define PORT14_PPS_PPS11_Pos \ - (11UL) /*!< PORT14 PPS: PPS11 (Bit 11) */ -#define PORT14_PPS_PPS11_Msk \ - (0x800UL) /*!< PORT14 PPS: PPS11 (Bitfield-Mask: 0x01) */ -#define PORT14_PPS_PPS12_Pos \ - (12UL) /*!< PORT14 PPS: PPS12 (Bit 12) */ -#define PORT14_PPS_PPS12_Msk \ - (0x1000UL) /*!< PORT14 PPS: PPS12 (Bitfield-Mask: 0x01) */ -#define PORT14_PPS_PPS13_Pos \ - (13UL) /*!< PORT14 PPS: PPS13 (Bit 13) */ -#define PORT14_PPS_PPS13_Msk \ - (0x2000UL) /*!< PORT14 PPS: PPS13 (Bitfield-Mask: 0x01) */ -#define PORT14_PPS_PPS14_Pos \ - (14UL) /*!< PORT14 PPS: PPS14 (Bit 14) */ -#define PORT14_PPS_PPS14_Msk \ - (0x4000UL) /*!< PORT14 PPS: PPS14 (Bitfield-Mask: 0x01) */ -#define PORT14_PPS_PPS15_Pos \ - (15UL) /*!< PORT14 PPS: PPS15 (Bit 15) */ -#define PORT14_PPS_PPS15_Msk \ - (0x8000UL) /*!< PORT14 PPS: PPS15 (Bitfield-Mask: 0x01) */ - -/* -------------------------------- PORT14_HWSEL -------------------------------- */ -#define PORT14_HWSEL_HW0_Pos \ - (0UL) /*!< PORT14 HWSEL: HW0 (Bit 0) */ -#define PORT14_HWSEL_HW0_Msk \ - (0x3UL) /*!< PORT14 HWSEL: HW0 (Bitfield-Mask: 0x03) */ -#define PORT14_HWSEL_HW1_Pos \ - (2UL) /*!< PORT14 HWSEL: HW1 (Bit 2) */ -#define PORT14_HWSEL_HW1_Msk \ - (0xcUL) /*!< PORT14 HWSEL: HW1 (Bitfield-Mask: 0x03) */ -#define PORT14_HWSEL_HW2_Pos \ - (4UL) /*!< PORT14 HWSEL: HW2 (Bit 4) */ -#define PORT14_HWSEL_HW2_Msk \ - (0x30UL) /*!< PORT14 HWSEL: HW2 (Bitfield-Mask: 0x03) */ -#define PORT14_HWSEL_HW3_Pos \ - (6UL) /*!< PORT14 HWSEL: HW3 (Bit 6) */ -#define PORT14_HWSEL_HW3_Msk \ - (0xc0UL) /*!< PORT14 HWSEL: HW3 (Bitfield-Mask: 0x03) */ -#define PORT14_HWSEL_HW4_Pos \ - (8UL) /*!< PORT14 HWSEL: HW4 (Bit 8) */ -#define PORT14_HWSEL_HW4_Msk \ - (0x300UL) /*!< PORT14 HWSEL: HW4 (Bitfield-Mask: 0x03) */ -#define PORT14_HWSEL_HW5_Pos \ - (10UL) /*!< PORT14 HWSEL: HW5 (Bit 10) */ -#define PORT14_HWSEL_HW5_Msk \ - (0xc00UL) /*!< PORT14 HWSEL: HW5 (Bitfield-Mask: 0x03) */ -#define PORT14_HWSEL_HW6_Pos \ - (12UL) /*!< PORT14 HWSEL: HW6 (Bit 12) */ -#define PORT14_HWSEL_HW6_Msk \ - (0x3000UL) /*!< PORT14 HWSEL: HW6 (Bitfield-Mask: 0x03) */ -#define PORT14_HWSEL_HW7_Pos \ - (14UL) /*!< PORT14 HWSEL: HW7 (Bit 14) */ -#define PORT14_HWSEL_HW7_Msk \ - (0xc000UL) /*!< PORT14 HWSEL: HW7 (Bitfield-Mask: 0x03) */ -#define PORT14_HWSEL_HW8_Pos \ - (16UL) /*!< PORT14 HWSEL: HW8 (Bit 16) */ -#define PORT14_HWSEL_HW8_Msk \ - (0x30000UL) /*!< PORT14 HWSEL: HW8 (Bitfield-Mask: 0x03) */ -#define PORT14_HWSEL_HW9_Pos \ - (18UL) /*!< PORT14 HWSEL: HW9 (Bit 18) */ -#define PORT14_HWSEL_HW9_Msk \ - (0xc0000UL) /*!< PORT14 HWSEL: HW9 (Bitfield-Mask: 0x03) */ -#define PORT14_HWSEL_HW10_Pos \ - (20UL) /*!< PORT14 HWSEL: HW10 (Bit 20) */ -#define PORT14_HWSEL_HW10_Msk \ - (0x300000UL) /*!< PORT14 HWSEL: HW10 (Bitfield-Mask: 0x03) */ -#define PORT14_HWSEL_HW11_Pos \ - (22UL) /*!< PORT14 HWSEL: HW11 (Bit 22) */ -#define PORT14_HWSEL_HW11_Msk \ - (0xc00000UL) /*!< PORT14 HWSEL: HW11 (Bitfield-Mask: 0x03) */ -#define PORT14_HWSEL_HW12_Pos \ - (24UL) /*!< PORT14 HWSEL: HW12 (Bit 24) */ -#define PORT14_HWSEL_HW12_Msk \ - (0x3000000UL) /*!< PORT14 HWSEL: HW12 (Bitfield-Mask: 0x03) */ -#define PORT14_HWSEL_HW13_Pos \ - (26UL) /*!< PORT14 HWSEL: HW13 (Bit 26) */ -#define PORT14_HWSEL_HW13_Msk \ - (0xc000000UL) /*!< PORT14 HWSEL: HW13 (Bitfield-Mask: 0x03) */ -#define PORT14_HWSEL_HW14_Pos \ - (28UL) /*!< PORT14 HWSEL: HW14 (Bit 28) */ -#define PORT14_HWSEL_HW14_Msk \ - (0x30000000UL) /*!< PORT14 HWSEL: HW14 (Bitfield-Mask: 0x03) */ -#define PORT14_HWSEL_HW15_Pos \ - (30UL) /*!< PORT14 HWSEL: HW15 (Bit 30) */ -#define PORT14_HWSEL_HW15_Msk \ - (0xc0000000UL) /*!< PORT14 HWSEL: HW15 (Bitfield-Mask: 0x03) */ - -/* ================================================================================ */ -/* ================ Peripheral memory map ================ */ -/* ================================================================================ */ - -#define PPB_BASE 0xE000E000UL -#define DLR_BASE 0x50004900UL -#define ERU0_BASE 0x50004800UL -#define ERU1_BASE 0x40044000UL -#define GPDMA0_BASE 0x500142C0UL -#define GPDMA0_CH0_BASE 0x50014000UL -#define GPDMA0_CH1_BASE 0x50014058UL -#define GPDMA0_CH2_BASE 0x500140B0UL -#define GPDMA0_CH3_BASE 0x50014108UL -#define GPDMA0_CH4_BASE 0x50014160UL -#define GPDMA0_CH5_BASE 0x500141B8UL -#define GPDMA0_CH6_BASE 0x50014210UL -#define GPDMA0_CH7_BASE 0x50014268UL -#define FCE_BASE 0x50020000UL -#define FCE_KE0_BASE 0x50020020UL -#define FCE_KE1_BASE 0x50020040UL -#define FCE_KE2_BASE 0x50020060UL -#define FCE_KE3_BASE 0x50020080UL -#define PBA0_BASE 0x40000000UL -#define PBA1_BASE 0x48000000UL -#define FLASH0_BASE 0x58001000UL -#define PREF_BASE 0x58004000UL -#define PMU0_BASE 0x58000508UL -#define WDT_BASE 0x50008000UL -#define RTC_BASE 0x50004A00UL -#define SCU_CLK_BASE 0x50004600UL -#define SCU_OSC_BASE 0x50004700UL -#define SCU_PLL_BASE 0x50004710UL -#define SCU_GENERAL_BASE 0x50004000UL -#define SCU_INTERRUPT_BASE 0x50004074UL -#define SCU_PARITY_BASE 0x5000413CUL -#define SCU_TRAP_BASE 0x50004160UL -#define SCU_HIBERNATE_BASE 0x50004300UL -#define SCU_POWER_BASE 0x50004200UL -#define SCU_RESET_BASE 0x50004400UL -#define LEDTS0_BASE 0x48010000UL -#define USB0_BASE 0x50040000UL -#define USB_EP_BASE 0x50040900UL -#define USB0_EP1_BASE 0x50040920UL -#define USB0_EP2_BASE 0x50040940UL -#define USB0_EP3_BASE 0x50040960UL -#define USB0_EP4_BASE 0x50040980UL -#define USB0_EP5_BASE 0x500409A0UL -#define USB0_EP6_BASE 0x500409C0UL -#define USIC0_BASE 0x40030008UL -#define USIC1_BASE 0x48020008UL -#define USIC0_CH0_BASE 0x40030000UL -#define USIC0_CH1_BASE 0x40030200UL -#define USIC1_CH0_BASE 0x48020000UL -#define USIC1_CH1_BASE 0x48020200UL -#define CAN_BASE 0x48014000UL -#define CAN_NODE0_BASE 0x48014200UL -#define CAN_NODE1_BASE 0x48014300UL -#define CAN_MO0_BASE 0x48015000UL -#define CAN_MO1_BASE 0x48015020UL -#define CAN_MO2_BASE 0x48015040UL -#define CAN_MO3_BASE 0x48015060UL -#define CAN_MO4_BASE 0x48015080UL -#define CAN_MO5_BASE 0x480150A0UL -#define CAN_MO6_BASE 0x480150C0UL -#define CAN_MO7_BASE 0x480150E0UL -#define CAN_MO8_BASE 0x48015100UL -#define CAN_MO9_BASE 0x48015120UL -#define CAN_MO10_BASE 0x48015140UL -#define CAN_MO11_BASE 0x48015160UL -#define CAN_MO12_BASE 0x48015180UL -#define CAN_MO13_BASE 0x480151A0UL -#define CAN_MO14_BASE 0x480151C0UL -#define CAN_MO15_BASE 0x480151E0UL -#define CAN_MO16_BASE 0x48015200UL -#define CAN_MO17_BASE 0x48015220UL -#define CAN_MO18_BASE 0x48015240UL -#define CAN_MO19_BASE 0x48015260UL -#define CAN_MO20_BASE 0x48015280UL -#define CAN_MO21_BASE 0x480152A0UL -#define CAN_MO22_BASE 0x480152C0UL -#define CAN_MO23_BASE 0x480152E0UL -#define CAN_MO24_BASE 0x48015300UL -#define CAN_MO25_BASE 0x48015320UL -#define CAN_MO26_BASE 0x48015340UL -#define CAN_MO27_BASE 0x48015360UL -#define CAN_MO28_BASE 0x48015380UL -#define CAN_MO29_BASE 0x480153A0UL -#define CAN_MO30_BASE 0x480153C0UL -#define CAN_MO31_BASE 0x480153E0UL -#define CAN_MO32_BASE 0x48015400UL -#define CAN_MO33_BASE 0x48015420UL -#define CAN_MO34_BASE 0x48015440UL -#define CAN_MO35_BASE 0x48015460UL -#define CAN_MO36_BASE 0x48015480UL -#define CAN_MO37_BASE 0x480154A0UL -#define CAN_MO38_BASE 0x480154C0UL -#define CAN_MO39_BASE 0x480154E0UL -#define CAN_MO40_BASE 0x48015500UL -#define CAN_MO41_BASE 0x48015520UL -#define CAN_MO42_BASE 0x48015540UL -#define CAN_MO43_BASE 0x48015560UL -#define CAN_MO44_BASE 0x48015580UL -#define CAN_MO45_BASE 0x480155A0UL -#define CAN_MO46_BASE 0x480155C0UL -#define CAN_MO47_BASE 0x480155E0UL -#define CAN_MO48_BASE 0x48015600UL -#define CAN_MO49_BASE 0x48015620UL -#define CAN_MO50_BASE 0x48015640UL -#define CAN_MO51_BASE 0x48015660UL -#define CAN_MO52_BASE 0x48015680UL -#define CAN_MO53_BASE 0x480156A0UL -#define CAN_MO54_BASE 0x480156C0UL -#define CAN_MO55_BASE 0x480156E0UL -#define CAN_MO56_BASE 0x48015700UL -#define CAN_MO57_BASE 0x48015720UL -#define CAN_MO58_BASE 0x48015740UL -#define CAN_MO59_BASE 0x48015760UL -#define CAN_MO60_BASE 0x48015780UL -#define CAN_MO61_BASE 0x480157A0UL -#define CAN_MO62_BASE 0x480157C0UL -#define CAN_MO63_BASE 0x480157E0UL -#define VADC_BASE 0x40004000UL -#define VADC_G0_BASE 0x40004400UL -#define VADC_G1_BASE 0x40004800UL -#define DAC_BASE 0x48018000UL -#define CCU40_BASE 0x4000C000UL -#define CCU41_BASE 0x40010000UL -#define CCU40_CC40_BASE 0x4000C100UL -#define CCU40_CC41_BASE 0x4000C200UL -#define CCU40_CC42_BASE 0x4000C300UL -#define CCU40_CC43_BASE 0x4000C400UL -#define CCU41_CC40_BASE 0x40010100UL -#define CCU41_CC41_BASE 0x40010200UL -#define CCU41_CC42_BASE 0x40010300UL -#define CCU41_CC43_BASE 0x40010400UL -#define CCU80_BASE 0x40020000UL -#define CCU80_CC80_BASE 0x40020100UL -#define CCU80_CC81_BASE 0x40020200UL -#define CCU80_CC82_BASE 0x40020300UL -#define CCU80_CC83_BASE 0x40020400UL -#define HRPWM0_BASE 0x40020900UL -#define HRPWM0_CSG0_BASE 0x40020A00UL -#define HRPWM0_CSG1_BASE 0x40020B00UL -#define HRPWM0_CSG2_BASE 0x40020C00UL -#define HRPWM0_HRC0_BASE 0x40021300UL -#define HRPWM0_HRC1_BASE 0x40021400UL -#define HRPWM0_HRC2_BASE 0x40021500UL -#define HRPWM0_HRC3_BASE 0x40021600UL -#define POSIF0_BASE 0x40028000UL -#define PORT0_BASE 0x48028000UL -#define PORT1_BASE 0x48028100UL -#define PORT2_BASE 0x48028200UL -#define PORT3_BASE 0x48028300UL -#define PORT14_BASE 0x48028E00UL - -/* ================================================================================ */ -/* ================ Peripheral declaration ================ */ -/* ================================================================================ */ - -#define PPB ((PPB_Type *)PPB_BASE) -#define DLR ((DLR_GLOBAL_TypeDef *)DLR_BASE) -#define ERU0 ((ERU_GLOBAL_TypeDef *)ERU0_BASE) -#define ERU1 ((ERU_GLOBAL_TypeDef *)ERU1_BASE) -#define GPDMA0 ((GPDMA0_GLOBAL_TypeDef *)GPDMA0_BASE) -#define GPDMA0_CH0 ((GPDMA0_CH_TypeDef *)GPDMA0_CH0_BASE) -#define GPDMA0_CH1 ((GPDMA0_CH_TypeDef *)GPDMA0_CH1_BASE) -#define GPDMA0_CH2 ((GPDMA0_CH_TypeDef *)GPDMA0_CH2_BASE) -#define GPDMA0_CH3 ((GPDMA0_CH_TypeDef *)GPDMA0_CH3_BASE) -#define GPDMA0_CH4 ((GPDMA0_CH_TypeDef *)GPDMA0_CH4_BASE) -#define GPDMA0_CH5 ((GPDMA0_CH_TypeDef *)GPDMA0_CH5_BASE) -#define GPDMA0_CH6 ((GPDMA0_CH_TypeDef *)GPDMA0_CH6_BASE) -#define GPDMA0_CH7 ((GPDMA0_CH_TypeDef *)GPDMA0_CH7_BASE) -#define FCE ((FCE_GLOBAL_TypeDef *)FCE_BASE) -#define FCE_KE0 ((FCE_KE_TypeDef *)FCE_KE0_BASE) -#define FCE_KE1 ((FCE_KE_TypeDef *)FCE_KE1_BASE) -#define FCE_KE2 ((FCE_KE_TypeDef *)FCE_KE2_BASE) -#define FCE_KE3 ((FCE_KE_TypeDef *)FCE_KE3_BASE) -#define PBA0 ((PBA_GLOBAL_TypeDef *)PBA0_BASE) -#define PBA1 ((PBA_GLOBAL_TypeDef *)PBA1_BASE) -#define FLASH0 ((FLASH0_GLOBAL_TypeDef *)FLASH0_BASE) -#define PREF ((PREF_GLOBAL_TypeDef *)PREF_BASE) -#define PMU0 ((PMU0_GLOBAL_TypeDef *)PMU0_BASE) -#define WDT ((WDT_GLOBAL_TypeDef *)WDT_BASE) -#define RTC ((RTC_GLOBAL_TypeDef *)RTC_BASE) -#define SCU_CLK ((SCU_CLK_TypeDef *)SCU_CLK_BASE) -#define SCU_OSC ((SCU_OSC_TypeDef *)SCU_OSC_BASE) -#define SCU_PLL ((SCU_PLL_TypeDef *)SCU_PLL_BASE) -#define SCU_GENERAL ((SCU_GENERAL_TypeDef *)SCU_GENERAL_BASE) -#define SCU_INTERRUPT ((SCU_INTERRUPT_TypeDef *)SCU_INTERRUPT_BASE) -#define SCU_PARITY ((SCU_PARITY_TypeDef *)SCU_PARITY_BASE) -#define SCU_TRAP ((SCU_TRAP_TypeDef *)SCU_TRAP_BASE) -#define SCU_HIBERNATE ((SCU_HIBERNATE_TypeDef *)SCU_HIBERNATE_BASE) -#define SCU_POWER ((SCU_POWER_TypeDef *)SCU_POWER_BASE) -#define SCU_RESET ((SCU_RESET_TypeDef *)SCU_RESET_BASE) -#define LEDTS0 ((LEDTS0_GLOBAL_TypeDef *)LEDTS0_BASE) -#define USB0 ((USB0_GLOBAL_TypeDef *)USB0_BASE) -#define USB0_EP0 ((USB0_EP0_TypeDef *)USB_EP_BASE) -#define USB0_EP1 ((USB0_EP_TypeDef *)USB0_EP1_BASE) -#define USB0_EP2 ((USB0_EP_TypeDef *)USB0_EP2_BASE) -#define USB0_EP3 ((USB0_EP_TypeDef *)USB0_EP3_BASE) -#define USB0_EP4 ((USB0_EP_TypeDef *)USB0_EP4_BASE) -#define USB0_EP5 ((USB0_EP_TypeDef *)USB0_EP5_BASE) -#define USB0_EP6 ((USB0_EP_TypeDef *)USB0_EP6_BASE) -#define USIC0 ((USIC_GLOBAL_TypeDef *)USIC0_BASE) -#define USIC1 ((USIC_GLOBAL_TypeDef *)USIC1_BASE) -#define USIC0_CH0 ((USIC_CH_TypeDef *)USIC0_CH0_BASE) -#define USIC0_CH1 ((USIC_CH_TypeDef *)USIC0_CH1_BASE) -#define USIC1_CH0 ((USIC_CH_TypeDef *)USIC1_CH0_BASE) -#define USIC1_CH1 ((USIC_CH_TypeDef *)USIC1_CH1_BASE) -#define CAN_xmc ((CAN_GLOBAL_TypeDef *)CAN_BASE) -#define CAN_NODE0 ((CAN_NODE_TypeDef *)CAN_NODE0_BASE) -#define CAN_NODE1 ((CAN_NODE_TypeDef *)CAN_NODE1_BASE) -#define CAN_MO0 ((CAN_MO_TypeDef *)CAN_MO0_BASE) -#define CAN_MO1 ((CAN_MO_TypeDef *)CAN_MO1_BASE) -#define CAN_MO2 ((CAN_MO_TypeDef *)CAN_MO2_BASE) -#define CAN_MO3 ((CAN_MO_TypeDef *)CAN_MO3_BASE) -#define CAN_MO4 ((CAN_MO_TypeDef *)CAN_MO4_BASE) -#define CAN_MO5 ((CAN_MO_TypeDef *)CAN_MO5_BASE) -#define CAN_MO6 ((CAN_MO_TypeDef *)CAN_MO6_BASE) -#define CAN_MO7 ((CAN_MO_TypeDef *)CAN_MO7_BASE) -#define CAN_MO8 ((CAN_MO_TypeDef *)CAN_MO8_BASE) -#define CAN_MO9 ((CAN_MO_TypeDef *)CAN_MO9_BASE) -#define CAN_MO10 ((CAN_MO_TypeDef *)CAN_MO10_BASE) -#define CAN_MO11 ((CAN_MO_TypeDef *)CAN_MO11_BASE) -#define CAN_MO12 ((CAN_MO_TypeDef *)CAN_MO12_BASE) -#define CAN_MO13 ((CAN_MO_TypeDef *)CAN_MO13_BASE) -#define CAN_MO14 ((CAN_MO_TypeDef *)CAN_MO14_BASE) -#define CAN_MO15 ((CAN_MO_TypeDef *)CAN_MO15_BASE) -#define CAN_MO16 ((CAN_MO_TypeDef *)CAN_MO16_BASE) -#define CAN_MO17 ((CAN_MO_TypeDef *)CAN_MO17_BASE) -#define CAN_MO18 ((CAN_MO_TypeDef *)CAN_MO18_BASE) -#define CAN_MO19 ((CAN_MO_TypeDef *)CAN_MO19_BASE) -#define CAN_MO20 ((CAN_MO_TypeDef *)CAN_MO20_BASE) -#define CAN_MO21 ((CAN_MO_TypeDef *)CAN_MO21_BASE) -#define CAN_MO22 ((CAN_MO_TypeDef *)CAN_MO22_BASE) -#define CAN_MO23 ((CAN_MO_TypeDef *)CAN_MO23_BASE) -#define CAN_MO24 ((CAN_MO_TypeDef *)CAN_MO24_BASE) -#define CAN_MO25 ((CAN_MO_TypeDef *)CAN_MO25_BASE) -#define CAN_MO26 ((CAN_MO_TypeDef *)CAN_MO26_BASE) -#define CAN_MO27 ((CAN_MO_TypeDef *)CAN_MO27_BASE) -#define CAN_MO28 ((CAN_MO_TypeDef *)CAN_MO28_BASE) -#define CAN_MO29 ((CAN_MO_TypeDef *)CAN_MO29_BASE) -#define CAN_MO30 ((CAN_MO_TypeDef *)CAN_MO30_BASE) -#define CAN_MO31 ((CAN_MO_TypeDef *)CAN_MO31_BASE) -#define CAN_MO32 ((CAN_MO_TypeDef *)CAN_MO32_BASE) -#define CAN_MO33 ((CAN_MO_TypeDef *)CAN_MO33_BASE) -#define CAN_MO34 ((CAN_MO_TypeDef *)CAN_MO34_BASE) -#define CAN_MO35 ((CAN_MO_TypeDef *)CAN_MO35_BASE) -#define CAN_MO36 ((CAN_MO_TypeDef *)CAN_MO36_BASE) -#define CAN_MO37 ((CAN_MO_TypeDef *)CAN_MO37_BASE) -#define CAN_MO38 ((CAN_MO_TypeDef *)CAN_MO38_BASE) -#define CAN_MO39 ((CAN_MO_TypeDef *)CAN_MO39_BASE) -#define CAN_MO40 ((CAN_MO_TypeDef *)CAN_MO40_BASE) -#define CAN_MO41 ((CAN_MO_TypeDef *)CAN_MO41_BASE) -#define CAN_MO42 ((CAN_MO_TypeDef *)CAN_MO42_BASE) -#define CAN_MO43 ((CAN_MO_TypeDef *)CAN_MO43_BASE) -#define CAN_MO44 ((CAN_MO_TypeDef *)CAN_MO44_BASE) -#define CAN_MO45 ((CAN_MO_TypeDef *)CAN_MO45_BASE) -#define CAN_MO46 ((CAN_MO_TypeDef *)CAN_MO46_BASE) -#define CAN_MO47 ((CAN_MO_TypeDef *)CAN_MO47_BASE) -#define CAN_MO48 ((CAN_MO_TypeDef *)CAN_MO48_BASE) -#define CAN_MO49 ((CAN_MO_TypeDef *)CAN_MO49_BASE) -#define CAN_MO50 ((CAN_MO_TypeDef *)CAN_MO50_BASE) -#define CAN_MO51 ((CAN_MO_TypeDef *)CAN_MO51_BASE) -#define CAN_MO52 ((CAN_MO_TypeDef *)CAN_MO52_BASE) -#define CAN_MO53 ((CAN_MO_TypeDef *)CAN_MO53_BASE) -#define CAN_MO54 ((CAN_MO_TypeDef *)CAN_MO54_BASE) -#define CAN_MO55 ((CAN_MO_TypeDef *)CAN_MO55_BASE) -#define CAN_MO56 ((CAN_MO_TypeDef *)CAN_MO56_BASE) -#define CAN_MO57 ((CAN_MO_TypeDef *)CAN_MO57_BASE) -#define CAN_MO58 ((CAN_MO_TypeDef *)CAN_MO58_BASE) -#define CAN_MO59 ((CAN_MO_TypeDef *)CAN_MO59_BASE) -#define CAN_MO60 ((CAN_MO_TypeDef *)CAN_MO60_BASE) -#define CAN_MO61 ((CAN_MO_TypeDef *)CAN_MO61_BASE) -#define CAN_MO62 ((CAN_MO_TypeDef *)CAN_MO62_BASE) -#define CAN_MO63 ((CAN_MO_TypeDef *)CAN_MO63_BASE) -#define VADC ((VADC_GLOBAL_TypeDef *)VADC_BASE) -#define VADC_G0 ((VADC_G_TypeDef *)VADC_G0_BASE) -#define VADC_G1 ((VADC_G_TypeDef *)VADC_G1_BASE) -#define DAC ((DAC_GLOBAL_TypeDef *)DAC_BASE) -#define CCU40 ((CCU4_GLOBAL_TypeDef *)CCU40_BASE) -#define CCU41 ((CCU4_GLOBAL_TypeDef *)CCU41_BASE) -#define CCU40_CC40 ((CCU4_CC4_TypeDef *)CCU40_CC40_BASE) -#define CCU40_CC41 ((CCU4_CC4_TypeDef *)CCU40_CC41_BASE) -#define CCU40_CC42 ((CCU4_CC4_TypeDef *)CCU40_CC42_BASE) -#define CCU40_CC43 ((CCU4_CC4_TypeDef *)CCU40_CC43_BASE) -#define CCU41_CC40 ((CCU4_CC4_TypeDef *)CCU41_CC40_BASE) -#define CCU41_CC41 ((CCU4_CC4_TypeDef *)CCU41_CC41_BASE) -#define CCU41_CC42 ((CCU4_CC4_TypeDef *)CCU41_CC42_BASE) -#define CCU41_CC43 ((CCU4_CC4_TypeDef *)CCU41_CC43_BASE) -#define CCU80 ((CCU8_GLOBAL_TypeDef *)CCU80_BASE) -#define CCU80_CC80 ((CCU8_CC8_TypeDef *)CCU80_CC80_BASE) -#define CCU80_CC81 ((CCU8_CC8_TypeDef *)CCU80_CC81_BASE) -#define CCU80_CC82 ((CCU8_CC8_TypeDef *)CCU80_CC82_BASE) -#define CCU80_CC83 ((CCU8_CC8_TypeDef *)CCU80_CC83_BASE) -#define HRPWM0 ((HRPWM0_Type *)HRPWM0_BASE) -#define HRPWM0_CSG0 ((HRPWM0_CSG_Type *)HRPWM0_CSG0_BASE) -#define HRPWM0_CSG1 ((HRPWM0_CSG_Type *)HRPWM0_CSG1_BASE) -#define HRPWM0_CSG2 ((HRPWM0_CSG_Type *)HRPWM0_CSG2_BASE) -#define HRPWM0_HRC0 ((HRPWM0_HRC_Type *)HRPWM0_HRC0_BASE) -#define HRPWM0_HRC1 ((HRPWM0_HRC_Type *)HRPWM0_HRC1_BASE) -#define HRPWM0_HRC2 ((HRPWM0_HRC_Type *)HRPWM0_HRC2_BASE) -#define HRPWM0_HRC3 ((HRPWM0_HRC_Type *)HRPWM0_HRC3_BASE) -#define POSIF0 ((POSIF_GLOBAL_TypeDef *)POSIF0_BASE) -#define PORT0 ((PORT0_Type *)PORT0_BASE) -#define PORT1 ((PORT1_Type *)PORT1_BASE) -#define PORT2 ((PORT2_Type *)PORT2_BASE) -#define PORT3 ((PORT3_Type *)PORT3_BASE) -#define PORT14 ((PORT14_Type *)PORT14_BASE) - -/** @} */ /* End of group Device_Peripheral_Registers */ -/** @} */ /* End of group XMC4200 */ -/** @} */ /* End of group Infineon */ - -#ifdef __cplusplus -} -#endif - -#endif /* XMC4200_H */ diff --git a/variants/XMC4200/config/XMC4200_Platform2GO/pins_arduino.h b/variants/XMC4200/config/XMC4200_Platform2GO/pins_arduino.h deleted file mode 100644 index bc5b4b9f..00000000 --- a/variants/XMC4200/config/XMC4200_Platform2GO/pins_arduino.h +++ /dev/null @@ -1,382 +0,0 @@ -/* - pins_arduino.h - Pin definition functions for Arduino - Part of Arduino - http://www.arduino.cc/ - - Copyright (c) 2007 David A. Mellis - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General - Public License along with this library; if not, write to the - Free Software Foundation, Inc., 59 Temple Place, Suite 330, - Boston, MA 02111-1307 USA - - Copyright (c) 2019 Infineon Technologies AG - This file has been modified for the XMC microcontroller series. -*/ -#ifndef PINS_ARDUINO_H_ -#define PINS_ARDUINO_H_ - -//**************************************************************************** -// @Project Includes -//**************************************************************************** -#include - -//**************************************************************************** -// @Defines -//**************************************************************************** -#define XMC_BOARD XMC 4200 Platform 2GO - -/* On board LED is ON when digital output is 1, HIGH, TRUE, ON */ -#define XMC_LED_ON 1 - -// Following were defines now evaluated by compilation as const variables -// After definitions of associated mapping arrays -extern const uint8_t NUM_DIGITAL; -extern const uint8_t GND; -extern const uint8_t NUM_PWM4; -extern const uint8_t NUM_PWM8; -extern const uint8_t NUM_PWM; -extern const uint8_t NUM_INTERRUPT; -extern const uint8_t NUM_ANALOG_INPUTS; -#ifdef DAC -extern const uint8_t NUM_ANALOG_OUTPUTS; -#endif -#define NUM_LEDS 1 -#define NUM_BUTTONS 1 -#define NUM_SERIAL 1 -#define NUM_TONE_PINS 7 -#define NUM_TASKS_VARIANT 12 -#define NUM_SPI 1 -#define NUM_I2C 1 - -// Indicate unit has RTC/Alarm -#define HAS_RTC 1 - -// Generate 490Hz @fCCU=80MHz -#define PWM4_TIMER_PERIOD (0x09F7) -// Generate 490Hz @fCCU=80MHz -#define PWM8_TIMER_PERIOD (0x09F7) - -#define PCLK 80000000u - -#define PIN_SPI_SS 10 -#define PIN_SPI_MOSI 11 -#define PIN_SPI_MISO 12 -#define PIN_SPI_SCK 13 - -extern uint8_t SS; -extern uint8_t MOSI; -extern uint8_t MISO; -extern uint8_t SCK; - -#define A0 0 // ADC G0CH0 P14.0 -#define A1 1 // ADC G0CH6 P14.6 -#define A2 2 // ADC G0CH7 P14.7 -#define A3 3 // ADC G1CH0 P14.8 -#define A4 4 // ADC G0CH4 P14.4 -#define A5 5 // ADC G0CH5 P14.5 -// Additional ADC ports starting here -#define A6 6 // ADC G1CH6 on P14.14 -#define A7 7 // ADC G1CH1 on P14.9 - -#define LED1 36 // Additional LED1 -#define LED_BUILTIN LED1 // Standard Arduino LED: Uses LED1 -#define LED2 \ - LED1 // Dummy LED define macro; added to comply with LED Library examples in CI/CD workflow -#define BUTTON1 27 // Additional BUTTON1 - -#define digitalPinToInterrupt(p) ((p) == 2 ? 0 : ((p) == 3 ? 1 : NOT_AN_INTERRUPT)) - -#ifdef ARDUINO_MAIN -// Mapping of digital pins and comments -const XMC_PORT_PIN_t mapping_port_pin[] = { - /* 0 */ {XMC_GPIO_PORT2, 15}, // RX P2.15 X1-4 - /* 1 */ {XMC_GPIO_PORT2, 14}, // TX P2.14 X1-3 - /* 2 */ {XMC_GPIO_PORT1, 0}, // GPIO / External INT 0 P1.0 X1-11 - /* 3 */ {XMC_GPIO_PORT2, 2}, // PWM41-3 / PWM0 / External INT 1 P2.2 X1-31 - /* 4 */ {XMC_GPIO_PORT2, 9}, // IO_0 P2.9 X1-36 - /* 5 */ {XMC_GPIO_PORT2, 3}, // PWM41-2 output / PWM1 P2.3 X1-32 - /* 6 */ {XMC_GPIO_PORT2, 4}, // PWM41-1 output / PWM2 P2.4 X1-33 - /* 7 */ {XMC_GPIO_PORT2, 8}, // IO_1 P2.8 X1-35 - - /* 8 */ {XMC_GPIO_PORT2, 6}, // IO_2 P2.6 X1-27 - /* 9 */ {XMC_GPIO_PORT0, 11}, // PWM80-31 output / PWM3 P0.11 X2-7 - /* 10 */ {XMC_GPIO_PORT1, 7}, // SPI-CS P1.7 X1-8 - /* 11 */ {XMC_GPIO_PORT1, 9}, // SPI-MOSI P1.9 X1-10 - /* 12 */ {XMC_GPIO_PORT0, 0}, // SPI-MISO P0.0 X2-18 - /* 13 */ {XMC_GPIO_PORT1, 8}, // SPI-SCK P1.8 X1-9 - /* 14 */ {XMC_GPIO_PORT2, 5}, // I2C Data / Address SDA / A4 P2.5 (Hardwired to A4) - // X1-34 - /* 15 */ {XMC_GPIO_PORT3, 0}, // I2C Clock SCL / A5 P3.0 (Hardwired to A5) - // X2-19 - /* 16 */ {XMC_GPIO_PORT14, 0}, // A0 / ADC Input P14.0 (INPUT ONLY) - // X2-34 - /* 17 */ {XMC_GPIO_PORT14, 6}, // A1 / ADC Input P14.6 (INPUT ONLY) - // X2-25 - /* 18 */ {XMC_GPIO_PORT14, 7}, // A2 / ADC Input P14.7 (INPUT ONLY) - // X2-28 - /* 19 */ {XMC_GPIO_PORT14, 8}, // A3 / ADC Input / AN_MikroBus / DAC0 P14.8 X2-33 - /* 20 */ {XMC_GPIO_PORT14, 4}, // A4 / ADC Input / SDA / AN1_2GO_1 P14.4 (Hardwired to - // SDA) X2-24 - /* 21 */ {XMC_GPIO_PORT14, 5}, // A5 / ADC Input / SCL / AN2_2GO_2 P14.5 (Hardwired to - // SCL) X2-30 - - // Additional pins for port X1 starting here - /* 22 */ {XMC_GPIO_PORT1, 1}, // PWM_MikroBus / PWM40-2 P1.1 X1-12 - /* 23 */ {XMC_GPIO_PORT1, 2}, // PWM / PWM40-1 / GPIO4_S2GO_1 P1.2 X1-13 - /* 24 */ {XMC_GPIO_PORT1, 3}, // PWM / PWM40-0 / GPIO4_2GO_2 P1.3 X1-14 - /* 25 */ {XMC_GPIO_PORT1, 4}, // PC_TXD P1.4 X1-15 - /* 26 */ {XMC_GPIO_PORT1, 5}, // PC_RXD P1.5 X1-16 - /* 27 */ {XMC_GPIO_PORT1, 15}, // BUTTON1 P1.15 X1-22 - /* 28 */ {XMC_GPIO_PORT2, 7}, // RST_MikroBus P2.7 X1-28 - /* 29 */ {XMC_GPIO_PORT2, 0}, // CAN_TX P2.0 X1-29 - /* 30 */ {XMC_GPIO_PORT2, 1}, // GPIO1_2GO_2 P2.1 X1-30 - - // Additional pins for port X2 starting here - /* 31 */ {XMC_GPIO_PORT0, 7}, // SPI-CS_MikroBus P0.7 X2-1 - /* 32 */ {XMC_GPIO_PORT0, 8}, // RST / GPIO2_2GO_1 P0.8 X2-4 - /* 33 */ {XMC_GPIO_PORT0, 5}, // INT / GPIO3_2GO_1 P0.5 X2-9 - /* 34 */ {XMC_GPIO_PORT0, 3}, // INT / GPIO3_2GO_2 P0.3 X2-11 - /* 35 */ {XMC_GPIO_PORT0, 6}, // RST / GPIO2_2GO_2 P0.6 X2-12 - /* 36 */ {XMC_GPIO_PORT0, 1}, // LED1 P0.1 X2-13 - /* 37 */ {XMC_GPIO_PORT0, 4}, // GPIO1_S2GO_1 P0.4 X2-14 - /* 38 */ {XMC_GPIO_PORT0, 10}, // INT_MikroBus P0.10 X2-15 - /* 39 */ {XMC_GPIO_PORT0, 2}, // SPI-CS_2GO_1 P0.2 X2-16 - /* 40 */ {XMC_GPIO_PORT0, 9}, // SPI-CS_2GO_2 P0.9 X2-20 - /* 41 */ {XMC_GPIO_PORT14, 14}, // AN2_2GO_1 / A6 / ADC Input P14.14 (INPUT ONLY) - // X2-21 - /* 42 */ {XMC_GPIO_PORT14, 3}, // CAN_RX P14.3 X2-32 - /* 43 */ {XMC_GPIO_PORT14, 9}, // AN1_2GO_2 / A7 / ADC Input / DAC1 P14.9 X2-36 -}; - -const uint8_t GND = (sizeof(mapping_port_pin) / sizeof(XMC_PORT_PIN_t)); -const uint8_t NUM_DIGITAL = (sizeof(mapping_port_pin) / sizeof(XMC_PORT_PIN_t)); -; - -const XMC_PIN_INTERRUPT_t mapping_interrupt[] = { - /* 0 */ {XMC_ERU0, XMC_ERU_ETL_INPUT_A0, XMC_ERU_ETL_INPUT_B0, 3, 3, 0}, - /* 1 */ {XMC_ERU0, XMC_ERU_ETL_INPUT_A0, XMC_ERU_ETL_INPUT_B2, 1, 0, 1}}; -const uint8_t NUM_INTERRUPT = (sizeof(mapping_interrupt) / sizeof(XMC_PIN_INTERRUPT_t)); - -/* Mapping of Arduino Pins to PWM4 channels as pin and index in PWM4 channel - mapping array XMC_PWM4_t mapping_pwm4[] - last entry 255 for both parts. - Putting both parts in array means if a PWM4 channel gets reassigned for - another function later a gap in channel numbers will not mess things up */ -const uint8_t mapping_pin_PWM4[][2] = {{3, 0}, // PWM0 - {5, 1}, // PWM1 - {6, 2}, // PWM2 - {22, 3}, // PWM - {23, 4}, // PWM - {24, 5}, // PWM - {255, 255}}; - -/* Configurations of PWM channels for CCU4 type */ -XMC_PWM4_t mapping_pwm4[] = { - {CCU41, CCU41_CC43, 3, mapping_port_pin[3], P2_2_AF_CCU41_OUT3, XMC_CCU4_SLICE_PRESCALER_64, - PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 3 P2.2 - {CCU41, CCU41_CC42, 2, mapping_port_pin[5], P2_3_AF_CCU41_OUT2, XMC_CCU4_SLICE_PRESCALER_64, - PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 5 P2.3 - {CCU41, CCU41_CC41, 1, mapping_port_pin[6], P2_4_AF_CCU41_OUT1, XMC_CCU4_SLICE_PRESCALER_64, - PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 6 P2.4 - // additional pwm outputs starting here - {CCU40, CCU40_CC42, 2, mapping_port_pin[22], P1_1_AF_CCU40_OUT2, XMC_CCU4_SLICE_PRESCALER_64, - PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 22 P1.1 - {CCU40, CCU40_CC41, 1, mapping_port_pin[23], P1_2_AF_CCU40_OUT1, XMC_CCU4_SLICE_PRESCALER_64, - PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 23 P1.2 - {CCU40, CCU40_CC40, 0, mapping_port_pin[24], P1_3_AF_CCU40_OUT0, XMC_CCU4_SLICE_PRESCALER_64, - PWM4_TIMER_PERIOD, DISABLED} // PWM disabled 24 P1.3 -}; -const uint8_t NUM_PWM4 = (sizeof(mapping_pwm4) / sizeof(XMC_PWM4_t)); - -/* Mapping in same manner as PWM4 for PWM8 channels */ -const uint8_t mapping_pin_PWM8[][2] = {{9, 0}, // PWM3 - {255, 255}}; - -/* Configurations of PWM channels for CCU8 type */ -XMC_PWM8_t mapping_pwm8[] = { - {CCU80, CCU80_CC83, 3, XMC_CCU8_SLICE_COMPARE_CHANNEL_1, mapping_port_pin[9], - P0_11_AF_CCU80_OUT31, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, - DISABLED} // PWM disabled 9 P0.11 -}; -const uint8_t NUM_PWM8 = (sizeof(mapping_pwm8) / sizeof(XMC_PWM8_t)); -const uint8_t NUM_PWM = - (sizeof(mapping_pwm4) / sizeof(XMC_PWM4_t)) + (sizeof(mapping_pwm8) / sizeof(XMC_PWM8_t)); - - /* Analog Pin mappings and configurations */ - #ifdef DAC -const uint8_t mapping_pin_DAC[][2] = {{19, 0}, {43, 1}, {255, 255}}; - -/* Analog Pin mappings and configurations */ -XMC_ARD_DAC_t mapping_dac[] = {{XMC_DAC0, 0, 12}, {XMC_DAC0, 1, 12}}; -const uint8_t NUM_ANALOG_OUTPUTS = (sizeof(mapping_dac) / sizeof(XMC_ARD_DAC_t)); - #endif - -XMC_ADC_t mapping_adc[] = { - // Result reg numbers are now equal to channel numbers - {VADC, 0, VADC_G0, 0, 0, DISABLED}, // A0 - {VADC, 6, VADC_G0, 0, 1, DISABLED}, // A1 - {VADC, 7, VADC_G0, 0, 2, DISABLED}, // A2 - {VADC, 0, VADC_G1, 1, 0, DISABLED}, // A3 - {VADC, 4, VADC_G0, 0, 3, DISABLED}, // A4 - {VADC, 5, VADC_G0, 0, 4, DISABLED}, // A5 - // Additional ADC channels starting here - {VADC, 6, VADC_G1, 1, 1, DISABLED}, // A6 - {VADC, 1, VADC_G1, 1, 2, DISABLED}, // A7 -}; -const uint8_t NUM_ANALOG_INPUTS = (sizeof(mapping_adc) / sizeof(XMC_ADC_t)); - -/* - * UART objects - * - */ - -// Since both the UART interfaces are present on different USIC instances, -// both can be enabled independently. - -// Serial is PC-DEBUG interface -// Serial1 is ONBOARD interface - -RingBuffer rx_buffer_0; -RingBuffer tx_buffer_0; - -RingBuffer rx_buffer_1; -RingBuffer tx_buffer_1; - -XMC_UART_t XMC_UART_0 = { - .channel = XMC_UART0_CH0, - .rx = {.port = (XMC_GPIO_PORT_t *)PORT1_BASE, .pin = (uint8_t)4}, - .rx_config = {.mode = XMC_GPIO_MODE_INPUT_TRISTATE, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .output_strength = XMC_GPIO_OUTPUT_STRENGTH_STRONG_SOFT_EDGE}, - .tx = {.port = (XMC_GPIO_PORT_t *)PORT1_BASE, .pin = (uint8_t)5}, - .tx_config = {.mode = (XMC_GPIO_MODE_t)XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT2, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .output_strength = XMC_GPIO_OUTPUT_STRENGTH_STRONG_SOFT_EDGE}, - .input_source_dx0 = (XMC_USIC_INPUT_t)USIC0_C0_DX0_P1_4, - .input_source_dx1 = XMC_INPUT_INVALID, - .input_source_dx2 = XMC_INPUT_INVALID, - .input_source_dx3 = XMC_INPUT_INVALID, - .irq_num = USIC0_0_IRQn, - .irq_service_request = 0}; - -XMC_UART_t XMC_UART_1 = { - .channel = XMC_UART1_CH0, - .rx = {.port = (XMC_GPIO_PORT_t *)PORT2_BASE, .pin = (uint8_t)15}, - .rx_config = {.mode = XMC_GPIO_MODE_INPUT_TRISTATE, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .output_strength = XMC_GPIO_OUTPUT_STRENGTH_STRONG_SOFT_EDGE}, - .tx = {.port = (XMC_GPIO_PORT_t *)PORT2_BASE, .pin = (uint8_t)14}, - .tx_config = {.mode = (XMC_GPIO_MODE_t)XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT2, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .output_strength = XMC_GPIO_OUTPUT_STRENGTH_STRONG_SOFT_EDGE}, - .input_source_dx0 = (XMC_USIC_INPUT_t)USIC1_C0_DX0_P2_15, - .input_source_dx1 = XMC_INPUT_INVALID, - .input_source_dx2 = XMC_INPUT_INVALID, - .input_source_dx3 = XMC_INPUT_INVALID, - .irq_num = USIC1_0_IRQn, - .irq_service_request = 0}; - -// Object instantiated of the HardwareSerial class for UART PC (debug) interface -HardwareSerial Serial(&XMC_UART_0, &rx_buffer_0, &tx_buffer_0); -// Object instantiated of the HardwareSerial class for UART ONBOARD interface -HardwareSerial Serial1(&XMC_UART_1, &rx_buffer_1, &tx_buffer_1); - -// SPI instance -XMC_SPI_t XMC_SPI_0 = { - .channel = XMC_SPI1_CH1, - .channel_config = {.baudrate = 20003906U, - .bus_mode = (XMC_SPI_CH_BUS_MODE_t)XMC_SPI_CH_BUS_MODE_MASTER, - .selo_inversion = XMC_SPI_CH_SLAVE_SEL_INV_TO_MSLS, - .parity_mode = XMC_USIC_CH_PARITY_MODE_NONE}, - .mosi = {.port = (XMC_GPIO_PORT_t *)PORT1_BASE, .pin = (uint8_t)9}, - .mosi_config = {.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT4, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .output_strength = XMC_GPIO_OUTPUT_STRENGTH_MEDIUM}, - .miso = {.port = (XMC_GPIO_PORT_t *)PORT0_BASE, .pin = (uint8_t)0}, - .miso_config = - { - .mode = XMC_GPIO_MODE_INPUT_TRISTATE, - }, - .input_source = XMC_INPUT_D, - .sclkout = {.port = (XMC_GPIO_PORT_t *)PORT1_BASE, .pin = (uint8_t)8}, - .sclkout_config = {.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT4, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .output_strength = XMC_GPIO_OUTPUT_STRENGTH_MEDIUM}, -}; - -// I2C instance -XMC_I2C_t XMC_I2C_0 = {.channel = XMC_I2C0_CH1, - .channel_config = {.baudrate = (uint32_t)(100000U), .address = 0U}, - .sda = {.port = (XMC_GPIO_PORT_t *)PORT2_BASE, .pin = (uint8_t)5}, - .sda_config = {.mode = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT2, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH}, - .scl = {.port = (XMC_GPIO_PORT_t *)PORT3_BASE, .pin = (uint8_t)0}, - .scl_config = {.mode = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT2, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH}, - .input_source_dx0 = XMC_INPUT_B, - .input_source_dx1 = XMC_INPUT_B, - .slave_receive_irq_num = (IRQn_Type)84, - .slave_receive_irq_service_request = 1, - .protocol_irq_num = (IRQn_Type)85, - .protocol_irq_service_request = 2}; - - // XMC CAN instance - #ifdef CAN_xmc -XMC_ARD_CAN_t XMC_CAN_0 = {.can_node = CAN_NODE0, - .can_node_num = XMC_NODE_NUM_0, - .can_clock = XMC_CAN_CANCLKSRC_FPERI, - .can_frequency = (uint32_t)144000000, - .rx = {.port = (XMC_GPIO_PORT_t *)PORT14_BASE, .pin = (uint8_t)3}, - .rx_config = {.mode = XMC_GPIO_MODE_INPUT_TRISTATE}, - .tx = {.port = (XMC_GPIO_PORT_t *)PORT2_BASE, .pin = (uint8_t)0}, - .tx_config = {.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT1}, - .node_input = CAN_NODE0_RXD_P14_3, - .irq_num = CAN0_7_IRQn, - .irq_service_request = 7u}; - #endif - - // Serial Interrupt and event handling - #ifdef __cplusplus -extern "C" { - #endif -void serialEventRun(); -void serialEvent() __attribute__((weak)); -void serialEvent1() __attribute__((weak)); - -void serialEventRun() { - if (serialEvent) { - if (Serial.available()) - serialEvent(); - } - if (serialEvent1) { - if (Serial1.available()) - serialEvent1(); - } -} - -// IRQ Handler of Serial Onboard (USIC1) -void USIC1_0_IRQHandler() { Serial1.IrqHandler(); } - -// IRQ Handler of Serial to PC USB (USIC0) -void USIC0_0_IRQHandler() { Serial.IrqHandler(); } - - #ifdef __cplusplus -} - #endif -#endif /* ARDUINO_MAIN*/ - -#ifdef __cplusplus -extern HardwareSerial Serial; -extern HardwareSerial Serial1; -#endif /* cplusplus */ -#endif diff --git a/variants/XMC4200/linker_script.ld b/variants/XMC4200/linker_script.ld deleted file mode 100644 index 6c17ab3d..00000000 --- a/variants/XMC4200/linker_script.ld +++ /dev/null @@ -1,286 +0,0 @@ -/** - * @file XMC4200x256.ld - * @date 2017-04-20 - * - * @cond - ********************************************************************************************************************* - * Linker file for the GNU C Compiler v1.8 - * Supported devices: XMC4200-F64x256 - * XMC4200-Q48x256 - * - * Copyright (c) 2015-2020, Infineon Technologies AG - * All rights reserved. - * - * Boost Software License - Version 1.0 - August 17th, 2003 - * - * Permission is hereby granted, free of charge, to any person or organization - * obtaining a copy of the software and accompanying documentation covered by - * this license (the "Software") to use, reproduce, display, distribute, - * execute, and transmit the Software, and to prepare derivative works of the - * Software, and to permit third-parties to whom the Software is furnished to - * do so, all subject to the following: - * - * The copyright notices in the Software and this entire statement, including - * the above license grant, this restriction and the following disclaimer, - * must be included in all copies of the Software, in whole or in part, and - * all derivative works of the Software, unless such copies or derivative - * works are solely in the form of machine-executable object code generated by - * a source language processor. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT - * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE - * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * To improve the quality of the software, users are encouraged to share - * modifications, enhancements or bug fixes with Infineon Technologies AG - * at XMCSupport@infineon.com. - ********************************************************************************************************************* - * - * Change History - * -------------- - * - * 2015-07-07: - * - Product splitting - * - Copyright notice update - * - * 2015-11-24: - * - Compatibility with GCC 4.9 2015q2 - * - * 2016-03-08: - * - Fix size of BSS and DATA sections to be multiple of 4 - * - Add assertion to check that region SRAM_combined does not overflowed no_init section - * - * 2017-04-07: - * - Added new symbols __text_size and eText - * - * 2017-04-20: - * - Change vtable location to flash area to save ram - * - * @endcond - * - */ - -OUTPUT_FORMAT("elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(Reset_Handler) - -MEMORY -{ - FLASH_1_cached(RX) : ORIGIN = 0x08000000, LENGTH = 0x40000 - FLASH_1_uncached(RX) : ORIGIN = 0x0C000000, LENGTH = 0x40000 - PSRAM_1(!RX) : ORIGIN = 0x1FFFC000, LENGTH = 0x4000 - DSRAM_1_system(!RX) : ORIGIN = 0x20000000, LENGTH = 0x6000 - SRAM_combined(!RX) : ORIGIN = 0x1FFFC000, LENGTH = 0xA000 -} - -stack_size = DEFINED(stack_size) ? stack_size : 2048; -no_init_size = 64; - -SECTIONS -{ - /* TEXT section */ - - .text : - { - sText = .; - KEEP(*(.reset)); - *(.text .text.* .gnu.linkonce.t.*); - - /* C++ Support */ - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata .rodata.*) - *(.gnu.linkonce.r*) - - *(vtable) - - . = ALIGN(4); - } > FLASH_1_cached AT > FLASH_1_uncached - - .eh_frame_hdr : ALIGN (4) - { - KEEP (*(.eh_frame_hdr)) - } > FLASH_1_cached AT > FLASH_1_uncached - - .eh_frame : ALIGN (4) - { - KEEP (*(.eh_frame)) - } > FLASH_1_cached AT > FLASH_1_uncached - - /* Exception handling, exidx needs a dedicated section */ - .ARM.extab : ALIGN(4) - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH_1_cached AT > FLASH_1_uncached - - . = ALIGN(4); - __exidx_start = .; - .ARM.exidx : ALIGN(4) - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH_1_cached AT > FLASH_1_uncached - __exidx_end = .; - . = ALIGN(4); - - /* DSRAM layout (Lowest to highest)*/ - Stack (NOLOAD) : - { - __stack_start = .; - . = . + stack_size; - __stack_end = .; - __initial_sp = .; - } > SRAM_combined - - /* functions with __attribute__((section(".ram_code"))) */ - .ram_code : - { - . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */ - __ram_code_start = .; - *(.ram_code) - . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */ - __ram_code_end = .; - } > SRAM_combined AT > FLASH_1_uncached - __ram_code_load = LOADADDR (.ram_code); - __ram_code_size = __ram_code_end - __ram_code_start; - - /* Standard DATA and user defined DATA/BSS/CONST sections */ - .data : - { - . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */ - __data_start = .; - * (.data); - * (.data*); - *(*.data); - *(.gnu.linkonce.d*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */ - __data_end = .; - } > SRAM_combined AT > FLASH_1_uncached - __data_load = LOADADDR (.data); - __data_size = __data_end - __data_start; - - __text_size = (__exidx_end - sText) + __data_size + __ram_code_size; - eText = sText + __text_size; - - /* BSS section */ - .bss (NOLOAD) : - { - . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */ - __bss_start = .; - * (.bss); - * (.bss*); - * (COMMON); - *(.gnu.linkonce.b*) - . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */ - __bss_end = .; - } > SRAM_combined - __bss_size = __bss_end - __bss_start; - - /* Shift location counter, so that ETH_RAM and USB_RAM are located above DSRAM_1_system */ - __shift_loc = (__bss_end >= ORIGIN(DSRAM_1_system)) ? 0 : (ORIGIN(DSRAM_1_system) - __bss_end); - - USB_RAM (__bss_end + __shift_loc) (NOLOAD) : - { - . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */ - USB_RAM_start = .; - *(USB_RAM) - . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */ - USB_RAM_end = .; - . = ALIGN(8); - Heap_Bank1_Start = .; - } > SRAM_combined - USB_RAM_size = USB_RAM_end - USB_RAM_start; - - /* .no_init section contains chipid, SystemCoreClock and trimming data. See system.c file */ - .no_init ORIGIN(SRAM_combined) + LENGTH(SRAM_combined) - no_init_size (NOLOAD) : - { - Heap_Bank1_End = .; - * (.no_init); - } > SRAM_combined - - /* Heap - Bank1*/ - Heap_Bank1_Size = Heap_Bank1_End - Heap_Bank1_Start; - - ASSERT(Heap_Bank1_Start <= Heap_Bank1_End, "region SRAM_combined overflowed no_init section") - - /DISCARD/ : - { - *(.comment) - } - - .stab 0 (NOLOAD) : { *(.stab) } - .stabstr 0 (NOLOAD) : { *(.stabstr) } - - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_pubtypes 0 : { *(.debug_pubtypes) } - - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - - /* DWARF 2.1 */ - .debug_ranges 0 : { *(.debug_ranges) } - - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - - /* Build attributes */ - .build_attributes 0 : { *(.ARM.attributes) } -} diff --git a/variants/XMC4200/startup_XMC4200.S b/variants/XMC4200/startup_XMC4200.S deleted file mode 100644 index 362c9ea6..00000000 --- a/variants/XMC4200/startup_XMC4200.S +++ /dev/null @@ -1,434 +0,0 @@ -/********************************************************************************************************************* - * @file startup_XMC4200.S - * @brief CMSIS Core Device Startup File for Infineon XMC4200 Device Series - * @version V1.1 - * @date 15 Mai 2020 - * - * @cond - ********************************************************************************************************************* - * Copyright (c) 2012-2020, Infineon Technologies AG - * All rights reserved. - * - * Boost Software License - Version 1.0 - August 17th, 2003 - * - * Permission is hereby granted, free of charge, to any person or organization - * obtaining a copy of the software and accompanying documentation covered by - * this license (the "Software") to use, reproduce, display, distribute, - * execute, and transmit the Software, and to prepare derivative works of the - * Software, and to permit third-parties to whom the Software is furnished to - * do so, all subject to the following: - * - * The copyright notices in the Software and this entire statement, including - * the above license grant, this restriction and the following disclaimer, - * must be included in all copies of the Software, in whole or in part, and - * all derivative works of the Software, unless such copies or derivative - * works are solely in the form of machine-executable object code generated by - * a source language processor. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT - * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE - * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * To improve the quality of the software, users are encouraged to share - * modifications, enhancements or bug fixes with Infineon Technologies AG - * at XMCSupport@infineon.com. - ********************************************************************************************************************* - * - **************************** Change history ******************************** - * V0.1,Sep, 13, 2012 ES : initial version - * V0.2,Oct, 12, 2012 PKB: C++ support - * V0.3,Jan, 26, 2013 PKB: Workaround for prefetch bug - * V0.4,Jul, 29, 2013 PKB: AAPCS violation in V0.3 fixed - * V0.5,Feb, 05, 2014 PKB: Removed redundant alignment code from copy+clear funcs - * V0.6,May, 05, 2014 JFT: Added ram_code section - * V0.7,Nov, 25, 2014 JFT: CPU workaround disabled. Single default handler. - * Removed DAVE3 dependency - * V0.8,Jan, 05, 2016 JFT: Fix .reset section attributes - * V0.9,March,04,2016 JFT: Fix weak definition of Veneers. - * Only relevant for AA, which needs ENABLE_PMU_CM_001_WORKAROUND - * V1.0,June ,01,2016 JFT: Rename ENABLE_CPU_CM_001_WORKAROUND to ENABLE_PMU_CM_001_WORKAROUND - * Action required: If using AA step, use ENABLE_PMU_CM_001_WORKAROUND instead of ENABLE_CPU_CM_001_WORKAROUND - * V1.1,Mai, 15, 2020 JFT:Added option (ENABLE_OWN_HANDLER) to generate a individual interrupt handlers for unhandled vectors - * @endcond - */ - -/* ===========START : MACRO DEFINITION MACRO DEFINITION ================== */ - -.macro Entry Handler -#if defined(ENABLE_PMU_CM_001_WORKAROUND) - .long \Handler\()_Veneer -#else - .long \Handler -#endif -.endm - -.macro Insert_ExceptionHandler Handler_Func - .weak \Handler_Func -#if defined(ENABLE_OWN_HANDLER) - .thumb_func - .type \Handler_Func, %function -\Handler_Func: - b . - .size \Handler_Func, . - \Handler_Func -#else - .thumb_set \Handler_Func, Default_Handler -#endif - -#if defined(ENABLE_PMU_CM_001_WORKAROUND) - .weak \Handler_Func\()_Veneer - .type \Handler_Func\()_Veneer, %function -\Handler_Func\()_Veneer: - push {r0, lr} - ldr r0, =\Handler_Func - blx r0 - pop {r0, pc} - .size \Handler_Func\()_Veneer, . - \Handler_Func\()_Veneer -#endif -.endm - -/* =============END : MACRO DEFINITION MACRO DEFINITION ================== */ - -/* ================== START OF VECTOR TABLE DEFINITION ====================== */ -/* Vector Table - This gets programed into VTOR register by onchip BootROM */ - .syntax unified - - .section .reset, "a", %progbits - - .align 2 - .globl __Vectors - .type __Vectors, %object -__Vectors: - .long __initial_sp /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - - Entry NMI_Handler /* NMI Handler */ - Entry HardFault_Handler /* Hard Fault Handler */ - Entry MemManage_Handler /* MPU Fault Handler */ - Entry BusFault_Handler /* Bus Fault Handler */ - Entry UsageFault_Handler /* Usage Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - Entry SVC_Handler /* SVCall Handler */ - Entry DebugMon_Handler /* Debug Monitor Handler */ - .long 0 /* Reserved */ - Entry PendSV_Handler /* PendSV Handler */ - Entry SysTick_Handler /* SysTick Handler */ - - /* Interrupt Handlers for Service Requests (SR) from XMC4200 Peripherals */ - Entry SCU_0_IRQHandler /* Handler name for SR SCU_0 */ - Entry ERU0_0_IRQHandler /* Handler name for SR ERU0_0 */ - Entry ERU0_1_IRQHandler /* Handler name for SR ERU0_1 */ - Entry ERU0_2_IRQHandler /* Handler name for SR ERU0_2 */ - Entry ERU0_3_IRQHandler /* Handler name for SR ERU0_3 */ - Entry ERU1_0_IRQHandler /* Handler name for SR ERU1_0 */ - Entry ERU1_1_IRQHandler /* Handler name for SR ERU1_1 */ - Entry ERU1_2_IRQHandler /* Handler name for SR ERU1_2 */ - Entry ERU1_3_IRQHandler /* Handler name for SR ERU1_3 */ - .long 0 /* Not Available */ - .long 0 /* Not Available */ - .long 0 /* Not Available */ - Entry PMU0_0_IRQHandler /* Handler name for SR PMU0_0 */ - .long 0 /* Not Available */ - Entry VADC0_C0_0_IRQHandler /* Handler name for SR VADC0_C0_0 */ - Entry VADC0_C0_1_IRQHandler /* Handler name for SR VADC0_C0_1 */ - Entry VADC0_C0_2_IRQHandler /* Handler name for SR VADC0_C0_1 */ - Entry VADC0_C0_3_IRQHandler /* Handler name for SR VADC0_C0_3 */ - Entry VADC0_G0_0_IRQHandler /* Handler name for SR VADC0_G0_0 */ - Entry VADC0_G0_1_IRQHandler /* Handler name for SR VADC0_G0_1 */ - Entry VADC0_G0_2_IRQHandler /* Handler name for SR VADC0_G0_2 */ - Entry VADC0_G0_3_IRQHandler /* Handler name for SR VADC0_G0_3 */ - Entry VADC0_G1_0_IRQHandler /* Handler name for SR VADC0_G1_0 */ - Entry VADC0_G1_1_IRQHandler /* Handler name for SR VADC0_G1_1 */ - Entry VADC0_G1_2_IRQHandler /* Handler name for SR VADC0_G1_2 */ - Entry VADC0_G1_3_IRQHandler /* Handler name for SR VADC0_G1_3 */ - .long 0 /* Not Available */ - .long 0 /* Not Available */ - .long 0 /* Not Available */ - .long 0 /* Not Available */ - .long 0 /* Not Available */ - .long 0 /* Not Available */ - .long 0 /* Not Available */ - .long 0 /* Not Available */ - .long 0 /* Not Available */ - .long 0 /* Not Available */ - .long 0 /* Not Available */ - .long 0 /* Not Available */ - .long 0 /* Not Available */ - .long 0 /* Not Available */ - .long 0 /* Not Available */ - .long 0 /* Not Available */ - Entry DAC0_0_IRQHandler /* Handler name for SR DAC0_0 */ - Entry DAC0_1_IRQHandler /* Handler name for SR DAC0_1 */ - Entry CCU40_0_IRQHandler /* Handler name for SR CCU40_0 */ - Entry CCU40_1_IRQHandler /* Handler name for SR CCU40_1 */ - Entry CCU40_2_IRQHandler /* Handler name for SR CCU40_2 */ - Entry CCU40_3_IRQHandler /* Handler name for SR CCU40_3 */ - Entry CCU41_0_IRQHandler /* Handler name for SR CCU41_0 */ - Entry CCU41_1_IRQHandler /* Handler name for SR CCU41_1 */ - Entry CCU41_2_IRQHandler /* Handler name for SR CCU41_2 */ - Entry CCU41_3_IRQHandler /* Handler name for SR CCU41_3 */ - .long 0 /* Not Available */ - .long 0 /* Not Available */ - .long 0 /* Not Available */ - .long 0 /* Not Available */ - .long 0 /* Not Available */ - .long 0 /* Not Available */ - .long 0 /* Not Available */ - .long 0 /* Not Available */ - Entry CCU80_0_IRQHandler /* Handler name for SR CCU80_0 */ - Entry CCU80_1_IRQHandler /* Handler name for SR CCU80_1 */ - Entry CCU80_2_IRQHandler /* Handler name for SR CCU80_2 */ - Entry CCU80_3_IRQHandler /* Handler name for SR CCU80_3 */ - .long 0 /* Not Available */ - .long 0 /* Not Available */ - .long 0 /* Not Available */ - .long 0 /* Not Available */ - Entry POSIF0_0_IRQHandler /* Handler name for SR POSIF0_0 */ - Entry POSIF0_1_IRQHandler /* Handler name for SR POSIF0_1 */ - .long 0 /* Not Available */ - .long 0 /* Not Available */ - Entry HRPWM_0_IRQHandler /* Handler name for SR HRPWM_0 */ - Entry HRPWM_1_IRQHandler /* Handler name for SR HRPWM_1 */ - Entry HRPWM_2_IRQHandler /* Handler name for SR HRPWM_2 */ - Entry HRPWM_3_IRQHandler /* Handler name for SR HRPWM_3 */ - Entry CAN0_0_IRQHandler /* Handler name for SR CAN0_0 */ - Entry CAN0_1_IRQHandler /* Handler name for SR CAN0_1 */ - Entry CAN0_2_IRQHandler /* Handler name for SR CAN0_2 */ - Entry CAN0_3_IRQHandler /* Handler name for SR CAN0_3 */ - Entry CAN0_4_IRQHandler /* Handler name for SR CAN0_4 */ - Entry CAN0_5_IRQHandler /* Handler name for SR CAN0_5 */ - Entry CAN0_6_IRQHandler /* Handler name for SR CAN0_6 */ - Entry CAN0_7_IRQHandler /* Handler name for SR CAN0_7 */ - Entry USIC0_0_IRQHandler /* Handler name for SR USIC0_0 */ - Entry USIC0_1_IRQHandler /* Handler name for SR USIC0_1 */ - Entry USIC0_2_IRQHandler /* Handler name for SR USIC0_2 */ - Entry USIC0_3_IRQHandler /* Handler name for SR USIC0_3 */ - Entry USIC0_4_IRQHandler /* Handler name for SR USIC0_4 */ - Entry USIC0_5_IRQHandler /* Handler name for SR USIC0_5 */ - Entry USIC1_0_IRQHandler /* Handler name for SR USIC1_0 */ - Entry USIC1_1_IRQHandler /* Handler name for SR USIC1_1 */ - Entry USIC1_2_IRQHandler /* Handler name for SR USIC1_2 */ - Entry USIC1_3_IRQHandler /* Handler name for SR USIC1_3 */ - Entry USIC1_4_IRQHandler /* Handler name for SR USIC1_4 */ - Entry USIC1_5_IRQHandler /* Handler name for SR USIC1_5 */ - .long 0 /* Not Available */ - .long 0 /* Not Available */ - .long 0 /* Not Available */ - .long 0 /* Not Available */ - .long 0 /* Not Available */ - .long 0 /* Not Available */ - Entry LEDTS0_0_IRQHandler /* Handler name for SR LEDTS0_0 */ - .long 0 /* Not Available */ - Entry FCE0_0_IRQHandler /* Handler name for SR FCE0_0 */ - Entry GPDMA0_0_IRQHandler /* Handler name for SR GPDMA0_0 */ - .long 0 /* Not Available */ - Entry USB0_0_IRQHandler /* Handler name for SR USB0_0 */ - .long 0 /* Not Available */ - .long 0 /* Not Available */ - .long 0 /* Not Available */ - .long 0 /* Not Available */ - - .size __Vectors, . - __Vectors -/* ================== END OF VECTOR TABLE DEFINITION ======================= */ - -/* ================== START OF VECTOR ROUTINES ============================= */ - - .align 1 - .thumb - -/* Reset Handler */ - .thumb_func - .globl Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - ldr sp,=__initial_sp - -#ifndef __SKIP_SYSTEM_INIT - ldr r0, =SystemInit - blx r0 -#endif - -/* Initialize data - * - * Between symbol address __copy_table_start__ and __copy_table_end__, - * there are array of triplets, each of which specify: - * offset 0: LMA of start of a section to copy from - * offset 4: VMA of start of a section to copy to - * offset 8: size of the section to copy. Must be multiply of 4 - * - * All addresses must be aligned to 4 bytes boundary. - */ - ldr r4, =__copy_table_start__ - ldr r5, =__copy_table_end__ - -.L_loop0: - cmp r4, r5 - bge .L_loop0_done - ldr r1, [r4] - ldr r2, [r4, #4] - ldr r3, [r4, #8] - -.L_loop0_0: - subs r3, #4 - ittt ge - ldrge r0, [r1, r3] - strge r0, [r2, r3] - bge .L_loop0_0 - - adds r4, #12 - b .L_loop0 - -.L_loop0_done: - -/* Zero initialized data - * Between symbol address __zero_table_start__ and __zero_table_end__, - * there are array of tuples specifying: - * offset 0: Start of a BSS section - * offset 4: Size of this BSS section. Must be multiply of 4 - * - * Define __SKIP_BSS_CLEAR to disable zeroing uninitialzed data in startup. - */ -#ifndef __SKIP_BSS_CLEAR - ldr r3, =__zero_table_start__ - ldr r4, =__zero_table_end__ - -.L_loop2: - cmp r3, r4 - bge .L_loop2_done - ldr r1, [r3] - ldr r2, [r3, #4] - movs r0, 0 - -.L_loop2_0: - subs r2, #4 - itt ge - strge r0, [r1, r2] - bge .L_loop2_0 - - adds r3, #8 - b .L_loop2 -.L_loop2_done: -#endif /* __SKIP_BSS_CLEAR */ - -#ifndef __SKIP_LIBC_INIT_ARRAY - ldr r0, =__libc_init_array - blx r0 -#endif - - ldr r0, =main - blx r0 - -.align 2 -__copy_table_start__: - .long __data_load, __data_start, __data_size - .long __ram_code_load, __ram_code_start, __ram_code_size -__copy_table_end__: - -__zero_table_start__: - .long __bss_start, __bss_size - .long USB_RAM_start, USB_RAM_size -__zero_table_end__: - - .pool - .size Reset_Handler,.-Reset_Handler - -/* ======================================================================== */ -/* ========== START OF EXCEPTION HANDLER DEFINITION ======================== */ - -/* Default exception Handlers - Users may override this default functionality by - defining handlers of the same name in their C code */ - - .align 1 - .thumb_func - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - b . - .size Default_Handler, . - Default_Handler - - Insert_ExceptionHandler NMI_Handler - Insert_ExceptionHandler HardFault_Handler - Insert_ExceptionHandler MemManage_Handler - Insert_ExceptionHandler BusFault_Handler - Insert_ExceptionHandler UsageFault_Handler - Insert_ExceptionHandler SVC_Handler - Insert_ExceptionHandler DebugMon_Handler - Insert_ExceptionHandler PendSV_Handler - Insert_ExceptionHandler SysTick_Handler - - Insert_ExceptionHandler SCU_0_IRQHandler - Insert_ExceptionHandler ERU0_0_IRQHandler - Insert_ExceptionHandler ERU0_1_IRQHandler - Insert_ExceptionHandler ERU0_2_IRQHandler - Insert_ExceptionHandler ERU0_3_IRQHandler - Insert_ExceptionHandler ERU1_0_IRQHandler - Insert_ExceptionHandler ERU1_1_IRQHandler - Insert_ExceptionHandler ERU1_2_IRQHandler - Insert_ExceptionHandler ERU1_3_IRQHandler - Insert_ExceptionHandler PMU0_0_IRQHandler - Insert_ExceptionHandler VADC0_C0_0_IRQHandler - Insert_ExceptionHandler VADC0_C0_1_IRQHandler - Insert_ExceptionHandler VADC0_C0_2_IRQHandler - Insert_ExceptionHandler VADC0_C0_3_IRQHandler - Insert_ExceptionHandler VADC0_G0_0_IRQHandler - Insert_ExceptionHandler VADC0_G0_1_IRQHandler - Insert_ExceptionHandler VADC0_G0_2_IRQHandler - Insert_ExceptionHandler VADC0_G0_3_IRQHandler - Insert_ExceptionHandler VADC0_G1_0_IRQHandler - Insert_ExceptionHandler VADC0_G1_1_IRQHandler - Insert_ExceptionHandler VADC0_G1_2_IRQHandler - Insert_ExceptionHandler VADC0_G1_3_IRQHandler - Insert_ExceptionHandler DAC0_0_IRQHandler - Insert_ExceptionHandler DAC0_1_IRQHandler - Insert_ExceptionHandler CCU40_0_IRQHandler - Insert_ExceptionHandler CCU40_1_IRQHandler - Insert_ExceptionHandler CCU40_2_IRQHandler - Insert_ExceptionHandler CCU40_3_IRQHandler - Insert_ExceptionHandler CCU41_0_IRQHandler - Insert_ExceptionHandler CCU41_1_IRQHandler - Insert_ExceptionHandler CCU41_2_IRQHandler - Insert_ExceptionHandler CCU41_3_IRQHandler - Insert_ExceptionHandler CCU80_0_IRQHandler - Insert_ExceptionHandler CCU80_1_IRQHandler - Insert_ExceptionHandler CCU80_2_IRQHandler - Insert_ExceptionHandler CCU80_3_IRQHandler - Insert_ExceptionHandler POSIF0_0_IRQHandler - Insert_ExceptionHandler POSIF0_1_IRQHandler - Insert_ExceptionHandler HRPWM_0_IRQHandler - Insert_ExceptionHandler HRPWM_1_IRQHandler - Insert_ExceptionHandler HRPWM_2_IRQHandler - Insert_ExceptionHandler HRPWM_3_IRQHandler - Insert_ExceptionHandler CAN0_0_IRQHandler - Insert_ExceptionHandler CAN0_1_IRQHandler - Insert_ExceptionHandler CAN0_2_IRQHandler - Insert_ExceptionHandler CAN0_3_IRQHandler - Insert_ExceptionHandler CAN0_4_IRQHandler - Insert_ExceptionHandler CAN0_5_IRQHandler - Insert_ExceptionHandler CAN0_6_IRQHandler - Insert_ExceptionHandler CAN0_7_IRQHandler - Insert_ExceptionHandler USIC0_0_IRQHandler - Insert_ExceptionHandler USIC0_1_IRQHandler - Insert_ExceptionHandler USIC0_2_IRQHandler - Insert_ExceptionHandler USIC0_3_IRQHandler - Insert_ExceptionHandler USIC0_4_IRQHandler - Insert_ExceptionHandler USIC0_5_IRQHandler - Insert_ExceptionHandler USIC1_0_IRQHandler - Insert_ExceptionHandler USIC1_1_IRQHandler - Insert_ExceptionHandler USIC1_2_IRQHandler - Insert_ExceptionHandler USIC1_3_IRQHandler - Insert_ExceptionHandler USIC1_4_IRQHandler - Insert_ExceptionHandler USIC1_5_IRQHandler - Insert_ExceptionHandler LEDTS0_0_IRQHandler - Insert_ExceptionHandler FCE0_0_IRQHandler - Insert_ExceptionHandler GPDMA0_0_IRQHandler - Insert_ExceptionHandler USB0_0_IRQHandler - -/* ============= END OF INTERRUPT HANDLER DEFINITION ====================== */ - - .end diff --git a/variants/XMC4200/system_XMC4200.c b/variants/XMC4200/system_XMC4200.c deleted file mode 100644 index 96513119..00000000 --- a/variants/XMC4200/system_XMC4200.c +++ /dev/null @@ -1,696 +0,0 @@ -/********************************************************************************************************************* - * @file system_XMC4200.c - * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File for the Infineon XMC4200 - *Device Series - * @version V3.1.6 - * @date 27. Aug 2020 - * - * @cond - ********************************************************************************************************************* - * Copyright (c) 2015-2020, Infineon Technologies AG - * All rights reserved. - * - * Boost Software License - Version 1.0 - August 17th, 2003 - * - * Permission is hereby granted, free of charge, to any person or organization - * obtaining a copy of the software and accompanying documentation covered by - * this license (the "Software") to use, reproduce, display, distribute, - * execute, and transmit the Software, and to prepare derivative works of the - * Software, and to permit third-parties to whom the Software is furnished to - * do so, all subject to the following: - * - * The copyright notices in the Software and this entire statement, including - * the above license grant, this restriction and the following disclaimer, - * must be included in all copies of the Software, in whole or in part, and - * all derivative works of the Software, unless such copies or derivative - * works are solely in the form of machine-executable object code generated by - * a source language processor. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT - * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE - * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * To improve the quality of the software, users are encouraged to share - * modifications, enhancements or bug fixes with Infineon Technologies AG - * at XMCSupport@infineon.com. - ********************************************************************************************************************* - * - ********************** Version History *************************************** - * V3.1.0, Dec 2014, Added options to configure clock settings - * V3.1.1, 01. Jun 2016, Fix masking of OSCHPCTRL value - * V3.1.2, 19. Jun 2017, Rely on cmsis_compiler.h instead of defining __WEAK - * Added support for ARM Compiler 6 (armclang) - * V3.1.3, 26. Sep 2017, Disable FPU if FPU_USED is zero - * V3.1.4, 29. Oct 2018, Fix variable location of SystemCoreClock, g_hrpwm_char_data and g_chipid - *for ARMCC compiler V3.1.5, 02. Dec 2019, Fix including device header file following the - *convention: angle brackets are used for standard includes and double quotes for everything else. - * Fix EXTCLKDIV macro definition - * Fix code for condition EXTCLK_PIN == EXTCLK_PIN_P1_15 - * V3.1.6, 27. Aug 2020. Fix K1 divider input clock for PLL in prescaler mode - * Added compiler checks for input VCO and VCO frequencies - * Added wait for K2 divider ready after updating the K2 divider in the PLL - *ramp up Removed wait for lock after changing the K2 divider in the PLL ramp up since a - *modification of the K2-divider has no impact on the VCO Lock status Use P,N,K2 even values - *dividers for system PLL to minimize jitter (for the case of external clock 12MHz) Use P,N,K2 value - *dividers for system PLL when running out of internal oscillator that centers the input frequency - *of the VCO to 6MHz instead of 4MHz (minimum value in DS) - ****************************************************************************** - * @endcond - */ - -/******************************************************************************* - * HEADER FILES - *******************************************************************************/ -#include - -#include "XMC4200.h" -#include "system_XMC4200.h" - -/******************************************************************************* - * MACROS - *******************************************************************************/ -#define CHIPID_LOC ((uint8_t *)0x20000000UL) -#define HRPWM_CHARDATA_LOC ((uint8_t *)0x20000084UL) - -#define PMU_FLASH_WS (0x2U) -#define FPLL_FREQUENCY (80000000U) -#define FOSCREF (2500000U) -#define DELAY_CNT_50US_50MHZ (2500UL) -#define DELAY_CNT_150US_50MHZ (7500UL) -#define DELAY_CNT_50US_60MHZ (3000UL) -#define DELAY_CNT_50US_80MHZ (4000UL) - -#define VCO_INPUT_MIN (4000000UL) -#define VCO_INPUT_MAX (16000000UL) -#define VCO_MIN (260000000UL) -#define VCO_MAX (520000000UL) - -#define SCU_PLL_PLLSTAT_OSC_USABLE \ - (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk | SCU_PLL_PLLSTAT_PLLSP_Msk) - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -*/ - -/* -// Clock configuration -*/ - -/* -// External crystal frequency [Hz] -// <8000000=> 8MHz -// <12000000=> 12MHz -// <16000000=> 16MHz -// Defines external crystal frequency -// Default: 8MHz -*/ -#define OSCHP_FREQUENCY (12000000U) - -#if OSCHP_FREQUENCY == 8000000U - #define USB_PDIV (1U) - #define USB_NDIV (95U) - #define USB_DIV (3U) - -#elif OSCHP_FREQUENCY == 12000000U - #define USB_PDIV (1U) - #define USB_NDIV (63U) - #define USB_DIV (3U) - -#elif OSCHP_FREQUENCY == 16000000U - #define USB_PDIV (1U) - #define USB_NDIV (47U) - #define USB_DIV (3U) - -#else - #error "External crystal frequency not supported" - -#endif - -#define USB_VCO ((OSCHP_FREQUENCY / (USB_PDIV + 1UL)) * (USB_NDIV + 1UL)) -#define USB_VCO_INPUT (OSCHP_FREQUENCY / (USB_PDIV + 1UL)) - -/* -// System clock (fSYS) source selection -// <0=> Backup clock (24MHz) -// <1=> Maximum clock frequency using PLL (80MHz) -// Default: Maximum clock frequency using PLL (80MHz) -*/ -#define SYS_CLOCK_SRC 1 -#define SYS_CLOCK_SRC_OFI 0 -#define SYS_CLOCK_SRC_PLL 1 - -/* -// Backup clock calibration mode -// <0=> Factory calibration -// <1=> Automatic calibration -// Default: Automatic calibration -*/ -#define FOFI_CALIBRATION_MODE 1 -#define FOFI_CALIBRATION_MODE_FACTORY 0 -#define FOFI_CALIBRATION_MODE_AUTOMATIC 1 - -/* -// Standby clock (fSTDBY) source selection -// <0=> Internal slow oscillator (32768Hz) -// <1=> External crystal (32768Hz) -// Default: Internal slow oscillator (32768Hz) -*/ -#define STDBY_CLOCK_SRC 0 -#define STDBY_CLOCK_SRC_OSI 0 -#define STDBY_CLOCK_SRC_OSCULP 1 - -/* -// PLL clock source selection -// <0=> External crystal -// <1=> External direct input -// <2=> Internal fast oscillator -// Default: External crystal -*/ -#define PLL_CLOCK_SRC 0 -#define PLL_CLOCK_SRC_EXT_XTAL 0 -#define PLL_CLOCK_SRC_EXT_DIRECT 1 -#define PLL_CLOCK_SRC_OFI 2 - -#if PLL_CLOCK_SRC == PLL_CLOCK_SRC_EXT_XTAL - #if OSCHP_FREQUENCY == 8000000U - #define PLL_PDIV (1U) - #define PLL_NDIV (79U) - #define PLL_K2DIV (3U) - - #elif OSCHP_FREQUENCY == 12000000U - #define PLL_PDIV (1U) - #define PLL_NDIV (79U) - #define PLL_K2DIV (5U) - - #elif OSCHP_FREQUENCY == 16000000U - #define PLL_PDIV (1U) - #define PLL_NDIV (39U) - #define PLL_K2DIV (3U) - - #else - #error "External crystal frequency not supported" - - #endif - - #define VCO ((OSCHP_FREQUENCY / (PLL_PDIV + 1UL)) * (PLL_NDIV + 1UL)) - #define VCO_INPUT (OSCHP_FREQUENCY / (PLL_PDIV + 1UL)) - -#else /* PLL_CLOCK_SRC == PLL_CLOCK_SRC_EXT_XTAL */ - #define PLL_PDIV (3U) - #define PLL_NDIV (79U) - #define PLL_K2DIV (5U) - - #define VCO ((OFI_FREQUENCY / (PLL_PDIV + 1UL)) * (PLL_NDIV + 1UL)) - #define VCO_INPUT (OFI_FREQUENCY / (PLL_PDIV + 1UL)) - -#endif /* PLL_CLOCK_SRC == PLL_CLOCK_SRC_OFI */ - -#if (VCO_INPUT < VCO_INPUT_MIN) || (VCO_INPUT > VCO_INPUT_MAX) - #error VCO_INPUT frequency out of range. -#endif - -#if (VCO < VCO_MIN) || (VCO > VCO_MAX) - #error VCO frequency out of range. -#endif - -#if (USB_VCO_INPUT < VCO_INPUT_MIN) || (USB_VCO_INPUT > VCO_INPUT_MAX) - #error USB_VCO_INPUT frequency out of range. -#endif - -#if (USB_VCO < VCO_MIN) || (USB_VCO > VCO_MAX) - #error USB_VCO frequency out of range. -#endif - -#define PLL_K2DIV_0 ((VCO / OFI_FREQUENCY) - 1UL) -#define PLL_K2DIV_1 ((VCO / 60000000U) - 1UL) - -#define SCU_CLK_CLKCLR_ENABLE_USBCLK SCU_CLK_CLKCLR_USBCDI_Msk -#define SCU_CLK_CLKCLR_ENABLE_CCUCLK SCU_CLK_CLKCLR_CCUCDI_Msk -#define SCU_CLK_CLKCLR_ENABLE_WDTCLK SCU_CLK_CLKCLR_WDTCDI_Msk - -#define SCU_CLK_USBCLKCR_USBSEL_USBPLL (0U << SCU_CLK_USBCLKCR_USBSEL_Pos) -#define SCU_CLK_USBCLKCR_USBSEL_PLL (1U << SCU_CLK_USBCLKCR_USBSEL_Pos) - -#define SCU_CLK_WDTCLKCR_WDTSEL_OFI (0U << SCU_CLK_WDTCLKCR_WDTSEL_Pos) -#define SCU_CLK_WDTCLKCR_WDTSEL_STANDBY (1U << SCU_CLK_WDTCLKCR_WDTSEL_Pos) -#define SCU_CLK_WDTCLKCR_WDTSEL_PLL (2U << SCU_CLK_WDTCLKCR_WDTSEL_Pos) - -#define SCU_CLK_EXTCLKCR_ECKSEL_SYS (0U << SCU_CLK_EXTCLKCR_ECKSEL_Pos) -#define SCU_CLK_EXTCLKCR_ECKSEL_USBPLL (2U << SCU_CLK_EXTCLKCR_ECKSEL_Pos) -#define SCU_CLK_EXTCLKCR_ECKSEL_PLL (3U << SCU_CLK_EXTCLKCR_ECKSEL_Pos) -#define SCU_CLK_EXTCLKCR_ECKSEL_STANDBY (4U << SCU_CLK_EXTCLKCR_ECKSEL_Pos) - -#define EXTCLK_PIN_P0_8 (0) -#define EXTCLK_PIN_P1_15 (1) - -/* -// Clock tree -// CPU clock divider -// <0=> fCPU = fSYS -// <1=> fCPU = fSYS / 2 -// Peripheral clock divider -// <0=> fPB = fCPU -// <1=> fPB = fCPU / 2 -// Enable CCU clock -// CCU clock divider -// <0=> fCCU = fCPU -// <1=> fCCU = fCPU / 2 -// -// Enable WDT clock -// WDT clock divider <1-256><#-1> -// WDT clock source <0=> fOFI -// <1=> fSTDBY -// <2=> fPLL -// -// Enable USB clock -// USB clock source <0=> USBPLL -// <1=> PLL -// -// External Clock configuration -// External clock source selection -// <0=> System clock -// <2=> USB PLL clock -// <3=> PLL clock -// <4=> Standby clock -// External clock divider <1-512><#-1> -// Only valid for USB PLL and PLL clocks -// External Pin Selection -// <0=> P0.8 -// <1=> P1.15 -// -// -*/ -#define ENABLE_SCUCLK (0U) -#define CPUCLKDIV (0U) -#define PBCLKDIV (0U) -#define CCUCLKDIV (0U) -#define WDTCLKDIV (0U | SCU_CLK_WDTCLKCR_WDTSEL_OFI) -#define USBCLKDIV (0U | SCU_CLK_USBCLKCR_USBSEL_USBPLL | USB_DIV) - -#define ENABLE_EXTCLK (0U) -#define EXTCLKDIV ((0U << SCU_CLK_EXTCLKCR_ECKDIV_Pos) | SCU_CLK_EXTCLKCR_ECKSEL_SYS) -#define EXTCLK_PIN (0U) - -#define ENABLE_PLL \ - (SYS_CLOCK_SRC == SYS_CLOCK_SRC_PLL) || \ - (((ENABLE_SCUCLK & SCU_CLK_CLKSET_USBCEN_Msk) != 0) && \ - ((USBCLKDIV & SCU_CLK_USBCLKCR_USBSEL_Msk) == SCU_CLK_USBCLKCR_USBSEL_PLL)) || \ - (((ENABLE_SCUCLK & SCU_CLK_CLKSET_WDTCEN_Msk) != 0) && \ - ((WDTCLKDIV & SCU_CLK_WDTCLKCR_WDTSEL_Msk) == SCU_CLK_WDTCLKCR_WDTSEL_PLL)) - -/* -// -*/ - -/* -//-------- <<< end of configuration section >>> ------------------ -*/ - -/******************************************************************************* - * GLOBAL VARIABLES - *******************************************************************************/ -#if defined(__CC_ARM) -uint32_t SystemCoreClock __attribute__((at(0x20005FC0))); -uint8_t g_chipid[16] __attribute__((at(0x20005FC4))); -uint32_t g_hrpwm_char_data[3] __attribute__((at(0x20005FD4))); -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -uint32_t SystemCoreClock __attribute__((section(".bss.ARM.__at_0x20005FC0"))); -uint8_t g_chipid[16] __attribute__((section(".bss.ARM.__at_0x20005FC4"))); -uint32_t g_hrpwm_char_data[3] __attribute__((section(".bss.ARM.__at_0x20005FD4"))); -#elif defined(__ICCARM__) -__no_init uint32_t SystemCoreClock; -__no_init uint8_t g_chipid[16]; -__no_init uint32_t g_hrpwm_char_data[3]; -#elif defined(__GNUC__) -uint32_t SystemCoreClock __attribute__((section(".no_init"))); -uint8_t g_chipid[16] __attribute__((section(".no_init"))); -uint32_t g_hrpwm_char_data[3] __attribute__((section(".no_init"))); -#elif defined(__TASKING__) -uint32_t SystemCoreClock __at(0x20005FC0); -uint8_t g_chipid[16] __at(0x20005FC4); -uint32_t g_hrpwm_char_data[3] __at(0x20005FD4); -#endif - -extern uint32_t __Vectors; - -/******************************************************************************* - * LOCAL FUNCTIONS - *******************************************************************************/ -static void delay(uint32_t cycles) { - volatile uint32_t i; - - for (i = 0UL; i < cycles; ++i) { - __NOP(); - } -} - -/******************************************************************************* - * API IMPLEMENTATION - *******************************************************************************/ - -__WEAK void SystemInit(void) { - memcpy(g_chipid, CHIPID_LOC, 16); - memcpy(g_hrpwm_char_data, HRPWM_CHARDATA_LOC, 12); - - SystemCoreSetup(); - SystemCoreClockSetup(); -} - -__WEAK void SystemCoreSetup(void) { - uint32_t temp; - - /* relocate vector table */ - __disable_irq(); - SCB->VTOR = (uint32_t)(&__Vectors); - __DSB(); - __enable_irq(); - - /* __FPU_PRESENT = 1 defined in device header file */ - /* __FPU_USED value depends on compiler/linker options. */ - /* __FPU_USED = 0 if -mfloat-abi=soft is selected */ - /* __FPU_USED = 1 if -mfloat-abi=softfp or –mfloat-abi=hard */ - -#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) - SCB->CPACR |= ((3UL << 10 * 2) | /* set CP10 Full Access */ - (3UL << 11 * 2)); /* set CP11 Full Access */ -#else - SCB->CPACR = 0; -#endif - - /* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */ - SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk); - - temp = FLASH0->FCON; - temp &= ~FLASH_FCON_WSPFLASH_Msk; - temp |= PMU_FLASH_WS; - FLASH0->FCON = temp; -} - -__WEAK void SystemCoreClockSetup(void) { -#if FOFI_CALIBRATION_MODE == FOFI_CALIBRATION_MODE_FACTORY - /* Enable factory calibration */ - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FOTR_Msk; -#else - /* Automatic calibration uses the fSTDBY */ - - /* Enable HIB domain */ - /* Power up HIB domain if and only if it is currently powered down */ - if ((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0) { - SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk; - - while ((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0) { - /* wait until HIB domain is enabled */ - } - } - - /* Remove the reset only if HIB domain were in a state of reset */ - if ((SCU_RESET->RSTSTAT) & SCU_RESET_RSTSTAT_HIBRS_Msk) { - SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; - delay(DELAY_CNT_150US_50MHZ); - } - - #if STDBY_CLOCK_SRC == STDBY_CLOCK_SRC_OSCULP - /* Enable OSC_ULP */ - if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk) != 0UL) { - /*enable OSC_ULP*/ - while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk) { - /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ - } - SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; - - /* Check if the clock is OK using OSCULP Oscillator Watchdog*/ - while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk) { - /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ - } - SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk; - - /* wait till clock is stable */ - do { - while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk) { - /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ - } - SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk; - - delay(DELAY_CNT_50US_50MHZ); - - } while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk) != 0UL); - } - - /* now OSC_ULP is running and can be used*/ - /* Select OSC_ULP as the clock source for RTC and STDBY*/ - while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk) { - /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ - } - SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk | SCU_HIBERNATE_HDCR_STDBYSEL_Msk; - - #endif /* STDBY_CLOCK_SRC == STDBY_CLOCK_SRC_OSCULP */ - - /* Enable automatic calibration of internal fast oscillator */ - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk; -#endif /* FOFI_CALIBRATION_MODE == FOFI_CALIBRATION_MODE_AUTOMATIC */ - - delay(DELAY_CNT_50US_50MHZ); - -#if ENABLE_PLL - - /* enable PLL */ - SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk); - - #if PLL_CLOCK_SRC != PLL_CLOCK_SRC_OFI - /* enable OSC_HP */ - if ((SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk) != 0U) { - SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_OSCHPCTRL_MODE_Msk | SCU_OSC_OSCHPCTRL_OSCVAL_Msk); - SCU_OSC->OSCHPCTRL |= ((OSCHP_GetFrequency() / FOSCREF) - 1UL) - << SCU_OSC_OSCHPCTRL_OSCVAL_Pos; - - /* select OSC_HP clock as PLL input */ - SCU_PLL->PLLCON2 = 0; - - /* restart OSC Watchdog */ - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; - - while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_OSC_USABLE) != SCU_PLL_PLLSTAT_OSC_USABLE) { - /* wait till OSC_HP output frequency is usable */ - } - } - #else /* PLL_CLOCK_SRC != PLL_CLOCK_SRC_OFI */ - - /* select backup clock as PLL input */ - SCU_PLL->PLLCON2 = SCU_PLL_PLLCON2_PINSEL_Msk | SCU_PLL_PLLCON2_K1INSEL_Msk; - #endif - - /* Go to bypass the Main PLL */ - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk; - while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOBYST_Msk) == 0U) { - /* wait for prescaler mode */ - } - - /* disconnect Oscillator from PLL */ - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk; - - /* Setup divider settings for main PLL */ - SCU_PLL->PLLCON1 = - ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) | (PLL_K2DIV_0 << SCU_PLL_PLLCON1_K2DIV_Pos) | - (PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos)); - - /* Set OSCDISCDIS */ - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk; - - /* connect Oscillator to PLL */ - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk; - - /* restart PLL Lock detection */ - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk; - - while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk) == 0U) { - /* wait for PLL Lock */ - } - - /* Disable bypass- put PLL clock back */ - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk; - while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOBYST_Msk) != 0U) { - /* wait for normal mode */ - } -#endif /* ENABLE_PLL */ - -#if (SYS_CLOCK_SRC == SYS_CLOCK_SRC_PLL) - /* Switch system clock to PLL */ - SCU_CLK->SYSCLKCR |= SCU_CLK_SYSCLKCR_SYSSEL_Msk; -#else - /* Switch system clock to backup clock */ - SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk; -#endif - - /* Before scaling to final frequency we need to setup the clock dividers */ - SCU_CLK->PBCLKCR = PBCLKDIV; - SCU_CLK->CPUCLKCR = CPUCLKDIV; - SCU_CLK->CCUCLKCR = CCUCLKDIV; - SCU_CLK->WDTCLKCR = WDTCLKDIV; - SCU_CLK->USBCLKCR = USBCLKDIV; - -#if ENABLE_PLL - /* PLL frequency stepping...*/ - /* Reset OSCDISCDIS */ - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk; - - SCU_PLL->PLLCON1 = - ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) | (PLL_K2DIV_1 << SCU_PLL_PLLCON1_K2DIV_Pos) | - (PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos)); - - while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_K2RDY_Msk) == 0U) { - /* wait until K2-divider operates on the configured value */ - } - - delay(DELAY_CNT_50US_60MHZ); - - SCU_PLL->PLLCON1 = - ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) | (PLL_K2DIV << SCU_PLL_PLLCON1_K2DIV_Pos) | - (PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos)); - - while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_K2RDY_Msk) == 0U) { - /* wait until K2-divider operates on the configured value */ - } - - delay(DELAY_CNT_50US_80MHZ); - - SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; -#endif /* ENABLE_PLL */ - -#if (((ENABLE_SCUCLK & SCU_CLK_CLKSET_USBCEN_Msk) != 0) && \ - ((USBCLKDIV & SCU_CLK_USBCLKCR_USBSEL_Msk) == SCU_CLK_USBCLKCR_USBSEL_USBPLL)) - /* enable USB PLL first */ - SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk); - - /* USB PLL uses as clock input the OSC_HP */ - /* check and if not already running enable OSC_HP */ - if ((SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk) != 0U) { - /* check if Main PLL is switched on for OSC WDG*/ - if ((SCU_PLL->PLLCON0 & (SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0UL) { - /* enable PLL first */ - SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk); - } - - SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_OSCHPCTRL_MODE_Msk | SCU_OSC_OSCHPCTRL_OSCVAL_Msk); - SCU_OSC->OSCHPCTRL |= ((OSCHP_GetFrequency() / FOSCREF) - 1UL) - << SCU_OSC_OSCHPCTRL_OSCVAL_Pos; - - /* restart OSC Watchdog */ - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; - - while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_OSC_USABLE) != SCU_PLL_PLLSTAT_OSC_USABLE) { - /* wait till OSC_HP output frequency is usable */ - } - } - - /* Setup USB PLL */ - /* Go to bypass the USB PLL */ - SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk; - while ((SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOBYST_Msk) == 0U) { - /* wait for prescaler mode */ - } - - /* disconnect Oscillator from USB PLL */ - SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk; - - /* Setup Divider settings for USB PLL */ - SCU_PLL->USBPLLCON = - ((USB_NDIV << SCU_PLL_USBPLLCON_NDIV_Pos) | (USB_PDIV << SCU_PLL_USBPLLCON_PDIV_Pos)); - - /* Set OSCDISCDIS */ - SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk; - - /* connect Oscillator to USB PLL */ - SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk; - - /* restart PLL Lock detection */ - SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk; - - while ((SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk) == 0U) { - /* wait for PLL Lock */ - } - - /* Disable bypass- put PLL clock back */ - SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_VCOBYP_Msk; - while ((SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOBYST_Msk) != 0U) { - /* wait for normal mode */ - } - - /* Reset OSCDISCDIS */ - SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_OSCDISCDIS_Msk; - - SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_UVCOLCKT_Msk; -#endif /* (USBCLKDIV & SCU_CLK_USBCLKCR_USBSEL_Msk) */ - - /* Enable selected clocks */ - SCU_CLK->CLKSET = ENABLE_SCUCLK; - -#if ENABLE_EXTCLK == 1 - /* Configure external clock */ - SCU_CLK->EXTCLKCR = EXTCLKDIV; - - #if EXTCLK_PIN == EXTCLK_PIN_P1_15 - /* P1.15 */ - PORT1->PDR1 &= ~PORT1_PDR1_PD15_Msk; - PORT1->IOCR12 = (PORT1->IOCR12 & ~PORT1_IOCR12_PC15_Msk) | (0x11U << PORT1_IOCR12_PC15_Pos); - #else - /* P0.8 */ - PORT0->HWSEL &= ~PORT0_HWSEL_HW8_Msk; - PORT0->PDR1 &= ~PORT0_PDR1_PD8_Msk; - PORT0->IOCR8 = (PORT0->IOCR8 & ~PORT0_IOCR8_PC8_Msk) | (0x11U << PORT0_IOCR8_PC8_Pos); - #endif - -#endif /* ENABLE_EXTCLK == 1 */ - - SystemCoreClockUpdate(); -} - -__WEAK void SystemCoreClockUpdate(void) { - uint32_t pdiv; - uint32_t ndiv; - uint32_t kdiv; - uint32_t temp; - - if (SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) { - /* fPLL is clock source for fSYS */ - if (SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk) { - /* PLL input clock is the backup clock (fOFI) */ - temp = OFI_FREQUENCY; - } else { - /* PLL input clock is the high performance osicllator (fOSCHP) */ - temp = OSCHP_GetFrequency(); - } - - /* check if PLL is locked */ - if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk) { - /* PLL normal mode */ - /* read back divider settings */ - pdiv = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk) >> SCU_PLL_PLLCON1_PDIV_Pos) + 1; - ndiv = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk) >> SCU_PLL_PLLCON1_NDIV_Pos) + 1; - kdiv = - ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk) >> SCU_PLL_PLLCON1_K2DIV_Pos) + 1; - - temp = (temp / (pdiv * kdiv)) * ndiv; - } else { - /* PLL prescalar mode */ - /* read back divider settings */ - kdiv = - ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K1DIV_Msk) >> SCU_PLL_PLLCON1_K1DIV_Pos) + 1; - - temp = (temp / kdiv); - } - } else { - /* fOFI is clock source for fSYS */ - temp = OFI_FREQUENCY; - } - - temp = temp / ((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk) + 1); - temp = temp / ((SCU_CLK->CPUCLKCR & SCU_CLK_CPUCLKCR_CPUDIV_Msk) + 1); - - SystemCoreClock = temp; -} - -__WEAK uint32_t OSCHP_GetFrequency(void) { return OSCHP_FREQUENCY; } diff --git a/variants/XMC4200/system_XMC4200.h b/variants/XMC4200/system_XMC4200.h deleted file mode 100644 index 1bb5fe33..00000000 --- a/variants/XMC4200/system_XMC4200.h +++ /dev/null @@ -1,110 +0,0 @@ -/********************************************************************************************************************* - * @file system_XMC4200.h - * @brief Device specific initialization for the XMC4200-Series according to CMSIS - * @version V1.6 - * @date 23 October 2012 - * - * @cond - ********************************************************************************************************************* - * Copyright (c) 2012-2020, Infineon Technologies AG - * All rights reserved. - * - * Boost Software License - Version 1.0 - August 17th, 2003 - * - * Permission is hereby granted, free of charge, to any person or organization - * obtaining a copy of the software and accompanying documentation covered by - * this license (the "Software") to use, reproduce, display, distribute, - * execute, and transmit the Software, and to prepare derivative works of the - * Software, and to permit third-parties to whom the Software is furnished to - * do so, all subject to the following: - * - * The copyright notices in the Software and this entire statement, including - * the above license grant, this restriction and the following disclaimer, - * must be included in all copies of the Software, in whole or in part, and - * all derivative works of the Software, unless such copies or derivative - * works are solely in the form of machine-executable object code generated by - * a source language processor. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT - * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE - * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * To improve the quality of the software, users are encouraged to share - * modifications, enhancements or bug fixes with Infineon Technologies AG - * at XMCSupport@infineon.com. - ********************************************************************************************************************* - * - **************************** Change history ********************************* - ***************************************************************************** - * @endcond - */ - -#ifndef SYSTEM_XMC4200_H -#define SYSTEM_XMC4200_H - -/******************************************************************************* - * HEADER FILES - *******************************************************************************/ - -#include - -/******************************************************************************* - * MACROS - *******************************************************************************/ -#define OFI_FREQUENCY (24000000UL) /**< 24MHz Backup Clock (fOFI) frequency. */ -#define OSI_FREQUENCY (32768UL) /**< 32KHz Internal Slow Clock source (fOSI) frequency. */ - -/******************************************************************************* - * GLOBAL VARIABLES - *******************************************************************************/ -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ -extern uint8_t g_chipid[16]; /*!< Unique chip ID */ -extern uint32_t g_hrpwm_char_data[3]; /*!< HRPWM characterization data */ - -/******************************************************************************* - * API PROTOTYPES - *******************************************************************************/ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Initialize the system - * - */ -void SystemInit(void); - -/** - * @brief Initialize CPU settings - * - */ -void SystemCoreSetup(void); - -/** - * @brief Initialize clock - * - */ -void SystemCoreClockSetup(void); - -/** - * @brief Update SystemCoreClock variable - * - */ -void SystemCoreClockUpdate(void); - -/** - * @brief Returns frequency of the high performace oscillator - * User needs to overload this function to return the correct oscillator frequency - */ -uint32_t OSCHP_GetFrequency(void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/variants/XMC4400/XMC4400.h b/variants/XMC4400/XMC4400.h deleted file mode 100644 index 27ec899a..00000000 --- a/variants/XMC4400/XMC4400.h +++ /dev/null @@ -1,27384 +0,0 @@ -/********************************************************************************************************************* - * Copyright (c) 2011-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted - *provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions - *and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions - *and the following disclaimer in the documentation and/or other materials provided with the - *distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to - *endorse or promote products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - *IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - *FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - *CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - *DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - *DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER - *IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - *OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements - *or bug fixes with Infineon Technologies AG dave@infineon.com). - *********************************************************************************************************************/ - -/****************************************************************************************************/ /** - * @file XMC4400.h - * - * @brief CMSIS Cortex-M4 Peripheral Access Layer Header File for - * XMC4400 from Infineon. - * - * @version V1.6.1 (Reference Manual v1.6) - * @date 19. June 2017 - * - * @note Generated with SVDConv V2.87l - * from CMSIS SVD File 'XMC4400_Processed_SVD.xml' Version 1.6.0 (Reference Manual v1.6), - * added support for ARM Compiler 6 (armclang) - *******************************************************************************************************/ - -/** @addtogroup Infineon - * @{ - */ - -/** @addtogroup XMC4400 - * @{ - */ - -#ifndef XMC4400_H -#define XMC4400_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -typedef enum { - /* ------------------- Cortex-M4 Processor Exceptions Numbers ------------------- */ - Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ - NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ - HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ - MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access - Violation and No Match */ - BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory - related Fault */ - UsageFault_IRQn = - -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ - SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ - DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ - PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ - SysTick_IRQn = -1, /*!< 15 System Tick Timer */ - /* --------------------- XMC4400 Specific Interrupt Numbers --------------------- */ - SCU_0_IRQn = 0, /*!< 0 System Control */ - ERU0_0_IRQn = 1, /*!< 1 External Request Unit 0 */ - ERU0_1_IRQn = 2, /*!< 2 External Request Unit 0 */ - ERU0_2_IRQn = 3, /*!< 3 External Request Unit 0 */ - ERU0_3_IRQn = 4, /*!< 4 External Request Unit 0 */ - ERU1_0_IRQn = 5, /*!< 5 External Request Unit 1 */ - ERU1_1_IRQn = 6, /*!< 6 External Request Unit 1 */ - ERU1_2_IRQn = 7, /*!< 7 External Request Unit 1 */ - ERU1_3_IRQn = 8, /*!< 8 External Request Unit 1 */ - PMU0_0_IRQn = 12, /*!< 12 Program Management Unit */ - VADC0_C0_0_IRQn = 14, /*!< 14 Analog to Digital Converter Common Block 0 */ - VADC0_C0_1_IRQn = 15, /*!< 15 Analog to Digital Converter Common Block 0 */ - VADC0_C0_2_IRQn = 16, /*!< 16 Analog to Digital Converter Common Block 0 */ - VADC0_C0_3_IRQn = 17, /*!< 17 Analog to Digital Converter Common Block 0 */ - VADC0_G0_0_IRQn = 18, /*!< 18 Analog to Digital Converter Group 0 */ - VADC0_G0_1_IRQn = 19, /*!< 19 Analog to Digital Converter Group 0 */ - VADC0_G0_2_IRQn = 20, /*!< 20 Analog to Digital Converter Group 0 */ - VADC0_G0_3_IRQn = 21, /*!< 21 Analog to Digital Converter Group 0 */ - VADC0_G1_0_IRQn = 22, /*!< 22 Analog to Digital Converter Group 1 */ - VADC0_G1_1_IRQn = 23, /*!< 23 Analog to Digital Converter Group 1 */ - VADC0_G1_2_IRQn = 24, /*!< 24 Analog to Digital Converter Group 1 */ - VADC0_G1_3_IRQn = 25, /*!< 25 Analog to Digital Converter Group 1 */ - VADC0_G2_0_IRQn = 26, /*!< 26 Analog to Digital Converter Group 2 */ - VADC0_G2_1_IRQn = 27, /*!< 27 Analog to Digital Converter Group 2 */ - VADC0_G2_2_IRQn = 28, /*!< 28 Analog to Digital Converter Group 2 */ - VADC0_G2_3_IRQn = 29, /*!< 29 Analog to Digital Converter Group 2 */ - VADC0_G3_0_IRQn = 30, /*!< 30 Analog to Digital Converter Group 3 */ - VADC0_G3_1_IRQn = 31, /*!< 31 Analog to Digital Converter Group 3 */ - VADC0_G3_2_IRQn = 32, /*!< 32 Analog to Digital Converter Group 3 */ - VADC0_G3_3_IRQn = 33, /*!< 33 Analog to Digital Converter Group 3 */ - DSD0_M_0_IRQn = 34, /*!< 34 Delta Sigma Demodulator Main */ - DSD0_M_1_IRQn = 35, /*!< 35 Delta Sigma Demodulator Main */ - DSD0_M_2_IRQn = 36, /*!< 36 Delta Sigma Demodulator Main */ - DSD0_M_3_IRQn = 37, /*!< 37 Delta Sigma Demodulator Main */ - DSD0_A_4_IRQn = 38, /*!< 38 Delta Sigma Demodulator Auxiliary */ - DSD0_A_5_IRQn = 39, /*!< 39 Delta Sigma Demodulator Auxiliary */ - DSD0_A_6_IRQn = 40, /*!< 40 Delta Sigma Demodulator Auxiliary */ - DSD0_A_7_IRQn = 41, /*!< 41 Delta Sigma Demodulator Auxiliary */ - DAC0_0_IRQn = 42, /*!< 42 Digital to Analog Converter */ - DAC0_1_IRQn = 43, /*!< 43 Digital to Analog Converter */ - CCU40_0_IRQn = 44, /*!< 44 Capture Compare Unit 4 (Module 0) */ - CCU40_1_IRQn = 45, /*!< 45 Capture Compare Unit 4 (Module 0) */ - CCU40_2_IRQn = 46, /*!< 46 Capture Compare Unit 4 (Module 0) */ - CCU40_3_IRQn = 47, /*!< 47 Capture Compare Unit 4 (Module 0) */ - CCU41_0_IRQn = 48, /*!< 48 Capture Compare Unit 4 (Module 1) */ - CCU41_1_IRQn = 49, /*!< 49 Capture Compare Unit 4 (Module 1) */ - CCU41_2_IRQn = 50, /*!< 50 Capture Compare Unit 4 (Module 1) */ - CCU41_3_IRQn = 51, /*!< 51 Capture Compare Unit 4 (Module 1) */ - CCU42_0_IRQn = 52, /*!< 52 Capture Compare Unit 4 (Module 2) */ - CCU42_1_IRQn = 53, /*!< 53 Capture Compare Unit 4 (Module 2) */ - CCU42_2_IRQn = 54, /*!< 54 Capture Compare Unit 4 (Module 2) */ - CCU42_3_IRQn = 55, /*!< 55 Capture Compare Unit 4 (Module 2) */ - CCU43_0_IRQn = 56, /*!< 56 Capture Compare Unit 4 (Module 3) */ - CCU43_1_IRQn = 57, /*!< 57 Capture Compare Unit 4 (Module 3) */ - CCU43_2_IRQn = 58, /*!< 58 Capture Compare Unit 4 (Module 3) */ - CCU43_3_IRQn = 59, /*!< 59 Capture Compare Unit 4 (Module 3) */ - CCU80_0_IRQn = 60, /*!< 60 Capture Compare Unit 8 (Module 0) */ - CCU80_1_IRQn = 61, /*!< 61 Capture Compare Unit 8 (Module 0) */ - CCU80_2_IRQn = 62, /*!< 62 Capture Compare Unit 8 (Module 0) */ - CCU80_3_IRQn = 63, /*!< 63 Capture Compare Unit 8 (Module 0) */ - CCU81_0_IRQn = 64, /*!< 64 Capture Compare Unit 8 (Module 1) */ - CCU81_1_IRQn = 65, /*!< 65 Capture Compare Unit 8 (Module 1) */ - CCU81_2_IRQn = 66, /*!< 66 Capture Compare Unit 8 (Module 1) */ - CCU81_3_IRQn = 67, /*!< 67 Capture Compare Unit 8 (Module 1) */ - POSIF0_0_IRQn = 68, /*!< 68 Position Interface (Module 0) */ - POSIF0_1_IRQn = 69, /*!< 69 Position Interface (Module 0) */ - POSIF1_0_IRQn = 70, /*!< 70 Position Interface (Module 1) */ - POSIF1_1_IRQn = 71, /*!< 71 Position Interface (Module 1) */ - HRPWM_0_IRQn = 72, /*!< 72 High Resolution Pulse Width Modulation (Module 0) */ - HRPWM_1_IRQn = 73, /*!< 73 High Resolution Pulse Width Modulation (Module 0) */ - HRPWM_2_IRQn = 74, /*!< 74 High Resolution Pulse Width Modulation (Module 0) */ - HRPWM_3_IRQn = 75, /*!< 75 High Resolution Pulse Width Modulation (Module 0) */ - CAN0_0_IRQn = 76, /*!< 76 MultiCAN */ - CAN0_1_IRQn = 77, /*!< 77 MultiCAN */ - CAN0_2_IRQn = 78, /*!< 78 MultiCAN */ - CAN0_3_IRQn = 79, /*!< 79 MultiCAN */ - CAN0_4_IRQn = 80, /*!< 80 MultiCAN */ - CAN0_5_IRQn = 81, /*!< 81 MultiCAN */ - CAN0_6_IRQn = 82, /*!< 82 MultiCAN */ - CAN0_7_IRQn = 83, /*!< 83 MultiCAN */ - USIC0_0_IRQn = 84, /*!< 84 Universal Serial Interface Channel (Module 0) */ - USIC0_1_IRQn = 85, /*!< 85 Universal Serial Interface Channel (Module 0) */ - USIC0_2_IRQn = 86, /*!< 86 Universal Serial Interface Channel (Module 0) */ - USIC0_3_IRQn = 87, /*!< 87 Universal Serial Interface Channel (Module 0) */ - USIC0_4_IRQn = 88, /*!< 88 Universal Serial Interface Channel (Module 0) */ - USIC0_5_IRQn = 89, /*!< 89 Universal Serial Interface Channel (Module 0) */ - USIC1_0_IRQn = 90, /*!< 90 Universal Serial Interface Channel (Module 1) */ - USIC1_1_IRQn = 91, /*!< 91 Universal Serial Interface Channel (Module 1) */ - USIC1_2_IRQn = 92, /*!< 92 Universal Serial Interface Channel (Module 1) */ - USIC1_3_IRQn = 93, /*!< 93 Universal Serial Interface Channel (Module 1) */ - USIC1_4_IRQn = 94, /*!< 94 Universal Serial Interface Channel (Module 1) */ - USIC1_5_IRQn = 95, /*!< 95 Universal Serial Interface Channel (Module 1) */ - LEDTS0_0_IRQn = 102, /*!< 102 LED and Touch Sense Control Unit (Module 0) */ - FCE0_0_IRQn = 104, /*!< 104 Flexible CRC Engine */ - GPDMA0_0_IRQn = 105, /*!< 105 General Purpose DMA Unit 0 */ - USB0_0_IRQn = 107, /*!< 107 Universal Serial Bus (Module 0) */ - ETH0_0_IRQn = 108 /*!< 108 Ethernet (Module 0) */ -} IRQn_Type; - -/** @addtogroup Configuration_of_CMSIS - * @{ - */ - -/* ================================================================================ */ -/* ================ Processor and Core Peripheral Section ================ */ -/* ================================================================================ */ - -/* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */ -#define __CM4_REV \ - 0x0200 /*!< Cortex-M4 Core Revision */ -#define __MPU_PRESENT \ - 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS \ - 6 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig \ - 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT \ - 1 /*!< FPU present or not */ -/** @} */ /* End of group Configuration_of_CMSIS */ - -#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */ -#include "system_XMC4400.h" /*!< XMC4400 System */ - -/* ================================================================================ */ -/* ================ Device Specific Peripheral Section ================ */ -/* ================================================================================ */ -/* Macro to modify desired bitfields of a register */ -#define WR_REG(reg, mask, pos, val) \ - reg = (((uint32_t)val << pos) & ((uint32_t)mask)) | (reg & ((uint32_t) ~((uint32_t)mask))) - -/* Macro to modify desired bitfields of a register */ -#define WR_REG_SIZE(reg, mask, pos, val, size) \ - { \ - uint##size##_t VAL1 = (uint##size##_t)((uint##size##_t)val << pos); \ - uint##size##_t VAL2 = (uint##size##_t)(VAL1 & (uint##size##_t)mask); \ - uint##size##_t VAL3 = (uint##size##_t) ~((uint##size##_t)mask); \ - uint##size##_t VAL4 = (uint##size##_t)((uint##size##_t)reg & VAL3); \ - reg = (uint##size##_t)(VAL2 | VAL4); \ - } - -/** Macro to read bitfields from a register */ -#define RD_REG(reg, mask, pos) (((uint32_t)reg & (uint32_t)mask) >> pos) - -/** Macro to read bitfields from a register */ -#define RD_REG_SIZE(reg, mask, pos, size) \ - ((uint##size##_t)(((uint32_t)reg & (uint32_t)mask) >> pos)) - -/** Macro to set a bit in register */ -#define SET_BIT(reg, pos) (reg |= ((uint32_t)1 << pos)) - -/** Macro to clear a bit in register */ -#define CLR_BIT(reg, pos) (reg = reg & (uint32_t)(~((uint32_t)1 << pos))) -/* - * ========================================================================== - * ---------- Interrupt Handler Definition ---------------------------------- - * ========================================================================== - */ -#define IRQ_Hdlr_0 SCU_0_IRQHandler -#define IRQ_Hdlr_1 ERU0_0_IRQHandler -#define IRQ_Hdlr_2 ERU0_1_IRQHandler -#define IRQ_Hdlr_3 ERU0_2_IRQHandler -#define IRQ_Hdlr_4 ERU0_3_IRQHandler -#define IRQ_Hdlr_5 ERU1_0_IRQHandler -#define IRQ_Hdlr_6 ERU1_1_IRQHandler -#define IRQ_Hdlr_7 ERU1_2_IRQHandler -#define IRQ_Hdlr_8 ERU1_3_IRQHandler -#define IRQ_Hdlr_12 PMU0_0_IRQHandler -#define IRQ_Hdlr_14 VADC0_C0_0_IRQHandler -#define IRQ_Hdlr_15 VADC0_C0_1_IRQHandler -#define IRQ_Hdlr_16 VADC0_C0_2_IRQHandler -#define IRQ_Hdlr_17 VADC0_C0_3_IRQHandler -#define IRQ_Hdlr_18 VADC0_G0_0_IRQHandler -#define IRQ_Hdlr_19 VADC0_G0_1_IRQHandler -#define IRQ_Hdlr_20 VADC0_G0_2_IRQHandler -#define IRQ_Hdlr_21 VADC0_G0_3_IRQHandler -#define IRQ_Hdlr_22 VADC0_G1_0_IRQHandler -#define IRQ_Hdlr_23 VADC0_G1_1_IRQHandler -#define IRQ_Hdlr_24 VADC0_G1_2_IRQHandler -#define IRQ_Hdlr_25 VADC0_G1_3_IRQHandler -#define IRQ_Hdlr_26 VADC0_G2_0_IRQHandler -#define IRQ_Hdlr_27 VADC0_G2_1_IRQHandler -#define IRQ_Hdlr_28 VADC0_G2_2_IRQHandler -#define IRQ_Hdlr_29 VADC0_G2_3_IRQHandler -#define IRQ_Hdlr_30 VADC0_G3_0_IRQHandler -#define IRQ_Hdlr_31 VADC0_G3_1_IRQHandler -#define IRQ_Hdlr_32 VADC0_G3_2_IRQHandler -#define IRQ_Hdlr_33 VADC0_G3_3_IRQHandler -#define IRQ_Hdlr_34 DSD0_0_IRQHandler -#define IRQ_Hdlr_35 DSD0_1_IRQHandler -#define IRQ_Hdlr_36 DSD0_2_IRQHandler -#define IRQ_Hdlr_37 DSD0_3_IRQHandler -#define IRQ_Hdlr_38 DSD0_4_IRQHandler -#define IRQ_Hdlr_39 DSD0_5_IRQHandler -#define IRQ_Hdlr_40 DSD0_6_IRQHandler -#define IRQ_Hdlr_41 DSD0_7_IRQHandler -#define IRQ_Hdlr_42 DAC0_0_IRQHandler -#define IRQ_Hdlr_43 DAC0_1_IRQHandler -#define IRQ_Hdlr_44 CCU40_0_IRQHandler -#define IRQ_Hdlr_45 CCU40_1_IRQHandler -#define IRQ_Hdlr_46 CCU40_2_IRQHandler -#define IRQ_Hdlr_47 CCU40_3_IRQHandler -#define IRQ_Hdlr_48 CCU41_0_IRQHandler -#define IRQ_Hdlr_49 CCU41_1_IRQHandler -#define IRQ_Hdlr_50 CCU41_2_IRQHandler -#define IRQ_Hdlr_51 CCU41_3_IRQHandler -#define IRQ_Hdlr_52 CCU42_0_IRQHandler -#define IRQ_Hdlr_53 CCU42_1_IRQHandler -#define IRQ_Hdlr_54 CCU42_2_IRQHandler -#define IRQ_Hdlr_55 CCU42_3_IRQHandler -#define IRQ_Hdlr_56 CCU43_0_IRQHandler -#define IRQ_Hdlr_57 CCU43_1_IRQHandler -#define IRQ_Hdlr_58 CCU43_2_IRQHandler -#define IRQ_Hdlr_59 CCU43_3_IRQHandler -#define IRQ_Hdlr_60 CCU80_0_IRQHandler -#define IRQ_Hdlr_61 CCU80_1_IRQHandler -#define IRQ_Hdlr_62 CCU80_2_IRQHandler -#define IRQ_Hdlr_63 CCU80_3_IRQHandler -#define IRQ_Hdlr_64 CCU81_0_IRQHandler -#define IRQ_Hdlr_65 CCU81_1_IRQHandler -#define IRQ_Hdlr_66 CCU81_2_IRQHandler -#define IRQ_Hdlr_67 CCU81_3_IRQHandler -#define IRQ_Hdlr_68 POSIF0_0_IRQHandler -#define IRQ_Hdlr_69 POSIF0_1_IRQHandler -#define IRQ_Hdlr_70 POSIF1_0_IRQHandler -#define IRQ_Hdlr_71 POSIF1_1_IRQHandler -#define IRQ_Hdlr_72 HRPWM_0_IRQHandler -#define IRQ_Hdlr_73 HRPWM_1_IRQHandler -#define IRQ_Hdlr_74 HRPWM_2_IRQHandler -#define IRQ_Hdlr_75 HRPWM_3_IRQHandler -#define IRQ_Hdlr_76 CAN0_0_IRQHandler -#define IRQ_Hdlr_77 CAN0_1_IRQHandler -#define IRQ_Hdlr_78 CAN0_2_IRQHandler -#define IRQ_Hdlr_79 CAN0_3_IRQHandler -#define IRQ_Hdlr_80 CAN0_4_IRQHandler -#define IRQ_Hdlr_81 CAN0_5_IRQHandler -#define IRQ_Hdlr_82 CAN0_6_IRQHandler -#define IRQ_Hdlr_83 CAN0_7_IRQHandler -#define IRQ_Hdlr_84 USIC0_0_IRQHandler -#define IRQ_Hdlr_85 USIC0_1_IRQHandler -#define IRQ_Hdlr_86 USIC0_2_IRQHandler -#define IRQ_Hdlr_87 USIC0_3_IRQHandler -#define IRQ_Hdlr_88 USIC0_4_IRQHandler -#define IRQ_Hdlr_89 USIC0_5_IRQHandler -#define IRQ_Hdlr_90 USIC1_0_IRQHandler -#define IRQ_Hdlr_91 USIC1_1_IRQHandler -#define IRQ_Hdlr_92 USIC1_2_IRQHandler -#define IRQ_Hdlr_93 USIC1_3_IRQHandler -#define IRQ_Hdlr_94 USIC1_4_IRQHandler -#define IRQ_Hdlr_95 USIC1_5_IRQHandler -#define IRQ_Hdlr_102 LEDTS0_0_IRQHandler -#define IRQ_Hdlr_104 FCE0_0_IRQHandler -#define IRQ_Hdlr_105 GPDMA0_0_IRQHandler -#define IRQ_Hdlr_107 USB0_0_IRQHandler -#define IRQ_Hdlr_108 ETH0_0_IRQHandler - -/* - * ========================================================================== - * ---------- Interrupt Handler retrieval macro ----------------------------- - * ========================================================================== - */ -#define GET_IRQ_HANDLER(N) IRQ_Hdlr_##N - -/** @addtogroup Device_Peripheral_Registers - * @{ - */ - -/* ------------------- Start of section using anonymous unions ------------------ */ -#if defined(__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wc11-extensions" - #pragma clang diagnostic ignored "-Wreserved-id-macro" -#elif defined(__ICCARM__) - #pragma language = extended -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__TMS470__) -/* anonymous unions are enabled by default */ -#elif defined(__TASKING__) - #pragma warning 586 -#else - #warning Not supported compiler type -#endif - -/* ================================================================================ */ -/* ================ PPB ================ */ -/* ================================================================================ */ - -/** - * @brief Cortex-M4 Private Peripheral Block (PPB) - */ - -typedef struct { /*!< (@ 0xE000E000) PPB Structure */ - __I uint32_t RESERVED[2]; - __IO uint32_t ACTLR; /*!< (@ 0xE000E008) Auxiliary Control Register */ - __I uint32_t RESERVED1; - __IO uint32_t SYST_CSR; /*!< (@ 0xE000E010) SysTick Control and Status Register */ - __IO uint32_t SYST_RVR; /*!< (@ 0xE000E014) SysTick Reload Value Register */ - __IO uint32_t SYST_CVR; /*!< (@ 0xE000E018) SysTick Current Value Register */ - __IO uint32_t SYST_CALIB; /*!< (@ 0xE000E01C) SysTick Calibration Value Register r */ - __I uint32_t RESERVED2[56]; - __IO uint32_t NVIC_ISER0; /*!< (@ 0xE000E100) Interrupt Set-enable Register 0 */ - __IO uint32_t NVIC_ISER1; /*!< (@ 0xE000E104) Interrupt Set-enable Register 1 */ - __IO uint32_t NVIC_ISER2; /*!< (@ 0xE000E108) Interrupt Set-enable Register 2 */ - __IO uint32_t NVIC_ISER3; /*!< (@ 0xE000E10C) Interrupt Set-enable Register 3 */ - __I uint32_t RESERVED3[28]; - __IO uint32_t NVIC_ICER0; /*!< (@ 0xE000E180) Interrupt Clear-enable Register 0 */ - __IO uint32_t NVIC_ICER1; /*!< (@ 0xE000E184) Interrupt Clear-enable Register 1 */ - __IO uint32_t NVIC_ICER2; /*!< (@ 0xE000E188) Interrupt Clear-enable Register 2 */ - __IO uint32_t NVIC_ICER3; /*!< (@ 0xE000E18C) Interrupt Clear-enable Register 3 */ - __I uint32_t RESERVED4[28]; - __IO uint32_t NVIC_ISPR0; /*!< (@ 0xE000E200) Interrupt Set-pending Register 0 */ - __IO uint32_t NVIC_ISPR1; /*!< (@ 0xE000E204) Interrupt Set-pending Register 1 */ - __IO uint32_t NVIC_ISPR2; /*!< (@ 0xE000E208) Interrupt Set-pending Register 2 */ - __IO uint32_t NVIC_ISPR3; /*!< (@ 0xE000E20C) Interrupt Set-pending Register 3 */ - __I uint32_t RESERVED5[28]; - __IO uint32_t NVIC_ICPR0; /*!< (@ 0xE000E280) Interrupt Clear-pending Register 0 */ - __IO uint32_t NVIC_ICPR1; /*!< (@ 0xE000E284) Interrupt Clear-pending Register 1 */ - __IO uint32_t NVIC_ICPR2; /*!< (@ 0xE000E288) Interrupt Clear-pending Register 2 */ - __IO uint32_t NVIC_ICPR3; /*!< (@ 0xE000E28C) Interrupt Clear-pending Register 3 */ - __I uint32_t RESERVED6[28]; - __IO uint32_t NVIC_IABR0; /*!< (@ 0xE000E300) Interrupt Active Bit Register 0 */ - __IO uint32_t NVIC_IABR1; /*!< (@ 0xE000E304) Interrupt Active Bit Register 1 */ - __IO uint32_t NVIC_IABR2; /*!< (@ 0xE000E308) Interrupt Active Bit Register 2 */ - __IO uint32_t NVIC_IABR3; /*!< (@ 0xE000E30C) Interrupt Active Bit Register 3 */ - __I uint32_t RESERVED7[60]; - __IO uint32_t NVIC_IPR0; /*!< (@ 0xE000E400) Interrupt Priority Register 0 */ - __IO uint32_t NVIC_IPR1; /*!< (@ 0xE000E404) Interrupt Priority Register 1 */ - __IO uint32_t NVIC_IPR2; /*!< (@ 0xE000E408) Interrupt Priority Register 2 */ - __IO uint32_t NVIC_IPR3; /*!< (@ 0xE000E40C) Interrupt Priority Register 3 */ - __IO uint32_t NVIC_IPR4; /*!< (@ 0xE000E410) Interrupt Priority Register 4 */ - __IO uint32_t NVIC_IPR5; /*!< (@ 0xE000E414) Interrupt Priority Register 5 */ - __IO uint32_t NVIC_IPR6; /*!< (@ 0xE000E418) Interrupt Priority Register 6 */ - __IO uint32_t NVIC_IPR7; /*!< (@ 0xE000E41C) Interrupt Priority Register 7 */ - __IO uint32_t NVIC_IPR8; /*!< (@ 0xE000E420) Interrupt Priority Register 8 */ - __IO uint32_t NVIC_IPR9; /*!< (@ 0xE000E424) Interrupt Priority Register 9 */ - __IO uint32_t NVIC_IPR10; /*!< (@ 0xE000E428) Interrupt Priority Register 10 */ - __IO uint32_t NVIC_IPR11; /*!< (@ 0xE000E42C) Interrupt Priority Register 11 */ - __IO uint32_t NVIC_IPR12; /*!< (@ 0xE000E430) Interrupt Priority Register 12 */ - __IO uint32_t NVIC_IPR13; /*!< (@ 0xE000E434) Interrupt Priority Register 13 */ - __IO uint32_t NVIC_IPR14; /*!< (@ 0xE000E438) Interrupt Priority Register 14 */ - __IO uint32_t NVIC_IPR15; /*!< (@ 0xE000E43C) Interrupt Priority Register 15 */ - __IO uint32_t NVIC_IPR16; /*!< (@ 0xE000E440) Interrupt Priority Register 16 */ - __IO uint32_t NVIC_IPR17; /*!< (@ 0xE000E444) Interrupt Priority Register 17 */ - __IO uint32_t NVIC_IPR18; /*!< (@ 0xE000E448) Interrupt Priority Register 18 */ - __IO uint32_t NVIC_IPR19; /*!< (@ 0xE000E44C) Interrupt Priority Register 19 */ - __IO uint32_t NVIC_IPR20; /*!< (@ 0xE000E450) Interrupt Priority Register 20 */ - __IO uint32_t NVIC_IPR21; /*!< (@ 0xE000E454) Interrupt Priority Register 21 */ - __IO uint32_t NVIC_IPR22; /*!< (@ 0xE000E458) Interrupt Priority Register 22 */ - __IO uint32_t NVIC_IPR23; /*!< (@ 0xE000E45C) Interrupt Priority Register 23 */ - __IO uint32_t NVIC_IPR24; /*!< (@ 0xE000E460) Interrupt Priority Register 24 */ - __IO uint32_t NVIC_IPR25; /*!< (@ 0xE000E464) Interrupt Priority Register 25 */ - __IO uint32_t NVIC_IPR26; /*!< (@ 0xE000E468) Interrupt Priority Register 26 */ - __IO uint32_t NVIC_IPR27; /*!< (@ 0xE000E46C) Interrupt Priority Register 27 */ - __I uint32_t RESERVED8[548]; - __I uint32_t CPUID; /*!< (@ 0xE000ED00) CPUID Base Register */ - __IO uint32_t ICSR; /*!< (@ 0xE000ED04) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< (@ 0xE000ED08) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< (@ 0xE000ED0C) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< (@ 0xE000ED10) System Control Register */ - __IO uint32_t CCR; /*!< (@ 0xE000ED14) Configuration and Control Register */ - __IO uint32_t SHPR1; /*!< (@ 0xE000ED18) System Handler Priority Register 1 */ - __IO uint32_t SHPR2; /*!< (@ 0xE000ED1C) System Handler Priority Register 2 */ - __IO uint32_t SHPR3; /*!< (@ 0xE000ED20) System Handler Priority Register 3 */ - __IO uint32_t SHCSR; /*!< (@ 0xE000ED24) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< (@ 0xE000ED28) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< (@ 0xE000ED2C) HardFault Status Register */ - __I uint32_t RESERVED9; - __IO uint32_t MMFAR; /*!< (@ 0xE000ED34) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< (@ 0xE000ED38) BusFault Address Register */ - __IO uint32_t AFSR; /*!< (@ 0xE000ED3C) Auxiliary Fault Status Register */ - __I uint32_t RESERVED10[18]; - __IO uint32_t CPACR; /*!< (@ 0xE000ED88) Coprocessor Access Control Register */ - __I uint32_t RESERVED11; - __I uint32_t MPU_TYPE; /*!< (@ 0xE000ED90) MPU Type Register */ - __IO uint32_t MPU_CTRL; /*!< (@ 0xE000ED94) MPU Control Register */ - __IO uint32_t MPU_RNR; /*!< (@ 0xE000ED98) MPU Region Number Register */ - __IO uint32_t MPU_RBAR; /*!< (@ 0xE000ED9C) MPU Region Base Address Register */ - __IO uint32_t MPU_RASR; /*!< (@ 0xE000EDA0) MPU Region Attribute and Size Register */ - __IO uint32_t MPU_RBAR_A1; /*!< (@ 0xE000EDA4) MPU Region Base Address Register A1 */ - __IO uint32_t MPU_RASR_A1; /*!< (@ 0xE000EDA8) MPU Region Attribute and Size Register A1 */ - __IO uint32_t MPU_RBAR_A2; /*!< (@ 0xE000EDAC) MPU Region Base Address Register A2 */ - __IO uint32_t MPU_RASR_A2; /*!< (@ 0xE000EDB0) MPU Region Attribute and Size Register A2 */ - __IO uint32_t MPU_RBAR_A3; /*!< (@ 0xE000EDB4) MPU Region Base Address Register A3 */ - __IO uint32_t MPU_RASR_A3; /*!< (@ 0xE000EDB8) MPU Region Attribute and Size Register A3 */ - __I uint32_t RESERVED12[81]; - __O uint32_t STIR; /*!< (@ 0xE000EF00) Software Trigger Interrupt Register */ - __I uint32_t RESERVED13[12]; - __IO uint32_t FPCCR; /*!< (@ 0xE000EF34) Floating-point Context Control Register */ - __IO uint32_t FPCAR; /*!< (@ 0xE000EF38) Floating-point Context Address Register */ - __IO uint32_t FPDSCR; /*!< (@ 0xE000EF3C) Floating-point Default Status Control Register */ -} PPB_Type; - -/* ================================================================================ */ -/* ================ DLR ================ */ -/* ================================================================================ */ - -/** - * @brief DMA Line Router (DLR) - */ - -typedef struct { /*!< (@ 0x50004900) DLR Structure */ - __I uint32_t OVRSTAT; /*!< (@ 0x50004900) Overrun Status */ - __O uint32_t OVRCLR; /*!< (@ 0x50004904) Overrun Clear */ - __IO uint32_t SRSEL0; /*!< (@ 0x50004908) Service Request Selection 0 */ - __I uint32_t RESERVED; - __IO uint32_t LNEN; /*!< (@ 0x50004910) Line Enable */ -} DLR_GLOBAL_TypeDef; - -/* ================================================================================ */ -/* ================ ERU [ERU0] ================ */ -/* ================================================================================ */ - -/** - * @brief Event Request Unit 0 (ERU) - */ - -typedef struct { /*!< (@ 0x50004800) ERU Structure */ - __IO uint32_t EXISEL; /*!< (@ 0x50004800) Event Input Select */ - __I uint32_t RESERVED[3]; - __IO uint32_t EXICON[4]; /*!< (@ 0x50004810) Event Input Control */ - __IO uint32_t EXOCON[4]; /*!< (@ 0x50004820) Event Output Trigger Control */ -} ERU_GLOBAL_TypeDef; - -/* ================================================================================ */ -/* ================ GPDMA0 ================ */ -/* ================================================================================ */ - -/** - * @brief General Purpose DMA Unit 0 (GPDMA0) - */ - -typedef struct { /*!< (@ 0x500142C0) GPDMA0 Structure */ - __IO uint32_t RAWTFR; /*!< (@ 0x500142C0) Raw IntTfr Status */ - __I uint32_t RESERVED; - __IO uint32_t RAWBLOCK; /*!< (@ 0x500142C8) Raw IntBlock Status */ - __I uint32_t RESERVED1; - __IO uint32_t RAWSRCTRAN; /*!< (@ 0x500142D0) Raw IntSrcTran Status */ - __I uint32_t RESERVED2; - __IO uint32_t RAWDSTTRAN; /*!< (@ 0x500142D8) Raw IntBlock Status */ - __I uint32_t RESERVED3; - __IO uint32_t RAWERR; /*!< (@ 0x500142E0) Raw IntErr Status */ - __I uint32_t RESERVED4; - __I uint32_t STATUSTFR; /*!< (@ 0x500142E8) IntTfr Status */ - __I uint32_t RESERVED5; - __I uint32_t STATUSBLOCK; /*!< (@ 0x500142F0) IntBlock Status */ - __I uint32_t RESERVED6; - __I uint32_t STATUSSRCTRAN; /*!< (@ 0x500142F8) IntSrcTran Status */ - __I uint32_t RESERVED7; - __I uint32_t STATUSDSTTRAN; /*!< (@ 0x50014300) IntBlock Status */ - __I uint32_t RESERVED8; - __I uint32_t STATUSERR; /*!< (@ 0x50014308) IntErr Status */ - __I uint32_t RESERVED9; - __IO uint32_t MASKTFR; /*!< (@ 0x50014310) Mask for Raw IntTfr Status */ - __I uint32_t RESERVED10; - __IO uint32_t MASKBLOCK; /*!< (@ 0x50014318) Mask for Raw IntBlock Status */ - __I uint32_t RESERVED11; - __IO uint32_t MASKSRCTRAN; /*!< (@ 0x50014320) Mask for Raw IntSrcTran Status */ - __I uint32_t RESERVED12; - __IO uint32_t MASKDSTTRAN; /*!< (@ 0x50014328) Mask for Raw IntBlock Status */ - __I uint32_t RESERVED13; - __IO uint32_t MASKERR; /*!< (@ 0x50014330) Mask for Raw IntErr Status */ - __I uint32_t RESERVED14; - __O uint32_t CLEARTFR; /*!< (@ 0x50014338) IntTfr Status */ - __I uint32_t RESERVED15; - __O uint32_t CLEARBLOCK; /*!< (@ 0x50014340) IntBlock Status */ - __I uint32_t RESERVED16; - __O uint32_t CLEARSRCTRAN; /*!< (@ 0x50014348) IntSrcTran Status */ - __I uint32_t RESERVED17; - __O uint32_t CLEARDSTTRAN; /*!< (@ 0x50014350) IntBlock Status */ - __I uint32_t RESERVED18; - __O uint32_t CLEARERR; /*!< (@ 0x50014358) IntErr Status */ - __I uint32_t RESERVED19; - __I uint32_t STATUSINT; /*!< (@ 0x50014360) Combined Interrupt Status Register */ - __I uint32_t RESERVED20; - __IO uint32_t REQSRCREG; /*!< (@ 0x50014368) Source Software Transaction Request Register */ - __I uint32_t RESERVED21; - __IO uint32_t - REQDSTREG; /*!< (@ 0x50014370) Destination Software Transaction Request Register */ - __I uint32_t RESERVED22; - __IO uint32_t SGLREQSRCREG; /*!< (@ 0x50014378) Single Source Transaction Request Register */ - __I uint32_t RESERVED23; - __IO uint32_t - SGLREQDSTREG; /*!< (@ 0x50014380) Single Destination Transaction Request Register */ - __I uint32_t RESERVED24; - __IO uint32_t LSTSRCREG; /*!< (@ 0x50014388) Last Source Transaction Request Register */ - __I uint32_t RESERVED25; - __IO uint32_t LSTDSTREG; /*!< (@ 0x50014390) Last Destination Transaction Request Register */ - __I uint32_t RESERVED26; - __IO uint32_t DMACFGREG; /*!< (@ 0x50014398) GPDMA Configuration Register */ - __I uint32_t RESERVED27; - __IO uint32_t CHENREG; /*!< (@ 0x500143A0) GPDMA Channel Enable Register */ - __I uint32_t RESERVED28; - __I uint32_t ID; /*!< (@ 0x500143A8) GPDMA0 ID Register */ - __I uint32_t RESERVED29[19]; - __I uint32_t TYPE; /*!< (@ 0x500143F8) GPDMA Component Type */ - __I uint32_t VERSION; /*!< (@ 0x500143FC) DMA Component Version */ -} GPDMA0_GLOBAL_TypeDef; - -/* ================================================================================ */ -/* ================ GPDMA0_CH0_1 [GPDMA0_CH0] ================ */ -/* ================================================================================ */ - -/** - * @brief General Purpose DMA Unit 0 (GPDMA0_CH0_1) - */ - -typedef struct { /*!< (@ 0x50014000) GPDMA0_CH0_1 Structure */ - __IO uint32_t SAR; /*!< (@ 0x50014000) Source Address Register */ - __I uint32_t RESERVED; - __IO uint32_t DAR; /*!< (@ 0x50014008) Destination Address Register */ - __I uint32_t RESERVED1; - __IO uint32_t LLP; /*!< (@ 0x50014010) Linked List Pointer Register */ - __I uint32_t RESERVED2; - __IO uint32_t CTLL; /*!< (@ 0x50014018) Control Register Low */ - __IO uint32_t CTLH; /*!< (@ 0x5001401C) Control Register High */ - __IO uint32_t SSTAT; /*!< (@ 0x50014020) Source Status Register */ - __I uint32_t RESERVED3; - __IO uint32_t DSTAT; /*!< (@ 0x50014028) Destination Status Register */ - __I uint32_t RESERVED4; - __IO uint32_t SSTATAR; /*!< (@ 0x50014030) Source Status Address Register */ - __I uint32_t RESERVED5; - __IO uint32_t DSTATAR; /*!< (@ 0x50014038) Destination Status Address Register */ - __I uint32_t RESERVED6; - __IO uint32_t CFGL; /*!< (@ 0x50014040) Configuration Register Low */ - __IO uint32_t CFGH; /*!< (@ 0x50014044) Configuration Register High */ - __IO uint32_t SGR; /*!< (@ 0x50014048) Source Gather Register */ - __I uint32_t RESERVED7; - __IO uint32_t DSR; /*!< (@ 0x50014050) Destination Scatter Register */ -} GPDMA0_CH_TypeDef; - -/* ================================================================================ */ -/* ================ GPDMA0_CH2_7 [GPDMA0_CH2] ================ */ -/* ================================================================================ */ - -/** - * @brief General Purpose DMA Unit 0 (GPDMA0_CH2_7) - */ - -typedef struct { /*!< (@ 0x500140B0) GPDMA0_CH2_7 Structure */ - __IO uint32_t SAR; /*!< (@ 0x500140B0) Source Address Register */ - __I uint32_t RESERVED; - __IO uint32_t DAR; /*!< (@ 0x500140B8) Destination Address Register */ - __I uint32_t RESERVED1[3]; - __IO uint32_t CTLL; /*!< (@ 0x500140C8) Control Register Low */ - __IO uint32_t CTLH; /*!< (@ 0x500140CC) Control Register High */ - __I uint32_t RESERVED2[8]; - __IO uint32_t CFGL; /*!< (@ 0x500140F0) Configuration Register Low */ - __IO uint32_t CFGH; /*!< (@ 0x500140F4) Configuration Register High */ -} GPDMA0_CH2_7_Type; - -/* ================================================================================ */ -/* ================ FCE ================ */ -/* ================================================================================ */ - -/** - * @brief Flexible CRC Engine (FCE) - */ - -typedef struct { /*!< (@ 0x50020000) FCE Structure */ - __IO uint32_t CLC; /*!< (@ 0x50020000) Clock Control Register */ - __I uint32_t RESERVED; - __I uint32_t ID; /*!< (@ 0x50020008) Module Identification Register */ -} FCE_GLOBAL_TypeDef; - -/* ================================================================================ */ -/* ================ FCE_KE [FCE_KE0] ================ */ -/* ================================================================================ */ - -/** - * @brief Flexible CRC Engine (FCE_KE) - */ - -typedef struct { /*!< (@ 0x50020020) FCE_KE Structure */ - __IO uint32_t IR; /*!< (@ 0x50020020) Input Register */ - __I uint32_t RES; /*!< (@ 0x50020024) CRC Result Register */ - __IO uint32_t CFG; /*!< (@ 0x50020028) CRC Configuration Register */ - __IO uint32_t STS; /*!< (@ 0x5002002C) CRC Status Register */ - __IO uint32_t LENGTH; /*!< (@ 0x50020030) CRC Length Register */ - __IO uint32_t CHECK; /*!< (@ 0x50020034) CRC Check Register */ - __IO uint32_t CRC; /*!< (@ 0x50020038) CRC Register */ - __IO uint32_t CTR; /*!< (@ 0x5002003C) CRC Test Register */ -} FCE_KE_TypeDef; - -/* ================================================================================ */ -/* ================ PBA [PBA0] ================ */ -/* ================================================================================ */ - -/** - * @brief Peripheral Bridge AHB 0 (PBA) - */ - -typedef struct { /*!< (@ 0x40000000) PBA Structure */ - __IO uint32_t STS; /*!< (@ 0x40000000) Peripheral Bridge Status Register */ - __I uint32_t WADDR; /*!< (@ 0x40000004) PBA Write Error Address Register */ -} PBA_GLOBAL_TypeDef; - -/* ================================================================================ */ -/* ================ FLASH [FLASH0] ================ */ -/* ================================================================================ */ - -/** - * @brief Flash Memory Controller (FLASH) - */ - -typedef struct { /*!< (@ 0x58001000) FLASH Structure */ - __I uint32_t RESERVED[1026]; - __I uint32_t ID; /*!< (@ 0x58002008) Flash Module Identification Register */ - __I uint32_t RESERVED1; - __I uint32_t FSR; /*!< (@ 0x58002010) Flash Status Register */ - __IO uint32_t FCON; /*!< (@ 0x58002014) Flash Configuration Register */ - __IO uint32_t MARP; /*!< (@ 0x58002018) Margin Control Register PFLASH */ - __I uint32_t RESERVED2; - __I uint32_t PROCON0; /*!< (@ 0x58002020) Flash Protection Configuration Register User - 0 */ - __I uint32_t PROCON1; /*!< (@ 0x58002024) Flash Protection Configuration Register User - 1 */ - __I uint32_t PROCON2; /*!< (@ 0x58002028) Flash Protection Configuration Register User - 2 */ -} FLASH0_GLOBAL_TypeDef; - -/* ================================================================================ */ -/* ================ PREF ================ */ -/* ================================================================================ */ - -/** - * @brief Prefetch Unit (PREF) - */ - -typedef struct { /*!< (@ 0x58004000) PREF Structure */ - __IO uint32_t PCON; /*!< (@ 0x58004000) Prefetch Configuration Register */ -} PREF_GLOBAL_TypeDef; - -/* ================================================================================ */ -/* ================ PMU [PMU0] ================ */ -/* ================================================================================ */ - -/** - * @brief Program Management Unit (PMU) - */ - -typedef struct { /*!< (@ 0x58000508) PMU Structure */ - __I uint32_t ID; /*!< (@ 0x58000508) PMU0 Identification Register */ -} PMU0_GLOBAL_TypeDef; - -/* ================================================================================ */ -/* ================ WDT ================ */ -/* ================================================================================ */ - -/** - * @brief Watch Dog Timer (WDT) - */ - -typedef struct { /*!< (@ 0x50008000) WDT Structure */ - __I uint32_t ID; /*!< (@ 0x50008000) WDT ID Register */ - __IO uint32_t CTR; /*!< (@ 0x50008004) WDT Control Register */ - __O uint32_t SRV; /*!< (@ 0x50008008) WDT Service Register */ - __I uint32_t TIM; /*!< (@ 0x5000800C) WDT Timer Register */ - __IO uint32_t WLB; /*!< (@ 0x50008010) WDT Window Lower Bound Register */ - __IO uint32_t WUB; /*!< (@ 0x50008014) WDT Window Upper Bound Register */ - __I uint32_t WDTSTS; /*!< (@ 0x50008018) WDT Status Register */ - __O uint32_t WDTCLR; /*!< (@ 0x5000801C) WDT Clear Register */ -} WDT_GLOBAL_TypeDef; - -/* ================================================================================ */ -/* ================ RTC ================ */ -/* ================================================================================ */ - -/** - * @brief Real Time Clock (RTC) - */ - -typedef struct { /*!< (@ 0x50004A00) RTC Structure */ - __I uint32_t ID; /*!< (@ 0x50004A00) RTC ID Register */ - __IO uint32_t CTR; /*!< (@ 0x50004A04) RTC Control Register */ - __I uint32_t RAWSTAT; /*!< (@ 0x50004A08) RTC Raw Service Request Register */ - __I uint32_t STSSR; /*!< (@ 0x50004A0C) RTC Service Request Status Register */ - __IO uint32_t MSKSR; /*!< (@ 0x50004A10) RTC Service Request Mask Register */ - __O uint32_t CLRSR; /*!< (@ 0x50004A14) RTC Clear Service Request Register */ - __IO uint32_t ATIM0; /*!< (@ 0x50004A18) RTC Alarm Time Register 0 */ - __IO uint32_t ATIM1; /*!< (@ 0x50004A1C) RTC Alarm Time Register 1 */ - __IO uint32_t TIM0; /*!< (@ 0x50004A20) RTC Time Register 0 */ - __IO uint32_t TIM1; /*!< (@ 0x50004A24) RTC Time Register 1 */ -} RTC_GLOBAL_TypeDef; - -/* ================================================================================ */ -/* ================ SCU_CLK ================ */ -/* ================================================================================ */ - -/** - * @brief System Control Unit (SCU_CLK) - */ - -typedef struct { /*!< (@ 0x50004600) SCU_CLK Structure */ - __I uint32_t CLKSTAT; /*!< (@ 0x50004600) Clock Status Register */ - __O uint32_t CLKSET; /*!< (@ 0x50004604) CLK Set Register */ - __O uint32_t CLKCLR; /*!< (@ 0x50004608) CLK Clear Register */ - __IO uint32_t SYSCLKCR; /*!< (@ 0x5000460C) System Clock Control Register */ - __IO uint32_t CPUCLKCR; /*!< (@ 0x50004610) CPU Clock Control Register */ - __IO uint32_t PBCLKCR; /*!< (@ 0x50004614) Peripheral Bus Clock Control Register */ - __IO uint32_t USBCLKCR; /*!< (@ 0x50004618) USB Clock Control Register */ - __I uint32_t RESERVED; - __IO uint32_t CCUCLKCR; /*!< (@ 0x50004620) CCU Clock Control Register */ - __IO uint32_t WDTCLKCR; /*!< (@ 0x50004624) WDT Clock Control Register */ - __IO uint32_t EXTCLKCR; /*!< (@ 0x50004628) External Clock Control */ - __IO uint32_t MLINKCLKCR; /*!< (@ 0x5000462C) Multi-Link Clock Control */ - __IO uint32_t SLEEPCR; /*!< (@ 0x50004630) Sleep Control Register */ - __IO uint32_t DSLEEPCR; /*!< (@ 0x50004634) Deep Sleep Control Register */ - __I uint32_t RESERVED1[2]; - __I uint32_t CGATSTAT0; /*!< (@ 0x50004640) Peripheral 0 Clock Gating Status */ - __O uint32_t CGATSET0; /*!< (@ 0x50004644) Peripheral 0 Clock Gating Set */ - __O uint32_t CGATCLR0; /*!< (@ 0x50004648) Peripheral 0 Clock Gating Clear */ - __I uint32_t CGATSTAT1; /*!< (@ 0x5000464C) Peripheral 1 Clock Gating Status */ - __O uint32_t CGATSET1; /*!< (@ 0x50004650) Peripheral 1 Clock Gating Set */ - __O uint32_t CGATCLR1; /*!< (@ 0x50004654) Peripheral 1 Clock Gating Clear */ - __I uint32_t CGATSTAT2; /*!< (@ 0x50004658) Peripheral 2 Clock Gating Status */ - __O uint32_t CGATSET2; /*!< (@ 0x5000465C) Peripheral 2 Clock Gating Set */ - __O uint32_t CGATCLR2; /*!< (@ 0x50004660) Peripheral 2 Clock Gating Clear */ -} SCU_CLK_TypeDef; - -/* ================================================================================ */ -/* ================ SCU_OSC ================ */ -/* ================================================================================ */ - -/** - * @brief System Control Unit (SCU_OSC) - */ - -typedef struct { /*!< (@ 0x50004700) SCU_OSC Structure */ - __I uint32_t OSCHPSTAT; /*!< (@ 0x50004700) OSC_HP Status Register */ - __IO uint32_t OSCHPCTRL; /*!< (@ 0x50004704) OSC_HP Control Register */ - __I uint32_t RESERVED; - __IO uint32_t CLKCALCONST; /*!< (@ 0x5000470C) Clock Calibration Constant Register */ -} SCU_OSC_TypeDef; - -/* ================================================================================ */ -/* ================ SCU_PLL ================ */ -/* ================================================================================ */ - -/** - * @brief System Control Unit (SCU_PLL) - */ - -typedef struct { /*!< (@ 0x50004710) SCU_PLL Structure */ - __I uint32_t PLLSTAT; /*!< (@ 0x50004710) PLL Status Register */ - __IO uint32_t PLLCON0; /*!< (@ 0x50004714) PLL Configuration 0 Register */ - __IO uint32_t PLLCON1; /*!< (@ 0x50004718) PLL Configuration 1 Register */ - __IO uint32_t PLLCON2; /*!< (@ 0x5000471C) PLL Configuration 2 Register */ - __I uint32_t USBPLLSTAT; /*!< (@ 0x50004720) USB PLL Status Register */ - __IO uint32_t USBPLLCON; /*!< (@ 0x50004724) USB PLL Configuration Register */ - __I uint32_t RESERVED[4]; - __I uint32_t CLKMXSTAT; /*!< (@ 0x50004738) Clock Multiplexing Status Register */ -} SCU_PLL_TypeDef; - -/* ================================================================================ */ -/* ================ SCU_GENERAL ================ */ -/* ================================================================================ */ - -/** - * @brief System Control Unit (SCU_GENERAL) - */ - -typedef struct { /*!< (@ 0x50004000) SCU_GENERAL Structure */ - __I uint32_t ID; /*!< (@ 0x50004000) SCU Module ID Register */ - __I uint32_t IDCHIP; /*!< (@ 0x50004004) Chip ID Register */ - __I uint32_t IDMANUF; /*!< (@ 0x50004008) Manufactory ID Register */ - __I uint32_t RESERVED; - __IO uint32_t STCON; /*!< (@ 0x50004010) Startup Configuration Register */ - __I uint32_t RESERVED1[6]; - __IO uint32_t GPR[2]; /*!< (@ 0x5000402C) General Purpose Register 0 */ - __I uint32_t RESERVED2[6]; - __IO uint32_t CCUCON; /*!< (@ 0x5000404C) CCU Control Register */ - __I uint32_t RESERVED3[15]; - __IO uint32_t DTSCON; /*!< (@ 0x5000408C) Die Temperature Sensor Control Register */ - __I uint32_t DTSSTAT; /*!< (@ 0x50004090) Die Temperature Sensor Status Register */ - __I uint32_t RESERVED4[3]; - __IO uint32_t GORCEN[2]; /*!< (@ 0x500040A0) Out of Range Comparator Enable Register 0 */ - __IO uint32_t DTEMPLIM; /*!< (@ 0x500040A8) Die Temperature Sensor Limit Register */ - __I uint32_t DTEMPALARM; /*!< (@ 0x500040AC) Die Temperature Sensor Alarm Register */ - __I uint32_t RESERVED5[5]; - __I uint32_t MIRRSTS; /*!< (@ 0x500040C4) Mirror Write Status Register */ - __IO uint32_t RMACR; /*!< (@ 0x500040C8) Retention Memory Access Control Register */ - __IO uint32_t RMDATA; /*!< (@ 0x500040CC) Retention Memory Access Data Register */ - __I uint32_t MIRRALLSTAT; /*!< (@ 0x500040D0) Mirror All Status */ - __O uint32_t MIRRALLREQ; /*!< (@ 0x500040D4) Mirror All Request */ -} SCU_GENERAL_TypeDef; - -/* ================================================================================ */ -/* ================ SCU_INTERRUPT ================ */ -/* ================================================================================ */ - -/** - * @brief System Control Unit (SCU_INTERRUPT) - */ - -typedef struct { /*!< (@ 0x50004074) SCU_INTERRUPT Structure */ - __I uint32_t SRSTAT; /*!< (@ 0x50004074) SCU Service Request Status */ - __I uint32_t SRRAW; /*!< (@ 0x50004078) SCU Raw Service Request Status */ - __IO uint32_t SRMSK; /*!< (@ 0x5000407C) SCU Service Request Mask */ - __O uint32_t SRCLR; /*!< (@ 0x50004080) SCU Service Request Clear */ - __O uint32_t SRSET; /*!< (@ 0x50004084) SCU Service Request Set */ - __IO uint32_t NMIREQEN; /*!< (@ 0x50004088) SCU Service Request Mask */ -} SCU_INTERRUPT_TypeDef; - -/* ================================================================================ */ -/* ================ SCU_PARITY ================ */ -/* ================================================================================ */ - -/** - * @brief System Control Unit (SCU_PARITY) - */ - -typedef struct { /*!< (@ 0x5000413C) SCU_PARITY Structure */ - __IO uint32_t PEEN; /*!< (@ 0x5000413C) Parity Error Enable Register */ - __IO uint32_t MCHKCON; /*!< (@ 0x50004140) Memory Checking Control Register */ - __IO uint32_t PETE; /*!< (@ 0x50004144) Parity Error Trap Enable Register */ - __IO uint32_t PERSTEN; /*!< (@ 0x50004148) Parity Error Reset Enable Register */ - __I uint32_t RESERVED; - __IO uint32_t PEFLAG; /*!< (@ 0x50004150) Parity Error Flag Register */ - __IO uint32_t PMTPR; /*!< (@ 0x50004154) Parity Memory Test Pattern Register */ - __IO uint32_t PMTSR; /*!< (@ 0x50004158) Parity Memory Test Select Register */ -} SCU_PARITY_TypeDef; - -/* ================================================================================ */ -/* ================ SCU_TRAP ================ */ -/* ================================================================================ */ - -/** - * @brief System Control Unit (SCU_TRAP) - */ - -typedef struct { /*!< (@ 0x50004160) SCU_TRAP Structure */ - __I uint32_t TRAPSTAT; /*!< (@ 0x50004160) Trap Status Register */ - __I uint32_t TRAPRAW; /*!< (@ 0x50004164) Trap Raw Status Register */ - __IO uint32_t TRAPDIS; /*!< (@ 0x50004168) Trap Disable Register */ - __O uint32_t TRAPCLR; /*!< (@ 0x5000416C) Trap Clear Register */ - __O uint32_t TRAPSET; /*!< (@ 0x50004170) Trap Set Register */ -} SCU_TRAP_TypeDef; - -/* ================================================================================ */ -/* ================ SCU_HIBERNATE ================ */ -/* ================================================================================ */ - -/** - * @brief System Control Unit (SCU_HIBERNATE) - */ - -typedef struct { /*!< (@ 0x50004300) SCU_HIBERNATE Structure */ - __I uint32_t HDSTAT; /*!< (@ 0x50004300) Hibernate Domain Status Register */ - __O uint32_t HDCLR; /*!< (@ 0x50004304) Hibernate Domain Status Clear Register */ - __O uint32_t HDSET; /*!< (@ 0x50004308) Hibernate Domain Status Set Register */ - __IO uint32_t HDCR; /*!< (@ 0x5000430C) Hibernate Domain Control Register */ - __I uint32_t RESERVED; - __IO uint32_t OSCSICTRL; /*!< (@ 0x50004314) fOSI Control Register */ - __I uint32_t OSCULSTAT; /*!< (@ 0x50004318) OSC_ULP Status Register */ - __IO uint32_t OSCULCTRL; /*!< (@ 0x5000431C) OSC_ULP Control Register */ - __IO uint32_t LPACCONF; /*!< (@ 0x50004320) Analog Wake-up Configuration Register */ - __IO uint32_t LPACTH0; /*!< (@ 0x50004324) LPAC Threshold Register 0 */ - __IO uint32_t LPACTH1; /*!< (@ 0x50004328) LPAC Threshold Register 1 */ - __I uint32_t LPACST; /*!< (@ 0x5000432C) Hibernate Analog Control State Register */ - __O uint32_t LPACCLR; /*!< (@ 0x50004330) LPAC Control Clear Register */ - __O uint32_t LPACSET; /*!< (@ 0x50004334) LPAC Control Set Register */ - __I uint32_t HINTST; /*!< (@ 0x50004338) Hibernate Internal Control State Register */ - __O uint32_t HINTCLR; /*!< (@ 0x5000433C) Hibernate Internal Control Clear Register */ - __O uint32_t HINTSET; /*!< (@ 0x50004340) Hibernate Internal Control Set Register */ -} SCU_HIBERNATE_TypeDef; - -/* ================================================================================ */ -/* ================ SCU_POWER ================ */ -/* ================================================================================ */ - -/** - * @brief System Control Unit (SCU_POWER) - */ - -typedef struct { /*!< (@ 0x50004200) SCU_POWER Structure */ - __I uint32_t PWRSTAT; /*!< (@ 0x50004200) PCU Status Register */ - __O uint32_t PWRSET; /*!< (@ 0x50004204) PCU Set Control Register */ - __O uint32_t PWRCLR; /*!< (@ 0x50004208) PCU Clear Control Register */ - __I uint32_t RESERVED; - __I uint32_t EVRSTAT; /*!< (@ 0x50004210) EVR Status Register */ - __I uint32_t EVRVADCSTAT; /*!< (@ 0x50004214) EVR VADC Status Register */ - __I uint32_t RESERVED1[5]; - __IO uint32_t PWRMON; /*!< (@ 0x5000422C) Power Monitor Control */ -} SCU_POWER_TypeDef; - -/* ================================================================================ */ -/* ================ SCU_RESET ================ */ -/* ================================================================================ */ - -/** - * @brief System Control Unit (SCU_RESET) - */ - -typedef struct { /*!< (@ 0x50004400) SCU_RESET Structure */ - __I uint32_t RSTSTAT; /*!< (@ 0x50004400) RCU Reset Status */ - __O uint32_t RSTSET; /*!< (@ 0x50004404) RCU Reset Set Register */ - __O uint32_t RSTCLR; /*!< (@ 0x50004408) RCU Reset Clear Register */ - __I uint32_t PRSTAT0; /*!< (@ 0x5000440C) RCU Peripheral 0 Reset Status */ - __O uint32_t PRSET0; /*!< (@ 0x50004410) RCU Peripheral 0 Reset Set */ - __O uint32_t PRCLR0; /*!< (@ 0x50004414) RCU Peripheral 0 Reset Clear */ - __I uint32_t PRSTAT1; /*!< (@ 0x50004418) RCU Peripheral 1 Reset Status */ - __O uint32_t PRSET1; /*!< (@ 0x5000441C) RCU Peripheral 1 Reset Set */ - __O uint32_t PRCLR1; /*!< (@ 0x50004420) RCU Peripheral 1 Reset Clear */ - __I uint32_t PRSTAT2; /*!< (@ 0x50004424) RCU Peripheral 2 Reset Status */ - __O uint32_t PRSET2; /*!< (@ 0x50004428) RCU Peripheral 2 Reset Set */ - __O uint32_t PRCLR2; /*!< (@ 0x5000442C) RCU Peripheral 2 Reset Clear */ -} SCU_RESET_TypeDef; - -/* ================================================================================ */ -/* ================ LEDTS [LEDTS0] ================ */ -/* ================================================================================ */ - -/** - * @brief LED and Touch Sense Unit 0 (LEDTS) - */ - -typedef struct { /*!< (@ 0x48010000) LEDTS Structure */ - __I uint32_t ID; /*!< (@ 0x48010000) Module Identification Register */ - __IO uint32_t GLOBCTL; /*!< (@ 0x48010004) Global Control Register */ - __IO uint32_t FNCTL; /*!< (@ 0x48010008) Function Control Register */ - __O uint32_t EVFR; /*!< (@ 0x4801000C) Event Flag Register */ - __IO uint32_t TSVAL; /*!< (@ 0x48010010) Touch-sense TS-Counter Value */ - __IO uint32_t LINE0; /*!< (@ 0x48010014) Line Pattern Register 0 */ - __IO uint32_t LINE1; /*!< (@ 0x48010018) Line Pattern Register 1 */ - __IO uint32_t LDCMP0; /*!< (@ 0x4801001C) LED Compare Register 0 */ - __IO uint32_t LDCMP1; /*!< (@ 0x48010020) LED Compare Register 1 */ - __IO uint32_t TSCMP0; /*!< (@ 0x48010024) Touch-sense Compare Register 0 */ - __IO uint32_t TSCMP1; /*!< (@ 0x48010028) Touch-sense Compare Register 1 */ -} LEDTS0_GLOBAL_TypeDef; - -/* ================================================================================ */ -/* ================ ETH0_CON ================ */ -/* ================================================================================ */ - -/** - * @brief Ethernet Control Register (ETH0_CON) - */ - -typedef struct { /*!< (@ 0x50004040) ETH0_CON Structure */ - __IO uint32_t CON; /*!< (@ 0x50004040) Ethernet 0 Port Control Register */ -} ETH0_CON_GLOBAL_TypeDef; - -/* ================================================================================ */ -/* ================ ETH [ETH0] ================ */ -/* ================================================================================ */ - -/** - * @brief Ethernet Unit 0 (ETH) - */ - -typedef struct { /*!< (@ 0x5000C000) ETH Structure */ - __IO uint32_t MAC_CONFIGURATION; /*!< (@ 0x5000C000) MAC Configuration Register */ - __IO uint32_t MAC_FRAME_FILTER; /*!< (@ 0x5000C004) MAC Frame Filter */ - __IO uint32_t HASH_TABLE_HIGH; /*!< (@ 0x5000C008) Hash Table High Register */ - __IO uint32_t HASH_TABLE_LOW; /*!< (@ 0x5000C00C) Hash Table Low Register */ - __IO uint32_t GMII_ADDRESS; /*!< (@ 0x5000C010) MII Address Register */ - __IO uint32_t GMII_DATA; /*!< (@ 0x5000C014) MII Data Register */ - __IO uint32_t FLOW_CONTROL; /*!< (@ 0x5000C018) Flow Control Register */ - __IO uint32_t VLAN_TAG; /*!< (@ 0x5000C01C) VLAN Tag Register */ - __I uint32_t VERSION; /*!< (@ 0x5000C020) Version Register */ - __I uint32_t DEBUG; /*!< (@ 0x5000C024) Debug Register */ - __IO uint32_t - REMOTE_WAKE_UP_FRAME_FILTER; /*!< (@ 0x5000C028) Remote Wake Up Frame Filter Register */ - __IO uint32_t PMT_CONTROL_STATUS; /*!< (@ 0x5000C02C) PMT Control and Status Register */ - __I uint32_t RESERVED[2]; - __I uint32_t INTERRUPT_STATUS; /*!< (@ 0x5000C038) Interrupt Register */ - __IO uint32_t INTERRUPT_MASK; /*!< (@ 0x5000C03C) Interrupt Mask Register */ - __IO uint32_t MAC_ADDRESS0_HIGH; /*!< (@ 0x5000C040) MAC Address0 High Register */ - __IO uint32_t MAC_ADDRESS0_LOW; /*!< (@ 0x5000C044) MAC Address0 Low Register */ - __IO uint32_t MAC_ADDRESS1_HIGH; /*!< (@ 0x5000C048) MAC Address1 High Register */ - __IO uint32_t MAC_ADDRESS1_LOW; /*!< (@ 0x5000C04C) MAC Address1 Low Register */ - __IO uint32_t MAC_ADDRESS2_HIGH; /*!< (@ 0x5000C050) MAC Address2 High Register */ - __IO uint32_t MAC_ADDRESS2_LOW; /*!< (@ 0x5000C054) MAC Address2 Low Register */ - __IO uint32_t MAC_ADDRESS3_HIGH; /*!< (@ 0x5000C058) MAC Address3 High Register */ - __IO uint32_t MAC_ADDRESS3_LOW; /*!< (@ 0x5000C05C) MAC Address3 Low Register */ - __I uint32_t RESERVED1[40]; - __IO uint32_t MMC_CONTROL; /*!< (@ 0x5000C100) MMC Control Register */ - __I uint32_t MMC_RECEIVE_INTERRUPT; /*!< (@ 0x5000C104) MMC Receive Interrupt Register */ - __I uint32_t MMC_TRANSMIT_INTERRUPT; /*!< (@ 0x5000C108) MMC Transmit Interrupt Register */ - __IO uint32_t - MMC_RECEIVE_INTERRUPT_MASK; /*!< (@ 0x5000C10C) MMC Reveive Interrupt Mask Register */ - __IO uint32_t - MMC_TRANSMIT_INTERRUPT_MASK; /*!< (@ 0x5000C110) MMC Transmit Interrupt Mask Register */ - __I uint32_t TX_OCTET_COUNT_GOOD_BAD; /*!< (@ 0x5000C114) Transmit Octet Count for Good and Bad - Frames Register */ - __I uint32_t TX_FRAME_COUNT_GOOD_BAD; /*!< (@ 0x5000C118) Transmit Frame Count for Goodand Bad - Frames Register */ - __I uint32_t TX_BROADCAST_FRAMES_GOOD; /*!< (@ 0x5000C11C) Transmit Frame Count for Good - Broadcast Frames */ - __I uint32_t TX_MULTICAST_FRAMES_GOOD; /*!< (@ 0x5000C120) Transmit Frame Count for Good - Multicast Frames */ - __I uint32_t TX_64OCTETS_FRAMES_GOOD_BAD; /*!< (@ 0x5000C124) Transmit Octet Count for Good and - Bad 64 Byte Frames */ - __I uint32_t TX_65TO127OCTETS_FRAMES_GOOD_BAD; /*!< (@ 0x5000C128) Transmit Octet Count for Good - and Bad 65 to 127 Bytes Frames */ - __I uint32_t TX_128TO255OCTETS_FRAMES_GOOD_BAD; /*!< (@ 0x5000C12C) Transmit Octet Count for - Good and Bad 128 to 255 Bytes Frames */ - __I uint32_t TX_256TO511OCTETS_FRAMES_GOOD_BAD; /*!< (@ 0x5000C130) Transmit Octet Count for - Good and Bad 256 to 511 Bytes Frames */ - __I uint32_t TX_512TO1023OCTETS_FRAMES_GOOD_BAD; /*!< (@ 0x5000C134) Transmit Octet Count for - Good and Bad 512 to 1023 Bytes Frames */ - __I uint32_t TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD; /*!< (@ 0x5000C138) Transmit Octet Count for - Good and Bad 1024 to Maxsize Bytes Frames */ - __I uint32_t TX_UNICAST_FRAMES_GOOD_BAD; /*!< (@ 0x5000C13C) Transmit Frame Count for Good and - Bad Unicast Frames */ - __I uint32_t TX_MULTICAST_FRAMES_GOOD_BAD; /*!< (@ 0x5000C140) Transmit Frame Count for Good and - Bad Multicast Frames */ - __I uint32_t TX_BROADCAST_FRAMES_GOOD_BAD; /*!< (@ 0x5000C144) Transmit Frame Count for Good and - Bad Broadcast Frames */ - __I uint32_t TX_UNDERFLOW_ERROR_FRAMES; /*!< (@ 0x5000C148) Transmit Frame Count for Underflow - Error Frames */ - __I uint32_t TX_SINGLE_COLLISION_GOOD_FRAMES; /*!< (@ 0x5000C14C) Transmit Frame Count for - Frames Transmitted after Single Collision */ - __I uint32_t - TX_MULTIPLE_COLLISION_GOOD_FRAMES; /*!< (@ 0x5000C150) Transmit Frame Count for Frames - Transmitted after Multiple Collision */ - __I uint32_t TX_DEFERRED_FRAMES; /*!< (@ 0x5000C154) Tx Deferred Frames Register */ - __I uint32_t TX_LATE_COLLISION_FRAMES; /*!< (@ 0x5000C158) Transmit Frame Count for Late - Collision Error Frames */ - __I uint32_t TX_EXCESSIVE_COLLISION_FRAMES; /*!< (@ 0x5000C15C) Transmit Frame Count for - Excessive Collision Error Frames */ - __I uint32_t TX_CARRIER_ERROR_FRAMES; /*!< (@ 0x5000C160) Transmit Frame Count for Carrier Sense - Error Frames */ - __I uint32_t TX_OCTET_COUNT_GOOD; /*!< (@ 0x5000C164) Tx Octet Count Good Register */ - __I uint32_t TX_FRAME_COUNT_GOOD; /*!< (@ 0x5000C168) Tx Frame Count Good Register */ - __I uint32_t TX_EXCESSIVE_DEFERRAL_ERROR; /*!< (@ 0x5000C16C) Transmit Frame Count for Excessive - Deferral Error Frames */ - __I uint32_t TX_PAUSE_FRAMES; /*!< (@ 0x5000C170) Transmit Frame Count for Good PAUSE Frames */ - __I uint32_t - TX_VLAN_FRAMES_GOOD; /*!< (@ 0x5000C174) Transmit Frame Count for Good VLAN Frames */ - __I uint32_t - TX_OSIZE_FRAMES_GOOD; /*!< (@ 0x5000C178) Transmit Frame Count for Good Oversize Frames */ - __I uint32_t RESERVED2; - __I uint32_t - RX_FRAMES_COUNT_GOOD_BAD; /*!< (@ 0x5000C180) Receive Frame Count for Good and Bad Frames */ - __I uint32_t - RX_OCTET_COUNT_GOOD_BAD; /*!< (@ 0x5000C184) Receive Octet Count for Good and Bad Frames */ - __I uint32_t RX_OCTET_COUNT_GOOD; /*!< (@ 0x5000C188) Rx Octet Count Good Register */ - __I uint32_t RX_BROADCAST_FRAMES_GOOD; /*!< (@ 0x5000C18C) Receive Frame Count for Good - Broadcast Frames */ - __I uint32_t RX_MULTICAST_FRAMES_GOOD; /*!< (@ 0x5000C190) Receive Frame Count for Good - Multicast Frames */ - __I uint32_t - RX_CRC_ERROR_FRAMES; /*!< (@ 0x5000C194) Receive Frame Count for CRC Error Frames */ - __I uint32_t RX_ALIGNMENT_ERROR_FRAMES; /*!< (@ 0x5000C198) Receive Frame Count for Alignment - Error Frames */ - __I uint32_t - RX_RUNT_ERROR_FRAMES; /*!< (@ 0x5000C19C) Receive Frame Count for Runt Error Frames */ - __I uint32_t - RX_JABBER_ERROR_FRAMES; /*!< (@ 0x5000C1A0) Receive Frame Count for Jabber Error Frames */ - __I uint32_t - RX_UNDERSIZE_FRAMES_GOOD; /*!< (@ 0x5000C1A4) Receive Frame Count for Undersize Frames */ - __I uint32_t RX_OVERSIZE_FRAMES_GOOD; /*!< (@ 0x5000C1A8) Rx Oversize Frames Good Register */ - __I uint32_t RX_64OCTETS_FRAMES_GOOD_BAD; /*!< (@ 0x5000C1AC) Receive Frame Count for Good and - Bad 64 Byte Frames */ - __I uint32_t RX_65TO127OCTETS_FRAMES_GOOD_BAD; /*!< (@ 0x5000C1B0) Receive Frame Count for Good - and Bad 65 to 127 Bytes Frames */ - __I uint32_t RX_128TO255OCTETS_FRAMES_GOOD_BAD; /*!< (@ 0x5000C1B4) Receive Frame Count for Good - and Bad 128 to 255 Bytes Frames */ - __I uint32_t RX_256TO511OCTETS_FRAMES_GOOD_BAD; /*!< (@ 0x5000C1B8) Receive Frame Count for Good - and Bad 256 to 511 Bytes Frames */ - __I uint32_t RX_512TO1023OCTETS_FRAMES_GOOD_BAD; /*!< (@ 0x5000C1BC) Receive Frame Count for - Good and Bad 512 to 1,023 Bytes Frames */ - __I uint32_t - RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD; /*!< (@ 0x5000C1C0) Receive Frame Count for Good and Bad - 1,024 to Maxsize Bytes Frames */ - __I uint32_t - RX_UNICAST_FRAMES_GOOD; /*!< (@ 0x5000C1C4) Receive Frame Count for Good Unicast Frames */ - __I uint32_t - RX_LENGTH_ERROR_FRAMES; /*!< (@ 0x5000C1C8) Receive Frame Count for Length Error Frames */ - __I uint32_t RX_OUT_OF_RANGE_TYPE_FRAMES; /*!< (@ 0x5000C1CC) Receive Frame Count for Out of - Range Frames */ - __I uint32_t RX_PAUSE_FRAMES; /*!< (@ 0x5000C1D0) Receive Frame Count for PAUSE Frames */ - __I uint32_t - RX_FIFO_OVERFLOW_FRAMES; /*!< (@ 0x5000C1D4) Receive Frame Count for FIFO Overflow Frames */ - __I uint32_t RX_VLAN_FRAMES_GOOD_BAD; /*!< (@ 0x5000C1D8) Receive Frame Count for Good and Bad - VLAN Frames */ - __I uint32_t RX_WATCHDOG_ERROR_FRAMES; /*!< (@ 0x5000C1DC) Receive Frame Count for Watchdog - Error Frames */ - __I uint32_t - RX_RECEIVE_ERROR_FRAMES; /*!< (@ 0x5000C1E0) Receive Frame Count for Receive Error Frames */ - __I uint32_t RX_CONTROL_FRAMES_GOOD; /*!< (@ 0x5000C1E4) Receive Frame Count for Good Control - Frames Frames */ - __I uint32_t RESERVED3[6]; - __IO uint32_t MMC_IPC_RECEIVE_INTERRUPT_MASK; /*!< (@ 0x5000C200) MMC Receive Checksum Offload - Interrupt Mask Register */ - __I uint32_t RESERVED4; - __I uint32_t MMC_IPC_RECEIVE_INTERRUPT; /*!< (@ 0x5000C208) MMC Receive Checksum Offload - Interrupt Register */ - __I uint32_t RESERVED5; - __I uint32_t RXIPV4_GOOD_FRAMES; /*!< (@ 0x5000C210) RxIPv4 Good Frames Register */ - __I uint32_t RXIPV4_HEADER_ERROR_FRAMES; /*!< (@ 0x5000C214) Receive IPV4 Header Error Frame - Counter Register */ - __I uint32_t RXIPV4_NO_PAYLOAD_FRAMES; /*!< (@ 0x5000C218) Receive IPV4 No Payload Frame Counter - Register */ - __I uint32_t RXIPV4_FRAGMENTED_FRAMES; /*!< (@ 0x5000C21C) Receive IPV4 Fragmented Frame Counter - Register */ - __I uint32_t RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES; /*!< (@ 0x5000C220) Receive IPV4 UDP Checksum - Disabled Frame Counter Register */ - __I uint32_t RXIPV6_GOOD_FRAMES; /*!< (@ 0x5000C224) RxIPv6 Good Frames Register */ - __I uint32_t RXIPV6_HEADER_ERROR_FRAMES; /*!< (@ 0x5000C228) Receive IPV6 Header Error Frame - Counter Register */ - __I uint32_t RXIPV6_NO_PAYLOAD_FRAMES; /*!< (@ 0x5000C22C) Receive IPV6 No Payload Frame Counter - Register */ - __I uint32_t RXUDP_GOOD_FRAMES; /*!< (@ 0x5000C230) RxUDP Good Frames Register */ - __I uint32_t RXUDP_ERROR_FRAMES; /*!< (@ 0x5000C234) RxUDP Error Frames Register */ - __I uint32_t RXTCP_GOOD_FRAMES; /*!< (@ 0x5000C238) RxTCP Good Frames Register */ - __I uint32_t RXTCP_ERROR_FRAMES; /*!< (@ 0x5000C23C) RxTCP Error Frames Register */ - __I uint32_t RXICMP_GOOD_FRAMES; /*!< (@ 0x5000C240) RxICMP Good Frames Register */ - __I uint32_t RXICMP_ERROR_FRAMES; /*!< (@ 0x5000C244) RxICMP Error Frames Register */ - __I uint32_t RESERVED6[2]; - __I uint32_t RXIPV4_GOOD_OCTETS; /*!< (@ 0x5000C250) RxIPv4 Good Octets Register */ - __I uint32_t RXIPV4_HEADER_ERROR_OCTETS; /*!< (@ 0x5000C254) Receive IPV4 Header Error Octet - Counter Register */ - __I uint32_t RXIPV4_NO_PAYLOAD_OCTETS; /*!< (@ 0x5000C258) Receive IPV4 No Payload Octet Counter - Register */ - __I uint32_t RXIPV4_FRAGMENTED_OCTETS; /*!< (@ 0x5000C25C) Receive IPV4 Fragmented Octet Counter - Register */ - __I uint32_t RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS; /*!< (@ 0x5000C260) Receive IPV4 Fragmented - Octet Counter Register */ - __I uint32_t RXIPV6_GOOD_OCTETS; /*!< (@ 0x5000C264) RxIPv6 Good Octets Register */ - __I uint32_t RXIPV6_HEADER_ERROR_OCTETS; /*!< (@ 0x5000C268) Receive IPV6 Header Error Octet - Counter Register */ - __I uint32_t RXIPV6_NO_PAYLOAD_OCTETS; /*!< (@ 0x5000C26C) Receive IPV6 No Payload Octet Counter - Register */ - __I uint32_t RXUDP_GOOD_OCTETS; /*!< (@ 0x5000C270) Receive UDP Good Octets Register */ - __I uint32_t RXUDP_ERROR_OCTETS; /*!< (@ 0x5000C274) Receive UDP Error Octets Register */ - __I uint32_t RXTCP_GOOD_OCTETS; /*!< (@ 0x5000C278) Receive TCP Good Octets Register */ - __I uint32_t RXTCP_ERROR_OCTETS; /*!< (@ 0x5000C27C) Receive TCP Error Octets Register */ - __I uint32_t RXICMP_GOOD_OCTETS; /*!< (@ 0x5000C280) Receive ICMP Good Octets Register */ - __I uint32_t RXICMP_ERROR_OCTETS; /*!< (@ 0x5000C284) Receive ICMP Error Octets Register */ - __I uint32_t RESERVED7[286]; - __IO uint32_t TIMESTAMP_CONTROL; /*!< (@ 0x5000C700) Timestamp Control Register */ - __IO uint32_t SUB_SECOND_INCREMENT; /*!< (@ 0x5000C704) Sub-Second Increment Register */ - __I uint32_t SYSTEM_TIME_SECONDS; /*!< (@ 0x5000C708) System Time - Seconds Register */ - __I uint32_t SYSTEM_TIME_NANOSECONDS; /*!< (@ 0x5000C70C) System Time Nanoseconds Register */ - __IO uint32_t - SYSTEM_TIME_SECONDS_UPDATE; /*!< (@ 0x5000C710) System Time - Seconds Update Register */ - __IO uint32_t SYSTEM_TIME_NANOSECONDS_UPDATE; /*!< (@ 0x5000C714) System Time Nanoseconds Update - Register */ - __IO uint32_t TIMESTAMP_ADDEND; /*!< (@ 0x5000C718) Timestamp Addend Register */ - __IO uint32_t TARGET_TIME_SECONDS; /*!< (@ 0x5000C71C) Target Time Seconds Register */ - __IO uint32_t TARGET_TIME_NANOSECONDS; /*!< (@ 0x5000C720) Target Time Nanoseconds Register */ - __IO uint32_t SYSTEM_TIME_HIGHER_WORD_SECONDS; /*!< (@ 0x5000C724) System Time - Higher Word - Seconds Register */ - __I uint32_t TIMESTAMP_STATUS; /*!< (@ 0x5000C728) Timestamp Status Register */ - __IO uint32_t PPS_CONTROL; /*!< (@ 0x5000C72C) PPS Control Register */ - __I uint32_t RESERVED8[564]; - __IO uint32_t BUS_MODE; /*!< (@ 0x5000D000) Bus Mode Register */ - __IO uint32_t TRANSMIT_POLL_DEMAND; /*!< (@ 0x5000D004) Transmit Poll Demand Register */ - __IO uint32_t RECEIVE_POLL_DEMAND; /*!< (@ 0x5000D008) Receive Poll Demand Register */ - __IO uint32_t - RECEIVE_DESCRIPTOR_LIST_ADDRESS; /*!< (@ 0x5000D00C) Receive Descriptor Address Register */ - __IO uint32_t TRANSMIT_DESCRIPTOR_LIST_ADDRESS; /*!< (@ 0x5000D010) Transmit descripter Address - Register */ - __IO uint32_t STATUS; /*!< (@ 0x5000D014) Status Register */ - __IO uint32_t OPERATION_MODE; /*!< (@ 0x5000D018) Operation Mode Register */ - __IO uint32_t INTERRUPT_ENABLE; /*!< (@ 0x5000D01C) Interrupt Enable Register */ - __I uint32_t MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER; /*!< (@ 0x5000D020) Missed Frame and - Buffer Overflow Counter Register */ - __IO uint32_t RECEIVE_INTERRUPT_WATCHDOG_TIMER; /*!< (@ 0x5000D024) Receive Interrupt Watchdog - Timer Register */ - __I uint32_t RESERVED9; - __I uint32_t AHB_STATUS; /*!< (@ 0x5000D02C) AHB Status Register */ - __I uint32_t RESERVED10[6]; - __I uint32_t CURRENT_HOST_TRANSMIT_DESCRIPTOR; /*!< (@ 0x5000D048) Current Host Transmit - Descriptor Register */ - __I uint32_t CURRENT_HOST_RECEIVE_DESCRIPTOR; /*!< (@ 0x5000D04C) Current Host Receive - Descriptor Register */ - __I uint32_t CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS; /*!< (@ 0x5000D050) Current Host Transmit - Buffer Address Register */ - __I uint32_t CURRENT_HOST_RECEIVE_BUFFER_ADDRESS; /*!< (@ 0x5000D054) Current Host Receive - Buffer Address Register */ - __IO uint32_t HW_FEATURE; /*!< (@ 0x5000D058) HW Feature Register */ -} ETH_GLOBAL_TypeDef; - -/* ================================================================================ */ -/* ================ USB [USB0] ================ */ -/* ================================================================================ */ - -/** - * @brief Universal Serial Bus (USB) - */ - -typedef struct { /*!< (@ 0x50040000) USB Structure */ - __IO uint32_t GOTGCTL; /*!< (@ 0x50040000) Control and Status Register */ - __IO uint32_t GOTGINT; /*!< (@ 0x50040004) OTG Interrupt Register */ - __IO uint32_t GAHBCFG; /*!< (@ 0x50040008) AHB Configuration Register */ - __IO uint32_t GUSBCFG; /*!< (@ 0x5004000C) USB Configuration Register */ - __IO uint32_t GRSTCTL; /*!< (@ 0x50040010) Reset Register */ - - union { - __IO uint32_t GINTSTS_DEVICEMODE; /*!< (@ 0x50040014) Interrupt Register [DEVICEMODE] */ - __IO uint32_t GINTSTS_HOSTMODE; /*!< (@ 0x50040014) Interrupt Register [HOSTMODE] */ - }; - - union { - __IO uint32_t - GINTMSK_DEVICEMODE; /*!< (@ 0x50040018) Interrupt Mask Register [DEVICEMODE] */ - __IO uint32_t GINTMSK_HOSTMODE; /*!< (@ 0x50040018) Interrupt Mask Register [HOSTMODE] */ - }; - - union { - __I uint32_t GRXSTSR_DEVICEMODE; /*!< (@ 0x5004001C) Receive Status Debug Read Register - [DEVICEMODE] */ - __I uint32_t - GRXSTSR_HOSTMODE; /*!< (@ 0x5004001C) Receive Status Debug Read Register [HOSTMODE] */ - }; - - union { - __I uint32_t - GRXSTSP_HOSTMODE; /*!< (@ 0x50040020) Receive Status Read and Pop Register [HOSTMODE] */ - __I uint32_t GRXSTSP_DEVICEMODE; /*!< (@ 0x50040020) Receive Status Read and Pop Register - [DEVICEMODE] */ - }; - - __IO uint32_t GRXFSIZ; /*!< (@ 0x50040024) Receive FIFO Size Register */ - - union { - __IO uint32_t GNPTXFSIZ_DEVICEMODE; /*!< (@ 0x50040028) Non-Periodic Transmit FIFO Size - Register [DEVICEMODE] */ - __IO uint32_t GNPTXFSIZ_HOSTMODE; /*!< (@ 0x50040028) Non-Periodic Transmit FIFO Size - Register [HOSTMODE] */ - }; - - __I uint32_t GNPTXSTS; /*!< (@ 0x5004002C) Non-Periodic Transmit FIFO/Queue Status Register */ - __I uint32_t RESERVED[3]; - __IO uint32_t GUID; /*!< (@ 0x5004003C) USB Module Identification Register */ - __I uint32_t RESERVED1[7]; - __IO uint32_t GDFIFOCFG; /*!< (@ 0x5004005C) Global DFIFO Software Config Register */ - __I uint32_t RESERVED2[40]; - __IO uint32_t HPTXFSIZ; /*!< (@ 0x50040100) Host Periodic Transmit FIFO Size Register */ - __IO uint32_t DIEPTXF1; /*!< (@ 0x50040104) Device IN Endpoint Transmit FIFO Size Register */ - __IO uint32_t DIEPTXF2; /*!< (@ 0x50040108) Device IN Endpoint Transmit FIFO Size Register */ - __IO uint32_t DIEPTXF3; /*!< (@ 0x5004010C) Device IN Endpoint Transmit FIFO Size Register */ - __IO uint32_t DIEPTXF4; /*!< (@ 0x50040110) Device IN Endpoint Transmit FIFO Size Register */ - __IO uint32_t DIEPTXF5; /*!< (@ 0x50040114) Device IN Endpoint Transmit FIFO Size Register */ - __IO uint32_t DIEPTXF6; /*!< (@ 0x50040118) Device IN Endpoint Transmit FIFO Size Register */ - __I uint32_t RESERVED3[185]; - __IO uint32_t HCFG; /*!< (@ 0x50040400) Host Configuration Register */ - __IO uint32_t HFIR; /*!< (@ 0x50040404) Host Frame Interval Register */ - __IO uint32_t HFNUM; /*!< (@ 0x50040408) Host Frame Number/Frame Time Remaining Register */ - __I uint32_t RESERVED4; - __IO uint32_t HPTXSTS; /*!< (@ 0x50040410) Host Periodic Transmit FIFO/ Queue Status Register */ - __I uint32_t HAINT; /*!< (@ 0x50040414) Host All Channels Interrupt Register */ - __IO uint32_t HAINTMSK; /*!< (@ 0x50040418) Host All Channels Interrupt Mask Register */ - __IO uint32_t HFLBADDR; /*!< (@ 0x5004041C) Host Frame List Base Address Register */ - __I uint32_t RESERVED5[8]; - __IO uint32_t HPRT; /*!< (@ 0x50040440) Host Port Control and Status Register */ - __I uint32_t RESERVED6[239]; - __IO uint32_t DCFG; /*!< (@ 0x50040800) Device Configuration Register */ - __IO uint32_t DCTL; /*!< (@ 0x50040804) Device Control Register */ - __I uint32_t DSTS; /*!< (@ 0x50040808) Device Status Register */ - __I uint32_t RESERVED7; - __IO uint32_t DIEPMSK; /*!< (@ 0x50040810) Device IN Endpoint Common Interrupt Mask Register */ - __IO uint32_t DOEPMSK; /*!< (@ 0x50040814) Device OUT Endpoint Common Interrupt Mask Register */ - __I uint32_t DAINT; /*!< (@ 0x50040818) Device All Endpoints Interrupt Register */ - __IO uint32_t DAINTMSK; /*!< (@ 0x5004081C) Device All Endpoints Interrupt Mask Register */ - __I uint32_t RESERVED8[2]; - __IO uint32_t DVBUSDIS; /*!< (@ 0x50040828) Device VBUS Discharge Time Register */ - __IO uint32_t DVBUSPULSE; /*!< (@ 0x5004082C) Device VBUS Pulsing Time Register */ - __I uint32_t RESERVED9; - __IO uint32_t DIEPEMPMSK; /*!< (@ 0x50040834) Device IN Endpoint FIFO Empty Interrupt Mask - Register */ - __I uint32_t RESERVED10[370]; - __IO uint32_t PCGCCTL; /*!< (@ 0x50040E00) Power and Clock Gating Control Register */ -} USB0_GLOBAL_TypeDef; - -/* ================================================================================ */ -/* ================ USB0_EP0 ================ */ -/* ================================================================================ */ - -/** - * @brief Universal Serial Bus (USB0_EP0) - */ - -typedef struct { /*!< (@ 0x50040900) USB0_EP0 Structure */ - __IO uint32_t DIEPCTL0; /*!< (@ 0x50040900) Device Control IN Endpoint Control Register */ - __I uint32_t RESERVED; - __IO uint32_t DIEPINT0; /*!< (@ 0x50040908) Device Endpoint Interrupt Register */ - __I uint32_t RESERVED1; - __IO uint32_t DIEPTSIZ0; /*!< (@ 0x50040910) Device IN Endpoint Transfer Size Register */ - __IO uint32_t DIEPDMA0; /*!< (@ 0x50040914) Device Endpoint DMA Address Register */ - __I uint32_t DTXFSTS0; /*!< (@ 0x50040918) Device IN Endpoint Transmit FIFO Status Register */ - __I uint32_t DIEPDMAB0; /*!< (@ 0x5004091C) Device Endpoint DMA Buffer Address Register */ - __I uint32_t RESERVED2[120]; - __IO uint32_t DOEPCTL0; /*!< (@ 0x50040B00) Device Control OUT Endpoint Control Register */ - __I uint32_t RESERVED3; - __IO uint32_t DOEPINT0; /*!< (@ 0x50040B08) Device Endpoint Interrupt Register */ - __I uint32_t RESERVED4; - __IO uint32_t DOEPTSIZ0; /*!< (@ 0x50040B10) Device OUT Endpoint Transfer Size Register */ - __IO uint32_t DOEPDMA0; /*!< (@ 0x50040B14) Device Endpoint DMA Address Register */ - __I uint32_t RESERVED5; - __I uint32_t DOEPDMAB0; /*!< (@ 0x50040B1C) Device Endpoint DMA Buffer Address Register */ -} USB0_EP0_TypeDef; - -/* ================================================================================ */ -/* ================ USB_EP [USB0_EP1] ================ */ -/* ================================================================================ */ - -/** - * @brief Universal Serial Bus (USB_EP) - */ - -typedef struct { /*!< (@ 0x50040920) USB_EP Structure */ - - union { - __IO uint32_t - DIEPCTL_INTBULK; /*!< (@ 0x50040920) Device Endpoint Control Register [INTBULK] */ - __IO uint32_t - DIEPCTL_ISOCONT; /*!< (@ 0x50040920) Device Endpoint Control Register [ISOCONT] */ - }; - - __I uint32_t RESERVED; - __IO uint32_t DIEPINT; /*!< (@ 0x50040928) Device Endpoint Interrupt Register */ - __I uint32_t RESERVED1; - __IO uint32_t DIEPTSIZ; /*!< (@ 0x50040930) Device Endpoint Transfer Size Register */ - __IO uint32_t DIEPDMA; /*!< (@ 0x50040934) Device Endpoint DMA Address Register */ - __I uint32_t DTXFSTS; /*!< (@ 0x50040938) Device IN Endpoint Transmit FIFO Status Register */ - __I uint32_t DIEPDMAB; /*!< (@ 0x5004093C) Device Endpoint DMA Buffer Address Register */ - __I uint32_t RESERVED2[120]; - - union { - __IO uint32_t - DOEPCTL_INTBULK; /*!< (@ 0x50040B20) Device Endpoint Control Register [INTBULK] */ - __IO uint32_t - DOEPCTL_ISOCONT; /*!< (@ 0x50040B20) Device Endpoint Control Register [ISOCONT] */ - }; - - __I uint32_t RESERVED3; - __IO uint32_t DOEPINT; /*!< (@ 0x50040B28) Device Endpoint Interrupt Register */ - __I uint32_t RESERVED4; - - union { - __IO uint32_t - DOEPTSIZ_CONTROL; /*!< (@ 0x50040B30) Device Endpoint Transfer Size Register [CONT] */ - __IO uint32_t - DOEPTSIZ_ISO; /*!< (@ 0x50040B30) Device Endpoint Transfer Size Register [ISO] */ - }; - - __IO uint32_t DOEPDMA; /*!< (@ 0x50040B34) Device Endpoint DMA Address Register */ - __I uint32_t RESERVED5; - __I uint32_t DOEPDMAB; /*!< (@ 0x50040B3C) Device Endpoint DMA Buffer Address Register */ -} USB0_EP_TypeDef; - -/* ================================================================================ */ -/* ================ USB_CH [USB0_CH0] ================ */ -/* ================================================================================ */ - -/** - * @brief Universal Serial Bus (USB_CH) - */ - -typedef struct { /*!< (@ 0x50040500) USB_CH Structure */ - __IO uint32_t HCCHAR; /*!< (@ 0x50040500) Host Channel Characteristics Register */ - __I uint32_t RESERVED; - __IO uint32_t HCINT; /*!< (@ 0x50040508) Host Channel Interrupt Register */ - __IO uint32_t HCINTMSK; /*!< (@ 0x5004050C) Host Channel Interrupt Mask Register */ - - union { - __IO uint32_t HCTSIZ_SCATGATHER; /*!< (@ 0x50040510) Host Channel Transfer Size Register - [SCATGATHER] */ - __IO uint32_t HCTSIZ_BUFFERMODE; /*!< (@ 0x50040510) Host Channel Transfer Size Register - [BUFFERMODE] */ - }; - - union { - __IO uint32_t - HCDMA_SCATGATHER; /*!< (@ 0x50040514) Host Channel DMA Address Register [SCATGATHER] */ - __IO uint32_t - HCDMA_BUFFERMODE; /*!< (@ 0x50040514) Host Channel DMA Address Register [BUFFERMODE] */ - }; - - __I uint32_t RESERVED1; - __I uint32_t HCDMAB; /*!< (@ 0x5004051C) Host Channel DMA Buffer Address Register */ -} USB0_CH_TypeDef; - -/* ================================================================================ */ -/* ================ USIC [USIC0] ================ */ -/* ================================================================================ */ - -/** - * @brief Universal Serial Interface Controller 0 (USIC) - */ - -typedef struct { /*!< (@ 0x40030008) USIC Structure */ - __I uint32_t ID; /*!< (@ 0x40030008) Module Identification Register */ -} USIC_GLOBAL_TypeDef; - -/* ================================================================================ */ -/* ================ USIC_CH [USIC0_CH0] ================ */ -/* ================================================================================ */ - -/** - * @brief Universal Serial Interface Controller 0 (USIC_CH) - */ - -typedef struct { /*!< (@ 0x40030000) USIC_CH Structure */ - __I uint32_t RESERVED; - __I uint32_t CCFG; /*!< (@ 0x40030004) Channel Configuration Register */ - __I uint32_t RESERVED1; - __IO uint32_t KSCFG; /*!< (@ 0x4003000C) Kernel State Configuration Register */ - __IO uint32_t FDR; /*!< (@ 0x40030010) Fractional Divider Register */ - __IO uint32_t BRG; /*!< (@ 0x40030014) Baud Rate Generator Register */ - __IO uint32_t INPR; /*!< (@ 0x40030018) Interrupt Node Pointer Register */ - __IO uint32_t DX0CR; /*!< (@ 0x4003001C) Input Control Register 0 */ - __IO uint32_t DX1CR; /*!< (@ 0x40030020) Input Control Register 1 */ - __IO uint32_t DX2CR; /*!< (@ 0x40030024) Input Control Register 2 */ - __IO uint32_t DX3CR; /*!< (@ 0x40030028) Input Control Register 3 */ - __IO uint32_t DX4CR; /*!< (@ 0x4003002C) Input Control Register 4 */ - __IO uint32_t DX5CR; /*!< (@ 0x40030030) Input Control Register 5 */ - __IO uint32_t SCTR; /*!< (@ 0x40030034) Shift Control Register */ - __IO uint32_t TCSR; /*!< (@ 0x40030038) Transmit Control/Status Register */ - - union { - __IO uint32_t PCR_IICMode; /*!< (@ 0x4003003C) Protocol Control Register [IIC Mode] */ - __IO uint32_t PCR_IISMode; /*!< (@ 0x4003003C) Protocol Control Register [IIS Mode] */ - __IO uint32_t PCR_SSCMode; /*!< (@ 0x4003003C) Protocol Control Register [SSC Mode] */ - __IO uint32_t PCR; /*!< (@ 0x4003003C) Protocol Control Register */ - __IO uint32_t PCR_ASCMode; /*!< (@ 0x4003003C) Protocol Control Register [ASC Mode] */ - }; - - __IO uint32_t CCR; /*!< (@ 0x40030040) Channel Control Register */ - __IO uint32_t CMTR; /*!< (@ 0x40030044) Capture Mode Timer Register */ - - union { - __IO uint32_t PSR_IICMode; /*!< (@ 0x40030048) Protocol Status Register [IIC Mode] */ - __IO uint32_t PSR_IISMode; /*!< (@ 0x40030048) Protocol Status Register [IIS Mode] */ - __IO uint32_t PSR_SSCMode; /*!< (@ 0x40030048) Protocol Status Register [SSC Mode] */ - __IO uint32_t PSR; /*!< (@ 0x40030048) Protocol Status Register */ - __IO uint32_t PSR_ASCMode; /*!< (@ 0x40030048) Protocol Status Register [ASC Mode] */ - }; - - __O uint32_t PSCR; /*!< (@ 0x4003004C) Protocol Status Clear Register */ - __I uint32_t RBUFSR; /*!< (@ 0x40030050) Receiver Buffer Status Register */ - __I uint32_t RBUF; /*!< (@ 0x40030054) Receiver Buffer Register */ - __I uint32_t RBUFD; /*!< (@ 0x40030058) Receiver Buffer Register for Debugger */ - __I uint32_t RBUF0; /*!< (@ 0x4003005C) Receiver Buffer Register 0 */ - __I uint32_t RBUF1; /*!< (@ 0x40030060) Receiver Buffer Register 1 */ - __I uint32_t RBUF01SR; /*!< (@ 0x40030064) Receiver Buffer 01 Status Register */ - __O uint32_t FMR; /*!< (@ 0x40030068) Flag Modification Register */ - __I uint32_t RESERVED2[5]; - __IO uint32_t TBUF[32]; /*!< (@ 0x40030080) Transmit Buffer */ - __IO uint32_t BYP; /*!< (@ 0x40030100) Bypass Data Register */ - __IO uint32_t BYPCR; /*!< (@ 0x40030104) Bypass Control Register */ - __IO uint32_t TBCTR; /*!< (@ 0x40030108) Transmitter Buffer Control Register */ - __IO uint32_t RBCTR; /*!< (@ 0x4003010C) Receiver Buffer Control Register */ - __I uint32_t TRBPTR; /*!< (@ 0x40030110) Transmit/Receive Buffer Pointer Register */ - __IO uint32_t TRBSR; /*!< (@ 0x40030114) Transmit/Receive Buffer Status Register */ - __O uint32_t TRBSCR; /*!< (@ 0x40030118) Transmit/Receive Buffer Status Clear Register */ - __I uint32_t OUTR; /*!< (@ 0x4003011C) Receiver Buffer Output Register */ - __I uint32_t OUTDR; /*!< (@ 0x40030120) Receiver Buffer Output Register L for Debugger */ - __I uint32_t RESERVED3[23]; - __O uint32_t IN[32]; /*!< (@ 0x40030180) Transmit FIFO Buffer */ -} USIC_CH_TypeDef; - -/* ================================================================================ */ -/* ================ CAN ================ */ -/* ================================================================================ */ - -/** - * @brief Controller Area Networks (CAN) - */ - -typedef struct { /*!< (@ 0x48014000) CAN Structure */ - __IO uint32_t CLC; /*!< (@ 0x48014000) CAN Clock Control Register */ - __I uint32_t RESERVED; - __I uint32_t ID; /*!< (@ 0x48014008) Module Identification Register */ - __IO uint32_t FDR; /*!< (@ 0x4801400C) CAN Fractional Divider Register */ - __I uint32_t RESERVED1[60]; - __I uint32_t LIST[8]; /*!< (@ 0x48014100) List Register */ - __I uint32_t RESERVED2[8]; - __IO uint32_t MSPND[8]; /*!< (@ 0x48014140) Message Pending Register */ - __I uint32_t RESERVED3[8]; - __I uint32_t MSID[8]; /*!< (@ 0x48014180) Message Index Register */ - __I uint32_t RESERVED4[8]; - __IO uint32_t MSIMASK; /*!< (@ 0x480141C0) Message Index Mask Register */ - __IO uint32_t PANCTR; /*!< (@ 0x480141C4) Panel Control Register */ - __IO uint32_t MCR; /*!< (@ 0x480141C8) Module Control Register */ - __O uint32_t MITR; /*!< (@ 0x480141CC) Module Interrupt Trigger Register */ -} CAN_GLOBAL_TypeDef; - -/* ================================================================================ */ -/* ================ CAN_NODE [CAN_NODE0] ================ */ -/* ================================================================================ */ - -/** - * @brief Controller Area Networks (CAN_NODE) - */ - -typedef struct { /*!< (@ 0x48014200) CAN_NODE Structure */ - __IO uint32_t NCR; /*!< (@ 0x48014200) Node Control Register */ - __IO uint32_t NSR; /*!< (@ 0x48014204) Node Status Register */ - __IO uint32_t NIPR; /*!< (@ 0x48014208) Node Interrupt Pointer Register */ - __IO uint32_t NPCR; /*!< (@ 0x4801420C) Node Port Control Register */ - __IO uint32_t NBTR; /*!< (@ 0x48014210) Node Bit Timing Register */ - __IO uint32_t NECNT; /*!< (@ 0x48014214) Node Error Counter Register */ - __IO uint32_t NFCR; /*!< (@ 0x48014218) Node Frame Counter Register */ -} CAN_NODE_TypeDef; - -/* ================================================================================ */ -/* ================ CAN_MO [CAN_MO0] ================ */ -/* ================================================================================ */ - -/** - * @brief Controller Area Networks (CAN_MO) - */ - -typedef struct { /*!< (@ 0x48015000) CAN_MO Structure */ - __IO uint32_t MOFCR; /*!< (@ 0x48015000) Message Object Function Control Register */ - __IO uint32_t MOFGPR; /*!< (@ 0x48015004) Message Object FIFO/Gateway Pointer Register */ - __IO uint32_t MOIPR; /*!< (@ 0x48015008) Message Object Interrupt Pointer Register */ - __IO uint32_t MOAMR; /*!< (@ 0x4801500C) Message Object Acceptance Mask Register */ - __IO uint32_t MODATAL; /*!< (@ 0x48015010) Message Object Data Register Low */ - __IO uint32_t MODATAH; /*!< (@ 0x48015014) Message Object Data Register High */ - __IO uint32_t MOAR; /*!< (@ 0x48015018) Message Object Arbitration Register */ - - union { - __I uint32_t MOSTAT; /*!< (@ 0x4801501C) Message Object Status Register */ - __O uint32_t MOCTR; /*!< (@ 0x4801501C) Message Object Control Register */ - }; -} CAN_MO_TypeDef; - -/* ================================================================================ */ -/* ================ VADC ================ */ -/* ================================================================================ */ - -/** - * @brief Analog to Digital Converter (VADC) - */ - -typedef struct { /*!< (@ 0x40004000) VADC Structure */ - __IO uint32_t CLC; /*!< (@ 0x40004000) Clock Control Register */ - __I uint32_t RESERVED; - __I uint32_t ID; /*!< (@ 0x40004008) Module Identification Register */ - __I uint32_t RESERVED1[7]; - __IO uint32_t OCS; /*!< (@ 0x40004028) OCDS Control and Status Register */ - __I uint32_t RESERVED2[21]; - __IO uint32_t GLOBCFG; /*!< (@ 0x40004080) Global Configuration Register */ - __I uint32_t RESERVED3[7]; - __IO uint32_t GLOBICLASS[2]; /*!< (@ 0x400040A0) Input Class Register, Global */ - __I uint32_t RESERVED4[4]; - __IO uint32_t GLOBBOUND; /*!< (@ 0x400040B8) Global Boundary Select Register */ - __I uint32_t RESERVED5[9]; - __IO uint32_t GLOBEFLAG; /*!< (@ 0x400040E0) Global Event Flag Register */ - __I uint32_t RESERVED6[23]; - __IO uint32_t GLOBEVNP; /*!< (@ 0x40004140) Global Event Node Pointer Register */ - __I uint32_t RESERVED7[7]; - __IO uint32_t GLOBTF; /*!< (@ 0x40004160) Global Test Functions Register */ - __I uint32_t RESERVED8[7]; - __IO uint32_t - BRSSEL[4]; /*!< (@ 0x40004180) Background Request Source Channel Select Register */ - __I uint32_t RESERVED9[12]; - __IO uint32_t BRSPND[4]; /*!< (@ 0x400041C0) Background Request Source Pending Register */ - __I uint32_t RESERVED10[12]; - __IO uint32_t BRSCTRL; /*!< (@ 0x40004200) Background Request Source Control Register */ - __IO uint32_t BRSMR; /*!< (@ 0x40004204) Background Request Source Mode Register */ - __I uint32_t RESERVED11[30]; - __IO uint32_t GLOBRCR; /*!< (@ 0x40004280) Global Result Control Register */ - __I uint32_t RESERVED12[31]; - __IO uint32_t GLOBRES; /*!< (@ 0x40004300) Global Result Register */ - __I uint32_t RESERVED13[31]; - __IO uint32_t GLOBRESD; /*!< (@ 0x40004380) Global Result Register, Debug */ - __I uint32_t RESERVED14[27]; - __IO uint32_t EMUXSEL; /*!< (@ 0x400043F0) External Multiplexer Select Register */ -} VADC_GLOBAL_TypeDef; - -/* ================================================================================ */ -/* ================ VADC_G [VADC_G0] ================ */ -/* ================================================================================ */ - -/** - * @brief Analog to Digital Converter (VADC_G) - */ - -typedef struct { /*!< (@ 0x40004400) VADC_G Structure */ - __I uint32_t RESERVED[32]; - __IO uint32_t ARBCFG; /*!< (@ 0x40004480) Arbitration Configuration Register */ - __IO uint32_t ARBPR; /*!< (@ 0x40004484) Arbitration Priority Register */ - __IO uint32_t CHASS; /*!< (@ 0x40004488) Channel Assignment Register */ - __I uint32_t RESERVED1[5]; - __IO uint32_t ICLASS[2]; /*!< (@ 0x400044A0) Input Class Register */ - __I uint32_t RESERVED2[2]; - __IO uint32_t ALIAS; /*!< (@ 0x400044B0) Alias Register */ - __I uint32_t RESERVED3; - __IO uint32_t BOUND; /*!< (@ 0x400044B8) Boundary Select Register */ - __I uint32_t RESERVED4; - __IO uint32_t SYNCTR; /*!< (@ 0x400044C0) Synchronization Control Register */ - __I uint32_t RESERVED5; - __IO uint32_t BFL; /*!< (@ 0x400044C8) Boundary Flag Register */ - __O uint32_t BFLS; /*!< (@ 0x400044CC) Boundary Flag Software Register */ - __IO uint32_t BFLC; /*!< (@ 0x400044D0) Boundary Flag Control Register */ - __IO uint32_t BFLNP; /*!< (@ 0x400044D4) Boundary Flag Node Pointer Register */ - __I uint32_t RESERVED6[10]; - __IO uint32_t QCTRL0; /*!< (@ 0x40004500) Queue 0 Source Control Register */ - __IO uint32_t QMR0; /*!< (@ 0x40004504) Queue 0 Mode Register */ - __I uint32_t QSR0; /*!< (@ 0x40004508) Queue 0 Status Register */ - __I uint32_t Q0R0; /*!< (@ 0x4000450C) Queue 0 Register 0 */ - - union { - __I uint32_t QBUR0; /*!< (@ 0x40004510) Queue 0 Backup Register */ - __O uint32_t QINR0; /*!< (@ 0x40004510) Queue 0 Input Register */ - }; - - __I uint32_t RESERVED7[3]; - __IO uint32_t ASCTRL; /*!< (@ 0x40004520) Autoscan Source Control Register */ - __IO uint32_t ASMR; /*!< (@ 0x40004524) Autoscan Source Mode Register */ - __IO uint32_t ASSEL; /*!< (@ 0x40004528) Autoscan Source Channel Select Register */ - __IO uint32_t ASPND; /*!< (@ 0x4000452C) Autoscan Source Pending Register */ - __I uint32_t RESERVED8[20]; - __IO uint32_t CEFLAG; /*!< (@ 0x40004580) Channel Event Flag Register */ - __IO uint32_t REFLAG; /*!< (@ 0x40004584) Result Event Flag Register */ - __IO uint32_t SEFLAG; /*!< (@ 0x40004588) Source Event Flag Register */ - __I uint32_t RESERVED9; - __O uint32_t CEFCLR; /*!< (@ 0x40004590) Channel Event Flag Clear Register */ - __O uint32_t REFCLR; /*!< (@ 0x40004594) Result Event Flag Clear Register */ - __O uint32_t SEFCLR; /*!< (@ 0x40004598) Source Event Flag Clear Register */ - __I uint32_t RESERVED10; - __IO uint32_t CEVNP0; /*!< (@ 0x400045A0) Channel Event Node Pointer Register 0 */ - __I uint32_t RESERVED11[3]; - __IO uint32_t REVNP0; /*!< (@ 0x400045B0) Result Event Node Pointer Register 0 */ - __IO uint32_t REVNP1; /*!< (@ 0x400045B4) Result Event Node Pointer Register 1 */ - __I uint32_t RESERVED12[2]; - __IO uint32_t SEVNP; /*!< (@ 0x400045C0) Source Event Node Pointer Register */ - __I uint32_t RESERVED13; - __O uint32_t SRACT; /*!< (@ 0x400045C8) Service Request Software Activation Trigger */ - __I uint32_t RESERVED14[9]; - __IO uint32_t EMUXCTR; /*!< (@ 0x400045F0) E0ternal Multiplexer Control Register */ - __I uint32_t RESERVED15; - __IO uint32_t VFR; /*!< (@ 0x400045F8) Valid Flag Register */ - __I uint32_t RESERVED16; - __IO uint32_t CHCTR[8]; /*!< (@ 0x40004600) Channel Ctrl. Reg. */ - __I uint32_t RESERVED17[24]; - __IO uint32_t RCR[16]; /*!< (@ 0x40004680) Result Control Register */ - __I uint32_t RESERVED18[16]; - __IO uint32_t RES[16]; /*!< (@ 0x40004700) Result Register */ - __I uint32_t RESERVED19[16]; - __I uint32_t RESD[16]; /*!< (@ 0x40004780) Result Register, Debug */ -} VADC_G_TypeDef; - -/* ================================================================================ */ -/* ================ DSD ================ */ -/* ================================================================================ */ - -/** - * @brief Delta Sigma Demodulator (DSD) - */ - -typedef struct { /*!< (@ 0x40008000) DSD Structure */ - __IO uint32_t CLC; /*!< (@ 0x40008000) Clock Control Register */ - __I uint32_t RESERVED; - __I uint32_t ID; /*!< (@ 0x40008008) Module Identification Register */ - __I uint32_t RESERVED1[7]; - __IO uint32_t OCS; /*!< (@ 0x40008028) OCDS Control and Status Register */ - __I uint32_t RESERVED2[21]; - __IO uint32_t GLOBCFG; /*!< (@ 0x40008080) Global Configuration Register */ - __I uint32_t RESERVED3; - __IO uint32_t GLOBRC; /*!< (@ 0x40008088) Global Run Control Register */ - __I uint32_t RESERVED4[5]; - __IO uint32_t CGCFG; /*!< (@ 0x400080A0) Carrier Generator Configuration Register */ - __I uint32_t RESERVED5[15]; - __IO uint32_t EVFLAG; /*!< (@ 0x400080E0) Event Flag Register */ - __O uint32_t EVFLAGCLR; /*!< (@ 0x400080E4) Event Flag Clear Register */ -} DSD_GLOBAL_TypeDef; - -/* ================================================================================ */ -/* ================ DSD_CH [DSD_CH0] ================ */ -/* ================================================================================ */ - -/** - * @brief Delta Sigma Demodulator (DSD_CH) - */ - -typedef struct { /*!< (@ 0x40008100) DSD_CH Structure */ - __IO uint32_t MODCFG; /*!< (@ 0x40008100) Modulator Configuration Register */ - __I uint32_t RESERVED; - __IO uint32_t DICFG; /*!< (@ 0x40008108) Demodulator Input Configuration Register */ - __I uint32_t RESERVED1[2]; - __IO uint32_t FCFGC; /*!< (@ 0x40008114) Filter Configuration Register, Main CIC Filter */ - __IO uint32_t FCFGA; /*!< (@ 0x40008118) Filter Configuration Register, Auxiliary Filter */ - __I uint32_t RESERVED2; - __IO uint32_t IWCTR; /*!< (@ 0x40008120) Integration Window Control Register */ - __I uint32_t RESERVED3; - __IO uint32_t BOUNDSEL; /*!< (@ 0x40008128) Boundary Select Register */ - __I uint32_t RESERVED4; - __I uint32_t RESM; /*!< (@ 0x40008130) Result Register, Main Filter */ - __I uint32_t RESERVED5; - __IO uint32_t OFFM; /*!< (@ 0x40008138) Offset Register, Main Filter */ - __I uint32_t RESERVED6; - __I uint32_t RESA; /*!< (@ 0x40008140) Result Register, Auxiliary Filter */ - __I uint32_t RESERVED7[3]; - __I uint32_t TSTMP; /*!< (@ 0x40008150) Time-Stamp Register */ - __I uint32_t RESERVED8[19]; - __IO uint32_t CGSYNC; /*!< (@ 0x400081A0) Carrier Generator Synchronization Register */ - __I uint32_t RESERVED9; - __IO uint32_t RECTCFG; /*!< (@ 0x400081A8) Rectification Configuration Register */ -} DSD_CH_TypeDef; - -/* ================================================================================ */ -/* ================ DAC ================ */ -/* ================================================================================ */ - -/** - * @brief Digital to Analog Converter (DAC) - */ - -typedef struct { /*!< (@ 0x48018000) DAC Structure */ - __I uint32_t ID; /*!< (@ 0x48018000) Module Identification Register */ - __IO uint32_t DAC0CFG0; /*!< (@ 0x48018004) DAC0 Configuration Register 0 */ - __IO uint32_t DAC0CFG1; /*!< (@ 0x48018008) DAC0 Configuration Register 1 */ - __IO uint32_t DAC1CFG0; /*!< (@ 0x4801800C) DAC1 Configuration Register 0 */ - __IO uint32_t DAC1CFG1; /*!< (@ 0x48018010) DAC1 Configuration Register 1 */ - __IO uint32_t DAC0DATA; /*!< (@ 0x48018014) DAC0 Data Register */ - __IO uint32_t DAC1DATA; /*!< (@ 0x48018018) DAC1 Data Register */ - __IO uint32_t DAC01DATA; /*!< (@ 0x4801801C) DAC01 Data Register */ - __IO uint32_t DAC0PATL; /*!< (@ 0x48018020) DAC0 Lower Pattern Register */ - __IO uint32_t DAC0PATH; /*!< (@ 0x48018024) DAC0 Higher Pattern Register */ - __IO uint32_t DAC1PATL; /*!< (@ 0x48018028) DAC1 Lower Pattern Register */ - __IO uint32_t DAC1PATH; /*!< (@ 0x4801802C) DAC1 Higher Pattern Register */ -} DAC_GLOBAL_TypeDef; - -/* ================================================================================ */ -/* ================ CCU4 [CCU40] ================ */ -/* ================================================================================ */ - -/** - * @brief Capture Compare Unit 4 - Unit 0 (CCU4) - */ - -typedef struct { /*!< (@ 0x4000C000) CCU4 Structure */ - __IO uint32_t GCTRL; /*!< (@ 0x4000C000) Global Control Register */ - __I uint32_t GSTAT; /*!< (@ 0x4000C004) Global Status Register */ - __O uint32_t GIDLS; /*!< (@ 0x4000C008) Global Idle Set */ - __O uint32_t GIDLC; /*!< (@ 0x4000C00C) Global Idle Clear */ - __O uint32_t GCSS; /*!< (@ 0x4000C010) Global Channel Set */ - __O uint32_t GCSC; /*!< (@ 0x4000C014) Global Channel Clear */ - __I uint32_t GCST; /*!< (@ 0x4000C018) Global Channel Status */ - __I uint32_t RESERVED[13]; - __I uint32_t ECRD; /*!< (@ 0x4000C050) Extended Capture Mode Read */ - __I uint32_t RESERVED1[11]; - __I uint32_t MIDR; /*!< (@ 0x4000C080) Module Identification */ -} CCU4_GLOBAL_TypeDef; - -/* ================================================================================ */ -/* ================ CCU4_CC4 [CCU40_CC40] ================ */ -/* ================================================================================ */ - -/** - * @brief Capture Compare Unit 4 - Unit 0 (CCU4_CC4) - */ - -typedef struct { /*!< (@ 0x4000C100) CCU4_CC4 Structure */ - __IO uint32_t INS; /*!< (@ 0x4000C100) Input Selector Configuration */ - __IO uint32_t CMC; /*!< (@ 0x4000C104) Connection Matrix Control */ - __I uint32_t TCST; /*!< (@ 0x4000C108) Slice Timer Status */ - __O uint32_t TCSET; /*!< (@ 0x4000C10C) Slice Timer Run Set */ - __O uint32_t TCCLR; /*!< (@ 0x4000C110) Slice Timer Clear */ - __IO uint32_t TC; /*!< (@ 0x4000C114) Slice Timer Control */ - __IO uint32_t PSL; /*!< (@ 0x4000C118) Passive Level Config */ - __I uint32_t DIT; /*!< (@ 0x4000C11C) Dither Config */ - __IO uint32_t DITS; /*!< (@ 0x4000C120) Dither Shadow Register */ - __IO uint32_t PSC; /*!< (@ 0x4000C124) Prescaler Control */ - __IO uint32_t FPC; /*!< (@ 0x4000C128) Floating Prescaler Control */ - __IO uint32_t FPCS; /*!< (@ 0x4000C12C) Floating Prescaler Shadow */ - __I uint32_t PR; /*!< (@ 0x4000C130) Timer Period Value */ - __IO uint32_t PRS; /*!< (@ 0x4000C134) Timer Shadow Period Value */ - __I uint32_t CR; /*!< (@ 0x4000C138) Timer Compare Value */ - __IO uint32_t CRS; /*!< (@ 0x4000C13C) Timer Shadow Compare Value */ - __I uint32_t RESERVED[12]; - __IO uint32_t TIMER; /*!< (@ 0x4000C170) Timer Value */ - __I uint32_t CV[4]; /*!< (@ 0x4000C174) Capture Register 0 */ - __I uint32_t RESERVED1[7]; - __I uint32_t INTS; /*!< (@ 0x4000C1A0) Interrupt Status */ - __IO uint32_t INTE; /*!< (@ 0x4000C1A4) Interrupt Enable Control */ - __IO uint32_t SRS; /*!< (@ 0x4000C1A8) Service Request Selector */ - __O uint32_t SWS; /*!< (@ 0x4000C1AC) Interrupt Status Set */ - __O uint32_t SWR; /*!< (@ 0x4000C1B0) Interrupt Status Clear */ -} CCU4_CC4_TypeDef; - -/* ================================================================================ */ -/* ================ CCU8 [CCU80] ================ */ -/* ================================================================================ */ - -/** - * @brief Capture Compare Unit 8 - Unit 0 (CCU8) - */ - -typedef struct { /*!< (@ 0x40020000) CCU8 Structure */ - __IO uint32_t GCTRL; /*!< (@ 0x40020000) Global Control Register */ - __I uint32_t GSTAT; /*!< (@ 0x40020004) Global Status Register */ - __O uint32_t GIDLS; /*!< (@ 0x40020008) Global Idle Set */ - __O uint32_t GIDLC; /*!< (@ 0x4002000C) Global Idle Clear */ - __O uint32_t GCSS; /*!< (@ 0x40020010) Global Channel Set */ - __O uint32_t GCSC; /*!< (@ 0x40020014) Global Channel Clear */ - __I uint32_t GCST; /*!< (@ 0x40020018) Global Channel status */ - __IO uint32_t GPCHK; /*!< (@ 0x4002001C) Parity Checker Configuration */ - __I uint32_t RESERVED[12]; - __I uint32_t ECRD; /*!< (@ 0x40020050) Extended Capture Mode Read */ - __I uint32_t RESERVED1[11]; - __I uint32_t MIDR; /*!< (@ 0x40020080) Module Identification */ -} CCU8_GLOBAL_TypeDef; - -/* ================================================================================ */ -/* ================ CCU8_CC8 [CCU80_CC80] ================ */ -/* ================================================================================ */ - -/** - * @brief Capture Compare Unit 8 - Unit 0 (CCU8_CC8) - */ - -typedef struct { /*!< (@ 0x40020100) CCU8_CC8 Structure */ - __IO uint32_t INS; /*!< (@ 0x40020100) Input Selector Configuration */ - __IO uint32_t CMC; /*!< (@ 0x40020104) Connection Matrix Control */ - __I uint32_t TCST; /*!< (@ 0x40020108) Slice Timer Status */ - __O uint32_t TCSET; /*!< (@ 0x4002010C) Slice Timer Run Set */ - __O uint32_t TCCLR; /*!< (@ 0x40020110) Slice Timer Clear */ - __IO uint32_t TC; /*!< (@ 0x40020114) Slice Timer Control */ - __IO uint32_t PSL; /*!< (@ 0x40020118) Passive Level Config */ - __I uint32_t DIT; /*!< (@ 0x4002011C) Dither Config */ - __IO uint32_t DITS; /*!< (@ 0x40020120) Dither Shadow Register */ - __IO uint32_t PSC; /*!< (@ 0x40020124) Prescaler Control */ - __IO uint32_t FPC; /*!< (@ 0x40020128) Floating Prescaler Control */ - __IO uint32_t FPCS; /*!< (@ 0x4002012C) Floating Prescaler Shadow */ - __I uint32_t PR; /*!< (@ 0x40020130) Timer Period Value */ - __IO uint32_t PRS; /*!< (@ 0x40020134) Timer Shadow Period Value */ - __I uint32_t CR1; /*!< (@ 0x40020138) Channel 1 Compare Value */ - __IO uint32_t CR1S; /*!< (@ 0x4002013C) Channel 1 Compare Shadow Value */ - __I uint32_t CR2; /*!< (@ 0x40020140) Channel 2 Compare Value */ - __IO uint32_t CR2S; /*!< (@ 0x40020144) Channel 2 Compare Shadow Value */ - __IO uint32_t CHC; /*!< (@ 0x40020148) Channel Control */ - __IO uint32_t DTC; /*!< (@ 0x4002014C) Dead Time Control */ - __IO uint32_t DC1R; /*!< (@ 0x40020150) Channel 1 Dead Time Values */ - __IO uint32_t DC2R; /*!< (@ 0x40020154) Channel 2 Dead Time Values */ - __I uint32_t RESERVED[6]; - __IO uint32_t TIMER; /*!< (@ 0x40020170) Timer Value */ - __I uint32_t CV[4]; /*!< (@ 0x40020174) Capture Register 0 */ - __I uint32_t RESERVED1[7]; - __I uint32_t INTS; /*!< (@ 0x400201A0) Interrupt Status */ - __IO uint32_t INTE; /*!< (@ 0x400201A4) Interrupt Enable Control */ - __IO uint32_t SRS; /*!< (@ 0x400201A8) Service Request Selector */ - __O uint32_t SWS; /*!< (@ 0x400201AC) Interrupt Status Set */ - __O uint32_t SWR; /*!< (@ 0x400201B0) Interrupt Status Clear */ - __IO uint32_t STC; /*!< (@ 0x400201B4) Shadow transfer control */ -} CCU8_CC8_TypeDef; - -/* ================================================================================ */ -/* ================ HRPWM0 ================ */ -/* ================================================================================ */ - -/** - * @brief High Resolution PWM Unit (HRPWM0) - */ - -typedef struct { /*!< (@ 0x40020900) HRPWM0 Structure */ - __IO uint32_t HRBSC; /*!< (@ 0x40020900) Bias and suspend configuration */ - __I uint32_t RESERVED; - __I uint32_t MIDR; /*!< (@ 0x40020908) Module identification register */ - __I uint32_t RESERVED1[2]; - __IO uint32_t GLBANA; /*!< (@ 0x40020914) Global Analog Configuration */ - __I uint32_t RESERVED2[2]; - __IO uint32_t CSGCFG; /*!< (@ 0x40020920) Global CSG configuration */ - __O uint32_t CSGSETG; /*!< (@ 0x40020924) Global CSG run bit set */ - __O uint32_t CSGCLRG; /*!< (@ 0x40020928) Global CSG run bit clear */ - __I uint32_t CSGSTATG; /*!< (@ 0x4002092C) Global CSG run bit status */ - __O uint32_t CSGFCG; /*!< (@ 0x40020930) Global CSG slope/prescaler control */ - __I uint32_t CSGFSG; /*!< (@ 0x40020934) Global CSG slope/prescaler status */ - __O uint32_t CSGTRG; /*!< (@ 0x40020938) Global CSG shadow/switch trigger */ - __O uint32_t CSGTRC; /*!< (@ 0x4002093C) Global CSG shadow trigger clear */ - __I uint32_t CSGTRSG; /*!< (@ 0x40020940) Global CSG shadow/switch status */ - __I uint32_t RESERVED3[7]; - __IO uint32_t HRCCFG; /*!< (@ 0x40020960) Global HRC configuration */ - __O uint32_t HRCSTRG; /*!< (@ 0x40020964) Global HRC shadow trigger set */ - __O uint32_t HRCCTRG; /*!< (@ 0x40020968) Global HRC shadow trigger clear */ - __I uint32_t HRCSTSG; /*!< (@ 0x4002096C) Global HRC shadow transfer status */ - __I uint32_t HRGHRS; /*!< (@ 0x40020970) High Resolution Generation Status */ -} HRPWM0_Type; - -/* ================================================================================ */ -/* ================ HRPWM0_CSG [HRPWM0_CSG0] ================ */ -/* ================================================================================ */ - -/** - * @brief High Resolution PWM Unit (HRPWM0_CSG) - */ - -typedef struct { /*!< (@ 0x40020A00) HRPWM0_CSG Structure */ - __IO uint32_t DCI; /*!< (@ 0x40020A00) External input selection */ - __IO uint32_t IES; /*!< (@ 0x40020A04) External input selection */ - __IO uint32_t SC; /*!< (@ 0x40020A08) Slope generation control */ - __I uint32_t PC; /*!< (@ 0x40020A0C) Pulse swallow configuration */ - __I uint32_t DSV1; /*!< (@ 0x40020A10) DAC reference value 1 */ - __IO uint32_t DSV2; /*!< (@ 0x40020A14) DAC reference value 1 */ - __IO uint32_t SDSV1; /*!< (@ 0x40020A18) Shadow reference value 1 */ - __IO uint32_t SPC; /*!< (@ 0x40020A1C) Shadow Pulse swallow value */ - __IO uint32_t CC; /*!< (@ 0x40020A20) Comparator configuration */ - __IO uint32_t PLC; /*!< (@ 0x40020A24) Passive level configuration */ - __IO uint32_t BLV; /*!< (@ 0x40020A28) Comparator blanking value */ - __IO uint32_t SRE; /*!< (@ 0x40020A2C) Service request enable */ - __IO uint32_t SRS; /*!< (@ 0x40020A30) Service request line selector */ - __O uint32_t SWS; /*!< (@ 0x40020A34) Service request SW set */ - __O uint32_t SWC; /*!< (@ 0x40020A38) Service request SW clear */ - __I uint32_t ISTAT; /*!< (@ 0x40020A3C) Service request status */ -} HRPWM0_CSG_Type; - -/* ================================================================================ */ -/* ================ HRPWM0_HRC [HRPWM0_HRC0] ================ */ -/* ================================================================================ */ - -/** - * @brief High Resolution PWM Unit (HRPWM0_HRC) - */ - -typedef struct { /*!< (@ 0x40021300) HRPWM0_HRC Structure */ - __IO uint32_t GC; /*!< (@ 0x40021300) HRC mode configuration */ - __IO uint32_t PL; /*!< (@ 0x40021304) HRC output passive level */ - __IO uint32_t GSEL; /*!< (@ 0x40021308) HRC global control selection */ - __IO uint32_t TSEL; /*!< (@ 0x4002130C) HRC timer selection */ - __I uint32_t SC; /*!< (@ 0x40021310) HRC current source for shadow */ - __I uint32_t DCR; /*!< (@ 0x40021314) HRC dead time rising value */ - __I uint32_t DCF; /*!< (@ 0x40021318) HRC dead time falling value */ - __I uint32_t CR1; /*!< (@ 0x4002131C) HRC rising edge value */ - __I uint32_t CR2; /*!< (@ 0x40021320) HRC falling edge value */ - __IO uint32_t SSC; /*!< (@ 0x40021324) HRC next source for shadow */ - __IO uint32_t SDCR; /*!< (@ 0x40021328) HRC shadow dead time rising */ - __IO uint32_t SDCF; /*!< (@ 0x4002132C) HRC shadow dead time falling */ - __IO uint32_t SCR1; /*!< (@ 0x40021330) HRC shadow rising edge value */ - __IO uint32_t SCR2; /*!< (@ 0x40021334) HRC shadow falling edge value */ -} HRPWM0_HRC_Type; - -/* ================================================================================ */ -/* ================ POSIF [POSIF0] ================ */ -/* ================================================================================ */ - -/** - * @brief Position Interface 0 (POSIF) - */ - -typedef struct { /*!< (@ 0x40028000) POSIF Structure */ - __IO uint32_t PCONF; /*!< (@ 0x40028000) Service Request Processing configuration */ - __IO uint32_t PSUS; /*!< (@ 0x40028004) Service Request Processing Suspend Config */ - __O uint32_t PRUNS; /*!< (@ 0x40028008) Service Request Processing Run Bit Set */ - __O uint32_t PRUNC; /*!< (@ 0x4002800C) Service Request Processing Run Bit Clear */ - __I uint32_t PRUN; /*!< (@ 0x40028010) Service Request Processing Run Bit Status */ - __I uint32_t RESERVED[3]; - __I uint32_t MIDR; /*!< (@ 0x40028020) Module Identification register */ - __I uint32_t RESERVED1[3]; - __I uint32_t HALP; /*!< (@ 0x40028030) Hall Sensor Patterns */ - __IO uint32_t HALPS; /*!< (@ 0x40028034) Hall Sensor Shadow Patterns */ - __I uint32_t RESERVED2[2]; - __I uint32_t MCM; /*!< (@ 0x40028040) Multi-Channel Pattern */ - __IO uint32_t MCSM; /*!< (@ 0x40028044) Multi-Channel Shadow Pattern */ - __O uint32_t MCMS; /*!< (@ 0x40028048) Multi-Channel Pattern Control set */ - __O uint32_t MCMC; /*!< (@ 0x4002804C) Multi-Channel Pattern Control clear */ - __I uint32_t MCMF; /*!< (@ 0x40028050) Multi-Channel Pattern Control flag */ - __I uint32_t RESERVED3[3]; - __IO uint32_t QDC; /*!< (@ 0x40028060) Quadrature Decoder Control */ - __I uint32_t RESERVED4[3]; - __I uint32_t PFLG; /*!< (@ 0x40028070) Service Request Processing Interrupt Flags */ - __IO uint32_t PFLGE; /*!< (@ 0x40028074) Service Request Processing Interrupt Enable */ - __O uint32_t SPFLG; /*!< (@ 0x40028078) Service Request Processing Interrupt Set */ - __O uint32_t RPFLG; /*!< (@ 0x4002807C) Service Request Processing Interrupt Clear */ - __I uint32_t RESERVED5[32]; - __I uint32_t PDBG; /*!< (@ 0x40028100) POSIF Debug register */ -} POSIF_GLOBAL_TypeDef; - -/* ================================================================================ */ -/* ================ PORT0 ================ */ -/* ================================================================================ */ - -/** - * @brief Port 0 (PORT0) - */ - -typedef struct { /*!< (@ 0x48028000) PORT0 Structure */ - __IO uint32_t OUT; /*!< (@ 0x48028000) Port 0 Output Register */ - __O uint32_t OMR; /*!< (@ 0x48028004) Port 0 Output Modification Register */ - __I uint32_t RESERVED[2]; - __IO uint32_t IOCR0; /*!< (@ 0x48028010) Port 0 Input/Output Control Register 0 */ - __IO uint32_t IOCR4; /*!< (@ 0x48028014) Port 0 Input/Output Control Register 4 */ - __IO uint32_t IOCR8; /*!< (@ 0x48028018) Port 0 Input/Output Control Register 8 */ - __IO uint32_t IOCR12; /*!< (@ 0x4802801C) Port 0 Input/Output Control Register 12 */ - __I uint32_t RESERVED1; - __I uint32_t IN; /*!< (@ 0x48028024) Port 0 Input Register */ - __I uint32_t RESERVED2[6]; - __IO uint32_t PDR0; /*!< (@ 0x48028040) Port 0 Pad Driver Mode 0 Register */ - __IO uint32_t PDR1; /*!< (@ 0x48028044) Port 0 Pad Driver Mode 1 Register */ - __I uint32_t RESERVED3[6]; - __I uint32_t PDISC; /*!< (@ 0x48028060) Port 0 Pin Function Decision Control Register */ - __I uint32_t RESERVED4[3]; - __IO uint32_t PPS; /*!< (@ 0x48028070) Port 0 Pin Power Save Register */ - __IO uint32_t HWSEL; /*!< (@ 0x48028074) Port 0 Pin Hardware Select Register */ -} PORT0_Type; - -/* ================================================================================ */ -/* ================ PORT1 ================ */ -/* ================================================================================ */ - -/** - * @brief Port 1 (PORT1) - */ - -typedef struct { /*!< (@ 0x48028100) PORT1 Structure */ - __IO uint32_t OUT; /*!< (@ 0x48028100) Port 1 Output Register */ - __O uint32_t OMR; /*!< (@ 0x48028104) Port 1 Output Modification Register */ - __I uint32_t RESERVED[2]; - __IO uint32_t IOCR0; /*!< (@ 0x48028110) Port 1 Input/Output Control Register 0 */ - __IO uint32_t IOCR4; /*!< (@ 0x48028114) Port 1 Input/Output Control Register 4 */ - __IO uint32_t IOCR8; /*!< (@ 0x48028118) Port 1 Input/Output Control Register 8 */ - __IO uint32_t IOCR12; /*!< (@ 0x4802811C) Port 1 Input/Output Control Register 12 */ - __I uint32_t RESERVED1; - __I uint32_t IN; /*!< (@ 0x48028124) Port 1 Input Register */ - __I uint32_t RESERVED2[6]; - __IO uint32_t PDR0; /*!< (@ 0x48028140) Port 1 Pad Driver Mode 0 Register */ - __IO uint32_t PDR1; /*!< (@ 0x48028144) Port 1 Pad Driver Mode 1 Register */ - __I uint32_t RESERVED3[6]; - __I uint32_t PDISC; /*!< (@ 0x48028160) Port 1 Pin Function Decision Control Register */ - __I uint32_t RESERVED4[3]; - __IO uint32_t PPS; /*!< (@ 0x48028170) Port 1 Pin Power Save Register */ - __IO uint32_t HWSEL; /*!< (@ 0x48028174) Port 1 Pin Hardware Select Register */ -} PORT1_Type; - -/* ================================================================================ */ -/* ================ PORT2 ================ */ -/* ================================================================================ */ - -/** - * @brief Port 2 (PORT2) - */ - -typedef struct { /*!< (@ 0x48028200) PORT2 Structure */ - __IO uint32_t OUT; /*!< (@ 0x48028200) Port 2 Output Register */ - __O uint32_t OMR; /*!< (@ 0x48028204) Port 2 Output Modification Register */ - __I uint32_t RESERVED[2]; - __IO uint32_t IOCR0; /*!< (@ 0x48028210) Port 2 Input/Output Control Register 0 */ - __IO uint32_t IOCR4; /*!< (@ 0x48028214) Port 2 Input/Output Control Register 4 */ - __IO uint32_t IOCR8; /*!< (@ 0x48028218) Port 2 Input/Output Control Register 8 */ - __IO uint32_t IOCR12; /*!< (@ 0x4802821C) Port 2 Input/Output Control Register 12 */ - __I uint32_t RESERVED1; - __I uint32_t IN; /*!< (@ 0x48028224) Port 2 Input Register */ - __I uint32_t RESERVED2[6]; - __IO uint32_t PDR0; /*!< (@ 0x48028240) Port 2 Pad Driver Mode 0 Register */ - __IO uint32_t PDR1; /*!< (@ 0x48028244) Port 2 Pad Driver Mode 1 Register */ - __I uint32_t RESERVED3[6]; - __I uint32_t PDISC; /*!< (@ 0x48028260) Port 2 Pin Function Decision Control Register */ - __I uint32_t RESERVED4[3]; - __IO uint32_t PPS; /*!< (@ 0x48028270) Port 2 Pin Power Save Register */ - __IO uint32_t HWSEL; /*!< (@ 0x48028274) Port 2 Pin Hardware Select Register */ -} PORT2_Type; - -/* ================================================================================ */ -/* ================ PORT3 ================ */ -/* ================================================================================ */ - -/** - * @brief Port 3 (PORT3) - */ - -typedef struct { /*!< (@ 0x48028300) PORT3 Structure */ - __IO uint32_t OUT; /*!< (@ 0x48028300) Port 3 Output Register */ - __O uint32_t OMR; /*!< (@ 0x48028304) Port 3 Output Modification Register */ - __I uint32_t RESERVED[2]; - __IO uint32_t IOCR0; /*!< (@ 0x48028310) Port 3 Input/Output Control Register 0 */ - __IO uint32_t IOCR4; /*!< (@ 0x48028314) Port 3 Input/Output Control Register 4 */ - __I uint32_t RESERVED1[3]; - __I uint32_t IN; /*!< (@ 0x48028324) Port 3 Input Register */ - __I uint32_t RESERVED2[6]; - __IO uint32_t PDR0; /*!< (@ 0x48028340) Port 3 Pad Driver Mode 0 Register */ - __I uint32_t RESERVED3[7]; - __I uint32_t PDISC; /*!< (@ 0x48028360) Port 3 Pin Function Decision Control Register */ - __I uint32_t RESERVED4[3]; - __IO uint32_t PPS; /*!< (@ 0x48028370) Port 3 Pin Power Save Register */ - __IO uint32_t HWSEL; /*!< (@ 0x48028374) Port 3 Pin Hardware Select Register */ -} PORT3_Type; - -/* ================================================================================ */ -/* ================ PORT4 ================ */ -/* ================================================================================ */ - -/** - * @brief Port 4 (PORT4) - */ - -typedef struct { /*!< (@ 0x48028400) PORT4 Structure */ - __IO uint32_t OUT; /*!< (@ 0x48028400) Port 4 Output Register */ - __O uint32_t OMR; /*!< (@ 0x48028404) Port 4 Output Modification Register */ - __I uint32_t RESERVED[2]; - __IO uint32_t IOCR0; /*!< (@ 0x48028410) Port 4 Input/Output Control Register 0 */ - __I uint32_t RESERVED1[4]; - __I uint32_t IN; /*!< (@ 0x48028424) Port 4 Input Register */ - __I uint32_t RESERVED2[6]; - __IO uint32_t PDR0; /*!< (@ 0x48028440) Port 4 Pad Driver Mode 0 Register */ - __I uint32_t RESERVED3[7]; - __I uint32_t PDISC; /*!< (@ 0x48028460) Port 4 Pin Function Decision Control Register */ - __I uint32_t RESERVED4[3]; - __IO uint32_t PPS; /*!< (@ 0x48028470) Port 4 Pin Power Save Register */ - __IO uint32_t HWSEL; /*!< (@ 0x48028474) Port 4 Pin Hardware Select Register */ -} PORT4_Type; - -/* ================================================================================ */ -/* ================ PORT5 ================ */ -/* ================================================================================ */ - -/** - * @brief Port 5 (PORT5) - */ - -typedef struct { /*!< (@ 0x48028500) PORT5 Structure */ - __IO uint32_t OUT; /*!< (@ 0x48028500) Port 5 Output Register */ - __O uint32_t OMR; /*!< (@ 0x48028504) Port 5 Output Modification Register */ - __I uint32_t RESERVED[2]; - __IO uint32_t IOCR0; /*!< (@ 0x48028510) Port 5 Input/Output Control Register 0 */ - __IO uint32_t IOCR4; /*!< (@ 0x48028514) Port 5 Input/Output Control Register 4 */ - __I uint32_t RESERVED1[3]; - __I uint32_t IN; /*!< (@ 0x48028524) Port 5 Input Register */ - __I uint32_t RESERVED2[6]; - __IO uint32_t PDR0; /*!< (@ 0x48028540) Port 5 Pad Driver Mode 0 Register */ - __I uint32_t RESERVED3[7]; - __I uint32_t PDISC; /*!< (@ 0x48028560) Port 5 Pin Function Decision Control Register */ - __I uint32_t RESERVED4[3]; - __IO uint32_t PPS; /*!< (@ 0x48028570) Port 5 Pin Power Save Register */ - __IO uint32_t HWSEL; /*!< (@ 0x48028574) Port 5 Pin Hardware Select Register */ -} PORT5_Type; - -/* ================================================================================ */ -/* ================ PORT14 ================ */ -/* ================================================================================ */ - -/** - * @brief Port 14 (PORT14) - */ - -typedef struct { /*!< (@ 0x48028E00) PORT14 Structure */ - __IO uint32_t OUT; /*!< (@ 0x48028E00) Port 14 Output Register */ - __O uint32_t OMR; /*!< (@ 0x48028E04) Port 14 Output Modification Register */ - __I uint32_t RESERVED[2]; - __IO uint32_t IOCR0; /*!< (@ 0x48028E10) Port 14 Input/Output Control Register 0 */ - __IO uint32_t IOCR4; /*!< (@ 0x48028E14) Port 14 Input/Output Control Register 4 */ - __IO uint32_t IOCR8; /*!< (@ 0x48028E18) Port 14 Input/Output Control Register 8 */ - __IO uint32_t IOCR12; /*!< (@ 0x48028E1C) Port 14 Input/Output Control Register 12 */ - __I uint32_t RESERVED1; - __I uint32_t IN; /*!< (@ 0x48028E24) Port 14 Input Register */ - __I uint32_t RESERVED2[14]; - __IO uint32_t PDISC; /*!< (@ 0x48028E60) Port 14 Pin Function Decision Control Register */ - __I uint32_t RESERVED3[3]; - __IO uint32_t PPS; /*!< (@ 0x48028E70) Port 14 Pin Power Save Register */ - __IO uint32_t HWSEL; /*!< (@ 0x48028E74) Port 14 Pin Hardware Select Register */ -} PORT14_Type; - -/* ================================================================================ */ -/* ================ PORT15 ================ */ -/* ================================================================================ */ - -/** - * @brief Port 15 (PORT15) - */ - -typedef struct { /*!< (@ 0x48028F00) PORT15 Structure */ - __IO uint32_t OUT; /*!< (@ 0x48028F00) Port 15 Output Register */ - __O uint32_t OMR; /*!< (@ 0x48028F04) Port 15 Output Modification Register */ - __I uint32_t RESERVED[2]; - __IO uint32_t IOCR0; /*!< (@ 0x48028F10) Port 15 Input/Output Control Register 0 */ - __IO uint32_t IOCR4; /*!< (@ 0x48028F14) Port 15 Input/Output Control Register 4 */ - __IO uint32_t IOCR8; /*!< (@ 0x48028F18) Port 15 Input/Output Control Register 8 */ - __I uint32_t RESERVED1[2]; - __I uint32_t IN; /*!< (@ 0x48028F24) Port 15 Input Register */ - __I uint32_t RESERVED2[14]; - __IO uint32_t PDISC; /*!< (@ 0x48028F60) Port 15 Pin Function Decision Control Register */ - __I uint32_t RESERVED3[3]; - __IO uint32_t PPS; /*!< (@ 0x48028F70) Port 15 Pin Power Save Register */ - __IO uint32_t HWSEL; /*!< (@ 0x48028F74) Port 15 Pin Hardware Select Register */ -} PORT15_Type; - -/* -------------------- End of section using anonymous unions ------------------- */ -#if defined(__CC_ARM) - #pragma pop -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#elif defined(__ICCARM__) - /* leave anonymous unions enabled */ -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined(__TASKING__) - #pragma warning restore -#else - #warning Not supported compiler type -#endif - -/* ================================================================================ */ -/* ================ struct 'PPB' Position & Mask ================ */ -/* ================================================================================ */ - -/* ---------------------------------- PPB_ACTLR --------------------------------- */ -#define PPB_ACTLR_DISMCYCINT_Pos \ - (0UL) /*!< PPB ACTLR: DISMCYCINT (Bit 0) */ -#define PPB_ACTLR_DISMCYCINT_Msk \ - (0x1UL) /*!< PPB ACTLR: DISMCYCINT (Bitfield-Mask: 0x01) */ -#define PPB_ACTLR_DISDEFWBUF_Pos \ - (1UL) /*!< PPB ACTLR: DISDEFWBUF (Bit 1) */ -#define PPB_ACTLR_DISDEFWBUF_Msk \ - (0x2UL) /*!< PPB ACTLR: DISDEFWBUF (Bitfield-Mask: 0x01) */ -#define PPB_ACTLR_DISFOLD_Pos \ - (2UL) /*!< PPB ACTLR: DISFOLD (Bit 2) */ -#define PPB_ACTLR_DISFOLD_Msk \ - (0x4UL) /*!< PPB ACTLR: DISFOLD (Bitfield-Mask: 0x01) */ -#define PPB_ACTLR_DISFPCA_Pos \ - (8UL) /*!< PPB ACTLR: DISFPCA (Bit 8) */ -#define PPB_ACTLR_DISFPCA_Msk \ - (0x100UL) /*!< PPB ACTLR: DISFPCA (Bitfield-Mask: 0x01) */ -#define PPB_ACTLR_DISOOFP_Pos \ - (9UL) /*!< PPB ACTLR: DISOOFP (Bit 9) */ -#define PPB_ACTLR_DISOOFP_Msk \ - (0x200UL) /*!< PPB ACTLR: DISOOFP (Bitfield-Mask: 0x01) */ - -/* -------------------------------- PPB_SYST_CSR -------------------------------- */ -#define PPB_SYST_CSR_ENABLE_Pos \ - (0UL) /*!< PPB SYST_CSR: ENABLE (Bit 0) */ -#define PPB_SYST_CSR_ENABLE_Msk \ - (0x1UL) /*!< PPB SYST_CSR: ENABLE (Bitfield-Mask: 0x01) */ -#define PPB_SYST_CSR_TICKINT_Pos \ - (1UL) /*!< PPB SYST_CSR: TICKINT (Bit 1) */ -#define PPB_SYST_CSR_TICKINT_Msk \ - (0x2UL) /*!< PPB SYST_CSR: TICKINT (Bitfield-Mask: 0x01) */ -#define PPB_SYST_CSR_CLKSOURCE_Pos \ - (2UL) /*!< PPB SYST_CSR: CLKSOURCE (Bit 2) */ -#define PPB_SYST_CSR_CLKSOURCE_Msk \ - (0x4UL) /*!< PPB SYST_CSR: CLKSOURCE (Bitfield-Mask: 0x01) */ -#define PPB_SYST_CSR_COUNTFLAG_Pos \ - (16UL) /*!< PPB SYST_CSR: COUNTFLAG (Bit 16) */ -#define PPB_SYST_CSR_COUNTFLAG_Msk \ - (0x10000UL) /*!< PPB SYST_CSR: COUNTFLAG (Bitfield-Mask: 0x01) */ - -/* -------------------------------- PPB_SYST_RVR -------------------------------- */ -#define PPB_SYST_RVR_RELOAD_Pos \ - (0UL) /*!< PPB SYST_RVR: RELOAD (Bit 0) */ -#define PPB_SYST_RVR_RELOAD_Msk \ - (0xffffffUL) /*!< PPB SYST_RVR: RELOAD (Bitfield-Mask: 0xffffff) */ - -/* -------------------------------- PPB_SYST_CVR -------------------------------- */ -#define PPB_SYST_CVR_CURRENT_Pos \ - (0UL) /*!< PPB SYST_CVR: CURRENT (Bit 0) */ -#define PPB_SYST_CVR_CURRENT_Msk \ - (0xffffffUL) /*!< PPB SYST_CVR: CURRENT (Bitfield-Mask: 0xffffff) */ - -/* ------------------------------- PPB_SYST_CALIB ------------------------------- */ -#define PPB_SYST_CALIB_TENMS_Pos \ - (0UL) /*!< PPB SYST_CALIB: TENMS (Bit 0) */ -#define PPB_SYST_CALIB_TENMS_Msk \ - (0xffffffUL) /*!< PPB SYST_CALIB: TENMS (Bitfield-Mask: 0xffffff) */ -#define PPB_SYST_CALIB_SKEW_Pos \ - (30UL) /*!< PPB SYST_CALIB: SKEW (Bit 30) */ -#define PPB_SYST_CALIB_SKEW_Msk \ - (0x40000000UL) /*!< PPB SYST_CALIB: SKEW (Bitfield-Mask: 0x01) */ -#define PPB_SYST_CALIB_NOREF_Pos \ - (31UL) /*!< PPB SYST_CALIB: NOREF (Bit 31) */ -#define PPB_SYST_CALIB_NOREF_Msk \ - (0x80000000UL) /*!< PPB SYST_CALIB: NOREF (Bitfield-Mask: 0x01) */ - -/* ------------------------------- PPB_NVIC_ISER0 ------------------------------- */ -#define PPB_NVIC_ISER0_SETENA_Pos \ - (0UL) /*!< PPB NVIC_ISER0: SETENA (Bit 0) */ -#define PPB_NVIC_ISER0_SETENA_Msk \ - (0xffffffffUL) /*!< PPB NVIC_ISER0: SETENA (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------- PPB_NVIC_ISER1 ------------------------------- */ -#define PPB_NVIC_ISER1_SETENA_Pos \ - (0UL) /*!< PPB NVIC_ISER1: SETENA (Bit 0) */ -#define PPB_NVIC_ISER1_SETENA_Msk \ - (0xffffffffUL) /*!< PPB NVIC_ISER1: SETENA (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------- PPB_NVIC_ISER2 ------------------------------- */ -#define PPB_NVIC_ISER2_SETENA_Pos \ - (0UL) /*!< PPB NVIC_ISER2: SETENA (Bit 0) */ -#define PPB_NVIC_ISER2_SETENA_Msk \ - (0xffffffffUL) /*!< PPB NVIC_ISER2: SETENA (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------- PPB_NVIC_ISER3 ------------------------------- */ -#define PPB_NVIC_ISER3_SETENA_Pos \ - (0UL) /*!< PPB NVIC_ISER3: SETENA (Bit 0) */ -#define PPB_NVIC_ISER3_SETENA_Msk \ - (0xffffffffUL) /*!< PPB NVIC_ISER3: SETENA (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------- PPB_NVIC_ICER0 ------------------------------- */ -#define PPB_NVIC_ICER0_CLRENA_Pos \ - (0UL) /*!< PPB NVIC_ICER0: CLRENA (Bit 0) */ -#define PPB_NVIC_ICER0_CLRENA_Msk \ - (0xffffffffUL) /*!< PPB NVIC_ICER0: CLRENA (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------- PPB_NVIC_ICER1 ------------------------------- */ -#define PPB_NVIC_ICER1_CLRENA_Pos \ - (0UL) /*!< PPB NVIC_ICER1: CLRENA (Bit 0) */ -#define PPB_NVIC_ICER1_CLRENA_Msk \ - (0xffffffffUL) /*!< PPB NVIC_ICER1: CLRENA (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------- PPB_NVIC_ICER2 ------------------------------- */ -#define PPB_NVIC_ICER2_CLRENA_Pos \ - (0UL) /*!< PPB NVIC_ICER2: CLRENA (Bit 0) */ -#define PPB_NVIC_ICER2_CLRENA_Msk \ - (0xffffffffUL) /*!< PPB NVIC_ICER2: CLRENA (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------- PPB_NVIC_ICER3 ------------------------------- */ -#define PPB_NVIC_ICER3_CLRENA_Pos \ - (0UL) /*!< PPB NVIC_ICER3: CLRENA (Bit 0) */ -#define PPB_NVIC_ICER3_CLRENA_Msk \ - (0xffffffffUL) /*!< PPB NVIC_ICER3: CLRENA (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------- PPB_NVIC_ISPR0 ------------------------------- */ -#define PPB_NVIC_ISPR0_SETPEND_Pos \ - (0UL) /*!< PPB NVIC_ISPR0: SETPEND (Bit 0) */ -#define PPB_NVIC_ISPR0_SETPEND_Msk \ - (0xffffffffUL) /*!< PPB NVIC_ISPR0: SETPEND (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------- PPB_NVIC_ISPR1 ------------------------------- */ -#define PPB_NVIC_ISPR1_SETPEND_Pos \ - (0UL) /*!< PPB NVIC_ISPR1: SETPEND (Bit 0) */ -#define PPB_NVIC_ISPR1_SETPEND_Msk \ - (0xffffffffUL) /*!< PPB NVIC_ISPR1: SETPEND (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------- PPB_NVIC_ISPR2 ------------------------------- */ -#define PPB_NVIC_ISPR2_SETPEND_Pos \ - (0UL) /*!< PPB NVIC_ISPR2: SETPEND (Bit 0) */ -#define PPB_NVIC_ISPR2_SETPEND_Msk \ - (0xffffffffUL) /*!< PPB NVIC_ISPR2: SETPEND (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------- PPB_NVIC_ISPR3 ------------------------------- */ -#define PPB_NVIC_ISPR3_SETPEND_Pos \ - (0UL) /*!< PPB NVIC_ISPR3: SETPEND (Bit 0) */ -#define PPB_NVIC_ISPR3_SETPEND_Msk \ - (0xffffffffUL) /*!< PPB NVIC_ISPR3: SETPEND (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------- PPB_NVIC_ICPR0 ------------------------------- */ -#define PPB_NVIC_ICPR0_CLRPEND_Pos \ - (0UL) /*!< PPB NVIC_ICPR0: CLRPEND (Bit 0) */ -#define PPB_NVIC_ICPR0_CLRPEND_Msk \ - (0xffffffffUL) /*!< PPB NVIC_ICPR0: CLRPEND (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------- PPB_NVIC_ICPR1 ------------------------------- */ -#define PPB_NVIC_ICPR1_CLRPEND_Pos \ - (0UL) /*!< PPB NVIC_ICPR1: CLRPEND (Bit 0) */ -#define PPB_NVIC_ICPR1_CLRPEND_Msk \ - (0xffffffffUL) /*!< PPB NVIC_ICPR1: CLRPEND (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------- PPB_NVIC_ICPR2 ------------------------------- */ -#define PPB_NVIC_ICPR2_CLRPEND_Pos \ - (0UL) /*!< PPB NVIC_ICPR2: CLRPEND (Bit 0) */ -#define PPB_NVIC_ICPR2_CLRPEND_Msk \ - (0xffffffffUL) /*!< PPB NVIC_ICPR2: CLRPEND (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------- PPB_NVIC_ICPR3 ------------------------------- */ -#define PPB_NVIC_ICPR3_CLRPEND_Pos \ - (0UL) /*!< PPB NVIC_ICPR3: CLRPEND (Bit 0) */ -#define PPB_NVIC_ICPR3_CLRPEND_Msk \ - (0xffffffffUL) /*!< PPB NVIC_ICPR3: CLRPEND (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------- PPB_NVIC_IABR0 ------------------------------- */ -#define PPB_NVIC_IABR0_ACTIVE_Pos \ - (0UL) /*!< PPB NVIC_IABR0: ACTIVE (Bit 0) */ -#define PPB_NVIC_IABR0_ACTIVE_Msk \ - (0xffffffffUL) /*!< PPB NVIC_IABR0: ACTIVE (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------- PPB_NVIC_IABR1 ------------------------------- */ -#define PPB_NVIC_IABR1_ACTIVE_Pos \ - (0UL) /*!< PPB NVIC_IABR1: ACTIVE (Bit 0) */ -#define PPB_NVIC_IABR1_ACTIVE_Msk \ - (0xffffffffUL) /*!< PPB NVIC_IABR1: ACTIVE (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------- PPB_NVIC_IABR2 ------------------------------- */ -#define PPB_NVIC_IABR2_ACTIVE_Pos \ - (0UL) /*!< PPB NVIC_IABR2: ACTIVE (Bit 0) */ -#define PPB_NVIC_IABR2_ACTIVE_Msk \ - (0xffffffffUL) /*!< PPB NVIC_IABR2: ACTIVE (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------- PPB_NVIC_IABR3 ------------------------------- */ -#define PPB_NVIC_IABR3_ACTIVE_Pos \ - (0UL) /*!< PPB NVIC_IABR3: ACTIVE (Bit 0) */ -#define PPB_NVIC_IABR3_ACTIVE_Msk \ - (0xffffffffUL) /*!< PPB NVIC_IABR3: ACTIVE (Bitfield-Mask: 0xffffffff) */ - -/* -------------------------------- PPB_NVIC_IPR0 ------------------------------- */ -#define PPB_NVIC_IPR0_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR0: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR0_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR0: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR0_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR0: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR0_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR0: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR0_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR0: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR0_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR0: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR0_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR0: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR0_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR0: PRI_3 (Bitfield-Mask: 0xff) */ - -/* -------------------------------- PPB_NVIC_IPR1 ------------------------------- */ -#define PPB_NVIC_IPR1_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR1: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR1_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR1: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR1_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR1: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR1_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR1: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR1_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR1: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR1_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR1: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR1_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR1: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR1_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR1: PRI_3 (Bitfield-Mask: 0xff) */ - -/* -------------------------------- PPB_NVIC_IPR2 ------------------------------- */ -#define PPB_NVIC_IPR2_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR2: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR2_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR2: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR2_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR2: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR2_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR2: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR2_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR2: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR2_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR2: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR2_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR2: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR2_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR2: PRI_3 (Bitfield-Mask: 0xff) */ - -/* -------------------------------- PPB_NVIC_IPR3 ------------------------------- */ -#define PPB_NVIC_IPR3_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR3: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR3_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR3: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR3_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR3: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR3_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR3: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR3_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR3: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR3_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR3: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR3_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR3: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR3_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR3: PRI_3 (Bitfield-Mask: 0xff) */ - -/* -------------------------------- PPB_NVIC_IPR4 ------------------------------- */ -#define PPB_NVIC_IPR4_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR4: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR4_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR4: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR4_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR4: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR4_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR4: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR4_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR4: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR4_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR4: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR4_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR4: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR4_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR4: PRI_3 (Bitfield-Mask: 0xff) */ - -/* -------------------------------- PPB_NVIC_IPR5 ------------------------------- */ -#define PPB_NVIC_IPR5_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR5: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR5_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR5: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR5_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR5: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR5_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR5: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR5_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR5: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR5_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR5: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR5_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR5: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR5_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR5: PRI_3 (Bitfield-Mask: 0xff) */ - -/* -------------------------------- PPB_NVIC_IPR6 ------------------------------- */ -#define PPB_NVIC_IPR6_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR6: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR6_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR6: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR6_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR6: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR6_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR6: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR6_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR6: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR6_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR6: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR6_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR6: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR6_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR6: PRI_3 (Bitfield-Mask: 0xff) */ - -/* -------------------------------- PPB_NVIC_IPR7 ------------------------------- */ -#define PPB_NVIC_IPR7_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR7: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR7_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR7: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR7_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR7: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR7_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR7: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR7_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR7: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR7_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR7: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR7_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR7: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR7_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR7: PRI_3 (Bitfield-Mask: 0xff) */ - -/* -------------------------------- PPB_NVIC_IPR8 ------------------------------- */ -#define PPB_NVIC_IPR8_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR8: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR8_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR8: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR8_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR8: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR8_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR8: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR8_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR8: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR8_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR8: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR8_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR8: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR8_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR8: PRI_3 (Bitfield-Mask: 0xff) */ - -/* -------------------------------- PPB_NVIC_IPR9 ------------------------------- */ -#define PPB_NVIC_IPR9_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR9: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR9_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR9: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR9_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR9: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR9_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR9: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR9_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR9: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR9_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR9: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR9_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR9: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR9_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR9: PRI_3 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- PPB_NVIC_IPR10 ------------------------------- */ -#define PPB_NVIC_IPR10_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR10: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR10_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR10: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR10_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR10: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR10_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR10: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR10_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR10: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR10_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR10: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR10_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR10: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR10_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR10: PRI_3 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- PPB_NVIC_IPR11 ------------------------------- */ -#define PPB_NVIC_IPR11_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR11: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR11_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR11: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR11_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR11: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR11_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR11: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR11_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR11: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR11_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR11: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR11_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR11: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR11_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR11: PRI_3 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- PPB_NVIC_IPR12 ------------------------------- */ -#define PPB_NVIC_IPR12_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR12: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR12_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR12: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR12_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR12: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR12_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR12: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR12_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR12: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR12_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR12: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR12_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR12: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR12_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR12: PRI_3 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- PPB_NVIC_IPR13 ------------------------------- */ -#define PPB_NVIC_IPR13_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR13: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR13_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR13: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR13_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR13: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR13_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR13: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR13_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR13: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR13_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR13: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR13_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR13: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR13_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR13: PRI_3 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- PPB_NVIC_IPR14 ------------------------------- */ -#define PPB_NVIC_IPR14_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR14: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR14_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR14: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR14_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR14: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR14_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR14: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR14_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR14: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR14_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR14: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR14_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR14: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR14_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR14: PRI_3 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- PPB_NVIC_IPR15 ------------------------------- */ -#define PPB_NVIC_IPR15_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR15: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR15_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR15: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR15_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR15: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR15_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR15: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR15_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR15: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR15_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR15: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR15_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR15: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR15_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR15: PRI_3 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- PPB_NVIC_IPR16 ------------------------------- */ -#define PPB_NVIC_IPR16_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR16: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR16_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR16: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR16_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR16: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR16_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR16: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR16_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR16: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR16_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR16: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR16_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR16: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR16_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR16: PRI_3 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- PPB_NVIC_IPR17 ------------------------------- */ -#define PPB_NVIC_IPR17_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR17: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR17_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR17: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR17_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR17: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR17_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR17: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR17_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR17: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR17_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR17: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR17_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR17: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR17_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR17: PRI_3 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- PPB_NVIC_IPR18 ------------------------------- */ -#define PPB_NVIC_IPR18_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR18: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR18_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR18: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR18_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR18: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR18_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR18: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR18_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR18: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR18_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR18: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR18_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR18: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR18_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR18: PRI_3 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- PPB_NVIC_IPR19 ------------------------------- */ -#define PPB_NVIC_IPR19_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR19: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR19_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR19: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR19_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR19: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR19_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR19: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR19_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR19: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR19_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR19: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR19_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR19: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR19_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR19: PRI_3 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- PPB_NVIC_IPR20 ------------------------------- */ -#define PPB_NVIC_IPR20_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR20: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR20_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR20: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR20_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR20: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR20_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR20: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR20_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR20: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR20_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR20: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR20_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR20: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR20_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR20: PRI_3 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- PPB_NVIC_IPR21 ------------------------------- */ -#define PPB_NVIC_IPR21_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR21: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR21_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR21: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR21_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR21: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR21_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR21: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR21_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR21: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR21_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR21: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR21_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR21: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR21_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR21: PRI_3 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- PPB_NVIC_IPR22 ------------------------------- */ -#define PPB_NVIC_IPR22_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR22: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR22_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR22: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR22_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR22: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR22_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR22: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR22_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR22: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR22_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR22: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR22_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR22: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR22_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR22: PRI_3 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- PPB_NVIC_IPR23 ------------------------------- */ -#define PPB_NVIC_IPR23_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR23: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR23_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR23: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR23_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR23: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR23_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR23: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR23_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR23: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR23_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR23: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR23_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR23: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR23_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR23: PRI_3 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- PPB_NVIC_IPR24 ------------------------------- */ -#define PPB_NVIC_IPR24_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR24: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR24_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR24: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR24_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR24: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR24_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR24: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR24_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR24: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR24_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR24: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR24_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR24: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR24_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR24: PRI_3 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- PPB_NVIC_IPR25 ------------------------------- */ -#define PPB_NVIC_IPR25_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR25: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR25_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR25: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR25_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR25: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR25_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR25: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR25_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR25: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR25_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR25: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR25_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR25: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR25_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR25: PRI_3 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- PPB_NVIC_IPR26 ------------------------------- */ -#define PPB_NVIC_IPR26_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR26: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR26_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR26: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR26_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR26: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR26_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR26: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR26_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR26: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR26_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR26: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR26_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR26: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR26_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR26: PRI_3 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- PPB_NVIC_IPR27 ------------------------------- */ -#define PPB_NVIC_IPR27_PRI_0_Pos \ - (0UL) /*!< PPB NVIC_IPR27: PRI_0 (Bit 0) */ -#define PPB_NVIC_IPR27_PRI_0_Msk \ - (0xffUL) /*!< PPB NVIC_IPR27: PRI_0 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR27_PRI_1_Pos \ - (8UL) /*!< PPB NVIC_IPR27: PRI_1 (Bit 8) */ -#define PPB_NVIC_IPR27_PRI_1_Msk \ - (0xff00UL) /*!< PPB NVIC_IPR27: PRI_1 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR27_PRI_2_Pos \ - (16UL) /*!< PPB NVIC_IPR27: PRI_2 (Bit 16) */ -#define PPB_NVIC_IPR27_PRI_2_Msk \ - (0xff0000UL) /*!< PPB NVIC_IPR27: PRI_2 (Bitfield-Mask: 0xff) */ -#define PPB_NVIC_IPR27_PRI_3_Pos \ - (24UL) /*!< PPB NVIC_IPR27: PRI_3 (Bit 24) */ -#define PPB_NVIC_IPR27_PRI_3_Msk \ - (0xff000000UL) /*!< PPB NVIC_IPR27: PRI_3 (Bitfield-Mask: 0xff) */ - -/* ---------------------------------- PPB_CPUID --------------------------------- */ -#define PPB_CPUID_Revision_Pos \ - (0UL) /*!< PPB CPUID: Revision (Bit 0) */ -#define PPB_CPUID_Revision_Msk \ - (0xfUL) /*!< PPB CPUID: Revision (Bitfield-Mask: 0x0f) */ -#define PPB_CPUID_PartNo_Pos \ - (4UL) /*!< PPB CPUID: PartNo (Bit 4) */ -#define PPB_CPUID_PartNo_Msk \ - (0xfff0UL) /*!< PPB CPUID: PartNo (Bitfield-Mask: 0xfff) */ -#define PPB_CPUID_Constant_Pos \ - (16UL) /*!< PPB CPUID: Constant (Bit 16) */ -#define PPB_CPUID_Constant_Msk \ - (0xf0000UL) /*!< PPB CPUID: Constant (Bitfield-Mask: 0x0f) */ -#define PPB_CPUID_Variant_Pos \ - (20UL) /*!< PPB CPUID: Variant (Bit 20) */ -#define PPB_CPUID_Variant_Msk \ - (0xf00000UL) /*!< PPB CPUID: Variant (Bitfield-Mask: 0x0f) */ -#define PPB_CPUID_Implementer_Pos \ - (24UL) /*!< PPB CPUID: Implementer (Bit 24) */ -#define PPB_CPUID_Implementer_Msk \ - (0xff000000UL) /*!< PPB CPUID: Implementer (Bitfield-Mask: 0xff) */ - -/* ---------------------------------- PPB_ICSR ---------------------------------- */ -#define PPB_ICSR_VECTACTIVE_Pos \ - (0UL) /*!< PPB ICSR: VECTACTIVE (Bit 0) */ -#define PPB_ICSR_VECTACTIVE_Msk \ - (0x1ffUL) /*!< PPB ICSR: VECTACTIVE (Bitfield-Mask: 0x1ff) */ -#define PPB_ICSR_RETTOBASE_Pos \ - (11UL) /*!< PPB ICSR: RETTOBASE (Bit 11) */ -#define PPB_ICSR_RETTOBASE_Msk \ - (0x800UL) /*!< PPB ICSR: RETTOBASE (Bitfield-Mask: 0x01) */ -#define PPB_ICSR_VECTPENDING_Pos \ - (12UL) /*!< PPB ICSR: VECTPENDING (Bit 12) */ -#define PPB_ICSR_VECTPENDING_Msk \ - (0x3f000UL) /*!< PPB ICSR: VECTPENDING (Bitfield-Mask: 0x3f) */ -#define PPB_ICSR_ISRPENDING_Pos \ - (22UL) /*!< PPB ICSR: ISRPENDING (Bit 22) */ -#define PPB_ICSR_ISRPENDING_Msk \ - (0x400000UL) /*!< PPB ICSR: ISRPENDING (Bitfield-Mask: 0x01) */ -#define PPB_ICSR_PENDSTCLR_Pos \ - (25UL) /*!< PPB ICSR: PENDSTCLR (Bit 25) */ -#define PPB_ICSR_PENDSTCLR_Msk \ - (0x2000000UL) /*!< PPB ICSR: PENDSTCLR (Bitfield-Mask: 0x01) */ -#define PPB_ICSR_PENDSTSET_Pos \ - (26UL) /*!< PPB ICSR: PENDSTSET (Bit 26) */ -#define PPB_ICSR_PENDSTSET_Msk \ - (0x4000000UL) /*!< PPB ICSR: PENDSTSET (Bitfield-Mask: 0x01) */ -#define PPB_ICSR_PENDSVCLR_Pos \ - (27UL) /*!< PPB ICSR: PENDSVCLR (Bit 27) */ -#define PPB_ICSR_PENDSVCLR_Msk \ - (0x8000000UL) /*!< PPB ICSR: PENDSVCLR (Bitfield-Mask: 0x01) */ -#define PPB_ICSR_PENDSVSET_Pos \ - (28UL) /*!< PPB ICSR: PENDSVSET (Bit 28) */ -#define PPB_ICSR_PENDSVSET_Msk \ - (0x10000000UL) /*!< PPB ICSR: PENDSVSET (Bitfield-Mask: 0x01) */ -#define PPB_ICSR_NMIPENDSET_Pos \ - (31UL) /*!< PPB ICSR: NMIPENDSET (Bit 31) */ -#define PPB_ICSR_NMIPENDSET_Msk \ - (0x80000000UL) /*!< PPB ICSR: NMIPENDSET (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- PPB_VTOR ---------------------------------- */ -#define PPB_VTOR_TBLOFF_Pos \ - (10UL) /*!< PPB VTOR: TBLOFF (Bit 10) */ -#define PPB_VTOR_TBLOFF_Msk \ - (0xfffffc00UL) /*!< PPB VTOR: TBLOFF (Bitfield-Mask: 0x3fffff) */ - -/* ---------------------------------- PPB_AIRCR --------------------------------- */ -#define PPB_AIRCR_VECTRESET_Pos \ - (0UL) /*!< PPB AIRCR: VECTRESET (Bit 0) */ -#define PPB_AIRCR_VECTRESET_Msk \ - (0x1UL) /*!< PPB AIRCR: VECTRESET (Bitfield-Mask: 0x01) */ -#define PPB_AIRCR_VECTCLRACTIVE_Pos \ - (1UL) /*!< PPB AIRCR: VECTCLRACTIVE (Bit 1) */ -#define PPB_AIRCR_VECTCLRACTIVE_Msk \ - (0x2UL) /*!< PPB AIRCR: VECTCLRACTIVE (Bitfield-Mask: 0x01) */ -#define PPB_AIRCR_SYSRESETREQ_Pos \ - (2UL) /*!< PPB AIRCR: SYSRESETREQ (Bit 2) */ -#define PPB_AIRCR_SYSRESETREQ_Msk \ - (0x4UL) /*!< PPB AIRCR: SYSRESETREQ (Bitfield-Mask: 0x01) */ -#define PPB_AIRCR_PRIGROUP_Pos \ - (8UL) /*!< PPB AIRCR: PRIGROUP (Bit 8) */ -#define PPB_AIRCR_PRIGROUP_Msk \ - (0x700UL) /*!< PPB AIRCR: PRIGROUP (Bitfield-Mask: 0x07) */ -#define PPB_AIRCR_ENDIANNESS_Pos \ - (15UL) /*!< PPB AIRCR: ENDIANNESS (Bit 15) */ -#define PPB_AIRCR_ENDIANNESS_Msk \ - (0x8000UL) /*!< PPB AIRCR: ENDIANNESS (Bitfield-Mask: 0x01) */ -#define PPB_AIRCR_VECTKEY_Pos \ - (16UL) /*!< PPB AIRCR: VECTKEY (Bit 16) */ -#define PPB_AIRCR_VECTKEY_Msk \ - (0xffff0000UL) /*!< PPB AIRCR: VECTKEY (Bitfield-Mask: 0xffff) */ - -/* ----------------------------------- PPB_SCR ---------------------------------- */ -#define PPB_SCR_SLEEPONEXIT_Pos \ - (1UL) /*!< PPB SCR: SLEEPONEXIT (Bit 1) */ -#define PPB_SCR_SLEEPONEXIT_Msk \ - (0x2UL) /*!< PPB SCR: SLEEPONEXIT (Bitfield-Mask: 0x01) */ -#define PPB_SCR_SLEEPDEEP_Pos \ - (2UL) /*!< PPB SCR: SLEEPDEEP (Bit 2) */ -#define PPB_SCR_SLEEPDEEP_Msk \ - (0x4UL) /*!< PPB SCR: SLEEPDEEP (Bitfield-Mask: 0x01) */ -#define PPB_SCR_SEVONPEND_Pos \ - (4UL) /*!< PPB SCR: SEVONPEND (Bit 4) */ -#define PPB_SCR_SEVONPEND_Msk \ - (0x10UL) /*!< PPB SCR: SEVONPEND (Bitfield-Mask: 0x01) */ - -/* ----------------------------------- PPB_CCR ---------------------------------- */ -#define PPB_CCR_NONBASETHRDENA_Pos \ - (0UL) /*!< PPB CCR: NONBASETHRDENA (Bit 0) */ -#define PPB_CCR_NONBASETHRDENA_Msk \ - (0x1UL) /*!< PPB CCR: NONBASETHRDENA (Bitfield-Mask: 0x01) */ -#define PPB_CCR_USERSETMPEND_Pos \ - (1UL) /*!< PPB CCR: USERSETMPEND (Bit 1) */ -#define PPB_CCR_USERSETMPEND_Msk \ - (0x2UL) /*!< PPB CCR: USERSETMPEND (Bitfield-Mask: 0x01) */ -#define PPB_CCR_UNALIGN_TRP_Pos \ - (3UL) /*!< PPB CCR: UNALIGN_TRP (Bit 3) */ -#define PPB_CCR_UNALIGN_TRP_Msk \ - (0x8UL) /*!< PPB CCR: UNALIGN_TRP (Bitfield-Mask: 0x01) */ -#define PPB_CCR_DIV_0_TRP_Pos \ - (4UL) /*!< PPB CCR: DIV_0_TRP (Bit 4) */ -#define PPB_CCR_DIV_0_TRP_Msk \ - (0x10UL) /*!< PPB CCR: DIV_0_TRP (Bitfield-Mask: 0x01) */ -#define PPB_CCR_BFHFNMIGN_Pos \ - (8UL) /*!< PPB CCR: BFHFNMIGN (Bit 8) */ -#define PPB_CCR_BFHFNMIGN_Msk \ - (0x100UL) /*!< PPB CCR: BFHFNMIGN (Bitfield-Mask: 0x01) */ -#define PPB_CCR_STKALIGN_Pos \ - (9UL) /*!< PPB CCR: STKALIGN (Bit 9) */ -#define PPB_CCR_STKALIGN_Msk \ - (0x200UL) /*!< PPB CCR: STKALIGN (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- PPB_SHPR1 --------------------------------- */ -#define PPB_SHPR1_PRI_4_Pos \ - (0UL) /*!< PPB SHPR1: PRI_4 (Bit 0) */ -#define PPB_SHPR1_PRI_4_Msk \ - (0xffUL) /*!< PPB SHPR1: PRI_4 (Bitfield-Mask: 0xff) */ -#define PPB_SHPR1_PRI_5_Pos \ - (8UL) /*!< PPB SHPR1: PRI_5 (Bit 8) */ -#define PPB_SHPR1_PRI_5_Msk \ - (0xff00UL) /*!< PPB SHPR1: PRI_5 (Bitfield-Mask: 0xff) */ -#define PPB_SHPR1_PRI_6_Pos \ - (16UL) /*!< PPB SHPR1: PRI_6 (Bit 16) */ -#define PPB_SHPR1_PRI_6_Msk \ - (0xff0000UL) /*!< PPB SHPR1: PRI_6 (Bitfield-Mask: 0xff) */ - -/* ---------------------------------- PPB_SHPR2 --------------------------------- */ -#define PPB_SHPR2_PRI_11_Pos \ - (24UL) /*!< PPB SHPR2: PRI_11 (Bit 24) */ -#define PPB_SHPR2_PRI_11_Msk \ - (0xff000000UL) /*!< PPB SHPR2: PRI_11 (Bitfield-Mask: 0xff) */ - -/* ---------------------------------- PPB_SHPR3 --------------------------------- */ -#define PPB_SHPR3_PRI_14_Pos \ - (16UL) /*!< PPB SHPR3: PRI_14 (Bit 16) */ -#define PPB_SHPR3_PRI_14_Msk \ - (0xff0000UL) /*!< PPB SHPR3: PRI_14 (Bitfield-Mask: 0xff) */ -#define PPB_SHPR3_PRI_15_Pos \ - (24UL) /*!< PPB SHPR3: PRI_15 (Bit 24) */ -#define PPB_SHPR3_PRI_15_Msk \ - (0xff000000UL) /*!< PPB SHPR3: PRI_15 (Bitfield-Mask: 0xff) */ - -/* ---------------------------------- PPB_SHCSR --------------------------------- */ -#define PPB_SHCSR_MEMFAULTACT_Pos \ - (0UL) /*!< PPB SHCSR: MEMFAULTACT (Bit 0) */ -#define PPB_SHCSR_MEMFAULTACT_Msk \ - (0x1UL) /*!< PPB SHCSR: MEMFAULTACT (Bitfield-Mask: 0x01) */ -#define PPB_SHCSR_BUSFAULTACT_Pos \ - (1UL) /*!< PPB SHCSR: BUSFAULTACT (Bit 1) */ -#define PPB_SHCSR_BUSFAULTACT_Msk \ - (0x2UL) /*!< PPB SHCSR: BUSFAULTACT (Bitfield-Mask: 0x01) */ -#define PPB_SHCSR_USGFAULTACT_Pos \ - (3UL) /*!< PPB SHCSR: USGFAULTACT (Bit 3) */ -#define PPB_SHCSR_USGFAULTACT_Msk \ - (0x8UL) /*!< PPB SHCSR: USGFAULTACT (Bitfield-Mask: 0x01) */ -#define PPB_SHCSR_SVCALLACT_Pos \ - (7UL) /*!< PPB SHCSR: SVCALLACT (Bit 7) */ -#define PPB_SHCSR_SVCALLACT_Msk \ - (0x80UL) /*!< PPB SHCSR: SVCALLACT (Bitfield-Mask: 0x01) */ -#define PPB_SHCSR_MONITORACT_Pos \ - (8UL) /*!< PPB SHCSR: MONITORACT (Bit 8) */ -#define PPB_SHCSR_MONITORACT_Msk \ - (0x100UL) /*!< PPB SHCSR: MONITORACT (Bitfield-Mask: 0x01) */ -#define PPB_SHCSR_PENDSVACT_Pos \ - (10UL) /*!< PPB SHCSR: PENDSVACT (Bit 10) */ -#define PPB_SHCSR_PENDSVACT_Msk \ - (0x400UL) /*!< PPB SHCSR: PENDSVACT (Bitfield-Mask: 0x01) */ -#define PPB_SHCSR_SYSTICKACT_Pos \ - (11UL) /*!< PPB SHCSR: SYSTICKACT (Bit 11) */ -#define PPB_SHCSR_SYSTICKACT_Msk \ - (0x800UL) /*!< PPB SHCSR: SYSTICKACT (Bitfield-Mask: 0x01) */ -#define PPB_SHCSR_USGFAULTPENDED_Pos \ - (12UL) /*!< PPB SHCSR: USGFAULTPENDED (Bit 12) */ -#define PPB_SHCSR_USGFAULTPENDED_Msk \ - (0x1000UL) /*!< PPB SHCSR: USGFAULTPENDED (Bitfield-Mask: 0x01) */ -#define PPB_SHCSR_MEMFAULTPENDED_Pos \ - (13UL) /*!< PPB SHCSR: MEMFAULTPENDED (Bit 13) */ -#define PPB_SHCSR_MEMFAULTPENDED_Msk \ - (0x2000UL) /*!< PPB SHCSR: MEMFAULTPENDED (Bitfield-Mask: 0x01) */ -#define PPB_SHCSR_BUSFAULTPENDED_Pos \ - (14UL) /*!< PPB SHCSR: BUSFAULTPENDED (Bit 14) */ -#define PPB_SHCSR_BUSFAULTPENDED_Msk \ - (0x4000UL) /*!< PPB SHCSR: BUSFAULTPENDED (Bitfield-Mask: 0x01) */ -#define PPB_SHCSR_SVCALLPENDED_Pos \ - (15UL) /*!< PPB SHCSR: SVCALLPENDED (Bit 15) */ -#define PPB_SHCSR_SVCALLPENDED_Msk \ - (0x8000UL) /*!< PPB SHCSR: SVCALLPENDED (Bitfield-Mask: 0x01) */ -#define PPB_SHCSR_MEMFAULTENA_Pos \ - (16UL) /*!< PPB SHCSR: MEMFAULTENA (Bit 16) */ -#define PPB_SHCSR_MEMFAULTENA_Msk \ - (0x10000UL) /*!< PPB SHCSR: MEMFAULTENA (Bitfield-Mask: 0x01) */ -#define PPB_SHCSR_BUSFAULTENA_Pos \ - (17UL) /*!< PPB SHCSR: BUSFAULTENA (Bit 17) */ -#define PPB_SHCSR_BUSFAULTENA_Msk \ - (0x20000UL) /*!< PPB SHCSR: BUSFAULTENA (Bitfield-Mask: 0x01) */ -#define PPB_SHCSR_USGFAULTENA_Pos \ - (18UL) /*!< PPB SHCSR: USGFAULTENA (Bit 18) */ -#define PPB_SHCSR_USGFAULTENA_Msk \ - (0x40000UL) /*!< PPB SHCSR: USGFAULTENA (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- PPB_CFSR ---------------------------------- */ -#define PPB_CFSR_IACCVIOL_Pos \ - (0UL) /*!< PPB CFSR: IACCVIOL (Bit 0) */ -#define PPB_CFSR_IACCVIOL_Msk \ - (0x1UL) /*!< PPB CFSR: IACCVIOL (Bitfield-Mask: 0x01) */ -#define PPB_CFSR_DACCVIOL_Pos \ - (1UL) /*!< PPB CFSR: DACCVIOL (Bit 1) */ -#define PPB_CFSR_DACCVIOL_Msk \ - (0x2UL) /*!< PPB CFSR: DACCVIOL (Bitfield-Mask: 0x01) */ -#define PPB_CFSR_MUNSTKERR_Pos \ - (3UL) /*!< PPB CFSR: MUNSTKERR (Bit 3) */ -#define PPB_CFSR_MUNSTKERR_Msk \ - (0x8UL) /*!< PPB CFSR: MUNSTKERR (Bitfield-Mask: 0x01) */ -#define PPB_CFSR_MSTKERR_Pos \ - (4UL) /*!< PPB CFSR: MSTKERR (Bit 4) */ -#define PPB_CFSR_MSTKERR_Msk \ - (0x10UL) /*!< PPB CFSR: MSTKERR (Bitfield-Mask: 0x01) */ -#define PPB_CFSR_MLSPERR_Pos \ - (5UL) /*!< PPB CFSR: MLSPERR (Bit 5) */ -#define PPB_CFSR_MLSPERR_Msk \ - (0x20UL) /*!< PPB CFSR: MLSPERR (Bitfield-Mask: 0x01) */ -#define PPB_CFSR_MMARVALID_Pos \ - (7UL) /*!< PPB CFSR: MMARVALID (Bit 7) */ -#define PPB_CFSR_MMARVALID_Msk \ - (0x80UL) /*!< PPB CFSR: MMARVALID (Bitfield-Mask: 0x01) */ -#define PPB_CFSR_IBUSERR_Pos \ - (8UL) /*!< PPB CFSR: IBUSERR (Bit 8) */ -#define PPB_CFSR_IBUSERR_Msk \ - (0x100UL) /*!< PPB CFSR: IBUSERR (Bitfield-Mask: 0x01) */ -#define PPB_CFSR_PRECISERR_Pos \ - (9UL) /*!< PPB CFSR: PRECISERR (Bit 9) */ -#define PPB_CFSR_PRECISERR_Msk \ - (0x200UL) /*!< PPB CFSR: PRECISERR (Bitfield-Mask: 0x01) */ -#define PPB_CFSR_IMPRECISERR_Pos \ - (10UL) /*!< PPB CFSR: IMPRECISERR (Bit 10) */ -#define PPB_CFSR_IMPRECISERR_Msk \ - (0x400UL) /*!< PPB CFSR: IMPRECISERR (Bitfield-Mask: 0x01) */ -#define PPB_CFSR_UNSTKERR_Pos \ - (11UL) /*!< PPB CFSR: UNSTKERR (Bit 11) */ -#define PPB_CFSR_UNSTKERR_Msk \ - (0x800UL) /*!< PPB CFSR: UNSTKERR (Bitfield-Mask: 0x01) */ -#define PPB_CFSR_STKERR_Pos \ - (12UL) /*!< PPB CFSR: STKERR (Bit 12) */ -#define PPB_CFSR_STKERR_Msk \ - (0x1000UL) /*!< PPB CFSR: STKERR (Bitfield-Mask: 0x01) */ -#define PPB_CFSR_LSPERR_Pos \ - (13UL) /*!< PPB CFSR: LSPERR (Bit 13) */ -#define PPB_CFSR_LSPERR_Msk \ - (0x2000UL) /*!< PPB CFSR: LSPERR (Bitfield-Mask: 0x01) */ -#define PPB_CFSR_BFARVALID_Pos \ - (15UL) /*!< PPB CFSR: BFARVALID (Bit 15) */ -#define PPB_CFSR_BFARVALID_Msk \ - (0x8000UL) /*!< PPB CFSR: BFARVALID (Bitfield-Mask: 0x01) */ -#define PPB_CFSR_UNDEFINSTR_Pos \ - (16UL) /*!< PPB CFSR: UNDEFINSTR (Bit 16) */ -#define PPB_CFSR_UNDEFINSTR_Msk \ - (0x10000UL) /*!< PPB CFSR: UNDEFINSTR (Bitfield-Mask: 0x01) */ -#define PPB_CFSR_INVSTATE_Pos \ - (17UL) /*!< PPB CFSR: INVSTATE (Bit 17) */ -#define PPB_CFSR_INVSTATE_Msk \ - (0x20000UL) /*!< PPB CFSR: INVSTATE (Bitfield-Mask: 0x01) */ -#define PPB_CFSR_INVPC_Pos \ - (18UL) /*!< PPB CFSR: INVPC (Bit 18) */ -#define PPB_CFSR_INVPC_Msk \ - (0x40000UL) /*!< PPB CFSR: INVPC (Bitfield-Mask: 0x01) */ -#define PPB_CFSR_NOCP_Pos (19UL) /*!< PPB CFSR: NOCP (Bit 19) */ -#define PPB_CFSR_NOCP_Msk \ - (0x80000UL) /*!< PPB CFSR: NOCP (Bitfield-Mask: 0x01) */ -#define PPB_CFSR_UNALIGNED_Pos \ - (24UL) /*!< PPB CFSR: UNALIGNED (Bit 24) */ -#define PPB_CFSR_UNALIGNED_Msk \ - (0x1000000UL) /*!< PPB CFSR: UNALIGNED (Bitfield-Mask: 0x01) */ -#define PPB_CFSR_DIVBYZERO_Pos \ - (25UL) /*!< PPB CFSR: DIVBYZERO (Bit 25) */ -#define PPB_CFSR_DIVBYZERO_Msk \ - (0x2000000UL) /*!< PPB CFSR: DIVBYZERO (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- PPB_HFSR ---------------------------------- */ -#define PPB_HFSR_VECTTBL_Pos \ - (1UL) /*!< PPB HFSR: VECTTBL (Bit 1) */ -#define PPB_HFSR_VECTTBL_Msk \ - (0x2UL) /*!< PPB HFSR: VECTTBL (Bitfield-Mask: 0x01) */ -#define PPB_HFSR_FORCED_Pos \ - (30UL) /*!< PPB HFSR: FORCED (Bit 30) */ -#define PPB_HFSR_FORCED_Msk \ - (0x40000000UL) /*!< PPB HFSR: FORCED (Bitfield-Mask: 0x01) */ -#define PPB_HFSR_DEBUGEVT_Pos \ - (31UL) /*!< PPB HFSR: DEBUGEVT (Bit 31) */ -#define PPB_HFSR_DEBUGEVT_Msk \ - (0x80000000UL) /*!< PPB HFSR: DEBUGEVT (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- PPB_MMFAR --------------------------------- */ -#define PPB_MMFAR_ADDRESS_Pos \ - (0UL) /*!< PPB MMFAR: ADDRESS (Bit 0) */ -#define PPB_MMFAR_ADDRESS_Msk \ - (0xffffffffUL) /*!< PPB MMFAR: ADDRESS (Bitfield-Mask: 0xffffffff) */ - -/* ---------------------------------- PPB_BFAR ---------------------------------- */ -#define PPB_BFAR_ADDRESS_Pos \ - (0UL) /*!< PPB BFAR: ADDRESS (Bit 0) */ -#define PPB_BFAR_ADDRESS_Msk \ - (0xffffffffUL) /*!< PPB BFAR: ADDRESS (Bitfield-Mask: 0xffffffff) */ - -/* ---------------------------------- PPB_AFSR ---------------------------------- */ -#define PPB_AFSR_VALUE_Pos (0UL) /*!< PPB AFSR: VALUE (Bit 0) */ -#define PPB_AFSR_VALUE_Msk \ - (0xffffffffUL) /*!< PPB AFSR: VALUE (Bitfield-Mask: 0xffffffff) */ - -/* ---------------------------------- PPB_CPACR --------------------------------- */ -#define PPB_CPACR_CP10_Pos \ - (20UL) /*!< PPB CPACR: CP10 (Bit 20) */ -#define PPB_CPACR_CP10_Msk \ - (0x300000UL) /*!< PPB CPACR: CP10 (Bitfield-Mask: 0x03) */ -#define PPB_CPACR_CP11_Pos \ - (22UL) /*!< PPB CPACR: CP11 (Bit 22) */ -#define PPB_CPACR_CP11_Msk \ - (0xc00000UL) /*!< PPB CPACR: CP11 (Bitfield-Mask: 0x03) */ - -/* -------------------------------- PPB_MPU_TYPE -------------------------------- */ -#define PPB_MPU_TYPE_SEPARATE_Pos \ - (0UL) /*!< PPB MPU_TYPE: SEPARATE (Bit 0) */ -#define PPB_MPU_TYPE_SEPARATE_Msk \ - (0x1UL) /*!< PPB MPU_TYPE: SEPARATE (Bitfield-Mask: 0x01) */ -#define PPB_MPU_TYPE_DREGION_Pos \ - (8UL) /*!< PPB MPU_TYPE: DREGION (Bit 8) */ -#define PPB_MPU_TYPE_DREGION_Msk \ - (0xff00UL) /*!< PPB MPU_TYPE: DREGION (Bitfield-Mask: 0xff) */ -#define PPB_MPU_TYPE_IREGION_Pos \ - (16UL) /*!< PPB MPU_TYPE: IREGION (Bit 16) */ -#define PPB_MPU_TYPE_IREGION_Msk \ - (0xff0000UL) /*!< PPB MPU_TYPE: IREGION (Bitfield-Mask: 0xff) */ - -/* -------------------------------- PPB_MPU_CTRL -------------------------------- */ -#define PPB_MPU_CTRL_ENABLE_Pos \ - (0UL) /*!< PPB MPU_CTRL: ENABLE (Bit 0) */ -#define PPB_MPU_CTRL_ENABLE_Msk \ - (0x1UL) /*!< PPB MPU_CTRL: ENABLE (Bitfield-Mask: 0x01) */ -#define PPB_MPU_CTRL_HFNMIENA_Pos \ - (1UL) /*!< PPB MPU_CTRL: HFNMIENA (Bit 1) */ -#define PPB_MPU_CTRL_HFNMIENA_Msk \ - (0x2UL) /*!< PPB MPU_CTRL: HFNMIENA (Bitfield-Mask: 0x01) */ -#define PPB_MPU_CTRL_PRIVDEFENA_Pos \ - (2UL) /*!< PPB MPU_CTRL: PRIVDEFENA (Bit 2) */ -#define PPB_MPU_CTRL_PRIVDEFENA_Msk \ - (0x4UL) /*!< PPB MPU_CTRL: PRIVDEFENA (Bitfield-Mask: 0x01) */ - -/* --------------------------------- PPB_MPU_RNR -------------------------------- */ -#define PPB_MPU_RNR_REGION_Pos \ - (0UL) /*!< PPB MPU_RNR: REGION (Bit 0) */ -#define PPB_MPU_RNR_REGION_Msk \ - (0xffUL) /*!< PPB MPU_RNR: REGION (Bitfield-Mask: 0xff) */ - -/* -------------------------------- PPB_MPU_RBAR -------------------------------- */ -#define PPB_MPU_RBAR_REGION_Pos \ - (0UL) /*!< PPB MPU_RBAR: REGION (Bit 0) */ -#define PPB_MPU_RBAR_REGION_Msk \ - (0xfUL) /*!< PPB MPU_RBAR: REGION (Bitfield-Mask: 0x0f) */ -#define PPB_MPU_RBAR_VALID_Pos \ - (4UL) /*!< PPB MPU_RBAR: VALID (Bit 4) */ -#define PPB_MPU_RBAR_VALID_Msk \ - (0x10UL) /*!< PPB MPU_RBAR: VALID (Bitfield-Mask: 0x01) */ -#define PPB_MPU_RBAR_ADDR_Pos \ - (9UL) /*!< PPB MPU_RBAR: ADDR (Bit 9) */ -#define PPB_MPU_RBAR_ADDR_Msk \ - (0xfffffe00UL) /*!< PPB MPU_RBAR: ADDR (Bitfield-Mask: 0x7fffff) */ - -/* -------------------------------- PPB_MPU_RASR -------------------------------- */ -#define PPB_MPU_RASR_ENABLE_Pos \ - (0UL) /*!< PPB MPU_RASR: ENABLE (Bit 0) */ -#define PPB_MPU_RASR_ENABLE_Msk \ - (0x1UL) /*!< PPB MPU_RASR: ENABLE (Bitfield-Mask: 0x01) */ -#define PPB_MPU_RASR_SIZE_Pos \ - (1UL) /*!< PPB MPU_RASR: SIZE (Bit 1) */ -#define PPB_MPU_RASR_SIZE_Msk \ - (0x3eUL) /*!< PPB MPU_RASR: SIZE (Bitfield-Mask: 0x1f) */ -#define PPB_MPU_RASR_SRD_Pos \ - (8UL) /*!< PPB MPU_RASR: SRD (Bit 8) */ -#define PPB_MPU_RASR_SRD_Msk \ - (0xff00UL) /*!< PPB MPU_RASR: SRD (Bitfield-Mask: 0xff) */ -#define PPB_MPU_RASR_B_Pos \ - (16UL) /*!< PPB MPU_RASR: B (Bit 16) */ -#define PPB_MPU_RASR_B_Msk \ - (0x10000UL) /*!< PPB MPU_RASR: B (Bitfield-Mask: 0x01) */ -#define PPB_MPU_RASR_C_Pos \ - (17UL) /*!< PPB MPU_RASR: C (Bit 17) */ -#define PPB_MPU_RASR_C_Msk \ - (0x20000UL) /*!< PPB MPU_RASR: C (Bitfield-Mask: 0x01) */ -#define PPB_MPU_RASR_S_Pos \ - (18UL) /*!< PPB MPU_RASR: S (Bit 18) */ -#define PPB_MPU_RASR_S_Msk \ - (0x40000UL) /*!< PPB MPU_RASR: S (Bitfield-Mask: 0x01) */ -#define PPB_MPU_RASR_TEX_Pos \ - (19UL) /*!< PPB MPU_RASR: TEX (Bit 19) */ -#define PPB_MPU_RASR_TEX_Msk \ - (0x380000UL) /*!< PPB MPU_RASR: TEX (Bitfield-Mask: 0x07) */ -#define PPB_MPU_RASR_AP_Pos \ - (24UL) /*!< PPB MPU_RASR: AP (Bit 24) */ -#define PPB_MPU_RASR_AP_Msk \ - (0x7000000UL) /*!< PPB MPU_RASR: AP (Bitfield-Mask: 0x07) */ -#define PPB_MPU_RASR_XN_Pos \ - (28UL) /*!< PPB MPU_RASR: XN (Bit 28) */ -#define PPB_MPU_RASR_XN_Msk \ - (0x10000000UL) /*!< PPB MPU_RASR: XN (Bitfield-Mask: 0x01) */ - -/* ------------------------------- PPB_MPU_RBAR_A1 ------------------------------ */ -#define PPB_MPU_RBAR_A1_REGION_Pos \ - (0UL) /*!< PPB MPU_RBAR_A1: REGION (Bit 0) */ -#define PPB_MPU_RBAR_A1_REGION_Msk \ - (0xfUL) /*!< PPB MPU_RBAR_A1: REGION (Bitfield-Mask: 0x0f) */ -#define PPB_MPU_RBAR_A1_VALID_Pos \ - (4UL) /*!< PPB MPU_RBAR_A1: VALID (Bit 4) */ -#define PPB_MPU_RBAR_A1_VALID_Msk \ - (0x10UL) /*!< PPB MPU_RBAR_A1: VALID (Bitfield-Mask: 0x01) */ -#define PPB_MPU_RBAR_A1_ADDR_Pos \ - (9UL) /*!< PPB MPU_RBAR_A1: ADDR (Bit 9) */ -#define PPB_MPU_RBAR_A1_ADDR_Msk \ - (0xfffffe00UL) /*!< PPB MPU_RBAR_A1: ADDR (Bitfield-Mask: 0x7fffff) */ - -/* ------------------------------- PPB_MPU_RASR_A1 ------------------------------ */ -#define PPB_MPU_RASR_A1_ENABLE_Pos \ - (0UL) /*!< PPB MPU_RASR_A1: ENABLE (Bit 0) */ -#define PPB_MPU_RASR_A1_ENABLE_Msk \ - (0x1UL) /*!< PPB MPU_RASR_A1: ENABLE (Bitfield-Mask: 0x01) */ -#define PPB_MPU_RASR_A1_SIZE_Pos \ - (1UL) /*!< PPB MPU_RASR_A1: SIZE (Bit 1) */ -#define PPB_MPU_RASR_A1_SIZE_Msk \ - (0x3eUL) /*!< PPB MPU_RASR_A1: SIZE (Bitfield-Mask: 0x1f) */ -#define PPB_MPU_RASR_A1_SRD_Pos \ - (8UL) /*!< PPB MPU_RASR_A1: SRD (Bit 8) */ -#define PPB_MPU_RASR_A1_SRD_Msk \ - (0xff00UL) /*!< PPB MPU_RASR_A1: SRD (Bitfield-Mask: 0xff) */ -#define PPB_MPU_RASR_A1_B_Pos \ - (16UL) /*!< PPB MPU_RASR_A1: B (Bit 16) */ -#define PPB_MPU_RASR_A1_B_Msk \ - (0x10000UL) /*!< PPB MPU_RASR_A1: B (Bitfield-Mask: 0x01) */ -#define PPB_MPU_RASR_A1_C_Pos \ - (17UL) /*!< PPB MPU_RASR_A1: C (Bit 17) */ -#define PPB_MPU_RASR_A1_C_Msk \ - (0x20000UL) /*!< PPB MPU_RASR_A1: C (Bitfield-Mask: 0x01) */ -#define PPB_MPU_RASR_A1_S_Pos \ - (18UL) /*!< PPB MPU_RASR_A1: S (Bit 18) */ -#define PPB_MPU_RASR_A1_S_Msk \ - (0x40000UL) /*!< PPB MPU_RASR_A1: S (Bitfield-Mask: 0x01) */ -#define PPB_MPU_RASR_A1_TEX_Pos \ - (19UL) /*!< PPB MPU_RASR_A1: TEX (Bit 19) */ -#define PPB_MPU_RASR_A1_TEX_Msk \ - (0x380000UL) /*!< PPB MPU_RASR_A1: TEX (Bitfield-Mask: 0x07) */ -#define PPB_MPU_RASR_A1_AP_Pos \ - (24UL) /*!< PPB MPU_RASR_A1: AP (Bit 24) */ -#define PPB_MPU_RASR_A1_AP_Msk \ - (0x7000000UL) /*!< PPB MPU_RASR_A1: AP (Bitfield-Mask: 0x07) */ -#define PPB_MPU_RASR_A1_XN_Pos \ - (28UL) /*!< PPB MPU_RASR_A1: XN (Bit 28) */ -#define PPB_MPU_RASR_A1_XN_Msk \ - (0x10000000UL) /*!< PPB MPU_RASR_A1: XN (Bitfield-Mask: 0x01) */ - -/* ------------------------------- PPB_MPU_RBAR_A2 ------------------------------ */ -#define PPB_MPU_RBAR_A2_REGION_Pos \ - (0UL) /*!< PPB MPU_RBAR_A2: REGION (Bit 0) */ -#define PPB_MPU_RBAR_A2_REGION_Msk \ - (0xfUL) /*!< PPB MPU_RBAR_A2: REGION (Bitfield-Mask: 0x0f) */ -#define PPB_MPU_RBAR_A2_VALID_Pos \ - (4UL) /*!< PPB MPU_RBAR_A2: VALID (Bit 4) */ -#define PPB_MPU_RBAR_A2_VALID_Msk \ - (0x10UL) /*!< PPB MPU_RBAR_A2: VALID (Bitfield-Mask: 0x01) */ -#define PPB_MPU_RBAR_A2_ADDR_Pos \ - (9UL) /*!< PPB MPU_RBAR_A2: ADDR (Bit 9) */ -#define PPB_MPU_RBAR_A2_ADDR_Msk \ - (0xfffffe00UL) /*!< PPB MPU_RBAR_A2: ADDR (Bitfield-Mask: 0x7fffff) */ - -/* ------------------------------- PPB_MPU_RASR_A2 ------------------------------ */ -#define PPB_MPU_RASR_A2_ENABLE_Pos \ - (0UL) /*!< PPB MPU_RASR_A2: ENABLE (Bit 0) */ -#define PPB_MPU_RASR_A2_ENABLE_Msk \ - (0x1UL) /*!< PPB MPU_RASR_A2: ENABLE (Bitfield-Mask: 0x01) */ -#define PPB_MPU_RASR_A2_SIZE_Pos \ - (1UL) /*!< PPB MPU_RASR_A2: SIZE (Bit 1) */ -#define PPB_MPU_RASR_A2_SIZE_Msk \ - (0x3eUL) /*!< PPB MPU_RASR_A2: SIZE (Bitfield-Mask: 0x1f) */ -#define PPB_MPU_RASR_A2_SRD_Pos \ - (8UL) /*!< PPB MPU_RASR_A2: SRD (Bit 8) */ -#define PPB_MPU_RASR_A2_SRD_Msk \ - (0xff00UL) /*!< PPB MPU_RASR_A2: SRD (Bitfield-Mask: 0xff) */ -#define PPB_MPU_RASR_A2_B_Pos \ - (16UL) /*!< PPB MPU_RASR_A2: B (Bit 16) */ -#define PPB_MPU_RASR_A2_B_Msk \ - (0x10000UL) /*!< PPB MPU_RASR_A2: B (Bitfield-Mask: 0x01) */ -#define PPB_MPU_RASR_A2_C_Pos \ - (17UL) /*!< PPB MPU_RASR_A2: C (Bit 17) */ -#define PPB_MPU_RASR_A2_C_Msk \ - (0x20000UL) /*!< PPB MPU_RASR_A2: C (Bitfield-Mask: 0x01) */ -#define PPB_MPU_RASR_A2_S_Pos \ - (18UL) /*!< PPB MPU_RASR_A2: S (Bit 18) */ -#define PPB_MPU_RASR_A2_S_Msk \ - (0x40000UL) /*!< PPB MPU_RASR_A2: S (Bitfield-Mask: 0x01) */ -#define PPB_MPU_RASR_A2_TEX_Pos \ - (19UL) /*!< PPB MPU_RASR_A2: TEX (Bit 19) */ -#define PPB_MPU_RASR_A2_TEX_Msk \ - (0x380000UL) /*!< PPB MPU_RASR_A2: TEX (Bitfield-Mask: 0x07) */ -#define PPB_MPU_RASR_A2_AP_Pos \ - (24UL) /*!< PPB MPU_RASR_A2: AP (Bit 24) */ -#define PPB_MPU_RASR_A2_AP_Msk \ - (0x7000000UL) /*!< PPB MPU_RASR_A2: AP (Bitfield-Mask: 0x07) */ -#define PPB_MPU_RASR_A2_XN_Pos \ - (28UL) /*!< PPB MPU_RASR_A2: XN (Bit 28) */ -#define PPB_MPU_RASR_A2_XN_Msk \ - (0x10000000UL) /*!< PPB MPU_RASR_A2: XN (Bitfield-Mask: 0x01) */ - -/* ------------------------------- PPB_MPU_RBAR_A3 ------------------------------ */ -#define PPB_MPU_RBAR_A3_REGION_Pos \ - (0UL) /*!< PPB MPU_RBAR_A3: REGION (Bit 0) */ -#define PPB_MPU_RBAR_A3_REGION_Msk \ - (0xfUL) /*!< PPB MPU_RBAR_A3: REGION (Bitfield-Mask: 0x0f) */ -#define PPB_MPU_RBAR_A3_VALID_Pos \ - (4UL) /*!< PPB MPU_RBAR_A3: VALID (Bit 4) */ -#define PPB_MPU_RBAR_A3_VALID_Msk \ - (0x10UL) /*!< PPB MPU_RBAR_A3: VALID (Bitfield-Mask: 0x01) */ -#define PPB_MPU_RBAR_A3_ADDR_Pos \ - (9UL) /*!< PPB MPU_RBAR_A3: ADDR (Bit 9) */ -#define PPB_MPU_RBAR_A3_ADDR_Msk \ - (0xfffffe00UL) /*!< PPB MPU_RBAR_A3: ADDR (Bitfield-Mask: 0x7fffff) */ - -/* ------------------------------- PPB_MPU_RASR_A3 ------------------------------ */ -#define PPB_MPU_RASR_A3_ENABLE_Pos \ - (0UL) /*!< PPB MPU_RASR_A3: ENABLE (Bit 0) */ -#define PPB_MPU_RASR_A3_ENABLE_Msk \ - (0x1UL) /*!< PPB MPU_RASR_A3: ENABLE (Bitfield-Mask: 0x01) */ -#define PPB_MPU_RASR_A3_SIZE_Pos \ - (1UL) /*!< PPB MPU_RASR_A3: SIZE (Bit 1) */ -#define PPB_MPU_RASR_A3_SIZE_Msk \ - (0x3eUL) /*!< PPB MPU_RASR_A3: SIZE (Bitfield-Mask: 0x1f) */ -#define PPB_MPU_RASR_A3_SRD_Pos \ - (8UL) /*!< PPB MPU_RASR_A3: SRD (Bit 8) */ -#define PPB_MPU_RASR_A3_SRD_Msk \ - (0xff00UL) /*!< PPB MPU_RASR_A3: SRD (Bitfield-Mask: 0xff) */ -#define PPB_MPU_RASR_A3_B_Pos \ - (16UL) /*!< PPB MPU_RASR_A3: B (Bit 16) */ -#define PPB_MPU_RASR_A3_B_Msk \ - (0x10000UL) /*!< PPB MPU_RASR_A3: B (Bitfield-Mask: 0x01) */ -#define PPB_MPU_RASR_A3_C_Pos \ - (17UL) /*!< PPB MPU_RASR_A3: C (Bit 17) */ -#define PPB_MPU_RASR_A3_C_Msk \ - (0x20000UL) /*!< PPB MPU_RASR_A3: C (Bitfield-Mask: 0x01) */ -#define PPB_MPU_RASR_A3_S_Pos \ - (18UL) /*!< PPB MPU_RASR_A3: S (Bit 18) */ -#define PPB_MPU_RASR_A3_S_Msk \ - (0x40000UL) /*!< PPB MPU_RASR_A3: S (Bitfield-Mask: 0x01) */ -#define PPB_MPU_RASR_A3_TEX_Pos \ - (19UL) /*!< PPB MPU_RASR_A3: TEX (Bit 19) */ -#define PPB_MPU_RASR_A3_TEX_Msk \ - (0x380000UL) /*!< PPB MPU_RASR_A3: TEX (Bitfield-Mask: 0x07) */ -#define PPB_MPU_RASR_A3_AP_Pos \ - (24UL) /*!< PPB MPU_RASR_A3: AP (Bit 24) */ -#define PPB_MPU_RASR_A3_AP_Msk \ - (0x7000000UL) /*!< PPB MPU_RASR_A3: AP (Bitfield-Mask: 0x07) */ -#define PPB_MPU_RASR_A3_XN_Pos \ - (28UL) /*!< PPB MPU_RASR_A3: XN (Bit 28) */ -#define PPB_MPU_RASR_A3_XN_Msk \ - (0x10000000UL) /*!< PPB MPU_RASR_A3: XN (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- PPB_STIR ---------------------------------- */ -#define PPB_STIR_INTID_Pos (0UL) /*!< PPB STIR: INTID (Bit 0) */ -#define PPB_STIR_INTID_Msk \ - (0x1ffUL) /*!< PPB STIR: INTID (Bitfield-Mask: 0x1ff) */ - -/* ---------------------------------- PPB_FPCCR --------------------------------- */ -#define PPB_FPCCR_LSPACT_Pos \ - (0UL) /*!< PPB FPCCR: LSPACT (Bit 0) */ -#define PPB_FPCCR_LSPACT_Msk \ - (0x1UL) /*!< PPB FPCCR: LSPACT (Bitfield-Mask: 0x01) */ -#define PPB_FPCCR_USER_Pos (1UL) /*!< PPB FPCCR: USER (Bit 1) */ -#define PPB_FPCCR_USER_Msk \ - (0x2UL) /*!< PPB FPCCR: USER (Bitfield-Mask: 0x01) */ -#define PPB_FPCCR_THREAD_Pos \ - (3UL) /*!< PPB FPCCR: THREAD (Bit 3) */ -#define PPB_FPCCR_THREAD_Msk \ - (0x8UL) /*!< PPB FPCCR: THREAD (Bitfield-Mask: 0x01) */ -#define PPB_FPCCR_HFRDY_Pos \ - (4UL) /*!< PPB FPCCR: HFRDY (Bit 4) */ -#define PPB_FPCCR_HFRDY_Msk \ - (0x10UL) /*!< PPB FPCCR: HFRDY (Bitfield-Mask: 0x01) */ -#define PPB_FPCCR_MMRDY_Pos \ - (5UL) /*!< PPB FPCCR: MMRDY (Bit 5) */ -#define PPB_FPCCR_MMRDY_Msk \ - (0x20UL) /*!< PPB FPCCR: MMRDY (Bitfield-Mask: 0x01) */ -#define PPB_FPCCR_BFRDY_Pos \ - (6UL) /*!< PPB FPCCR: BFRDY (Bit 6) */ -#define PPB_FPCCR_BFRDY_Msk \ - (0x40UL) /*!< PPB FPCCR: BFRDY (Bitfield-Mask: 0x01) */ -#define PPB_FPCCR_MONRDY_Pos \ - (8UL) /*!< PPB FPCCR: MONRDY (Bit 8) */ -#define PPB_FPCCR_MONRDY_Msk \ - (0x100UL) /*!< PPB FPCCR: MONRDY (Bitfield-Mask: 0x01) */ -#define PPB_FPCCR_LSPEN_Pos \ - (30UL) /*!< PPB FPCCR: LSPEN (Bit 30) */ -#define PPB_FPCCR_LSPEN_Msk \ - (0x40000000UL) /*!< PPB FPCCR: LSPEN (Bitfield-Mask: 0x01) */ -#define PPB_FPCCR_ASPEN_Pos \ - (31UL) /*!< PPB FPCCR: ASPEN (Bit 31) */ -#define PPB_FPCCR_ASPEN_Msk \ - (0x80000000UL) /*!< PPB FPCCR: ASPEN (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- PPB_FPCAR --------------------------------- */ -#define PPB_FPCAR_ADDRESS_Pos \ - (3UL) /*!< PPB FPCAR: ADDRESS (Bit 3) */ -#define PPB_FPCAR_ADDRESS_Msk \ - (0xfffffff8UL) /*!< PPB FPCAR: ADDRESS (Bitfield-Mask: 0x1fffffff) */ - -/* --------------------------------- PPB_FPDSCR --------------------------------- */ -#define PPB_FPDSCR_RMode_Pos \ - (22UL) /*!< PPB FPDSCR: RMode (Bit 22) */ -#define PPB_FPDSCR_RMode_Msk \ - (0xc00000UL) /*!< PPB FPDSCR: RMode (Bitfield-Mask: 0x03) */ -#define PPB_FPDSCR_FZ_Pos (24UL) /*!< PPB FPDSCR: FZ (Bit 24) */ -#define PPB_FPDSCR_FZ_Msk \ - (0x1000000UL) /*!< PPB FPDSCR: FZ (Bitfield-Mask: 0x01) */ -#define PPB_FPDSCR_DN_Pos (25UL) /*!< PPB FPDSCR: DN (Bit 25) */ -#define PPB_FPDSCR_DN_Msk \ - (0x2000000UL) /*!< PPB FPDSCR: DN (Bitfield-Mask: 0x01) */ -#define PPB_FPDSCR_AHP_Pos \ - (26UL) /*!< PPB FPDSCR: AHP (Bit 26) */ -#define PPB_FPDSCR_AHP_Msk \ - (0x4000000UL) /*!< PPB FPDSCR: AHP (Bitfield-Mask: 0x01) */ - -/* ================================================================================ */ -/* ================ struct 'DLR' Position & Mask ================ */ -/* ================================================================================ */ - -/* --------------------------------- DLR_OVRSTAT -------------------------------- */ -#define DLR_OVRSTAT_LN0_Pos \ - (0UL) /*!< DLR OVRSTAT: LN0 (Bit 0) */ -#define DLR_OVRSTAT_LN0_Msk \ - (0x1UL) /*!< DLR OVRSTAT: LN0 (Bitfield-Mask: 0x01) */ -#define DLR_OVRSTAT_LN1_Pos \ - (1UL) /*!< DLR OVRSTAT: LN1 (Bit 1) */ -#define DLR_OVRSTAT_LN1_Msk \ - (0x2UL) /*!< DLR OVRSTAT: LN1 (Bitfield-Mask: 0x01) */ -#define DLR_OVRSTAT_LN2_Pos \ - (2UL) /*!< DLR OVRSTAT: LN2 (Bit 2) */ -#define DLR_OVRSTAT_LN2_Msk \ - (0x4UL) /*!< DLR OVRSTAT: LN2 (Bitfield-Mask: 0x01) */ -#define DLR_OVRSTAT_LN3_Pos \ - (3UL) /*!< DLR OVRSTAT: LN3 (Bit 3) */ -#define DLR_OVRSTAT_LN3_Msk \ - (0x8UL) /*!< DLR OVRSTAT: LN3 (Bitfield-Mask: 0x01) */ -#define DLR_OVRSTAT_LN4_Pos \ - (4UL) /*!< DLR OVRSTAT: LN4 (Bit 4) */ -#define DLR_OVRSTAT_LN4_Msk \ - (0x10UL) /*!< DLR OVRSTAT: LN4 (Bitfield-Mask: 0x01) */ -#define DLR_OVRSTAT_LN5_Pos \ - (5UL) /*!< DLR OVRSTAT: LN5 (Bit 5) */ -#define DLR_OVRSTAT_LN5_Msk \ - (0x20UL) /*!< DLR OVRSTAT: LN5 (Bitfield-Mask: 0x01) */ -#define DLR_OVRSTAT_LN6_Pos \ - (6UL) /*!< DLR OVRSTAT: LN6 (Bit 6) */ -#define DLR_OVRSTAT_LN6_Msk \ - (0x40UL) /*!< DLR OVRSTAT: LN6 (Bitfield-Mask: 0x01) */ -#define DLR_OVRSTAT_LN7_Pos \ - (7UL) /*!< DLR OVRSTAT: LN7 (Bit 7) */ -#define DLR_OVRSTAT_LN7_Msk \ - (0x80UL) /*!< DLR OVRSTAT: LN7 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- DLR_OVRCLR --------------------------------- */ -#define DLR_OVRCLR_LN0_Pos (0UL) /*!< DLR OVRCLR: LN0 (Bit 0) */ -#define DLR_OVRCLR_LN0_Msk \ - (0x1UL) /*!< DLR OVRCLR: LN0 (Bitfield-Mask: 0x01) */ -#define DLR_OVRCLR_LN1_Pos (1UL) /*!< DLR OVRCLR: LN1 (Bit 1) */ -#define DLR_OVRCLR_LN1_Msk \ - (0x2UL) /*!< DLR OVRCLR: LN1 (Bitfield-Mask: 0x01) */ -#define DLR_OVRCLR_LN2_Pos (2UL) /*!< DLR OVRCLR: LN2 (Bit 2) */ -#define DLR_OVRCLR_LN2_Msk \ - (0x4UL) /*!< DLR OVRCLR: LN2 (Bitfield-Mask: 0x01) */ -#define DLR_OVRCLR_LN3_Pos (3UL) /*!< DLR OVRCLR: LN3 (Bit 3) */ -#define DLR_OVRCLR_LN3_Msk \ - (0x8UL) /*!< DLR OVRCLR: LN3 (Bitfield-Mask: 0x01) */ -#define DLR_OVRCLR_LN4_Pos (4UL) /*!< DLR OVRCLR: LN4 (Bit 4) */ -#define DLR_OVRCLR_LN4_Msk \ - (0x10UL) /*!< DLR OVRCLR: LN4 (Bitfield-Mask: 0x01) */ -#define DLR_OVRCLR_LN5_Pos (5UL) /*!< DLR OVRCLR: LN5 (Bit 5) */ -#define DLR_OVRCLR_LN5_Msk \ - (0x20UL) /*!< DLR OVRCLR: LN5 (Bitfield-Mask: 0x01) */ -#define DLR_OVRCLR_LN6_Pos (6UL) /*!< DLR OVRCLR: LN6 (Bit 6) */ -#define DLR_OVRCLR_LN6_Msk \ - (0x40UL) /*!< DLR OVRCLR: LN6 (Bitfield-Mask: 0x01) */ -#define DLR_OVRCLR_LN7_Pos (7UL) /*!< DLR OVRCLR: LN7 (Bit 7) */ -#define DLR_OVRCLR_LN7_Msk \ - (0x80UL) /*!< DLR OVRCLR: LN7 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- DLR_SRSEL0 --------------------------------- */ -#define DLR_SRSEL0_RS0_Pos (0UL) /*!< DLR SRSEL0: RS0 (Bit 0) */ -#define DLR_SRSEL0_RS0_Msk \ - (0xfUL) /*!< DLR SRSEL0: RS0 (Bitfield-Mask: 0x0f) */ -#define DLR_SRSEL0_RS1_Pos (4UL) /*!< DLR SRSEL0: RS1 (Bit 4) */ -#define DLR_SRSEL0_RS1_Msk \ - (0xf0UL) /*!< DLR SRSEL0: RS1 (Bitfield-Mask: 0x0f) */ -#define DLR_SRSEL0_RS2_Pos (8UL) /*!< DLR SRSEL0: RS2 (Bit 8) */ -#define DLR_SRSEL0_RS2_Msk \ - (0xf00UL) /*!< DLR SRSEL0: RS2 (Bitfield-Mask: 0x0f) */ -#define DLR_SRSEL0_RS3_Pos \ - (12UL) /*!< DLR SRSEL0: RS3 (Bit 12) */ -#define DLR_SRSEL0_RS3_Msk \ - (0xf000UL) /*!< DLR SRSEL0: RS3 (Bitfield-Mask: 0x0f) */ -#define DLR_SRSEL0_RS4_Pos \ - (16UL) /*!< DLR SRSEL0: RS4 (Bit 16) */ -#define DLR_SRSEL0_RS4_Msk \ - (0xf0000UL) /*!< DLR SRSEL0: RS4 (Bitfield-Mask: 0x0f) */ -#define DLR_SRSEL0_RS5_Pos \ - (20UL) /*!< DLR SRSEL0: RS5 (Bit 20) */ -#define DLR_SRSEL0_RS5_Msk \ - (0xf00000UL) /*!< DLR SRSEL0: RS5 (Bitfield-Mask: 0x0f) */ -#define DLR_SRSEL0_RS6_Pos \ - (24UL) /*!< DLR SRSEL0: RS6 (Bit 24) */ -#define DLR_SRSEL0_RS6_Msk \ - (0xf000000UL) /*!< DLR SRSEL0: RS6 (Bitfield-Mask: 0x0f) */ -#define DLR_SRSEL0_RS7_Pos \ - (28UL) /*!< DLR SRSEL0: RS7 (Bit 28) */ -#define DLR_SRSEL0_RS7_Msk \ - (0xf0000000UL) /*!< DLR SRSEL0: RS7 (Bitfield-Mask: 0x0f) */ - -/* ---------------------------------- DLR_LNEN ---------------------------------- */ -#define DLR_LNEN_LN0_Pos (0UL) /*!< DLR LNEN: LN0 (Bit 0) */ -#define DLR_LNEN_LN0_Msk (0x1UL) /*!< DLR LNEN: LN0 (Bitfield-Mask: 0x01) */ -#define DLR_LNEN_LN1_Pos (1UL) /*!< DLR LNEN: LN1 (Bit 1) */ -#define DLR_LNEN_LN1_Msk (0x2UL) /*!< DLR LNEN: LN1 (Bitfield-Mask: 0x01) */ -#define DLR_LNEN_LN2_Pos (2UL) /*!< DLR LNEN: LN2 (Bit 2) */ -#define DLR_LNEN_LN2_Msk (0x4UL) /*!< DLR LNEN: LN2 (Bitfield-Mask: 0x01) */ -#define DLR_LNEN_LN3_Pos (3UL) /*!< DLR LNEN: LN3 (Bit 3) */ -#define DLR_LNEN_LN3_Msk (0x8UL) /*!< DLR LNEN: LN3 (Bitfield-Mask: 0x01) */ -#define DLR_LNEN_LN4_Pos (4UL) /*!< DLR LNEN: LN4 (Bit 4) */ -#define DLR_LNEN_LN4_Msk \ - (0x10UL) /*!< DLR LNEN: LN4 (Bitfield-Mask: 0x01) */ -#define DLR_LNEN_LN5_Pos (5UL) /*!< DLR LNEN: LN5 (Bit 5) */ -#define DLR_LNEN_LN5_Msk \ - (0x20UL) /*!< DLR LNEN: LN5 (Bitfield-Mask: 0x01) */ -#define DLR_LNEN_LN6_Pos (6UL) /*!< DLR LNEN: LN6 (Bit 6) */ -#define DLR_LNEN_LN6_Msk \ - (0x40UL) /*!< DLR LNEN: LN6 (Bitfield-Mask: 0x01) */ -#define DLR_LNEN_LN7_Pos (7UL) /*!< DLR LNEN: LN7 (Bit 7) */ -#define DLR_LNEN_LN7_Msk \ - (0x80UL) /*!< DLR LNEN: LN7 (Bitfield-Mask: 0x01) */ - -/* ================================================================================ */ -/* ================ Group 'ERU' Position & Mask ================ */ -/* ================================================================================ */ - -/* --------------------------------- ERU_EXISEL --------------------------------- */ -#define ERU_EXISEL_EXS0A_Pos \ - (0UL) /*!< ERU EXISEL: EXS0A (Bit 0) */ -#define ERU_EXISEL_EXS0A_Msk \ - (0x3UL) /*!< ERU EXISEL: EXS0A (Bitfield-Mask: 0x03) */ -#define ERU_EXISEL_EXS0B_Pos \ - (2UL) /*!< ERU EXISEL: EXS0B (Bit 2) */ -#define ERU_EXISEL_EXS0B_Msk \ - (0xcUL) /*!< ERU EXISEL: EXS0B (Bitfield-Mask: 0x03) */ -#define ERU_EXISEL_EXS1A_Pos \ - (4UL) /*!< ERU EXISEL: EXS1A (Bit 4) */ -#define ERU_EXISEL_EXS1A_Msk \ - (0x30UL) /*!< ERU EXISEL: EXS1A (Bitfield-Mask: 0x03) */ -#define ERU_EXISEL_EXS1B_Pos \ - (6UL) /*!< ERU EXISEL: EXS1B (Bit 6) */ -#define ERU_EXISEL_EXS1B_Msk \ - (0xc0UL) /*!< ERU EXISEL: EXS1B (Bitfield-Mask: 0x03) */ -#define ERU_EXISEL_EXS2A_Pos \ - (8UL) /*!< ERU EXISEL: EXS2A (Bit 8) */ -#define ERU_EXISEL_EXS2A_Msk \ - (0x300UL) /*!< ERU EXISEL: EXS2A (Bitfield-Mask: 0x03) */ -#define ERU_EXISEL_EXS2B_Pos \ - (10UL) /*!< ERU EXISEL: EXS2B (Bit 10) */ -#define ERU_EXISEL_EXS2B_Msk \ - (0xc00UL) /*!< ERU EXISEL: EXS2B (Bitfield-Mask: 0x03) */ -#define ERU_EXISEL_EXS3A_Pos \ - (12UL) /*!< ERU EXISEL: EXS3A (Bit 12) */ -#define ERU_EXISEL_EXS3A_Msk \ - (0x3000UL) /*!< ERU EXISEL: EXS3A (Bitfield-Mask: 0x03) */ -#define ERU_EXISEL_EXS3B_Pos \ - (14UL) /*!< ERU EXISEL: EXS3B (Bit 14) */ -#define ERU_EXISEL_EXS3B_Msk \ - (0xc000UL) /*!< ERU EXISEL: EXS3B (Bitfield-Mask: 0x03) */ - -/* --------------------------------- ERU_EXICON --------------------------------- */ -#define ERU_EXICON_PE_Pos (0UL) /*!< ERU EXICON: PE (Bit 0) */ -#define ERU_EXICON_PE_Msk \ - (0x1UL) /*!< ERU EXICON: PE (Bitfield-Mask: 0x01) */ -#define ERU_EXICON_LD_Pos (1UL) /*!< ERU EXICON: LD (Bit 1) */ -#define ERU_EXICON_LD_Msk \ - (0x2UL) /*!< ERU EXICON: LD (Bitfield-Mask: 0x01) */ -#define ERU_EXICON_RE_Pos (2UL) /*!< ERU EXICON: RE (Bit 2) */ -#define ERU_EXICON_RE_Msk \ - (0x4UL) /*!< ERU EXICON: RE (Bitfield-Mask: 0x01) */ -#define ERU_EXICON_FE_Pos (3UL) /*!< ERU EXICON: FE (Bit 3) */ -#define ERU_EXICON_FE_Msk \ - (0x8UL) /*!< ERU EXICON: FE (Bitfield-Mask: 0x01) */ -#define ERU_EXICON_OCS_Pos (4UL) /*!< ERU EXICON: OCS (Bit 4) */ -#define ERU_EXICON_OCS_Msk \ - (0x70UL) /*!< ERU EXICON: OCS (Bitfield-Mask: 0x07) */ -#define ERU_EXICON_FL_Pos (7UL) /*!< ERU EXICON: FL (Bit 7) */ -#define ERU_EXICON_FL_Msk \ - (0x80UL) /*!< ERU EXICON: FL (Bitfield-Mask: 0x01) */ -#define ERU_EXICON_SS_Pos (8UL) /*!< ERU EXICON: SS (Bit 8) */ -#define ERU_EXICON_SS_Msk \ - (0x300UL) /*!< ERU EXICON: SS (Bitfield-Mask: 0x03) */ -#define ERU_EXICON_NA_Pos (10UL) /*!< ERU EXICON: NA (Bit 10) */ -#define ERU_EXICON_NA_Msk \ - (0x400UL) /*!< ERU EXICON: NA (Bitfield-Mask: 0x01) */ -#define ERU_EXICON_NB_Pos (11UL) /*!< ERU EXICON: NB (Bit 11) */ -#define ERU_EXICON_NB_Msk \ - (0x800UL) /*!< ERU EXICON: NB (Bitfield-Mask: 0x01) */ - -/* --------------------------------- ERU_EXOCON --------------------------------- */ -#define ERU_EXOCON_ISS_Pos (0UL) /*!< ERU EXOCON: ISS (Bit 0) */ -#define ERU_EXOCON_ISS_Msk \ - (0x3UL) /*!< ERU EXOCON: ISS (Bitfield-Mask: 0x03) */ -#define ERU_EXOCON_GEEN_Pos \ - (2UL) /*!< ERU EXOCON: GEEN (Bit 2) */ -#define ERU_EXOCON_GEEN_Msk \ - (0x4UL) /*!< ERU EXOCON: GEEN (Bitfield-Mask: 0x01) */ -#define ERU_EXOCON_PDR_Pos (3UL) /*!< ERU EXOCON: PDR (Bit 3) */ -#define ERU_EXOCON_PDR_Msk \ - (0x8UL) /*!< ERU EXOCON: PDR (Bitfield-Mask: 0x01) */ -#define ERU_EXOCON_GP_Pos (4UL) /*!< ERU EXOCON: GP (Bit 4) */ -#define ERU_EXOCON_GP_Msk \ - (0x30UL) /*!< ERU EXOCON: GP (Bitfield-Mask: 0x03) */ -#define ERU_EXOCON_IPEN0_Pos \ - (12UL) /*!< ERU EXOCON: IPEN0 (Bit 12) */ -#define ERU_EXOCON_IPEN0_Msk \ - (0x1000UL) /*!< ERU EXOCON: IPEN0 (Bitfield-Mask: 0x01) */ -#define ERU_EXOCON_IPEN1_Pos \ - (13UL) /*!< ERU EXOCON: IPEN1 (Bit 13) */ -#define ERU_EXOCON_IPEN1_Msk \ - (0x2000UL) /*!< ERU EXOCON: IPEN1 (Bitfield-Mask: 0x01) */ -#define ERU_EXOCON_IPEN2_Pos \ - (14UL) /*!< ERU EXOCON: IPEN2 (Bit 14) */ -#define ERU_EXOCON_IPEN2_Msk \ - (0x4000UL) /*!< ERU EXOCON: IPEN2 (Bitfield-Mask: 0x01) */ -#define ERU_EXOCON_IPEN3_Pos \ - (15UL) /*!< ERU EXOCON: IPEN3 (Bit 15) */ -#define ERU_EXOCON_IPEN3_Msk \ - (0x8000UL) /*!< ERU EXOCON: IPEN3 (Bitfield-Mask: 0x01) */ - -/* ================================================================================ */ -/* ================ struct 'GPDMA0' Position & Mask ================ */ -/* ================================================================================ */ - -/* -------------------------------- GPDMA0_RAWTFR ------------------------------- */ -#define GPDMA0_RAWTFR_CH0_Pos \ - (0UL) /*!< GPDMA0 RAWTFR: CH0 (Bit 0) */ -#define GPDMA0_RAWTFR_CH0_Msk \ - (0x1UL) /*!< GPDMA0 RAWTFR: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWTFR_CH1_Pos \ - (1UL) /*!< GPDMA0 RAWTFR: CH1 (Bit 1) */ -#define GPDMA0_RAWTFR_CH1_Msk \ - (0x2UL) /*!< GPDMA0 RAWTFR: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWTFR_CH2_Pos \ - (2UL) /*!< GPDMA0 RAWTFR: CH2 (Bit 2) */ -#define GPDMA0_RAWTFR_CH2_Msk \ - (0x4UL) /*!< GPDMA0 RAWTFR: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWTFR_CH3_Pos \ - (3UL) /*!< GPDMA0 RAWTFR: CH3 (Bit 3) */ -#define GPDMA0_RAWTFR_CH3_Msk \ - (0x8UL) /*!< GPDMA0 RAWTFR: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWTFR_CH4_Pos \ - (4UL) /*!< GPDMA0 RAWTFR: CH4 (Bit 4) */ -#define GPDMA0_RAWTFR_CH4_Msk \ - (0x10UL) /*!< GPDMA0 RAWTFR: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWTFR_CH5_Pos \ - (5UL) /*!< GPDMA0 RAWTFR: CH5 (Bit 5) */ -#define GPDMA0_RAWTFR_CH5_Msk \ - (0x20UL) /*!< GPDMA0 RAWTFR: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWTFR_CH6_Pos \ - (6UL) /*!< GPDMA0 RAWTFR: CH6 (Bit 6) */ -#define GPDMA0_RAWTFR_CH6_Msk \ - (0x40UL) /*!< GPDMA0 RAWTFR: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWTFR_CH7_Pos \ - (7UL) /*!< GPDMA0 RAWTFR: CH7 (Bit 7) */ -#define GPDMA0_RAWTFR_CH7_Msk \ - (0x80UL) /*!< GPDMA0 RAWTFR: CH7 (Bitfield-Mask: 0x01) */ - -/* ------------------------------- GPDMA0_RAWBLOCK ------------------------------ */ -#define GPDMA0_RAWBLOCK_CH0_Pos \ - (0UL) /*!< GPDMA0 RAWBLOCK: CH0 (Bit 0) */ -#define GPDMA0_RAWBLOCK_CH0_Msk \ - (0x1UL) /*!< GPDMA0 RAWBLOCK: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWBLOCK_CH1_Pos \ - (1UL) /*!< GPDMA0 RAWBLOCK: CH1 (Bit 1) */ -#define GPDMA0_RAWBLOCK_CH1_Msk \ - (0x2UL) /*!< GPDMA0 RAWBLOCK: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWBLOCK_CH2_Pos \ - (2UL) /*!< GPDMA0 RAWBLOCK: CH2 (Bit 2) */ -#define GPDMA0_RAWBLOCK_CH2_Msk \ - (0x4UL) /*!< GPDMA0 RAWBLOCK: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWBLOCK_CH3_Pos \ - (3UL) /*!< GPDMA0 RAWBLOCK: CH3 (Bit 3) */ -#define GPDMA0_RAWBLOCK_CH3_Msk \ - (0x8UL) /*!< GPDMA0 RAWBLOCK: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWBLOCK_CH4_Pos \ - (4UL) /*!< GPDMA0 RAWBLOCK: CH4 (Bit 4) */ -#define GPDMA0_RAWBLOCK_CH4_Msk \ - (0x10UL) /*!< GPDMA0 RAWBLOCK: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWBLOCK_CH5_Pos \ - (5UL) /*!< GPDMA0 RAWBLOCK: CH5 (Bit 5) */ -#define GPDMA0_RAWBLOCK_CH5_Msk \ - (0x20UL) /*!< GPDMA0 RAWBLOCK: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWBLOCK_CH6_Pos \ - (6UL) /*!< GPDMA0 RAWBLOCK: CH6 (Bit 6) */ -#define GPDMA0_RAWBLOCK_CH6_Msk \ - (0x40UL) /*!< GPDMA0 RAWBLOCK: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWBLOCK_CH7_Pos \ - (7UL) /*!< GPDMA0 RAWBLOCK: CH7 (Bit 7) */ -#define GPDMA0_RAWBLOCK_CH7_Msk \ - (0x80UL) /*!< GPDMA0 RAWBLOCK: CH7 (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPDMA0_RAWSRCTRAN ----------------------------- */ -#define GPDMA0_RAWSRCTRAN_CH0_Pos \ - (0UL) /*!< GPDMA0 RAWSRCTRAN: CH0 (Bit 0) */ -#define GPDMA0_RAWSRCTRAN_CH0_Msk \ - (0x1UL) /*!< GPDMA0 RAWSRCTRAN: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWSRCTRAN_CH1_Pos \ - (1UL) /*!< GPDMA0 RAWSRCTRAN: CH1 (Bit 1) */ -#define GPDMA0_RAWSRCTRAN_CH1_Msk \ - (0x2UL) /*!< GPDMA0 RAWSRCTRAN: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWSRCTRAN_CH2_Pos \ - (2UL) /*!< GPDMA0 RAWSRCTRAN: CH2 (Bit 2) */ -#define GPDMA0_RAWSRCTRAN_CH2_Msk \ - (0x4UL) /*!< GPDMA0 RAWSRCTRAN: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWSRCTRAN_CH3_Pos \ - (3UL) /*!< GPDMA0 RAWSRCTRAN: CH3 (Bit 3) */ -#define GPDMA0_RAWSRCTRAN_CH3_Msk \ - (0x8UL) /*!< GPDMA0 RAWSRCTRAN: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWSRCTRAN_CH4_Pos \ - (4UL) /*!< GPDMA0 RAWSRCTRAN: CH4 (Bit 4) */ -#define GPDMA0_RAWSRCTRAN_CH4_Msk \ - (0x10UL) /*!< GPDMA0 RAWSRCTRAN: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWSRCTRAN_CH5_Pos \ - (5UL) /*!< GPDMA0 RAWSRCTRAN: CH5 (Bit 5) */ -#define GPDMA0_RAWSRCTRAN_CH5_Msk \ - (0x20UL) /*!< GPDMA0 RAWSRCTRAN: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWSRCTRAN_CH6_Pos \ - (6UL) /*!< GPDMA0 RAWSRCTRAN: CH6 (Bit 6) */ -#define GPDMA0_RAWSRCTRAN_CH6_Msk \ - (0x40UL) /*!< GPDMA0 RAWSRCTRAN: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWSRCTRAN_CH7_Pos \ - (7UL) /*!< GPDMA0 RAWSRCTRAN: CH7 (Bit 7) */ -#define GPDMA0_RAWSRCTRAN_CH7_Msk \ - (0x80UL) /*!< GPDMA0 RAWSRCTRAN: CH7 (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPDMA0_RAWDSTTRAN ----------------------------- */ -#define GPDMA0_RAWDSTTRAN_CH0_Pos \ - (0UL) /*!< GPDMA0 RAWDSTTRAN: CH0 (Bit 0) */ -#define GPDMA0_RAWDSTTRAN_CH0_Msk \ - (0x1UL) /*!< GPDMA0 RAWDSTTRAN: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWDSTTRAN_CH1_Pos \ - (1UL) /*!< GPDMA0 RAWDSTTRAN: CH1 (Bit 1) */ -#define GPDMA0_RAWDSTTRAN_CH1_Msk \ - (0x2UL) /*!< GPDMA0 RAWDSTTRAN: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWDSTTRAN_CH2_Pos \ - (2UL) /*!< GPDMA0 RAWDSTTRAN: CH2 (Bit 2) */ -#define GPDMA0_RAWDSTTRAN_CH2_Msk \ - (0x4UL) /*!< GPDMA0 RAWDSTTRAN: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWDSTTRAN_CH3_Pos \ - (3UL) /*!< GPDMA0 RAWDSTTRAN: CH3 (Bit 3) */ -#define GPDMA0_RAWDSTTRAN_CH3_Msk \ - (0x8UL) /*!< GPDMA0 RAWDSTTRAN: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWDSTTRAN_CH4_Pos \ - (4UL) /*!< GPDMA0 RAWDSTTRAN: CH4 (Bit 4) */ -#define GPDMA0_RAWDSTTRAN_CH4_Msk \ - (0x10UL) /*!< GPDMA0 RAWDSTTRAN: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWDSTTRAN_CH5_Pos \ - (5UL) /*!< GPDMA0 RAWDSTTRAN: CH5 (Bit 5) */ -#define GPDMA0_RAWDSTTRAN_CH5_Msk \ - (0x20UL) /*!< GPDMA0 RAWDSTTRAN: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWDSTTRAN_CH6_Pos \ - (6UL) /*!< GPDMA0 RAWDSTTRAN: CH6 (Bit 6) */ -#define GPDMA0_RAWDSTTRAN_CH6_Msk \ - (0x40UL) /*!< GPDMA0 RAWDSTTRAN: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWDSTTRAN_CH7_Pos \ - (7UL) /*!< GPDMA0 RAWDSTTRAN: CH7 (Bit 7) */ -#define GPDMA0_RAWDSTTRAN_CH7_Msk \ - (0x80UL) /*!< GPDMA0 RAWDSTTRAN: CH7 (Bitfield-Mask: 0x01) */ - -/* -------------------------------- GPDMA0_RAWERR ------------------------------- */ -#define GPDMA0_RAWERR_CH0_Pos \ - (0UL) /*!< GPDMA0 RAWERR: CH0 (Bit 0) */ -#define GPDMA0_RAWERR_CH0_Msk \ - (0x1UL) /*!< GPDMA0 RAWERR: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWERR_CH1_Pos \ - (1UL) /*!< GPDMA0 RAWERR: CH1 (Bit 1) */ -#define GPDMA0_RAWERR_CH1_Msk \ - (0x2UL) /*!< GPDMA0 RAWERR: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWERR_CH2_Pos \ - (2UL) /*!< GPDMA0 RAWERR: CH2 (Bit 2) */ -#define GPDMA0_RAWERR_CH2_Msk \ - (0x4UL) /*!< GPDMA0 RAWERR: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWERR_CH3_Pos \ - (3UL) /*!< GPDMA0 RAWERR: CH3 (Bit 3) */ -#define GPDMA0_RAWERR_CH3_Msk \ - (0x8UL) /*!< GPDMA0 RAWERR: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWERR_CH4_Pos \ - (4UL) /*!< GPDMA0 RAWERR: CH4 (Bit 4) */ -#define GPDMA0_RAWERR_CH4_Msk \ - (0x10UL) /*!< GPDMA0 RAWERR: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWERR_CH5_Pos \ - (5UL) /*!< GPDMA0 RAWERR: CH5 (Bit 5) */ -#define GPDMA0_RAWERR_CH5_Msk \ - (0x20UL) /*!< GPDMA0 RAWERR: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWERR_CH6_Pos \ - (6UL) /*!< GPDMA0 RAWERR: CH6 (Bit 6) */ -#define GPDMA0_RAWERR_CH6_Msk \ - (0x40UL) /*!< GPDMA0 RAWERR: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_RAWERR_CH7_Pos \ - (7UL) /*!< GPDMA0 RAWERR: CH7 (Bit 7) */ -#define GPDMA0_RAWERR_CH7_Msk \ - (0x80UL) /*!< GPDMA0 RAWERR: CH7 (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPDMA0_STATUSTFR ------------------------------ */ -#define GPDMA0_STATUSTFR_CH0_Pos \ - (0UL) /*!< GPDMA0 STATUSTFR: CH0 (Bit 0) */ -#define GPDMA0_STATUSTFR_CH0_Msk \ - (0x1UL) /*!< GPDMA0 STATUSTFR: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSTFR_CH1_Pos \ - (1UL) /*!< GPDMA0 STATUSTFR: CH1 (Bit 1) */ -#define GPDMA0_STATUSTFR_CH1_Msk \ - (0x2UL) /*!< GPDMA0 STATUSTFR: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSTFR_CH2_Pos \ - (2UL) /*!< GPDMA0 STATUSTFR: CH2 (Bit 2) */ -#define GPDMA0_STATUSTFR_CH2_Msk \ - (0x4UL) /*!< GPDMA0 STATUSTFR: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSTFR_CH3_Pos \ - (3UL) /*!< GPDMA0 STATUSTFR: CH3 (Bit 3) */ -#define GPDMA0_STATUSTFR_CH3_Msk \ - (0x8UL) /*!< GPDMA0 STATUSTFR: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSTFR_CH4_Pos \ - (4UL) /*!< GPDMA0 STATUSTFR: CH4 (Bit 4) */ -#define GPDMA0_STATUSTFR_CH4_Msk \ - (0x10UL) /*!< GPDMA0 STATUSTFR: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSTFR_CH5_Pos \ - (5UL) /*!< GPDMA0 STATUSTFR: CH5 (Bit 5) */ -#define GPDMA0_STATUSTFR_CH5_Msk \ - (0x20UL) /*!< GPDMA0 STATUSTFR: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSTFR_CH6_Pos \ - (6UL) /*!< GPDMA0 STATUSTFR: CH6 (Bit 6) */ -#define GPDMA0_STATUSTFR_CH6_Msk \ - (0x40UL) /*!< GPDMA0 STATUSTFR: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSTFR_CH7_Pos \ - (7UL) /*!< GPDMA0 STATUSTFR: CH7 (Bit 7) */ -#define GPDMA0_STATUSTFR_CH7_Msk \ - (0x80UL) /*!< GPDMA0 STATUSTFR: CH7 (Bitfield-Mask: 0x01) */ - -/* ----------------------------- GPDMA0_STATUSBLOCK ----------------------------- */ -#define GPDMA0_STATUSBLOCK_CH0_Pos \ - (0UL) /*!< GPDMA0 STATUSBLOCK: CH0 (Bit 0) */ -#define GPDMA0_STATUSBLOCK_CH0_Msk \ - (0x1UL) /*!< GPDMA0 STATUSBLOCK: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSBLOCK_CH1_Pos \ - (1UL) /*!< GPDMA0 STATUSBLOCK: CH1 (Bit 1) */ -#define GPDMA0_STATUSBLOCK_CH1_Msk \ - (0x2UL) /*!< GPDMA0 STATUSBLOCK: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSBLOCK_CH2_Pos \ - (2UL) /*!< GPDMA0 STATUSBLOCK: CH2 (Bit 2) */ -#define GPDMA0_STATUSBLOCK_CH2_Msk \ - (0x4UL) /*!< GPDMA0 STATUSBLOCK: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSBLOCK_CH3_Pos \ - (3UL) /*!< GPDMA0 STATUSBLOCK: CH3 (Bit 3) */ -#define GPDMA0_STATUSBLOCK_CH3_Msk \ - (0x8UL) /*!< GPDMA0 STATUSBLOCK: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSBLOCK_CH4_Pos \ - (4UL) /*!< GPDMA0 STATUSBLOCK: CH4 (Bit 4) */ -#define GPDMA0_STATUSBLOCK_CH4_Msk \ - (0x10UL) /*!< GPDMA0 STATUSBLOCK: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSBLOCK_CH5_Pos \ - (5UL) /*!< GPDMA0 STATUSBLOCK: CH5 (Bit 5) */ -#define GPDMA0_STATUSBLOCK_CH5_Msk \ - (0x20UL) /*!< GPDMA0 STATUSBLOCK: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSBLOCK_CH6_Pos \ - (6UL) /*!< GPDMA0 STATUSBLOCK: CH6 (Bit 6) */ -#define GPDMA0_STATUSBLOCK_CH6_Msk \ - (0x40UL) /*!< GPDMA0 STATUSBLOCK: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSBLOCK_CH7_Pos \ - (7UL) /*!< GPDMA0 STATUSBLOCK: CH7 (Bit 7) */ -#define GPDMA0_STATUSBLOCK_CH7_Msk \ - (0x80UL) /*!< GPDMA0 STATUSBLOCK: CH7 (Bitfield-Mask: 0x01) */ - -/* ---------------------------- GPDMA0_STATUSSRCTRAN ---------------------------- */ -#define GPDMA0_STATUSSRCTRAN_CH0_Pos \ - (0UL) /*!< GPDMA0 STATUSSRCTRAN: CH0 (Bit 0) */ -#define GPDMA0_STATUSSRCTRAN_CH0_Msk \ - (0x1UL) /*!< GPDMA0 STATUSSRCTRAN: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSSRCTRAN_CH1_Pos \ - (1UL) /*!< GPDMA0 STATUSSRCTRAN: CH1 (Bit 1) */ -#define GPDMA0_STATUSSRCTRAN_CH1_Msk \ - (0x2UL) /*!< GPDMA0 STATUSSRCTRAN: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSSRCTRAN_CH2_Pos \ - (2UL) /*!< GPDMA0 STATUSSRCTRAN: CH2 (Bit 2) */ -#define GPDMA0_STATUSSRCTRAN_CH2_Msk \ - (0x4UL) /*!< GPDMA0 STATUSSRCTRAN: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSSRCTRAN_CH3_Pos \ - (3UL) /*!< GPDMA0 STATUSSRCTRAN: CH3 (Bit 3) */ -#define GPDMA0_STATUSSRCTRAN_CH3_Msk \ - (0x8UL) /*!< GPDMA0 STATUSSRCTRAN: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSSRCTRAN_CH4_Pos \ - (4UL) /*!< GPDMA0 STATUSSRCTRAN: CH4 (Bit 4) */ -#define GPDMA0_STATUSSRCTRAN_CH4_Msk \ - (0x10UL) /*!< GPDMA0 STATUSSRCTRAN: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSSRCTRAN_CH5_Pos \ - (5UL) /*!< GPDMA0 STATUSSRCTRAN: CH5 (Bit 5) */ -#define GPDMA0_STATUSSRCTRAN_CH5_Msk \ - (0x20UL) /*!< GPDMA0 STATUSSRCTRAN: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSSRCTRAN_CH6_Pos \ - (6UL) /*!< GPDMA0 STATUSSRCTRAN: CH6 (Bit 6) */ -#define GPDMA0_STATUSSRCTRAN_CH6_Msk \ - (0x40UL) /*!< GPDMA0 STATUSSRCTRAN: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSSRCTRAN_CH7_Pos \ - (7UL) /*!< GPDMA0 STATUSSRCTRAN: CH7 (Bit 7) */ -#define GPDMA0_STATUSSRCTRAN_CH7_Msk \ - (0x80UL) /*!< GPDMA0 STATUSSRCTRAN: CH7 (Bitfield-Mask: 0x01) */ - -/* ---------------------------- GPDMA0_STATUSDSTTRAN ---------------------------- */ -#define GPDMA0_STATUSDSTTRAN_CH0_Pos \ - (0UL) /*!< GPDMA0 STATUSDSTTRAN: CH0 (Bit 0) */ -#define GPDMA0_STATUSDSTTRAN_CH0_Msk \ - (0x1UL) /*!< GPDMA0 STATUSDSTTRAN: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSDSTTRAN_CH1_Pos \ - (1UL) /*!< GPDMA0 STATUSDSTTRAN: CH1 (Bit 1) */ -#define GPDMA0_STATUSDSTTRAN_CH1_Msk \ - (0x2UL) /*!< GPDMA0 STATUSDSTTRAN: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSDSTTRAN_CH2_Pos \ - (2UL) /*!< GPDMA0 STATUSDSTTRAN: CH2 (Bit 2) */ -#define GPDMA0_STATUSDSTTRAN_CH2_Msk \ - (0x4UL) /*!< GPDMA0 STATUSDSTTRAN: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSDSTTRAN_CH3_Pos \ - (3UL) /*!< GPDMA0 STATUSDSTTRAN: CH3 (Bit 3) */ -#define GPDMA0_STATUSDSTTRAN_CH3_Msk \ - (0x8UL) /*!< GPDMA0 STATUSDSTTRAN: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSDSTTRAN_CH4_Pos \ - (4UL) /*!< GPDMA0 STATUSDSTTRAN: CH4 (Bit 4) */ -#define GPDMA0_STATUSDSTTRAN_CH4_Msk \ - (0x10UL) /*!< GPDMA0 STATUSDSTTRAN: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSDSTTRAN_CH5_Pos \ - (5UL) /*!< GPDMA0 STATUSDSTTRAN: CH5 (Bit 5) */ -#define GPDMA0_STATUSDSTTRAN_CH5_Msk \ - (0x20UL) /*!< GPDMA0 STATUSDSTTRAN: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSDSTTRAN_CH6_Pos \ - (6UL) /*!< GPDMA0 STATUSDSTTRAN: CH6 (Bit 6) */ -#define GPDMA0_STATUSDSTTRAN_CH6_Msk \ - (0x40UL) /*!< GPDMA0 STATUSDSTTRAN: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSDSTTRAN_CH7_Pos \ - (7UL) /*!< GPDMA0 STATUSDSTTRAN: CH7 (Bit 7) */ -#define GPDMA0_STATUSDSTTRAN_CH7_Msk \ - (0x80UL) /*!< GPDMA0 STATUSDSTTRAN: CH7 (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPDMA0_STATUSERR ------------------------------ */ -#define GPDMA0_STATUSERR_CH0_Pos \ - (0UL) /*!< GPDMA0 STATUSERR: CH0 (Bit 0) */ -#define GPDMA0_STATUSERR_CH0_Msk \ - (0x1UL) /*!< GPDMA0 STATUSERR: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSERR_CH1_Pos \ - (1UL) /*!< GPDMA0 STATUSERR: CH1 (Bit 1) */ -#define GPDMA0_STATUSERR_CH1_Msk \ - (0x2UL) /*!< GPDMA0 STATUSERR: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSERR_CH2_Pos \ - (2UL) /*!< GPDMA0 STATUSERR: CH2 (Bit 2) */ -#define GPDMA0_STATUSERR_CH2_Msk \ - (0x4UL) /*!< GPDMA0 STATUSERR: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSERR_CH3_Pos \ - (3UL) /*!< GPDMA0 STATUSERR: CH3 (Bit 3) */ -#define GPDMA0_STATUSERR_CH3_Msk \ - (0x8UL) /*!< GPDMA0 STATUSERR: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSERR_CH4_Pos \ - (4UL) /*!< GPDMA0 STATUSERR: CH4 (Bit 4) */ -#define GPDMA0_STATUSERR_CH4_Msk \ - (0x10UL) /*!< GPDMA0 STATUSERR: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSERR_CH5_Pos \ - (5UL) /*!< GPDMA0 STATUSERR: CH5 (Bit 5) */ -#define GPDMA0_STATUSERR_CH5_Msk \ - (0x20UL) /*!< GPDMA0 STATUSERR: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSERR_CH6_Pos \ - (6UL) /*!< GPDMA0 STATUSERR: CH6 (Bit 6) */ -#define GPDMA0_STATUSERR_CH6_Msk \ - (0x40UL) /*!< GPDMA0 STATUSERR: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSERR_CH7_Pos \ - (7UL) /*!< GPDMA0 STATUSERR: CH7 (Bit 7) */ -#define GPDMA0_STATUSERR_CH7_Msk \ - (0x80UL) /*!< GPDMA0 STATUSERR: CH7 (Bitfield-Mask: 0x01) */ - -/* ------------------------------- GPDMA0_MASKTFR ------------------------------- */ -#define GPDMA0_MASKTFR_CH0_Pos \ - (0UL) /*!< GPDMA0 MASKTFR: CH0 (Bit 0) */ -#define GPDMA0_MASKTFR_CH0_Msk \ - (0x1UL) /*!< GPDMA0 MASKTFR: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKTFR_CH1_Pos \ - (1UL) /*!< GPDMA0 MASKTFR: CH1 (Bit 1) */ -#define GPDMA0_MASKTFR_CH1_Msk \ - (0x2UL) /*!< GPDMA0 MASKTFR: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKTFR_CH2_Pos \ - (2UL) /*!< GPDMA0 MASKTFR: CH2 (Bit 2) */ -#define GPDMA0_MASKTFR_CH2_Msk \ - (0x4UL) /*!< GPDMA0 MASKTFR: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKTFR_CH3_Pos \ - (3UL) /*!< GPDMA0 MASKTFR: CH3 (Bit 3) */ -#define GPDMA0_MASKTFR_CH3_Msk \ - (0x8UL) /*!< GPDMA0 MASKTFR: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKTFR_CH4_Pos \ - (4UL) /*!< GPDMA0 MASKTFR: CH4 (Bit 4) */ -#define GPDMA0_MASKTFR_CH4_Msk \ - (0x10UL) /*!< GPDMA0 MASKTFR: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKTFR_CH5_Pos \ - (5UL) /*!< GPDMA0 MASKTFR: CH5 (Bit 5) */ -#define GPDMA0_MASKTFR_CH5_Msk \ - (0x20UL) /*!< GPDMA0 MASKTFR: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKTFR_CH6_Pos \ - (6UL) /*!< GPDMA0 MASKTFR: CH6 (Bit 6) */ -#define GPDMA0_MASKTFR_CH6_Msk \ - (0x40UL) /*!< GPDMA0 MASKTFR: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKTFR_CH7_Pos \ - (7UL) /*!< GPDMA0 MASKTFR: CH7 (Bit 7) */ -#define GPDMA0_MASKTFR_CH7_Msk \ - (0x80UL) /*!< GPDMA0 MASKTFR: CH7 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKTFR_WE_CH0_Pos \ - (8UL) /*!< GPDMA0 MASKTFR: WE_CH0 (Bit 8) */ -#define GPDMA0_MASKTFR_WE_CH0_Msk \ - (0x100UL) /*!< GPDMA0 MASKTFR: WE_CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKTFR_WE_CH1_Pos \ - (9UL) /*!< GPDMA0 MASKTFR: WE_CH1 (Bit 9) */ -#define GPDMA0_MASKTFR_WE_CH1_Msk \ - (0x200UL) /*!< GPDMA0 MASKTFR: WE_CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKTFR_WE_CH2_Pos \ - (10UL) /*!< GPDMA0 MASKTFR: WE_CH2 (Bit 10) */ -#define GPDMA0_MASKTFR_WE_CH2_Msk \ - (0x400UL) /*!< GPDMA0 MASKTFR: WE_CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKTFR_WE_CH3_Pos \ - (11UL) /*!< GPDMA0 MASKTFR: WE_CH3 (Bit 11) */ -#define GPDMA0_MASKTFR_WE_CH3_Msk \ - (0x800UL) /*!< GPDMA0 MASKTFR: WE_CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKTFR_WE_CH4_Pos \ - (12UL) /*!< GPDMA0 MASKTFR: WE_CH4 (Bit 12) */ -#define GPDMA0_MASKTFR_WE_CH4_Msk \ - (0x1000UL) /*!< GPDMA0 MASKTFR: WE_CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKTFR_WE_CH5_Pos \ - (13UL) /*!< GPDMA0 MASKTFR: WE_CH5 (Bit 13) */ -#define GPDMA0_MASKTFR_WE_CH5_Msk \ - (0x2000UL) /*!< GPDMA0 MASKTFR: WE_CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKTFR_WE_CH6_Pos \ - (14UL) /*!< GPDMA0 MASKTFR: WE_CH6 (Bit 14) */ -#define GPDMA0_MASKTFR_WE_CH6_Msk \ - (0x4000UL) /*!< GPDMA0 MASKTFR: WE_CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKTFR_WE_CH7_Pos \ - (15UL) /*!< GPDMA0 MASKTFR: WE_CH7 (Bit 15) */ -#define GPDMA0_MASKTFR_WE_CH7_Msk \ - (0x8000UL) /*!< GPDMA0 MASKTFR: WE_CH7 (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPDMA0_MASKBLOCK ------------------------------ */ -#define GPDMA0_MASKBLOCK_CH0_Pos \ - (0UL) /*!< GPDMA0 MASKBLOCK: CH0 (Bit 0) */ -#define GPDMA0_MASKBLOCK_CH0_Msk \ - (0x1UL) /*!< GPDMA0 MASKBLOCK: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKBLOCK_CH1_Pos \ - (1UL) /*!< GPDMA0 MASKBLOCK: CH1 (Bit 1) */ -#define GPDMA0_MASKBLOCK_CH1_Msk \ - (0x2UL) /*!< GPDMA0 MASKBLOCK: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKBLOCK_CH2_Pos \ - (2UL) /*!< GPDMA0 MASKBLOCK: CH2 (Bit 2) */ -#define GPDMA0_MASKBLOCK_CH2_Msk \ - (0x4UL) /*!< GPDMA0 MASKBLOCK: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKBLOCK_CH3_Pos \ - (3UL) /*!< GPDMA0 MASKBLOCK: CH3 (Bit 3) */ -#define GPDMA0_MASKBLOCK_CH3_Msk \ - (0x8UL) /*!< GPDMA0 MASKBLOCK: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKBLOCK_CH4_Pos \ - (4UL) /*!< GPDMA0 MASKBLOCK: CH4 (Bit 4) */ -#define GPDMA0_MASKBLOCK_CH4_Msk \ - (0x10UL) /*!< GPDMA0 MASKBLOCK: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKBLOCK_CH5_Pos \ - (5UL) /*!< GPDMA0 MASKBLOCK: CH5 (Bit 5) */ -#define GPDMA0_MASKBLOCK_CH5_Msk \ - (0x20UL) /*!< GPDMA0 MASKBLOCK: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKBLOCK_CH6_Pos \ - (6UL) /*!< GPDMA0 MASKBLOCK: CH6 (Bit 6) */ -#define GPDMA0_MASKBLOCK_CH6_Msk \ - (0x40UL) /*!< GPDMA0 MASKBLOCK: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKBLOCK_CH7_Pos \ - (7UL) /*!< GPDMA0 MASKBLOCK: CH7 (Bit 7) */ -#define GPDMA0_MASKBLOCK_CH7_Msk \ - (0x80UL) /*!< GPDMA0 MASKBLOCK: CH7 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKBLOCK_WE_CH0_Pos \ - (8UL) /*!< GPDMA0 MASKBLOCK: WE_CH0 (Bit 8) */ -#define GPDMA0_MASKBLOCK_WE_CH0_Msk \ - (0x100UL) /*!< GPDMA0 MASKBLOCK: WE_CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKBLOCK_WE_CH1_Pos \ - (9UL) /*!< GPDMA0 MASKBLOCK: WE_CH1 (Bit 9) */ -#define GPDMA0_MASKBLOCK_WE_CH1_Msk \ - (0x200UL) /*!< GPDMA0 MASKBLOCK: WE_CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKBLOCK_WE_CH2_Pos \ - (10UL) /*!< GPDMA0 MASKBLOCK: WE_CH2 (Bit 10) */ -#define GPDMA0_MASKBLOCK_WE_CH2_Msk \ - (0x400UL) /*!< GPDMA0 MASKBLOCK: WE_CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKBLOCK_WE_CH3_Pos \ - (11UL) /*!< GPDMA0 MASKBLOCK: WE_CH3 (Bit 11) */ -#define GPDMA0_MASKBLOCK_WE_CH3_Msk \ - (0x800UL) /*!< GPDMA0 MASKBLOCK: WE_CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKBLOCK_WE_CH4_Pos \ - (12UL) /*!< GPDMA0 MASKBLOCK: WE_CH4 (Bit 12) */ -#define GPDMA0_MASKBLOCK_WE_CH4_Msk \ - (0x1000UL) /*!< GPDMA0 MASKBLOCK: WE_CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKBLOCK_WE_CH5_Pos \ - (13UL) /*!< GPDMA0 MASKBLOCK: WE_CH5 (Bit 13) */ -#define GPDMA0_MASKBLOCK_WE_CH5_Msk \ - (0x2000UL) /*!< GPDMA0 MASKBLOCK: WE_CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKBLOCK_WE_CH6_Pos \ - (14UL) /*!< GPDMA0 MASKBLOCK: WE_CH6 (Bit 14) */ -#define GPDMA0_MASKBLOCK_WE_CH6_Msk \ - (0x4000UL) /*!< GPDMA0 MASKBLOCK: WE_CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKBLOCK_WE_CH7_Pos \ - (15UL) /*!< GPDMA0 MASKBLOCK: WE_CH7 (Bit 15) */ -#define GPDMA0_MASKBLOCK_WE_CH7_Msk \ - (0x8000UL) /*!< GPDMA0 MASKBLOCK: WE_CH7 (Bitfield-Mask: 0x01) */ - -/* ----------------------------- GPDMA0_MASKSRCTRAN ----------------------------- */ -#define GPDMA0_MASKSRCTRAN_CH0_Pos \ - (0UL) /*!< GPDMA0 MASKSRCTRAN: CH0 (Bit 0) */ -#define GPDMA0_MASKSRCTRAN_CH0_Msk \ - (0x1UL) /*!< GPDMA0 MASKSRCTRAN: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKSRCTRAN_CH1_Pos \ - (1UL) /*!< GPDMA0 MASKSRCTRAN: CH1 (Bit 1) */ -#define GPDMA0_MASKSRCTRAN_CH1_Msk \ - (0x2UL) /*!< GPDMA0 MASKSRCTRAN: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKSRCTRAN_CH2_Pos \ - (2UL) /*!< GPDMA0 MASKSRCTRAN: CH2 (Bit 2) */ -#define GPDMA0_MASKSRCTRAN_CH2_Msk \ - (0x4UL) /*!< GPDMA0 MASKSRCTRAN: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKSRCTRAN_CH3_Pos \ - (3UL) /*!< GPDMA0 MASKSRCTRAN: CH3 (Bit 3) */ -#define GPDMA0_MASKSRCTRAN_CH3_Msk \ - (0x8UL) /*!< GPDMA0 MASKSRCTRAN: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKSRCTRAN_CH4_Pos \ - (4UL) /*!< GPDMA0 MASKSRCTRAN: CH4 (Bit 4) */ -#define GPDMA0_MASKSRCTRAN_CH4_Msk \ - (0x10UL) /*!< GPDMA0 MASKSRCTRAN: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKSRCTRAN_CH5_Pos \ - (5UL) /*!< GPDMA0 MASKSRCTRAN: CH5 (Bit 5) */ -#define GPDMA0_MASKSRCTRAN_CH5_Msk \ - (0x20UL) /*!< GPDMA0 MASKSRCTRAN: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKSRCTRAN_CH6_Pos \ - (6UL) /*!< GPDMA0 MASKSRCTRAN: CH6 (Bit 6) */ -#define GPDMA0_MASKSRCTRAN_CH6_Msk \ - (0x40UL) /*!< GPDMA0 MASKSRCTRAN: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKSRCTRAN_CH7_Pos \ - (7UL) /*!< GPDMA0 MASKSRCTRAN: CH7 (Bit 7) */ -#define GPDMA0_MASKSRCTRAN_CH7_Msk \ - (0x80UL) /*!< GPDMA0 MASKSRCTRAN: CH7 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKSRCTRAN_WE_CH0_Pos \ - (8UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH0 (Bit 8) */ -#define GPDMA0_MASKSRCTRAN_WE_CH0_Msk \ - (0x100UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKSRCTRAN_WE_CH1_Pos \ - (9UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH1 (Bit 9) */ -#define GPDMA0_MASKSRCTRAN_WE_CH1_Msk \ - (0x200UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKSRCTRAN_WE_CH2_Pos \ - (10UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH2 (Bit 10) */ -#define GPDMA0_MASKSRCTRAN_WE_CH2_Msk \ - (0x400UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKSRCTRAN_WE_CH3_Pos \ - (11UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH3 (Bit 11) */ -#define GPDMA0_MASKSRCTRAN_WE_CH3_Msk \ - (0x800UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKSRCTRAN_WE_CH4_Pos \ - (12UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH4 (Bit 12) */ -#define GPDMA0_MASKSRCTRAN_WE_CH4_Msk \ - (0x1000UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKSRCTRAN_WE_CH5_Pos \ - (13UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH5 (Bit 13) */ -#define GPDMA0_MASKSRCTRAN_WE_CH5_Msk \ - (0x2000UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKSRCTRAN_WE_CH6_Pos \ - (14UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH6 (Bit 14) */ -#define GPDMA0_MASKSRCTRAN_WE_CH6_Msk \ - (0x4000UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKSRCTRAN_WE_CH7_Pos \ - (15UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH7 (Bit 15) */ -#define GPDMA0_MASKSRCTRAN_WE_CH7_Msk \ - (0x8000UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH7 (Bitfield-Mask: 0x01) */ - -/* ----------------------------- GPDMA0_MASKDSTTRAN ----------------------------- */ -#define GPDMA0_MASKDSTTRAN_CH0_Pos \ - (0UL) /*!< GPDMA0 MASKDSTTRAN: CH0 (Bit 0) */ -#define GPDMA0_MASKDSTTRAN_CH0_Msk \ - (0x1UL) /*!< GPDMA0 MASKDSTTRAN: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKDSTTRAN_CH1_Pos \ - (1UL) /*!< GPDMA0 MASKDSTTRAN: CH1 (Bit 1) */ -#define GPDMA0_MASKDSTTRAN_CH1_Msk \ - (0x2UL) /*!< GPDMA0 MASKDSTTRAN: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKDSTTRAN_CH2_Pos \ - (2UL) /*!< GPDMA0 MASKDSTTRAN: CH2 (Bit 2) */ -#define GPDMA0_MASKDSTTRAN_CH2_Msk \ - (0x4UL) /*!< GPDMA0 MASKDSTTRAN: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKDSTTRAN_CH3_Pos \ - (3UL) /*!< GPDMA0 MASKDSTTRAN: CH3 (Bit 3) */ -#define GPDMA0_MASKDSTTRAN_CH3_Msk \ - (0x8UL) /*!< GPDMA0 MASKDSTTRAN: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKDSTTRAN_CH4_Pos \ - (4UL) /*!< GPDMA0 MASKDSTTRAN: CH4 (Bit 4) */ -#define GPDMA0_MASKDSTTRAN_CH4_Msk \ - (0x10UL) /*!< GPDMA0 MASKDSTTRAN: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKDSTTRAN_CH5_Pos \ - (5UL) /*!< GPDMA0 MASKDSTTRAN: CH5 (Bit 5) */ -#define GPDMA0_MASKDSTTRAN_CH5_Msk \ - (0x20UL) /*!< GPDMA0 MASKDSTTRAN: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKDSTTRAN_CH6_Pos \ - (6UL) /*!< GPDMA0 MASKDSTTRAN: CH6 (Bit 6) */ -#define GPDMA0_MASKDSTTRAN_CH6_Msk \ - (0x40UL) /*!< GPDMA0 MASKDSTTRAN: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKDSTTRAN_CH7_Pos \ - (7UL) /*!< GPDMA0 MASKDSTTRAN: CH7 (Bit 7) */ -#define GPDMA0_MASKDSTTRAN_CH7_Msk \ - (0x80UL) /*!< GPDMA0 MASKDSTTRAN: CH7 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKDSTTRAN_WE_CH0_Pos \ - (8UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH0 (Bit 8) */ -#define GPDMA0_MASKDSTTRAN_WE_CH0_Msk \ - (0x100UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKDSTTRAN_WE_CH1_Pos \ - (9UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH1 (Bit 9) */ -#define GPDMA0_MASKDSTTRAN_WE_CH1_Msk \ - (0x200UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKDSTTRAN_WE_CH2_Pos \ - (10UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH2 (Bit 10) */ -#define GPDMA0_MASKDSTTRAN_WE_CH2_Msk \ - (0x400UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKDSTTRAN_WE_CH3_Pos \ - (11UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH3 (Bit 11) */ -#define GPDMA0_MASKDSTTRAN_WE_CH3_Msk \ - (0x800UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKDSTTRAN_WE_CH4_Pos \ - (12UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH4 (Bit 12) */ -#define GPDMA0_MASKDSTTRAN_WE_CH4_Msk \ - (0x1000UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKDSTTRAN_WE_CH5_Pos \ - (13UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH5 (Bit 13) */ -#define GPDMA0_MASKDSTTRAN_WE_CH5_Msk \ - (0x2000UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKDSTTRAN_WE_CH6_Pos \ - (14UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH6 (Bit 14) */ -#define GPDMA0_MASKDSTTRAN_WE_CH6_Msk \ - (0x4000UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKDSTTRAN_WE_CH7_Pos \ - (15UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH7 (Bit 15) */ -#define GPDMA0_MASKDSTTRAN_WE_CH7_Msk \ - (0x8000UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH7 (Bitfield-Mask: 0x01) */ - -/* ------------------------------- GPDMA0_MASKERR ------------------------------- */ -#define GPDMA0_MASKERR_CH0_Pos \ - (0UL) /*!< GPDMA0 MASKERR: CH0 (Bit 0) */ -#define GPDMA0_MASKERR_CH0_Msk \ - (0x1UL) /*!< GPDMA0 MASKERR: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKERR_CH1_Pos \ - (1UL) /*!< GPDMA0 MASKERR: CH1 (Bit 1) */ -#define GPDMA0_MASKERR_CH1_Msk \ - (0x2UL) /*!< GPDMA0 MASKERR: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKERR_CH2_Pos \ - (2UL) /*!< GPDMA0 MASKERR: CH2 (Bit 2) */ -#define GPDMA0_MASKERR_CH2_Msk \ - (0x4UL) /*!< GPDMA0 MASKERR: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKERR_CH3_Pos \ - (3UL) /*!< GPDMA0 MASKERR: CH3 (Bit 3) */ -#define GPDMA0_MASKERR_CH3_Msk \ - (0x8UL) /*!< GPDMA0 MASKERR: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKERR_CH4_Pos \ - (4UL) /*!< GPDMA0 MASKERR: CH4 (Bit 4) */ -#define GPDMA0_MASKERR_CH4_Msk \ - (0x10UL) /*!< GPDMA0 MASKERR: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKERR_CH5_Pos \ - (5UL) /*!< GPDMA0 MASKERR: CH5 (Bit 5) */ -#define GPDMA0_MASKERR_CH5_Msk \ - (0x20UL) /*!< GPDMA0 MASKERR: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKERR_CH6_Pos \ - (6UL) /*!< GPDMA0 MASKERR: CH6 (Bit 6) */ -#define GPDMA0_MASKERR_CH6_Msk \ - (0x40UL) /*!< GPDMA0 MASKERR: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKERR_CH7_Pos \ - (7UL) /*!< GPDMA0 MASKERR: CH7 (Bit 7) */ -#define GPDMA0_MASKERR_CH7_Msk \ - (0x80UL) /*!< GPDMA0 MASKERR: CH7 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKERR_WE_CH0_Pos \ - (8UL) /*!< GPDMA0 MASKERR: WE_CH0 (Bit 8) */ -#define GPDMA0_MASKERR_WE_CH0_Msk \ - (0x100UL) /*!< GPDMA0 MASKERR: WE_CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKERR_WE_CH1_Pos \ - (9UL) /*!< GPDMA0 MASKERR: WE_CH1 (Bit 9) */ -#define GPDMA0_MASKERR_WE_CH1_Msk \ - (0x200UL) /*!< GPDMA0 MASKERR: WE_CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKERR_WE_CH2_Pos \ - (10UL) /*!< GPDMA0 MASKERR: WE_CH2 (Bit 10) */ -#define GPDMA0_MASKERR_WE_CH2_Msk \ - (0x400UL) /*!< GPDMA0 MASKERR: WE_CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKERR_WE_CH3_Pos \ - (11UL) /*!< GPDMA0 MASKERR: WE_CH3 (Bit 11) */ -#define GPDMA0_MASKERR_WE_CH3_Msk \ - (0x800UL) /*!< GPDMA0 MASKERR: WE_CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKERR_WE_CH4_Pos \ - (12UL) /*!< GPDMA0 MASKERR: WE_CH4 (Bit 12) */ -#define GPDMA0_MASKERR_WE_CH4_Msk \ - (0x1000UL) /*!< GPDMA0 MASKERR: WE_CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKERR_WE_CH5_Pos \ - (13UL) /*!< GPDMA0 MASKERR: WE_CH5 (Bit 13) */ -#define GPDMA0_MASKERR_WE_CH5_Msk \ - (0x2000UL) /*!< GPDMA0 MASKERR: WE_CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKERR_WE_CH6_Pos \ - (14UL) /*!< GPDMA0 MASKERR: WE_CH6 (Bit 14) */ -#define GPDMA0_MASKERR_WE_CH6_Msk \ - (0x4000UL) /*!< GPDMA0 MASKERR: WE_CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_MASKERR_WE_CH7_Pos \ - (15UL) /*!< GPDMA0 MASKERR: WE_CH7 (Bit 15) */ -#define GPDMA0_MASKERR_WE_CH7_Msk \ - (0x8000UL) /*!< GPDMA0 MASKERR: WE_CH7 (Bitfield-Mask: 0x01) */ - -/* ------------------------------- GPDMA0_CLEARTFR ------------------------------ */ -#define GPDMA0_CLEARTFR_CH0_Pos \ - (0UL) /*!< GPDMA0 CLEARTFR: CH0 (Bit 0) */ -#define GPDMA0_CLEARTFR_CH0_Msk \ - (0x1UL) /*!< GPDMA0 CLEARTFR: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARTFR_CH1_Pos \ - (1UL) /*!< GPDMA0 CLEARTFR: CH1 (Bit 1) */ -#define GPDMA0_CLEARTFR_CH1_Msk \ - (0x2UL) /*!< GPDMA0 CLEARTFR: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARTFR_CH2_Pos \ - (2UL) /*!< GPDMA0 CLEARTFR: CH2 (Bit 2) */ -#define GPDMA0_CLEARTFR_CH2_Msk \ - (0x4UL) /*!< GPDMA0 CLEARTFR: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARTFR_CH3_Pos \ - (3UL) /*!< GPDMA0 CLEARTFR: CH3 (Bit 3) */ -#define GPDMA0_CLEARTFR_CH3_Msk \ - (0x8UL) /*!< GPDMA0 CLEARTFR: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARTFR_CH4_Pos \ - (4UL) /*!< GPDMA0 CLEARTFR: CH4 (Bit 4) */ -#define GPDMA0_CLEARTFR_CH4_Msk \ - (0x10UL) /*!< GPDMA0 CLEARTFR: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARTFR_CH5_Pos \ - (5UL) /*!< GPDMA0 CLEARTFR: CH5 (Bit 5) */ -#define GPDMA0_CLEARTFR_CH5_Msk \ - (0x20UL) /*!< GPDMA0 CLEARTFR: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARTFR_CH6_Pos \ - (6UL) /*!< GPDMA0 CLEARTFR: CH6 (Bit 6) */ -#define GPDMA0_CLEARTFR_CH6_Msk \ - (0x40UL) /*!< GPDMA0 CLEARTFR: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARTFR_CH7_Pos \ - (7UL) /*!< GPDMA0 CLEARTFR: CH7 (Bit 7) */ -#define GPDMA0_CLEARTFR_CH7_Msk \ - (0x80UL) /*!< GPDMA0 CLEARTFR: CH7 (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPDMA0_CLEARBLOCK ----------------------------- */ -#define GPDMA0_CLEARBLOCK_CH0_Pos \ - (0UL) /*!< GPDMA0 CLEARBLOCK: CH0 (Bit 0) */ -#define GPDMA0_CLEARBLOCK_CH0_Msk \ - (0x1UL) /*!< GPDMA0 CLEARBLOCK: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARBLOCK_CH1_Pos \ - (1UL) /*!< GPDMA0 CLEARBLOCK: CH1 (Bit 1) */ -#define GPDMA0_CLEARBLOCK_CH1_Msk \ - (0x2UL) /*!< GPDMA0 CLEARBLOCK: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARBLOCK_CH2_Pos \ - (2UL) /*!< GPDMA0 CLEARBLOCK: CH2 (Bit 2) */ -#define GPDMA0_CLEARBLOCK_CH2_Msk \ - (0x4UL) /*!< GPDMA0 CLEARBLOCK: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARBLOCK_CH3_Pos \ - (3UL) /*!< GPDMA0 CLEARBLOCK: CH3 (Bit 3) */ -#define GPDMA0_CLEARBLOCK_CH3_Msk \ - (0x8UL) /*!< GPDMA0 CLEARBLOCK: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARBLOCK_CH4_Pos \ - (4UL) /*!< GPDMA0 CLEARBLOCK: CH4 (Bit 4) */ -#define GPDMA0_CLEARBLOCK_CH4_Msk \ - (0x10UL) /*!< GPDMA0 CLEARBLOCK: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARBLOCK_CH5_Pos \ - (5UL) /*!< GPDMA0 CLEARBLOCK: CH5 (Bit 5) */ -#define GPDMA0_CLEARBLOCK_CH5_Msk \ - (0x20UL) /*!< GPDMA0 CLEARBLOCK: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARBLOCK_CH6_Pos \ - (6UL) /*!< GPDMA0 CLEARBLOCK: CH6 (Bit 6) */ -#define GPDMA0_CLEARBLOCK_CH6_Msk \ - (0x40UL) /*!< GPDMA0 CLEARBLOCK: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARBLOCK_CH7_Pos \ - (7UL) /*!< GPDMA0 CLEARBLOCK: CH7 (Bit 7) */ -#define GPDMA0_CLEARBLOCK_CH7_Msk \ - (0x80UL) /*!< GPDMA0 CLEARBLOCK: CH7 (Bitfield-Mask: 0x01) */ - -/* ----------------------------- GPDMA0_CLEARSRCTRAN ---------------------------- */ -#define GPDMA0_CLEARSRCTRAN_CH0_Pos \ - (0UL) /*!< GPDMA0 CLEARSRCTRAN: CH0 (Bit 0) */ -#define GPDMA0_CLEARSRCTRAN_CH0_Msk \ - (0x1UL) /*!< GPDMA0 CLEARSRCTRAN: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARSRCTRAN_CH1_Pos \ - (1UL) /*!< GPDMA0 CLEARSRCTRAN: CH1 (Bit 1) */ -#define GPDMA0_CLEARSRCTRAN_CH1_Msk \ - (0x2UL) /*!< GPDMA0 CLEARSRCTRAN: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARSRCTRAN_CH2_Pos \ - (2UL) /*!< GPDMA0 CLEARSRCTRAN: CH2 (Bit 2) */ -#define GPDMA0_CLEARSRCTRAN_CH2_Msk \ - (0x4UL) /*!< GPDMA0 CLEARSRCTRAN: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARSRCTRAN_CH3_Pos \ - (3UL) /*!< GPDMA0 CLEARSRCTRAN: CH3 (Bit 3) */ -#define GPDMA0_CLEARSRCTRAN_CH3_Msk \ - (0x8UL) /*!< GPDMA0 CLEARSRCTRAN: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARSRCTRAN_CH4_Pos \ - (4UL) /*!< GPDMA0 CLEARSRCTRAN: CH4 (Bit 4) */ -#define GPDMA0_CLEARSRCTRAN_CH4_Msk \ - (0x10UL) /*!< GPDMA0 CLEARSRCTRAN: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARSRCTRAN_CH5_Pos \ - (5UL) /*!< GPDMA0 CLEARSRCTRAN: CH5 (Bit 5) */ -#define GPDMA0_CLEARSRCTRAN_CH5_Msk \ - (0x20UL) /*!< GPDMA0 CLEARSRCTRAN: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARSRCTRAN_CH6_Pos \ - (6UL) /*!< GPDMA0 CLEARSRCTRAN: CH6 (Bit 6) */ -#define GPDMA0_CLEARSRCTRAN_CH6_Msk \ - (0x40UL) /*!< GPDMA0 CLEARSRCTRAN: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARSRCTRAN_CH7_Pos \ - (7UL) /*!< GPDMA0 CLEARSRCTRAN: CH7 (Bit 7) */ -#define GPDMA0_CLEARSRCTRAN_CH7_Msk \ - (0x80UL) /*!< GPDMA0 CLEARSRCTRAN: CH7 (Bitfield-Mask: 0x01) */ - -/* ----------------------------- GPDMA0_CLEARDSTTRAN ---------------------------- */ -#define GPDMA0_CLEARDSTTRAN_CH0_Pos \ - (0UL) /*!< GPDMA0 CLEARDSTTRAN: CH0 (Bit 0) */ -#define GPDMA0_CLEARDSTTRAN_CH0_Msk \ - (0x1UL) /*!< GPDMA0 CLEARDSTTRAN: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARDSTTRAN_CH1_Pos \ - (1UL) /*!< GPDMA0 CLEARDSTTRAN: CH1 (Bit 1) */ -#define GPDMA0_CLEARDSTTRAN_CH1_Msk \ - (0x2UL) /*!< GPDMA0 CLEARDSTTRAN: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARDSTTRAN_CH2_Pos \ - (2UL) /*!< GPDMA0 CLEARDSTTRAN: CH2 (Bit 2) */ -#define GPDMA0_CLEARDSTTRAN_CH2_Msk \ - (0x4UL) /*!< GPDMA0 CLEARDSTTRAN: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARDSTTRAN_CH3_Pos \ - (3UL) /*!< GPDMA0 CLEARDSTTRAN: CH3 (Bit 3) */ -#define GPDMA0_CLEARDSTTRAN_CH3_Msk \ - (0x8UL) /*!< GPDMA0 CLEARDSTTRAN: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARDSTTRAN_CH4_Pos \ - (4UL) /*!< GPDMA0 CLEARDSTTRAN: CH4 (Bit 4) */ -#define GPDMA0_CLEARDSTTRAN_CH4_Msk \ - (0x10UL) /*!< GPDMA0 CLEARDSTTRAN: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARDSTTRAN_CH5_Pos \ - (5UL) /*!< GPDMA0 CLEARDSTTRAN: CH5 (Bit 5) */ -#define GPDMA0_CLEARDSTTRAN_CH5_Msk \ - (0x20UL) /*!< GPDMA0 CLEARDSTTRAN: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARDSTTRAN_CH6_Pos \ - (6UL) /*!< GPDMA0 CLEARDSTTRAN: CH6 (Bit 6) */ -#define GPDMA0_CLEARDSTTRAN_CH6_Msk \ - (0x40UL) /*!< GPDMA0 CLEARDSTTRAN: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARDSTTRAN_CH7_Pos \ - (7UL) /*!< GPDMA0 CLEARDSTTRAN: CH7 (Bit 7) */ -#define GPDMA0_CLEARDSTTRAN_CH7_Msk \ - (0x80UL) /*!< GPDMA0 CLEARDSTTRAN: CH7 (Bitfield-Mask: 0x01) */ - -/* ------------------------------- GPDMA0_CLEARERR ------------------------------ */ -#define GPDMA0_CLEARERR_CH0_Pos \ - (0UL) /*!< GPDMA0 CLEARERR: CH0 (Bit 0) */ -#define GPDMA0_CLEARERR_CH0_Msk \ - (0x1UL) /*!< GPDMA0 CLEARERR: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARERR_CH1_Pos \ - (1UL) /*!< GPDMA0 CLEARERR: CH1 (Bit 1) */ -#define GPDMA0_CLEARERR_CH1_Msk \ - (0x2UL) /*!< GPDMA0 CLEARERR: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARERR_CH2_Pos \ - (2UL) /*!< GPDMA0 CLEARERR: CH2 (Bit 2) */ -#define GPDMA0_CLEARERR_CH2_Msk \ - (0x4UL) /*!< GPDMA0 CLEARERR: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARERR_CH3_Pos \ - (3UL) /*!< GPDMA0 CLEARERR: CH3 (Bit 3) */ -#define GPDMA0_CLEARERR_CH3_Msk \ - (0x8UL) /*!< GPDMA0 CLEARERR: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARERR_CH4_Pos \ - (4UL) /*!< GPDMA0 CLEARERR: CH4 (Bit 4) */ -#define GPDMA0_CLEARERR_CH4_Msk \ - (0x10UL) /*!< GPDMA0 CLEARERR: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARERR_CH5_Pos \ - (5UL) /*!< GPDMA0 CLEARERR: CH5 (Bit 5) */ -#define GPDMA0_CLEARERR_CH5_Msk \ - (0x20UL) /*!< GPDMA0 CLEARERR: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARERR_CH6_Pos \ - (6UL) /*!< GPDMA0 CLEARERR: CH6 (Bit 6) */ -#define GPDMA0_CLEARERR_CH6_Msk \ - (0x40UL) /*!< GPDMA0 CLEARERR: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_CLEARERR_CH7_Pos \ - (7UL) /*!< GPDMA0 CLEARERR: CH7 (Bit 7) */ -#define GPDMA0_CLEARERR_CH7_Msk \ - (0x80UL) /*!< GPDMA0 CLEARERR: CH7 (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPDMA0_STATUSINT ------------------------------ */ -#define GPDMA0_STATUSINT_TFR_Pos \ - (0UL) /*!< GPDMA0 STATUSINT: TFR (Bit 0) */ -#define GPDMA0_STATUSINT_TFR_Msk \ - (0x1UL) /*!< GPDMA0 STATUSINT: TFR (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSINT_BLOCK_Pos \ - (1UL) /*!< GPDMA0 STATUSINT: BLOCK (Bit 1) */ -#define GPDMA0_STATUSINT_BLOCK_Msk \ - (0x2UL) /*!< GPDMA0 STATUSINT: BLOCK (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSINT_SRCT_Pos \ - (2UL) /*!< GPDMA0 STATUSINT: SRCT (Bit 2) */ -#define GPDMA0_STATUSINT_SRCT_Msk \ - (0x4UL) /*!< GPDMA0 STATUSINT: SRCT (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSINT_DSTT_Pos \ - (3UL) /*!< GPDMA0 STATUSINT: DSTT (Bit 3) */ -#define GPDMA0_STATUSINT_DSTT_Msk \ - (0x8UL) /*!< GPDMA0 STATUSINT: DSTT (Bitfield-Mask: 0x01) */ -#define GPDMA0_STATUSINT_ERR_Pos \ - (4UL) /*!< GPDMA0 STATUSINT: ERR (Bit 4) */ -#define GPDMA0_STATUSINT_ERR_Msk \ - (0x10UL) /*!< GPDMA0 STATUSINT: ERR (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPDMA0_REQSRCREG ------------------------------ */ -#define GPDMA0_REQSRCREG_CH0_Pos \ - (0UL) /*!< GPDMA0 REQSRCREG: CH0 (Bit 0) */ -#define GPDMA0_REQSRCREG_CH0_Msk \ - (0x1UL) /*!< GPDMA0 REQSRCREG: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQSRCREG_CH1_Pos \ - (1UL) /*!< GPDMA0 REQSRCREG: CH1 (Bit 1) */ -#define GPDMA0_REQSRCREG_CH1_Msk \ - (0x2UL) /*!< GPDMA0 REQSRCREG: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQSRCREG_CH2_Pos \ - (2UL) /*!< GPDMA0 REQSRCREG: CH2 (Bit 2) */ -#define GPDMA0_REQSRCREG_CH2_Msk \ - (0x4UL) /*!< GPDMA0 REQSRCREG: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQSRCREG_CH3_Pos \ - (3UL) /*!< GPDMA0 REQSRCREG: CH3 (Bit 3) */ -#define GPDMA0_REQSRCREG_CH3_Msk \ - (0x8UL) /*!< GPDMA0 REQSRCREG: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQSRCREG_CH4_Pos \ - (4UL) /*!< GPDMA0 REQSRCREG: CH4 (Bit 4) */ -#define GPDMA0_REQSRCREG_CH4_Msk \ - (0x10UL) /*!< GPDMA0 REQSRCREG: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQSRCREG_CH5_Pos \ - (5UL) /*!< GPDMA0 REQSRCREG: CH5 (Bit 5) */ -#define GPDMA0_REQSRCREG_CH5_Msk \ - (0x20UL) /*!< GPDMA0 REQSRCREG: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQSRCREG_CH6_Pos \ - (6UL) /*!< GPDMA0 REQSRCREG: CH6 (Bit 6) */ -#define GPDMA0_REQSRCREG_CH6_Msk \ - (0x40UL) /*!< GPDMA0 REQSRCREG: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQSRCREG_CH7_Pos \ - (7UL) /*!< GPDMA0 REQSRCREG: CH7 (Bit 7) */ -#define GPDMA0_REQSRCREG_CH7_Msk \ - (0x80UL) /*!< GPDMA0 REQSRCREG: CH7 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQSRCREG_WE_CH0_Pos \ - (8UL) /*!< GPDMA0 REQSRCREG: WE_CH0 (Bit 8) */ -#define GPDMA0_REQSRCREG_WE_CH0_Msk \ - (0x100UL) /*!< GPDMA0 REQSRCREG: WE_CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQSRCREG_WE_CH1_Pos \ - (9UL) /*!< GPDMA0 REQSRCREG: WE_CH1 (Bit 9) */ -#define GPDMA0_REQSRCREG_WE_CH1_Msk \ - (0x200UL) /*!< GPDMA0 REQSRCREG: WE_CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQSRCREG_WE_CH2_Pos \ - (10UL) /*!< GPDMA0 REQSRCREG: WE_CH2 (Bit 10) */ -#define GPDMA0_REQSRCREG_WE_CH2_Msk \ - (0x400UL) /*!< GPDMA0 REQSRCREG: WE_CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQSRCREG_WE_CH3_Pos \ - (11UL) /*!< GPDMA0 REQSRCREG: WE_CH3 (Bit 11) */ -#define GPDMA0_REQSRCREG_WE_CH3_Msk \ - (0x800UL) /*!< GPDMA0 REQSRCREG: WE_CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQSRCREG_WE_CH4_Pos \ - (12UL) /*!< GPDMA0 REQSRCREG: WE_CH4 (Bit 12) */ -#define GPDMA0_REQSRCREG_WE_CH4_Msk \ - (0x1000UL) /*!< GPDMA0 REQSRCREG: WE_CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQSRCREG_WE_CH5_Pos \ - (13UL) /*!< GPDMA0 REQSRCREG: WE_CH5 (Bit 13) */ -#define GPDMA0_REQSRCREG_WE_CH5_Msk \ - (0x2000UL) /*!< GPDMA0 REQSRCREG: WE_CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQSRCREG_WE_CH6_Pos \ - (14UL) /*!< GPDMA0 REQSRCREG: WE_CH6 (Bit 14) */ -#define GPDMA0_REQSRCREG_WE_CH6_Msk \ - (0x4000UL) /*!< GPDMA0 REQSRCREG: WE_CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQSRCREG_WE_CH7_Pos \ - (15UL) /*!< GPDMA0 REQSRCREG: WE_CH7 (Bit 15) */ -#define GPDMA0_REQSRCREG_WE_CH7_Msk \ - (0x8000UL) /*!< GPDMA0 REQSRCREG: WE_CH7 (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPDMA0_REQDSTREG ------------------------------ */ -#define GPDMA0_REQDSTREG_CH0_Pos \ - (0UL) /*!< GPDMA0 REQDSTREG: CH0 (Bit 0) */ -#define GPDMA0_REQDSTREG_CH0_Msk \ - (0x1UL) /*!< GPDMA0 REQDSTREG: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQDSTREG_CH1_Pos \ - (1UL) /*!< GPDMA0 REQDSTREG: CH1 (Bit 1) */ -#define GPDMA0_REQDSTREG_CH1_Msk \ - (0x2UL) /*!< GPDMA0 REQDSTREG: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQDSTREG_CH2_Pos \ - (2UL) /*!< GPDMA0 REQDSTREG: CH2 (Bit 2) */ -#define GPDMA0_REQDSTREG_CH2_Msk \ - (0x4UL) /*!< GPDMA0 REQDSTREG: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQDSTREG_CH3_Pos \ - (3UL) /*!< GPDMA0 REQDSTREG: CH3 (Bit 3) */ -#define GPDMA0_REQDSTREG_CH3_Msk \ - (0x8UL) /*!< GPDMA0 REQDSTREG: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQDSTREG_CH4_Pos \ - (4UL) /*!< GPDMA0 REQDSTREG: CH4 (Bit 4) */ -#define GPDMA0_REQDSTREG_CH4_Msk \ - (0x10UL) /*!< GPDMA0 REQDSTREG: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQDSTREG_CH5_Pos \ - (5UL) /*!< GPDMA0 REQDSTREG: CH5 (Bit 5) */ -#define GPDMA0_REQDSTREG_CH5_Msk \ - (0x20UL) /*!< GPDMA0 REQDSTREG: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQDSTREG_CH6_Pos \ - (6UL) /*!< GPDMA0 REQDSTREG: CH6 (Bit 6) */ -#define GPDMA0_REQDSTREG_CH6_Msk \ - (0x40UL) /*!< GPDMA0 REQDSTREG: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQDSTREG_CH7_Pos \ - (7UL) /*!< GPDMA0 REQDSTREG: CH7 (Bit 7) */ -#define GPDMA0_REQDSTREG_CH7_Msk \ - (0x80UL) /*!< GPDMA0 REQDSTREG: CH7 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQDSTREG_WE_CH0_Pos \ - (8UL) /*!< GPDMA0 REQDSTREG: WE_CH0 (Bit 8) */ -#define GPDMA0_REQDSTREG_WE_CH0_Msk \ - (0x100UL) /*!< GPDMA0 REQDSTREG: WE_CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQDSTREG_WE_CH1_Pos \ - (9UL) /*!< GPDMA0 REQDSTREG: WE_CH1 (Bit 9) */ -#define GPDMA0_REQDSTREG_WE_CH1_Msk \ - (0x200UL) /*!< GPDMA0 REQDSTREG: WE_CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQDSTREG_WE_CH2_Pos \ - (10UL) /*!< GPDMA0 REQDSTREG: WE_CH2 (Bit 10) */ -#define GPDMA0_REQDSTREG_WE_CH2_Msk \ - (0x400UL) /*!< GPDMA0 REQDSTREG: WE_CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQDSTREG_WE_CH3_Pos \ - (11UL) /*!< GPDMA0 REQDSTREG: WE_CH3 (Bit 11) */ -#define GPDMA0_REQDSTREG_WE_CH3_Msk \ - (0x800UL) /*!< GPDMA0 REQDSTREG: WE_CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQDSTREG_WE_CH4_Pos \ - (12UL) /*!< GPDMA0 REQDSTREG: WE_CH4 (Bit 12) */ -#define GPDMA0_REQDSTREG_WE_CH4_Msk \ - (0x1000UL) /*!< GPDMA0 REQDSTREG: WE_CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQDSTREG_WE_CH5_Pos \ - (13UL) /*!< GPDMA0 REQDSTREG: WE_CH5 (Bit 13) */ -#define GPDMA0_REQDSTREG_WE_CH5_Msk \ - (0x2000UL) /*!< GPDMA0 REQDSTREG: WE_CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQDSTREG_WE_CH6_Pos \ - (14UL) /*!< GPDMA0 REQDSTREG: WE_CH6 (Bit 14) */ -#define GPDMA0_REQDSTREG_WE_CH6_Msk \ - (0x4000UL) /*!< GPDMA0 REQDSTREG: WE_CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_REQDSTREG_WE_CH7_Pos \ - (15UL) /*!< GPDMA0 REQDSTREG: WE_CH7 (Bit 15) */ -#define GPDMA0_REQDSTREG_WE_CH7_Msk \ - (0x8000UL) /*!< GPDMA0 REQDSTREG: WE_CH7 (Bitfield-Mask: 0x01) */ - -/* ----------------------------- GPDMA0_SGLREQSRCREG ---------------------------- */ -#define GPDMA0_SGLREQSRCREG_CH0_Pos \ - (0UL) /*!< GPDMA0 SGLREQSRCREG: CH0 (Bit 0) */ -#define GPDMA0_SGLREQSRCREG_CH0_Msk \ - (0x1UL) /*!< GPDMA0 SGLREQSRCREG: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQSRCREG_CH1_Pos \ - (1UL) /*!< GPDMA0 SGLREQSRCREG: CH1 (Bit 1) */ -#define GPDMA0_SGLREQSRCREG_CH1_Msk \ - (0x2UL) /*!< GPDMA0 SGLREQSRCREG: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQSRCREG_CH2_Pos \ - (2UL) /*!< GPDMA0 SGLREQSRCREG: CH2 (Bit 2) */ -#define GPDMA0_SGLREQSRCREG_CH2_Msk \ - (0x4UL) /*!< GPDMA0 SGLREQSRCREG: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQSRCREG_CH3_Pos \ - (3UL) /*!< GPDMA0 SGLREQSRCREG: CH3 (Bit 3) */ -#define GPDMA0_SGLREQSRCREG_CH3_Msk \ - (0x8UL) /*!< GPDMA0 SGLREQSRCREG: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQSRCREG_CH4_Pos \ - (4UL) /*!< GPDMA0 SGLREQSRCREG: CH4 (Bit 4) */ -#define GPDMA0_SGLREQSRCREG_CH4_Msk \ - (0x10UL) /*!< GPDMA0 SGLREQSRCREG: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQSRCREG_CH5_Pos \ - (5UL) /*!< GPDMA0 SGLREQSRCREG: CH5 (Bit 5) */ -#define GPDMA0_SGLREQSRCREG_CH5_Msk \ - (0x20UL) /*!< GPDMA0 SGLREQSRCREG: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQSRCREG_CH6_Pos \ - (6UL) /*!< GPDMA0 SGLREQSRCREG: CH6 (Bit 6) */ -#define GPDMA0_SGLREQSRCREG_CH6_Msk \ - (0x40UL) /*!< GPDMA0 SGLREQSRCREG: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQSRCREG_CH7_Pos \ - (7UL) /*!< GPDMA0 SGLREQSRCREG: CH7 (Bit 7) */ -#define GPDMA0_SGLREQSRCREG_CH7_Msk \ - (0x80UL) /*!< GPDMA0 SGLREQSRCREG: CH7 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQSRCREG_WE_CH0_Pos \ - (8UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH0 (Bit 8) */ -#define GPDMA0_SGLREQSRCREG_WE_CH0_Msk \ - (0x100UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQSRCREG_WE_CH1_Pos \ - (9UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH1 (Bit 9) */ -#define GPDMA0_SGLREQSRCREG_WE_CH1_Msk \ - (0x200UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQSRCREG_WE_CH2_Pos \ - (10UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH2 (Bit 10) */ -#define GPDMA0_SGLREQSRCREG_WE_CH2_Msk \ - (0x400UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQSRCREG_WE_CH3_Pos \ - (11UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH3 (Bit 11) */ -#define GPDMA0_SGLREQSRCREG_WE_CH3_Msk \ - (0x800UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQSRCREG_WE_CH4_Pos \ - (12UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH4 (Bit 12) */ -#define GPDMA0_SGLREQSRCREG_WE_CH4_Msk \ - (0x1000UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQSRCREG_WE_CH5_Pos \ - (13UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH5 (Bit 13) */ -#define GPDMA0_SGLREQSRCREG_WE_CH5_Msk \ - (0x2000UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQSRCREG_WE_CH6_Pos \ - (14UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH6 (Bit 14) */ -#define GPDMA0_SGLREQSRCREG_WE_CH6_Msk \ - (0x4000UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQSRCREG_WE_CH7_Pos \ - (15UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH7 (Bit 15) */ -#define GPDMA0_SGLREQSRCREG_WE_CH7_Msk \ - (0x8000UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH7 (Bitfield-Mask: 0x01) */ - -/* ----------------------------- GPDMA0_SGLREQDSTREG ---------------------------- */ -#define GPDMA0_SGLREQDSTREG_CH0_Pos \ - (0UL) /*!< GPDMA0 SGLREQDSTREG: CH0 (Bit 0) */ -#define GPDMA0_SGLREQDSTREG_CH0_Msk \ - (0x1UL) /*!< GPDMA0 SGLREQDSTREG: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQDSTREG_CH1_Pos \ - (1UL) /*!< GPDMA0 SGLREQDSTREG: CH1 (Bit 1) */ -#define GPDMA0_SGLREQDSTREG_CH1_Msk \ - (0x2UL) /*!< GPDMA0 SGLREQDSTREG: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQDSTREG_CH2_Pos \ - (2UL) /*!< GPDMA0 SGLREQDSTREG: CH2 (Bit 2) */ -#define GPDMA0_SGLREQDSTREG_CH2_Msk \ - (0x4UL) /*!< GPDMA0 SGLREQDSTREG: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQDSTREG_CH3_Pos \ - (3UL) /*!< GPDMA0 SGLREQDSTREG: CH3 (Bit 3) */ -#define GPDMA0_SGLREQDSTREG_CH3_Msk \ - (0x8UL) /*!< GPDMA0 SGLREQDSTREG: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQDSTREG_CH4_Pos \ - (4UL) /*!< GPDMA0 SGLREQDSTREG: CH4 (Bit 4) */ -#define GPDMA0_SGLREQDSTREG_CH4_Msk \ - (0x10UL) /*!< GPDMA0 SGLREQDSTREG: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQDSTREG_CH5_Pos \ - (5UL) /*!< GPDMA0 SGLREQDSTREG: CH5 (Bit 5) */ -#define GPDMA0_SGLREQDSTREG_CH5_Msk \ - (0x20UL) /*!< GPDMA0 SGLREQDSTREG: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQDSTREG_CH6_Pos \ - (6UL) /*!< GPDMA0 SGLREQDSTREG: CH6 (Bit 6) */ -#define GPDMA0_SGLREQDSTREG_CH6_Msk \ - (0x40UL) /*!< GPDMA0 SGLREQDSTREG: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQDSTREG_CH7_Pos \ - (7UL) /*!< GPDMA0 SGLREQDSTREG: CH7 (Bit 7) */ -#define GPDMA0_SGLREQDSTREG_CH7_Msk \ - (0x80UL) /*!< GPDMA0 SGLREQDSTREG: CH7 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQDSTREG_WE_CH0_Pos \ - (8UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH0 (Bit 8) */ -#define GPDMA0_SGLREQDSTREG_WE_CH0_Msk \ - (0x100UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQDSTREG_WE_CH1_Pos \ - (9UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH1 (Bit 9) */ -#define GPDMA0_SGLREQDSTREG_WE_CH1_Msk \ - (0x200UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQDSTREG_WE_CH2_Pos \ - (10UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH2 (Bit 10) */ -#define GPDMA0_SGLREQDSTREG_WE_CH2_Msk \ - (0x400UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQDSTREG_WE_CH3_Pos \ - (11UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH3 (Bit 11) */ -#define GPDMA0_SGLREQDSTREG_WE_CH3_Msk \ - (0x800UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQDSTREG_WE_CH4_Pos \ - (12UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH4 (Bit 12) */ -#define GPDMA0_SGLREQDSTREG_WE_CH4_Msk \ - (0x1000UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQDSTREG_WE_CH5_Pos \ - (13UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH5 (Bit 13) */ -#define GPDMA0_SGLREQDSTREG_WE_CH5_Msk \ - (0x2000UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQDSTREG_WE_CH6_Pos \ - (14UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH6 (Bit 14) */ -#define GPDMA0_SGLREQDSTREG_WE_CH6_Msk \ - (0x4000UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_SGLREQDSTREG_WE_CH7_Pos \ - (15UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH7 (Bit 15) */ -#define GPDMA0_SGLREQDSTREG_WE_CH7_Msk \ - (0x8000UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH7 (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPDMA0_LSTSRCREG ------------------------------ */ -#define GPDMA0_LSTSRCREG_CH0_Pos \ - (0UL) /*!< GPDMA0 LSTSRCREG: CH0 (Bit 0) */ -#define GPDMA0_LSTSRCREG_CH0_Msk \ - (0x1UL) /*!< GPDMA0 LSTSRCREG: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTSRCREG_CH1_Pos \ - (1UL) /*!< GPDMA0 LSTSRCREG: CH1 (Bit 1) */ -#define GPDMA0_LSTSRCREG_CH1_Msk \ - (0x2UL) /*!< GPDMA0 LSTSRCREG: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTSRCREG_CH2_Pos \ - (2UL) /*!< GPDMA0 LSTSRCREG: CH2 (Bit 2) */ -#define GPDMA0_LSTSRCREG_CH2_Msk \ - (0x4UL) /*!< GPDMA0 LSTSRCREG: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTSRCREG_CH3_Pos \ - (3UL) /*!< GPDMA0 LSTSRCREG: CH3 (Bit 3) */ -#define GPDMA0_LSTSRCREG_CH3_Msk \ - (0x8UL) /*!< GPDMA0 LSTSRCREG: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTSRCREG_CH4_Pos \ - (4UL) /*!< GPDMA0 LSTSRCREG: CH4 (Bit 4) */ -#define GPDMA0_LSTSRCREG_CH4_Msk \ - (0x10UL) /*!< GPDMA0 LSTSRCREG: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTSRCREG_CH5_Pos \ - (5UL) /*!< GPDMA0 LSTSRCREG: CH5 (Bit 5) */ -#define GPDMA0_LSTSRCREG_CH5_Msk \ - (0x20UL) /*!< GPDMA0 LSTSRCREG: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTSRCREG_CH6_Pos \ - (6UL) /*!< GPDMA0 LSTSRCREG: CH6 (Bit 6) */ -#define GPDMA0_LSTSRCREG_CH6_Msk \ - (0x40UL) /*!< GPDMA0 LSTSRCREG: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTSRCREG_CH7_Pos \ - (7UL) /*!< GPDMA0 LSTSRCREG: CH7 (Bit 7) */ -#define GPDMA0_LSTSRCREG_CH7_Msk \ - (0x80UL) /*!< GPDMA0 LSTSRCREG: CH7 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTSRCREG_WE_CH0_Pos \ - (8UL) /*!< GPDMA0 LSTSRCREG: WE_CH0 (Bit 8) */ -#define GPDMA0_LSTSRCREG_WE_CH0_Msk \ - (0x100UL) /*!< GPDMA0 LSTSRCREG: WE_CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTSRCREG_WE_CH1_Pos \ - (9UL) /*!< GPDMA0 LSTSRCREG: WE_CH1 (Bit 9) */ -#define GPDMA0_LSTSRCREG_WE_CH1_Msk \ - (0x200UL) /*!< GPDMA0 LSTSRCREG: WE_CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTSRCREG_WE_CH2_Pos \ - (10UL) /*!< GPDMA0 LSTSRCREG: WE_CH2 (Bit 10) */ -#define GPDMA0_LSTSRCREG_WE_CH2_Msk \ - (0x400UL) /*!< GPDMA0 LSTSRCREG: WE_CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTSRCREG_WE_CH3_Pos \ - (11UL) /*!< GPDMA0 LSTSRCREG: WE_CH3 (Bit 11) */ -#define GPDMA0_LSTSRCREG_WE_CH3_Msk \ - (0x800UL) /*!< GPDMA0 LSTSRCREG: WE_CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTSRCREG_WE_CH4_Pos \ - (12UL) /*!< GPDMA0 LSTSRCREG: WE_CH4 (Bit 12) */ -#define GPDMA0_LSTSRCREG_WE_CH4_Msk \ - (0x1000UL) /*!< GPDMA0 LSTSRCREG: WE_CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTSRCREG_WE_CH5_Pos \ - (13UL) /*!< GPDMA0 LSTSRCREG: WE_CH5 (Bit 13) */ -#define GPDMA0_LSTSRCREG_WE_CH5_Msk \ - (0x2000UL) /*!< GPDMA0 LSTSRCREG: WE_CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTSRCREG_WE_CH6_Pos \ - (14UL) /*!< GPDMA0 LSTSRCREG: WE_CH6 (Bit 14) */ -#define GPDMA0_LSTSRCREG_WE_CH6_Msk \ - (0x4000UL) /*!< GPDMA0 LSTSRCREG: WE_CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTSRCREG_WE_CH7_Pos \ - (15UL) /*!< GPDMA0 LSTSRCREG: WE_CH7 (Bit 15) */ -#define GPDMA0_LSTSRCREG_WE_CH7_Msk \ - (0x8000UL) /*!< GPDMA0 LSTSRCREG: WE_CH7 (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPDMA0_LSTDSTREG ------------------------------ */ -#define GPDMA0_LSTDSTREG_CH0_Pos \ - (0UL) /*!< GPDMA0 LSTDSTREG: CH0 (Bit 0) */ -#define GPDMA0_LSTDSTREG_CH0_Msk \ - (0x1UL) /*!< GPDMA0 LSTDSTREG: CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTDSTREG_CH1_Pos \ - (1UL) /*!< GPDMA0 LSTDSTREG: CH1 (Bit 1) */ -#define GPDMA0_LSTDSTREG_CH1_Msk \ - (0x2UL) /*!< GPDMA0 LSTDSTREG: CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTDSTREG_CH2_Pos \ - (2UL) /*!< GPDMA0 LSTDSTREG: CH2 (Bit 2) */ -#define GPDMA0_LSTDSTREG_CH2_Msk \ - (0x4UL) /*!< GPDMA0 LSTDSTREG: CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTDSTREG_CH3_Pos \ - (3UL) /*!< GPDMA0 LSTDSTREG: CH3 (Bit 3) */ -#define GPDMA0_LSTDSTREG_CH3_Msk \ - (0x8UL) /*!< GPDMA0 LSTDSTREG: CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTDSTREG_CH4_Pos \ - (4UL) /*!< GPDMA0 LSTDSTREG: CH4 (Bit 4) */ -#define GPDMA0_LSTDSTREG_CH4_Msk \ - (0x10UL) /*!< GPDMA0 LSTDSTREG: CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTDSTREG_CH5_Pos \ - (5UL) /*!< GPDMA0 LSTDSTREG: CH5 (Bit 5) */ -#define GPDMA0_LSTDSTREG_CH5_Msk \ - (0x20UL) /*!< GPDMA0 LSTDSTREG: CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTDSTREG_CH6_Pos \ - (6UL) /*!< GPDMA0 LSTDSTREG: CH6 (Bit 6) */ -#define GPDMA0_LSTDSTREG_CH6_Msk \ - (0x40UL) /*!< GPDMA0 LSTDSTREG: CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTDSTREG_CH7_Pos \ - (7UL) /*!< GPDMA0 LSTDSTREG: CH7 (Bit 7) */ -#define GPDMA0_LSTDSTREG_CH7_Msk \ - (0x80UL) /*!< GPDMA0 LSTDSTREG: CH7 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTDSTREG_WE_CH0_Pos \ - (8UL) /*!< GPDMA0 LSTDSTREG: WE_CH0 (Bit 8) */ -#define GPDMA0_LSTDSTREG_WE_CH0_Msk \ - (0x100UL) /*!< GPDMA0 LSTDSTREG: WE_CH0 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTDSTREG_WE_CH1_Pos \ - (9UL) /*!< GPDMA0 LSTDSTREG: WE_CH1 (Bit 9) */ -#define GPDMA0_LSTDSTREG_WE_CH1_Msk \ - (0x200UL) /*!< GPDMA0 LSTDSTREG: WE_CH1 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTDSTREG_WE_CH2_Pos \ - (10UL) /*!< GPDMA0 LSTDSTREG: WE_CH2 (Bit 10) */ -#define GPDMA0_LSTDSTREG_WE_CH2_Msk \ - (0x400UL) /*!< GPDMA0 LSTDSTREG: WE_CH2 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTDSTREG_WE_CH3_Pos \ - (11UL) /*!< GPDMA0 LSTDSTREG: WE_CH3 (Bit 11) */ -#define GPDMA0_LSTDSTREG_WE_CH3_Msk \ - (0x800UL) /*!< GPDMA0 LSTDSTREG: WE_CH3 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTDSTREG_WE_CH4_Pos \ - (12UL) /*!< GPDMA0 LSTDSTREG: WE_CH4 (Bit 12) */ -#define GPDMA0_LSTDSTREG_WE_CH4_Msk \ - (0x1000UL) /*!< GPDMA0 LSTDSTREG: WE_CH4 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTDSTREG_WE_CH5_Pos \ - (13UL) /*!< GPDMA0 LSTDSTREG: WE_CH5 (Bit 13) */ -#define GPDMA0_LSTDSTREG_WE_CH5_Msk \ - (0x2000UL) /*!< GPDMA0 LSTDSTREG: WE_CH5 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTDSTREG_WE_CH6_Pos \ - (14UL) /*!< GPDMA0 LSTDSTREG: WE_CH6 (Bit 14) */ -#define GPDMA0_LSTDSTREG_WE_CH6_Msk \ - (0x4000UL) /*!< GPDMA0 LSTDSTREG: WE_CH6 (Bitfield-Mask: 0x01) */ -#define GPDMA0_LSTDSTREG_WE_CH7_Pos \ - (15UL) /*!< GPDMA0 LSTDSTREG: WE_CH7 (Bit 15) */ -#define GPDMA0_LSTDSTREG_WE_CH7_Msk \ - (0x8000UL) /*!< GPDMA0 LSTDSTREG: WE_CH7 (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPDMA0_DMACFGREG ------------------------------ */ -#define GPDMA0_DMACFGREG_DMA_EN_Pos \ - (0UL) /*!< GPDMA0 DMACFGREG: DMA_EN (Bit 0) */ -#define GPDMA0_DMACFGREG_DMA_EN_Msk \ - (0x1UL) /*!< GPDMA0 DMACFGREG: DMA_EN (Bitfield-Mask: 0x01) */ - -/* ------------------------------- GPDMA0_CHENREG ------------------------------- */ -#define GPDMA0_CHENREG_CH_Pos \ - (0UL) /*!< GPDMA0 CHENREG: CH (Bit 0) */ -#define GPDMA0_CHENREG_CH_Msk \ - (0xffUL) /*!< GPDMA0 CHENREG: CH (Bitfield-Mask: 0xff) */ -#define GPDMA0_CHENREG_WE_CH_Pos \ - (8UL) /*!< GPDMA0 CHENREG: WE_CH (Bit 8) */ -#define GPDMA0_CHENREG_WE_CH_Msk \ - (0xff00UL) /*!< GPDMA0 CHENREG: WE_CH (Bitfield-Mask: 0xff) */ - -/* ---------------------------------- GPDMA0_ID --------------------------------- */ -#define GPDMA0_ID_VALUE_Pos \ - (0UL) /*!< GPDMA0 ID: VALUE (Bit 0) */ -#define GPDMA0_ID_VALUE_Msk \ - (0xffffffffUL) /*!< GPDMA0 ID: VALUE (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------------- GPDMA0_TYPE -------------------------------- */ -#define GPDMA0_TYPE_VALUE_Pos \ - (0UL) /*!< GPDMA0 TYPE: VALUE (Bit 0) */ -#define GPDMA0_TYPE_VALUE_Msk \ - (0xffffffffUL) /*!< GPDMA0 TYPE: VALUE (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------- GPDMA0_VERSION ------------------------------- */ -#define GPDMA0_VERSION_VALUE_Pos \ - (0UL) /*!< GPDMA0 VERSION: VALUE (Bit 0) */ -#define GPDMA0_VERSION_VALUE_Msk \ - (0xffffffffUL) /*!< GPDMA0 VERSION: VALUE (Bitfield-Mask: 0xffffffff) */ - -/* ================================================================================ */ -/* ================ Group 'GPDMA0_CH0_1' Position & Mask ================ */ -/* ================================================================================ */ - -/* ------------------------------ GPDMA0_CH_SAR ------------------------------ */ -#define GPDMA0_CH_SAR_SAR_Pos \ - (0UL) /*!< GPDMA0_CH0_1 SAR: SAR (Bit 0) */ -#define GPDMA0_CH_SAR_SAR_Msk \ - (0xffffffffUL) /*!< GPDMA0_CH0_1 SAR: SAR (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------ GPDMA0_CH_DAR ------------------------------ */ -#define GPDMA0_CH_DAR_DAR_Pos \ - (0UL) /*!< GPDMA0_CH0_1 DAR: DAR (Bit 0) */ -#define GPDMA0_CH_DAR_DAR_Msk \ - (0xffffffffUL) /*!< GPDMA0_CH0_1 DAR: DAR (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------ GPDMA0_CH_LLP ------------------------------ */ -#define GPDMA0_CH_LLP_LOC_Pos \ - (2UL) /*!< GPDMA0_CH0_1 LLP: LOC (Bit 2) */ -#define GPDMA0_CH_LLP_LOC_Msk \ - (0xfffffffcUL) /*!< GPDMA0_CH0_1 LLP: LOC (Bitfield-Mask: 0x3fffffff) */ - -/* ------------------------------ GPDMA0_CH_CTLL ----------------------------- */ -#define GPDMA0_CH_CTLL_INT_EN_Pos \ - (0UL) /*!< GPDMA0_CH0_1 CTLL: INT_EN (Bit 0) */ -#define GPDMA0_CH_CTLL_INT_EN_Msk \ - (0x1UL) /*!< GPDMA0_CH0_1 CTLL: INT_EN (Bitfield-Mask: 0x01) */ -#define GPDMA0_CH_CTLL_DST_TR_WIDTH_Pos \ - (1UL) /*!< GPDMA0_CH0_1 CTLL: DST_TR_WIDTH (Bit 1) */ -#define GPDMA0_CH_CTLL_DST_TR_WIDTH_Msk \ - (0xeUL) /*!< GPDMA0_CH0_1 CTLL: DST_TR_WIDTH (Bitfield-Mask: 0x07) */ -#define GPDMA0_CH_CTLL_SRC_TR_WIDTH_Pos \ - (4UL) /*!< GPDMA0_CH0_1 CTLL: SRC_TR_WIDTH (Bit 4) */ -#define GPDMA0_CH_CTLL_SRC_TR_WIDTH_Msk \ - (0x70UL) /*!< GPDMA0_CH0_1 CTLL: SRC_TR_WIDTH (Bitfield-Mask: 0x07) */ -#define GPDMA0_CH_CTLL_DINC_Pos \ - (7UL) /*!< GPDMA0_CH0_1 CTLL: DINC (Bit 7) */ -#define GPDMA0_CH_CTLL_DINC_Msk \ - (0x180UL) /*!< GPDMA0_CH0_1 CTLL: DINC (Bitfield-Mask: 0x03) */ -#define GPDMA0_CH_CTLL_SINC_Pos \ - (9UL) /*!< GPDMA0_CH0_1 CTLL: SINC (Bit 9) */ -#define GPDMA0_CH_CTLL_SINC_Msk \ - (0x600UL) /*!< GPDMA0_CH0_1 CTLL: SINC (Bitfield-Mask: 0x03) */ -#define GPDMA0_CH_CTLL_DEST_MSIZE_Pos \ - (11UL) /*!< GPDMA0_CH0_1 CTLL: DEST_MSIZE (Bit 11) */ -#define GPDMA0_CH_CTLL_DEST_MSIZE_Msk \ - (0x3800UL) /*!< GPDMA0_CH0_1 CTLL: DEST_MSIZE (Bitfield-Mask: 0x07) */ -#define GPDMA0_CH_CTLL_SRC_MSIZE_Pos \ - (14UL) /*!< GPDMA0_CH0_1 CTLL: SRC_MSIZE (Bit 14) */ -#define GPDMA0_CH_CTLL_SRC_MSIZE_Msk \ - (0x1c000UL) /*!< GPDMA0_CH0_1 CTLL: SRC_MSIZE (Bitfield-Mask: 0x07) */ -#define GPDMA0_CH_CTLL_SRC_GATHER_EN_Pos \ - (17UL) /*!< GPDMA0_CH0_1 CTLL: SRC_GATHER_EN (Bit 17) */ -#define GPDMA0_CH_CTLL_SRC_GATHER_EN_Msk \ - (0x20000UL) /*!< GPDMA0_CH0_1 CTLL: SRC_GATHER_EN (Bitfield-Mask: 0x01) */ -#define GPDMA0_CH_CTLL_DST_SCATTER_EN_Pos \ - (18UL) /*!< GPDMA0_CH0_1 CTLL: DST_SCATTER_EN (Bit 18) */ -#define GPDMA0_CH_CTLL_DST_SCATTER_EN_Msk \ - (0x40000UL) /*!< GPDMA0_CH0_1 CTLL: DST_SCATTER_EN (Bitfield-Mask: 0x01) */ -#define GPDMA0_CH_CTLL_TT_FC_Pos \ - (20UL) /*!< GPDMA0_CH0_1 CTLL: TT_FC (Bit 20) */ -#define GPDMA0_CH_CTLL_TT_FC_Msk \ - (0x700000UL) /*!< GPDMA0_CH0_1 CTLL: TT_FC (Bitfield-Mask: 0x07) */ -#define GPDMA0_CH_CTLL_LLP_DST_EN_Pos \ - (27UL) /*!< GPDMA0_CH0_1 CTLL: LLP_DST_EN (Bit 27) */ -#define GPDMA0_CH_CTLL_LLP_DST_EN_Msk \ - (0x8000000UL) /*!< GPDMA0_CH0_1 CTLL: LLP_DST_EN (Bitfield-Mask: 0x01) */ -#define GPDMA0_CH_CTLL_LLP_SRC_EN_Pos \ - (28UL) /*!< GPDMA0_CH0_1 CTLL: LLP_SRC_EN (Bit 28) */ -#define GPDMA0_CH_CTLL_LLP_SRC_EN_Msk \ - (0x10000000UL) /*!< GPDMA0_CH0_1 CTLL: LLP_SRC_EN (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPDMA0_CH_CTLH ----------------------------- */ -#define GPDMA0_CH_CTLH_BLOCK_TS_Pos \ - (0UL) /*!< GPDMA0_CH0_1 CTLH: BLOCK_TS (Bit 0) */ -#define GPDMA0_CH_CTLH_BLOCK_TS_Msk \ - (0xfffUL) /*!< GPDMA0_CH0_1 CTLH: BLOCK_TS (Bitfield-Mask: 0xfff) */ -#define GPDMA0_CH_CTLH_DONE_Pos \ - (12UL) /*!< GPDMA0_CH0_1 CTLH: DONE (Bit 12) */ -#define GPDMA0_CH_CTLH_DONE_Msk \ - (0x1000UL) /*!< GPDMA0_CH0_1 CTLH: DONE (Bitfield-Mask: 0x01) */ - -/* ----------------------------- GPDMA0_CH_SSTAT ----------------------------- */ -#define GPDMA0_CH_SSTAT_SSTAT_Pos \ - (0UL) /*!< GPDMA0_CH0_1 SSTAT: SSTAT (Bit 0) */ -#define GPDMA0_CH_SSTAT_SSTAT_Msk \ - (0xffffffffUL) /*!< GPDMA0_CH0_1 SSTAT: SSTAT (Bitfield-Mask: 0xffffffff) */ - -/* ----------------------------- GPDMA0_CH_DSTAT ----------------------------- */ -#define GPDMA0_CH_DSTAT_DSTAT_Pos \ - (0UL) /*!< GPDMA0_CH0_1 DSTAT: DSTAT (Bit 0) */ -#define GPDMA0_CH_DSTAT_DSTAT_Msk \ - (0xffffffffUL) /*!< GPDMA0_CH0_1 DSTAT: DSTAT (Bitfield-Mask: 0xffffffff) */ - -/* ---------------------------- GPDMA0_CH_SSTATAR ---------------------------- */ -#define GPDMA0_CH_SSTATAR_SSTATAR_Pos \ - (0UL) /*!< GPDMA0_CH0_1 SSTATAR: SSTATAR (Bit 0) */ -#define GPDMA0_CH_SSTATAR_SSTATAR_Msk \ - (0xffffffffUL) /*!< GPDMA0_CH0_1 SSTATAR: SSTATAR (Bitfield-Mask: 0xffffffff) */ - -/* ---------------------------- GPDMA0_CH_DSTATAR ---------------------------- */ -#define GPDMA0_CH_DSTATAR_DSTATAR_Pos \ - (0UL) /*!< GPDMA0_CH0_1 DSTATAR: DSTATAR (Bit 0) */ -#define GPDMA0_CH_DSTATAR_DSTATAR_Msk \ - (0xffffffffUL) /*!< GPDMA0_CH0_1 DSTATAR: DSTATAR (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------ GPDMA0_CH_CFGL ----------------------------- */ -#define GPDMA0_CH_CFGL_CH_PRIOR_Pos \ - (5UL) /*!< GPDMA0_CH0_1 CFGL: CH_PRIOR (Bit 5) */ -#define GPDMA0_CH_CFGL_CH_PRIOR_Msk \ - (0xe0UL) /*!< GPDMA0_CH0_1 CFGL: CH_PRIOR (Bitfield-Mask: 0x07) */ -#define GPDMA0_CH_CFGL_CH_SUSP_Pos \ - (8UL) /*!< GPDMA0_CH0_1 CFGL: CH_SUSP (Bit 8) */ -#define GPDMA0_CH_CFGL_CH_SUSP_Msk \ - (0x100UL) /*!< GPDMA0_CH0_1 CFGL: CH_SUSP (Bitfield-Mask: 0x01) */ -#define GPDMA0_CH_CFGL_FIFO_EMPTY_Pos \ - (9UL) /*!< GPDMA0_CH0_1 CFGL: FIFO_EMPTY (Bit 9) */ -#define GPDMA0_CH_CFGL_FIFO_EMPTY_Msk \ - (0x200UL) /*!< GPDMA0_CH0_1 CFGL: FIFO_EMPTY (Bitfield-Mask: 0x01) */ -#define GPDMA0_CH_CFGL_HS_SEL_DST_Pos \ - (10UL) /*!< GPDMA0_CH0_1 CFGL: HS_SEL_DST (Bit 10) */ -#define GPDMA0_CH_CFGL_HS_SEL_DST_Msk \ - (0x400UL) /*!< GPDMA0_CH0_1 CFGL: HS_SEL_DST (Bitfield-Mask: 0x01) */ -#define GPDMA0_CH_CFGL_HS_SEL_SRC_Pos \ - (11UL) /*!< GPDMA0_CH0_1 CFGL: HS_SEL_SRC (Bit 11) */ -#define GPDMA0_CH_CFGL_HS_SEL_SRC_Msk \ - (0x800UL) /*!< GPDMA0_CH0_1 CFGL: HS_SEL_SRC (Bitfield-Mask: 0x01) */ -#define GPDMA0_CH_CFGL_LOCK_CH_L_Pos \ - (12UL) /*!< GPDMA0_CH0_1 CFGL: LOCK_CH_L (Bit 12) */ -#define GPDMA0_CH_CFGL_LOCK_CH_L_Msk \ - (0x3000UL) /*!< GPDMA0_CH0_1 CFGL: LOCK_CH_L (Bitfield-Mask: 0x03) */ -#define GPDMA0_CH_CFGL_LOCK_B_L_Pos \ - (14UL) /*!< GPDMA0_CH0_1 CFGL: LOCK_B_L (Bit 14) */ -#define GPDMA0_CH_CFGL_LOCK_B_L_Msk \ - (0xc000UL) /*!< GPDMA0_CH0_1 CFGL: LOCK_B_L (Bitfield-Mask: 0x03) */ -#define GPDMA0_CH_CFGL_LOCK_CH_Pos \ - (16UL) /*!< GPDMA0_CH0_1 CFGL: LOCK_CH (Bit 16) */ -#define GPDMA0_CH_CFGL_LOCK_CH_Msk \ - (0x10000UL) /*!< GPDMA0_CH0_1 CFGL: LOCK_CH (Bitfield-Mask: 0x01) */ -#define GPDMA0_CH_CFGL_LOCK_B_Pos \ - (17UL) /*!< GPDMA0_CH0_1 CFGL: LOCK_B (Bit 17) */ -#define GPDMA0_CH_CFGL_LOCK_B_Msk \ - (0x20000UL) /*!< GPDMA0_CH0_1 CFGL: LOCK_B (Bitfield-Mask: 0x01) */ -#define GPDMA0_CH_CFGL_DST_HS_POL_Pos \ - (18UL) /*!< GPDMA0_CH0_1 CFGL: DST_HS_POL (Bit 18) */ -#define GPDMA0_CH_CFGL_DST_HS_POL_Msk \ - (0x40000UL) /*!< GPDMA0_CH0_1 CFGL: DST_HS_POL (Bitfield-Mask: 0x01) */ -#define GPDMA0_CH_CFGL_SRC_HS_POL_Pos \ - (19UL) /*!< GPDMA0_CH0_1 CFGL: SRC_HS_POL (Bit 19) */ -#define GPDMA0_CH_CFGL_SRC_HS_POL_Msk \ - (0x80000UL) /*!< GPDMA0_CH0_1 CFGL: SRC_HS_POL (Bitfield-Mask: 0x01) */ -#define GPDMA0_CH_CFGL_MAX_ABRST_Pos \ - (20UL) /*!< GPDMA0_CH0_1 CFGL: MAX_ABRST (Bit 20) */ -#define GPDMA0_CH_CFGL_MAX_ABRST_Msk \ - (0x3ff00000UL) /*!< GPDMA0_CH0_1 CFGL: MAX_ABRST (Bitfield-Mask: 0x3ff) */ -#define GPDMA0_CH_CFGL_RELOAD_SRC_Pos \ - (30UL) /*!< GPDMA0_CH0_1 CFGL: RELOAD_SRC (Bit 30) */ -#define GPDMA0_CH_CFGL_RELOAD_SRC_Msk \ - (0x40000000UL) /*!< GPDMA0_CH0_1 CFGL: RELOAD_SRC (Bitfield-Mask: 0x01) */ -#define GPDMA0_CH_CFGL_RELOAD_DST_Pos \ - (31UL) /*!< GPDMA0_CH0_1 CFGL: RELOAD_DST (Bit 31) */ -#define GPDMA0_CH_CFGL_RELOAD_DST_Msk \ - (0x80000000UL) /*!< GPDMA0_CH0_1 CFGL: RELOAD_DST (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPDMA0_CH_CFGH ----------------------------- */ -#define GPDMA0_CH_CFGH_FCMODE_Pos \ - (0UL) /*!< GPDMA0_CH0_1 CFGH: FCMODE (Bit 0) */ -#define GPDMA0_CH_CFGH_FCMODE_Msk \ - (0x1UL) /*!< GPDMA0_CH0_1 CFGH: FCMODE (Bitfield-Mask: 0x01) */ -#define GPDMA0_CH_CFGH_FIFO_MODE_Pos \ - (1UL) /*!< GPDMA0_CH0_1 CFGH: FIFO_MODE (Bit 1) */ -#define GPDMA0_CH_CFGH_FIFO_MODE_Msk \ - (0x2UL) /*!< GPDMA0_CH0_1 CFGH: FIFO_MODE (Bitfield-Mask: 0x01) */ -#define GPDMA0_CH_CFGH_PROTCTL_Pos \ - (2UL) /*!< GPDMA0_CH0_1 CFGH: PROTCTL (Bit 2) */ -#define GPDMA0_CH_CFGH_PROTCTL_Msk \ - (0x1cUL) /*!< GPDMA0_CH0_1 CFGH: PROTCTL (Bitfield-Mask: 0x07) */ -#define GPDMA0_CH_CFGH_DS_UPD_EN_Pos \ - (5UL) /*!< GPDMA0_CH0_1 CFGH: DS_UPD_EN (Bit 5) */ -#define GPDMA0_CH_CFGH_DS_UPD_EN_Msk \ - (0x20UL) /*!< GPDMA0_CH0_1 CFGH: DS_UPD_EN (Bitfield-Mask: 0x01) */ -#define GPDMA0_CH_CFGH_SS_UPD_EN_Pos \ - (6UL) /*!< GPDMA0_CH0_1 CFGH: SS_UPD_EN (Bit 6) */ -#define GPDMA0_CH_CFGH_SS_UPD_EN_Msk \ - (0x40UL) /*!< GPDMA0_CH0_1 CFGH: SS_UPD_EN (Bitfield-Mask: 0x01) */ -#define GPDMA0_CH_CFGH_SRC_PER_Pos \ - (7UL) /*!< GPDMA0_CH0_1 CFGH: SRC_PER (Bit 7) */ -#define GPDMA0_CH_CFGH_SRC_PER_Msk \ - (0x780UL) /*!< GPDMA0_CH0_1 CFGH: SRC_PER (Bitfield-Mask: 0x0f) */ -#define GPDMA0_CH_CFGH_DEST_PER_Pos \ - (11UL) /*!< GPDMA0_CH0_1 CFGH: DEST_PER (Bit 11) */ -#define GPDMA0_CH_CFGH_DEST_PER_Msk \ - (0x7800UL) /*!< GPDMA0_CH0_1 CFGH: DEST_PER (Bitfield-Mask: 0x0f) */ - -/* ------------------------------ GPDMA0_CH_SGR ------------------------------ */ -#define GPDMA0_CH_SGR_SGI_Pos \ - (0UL) /*!< GPDMA0_CH0_1 SGR: SGI (Bit 0) */ -#define GPDMA0_CH_SGR_SGI_Msk \ - (0xfffffUL) /*!< GPDMA0_CH0_1 SGR: SGI (Bitfield-Mask: 0xfffff) */ -#define GPDMA0_CH_SGR_SGC_Pos \ - (20UL) /*!< GPDMA0_CH0_1 SGR: SGC (Bit 20) */ -#define GPDMA0_CH_SGR_SGC_Msk \ - (0xfff00000UL) /*!< GPDMA0_CH0_1 SGR: SGC (Bitfield-Mask: 0xfff) */ - -/* ------------------------------ GPDMA0_CH_DSR ------------------------------ */ -#define GPDMA0_CH_DSR_DSI_Pos \ - (0UL) /*!< GPDMA0_CH0_1 DSR: DSI (Bit 0) */ -#define GPDMA0_CH_DSR_DSI_Msk \ - (0xfffffUL) /*!< GPDMA0_CH0_1 DSR: DSI (Bitfield-Mask: 0xfffff) */ -#define GPDMA0_CH_DSR_DSC_Pos \ - (20UL) /*!< GPDMA0_CH0_1 DSR: DSC (Bit 20) */ -#define GPDMA0_CH_DSR_DSC_Msk \ - (0xfff00000UL) /*!< GPDMA0_CH0_1 DSR: DSC (Bitfield-Mask: 0xfff) */ - -/* ================================================================================ */ -/* ================ struct 'FCE' Position & Mask ================ */ -/* ================================================================================ */ - -/* ----------------------------------- FCE_CLC ---------------------------------- */ -#define FCE_CLC_DISR_Pos (0UL) /*!< FCE CLC: DISR (Bit 0) */ -#define FCE_CLC_DISR_Msk (0x1UL) /*!< FCE CLC: DISR (Bitfield-Mask: 0x01) */ -#define FCE_CLC_DISS_Pos (1UL) /*!< FCE CLC: DISS (Bit 1) */ -#define FCE_CLC_DISS_Msk (0x2UL) /*!< FCE CLC: DISS (Bitfield-Mask: 0x01) */ - -/* ----------------------------------- FCE_ID ----------------------------------- */ -#define FCE_ID_MOD_REV_Pos (0UL) /*!< FCE ID: MOD_REV (Bit 0) */ -#define FCE_ID_MOD_REV_Msk \ - (0xffUL) /*!< FCE ID: MOD_REV (Bitfield-Mask: 0xff) */ -#define FCE_ID_MOD_TYPE_Pos \ - (8UL) /*!< FCE ID: MOD_TYPE (Bit 8) */ -#define FCE_ID_MOD_TYPE_Msk \ - (0xff00UL) /*!< FCE ID: MOD_TYPE (Bitfield-Mask: 0xff) */ -#define FCE_ID_MOD_NUMBER_Pos \ - (16UL) /*!< FCE ID: MOD_NUMBER (Bit 16) */ -#define FCE_ID_MOD_NUMBER_Msk \ - (0xffff0000UL) /*!< FCE ID: MOD_NUMBER (Bitfield-Mask: 0xffff) */ - -/* ================================================================================ */ -/* ================ Group 'FCE_KE' Position & Mask ================ */ -/* ================================================================================ */ - -/* ---------------------------------- FCE_KE_IR --------------------------------- */ -#define FCE_KE_IR_IR_Pos (0UL) /*!< FCE_KE IR: IR (Bit 0) */ -#define FCE_KE_IR_IR_Msk \ - (0xffffffffUL) /*!< FCE_KE IR: IR (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------------- FCE_KE_RES --------------------------------- */ -#define FCE_KE_RES_RES_Pos (0UL) /*!< FCE_KE RES: RES (Bit 0) */ -#define FCE_KE_RES_RES_Msk \ - (0xffffffffUL) /*!< FCE_KE RES: RES (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------------- FCE_KE_CFG --------------------------------- */ -#define FCE_KE_CFG_CMI_Pos (0UL) /*!< FCE_KE CFG: CMI (Bit 0) */ -#define FCE_KE_CFG_CMI_Msk \ - (0x1UL) /*!< FCE_KE CFG: CMI (Bitfield-Mask: 0x01) */ -#define FCE_KE_CFG_CEI_Pos (1UL) /*!< FCE_KE CFG: CEI (Bit 1) */ -#define FCE_KE_CFG_CEI_Msk \ - (0x2UL) /*!< FCE_KE CFG: CEI (Bitfield-Mask: 0x01) */ -#define FCE_KE_CFG_LEI_Pos (2UL) /*!< FCE_KE CFG: LEI (Bit 2) */ -#define FCE_KE_CFG_LEI_Msk \ - (0x4UL) /*!< FCE_KE CFG: LEI (Bitfield-Mask: 0x01) */ -#define FCE_KE_CFG_BEI_Pos (3UL) /*!< FCE_KE CFG: BEI (Bit 3) */ -#define FCE_KE_CFG_BEI_Msk \ - (0x8UL) /*!< FCE_KE CFG: BEI (Bitfield-Mask: 0x01) */ -#define FCE_KE_CFG_CCE_Pos (4UL) /*!< FCE_KE CFG: CCE (Bit 4) */ -#define FCE_KE_CFG_CCE_Msk \ - (0x10UL) /*!< FCE_KE CFG: CCE (Bitfield-Mask: 0x01) */ -#define FCE_KE_CFG_ALR_Pos (5UL) /*!< FCE_KE CFG: ALR (Bit 5) */ -#define FCE_KE_CFG_ALR_Msk \ - (0x20UL) /*!< FCE_KE CFG: ALR (Bitfield-Mask: 0x01) */ -#define FCE_KE_CFG_REFIN_Pos \ - (8UL) /*!< FCE_KE CFG: REFIN (Bit 8) */ -#define FCE_KE_CFG_REFIN_Msk \ - (0x100UL) /*!< FCE_KE CFG: REFIN (Bitfield-Mask: 0x01) */ -#define FCE_KE_CFG_REFOUT_Pos \ - (9UL) /*!< FCE_KE CFG: REFOUT (Bit 9) */ -#define FCE_KE_CFG_REFOUT_Msk \ - (0x200UL) /*!< FCE_KE CFG: REFOUT (Bitfield-Mask: 0x01) */ -#define FCE_KE_CFG_XSEL_Pos \ - (10UL) /*!< FCE_KE CFG: XSEL (Bit 10) */ -#define FCE_KE_CFG_XSEL_Msk \ - (0x400UL) /*!< FCE_KE CFG: XSEL (Bitfield-Mask: 0x01) */ - -/* --------------------------------- FCE_KE_STS --------------------------------- */ -#define FCE_KE_STS_CMF_Pos (0UL) /*!< FCE_KE STS: CMF (Bit 0) */ -#define FCE_KE_STS_CMF_Msk \ - (0x1UL) /*!< FCE_KE STS: CMF (Bitfield-Mask: 0x01) */ -#define FCE_KE_STS_CEF_Pos (1UL) /*!< FCE_KE STS: CEF (Bit 1) */ -#define FCE_KE_STS_CEF_Msk \ - (0x2UL) /*!< FCE_KE STS: CEF (Bitfield-Mask: 0x01) */ -#define FCE_KE_STS_LEF_Pos (2UL) /*!< FCE_KE STS: LEF (Bit 2) */ -#define FCE_KE_STS_LEF_Msk \ - (0x4UL) /*!< FCE_KE STS: LEF (Bitfield-Mask: 0x01) */ -#define FCE_KE_STS_BEF_Pos (3UL) /*!< FCE_KE STS: BEF (Bit 3) */ -#define FCE_KE_STS_BEF_Msk \ - (0x8UL) /*!< FCE_KE STS: BEF (Bitfield-Mask: 0x01) */ - -/* -------------------------------- FCE_KE_LENGTH ------------------------------- */ -#define FCE_KE_LENGTH_LENGTH_Pos \ - (0UL) /*!< FCE_KE LENGTH: LENGTH (Bit 0) */ -#define FCE_KE_LENGTH_LENGTH_Msk \ - (0xffffUL) /*!< FCE_KE LENGTH: LENGTH (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- FCE_KE_CHECK -------------------------------- */ -#define FCE_KE_CHECK_CHECK_Pos \ - (0UL) /*!< FCE_KE CHECK: CHECK (Bit 0) */ -#define FCE_KE_CHECK_CHECK_Msk \ - (0xffffffffUL) /*!< FCE_KE CHECK: CHECK (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------------- FCE_KE_CRC --------------------------------- */ -#define FCE_KE_CRC_CRC_Pos (0UL) /*!< FCE_KE CRC: CRC (Bit 0) */ -#define FCE_KE_CRC_CRC_Msk \ - (0xffffffffUL) /*!< FCE_KE CRC: CRC (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------------- FCE_KE_CTR --------------------------------- */ -#define FCE_KE_CTR_FCM_Pos (0UL) /*!< FCE_KE CTR: FCM (Bit 0) */ -#define FCE_KE_CTR_FCM_Msk \ - (0x1UL) /*!< FCE_KE CTR: FCM (Bitfield-Mask: 0x01) */ -#define FCE_KE_CTR_FRM_CFG_Pos \ - (1UL) /*!< FCE_KE CTR: FRM_CFG (Bit 1) */ -#define FCE_KE_CTR_FRM_CFG_Msk \ - (0x2UL) /*!< FCE_KE CTR: FRM_CFG (Bitfield-Mask: 0x01) */ -#define FCE_KE_CTR_FRM_CHECK_Pos \ - (2UL) /*!< FCE_KE CTR: FRM_CHECK (Bit 2) */ -#define FCE_KE_CTR_FRM_CHECK_Msk \ - (0x4UL) /*!< FCE_KE CTR: FRM_CHECK (Bitfield-Mask: 0x01) */ - -/* ================================================================================ */ -/* ================ Group 'PBA' Position & Mask ================ */ -/* ================================================================================ */ - -/* ----------------------------------- PBA_STS ---------------------------------- */ -#define PBA_STS_WERR_Pos (0UL) /*!< PBA STS: WERR (Bit 0) */ -#define PBA_STS_WERR_Msk (0x1UL) /*!< PBA STS: WERR (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- PBA_WADDR --------------------------------- */ -#define PBA_WADDR_WADDR_Pos \ - (0UL) /*!< PBA WADDR: WADDR (Bit 0) */ -#define PBA_WADDR_WADDR_Msk \ - (0xffffffffUL) /*!< PBA WADDR: WADDR (Bitfield-Mask: 0xffffffff) */ - -/* ================================================================================ */ -/* ================ Group 'FLASH' Position & Mask ================ */ -/* ================================================================================ */ - -/* ---------------------------------- FLASH_ID ---------------------------------- */ -#define FLASH_ID_MOD_REV_Pos \ - (0UL) /*!< FLASH ID: MOD_REV (Bit 0) */ -#define FLASH_ID_MOD_REV_Msk \ - (0xffUL) /*!< FLASH ID: MOD_REV (Bitfield-Mask: 0xff) */ -#define FLASH_ID_MOD_TYPE_Pos \ - (8UL) /*!< FLASH ID: MOD_TYPE (Bit 8) */ -#define FLASH_ID_MOD_TYPE_Msk \ - (0xff00UL) /*!< FLASH ID: MOD_TYPE (Bitfield-Mask: 0xff) */ -#define FLASH_ID_MOD_NUMBER_Pos \ - (16UL) /*!< FLASH ID: MOD_NUMBER (Bit 16) */ -#define FLASH_ID_MOD_NUMBER_Msk \ - (0xffff0000UL) /*!< FLASH ID: MOD_NUMBER (Bitfield-Mask: 0xffff) */ - -/* ---------------------------------- FLASH_FSR --------------------------------- */ -#define FLASH_FSR_PBUSY_Pos \ - (0UL) /*!< FLASH FSR: PBUSY (Bit 0) */ -#define FLASH_FSR_PBUSY_Msk \ - (0x1UL) /*!< FLASH FSR: PBUSY (Bitfield-Mask: 0x01) */ -#define FLASH_FSR_FABUSY_Pos \ - (1UL) /*!< FLASH FSR: FABUSY (Bit 1) */ -#define FLASH_FSR_FABUSY_Msk \ - (0x2UL) /*!< FLASH FSR: FABUSY (Bitfield-Mask: 0x01) */ -#define FLASH_FSR_PROG_Pos (4UL) /*!< FLASH FSR: PROG (Bit 4) */ -#define FLASH_FSR_PROG_Msk \ - (0x10UL) /*!< FLASH FSR: PROG (Bitfield-Mask: 0x01) */ -#define FLASH_FSR_ERASE_Pos \ - (5UL) /*!< FLASH FSR: ERASE (Bit 5) */ -#define FLASH_FSR_ERASE_Msk \ - (0x20UL) /*!< FLASH FSR: ERASE (Bitfield-Mask: 0x01) */ -#define FLASH_FSR_PFPAGE_Pos \ - (6UL) /*!< FLASH FSR: PFPAGE (Bit 6) */ -#define FLASH_FSR_PFPAGE_Msk \ - (0x40UL) /*!< FLASH FSR: PFPAGE (Bitfield-Mask: 0x01) */ -#define FLASH_FSR_PFOPER_Pos \ - (8UL) /*!< FLASH FSR: PFOPER (Bit 8) */ -#define FLASH_FSR_PFOPER_Msk \ - (0x100UL) /*!< FLASH FSR: PFOPER (Bitfield-Mask: 0x01) */ -#define FLASH_FSR_SQER_Pos \ - (10UL) /*!< FLASH FSR: SQER (Bit 10) */ -#define FLASH_FSR_SQER_Msk \ - (0x400UL) /*!< FLASH FSR: SQER (Bitfield-Mask: 0x01) */ -#define FLASH_FSR_PROER_Pos \ - (11UL) /*!< FLASH FSR: PROER (Bit 11) */ -#define FLASH_FSR_PROER_Msk \ - (0x800UL) /*!< FLASH FSR: PROER (Bitfield-Mask: 0x01) */ -#define FLASH_FSR_PFSBER_Pos \ - (12UL) /*!< FLASH FSR: PFSBER (Bit 12) */ -#define FLASH_FSR_PFSBER_Msk \ - (0x1000UL) /*!< FLASH FSR: PFSBER (Bitfield-Mask: 0x01) */ -#define FLASH_FSR_PFDBER_Pos \ - (14UL) /*!< FLASH FSR: PFDBER (Bit 14) */ -#define FLASH_FSR_PFDBER_Msk \ - (0x4000UL) /*!< FLASH FSR: PFDBER (Bitfield-Mask: 0x01) */ -#define FLASH_FSR_PROIN_Pos \ - (16UL) /*!< FLASH FSR: PROIN (Bit 16) */ -#define FLASH_FSR_PROIN_Msk \ - (0x10000UL) /*!< FLASH FSR: PROIN (Bitfield-Mask: 0x01) */ -#define FLASH_FSR_RPROIN_Pos \ - (18UL) /*!< FLASH FSR: RPROIN (Bit 18) */ -#define FLASH_FSR_RPROIN_Msk \ - (0x40000UL) /*!< FLASH FSR: RPROIN (Bitfield-Mask: 0x01) */ -#define FLASH_FSR_RPRODIS_Pos \ - (19UL) /*!< FLASH FSR: RPRODIS (Bit 19) */ -#define FLASH_FSR_RPRODIS_Msk \ - (0x80000UL) /*!< FLASH FSR: RPRODIS (Bitfield-Mask: 0x01) */ -#define FLASH_FSR_WPROIN0_Pos \ - (21UL) /*!< FLASH FSR: WPROIN0 (Bit 21) */ -#define FLASH_FSR_WPROIN0_Msk \ - (0x200000UL) /*!< FLASH FSR: WPROIN0 (Bitfield-Mask: 0x01) */ -#define FLASH_FSR_WPROIN1_Pos \ - (22UL) /*!< FLASH FSR: WPROIN1 (Bit 22) */ -#define FLASH_FSR_WPROIN1_Msk \ - (0x400000UL) /*!< FLASH FSR: WPROIN1 (Bitfield-Mask: 0x01) */ -#define FLASH_FSR_WPROIN2_Pos \ - (23UL) /*!< FLASH FSR: WPROIN2 (Bit 23) */ -#define FLASH_FSR_WPROIN2_Msk \ - (0x800000UL) /*!< FLASH FSR: WPROIN2 (Bitfield-Mask: 0x01) */ -#define FLASH_FSR_WPRODIS0_Pos \ - (25UL) /*!< FLASH FSR: WPRODIS0 (Bit 25) */ -#define FLASH_FSR_WPRODIS0_Msk \ - (0x2000000UL) /*!< FLASH FSR: WPRODIS0 (Bitfield-Mask: 0x01) */ -#define FLASH_FSR_WPRODIS1_Pos \ - (26UL) /*!< FLASH FSR: WPRODIS1 (Bit 26) */ -#define FLASH_FSR_WPRODIS1_Msk \ - (0x4000000UL) /*!< FLASH FSR: WPRODIS1 (Bitfield-Mask: 0x01) */ -#define FLASH_FSR_SLM_Pos (28UL) /*!< FLASH FSR: SLM (Bit 28) */ -#define FLASH_FSR_SLM_Msk \ - (0x10000000UL) /*!< FLASH FSR: SLM (Bitfield-Mask: 0x01) */ -#define FLASH_FSR_VER_Pos (31UL) /*!< FLASH FSR: VER (Bit 31) */ -#define FLASH_FSR_VER_Msk \ - (0x80000000UL) /*!< FLASH FSR: VER (Bitfield-Mask: 0x01) */ - -/* --------------------------------- FLASH_FCON --------------------------------- */ -#define FLASH_FCON_WSPFLASH_Pos \ - (0UL) /*!< FLASH FCON: WSPFLASH (Bit 0) */ -#define FLASH_FCON_WSPFLASH_Msk \ - (0xfUL) /*!< FLASH FCON: WSPFLASH (Bitfield-Mask: 0x0f) */ -#define FLASH_FCON_WSECPF_Pos \ - (4UL) /*!< FLASH FCON: WSECPF (Bit 4) */ -#define FLASH_FCON_WSECPF_Msk \ - (0x10UL) /*!< FLASH FCON: WSECPF (Bitfield-Mask: 0x01) */ -#define FLASH_FCON_IDLE_Pos \ - (13UL) /*!< FLASH FCON: IDLE (Bit 13) */ -#define FLASH_FCON_IDLE_Msk \ - (0x2000UL) /*!< FLASH FCON: IDLE (Bitfield-Mask: 0x01) */ -#define FLASH_FCON_ESLDIS_Pos \ - (14UL) /*!< FLASH FCON: ESLDIS (Bit 14) */ -#define FLASH_FCON_ESLDIS_Msk \ - (0x4000UL) /*!< FLASH FCON: ESLDIS (Bitfield-Mask: 0x01) */ -#define FLASH_FCON_SLEEP_Pos \ - (15UL) /*!< FLASH FCON: SLEEP (Bit 15) */ -#define FLASH_FCON_SLEEP_Msk \ - (0x8000UL) /*!< FLASH FCON: SLEEP (Bitfield-Mask: 0x01) */ -#define FLASH_FCON_RPA_Pos \ - (16UL) /*!< FLASH FCON: RPA (Bit 16) */ -#define FLASH_FCON_RPA_Msk \ - (0x10000UL) /*!< FLASH FCON: RPA (Bitfield-Mask: 0x01) */ -#define FLASH_FCON_DCF_Pos \ - (17UL) /*!< FLASH FCON: DCF (Bit 17) */ -#define FLASH_FCON_DCF_Msk \ - (0x20000UL) /*!< FLASH FCON: DCF (Bitfield-Mask: 0x01) */ -#define FLASH_FCON_DDF_Pos \ - (18UL) /*!< FLASH FCON: DDF (Bit 18) */ -#define FLASH_FCON_DDF_Msk \ - (0x40000UL) /*!< FLASH FCON: DDF (Bitfield-Mask: 0x01) */ -#define FLASH_FCON_VOPERM_Pos \ - (24UL) /*!< FLASH FCON: VOPERM (Bit 24) */ -#define FLASH_FCON_VOPERM_Msk \ - (0x1000000UL) /*!< FLASH FCON: VOPERM (Bitfield-Mask: 0x01) */ -#define FLASH_FCON_SQERM_Pos \ - (25UL) /*!< FLASH FCON: SQERM (Bit 25) */ -#define FLASH_FCON_SQERM_Msk \ - (0x2000000UL) /*!< FLASH FCON: SQERM (Bitfield-Mask: 0x01) */ -#define FLASH_FCON_PROERM_Pos \ - (26UL) /*!< FLASH FCON: PROERM (Bit 26) */ -#define FLASH_FCON_PROERM_Msk \ - (0x4000000UL) /*!< FLASH FCON: PROERM (Bitfield-Mask: 0x01) */ -#define FLASH_FCON_PFSBERM_Pos \ - (27UL) /*!< FLASH FCON: PFSBERM (Bit 27) */ -#define FLASH_FCON_PFSBERM_Msk \ - (0x8000000UL) /*!< FLASH FCON: PFSBERM (Bitfield-Mask: 0x01) */ -#define FLASH_FCON_PFDBERM_Pos \ - (29UL) /*!< FLASH FCON: PFDBERM (Bit 29) */ -#define FLASH_FCON_PFDBERM_Msk \ - (0x20000000UL) /*!< FLASH FCON: PFDBERM (Bitfield-Mask: 0x01) */ -#define FLASH_FCON_EOBM_Pos \ - (31UL) /*!< FLASH FCON: EOBM (Bit 31) */ -#define FLASH_FCON_EOBM_Msk \ - (0x80000000UL) /*!< FLASH FCON: EOBM (Bitfield-Mask: 0x01) */ - -/* --------------------------------- FLASH_MARP --------------------------------- */ -#define FLASH_MARP_MARGIN_Pos \ - (0UL) /*!< FLASH MARP: MARGIN (Bit 0) */ -#define FLASH_MARP_MARGIN_Msk \ - (0xfUL) /*!< FLASH MARP: MARGIN (Bitfield-Mask: 0x0f) */ -#define FLASH_MARP_TRAPDIS_Pos \ - (15UL) /*!< FLASH MARP: TRAPDIS (Bit 15) */ -#define FLASH_MARP_TRAPDIS_Msk \ - (0x8000UL) /*!< FLASH MARP: TRAPDIS (Bitfield-Mask: 0x01) */ - -/* -------------------------------- FLASH_PROCON0 ------------------------------- */ -#define FLASH_PROCON0_S0L_Pos \ - (0UL) /*!< FLASH PROCON0: S0L (Bit 0) */ -#define FLASH_PROCON0_S0L_Msk \ - (0x1UL) /*!< FLASH PROCON0: S0L (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON0_S1L_Pos \ - (1UL) /*!< FLASH PROCON0: S1L (Bit 1) */ -#define FLASH_PROCON0_S1L_Msk \ - (0x2UL) /*!< FLASH PROCON0: S1L (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON0_S2L_Pos \ - (2UL) /*!< FLASH PROCON0: S2L (Bit 2) */ -#define FLASH_PROCON0_S2L_Msk \ - (0x4UL) /*!< FLASH PROCON0: S2L (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON0_S3L_Pos \ - (3UL) /*!< FLASH PROCON0: S3L (Bit 3) */ -#define FLASH_PROCON0_S3L_Msk \ - (0x8UL) /*!< FLASH PROCON0: S3L (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON0_S4L_Pos \ - (4UL) /*!< FLASH PROCON0: S4L (Bit 4) */ -#define FLASH_PROCON0_S4L_Msk \ - (0x10UL) /*!< FLASH PROCON0: S4L (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON0_S5L_Pos \ - (5UL) /*!< FLASH PROCON0: S5L (Bit 5) */ -#define FLASH_PROCON0_S5L_Msk \ - (0x20UL) /*!< FLASH PROCON0: S5L (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON0_S6L_Pos \ - (6UL) /*!< FLASH PROCON0: S6L (Bit 6) */ -#define FLASH_PROCON0_S6L_Msk \ - (0x40UL) /*!< FLASH PROCON0: S6L (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON0_S7L_Pos \ - (7UL) /*!< FLASH PROCON0: S7L (Bit 7) */ -#define FLASH_PROCON0_S7L_Msk \ - (0x80UL) /*!< FLASH PROCON0: S7L (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON0_S8L_Pos \ - (8UL) /*!< FLASH PROCON0: S8L (Bit 8) */ -#define FLASH_PROCON0_S8L_Msk \ - (0x100UL) /*!< FLASH PROCON0: S8L (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON0_S9L_Pos \ - (9UL) /*!< FLASH PROCON0: S9L (Bit 9) */ -#define FLASH_PROCON0_S9L_Msk \ - (0x200UL) /*!< FLASH PROCON0: S9L (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON0_RPRO_Pos \ - (15UL) /*!< FLASH PROCON0: RPRO (Bit 15) */ -#define FLASH_PROCON0_RPRO_Msk \ - (0x8000UL) /*!< FLASH PROCON0: RPRO (Bitfield-Mask: 0x01) */ - -/* -------------------------------- FLASH_PROCON1 ------------------------------- */ -#define FLASH_PROCON1_S0L_Pos \ - (0UL) /*!< FLASH PROCON1: S0L (Bit 0) */ -#define FLASH_PROCON1_S0L_Msk \ - (0x1UL) /*!< FLASH PROCON1: S0L (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON1_S1L_Pos \ - (1UL) /*!< FLASH PROCON1: S1L (Bit 1) */ -#define FLASH_PROCON1_S1L_Msk \ - (0x2UL) /*!< FLASH PROCON1: S1L (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON1_S2L_Pos \ - (2UL) /*!< FLASH PROCON1: S2L (Bit 2) */ -#define FLASH_PROCON1_S2L_Msk \ - (0x4UL) /*!< FLASH PROCON1: S2L (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON1_S3L_Pos \ - (3UL) /*!< FLASH PROCON1: S3L (Bit 3) */ -#define FLASH_PROCON1_S3L_Msk \ - (0x8UL) /*!< FLASH PROCON1: S3L (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON1_S4L_Pos \ - (4UL) /*!< FLASH PROCON1: S4L (Bit 4) */ -#define FLASH_PROCON1_S4L_Msk \ - (0x10UL) /*!< FLASH PROCON1: S4L (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON1_S5L_Pos \ - (5UL) /*!< FLASH PROCON1: S5L (Bit 5) */ -#define FLASH_PROCON1_S5L_Msk \ - (0x20UL) /*!< FLASH PROCON1: S5L (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON1_S6L_Pos \ - (6UL) /*!< FLASH PROCON1: S6L (Bit 6) */ -#define FLASH_PROCON1_S6L_Msk \ - (0x40UL) /*!< FLASH PROCON1: S6L (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON1_S7L_Pos \ - (7UL) /*!< FLASH PROCON1: S7L (Bit 7) */ -#define FLASH_PROCON1_S7L_Msk \ - (0x80UL) /*!< FLASH PROCON1: S7L (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON1_S8L_Pos \ - (8UL) /*!< FLASH PROCON1: S8L (Bit 8) */ -#define FLASH_PROCON1_S8L_Msk \ - (0x100UL) /*!< FLASH PROCON1: S8L (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON1_S9L_Pos \ - (9UL) /*!< FLASH PROCON1: S9L (Bit 9) */ -#define FLASH_PROCON1_S9L_Msk \ - (0x200UL) /*!< FLASH PROCON1: S9L (Bitfield-Mask: 0x01) */ - -/* -------------------------------- FLASH_PROCON2 ------------------------------- */ -#define FLASH_PROCON2_S0ROM_Pos \ - (0UL) /*!< FLASH PROCON2: S0ROM (Bit 0) */ -#define FLASH_PROCON2_S0ROM_Msk \ - (0x1UL) /*!< FLASH PROCON2: S0ROM (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON2_S1ROM_Pos \ - (1UL) /*!< FLASH PROCON2: S1ROM (Bit 1) */ -#define FLASH_PROCON2_S1ROM_Msk \ - (0x2UL) /*!< FLASH PROCON2: S1ROM (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON2_S2ROM_Pos \ - (2UL) /*!< FLASH PROCON2: S2ROM (Bit 2) */ -#define FLASH_PROCON2_S2ROM_Msk \ - (0x4UL) /*!< FLASH PROCON2: S2ROM (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON2_S3ROM_Pos \ - (3UL) /*!< FLASH PROCON2: S3ROM (Bit 3) */ -#define FLASH_PROCON2_S3ROM_Msk \ - (0x8UL) /*!< FLASH PROCON2: S3ROM (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON2_S4ROM_Pos \ - (4UL) /*!< FLASH PROCON2: S4ROM (Bit 4) */ -#define FLASH_PROCON2_S4ROM_Msk \ - (0x10UL) /*!< FLASH PROCON2: S4ROM (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON2_S5ROM_Pos \ - (5UL) /*!< FLASH PROCON2: S5ROM (Bit 5) */ -#define FLASH_PROCON2_S5ROM_Msk \ - (0x20UL) /*!< FLASH PROCON2: S5ROM (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON2_S6ROM_Pos \ - (6UL) /*!< FLASH PROCON2: S6ROM (Bit 6) */ -#define FLASH_PROCON2_S6ROM_Msk \ - (0x40UL) /*!< FLASH PROCON2: S6ROM (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON2_S7ROM_Pos \ - (7UL) /*!< FLASH PROCON2: S7ROM (Bit 7) */ -#define FLASH_PROCON2_S7ROM_Msk \ - (0x80UL) /*!< FLASH PROCON2: S7ROM (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON2_S8ROM_Pos \ - (8UL) /*!< FLASH PROCON2: S8ROM (Bit 8) */ -#define FLASH_PROCON2_S8ROM_Msk \ - (0x100UL) /*!< FLASH PROCON2: S8ROM (Bitfield-Mask: 0x01) */ -#define FLASH_PROCON2_S9ROM_Pos \ - (9UL) /*!< FLASH PROCON2: S9ROM (Bit 9) */ -#define FLASH_PROCON2_S9ROM_Msk \ - (0x200UL) /*!< FLASH PROCON2: S9ROM (Bitfield-Mask: 0x01) */ - -/* ================================================================================ */ -/* ================ struct 'PREF' Position & Mask ================ */ -/* ================================================================================ */ - -/* ---------------------------------- PREF_PCON --------------------------------- */ -#define PREF_PCON_IBYP_Pos (0UL) /*!< PREF PCON: IBYP (Bit 0) */ -#define PREF_PCON_IBYP_Msk \ - (0x1UL) /*!< PREF PCON: IBYP (Bitfield-Mask: 0x01) */ -#define PREF_PCON_IINV_Pos (1UL) /*!< PREF PCON: IINV (Bit 1) */ -#define PREF_PCON_IINV_Msk \ - (0x2UL) /*!< PREF PCON: IINV (Bitfield-Mask: 0x01) */ - -/* ================================================================================ */ -/* ================ Group 'PMU' Position & Mask ================ */ -/* ================================================================================ */ - -/* ----------------------------------- PMU_ID ----------------------------------- */ -#define PMU_ID_MOD_REV_Pos (0UL) /*!< PMU ID: MOD_REV (Bit 0) */ -#define PMU_ID_MOD_REV_Msk \ - (0xffUL) /*!< PMU ID: MOD_REV (Bitfield-Mask: 0xff) */ -#define PMU_ID_MOD_TYPE_Pos \ - (8UL) /*!< PMU ID: MOD_TYPE (Bit 8) */ -#define PMU_ID_MOD_TYPE_Msk \ - (0xff00UL) /*!< PMU ID: MOD_TYPE (Bitfield-Mask: 0xff) */ -#define PMU_ID_MOD_NUMBER_Pos \ - (16UL) /*!< PMU ID: MOD_NUMBER (Bit 16) */ -#define PMU_ID_MOD_NUMBER_Msk \ - (0xffff0000UL) /*!< PMU ID: MOD_NUMBER (Bitfield-Mask: 0xffff) */ - -/* ================================================================================ */ -/* ================ struct 'WDT' Position & Mask ================ */ -/* ================================================================================ */ - -/* ----------------------------------- WDT_ID ----------------------------------- */ -#define WDT_ID_MOD_REV_Pos (0UL) /*!< WDT ID: MOD_REV (Bit 0) */ -#define WDT_ID_MOD_REV_Msk \ - (0xffUL) /*!< WDT ID: MOD_REV (Bitfield-Mask: 0xff) */ -#define WDT_ID_MOD_TYPE_Pos \ - (8UL) /*!< WDT ID: MOD_TYPE (Bit 8) */ -#define WDT_ID_MOD_TYPE_Msk \ - (0xff00UL) /*!< WDT ID: MOD_TYPE (Bitfield-Mask: 0xff) */ -#define WDT_ID_MOD_NUMBER_Pos \ - (16UL) /*!< WDT ID: MOD_NUMBER (Bit 16) */ -#define WDT_ID_MOD_NUMBER_Msk \ - (0xffff0000UL) /*!< WDT ID: MOD_NUMBER (Bitfield-Mask: 0xffff) */ - -/* ----------------------------------- WDT_CTR ---------------------------------- */ -#define WDT_CTR_ENB_Pos (0UL) /*!< WDT CTR: ENB (Bit 0) */ -#define WDT_CTR_ENB_Msk (0x1UL) /*!< WDT CTR: ENB (Bitfield-Mask: 0x01) */ -#define WDT_CTR_PRE_Pos (1UL) /*!< WDT CTR: PRE (Bit 1) */ -#define WDT_CTR_PRE_Msk (0x2UL) /*!< WDT CTR: PRE (Bitfield-Mask: 0x01) */ -#define WDT_CTR_DSP_Pos (4UL) /*!< WDT CTR: DSP (Bit 4) */ -#define WDT_CTR_DSP_Msk (0x10UL) /*!< WDT CTR: DSP (Bitfield-Mask: 0x01) */ -#define WDT_CTR_SPW_Pos (8UL) /*!< WDT CTR: SPW (Bit 8) */ -#define WDT_CTR_SPW_Msk \ - (0xff00UL) /*!< WDT CTR: SPW (Bitfield-Mask: 0xff) */ - -/* ----------------------------------- WDT_SRV ---------------------------------- */ -#define WDT_SRV_SRV_Pos (0UL) /*!< WDT SRV: SRV (Bit 0) */ -#define WDT_SRV_SRV_Msk \ - (0xffffffffUL) /*!< WDT SRV: SRV (Bitfield-Mask: 0xffffffff) */ - -/* ----------------------------------- WDT_TIM ---------------------------------- */ -#define WDT_TIM_TIM_Pos (0UL) /*!< WDT TIM: TIM (Bit 0) */ -#define WDT_TIM_TIM_Msk \ - (0xffffffffUL) /*!< WDT TIM: TIM (Bitfield-Mask: 0xffffffff) */ - -/* ----------------------------------- WDT_WLB ---------------------------------- */ -#define WDT_WLB_WLB_Pos (0UL) /*!< WDT WLB: WLB (Bit 0) */ -#define WDT_WLB_WLB_Msk \ - (0xffffffffUL) /*!< WDT WLB: WLB (Bitfield-Mask: 0xffffffff) */ - -/* ----------------------------------- WDT_WUB ---------------------------------- */ -#define WDT_WUB_WUB_Pos (0UL) /*!< WDT WUB: WUB (Bit 0) */ -#define WDT_WUB_WUB_Msk \ - (0xffffffffUL) /*!< WDT WUB: WUB (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------------- WDT_WDTSTS --------------------------------- */ -#define WDT_WDTSTS_ALMS_Pos \ - (0UL) /*!< WDT WDTSTS: ALMS (Bit 0) */ -#define WDT_WDTSTS_ALMS_Msk \ - (0x1UL) /*!< WDT WDTSTS: ALMS (Bitfield-Mask: 0x01) */ - -/* --------------------------------- WDT_WDTCLR --------------------------------- */ -#define WDT_WDTCLR_ALMC_Pos \ - (0UL) /*!< WDT WDTCLR: ALMC (Bit 0) */ -#define WDT_WDTCLR_ALMC_Msk \ - (0x1UL) /*!< WDT WDTCLR: ALMC (Bitfield-Mask: 0x01) */ - -/* ================================================================================ */ -/* ================ struct 'RTC' Position & Mask ================ */ -/* ================================================================================ */ - -/* ----------------------------------- RTC_ID ----------------------------------- */ -#define RTC_ID_MOD_REV_Pos (0UL) /*!< RTC ID: MOD_REV (Bit 0) */ -#define RTC_ID_MOD_REV_Msk \ - (0xffUL) /*!< RTC ID: MOD_REV (Bitfield-Mask: 0xff) */ -#define RTC_ID_MOD_TYPE_Pos \ - (8UL) /*!< RTC ID: MOD_TYPE (Bit 8) */ -#define RTC_ID_MOD_TYPE_Msk \ - (0xff00UL) /*!< RTC ID: MOD_TYPE (Bitfield-Mask: 0xff) */ -#define RTC_ID_MOD_NUMBER_Pos \ - (16UL) /*!< RTC ID: MOD_NUMBER (Bit 16) */ -#define RTC_ID_MOD_NUMBER_Msk \ - (0xffff0000UL) /*!< RTC ID: MOD_NUMBER (Bitfield-Mask: 0xffff) */ - -/* ----------------------------------- RTC_CTR ---------------------------------- */ -#define RTC_CTR_ENB_Pos (0UL) /*!< RTC CTR: ENB (Bit 0) */ -#define RTC_CTR_ENB_Msk (0x1UL) /*!< RTC CTR: ENB (Bitfield-Mask: 0x01) */ -#define RTC_CTR_TAE_Pos (2UL) /*!< RTC CTR: TAE (Bit 2) */ -#define RTC_CTR_TAE_Msk (0x4UL) /*!< RTC CTR: TAE (Bitfield-Mask: 0x01) */ -#define RTC_CTR_ESEC_Pos (8UL) /*!< RTC CTR: ESEC (Bit 8) */ -#define RTC_CTR_ESEC_Msk \ - (0x100UL) /*!< RTC CTR: ESEC (Bitfield-Mask: 0x01) */ -#define RTC_CTR_EMIC_Pos (9UL) /*!< RTC CTR: EMIC (Bit 9) */ -#define RTC_CTR_EMIC_Msk \ - (0x200UL) /*!< RTC CTR: EMIC (Bitfield-Mask: 0x01) */ -#define RTC_CTR_EHOC_Pos (10UL) /*!< RTC CTR: EHOC (Bit 10) */ -#define RTC_CTR_EHOC_Msk \ - (0x400UL) /*!< RTC CTR: EHOC (Bitfield-Mask: 0x01) */ -#define RTC_CTR_EDAC_Pos (11UL) /*!< RTC CTR: EDAC (Bit 11) */ -#define RTC_CTR_EDAC_Msk \ - (0x800UL) /*!< RTC CTR: EDAC (Bitfield-Mask: 0x01) */ -#define RTC_CTR_EMOC_Pos (13UL) /*!< RTC CTR: EMOC (Bit 13) */ -#define RTC_CTR_EMOC_Msk \ - (0x2000UL) /*!< RTC CTR: EMOC (Bitfield-Mask: 0x01) */ -#define RTC_CTR_EYEC_Pos (14UL) /*!< RTC CTR: EYEC (Bit 14) */ -#define RTC_CTR_EYEC_Msk \ - (0x4000UL) /*!< RTC CTR: EYEC (Bitfield-Mask: 0x01) */ -#define RTC_CTR_DIV_Pos (16UL) /*!< RTC CTR: DIV (Bit 16) */ -#define RTC_CTR_DIV_Msk \ - (0xffff0000UL) /*!< RTC CTR: DIV (Bitfield-Mask: 0xffff) */ - -/* --------------------------------- RTC_RAWSTAT -------------------------------- */ -#define RTC_RAWSTAT_RPSE_Pos \ - (0UL) /*!< RTC RAWSTAT: RPSE (Bit 0) */ -#define RTC_RAWSTAT_RPSE_Msk \ - (0x1UL) /*!< RTC RAWSTAT: RPSE (Bitfield-Mask: 0x01) */ -#define RTC_RAWSTAT_RPMI_Pos \ - (1UL) /*!< RTC RAWSTAT: RPMI (Bit 1) */ -#define RTC_RAWSTAT_RPMI_Msk \ - (0x2UL) /*!< RTC RAWSTAT: RPMI (Bitfield-Mask: 0x01) */ -#define RTC_RAWSTAT_RPHO_Pos \ - (2UL) /*!< RTC RAWSTAT: RPHO (Bit 2) */ -#define RTC_RAWSTAT_RPHO_Msk \ - (0x4UL) /*!< RTC RAWSTAT: RPHO (Bitfield-Mask: 0x01) */ -#define RTC_RAWSTAT_RPDA_Pos \ - (3UL) /*!< RTC RAWSTAT: RPDA (Bit 3) */ -#define RTC_RAWSTAT_RPDA_Msk \ - (0x8UL) /*!< RTC RAWSTAT: RPDA (Bitfield-Mask: 0x01) */ -#define RTC_RAWSTAT_RPMO_Pos \ - (5UL) /*!< RTC RAWSTAT: RPMO (Bit 5) */ -#define RTC_RAWSTAT_RPMO_Msk \ - (0x20UL) /*!< RTC RAWSTAT: RPMO (Bitfield-Mask: 0x01) */ -#define RTC_RAWSTAT_RPYE_Pos \ - (6UL) /*!< RTC RAWSTAT: RPYE (Bit 6) */ -#define RTC_RAWSTAT_RPYE_Msk \ - (0x40UL) /*!< RTC RAWSTAT: RPYE (Bitfield-Mask: 0x01) */ -#define RTC_RAWSTAT_RAI_Pos \ - (8UL) /*!< RTC RAWSTAT: RAI (Bit 8) */ -#define RTC_RAWSTAT_RAI_Msk \ - (0x100UL) /*!< RTC RAWSTAT: RAI (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- RTC_STSSR --------------------------------- */ -#define RTC_STSSR_SPSE_Pos (0UL) /*!< RTC STSSR: SPSE (Bit 0) */ -#define RTC_STSSR_SPSE_Msk \ - (0x1UL) /*!< RTC STSSR: SPSE (Bitfield-Mask: 0x01) */ -#define RTC_STSSR_SPMI_Pos (1UL) /*!< RTC STSSR: SPMI (Bit 1) */ -#define RTC_STSSR_SPMI_Msk \ - (0x2UL) /*!< RTC STSSR: SPMI (Bitfield-Mask: 0x01) */ -#define RTC_STSSR_SPHO_Pos (2UL) /*!< RTC STSSR: SPHO (Bit 2) */ -#define RTC_STSSR_SPHO_Msk \ - (0x4UL) /*!< RTC STSSR: SPHO (Bitfield-Mask: 0x01) */ -#define RTC_STSSR_SPDA_Pos (3UL) /*!< RTC STSSR: SPDA (Bit 3) */ -#define RTC_STSSR_SPDA_Msk \ - (0x8UL) /*!< RTC STSSR: SPDA (Bitfield-Mask: 0x01) */ -#define RTC_STSSR_SPMO_Pos (5UL) /*!< RTC STSSR: SPMO (Bit 5) */ -#define RTC_STSSR_SPMO_Msk \ - (0x20UL) /*!< RTC STSSR: SPMO (Bitfield-Mask: 0x01) */ -#define RTC_STSSR_SPYE_Pos (6UL) /*!< RTC STSSR: SPYE (Bit 6) */ -#define RTC_STSSR_SPYE_Msk \ - (0x40UL) /*!< RTC STSSR: SPYE (Bitfield-Mask: 0x01) */ -#define RTC_STSSR_SAI_Pos (8UL) /*!< RTC STSSR: SAI (Bit 8) */ -#define RTC_STSSR_SAI_Msk \ - (0x100UL) /*!< RTC STSSR: SAI (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- RTC_MSKSR --------------------------------- */ -#define RTC_MSKSR_MPSE_Pos (0UL) /*!< RTC MSKSR: MPSE (Bit 0) */ -#define RTC_MSKSR_MPSE_Msk \ - (0x1UL) /*!< RTC MSKSR: MPSE (Bitfield-Mask: 0x01) */ -#define RTC_MSKSR_MPMI_Pos (1UL) /*!< RTC MSKSR: MPMI (Bit 1) */ -#define RTC_MSKSR_MPMI_Msk \ - (0x2UL) /*!< RTC MSKSR: MPMI (Bitfield-Mask: 0x01) */ -#define RTC_MSKSR_MPHO_Pos (2UL) /*!< RTC MSKSR: MPHO (Bit 2) */ -#define RTC_MSKSR_MPHO_Msk \ - (0x4UL) /*!< RTC MSKSR: MPHO (Bitfield-Mask: 0x01) */ -#define RTC_MSKSR_MPDA_Pos (3UL) /*!< RTC MSKSR: MPDA (Bit 3) */ -#define RTC_MSKSR_MPDA_Msk \ - (0x8UL) /*!< RTC MSKSR: MPDA (Bitfield-Mask: 0x01) */ -#define RTC_MSKSR_MPMO_Pos (5UL) /*!< RTC MSKSR: MPMO (Bit 5) */ -#define RTC_MSKSR_MPMO_Msk \ - (0x20UL) /*!< RTC MSKSR: MPMO (Bitfield-Mask: 0x01) */ -#define RTC_MSKSR_MPYE_Pos (6UL) /*!< RTC MSKSR: MPYE (Bit 6) */ -#define RTC_MSKSR_MPYE_Msk \ - (0x40UL) /*!< RTC MSKSR: MPYE (Bitfield-Mask: 0x01) */ -#define RTC_MSKSR_MAI_Pos (8UL) /*!< RTC MSKSR: MAI (Bit 8) */ -#define RTC_MSKSR_MAI_Msk \ - (0x100UL) /*!< RTC MSKSR: MAI (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- RTC_CLRSR --------------------------------- */ -#define RTC_CLRSR_RPSE_Pos (0UL) /*!< RTC CLRSR: RPSE (Bit 0) */ -#define RTC_CLRSR_RPSE_Msk \ - (0x1UL) /*!< RTC CLRSR: RPSE (Bitfield-Mask: 0x01) */ -#define RTC_CLRSR_RPMI_Pos (1UL) /*!< RTC CLRSR: RPMI (Bit 1) */ -#define RTC_CLRSR_RPMI_Msk \ - (0x2UL) /*!< RTC CLRSR: RPMI (Bitfield-Mask: 0x01) */ -#define RTC_CLRSR_RPHO_Pos (2UL) /*!< RTC CLRSR: RPHO (Bit 2) */ -#define RTC_CLRSR_RPHO_Msk \ - (0x4UL) /*!< RTC CLRSR: RPHO (Bitfield-Mask: 0x01) */ -#define RTC_CLRSR_RPDA_Pos (3UL) /*!< RTC CLRSR: RPDA (Bit 3) */ -#define RTC_CLRSR_RPDA_Msk \ - (0x8UL) /*!< RTC CLRSR: RPDA (Bitfield-Mask: 0x01) */ -#define RTC_CLRSR_RPMO_Pos (5UL) /*!< RTC CLRSR: RPMO (Bit 5) */ -#define RTC_CLRSR_RPMO_Msk \ - (0x20UL) /*!< RTC CLRSR: RPMO (Bitfield-Mask: 0x01) */ -#define RTC_CLRSR_RPYE_Pos (6UL) /*!< RTC CLRSR: RPYE (Bit 6) */ -#define RTC_CLRSR_RPYE_Msk \ - (0x40UL) /*!< RTC CLRSR: RPYE (Bitfield-Mask: 0x01) */ -#define RTC_CLRSR_RAI_Pos (8UL) /*!< RTC CLRSR: RAI (Bit 8) */ -#define RTC_CLRSR_RAI_Msk \ - (0x100UL) /*!< RTC CLRSR: RAI (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- RTC_ATIM0 --------------------------------- */ -#define RTC_ATIM0_ASE_Pos (0UL) /*!< RTC ATIM0: ASE (Bit 0) */ -#define RTC_ATIM0_ASE_Msk \ - (0x3fUL) /*!< RTC ATIM0: ASE (Bitfield-Mask: 0x3f) */ -#define RTC_ATIM0_AMI_Pos (8UL) /*!< RTC ATIM0: AMI (Bit 8) */ -#define RTC_ATIM0_AMI_Msk \ - (0x3f00UL) /*!< RTC ATIM0: AMI (Bitfield-Mask: 0x3f) */ -#define RTC_ATIM0_AHO_Pos (16UL) /*!< RTC ATIM0: AHO (Bit 16) */ -#define RTC_ATIM0_AHO_Msk \ - (0x1f0000UL) /*!< RTC ATIM0: AHO (Bitfield-Mask: 0x1f) */ -#define RTC_ATIM0_ADA_Pos (24UL) /*!< RTC ATIM0: ADA (Bit 24) */ -#define RTC_ATIM0_ADA_Msk \ - (0x1f000000UL) /*!< RTC ATIM0: ADA (Bitfield-Mask: 0x1f) */ - -/* ---------------------------------- RTC_ATIM1 --------------------------------- */ -#define RTC_ATIM1_AMO_Pos (8UL) /*!< RTC ATIM1: AMO (Bit 8) */ -#define RTC_ATIM1_AMO_Msk \ - (0xf00UL) /*!< RTC ATIM1: AMO (Bitfield-Mask: 0x0f) */ -#define RTC_ATIM1_AYE_Pos (16UL) /*!< RTC ATIM1: AYE (Bit 16) */ -#define RTC_ATIM1_AYE_Msk \ - (0xffff0000UL) /*!< RTC ATIM1: AYE (Bitfield-Mask: 0xffff) */ - -/* ---------------------------------- RTC_TIM0 ---------------------------------- */ -#define RTC_TIM0_SE_Pos (0UL) /*!< RTC TIM0: SE (Bit 0) */ -#define RTC_TIM0_SE_Msk (0x3fUL) /*!< RTC TIM0: SE (Bitfield-Mask: 0x3f) */ -#define RTC_TIM0_MI_Pos (8UL) /*!< RTC TIM0: MI (Bit 8) */ -#define RTC_TIM0_MI_Msk \ - (0x3f00UL) /*!< RTC TIM0: MI (Bitfield-Mask: 0x3f) */ -#define RTC_TIM0_HO_Pos (16UL) /*!< RTC TIM0: HO (Bit 16) */ -#define RTC_TIM0_HO_Msk \ - (0x1f0000UL) /*!< RTC TIM0: HO (Bitfield-Mask: 0x1f) */ -#define RTC_TIM0_DA_Pos (24UL) /*!< RTC TIM0: DA (Bit 24) */ -#define RTC_TIM0_DA_Msk \ - (0x1f000000UL) /*!< RTC TIM0: DA (Bitfield-Mask: 0x1f) */ - -/* ---------------------------------- RTC_TIM1 ---------------------------------- */ -#define RTC_TIM1_DAWE_Pos (0UL) /*!< RTC TIM1: DAWE (Bit 0) */ -#define RTC_TIM1_DAWE_Msk \ - (0x7UL) /*!< RTC TIM1: DAWE (Bitfield-Mask: 0x07) */ -#define RTC_TIM1_MO_Pos (8UL) /*!< RTC TIM1: MO (Bit 8) */ -#define RTC_TIM1_MO_Msk \ - (0xf00UL) /*!< RTC TIM1: MO (Bitfield-Mask: 0x0f) */ -#define RTC_TIM1_YE_Pos (16UL) /*!< RTC TIM1: YE (Bit 16) */ -#define RTC_TIM1_YE_Msk \ - (0xffff0000UL) /*!< RTC TIM1: YE (Bitfield-Mask: 0xffff) */ - -/* ================================================================================ */ -/* ================ struct 'SCU_CLK' Position & Mask ================ */ -/* ================================================================================ */ - -/* ------------------------------- SCU_CLK_CLKSTAT ------------------------------ */ -#define SCU_CLK_CLKSTAT_USBCST_Pos \ - (0UL) /*!< SCU_CLK CLKSTAT: USBCST (Bit 0) */ -#define SCU_CLK_CLKSTAT_USBCST_Msk \ - (0x1UL) /*!< SCU_CLK CLKSTAT: USBCST (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CLKSTAT_ETH0CST_Pos \ - (2UL) /*!< SCU_CLK CLKSTAT: ETH0CST (Bit 2) */ -#define SCU_CLK_CLKSTAT_ETH0CST_Msk \ - (0x4UL) /*!< SCU_CLK CLKSTAT: ETH0CST (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CLKSTAT_CCUCST_Pos \ - (4UL) /*!< SCU_CLK CLKSTAT: CCUCST (Bit 4) */ -#define SCU_CLK_CLKSTAT_CCUCST_Msk \ - (0x10UL) /*!< SCU_CLK CLKSTAT: CCUCST (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CLKSTAT_WDTCST_Pos \ - (5UL) /*!< SCU_CLK CLKSTAT: WDTCST (Bit 5) */ -#define SCU_CLK_CLKSTAT_WDTCST_Msk \ - (0x20UL) /*!< SCU_CLK CLKSTAT: WDTCST (Bitfield-Mask: 0x01) */ - -/* ------------------------------- SCU_CLK_CLKSET ------------------------------- */ -#define SCU_CLK_CLKSET_USBCEN_Pos \ - (0UL) /*!< SCU_CLK CLKSET: USBCEN (Bit 0) */ -#define SCU_CLK_CLKSET_USBCEN_Msk \ - (0x1UL) /*!< SCU_CLK CLKSET: USBCEN (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CLKSET_ETH0CEN_Pos \ - (2UL) /*!< SCU_CLK CLKSET: ETH0CEN (Bit 2) */ -#define SCU_CLK_CLKSET_ETH0CEN_Msk \ - (0x4UL) /*!< SCU_CLK CLKSET: ETH0CEN (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CLKSET_CCUCEN_Pos \ - (4UL) /*!< SCU_CLK CLKSET: CCUCEN (Bit 4) */ -#define SCU_CLK_CLKSET_CCUCEN_Msk \ - (0x10UL) /*!< SCU_CLK CLKSET: CCUCEN (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CLKSET_WDTCEN_Pos \ - (5UL) /*!< SCU_CLK CLKSET: WDTCEN (Bit 5) */ -#define SCU_CLK_CLKSET_WDTCEN_Msk \ - (0x20UL) /*!< SCU_CLK CLKSET: WDTCEN (Bitfield-Mask: 0x01) */ - -/* ------------------------------- SCU_CLK_CLKCLR ------------------------------- */ -#define SCU_CLK_CLKCLR_USBCDI_Pos \ - (0UL) /*!< SCU_CLK CLKCLR: USBCDI (Bit 0) */ -#define SCU_CLK_CLKCLR_USBCDI_Msk \ - (0x1UL) /*!< SCU_CLK CLKCLR: USBCDI (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CLKCLR_ETH0CDI_Pos \ - (2UL) /*!< SCU_CLK CLKCLR: ETH0CDI (Bit 2) */ -#define SCU_CLK_CLKCLR_ETH0CDI_Msk \ - (0x4UL) /*!< SCU_CLK CLKCLR: ETH0CDI (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CLKCLR_CCUCDI_Pos \ - (4UL) /*!< SCU_CLK CLKCLR: CCUCDI (Bit 4) */ -#define SCU_CLK_CLKCLR_CCUCDI_Msk \ - (0x10UL) /*!< SCU_CLK CLKCLR: CCUCDI (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CLKCLR_WDTCDI_Pos \ - (5UL) /*!< SCU_CLK CLKCLR: WDTCDI (Bit 5) */ -#define SCU_CLK_CLKCLR_WDTCDI_Msk \ - (0x20UL) /*!< SCU_CLK CLKCLR: WDTCDI (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_CLK_SYSCLKCR ------------------------------ */ -#define SCU_CLK_SYSCLKCR_SYSDIV_Pos \ - (0UL) /*!< SCU_CLK SYSCLKCR: SYSDIV (Bit 0) */ -#define SCU_CLK_SYSCLKCR_SYSDIV_Msk \ - (0xffUL) /*!< SCU_CLK SYSCLKCR: SYSDIV (Bitfield-Mask: 0xff) */ -#define SCU_CLK_SYSCLKCR_SYSSEL_Pos \ - (16UL) /*!< SCU_CLK SYSCLKCR: SYSSEL (Bit 16) */ -#define SCU_CLK_SYSCLKCR_SYSSEL_Msk \ - (0x10000UL) /*!< SCU_CLK SYSCLKCR: SYSSEL (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_CLK_CPUCLKCR ------------------------------ */ -#define SCU_CLK_CPUCLKCR_CPUDIV_Pos \ - (0UL) /*!< SCU_CLK CPUCLKCR: CPUDIV (Bit 0) */ -#define SCU_CLK_CPUCLKCR_CPUDIV_Msk \ - (0x1UL) /*!< SCU_CLK CPUCLKCR: CPUDIV (Bitfield-Mask: 0x01) */ - -/* ------------------------------- SCU_CLK_PBCLKCR ------------------------------ */ -#define SCU_CLK_PBCLKCR_PBDIV_Pos \ - (0UL) /*!< SCU_CLK PBCLKCR: PBDIV (Bit 0) */ -#define SCU_CLK_PBCLKCR_PBDIV_Msk \ - (0x1UL) /*!< SCU_CLK PBCLKCR: PBDIV (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_CLK_USBCLKCR ------------------------------ */ -#define SCU_CLK_USBCLKCR_USBDIV_Pos \ - (0UL) /*!< SCU_CLK USBCLKCR: USBDIV (Bit 0) */ -#define SCU_CLK_USBCLKCR_USBDIV_Msk \ - (0x7UL) /*!< SCU_CLK USBCLKCR: USBDIV (Bitfield-Mask: 0x07) */ -#define SCU_CLK_USBCLKCR_USBSEL_Pos \ - (16UL) /*!< SCU_CLK USBCLKCR: USBSEL (Bit 16) */ -#define SCU_CLK_USBCLKCR_USBSEL_Msk \ - (0x10000UL) /*!< SCU_CLK USBCLKCR: USBSEL (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_CLK_CCUCLKCR ------------------------------ */ -#define SCU_CLK_CCUCLKCR_CCUDIV_Pos \ - (0UL) /*!< SCU_CLK CCUCLKCR: CCUDIV (Bit 0) */ -#define SCU_CLK_CCUCLKCR_CCUDIV_Msk \ - (0x1UL) /*!< SCU_CLK CCUCLKCR: CCUDIV (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_CLK_WDTCLKCR ------------------------------ */ -#define SCU_CLK_WDTCLKCR_WDTDIV_Pos \ - (0UL) /*!< SCU_CLK WDTCLKCR: WDTDIV (Bit 0) */ -#define SCU_CLK_WDTCLKCR_WDTDIV_Msk \ - (0xffUL) /*!< SCU_CLK WDTCLKCR: WDTDIV (Bitfield-Mask: 0xff) */ -#define SCU_CLK_WDTCLKCR_WDTSEL_Pos \ - (16UL) /*!< SCU_CLK WDTCLKCR: WDTSEL (Bit 16) */ -#define SCU_CLK_WDTCLKCR_WDTSEL_Msk \ - (0x30000UL) /*!< SCU_CLK WDTCLKCR: WDTSEL (Bitfield-Mask: 0x03) */ - -/* ------------------------------ SCU_CLK_EXTCLKCR ------------------------------ */ -#define SCU_CLK_EXTCLKCR_ECKSEL_Pos \ - (0UL) /*!< SCU_CLK EXTCLKCR: ECKSEL (Bit 0) */ -#define SCU_CLK_EXTCLKCR_ECKSEL_Msk \ - (0x7UL) /*!< SCU_CLK EXTCLKCR: ECKSEL (Bitfield-Mask: 0x07) */ -#define SCU_CLK_EXTCLKCR_ECKDIV_Pos \ - (16UL) /*!< SCU_CLK EXTCLKCR: ECKDIV (Bit 16) */ -#define SCU_CLK_EXTCLKCR_ECKDIV_Msk \ - (0x1ff0000UL) /*!< SCU_CLK EXTCLKCR: ECKDIV (Bitfield-Mask: 0x1ff) */ - -/* ----------------------------- SCU_CLK_MLINKCLKCR ----------------------------- */ -#define SCU_CLK_MLINKCLKCR_SYSDIV_Pos \ - (0UL) /*!< SCU_CLK MLINKCLKCR: SYSDIV (Bit 0) */ -#define SCU_CLK_MLINKCLKCR_SYSDIV_Msk \ - (0xffUL) /*!< SCU_CLK MLINKCLKCR: SYSDIV (Bitfield-Mask: 0xff) */ -#define SCU_CLK_MLINKCLKCR_SYSSEL_Pos \ - (8UL) /*!< SCU_CLK MLINKCLKCR: SYSSEL (Bit 8) */ -#define SCU_CLK_MLINKCLKCR_SYSSEL_Msk \ - (0x100UL) /*!< SCU_CLK MLINKCLKCR: SYSSEL (Bitfield-Mask: 0x01) */ -#define SCU_CLK_MLINKCLKCR_CPUDIV_Pos \ - (10UL) /*!< SCU_CLK MLINKCLKCR: CPUDIV (Bit 10) */ -#define SCU_CLK_MLINKCLKCR_CPUDIV_Msk \ - (0x400UL) /*!< SCU_CLK MLINKCLKCR: CPUDIV (Bitfield-Mask: 0x01) */ -#define SCU_CLK_MLINKCLKCR_PBDIV_Pos \ - (12UL) /*!< SCU_CLK MLINKCLKCR: PBDIV (Bit 12) */ -#define SCU_CLK_MLINKCLKCR_PBDIV_Msk \ - (0x1000UL) /*!< SCU_CLK MLINKCLKCR: PBDIV (Bitfield-Mask: 0x01) */ -#define SCU_CLK_MLINKCLKCR_CCUDIV_Pos \ - (14UL) /*!< SCU_CLK MLINKCLKCR: CCUDIV (Bit 14) */ -#define SCU_CLK_MLINKCLKCR_CCUDIV_Msk \ - (0x4000UL) /*!< SCU_CLK MLINKCLKCR: CCUDIV (Bitfield-Mask: 0x01) */ -#define SCU_CLK_MLINKCLKCR_WDTDIV_Pos \ - (16UL) /*!< SCU_CLK MLINKCLKCR: WDTDIV (Bit 16) */ -#define SCU_CLK_MLINKCLKCR_WDTDIV_Msk \ - (0xff0000UL) /*!< SCU_CLK MLINKCLKCR: WDTDIV (Bitfield-Mask: 0xff) */ -#define SCU_CLK_MLINKCLKCR_WDTSEL_Pos \ - (24UL) /*!< SCU_CLK MLINKCLKCR: WDTSEL (Bit 24) */ -#define SCU_CLK_MLINKCLKCR_WDTSEL_Msk \ - (0x3000000UL) /*!< SCU_CLK MLINKCLKCR: WDTSEL (Bitfield-Mask: 0x03) */ - -/* ------------------------------- SCU_CLK_SLEEPCR ------------------------------ */ -#define SCU_CLK_SLEEPCR_SYSSEL_Pos \ - (0UL) /*!< SCU_CLK SLEEPCR: SYSSEL (Bit 0) */ -#define SCU_CLK_SLEEPCR_SYSSEL_Msk \ - (0x1UL) /*!< SCU_CLK SLEEPCR: SYSSEL (Bitfield-Mask: 0x01) */ -#define SCU_CLK_SLEEPCR_USBCR_Pos \ - (16UL) /*!< SCU_CLK SLEEPCR: USBCR (Bit 16) */ -#define SCU_CLK_SLEEPCR_USBCR_Msk \ - (0x10000UL) /*!< SCU_CLK SLEEPCR: USBCR (Bitfield-Mask: 0x01) */ -#define SCU_CLK_SLEEPCR_ETH0CR_Pos \ - (18UL) /*!< SCU_CLK SLEEPCR: ETH0CR (Bit 18) */ -#define SCU_CLK_SLEEPCR_ETH0CR_Msk \ - (0x40000UL) /*!< SCU_CLK SLEEPCR: ETH0CR (Bitfield-Mask: 0x01) */ -#define SCU_CLK_SLEEPCR_CCUCR_Pos \ - (20UL) /*!< SCU_CLK SLEEPCR: CCUCR (Bit 20) */ -#define SCU_CLK_SLEEPCR_CCUCR_Msk \ - (0x100000UL) /*!< SCU_CLK SLEEPCR: CCUCR (Bitfield-Mask: 0x01) */ -#define SCU_CLK_SLEEPCR_WDTCR_Pos \ - (21UL) /*!< SCU_CLK SLEEPCR: WDTCR (Bit 21) */ -#define SCU_CLK_SLEEPCR_WDTCR_Msk \ - (0x200000UL) /*!< SCU_CLK SLEEPCR: WDTCR (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_CLK_DSLEEPCR ------------------------------ */ -#define SCU_CLK_DSLEEPCR_SYSSEL_Pos \ - (0UL) /*!< SCU_CLK DSLEEPCR: SYSSEL (Bit 0) */ -#define SCU_CLK_DSLEEPCR_SYSSEL_Msk \ - (0x1UL) /*!< SCU_CLK DSLEEPCR: SYSSEL (Bitfield-Mask: 0x01) */ -#define SCU_CLK_DSLEEPCR_FPDN_Pos \ - (11UL) /*!< SCU_CLK DSLEEPCR: FPDN (Bit 11) */ -#define SCU_CLK_DSLEEPCR_FPDN_Msk \ - (0x800UL) /*!< SCU_CLK DSLEEPCR: FPDN (Bitfield-Mask: 0x01) */ -#define SCU_CLK_DSLEEPCR_PLLPDN_Pos \ - (12UL) /*!< SCU_CLK DSLEEPCR: PLLPDN (Bit 12) */ -#define SCU_CLK_DSLEEPCR_PLLPDN_Msk \ - (0x1000UL) /*!< SCU_CLK DSLEEPCR: PLLPDN (Bitfield-Mask: 0x01) */ -#define SCU_CLK_DSLEEPCR_VCOPDN_Pos \ - (13UL) /*!< SCU_CLK DSLEEPCR: VCOPDN (Bit 13) */ -#define SCU_CLK_DSLEEPCR_VCOPDN_Msk \ - (0x2000UL) /*!< SCU_CLK DSLEEPCR: VCOPDN (Bitfield-Mask: 0x01) */ -#define SCU_CLK_DSLEEPCR_USBCR_Pos \ - (16UL) /*!< SCU_CLK DSLEEPCR: USBCR (Bit 16) */ -#define SCU_CLK_DSLEEPCR_USBCR_Msk \ - (0x10000UL) /*!< SCU_CLK DSLEEPCR: USBCR (Bitfield-Mask: 0x01) */ -#define SCU_CLK_DSLEEPCR_ETH0CR_Pos \ - (18UL) /*!< SCU_CLK DSLEEPCR: ETH0CR (Bit 18) */ -#define SCU_CLK_DSLEEPCR_ETH0CR_Msk \ - (0x40000UL) /*!< SCU_CLK DSLEEPCR: ETH0CR (Bitfield-Mask: 0x01) */ -#define SCU_CLK_DSLEEPCR_CCUCR_Pos \ - (20UL) /*!< SCU_CLK DSLEEPCR: CCUCR (Bit 20) */ -#define SCU_CLK_DSLEEPCR_CCUCR_Msk \ - (0x100000UL) /*!< SCU_CLK DSLEEPCR: CCUCR (Bitfield-Mask: 0x01) */ -#define SCU_CLK_DSLEEPCR_WDTCR_Pos \ - (21UL) /*!< SCU_CLK DSLEEPCR: WDTCR (Bit 21) */ -#define SCU_CLK_DSLEEPCR_WDTCR_Msk \ - (0x200000UL) /*!< SCU_CLK DSLEEPCR: WDTCR (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_CLK_CGATSTAT0 ----------------------------- */ -#define SCU_CLK_CGATSTAT0_VADC_Pos \ - (0UL) /*!< SCU_CLK CGATSTAT0: VADC (Bit 0) */ -#define SCU_CLK_CGATSTAT0_VADC_Msk \ - (0x1UL) /*!< SCU_CLK CGATSTAT0: VADC (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSTAT0_DSD_Pos \ - (1UL) /*!< SCU_CLK CGATSTAT0: DSD (Bit 1) */ -#define SCU_CLK_CGATSTAT0_DSD_Msk \ - (0x2UL) /*!< SCU_CLK CGATSTAT0: DSD (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSTAT0_CCU40_Pos \ - (2UL) /*!< SCU_CLK CGATSTAT0: CCU40 (Bit 2) */ -#define SCU_CLK_CGATSTAT0_CCU40_Msk \ - (0x4UL) /*!< SCU_CLK CGATSTAT0: CCU40 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSTAT0_CCU41_Pos \ - (3UL) /*!< SCU_CLK CGATSTAT0: CCU41 (Bit 3) */ -#define SCU_CLK_CGATSTAT0_CCU41_Msk \ - (0x8UL) /*!< SCU_CLK CGATSTAT0: CCU41 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSTAT0_CCU42_Pos \ - (4UL) /*!< SCU_CLK CGATSTAT0: CCU42 (Bit 4) */ -#define SCU_CLK_CGATSTAT0_CCU42_Msk \ - (0x10UL) /*!< SCU_CLK CGATSTAT0: CCU42 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSTAT0_CCU80_Pos \ - (7UL) /*!< SCU_CLK CGATSTAT0: CCU80 (Bit 7) */ -#define SCU_CLK_CGATSTAT0_CCU80_Msk \ - (0x80UL) /*!< SCU_CLK CGATSTAT0: CCU80 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSTAT0_CCU81_Pos \ - (8UL) /*!< SCU_CLK CGATSTAT0: CCU81 (Bit 8) */ -#define SCU_CLK_CGATSTAT0_CCU81_Msk \ - (0x100UL) /*!< SCU_CLK CGATSTAT0: CCU81 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSTAT0_POSIF0_Pos \ - (9UL) /*!< SCU_CLK CGATSTAT0: POSIF0 (Bit 9) */ -#define SCU_CLK_CGATSTAT0_POSIF0_Msk \ - (0x200UL) /*!< SCU_CLK CGATSTAT0: POSIF0 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSTAT0_POSIF1_Pos \ - (10UL) /*!< SCU_CLK CGATSTAT0: POSIF1 (Bit 10) */ -#define SCU_CLK_CGATSTAT0_POSIF1_Msk \ - (0x400UL) /*!< SCU_CLK CGATSTAT0: POSIF1 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSTAT0_USIC0_Pos \ - (11UL) /*!< SCU_CLK CGATSTAT0: USIC0 (Bit 11) */ -#define SCU_CLK_CGATSTAT0_USIC0_Msk \ - (0x800UL) /*!< SCU_CLK CGATSTAT0: USIC0 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSTAT0_ERU1_Pos \ - (16UL) /*!< SCU_CLK CGATSTAT0: ERU1 (Bit 16) */ -#define SCU_CLK_CGATSTAT0_ERU1_Msk \ - (0x10000UL) /*!< SCU_CLK CGATSTAT0: ERU1 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSTAT0_HRPWM0_Pos \ - (23UL) /*!< SCU_CLK CGATSTAT0: HRPWM0 (Bit 23) */ -#define SCU_CLK_CGATSTAT0_HRPWM0_Msk \ - (0x800000UL) /*!< SCU_CLK CGATSTAT0: HRPWM0 (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_CLK_CGATSET0 ------------------------------ */ -#define SCU_CLK_CGATSET0_VADC_Pos \ - (0UL) /*!< SCU_CLK CGATSET0: VADC (Bit 0) */ -#define SCU_CLK_CGATSET0_VADC_Msk \ - (0x1UL) /*!< SCU_CLK CGATSET0: VADC (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSET0_DSD_Pos \ - (1UL) /*!< SCU_CLK CGATSET0: DSD (Bit 1) */ -#define SCU_CLK_CGATSET0_DSD_Msk \ - (0x2UL) /*!< SCU_CLK CGATSET0: DSD (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSET0_CCU40_Pos \ - (2UL) /*!< SCU_CLK CGATSET0: CCU40 (Bit 2) */ -#define SCU_CLK_CGATSET0_CCU40_Msk \ - (0x4UL) /*!< SCU_CLK CGATSET0: CCU40 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSET0_CCU41_Pos \ - (3UL) /*!< SCU_CLK CGATSET0: CCU41 (Bit 3) */ -#define SCU_CLK_CGATSET0_CCU41_Msk \ - (0x8UL) /*!< SCU_CLK CGATSET0: CCU41 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSET0_CCU42_Pos \ - (4UL) /*!< SCU_CLK CGATSET0: CCU42 (Bit 4) */ -#define SCU_CLK_CGATSET0_CCU42_Msk \ - (0x10UL) /*!< SCU_CLK CGATSET0: CCU42 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSET0_CCU80_Pos \ - (7UL) /*!< SCU_CLK CGATSET0: CCU80 (Bit 7) */ -#define SCU_CLK_CGATSET0_CCU80_Msk \ - (0x80UL) /*!< SCU_CLK CGATSET0: CCU80 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSET0_CCU81_Pos \ - (8UL) /*!< SCU_CLK CGATSET0: CCU81 (Bit 8) */ -#define SCU_CLK_CGATSET0_CCU81_Msk \ - (0x100UL) /*!< SCU_CLK CGATSET0: CCU81 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSET0_POSIF0_Pos \ - (9UL) /*!< SCU_CLK CGATSET0: POSIF0 (Bit 9) */ -#define SCU_CLK_CGATSET0_POSIF0_Msk \ - (0x200UL) /*!< SCU_CLK CGATSET0: POSIF0 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSET0_POSIF1_Pos \ - (10UL) /*!< SCU_CLK CGATSET0: POSIF1 (Bit 10) */ -#define SCU_CLK_CGATSET0_POSIF1_Msk \ - (0x400UL) /*!< SCU_CLK CGATSET0: POSIF1 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSET0_USIC0_Pos \ - (11UL) /*!< SCU_CLK CGATSET0: USIC0 (Bit 11) */ -#define SCU_CLK_CGATSET0_USIC0_Msk \ - (0x800UL) /*!< SCU_CLK CGATSET0: USIC0 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSET0_ERU1_Pos \ - (16UL) /*!< SCU_CLK CGATSET0: ERU1 (Bit 16) */ -#define SCU_CLK_CGATSET0_ERU1_Msk \ - (0x10000UL) /*!< SCU_CLK CGATSET0: ERU1 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSET0_HRPWM0_Pos \ - (23UL) /*!< SCU_CLK CGATSET0: HRPWM0 (Bit 23) */ -#define SCU_CLK_CGATSET0_HRPWM0_Msk \ - (0x800000UL) /*!< SCU_CLK CGATSET0: HRPWM0 (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_CLK_CGATCLR0 ------------------------------ */ -#define SCU_CLK_CGATCLR0_VADC_Pos \ - (0UL) /*!< SCU_CLK CGATCLR0: VADC (Bit 0) */ -#define SCU_CLK_CGATCLR0_VADC_Msk \ - (0x1UL) /*!< SCU_CLK CGATCLR0: VADC (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATCLR0_DSD_Pos \ - (1UL) /*!< SCU_CLK CGATCLR0: DSD (Bit 1) */ -#define SCU_CLK_CGATCLR0_DSD_Msk \ - (0x2UL) /*!< SCU_CLK CGATCLR0: DSD (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATCLR0_CCU40_Pos \ - (2UL) /*!< SCU_CLK CGATCLR0: CCU40 (Bit 2) */ -#define SCU_CLK_CGATCLR0_CCU40_Msk \ - (0x4UL) /*!< SCU_CLK CGATCLR0: CCU40 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATCLR0_CCU41_Pos \ - (3UL) /*!< SCU_CLK CGATCLR0: CCU41 (Bit 3) */ -#define SCU_CLK_CGATCLR0_CCU41_Msk \ - (0x8UL) /*!< SCU_CLK CGATCLR0: CCU41 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATCLR0_CCU42_Pos \ - (4UL) /*!< SCU_CLK CGATCLR0: CCU42 (Bit 4) */ -#define SCU_CLK_CGATCLR0_CCU42_Msk \ - (0x10UL) /*!< SCU_CLK CGATCLR0: CCU42 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATCLR0_CCU80_Pos \ - (7UL) /*!< SCU_CLK CGATCLR0: CCU80 (Bit 7) */ -#define SCU_CLK_CGATCLR0_CCU80_Msk \ - (0x80UL) /*!< SCU_CLK CGATCLR0: CCU80 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATCLR0_CCU81_Pos \ - (8UL) /*!< SCU_CLK CGATCLR0: CCU81 (Bit 8) */ -#define SCU_CLK_CGATCLR0_CCU81_Msk \ - (0x100UL) /*!< SCU_CLK CGATCLR0: CCU81 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATCLR0_POSIF0_Pos \ - (9UL) /*!< SCU_CLK CGATCLR0: POSIF0 (Bit 9) */ -#define SCU_CLK_CGATCLR0_POSIF0_Msk \ - (0x200UL) /*!< SCU_CLK CGATCLR0: POSIF0 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATCLR0_POSIF1_Pos \ - (10UL) /*!< SCU_CLK CGATCLR0: POSIF1 (Bit 10) */ -#define SCU_CLK_CGATCLR0_POSIF1_Msk \ - (0x400UL) /*!< SCU_CLK CGATCLR0: POSIF1 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATCLR0_USIC0_Pos \ - (11UL) /*!< SCU_CLK CGATCLR0: USIC0 (Bit 11) */ -#define SCU_CLK_CGATCLR0_USIC0_Msk \ - (0x800UL) /*!< SCU_CLK CGATCLR0: USIC0 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATCLR0_ERU1_Pos \ - (16UL) /*!< SCU_CLK CGATCLR0: ERU1 (Bit 16) */ -#define SCU_CLK_CGATCLR0_ERU1_Msk \ - (0x10000UL) /*!< SCU_CLK CGATCLR0: ERU1 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATCLR0_HRPWM0_Pos \ - (23UL) /*!< SCU_CLK CGATCLR0: HRPWM0 (Bit 23) */ -#define SCU_CLK_CGATCLR0_HRPWM0_Msk \ - (0x800000UL) /*!< SCU_CLK CGATCLR0: HRPWM0 (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_CLK_CGATSTAT1 ----------------------------- */ -#define SCU_CLK_CGATSTAT1_CCU43_Pos \ - (0UL) /*!< SCU_CLK CGATSTAT1: CCU43 (Bit 0) */ -#define SCU_CLK_CGATSTAT1_CCU43_Msk \ - (0x1UL) /*!< SCU_CLK CGATSTAT1: CCU43 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSTAT1_LEDTSCU0_Pos \ - (3UL) /*!< SCU_CLK CGATSTAT1: LEDTSCU0 (Bit 3) */ -#define SCU_CLK_CGATSTAT1_LEDTSCU0_Msk \ - (0x8UL) /*!< SCU_CLK CGATSTAT1: LEDTSCU0 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSTAT1_MCAN0_Pos \ - (4UL) /*!< SCU_CLK CGATSTAT1: MCAN0 (Bit 4) */ -#define SCU_CLK_CGATSTAT1_MCAN0_Msk \ - (0x10UL) /*!< SCU_CLK CGATSTAT1: MCAN0 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSTAT1_DAC_Pos \ - (5UL) /*!< SCU_CLK CGATSTAT1: DAC (Bit 5) */ -#define SCU_CLK_CGATSTAT1_DAC_Msk \ - (0x20UL) /*!< SCU_CLK CGATSTAT1: DAC (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSTAT1_USIC1_Pos \ - (7UL) /*!< SCU_CLK CGATSTAT1: USIC1 (Bit 7) */ -#define SCU_CLK_CGATSTAT1_USIC1_Msk \ - (0x80UL) /*!< SCU_CLK CGATSTAT1: USIC1 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSTAT1_PPORTS_Pos \ - (9UL) /*!< SCU_CLK CGATSTAT1: PPORTS (Bit 9) */ -#define SCU_CLK_CGATSTAT1_PPORTS_Msk \ - (0x200UL) /*!< SCU_CLK CGATSTAT1: PPORTS (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_CLK_CGATSET1 ------------------------------ */ -#define SCU_CLK_CGATSET1_CCU43_Pos \ - (0UL) /*!< SCU_CLK CGATSET1: CCU43 (Bit 0) */ -#define SCU_CLK_CGATSET1_CCU43_Msk \ - (0x1UL) /*!< SCU_CLK CGATSET1: CCU43 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSET1_LEDTSCU0_Pos \ - (3UL) /*!< SCU_CLK CGATSET1: LEDTSCU0 (Bit 3) */ -#define SCU_CLK_CGATSET1_LEDTSCU0_Msk \ - (0x8UL) /*!< SCU_CLK CGATSET1: LEDTSCU0 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSET1_MCAN0_Pos \ - (4UL) /*!< SCU_CLK CGATSET1: MCAN0 (Bit 4) */ -#define SCU_CLK_CGATSET1_MCAN0_Msk \ - (0x10UL) /*!< SCU_CLK CGATSET1: MCAN0 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSET1_DAC_Pos \ - (5UL) /*!< SCU_CLK CGATSET1: DAC (Bit 5) */ -#define SCU_CLK_CGATSET1_DAC_Msk \ - (0x20UL) /*!< SCU_CLK CGATSET1: DAC (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSET1_USIC1_Pos \ - (7UL) /*!< SCU_CLK CGATSET1: USIC1 (Bit 7) */ -#define SCU_CLK_CGATSET1_USIC1_Msk \ - (0x80UL) /*!< SCU_CLK CGATSET1: USIC1 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSET1_PPORTS_Pos \ - (9UL) /*!< SCU_CLK CGATSET1: PPORTS (Bit 9) */ -#define SCU_CLK_CGATSET1_PPORTS_Msk \ - (0x200UL) /*!< SCU_CLK CGATSET1: PPORTS (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_CLK_CGATCLR1 ------------------------------ */ -#define SCU_CLK_CGATCLR1_CCU43_Pos \ - (0UL) /*!< SCU_CLK CGATCLR1: CCU43 (Bit 0) */ -#define SCU_CLK_CGATCLR1_CCU43_Msk \ - (0x1UL) /*!< SCU_CLK CGATCLR1: CCU43 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATCLR1_LEDTSCU0_Pos \ - (3UL) /*!< SCU_CLK CGATCLR1: LEDTSCU0 (Bit 3) */ -#define SCU_CLK_CGATCLR1_LEDTSCU0_Msk \ - (0x8UL) /*!< SCU_CLK CGATCLR1: LEDTSCU0 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATCLR1_MCAN0_Pos \ - (4UL) /*!< SCU_CLK CGATCLR1: MCAN0 (Bit 4) */ -#define SCU_CLK_CGATCLR1_MCAN0_Msk \ - (0x10UL) /*!< SCU_CLK CGATCLR1: MCAN0 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATCLR1_DAC_Pos \ - (5UL) /*!< SCU_CLK CGATCLR1: DAC (Bit 5) */ -#define SCU_CLK_CGATCLR1_DAC_Msk \ - (0x20UL) /*!< SCU_CLK CGATCLR1: DAC (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATCLR1_USIC1_Pos \ - (7UL) /*!< SCU_CLK CGATCLR1: USIC1 (Bit 7) */ -#define SCU_CLK_CGATCLR1_USIC1_Msk \ - (0x80UL) /*!< SCU_CLK CGATCLR1: USIC1 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATCLR1_PPORTS_Pos \ - (9UL) /*!< SCU_CLK CGATCLR1: PPORTS (Bit 9) */ -#define SCU_CLK_CGATCLR1_PPORTS_Msk \ - (0x200UL) /*!< SCU_CLK CGATCLR1: PPORTS (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_CLK_CGATSTAT2 ----------------------------- */ -#define SCU_CLK_CGATSTAT2_WDT_Pos \ - (1UL) /*!< SCU_CLK CGATSTAT2: WDT (Bit 1) */ -#define SCU_CLK_CGATSTAT2_WDT_Msk \ - (0x2UL) /*!< SCU_CLK CGATSTAT2: WDT (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSTAT2_ETH0_Pos \ - (2UL) /*!< SCU_CLK CGATSTAT2: ETH0 (Bit 2) */ -#define SCU_CLK_CGATSTAT2_ETH0_Msk \ - (0x4UL) /*!< SCU_CLK CGATSTAT2: ETH0 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSTAT2_DMA0_Pos \ - (4UL) /*!< SCU_CLK CGATSTAT2: DMA0 (Bit 4) */ -#define SCU_CLK_CGATSTAT2_DMA0_Msk \ - (0x10UL) /*!< SCU_CLK CGATSTAT2: DMA0 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSTAT2_FCE_Pos \ - (6UL) /*!< SCU_CLK CGATSTAT2: FCE (Bit 6) */ -#define SCU_CLK_CGATSTAT2_FCE_Msk \ - (0x40UL) /*!< SCU_CLK CGATSTAT2: FCE (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSTAT2_USB_Pos \ - (7UL) /*!< SCU_CLK CGATSTAT2: USB (Bit 7) */ -#define SCU_CLK_CGATSTAT2_USB_Msk \ - (0x80UL) /*!< SCU_CLK CGATSTAT2: USB (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_CLK_CGATSET2 ------------------------------ */ -#define SCU_CLK_CGATSET2_WDT_Pos \ - (1UL) /*!< SCU_CLK CGATSET2: WDT (Bit 1) */ -#define SCU_CLK_CGATSET2_WDT_Msk \ - (0x2UL) /*!< SCU_CLK CGATSET2: WDT (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSET2_ETH0_Pos \ - (2UL) /*!< SCU_CLK CGATSET2: ETH0 (Bit 2) */ -#define SCU_CLK_CGATSET2_ETH0_Msk \ - (0x4UL) /*!< SCU_CLK CGATSET2: ETH0 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSET2_DMA0_Pos \ - (4UL) /*!< SCU_CLK CGATSET2: DMA0 (Bit 4) */ -#define SCU_CLK_CGATSET2_DMA0_Msk \ - (0x10UL) /*!< SCU_CLK CGATSET2: DMA0 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSET2_FCE_Pos \ - (6UL) /*!< SCU_CLK CGATSET2: FCE (Bit 6) */ -#define SCU_CLK_CGATSET2_FCE_Msk \ - (0x40UL) /*!< SCU_CLK CGATSET2: FCE (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATSET2_USB_Pos \ - (7UL) /*!< SCU_CLK CGATSET2: USB (Bit 7) */ -#define SCU_CLK_CGATSET2_USB_Msk \ - (0x80UL) /*!< SCU_CLK CGATSET2: USB (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_CLK_CGATCLR2 ------------------------------ */ -#define SCU_CLK_CGATCLR2_WDT_Pos \ - (1UL) /*!< SCU_CLK CGATCLR2: WDT (Bit 1) */ -#define SCU_CLK_CGATCLR2_WDT_Msk \ - (0x2UL) /*!< SCU_CLK CGATCLR2: WDT (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATCLR2_ETH0_Pos \ - (2UL) /*!< SCU_CLK CGATCLR2: ETH0 (Bit 2) */ -#define SCU_CLK_CGATCLR2_ETH0_Msk \ - (0x4UL) /*!< SCU_CLK CGATCLR2: ETH0 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATCLR2_DMA0_Pos \ - (4UL) /*!< SCU_CLK CGATCLR2: DMA0 (Bit 4) */ -#define SCU_CLK_CGATCLR2_DMA0_Msk \ - (0x10UL) /*!< SCU_CLK CGATCLR2: DMA0 (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATCLR2_FCE_Pos \ - (6UL) /*!< SCU_CLK CGATCLR2: FCE (Bit 6) */ -#define SCU_CLK_CGATCLR2_FCE_Msk \ - (0x40UL) /*!< SCU_CLK CGATCLR2: FCE (Bitfield-Mask: 0x01) */ -#define SCU_CLK_CGATCLR2_USB_Pos \ - (7UL) /*!< SCU_CLK CGATCLR2: USB (Bit 7) */ -#define SCU_CLK_CGATCLR2_USB_Msk \ - (0x80UL) /*!< SCU_CLK CGATCLR2: USB (Bitfield-Mask: 0x01) */ - -/* ================================================================================ */ -/* ================ struct 'SCU_OSC' Position & Mask ================ */ -/* ================================================================================ */ - -/* ------------------------------ SCU_OSC_OSCHPSTAT ----------------------------- */ -#define SCU_OSC_OSCHPSTAT_X1D_Pos \ - (0UL) /*!< SCU_OSC OSCHPSTAT: X1D (Bit 0) */ -#define SCU_OSC_OSCHPSTAT_X1D_Msk \ - (0x1UL) /*!< SCU_OSC OSCHPSTAT: X1D (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_OSC_OSCHPCTRL ----------------------------- */ -#define SCU_OSC_OSCHPCTRL_X1DEN_Pos \ - (0UL) /*!< SCU_OSC OSCHPCTRL: X1DEN (Bit 0) */ -#define SCU_OSC_OSCHPCTRL_X1DEN_Msk \ - (0x1UL) /*!< SCU_OSC OSCHPCTRL: X1DEN (Bitfield-Mask: 0x01) */ -#define SCU_OSC_OSCHPCTRL_SHBY_Pos \ - (1UL) /*!< SCU_OSC OSCHPCTRL: SHBY (Bit 1) */ -#define SCU_OSC_OSCHPCTRL_SHBY_Msk \ - (0x2UL) /*!< SCU_OSC OSCHPCTRL: SHBY (Bitfield-Mask: 0x01) */ -#define SCU_OSC_OSCHPCTRL_MODE_Pos \ - (4UL) /*!< SCU_OSC OSCHPCTRL: MODE (Bit 4) */ -#define SCU_OSC_OSCHPCTRL_MODE_Msk \ - (0x30UL) /*!< SCU_OSC OSCHPCTRL: MODE (Bitfield-Mask: 0x03) */ -#define SCU_OSC_OSCHPCTRL_OSCVAL_Pos \ - (16UL) /*!< SCU_OSC OSCHPCTRL: OSCVAL (Bit 16) */ -#define SCU_OSC_OSCHPCTRL_OSCVAL_Msk \ - (0xf0000UL) /*!< SCU_OSC OSCHPCTRL: OSCVAL (Bitfield-Mask: 0x0f) */ - -/* ----------------------------- SCU_OSC_CLKCALCONST ---------------------------- */ -#define SCU_OSC_CLKCALCONST_CALIBCONST_Pos \ - (0UL) /*!< SCU_OSC CLKCALCONST: CALIBCONST (Bit 0) */ -#define SCU_OSC_CLKCALCONST_CALIBCONST_Msk \ - (0xfUL) /*!< SCU_OSC CLKCALCONST: CALIBCONST (Bitfield-Mask: 0x0f) */ - -/* ================================================================================ */ -/* ================ struct 'SCU_PLL' Position & Mask ================ */ -/* ================================================================================ */ - -/* ------------------------------- SCU_PLL_PLLSTAT ------------------------------ */ -#define SCU_PLL_PLLSTAT_VCOBYST_Pos \ - (0UL) /*!< SCU_PLL PLLSTAT: VCOBYST (Bit 0) */ -#define SCU_PLL_PLLSTAT_VCOBYST_Msk \ - (0x1UL) /*!< SCU_PLL PLLSTAT: VCOBYST (Bitfield-Mask: 0x01) */ -#define SCU_PLL_PLLSTAT_PWDSTAT_Pos \ - (1UL) /*!< SCU_PLL PLLSTAT: PWDSTAT (Bit 1) */ -#define SCU_PLL_PLLSTAT_PWDSTAT_Msk \ - (0x2UL) /*!< SCU_PLL PLLSTAT: PWDSTAT (Bitfield-Mask: 0x01) */ -#define SCU_PLL_PLLSTAT_VCOLOCK_Pos \ - (2UL) /*!< SCU_PLL PLLSTAT: VCOLOCK (Bit 2) */ -#define SCU_PLL_PLLSTAT_VCOLOCK_Msk \ - (0x4UL) /*!< SCU_PLL PLLSTAT: VCOLOCK (Bitfield-Mask: 0x01) */ -#define SCU_PLL_PLLSTAT_K1RDY_Pos \ - (4UL) /*!< SCU_PLL PLLSTAT: K1RDY (Bit 4) */ -#define SCU_PLL_PLLSTAT_K1RDY_Msk \ - (0x10UL) /*!< SCU_PLL PLLSTAT: K1RDY (Bitfield-Mask: 0x01) */ -#define SCU_PLL_PLLSTAT_K2RDY_Pos \ - (5UL) /*!< SCU_PLL PLLSTAT: K2RDY (Bit 5) */ -#define SCU_PLL_PLLSTAT_K2RDY_Msk \ - (0x20UL) /*!< SCU_PLL PLLSTAT: K2RDY (Bitfield-Mask: 0x01) */ -#define SCU_PLL_PLLSTAT_BY_Pos \ - (6UL) /*!< SCU_PLL PLLSTAT: BY (Bit 6) */ -#define SCU_PLL_PLLSTAT_BY_Msk \ - (0x40UL) /*!< SCU_PLL PLLSTAT: BY (Bitfield-Mask: 0x01) */ -#define SCU_PLL_PLLSTAT_PLLLV_Pos \ - (7UL) /*!< SCU_PLL PLLSTAT: PLLLV (Bit 7) */ -#define SCU_PLL_PLLSTAT_PLLLV_Msk \ - (0x80UL) /*!< SCU_PLL PLLSTAT: PLLLV (Bitfield-Mask: 0x01) */ -#define SCU_PLL_PLLSTAT_PLLHV_Pos \ - (8UL) /*!< SCU_PLL PLLSTAT: PLLHV (Bit 8) */ -#define SCU_PLL_PLLSTAT_PLLHV_Msk \ - (0x100UL) /*!< SCU_PLL PLLSTAT: PLLHV (Bitfield-Mask: 0x01) */ -#define SCU_PLL_PLLSTAT_PLLSP_Pos \ - (9UL) /*!< SCU_PLL PLLSTAT: PLLSP (Bit 9) */ -#define SCU_PLL_PLLSTAT_PLLSP_Msk \ - (0x200UL) /*!< SCU_PLL PLLSTAT: PLLSP (Bitfield-Mask: 0x01) */ - -/* ------------------------------- SCU_PLL_PLLCON0 ------------------------------ */ -#define SCU_PLL_PLLCON0_VCOBYP_Pos \ - (0UL) /*!< SCU_PLL PLLCON0: VCOBYP (Bit 0) */ -#define SCU_PLL_PLLCON0_VCOBYP_Msk \ - (0x1UL) /*!< SCU_PLL PLLCON0: VCOBYP (Bitfield-Mask: 0x01) */ -#define SCU_PLL_PLLCON0_VCOPWD_Pos \ - (1UL) /*!< SCU_PLL PLLCON0: VCOPWD (Bit 1) */ -#define SCU_PLL_PLLCON0_VCOPWD_Msk \ - (0x2UL) /*!< SCU_PLL PLLCON0: VCOPWD (Bitfield-Mask: 0x01) */ -#define SCU_PLL_PLLCON0_VCOTR_Pos \ - (2UL) /*!< SCU_PLL PLLCON0: VCOTR (Bit 2) */ -#define SCU_PLL_PLLCON0_VCOTR_Msk \ - (0x4UL) /*!< SCU_PLL PLLCON0: VCOTR (Bitfield-Mask: 0x01) */ -#define SCU_PLL_PLLCON0_FINDIS_Pos \ - (4UL) /*!< SCU_PLL PLLCON0: FINDIS (Bit 4) */ -#define SCU_PLL_PLLCON0_FINDIS_Msk \ - (0x10UL) /*!< SCU_PLL PLLCON0: FINDIS (Bitfield-Mask: 0x01) */ -#define SCU_PLL_PLLCON0_OSCDISCDIS_Pos \ - (6UL) /*!< SCU_PLL PLLCON0: OSCDISCDIS (Bit 6) */ -#define SCU_PLL_PLLCON0_OSCDISCDIS_Msk \ - (0x40UL) /*!< SCU_PLL PLLCON0: OSCDISCDIS (Bitfield-Mask: 0x01) */ -#define SCU_PLL_PLLCON0_PLLPWD_Pos \ - (16UL) /*!< SCU_PLL PLLCON0: PLLPWD (Bit 16) */ -#define SCU_PLL_PLLCON0_PLLPWD_Msk \ - (0x10000UL) /*!< SCU_PLL PLLCON0: PLLPWD (Bitfield-Mask: 0x01) */ -#define SCU_PLL_PLLCON0_OSCRES_Pos \ - (17UL) /*!< SCU_PLL PLLCON0: OSCRES (Bit 17) */ -#define SCU_PLL_PLLCON0_OSCRES_Msk \ - (0x20000UL) /*!< SCU_PLL PLLCON0: OSCRES (Bitfield-Mask: 0x01) */ -#define SCU_PLL_PLLCON0_RESLD_Pos \ - (18UL) /*!< SCU_PLL PLLCON0: RESLD (Bit 18) */ -#define SCU_PLL_PLLCON0_RESLD_Msk \ - (0x40000UL) /*!< SCU_PLL PLLCON0: RESLD (Bitfield-Mask: 0x01) */ -#define SCU_PLL_PLLCON0_AOTREN_Pos \ - (19UL) /*!< SCU_PLL PLLCON0: AOTREN (Bit 19) */ -#define SCU_PLL_PLLCON0_AOTREN_Msk \ - (0x80000UL) /*!< SCU_PLL PLLCON0: AOTREN (Bitfield-Mask: 0x01) */ -#define SCU_PLL_PLLCON0_FOTR_Pos \ - (20UL) /*!< SCU_PLL PLLCON0: FOTR (Bit 20) */ -#define SCU_PLL_PLLCON0_FOTR_Msk \ - (0x100000UL) /*!< SCU_PLL PLLCON0: FOTR (Bitfield-Mask: 0x01) */ - -/* ------------------------------- SCU_PLL_PLLCON1 ------------------------------ */ -#define SCU_PLL_PLLCON1_K1DIV_Pos \ - (0UL) /*!< SCU_PLL PLLCON1: K1DIV (Bit 0) */ -#define SCU_PLL_PLLCON1_K1DIV_Msk \ - (0x7fUL) /*!< SCU_PLL PLLCON1: K1DIV (Bitfield-Mask: 0x7f) */ -#define SCU_PLL_PLLCON1_NDIV_Pos \ - (8UL) /*!< SCU_PLL PLLCON1: NDIV (Bit 8) */ -#define SCU_PLL_PLLCON1_NDIV_Msk \ - (0x7f00UL) /*!< SCU_PLL PLLCON1: NDIV (Bitfield-Mask: 0x7f) */ -#define SCU_PLL_PLLCON1_K2DIV_Pos \ - (16UL) /*!< SCU_PLL PLLCON1: K2DIV (Bit 16) */ -#define SCU_PLL_PLLCON1_K2DIV_Msk \ - (0x7f0000UL) /*!< SCU_PLL PLLCON1: K2DIV (Bitfield-Mask: 0x7f) */ -#define SCU_PLL_PLLCON1_PDIV_Pos \ - (24UL) /*!< SCU_PLL PLLCON1: PDIV (Bit 24) */ -#define SCU_PLL_PLLCON1_PDIV_Msk \ - (0xf000000UL) /*!< SCU_PLL PLLCON1: PDIV (Bitfield-Mask: 0x0f) */ - -/* ------------------------------- SCU_PLL_PLLCON2 ------------------------------ */ -#define SCU_PLL_PLLCON2_PINSEL_Pos \ - (0UL) /*!< SCU_PLL PLLCON2: PINSEL (Bit 0) */ -#define SCU_PLL_PLLCON2_PINSEL_Msk \ - (0x1UL) /*!< SCU_PLL PLLCON2: PINSEL (Bitfield-Mask: 0x01) */ -#define SCU_PLL_PLLCON2_K1INSEL_Pos \ - (8UL) /*!< SCU_PLL PLLCON2: K1INSEL (Bit 8) */ -#define SCU_PLL_PLLCON2_K1INSEL_Msk \ - (0x100UL) /*!< SCU_PLL PLLCON2: K1INSEL (Bitfield-Mask: 0x01) */ - -/* ----------------------------- SCU_PLL_USBPLLSTAT ----------------------------- */ -#define SCU_PLL_USBPLLSTAT_VCOBYST_Pos \ - (0UL) /*!< SCU_PLL USBPLLSTAT: VCOBYST (Bit 0) */ -#define SCU_PLL_USBPLLSTAT_VCOBYST_Msk \ - (0x1UL) /*!< SCU_PLL USBPLLSTAT: VCOBYST (Bitfield-Mask: 0x01) */ -#define SCU_PLL_USBPLLSTAT_PWDSTAT_Pos \ - (1UL) /*!< SCU_PLL USBPLLSTAT: PWDSTAT (Bit 1) */ -#define SCU_PLL_USBPLLSTAT_PWDSTAT_Msk \ - (0x2UL) /*!< SCU_PLL USBPLLSTAT: PWDSTAT (Bitfield-Mask: 0x01) */ -#define SCU_PLL_USBPLLSTAT_VCOLOCK_Pos \ - (2UL) /*!< SCU_PLL USBPLLSTAT: VCOLOCK (Bit 2) */ -#define SCU_PLL_USBPLLSTAT_VCOLOCK_Msk \ - (0x4UL) /*!< SCU_PLL USBPLLSTAT: VCOLOCK (Bitfield-Mask: 0x01) */ -#define SCU_PLL_USBPLLSTAT_BY_Pos \ - (6UL) /*!< SCU_PLL USBPLLSTAT: BY (Bit 6) */ -#define SCU_PLL_USBPLLSTAT_BY_Msk \ - (0x40UL) /*!< SCU_PLL USBPLLSTAT: BY (Bitfield-Mask: 0x01) */ -#define SCU_PLL_USBPLLSTAT_VCOLOCKED_Pos \ - (7UL) /*!< SCU_PLL USBPLLSTAT: VCOLOCKED (Bit 7) */ -#define SCU_PLL_USBPLLSTAT_VCOLOCKED_Msk \ - (0x80UL) /*!< SCU_PLL USBPLLSTAT: VCOLOCKED (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_PLL_USBPLLCON ----------------------------- */ -#define SCU_PLL_USBPLLCON_VCOBYP_Pos \ - (0UL) /*!< SCU_PLL USBPLLCON: VCOBYP (Bit 0) */ -#define SCU_PLL_USBPLLCON_VCOBYP_Msk \ - (0x1UL) /*!< SCU_PLL USBPLLCON: VCOBYP (Bitfield-Mask: 0x01) */ -#define SCU_PLL_USBPLLCON_VCOPWD_Pos \ - (1UL) /*!< SCU_PLL USBPLLCON: VCOPWD (Bit 1) */ -#define SCU_PLL_USBPLLCON_VCOPWD_Msk \ - (0x2UL) /*!< SCU_PLL USBPLLCON: VCOPWD (Bitfield-Mask: 0x01) */ -#define SCU_PLL_USBPLLCON_VCOTR_Pos \ - (2UL) /*!< SCU_PLL USBPLLCON: VCOTR (Bit 2) */ -#define SCU_PLL_USBPLLCON_VCOTR_Msk \ - (0x4UL) /*!< SCU_PLL USBPLLCON: VCOTR (Bitfield-Mask: 0x01) */ -#define SCU_PLL_USBPLLCON_FINDIS_Pos \ - (4UL) /*!< SCU_PLL USBPLLCON: FINDIS (Bit 4) */ -#define SCU_PLL_USBPLLCON_FINDIS_Msk \ - (0x10UL) /*!< SCU_PLL USBPLLCON: FINDIS (Bitfield-Mask: 0x01) */ -#define SCU_PLL_USBPLLCON_OSCDISCDIS_Pos \ - (6UL) /*!< SCU_PLL USBPLLCON: OSCDISCDIS (Bit 6) */ -#define SCU_PLL_USBPLLCON_OSCDISCDIS_Msk \ - (0x40UL) /*!< SCU_PLL USBPLLCON: OSCDISCDIS (Bitfield-Mask: 0x01) */ -#define SCU_PLL_USBPLLCON_NDIV_Pos \ - (8UL) /*!< SCU_PLL USBPLLCON: NDIV (Bit 8) */ -#define SCU_PLL_USBPLLCON_NDIV_Msk \ - (0x7f00UL) /*!< SCU_PLL USBPLLCON: NDIV (Bitfield-Mask: 0x7f) */ -#define SCU_PLL_USBPLLCON_PLLPWD_Pos \ - (16UL) /*!< SCU_PLL USBPLLCON: PLLPWD (Bit 16) */ -#define SCU_PLL_USBPLLCON_PLLPWD_Msk \ - (0x10000UL) /*!< SCU_PLL USBPLLCON: PLLPWD (Bitfield-Mask: 0x01) */ -#define SCU_PLL_USBPLLCON_RESLD_Pos \ - (18UL) /*!< SCU_PLL USBPLLCON: RESLD (Bit 18) */ -#define SCU_PLL_USBPLLCON_RESLD_Msk \ - (0x40000UL) /*!< SCU_PLL USBPLLCON: RESLD (Bitfield-Mask: 0x01) */ -#define SCU_PLL_USBPLLCON_PDIV_Pos \ - (24UL) /*!< SCU_PLL USBPLLCON: PDIV (Bit 24) */ -#define SCU_PLL_USBPLLCON_PDIV_Msk \ - (0xf000000UL) /*!< SCU_PLL USBPLLCON: PDIV (Bitfield-Mask: 0x0f) */ - -/* ------------------------------ SCU_PLL_CLKMXSTAT ----------------------------- */ -#define SCU_PLL_CLKMXSTAT_SYSCLKMUX_Pos \ - (0UL) /*!< SCU_PLL CLKMXSTAT: SYSCLKMUX (Bit 0) */ -#define SCU_PLL_CLKMXSTAT_SYSCLKMUX_Msk \ - (0x3UL) /*!< SCU_PLL CLKMXSTAT: SYSCLKMUX (Bitfield-Mask: 0x03) */ - -/* ================================================================================ */ -/* ================ struct 'SCU_GENERAL' Position & Mask ================ */ -/* ================================================================================ */ - -/* ------------------------------- SCU_GENERAL_ID ------------------------------- */ -#define SCU_GENERAL_ID_MOD_REV_Pos \ - (0UL) /*!< SCU_GENERAL ID: MOD_REV (Bit 0) */ -#define SCU_GENERAL_ID_MOD_REV_Msk \ - (0xffUL) /*!< SCU_GENERAL ID: MOD_REV (Bitfield-Mask: 0xff) */ -#define SCU_GENERAL_ID_MOD_TYPE_Pos \ - (8UL) /*!< SCU_GENERAL ID: MOD_TYPE (Bit 8) */ -#define SCU_GENERAL_ID_MOD_TYPE_Msk \ - (0xff00UL) /*!< SCU_GENERAL ID: MOD_TYPE (Bitfield-Mask: 0xff) */ -#define SCU_GENERAL_ID_MOD_NUMBER_Pos \ - (16UL) /*!< SCU_GENERAL ID: MOD_NUMBER (Bit 16) */ -#define SCU_GENERAL_ID_MOD_NUMBER_Msk \ - (0xffff0000UL) /*!< SCU_GENERAL ID: MOD_NUMBER (Bitfield-Mask: 0xffff) */ - -/* ----------------------------- SCU_GENERAL_IDCHIP ----------------------------- */ -#define SCU_GENERAL_IDCHIP_IDCHIP_Pos \ - (0UL) /*!< SCU_GENERAL IDCHIP: IDCHIP (Bit 0) */ -#define SCU_GENERAL_IDCHIP_IDCHIP_Msk \ - (0xffffffffUL) /*!< SCU_GENERAL IDCHIP: IDCHIP (Bitfield-Mask: 0xffffffff) */ - -/* ----------------------------- SCU_GENERAL_IDMANUF ---------------------------- */ -#define SCU_GENERAL_IDMANUF_DEPT_Pos \ - (0UL) /*!< SCU_GENERAL IDMANUF: DEPT (Bit 0) */ -#define SCU_GENERAL_IDMANUF_DEPT_Msk \ - (0x1fUL) /*!< SCU_GENERAL IDMANUF: DEPT (Bitfield-Mask: 0x1f) */ -#define SCU_GENERAL_IDMANUF_MANUF_Pos \ - (5UL) /*!< SCU_GENERAL IDMANUF: MANUF (Bit 5) */ -#define SCU_GENERAL_IDMANUF_MANUF_Msk \ - (0xffe0UL) /*!< SCU_GENERAL IDMANUF: MANUF (Bitfield-Mask: 0x7ff) */ - -/* ------------------------------ SCU_GENERAL_STCON ----------------------------- */ -#define SCU_GENERAL_STCON_HWCON_Pos \ - (0UL) /*!< SCU_GENERAL STCON: HWCON (Bit 0) */ -#define SCU_GENERAL_STCON_HWCON_Msk \ - (0x3UL) /*!< SCU_GENERAL STCON: HWCON (Bitfield-Mask: 0x03) */ -#define SCU_GENERAL_STCON_SWCON_Pos \ - (8UL) /*!< SCU_GENERAL STCON: SWCON (Bit 8) */ -#define SCU_GENERAL_STCON_SWCON_Msk \ - (0xf00UL) /*!< SCU_GENERAL STCON: SWCON (Bitfield-Mask: 0x0f) */ - -/* ------------------------------- SCU_GENERAL_GPR ------------------------------ */ -#define SCU_GENERAL_GPR_DAT_Pos \ - (0UL) /*!< SCU_GENERAL GPR: DAT (Bit 0) */ -#define SCU_GENERAL_GPR_DAT_Msk \ - (0xffffffffUL) /*!< SCU_GENERAL GPR: DAT (Bitfield-Mask: 0xffffffff) */ - -/* ----------------------------- SCU_GENERAL_CCUCON ----------------------------- */ -#define SCU_GENERAL_CCUCON_GSC40_Pos \ - (0UL) /*!< SCU_GENERAL CCUCON: GSC40 (Bit 0) */ -#define SCU_GENERAL_CCUCON_GSC40_Msk \ - (0x1UL) /*!< SCU_GENERAL CCUCON: GSC40 (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_CCUCON_GSC41_Pos \ - (1UL) /*!< SCU_GENERAL CCUCON: GSC41 (Bit 1) */ -#define SCU_GENERAL_CCUCON_GSC41_Msk \ - (0x2UL) /*!< SCU_GENERAL CCUCON: GSC41 (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_CCUCON_GSC42_Pos \ - (2UL) /*!< SCU_GENERAL CCUCON: GSC42 (Bit 2) */ -#define SCU_GENERAL_CCUCON_GSC42_Msk \ - (0x4UL) /*!< SCU_GENERAL CCUCON: GSC42 (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_CCUCON_GSC43_Pos \ - (3UL) /*!< SCU_GENERAL CCUCON: GSC43 (Bit 3) */ -#define SCU_GENERAL_CCUCON_GSC43_Msk \ - (0x8UL) /*!< SCU_GENERAL CCUCON: GSC43 (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_CCUCON_GSC80_Pos \ - (8UL) /*!< SCU_GENERAL CCUCON: GSC80 (Bit 8) */ -#define SCU_GENERAL_CCUCON_GSC80_Msk \ - (0x100UL) /*!< SCU_GENERAL CCUCON: GSC80 (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_CCUCON_GSC81_Pos \ - (9UL) /*!< SCU_GENERAL CCUCON: GSC81 (Bit 9) */ -#define SCU_GENERAL_CCUCON_GSC81_Msk \ - (0x200UL) /*!< SCU_GENERAL CCUCON: GSC81 (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_CCUCON_GSHR0_Pos \ - (24UL) /*!< SCU_GENERAL CCUCON: GSHR0 (Bit 24) */ -#define SCU_GENERAL_CCUCON_GSHR0_Msk \ - (0x1000000UL) /*!< SCU_GENERAL CCUCON: GSHR0 (Bitfield-Mask: 0x01) */ - -/* ----------------------------- SCU_GENERAL_DTSCON ----------------------------- */ -#define SCU_GENERAL_DTSCON_PWD_Pos \ - (0UL) /*!< SCU_GENERAL DTSCON: PWD (Bit 0) */ -#define SCU_GENERAL_DTSCON_PWD_Msk \ - (0x1UL) /*!< SCU_GENERAL DTSCON: PWD (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_DTSCON_START_Pos \ - (1UL) /*!< SCU_GENERAL DTSCON: START (Bit 1) */ -#define SCU_GENERAL_DTSCON_START_Msk \ - (0x2UL) /*!< SCU_GENERAL DTSCON: START (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_DTSCON_OFFSET_Pos \ - (4UL) /*!< SCU_GENERAL DTSCON: OFFSET (Bit 4) */ -#define SCU_GENERAL_DTSCON_OFFSET_Msk \ - (0x7f0UL) /*!< SCU_GENERAL DTSCON: OFFSET (Bitfield-Mask: 0x7f) */ -#define SCU_GENERAL_DTSCON_GAIN_Pos \ - (11UL) /*!< SCU_GENERAL DTSCON: GAIN (Bit 11) */ -#define SCU_GENERAL_DTSCON_GAIN_Msk \ - (0x1f800UL) /*!< SCU_GENERAL DTSCON: GAIN (Bitfield-Mask: 0x3f) */ -#define SCU_GENERAL_DTSCON_REFTRIM_Pos \ - (17UL) /*!< SCU_GENERAL DTSCON: REFTRIM (Bit 17) */ -#define SCU_GENERAL_DTSCON_REFTRIM_Msk \ - (0xe0000UL) /*!< SCU_GENERAL DTSCON: REFTRIM (Bitfield-Mask: 0x07) */ -#define SCU_GENERAL_DTSCON_BGTRIM_Pos \ - (20UL) /*!< SCU_GENERAL DTSCON: BGTRIM (Bit 20) */ -#define SCU_GENERAL_DTSCON_BGTRIM_Msk \ - (0xf00000UL) /*!< SCU_GENERAL DTSCON: BGTRIM (Bitfield-Mask: 0x0f) */ - -/* ----------------------------- SCU_GENERAL_DTSSTAT ---------------------------- */ -#define SCU_GENERAL_DTSSTAT_RESULT_Pos \ - (0UL) /*!< SCU_GENERAL DTSSTAT: RESULT (Bit 0) */ -#define SCU_GENERAL_DTSSTAT_RESULT_Msk \ - (0x3ffUL) /*!< SCU_GENERAL DTSSTAT: RESULT (Bitfield-Mask: 0x3ff) */ -#define SCU_GENERAL_DTSSTAT_RDY_Pos \ - (14UL) /*!< SCU_GENERAL DTSSTAT: RDY (Bit 14) */ -#define SCU_GENERAL_DTSSTAT_RDY_Msk \ - (0x4000UL) /*!< SCU_GENERAL DTSSTAT: RDY (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_DTSSTAT_BUSY_Pos \ - (15UL) /*!< SCU_GENERAL DTSSTAT: BUSY (Bit 15) */ -#define SCU_GENERAL_DTSSTAT_BUSY_Msk \ - (0x8000UL) /*!< SCU_GENERAL DTSSTAT: BUSY (Bitfield-Mask: 0x01) */ - -/* ----------------------------- SCU_GENERAL_GORCEN ----------------------------- */ -#define SCU_GENERAL_GORCEN_ENORC6_Pos \ - (6UL) /*!< SCU_GENERAL GORCEN: ENORC6 (Bit 6) */ -#define SCU_GENERAL_GORCEN_ENORC6_Msk \ - (0x40UL) /*!< SCU_GENERAL GORCEN: ENORC6 (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_GORCEN_ENORC7_Pos \ - (7UL) /*!< SCU_GENERAL GORCEN: ENORC7 (Bit 7) */ -#define SCU_GENERAL_GORCEN_ENORC7_Msk \ - (0x80UL) /*!< SCU_GENERAL GORCEN: ENORC7 (Bitfield-Mask: 0x01) */ - -/* ---------------------------- SCU_GENERAL_DTEMPLIM ---------------------------- */ -#define SCU_GENERAL_DTEMPLIM_LOWER_Pos \ - (0UL) /*!< SCU_GENERAL DTEMPLIM: LOWER (Bit 0) */ -#define SCU_GENERAL_DTEMPLIM_LOWER_Msk \ - (0x3ffUL) /*!< SCU_GENERAL DTEMPLIM: LOWER (Bitfield-Mask: 0x3ff) */ -#define SCU_GENERAL_DTEMPLIM_UPPER_Pos \ - (16UL) /*!< SCU_GENERAL DTEMPLIM: UPPER (Bit 16) */ -#define SCU_GENERAL_DTEMPLIM_UPPER_Msk \ - (0x3ff0000UL) /*!< SCU_GENERAL DTEMPLIM: UPPER (Bitfield-Mask: 0x3ff) */ - -/* --------------------------- SCU_GENERAL_DTEMPALARM --------------------------- */ -#define SCU_GENERAL_DTEMPALARM_UNDERFL_Pos \ - (0UL) /*!< SCU_GENERAL DTEMPALARM: UNDERFL (Bit 0) */ -#define SCU_GENERAL_DTEMPALARM_UNDERFL_Msk \ - (0x1UL) /*!< SCU_GENERAL DTEMPALARM: UNDERFL (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_DTEMPALARM_OVERFL_Pos \ - (16UL) /*!< SCU_GENERAL DTEMPALARM: OVERFL (Bit 16) */ -#define SCU_GENERAL_DTEMPALARM_OVERFL_Msk \ - (0x10000UL) /*!< SCU_GENERAL DTEMPALARM: OVERFL (Bitfield-Mask: 0x01) */ - -/* ----------------------------- SCU_GENERAL_MIRRSTS ---------------------------- */ -#define SCU_GENERAL_MIRRSTS_HDCLR_Pos \ - (1UL) /*!< SCU_GENERAL MIRRSTS: HDCLR (Bit 1) */ -#define SCU_GENERAL_MIRRSTS_HDCLR_Msk \ - (0x2UL) /*!< SCU_GENERAL MIRRSTS: HDCLR (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_MIRRSTS_HDSET_Pos \ - (2UL) /*!< SCU_GENERAL MIRRSTS: HDSET (Bit 2) */ -#define SCU_GENERAL_MIRRSTS_HDSET_Msk \ - (0x4UL) /*!< SCU_GENERAL MIRRSTS: HDSET (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_MIRRSTS_HDCR_Pos \ - (3UL) /*!< SCU_GENERAL MIRRSTS: HDCR (Bit 3) */ -#define SCU_GENERAL_MIRRSTS_HDCR_Msk \ - (0x8UL) /*!< SCU_GENERAL MIRRSTS: HDCR (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_MIRRSTS_OSCSICTRL_Pos \ - (5UL) /*!< SCU_GENERAL MIRRSTS: OSCSICTRL (Bit 5) */ -#define SCU_GENERAL_MIRRSTS_OSCSICTRL_Msk \ - (0x20UL) /*!< SCU_GENERAL MIRRSTS: OSCSICTRL (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_MIRRSTS_OSCULCTRL_Pos \ - (7UL) /*!< SCU_GENERAL MIRRSTS: OSCULCTRL (Bit 7) */ -#define SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk \ - (0x80UL) /*!< SCU_GENERAL MIRRSTS: OSCULCTRL (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_MIRRSTS_RTC_CTR_Pos \ - (8UL) /*!< SCU_GENERAL MIRRSTS: RTC_CTR (Bit 8) */ -#define SCU_GENERAL_MIRRSTS_RTC_CTR_Msk \ - (0x100UL) /*!< SCU_GENERAL MIRRSTS: RTC_CTR (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_MIRRSTS_RTC_ATIM0_Pos \ - (9UL) /*!< SCU_GENERAL MIRRSTS: RTC_ATIM0 (Bit 9) */ -#define SCU_GENERAL_MIRRSTS_RTC_ATIM0_Msk \ - (0x200UL) /*!< SCU_GENERAL MIRRSTS: RTC_ATIM0 (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_MIRRSTS_RTC_ATIM1_Pos \ - (10UL) /*!< SCU_GENERAL MIRRSTS: RTC_ATIM1 (Bit 10) */ -#define SCU_GENERAL_MIRRSTS_RTC_ATIM1_Msk \ - (0x400UL) /*!< SCU_GENERAL MIRRSTS: RTC_ATIM1 (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_MIRRSTS_RTC_TIM0_Pos \ - (11UL) /*!< SCU_GENERAL MIRRSTS: RTC_TIM0 (Bit 11) */ -#define SCU_GENERAL_MIRRSTS_RTC_TIM0_Msk \ - (0x800UL) /*!< SCU_GENERAL MIRRSTS: RTC_TIM0 (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_MIRRSTS_RTC_TIM1_Pos \ - (12UL) /*!< SCU_GENERAL MIRRSTS: RTC_TIM1 (Bit 12) */ -#define SCU_GENERAL_MIRRSTS_RTC_TIM1_Msk \ - (0x1000UL) /*!< SCU_GENERAL MIRRSTS: RTC_TIM1 (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_MIRRSTS_RMX_Pos \ - (13UL) /*!< SCU_GENERAL MIRRSTS: RMX (Bit 13) */ -#define SCU_GENERAL_MIRRSTS_RMX_Msk \ - (0x2000UL) /*!< SCU_GENERAL MIRRSTS: RMX (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_MIRRSTS_RTC_MSKSR_Pos \ - (14UL) /*!< SCU_GENERAL MIRRSTS: RTC_MSKSR (Bit 14) */ -#define SCU_GENERAL_MIRRSTS_RTC_MSKSR_Msk \ - (0x4000UL) /*!< SCU_GENERAL MIRRSTS: RTC_MSKSR (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_MIRRSTS_RTC_CLRSR_Pos \ - (15UL) /*!< SCU_GENERAL MIRRSTS: RTC_CLRSR (Bit 15) */ -#define SCU_GENERAL_MIRRSTS_RTC_CLRSR_Msk \ - (0x8000UL) /*!< SCU_GENERAL MIRRSTS: RTC_CLRSR (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_MIRRSTS_LPACCONF_Pos \ - (16UL) /*!< SCU_GENERAL MIRRSTS: LPACCONF (Bit 16) */ -#define SCU_GENERAL_MIRRSTS_LPACCONF_Msk \ - (0x10000UL) /*!< SCU_GENERAL MIRRSTS: LPACCONF (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_MIRRSTS_LPACTH0_Pos \ - (17UL) /*!< SCU_GENERAL MIRRSTS: LPACTH0 (Bit 17) */ -#define SCU_GENERAL_MIRRSTS_LPACTH0_Msk \ - (0x20000UL) /*!< SCU_GENERAL MIRRSTS: LPACTH0 (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_MIRRSTS_LPACTH1_Pos \ - (18UL) /*!< SCU_GENERAL MIRRSTS: LPACTH1 (Bit 18) */ -#define SCU_GENERAL_MIRRSTS_LPACTH1_Msk \ - (0x40000UL) /*!< SCU_GENERAL MIRRSTS: LPACTH1 (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_MIRRSTS_LPACCLR_Pos \ - (20UL) /*!< SCU_GENERAL MIRRSTS: LPACCLR (Bit 20) */ -#define SCU_GENERAL_MIRRSTS_LPACCLR_Msk \ - (0x100000UL) /*!< SCU_GENERAL MIRRSTS: LPACCLR (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_MIRRSTS_LPACSET_Pos \ - (21UL) /*!< SCU_GENERAL MIRRSTS: LPACSET (Bit 21) */ -#define SCU_GENERAL_MIRRSTS_LPACSET_Msk \ - (0x200000UL) /*!< SCU_GENERAL MIRRSTS: LPACSET (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_MIRRSTS_HINTCLR_Pos \ - (23UL) /*!< SCU_GENERAL MIRRSTS: HINTCLR (Bit 23) */ -#define SCU_GENERAL_MIRRSTS_HINTCLR_Msk \ - (0x800000UL) /*!< SCU_GENERAL MIRRSTS: HINTCLR (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_MIRRSTS_HINTSET_Pos \ - (24UL) /*!< SCU_GENERAL MIRRSTS: HINTSET (Bit 24) */ -#define SCU_GENERAL_MIRRSTS_HINTSET_Msk \ - (0x1000000UL) /*!< SCU_GENERAL MIRRSTS: HINTSET (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_GENERAL_RMACR ----------------------------- */ -#define SCU_GENERAL_RMACR_RDWR_Pos \ - (0UL) /*!< SCU_GENERAL RMACR: RDWR (Bit 0) */ -#define SCU_GENERAL_RMACR_RDWR_Msk \ - (0x1UL) /*!< SCU_GENERAL RMACR: RDWR (Bitfield-Mask: 0x01) */ -#define SCU_GENERAL_RMACR_ADDR_Pos \ - (16UL) /*!< SCU_GENERAL RMACR: ADDR (Bit 16) */ -#define SCU_GENERAL_RMACR_ADDR_Msk \ - (0xf0000UL) /*!< SCU_GENERAL RMACR: ADDR (Bitfield-Mask: 0x0f) */ - -/* ----------------------------- SCU_GENERAL_RMDATA ----------------------------- */ -#define SCU_GENERAL_RMDATA_DATA_Pos \ - (0UL) /*!< SCU_GENERAL RMDATA: DATA (Bit 0) */ -#define SCU_GENERAL_RMDATA_DATA_Msk \ - (0xffffffffUL) /*!< SCU_GENERAL RMDATA: DATA (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------- SCU_GENERAL_MIRRALLSTAT -------------------------- */ -#define SCU_GENERAL_MIRRALLSTAT_BUSY_Pos \ - (0UL) /*!< SCU_GENERAL MIRRALLSTAT: BUSY (Bit 0) */ -#define SCU_GENERAL_MIRRALLSTAT_BUSY_Msk \ - (0x1UL) /*!< SCU_GENERAL MIRRALLSTAT: BUSY (Bitfield-Mask: 0x01) */ - -/* --------------------------- SCU_GENERAL_MIRRALLREQ --------------------------- */ -#define SCU_GENERAL_MIRRALLREQ_REQ_Pos \ - (0UL) /*!< SCU_GENERAL MIRRALLREQ: REQ (Bit 0) */ -#define SCU_GENERAL_MIRRALLREQ_REQ_Msk \ - (0x1UL) /*!< SCU_GENERAL MIRRALLREQ: REQ (Bitfield-Mask: 0x01) */ - -/* ================================================================================ */ -/* ================ struct 'SCU_INTERRUPT' Position & Mask ================ */ -/* ================================================================================ */ - -/* ---------------------------- SCU_INTERRUPT_SRSTAT ---------------------------- */ -#define SCU_INTERRUPT_SRSTAT_PRWARN_Pos \ - (0UL) /*!< SCU_INTERRUPT SRSTAT: PRWARN (Bit 0) */ -#define SCU_INTERRUPT_SRSTAT_PRWARN_Msk \ - (0x1UL) /*!< SCU_INTERRUPT SRSTAT: PRWARN (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSTAT_PI_Pos \ - (1UL) /*!< SCU_INTERRUPT SRSTAT: PI (Bit 1) */ -#define SCU_INTERRUPT_SRSTAT_PI_Msk \ - (0x2UL) /*!< SCU_INTERRUPT SRSTAT: PI (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSTAT_AI_Pos \ - (2UL) /*!< SCU_INTERRUPT SRSTAT: AI (Bit 2) */ -#define SCU_INTERRUPT_SRSTAT_AI_Msk \ - (0x4UL) /*!< SCU_INTERRUPT SRSTAT: AI (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSTAT_DLROVR_Pos \ - (3UL) /*!< SCU_INTERRUPT SRSTAT: DLROVR (Bit 3) */ -#define SCU_INTERRUPT_SRSTAT_DLROVR_Msk \ - (0x8UL) /*!< SCU_INTERRUPT SRSTAT: DLROVR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSTAT_LPACCR_Pos \ - (6UL) /*!< SCU_INTERRUPT SRSTAT: LPACCR (Bit 6) */ -#define SCU_INTERRUPT_SRSTAT_LPACCR_Msk \ - (0x40UL) /*!< SCU_INTERRUPT SRSTAT: LPACCR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSTAT_LPACTH0_Pos \ - (7UL) /*!< SCU_INTERRUPT SRSTAT: LPACTH0 (Bit 7) */ -#define SCU_INTERRUPT_SRSTAT_LPACTH0_Msk \ - (0x80UL) /*!< SCU_INTERRUPT SRSTAT: LPACTH0 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSTAT_LPACTH1_Pos \ - (8UL) /*!< SCU_INTERRUPT SRSTAT: LPACTH1 (Bit 8) */ -#define SCU_INTERRUPT_SRSTAT_LPACTH1_Msk \ - (0x100UL) /*!< SCU_INTERRUPT SRSTAT: LPACTH1 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSTAT_LPACST_Pos \ - (9UL) /*!< SCU_INTERRUPT SRSTAT: LPACST (Bit 9) */ -#define SCU_INTERRUPT_SRSTAT_LPACST_Msk \ - (0x200UL) /*!< SCU_INTERRUPT SRSTAT: LPACST (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSTAT_LPACCLR_Pos \ - (10UL) /*!< SCU_INTERRUPT SRSTAT: LPACCLR (Bit 10) */ -#define SCU_INTERRUPT_SRSTAT_LPACCLR_Msk \ - (0x400UL) /*!< SCU_INTERRUPT SRSTAT: LPACCLR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSTAT_LPACSET_Pos \ - (11UL) /*!< SCU_INTERRUPT SRSTAT: LPACSET (Bit 11) */ -#define SCU_INTERRUPT_SRSTAT_LPACSET_Msk \ - (0x800UL) /*!< SCU_INTERRUPT SRSTAT: LPACSET (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSTAT_HINTST_Pos \ - (12UL) /*!< SCU_INTERRUPT SRSTAT: HINTST (Bit 12) */ -#define SCU_INTERRUPT_SRSTAT_HINTST_Msk \ - (0x1000UL) /*!< SCU_INTERRUPT SRSTAT: HINTST (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSTAT_HINTCLR_Pos \ - (13UL) /*!< SCU_INTERRUPT SRSTAT: HINTCLR (Bit 13) */ -#define SCU_INTERRUPT_SRSTAT_HINTCLR_Msk \ - (0x2000UL) /*!< SCU_INTERRUPT SRSTAT: HINTCLR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSTAT_HINTSET_Pos \ - (14UL) /*!< SCU_INTERRUPT SRSTAT: HINTSET (Bit 14) */ -#define SCU_INTERRUPT_SRSTAT_HINTSET_Msk \ - (0x4000UL) /*!< SCU_INTERRUPT SRSTAT: HINTSET (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSTAT_HDCLR_Pos \ - (17UL) /*!< SCU_INTERRUPT SRSTAT: HDCLR (Bit 17) */ -#define SCU_INTERRUPT_SRSTAT_HDCLR_Msk \ - (0x20000UL) /*!< SCU_INTERRUPT SRSTAT: HDCLR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSTAT_HDSET_Pos \ - (18UL) /*!< SCU_INTERRUPT SRSTAT: HDSET (Bit 18) */ -#define SCU_INTERRUPT_SRSTAT_HDSET_Msk \ - (0x40000UL) /*!< SCU_INTERRUPT SRSTAT: HDSET (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSTAT_HDCR_Pos \ - (19UL) /*!< SCU_INTERRUPT SRSTAT: HDCR (Bit 19) */ -#define SCU_INTERRUPT_SRSTAT_HDCR_Msk \ - (0x80000UL) /*!< SCU_INTERRUPT SRSTAT: HDCR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSTAT_OSCSICTRL_Pos \ - (21UL) /*!< SCU_INTERRUPT SRSTAT: OSCSICTRL (Bit 21) */ -#define SCU_INTERRUPT_SRSTAT_OSCSICTRL_Msk \ - (0x200000UL) /*!< SCU_INTERRUPT SRSTAT: OSCSICTRL (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSTAT_OSCULCTRL_Pos \ - (23UL) /*!< SCU_INTERRUPT SRSTAT: OSCULCTRL (Bit 23) */ -#define SCU_INTERRUPT_SRSTAT_OSCULCTRL_Msk \ - (0x800000UL) /*!< SCU_INTERRUPT SRSTAT: OSCULCTRL (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSTAT_RTC_CTR_Pos \ - (24UL) /*!< SCU_INTERRUPT SRSTAT: RTC_CTR (Bit 24) */ -#define SCU_INTERRUPT_SRSTAT_RTC_CTR_Msk \ - (0x1000000UL) /*!< SCU_INTERRUPT SRSTAT: RTC_CTR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSTAT_RTC_ATIM0_Pos \ - (25UL) /*!< SCU_INTERRUPT SRSTAT: RTC_ATIM0 (Bit 25) */ -#define SCU_INTERRUPT_SRSTAT_RTC_ATIM0_Msk \ - (0x2000000UL) /*!< SCU_INTERRUPT SRSTAT: RTC_ATIM0 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSTAT_RTC_ATIM1_Pos \ - (26UL) /*!< SCU_INTERRUPT SRSTAT: RTC_ATIM1 (Bit 26) */ -#define SCU_INTERRUPT_SRSTAT_RTC_ATIM1_Msk \ - (0x4000000UL) /*!< SCU_INTERRUPT SRSTAT: RTC_ATIM1 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSTAT_RTC_TIM0_Pos \ - (27UL) /*!< SCU_INTERRUPT SRSTAT: RTC_TIM0 (Bit 27) */ -#define SCU_INTERRUPT_SRSTAT_RTC_TIM0_Msk \ - (0x8000000UL) /*!< SCU_INTERRUPT SRSTAT: RTC_TIM0 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSTAT_RTC_TIM1_Pos \ - (28UL) /*!< SCU_INTERRUPT SRSTAT: RTC_TIM1 (Bit 28) */ -#define SCU_INTERRUPT_SRSTAT_RTC_TIM1_Msk \ - (0x10000000UL) /*!< SCU_INTERRUPT SRSTAT: RTC_TIM1 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSTAT_RMX_Pos \ - (29UL) /*!< SCU_INTERRUPT SRSTAT: RMX (Bit 29) */ -#define SCU_INTERRUPT_SRSTAT_RMX_Msk \ - (0x20000000UL) /*!< SCU_INTERRUPT SRSTAT: RMX (Bitfield-Mask: 0x01) */ - -/* ----------------------------- SCU_INTERRUPT_SRRAW ---------------------------- */ -#define SCU_INTERRUPT_SRRAW_PRWARN_Pos \ - (0UL) /*!< SCU_INTERRUPT SRRAW: PRWARN (Bit 0) */ -#define SCU_INTERRUPT_SRRAW_PRWARN_Msk \ - (0x1UL) /*!< SCU_INTERRUPT SRRAW: PRWARN (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRRAW_PI_Pos \ - (1UL) /*!< SCU_INTERRUPT SRRAW: PI (Bit 1) */ -#define SCU_INTERRUPT_SRRAW_PI_Msk \ - (0x2UL) /*!< SCU_INTERRUPT SRRAW: PI (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRRAW_AI_Pos \ - (2UL) /*!< SCU_INTERRUPT SRRAW: AI (Bit 2) */ -#define SCU_INTERRUPT_SRRAW_AI_Msk \ - (0x4UL) /*!< SCU_INTERRUPT SRRAW: AI (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRRAW_DLROVR_Pos \ - (3UL) /*!< SCU_INTERRUPT SRRAW: DLROVR (Bit 3) */ -#define SCU_INTERRUPT_SRRAW_DLROVR_Msk \ - (0x8UL) /*!< SCU_INTERRUPT SRRAW: DLROVR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRRAW_LPACCR_Pos \ - (6UL) /*!< SCU_INTERRUPT SRRAW: LPACCR (Bit 6) */ -#define SCU_INTERRUPT_SRRAW_LPACCR_Msk \ - (0x40UL) /*!< SCU_INTERRUPT SRRAW: LPACCR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRRAW_LPACTH0_Pos \ - (7UL) /*!< SCU_INTERRUPT SRRAW: LPACTH0 (Bit 7) */ -#define SCU_INTERRUPT_SRRAW_LPACTH0_Msk \ - (0x80UL) /*!< SCU_INTERRUPT SRRAW: LPACTH0 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRRAW_LPACTH1_Pos \ - (8UL) /*!< SCU_INTERRUPT SRRAW: LPACTH1 (Bit 8) */ -#define SCU_INTERRUPT_SRRAW_LPACTH1_Msk \ - (0x100UL) /*!< SCU_INTERRUPT SRRAW: LPACTH1 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRRAW_LPACST_Pos \ - (9UL) /*!< SCU_INTERRUPT SRRAW: LPACST (Bit 9) */ -#define SCU_INTERRUPT_SRRAW_LPACST_Msk \ - (0x200UL) /*!< SCU_INTERRUPT SRRAW: LPACST (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRRAW_LPACCLR_Pos \ - (10UL) /*!< SCU_INTERRUPT SRRAW: LPACCLR (Bit 10) */ -#define SCU_INTERRUPT_SRRAW_LPACCLR_Msk \ - (0x400UL) /*!< SCU_INTERRUPT SRRAW: LPACCLR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRRAW_LPACSET_Pos \ - (11UL) /*!< SCU_INTERRUPT SRRAW: LPACSET (Bit 11) */ -#define SCU_INTERRUPT_SRRAW_LPACSET_Msk \ - (0x800UL) /*!< SCU_INTERRUPT SRRAW: LPACSET (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRRAW_HINTST_Pos \ - (12UL) /*!< SCU_INTERRUPT SRRAW: HINTST (Bit 12) */ -#define SCU_INTERRUPT_SRRAW_HINTST_Msk \ - (0x1000UL) /*!< SCU_INTERRUPT SRRAW: HINTST (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRRAW_HINTCLR_Pos \ - (13UL) /*!< SCU_INTERRUPT SRRAW: HINTCLR (Bit 13) */ -#define SCU_INTERRUPT_SRRAW_HINTCLR_Msk \ - (0x2000UL) /*!< SCU_INTERRUPT SRRAW: HINTCLR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRRAW_HINTSET_Pos \ - (14UL) /*!< SCU_INTERRUPT SRRAW: HINTSET (Bit 14) */ -#define SCU_INTERRUPT_SRRAW_HINTSET_Msk \ - (0x4000UL) /*!< SCU_INTERRUPT SRRAW: HINTSET (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRRAW_HDCLR_Pos \ - (17UL) /*!< SCU_INTERRUPT SRRAW: HDCLR (Bit 17) */ -#define SCU_INTERRUPT_SRRAW_HDCLR_Msk \ - (0x20000UL) /*!< SCU_INTERRUPT SRRAW: HDCLR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRRAW_HDSET_Pos \ - (18UL) /*!< SCU_INTERRUPT SRRAW: HDSET (Bit 18) */ -#define SCU_INTERRUPT_SRRAW_HDSET_Msk \ - (0x40000UL) /*!< SCU_INTERRUPT SRRAW: HDSET (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRRAW_HDCR_Pos \ - (19UL) /*!< SCU_INTERRUPT SRRAW: HDCR (Bit 19) */ -#define SCU_INTERRUPT_SRRAW_HDCR_Msk \ - (0x80000UL) /*!< SCU_INTERRUPT SRRAW: HDCR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRRAW_OSCSICTRL_Pos \ - (21UL) /*!< SCU_INTERRUPT SRRAW: OSCSICTRL (Bit 21) */ -#define SCU_INTERRUPT_SRRAW_OSCSICTRL_Msk \ - (0x200000UL) /*!< SCU_INTERRUPT SRRAW: OSCSICTRL (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRRAW_OSCULCTRL_Pos \ - (23UL) /*!< SCU_INTERRUPT SRRAW: OSCULCTRL (Bit 23) */ -#define SCU_INTERRUPT_SRRAW_OSCULCTRL_Msk \ - (0x800000UL) /*!< SCU_INTERRUPT SRRAW: OSCULCTRL (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRRAW_RTC_CTR_Pos \ - (24UL) /*!< SCU_INTERRUPT SRRAW: RTC_CTR (Bit 24) */ -#define SCU_INTERRUPT_SRRAW_RTC_CTR_Msk \ - (0x1000000UL) /*!< SCU_INTERRUPT SRRAW: RTC_CTR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRRAW_RTC_ATIM0_Pos \ - (25UL) /*!< SCU_INTERRUPT SRRAW: RTC_ATIM0 (Bit 25) */ -#define SCU_INTERRUPT_SRRAW_RTC_ATIM0_Msk \ - (0x2000000UL) /*!< SCU_INTERRUPT SRRAW: RTC_ATIM0 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRRAW_RTC_ATIM1_Pos \ - (26UL) /*!< SCU_INTERRUPT SRRAW: RTC_ATIM1 (Bit 26) */ -#define SCU_INTERRUPT_SRRAW_RTC_ATIM1_Msk \ - (0x4000000UL) /*!< SCU_INTERRUPT SRRAW: RTC_ATIM1 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRRAW_RTC_TIM0_Pos \ - (27UL) /*!< SCU_INTERRUPT SRRAW: RTC_TIM0 (Bit 27) */ -#define SCU_INTERRUPT_SRRAW_RTC_TIM0_Msk \ - (0x8000000UL) /*!< SCU_INTERRUPT SRRAW: RTC_TIM0 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRRAW_RTC_TIM1_Pos \ - (28UL) /*!< SCU_INTERRUPT SRRAW: RTC_TIM1 (Bit 28) */ -#define SCU_INTERRUPT_SRRAW_RTC_TIM1_Msk \ - (0x10000000UL) /*!< SCU_INTERRUPT SRRAW: RTC_TIM1 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRRAW_RMX_Pos \ - (29UL) /*!< SCU_INTERRUPT SRRAW: RMX (Bit 29) */ -#define SCU_INTERRUPT_SRRAW_RMX_Msk \ - (0x20000000UL) /*!< SCU_INTERRUPT SRRAW: RMX (Bitfield-Mask: 0x01) */ - -/* ----------------------------- SCU_INTERRUPT_SRMSK ---------------------------- */ -#define SCU_INTERRUPT_SRMSK_PRWARN_Pos \ - (0UL) /*!< SCU_INTERRUPT SRMSK: PRWARN (Bit 0) */ -#define SCU_INTERRUPT_SRMSK_PRWARN_Msk \ - (0x1UL) /*!< SCU_INTERRUPT SRMSK: PRWARN (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRMSK_PI_Pos \ - (1UL) /*!< SCU_INTERRUPT SRMSK: PI (Bit 1) */ -#define SCU_INTERRUPT_SRMSK_PI_Msk \ - (0x2UL) /*!< SCU_INTERRUPT SRMSK: PI (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRMSK_AI_Pos \ - (2UL) /*!< SCU_INTERRUPT SRMSK: AI (Bit 2) */ -#define SCU_INTERRUPT_SRMSK_AI_Msk \ - (0x4UL) /*!< SCU_INTERRUPT SRMSK: AI (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRMSK_DLROVR_Pos \ - (3UL) /*!< SCU_INTERRUPT SRMSK: DLROVR (Bit 3) */ -#define SCU_INTERRUPT_SRMSK_DLROVR_Msk \ - (0x8UL) /*!< SCU_INTERRUPT SRMSK: DLROVR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRMSK_LPACCR_Pos \ - (6UL) /*!< SCU_INTERRUPT SRMSK: LPACCR (Bit 6) */ -#define SCU_INTERRUPT_SRMSK_LPACCR_Msk \ - (0x40UL) /*!< SCU_INTERRUPT SRMSK: LPACCR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRMSK_LPACTH0_Pos \ - (7UL) /*!< SCU_INTERRUPT SRMSK: LPACTH0 (Bit 7) */ -#define SCU_INTERRUPT_SRMSK_LPACTH0_Msk \ - (0x80UL) /*!< SCU_INTERRUPT SRMSK: LPACTH0 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRMSK_LPACTH1_Pos \ - (8UL) /*!< SCU_INTERRUPT SRMSK: LPACTH1 (Bit 8) */ -#define SCU_INTERRUPT_SRMSK_LPACTH1_Msk \ - (0x100UL) /*!< SCU_INTERRUPT SRMSK: LPACTH1 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRMSK_LPACST_Pos \ - (9UL) /*!< SCU_INTERRUPT SRMSK: LPACST (Bit 9) */ -#define SCU_INTERRUPT_SRMSK_LPACST_Msk \ - (0x200UL) /*!< SCU_INTERRUPT SRMSK: LPACST (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRMSK_LPACCLR_Pos \ - (10UL) /*!< SCU_INTERRUPT SRMSK: LPACCLR (Bit 10) */ -#define SCU_INTERRUPT_SRMSK_LPACCLR_Msk \ - (0x400UL) /*!< SCU_INTERRUPT SRMSK: LPACCLR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRMSK_LPACSET_Pos \ - (11UL) /*!< SCU_INTERRUPT SRMSK: LPACSET (Bit 11) */ -#define SCU_INTERRUPT_SRMSK_LPACSET_Msk \ - (0x800UL) /*!< SCU_INTERRUPT SRMSK: LPACSET (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRMSK_HINTST_Pos \ - (12UL) /*!< SCU_INTERRUPT SRMSK: HINTST (Bit 12) */ -#define SCU_INTERRUPT_SRMSK_HINTST_Msk \ - (0x1000UL) /*!< SCU_INTERRUPT SRMSK: HINTST (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRMSK_HINTCLR_Pos \ - (13UL) /*!< SCU_INTERRUPT SRMSK: HINTCLR (Bit 13) */ -#define SCU_INTERRUPT_SRMSK_HINTCLR_Msk \ - (0x2000UL) /*!< SCU_INTERRUPT SRMSK: HINTCLR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRMSK_HINTSET_Pos \ - (14UL) /*!< SCU_INTERRUPT SRMSK: HINTSET (Bit 14) */ -#define SCU_INTERRUPT_SRMSK_HINTSET_Msk \ - (0x4000UL) /*!< SCU_INTERRUPT SRMSK: HINTSET (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRMSK_HDCLR_Pos \ - (17UL) /*!< SCU_INTERRUPT SRMSK: HDCLR (Bit 17) */ -#define SCU_INTERRUPT_SRMSK_HDCLR_Msk \ - (0x20000UL) /*!< SCU_INTERRUPT SRMSK: HDCLR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRMSK_HDSET_Pos \ - (18UL) /*!< SCU_INTERRUPT SRMSK: HDSET (Bit 18) */ -#define SCU_INTERRUPT_SRMSK_HDSET_Msk \ - (0x40000UL) /*!< SCU_INTERRUPT SRMSK: HDSET (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRMSK_HDCR_Pos \ - (19UL) /*!< SCU_INTERRUPT SRMSK: HDCR (Bit 19) */ -#define SCU_INTERRUPT_SRMSK_HDCR_Msk \ - (0x80000UL) /*!< SCU_INTERRUPT SRMSK: HDCR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRMSK_OSCSICTRL_Pos \ - (21UL) /*!< SCU_INTERRUPT SRMSK: OSCSICTRL (Bit 21) */ -#define SCU_INTERRUPT_SRMSK_OSCSICTRL_Msk \ - (0x200000UL) /*!< SCU_INTERRUPT SRMSK: OSCSICTRL (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRMSK_OSCULCTRL_Pos \ - (23UL) /*!< SCU_INTERRUPT SRMSK: OSCULCTRL (Bit 23) */ -#define SCU_INTERRUPT_SRMSK_OSCULCTRL_Msk \ - (0x800000UL) /*!< SCU_INTERRUPT SRMSK: OSCULCTRL (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRMSK_RTC_CTR_Pos \ - (24UL) /*!< SCU_INTERRUPT SRMSK: RTC_CTR (Bit 24) */ -#define SCU_INTERRUPT_SRMSK_RTC_CTR_Msk \ - (0x1000000UL) /*!< SCU_INTERRUPT SRMSK: RTC_CTR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRMSK_RTC_ATIM0_Pos \ - (25UL) /*!< SCU_INTERRUPT SRMSK: RTC_ATIM0 (Bit 25) */ -#define SCU_INTERRUPT_SRMSK_RTC_ATIM0_Msk \ - (0x2000000UL) /*!< SCU_INTERRUPT SRMSK: RTC_ATIM0 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRMSK_RTC_ATIM1_Pos \ - (26UL) /*!< SCU_INTERRUPT SRMSK: RTC_ATIM1 (Bit 26) */ -#define SCU_INTERRUPT_SRMSK_RTC_ATIM1_Msk \ - (0x4000000UL) /*!< SCU_INTERRUPT SRMSK: RTC_ATIM1 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRMSK_RTC_TIM0_Pos \ - (27UL) /*!< SCU_INTERRUPT SRMSK: RTC_TIM0 (Bit 27) */ -#define SCU_INTERRUPT_SRMSK_RTC_TIM0_Msk \ - (0x8000000UL) /*!< SCU_INTERRUPT SRMSK: RTC_TIM0 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRMSK_RTC_TIM1_Pos \ - (28UL) /*!< SCU_INTERRUPT SRMSK: RTC_TIM1 (Bit 28) */ -#define SCU_INTERRUPT_SRMSK_RTC_TIM1_Msk \ - (0x10000000UL) /*!< SCU_INTERRUPT SRMSK: RTC_TIM1 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRMSK_RMX_Pos \ - (29UL) /*!< SCU_INTERRUPT SRMSK: RMX (Bit 29) */ -#define SCU_INTERRUPT_SRMSK_RMX_Msk \ - (0x20000000UL) /*!< SCU_INTERRUPT SRMSK: RMX (Bitfield-Mask: 0x01) */ - -/* ----------------------------- SCU_INTERRUPT_SRCLR ---------------------------- */ -#define SCU_INTERRUPT_SRCLR_PRWARN_Pos \ - (0UL) /*!< SCU_INTERRUPT SRCLR: PRWARN (Bit 0) */ -#define SCU_INTERRUPT_SRCLR_PRWARN_Msk \ - (0x1UL) /*!< SCU_INTERRUPT SRCLR: PRWARN (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRCLR_PI_Pos \ - (1UL) /*!< SCU_INTERRUPT SRCLR: PI (Bit 1) */ -#define SCU_INTERRUPT_SRCLR_PI_Msk \ - (0x2UL) /*!< SCU_INTERRUPT SRCLR: PI (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRCLR_AI_Pos \ - (2UL) /*!< SCU_INTERRUPT SRCLR: AI (Bit 2) */ -#define SCU_INTERRUPT_SRCLR_AI_Msk \ - (0x4UL) /*!< SCU_INTERRUPT SRCLR: AI (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRCLR_DLROVR_Pos \ - (3UL) /*!< SCU_INTERRUPT SRCLR: DLROVR (Bit 3) */ -#define SCU_INTERRUPT_SRCLR_DLROVR_Msk \ - (0x8UL) /*!< SCU_INTERRUPT SRCLR: DLROVR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRCLR_LPACCR_Pos \ - (6UL) /*!< SCU_INTERRUPT SRCLR: LPACCR (Bit 6) */ -#define SCU_INTERRUPT_SRCLR_LPACCR_Msk \ - (0x40UL) /*!< SCU_INTERRUPT SRCLR: LPACCR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRCLR_LPACTH0_Pos \ - (7UL) /*!< SCU_INTERRUPT SRCLR: LPACTH0 (Bit 7) */ -#define SCU_INTERRUPT_SRCLR_LPACTH0_Msk \ - (0x80UL) /*!< SCU_INTERRUPT SRCLR: LPACTH0 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRCLR_LPACTH1_Pos \ - (8UL) /*!< SCU_INTERRUPT SRCLR: LPACTH1 (Bit 8) */ -#define SCU_INTERRUPT_SRCLR_LPACTH1_Msk \ - (0x100UL) /*!< SCU_INTERRUPT SRCLR: LPACTH1 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRCLR_LPACST_Pos \ - (9UL) /*!< SCU_INTERRUPT SRCLR: LPACST (Bit 9) */ -#define SCU_INTERRUPT_SRCLR_LPACST_Msk \ - (0x200UL) /*!< SCU_INTERRUPT SRCLR: LPACST (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRCLR_LPACCLR_Pos \ - (10UL) /*!< SCU_INTERRUPT SRCLR: LPACCLR (Bit 10) */ -#define SCU_INTERRUPT_SRCLR_LPACCLR_Msk \ - (0x400UL) /*!< SCU_INTERRUPT SRCLR: LPACCLR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRCLR_LPACSET_Pos \ - (11UL) /*!< SCU_INTERRUPT SRCLR: LPACSET (Bit 11) */ -#define SCU_INTERRUPT_SRCLR_LPACSET_Msk \ - (0x800UL) /*!< SCU_INTERRUPT SRCLR: LPACSET (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRCLR_HINTST_Pos \ - (12UL) /*!< SCU_INTERRUPT SRCLR: HINTST (Bit 12) */ -#define SCU_INTERRUPT_SRCLR_HINTST_Msk \ - (0x1000UL) /*!< SCU_INTERRUPT SRCLR: HINTST (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRCLR_HINTCLR_Pos \ - (13UL) /*!< SCU_INTERRUPT SRCLR: HINTCLR (Bit 13) */ -#define SCU_INTERRUPT_SRCLR_HINTCLR_Msk \ - (0x2000UL) /*!< SCU_INTERRUPT SRCLR: HINTCLR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRCLR_HINTSET_Pos \ - (14UL) /*!< SCU_INTERRUPT SRCLR: HINTSET (Bit 14) */ -#define SCU_INTERRUPT_SRCLR_HINTSET_Msk \ - (0x4000UL) /*!< SCU_INTERRUPT SRCLR: HINTSET (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRCLR_HDCLR_Pos \ - (17UL) /*!< SCU_INTERRUPT SRCLR: HDCLR (Bit 17) */ -#define SCU_INTERRUPT_SRCLR_HDCLR_Msk \ - (0x20000UL) /*!< SCU_INTERRUPT SRCLR: HDCLR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRCLR_HDSET_Pos \ - (18UL) /*!< SCU_INTERRUPT SRCLR: HDSET (Bit 18) */ -#define SCU_INTERRUPT_SRCLR_HDSET_Msk \ - (0x40000UL) /*!< SCU_INTERRUPT SRCLR: HDSET (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRCLR_HDCR_Pos \ - (19UL) /*!< SCU_INTERRUPT SRCLR: HDCR (Bit 19) */ -#define SCU_INTERRUPT_SRCLR_HDCR_Msk \ - (0x80000UL) /*!< SCU_INTERRUPT SRCLR: HDCR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRCLR_OSCSICTRL_Pos \ - (21UL) /*!< SCU_INTERRUPT SRCLR: OSCSICTRL (Bit 21) */ -#define SCU_INTERRUPT_SRCLR_OSCSICTRL_Msk \ - (0x200000UL) /*!< SCU_INTERRUPT SRCLR: OSCSICTRL (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRCLR_OSCULCTRL_Pos \ - (23UL) /*!< SCU_INTERRUPT SRCLR: OSCULCTRL (Bit 23) */ -#define SCU_INTERRUPT_SRCLR_OSCULCTRL_Msk \ - (0x800000UL) /*!< SCU_INTERRUPT SRCLR: OSCULCTRL (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRCLR_RTC_CTR_Pos \ - (24UL) /*!< SCU_INTERRUPT SRCLR: RTC_CTR (Bit 24) */ -#define SCU_INTERRUPT_SRCLR_RTC_CTR_Msk \ - (0x1000000UL) /*!< SCU_INTERRUPT SRCLR: RTC_CTR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRCLR_RTC_ATIM0_Pos \ - (25UL) /*!< SCU_INTERRUPT SRCLR: RTC_ATIM0 (Bit 25) */ -#define SCU_INTERRUPT_SRCLR_RTC_ATIM0_Msk \ - (0x2000000UL) /*!< SCU_INTERRUPT SRCLR: RTC_ATIM0 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRCLR_RTC_ATIM1_Pos \ - (26UL) /*!< SCU_INTERRUPT SRCLR: RTC_ATIM1 (Bit 26) */ -#define SCU_INTERRUPT_SRCLR_RTC_ATIM1_Msk \ - (0x4000000UL) /*!< SCU_INTERRUPT SRCLR: RTC_ATIM1 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRCLR_RTC_TIM0_Pos \ - (27UL) /*!< SCU_INTERRUPT SRCLR: RTC_TIM0 (Bit 27) */ -#define SCU_INTERRUPT_SRCLR_RTC_TIM0_Msk \ - (0x8000000UL) /*!< SCU_INTERRUPT SRCLR: RTC_TIM0 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRCLR_RTC_TIM1_Pos \ - (28UL) /*!< SCU_INTERRUPT SRCLR: RTC_TIM1 (Bit 28) */ -#define SCU_INTERRUPT_SRCLR_RTC_TIM1_Msk \ - (0x10000000UL) /*!< SCU_INTERRUPT SRCLR: RTC_TIM1 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRCLR_RMX_Pos \ - (29UL) /*!< SCU_INTERRUPT SRCLR: RMX (Bit 29) */ -#define SCU_INTERRUPT_SRCLR_RMX_Msk \ - (0x20000000UL) /*!< SCU_INTERRUPT SRCLR: RMX (Bitfield-Mask: 0x01) */ - -/* ----------------------------- SCU_INTERRUPT_SRSET ---------------------------- */ -#define SCU_INTERRUPT_SRSET_PRWARN_Pos \ - (0UL) /*!< SCU_INTERRUPT SRSET: PRWARN (Bit 0) */ -#define SCU_INTERRUPT_SRSET_PRWARN_Msk \ - (0x1UL) /*!< SCU_INTERRUPT SRSET: PRWARN (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSET_PI_Pos \ - (1UL) /*!< SCU_INTERRUPT SRSET: PI (Bit 1) */ -#define SCU_INTERRUPT_SRSET_PI_Msk \ - (0x2UL) /*!< SCU_INTERRUPT SRSET: PI (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSET_AI_Pos \ - (2UL) /*!< SCU_INTERRUPT SRSET: AI (Bit 2) */ -#define SCU_INTERRUPT_SRSET_AI_Msk \ - (0x4UL) /*!< SCU_INTERRUPT SRSET: AI (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSET_DLROVR_Pos \ - (3UL) /*!< SCU_INTERRUPT SRSET: DLROVR (Bit 3) */ -#define SCU_INTERRUPT_SRSET_DLROVR_Msk \ - (0x8UL) /*!< SCU_INTERRUPT SRSET: DLROVR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSET_LPACCR_Pos \ - (6UL) /*!< SCU_INTERRUPT SRSET: LPACCR (Bit 6) */ -#define SCU_INTERRUPT_SRSET_LPACCR_Msk \ - (0x40UL) /*!< SCU_INTERRUPT SRSET: LPACCR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSET_LPACTH0_Pos \ - (7UL) /*!< SCU_INTERRUPT SRSET: LPACTH0 (Bit 7) */ -#define SCU_INTERRUPT_SRSET_LPACTH0_Msk \ - (0x80UL) /*!< SCU_INTERRUPT SRSET: LPACTH0 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSET_LPACTH1_Pos \ - (8UL) /*!< SCU_INTERRUPT SRSET: LPACTH1 (Bit 8) */ -#define SCU_INTERRUPT_SRSET_LPACTH1_Msk \ - (0x100UL) /*!< SCU_INTERRUPT SRSET: LPACTH1 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSET_LPACST_Pos \ - (9UL) /*!< SCU_INTERRUPT SRSET: LPACST (Bit 9) */ -#define SCU_INTERRUPT_SRSET_LPACST_Msk \ - (0x200UL) /*!< SCU_INTERRUPT SRSET: LPACST (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSET_LPACCLR_Pos \ - (10UL) /*!< SCU_INTERRUPT SRSET: LPACCLR (Bit 10) */ -#define SCU_INTERRUPT_SRSET_LPACCLR_Msk \ - (0x400UL) /*!< SCU_INTERRUPT SRSET: LPACCLR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSET_LPACSET_Pos \ - (11UL) /*!< SCU_INTERRUPT SRSET: LPACSET (Bit 11) */ -#define SCU_INTERRUPT_SRSET_LPACSET_Msk \ - (0x800UL) /*!< SCU_INTERRUPT SRSET: LPACSET (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSET_HINTST_Pos \ - (12UL) /*!< SCU_INTERRUPT SRSET: HINTST (Bit 12) */ -#define SCU_INTERRUPT_SRSET_HINTST_Msk \ - (0x1000UL) /*!< SCU_INTERRUPT SRSET: HINTST (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSET_HINTCLR_Pos \ - (13UL) /*!< SCU_INTERRUPT SRSET: HINTCLR (Bit 13) */ -#define SCU_INTERRUPT_SRSET_HINTCLR_Msk \ - (0x2000UL) /*!< SCU_INTERRUPT SRSET: HINTCLR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSET_HINTSET_Pos \ - (14UL) /*!< SCU_INTERRUPT SRSET: HINTSET (Bit 14) */ -#define SCU_INTERRUPT_SRSET_HINTSET_Msk \ - (0x4000UL) /*!< SCU_INTERRUPT SRSET: HINTSET (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSET_HDCRCLR_Pos \ - (17UL) /*!< SCU_INTERRUPT SRSET: HDCRCLR (Bit 17) */ -#define SCU_INTERRUPT_SRSET_HDCRCLR_Msk \ - (0x20000UL) /*!< SCU_INTERRUPT SRSET: HDCRCLR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSET_HDCRSET_Pos \ - (18UL) /*!< SCU_INTERRUPT SRSET: HDCRSET (Bit 18) */ -#define SCU_INTERRUPT_SRSET_HDCRSET_Msk \ - (0x40000UL) /*!< SCU_INTERRUPT SRSET: HDCRSET (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSET_HDCR_Pos \ - (19UL) /*!< SCU_INTERRUPT SRSET: HDCR (Bit 19) */ -#define SCU_INTERRUPT_SRSET_HDCR_Msk \ - (0x80000UL) /*!< SCU_INTERRUPT SRSET: HDCR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSET_OSCSICTRL_Pos \ - (21UL) /*!< SCU_INTERRUPT SRSET: OSCSICTRL (Bit 21) */ -#define SCU_INTERRUPT_SRSET_OSCSICTRL_Msk \ - (0x200000UL) /*!< SCU_INTERRUPT SRSET: OSCSICTRL (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSET_OSCULCTRL_Pos \ - (23UL) /*!< SCU_INTERRUPT SRSET: OSCULCTRL (Bit 23) */ -#define SCU_INTERRUPT_SRSET_OSCULCTRL_Msk \ - (0x800000UL) /*!< SCU_INTERRUPT SRSET: OSCULCTRL (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSET_RTC_CTR_Pos \ - (24UL) /*!< SCU_INTERRUPT SRSET: RTC_CTR (Bit 24) */ -#define SCU_INTERRUPT_SRSET_RTC_CTR_Msk \ - (0x1000000UL) /*!< SCU_INTERRUPT SRSET: RTC_CTR (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSET_RTC_ATIM0_Pos \ - (25UL) /*!< SCU_INTERRUPT SRSET: RTC_ATIM0 (Bit 25) */ -#define SCU_INTERRUPT_SRSET_RTC_ATIM0_Msk \ - (0x2000000UL) /*!< SCU_INTERRUPT SRSET: RTC_ATIM0 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSET_RTC_ATIM1_Pos \ - (26UL) /*!< SCU_INTERRUPT SRSET: RTC_ATIM1 (Bit 26) */ -#define SCU_INTERRUPT_SRSET_RTC_ATIM1_Msk \ - (0x4000000UL) /*!< SCU_INTERRUPT SRSET: RTC_ATIM1 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSET_RTC_TIM0_Pos \ - (27UL) /*!< SCU_INTERRUPT SRSET: RTC_TIM0 (Bit 27) */ -#define SCU_INTERRUPT_SRSET_RTC_TIM0_Msk \ - (0x8000000UL) /*!< SCU_INTERRUPT SRSET: RTC_TIM0 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSET_RTC_TIM1_Pos \ - (28UL) /*!< SCU_INTERRUPT SRSET: RTC_TIM1 (Bit 28) */ -#define SCU_INTERRUPT_SRSET_RTC_TIM1_Msk \ - (0x10000000UL) /*!< SCU_INTERRUPT SRSET: RTC_TIM1 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_SRSET_RMX_Pos \ - (29UL) /*!< SCU_INTERRUPT SRSET: RMX (Bit 29) */ -#define SCU_INTERRUPT_SRSET_RMX_Msk \ - (0x20000000UL) /*!< SCU_INTERRUPT SRSET: RMX (Bitfield-Mask: 0x01) */ - -/* --------------------------- SCU_INTERRUPT_NMIREQEN --------------------------- */ -#define SCU_INTERRUPT_NMIREQEN_PRWARN_Pos \ - (0UL) /*!< SCU_INTERRUPT NMIREQEN: PRWARN (Bit 0) */ -#define SCU_INTERRUPT_NMIREQEN_PRWARN_Msk \ - (0x1UL) /*!< SCU_INTERRUPT NMIREQEN: PRWARN (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_NMIREQEN_PI_Pos \ - (1UL) /*!< SCU_INTERRUPT NMIREQEN: PI (Bit 1) */ -#define SCU_INTERRUPT_NMIREQEN_PI_Msk \ - (0x2UL) /*!< SCU_INTERRUPT NMIREQEN: PI (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_NMIREQEN_AI_Pos \ - (2UL) /*!< SCU_INTERRUPT NMIREQEN: AI (Bit 2) */ -#define SCU_INTERRUPT_NMIREQEN_AI_Msk \ - (0x4UL) /*!< SCU_INTERRUPT NMIREQEN: AI (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_NMIREQEN_ERU00_Pos \ - (16UL) /*!< SCU_INTERRUPT NMIREQEN: ERU00 (Bit 16) */ -#define SCU_INTERRUPT_NMIREQEN_ERU00_Msk \ - (0x10000UL) /*!< SCU_INTERRUPT NMIREQEN: ERU00 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_NMIREQEN_ERU01_Pos \ - (17UL) /*!< SCU_INTERRUPT NMIREQEN: ERU01 (Bit 17) */ -#define SCU_INTERRUPT_NMIREQEN_ERU01_Msk \ - (0x20000UL) /*!< SCU_INTERRUPT NMIREQEN: ERU01 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_NMIREQEN_ERU02_Pos \ - (18UL) /*!< SCU_INTERRUPT NMIREQEN: ERU02 (Bit 18) */ -#define SCU_INTERRUPT_NMIREQEN_ERU02_Msk \ - (0x40000UL) /*!< SCU_INTERRUPT NMIREQEN: ERU02 (Bitfield-Mask: 0x01) */ -#define SCU_INTERRUPT_NMIREQEN_ERU03_Pos \ - (19UL) /*!< SCU_INTERRUPT NMIREQEN: ERU03 (Bit 19) */ -#define SCU_INTERRUPT_NMIREQEN_ERU03_Msk \ - (0x80000UL) /*!< SCU_INTERRUPT NMIREQEN: ERU03 (Bitfield-Mask: 0x01) */ - -/* ================================================================================ */ -/* ================ struct 'SCU_PARITY' Position & Mask ================ */ -/* ================================================================================ */ - -/* ------------------------------- SCU_PARITY_PEEN ------------------------------ */ -#define SCU_PARITY_PEEN_PEENPS_Pos \ - (0UL) /*!< SCU_PARITY PEEN: PEENPS (Bit 0) */ -#define SCU_PARITY_PEEN_PEENPS_Msk \ - (0x1UL) /*!< SCU_PARITY PEEN: PEENPS (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PEEN_PEENDS1_Pos \ - (1UL) /*!< SCU_PARITY PEEN: PEENDS1 (Bit 1) */ -#define SCU_PARITY_PEEN_PEENDS1_Msk \ - (0x2UL) /*!< SCU_PARITY PEEN: PEENDS1 (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PEEN_PEENDS2_Pos \ - (2UL) /*!< SCU_PARITY PEEN: PEENDS2 (Bit 2) */ -#define SCU_PARITY_PEEN_PEENDS2_Msk \ - (0x4UL) /*!< SCU_PARITY PEEN: PEENDS2 (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PEEN_PEENU0_Pos \ - (8UL) /*!< SCU_PARITY PEEN: PEENU0 (Bit 8) */ -#define SCU_PARITY_PEEN_PEENU0_Msk \ - (0x100UL) /*!< SCU_PARITY PEEN: PEENU0 (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PEEN_PEENU1_Pos \ - (9UL) /*!< SCU_PARITY PEEN: PEENU1 (Bit 9) */ -#define SCU_PARITY_PEEN_PEENU1_Msk \ - (0x200UL) /*!< SCU_PARITY PEEN: PEENU1 (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PEEN_PEENMC_Pos \ - (12UL) /*!< SCU_PARITY PEEN: PEENMC (Bit 12) */ -#define SCU_PARITY_PEEN_PEENMC_Msk \ - (0x1000UL) /*!< SCU_PARITY PEEN: PEENMC (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PEEN_PEENPPRF_Pos \ - (13UL) /*!< SCU_PARITY PEEN: PEENPPRF (Bit 13) */ -#define SCU_PARITY_PEEN_PEENPPRF_Msk \ - (0x2000UL) /*!< SCU_PARITY PEEN: PEENPPRF (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PEEN_PEENUSB_Pos \ - (16UL) /*!< SCU_PARITY PEEN: PEENUSB (Bit 16) */ -#define SCU_PARITY_PEEN_PEENUSB_Msk \ - (0x10000UL) /*!< SCU_PARITY PEEN: PEENUSB (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PEEN_PEENETH0TX_Pos \ - (17UL) /*!< SCU_PARITY PEEN: PEENETH0TX (Bit 17) */ -#define SCU_PARITY_PEEN_PEENETH0TX_Msk \ - (0x20000UL) /*!< SCU_PARITY PEEN: PEENETH0TX (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PEEN_PEENETH0RX_Pos \ - (18UL) /*!< SCU_PARITY PEEN: PEENETH0RX (Bit 18) */ -#define SCU_PARITY_PEEN_PEENETH0RX_Msk \ - (0x40000UL) /*!< SCU_PARITY PEEN: PEENETH0RX (Bitfield-Mask: 0x01) */ - -/* ----------------------------- SCU_PARITY_MCHKCON ----------------------------- */ -#define SCU_PARITY_MCHKCON_SELPS_Pos \ - (0UL) /*!< SCU_PARITY MCHKCON: SELPS (Bit 0) */ -#define SCU_PARITY_MCHKCON_SELPS_Msk \ - (0x1UL) /*!< SCU_PARITY MCHKCON: SELPS (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_MCHKCON_SELDS1_Pos \ - (1UL) /*!< SCU_PARITY MCHKCON: SELDS1 (Bit 1) */ -#define SCU_PARITY_MCHKCON_SELDS1_Msk \ - (0x2UL) /*!< SCU_PARITY MCHKCON: SELDS1 (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_MCHKCON_SELDS2_Pos \ - (2UL) /*!< SCU_PARITY MCHKCON: SELDS2 (Bit 2) */ -#define SCU_PARITY_MCHKCON_SELDS2_Msk \ - (0x4UL) /*!< SCU_PARITY MCHKCON: SELDS2 (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_MCHKCON_USIC0DRA_Pos \ - (8UL) /*!< SCU_PARITY MCHKCON: USIC0DRA (Bit 8) */ -#define SCU_PARITY_MCHKCON_USIC0DRA_Msk \ - (0x100UL) /*!< SCU_PARITY MCHKCON: USIC0DRA (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_MCHKCON_USIC1DRA_Pos \ - (9UL) /*!< SCU_PARITY MCHKCON: USIC1DRA (Bit 9) */ -#define SCU_PARITY_MCHKCON_USIC1DRA_Msk \ - (0x200UL) /*!< SCU_PARITY MCHKCON: USIC1DRA (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_MCHKCON_MCANDRA_Pos \ - (12UL) /*!< SCU_PARITY MCHKCON: MCANDRA (Bit 12) */ -#define SCU_PARITY_MCHKCON_MCANDRA_Msk \ - (0x1000UL) /*!< SCU_PARITY MCHKCON: MCANDRA (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_MCHKCON_PPRFDRA_Pos \ - (13UL) /*!< SCU_PARITY MCHKCON: PPRFDRA (Bit 13) */ -#define SCU_PARITY_MCHKCON_PPRFDRA_Msk \ - (0x2000UL) /*!< SCU_PARITY MCHKCON: PPRFDRA (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_MCHKCON_SELUSB_Pos \ - (16UL) /*!< SCU_PARITY MCHKCON: SELUSB (Bit 16) */ -#define SCU_PARITY_MCHKCON_SELUSB_Msk \ - (0x10000UL) /*!< SCU_PARITY MCHKCON: SELUSB (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_MCHKCON_SELETH0TX_Pos \ - (17UL) /*!< SCU_PARITY MCHKCON: SELETH0TX (Bit 17) */ -#define SCU_PARITY_MCHKCON_SELETH0TX_Msk \ - (0x20000UL) /*!< SCU_PARITY MCHKCON: SELETH0TX (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_MCHKCON_SELETH0RX_Pos \ - (18UL) /*!< SCU_PARITY MCHKCON: SELETH0RX (Bit 18) */ -#define SCU_PARITY_MCHKCON_SELETH0RX_Msk \ - (0x40000UL) /*!< SCU_PARITY MCHKCON: SELETH0RX (Bitfield-Mask: 0x01) */ - -/* ------------------------------- SCU_PARITY_PETE ------------------------------ */ -#define SCU_PARITY_PETE_PETEPS_Pos \ - (0UL) /*!< SCU_PARITY PETE: PETEPS (Bit 0) */ -#define SCU_PARITY_PETE_PETEPS_Msk \ - (0x1UL) /*!< SCU_PARITY PETE: PETEPS (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PETE_PETEDS1_Pos \ - (1UL) /*!< SCU_PARITY PETE: PETEDS1 (Bit 1) */ -#define SCU_PARITY_PETE_PETEDS1_Msk \ - (0x2UL) /*!< SCU_PARITY PETE: PETEDS1 (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PETE_PETEDS2_Pos \ - (2UL) /*!< SCU_PARITY PETE: PETEDS2 (Bit 2) */ -#define SCU_PARITY_PETE_PETEDS2_Msk \ - (0x4UL) /*!< SCU_PARITY PETE: PETEDS2 (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PETE_PETEU0_Pos \ - (8UL) /*!< SCU_PARITY PETE: PETEU0 (Bit 8) */ -#define SCU_PARITY_PETE_PETEU0_Msk \ - (0x100UL) /*!< SCU_PARITY PETE: PETEU0 (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PETE_PETEU1_Pos \ - (9UL) /*!< SCU_PARITY PETE: PETEU1 (Bit 9) */ -#define SCU_PARITY_PETE_PETEU1_Msk \ - (0x200UL) /*!< SCU_PARITY PETE: PETEU1 (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PETE_PETEMC_Pos \ - (12UL) /*!< SCU_PARITY PETE: PETEMC (Bit 12) */ -#define SCU_PARITY_PETE_PETEMC_Msk \ - (0x1000UL) /*!< SCU_PARITY PETE: PETEMC (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PETE_PETEPPRF_Pos \ - (13UL) /*!< SCU_PARITY PETE: PETEPPRF (Bit 13) */ -#define SCU_PARITY_PETE_PETEPPRF_Msk \ - (0x2000UL) /*!< SCU_PARITY PETE: PETEPPRF (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PETE_PETEUSB_Pos \ - (16UL) /*!< SCU_PARITY PETE: PETEUSB (Bit 16) */ -#define SCU_PARITY_PETE_PETEUSB_Msk \ - (0x10000UL) /*!< SCU_PARITY PETE: PETEUSB (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PETE_PETEETH0TX_Pos \ - (17UL) /*!< SCU_PARITY PETE: PETEETH0TX (Bit 17) */ -#define SCU_PARITY_PETE_PETEETH0TX_Msk \ - (0x20000UL) /*!< SCU_PARITY PETE: PETEETH0TX (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PETE_PETEETH0RX_Pos \ - (18UL) /*!< SCU_PARITY PETE: PETEETH0RX (Bit 18) */ -#define SCU_PARITY_PETE_PETEETH0RX_Msk \ - (0x40000UL) /*!< SCU_PARITY PETE: PETEETH0RX (Bitfield-Mask: 0x01) */ - -/* ----------------------------- SCU_PARITY_PERSTEN ----------------------------- */ -#define SCU_PARITY_PERSTEN_RSEN_Pos \ - (0UL) /*!< SCU_PARITY PERSTEN: RSEN (Bit 0) */ -#define SCU_PARITY_PERSTEN_RSEN_Msk \ - (0x1UL) /*!< SCU_PARITY PERSTEN: RSEN (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_PARITY_PEFLAG ----------------------------- */ -#define SCU_PARITY_PEFLAG_PEFPS_Pos \ - (0UL) /*!< SCU_PARITY PEFLAG: PEFPS (Bit 0) */ -#define SCU_PARITY_PEFLAG_PEFPS_Msk \ - (0x1UL) /*!< SCU_PARITY PEFLAG: PEFPS (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PEFLAG_PEFDS1_Pos \ - (1UL) /*!< SCU_PARITY PEFLAG: PEFDS1 (Bit 1) */ -#define SCU_PARITY_PEFLAG_PEFDS1_Msk \ - (0x2UL) /*!< SCU_PARITY PEFLAG: PEFDS1 (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PEFLAG_PEFDS2_Pos \ - (2UL) /*!< SCU_PARITY PEFLAG: PEFDS2 (Bit 2) */ -#define SCU_PARITY_PEFLAG_PEFDS2_Msk \ - (0x4UL) /*!< SCU_PARITY PEFLAG: PEFDS2 (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PEFLAG_PEFU0_Pos \ - (8UL) /*!< SCU_PARITY PEFLAG: PEFU0 (Bit 8) */ -#define SCU_PARITY_PEFLAG_PEFU0_Msk \ - (0x100UL) /*!< SCU_PARITY PEFLAG: PEFU0 (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PEFLAG_PEFU1_Pos \ - (9UL) /*!< SCU_PARITY PEFLAG: PEFU1 (Bit 9) */ -#define SCU_PARITY_PEFLAG_PEFU1_Msk \ - (0x200UL) /*!< SCU_PARITY PEFLAG: PEFU1 (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PEFLAG_PEFMC_Pos \ - (12UL) /*!< SCU_PARITY PEFLAG: PEFMC (Bit 12) */ -#define SCU_PARITY_PEFLAG_PEFMC_Msk \ - (0x1000UL) /*!< SCU_PARITY PEFLAG: PEFMC (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PEFLAG_PEFPPRF_Pos \ - (13UL) /*!< SCU_PARITY PEFLAG: PEFPPRF (Bit 13) */ -#define SCU_PARITY_PEFLAG_PEFPPRF_Msk \ - (0x2000UL) /*!< SCU_PARITY PEFLAG: PEFPPRF (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PEFLAG_PEUSB_Pos \ - (16UL) /*!< SCU_PARITY PEFLAG: PEUSB (Bit 16) */ -#define SCU_PARITY_PEFLAG_PEUSB_Msk \ - (0x10000UL) /*!< SCU_PARITY PEFLAG: PEUSB (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PEFLAG_PEETH0TX_Pos \ - (17UL) /*!< SCU_PARITY PEFLAG: PEETH0TX (Bit 17) */ -#define SCU_PARITY_PEFLAG_PEETH0TX_Msk \ - (0x20000UL) /*!< SCU_PARITY PEFLAG: PEETH0TX (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PEFLAG_PEETH0RX_Pos \ - (18UL) /*!< SCU_PARITY PEFLAG: PEETH0RX (Bit 18) */ -#define SCU_PARITY_PEFLAG_PEETH0RX_Msk \ - (0x40000UL) /*!< SCU_PARITY PEFLAG: PEETH0RX (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_PARITY_PMTPR ------------------------------ */ -#define SCU_PARITY_PMTPR_PWR_Pos \ - (0UL) /*!< SCU_PARITY PMTPR: PWR (Bit 0) */ -#define SCU_PARITY_PMTPR_PWR_Msk \ - (0xffUL) /*!< SCU_PARITY PMTPR: PWR (Bitfield-Mask: 0xff) */ -#define SCU_PARITY_PMTPR_PRD_Pos \ - (8UL) /*!< SCU_PARITY PMTPR: PRD (Bit 8) */ -#define SCU_PARITY_PMTPR_PRD_Msk \ - (0xff00UL) /*!< SCU_PARITY PMTPR: PRD (Bitfield-Mask: 0xff) */ - -/* ------------------------------ SCU_PARITY_PMTSR ------------------------------ */ -#define SCU_PARITY_PMTSR_MTENPS_Pos \ - (0UL) /*!< SCU_PARITY PMTSR: MTENPS (Bit 0) */ -#define SCU_PARITY_PMTSR_MTENPS_Msk \ - (0x1UL) /*!< SCU_PARITY PMTSR: MTENPS (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PMTSR_MTENDS1_Pos \ - (1UL) /*!< SCU_PARITY PMTSR: MTENDS1 (Bit 1) */ -#define SCU_PARITY_PMTSR_MTENDS1_Msk \ - (0x2UL) /*!< SCU_PARITY PMTSR: MTENDS1 (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PMTSR_MTENDS2_Pos \ - (2UL) /*!< SCU_PARITY PMTSR: MTENDS2 (Bit 2) */ -#define SCU_PARITY_PMTSR_MTENDS2_Msk \ - (0x4UL) /*!< SCU_PARITY PMTSR: MTENDS2 (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PMTSR_MTEU0_Pos \ - (8UL) /*!< SCU_PARITY PMTSR: MTEU0 (Bit 8) */ -#define SCU_PARITY_PMTSR_MTEU0_Msk \ - (0x100UL) /*!< SCU_PARITY PMTSR: MTEU0 (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PMTSR_MTEU1_Pos \ - (9UL) /*!< SCU_PARITY PMTSR: MTEU1 (Bit 9) */ -#define SCU_PARITY_PMTSR_MTEU1_Msk \ - (0x200UL) /*!< SCU_PARITY PMTSR: MTEU1 (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PMTSR_MTEMC_Pos \ - (12UL) /*!< SCU_PARITY PMTSR: MTEMC (Bit 12) */ -#define SCU_PARITY_PMTSR_MTEMC_Msk \ - (0x1000UL) /*!< SCU_PARITY PMTSR: MTEMC (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PMTSR_MTEPPRF_Pos \ - (13UL) /*!< SCU_PARITY PMTSR: MTEPPRF (Bit 13) */ -#define SCU_PARITY_PMTSR_MTEPPRF_Msk \ - (0x2000UL) /*!< SCU_PARITY PMTSR: MTEPPRF (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PMTSR_MTUSB_Pos \ - (16UL) /*!< SCU_PARITY PMTSR: MTUSB (Bit 16) */ -#define SCU_PARITY_PMTSR_MTUSB_Msk \ - (0x10000UL) /*!< SCU_PARITY PMTSR: MTUSB (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PMTSR_MTETH0TX_Pos \ - (17UL) /*!< SCU_PARITY PMTSR: MTETH0TX (Bit 17) */ -#define SCU_PARITY_PMTSR_MTETH0TX_Msk \ - (0x20000UL) /*!< SCU_PARITY PMTSR: MTETH0TX (Bitfield-Mask: 0x01) */ -#define SCU_PARITY_PMTSR_MTETH0RX_Pos \ - (18UL) /*!< SCU_PARITY PMTSR: MTETH0RX (Bit 18) */ -#define SCU_PARITY_PMTSR_MTETH0RX_Msk \ - (0x40000UL) /*!< SCU_PARITY PMTSR: MTETH0RX (Bitfield-Mask: 0x01) */ - -/* ================================================================================ */ -/* ================ struct 'SCU_TRAP' Position & Mask ================ */ -/* ================================================================================ */ - -/* ------------------------------ SCU_TRAP_TRAPSTAT ----------------------------- */ -#define SCU_TRAP_TRAPSTAT_SOSCWDGT_Pos \ - (0UL) /*!< SCU_TRAP TRAPSTAT: SOSCWDGT (Bit 0) */ -#define SCU_TRAP_TRAPSTAT_SOSCWDGT_Msk \ - (0x1UL) /*!< SCU_TRAP TRAPSTAT: SOSCWDGT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPSTAT_SVCOLCKT_Pos \ - (2UL) /*!< SCU_TRAP TRAPSTAT: SVCOLCKT (Bit 2) */ -#define SCU_TRAP_TRAPSTAT_SVCOLCKT_Msk \ - (0x4UL) /*!< SCU_TRAP TRAPSTAT: SVCOLCKT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPSTAT_UVCOLCKT_Pos \ - (3UL) /*!< SCU_TRAP TRAPSTAT: UVCOLCKT (Bit 3) */ -#define SCU_TRAP_TRAPSTAT_UVCOLCKT_Msk \ - (0x8UL) /*!< SCU_TRAP TRAPSTAT: UVCOLCKT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPSTAT_PET_Pos \ - (4UL) /*!< SCU_TRAP TRAPSTAT: PET (Bit 4) */ -#define SCU_TRAP_TRAPSTAT_PET_Msk \ - (0x10UL) /*!< SCU_TRAP TRAPSTAT: PET (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPSTAT_BRWNT_Pos \ - (5UL) /*!< SCU_TRAP TRAPSTAT: BRWNT (Bit 5) */ -#define SCU_TRAP_TRAPSTAT_BRWNT_Msk \ - (0x20UL) /*!< SCU_TRAP TRAPSTAT: BRWNT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPSTAT_ULPWDGT_Pos \ - (6UL) /*!< SCU_TRAP TRAPSTAT: ULPWDGT (Bit 6) */ -#define SCU_TRAP_TRAPSTAT_ULPWDGT_Msk \ - (0x40UL) /*!< SCU_TRAP TRAPSTAT: ULPWDGT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPSTAT_BWERR0T_Pos \ - (7UL) /*!< SCU_TRAP TRAPSTAT: BWERR0T (Bit 7) */ -#define SCU_TRAP_TRAPSTAT_BWERR0T_Msk \ - (0x80UL) /*!< SCU_TRAP TRAPSTAT: BWERR0T (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPSTAT_BWERR1T_Pos \ - (8UL) /*!< SCU_TRAP TRAPSTAT: BWERR1T (Bit 8) */ -#define SCU_TRAP_TRAPSTAT_BWERR1T_Msk \ - (0x100UL) /*!< SCU_TRAP TRAPSTAT: BWERR1T (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPSTAT_TEMPHIT_Pos \ - (12UL) /*!< SCU_TRAP TRAPSTAT: TEMPHIT (Bit 12) */ -#define SCU_TRAP_TRAPSTAT_TEMPHIT_Msk \ - (0x1000UL) /*!< SCU_TRAP TRAPSTAT: TEMPHIT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPSTAT_TEMPLOT_Pos \ - (13UL) /*!< SCU_TRAP TRAPSTAT: TEMPLOT (Bit 13) */ -#define SCU_TRAP_TRAPSTAT_TEMPLOT_Msk \ - (0x2000UL) /*!< SCU_TRAP TRAPSTAT: TEMPLOT (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_TRAP_TRAPRAW ------------------------------ */ -#define SCU_TRAP_TRAPRAW_SOSCWDGT_Pos \ - (0UL) /*!< SCU_TRAP TRAPRAW: SOSCWDGT (Bit 0) */ -#define SCU_TRAP_TRAPRAW_SOSCWDGT_Msk \ - (0x1UL) /*!< SCU_TRAP TRAPRAW: SOSCWDGT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPRAW_SVCOLCKT_Pos \ - (2UL) /*!< SCU_TRAP TRAPRAW: SVCOLCKT (Bit 2) */ -#define SCU_TRAP_TRAPRAW_SVCOLCKT_Msk \ - (0x4UL) /*!< SCU_TRAP TRAPRAW: SVCOLCKT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPRAW_UVCOLCKT_Pos \ - (3UL) /*!< SCU_TRAP TRAPRAW: UVCOLCKT (Bit 3) */ -#define SCU_TRAP_TRAPRAW_UVCOLCKT_Msk \ - (0x8UL) /*!< SCU_TRAP TRAPRAW: UVCOLCKT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPRAW_PET_Pos \ - (4UL) /*!< SCU_TRAP TRAPRAW: PET (Bit 4) */ -#define SCU_TRAP_TRAPRAW_PET_Msk \ - (0x10UL) /*!< SCU_TRAP TRAPRAW: PET (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPRAW_BRWNT_Pos \ - (5UL) /*!< SCU_TRAP TRAPRAW: BRWNT (Bit 5) */ -#define SCU_TRAP_TRAPRAW_BRWNT_Msk \ - (0x20UL) /*!< SCU_TRAP TRAPRAW: BRWNT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPRAW_ULPWDGT_Pos \ - (6UL) /*!< SCU_TRAP TRAPRAW: ULPWDGT (Bit 6) */ -#define SCU_TRAP_TRAPRAW_ULPWDGT_Msk \ - (0x40UL) /*!< SCU_TRAP TRAPRAW: ULPWDGT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPRAW_BWERR0T_Pos \ - (7UL) /*!< SCU_TRAP TRAPRAW: BWERR0T (Bit 7) */ -#define SCU_TRAP_TRAPRAW_BWERR0T_Msk \ - (0x80UL) /*!< SCU_TRAP TRAPRAW: BWERR0T (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPRAW_BWERR1T_Pos \ - (8UL) /*!< SCU_TRAP TRAPRAW: BWERR1T (Bit 8) */ -#define SCU_TRAP_TRAPRAW_BWERR1T_Msk \ - (0x100UL) /*!< SCU_TRAP TRAPRAW: BWERR1T (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPRAW_TEMPHIT_Pos \ - (12UL) /*!< SCU_TRAP TRAPRAW: TEMPHIT (Bit 12) */ -#define SCU_TRAP_TRAPRAW_TEMPHIT_Msk \ - (0x1000UL) /*!< SCU_TRAP TRAPRAW: TEMPHIT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPRAW_TEMPLOT_Pos \ - (13UL) /*!< SCU_TRAP TRAPRAW: TEMPLOT (Bit 13) */ -#define SCU_TRAP_TRAPRAW_TEMPLOT_Msk \ - (0x2000UL) /*!< SCU_TRAP TRAPRAW: TEMPLOT (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_TRAP_TRAPDIS ------------------------------ */ -#define SCU_TRAP_TRAPDIS_SOSCWDGT_Pos \ - (0UL) /*!< SCU_TRAP TRAPDIS: SOSCWDGT (Bit 0) */ -#define SCU_TRAP_TRAPDIS_SOSCWDGT_Msk \ - (0x1UL) /*!< SCU_TRAP TRAPDIS: SOSCWDGT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPDIS_SVCOLCKT_Pos \ - (2UL) /*!< SCU_TRAP TRAPDIS: SVCOLCKT (Bit 2) */ -#define SCU_TRAP_TRAPDIS_SVCOLCKT_Msk \ - (0x4UL) /*!< SCU_TRAP TRAPDIS: SVCOLCKT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPDIS_UVCOLCKT_Pos \ - (3UL) /*!< SCU_TRAP TRAPDIS: UVCOLCKT (Bit 3) */ -#define SCU_TRAP_TRAPDIS_UVCOLCKT_Msk \ - (0x8UL) /*!< SCU_TRAP TRAPDIS: UVCOLCKT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPDIS_PET_Pos \ - (4UL) /*!< SCU_TRAP TRAPDIS: PET (Bit 4) */ -#define SCU_TRAP_TRAPDIS_PET_Msk \ - (0x10UL) /*!< SCU_TRAP TRAPDIS: PET (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPDIS_BRWNT_Pos \ - (5UL) /*!< SCU_TRAP TRAPDIS: BRWNT (Bit 5) */ -#define SCU_TRAP_TRAPDIS_BRWNT_Msk \ - (0x20UL) /*!< SCU_TRAP TRAPDIS: BRWNT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPDIS_ULPWDGT_Pos \ - (6UL) /*!< SCU_TRAP TRAPDIS: ULPWDGT (Bit 6) */ -#define SCU_TRAP_TRAPDIS_ULPWDGT_Msk \ - (0x40UL) /*!< SCU_TRAP TRAPDIS: ULPWDGT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPDIS_BWERR0T_Pos \ - (7UL) /*!< SCU_TRAP TRAPDIS: BWERR0T (Bit 7) */ -#define SCU_TRAP_TRAPDIS_BWERR0T_Msk \ - (0x80UL) /*!< SCU_TRAP TRAPDIS: BWERR0T (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPDIS_BWERR1T_Pos \ - (8UL) /*!< SCU_TRAP TRAPDIS: BWERR1T (Bit 8) */ -#define SCU_TRAP_TRAPDIS_BWERR1T_Msk \ - (0x100UL) /*!< SCU_TRAP TRAPDIS: BWERR1T (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPDIS_TEMPHIT_Pos \ - (12UL) /*!< SCU_TRAP TRAPDIS: TEMPHIT (Bit 12) */ -#define SCU_TRAP_TRAPDIS_TEMPHIT_Msk \ - (0x1000UL) /*!< SCU_TRAP TRAPDIS: TEMPHIT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPDIS_TEMPLOT_Pos \ - (13UL) /*!< SCU_TRAP TRAPDIS: TEMPLOT (Bit 13) */ -#define SCU_TRAP_TRAPDIS_TEMPLOT_Msk \ - (0x2000UL) /*!< SCU_TRAP TRAPDIS: TEMPLOT (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_TRAP_TRAPCLR ------------------------------ */ -#define SCU_TRAP_TRAPCLR_SOSCWDGT_Pos \ - (0UL) /*!< SCU_TRAP TRAPCLR: SOSCWDGT (Bit 0) */ -#define SCU_TRAP_TRAPCLR_SOSCWDGT_Msk \ - (0x1UL) /*!< SCU_TRAP TRAPCLR: SOSCWDGT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPCLR_SVCOLCKT_Pos \ - (2UL) /*!< SCU_TRAP TRAPCLR: SVCOLCKT (Bit 2) */ -#define SCU_TRAP_TRAPCLR_SVCOLCKT_Msk \ - (0x4UL) /*!< SCU_TRAP TRAPCLR: SVCOLCKT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPCLR_UVCOLCKT_Pos \ - (3UL) /*!< SCU_TRAP TRAPCLR: UVCOLCKT (Bit 3) */ -#define SCU_TRAP_TRAPCLR_UVCOLCKT_Msk \ - (0x8UL) /*!< SCU_TRAP TRAPCLR: UVCOLCKT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPCLR_PET_Pos \ - (4UL) /*!< SCU_TRAP TRAPCLR: PET (Bit 4) */ -#define SCU_TRAP_TRAPCLR_PET_Msk \ - (0x10UL) /*!< SCU_TRAP TRAPCLR: PET (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPCLR_BRWNT_Pos \ - (5UL) /*!< SCU_TRAP TRAPCLR: BRWNT (Bit 5) */ -#define SCU_TRAP_TRAPCLR_BRWNT_Msk \ - (0x20UL) /*!< SCU_TRAP TRAPCLR: BRWNT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPCLR_ULPWDGT_Pos \ - (6UL) /*!< SCU_TRAP TRAPCLR: ULPWDGT (Bit 6) */ -#define SCU_TRAP_TRAPCLR_ULPWDGT_Msk \ - (0x40UL) /*!< SCU_TRAP TRAPCLR: ULPWDGT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPCLR_BWERR0T_Pos \ - (7UL) /*!< SCU_TRAP TRAPCLR: BWERR0T (Bit 7) */ -#define SCU_TRAP_TRAPCLR_BWERR0T_Msk \ - (0x80UL) /*!< SCU_TRAP TRAPCLR: BWERR0T (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPCLR_BWERR1T_Pos \ - (8UL) /*!< SCU_TRAP TRAPCLR: BWERR1T (Bit 8) */ -#define SCU_TRAP_TRAPCLR_BWERR1T_Msk \ - (0x100UL) /*!< SCU_TRAP TRAPCLR: BWERR1T (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPCLR_TEMPHIT_Pos \ - (12UL) /*!< SCU_TRAP TRAPCLR: TEMPHIT (Bit 12) */ -#define SCU_TRAP_TRAPCLR_TEMPHIT_Msk \ - (0x1000UL) /*!< SCU_TRAP TRAPCLR: TEMPHIT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPCLR_TEMPLOT_Pos \ - (13UL) /*!< SCU_TRAP TRAPCLR: TEMPLOT (Bit 13) */ -#define SCU_TRAP_TRAPCLR_TEMPLOT_Msk \ - (0x2000UL) /*!< SCU_TRAP TRAPCLR: TEMPLOT (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_TRAP_TRAPSET ------------------------------ */ -#define SCU_TRAP_TRAPSET_SOSCWDGT_Pos \ - (0UL) /*!< SCU_TRAP TRAPSET: SOSCWDGT (Bit 0) */ -#define SCU_TRAP_TRAPSET_SOSCWDGT_Msk \ - (0x1UL) /*!< SCU_TRAP TRAPSET: SOSCWDGT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPSET_SVCOLCKT_Pos \ - (2UL) /*!< SCU_TRAP TRAPSET: SVCOLCKT (Bit 2) */ -#define SCU_TRAP_TRAPSET_SVCOLCKT_Msk \ - (0x4UL) /*!< SCU_TRAP TRAPSET: SVCOLCKT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPSET_UVCOLCKT_Pos \ - (3UL) /*!< SCU_TRAP TRAPSET: UVCOLCKT (Bit 3) */ -#define SCU_TRAP_TRAPSET_UVCOLCKT_Msk \ - (0x8UL) /*!< SCU_TRAP TRAPSET: UVCOLCKT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPSET_PET_Pos \ - (4UL) /*!< SCU_TRAP TRAPSET: PET (Bit 4) */ -#define SCU_TRAP_TRAPSET_PET_Msk \ - (0x10UL) /*!< SCU_TRAP TRAPSET: PET (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPSET_BRWNT_Pos \ - (5UL) /*!< SCU_TRAP TRAPSET: BRWNT (Bit 5) */ -#define SCU_TRAP_TRAPSET_BRWNT_Msk \ - (0x20UL) /*!< SCU_TRAP TRAPSET: BRWNT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPSET_ULPWDT_Pos \ - (6UL) /*!< SCU_TRAP TRAPSET: ULPWDT (Bit 6) */ -#define SCU_TRAP_TRAPSET_ULPWDT_Msk \ - (0x40UL) /*!< SCU_TRAP TRAPSET: ULPWDT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPSET_BWERR0T_Pos \ - (7UL) /*!< SCU_TRAP TRAPSET: BWERR0T (Bit 7) */ -#define SCU_TRAP_TRAPSET_BWERR0T_Msk \ - (0x80UL) /*!< SCU_TRAP TRAPSET: BWERR0T (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPSET_BWERR1T_Pos \ - (8UL) /*!< SCU_TRAP TRAPSET: BWERR1T (Bit 8) */ -#define SCU_TRAP_TRAPSET_BWERR1T_Msk \ - (0x100UL) /*!< SCU_TRAP TRAPSET: BWERR1T (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPSET_TEMPHIT_Pos \ - (12UL) /*!< SCU_TRAP TRAPSET: TEMPHIT (Bit 12) */ -#define SCU_TRAP_TRAPSET_TEMPHIT_Msk \ - (0x1000UL) /*!< SCU_TRAP TRAPSET: TEMPHIT (Bitfield-Mask: 0x01) */ -#define SCU_TRAP_TRAPSET_TEMPLOT_Pos \ - (13UL) /*!< SCU_TRAP TRAPSET: TEMPLOT (Bit 13) */ -#define SCU_TRAP_TRAPSET_TEMPLOT_Msk \ - (0x2000UL) /*!< SCU_TRAP TRAPSET: TEMPLOT (Bitfield-Mask: 0x01) */ - -/* ================================================================================ */ -/* ================ struct 'SCU_HIBERNATE' Position & Mask ================ */ -/* ================================================================================ */ - -/* ---------------------------- SCU_HIBERNATE_HDSTAT ---------------------------- */ -#define SCU_HIBERNATE_HDSTAT_EPEV_Pos \ - (0UL) /*!< SCU_HIBERNATE HDSTAT: EPEV (Bit 0) */ -#define SCU_HIBERNATE_HDSTAT_EPEV_Msk \ - (0x1UL) /*!< SCU_HIBERNATE HDSTAT: EPEV (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDSTAT_ENEV_Pos \ - (1UL) /*!< SCU_HIBERNATE HDSTAT: ENEV (Bit 1) */ -#define SCU_HIBERNATE_HDSTAT_ENEV_Msk \ - (0x2UL) /*!< SCU_HIBERNATE HDSTAT: ENEV (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDSTAT_RTCEV_Pos \ - (2UL) /*!< SCU_HIBERNATE HDSTAT: RTCEV (Bit 2) */ -#define SCU_HIBERNATE_HDSTAT_RTCEV_Msk \ - (0x4UL) /*!< SCU_HIBERNATE HDSTAT: RTCEV (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDSTAT_ULPWDG_Pos \ - (3UL) /*!< SCU_HIBERNATE HDSTAT: ULPWDG (Bit 3) */ -#define SCU_HIBERNATE_HDSTAT_ULPWDG_Msk \ - (0x8UL) /*!< SCU_HIBERNATE HDSTAT: ULPWDG (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDSTAT_HIBNOUT_Pos \ - (4UL) /*!< SCU_HIBERNATE HDSTAT: HIBNOUT (Bit 4) */ -#define SCU_HIBERNATE_HDSTAT_HIBNOUT_Msk \ - (0x10UL) /*!< SCU_HIBERNATE HDSTAT: HIBNOUT (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDSTAT_VBATPEV_Pos \ - (8UL) /*!< SCU_HIBERNATE HDSTAT: VBATPEV (Bit 8) */ -#define SCU_HIBERNATE_HDSTAT_VBATPEV_Msk \ - (0x100UL) /*!< SCU_HIBERNATE HDSTAT: VBATPEV (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDSTAT_VBATNEV_Pos \ - (9UL) /*!< SCU_HIBERNATE HDSTAT: VBATNEV (Bit 9) */ -#define SCU_HIBERNATE_HDSTAT_VBATNEV_Msk \ - (0x200UL) /*!< SCU_HIBERNATE HDSTAT: VBATNEV (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDSTAT_AHIBIO0PEV_Pos \ - (10UL) /*!< SCU_HIBERNATE HDSTAT: AHIBIO0PEV (Bit 10) */ -#define SCU_HIBERNATE_HDSTAT_AHIBIO0PEV_Msk \ - (0x400UL) /*!< SCU_HIBERNATE HDSTAT: AHIBIO0PEV (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDSTAT_AHIBIO0NEV_Pos \ - (11UL) /*!< SCU_HIBERNATE HDSTAT: AHIBIO0NEV (Bit 11) */ -#define SCU_HIBERNATE_HDSTAT_AHIBIO0NEV_Msk \ - (0x800UL) /*!< SCU_HIBERNATE HDSTAT: AHIBIO0NEV (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDSTAT_AHIBIO1PEV_Pos \ - (12UL) /*!< SCU_HIBERNATE HDSTAT: AHIBIO1PEV (Bit 12) */ -#define SCU_HIBERNATE_HDSTAT_AHIBIO1PEV_Msk \ - (0x1000UL) /*!< SCU_HIBERNATE HDSTAT: AHIBIO1PEV (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDSTAT_AHIBIO1NEV_Pos \ - (13UL) /*!< SCU_HIBERNATE HDSTAT: AHIBIO1NEV (Bit 13) */ -#define SCU_HIBERNATE_HDSTAT_AHIBIO1NEV_Msk \ - (0x2000UL) /*!< SCU_HIBERNATE HDSTAT: AHIBIO1NEV (Bitfield-Mask: 0x01) */ - -/* ----------------------------- SCU_HIBERNATE_HDCLR ---------------------------- */ -#define SCU_HIBERNATE_HDCLR_EPEV_Pos \ - (0UL) /*!< SCU_HIBERNATE HDCLR: EPEV (Bit 0) */ -#define SCU_HIBERNATE_HDCLR_EPEV_Msk \ - (0x1UL) /*!< SCU_HIBERNATE HDCLR: EPEV (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDCLR_ENEV_Pos \ - (1UL) /*!< SCU_HIBERNATE HDCLR: ENEV (Bit 1) */ -#define SCU_HIBERNATE_HDCLR_ENEV_Msk \ - (0x2UL) /*!< SCU_HIBERNATE HDCLR: ENEV (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDCLR_RTCEV_Pos \ - (2UL) /*!< SCU_HIBERNATE HDCLR: RTCEV (Bit 2) */ -#define SCU_HIBERNATE_HDCLR_RTCEV_Msk \ - (0x4UL) /*!< SCU_HIBERNATE HDCLR: RTCEV (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDCLR_ULPWDG_Pos \ - (3UL) /*!< SCU_HIBERNATE HDCLR: ULPWDG (Bit 3) */ -#define SCU_HIBERNATE_HDCLR_ULPWDG_Msk \ - (0x8UL) /*!< SCU_HIBERNATE HDCLR: ULPWDG (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDCLR_VBATPEV_Pos \ - (8UL) /*!< SCU_HIBERNATE HDCLR: VBATPEV (Bit 8) */ -#define SCU_HIBERNATE_HDCLR_VBATPEV_Msk \ - (0x100UL) /*!< SCU_HIBERNATE HDCLR: VBATPEV (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDCLR_VBATNEV_Pos \ - (9UL) /*!< SCU_HIBERNATE HDCLR: VBATNEV (Bit 9) */ -#define SCU_HIBERNATE_HDCLR_VBATNEV_Msk \ - (0x200UL) /*!< SCU_HIBERNATE HDCLR: VBATNEV (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDCLR_AHIBIO0PEV_Pos \ - (10UL) /*!< SCU_HIBERNATE HDCLR: AHIBIO0PEV (Bit 10) */ -#define SCU_HIBERNATE_HDCLR_AHIBIO0PEV_Msk \ - (0x400UL) /*!< SCU_HIBERNATE HDCLR: AHIBIO0PEV (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDCLR_AHIBIO0NEV_Pos \ - (11UL) /*!< SCU_HIBERNATE HDCLR: AHIBIO0NEV (Bit 11) */ -#define SCU_HIBERNATE_HDCLR_AHIBIO0NEV_Msk \ - (0x800UL) /*!< SCU_HIBERNATE HDCLR: AHIBIO0NEV (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDCLR_AHIBIO1PEV_Pos \ - (12UL) /*!< SCU_HIBERNATE HDCLR: AHIBIO1PEV (Bit 12) */ -#define SCU_HIBERNATE_HDCLR_AHIBIO1PEV_Msk \ - (0x1000UL) /*!< SCU_HIBERNATE HDCLR: AHIBIO1PEV (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDCLR_AHIBIO1NEV_Pos \ - (13UL) /*!< SCU_HIBERNATE HDCLR: AHIBIO1NEV (Bit 13) */ -#define SCU_HIBERNATE_HDCLR_AHIBIO1NEV_Msk \ - (0x2000UL) /*!< SCU_HIBERNATE HDCLR: AHIBIO1NEV (Bitfield-Mask: 0x01) */ - -/* ----------------------------- SCU_HIBERNATE_HDSET ---------------------------- */ -#define SCU_HIBERNATE_HDSET_EPEV_Pos \ - (0UL) /*!< SCU_HIBERNATE HDSET: EPEV (Bit 0) */ -#define SCU_HIBERNATE_HDSET_EPEV_Msk \ - (0x1UL) /*!< SCU_HIBERNATE HDSET: EPEV (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDSET_ENEV_Pos \ - (1UL) /*!< SCU_HIBERNATE HDSET: ENEV (Bit 1) */ -#define SCU_HIBERNATE_HDSET_ENEV_Msk \ - (0x2UL) /*!< SCU_HIBERNATE HDSET: ENEV (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDSET_RTCEV_Pos \ - (2UL) /*!< SCU_HIBERNATE HDSET: RTCEV (Bit 2) */ -#define SCU_HIBERNATE_HDSET_RTCEV_Msk \ - (0x4UL) /*!< SCU_HIBERNATE HDSET: RTCEV (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDSET_ULPWDG_Pos \ - (3UL) /*!< SCU_HIBERNATE HDSET: ULPWDG (Bit 3) */ -#define SCU_HIBERNATE_HDSET_ULPWDG_Msk \ - (0x8UL) /*!< SCU_HIBERNATE HDSET: ULPWDG (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDSET_VBATPEV_Pos \ - (8UL) /*!< SCU_HIBERNATE HDSET: VBATPEV (Bit 8) */ -#define SCU_HIBERNATE_HDSET_VBATPEV_Msk \ - (0x100UL) /*!< SCU_HIBERNATE HDSET: VBATPEV (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDSET_VBATNEV_Pos \ - (9UL) /*!< SCU_HIBERNATE HDSET: VBATNEV (Bit 9) */ -#define SCU_HIBERNATE_HDSET_VBATNEV_Msk \ - (0x200UL) /*!< SCU_HIBERNATE HDSET: VBATNEV (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDSET_AHIBIO0PEV_Pos \ - (10UL) /*!< SCU_HIBERNATE HDSET: AHIBIO0PEV (Bit 10) */ -#define SCU_HIBERNATE_HDSET_AHIBIO0PEV_Msk \ - (0x400UL) /*!< SCU_HIBERNATE HDSET: AHIBIO0PEV (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDSET_AHIBIO0NEV_Pos \ - (11UL) /*!< SCU_HIBERNATE HDSET: AHIBIO0NEV (Bit 11) */ -#define SCU_HIBERNATE_HDSET_AHIBIO0NEV_Msk \ - (0x800UL) /*!< SCU_HIBERNATE HDSET: AHIBIO0NEV (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDSET_AHIBIO1PEV_Pos \ - (12UL) /*!< SCU_HIBERNATE HDSET: AHIBIO1PEV (Bit 12) */ -#define SCU_HIBERNATE_HDSET_AHIBIO1PEV_Msk \ - (0x1000UL) /*!< SCU_HIBERNATE HDSET: AHIBIO1PEV (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDSET_AHIBIO1NEV_Pos \ - (13UL) /*!< SCU_HIBERNATE HDSET: AHIBIO1NEV (Bit 13) */ -#define SCU_HIBERNATE_HDSET_AHIBIO1NEV_Msk \ - (0x2000UL) /*!< SCU_HIBERNATE HDSET: AHIBIO1NEV (Bitfield-Mask: 0x01) */ - -/* ----------------------------- SCU_HIBERNATE_HDCR ----------------------------- */ -#define SCU_HIBERNATE_HDCR_WKPEP_Pos \ - (0UL) /*!< SCU_HIBERNATE HDCR: WKPEP (Bit 0) */ -#define SCU_HIBERNATE_HDCR_WKPEP_Msk \ - (0x1UL) /*!< SCU_HIBERNATE HDCR: WKPEP (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDCR_WKPEN_Pos \ - (1UL) /*!< SCU_HIBERNATE HDCR: WKPEN (Bit 1) */ -#define SCU_HIBERNATE_HDCR_WKPEN_Msk \ - (0x2UL) /*!< SCU_HIBERNATE HDCR: WKPEN (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDCR_RTCE_Pos \ - (2UL) /*!< SCU_HIBERNATE HDCR: RTCE (Bit 2) */ -#define SCU_HIBERNATE_HDCR_RTCE_Msk \ - (0x4UL) /*!< SCU_HIBERNATE HDCR: RTCE (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDCR_ULPWDGEN_Pos \ - (3UL) /*!< SCU_HIBERNATE HDCR: ULPWDGEN (Bit 3) */ -#define SCU_HIBERNATE_HDCR_ULPWDGEN_Msk \ - (0x8UL) /*!< SCU_HIBERNATE HDCR: ULPWDGEN (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDCR_HIB_Pos \ - (4UL) /*!< SCU_HIBERNATE HDCR: HIB (Bit 4) */ -#define SCU_HIBERNATE_HDCR_HIB_Msk \ - (0x10UL) /*!< SCU_HIBERNATE HDCR: HIB (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDCR_XTALGPI1SEL_Pos \ - (5UL) /*!< SCU_HIBERNATE HDCR: XTALGPI1SEL (Bit 5) */ -#define SCU_HIBERNATE_HDCR_XTALGPI1SEL_Msk \ - (0x20UL) /*!< SCU_HIBERNATE HDCR: XTALGPI1SEL (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDCR_RCS_Pos \ - (6UL) /*!< SCU_HIBERNATE HDCR: RCS (Bit 6) */ -#define SCU_HIBERNATE_HDCR_RCS_Msk \ - (0x40UL) /*!< SCU_HIBERNATE HDCR: RCS (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDCR_STDBYSEL_Pos \ - (7UL) /*!< SCU_HIBERNATE HDCR: STDBYSEL (Bit 7) */ -#define SCU_HIBERNATE_HDCR_STDBYSEL_Msk \ - (0x80UL) /*!< SCU_HIBERNATE HDCR: STDBYSEL (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDCR_WKUPSEL_Pos \ - (8UL) /*!< SCU_HIBERNATE HDCR: WKUPSEL (Bit 8) */ -#define SCU_HIBERNATE_HDCR_WKUPSEL_Msk \ - (0x100UL) /*!< SCU_HIBERNATE HDCR: WKUPSEL (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDCR_GPI0SEL_Pos \ - (10UL) /*!< SCU_HIBERNATE HDCR: GPI0SEL (Bit 10) */ -#define SCU_HIBERNATE_HDCR_GPI0SEL_Msk \ - (0x400UL) /*!< SCU_HIBERNATE HDCR: GPI0SEL (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDCR_GPI1SEL_Pos \ - (11UL) /*!< SCU_HIBERNATE HDCR: GPI1SEL (Bit 11) */ -#define SCU_HIBERNATE_HDCR_GPI1SEL_Msk \ - (0x800UL) /*!< SCU_HIBERNATE HDCR: GPI1SEL (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDCR_HIBIO0POL_Pos \ - (12UL) /*!< SCU_HIBERNATE HDCR: HIBIO0POL (Bit 12) */ -#define SCU_HIBERNATE_HDCR_HIBIO0POL_Msk \ - (0x1000UL) /*!< SCU_HIBERNATE HDCR: HIBIO0POL (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDCR_HIBIO1POL_Pos \ - (13UL) /*!< SCU_HIBERNATE HDCR: HIBIO1POL (Bit 13) */ -#define SCU_HIBERNATE_HDCR_HIBIO1POL_Msk \ - (0x2000UL) /*!< SCU_HIBERNATE HDCR: HIBIO1POL (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDCR_ADIG0SEL_Pos \ - (14UL) /*!< SCU_HIBERNATE HDCR: ADIG0SEL (Bit 14) */ -#define SCU_HIBERNATE_HDCR_ADIG0SEL_Msk \ - (0x4000UL) /*!< SCU_HIBERNATE HDCR: ADIG0SEL (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDCR_ADIG1SEL_Pos \ - (15UL) /*!< SCU_HIBERNATE HDCR: ADIG1SEL (Bit 15) */ -#define SCU_HIBERNATE_HDCR_ADIG1SEL_Msk \ - (0x8000UL) /*!< SCU_HIBERNATE HDCR: ADIG1SEL (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDCR_HIBIO0SEL_Pos \ - (16UL) /*!< SCU_HIBERNATE HDCR: HIBIO0SEL (Bit 16) */ -#define SCU_HIBERNATE_HDCR_HIBIO0SEL_Msk \ - (0xf0000UL) /*!< SCU_HIBERNATE HDCR: HIBIO0SEL (Bitfield-Mask: 0x0f) */ -#define SCU_HIBERNATE_HDCR_HIBIO1SEL_Pos \ - (20UL) /*!< SCU_HIBERNATE HDCR: HIBIO1SEL (Bit 20) */ -#define SCU_HIBERNATE_HDCR_HIBIO1SEL_Msk \ - (0xf00000UL) /*!< SCU_HIBERNATE HDCR: HIBIO1SEL (Bitfield-Mask: 0x0f) */ -#define SCU_HIBERNATE_HDCR_VBATLO_Pos \ - (24UL) /*!< SCU_HIBERNATE HDCR: VBATLO (Bit 24) */ -#define SCU_HIBERNATE_HDCR_VBATLO_Msk \ - (0x1000000UL) /*!< SCU_HIBERNATE HDCR: VBATLO (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDCR_VBATHI_Pos \ - (25UL) /*!< SCU_HIBERNATE HDCR: VBATHI (Bit 25) */ -#define SCU_HIBERNATE_HDCR_VBATHI_Msk \ - (0x2000000UL) /*!< SCU_HIBERNATE HDCR: VBATHI (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDCR_AHIBIO0LO_Pos \ - (26UL) /*!< SCU_HIBERNATE HDCR: AHIBIO0LO (Bit 26) */ -#define SCU_HIBERNATE_HDCR_AHIBIO0LO_Msk \ - (0x4000000UL) /*!< SCU_HIBERNATE HDCR: AHIBIO0LO (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDCR_AHIBIO0HI_Pos \ - (27UL) /*!< SCU_HIBERNATE HDCR: AHIBIO0HI (Bit 27) */ -#define SCU_HIBERNATE_HDCR_AHIBIO0HI_Msk \ - (0x8000000UL) /*!< SCU_HIBERNATE HDCR: AHIBIO0HI (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDCR_AHIBIO1LO_Pos \ - (28UL) /*!< SCU_HIBERNATE HDCR: AHIBIO1LO (Bit 28) */ -#define SCU_HIBERNATE_HDCR_AHIBIO1LO_Msk \ - (0x10000000UL) /*!< SCU_HIBERNATE HDCR: AHIBIO1LO (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HDCR_AHIBIO1HI_Pos \ - (29UL) /*!< SCU_HIBERNATE HDCR: AHIBIO1HI (Bit 29) */ -#define SCU_HIBERNATE_HDCR_AHIBIO1HI_Msk \ - (0x20000000UL) /*!< SCU_HIBERNATE HDCR: AHIBIO1HI (Bitfield-Mask: 0x01) */ - -/* --------------------------- SCU_HIBERNATE_OSCSICTRL -------------------------- */ -#define SCU_HIBERNATE_OSCSICTRL_PWD_Pos \ - (0UL) /*!< SCU_HIBERNATE OSCSICTRL: PWD (Bit 0) */ -#define SCU_HIBERNATE_OSCSICTRL_PWD_Msk \ - (0x1UL) /*!< SCU_HIBERNATE OSCSICTRL: PWD (Bitfield-Mask: 0x01) */ - -/* --------------------------- SCU_HIBERNATE_OSCULSTAT -------------------------- */ -#define SCU_HIBERNATE_OSCULSTAT_X1D_Pos \ - (0UL) /*!< SCU_HIBERNATE OSCULSTAT: X1D (Bit 0) */ -#define SCU_HIBERNATE_OSCULSTAT_X1D_Msk \ - (0x1UL) /*!< SCU_HIBERNATE OSCULSTAT: X1D (Bitfield-Mask: 0x01) */ - -/* --------------------------- SCU_HIBERNATE_OSCULCTRL -------------------------- */ -#define SCU_HIBERNATE_OSCULCTRL_X1DEN_Pos \ - (0UL) /*!< SCU_HIBERNATE OSCULCTRL: X1DEN (Bit 0) */ -#define SCU_HIBERNATE_OSCULCTRL_X1DEN_Msk \ - (0x1UL) /*!< SCU_HIBERNATE OSCULCTRL: X1DEN (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_OSCULCTRL_MODE_Pos \ - (4UL) /*!< SCU_HIBERNATE OSCULCTRL: MODE (Bit 4) */ -#define SCU_HIBERNATE_OSCULCTRL_MODE_Msk \ - (0x30UL) /*!< SCU_HIBERNATE OSCULCTRL: MODE (Bitfield-Mask: 0x03) */ - -/* --------------------------- SCU_HIBERNATE_LPACCONF --------------------------- */ -#define SCU_HIBERNATE_LPACCONF_CMPEN_Pos \ - (0UL) /*!< SCU_HIBERNATE LPACCONF: CMPEN (Bit 0) */ -#define SCU_HIBERNATE_LPACCONF_CMPEN_Msk \ - (0x7UL) /*!< SCU_HIBERNATE LPACCONF: CMPEN (Bitfield-Mask: 0x07) */ -#define SCU_HIBERNATE_LPACCONF_TRIGSEL_Pos \ - (4UL) /*!< SCU_HIBERNATE LPACCONF: TRIGSEL (Bit 4) */ -#define SCU_HIBERNATE_LPACCONF_TRIGSEL_Msk \ - (0x70UL) /*!< SCU_HIBERNATE LPACCONF: TRIGSEL (Bitfield-Mask: 0x07) */ -#define SCU_HIBERNATE_LPACCONF_CONVDEL_Pos \ - (12UL) /*!< SCU_HIBERNATE LPACCONF: CONVDEL (Bit 12) */ -#define SCU_HIBERNATE_LPACCONF_CONVDEL_Msk \ - (0x1000UL) /*!< SCU_HIBERNATE LPACCONF: CONVDEL (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_LPACCONF_INTERVCNT_Pos \ - (16UL) /*!< SCU_HIBERNATE LPACCONF: INTERVCNT (Bit 16) */ -#define SCU_HIBERNATE_LPACCONF_INTERVCNT_Msk \ - (0xfff0000UL) /*!< SCU_HIBERNATE LPACCONF: INTERVCNT (Bitfield-Mask: 0xfff) */ -#define SCU_HIBERNATE_LPACCONF_SETTLECNT_Pos \ - (28UL) /*!< SCU_HIBERNATE LPACCONF: SETTLECNT (Bit 28) */ -#define SCU_HIBERNATE_LPACCONF_SETTLECNT_Msk \ - (0xf0000000UL) /*!< SCU_HIBERNATE LPACCONF: SETTLECNT (Bitfield-Mask: 0x0f) */ - -/* ---------------------------- SCU_HIBERNATE_LPACTH0 --------------------------- */ -#define SCU_HIBERNATE_LPACTH0_VBATLO_Pos \ - (0UL) /*!< SCU_HIBERNATE LPACTH0: VBATLO (Bit 0) */ -#define SCU_HIBERNATE_LPACTH0_VBATLO_Msk \ - (0x3fUL) /*!< SCU_HIBERNATE LPACTH0: VBATLO (Bitfield-Mask: 0x3f) */ -#define SCU_HIBERNATE_LPACTH0_VBATHI_Pos \ - (8UL) /*!< SCU_HIBERNATE LPACTH0: VBATHI (Bit 8) */ -#define SCU_HIBERNATE_LPACTH0_VBATHI_Msk \ - (0x3f00UL) /*!< SCU_HIBERNATE LPACTH0: VBATHI (Bitfield-Mask: 0x3f) */ - -/* ---------------------------- SCU_HIBERNATE_LPACTH1 --------------------------- */ -#define SCU_HIBERNATE_LPACTH1_AHIBIO0LO_Pos \ - (0UL) /*!< SCU_HIBERNATE LPACTH1: AHIBIO0LO (Bit 0) */ -#define SCU_HIBERNATE_LPACTH1_AHIBIO0LO_Msk \ - (0x3fUL) /*!< SCU_HIBERNATE LPACTH1: AHIBIO0LO (Bitfield-Mask: 0x3f) */ -#define SCU_HIBERNATE_LPACTH1_AHIBIO0HI_Pos \ - (8UL) /*!< SCU_HIBERNATE LPACTH1: AHIBIO0HI (Bit 8) */ -#define SCU_HIBERNATE_LPACTH1_AHIBIO0HI_Msk \ - (0x3f00UL) /*!< SCU_HIBERNATE LPACTH1: AHIBIO0HI (Bitfield-Mask: 0x3f) */ -#define SCU_HIBERNATE_LPACTH1_AHIBIO1LO_Pos \ - (16UL) /*!< SCU_HIBERNATE LPACTH1: AHIBIO1LO (Bit 16) */ -#define SCU_HIBERNATE_LPACTH1_AHIBIO1LO_Msk \ - (0x3f0000UL) /*!< SCU_HIBERNATE LPACTH1: AHIBIO1LO (Bitfield-Mask: 0x3f) */ -#define SCU_HIBERNATE_LPACTH1_AHIBIO1HI_Pos \ - (24UL) /*!< SCU_HIBERNATE LPACTH1: AHIBIO1HI (Bit 24) */ -#define SCU_HIBERNATE_LPACTH1_AHIBIO1HI_Msk \ - (0x3f000000UL) /*!< SCU_HIBERNATE LPACTH1: AHIBIO1HI (Bitfield-Mask: 0x3f) */ - -/* ---------------------------- SCU_HIBERNATE_LPACST ---------------------------- */ -#define SCU_HIBERNATE_LPACST_VBATSCMP_Pos \ - (0UL) /*!< SCU_HIBERNATE LPACST: VBATSCMP (Bit 0) */ -#define SCU_HIBERNATE_LPACST_VBATSCMP_Msk \ - (0x1UL) /*!< SCU_HIBERNATE LPACST: VBATSCMP (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_LPACST_AHIBIO0SCMP_Pos \ - (1UL) /*!< SCU_HIBERNATE LPACST: AHIBIO0SCMP (Bit 1) */ -#define SCU_HIBERNATE_LPACST_AHIBIO0SCMP_Msk \ - (0x2UL) /*!< SCU_HIBERNATE LPACST: AHIBIO0SCMP (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_LPACST_AHIBIO1SCMP_Pos \ - (2UL) /*!< SCU_HIBERNATE LPACST: AHIBIO1SCMP (Bit 2) */ -#define SCU_HIBERNATE_LPACST_AHIBIO1SCMP_Msk \ - (0x4UL) /*!< SCU_HIBERNATE LPACST: AHIBIO1SCMP (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_LPACST_VBATVAL_Pos \ - (16UL) /*!< SCU_HIBERNATE LPACST: VBATVAL (Bit 16) */ -#define SCU_HIBERNATE_LPACST_VBATVAL_Msk \ - (0x10000UL) /*!< SCU_HIBERNATE LPACST: VBATVAL (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_LPACST_AHIBIO0VAL_Pos \ - (17UL) /*!< SCU_HIBERNATE LPACST: AHIBIO0VAL (Bit 17) */ -#define SCU_HIBERNATE_LPACST_AHIBIO0VAL_Msk \ - (0x20000UL) /*!< SCU_HIBERNATE LPACST: AHIBIO0VAL (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_LPACST_AHIBIO1VAL_Pos \ - (18UL) /*!< SCU_HIBERNATE LPACST: AHIBIO1VAL (Bit 18) */ -#define SCU_HIBERNATE_LPACST_AHIBIO1VAL_Msk \ - (0x40000UL) /*!< SCU_HIBERNATE LPACST: AHIBIO1VAL (Bitfield-Mask: 0x01) */ - -/* ---------------------------- SCU_HIBERNATE_LPACCLR --------------------------- */ -#define SCU_HIBERNATE_LPACCLR_VBATSCMP_Pos \ - (0UL) /*!< SCU_HIBERNATE LPACCLR: VBATSCMP (Bit 0) */ -#define SCU_HIBERNATE_LPACCLR_VBATSCMP_Msk \ - (0x1UL) /*!< SCU_HIBERNATE LPACCLR: VBATSCMP (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_LPACCLR_AHIBIO0SCMP_Pos \ - (1UL) /*!< SCU_HIBERNATE LPACCLR: AHIBIO0SCMP (Bit 1) */ -#define SCU_HIBERNATE_LPACCLR_AHIBIO0SCMP_Msk \ - (0x2UL) /*!< SCU_HIBERNATE LPACCLR: AHIBIO0SCMP (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_LPACCLR_AHIBIO1SCMP_Pos \ - (2UL) /*!< SCU_HIBERNATE LPACCLR: AHIBIO1SCMP (Bit 2) */ -#define SCU_HIBERNATE_LPACCLR_AHIBIO1SCMP_Msk \ - (0x4UL) /*!< SCU_HIBERNATE LPACCLR: AHIBIO1SCMP (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_LPACCLR_VBATVAL_Pos \ - (16UL) /*!< SCU_HIBERNATE LPACCLR: VBATVAL (Bit 16) */ -#define SCU_HIBERNATE_LPACCLR_VBATVAL_Msk \ - (0x10000UL) /*!< SCU_HIBERNATE LPACCLR: VBATVAL (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_LPACCLR_AHIBIO0VAL_Pos \ - (17UL) /*!< SCU_HIBERNATE LPACCLR: AHIBIO0VAL (Bit 17) */ -#define SCU_HIBERNATE_LPACCLR_AHIBIO0VAL_Msk \ - (0x20000UL) /*!< SCU_HIBERNATE LPACCLR: AHIBIO0VAL (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_LPACCLR_AHIBIO1VAL_Pos \ - (18UL) /*!< SCU_HIBERNATE LPACCLR: AHIBIO1VAL (Bit 18) */ -#define SCU_HIBERNATE_LPACCLR_AHIBIO1VAL_Msk \ - (0x40000UL) /*!< SCU_HIBERNATE LPACCLR: AHIBIO1VAL (Bitfield-Mask: 0x01) */ - -/* ---------------------------- SCU_HIBERNATE_LPACSET --------------------------- */ -#define SCU_HIBERNATE_LPACSET_VBATSCMP_Pos \ - (0UL) /*!< SCU_HIBERNATE LPACSET: VBATSCMP (Bit 0) */ -#define SCU_HIBERNATE_LPACSET_VBATSCMP_Msk \ - (0x1UL) /*!< SCU_HIBERNATE LPACSET: VBATSCMP (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_LPACSET_AHIBIO0SCMP_Pos \ - (1UL) /*!< SCU_HIBERNATE LPACSET: AHIBIO0SCMP (Bit 1) */ -#define SCU_HIBERNATE_LPACSET_AHIBIO0SCMP_Msk \ - (0x2UL) /*!< SCU_HIBERNATE LPACSET: AHIBIO0SCMP (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_LPACSET_AHIBIO1SCMP_Pos \ - (2UL) /*!< SCU_HIBERNATE LPACSET: AHIBIO1SCMP (Bit 2) */ -#define SCU_HIBERNATE_LPACSET_AHIBIO1SCMP_Msk \ - (0x4UL) /*!< SCU_HIBERNATE LPACSET: AHIBIO1SCMP (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_LPACSET_VBATVAL_Pos \ - (16UL) /*!< SCU_HIBERNATE LPACSET: VBATVAL (Bit 16) */ -#define SCU_HIBERNATE_LPACSET_VBATVAL_Msk \ - (0x10000UL) /*!< SCU_HIBERNATE LPACSET: VBATVAL (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_LPACSET_AHIBIO0VAL_Pos \ - (17UL) /*!< SCU_HIBERNATE LPACSET: AHIBIO0VAL (Bit 17) */ -#define SCU_HIBERNATE_LPACSET_AHIBIO0VAL_Msk \ - (0x20000UL) /*!< SCU_HIBERNATE LPACSET: AHIBIO0VAL (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_LPACSET_AHIBIO1VAL_Pos \ - (18UL) /*!< SCU_HIBERNATE LPACSET: AHIBIO1VAL (Bit 18) */ -#define SCU_HIBERNATE_LPACSET_AHIBIO1VAL_Msk \ - (0x40000UL) /*!< SCU_HIBERNATE LPACSET: AHIBIO1VAL (Bitfield-Mask: 0x01) */ - -/* ---------------------------- SCU_HIBERNATE_HINTST ---------------------------- */ -#define SCU_HIBERNATE_HINTST_HIBNINT_Pos \ - (0UL) /*!< SCU_HIBERNATE HINTST: HIBNINT (Bit 0) */ -#define SCU_HIBERNATE_HINTST_HIBNINT_Msk \ - (0x1UL) /*!< SCU_HIBERNATE HINTST: HIBNINT (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HINTST_FLASHOFF_Pos \ - (2UL) /*!< SCU_HIBERNATE HINTST: FLASHOFF (Bit 2) */ -#define SCU_HIBERNATE_HINTST_FLASHOFF_Msk \ - (0x4UL) /*!< SCU_HIBERNATE HINTST: FLASHOFF (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HINTST_FLASHPD_Pos \ - (3UL) /*!< SCU_HIBERNATE HINTST: FLASHPD (Bit 3) */ -#define SCU_HIBERNATE_HINTST_FLASHPD_Msk \ - (0x8UL) /*!< SCU_HIBERNATE HINTST: FLASHPD (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HINTST_POFFD_Pos \ - (4UL) /*!< SCU_HIBERNATE HINTST: POFFD (Bit 4) */ -#define SCU_HIBERNATE_HINTST_POFFD_Msk \ - (0x10UL) /*!< SCU_HIBERNATE HINTST: POFFD (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HINTST_PPODEL_Pos \ - (16UL) /*!< SCU_HIBERNATE HINTST: PPODEL (Bit 16) */ -#define SCU_HIBERNATE_HINTST_PPODEL_Msk \ - (0x30000UL) /*!< SCU_HIBERNATE HINTST: PPODEL (Bitfield-Mask: 0x03) */ -#define SCU_HIBERNATE_HINTST_POFFH_Pos \ - (20UL) /*!< SCU_HIBERNATE HINTST: POFFH (Bit 20) */ -#define SCU_HIBERNATE_HINTST_POFFH_Msk \ - (0x100000UL) /*!< SCU_HIBERNATE HINTST: POFFH (Bitfield-Mask: 0x01) */ - -/* ---------------------------- SCU_HIBERNATE_HINTCLR --------------------------- */ -#define SCU_HIBERNATE_HINTCLR_HIBNINT_Pos \ - (0UL) /*!< SCU_HIBERNATE HINTCLR: HIBNINT (Bit 0) */ -#define SCU_HIBERNATE_HINTCLR_HIBNINT_Msk \ - (0x1UL) /*!< SCU_HIBERNATE HINTCLR: HIBNINT (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HINTCLR_FLASHOFF_Pos \ - (2UL) /*!< SCU_HIBERNATE HINTCLR: FLASHOFF (Bit 2) */ -#define SCU_HIBERNATE_HINTCLR_FLASHOFF_Msk \ - (0x4UL) /*!< SCU_HIBERNATE HINTCLR: FLASHOFF (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HINTCLR_FLASHPD_Pos \ - (3UL) /*!< SCU_HIBERNATE HINTCLR: FLASHPD (Bit 3) */ -#define SCU_HIBERNATE_HINTCLR_FLASHPD_Msk \ - (0x8UL) /*!< SCU_HIBERNATE HINTCLR: FLASHPD (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HINTCLR_POFFD_Pos \ - (4UL) /*!< SCU_HIBERNATE HINTCLR: POFFD (Bit 4) */ -#define SCU_HIBERNATE_HINTCLR_POFFD_Msk \ - (0x10UL) /*!< SCU_HIBERNATE HINTCLR: POFFD (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HINTCLR_PPODEL_Pos \ - (16UL) /*!< SCU_HIBERNATE HINTCLR: PPODEL (Bit 16) */ -#define SCU_HIBERNATE_HINTCLR_PPODEL_Msk \ - (0x30000UL) /*!< SCU_HIBERNATE HINTCLR: PPODEL (Bitfield-Mask: 0x03) */ -#define SCU_HIBERNATE_HINTCLR_POFFH_Pos \ - (20UL) /*!< SCU_HIBERNATE HINTCLR: POFFH (Bit 20) */ -#define SCU_HIBERNATE_HINTCLR_POFFH_Msk \ - (0x100000UL) /*!< SCU_HIBERNATE HINTCLR: POFFH (Bitfield-Mask: 0x01) */ - -/* ---------------------------- SCU_HIBERNATE_HINTSET --------------------------- */ -#define SCU_HIBERNATE_HINTSET_HIBNINT_Pos \ - (0UL) /*!< SCU_HIBERNATE HINTSET: HIBNINT (Bit 0) */ -#define SCU_HIBERNATE_HINTSET_HIBNINT_Msk \ - (0x1UL) /*!< SCU_HIBERNATE HINTSET: HIBNINT (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HINTSET_VCOREOFF_Pos \ - (1UL) /*!< SCU_HIBERNATE HINTSET: VCOREOFF (Bit 1) */ -#define SCU_HIBERNATE_HINTSET_VCOREOFF_Msk \ - (0x2UL) /*!< SCU_HIBERNATE HINTSET: VCOREOFF (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HINTSET_FLASHOFF_Pos \ - (2UL) /*!< SCU_HIBERNATE HINTSET: FLASHOFF (Bit 2) */ -#define SCU_HIBERNATE_HINTSET_FLASHOFF_Msk \ - (0x4UL) /*!< SCU_HIBERNATE HINTSET: FLASHOFF (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HINTSET_FLASHPD_Pos \ - (3UL) /*!< SCU_HIBERNATE HINTSET: FLASHPD (Bit 3) */ -#define SCU_HIBERNATE_HINTSET_FLASHPD_Msk \ - (0x8UL) /*!< SCU_HIBERNATE HINTSET: FLASHPD (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HINTSET_POFFD_Pos \ - (4UL) /*!< SCU_HIBERNATE HINTSET: POFFD (Bit 4) */ -#define SCU_HIBERNATE_HINTSET_POFFD_Msk \ - (0x10UL) /*!< SCU_HIBERNATE HINTSET: POFFD (Bitfield-Mask: 0x01) */ -#define SCU_HIBERNATE_HINTSET_PPODEL_Pos \ - (16UL) /*!< SCU_HIBERNATE HINTSET: PPODEL (Bit 16) */ -#define SCU_HIBERNATE_HINTSET_PPODEL_Msk \ - (0x30000UL) /*!< SCU_HIBERNATE HINTSET: PPODEL (Bitfield-Mask: 0x03) */ -#define SCU_HIBERNATE_HINTSET_POFFH_Pos \ - (20UL) /*!< SCU_HIBERNATE HINTSET: POFFH (Bit 20) */ -#define SCU_HIBERNATE_HINTSET_POFFH_Msk \ - (0x100000UL) /*!< SCU_HIBERNATE HINTSET: POFFH (Bitfield-Mask: 0x01) */ - -/* ================================================================================ */ -/* ================ struct 'SCU_POWER' Position & Mask ================ */ -/* ================================================================================ */ - -/* ------------------------------ SCU_POWER_PWRSTAT ----------------------------- */ -#define SCU_POWER_PWRSTAT_HIBEN_Pos \ - (0UL) /*!< SCU_POWER PWRSTAT: HIBEN (Bit 0) */ -#define SCU_POWER_PWRSTAT_HIBEN_Msk \ - (0x1UL) /*!< SCU_POWER PWRSTAT: HIBEN (Bitfield-Mask: 0x01) */ -#define SCU_POWER_PWRSTAT_USBPHYPDQ_Pos \ - (16UL) /*!< SCU_POWER PWRSTAT: USBPHYPDQ (Bit 16) */ -#define SCU_POWER_PWRSTAT_USBPHYPDQ_Msk \ - (0x10000UL) /*!< SCU_POWER PWRSTAT: USBPHYPDQ (Bitfield-Mask: 0x01) */ -#define SCU_POWER_PWRSTAT_USBOTGEN_Pos \ - (17UL) /*!< SCU_POWER PWRSTAT: USBOTGEN (Bit 17) */ -#define SCU_POWER_PWRSTAT_USBOTGEN_Msk \ - (0x20000UL) /*!< SCU_POWER PWRSTAT: USBOTGEN (Bitfield-Mask: 0x01) */ -#define SCU_POWER_PWRSTAT_USBPUWQ_Pos \ - (18UL) /*!< SCU_POWER PWRSTAT: USBPUWQ (Bit 18) */ -#define SCU_POWER_PWRSTAT_USBPUWQ_Msk \ - (0x40000UL) /*!< SCU_POWER PWRSTAT: USBPUWQ (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_POWER_PWRSET ------------------------------ */ -#define SCU_POWER_PWRSET_HIB_Pos \ - (0UL) /*!< SCU_POWER PWRSET: HIB (Bit 0) */ -#define SCU_POWER_PWRSET_HIB_Msk \ - (0x1UL) /*!< SCU_POWER PWRSET: HIB (Bitfield-Mask: 0x01) */ -#define SCU_POWER_PWRSET_USBPHYPDQ_Pos \ - (16UL) /*!< SCU_POWER PWRSET: USBPHYPDQ (Bit 16) */ -#define SCU_POWER_PWRSET_USBPHYPDQ_Msk \ - (0x10000UL) /*!< SCU_POWER PWRSET: USBPHYPDQ (Bitfield-Mask: 0x01) */ -#define SCU_POWER_PWRSET_USBOTGEN_Pos \ - (17UL) /*!< SCU_POWER PWRSET: USBOTGEN (Bit 17) */ -#define SCU_POWER_PWRSET_USBOTGEN_Msk \ - (0x20000UL) /*!< SCU_POWER PWRSET: USBOTGEN (Bitfield-Mask: 0x01) */ -#define SCU_POWER_PWRSET_USBPUWQ_Pos \ - (18UL) /*!< SCU_POWER PWRSET: USBPUWQ (Bit 18) */ -#define SCU_POWER_PWRSET_USBPUWQ_Msk \ - (0x40000UL) /*!< SCU_POWER PWRSET: USBPUWQ (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_POWER_PWRCLR ------------------------------ */ -#define SCU_POWER_PWRCLR_HIB_Pos \ - (0UL) /*!< SCU_POWER PWRCLR: HIB (Bit 0) */ -#define SCU_POWER_PWRCLR_HIB_Msk \ - (0x1UL) /*!< SCU_POWER PWRCLR: HIB (Bitfield-Mask: 0x01) */ -#define SCU_POWER_PWRCLR_USBPHYPDQ_Pos \ - (16UL) /*!< SCU_POWER PWRCLR: USBPHYPDQ (Bit 16) */ -#define SCU_POWER_PWRCLR_USBPHYPDQ_Msk \ - (0x10000UL) /*!< SCU_POWER PWRCLR: USBPHYPDQ (Bitfield-Mask: 0x01) */ -#define SCU_POWER_PWRCLR_USBOTGEN_Pos \ - (17UL) /*!< SCU_POWER PWRCLR: USBOTGEN (Bit 17) */ -#define SCU_POWER_PWRCLR_USBOTGEN_Msk \ - (0x20000UL) /*!< SCU_POWER PWRCLR: USBOTGEN (Bitfield-Mask: 0x01) */ -#define SCU_POWER_PWRCLR_USBPUWQ_Pos \ - (18UL) /*!< SCU_POWER PWRCLR: USBPUWQ (Bit 18) */ -#define SCU_POWER_PWRCLR_USBPUWQ_Msk \ - (0x40000UL) /*!< SCU_POWER PWRCLR: USBPUWQ (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_POWER_EVRSTAT ----------------------------- */ -#define SCU_POWER_EVRSTAT_OV13_Pos \ - (1UL) /*!< SCU_POWER EVRSTAT: OV13 (Bit 1) */ -#define SCU_POWER_EVRSTAT_OV13_Msk \ - (0x2UL) /*!< SCU_POWER EVRSTAT: OV13 (Bitfield-Mask: 0x01) */ - -/* ---------------------------- SCU_POWER_EVRVADCSTAT --------------------------- */ -#define SCU_POWER_EVRVADCSTAT_VADC13V_Pos \ - (0UL) /*!< SCU_POWER EVRVADCSTAT: VADC13V (Bit 0) */ -#define SCU_POWER_EVRVADCSTAT_VADC13V_Msk \ - (0xffUL) /*!< SCU_POWER EVRVADCSTAT: VADC13V (Bitfield-Mask: 0xff) */ -#define SCU_POWER_EVRVADCSTAT_VADC33V_Pos \ - (8UL) /*!< SCU_POWER EVRVADCSTAT: VADC33V (Bit 8) */ -#define SCU_POWER_EVRVADCSTAT_VADC33V_Msk \ - (0xff00UL) /*!< SCU_POWER EVRVADCSTAT: VADC33V (Bitfield-Mask: 0xff) */ - -/* ------------------------------ SCU_POWER_PWRMON ------------------------------ */ -#define SCU_POWER_PWRMON_THRS_Pos \ - (0UL) /*!< SCU_POWER PWRMON: THRS (Bit 0) */ -#define SCU_POWER_PWRMON_THRS_Msk \ - (0xffUL) /*!< SCU_POWER PWRMON: THRS (Bitfield-Mask: 0xff) */ -#define SCU_POWER_PWRMON_INTV_Pos \ - (8UL) /*!< SCU_POWER PWRMON: INTV (Bit 8) */ -#define SCU_POWER_PWRMON_INTV_Msk \ - (0xff00UL) /*!< SCU_POWER PWRMON: INTV (Bitfield-Mask: 0xff) */ -#define SCU_POWER_PWRMON_ENB_Pos \ - (16UL) /*!< SCU_POWER PWRMON: ENB (Bit 16) */ -#define SCU_POWER_PWRMON_ENB_Msk \ - (0x10000UL) /*!< SCU_POWER PWRMON: ENB (Bitfield-Mask: 0x01) */ - -/* ================================================================================ */ -/* ================ struct 'SCU_RESET' Position & Mask ================ */ -/* ================================================================================ */ - -/* ------------------------------ SCU_RESET_RSTSTAT ----------------------------- */ -#define SCU_RESET_RSTSTAT_RSTSTAT_Pos \ - (0UL) /*!< SCU_RESET RSTSTAT: RSTSTAT (Bit 0) */ -#define SCU_RESET_RSTSTAT_RSTSTAT_Msk \ - (0xffUL) /*!< SCU_RESET RSTSTAT: RSTSTAT (Bitfield-Mask: 0xff) */ -#define SCU_RESET_RSTSTAT_HIBWK_Pos \ - (8UL) /*!< SCU_RESET RSTSTAT: HIBWK (Bit 8) */ -#define SCU_RESET_RSTSTAT_HIBWK_Msk \ - (0x100UL) /*!< SCU_RESET RSTSTAT: HIBWK (Bitfield-Mask: 0x01) */ -#define SCU_RESET_RSTSTAT_HIBRS_Pos \ - (9UL) /*!< SCU_RESET RSTSTAT: HIBRS (Bit 9) */ -#define SCU_RESET_RSTSTAT_HIBRS_Msk \ - (0x200UL) /*!< SCU_RESET RSTSTAT: HIBRS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_RSTSTAT_LCKEN_Pos \ - (10UL) /*!< SCU_RESET RSTSTAT: LCKEN (Bit 10) */ -#define SCU_RESET_RSTSTAT_LCKEN_Msk \ - (0x400UL) /*!< SCU_RESET RSTSTAT: LCKEN (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_RESET_RSTSET ------------------------------ */ -#define SCU_RESET_RSTSET_HIBWK_Pos \ - (8UL) /*!< SCU_RESET RSTSET: HIBWK (Bit 8) */ -#define SCU_RESET_RSTSET_HIBWK_Msk \ - (0x100UL) /*!< SCU_RESET RSTSET: HIBWK (Bitfield-Mask: 0x01) */ -#define SCU_RESET_RSTSET_HIBRS_Pos \ - (9UL) /*!< SCU_RESET RSTSET: HIBRS (Bit 9) */ -#define SCU_RESET_RSTSET_HIBRS_Msk \ - (0x200UL) /*!< SCU_RESET RSTSET: HIBRS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_RSTSET_LCKEN_Pos \ - (10UL) /*!< SCU_RESET RSTSET: LCKEN (Bit 10) */ -#define SCU_RESET_RSTSET_LCKEN_Msk \ - (0x400UL) /*!< SCU_RESET RSTSET: LCKEN (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_RESET_RSTCLR ------------------------------ */ -#define SCU_RESET_RSTCLR_RSCLR_Pos \ - (0UL) /*!< SCU_RESET RSTCLR: RSCLR (Bit 0) */ -#define SCU_RESET_RSTCLR_RSCLR_Msk \ - (0x1UL) /*!< SCU_RESET RSTCLR: RSCLR (Bitfield-Mask: 0x01) */ -#define SCU_RESET_RSTCLR_HIBWK_Pos \ - (8UL) /*!< SCU_RESET RSTCLR: HIBWK (Bit 8) */ -#define SCU_RESET_RSTCLR_HIBWK_Msk \ - (0x100UL) /*!< SCU_RESET RSTCLR: HIBWK (Bitfield-Mask: 0x01) */ -#define SCU_RESET_RSTCLR_HIBRS_Pos \ - (9UL) /*!< SCU_RESET RSTCLR: HIBRS (Bit 9) */ -#define SCU_RESET_RSTCLR_HIBRS_Msk \ - (0x200UL) /*!< SCU_RESET RSTCLR: HIBRS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_RSTCLR_LCKEN_Pos \ - (10UL) /*!< SCU_RESET RSTCLR: LCKEN (Bit 10) */ -#define SCU_RESET_RSTCLR_LCKEN_Msk \ - (0x400UL) /*!< SCU_RESET RSTCLR: LCKEN (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_RESET_PRSTAT0 ----------------------------- */ -#define SCU_RESET_PRSTAT0_VADCRS_Pos \ - (0UL) /*!< SCU_RESET PRSTAT0: VADCRS (Bit 0) */ -#define SCU_RESET_PRSTAT0_VADCRS_Msk \ - (0x1UL) /*!< SCU_RESET PRSTAT0: VADCRS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSTAT0_DSDRS_Pos \ - (1UL) /*!< SCU_RESET PRSTAT0: DSDRS (Bit 1) */ -#define SCU_RESET_PRSTAT0_DSDRS_Msk \ - (0x2UL) /*!< SCU_RESET PRSTAT0: DSDRS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSTAT0_CCU40RS_Pos \ - (2UL) /*!< SCU_RESET PRSTAT0: CCU40RS (Bit 2) */ -#define SCU_RESET_PRSTAT0_CCU40RS_Msk \ - (0x4UL) /*!< SCU_RESET PRSTAT0: CCU40RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSTAT0_CCU41RS_Pos \ - (3UL) /*!< SCU_RESET PRSTAT0: CCU41RS (Bit 3) */ -#define SCU_RESET_PRSTAT0_CCU41RS_Msk \ - (0x8UL) /*!< SCU_RESET PRSTAT0: CCU41RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSTAT0_CCU42RS_Pos \ - (4UL) /*!< SCU_RESET PRSTAT0: CCU42RS (Bit 4) */ -#define SCU_RESET_PRSTAT0_CCU42RS_Msk \ - (0x10UL) /*!< SCU_RESET PRSTAT0: CCU42RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSTAT0_CCU80RS_Pos \ - (7UL) /*!< SCU_RESET PRSTAT0: CCU80RS (Bit 7) */ -#define SCU_RESET_PRSTAT0_CCU80RS_Msk \ - (0x80UL) /*!< SCU_RESET PRSTAT0: CCU80RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSTAT0_CCU81RS_Pos \ - (8UL) /*!< SCU_RESET PRSTAT0: CCU81RS (Bit 8) */ -#define SCU_RESET_PRSTAT0_CCU81RS_Msk \ - (0x100UL) /*!< SCU_RESET PRSTAT0: CCU81RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSTAT0_POSIF0RS_Pos \ - (9UL) /*!< SCU_RESET PRSTAT0: POSIF0RS (Bit 9) */ -#define SCU_RESET_PRSTAT0_POSIF0RS_Msk \ - (0x200UL) /*!< SCU_RESET PRSTAT0: POSIF0RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSTAT0_POSIF1RS_Pos \ - (10UL) /*!< SCU_RESET PRSTAT0: POSIF1RS (Bit 10) */ -#define SCU_RESET_PRSTAT0_POSIF1RS_Msk \ - (0x400UL) /*!< SCU_RESET PRSTAT0: POSIF1RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSTAT0_USIC0RS_Pos \ - (11UL) /*!< SCU_RESET PRSTAT0: USIC0RS (Bit 11) */ -#define SCU_RESET_PRSTAT0_USIC0RS_Msk \ - (0x800UL) /*!< SCU_RESET PRSTAT0: USIC0RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSTAT0_ERU1RS_Pos \ - (16UL) /*!< SCU_RESET PRSTAT0: ERU1RS (Bit 16) */ -#define SCU_RESET_PRSTAT0_ERU1RS_Msk \ - (0x10000UL) /*!< SCU_RESET PRSTAT0: ERU1RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSTAT0_HRPWM0RS_Pos \ - (23UL) /*!< SCU_RESET PRSTAT0: HRPWM0RS (Bit 23) */ -#define SCU_RESET_PRSTAT0_HRPWM0RS_Msk \ - (0x800000UL) /*!< SCU_RESET PRSTAT0: HRPWM0RS (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_RESET_PRSET0 ------------------------------ */ -#define SCU_RESET_PRSET0_VADCRS_Pos \ - (0UL) /*!< SCU_RESET PRSET0: VADCRS (Bit 0) */ -#define SCU_RESET_PRSET0_VADCRS_Msk \ - (0x1UL) /*!< SCU_RESET PRSET0: VADCRS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSET0_DSDRS_Pos \ - (1UL) /*!< SCU_RESET PRSET0: DSDRS (Bit 1) */ -#define SCU_RESET_PRSET0_DSDRS_Msk \ - (0x2UL) /*!< SCU_RESET PRSET0: DSDRS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSET0_CCU40RS_Pos \ - (2UL) /*!< SCU_RESET PRSET0: CCU40RS (Bit 2) */ -#define SCU_RESET_PRSET0_CCU40RS_Msk \ - (0x4UL) /*!< SCU_RESET PRSET0: CCU40RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSET0_CCU41RS_Pos \ - (3UL) /*!< SCU_RESET PRSET0: CCU41RS (Bit 3) */ -#define SCU_RESET_PRSET0_CCU41RS_Msk \ - (0x8UL) /*!< SCU_RESET PRSET0: CCU41RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSET0_CCU42RS_Pos \ - (4UL) /*!< SCU_RESET PRSET0: CCU42RS (Bit 4) */ -#define SCU_RESET_PRSET0_CCU42RS_Msk \ - (0x10UL) /*!< SCU_RESET PRSET0: CCU42RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSET0_CCU80RS_Pos \ - (7UL) /*!< SCU_RESET PRSET0: CCU80RS (Bit 7) */ -#define SCU_RESET_PRSET0_CCU80RS_Msk \ - (0x80UL) /*!< SCU_RESET PRSET0: CCU80RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSET0_CCU81RS_Pos \ - (8UL) /*!< SCU_RESET PRSET0: CCU81RS (Bit 8) */ -#define SCU_RESET_PRSET0_CCU81RS_Msk \ - (0x100UL) /*!< SCU_RESET PRSET0: CCU81RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSET0_POSIF0RS_Pos \ - (9UL) /*!< SCU_RESET PRSET0: POSIF0RS (Bit 9) */ -#define SCU_RESET_PRSET0_POSIF0RS_Msk \ - (0x200UL) /*!< SCU_RESET PRSET0: POSIF0RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSET0_POSIF1RS_Pos \ - (10UL) /*!< SCU_RESET PRSET0: POSIF1RS (Bit 10) */ -#define SCU_RESET_PRSET0_POSIF1RS_Msk \ - (0x400UL) /*!< SCU_RESET PRSET0: POSIF1RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSET0_USIC0RS_Pos \ - (11UL) /*!< SCU_RESET PRSET0: USIC0RS (Bit 11) */ -#define SCU_RESET_PRSET0_USIC0RS_Msk \ - (0x800UL) /*!< SCU_RESET PRSET0: USIC0RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSET0_ERU1RS_Pos \ - (16UL) /*!< SCU_RESET PRSET0: ERU1RS (Bit 16) */ -#define SCU_RESET_PRSET0_ERU1RS_Msk \ - (0x10000UL) /*!< SCU_RESET PRSET0: ERU1RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSET0_HRPWM0RS_Pos \ - (23UL) /*!< SCU_RESET PRSET0: HRPWM0RS (Bit 23) */ -#define SCU_RESET_PRSET0_HRPWM0RS_Msk \ - (0x800000UL) /*!< SCU_RESET PRSET0: HRPWM0RS (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_RESET_PRCLR0 ------------------------------ */ -#define SCU_RESET_PRCLR0_VADCRS_Pos \ - (0UL) /*!< SCU_RESET PRCLR0: VADCRS (Bit 0) */ -#define SCU_RESET_PRCLR0_VADCRS_Msk \ - (0x1UL) /*!< SCU_RESET PRCLR0: VADCRS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRCLR0_DSDRS_Pos \ - (1UL) /*!< SCU_RESET PRCLR0: DSDRS (Bit 1) */ -#define SCU_RESET_PRCLR0_DSDRS_Msk \ - (0x2UL) /*!< SCU_RESET PRCLR0: DSDRS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRCLR0_CCU40RS_Pos \ - (2UL) /*!< SCU_RESET PRCLR0: CCU40RS (Bit 2) */ -#define SCU_RESET_PRCLR0_CCU40RS_Msk \ - (0x4UL) /*!< SCU_RESET PRCLR0: CCU40RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRCLR0_CCU41RS_Pos \ - (3UL) /*!< SCU_RESET PRCLR0: CCU41RS (Bit 3) */ -#define SCU_RESET_PRCLR0_CCU41RS_Msk \ - (0x8UL) /*!< SCU_RESET PRCLR0: CCU41RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRCLR0_CCU42RS_Pos \ - (4UL) /*!< SCU_RESET PRCLR0: CCU42RS (Bit 4) */ -#define SCU_RESET_PRCLR0_CCU42RS_Msk \ - (0x10UL) /*!< SCU_RESET PRCLR0: CCU42RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRCLR0_CCU80RS_Pos \ - (7UL) /*!< SCU_RESET PRCLR0: CCU80RS (Bit 7) */ -#define SCU_RESET_PRCLR0_CCU80RS_Msk \ - (0x80UL) /*!< SCU_RESET PRCLR0: CCU80RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRCLR0_CCU81RS_Pos \ - (8UL) /*!< SCU_RESET PRCLR0: CCU81RS (Bit 8) */ -#define SCU_RESET_PRCLR0_CCU81RS_Msk \ - (0x100UL) /*!< SCU_RESET PRCLR0: CCU81RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRCLR0_POSIF0RS_Pos \ - (9UL) /*!< SCU_RESET PRCLR0: POSIF0RS (Bit 9) */ -#define SCU_RESET_PRCLR0_POSIF0RS_Msk \ - (0x200UL) /*!< SCU_RESET PRCLR0: POSIF0RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRCLR0_POSIF1RS_Pos \ - (10UL) /*!< SCU_RESET PRCLR0: POSIF1RS (Bit 10) */ -#define SCU_RESET_PRCLR0_POSIF1RS_Msk \ - (0x400UL) /*!< SCU_RESET PRCLR0: POSIF1RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRCLR0_USIC0RS_Pos \ - (11UL) /*!< SCU_RESET PRCLR0: USIC0RS (Bit 11) */ -#define SCU_RESET_PRCLR0_USIC0RS_Msk \ - (0x800UL) /*!< SCU_RESET PRCLR0: USIC0RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRCLR0_ERU1RS_Pos \ - (16UL) /*!< SCU_RESET PRCLR0: ERU1RS (Bit 16) */ -#define SCU_RESET_PRCLR0_ERU1RS_Msk \ - (0x10000UL) /*!< SCU_RESET PRCLR0: ERU1RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRCLR0_HRPWM0RS_Pos \ - (23UL) /*!< SCU_RESET PRCLR0: HRPWM0RS (Bit 23) */ -#define SCU_RESET_PRCLR0_HRPWM0RS_Msk \ - (0x800000UL) /*!< SCU_RESET PRCLR0: HRPWM0RS (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_RESET_PRSTAT1 ----------------------------- */ -#define SCU_RESET_PRSTAT1_CCU43RS_Pos \ - (0UL) /*!< SCU_RESET PRSTAT1: CCU43RS (Bit 0) */ -#define SCU_RESET_PRSTAT1_CCU43RS_Msk \ - (0x1UL) /*!< SCU_RESET PRSTAT1: CCU43RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSTAT1_LEDTSCU0RS_Pos \ - (3UL) /*!< SCU_RESET PRSTAT1: LEDTSCU0RS (Bit 3) */ -#define SCU_RESET_PRSTAT1_LEDTSCU0RS_Msk \ - (0x8UL) /*!< SCU_RESET PRSTAT1: LEDTSCU0RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSTAT1_MCAN0RS_Pos \ - (4UL) /*!< SCU_RESET PRSTAT1: MCAN0RS (Bit 4) */ -#define SCU_RESET_PRSTAT1_MCAN0RS_Msk \ - (0x10UL) /*!< SCU_RESET PRSTAT1: MCAN0RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSTAT1_DACRS_Pos \ - (5UL) /*!< SCU_RESET PRSTAT1: DACRS (Bit 5) */ -#define SCU_RESET_PRSTAT1_DACRS_Msk \ - (0x20UL) /*!< SCU_RESET PRSTAT1: DACRS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSTAT1_USIC1RS_Pos \ - (7UL) /*!< SCU_RESET PRSTAT1: USIC1RS (Bit 7) */ -#define SCU_RESET_PRSTAT1_USIC1RS_Msk \ - (0x80UL) /*!< SCU_RESET PRSTAT1: USIC1RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSTAT1_PPORTSRS_Pos \ - (9UL) /*!< SCU_RESET PRSTAT1: PPORTSRS (Bit 9) */ -#define SCU_RESET_PRSTAT1_PPORTSRS_Msk \ - (0x200UL) /*!< SCU_RESET PRSTAT1: PPORTSRS (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_RESET_PRSET1 ------------------------------ */ -#define SCU_RESET_PRSET1_CCU43RS_Pos \ - (0UL) /*!< SCU_RESET PRSET1: CCU43RS (Bit 0) */ -#define SCU_RESET_PRSET1_CCU43RS_Msk \ - (0x1UL) /*!< SCU_RESET PRSET1: CCU43RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSET1_LEDTSCU0RS_Pos \ - (3UL) /*!< SCU_RESET PRSET1: LEDTSCU0RS (Bit 3) */ -#define SCU_RESET_PRSET1_LEDTSCU0RS_Msk \ - (0x8UL) /*!< SCU_RESET PRSET1: LEDTSCU0RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSET1_MCAN0RS_Pos \ - (4UL) /*!< SCU_RESET PRSET1: MCAN0RS (Bit 4) */ -#define SCU_RESET_PRSET1_MCAN0RS_Msk \ - (0x10UL) /*!< SCU_RESET PRSET1: MCAN0RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSET1_DACRS_Pos \ - (5UL) /*!< SCU_RESET PRSET1: DACRS (Bit 5) */ -#define SCU_RESET_PRSET1_DACRS_Msk \ - (0x20UL) /*!< SCU_RESET PRSET1: DACRS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSET1_USIC1RS_Pos \ - (7UL) /*!< SCU_RESET PRSET1: USIC1RS (Bit 7) */ -#define SCU_RESET_PRSET1_USIC1RS_Msk \ - (0x80UL) /*!< SCU_RESET PRSET1: USIC1RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSET1_PPORTSRS_Pos \ - (9UL) /*!< SCU_RESET PRSET1: PPORTSRS (Bit 9) */ -#define SCU_RESET_PRSET1_PPORTSRS_Msk \ - (0x200UL) /*!< SCU_RESET PRSET1: PPORTSRS (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_RESET_PRCLR1 ------------------------------ */ -#define SCU_RESET_PRCLR1_CCU43RS_Pos \ - (0UL) /*!< SCU_RESET PRCLR1: CCU43RS (Bit 0) */ -#define SCU_RESET_PRCLR1_CCU43RS_Msk \ - (0x1UL) /*!< SCU_RESET PRCLR1: CCU43RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRCLR1_LEDTSCU0RS_Pos \ - (3UL) /*!< SCU_RESET PRCLR1: LEDTSCU0RS (Bit 3) */ -#define SCU_RESET_PRCLR1_LEDTSCU0RS_Msk \ - (0x8UL) /*!< SCU_RESET PRCLR1: LEDTSCU0RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRCLR1_MCAN0RS_Pos \ - (4UL) /*!< SCU_RESET PRCLR1: MCAN0RS (Bit 4) */ -#define SCU_RESET_PRCLR1_MCAN0RS_Msk \ - (0x10UL) /*!< SCU_RESET PRCLR1: MCAN0RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRCLR1_DACRS_Pos \ - (5UL) /*!< SCU_RESET PRCLR1: DACRS (Bit 5) */ -#define SCU_RESET_PRCLR1_DACRS_Msk \ - (0x20UL) /*!< SCU_RESET PRCLR1: DACRS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRCLR1_USIC1RS_Pos \ - (7UL) /*!< SCU_RESET PRCLR1: USIC1RS (Bit 7) */ -#define SCU_RESET_PRCLR1_USIC1RS_Msk \ - (0x80UL) /*!< SCU_RESET PRCLR1: USIC1RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRCLR1_PPORTSRS_Pos \ - (9UL) /*!< SCU_RESET PRCLR1: PPORTSRS (Bit 9) */ -#define SCU_RESET_PRCLR1_PPORTSRS_Msk \ - (0x200UL) /*!< SCU_RESET PRCLR1: PPORTSRS (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_RESET_PRSTAT2 ----------------------------- */ -#define SCU_RESET_PRSTAT2_WDTRS_Pos \ - (1UL) /*!< SCU_RESET PRSTAT2: WDTRS (Bit 1) */ -#define SCU_RESET_PRSTAT2_WDTRS_Msk \ - (0x2UL) /*!< SCU_RESET PRSTAT2: WDTRS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSTAT2_ETH0RS_Pos \ - (2UL) /*!< SCU_RESET PRSTAT2: ETH0RS (Bit 2) */ -#define SCU_RESET_PRSTAT2_ETH0RS_Msk \ - (0x4UL) /*!< SCU_RESET PRSTAT2: ETH0RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSTAT2_DMA0RS_Pos \ - (4UL) /*!< SCU_RESET PRSTAT2: DMA0RS (Bit 4) */ -#define SCU_RESET_PRSTAT2_DMA0RS_Msk \ - (0x10UL) /*!< SCU_RESET PRSTAT2: DMA0RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSTAT2_FCERS_Pos \ - (6UL) /*!< SCU_RESET PRSTAT2: FCERS (Bit 6) */ -#define SCU_RESET_PRSTAT2_FCERS_Msk \ - (0x40UL) /*!< SCU_RESET PRSTAT2: FCERS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSTAT2_USBRS_Pos \ - (7UL) /*!< SCU_RESET PRSTAT2: USBRS (Bit 7) */ -#define SCU_RESET_PRSTAT2_USBRS_Msk \ - (0x80UL) /*!< SCU_RESET PRSTAT2: USBRS (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_RESET_PRSET2 ------------------------------ */ -#define SCU_RESET_PRSET2_WDTRS_Pos \ - (1UL) /*!< SCU_RESET PRSET2: WDTRS (Bit 1) */ -#define SCU_RESET_PRSET2_WDTRS_Msk \ - (0x2UL) /*!< SCU_RESET PRSET2: WDTRS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSET2_ETH0RS_Pos \ - (2UL) /*!< SCU_RESET PRSET2: ETH0RS (Bit 2) */ -#define SCU_RESET_PRSET2_ETH0RS_Msk \ - (0x4UL) /*!< SCU_RESET PRSET2: ETH0RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSET2_DMA0RS_Pos \ - (4UL) /*!< SCU_RESET PRSET2: DMA0RS (Bit 4) */ -#define SCU_RESET_PRSET2_DMA0RS_Msk \ - (0x10UL) /*!< SCU_RESET PRSET2: DMA0RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSET2_FCERS_Pos \ - (6UL) /*!< SCU_RESET PRSET2: FCERS (Bit 6) */ -#define SCU_RESET_PRSET2_FCERS_Msk \ - (0x40UL) /*!< SCU_RESET PRSET2: FCERS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRSET2_USBRS_Pos \ - (7UL) /*!< SCU_RESET PRSET2: USBRS (Bit 7) */ -#define SCU_RESET_PRSET2_USBRS_Msk \ - (0x80UL) /*!< SCU_RESET PRSET2: USBRS (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SCU_RESET_PRCLR2 ------------------------------ */ -#define SCU_RESET_PRCLR2_WDTRS_Pos \ - (1UL) /*!< SCU_RESET PRCLR2: WDTRS (Bit 1) */ -#define SCU_RESET_PRCLR2_WDTRS_Msk \ - (0x2UL) /*!< SCU_RESET PRCLR2: WDTRS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRCLR2_ETH0RS_Pos \ - (2UL) /*!< SCU_RESET PRCLR2: ETH0RS (Bit 2) */ -#define SCU_RESET_PRCLR2_ETH0RS_Msk \ - (0x4UL) /*!< SCU_RESET PRCLR2: ETH0RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRCLR2_DMA0RS_Pos \ - (4UL) /*!< SCU_RESET PRCLR2: DMA0RS (Bit 4) */ -#define SCU_RESET_PRCLR2_DMA0RS_Msk \ - (0x10UL) /*!< SCU_RESET PRCLR2: DMA0RS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRCLR2_FCERS_Pos \ - (6UL) /*!< SCU_RESET PRCLR2: FCERS (Bit 6) */ -#define SCU_RESET_PRCLR2_FCERS_Msk \ - (0x40UL) /*!< SCU_RESET PRCLR2: FCERS (Bitfield-Mask: 0x01) */ -#define SCU_RESET_PRCLR2_USBRS_Pos \ - (7UL) /*!< SCU_RESET PRCLR2: USBRS (Bit 7) */ -#define SCU_RESET_PRCLR2_USBRS_Msk \ - (0x80UL) /*!< SCU_RESET PRCLR2: USBRS (Bitfield-Mask: 0x01) */ - -/* ================================================================================ */ -/* ================ Group 'LEDTS' Position & Mask ================ */ -/* ================================================================================ */ - -/* ---------------------------------- LEDTS_ID ---------------------------------- */ -#define LEDTS_ID_MOD_REV_Pos \ - (0UL) /*!< LEDTS ID: MOD_REV (Bit 0) */ -#define LEDTS_ID_MOD_REV_Msk \ - (0xffUL) /*!< LEDTS ID: MOD_REV (Bitfield-Mask: 0xff) */ -#define LEDTS_ID_MOD_TYPE_Pos \ - (8UL) /*!< LEDTS ID: MOD_TYPE (Bit 8) */ -#define LEDTS_ID_MOD_TYPE_Msk \ - (0xff00UL) /*!< LEDTS ID: MOD_TYPE (Bitfield-Mask: 0xff) */ -#define LEDTS_ID_MOD_NUMBER_Pos \ - (16UL) /*!< LEDTS ID: MOD_NUMBER (Bit 16) */ -#define LEDTS_ID_MOD_NUMBER_Msk \ - (0xffff0000UL) /*!< LEDTS ID: MOD_NUMBER (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- LEDTS_GLOBCTL ------------------------------- */ -#define LEDTS_GLOBCTL_TS_EN_Pos \ - (0UL) /*!< LEDTS GLOBCTL: TS_EN (Bit 0) */ -#define LEDTS_GLOBCTL_TS_EN_Msk \ - (0x1UL) /*!< LEDTS GLOBCTL: TS_EN (Bitfield-Mask: 0x01) */ -#define LEDTS_GLOBCTL_LD_EN_Pos \ - (1UL) /*!< LEDTS GLOBCTL: LD_EN (Bit 1) */ -#define LEDTS_GLOBCTL_LD_EN_Msk \ - (0x2UL) /*!< LEDTS GLOBCTL: LD_EN (Bitfield-Mask: 0x01) */ -#define LEDTS_GLOBCTL_CMTR_Pos \ - (2UL) /*!< LEDTS GLOBCTL: CMTR (Bit 2) */ -#define LEDTS_GLOBCTL_CMTR_Msk \ - (0x4UL) /*!< LEDTS GLOBCTL: CMTR (Bitfield-Mask: 0x01) */ -#define LEDTS_GLOBCTL_ENSYNC_Pos \ - (3UL) /*!< LEDTS GLOBCTL: ENSYNC (Bit 3) */ -#define LEDTS_GLOBCTL_ENSYNC_Msk \ - (0x8UL) /*!< LEDTS GLOBCTL: ENSYNC (Bitfield-Mask: 0x01) */ -#define LEDTS_GLOBCTL_SUSCFG_Pos \ - (8UL) /*!< LEDTS GLOBCTL: SUSCFG (Bit 8) */ -#define LEDTS_GLOBCTL_SUSCFG_Msk \ - (0x100UL) /*!< LEDTS GLOBCTL: SUSCFG (Bitfield-Mask: 0x01) */ -#define LEDTS_GLOBCTL_MASKVAL_Pos \ - (9UL) /*!< LEDTS GLOBCTL: MASKVAL (Bit 9) */ -#define LEDTS_GLOBCTL_MASKVAL_Msk \ - (0xe00UL) /*!< LEDTS GLOBCTL: MASKVAL (Bitfield-Mask: 0x07) */ -#define LEDTS_GLOBCTL_FENVAL_Pos \ - (12UL) /*!< LEDTS GLOBCTL: FENVAL (Bit 12) */ -#define LEDTS_GLOBCTL_FENVAL_Msk \ - (0x1000UL) /*!< LEDTS GLOBCTL: FENVAL (Bitfield-Mask: 0x01) */ -#define LEDTS_GLOBCTL_ITS_EN_Pos \ - (13UL) /*!< LEDTS GLOBCTL: ITS_EN (Bit 13) */ -#define LEDTS_GLOBCTL_ITS_EN_Msk \ - (0x2000UL) /*!< LEDTS GLOBCTL: ITS_EN (Bitfield-Mask: 0x01) */ -#define LEDTS_GLOBCTL_ITF_EN_Pos \ - (14UL) /*!< LEDTS GLOBCTL: ITF_EN (Bit 14) */ -#define LEDTS_GLOBCTL_ITF_EN_Msk \ - (0x4000UL) /*!< LEDTS GLOBCTL: ITF_EN (Bitfield-Mask: 0x01) */ -#define LEDTS_GLOBCTL_ITP_EN_Pos \ - (15UL) /*!< LEDTS GLOBCTL: ITP_EN (Bit 15) */ -#define LEDTS_GLOBCTL_ITP_EN_Msk \ - (0x8000UL) /*!< LEDTS GLOBCTL: ITP_EN (Bitfield-Mask: 0x01) */ -#define LEDTS_GLOBCTL_CLK_PS_Pos \ - (16UL) /*!< LEDTS GLOBCTL: CLK_PS (Bit 16) */ -#define LEDTS_GLOBCTL_CLK_PS_Msk \ - (0xffff0000UL) /*!< LEDTS GLOBCTL: CLK_PS (Bitfield-Mask: 0xffff) */ - -/* --------------------------------- LEDTS_FNCTL -------------------------------- */ -#define LEDTS_FNCTL_PADT_Pos \ - (0UL) /*!< LEDTS FNCTL: PADT (Bit 0) */ -#define LEDTS_FNCTL_PADT_Msk \ - (0x7UL) /*!< LEDTS FNCTL: PADT (Bitfield-Mask: 0x07) */ -#define LEDTS_FNCTL_PADTSW_Pos \ - (3UL) /*!< LEDTS FNCTL: PADTSW (Bit 3) */ -#define LEDTS_FNCTL_PADTSW_Msk \ - (0x8UL) /*!< LEDTS FNCTL: PADTSW (Bitfield-Mask: 0x01) */ -#define LEDTS_FNCTL_EPULL_Pos \ - (4UL) /*!< LEDTS FNCTL: EPULL (Bit 4) */ -#define LEDTS_FNCTL_EPULL_Msk \ - (0x10UL) /*!< LEDTS FNCTL: EPULL (Bitfield-Mask: 0x01) */ -#define LEDTS_FNCTL_FNCOL_Pos \ - (5UL) /*!< LEDTS FNCTL: FNCOL (Bit 5) */ -#define LEDTS_FNCTL_FNCOL_Msk \ - (0xe0UL) /*!< LEDTS FNCTL: FNCOL (Bitfield-Mask: 0x07) */ -#define LEDTS_FNCTL_ACCCNT_Pos \ - (16UL) /*!< LEDTS FNCTL: ACCCNT (Bit 16) */ -#define LEDTS_FNCTL_ACCCNT_Msk \ - (0xf0000UL) /*!< LEDTS FNCTL: ACCCNT (Bitfield-Mask: 0x0f) */ -#define LEDTS_FNCTL_TSCCMP_Pos \ - (20UL) /*!< LEDTS FNCTL: TSCCMP (Bit 20) */ -#define LEDTS_FNCTL_TSCCMP_Msk \ - (0x100000UL) /*!< LEDTS FNCTL: TSCCMP (Bitfield-Mask: 0x01) */ -#define LEDTS_FNCTL_TSOEXT_Pos \ - (21UL) /*!< LEDTS FNCTL: TSOEXT (Bit 21) */ -#define LEDTS_FNCTL_TSOEXT_Msk \ - (0x600000UL) /*!< LEDTS FNCTL: TSOEXT (Bitfield-Mask: 0x03) */ -#define LEDTS_FNCTL_TSCTRR_Pos \ - (23UL) /*!< LEDTS FNCTL: TSCTRR (Bit 23) */ -#define LEDTS_FNCTL_TSCTRR_Msk \ - (0x800000UL) /*!< LEDTS FNCTL: TSCTRR (Bitfield-Mask: 0x01) */ -#define LEDTS_FNCTL_TSCTRSAT_Pos \ - (24UL) /*!< LEDTS FNCTL: TSCTRSAT (Bit 24) */ -#define LEDTS_FNCTL_TSCTRSAT_Msk \ - (0x1000000UL) /*!< LEDTS FNCTL: TSCTRSAT (Bitfield-Mask: 0x01) */ -#define LEDTS_FNCTL_NR_TSIN_Pos \ - (25UL) /*!< LEDTS FNCTL: NR_TSIN (Bit 25) */ -#define LEDTS_FNCTL_NR_TSIN_Msk \ - (0xe000000UL) /*!< LEDTS FNCTL: NR_TSIN (Bitfield-Mask: 0x07) */ -#define LEDTS_FNCTL_COLLEV_Pos \ - (28UL) /*!< LEDTS FNCTL: COLLEV (Bit 28) */ -#define LEDTS_FNCTL_COLLEV_Msk \ - (0x10000000UL) /*!< LEDTS FNCTL: COLLEV (Bitfield-Mask: 0x01) */ -#define LEDTS_FNCTL_NR_LEDCOL_Pos \ - (29UL) /*!< LEDTS FNCTL: NR_LEDCOL (Bit 29) */ -#define LEDTS_FNCTL_NR_LEDCOL_Msk \ - (0xe0000000UL) /*!< LEDTS FNCTL: NR_LEDCOL (Bitfield-Mask: 0x07) */ - -/* --------------------------------- LEDTS_EVFR --------------------------------- */ -#define LEDTS_EVFR_TSF_Pos (0UL) /*!< LEDTS EVFR: TSF (Bit 0) */ -#define LEDTS_EVFR_TSF_Msk \ - (0x1UL) /*!< LEDTS EVFR: TSF (Bitfield-Mask: 0x01) */ -#define LEDTS_EVFR_TFF_Pos (1UL) /*!< LEDTS EVFR: TFF (Bit 1) */ -#define LEDTS_EVFR_TFF_Msk \ - (0x2UL) /*!< LEDTS EVFR: TFF (Bitfield-Mask: 0x01) */ -#define LEDTS_EVFR_TPF_Pos (2UL) /*!< LEDTS EVFR: TPF (Bit 2) */ -#define LEDTS_EVFR_TPF_Msk \ - (0x4UL) /*!< LEDTS EVFR: TPF (Bitfield-Mask: 0x01) */ -#define LEDTS_EVFR_TSCTROVF_Pos \ - (3UL) /*!< LEDTS EVFR: TSCTROVF (Bit 3) */ -#define LEDTS_EVFR_TSCTROVF_Msk \ - (0x8UL) /*!< LEDTS EVFR: TSCTROVF (Bitfield-Mask: 0x01) */ -#define LEDTS_EVFR_CTSF_Pos \ - (16UL) /*!< LEDTS EVFR: CTSF (Bit 16) */ -#define LEDTS_EVFR_CTSF_Msk \ - (0x10000UL) /*!< LEDTS EVFR: CTSF (Bitfield-Mask: 0x01) */ -#define LEDTS_EVFR_CTFF_Pos \ - (17UL) /*!< LEDTS EVFR: CTFF (Bit 17) */ -#define LEDTS_EVFR_CTFF_Msk \ - (0x20000UL) /*!< LEDTS EVFR: CTFF (Bitfield-Mask: 0x01) */ -#define LEDTS_EVFR_CTPF_Pos \ - (18UL) /*!< LEDTS EVFR: CTPF (Bit 18) */ -#define LEDTS_EVFR_CTPF_Msk \ - (0x40000UL) /*!< LEDTS EVFR: CTPF (Bitfield-Mask: 0x01) */ - -/* --------------------------------- LEDTS_TSVAL -------------------------------- */ -#define LEDTS_TSVAL_TSCTRVALR_Pos \ - (0UL) /*!< LEDTS TSVAL: TSCTRVALR (Bit 0) */ -#define LEDTS_TSVAL_TSCTRVALR_Msk \ - (0xffffUL) /*!< LEDTS TSVAL: TSCTRVALR (Bitfield-Mask: 0xffff) */ -#define LEDTS_TSVAL_TSCTRVAL_Pos \ - (16UL) /*!< LEDTS TSVAL: TSCTRVAL (Bit 16) */ -#define LEDTS_TSVAL_TSCTRVAL_Msk \ - (0xffff0000UL) /*!< LEDTS TSVAL: TSCTRVAL (Bitfield-Mask: 0xffff) */ - -/* --------------------------------- LEDTS_LINE0 -------------------------------- */ -#define LEDTS_LINE0_LINE_0_Pos \ - (0UL) /*!< LEDTS LINE0: LINE_0 (Bit 0) */ -#define LEDTS_LINE0_LINE_0_Msk \ - (0xffUL) /*!< LEDTS LINE0: LINE_0 (Bitfield-Mask: 0xff) */ -#define LEDTS_LINE0_LINE_1_Pos \ - (8UL) /*!< LEDTS LINE0: LINE_1 (Bit 8) */ -#define LEDTS_LINE0_LINE_1_Msk \ - (0xff00UL) /*!< LEDTS LINE0: LINE_1 (Bitfield-Mask: 0xff) */ -#define LEDTS_LINE0_LINE_2_Pos \ - (16UL) /*!< LEDTS LINE0: LINE_2 (Bit 16) */ -#define LEDTS_LINE0_LINE_2_Msk \ - (0xff0000UL) /*!< LEDTS LINE0: LINE_2 (Bitfield-Mask: 0xff) */ -#define LEDTS_LINE0_LINE_3_Pos \ - (24UL) /*!< LEDTS LINE0: LINE_3 (Bit 24) */ -#define LEDTS_LINE0_LINE_3_Msk \ - (0xff000000UL) /*!< LEDTS LINE0: LINE_3 (Bitfield-Mask: 0xff) */ - -/* --------------------------------- LEDTS_LINE1 -------------------------------- */ -#define LEDTS_LINE1_LINE_4_Pos \ - (0UL) /*!< LEDTS LINE1: LINE_4 (Bit 0) */ -#define LEDTS_LINE1_LINE_4_Msk \ - (0xffUL) /*!< LEDTS LINE1: LINE_4 (Bitfield-Mask: 0xff) */ -#define LEDTS_LINE1_LINE_5_Pos \ - (8UL) /*!< LEDTS LINE1: LINE_5 (Bit 8) */ -#define LEDTS_LINE1_LINE_5_Msk \ - (0xff00UL) /*!< LEDTS LINE1: LINE_5 (Bitfield-Mask: 0xff) */ -#define LEDTS_LINE1_LINE_6_Pos \ - (16UL) /*!< LEDTS LINE1: LINE_6 (Bit 16) */ -#define LEDTS_LINE1_LINE_6_Msk \ - (0xff0000UL) /*!< LEDTS LINE1: LINE_6 (Bitfield-Mask: 0xff) */ -#define LEDTS_LINE1_LINE_A_Pos \ - (24UL) /*!< LEDTS LINE1: LINE_A (Bit 24) */ -#define LEDTS_LINE1_LINE_A_Msk \ - (0xff000000UL) /*!< LEDTS LINE1: LINE_A (Bitfield-Mask: 0xff) */ - -/* -------------------------------- LEDTS_LDCMP0 -------------------------------- */ -#define LEDTS_LDCMP0_CMP_LD0_Pos \ - (0UL) /*!< LEDTS LDCMP0: CMP_LD0 (Bit 0) */ -#define LEDTS_LDCMP0_CMP_LD0_Msk \ - (0xffUL) /*!< LEDTS LDCMP0: CMP_LD0 (Bitfield-Mask: 0xff) */ -#define LEDTS_LDCMP0_CMP_LD1_Pos \ - (8UL) /*!< LEDTS LDCMP0: CMP_LD1 (Bit 8) */ -#define LEDTS_LDCMP0_CMP_LD1_Msk \ - (0xff00UL) /*!< LEDTS LDCMP0: CMP_LD1 (Bitfield-Mask: 0xff) */ -#define LEDTS_LDCMP0_CMP_LD2_Pos \ - (16UL) /*!< LEDTS LDCMP0: CMP_LD2 (Bit 16) */ -#define LEDTS_LDCMP0_CMP_LD2_Msk \ - (0xff0000UL) /*!< LEDTS LDCMP0: CMP_LD2 (Bitfield-Mask: 0xff) */ -#define LEDTS_LDCMP0_CMP_LD3_Pos \ - (24UL) /*!< LEDTS LDCMP0: CMP_LD3 (Bit 24) */ -#define LEDTS_LDCMP0_CMP_LD3_Msk \ - (0xff000000UL) /*!< LEDTS LDCMP0: CMP_LD3 (Bitfield-Mask: 0xff) */ - -/* -------------------------------- LEDTS_LDCMP1 -------------------------------- */ -#define LEDTS_LDCMP1_CMP_LD4_Pos \ - (0UL) /*!< LEDTS LDCMP1: CMP_LD4 (Bit 0) */ -#define LEDTS_LDCMP1_CMP_LD4_Msk \ - (0xffUL) /*!< LEDTS LDCMP1: CMP_LD4 (Bitfield-Mask: 0xff) */ -#define LEDTS_LDCMP1_CMP_LD5_Pos \ - (8UL) /*!< LEDTS LDCMP1: CMP_LD5 (Bit 8) */ -#define LEDTS_LDCMP1_CMP_LD5_Msk \ - (0xff00UL) /*!< LEDTS LDCMP1: CMP_LD5 (Bitfield-Mask: 0xff) */ -#define LEDTS_LDCMP1_CMP_LD6_Pos \ - (16UL) /*!< LEDTS LDCMP1: CMP_LD6 (Bit 16) */ -#define LEDTS_LDCMP1_CMP_LD6_Msk \ - (0xff0000UL) /*!< LEDTS LDCMP1: CMP_LD6 (Bitfield-Mask: 0xff) */ -#define LEDTS_LDCMP1_CMP_LDA_TSCOM_Pos \ - (24UL) /*!< LEDTS LDCMP1: CMP_LDA_TSCOM (Bit 24) */ -#define LEDTS_LDCMP1_CMP_LDA_TSCOM_Msk \ - (0xff000000UL) /*!< LEDTS LDCMP1: CMP_LDA_TSCOM (Bitfield-Mask: 0xff) */ - -/* -------------------------------- LEDTS_TSCMP0 -------------------------------- */ -#define LEDTS_TSCMP0_CMP_TS0_Pos \ - (0UL) /*!< LEDTS TSCMP0: CMP_TS0 (Bit 0) */ -#define LEDTS_TSCMP0_CMP_TS0_Msk \ - (0xffUL) /*!< LEDTS TSCMP0: CMP_TS0 (Bitfield-Mask: 0xff) */ -#define LEDTS_TSCMP0_CMP_TS1_Pos \ - (8UL) /*!< LEDTS TSCMP0: CMP_TS1 (Bit 8) */ -#define LEDTS_TSCMP0_CMP_TS1_Msk \ - (0xff00UL) /*!< LEDTS TSCMP0: CMP_TS1 (Bitfield-Mask: 0xff) */ -#define LEDTS_TSCMP0_CMP_TS2_Pos \ - (16UL) /*!< LEDTS TSCMP0: CMP_TS2 (Bit 16) */ -#define LEDTS_TSCMP0_CMP_TS2_Msk \ - (0xff0000UL) /*!< LEDTS TSCMP0: CMP_TS2 (Bitfield-Mask: 0xff) */ -#define LEDTS_TSCMP0_CMP_TS3_Pos \ - (24UL) /*!< LEDTS TSCMP0: CMP_TS3 (Bit 24) */ -#define LEDTS_TSCMP0_CMP_TS3_Msk \ - (0xff000000UL) /*!< LEDTS TSCMP0: CMP_TS3 (Bitfield-Mask: 0xff) */ - -/* -------------------------------- LEDTS_TSCMP1 -------------------------------- */ -#define LEDTS_TSCMP1_CMP_TS4_Pos \ - (0UL) /*!< LEDTS TSCMP1: CMP_TS4 (Bit 0) */ -#define LEDTS_TSCMP1_CMP_TS4_Msk \ - (0xffUL) /*!< LEDTS TSCMP1: CMP_TS4 (Bitfield-Mask: 0xff) */ -#define LEDTS_TSCMP1_CMP_TS5_Pos \ - (8UL) /*!< LEDTS TSCMP1: CMP_TS5 (Bit 8) */ -#define LEDTS_TSCMP1_CMP_TS5_Msk \ - (0xff00UL) /*!< LEDTS TSCMP1: CMP_TS5 (Bitfield-Mask: 0xff) */ -#define LEDTS_TSCMP1_CMP_TS6_Pos \ - (16UL) /*!< LEDTS TSCMP1: CMP_TS6 (Bit 16) */ -#define LEDTS_TSCMP1_CMP_TS6_Msk \ - (0xff0000UL) /*!< LEDTS TSCMP1: CMP_TS6 (Bitfield-Mask: 0xff) */ -#define LEDTS_TSCMP1_CMP_TS7_Pos \ - (24UL) /*!< LEDTS TSCMP1: CMP_TS7 (Bit 24) */ -#define LEDTS_TSCMP1_CMP_TS7_Msk \ - (0xff000000UL) /*!< LEDTS TSCMP1: CMP_TS7 (Bitfield-Mask: 0xff) */ - -/* ================================================================================ */ -/* ================ struct 'ETH0_CON' Position & Mask ================ */ -/* ================================================================================ */ - -/* ------------------------------ ETH0_CON_ETH0_CON ----------------------------- */ -#define ETH_CON_RXD0_Pos (0UL) /*!< ETH0_CON ETH0_CON: RXD0 (Bit 0) */ -#define ETH_CON_RXD0_Msk (0x3UL) /*!< ETH0_CON ETH0_CON: RXD0 (Bitfield-Mask: 0x03) */ -#define ETH_CON_RXD1_Pos (2UL) /*!< ETH0_CON ETH0_CON: RXD1 (Bit 2) */ -#define ETH_CON_RXD1_Msk (0xcUL) /*!< ETH0_CON ETH0_CON: RXD1 (Bitfield-Mask: 0x03) */ -#define ETH_CON_RXD2_Pos (4UL) /*!< ETH0_CON ETH0_CON: RXD2 (Bit 4) */ -#define ETH_CON_RXD2_Msk \ - (0x30UL) /*!< ETH0_CON ETH0_CON: RXD2 (Bitfield-Mask: 0x03) */ -#define ETH_CON_RXD3_Pos (6UL) /*!< ETH0_CON ETH0_CON: RXD3 (Bit 6) */ -#define ETH_CON_RXD3_Msk \ - (0xc0UL) /*!< ETH0_CON ETH0_CON: RXD3 (Bitfield-Mask: 0x03) */ -#define ETH_CON_CLK_RMII_Pos \ - (8UL) /*!< ETH0_CON ETH0_CON: CLK_RMII (Bit 8) */ -#define ETH_CON_CLK_RMII_Msk \ - (0x300UL) /*!< ETH0_CON ETH0_CON: CLK_RMII (Bitfield-Mask: 0x03) */ -#define ETH_CON_CRS_DV_Pos \ - (10UL) /*!< ETH0_CON ETH0_CON: CRS_DV (Bit 10) */ -#define ETH_CON_CRS_DV_Msk \ - (0xc00UL) /*!< ETH0_CON ETH0_CON: CRS_DV (Bitfield-Mask: 0x03) */ -#define ETH_CON_CRS_Pos (12UL) /*!< ETH0_CON ETH0_CON: CRS (Bit 12) */ -#define ETH_CON_CRS_Msk \ - (0x3000UL) /*!< ETH0_CON ETH0_CON: CRS (Bitfield-Mask: 0x03) */ -#define ETH_CON_RXER_Pos (14UL) /*!< ETH0_CON ETH0_CON: RXER (Bit 14) */ -#define ETH_CON_RXER_Msk \ - (0xc000UL) /*!< ETH0_CON ETH0_CON: RXER (Bitfield-Mask: 0x03) */ -#define ETH_CON_COL_Pos (16UL) /*!< ETH0_CON ETH0_CON: COL (Bit 16) */ -#define ETH_CON_COL_Msk \ - (0x30000UL) /*!< ETH0_CON ETH0_CON: COL (Bitfield-Mask: 0x03) */ -#define ETH_CON_CLK_TX_Pos \ - (18UL) /*!< ETH0_CON ETH0_CON: CLK_TX (Bit 18) */ -#define ETH_CON_CLK_TX_Msk \ - (0xc0000UL) /*!< ETH0_CON ETH0_CON: CLK_TX (Bitfield-Mask: 0x03) */ -#define ETH_CON_MDIO_Pos (22UL) /*!< ETH0_CON ETH0_CON: MDIO (Bit 22) */ -#define ETH_CON_MDIO_Msk \ - (0xc00000UL) /*!< ETH0_CON ETH0_CON: MDIO (Bitfield-Mask: 0x03) */ -#define ETH_CON_INFSEL_Pos \ - (26UL) /*!< ETH0_CON ETH0_CON: INFSEL (Bit 26) */ -#define ETH_CON_INFSEL_Msk \ - (0x4000000UL) /*!< ETH0_CON ETH0_CON: INFSEL (Bitfield-Mask: 0x01) */ - -/* ================================================================================ */ -/* ================ Group 'ETH' Position & Mask ================ */ -/* ================================================================================ */ - -/* ---------------------------- ETH_MAC_CONFIGURATION --------------------------- */ -#define ETH_MAC_CONFIGURATION_PRELEN_Pos \ - (0UL) /*!< ETH MAC_CONFIGURATION: PRELEN (Bit 0) */ -#define ETH_MAC_CONFIGURATION_PRELEN_Msk \ - (0x3UL) /*!< ETH MAC_CONFIGURATION: PRELEN (Bitfield-Mask: 0x03) */ -#define ETH_MAC_CONFIGURATION_RE_Pos \ - (2UL) /*!< ETH MAC_CONFIGURATION: RE (Bit 2) */ -#define ETH_MAC_CONFIGURATION_RE_Msk \ - (0x4UL) /*!< ETH MAC_CONFIGURATION: RE (Bitfield-Mask: 0x01) */ -#define ETH_MAC_CONFIGURATION_TE_Pos \ - (3UL) /*!< ETH MAC_CONFIGURATION: TE (Bit 3) */ -#define ETH_MAC_CONFIGURATION_TE_Msk \ - (0x8UL) /*!< ETH MAC_CONFIGURATION: TE (Bitfield-Mask: 0x01) */ -#define ETH_MAC_CONFIGURATION_DC_Pos \ - (4UL) /*!< ETH MAC_CONFIGURATION: DC (Bit 4) */ -#define ETH_MAC_CONFIGURATION_DC_Msk \ - (0x10UL) /*!< ETH MAC_CONFIGURATION: DC (Bitfield-Mask: 0x01) */ -#define ETH_MAC_CONFIGURATION_BL_Pos \ - (5UL) /*!< ETH MAC_CONFIGURATION: BL (Bit 5) */ -#define ETH_MAC_CONFIGURATION_BL_Msk \ - (0x60UL) /*!< ETH MAC_CONFIGURATION: BL (Bitfield-Mask: 0x03) */ -#define ETH_MAC_CONFIGURATION_ACS_Pos \ - (7UL) /*!< ETH MAC_CONFIGURATION: ACS (Bit 7) */ -#define ETH_MAC_CONFIGURATION_ACS_Msk \ - (0x80UL) /*!< ETH MAC_CONFIGURATION: ACS (Bitfield-Mask: 0x01) */ -#define ETH_MAC_CONFIGURATION_DR_Pos \ - (9UL) /*!< ETH MAC_CONFIGURATION: DR (Bit 9) */ -#define ETH_MAC_CONFIGURATION_DR_Msk \ - (0x200UL) /*!< ETH MAC_CONFIGURATION: DR (Bitfield-Mask: 0x01) */ -#define ETH_MAC_CONFIGURATION_IPC_Pos \ - (10UL) /*!< ETH MAC_CONFIGURATION: IPC (Bit 10) */ -#define ETH_MAC_CONFIGURATION_IPC_Msk \ - (0x400UL) /*!< ETH MAC_CONFIGURATION: IPC (Bitfield-Mask: 0x01) */ -#define ETH_MAC_CONFIGURATION_DM_Pos \ - (11UL) /*!< ETH MAC_CONFIGURATION: DM (Bit 11) */ -#define ETH_MAC_CONFIGURATION_DM_Msk \ - (0x800UL) /*!< ETH MAC_CONFIGURATION: DM (Bitfield-Mask: 0x01) */ -#define ETH_MAC_CONFIGURATION_LM_Pos \ - (12UL) /*!< ETH MAC_CONFIGURATION: LM (Bit 12) */ -#define ETH_MAC_CONFIGURATION_LM_Msk \ - (0x1000UL) /*!< ETH MAC_CONFIGURATION: LM (Bitfield-Mask: 0x01) */ -#define ETH_MAC_CONFIGURATION_DO_Pos \ - (13UL) /*!< ETH MAC_CONFIGURATION: DO (Bit 13) */ -#define ETH_MAC_CONFIGURATION_DO_Msk \ - (0x2000UL) /*!< ETH MAC_CONFIGURATION: DO (Bitfield-Mask: 0x01) */ -#define ETH_MAC_CONFIGURATION_FES_Pos \ - (14UL) /*!< ETH MAC_CONFIGURATION: FES (Bit 14) */ -#define ETH_MAC_CONFIGURATION_FES_Msk \ - (0x4000UL) /*!< ETH MAC_CONFIGURATION: FES (Bitfield-Mask: 0x01) */ -#define ETH_MAC_CONFIGURATION_DCRS_Pos \ - (16UL) /*!< ETH MAC_CONFIGURATION: DCRS (Bit 16) */ -#define ETH_MAC_CONFIGURATION_DCRS_Msk \ - (0x10000UL) /*!< ETH MAC_CONFIGURATION: DCRS (Bitfield-Mask: 0x01) */ -#define ETH_MAC_CONFIGURATION_IFG_Pos \ - (17UL) /*!< ETH MAC_CONFIGURATION: IFG (Bit 17) */ -#define ETH_MAC_CONFIGURATION_IFG_Msk \ - (0xe0000UL) /*!< ETH MAC_CONFIGURATION: IFG (Bitfield-Mask: 0x07) */ -#define ETH_MAC_CONFIGURATION_JE_Pos \ - (20UL) /*!< ETH MAC_CONFIGURATION: JE (Bit 20) */ -#define ETH_MAC_CONFIGURATION_JE_Msk \ - (0x100000UL) /*!< ETH MAC_CONFIGURATION: JE (Bitfield-Mask: 0x01) */ -#define ETH_MAC_CONFIGURATION_BE_Pos \ - (21UL) /*!< ETH MAC_CONFIGURATION: BE (Bit 21) */ -#define ETH_MAC_CONFIGURATION_BE_Msk \ - (0x200000UL) /*!< ETH MAC_CONFIGURATION: BE (Bitfield-Mask: 0x01) */ -#define ETH_MAC_CONFIGURATION_JD_Pos \ - (22UL) /*!< ETH MAC_CONFIGURATION: JD (Bit 22) */ -#define ETH_MAC_CONFIGURATION_JD_Msk \ - (0x400000UL) /*!< ETH MAC_CONFIGURATION: JD (Bitfield-Mask: 0x01) */ -#define ETH_MAC_CONFIGURATION_WD_Pos \ - (23UL) /*!< ETH MAC_CONFIGURATION: WD (Bit 23) */ -#define ETH_MAC_CONFIGURATION_WD_Msk \ - (0x800000UL) /*!< ETH MAC_CONFIGURATION: WD (Bitfield-Mask: 0x01) */ -#define ETH_MAC_CONFIGURATION_TC_Pos \ - (24UL) /*!< ETH MAC_CONFIGURATION: TC (Bit 24) */ -#define ETH_MAC_CONFIGURATION_TC_Msk \ - (0x1000000UL) /*!< ETH MAC_CONFIGURATION: TC (Bitfield-Mask: 0x01) */ -#define ETH_MAC_CONFIGURATION_CST_Pos \ - (25UL) /*!< ETH MAC_CONFIGURATION: CST (Bit 25) */ -#define ETH_MAC_CONFIGURATION_CST_Msk \ - (0x2000000UL) /*!< ETH MAC_CONFIGURATION: CST (Bitfield-Mask: 0x01) */ -#define ETH_MAC_CONFIGURATION_TWOKPE_Pos \ - (27UL) /*!< ETH MAC_CONFIGURATION: TWOKPE (Bit 27) */ -#define ETH_MAC_CONFIGURATION_TWOKPE_Msk \ - (0x8000000UL) /*!< ETH MAC_CONFIGURATION: TWOKPE (Bitfield-Mask: 0x01) */ -#define ETH_MAC_CONFIGURATION_SARC_Pos \ - (28UL) /*!< ETH MAC_CONFIGURATION: SARC (Bit 28) */ -#define ETH_MAC_CONFIGURATION_SARC_Msk \ - (0x70000000UL) /*!< ETH MAC_CONFIGURATION: SARC (Bitfield-Mask: 0x07) */ - -/* ---------------------------- ETH_MAC_FRAME_FILTER ---------------------------- */ -#define ETH_MAC_FRAME_FILTER_PR_Pos \ - (0UL) /*!< ETH MAC_FRAME_FILTER: PR (Bit 0) */ -#define ETH_MAC_FRAME_FILTER_PR_Msk \ - (0x1UL) /*!< ETH MAC_FRAME_FILTER: PR (Bitfield-Mask: 0x01) */ -#define ETH_MAC_FRAME_FILTER_HUC_Pos \ - (1UL) /*!< ETH MAC_FRAME_FILTER: HUC (Bit 1) */ -#define ETH_MAC_FRAME_FILTER_HUC_Msk \ - (0x2UL) /*!< ETH MAC_FRAME_FILTER: HUC (Bitfield-Mask: 0x01) */ -#define ETH_MAC_FRAME_FILTER_HMC_Pos \ - (2UL) /*!< ETH MAC_FRAME_FILTER: HMC (Bit 2) */ -#define ETH_MAC_FRAME_FILTER_HMC_Msk \ - (0x4UL) /*!< ETH MAC_FRAME_FILTER: HMC (Bitfield-Mask: 0x01) */ -#define ETH_MAC_FRAME_FILTER_DAIF_Pos \ - (3UL) /*!< ETH MAC_FRAME_FILTER: DAIF (Bit 3) */ -#define ETH_MAC_FRAME_FILTER_DAIF_Msk \ - (0x8UL) /*!< ETH MAC_FRAME_FILTER: DAIF (Bitfield-Mask: 0x01) */ -#define ETH_MAC_FRAME_FILTER_PM_Pos \ - (4UL) /*!< ETH MAC_FRAME_FILTER: PM (Bit 4) */ -#define ETH_MAC_FRAME_FILTER_PM_Msk \ - (0x10UL) /*!< ETH MAC_FRAME_FILTER: PM (Bitfield-Mask: 0x01) */ -#define ETH_MAC_FRAME_FILTER_DBF_Pos \ - (5UL) /*!< ETH MAC_FRAME_FILTER: DBF (Bit 5) */ -#define ETH_MAC_FRAME_FILTER_DBF_Msk \ - (0x20UL) /*!< ETH MAC_FRAME_FILTER: DBF (Bitfield-Mask: 0x01) */ -#define ETH_MAC_FRAME_FILTER_PCF_Pos \ - (6UL) /*!< ETH MAC_FRAME_FILTER: PCF (Bit 6) */ -#define ETH_MAC_FRAME_FILTER_PCF_Msk \ - (0xc0UL) /*!< ETH MAC_FRAME_FILTER: PCF (Bitfield-Mask: 0x03) */ -#define ETH_MAC_FRAME_FILTER_SAIF_Pos \ - (8UL) /*!< ETH MAC_FRAME_FILTER: SAIF (Bit 8) */ -#define ETH_MAC_FRAME_FILTER_SAIF_Msk \ - (0x100UL) /*!< ETH MAC_FRAME_FILTER: SAIF (Bitfield-Mask: 0x01) */ -#define ETH_MAC_FRAME_FILTER_SAF_Pos \ - (9UL) /*!< ETH MAC_FRAME_FILTER: SAF (Bit 9) */ -#define ETH_MAC_FRAME_FILTER_SAF_Msk \ - (0x200UL) /*!< ETH MAC_FRAME_FILTER: SAF (Bitfield-Mask: 0x01) */ -#define ETH_MAC_FRAME_FILTER_HPF_Pos \ - (10UL) /*!< ETH MAC_FRAME_FILTER: HPF (Bit 10) */ -#define ETH_MAC_FRAME_FILTER_HPF_Msk \ - (0x400UL) /*!< ETH MAC_FRAME_FILTER: HPF (Bitfield-Mask: 0x01) */ -#define ETH_MAC_FRAME_FILTER_VTFE_Pos \ - (16UL) /*!< ETH MAC_FRAME_FILTER: VTFE (Bit 16) */ -#define ETH_MAC_FRAME_FILTER_VTFE_Msk \ - (0x10000UL) /*!< ETH MAC_FRAME_FILTER: VTFE (Bitfield-Mask: 0x01) */ -#define ETH_MAC_FRAME_FILTER_IPFE_Pos \ - (20UL) /*!< ETH MAC_FRAME_FILTER: IPFE (Bit 20) */ -#define ETH_MAC_FRAME_FILTER_IPFE_Msk \ - (0x100000UL) /*!< ETH MAC_FRAME_FILTER: IPFE (Bitfield-Mask: 0x01) */ -#define ETH_MAC_FRAME_FILTER_DNTU_Pos \ - (21UL) /*!< ETH MAC_FRAME_FILTER: DNTU (Bit 21) */ -#define ETH_MAC_FRAME_FILTER_DNTU_Msk \ - (0x200000UL) /*!< ETH MAC_FRAME_FILTER: DNTU (Bitfield-Mask: 0x01) */ -#define ETH_MAC_FRAME_FILTER_RA_Pos \ - (31UL) /*!< ETH MAC_FRAME_FILTER: RA (Bit 31) */ -#define ETH_MAC_FRAME_FILTER_RA_Msk \ - (0x80000000UL) /*!< ETH MAC_FRAME_FILTER: RA (Bitfield-Mask: 0x01) */ - -/* ----------------------------- ETH_HASH_TABLE_HIGH ---------------------------- */ -#define ETH_HASH_TABLE_HIGH_HTH_Pos \ - (0UL) /*!< ETH HASH_TABLE_HIGH: HTH (Bit 0) */ -#define ETH_HASH_TABLE_HIGH_HTH_Msk \ - (0xffffffffUL) /*!< ETH HASH_TABLE_HIGH: HTH (Bitfield-Mask: 0xffffffff) */ - -/* ----------------------------- ETH_HASH_TABLE_LOW ----------------------------- */ -#define ETH_HASH_TABLE_LOW_HTL_Pos \ - (0UL) /*!< ETH HASH_TABLE_LOW: HTL (Bit 0) */ -#define ETH_HASH_TABLE_LOW_HTL_Msk \ - (0xffffffffUL) /*!< ETH HASH_TABLE_LOW: HTL (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------ ETH_GMII_ADDRESS ------------------------------ */ -#define ETH_GMII_ADDRESS_MB_Pos \ - (0UL) /*!< ETH GMII_ADDRESS: MB (Bit 0) */ -#define ETH_GMII_ADDRESS_MB_Msk \ - (0x1UL) /*!< ETH GMII_ADDRESS: MB (Bitfield-Mask: 0x01) */ -#define ETH_GMII_ADDRESS_MW_Pos \ - (1UL) /*!< ETH GMII_ADDRESS: MW (Bit 1) */ -#define ETH_GMII_ADDRESS_MW_Msk \ - (0x2UL) /*!< ETH GMII_ADDRESS: MW (Bitfield-Mask: 0x01) */ -#define ETH_GMII_ADDRESS_CR_Pos \ - (2UL) /*!< ETH GMII_ADDRESS: CR (Bit 2) */ -#define ETH_GMII_ADDRESS_CR_Msk \ - (0x3cUL) /*!< ETH GMII_ADDRESS: CR (Bitfield-Mask: 0x0f) */ -#define ETH_GMII_ADDRESS_MR_Pos \ - (6UL) /*!< ETH GMII_ADDRESS: MR (Bit 6) */ -#define ETH_GMII_ADDRESS_MR_Msk \ - (0x7c0UL) /*!< ETH GMII_ADDRESS: MR (Bitfield-Mask: 0x1f) */ -#define ETH_GMII_ADDRESS_PA_Pos \ - (11UL) /*!< ETH GMII_ADDRESS: PA (Bit 11) */ -#define ETH_GMII_ADDRESS_PA_Msk \ - (0xf800UL) /*!< ETH GMII_ADDRESS: PA (Bitfield-Mask: 0x1f) */ - -/* -------------------------------- ETH_GMII_DATA ------------------------------- */ -#define ETH_GMII_DATA_MD_Pos \ - (0UL) /*!< ETH GMII_DATA: MD (Bit 0) */ -#define ETH_GMII_DATA_MD_Msk \ - (0xffffUL) /*!< ETH GMII_DATA: MD (Bitfield-Mask: 0xffff) */ - -/* ------------------------------ ETH_FLOW_CONTROL ------------------------------ */ -#define ETH_FLOW_CONTROL_FCA_BPA_Pos \ - (0UL) /*!< ETH FLOW_CONTROL: FCA_BPA (Bit 0) */ -#define ETH_FLOW_CONTROL_FCA_BPA_Msk \ - (0x1UL) /*!< ETH FLOW_CONTROL: FCA_BPA (Bitfield-Mask: 0x01) */ -#define ETH_FLOW_CONTROL_TFE_Pos \ - (1UL) /*!< ETH FLOW_CONTROL: TFE (Bit 1) */ -#define ETH_FLOW_CONTROL_TFE_Msk \ - (0x2UL) /*!< ETH FLOW_CONTROL: TFE (Bitfield-Mask: 0x01) */ -#define ETH_FLOW_CONTROL_RFE_Pos \ - (2UL) /*!< ETH FLOW_CONTROL: RFE (Bit 2) */ -#define ETH_FLOW_CONTROL_RFE_Msk \ - (0x4UL) /*!< ETH FLOW_CONTROL: RFE (Bitfield-Mask: 0x01) */ -#define ETH_FLOW_CONTROL_UP_Pos \ - (3UL) /*!< ETH FLOW_CONTROL: UP (Bit 3) */ -#define ETH_FLOW_CONTROL_UP_Msk \ - (0x8UL) /*!< ETH FLOW_CONTROL: UP (Bitfield-Mask: 0x01) */ -#define ETH_FLOW_CONTROL_PLT_Pos \ - (4UL) /*!< ETH FLOW_CONTROL: PLT (Bit 4) */ -#define ETH_FLOW_CONTROL_PLT_Msk \ - (0x30UL) /*!< ETH FLOW_CONTROL: PLT (Bitfield-Mask: 0x03) */ -#define ETH_FLOW_CONTROL_DZPQ_Pos \ - (7UL) /*!< ETH FLOW_CONTROL: DZPQ (Bit 7) */ -#define ETH_FLOW_CONTROL_DZPQ_Msk \ - (0x80UL) /*!< ETH FLOW_CONTROL: DZPQ (Bitfield-Mask: 0x01) */ -#define ETH_FLOW_CONTROL_PT_Pos \ - (16UL) /*!< ETH FLOW_CONTROL: PT (Bit 16) */ -#define ETH_FLOW_CONTROL_PT_Msk \ - (0xffff0000UL) /*!< ETH FLOW_CONTROL: PT (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- ETH_VLAN_TAG -------------------------------- */ -#define ETH_VLAN_TAG_VL_Pos \ - (0UL) /*!< ETH VLAN_TAG: VL (Bit 0) */ -#define ETH_VLAN_TAG_VL_Msk \ - (0xffffUL) /*!< ETH VLAN_TAG: VL (Bitfield-Mask: 0xffff) */ -#define ETH_VLAN_TAG_ETV_Pos \ - (16UL) /*!< ETH VLAN_TAG: ETV (Bit 16) */ -#define ETH_VLAN_TAG_ETV_Msk \ - (0x10000UL) /*!< ETH VLAN_TAG: ETV (Bitfield-Mask: 0x01) */ -#define ETH_VLAN_TAG_VTIM_Pos \ - (17UL) /*!< ETH VLAN_TAG: VTIM (Bit 17) */ -#define ETH_VLAN_TAG_VTIM_Msk \ - (0x20000UL) /*!< ETH VLAN_TAG: VTIM (Bitfield-Mask: 0x01) */ -#define ETH_VLAN_TAG_ESVL_Pos \ - (18UL) /*!< ETH VLAN_TAG: ESVL (Bit 18) */ -#define ETH_VLAN_TAG_ESVL_Msk \ - (0x40000UL) /*!< ETH VLAN_TAG: ESVL (Bitfield-Mask: 0x01) */ -#define ETH_VLAN_TAG_VTHM_Pos \ - (19UL) /*!< ETH VLAN_TAG: VTHM (Bit 19) */ -#define ETH_VLAN_TAG_VTHM_Msk \ - (0x80000UL) /*!< ETH VLAN_TAG: VTHM (Bitfield-Mask: 0x01) */ - -/* --------------------------------- ETH_VERSION -------------------------------- */ -#define ETH_VERSION_SNPSVER_Pos \ - (0UL) /*!< ETH VERSION: SNPSVER (Bit 0) */ -#define ETH_VERSION_SNPSVER_Msk \ - (0xffUL) /*!< ETH VERSION: SNPSVER (Bitfield-Mask: 0xff) */ -#define ETH_VERSION_USERVER_Pos \ - (8UL) /*!< ETH VERSION: USERVER (Bit 8) */ -#define ETH_VERSION_USERVER_Msk \ - (0xff00UL) /*!< ETH VERSION: USERVER (Bitfield-Mask: 0xff) */ - -/* ---------------------------------- ETH_DEBUG --------------------------------- */ -#define ETH_DEBUG_RPESTS_Pos \ - (0UL) /*!< ETH DEBUG: RPESTS (Bit 0) */ -#define ETH_DEBUG_RPESTS_Msk \ - (0x1UL) /*!< ETH DEBUG: RPESTS (Bitfield-Mask: 0x01) */ -#define ETH_DEBUG_RFCFCSTS_Pos \ - (1UL) /*!< ETH DEBUG: RFCFCSTS (Bit 1) */ -#define ETH_DEBUG_RFCFCSTS_Msk \ - (0x6UL) /*!< ETH DEBUG: RFCFCSTS (Bitfield-Mask: 0x03) */ -#define ETH_DEBUG_RWCSTS_Pos \ - (4UL) /*!< ETH DEBUG: RWCSTS (Bit 4) */ -#define ETH_DEBUG_RWCSTS_Msk \ - (0x10UL) /*!< ETH DEBUG: RWCSTS (Bitfield-Mask: 0x01) */ -#define ETH_DEBUG_RRCSTS_Pos \ - (5UL) /*!< ETH DEBUG: RRCSTS (Bit 5) */ -#define ETH_DEBUG_RRCSTS_Msk \ - (0x60UL) /*!< ETH DEBUG: RRCSTS (Bitfield-Mask: 0x03) */ -#define ETH_DEBUG_RXFSTS_Pos \ - (8UL) /*!< ETH DEBUG: RXFSTS (Bit 8) */ -#define ETH_DEBUG_RXFSTS_Msk \ - (0x300UL) /*!< ETH DEBUG: RXFSTS (Bitfield-Mask: 0x03) */ -#define ETH_DEBUG_TPESTS_Pos \ - (16UL) /*!< ETH DEBUG: TPESTS (Bit 16) */ -#define ETH_DEBUG_TPESTS_Msk \ - (0x10000UL) /*!< ETH DEBUG: TPESTS (Bitfield-Mask: 0x01) */ -#define ETH_DEBUG_TFCSTS_Pos \ - (17UL) /*!< ETH DEBUG: TFCSTS (Bit 17) */ -#define ETH_DEBUG_TFCSTS_Msk \ - (0x60000UL) /*!< ETH DEBUG: TFCSTS (Bitfield-Mask: 0x03) */ -#define ETH_DEBUG_TXPAUSED_Pos \ - (19UL) /*!< ETH DEBUG: TXPAUSED (Bit 19) */ -#define ETH_DEBUG_TXPAUSED_Msk \ - (0x80000UL) /*!< ETH DEBUG: TXPAUSED (Bitfield-Mask: 0x01) */ -#define ETH_DEBUG_TRCSTS_Pos \ - (20UL) /*!< ETH DEBUG: TRCSTS (Bit 20) */ -#define ETH_DEBUG_TRCSTS_Msk \ - (0x300000UL) /*!< ETH DEBUG: TRCSTS (Bitfield-Mask: 0x03) */ -#define ETH_DEBUG_TWCSTS_Pos \ - (22UL) /*!< ETH DEBUG: TWCSTS (Bit 22) */ -#define ETH_DEBUG_TWCSTS_Msk \ - (0x400000UL) /*!< ETH DEBUG: TWCSTS (Bitfield-Mask: 0x01) */ -#define ETH_DEBUG_TXFSTS_Pos \ - (24UL) /*!< ETH DEBUG: TXFSTS (Bit 24) */ -#define ETH_DEBUG_TXFSTS_Msk \ - (0x1000000UL) /*!< ETH DEBUG: TXFSTS (Bitfield-Mask: 0x01) */ -#define ETH_DEBUG_TXSTSFSTS_Pos \ - (25UL) /*!< ETH DEBUG: TXSTSFSTS (Bit 25) */ -#define ETH_DEBUG_TXSTSFSTS_Msk \ - (0x2000000UL) /*!< ETH DEBUG: TXSTSFSTS (Bitfield-Mask: 0x01) */ - -/* ----------------------- ETH_REMOTE_WAKE_UP_FRAME_FILTER ---------------------- */ -#define ETH_REMOTE_WAKE_UP_FRAME_FILTER_WKUPFRMFTR_Pos \ - (0UL) /*!< ETH REMOTE_WAKE_UP_FRAME_FILTER: WKUPFRMFTR (Bit 0) */ -#define ETH_REMOTE_WAKE_UP_FRAME_FILTER_WKUPFRMFTR_Msk \ - (0xffffffffUL) /*!< ETH REMOTE_WAKE_UP_FRAME_FILTER: WKUPFRMFTR (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------- ETH_PMT_CONTROL_STATUS --------------------------- */ -#define ETH_PMT_CONTROL_STATUS_PWRDWN_Pos \ - (0UL) /*!< ETH PMT_CONTROL_STATUS: PWRDWN (Bit 0) */ -#define ETH_PMT_CONTROL_STATUS_PWRDWN_Msk \ - (0x1UL) /*!< ETH PMT_CONTROL_STATUS: PWRDWN (Bitfield-Mask: 0x01) */ -#define ETH_PMT_CONTROL_STATUS_MGKPKTEN_Pos \ - (1UL) /*!< ETH PMT_CONTROL_STATUS: MGKPKTEN (Bit 1) */ -#define ETH_PMT_CONTROL_STATUS_MGKPKTEN_Msk \ - (0x2UL) /*!< ETH PMT_CONTROL_STATUS: MGKPKTEN (Bitfield-Mask: 0x01) */ -#define ETH_PMT_CONTROL_STATUS_RWKPKTEN_Pos \ - (2UL) /*!< ETH PMT_CONTROL_STATUS: RWKPKTEN (Bit 2) */ -#define ETH_PMT_CONTROL_STATUS_RWKPKTEN_Msk \ - (0x4UL) /*!< ETH PMT_CONTROL_STATUS: RWKPKTEN (Bitfield-Mask: 0x01) */ -#define ETH_PMT_CONTROL_STATUS_MGKPRCVD_Pos \ - (5UL) /*!< ETH PMT_CONTROL_STATUS: MGKPRCVD (Bit 5) */ -#define ETH_PMT_CONTROL_STATUS_MGKPRCVD_Msk \ - (0x20UL) /*!< ETH PMT_CONTROL_STATUS: MGKPRCVD (Bitfield-Mask: 0x01) */ -#define ETH_PMT_CONTROL_STATUS_RWKPRCVD_Pos \ - (6UL) /*!< ETH PMT_CONTROL_STATUS: RWKPRCVD (Bit 6) */ -#define ETH_PMT_CONTROL_STATUS_RWKPRCVD_Msk \ - (0x40UL) /*!< ETH PMT_CONTROL_STATUS: RWKPRCVD (Bitfield-Mask: 0x01) */ -#define ETH_PMT_CONTROL_STATUS_GLBLUCAST_Pos \ - (9UL) /*!< ETH PMT_CONTROL_STATUS: GLBLUCAST (Bit 9) */ -#define ETH_PMT_CONTROL_STATUS_GLBLUCAST_Msk \ - (0x200UL) /*!< ETH PMT_CONTROL_STATUS: GLBLUCAST (Bitfield-Mask: 0x01) */ -#define ETH_PMT_CONTROL_STATUS_RWKFILTRST_Pos \ - (31UL) /*!< ETH PMT_CONTROL_STATUS: RWKFILTRST (Bit 31) */ -#define ETH_PMT_CONTROL_STATUS_RWKFILTRST_Msk \ - (0x80000000UL) /*!< ETH PMT_CONTROL_STATUS: RWKFILTRST (Bitfield-Mask: 0x01) */ - -/* ---------------------------- ETH_INTERRUPT_STATUS ---------------------------- */ -#define ETH_INTERRUPT_STATUS_PMTIS_Pos \ - (3UL) /*!< ETH INTERRUPT_STATUS: PMTIS (Bit 3) */ -#define ETH_INTERRUPT_STATUS_PMTIS_Msk \ - (0x8UL) /*!< ETH INTERRUPT_STATUS: PMTIS (Bitfield-Mask: 0x01) */ -#define ETH_INTERRUPT_STATUS_MMCIS_Pos \ - (4UL) /*!< ETH INTERRUPT_STATUS: MMCIS (Bit 4) */ -#define ETH_INTERRUPT_STATUS_MMCIS_Msk \ - (0x10UL) /*!< ETH INTERRUPT_STATUS: MMCIS (Bitfield-Mask: 0x01) */ -#define ETH_INTERRUPT_STATUS_MMCRXIS_Pos \ - (5UL) /*!< ETH INTERRUPT_STATUS: MMCRXIS (Bit 5) */ -#define ETH_INTERRUPT_STATUS_MMCRXIS_Msk \ - (0x20UL) /*!< ETH INTERRUPT_STATUS: MMCRXIS (Bitfield-Mask: 0x01) */ -#define ETH_INTERRUPT_STATUS_MMCTXIS_Pos \ - (6UL) /*!< ETH INTERRUPT_STATUS: MMCTXIS (Bit 6) */ -#define ETH_INTERRUPT_STATUS_MMCTXIS_Msk \ - (0x40UL) /*!< ETH INTERRUPT_STATUS: MMCTXIS (Bitfield-Mask: 0x01) */ -#define ETH_INTERRUPT_STATUS_MMCRXIPIS_Pos \ - (7UL) /*!< ETH INTERRUPT_STATUS: MMCRXIPIS (Bit 7) */ -#define ETH_INTERRUPT_STATUS_MMCRXIPIS_Msk \ - (0x80UL) /*!< ETH INTERRUPT_STATUS: MMCRXIPIS (Bitfield-Mask: 0x01) */ -#define ETH_INTERRUPT_STATUS_TSIS_Pos \ - (9UL) /*!< ETH INTERRUPT_STATUS: TSIS (Bit 9) */ -#define ETH_INTERRUPT_STATUS_TSIS_Msk \ - (0x200UL) /*!< ETH INTERRUPT_STATUS: TSIS (Bitfield-Mask: 0x01) */ - -/* ----------------------------- ETH_INTERRUPT_MASK ----------------------------- */ -#define ETH_INTERRUPT_MASK_PMTIM_Pos \ - (3UL) /*!< ETH INTERRUPT_MASK: PMTIM (Bit 3) */ -#define ETH_INTERRUPT_MASK_PMTIM_Msk \ - (0x8UL) /*!< ETH INTERRUPT_MASK: PMTIM (Bitfield-Mask: 0x01) */ -#define ETH_INTERRUPT_MASK_TSIM_Pos \ - (9UL) /*!< ETH INTERRUPT_MASK: TSIM (Bit 9) */ -#define ETH_INTERRUPT_MASK_TSIM_Msk \ - (0x200UL) /*!< ETH INTERRUPT_MASK: TSIM (Bitfield-Mask: 0x01) */ - -/* ---------------------------- ETH_MAC_ADDRESS0_HIGH --------------------------- */ -#define ETH_MAC_ADDRESS0_HIGH_ADDRHI_Pos \ - (0UL) /*!< ETH MAC_ADDRESS0_HIGH: ADDRHI (Bit 0) */ -#define ETH_MAC_ADDRESS0_HIGH_ADDRHI_Msk \ - (0xffffUL) /*!< ETH MAC_ADDRESS0_HIGH: ADDRHI (Bitfield-Mask: 0xffff) */ -#define ETH_MAC_ADDRESS0_HIGH_AE_Pos \ - (31UL) /*!< ETH MAC_ADDRESS0_HIGH: AE (Bit 31) */ -#define ETH_MAC_ADDRESS0_HIGH_AE_Msk \ - (0x80000000UL) /*!< ETH MAC_ADDRESS0_HIGH: AE (Bitfield-Mask: 0x01) */ - -/* ---------------------------- ETH_MAC_ADDRESS0_LOW ---------------------------- */ -#define ETH_MAC_ADDRESS0_LOW_ADDRLO_Pos \ - (0UL) /*!< ETH MAC_ADDRESS0_LOW: ADDRLO (Bit 0) */ -#define ETH_MAC_ADDRESS0_LOW_ADDRLO_Msk \ - (0xffffffffUL) /*!< ETH MAC_ADDRESS0_LOW: ADDRLO (Bitfield-Mask: 0xffffffff) */ - -/* ---------------------------- ETH_MAC_ADDRESS1_HIGH --------------------------- */ -#define ETH_MAC_ADDRESS1_HIGH_ADDRHI_Pos \ - (0UL) /*!< ETH MAC_ADDRESS1_HIGH: ADDRHI (Bit 0) */ -#define ETH_MAC_ADDRESS1_HIGH_ADDRHI_Msk \ - (0xffffUL) /*!< ETH MAC_ADDRESS1_HIGH: ADDRHI (Bitfield-Mask: 0xffff) */ -#define ETH_MAC_ADDRESS1_HIGH_MBC_Pos \ - (24UL) /*!< ETH MAC_ADDRESS1_HIGH: MBC (Bit 24) */ -#define ETH_MAC_ADDRESS1_HIGH_MBC_Msk \ - (0x3f000000UL) /*!< ETH MAC_ADDRESS1_HIGH: MBC (Bitfield-Mask: 0x3f) */ -#define ETH_MAC_ADDRESS1_HIGH_SA_Pos \ - (30UL) /*!< ETH MAC_ADDRESS1_HIGH: SA (Bit 30) */ -#define ETH_MAC_ADDRESS1_HIGH_SA_Msk \ - (0x40000000UL) /*!< ETH MAC_ADDRESS1_HIGH: SA (Bitfield-Mask: 0x01) */ -#define ETH_MAC_ADDRESS1_HIGH_AE_Pos \ - (31UL) /*!< ETH MAC_ADDRESS1_HIGH: AE (Bit 31) */ -#define ETH_MAC_ADDRESS1_HIGH_AE_Msk \ - (0x80000000UL) /*!< ETH MAC_ADDRESS1_HIGH: AE (Bitfield-Mask: 0x01) */ - -/* ---------------------------- ETH_MAC_ADDRESS1_LOW ---------------------------- */ -#define ETH_MAC_ADDRESS1_LOW_ADDRLO_Pos \ - (0UL) /*!< ETH MAC_ADDRESS1_LOW: ADDRLO (Bit 0) */ -#define ETH_MAC_ADDRESS1_LOW_ADDRLO_Msk \ - (0xffffffffUL) /*!< ETH MAC_ADDRESS1_LOW: ADDRLO (Bitfield-Mask: 0xffffffff) */ - -/* ---------------------------- ETH_MAC_ADDRESS2_HIGH --------------------------- */ -#define ETH_MAC_ADDRESS2_HIGH_ADDRHI_Pos \ - (0UL) /*!< ETH MAC_ADDRESS2_HIGH: ADDRHI (Bit 0) */ -#define ETH_MAC_ADDRESS2_HIGH_ADDRHI_Msk \ - (0xffffUL) /*!< ETH MAC_ADDRESS2_HIGH: ADDRHI (Bitfield-Mask: 0xffff) */ -#define ETH_MAC_ADDRESS2_HIGH_MBC_Pos \ - (24UL) /*!< ETH MAC_ADDRESS2_HIGH: MBC (Bit 24) */ -#define ETH_MAC_ADDRESS2_HIGH_MBC_Msk \ - (0x3f000000UL) /*!< ETH MAC_ADDRESS2_HIGH: MBC (Bitfield-Mask: 0x3f) */ -#define ETH_MAC_ADDRESS2_HIGH_SA_Pos \ - (30UL) /*!< ETH MAC_ADDRESS2_HIGH: SA (Bit 30) */ -#define ETH_MAC_ADDRESS2_HIGH_SA_Msk \ - (0x40000000UL) /*!< ETH MAC_ADDRESS2_HIGH: SA (Bitfield-Mask: 0x01) */ -#define ETH_MAC_ADDRESS2_HIGH_AE_Pos \ - (31UL) /*!< ETH MAC_ADDRESS2_HIGH: AE (Bit 31) */ -#define ETH_MAC_ADDRESS2_HIGH_AE_Msk \ - (0x80000000UL) /*!< ETH MAC_ADDRESS2_HIGH: AE (Bitfield-Mask: 0x01) */ - -/* ---------------------------- ETH_MAC_ADDRESS2_LOW ---------------------------- */ -#define ETH_MAC_ADDRESS2_LOW_ADDRLO_Pos \ - (0UL) /*!< ETH MAC_ADDRESS2_LOW: ADDRLO (Bit 0) */ -#define ETH_MAC_ADDRESS2_LOW_ADDRLO_Msk \ - (0xffffffffUL) /*!< ETH MAC_ADDRESS2_LOW: ADDRLO (Bitfield-Mask: 0xffffffff) */ - -/* ---------------------------- ETH_MAC_ADDRESS3_HIGH --------------------------- */ -#define ETH_MAC_ADDRESS3_HIGH_ADDRHI_Pos \ - (0UL) /*!< ETH MAC_ADDRESS3_HIGH: ADDRHI (Bit 0) */ -#define ETH_MAC_ADDRESS3_HIGH_ADDRHI_Msk \ - (0xffffUL) /*!< ETH MAC_ADDRESS3_HIGH: ADDRHI (Bitfield-Mask: 0xffff) */ -#define ETH_MAC_ADDRESS3_HIGH_MBC_Pos \ - (24UL) /*!< ETH MAC_ADDRESS3_HIGH: MBC (Bit 24) */ -#define ETH_MAC_ADDRESS3_HIGH_MBC_Msk \ - (0x3f000000UL) /*!< ETH MAC_ADDRESS3_HIGH: MBC (Bitfield-Mask: 0x3f) */ -#define ETH_MAC_ADDRESS3_HIGH_SA_Pos \ - (30UL) /*!< ETH MAC_ADDRESS3_HIGH: SA (Bit 30) */ -#define ETH_MAC_ADDRESS3_HIGH_SA_Msk \ - (0x40000000UL) /*!< ETH MAC_ADDRESS3_HIGH: SA (Bitfield-Mask: 0x01) */ -#define ETH_MAC_ADDRESS3_HIGH_AE_Pos \ - (31UL) /*!< ETH MAC_ADDRESS3_HIGH: AE (Bit 31) */ -#define ETH_MAC_ADDRESS3_HIGH_AE_Msk \ - (0x80000000UL) /*!< ETH MAC_ADDRESS3_HIGH: AE (Bitfield-Mask: 0x01) */ - -/* ---------------------------- ETH_MAC_ADDRESS3_LOW ---------------------------- */ -#define ETH_MAC_ADDRESS3_LOW_ADDRLO_Pos \ - (0UL) /*!< ETH MAC_ADDRESS3_LOW: ADDRLO (Bit 0) */ -#define ETH_MAC_ADDRESS3_LOW_ADDRLO_Msk \ - (0xffffffffUL) /*!< ETH MAC_ADDRESS3_LOW: ADDRLO (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------- ETH_MMC_CONTROL ------------------------------ */ -#define ETH_MMC_CONTROL_CNTRST_Pos \ - (0UL) /*!< ETH MMC_CONTROL: CNTRST (Bit 0) */ -#define ETH_MMC_CONTROL_CNTRST_Msk \ - (0x1UL) /*!< ETH MMC_CONTROL: CNTRST (Bitfield-Mask: 0x01) */ -#define ETH_MMC_CONTROL_CNTSTOPRO_Pos \ - (1UL) /*!< ETH MMC_CONTROL: CNTSTOPRO (Bit 1) */ -#define ETH_MMC_CONTROL_CNTSTOPRO_Msk \ - (0x2UL) /*!< ETH MMC_CONTROL: CNTSTOPRO (Bitfield-Mask: 0x01) */ -#define ETH_MMC_CONTROL_RSTONRD_Pos \ - (2UL) /*!< ETH MMC_CONTROL: RSTONRD (Bit 2) */ -#define ETH_MMC_CONTROL_RSTONRD_Msk \ - (0x4UL) /*!< ETH MMC_CONTROL: RSTONRD (Bitfield-Mask: 0x01) */ -#define ETH_MMC_CONTROL_CNTFREEZ_Pos \ - (3UL) /*!< ETH MMC_CONTROL: CNTFREEZ (Bit 3) */ -#define ETH_MMC_CONTROL_CNTFREEZ_Msk \ - (0x8UL) /*!< ETH MMC_CONTROL: CNTFREEZ (Bitfield-Mask: 0x01) */ -#define ETH_MMC_CONTROL_CNTPRST_Pos \ - (4UL) /*!< ETH MMC_CONTROL: CNTPRST (Bit 4) */ -#define ETH_MMC_CONTROL_CNTPRST_Msk \ - (0x10UL) /*!< ETH MMC_CONTROL: CNTPRST (Bitfield-Mask: 0x01) */ -#define ETH_MMC_CONTROL_CNTPRSTLVL_Pos \ - (5UL) /*!< ETH MMC_CONTROL: CNTPRSTLVL (Bit 5) */ -#define ETH_MMC_CONTROL_CNTPRSTLVL_Msk \ - (0x20UL) /*!< ETH MMC_CONTROL: CNTPRSTLVL (Bitfield-Mask: 0x01) */ -#define ETH_MMC_CONTROL_UCDBC_Pos \ - (8UL) /*!< ETH MMC_CONTROL: UCDBC (Bit 8) */ -#define ETH_MMC_CONTROL_UCDBC_Msk \ - (0x100UL) /*!< ETH MMC_CONTROL: UCDBC (Bitfield-Mask: 0x01) */ - -/* -------------------------- ETH_MMC_RECEIVE_INTERRUPT ------------------------- */ -#define ETH_MMC_RECEIVE_INTERRUPT_RXGBFRMIS_Pos \ - (0UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXGBFRMIS (Bit 0) */ -#define ETH_MMC_RECEIVE_INTERRUPT_RXGBFRMIS_Msk \ - (0x1UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXGBFRMIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_RECEIVE_INTERRUPT_RXGBOCTIS_Pos \ - (1UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXGBOCTIS (Bit 1) */ -#define ETH_MMC_RECEIVE_INTERRUPT_RXGBOCTIS_Msk \ - (0x2UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXGBOCTIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_RECEIVE_INTERRUPT_RXGOCTIS_Pos \ - (2UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXGOCTIS (Bit 2) */ -#define ETH_MMC_RECEIVE_INTERRUPT_RXGOCTIS_Msk \ - (0x4UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXGOCTIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_RECEIVE_INTERRUPT_RXBCGFIS_Pos \ - (3UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXBCGFIS (Bit 3) */ -#define ETH_MMC_RECEIVE_INTERRUPT_RXBCGFIS_Msk \ - (0x8UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXBCGFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_RECEIVE_INTERRUPT_RXMCGFIS_Pos \ - (4UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXMCGFIS (Bit 4) */ -#define ETH_MMC_RECEIVE_INTERRUPT_RXMCGFIS_Msk \ - (0x10UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXMCGFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_RECEIVE_INTERRUPT_RXCRCERFIS_Pos \ - (5UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXCRCERFIS (Bit 5) */ -#define ETH_MMC_RECEIVE_INTERRUPT_RXCRCERFIS_Msk \ - (0x20UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXCRCERFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_RECEIVE_INTERRUPT_RXALGNERFIS_Pos \ - (6UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXALGNERFIS (Bit 6) */ -#define ETH_MMC_RECEIVE_INTERRUPT_RXALGNERFIS_Msk \ - (0x40UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXALGNERFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_RECEIVE_INTERRUPT_RXRUNTFIS_Pos \ - (7UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXRUNTFIS (Bit 7) */ -#define ETH_MMC_RECEIVE_INTERRUPT_RXRUNTFIS_Msk \ - (0x80UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXRUNTFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_RECEIVE_INTERRUPT_RXJABERFIS_Pos \ - (8UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXJABERFIS (Bit 8) */ -#define ETH_MMC_RECEIVE_INTERRUPT_RXJABERFIS_Msk \ - (0x100UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXJABERFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_RECEIVE_INTERRUPT_RXUSIZEGFIS_Pos \ - (9UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXUSIZEGFIS (Bit 9) */ -#define ETH_MMC_RECEIVE_INTERRUPT_RXUSIZEGFIS_Msk \ - (0x200UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXUSIZEGFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_RECEIVE_INTERRUPT_RXOSIZEGFIS_Pos \ - (10UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXOSIZEGFIS (Bit 10) */ -#define ETH_MMC_RECEIVE_INTERRUPT_RXOSIZEGFIS_Msk \ - (0x400UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXOSIZEGFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_RECEIVE_INTERRUPT_RX64OCTGBFIS_Pos \ - (11UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RX64OCTGBFIS (Bit 11) */ -#define ETH_MMC_RECEIVE_INTERRUPT_RX64OCTGBFIS_Msk \ - (0x800UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RX64OCTGBFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_RECEIVE_INTERRUPT_RX65T127OCTGBFIS_Pos \ - (12UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RX65T127OCTGBFIS (Bit 12) */ -#define ETH_MMC_RECEIVE_INTERRUPT_RX65T127OCTGBFIS_Msk \ - (0x1000UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RX65T127OCTGBFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_RECEIVE_INTERRUPT_RX128T255OCTGBFIS_Pos \ - (13UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RX128T255OCTGBFIS (Bit 13) */ -#define ETH_MMC_RECEIVE_INTERRUPT_RX128T255OCTGBFIS_Msk \ - (0x2000UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RX128T255OCTGBFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_RECEIVE_INTERRUPT_RX256T511OCTGBFIS_Pos \ - (14UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RX256T511OCTGBFIS (Bit 14) */ -#define ETH_MMC_RECEIVE_INTERRUPT_RX256T511OCTGBFIS_Msk \ - (0x4000UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RX256T511OCTGBFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_RECEIVE_INTERRUPT_RX512T1023OCTGBFIS_Pos \ - (15UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RX512T1023OCTGBFIS (Bit 15) */ -#define ETH_MMC_RECEIVE_INTERRUPT_RX512T1023OCTGBFIS_Msk \ - (0x8000UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RX512T1023OCTGBFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_RECEIVE_INTERRUPT_RX1024TMAXOCTGBFIS_Pos \ - (16UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RX1024TMAXOCTGBFIS (Bit 16) */ -#define ETH_MMC_RECEIVE_INTERRUPT_RX1024TMAXOCTGBFIS_Msk \ - (0x10000UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RX1024TMAXOCTGBFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_RECEIVE_INTERRUPT_RXUCGFIS_Pos \ - (17UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXUCGFIS (Bit 17) */ -#define ETH_MMC_RECEIVE_INTERRUPT_RXUCGFIS_Msk \ - (0x20000UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXUCGFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_RECEIVE_INTERRUPT_RXLENERFIS_Pos \ - (18UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXLENERFIS (Bit 18) */ -#define ETH_MMC_RECEIVE_INTERRUPT_RXLENERFIS_Msk \ - (0x40000UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXLENERFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_RECEIVE_INTERRUPT_RXORANGEFIS_Pos \ - (19UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXORANGEFIS (Bit 19) */ -#define ETH_MMC_RECEIVE_INTERRUPT_RXORANGEFIS_Msk \ - (0x80000UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXORANGEFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_RECEIVE_INTERRUPT_RXPAUSFIS_Pos \ - (20UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXPAUSFIS (Bit 20) */ -#define ETH_MMC_RECEIVE_INTERRUPT_RXPAUSFIS_Msk \ - (0x100000UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXPAUSFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_RECEIVE_INTERRUPT_RXFOVFIS_Pos \ - (21UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXFOVFIS (Bit 21) */ -#define ETH_MMC_RECEIVE_INTERRUPT_RXFOVFIS_Msk \ - (0x200000UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXFOVFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_RECEIVE_INTERRUPT_RXVLANGBFIS_Pos \ - (22UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXVLANGBFIS (Bit 22) */ -#define ETH_MMC_RECEIVE_INTERRUPT_RXVLANGBFIS_Msk \ - (0x400000UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXVLANGBFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_RECEIVE_INTERRUPT_RXWDOGFIS_Pos \ - (23UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXWDOGFIS (Bit 23) */ -#define ETH_MMC_RECEIVE_INTERRUPT_RXWDOGFIS_Msk \ - (0x800000UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXWDOGFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_RECEIVE_INTERRUPT_RXRCVERRFIS_Pos \ - (24UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXRCVERRFIS (Bit 24) */ -#define ETH_MMC_RECEIVE_INTERRUPT_RXRCVERRFIS_Msk \ - (0x1000000UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXRCVERRFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_RECEIVE_INTERRUPT_RXCTRLFIS_Pos \ - (25UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXCTRLFIS (Bit 25) */ -#define ETH_MMC_RECEIVE_INTERRUPT_RXCTRLFIS_Msk \ - (0x2000000UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXCTRLFIS (Bitfield-Mask: 0x01) */ - -/* ------------------------- ETH_MMC_TRANSMIT_INTERRUPT ------------------------- */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TXGBOCTIS_Pos \ - (0UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXGBOCTIS (Bit 0) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TXGBOCTIS_Msk \ - (0x1UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXGBOCTIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TXGBFRMIS_Pos \ - (1UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXGBFRMIS (Bit 1) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TXGBFRMIS_Msk \ - (0x2UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXGBFRMIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TXBCGFIS_Pos \ - (2UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXBCGFIS (Bit 2) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TXBCGFIS_Msk \ - (0x4UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXBCGFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TXMCGFIS_Pos \ - (3UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXMCGFIS (Bit 3) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TXMCGFIS_Msk \ - (0x8UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXMCGFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TX64OCTGBFIS_Pos \ - (4UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TX64OCTGBFIS (Bit 4) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TX64OCTGBFIS_Msk \ - (0x10UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TX64OCTGBFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TX65T127OCTGBFIS_Pos \ - (5UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TX65T127OCTGBFIS (Bit 5) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TX65T127OCTGBFIS_Msk \ - (0x20UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TX65T127OCTGBFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TX128T255OCTGBFIS_Pos \ - (6UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TX128T255OCTGBFIS (Bit 6) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TX128T255OCTGBFIS_Msk \ - (0x40UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TX128T255OCTGBFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TX256T511OCTGBFIS_Pos \ - (7UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TX256T511OCTGBFIS (Bit 7) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TX256T511OCTGBFIS_Msk \ - (0x80UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TX256T511OCTGBFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TX512T1023OCTGBFIS_Pos \ - (8UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TX512T1023OCTGBFIS (Bit 8) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TX512T1023OCTGBFIS_Msk \ - (0x100UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TX512T1023OCTGBFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TX1024TMAXOCTGBFIS_Pos \ - (9UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TX1024TMAXOCTGBFIS (Bit 9) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TX1024TMAXOCTGBFIS_Msk \ - (0x200UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TX1024TMAXOCTGBFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TXUCGBFIS_Pos \ - (10UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXUCGBFIS (Bit 10) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TXUCGBFIS_Msk \ - (0x400UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXUCGBFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TXMCGBFIS_Pos \ - (11UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXMCGBFIS (Bit 11) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TXMCGBFIS_Msk \ - (0x800UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXMCGBFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TXBCGBFIS_Pos \ - (12UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXBCGBFIS (Bit 12) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TXBCGBFIS_Msk \ - (0x1000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXBCGBFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TXUFLOWERFIS_Pos \ - (13UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXUFLOWERFIS (Bit 13) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TXUFLOWERFIS_Msk \ - (0x2000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXUFLOWERFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TXSCOLGFIS_Pos \ - (14UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXSCOLGFIS (Bit 14) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TXSCOLGFIS_Msk \ - (0x4000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXSCOLGFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TXMCOLGFIS_Pos \ - (15UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXMCOLGFIS (Bit 15) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TXMCOLGFIS_Msk \ - (0x8000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXMCOLGFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TXDEFFIS_Pos \ - (16UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXDEFFIS (Bit 16) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TXDEFFIS_Msk \ - (0x10000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXDEFFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TXLATCOLFIS_Pos \ - (17UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXLATCOLFIS (Bit 17) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TXLATCOLFIS_Msk \ - (0x20000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXLATCOLFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TXEXCOLFIS_Pos \ - (18UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXEXCOLFIS (Bit 18) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TXEXCOLFIS_Msk \ - (0x40000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXEXCOLFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TXCARERFIS_Pos \ - (19UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXCARERFIS (Bit 19) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TXCARERFIS_Msk \ - (0x80000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXCARERFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TXGOCTIS_Pos \ - (20UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXGOCTIS (Bit 20) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TXGOCTIS_Msk \ - (0x100000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXGOCTIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TXGFRMIS_Pos \ - (21UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXGFRMIS (Bit 21) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TXGFRMIS_Msk \ - (0x200000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXGFRMIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TXEXDEFFIS_Pos \ - (22UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXEXDEFFIS (Bit 22) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TXEXDEFFIS_Msk \ - (0x400000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXEXDEFFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TXPAUSFIS_Pos \ - (23UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXPAUSFIS (Bit 23) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TXPAUSFIS_Msk \ - (0x800000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXPAUSFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TXVLANGFIS_Pos \ - (24UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXVLANGFIS (Bit 24) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TXVLANGFIS_Msk \ - (0x1000000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXVLANGFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TXOSIZEGFIS_Pos \ - (25UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXOSIZEGFIS (Bit 25) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_TXOSIZEGFIS_Msk \ - (0x2000000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXOSIZEGFIS (Bitfield-Mask: 0x01) */ - -/* ----------------------- ETH_MMC_RECEIVE_INTERRUPT_MASK ----------------------- */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBFRMIM_Pos \ - (0UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXGBFRMIM (Bit 0) */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBFRMIM_Msk \ - (0x1UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXGBFRMIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBOCTIM_Pos \ - (1UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXGBOCTIM (Bit 1) */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBOCTIM_Msk \ - (0x2UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXGBOCTIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGOCTIM_Pos \ - (2UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXGOCTIM (Bit 2) */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGOCTIM_Msk \ - (0x4UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXGOCTIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXBCGFIM_Pos \ - (3UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXBCGFIM (Bit 3) */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXBCGFIM_Msk \ - (0x8UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXBCGFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXMCGFIM_Pos \ - (4UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXMCGFIM (Bit 4) */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXMCGFIM_Msk \ - (0x10UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXMCGFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCRCERFIM_Pos \ - (5UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXCRCERFIM (Bit 5) */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCRCERFIM_Msk \ - (0x20UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXCRCERFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXALGNERFIM_Pos \ - (6UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXALGNERFIM (Bit 6) */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXALGNERFIM_Msk \ - (0x40UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXALGNERFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRUNTFIM_Pos \ - (7UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXRUNTFIM (Bit 7) */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRUNTFIM_Msk \ - (0x80UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXRUNTFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXJABERFIM_Pos \ - (8UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXJABERFIM (Bit 8) */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXJABERFIM_Msk \ - (0x100UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXJABERFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUSIZEGFIM_Pos \ - (9UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXUSIZEGFIM (Bit 9) */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUSIZEGFIM_Msk \ - (0x200UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXUSIZEGFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXOSIZEGFIM_Pos \ - (10UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXOSIZEGFIM (Bit 10) */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXOSIZEGFIM_Msk \ - (0x400UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXOSIZEGFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX64OCTGBFIM_Pos \ - (11UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX64OCTGBFIM (Bit 11) */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX64OCTGBFIM_Msk \ - (0x800UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX64OCTGBFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX65T127OCTGBFIM_Pos \ - (12UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX65T127OCTGBFIM (Bit 12) */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX65T127OCTGBFIM_Msk \ - (0x1000UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX65T127OCTGBFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX128T255OCTGBFIM_Pos \ - (13UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX128T255OCTGBFIM (Bit 13) */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX128T255OCTGBFIM_Msk \ - (0x2000UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX128T255OCTGBFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX256T511OCTGBFIM_Pos \ - (14UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX256T511OCTGBFIM (Bit 14) */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX256T511OCTGBFIM_Msk \ - (0x4000UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX256T511OCTGBFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX512T1023OCTGBFIM_Pos \ - (15UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX512T1023OCTGBFIM (Bit 15) */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX512T1023OCTGBFIM_Msk \ - (0x8000UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX512T1023OCTGBFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX1024TMAXOCTGBFIM_Pos \ - (16UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX1024TMAXOCTGBFIM (Bit 16) */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX1024TMAXOCTGBFIM_Msk \ - (0x10000UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX1024TMAXOCTGBFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUCGFIM_Pos \ - (17UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXUCGFIM (Bit 17) */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUCGFIM_Msk \ - (0x20000UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXUCGFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXLENERFIM_Pos \ - (18UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXLENERFIM (Bit 18) */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXLENERFIM_Msk \ - (0x40000UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXLENERFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXORANGEFIM_Pos \ - (19UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXORANGEFIM (Bit 19) */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXORANGEFIM_Msk \ - (0x80000UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXORANGEFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXPAUSFIM_Pos \ - (20UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXPAUSFIM (Bit 20) */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXPAUSFIM_Msk \ - (0x100000UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXPAUSFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXFOVFIM_Pos \ - (21UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXFOVFIM (Bit 21) */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXFOVFIM_Msk \ - (0x200000UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXFOVFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXVLANGBFIM_Pos \ - (22UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXVLANGBFIM (Bit 22) */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXVLANGBFIM_Msk \ - (0x400000UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXVLANGBFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXWDOGFIM_Pos \ - (23UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXWDOGFIM (Bit 23) */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXWDOGFIM_Msk \ - (0x800000UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXWDOGFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRCVERRFIM_Pos \ - (24UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXRCVERRFIM (Bit 24) */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRCVERRFIM_Msk \ - (0x1000000UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXRCVERRFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCTRLFIM_Pos \ - (25UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXCTRLFIM (Bit 25) */ -#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCTRLFIM_Msk \ - (0x2000000UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXCTRLFIM (Bitfield-Mask: 0x01) */ - -/* ----------------------- ETH_MMC_TRANSMIT_INTERRUPT_MASK ---------------------- */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBOCTIM_Pos \ - (0UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXGBOCTIM (Bit 0) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBOCTIM_Msk \ - (0x1UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXGBOCTIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBFRMIM_Pos \ - (1UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXGBFRMIM (Bit 1) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBFRMIM_Msk \ - (0x2UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXGBFRMIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGFIM_Pos \ - (2UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXBCGFIM (Bit 2) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGFIM_Msk \ - (0x4UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXBCGFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGFIM_Pos \ - (3UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXMCGFIM (Bit 3) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGFIM_Msk \ - (0x8UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXMCGFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX64OCTGBFIM_Pos \ - (4UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX64OCTGBFIM (Bit 4) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX64OCTGBFIM_Msk \ - (0x10UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX64OCTGBFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX65T127OCTGBFIM_Pos \ - (5UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX65T127OCTGBFIM (Bit 5) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX65T127OCTGBFIM_Msk \ - (0x20UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX65T127OCTGBFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX128T255OCTGBFIM_Pos \ - (6UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX128T255OCTGBFIM (Bit 6) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX128T255OCTGBFIM_Msk \ - (0x40UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX128T255OCTGBFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX256T511OCTGBFIM_Pos \ - (7UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX256T511OCTGBFIM (Bit 7) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX256T511OCTGBFIM_Msk \ - (0x80UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX256T511OCTGBFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX512T1023OCTGBFIM_Pos \ - (8UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX512T1023OCTGBFIM (Bit 8) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX512T1023OCTGBFIM_Msk \ - (0x100UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX512T1023OCTGBFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX1024TMAXOCTGBFIM_Pos \ - (9UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX1024TMAXOCTGBFIM (Bit 9) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX1024TMAXOCTGBFIM_Msk \ - (0x200UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX1024TMAXOCTGBFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUCGBFIM_Pos \ - (10UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXUCGBFIM (Bit 10) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUCGBFIM_Msk \ - (0x400UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXUCGBFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGBFIM_Pos \ - (11UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXMCGBFIM (Bit 11) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGBFIM_Msk \ - (0x800UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXMCGBFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGBFIM_Pos \ - (12UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXBCGBFIM (Bit 12) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGBFIM_Msk \ - (0x1000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXBCGBFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUFLOWERFIM_Pos \ - (13UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXUFLOWERFIM (Bit 13) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUFLOWERFIM_Msk \ - (0x2000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXUFLOWERFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXSCOLGFIM_Pos \ - (14UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXSCOLGFIM (Bit 14) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXSCOLGFIM_Msk \ - (0x4000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXSCOLGFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCOLGFIM_Pos \ - (15UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXMCOLGFIM (Bit 15) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCOLGFIM_Msk \ - (0x8000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXMCOLGFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXDEFFIM_Pos \ - (16UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXDEFFIM (Bit 16) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXDEFFIM_Msk \ - (0x10000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXDEFFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXLATCOLFIM_Pos \ - (17UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXLATCOLFIM (Bit 17) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXLATCOLFIM_Msk \ - (0x20000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXLATCOLFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXCOLFIM_Pos \ - (18UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXEXCOLFIM (Bit 18) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXCOLFIM_Msk \ - (0x40000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXEXCOLFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXCARERFIM_Pos \ - (19UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXCARERFIM (Bit 19) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXCARERFIM_Msk \ - (0x80000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXCARERFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGOCTIM_Pos \ - (20UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXGOCTIM (Bit 20) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGOCTIM_Msk \ - (0x100000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXGOCTIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGFRMIM_Pos \ - (21UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXGFRMIM (Bit 21) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGFRMIM_Msk \ - (0x200000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXGFRMIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXDEFFIM_Pos \ - (22UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXEXDEFFIM (Bit 22) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXDEFFIM_Msk \ - (0x400000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXEXDEFFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXPAUSFIM_Pos \ - (23UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXPAUSFIM (Bit 23) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXPAUSFIM_Msk \ - (0x800000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXPAUSFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXVLANGFIM_Pos \ - (24UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXVLANGFIM (Bit 24) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXVLANGFIM_Msk \ - (0x1000000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXVLANGFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXOSIZEGFIM_Pos \ - (25UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXOSIZEGFIM (Bit 25) */ -#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXOSIZEGFIM_Msk \ - (0x2000000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXOSIZEGFIM (Bitfield-Mask: 0x01) */ - -/* ------------------------- ETH_TX_OCTET_COUNT_GOOD_BAD ------------------------ */ -#define ETH_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_Pos \ - (0UL) /*!< ETH TX_OCTET_COUNT_GOOD_BAD: TXOCTGB (Bit 0) */ -#define ETH_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_Msk \ - (0xffffffffUL) /*!< ETH TX_OCTET_COUNT_GOOD_BAD: TXOCTGB (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------- ETH_TX_FRAME_COUNT_GOOD_BAD ------------------------ */ -#define ETH_TX_FRAME_COUNT_GOOD_BAD_TXFRMGB_Pos \ - (0UL) /*!< ETH TX_FRAME_COUNT_GOOD_BAD: TXFRMGB (Bit 0) */ -#define ETH_TX_FRAME_COUNT_GOOD_BAD_TXFRMGB_Msk \ - (0xffffffffUL) /*!< ETH TX_FRAME_COUNT_GOOD_BAD: TXFRMGB (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------ ETH_TX_BROADCAST_FRAMES_GOOD ------------------------ */ -#define ETH_TX_BROADCAST_FRAMES_GOOD_TXBCASTG_Pos \ - (0UL) /*!< ETH TX_BROADCAST_FRAMES_GOOD: TXBCASTG (Bit 0) */ -#define ETH_TX_BROADCAST_FRAMES_GOOD_TXBCASTG_Msk \ - (0xffffffffUL) /*!< ETH TX_BROADCAST_FRAMES_GOOD: TXBCASTG (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------ ETH_TX_MULTICAST_FRAMES_GOOD ------------------------ */ -#define ETH_TX_MULTICAST_FRAMES_GOOD_TXMCASTG_Pos \ - (0UL) /*!< ETH TX_MULTICAST_FRAMES_GOOD: TXMCASTG (Bit 0) */ -#define ETH_TX_MULTICAST_FRAMES_GOOD_TXMCASTG_Msk \ - (0xffffffffUL) /*!< ETH TX_MULTICAST_FRAMES_GOOD: TXMCASTG (Bitfield-Mask: 0xffffffff) */ - -/* ----------------------- ETH_TX_64OCTETS_FRAMES_GOOD_BAD ---------------------- */ -#define ETH_TX_64OCTETS_FRAMES_GOOD_BAD_TX64OCTGB_Pos \ - (0UL) /*!< ETH TX_64OCTETS_FRAMES_GOOD_BAD: TX64OCTGB (Bit 0) */ -#define ETH_TX_64OCTETS_FRAMES_GOOD_BAD_TX64OCTGB_Msk \ - (0xffffffffUL) /*!< ETH TX_64OCTETS_FRAMES_GOOD_BAD: TX64OCTGB (Bitfield-Mask: 0xffffffff) */ - -/* -------------------- ETH_TX_65TO127OCTETS_FRAMES_GOOD_BAD -------------------- */ -#define ETH_TX_65TO127OCTETS_FRAMES_GOOD_BAD_TX65_127OCTGB_Pos \ - (0UL) /*!< ETH TX_65TO127OCTETS_FRAMES_GOOD_BAD: TX65_127OCTGB (Bit 0) */ -#define ETH_TX_65TO127OCTETS_FRAMES_GOOD_BAD_TX65_127OCTGB_Msk \ - (0xffffffffUL) /*!< ETH TX_65TO127OCTETS_FRAMES_GOOD_BAD: TX65_127OCTGB (Bitfield-Mask: \ - 0xffffffff) */ - -/* -------------------- ETH_TX_128TO255OCTETS_FRAMES_GOOD_BAD ------------------- */ -#define ETH_TX_128TO255OCTETS_FRAMES_GOOD_BAD_TX128_255OCTGB_Pos \ - (0UL) /*!< ETH TX_128TO255OCTETS_FRAMES_GOOD_BAD: TX128_255OCTGB (Bit 0) */ -#define ETH_TX_128TO255OCTETS_FRAMES_GOOD_BAD_TX128_255OCTGB_Msk \ - (0xffffffffUL) /*!< ETH TX_128TO255OCTETS_FRAMES_GOOD_BAD: TX128_255OCTGB (Bitfield-Mask: \ - 0xffffffff) */ - -/* -------------------- ETH_TX_256TO511OCTETS_FRAMES_GOOD_BAD ------------------- */ -#define ETH_TX_256TO511OCTETS_FRAMES_GOOD_BAD_TX256_511OCTGB_Pos \ - (0UL) /*!< ETH TX_256TO511OCTETS_FRAMES_GOOD_BAD: TX256_511OCTGB (Bit 0) */ -#define ETH_TX_256TO511OCTETS_FRAMES_GOOD_BAD_TX256_511OCTGB_Msk \ - (0xffffffffUL) /*!< ETH TX_256TO511OCTETS_FRAMES_GOOD_BAD: TX256_511OCTGB (Bitfield-Mask: \ - 0xffffffff) */ - -/* ------------------- ETH_TX_512TO1023OCTETS_FRAMES_GOOD_BAD ------------------- */ -#define ETH_TX_512TO1023OCTETS_FRAMES_GOOD_BAD_TX512_1023OCTGB_Pos \ - (0UL) /*!< ETH TX_512TO1023OCTETS_FRAMES_GOOD_BAD: TX512_1023OCTGB (Bit 0) */ -#define ETH_TX_512TO1023OCTETS_FRAMES_GOOD_BAD_TX512_1023OCTGB_Msk \ - (0xffffffffUL) /*!< ETH TX_512TO1023OCTETS_FRAMES_GOOD_BAD: TX512_1023OCTGB (Bitfield-Mask: \ - 0xffffffff) */ - -/* ------------------- ETH_TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD ------------------- */ -#define ETH_TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_TX1024_MAXOCTGB_Pos \ - (0UL) /*!< ETH TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD: TX1024_MAXOCTGB (Bit 0) */ -#define ETH_TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_TX1024_MAXOCTGB_Msk \ - (0xffffffffUL) /*!< ETH TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD: TX1024_MAXOCTGB (Bitfield-Mask: \ - 0xffffffff) */ - -/* ----------------------- ETH_TX_UNICAST_FRAMES_GOOD_BAD ----------------------- */ -#define ETH_TX_UNICAST_FRAMES_GOOD_BAD_TXUCASTGB_Pos \ - (0UL) /*!< ETH TX_UNICAST_FRAMES_GOOD_BAD: TXUCASTGB (Bit 0) */ -#define ETH_TX_UNICAST_FRAMES_GOOD_BAD_TXUCASTGB_Msk \ - (0xffffffffUL) /*!< ETH TX_UNICAST_FRAMES_GOOD_BAD: TXUCASTGB (Bitfield-Mask: 0xffffffff) */ - -/* ---------------------- ETH_TX_MULTICAST_FRAMES_GOOD_BAD ---------------------- */ -#define ETH_TX_MULTICAST_FRAMES_GOOD_BAD_TXMCASTGB_Pos \ - (0UL) /*!< ETH TX_MULTICAST_FRAMES_GOOD_BAD: TXMCASTGB (Bit 0) */ -#define ETH_TX_MULTICAST_FRAMES_GOOD_BAD_TXMCASTGB_Msk \ - (0xffffffffUL) /*!< ETH TX_MULTICAST_FRAMES_GOOD_BAD: TXMCASTGB (Bitfield-Mask: 0xffffffff) */ - -/* ---------------------- ETH_TX_BROADCAST_FRAMES_GOOD_BAD ---------------------- */ -#define ETH_TX_BROADCAST_FRAMES_GOOD_BAD_TXBCASTGB_Pos \ - (0UL) /*!< ETH TX_BROADCAST_FRAMES_GOOD_BAD: TXBCASTGB (Bit 0) */ -#define ETH_TX_BROADCAST_FRAMES_GOOD_BAD_TXBCASTGB_Msk \ - (0xffffffffUL) /*!< ETH TX_BROADCAST_FRAMES_GOOD_BAD: TXBCASTGB (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------ ETH_TX_UNDERFLOW_ERROR_FRAMES ----------------------- */ -#define ETH_TX_UNDERFLOW_ERROR_FRAMES_TXUNDRFLW_Pos \ - (0UL) /*!< ETH TX_UNDERFLOW_ERROR_FRAMES: TXUNDRFLW (Bit 0) */ -#define ETH_TX_UNDERFLOW_ERROR_FRAMES_TXUNDRFLW_Msk \ - (0xffffffffUL) /*!< ETH TX_UNDERFLOW_ERROR_FRAMES: TXUNDRFLW (Bitfield-Mask: 0xffffffff) */ - -/* --------------------- ETH_TX_SINGLE_COLLISION_GOOD_FRAMES -------------------- */ -#define ETH_TX_SINGLE_COLLISION_GOOD_FRAMES_TXSNGLCOLG_Pos \ - (0UL) /*!< ETH TX_SINGLE_COLLISION_GOOD_FRAMES: TXSNGLCOLG (Bit 0) */ -#define ETH_TX_SINGLE_COLLISION_GOOD_FRAMES_TXSNGLCOLG_Msk \ - (0xffffffffUL) /*!< ETH TX_SINGLE_COLLISION_GOOD_FRAMES: TXSNGLCOLG (Bitfield-Mask: \ - 0xffffffff) */ - -/* -------------------- ETH_TX_MULTIPLE_COLLISION_GOOD_FRAMES ------------------- */ -#define ETH_TX_MULTIPLE_COLLISION_GOOD_FRAMES_TXMULTCOLG_Pos \ - (0UL) /*!< ETH TX_MULTIPLE_COLLISION_GOOD_FRAMES: TXMULTCOLG (Bit 0) */ -#define ETH_TX_MULTIPLE_COLLISION_GOOD_FRAMES_TXMULTCOLG_Msk \ - (0xffffffffUL) /*!< ETH TX_MULTIPLE_COLLISION_GOOD_FRAMES: TXMULTCOLG (Bitfield-Mask: \ - 0xffffffff) */ - -/* --------------------------- ETH_TX_DEFERRED_FRAMES --------------------------- */ -#define ETH_TX_DEFERRED_FRAMES_TXDEFRD_Pos \ - (0UL) /*!< ETH TX_DEFERRED_FRAMES: TXDEFRD (Bit 0) */ -#define ETH_TX_DEFERRED_FRAMES_TXDEFRD_Msk \ - (0xffffffffUL) /*!< ETH TX_DEFERRED_FRAMES: TXDEFRD (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------ ETH_TX_LATE_COLLISION_FRAMES ------------------------ */ -#define ETH_TX_LATE_COLLISION_FRAMES_TXLATECOL_Pos \ - (0UL) /*!< ETH TX_LATE_COLLISION_FRAMES: TXLATECOL (Bit 0) */ -#define ETH_TX_LATE_COLLISION_FRAMES_TXLATECOL_Msk \ - (0xffffffffUL) /*!< ETH TX_LATE_COLLISION_FRAMES: TXLATECOL (Bitfield-Mask: 0xffffffff) */ - -/* ---------------------- ETH_TX_EXCESSIVE_COLLISION_FRAMES --------------------- */ -#define ETH_TX_EXCESSIVE_COLLISION_FRAMES_TXEXSCOL_Pos \ - (0UL) /*!< ETH TX_EXCESSIVE_COLLISION_FRAMES: TXEXSCOL (Bit 0) */ -#define ETH_TX_EXCESSIVE_COLLISION_FRAMES_TXEXSCOL_Msk \ - (0xffffffffUL) /*!< ETH TX_EXCESSIVE_COLLISION_FRAMES: TXEXSCOL (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------- ETH_TX_CARRIER_ERROR_FRAMES ------------------------ */ -#define ETH_TX_CARRIER_ERROR_FRAMES_TXCARR_Pos \ - (0UL) /*!< ETH TX_CARRIER_ERROR_FRAMES: TXCARR (Bit 0) */ -#define ETH_TX_CARRIER_ERROR_FRAMES_TXCARR_Msk \ - (0xffffffffUL) /*!< ETH TX_CARRIER_ERROR_FRAMES: TXCARR (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------- ETH_TX_OCTET_COUNT_GOOD -------------------------- */ -#define ETH_TX_OCTET_COUNT_GOOD_TXOCTG_Pos \ - (0UL) /*!< ETH TX_OCTET_COUNT_GOOD: TXOCTG (Bit 0) */ -#define ETH_TX_OCTET_COUNT_GOOD_TXOCTG_Msk \ - (0xffffffffUL) /*!< ETH TX_OCTET_COUNT_GOOD: TXOCTG (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------- ETH_TX_FRAME_COUNT_GOOD -------------------------- */ -#define ETH_TX_FRAME_COUNT_GOOD_TXFRMG_Pos \ - (0UL) /*!< ETH TX_FRAME_COUNT_GOOD: TXFRMG (Bit 0) */ -#define ETH_TX_FRAME_COUNT_GOOD_TXFRMG_Msk \ - (0xffffffffUL) /*!< ETH TX_FRAME_COUNT_GOOD: TXFRMG (Bitfield-Mask: 0xffffffff) */ - -/* ----------------------- ETH_TX_EXCESSIVE_DEFERRAL_ERROR ---------------------- */ -#define ETH_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_Pos \ - (0UL) /*!< ETH TX_EXCESSIVE_DEFERRAL_ERROR: TXEXSDEF (Bit 0) */ -#define ETH_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_Msk \ - (0xffffffffUL) /*!< ETH TX_EXCESSIVE_DEFERRAL_ERROR: TXEXSDEF (Bitfield-Mask: 0xffffffff) */ - -/* ----------------------------- ETH_TX_PAUSE_FRAMES ---------------------------- */ -#define ETH_TX_PAUSE_FRAMES_TXPAUSE_Pos \ - (0UL) /*!< ETH TX_PAUSE_FRAMES: TXPAUSE (Bit 0) */ -#define ETH_TX_PAUSE_FRAMES_TXPAUSE_Msk \ - (0xffffffffUL) /*!< ETH TX_PAUSE_FRAMES: TXPAUSE (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------- ETH_TX_VLAN_FRAMES_GOOD -------------------------- */ -#define ETH_TX_VLAN_FRAMES_GOOD_TXVLANG_Pos \ - (0UL) /*!< ETH TX_VLAN_FRAMES_GOOD: TXVLANG (Bit 0) */ -#define ETH_TX_VLAN_FRAMES_GOOD_TXVLANG_Msk \ - (0xffffffffUL) /*!< ETH TX_VLAN_FRAMES_GOOD: TXVLANG (Bitfield-Mask: 0xffffffff) */ - -/* -------------------------- ETH_TX_OSIZE_FRAMES_GOOD -------------------------- */ -#define ETH_TX_OSIZE_FRAMES_GOOD_TXOSIZG_Pos \ - (0UL) /*!< ETH TX_OSIZE_FRAMES_GOOD: TXOSIZG (Bit 0) */ -#define ETH_TX_OSIZE_FRAMES_GOOD_TXOSIZG_Msk \ - (0xffffffffUL) /*!< ETH TX_OSIZE_FRAMES_GOOD: TXOSIZG (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------ ETH_RX_FRAMES_COUNT_GOOD_BAD ------------------------ */ -#define ETH_RX_FRAMES_COUNT_GOOD_BAD_RXFRMGB_Pos \ - (0UL) /*!< ETH RX_FRAMES_COUNT_GOOD_BAD: RXFRMGB (Bit 0) */ -#define ETH_RX_FRAMES_COUNT_GOOD_BAD_RXFRMGB_Msk \ - (0xffffffffUL) /*!< ETH RX_FRAMES_COUNT_GOOD_BAD: RXFRMGB (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------- ETH_RX_OCTET_COUNT_GOOD_BAD ------------------------ */ -#define ETH_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_Pos \ - (0UL) /*!< ETH RX_OCTET_COUNT_GOOD_BAD: RXOCTGB (Bit 0) */ -#define ETH_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_Msk \ - (0xffffffffUL) /*!< ETH RX_OCTET_COUNT_GOOD_BAD: RXOCTGB (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------- ETH_RX_OCTET_COUNT_GOOD -------------------------- */ -#define ETH_RX_OCTET_COUNT_GOOD_RXOCTG_Pos \ - (0UL) /*!< ETH RX_OCTET_COUNT_GOOD: RXOCTG (Bit 0) */ -#define ETH_RX_OCTET_COUNT_GOOD_RXOCTG_Msk \ - (0xffffffffUL) /*!< ETH RX_OCTET_COUNT_GOOD: RXOCTG (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------ ETH_RX_BROADCAST_FRAMES_GOOD ------------------------ */ -#define ETH_RX_BROADCAST_FRAMES_GOOD_RXBCASTG_Pos \ - (0UL) /*!< ETH RX_BROADCAST_FRAMES_GOOD: RXBCASTG (Bit 0) */ -#define ETH_RX_BROADCAST_FRAMES_GOOD_RXBCASTG_Msk \ - (0xffffffffUL) /*!< ETH RX_BROADCAST_FRAMES_GOOD: RXBCASTG (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------ ETH_RX_MULTICAST_FRAMES_GOOD ------------------------ */ -#define ETH_RX_MULTICAST_FRAMES_GOOD_RXMCASTG_Pos \ - (0UL) /*!< ETH RX_MULTICAST_FRAMES_GOOD: RXMCASTG (Bit 0) */ -#define ETH_RX_MULTICAST_FRAMES_GOOD_RXMCASTG_Msk \ - (0xffffffffUL) /*!< ETH RX_MULTICAST_FRAMES_GOOD: RXMCASTG (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------- ETH_RX_CRC_ERROR_FRAMES -------------------------- */ -#define ETH_RX_CRC_ERROR_FRAMES_RXCRCERR_Pos \ - (0UL) /*!< ETH RX_CRC_ERROR_FRAMES: RXCRCERR (Bit 0) */ -#define ETH_RX_CRC_ERROR_FRAMES_RXCRCERR_Msk \ - (0xffffffffUL) /*!< ETH RX_CRC_ERROR_FRAMES: RXCRCERR (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------ ETH_RX_ALIGNMENT_ERROR_FRAMES ----------------------- */ -#define ETH_RX_ALIGNMENT_ERROR_FRAMES_RXALGNERR_Pos \ - (0UL) /*!< ETH RX_ALIGNMENT_ERROR_FRAMES: RXALGNERR (Bit 0) */ -#define ETH_RX_ALIGNMENT_ERROR_FRAMES_RXALGNERR_Msk \ - (0xffffffffUL) /*!< ETH RX_ALIGNMENT_ERROR_FRAMES: RXALGNERR (Bitfield-Mask: 0xffffffff) */ - -/* -------------------------- ETH_RX_RUNT_ERROR_FRAMES -------------------------- */ -#define ETH_RX_RUNT_ERROR_FRAMES_RXRUNTERR_Pos \ - (0UL) /*!< ETH RX_RUNT_ERROR_FRAMES: RXRUNTERR (Bit 0) */ -#define ETH_RX_RUNT_ERROR_FRAMES_RXRUNTERR_Msk \ - (0xffffffffUL) /*!< ETH RX_RUNT_ERROR_FRAMES: RXRUNTERR (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------- ETH_RX_JABBER_ERROR_FRAMES ------------------------- */ -#define ETH_RX_JABBER_ERROR_FRAMES_RXJABERR_Pos \ - (0UL) /*!< ETH RX_JABBER_ERROR_FRAMES: RXJABERR (Bit 0) */ -#define ETH_RX_JABBER_ERROR_FRAMES_RXJABERR_Msk \ - (0xffffffffUL) /*!< ETH RX_JABBER_ERROR_FRAMES: RXJABERR (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------ ETH_RX_UNDERSIZE_FRAMES_GOOD ------------------------ */ -#define ETH_RX_UNDERSIZE_FRAMES_GOOD_RXUNDERSZG_Pos \ - (0UL) /*!< ETH RX_UNDERSIZE_FRAMES_GOOD: RXUNDERSZG (Bit 0) */ -#define ETH_RX_UNDERSIZE_FRAMES_GOOD_RXUNDERSZG_Msk \ - (0xffffffffUL) /*!< ETH RX_UNDERSIZE_FRAMES_GOOD: RXUNDERSZG (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------- ETH_RX_OVERSIZE_FRAMES_GOOD ------------------------ */ -#define ETH_RX_OVERSIZE_FRAMES_GOOD_RXOVERSZG_Pos \ - (0UL) /*!< ETH RX_OVERSIZE_FRAMES_GOOD: RXOVERSZG (Bit 0) */ -#define ETH_RX_OVERSIZE_FRAMES_GOOD_RXOVERSZG_Msk \ - (0xffffffffUL) /*!< ETH RX_OVERSIZE_FRAMES_GOOD: RXOVERSZG (Bitfield-Mask: 0xffffffff) */ - -/* ----------------------- ETH_RX_64OCTETS_FRAMES_GOOD_BAD ---------------------- */ -#define ETH_RX_64OCTETS_FRAMES_GOOD_BAD_RX64OCTGB_Pos \ - (0UL) /*!< ETH RX_64OCTETS_FRAMES_GOOD_BAD: RX64OCTGB (Bit 0) */ -#define ETH_RX_64OCTETS_FRAMES_GOOD_BAD_RX64OCTGB_Msk \ - (0xffffffffUL) /*!< ETH RX_64OCTETS_FRAMES_GOOD_BAD: RX64OCTGB (Bitfield-Mask: 0xffffffff) */ - -/* -------------------- ETH_RX_65TO127OCTETS_FRAMES_GOOD_BAD -------------------- */ -#define ETH_RX_65TO127OCTETS_FRAMES_GOOD_BAD_RX65_127OCTGB_Pos \ - (0UL) /*!< ETH RX_65TO127OCTETS_FRAMES_GOOD_BAD: RX65_127OCTGB (Bit 0) */ -#define ETH_RX_65TO127OCTETS_FRAMES_GOOD_BAD_RX65_127OCTGB_Msk \ - (0xffffffffUL) /*!< ETH RX_65TO127OCTETS_FRAMES_GOOD_BAD: RX65_127OCTGB (Bitfield-Mask: \ - 0xffffffff) */ - -/* -------------------- ETH_RX_128TO255OCTETS_FRAMES_GOOD_BAD ------------------- */ -#define ETH_RX_128TO255OCTETS_FRAMES_GOOD_BAD_RX128_255OCTGB_Pos \ - (0UL) /*!< ETH RX_128TO255OCTETS_FRAMES_GOOD_BAD: RX128_255OCTGB (Bit 0) */ -#define ETH_RX_128TO255OCTETS_FRAMES_GOOD_BAD_RX128_255OCTGB_Msk \ - (0xffffffffUL) /*!< ETH RX_128TO255OCTETS_FRAMES_GOOD_BAD: RX128_255OCTGB (Bitfield-Mask: \ - 0xffffffff) */ - -/* -------------------- ETH_RX_256TO511OCTETS_FRAMES_GOOD_BAD ------------------- */ -#define ETH_RX_256TO511OCTETS_FRAMES_GOOD_BAD_RX256_511OCTGB_Pos \ - (0UL) /*!< ETH RX_256TO511OCTETS_FRAMES_GOOD_BAD: RX256_511OCTGB (Bit 0) */ -#define ETH_RX_256TO511OCTETS_FRAMES_GOOD_BAD_RX256_511OCTGB_Msk \ - (0xffffffffUL) /*!< ETH RX_256TO511OCTETS_FRAMES_GOOD_BAD: RX256_511OCTGB (Bitfield-Mask: \ - 0xffffffff) */ - -/* ------------------- ETH_RX_512TO1023OCTETS_FRAMES_GOOD_BAD ------------------- */ -#define ETH_RX_512TO1023OCTETS_FRAMES_GOOD_BAD_RX512_1023OCTGB_Pos \ - (0UL) /*!< ETH RX_512TO1023OCTETS_FRAMES_GOOD_BAD: RX512_1023OCTGB (Bit 0) */ -#define ETH_RX_512TO1023OCTETS_FRAMES_GOOD_BAD_RX512_1023OCTGB_Msk \ - (0xffffffffUL) /*!< ETH RX_512TO1023OCTETS_FRAMES_GOOD_BAD: RX512_1023OCTGB (Bitfield-Mask: \ - 0xffffffff) */ - -/* ------------------- ETH_RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD ------------------- */ -#define ETH_RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_RX1024_MAXOCTGB_Pos \ - (0UL) /*!< ETH RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD: RX1024_MAXOCTGB (Bit 0) */ -#define ETH_RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_RX1024_MAXOCTGB_Msk \ - (0xffffffffUL) /*!< ETH RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD: RX1024_MAXOCTGB (Bitfield-Mask: \ - 0xffffffff) */ - -/* ------------------------- ETH_RX_UNICAST_FRAMES_GOOD ------------------------- */ -#define ETH_RX_UNICAST_FRAMES_GOOD_RXUCASTG_Pos \ - (0UL) /*!< ETH RX_UNICAST_FRAMES_GOOD: RXUCASTG (Bit 0) */ -#define ETH_RX_UNICAST_FRAMES_GOOD_RXUCASTG_Msk \ - (0xffffffffUL) /*!< ETH RX_UNICAST_FRAMES_GOOD: RXUCASTG (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------- ETH_RX_LENGTH_ERROR_FRAMES ------------------------- */ -#define ETH_RX_LENGTH_ERROR_FRAMES_RXLENERR_Pos \ - (0UL) /*!< ETH RX_LENGTH_ERROR_FRAMES: RXLENERR (Bit 0) */ -#define ETH_RX_LENGTH_ERROR_FRAMES_RXLENERR_Msk \ - (0xffffffffUL) /*!< ETH RX_LENGTH_ERROR_FRAMES: RXLENERR (Bitfield-Mask: 0xffffffff) */ - -/* ----------------------- ETH_RX_OUT_OF_RANGE_TYPE_FRAMES ---------------------- */ -#define ETH_RX_OUT_OF_RANGE_TYPE_FRAMES_RXOUTOFRNG_Pos \ - (0UL) /*!< ETH RX_OUT_OF_RANGE_TYPE_FRAMES: RXOUTOFRNG (Bit 0) */ -#define ETH_RX_OUT_OF_RANGE_TYPE_FRAMES_RXOUTOFRNG_Msk \ - (0xffffffffUL) /*!< ETH RX_OUT_OF_RANGE_TYPE_FRAMES: RXOUTOFRNG (Bitfield-Mask: 0xffffffff) */ - -/* ----------------------------- ETH_RX_PAUSE_FRAMES ---------------------------- */ -#define ETH_RX_PAUSE_FRAMES_RXPAUSEFRM_Pos \ - (0UL) /*!< ETH RX_PAUSE_FRAMES: RXPAUSEFRM (Bit 0) */ -#define ETH_RX_PAUSE_FRAMES_RXPAUSEFRM_Msk \ - (0xffffffffUL) /*!< ETH RX_PAUSE_FRAMES: RXPAUSEFRM (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------- ETH_RX_FIFO_OVERFLOW_FRAMES ------------------------ */ -#define ETH_RX_FIFO_OVERFLOW_FRAMES_RXFIFOOVFL_Pos \ - (0UL) /*!< ETH RX_FIFO_OVERFLOW_FRAMES: RXFIFOOVFL (Bit 0) */ -#define ETH_RX_FIFO_OVERFLOW_FRAMES_RXFIFOOVFL_Msk \ - (0xffffffffUL) /*!< ETH RX_FIFO_OVERFLOW_FRAMES: RXFIFOOVFL (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------- ETH_RX_VLAN_FRAMES_GOOD_BAD ------------------------ */ -#define ETH_RX_VLAN_FRAMES_GOOD_BAD_RXVLANFRGB_Pos \ - (0UL) /*!< ETH RX_VLAN_FRAMES_GOOD_BAD: RXVLANFRGB (Bit 0) */ -#define ETH_RX_VLAN_FRAMES_GOOD_BAD_RXVLANFRGB_Msk \ - (0xffffffffUL) /*!< ETH RX_VLAN_FRAMES_GOOD_BAD: RXVLANFRGB (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------ ETH_RX_WATCHDOG_ERROR_FRAMES ------------------------ */ -#define ETH_RX_WATCHDOG_ERROR_FRAMES_RXWDGERR_Pos \ - (0UL) /*!< ETH RX_WATCHDOG_ERROR_FRAMES: RXWDGERR (Bit 0) */ -#define ETH_RX_WATCHDOG_ERROR_FRAMES_RXWDGERR_Msk \ - (0xffffffffUL) /*!< ETH RX_WATCHDOG_ERROR_FRAMES: RXWDGERR (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------- ETH_RX_RECEIVE_ERROR_FRAMES ------------------------ */ -#define ETH_RX_RECEIVE_ERROR_FRAMES_RXRCVERR_Pos \ - (0UL) /*!< ETH RX_RECEIVE_ERROR_FRAMES: RXRCVERR (Bit 0) */ -#define ETH_RX_RECEIVE_ERROR_FRAMES_RXRCVERR_Msk \ - (0xffffffffUL) /*!< ETH RX_RECEIVE_ERROR_FRAMES: RXRCVERR (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------- ETH_RX_CONTROL_FRAMES_GOOD ------------------------- */ -#define ETH_RX_CONTROL_FRAMES_GOOD_RXCTRLG_Pos \ - (0UL) /*!< ETH RX_CONTROL_FRAMES_GOOD: RXCTRLG (Bit 0) */ -#define ETH_RX_CONTROL_FRAMES_GOOD_RXCTRLG_Msk \ - (0xffffffffUL) /*!< ETH RX_CONTROL_FRAMES_GOOD: RXCTRLG (Bitfield-Mask: 0xffffffff) */ - -/* --------------------- ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK --------------------- */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GFIM_Pos \ - (0UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4GFIM (Bit 0) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GFIM_Msk \ - (0x1UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4GFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HERFIM_Pos \ - (1UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4HERFIM (Bit 1) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HERFIM_Msk \ - (0x2UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4HERFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYFIM_Pos \ - (2UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4NOPAYFIM (Bit 2) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYFIM_Msk \ - (0x4UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4NOPAYFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGFIM_Pos \ - (3UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4FRAGFIM (Bit 3) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGFIM_Msk \ - (0x8UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4FRAGFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLFIM_Pos \ - (4UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4UDSBLFIM (Bit 4) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLFIM_Msk \ - (0x10UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4UDSBLFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GFIM_Pos \ - (5UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6GFIM (Bit 5) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GFIM_Msk \ - (0x20UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6GFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HERFIM_Pos \ - (6UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6HERFIM (Bit 6) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HERFIM_Msk \ - (0x40UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6HERFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYFIM_Pos \ - (7UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6NOPAYFIM (Bit 7) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYFIM_Msk \ - (0x80UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6NOPAYFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGFIM_Pos \ - (8UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXUDPGFIM (Bit 8) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGFIM_Msk \ - (0x100UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXUDPGFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPERFIM_Pos \ - (9UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXUDPERFIM (Bit 9) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPERFIM_Msk \ - (0x200UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXUDPERFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGFIM_Pos \ - (10UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXTCPGFIM (Bit 10) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGFIM_Msk \ - (0x400UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXTCPGFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPERFIM_Pos \ - (11UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXTCPERFIM (Bit 11) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPERFIM_Msk \ - (0x800UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXTCPERFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGFIM_Pos \ - (12UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXICMPGFIM (Bit 12) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGFIM_Msk \ - (0x1000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXICMPGFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPERFIM_Pos \ - (13UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXICMPERFIM (Bit 13) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPERFIM_Msk \ - (0x2000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXICMPERFIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GOIM_Pos \ - (16UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4GOIM (Bit 16) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GOIM_Msk \ - (0x10000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4GOIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HEROIM_Pos \ - (17UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4HEROIM (Bit 17) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HEROIM_Msk \ - (0x20000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4HEROIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYOIM_Pos \ - (18UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4NOPAYOIM (Bit 18) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYOIM_Msk \ - (0x40000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4NOPAYOIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGOIM_Pos \ - (19UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4FRAGOIM (Bit 19) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGOIM_Msk \ - (0x80000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4FRAGOIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLOIM_Pos \ - (20UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4UDSBLOIM (Bit 20) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLOIM_Msk \ - (0x100000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4UDSBLOIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GOIM_Pos \ - (21UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6GOIM (Bit 21) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GOIM_Msk \ - (0x200000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6GOIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HEROIM_Pos \ - (22UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6HEROIM (Bit 22) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HEROIM_Msk \ - (0x400000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6HEROIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYOIM_Pos \ - (23UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6NOPAYOIM (Bit 23) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYOIM_Msk \ - (0x800000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6NOPAYOIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGOIM_Pos \ - (24UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXUDPGOIM (Bit 24) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGOIM_Msk \ - (0x1000000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXUDPGOIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPEROIM_Pos \ - (25UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXUDPEROIM (Bit 25) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPEROIM_Msk \ - (0x2000000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXUDPEROIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGOIM_Pos \ - (26UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXTCPGOIM (Bit 26) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGOIM_Msk \ - (0x4000000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXTCPGOIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPEROIM_Pos \ - (27UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXTCPEROIM (Bit 27) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPEROIM_Msk \ - (0x8000000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXTCPEROIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGOIM_Pos \ - (28UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXICMPGOIM (Bit 28) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGOIM_Msk \ - (0x10000000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXICMPGOIM (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPEROIM_Pos \ - (29UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXICMPEROIM (Bit 29) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPEROIM_Msk \ - (0x20000000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXICMPEROIM (Bitfield-Mask: 0x01) */ - -/* ------------------------ ETH_MMC_IPC_RECEIVE_INTERRUPT ----------------------- */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GFIS_Pos \ - (0UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4GFIS (Bit 0) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GFIS_Msk \ - (0x1UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4GFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HERFIS_Pos \ - (1UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4HERFIS (Bit 1) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HERFIS_Msk \ - (0x2UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4HERFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYFIS_Pos \ - (2UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4NOPAYFIS (Bit 2) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYFIS_Msk \ - (0x4UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4NOPAYFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGFIS_Pos \ - (3UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4FRAGFIS (Bit 3) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGFIS_Msk \ - (0x8UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4FRAGFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLFIS_Pos \ - (4UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4UDSBLFIS (Bit 4) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLFIS_Msk \ - (0x10UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4UDSBLFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GFIS_Pos \ - (5UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6GFIS (Bit 5) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GFIS_Msk \ - (0x20UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6GFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HERFIS_Pos \ - (6UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6HERFIS (Bit 6) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HERFIS_Msk \ - (0x40UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6HERFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYFIS_Pos \ - (7UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6NOPAYFIS (Bit 7) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYFIS_Msk \ - (0x80UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6NOPAYFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGFIS_Pos \ - (8UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXUDPGFIS (Bit 8) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGFIS_Msk \ - (0x100UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXUDPGFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPERFIS_Pos \ - (9UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXUDPERFIS (Bit 9) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPERFIS_Msk \ - (0x200UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXUDPERFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGFIS_Pos \ - (10UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXTCPGFIS (Bit 10) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGFIS_Msk \ - (0x400UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXTCPGFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPERFIS_Pos \ - (11UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXTCPERFIS (Bit 11) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPERFIS_Msk \ - (0x800UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXTCPERFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGFIS_Pos \ - (12UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXICMPGFIS (Bit 12) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGFIS_Msk \ - (0x1000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXICMPGFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPERFIS_Pos \ - (13UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXICMPERFIS (Bit 13) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPERFIS_Msk \ - (0x2000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXICMPERFIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GOIS_Pos \ - (16UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4GOIS (Bit 16) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GOIS_Msk \ - (0x10000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4GOIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HEROIS_Pos \ - (17UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4HEROIS (Bit 17) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HEROIS_Msk \ - (0x20000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4HEROIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYOIS_Pos \ - (18UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4NOPAYOIS (Bit 18) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYOIS_Msk \ - (0x40000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4NOPAYOIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGOIS_Pos \ - (19UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4FRAGOIS (Bit 19) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGOIS_Msk \ - (0x80000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4FRAGOIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLOIS_Pos \ - (20UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4UDSBLOIS (Bit 20) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLOIS_Msk \ - (0x100000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4UDSBLOIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GOIS_Pos \ - (21UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6GOIS (Bit 21) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GOIS_Msk \ - (0x200000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6GOIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HEROIS_Pos \ - (22UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6HEROIS (Bit 22) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HEROIS_Msk \ - (0x400000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6HEROIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYOIS_Pos \ - (23UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6NOPAYOIS (Bit 23) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYOIS_Msk \ - (0x800000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6NOPAYOIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGOIS_Pos \ - (24UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXUDPGOIS (Bit 24) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGOIS_Msk \ - (0x1000000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXUDPGOIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPEROIS_Pos \ - (25UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXUDPEROIS (Bit 25) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPEROIS_Msk \ - (0x2000000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXUDPEROIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGOIS_Pos \ - (26UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXTCPGOIS (Bit 26) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGOIS_Msk \ - (0x4000000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXTCPGOIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPEROIS_Pos \ - (27UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXTCPEROIS (Bit 27) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPEROIS_Msk \ - (0x8000000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXTCPEROIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGOIS_Pos \ - (28UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXICMPGOIS (Bit 28) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGOIS_Msk \ - (0x10000000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXICMPGOIS (Bitfield-Mask: 0x01) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPEROIS_Pos \ - (29UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXICMPEROIS (Bit 29) */ -#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPEROIS_Msk \ - (0x20000000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXICMPEROIS (Bitfield-Mask: 0x01) */ - -/* --------------------------- ETH_RXIPV4_GOOD_FRAMES --------------------------- */ -#define ETH_RXIPV4_GOOD_FRAMES_RXIPV4GDFRM_Pos \ - (0UL) /*!< ETH RXIPV4_GOOD_FRAMES: RXIPV4GDFRM (Bit 0) */ -#define ETH_RXIPV4_GOOD_FRAMES_RXIPV4GDFRM_Msk \ - (0xffffffffUL) /*!< ETH RXIPV4_GOOD_FRAMES: RXIPV4GDFRM (Bitfield-Mask: 0xffffffff) */ - -/* ----------------------- ETH_RXIPV4_HEADER_ERROR_FRAMES ----------------------- */ -#define ETH_RXIPV4_HEADER_ERROR_FRAMES_RXIPV4HDRERRFRM_Pos \ - (0UL) /*!< ETH RXIPV4_HEADER_ERROR_FRAMES: RXIPV4HDRERRFRM (Bit 0) */ -#define ETH_RXIPV4_HEADER_ERROR_FRAMES_RXIPV4HDRERRFRM_Msk \ - (0xffffffffUL) /*!< ETH RXIPV4_HEADER_ERROR_FRAMES: RXIPV4HDRERRFRM (Bitfield-Mask: \ - 0xffffffff) */ - -/* ------------------------ ETH_RXIPV4_NO_PAYLOAD_FRAMES ------------------------ */ -#define ETH_RXIPV4_NO_PAYLOAD_FRAMES_RXIPV4NOPAYFRM_Pos \ - (0UL) /*!< ETH RXIPV4_NO_PAYLOAD_FRAMES: RXIPV4NOPAYFRM (Bit 0) */ -#define ETH_RXIPV4_NO_PAYLOAD_FRAMES_RXIPV4NOPAYFRM_Msk \ - (0xffffffffUL) /*!< ETH RXIPV4_NO_PAYLOAD_FRAMES: RXIPV4NOPAYFRM (Bitfield-Mask: 0xffffffff) \ - */ - -/* ------------------------ ETH_RXIPV4_FRAGMENTED_FRAMES ------------------------ */ -#define ETH_RXIPV4_FRAGMENTED_FRAMES_RXIPV4FRAGFRM_Pos \ - (0UL) /*!< ETH RXIPV4_FRAGMENTED_FRAMES: RXIPV4FRAGFRM (Bit 0) */ -#define ETH_RXIPV4_FRAGMENTED_FRAMES_RXIPV4FRAGFRM_Msk \ - (0xffffffffUL) /*!< ETH RXIPV4_FRAGMENTED_FRAMES: RXIPV4FRAGFRM (Bitfield-Mask: 0xffffffff) */ - -/* ------------------- ETH_RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES ------------------ */ -#define ETH_RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES_RXIPV4UDSBLFRM_Pos \ - (0UL) /*!< ETH RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES: RXIPV4UDSBLFRM (Bit 0) */ -#define ETH_RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES_RXIPV4UDSBLFRM_Msk \ - (0xffffffffUL) /*!< ETH RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES: RXIPV4UDSBLFRM (Bitfield-Mask: \ - 0xffffffff) */ - -/* --------------------------- ETH_RXIPV6_GOOD_FRAMES --------------------------- */ -#define ETH_RXIPV6_GOOD_FRAMES_RXIPV6GDFRM_Pos \ - (0UL) /*!< ETH RXIPV6_GOOD_FRAMES: RXIPV6GDFRM (Bit 0) */ -#define ETH_RXIPV6_GOOD_FRAMES_RXIPV6GDFRM_Msk \ - (0xffffffffUL) /*!< ETH RXIPV6_GOOD_FRAMES: RXIPV6GDFRM (Bitfield-Mask: 0xffffffff) */ - -/* ----------------------- ETH_RXIPV6_HEADER_ERROR_FRAMES ----------------------- */ -#define ETH_RXIPV6_HEADER_ERROR_FRAMES_RXIPV6HDRERRFRM_Pos \ - (0UL) /*!< ETH RXIPV6_HEADER_ERROR_FRAMES: RXIPV6HDRERRFRM (Bit 0) */ -#define ETH_RXIPV6_HEADER_ERROR_FRAMES_RXIPV6HDRERRFRM_Msk \ - (0xffffffffUL) /*!< ETH RXIPV6_HEADER_ERROR_FRAMES: RXIPV6HDRERRFRM (Bitfield-Mask: \ - 0xffffffff) */ - -/* ------------------------ ETH_RXIPV6_NO_PAYLOAD_FRAMES ------------------------ */ -#define ETH_RXIPV6_NO_PAYLOAD_FRAMES_RXIPV6NOPAYFRM_Pos \ - (0UL) /*!< ETH RXIPV6_NO_PAYLOAD_FRAMES: RXIPV6NOPAYFRM (Bit 0) */ -#define ETH_RXIPV6_NO_PAYLOAD_FRAMES_RXIPV6NOPAYFRM_Msk \ - (0xffffffffUL) /*!< ETH RXIPV6_NO_PAYLOAD_FRAMES: RXIPV6NOPAYFRM (Bitfield-Mask: 0xffffffff) \ - */ - -/* ---------------------------- ETH_RXUDP_GOOD_FRAMES --------------------------- */ -#define ETH_RXUDP_GOOD_FRAMES_RXUDPGDFRM_Pos \ - (0UL) /*!< ETH RXUDP_GOOD_FRAMES: RXUDPGDFRM (Bit 0) */ -#define ETH_RXUDP_GOOD_FRAMES_RXUDPGDFRM_Msk \ - (0xffffffffUL) /*!< ETH RXUDP_GOOD_FRAMES: RXUDPGDFRM (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------- ETH_RXUDP_ERROR_FRAMES --------------------------- */ -#define ETH_RXUDP_ERROR_FRAMES_RXUDPERRFRM_Pos \ - (0UL) /*!< ETH RXUDP_ERROR_FRAMES: RXUDPERRFRM (Bit 0) */ -#define ETH_RXUDP_ERROR_FRAMES_RXUDPERRFRM_Msk \ - (0xffffffffUL) /*!< ETH RXUDP_ERROR_FRAMES: RXUDPERRFRM (Bitfield-Mask: 0xffffffff) */ - -/* ---------------------------- ETH_RXTCP_GOOD_FRAMES --------------------------- */ -#define ETH_RXTCP_GOOD_FRAMES_RXTCPGDFRM_Pos \ - (0UL) /*!< ETH RXTCP_GOOD_FRAMES: RXTCPGDFRM (Bit 0) */ -#define ETH_RXTCP_GOOD_FRAMES_RXTCPGDFRM_Msk \ - (0xffffffffUL) /*!< ETH RXTCP_GOOD_FRAMES: RXTCPGDFRM (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------- ETH_RXTCP_ERROR_FRAMES --------------------------- */ -#define ETH_RXTCP_ERROR_FRAMES_RXTCPERRFRM_Pos \ - (0UL) /*!< ETH RXTCP_ERROR_FRAMES: RXTCPERRFRM (Bit 0) */ -#define ETH_RXTCP_ERROR_FRAMES_RXTCPERRFRM_Msk \ - (0xffffffffUL) /*!< ETH RXTCP_ERROR_FRAMES: RXTCPERRFRM (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------- ETH_RXICMP_GOOD_FRAMES --------------------------- */ -#define ETH_RXICMP_GOOD_FRAMES_RXICMPGDFRM_Pos \ - (0UL) /*!< ETH RXICMP_GOOD_FRAMES: RXICMPGDFRM (Bit 0) */ -#define ETH_RXICMP_GOOD_FRAMES_RXICMPGDFRM_Msk \ - (0xffffffffUL) /*!< ETH RXICMP_GOOD_FRAMES: RXICMPGDFRM (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------- ETH_RXICMP_ERROR_FRAMES -------------------------- */ -#define ETH_RXICMP_ERROR_FRAMES_RXICMPERRFRM_Pos \ - (0UL) /*!< ETH RXICMP_ERROR_FRAMES: RXICMPERRFRM (Bit 0) */ -#define ETH_RXICMP_ERROR_FRAMES_RXICMPERRFRM_Msk \ - (0xffffffffUL) /*!< ETH RXICMP_ERROR_FRAMES: RXICMPERRFRM (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------- ETH_RXIPV4_GOOD_OCTETS --------------------------- */ -#define ETH_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_Pos \ - (0UL) /*!< ETH RXIPV4_GOOD_OCTETS: RXIPV4GDOCT (Bit 0) */ -#define ETH_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_Msk \ - (0xffffffffUL) /*!< ETH RXIPV4_GOOD_OCTETS: RXIPV4GDOCT (Bitfield-Mask: 0xffffffff) */ - -/* ----------------------- ETH_RXIPV4_HEADER_ERROR_OCTETS ----------------------- */ -#define ETH_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_Pos \ - (0UL) /*!< ETH RXIPV4_HEADER_ERROR_OCTETS: RXIPV4HDRERROCT (Bit 0) */ -#define ETH_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_Msk \ - (0xffffffffUL) /*!< ETH RXIPV4_HEADER_ERROR_OCTETS: RXIPV4HDRERROCT (Bitfield-Mask: \ - 0xffffffff) */ - -/* ------------------------ ETH_RXIPV4_NO_PAYLOAD_OCTETS ------------------------ */ -#define ETH_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_Pos \ - (0UL) /*!< ETH RXIPV4_NO_PAYLOAD_OCTETS: RXIPV4NOPAYOCT (Bit 0) */ -#define ETH_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_Msk \ - (0xffffffffUL) /*!< ETH RXIPV4_NO_PAYLOAD_OCTETS: RXIPV4NOPAYOCT (Bitfield-Mask: 0xffffffff) \ - */ - -/* ------------------------ ETH_RXIPV4_FRAGMENTED_OCTETS ------------------------ */ -#define ETH_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_Pos \ - (0UL) /*!< ETH RXIPV4_FRAGMENTED_OCTETS: RXIPV4FRAGOCT (Bit 0) */ -#define ETH_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_Msk \ - (0xffffffffUL) /*!< ETH RXIPV4_FRAGMENTED_OCTETS: RXIPV4FRAGOCT (Bitfield-Mask: 0xffffffff) */ - -/* ------------------- ETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS ------------------- */ -#define ETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_Pos \ - (0UL) /*!< ETH RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS: RXIPV4UDSBLOCT (Bit 0) */ -#define ETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_Msk \ - (0xffffffffUL) /*!< ETH RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS: RXIPV4UDSBLOCT (Bitfield-Mask: \ - 0xffffffff) */ - -/* --------------------------- ETH_RXIPV6_GOOD_OCTETS --------------------------- */ -#define ETH_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_Pos \ - (0UL) /*!< ETH RXIPV6_GOOD_OCTETS: RXIPV6GDOCT (Bit 0) */ -#define ETH_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_Msk \ - (0xffffffffUL) /*!< ETH RXIPV6_GOOD_OCTETS: RXIPV6GDOCT (Bitfield-Mask: 0xffffffff) */ - -/* ----------------------- ETH_RXIPV6_HEADER_ERROR_OCTETS ----------------------- */ -#define ETH_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_Pos \ - (0UL) /*!< ETH RXIPV6_HEADER_ERROR_OCTETS: RXIPV6HDRERROCT (Bit 0) */ -#define ETH_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_Msk \ - (0xffffffffUL) /*!< ETH RXIPV6_HEADER_ERROR_OCTETS: RXIPV6HDRERROCT (Bitfield-Mask: \ - 0xffffffff) */ - -/* ------------------------ ETH_RXIPV6_NO_PAYLOAD_OCTETS ------------------------ */ -#define ETH_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_Pos \ - (0UL) /*!< ETH RXIPV6_NO_PAYLOAD_OCTETS: RXIPV6NOPAYOCT (Bit 0) */ -#define ETH_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_Msk \ - (0xffffffffUL) /*!< ETH RXIPV6_NO_PAYLOAD_OCTETS: RXIPV6NOPAYOCT (Bitfield-Mask: 0xffffffff) \ - */ - -/* ---------------------------- ETH_RXUDP_GOOD_OCTETS --------------------------- */ -#define ETH_RXUDP_GOOD_OCTETS_RXUDPGDOCT_Pos \ - (0UL) /*!< ETH RXUDP_GOOD_OCTETS: RXUDPGDOCT (Bit 0) */ -#define ETH_RXUDP_GOOD_OCTETS_RXUDPGDOCT_Msk \ - (0xffffffffUL) /*!< ETH RXUDP_GOOD_OCTETS: RXUDPGDOCT (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------- ETH_RXUDP_ERROR_OCTETS --------------------------- */ -#define ETH_RXUDP_ERROR_OCTETS_RXUDPERROCT_Pos \ - (0UL) /*!< ETH RXUDP_ERROR_OCTETS: RXUDPERROCT (Bit 0) */ -#define ETH_RXUDP_ERROR_OCTETS_RXUDPERROCT_Msk \ - (0xffffffffUL) /*!< ETH RXUDP_ERROR_OCTETS: RXUDPERROCT (Bitfield-Mask: 0xffffffff) */ - -/* ---------------------------- ETH_RXTCP_GOOD_OCTETS --------------------------- */ -#define ETH_RXTCP_GOOD_OCTETS_RXTCPGDOCT_Pos \ - (0UL) /*!< ETH RXTCP_GOOD_OCTETS: RXTCPGDOCT (Bit 0) */ -#define ETH_RXTCP_GOOD_OCTETS_RXTCPGDOCT_Msk \ - (0xffffffffUL) /*!< ETH RXTCP_GOOD_OCTETS: RXTCPGDOCT (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------- ETH_RXTCP_ERROR_OCTETS --------------------------- */ -#define ETH_RXTCP_ERROR_OCTETS_RXTCPERROCT_Pos \ - (0UL) /*!< ETH RXTCP_ERROR_OCTETS: RXTCPERROCT (Bit 0) */ -#define ETH_RXTCP_ERROR_OCTETS_RXTCPERROCT_Msk \ - (0xffffffffUL) /*!< ETH RXTCP_ERROR_OCTETS: RXTCPERROCT (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------- ETH_RXICMP_GOOD_OCTETS --------------------------- */ -#define ETH_RXICMP_GOOD_OCTETS_RXICMPGDOCT_Pos \ - (0UL) /*!< ETH RXICMP_GOOD_OCTETS: RXICMPGDOCT (Bit 0) */ -#define ETH_RXICMP_GOOD_OCTETS_RXICMPGDOCT_Msk \ - (0xffffffffUL) /*!< ETH RXICMP_GOOD_OCTETS: RXICMPGDOCT (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------- ETH_RXICMP_ERROR_OCTETS -------------------------- */ -#define ETH_RXICMP_ERROR_OCTETS_RXICMPERROCT_Pos \ - (0UL) /*!< ETH RXICMP_ERROR_OCTETS: RXICMPERROCT (Bit 0) */ -#define ETH_RXICMP_ERROR_OCTETS_RXICMPERROCT_Msk \ - (0xffffffffUL) /*!< ETH RXICMP_ERROR_OCTETS: RXICMPERROCT (Bitfield-Mask: 0xffffffff) */ - -/* ---------------------------- ETH_TIMESTAMP_CONTROL --------------------------- */ -#define ETH_TIMESTAMP_CONTROL_TSENA_Pos \ - (0UL) /*!< ETH TIMESTAMP_CONTROL: TSENA (Bit 0) */ -#define ETH_TIMESTAMP_CONTROL_TSENA_Msk \ - (0x1UL) /*!< ETH TIMESTAMP_CONTROL: TSENA (Bitfield-Mask: 0x01) */ -#define ETH_TIMESTAMP_CONTROL_TSCFUPDT_Pos \ - (1UL) /*!< ETH TIMESTAMP_CONTROL: TSCFUPDT (Bit 1) */ -#define ETH_TIMESTAMP_CONTROL_TSCFUPDT_Msk \ - (0x2UL) /*!< ETH TIMESTAMP_CONTROL: TSCFUPDT (Bitfield-Mask: 0x01) */ -#define ETH_TIMESTAMP_CONTROL_TSINIT_Pos \ - (2UL) /*!< ETH TIMESTAMP_CONTROL: TSINIT (Bit 2) */ -#define ETH_TIMESTAMP_CONTROL_TSINIT_Msk \ - (0x4UL) /*!< ETH TIMESTAMP_CONTROL: TSINIT (Bitfield-Mask: 0x01) */ -#define ETH_TIMESTAMP_CONTROL_TSUPDT_Pos \ - (3UL) /*!< ETH TIMESTAMP_CONTROL: TSUPDT (Bit 3) */ -#define ETH_TIMESTAMP_CONTROL_TSUPDT_Msk \ - (0x8UL) /*!< ETH TIMESTAMP_CONTROL: TSUPDT (Bitfield-Mask: 0x01) */ -#define ETH_TIMESTAMP_CONTROL_TSTRIG_Pos \ - (4UL) /*!< ETH TIMESTAMP_CONTROL: TSTRIG (Bit 4) */ -#define ETH_TIMESTAMP_CONTROL_TSTRIG_Msk \ - (0x10UL) /*!< ETH TIMESTAMP_CONTROL: TSTRIG (Bitfield-Mask: 0x01) */ -#define ETH_TIMESTAMP_CONTROL_TSADDREG_Pos \ - (5UL) /*!< ETH TIMESTAMP_CONTROL: TSADDREG (Bit 5) */ -#define ETH_TIMESTAMP_CONTROL_TSADDREG_Msk \ - (0x20UL) /*!< ETH TIMESTAMP_CONTROL: TSADDREG (Bitfield-Mask: 0x01) */ -#define ETH_TIMESTAMP_CONTROL_TSENALL_Pos \ - (8UL) /*!< ETH TIMESTAMP_CONTROL: TSENALL (Bit 8) */ -#define ETH_TIMESTAMP_CONTROL_TSENALL_Msk \ - (0x100UL) /*!< ETH TIMESTAMP_CONTROL: TSENALL (Bitfield-Mask: 0x01) */ -#define ETH_TIMESTAMP_CONTROL_TSCTRLSSR_Pos \ - (9UL) /*!< ETH TIMESTAMP_CONTROL: TSCTRLSSR (Bit 9) */ -#define ETH_TIMESTAMP_CONTROL_TSCTRLSSR_Msk \ - (0x200UL) /*!< ETH TIMESTAMP_CONTROL: TSCTRLSSR (Bitfield-Mask: 0x01) */ -#define ETH_TIMESTAMP_CONTROL_TSVER2ENA_Pos \ - (10UL) /*!< ETH TIMESTAMP_CONTROL: TSVER2ENA (Bit 10) */ -#define ETH_TIMESTAMP_CONTROL_TSVER2ENA_Msk \ - (0x400UL) /*!< ETH TIMESTAMP_CONTROL: TSVER2ENA (Bitfield-Mask: 0x01) */ -#define ETH_TIMESTAMP_CONTROL_TSIPENA_Pos \ - (11UL) /*!< ETH TIMESTAMP_CONTROL: TSIPENA (Bit 11) */ -#define ETH_TIMESTAMP_CONTROL_TSIPENA_Msk \ - (0x800UL) /*!< ETH TIMESTAMP_CONTROL: TSIPENA (Bitfield-Mask: 0x01) */ -#define ETH_TIMESTAMP_CONTROL_TSIPV6ENA_Pos \ - (12UL) /*!< ETH TIMESTAMP_CONTROL: TSIPV6ENA (Bit 12) */ -#define ETH_TIMESTAMP_CONTROL_TSIPV6ENA_Msk \ - (0x1000UL) /*!< ETH TIMESTAMP_CONTROL: TSIPV6ENA (Bitfield-Mask: 0x01) */ -#define ETH_TIMESTAMP_CONTROL_TSIPV4ENA_Pos \ - (13UL) /*!< ETH TIMESTAMP_CONTROL: TSIPV4ENA (Bit 13) */ -#define ETH_TIMESTAMP_CONTROL_TSIPV4ENA_Msk \ - (0x2000UL) /*!< ETH TIMESTAMP_CONTROL: TSIPV4ENA (Bitfield-Mask: 0x01) */ -#define ETH_TIMESTAMP_CONTROL_TSEVNTENA_Pos \ - (14UL) /*!< ETH TIMESTAMP_CONTROL: TSEVNTENA (Bit 14) */ -#define ETH_TIMESTAMP_CONTROL_TSEVNTENA_Msk \ - (0x4000UL) /*!< ETH TIMESTAMP_CONTROL: TSEVNTENA (Bitfield-Mask: 0x01) */ -#define ETH_TIMESTAMP_CONTROL_TSMSTRENA_Pos \ - (15UL) /*!< ETH TIMESTAMP_CONTROL: TSMSTRENA (Bit 15) */ -#define ETH_TIMESTAMP_CONTROL_TSMSTRENA_Msk \ - (0x8000UL) /*!< ETH TIMESTAMP_CONTROL: TSMSTRENA (Bitfield-Mask: 0x01) */ -#define ETH_TIMESTAMP_CONTROL_SNAPTYPSEL_Pos \ - (16UL) /*!< ETH TIMESTAMP_CONTROL: SNAPTYPSEL (Bit 16) */ -#define ETH_TIMESTAMP_CONTROL_SNAPTYPSEL_Msk \ - (0x30000UL) /*!< ETH TIMESTAMP_CONTROL: SNAPTYPSEL (Bitfield-Mask: 0x03) */ -#define ETH_TIMESTAMP_CONTROL_TSENMACADDR_Pos \ - (18UL) /*!< ETH TIMESTAMP_CONTROL: TSENMACADDR (Bit 18) */ -#define ETH_TIMESTAMP_CONTROL_TSENMACADDR_Msk \ - (0x40000UL) /*!< ETH TIMESTAMP_CONTROL: TSENMACADDR (Bitfield-Mask: 0x01) */ - -/* -------------------------- ETH_SUB_SECOND_INCREMENT -------------------------- */ -#define ETH_SUB_SECOND_INCREMENT_SSINC_Pos \ - (0UL) /*!< ETH SUB_SECOND_INCREMENT: SSINC (Bit 0) */ -#define ETH_SUB_SECOND_INCREMENT_SSINC_Msk \ - (0xffUL) /*!< ETH SUB_SECOND_INCREMENT: SSINC (Bitfield-Mask: 0xff) */ - -/* --------------------------- ETH_SYSTEM_TIME_SECONDS -------------------------- */ -#define ETH_SYSTEM_TIME_SECONDS_TSS_Pos \ - (0UL) /*!< ETH SYSTEM_TIME_SECONDS: TSS (Bit 0) */ -#define ETH_SYSTEM_TIME_SECONDS_TSS_Msk \ - (0xffffffffUL) /*!< ETH SYSTEM_TIME_SECONDS: TSS (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------- ETH_SYSTEM_TIME_NANOSECONDS ------------------------ */ -#define ETH_SYSTEM_TIME_NANOSECONDS_TSSS_Pos \ - (0UL) /*!< ETH SYSTEM_TIME_NANOSECONDS: TSSS (Bit 0) */ -#define ETH_SYSTEM_TIME_NANOSECONDS_TSSS_Msk \ - (0x7fffffffUL) /*!< ETH SYSTEM_TIME_NANOSECONDS: TSSS (Bitfield-Mask: 0x7fffffff) */ - -/* ----------------------- ETH_SYSTEM_TIME_SECONDS_UPDATE ----------------------- */ -#define ETH_SYSTEM_TIME_SECONDS_UPDATE_TSS_Pos \ - (0UL) /*!< ETH SYSTEM_TIME_SECONDS_UPDATE: TSS (Bit 0) */ -#define ETH_SYSTEM_TIME_SECONDS_UPDATE_TSS_Msk \ - (0xffffffffUL) /*!< ETH SYSTEM_TIME_SECONDS_UPDATE: TSS (Bitfield-Mask: 0xffffffff) */ - -/* --------------------- ETH_SYSTEM_TIME_NANOSECONDS_UPDATE --------------------- */ -#define ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_Pos \ - (0UL) /*!< ETH SYSTEM_TIME_NANOSECONDS_UPDATE: TSSS (Bit 0) */ -#define ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_Msk \ - (0x7fffffffUL) /*!< ETH SYSTEM_TIME_NANOSECONDS_UPDATE: TSSS (Bitfield-Mask: 0x7fffffff) */ -#define ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_Pos \ - (31UL) /*!< ETH SYSTEM_TIME_NANOSECONDS_UPDATE: ADDSUB (Bit 31) */ -#define ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_Msk \ - (0x80000000UL) /*!< ETH SYSTEM_TIME_NANOSECONDS_UPDATE: ADDSUB (Bitfield-Mask: 0x01) */ - -/* ---------------------------- ETH_TIMESTAMP_ADDEND ---------------------------- */ -#define ETH_TIMESTAMP_ADDEND_TSAR_Pos \ - (0UL) /*!< ETH TIMESTAMP_ADDEND: TSAR (Bit 0) */ -#define ETH_TIMESTAMP_ADDEND_TSAR_Msk \ - (0xffffffffUL) /*!< ETH TIMESTAMP_ADDEND: TSAR (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------- ETH_TARGET_TIME_SECONDS -------------------------- */ -#define ETH_TARGET_TIME_SECONDS_TSTR_Pos \ - (0UL) /*!< ETH TARGET_TIME_SECONDS: TSTR (Bit 0) */ -#define ETH_TARGET_TIME_SECONDS_TSTR_Msk \ - (0xffffffffUL) /*!< ETH TARGET_TIME_SECONDS: TSTR (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------- ETH_TARGET_TIME_NANOSECONDS ------------------------ */ -#define ETH_TARGET_TIME_NANOSECONDS_TTSLO_Pos \ - (0UL) /*!< ETH TARGET_TIME_NANOSECONDS: TTSLO (Bit 0) */ -#define ETH_TARGET_TIME_NANOSECONDS_TTSLO_Msk \ - (0x7fffffffUL) /*!< ETH TARGET_TIME_NANOSECONDS: TTSLO (Bitfield-Mask: 0x7fffffff) */ -#define ETH_TARGET_TIME_NANOSECONDS_TRGTBUSY_Pos \ - (31UL) /*!< ETH TARGET_TIME_NANOSECONDS: TRGTBUSY (Bit 31) */ -#define ETH_TARGET_TIME_NANOSECONDS_TRGTBUSY_Msk \ - (0x80000000UL) /*!< ETH TARGET_TIME_NANOSECONDS: TRGTBUSY (Bitfield-Mask: 0x01) */ - -/* --------------------- ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS -------------------- */ -#define ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_Pos \ - (0UL) /*!< ETH SYSTEM_TIME_HIGHER_WORD_SECONDS: TSHWR (Bit 0) */ -#define ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_Msk \ - (0xffffUL) /*!< ETH SYSTEM_TIME_HIGHER_WORD_SECONDS: TSHWR (Bitfield-Mask: 0xffff) */ - -/* ---------------------------- ETH_TIMESTAMP_STATUS ---------------------------- */ -#define ETH_TIMESTAMP_STATUS_TSSOVF_Pos \ - (0UL) /*!< ETH TIMESTAMP_STATUS: TSSOVF (Bit 0) */ -#define ETH_TIMESTAMP_STATUS_TSSOVF_Msk \ - (0x1UL) /*!< ETH TIMESTAMP_STATUS: TSSOVF (Bitfield-Mask: 0x01) */ -#define ETH_TIMESTAMP_STATUS_TSTARGT_Pos \ - (1UL) /*!< ETH TIMESTAMP_STATUS: TSTARGT (Bit 1) */ -#define ETH_TIMESTAMP_STATUS_TSTARGT_Msk \ - (0x2UL) /*!< ETH TIMESTAMP_STATUS: TSTARGT (Bitfield-Mask: 0x01) */ -#define ETH_TIMESTAMP_STATUS_TSTRGTERR_Pos \ - (3UL) /*!< ETH TIMESTAMP_STATUS: TSTRGTERR (Bit 3) */ -#define ETH_TIMESTAMP_STATUS_TSTRGTERR_Msk \ - (0x8UL) /*!< ETH TIMESTAMP_STATUS: TSTRGTERR (Bitfield-Mask: 0x01) */ -#define ETH_TIMESTAMP_STATUS_TSTARGT1_Pos \ - (4UL) /*!< ETH TIMESTAMP_STATUS: TSTARGT1 (Bit 4) */ -#define ETH_TIMESTAMP_STATUS_TSTARGT1_Msk \ - (0x10UL) /*!< ETH TIMESTAMP_STATUS: TSTARGT1 (Bitfield-Mask: 0x01) */ -#define ETH_TIMESTAMP_STATUS_TSTRGTERR1_Pos \ - (5UL) /*!< ETH TIMESTAMP_STATUS: TSTRGTERR1 (Bit 5) */ -#define ETH_TIMESTAMP_STATUS_TSTRGTERR1_Msk \ - (0x20UL) /*!< ETH TIMESTAMP_STATUS: TSTRGTERR1 (Bitfield-Mask: 0x01) */ -#define ETH_TIMESTAMP_STATUS_TSTARGT2_Pos \ - (6UL) /*!< ETH TIMESTAMP_STATUS: TSTARGT2 (Bit 6) */ -#define ETH_TIMESTAMP_STATUS_TSTARGT2_Msk \ - (0x40UL) /*!< ETH TIMESTAMP_STATUS: TSTARGT2 (Bitfield-Mask: 0x01) */ -#define ETH_TIMESTAMP_STATUS_TSTRGTERR2_Pos \ - (7UL) /*!< ETH TIMESTAMP_STATUS: TSTRGTERR2 (Bit 7) */ -#define ETH_TIMESTAMP_STATUS_TSTRGTERR2_Msk \ - (0x80UL) /*!< ETH TIMESTAMP_STATUS: TSTRGTERR2 (Bitfield-Mask: 0x01) */ -#define ETH_TIMESTAMP_STATUS_TSTARGT3_Pos \ - (8UL) /*!< ETH TIMESTAMP_STATUS: TSTARGT3 (Bit 8) */ -#define ETH_TIMESTAMP_STATUS_TSTARGT3_Msk \ - (0x100UL) /*!< ETH TIMESTAMP_STATUS: TSTARGT3 (Bitfield-Mask: 0x01) */ -#define ETH_TIMESTAMP_STATUS_TSTRGTERR3_Pos \ - (9UL) /*!< ETH TIMESTAMP_STATUS: TSTRGTERR3 (Bit 9) */ -#define ETH_TIMESTAMP_STATUS_TSTRGTERR3_Msk \ - (0x200UL) /*!< ETH TIMESTAMP_STATUS: TSTRGTERR3 (Bitfield-Mask: 0x01) */ - -/* ------------------------------- ETH_PPS_CONTROL ------------------------------ */ -#define ETH_PPS_CONTROL_PPSCTRL_PPSCMD_Pos \ - (0UL) /*!< ETH PPS_CONTROL: PPSCTRL_PPSCMD (Bit 0) */ -#define ETH_PPS_CONTROL_PPSCTRL_PPSCMD_Msk \ - (0xfUL) /*!< ETH PPS_CONTROL: PPSCTRL_PPSCMD (Bitfield-Mask: 0x0f) */ -#define ETH_PPS_CONTROL_PPSEN0_Pos \ - (4UL) /*!< ETH PPS_CONTROL: PPSEN0 (Bit 4) */ -#define ETH_PPS_CONTROL_PPSEN0_Msk \ - (0x10UL) /*!< ETH PPS_CONTROL: PPSEN0 (Bitfield-Mask: 0x01) */ -#define ETH_PPS_CONTROL_TRGTMODSEL0_Pos \ - (5UL) /*!< ETH PPS_CONTROL: TRGTMODSEL0 (Bit 5) */ -#define ETH_PPS_CONTROL_TRGTMODSEL0_Msk \ - (0x60UL) /*!< ETH PPS_CONTROL: TRGTMODSEL0 (Bitfield-Mask: 0x03) */ -#define ETH_PPS_CONTROL_PPSCMD1_Pos \ - (8UL) /*!< ETH PPS_CONTROL: PPSCMD1 (Bit 8) */ -#define ETH_PPS_CONTROL_PPSCMD1_Msk \ - (0x700UL) /*!< ETH PPS_CONTROL: PPSCMD1 (Bitfield-Mask: 0x07) */ -#define ETH_PPS_CONTROL_TRGTMODSEL1_Pos \ - (13UL) /*!< ETH PPS_CONTROL: TRGTMODSEL1 (Bit 13) */ -#define ETH_PPS_CONTROL_TRGTMODSEL1_Msk \ - (0x6000UL) /*!< ETH PPS_CONTROL: TRGTMODSEL1 (Bitfield-Mask: 0x03) */ -#define ETH_PPS_CONTROL_PPSCMD2_Pos \ - (16UL) /*!< ETH PPS_CONTROL: PPSCMD2 (Bit 16) */ -#define ETH_PPS_CONTROL_PPSCMD2_Msk \ - (0x70000UL) /*!< ETH PPS_CONTROL: PPSCMD2 (Bitfield-Mask: 0x07) */ -#define ETH_PPS_CONTROL_TRGTMODSEL2_Pos \ - (21UL) /*!< ETH PPS_CONTROL: TRGTMODSEL2 (Bit 21) */ -#define ETH_PPS_CONTROL_TRGTMODSEL2_Msk \ - (0x600000UL) /*!< ETH PPS_CONTROL: TRGTMODSEL2 (Bitfield-Mask: 0x03) */ -#define ETH_PPS_CONTROL_PPSCMD3_Pos \ - (24UL) /*!< ETH PPS_CONTROL: PPSCMD3 (Bit 24) */ -#define ETH_PPS_CONTROL_PPSCMD3_Msk \ - (0x7000000UL) /*!< ETH PPS_CONTROL: PPSCMD3 (Bitfield-Mask: 0x07) */ -#define ETH_PPS_CONTROL_TRGTMODSEL3_Pos \ - (29UL) /*!< ETH PPS_CONTROL: TRGTMODSEL3 (Bit 29) */ -#define ETH_PPS_CONTROL_TRGTMODSEL3_Msk \ - (0x60000000UL) /*!< ETH PPS_CONTROL: TRGTMODSEL3 (Bitfield-Mask: 0x03) */ - -/* -------------------------------- ETH_BUS_MODE -------------------------------- */ -#define ETH_BUS_MODE_SWR_Pos \ - (0UL) /*!< ETH BUS_MODE: SWR (Bit 0) */ -#define ETH_BUS_MODE_SWR_Msk \ - (0x1UL) /*!< ETH BUS_MODE: SWR (Bitfield-Mask: 0x01) */ -#define ETH_BUS_MODE_DA_Pos \ - (1UL) /*!< ETH BUS_MODE: DA (Bit 1) */ -#define ETH_BUS_MODE_DA_Msk \ - (0x2UL) /*!< ETH BUS_MODE: DA (Bitfield-Mask: 0x01) */ -#define ETH_BUS_MODE_DSL_Pos \ - (2UL) /*!< ETH BUS_MODE: DSL (Bit 2) */ -#define ETH_BUS_MODE_DSL_Msk \ - (0x7cUL) /*!< ETH BUS_MODE: DSL (Bitfield-Mask: 0x1f) */ -#define ETH_BUS_MODE_ATDS_Pos \ - (7UL) /*!< ETH BUS_MODE: ATDS (Bit 7) */ -#define ETH_BUS_MODE_ATDS_Msk \ - (0x80UL) /*!< ETH BUS_MODE: ATDS (Bitfield-Mask: 0x01) */ -#define ETH_BUS_MODE_PBL_Pos \ - (8UL) /*!< ETH BUS_MODE: PBL (Bit 8) */ -#define ETH_BUS_MODE_PBL_Msk \ - (0x3f00UL) /*!< ETH BUS_MODE: PBL (Bitfield-Mask: 0x3f) */ -#define ETH_BUS_MODE_PR_Pos \ - (14UL) /*!< ETH BUS_MODE: PR (Bit 14) */ -#define ETH_BUS_MODE_PR_Msk \ - (0xc000UL) /*!< ETH BUS_MODE: PR (Bitfield-Mask: 0x03) */ -#define ETH_BUS_MODE_FB_Pos \ - (16UL) /*!< ETH BUS_MODE: FB (Bit 16) */ -#define ETH_BUS_MODE_FB_Msk \ - (0x10000UL) /*!< ETH BUS_MODE: FB (Bitfield-Mask: 0x01) */ -#define ETH_BUS_MODE_RPBL_Pos \ - (17UL) /*!< ETH BUS_MODE: RPBL (Bit 17) */ -#define ETH_BUS_MODE_RPBL_Msk \ - (0x7e0000UL) /*!< ETH BUS_MODE: RPBL (Bitfield-Mask: 0x3f) */ -#define ETH_BUS_MODE_USP_Pos \ - (23UL) /*!< ETH BUS_MODE: USP (Bit 23) */ -#define ETH_BUS_MODE_USP_Msk \ - (0x800000UL) /*!< ETH BUS_MODE: USP (Bitfield-Mask: 0x01) */ -#define ETH_BUS_MODE_EIGHTxPBL_Pos \ - (24UL) /*!< ETH BUS_MODE: EIGHTxPBL (Bit 24) */ -#define ETH_BUS_MODE_EIGHTxPBL_Msk \ - (0x1000000UL) /*!< ETH BUS_MODE: EIGHTxPBL (Bitfield-Mask: 0x01) */ -#define ETH_BUS_MODE_AAL_Pos \ - (25UL) /*!< ETH BUS_MODE: AAL (Bit 25) */ -#define ETH_BUS_MODE_AAL_Msk \ - (0x2000000UL) /*!< ETH BUS_MODE: AAL (Bitfield-Mask: 0x01) */ -#define ETH_BUS_MODE_MB_Pos \ - (26UL) /*!< ETH BUS_MODE: MB (Bit 26) */ -#define ETH_BUS_MODE_MB_Msk \ - (0x4000000UL) /*!< ETH BUS_MODE: MB (Bitfield-Mask: 0x01) */ -#define ETH_BUS_MODE_TXPR_Pos \ - (27UL) /*!< ETH BUS_MODE: TXPR (Bit 27) */ -#define ETH_BUS_MODE_TXPR_Msk \ - (0x8000000UL) /*!< ETH BUS_MODE: TXPR (Bitfield-Mask: 0x01) */ -#define ETH_BUS_MODE_PRWG_Pos \ - (28UL) /*!< ETH BUS_MODE: PRWG (Bit 28) */ -#define ETH_BUS_MODE_PRWG_Msk \ - (0x30000000UL) /*!< ETH BUS_MODE: PRWG (Bitfield-Mask: 0x03) */ - -/* -------------------------- ETH_TRANSMIT_POLL_DEMAND -------------------------- */ -#define ETH_TRANSMIT_POLL_DEMAND_TPD_Pos \ - (0UL) /*!< ETH TRANSMIT_POLL_DEMAND: TPD (Bit 0) */ -#define ETH_TRANSMIT_POLL_DEMAND_TPD_Msk \ - (0xffffffffUL) /*!< ETH TRANSMIT_POLL_DEMAND: TPD (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------- ETH_RECEIVE_POLL_DEMAND -------------------------- */ -#define ETH_RECEIVE_POLL_DEMAND_RPD_Pos \ - (0UL) /*!< ETH RECEIVE_POLL_DEMAND: RPD (Bit 0) */ -#define ETH_RECEIVE_POLL_DEMAND_RPD_Msk \ - (0xffffffffUL) /*!< ETH RECEIVE_POLL_DEMAND: RPD (Bitfield-Mask: 0xffffffff) */ - -/* --------------------- ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS -------------------- */ -#define ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_32bit_Pos \ - (2UL) /*!< ETH RECEIVE_DESCRIPTOR_LIST_ADDRESS: RDESLA_32bit (Bit 2) */ -#define ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_32bit_Msk \ - (0xfffffffcUL) /*!< ETH RECEIVE_DESCRIPTOR_LIST_ADDRESS: RDESLA_32bit (Bitfield-Mask: \ - 0x3fffffff) */ - -/* -------------------- ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS -------------------- */ -#define ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_32bit_Pos \ - (2UL) /*!< ETH TRANSMIT_DESCRIPTOR_LIST_ADDRESS: TDESLA_32bit (Bit 2) */ -#define ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_32bit_Msk \ - (0xfffffffcUL) /*!< ETH TRANSMIT_DESCRIPTOR_LIST_ADDRESS: TDESLA_32bit (Bitfield-Mask: \ - 0x3fffffff) */ - -/* --------------------------------- ETH_STATUS --------------------------------- */ -#define ETH_STATUS_TI_Pos (0UL) /*!< ETH STATUS: TI (Bit 0) */ -#define ETH_STATUS_TI_Msk \ - (0x1UL) /*!< ETH STATUS: TI (Bitfield-Mask: 0x01) */ -#define ETH_STATUS_TPS_Pos (1UL) /*!< ETH STATUS: TPS (Bit 1) */ -#define ETH_STATUS_TPS_Msk \ - (0x2UL) /*!< ETH STATUS: TPS (Bitfield-Mask: 0x01) */ -#define ETH_STATUS_TU_Pos (2UL) /*!< ETH STATUS: TU (Bit 2) */ -#define ETH_STATUS_TU_Msk \ - (0x4UL) /*!< ETH STATUS: TU (Bitfield-Mask: 0x01) */ -#define ETH_STATUS_TJT_Pos (3UL) /*!< ETH STATUS: TJT (Bit 3) */ -#define ETH_STATUS_TJT_Msk \ - (0x8UL) /*!< ETH STATUS: TJT (Bitfield-Mask: 0x01) */ -#define ETH_STATUS_OVF_Pos (4UL) /*!< ETH STATUS: OVF (Bit 4) */ -#define ETH_STATUS_OVF_Msk \ - (0x10UL) /*!< ETH STATUS: OVF (Bitfield-Mask: 0x01) */ -#define ETH_STATUS_UNF_Pos (5UL) /*!< ETH STATUS: UNF (Bit 5) */ -#define ETH_STATUS_UNF_Msk \ - (0x20UL) /*!< ETH STATUS: UNF (Bitfield-Mask: 0x01) */ -#define ETH_STATUS_RI_Pos (6UL) /*!< ETH STATUS: RI (Bit 6) */ -#define ETH_STATUS_RI_Msk \ - (0x40UL) /*!< ETH STATUS: RI (Bitfield-Mask: 0x01) */ -#define ETH_STATUS_RU_Pos (7UL) /*!< ETH STATUS: RU (Bit 7) */ -#define ETH_STATUS_RU_Msk \ - (0x80UL) /*!< ETH STATUS: RU (Bitfield-Mask: 0x01) */ -#define ETH_STATUS_RPS_Pos (8UL) /*!< ETH STATUS: RPS (Bit 8) */ -#define ETH_STATUS_RPS_Msk \ - (0x100UL) /*!< ETH STATUS: RPS (Bitfield-Mask: 0x01) */ -#define ETH_STATUS_RWT_Pos (9UL) /*!< ETH STATUS: RWT (Bit 9) */ -#define ETH_STATUS_RWT_Msk \ - (0x200UL) /*!< ETH STATUS: RWT (Bitfield-Mask: 0x01) */ -#define ETH_STATUS_ETI_Pos \ - (10UL) /*!< ETH STATUS: ETI (Bit 10) */ -#define ETH_STATUS_ETI_Msk \ - (0x400UL) /*!< ETH STATUS: ETI (Bitfield-Mask: 0x01) */ -#define ETH_STATUS_FBI_Pos \ - (13UL) /*!< ETH STATUS: FBI (Bit 13) */ -#define ETH_STATUS_FBI_Msk \ - (0x2000UL) /*!< ETH STATUS: FBI (Bitfield-Mask: 0x01) */ -#define ETH_STATUS_ERI_Pos \ - (14UL) /*!< ETH STATUS: ERI (Bit 14) */ -#define ETH_STATUS_ERI_Msk \ - (0x4000UL) /*!< ETH STATUS: ERI (Bitfield-Mask: 0x01) */ -#define ETH_STATUS_AIS_Pos \ - (15UL) /*!< ETH STATUS: AIS (Bit 15) */ -#define ETH_STATUS_AIS_Msk \ - (0x8000UL) /*!< ETH STATUS: AIS (Bitfield-Mask: 0x01) */ -#define ETH_STATUS_NIS_Pos \ - (16UL) /*!< ETH STATUS: NIS (Bit 16) */ -#define ETH_STATUS_NIS_Msk \ - (0x10000UL) /*!< ETH STATUS: NIS (Bitfield-Mask: 0x01) */ -#define ETH_STATUS_RS_Pos (17UL) /*!< ETH STATUS: RS (Bit 17) */ -#define ETH_STATUS_RS_Msk \ - (0xe0000UL) /*!< ETH STATUS: RS (Bitfield-Mask: 0x07) */ -#define ETH_STATUS_TS_Pos (20UL) /*!< ETH STATUS: TS (Bit 20) */ -#define ETH_STATUS_TS_Msk \ - (0x700000UL) /*!< ETH STATUS: TS (Bitfield-Mask: 0x07) */ -#define ETH_STATUS_EB_Pos (23UL) /*!< ETH STATUS: EB (Bit 23) */ -#define ETH_STATUS_EB_Msk \ - (0x3800000UL) /*!< ETH STATUS: EB (Bitfield-Mask: 0x07) */ -#define ETH_STATUS_EMI_Pos \ - (27UL) /*!< ETH STATUS: EMI (Bit 27) */ -#define ETH_STATUS_EMI_Msk \ - (0x8000000UL) /*!< ETH STATUS: EMI (Bitfield-Mask: 0x01) */ -#define ETH_STATUS_EPI_Pos \ - (28UL) /*!< ETH STATUS: EPI (Bit 28) */ -#define ETH_STATUS_EPI_Msk \ - (0x10000000UL) /*!< ETH STATUS: EPI (Bitfield-Mask: 0x01) */ -#define ETH_STATUS_TTI_Pos \ - (29UL) /*!< ETH STATUS: TTI (Bit 29) */ -#define ETH_STATUS_TTI_Msk \ - (0x20000000UL) /*!< ETH STATUS: TTI (Bitfield-Mask: 0x01) */ - -/* ----------------------------- ETH_OPERATION_MODE ----------------------------- */ -#define ETH_OPERATION_MODE_SR_Pos \ - (1UL) /*!< ETH OPERATION_MODE: SR (Bit 1) */ -#define ETH_OPERATION_MODE_SR_Msk \ - (0x2UL) /*!< ETH OPERATION_MODE: SR (Bitfield-Mask: 0x01) */ -#define ETH_OPERATION_MODE_OSF_Pos \ - (2UL) /*!< ETH OPERATION_MODE: OSF (Bit 2) */ -#define ETH_OPERATION_MODE_OSF_Msk \ - (0x4UL) /*!< ETH OPERATION_MODE: OSF (Bitfield-Mask: 0x01) */ -#define ETH_OPERATION_MODE_RTC_Pos \ - (3UL) /*!< ETH OPERATION_MODE: RTC (Bit 3) */ -#define ETH_OPERATION_MODE_RTC_Msk \ - (0x18UL) /*!< ETH OPERATION_MODE: RTC (Bitfield-Mask: 0x03) */ -#define ETH_OPERATION_MODE_FUF_Pos \ - (6UL) /*!< ETH OPERATION_MODE: FUF (Bit 6) */ -#define ETH_OPERATION_MODE_FUF_Msk \ - (0x40UL) /*!< ETH OPERATION_MODE: FUF (Bitfield-Mask: 0x01) */ -#define ETH_OPERATION_MODE_FEF_Pos \ - (7UL) /*!< ETH OPERATION_MODE: FEF (Bit 7) */ -#define ETH_OPERATION_MODE_FEF_Msk \ - (0x80UL) /*!< ETH OPERATION_MODE: FEF (Bitfield-Mask: 0x01) */ -#define ETH_OPERATION_MODE_ST_Pos \ - (13UL) /*!< ETH OPERATION_MODE: ST (Bit 13) */ -#define ETH_OPERATION_MODE_ST_Msk \ - (0x2000UL) /*!< ETH OPERATION_MODE: ST (Bitfield-Mask: 0x01) */ -#define ETH_OPERATION_MODE_TTC_Pos \ - (14UL) /*!< ETH OPERATION_MODE: TTC (Bit 14) */ -#define ETH_OPERATION_MODE_TTC_Msk \ - (0x1c000UL) /*!< ETH OPERATION_MODE: TTC (Bitfield-Mask: 0x07) */ -#define ETH_OPERATION_MODE_FTF_Pos \ - (20UL) /*!< ETH OPERATION_MODE: FTF (Bit 20) */ -#define ETH_OPERATION_MODE_FTF_Msk \ - (0x100000UL) /*!< ETH OPERATION_MODE: FTF (Bitfield-Mask: 0x01) */ -#define ETH_OPERATION_MODE_TSF_Pos \ - (21UL) /*!< ETH OPERATION_MODE: TSF (Bit 21) */ -#define ETH_OPERATION_MODE_TSF_Msk \ - (0x200000UL) /*!< ETH OPERATION_MODE: TSF (Bitfield-Mask: 0x01) */ -#define ETH_OPERATION_MODE_DFF_Pos \ - (24UL) /*!< ETH OPERATION_MODE: DFF (Bit 24) */ -#define ETH_OPERATION_MODE_DFF_Msk \ - (0x1000000UL) /*!< ETH OPERATION_MODE: DFF (Bitfield-Mask: 0x01) */ -#define ETH_OPERATION_MODE_RSF_Pos \ - (25UL) /*!< ETH OPERATION_MODE: RSF (Bit 25) */ -#define ETH_OPERATION_MODE_RSF_Msk \ - (0x2000000UL) /*!< ETH OPERATION_MODE: RSF (Bitfield-Mask: 0x01) */ -#define ETH_OPERATION_MODE_DT_Pos \ - (26UL) /*!< ETH OPERATION_MODE: DT (Bit 26) */ -#define ETH_OPERATION_MODE_DT_Msk \ - (0x4000000UL) /*!< ETH OPERATION_MODE: DT (Bitfield-Mask: 0x01) */ - -/* ---------------------------- ETH_INTERRUPT_ENABLE ---------------------------- */ -#define ETH_INTERRUPT_ENABLE_TIE_Pos \ - (0UL) /*!< ETH INTERRUPT_ENABLE: TIE (Bit 0) */ -#define ETH_INTERRUPT_ENABLE_TIE_Msk \ - (0x1UL) /*!< ETH INTERRUPT_ENABLE: TIE (Bitfield-Mask: 0x01) */ -#define ETH_INTERRUPT_ENABLE_TSE_Pos \ - (1UL) /*!< ETH INTERRUPT_ENABLE: TSE (Bit 1) */ -#define ETH_INTERRUPT_ENABLE_TSE_Msk \ - (0x2UL) /*!< ETH INTERRUPT_ENABLE: TSE (Bitfield-Mask: 0x01) */ -#define ETH_INTERRUPT_ENABLE_TUE_Pos \ - (2UL) /*!< ETH INTERRUPT_ENABLE: TUE (Bit 2) */ -#define ETH_INTERRUPT_ENABLE_TUE_Msk \ - (0x4UL) /*!< ETH INTERRUPT_ENABLE: TUE (Bitfield-Mask: 0x01) */ -#define ETH_INTERRUPT_ENABLE_TJE_Pos \ - (3UL) /*!< ETH INTERRUPT_ENABLE: TJE (Bit 3) */ -#define ETH_INTERRUPT_ENABLE_TJE_Msk \ - (0x8UL) /*!< ETH INTERRUPT_ENABLE: TJE (Bitfield-Mask: 0x01) */ -#define ETH_INTERRUPT_ENABLE_OVE_Pos \ - (4UL) /*!< ETH INTERRUPT_ENABLE: OVE (Bit 4) */ -#define ETH_INTERRUPT_ENABLE_OVE_Msk \ - (0x10UL) /*!< ETH INTERRUPT_ENABLE: OVE (Bitfield-Mask: 0x01) */ -#define ETH_INTERRUPT_ENABLE_UNE_Pos \ - (5UL) /*!< ETH INTERRUPT_ENABLE: UNE (Bit 5) */ -#define ETH_INTERRUPT_ENABLE_UNE_Msk \ - (0x20UL) /*!< ETH INTERRUPT_ENABLE: UNE (Bitfield-Mask: 0x01) */ -#define ETH_INTERRUPT_ENABLE_RIE_Pos \ - (6UL) /*!< ETH INTERRUPT_ENABLE: RIE (Bit 6) */ -#define ETH_INTERRUPT_ENABLE_RIE_Msk \ - (0x40UL) /*!< ETH INTERRUPT_ENABLE: RIE (Bitfield-Mask: 0x01) */ -#define ETH_INTERRUPT_ENABLE_RUE_Pos \ - (7UL) /*!< ETH INTERRUPT_ENABLE: RUE (Bit 7) */ -#define ETH_INTERRUPT_ENABLE_RUE_Msk \ - (0x80UL) /*!< ETH INTERRUPT_ENABLE: RUE (Bitfield-Mask: 0x01) */ -#define ETH_INTERRUPT_ENABLE_RSE_Pos \ - (8UL) /*!< ETH INTERRUPT_ENABLE: RSE (Bit 8) */ -#define ETH_INTERRUPT_ENABLE_RSE_Msk \ - (0x100UL) /*!< ETH INTERRUPT_ENABLE: RSE (Bitfield-Mask: 0x01) */ -#define ETH_INTERRUPT_ENABLE_RWE_Pos \ - (9UL) /*!< ETH INTERRUPT_ENABLE: RWE (Bit 9) */ -#define ETH_INTERRUPT_ENABLE_RWE_Msk \ - (0x200UL) /*!< ETH INTERRUPT_ENABLE: RWE (Bitfield-Mask: 0x01) */ -#define ETH_INTERRUPT_ENABLE_ETE_Pos \ - (10UL) /*!< ETH INTERRUPT_ENABLE: ETE (Bit 10) */ -#define ETH_INTERRUPT_ENABLE_ETE_Msk \ - (0x400UL) /*!< ETH INTERRUPT_ENABLE: ETE (Bitfield-Mask: 0x01) */ -#define ETH_INTERRUPT_ENABLE_FBE_Pos \ - (13UL) /*!< ETH INTERRUPT_ENABLE: FBE (Bit 13) */ -#define ETH_INTERRUPT_ENABLE_FBE_Msk \ - (0x2000UL) /*!< ETH INTERRUPT_ENABLE: FBE (Bitfield-Mask: 0x01) */ -#define ETH_INTERRUPT_ENABLE_ERE_Pos \ - (14UL) /*!< ETH INTERRUPT_ENABLE: ERE (Bit 14) */ -#define ETH_INTERRUPT_ENABLE_ERE_Msk \ - (0x4000UL) /*!< ETH INTERRUPT_ENABLE: ERE (Bitfield-Mask: 0x01) */ -#define ETH_INTERRUPT_ENABLE_AIE_Pos \ - (15UL) /*!< ETH INTERRUPT_ENABLE: AIE (Bit 15) */ -#define ETH_INTERRUPT_ENABLE_AIE_Msk \ - (0x8000UL) /*!< ETH INTERRUPT_ENABLE: AIE (Bitfield-Mask: 0x01) */ -#define ETH_INTERRUPT_ENABLE_NIE_Pos \ - (16UL) /*!< ETH INTERRUPT_ENABLE: NIE (Bit 16) */ -#define ETH_INTERRUPT_ENABLE_NIE_Msk \ - (0x10000UL) /*!< ETH INTERRUPT_ENABLE: NIE (Bitfield-Mask: 0x01) */ - -/* ---------------- ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER ---------------- */ -#define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT_Pos \ - (0UL) /*!< ETH MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER: MISFRMCNT (Bit 0) */ -#define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT_Msk \ - (0xffffUL) /*!< ETH MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER: MISFRMCNT (Bitfield-Mask: \ - 0xffff) */ -#define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF_Pos \ - (16UL) /*!< ETH MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER: MISCNTOVF (Bit 16) */ -#define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF_Msk \ - (0x10000UL) /*!< ETH MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER: MISCNTOVF (Bitfield-Mask: 0x01) \ - */ -#define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT_Pos \ - (17UL) /*!< ETH MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER: OVFFRMCNT (Bit 17) */ -#define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT_Msk \ - (0xffe0000UL) /*!< ETH MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER: OVFFRMCNT (Bitfield-Mask: \ - 0x7ff) */ -#define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF_Pos \ - (28UL) /*!< ETH MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER: OVFCNTOVF (Bit 28) */ -#define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF_Msk \ - (0x10000000UL) /*!< ETH MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER: OVFCNTOVF (Bitfield-Mask: \ - 0x01) */ - -/* -------------------- ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER -------------------- */ -#define ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT_Pos \ - (0UL) /*!< ETH RECEIVE_INTERRUPT_WATCHDOG_TIMER: RIWT (Bit 0) */ -#define ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT_Msk \ - (0xffUL) /*!< ETH RECEIVE_INTERRUPT_WATCHDOG_TIMER: RIWT (Bitfield-Mask: 0xff) */ - -/* ------------------------------- ETH_AHB_STATUS ------------------------------- */ -#define ETH_AHB_STATUS_AHBMS_Pos \ - (0UL) /*!< ETH AHB_STATUS: AHBMS (Bit 0) */ -#define ETH_AHB_STATUS_AHBMS_Msk \ - (0x1UL) /*!< ETH AHB_STATUS: AHBMS (Bitfield-Mask: 0x01) */ - -/* -------------------- ETH_CURRENT_HOST_TRANSMIT_DESCRIPTOR -------------------- */ -#define ETH_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR_Pos \ - (0UL) /*!< ETH CURRENT_HOST_TRANSMIT_DESCRIPTOR: CURTDESAPTR (Bit 0) */ -#define ETH_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR_Msk \ - (0xffffffffUL) /*!< ETH CURRENT_HOST_TRANSMIT_DESCRIPTOR: CURTDESAPTR (Bitfield-Mask: \ - 0xffffffff) */ - -/* --------------------- ETH_CURRENT_HOST_RECEIVE_DESCRIPTOR -------------------- */ -#define ETH_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR_Pos \ - (0UL) /*!< ETH CURRENT_HOST_RECEIVE_DESCRIPTOR: CURRDESAPTR (Bit 0) */ -#define ETH_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR_Msk \ - (0xffffffffUL) /*!< ETH CURRENT_HOST_RECEIVE_DESCRIPTOR: CURRDESAPTR (Bitfield-Mask: \ - 0xffffffff) */ - -/* ------------------ ETH_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS ------------------ */ -#define ETH_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR_Pos \ - (0UL) /*!< ETH CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS: CURTBUFAPTR (Bit 0) */ -#define ETH_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR_Msk \ - (0xffffffffUL) /*!< ETH CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS: CURTBUFAPTR (Bitfield-Mask: \ - 0xffffffff) */ - -/* ------------------- ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS ------------------ */ -#define ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR_Pos \ - (0UL) /*!< ETH CURRENT_HOST_RECEIVE_BUFFER_ADDRESS: CURRBUFAPTR (Bit 0) */ -#define ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR_Msk \ - (0xffffffffUL) /*!< ETH CURRENT_HOST_RECEIVE_BUFFER_ADDRESS: CURRBUFAPTR (Bitfield-Mask: \ - 0xffffffff) */ - -/* ------------------------------- ETH_HW_FEATURE ------------------------------- */ -#define ETH_HW_FEATURE_MIISEL_Pos \ - (0UL) /*!< ETH HW_FEATURE: MIISEL (Bit 0) */ -#define ETH_HW_FEATURE_MIISEL_Msk \ - (0x1UL) /*!< ETH HW_FEATURE: MIISEL (Bitfield-Mask: 0x01) */ -#define ETH_HW_FEATURE_GMIISEL_Pos \ - (1UL) /*!< ETH HW_FEATURE: GMIISEL (Bit 1) */ -#define ETH_HW_FEATURE_GMIISEL_Msk \ - (0x2UL) /*!< ETH HW_FEATURE: GMIISEL (Bitfield-Mask: 0x01) */ -#define ETH_HW_FEATURE_HDSEL_Pos \ - (2UL) /*!< ETH HW_FEATURE: HDSEL (Bit 2) */ -#define ETH_HW_FEATURE_HDSEL_Msk \ - (0x4UL) /*!< ETH HW_FEATURE: HDSEL (Bitfield-Mask: 0x01) */ -#define ETH_HW_FEATURE_EXTHASHEN_Pos \ - (3UL) /*!< ETH HW_FEATURE: EXTHASHEN (Bit 3) */ -#define ETH_HW_FEATURE_EXTHASHEN_Msk \ - (0x8UL) /*!< ETH HW_FEATURE: EXTHASHEN (Bitfield-Mask: 0x01) */ -#define ETH_HW_FEATURE_HASHSEL_Pos \ - (4UL) /*!< ETH HW_FEATURE: HASHSEL (Bit 4) */ -#define ETH_HW_FEATURE_HASHSEL_Msk \ - (0x10UL) /*!< ETH HW_FEATURE: HASHSEL (Bitfield-Mask: 0x01) */ -#define ETH_HW_FEATURE_ADDMACADRSEL_Pos \ - (5UL) /*!< ETH HW_FEATURE: ADDMACADRSEL (Bit 5) */ -#define ETH_HW_FEATURE_ADDMACADRSEL_Msk \ - (0x20UL) /*!< ETH HW_FEATURE: ADDMACADRSEL (Bitfield-Mask: 0x01) */ -#define ETH_HW_FEATURE_PCSSEL_Pos \ - (6UL) /*!< ETH HW_FEATURE: PCSSEL (Bit 6) */ -#define ETH_HW_FEATURE_PCSSEL_Msk \ - (0x40UL) /*!< ETH HW_FEATURE: PCSSEL (Bitfield-Mask: 0x01) */ -#define ETH_HW_FEATURE_L3L4FLTREN_Pos \ - (7UL) /*!< ETH HW_FEATURE: L3L4FLTREN (Bit 7) */ -#define ETH_HW_FEATURE_L3L4FLTREN_Msk \ - (0x80UL) /*!< ETH HW_FEATURE: L3L4FLTREN (Bitfield-Mask: 0x01) */ -#define ETH_HW_FEATURE_SMASEL_Pos \ - (8UL) /*!< ETH HW_FEATURE: SMASEL (Bit 8) */ -#define ETH_HW_FEATURE_SMASEL_Msk \ - (0x100UL) /*!< ETH HW_FEATURE: SMASEL (Bitfield-Mask: 0x01) */ -#define ETH_HW_FEATURE_RWKSEL_Pos \ - (9UL) /*!< ETH HW_FEATURE: RWKSEL (Bit 9) */ -#define ETH_HW_FEATURE_RWKSEL_Msk \ - (0x200UL) /*!< ETH HW_FEATURE: RWKSEL (Bitfield-Mask: 0x01) */ -#define ETH_HW_FEATURE_MGKSEL_Pos \ - (10UL) /*!< ETH HW_FEATURE: MGKSEL (Bit 10) */ -#define ETH_HW_FEATURE_MGKSEL_Msk \ - (0x400UL) /*!< ETH HW_FEATURE: MGKSEL (Bitfield-Mask: 0x01) */ -#define ETH_HW_FEATURE_MMCSEL_Pos \ - (11UL) /*!< ETH HW_FEATURE: MMCSEL (Bit 11) */ -#define ETH_HW_FEATURE_MMCSEL_Msk \ - (0x800UL) /*!< ETH HW_FEATURE: MMCSEL (Bitfield-Mask: 0x01) */ -#define ETH_HW_FEATURE_TSVER1SEL_Pos \ - (12UL) /*!< ETH HW_FEATURE: TSVER1SEL (Bit 12) */ -#define ETH_HW_FEATURE_TSVER1SEL_Msk \ - (0x1000UL) /*!< ETH HW_FEATURE: TSVER1SEL (Bitfield-Mask: 0x01) */ -#define ETH_HW_FEATURE_TSVER2SEL_Pos \ - (13UL) /*!< ETH HW_FEATURE: TSVER2SEL (Bit 13) */ -#define ETH_HW_FEATURE_TSVER2SEL_Msk \ - (0x2000UL) /*!< ETH HW_FEATURE: TSVER2SEL (Bitfield-Mask: 0x01) */ -#define ETH_HW_FEATURE_EEESEL_Pos \ - (14UL) /*!< ETH HW_FEATURE: EEESEL (Bit 14) */ -#define ETH_HW_FEATURE_EEESEL_Msk \ - (0x4000UL) /*!< ETH HW_FEATURE: EEESEL (Bitfield-Mask: 0x01) */ -#define ETH_HW_FEATURE_AVSEL_Pos \ - (15UL) /*!< ETH HW_FEATURE: AVSEL (Bit 15) */ -#define ETH_HW_FEATURE_AVSEL_Msk \ - (0x8000UL) /*!< ETH HW_FEATURE: AVSEL (Bitfield-Mask: 0x01) */ -#define ETH_HW_FEATURE_TXCOESEL_Pos \ - (16UL) /*!< ETH HW_FEATURE: TXCOESEL (Bit 16) */ -#define ETH_HW_FEATURE_TXCOESEL_Msk \ - (0x10000UL) /*!< ETH HW_FEATURE: TXCOESEL (Bitfield-Mask: 0x01) */ -#define ETH_HW_FEATURE_RXTYP1COE_Pos \ - (17UL) /*!< ETH HW_FEATURE: RXTYP1COE (Bit 17) */ -#define ETH_HW_FEATURE_RXTYP1COE_Msk \ - (0x20000UL) /*!< ETH HW_FEATURE: RXTYP1COE (Bitfield-Mask: 0x01) */ -#define ETH_HW_FEATURE_RXTYP2COE_Pos \ - (18UL) /*!< ETH HW_FEATURE: RXTYP2COE (Bit 18) */ -#define ETH_HW_FEATURE_RXTYP2COE_Msk \ - (0x40000UL) /*!< ETH HW_FEATURE: RXTYP2COE (Bitfield-Mask: 0x01) */ -#define ETH_HW_FEATURE_RXFIFOSIZE_Pos \ - (19UL) /*!< ETH HW_FEATURE: RXFIFOSIZE (Bit 19) */ -#define ETH_HW_FEATURE_RXFIFOSIZE_Msk \ - (0x80000UL) /*!< ETH HW_FEATURE: RXFIFOSIZE (Bitfield-Mask: 0x01) */ -#define ETH_HW_FEATURE_RXCHCNT_Pos \ - (20UL) /*!< ETH HW_FEATURE: RXCHCNT (Bit 20) */ -#define ETH_HW_FEATURE_RXCHCNT_Msk \ - (0x300000UL) /*!< ETH HW_FEATURE: RXCHCNT (Bitfield-Mask: 0x03) */ -#define ETH_HW_FEATURE_TXCHCNT_Pos \ - (22UL) /*!< ETH HW_FEATURE: TXCHCNT (Bit 22) */ -#define ETH_HW_FEATURE_TXCHCNT_Msk \ - (0xc00000UL) /*!< ETH HW_FEATURE: TXCHCNT (Bitfield-Mask: 0x03) */ -#define ETH_HW_FEATURE_ENHDESSEL_Pos \ - (24UL) /*!< ETH HW_FEATURE: ENHDESSEL (Bit 24) */ -#define ETH_HW_FEATURE_ENHDESSEL_Msk \ - (0x1000000UL) /*!< ETH HW_FEATURE: ENHDESSEL (Bitfield-Mask: 0x01) */ -#define ETH_HW_FEATURE_INTTSEN_Pos \ - (25UL) /*!< ETH HW_FEATURE: INTTSEN (Bit 25) */ -#define ETH_HW_FEATURE_INTTSEN_Msk \ - (0x2000000UL) /*!< ETH HW_FEATURE: INTTSEN (Bitfield-Mask: 0x01) */ -#define ETH_HW_FEATURE_FLEXIPPSEN_Pos \ - (26UL) /*!< ETH HW_FEATURE: FLEXIPPSEN (Bit 26) */ -#define ETH_HW_FEATURE_FLEXIPPSEN_Msk \ - (0x4000000UL) /*!< ETH HW_FEATURE: FLEXIPPSEN (Bitfield-Mask: 0x01) */ -#define ETH_HW_FEATURE_SAVLANINS_Pos \ - (27UL) /*!< ETH HW_FEATURE: SAVLANINS (Bit 27) */ -#define ETH_HW_FEATURE_SAVLANINS_Msk \ - (0x8000000UL) /*!< ETH HW_FEATURE: SAVLANINS (Bitfield-Mask: 0x01) */ -#define ETH_HW_FEATURE_ACTPHYIF_Pos \ - (28UL) /*!< ETH HW_FEATURE: ACTPHYIF (Bit 28) */ -#define ETH_HW_FEATURE_ACTPHYIF_Msk \ - (0x70000000UL) /*!< ETH HW_FEATURE: ACTPHYIF (Bitfield-Mask: 0x07) */ - -/* ================================================================================ */ -/* ================ Group 'USB' Position & Mask ================ */ -/* ================================================================================ */ - -/* --------------------------------- USB_GOTGCTL -------------------------------- */ -#define USB_GOTGCTL_SesReqScs_Pos \ - (0UL) /*!< USB GOTGCTL: SesReqScs (Bit 0) */ -#define USB_GOTGCTL_SesReqScs_Msk \ - (0x1UL) /*!< USB GOTGCTL: SesReqScs (Bitfield-Mask: 0x01) */ -#define USB_GOTGCTL_SesReq_Pos \ - (1UL) /*!< USB GOTGCTL: SesReq (Bit 1) */ -#define USB_GOTGCTL_SesReq_Msk \ - (0x2UL) /*!< USB GOTGCTL: SesReq (Bitfield-Mask: 0x01) */ -#define USB_GOTGCTL_VbvalidOvEn_Pos \ - (2UL) /*!< USB GOTGCTL: VbvalidOvEn (Bit 2) */ -#define USB_GOTGCTL_VbvalidOvEn_Msk \ - (0x4UL) /*!< USB GOTGCTL: VbvalidOvEn (Bitfield-Mask: 0x01) */ -#define USB_GOTGCTL_VbvalidOvVal_Pos \ - (3UL) /*!< USB GOTGCTL: VbvalidOvVal (Bit 3) */ -#define USB_GOTGCTL_VbvalidOvVal_Msk \ - (0x8UL) /*!< USB GOTGCTL: VbvalidOvVal (Bitfield-Mask: 0x01) */ -#define USB_GOTGCTL_AvalidOvEn_Pos \ - (4UL) /*!< USB GOTGCTL: AvalidOvEn (Bit 4) */ -#define USB_GOTGCTL_AvalidOvEn_Msk \ - (0x10UL) /*!< USB GOTGCTL: AvalidOvEn (Bitfield-Mask: 0x01) */ -#define USB_GOTGCTL_AvalidOvVal_Pos \ - (5UL) /*!< USB GOTGCTL: AvalidOvVal (Bit 5) */ -#define USB_GOTGCTL_AvalidOvVal_Msk \ - (0x20UL) /*!< USB GOTGCTL: AvalidOvVal (Bitfield-Mask: 0x01) */ -#define USB_GOTGCTL_BvalidOvEn_Pos \ - (6UL) /*!< USB GOTGCTL: BvalidOvEn (Bit 6) */ -#define USB_GOTGCTL_BvalidOvEn_Msk \ - (0x40UL) /*!< USB GOTGCTL: BvalidOvEn (Bitfield-Mask: 0x01) */ -#define USB_GOTGCTL_BvalidOvVal_Pos \ - (7UL) /*!< USB GOTGCTL: BvalidOvVal (Bit 7) */ -#define USB_GOTGCTL_BvalidOvVal_Msk \ - (0x80UL) /*!< USB GOTGCTL: BvalidOvVal (Bitfield-Mask: 0x01) */ -#define USB_GOTGCTL_HstNegScs_Pos \ - (8UL) /*!< USB GOTGCTL: HstNegScs (Bit 8) */ -#define USB_GOTGCTL_HstNegScs_Msk \ - (0x100UL) /*!< USB GOTGCTL: HstNegScs (Bitfield-Mask: 0x01) */ -#define USB_GOTGCTL_HNPReq_Pos \ - (9UL) /*!< USB GOTGCTL: HNPReq (Bit 9) */ -#define USB_GOTGCTL_HNPReq_Msk \ - (0x200UL) /*!< USB GOTGCTL: HNPReq (Bitfield-Mask: 0x01) */ -#define USB_GOTGCTL_HstSetHNPEn_Pos \ - (10UL) /*!< USB GOTGCTL: HstSetHNPEn (Bit 10) */ -#define USB_GOTGCTL_HstSetHNPEn_Msk \ - (0x400UL) /*!< USB GOTGCTL: HstSetHNPEn (Bitfield-Mask: 0x01) */ -#define USB_GOTGCTL_DevHNPEn_Pos \ - (11UL) /*!< USB GOTGCTL: DevHNPEn (Bit 11) */ -#define USB_GOTGCTL_DevHNPEn_Msk \ - (0x800UL) /*!< USB GOTGCTL: DevHNPEn (Bitfield-Mask: 0x01) */ -#define USB_GOTGCTL_ConlDSts_Pos \ - (16UL) /*!< USB GOTGCTL: ConlDSts (Bit 16) */ -#define USB_GOTGCTL_ConlDSts_Msk \ - (0x10000UL) /*!< USB GOTGCTL: ConlDSts (Bitfield-Mask: 0x01) */ -#define USB_GOTGCTL_DbncTime_Pos \ - (17UL) /*!< USB GOTGCTL: DbncTime (Bit 17) */ -#define USB_GOTGCTL_DbncTime_Msk \ - (0x20000UL) /*!< USB GOTGCTL: DbncTime (Bitfield-Mask: 0x01) */ -#define USB_GOTGCTL_ASesVId_Pos \ - (18UL) /*!< USB GOTGCTL: ASesVId (Bit 18) */ -#define USB_GOTGCTL_ASesVId_Msk \ - (0x40000UL) /*!< USB GOTGCTL: ASesVId (Bitfield-Mask: 0x01) */ -#define USB_GOTGCTL_BSesVld_Pos \ - (19UL) /*!< USB GOTGCTL: BSesVld (Bit 19) */ -#define USB_GOTGCTL_BSesVld_Msk \ - (0x80000UL) /*!< USB GOTGCTL: BSesVld (Bitfield-Mask: 0x01) */ -#define USB_GOTGCTL_OTGVer_Pos \ - (20UL) /*!< USB GOTGCTL: OTGVer (Bit 20) */ -#define USB_GOTGCTL_OTGVer_Msk \ - (0x100000UL) /*!< USB GOTGCTL: OTGVer (Bitfield-Mask: 0x01) */ - -/* --------------------------------- USB_GOTGINT -------------------------------- */ -#define USB_GOTGINT_SesEndDet_Pos \ - (2UL) /*!< USB GOTGINT: SesEndDet (Bit 2) */ -#define USB_GOTGINT_SesEndDet_Msk \ - (0x4UL) /*!< USB GOTGINT: SesEndDet (Bitfield-Mask: 0x01) */ -#define USB_GOTGINT_SesReqSucStsChng_Pos \ - (8UL) /*!< USB GOTGINT: SesReqSucStsChng (Bit 8) */ -#define USB_GOTGINT_SesReqSucStsChng_Msk \ - (0x100UL) /*!< USB GOTGINT: SesReqSucStsChng (Bitfield-Mask: 0x01) */ -#define USB_GOTGINT_HstNegSucStsChng_Pos \ - (9UL) /*!< USB GOTGINT: HstNegSucStsChng (Bit 9) */ -#define USB_GOTGINT_HstNegSucStsChng_Msk \ - (0x200UL) /*!< USB GOTGINT: HstNegSucStsChng (Bitfield-Mask: 0x01) */ -#define USB_GOTGINT_HstNegDet_Pos \ - (17UL) /*!< USB GOTGINT: HstNegDet (Bit 17) */ -#define USB_GOTGINT_HstNegDet_Msk \ - (0x20000UL) /*!< USB GOTGINT: HstNegDet (Bitfield-Mask: 0x01) */ -#define USB_GOTGINT_ADevTOUTChg_Pos \ - (18UL) /*!< USB GOTGINT: ADevTOUTChg (Bit 18) */ -#define USB_GOTGINT_ADevTOUTChg_Msk \ - (0x40000UL) /*!< USB GOTGINT: ADevTOUTChg (Bitfield-Mask: 0x01) */ -#define USB_GOTGINT_DbnceDone_Pos \ - (19UL) /*!< USB GOTGINT: DbnceDone (Bit 19) */ -#define USB_GOTGINT_DbnceDone_Msk \ - (0x80000UL) /*!< USB GOTGINT: DbnceDone (Bitfield-Mask: 0x01) */ - -/* --------------------------------- USB_GAHBCFG -------------------------------- */ -#define USB_GAHBCFG_GlblIntrMsk_Pos \ - (0UL) /*!< USB GAHBCFG: GlblIntrMsk (Bit 0) */ -#define USB_GAHBCFG_GlblIntrMsk_Msk \ - (0x1UL) /*!< USB GAHBCFG: GlblIntrMsk (Bitfield-Mask: 0x01) */ -#define USB_GAHBCFG_HBstLen_Pos \ - (1UL) /*!< USB GAHBCFG: HBstLen (Bit 1) */ -#define USB_GAHBCFG_HBstLen_Msk \ - (0x1eUL) /*!< USB GAHBCFG: HBstLen (Bitfield-Mask: 0x0f) */ -#define USB_GAHBCFG_DMAEn_Pos \ - (5UL) /*!< USB GAHBCFG: DMAEn (Bit 5) */ -#define USB_GAHBCFG_DMAEn_Msk \ - (0x20UL) /*!< USB GAHBCFG: DMAEn (Bitfield-Mask: 0x01) */ -#define USB_GAHBCFG_NPTxFEmpLvl_Pos \ - (7UL) /*!< USB GAHBCFG: NPTxFEmpLvl (Bit 7) */ -#define USB_GAHBCFG_NPTxFEmpLvl_Msk \ - (0x80UL) /*!< USB GAHBCFG: NPTxFEmpLvl (Bitfield-Mask: 0x01) */ -#define USB_GAHBCFG_PTxFEmpLvl_Pos \ - (8UL) /*!< USB GAHBCFG: PTxFEmpLvl (Bit 8) */ -#define USB_GAHBCFG_PTxFEmpLvl_Msk \ - (0x100UL) /*!< USB GAHBCFG: PTxFEmpLvl (Bitfield-Mask: 0x01) */ -#define USB_GAHBCFG_AHBSingle_Pos \ - (23UL) /*!< USB GAHBCFG: AHBSingle (Bit 23) */ -#define USB_GAHBCFG_AHBSingle_Msk \ - (0x800000UL) /*!< USB GAHBCFG: AHBSingle (Bitfield-Mask: 0x01) */ - -/* --------------------------------- USB_GUSBCFG -------------------------------- */ -#define USB_GUSBCFG_TOutCal_Pos \ - (0UL) /*!< USB GUSBCFG: TOutCal (Bit 0) */ -#define USB_GUSBCFG_TOutCal_Msk \ - (0x7UL) /*!< USB GUSBCFG: TOutCal (Bitfield-Mask: 0x07) */ -#define USB_GUSBCFG_PHYSel_Pos \ - (6UL) /*!< USB GUSBCFG: PHYSel (Bit 6) */ -#define USB_GUSBCFG_PHYSel_Msk \ - (0x40UL) /*!< USB GUSBCFG: PHYSel (Bitfield-Mask: 0x01) */ -#define USB_GUSBCFG_SRPCap_Pos \ - (8UL) /*!< USB GUSBCFG: SRPCap (Bit 8) */ -#define USB_GUSBCFG_SRPCap_Msk \ - (0x100UL) /*!< USB GUSBCFG: SRPCap (Bitfield-Mask: 0x01) */ -#define USB_GUSBCFG_HNPCap_Pos \ - (9UL) /*!< USB GUSBCFG: HNPCap (Bit 9) */ -#define USB_GUSBCFG_HNPCap_Msk \ - (0x200UL) /*!< USB GUSBCFG: HNPCap (Bitfield-Mask: 0x01) */ -#define USB_GUSBCFG_USBTrdTim_Pos \ - (10UL) /*!< USB GUSBCFG: USBTrdTim (Bit 10) */ -#define USB_GUSBCFG_USBTrdTim_Msk \ - (0x3c00UL) /*!< USB GUSBCFG: USBTrdTim (Bitfield-Mask: 0x0f) */ -#define USB_GUSBCFG_OtgI2CSel_Pos \ - (16UL) /*!< USB GUSBCFG: OtgI2CSel (Bit 16) */ -#define USB_GUSBCFG_OtgI2CSel_Msk \ - (0x10000UL) /*!< USB GUSBCFG: OtgI2CSel (Bitfield-Mask: 0x01) */ -#define USB_GUSBCFG_TxEndDelay_Pos \ - (28UL) /*!< USB GUSBCFG: TxEndDelay (Bit 28) */ -#define USB_GUSBCFG_TxEndDelay_Msk \ - (0x10000000UL) /*!< USB GUSBCFG: TxEndDelay (Bitfield-Mask: 0x01) */ -#define USB_GUSBCFG_ForceHstMode_Pos \ - (29UL) /*!< USB GUSBCFG: ForceHstMode (Bit 29) */ -#define USB_GUSBCFG_ForceHstMode_Msk \ - (0x20000000UL) /*!< USB GUSBCFG: ForceHstMode (Bitfield-Mask: 0x01) */ -#define USB_GUSBCFG_ForceDevMode_Pos \ - (30UL) /*!< USB GUSBCFG: ForceDevMode (Bit 30) */ -#define USB_GUSBCFG_ForceDevMode_Msk \ - (0x40000000UL) /*!< USB GUSBCFG: ForceDevMode (Bitfield-Mask: 0x01) */ -#define USB_GUSBCFG_CTP_Pos \ - (31UL) /*!< USB GUSBCFG: CTP (Bit 31) */ -#define USB_GUSBCFG_CTP_Msk \ - (0x80000000UL) /*!< USB GUSBCFG: CTP (Bitfield-Mask: 0x01) */ - -/* --------------------------------- USB_GRSTCTL -------------------------------- */ -#define USB_GRSTCTL_CSftRst_Pos \ - (0UL) /*!< USB GRSTCTL: CSftRst (Bit 0) */ -#define USB_GRSTCTL_CSftRst_Msk \ - (0x1UL) /*!< USB GRSTCTL: CSftRst (Bitfield-Mask: 0x01) */ -#define USB_GRSTCTL_FrmCntrRst_Pos \ - (2UL) /*!< USB GRSTCTL: FrmCntrRst (Bit 2) */ -#define USB_GRSTCTL_FrmCntrRst_Msk \ - (0x4UL) /*!< USB GRSTCTL: FrmCntrRst (Bitfield-Mask: 0x01) */ -#define USB_GRSTCTL_RxFFlsh_Pos \ - (4UL) /*!< USB GRSTCTL: RxFFlsh (Bit 4) */ -#define USB_GRSTCTL_RxFFlsh_Msk \ - (0x10UL) /*!< USB GRSTCTL: RxFFlsh (Bitfield-Mask: 0x01) */ -#define USB_GRSTCTL_TxFFlsh_Pos \ - (5UL) /*!< USB GRSTCTL: TxFFlsh (Bit 5) */ -#define USB_GRSTCTL_TxFFlsh_Msk \ - (0x20UL) /*!< USB GRSTCTL: TxFFlsh (Bitfield-Mask: 0x01) */ -#define USB_GRSTCTL_TxFNum_Pos \ - (6UL) /*!< USB GRSTCTL: TxFNum (Bit 6) */ -#define USB_GRSTCTL_TxFNum_Msk \ - (0x7c0UL) /*!< USB GRSTCTL: TxFNum (Bitfield-Mask: 0x1f) */ -#define USB_GRSTCTL_DMAReq_Pos \ - (30UL) /*!< USB GRSTCTL: DMAReq (Bit 30) */ -#define USB_GRSTCTL_DMAReq_Msk \ - (0x40000000UL) /*!< USB GRSTCTL: DMAReq (Bitfield-Mask: 0x01) */ -#define USB_GRSTCTL_AHBIdle_Pos \ - (31UL) /*!< USB GRSTCTL: AHBIdle (Bit 31) */ -#define USB_GRSTCTL_AHBIdle_Msk \ - (0x80000000UL) /*!< USB GRSTCTL: AHBIdle (Bitfield-Mask: 0x01) */ - -/* ---------------------------- USB_GINTSTS_HOSTMODE ---------------------------- */ -#define USB_GINTSTS_HOSTMODE_CurMod_Pos \ - (0UL) /*!< USB GINTSTS_HOSTMODE: CurMod (Bit 0) */ -#define USB_GINTSTS_HOSTMODE_CurMod_Msk \ - (0x1UL) /*!< USB GINTSTS_HOSTMODE: CurMod (Bitfield-Mask: 0x01) */ -#define USB_GINTSTS_HOSTMODE_ModeMis_Pos \ - (1UL) /*!< USB GINTSTS_HOSTMODE: ModeMis (Bit 1) */ -#define USB_GINTSTS_HOSTMODE_ModeMis_Msk \ - (0x2UL) /*!< USB GINTSTS_HOSTMODE: ModeMis (Bitfield-Mask: 0x01) */ -#define USB_GINTSTS_HOSTMODE_OTGInt_Pos \ - (2UL) /*!< USB GINTSTS_HOSTMODE: OTGInt (Bit 2) */ -#define USB_GINTSTS_HOSTMODE_OTGInt_Msk \ - (0x4UL) /*!< USB GINTSTS_HOSTMODE: OTGInt (Bitfield-Mask: 0x01) */ -#define USB_GINTSTS_HOSTMODE_Sof_Pos \ - (3UL) /*!< USB GINTSTS_HOSTMODE: Sof (Bit 3) */ -#define USB_GINTSTS_HOSTMODE_Sof_Msk \ - (0x8UL) /*!< USB GINTSTS_HOSTMODE: Sof (Bitfield-Mask: 0x01) */ -#define USB_GINTSTS_HOSTMODE_RxFLvl_Pos \ - (4UL) /*!< USB GINTSTS_HOSTMODE: RxFLvl (Bit 4) */ -#define USB_GINTSTS_HOSTMODE_RxFLvl_Msk \ - (0x10UL) /*!< USB GINTSTS_HOSTMODE: RxFLvl (Bitfield-Mask: 0x01) */ -#define USB_GINTSTS_HOSTMODE_incomplP_Pos \ - (21UL) /*!< USB GINTSTS_HOSTMODE: incomplP (Bit 21) */ -#define USB_GINTSTS_HOSTMODE_incomplP_Msk \ - (0x200000UL) /*!< USB GINTSTS_HOSTMODE: incomplP (Bitfield-Mask: 0x01) */ -#define USB_GINTSTS_HOSTMODE_PrtInt_Pos \ - (24UL) /*!< USB GINTSTS_HOSTMODE: PrtInt (Bit 24) */ -#define USB_GINTSTS_HOSTMODE_PrtInt_Msk \ - (0x1000000UL) /*!< USB GINTSTS_HOSTMODE: PrtInt (Bitfield-Mask: 0x01) */ -#define USB_GINTSTS_HOSTMODE_HChInt_Pos \ - (25UL) /*!< USB GINTSTS_HOSTMODE: HChInt (Bit 25) */ -#define USB_GINTSTS_HOSTMODE_HChInt_Msk \ - (0x2000000UL) /*!< USB GINTSTS_HOSTMODE: HChInt (Bitfield-Mask: 0x01) */ -#define USB_GINTSTS_HOSTMODE_PTxFEmp_Pos \ - (26UL) /*!< USB GINTSTS_HOSTMODE: PTxFEmp (Bit 26) */ -#define USB_GINTSTS_HOSTMODE_PTxFEmp_Msk \ - (0x4000000UL) /*!< USB GINTSTS_HOSTMODE: PTxFEmp (Bitfield-Mask: 0x01) */ -#define USB_GINTSTS_HOSTMODE_ConIDStsChng_Pos \ - (28UL) /*!< USB GINTSTS_HOSTMODE: ConIDStsChng (Bit 28) */ -#define USB_GINTSTS_HOSTMODE_ConIDStsChng_Msk \ - (0x10000000UL) /*!< USB GINTSTS_HOSTMODE: ConIDStsChng (Bitfield-Mask: 0x01) */ -#define USB_GINTSTS_HOSTMODE_DisconnInt_Pos \ - (29UL) /*!< USB GINTSTS_HOSTMODE: DisconnInt (Bit 29) */ -#define USB_GINTSTS_HOSTMODE_DisconnInt_Msk \ - (0x20000000UL) /*!< USB GINTSTS_HOSTMODE: DisconnInt (Bitfield-Mask: 0x01) */ -#define USB_GINTSTS_HOSTMODE_SessReqInt_Pos \ - (30UL) /*!< USB GINTSTS_HOSTMODE: SessReqInt (Bit 30) */ -#define USB_GINTSTS_HOSTMODE_SessReqInt_Msk \ - (0x40000000UL) /*!< USB GINTSTS_HOSTMODE: SessReqInt (Bitfield-Mask: 0x01) */ -#define USB_GINTSTS_HOSTMODE_WkUpInt_Pos \ - (31UL) /*!< USB GINTSTS_HOSTMODE: WkUpInt (Bit 31) */ -#define USB_GINTSTS_HOSTMODE_WkUpInt_Msk \ - (0x80000000UL) /*!< USB GINTSTS_HOSTMODE: WkUpInt (Bitfield-Mask: 0x01) */ - -/* --------------------------- USB_GINTSTS_DEVICEMODE --------------------------- */ -#define USB_GINTSTS_DEVICEMODE_CurMod_Pos \ - (0UL) /*!< USB GINTSTS_DEVICEMODE: CurMod (Bit 0) */ -#define USB_GINTSTS_DEVICEMODE_CurMod_Msk \ - (0x1UL) /*!< USB GINTSTS_DEVICEMODE: CurMod (Bitfield-Mask: 0x01) */ -#define USB_GINTSTS_DEVICEMODE_ModeMis_Pos \ - (1UL) /*!< USB GINTSTS_DEVICEMODE: ModeMis (Bit 1) */ -#define USB_GINTSTS_DEVICEMODE_ModeMis_Msk \ - (0x2UL) /*!< USB GINTSTS_DEVICEMODE: ModeMis (Bitfield-Mask: 0x01) */ -#define USB_GINTSTS_DEVICEMODE_OTGInt_Pos \ - (2UL) /*!< USB GINTSTS_DEVICEMODE: OTGInt (Bit 2) */ -#define USB_GINTSTS_DEVICEMODE_OTGInt_Msk \ - (0x4UL) /*!< USB GINTSTS_DEVICEMODE: OTGInt (Bitfield-Mask: 0x01) */ -#define USB_GINTSTS_DEVICEMODE_Sof_Pos \ - (3UL) /*!< USB GINTSTS_DEVICEMODE: Sof (Bit 3) */ -#define USB_GINTSTS_DEVICEMODE_Sof_Msk \ - (0x8UL) /*!< USB GINTSTS_DEVICEMODE: Sof (Bitfield-Mask: 0x01) */ -#define USB_GINTSTS_DEVICEMODE_RxFLvl_Pos \ - (4UL) /*!< USB GINTSTS_DEVICEMODE: RxFLvl (Bit 4) */ -#define USB_GINTSTS_DEVICEMODE_RxFLvl_Msk \ - (0x10UL) /*!< USB GINTSTS_DEVICEMODE: RxFLvl (Bitfield-Mask: 0x01) */ -#define USB_GINTSTS_DEVICEMODE_GINNakEff_Pos \ - (6UL) /*!< USB GINTSTS_DEVICEMODE: GINNakEff (Bit 6) */ -#define USB_GINTSTS_DEVICEMODE_GINNakEff_Msk \ - (0x40UL) /*!< USB GINTSTS_DEVICEMODE: GINNakEff (Bitfield-Mask: 0x01) */ -#define USB_GINTSTS_DEVICEMODE_GOUTNakEff_Pos \ - (7UL) /*!< USB GINTSTS_DEVICEMODE: GOUTNakEff (Bit 7) */ -#define USB_GINTSTS_DEVICEMODE_GOUTNakEff_Msk \ - (0x80UL) /*!< USB GINTSTS_DEVICEMODE: GOUTNakEff (Bitfield-Mask: 0x01) */ -#define USB_GINTSTS_DEVICEMODE_ErlySusp_Pos \ - (10UL) /*!< USB GINTSTS_DEVICEMODE: ErlySusp (Bit 10) */ -#define USB_GINTSTS_DEVICEMODE_ErlySusp_Msk \ - (0x400UL) /*!< USB GINTSTS_DEVICEMODE: ErlySusp (Bitfield-Mask: 0x01) */ -#define USB_GINTSTS_DEVICEMODE_USBSusp_Pos \ - (11UL) /*!< USB GINTSTS_DEVICEMODE: USBSusp (Bit 11) */ -#define USB_GINTSTS_DEVICEMODE_USBSusp_Msk \ - (0x800UL) /*!< USB GINTSTS_DEVICEMODE: USBSusp (Bitfield-Mask: 0x01) */ -#define USB_GINTSTS_DEVICEMODE_USBRst_Pos \ - (12UL) /*!< USB GINTSTS_DEVICEMODE: USBRst (Bit 12) */ -#define USB_GINTSTS_DEVICEMODE_USBRst_Msk \ - (0x1000UL) /*!< USB GINTSTS_DEVICEMODE: USBRst (Bitfield-Mask: 0x01) */ -#define USB_GINTSTS_DEVICEMODE_EnumDone_Pos \ - (13UL) /*!< USB GINTSTS_DEVICEMODE: EnumDone (Bit 13) */ -#define USB_GINTSTS_DEVICEMODE_EnumDone_Msk \ - (0x2000UL) /*!< USB GINTSTS_DEVICEMODE: EnumDone (Bitfield-Mask: 0x01) */ -#define USB_GINTSTS_DEVICEMODE_ISOOutDrop_Pos \ - (14UL) /*!< USB GINTSTS_DEVICEMODE: ISOOutDrop (Bit 14) */ -#define USB_GINTSTS_DEVICEMODE_ISOOutDrop_Msk \ - (0x4000UL) /*!< USB GINTSTS_DEVICEMODE: ISOOutDrop (Bitfield-Mask: 0x01) */ -#define USB_GINTSTS_DEVICEMODE_EOPF_Pos \ - (15UL) /*!< USB GINTSTS_DEVICEMODE: EOPF (Bit 15) */ -#define USB_GINTSTS_DEVICEMODE_EOPF_Msk \ - (0x8000UL) /*!< USB GINTSTS_DEVICEMODE: EOPF (Bitfield-Mask: 0x01) */ -#define USB_GINTSTS_DEVICEMODE_IEPInt_Pos \ - (18UL) /*!< USB GINTSTS_DEVICEMODE: IEPInt (Bit 18) */ -#define USB_GINTSTS_DEVICEMODE_IEPInt_Msk \ - (0x40000UL) /*!< USB GINTSTS_DEVICEMODE: IEPInt (Bitfield-Mask: 0x01) */ -#define USB_GINTSTS_DEVICEMODE_OEPInt_Pos \ - (19UL) /*!< USB GINTSTS_DEVICEMODE: OEPInt (Bit 19) */ -#define USB_GINTSTS_DEVICEMODE_OEPInt_Msk \ - (0x80000UL) /*!< USB GINTSTS_DEVICEMODE: OEPInt (Bitfield-Mask: 0x01) */ -#define USB_GINTSTS_DEVICEMODE_incompISOIN_Pos \ - (20UL) /*!< USB GINTSTS_DEVICEMODE: incompISOIN (Bit 20) */ -#define USB_GINTSTS_DEVICEMODE_incompISOIN_Msk \ - (0x100000UL) /*!< USB GINTSTS_DEVICEMODE: incompISOIN (Bitfield-Mask: 0x01) */ -#define USB_GINTSTS_DEVICEMODE_incomplSOOUT_Pos \ - (21UL) /*!< USB GINTSTS_DEVICEMODE: incomplSOOUT (Bit 21) */ -#define USB_GINTSTS_DEVICEMODE_incomplSOOUT_Msk \ - (0x200000UL) /*!< USB GINTSTS_DEVICEMODE: incomplSOOUT (Bitfield-Mask: 0x01) */ -#define USB_GINTSTS_DEVICEMODE_ConIDStsChng_Pos \ - (28UL) /*!< USB GINTSTS_DEVICEMODE: ConIDStsChng (Bit 28) */ -#define USB_GINTSTS_DEVICEMODE_ConIDStsChng_Msk \ - (0x10000000UL) /*!< USB GINTSTS_DEVICEMODE: ConIDStsChng (Bitfield-Mask: 0x01) */ -#define USB_GINTSTS_DEVICEMODE_SessReqInt_Pos \ - (30UL) /*!< USB GINTSTS_DEVICEMODE: SessReqInt (Bit 30) */ -#define USB_GINTSTS_DEVICEMODE_SessReqInt_Msk \ - (0x40000000UL) /*!< USB GINTSTS_DEVICEMODE: SessReqInt (Bitfield-Mask: 0x01) */ -#define USB_GINTSTS_DEVICEMODE_WkUpInt_Pos \ - (31UL) /*!< USB GINTSTS_DEVICEMODE: WkUpInt (Bit 31) */ -#define USB_GINTSTS_DEVICEMODE_WkUpInt_Msk \ - (0x80000000UL) /*!< USB GINTSTS_DEVICEMODE: WkUpInt (Bitfield-Mask: 0x01) */ - -/* ---------------------------- USB_GINTMSK_HOSTMODE ---------------------------- */ -#define USB_GINTMSK_HOSTMODE_ModeMisMsk_Pos \ - (1UL) /*!< USB GINTMSK_HOSTMODE: ModeMisMsk (Bit 1) */ -#define USB_GINTMSK_HOSTMODE_ModeMisMsk_Msk \ - (0x2UL) /*!< USB GINTMSK_HOSTMODE: ModeMisMsk (Bitfield-Mask: 0x01) */ -#define USB_GINTMSK_HOSTMODE_OTGIntMsk_Pos \ - (2UL) /*!< USB GINTMSK_HOSTMODE: OTGIntMsk (Bit 2) */ -#define USB_GINTMSK_HOSTMODE_OTGIntMsk_Msk \ - (0x4UL) /*!< USB GINTMSK_HOSTMODE: OTGIntMsk (Bitfield-Mask: 0x01) */ -#define USB_GINTMSK_HOSTMODE_SofMsk_Pos \ - (3UL) /*!< USB GINTMSK_HOSTMODE: SofMsk (Bit 3) */ -#define USB_GINTMSK_HOSTMODE_SofMsk_Msk \ - (0x8UL) /*!< USB GINTMSK_HOSTMODE: SofMsk (Bitfield-Mask: 0x01) */ -#define USB_GINTMSK_HOSTMODE_RxFLvlMsk_Pos \ - (4UL) /*!< USB GINTMSK_HOSTMODE: RxFLvlMsk (Bit 4) */ -#define USB_GINTMSK_HOSTMODE_RxFLvlMsk_Msk \ - (0x10UL) /*!< USB GINTMSK_HOSTMODE: RxFLvlMsk (Bitfield-Mask: 0x01) */ -#define USB_GINTMSK_HOSTMODE_incomplPMsk_Pos \ - (21UL) /*!< USB GINTMSK_HOSTMODE: incomplPMsk (Bit 21) */ -#define USB_GINTMSK_HOSTMODE_incomplPMsk_Msk \ - (0x200000UL) /*!< USB GINTMSK_HOSTMODE: incomplPMsk (Bitfield-Mask: 0x01) */ -#define USB_GINTMSK_HOSTMODE_PrtIntMsk_Pos \ - (24UL) /*!< USB GINTMSK_HOSTMODE: PrtIntMsk (Bit 24) */ -#define USB_GINTMSK_HOSTMODE_PrtIntMsk_Msk \ - (0x1000000UL) /*!< USB GINTMSK_HOSTMODE: PrtIntMsk (Bitfield-Mask: 0x01) */ -#define USB_GINTMSK_HOSTMODE_HChIntMsk_Pos \ - (25UL) /*!< USB GINTMSK_HOSTMODE: HChIntMsk (Bit 25) */ -#define USB_GINTMSK_HOSTMODE_HChIntMsk_Msk \ - (0x2000000UL) /*!< USB GINTMSK_HOSTMODE: HChIntMsk (Bitfield-Mask: 0x01) */ -#define USB_GINTMSK_HOSTMODE_PTxFEmpMsk_Pos \ - (26UL) /*!< USB GINTMSK_HOSTMODE: PTxFEmpMsk (Bit 26) */ -#define USB_GINTMSK_HOSTMODE_PTxFEmpMsk_Msk \ - (0x4000000UL) /*!< USB GINTMSK_HOSTMODE: PTxFEmpMsk (Bitfield-Mask: 0x01) */ -#define USB_GINTMSK_HOSTMODE_ConIDStsChngMsk_Pos \ - (28UL) /*!< USB GINTMSK_HOSTMODE: ConIDStsChngMsk (Bit 28) */ -#define USB_GINTMSK_HOSTMODE_ConIDStsChngMsk_Msk \ - (0x10000000UL) /*!< USB GINTMSK_HOSTMODE: ConIDStsChngMsk (Bitfield-Mask: 0x01) */ -#define USB_GINTMSK_HOSTMODE_DisconnIntMsk_Pos \ - (29UL) /*!< USB GINTMSK_HOSTMODE: DisconnIntMsk (Bit 29) */ -#define USB_GINTMSK_HOSTMODE_DisconnIntMsk_Msk \ - (0x20000000UL) /*!< USB GINTMSK_HOSTMODE: DisconnIntMsk (Bitfield-Mask: 0x01) */ -#define USB_GINTMSK_HOSTMODE_SessReqIntMsk_Pos \ - (30UL) /*!< USB GINTMSK_HOSTMODE: SessReqIntMsk (Bit 30) */ -#define USB_GINTMSK_HOSTMODE_SessReqIntMsk_Msk \ - (0x40000000UL) /*!< USB GINTMSK_HOSTMODE: SessReqIntMsk (Bitfield-Mask: 0x01) */ -#define USB_GINTMSK_HOSTMODE_WkUpIntMsk_Pos \ - (31UL) /*!< USB GINTMSK_HOSTMODE: WkUpIntMsk (Bit 31) */ -#define USB_GINTMSK_HOSTMODE_WkUpIntMsk_Msk \ - (0x80000000UL) /*!< USB GINTMSK_HOSTMODE: WkUpIntMsk (Bitfield-Mask: 0x01) */ - -/* --------------------------- USB_GINTMSK_DEVICEMODE --------------------------- */ -#define USB_GINTMSK_DEVICEMODE_ModeMisMsk_Pos \ - (1UL) /*!< USB GINTMSK_DEVICEMODE: ModeMisMsk (Bit 1) */ -#define USB_GINTMSK_DEVICEMODE_ModeMisMsk_Msk \ - (0x2UL) /*!< USB GINTMSK_DEVICEMODE: ModeMisMsk (Bitfield-Mask: 0x01) */ -#define USB_GINTMSK_DEVICEMODE_OTGIntMsk_Pos \ - (2UL) /*!< USB GINTMSK_DEVICEMODE: OTGIntMsk (Bit 2) */ -#define USB_GINTMSK_DEVICEMODE_OTGIntMsk_Msk \ - (0x4UL) /*!< USB GINTMSK_DEVICEMODE: OTGIntMsk (Bitfield-Mask: 0x01) */ -#define USB_GINTMSK_DEVICEMODE_SofMsk_Pos \ - (3UL) /*!< USB GINTMSK_DEVICEMODE: SofMsk (Bit 3) */ -#define USB_GINTMSK_DEVICEMODE_SofMsk_Msk \ - (0x8UL) /*!< USB GINTMSK_DEVICEMODE: SofMsk (Bitfield-Mask: 0x01) */ -#define USB_GINTMSK_DEVICEMODE_RxFLvlMsk_Pos \ - (4UL) /*!< USB GINTMSK_DEVICEMODE: RxFLvlMsk (Bit 4) */ -#define USB_GINTMSK_DEVICEMODE_RxFLvlMsk_Msk \ - (0x10UL) /*!< USB GINTMSK_DEVICEMODE: RxFLvlMsk (Bitfield-Mask: 0x01) */ -#define USB_GINTMSK_DEVICEMODE_GINNakEffMsk_Pos \ - (6UL) /*!< USB GINTMSK_DEVICEMODE: GINNakEffMsk (Bit 6) */ -#define USB_GINTMSK_DEVICEMODE_GINNakEffMsk_Msk \ - (0x40UL) /*!< USB GINTMSK_DEVICEMODE: GINNakEffMsk (Bitfield-Mask: 0x01) */ -#define USB_GINTMSK_DEVICEMODE_GOUTNakEffMsk_Pos \ - (7UL) /*!< USB GINTMSK_DEVICEMODE: GOUTNakEffMsk (Bit 7) */ -#define USB_GINTMSK_DEVICEMODE_GOUTNakEffMsk_Msk \ - (0x80UL) /*!< USB GINTMSK_DEVICEMODE: GOUTNakEffMsk (Bitfield-Mask: 0x01) */ -#define USB_GINTMSK_DEVICEMODE_ErlySuspMsk_Pos \ - (10UL) /*!< USB GINTMSK_DEVICEMODE: ErlySuspMsk (Bit 10) */ -#define USB_GINTMSK_DEVICEMODE_ErlySuspMsk_Msk \ - (0x400UL) /*!< USB GINTMSK_DEVICEMODE: ErlySuspMsk (Bitfield-Mask: 0x01) */ -#define USB_GINTMSK_DEVICEMODE_USBSuspMsk_Pos \ - (11UL) /*!< USB GINTMSK_DEVICEMODE: USBSuspMsk (Bit 11) */ -#define USB_GINTMSK_DEVICEMODE_USBSuspMsk_Msk \ - (0x800UL) /*!< USB GINTMSK_DEVICEMODE: USBSuspMsk (Bitfield-Mask: 0x01) */ -#define USB_GINTMSK_DEVICEMODE_USBRstMsk_Pos \ - (12UL) /*!< USB GINTMSK_DEVICEMODE: USBRstMsk (Bit 12) */ -#define USB_GINTMSK_DEVICEMODE_USBRstMsk_Msk \ - (0x1000UL) /*!< USB GINTMSK_DEVICEMODE: USBRstMsk (Bitfield-Mask: 0x01) */ -#define USB_GINTMSK_DEVICEMODE_EnumDoneMsk_Pos \ - (13UL) /*!< USB GINTMSK_DEVICEMODE: EnumDoneMsk (Bit 13) */ -#define USB_GINTMSK_DEVICEMODE_EnumDoneMsk_Msk \ - (0x2000UL) /*!< USB GINTMSK_DEVICEMODE: EnumDoneMsk (Bitfield-Mask: 0x01) */ -#define USB_GINTMSK_DEVICEMODE_ISOOutDropMsk_Pos \ - (14UL) /*!< USB GINTMSK_DEVICEMODE: ISOOutDropMsk (Bit 14) */ -#define USB_GINTMSK_DEVICEMODE_ISOOutDropMsk_Msk \ - (0x4000UL) /*!< USB GINTMSK_DEVICEMODE: ISOOutDropMsk (Bitfield-Mask: 0x01) */ -#define USB_GINTMSK_DEVICEMODE_EOPFMsk_Pos \ - (15UL) /*!< USB GINTMSK_DEVICEMODE: EOPFMsk (Bit 15) */ -#define USB_GINTMSK_DEVICEMODE_EOPFMsk_Msk \ - (0x8000UL) /*!< USB GINTMSK_DEVICEMODE: EOPFMsk (Bitfield-Mask: 0x01) */ -#define USB_GINTMSK_DEVICEMODE_IEPIntMsk_Pos \ - (18UL) /*!< USB GINTMSK_DEVICEMODE: IEPIntMsk (Bit 18) */ -#define USB_GINTMSK_DEVICEMODE_IEPIntMsk_Msk \ - (0x40000UL) /*!< USB GINTMSK_DEVICEMODE: IEPIntMsk (Bitfield-Mask: 0x01) */ -#define USB_GINTMSK_DEVICEMODE_OEPIntMsk_Pos \ - (19UL) /*!< USB GINTMSK_DEVICEMODE: OEPIntMsk (Bit 19) */ -#define USB_GINTMSK_DEVICEMODE_OEPIntMsk_Msk \ - (0x80000UL) /*!< USB GINTMSK_DEVICEMODE: OEPIntMsk (Bitfield-Mask: 0x01) */ -#define USB_GINTMSK_DEVICEMODE_incompISOINMsk_Pos \ - (20UL) /*!< USB GINTMSK_DEVICEMODE: incompISOINMsk (Bit 20) */ -#define USB_GINTMSK_DEVICEMODE_incompISOINMsk_Msk \ - (0x100000UL) /*!< USB GINTMSK_DEVICEMODE: incompISOINMsk (Bitfield-Mask: 0x01) */ -#define USB_GINTMSK_DEVICEMODE_incomplSOOUTMsk_Pos \ - (21UL) /*!< USB GINTMSK_DEVICEMODE: incomplSOOUTMsk (Bit 21) */ -#define USB_GINTMSK_DEVICEMODE_incomplSOOUTMsk_Msk \ - (0x200000UL) /*!< USB GINTMSK_DEVICEMODE: incomplSOOUTMsk (Bitfield-Mask: 0x01) */ -#define USB_GINTMSK_DEVICEMODE_ConIDStsChngMsk_Pos \ - (28UL) /*!< USB GINTMSK_DEVICEMODE: ConIDStsChngMsk (Bit 28) */ -#define USB_GINTMSK_DEVICEMODE_ConIDStsChngMsk_Msk \ - (0x10000000UL) /*!< USB GINTMSK_DEVICEMODE: ConIDStsChngMsk (Bitfield-Mask: 0x01) */ -#define USB_GINTMSK_DEVICEMODE_DisconnIntMsk_Pos \ - (29UL) /*!< USB GINTMSK_DEVICEMODE: DisconnIntMsk (Bit 29) */ -#define USB_GINTMSK_DEVICEMODE_DisconnIntMsk_Msk \ - (0x20000000UL) /*!< USB GINTMSK_DEVICEMODE: DisconnIntMsk (Bitfield-Mask: 0x01) */ -#define USB_GINTMSK_DEVICEMODE_SessReqIntMsk_Pos \ - (30UL) /*!< USB GINTMSK_DEVICEMODE: SessReqIntMsk (Bit 30) */ -#define USB_GINTMSK_DEVICEMODE_SessReqIntMsk_Msk \ - (0x40000000UL) /*!< USB GINTMSK_DEVICEMODE: SessReqIntMsk (Bitfield-Mask: 0x01) */ -#define USB_GINTMSK_DEVICEMODE_WkUpIntMsk_Pos \ - (31UL) /*!< USB GINTMSK_DEVICEMODE: WkUpIntMsk (Bit 31) */ -#define USB_GINTMSK_DEVICEMODE_WkUpIntMsk_Msk \ - (0x80000000UL) /*!< USB GINTMSK_DEVICEMODE: WkUpIntMsk (Bitfield-Mask: 0x01) */ - -/* ---------------------------- USB_GRXSTSR_HOSTMODE ---------------------------- */ -#define USB_GRXSTSR_HOSTMODE_ChNum_Pos \ - (0UL) /*!< USB GRXSTSR_HOSTMODE: ChNum (Bit 0) */ -#define USB_GRXSTSR_HOSTMODE_ChNum_Msk \ - (0xfUL) /*!< USB GRXSTSR_HOSTMODE: ChNum (Bitfield-Mask: 0x0f) */ -#define USB_GRXSTSR_HOSTMODE_BCnt_Pos \ - (4UL) /*!< USB GRXSTSR_HOSTMODE: BCnt (Bit 4) */ -#define USB_GRXSTSR_HOSTMODE_BCnt_Msk \ - (0x7ff0UL) /*!< USB GRXSTSR_HOSTMODE: BCnt (Bitfield-Mask: 0x7ff) */ -#define USB_GRXSTSR_HOSTMODE_DPID_Pos \ - (15UL) /*!< USB GRXSTSR_HOSTMODE: DPID (Bit 15) */ -#define USB_GRXSTSR_HOSTMODE_DPID_Msk \ - (0x18000UL) /*!< USB GRXSTSR_HOSTMODE: DPID (Bitfield-Mask: 0x03) */ -#define USB_GRXSTSR_HOSTMODE_PktSts_Pos \ - (17UL) /*!< USB GRXSTSR_HOSTMODE: PktSts (Bit 17) */ -#define USB_GRXSTSR_HOSTMODE_PktSts_Msk \ - (0x1e0000UL) /*!< USB GRXSTSR_HOSTMODE: PktSts (Bitfield-Mask: 0x0f) */ - -/* --------------------------- USB_GRXSTSR_DEVICEMODE --------------------------- */ -#define USB_GRXSTSR_DEVICEMODE_EPNum_Pos \ - (0UL) /*!< USB GRXSTSR_DEVICEMODE: EPNum (Bit 0) */ -#define USB_GRXSTSR_DEVICEMODE_EPNum_Msk \ - (0xfUL) /*!< USB GRXSTSR_DEVICEMODE: EPNum (Bitfield-Mask: 0x0f) */ -#define USB_GRXSTSR_DEVICEMODE_BCnt_Pos \ - (4UL) /*!< USB GRXSTSR_DEVICEMODE: BCnt (Bit 4) */ -#define USB_GRXSTSR_DEVICEMODE_BCnt_Msk \ - (0x7ff0UL) /*!< USB GRXSTSR_DEVICEMODE: BCnt (Bitfield-Mask: 0x7ff) */ -#define USB_GRXSTSR_DEVICEMODE_DPID_Pos \ - (15UL) /*!< USB GRXSTSR_DEVICEMODE: DPID (Bit 15) */ -#define USB_GRXSTSR_DEVICEMODE_DPID_Msk \ - (0x18000UL) /*!< USB GRXSTSR_DEVICEMODE: DPID (Bitfield-Mask: 0x03) */ -#define USB_GRXSTSR_DEVICEMODE_PktSts_Pos \ - (17UL) /*!< USB GRXSTSR_DEVICEMODE: PktSts (Bit 17) */ -#define USB_GRXSTSR_DEVICEMODE_PktSts_Msk \ - (0x1e0000UL) /*!< USB GRXSTSR_DEVICEMODE: PktSts (Bitfield-Mask: 0x0f) */ -#define USB_GRXSTSR_DEVICEMODE_FN_Pos \ - (21UL) /*!< USB GRXSTSR_DEVICEMODE: FN (Bit 21) */ -#define USB_GRXSTSR_DEVICEMODE_FN_Msk \ - (0x1e00000UL) /*!< USB GRXSTSR_DEVICEMODE: FN (Bitfield-Mask: 0x0f) */ - -/* --------------------------- USB_GRXSTSP_DEVICEMODE --------------------------- */ -#define USB_GRXSTSP_DEVICEMODE_EPNum_Pos \ - (0UL) /*!< USB GRXSTSP_DEVICEMODE: EPNum (Bit 0) */ -#define USB_GRXSTSP_DEVICEMODE_EPNum_Msk \ - (0xfUL) /*!< USB GRXSTSP_DEVICEMODE: EPNum (Bitfield-Mask: 0x0f) */ -#define USB_GRXSTSP_DEVICEMODE_BCnt_Pos \ - (4UL) /*!< USB GRXSTSP_DEVICEMODE: BCnt (Bit 4) */ -#define USB_GRXSTSP_DEVICEMODE_BCnt_Msk \ - (0x7ff0UL) /*!< USB GRXSTSP_DEVICEMODE: BCnt (Bitfield-Mask: 0x7ff) */ -#define USB_GRXSTSP_DEVICEMODE_DPID_Pos \ - (15UL) /*!< USB GRXSTSP_DEVICEMODE: DPID (Bit 15) */ -#define USB_GRXSTSP_DEVICEMODE_DPID_Msk \ - (0x18000UL) /*!< USB GRXSTSP_DEVICEMODE: DPID (Bitfield-Mask: 0x03) */ -#define USB_GRXSTSP_DEVICEMODE_PktSts_Pos \ - (17UL) /*!< USB GRXSTSP_DEVICEMODE: PktSts (Bit 17) */ -#define USB_GRXSTSP_DEVICEMODE_PktSts_Msk \ - (0x1e0000UL) /*!< USB GRXSTSP_DEVICEMODE: PktSts (Bitfield-Mask: 0x0f) */ -#define USB_GRXSTSP_DEVICEMODE_FN_Pos \ - (21UL) /*!< USB GRXSTSP_DEVICEMODE: FN (Bit 21) */ -#define USB_GRXSTSP_DEVICEMODE_FN_Msk \ - (0x1e00000UL) /*!< USB GRXSTSP_DEVICEMODE: FN (Bitfield-Mask: 0x0f) */ - -/* ---------------------------- USB_GRXSTSP_HOSTMODE ---------------------------- */ -#define USB_GRXSTSP_HOSTMODE_ChNum_Pos \ - (0UL) /*!< USB GRXSTSP_HOSTMODE: ChNum (Bit 0) */ -#define USB_GRXSTSP_HOSTMODE_ChNum_Msk \ - (0xfUL) /*!< USB GRXSTSP_HOSTMODE: ChNum (Bitfield-Mask: 0x0f) */ -#define USB_GRXSTSP_HOSTMODE_BCnt_Pos \ - (4UL) /*!< USB GRXSTSP_HOSTMODE: BCnt (Bit 4) */ -#define USB_GRXSTSP_HOSTMODE_BCnt_Msk \ - (0x7ff0UL) /*!< USB GRXSTSP_HOSTMODE: BCnt (Bitfield-Mask: 0x7ff) */ -#define USB_GRXSTSP_HOSTMODE_DPID_Pos \ - (15UL) /*!< USB GRXSTSP_HOSTMODE: DPID (Bit 15) */ -#define USB_GRXSTSP_HOSTMODE_DPID_Msk \ - (0x18000UL) /*!< USB GRXSTSP_HOSTMODE: DPID (Bitfield-Mask: 0x03) */ -#define USB_GRXSTSP_HOSTMODE_PktSts_Pos \ - (17UL) /*!< USB GRXSTSP_HOSTMODE: PktSts (Bit 17) */ -#define USB_GRXSTSP_HOSTMODE_PktSts_Msk \ - (0x1e0000UL) /*!< USB GRXSTSP_HOSTMODE: PktSts (Bitfield-Mask: 0x0f) */ - -/* --------------------------------- USB_GRXFSIZ -------------------------------- */ -#define USB_GRXFSIZ_RxFDep_Pos \ - (0UL) /*!< USB GRXFSIZ: RxFDep (Bit 0) */ -#define USB_GRXFSIZ_RxFDep_Msk \ - (0xffffUL) /*!< USB GRXFSIZ: RxFDep (Bitfield-Mask: 0xffff) */ - -/* --------------------------- USB_GNPTXFSIZ_HOSTMODE --------------------------- */ -#define USB_GNPTXFSIZ_HOSTMODE_NPTxFStAddr_Pos \ - (0UL) /*!< USB GNPTXFSIZ_HOSTMODE: NPTxFStAddr (Bit 0) */ -#define USB_GNPTXFSIZ_HOSTMODE_NPTxFStAddr_Msk \ - (0xffffUL) /*!< USB GNPTXFSIZ_HOSTMODE: NPTxFStAddr (Bitfield-Mask: 0xffff) */ -#define USB_GNPTXFSIZ_HOSTMODE_NPTxFDep_Pos \ - (16UL) /*!< USB GNPTXFSIZ_HOSTMODE: NPTxFDep (Bit 16) */ -#define USB_GNPTXFSIZ_HOSTMODE_NPTxFDep_Msk \ - (0xffff0000UL) /*!< USB GNPTXFSIZ_HOSTMODE: NPTxFDep (Bitfield-Mask: 0xffff) */ - -/* -------------------------- USB_GNPTXFSIZ_DEVICEMODE -------------------------- */ -#define USB_GNPTXFSIZ_DEVICEMODE_INEPTxF0StAddr_Pos \ - (0UL) /*!< USB GNPTXFSIZ_DEVICEMODE: INEPTxF0StAddr (Bit 0) */ -#define USB_GNPTXFSIZ_DEVICEMODE_INEPTxF0StAddr_Msk \ - (0xffffUL) /*!< USB GNPTXFSIZ_DEVICEMODE: INEPTxF0StAddr (Bitfield-Mask: 0xffff) */ -#define USB_GNPTXFSIZ_DEVICEMODE_INEPTxF0Dep_Pos \ - (16UL) /*!< USB GNPTXFSIZ_DEVICEMODE: INEPTxF0Dep (Bit 16) */ -#define USB_GNPTXFSIZ_DEVICEMODE_INEPTxF0Dep_Msk \ - (0xffff0000UL) /*!< USB GNPTXFSIZ_DEVICEMODE: INEPTxF0Dep (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- USB_GNPTXSTS -------------------------------- */ -#define USB_GNPTXSTS_NPTxFSpcAvail_Pos \ - (0UL) /*!< USB GNPTXSTS: NPTxFSpcAvail (Bit 0) */ -#define USB_GNPTXSTS_NPTxFSpcAvail_Msk \ - (0xffffUL) /*!< USB GNPTXSTS: NPTxFSpcAvail (Bitfield-Mask: 0xffff) */ -#define USB_GNPTXSTS_NPTxQSpcAvail_Pos \ - (16UL) /*!< USB GNPTXSTS: NPTxQSpcAvail (Bit 16) */ -#define USB_GNPTXSTS_NPTxQSpcAvail_Msk \ - (0xff0000UL) /*!< USB GNPTXSTS: NPTxQSpcAvail (Bitfield-Mask: 0xff) */ -#define USB_GNPTXSTS_NPTxQTop_Pos \ - (24UL) /*!< USB GNPTXSTS: NPTxQTop (Bit 24) */ -#define USB_GNPTXSTS_NPTxQTop_Msk \ - (0x7f000000UL) /*!< USB GNPTXSTS: NPTxQTop (Bitfield-Mask: 0x7f) */ - -/* ---------------------------------- USB_GUID ---------------------------------- */ -#define USB_GUID_MOD_REV_Pos \ - (0UL) /*!< USB GUID: MOD_REV (Bit 0) */ -#define USB_GUID_MOD_REV_Msk \ - (0xffUL) /*!< USB GUID: MOD_REV (Bitfield-Mask: 0xff) */ -#define USB_GUID_MOD_TYPE_Pos \ - (8UL) /*!< USB GUID: MOD_TYPE (Bit 8) */ -#define USB_GUID_MOD_TYPE_Msk \ - (0xff00UL) /*!< USB GUID: MOD_TYPE (Bitfield-Mask: 0xff) */ -#define USB_GUID_MOD_NUMBER_Pos \ - (16UL) /*!< USB GUID: MOD_NUMBER (Bit 16) */ -#define USB_GUID_MOD_NUMBER_Msk \ - (0xffff0000UL) /*!< USB GUID: MOD_NUMBER (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- USB_GDFIFOCFG ------------------------------- */ -#define USB_GDFIFOCFG_GDFIFOCfg_Pos \ - (0UL) /*!< USB GDFIFOCFG: GDFIFOCfg (Bit 0) */ -#define USB_GDFIFOCFG_GDFIFOCfg_Msk \ - (0xffffUL) /*!< USB GDFIFOCFG: GDFIFOCfg (Bitfield-Mask: 0xffff) */ -#define USB_GDFIFOCFG_EPInfoBaseAddr_Pos \ - (16UL) /*!< USB GDFIFOCFG: EPInfoBaseAddr (Bit 16) */ -#define USB_GDFIFOCFG_EPInfoBaseAddr_Msk \ - (0xffff0000UL) /*!< USB GDFIFOCFG: EPInfoBaseAddr (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- USB_HPTXFSIZ -------------------------------- */ -#define USB_HPTXFSIZ_PTxFStAddr_Pos \ - (0UL) /*!< USB HPTXFSIZ: PTxFStAddr (Bit 0) */ -#define USB_HPTXFSIZ_PTxFStAddr_Msk \ - (0xffffUL) /*!< USB HPTXFSIZ: PTxFStAddr (Bitfield-Mask: 0xffff) */ -#define USB_HPTXFSIZ_PTxFSize_Pos \ - (16UL) /*!< USB HPTXFSIZ: PTxFSize (Bit 16) */ -#define USB_HPTXFSIZ_PTxFSize_Msk \ - (0xffff0000UL) /*!< USB HPTXFSIZ: PTxFSize (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- USB_DIEPTXF1 -------------------------------- */ -#define USB_DIEPTXF1_INEPnTxFStAddr_Pos \ - (0UL) /*!< USB DIEPTXF1: INEPnTxFStAddr (Bit 0) */ -#define USB_DIEPTXF1_INEPnTxFStAddr_Msk \ - (0xffffUL) /*!< USB DIEPTXF1: INEPnTxFStAddr (Bitfield-Mask: 0xffff) */ -#define USB_DIEPTXF1_INEPnTxFDep_Pos \ - (16UL) /*!< USB DIEPTXF1: INEPnTxFDep (Bit 16) */ -#define USB_DIEPTXF1_INEPnTxFDep_Msk \ - (0xffff0000UL) /*!< USB DIEPTXF1: INEPnTxFDep (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- USB_DIEPTXF2 -------------------------------- */ -#define USB_DIEPTXF2_INEPnTxFStAddr_Pos \ - (0UL) /*!< USB DIEPTXF2: INEPnTxFStAddr (Bit 0) */ -#define USB_DIEPTXF2_INEPnTxFStAddr_Msk \ - (0xffffUL) /*!< USB DIEPTXF2: INEPnTxFStAddr (Bitfield-Mask: 0xffff) */ -#define USB_DIEPTXF2_INEPnTxFDep_Pos \ - (16UL) /*!< USB DIEPTXF2: INEPnTxFDep (Bit 16) */ -#define USB_DIEPTXF2_INEPnTxFDep_Msk \ - (0xffff0000UL) /*!< USB DIEPTXF2: INEPnTxFDep (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- USB_DIEPTXF3 -------------------------------- */ -#define USB_DIEPTXF3_INEPnTxFStAddr_Pos \ - (0UL) /*!< USB DIEPTXF3: INEPnTxFStAddr (Bit 0) */ -#define USB_DIEPTXF3_INEPnTxFStAddr_Msk \ - (0xffffUL) /*!< USB DIEPTXF3: INEPnTxFStAddr (Bitfield-Mask: 0xffff) */ -#define USB_DIEPTXF3_INEPnTxFDep_Pos \ - (16UL) /*!< USB DIEPTXF3: INEPnTxFDep (Bit 16) */ -#define USB_DIEPTXF3_INEPnTxFDep_Msk \ - (0xffff0000UL) /*!< USB DIEPTXF3: INEPnTxFDep (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- USB_DIEPTXF4 -------------------------------- */ -#define USB_DIEPTXF4_INEPnTxFStAddr_Pos \ - (0UL) /*!< USB DIEPTXF4: INEPnTxFStAddr (Bit 0) */ -#define USB_DIEPTXF4_INEPnTxFStAddr_Msk \ - (0xffffUL) /*!< USB DIEPTXF4: INEPnTxFStAddr (Bitfield-Mask: 0xffff) */ -#define USB_DIEPTXF4_INEPnTxFDep_Pos \ - (16UL) /*!< USB DIEPTXF4: INEPnTxFDep (Bit 16) */ -#define USB_DIEPTXF4_INEPnTxFDep_Msk \ - (0xffff0000UL) /*!< USB DIEPTXF4: INEPnTxFDep (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- USB_DIEPTXF5 -------------------------------- */ -#define USB_DIEPTXF5_INEPnTxFStAddr_Pos \ - (0UL) /*!< USB DIEPTXF5: INEPnTxFStAddr (Bit 0) */ -#define USB_DIEPTXF5_INEPnTxFStAddr_Msk \ - (0xffffUL) /*!< USB DIEPTXF5: INEPnTxFStAddr (Bitfield-Mask: 0xffff) */ -#define USB_DIEPTXF5_INEPnTxFDep_Pos \ - (16UL) /*!< USB DIEPTXF5: INEPnTxFDep (Bit 16) */ -#define USB_DIEPTXF5_INEPnTxFDep_Msk \ - (0xffff0000UL) /*!< USB DIEPTXF5: INEPnTxFDep (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- USB_DIEPTXF6 -------------------------------- */ -#define USB_DIEPTXF6_INEPnTxFStAddr_Pos \ - (0UL) /*!< USB DIEPTXF6: INEPnTxFStAddr (Bit 0) */ -#define USB_DIEPTXF6_INEPnTxFStAddr_Msk \ - (0xffffUL) /*!< USB DIEPTXF6: INEPnTxFStAddr (Bitfield-Mask: 0xffff) */ -#define USB_DIEPTXF6_INEPnTxFDep_Pos \ - (16UL) /*!< USB DIEPTXF6: INEPnTxFDep (Bit 16) */ -#define USB_DIEPTXF6_INEPnTxFDep_Msk \ - (0xffff0000UL) /*!< USB DIEPTXF6: INEPnTxFDep (Bitfield-Mask: 0xffff) */ - -/* ---------------------------------- USB_HCFG ---------------------------------- */ -#define USB_HCFG_FSLSPclkSel_Pos \ - (0UL) /*!< USB HCFG: FSLSPclkSel (Bit 0) */ -#define USB_HCFG_FSLSPclkSel_Msk \ - (0x3UL) /*!< USB HCFG: FSLSPclkSel (Bitfield-Mask: 0x03) */ -#define USB_HCFG_FSLSSupp_Pos \ - (2UL) /*!< USB HCFG: FSLSSupp (Bit 2) */ -#define USB_HCFG_FSLSSupp_Msk \ - (0x4UL) /*!< USB HCFG: FSLSSupp (Bitfield-Mask: 0x01) */ -#define USB_HCFG_DescDMA_Pos \ - (23UL) /*!< USB HCFG: DescDMA (Bit 23) */ -#define USB_HCFG_DescDMA_Msk \ - (0x800000UL) /*!< USB HCFG: DescDMA (Bitfield-Mask: 0x01) */ -#define USB_HCFG_FrListEn_Pos \ - (24UL) /*!< USB HCFG: FrListEn (Bit 24) */ -#define USB_HCFG_FrListEn_Msk \ - (0x3000000UL) /*!< USB HCFG: FrListEn (Bitfield-Mask: 0x03) */ -#define USB_HCFG_PerSchedEna_Pos \ - (26UL) /*!< USB HCFG: PerSchedEna (Bit 26) */ -#define USB_HCFG_PerSchedEna_Msk \ - (0x4000000UL) /*!< USB HCFG: PerSchedEna (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- USB_HFIR ---------------------------------- */ -#define USB_HFIR_FrInt_Pos (0UL) /*!< USB HFIR: FrInt (Bit 0) */ -#define USB_HFIR_FrInt_Msk \ - (0xffffUL) /*!< USB HFIR: FrInt (Bitfield-Mask: 0xffff) */ -#define USB_HFIR_HFIRRldCtrl_Pos \ - (16UL) /*!< USB HFIR: HFIRRldCtrl (Bit 16) */ -#define USB_HFIR_HFIRRldCtrl_Msk \ - (0x10000UL) /*!< USB HFIR: HFIRRldCtrl (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- USB_HFNUM --------------------------------- */ -#define USB_HFNUM_FrNum_Pos \ - (0UL) /*!< USB HFNUM: FrNum (Bit 0) */ -#define USB_HFNUM_FrNum_Msk \ - (0xffffUL) /*!< USB HFNUM: FrNum (Bitfield-Mask: 0xffff) */ -#define USB_HFNUM_FrRem_Pos \ - (16UL) /*!< USB HFNUM: FrRem (Bit 16) */ -#define USB_HFNUM_FrRem_Msk \ - (0xffff0000UL) /*!< USB HFNUM: FrRem (Bitfield-Mask: 0xffff) */ - -/* --------------------------------- USB_HPTXSTS -------------------------------- */ -#define USB_HPTXSTS_PTxFSpcAvail_Pos \ - (0UL) /*!< USB HPTXSTS: PTxFSpcAvail (Bit 0) */ -#define USB_HPTXSTS_PTxFSpcAvail_Msk \ - (0xffffUL) /*!< USB HPTXSTS: PTxFSpcAvail (Bitfield-Mask: 0xffff) */ -#define USB_HPTXSTS_PTxQSpcAvail_Pos \ - (16UL) /*!< USB HPTXSTS: PTxQSpcAvail (Bit 16) */ -#define USB_HPTXSTS_PTxQSpcAvail_Msk \ - (0xff0000UL) /*!< USB HPTXSTS: PTxQSpcAvail (Bitfield-Mask: 0xff) */ -#define USB_HPTXSTS_PTxQTop_Pos \ - (24UL) /*!< USB HPTXSTS: PTxQTop (Bit 24) */ -#define USB_HPTXSTS_PTxQTop_Msk \ - (0xff000000UL) /*!< USB HPTXSTS: PTxQTop (Bitfield-Mask: 0xff) */ - -/* ---------------------------------- USB_HAINT --------------------------------- */ -#define USB_HAINT_HAINT_Pos \ - (0UL) /*!< USB HAINT: HAINT (Bit 0) */ -#define USB_HAINT_HAINT_Msk \ - (0x3fffUL) /*!< USB HAINT: HAINT (Bitfield-Mask: 0x3fff) */ - -/* -------------------------------- USB_HAINTMSK -------------------------------- */ -#define USB_HAINTMSK_HAINTMsk_Pos \ - (0UL) /*!< USB HAINTMSK: HAINTMsk (Bit 0) */ -#define USB_HAINTMSK_HAINTMsk_Msk \ - (0x3fffUL) /*!< USB HAINTMSK: HAINTMsk (Bitfield-Mask: 0x3fff) */ - -/* -------------------------------- USB_HFLBADDR -------------------------------- */ -#define USB_HFLBADDR_Starting_Address_Pos \ - (0UL) /*!< USB HFLBADDR: Starting_Address (Bit 0) */ -#define USB_HFLBADDR_Starting_Address_Msk \ - (0xffffffffUL) /*!< USB HFLBADDR: Starting_Address (Bitfield-Mask: 0xffffffff) */ - -/* ---------------------------------- USB_HPRT ---------------------------------- */ -#define USB_HPRT_PrtConnSts_Pos \ - (0UL) /*!< USB HPRT: PrtConnSts (Bit 0) */ -#define USB_HPRT_PrtConnSts_Msk \ - (0x1UL) /*!< USB HPRT: PrtConnSts (Bitfield-Mask: 0x01) */ -#define USB_HPRT_PrtConnDet_Pos \ - (1UL) /*!< USB HPRT: PrtConnDet (Bit 1) */ -#define USB_HPRT_PrtConnDet_Msk \ - (0x2UL) /*!< USB HPRT: PrtConnDet (Bitfield-Mask: 0x01) */ -#define USB_HPRT_PrtEna_Pos \ - (2UL) /*!< USB HPRT: PrtEna (Bit 2) */ -#define USB_HPRT_PrtEna_Msk \ - (0x4UL) /*!< USB HPRT: PrtEna (Bitfield-Mask: 0x01) */ -#define USB_HPRT_PrtEnChng_Pos \ - (3UL) /*!< USB HPRT: PrtEnChng (Bit 3) */ -#define USB_HPRT_PrtEnChng_Msk \ - (0x8UL) /*!< USB HPRT: PrtEnChng (Bitfield-Mask: 0x01) */ -#define USB_HPRT_PrtOvrCurrAct_Pos \ - (4UL) /*!< USB HPRT: PrtOvrCurrAct (Bit 4) */ -#define USB_HPRT_PrtOvrCurrAct_Msk \ - (0x10UL) /*!< USB HPRT: PrtOvrCurrAct (Bitfield-Mask: 0x01) */ -#define USB_HPRT_PrtOvrCurrChng_Pos \ - (5UL) /*!< USB HPRT: PrtOvrCurrChng (Bit 5) */ -#define USB_HPRT_PrtOvrCurrChng_Msk \ - (0x20UL) /*!< USB HPRT: PrtOvrCurrChng (Bitfield-Mask: 0x01) */ -#define USB_HPRT_PrtRes_Pos \ - (6UL) /*!< USB HPRT: PrtRes (Bit 6) */ -#define USB_HPRT_PrtRes_Msk \ - (0x40UL) /*!< USB HPRT: PrtRes (Bitfield-Mask: 0x01) */ -#define USB_HPRT_PrtSusp_Pos \ - (7UL) /*!< USB HPRT: PrtSusp (Bit 7) */ -#define USB_HPRT_PrtSusp_Msk \ - (0x80UL) /*!< USB HPRT: PrtSusp (Bitfield-Mask: 0x01) */ -#define USB_HPRT_PrtRst_Pos \ - (8UL) /*!< USB HPRT: PrtRst (Bit 8) */ -#define USB_HPRT_PrtRst_Msk \ - (0x100UL) /*!< USB HPRT: PrtRst (Bitfield-Mask: 0x01) */ -#define USB_HPRT_PrtLnSts_Pos \ - (10UL) /*!< USB HPRT: PrtLnSts (Bit 10) */ -#define USB_HPRT_PrtLnSts_Msk \ - (0xc00UL) /*!< USB HPRT: PrtLnSts (Bitfield-Mask: 0x03) */ -#define USB_HPRT_PrtPwr_Pos \ - (12UL) /*!< USB HPRT: PrtPwr (Bit 12) */ -#define USB_HPRT_PrtPwr_Msk \ - (0x1000UL) /*!< USB HPRT: PrtPwr (Bitfield-Mask: 0x01) */ -#define USB_HPRT_PrtSpd_Pos \ - (17UL) /*!< USB HPRT: PrtSpd (Bit 17) */ -#define USB_HPRT_PrtSpd_Msk \ - (0x60000UL) /*!< USB HPRT: PrtSpd (Bitfield-Mask: 0x03) */ - -/* ---------------------------------- USB_DCFG ---------------------------------- */ -#define USB_DCFG_DevSpd_Pos \ - (0UL) /*!< USB DCFG: DevSpd (Bit 0) */ -#define USB_DCFG_DevSpd_Msk \ - (0x3UL) /*!< USB DCFG: DevSpd (Bitfield-Mask: 0x03) */ -#define USB_DCFG_NZStsOUTHShk_Pos \ - (2UL) /*!< USB DCFG: NZStsOUTHShk (Bit 2) */ -#define USB_DCFG_NZStsOUTHShk_Msk \ - (0x4UL) /*!< USB DCFG: NZStsOUTHShk (Bitfield-Mask: 0x01) */ -#define USB_DCFG_DevAddr_Pos \ - (4UL) /*!< USB DCFG: DevAddr (Bit 4) */ -#define USB_DCFG_DevAddr_Msk \ - (0x7f0UL) /*!< USB DCFG: DevAddr (Bitfield-Mask: 0x7f) */ -#define USB_DCFG_PerFrInt_Pos \ - (11UL) /*!< USB DCFG: PerFrInt (Bit 11) */ -#define USB_DCFG_PerFrInt_Msk \ - (0x1800UL) /*!< USB DCFG: PerFrInt (Bitfield-Mask: 0x03) */ -#define USB_DCFG_DescDMA_Pos \ - (23UL) /*!< USB DCFG: DescDMA (Bit 23) */ -#define USB_DCFG_DescDMA_Msk \ - (0x800000UL) /*!< USB DCFG: DescDMA (Bitfield-Mask: 0x01) */ -#define USB_DCFG_PerSchIntvl_Pos \ - (24UL) /*!< USB DCFG: PerSchIntvl (Bit 24) */ -#define USB_DCFG_PerSchIntvl_Msk \ - (0x3000000UL) /*!< USB DCFG: PerSchIntvl (Bitfield-Mask: 0x03) */ - -/* ---------------------------------- USB_DCTL ---------------------------------- */ -#define USB_DCTL_RmtWkUpSig_Pos \ - (0UL) /*!< USB DCTL: RmtWkUpSig (Bit 0) */ -#define USB_DCTL_RmtWkUpSig_Msk \ - (0x1UL) /*!< USB DCTL: RmtWkUpSig (Bitfield-Mask: 0x01) */ -#define USB_DCTL_SftDiscon_Pos \ - (1UL) /*!< USB DCTL: SftDiscon (Bit 1) */ -#define USB_DCTL_SftDiscon_Msk \ - (0x2UL) /*!< USB DCTL: SftDiscon (Bitfield-Mask: 0x01) */ -#define USB_DCTL_GNPINNakSts_Pos \ - (2UL) /*!< USB DCTL: GNPINNakSts (Bit 2) */ -#define USB_DCTL_GNPINNakSts_Msk \ - (0x4UL) /*!< USB DCTL: GNPINNakSts (Bitfield-Mask: 0x01) */ -#define USB_DCTL_GOUTNakSts_Pos \ - (3UL) /*!< USB DCTL: GOUTNakSts (Bit 3) */ -#define USB_DCTL_GOUTNakSts_Msk \ - (0x8UL) /*!< USB DCTL: GOUTNakSts (Bitfield-Mask: 0x01) */ -#define USB_DCTL_SGNPInNak_Pos \ - (7UL) /*!< USB DCTL: SGNPInNak (Bit 7) */ -#define USB_DCTL_SGNPInNak_Msk \ - (0x80UL) /*!< USB DCTL: SGNPInNak (Bitfield-Mask: 0x01) */ -#define USB_DCTL_CGNPInNak_Pos \ - (8UL) /*!< USB DCTL: CGNPInNak (Bit 8) */ -#define USB_DCTL_CGNPInNak_Msk \ - (0x100UL) /*!< USB DCTL: CGNPInNak (Bitfield-Mask: 0x01) */ -#define USB_DCTL_SGOUTNak_Pos \ - (9UL) /*!< USB DCTL: SGOUTNak (Bit 9) */ -#define USB_DCTL_SGOUTNak_Msk \ - (0x200UL) /*!< USB DCTL: SGOUTNak (Bitfield-Mask: 0x01) */ -#define USB_DCTL_CGOUTNak_Pos \ - (10UL) /*!< USB DCTL: CGOUTNak (Bit 10) */ -#define USB_DCTL_CGOUTNak_Msk \ - (0x400UL) /*!< USB DCTL: CGOUTNak (Bitfield-Mask: 0x01) */ -#define USB_DCTL_GMC_Pos (13UL) /*!< USB DCTL: GMC (Bit 13) */ -#define USB_DCTL_GMC_Msk \ - (0x6000UL) /*!< USB DCTL: GMC (Bitfield-Mask: 0x03) */ -#define USB_DCTL_IgnrFrmNum_Pos \ - (15UL) /*!< USB DCTL: IgnrFrmNum (Bit 15) */ -#define USB_DCTL_IgnrFrmNum_Msk \ - (0x8000UL) /*!< USB DCTL: IgnrFrmNum (Bitfield-Mask: 0x01) */ -#define USB_DCTL_NakOnBble_Pos \ - (16UL) /*!< USB DCTL: NakOnBble (Bit 16) */ -#define USB_DCTL_NakOnBble_Msk \ - (0x10000UL) /*!< USB DCTL: NakOnBble (Bitfield-Mask: 0x01) */ -#define USB_DCTL_EnContOnBNA_Pos \ - (17UL) /*!< USB DCTL: EnContOnBNA (Bit 17) */ -#define USB_DCTL_EnContOnBNA_Msk \ - (0x20000UL) /*!< USB DCTL: EnContOnBNA (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- USB_DSTS ---------------------------------- */ -#define USB_DSTS_SuspSts_Pos \ - (0UL) /*!< USB DSTS: SuspSts (Bit 0) */ -#define USB_DSTS_SuspSts_Msk \ - (0x1UL) /*!< USB DSTS: SuspSts (Bitfield-Mask: 0x01) */ -#define USB_DSTS_EnumSpd_Pos \ - (1UL) /*!< USB DSTS: EnumSpd (Bit 1) */ -#define USB_DSTS_EnumSpd_Msk \ - (0x6UL) /*!< USB DSTS: EnumSpd (Bitfield-Mask: 0x03) */ -#define USB_DSTS_ErrticErr_Pos \ - (3UL) /*!< USB DSTS: ErrticErr (Bit 3) */ -#define USB_DSTS_ErrticErr_Msk \ - (0x8UL) /*!< USB DSTS: ErrticErr (Bitfield-Mask: 0x01) */ -#define USB_DSTS_SOFFN_Pos (8UL) /*!< USB DSTS: SOFFN (Bit 8) */ -#define USB_DSTS_SOFFN_Msk \ - (0x3fff00UL) /*!< USB DSTS: SOFFN (Bitfield-Mask: 0x3fff) */ - -/* --------------------------------- USB_DIEPMSK -------------------------------- */ -#define USB_DIEPMSK_XferComplMsk_Pos \ - (0UL) /*!< USB DIEPMSK: XferComplMsk (Bit 0) */ -#define USB_DIEPMSK_XferComplMsk_Msk \ - (0x1UL) /*!< USB DIEPMSK: XferComplMsk (Bitfield-Mask: 0x01) */ -#define USB_DIEPMSK_EPDisbldMsk_Pos \ - (1UL) /*!< USB DIEPMSK: EPDisbldMsk (Bit 1) */ -#define USB_DIEPMSK_EPDisbldMsk_Msk \ - (0x2UL) /*!< USB DIEPMSK: EPDisbldMsk (Bitfield-Mask: 0x01) */ -#define USB_DIEPMSK_AHBErrMsk_Pos \ - (2UL) /*!< USB DIEPMSK: AHBErrMsk (Bit 2) */ -#define USB_DIEPMSK_AHBErrMsk_Msk \ - (0x4UL) /*!< USB DIEPMSK: AHBErrMsk (Bitfield-Mask: 0x01) */ -#define USB_DIEPMSK_TimeOUTMsk_Pos \ - (3UL) /*!< USB DIEPMSK: TimeOUTMsk (Bit 3) */ -#define USB_DIEPMSK_TimeOUTMsk_Msk \ - (0x8UL) /*!< USB DIEPMSK: TimeOUTMsk (Bitfield-Mask: 0x01) */ -#define USB_DIEPMSK_INTknTXFEmpMsk_Pos \ - (4UL) /*!< USB DIEPMSK: INTknTXFEmpMsk (Bit 4) */ -#define USB_DIEPMSK_INTknTXFEmpMsk_Msk \ - (0x10UL) /*!< USB DIEPMSK: INTknTXFEmpMsk (Bitfield-Mask: 0x01) */ -#define USB_DIEPMSK_INEPNakEffMsk_Pos \ - (6UL) /*!< USB DIEPMSK: INEPNakEffMsk (Bit 6) */ -#define USB_DIEPMSK_INEPNakEffMsk_Msk \ - (0x40UL) /*!< USB DIEPMSK: INEPNakEffMsk (Bitfield-Mask: 0x01) */ -#define USB_DIEPMSK_TxfifoUndrnMsk_Pos \ - (8UL) /*!< USB DIEPMSK: TxfifoUndrnMsk (Bit 8) */ -#define USB_DIEPMSK_TxfifoUndrnMsk_Msk \ - (0x100UL) /*!< USB DIEPMSK: TxfifoUndrnMsk (Bitfield-Mask: 0x01) */ -#define USB_DIEPMSK_BNAInIntrMsk_Pos \ - (9UL) /*!< USB DIEPMSK: BNAInIntrMsk (Bit 9) */ -#define USB_DIEPMSK_BNAInIntrMsk_Msk \ - (0x200UL) /*!< USB DIEPMSK: BNAInIntrMsk (Bitfield-Mask: 0x01) */ -#define USB_DIEPMSK_NAKMsk_Pos \ - (13UL) /*!< USB DIEPMSK: NAKMsk (Bit 13) */ -#define USB_DIEPMSK_NAKMsk_Msk \ - (0x2000UL) /*!< USB DIEPMSK: NAKMsk (Bitfield-Mask: 0x01) */ - -/* --------------------------------- USB_DOEPMSK -------------------------------- */ -#define USB_DOEPMSK_XferComplMsk_Pos \ - (0UL) /*!< USB DOEPMSK: XferComplMsk (Bit 0) */ -#define USB_DOEPMSK_XferComplMsk_Msk \ - (0x1UL) /*!< USB DOEPMSK: XferComplMsk (Bitfield-Mask: 0x01) */ -#define USB_DOEPMSK_EPDisbldMsk_Pos \ - (1UL) /*!< USB DOEPMSK: EPDisbldMsk (Bit 1) */ -#define USB_DOEPMSK_EPDisbldMsk_Msk \ - (0x2UL) /*!< USB DOEPMSK: EPDisbldMsk (Bitfield-Mask: 0x01) */ -#define USB_DOEPMSK_AHBErrMsk_Pos \ - (2UL) /*!< USB DOEPMSK: AHBErrMsk (Bit 2) */ -#define USB_DOEPMSK_AHBErrMsk_Msk \ - (0x4UL) /*!< USB DOEPMSK: AHBErrMsk (Bitfield-Mask: 0x01) */ -#define USB_DOEPMSK_SetUPMsk_Pos \ - (3UL) /*!< USB DOEPMSK: SetUPMsk (Bit 3) */ -#define USB_DOEPMSK_SetUPMsk_Msk \ - (0x8UL) /*!< USB DOEPMSK: SetUPMsk (Bitfield-Mask: 0x01) */ -#define USB_DOEPMSK_OUTTknEPdisMsk_Pos \ - (4UL) /*!< USB DOEPMSK: OUTTknEPdisMsk (Bit 4) */ -#define USB_DOEPMSK_OUTTknEPdisMsk_Msk \ - (0x10UL) /*!< USB DOEPMSK: OUTTknEPdisMsk (Bitfield-Mask: 0x01) */ -#define USB_DOEPMSK_Back2BackSETup_Pos \ - (6UL) /*!< USB DOEPMSK: Back2BackSETup (Bit 6) */ -#define USB_DOEPMSK_Back2BackSETup_Msk \ - (0x40UL) /*!< USB DOEPMSK: Back2BackSETup (Bitfield-Mask: 0x01) */ -#define USB_DOEPMSK_OutPktErrMsk_Pos \ - (8UL) /*!< USB DOEPMSK: OutPktErrMsk (Bit 8) */ -#define USB_DOEPMSK_OutPktErrMsk_Msk \ - (0x100UL) /*!< USB DOEPMSK: OutPktErrMsk (Bitfield-Mask: 0x01) */ -#define USB_DOEPMSK_BnaOutIntrMsk_Pos \ - (9UL) /*!< USB DOEPMSK: BnaOutIntrMsk (Bit 9) */ -#define USB_DOEPMSK_BnaOutIntrMsk_Msk \ - (0x200UL) /*!< USB DOEPMSK: BnaOutIntrMsk (Bitfield-Mask: 0x01) */ -#define USB_DOEPMSK_BbleErrMsk_Pos \ - (12UL) /*!< USB DOEPMSK: BbleErrMsk (Bit 12) */ -#define USB_DOEPMSK_BbleErrMsk_Msk \ - (0x1000UL) /*!< USB DOEPMSK: BbleErrMsk (Bitfield-Mask: 0x01) */ -#define USB_DOEPMSK_NAKMsk_Pos \ - (13UL) /*!< USB DOEPMSK: NAKMsk (Bit 13) */ -#define USB_DOEPMSK_NAKMsk_Msk \ - (0x2000UL) /*!< USB DOEPMSK: NAKMsk (Bitfield-Mask: 0x01) */ -#define USB_DOEPMSK_NYETMsk_Pos \ - (14UL) /*!< USB DOEPMSK: NYETMsk (Bit 14) */ -#define USB_DOEPMSK_NYETMsk_Msk \ - (0x4000UL) /*!< USB DOEPMSK: NYETMsk (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- USB_DAINT --------------------------------- */ -#define USB_DAINT_InEpInt_Pos \ - (0UL) /*!< USB DAINT: InEpInt (Bit 0) */ -#define USB_DAINT_InEpInt_Msk \ - (0xffffUL) /*!< USB DAINT: InEpInt (Bitfield-Mask: 0xffff) */ -#define USB_DAINT_OutEPInt_Pos \ - (16UL) /*!< USB DAINT: OutEPInt (Bit 16) */ -#define USB_DAINT_OutEPInt_Msk \ - (0xffff0000UL) /*!< USB DAINT: OutEPInt (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- USB_DAINTMSK -------------------------------- */ -#define USB_DAINTMSK_InEpMsk_Pos \ - (0UL) /*!< USB DAINTMSK: InEpMsk (Bit 0) */ -#define USB_DAINTMSK_InEpMsk_Msk \ - (0xffffUL) /*!< USB DAINTMSK: InEpMsk (Bitfield-Mask: 0xffff) */ -#define USB_DAINTMSK_OutEpMsk_Pos \ - (16UL) /*!< USB DAINTMSK: OutEpMsk (Bit 16) */ -#define USB_DAINTMSK_OutEpMsk_Msk \ - (0xffff0000UL) /*!< USB DAINTMSK: OutEpMsk (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- USB_DVBUSDIS -------------------------------- */ -#define USB_DVBUSDIS_DVBUSDis_Pos \ - (0UL) /*!< USB DVBUSDIS: DVBUSDis (Bit 0) */ -#define USB_DVBUSDIS_DVBUSDis_Msk \ - (0xffffUL) /*!< USB DVBUSDIS: DVBUSDis (Bitfield-Mask: 0xffff) */ - -/* ------------------------------- USB_DVBUSPULSE ------------------------------- */ -#define USB_DVBUSPULSE_DVBUSPulse_Pos \ - (0UL) /*!< USB DVBUSPULSE: DVBUSPulse (Bit 0) */ -#define USB_DVBUSPULSE_DVBUSPulse_Msk \ - (0xfffUL) /*!< USB DVBUSPULSE: DVBUSPulse (Bitfield-Mask: 0xfff) */ - -/* ------------------------------- USB_DIEPEMPMSK ------------------------------- */ -#define USB_DIEPEMPMSK_InEpTxfEmpMsk_Pos \ - (0UL) /*!< USB DIEPEMPMSK: InEpTxfEmpMsk (Bit 0) */ -#define USB_DIEPEMPMSK_InEpTxfEmpMsk_Msk \ - (0xffffUL) /*!< USB DIEPEMPMSK: InEpTxfEmpMsk (Bitfield-Mask: 0xffff) */ - -/* --------------------------------- USB_PCGCCTL -------------------------------- */ -#define USB_PCGCCTL_StopPclk_Pos \ - (0UL) /*!< USB PCGCCTL: StopPclk (Bit 0) */ -#define USB_PCGCCTL_StopPclk_Msk \ - (0x1UL) /*!< USB PCGCCTL: StopPclk (Bitfield-Mask: 0x01) */ -#define USB_PCGCCTL_GateHclk_Pos \ - (1UL) /*!< USB PCGCCTL: GateHclk (Bit 1) */ -#define USB_PCGCCTL_GateHclk_Msk \ - (0x2UL) /*!< USB PCGCCTL: GateHclk (Bitfield-Mask: 0x01) */ - -/* ================================================================================ */ -/* ================ struct 'USB0_EP0' Position & Mask ================ */ -/* ================================================================================ */ - -/* ------------------------------ USB_EP_DIEPCTL0 ----------------------------- */ -#define USB_EP_DIEPCTL0_MPS_Pos \ - (0UL) /*!< USB0_EP0 DIEPCTL0: MPS (Bit 0) */ -#define USB_EP_DIEPCTL0_MPS_Msk \ - (0x3UL) /*!< USB0_EP0 DIEPCTL0: MPS (Bitfield-Mask: 0x03) */ -#define USB_EP_DIEPCTL0_USBActEP_Pos \ - (15UL) /*!< USB0_EP0 DIEPCTL0: USBActEP (Bit 15) */ -#define USB_EP_DIEPCTL0_USBActEP_Msk \ - (0x8000UL) /*!< USB0_EP0 DIEPCTL0: USBActEP (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL0_NAKSts_Pos \ - (17UL) /*!< USB0_EP0 DIEPCTL0: NAKSts (Bit 17) */ -#define USB_EP_DIEPCTL0_NAKSts_Msk \ - (0x20000UL) /*!< USB0_EP0 DIEPCTL0: NAKSts (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL0_EPType_Pos \ - (18UL) /*!< USB0_EP0 DIEPCTL0: EPType (Bit 18) */ -#define USB_EP_DIEPCTL0_EPType_Msk \ - (0xc0000UL) /*!< USB0_EP0 DIEPCTL0: EPType (Bitfield-Mask: 0x03) */ -#define USB_EP_DIEPCTL0_Stall_Pos \ - (21UL) /*!< USB0_EP0 DIEPCTL0: Stall (Bit 21) */ -#define USB_EP_DIEPCTL0_Stall_Msk \ - (0x200000UL) /*!< USB0_EP0 DIEPCTL0: Stall (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL0_TxFNum_Pos \ - (22UL) /*!< USB0_EP0 DIEPCTL0: TxFNum (Bit 22) */ -#define USB_EP_DIEPCTL0_TxFNum_Msk \ - (0x3c00000UL) /*!< USB0_EP0 DIEPCTL0: TxFNum (Bitfield-Mask: 0x0f) */ -#define USB_EP_DIEPCTL0_CNAK_Pos \ - (26UL) /*!< USB0_EP0 DIEPCTL0: CNAK (Bit 26) */ -#define USB_EP_DIEPCTL0_CNAK_Msk \ - (0x4000000UL) /*!< USB0_EP0 DIEPCTL0: CNAK (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL0_SNAK_Pos \ - (27UL) /*!< USB0_EP0 DIEPCTL0: SNAK (Bit 27) */ -#define USB_EP_DIEPCTL0_SNAK_Msk \ - (0x8000000UL) /*!< USB0_EP0 DIEPCTL0: SNAK (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL0_EPDis_Pos \ - (30UL) /*!< USB0_EP0 DIEPCTL0: EPDis (Bit 30) */ -#define USB_EP_DIEPCTL0_EPDis_Msk \ - (0x40000000UL) /*!< USB0_EP0 DIEPCTL0: EPDis (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL0_EPEna_Pos \ - (31UL) /*!< USB0_EP0 DIEPCTL0: EPEna (Bit 31) */ -#define USB_EP_DIEPCTL0_EPEna_Msk \ - (0x80000000UL) /*!< USB0_EP0 DIEPCTL0: EPEna (Bitfield-Mask: 0x01) */ - -/* ------------------------------ USB_EP_DIEPINT0 ----------------------------- */ -#define USB_EP_DIEPINT0_XferCompl_Pos \ - (0UL) /*!< USB0_EP0 DIEPINT0: XferCompl (Bit 0) */ -#define USB_EP_DIEPINT0_XferCompl_Msk \ - (0x1UL) /*!< USB0_EP0 DIEPINT0: XferCompl (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPINT0_EPDisbld_Pos \ - (1UL) /*!< USB0_EP0 DIEPINT0: EPDisbld (Bit 1) */ -#define USB_EP_DIEPINT0_EPDisbld_Msk \ - (0x2UL) /*!< USB0_EP0 DIEPINT0: EPDisbld (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPINT0_AHBErr_Pos \ - (2UL) /*!< USB0_EP0 DIEPINT0: AHBErr (Bit 2) */ -#define USB_EP_DIEPINT0_AHBErr_Msk \ - (0x4UL) /*!< USB0_EP0 DIEPINT0: AHBErr (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPINT0_TimeOUT_Pos \ - (3UL) /*!< USB0_EP0 DIEPINT0: TimeOUT (Bit 3) */ -#define USB_EP_DIEPINT0_TimeOUT_Msk \ - (0x8UL) /*!< USB0_EP0 DIEPINT0: TimeOUT (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPINT0_INTknTXFEmp_Pos \ - (4UL) /*!< USB0_EP0 DIEPINT0: INTknTXFEmp (Bit 4) */ -#define USB_EP_DIEPINT0_INTknTXFEmp_Msk \ - (0x10UL) /*!< USB0_EP0 DIEPINT0: INTknTXFEmp (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPINT0_INEPNakEff_Pos \ - (6UL) /*!< USB0_EP0 DIEPINT0: INEPNakEff (Bit 6) */ -#define USB_EP_DIEPINT0_INEPNakEff_Msk \ - (0x40UL) /*!< USB0_EP0 DIEPINT0: INEPNakEff (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPINT0_TxFEmp_Pos \ - (7UL) /*!< USB0_EP0 DIEPINT0: TxFEmp (Bit 7) */ -#define USB_EP_DIEPINT0_TxFEmp_Msk \ - (0x80UL) /*!< USB0_EP0 DIEPINT0: TxFEmp (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPINT0_BNAIntr_Pos \ - (9UL) /*!< USB0_EP0 DIEPINT0: BNAIntr (Bit 9) */ -#define USB_EP_DIEPINT0_BNAIntr_Msk \ - (0x200UL) /*!< USB0_EP0 DIEPINT0: BNAIntr (Bitfield-Mask: 0x01) */ - -/* ----------------------------- USB_EP_DIEPTSIZ0 ----------------------------- */ -#define USB_EP_DIEPTSIZ0_XferSize_Pos \ - (0UL) /*!< USB0_EP0 DIEPTSIZ0: XferSize (Bit 0) */ -#define USB_EP_DIEPTSIZ0_XferSize_Msk \ - (0x7fUL) /*!< USB0_EP0 DIEPTSIZ0: XferSize (Bitfield-Mask: 0x7f) */ -#define USB_EP_DIEPTSIZ0_PktCnt_Pos \ - (19UL) /*!< USB0_EP0 DIEPTSIZ0: PktCnt (Bit 19) */ -#define USB_EP_DIEPTSIZ0_PktCnt_Msk \ - (0x180000UL) /*!< USB0_EP0 DIEPTSIZ0: PktCnt (Bitfield-Mask: 0x03) */ - -/* ------------------------------ USB_EP_DIEPDMA0 ----------------------------- */ -#define USB_EP_DIEPDMA0_DMAAddr_Pos \ - (0UL) /*!< USB0_EP0 DIEPDMA0: DMAAddr (Bit 0) */ -#define USB_EP_DIEPDMA0_DMAAddr_Msk \ - (0xffffffffUL) /*!< USB0_EP0 DIEPDMA0: DMAAddr (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------ USB_EP_DTXFSTS0 ----------------------------- */ -#define USB_EP_DTXFSTS0_INEPTxFSpcAvail_Pos \ - (0UL) /*!< USB0_EP0 DTXFSTS0: INEPTxFSpcAvail (Bit 0) */ -#define USB_EP_DTXFSTS0_INEPTxFSpcAvail_Msk \ - (0xffffUL) /*!< USB0_EP0 DTXFSTS0: INEPTxFSpcAvail (Bitfield-Mask: 0xffff) */ - -/* ----------------------------- USB_EP_DIEPDMAB0 ----------------------------- */ -#define USB_EP_DIEPDMAB0_DMABufferAddr_Pos \ - (0UL) /*!< USB0_EP0 DIEPDMAB0: DMABufferAddr (Bit 0) */ -#define USB_EP_DIEPDMAB0_DMABufferAddr_Msk \ - (0xffffffffUL) /*!< USB0_EP0 DIEPDMAB0: DMABufferAddr (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------ USB_EP_DOEPCTL0 ----------------------------- */ -#define USB_EP_DOEPCTL0_MPS_Pos \ - (0UL) /*!< USB0_EP0 DOEPCTL0: MPS (Bit 0) */ -#define USB_EP_DOEPCTL0_MPS_Msk \ - (0x3UL) /*!< USB0_EP0 DOEPCTL0: MPS (Bitfield-Mask: 0x03) */ -#define USB_EP_DOEPCTL0_USBActEP_Pos \ - (15UL) /*!< USB0_EP0 DOEPCTL0: USBActEP (Bit 15) */ -#define USB_EP_DOEPCTL0_USBActEP_Msk \ - (0x8000UL) /*!< USB0_EP0 DOEPCTL0: USBActEP (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL0_NAKSts_Pos \ - (17UL) /*!< USB0_EP0 DOEPCTL0: NAKSts (Bit 17) */ -#define USB_EP_DOEPCTL0_NAKSts_Msk \ - (0x20000UL) /*!< USB0_EP0 DOEPCTL0: NAKSts (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL0_EPType_Pos \ - (18UL) /*!< USB0_EP0 DOEPCTL0: EPType (Bit 18) */ -#define USB_EP_DOEPCTL0_EPType_Msk \ - (0xc0000UL) /*!< USB0_EP0 DOEPCTL0: EPType (Bitfield-Mask: 0x03) */ -#define USB_EP_DOEPCTL0_Snp_Pos \ - (20UL) /*!< USB0_EP0 DOEPCTL0: Snp (Bit 20) */ -#define USB_EP_DOEPCTL0_Snp_Msk \ - (0x100000UL) /*!< USB0_EP0 DOEPCTL0: Snp (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL0_Stall_Pos \ - (21UL) /*!< USB0_EP0 DOEPCTL0: Stall (Bit 21) */ -#define USB_EP_DOEPCTL0_Stall_Msk \ - (0x200000UL) /*!< USB0_EP0 DOEPCTL0: Stall (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL0_CNAK_Pos \ - (26UL) /*!< USB0_EP0 DOEPCTL0: CNAK (Bit 26) */ -#define USB_EP_DOEPCTL0_CNAK_Msk \ - (0x4000000UL) /*!< USB0_EP0 DOEPCTL0: CNAK (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL0_SNAK_Pos \ - (27UL) /*!< USB0_EP0 DOEPCTL0: SNAK (Bit 27) */ -#define USB_EP_DOEPCTL0_SNAK_Msk \ - (0x8000000UL) /*!< USB0_EP0 DOEPCTL0: SNAK (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL0_EPDis_Pos \ - (30UL) /*!< USB0_EP0 DOEPCTL0: EPDis (Bit 30) */ -#define USB_EP_DOEPCTL0_EPDis_Msk \ - (0x40000000UL) /*!< USB0_EP0 DOEPCTL0: EPDis (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL0_EPEna_Pos \ - (31UL) /*!< USB0_EP0 DOEPCTL0: EPEna (Bit 31) */ -#define USB_EP_DOEPCTL0_EPEna_Msk \ - (0x80000000UL) /*!< USB0_EP0 DOEPCTL0: EPEna (Bitfield-Mask: 0x01) */ - -/* ------------------------------ USB_EP_DOEPINT0 ----------------------------- */ -#define USB_EP_DOEPINT0_XferCompl_Pos \ - (0UL) /*!< USB0_EP0 DOEPINT0: XferCompl (Bit 0) */ -#define USB_EP_DOEPINT0_XferCompl_Msk \ - (0x1UL) /*!< USB0_EP0 DOEPINT0: XferCompl (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPINT0_EPDisbld_Pos \ - (1UL) /*!< USB0_EP0 DOEPINT0: EPDisbld (Bit 1) */ -#define USB_EP_DOEPINT0_EPDisbld_Msk \ - (0x2UL) /*!< USB0_EP0 DOEPINT0: EPDisbld (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPINT0_AHBErr_Pos \ - (2UL) /*!< USB0_EP0 DOEPINT0: AHBErr (Bit 2) */ -#define USB_EP_DOEPINT0_AHBErr_Msk \ - (0x4UL) /*!< USB0_EP0 DOEPINT0: AHBErr (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPINT0_SetUp_Pos \ - (3UL) /*!< USB0_EP0 DOEPINT0: SetUp (Bit 3) */ -#define USB_EP_DOEPINT0_SetUp_Msk \ - (0x8UL) /*!< USB0_EP0 DOEPINT0: SetUp (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPINT0_OUTTknEPdis_Pos \ - (4UL) /*!< USB0_EP0 DOEPINT0: OUTTknEPdis (Bit 4) */ -#define USB_EP_DOEPINT0_OUTTknEPdis_Msk \ - (0x10UL) /*!< USB0_EP0 DOEPINT0: OUTTknEPdis (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPINT0_StsPhseRcvd_Pos \ - (5UL) /*!< USB0_EP0 DOEPINT0: StsPhseRcvd (Bit 5) */ -#define USB_EP_DOEPINT0_StsPhseRcvd_Msk \ - (0x20UL) /*!< USB0_EP0 DOEPINT0: StsPhseRcvd (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPINT0_Back2BackSETup_Pos \ - (6UL) /*!< USB0_EP0 DOEPINT0: Back2BackSETup (Bit 6) */ -#define USB_EP_DOEPINT0_Back2BackSETup_Msk \ - (0x40UL) /*!< USB0_EP0 DOEPINT0: Back2BackSETup (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPINT0_BNAIntr_Pos \ - (9UL) /*!< USB0_EP0 DOEPINT0: BNAIntr (Bit 9) */ -#define USB_EP_DOEPINT0_BNAIntr_Msk \ - (0x200UL) /*!< USB0_EP0 DOEPINT0: BNAIntr (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPINT0_PktDrpSts_Pos \ - (11UL) /*!< USB0_EP0 DOEPINT0: PktDrpSts (Bit 11) */ -#define USB_EP_DOEPINT0_PktDrpSts_Msk \ - (0x800UL) /*!< USB0_EP0 DOEPINT0: PktDrpSts (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPINT0_BbleErrIntrpt_Pos \ - (12UL) /*!< USB0_EP0 DOEPINT0: BbleErrIntrpt (Bit 12) */ -#define USB_EP_DOEPINT0_BbleErrIntrpt_Msk \ - (0x1000UL) /*!< USB0_EP0 DOEPINT0: BbleErrIntrpt (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPINT0_NAKIntrpt_Pos \ - (13UL) /*!< USB0_EP0 DOEPINT0: NAKIntrpt (Bit 13) */ -#define USB_EP_DOEPINT0_NAKIntrpt_Msk \ - (0x2000UL) /*!< USB0_EP0 DOEPINT0: NAKIntrpt (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPINT0_NYETIntrpt_Pos \ - (14UL) /*!< USB0_EP0 DOEPINT0: NYETIntrpt (Bit 14) */ -#define USB_EP_DOEPINT0_NYETIntrpt_Msk \ - (0x4000UL) /*!< USB0_EP0 DOEPINT0: NYETIntrpt (Bitfield-Mask: 0x01) */ - -/* ----------------------------- USB_EP_DOEPTSIZ0 ----------------------------- */ -#define USB_EP_DOEPTSIZ0_XferSize_Pos \ - (0UL) /*!< USB0_EP0 DOEPTSIZ0: XferSize (Bit 0) */ -#define USB_EP_DOEPTSIZ0_XferSize_Msk \ - (0x7fUL) /*!< USB0_EP0 DOEPTSIZ0: XferSize (Bitfield-Mask: 0x7f) */ -#define USB_EP_DOEPTSIZ0_PktCnt_Pos \ - (19UL) /*!< USB0_EP0 DOEPTSIZ0: PktCnt (Bit 19) */ -#define USB_EP_DOEPTSIZ0_PktCnt_Msk \ - (0x180000UL) /*!< USB0_EP0 DOEPTSIZ0: PktCnt (Bitfield-Mask: 0x03) */ -#define USB_EP_DOEPTSIZ0_SUPCnt_Pos \ - (29UL) /*!< USB0_EP0 DOEPTSIZ0: SUPCnt (Bit 29) */ -#define USB_EP_DOEPTSIZ0_SUPCnt_Msk \ - (0x60000000UL) /*!< USB0_EP0 DOEPTSIZ0: SUPCnt (Bitfield-Mask: 0x03) */ - -/* ------------------------------ USB_EP_DOEPDMA0 ----------------------------- */ -#define USB_EP_DOEPDMA0_DMAAddr_Pos \ - (0UL) /*!< USB0_EP0 DOEPDMA0: DMAAddr (Bit 0) */ -#define USB_EP_DOEPDMA0_DMAAddr_Msk \ - (0xffffffffUL) /*!< USB0_EP0 DOEPDMA0: DMAAddr (Bitfield-Mask: 0xffffffff) */ - -/* ----------------------------- USB_EP_DOEPDMAB0 ----------------------------- */ -#define USB_EP_DOEPDMAB0_DMABufferAddr_Pos \ - (0UL) /*!< USB0_EP0 DOEPDMAB0: DMABufferAddr (Bit 0) */ -#define USB_EP_DOEPDMAB0_DMABufferAddr_Msk \ - (0xffffffffUL) /*!< USB0_EP0 DOEPDMAB0: DMABufferAddr (Bitfield-Mask: 0xffffffff) */ - -/* ================================================================================ */ -/* ================ Group 'USB_EP' Position & Mask ================ */ -/* ================================================================================ */ - -/* --------------------------- USB_EP_DIEPCTL_ISOCONT --------------------------- */ -#define USB_EP_DIEPCTL_ISOCONT_MPS_Pos \ - (0UL) /*!< USB_EP DIEPCTL_ISOCONT: MPS (Bit 0) */ -#define USB_EP_DIEPCTL_ISOCONT_MPS_Msk \ - (0x7ffUL) /*!< USB_EP DIEPCTL_ISOCONT: MPS (Bitfield-Mask: 0x7ff) */ -#define USB_EP_DIEPCTL_ISOCONT_USBActEP_Pos \ - (15UL) /*!< USB_EP DIEPCTL_ISOCONT: USBActEP (Bit 15) */ -#define USB_EP_DIEPCTL_ISOCONT_USBActEP_Msk \ - (0x8000UL) /*!< USB_EP DIEPCTL_ISOCONT: USBActEP (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL_ISOCONT_EO_FrNum_Pos \ - (16UL) /*!< USB_EP DIEPCTL_ISOCONT: EO_FrNum (Bit 16) */ -#define USB_EP_DIEPCTL_ISOCONT_EO_FrNum_Msk \ - (0x10000UL) /*!< USB_EP DIEPCTL_ISOCONT: EO_FrNum (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL_ISOCONT_NAKSts_Pos \ - (17UL) /*!< USB_EP DIEPCTL_ISOCONT: NAKSts (Bit 17) */ -#define USB_EP_DIEPCTL_ISOCONT_NAKSts_Msk \ - (0x20000UL) /*!< USB_EP DIEPCTL_ISOCONT: NAKSts (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL_ISOCONT_EPType_Pos \ - (18UL) /*!< USB_EP DIEPCTL_ISOCONT: EPType (Bit 18) */ -#define USB_EP_DIEPCTL_ISOCONT_EPType_Msk \ - (0xc0000UL) /*!< USB_EP DIEPCTL_ISOCONT: EPType (Bitfield-Mask: 0x03) */ -#define USB_EP_DIEPCTL_ISOCONT_Snp_Pos \ - (20UL) /*!< USB_EP DIEPCTL_ISOCONT: Snp (Bit 20) */ -#define USB_EP_DIEPCTL_ISOCONT_Snp_Msk \ - (0x100000UL) /*!< USB_EP DIEPCTL_ISOCONT: Snp (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL_ISOCONT_Stall_Pos \ - (21UL) /*!< USB_EP DIEPCTL_ISOCONT: Stall (Bit 21) */ -#define USB_EP_DIEPCTL_ISOCONT_Stall_Msk \ - (0x200000UL) /*!< USB_EP DIEPCTL_ISOCONT: Stall (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL_ISOCONT_TxFNum_Pos \ - (22UL) /*!< USB_EP DIEPCTL_ISOCONT: TxFNum (Bit 22) */ -#define USB_EP_DIEPCTL_ISOCONT_TxFNum_Msk \ - (0x3c00000UL) /*!< USB_EP DIEPCTL_ISOCONT: TxFNum (Bitfield-Mask: 0x0f) */ -#define USB_EP_DIEPCTL_ISOCONT_CNAK_Pos \ - (26UL) /*!< USB_EP DIEPCTL_ISOCONT: CNAK (Bit 26) */ -#define USB_EP_DIEPCTL_ISOCONT_CNAK_Msk \ - (0x4000000UL) /*!< USB_EP DIEPCTL_ISOCONT: CNAK (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL_ISOCONT_SNAK_Pos \ - (27UL) /*!< USB_EP DIEPCTL_ISOCONT: SNAK (Bit 27) */ -#define USB_EP_DIEPCTL_ISOCONT_SNAK_Msk \ - (0x8000000UL) /*!< USB_EP DIEPCTL_ISOCONT: SNAK (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL_ISOCONT_SetEvenFr_Pos \ - (28UL) /*!< USB_EP DIEPCTL_ISOCONT: SetEvenFr (Bit 28) */ -#define USB_EP_DIEPCTL_ISOCONT_SetEvenFr_Msk \ - (0x10000000UL) /*!< USB_EP DIEPCTL_ISOCONT: SetEvenFr (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL_ISOCONT_SetOddFr_Pos \ - (29UL) /*!< USB_EP DIEPCTL_ISOCONT: SetOddFr (Bit 29) */ -#define USB_EP_DIEPCTL_ISOCONT_SetOddFr_Msk \ - (0x20000000UL) /*!< USB_EP DIEPCTL_ISOCONT: SetOddFr (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL_ISOCONT_EPDis_Pos \ - (30UL) /*!< USB_EP DIEPCTL_ISOCONT: EPDis (Bit 30) */ -#define USB_EP_DIEPCTL_ISOCONT_EPDis_Msk \ - (0x40000000UL) /*!< USB_EP DIEPCTL_ISOCONT: EPDis (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL_ISOCONT_EPEna_Pos \ - (31UL) /*!< USB_EP DIEPCTL_ISOCONT: EPEna (Bit 31) */ -#define USB_EP_DIEPCTL_ISOCONT_EPEna_Msk \ - (0x80000000UL) /*!< USB_EP DIEPCTL_ISOCONT: EPEna (Bitfield-Mask: 0x01) */ - -/* --------------------------- USB_EP_DIEPCTL_INTBULK --------------------------- */ -#define USB_EP_DIEPCTL_INTBULK_MPS_Pos \ - (0UL) /*!< USB_EP DIEPCTL_INTBULK: MPS (Bit 0) */ -#define USB_EP_DIEPCTL_INTBULK_MPS_Msk \ - (0x7ffUL) /*!< USB_EP DIEPCTL_INTBULK: MPS (Bitfield-Mask: 0x7ff) */ -#define USB_EP_DIEPCTL_INTBULK_USBActEP_Pos \ - (15UL) /*!< USB_EP DIEPCTL_INTBULK: USBActEP (Bit 15) */ -#define USB_EP_DIEPCTL_INTBULK_USBActEP_Msk \ - (0x8000UL) /*!< USB_EP DIEPCTL_INTBULK: USBActEP (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL_INTBULK_DPID_Pos \ - (16UL) /*!< USB_EP DIEPCTL_INTBULK: DPID (Bit 16) */ -#define USB_EP_DIEPCTL_INTBULK_DPID_Msk \ - (0x10000UL) /*!< USB_EP DIEPCTL_INTBULK: DPID (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL_INTBULK_NAKSts_Pos \ - (17UL) /*!< USB_EP DIEPCTL_INTBULK: NAKSts (Bit 17) */ -#define USB_EP_DIEPCTL_INTBULK_NAKSts_Msk \ - (0x20000UL) /*!< USB_EP DIEPCTL_INTBULK: NAKSts (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL_INTBULK_EPType_Pos \ - (18UL) /*!< USB_EP DIEPCTL_INTBULK: EPType (Bit 18) */ -#define USB_EP_DIEPCTL_INTBULK_EPType_Msk \ - (0xc0000UL) /*!< USB_EP DIEPCTL_INTBULK: EPType (Bitfield-Mask: 0x03) */ -#define USB_EP_DIEPCTL_INTBULK_Snp_Pos \ - (20UL) /*!< USB_EP DIEPCTL_INTBULK: Snp (Bit 20) */ -#define USB_EP_DIEPCTL_INTBULK_Snp_Msk \ - (0x100000UL) /*!< USB_EP DIEPCTL_INTBULK: Snp (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL_INTBULK_Stall_Pos \ - (21UL) /*!< USB_EP DIEPCTL_INTBULK: Stall (Bit 21) */ -#define USB_EP_DIEPCTL_INTBULK_Stall_Msk \ - (0x200000UL) /*!< USB_EP DIEPCTL_INTBULK: Stall (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL_INTBULK_TxFNum_Pos \ - (22UL) /*!< USB_EP DIEPCTL_INTBULK: TxFNum (Bit 22) */ -#define USB_EP_DIEPCTL_INTBULK_TxFNum_Msk \ - (0x3c00000UL) /*!< USB_EP DIEPCTL_INTBULK: TxFNum (Bitfield-Mask: 0x0f) */ -#define USB_EP_DIEPCTL_INTBULK_CNAK_Pos \ - (26UL) /*!< USB_EP DIEPCTL_INTBULK: CNAK (Bit 26) */ -#define USB_EP_DIEPCTL_INTBULK_CNAK_Msk \ - (0x4000000UL) /*!< USB_EP DIEPCTL_INTBULK: CNAK (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL_INTBULK_SNAK_Pos \ - (27UL) /*!< USB_EP DIEPCTL_INTBULK: SNAK (Bit 27) */ -#define USB_EP_DIEPCTL_INTBULK_SNAK_Msk \ - (0x8000000UL) /*!< USB_EP DIEPCTL_INTBULK: SNAK (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL_INTBULK_SetD0PID_Pos \ - (28UL) /*!< USB_EP DIEPCTL_INTBULK: SetD0PID (Bit 28) */ -#define USB_EP_DIEPCTL_INTBULK_SetD0PID_Msk \ - (0x10000000UL) /*!< USB_EP DIEPCTL_INTBULK: SetD0PID (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL_INTBULK_SetD1PID_Pos \ - (29UL) /*!< USB_EP DIEPCTL_INTBULK: SetD1PID (Bit 29) */ -#define USB_EP_DIEPCTL_INTBULK_SetD1PID_Msk \ - (0x20000000UL) /*!< USB_EP DIEPCTL_INTBULK: SetD1PID (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL_INTBULK_EPDis_Pos \ - (30UL) /*!< USB_EP DIEPCTL_INTBULK: EPDis (Bit 30) */ -#define USB_EP_DIEPCTL_INTBULK_EPDis_Msk \ - (0x40000000UL) /*!< USB_EP DIEPCTL_INTBULK: EPDis (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPCTL_INTBULK_EPEna_Pos \ - (31UL) /*!< USB_EP DIEPCTL_INTBULK: EPEna (Bit 31) */ -#define USB_EP_DIEPCTL_INTBULK_EPEna_Msk \ - (0x80000000UL) /*!< USB_EP DIEPCTL_INTBULK: EPEna (Bitfield-Mask: 0x01) */ - -/* ------------------------------- USB_EP_DIEPINT ------------------------------- */ -#define USB_EP_DIEPINT_XferCompl_Pos \ - (0UL) /*!< USB_EP DIEPINT: XferCompl (Bit 0) */ -#define USB_EP_DIEPINT_XferCompl_Msk \ - (0x1UL) /*!< USB_EP DIEPINT: XferCompl (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPINT_EPDisbld_Pos \ - (1UL) /*!< USB_EP DIEPINT: EPDisbld (Bit 1) */ -#define USB_EP_DIEPINT_EPDisbld_Msk \ - (0x2UL) /*!< USB_EP DIEPINT: EPDisbld (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPINT_AHBErr_Pos \ - (2UL) /*!< USB_EP DIEPINT: AHBErr (Bit 2) */ -#define USB_EP_DIEPINT_AHBErr_Msk \ - (0x4UL) /*!< USB_EP DIEPINT: AHBErr (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPINT_TimeOUT_Pos \ - (3UL) /*!< USB_EP DIEPINT: TimeOUT (Bit 3) */ -#define USB_EP_DIEPINT_TimeOUT_Msk \ - (0x8UL) /*!< USB_EP DIEPINT: TimeOUT (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPINT_INTknTXFEmp_Pos \ - (4UL) /*!< USB_EP DIEPINT: INTknTXFEmp (Bit 4) */ -#define USB_EP_DIEPINT_INTknTXFEmp_Msk \ - (0x10UL) /*!< USB_EP DIEPINT: INTknTXFEmp (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPINT_INEPNakEff_Pos \ - (6UL) /*!< USB_EP DIEPINT: INEPNakEff (Bit 6) */ -#define USB_EP_DIEPINT_INEPNakEff_Msk \ - (0x40UL) /*!< USB_EP DIEPINT: INEPNakEff (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPINT_TxFEmp_Pos \ - (7UL) /*!< USB_EP DIEPINT: TxFEmp (Bit 7) */ -#define USB_EP_DIEPINT_TxFEmp_Msk \ - (0x80UL) /*!< USB_EP DIEPINT: TxFEmp (Bitfield-Mask: 0x01) */ -#define USB_EP_DIEPINT_BNAIntr_Pos \ - (9UL) /*!< USB_EP DIEPINT: BNAIntr (Bit 9) */ -#define USB_EP_DIEPINT_BNAIntr_Msk \ - (0x200UL) /*!< USB_EP DIEPINT: BNAIntr (Bitfield-Mask: 0x01) */ - -/* ------------------------------- USB_EP_DIEPTSIZ ------------------------------ */ -#define USB_EP_DIEPTSIZ_XferSize_Pos \ - (0UL) /*!< USB_EP DIEPTSIZ: XferSize (Bit 0) */ -#define USB_EP_DIEPTSIZ_XferSize_Msk \ - (0x7ffffUL) /*!< USB_EP DIEPTSIZ: XferSize (Bitfield-Mask: 0x7ffff) */ -#define USB_EP_DIEPTSIZ_PktCnt_Pos \ - (19UL) /*!< USB_EP DIEPTSIZ: PktCnt (Bit 19) */ -#define USB_EP_DIEPTSIZ_PktCnt_Msk \ - (0x1ff80000UL) /*!< USB_EP DIEPTSIZ: PktCnt (Bitfield-Mask: 0x3ff) */ - -/* ------------------------------- USB_EP_DIEPDMA ------------------------------- */ -#define USB_EP_DIEPDMA_DMAAddr_Pos \ - (0UL) /*!< USB_EP DIEPDMA: DMAAddr (Bit 0) */ -#define USB_EP_DIEPDMA_DMAAddr_Msk \ - (0xffffffffUL) /*!< USB_EP DIEPDMA: DMAAddr (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------- USB_EP_DTXFSTS ------------------------------- */ -#define USB_EP_DTXFSTS_INEPTxFSpcAvail_Pos \ - (0UL) /*!< USB_EP DTXFSTS: INEPTxFSpcAvail (Bit 0) */ -#define USB_EP_DTXFSTS_INEPTxFSpcAvail_Msk \ - (0xffffUL) /*!< USB_EP DTXFSTS: INEPTxFSpcAvail (Bitfield-Mask: 0xffff) */ - -/* ------------------------------- USB_EP_DIEPDMAB ------------------------------ */ -#define USB_EP_DIEPDMAB_DMABufferAddr_Pos \ - (0UL) /*!< USB_EP DIEPDMAB: DMABufferAddr (Bit 0) */ -#define USB_EP_DIEPDMAB_DMABufferAddr_Msk \ - (0xffffffffUL) /*!< USB_EP DIEPDMAB: DMABufferAddr (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------- USB_EP_DOEPCTL_ISOCONT --------------------------- */ -#define USB_EP_DOEPCTL_ISOCONT_MPS_Pos \ - (0UL) /*!< USB_EP DOEPCTL_ISOCONT: MPS (Bit 0) */ -#define USB_EP_DOEPCTL_ISOCONT_MPS_Msk \ - (0x7ffUL) /*!< USB_EP DOEPCTL_ISOCONT: MPS (Bitfield-Mask: 0x7ff) */ -#define USB_EP_DOEPCTL_ISOCONT_USBActEP_Pos \ - (15UL) /*!< USB_EP DOEPCTL_ISOCONT: USBActEP (Bit 15) */ -#define USB_EP_DOEPCTL_ISOCONT_USBActEP_Msk \ - (0x8000UL) /*!< USB_EP DOEPCTL_ISOCONT: USBActEP (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL_ISOCONT_EO_FrNum_Pos \ - (16UL) /*!< USB_EP DOEPCTL_ISOCONT: EO_FrNum (Bit 16) */ -#define USB_EP_DOEPCTL_ISOCONT_EO_FrNum_Msk \ - (0x10000UL) /*!< USB_EP DOEPCTL_ISOCONT: EO_FrNum (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL_ISOCONT_NAKSts_Pos \ - (17UL) /*!< USB_EP DOEPCTL_ISOCONT: NAKSts (Bit 17) */ -#define USB_EP_DOEPCTL_ISOCONT_NAKSts_Msk \ - (0x20000UL) /*!< USB_EP DOEPCTL_ISOCONT: NAKSts (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL_ISOCONT_EPType_Pos \ - (18UL) /*!< USB_EP DOEPCTL_ISOCONT: EPType (Bit 18) */ -#define USB_EP_DOEPCTL_ISOCONT_EPType_Msk \ - (0xc0000UL) /*!< USB_EP DOEPCTL_ISOCONT: EPType (Bitfield-Mask: 0x03) */ -#define USB_EP_DOEPCTL_ISOCONT_Snp_Pos \ - (20UL) /*!< USB_EP DOEPCTL_ISOCONT: Snp (Bit 20) */ -#define USB_EP_DOEPCTL_ISOCONT_Snp_Msk \ - (0x100000UL) /*!< USB_EP DOEPCTL_ISOCONT: Snp (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL_ISOCONT_Stall_Pos \ - (21UL) /*!< USB_EP DOEPCTL_ISOCONT: Stall (Bit 21) */ -#define USB_EP_DOEPCTL_ISOCONT_Stall_Msk \ - (0x200000UL) /*!< USB_EP DOEPCTL_ISOCONT: Stall (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL_ISOCONT_TxFNum_Pos \ - (22UL) /*!< USB_EP DOEPCTL_ISOCONT: TxFNum (Bit 22) */ -#define USB_EP_DOEPCTL_ISOCONT_TxFNum_Msk \ - (0x3c00000UL) /*!< USB_EP DOEPCTL_ISOCONT: TxFNum (Bitfield-Mask: 0x0f) */ -#define USB_EP_DOEPCTL_ISOCONT_CNAK_Pos \ - (26UL) /*!< USB_EP DOEPCTL_ISOCONT: CNAK (Bit 26) */ -#define USB_EP_DOEPCTL_ISOCONT_CNAK_Msk \ - (0x4000000UL) /*!< USB_EP DOEPCTL_ISOCONT: CNAK (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL_ISOCONT_SNAK_Pos \ - (27UL) /*!< USB_EP DOEPCTL_ISOCONT: SNAK (Bit 27) */ -#define USB_EP_DOEPCTL_ISOCONT_SNAK_Msk \ - (0x8000000UL) /*!< USB_EP DOEPCTL_ISOCONT: SNAK (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL_ISOCONT_SetEvenFr_Pos \ - (28UL) /*!< USB_EP DOEPCTL_ISOCONT: SetEvenFr (Bit 28) */ -#define USB_EP_DOEPCTL_ISOCONT_SetEvenFr_Msk \ - (0x10000000UL) /*!< USB_EP DOEPCTL_ISOCONT: SetEvenFr (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL_ISOCONT_SetOddFr_Pos \ - (29UL) /*!< USB_EP DOEPCTL_ISOCONT: SetOddFr (Bit 29) */ -#define USB_EP_DOEPCTL_ISOCONT_SetOddFr_Msk \ - (0x20000000UL) /*!< USB_EP DOEPCTL_ISOCONT: SetOddFr (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL_ISOCONT_EPDis_Pos \ - (30UL) /*!< USB_EP DOEPCTL_ISOCONT: EPDis (Bit 30) */ -#define USB_EP_DOEPCTL_ISOCONT_EPDis_Msk \ - (0x40000000UL) /*!< USB_EP DOEPCTL_ISOCONT: EPDis (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL_ISOCONT_EPEna_Pos \ - (31UL) /*!< USB_EP DOEPCTL_ISOCONT: EPEna (Bit 31) */ -#define USB_EP_DOEPCTL_ISOCONT_EPEna_Msk \ - (0x80000000UL) /*!< USB_EP DOEPCTL_ISOCONT: EPEna (Bitfield-Mask: 0x01) */ - -/* --------------------------- USB_EP_DOEPCTL_INTBULK --------------------------- */ -#define USB_EP_DOEPCTL_INTBULK_MPS_Pos \ - (0UL) /*!< USB_EP DOEPCTL_INTBULK: MPS (Bit 0) */ -#define USB_EP_DOEPCTL_INTBULK_MPS_Msk \ - (0x7ffUL) /*!< USB_EP DOEPCTL_INTBULK: MPS (Bitfield-Mask: 0x7ff) */ -#define USB_EP_DOEPCTL_INTBULK_USBActEP_Pos \ - (15UL) /*!< USB_EP DOEPCTL_INTBULK: USBActEP (Bit 15) */ -#define USB_EP_DOEPCTL_INTBULK_USBActEP_Msk \ - (0x8000UL) /*!< USB_EP DOEPCTL_INTBULK: USBActEP (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL_INTBULK_DPID_Pos \ - (16UL) /*!< USB_EP DOEPCTL_INTBULK: DPID (Bit 16) */ -#define USB_EP_DOEPCTL_INTBULK_DPID_Msk \ - (0x10000UL) /*!< USB_EP DOEPCTL_INTBULK: DPID (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL_INTBULK_NAKSts_Pos \ - (17UL) /*!< USB_EP DOEPCTL_INTBULK: NAKSts (Bit 17) */ -#define USB_EP_DOEPCTL_INTBULK_NAKSts_Msk \ - (0x20000UL) /*!< USB_EP DOEPCTL_INTBULK: NAKSts (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL_INTBULK_EPType_Pos \ - (18UL) /*!< USB_EP DOEPCTL_INTBULK: EPType (Bit 18) */ -#define USB_EP_DOEPCTL_INTBULK_EPType_Msk \ - (0xc0000UL) /*!< USB_EP DOEPCTL_INTBULK: EPType (Bitfield-Mask: 0x03) */ -#define USB_EP_DOEPCTL_INTBULK_Snp_Pos \ - (20UL) /*!< USB_EP DOEPCTL_INTBULK: Snp (Bit 20) */ -#define USB_EP_DOEPCTL_INTBULK_Snp_Msk \ - (0x100000UL) /*!< USB_EP DOEPCTL_INTBULK: Snp (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL_INTBULK_Stall_Pos \ - (21UL) /*!< USB_EP DOEPCTL_INTBULK: Stall (Bit 21) */ -#define USB_EP_DOEPCTL_INTBULK_Stall_Msk \ - (0x200000UL) /*!< USB_EP DOEPCTL_INTBULK: Stall (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL_INTBULK_TxFNum_Pos \ - (22UL) /*!< USB_EP DOEPCTL_INTBULK: TxFNum (Bit 22) */ -#define USB_EP_DOEPCTL_INTBULK_TxFNum_Msk \ - (0x3c00000UL) /*!< USB_EP DOEPCTL_INTBULK: TxFNum (Bitfield-Mask: 0x0f) */ -#define USB_EP_DOEPCTL_INTBULK_CNAK_Pos \ - (26UL) /*!< USB_EP DOEPCTL_INTBULK: CNAK (Bit 26) */ -#define USB_EP_DOEPCTL_INTBULK_CNAK_Msk \ - (0x4000000UL) /*!< USB_EP DOEPCTL_INTBULK: CNAK (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL_INTBULK_SNAK_Pos \ - (27UL) /*!< USB_EP DOEPCTL_INTBULK: SNAK (Bit 27) */ -#define USB_EP_DOEPCTL_INTBULK_SNAK_Msk \ - (0x8000000UL) /*!< USB_EP DOEPCTL_INTBULK: SNAK (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL_INTBULK_SetD0PID_Pos \ - (28UL) /*!< USB_EP DOEPCTL_INTBULK: SetD0PID (Bit 28) */ -#define USB_EP_DOEPCTL_INTBULK_SetD0PID_Msk \ - (0x10000000UL) /*!< USB_EP DOEPCTL_INTBULK: SetD0PID (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL_INTBULK_SetD1PID_Pos \ - (29UL) /*!< USB_EP DOEPCTL_INTBULK: SetD1PID (Bit 29) */ -#define USB_EP_DOEPCTL_INTBULK_SetD1PID_Msk \ - (0x20000000UL) /*!< USB_EP DOEPCTL_INTBULK: SetD1PID (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL_INTBULK_EPDis_Pos \ - (30UL) /*!< USB_EP DOEPCTL_INTBULK: EPDis (Bit 30) */ -#define USB_EP_DOEPCTL_INTBULK_EPDis_Msk \ - (0x40000000UL) /*!< USB_EP DOEPCTL_INTBULK: EPDis (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPCTL_INTBULK_EPEna_Pos \ - (31UL) /*!< USB_EP DOEPCTL_INTBULK: EPEna (Bit 31) */ -#define USB_EP_DOEPCTL_INTBULK_EPEna_Msk \ - (0x80000000UL) /*!< USB_EP DOEPCTL_INTBULK: EPEna (Bitfield-Mask: 0x01) */ - -/* ------------------------------- USB_EP_DOEPINT ------------------------------- */ -#define USB_EP_DOEPINT_XferCompl_Pos \ - (0UL) /*!< USB_EP DOEPINT: XferCompl (Bit 0) */ -#define USB_EP_DOEPINT_XferCompl_Msk \ - (0x1UL) /*!< USB_EP DOEPINT: XferCompl (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPINT_EPDisbld_Pos \ - (1UL) /*!< USB_EP DOEPINT: EPDisbld (Bit 1) */ -#define USB_EP_DOEPINT_EPDisbld_Msk \ - (0x2UL) /*!< USB_EP DOEPINT: EPDisbld (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPINT_AHBErr_Pos \ - (2UL) /*!< USB_EP DOEPINT: AHBErr (Bit 2) */ -#define USB_EP_DOEPINT_AHBErr_Msk \ - (0x4UL) /*!< USB_EP DOEPINT: AHBErr (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPINT_SetUp_Pos \ - (3UL) /*!< USB_EP DOEPINT: SetUp (Bit 3) */ -#define USB_EP_DOEPINT_SetUp_Msk \ - (0x8UL) /*!< USB_EP DOEPINT: SetUp (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPINT_OUTTknEPdis_Pos \ - (4UL) /*!< USB_EP DOEPINT: OUTTknEPdis (Bit 4) */ -#define USB_EP_DOEPINT_OUTTknEPdis_Msk \ - (0x10UL) /*!< USB_EP DOEPINT: OUTTknEPdis (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPINT_StsPhseRcvd_Pos \ - (5UL) /*!< USB_EP DOEPINT: StsPhseRcvd (Bit 5) */ -#define USB_EP_DOEPINT_StsPhseRcvd_Msk \ - (0x20UL) /*!< USB_EP DOEPINT: StsPhseRcvd (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPINT_Back2BackSETup_Pos \ - (6UL) /*!< USB_EP DOEPINT: Back2BackSETup (Bit 6) */ -#define USB_EP_DOEPINT_Back2BackSETup_Msk \ - (0x40UL) /*!< USB_EP DOEPINT: Back2BackSETup (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPINT_BNAIntr_Pos \ - (9UL) /*!< USB_EP DOEPINT: BNAIntr (Bit 9) */ -#define USB_EP_DOEPINT_BNAIntr_Msk \ - (0x200UL) /*!< USB_EP DOEPINT: BNAIntr (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPINT_PktDrpSts_Pos \ - (11UL) /*!< USB_EP DOEPINT: PktDrpSts (Bit 11) */ -#define USB_EP_DOEPINT_PktDrpSts_Msk \ - (0x800UL) /*!< USB_EP DOEPINT: PktDrpSts (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPINT_BbleErrIntrpt_Pos \ - (12UL) /*!< USB_EP DOEPINT: BbleErrIntrpt (Bit 12) */ -#define USB_EP_DOEPINT_BbleErrIntrpt_Msk \ - (0x1000UL) /*!< USB_EP DOEPINT: BbleErrIntrpt (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPINT_NAKIntrpt_Pos \ - (13UL) /*!< USB_EP DOEPINT: NAKIntrpt (Bit 13) */ -#define USB_EP_DOEPINT_NAKIntrpt_Msk \ - (0x2000UL) /*!< USB_EP DOEPINT: NAKIntrpt (Bitfield-Mask: 0x01) */ -#define USB_EP_DOEPINT_NYETIntrpt_Pos \ - (14UL) /*!< USB_EP DOEPINT: NYETIntrpt (Bit 14) */ -#define USB_EP_DOEPINT_NYETIntrpt_Msk \ - (0x4000UL) /*!< USB_EP DOEPINT: NYETIntrpt (Bitfield-Mask: 0x01) */ - -/* ----------------------------- USB_EP_DOEPTSIZ_ISO ---------------------------- */ -#define USB_EP_DOEPTSIZ_ISO_XferSize_Pos \ - (0UL) /*!< USB_EP DOEPTSIZ_ISO: XferSize (Bit 0) */ -#define USB_EP_DOEPTSIZ_ISO_XferSize_Msk \ - (0x7ffffUL) /*!< USB_EP DOEPTSIZ_ISO: XferSize (Bitfield-Mask: 0x7ffff) */ -#define USB_EP_DOEPTSIZ_ISO_PktCnt_Pos \ - (19UL) /*!< USB_EP DOEPTSIZ_ISO: PktCnt (Bit 19) */ -#define USB_EP_DOEPTSIZ_ISO_PktCnt_Msk \ - (0x1ff80000UL) /*!< USB_EP DOEPTSIZ_ISO: PktCnt (Bitfield-Mask: 0x3ff) */ -#define USB_EP_DOEPTSIZ_ISO_RxDPID_Pos \ - (29UL) /*!< USB_EP DOEPTSIZ_ISO: RxDPID (Bit 29) */ -#define USB_EP_DOEPTSIZ_ISO_RxDPID_Msk \ - (0x60000000UL) /*!< USB_EP DOEPTSIZ_ISO: RxDPID (Bitfield-Mask: 0x03) */ - -/* --------------------------- USB_EP_DOEPTSIZ_CONTROL -------------------------- */ -#define USB_EP_DOEPTSIZ_CONTROL_XferSize_Pos \ - (0UL) /*!< USB_EP DOEPTSIZ_CONTROL: XferSize (Bit 0) */ -#define USB_EP_DOEPTSIZ_CONTROL_XferSize_Msk \ - (0x7ffffUL) /*!< USB_EP DOEPTSIZ_CONTROL: XferSize (Bitfield-Mask: 0x7ffff) */ -#define USB_EP_DOEPTSIZ_CONTROL_PktCnt_Pos \ - (19UL) /*!< USB_EP DOEPTSIZ_CONTROL: PktCnt (Bit 19) */ -#define USB_EP_DOEPTSIZ_CONTROL_PktCnt_Msk \ - (0x1ff80000UL) /*!< USB_EP DOEPTSIZ_CONTROL: PktCnt (Bitfield-Mask: 0x3ff) */ -#define USB_EP_DOEPTSIZ_CONTROL_SUPCnt_Pos \ - (29UL) /*!< USB_EP DOEPTSIZ_CONTROL: SUPCnt (Bit 29) */ -#define USB_EP_DOEPTSIZ_CONTROL_SUPCnt_Msk \ - (0x60000000UL) /*!< USB_EP DOEPTSIZ_CONTROL: SUPCnt (Bitfield-Mask: 0x03) */ - -/* ------------------------------- USB_EP_DOEPDMA ------------------------------- */ -#define USB_EP_DOEPDMA_DMAAddr_Pos \ - (0UL) /*!< USB_EP DOEPDMA: DMAAddr (Bit 0) */ -#define USB_EP_DOEPDMA_DMAAddr_Msk \ - (0xffffffffUL) /*!< USB_EP DOEPDMA: DMAAddr (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------- USB_EP_DOEPDMAB ------------------------------ */ -#define USB_EP_DOEPDMAB_DMABufferAddr_Pos \ - (0UL) /*!< USB_EP DOEPDMAB: DMABufferAddr (Bit 0) */ -#define USB_EP_DOEPDMAB_DMABufferAddr_Msk \ - (0xffffffffUL) /*!< USB_EP DOEPDMAB: DMABufferAddr (Bitfield-Mask: 0xffffffff) */ - -/* ================================================================================ */ -/* ================ Group 'USB_CH' Position & Mask ================ */ -/* ================================================================================ */ - -/* -------------------------------- USB_CH_HCCHAR ------------------------------- */ -#define USB_CH_HCCHAR_MPS_Pos \ - (0UL) /*!< USB_CH HCCHAR: MPS (Bit 0) */ -#define USB_CH_HCCHAR_MPS_Msk \ - (0x7ffUL) /*!< USB_CH HCCHAR: MPS (Bitfield-Mask: 0x7ff) */ -#define USB_CH_HCCHAR_EPNum_Pos \ - (11UL) /*!< USB_CH HCCHAR: EPNum (Bit 11) */ -#define USB_CH_HCCHAR_EPNum_Msk \ - (0x7800UL) /*!< USB_CH HCCHAR: EPNum (Bitfield-Mask: 0x0f) */ -#define USB_CH_HCCHAR_EPDir_Pos \ - (15UL) /*!< USB_CH HCCHAR: EPDir (Bit 15) */ -#define USB_CH_HCCHAR_EPDir_Msk \ - (0x8000UL) /*!< USB_CH HCCHAR: EPDir (Bitfield-Mask: 0x01) */ -#define USB_CH_HCCHAR_EPType_Pos \ - (18UL) /*!< USB_CH HCCHAR: EPType (Bit 18) */ -#define USB_CH_HCCHAR_EPType_Msk \ - (0xc0000UL) /*!< USB_CH HCCHAR: EPType (Bitfield-Mask: 0x03) */ -#define USB_CH_HCCHAR_MC_EC_Pos \ - (20UL) /*!< USB_CH HCCHAR: MC_EC (Bit 20) */ -#define USB_CH_HCCHAR_MC_EC_Msk \ - (0x300000UL) /*!< USB_CH HCCHAR: MC_EC (Bitfield-Mask: 0x03) */ -#define USB_CH_HCCHAR_DevAddr_Pos \ - (22UL) /*!< USB_CH HCCHAR: DevAddr (Bit 22) */ -#define USB_CH_HCCHAR_DevAddr_Msk \ - (0x1fc00000UL) /*!< USB_CH HCCHAR: DevAddr (Bitfield-Mask: 0x7f) */ -#define USB_CH_HCCHAR_OddFrm_Pos \ - (29UL) /*!< USB_CH HCCHAR: OddFrm (Bit 29) */ -#define USB_CH_HCCHAR_OddFrm_Msk \ - (0x20000000UL) /*!< USB_CH HCCHAR: OddFrm (Bitfield-Mask: 0x01) */ -#define USB_CH_HCCHAR_ChDis_Pos \ - (30UL) /*!< USB_CH HCCHAR: ChDis (Bit 30) */ -#define USB_CH_HCCHAR_ChDis_Msk \ - (0x40000000UL) /*!< USB_CH HCCHAR: ChDis (Bitfield-Mask: 0x01) */ -#define USB_CH_HCCHAR_ChEna_Pos \ - (31UL) /*!< USB_CH HCCHAR: ChEna (Bit 31) */ -#define USB_CH_HCCHAR_ChEna_Msk \ - (0x80000000UL) /*!< USB_CH HCCHAR: ChEna (Bitfield-Mask: 0x01) */ - -/* -------------------------------- USB_CH_HCINT -------------------------------- */ -#define USB_CH_HCINT_XferCompl_Pos \ - (0UL) /*!< USB_CH HCINT: XferCompl (Bit 0) */ -#define USB_CH_HCINT_XferCompl_Msk \ - (0x1UL) /*!< USB_CH HCINT: XferCompl (Bitfield-Mask: 0x01) */ -#define USB_CH_HCINT_ChHltd_Pos \ - (1UL) /*!< USB_CH HCINT: ChHltd (Bit 1) */ -#define USB_CH_HCINT_ChHltd_Msk \ - (0x2UL) /*!< USB_CH HCINT: ChHltd (Bitfield-Mask: 0x01) */ -#define USB_CH_HCINT_AHBErr_Pos \ - (2UL) /*!< USB_CH HCINT: AHBErr (Bit 2) */ -#define USB_CH_HCINT_AHBErr_Msk \ - (0x4UL) /*!< USB_CH HCINT: AHBErr (Bitfield-Mask: 0x01) */ -#define USB_CH_HCINT_STALL_Pos \ - (3UL) /*!< USB_CH HCINT: STALL (Bit 3) */ -#define USB_CH_HCINT_STALL_Msk \ - (0x8UL) /*!< USB_CH HCINT: STALL (Bitfield-Mask: 0x01) */ -#define USB_CH_HCINT_NAK_Pos \ - (4UL) /*!< USB_CH HCINT: NAK (Bit 4) */ -#define USB_CH_HCINT_NAK_Msk \ - (0x10UL) /*!< USB_CH HCINT: NAK (Bitfield-Mask: 0x01) */ -#define USB_CH_HCINT_ACK_Pos \ - (5UL) /*!< USB_CH HCINT: ACK (Bit 5) */ -#define USB_CH_HCINT_ACK_Msk \ - (0x20UL) /*!< USB_CH HCINT: ACK (Bitfield-Mask: 0x01) */ -#define USB_CH_HCINT_NYET_Pos \ - (6UL) /*!< USB_CH HCINT: NYET (Bit 6) */ -#define USB_CH_HCINT_NYET_Msk \ - (0x40UL) /*!< USB_CH HCINT: NYET (Bitfield-Mask: 0x01) */ -#define USB_CH_HCINT_XactErr_Pos \ - (7UL) /*!< USB_CH HCINT: XactErr (Bit 7) */ -#define USB_CH_HCINT_XactErr_Msk \ - (0x80UL) /*!< USB_CH HCINT: XactErr (Bitfield-Mask: 0x01) */ -#define USB_CH_HCINT_BblErr_Pos \ - (8UL) /*!< USB_CH HCINT: BblErr (Bit 8) */ -#define USB_CH_HCINT_BblErr_Msk \ - (0x100UL) /*!< USB_CH HCINT: BblErr (Bitfield-Mask: 0x01) */ -#define USB_CH_HCINT_FrmOvrun_Pos \ - (9UL) /*!< USB_CH HCINT: FrmOvrun (Bit 9) */ -#define USB_CH_HCINT_FrmOvrun_Msk \ - (0x200UL) /*!< USB_CH HCINT: FrmOvrun (Bitfield-Mask: 0x01) */ -#define USB_CH_HCINT_DataTglErr_Pos \ - (10UL) /*!< USB_CH HCINT: DataTglErr (Bit 10) */ -#define USB_CH_HCINT_DataTglErr_Msk \ - (0x400UL) /*!< USB_CH HCINT: DataTglErr (Bitfield-Mask: 0x01) */ -#define USB_CH_HCINT_BNAIntr_Pos \ - (11UL) /*!< USB_CH HCINT: BNAIntr (Bit 11) */ -#define USB_CH_HCINT_BNAIntr_Msk \ - (0x800UL) /*!< USB_CH HCINT: BNAIntr (Bitfield-Mask: 0x01) */ -#define USB_CH_HCINT_XCS_XACT_ERR_Pos \ - (12UL) /*!< USB_CH HCINT: XCS_XACT_ERR (Bit 12) */ -#define USB_CH_HCINT_XCS_XACT_ERR_Msk \ - (0x1000UL) /*!< USB_CH HCINT: XCS_XACT_ERR (Bitfield-Mask: 0x01) */ -#define USB_CH_HCINT_DESC_LST_ROLLIntr_Pos \ - (13UL) /*!< USB_CH HCINT: DESC_LST_ROLLIntr (Bit 13) */ -#define USB_CH_HCINT_DESC_LST_ROLLIntr_Msk \ - (0x2000UL) /*!< USB_CH HCINT: DESC_LST_ROLLIntr (Bitfield-Mask: 0x01) */ - -/* ------------------------------- USB_CH_HCINTMSK ------------------------------ */ -#define USB_CH_HCINTMSK_XferComplMsk_Pos \ - (0UL) /*!< USB_CH HCINTMSK: XferComplMsk (Bit 0) */ -#define USB_CH_HCINTMSK_XferComplMsk_Msk \ - (0x1UL) /*!< USB_CH HCINTMSK: XferComplMsk (Bitfield-Mask: 0x01) */ -#define USB_CH_HCINTMSK_ChHltdMsk_Pos \ - (1UL) /*!< USB_CH HCINTMSK: ChHltdMsk (Bit 1) */ -#define USB_CH_HCINTMSK_ChHltdMsk_Msk \ - (0x2UL) /*!< USB_CH HCINTMSK: ChHltdMsk (Bitfield-Mask: 0x01) */ -#define USB_CH_HCINTMSK_AHBErrMsk_Pos \ - (2UL) /*!< USB_CH HCINTMSK: AHBErrMsk (Bit 2) */ -#define USB_CH_HCINTMSK_AHBErrMsk_Msk \ - (0x4UL) /*!< USB_CH HCINTMSK: AHBErrMsk (Bitfield-Mask: 0x01) */ -#define USB_CH_HCINTMSK_StallMsk_Pos \ - (3UL) /*!< USB_CH HCINTMSK: StallMsk (Bit 3) */ -#define USB_CH_HCINTMSK_StallMsk_Msk \ - (0x8UL) /*!< USB_CH HCINTMSK: StallMsk (Bitfield-Mask: 0x01) */ -#define USB_CH_HCINTMSK_NakMsk_Pos \ - (4UL) /*!< USB_CH HCINTMSK: NakMsk (Bit 4) */ -#define USB_CH_HCINTMSK_NakMsk_Msk \ - (0x10UL) /*!< USB_CH HCINTMSK: NakMsk (Bitfield-Mask: 0x01) */ -#define USB_CH_HCINTMSK_AckMsk_Pos \ - (5UL) /*!< USB_CH HCINTMSK: AckMsk (Bit 5) */ -#define USB_CH_HCINTMSK_AckMsk_Msk \ - (0x20UL) /*!< USB_CH HCINTMSK: AckMsk (Bitfield-Mask: 0x01) */ -#define USB_CH_HCINTMSK_NyetMsk_Pos \ - (6UL) /*!< USB_CH HCINTMSK: NyetMsk (Bit 6) */ -#define USB_CH_HCINTMSK_NyetMsk_Msk \ - (0x40UL) /*!< USB_CH HCINTMSK: NyetMsk (Bitfield-Mask: 0x01) */ -#define USB_CH_HCINTMSK_XactErrMsk_Pos \ - (7UL) /*!< USB_CH HCINTMSK: XactErrMsk (Bit 7) */ -#define USB_CH_HCINTMSK_XactErrMsk_Msk \ - (0x80UL) /*!< USB_CH HCINTMSK: XactErrMsk (Bitfield-Mask: 0x01) */ -#define USB_CH_HCINTMSK_BblErrMsk_Pos \ - (8UL) /*!< USB_CH HCINTMSK: BblErrMsk (Bit 8) */ -#define USB_CH_HCINTMSK_BblErrMsk_Msk \ - (0x100UL) /*!< USB_CH HCINTMSK: BblErrMsk (Bitfield-Mask: 0x01) */ -#define USB_CH_HCINTMSK_FrmOvrunMsk_Pos \ - (9UL) /*!< USB_CH HCINTMSK: FrmOvrunMsk (Bit 9) */ -#define USB_CH_HCINTMSK_FrmOvrunMsk_Msk \ - (0x200UL) /*!< USB_CH HCINTMSK: FrmOvrunMsk (Bitfield-Mask: 0x01) */ -#define USB_CH_HCINTMSK_DataTglErrMsk_Pos \ - (10UL) /*!< USB_CH HCINTMSK: DataTglErrMsk (Bit 10) */ -#define USB_CH_HCINTMSK_DataTglErrMsk_Msk \ - (0x400UL) /*!< USB_CH HCINTMSK: DataTglErrMsk (Bitfield-Mask: 0x01) */ -#define USB_CH_HCINTMSK_BNAIntrMsk_Pos \ - (11UL) /*!< USB_CH HCINTMSK: BNAIntrMsk (Bit 11) */ -#define USB_CH_HCINTMSK_BNAIntrMsk_Msk \ - (0x800UL) /*!< USB_CH HCINTMSK: BNAIntrMsk (Bitfield-Mask: 0x01) */ -#define USB_CH_HCINTMSK_DESC_LST_ROLLIntrMsk_Pos \ - (13UL) /*!< USB_CH HCINTMSK: DESC_LST_ROLLIntrMsk (Bit 13) */ -#define USB_CH_HCINTMSK_DESC_LST_ROLLIntrMsk_Msk \ - (0x2000UL) /*!< USB_CH HCINTMSK: DESC_LST_ROLLIntrMsk (Bitfield-Mask: 0x01) */ - -/* -------------------------- USB_CH_HCTSIZ_BUFFERMODE -------------------------- */ -#define USB_CH_HCTSIZ_BUFFERMODE_XferSize_Pos \ - (0UL) /*!< USB_CH HCTSIZ_BUFFERMODE: XferSize (Bit 0) */ -#define USB_CH_HCTSIZ_BUFFERMODE_XferSize_Msk \ - (0x7ffffUL) /*!< USB_CH HCTSIZ_BUFFERMODE: XferSize (Bitfield-Mask: 0x7ffff) */ -#define USB_CH_HCTSIZ_BUFFERMODE_PktCnt_Pos \ - (19UL) /*!< USB_CH HCTSIZ_BUFFERMODE: PktCnt (Bit 19) */ -#define USB_CH_HCTSIZ_BUFFERMODE_PktCnt_Msk \ - (0x1ff80000UL) /*!< USB_CH HCTSIZ_BUFFERMODE: PktCnt (Bitfield-Mask: 0x3ff) */ -#define USB_CH_HCTSIZ_BUFFERMODE_Pid_Pos \ - (29UL) /*!< USB_CH HCTSIZ_BUFFERMODE: Pid (Bit 29) */ -#define USB_CH_HCTSIZ_BUFFERMODE_Pid_Msk \ - (0x60000000UL) /*!< USB_CH HCTSIZ_BUFFERMODE: Pid (Bitfield-Mask: 0x03) */ - -/* -------------------------- USB_CH_HCTSIZ_SCATGATHER -------------------------- */ -#define USB_CH_HCTSIZ_SCATGATHER_SCHED_INFO_Pos \ - (0UL) /*!< USB_CH HCTSIZ_SCATGATHER: SCHED_INFO (Bit 0) */ -#define USB_CH_HCTSIZ_SCATGATHER_SCHED_INFO_Msk \ - (0xffUL) /*!< USB_CH HCTSIZ_SCATGATHER: SCHED_INFO (Bitfield-Mask: 0xff) */ -#define USB_CH_HCTSIZ_SCATGATHER_NTD_Pos \ - (8UL) /*!< USB_CH HCTSIZ_SCATGATHER: NTD (Bit 8) */ -#define USB_CH_HCTSIZ_SCATGATHER_NTD_Msk \ - (0xff00UL) /*!< USB_CH HCTSIZ_SCATGATHER: NTD (Bitfield-Mask: 0xff) */ -#define USB_CH_HCTSIZ_SCATGATHER_Pid_Pos \ - (29UL) /*!< USB_CH HCTSIZ_SCATGATHER: Pid (Bit 29) */ -#define USB_CH_HCTSIZ_SCATGATHER_Pid_Msk \ - (0x60000000UL) /*!< USB_CH HCTSIZ_SCATGATHER: Pid (Bitfield-Mask: 0x03) */ - -/* --------------------------- USB_CH_HCDMA_BUFFERMODE -------------------------- */ -#define USB_CH_HCDMA_BUFFERMODE_DMAAddr_Pos \ - (0UL) /*!< USB_CH HCDMA_BUFFERMODE: DMAAddr (Bit 0) */ -#define USB_CH_HCDMA_BUFFERMODE_DMAAddr_Msk \ - (0xffffffffUL) /*!< USB_CH HCDMA_BUFFERMODE: DMAAddr (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------- USB_CH_HCDMA_SCATGATHER -------------------------- */ -#define USB_CH_HCDMA_SCATGATHER_CTD_Pos \ - (3UL) /*!< USB_CH HCDMA_SCATGATHER: CTD (Bit 3) */ -#define USB_CH_HCDMA_SCATGATHER_CTD_Msk \ - (0x1f8UL) /*!< USB_CH HCDMA_SCATGATHER: CTD (Bitfield-Mask: 0x3f) */ -#define USB_CH_HCDMA_SCATGATHER_DMAAddr_Pos \ - (9UL) /*!< USB_CH HCDMA_SCATGATHER: DMAAddr (Bit 9) */ -#define USB_CH_HCDMA_SCATGATHER_DMAAddr_Msk \ - (0xfffffe00UL) /*!< USB_CH HCDMA_SCATGATHER: DMAAddr (Bitfield-Mask: 0x7fffff) */ - -/* -------------------------------- USB_CH_HCDMAB ------------------------------- */ -#define USB_CH_HCDMAB_Buffer_Address_Pos \ - (0UL) /*!< USB_CH HCDMAB: Buffer_Address (Bit 0) */ -#define USB_CH_HCDMAB_Buffer_Address_Msk \ - (0xffffffffUL) /*!< USB_CH HCDMAB: Buffer_Address (Bitfield-Mask: 0xffffffff) */ - -/* ================================================================================ */ -/* ================ Group 'USIC' Position & Mask ================ */ -/* ================================================================================ */ - -/* ----------------------------------- USIC_ID ---------------------------------- */ -#define USIC_ID_MOD_REV_Pos \ - (0UL) /*!< USIC ID: MOD_REV (Bit 0) */ -#define USIC_ID_MOD_REV_Msk \ - (0xffUL) /*!< USIC ID: MOD_REV (Bitfield-Mask: 0xff) */ -#define USIC_ID_MOD_TYPE_Pos \ - (8UL) /*!< USIC ID: MOD_TYPE (Bit 8) */ -#define USIC_ID_MOD_TYPE_Msk \ - (0xff00UL) /*!< USIC ID: MOD_TYPE (Bitfield-Mask: 0xff) */ -#define USIC_ID_MOD_NUMBER_Pos \ - (16UL) /*!< USIC ID: MOD_NUMBER (Bit 16) */ -#define USIC_ID_MOD_NUMBER_Msk \ - (0xffff0000UL) /*!< USIC ID: MOD_NUMBER (Bitfield-Mask: 0xffff) */ - -/* ================================================================================ */ -/* ================ Group 'USIC_CH' Position & Mask ================ */ -/* ================================================================================ */ - -/* -------------------------------- USIC_CH_CCFG -------------------------------- */ -#define USIC_CH_CCFG_SSC_Pos \ - (0UL) /*!< USIC_CH CCFG: SSC (Bit 0) */ -#define USIC_CH_CCFG_SSC_Msk \ - (0x1UL) /*!< USIC_CH CCFG: SSC (Bitfield-Mask: 0x01) */ -#define USIC_CH_CCFG_ASC_Pos \ - (1UL) /*!< USIC_CH CCFG: ASC (Bit 1) */ -#define USIC_CH_CCFG_ASC_Msk \ - (0x2UL) /*!< USIC_CH CCFG: ASC (Bitfield-Mask: 0x01) */ -#define USIC_CH_CCFG_IIC_Pos \ - (2UL) /*!< USIC_CH CCFG: IIC (Bit 2) */ -#define USIC_CH_CCFG_IIC_Msk \ - (0x4UL) /*!< USIC_CH CCFG: IIC (Bitfield-Mask: 0x01) */ -#define USIC_CH_CCFG_IIS_Pos \ - (3UL) /*!< USIC_CH CCFG: IIS (Bit 3) */ -#define USIC_CH_CCFG_IIS_Msk \ - (0x8UL) /*!< USIC_CH CCFG: IIS (Bitfield-Mask: 0x01) */ -#define USIC_CH_CCFG_RB_Pos \ - (6UL) /*!< USIC_CH CCFG: RB (Bit 6) */ -#define USIC_CH_CCFG_RB_Msk \ - (0x40UL) /*!< USIC_CH CCFG: RB (Bitfield-Mask: 0x01) */ -#define USIC_CH_CCFG_TB_Pos \ - (7UL) /*!< USIC_CH CCFG: TB (Bit 7) */ -#define USIC_CH_CCFG_TB_Msk \ - (0x80UL) /*!< USIC_CH CCFG: TB (Bitfield-Mask: 0x01) */ - -/* -------------------------------- USIC_CH_KSCFG ------------------------------- */ -#define USIC_CH_KSCFG_MODEN_Pos \ - (0UL) /*!< USIC_CH KSCFG: MODEN (Bit 0) */ -#define USIC_CH_KSCFG_MODEN_Msk \ - (0x1UL) /*!< USIC_CH KSCFG: MODEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_KSCFG_BPMODEN_Pos \ - (1UL) /*!< USIC_CH KSCFG: BPMODEN (Bit 1) */ -#define USIC_CH_KSCFG_BPMODEN_Msk \ - (0x2UL) /*!< USIC_CH KSCFG: BPMODEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_KSCFG_NOMCFG_Pos \ - (4UL) /*!< USIC_CH KSCFG: NOMCFG (Bit 4) */ -#define USIC_CH_KSCFG_NOMCFG_Msk \ - (0x30UL) /*!< USIC_CH KSCFG: NOMCFG (Bitfield-Mask: 0x03) */ -#define USIC_CH_KSCFG_BPNOM_Pos \ - (7UL) /*!< USIC_CH KSCFG: BPNOM (Bit 7) */ -#define USIC_CH_KSCFG_BPNOM_Msk \ - (0x80UL) /*!< USIC_CH KSCFG: BPNOM (Bitfield-Mask: 0x01) */ -#define USIC_CH_KSCFG_SUMCFG_Pos \ - (8UL) /*!< USIC_CH KSCFG: SUMCFG (Bit 8) */ -#define USIC_CH_KSCFG_SUMCFG_Msk \ - (0x300UL) /*!< USIC_CH KSCFG: SUMCFG (Bitfield-Mask: 0x03) */ -#define USIC_CH_KSCFG_BPSUM_Pos \ - (11UL) /*!< USIC_CH KSCFG: BPSUM (Bit 11) */ -#define USIC_CH_KSCFG_BPSUM_Msk \ - (0x800UL) /*!< USIC_CH KSCFG: BPSUM (Bitfield-Mask: 0x01) */ - -/* --------------------------------- USIC_CH_FDR -------------------------------- */ -#define USIC_CH_FDR_STEP_Pos \ - (0UL) /*!< USIC_CH FDR: STEP (Bit 0) */ -#define USIC_CH_FDR_STEP_Msk \ - (0x3ffUL) /*!< USIC_CH FDR: STEP (Bitfield-Mask: 0x3ff) */ -#define USIC_CH_FDR_DM_Pos \ - (14UL) /*!< USIC_CH FDR: DM (Bit 14) */ -#define USIC_CH_FDR_DM_Msk \ - (0xc000UL) /*!< USIC_CH FDR: DM (Bitfield-Mask: 0x03) */ -#define USIC_CH_FDR_RESULT_Pos \ - (16UL) /*!< USIC_CH FDR: RESULT (Bit 16) */ -#define USIC_CH_FDR_RESULT_Msk \ - (0x3ff0000UL) /*!< USIC_CH FDR: RESULT (Bitfield-Mask: 0x3ff) */ - -/* --------------------------------- USIC_CH_BRG -------------------------------- */ -#define USIC_CH_BRG_CLKSEL_Pos \ - (0UL) /*!< USIC_CH BRG: CLKSEL (Bit 0) */ -#define USIC_CH_BRG_CLKSEL_Msk \ - (0x3UL) /*!< USIC_CH BRG: CLKSEL (Bitfield-Mask: 0x03) */ -#define USIC_CH_BRG_TMEN_Pos \ - (3UL) /*!< USIC_CH BRG: TMEN (Bit 3) */ -#define USIC_CH_BRG_TMEN_Msk \ - (0x8UL) /*!< USIC_CH BRG: TMEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_BRG_PPPEN_Pos \ - (4UL) /*!< USIC_CH BRG: PPPEN (Bit 4) */ -#define USIC_CH_BRG_PPPEN_Msk \ - (0x10UL) /*!< USIC_CH BRG: PPPEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_BRG_CTQSEL_Pos \ - (6UL) /*!< USIC_CH BRG: CTQSEL (Bit 6) */ -#define USIC_CH_BRG_CTQSEL_Msk \ - (0xc0UL) /*!< USIC_CH BRG: CTQSEL (Bitfield-Mask: 0x03) */ -#define USIC_CH_BRG_PCTQ_Pos \ - (8UL) /*!< USIC_CH BRG: PCTQ (Bit 8) */ -#define USIC_CH_BRG_PCTQ_Msk \ - (0x300UL) /*!< USIC_CH BRG: PCTQ (Bitfield-Mask: 0x03) */ -#define USIC_CH_BRG_DCTQ_Pos \ - (10UL) /*!< USIC_CH BRG: DCTQ (Bit 10) */ -#define USIC_CH_BRG_DCTQ_Msk \ - (0x7c00UL) /*!< USIC_CH BRG: DCTQ (Bitfield-Mask: 0x1f) */ -#define USIC_CH_BRG_PDIV_Pos \ - (16UL) /*!< USIC_CH BRG: PDIV (Bit 16) */ -#define USIC_CH_BRG_PDIV_Msk \ - (0x3ff0000UL) /*!< USIC_CH BRG: PDIV (Bitfield-Mask: 0x3ff) */ -#define USIC_CH_BRG_SCLKOSEL_Pos \ - (28UL) /*!< USIC_CH BRG: SCLKOSEL (Bit 28) */ -#define USIC_CH_BRG_SCLKOSEL_Msk \ - (0x10000000UL) /*!< USIC_CH BRG: SCLKOSEL (Bitfield-Mask: 0x01) */ -#define USIC_CH_BRG_MCLKCFG_Pos \ - (29UL) /*!< USIC_CH BRG: MCLKCFG (Bit 29) */ -#define USIC_CH_BRG_MCLKCFG_Msk \ - (0x20000000UL) /*!< USIC_CH BRG: MCLKCFG (Bitfield-Mask: 0x01) */ -#define USIC_CH_BRG_SCLKCFG_Pos \ - (30UL) /*!< USIC_CH BRG: SCLKCFG (Bit 30) */ -#define USIC_CH_BRG_SCLKCFG_Msk \ - (0xc0000000UL) /*!< USIC_CH BRG: SCLKCFG (Bitfield-Mask: 0x03) */ - -/* -------------------------------- USIC_CH_INPR -------------------------------- */ -#define USIC_CH_INPR_TSINP_Pos \ - (0UL) /*!< USIC_CH INPR: TSINP (Bit 0) */ -#define USIC_CH_INPR_TSINP_Msk \ - (0x7UL) /*!< USIC_CH INPR: TSINP (Bitfield-Mask: 0x07) */ -#define USIC_CH_INPR_TBINP_Pos \ - (4UL) /*!< USIC_CH INPR: TBINP (Bit 4) */ -#define USIC_CH_INPR_TBINP_Msk \ - (0x70UL) /*!< USIC_CH INPR: TBINP (Bitfield-Mask: 0x07) */ -#define USIC_CH_INPR_RINP_Pos \ - (8UL) /*!< USIC_CH INPR: RINP (Bit 8) */ -#define USIC_CH_INPR_RINP_Msk \ - (0x700UL) /*!< USIC_CH INPR: RINP (Bitfield-Mask: 0x07) */ -#define USIC_CH_INPR_AINP_Pos \ - (12UL) /*!< USIC_CH INPR: AINP (Bit 12) */ -#define USIC_CH_INPR_AINP_Msk \ - (0x7000UL) /*!< USIC_CH INPR: AINP (Bitfield-Mask: 0x07) */ -#define USIC_CH_INPR_PINP_Pos \ - (16UL) /*!< USIC_CH INPR: PINP (Bit 16) */ -#define USIC_CH_INPR_PINP_Msk \ - (0x70000UL) /*!< USIC_CH INPR: PINP (Bitfield-Mask: 0x07) */ - -/* -------------------------------- USIC_CH_DX0CR ------------------------------- */ -#define USIC_CH_DX0CR_DSEL_Pos \ - (0UL) /*!< USIC_CH DX0CR: DSEL (Bit 0) */ -#define USIC_CH_DX0CR_DSEL_Msk \ - (0x7UL) /*!< USIC_CH DX0CR: DSEL (Bitfield-Mask: 0x07) */ -#define USIC_CH_DX0CR_INSW_Pos \ - (4UL) /*!< USIC_CH DX0CR: INSW (Bit 4) */ -#define USIC_CH_DX0CR_INSW_Msk \ - (0x10UL) /*!< USIC_CH DX0CR: INSW (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX0CR_DFEN_Pos \ - (5UL) /*!< USIC_CH DX0CR: DFEN (Bit 5) */ -#define USIC_CH_DX0CR_DFEN_Msk \ - (0x20UL) /*!< USIC_CH DX0CR: DFEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX0CR_DSEN_Pos \ - (6UL) /*!< USIC_CH DX0CR: DSEN (Bit 6) */ -#define USIC_CH_DX0CR_DSEN_Msk \ - (0x40UL) /*!< USIC_CH DX0CR: DSEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX0CR_DPOL_Pos \ - (8UL) /*!< USIC_CH DX0CR: DPOL (Bit 8) */ -#define USIC_CH_DX0CR_DPOL_Msk \ - (0x100UL) /*!< USIC_CH DX0CR: DPOL (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX0CR_SFSEL_Pos \ - (9UL) /*!< USIC_CH DX0CR: SFSEL (Bit 9) */ -#define USIC_CH_DX0CR_SFSEL_Msk \ - (0x200UL) /*!< USIC_CH DX0CR: SFSEL (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX0CR_CM_Pos \ - (10UL) /*!< USIC_CH DX0CR: CM (Bit 10) */ -#define USIC_CH_DX0CR_CM_Msk \ - (0xc00UL) /*!< USIC_CH DX0CR: CM (Bitfield-Mask: 0x03) */ -#define USIC_CH_DX0CR_DXS_Pos \ - (15UL) /*!< USIC_CH DX0CR: DXS (Bit 15) */ -#define USIC_CH_DX0CR_DXS_Msk \ - (0x8000UL) /*!< USIC_CH DX0CR: DXS (Bitfield-Mask: 0x01) */ - -/* -------------------------------- USIC_CH_DX1CR ------------------------------- */ -#define USIC_CH_DX1CR_DSEL_Pos \ - (0UL) /*!< USIC_CH DX1CR: DSEL (Bit 0) */ -#define USIC_CH_DX1CR_DSEL_Msk \ - (0x7UL) /*!< USIC_CH DX1CR: DSEL (Bitfield-Mask: 0x07) */ -#define USIC_CH_DX1CR_DCEN_Pos \ - (3UL) /*!< USIC_CH DX1CR: DCEN (Bit 3) */ -#define USIC_CH_DX1CR_DCEN_Msk \ - (0x8UL) /*!< USIC_CH DX1CR: DCEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX1CR_INSW_Pos \ - (4UL) /*!< USIC_CH DX1CR: INSW (Bit 4) */ -#define USIC_CH_DX1CR_INSW_Msk \ - (0x10UL) /*!< USIC_CH DX1CR: INSW (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX1CR_DFEN_Pos \ - (5UL) /*!< USIC_CH DX1CR: DFEN (Bit 5) */ -#define USIC_CH_DX1CR_DFEN_Msk \ - (0x20UL) /*!< USIC_CH DX1CR: DFEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX1CR_DSEN_Pos \ - (6UL) /*!< USIC_CH DX1CR: DSEN (Bit 6) */ -#define USIC_CH_DX1CR_DSEN_Msk \ - (0x40UL) /*!< USIC_CH DX1CR: DSEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX1CR_DPOL_Pos \ - (8UL) /*!< USIC_CH DX1CR: DPOL (Bit 8) */ -#define USIC_CH_DX1CR_DPOL_Msk \ - (0x100UL) /*!< USIC_CH DX1CR: DPOL (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX1CR_SFSEL_Pos \ - (9UL) /*!< USIC_CH DX1CR: SFSEL (Bit 9) */ -#define USIC_CH_DX1CR_SFSEL_Msk \ - (0x200UL) /*!< USIC_CH DX1CR: SFSEL (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX1CR_CM_Pos \ - (10UL) /*!< USIC_CH DX1CR: CM (Bit 10) */ -#define USIC_CH_DX1CR_CM_Msk \ - (0xc00UL) /*!< USIC_CH DX1CR: CM (Bitfield-Mask: 0x03) */ -#define USIC_CH_DX1CR_DXS_Pos \ - (15UL) /*!< USIC_CH DX1CR: DXS (Bit 15) */ -#define USIC_CH_DX1CR_DXS_Msk \ - (0x8000UL) /*!< USIC_CH DX1CR: DXS (Bitfield-Mask: 0x01) */ - -/* -------------------------------- USIC_CH_DX2CR ------------------------------- */ -#define USIC_CH_DX2CR_DSEL_Pos \ - (0UL) /*!< USIC_CH DX2CR: DSEL (Bit 0) */ -#define USIC_CH_DX2CR_DSEL_Msk \ - (0x7UL) /*!< USIC_CH DX2CR: DSEL (Bitfield-Mask: 0x07) */ -#define USIC_CH_DX2CR_INSW_Pos \ - (4UL) /*!< USIC_CH DX2CR: INSW (Bit 4) */ -#define USIC_CH_DX2CR_INSW_Msk \ - (0x10UL) /*!< USIC_CH DX2CR: INSW (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX2CR_DFEN_Pos \ - (5UL) /*!< USIC_CH DX2CR: DFEN (Bit 5) */ -#define USIC_CH_DX2CR_DFEN_Msk \ - (0x20UL) /*!< USIC_CH DX2CR: DFEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX2CR_DSEN_Pos \ - (6UL) /*!< USIC_CH DX2CR: DSEN (Bit 6) */ -#define USIC_CH_DX2CR_DSEN_Msk \ - (0x40UL) /*!< USIC_CH DX2CR: DSEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX2CR_DPOL_Pos \ - (8UL) /*!< USIC_CH DX2CR: DPOL (Bit 8) */ -#define USIC_CH_DX2CR_DPOL_Msk \ - (0x100UL) /*!< USIC_CH DX2CR: DPOL (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX2CR_SFSEL_Pos \ - (9UL) /*!< USIC_CH DX2CR: SFSEL (Bit 9) */ -#define USIC_CH_DX2CR_SFSEL_Msk \ - (0x200UL) /*!< USIC_CH DX2CR: SFSEL (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX2CR_CM_Pos \ - (10UL) /*!< USIC_CH DX2CR: CM (Bit 10) */ -#define USIC_CH_DX2CR_CM_Msk \ - (0xc00UL) /*!< USIC_CH DX2CR: CM (Bitfield-Mask: 0x03) */ -#define USIC_CH_DX2CR_DXS_Pos \ - (15UL) /*!< USIC_CH DX2CR: DXS (Bit 15) */ -#define USIC_CH_DX2CR_DXS_Msk \ - (0x8000UL) /*!< USIC_CH DX2CR: DXS (Bitfield-Mask: 0x01) */ - -/* -------------------------------- USIC_CH_DX3CR ------------------------------- */ -#define USIC_CH_DX3CR_DSEL_Pos \ - (0UL) /*!< USIC_CH DX3CR: DSEL (Bit 0) */ -#define USIC_CH_DX3CR_DSEL_Msk \ - (0x7UL) /*!< USIC_CH DX3CR: DSEL (Bitfield-Mask: 0x07) */ -#define USIC_CH_DX3CR_INSW_Pos \ - (4UL) /*!< USIC_CH DX3CR: INSW (Bit 4) */ -#define USIC_CH_DX3CR_INSW_Msk \ - (0x10UL) /*!< USIC_CH DX3CR: INSW (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX3CR_DFEN_Pos \ - (5UL) /*!< USIC_CH DX3CR: DFEN (Bit 5) */ -#define USIC_CH_DX3CR_DFEN_Msk \ - (0x20UL) /*!< USIC_CH DX3CR: DFEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX3CR_DSEN_Pos \ - (6UL) /*!< USIC_CH DX3CR: DSEN (Bit 6) */ -#define USIC_CH_DX3CR_DSEN_Msk \ - (0x40UL) /*!< USIC_CH DX3CR: DSEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX3CR_DPOL_Pos \ - (8UL) /*!< USIC_CH DX3CR: DPOL (Bit 8) */ -#define USIC_CH_DX3CR_DPOL_Msk \ - (0x100UL) /*!< USIC_CH DX3CR: DPOL (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX3CR_SFSEL_Pos \ - (9UL) /*!< USIC_CH DX3CR: SFSEL (Bit 9) */ -#define USIC_CH_DX3CR_SFSEL_Msk \ - (0x200UL) /*!< USIC_CH DX3CR: SFSEL (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX3CR_CM_Pos \ - (10UL) /*!< USIC_CH DX3CR: CM (Bit 10) */ -#define USIC_CH_DX3CR_CM_Msk \ - (0xc00UL) /*!< USIC_CH DX3CR: CM (Bitfield-Mask: 0x03) */ -#define USIC_CH_DX3CR_DXS_Pos \ - (15UL) /*!< USIC_CH DX3CR: DXS (Bit 15) */ -#define USIC_CH_DX3CR_DXS_Msk \ - (0x8000UL) /*!< USIC_CH DX3CR: DXS (Bitfield-Mask: 0x01) */ - -/* -------------------------------- USIC_CH_DX4CR ------------------------------- */ -#define USIC_CH_DX4CR_DSEL_Pos \ - (0UL) /*!< USIC_CH DX4CR: DSEL (Bit 0) */ -#define USIC_CH_DX4CR_DSEL_Msk \ - (0x7UL) /*!< USIC_CH DX4CR: DSEL (Bitfield-Mask: 0x07) */ -#define USIC_CH_DX4CR_INSW_Pos \ - (4UL) /*!< USIC_CH DX4CR: INSW (Bit 4) */ -#define USIC_CH_DX4CR_INSW_Msk \ - (0x10UL) /*!< USIC_CH DX4CR: INSW (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX4CR_DFEN_Pos \ - (5UL) /*!< USIC_CH DX4CR: DFEN (Bit 5) */ -#define USIC_CH_DX4CR_DFEN_Msk \ - (0x20UL) /*!< USIC_CH DX4CR: DFEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX4CR_DSEN_Pos \ - (6UL) /*!< USIC_CH DX4CR: DSEN (Bit 6) */ -#define USIC_CH_DX4CR_DSEN_Msk \ - (0x40UL) /*!< USIC_CH DX4CR: DSEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX4CR_DPOL_Pos \ - (8UL) /*!< USIC_CH DX4CR: DPOL (Bit 8) */ -#define USIC_CH_DX4CR_DPOL_Msk \ - (0x100UL) /*!< USIC_CH DX4CR: DPOL (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX4CR_SFSEL_Pos \ - (9UL) /*!< USIC_CH DX4CR: SFSEL (Bit 9) */ -#define USIC_CH_DX4CR_SFSEL_Msk \ - (0x200UL) /*!< USIC_CH DX4CR: SFSEL (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX4CR_CM_Pos \ - (10UL) /*!< USIC_CH DX4CR: CM (Bit 10) */ -#define USIC_CH_DX4CR_CM_Msk \ - (0xc00UL) /*!< USIC_CH DX4CR: CM (Bitfield-Mask: 0x03) */ -#define USIC_CH_DX4CR_DXS_Pos \ - (15UL) /*!< USIC_CH DX4CR: DXS (Bit 15) */ -#define USIC_CH_DX4CR_DXS_Msk \ - (0x8000UL) /*!< USIC_CH DX4CR: DXS (Bitfield-Mask: 0x01) */ - -/* -------------------------------- USIC_CH_DX5CR ------------------------------- */ -#define USIC_CH_DX5CR_DSEL_Pos \ - (0UL) /*!< USIC_CH DX5CR: DSEL (Bit 0) */ -#define USIC_CH_DX5CR_DSEL_Msk \ - (0x7UL) /*!< USIC_CH DX5CR: DSEL (Bitfield-Mask: 0x07) */ -#define USIC_CH_DX5CR_INSW_Pos \ - (4UL) /*!< USIC_CH DX5CR: INSW (Bit 4) */ -#define USIC_CH_DX5CR_INSW_Msk \ - (0x10UL) /*!< USIC_CH DX5CR: INSW (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX5CR_DFEN_Pos \ - (5UL) /*!< USIC_CH DX5CR: DFEN (Bit 5) */ -#define USIC_CH_DX5CR_DFEN_Msk \ - (0x20UL) /*!< USIC_CH DX5CR: DFEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX5CR_DSEN_Pos \ - (6UL) /*!< USIC_CH DX5CR: DSEN (Bit 6) */ -#define USIC_CH_DX5CR_DSEN_Msk \ - (0x40UL) /*!< USIC_CH DX5CR: DSEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX5CR_DPOL_Pos \ - (8UL) /*!< USIC_CH DX5CR: DPOL (Bit 8) */ -#define USIC_CH_DX5CR_DPOL_Msk \ - (0x100UL) /*!< USIC_CH DX5CR: DPOL (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX5CR_SFSEL_Pos \ - (9UL) /*!< USIC_CH DX5CR: SFSEL (Bit 9) */ -#define USIC_CH_DX5CR_SFSEL_Msk \ - (0x200UL) /*!< USIC_CH DX5CR: SFSEL (Bitfield-Mask: 0x01) */ -#define USIC_CH_DX5CR_CM_Pos \ - (10UL) /*!< USIC_CH DX5CR: CM (Bit 10) */ -#define USIC_CH_DX5CR_CM_Msk \ - (0xc00UL) /*!< USIC_CH DX5CR: CM (Bitfield-Mask: 0x03) */ -#define USIC_CH_DX5CR_DXS_Pos \ - (15UL) /*!< USIC_CH DX5CR: DXS (Bit 15) */ -#define USIC_CH_DX5CR_DXS_Msk \ - (0x8000UL) /*!< USIC_CH DX5CR: DXS (Bitfield-Mask: 0x01) */ - -/* -------------------------------- USIC_CH_SCTR -------------------------------- */ -#define USIC_CH_SCTR_SDIR_Pos \ - (0UL) /*!< USIC_CH SCTR: SDIR (Bit 0) */ -#define USIC_CH_SCTR_SDIR_Msk \ - (0x1UL) /*!< USIC_CH SCTR: SDIR (Bitfield-Mask: 0x01) */ -#define USIC_CH_SCTR_PDL_Pos \ - (1UL) /*!< USIC_CH SCTR: PDL (Bit 1) */ -#define USIC_CH_SCTR_PDL_Msk \ - (0x2UL) /*!< USIC_CH SCTR: PDL (Bitfield-Mask: 0x01) */ -#define USIC_CH_SCTR_DSM_Pos \ - (2UL) /*!< USIC_CH SCTR: DSM (Bit 2) */ -#define USIC_CH_SCTR_DSM_Msk \ - (0xcUL) /*!< USIC_CH SCTR: DSM (Bitfield-Mask: 0x03) */ -#define USIC_CH_SCTR_HPCDIR_Pos \ - (4UL) /*!< USIC_CH SCTR: HPCDIR (Bit 4) */ -#define USIC_CH_SCTR_HPCDIR_Msk \ - (0x10UL) /*!< USIC_CH SCTR: HPCDIR (Bitfield-Mask: 0x01) */ -#define USIC_CH_SCTR_DOCFG_Pos \ - (6UL) /*!< USIC_CH SCTR: DOCFG (Bit 6) */ -#define USIC_CH_SCTR_DOCFG_Msk \ - (0xc0UL) /*!< USIC_CH SCTR: DOCFG (Bitfield-Mask: 0x03) */ -#define USIC_CH_SCTR_TRM_Pos \ - (8UL) /*!< USIC_CH SCTR: TRM (Bit 8) */ -#define USIC_CH_SCTR_TRM_Msk \ - (0x300UL) /*!< USIC_CH SCTR: TRM (Bitfield-Mask: 0x03) */ -#define USIC_CH_SCTR_FLE_Pos \ - (16UL) /*!< USIC_CH SCTR: FLE (Bit 16) */ -#define USIC_CH_SCTR_FLE_Msk \ - (0x3f0000UL) /*!< USIC_CH SCTR: FLE (Bitfield-Mask: 0x3f) */ -#define USIC_CH_SCTR_WLE_Pos \ - (24UL) /*!< USIC_CH SCTR: WLE (Bit 24) */ -#define USIC_CH_SCTR_WLE_Msk \ - (0xf000000UL) /*!< USIC_CH SCTR: WLE (Bitfield-Mask: 0x0f) */ - -/* -------------------------------- USIC_CH_TCSR -------------------------------- */ -#define USIC_CH_TCSR_WLEMD_Pos \ - (0UL) /*!< USIC_CH TCSR: WLEMD (Bit 0) */ -#define USIC_CH_TCSR_WLEMD_Msk \ - (0x1UL) /*!< USIC_CH TCSR: WLEMD (Bitfield-Mask: 0x01) */ -#define USIC_CH_TCSR_SELMD_Pos \ - (1UL) /*!< USIC_CH TCSR: SELMD (Bit 1) */ -#define USIC_CH_TCSR_SELMD_Msk \ - (0x2UL) /*!< USIC_CH TCSR: SELMD (Bitfield-Mask: 0x01) */ -#define USIC_CH_TCSR_FLEMD_Pos \ - (2UL) /*!< USIC_CH TCSR: FLEMD (Bit 2) */ -#define USIC_CH_TCSR_FLEMD_Msk \ - (0x4UL) /*!< USIC_CH TCSR: FLEMD (Bitfield-Mask: 0x01) */ -#define USIC_CH_TCSR_WAMD_Pos \ - (3UL) /*!< USIC_CH TCSR: WAMD (Bit 3) */ -#define USIC_CH_TCSR_WAMD_Msk \ - (0x8UL) /*!< USIC_CH TCSR: WAMD (Bitfield-Mask: 0x01) */ -#define USIC_CH_TCSR_HPCMD_Pos \ - (4UL) /*!< USIC_CH TCSR: HPCMD (Bit 4) */ -#define USIC_CH_TCSR_HPCMD_Msk \ - (0x10UL) /*!< USIC_CH TCSR: HPCMD (Bitfield-Mask: 0x01) */ -#define USIC_CH_TCSR_SOF_Pos \ - (5UL) /*!< USIC_CH TCSR: SOF (Bit 5) */ -#define USIC_CH_TCSR_SOF_Msk \ - (0x20UL) /*!< USIC_CH TCSR: SOF (Bitfield-Mask: 0x01) */ -#define USIC_CH_TCSR_EOF_Pos \ - (6UL) /*!< USIC_CH TCSR: EOF (Bit 6) */ -#define USIC_CH_TCSR_EOF_Msk \ - (0x40UL) /*!< USIC_CH TCSR: EOF (Bitfield-Mask: 0x01) */ -#define USIC_CH_TCSR_TDV_Pos \ - (7UL) /*!< USIC_CH TCSR: TDV (Bit 7) */ -#define USIC_CH_TCSR_TDV_Msk \ - (0x80UL) /*!< USIC_CH TCSR: TDV (Bitfield-Mask: 0x01) */ -#define USIC_CH_TCSR_TDSSM_Pos \ - (8UL) /*!< USIC_CH TCSR: TDSSM (Bit 8) */ -#define USIC_CH_TCSR_TDSSM_Msk \ - (0x100UL) /*!< USIC_CH TCSR: TDSSM (Bitfield-Mask: 0x01) */ -#define USIC_CH_TCSR_TDEN_Pos \ - (10UL) /*!< USIC_CH TCSR: TDEN (Bit 10) */ -#define USIC_CH_TCSR_TDEN_Msk \ - (0xc00UL) /*!< USIC_CH TCSR: TDEN (Bitfield-Mask: 0x03) */ -#define USIC_CH_TCSR_TDVTR_Pos \ - (12UL) /*!< USIC_CH TCSR: TDVTR (Bit 12) */ -#define USIC_CH_TCSR_TDVTR_Msk \ - (0x1000UL) /*!< USIC_CH TCSR: TDVTR (Bitfield-Mask: 0x01) */ -#define USIC_CH_TCSR_WA_Pos \ - (13UL) /*!< USIC_CH TCSR: WA (Bit 13) */ -#define USIC_CH_TCSR_WA_Msk \ - (0x2000UL) /*!< USIC_CH TCSR: WA (Bitfield-Mask: 0x01) */ -#define USIC_CH_TCSR_TSOF_Pos \ - (24UL) /*!< USIC_CH TCSR: TSOF (Bit 24) */ -#define USIC_CH_TCSR_TSOF_Msk \ - (0x1000000UL) /*!< USIC_CH TCSR: TSOF (Bitfield-Mask: 0x01) */ -#define USIC_CH_TCSR_TV_Pos \ - (26UL) /*!< USIC_CH TCSR: TV (Bit 26) */ -#define USIC_CH_TCSR_TV_Msk \ - (0x4000000UL) /*!< USIC_CH TCSR: TV (Bitfield-Mask: 0x01) */ -#define USIC_CH_TCSR_TVC_Pos \ - (27UL) /*!< USIC_CH TCSR: TVC (Bit 27) */ -#define USIC_CH_TCSR_TVC_Msk \ - (0x8000000UL) /*!< USIC_CH TCSR: TVC (Bitfield-Mask: 0x01) */ -#define USIC_CH_TCSR_TE_Pos \ - (28UL) /*!< USIC_CH TCSR: TE (Bit 28) */ -#define USIC_CH_TCSR_TE_Msk \ - (0x10000000UL) /*!< USIC_CH TCSR: TE (Bitfield-Mask: 0x01) */ - -/* --------------------------------- USIC_CH_PCR -------------------------------- */ -#define USIC_CH_PCR_CTR0_Pos \ - (0UL) /*!< USIC_CH PCR: CTR0 (Bit 0) */ -#define USIC_CH_PCR_CTR0_Msk \ - (0x1UL) /*!< USIC_CH PCR: CTR0 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR1_Pos \ - (1UL) /*!< USIC_CH PCR: CTR1 (Bit 1) */ -#define USIC_CH_PCR_CTR1_Msk \ - (0x2UL) /*!< USIC_CH PCR: CTR1 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR2_Pos \ - (2UL) /*!< USIC_CH PCR: CTR2 (Bit 2) */ -#define USIC_CH_PCR_CTR2_Msk \ - (0x4UL) /*!< USIC_CH PCR: CTR2 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR3_Pos \ - (3UL) /*!< USIC_CH PCR: CTR3 (Bit 3) */ -#define USIC_CH_PCR_CTR3_Msk \ - (0x8UL) /*!< USIC_CH PCR: CTR3 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR4_Pos \ - (4UL) /*!< USIC_CH PCR: CTR4 (Bit 4) */ -#define USIC_CH_PCR_CTR4_Msk \ - (0x10UL) /*!< USIC_CH PCR: CTR4 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR5_Pos \ - (5UL) /*!< USIC_CH PCR: CTR5 (Bit 5) */ -#define USIC_CH_PCR_CTR5_Msk \ - (0x20UL) /*!< USIC_CH PCR: CTR5 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR6_Pos \ - (6UL) /*!< USIC_CH PCR: CTR6 (Bit 6) */ -#define USIC_CH_PCR_CTR6_Msk \ - (0x40UL) /*!< USIC_CH PCR: CTR6 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR7_Pos \ - (7UL) /*!< USIC_CH PCR: CTR7 (Bit 7) */ -#define USIC_CH_PCR_CTR7_Msk \ - (0x80UL) /*!< USIC_CH PCR: CTR7 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR8_Pos \ - (8UL) /*!< USIC_CH PCR: CTR8 (Bit 8) */ -#define USIC_CH_PCR_CTR8_Msk \ - (0x100UL) /*!< USIC_CH PCR: CTR8 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR9_Pos \ - (9UL) /*!< USIC_CH PCR: CTR9 (Bit 9) */ -#define USIC_CH_PCR_CTR9_Msk \ - (0x200UL) /*!< USIC_CH PCR: CTR9 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR10_Pos \ - (10UL) /*!< USIC_CH PCR: CTR10 (Bit 10) */ -#define USIC_CH_PCR_CTR10_Msk \ - (0x400UL) /*!< USIC_CH PCR: CTR10 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR11_Pos \ - (11UL) /*!< USIC_CH PCR: CTR11 (Bit 11) */ -#define USIC_CH_PCR_CTR11_Msk \ - (0x800UL) /*!< USIC_CH PCR: CTR11 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR12_Pos \ - (12UL) /*!< USIC_CH PCR: CTR12 (Bit 12) */ -#define USIC_CH_PCR_CTR12_Msk \ - (0x1000UL) /*!< USIC_CH PCR: CTR12 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR13_Pos \ - (13UL) /*!< USIC_CH PCR: CTR13 (Bit 13) */ -#define USIC_CH_PCR_CTR13_Msk \ - (0x2000UL) /*!< USIC_CH PCR: CTR13 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR14_Pos \ - (14UL) /*!< USIC_CH PCR: CTR14 (Bit 14) */ -#define USIC_CH_PCR_CTR14_Msk \ - (0x4000UL) /*!< USIC_CH PCR: CTR14 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR15_Pos \ - (15UL) /*!< USIC_CH PCR: CTR15 (Bit 15) */ -#define USIC_CH_PCR_CTR15_Msk \ - (0x8000UL) /*!< USIC_CH PCR: CTR15 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR16_Pos \ - (16UL) /*!< USIC_CH PCR: CTR16 (Bit 16) */ -#define USIC_CH_PCR_CTR16_Msk \ - (0x10000UL) /*!< USIC_CH PCR: CTR16 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR17_Pos \ - (17UL) /*!< USIC_CH PCR: CTR17 (Bit 17) */ -#define USIC_CH_PCR_CTR17_Msk \ - (0x20000UL) /*!< USIC_CH PCR: CTR17 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR18_Pos \ - (18UL) /*!< USIC_CH PCR: CTR18 (Bit 18) */ -#define USIC_CH_PCR_CTR18_Msk \ - (0x40000UL) /*!< USIC_CH PCR: CTR18 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR19_Pos \ - (19UL) /*!< USIC_CH PCR: CTR19 (Bit 19) */ -#define USIC_CH_PCR_CTR19_Msk \ - (0x80000UL) /*!< USIC_CH PCR: CTR19 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR20_Pos \ - (20UL) /*!< USIC_CH PCR: CTR20 (Bit 20) */ -#define USIC_CH_PCR_CTR20_Msk \ - (0x100000UL) /*!< USIC_CH PCR: CTR20 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR21_Pos \ - (21UL) /*!< USIC_CH PCR: CTR21 (Bit 21) */ -#define USIC_CH_PCR_CTR21_Msk \ - (0x200000UL) /*!< USIC_CH PCR: CTR21 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR22_Pos \ - (22UL) /*!< USIC_CH PCR: CTR22 (Bit 22) */ -#define USIC_CH_PCR_CTR22_Msk \ - (0x400000UL) /*!< USIC_CH PCR: CTR22 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR23_Pos \ - (23UL) /*!< USIC_CH PCR: CTR23 (Bit 23) */ -#define USIC_CH_PCR_CTR23_Msk \ - (0x800000UL) /*!< USIC_CH PCR: CTR23 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR24_Pos \ - (24UL) /*!< USIC_CH PCR: CTR24 (Bit 24) */ -#define USIC_CH_PCR_CTR24_Msk \ - (0x1000000UL) /*!< USIC_CH PCR: CTR24 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR25_Pos \ - (25UL) /*!< USIC_CH PCR: CTR25 (Bit 25) */ -#define USIC_CH_PCR_CTR25_Msk \ - (0x2000000UL) /*!< USIC_CH PCR: CTR25 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR26_Pos \ - (26UL) /*!< USIC_CH PCR: CTR26 (Bit 26) */ -#define USIC_CH_PCR_CTR26_Msk \ - (0x4000000UL) /*!< USIC_CH PCR: CTR26 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR27_Pos \ - (27UL) /*!< USIC_CH PCR: CTR27 (Bit 27) */ -#define USIC_CH_PCR_CTR27_Msk \ - (0x8000000UL) /*!< USIC_CH PCR: CTR27 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR28_Pos \ - (28UL) /*!< USIC_CH PCR: CTR28 (Bit 28) */ -#define USIC_CH_PCR_CTR28_Msk \ - (0x10000000UL) /*!< USIC_CH PCR: CTR28 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR29_Pos \ - (29UL) /*!< USIC_CH PCR: CTR29 (Bit 29) */ -#define USIC_CH_PCR_CTR29_Msk \ - (0x20000000UL) /*!< USIC_CH PCR: CTR29 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR30_Pos \ - (30UL) /*!< USIC_CH PCR: CTR30 (Bit 30) */ -#define USIC_CH_PCR_CTR30_Msk \ - (0x40000000UL) /*!< USIC_CH PCR: CTR30 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_CTR31_Pos \ - (31UL) /*!< USIC_CH PCR: CTR31 (Bit 31) */ -#define USIC_CH_PCR_CTR31_Msk \ - (0x80000000UL) /*!< USIC_CH PCR: CTR31 (Bitfield-Mask: 0x01) */ - -/* ----------------------------- USIC_CH_PCR_ASCMode ---------------------------- */ -#define USIC_CH_PCR_ASCMode_SMD_Pos \ - (0UL) /*!< USIC_CH PCR_ASCMode: SMD (Bit 0) */ -#define USIC_CH_PCR_ASCMode_SMD_Msk \ - (0x1UL) /*!< USIC_CH PCR_ASCMode: SMD (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_ASCMode_STPB_Pos \ - (1UL) /*!< USIC_CH PCR_ASCMode: STPB (Bit 1) */ -#define USIC_CH_PCR_ASCMode_STPB_Msk \ - (0x2UL) /*!< USIC_CH PCR_ASCMode: STPB (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_ASCMode_IDM_Pos \ - (2UL) /*!< USIC_CH PCR_ASCMode: IDM (Bit 2) */ -#define USIC_CH_PCR_ASCMode_IDM_Msk \ - (0x4UL) /*!< USIC_CH PCR_ASCMode: IDM (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_ASCMode_SBIEN_Pos \ - (3UL) /*!< USIC_CH PCR_ASCMode: SBIEN (Bit 3) */ -#define USIC_CH_PCR_ASCMode_SBIEN_Msk \ - (0x8UL) /*!< USIC_CH PCR_ASCMode: SBIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_ASCMode_CDEN_Pos \ - (4UL) /*!< USIC_CH PCR_ASCMode: CDEN (Bit 4) */ -#define USIC_CH_PCR_ASCMode_CDEN_Msk \ - (0x10UL) /*!< USIC_CH PCR_ASCMode: CDEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_ASCMode_RNIEN_Pos \ - (5UL) /*!< USIC_CH PCR_ASCMode: RNIEN (Bit 5) */ -#define USIC_CH_PCR_ASCMode_RNIEN_Msk \ - (0x20UL) /*!< USIC_CH PCR_ASCMode: RNIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_ASCMode_FEIEN_Pos \ - (6UL) /*!< USIC_CH PCR_ASCMode: FEIEN (Bit 6) */ -#define USIC_CH_PCR_ASCMode_FEIEN_Msk \ - (0x40UL) /*!< USIC_CH PCR_ASCMode: FEIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_ASCMode_FFIEN_Pos \ - (7UL) /*!< USIC_CH PCR_ASCMode: FFIEN (Bit 7) */ -#define USIC_CH_PCR_ASCMode_FFIEN_Msk \ - (0x80UL) /*!< USIC_CH PCR_ASCMode: FFIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_ASCMode_SP_Pos \ - (8UL) /*!< USIC_CH PCR_ASCMode: SP (Bit 8) */ -#define USIC_CH_PCR_ASCMode_SP_Msk \ - (0x1f00UL) /*!< USIC_CH PCR_ASCMode: SP (Bitfield-Mask: 0x1f) */ -#define USIC_CH_PCR_ASCMode_PL_Pos \ - (13UL) /*!< USIC_CH PCR_ASCMode: PL (Bit 13) */ -#define USIC_CH_PCR_ASCMode_PL_Msk \ - (0xe000UL) /*!< USIC_CH PCR_ASCMode: PL (Bitfield-Mask: 0x07) */ -#define USIC_CH_PCR_ASCMode_RSTEN_Pos \ - (16UL) /*!< USIC_CH PCR_ASCMode: RSTEN (Bit 16) */ -#define USIC_CH_PCR_ASCMode_RSTEN_Msk \ - (0x10000UL) /*!< USIC_CH PCR_ASCMode: RSTEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_ASCMode_TSTEN_Pos \ - (17UL) /*!< USIC_CH PCR_ASCMode: TSTEN (Bit 17) */ -#define USIC_CH_PCR_ASCMode_TSTEN_Msk \ - (0x20000UL) /*!< USIC_CH PCR_ASCMode: TSTEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_ASCMode_MCLK_Pos \ - (31UL) /*!< USIC_CH PCR_ASCMode: MCLK (Bit 31) */ -#define USIC_CH_PCR_ASCMode_MCLK_Msk \ - (0x80000000UL) /*!< USIC_CH PCR_ASCMode: MCLK (Bitfield-Mask: 0x01) */ - -/* ----------------------------- USIC_CH_PCR_SSCMode ---------------------------- */ -#define USIC_CH_PCR_SSCMode_MSLSEN_Pos \ - (0UL) /*!< USIC_CH PCR_SSCMode: MSLSEN (Bit 0) */ -#define USIC_CH_PCR_SSCMode_MSLSEN_Msk \ - (0x1UL) /*!< USIC_CH PCR_SSCMode: MSLSEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_SSCMode_SELCTR_Pos \ - (1UL) /*!< USIC_CH PCR_SSCMode: SELCTR (Bit 1) */ -#define USIC_CH_PCR_SSCMode_SELCTR_Msk \ - (0x2UL) /*!< USIC_CH PCR_SSCMode: SELCTR (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_SSCMode_SELINV_Pos \ - (2UL) /*!< USIC_CH PCR_SSCMode: SELINV (Bit 2) */ -#define USIC_CH_PCR_SSCMode_SELINV_Msk \ - (0x4UL) /*!< USIC_CH PCR_SSCMode: SELINV (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_SSCMode_FEM_Pos \ - (3UL) /*!< USIC_CH PCR_SSCMode: FEM (Bit 3) */ -#define USIC_CH_PCR_SSCMode_FEM_Msk \ - (0x8UL) /*!< USIC_CH PCR_SSCMode: FEM (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_SSCMode_CTQSEL1_Pos \ - (4UL) /*!< USIC_CH PCR_SSCMode: CTQSEL1 (Bit 4) */ -#define USIC_CH_PCR_SSCMode_CTQSEL1_Msk \ - (0x30UL) /*!< USIC_CH PCR_SSCMode: CTQSEL1 (Bitfield-Mask: 0x03) */ -#define USIC_CH_PCR_SSCMode_PCTQ1_Pos \ - (6UL) /*!< USIC_CH PCR_SSCMode: PCTQ1 (Bit 6) */ -#define USIC_CH_PCR_SSCMode_PCTQ1_Msk \ - (0xc0UL) /*!< USIC_CH PCR_SSCMode: PCTQ1 (Bitfield-Mask: 0x03) */ -#define USIC_CH_PCR_SSCMode_DCTQ1_Pos \ - (8UL) /*!< USIC_CH PCR_SSCMode: DCTQ1 (Bit 8) */ -#define USIC_CH_PCR_SSCMode_DCTQ1_Msk \ - (0x1f00UL) /*!< USIC_CH PCR_SSCMode: DCTQ1 (Bitfield-Mask: 0x1f) */ -#define USIC_CH_PCR_SSCMode_PARIEN_Pos \ - (13UL) /*!< USIC_CH PCR_SSCMode: PARIEN (Bit 13) */ -#define USIC_CH_PCR_SSCMode_PARIEN_Msk \ - (0x2000UL) /*!< USIC_CH PCR_SSCMode: PARIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_SSCMode_MSLSIEN_Pos \ - (14UL) /*!< USIC_CH PCR_SSCMode: MSLSIEN (Bit 14) */ -#define USIC_CH_PCR_SSCMode_MSLSIEN_Msk \ - (0x4000UL) /*!< USIC_CH PCR_SSCMode: MSLSIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_SSCMode_DX2TIEN_Pos \ - (15UL) /*!< USIC_CH PCR_SSCMode: DX2TIEN (Bit 15) */ -#define USIC_CH_PCR_SSCMode_DX2TIEN_Msk \ - (0x8000UL) /*!< USIC_CH PCR_SSCMode: DX2TIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_SSCMode_SELO_Pos \ - (16UL) /*!< USIC_CH PCR_SSCMode: SELO (Bit 16) */ -#define USIC_CH_PCR_SSCMode_SELO_Msk \ - (0xff0000UL) /*!< USIC_CH PCR_SSCMode: SELO (Bitfield-Mask: 0xff) */ -#define USIC_CH_PCR_SSCMode_TIWEN_Pos \ - (24UL) /*!< USIC_CH PCR_SSCMode: TIWEN (Bit 24) */ -#define USIC_CH_PCR_SSCMode_TIWEN_Msk \ - (0x1000000UL) /*!< USIC_CH PCR_SSCMode: TIWEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_SSCMode_SLPHSEL_Pos \ - (25UL) /*!< USIC_CH PCR_SSCMode: SLPHSEL (Bit 25) */ -#define USIC_CH_PCR_SSCMode_SLPHSEL_Msk \ - (0x2000000UL) /*!< USIC_CH PCR_SSCMode: SLPHSEL (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_SSCMode_MCLK_Pos \ - (31UL) /*!< USIC_CH PCR_SSCMode: MCLK (Bit 31) */ -#define USIC_CH_PCR_SSCMode_MCLK_Msk \ - (0x80000000UL) /*!< USIC_CH PCR_SSCMode: MCLK (Bitfield-Mask: 0x01) */ - -/* ----------------------------- USIC_CH_PCR_IICMode ---------------------------- */ -#define USIC_CH_PCR_IICMode_SLAD_Pos \ - (0UL) /*!< USIC_CH PCR_IICMode: SLAD (Bit 0) */ -#define USIC_CH_PCR_IICMode_SLAD_Msk \ - (0xffffUL) /*!< USIC_CH PCR_IICMode: SLAD (Bitfield-Mask: 0xffff) */ -#define USIC_CH_PCR_IICMode_ACK00_Pos \ - (16UL) /*!< USIC_CH PCR_IICMode: ACK00 (Bit 16) */ -#define USIC_CH_PCR_IICMode_ACK00_Msk \ - (0x10000UL) /*!< USIC_CH PCR_IICMode: ACK00 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_IICMode_STIM_Pos \ - (17UL) /*!< USIC_CH PCR_IICMode: STIM (Bit 17) */ -#define USIC_CH_PCR_IICMode_STIM_Msk \ - (0x20000UL) /*!< USIC_CH PCR_IICMode: STIM (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_IICMode_SCRIEN_Pos \ - (18UL) /*!< USIC_CH PCR_IICMode: SCRIEN (Bit 18) */ -#define USIC_CH_PCR_IICMode_SCRIEN_Msk \ - (0x40000UL) /*!< USIC_CH PCR_IICMode: SCRIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_IICMode_RSCRIEN_Pos \ - (19UL) /*!< USIC_CH PCR_IICMode: RSCRIEN (Bit 19) */ -#define USIC_CH_PCR_IICMode_RSCRIEN_Msk \ - (0x80000UL) /*!< USIC_CH PCR_IICMode: RSCRIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_IICMode_PCRIEN_Pos \ - (20UL) /*!< USIC_CH PCR_IICMode: PCRIEN (Bit 20) */ -#define USIC_CH_PCR_IICMode_PCRIEN_Msk \ - (0x100000UL) /*!< USIC_CH PCR_IICMode: PCRIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_IICMode_NACKIEN_Pos \ - (21UL) /*!< USIC_CH PCR_IICMode: NACKIEN (Bit 21) */ -#define USIC_CH_PCR_IICMode_NACKIEN_Msk \ - (0x200000UL) /*!< USIC_CH PCR_IICMode: NACKIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_IICMode_ARLIEN_Pos \ - (22UL) /*!< USIC_CH PCR_IICMode: ARLIEN (Bit 22) */ -#define USIC_CH_PCR_IICMode_ARLIEN_Msk \ - (0x400000UL) /*!< USIC_CH PCR_IICMode: ARLIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_IICMode_SRRIEN_Pos \ - (23UL) /*!< USIC_CH PCR_IICMode: SRRIEN (Bit 23) */ -#define USIC_CH_PCR_IICMode_SRRIEN_Msk \ - (0x800000UL) /*!< USIC_CH PCR_IICMode: SRRIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_IICMode_ERRIEN_Pos \ - (24UL) /*!< USIC_CH PCR_IICMode: ERRIEN (Bit 24) */ -#define USIC_CH_PCR_IICMode_ERRIEN_Msk \ - (0x1000000UL) /*!< USIC_CH PCR_IICMode: ERRIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_IICMode_SACKDIS_Pos \ - (25UL) /*!< USIC_CH PCR_IICMode: SACKDIS (Bit 25) */ -#define USIC_CH_PCR_IICMode_SACKDIS_Msk \ - (0x2000000UL) /*!< USIC_CH PCR_IICMode: SACKDIS (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_IICMode_HDEL_Pos \ - (26UL) /*!< USIC_CH PCR_IICMode: HDEL (Bit 26) */ -#define USIC_CH_PCR_IICMode_HDEL_Msk \ - (0x3c000000UL) /*!< USIC_CH PCR_IICMode: HDEL (Bitfield-Mask: 0x0f) */ -#define USIC_CH_PCR_IICMode_ACKIEN_Pos \ - (30UL) /*!< USIC_CH PCR_IICMode: ACKIEN (Bit 30) */ -#define USIC_CH_PCR_IICMode_ACKIEN_Msk \ - (0x40000000UL) /*!< USIC_CH PCR_IICMode: ACKIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_IICMode_MCLK_Pos \ - (31UL) /*!< USIC_CH PCR_IICMode: MCLK (Bit 31) */ -#define USIC_CH_PCR_IICMode_MCLK_Msk \ - (0x80000000UL) /*!< USIC_CH PCR_IICMode: MCLK (Bitfield-Mask: 0x01) */ - -/* ----------------------------- USIC_CH_PCR_IISMode ---------------------------- */ -#define USIC_CH_PCR_IISMode_WAGEN_Pos \ - (0UL) /*!< USIC_CH PCR_IISMode: WAGEN (Bit 0) */ -#define USIC_CH_PCR_IISMode_WAGEN_Msk \ - (0x1UL) /*!< USIC_CH PCR_IISMode: WAGEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_IISMode_DTEN_Pos \ - (1UL) /*!< USIC_CH PCR_IISMode: DTEN (Bit 1) */ -#define USIC_CH_PCR_IISMode_DTEN_Msk \ - (0x2UL) /*!< USIC_CH PCR_IISMode: DTEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_IISMode_SELINV_Pos \ - (2UL) /*!< USIC_CH PCR_IISMode: SELINV (Bit 2) */ -#define USIC_CH_PCR_IISMode_SELINV_Msk \ - (0x4UL) /*!< USIC_CH PCR_IISMode: SELINV (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_IISMode_WAFEIEN_Pos \ - (4UL) /*!< USIC_CH PCR_IISMode: WAFEIEN (Bit 4) */ -#define USIC_CH_PCR_IISMode_WAFEIEN_Msk \ - (0x10UL) /*!< USIC_CH PCR_IISMode: WAFEIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_IISMode_WAREIEN_Pos \ - (5UL) /*!< USIC_CH PCR_IISMode: WAREIEN (Bit 5) */ -#define USIC_CH_PCR_IISMode_WAREIEN_Msk \ - (0x20UL) /*!< USIC_CH PCR_IISMode: WAREIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_IISMode_ENDIEN_Pos \ - (6UL) /*!< USIC_CH PCR_IISMode: ENDIEN (Bit 6) */ -#define USIC_CH_PCR_IISMode_ENDIEN_Msk \ - (0x40UL) /*!< USIC_CH PCR_IISMode: ENDIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_IISMode_DX2TIEN_Pos \ - (15UL) /*!< USIC_CH PCR_IISMode: DX2TIEN (Bit 15) */ -#define USIC_CH_PCR_IISMode_DX2TIEN_Msk \ - (0x8000UL) /*!< USIC_CH PCR_IISMode: DX2TIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_PCR_IISMode_TDEL_Pos \ - (16UL) /*!< USIC_CH PCR_IISMode: TDEL (Bit 16) */ -#define USIC_CH_PCR_IISMode_TDEL_Msk \ - (0x3f0000UL) /*!< USIC_CH PCR_IISMode: TDEL (Bitfield-Mask: 0x3f) */ -#define USIC_CH_PCR_IISMode_MCLK_Pos \ - (31UL) /*!< USIC_CH PCR_IISMode: MCLK (Bit 31) */ -#define USIC_CH_PCR_IISMode_MCLK_Msk \ - (0x80000000UL) /*!< USIC_CH PCR_IISMode: MCLK (Bitfield-Mask: 0x01) */ - -/* --------------------------------- USIC_CH_CCR -------------------------------- */ -#define USIC_CH_CCR_MODE_Pos \ - (0UL) /*!< USIC_CH CCR: MODE (Bit 0) */ -#define USIC_CH_CCR_MODE_Msk \ - (0xfUL) /*!< USIC_CH CCR: MODE (Bitfield-Mask: 0x0f) */ -#define USIC_CH_CCR_HPCEN_Pos \ - (6UL) /*!< USIC_CH CCR: HPCEN (Bit 6) */ -#define USIC_CH_CCR_HPCEN_Msk \ - (0xc0UL) /*!< USIC_CH CCR: HPCEN (Bitfield-Mask: 0x03) */ -#define USIC_CH_CCR_PM_Pos (8UL) /*!< USIC_CH CCR: PM (Bit 8) */ -#define USIC_CH_CCR_PM_Msk \ - (0x300UL) /*!< USIC_CH CCR: PM (Bitfield-Mask: 0x03) */ -#define USIC_CH_CCR_RSIEN_Pos \ - (10UL) /*!< USIC_CH CCR: RSIEN (Bit 10) */ -#define USIC_CH_CCR_RSIEN_Msk \ - (0x400UL) /*!< USIC_CH CCR: RSIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_CCR_DLIEN_Pos \ - (11UL) /*!< USIC_CH CCR: DLIEN (Bit 11) */ -#define USIC_CH_CCR_DLIEN_Msk \ - (0x800UL) /*!< USIC_CH CCR: DLIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_CCR_TSIEN_Pos \ - (12UL) /*!< USIC_CH CCR: TSIEN (Bit 12) */ -#define USIC_CH_CCR_TSIEN_Msk \ - (0x1000UL) /*!< USIC_CH CCR: TSIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_CCR_TBIEN_Pos \ - (13UL) /*!< USIC_CH CCR: TBIEN (Bit 13) */ -#define USIC_CH_CCR_TBIEN_Msk \ - (0x2000UL) /*!< USIC_CH CCR: TBIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_CCR_RIEN_Pos \ - (14UL) /*!< USIC_CH CCR: RIEN (Bit 14) */ -#define USIC_CH_CCR_RIEN_Msk \ - (0x4000UL) /*!< USIC_CH CCR: RIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_CCR_AIEN_Pos \ - (15UL) /*!< USIC_CH CCR: AIEN (Bit 15) */ -#define USIC_CH_CCR_AIEN_Msk \ - (0x8000UL) /*!< USIC_CH CCR: AIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_CCR_BRGIEN_Pos \ - (16UL) /*!< USIC_CH CCR: BRGIEN (Bit 16) */ -#define USIC_CH_CCR_BRGIEN_Msk \ - (0x10000UL) /*!< USIC_CH CCR: BRGIEN (Bitfield-Mask: 0x01) */ - -/* -------------------------------- USIC_CH_CMTR -------------------------------- */ -#define USIC_CH_CMTR_CTV_Pos \ - (0UL) /*!< USIC_CH CMTR: CTV (Bit 0) */ -#define USIC_CH_CMTR_CTV_Msk \ - (0x3ffUL) /*!< USIC_CH CMTR: CTV (Bitfield-Mask: 0x3ff) */ - -/* --------------------------------- USIC_CH_PSR -------------------------------- */ -#define USIC_CH_PSR_ST0_Pos \ - (0UL) /*!< USIC_CH PSR: ST0 (Bit 0) */ -#define USIC_CH_PSR_ST0_Msk \ - (0x1UL) /*!< USIC_CH PSR: ST0 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_ST1_Pos \ - (1UL) /*!< USIC_CH PSR: ST1 (Bit 1) */ -#define USIC_CH_PSR_ST1_Msk \ - (0x2UL) /*!< USIC_CH PSR: ST1 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_ST2_Pos \ - (2UL) /*!< USIC_CH PSR: ST2 (Bit 2) */ -#define USIC_CH_PSR_ST2_Msk \ - (0x4UL) /*!< USIC_CH PSR: ST2 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_ST3_Pos \ - (3UL) /*!< USIC_CH PSR: ST3 (Bit 3) */ -#define USIC_CH_PSR_ST3_Msk \ - (0x8UL) /*!< USIC_CH PSR: ST3 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_ST4_Pos \ - (4UL) /*!< USIC_CH PSR: ST4 (Bit 4) */ -#define USIC_CH_PSR_ST4_Msk \ - (0x10UL) /*!< USIC_CH PSR: ST4 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_ST5_Pos \ - (5UL) /*!< USIC_CH PSR: ST5 (Bit 5) */ -#define USIC_CH_PSR_ST5_Msk \ - (0x20UL) /*!< USIC_CH PSR: ST5 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_ST6_Pos \ - (6UL) /*!< USIC_CH PSR: ST6 (Bit 6) */ -#define USIC_CH_PSR_ST6_Msk \ - (0x40UL) /*!< USIC_CH PSR: ST6 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_ST7_Pos \ - (7UL) /*!< USIC_CH PSR: ST7 (Bit 7) */ -#define USIC_CH_PSR_ST7_Msk \ - (0x80UL) /*!< USIC_CH PSR: ST7 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_ST8_Pos \ - (8UL) /*!< USIC_CH PSR: ST8 (Bit 8) */ -#define USIC_CH_PSR_ST8_Msk \ - (0x100UL) /*!< USIC_CH PSR: ST8 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_ST9_Pos \ - (9UL) /*!< USIC_CH PSR: ST9 (Bit 9) */ -#define USIC_CH_PSR_ST9_Msk \ - (0x200UL) /*!< USIC_CH PSR: ST9 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_RSIF_Pos \ - (10UL) /*!< USIC_CH PSR: RSIF (Bit 10) */ -#define USIC_CH_PSR_RSIF_Msk \ - (0x400UL) /*!< USIC_CH PSR: RSIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_DLIF_Pos \ - (11UL) /*!< USIC_CH PSR: DLIF (Bit 11) */ -#define USIC_CH_PSR_DLIF_Msk \ - (0x800UL) /*!< USIC_CH PSR: DLIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_TSIF_Pos \ - (12UL) /*!< USIC_CH PSR: TSIF (Bit 12) */ -#define USIC_CH_PSR_TSIF_Msk \ - (0x1000UL) /*!< USIC_CH PSR: TSIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_TBIF_Pos \ - (13UL) /*!< USIC_CH PSR: TBIF (Bit 13) */ -#define USIC_CH_PSR_TBIF_Msk \ - (0x2000UL) /*!< USIC_CH PSR: TBIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_RIF_Pos \ - (14UL) /*!< USIC_CH PSR: RIF (Bit 14) */ -#define USIC_CH_PSR_RIF_Msk \ - (0x4000UL) /*!< USIC_CH PSR: RIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_AIF_Pos \ - (15UL) /*!< USIC_CH PSR: AIF (Bit 15) */ -#define USIC_CH_PSR_AIF_Msk \ - (0x8000UL) /*!< USIC_CH PSR: AIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_BRGIF_Pos \ - (16UL) /*!< USIC_CH PSR: BRGIF (Bit 16) */ -#define USIC_CH_PSR_BRGIF_Msk \ - (0x10000UL) /*!< USIC_CH PSR: BRGIF (Bitfield-Mask: 0x01) */ - -/* ----------------------------- USIC_CH_PSR_ASCMode ---------------------------- */ -#define USIC_CH_PSR_ASCMode_TXIDLE_Pos \ - (0UL) /*!< USIC_CH PSR_ASCMode: TXIDLE (Bit 0) */ -#define USIC_CH_PSR_ASCMode_TXIDLE_Msk \ - (0x1UL) /*!< USIC_CH PSR_ASCMode: TXIDLE (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_ASCMode_RXIDLE_Pos \ - (1UL) /*!< USIC_CH PSR_ASCMode: RXIDLE (Bit 1) */ -#define USIC_CH_PSR_ASCMode_RXIDLE_Msk \ - (0x2UL) /*!< USIC_CH PSR_ASCMode: RXIDLE (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_ASCMode_SBD_Pos \ - (2UL) /*!< USIC_CH PSR_ASCMode: SBD (Bit 2) */ -#define USIC_CH_PSR_ASCMode_SBD_Msk \ - (0x4UL) /*!< USIC_CH PSR_ASCMode: SBD (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_ASCMode_COL_Pos \ - (3UL) /*!< USIC_CH PSR_ASCMode: COL (Bit 3) */ -#define USIC_CH_PSR_ASCMode_COL_Msk \ - (0x8UL) /*!< USIC_CH PSR_ASCMode: COL (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_ASCMode_RNS_Pos \ - (4UL) /*!< USIC_CH PSR_ASCMode: RNS (Bit 4) */ -#define USIC_CH_PSR_ASCMode_RNS_Msk \ - (0x10UL) /*!< USIC_CH PSR_ASCMode: RNS (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_ASCMode_FER0_Pos \ - (5UL) /*!< USIC_CH PSR_ASCMode: FER0 (Bit 5) */ -#define USIC_CH_PSR_ASCMode_FER0_Msk \ - (0x20UL) /*!< USIC_CH PSR_ASCMode: FER0 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_ASCMode_FER1_Pos \ - (6UL) /*!< USIC_CH PSR_ASCMode: FER1 (Bit 6) */ -#define USIC_CH_PSR_ASCMode_FER1_Msk \ - (0x40UL) /*!< USIC_CH PSR_ASCMode: FER1 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_ASCMode_RFF_Pos \ - (7UL) /*!< USIC_CH PSR_ASCMode: RFF (Bit 7) */ -#define USIC_CH_PSR_ASCMode_RFF_Msk \ - (0x80UL) /*!< USIC_CH PSR_ASCMode: RFF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_ASCMode_TFF_Pos \ - (8UL) /*!< USIC_CH PSR_ASCMode: TFF (Bit 8) */ -#define USIC_CH_PSR_ASCMode_TFF_Msk \ - (0x100UL) /*!< USIC_CH PSR_ASCMode: TFF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_ASCMode_BUSY_Pos \ - (9UL) /*!< USIC_CH PSR_ASCMode: BUSY (Bit 9) */ -#define USIC_CH_PSR_ASCMode_BUSY_Msk \ - (0x200UL) /*!< USIC_CH PSR_ASCMode: BUSY (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_ASCMode_RSIF_Pos \ - (10UL) /*!< USIC_CH PSR_ASCMode: RSIF (Bit 10) */ -#define USIC_CH_PSR_ASCMode_RSIF_Msk \ - (0x400UL) /*!< USIC_CH PSR_ASCMode: RSIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_ASCMode_DLIF_Pos \ - (11UL) /*!< USIC_CH PSR_ASCMode: DLIF (Bit 11) */ -#define USIC_CH_PSR_ASCMode_DLIF_Msk \ - (0x800UL) /*!< USIC_CH PSR_ASCMode: DLIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_ASCMode_TSIF_Pos \ - (12UL) /*!< USIC_CH PSR_ASCMode: TSIF (Bit 12) */ -#define USIC_CH_PSR_ASCMode_TSIF_Msk \ - (0x1000UL) /*!< USIC_CH PSR_ASCMode: TSIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_ASCMode_TBIF_Pos \ - (13UL) /*!< USIC_CH PSR_ASCMode: TBIF (Bit 13) */ -#define USIC_CH_PSR_ASCMode_TBIF_Msk \ - (0x2000UL) /*!< USIC_CH PSR_ASCMode: TBIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_ASCMode_RIF_Pos \ - (14UL) /*!< USIC_CH PSR_ASCMode: RIF (Bit 14) */ -#define USIC_CH_PSR_ASCMode_RIF_Msk \ - (0x4000UL) /*!< USIC_CH PSR_ASCMode: RIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_ASCMode_AIF_Pos \ - (15UL) /*!< USIC_CH PSR_ASCMode: AIF (Bit 15) */ -#define USIC_CH_PSR_ASCMode_AIF_Msk \ - (0x8000UL) /*!< USIC_CH PSR_ASCMode: AIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_ASCMode_BRGIF_Pos \ - (16UL) /*!< USIC_CH PSR_ASCMode: BRGIF (Bit 16) */ -#define USIC_CH_PSR_ASCMode_BRGIF_Msk \ - (0x10000UL) /*!< USIC_CH PSR_ASCMode: BRGIF (Bitfield-Mask: 0x01) */ - -/* ----------------------------- USIC_CH_PSR_SSCMode ---------------------------- */ -#define USIC_CH_PSR_SSCMode_MSLS_Pos \ - (0UL) /*!< USIC_CH PSR_SSCMode: MSLS (Bit 0) */ -#define USIC_CH_PSR_SSCMode_MSLS_Msk \ - (0x1UL) /*!< USIC_CH PSR_SSCMode: MSLS (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_SSCMode_DX2S_Pos \ - (1UL) /*!< USIC_CH PSR_SSCMode: DX2S (Bit 1) */ -#define USIC_CH_PSR_SSCMode_DX2S_Msk \ - (0x2UL) /*!< USIC_CH PSR_SSCMode: DX2S (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_SSCMode_MSLSEV_Pos \ - (2UL) /*!< USIC_CH PSR_SSCMode: MSLSEV (Bit 2) */ -#define USIC_CH_PSR_SSCMode_MSLSEV_Msk \ - (0x4UL) /*!< USIC_CH PSR_SSCMode: MSLSEV (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_SSCMode_DX2TEV_Pos \ - (3UL) /*!< USIC_CH PSR_SSCMode: DX2TEV (Bit 3) */ -#define USIC_CH_PSR_SSCMode_DX2TEV_Msk \ - (0x8UL) /*!< USIC_CH PSR_SSCMode: DX2TEV (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_SSCMode_PARERR_Pos \ - (4UL) /*!< USIC_CH PSR_SSCMode: PARERR (Bit 4) */ -#define USIC_CH_PSR_SSCMode_PARERR_Msk \ - (0x10UL) /*!< USIC_CH PSR_SSCMode: PARERR (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_SSCMode_RSIF_Pos \ - (10UL) /*!< USIC_CH PSR_SSCMode: RSIF (Bit 10) */ -#define USIC_CH_PSR_SSCMode_RSIF_Msk \ - (0x400UL) /*!< USIC_CH PSR_SSCMode: RSIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_SSCMode_DLIF_Pos \ - (11UL) /*!< USIC_CH PSR_SSCMode: DLIF (Bit 11) */ -#define USIC_CH_PSR_SSCMode_DLIF_Msk \ - (0x800UL) /*!< USIC_CH PSR_SSCMode: DLIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_SSCMode_TSIF_Pos \ - (12UL) /*!< USIC_CH PSR_SSCMode: TSIF (Bit 12) */ -#define USIC_CH_PSR_SSCMode_TSIF_Msk \ - (0x1000UL) /*!< USIC_CH PSR_SSCMode: TSIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_SSCMode_TBIF_Pos \ - (13UL) /*!< USIC_CH PSR_SSCMode: TBIF (Bit 13) */ -#define USIC_CH_PSR_SSCMode_TBIF_Msk \ - (0x2000UL) /*!< USIC_CH PSR_SSCMode: TBIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_SSCMode_RIF_Pos \ - (14UL) /*!< USIC_CH PSR_SSCMode: RIF (Bit 14) */ -#define USIC_CH_PSR_SSCMode_RIF_Msk \ - (0x4000UL) /*!< USIC_CH PSR_SSCMode: RIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_SSCMode_AIF_Pos \ - (15UL) /*!< USIC_CH PSR_SSCMode: AIF (Bit 15) */ -#define USIC_CH_PSR_SSCMode_AIF_Msk \ - (0x8000UL) /*!< USIC_CH PSR_SSCMode: AIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_SSCMode_BRGIF_Pos \ - (16UL) /*!< USIC_CH PSR_SSCMode: BRGIF (Bit 16) */ -#define USIC_CH_PSR_SSCMode_BRGIF_Msk \ - (0x10000UL) /*!< USIC_CH PSR_SSCMode: BRGIF (Bitfield-Mask: 0x01) */ - -/* ----------------------------- USIC_CH_PSR_IICMode ---------------------------- */ -#define USIC_CH_PSR_IICMode_SLSEL_Pos \ - (0UL) /*!< USIC_CH PSR_IICMode: SLSEL (Bit 0) */ -#define USIC_CH_PSR_IICMode_SLSEL_Msk \ - (0x1UL) /*!< USIC_CH PSR_IICMode: SLSEL (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IICMode_WTDF_Pos \ - (1UL) /*!< USIC_CH PSR_IICMode: WTDF (Bit 1) */ -#define USIC_CH_PSR_IICMode_WTDF_Msk \ - (0x2UL) /*!< USIC_CH PSR_IICMode: WTDF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IICMode_SCR_Pos \ - (2UL) /*!< USIC_CH PSR_IICMode: SCR (Bit 2) */ -#define USIC_CH_PSR_IICMode_SCR_Msk \ - (0x4UL) /*!< USIC_CH PSR_IICMode: SCR (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IICMode_RSCR_Pos \ - (3UL) /*!< USIC_CH PSR_IICMode: RSCR (Bit 3) */ -#define USIC_CH_PSR_IICMode_RSCR_Msk \ - (0x8UL) /*!< USIC_CH PSR_IICMode: RSCR (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IICMode_PCR_Pos \ - (4UL) /*!< USIC_CH PSR_IICMode: PCR (Bit 4) */ -#define USIC_CH_PSR_IICMode_PCR_Msk \ - (0x10UL) /*!< USIC_CH PSR_IICMode: PCR (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IICMode_NACK_Pos \ - (5UL) /*!< USIC_CH PSR_IICMode: NACK (Bit 5) */ -#define USIC_CH_PSR_IICMode_NACK_Msk \ - (0x20UL) /*!< USIC_CH PSR_IICMode: NACK (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IICMode_ARL_Pos \ - (6UL) /*!< USIC_CH PSR_IICMode: ARL (Bit 6) */ -#define USIC_CH_PSR_IICMode_ARL_Msk \ - (0x40UL) /*!< USIC_CH PSR_IICMode: ARL (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IICMode_SRR_Pos \ - (7UL) /*!< USIC_CH PSR_IICMode: SRR (Bit 7) */ -#define USIC_CH_PSR_IICMode_SRR_Msk \ - (0x80UL) /*!< USIC_CH PSR_IICMode: SRR (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IICMode_ERR_Pos \ - (8UL) /*!< USIC_CH PSR_IICMode: ERR (Bit 8) */ -#define USIC_CH_PSR_IICMode_ERR_Msk \ - (0x100UL) /*!< USIC_CH PSR_IICMode: ERR (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IICMode_ACK_Pos \ - (9UL) /*!< USIC_CH PSR_IICMode: ACK (Bit 9) */ -#define USIC_CH_PSR_IICMode_ACK_Msk \ - (0x200UL) /*!< USIC_CH PSR_IICMode: ACK (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IICMode_RSIF_Pos \ - (10UL) /*!< USIC_CH PSR_IICMode: RSIF (Bit 10) */ -#define USIC_CH_PSR_IICMode_RSIF_Msk \ - (0x400UL) /*!< USIC_CH PSR_IICMode: RSIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IICMode_DLIF_Pos \ - (11UL) /*!< USIC_CH PSR_IICMode: DLIF (Bit 11) */ -#define USIC_CH_PSR_IICMode_DLIF_Msk \ - (0x800UL) /*!< USIC_CH PSR_IICMode: DLIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IICMode_TSIF_Pos \ - (12UL) /*!< USIC_CH PSR_IICMode: TSIF (Bit 12) */ -#define USIC_CH_PSR_IICMode_TSIF_Msk \ - (0x1000UL) /*!< USIC_CH PSR_IICMode: TSIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IICMode_TBIF_Pos \ - (13UL) /*!< USIC_CH PSR_IICMode: TBIF (Bit 13) */ -#define USIC_CH_PSR_IICMode_TBIF_Msk \ - (0x2000UL) /*!< USIC_CH PSR_IICMode: TBIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IICMode_RIF_Pos \ - (14UL) /*!< USIC_CH PSR_IICMode: RIF (Bit 14) */ -#define USIC_CH_PSR_IICMode_RIF_Msk \ - (0x4000UL) /*!< USIC_CH PSR_IICMode: RIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IICMode_AIF_Pos \ - (15UL) /*!< USIC_CH PSR_IICMode: AIF (Bit 15) */ -#define USIC_CH_PSR_IICMode_AIF_Msk \ - (0x8000UL) /*!< USIC_CH PSR_IICMode: AIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IICMode_BRGIF_Pos \ - (16UL) /*!< USIC_CH PSR_IICMode: BRGIF (Bit 16) */ -#define USIC_CH_PSR_IICMode_BRGIF_Msk \ - (0x10000UL) /*!< USIC_CH PSR_IICMode: BRGIF (Bitfield-Mask: 0x01) */ - -/* ----------------------------- USIC_CH_PSR_IISMode ---------------------------- */ -#define USIC_CH_PSR_IISMode_WA_Pos \ - (0UL) /*!< USIC_CH PSR_IISMode: WA (Bit 0) */ -#define USIC_CH_PSR_IISMode_WA_Msk \ - (0x1UL) /*!< USIC_CH PSR_IISMode: WA (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IISMode_DX2S_Pos \ - (1UL) /*!< USIC_CH PSR_IISMode: DX2S (Bit 1) */ -#define USIC_CH_PSR_IISMode_DX2S_Msk \ - (0x2UL) /*!< USIC_CH PSR_IISMode: DX2S (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IISMode_DX2TEV_Pos \ - (3UL) /*!< USIC_CH PSR_IISMode: DX2TEV (Bit 3) */ -#define USIC_CH_PSR_IISMode_DX2TEV_Msk \ - (0x8UL) /*!< USIC_CH PSR_IISMode: DX2TEV (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IISMode_WAFE_Pos \ - (4UL) /*!< USIC_CH PSR_IISMode: WAFE (Bit 4) */ -#define USIC_CH_PSR_IISMode_WAFE_Msk \ - (0x10UL) /*!< USIC_CH PSR_IISMode: WAFE (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IISMode_WARE_Pos \ - (5UL) /*!< USIC_CH PSR_IISMode: WARE (Bit 5) */ -#define USIC_CH_PSR_IISMode_WARE_Msk \ - (0x20UL) /*!< USIC_CH PSR_IISMode: WARE (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IISMode_END_Pos \ - (6UL) /*!< USIC_CH PSR_IISMode: END (Bit 6) */ -#define USIC_CH_PSR_IISMode_END_Msk \ - (0x40UL) /*!< USIC_CH PSR_IISMode: END (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IISMode_RSIF_Pos \ - (10UL) /*!< USIC_CH PSR_IISMode: RSIF (Bit 10) */ -#define USIC_CH_PSR_IISMode_RSIF_Msk \ - (0x400UL) /*!< USIC_CH PSR_IISMode: RSIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IISMode_DLIF_Pos \ - (11UL) /*!< USIC_CH PSR_IISMode: DLIF (Bit 11) */ -#define USIC_CH_PSR_IISMode_DLIF_Msk \ - (0x800UL) /*!< USIC_CH PSR_IISMode: DLIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IISMode_TSIF_Pos \ - (12UL) /*!< USIC_CH PSR_IISMode: TSIF (Bit 12) */ -#define USIC_CH_PSR_IISMode_TSIF_Msk \ - (0x1000UL) /*!< USIC_CH PSR_IISMode: TSIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IISMode_TBIF_Pos \ - (13UL) /*!< USIC_CH PSR_IISMode: TBIF (Bit 13) */ -#define USIC_CH_PSR_IISMode_TBIF_Msk \ - (0x2000UL) /*!< USIC_CH PSR_IISMode: TBIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IISMode_RIF_Pos \ - (14UL) /*!< USIC_CH PSR_IISMode: RIF (Bit 14) */ -#define USIC_CH_PSR_IISMode_RIF_Msk \ - (0x4000UL) /*!< USIC_CH PSR_IISMode: RIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IISMode_AIF_Pos \ - (15UL) /*!< USIC_CH PSR_IISMode: AIF (Bit 15) */ -#define USIC_CH_PSR_IISMode_AIF_Msk \ - (0x8000UL) /*!< USIC_CH PSR_IISMode: AIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSR_IISMode_BRGIF_Pos \ - (16UL) /*!< USIC_CH PSR_IISMode: BRGIF (Bit 16) */ -#define USIC_CH_PSR_IISMode_BRGIF_Msk \ - (0x10000UL) /*!< USIC_CH PSR_IISMode: BRGIF (Bitfield-Mask: 0x01) */ - -/* -------------------------------- USIC_CH_PSCR -------------------------------- */ -#define USIC_CH_PSCR_CST0_Pos \ - (0UL) /*!< USIC_CH PSCR: CST0 (Bit 0) */ -#define USIC_CH_PSCR_CST0_Msk \ - (0x1UL) /*!< USIC_CH PSCR: CST0 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSCR_CST1_Pos \ - (1UL) /*!< USIC_CH PSCR: CST1 (Bit 1) */ -#define USIC_CH_PSCR_CST1_Msk \ - (0x2UL) /*!< USIC_CH PSCR: CST1 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSCR_CST2_Pos \ - (2UL) /*!< USIC_CH PSCR: CST2 (Bit 2) */ -#define USIC_CH_PSCR_CST2_Msk \ - (0x4UL) /*!< USIC_CH PSCR: CST2 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSCR_CST3_Pos \ - (3UL) /*!< USIC_CH PSCR: CST3 (Bit 3) */ -#define USIC_CH_PSCR_CST3_Msk \ - (0x8UL) /*!< USIC_CH PSCR: CST3 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSCR_CST4_Pos \ - (4UL) /*!< USIC_CH PSCR: CST4 (Bit 4) */ -#define USIC_CH_PSCR_CST4_Msk \ - (0x10UL) /*!< USIC_CH PSCR: CST4 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSCR_CST5_Pos \ - (5UL) /*!< USIC_CH PSCR: CST5 (Bit 5) */ -#define USIC_CH_PSCR_CST5_Msk \ - (0x20UL) /*!< USIC_CH PSCR: CST5 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSCR_CST6_Pos \ - (6UL) /*!< USIC_CH PSCR: CST6 (Bit 6) */ -#define USIC_CH_PSCR_CST6_Msk \ - (0x40UL) /*!< USIC_CH PSCR: CST6 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSCR_CST7_Pos \ - (7UL) /*!< USIC_CH PSCR: CST7 (Bit 7) */ -#define USIC_CH_PSCR_CST7_Msk \ - (0x80UL) /*!< USIC_CH PSCR: CST7 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSCR_CST8_Pos \ - (8UL) /*!< USIC_CH PSCR: CST8 (Bit 8) */ -#define USIC_CH_PSCR_CST8_Msk \ - (0x100UL) /*!< USIC_CH PSCR: CST8 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSCR_CST9_Pos \ - (9UL) /*!< USIC_CH PSCR: CST9 (Bit 9) */ -#define USIC_CH_PSCR_CST9_Msk \ - (0x200UL) /*!< USIC_CH PSCR: CST9 (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSCR_CRSIF_Pos \ - (10UL) /*!< USIC_CH PSCR: CRSIF (Bit 10) */ -#define USIC_CH_PSCR_CRSIF_Msk \ - (0x400UL) /*!< USIC_CH PSCR: CRSIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSCR_CDLIF_Pos \ - (11UL) /*!< USIC_CH PSCR: CDLIF (Bit 11) */ -#define USIC_CH_PSCR_CDLIF_Msk \ - (0x800UL) /*!< USIC_CH PSCR: CDLIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSCR_CTSIF_Pos \ - (12UL) /*!< USIC_CH PSCR: CTSIF (Bit 12) */ -#define USIC_CH_PSCR_CTSIF_Msk \ - (0x1000UL) /*!< USIC_CH PSCR: CTSIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSCR_CTBIF_Pos \ - (13UL) /*!< USIC_CH PSCR: CTBIF (Bit 13) */ -#define USIC_CH_PSCR_CTBIF_Msk \ - (0x2000UL) /*!< USIC_CH PSCR: CTBIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSCR_CRIF_Pos \ - (14UL) /*!< USIC_CH PSCR: CRIF (Bit 14) */ -#define USIC_CH_PSCR_CRIF_Msk \ - (0x4000UL) /*!< USIC_CH PSCR: CRIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSCR_CAIF_Pos \ - (15UL) /*!< USIC_CH PSCR: CAIF (Bit 15) */ -#define USIC_CH_PSCR_CAIF_Msk \ - (0x8000UL) /*!< USIC_CH PSCR: CAIF (Bitfield-Mask: 0x01) */ -#define USIC_CH_PSCR_CBRGIF_Pos \ - (16UL) /*!< USIC_CH PSCR: CBRGIF (Bit 16) */ -#define USIC_CH_PSCR_CBRGIF_Msk \ - (0x10000UL) /*!< USIC_CH PSCR: CBRGIF (Bitfield-Mask: 0x01) */ - -/* ------------------------------- USIC_CH_RBUFSR ------------------------------- */ -#define USIC_CH_RBUFSR_WLEN_Pos \ - (0UL) /*!< USIC_CH RBUFSR: WLEN (Bit 0) */ -#define USIC_CH_RBUFSR_WLEN_Msk \ - (0xfUL) /*!< USIC_CH RBUFSR: WLEN (Bitfield-Mask: 0x0f) */ -#define USIC_CH_RBUFSR_SOF_Pos \ - (6UL) /*!< USIC_CH RBUFSR: SOF (Bit 6) */ -#define USIC_CH_RBUFSR_SOF_Msk \ - (0x40UL) /*!< USIC_CH RBUFSR: SOF (Bitfield-Mask: 0x01) */ -#define USIC_CH_RBUFSR_PAR_Pos \ - (8UL) /*!< USIC_CH RBUFSR: PAR (Bit 8) */ -#define USIC_CH_RBUFSR_PAR_Msk \ - (0x100UL) /*!< USIC_CH RBUFSR: PAR (Bitfield-Mask: 0x01) */ -#define USIC_CH_RBUFSR_PERR_Pos \ - (9UL) /*!< USIC_CH RBUFSR: PERR (Bit 9) */ -#define USIC_CH_RBUFSR_PERR_Msk \ - (0x200UL) /*!< USIC_CH RBUFSR: PERR (Bitfield-Mask: 0x01) */ -#define USIC_CH_RBUFSR_RDV0_Pos \ - (13UL) /*!< USIC_CH RBUFSR: RDV0 (Bit 13) */ -#define USIC_CH_RBUFSR_RDV0_Msk \ - (0x2000UL) /*!< USIC_CH RBUFSR: RDV0 (Bitfield-Mask: 0x01) */ -#define USIC_CH_RBUFSR_RDV1_Pos \ - (14UL) /*!< USIC_CH RBUFSR: RDV1 (Bit 14) */ -#define USIC_CH_RBUFSR_RDV1_Msk \ - (0x4000UL) /*!< USIC_CH RBUFSR: RDV1 (Bitfield-Mask: 0x01) */ -#define USIC_CH_RBUFSR_DS_Pos \ - (15UL) /*!< USIC_CH RBUFSR: DS (Bit 15) */ -#define USIC_CH_RBUFSR_DS_Msk \ - (0x8000UL) /*!< USIC_CH RBUFSR: DS (Bitfield-Mask: 0x01) */ - -/* -------------------------------- USIC_CH_RBUF -------------------------------- */ -#define USIC_CH_RBUF_DSR_Pos \ - (0UL) /*!< USIC_CH RBUF: DSR (Bit 0) */ -#define USIC_CH_RBUF_DSR_Msk \ - (0xffffUL) /*!< USIC_CH RBUF: DSR (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- USIC_CH_RBUFD ------------------------------- */ -#define USIC_CH_RBUFD_DSR_Pos \ - (0UL) /*!< USIC_CH RBUFD: DSR (Bit 0) */ -#define USIC_CH_RBUFD_DSR_Msk \ - (0xffffUL) /*!< USIC_CH RBUFD: DSR (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- USIC_CH_RBUF0 ------------------------------- */ -#define USIC_CH_RBUF0_DSR0_Pos \ - (0UL) /*!< USIC_CH RBUF0: DSR0 (Bit 0) */ -#define USIC_CH_RBUF0_DSR0_Msk \ - (0xffffUL) /*!< USIC_CH RBUF0: DSR0 (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- USIC_CH_RBUF1 ------------------------------- */ -#define USIC_CH_RBUF1_DSR1_Pos \ - (0UL) /*!< USIC_CH RBUF1: DSR1 (Bit 0) */ -#define USIC_CH_RBUF1_DSR1_Msk \ - (0xffffUL) /*!< USIC_CH RBUF1: DSR1 (Bitfield-Mask: 0xffff) */ - -/* ------------------------------ USIC_CH_RBUF01SR ------------------------------ */ -#define USIC_CH_RBUF01SR_WLEN0_Pos \ - (0UL) /*!< USIC_CH RBUF01SR: WLEN0 (Bit 0) */ -#define USIC_CH_RBUF01SR_WLEN0_Msk \ - (0xfUL) /*!< USIC_CH RBUF01SR: WLEN0 (Bitfield-Mask: 0x0f) */ -#define USIC_CH_RBUF01SR_SOF0_Pos \ - (6UL) /*!< USIC_CH RBUF01SR: SOF0 (Bit 6) */ -#define USIC_CH_RBUF01SR_SOF0_Msk \ - (0x40UL) /*!< USIC_CH RBUF01SR: SOF0 (Bitfield-Mask: 0x01) */ -#define USIC_CH_RBUF01SR_PAR0_Pos \ - (8UL) /*!< USIC_CH RBUF01SR: PAR0 (Bit 8) */ -#define USIC_CH_RBUF01SR_PAR0_Msk \ - (0x100UL) /*!< USIC_CH RBUF01SR: PAR0 (Bitfield-Mask: 0x01) */ -#define USIC_CH_RBUF01SR_PERR0_Pos \ - (9UL) /*!< USIC_CH RBUF01SR: PERR0 (Bit 9) */ -#define USIC_CH_RBUF01SR_PERR0_Msk \ - (0x200UL) /*!< USIC_CH RBUF01SR: PERR0 (Bitfield-Mask: 0x01) */ -#define USIC_CH_RBUF01SR_RDV00_Pos \ - (13UL) /*!< USIC_CH RBUF01SR: RDV00 (Bit 13) */ -#define USIC_CH_RBUF01SR_RDV00_Msk \ - (0x2000UL) /*!< USIC_CH RBUF01SR: RDV00 (Bitfield-Mask: 0x01) */ -#define USIC_CH_RBUF01SR_RDV01_Pos \ - (14UL) /*!< USIC_CH RBUF01SR: RDV01 (Bit 14) */ -#define USIC_CH_RBUF01SR_RDV01_Msk \ - (0x4000UL) /*!< USIC_CH RBUF01SR: RDV01 (Bitfield-Mask: 0x01) */ -#define USIC_CH_RBUF01SR_DS0_Pos \ - (15UL) /*!< USIC_CH RBUF01SR: DS0 (Bit 15) */ -#define USIC_CH_RBUF01SR_DS0_Msk \ - (0x8000UL) /*!< USIC_CH RBUF01SR: DS0 (Bitfield-Mask: 0x01) */ -#define USIC_CH_RBUF01SR_WLEN1_Pos \ - (16UL) /*!< USIC_CH RBUF01SR: WLEN1 (Bit 16) */ -#define USIC_CH_RBUF01SR_WLEN1_Msk \ - (0xf0000UL) /*!< USIC_CH RBUF01SR: WLEN1 (Bitfield-Mask: 0x0f) */ -#define USIC_CH_RBUF01SR_SOF1_Pos \ - (22UL) /*!< USIC_CH RBUF01SR: SOF1 (Bit 22) */ -#define USIC_CH_RBUF01SR_SOF1_Msk \ - (0x400000UL) /*!< USIC_CH RBUF01SR: SOF1 (Bitfield-Mask: 0x01) */ -#define USIC_CH_RBUF01SR_PAR1_Pos \ - (24UL) /*!< USIC_CH RBUF01SR: PAR1 (Bit 24) */ -#define USIC_CH_RBUF01SR_PAR1_Msk \ - (0x1000000UL) /*!< USIC_CH RBUF01SR: PAR1 (Bitfield-Mask: 0x01) */ -#define USIC_CH_RBUF01SR_PERR1_Pos \ - (25UL) /*!< USIC_CH RBUF01SR: PERR1 (Bit 25) */ -#define USIC_CH_RBUF01SR_PERR1_Msk \ - (0x2000000UL) /*!< USIC_CH RBUF01SR: PERR1 (Bitfield-Mask: 0x01) */ -#define USIC_CH_RBUF01SR_RDV10_Pos \ - (29UL) /*!< USIC_CH RBUF01SR: RDV10 (Bit 29) */ -#define USIC_CH_RBUF01SR_RDV10_Msk \ - (0x20000000UL) /*!< USIC_CH RBUF01SR: RDV10 (Bitfield-Mask: 0x01) */ -#define USIC_CH_RBUF01SR_RDV11_Pos \ - (30UL) /*!< USIC_CH RBUF01SR: RDV11 (Bit 30) */ -#define USIC_CH_RBUF01SR_RDV11_Msk \ - (0x40000000UL) /*!< USIC_CH RBUF01SR: RDV11 (Bitfield-Mask: 0x01) */ -#define USIC_CH_RBUF01SR_DS1_Pos \ - (31UL) /*!< USIC_CH RBUF01SR: DS1 (Bit 31) */ -#define USIC_CH_RBUF01SR_DS1_Msk \ - (0x80000000UL) /*!< USIC_CH RBUF01SR: DS1 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- USIC_CH_FMR -------------------------------- */ -#define USIC_CH_FMR_MTDV_Pos \ - (0UL) /*!< USIC_CH FMR: MTDV (Bit 0) */ -#define USIC_CH_FMR_MTDV_Msk \ - (0x3UL) /*!< USIC_CH FMR: MTDV (Bitfield-Mask: 0x03) */ -#define USIC_CH_FMR_ATVC_Pos \ - (4UL) /*!< USIC_CH FMR: ATVC (Bit 4) */ -#define USIC_CH_FMR_ATVC_Msk \ - (0x10UL) /*!< USIC_CH FMR: ATVC (Bitfield-Mask: 0x01) */ -#define USIC_CH_FMR_CRDV0_Pos \ - (14UL) /*!< USIC_CH FMR: CRDV0 (Bit 14) */ -#define USIC_CH_FMR_CRDV0_Msk \ - (0x4000UL) /*!< USIC_CH FMR: CRDV0 (Bitfield-Mask: 0x01) */ -#define USIC_CH_FMR_CRDV1_Pos \ - (15UL) /*!< USIC_CH FMR: CRDV1 (Bit 15) */ -#define USIC_CH_FMR_CRDV1_Msk \ - (0x8000UL) /*!< USIC_CH FMR: CRDV1 (Bitfield-Mask: 0x01) */ -#define USIC_CH_FMR_SIO0_Pos \ - (16UL) /*!< USIC_CH FMR: SIO0 (Bit 16) */ -#define USIC_CH_FMR_SIO0_Msk \ - (0x10000UL) /*!< USIC_CH FMR: SIO0 (Bitfield-Mask: 0x01) */ -#define USIC_CH_FMR_SIO1_Pos \ - (17UL) /*!< USIC_CH FMR: SIO1 (Bit 17) */ -#define USIC_CH_FMR_SIO1_Msk \ - (0x20000UL) /*!< USIC_CH FMR: SIO1 (Bitfield-Mask: 0x01) */ -#define USIC_CH_FMR_SIO2_Pos \ - (18UL) /*!< USIC_CH FMR: SIO2 (Bit 18) */ -#define USIC_CH_FMR_SIO2_Msk \ - (0x40000UL) /*!< USIC_CH FMR: SIO2 (Bitfield-Mask: 0x01) */ -#define USIC_CH_FMR_SIO3_Pos \ - (19UL) /*!< USIC_CH FMR: SIO3 (Bit 19) */ -#define USIC_CH_FMR_SIO3_Msk \ - (0x80000UL) /*!< USIC_CH FMR: SIO3 (Bitfield-Mask: 0x01) */ -#define USIC_CH_FMR_SIO4_Pos \ - (20UL) /*!< USIC_CH FMR: SIO4 (Bit 20) */ -#define USIC_CH_FMR_SIO4_Msk \ - (0x100000UL) /*!< USIC_CH FMR: SIO4 (Bitfield-Mask: 0x01) */ -#define USIC_CH_FMR_SIO5_Pos \ - (21UL) /*!< USIC_CH FMR: SIO5 (Bit 21) */ -#define USIC_CH_FMR_SIO5_Msk \ - (0x200000UL) /*!< USIC_CH FMR: SIO5 (Bitfield-Mask: 0x01) */ - -/* -------------------------------- USIC_CH_TBUF -------------------------------- */ -#define USIC_CH_TBUF_TDATA_Pos \ - (0UL) /*!< USIC_CH TBUF: TDATA (Bit 0) */ -#define USIC_CH_TBUF_TDATA_Msk \ - (0xffffUL) /*!< USIC_CH TBUF: TDATA (Bitfield-Mask: 0xffff) */ - -/* --------------------------------- USIC_CH_BYP -------------------------------- */ -#define USIC_CH_BYP_BDATA_Pos \ - (0UL) /*!< USIC_CH BYP: BDATA (Bit 0) */ -#define USIC_CH_BYP_BDATA_Msk \ - (0xffffUL) /*!< USIC_CH BYP: BDATA (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- USIC_CH_BYPCR ------------------------------- */ -#define USIC_CH_BYPCR_BWLE_Pos \ - (0UL) /*!< USIC_CH BYPCR: BWLE (Bit 0) */ -#define USIC_CH_BYPCR_BWLE_Msk \ - (0xfUL) /*!< USIC_CH BYPCR: BWLE (Bitfield-Mask: 0x0f) */ -#define USIC_CH_BYPCR_BDSSM_Pos \ - (8UL) /*!< USIC_CH BYPCR: BDSSM (Bit 8) */ -#define USIC_CH_BYPCR_BDSSM_Msk \ - (0x100UL) /*!< USIC_CH BYPCR: BDSSM (Bitfield-Mask: 0x01) */ -#define USIC_CH_BYPCR_BDEN_Pos \ - (10UL) /*!< USIC_CH BYPCR: BDEN (Bit 10) */ -#define USIC_CH_BYPCR_BDEN_Msk \ - (0xc00UL) /*!< USIC_CH BYPCR: BDEN (Bitfield-Mask: 0x03) */ -#define USIC_CH_BYPCR_BDVTR_Pos \ - (12UL) /*!< USIC_CH BYPCR: BDVTR (Bit 12) */ -#define USIC_CH_BYPCR_BDVTR_Msk \ - (0x1000UL) /*!< USIC_CH BYPCR: BDVTR (Bitfield-Mask: 0x01) */ -#define USIC_CH_BYPCR_BPRIO_Pos \ - (13UL) /*!< USIC_CH BYPCR: BPRIO (Bit 13) */ -#define USIC_CH_BYPCR_BPRIO_Msk \ - (0x2000UL) /*!< USIC_CH BYPCR: BPRIO (Bitfield-Mask: 0x01) */ -#define USIC_CH_BYPCR_BDV_Pos \ - (15UL) /*!< USIC_CH BYPCR: BDV (Bit 15) */ -#define USIC_CH_BYPCR_BDV_Msk \ - (0x8000UL) /*!< USIC_CH BYPCR: BDV (Bitfield-Mask: 0x01) */ -#define USIC_CH_BYPCR_BSELO_Pos \ - (16UL) /*!< USIC_CH BYPCR: BSELO (Bit 16) */ -#define USIC_CH_BYPCR_BSELO_Msk \ - (0x1f0000UL) /*!< USIC_CH BYPCR: BSELO (Bitfield-Mask: 0x1f) */ -#define USIC_CH_BYPCR_BHPC_Pos \ - (21UL) /*!< USIC_CH BYPCR: BHPC (Bit 21) */ -#define USIC_CH_BYPCR_BHPC_Msk \ - (0xe00000UL) /*!< USIC_CH BYPCR: BHPC (Bitfield-Mask: 0x07) */ - -/* -------------------------------- USIC_CH_TBCTR ------------------------------- */ -#define USIC_CH_TBCTR_DPTR_Pos \ - (0UL) /*!< USIC_CH TBCTR: DPTR (Bit 0) */ -#define USIC_CH_TBCTR_DPTR_Msk \ - (0x3fUL) /*!< USIC_CH TBCTR: DPTR (Bitfield-Mask: 0x3f) */ -#define USIC_CH_TBCTR_LIMIT_Pos \ - (8UL) /*!< USIC_CH TBCTR: LIMIT (Bit 8) */ -#define USIC_CH_TBCTR_LIMIT_Msk \ - (0x3f00UL) /*!< USIC_CH TBCTR: LIMIT (Bitfield-Mask: 0x3f) */ -#define USIC_CH_TBCTR_STBTM_Pos \ - (14UL) /*!< USIC_CH TBCTR: STBTM (Bit 14) */ -#define USIC_CH_TBCTR_STBTM_Msk \ - (0x4000UL) /*!< USIC_CH TBCTR: STBTM (Bitfield-Mask: 0x01) */ -#define USIC_CH_TBCTR_STBTEN_Pos \ - (15UL) /*!< USIC_CH TBCTR: STBTEN (Bit 15) */ -#define USIC_CH_TBCTR_STBTEN_Msk \ - (0x8000UL) /*!< USIC_CH TBCTR: STBTEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_TBCTR_STBINP_Pos \ - (16UL) /*!< USIC_CH TBCTR: STBINP (Bit 16) */ -#define USIC_CH_TBCTR_STBINP_Msk \ - (0x70000UL) /*!< USIC_CH TBCTR: STBINP (Bitfield-Mask: 0x07) */ -#define USIC_CH_TBCTR_ATBINP_Pos \ - (19UL) /*!< USIC_CH TBCTR: ATBINP (Bit 19) */ -#define USIC_CH_TBCTR_ATBINP_Msk \ - (0x380000UL) /*!< USIC_CH TBCTR: ATBINP (Bitfield-Mask: 0x07) */ -#define USIC_CH_TBCTR_SIZE_Pos \ - (24UL) /*!< USIC_CH TBCTR: SIZE (Bit 24) */ -#define USIC_CH_TBCTR_SIZE_Msk \ - (0x7000000UL) /*!< USIC_CH TBCTR: SIZE (Bitfield-Mask: 0x07) */ -#define USIC_CH_TBCTR_LOF_Pos \ - (28UL) /*!< USIC_CH TBCTR: LOF (Bit 28) */ -#define USIC_CH_TBCTR_LOF_Msk \ - (0x10000000UL) /*!< USIC_CH TBCTR: LOF (Bitfield-Mask: 0x01) */ -#define USIC_CH_TBCTR_STBIEN_Pos \ - (30UL) /*!< USIC_CH TBCTR: STBIEN (Bit 30) */ -#define USIC_CH_TBCTR_STBIEN_Msk \ - (0x40000000UL) /*!< USIC_CH TBCTR: STBIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_TBCTR_TBERIEN_Pos \ - (31UL) /*!< USIC_CH TBCTR: TBERIEN (Bit 31) */ -#define USIC_CH_TBCTR_TBERIEN_Msk \ - (0x80000000UL) /*!< USIC_CH TBCTR: TBERIEN (Bitfield-Mask: 0x01) */ - -/* -------------------------------- USIC_CH_RBCTR ------------------------------- */ -#define USIC_CH_RBCTR_DPTR_Pos \ - (0UL) /*!< USIC_CH RBCTR: DPTR (Bit 0) */ -#define USIC_CH_RBCTR_DPTR_Msk \ - (0x3fUL) /*!< USIC_CH RBCTR: DPTR (Bitfield-Mask: 0x3f) */ -#define USIC_CH_RBCTR_LIMIT_Pos \ - (8UL) /*!< USIC_CH RBCTR: LIMIT (Bit 8) */ -#define USIC_CH_RBCTR_LIMIT_Msk \ - (0x3f00UL) /*!< USIC_CH RBCTR: LIMIT (Bitfield-Mask: 0x3f) */ -#define USIC_CH_RBCTR_SRBTM_Pos \ - (14UL) /*!< USIC_CH RBCTR: SRBTM (Bit 14) */ -#define USIC_CH_RBCTR_SRBTM_Msk \ - (0x4000UL) /*!< USIC_CH RBCTR: SRBTM (Bitfield-Mask: 0x01) */ -#define USIC_CH_RBCTR_SRBTEN_Pos \ - (15UL) /*!< USIC_CH RBCTR: SRBTEN (Bit 15) */ -#define USIC_CH_RBCTR_SRBTEN_Msk \ - (0x8000UL) /*!< USIC_CH RBCTR: SRBTEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_RBCTR_SRBINP_Pos \ - (16UL) /*!< USIC_CH RBCTR: SRBINP (Bit 16) */ -#define USIC_CH_RBCTR_SRBINP_Msk \ - (0x70000UL) /*!< USIC_CH RBCTR: SRBINP (Bitfield-Mask: 0x07) */ -#define USIC_CH_RBCTR_ARBINP_Pos \ - (19UL) /*!< USIC_CH RBCTR: ARBINP (Bit 19) */ -#define USIC_CH_RBCTR_ARBINP_Msk \ - (0x380000UL) /*!< USIC_CH RBCTR: ARBINP (Bitfield-Mask: 0x07) */ -#define USIC_CH_RBCTR_RCIM_Pos \ - (22UL) /*!< USIC_CH RBCTR: RCIM (Bit 22) */ -#define USIC_CH_RBCTR_RCIM_Msk \ - (0xc00000UL) /*!< USIC_CH RBCTR: RCIM (Bitfield-Mask: 0x03) */ -#define USIC_CH_RBCTR_SIZE_Pos \ - (24UL) /*!< USIC_CH RBCTR: SIZE (Bit 24) */ -#define USIC_CH_RBCTR_SIZE_Msk \ - (0x7000000UL) /*!< USIC_CH RBCTR: SIZE (Bitfield-Mask: 0x07) */ -#define USIC_CH_RBCTR_RNM_Pos \ - (27UL) /*!< USIC_CH RBCTR: RNM (Bit 27) */ -#define USIC_CH_RBCTR_RNM_Msk \ - (0x8000000UL) /*!< USIC_CH RBCTR: RNM (Bitfield-Mask: 0x01) */ -#define USIC_CH_RBCTR_LOF_Pos \ - (28UL) /*!< USIC_CH RBCTR: LOF (Bit 28) */ -#define USIC_CH_RBCTR_LOF_Msk \ - (0x10000000UL) /*!< USIC_CH RBCTR: LOF (Bitfield-Mask: 0x01) */ -#define USIC_CH_RBCTR_ARBIEN_Pos \ - (29UL) /*!< USIC_CH RBCTR: ARBIEN (Bit 29) */ -#define USIC_CH_RBCTR_ARBIEN_Msk \ - (0x20000000UL) /*!< USIC_CH RBCTR: ARBIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_RBCTR_SRBIEN_Pos \ - (30UL) /*!< USIC_CH RBCTR: SRBIEN (Bit 30) */ -#define USIC_CH_RBCTR_SRBIEN_Msk \ - (0x40000000UL) /*!< USIC_CH RBCTR: SRBIEN (Bitfield-Mask: 0x01) */ -#define USIC_CH_RBCTR_RBERIEN_Pos \ - (31UL) /*!< USIC_CH RBCTR: RBERIEN (Bit 31) */ -#define USIC_CH_RBCTR_RBERIEN_Msk \ - (0x80000000UL) /*!< USIC_CH RBCTR: RBERIEN (Bitfield-Mask: 0x01) */ - -/* ------------------------------- USIC_CH_TRBPTR ------------------------------- */ -#define USIC_CH_TRBPTR_TDIPTR_Pos \ - (0UL) /*!< USIC_CH TRBPTR: TDIPTR (Bit 0) */ -#define USIC_CH_TRBPTR_TDIPTR_Msk \ - (0x3fUL) /*!< USIC_CH TRBPTR: TDIPTR (Bitfield-Mask: 0x3f) */ -#define USIC_CH_TRBPTR_TDOPTR_Pos \ - (8UL) /*!< USIC_CH TRBPTR: TDOPTR (Bit 8) */ -#define USIC_CH_TRBPTR_TDOPTR_Msk \ - (0x3f00UL) /*!< USIC_CH TRBPTR: TDOPTR (Bitfield-Mask: 0x3f) */ -#define USIC_CH_TRBPTR_RDIPTR_Pos \ - (16UL) /*!< USIC_CH TRBPTR: RDIPTR (Bit 16) */ -#define USIC_CH_TRBPTR_RDIPTR_Msk \ - (0x3f0000UL) /*!< USIC_CH TRBPTR: RDIPTR (Bitfield-Mask: 0x3f) */ -#define USIC_CH_TRBPTR_RDOPTR_Pos \ - (24UL) /*!< USIC_CH TRBPTR: RDOPTR (Bit 24) */ -#define USIC_CH_TRBPTR_RDOPTR_Msk \ - (0x3f000000UL) /*!< USIC_CH TRBPTR: RDOPTR (Bitfield-Mask: 0x3f) */ - -/* -------------------------------- USIC_CH_TRBSR ------------------------------- */ -#define USIC_CH_TRBSR_SRBI_Pos \ - (0UL) /*!< USIC_CH TRBSR: SRBI (Bit 0) */ -#define USIC_CH_TRBSR_SRBI_Msk \ - (0x1UL) /*!< USIC_CH TRBSR: SRBI (Bitfield-Mask: 0x01) */ -#define USIC_CH_TRBSR_RBERI_Pos \ - (1UL) /*!< USIC_CH TRBSR: RBERI (Bit 1) */ -#define USIC_CH_TRBSR_RBERI_Msk \ - (0x2UL) /*!< USIC_CH TRBSR: RBERI (Bitfield-Mask: 0x01) */ -#define USIC_CH_TRBSR_ARBI_Pos \ - (2UL) /*!< USIC_CH TRBSR: ARBI (Bit 2) */ -#define USIC_CH_TRBSR_ARBI_Msk \ - (0x4UL) /*!< USIC_CH TRBSR: ARBI (Bitfield-Mask: 0x01) */ -#define USIC_CH_TRBSR_REMPTY_Pos \ - (3UL) /*!< USIC_CH TRBSR: REMPTY (Bit 3) */ -#define USIC_CH_TRBSR_REMPTY_Msk \ - (0x8UL) /*!< USIC_CH TRBSR: REMPTY (Bitfield-Mask: 0x01) */ -#define USIC_CH_TRBSR_RFULL_Pos \ - (4UL) /*!< USIC_CH TRBSR: RFULL (Bit 4) */ -#define USIC_CH_TRBSR_RFULL_Msk \ - (0x10UL) /*!< USIC_CH TRBSR: RFULL (Bitfield-Mask: 0x01) */ -#define USIC_CH_TRBSR_RBUS_Pos \ - (5UL) /*!< USIC_CH TRBSR: RBUS (Bit 5) */ -#define USIC_CH_TRBSR_RBUS_Msk \ - (0x20UL) /*!< USIC_CH TRBSR: RBUS (Bitfield-Mask: 0x01) */ -#define USIC_CH_TRBSR_SRBT_Pos \ - (6UL) /*!< USIC_CH TRBSR: SRBT (Bit 6) */ -#define USIC_CH_TRBSR_SRBT_Msk \ - (0x40UL) /*!< USIC_CH TRBSR: SRBT (Bitfield-Mask: 0x01) */ -#define USIC_CH_TRBSR_STBI_Pos \ - (8UL) /*!< USIC_CH TRBSR: STBI (Bit 8) */ -#define USIC_CH_TRBSR_STBI_Msk \ - (0x100UL) /*!< USIC_CH TRBSR: STBI (Bitfield-Mask: 0x01) */ -#define USIC_CH_TRBSR_TBERI_Pos \ - (9UL) /*!< USIC_CH TRBSR: TBERI (Bit 9) */ -#define USIC_CH_TRBSR_TBERI_Msk \ - (0x200UL) /*!< USIC_CH TRBSR: TBERI (Bitfield-Mask: 0x01) */ -#define USIC_CH_TRBSR_TEMPTY_Pos \ - (11UL) /*!< USIC_CH TRBSR: TEMPTY (Bit 11) */ -#define USIC_CH_TRBSR_TEMPTY_Msk \ - (0x800UL) /*!< USIC_CH TRBSR: TEMPTY (Bitfield-Mask: 0x01) */ -#define USIC_CH_TRBSR_TFULL_Pos \ - (12UL) /*!< USIC_CH TRBSR: TFULL (Bit 12) */ -#define USIC_CH_TRBSR_TFULL_Msk \ - (0x1000UL) /*!< USIC_CH TRBSR: TFULL (Bitfield-Mask: 0x01) */ -#define USIC_CH_TRBSR_TBUS_Pos \ - (13UL) /*!< USIC_CH TRBSR: TBUS (Bit 13) */ -#define USIC_CH_TRBSR_TBUS_Msk \ - (0x2000UL) /*!< USIC_CH TRBSR: TBUS (Bitfield-Mask: 0x01) */ -#define USIC_CH_TRBSR_STBT_Pos \ - (14UL) /*!< USIC_CH TRBSR: STBT (Bit 14) */ -#define USIC_CH_TRBSR_STBT_Msk \ - (0x4000UL) /*!< USIC_CH TRBSR: STBT (Bitfield-Mask: 0x01) */ -#define USIC_CH_TRBSR_RBFLVL_Pos \ - (16UL) /*!< USIC_CH TRBSR: RBFLVL (Bit 16) */ -#define USIC_CH_TRBSR_RBFLVL_Msk \ - (0x7f0000UL) /*!< USIC_CH TRBSR: RBFLVL (Bitfield-Mask: 0x7f) */ -#define USIC_CH_TRBSR_TBFLVL_Pos \ - (24UL) /*!< USIC_CH TRBSR: TBFLVL (Bit 24) */ -#define USIC_CH_TRBSR_TBFLVL_Msk \ - (0x7f000000UL) /*!< USIC_CH TRBSR: TBFLVL (Bitfield-Mask: 0x7f) */ - -/* ------------------------------- USIC_CH_TRBSCR ------------------------------- */ -#define USIC_CH_TRBSCR_CSRBI_Pos \ - (0UL) /*!< USIC_CH TRBSCR: CSRBI (Bit 0) */ -#define USIC_CH_TRBSCR_CSRBI_Msk \ - (0x1UL) /*!< USIC_CH TRBSCR: CSRBI (Bitfield-Mask: 0x01) */ -#define USIC_CH_TRBSCR_CRBERI_Pos \ - (1UL) /*!< USIC_CH TRBSCR: CRBERI (Bit 1) */ -#define USIC_CH_TRBSCR_CRBERI_Msk \ - (0x2UL) /*!< USIC_CH TRBSCR: CRBERI (Bitfield-Mask: 0x01) */ -#define USIC_CH_TRBSCR_CARBI_Pos \ - (2UL) /*!< USIC_CH TRBSCR: CARBI (Bit 2) */ -#define USIC_CH_TRBSCR_CARBI_Msk \ - (0x4UL) /*!< USIC_CH TRBSCR: CARBI (Bitfield-Mask: 0x01) */ -#define USIC_CH_TRBSCR_CSTBI_Pos \ - (8UL) /*!< USIC_CH TRBSCR: CSTBI (Bit 8) */ -#define USIC_CH_TRBSCR_CSTBI_Msk \ - (0x100UL) /*!< USIC_CH TRBSCR: CSTBI (Bitfield-Mask: 0x01) */ -#define USIC_CH_TRBSCR_CTBERI_Pos \ - (9UL) /*!< USIC_CH TRBSCR: CTBERI (Bit 9) */ -#define USIC_CH_TRBSCR_CTBERI_Msk \ - (0x200UL) /*!< USIC_CH TRBSCR: CTBERI (Bitfield-Mask: 0x01) */ -#define USIC_CH_TRBSCR_CBDV_Pos \ - (10UL) /*!< USIC_CH TRBSCR: CBDV (Bit 10) */ -#define USIC_CH_TRBSCR_CBDV_Msk \ - (0x400UL) /*!< USIC_CH TRBSCR: CBDV (Bitfield-Mask: 0x01) */ -#define USIC_CH_TRBSCR_FLUSHRB_Pos \ - (14UL) /*!< USIC_CH TRBSCR: FLUSHRB (Bit 14) */ -#define USIC_CH_TRBSCR_FLUSHRB_Msk \ - (0x4000UL) /*!< USIC_CH TRBSCR: FLUSHRB (Bitfield-Mask: 0x01) */ -#define USIC_CH_TRBSCR_FLUSHTB_Pos \ - (15UL) /*!< USIC_CH TRBSCR: FLUSHTB (Bit 15) */ -#define USIC_CH_TRBSCR_FLUSHTB_Msk \ - (0x8000UL) /*!< USIC_CH TRBSCR: FLUSHTB (Bitfield-Mask: 0x01) */ - -/* -------------------------------- USIC_CH_OUTR -------------------------------- */ -#define USIC_CH_OUTR_DSR_Pos \ - (0UL) /*!< USIC_CH OUTR: DSR (Bit 0) */ -#define USIC_CH_OUTR_DSR_Msk \ - (0xffffUL) /*!< USIC_CH OUTR: DSR (Bitfield-Mask: 0xffff) */ -#define USIC_CH_OUTR_RCI_Pos \ - (16UL) /*!< USIC_CH OUTR: RCI (Bit 16) */ -#define USIC_CH_OUTR_RCI_Msk \ - (0x1f0000UL) /*!< USIC_CH OUTR: RCI (Bitfield-Mask: 0x1f) */ - -/* -------------------------------- USIC_CH_OUTDR ------------------------------- */ -#define USIC_CH_OUTDR_DSR_Pos \ - (0UL) /*!< USIC_CH OUTDR: DSR (Bit 0) */ -#define USIC_CH_OUTDR_DSR_Msk \ - (0xffffUL) /*!< USIC_CH OUTDR: DSR (Bitfield-Mask: 0xffff) */ -#define USIC_CH_OUTDR_RCI_Pos \ - (16UL) /*!< USIC_CH OUTDR: RCI (Bit 16) */ -#define USIC_CH_OUTDR_RCI_Msk \ - (0x1f0000UL) /*!< USIC_CH OUTDR: RCI (Bitfield-Mask: 0x1f) */ - -/* --------------------------------- USIC_CH_IN --------------------------------- */ -#define USIC_CH_IN_TDATA_Pos \ - (0UL) /*!< USIC_CH IN: TDATA (Bit 0) */ -#define USIC_CH_IN_TDATA_Msk \ - (0xffffUL) /*!< USIC_CH IN: TDATA (Bitfield-Mask: 0xffff) */ - -/* ================================================================================ */ -/* ================ struct 'CAN' Position & Mask ================ */ -/* ================================================================================ */ - -/* ----------------------------------- CAN_CLC ---------------------------------- */ -#define CAN_CLC_DISR_Pos (0UL) /*!< CAN CLC: DISR (Bit 0) */ -#define CAN_CLC_DISR_Msk (0x1UL) /*!< CAN CLC: DISR (Bitfield-Mask: 0x01) */ -#define CAN_CLC_DISS_Pos (1UL) /*!< CAN CLC: DISS (Bit 1) */ -#define CAN_CLC_DISS_Msk (0x2UL) /*!< CAN CLC: DISS (Bitfield-Mask: 0x01) */ -#define CAN_CLC_EDIS_Pos (3UL) /*!< CAN CLC: EDIS (Bit 3) */ -#define CAN_CLC_EDIS_Msk (0x8UL) /*!< CAN CLC: EDIS (Bitfield-Mask: 0x01) */ -#define CAN_CLC_SBWE_Pos (4UL) /*!< CAN CLC: SBWE (Bit 4) */ -#define CAN_CLC_SBWE_Msk \ - (0x10UL) /*!< CAN CLC: SBWE (Bitfield-Mask: 0x01) */ - -/* ----------------------------------- CAN_ID ----------------------------------- */ -#define CAN_ID_MOD_REV_Pos (0UL) /*!< CAN ID: MOD_REV (Bit 0) */ -#define CAN_ID_MOD_REV_Msk \ - (0xffUL) /*!< CAN ID: MOD_REV (Bitfield-Mask: 0xff) */ -#define CAN_ID_MOD_TYPE_Pos \ - (8UL) /*!< CAN ID: MOD_TYPE (Bit 8) */ -#define CAN_ID_MOD_TYPE_Msk \ - (0xff00UL) /*!< CAN ID: MOD_TYPE (Bitfield-Mask: 0xff) */ -#define CAN_ID_MOD_NUMBER_Pos \ - (16UL) /*!< CAN ID: MOD_NUMBER (Bit 16) */ -#define CAN_ID_MOD_NUMBER_Msk \ - (0xffff0000UL) /*!< CAN ID: MOD_NUMBER (Bitfield-Mask: 0xffff) */ - -/* ----------------------------------- CAN_FDR ---------------------------------- */ -#define CAN_FDR_STEP_Pos (0UL) /*!< CAN FDR: STEP (Bit 0) */ -#define CAN_FDR_STEP_Msk \ - (0x3ffUL) /*!< CAN FDR: STEP (Bitfield-Mask: 0x3ff) */ -#define CAN_FDR_SM_Pos (11UL) /*!< CAN FDR: SM (Bit 11) */ -#define CAN_FDR_SM_Msk (0x800UL) /*!< CAN FDR: SM (Bitfield-Mask: 0x01) */ -#define CAN_FDR_SC_Pos (12UL) /*!< CAN FDR: SC (Bit 12) */ -#define CAN_FDR_SC_Msk \ - (0x3000UL) /*!< CAN FDR: SC (Bitfield-Mask: 0x03) */ -#define CAN_FDR_DM_Pos (14UL) /*!< CAN FDR: DM (Bit 14) */ -#define CAN_FDR_DM_Msk \ - (0xc000UL) /*!< CAN FDR: DM (Bitfield-Mask: 0x03) */ -#define CAN_FDR_RESULT_Pos \ - (16UL) /*!< CAN FDR: RESULT (Bit 16) */ -#define CAN_FDR_RESULT_Msk \ - (0x3ff0000UL) /*!< CAN FDR: RESULT (Bitfield-Mask: 0x3ff) */ -#define CAN_FDR_SUSACK_Pos \ - (28UL) /*!< CAN FDR: SUSACK (Bit 28) */ -#define CAN_FDR_SUSACK_Msk \ - (0x10000000UL) /*!< CAN FDR: SUSACK (Bitfield-Mask: 0x01) */ -#define CAN_FDR_SUSREQ_Pos \ - (29UL) /*!< CAN FDR: SUSREQ (Bit 29) */ -#define CAN_FDR_SUSREQ_Msk \ - (0x20000000UL) /*!< CAN FDR: SUSREQ (Bitfield-Mask: 0x01) */ -#define CAN_FDR_ENHW_Pos (30UL) /*!< CAN FDR: ENHW (Bit 30) */ -#define CAN_FDR_ENHW_Msk \ - (0x40000000UL) /*!< CAN FDR: ENHW (Bitfield-Mask: 0x01) */ -#define CAN_FDR_DISCLK_Pos \ - (31UL) /*!< CAN FDR: DISCLK (Bit 31) */ -#define CAN_FDR_DISCLK_Msk \ - (0x80000000UL) /*!< CAN FDR: DISCLK (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- CAN_LIST ---------------------------------- */ -#define CAN_LIST_BEGIN_Pos (0UL) /*!< CAN LIST: BEGIN (Bit 0) */ -#define CAN_LIST_BEGIN_Msk \ - (0xffUL) /*!< CAN LIST: BEGIN (Bitfield-Mask: 0xff) */ -#define CAN_LIST_END_Pos (8UL) /*!< CAN LIST: END (Bit 8) */ -#define CAN_LIST_END_Msk \ - (0xff00UL) /*!< CAN LIST: END (Bitfield-Mask: 0xff) */ -#define CAN_LIST_SIZE_Pos (16UL) /*!< CAN LIST: SIZE (Bit 16) */ -#define CAN_LIST_SIZE_Msk \ - (0xff0000UL) /*!< CAN LIST: SIZE (Bitfield-Mask: 0xff) */ -#define CAN_LIST_EMPTY_Pos \ - (24UL) /*!< CAN LIST: EMPTY (Bit 24) */ -#define CAN_LIST_EMPTY_Msk \ - (0x1000000UL) /*!< CAN LIST: EMPTY (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- CAN_MSPND --------------------------------- */ -#define CAN_MSPND_PND_Pos (0UL) /*!< CAN MSPND: PND (Bit 0) */ -#define CAN_MSPND_PND_Msk \ - (0xffffffffUL) /*!< CAN MSPND: PND (Bitfield-Mask: 0xffffffff) */ - -/* ---------------------------------- CAN_MSID ---------------------------------- */ -#define CAN_MSID_INDEX_Pos (0UL) /*!< CAN MSID: INDEX (Bit 0) */ -#define CAN_MSID_INDEX_Msk \ - (0x3fUL) /*!< CAN MSID: INDEX (Bitfield-Mask: 0x3f) */ - -/* --------------------------------- CAN_MSIMASK -------------------------------- */ -#define CAN_MSIMASK_IM_Pos (0UL) /*!< CAN MSIMASK: IM (Bit 0) */ -#define CAN_MSIMASK_IM_Msk \ - (0xffffffffUL) /*!< CAN MSIMASK: IM (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------------- CAN_PANCTR --------------------------------- */ -#define CAN_PANCTR_PANCMD_Pos \ - (0UL) /*!< CAN PANCTR: PANCMD (Bit 0) */ -#define CAN_PANCTR_PANCMD_Msk \ - (0xffUL) /*!< CAN PANCTR: PANCMD (Bitfield-Mask: 0xff) */ -#define CAN_PANCTR_BUSY_Pos \ - (8UL) /*!< CAN PANCTR: BUSY (Bit 8) */ -#define CAN_PANCTR_BUSY_Msk \ - (0x100UL) /*!< CAN PANCTR: BUSY (Bitfield-Mask: 0x01) */ -#define CAN_PANCTR_RBUSY_Pos \ - (9UL) /*!< CAN PANCTR: RBUSY (Bit 9) */ -#define CAN_PANCTR_RBUSY_Msk \ - (0x200UL) /*!< CAN PANCTR: RBUSY (Bitfield-Mask: 0x01) */ -#define CAN_PANCTR_PANAR1_Pos \ - (16UL) /*!< CAN PANCTR: PANAR1 (Bit 16) */ -#define CAN_PANCTR_PANAR1_Msk \ - (0xff0000UL) /*!< CAN PANCTR: PANAR1 (Bitfield-Mask: 0xff) */ -#define CAN_PANCTR_PANAR2_Pos \ - (24UL) /*!< CAN PANCTR: PANAR2 (Bit 24) */ -#define CAN_PANCTR_PANAR2_Msk \ - (0xff000000UL) /*!< CAN PANCTR: PANAR2 (Bitfield-Mask: 0xff) */ - -/* ----------------------------------- CAN_MCR ---------------------------------- */ -#define CAN_MCR_MPSEL_Pos (12UL) /*!< CAN MCR: MPSEL (Bit 12) */ -#define CAN_MCR_MPSEL_Msk \ - (0xf000UL) /*!< CAN MCR: MPSEL (Bitfield-Mask: 0x0f) */ - -/* ---------------------------------- CAN_MITR ---------------------------------- */ -#define CAN_MITR_IT_Pos (0UL) /*!< CAN MITR: IT (Bit 0) */ -#define CAN_MITR_IT_Msk (0xffUL) /*!< CAN MITR: IT (Bitfield-Mask: 0xff) */ - -/* ================================================================================ */ -/* ================ Group 'CAN_NODE' Position & Mask ================ */ -/* ================================================================================ */ - -/* -------------------------------- CAN_NODE_NCR -------------------------------- */ -#define CAN_NODE_NCR_INIT_Pos \ - (0UL) /*!< CAN_NODE NCR: INIT (Bit 0) */ -#define CAN_NODE_NCR_INIT_Msk \ - (0x1UL) /*!< CAN_NODE NCR: INIT (Bitfield-Mask: 0x01) */ -#define CAN_NODE_NCR_TRIE_Pos \ - (1UL) /*!< CAN_NODE NCR: TRIE (Bit 1) */ -#define CAN_NODE_NCR_TRIE_Msk \ - (0x2UL) /*!< CAN_NODE NCR: TRIE (Bitfield-Mask: 0x01) */ -#define CAN_NODE_NCR_LECIE_Pos \ - (2UL) /*!< CAN_NODE NCR: LECIE (Bit 2) */ -#define CAN_NODE_NCR_LECIE_Msk \ - (0x4UL) /*!< CAN_NODE NCR: LECIE (Bitfield-Mask: 0x01) */ -#define CAN_NODE_NCR_ALIE_Pos \ - (3UL) /*!< CAN_NODE NCR: ALIE (Bit 3) */ -#define CAN_NODE_NCR_ALIE_Msk \ - (0x8UL) /*!< CAN_NODE NCR: ALIE (Bitfield-Mask: 0x01) */ -#define CAN_NODE_NCR_CANDIS_Pos \ - (4UL) /*!< CAN_NODE NCR: CANDIS (Bit 4) */ -#define CAN_NODE_NCR_CANDIS_Msk \ - (0x10UL) /*!< CAN_NODE NCR: CANDIS (Bitfield-Mask: 0x01) */ -#define CAN_NODE_NCR_CCE_Pos \ - (6UL) /*!< CAN_NODE NCR: CCE (Bit 6) */ -#define CAN_NODE_NCR_CCE_Msk \ - (0x40UL) /*!< CAN_NODE NCR: CCE (Bitfield-Mask: 0x01) */ -#define CAN_NODE_NCR_CALM_Pos \ - (7UL) /*!< CAN_NODE NCR: CALM (Bit 7) */ -#define CAN_NODE_NCR_CALM_Msk \ - (0x80UL) /*!< CAN_NODE NCR: CALM (Bitfield-Mask: 0x01) */ -#define CAN_NODE_NCR_SUSEN_Pos \ - (8UL) /*!< CAN_NODE NCR: SUSEN (Bit 8) */ -#define CAN_NODE_NCR_SUSEN_Msk \ - (0x100UL) /*!< CAN_NODE NCR: SUSEN (Bitfield-Mask: 0x01) */ - -/* -------------------------------- CAN_NODE_NSR -------------------------------- */ -#define CAN_NODE_NSR_LEC_Pos \ - (0UL) /*!< CAN_NODE NSR: LEC (Bit 0) */ -#define CAN_NODE_NSR_LEC_Msk \ - (0x7UL) /*!< CAN_NODE NSR: LEC (Bitfield-Mask: 0x07) */ -#define CAN_NODE_NSR_TXOK_Pos \ - (3UL) /*!< CAN_NODE NSR: TXOK (Bit 3) */ -#define CAN_NODE_NSR_TXOK_Msk \ - (0x8UL) /*!< CAN_NODE NSR: TXOK (Bitfield-Mask: 0x01) */ -#define CAN_NODE_NSR_RXOK_Pos \ - (4UL) /*!< CAN_NODE NSR: RXOK (Bit 4) */ -#define CAN_NODE_NSR_RXOK_Msk \ - (0x10UL) /*!< CAN_NODE NSR: RXOK (Bitfield-Mask: 0x01) */ -#define CAN_NODE_NSR_ALERT_Pos \ - (5UL) /*!< CAN_NODE NSR: ALERT (Bit 5) */ -#define CAN_NODE_NSR_ALERT_Msk \ - (0x20UL) /*!< CAN_NODE NSR: ALERT (Bitfield-Mask: 0x01) */ -#define CAN_NODE_NSR_EWRN_Pos \ - (6UL) /*!< CAN_NODE NSR: EWRN (Bit 6) */ -#define CAN_NODE_NSR_EWRN_Msk \ - (0x40UL) /*!< CAN_NODE NSR: EWRN (Bitfield-Mask: 0x01) */ -#define CAN_NODE_NSR_BOFF_Pos \ - (7UL) /*!< CAN_NODE NSR: BOFF (Bit 7) */ -#define CAN_NODE_NSR_BOFF_Msk \ - (0x80UL) /*!< CAN_NODE NSR: BOFF (Bitfield-Mask: 0x01) */ -#define CAN_NODE_NSR_LLE_Pos \ - (8UL) /*!< CAN_NODE NSR: LLE (Bit 8) */ -#define CAN_NODE_NSR_LLE_Msk \ - (0x100UL) /*!< CAN_NODE NSR: LLE (Bitfield-Mask: 0x01) */ -#define CAN_NODE_NSR_LOE_Pos \ - (9UL) /*!< CAN_NODE NSR: LOE (Bit 9) */ -#define CAN_NODE_NSR_LOE_Msk \ - (0x200UL) /*!< CAN_NODE NSR: LOE (Bitfield-Mask: 0x01) */ -#define CAN_NODE_NSR_SUSACK_Pos \ - (10UL) /*!< CAN_NODE NSR: SUSACK (Bit 10) */ -#define CAN_NODE_NSR_SUSACK_Msk \ - (0x400UL) /*!< CAN_NODE NSR: SUSACK (Bitfield-Mask: 0x01) */ - -/* -------------------------------- CAN_NODE_NIPR ------------------------------- */ -#define CAN_NODE_NIPR_ALINP_Pos \ - (0UL) /*!< CAN_NODE NIPR: ALINP (Bit 0) */ -#define CAN_NODE_NIPR_ALINP_Msk \ - (0x7UL) /*!< CAN_NODE NIPR: ALINP (Bitfield-Mask: 0x07) */ -#define CAN_NODE_NIPR_LECINP_Pos \ - (4UL) /*!< CAN_NODE NIPR: LECINP (Bit 4) */ -#define CAN_NODE_NIPR_LECINP_Msk \ - (0x70UL) /*!< CAN_NODE NIPR: LECINP (Bitfield-Mask: 0x07) */ -#define CAN_NODE_NIPR_TRINP_Pos \ - (8UL) /*!< CAN_NODE NIPR: TRINP (Bit 8) */ -#define CAN_NODE_NIPR_TRINP_Msk \ - (0x700UL) /*!< CAN_NODE NIPR: TRINP (Bitfield-Mask: 0x07) */ -#define CAN_NODE_NIPR_CFCINP_Pos \ - (12UL) /*!< CAN_NODE NIPR: CFCINP (Bit 12) */ -#define CAN_NODE_NIPR_CFCINP_Msk \ - (0x7000UL) /*!< CAN_NODE NIPR: CFCINP (Bitfield-Mask: 0x07) */ - -/* -------------------------------- CAN_NODE_NPCR ------------------------------- */ -#define CAN_NODE_NPCR_RXSEL_Pos \ - (0UL) /*!< CAN_NODE NPCR: RXSEL (Bit 0) */ -#define CAN_NODE_NPCR_RXSEL_Msk \ - (0x7UL) /*!< CAN_NODE NPCR: RXSEL (Bitfield-Mask: 0x07) */ -#define CAN_NODE_NPCR_LBM_Pos \ - (8UL) /*!< CAN_NODE NPCR: LBM (Bit 8) */ -#define CAN_NODE_NPCR_LBM_Msk \ - (0x100UL) /*!< CAN_NODE NPCR: LBM (Bitfield-Mask: 0x01) */ - -/* -------------------------------- CAN_NODE_NBTR ------------------------------- */ -#define CAN_NODE_NBTR_BRP_Pos \ - (0UL) /*!< CAN_NODE NBTR: BRP (Bit 0) */ -#define CAN_NODE_NBTR_BRP_Msk \ - (0x3fUL) /*!< CAN_NODE NBTR: BRP (Bitfield-Mask: 0x3f) */ -#define CAN_NODE_NBTR_SJW_Pos \ - (6UL) /*!< CAN_NODE NBTR: SJW (Bit 6) */ -#define CAN_NODE_NBTR_SJW_Msk \ - (0xc0UL) /*!< CAN_NODE NBTR: SJW (Bitfield-Mask: 0x03) */ -#define CAN_NODE_NBTR_TSEG1_Pos \ - (8UL) /*!< CAN_NODE NBTR: TSEG1 (Bit 8) */ -#define CAN_NODE_NBTR_TSEG1_Msk \ - (0xf00UL) /*!< CAN_NODE NBTR: TSEG1 (Bitfield-Mask: 0x0f) */ -#define CAN_NODE_NBTR_TSEG2_Pos \ - (12UL) /*!< CAN_NODE NBTR: TSEG2 (Bit 12) */ -#define CAN_NODE_NBTR_TSEG2_Msk \ - (0x7000UL) /*!< CAN_NODE NBTR: TSEG2 (Bitfield-Mask: 0x07) */ -#define CAN_NODE_NBTR_DIV8_Pos \ - (15UL) /*!< CAN_NODE NBTR: DIV8 (Bit 15) */ -#define CAN_NODE_NBTR_DIV8_Msk \ - (0x8000UL) /*!< CAN_NODE NBTR: DIV8 (Bitfield-Mask: 0x01) */ - -/* ------------------------------- CAN_NODE_NECNT ------------------------------- */ -#define CAN_NODE_NECNT_REC_Pos \ - (0UL) /*!< CAN_NODE NECNT: REC (Bit 0) */ -#define CAN_NODE_NECNT_REC_Msk \ - (0xffUL) /*!< CAN_NODE NECNT: REC (Bitfield-Mask: 0xff) */ -#define CAN_NODE_NECNT_TEC_Pos \ - (8UL) /*!< CAN_NODE NECNT: TEC (Bit 8) */ -#define CAN_NODE_NECNT_TEC_Msk \ - (0xff00UL) /*!< CAN_NODE NECNT: TEC (Bitfield-Mask: 0xff) */ -#define CAN_NODE_NECNT_EWRNLVL_Pos \ - (16UL) /*!< CAN_NODE NECNT: EWRNLVL (Bit 16) */ -#define CAN_NODE_NECNT_EWRNLVL_Msk \ - (0xff0000UL) /*!< CAN_NODE NECNT: EWRNLVL (Bitfield-Mask: 0xff) */ -#define CAN_NODE_NECNT_LETD_Pos \ - (24UL) /*!< CAN_NODE NECNT: LETD (Bit 24) */ -#define CAN_NODE_NECNT_LETD_Msk \ - (0x1000000UL) /*!< CAN_NODE NECNT: LETD (Bitfield-Mask: 0x01) */ -#define CAN_NODE_NECNT_LEINC_Pos \ - (25UL) /*!< CAN_NODE NECNT: LEINC (Bit 25) */ -#define CAN_NODE_NECNT_LEINC_Msk \ - (0x2000000UL) /*!< CAN_NODE NECNT: LEINC (Bitfield-Mask: 0x01) */ - -/* -------------------------------- CAN_NODE_NFCR ------------------------------- */ -#define CAN_NODE_NFCR_CFC_Pos \ - (0UL) /*!< CAN_NODE NFCR: CFC (Bit 0) */ -#define CAN_NODE_NFCR_CFC_Msk \ - (0xffffUL) /*!< CAN_NODE NFCR: CFC (Bitfield-Mask: 0xffff) */ -#define CAN_NODE_NFCR_CFSEL_Pos \ - (16UL) /*!< CAN_NODE NFCR: CFSEL (Bit 16) */ -#define CAN_NODE_NFCR_CFSEL_Msk \ - (0x70000UL) /*!< CAN_NODE NFCR: CFSEL (Bitfield-Mask: 0x07) */ -#define CAN_NODE_NFCR_CFMOD_Pos \ - (19UL) /*!< CAN_NODE NFCR: CFMOD (Bit 19) */ -#define CAN_NODE_NFCR_CFMOD_Msk \ - (0x180000UL) /*!< CAN_NODE NFCR: CFMOD (Bitfield-Mask: 0x03) */ -#define CAN_NODE_NFCR_CFCIE_Pos \ - (22UL) /*!< CAN_NODE NFCR: CFCIE (Bit 22) */ -#define CAN_NODE_NFCR_CFCIE_Msk \ - (0x400000UL) /*!< CAN_NODE NFCR: CFCIE (Bitfield-Mask: 0x01) */ -#define CAN_NODE_NFCR_CFCOV_Pos \ - (23UL) /*!< CAN_NODE NFCR: CFCOV (Bit 23) */ -#define CAN_NODE_NFCR_CFCOV_Msk \ - (0x800000UL) /*!< CAN_NODE NFCR: CFCOV (Bitfield-Mask: 0x01) */ - -/* ================================================================================ */ -/* ================ Group 'CAN_MO' Position & Mask ================ */ -/* ================================================================================ */ - -/* -------------------------------- CAN_MO_MOFCR -------------------------------- */ -#define CAN_MO_MOFCR_MMC_Pos \ - (0UL) /*!< CAN_MO MOFCR: MMC (Bit 0) */ -#define CAN_MO_MOFCR_MMC_Msk \ - (0xfUL) /*!< CAN_MO MOFCR: MMC (Bitfield-Mask: 0x0f) */ -#define CAN_MO_MOFCR_GDFS_Pos \ - (8UL) /*!< CAN_MO MOFCR: GDFS (Bit 8) */ -#define CAN_MO_MOFCR_GDFS_Msk \ - (0x100UL) /*!< CAN_MO MOFCR: GDFS (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOFCR_IDC_Pos \ - (9UL) /*!< CAN_MO MOFCR: IDC (Bit 9) */ -#define CAN_MO_MOFCR_IDC_Msk \ - (0x200UL) /*!< CAN_MO MOFCR: IDC (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOFCR_DLCC_Pos \ - (10UL) /*!< CAN_MO MOFCR: DLCC (Bit 10) */ -#define CAN_MO_MOFCR_DLCC_Msk \ - (0x400UL) /*!< CAN_MO MOFCR: DLCC (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOFCR_DATC_Pos \ - (11UL) /*!< CAN_MO MOFCR: DATC (Bit 11) */ -#define CAN_MO_MOFCR_DATC_Msk \ - (0x800UL) /*!< CAN_MO MOFCR: DATC (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOFCR_RXIE_Pos \ - (16UL) /*!< CAN_MO MOFCR: RXIE (Bit 16) */ -#define CAN_MO_MOFCR_RXIE_Msk \ - (0x10000UL) /*!< CAN_MO MOFCR: RXIE (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOFCR_TXIE_Pos \ - (17UL) /*!< CAN_MO MOFCR: TXIE (Bit 17) */ -#define CAN_MO_MOFCR_TXIE_Msk \ - (0x20000UL) /*!< CAN_MO MOFCR: TXIE (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOFCR_OVIE_Pos \ - (18UL) /*!< CAN_MO MOFCR: OVIE (Bit 18) */ -#define CAN_MO_MOFCR_OVIE_Msk \ - (0x40000UL) /*!< CAN_MO MOFCR: OVIE (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOFCR_FRREN_Pos \ - (20UL) /*!< CAN_MO MOFCR: FRREN (Bit 20) */ -#define CAN_MO_MOFCR_FRREN_Msk \ - (0x100000UL) /*!< CAN_MO MOFCR: FRREN (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOFCR_RMM_Pos \ - (21UL) /*!< CAN_MO MOFCR: RMM (Bit 21) */ -#define CAN_MO_MOFCR_RMM_Msk \ - (0x200000UL) /*!< CAN_MO MOFCR: RMM (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOFCR_SDT_Pos \ - (22UL) /*!< CAN_MO MOFCR: SDT (Bit 22) */ -#define CAN_MO_MOFCR_SDT_Msk \ - (0x400000UL) /*!< CAN_MO MOFCR: SDT (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOFCR_STT_Pos \ - (23UL) /*!< CAN_MO MOFCR: STT (Bit 23) */ -#define CAN_MO_MOFCR_STT_Msk \ - (0x800000UL) /*!< CAN_MO MOFCR: STT (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOFCR_DLC_Pos \ - (24UL) /*!< CAN_MO MOFCR: DLC (Bit 24) */ -#define CAN_MO_MOFCR_DLC_Msk \ - (0xf000000UL) /*!< CAN_MO MOFCR: DLC (Bitfield-Mask: 0x0f) */ - -/* -------------------------------- CAN_MO_MOFGPR ------------------------------- */ -#define CAN_MO_MOFGPR_BOT_Pos \ - (0UL) /*!< CAN_MO MOFGPR: BOT (Bit 0) */ -#define CAN_MO_MOFGPR_BOT_Msk \ - (0xffUL) /*!< CAN_MO MOFGPR: BOT (Bitfield-Mask: 0xff) */ -#define CAN_MO_MOFGPR_TOP_Pos \ - (8UL) /*!< CAN_MO MOFGPR: TOP (Bit 8) */ -#define CAN_MO_MOFGPR_TOP_Msk \ - (0xff00UL) /*!< CAN_MO MOFGPR: TOP (Bitfield-Mask: 0xff) */ -#define CAN_MO_MOFGPR_CUR_Pos \ - (16UL) /*!< CAN_MO MOFGPR: CUR (Bit 16) */ -#define CAN_MO_MOFGPR_CUR_Msk \ - (0xff0000UL) /*!< CAN_MO MOFGPR: CUR (Bitfield-Mask: 0xff) */ -#define CAN_MO_MOFGPR_SEL_Pos \ - (24UL) /*!< CAN_MO MOFGPR: SEL (Bit 24) */ -#define CAN_MO_MOFGPR_SEL_Msk \ - (0xff000000UL) /*!< CAN_MO MOFGPR: SEL (Bitfield-Mask: 0xff) */ - -/* -------------------------------- CAN_MO_MOIPR -------------------------------- */ -#define CAN_MO_MOIPR_RXINP_Pos \ - (0UL) /*!< CAN_MO MOIPR: RXINP (Bit 0) */ -#define CAN_MO_MOIPR_RXINP_Msk \ - (0x7UL) /*!< CAN_MO MOIPR: RXINP (Bitfield-Mask: 0x07) */ -#define CAN_MO_MOIPR_TXINP_Pos \ - (4UL) /*!< CAN_MO MOIPR: TXINP (Bit 4) */ -#define CAN_MO_MOIPR_TXINP_Msk \ - (0x70UL) /*!< CAN_MO MOIPR: TXINP (Bitfield-Mask: 0x07) */ -#define CAN_MO_MOIPR_MPN_Pos \ - (8UL) /*!< CAN_MO MOIPR: MPN (Bit 8) */ -#define CAN_MO_MOIPR_MPN_Msk \ - (0xff00UL) /*!< CAN_MO MOIPR: MPN (Bitfield-Mask: 0xff) */ -#define CAN_MO_MOIPR_CFCVAL_Pos \ - (16UL) /*!< CAN_MO MOIPR: CFCVAL (Bit 16) */ -#define CAN_MO_MOIPR_CFCVAL_Msk \ - (0xffff0000UL) /*!< CAN_MO MOIPR: CFCVAL (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- CAN_MO_MOAMR -------------------------------- */ -#define CAN_MO_MOAMR_AM_Pos \ - (0UL) /*!< CAN_MO MOAMR: AM (Bit 0) */ -#define CAN_MO_MOAMR_AM_Msk \ - (0x1fffffffUL) /*!< CAN_MO MOAMR: AM (Bitfield-Mask: 0x1fffffff) */ -#define CAN_MO_MOAMR_MIDE_Pos \ - (29UL) /*!< CAN_MO MOAMR: MIDE (Bit 29) */ -#define CAN_MO_MOAMR_MIDE_Msk \ - (0x20000000UL) /*!< CAN_MO MOAMR: MIDE (Bitfield-Mask: 0x01) */ - -/* ------------------------------- CAN_MO_MODATAL ------------------------------- */ -#define CAN_MO_MODATAL_DB0_Pos \ - (0UL) /*!< CAN_MO MODATAL: DB0 (Bit 0) */ -#define CAN_MO_MODATAL_DB0_Msk \ - (0xffUL) /*!< CAN_MO MODATAL: DB0 (Bitfield-Mask: 0xff) */ -#define CAN_MO_MODATAL_DB1_Pos \ - (8UL) /*!< CAN_MO MODATAL: DB1 (Bit 8) */ -#define CAN_MO_MODATAL_DB1_Msk \ - (0xff00UL) /*!< CAN_MO MODATAL: DB1 (Bitfield-Mask: 0xff) */ -#define CAN_MO_MODATAL_DB2_Pos \ - (16UL) /*!< CAN_MO MODATAL: DB2 (Bit 16) */ -#define CAN_MO_MODATAL_DB2_Msk \ - (0xff0000UL) /*!< CAN_MO MODATAL: DB2 (Bitfield-Mask: 0xff) */ -#define CAN_MO_MODATAL_DB3_Pos \ - (24UL) /*!< CAN_MO MODATAL: DB3 (Bit 24) */ -#define CAN_MO_MODATAL_DB3_Msk \ - (0xff000000UL) /*!< CAN_MO MODATAL: DB3 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- CAN_MO_MODATAH ------------------------------- */ -#define CAN_MO_MODATAH_DB4_Pos \ - (0UL) /*!< CAN_MO MODATAH: DB4 (Bit 0) */ -#define CAN_MO_MODATAH_DB4_Msk \ - (0xffUL) /*!< CAN_MO MODATAH: DB4 (Bitfield-Mask: 0xff) */ -#define CAN_MO_MODATAH_DB5_Pos \ - (8UL) /*!< CAN_MO MODATAH: DB5 (Bit 8) */ -#define CAN_MO_MODATAH_DB5_Msk \ - (0xff00UL) /*!< CAN_MO MODATAH: DB5 (Bitfield-Mask: 0xff) */ -#define CAN_MO_MODATAH_DB6_Pos \ - (16UL) /*!< CAN_MO MODATAH: DB6 (Bit 16) */ -#define CAN_MO_MODATAH_DB6_Msk \ - (0xff0000UL) /*!< CAN_MO MODATAH: DB6 (Bitfield-Mask: 0xff) */ -#define CAN_MO_MODATAH_DB7_Pos \ - (24UL) /*!< CAN_MO MODATAH: DB7 (Bit 24) */ -#define CAN_MO_MODATAH_DB7_Msk \ - (0xff000000UL) /*!< CAN_MO MODATAH: DB7 (Bitfield-Mask: 0xff) */ - -/* --------------------------------- CAN_MO_MOAR -------------------------------- */ -#define CAN_MO_MOAR_ID_Pos (0UL) /*!< CAN_MO MOAR: ID (Bit 0) */ -#define CAN_MO_MOAR_ID_Msk \ - (0x1fffffffUL) /*!< CAN_MO MOAR: ID (Bitfield-Mask: 0x1fffffff) */ -#define CAN_MO_MOAR_IDE_Pos \ - (29UL) /*!< CAN_MO MOAR: IDE (Bit 29) */ -#define CAN_MO_MOAR_IDE_Msk \ - (0x20000000UL) /*!< CAN_MO MOAR: IDE (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOAR_PRI_Pos \ - (30UL) /*!< CAN_MO MOAR: PRI (Bit 30) */ -#define CAN_MO_MOAR_PRI_Msk \ - (0xc0000000UL) /*!< CAN_MO MOAR: PRI (Bitfield-Mask: 0x03) */ - -/* -------------------------------- CAN_MO_MOCTR -------------------------------- */ -#define CAN_MO_MOCTR_RESRXPND_Pos \ - (0UL) /*!< CAN_MO MOCTR: RESRXPND (Bit 0) */ -#define CAN_MO_MOCTR_RESRXPND_Msk \ - (0x1UL) /*!< CAN_MO MOCTR: RESRXPND (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOCTR_RESTXPND_Pos \ - (1UL) /*!< CAN_MO MOCTR: RESTXPND (Bit 1) */ -#define CAN_MO_MOCTR_RESTXPND_Msk \ - (0x2UL) /*!< CAN_MO MOCTR: RESTXPND (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOCTR_RESRXUPD_Pos \ - (2UL) /*!< CAN_MO MOCTR: RESRXUPD (Bit 2) */ -#define CAN_MO_MOCTR_RESRXUPD_Msk \ - (0x4UL) /*!< CAN_MO MOCTR: RESRXUPD (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOCTR_RESNEWDAT_Pos \ - (3UL) /*!< CAN_MO MOCTR: RESNEWDAT (Bit 3) */ -#define CAN_MO_MOCTR_RESNEWDAT_Msk \ - (0x8UL) /*!< CAN_MO MOCTR: RESNEWDAT (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOCTR_RESMSGLST_Pos \ - (4UL) /*!< CAN_MO MOCTR: RESMSGLST (Bit 4) */ -#define CAN_MO_MOCTR_RESMSGLST_Msk \ - (0x10UL) /*!< CAN_MO MOCTR: RESMSGLST (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOCTR_RESMSGVAL_Pos \ - (5UL) /*!< CAN_MO MOCTR: RESMSGVAL (Bit 5) */ -#define CAN_MO_MOCTR_RESMSGVAL_Msk \ - (0x20UL) /*!< CAN_MO MOCTR: RESMSGVAL (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOCTR_RESRTSEL_Pos \ - (6UL) /*!< CAN_MO MOCTR: RESRTSEL (Bit 6) */ -#define CAN_MO_MOCTR_RESRTSEL_Msk \ - (0x40UL) /*!< CAN_MO MOCTR: RESRTSEL (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOCTR_RESRXEN_Pos \ - (7UL) /*!< CAN_MO MOCTR: RESRXEN (Bit 7) */ -#define CAN_MO_MOCTR_RESRXEN_Msk \ - (0x80UL) /*!< CAN_MO MOCTR: RESRXEN (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOCTR_RESTXRQ_Pos \ - (8UL) /*!< CAN_MO MOCTR: RESTXRQ (Bit 8) */ -#define CAN_MO_MOCTR_RESTXRQ_Msk \ - (0x100UL) /*!< CAN_MO MOCTR: RESTXRQ (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOCTR_RESTXEN0_Pos \ - (9UL) /*!< CAN_MO MOCTR: RESTXEN0 (Bit 9) */ -#define CAN_MO_MOCTR_RESTXEN0_Msk \ - (0x200UL) /*!< CAN_MO MOCTR: RESTXEN0 (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOCTR_RESTXEN1_Pos \ - (10UL) /*!< CAN_MO MOCTR: RESTXEN1 (Bit 10) */ -#define CAN_MO_MOCTR_RESTXEN1_Msk \ - (0x400UL) /*!< CAN_MO MOCTR: RESTXEN1 (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOCTR_RESDIR_Pos \ - (11UL) /*!< CAN_MO MOCTR: RESDIR (Bit 11) */ -#define CAN_MO_MOCTR_RESDIR_Msk \ - (0x800UL) /*!< CAN_MO MOCTR: RESDIR (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOCTR_SETRXPND_Pos \ - (16UL) /*!< CAN_MO MOCTR: SETRXPND (Bit 16) */ -#define CAN_MO_MOCTR_SETRXPND_Msk \ - (0x10000UL) /*!< CAN_MO MOCTR: SETRXPND (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOCTR_SETTXPND_Pos \ - (17UL) /*!< CAN_MO MOCTR: SETTXPND (Bit 17) */ -#define CAN_MO_MOCTR_SETTXPND_Msk \ - (0x20000UL) /*!< CAN_MO MOCTR: SETTXPND (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOCTR_SETRXUPD_Pos \ - (18UL) /*!< CAN_MO MOCTR: SETRXUPD (Bit 18) */ -#define CAN_MO_MOCTR_SETRXUPD_Msk \ - (0x40000UL) /*!< CAN_MO MOCTR: SETRXUPD (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOCTR_SETNEWDAT_Pos \ - (19UL) /*!< CAN_MO MOCTR: SETNEWDAT (Bit 19) */ -#define CAN_MO_MOCTR_SETNEWDAT_Msk \ - (0x80000UL) /*!< CAN_MO MOCTR: SETNEWDAT (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOCTR_SETMSGLST_Pos \ - (20UL) /*!< CAN_MO MOCTR: SETMSGLST (Bit 20) */ -#define CAN_MO_MOCTR_SETMSGLST_Msk \ - (0x100000UL) /*!< CAN_MO MOCTR: SETMSGLST (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOCTR_SETMSGVAL_Pos \ - (21UL) /*!< CAN_MO MOCTR: SETMSGVAL (Bit 21) */ -#define CAN_MO_MOCTR_SETMSGVAL_Msk \ - (0x200000UL) /*!< CAN_MO MOCTR: SETMSGVAL (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOCTR_SETRTSEL_Pos \ - (22UL) /*!< CAN_MO MOCTR: SETRTSEL (Bit 22) */ -#define CAN_MO_MOCTR_SETRTSEL_Msk \ - (0x400000UL) /*!< CAN_MO MOCTR: SETRTSEL (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOCTR_SETRXEN_Pos \ - (23UL) /*!< CAN_MO MOCTR: SETRXEN (Bit 23) */ -#define CAN_MO_MOCTR_SETRXEN_Msk \ - (0x800000UL) /*!< CAN_MO MOCTR: SETRXEN (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOCTR_SETTXRQ_Pos \ - (24UL) /*!< CAN_MO MOCTR: SETTXRQ (Bit 24) */ -#define CAN_MO_MOCTR_SETTXRQ_Msk \ - (0x1000000UL) /*!< CAN_MO MOCTR: SETTXRQ (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOCTR_SETTXEN0_Pos \ - (25UL) /*!< CAN_MO MOCTR: SETTXEN0 (Bit 25) */ -#define CAN_MO_MOCTR_SETTXEN0_Msk \ - (0x2000000UL) /*!< CAN_MO MOCTR: SETTXEN0 (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOCTR_SETTXEN1_Pos \ - (26UL) /*!< CAN_MO MOCTR: SETTXEN1 (Bit 26) */ -#define CAN_MO_MOCTR_SETTXEN1_Msk \ - (0x4000000UL) /*!< CAN_MO MOCTR: SETTXEN1 (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOCTR_SETDIR_Pos \ - (27UL) /*!< CAN_MO MOCTR: SETDIR (Bit 27) */ -#define CAN_MO_MOCTR_SETDIR_Msk \ - (0x8000000UL) /*!< CAN_MO MOCTR: SETDIR (Bitfield-Mask: 0x01) */ - -/* -------------------------------- CAN_MO_MOSTAT ------------------------------- */ -#define CAN_MO_MOSTAT_RXPND_Pos \ - (0UL) /*!< CAN_MO MOSTAT: RXPND (Bit 0) */ -#define CAN_MO_MOSTAT_RXPND_Msk \ - (0x1UL) /*!< CAN_MO MOSTAT: RXPND (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOSTAT_TXPND_Pos \ - (1UL) /*!< CAN_MO MOSTAT: TXPND (Bit 1) */ -#define CAN_MO_MOSTAT_TXPND_Msk \ - (0x2UL) /*!< CAN_MO MOSTAT: TXPND (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOSTAT_RXUPD_Pos \ - (2UL) /*!< CAN_MO MOSTAT: RXUPD (Bit 2) */ -#define CAN_MO_MOSTAT_RXUPD_Msk \ - (0x4UL) /*!< CAN_MO MOSTAT: RXUPD (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOSTAT_NEWDAT_Pos \ - (3UL) /*!< CAN_MO MOSTAT: NEWDAT (Bit 3) */ -#define CAN_MO_MOSTAT_NEWDAT_Msk \ - (0x8UL) /*!< CAN_MO MOSTAT: NEWDAT (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOSTAT_MSGLST_Pos \ - (4UL) /*!< CAN_MO MOSTAT: MSGLST (Bit 4) */ -#define CAN_MO_MOSTAT_MSGLST_Msk \ - (0x10UL) /*!< CAN_MO MOSTAT: MSGLST (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOSTAT_MSGVAL_Pos \ - (5UL) /*!< CAN_MO MOSTAT: MSGVAL (Bit 5) */ -#define CAN_MO_MOSTAT_MSGVAL_Msk \ - (0x20UL) /*!< CAN_MO MOSTAT: MSGVAL (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOSTAT_RTSEL_Pos \ - (6UL) /*!< CAN_MO MOSTAT: RTSEL (Bit 6) */ -#define CAN_MO_MOSTAT_RTSEL_Msk \ - (0x40UL) /*!< CAN_MO MOSTAT: RTSEL (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOSTAT_RXEN_Pos \ - (7UL) /*!< CAN_MO MOSTAT: RXEN (Bit 7) */ -#define CAN_MO_MOSTAT_RXEN_Msk \ - (0x80UL) /*!< CAN_MO MOSTAT: RXEN (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOSTAT_TXRQ_Pos \ - (8UL) /*!< CAN_MO MOSTAT: TXRQ (Bit 8) */ -#define CAN_MO_MOSTAT_TXRQ_Msk \ - (0x100UL) /*!< CAN_MO MOSTAT: TXRQ (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOSTAT_TXEN0_Pos \ - (9UL) /*!< CAN_MO MOSTAT: TXEN0 (Bit 9) */ -#define CAN_MO_MOSTAT_TXEN0_Msk \ - (0x200UL) /*!< CAN_MO MOSTAT: TXEN0 (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOSTAT_TXEN1_Pos \ - (10UL) /*!< CAN_MO MOSTAT: TXEN1 (Bit 10) */ -#define CAN_MO_MOSTAT_TXEN1_Msk \ - (0x400UL) /*!< CAN_MO MOSTAT: TXEN1 (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOSTAT_DIR_Pos \ - (11UL) /*!< CAN_MO MOSTAT: DIR (Bit 11) */ -#define CAN_MO_MOSTAT_DIR_Msk \ - (0x800UL) /*!< CAN_MO MOSTAT: DIR (Bitfield-Mask: 0x01) */ -#define CAN_MO_MOSTAT_LIST_Pos \ - (12UL) /*!< CAN_MO MOSTAT: LIST (Bit 12) */ -#define CAN_MO_MOSTAT_LIST_Msk \ - (0xf000UL) /*!< CAN_MO MOSTAT: LIST (Bitfield-Mask: 0x0f) */ -#define CAN_MO_MOSTAT_PPREV_Pos \ - (16UL) /*!< CAN_MO MOSTAT: PPREV (Bit 16) */ -#define CAN_MO_MOSTAT_PPREV_Msk \ - (0xff0000UL) /*!< CAN_MO MOSTAT: PPREV (Bitfield-Mask: 0xff) */ -#define CAN_MO_MOSTAT_PNEXT_Pos \ - (24UL) /*!< CAN_MO MOSTAT: PNEXT (Bit 24) */ -#define CAN_MO_MOSTAT_PNEXT_Msk \ - (0xff000000UL) /*!< CAN_MO MOSTAT: PNEXT (Bitfield-Mask: 0xff) */ - -/* ================================================================================ */ -/* ================ struct 'VADC' Position & Mask ================ */ -/* ================================================================================ */ - -/* ---------------------------------- VADC_CLC ---------------------------------- */ -#define VADC_CLC_DISR_Pos (0UL) /*!< VADC CLC: DISR (Bit 0) */ -#define VADC_CLC_DISR_Msk \ - (0x1UL) /*!< VADC CLC: DISR (Bitfield-Mask: 0x01) */ -#define VADC_CLC_DISS_Pos (1UL) /*!< VADC CLC: DISS (Bit 1) */ -#define VADC_CLC_DISS_Msk \ - (0x2UL) /*!< VADC CLC: DISS (Bitfield-Mask: 0x01) */ -#define VADC_CLC_EDIS_Pos (3UL) /*!< VADC CLC: EDIS (Bit 3) */ -#define VADC_CLC_EDIS_Msk \ - (0x8UL) /*!< VADC CLC: EDIS (Bitfield-Mask: 0x01) */ - -/* ----------------------------------- VADC_ID ---------------------------------- */ -#define VADC_ID_MOD_REV_Pos \ - (0UL) /*!< VADC ID: MOD_REV (Bit 0) */ -#define VADC_ID_MOD_REV_Msk \ - (0xffUL) /*!< VADC ID: MOD_REV (Bitfield-Mask: 0xff) */ -#define VADC_ID_MOD_TYPE_Pos \ - (8UL) /*!< VADC ID: MOD_TYPE (Bit 8) */ -#define VADC_ID_MOD_TYPE_Msk \ - (0xff00UL) /*!< VADC ID: MOD_TYPE (Bitfield-Mask: 0xff) */ -#define VADC_ID_MOD_NUMBER_Pos \ - (16UL) /*!< VADC ID: MOD_NUMBER (Bit 16) */ -#define VADC_ID_MOD_NUMBER_Msk \ - (0xffff0000UL) /*!< VADC ID: MOD_NUMBER (Bitfield-Mask: 0xffff) */ - -/* ---------------------------------- VADC_OCS ---------------------------------- */ -#define VADC_OCS_TGS_Pos (0UL) /*!< VADC OCS: TGS (Bit 0) */ -#define VADC_OCS_TGS_Msk (0x3UL) /*!< VADC OCS: TGS (Bitfield-Mask: 0x03) */ -#define VADC_OCS_TGB_Pos (2UL) /*!< VADC OCS: TGB (Bit 2) */ -#define VADC_OCS_TGB_Msk (0x4UL) /*!< VADC OCS: TGB (Bitfield-Mask: 0x01) */ -#define VADC_OCS_TG_P_Pos (3UL) /*!< VADC OCS: TG_P (Bit 3) */ -#define VADC_OCS_TG_P_Msk \ - (0x8UL) /*!< VADC OCS: TG_P (Bitfield-Mask: 0x01) */ -#define VADC_OCS_SUS_Pos (24UL) /*!< VADC OCS: SUS (Bit 24) */ -#define VADC_OCS_SUS_Msk \ - (0xf000000UL) /*!< VADC OCS: SUS (Bitfield-Mask: 0x0f) */ -#define VADC_OCS_SUS_P_Pos \ - (28UL) /*!< VADC OCS: SUS_P (Bit 28) */ -#define VADC_OCS_SUS_P_Msk \ - (0x10000000UL) /*!< VADC OCS: SUS_P (Bitfield-Mask: 0x01) */ -#define VADC_OCS_SUSSTA_Pos \ - (29UL) /*!< VADC OCS: SUSSTA (Bit 29) */ -#define VADC_OCS_SUSSTA_Msk \ - (0x20000000UL) /*!< VADC OCS: SUSSTA (Bitfield-Mask: 0x01) */ - -/* -------------------------------- VADC_GLOBCFG -------------------------------- */ -#define VADC_GLOBCFG_DIVA_Pos \ - (0UL) /*!< VADC GLOBCFG: DIVA (Bit 0) */ -#define VADC_GLOBCFG_DIVA_Msk \ - (0x1fUL) /*!< VADC GLOBCFG: DIVA (Bitfield-Mask: 0x1f) */ -#define VADC_GLOBCFG_DCMSB_Pos \ - (7UL) /*!< VADC GLOBCFG: DCMSB (Bit 7) */ -#define VADC_GLOBCFG_DCMSB_Msk \ - (0x80UL) /*!< VADC GLOBCFG: DCMSB (Bitfield-Mask: 0x01) */ -#define VADC_GLOBCFG_DIVD_Pos \ - (8UL) /*!< VADC GLOBCFG: DIVD (Bit 8) */ -#define VADC_GLOBCFG_DIVD_Msk \ - (0x300UL) /*!< VADC GLOBCFG: DIVD (Bitfield-Mask: 0x03) */ -#define VADC_GLOBCFG_DIVWC_Pos \ - (15UL) /*!< VADC GLOBCFG: DIVWC (Bit 15) */ -#define VADC_GLOBCFG_DIVWC_Msk \ - (0x8000UL) /*!< VADC GLOBCFG: DIVWC (Bitfield-Mask: 0x01) */ -#define VADC_GLOBCFG_DPCAL0_Pos \ - (16UL) /*!< VADC GLOBCFG: DPCAL0 (Bit 16) */ -#define VADC_GLOBCFG_DPCAL0_Msk \ - (0x10000UL) /*!< VADC GLOBCFG: DPCAL0 (Bitfield-Mask: 0x01) */ -#define VADC_GLOBCFG_DPCAL1_Pos \ - (17UL) /*!< VADC GLOBCFG: DPCAL1 (Bit 17) */ -#define VADC_GLOBCFG_DPCAL1_Msk \ - (0x20000UL) /*!< VADC GLOBCFG: DPCAL1 (Bitfield-Mask: 0x01) */ -#define VADC_GLOBCFG_DPCAL2_Pos \ - (18UL) /*!< VADC GLOBCFG: DPCAL2 (Bit 18) */ -#define VADC_GLOBCFG_DPCAL2_Msk \ - (0x40000UL) /*!< VADC GLOBCFG: DPCAL2 (Bitfield-Mask: 0x01) */ -#define VADC_GLOBCFG_DPCAL3_Pos \ - (19UL) /*!< VADC GLOBCFG: DPCAL3 (Bit 19) */ -#define VADC_GLOBCFG_DPCAL3_Msk \ - (0x80000UL) /*!< VADC GLOBCFG: DPCAL3 (Bitfield-Mask: 0x01) */ -#define VADC_GLOBCFG_SUCAL_Pos \ - (31UL) /*!< VADC GLOBCFG: SUCAL (Bit 31) */ -#define VADC_GLOBCFG_SUCAL_Msk \ - (0x80000000UL) /*!< VADC GLOBCFG: SUCAL (Bitfield-Mask: 0x01) */ - -/* ------------------------------- VADC_GLOBICLASS ------------------------------ */ -#define VADC_GLOBICLASS_STCS_Pos \ - (0UL) /*!< VADC GLOBICLASS: STCS (Bit 0) */ -#define VADC_GLOBICLASS_STCS_Msk \ - (0x1fUL) /*!< VADC GLOBICLASS: STCS (Bitfield-Mask: 0x1f) */ -#define VADC_GLOBICLASS_CMS_Pos \ - (8UL) /*!< VADC GLOBICLASS: CMS (Bit 8) */ -#define VADC_GLOBICLASS_CMS_Msk \ - (0x700UL) /*!< VADC GLOBICLASS: CMS (Bitfield-Mask: 0x07) */ -#define VADC_GLOBICLASS_STCE_Pos \ - (16UL) /*!< VADC GLOBICLASS: STCE (Bit 16) */ -#define VADC_GLOBICLASS_STCE_Msk \ - (0x1f0000UL) /*!< VADC GLOBICLASS: STCE (Bitfield-Mask: 0x1f) */ -#define VADC_GLOBICLASS_CME_Pos \ - (24UL) /*!< VADC GLOBICLASS: CME (Bit 24) */ -#define VADC_GLOBICLASS_CME_Msk \ - (0x7000000UL) /*!< VADC GLOBICLASS: CME (Bitfield-Mask: 0x07) */ - -/* ------------------------------- VADC_GLOBBOUND ------------------------------- */ -#define VADC_GLOBBOUND_BOUNDARY0_Pos \ - (0UL) /*!< VADC GLOBBOUND: BOUNDARY0 (Bit 0) */ -#define VADC_GLOBBOUND_BOUNDARY0_Msk \ - (0xfffUL) /*!< VADC GLOBBOUND: BOUNDARY0 (Bitfield-Mask: 0xfff) */ -#define VADC_GLOBBOUND_BOUNDARY1_Pos \ - (16UL) /*!< VADC GLOBBOUND: BOUNDARY1 (Bit 16) */ -#define VADC_GLOBBOUND_BOUNDARY1_Msk \ - (0xfff0000UL) /*!< VADC GLOBBOUND: BOUNDARY1 (Bitfield-Mask: 0xfff) */ - -/* ------------------------------- VADC_GLOBEFLAG ------------------------------- */ -#define VADC_GLOBEFLAG_SEVGLB_Pos \ - (0UL) /*!< VADC GLOBEFLAG: SEVGLB (Bit 0) */ -#define VADC_GLOBEFLAG_SEVGLB_Msk \ - (0x1UL) /*!< VADC GLOBEFLAG: SEVGLB (Bitfield-Mask: 0x01) */ -#define VADC_GLOBEFLAG_REVGLB_Pos \ - (8UL) /*!< VADC GLOBEFLAG: REVGLB (Bit 8) */ -#define VADC_GLOBEFLAG_REVGLB_Msk \ - (0x100UL) /*!< VADC GLOBEFLAG: REVGLB (Bitfield-Mask: 0x01) */ -#define VADC_GLOBEFLAG_SEVGLBCLR_Pos \ - (16UL) /*!< VADC GLOBEFLAG: SEVGLBCLR (Bit 16) */ -#define VADC_GLOBEFLAG_SEVGLBCLR_Msk \ - (0x10000UL) /*!< VADC GLOBEFLAG: SEVGLBCLR (Bitfield-Mask: 0x01) */ -#define VADC_GLOBEFLAG_REVGLBCLR_Pos \ - (24UL) /*!< VADC GLOBEFLAG: REVGLBCLR (Bit 24) */ -#define VADC_GLOBEFLAG_REVGLBCLR_Msk \ - (0x1000000UL) /*!< VADC GLOBEFLAG: REVGLBCLR (Bitfield-Mask: 0x01) */ - -/* -------------------------------- VADC_GLOBEVNP ------------------------------- */ -#define VADC_GLOBEVNP_SEV0NP_Pos \ - (0UL) /*!< VADC GLOBEVNP: SEV0NP (Bit 0) */ -#define VADC_GLOBEVNP_SEV0NP_Msk \ - (0xfUL) /*!< VADC GLOBEVNP: SEV0NP (Bitfield-Mask: 0x0f) */ -#define VADC_GLOBEVNP_REV0NP_Pos \ - (16UL) /*!< VADC GLOBEVNP: REV0NP (Bit 16) */ -#define VADC_GLOBEVNP_REV0NP_Msk \ - (0xf0000UL) /*!< VADC GLOBEVNP: REV0NP (Bitfield-Mask: 0x0f) */ - -/* --------------------------------- VADC_GLOBTF -------------------------------- */ -#define VADC_GLOBTF_CDGR_Pos \ - (4UL) /*!< VADC GLOBTF: CDGR (Bit 4) */ -#define VADC_GLOBTF_CDGR_Msk \ - (0xf0UL) /*!< VADC GLOBTF: CDGR (Bitfield-Mask: 0x0f) */ -#define VADC_GLOBTF_CDEN_Pos \ - (8UL) /*!< VADC GLOBTF: CDEN (Bit 8) */ -#define VADC_GLOBTF_CDEN_Msk \ - (0x100UL) /*!< VADC GLOBTF: CDEN (Bitfield-Mask: 0x01) */ -#define VADC_GLOBTF_CDSEL_Pos \ - (9UL) /*!< VADC GLOBTF: CDSEL (Bit 9) */ -#define VADC_GLOBTF_CDSEL_Msk \ - (0x600UL) /*!< VADC GLOBTF: CDSEL (Bitfield-Mask: 0x03) */ -#define VADC_GLOBTF_CDWC_Pos \ - (15UL) /*!< VADC GLOBTF: CDWC (Bit 15) */ -#define VADC_GLOBTF_CDWC_Msk \ - (0x8000UL) /*!< VADC GLOBTF: CDWC (Bitfield-Mask: 0x01) */ -#define VADC_GLOBTF_PDD_Pos \ - (16UL) /*!< VADC GLOBTF: PDD (Bit 16) */ -#define VADC_GLOBTF_PDD_Msk \ - (0x10000UL) /*!< VADC GLOBTF: PDD (Bitfield-Mask: 0x01) */ -#define VADC_GLOBTF_MDWC_Pos \ - (23UL) /*!< VADC GLOBTF: MDWC (Bit 23) */ -#define VADC_GLOBTF_MDWC_Msk \ - (0x800000UL) /*!< VADC GLOBTF: MDWC (Bitfield-Mask: 0x01) */ - -/* --------------------------------- VADC_BRSSEL -------------------------------- */ -#define VADC_BRSSEL_CHSELG0_Pos \ - (0UL) /*!< VADC BRSSEL: CHSELG0 (Bit 0) */ -#define VADC_BRSSEL_CHSELG0_Msk \ - (0x1UL) /*!< VADC BRSSEL: CHSELG0 (Bitfield-Mask: 0x01) */ -#define VADC_BRSSEL_CHSELG1_Pos \ - (1UL) /*!< VADC BRSSEL: CHSELG1 (Bit 1) */ -#define VADC_BRSSEL_CHSELG1_Msk \ - (0x2UL) /*!< VADC BRSSEL: CHSELG1 (Bitfield-Mask: 0x01) */ -#define VADC_BRSSEL_CHSELG2_Pos \ - (2UL) /*!< VADC BRSSEL: CHSELG2 (Bit 2) */ -#define VADC_BRSSEL_CHSELG2_Msk \ - (0x4UL) /*!< VADC BRSSEL: CHSELG2 (Bitfield-Mask: 0x01) */ -#define VADC_BRSSEL_CHSELG3_Pos \ - (3UL) /*!< VADC BRSSEL: CHSELG3 (Bit 3) */ -#define VADC_BRSSEL_CHSELG3_Msk \ - (0x8UL) /*!< VADC BRSSEL: CHSELG3 (Bitfield-Mask: 0x01) */ -#define VADC_BRSSEL_CHSELG4_Pos \ - (4UL) /*!< VADC BRSSEL: CHSELG4 (Bit 4) */ -#define VADC_BRSSEL_CHSELG4_Msk \ - (0x10UL) /*!< VADC BRSSEL: CHSELG4 (Bitfield-Mask: 0x01) */ -#define VADC_BRSSEL_CHSELG5_Pos \ - (5UL) /*!< VADC BRSSEL: CHSELG5 (Bit 5) */ -#define VADC_BRSSEL_CHSELG5_Msk \ - (0x20UL) /*!< VADC BRSSEL: CHSELG5 (Bitfield-Mask: 0x01) */ -#define VADC_BRSSEL_CHSELG6_Pos \ - (6UL) /*!< VADC BRSSEL: CHSELG6 (Bit 6) */ -#define VADC_BRSSEL_CHSELG6_Msk \ - (0x40UL) /*!< VADC BRSSEL: CHSELG6 (Bitfield-Mask: 0x01) */ -#define VADC_BRSSEL_CHSELG7_Pos \ - (7UL) /*!< VADC BRSSEL: CHSELG7 (Bit 7) */ -#define VADC_BRSSEL_CHSELG7_Msk \ - (0x80UL) /*!< VADC BRSSEL: CHSELG7 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- VADC_BRSPND -------------------------------- */ -#define VADC_BRSPND_CHPNDG0_Pos \ - (0UL) /*!< VADC BRSPND: CHPNDG0 (Bit 0) */ -#define VADC_BRSPND_CHPNDG0_Msk \ - (0x1UL) /*!< VADC BRSPND: CHPNDG0 (Bitfield-Mask: 0x01) */ -#define VADC_BRSPND_CHPNDG1_Pos \ - (1UL) /*!< VADC BRSPND: CHPNDG1 (Bit 1) */ -#define VADC_BRSPND_CHPNDG1_Msk \ - (0x2UL) /*!< VADC BRSPND: CHPNDG1 (Bitfield-Mask: 0x01) */ -#define VADC_BRSPND_CHPNDG2_Pos \ - (2UL) /*!< VADC BRSPND: CHPNDG2 (Bit 2) */ -#define VADC_BRSPND_CHPNDG2_Msk \ - (0x4UL) /*!< VADC BRSPND: CHPNDG2 (Bitfield-Mask: 0x01) */ -#define VADC_BRSPND_CHPNDG3_Pos \ - (3UL) /*!< VADC BRSPND: CHPNDG3 (Bit 3) */ -#define VADC_BRSPND_CHPNDG3_Msk \ - (0x8UL) /*!< VADC BRSPND: CHPNDG3 (Bitfield-Mask: 0x01) */ -#define VADC_BRSPND_CHPNDG4_Pos \ - (4UL) /*!< VADC BRSPND: CHPNDG4 (Bit 4) */ -#define VADC_BRSPND_CHPNDG4_Msk \ - (0x10UL) /*!< VADC BRSPND: CHPNDG4 (Bitfield-Mask: 0x01) */ -#define VADC_BRSPND_CHPNDG5_Pos \ - (5UL) /*!< VADC BRSPND: CHPNDG5 (Bit 5) */ -#define VADC_BRSPND_CHPNDG5_Msk \ - (0x20UL) /*!< VADC BRSPND: CHPNDG5 (Bitfield-Mask: 0x01) */ -#define VADC_BRSPND_CHPNDG6_Pos \ - (6UL) /*!< VADC BRSPND: CHPNDG6 (Bit 6) */ -#define VADC_BRSPND_CHPNDG6_Msk \ - (0x40UL) /*!< VADC BRSPND: CHPNDG6 (Bitfield-Mask: 0x01) */ -#define VADC_BRSPND_CHPNDG7_Pos \ - (7UL) /*!< VADC BRSPND: CHPNDG7 (Bit 7) */ -#define VADC_BRSPND_CHPNDG7_Msk \ - (0x80UL) /*!< VADC BRSPND: CHPNDG7 (Bitfield-Mask: 0x01) */ - -/* -------------------------------- VADC_BRSCTRL -------------------------------- */ -#define VADC_BRSCTRL_SRCRESREG_Pos \ - (0UL) /*!< VADC BRSCTRL: SRCRESREG (Bit 0) */ -#define VADC_BRSCTRL_SRCRESREG_Msk \ - (0xfUL) /*!< VADC BRSCTRL: SRCRESREG (Bitfield-Mask: 0x0f) */ -#define VADC_BRSCTRL_XTSEL_Pos \ - (8UL) /*!< VADC BRSCTRL: XTSEL (Bit 8) */ -#define VADC_BRSCTRL_XTSEL_Msk \ - (0xf00UL) /*!< VADC BRSCTRL: XTSEL (Bitfield-Mask: 0x0f) */ -#define VADC_BRSCTRL_XTLVL_Pos \ - (12UL) /*!< VADC BRSCTRL: XTLVL (Bit 12) */ -#define VADC_BRSCTRL_XTLVL_Msk \ - (0x1000UL) /*!< VADC BRSCTRL: XTLVL (Bitfield-Mask: 0x01) */ -#define VADC_BRSCTRL_XTMODE_Pos \ - (13UL) /*!< VADC BRSCTRL: XTMODE (Bit 13) */ -#define VADC_BRSCTRL_XTMODE_Msk \ - (0x6000UL) /*!< VADC BRSCTRL: XTMODE (Bitfield-Mask: 0x03) */ -#define VADC_BRSCTRL_XTWC_Pos \ - (15UL) /*!< VADC BRSCTRL: XTWC (Bit 15) */ -#define VADC_BRSCTRL_XTWC_Msk \ - (0x8000UL) /*!< VADC BRSCTRL: XTWC (Bitfield-Mask: 0x01) */ -#define VADC_BRSCTRL_GTSEL_Pos \ - (16UL) /*!< VADC BRSCTRL: GTSEL (Bit 16) */ -#define VADC_BRSCTRL_GTSEL_Msk \ - (0xf0000UL) /*!< VADC BRSCTRL: GTSEL (Bitfield-Mask: 0x0f) */ -#define VADC_BRSCTRL_GTLVL_Pos \ - (20UL) /*!< VADC BRSCTRL: GTLVL (Bit 20) */ -#define VADC_BRSCTRL_GTLVL_Msk \ - (0x100000UL) /*!< VADC BRSCTRL: GTLVL (Bitfield-Mask: 0x01) */ -#define VADC_BRSCTRL_GTWC_Pos \ - (23UL) /*!< VADC BRSCTRL: GTWC (Bit 23) */ -#define VADC_BRSCTRL_GTWC_Msk \ - (0x800000UL) /*!< VADC BRSCTRL: GTWC (Bitfield-Mask: 0x01) */ - -/* --------------------------------- VADC_BRSMR --------------------------------- */ -#define VADC_BRSMR_ENGT_Pos \ - (0UL) /*!< VADC BRSMR: ENGT (Bit 0) */ -#define VADC_BRSMR_ENGT_Msk \ - (0x3UL) /*!< VADC BRSMR: ENGT (Bitfield-Mask: 0x03) */ -#define VADC_BRSMR_ENTR_Pos \ - (2UL) /*!< VADC BRSMR: ENTR (Bit 2) */ -#define VADC_BRSMR_ENTR_Msk \ - (0x4UL) /*!< VADC BRSMR: ENTR (Bitfield-Mask: 0x01) */ -#define VADC_BRSMR_ENSI_Pos \ - (3UL) /*!< VADC BRSMR: ENSI (Bit 3) */ -#define VADC_BRSMR_ENSI_Msk \ - (0x8UL) /*!< VADC BRSMR: ENSI (Bitfield-Mask: 0x01) */ -#define VADC_BRSMR_SCAN_Pos \ - (4UL) /*!< VADC BRSMR: SCAN (Bit 4) */ -#define VADC_BRSMR_SCAN_Msk \ - (0x10UL) /*!< VADC BRSMR: SCAN (Bitfield-Mask: 0x01) */ -#define VADC_BRSMR_LDM_Pos (5UL) /*!< VADC BRSMR: LDM (Bit 5) */ -#define VADC_BRSMR_LDM_Msk \ - (0x20UL) /*!< VADC BRSMR: LDM (Bitfield-Mask: 0x01) */ -#define VADC_BRSMR_REQGT_Pos \ - (7UL) /*!< VADC BRSMR: REQGT (Bit 7) */ -#define VADC_BRSMR_REQGT_Msk \ - (0x80UL) /*!< VADC BRSMR: REQGT (Bitfield-Mask: 0x01) */ -#define VADC_BRSMR_CLRPND_Pos \ - (8UL) /*!< VADC BRSMR: CLRPND (Bit 8) */ -#define VADC_BRSMR_CLRPND_Msk \ - (0x100UL) /*!< VADC BRSMR: CLRPND (Bitfield-Mask: 0x01) */ -#define VADC_BRSMR_LDEV_Pos \ - (9UL) /*!< VADC BRSMR: LDEV (Bit 9) */ -#define VADC_BRSMR_LDEV_Msk \ - (0x200UL) /*!< VADC BRSMR: LDEV (Bitfield-Mask: 0x01) */ -#define VADC_BRSMR_RPTDIS_Pos \ - (16UL) /*!< VADC BRSMR: RPTDIS (Bit 16) */ -#define VADC_BRSMR_RPTDIS_Msk \ - (0x10000UL) /*!< VADC BRSMR: RPTDIS (Bitfield-Mask: 0x01) */ - -/* -------------------------------- VADC_GLOBRCR -------------------------------- */ -#define VADC_GLOBRCR_DRCTR_Pos \ - (16UL) /*!< VADC GLOBRCR: DRCTR (Bit 16) */ -#define VADC_GLOBRCR_DRCTR_Msk \ - (0xf0000UL) /*!< VADC GLOBRCR: DRCTR (Bitfield-Mask: 0x0f) */ -#define VADC_GLOBRCR_WFR_Pos \ - (24UL) /*!< VADC GLOBRCR: WFR (Bit 24) */ -#define VADC_GLOBRCR_WFR_Msk \ - (0x1000000UL) /*!< VADC GLOBRCR: WFR (Bitfield-Mask: 0x01) */ -#define VADC_GLOBRCR_SRGEN_Pos \ - (31UL) /*!< VADC GLOBRCR: SRGEN (Bit 31) */ -#define VADC_GLOBRCR_SRGEN_Msk \ - (0x80000000UL) /*!< VADC GLOBRCR: SRGEN (Bitfield-Mask: 0x01) */ - -/* -------------------------------- VADC_GLOBRES -------------------------------- */ -#define VADC_GLOBRES_RESULT_Pos \ - (0UL) /*!< VADC GLOBRES: RESULT (Bit 0) */ -#define VADC_GLOBRES_RESULT_Msk \ - (0xffffUL) /*!< VADC GLOBRES: RESULT (Bitfield-Mask: 0xffff) */ -#define VADC_GLOBRES_GNR_Pos \ - (16UL) /*!< VADC GLOBRES: GNR (Bit 16) */ -#define VADC_GLOBRES_GNR_Msk \ - (0xf0000UL) /*!< VADC GLOBRES: GNR (Bitfield-Mask: 0x0f) */ -#define VADC_GLOBRES_CHNR_Pos \ - (20UL) /*!< VADC GLOBRES: CHNR (Bit 20) */ -#define VADC_GLOBRES_CHNR_Msk \ - (0x1f00000UL) /*!< VADC GLOBRES: CHNR (Bitfield-Mask: 0x1f) */ -#define VADC_GLOBRES_EMUX_Pos \ - (25UL) /*!< VADC GLOBRES: EMUX (Bit 25) */ -#define VADC_GLOBRES_EMUX_Msk \ - (0xe000000UL) /*!< VADC GLOBRES: EMUX (Bitfield-Mask: 0x07) */ -#define VADC_GLOBRES_CRS_Pos \ - (28UL) /*!< VADC GLOBRES: CRS (Bit 28) */ -#define VADC_GLOBRES_CRS_Msk \ - (0x30000000UL) /*!< VADC GLOBRES: CRS (Bitfield-Mask: 0x03) */ -#define VADC_GLOBRES_FCR_Pos \ - (30UL) /*!< VADC GLOBRES: FCR (Bit 30) */ -#define VADC_GLOBRES_FCR_Msk \ - (0x40000000UL) /*!< VADC GLOBRES: FCR (Bitfield-Mask: 0x01) */ -#define VADC_GLOBRES_VF_Pos \ - (31UL) /*!< VADC GLOBRES: VF (Bit 31) */ -#define VADC_GLOBRES_VF_Msk \ - (0x80000000UL) /*!< VADC GLOBRES: VF (Bitfield-Mask: 0x01) */ - -/* -------------------------------- VADC_GLOBRESD ------------------------------- */ -#define VADC_GLOBRESD_RESULT_Pos \ - (0UL) /*!< VADC GLOBRESD: RESULT (Bit 0) */ -#define VADC_GLOBRESD_RESULT_Msk \ - (0xffffUL) /*!< VADC GLOBRESD: RESULT (Bitfield-Mask: 0xffff) */ -#define VADC_GLOBRESD_GNR_Pos \ - (16UL) /*!< VADC GLOBRESD: GNR (Bit 16) */ -#define VADC_GLOBRESD_GNR_Msk \ - (0xf0000UL) /*!< VADC GLOBRESD: GNR (Bitfield-Mask: 0x0f) */ -#define VADC_GLOBRESD_CHNR_Pos \ - (20UL) /*!< VADC GLOBRESD: CHNR (Bit 20) */ -#define VADC_GLOBRESD_CHNR_Msk \ - (0x1f00000UL) /*!< VADC GLOBRESD: CHNR (Bitfield-Mask: 0x1f) */ -#define VADC_GLOBRESD_EMUX_Pos \ - (25UL) /*!< VADC GLOBRESD: EMUX (Bit 25) */ -#define VADC_GLOBRESD_EMUX_Msk \ - (0xe000000UL) /*!< VADC GLOBRESD: EMUX (Bitfield-Mask: 0x07) */ -#define VADC_GLOBRESD_CRS_Pos \ - (28UL) /*!< VADC GLOBRESD: CRS (Bit 28) */ -#define VADC_GLOBRESD_CRS_Msk \ - (0x30000000UL) /*!< VADC GLOBRESD: CRS (Bitfield-Mask: 0x03) */ -#define VADC_GLOBRESD_FCR_Pos \ - (30UL) /*!< VADC GLOBRESD: FCR (Bit 30) */ -#define VADC_GLOBRESD_FCR_Msk \ - (0x40000000UL) /*!< VADC GLOBRESD: FCR (Bitfield-Mask: 0x01) */ -#define VADC_GLOBRESD_VF_Pos \ - (31UL) /*!< VADC GLOBRESD: VF (Bit 31) */ -#define VADC_GLOBRESD_VF_Msk \ - (0x80000000UL) /*!< VADC GLOBRESD: VF (Bitfield-Mask: 0x01) */ - -/* -------------------------------- VADC_EMUXSEL -------------------------------- */ -#define VADC_EMUXSEL_EMUXGRP0_Pos \ - (0UL) /*!< VADC EMUXSEL: EMUXGRP0 (Bit 0) */ -#define VADC_EMUXSEL_EMUXGRP0_Msk \ - (0xfUL) /*!< VADC EMUXSEL: EMUXGRP0 (Bitfield-Mask: 0x0f) */ -#define VADC_EMUXSEL_EMUXGRP1_Pos \ - (4UL) /*!< VADC EMUXSEL: EMUXGRP1 (Bit 4) */ -#define VADC_EMUXSEL_EMUXGRP1_Msk \ - (0xf0UL) /*!< VADC EMUXSEL: EMUXGRP1 (Bitfield-Mask: 0x0f) */ - -/* ================================================================================ */ -/* ================ Group 'VADC_G' Position & Mask ================ */ -/* ================================================================================ */ - -/* -------------------------------- VADC_G_ARBCFG ------------------------------- */ -#define VADC_G_ARBCFG_ANONC_Pos \ - (0UL) /*!< VADC_G ARBCFG: ANONC (Bit 0) */ -#define VADC_G_ARBCFG_ANONC_Msk \ - (0x3UL) /*!< VADC_G ARBCFG: ANONC (Bitfield-Mask: 0x03) */ -#define VADC_G_ARBCFG_ARBRND_Pos \ - (4UL) /*!< VADC_G ARBCFG: ARBRND (Bit 4) */ -#define VADC_G_ARBCFG_ARBRND_Msk \ - (0x30UL) /*!< VADC_G ARBCFG: ARBRND (Bitfield-Mask: 0x03) */ -#define VADC_G_ARBCFG_ARBM_Pos \ - (7UL) /*!< VADC_G ARBCFG: ARBM (Bit 7) */ -#define VADC_G_ARBCFG_ARBM_Msk \ - (0x80UL) /*!< VADC_G ARBCFG: ARBM (Bitfield-Mask: 0x01) */ -#define VADC_G_ARBCFG_ANONS_Pos \ - (16UL) /*!< VADC_G ARBCFG: ANONS (Bit 16) */ -#define VADC_G_ARBCFG_ANONS_Msk \ - (0x30000UL) /*!< VADC_G ARBCFG: ANONS (Bitfield-Mask: 0x03) */ -#define VADC_G_ARBCFG_CAL_Pos \ - (28UL) /*!< VADC_G ARBCFG: CAL (Bit 28) */ -#define VADC_G_ARBCFG_CAL_Msk \ - (0x10000000UL) /*!< VADC_G ARBCFG: CAL (Bitfield-Mask: 0x01) */ -#define VADC_G_ARBCFG_BUSY_Pos \ - (30UL) /*!< VADC_G ARBCFG: BUSY (Bit 30) */ -#define VADC_G_ARBCFG_BUSY_Msk \ - (0x40000000UL) /*!< VADC_G ARBCFG: BUSY (Bitfield-Mask: 0x01) */ -#define VADC_G_ARBCFG_SAMPLE_Pos \ - (31UL) /*!< VADC_G ARBCFG: SAMPLE (Bit 31) */ -#define VADC_G_ARBCFG_SAMPLE_Msk \ - (0x80000000UL) /*!< VADC_G ARBCFG: SAMPLE (Bitfield-Mask: 0x01) */ - -/* -------------------------------- VADC_G_ARBPR -------------------------------- */ -#define VADC_G_ARBPR_PRIO0_Pos \ - (0UL) /*!< VADC_G ARBPR: PRIO0 (Bit 0) */ -#define VADC_G_ARBPR_PRIO0_Msk \ - (0x3UL) /*!< VADC_G ARBPR: PRIO0 (Bitfield-Mask: 0x03) */ -#define VADC_G_ARBPR_CSM0_Pos \ - (3UL) /*!< VADC_G ARBPR: CSM0 (Bit 3) */ -#define VADC_G_ARBPR_CSM0_Msk \ - (0x8UL) /*!< VADC_G ARBPR: CSM0 (Bitfield-Mask: 0x01) */ -#define VADC_G_ARBPR_PRIO1_Pos \ - (4UL) /*!< VADC_G ARBPR: PRIO1 (Bit 4) */ -#define VADC_G_ARBPR_PRIO1_Msk \ - (0x30UL) /*!< VADC_G ARBPR: PRIO1 (Bitfield-Mask: 0x03) */ -#define VADC_G_ARBPR_CSM1_Pos \ - (7UL) /*!< VADC_G ARBPR: CSM1 (Bit 7) */ -#define VADC_G_ARBPR_CSM1_Msk \ - (0x80UL) /*!< VADC_G ARBPR: CSM1 (Bitfield-Mask: 0x01) */ -#define VADC_G_ARBPR_PRIO2_Pos \ - (8UL) /*!< VADC_G ARBPR: PRIO2 (Bit 8) */ -#define VADC_G_ARBPR_PRIO2_Msk \ - (0x300UL) /*!< VADC_G ARBPR: PRIO2 (Bitfield-Mask: 0x03) */ -#define VADC_G_ARBPR_CSM2_Pos \ - (11UL) /*!< VADC_G ARBPR: CSM2 (Bit 11) */ -#define VADC_G_ARBPR_CSM2_Msk \ - (0x800UL) /*!< VADC_G ARBPR: CSM2 (Bitfield-Mask: 0x01) */ -#define VADC_G_ARBPR_ASEN0_Pos \ - (24UL) /*!< VADC_G ARBPR: ASEN0 (Bit 24) */ -#define VADC_G_ARBPR_ASEN0_Msk \ - (0x1000000UL) /*!< VADC_G ARBPR: ASEN0 (Bitfield-Mask: 0x01) */ -#define VADC_G_ARBPR_ASEN1_Pos \ - (25UL) /*!< VADC_G ARBPR: ASEN1 (Bit 25) */ -#define VADC_G_ARBPR_ASEN1_Msk \ - (0x2000000UL) /*!< VADC_G ARBPR: ASEN1 (Bitfield-Mask: 0x01) */ -#define VADC_G_ARBPR_ASEN2_Pos \ - (26UL) /*!< VADC_G ARBPR: ASEN2 (Bit 26) */ -#define VADC_G_ARBPR_ASEN2_Msk \ - (0x4000000UL) /*!< VADC_G ARBPR: ASEN2 (Bitfield-Mask: 0x01) */ - -/* -------------------------------- VADC_G_CHASS -------------------------------- */ -#define VADC_G_CHASS_ASSCH0_Pos \ - (0UL) /*!< VADC_G CHASS: ASSCH0 (Bit 0) */ -#define VADC_G_CHASS_ASSCH0_Msk \ - (0x1UL) /*!< VADC_G CHASS: ASSCH0 (Bitfield-Mask: 0x01) */ -#define VADC_G_CHASS_ASSCH1_Pos \ - (1UL) /*!< VADC_G CHASS: ASSCH1 (Bit 1) */ -#define VADC_G_CHASS_ASSCH1_Msk \ - (0x2UL) /*!< VADC_G CHASS: ASSCH1 (Bitfield-Mask: 0x01) */ -#define VADC_G_CHASS_ASSCH2_Pos \ - (2UL) /*!< VADC_G CHASS: ASSCH2 (Bit 2) */ -#define VADC_G_CHASS_ASSCH2_Msk \ - (0x4UL) /*!< VADC_G CHASS: ASSCH2 (Bitfield-Mask: 0x01) */ -#define VADC_G_CHASS_ASSCH3_Pos \ - (3UL) /*!< VADC_G CHASS: ASSCH3 (Bit 3) */ -#define VADC_G_CHASS_ASSCH3_Msk \ - (0x8UL) /*!< VADC_G CHASS: ASSCH3 (Bitfield-Mask: 0x01) */ -#define VADC_G_CHASS_ASSCH4_Pos \ - (4UL) /*!< VADC_G CHASS: ASSCH4 (Bit 4) */ -#define VADC_G_CHASS_ASSCH4_Msk \ - (0x10UL) /*!< VADC_G CHASS: ASSCH4 (Bitfield-Mask: 0x01) */ -#define VADC_G_CHASS_ASSCH5_Pos \ - (5UL) /*!< VADC_G CHASS: ASSCH5 (Bit 5) */ -#define VADC_G_CHASS_ASSCH5_Msk \ - (0x20UL) /*!< VADC_G CHASS: ASSCH5 (Bitfield-Mask: 0x01) */ -#define VADC_G_CHASS_ASSCH6_Pos \ - (6UL) /*!< VADC_G CHASS: ASSCH6 (Bit 6) */ -#define VADC_G_CHASS_ASSCH6_Msk \ - (0x40UL) /*!< VADC_G CHASS: ASSCH6 (Bitfield-Mask: 0x01) */ -#define VADC_G_CHASS_ASSCH7_Pos \ - (7UL) /*!< VADC_G CHASS: ASSCH7 (Bit 7) */ -#define VADC_G_CHASS_ASSCH7_Msk \ - (0x80UL) /*!< VADC_G CHASS: ASSCH7 (Bitfield-Mask: 0x01) */ - -/* -------------------------------- VADC_G_ICLASS ------------------------------- */ -#define VADC_G_ICLASS_STCS_Pos \ - (0UL) /*!< VADC_G ICLASS: STCS (Bit 0) */ -#define VADC_G_ICLASS_STCS_Msk \ - (0x1fUL) /*!< VADC_G ICLASS: STCS (Bitfield-Mask: 0x1f) */ -#define VADC_G_ICLASS_CMS_Pos \ - (8UL) /*!< VADC_G ICLASS: CMS (Bit 8) */ -#define VADC_G_ICLASS_CMS_Msk \ - (0x700UL) /*!< VADC_G ICLASS: CMS (Bitfield-Mask: 0x07) */ -#define VADC_G_ICLASS_STCE_Pos \ - (16UL) /*!< VADC_G ICLASS: STCE (Bit 16) */ -#define VADC_G_ICLASS_STCE_Msk \ - (0x1f0000UL) /*!< VADC_G ICLASS: STCE (Bitfield-Mask: 0x1f) */ -#define VADC_G_ICLASS_CME_Pos \ - (24UL) /*!< VADC_G ICLASS: CME (Bit 24) */ -#define VADC_G_ICLASS_CME_Msk \ - (0x7000000UL) /*!< VADC_G ICLASS: CME (Bitfield-Mask: 0x07) */ - -/* -------------------------------- VADC_G_ALIAS -------------------------------- */ -#define VADC_G_ALIAS_ALIAS0_Pos \ - (0UL) /*!< VADC_G ALIAS: ALIAS0 (Bit 0) */ -#define VADC_G_ALIAS_ALIAS0_Msk \ - (0x1fUL) /*!< VADC_G ALIAS: ALIAS0 (Bitfield-Mask: 0x1f) */ -#define VADC_G_ALIAS_ALIAS1_Pos \ - (8UL) /*!< VADC_G ALIAS: ALIAS1 (Bit 8) */ -#define VADC_G_ALIAS_ALIAS1_Msk \ - (0x1f00UL) /*!< VADC_G ALIAS: ALIAS1 (Bitfield-Mask: 0x1f) */ - -/* -------------------------------- VADC_G_BOUND -------------------------------- */ -#define VADC_G_BOUND_BOUNDARY0_Pos \ - (0UL) /*!< VADC_G BOUND: BOUNDARY0 (Bit 0) */ -#define VADC_G_BOUND_BOUNDARY0_Msk \ - (0xfffUL) /*!< VADC_G BOUND: BOUNDARY0 (Bitfield-Mask: 0xfff) */ -#define VADC_G_BOUND_BOUNDARY1_Pos \ - (16UL) /*!< VADC_G BOUND: BOUNDARY1 (Bit 16) */ -#define VADC_G_BOUND_BOUNDARY1_Msk \ - (0xfff0000UL) /*!< VADC_G BOUND: BOUNDARY1 (Bitfield-Mask: 0xfff) */ - -/* -------------------------------- VADC_G_SYNCTR ------------------------------- */ -#define VADC_G_SYNCTR_STSEL_Pos \ - (0UL) /*!< VADC_G SYNCTR: STSEL (Bit 0) */ -#define VADC_G_SYNCTR_STSEL_Msk \ - (0x3UL) /*!< VADC_G SYNCTR: STSEL (Bitfield-Mask: 0x03) */ -#define VADC_G_SYNCTR_EVALR1_Pos \ - (4UL) /*!< VADC_G SYNCTR: EVALR1 (Bit 4) */ -#define VADC_G_SYNCTR_EVALR1_Msk \ - (0x10UL) /*!< VADC_G SYNCTR: EVALR1 (Bitfield-Mask: 0x01) */ -#define VADC_G_SYNCTR_EVALR2_Pos \ - (5UL) /*!< VADC_G SYNCTR: EVALR2 (Bit 5) */ -#define VADC_G_SYNCTR_EVALR2_Msk \ - (0x20UL) /*!< VADC_G SYNCTR: EVALR2 (Bitfield-Mask: 0x01) */ -#define VADC_G_SYNCTR_EVALR3_Pos \ - (6UL) /*!< VADC_G SYNCTR: EVALR3 (Bit 6) */ -#define VADC_G_SYNCTR_EVALR3_Msk \ - (0x40UL) /*!< VADC_G SYNCTR: EVALR3 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- VADC_G_BFL --------------------------------- */ -#define VADC_G_BFL_BFL0_Pos \ - (0UL) /*!< VADC_G BFL: BFL0 (Bit 0) */ -#define VADC_G_BFL_BFL0_Msk \ - (0x1UL) /*!< VADC_G BFL: BFL0 (Bitfield-Mask: 0x01) */ -#define VADC_G_BFL_BFL1_Pos \ - (1UL) /*!< VADC_G BFL: BFL1 (Bit 1) */ -#define VADC_G_BFL_BFL1_Msk \ - (0x2UL) /*!< VADC_G BFL: BFL1 (Bitfield-Mask: 0x01) */ -#define VADC_G_BFL_BFL2_Pos \ - (2UL) /*!< VADC_G BFL: BFL2 (Bit 2) */ -#define VADC_G_BFL_BFL2_Msk \ - (0x4UL) /*!< VADC_G BFL: BFL2 (Bitfield-Mask: 0x01) */ -#define VADC_G_BFL_BFL3_Pos \ - (3UL) /*!< VADC_G BFL: BFL3 (Bit 3) */ -#define VADC_G_BFL_BFL3_Msk \ - (0x8UL) /*!< VADC_G BFL: BFL3 (Bitfield-Mask: 0x01) */ -#define VADC_G_BFL_BFA0_Pos \ - (8UL) /*!< VADC_G BFL: BFA0 (Bit 8) */ -#define VADC_G_BFL_BFA0_Msk \ - (0x100UL) /*!< VADC_G BFL: BFA0 (Bitfield-Mask: 0x01) */ -#define VADC_G_BFL_BFA1_Pos \ - (9UL) /*!< VADC_G BFL: BFA1 (Bit 9) */ -#define VADC_G_BFL_BFA1_Msk \ - (0x200UL) /*!< VADC_G BFL: BFA1 (Bitfield-Mask: 0x01) */ -#define VADC_G_BFL_BFA2_Pos \ - (10UL) /*!< VADC_G BFL: BFA2 (Bit 10) */ -#define VADC_G_BFL_BFA2_Msk \ - (0x400UL) /*!< VADC_G BFL: BFA2 (Bitfield-Mask: 0x01) */ -#define VADC_G_BFL_BFA3_Pos \ - (11UL) /*!< VADC_G BFL: BFA3 (Bit 11) */ -#define VADC_G_BFL_BFA3_Msk \ - (0x800UL) /*!< VADC_G BFL: BFA3 (Bitfield-Mask: 0x01) */ -#define VADC_G_BFL_BFI0_Pos \ - (16UL) /*!< VADC_G BFL: BFI0 (Bit 16) */ -#define VADC_G_BFL_BFI0_Msk \ - (0x10000UL) /*!< VADC_G BFL: BFI0 (Bitfield-Mask: 0x01) */ -#define VADC_G_BFL_BFI1_Pos \ - (17UL) /*!< VADC_G BFL: BFI1 (Bit 17) */ -#define VADC_G_BFL_BFI1_Msk \ - (0x20000UL) /*!< VADC_G BFL: BFI1 (Bitfield-Mask: 0x01) */ -#define VADC_G_BFL_BFI2_Pos \ - (18UL) /*!< VADC_G BFL: BFI2 (Bit 18) */ -#define VADC_G_BFL_BFI2_Msk \ - (0x40000UL) /*!< VADC_G BFL: BFI2 (Bitfield-Mask: 0x01) */ -#define VADC_G_BFL_BFI3_Pos \ - (19UL) /*!< VADC_G BFL: BFI3 (Bit 19) */ -#define VADC_G_BFL_BFI3_Msk \ - (0x80000UL) /*!< VADC_G BFL: BFI3 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- VADC_G_BFLS -------------------------------- */ -#define VADC_G_BFLS_BFC0_Pos \ - (0UL) /*!< VADC_G BFLS: BFC0 (Bit 0) */ -#define VADC_G_BFLS_BFC0_Msk \ - (0x1UL) /*!< VADC_G BFLS: BFC0 (Bitfield-Mask: 0x01) */ -#define VADC_G_BFLS_BFC1_Pos \ - (1UL) /*!< VADC_G BFLS: BFC1 (Bit 1) */ -#define VADC_G_BFLS_BFC1_Msk \ - (0x2UL) /*!< VADC_G BFLS: BFC1 (Bitfield-Mask: 0x01) */ -#define VADC_G_BFLS_BFC2_Pos \ - (2UL) /*!< VADC_G BFLS: BFC2 (Bit 2) */ -#define VADC_G_BFLS_BFC2_Msk \ - (0x4UL) /*!< VADC_G BFLS: BFC2 (Bitfield-Mask: 0x01) */ -#define VADC_G_BFLS_BFC3_Pos \ - (3UL) /*!< VADC_G BFLS: BFC3 (Bit 3) */ -#define VADC_G_BFLS_BFC3_Msk \ - (0x8UL) /*!< VADC_G BFLS: BFC3 (Bitfield-Mask: 0x01) */ -#define VADC_G_BFLS_BFS0_Pos \ - (16UL) /*!< VADC_G BFLS: BFS0 (Bit 16) */ -#define VADC_G_BFLS_BFS0_Msk \ - (0x10000UL) /*!< VADC_G BFLS: BFS0 (Bitfield-Mask: 0x01) */ -#define VADC_G_BFLS_BFS1_Pos \ - (17UL) /*!< VADC_G BFLS: BFS1 (Bit 17) */ -#define VADC_G_BFLS_BFS1_Msk \ - (0x20000UL) /*!< VADC_G BFLS: BFS1 (Bitfield-Mask: 0x01) */ -#define VADC_G_BFLS_BFS2_Pos \ - (18UL) /*!< VADC_G BFLS: BFS2 (Bit 18) */ -#define VADC_G_BFLS_BFS2_Msk \ - (0x40000UL) /*!< VADC_G BFLS: BFS2 (Bitfield-Mask: 0x01) */ -#define VADC_G_BFLS_BFS3_Pos \ - (19UL) /*!< VADC_G BFLS: BFS3 (Bit 19) */ -#define VADC_G_BFLS_BFS3_Msk \ - (0x80000UL) /*!< VADC_G BFLS: BFS3 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- VADC_G_BFLC -------------------------------- */ -#define VADC_G_BFLC_BFM0_Pos \ - (0UL) /*!< VADC_G BFLC: BFM0 (Bit 0) */ -#define VADC_G_BFLC_BFM0_Msk \ - (0xfUL) /*!< VADC_G BFLC: BFM0 (Bitfield-Mask: 0x0f) */ -#define VADC_G_BFLC_BFM1_Pos \ - (4UL) /*!< VADC_G BFLC: BFM1 (Bit 4) */ -#define VADC_G_BFLC_BFM1_Msk \ - (0xf0UL) /*!< VADC_G BFLC: BFM1 (Bitfield-Mask: 0x0f) */ -#define VADC_G_BFLC_BFM2_Pos \ - (8UL) /*!< VADC_G BFLC: BFM2 (Bit 8) */ -#define VADC_G_BFLC_BFM2_Msk \ - (0xf00UL) /*!< VADC_G BFLC: BFM2 (Bitfield-Mask: 0x0f) */ -#define VADC_G_BFLC_BFM3_Pos \ - (12UL) /*!< VADC_G BFLC: BFM3 (Bit 12) */ -#define VADC_G_BFLC_BFM3_Msk \ - (0xf000UL) /*!< VADC_G BFLC: BFM3 (Bitfield-Mask: 0x0f) */ - -/* -------------------------------- VADC_G_BFLNP -------------------------------- */ -#define VADC_G_BFLNP_BFL0NP_Pos \ - (0UL) /*!< VADC_G BFLNP: BFL0NP (Bit 0) */ -#define VADC_G_BFLNP_BFL0NP_Msk \ - (0xfUL) /*!< VADC_G BFLNP: BFL0NP (Bitfield-Mask: 0x0f) */ -#define VADC_G_BFLNP_BFL1NP_Pos \ - (4UL) /*!< VADC_G BFLNP: BFL1NP (Bit 4) */ -#define VADC_G_BFLNP_BFL1NP_Msk \ - (0xf0UL) /*!< VADC_G BFLNP: BFL1NP (Bitfield-Mask: 0x0f) */ -#define VADC_G_BFLNP_BFL2NP_Pos \ - (8UL) /*!< VADC_G BFLNP: BFL2NP (Bit 8) */ -#define VADC_G_BFLNP_BFL2NP_Msk \ - (0xf00UL) /*!< VADC_G BFLNP: BFL2NP (Bitfield-Mask: 0x0f) */ -#define VADC_G_BFLNP_BFL3NP_Pos \ - (12UL) /*!< VADC_G BFLNP: BFL3NP (Bit 12) */ -#define VADC_G_BFLNP_BFL3NP_Msk \ - (0xf000UL) /*!< VADC_G BFLNP: BFL3NP (Bitfield-Mask: 0x0f) */ - -/* -------------------------------- VADC_G_QCTRL0 ------------------------------- */ -#define VADC_G_QCTRL0_SRCRESREG_Pos \ - (0UL) /*!< VADC_G QCTRL0: SRCRESREG (Bit 0) */ -#define VADC_G_QCTRL0_SRCRESREG_Msk \ - (0xfUL) /*!< VADC_G QCTRL0: SRCRESREG (Bitfield-Mask: 0x0f) */ -#define VADC_G_QCTRL0_XTSEL_Pos \ - (8UL) /*!< VADC_G QCTRL0: XTSEL (Bit 8) */ -#define VADC_G_QCTRL0_XTSEL_Msk \ - (0xf00UL) /*!< VADC_G QCTRL0: XTSEL (Bitfield-Mask: 0x0f) */ -#define VADC_G_QCTRL0_XTLVL_Pos \ - (12UL) /*!< VADC_G QCTRL0: XTLVL (Bit 12) */ -#define VADC_G_QCTRL0_XTLVL_Msk \ - (0x1000UL) /*!< VADC_G QCTRL0: XTLVL (Bitfield-Mask: 0x01) */ -#define VADC_G_QCTRL0_XTMODE_Pos \ - (13UL) /*!< VADC_G QCTRL0: XTMODE (Bit 13) */ -#define VADC_G_QCTRL0_XTMODE_Msk \ - (0x6000UL) /*!< VADC_G QCTRL0: XTMODE (Bitfield-Mask: 0x03) */ -#define VADC_G_QCTRL0_XTWC_Pos \ - (15UL) /*!< VADC_G QCTRL0: XTWC (Bit 15) */ -#define VADC_G_QCTRL0_XTWC_Msk \ - (0x8000UL) /*!< VADC_G QCTRL0: XTWC (Bitfield-Mask: 0x01) */ -#define VADC_G_QCTRL0_GTSEL_Pos \ - (16UL) /*!< VADC_G QCTRL0: GTSEL (Bit 16) */ -#define VADC_G_QCTRL0_GTSEL_Msk \ - (0xf0000UL) /*!< VADC_G QCTRL0: GTSEL (Bitfield-Mask: 0x0f) */ -#define VADC_G_QCTRL0_GTLVL_Pos \ - (20UL) /*!< VADC_G QCTRL0: GTLVL (Bit 20) */ -#define VADC_G_QCTRL0_GTLVL_Msk \ - (0x100000UL) /*!< VADC_G QCTRL0: GTLVL (Bitfield-Mask: 0x01) */ -#define VADC_G_QCTRL0_GTWC_Pos \ - (23UL) /*!< VADC_G QCTRL0: GTWC (Bit 23) */ -#define VADC_G_QCTRL0_GTWC_Msk \ - (0x800000UL) /*!< VADC_G QCTRL0: GTWC (Bitfield-Mask: 0x01) */ -#define VADC_G_QCTRL0_TMEN_Pos \ - (28UL) /*!< VADC_G QCTRL0: TMEN (Bit 28) */ -#define VADC_G_QCTRL0_TMEN_Msk \ - (0x10000000UL) /*!< VADC_G QCTRL0: TMEN (Bitfield-Mask: 0x01) */ -#define VADC_G_QCTRL0_TMWC_Pos \ - (31UL) /*!< VADC_G QCTRL0: TMWC (Bit 31) */ -#define VADC_G_QCTRL0_TMWC_Msk \ - (0x80000000UL) /*!< VADC_G QCTRL0: TMWC (Bitfield-Mask: 0x01) */ - -/* --------------------------------- VADC_G_QMR0 -------------------------------- */ -#define VADC_G_QMR0_ENGT_Pos \ - (0UL) /*!< VADC_G QMR0: ENGT (Bit 0) */ -#define VADC_G_QMR0_ENGT_Msk \ - (0x3UL) /*!< VADC_G QMR0: ENGT (Bitfield-Mask: 0x03) */ -#define VADC_G_QMR0_ENTR_Pos \ - (2UL) /*!< VADC_G QMR0: ENTR (Bit 2) */ -#define VADC_G_QMR0_ENTR_Msk \ - (0x4UL) /*!< VADC_G QMR0: ENTR (Bitfield-Mask: 0x01) */ -#define VADC_G_QMR0_CLRV_Pos \ - (8UL) /*!< VADC_G QMR0: CLRV (Bit 8) */ -#define VADC_G_QMR0_CLRV_Msk \ - (0x100UL) /*!< VADC_G QMR0: CLRV (Bitfield-Mask: 0x01) */ -#define VADC_G_QMR0_TREV_Pos \ - (9UL) /*!< VADC_G QMR0: TREV (Bit 9) */ -#define VADC_G_QMR0_TREV_Msk \ - (0x200UL) /*!< VADC_G QMR0: TREV (Bitfield-Mask: 0x01) */ -#define VADC_G_QMR0_FLUSH_Pos \ - (10UL) /*!< VADC_G QMR0: FLUSH (Bit 10) */ -#define VADC_G_QMR0_FLUSH_Msk \ - (0x400UL) /*!< VADC_G QMR0: FLUSH (Bitfield-Mask: 0x01) */ -#define VADC_G_QMR0_CEV_Pos \ - (11UL) /*!< VADC_G QMR0: CEV (Bit 11) */ -#define VADC_G_QMR0_CEV_Msk \ - (0x800UL) /*!< VADC_G QMR0: CEV (Bitfield-Mask: 0x01) */ -#define VADC_G_QMR0_RPTDIS_Pos \ - (16UL) /*!< VADC_G QMR0: RPTDIS (Bit 16) */ -#define VADC_G_QMR0_RPTDIS_Msk \ - (0x10000UL) /*!< VADC_G QMR0: RPTDIS (Bitfield-Mask: 0x01) */ - -/* --------------------------------- VADC_G_QSR0 -------------------------------- */ -#define VADC_G_QSR0_FILL_Pos \ - (0UL) /*!< VADC_G QSR0: FILL (Bit 0) */ -#define VADC_G_QSR0_FILL_Msk \ - (0xfUL) /*!< VADC_G QSR0: FILL (Bitfield-Mask: 0x0f) */ -#define VADC_G_QSR0_EMPTY_Pos \ - (5UL) /*!< VADC_G QSR0: EMPTY (Bit 5) */ -#define VADC_G_QSR0_EMPTY_Msk \ - (0x20UL) /*!< VADC_G QSR0: EMPTY (Bitfield-Mask: 0x01) */ -#define VADC_G_QSR0_REQGT_Pos \ - (7UL) /*!< VADC_G QSR0: REQGT (Bit 7) */ -#define VADC_G_QSR0_REQGT_Msk \ - (0x80UL) /*!< VADC_G QSR0: REQGT (Bitfield-Mask: 0x01) */ -#define VADC_G_QSR0_EV_Pos (8UL) /*!< VADC_G QSR0: EV (Bit 8) */ -#define VADC_G_QSR0_EV_Msk \ - (0x100UL) /*!< VADC_G QSR0: EV (Bitfield-Mask: 0x01) */ - -/* --------------------------------- VADC_G_Q0R0 -------------------------------- */ -#define VADC_G_Q0R0_REQCHNR_Pos \ - (0UL) /*!< VADC_G Q0R0: REQCHNR (Bit 0) */ -#define VADC_G_Q0R0_REQCHNR_Msk \ - (0x1fUL) /*!< VADC_G Q0R0: REQCHNR (Bitfield-Mask: 0x1f) */ -#define VADC_G_Q0R0_RF_Pos (5UL) /*!< VADC_G Q0R0: RF (Bit 5) */ -#define VADC_G_Q0R0_RF_Msk \ - (0x20UL) /*!< VADC_G Q0R0: RF (Bitfield-Mask: 0x01) */ -#define VADC_G_Q0R0_ENSI_Pos \ - (6UL) /*!< VADC_G Q0R0: ENSI (Bit 6) */ -#define VADC_G_Q0R0_ENSI_Msk \ - (0x40UL) /*!< VADC_G Q0R0: ENSI (Bitfield-Mask: 0x01) */ -#define VADC_G_Q0R0_EXTR_Pos \ - (7UL) /*!< VADC_G Q0R0: EXTR (Bit 7) */ -#define VADC_G_Q0R0_EXTR_Msk \ - (0x80UL) /*!< VADC_G Q0R0: EXTR (Bitfield-Mask: 0x01) */ -#define VADC_G_Q0R0_V_Pos (8UL) /*!< VADC_G Q0R0: V (Bit 8) */ -#define VADC_G_Q0R0_V_Msk \ - (0x100UL) /*!< VADC_G Q0R0: V (Bitfield-Mask: 0x01) */ - -/* -------------------------------- VADC_G_QINR0 -------------------------------- */ -#define VADC_G_QINR0_REQCHNR_Pos \ - (0UL) /*!< VADC_G QINR0: REQCHNR (Bit 0) */ -#define VADC_G_QINR0_REQCHNR_Msk \ - (0x1fUL) /*!< VADC_G QINR0: REQCHNR (Bitfield-Mask: 0x1f) */ -#define VADC_G_QINR0_RF_Pos \ - (5UL) /*!< VADC_G QINR0: RF (Bit 5) */ -#define VADC_G_QINR0_RF_Msk \ - (0x20UL) /*!< VADC_G QINR0: RF (Bitfield-Mask: 0x01) */ -#define VADC_G_QINR0_ENSI_Pos \ - (6UL) /*!< VADC_G QINR0: ENSI (Bit 6) */ -#define VADC_G_QINR0_ENSI_Msk \ - (0x40UL) /*!< VADC_G QINR0: ENSI (Bitfield-Mask: 0x01) */ -#define VADC_G_QINR0_EXTR_Pos \ - (7UL) /*!< VADC_G QINR0: EXTR (Bit 7) */ -#define VADC_G_QINR0_EXTR_Msk \ - (0x80UL) /*!< VADC_G QINR0: EXTR (Bitfield-Mask: 0x01) */ - -/* -------------------------------- VADC_G_QBUR0 -------------------------------- */ -#define VADC_G_QBUR0_REQCHNR_Pos \ - (0UL) /*!< VADC_G QBUR0: REQCHNR (Bit 0) */ -#define VADC_G_QBUR0_REQCHNR_Msk \ - (0x1fUL) /*!< VADC_G QBUR0: REQCHNR (Bitfield-Mask: 0x1f) */ -#define VADC_G_QBUR0_RF_Pos \ - (5UL) /*!< VADC_G QBUR0: RF (Bit 5) */ -#define VADC_G_QBUR0_RF_Msk \ - (0x20UL) /*!< VADC_G QBUR0: RF (Bitfield-Mask: 0x01) */ -#define VADC_G_QBUR0_ENSI_Pos \ - (6UL) /*!< VADC_G QBUR0: ENSI (Bit 6) */ -#define VADC_G_QBUR0_ENSI_Msk \ - (0x40UL) /*!< VADC_G QBUR0: ENSI (Bitfield-Mask: 0x01) */ -#define VADC_G_QBUR0_EXTR_Pos \ - (7UL) /*!< VADC_G QBUR0: EXTR (Bit 7) */ -#define VADC_G_QBUR0_EXTR_Msk \ - (0x80UL) /*!< VADC_G QBUR0: EXTR (Bitfield-Mask: 0x01) */ -#define VADC_G_QBUR0_V_Pos (8UL) /*!< VADC_G QBUR0: V (Bit 8) */ -#define VADC_G_QBUR0_V_Msk \ - (0x100UL) /*!< VADC_G QBUR0: V (Bitfield-Mask: 0x01) */ - -/* -------------------------------- VADC_G_ASCTRL ------------------------------- */ -#define VADC_G_ASCTRL_SRCRESREG_Pos \ - (0UL) /*!< VADC_G ASCTRL: SRCRESREG (Bit 0) */ -#define VADC_G_ASCTRL_SRCRESREG_Msk \ - (0xfUL) /*!< VADC_G ASCTRL: SRCRESREG (Bitfield-Mask: 0x0f) */ -#define VADC_G_ASCTRL_XTSEL_Pos \ - (8UL) /*!< VADC_G ASCTRL: XTSEL (Bit 8) */ -#define VADC_G_ASCTRL_XTSEL_Msk \ - (0xf00UL) /*!< VADC_G ASCTRL: XTSEL (Bitfield-Mask: 0x0f) */ -#define VADC_G_ASCTRL_XTLVL_Pos \ - (12UL) /*!< VADC_G ASCTRL: XTLVL (Bit 12) */ -#define VADC_G_ASCTRL_XTLVL_Msk \ - (0x1000UL) /*!< VADC_G ASCTRL: XTLVL (Bitfield-Mask: 0x01) */ -#define VADC_G_ASCTRL_XTMODE_Pos \ - (13UL) /*!< VADC_G ASCTRL: XTMODE (Bit 13) */ -#define VADC_G_ASCTRL_XTMODE_Msk \ - (0x6000UL) /*!< VADC_G ASCTRL: XTMODE (Bitfield-Mask: 0x03) */ -#define VADC_G_ASCTRL_XTWC_Pos \ - (15UL) /*!< VADC_G ASCTRL: XTWC (Bit 15) */ -#define VADC_G_ASCTRL_XTWC_Msk \ - (0x8000UL) /*!< VADC_G ASCTRL: XTWC (Bitfield-Mask: 0x01) */ -#define VADC_G_ASCTRL_GTSEL_Pos \ - (16UL) /*!< VADC_G ASCTRL: GTSEL (Bit 16) */ -#define VADC_G_ASCTRL_GTSEL_Msk \ - (0xf0000UL) /*!< VADC_G ASCTRL: GTSEL (Bitfield-Mask: 0x0f) */ -#define VADC_G_ASCTRL_GTLVL_Pos \ - (20UL) /*!< VADC_G ASCTRL: GTLVL (Bit 20) */ -#define VADC_G_ASCTRL_GTLVL_Msk \ - (0x100000UL) /*!< VADC_G ASCTRL: GTLVL (Bitfield-Mask: 0x01) */ -#define VADC_G_ASCTRL_GTWC_Pos \ - (23UL) /*!< VADC_G ASCTRL: GTWC (Bit 23) */ -#define VADC_G_ASCTRL_GTWC_Msk \ - (0x800000UL) /*!< VADC_G ASCTRL: GTWC (Bitfield-Mask: 0x01) */ -#define VADC_G_ASCTRL_TMEN_Pos \ - (28UL) /*!< VADC_G ASCTRL: TMEN (Bit 28) */ -#define VADC_G_ASCTRL_TMEN_Msk \ - (0x10000000UL) /*!< VADC_G ASCTRL: TMEN (Bitfield-Mask: 0x01) */ -#define VADC_G_ASCTRL_TMWC_Pos \ - (31UL) /*!< VADC_G ASCTRL: TMWC (Bit 31) */ -#define VADC_G_ASCTRL_TMWC_Msk \ - (0x80000000UL) /*!< VADC_G ASCTRL: TMWC (Bitfield-Mask: 0x01) */ - -/* --------------------------------- VADC_G_ASMR -------------------------------- */ -#define VADC_G_ASMR_ENGT_Pos \ - (0UL) /*!< VADC_G ASMR: ENGT (Bit 0) */ -#define VADC_G_ASMR_ENGT_Msk \ - (0x3UL) /*!< VADC_G ASMR: ENGT (Bitfield-Mask: 0x03) */ -#define VADC_G_ASMR_ENTR_Pos \ - (2UL) /*!< VADC_G ASMR: ENTR (Bit 2) */ -#define VADC_G_ASMR_ENTR_Msk \ - (0x4UL) /*!< VADC_G ASMR: ENTR (Bitfield-Mask: 0x01) */ -#define VADC_G_ASMR_ENSI_Pos \ - (3UL) /*!< VADC_G ASMR: ENSI (Bit 3) */ -#define VADC_G_ASMR_ENSI_Msk \ - (0x8UL) /*!< VADC_G ASMR: ENSI (Bitfield-Mask: 0x01) */ -#define VADC_G_ASMR_SCAN_Pos \ - (4UL) /*!< VADC_G ASMR: SCAN (Bit 4) */ -#define VADC_G_ASMR_SCAN_Msk \ - (0x10UL) /*!< VADC_G ASMR: SCAN (Bitfield-Mask: 0x01) */ -#define VADC_G_ASMR_LDM_Pos \ - (5UL) /*!< VADC_G ASMR: LDM (Bit 5) */ -#define VADC_G_ASMR_LDM_Msk \ - (0x20UL) /*!< VADC_G ASMR: LDM (Bitfield-Mask: 0x01) */ -#define VADC_G_ASMR_REQGT_Pos \ - (7UL) /*!< VADC_G ASMR: REQGT (Bit 7) */ -#define VADC_G_ASMR_REQGT_Msk \ - (0x80UL) /*!< VADC_G ASMR: REQGT (Bitfield-Mask: 0x01) */ -#define VADC_G_ASMR_CLRPND_Pos \ - (8UL) /*!< VADC_G ASMR: CLRPND (Bit 8) */ -#define VADC_G_ASMR_CLRPND_Msk \ - (0x100UL) /*!< VADC_G ASMR: CLRPND (Bitfield-Mask: 0x01) */ -#define VADC_G_ASMR_LDEV_Pos \ - (9UL) /*!< VADC_G ASMR: LDEV (Bit 9) */ -#define VADC_G_ASMR_LDEV_Msk \ - (0x200UL) /*!< VADC_G ASMR: LDEV (Bitfield-Mask: 0x01) */ -#define VADC_G_ASMR_RPTDIS_Pos \ - (16UL) /*!< VADC_G ASMR: RPTDIS (Bit 16) */ -#define VADC_G_ASMR_RPTDIS_Msk \ - (0x10000UL) /*!< VADC_G ASMR: RPTDIS (Bitfield-Mask: 0x01) */ - -/* -------------------------------- VADC_G_ASSEL -------------------------------- */ -#define VADC_G_ASSEL_CHSEL0_Pos \ - (0UL) /*!< VADC_G ASSEL: CHSEL0 (Bit 0) */ -#define VADC_G_ASSEL_CHSEL0_Msk \ - (0x1UL) /*!< VADC_G ASSEL: CHSEL0 (Bitfield-Mask: 0x01) */ -#define VADC_G_ASSEL_CHSEL1_Pos \ - (1UL) /*!< VADC_G ASSEL: CHSEL1 (Bit 1) */ -#define VADC_G_ASSEL_CHSEL1_Msk \ - (0x2UL) /*!< VADC_G ASSEL: CHSEL1 (Bitfield-Mask: 0x01) */ -#define VADC_G_ASSEL_CHSEL2_Pos \ - (2UL) /*!< VADC_G ASSEL: CHSEL2 (Bit 2) */ -#define VADC_G_ASSEL_CHSEL2_Msk \ - (0x4UL) /*!< VADC_G ASSEL: CHSEL2 (Bitfield-Mask: 0x01) */ -#define VADC_G_ASSEL_CHSEL3_Pos \ - (3UL) /*!< VADC_G ASSEL: CHSEL3 (Bit 3) */ -#define VADC_G_ASSEL_CHSEL3_Msk \ - (0x8UL) /*!< VADC_G ASSEL: CHSEL3 (Bitfield-Mask: 0x01) */ -#define VADC_G_ASSEL_CHSEL4_Pos \ - (4UL) /*!< VADC_G ASSEL: CHSEL4 (Bit 4) */ -#define VADC_G_ASSEL_CHSEL4_Msk \ - (0x10UL) /*!< VADC_G ASSEL: CHSEL4 (Bitfield-Mask: 0x01) */ -#define VADC_G_ASSEL_CHSEL5_Pos \ - (5UL) /*!< VADC_G ASSEL: CHSEL5 (Bit 5) */ -#define VADC_G_ASSEL_CHSEL5_Msk \ - (0x20UL) /*!< VADC_G ASSEL: CHSEL5 (Bitfield-Mask: 0x01) */ -#define VADC_G_ASSEL_CHSEL6_Pos \ - (6UL) /*!< VADC_G ASSEL: CHSEL6 (Bit 6) */ -#define VADC_G_ASSEL_CHSEL6_Msk \ - (0x40UL) /*!< VADC_G ASSEL: CHSEL6 (Bitfield-Mask: 0x01) */ -#define VADC_G_ASSEL_CHSEL7_Pos \ - (7UL) /*!< VADC_G ASSEL: CHSEL7 (Bit 7) */ -#define VADC_G_ASSEL_CHSEL7_Msk \ - (0x80UL) /*!< VADC_G ASSEL: CHSEL7 (Bitfield-Mask: 0x01) */ - -/* -------------------------------- VADC_G_ASPND -------------------------------- */ -#define VADC_G_ASPND_CHPND0_Pos \ - (0UL) /*!< VADC_G ASPND: CHPND0 (Bit 0) */ -#define VADC_G_ASPND_CHPND0_Msk \ - (0x1UL) /*!< VADC_G ASPND: CHPND0 (Bitfield-Mask: 0x01) */ -#define VADC_G_ASPND_CHPND1_Pos \ - (1UL) /*!< VADC_G ASPND: CHPND1 (Bit 1) */ -#define VADC_G_ASPND_CHPND1_Msk \ - (0x2UL) /*!< VADC_G ASPND: CHPND1 (Bitfield-Mask: 0x01) */ -#define VADC_G_ASPND_CHPND2_Pos \ - (2UL) /*!< VADC_G ASPND: CHPND2 (Bit 2) */ -#define VADC_G_ASPND_CHPND2_Msk \ - (0x4UL) /*!< VADC_G ASPND: CHPND2 (Bitfield-Mask: 0x01) */ -#define VADC_G_ASPND_CHPND3_Pos \ - (3UL) /*!< VADC_G ASPND: CHPND3 (Bit 3) */ -#define VADC_G_ASPND_CHPND3_Msk \ - (0x8UL) /*!< VADC_G ASPND: CHPND3 (Bitfield-Mask: 0x01) */ -#define VADC_G_ASPND_CHPND4_Pos \ - (4UL) /*!< VADC_G ASPND: CHPND4 (Bit 4) */ -#define VADC_G_ASPND_CHPND4_Msk \ - (0x10UL) /*!< VADC_G ASPND: CHPND4 (Bitfield-Mask: 0x01) */ -#define VADC_G_ASPND_CHPND5_Pos \ - (5UL) /*!< VADC_G ASPND: CHPND5 (Bit 5) */ -#define VADC_G_ASPND_CHPND5_Msk \ - (0x20UL) /*!< VADC_G ASPND: CHPND5 (Bitfield-Mask: 0x01) */ -#define VADC_G_ASPND_CHPND6_Pos \ - (6UL) /*!< VADC_G ASPND: CHPND6 (Bit 6) */ -#define VADC_G_ASPND_CHPND6_Msk \ - (0x40UL) /*!< VADC_G ASPND: CHPND6 (Bitfield-Mask: 0x01) */ -#define VADC_G_ASPND_CHPND7_Pos \ - (7UL) /*!< VADC_G ASPND: CHPND7 (Bit 7) */ -#define VADC_G_ASPND_CHPND7_Msk \ - (0x80UL) /*!< VADC_G ASPND: CHPND7 (Bitfield-Mask: 0x01) */ - -/* -------------------------------- VADC_G_CEFLAG ------------------------------- */ -#define VADC_G_CEFLAG_CEV0_Pos \ - (0UL) /*!< VADC_G CEFLAG: CEV0 (Bit 0) */ -#define VADC_G_CEFLAG_CEV0_Msk \ - (0x1UL) /*!< VADC_G CEFLAG: CEV0 (Bitfield-Mask: 0x01) */ -#define VADC_G_CEFLAG_CEV1_Pos \ - (1UL) /*!< VADC_G CEFLAG: CEV1 (Bit 1) */ -#define VADC_G_CEFLAG_CEV1_Msk \ - (0x2UL) /*!< VADC_G CEFLAG: CEV1 (Bitfield-Mask: 0x01) */ -#define VADC_G_CEFLAG_CEV2_Pos \ - (2UL) /*!< VADC_G CEFLAG: CEV2 (Bit 2) */ -#define VADC_G_CEFLAG_CEV2_Msk \ - (0x4UL) /*!< VADC_G CEFLAG: CEV2 (Bitfield-Mask: 0x01) */ -#define VADC_G_CEFLAG_CEV3_Pos \ - (3UL) /*!< VADC_G CEFLAG: CEV3 (Bit 3) */ -#define VADC_G_CEFLAG_CEV3_Msk \ - (0x8UL) /*!< VADC_G CEFLAG: CEV3 (Bitfield-Mask: 0x01) */ -#define VADC_G_CEFLAG_CEV4_Pos \ - (4UL) /*!< VADC_G CEFLAG: CEV4 (Bit 4) */ -#define VADC_G_CEFLAG_CEV4_Msk \ - (0x10UL) /*!< VADC_G CEFLAG: CEV4 (Bitfield-Mask: 0x01) */ -#define VADC_G_CEFLAG_CEV5_Pos \ - (5UL) /*!< VADC_G CEFLAG: CEV5 (Bit 5) */ -#define VADC_G_CEFLAG_CEV5_Msk \ - (0x20UL) /*!< VADC_G CEFLAG: CEV5 (Bitfield-Mask: 0x01) */ -#define VADC_G_CEFLAG_CEV6_Pos \ - (6UL) /*!< VADC_G CEFLAG: CEV6 (Bit 6) */ -#define VADC_G_CEFLAG_CEV6_Msk \ - (0x40UL) /*!< VADC_G CEFLAG: CEV6 (Bitfield-Mask: 0x01) */ -#define VADC_G_CEFLAG_CEV7_Pos \ - (7UL) /*!< VADC_G CEFLAG: CEV7 (Bit 7) */ -#define VADC_G_CEFLAG_CEV7_Msk \ - (0x80UL) /*!< VADC_G CEFLAG: CEV7 (Bitfield-Mask: 0x01) */ - -/* -------------------------------- VADC_G_REFLAG ------------------------------- */ -#define VADC_G_REFLAG_REV0_Pos \ - (0UL) /*!< VADC_G REFLAG: REV0 (Bit 0) */ -#define VADC_G_REFLAG_REV0_Msk \ - (0x1UL) /*!< VADC_G REFLAG: REV0 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFLAG_REV1_Pos \ - (1UL) /*!< VADC_G REFLAG: REV1 (Bit 1) */ -#define VADC_G_REFLAG_REV1_Msk \ - (0x2UL) /*!< VADC_G REFLAG: REV1 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFLAG_REV2_Pos \ - (2UL) /*!< VADC_G REFLAG: REV2 (Bit 2) */ -#define VADC_G_REFLAG_REV2_Msk \ - (0x4UL) /*!< VADC_G REFLAG: REV2 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFLAG_REV3_Pos \ - (3UL) /*!< VADC_G REFLAG: REV3 (Bit 3) */ -#define VADC_G_REFLAG_REV3_Msk \ - (0x8UL) /*!< VADC_G REFLAG: REV3 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFLAG_REV4_Pos \ - (4UL) /*!< VADC_G REFLAG: REV4 (Bit 4) */ -#define VADC_G_REFLAG_REV4_Msk \ - (0x10UL) /*!< VADC_G REFLAG: REV4 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFLAG_REV5_Pos \ - (5UL) /*!< VADC_G REFLAG: REV5 (Bit 5) */ -#define VADC_G_REFLAG_REV5_Msk \ - (0x20UL) /*!< VADC_G REFLAG: REV5 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFLAG_REV6_Pos \ - (6UL) /*!< VADC_G REFLAG: REV6 (Bit 6) */ -#define VADC_G_REFLAG_REV6_Msk \ - (0x40UL) /*!< VADC_G REFLAG: REV6 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFLAG_REV7_Pos \ - (7UL) /*!< VADC_G REFLAG: REV7 (Bit 7) */ -#define VADC_G_REFLAG_REV7_Msk \ - (0x80UL) /*!< VADC_G REFLAG: REV7 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFLAG_REV8_Pos \ - (8UL) /*!< VADC_G REFLAG: REV8 (Bit 8) */ -#define VADC_G_REFLAG_REV8_Msk \ - (0x100UL) /*!< VADC_G REFLAG: REV8 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFLAG_REV9_Pos \ - (9UL) /*!< VADC_G REFLAG: REV9 (Bit 9) */ -#define VADC_G_REFLAG_REV9_Msk \ - (0x200UL) /*!< VADC_G REFLAG: REV9 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFLAG_REV10_Pos \ - (10UL) /*!< VADC_G REFLAG: REV10 (Bit 10) */ -#define VADC_G_REFLAG_REV10_Msk \ - (0x400UL) /*!< VADC_G REFLAG: REV10 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFLAG_REV11_Pos \ - (11UL) /*!< VADC_G REFLAG: REV11 (Bit 11) */ -#define VADC_G_REFLAG_REV11_Msk \ - (0x800UL) /*!< VADC_G REFLAG: REV11 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFLAG_REV12_Pos \ - (12UL) /*!< VADC_G REFLAG: REV12 (Bit 12) */ -#define VADC_G_REFLAG_REV12_Msk \ - (0x1000UL) /*!< VADC_G REFLAG: REV12 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFLAG_REV13_Pos \ - (13UL) /*!< VADC_G REFLAG: REV13 (Bit 13) */ -#define VADC_G_REFLAG_REV13_Msk \ - (0x2000UL) /*!< VADC_G REFLAG: REV13 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFLAG_REV14_Pos \ - (14UL) /*!< VADC_G REFLAG: REV14 (Bit 14) */ -#define VADC_G_REFLAG_REV14_Msk \ - (0x4000UL) /*!< VADC_G REFLAG: REV14 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFLAG_REV15_Pos \ - (15UL) /*!< VADC_G REFLAG: REV15 (Bit 15) */ -#define VADC_G_REFLAG_REV15_Msk \ - (0x8000UL) /*!< VADC_G REFLAG: REV15 (Bitfield-Mask: 0x01) */ - -/* -------------------------------- VADC_G_SEFLAG ------------------------------- */ -#define VADC_G_SEFLAG_SEV0_Pos \ - (0UL) /*!< VADC_G SEFLAG: SEV0 (Bit 0) */ -#define VADC_G_SEFLAG_SEV0_Msk \ - (0x1UL) /*!< VADC_G SEFLAG: SEV0 (Bitfield-Mask: 0x01) */ -#define VADC_G_SEFLAG_SEV1_Pos \ - (1UL) /*!< VADC_G SEFLAG: SEV1 (Bit 1) */ -#define VADC_G_SEFLAG_SEV1_Msk \ - (0x2UL) /*!< VADC_G SEFLAG: SEV1 (Bitfield-Mask: 0x01) */ - -/* -------------------------------- VADC_G_CEFCLR ------------------------------- */ -#define VADC_G_CEFCLR_CEV0_Pos \ - (0UL) /*!< VADC_G CEFCLR: CEV0 (Bit 0) */ -#define VADC_G_CEFCLR_CEV0_Msk \ - (0x1UL) /*!< VADC_G CEFCLR: CEV0 (Bitfield-Mask: 0x01) */ -#define VADC_G_CEFCLR_CEV1_Pos \ - (1UL) /*!< VADC_G CEFCLR: CEV1 (Bit 1) */ -#define VADC_G_CEFCLR_CEV1_Msk \ - (0x2UL) /*!< VADC_G CEFCLR: CEV1 (Bitfield-Mask: 0x01) */ -#define VADC_G_CEFCLR_CEV2_Pos \ - (2UL) /*!< VADC_G CEFCLR: CEV2 (Bit 2) */ -#define VADC_G_CEFCLR_CEV2_Msk \ - (0x4UL) /*!< VADC_G CEFCLR: CEV2 (Bitfield-Mask: 0x01) */ -#define VADC_G_CEFCLR_CEV3_Pos \ - (3UL) /*!< VADC_G CEFCLR: CEV3 (Bit 3) */ -#define VADC_G_CEFCLR_CEV3_Msk \ - (0x8UL) /*!< VADC_G CEFCLR: CEV3 (Bitfield-Mask: 0x01) */ -#define VADC_G_CEFCLR_CEV4_Pos \ - (4UL) /*!< VADC_G CEFCLR: CEV4 (Bit 4) */ -#define VADC_G_CEFCLR_CEV4_Msk \ - (0x10UL) /*!< VADC_G CEFCLR: CEV4 (Bitfield-Mask: 0x01) */ -#define VADC_G_CEFCLR_CEV5_Pos \ - (5UL) /*!< VADC_G CEFCLR: CEV5 (Bit 5) */ -#define VADC_G_CEFCLR_CEV5_Msk \ - (0x20UL) /*!< VADC_G CEFCLR: CEV5 (Bitfield-Mask: 0x01) */ -#define VADC_G_CEFCLR_CEV6_Pos \ - (6UL) /*!< VADC_G CEFCLR: CEV6 (Bit 6) */ -#define VADC_G_CEFCLR_CEV6_Msk \ - (0x40UL) /*!< VADC_G CEFCLR: CEV6 (Bitfield-Mask: 0x01) */ -#define VADC_G_CEFCLR_CEV7_Pos \ - (7UL) /*!< VADC_G CEFCLR: CEV7 (Bit 7) */ -#define VADC_G_CEFCLR_CEV7_Msk \ - (0x80UL) /*!< VADC_G CEFCLR: CEV7 (Bitfield-Mask: 0x01) */ - -/* -------------------------------- VADC_G_REFCLR ------------------------------- */ -#define VADC_G_REFCLR_REV0_Pos \ - (0UL) /*!< VADC_G REFCLR: REV0 (Bit 0) */ -#define VADC_G_REFCLR_REV0_Msk \ - (0x1UL) /*!< VADC_G REFCLR: REV0 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFCLR_REV1_Pos \ - (1UL) /*!< VADC_G REFCLR: REV1 (Bit 1) */ -#define VADC_G_REFCLR_REV1_Msk \ - (0x2UL) /*!< VADC_G REFCLR: REV1 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFCLR_REV2_Pos \ - (2UL) /*!< VADC_G REFCLR: REV2 (Bit 2) */ -#define VADC_G_REFCLR_REV2_Msk \ - (0x4UL) /*!< VADC_G REFCLR: REV2 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFCLR_REV3_Pos \ - (3UL) /*!< VADC_G REFCLR: REV3 (Bit 3) */ -#define VADC_G_REFCLR_REV3_Msk \ - (0x8UL) /*!< VADC_G REFCLR: REV3 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFCLR_REV4_Pos \ - (4UL) /*!< VADC_G REFCLR: REV4 (Bit 4) */ -#define VADC_G_REFCLR_REV4_Msk \ - (0x10UL) /*!< VADC_G REFCLR: REV4 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFCLR_REV5_Pos \ - (5UL) /*!< VADC_G REFCLR: REV5 (Bit 5) */ -#define VADC_G_REFCLR_REV5_Msk \ - (0x20UL) /*!< VADC_G REFCLR: REV5 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFCLR_REV6_Pos \ - (6UL) /*!< VADC_G REFCLR: REV6 (Bit 6) */ -#define VADC_G_REFCLR_REV6_Msk \ - (0x40UL) /*!< VADC_G REFCLR: REV6 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFCLR_REV7_Pos \ - (7UL) /*!< VADC_G REFCLR: REV7 (Bit 7) */ -#define VADC_G_REFCLR_REV7_Msk \ - (0x80UL) /*!< VADC_G REFCLR: REV7 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFCLR_REV8_Pos \ - (8UL) /*!< VADC_G REFCLR: REV8 (Bit 8) */ -#define VADC_G_REFCLR_REV8_Msk \ - (0x100UL) /*!< VADC_G REFCLR: REV8 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFCLR_REV9_Pos \ - (9UL) /*!< VADC_G REFCLR: REV9 (Bit 9) */ -#define VADC_G_REFCLR_REV9_Msk \ - (0x200UL) /*!< VADC_G REFCLR: REV9 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFCLR_REV10_Pos \ - (10UL) /*!< VADC_G REFCLR: REV10 (Bit 10) */ -#define VADC_G_REFCLR_REV10_Msk \ - (0x400UL) /*!< VADC_G REFCLR: REV10 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFCLR_REV11_Pos \ - (11UL) /*!< VADC_G REFCLR: REV11 (Bit 11) */ -#define VADC_G_REFCLR_REV11_Msk \ - (0x800UL) /*!< VADC_G REFCLR: REV11 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFCLR_REV12_Pos \ - (12UL) /*!< VADC_G REFCLR: REV12 (Bit 12) */ -#define VADC_G_REFCLR_REV12_Msk \ - (0x1000UL) /*!< VADC_G REFCLR: REV12 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFCLR_REV13_Pos \ - (13UL) /*!< VADC_G REFCLR: REV13 (Bit 13) */ -#define VADC_G_REFCLR_REV13_Msk \ - (0x2000UL) /*!< VADC_G REFCLR: REV13 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFCLR_REV14_Pos \ - (14UL) /*!< VADC_G REFCLR: REV14 (Bit 14) */ -#define VADC_G_REFCLR_REV14_Msk \ - (0x4000UL) /*!< VADC_G REFCLR: REV14 (Bitfield-Mask: 0x01) */ -#define VADC_G_REFCLR_REV15_Pos \ - (15UL) /*!< VADC_G REFCLR: REV15 (Bit 15) */ -#define VADC_G_REFCLR_REV15_Msk \ - (0x8000UL) /*!< VADC_G REFCLR: REV15 (Bitfield-Mask: 0x01) */ - -/* -------------------------------- VADC_G_SEFCLR ------------------------------- */ -#define VADC_G_SEFCLR_SEV0_Pos \ - (0UL) /*!< VADC_G SEFCLR: SEV0 (Bit 0) */ -#define VADC_G_SEFCLR_SEV0_Msk \ - (0x1UL) /*!< VADC_G SEFCLR: SEV0 (Bitfield-Mask: 0x01) */ -#define VADC_G_SEFCLR_SEV1_Pos \ - (1UL) /*!< VADC_G SEFCLR: SEV1 (Bit 1) */ -#define VADC_G_SEFCLR_SEV1_Msk \ - (0x2UL) /*!< VADC_G SEFCLR: SEV1 (Bitfield-Mask: 0x01) */ - -/* -------------------------------- VADC_G_CEVNP0 ------------------------------- */ -#define VADC_G_CEVNP0_CEV0NP_Pos \ - (0UL) /*!< VADC_G CEVNP0: CEV0NP (Bit 0) */ -#define VADC_G_CEVNP0_CEV0NP_Msk \ - (0xfUL) /*!< VADC_G CEVNP0: CEV0NP (Bitfield-Mask: 0x0f) */ -#define VADC_G_CEVNP0_CEV1NP_Pos \ - (4UL) /*!< VADC_G CEVNP0: CEV1NP (Bit 4) */ -#define VADC_G_CEVNP0_CEV1NP_Msk \ - (0xf0UL) /*!< VADC_G CEVNP0: CEV1NP (Bitfield-Mask: 0x0f) */ -#define VADC_G_CEVNP0_CEV2NP_Pos \ - (8UL) /*!< VADC_G CEVNP0: CEV2NP (Bit 8) */ -#define VADC_G_CEVNP0_CEV2NP_Msk \ - (0xf00UL) /*!< VADC_G CEVNP0: CEV2NP (Bitfield-Mask: 0x0f) */ -#define VADC_G_CEVNP0_CEV3NP_Pos \ - (12UL) /*!< VADC_G CEVNP0: CEV3NP (Bit 12) */ -#define VADC_G_CEVNP0_CEV3NP_Msk \ - (0xf000UL) /*!< VADC_G CEVNP0: CEV3NP (Bitfield-Mask: 0x0f) */ -#define VADC_G_CEVNP0_CEV4NP_Pos \ - (16UL) /*!< VADC_G CEVNP0: CEV4NP (Bit 16) */ -#define VADC_G_CEVNP0_CEV4NP_Msk \ - (0xf0000UL) /*!< VADC_G CEVNP0: CEV4NP (Bitfield-Mask: 0x0f) */ -#define VADC_G_CEVNP0_CEV5NP_Pos \ - (20UL) /*!< VADC_G CEVNP0: CEV5NP (Bit 20) */ -#define VADC_G_CEVNP0_CEV5NP_Msk \ - (0xf00000UL) /*!< VADC_G CEVNP0: CEV5NP (Bitfield-Mask: 0x0f) */ -#define VADC_G_CEVNP0_CEV6NP_Pos \ - (24UL) /*!< VADC_G CEVNP0: CEV6NP (Bit 24) */ -#define VADC_G_CEVNP0_CEV6NP_Msk \ - (0xf000000UL) /*!< VADC_G CEVNP0: CEV6NP (Bitfield-Mask: 0x0f) */ -#define VADC_G_CEVNP0_CEV7NP_Pos \ - (28UL) /*!< VADC_G CEVNP0: CEV7NP (Bit 28) */ -#define VADC_G_CEVNP0_CEV7NP_Msk \ - (0xf0000000UL) /*!< VADC_G CEVNP0: CEV7NP (Bitfield-Mask: 0x0f) */ - -/* -------------------------------- VADC_G_REVNP0 ------------------------------- */ -#define VADC_G_REVNP0_REV0NP_Pos \ - (0UL) /*!< VADC_G REVNP0: REV0NP (Bit 0) */ -#define VADC_G_REVNP0_REV0NP_Msk \ - (0xfUL) /*!< VADC_G REVNP0: REV0NP (Bitfield-Mask: 0x0f) */ -#define VADC_G_REVNP0_REV1NP_Pos \ - (4UL) /*!< VADC_G REVNP0: REV1NP (Bit 4) */ -#define VADC_G_REVNP0_REV1NP_Msk \ - (0xf0UL) /*!< VADC_G REVNP0: REV1NP (Bitfield-Mask: 0x0f) */ -#define VADC_G_REVNP0_REV2NP_Pos \ - (8UL) /*!< VADC_G REVNP0: REV2NP (Bit 8) */ -#define VADC_G_REVNP0_REV2NP_Msk \ - (0xf00UL) /*!< VADC_G REVNP0: REV2NP (Bitfield-Mask: 0x0f) */ -#define VADC_G_REVNP0_REV3NP_Pos \ - (12UL) /*!< VADC_G REVNP0: REV3NP (Bit 12) */ -#define VADC_G_REVNP0_REV3NP_Msk \ - (0xf000UL) /*!< VADC_G REVNP0: REV3NP (Bitfield-Mask: 0x0f) */ -#define VADC_G_REVNP0_REV4NP_Pos \ - (16UL) /*!< VADC_G REVNP0: REV4NP (Bit 16) */ -#define VADC_G_REVNP0_REV4NP_Msk \ - (0xf0000UL) /*!< VADC_G REVNP0: REV4NP (Bitfield-Mask: 0x0f) */ -#define VADC_G_REVNP0_REV5NP_Pos \ - (20UL) /*!< VADC_G REVNP0: REV5NP (Bit 20) */ -#define VADC_G_REVNP0_REV5NP_Msk \ - (0xf00000UL) /*!< VADC_G REVNP0: REV5NP (Bitfield-Mask: 0x0f) */ -#define VADC_G_REVNP0_REV6NP_Pos \ - (24UL) /*!< VADC_G REVNP0: REV6NP (Bit 24) */ -#define VADC_G_REVNP0_REV6NP_Msk \ - (0xf000000UL) /*!< VADC_G REVNP0: REV6NP (Bitfield-Mask: 0x0f) */ -#define VADC_G_REVNP0_REV7NP_Pos \ - (28UL) /*!< VADC_G REVNP0: REV7NP (Bit 28) */ -#define VADC_G_REVNP0_REV7NP_Msk \ - (0xf0000000UL) /*!< VADC_G REVNP0: REV7NP (Bitfield-Mask: 0x0f) */ - -/* -------------------------------- VADC_G_REVNP1 ------------------------------- */ -#define VADC_G_REVNP1_REV8NP_Pos \ - (0UL) /*!< VADC_G REVNP1: REV8NP (Bit 0) */ -#define VADC_G_REVNP1_REV8NP_Msk \ - (0xfUL) /*!< VADC_G REVNP1: REV8NP (Bitfield-Mask: 0x0f) */ -#define VADC_G_REVNP1_REV9NP_Pos \ - (4UL) /*!< VADC_G REVNP1: REV9NP (Bit 4) */ -#define VADC_G_REVNP1_REV9NP_Msk \ - (0xf0UL) /*!< VADC_G REVNP1: REV9NP (Bitfield-Mask: 0x0f) */ -#define VADC_G_REVNP1_REV10NP_Pos \ - (8UL) /*!< VADC_G REVNP1: REV10NP (Bit 8) */ -#define VADC_G_REVNP1_REV10NP_Msk \ - (0xf00UL) /*!< VADC_G REVNP1: REV10NP (Bitfield-Mask: 0x0f) */ -#define VADC_G_REVNP1_REV11NP_Pos \ - (12UL) /*!< VADC_G REVNP1: REV11NP (Bit 12) */ -#define VADC_G_REVNP1_REV11NP_Msk \ - (0xf000UL) /*!< VADC_G REVNP1: REV11NP (Bitfield-Mask: 0x0f) */ -#define VADC_G_REVNP1_REV12NP_Pos \ - (16UL) /*!< VADC_G REVNP1: REV12NP (Bit 16) */ -#define VADC_G_REVNP1_REV12NP_Msk \ - (0xf0000UL) /*!< VADC_G REVNP1: REV12NP (Bitfield-Mask: 0x0f) */ -#define VADC_G_REVNP1_REV13NP_Pos \ - (20UL) /*!< VADC_G REVNP1: REV13NP (Bit 20) */ -#define VADC_G_REVNP1_REV13NP_Msk \ - (0xf00000UL) /*!< VADC_G REVNP1: REV13NP (Bitfield-Mask: 0x0f) */ -#define VADC_G_REVNP1_REV14NP_Pos \ - (24UL) /*!< VADC_G REVNP1: REV14NP (Bit 24) */ -#define VADC_G_REVNP1_REV14NP_Msk \ - (0xf000000UL) /*!< VADC_G REVNP1: REV14NP (Bitfield-Mask: 0x0f) */ -#define VADC_G_REVNP1_REV15NP_Pos \ - (28UL) /*!< VADC_G REVNP1: REV15NP (Bit 28) */ -#define VADC_G_REVNP1_REV15NP_Msk \ - (0xf0000000UL) /*!< VADC_G REVNP1: REV15NP (Bitfield-Mask: 0x0f) */ - -/* -------------------------------- VADC_G_SEVNP -------------------------------- */ -#define VADC_G_SEVNP_SEV0NP_Pos \ - (0UL) /*!< VADC_G SEVNP: SEV0NP (Bit 0) */ -#define VADC_G_SEVNP_SEV0NP_Msk \ - (0xfUL) /*!< VADC_G SEVNP: SEV0NP (Bitfield-Mask: 0x0f) */ -#define VADC_G_SEVNP_SEV1NP_Pos \ - (4UL) /*!< VADC_G SEVNP: SEV1NP (Bit 4) */ -#define VADC_G_SEVNP_SEV1NP_Msk \ - (0xf0UL) /*!< VADC_G SEVNP: SEV1NP (Bitfield-Mask: 0x0f) */ - -/* -------------------------------- VADC_G_SRACT -------------------------------- */ -#define VADC_G_SRACT_AGSR0_Pos \ - (0UL) /*!< VADC_G SRACT: AGSR0 (Bit 0) */ -#define VADC_G_SRACT_AGSR0_Msk \ - (0x1UL) /*!< VADC_G SRACT: AGSR0 (Bitfield-Mask: 0x01) */ -#define VADC_G_SRACT_AGSR1_Pos \ - (1UL) /*!< VADC_G SRACT: AGSR1 (Bit 1) */ -#define VADC_G_SRACT_AGSR1_Msk \ - (0x2UL) /*!< VADC_G SRACT: AGSR1 (Bitfield-Mask: 0x01) */ -#define VADC_G_SRACT_AGSR2_Pos \ - (2UL) /*!< VADC_G SRACT: AGSR2 (Bit 2) */ -#define VADC_G_SRACT_AGSR2_Msk \ - (0x4UL) /*!< VADC_G SRACT: AGSR2 (Bitfield-Mask: 0x01) */ -#define VADC_G_SRACT_AGSR3_Pos \ - (3UL) /*!< VADC_G SRACT: AGSR3 (Bit 3) */ -#define VADC_G_SRACT_AGSR3_Msk \ - (0x8UL) /*!< VADC_G SRACT: AGSR3 (Bitfield-Mask: 0x01) */ -#define VADC_G_SRACT_ASSR0_Pos \ - (8UL) /*!< VADC_G SRACT: ASSR0 (Bit 8) */ -#define VADC_G_SRACT_ASSR0_Msk \ - (0x100UL) /*!< VADC_G SRACT: ASSR0 (Bitfield-Mask: 0x01) */ -#define VADC_G_SRACT_ASSR1_Pos \ - (9UL) /*!< VADC_G SRACT: ASSR1 (Bit 9) */ -#define VADC_G_SRACT_ASSR1_Msk \ - (0x200UL) /*!< VADC_G SRACT: ASSR1 (Bitfield-Mask: 0x01) */ -#define VADC_G_SRACT_ASSR2_Pos \ - (10UL) /*!< VADC_G SRACT: ASSR2 (Bit 10) */ -#define VADC_G_SRACT_ASSR2_Msk \ - (0x400UL) /*!< VADC_G SRACT: ASSR2 (Bitfield-Mask: 0x01) */ -#define VADC_G_SRACT_ASSR3_Pos \ - (11UL) /*!< VADC_G SRACT: ASSR3 (Bit 11) */ -#define VADC_G_SRACT_ASSR3_Msk \ - (0x800UL) /*!< VADC_G SRACT: ASSR3 (Bitfield-Mask: 0x01) */ - -/* ------------------------------- VADC_G_EMUXCTR ------------------------------- */ -#define VADC_G_EMUXCTR_EMUXSET_Pos \ - (0UL) /*!< VADC_G EMUXCTR: EMUXSET (Bit 0) */ -#define VADC_G_EMUXCTR_EMUXSET_Msk \ - (0x7UL) /*!< VADC_G EMUXCTR: EMUXSET (Bitfield-Mask: 0x07) */ -#define VADC_G_EMUXCTR_EMUXACT_Pos \ - (8UL) /*!< VADC_G EMUXCTR: EMUXACT (Bit 8) */ -#define VADC_G_EMUXCTR_EMUXACT_Msk \ - (0x700UL) /*!< VADC_G EMUXCTR: EMUXACT (Bitfield-Mask: 0x07) */ -#define VADC_G_EMUXCTR_EMUXCH_Pos \ - (16UL) /*!< VADC_G EMUXCTR: EMUXCH (Bit 16) */ -#define VADC_G_EMUXCTR_EMUXCH_Msk \ - (0x3ff0000UL) /*!< VADC_G EMUXCTR: EMUXCH (Bitfield-Mask: 0x3ff) */ -#define VADC_G_EMUXCTR_EMUXMODE_Pos \ - (26UL) /*!< VADC_G EMUXCTR: EMUXMODE (Bit 26) */ -#define VADC_G_EMUXCTR_EMUXMODE_Msk \ - (0xc000000UL) /*!< VADC_G EMUXCTR: EMUXMODE (Bitfield-Mask: 0x03) */ -#define VADC_G_EMUXCTR_EMXCOD_Pos \ - (28UL) /*!< VADC_G EMUXCTR: EMXCOD (Bit 28) */ -#define VADC_G_EMUXCTR_EMXCOD_Msk \ - (0x10000000UL) /*!< VADC_G EMUXCTR: EMXCOD (Bitfield-Mask: 0x01) */ -#define VADC_G_EMUXCTR_EMXST_Pos \ - (29UL) /*!< VADC_G EMUXCTR: EMXST (Bit 29) */ -#define VADC_G_EMUXCTR_EMXST_Msk \ - (0x20000000UL) /*!< VADC_G EMUXCTR: EMXST (Bitfield-Mask: 0x01) */ -#define VADC_G_EMUXCTR_EMXCSS_Pos \ - (30UL) /*!< VADC_G EMUXCTR: EMXCSS (Bit 30) */ -#define VADC_G_EMUXCTR_EMXCSS_Msk \ - (0x40000000UL) /*!< VADC_G EMUXCTR: EMXCSS (Bitfield-Mask: 0x01) */ -#define VADC_G_EMUXCTR_EMXWC_Pos \ - (31UL) /*!< VADC_G EMUXCTR: EMXWC (Bit 31) */ -#define VADC_G_EMUXCTR_EMXWC_Msk \ - (0x80000000UL) /*!< VADC_G EMUXCTR: EMXWC (Bitfield-Mask: 0x01) */ - -/* --------------------------------- VADC_G_VFR --------------------------------- */ -#define VADC_G_VFR_VF0_Pos (0UL) /*!< VADC_G VFR: VF0 (Bit 0) */ -#define VADC_G_VFR_VF0_Msk \ - (0x1UL) /*!< VADC_G VFR: VF0 (Bitfield-Mask: 0x01) */ -#define VADC_G_VFR_VF1_Pos (1UL) /*!< VADC_G VFR: VF1 (Bit 1) */ -#define VADC_G_VFR_VF1_Msk \ - (0x2UL) /*!< VADC_G VFR: VF1 (Bitfield-Mask: 0x01) */ -#define VADC_G_VFR_VF2_Pos (2UL) /*!< VADC_G VFR: VF2 (Bit 2) */ -#define VADC_G_VFR_VF2_Msk \ - (0x4UL) /*!< VADC_G VFR: VF2 (Bitfield-Mask: 0x01) */ -#define VADC_G_VFR_VF3_Pos (3UL) /*!< VADC_G VFR: VF3 (Bit 3) */ -#define VADC_G_VFR_VF3_Msk \ - (0x8UL) /*!< VADC_G VFR: VF3 (Bitfield-Mask: 0x01) */ -#define VADC_G_VFR_VF4_Pos (4UL) /*!< VADC_G VFR: VF4 (Bit 4) */ -#define VADC_G_VFR_VF4_Msk \ - (0x10UL) /*!< VADC_G VFR: VF4 (Bitfield-Mask: 0x01) */ -#define VADC_G_VFR_VF5_Pos (5UL) /*!< VADC_G VFR: VF5 (Bit 5) */ -#define VADC_G_VFR_VF5_Msk \ - (0x20UL) /*!< VADC_G VFR: VF5 (Bitfield-Mask: 0x01) */ -#define VADC_G_VFR_VF6_Pos (6UL) /*!< VADC_G VFR: VF6 (Bit 6) */ -#define VADC_G_VFR_VF6_Msk \ - (0x40UL) /*!< VADC_G VFR: VF6 (Bitfield-Mask: 0x01) */ -#define VADC_G_VFR_VF7_Pos (7UL) /*!< VADC_G VFR: VF7 (Bit 7) */ -#define VADC_G_VFR_VF7_Msk \ - (0x80UL) /*!< VADC_G VFR: VF7 (Bitfield-Mask: 0x01) */ -#define VADC_G_VFR_VF8_Pos (8UL) /*!< VADC_G VFR: VF8 (Bit 8) */ -#define VADC_G_VFR_VF8_Msk \ - (0x100UL) /*!< VADC_G VFR: VF8 (Bitfield-Mask: 0x01) */ -#define VADC_G_VFR_VF9_Pos (9UL) /*!< VADC_G VFR: VF9 (Bit 9) */ -#define VADC_G_VFR_VF9_Msk \ - (0x200UL) /*!< VADC_G VFR: VF9 (Bitfield-Mask: 0x01) */ -#define VADC_G_VFR_VF10_Pos \ - (10UL) /*!< VADC_G VFR: VF10 (Bit 10) */ -#define VADC_G_VFR_VF10_Msk \ - (0x400UL) /*!< VADC_G VFR: VF10 (Bitfield-Mask: 0x01) */ -#define VADC_G_VFR_VF11_Pos \ - (11UL) /*!< VADC_G VFR: VF11 (Bit 11) */ -#define VADC_G_VFR_VF11_Msk \ - (0x800UL) /*!< VADC_G VFR: VF11 (Bitfield-Mask: 0x01) */ -#define VADC_G_VFR_VF12_Pos \ - (12UL) /*!< VADC_G VFR: VF12 (Bit 12) */ -#define VADC_G_VFR_VF12_Msk \ - (0x1000UL) /*!< VADC_G VFR: VF12 (Bitfield-Mask: 0x01) */ -#define VADC_G_VFR_VF13_Pos \ - (13UL) /*!< VADC_G VFR: VF13 (Bit 13) */ -#define VADC_G_VFR_VF13_Msk \ - (0x2000UL) /*!< VADC_G VFR: VF13 (Bitfield-Mask: 0x01) */ -#define VADC_G_VFR_VF14_Pos \ - (14UL) /*!< VADC_G VFR: VF14 (Bit 14) */ -#define VADC_G_VFR_VF14_Msk \ - (0x4000UL) /*!< VADC_G VFR: VF14 (Bitfield-Mask: 0x01) */ -#define VADC_G_VFR_VF15_Pos \ - (15UL) /*!< VADC_G VFR: VF15 (Bit 15) */ -#define VADC_G_VFR_VF15_Msk \ - (0x8000UL) /*!< VADC_G VFR: VF15 (Bitfield-Mask: 0x01) */ - -/* -------------------------------- VADC_G_CHCTR -------------------------------- */ -#define VADC_G_CHCTR_ICLSEL_Pos \ - (0UL) /*!< VADC_G CHCTR: ICLSEL (Bit 0) */ -#define VADC_G_CHCTR_ICLSEL_Msk \ - (0x3UL) /*!< VADC_G CHCTR: ICLSEL (Bitfield-Mask: 0x03) */ -#define VADC_G_CHCTR_BNDSELL_Pos \ - (4UL) /*!< VADC_G CHCTR: BNDSELL (Bit 4) */ -#define VADC_G_CHCTR_BNDSELL_Msk \ - (0x30UL) /*!< VADC_G CHCTR: BNDSELL (Bitfield-Mask: 0x03) */ -#define VADC_G_CHCTR_BNDSELU_Pos \ - (6UL) /*!< VADC_G CHCTR: BNDSELU (Bit 6) */ -#define VADC_G_CHCTR_BNDSELU_Msk \ - (0xc0UL) /*!< VADC_G CHCTR: BNDSELU (Bitfield-Mask: 0x03) */ -#define VADC_G_CHCTR_CHEVMODE_Pos \ - (8UL) /*!< VADC_G CHCTR: CHEVMODE (Bit 8) */ -#define VADC_G_CHCTR_CHEVMODE_Msk \ - (0x300UL) /*!< VADC_G CHCTR: CHEVMODE (Bitfield-Mask: 0x03) */ -#define VADC_G_CHCTR_SYNC_Pos \ - (10UL) /*!< VADC_G CHCTR: SYNC (Bit 10) */ -#define VADC_G_CHCTR_SYNC_Msk \ - (0x400UL) /*!< VADC_G CHCTR: SYNC (Bitfield-Mask: 0x01) */ -#define VADC_G_CHCTR_REFSEL_Pos \ - (11UL) /*!< VADC_G CHCTR: REFSEL (Bit 11) */ -#define VADC_G_CHCTR_REFSEL_Msk \ - (0x800UL) /*!< VADC_G CHCTR: REFSEL (Bitfield-Mask: 0x01) */ -#define VADC_G_CHCTR_RESREG_Pos \ - (16UL) /*!< VADC_G CHCTR: RESREG (Bit 16) */ -#define VADC_G_CHCTR_RESREG_Msk \ - (0xf0000UL) /*!< VADC_G CHCTR: RESREG (Bitfield-Mask: 0x0f) */ -#define VADC_G_CHCTR_RESTBS_Pos \ - (20UL) /*!< VADC_G CHCTR: RESTBS (Bit 20) */ -#define VADC_G_CHCTR_RESTBS_Msk \ - (0x100000UL) /*!< VADC_G CHCTR: RESTBS (Bitfield-Mask: 0x01) */ -#define VADC_G_CHCTR_RESPOS_Pos \ - (21UL) /*!< VADC_G CHCTR: RESPOS (Bit 21) */ -#define VADC_G_CHCTR_RESPOS_Msk \ - (0x200000UL) /*!< VADC_G CHCTR: RESPOS (Bitfield-Mask: 0x01) */ -#define VADC_G_CHCTR_BWDCH_Pos \ - (28UL) /*!< VADC_G CHCTR: BWDCH (Bit 28) */ -#define VADC_G_CHCTR_BWDCH_Msk \ - (0x30000000UL) /*!< VADC_G CHCTR: BWDCH (Bitfield-Mask: 0x03) */ -#define VADC_G_CHCTR_BWDEN_Pos \ - (30UL) /*!< VADC_G CHCTR: BWDEN (Bit 30) */ -#define VADC_G_CHCTR_BWDEN_Msk \ - (0x40000000UL) /*!< VADC_G CHCTR: BWDEN (Bitfield-Mask: 0x01) */ - -/* --------------------------------- VADC_G_RCR --------------------------------- */ -#define VADC_G_RCR_DRCTR_Pos \ - (16UL) /*!< VADC_G RCR: DRCTR (Bit 16) */ -#define VADC_G_RCR_DRCTR_Msk \ - (0xf0000UL) /*!< VADC_G RCR: DRCTR (Bitfield-Mask: 0x0f) */ -#define VADC_G_RCR_DMM_Pos \ - (20UL) /*!< VADC_G RCR: DMM (Bit 20) */ -#define VADC_G_RCR_DMM_Msk \ - (0x300000UL) /*!< VADC_G RCR: DMM (Bitfield-Mask: 0x03) */ -#define VADC_G_RCR_WFR_Pos \ - (24UL) /*!< VADC_G RCR: WFR (Bit 24) */ -#define VADC_G_RCR_WFR_Msk \ - (0x1000000UL) /*!< VADC_G RCR: WFR (Bitfield-Mask: 0x01) */ -#define VADC_G_RCR_FEN_Pos \ - (25UL) /*!< VADC_G RCR: FEN (Bit 25) */ -#define VADC_G_RCR_FEN_Msk \ - (0x6000000UL) /*!< VADC_G RCR: FEN (Bitfield-Mask: 0x03) */ -#define VADC_G_RCR_SRGEN_Pos \ - (31UL) /*!< VADC_G RCR: SRGEN (Bit 31) */ -#define VADC_G_RCR_SRGEN_Msk \ - (0x80000000UL) /*!< VADC_G RCR: SRGEN (Bitfield-Mask: 0x01) */ - -/* --------------------------------- VADC_G_RES --------------------------------- */ -#define VADC_G_RES_RESULT_Pos \ - (0UL) /*!< VADC_G RES: RESULT (Bit 0) */ -#define VADC_G_RES_RESULT_Msk \ - (0xffffUL) /*!< VADC_G RES: RESULT (Bitfield-Mask: 0xffff) */ -#define VADC_G_RES_DRC_Pos \ - (16UL) /*!< VADC_G RES: DRC (Bit 16) */ -#define VADC_G_RES_DRC_Msk \ - (0xf0000UL) /*!< VADC_G RES: DRC (Bitfield-Mask: 0x0f) */ -#define VADC_G_RES_CHNR_Pos \ - (20UL) /*!< VADC_G RES: CHNR (Bit 20) */ -#define VADC_G_RES_CHNR_Msk \ - (0x1f00000UL) /*!< VADC_G RES: CHNR (Bitfield-Mask: 0x1f) */ -#define VADC_G_RES_EMUX_Pos \ - (25UL) /*!< VADC_G RES: EMUX (Bit 25) */ -#define VADC_G_RES_EMUX_Msk \ - (0xe000000UL) /*!< VADC_G RES: EMUX (Bitfield-Mask: 0x07) */ -#define VADC_G_RES_CRS_Pos \ - (28UL) /*!< VADC_G RES: CRS (Bit 28) */ -#define VADC_G_RES_CRS_Msk \ - (0x30000000UL) /*!< VADC_G RES: CRS (Bitfield-Mask: 0x03) */ -#define VADC_G_RES_FCR_Pos \ - (30UL) /*!< VADC_G RES: FCR (Bit 30) */ -#define VADC_G_RES_FCR_Msk \ - (0x40000000UL) /*!< VADC_G RES: FCR (Bitfield-Mask: 0x01) */ -#define VADC_G_RES_VF_Pos (31UL) /*!< VADC_G RES: VF (Bit 31) */ -#define VADC_G_RES_VF_Msk \ - (0x80000000UL) /*!< VADC_G RES: VF (Bitfield-Mask: 0x01) */ - -/* --------------------------------- VADC_G_RESD -------------------------------- */ -#define VADC_G_RESD_RESULT_Pos \ - (0UL) /*!< VADC_G RESD: RESULT (Bit 0) */ -#define VADC_G_RESD_RESULT_Msk \ - (0xffffUL) /*!< VADC_G RESD: RESULT (Bitfield-Mask: 0xffff) */ -#define VADC_G_RESD_DRC_Pos \ - (16UL) /*!< VADC_G RESD: DRC (Bit 16) */ -#define VADC_G_RESD_DRC_Msk \ - (0xf0000UL) /*!< VADC_G RESD: DRC (Bitfield-Mask: 0x0f) */ -#define VADC_G_RESD_CHNR_Pos \ - (20UL) /*!< VADC_G RESD: CHNR (Bit 20) */ -#define VADC_G_RESD_CHNR_Msk \ - (0x1f00000UL) /*!< VADC_G RESD: CHNR (Bitfield-Mask: 0x1f) */ -#define VADC_G_RESD_EMUX_Pos \ - (25UL) /*!< VADC_G RESD: EMUX (Bit 25) */ -#define VADC_G_RESD_EMUX_Msk \ - (0xe000000UL) /*!< VADC_G RESD: EMUX (Bitfield-Mask: 0x07) */ -#define VADC_G_RESD_CRS_Pos \ - (28UL) /*!< VADC_G RESD: CRS (Bit 28) */ -#define VADC_G_RESD_CRS_Msk \ - (0x30000000UL) /*!< VADC_G RESD: CRS (Bitfield-Mask: 0x03) */ -#define VADC_G_RESD_FCR_Pos \ - (30UL) /*!< VADC_G RESD: FCR (Bit 30) */ -#define VADC_G_RESD_FCR_Msk \ - (0x40000000UL) /*!< VADC_G RESD: FCR (Bitfield-Mask: 0x01) */ -#define VADC_G_RESD_VF_Pos \ - (31UL) /*!< VADC_G RESD: VF (Bit 31) */ -#define VADC_G_RESD_VF_Msk \ - (0x80000000UL) /*!< VADC_G RESD: VF (Bitfield-Mask: 0x01) */ - -/* ================================================================================ */ -/* ================ struct 'DSD' Position & Mask ================ */ -/* ================================================================================ */ - -/* ----------------------------------- DSD_CLC ---------------------------------- */ -#define DSD_CLC_DISR_Pos (0UL) /*!< DSD CLC: DISR (Bit 0) */ -#define DSD_CLC_DISR_Msk (0x1UL) /*!< DSD CLC: DISR (Bitfield-Mask: 0x01) */ -#define DSD_CLC_DISS_Pos (1UL) /*!< DSD CLC: DISS (Bit 1) */ -#define DSD_CLC_DISS_Msk (0x2UL) /*!< DSD CLC: DISS (Bitfield-Mask: 0x01) */ -#define DSD_CLC_EDIS_Pos (3UL) /*!< DSD CLC: EDIS (Bit 3) */ -#define DSD_CLC_EDIS_Msk (0x8UL) /*!< DSD CLC: EDIS (Bitfield-Mask: 0x01) */ - -/* ----------------------------------- DSD_ID ----------------------------------- */ -#define DSD_ID_MOD_REV_Pos (0UL) /*!< DSD ID: MOD_REV (Bit 0) */ -#define DSD_ID_MOD_REV_Msk \ - (0xffUL) /*!< DSD ID: MOD_REV (Bitfield-Mask: 0xff) */ -#define DSD_ID_MOD_TYPE_Pos \ - (8UL) /*!< DSD ID: MOD_TYPE (Bit 8) */ -#define DSD_ID_MOD_TYPE_Msk \ - (0xff00UL) /*!< DSD ID: MOD_TYPE (Bitfield-Mask: 0xff) */ -#define DSD_ID_MOD_NUMBER_Pos \ - (16UL) /*!< DSD ID: MOD_NUMBER (Bit 16) */ -#define DSD_ID_MOD_NUMBER_Msk \ - (0xffff0000UL) /*!< DSD ID: MOD_NUMBER (Bitfield-Mask: 0xffff) */ - -/* ----------------------------------- DSD_OCS ---------------------------------- */ -#define DSD_OCS_SUS_Pos (24UL) /*!< DSD OCS: SUS (Bit 24) */ -#define DSD_OCS_SUS_Msk \ - (0xf000000UL) /*!< DSD OCS: SUS (Bitfield-Mask: 0x0f) */ -#define DSD_OCS_SUS_P_Pos (28UL) /*!< DSD OCS: SUS_P (Bit 28) */ -#define DSD_OCS_SUS_P_Msk \ - (0x10000000UL) /*!< DSD OCS: SUS_P (Bitfield-Mask: 0x01) */ -#define DSD_OCS_SUSSTA_Pos \ - (29UL) /*!< DSD OCS: SUSSTA (Bit 29) */ -#define DSD_OCS_SUSSTA_Msk \ - (0x20000000UL) /*!< DSD OCS: SUSSTA (Bitfield-Mask: 0x01) */ - -/* --------------------------------- DSD_GLOBCFG -------------------------------- */ -#define DSD_GLOBCFG_MCSEL_Pos \ - (0UL) /*!< DSD GLOBCFG: MCSEL (Bit 0) */ -#define DSD_GLOBCFG_MCSEL_Msk \ - (0x7UL) /*!< DSD GLOBCFG: MCSEL (Bitfield-Mask: 0x07) */ - -/* --------------------------------- DSD_GLOBRC --------------------------------- */ -#define DSD_GLOBRC_CH0RUN_Pos \ - (0UL) /*!< DSD GLOBRC: CH0RUN (Bit 0) */ -#define DSD_GLOBRC_CH0RUN_Msk \ - (0x1UL) /*!< DSD GLOBRC: CH0RUN (Bitfield-Mask: 0x01) */ -#define DSD_GLOBRC_CH1RUN_Pos \ - (1UL) /*!< DSD GLOBRC: CH1RUN (Bit 1) */ -#define DSD_GLOBRC_CH1RUN_Msk \ - (0x2UL) /*!< DSD GLOBRC: CH1RUN (Bitfield-Mask: 0x01) */ -#define DSD_GLOBRC_CH2RUN_Pos \ - (2UL) /*!< DSD GLOBRC: CH2RUN (Bit 2) */ -#define DSD_GLOBRC_CH2RUN_Msk \ - (0x4UL) /*!< DSD GLOBRC: CH2RUN (Bitfield-Mask: 0x01) */ -#define DSD_GLOBRC_CH3RUN_Pos \ - (3UL) /*!< DSD GLOBRC: CH3RUN (Bit 3) */ -#define DSD_GLOBRC_CH3RUN_Msk \ - (0x8UL) /*!< DSD GLOBRC: CH3RUN (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- DSD_CGCFG --------------------------------- */ -#define DSD_CGCFG_CGMOD_Pos \ - (0UL) /*!< DSD CGCFG: CGMOD (Bit 0) */ -#define DSD_CGCFG_CGMOD_Msk \ - (0x3UL) /*!< DSD CGCFG: CGMOD (Bitfield-Mask: 0x03) */ -#define DSD_CGCFG_BREV_Pos (2UL) /*!< DSD CGCFG: BREV (Bit 2) */ -#define DSD_CGCFG_BREV_Msk \ - (0x4UL) /*!< DSD CGCFG: BREV (Bitfield-Mask: 0x01) */ -#define DSD_CGCFG_SIGPOL_Pos \ - (3UL) /*!< DSD CGCFG: SIGPOL (Bit 3) */ -#define DSD_CGCFG_SIGPOL_Msk \ - (0x8UL) /*!< DSD CGCFG: SIGPOL (Bitfield-Mask: 0x01) */ -#define DSD_CGCFG_DIVCG_Pos \ - (4UL) /*!< DSD CGCFG: DIVCG (Bit 4) */ -#define DSD_CGCFG_DIVCG_Msk \ - (0xf0UL) /*!< DSD CGCFG: DIVCG (Bitfield-Mask: 0x0f) */ -#define DSD_CGCFG_RUN_Pos (15UL) /*!< DSD CGCFG: RUN (Bit 15) */ -#define DSD_CGCFG_RUN_Msk \ - (0x8000UL) /*!< DSD CGCFG: RUN (Bitfield-Mask: 0x01) */ -#define DSD_CGCFG_BITCOUNT_Pos \ - (16UL) /*!< DSD CGCFG: BITCOUNT (Bit 16) */ -#define DSD_CGCFG_BITCOUNT_Msk \ - (0x1f0000UL) /*!< DSD CGCFG: BITCOUNT (Bitfield-Mask: 0x1f) */ -#define DSD_CGCFG_STEPCOUNT_Pos \ - (24UL) /*!< DSD CGCFG: STEPCOUNT (Bit 24) */ -#define DSD_CGCFG_STEPCOUNT_Msk \ - (0xf000000UL) /*!< DSD CGCFG: STEPCOUNT (Bitfield-Mask: 0x0f) */ -#define DSD_CGCFG_STEPS_Pos \ - (28UL) /*!< DSD CGCFG: STEPS (Bit 28) */ -#define DSD_CGCFG_STEPS_Msk \ - (0x10000000UL) /*!< DSD CGCFG: STEPS (Bitfield-Mask: 0x01) */ -#define DSD_CGCFG_STEPD_Pos \ - (29UL) /*!< DSD CGCFG: STEPD (Bit 29) */ -#define DSD_CGCFG_STEPD_Msk \ - (0x20000000UL) /*!< DSD CGCFG: STEPD (Bitfield-Mask: 0x01) */ -#define DSD_CGCFG_SGNCG_Pos \ - (30UL) /*!< DSD CGCFG: SGNCG (Bit 30) */ -#define DSD_CGCFG_SGNCG_Msk \ - (0x40000000UL) /*!< DSD CGCFG: SGNCG (Bitfield-Mask: 0x01) */ - -/* --------------------------------- DSD_EVFLAG --------------------------------- */ -#define DSD_EVFLAG_RESEV0_Pos \ - (0UL) /*!< DSD EVFLAG: RESEV0 (Bit 0) */ -#define DSD_EVFLAG_RESEV0_Msk \ - (0x1UL) /*!< DSD EVFLAG: RESEV0 (Bitfield-Mask: 0x01) */ -#define DSD_EVFLAG_RESEV1_Pos \ - (1UL) /*!< DSD EVFLAG: RESEV1 (Bit 1) */ -#define DSD_EVFLAG_RESEV1_Msk \ - (0x2UL) /*!< DSD EVFLAG: RESEV1 (Bitfield-Mask: 0x01) */ -#define DSD_EVFLAG_RESEV2_Pos \ - (2UL) /*!< DSD EVFLAG: RESEV2 (Bit 2) */ -#define DSD_EVFLAG_RESEV2_Msk \ - (0x4UL) /*!< DSD EVFLAG: RESEV2 (Bitfield-Mask: 0x01) */ -#define DSD_EVFLAG_RESEV3_Pos \ - (3UL) /*!< DSD EVFLAG: RESEV3 (Bit 3) */ -#define DSD_EVFLAG_RESEV3_Msk \ - (0x8UL) /*!< DSD EVFLAG: RESEV3 (Bitfield-Mask: 0x01) */ -#define DSD_EVFLAG_ALEV0_Pos \ - (16UL) /*!< DSD EVFLAG: ALEV0 (Bit 16) */ -#define DSD_EVFLAG_ALEV0_Msk \ - (0x10000UL) /*!< DSD EVFLAG: ALEV0 (Bitfield-Mask: 0x01) */ -#define DSD_EVFLAG_ALEV1_Pos \ - (17UL) /*!< DSD EVFLAG: ALEV1 (Bit 17) */ -#define DSD_EVFLAG_ALEV1_Msk \ - (0x20000UL) /*!< DSD EVFLAG: ALEV1 (Bitfield-Mask: 0x01) */ -#define DSD_EVFLAG_ALEV2_Pos \ - (18UL) /*!< DSD EVFLAG: ALEV2 (Bit 18) */ -#define DSD_EVFLAG_ALEV2_Msk \ - (0x40000UL) /*!< DSD EVFLAG: ALEV2 (Bitfield-Mask: 0x01) */ -#define DSD_EVFLAG_ALEV3_Pos \ - (19UL) /*!< DSD EVFLAG: ALEV3 (Bit 19) */ -#define DSD_EVFLAG_ALEV3_Msk \ - (0x80000UL) /*!< DSD EVFLAG: ALEV3 (Bitfield-Mask: 0x01) */ -#define DSD_EVFLAG_ALEV4_Pos \ - (20UL) /*!< DSD EVFLAG: ALEV4 (Bit 20) */ -#define DSD_EVFLAG_ALEV4_Msk \ - (0x100000UL) /*!< DSD EVFLAG: ALEV4 (Bitfield-Mask: 0x01) */ -#define DSD_EVFLAG_ALEV5_Pos \ - (21UL) /*!< DSD EVFLAG: ALEV5 (Bit 21) */ -#define DSD_EVFLAG_ALEV5_Msk \ - (0x200000UL) /*!< DSD EVFLAG: ALEV5 (Bitfield-Mask: 0x01) */ -#define DSD_EVFLAG_ALEV6_Pos \ - (22UL) /*!< DSD EVFLAG: ALEV6 (Bit 22) */ -#define DSD_EVFLAG_ALEV6_Msk \ - (0x400000UL) /*!< DSD EVFLAG: ALEV6 (Bitfield-Mask: 0x01) */ -#define DSD_EVFLAG_ALEV7_Pos \ - (23UL) /*!< DSD EVFLAG: ALEV7 (Bit 23) */ -#define DSD_EVFLAG_ALEV7_Msk \ - (0x800000UL) /*!< DSD EVFLAG: ALEV7 (Bitfield-Mask: 0x01) */ -#define DSD_EVFLAG_ALEV8_Pos \ - (24UL) /*!< DSD EVFLAG: ALEV8 (Bit 24) */ -#define DSD_EVFLAG_ALEV8_Msk \ - (0x1000000UL) /*!< DSD EVFLAG: ALEV8 (Bitfield-Mask: 0x01) */ -#define DSD_EVFLAG_ALEV9_Pos \ - (25UL) /*!< DSD EVFLAG: ALEV9 (Bit 25) */ -#define DSD_EVFLAG_ALEV9_Msk \ - (0x2000000UL) /*!< DSD EVFLAG: ALEV9 (Bitfield-Mask: 0x01) */ - -/* -------------------------------- DSD_EVFLAGCLR ------------------------------- */ -#define DSD_EVFLAGCLR_RESEC0_Pos \ - (0UL) /*!< DSD EVFLAGCLR: RESEC0 (Bit 0) */ -#define DSD_EVFLAGCLR_RESEC0_Msk \ - (0x1UL) /*!< DSD EVFLAGCLR: RESEC0 (Bitfield-Mask: 0x01) */ -#define DSD_EVFLAGCLR_RESEC1_Pos \ - (1UL) /*!< DSD EVFLAGCLR: RESEC1 (Bit 1) */ -#define DSD_EVFLAGCLR_RESEC1_Msk \ - (0x2UL) /*!< DSD EVFLAGCLR: RESEC1 (Bitfield-Mask: 0x01) */ -#define DSD_EVFLAGCLR_RESEC2_Pos \ - (2UL) /*!< DSD EVFLAGCLR: RESEC2 (Bit 2) */ -#define DSD_EVFLAGCLR_RESEC2_Msk \ - (0x4UL) /*!< DSD EVFLAGCLR: RESEC2 (Bitfield-Mask: 0x01) */ -#define DSD_EVFLAGCLR_RESEC3_Pos \ - (3UL) /*!< DSD EVFLAGCLR: RESEC3 (Bit 3) */ -#define DSD_EVFLAGCLR_RESEC3_Msk \ - (0x8UL) /*!< DSD EVFLAGCLR: RESEC3 (Bitfield-Mask: 0x01) */ -#define DSD_EVFLAGCLR_ALEC0_Pos \ - (16UL) /*!< DSD EVFLAGCLR: ALEC0 (Bit 16) */ -#define DSD_EVFLAGCLR_ALEC0_Msk \ - (0x10000UL) /*!< DSD EVFLAGCLR: ALEC0 (Bitfield-Mask: 0x01) */ -#define DSD_EVFLAGCLR_ALEC1_Pos \ - (17UL) /*!< DSD EVFLAGCLR: ALEC1 (Bit 17) */ -#define DSD_EVFLAGCLR_ALEC1_Msk \ - (0x20000UL) /*!< DSD EVFLAGCLR: ALEC1 (Bitfield-Mask: 0x01) */ -#define DSD_EVFLAGCLR_ALEC2_Pos \ - (18UL) /*!< DSD EVFLAGCLR: ALEC2 (Bit 18) */ -#define DSD_EVFLAGCLR_ALEC2_Msk \ - (0x40000UL) /*!< DSD EVFLAGCLR: ALEC2 (Bitfield-Mask: 0x01) */ -#define DSD_EVFLAGCLR_ALEC3_Pos \ - (19UL) /*!< DSD EVFLAGCLR: ALEC3 (Bit 19) */ -#define DSD_EVFLAGCLR_ALEC3_Msk \ - (0x80000UL) /*!< DSD EVFLAGCLR: ALEC3 (Bitfield-Mask: 0x01) */ - -/* ================================================================================ */ -/* ================ Group 'DSD_CH' Position & Mask ================ */ -/* ================================================================================ */ - -/* -------------------------------- DSD_CH_MODCFG ------------------------------- */ -#define DSD_CH_MODCFG_DIVM_Pos \ - (16UL) /*!< DSD_CH MODCFG: DIVM (Bit 16) */ -#define DSD_CH_MODCFG_DIVM_Msk \ - (0xf0000UL) /*!< DSD_CH MODCFG: DIVM (Bitfield-Mask: 0x0f) */ -#define DSD_CH_MODCFG_DWC_Pos \ - (23UL) /*!< DSD_CH MODCFG: DWC (Bit 23) */ -#define DSD_CH_MODCFG_DWC_Msk \ - (0x800000UL) /*!< DSD_CH MODCFG: DWC (Bitfield-Mask: 0x01) */ - -/* -------------------------------- DSD_CH_DICFG -------------------------------- */ -#define DSD_CH_DICFG_DSRC_Pos \ - (0UL) /*!< DSD_CH DICFG: DSRC (Bit 0) */ -#define DSD_CH_DICFG_DSRC_Msk \ - (0xfUL) /*!< DSD_CH DICFG: DSRC (Bitfield-Mask: 0x0f) */ -#define DSD_CH_DICFG_DSWC_Pos \ - (7UL) /*!< DSD_CH DICFG: DSWC (Bit 7) */ -#define DSD_CH_DICFG_DSWC_Msk \ - (0x80UL) /*!< DSD_CH DICFG: DSWC (Bitfield-Mask: 0x01) */ -#define DSD_CH_DICFG_ITRMODE_Pos \ - (8UL) /*!< DSD_CH DICFG: ITRMODE (Bit 8) */ -#define DSD_CH_DICFG_ITRMODE_Msk \ - (0x300UL) /*!< DSD_CH DICFG: ITRMODE (Bitfield-Mask: 0x03) */ -#define DSD_CH_DICFG_TSTRMODE_Pos \ - (10UL) /*!< DSD_CH DICFG: TSTRMODE (Bit 10) */ -#define DSD_CH_DICFG_TSTRMODE_Msk \ - (0xc00UL) /*!< DSD_CH DICFG: TSTRMODE (Bitfield-Mask: 0x03) */ -#define DSD_CH_DICFG_TRSEL_Pos \ - (12UL) /*!< DSD_CH DICFG: TRSEL (Bit 12) */ -#define DSD_CH_DICFG_TRSEL_Msk \ - (0x7000UL) /*!< DSD_CH DICFG: TRSEL (Bitfield-Mask: 0x07) */ -#define DSD_CH_DICFG_TRWC_Pos \ - (15UL) /*!< DSD_CH DICFG: TRWC (Bit 15) */ -#define DSD_CH_DICFG_TRWC_Msk \ - (0x8000UL) /*!< DSD_CH DICFG: TRWC (Bitfield-Mask: 0x01) */ -#define DSD_CH_DICFG_CSRC_Pos \ - (16UL) /*!< DSD_CH DICFG: CSRC (Bit 16) */ -#define DSD_CH_DICFG_CSRC_Msk \ - (0xf0000UL) /*!< DSD_CH DICFG: CSRC (Bitfield-Mask: 0x0f) */ -#define DSD_CH_DICFG_STROBE_Pos \ - (20UL) /*!< DSD_CH DICFG: STROBE (Bit 20) */ -#define DSD_CH_DICFG_STROBE_Msk \ - (0xf00000UL) /*!< DSD_CH DICFG: STROBE (Bitfield-Mask: 0x0f) */ -#define DSD_CH_DICFG_SCWC_Pos \ - (31UL) /*!< DSD_CH DICFG: SCWC (Bit 31) */ -#define DSD_CH_DICFG_SCWC_Msk \ - (0x80000000UL) /*!< DSD_CH DICFG: SCWC (Bitfield-Mask: 0x01) */ - -/* -------------------------------- DSD_CH_FCFGC -------------------------------- */ -#define DSD_CH_FCFGC_CFMDF_Pos \ - (0UL) /*!< DSD_CH FCFGC: CFMDF (Bit 0) */ -#define DSD_CH_FCFGC_CFMDF_Msk \ - (0xffUL) /*!< DSD_CH FCFGC: CFMDF (Bitfield-Mask: 0xff) */ -#define DSD_CH_FCFGC_CFMC_Pos \ - (8UL) /*!< DSD_CH FCFGC: CFMC (Bit 8) */ -#define DSD_CH_FCFGC_CFMC_Msk \ - (0x300UL) /*!< DSD_CH FCFGC: CFMC (Bitfield-Mask: 0x03) */ -#define DSD_CH_FCFGC_CFEN_Pos \ - (10UL) /*!< DSD_CH FCFGC: CFEN (Bit 10) */ -#define DSD_CH_FCFGC_CFEN_Msk \ - (0x400UL) /*!< DSD_CH FCFGC: CFEN (Bitfield-Mask: 0x01) */ -#define DSD_CH_FCFGC_SRGM_Pos \ - (14UL) /*!< DSD_CH FCFGC: SRGM (Bit 14) */ -#define DSD_CH_FCFGC_SRGM_Msk \ - (0xc000UL) /*!< DSD_CH FCFGC: SRGM (Bitfield-Mask: 0x03) */ -#define DSD_CH_FCFGC_CFMSV_Pos \ - (16UL) /*!< DSD_CH FCFGC: CFMSV (Bit 16) */ -#define DSD_CH_FCFGC_CFMSV_Msk \ - (0xff0000UL) /*!< DSD_CH FCFGC: CFMSV (Bitfield-Mask: 0xff) */ -#define DSD_CH_FCFGC_CFMDCNT_Pos \ - (24UL) /*!< DSD_CH FCFGC: CFMDCNT (Bit 24) */ -#define DSD_CH_FCFGC_CFMDCNT_Msk \ - (0xff000000UL) /*!< DSD_CH FCFGC: CFMDCNT (Bitfield-Mask: 0xff) */ - -/* -------------------------------- DSD_CH_FCFGA -------------------------------- */ -#define DSD_CH_FCFGA_CFADF_Pos \ - (0UL) /*!< DSD_CH FCFGA: CFADF (Bit 0) */ -#define DSD_CH_FCFGA_CFADF_Msk \ - (0xffUL) /*!< DSD_CH FCFGA: CFADF (Bitfield-Mask: 0xff) */ -#define DSD_CH_FCFGA_CFAC_Pos \ - (8UL) /*!< DSD_CH FCFGA: CFAC (Bit 8) */ -#define DSD_CH_FCFGA_CFAC_Msk \ - (0x300UL) /*!< DSD_CH FCFGA: CFAC (Bitfield-Mask: 0x03) */ -#define DSD_CH_FCFGA_SRGA_Pos \ - (10UL) /*!< DSD_CH FCFGA: SRGA (Bit 10) */ -#define DSD_CH_FCFGA_SRGA_Msk \ - (0xc00UL) /*!< DSD_CH FCFGA: SRGA (Bitfield-Mask: 0x03) */ -#define DSD_CH_FCFGA_ESEL_Pos \ - (12UL) /*!< DSD_CH FCFGA: ESEL (Bit 12) */ -#define DSD_CH_FCFGA_ESEL_Msk \ - (0x3000UL) /*!< DSD_CH FCFGA: ESEL (Bitfield-Mask: 0x03) */ -#define DSD_CH_FCFGA_EGT_Pos \ - (14UL) /*!< DSD_CH FCFGA: EGT (Bit 14) */ -#define DSD_CH_FCFGA_EGT_Msk \ - (0x4000UL) /*!< DSD_CH FCFGA: EGT (Bitfield-Mask: 0x01) */ -#define DSD_CH_FCFGA_CFADCNT_Pos \ - (24UL) /*!< DSD_CH FCFGA: CFADCNT (Bit 24) */ -#define DSD_CH_FCFGA_CFADCNT_Msk \ - (0xff000000UL) /*!< DSD_CH FCFGA: CFADCNT (Bitfield-Mask: 0xff) */ - -/* -------------------------------- DSD_CH_IWCTR -------------------------------- */ -#define DSD_CH_IWCTR_NVALCNT_Pos \ - (0UL) /*!< DSD_CH IWCTR: NVALCNT (Bit 0) */ -#define DSD_CH_IWCTR_NVALCNT_Msk \ - (0x3fUL) /*!< DSD_CH IWCTR: NVALCNT (Bitfield-Mask: 0x3f) */ -#define DSD_CH_IWCTR_INTEN_Pos \ - (7UL) /*!< DSD_CH IWCTR: INTEN (Bit 7) */ -#define DSD_CH_IWCTR_INTEN_Msk \ - (0x80UL) /*!< DSD_CH IWCTR: INTEN (Bitfield-Mask: 0x01) */ -#define DSD_CH_IWCTR_REPCNT_Pos \ - (8UL) /*!< DSD_CH IWCTR: REPCNT (Bit 8) */ -#define DSD_CH_IWCTR_REPCNT_Msk \ - (0xf00UL) /*!< DSD_CH IWCTR: REPCNT (Bitfield-Mask: 0x0f) */ -#define DSD_CH_IWCTR_REPVAL_Pos \ - (12UL) /*!< DSD_CH IWCTR: REPVAL (Bit 12) */ -#define DSD_CH_IWCTR_REPVAL_Msk \ - (0xf000UL) /*!< DSD_CH IWCTR: REPVAL (Bitfield-Mask: 0x0f) */ -#define DSD_CH_IWCTR_NVALDIS_Pos \ - (16UL) /*!< DSD_CH IWCTR: NVALDIS (Bit 16) */ -#define DSD_CH_IWCTR_NVALDIS_Msk \ - (0x3f0000UL) /*!< DSD_CH IWCTR: NVALDIS (Bitfield-Mask: 0x3f) */ -#define DSD_CH_IWCTR_IWS_Pos \ - (23UL) /*!< DSD_CH IWCTR: IWS (Bit 23) */ -#define DSD_CH_IWCTR_IWS_Msk \ - (0x800000UL) /*!< DSD_CH IWCTR: IWS (Bitfield-Mask: 0x01) */ -#define DSD_CH_IWCTR_NVALINT_Pos \ - (24UL) /*!< DSD_CH IWCTR: NVALINT (Bit 24) */ -#define DSD_CH_IWCTR_NVALINT_Msk \ - (0x3f000000UL) /*!< DSD_CH IWCTR: NVALINT (Bitfield-Mask: 0x3f) */ - -/* ------------------------------- DSD_CH_BOUNDSEL ------------------------------ */ -#define DSD_CH_BOUNDSEL_BOUNDARYL_Pos \ - (0UL) /*!< DSD_CH BOUNDSEL: BOUNDARYL (Bit 0) */ -#define DSD_CH_BOUNDSEL_BOUNDARYL_Msk \ - (0xffffUL) /*!< DSD_CH BOUNDSEL: BOUNDARYL (Bitfield-Mask: 0xffff) */ -#define DSD_CH_BOUNDSEL_BOUNDARYU_Pos \ - (16UL) /*!< DSD_CH BOUNDSEL: BOUNDARYU (Bit 16) */ -#define DSD_CH_BOUNDSEL_BOUNDARYU_Msk \ - (0xffff0000UL) /*!< DSD_CH BOUNDSEL: BOUNDARYU (Bitfield-Mask: 0xffff) */ - -/* --------------------------------- DSD_CH_RESM -------------------------------- */ -#define DSD_CH_RESM_RESULT_Pos \ - (0UL) /*!< DSD_CH RESM: RESULT (Bit 0) */ -#define DSD_CH_RESM_RESULT_Msk \ - (0xffffUL) /*!< DSD_CH RESM: RESULT (Bitfield-Mask: 0xffff) */ - -/* --------------------------------- DSD_CH_OFFM -------------------------------- */ -#define DSD_CH_OFFM_OFFSET_Pos \ - (0UL) /*!< DSD_CH OFFM: OFFSET (Bit 0) */ -#define DSD_CH_OFFM_OFFSET_Msk \ - (0xffffUL) /*!< DSD_CH OFFM: OFFSET (Bitfield-Mask: 0xffff) */ - -/* --------------------------------- DSD_CH_RESA -------------------------------- */ -#define DSD_CH_RESA_RESULT_Pos \ - (0UL) /*!< DSD_CH RESA: RESULT (Bit 0) */ -#define DSD_CH_RESA_RESULT_Msk \ - (0xffffUL) /*!< DSD_CH RESA: RESULT (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- DSD_CH_TSTMP -------------------------------- */ -#define DSD_CH_TSTMP_RESULT_Pos \ - (0UL) /*!< DSD_CH TSTMP: RESULT (Bit 0) */ -#define DSD_CH_TSTMP_RESULT_Msk \ - (0xffffUL) /*!< DSD_CH TSTMP: RESULT (Bitfield-Mask: 0xffff) */ -#define DSD_CH_TSTMP_CFMDCNT_Pos \ - (16UL) /*!< DSD_CH TSTMP: CFMDCNT (Bit 16) */ -#define DSD_CH_TSTMP_CFMDCNT_Msk \ - (0xff0000UL) /*!< DSD_CH TSTMP: CFMDCNT (Bitfield-Mask: 0xff) */ -#define DSD_CH_TSTMP_NVALCNT_Pos \ - (24UL) /*!< DSD_CH TSTMP: NVALCNT (Bit 24) */ -#define DSD_CH_TSTMP_NVALCNT_Msk \ - (0x3f000000UL) /*!< DSD_CH TSTMP: NVALCNT (Bitfield-Mask: 0x3f) */ - -/* -------------------------------- DSD_CH_CGSYNC ------------------------------- */ -#define DSD_CH_CGSYNC_SDCOUNT_Pos \ - (0UL) /*!< DSD_CH CGSYNC: SDCOUNT (Bit 0) */ -#define DSD_CH_CGSYNC_SDCOUNT_Msk \ - (0xffUL) /*!< DSD_CH CGSYNC: SDCOUNT (Bitfield-Mask: 0xff) */ -#define DSD_CH_CGSYNC_SDCAP_Pos \ - (8UL) /*!< DSD_CH CGSYNC: SDCAP (Bit 8) */ -#define DSD_CH_CGSYNC_SDCAP_Msk \ - (0xff00UL) /*!< DSD_CH CGSYNC: SDCAP (Bitfield-Mask: 0xff) */ -#define DSD_CH_CGSYNC_SDPOS_Pos \ - (16UL) /*!< DSD_CH CGSYNC: SDPOS (Bit 16) */ -#define DSD_CH_CGSYNC_SDPOS_Msk \ - (0xff0000UL) /*!< DSD_CH CGSYNC: SDPOS (Bitfield-Mask: 0xff) */ -#define DSD_CH_CGSYNC_SDNEG_Pos \ - (24UL) /*!< DSD_CH CGSYNC: SDNEG (Bit 24) */ -#define DSD_CH_CGSYNC_SDNEG_Msk \ - (0xff000000UL) /*!< DSD_CH CGSYNC: SDNEG (Bitfield-Mask: 0xff) */ - -/* ------------------------------- DSD_CH_RECTCFG ------------------------------- */ -#define DSD_CH_RECTCFG_RFEN_Pos \ - (0UL) /*!< DSD_CH RECTCFG: RFEN (Bit 0) */ -#define DSD_CH_RECTCFG_RFEN_Msk \ - (0x1UL) /*!< DSD_CH RECTCFG: RFEN (Bitfield-Mask: 0x01) */ -#define DSD_CH_RECTCFG_SSRC_Pos \ - (4UL) /*!< DSD_CH RECTCFG: SSRC (Bit 4) */ -#define DSD_CH_RECTCFG_SSRC_Msk \ - (0x30UL) /*!< DSD_CH RECTCFG: SSRC (Bitfield-Mask: 0x03) */ -#define DSD_CH_RECTCFG_SDVAL_Pos \ - (15UL) /*!< DSD_CH RECTCFG: SDVAL (Bit 15) */ -#define DSD_CH_RECTCFG_SDVAL_Msk \ - (0x8000UL) /*!< DSD_CH RECTCFG: SDVAL (Bitfield-Mask: 0x01) */ -#define DSD_CH_RECTCFG_SGNCS_Pos \ - (30UL) /*!< DSD_CH RECTCFG: SGNCS (Bit 30) */ -#define DSD_CH_RECTCFG_SGNCS_Msk \ - (0x40000000UL) /*!< DSD_CH RECTCFG: SGNCS (Bitfield-Mask: 0x01) */ -#define DSD_CH_RECTCFG_SGND_Pos \ - (31UL) /*!< DSD_CH RECTCFG: SGND (Bit 31) */ -#define DSD_CH_RECTCFG_SGND_Msk \ - (0x80000000UL) /*!< DSD_CH RECTCFG: SGND (Bitfield-Mask: 0x01) */ - -/* ================================================================================ */ -/* ================ struct 'DAC' Position & Mask ================ */ -/* ================================================================================ */ - -/* ----------------------------------- DAC_ID ----------------------------------- */ -#define DAC_ID_MODR_Pos (0UL) /*!< DAC ID: MODR (Bit 0) */ -#define DAC_ID_MODR_Msk (0xffUL) /*!< DAC ID: MODR (Bitfield-Mask: 0xff) */ -#define DAC_ID_MODT_Pos (8UL) /*!< DAC ID: MODT (Bit 8) */ -#define DAC_ID_MODT_Msk \ - (0xff00UL) /*!< DAC ID: MODT (Bitfield-Mask: 0xff) */ -#define DAC_ID_MODN_Pos (16UL) /*!< DAC ID: MODN (Bit 16) */ -#define DAC_ID_MODN_Msk \ - (0xffff0000UL) /*!< DAC ID: MODN (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- DAC_DAC0CFG0 -------------------------------- */ -#define DAC_DAC0CFG0_FREQ_Pos \ - (0UL) /*!< DAC DAC0CFG0: FREQ (Bit 0) */ -#define DAC_DAC0CFG0_FREQ_Msk \ - (0xfffffUL) /*!< DAC DAC0CFG0: FREQ (Bitfield-Mask: 0xfffff) */ -#define DAC_DAC0CFG0_MODE_Pos \ - (20UL) /*!< DAC DAC0CFG0: MODE (Bit 20) */ -#define DAC_DAC0CFG0_MODE_Msk \ - (0x700000UL) /*!< DAC DAC0CFG0: MODE (Bitfield-Mask: 0x07) */ -#define DAC_DAC0CFG0_SIGN_Pos \ - (23UL) /*!< DAC DAC0CFG0: SIGN (Bit 23) */ -#define DAC_DAC0CFG0_SIGN_Msk \ - (0x800000UL) /*!< DAC DAC0CFG0: SIGN (Bitfield-Mask: 0x01) */ -#define DAC_DAC0CFG0_FIFOIND_Pos \ - (24UL) /*!< DAC DAC0CFG0: FIFOIND (Bit 24) */ -#define DAC_DAC0CFG0_FIFOIND_Msk \ - (0x3000000UL) /*!< DAC DAC0CFG0: FIFOIND (Bitfield-Mask: 0x03) */ -#define DAC_DAC0CFG0_FIFOEMP_Pos \ - (26UL) /*!< DAC DAC0CFG0: FIFOEMP (Bit 26) */ -#define DAC_DAC0CFG0_FIFOEMP_Msk \ - (0x4000000UL) /*!< DAC DAC0CFG0: FIFOEMP (Bitfield-Mask: 0x01) */ -#define DAC_DAC0CFG0_FIFOFUL_Pos \ - (27UL) /*!< DAC DAC0CFG0: FIFOFUL (Bit 27) */ -#define DAC_DAC0CFG0_FIFOFUL_Msk \ - (0x8000000UL) /*!< DAC DAC0CFG0: FIFOFUL (Bitfield-Mask: 0x01) */ -#define DAC_DAC0CFG0_NEGATE_Pos \ - (28UL) /*!< DAC DAC0CFG0: NEGATE (Bit 28) */ -#define DAC_DAC0CFG0_NEGATE_Msk \ - (0x10000000UL) /*!< DAC DAC0CFG0: NEGATE (Bitfield-Mask: 0x01) */ -#define DAC_DAC0CFG0_SIGNEN_Pos \ - (29UL) /*!< DAC DAC0CFG0: SIGNEN (Bit 29) */ -#define DAC_DAC0CFG0_SIGNEN_Msk \ - (0x20000000UL) /*!< DAC DAC0CFG0: SIGNEN (Bitfield-Mask: 0x01) */ -#define DAC_DAC0CFG0_SREN_Pos \ - (30UL) /*!< DAC DAC0CFG0: SREN (Bit 30) */ -#define DAC_DAC0CFG0_SREN_Msk \ - (0x40000000UL) /*!< DAC DAC0CFG0: SREN (Bitfield-Mask: 0x01) */ -#define DAC_DAC0CFG0_RUN_Pos \ - (31UL) /*!< DAC DAC0CFG0: RUN (Bit 31) */ -#define DAC_DAC0CFG0_RUN_Msk \ - (0x80000000UL) /*!< DAC DAC0CFG0: RUN (Bitfield-Mask: 0x01) */ - -/* -------------------------------- DAC_DAC0CFG1 -------------------------------- */ -#define DAC_DAC0CFG1_SCALE_Pos \ - (0UL) /*!< DAC DAC0CFG1: SCALE (Bit 0) */ -#define DAC_DAC0CFG1_SCALE_Msk \ - (0x7UL) /*!< DAC DAC0CFG1: SCALE (Bitfield-Mask: 0x07) */ -#define DAC_DAC0CFG1_MULDIV_Pos \ - (3UL) /*!< DAC DAC0CFG1: MULDIV (Bit 3) */ -#define DAC_DAC0CFG1_MULDIV_Msk \ - (0x8UL) /*!< DAC DAC0CFG1: MULDIV (Bitfield-Mask: 0x01) */ -#define DAC_DAC0CFG1_OFFS_Pos \ - (4UL) /*!< DAC DAC0CFG1: OFFS (Bit 4) */ -#define DAC_DAC0CFG1_OFFS_Msk \ - (0xff0UL) /*!< DAC DAC0CFG1: OFFS (Bitfield-Mask: 0xff) */ -#define DAC_DAC0CFG1_TRIGSEL_Pos \ - (12UL) /*!< DAC DAC0CFG1: TRIGSEL (Bit 12) */ -#define DAC_DAC0CFG1_TRIGSEL_Msk \ - (0x7000UL) /*!< DAC DAC0CFG1: TRIGSEL (Bitfield-Mask: 0x07) */ -#define DAC_DAC0CFG1_DATMOD_Pos \ - (15UL) /*!< DAC DAC0CFG1: DATMOD (Bit 15) */ -#define DAC_DAC0CFG1_DATMOD_Msk \ - (0x8000UL) /*!< DAC DAC0CFG1: DATMOD (Bitfield-Mask: 0x01) */ -#define DAC_DAC0CFG1_SWTRIG_Pos \ - (16UL) /*!< DAC DAC0CFG1: SWTRIG (Bit 16) */ -#define DAC_DAC0CFG1_SWTRIG_Msk \ - (0x10000UL) /*!< DAC DAC0CFG1: SWTRIG (Bitfield-Mask: 0x01) */ -#define DAC_DAC0CFG1_TRIGMOD_Pos \ - (17UL) /*!< DAC DAC0CFG1: TRIGMOD (Bit 17) */ -#define DAC_DAC0CFG1_TRIGMOD_Msk \ - (0x60000UL) /*!< DAC DAC0CFG1: TRIGMOD (Bitfield-Mask: 0x03) */ -#define DAC_DAC0CFG1_ANACFG_Pos \ - (19UL) /*!< DAC DAC0CFG1: ANACFG (Bit 19) */ -#define DAC_DAC0CFG1_ANACFG_Msk \ - (0xf80000UL) /*!< DAC DAC0CFG1: ANACFG (Bitfield-Mask: 0x1f) */ -#define DAC_DAC0CFG1_ANAEN_Pos \ - (24UL) /*!< DAC DAC0CFG1: ANAEN (Bit 24) */ -#define DAC_DAC0CFG1_ANAEN_Msk \ - (0x1000000UL) /*!< DAC DAC0CFG1: ANAEN (Bitfield-Mask: 0x01) */ -#define DAC_DAC0CFG1_REFCFGL_Pos \ - (28UL) /*!< DAC DAC0CFG1: REFCFGL (Bit 28) */ -#define DAC_DAC0CFG1_REFCFGL_Msk \ - (0xf0000000UL) /*!< DAC DAC0CFG1: REFCFGL (Bitfield-Mask: 0x0f) */ - -/* -------------------------------- DAC_DAC1CFG0 -------------------------------- */ -#define DAC_DAC1CFG0_FREQ_Pos \ - (0UL) /*!< DAC DAC1CFG0: FREQ (Bit 0) */ -#define DAC_DAC1CFG0_FREQ_Msk \ - (0xfffffUL) /*!< DAC DAC1CFG0: FREQ (Bitfield-Mask: 0xfffff) */ -#define DAC_DAC1CFG0_MODE_Pos \ - (20UL) /*!< DAC DAC1CFG0: MODE (Bit 20) */ -#define DAC_DAC1CFG0_MODE_Msk \ - (0x700000UL) /*!< DAC DAC1CFG0: MODE (Bitfield-Mask: 0x07) */ -#define DAC_DAC1CFG0_SIGN_Pos \ - (23UL) /*!< DAC DAC1CFG0: SIGN (Bit 23) */ -#define DAC_DAC1CFG0_SIGN_Msk \ - (0x800000UL) /*!< DAC DAC1CFG0: SIGN (Bitfield-Mask: 0x01) */ -#define DAC_DAC1CFG0_FIFOIND_Pos \ - (24UL) /*!< DAC DAC1CFG0: FIFOIND (Bit 24) */ -#define DAC_DAC1CFG0_FIFOIND_Msk \ - (0x3000000UL) /*!< DAC DAC1CFG0: FIFOIND (Bitfield-Mask: 0x03) */ -#define DAC_DAC1CFG0_FIFOEMP_Pos \ - (26UL) /*!< DAC DAC1CFG0: FIFOEMP (Bit 26) */ -#define DAC_DAC1CFG0_FIFOEMP_Msk \ - (0x4000000UL) /*!< DAC DAC1CFG0: FIFOEMP (Bitfield-Mask: 0x01) */ -#define DAC_DAC1CFG0_FIFOFUL_Pos \ - (27UL) /*!< DAC DAC1CFG0: FIFOFUL (Bit 27) */ -#define DAC_DAC1CFG0_FIFOFUL_Msk \ - (0x8000000UL) /*!< DAC DAC1CFG0: FIFOFUL (Bitfield-Mask: 0x01) */ -#define DAC_DAC1CFG0_NEGATE_Pos \ - (28UL) /*!< DAC DAC1CFG0: NEGATE (Bit 28) */ -#define DAC_DAC1CFG0_NEGATE_Msk \ - (0x10000000UL) /*!< DAC DAC1CFG0: NEGATE (Bitfield-Mask: 0x01) */ -#define DAC_DAC1CFG0_SIGNEN_Pos \ - (29UL) /*!< DAC DAC1CFG0: SIGNEN (Bit 29) */ -#define DAC_DAC1CFG0_SIGNEN_Msk \ - (0x20000000UL) /*!< DAC DAC1CFG0: SIGNEN (Bitfield-Mask: 0x01) */ -#define DAC_DAC1CFG0_SREN_Pos \ - (30UL) /*!< DAC DAC1CFG0: SREN (Bit 30) */ -#define DAC_DAC1CFG0_SREN_Msk \ - (0x40000000UL) /*!< DAC DAC1CFG0: SREN (Bitfield-Mask: 0x01) */ -#define DAC_DAC1CFG0_RUN_Pos \ - (31UL) /*!< DAC DAC1CFG0: RUN (Bit 31) */ -#define DAC_DAC1CFG0_RUN_Msk \ - (0x80000000UL) /*!< DAC DAC1CFG0: RUN (Bitfield-Mask: 0x01) */ - -/* -------------------------------- DAC_DAC1CFG1 -------------------------------- */ -#define DAC_DAC1CFG1_SCALE_Pos \ - (0UL) /*!< DAC DAC1CFG1: SCALE (Bit 0) */ -#define DAC_DAC1CFG1_SCALE_Msk \ - (0x7UL) /*!< DAC DAC1CFG1: SCALE (Bitfield-Mask: 0x07) */ -#define DAC_DAC1CFG1_MULDIV_Pos \ - (3UL) /*!< DAC DAC1CFG1: MULDIV (Bit 3) */ -#define DAC_DAC1CFG1_MULDIV_Msk \ - (0x8UL) /*!< DAC DAC1CFG1: MULDIV (Bitfield-Mask: 0x01) */ -#define DAC_DAC1CFG1_OFFS_Pos \ - (4UL) /*!< DAC DAC1CFG1: OFFS (Bit 4) */ -#define DAC_DAC1CFG1_OFFS_Msk \ - (0xff0UL) /*!< DAC DAC1CFG1: OFFS (Bitfield-Mask: 0xff) */ -#define DAC_DAC1CFG1_TRIGSEL_Pos \ - (12UL) /*!< DAC DAC1CFG1: TRIGSEL (Bit 12) */ -#define DAC_DAC1CFG1_TRIGSEL_Msk \ - (0x7000UL) /*!< DAC DAC1CFG1: TRIGSEL (Bitfield-Mask: 0x07) */ -#define DAC_DAC1CFG1_SWTRIG_Pos \ - (16UL) /*!< DAC DAC1CFG1: SWTRIG (Bit 16) */ -#define DAC_DAC1CFG1_SWTRIG_Msk \ - (0x10000UL) /*!< DAC DAC1CFG1: SWTRIG (Bitfield-Mask: 0x01) */ -#define DAC_DAC1CFG1_TRIGMOD_Pos \ - (17UL) /*!< DAC DAC1CFG1: TRIGMOD (Bit 17) */ -#define DAC_DAC1CFG1_TRIGMOD_Msk \ - (0x60000UL) /*!< DAC DAC1CFG1: TRIGMOD (Bitfield-Mask: 0x03) */ -#define DAC_DAC1CFG1_ANACFG_Pos \ - (19UL) /*!< DAC DAC1CFG1: ANACFG (Bit 19) */ -#define DAC_DAC1CFG1_ANACFG_Msk \ - (0xf80000UL) /*!< DAC DAC1CFG1: ANACFG (Bitfield-Mask: 0x1f) */ -#define DAC_DAC1CFG1_ANAEN_Pos \ - (24UL) /*!< DAC DAC1CFG1: ANAEN (Bit 24) */ -#define DAC_DAC1CFG1_ANAEN_Msk \ - (0x1000000UL) /*!< DAC DAC1CFG1: ANAEN (Bitfield-Mask: 0x01) */ -#define DAC_DAC1CFG1_REFCFGH_Pos \ - (28UL) /*!< DAC DAC1CFG1: REFCFGH (Bit 28) */ -#define DAC_DAC1CFG1_REFCFGH_Msk \ - (0xf0000000UL) /*!< DAC DAC1CFG1: REFCFGH (Bitfield-Mask: 0x0f) */ - -/* -------------------------------- DAC_DAC0DATA -------------------------------- */ -#define DAC_DAC0DATA_DATA0_Pos \ - (0UL) /*!< DAC DAC0DATA: DATA0 (Bit 0) */ -#define DAC_DAC0DATA_DATA0_Msk \ - (0xfffUL) /*!< DAC DAC0DATA: DATA0 (Bitfield-Mask: 0xfff) */ - -/* -------------------------------- DAC_DAC1DATA -------------------------------- */ -#define DAC_DAC1DATA_DATA1_Pos \ - (0UL) /*!< DAC DAC1DATA: DATA1 (Bit 0) */ -#define DAC_DAC1DATA_DATA1_Msk \ - (0xfffUL) /*!< DAC DAC1DATA: DATA1 (Bitfield-Mask: 0xfff) */ - -/* -------------------------------- DAC_DAC01DATA ------------------------------- */ -#define DAC_DAC01DATA_DATA0_Pos \ - (0UL) /*!< DAC DAC01DATA: DATA0 (Bit 0) */ -#define DAC_DAC01DATA_DATA0_Msk \ - (0xfffUL) /*!< DAC DAC01DATA: DATA0 (Bitfield-Mask: 0xfff) */ -#define DAC_DAC01DATA_DATA1_Pos \ - (16UL) /*!< DAC DAC01DATA: DATA1 (Bit 16) */ -#define DAC_DAC01DATA_DATA1_Msk \ - (0xfff0000UL) /*!< DAC DAC01DATA: DATA1 (Bitfield-Mask: 0xfff) */ - -/* -------------------------------- DAC_DAC0PATL -------------------------------- */ -#define DAC_DAC0PATL_PAT0_Pos \ - (0UL) /*!< DAC DAC0PATL: PAT0 (Bit 0) */ -#define DAC_DAC0PATL_PAT0_Msk \ - (0x1fUL) /*!< DAC DAC0PATL: PAT0 (Bitfield-Mask: 0x1f) */ -#define DAC_DAC0PATL_PAT1_Pos \ - (5UL) /*!< DAC DAC0PATL: PAT1 (Bit 5) */ -#define DAC_DAC0PATL_PAT1_Msk \ - (0x3e0UL) /*!< DAC DAC0PATL: PAT1 (Bitfield-Mask: 0x1f) */ -#define DAC_DAC0PATL_PAT2_Pos \ - (10UL) /*!< DAC DAC0PATL: PAT2 (Bit 10) */ -#define DAC_DAC0PATL_PAT2_Msk \ - (0x7c00UL) /*!< DAC DAC0PATL: PAT2 (Bitfield-Mask: 0x1f) */ -#define DAC_DAC0PATL_PAT3_Pos \ - (15UL) /*!< DAC DAC0PATL: PAT3 (Bit 15) */ -#define DAC_DAC0PATL_PAT3_Msk \ - (0xf8000UL) /*!< DAC DAC0PATL: PAT3 (Bitfield-Mask: 0x1f) */ -#define DAC_DAC0PATL_PAT4_Pos \ - (20UL) /*!< DAC DAC0PATL: PAT4 (Bit 20) */ -#define DAC_DAC0PATL_PAT4_Msk \ - (0x1f00000UL) /*!< DAC DAC0PATL: PAT4 (Bitfield-Mask: 0x1f) */ -#define DAC_DAC0PATL_PAT5_Pos \ - (25UL) /*!< DAC DAC0PATL: PAT5 (Bit 25) */ -#define DAC_DAC0PATL_PAT5_Msk \ - (0x3e000000UL) /*!< DAC DAC0PATL: PAT5 (Bitfield-Mask: 0x1f) */ - -/* -------------------------------- DAC_DAC0PATH -------------------------------- */ -#define DAC_DAC0PATH_PAT6_Pos \ - (0UL) /*!< DAC DAC0PATH: PAT6 (Bit 0) */ -#define DAC_DAC0PATH_PAT6_Msk \ - (0x1fUL) /*!< DAC DAC0PATH: PAT6 (Bitfield-Mask: 0x1f) */ -#define DAC_DAC0PATH_PAT7_Pos \ - (5UL) /*!< DAC DAC0PATH: PAT7 (Bit 5) */ -#define DAC_DAC0PATH_PAT7_Msk \ - (0x3e0UL) /*!< DAC DAC0PATH: PAT7 (Bitfield-Mask: 0x1f) */ -#define DAC_DAC0PATH_PAT8_Pos \ - (10UL) /*!< DAC DAC0PATH: PAT8 (Bit 10) */ -#define DAC_DAC0PATH_PAT8_Msk \ - (0x7c00UL) /*!< DAC DAC0PATH: PAT8 (Bitfield-Mask: 0x1f) */ - -/* -------------------------------- DAC_DAC1PATL -------------------------------- */ -#define DAC_DAC1PATL_PAT0_Pos \ - (0UL) /*!< DAC DAC1PATL: PAT0 (Bit 0) */ -#define DAC_DAC1PATL_PAT0_Msk \ - (0x1fUL) /*!< DAC DAC1PATL: PAT0 (Bitfield-Mask: 0x1f) */ -#define DAC_DAC1PATL_PAT1_Pos \ - (5UL) /*!< DAC DAC1PATL: PAT1 (Bit 5) */ -#define DAC_DAC1PATL_PAT1_Msk \ - (0x3e0UL) /*!< DAC DAC1PATL: PAT1 (Bitfield-Mask: 0x1f) */ -#define DAC_DAC1PATL_PAT2_Pos \ - (10UL) /*!< DAC DAC1PATL: PAT2 (Bit 10) */ -#define DAC_DAC1PATL_PAT2_Msk \ - (0x7c00UL) /*!< DAC DAC1PATL: PAT2 (Bitfield-Mask: 0x1f) */ -#define DAC_DAC1PATL_PAT3_Pos \ - (15UL) /*!< DAC DAC1PATL: PAT3 (Bit 15) */ -#define DAC_DAC1PATL_PAT3_Msk \ - (0xf8000UL) /*!< DAC DAC1PATL: PAT3 (Bitfield-Mask: 0x1f) */ -#define DAC_DAC1PATL_PAT4_Pos \ - (20UL) /*!< DAC DAC1PATL: PAT4 (Bit 20) */ -#define DAC_DAC1PATL_PAT4_Msk \ - (0x1f00000UL) /*!< DAC DAC1PATL: PAT4 (Bitfield-Mask: 0x1f) */ -#define DAC_DAC1PATL_PAT5_Pos \ - (25UL) /*!< DAC DAC1PATL: PAT5 (Bit 25) */ -#define DAC_DAC1PATL_PAT5_Msk \ - (0x3e000000UL) /*!< DAC DAC1PATL: PAT5 (Bitfield-Mask: 0x1f) */ - -/* -------------------------------- DAC_DAC1PATH -------------------------------- */ -#define DAC_DAC1PATH_PAT6_Pos \ - (0UL) /*!< DAC DAC1PATH: PAT6 (Bit 0) */ -#define DAC_DAC1PATH_PAT6_Msk \ - (0x1fUL) /*!< DAC DAC1PATH: PAT6 (Bitfield-Mask: 0x1f) */ -#define DAC_DAC1PATH_PAT7_Pos \ - (5UL) /*!< DAC DAC1PATH: PAT7 (Bit 5) */ -#define DAC_DAC1PATH_PAT7_Msk \ - (0x3e0UL) /*!< DAC DAC1PATH: PAT7 (Bitfield-Mask: 0x1f) */ -#define DAC_DAC1PATH_PAT8_Pos \ - (10UL) /*!< DAC DAC1PATH: PAT8 (Bit 10) */ -#define DAC_DAC1PATH_PAT8_Msk \ - (0x7c00UL) /*!< DAC DAC1PATH: PAT8 (Bitfield-Mask: 0x1f) */ - -/* ================================================================================ */ -/* ================ Group 'CCU4' Position & Mask ================ */ -/* ================================================================================ */ - -/* --------------------------------- CCU4_GCTRL --------------------------------- */ -#define CCU4_GCTRL_PRBC_Pos \ - (0UL) /*!< CCU4 GCTRL: PRBC (Bit 0) */ -#define CCU4_GCTRL_PRBC_Msk \ - (0x7UL) /*!< CCU4 GCTRL: PRBC (Bitfield-Mask: 0x07) */ -#define CCU4_GCTRL_PCIS_Pos \ - (4UL) /*!< CCU4 GCTRL: PCIS (Bit 4) */ -#define CCU4_GCTRL_PCIS_Msk \ - (0x30UL) /*!< CCU4 GCTRL: PCIS (Bitfield-Mask: 0x03) */ -#define CCU4_GCTRL_SUSCFG_Pos \ - (8UL) /*!< CCU4 GCTRL: SUSCFG (Bit 8) */ -#define CCU4_GCTRL_SUSCFG_Msk \ - (0x300UL) /*!< CCU4 GCTRL: SUSCFG (Bitfield-Mask: 0x03) */ -#define CCU4_GCTRL_MSE0_Pos \ - (10UL) /*!< CCU4 GCTRL: MSE0 (Bit 10) */ -#define CCU4_GCTRL_MSE0_Msk \ - (0x400UL) /*!< CCU4 GCTRL: MSE0 (Bitfield-Mask: 0x01) */ -#define CCU4_GCTRL_MSE1_Pos \ - (11UL) /*!< CCU4 GCTRL: MSE1 (Bit 11) */ -#define CCU4_GCTRL_MSE1_Msk \ - (0x800UL) /*!< CCU4 GCTRL: MSE1 (Bitfield-Mask: 0x01) */ -#define CCU4_GCTRL_MSE2_Pos \ - (12UL) /*!< CCU4 GCTRL: MSE2 (Bit 12) */ -#define CCU4_GCTRL_MSE2_Msk \ - (0x1000UL) /*!< CCU4 GCTRL: MSE2 (Bitfield-Mask: 0x01) */ -#define CCU4_GCTRL_MSE3_Pos \ - (13UL) /*!< CCU4 GCTRL: MSE3 (Bit 13) */ -#define CCU4_GCTRL_MSE3_Msk \ - (0x2000UL) /*!< CCU4 GCTRL: MSE3 (Bitfield-Mask: 0x01) */ -#define CCU4_GCTRL_MSDE_Pos \ - (14UL) /*!< CCU4 GCTRL: MSDE (Bit 14) */ -#define CCU4_GCTRL_MSDE_Msk \ - (0xc000UL) /*!< CCU4 GCTRL: MSDE (Bitfield-Mask: 0x03) */ - -/* --------------------------------- CCU4_GSTAT --------------------------------- */ -#define CCU4_GSTAT_S0I_Pos (0UL) /*!< CCU4 GSTAT: S0I (Bit 0) */ -#define CCU4_GSTAT_S0I_Msk \ - (0x1UL) /*!< CCU4 GSTAT: S0I (Bitfield-Mask: 0x01) */ -#define CCU4_GSTAT_S1I_Pos (1UL) /*!< CCU4 GSTAT: S1I (Bit 1) */ -#define CCU4_GSTAT_S1I_Msk \ - (0x2UL) /*!< CCU4 GSTAT: S1I (Bitfield-Mask: 0x01) */ -#define CCU4_GSTAT_S2I_Pos (2UL) /*!< CCU4 GSTAT: S2I (Bit 2) */ -#define CCU4_GSTAT_S2I_Msk \ - (0x4UL) /*!< CCU4 GSTAT: S2I (Bitfield-Mask: 0x01) */ -#define CCU4_GSTAT_S3I_Pos (3UL) /*!< CCU4 GSTAT: S3I (Bit 3) */ -#define CCU4_GSTAT_S3I_Msk \ - (0x8UL) /*!< CCU4 GSTAT: S3I (Bitfield-Mask: 0x01) */ -#define CCU4_GSTAT_PRB_Pos (8UL) /*!< CCU4 GSTAT: PRB (Bit 8) */ -#define CCU4_GSTAT_PRB_Msk \ - (0x100UL) /*!< CCU4 GSTAT: PRB (Bitfield-Mask: 0x01) */ - -/* --------------------------------- CCU4_GIDLS --------------------------------- */ -#define CCU4_GIDLS_SS0I_Pos \ - (0UL) /*!< CCU4 GIDLS: SS0I (Bit 0) */ -#define CCU4_GIDLS_SS0I_Msk \ - (0x1UL) /*!< CCU4 GIDLS: SS0I (Bitfield-Mask: 0x01) */ -#define CCU4_GIDLS_SS1I_Pos \ - (1UL) /*!< CCU4 GIDLS: SS1I (Bit 1) */ -#define CCU4_GIDLS_SS1I_Msk \ - (0x2UL) /*!< CCU4 GIDLS: SS1I (Bitfield-Mask: 0x01) */ -#define CCU4_GIDLS_SS2I_Pos \ - (2UL) /*!< CCU4 GIDLS: SS2I (Bit 2) */ -#define CCU4_GIDLS_SS2I_Msk \ - (0x4UL) /*!< CCU4 GIDLS: SS2I (Bitfield-Mask: 0x01) */ -#define CCU4_GIDLS_SS3I_Pos \ - (3UL) /*!< CCU4 GIDLS: SS3I (Bit 3) */ -#define CCU4_GIDLS_SS3I_Msk \ - (0x8UL) /*!< CCU4 GIDLS: SS3I (Bitfield-Mask: 0x01) */ -#define CCU4_GIDLS_CPRB_Pos \ - (8UL) /*!< CCU4 GIDLS: CPRB (Bit 8) */ -#define CCU4_GIDLS_CPRB_Msk \ - (0x100UL) /*!< CCU4 GIDLS: CPRB (Bitfield-Mask: 0x01) */ -#define CCU4_GIDLS_PSIC_Pos \ - (9UL) /*!< CCU4 GIDLS: PSIC (Bit 9) */ -#define CCU4_GIDLS_PSIC_Msk \ - (0x200UL) /*!< CCU4 GIDLS: PSIC (Bitfield-Mask: 0x01) */ - -/* --------------------------------- CCU4_GIDLC --------------------------------- */ -#define CCU4_GIDLC_CS0I_Pos \ - (0UL) /*!< CCU4 GIDLC: CS0I (Bit 0) */ -#define CCU4_GIDLC_CS0I_Msk \ - (0x1UL) /*!< CCU4 GIDLC: CS0I (Bitfield-Mask: 0x01) */ -#define CCU4_GIDLC_CS1I_Pos \ - (1UL) /*!< CCU4 GIDLC: CS1I (Bit 1) */ -#define CCU4_GIDLC_CS1I_Msk \ - (0x2UL) /*!< CCU4 GIDLC: CS1I (Bitfield-Mask: 0x01) */ -#define CCU4_GIDLC_CS2I_Pos \ - (2UL) /*!< CCU4 GIDLC: CS2I (Bit 2) */ -#define CCU4_GIDLC_CS2I_Msk \ - (0x4UL) /*!< CCU4 GIDLC: CS2I (Bitfield-Mask: 0x01) */ -#define CCU4_GIDLC_CS3I_Pos \ - (3UL) /*!< CCU4 GIDLC: CS3I (Bit 3) */ -#define CCU4_GIDLC_CS3I_Msk \ - (0x8UL) /*!< CCU4 GIDLC: CS3I (Bitfield-Mask: 0x01) */ -#define CCU4_GIDLC_SPRB_Pos \ - (8UL) /*!< CCU4 GIDLC: SPRB (Bit 8) */ -#define CCU4_GIDLC_SPRB_Msk \ - (0x100UL) /*!< CCU4 GIDLC: SPRB (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- CCU4_GCSS --------------------------------- */ -#define CCU4_GCSS_S0SE_Pos (0UL) /*!< CCU4 GCSS: S0SE (Bit 0) */ -#define CCU4_GCSS_S0SE_Msk \ - (0x1UL) /*!< CCU4 GCSS: S0SE (Bitfield-Mask: 0x01) */ -#define CCU4_GCSS_S0DSE_Pos \ - (1UL) /*!< CCU4 GCSS: S0DSE (Bit 1) */ -#define CCU4_GCSS_S0DSE_Msk \ - (0x2UL) /*!< CCU4 GCSS: S0DSE (Bitfield-Mask: 0x01) */ -#define CCU4_GCSS_S0PSE_Pos \ - (2UL) /*!< CCU4 GCSS: S0PSE (Bit 2) */ -#define CCU4_GCSS_S0PSE_Msk \ - (0x4UL) /*!< CCU4 GCSS: S0PSE (Bitfield-Mask: 0x01) */ -#define CCU4_GCSS_S1SE_Pos (4UL) /*!< CCU4 GCSS: S1SE (Bit 4) */ -#define CCU4_GCSS_S1SE_Msk \ - (0x10UL) /*!< CCU4 GCSS: S1SE (Bitfield-Mask: 0x01) */ -#define CCU4_GCSS_S1DSE_Pos \ - (5UL) /*!< CCU4 GCSS: S1DSE (Bit 5) */ -#define CCU4_GCSS_S1DSE_Msk \ - (0x20UL) /*!< CCU4 GCSS: S1DSE (Bitfield-Mask: 0x01) */ -#define CCU4_GCSS_S1PSE_Pos \ - (6UL) /*!< CCU4 GCSS: S1PSE (Bit 6) */ -#define CCU4_GCSS_S1PSE_Msk \ - (0x40UL) /*!< CCU4 GCSS: S1PSE (Bitfield-Mask: 0x01) */ -#define CCU4_GCSS_S2SE_Pos (8UL) /*!< CCU4 GCSS: S2SE (Bit 8) */ -#define CCU4_GCSS_S2SE_Msk \ - (0x100UL) /*!< CCU4 GCSS: S2SE (Bitfield-Mask: 0x01) */ -#define CCU4_GCSS_S2DSE_Pos \ - (9UL) /*!< CCU4 GCSS: S2DSE (Bit 9) */ -#define CCU4_GCSS_S2DSE_Msk \ - (0x200UL) /*!< CCU4 GCSS: S2DSE (Bitfield-Mask: 0x01) */ -#define CCU4_GCSS_S2PSE_Pos \ - (10UL) /*!< CCU4 GCSS: S2PSE (Bit 10) */ -#define CCU4_GCSS_S2PSE_Msk \ - (0x400UL) /*!< CCU4 GCSS: S2PSE (Bitfield-Mask: 0x01) */ -#define CCU4_GCSS_S3SE_Pos \ - (12UL) /*!< CCU4 GCSS: S3SE (Bit 12) */ -#define CCU4_GCSS_S3SE_Msk \ - (0x1000UL) /*!< CCU4 GCSS: S3SE (Bitfield-Mask: 0x01) */ -#define CCU4_GCSS_S3DSE_Pos \ - (13UL) /*!< CCU4 GCSS: S3DSE (Bit 13) */ -#define CCU4_GCSS_S3DSE_Msk \ - (0x2000UL) /*!< CCU4 GCSS: S3DSE (Bitfield-Mask: 0x01) */ -#define CCU4_GCSS_S3PSE_Pos \ - (14UL) /*!< CCU4 GCSS: S3PSE (Bit 14) */ -#define CCU4_GCSS_S3PSE_Msk \ - (0x4000UL) /*!< CCU4 GCSS: S3PSE (Bitfield-Mask: 0x01) */ -#define CCU4_GCSS_S0STS_Pos \ - (16UL) /*!< CCU4 GCSS: S0STS (Bit 16) */ -#define CCU4_GCSS_S0STS_Msk \ - (0x10000UL) /*!< CCU4 GCSS: S0STS (Bitfield-Mask: 0x01) */ -#define CCU4_GCSS_S1STS_Pos \ - (17UL) /*!< CCU4 GCSS: S1STS (Bit 17) */ -#define CCU4_GCSS_S1STS_Msk \ - (0x20000UL) /*!< CCU4 GCSS: S1STS (Bitfield-Mask: 0x01) */ -#define CCU4_GCSS_S2STS_Pos \ - (18UL) /*!< CCU4 GCSS: S2STS (Bit 18) */ -#define CCU4_GCSS_S2STS_Msk \ - (0x40000UL) /*!< CCU4 GCSS: S2STS (Bitfield-Mask: 0x01) */ -#define CCU4_GCSS_S3STS_Pos \ - (19UL) /*!< CCU4 GCSS: S3STS (Bit 19) */ -#define CCU4_GCSS_S3STS_Msk \ - (0x80000UL) /*!< CCU4 GCSS: S3STS (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- CCU4_GCSC --------------------------------- */ -#define CCU4_GCSC_S0SC_Pos (0UL) /*!< CCU4 GCSC: S0SC (Bit 0) */ -#define CCU4_GCSC_S0SC_Msk \ - (0x1UL) /*!< CCU4 GCSC: S0SC (Bitfield-Mask: 0x01) */ -#define CCU4_GCSC_S0DSC_Pos \ - (1UL) /*!< CCU4 GCSC: S0DSC (Bit 1) */ -#define CCU4_GCSC_S0DSC_Msk \ - (0x2UL) /*!< CCU4 GCSC: S0DSC (Bitfield-Mask: 0x01) */ -#define CCU4_GCSC_S0PSC_Pos \ - (2UL) /*!< CCU4 GCSC: S0PSC (Bit 2) */ -#define CCU4_GCSC_S0PSC_Msk \ - (0x4UL) /*!< CCU4 GCSC: S0PSC (Bitfield-Mask: 0x01) */ -#define CCU4_GCSC_S1SC_Pos (4UL) /*!< CCU4 GCSC: S1SC (Bit 4) */ -#define CCU4_GCSC_S1SC_Msk \ - (0x10UL) /*!< CCU4 GCSC: S1SC (Bitfield-Mask: 0x01) */ -#define CCU4_GCSC_S1DSC_Pos \ - (5UL) /*!< CCU4 GCSC: S1DSC (Bit 5) */ -#define CCU4_GCSC_S1DSC_Msk \ - (0x20UL) /*!< CCU4 GCSC: S1DSC (Bitfield-Mask: 0x01) */ -#define CCU4_GCSC_S1PSC_Pos \ - (6UL) /*!< CCU4 GCSC: S1PSC (Bit 6) */ -#define CCU4_GCSC_S1PSC_Msk \ - (0x40UL) /*!< CCU4 GCSC: S1PSC (Bitfield-Mask: 0x01) */ -#define CCU4_GCSC_S2SC_Pos (8UL) /*!< CCU4 GCSC: S2SC (Bit 8) */ -#define CCU4_GCSC_S2SC_Msk \ - (0x100UL) /*!< CCU4 GCSC: S2SC (Bitfield-Mask: 0x01) */ -#define CCU4_GCSC_S2DSC_Pos \ - (9UL) /*!< CCU4 GCSC: S2DSC (Bit 9) */ -#define CCU4_GCSC_S2DSC_Msk \ - (0x200UL) /*!< CCU4 GCSC: S2DSC (Bitfield-Mask: 0x01) */ -#define CCU4_GCSC_S2PSC_Pos \ - (10UL) /*!< CCU4 GCSC: S2PSC (Bit 10) */ -#define CCU4_GCSC_S2PSC_Msk \ - (0x400UL) /*!< CCU4 GCSC: S2PSC (Bitfield-Mask: 0x01) */ -#define CCU4_GCSC_S3SC_Pos \ - (12UL) /*!< CCU4 GCSC: S3SC (Bit 12) */ -#define CCU4_GCSC_S3SC_Msk \ - (0x1000UL) /*!< CCU4 GCSC: S3SC (Bitfield-Mask: 0x01) */ -#define CCU4_GCSC_S3DSC_Pos \ - (13UL) /*!< CCU4 GCSC: S3DSC (Bit 13) */ -#define CCU4_GCSC_S3DSC_Msk \ - (0x2000UL) /*!< CCU4 GCSC: S3DSC (Bitfield-Mask: 0x01) */ -#define CCU4_GCSC_S3PSC_Pos \ - (14UL) /*!< CCU4 GCSC: S3PSC (Bit 14) */ -#define CCU4_GCSC_S3PSC_Msk \ - (0x4000UL) /*!< CCU4 GCSC: S3PSC (Bitfield-Mask: 0x01) */ -#define CCU4_GCSC_S0STC_Pos \ - (16UL) /*!< CCU4 GCSC: S0STC (Bit 16) */ -#define CCU4_GCSC_S0STC_Msk \ - (0x10000UL) /*!< CCU4 GCSC: S0STC (Bitfield-Mask: 0x01) */ -#define CCU4_GCSC_S1STC_Pos \ - (17UL) /*!< CCU4 GCSC: S1STC (Bit 17) */ -#define CCU4_GCSC_S1STC_Msk \ - (0x20000UL) /*!< CCU4 GCSC: S1STC (Bitfield-Mask: 0x01) */ -#define CCU4_GCSC_S2STC_Pos \ - (18UL) /*!< CCU4 GCSC: S2STC (Bit 18) */ -#define CCU4_GCSC_S2STC_Msk \ - (0x40000UL) /*!< CCU4 GCSC: S2STC (Bitfield-Mask: 0x01) */ -#define CCU4_GCSC_S3STC_Pos \ - (19UL) /*!< CCU4 GCSC: S3STC (Bit 19) */ -#define CCU4_GCSC_S3STC_Msk \ - (0x80000UL) /*!< CCU4 GCSC: S3STC (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- CCU4_GCST --------------------------------- */ -#define CCU4_GCST_S0SS_Pos (0UL) /*!< CCU4 GCST: S0SS (Bit 0) */ -#define CCU4_GCST_S0SS_Msk \ - (0x1UL) /*!< CCU4 GCST: S0SS (Bitfield-Mask: 0x01) */ -#define CCU4_GCST_S0DSS_Pos \ - (1UL) /*!< CCU4 GCST: S0DSS (Bit 1) */ -#define CCU4_GCST_S0DSS_Msk \ - (0x2UL) /*!< CCU4 GCST: S0DSS (Bitfield-Mask: 0x01) */ -#define CCU4_GCST_S0PSS_Pos \ - (2UL) /*!< CCU4 GCST: S0PSS (Bit 2) */ -#define CCU4_GCST_S0PSS_Msk \ - (0x4UL) /*!< CCU4 GCST: S0PSS (Bitfield-Mask: 0x01) */ -#define CCU4_GCST_S1SS_Pos (4UL) /*!< CCU4 GCST: S1SS (Bit 4) */ -#define CCU4_GCST_S1SS_Msk \ - (0x10UL) /*!< CCU4 GCST: S1SS (Bitfield-Mask: 0x01) */ -#define CCU4_GCST_S1DSS_Pos \ - (5UL) /*!< CCU4 GCST: S1DSS (Bit 5) */ -#define CCU4_GCST_S1DSS_Msk \ - (0x20UL) /*!< CCU4 GCST: S1DSS (Bitfield-Mask: 0x01) */ -#define CCU4_GCST_S1PSS_Pos \ - (6UL) /*!< CCU4 GCST: S1PSS (Bit 6) */ -#define CCU4_GCST_S1PSS_Msk \ - (0x40UL) /*!< CCU4 GCST: S1PSS (Bitfield-Mask: 0x01) */ -#define CCU4_GCST_S2SS_Pos (8UL) /*!< CCU4 GCST: S2SS (Bit 8) */ -#define CCU4_GCST_S2SS_Msk \ - (0x100UL) /*!< CCU4 GCST: S2SS (Bitfield-Mask: 0x01) */ -#define CCU4_GCST_S2DSS_Pos \ - (9UL) /*!< CCU4 GCST: S2DSS (Bit 9) */ -#define CCU4_GCST_S2DSS_Msk \ - (0x200UL) /*!< CCU4 GCST: S2DSS (Bitfield-Mask: 0x01) */ -#define CCU4_GCST_S2PSS_Pos \ - (10UL) /*!< CCU4 GCST: S2PSS (Bit 10) */ -#define CCU4_GCST_S2PSS_Msk \ - (0x400UL) /*!< CCU4 GCST: S2PSS (Bitfield-Mask: 0x01) */ -#define CCU4_GCST_S3SS_Pos \ - (12UL) /*!< CCU4 GCST: S3SS (Bit 12) */ -#define CCU4_GCST_S3SS_Msk \ - (0x1000UL) /*!< CCU4 GCST: S3SS (Bitfield-Mask: 0x01) */ -#define CCU4_GCST_S3DSS_Pos \ - (13UL) /*!< CCU4 GCST: S3DSS (Bit 13) */ -#define CCU4_GCST_S3DSS_Msk \ - (0x2000UL) /*!< CCU4 GCST: S3DSS (Bitfield-Mask: 0x01) */ -#define CCU4_GCST_S3PSS_Pos \ - (14UL) /*!< CCU4 GCST: S3PSS (Bit 14) */ -#define CCU4_GCST_S3PSS_Msk \ - (0x4000UL) /*!< CCU4 GCST: S3PSS (Bitfield-Mask: 0x01) */ -#define CCU4_GCST_CC40ST_Pos \ - (16UL) /*!< CCU4 GCST: CC40ST (Bit 16) */ -#define CCU4_GCST_CC40ST_Msk \ - (0x10000UL) /*!< CCU4 GCST: CC40ST (Bitfield-Mask: 0x01) */ -#define CCU4_GCST_CC41ST_Pos \ - (17UL) /*!< CCU4 GCST: CC41ST (Bit 17) */ -#define CCU4_GCST_CC41ST_Msk \ - (0x20000UL) /*!< CCU4 GCST: CC41ST (Bitfield-Mask: 0x01) */ -#define CCU4_GCST_CC42ST_Pos \ - (18UL) /*!< CCU4 GCST: CC42ST (Bit 18) */ -#define CCU4_GCST_CC42ST_Msk \ - (0x40000UL) /*!< CCU4 GCST: CC42ST (Bitfield-Mask: 0x01) */ -#define CCU4_GCST_CC43ST_Pos \ - (19UL) /*!< CCU4 GCST: CC43ST (Bit 19) */ -#define CCU4_GCST_CC43ST_Msk \ - (0x80000UL) /*!< CCU4 GCST: CC43ST (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- CCU4_ECRD --------------------------------- */ -#define CCU4_ECRD_CAPV_Pos (0UL) /*!< CCU4 ECRD: CAPV (Bit 0) */ -#define CCU4_ECRD_CAPV_Msk \ - (0xffffUL) /*!< CCU4 ECRD: CAPV (Bitfield-Mask: 0xffff) */ -#define CCU4_ECRD_FPCV_Pos \ - (16UL) /*!< CCU4 ECRD: FPCV (Bit 16) */ -#define CCU4_ECRD_FPCV_Msk \ - (0xf0000UL) /*!< CCU4 ECRD: FPCV (Bitfield-Mask: 0x0f) */ -#define CCU4_ECRD_SPTR_Pos \ - (20UL) /*!< CCU4 ECRD: SPTR (Bit 20) */ -#define CCU4_ECRD_SPTR_Msk \ - (0x300000UL) /*!< CCU4 ECRD: SPTR (Bitfield-Mask: 0x03) */ -#define CCU4_ECRD_VPTR_Pos \ - (22UL) /*!< CCU4 ECRD: VPTR (Bit 22) */ -#define CCU4_ECRD_VPTR_Msk \ - (0xc00000UL) /*!< CCU4 ECRD: VPTR (Bitfield-Mask: 0x03) */ -#define CCU4_ECRD_FFL_Pos (24UL) /*!< CCU4 ECRD: FFL (Bit 24) */ -#define CCU4_ECRD_FFL_Msk \ - (0x1000000UL) /*!< CCU4 ECRD: FFL (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- CCU4_MIDR --------------------------------- */ -#define CCU4_MIDR_MODR_Pos (0UL) /*!< CCU4 MIDR: MODR (Bit 0) */ -#define CCU4_MIDR_MODR_Msk \ - (0xffUL) /*!< CCU4 MIDR: MODR (Bitfield-Mask: 0xff) */ -#define CCU4_MIDR_MODT_Pos (8UL) /*!< CCU4 MIDR: MODT (Bit 8) */ -#define CCU4_MIDR_MODT_Msk \ - (0xff00UL) /*!< CCU4 MIDR: MODT (Bitfield-Mask: 0xff) */ -#define CCU4_MIDR_MODN_Pos \ - (16UL) /*!< CCU4 MIDR: MODN (Bit 16) */ -#define CCU4_MIDR_MODN_Msk \ - (0xffff0000UL) /*!< CCU4 MIDR: MODN (Bitfield-Mask: 0xffff) */ - -/* ================================================================================ */ -/* ================ Group 'CCU4_CC4' Position & Mask ================ */ -/* ================================================================================ */ - -/* -------------------------------- CCU4_CC4_INS -------------------------------- */ -#define CCU4_CC4_INS_EV0IS_Pos \ - (0UL) /*!< CCU4_CC4 INS: EV0IS (Bit 0) */ -#define CCU4_CC4_INS_EV0IS_Msk \ - (0xfUL) /*!< CCU4_CC4 INS: EV0IS (Bitfield-Mask: 0x0f) */ -#define CCU4_CC4_INS_EV1IS_Pos \ - (4UL) /*!< CCU4_CC4 INS: EV1IS (Bit 4) */ -#define CCU4_CC4_INS_EV1IS_Msk \ - (0xf0UL) /*!< CCU4_CC4 INS: EV1IS (Bitfield-Mask: 0x0f) */ -#define CCU4_CC4_INS_EV2IS_Pos \ - (8UL) /*!< CCU4_CC4 INS: EV2IS (Bit 8) */ -#define CCU4_CC4_INS_EV2IS_Msk \ - (0xf00UL) /*!< CCU4_CC4 INS: EV2IS (Bitfield-Mask: 0x0f) */ -#define CCU4_CC4_INS_EV0EM_Pos \ - (16UL) /*!< CCU4_CC4 INS: EV0EM (Bit 16) */ -#define CCU4_CC4_INS_EV0EM_Msk \ - (0x30000UL) /*!< CCU4_CC4 INS: EV0EM (Bitfield-Mask: 0x03) */ -#define CCU4_CC4_INS_EV1EM_Pos \ - (18UL) /*!< CCU4_CC4 INS: EV1EM (Bit 18) */ -#define CCU4_CC4_INS_EV1EM_Msk \ - (0xc0000UL) /*!< CCU4_CC4 INS: EV1EM (Bitfield-Mask: 0x03) */ -#define CCU4_CC4_INS_EV2EM_Pos \ - (20UL) /*!< CCU4_CC4 INS: EV2EM (Bit 20) */ -#define CCU4_CC4_INS_EV2EM_Msk \ - (0x300000UL) /*!< CCU4_CC4 INS: EV2EM (Bitfield-Mask: 0x03) */ -#define CCU4_CC4_INS_EV0LM_Pos \ - (22UL) /*!< CCU4_CC4 INS: EV0LM (Bit 22) */ -#define CCU4_CC4_INS_EV0LM_Msk \ - (0x400000UL) /*!< CCU4_CC4 INS: EV0LM (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_INS_EV1LM_Pos \ - (23UL) /*!< CCU4_CC4 INS: EV1LM (Bit 23) */ -#define CCU4_CC4_INS_EV1LM_Msk \ - (0x800000UL) /*!< CCU4_CC4 INS: EV1LM (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_INS_EV2LM_Pos \ - (24UL) /*!< CCU4_CC4 INS: EV2LM (Bit 24) */ -#define CCU4_CC4_INS_EV2LM_Msk \ - (0x1000000UL) /*!< CCU4_CC4 INS: EV2LM (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_INS_LPF0M_Pos \ - (25UL) /*!< CCU4_CC4 INS: LPF0M (Bit 25) */ -#define CCU4_CC4_INS_LPF0M_Msk \ - (0x6000000UL) /*!< CCU4_CC4 INS: LPF0M (Bitfield-Mask: 0x03) */ -#define CCU4_CC4_INS_LPF1M_Pos \ - (27UL) /*!< CCU4_CC4 INS: LPF1M (Bit 27) */ -#define CCU4_CC4_INS_LPF1M_Msk \ - (0x18000000UL) /*!< CCU4_CC4 INS: LPF1M (Bitfield-Mask: 0x03) */ -#define CCU4_CC4_INS_LPF2M_Pos \ - (29UL) /*!< CCU4_CC4 INS: LPF2M (Bit 29) */ -#define CCU4_CC4_INS_LPF2M_Msk \ - (0x60000000UL) /*!< CCU4_CC4 INS: LPF2M (Bitfield-Mask: 0x03) */ - -/* -------------------------------- CCU4_CC4_CMC -------------------------------- */ -#define CCU4_CC4_CMC_STRTS_Pos \ - (0UL) /*!< CCU4_CC4 CMC: STRTS (Bit 0) */ -#define CCU4_CC4_CMC_STRTS_Msk \ - (0x3UL) /*!< CCU4_CC4 CMC: STRTS (Bitfield-Mask: 0x03) */ -#define CCU4_CC4_CMC_ENDS_Pos \ - (2UL) /*!< CCU4_CC4 CMC: ENDS (Bit 2) */ -#define CCU4_CC4_CMC_ENDS_Msk \ - (0xcUL) /*!< CCU4_CC4 CMC: ENDS (Bitfield-Mask: 0x03) */ -#define CCU4_CC4_CMC_CAP0S_Pos \ - (4UL) /*!< CCU4_CC4 CMC: CAP0S (Bit 4) */ -#define CCU4_CC4_CMC_CAP0S_Msk \ - (0x30UL) /*!< CCU4_CC4 CMC: CAP0S (Bitfield-Mask: 0x03) */ -#define CCU4_CC4_CMC_CAP1S_Pos \ - (6UL) /*!< CCU4_CC4 CMC: CAP1S (Bit 6) */ -#define CCU4_CC4_CMC_CAP1S_Msk \ - (0xc0UL) /*!< CCU4_CC4 CMC: CAP1S (Bitfield-Mask: 0x03) */ -#define CCU4_CC4_CMC_GATES_Pos \ - (8UL) /*!< CCU4_CC4 CMC: GATES (Bit 8) */ -#define CCU4_CC4_CMC_GATES_Msk \ - (0x300UL) /*!< CCU4_CC4 CMC: GATES (Bitfield-Mask: 0x03) */ -#define CCU4_CC4_CMC_UDS_Pos \ - (10UL) /*!< CCU4_CC4 CMC: UDS (Bit 10) */ -#define CCU4_CC4_CMC_UDS_Msk \ - (0xc00UL) /*!< CCU4_CC4 CMC: UDS (Bitfield-Mask: 0x03) */ -#define CCU4_CC4_CMC_LDS_Pos \ - (12UL) /*!< CCU4_CC4 CMC: LDS (Bit 12) */ -#define CCU4_CC4_CMC_LDS_Msk \ - (0x3000UL) /*!< CCU4_CC4 CMC: LDS (Bitfield-Mask: 0x03) */ -#define CCU4_CC4_CMC_CNTS_Pos \ - (14UL) /*!< CCU4_CC4 CMC: CNTS (Bit 14) */ -#define CCU4_CC4_CMC_CNTS_Msk \ - (0xc000UL) /*!< CCU4_CC4 CMC: CNTS (Bitfield-Mask: 0x03) */ -#define CCU4_CC4_CMC_OFS_Pos \ - (16UL) /*!< CCU4_CC4 CMC: OFS (Bit 16) */ -#define CCU4_CC4_CMC_OFS_Msk \ - (0x10000UL) /*!< CCU4_CC4 CMC: OFS (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_CMC_TS_Pos \ - (17UL) /*!< CCU4_CC4 CMC: TS (Bit 17) */ -#define CCU4_CC4_CMC_TS_Msk \ - (0x20000UL) /*!< CCU4_CC4 CMC: TS (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_CMC_MOS_Pos \ - (18UL) /*!< CCU4_CC4 CMC: MOS (Bit 18) */ -#define CCU4_CC4_CMC_MOS_Msk \ - (0xc0000UL) /*!< CCU4_CC4 CMC: MOS (Bitfield-Mask: 0x03) */ -#define CCU4_CC4_CMC_TCE_Pos \ - (20UL) /*!< CCU4_CC4 CMC: TCE (Bit 20) */ -#define CCU4_CC4_CMC_TCE_Msk \ - (0x100000UL) /*!< CCU4_CC4 CMC: TCE (Bitfield-Mask: 0x01) */ - -/* -------------------------------- CCU4_CC4_TCST ------------------------------- */ -#define CCU4_CC4_TCST_TRB_Pos \ - (0UL) /*!< CCU4_CC4 TCST: TRB (Bit 0) */ -#define CCU4_CC4_TCST_TRB_Msk \ - (0x1UL) /*!< CCU4_CC4 TCST: TRB (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_TCST_CDIR_Pos \ - (1UL) /*!< CCU4_CC4 TCST: CDIR (Bit 1) */ -#define CCU4_CC4_TCST_CDIR_Msk \ - (0x2UL) /*!< CCU4_CC4 TCST: CDIR (Bitfield-Mask: 0x01) */ - -/* ------------------------------- CCU4_CC4_TCSET ------------------------------- */ -#define CCU4_CC4_TCSET_TRBS_Pos \ - (0UL) /*!< CCU4_CC4 TCSET: TRBS (Bit 0) */ -#define CCU4_CC4_TCSET_TRBS_Msk \ - (0x1UL) /*!< CCU4_CC4 TCSET: TRBS (Bitfield-Mask: 0x01) */ - -/* ------------------------------- CCU4_CC4_TCCLR ------------------------------- */ -#define CCU4_CC4_TCCLR_TRBC_Pos \ - (0UL) /*!< CCU4_CC4 TCCLR: TRBC (Bit 0) */ -#define CCU4_CC4_TCCLR_TRBC_Msk \ - (0x1UL) /*!< CCU4_CC4 TCCLR: TRBC (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_TCCLR_TCC_Pos \ - (1UL) /*!< CCU4_CC4 TCCLR: TCC (Bit 1) */ -#define CCU4_CC4_TCCLR_TCC_Msk \ - (0x2UL) /*!< CCU4_CC4 TCCLR: TCC (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_TCCLR_DITC_Pos \ - (2UL) /*!< CCU4_CC4 TCCLR: DITC (Bit 2) */ -#define CCU4_CC4_TCCLR_DITC_Msk \ - (0x4UL) /*!< CCU4_CC4 TCCLR: DITC (Bitfield-Mask: 0x01) */ - -/* --------------------------------- CCU4_CC4_TC -------------------------------- */ -#define CCU4_CC4_TC_TCM_Pos \ - (0UL) /*!< CCU4_CC4 TC: TCM (Bit 0) */ -#define CCU4_CC4_TC_TCM_Msk \ - (0x1UL) /*!< CCU4_CC4 TC: TCM (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_TC_TSSM_Pos \ - (1UL) /*!< CCU4_CC4 TC: TSSM (Bit 1) */ -#define CCU4_CC4_TC_TSSM_Msk \ - (0x2UL) /*!< CCU4_CC4 TC: TSSM (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_TC_CLST_Pos \ - (2UL) /*!< CCU4_CC4 TC: CLST (Bit 2) */ -#define CCU4_CC4_TC_CLST_Msk \ - (0x4UL) /*!< CCU4_CC4 TC: CLST (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_TC_CMOD_Pos \ - (3UL) /*!< CCU4_CC4 TC: CMOD (Bit 3) */ -#define CCU4_CC4_TC_CMOD_Msk \ - (0x8UL) /*!< CCU4_CC4 TC: CMOD (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_TC_ECM_Pos \ - (4UL) /*!< CCU4_CC4 TC: ECM (Bit 4) */ -#define CCU4_CC4_TC_ECM_Msk \ - (0x10UL) /*!< CCU4_CC4 TC: ECM (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_TC_CAPC_Pos \ - (5UL) /*!< CCU4_CC4 TC: CAPC (Bit 5) */ -#define CCU4_CC4_TC_CAPC_Msk \ - (0x60UL) /*!< CCU4_CC4 TC: CAPC (Bitfield-Mask: 0x03) */ -#define CCU4_CC4_TC_ENDM_Pos \ - (8UL) /*!< CCU4_CC4 TC: ENDM (Bit 8) */ -#define CCU4_CC4_TC_ENDM_Msk \ - (0x300UL) /*!< CCU4_CC4 TC: ENDM (Bitfield-Mask: 0x03) */ -#define CCU4_CC4_TC_STRM_Pos \ - (10UL) /*!< CCU4_CC4 TC: STRM (Bit 10) */ -#define CCU4_CC4_TC_STRM_Msk \ - (0x400UL) /*!< CCU4_CC4 TC: STRM (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_TC_SCE_Pos \ - (11UL) /*!< CCU4_CC4 TC: SCE (Bit 11) */ -#define CCU4_CC4_TC_SCE_Msk \ - (0x800UL) /*!< CCU4_CC4 TC: SCE (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_TC_CCS_Pos \ - (12UL) /*!< CCU4_CC4 TC: CCS (Bit 12) */ -#define CCU4_CC4_TC_CCS_Msk \ - (0x1000UL) /*!< CCU4_CC4 TC: CCS (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_TC_DITHE_Pos \ - (13UL) /*!< CCU4_CC4 TC: DITHE (Bit 13) */ -#define CCU4_CC4_TC_DITHE_Msk \ - (0x6000UL) /*!< CCU4_CC4 TC: DITHE (Bitfield-Mask: 0x03) */ -#define CCU4_CC4_TC_DIM_Pos \ - (15UL) /*!< CCU4_CC4 TC: DIM (Bit 15) */ -#define CCU4_CC4_TC_DIM_Msk \ - (0x8000UL) /*!< CCU4_CC4 TC: DIM (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_TC_FPE_Pos \ - (16UL) /*!< CCU4_CC4 TC: FPE (Bit 16) */ -#define CCU4_CC4_TC_FPE_Msk \ - (0x10000UL) /*!< CCU4_CC4 TC: FPE (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_TC_TRAPE_Pos \ - (17UL) /*!< CCU4_CC4 TC: TRAPE (Bit 17) */ -#define CCU4_CC4_TC_TRAPE_Msk \ - (0x20000UL) /*!< CCU4_CC4 TC: TRAPE (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_TC_TRPSE_Pos \ - (21UL) /*!< CCU4_CC4 TC: TRPSE (Bit 21) */ -#define CCU4_CC4_TC_TRPSE_Msk \ - (0x200000UL) /*!< CCU4_CC4 TC: TRPSE (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_TC_TRPSW_Pos \ - (22UL) /*!< CCU4_CC4 TC: TRPSW (Bit 22) */ -#define CCU4_CC4_TC_TRPSW_Msk \ - (0x400000UL) /*!< CCU4_CC4 TC: TRPSW (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_TC_EMS_Pos \ - (23UL) /*!< CCU4_CC4 TC: EMS (Bit 23) */ -#define CCU4_CC4_TC_EMS_Msk \ - (0x800000UL) /*!< CCU4_CC4 TC: EMS (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_TC_EMT_Pos \ - (24UL) /*!< CCU4_CC4 TC: EMT (Bit 24) */ -#define CCU4_CC4_TC_EMT_Msk \ - (0x1000000UL) /*!< CCU4_CC4 TC: EMT (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_TC_MCME_Pos \ - (25UL) /*!< CCU4_CC4 TC: MCME (Bit 25) */ -#define CCU4_CC4_TC_MCME_Msk \ - (0x2000000UL) /*!< CCU4_CC4 TC: MCME (Bitfield-Mask: 0x01) */ - -/* -------------------------------- CCU4_CC4_PSL -------------------------------- */ -#define CCU4_CC4_PSL_PSL_Pos \ - (0UL) /*!< CCU4_CC4 PSL: PSL (Bit 0) */ -#define CCU4_CC4_PSL_PSL_Msk \ - (0x1UL) /*!< CCU4_CC4 PSL: PSL (Bitfield-Mask: 0x01) */ - -/* -------------------------------- CCU4_CC4_DIT -------------------------------- */ -#define CCU4_CC4_DIT_DCV_Pos \ - (0UL) /*!< CCU4_CC4 DIT: DCV (Bit 0) */ -#define CCU4_CC4_DIT_DCV_Msk \ - (0xfUL) /*!< CCU4_CC4 DIT: DCV (Bitfield-Mask: 0x0f) */ -#define CCU4_CC4_DIT_DCNT_Pos \ - (8UL) /*!< CCU4_CC4 DIT: DCNT (Bit 8) */ -#define CCU4_CC4_DIT_DCNT_Msk \ - (0xf00UL) /*!< CCU4_CC4 DIT: DCNT (Bitfield-Mask: 0x0f) */ - -/* -------------------------------- CCU4_CC4_DITS ------------------------------- */ -#define CCU4_CC4_DITS_DCVS_Pos \ - (0UL) /*!< CCU4_CC4 DITS: DCVS (Bit 0) */ -#define CCU4_CC4_DITS_DCVS_Msk \ - (0xfUL) /*!< CCU4_CC4 DITS: DCVS (Bitfield-Mask: 0x0f) */ - -/* -------------------------------- CCU4_CC4_PSC -------------------------------- */ -#define CCU4_CC4_PSC_PSIV_Pos \ - (0UL) /*!< CCU4_CC4 PSC: PSIV (Bit 0) */ -#define CCU4_CC4_PSC_PSIV_Msk \ - (0xfUL) /*!< CCU4_CC4 PSC: PSIV (Bitfield-Mask: 0x0f) */ - -/* -------------------------------- CCU4_CC4_FPC -------------------------------- */ -#define CCU4_CC4_FPC_PCMP_Pos \ - (0UL) /*!< CCU4_CC4 FPC: PCMP (Bit 0) */ -#define CCU4_CC4_FPC_PCMP_Msk \ - (0xfUL) /*!< CCU4_CC4 FPC: PCMP (Bitfield-Mask: 0x0f) */ -#define CCU4_CC4_FPC_PVAL_Pos \ - (8UL) /*!< CCU4_CC4 FPC: PVAL (Bit 8) */ -#define CCU4_CC4_FPC_PVAL_Msk \ - (0xf00UL) /*!< CCU4_CC4 FPC: PVAL (Bitfield-Mask: 0x0f) */ - -/* -------------------------------- CCU4_CC4_FPCS ------------------------------- */ -#define CCU4_CC4_FPCS_PCMP_Pos \ - (0UL) /*!< CCU4_CC4 FPCS: PCMP (Bit 0) */ -#define CCU4_CC4_FPCS_PCMP_Msk \ - (0xfUL) /*!< CCU4_CC4 FPCS: PCMP (Bitfield-Mask: 0x0f) */ - -/* --------------------------------- CCU4_CC4_PR -------------------------------- */ -#define CCU4_CC4_PR_PR_Pos (0UL) /*!< CCU4_CC4 PR: PR (Bit 0) */ -#define CCU4_CC4_PR_PR_Msk \ - (0xffffUL) /*!< CCU4_CC4 PR: PR (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- CCU4_CC4_PRS -------------------------------- */ -#define CCU4_CC4_PRS_PRS_Pos \ - (0UL) /*!< CCU4_CC4 PRS: PRS (Bit 0) */ -#define CCU4_CC4_PRS_PRS_Msk \ - (0xffffUL) /*!< CCU4_CC4 PRS: PRS (Bitfield-Mask: 0xffff) */ - -/* --------------------------------- CCU4_CC4_CR -------------------------------- */ -#define CCU4_CC4_CR_CR_Pos (0UL) /*!< CCU4_CC4 CR: CR (Bit 0) */ -#define CCU4_CC4_CR_CR_Msk \ - (0xffffUL) /*!< CCU4_CC4 CR: CR (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- CCU4_CC4_CRS -------------------------------- */ -#define CCU4_CC4_CRS_CRS_Pos \ - (0UL) /*!< CCU4_CC4 CRS: CRS (Bit 0) */ -#define CCU4_CC4_CRS_CRS_Msk \ - (0xffffUL) /*!< CCU4_CC4 CRS: CRS (Bitfield-Mask: 0xffff) */ - -/* ------------------------------- CCU4_CC4_TIMER ------------------------------- */ -#define CCU4_CC4_TIMER_TVAL_Pos \ - (0UL) /*!< CCU4_CC4 TIMER: TVAL (Bit 0) */ -#define CCU4_CC4_TIMER_TVAL_Msk \ - (0xffffUL) /*!< CCU4_CC4 TIMER: TVAL (Bitfield-Mask: 0xffff) */ - -/* --------------------------------- CCU4_CC4_CV -------------------------------- */ -#define CCU4_CC4_CV_CAPTV_Pos \ - (0UL) /*!< CCU4_CC4 CV: CAPTV (Bit 0) */ -#define CCU4_CC4_CV_CAPTV_Msk \ - (0xffffUL) /*!< CCU4_CC4 CV: CAPTV (Bitfield-Mask: 0xffff) */ -#define CCU4_CC4_CV_FPCV_Pos \ - (16UL) /*!< CCU4_CC4 CV: FPCV (Bit 16) */ -#define CCU4_CC4_CV_FPCV_Msk \ - (0xf0000UL) /*!< CCU4_CC4 CV: FPCV (Bitfield-Mask: 0x0f) */ -#define CCU4_CC4_CV_FFL_Pos \ - (20UL) /*!< CCU4_CC4 CV: FFL (Bit 20) */ -#define CCU4_CC4_CV_FFL_Msk \ - (0x100000UL) /*!< CCU4_CC4 CV: FFL (Bitfield-Mask: 0x01) */ - -/* -------------------------------- CCU4_CC4_INTS ------------------------------- */ -#define CCU4_CC4_INTS_PMUS_Pos \ - (0UL) /*!< CCU4_CC4 INTS: PMUS (Bit 0) */ -#define CCU4_CC4_INTS_PMUS_Msk \ - (0x1UL) /*!< CCU4_CC4 INTS: PMUS (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_INTS_OMDS_Pos \ - (1UL) /*!< CCU4_CC4 INTS: OMDS (Bit 1) */ -#define CCU4_CC4_INTS_OMDS_Msk \ - (0x2UL) /*!< CCU4_CC4 INTS: OMDS (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_INTS_CMUS_Pos \ - (2UL) /*!< CCU4_CC4 INTS: CMUS (Bit 2) */ -#define CCU4_CC4_INTS_CMUS_Msk \ - (0x4UL) /*!< CCU4_CC4 INTS: CMUS (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_INTS_CMDS_Pos \ - (3UL) /*!< CCU4_CC4 INTS: CMDS (Bit 3) */ -#define CCU4_CC4_INTS_CMDS_Msk \ - (0x8UL) /*!< CCU4_CC4 INTS: CMDS (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_INTS_E0AS_Pos \ - (8UL) /*!< CCU4_CC4 INTS: E0AS (Bit 8) */ -#define CCU4_CC4_INTS_E0AS_Msk \ - (0x100UL) /*!< CCU4_CC4 INTS: E0AS (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_INTS_E1AS_Pos \ - (9UL) /*!< CCU4_CC4 INTS: E1AS (Bit 9) */ -#define CCU4_CC4_INTS_E1AS_Msk \ - (0x200UL) /*!< CCU4_CC4 INTS: E1AS (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_INTS_E2AS_Pos \ - (10UL) /*!< CCU4_CC4 INTS: E2AS (Bit 10) */ -#define CCU4_CC4_INTS_E2AS_Msk \ - (0x400UL) /*!< CCU4_CC4 INTS: E2AS (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_INTS_TRPF_Pos \ - (11UL) /*!< CCU4_CC4 INTS: TRPF (Bit 11) */ -#define CCU4_CC4_INTS_TRPF_Msk \ - (0x800UL) /*!< CCU4_CC4 INTS: TRPF (Bitfield-Mask: 0x01) */ - -/* -------------------------------- CCU4_CC4_INTE ------------------------------- */ -#define CCU4_CC4_INTE_PME_Pos \ - (0UL) /*!< CCU4_CC4 INTE: PME (Bit 0) */ -#define CCU4_CC4_INTE_PME_Msk \ - (0x1UL) /*!< CCU4_CC4 INTE: PME (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_INTE_OME_Pos \ - (1UL) /*!< CCU4_CC4 INTE: OME (Bit 1) */ -#define CCU4_CC4_INTE_OME_Msk \ - (0x2UL) /*!< CCU4_CC4 INTE: OME (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_INTE_CMUE_Pos \ - (2UL) /*!< CCU4_CC4 INTE: CMUE (Bit 2) */ -#define CCU4_CC4_INTE_CMUE_Msk \ - (0x4UL) /*!< CCU4_CC4 INTE: CMUE (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_INTE_CMDE_Pos \ - (3UL) /*!< CCU4_CC4 INTE: CMDE (Bit 3) */ -#define CCU4_CC4_INTE_CMDE_Msk \ - (0x8UL) /*!< CCU4_CC4 INTE: CMDE (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_INTE_E0AE_Pos \ - (8UL) /*!< CCU4_CC4 INTE: E0AE (Bit 8) */ -#define CCU4_CC4_INTE_E0AE_Msk \ - (0x100UL) /*!< CCU4_CC4 INTE: E0AE (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_INTE_E1AE_Pos \ - (9UL) /*!< CCU4_CC4 INTE: E1AE (Bit 9) */ -#define CCU4_CC4_INTE_E1AE_Msk \ - (0x200UL) /*!< CCU4_CC4 INTE: E1AE (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_INTE_E2AE_Pos \ - (10UL) /*!< CCU4_CC4 INTE: E2AE (Bit 10) */ -#define CCU4_CC4_INTE_E2AE_Msk \ - (0x400UL) /*!< CCU4_CC4 INTE: E2AE (Bitfield-Mask: 0x01) */ - -/* -------------------------------- CCU4_CC4_SRS -------------------------------- */ -#define CCU4_CC4_SRS_POSR_Pos \ - (0UL) /*!< CCU4_CC4 SRS: POSR (Bit 0) */ -#define CCU4_CC4_SRS_POSR_Msk \ - (0x3UL) /*!< CCU4_CC4 SRS: POSR (Bitfield-Mask: 0x03) */ -#define CCU4_CC4_SRS_CMSR_Pos \ - (2UL) /*!< CCU4_CC4 SRS: CMSR (Bit 2) */ -#define CCU4_CC4_SRS_CMSR_Msk \ - (0xcUL) /*!< CCU4_CC4 SRS: CMSR (Bitfield-Mask: 0x03) */ -#define CCU4_CC4_SRS_E0SR_Pos \ - (8UL) /*!< CCU4_CC4 SRS: E0SR (Bit 8) */ -#define CCU4_CC4_SRS_E0SR_Msk \ - (0x300UL) /*!< CCU4_CC4 SRS: E0SR (Bitfield-Mask: 0x03) */ -#define CCU4_CC4_SRS_E1SR_Pos \ - (10UL) /*!< CCU4_CC4 SRS: E1SR (Bit 10) */ -#define CCU4_CC4_SRS_E1SR_Msk \ - (0xc00UL) /*!< CCU4_CC4 SRS: E1SR (Bitfield-Mask: 0x03) */ -#define CCU4_CC4_SRS_E2SR_Pos \ - (12UL) /*!< CCU4_CC4 SRS: E2SR (Bit 12) */ -#define CCU4_CC4_SRS_E2SR_Msk \ - (0x3000UL) /*!< CCU4_CC4 SRS: E2SR (Bitfield-Mask: 0x03) */ - -/* -------------------------------- CCU4_CC4_SWS -------------------------------- */ -#define CCU4_CC4_SWS_SPM_Pos \ - (0UL) /*!< CCU4_CC4 SWS: SPM (Bit 0) */ -#define CCU4_CC4_SWS_SPM_Msk \ - (0x1UL) /*!< CCU4_CC4 SWS: SPM (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_SWS_SOM_Pos \ - (1UL) /*!< CCU4_CC4 SWS: SOM (Bit 1) */ -#define CCU4_CC4_SWS_SOM_Msk \ - (0x2UL) /*!< CCU4_CC4 SWS: SOM (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_SWS_SCMU_Pos \ - (2UL) /*!< CCU4_CC4 SWS: SCMU (Bit 2) */ -#define CCU4_CC4_SWS_SCMU_Msk \ - (0x4UL) /*!< CCU4_CC4 SWS: SCMU (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_SWS_SCMD_Pos \ - (3UL) /*!< CCU4_CC4 SWS: SCMD (Bit 3) */ -#define CCU4_CC4_SWS_SCMD_Msk \ - (0x8UL) /*!< CCU4_CC4 SWS: SCMD (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_SWS_SE0A_Pos \ - (8UL) /*!< CCU4_CC4 SWS: SE0A (Bit 8) */ -#define CCU4_CC4_SWS_SE0A_Msk \ - (0x100UL) /*!< CCU4_CC4 SWS: SE0A (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_SWS_SE1A_Pos \ - (9UL) /*!< CCU4_CC4 SWS: SE1A (Bit 9) */ -#define CCU4_CC4_SWS_SE1A_Msk \ - (0x200UL) /*!< CCU4_CC4 SWS: SE1A (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_SWS_SE2A_Pos \ - (10UL) /*!< CCU4_CC4 SWS: SE2A (Bit 10) */ -#define CCU4_CC4_SWS_SE2A_Msk \ - (0x400UL) /*!< CCU4_CC4 SWS: SE2A (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_SWS_STRPF_Pos \ - (11UL) /*!< CCU4_CC4 SWS: STRPF (Bit 11) */ -#define CCU4_CC4_SWS_STRPF_Msk \ - (0x800UL) /*!< CCU4_CC4 SWS: STRPF (Bitfield-Mask: 0x01) */ - -/* -------------------------------- CCU4_CC4_SWR -------------------------------- */ -#define CCU4_CC4_SWR_RPM_Pos \ - (0UL) /*!< CCU4_CC4 SWR: RPM (Bit 0) */ -#define CCU4_CC4_SWR_RPM_Msk \ - (0x1UL) /*!< CCU4_CC4 SWR: RPM (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_SWR_ROM_Pos \ - (1UL) /*!< CCU4_CC4 SWR: ROM (Bit 1) */ -#define CCU4_CC4_SWR_ROM_Msk \ - (0x2UL) /*!< CCU4_CC4 SWR: ROM (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_SWR_RCMU_Pos \ - (2UL) /*!< CCU4_CC4 SWR: RCMU (Bit 2) */ -#define CCU4_CC4_SWR_RCMU_Msk \ - (0x4UL) /*!< CCU4_CC4 SWR: RCMU (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_SWR_RCMD_Pos \ - (3UL) /*!< CCU4_CC4 SWR: RCMD (Bit 3) */ -#define CCU4_CC4_SWR_RCMD_Msk \ - (0x8UL) /*!< CCU4_CC4 SWR: RCMD (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_SWR_RE0A_Pos \ - (8UL) /*!< CCU4_CC4 SWR: RE0A (Bit 8) */ -#define CCU4_CC4_SWR_RE0A_Msk \ - (0x100UL) /*!< CCU4_CC4 SWR: RE0A (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_SWR_RE1A_Pos \ - (9UL) /*!< CCU4_CC4 SWR: RE1A (Bit 9) */ -#define CCU4_CC4_SWR_RE1A_Msk \ - (0x200UL) /*!< CCU4_CC4 SWR: RE1A (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_SWR_RE2A_Pos \ - (10UL) /*!< CCU4_CC4 SWR: RE2A (Bit 10) */ -#define CCU4_CC4_SWR_RE2A_Msk \ - (0x400UL) /*!< CCU4_CC4 SWR: RE2A (Bitfield-Mask: 0x01) */ -#define CCU4_CC4_SWR_RTRPF_Pos \ - (11UL) /*!< CCU4_CC4 SWR: RTRPF (Bit 11) */ -#define CCU4_CC4_SWR_RTRPF_Msk \ - (0x800UL) /*!< CCU4_CC4 SWR: RTRPF (Bitfield-Mask: 0x01) */ - -/* ================================================================================ */ -/* ================ Group 'CCU8' Position & Mask ================ */ -/* ================================================================================ */ - -/* --------------------------------- CCU8_GCTRL --------------------------------- */ -#define CCU8_GCTRL_PRBC_Pos \ - (0UL) /*!< CCU8 GCTRL: PRBC (Bit 0) */ -#define CCU8_GCTRL_PRBC_Msk \ - (0x7UL) /*!< CCU8 GCTRL: PRBC (Bitfield-Mask: 0x07) */ -#define CCU8_GCTRL_PCIS_Pos \ - (4UL) /*!< CCU8 GCTRL: PCIS (Bit 4) */ -#define CCU8_GCTRL_PCIS_Msk \ - (0x30UL) /*!< CCU8 GCTRL: PCIS (Bitfield-Mask: 0x03) */ -#define CCU8_GCTRL_SUSCFG_Pos \ - (8UL) /*!< CCU8 GCTRL: SUSCFG (Bit 8) */ -#define CCU8_GCTRL_SUSCFG_Msk \ - (0x300UL) /*!< CCU8 GCTRL: SUSCFG (Bitfield-Mask: 0x03) */ -#define CCU8_GCTRL_MSE0_Pos \ - (10UL) /*!< CCU8 GCTRL: MSE0 (Bit 10) */ -#define CCU8_GCTRL_MSE0_Msk \ - (0x400UL) /*!< CCU8 GCTRL: MSE0 (Bitfield-Mask: 0x01) */ -#define CCU8_GCTRL_MSE1_Pos \ - (11UL) /*!< CCU8 GCTRL: MSE1 (Bit 11) */ -#define CCU8_GCTRL_MSE1_Msk \ - (0x800UL) /*!< CCU8 GCTRL: MSE1 (Bitfield-Mask: 0x01) */ -#define CCU8_GCTRL_MSE2_Pos \ - (12UL) /*!< CCU8 GCTRL: MSE2 (Bit 12) */ -#define CCU8_GCTRL_MSE2_Msk \ - (0x1000UL) /*!< CCU8 GCTRL: MSE2 (Bitfield-Mask: 0x01) */ -#define CCU8_GCTRL_MSE3_Pos \ - (13UL) /*!< CCU8 GCTRL: MSE3 (Bit 13) */ -#define CCU8_GCTRL_MSE3_Msk \ - (0x2000UL) /*!< CCU8 GCTRL: MSE3 (Bitfield-Mask: 0x01) */ -#define CCU8_GCTRL_MSDE_Pos \ - (14UL) /*!< CCU8 GCTRL: MSDE (Bit 14) */ -#define CCU8_GCTRL_MSDE_Msk \ - (0xc000UL) /*!< CCU8 GCTRL: MSDE (Bitfield-Mask: 0x03) */ - -/* --------------------------------- CCU8_GSTAT --------------------------------- */ -#define CCU8_GSTAT_S0I_Pos (0UL) /*!< CCU8 GSTAT: S0I (Bit 0) */ -#define CCU8_GSTAT_S0I_Msk \ - (0x1UL) /*!< CCU8 GSTAT: S0I (Bitfield-Mask: 0x01) */ -#define CCU8_GSTAT_S1I_Pos (1UL) /*!< CCU8 GSTAT: S1I (Bit 1) */ -#define CCU8_GSTAT_S1I_Msk \ - (0x2UL) /*!< CCU8 GSTAT: S1I (Bitfield-Mask: 0x01) */ -#define CCU8_GSTAT_S2I_Pos (2UL) /*!< CCU8 GSTAT: S2I (Bit 2) */ -#define CCU8_GSTAT_S2I_Msk \ - (0x4UL) /*!< CCU8 GSTAT: S2I (Bitfield-Mask: 0x01) */ -#define CCU8_GSTAT_S3I_Pos (3UL) /*!< CCU8 GSTAT: S3I (Bit 3) */ -#define CCU8_GSTAT_S3I_Msk \ - (0x8UL) /*!< CCU8 GSTAT: S3I (Bitfield-Mask: 0x01) */ -#define CCU8_GSTAT_PRB_Pos (8UL) /*!< CCU8 GSTAT: PRB (Bit 8) */ -#define CCU8_GSTAT_PRB_Msk \ - (0x100UL) /*!< CCU8 GSTAT: PRB (Bitfield-Mask: 0x01) */ -#define CCU8_GSTAT_PCRB_Pos \ - (10UL) /*!< CCU8 GSTAT: PCRB (Bit 10) */ -#define CCU8_GSTAT_PCRB_Msk \ - (0x400UL) /*!< CCU8 GSTAT: PCRB (Bitfield-Mask: 0x01) */ - -/* --------------------------------- CCU8_GIDLS --------------------------------- */ -#define CCU8_GIDLS_SS0I_Pos \ - (0UL) /*!< CCU8 GIDLS: SS0I (Bit 0) */ -#define CCU8_GIDLS_SS0I_Msk \ - (0x1UL) /*!< CCU8 GIDLS: SS0I (Bitfield-Mask: 0x01) */ -#define CCU8_GIDLS_SS1I_Pos \ - (1UL) /*!< CCU8 GIDLS: SS1I (Bit 1) */ -#define CCU8_GIDLS_SS1I_Msk \ - (0x2UL) /*!< CCU8 GIDLS: SS1I (Bitfield-Mask: 0x01) */ -#define CCU8_GIDLS_SS2I_Pos \ - (2UL) /*!< CCU8 GIDLS: SS2I (Bit 2) */ -#define CCU8_GIDLS_SS2I_Msk \ - (0x4UL) /*!< CCU8 GIDLS: SS2I (Bitfield-Mask: 0x01) */ -#define CCU8_GIDLS_SS3I_Pos \ - (3UL) /*!< CCU8 GIDLS: SS3I (Bit 3) */ -#define CCU8_GIDLS_SS3I_Msk \ - (0x8UL) /*!< CCU8 GIDLS: SS3I (Bitfield-Mask: 0x01) */ -#define CCU8_GIDLS_CPRB_Pos \ - (8UL) /*!< CCU8 GIDLS: CPRB (Bit 8) */ -#define CCU8_GIDLS_CPRB_Msk \ - (0x100UL) /*!< CCU8 GIDLS: CPRB (Bitfield-Mask: 0x01) */ -#define CCU8_GIDLS_PSIC_Pos \ - (9UL) /*!< CCU8 GIDLS: PSIC (Bit 9) */ -#define CCU8_GIDLS_PSIC_Msk \ - (0x200UL) /*!< CCU8 GIDLS: PSIC (Bitfield-Mask: 0x01) */ -#define CCU8_GIDLS_CPCH_Pos \ - (10UL) /*!< CCU8 GIDLS: CPCH (Bit 10) */ -#define CCU8_GIDLS_CPCH_Msk \ - (0x400UL) /*!< CCU8 GIDLS: CPCH (Bitfield-Mask: 0x01) */ - -/* --------------------------------- CCU8_GIDLC --------------------------------- */ -#define CCU8_GIDLC_CS0I_Pos \ - (0UL) /*!< CCU8 GIDLC: CS0I (Bit 0) */ -#define CCU8_GIDLC_CS0I_Msk \ - (0x1UL) /*!< CCU8 GIDLC: CS0I (Bitfield-Mask: 0x01) */ -#define CCU8_GIDLC_CS1I_Pos \ - (1UL) /*!< CCU8 GIDLC: CS1I (Bit 1) */ -#define CCU8_GIDLC_CS1I_Msk \ - (0x2UL) /*!< CCU8 GIDLC: CS1I (Bitfield-Mask: 0x01) */ -#define CCU8_GIDLC_CS2I_Pos \ - (2UL) /*!< CCU8 GIDLC: CS2I (Bit 2) */ -#define CCU8_GIDLC_CS2I_Msk \ - (0x4UL) /*!< CCU8 GIDLC: CS2I (Bitfield-Mask: 0x01) */ -#define CCU8_GIDLC_CS3I_Pos \ - (3UL) /*!< CCU8 GIDLC: CS3I (Bit 3) */ -#define CCU8_GIDLC_CS3I_Msk \ - (0x8UL) /*!< CCU8 GIDLC: CS3I (Bitfield-Mask: 0x01) */ -#define CCU8_GIDLC_SPRB_Pos \ - (8UL) /*!< CCU8 GIDLC: SPRB (Bit 8) */ -#define CCU8_GIDLC_SPRB_Msk \ - (0x100UL) /*!< CCU8 GIDLC: SPRB (Bitfield-Mask: 0x01) */ -#define CCU8_GIDLC_SPCH_Pos \ - (10UL) /*!< CCU8 GIDLC: SPCH (Bit 10) */ -#define CCU8_GIDLC_SPCH_Msk \ - (0x400UL) /*!< CCU8 GIDLC: SPCH (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- CCU8_GCSS --------------------------------- */ -#define CCU8_GCSS_S0SE_Pos (0UL) /*!< CCU8 GCSS: S0SE (Bit 0) */ -#define CCU8_GCSS_S0SE_Msk \ - (0x1UL) /*!< CCU8 GCSS: S0SE (Bitfield-Mask: 0x01) */ -#define CCU8_GCSS_S0DSE_Pos \ - (1UL) /*!< CCU8 GCSS: S0DSE (Bit 1) */ -#define CCU8_GCSS_S0DSE_Msk \ - (0x2UL) /*!< CCU8 GCSS: S0DSE (Bitfield-Mask: 0x01) */ -#define CCU8_GCSS_S0PSE_Pos \ - (2UL) /*!< CCU8 GCSS: S0PSE (Bit 2) */ -#define CCU8_GCSS_S0PSE_Msk \ - (0x4UL) /*!< CCU8 GCSS: S0PSE (Bitfield-Mask: 0x01) */ -#define CCU8_GCSS_S1SE_Pos (4UL) /*!< CCU8 GCSS: S1SE (Bit 4) */ -#define CCU8_GCSS_S1SE_Msk \ - (0x10UL) /*!< CCU8 GCSS: S1SE (Bitfield-Mask: 0x01) */ -#define CCU8_GCSS_S1DSE_Pos \ - (5UL) /*!< CCU8 GCSS: S1DSE (Bit 5) */ -#define CCU8_GCSS_S1DSE_Msk \ - (0x20UL) /*!< CCU8 GCSS: S1DSE (Bitfield-Mask: 0x01) */ -#define CCU8_GCSS_S1PSE_Pos \ - (6UL) /*!< CCU8 GCSS: S1PSE (Bit 6) */ -#define CCU8_GCSS_S1PSE_Msk \ - (0x40UL) /*!< CCU8 GCSS: S1PSE (Bitfield-Mask: 0x01) */ -#define CCU8_GCSS_S2SE_Pos (8UL) /*!< CCU8 GCSS: S2SE (Bit 8) */ -#define CCU8_GCSS_S2SE_Msk \ - (0x100UL) /*!< CCU8 GCSS: S2SE (Bitfield-Mask: 0x01) */ -#define CCU8_GCSS_S2DSE_Pos \ - (9UL) /*!< CCU8 GCSS: S2DSE (Bit 9) */ -#define CCU8_GCSS_S2DSE_Msk \ - (0x200UL) /*!< CCU8 GCSS: S2DSE (Bitfield-Mask: 0x01) */ -#define CCU8_GCSS_S2PSE_Pos \ - (10UL) /*!< CCU8 GCSS: S2PSE (Bit 10) */ -#define CCU8_GCSS_S2PSE_Msk \ - (0x400UL) /*!< CCU8 GCSS: S2PSE (Bitfield-Mask: 0x01) */ -#define CCU8_GCSS_S3SE_Pos \ - (12UL) /*!< CCU8 GCSS: S3SE (Bit 12) */ -#define CCU8_GCSS_S3SE_Msk \ - (0x1000UL) /*!< CCU8 GCSS: S3SE (Bitfield-Mask: 0x01) */ -#define CCU8_GCSS_S3DSE_Pos \ - (13UL) /*!< CCU8 GCSS: S3DSE (Bit 13) */ -#define CCU8_GCSS_S3DSE_Msk \ - (0x2000UL) /*!< CCU8 GCSS: S3DSE (Bitfield-Mask: 0x01) */ -#define CCU8_GCSS_S3PSE_Pos \ - (14UL) /*!< CCU8 GCSS: S3PSE (Bit 14) */ -#define CCU8_GCSS_S3PSE_Msk \ - (0x4000UL) /*!< CCU8 GCSS: S3PSE (Bitfield-Mask: 0x01) */ -#define CCU8_GCSS_S0ST1S_Pos \ - (16UL) /*!< CCU8 GCSS: S0ST1S (Bit 16) */ -#define CCU8_GCSS_S0ST1S_Msk \ - (0x10000UL) /*!< CCU8 GCSS: S0ST1S (Bitfield-Mask: 0x01) */ -#define CCU8_GCSS_S1ST1S_Pos \ - (17UL) /*!< CCU8 GCSS: S1ST1S (Bit 17) */ -#define CCU8_GCSS_S1ST1S_Msk \ - (0x20000UL) /*!< CCU8 GCSS: S1ST1S (Bitfield-Mask: 0x01) */ -#define CCU8_GCSS_S2ST1S_Pos \ - (18UL) /*!< CCU8 GCSS: S2ST1S (Bit 18) */ -#define CCU8_GCSS_S2ST1S_Msk \ - (0x40000UL) /*!< CCU8 GCSS: S2ST1S (Bitfield-Mask: 0x01) */ -#define CCU8_GCSS_S3ST1S_Pos \ - (19UL) /*!< CCU8 GCSS: S3ST1S (Bit 19) */ -#define CCU8_GCSS_S3ST1S_Msk \ - (0x80000UL) /*!< CCU8 GCSS: S3ST1S (Bitfield-Mask: 0x01) */ -#define CCU8_GCSS_S0ST2S_Pos \ - (20UL) /*!< CCU8 GCSS: S0ST2S (Bit 20) */ -#define CCU8_GCSS_S0ST2S_Msk \ - (0x100000UL) /*!< CCU8 GCSS: S0ST2S (Bitfield-Mask: 0x01) */ -#define CCU8_GCSS_S1ST2S_Pos \ - (21UL) /*!< CCU8 GCSS: S1ST2S (Bit 21) */ -#define CCU8_GCSS_S1ST2S_Msk \ - (0x200000UL) /*!< CCU8 GCSS: S1ST2S (Bitfield-Mask: 0x01) */ -#define CCU8_GCSS_S2ST2S_Pos \ - (22UL) /*!< CCU8 GCSS: S2ST2S (Bit 22) */ -#define CCU8_GCSS_S2ST2S_Msk \ - (0x400000UL) /*!< CCU8 GCSS: S2ST2S (Bitfield-Mask: 0x01) */ -#define CCU8_GCSS_S3ST2S_Pos \ - (23UL) /*!< CCU8 GCSS: S3ST2S (Bit 23) */ -#define CCU8_GCSS_S3ST2S_Msk \ - (0x800000UL) /*!< CCU8 GCSS: S3ST2S (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- CCU8_GCSC --------------------------------- */ -#define CCU8_GCSC_S0SC_Pos (0UL) /*!< CCU8 GCSC: S0SC (Bit 0) */ -#define CCU8_GCSC_S0SC_Msk \ - (0x1UL) /*!< CCU8 GCSC: S0SC (Bitfield-Mask: 0x01) */ -#define CCU8_GCSC_S0DSC_Pos \ - (1UL) /*!< CCU8 GCSC: S0DSC (Bit 1) */ -#define CCU8_GCSC_S0DSC_Msk \ - (0x2UL) /*!< CCU8 GCSC: S0DSC (Bitfield-Mask: 0x01) */ -#define CCU8_GCSC_S0PSC_Pos \ - (2UL) /*!< CCU8 GCSC: S0PSC (Bit 2) */ -#define CCU8_GCSC_S0PSC_Msk \ - (0x4UL) /*!< CCU8 GCSC: S0PSC (Bitfield-Mask: 0x01) */ -#define CCU8_GCSC_S1SC_Pos (4UL) /*!< CCU8 GCSC: S1SC (Bit 4) */ -#define CCU8_GCSC_S1SC_Msk \ - (0x10UL) /*!< CCU8 GCSC: S1SC (Bitfield-Mask: 0x01) */ -#define CCU8_GCSC_S1DSC_Pos \ - (5UL) /*!< CCU8 GCSC: S1DSC (Bit 5) */ -#define CCU8_GCSC_S1DSC_Msk \ - (0x20UL) /*!< CCU8 GCSC: S1DSC (Bitfield-Mask: 0x01) */ -#define CCU8_GCSC_S1PSC_Pos \ - (6UL) /*!< CCU8 GCSC: S1PSC (Bit 6) */ -#define CCU8_GCSC_S1PSC_Msk \ - (0x40UL) /*!< CCU8 GCSC: S1PSC (Bitfield-Mask: 0x01) */ -#define CCU8_GCSC_S2SC_Pos (8UL) /*!< CCU8 GCSC: S2SC (Bit 8) */ -#define CCU8_GCSC_S2SC_Msk \ - (0x100UL) /*!< CCU8 GCSC: S2SC (Bitfield-Mask: 0x01) */ -#define CCU8_GCSC_S2DSC_Pos \ - (9UL) /*!< CCU8 GCSC: S2DSC (Bit 9) */ -#define CCU8_GCSC_S2DSC_Msk \ - (0x200UL) /*!< CCU8 GCSC: S2DSC (Bitfield-Mask: 0x01) */ -#define CCU8_GCSC_S2PSC_Pos \ - (10UL) /*!< CCU8 GCSC: S2PSC (Bit 10) */ -#define CCU8_GCSC_S2PSC_Msk \ - (0x400UL) /*!< CCU8 GCSC: S2PSC (Bitfield-Mask: 0x01) */ -#define CCU8_GCSC_S3SC_Pos \ - (12UL) /*!< CCU8 GCSC: S3SC (Bit 12) */ -#define CCU8_GCSC_S3SC_Msk \ - (0x1000UL) /*!< CCU8 GCSC: S3SC (Bitfield-Mask: 0x01) */ -#define CCU8_GCSC_S3DSC_Pos \ - (13UL) /*!< CCU8 GCSC: S3DSC (Bit 13) */ -#define CCU8_GCSC_S3DSC_Msk \ - (0x2000UL) /*!< CCU8 GCSC: S3DSC (Bitfield-Mask: 0x01) */ -#define CCU8_GCSC_S3PSC_Pos \ - (14UL) /*!< CCU8 GCSC: S3PSC (Bit 14) */ -#define CCU8_GCSC_S3PSC_Msk \ - (0x4000UL) /*!< CCU8 GCSC: S3PSC (Bitfield-Mask: 0x01) */ -#define CCU8_GCSC_S0ST1C_Pos \ - (16UL) /*!< CCU8 GCSC: S0ST1C (Bit 16) */ -#define CCU8_GCSC_S0ST1C_Msk \ - (0x10000UL) /*!< CCU8 GCSC: S0ST1C (Bitfield-Mask: 0x01) */ -#define CCU8_GCSC_S1ST1C_Pos \ - (17UL) /*!< CCU8 GCSC: S1ST1C (Bit 17) */ -#define CCU8_GCSC_S1ST1C_Msk \ - (0x20000UL) /*!< CCU8 GCSC: S1ST1C (Bitfield-Mask: 0x01) */ -#define CCU8_GCSC_S2ST1C_Pos \ - (18UL) /*!< CCU8 GCSC: S2ST1C (Bit 18) */ -#define CCU8_GCSC_S2ST1C_Msk \ - (0x40000UL) /*!< CCU8 GCSC: S2ST1C (Bitfield-Mask: 0x01) */ -#define CCU8_GCSC_S3ST1C_Pos \ - (19UL) /*!< CCU8 GCSC: S3ST1C (Bit 19) */ -#define CCU8_GCSC_S3ST1C_Msk \ - (0x80000UL) /*!< CCU8 GCSC: S3ST1C (Bitfield-Mask: 0x01) */ -#define CCU8_GCSC_S0ST2C_Pos \ - (20UL) /*!< CCU8 GCSC: S0ST2C (Bit 20) */ -#define CCU8_GCSC_S0ST2C_Msk \ - (0x100000UL) /*!< CCU8 GCSC: S0ST2C (Bitfield-Mask: 0x01) */ -#define CCU8_GCSC_S1ST2C_Pos \ - (21UL) /*!< CCU8 GCSC: S1ST2C (Bit 21) */ -#define CCU8_GCSC_S1ST2C_Msk \ - (0x200000UL) /*!< CCU8 GCSC: S1ST2C (Bitfield-Mask: 0x01) */ -#define CCU8_GCSC_S2ST2C_Pos \ - (22UL) /*!< CCU8 GCSC: S2ST2C (Bit 22) */ -#define CCU8_GCSC_S2ST2C_Msk \ - (0x400000UL) /*!< CCU8 GCSC: S2ST2C (Bitfield-Mask: 0x01) */ -#define CCU8_GCSC_S3ST2C_Pos \ - (23UL) /*!< CCU8 GCSC: S3ST2C (Bit 23) */ -#define CCU8_GCSC_S3ST2C_Msk \ - (0x800000UL) /*!< CCU8 GCSC: S3ST2C (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- CCU8_GCST --------------------------------- */ -#define CCU8_GCST_S0SS_Pos (0UL) /*!< CCU8 GCST: S0SS (Bit 0) */ -#define CCU8_GCST_S0SS_Msk \ - (0x1UL) /*!< CCU8 GCST: S0SS (Bitfield-Mask: 0x01) */ -#define CCU8_GCST_S0DSS_Pos \ - (1UL) /*!< CCU8 GCST: S0DSS (Bit 1) */ -#define CCU8_GCST_S0DSS_Msk \ - (0x2UL) /*!< CCU8 GCST: S0DSS (Bitfield-Mask: 0x01) */ -#define CCU8_GCST_S0PSS_Pos \ - (2UL) /*!< CCU8 GCST: S0PSS (Bit 2) */ -#define CCU8_GCST_S0PSS_Msk \ - (0x4UL) /*!< CCU8 GCST: S0PSS (Bitfield-Mask: 0x01) */ -#define CCU8_GCST_S1SS_Pos (4UL) /*!< CCU8 GCST: S1SS (Bit 4) */ -#define CCU8_GCST_S1SS_Msk \ - (0x10UL) /*!< CCU8 GCST: S1SS (Bitfield-Mask: 0x01) */ -#define CCU8_GCST_S1DSS_Pos \ - (5UL) /*!< CCU8 GCST: S1DSS (Bit 5) */ -#define CCU8_GCST_S1DSS_Msk \ - (0x20UL) /*!< CCU8 GCST: S1DSS (Bitfield-Mask: 0x01) */ -#define CCU8_GCST_S1PSS_Pos \ - (6UL) /*!< CCU8 GCST: S1PSS (Bit 6) */ -#define CCU8_GCST_S1PSS_Msk \ - (0x40UL) /*!< CCU8 GCST: S1PSS (Bitfield-Mask: 0x01) */ -#define CCU8_GCST_S2SS_Pos (8UL) /*!< CCU8 GCST: S2SS (Bit 8) */ -#define CCU8_GCST_S2SS_Msk \ - (0x100UL) /*!< CCU8 GCST: S2SS (Bitfield-Mask: 0x01) */ -#define CCU8_GCST_S2DSS_Pos \ - (9UL) /*!< CCU8 GCST: S2DSS (Bit 9) */ -#define CCU8_GCST_S2DSS_Msk \ - (0x200UL) /*!< CCU8 GCST: S2DSS (Bitfield-Mask: 0x01) */ -#define CCU8_GCST_S2PSS_Pos \ - (10UL) /*!< CCU8 GCST: S2PSS (Bit 10) */ -#define CCU8_GCST_S2PSS_Msk \ - (0x400UL) /*!< CCU8 GCST: S2PSS (Bitfield-Mask: 0x01) */ -#define CCU8_GCST_S3SS_Pos \ - (12UL) /*!< CCU8 GCST: S3SS (Bit 12) */ -#define CCU8_GCST_S3SS_Msk \ - (0x1000UL) /*!< CCU8 GCST: S3SS (Bitfield-Mask: 0x01) */ -#define CCU8_GCST_S3DSS_Pos \ - (13UL) /*!< CCU8 GCST: S3DSS (Bit 13) */ -#define CCU8_GCST_S3DSS_Msk \ - (0x2000UL) /*!< CCU8 GCST: S3DSS (Bitfield-Mask: 0x01) */ -#define CCU8_GCST_S3PSS_Pos \ - (14UL) /*!< CCU8 GCST: S3PSS (Bit 14) */ -#define CCU8_GCST_S3PSS_Msk \ - (0x4000UL) /*!< CCU8 GCST: S3PSS (Bitfield-Mask: 0x01) */ -#define CCU8_GCST_CC80ST1_Pos \ - (16UL) /*!< CCU8 GCST: CC80ST1 (Bit 16) */ -#define CCU8_GCST_CC80ST1_Msk \ - (0x10000UL) /*!< CCU8 GCST: CC80ST1 (Bitfield-Mask: 0x01) */ -#define CCU8_GCST_CC81ST1_Pos \ - (17UL) /*!< CCU8 GCST: CC81ST1 (Bit 17) */ -#define CCU8_GCST_CC81ST1_Msk \ - (0x20000UL) /*!< CCU8 GCST: CC81ST1 (Bitfield-Mask: 0x01) */ -#define CCU8_GCST_CC82ST1_Pos \ - (18UL) /*!< CCU8 GCST: CC82ST1 (Bit 18) */ -#define CCU8_GCST_CC82ST1_Msk \ - (0x40000UL) /*!< CCU8 GCST: CC82ST1 (Bitfield-Mask: 0x01) */ -#define CCU8_GCST_CC83ST1_Pos \ - (19UL) /*!< CCU8 GCST: CC83ST1 (Bit 19) */ -#define CCU8_GCST_CC83ST1_Msk \ - (0x80000UL) /*!< CCU8 GCST: CC83ST1 (Bitfield-Mask: 0x01) */ -#define CCU8_GCST_CC80ST2_Pos \ - (20UL) /*!< CCU8 GCST: CC80ST2 (Bit 20) */ -#define CCU8_GCST_CC80ST2_Msk \ - (0x100000UL) /*!< CCU8 GCST: CC80ST2 (Bitfield-Mask: 0x01) */ -#define CCU8_GCST_CC81ST2_Pos \ - (21UL) /*!< CCU8 GCST: CC81ST2 (Bit 21) */ -#define CCU8_GCST_CC81ST2_Msk \ - (0x200000UL) /*!< CCU8 GCST: CC81ST2 (Bitfield-Mask: 0x01) */ -#define CCU8_GCST_CC82ST2_Pos \ - (22UL) /*!< CCU8 GCST: CC82ST2 (Bit 22) */ -#define CCU8_GCST_CC82ST2_Msk \ - (0x400000UL) /*!< CCU8 GCST: CC82ST2 (Bitfield-Mask: 0x01) */ -#define CCU8_GCST_CC83ST2_Pos \ - (23UL) /*!< CCU8 GCST: CC83ST2 (Bit 23) */ -#define CCU8_GCST_CC83ST2_Msk \ - (0x800000UL) /*!< CCU8 GCST: CC83ST2 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- CCU8_GPCHK --------------------------------- */ -#define CCU8_GPCHK_PASE_Pos \ - (0UL) /*!< CCU8 GPCHK: PASE (Bit 0) */ -#define CCU8_GPCHK_PASE_Msk \ - (0x1UL) /*!< CCU8 GPCHK: PASE (Bitfield-Mask: 0x01) */ -#define CCU8_GPCHK_PACS_Pos \ - (1UL) /*!< CCU8 GPCHK: PACS (Bit 1) */ -#define CCU8_GPCHK_PACS_Msk \ - (0x6UL) /*!< CCU8 GPCHK: PACS (Bitfield-Mask: 0x03) */ -#define CCU8_GPCHK_PISEL_Pos \ - (3UL) /*!< CCU8 GPCHK: PISEL (Bit 3) */ -#define CCU8_GPCHK_PISEL_Msk \ - (0x18UL) /*!< CCU8 GPCHK: PISEL (Bitfield-Mask: 0x03) */ -#define CCU8_GPCHK_PCDS_Pos \ - (5UL) /*!< CCU8 GPCHK: PCDS (Bit 5) */ -#define CCU8_GPCHK_PCDS_Msk \ - (0x60UL) /*!< CCU8 GPCHK: PCDS (Bitfield-Mask: 0x03) */ -#define CCU8_GPCHK_PCTS_Pos \ - (7UL) /*!< CCU8 GPCHK: PCTS (Bit 7) */ -#define CCU8_GPCHK_PCTS_Msk \ - (0x80UL) /*!< CCU8 GPCHK: PCTS (Bitfield-Mask: 0x01) */ -#define CCU8_GPCHK_PCST_Pos \ - (15UL) /*!< CCU8 GPCHK: PCST (Bit 15) */ -#define CCU8_GPCHK_PCST_Msk \ - (0x8000UL) /*!< CCU8 GPCHK: PCST (Bitfield-Mask: 0x01) */ -#define CCU8_GPCHK_PCSEL0_Pos \ - (16UL) /*!< CCU8 GPCHK: PCSEL0 (Bit 16) */ -#define CCU8_GPCHK_PCSEL0_Msk \ - (0xf0000UL) /*!< CCU8 GPCHK: PCSEL0 (Bitfield-Mask: 0x0f) */ -#define CCU8_GPCHK_PCSEL1_Pos \ - (20UL) /*!< CCU8 GPCHK: PCSEL1 (Bit 20) */ -#define CCU8_GPCHK_PCSEL1_Msk \ - (0xf00000UL) /*!< CCU8 GPCHK: PCSEL1 (Bitfield-Mask: 0x0f) */ -#define CCU8_GPCHK_PCSEL2_Pos \ - (24UL) /*!< CCU8 GPCHK: PCSEL2 (Bit 24) */ -#define CCU8_GPCHK_PCSEL2_Msk \ - (0xf000000UL) /*!< CCU8 GPCHK: PCSEL2 (Bitfield-Mask: 0x0f) */ -#define CCU8_GPCHK_PCSEL3_Pos \ - (28UL) /*!< CCU8 GPCHK: PCSEL3 (Bit 28) */ -#define CCU8_GPCHK_PCSEL3_Msk \ - (0xf0000000UL) /*!< CCU8 GPCHK: PCSEL3 (Bitfield-Mask: 0x0f) */ - -/* ---------------------------------- CCU8_ECRD --------------------------------- */ -#define CCU8_ECRD_CAPV_Pos (0UL) /*!< CCU8 ECRD: CAPV (Bit 0) */ -#define CCU8_ECRD_CAPV_Msk \ - (0xffffUL) /*!< CCU8 ECRD: CAPV (Bitfield-Mask: 0xffff) */ -#define CCU8_ECRD_FPCV_Pos \ - (16UL) /*!< CCU8 ECRD: FPCV (Bit 16) */ -#define CCU8_ECRD_FPCV_Msk \ - (0xf0000UL) /*!< CCU8 ECRD: FPCV (Bitfield-Mask: 0x0f) */ -#define CCU8_ECRD_SPTR_Pos \ - (20UL) /*!< CCU8 ECRD: SPTR (Bit 20) */ -#define CCU8_ECRD_SPTR_Msk \ - (0x300000UL) /*!< CCU8 ECRD: SPTR (Bitfield-Mask: 0x03) */ -#define CCU8_ECRD_VPTR_Pos \ - (22UL) /*!< CCU8 ECRD: VPTR (Bit 22) */ -#define CCU8_ECRD_VPTR_Msk \ - (0xc00000UL) /*!< CCU8 ECRD: VPTR (Bitfield-Mask: 0x03) */ -#define CCU8_ECRD_FFL_Pos (24UL) /*!< CCU8 ECRD: FFL (Bit 24) */ -#define CCU8_ECRD_FFL_Msk \ - (0x1000000UL) /*!< CCU8 ECRD: FFL (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- CCU8_MIDR --------------------------------- */ -#define CCU8_MIDR_MODR_Pos (0UL) /*!< CCU8 MIDR: MODR (Bit 0) */ -#define CCU8_MIDR_MODR_Msk \ - (0xffUL) /*!< CCU8 MIDR: MODR (Bitfield-Mask: 0xff) */ -#define CCU8_MIDR_MODT_Pos (8UL) /*!< CCU8 MIDR: MODT (Bit 8) */ -#define CCU8_MIDR_MODT_Msk \ - (0xff00UL) /*!< CCU8 MIDR: MODT (Bitfield-Mask: 0xff) */ -#define CCU8_MIDR_MODN_Pos \ - (16UL) /*!< CCU8 MIDR: MODN (Bit 16) */ -#define CCU8_MIDR_MODN_Msk \ - (0xffff0000UL) /*!< CCU8 MIDR: MODN (Bitfield-Mask: 0xffff) */ - -/* ================================================================================ */ -/* ================ Group 'CCU8_CC8' Position & Mask ================ */ -/* ================================================================================ */ - -/* -------------------------------- CCU8_CC8_INS -------------------------------- */ -#define CCU8_CC8_INS_EV0IS_Pos \ - (0UL) /*!< CCU8_CC8 INS: EV0IS (Bit 0) */ -#define CCU8_CC8_INS_EV0IS_Msk \ - (0xfUL) /*!< CCU8_CC8 INS: EV0IS (Bitfield-Mask: 0x0f) */ -#define CCU8_CC8_INS_EV1IS_Pos \ - (4UL) /*!< CCU8_CC8 INS: EV1IS (Bit 4) */ -#define CCU8_CC8_INS_EV1IS_Msk \ - (0xf0UL) /*!< CCU8_CC8 INS: EV1IS (Bitfield-Mask: 0x0f) */ -#define CCU8_CC8_INS_EV2IS_Pos \ - (8UL) /*!< CCU8_CC8 INS: EV2IS (Bit 8) */ -#define CCU8_CC8_INS_EV2IS_Msk \ - (0xf00UL) /*!< CCU8_CC8 INS: EV2IS (Bitfield-Mask: 0x0f) */ -#define CCU8_CC8_INS_EV0EM_Pos \ - (16UL) /*!< CCU8_CC8 INS: EV0EM (Bit 16) */ -#define CCU8_CC8_INS_EV0EM_Msk \ - (0x30000UL) /*!< CCU8_CC8 INS: EV0EM (Bitfield-Mask: 0x03) */ -#define CCU8_CC8_INS_EV1EM_Pos \ - (18UL) /*!< CCU8_CC8 INS: EV1EM (Bit 18) */ -#define CCU8_CC8_INS_EV1EM_Msk \ - (0xc0000UL) /*!< CCU8_CC8 INS: EV1EM (Bitfield-Mask: 0x03) */ -#define CCU8_CC8_INS_EV2EM_Pos \ - (20UL) /*!< CCU8_CC8 INS: EV2EM (Bit 20) */ -#define CCU8_CC8_INS_EV2EM_Msk \ - (0x300000UL) /*!< CCU8_CC8 INS: EV2EM (Bitfield-Mask: 0x03) */ -#define CCU8_CC8_INS_EV0LM_Pos \ - (22UL) /*!< CCU8_CC8 INS: EV0LM (Bit 22) */ -#define CCU8_CC8_INS_EV0LM_Msk \ - (0x400000UL) /*!< CCU8_CC8 INS: EV0LM (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_INS_EV1LM_Pos \ - (23UL) /*!< CCU8_CC8 INS: EV1LM (Bit 23) */ -#define CCU8_CC8_INS_EV1LM_Msk \ - (0x800000UL) /*!< CCU8_CC8 INS: EV1LM (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_INS_EV2LM_Pos \ - (24UL) /*!< CCU8_CC8 INS: EV2LM (Bit 24) */ -#define CCU8_CC8_INS_EV2LM_Msk \ - (0x1000000UL) /*!< CCU8_CC8 INS: EV2LM (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_INS_LPF0M_Pos \ - (25UL) /*!< CCU8_CC8 INS: LPF0M (Bit 25) */ -#define CCU8_CC8_INS_LPF0M_Msk \ - (0x6000000UL) /*!< CCU8_CC8 INS: LPF0M (Bitfield-Mask: 0x03) */ -#define CCU8_CC8_INS_LPF1M_Pos \ - (27UL) /*!< CCU8_CC8 INS: LPF1M (Bit 27) */ -#define CCU8_CC8_INS_LPF1M_Msk \ - (0x18000000UL) /*!< CCU8_CC8 INS: LPF1M (Bitfield-Mask: 0x03) */ -#define CCU8_CC8_INS_LPF2M_Pos \ - (29UL) /*!< CCU8_CC8 INS: LPF2M (Bit 29) */ -#define CCU8_CC8_INS_LPF2M_Msk \ - (0x60000000UL) /*!< CCU8_CC8 INS: LPF2M (Bitfield-Mask: 0x03) */ - -/* -------------------------------- CCU8_CC8_CMC -------------------------------- */ -#define CCU8_CC8_CMC_STRTS_Pos \ - (0UL) /*!< CCU8_CC8 CMC: STRTS (Bit 0) */ -#define CCU8_CC8_CMC_STRTS_Msk \ - (0x3UL) /*!< CCU8_CC8 CMC: STRTS (Bitfield-Mask: 0x03) */ -#define CCU8_CC8_CMC_ENDS_Pos \ - (2UL) /*!< CCU8_CC8 CMC: ENDS (Bit 2) */ -#define CCU8_CC8_CMC_ENDS_Msk \ - (0xcUL) /*!< CCU8_CC8 CMC: ENDS (Bitfield-Mask: 0x03) */ -#define CCU8_CC8_CMC_CAP0S_Pos \ - (4UL) /*!< CCU8_CC8 CMC: CAP0S (Bit 4) */ -#define CCU8_CC8_CMC_CAP0S_Msk \ - (0x30UL) /*!< CCU8_CC8 CMC: CAP0S (Bitfield-Mask: 0x03) */ -#define CCU8_CC8_CMC_CAP1S_Pos \ - (6UL) /*!< CCU8_CC8 CMC: CAP1S (Bit 6) */ -#define CCU8_CC8_CMC_CAP1S_Msk \ - (0xc0UL) /*!< CCU8_CC8 CMC: CAP1S (Bitfield-Mask: 0x03) */ -#define CCU8_CC8_CMC_GATES_Pos \ - (8UL) /*!< CCU8_CC8 CMC: GATES (Bit 8) */ -#define CCU8_CC8_CMC_GATES_Msk \ - (0x300UL) /*!< CCU8_CC8 CMC: GATES (Bitfield-Mask: 0x03) */ -#define CCU8_CC8_CMC_UDS_Pos \ - (10UL) /*!< CCU8_CC8 CMC: UDS (Bit 10) */ -#define CCU8_CC8_CMC_UDS_Msk \ - (0xc00UL) /*!< CCU8_CC8 CMC: UDS (Bitfield-Mask: 0x03) */ -#define CCU8_CC8_CMC_LDS_Pos \ - (12UL) /*!< CCU8_CC8 CMC: LDS (Bit 12) */ -#define CCU8_CC8_CMC_LDS_Msk \ - (0x3000UL) /*!< CCU8_CC8 CMC: LDS (Bitfield-Mask: 0x03) */ -#define CCU8_CC8_CMC_CNTS_Pos \ - (14UL) /*!< CCU8_CC8 CMC: CNTS (Bit 14) */ -#define CCU8_CC8_CMC_CNTS_Msk \ - (0xc000UL) /*!< CCU8_CC8 CMC: CNTS (Bitfield-Mask: 0x03) */ -#define CCU8_CC8_CMC_OFS_Pos \ - (16UL) /*!< CCU8_CC8 CMC: OFS (Bit 16) */ -#define CCU8_CC8_CMC_OFS_Msk \ - (0x10000UL) /*!< CCU8_CC8 CMC: OFS (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_CMC_TS_Pos \ - (17UL) /*!< CCU8_CC8 CMC: TS (Bit 17) */ -#define CCU8_CC8_CMC_TS_Msk \ - (0x20000UL) /*!< CCU8_CC8 CMC: TS (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_CMC_MOS_Pos \ - (18UL) /*!< CCU8_CC8 CMC: MOS (Bit 18) */ -#define CCU8_CC8_CMC_MOS_Msk \ - (0xc0000UL) /*!< CCU8_CC8 CMC: MOS (Bitfield-Mask: 0x03) */ -#define CCU8_CC8_CMC_TCE_Pos \ - (20UL) /*!< CCU8_CC8 CMC: TCE (Bit 20) */ -#define CCU8_CC8_CMC_TCE_Msk \ - (0x100000UL) /*!< CCU8_CC8 CMC: TCE (Bitfield-Mask: 0x01) */ - -/* -------------------------------- CCU8_CC8_TCST ------------------------------- */ -#define CCU8_CC8_TCST_TRB_Pos \ - (0UL) /*!< CCU8_CC8 TCST: TRB (Bit 0) */ -#define CCU8_CC8_TCST_TRB_Msk \ - (0x1UL) /*!< CCU8_CC8 TCST: TRB (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TCST_CDIR_Pos \ - (1UL) /*!< CCU8_CC8 TCST: CDIR (Bit 1) */ -#define CCU8_CC8_TCST_CDIR_Msk \ - (0x2UL) /*!< CCU8_CC8 TCST: CDIR (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TCST_DTR1_Pos \ - (3UL) /*!< CCU8_CC8 TCST: DTR1 (Bit 3) */ -#define CCU8_CC8_TCST_DTR1_Msk \ - (0x8UL) /*!< CCU8_CC8 TCST: DTR1 (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TCST_DTR2_Pos \ - (4UL) /*!< CCU8_CC8 TCST: DTR2 (Bit 4) */ -#define CCU8_CC8_TCST_DTR2_Msk \ - (0x10UL) /*!< CCU8_CC8 TCST: DTR2 (Bitfield-Mask: 0x01) */ - -/* ------------------------------- CCU8_CC8_TCSET ------------------------------- */ -#define CCU8_CC8_TCSET_TRBS_Pos \ - (0UL) /*!< CCU8_CC8 TCSET: TRBS (Bit 0) */ -#define CCU8_CC8_TCSET_TRBS_Msk \ - (0x1UL) /*!< CCU8_CC8 TCSET: TRBS (Bitfield-Mask: 0x01) */ - -/* ------------------------------- CCU8_CC8_TCCLR ------------------------------- */ -#define CCU8_CC8_TCCLR_TRBC_Pos \ - (0UL) /*!< CCU8_CC8 TCCLR: TRBC (Bit 0) */ -#define CCU8_CC8_TCCLR_TRBC_Msk \ - (0x1UL) /*!< CCU8_CC8 TCCLR: TRBC (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TCCLR_TCC_Pos \ - (1UL) /*!< CCU8_CC8 TCCLR: TCC (Bit 1) */ -#define CCU8_CC8_TCCLR_TCC_Msk \ - (0x2UL) /*!< CCU8_CC8 TCCLR: TCC (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TCCLR_DITC_Pos \ - (2UL) /*!< CCU8_CC8 TCCLR: DITC (Bit 2) */ -#define CCU8_CC8_TCCLR_DITC_Msk \ - (0x4UL) /*!< CCU8_CC8 TCCLR: DITC (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TCCLR_DTC1C_Pos \ - (3UL) /*!< CCU8_CC8 TCCLR: DTC1C (Bit 3) */ -#define CCU8_CC8_TCCLR_DTC1C_Msk \ - (0x8UL) /*!< CCU8_CC8 TCCLR: DTC1C (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TCCLR_DTC2C_Pos \ - (4UL) /*!< CCU8_CC8 TCCLR: DTC2C (Bit 4) */ -#define CCU8_CC8_TCCLR_DTC2C_Msk \ - (0x10UL) /*!< CCU8_CC8 TCCLR: DTC2C (Bitfield-Mask: 0x01) */ - -/* --------------------------------- CCU8_CC8_TC -------------------------------- */ -#define CCU8_CC8_TC_TCM_Pos \ - (0UL) /*!< CCU8_CC8 TC: TCM (Bit 0) */ -#define CCU8_CC8_TC_TCM_Msk \ - (0x1UL) /*!< CCU8_CC8 TC: TCM (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TC_TSSM_Pos \ - (1UL) /*!< CCU8_CC8 TC: TSSM (Bit 1) */ -#define CCU8_CC8_TC_TSSM_Msk \ - (0x2UL) /*!< CCU8_CC8 TC: TSSM (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TC_CLST_Pos \ - (2UL) /*!< CCU8_CC8 TC: CLST (Bit 2) */ -#define CCU8_CC8_TC_CLST_Msk \ - (0x4UL) /*!< CCU8_CC8 TC: CLST (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TC_CMOD_Pos \ - (3UL) /*!< CCU8_CC8 TC: CMOD (Bit 3) */ -#define CCU8_CC8_TC_CMOD_Msk \ - (0x8UL) /*!< CCU8_CC8 TC: CMOD (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TC_ECM_Pos \ - (4UL) /*!< CCU8_CC8 TC: ECM (Bit 4) */ -#define CCU8_CC8_TC_ECM_Msk \ - (0x10UL) /*!< CCU8_CC8 TC: ECM (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TC_CAPC_Pos \ - (5UL) /*!< CCU8_CC8 TC: CAPC (Bit 5) */ -#define CCU8_CC8_TC_CAPC_Msk \ - (0x60UL) /*!< CCU8_CC8 TC: CAPC (Bitfield-Mask: 0x03) */ -#define CCU8_CC8_TC_TLS_Pos \ - (7UL) /*!< CCU8_CC8 TC: TLS (Bit 7) */ -#define CCU8_CC8_TC_TLS_Msk \ - (0x80UL) /*!< CCU8_CC8 TC: TLS (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TC_ENDM_Pos \ - (8UL) /*!< CCU8_CC8 TC: ENDM (Bit 8) */ -#define CCU8_CC8_TC_ENDM_Msk \ - (0x300UL) /*!< CCU8_CC8 TC: ENDM (Bitfield-Mask: 0x03) */ -#define CCU8_CC8_TC_STRM_Pos \ - (10UL) /*!< CCU8_CC8 TC: STRM (Bit 10) */ -#define CCU8_CC8_TC_STRM_Msk \ - (0x400UL) /*!< CCU8_CC8 TC: STRM (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TC_SCE_Pos \ - (11UL) /*!< CCU8_CC8 TC: SCE (Bit 11) */ -#define CCU8_CC8_TC_SCE_Msk \ - (0x800UL) /*!< CCU8_CC8 TC: SCE (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TC_CCS_Pos \ - (12UL) /*!< CCU8_CC8 TC: CCS (Bit 12) */ -#define CCU8_CC8_TC_CCS_Msk \ - (0x1000UL) /*!< CCU8_CC8 TC: CCS (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TC_DITHE_Pos \ - (13UL) /*!< CCU8_CC8 TC: DITHE (Bit 13) */ -#define CCU8_CC8_TC_DITHE_Msk \ - (0x6000UL) /*!< CCU8_CC8 TC: DITHE (Bitfield-Mask: 0x03) */ -#define CCU8_CC8_TC_DIM_Pos \ - (15UL) /*!< CCU8_CC8 TC: DIM (Bit 15) */ -#define CCU8_CC8_TC_DIM_Msk \ - (0x8000UL) /*!< CCU8_CC8 TC: DIM (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TC_FPE_Pos \ - (16UL) /*!< CCU8_CC8 TC: FPE (Bit 16) */ -#define CCU8_CC8_TC_FPE_Msk \ - (0x10000UL) /*!< CCU8_CC8 TC: FPE (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TC_TRAPE0_Pos \ - (17UL) /*!< CCU8_CC8 TC: TRAPE0 (Bit 17) */ -#define CCU8_CC8_TC_TRAPE0_Msk \ - (0x20000UL) /*!< CCU8_CC8 TC: TRAPE0 (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TC_TRAPE1_Pos \ - (18UL) /*!< CCU8_CC8 TC: TRAPE1 (Bit 18) */ -#define CCU8_CC8_TC_TRAPE1_Msk \ - (0x40000UL) /*!< CCU8_CC8 TC: TRAPE1 (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TC_TRAPE2_Pos \ - (19UL) /*!< CCU8_CC8 TC: TRAPE2 (Bit 19) */ -#define CCU8_CC8_TC_TRAPE2_Msk \ - (0x80000UL) /*!< CCU8_CC8 TC: TRAPE2 (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TC_TRAPE3_Pos \ - (20UL) /*!< CCU8_CC8 TC: TRAPE3 (Bit 20) */ -#define CCU8_CC8_TC_TRAPE3_Msk \ - (0x100000UL) /*!< CCU8_CC8 TC: TRAPE3 (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TC_TRPSE_Pos \ - (21UL) /*!< CCU8_CC8 TC: TRPSE (Bit 21) */ -#define CCU8_CC8_TC_TRPSE_Msk \ - (0x200000UL) /*!< CCU8_CC8 TC: TRPSE (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TC_TRPSW_Pos \ - (22UL) /*!< CCU8_CC8 TC: TRPSW (Bit 22) */ -#define CCU8_CC8_TC_TRPSW_Msk \ - (0x400000UL) /*!< CCU8_CC8 TC: TRPSW (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TC_EMS_Pos \ - (23UL) /*!< CCU8_CC8 TC: EMS (Bit 23) */ -#define CCU8_CC8_TC_EMS_Msk \ - (0x800000UL) /*!< CCU8_CC8 TC: EMS (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TC_EMT_Pos \ - (24UL) /*!< CCU8_CC8 TC: EMT (Bit 24) */ -#define CCU8_CC8_TC_EMT_Msk \ - (0x1000000UL) /*!< CCU8_CC8 TC: EMT (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TC_MCME1_Pos \ - (25UL) /*!< CCU8_CC8 TC: MCME1 (Bit 25) */ -#define CCU8_CC8_TC_MCME1_Msk \ - (0x2000000UL) /*!< CCU8_CC8 TC: MCME1 (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TC_MCME2_Pos \ - (26UL) /*!< CCU8_CC8 TC: MCME2 (Bit 26) */ -#define CCU8_CC8_TC_MCME2_Msk \ - (0x4000000UL) /*!< CCU8_CC8 TC: MCME2 (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_TC_EME_Pos \ - (27UL) /*!< CCU8_CC8 TC: EME (Bit 27) */ -#define CCU8_CC8_TC_EME_Msk \ - (0x18000000UL) /*!< CCU8_CC8 TC: EME (Bitfield-Mask: 0x03) */ -#define CCU8_CC8_TC_STOS_Pos \ - (29UL) /*!< CCU8_CC8 TC: STOS (Bit 29) */ -#define CCU8_CC8_TC_STOS_Msk \ - (0x60000000UL) /*!< CCU8_CC8 TC: STOS (Bitfield-Mask: 0x03) */ - -/* -------------------------------- CCU8_CC8_PSL -------------------------------- */ -#define CCU8_CC8_PSL_PSL11_Pos \ - (0UL) /*!< CCU8_CC8 PSL: PSL11 (Bit 0) */ -#define CCU8_CC8_PSL_PSL11_Msk \ - (0x1UL) /*!< CCU8_CC8 PSL: PSL11 (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_PSL_PSL12_Pos \ - (1UL) /*!< CCU8_CC8 PSL: PSL12 (Bit 1) */ -#define CCU8_CC8_PSL_PSL12_Msk \ - (0x2UL) /*!< CCU8_CC8 PSL: PSL12 (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_PSL_PSL21_Pos \ - (2UL) /*!< CCU8_CC8 PSL: PSL21 (Bit 2) */ -#define CCU8_CC8_PSL_PSL21_Msk \ - (0x4UL) /*!< CCU8_CC8 PSL: PSL21 (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_PSL_PSL22_Pos \ - (3UL) /*!< CCU8_CC8 PSL: PSL22 (Bit 3) */ -#define CCU8_CC8_PSL_PSL22_Msk \ - (0x8UL) /*!< CCU8_CC8 PSL: PSL22 (Bitfield-Mask: 0x01) */ - -/* -------------------------------- CCU8_CC8_DIT -------------------------------- */ -#define CCU8_CC8_DIT_DCV_Pos \ - (0UL) /*!< CCU8_CC8 DIT: DCV (Bit 0) */ -#define CCU8_CC8_DIT_DCV_Msk \ - (0xfUL) /*!< CCU8_CC8 DIT: DCV (Bitfield-Mask: 0x0f) */ -#define CCU8_CC8_DIT_DCNT_Pos \ - (8UL) /*!< CCU8_CC8 DIT: DCNT (Bit 8) */ -#define CCU8_CC8_DIT_DCNT_Msk \ - (0xf00UL) /*!< CCU8_CC8 DIT: DCNT (Bitfield-Mask: 0x0f) */ - -/* -------------------------------- CCU8_CC8_DITS ------------------------------- */ -#define CCU8_CC8_DITS_DCVS_Pos \ - (0UL) /*!< CCU8_CC8 DITS: DCVS (Bit 0) */ -#define CCU8_CC8_DITS_DCVS_Msk \ - (0xfUL) /*!< CCU8_CC8 DITS: DCVS (Bitfield-Mask: 0x0f) */ - -/* -------------------------------- CCU8_CC8_PSC -------------------------------- */ -#define CCU8_CC8_PSC_PSIV_Pos \ - (0UL) /*!< CCU8_CC8 PSC: PSIV (Bit 0) */ -#define CCU8_CC8_PSC_PSIV_Msk \ - (0xfUL) /*!< CCU8_CC8 PSC: PSIV (Bitfield-Mask: 0x0f) */ - -/* -------------------------------- CCU8_CC8_FPC -------------------------------- */ -#define CCU8_CC8_FPC_PCMP_Pos \ - (0UL) /*!< CCU8_CC8 FPC: PCMP (Bit 0) */ -#define CCU8_CC8_FPC_PCMP_Msk \ - (0xfUL) /*!< CCU8_CC8 FPC: PCMP (Bitfield-Mask: 0x0f) */ -#define CCU8_CC8_FPC_PVAL_Pos \ - (8UL) /*!< CCU8_CC8 FPC: PVAL (Bit 8) */ -#define CCU8_CC8_FPC_PVAL_Msk \ - (0xf00UL) /*!< CCU8_CC8 FPC: PVAL (Bitfield-Mask: 0x0f) */ - -/* -------------------------------- CCU8_CC8_FPCS ------------------------------- */ -#define CCU8_CC8_FPCS_PCMP_Pos \ - (0UL) /*!< CCU8_CC8 FPCS: PCMP (Bit 0) */ -#define CCU8_CC8_FPCS_PCMP_Msk \ - (0xfUL) /*!< CCU8_CC8 FPCS: PCMP (Bitfield-Mask: 0x0f) */ - -/* --------------------------------- CCU8_CC8_PR -------------------------------- */ -#define CCU8_CC8_PR_PR_Pos (0UL) /*!< CCU8_CC8 PR: PR (Bit 0) */ -#define CCU8_CC8_PR_PR_Msk \ - (0xffffUL) /*!< CCU8_CC8 PR: PR (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- CCU8_CC8_PRS -------------------------------- */ -#define CCU8_CC8_PRS_PRS_Pos \ - (0UL) /*!< CCU8_CC8 PRS: PRS (Bit 0) */ -#define CCU8_CC8_PRS_PRS_Msk \ - (0xffffUL) /*!< CCU8_CC8 PRS: PRS (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- CCU8_CC8_CR1 -------------------------------- */ -#define CCU8_CC8_CR1_CR1_Pos \ - (0UL) /*!< CCU8_CC8 CR1: CR1 (Bit 0) */ -#define CCU8_CC8_CR1_CR1_Msk \ - (0xffffUL) /*!< CCU8_CC8 CR1: CR1 (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- CCU8_CC8_CR1S ------------------------------- */ -#define CCU8_CC8_CR1S_CR1S_Pos \ - (0UL) /*!< CCU8_CC8 CR1S: CR1S (Bit 0) */ -#define CCU8_CC8_CR1S_CR1S_Msk \ - (0xffffUL) /*!< CCU8_CC8 CR1S: CR1S (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- CCU8_CC8_CR2 -------------------------------- */ -#define CCU8_CC8_CR2_CR2_Pos \ - (0UL) /*!< CCU8_CC8 CR2: CR2 (Bit 0) */ -#define CCU8_CC8_CR2_CR2_Msk \ - (0xffffUL) /*!< CCU8_CC8 CR2: CR2 (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- CCU8_CC8_CR2S ------------------------------- */ -#define CCU8_CC8_CR2S_CR2S_Pos \ - (0UL) /*!< CCU8_CC8 CR2S: CR2S (Bit 0) */ -#define CCU8_CC8_CR2S_CR2S_Msk \ - (0xffffUL) /*!< CCU8_CC8 CR2S: CR2S (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- CCU8_CC8_CHC -------------------------------- */ -#define CCU8_CC8_CHC_ASE_Pos \ - (0UL) /*!< CCU8_CC8 CHC: ASE (Bit 0) */ -#define CCU8_CC8_CHC_ASE_Msk \ - (0x1UL) /*!< CCU8_CC8 CHC: ASE (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_CHC_OCS1_Pos \ - (1UL) /*!< CCU8_CC8 CHC: OCS1 (Bit 1) */ -#define CCU8_CC8_CHC_OCS1_Msk \ - (0x2UL) /*!< CCU8_CC8 CHC: OCS1 (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_CHC_OCS2_Pos \ - (2UL) /*!< CCU8_CC8 CHC: OCS2 (Bit 2) */ -#define CCU8_CC8_CHC_OCS2_Msk \ - (0x4UL) /*!< CCU8_CC8 CHC: OCS2 (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_CHC_OCS3_Pos \ - (3UL) /*!< CCU8_CC8 CHC: OCS3 (Bit 3) */ -#define CCU8_CC8_CHC_OCS3_Msk \ - (0x8UL) /*!< CCU8_CC8 CHC: OCS3 (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_CHC_OCS4_Pos \ - (4UL) /*!< CCU8_CC8 CHC: OCS4 (Bit 4) */ -#define CCU8_CC8_CHC_OCS4_Msk \ - (0x10UL) /*!< CCU8_CC8 CHC: OCS4 (Bitfield-Mask: 0x01) */ - -/* -------------------------------- CCU8_CC8_DTC -------------------------------- */ -#define CCU8_CC8_DTC_DTE1_Pos \ - (0UL) /*!< CCU8_CC8 DTC: DTE1 (Bit 0) */ -#define CCU8_CC8_DTC_DTE1_Msk \ - (0x1UL) /*!< CCU8_CC8 DTC: DTE1 (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_DTC_DTE2_Pos \ - (1UL) /*!< CCU8_CC8 DTC: DTE2 (Bit 1) */ -#define CCU8_CC8_DTC_DTE2_Msk \ - (0x2UL) /*!< CCU8_CC8 DTC: DTE2 (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_DTC_DCEN1_Pos \ - (2UL) /*!< CCU8_CC8 DTC: DCEN1 (Bit 2) */ -#define CCU8_CC8_DTC_DCEN1_Msk \ - (0x4UL) /*!< CCU8_CC8 DTC: DCEN1 (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_DTC_DCEN2_Pos \ - (3UL) /*!< CCU8_CC8 DTC: DCEN2 (Bit 3) */ -#define CCU8_CC8_DTC_DCEN2_Msk \ - (0x8UL) /*!< CCU8_CC8 DTC: DCEN2 (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_DTC_DCEN3_Pos \ - (4UL) /*!< CCU8_CC8 DTC: DCEN3 (Bit 4) */ -#define CCU8_CC8_DTC_DCEN3_Msk \ - (0x10UL) /*!< CCU8_CC8 DTC: DCEN3 (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_DTC_DCEN4_Pos \ - (5UL) /*!< CCU8_CC8 DTC: DCEN4 (Bit 5) */ -#define CCU8_CC8_DTC_DCEN4_Msk \ - (0x20UL) /*!< CCU8_CC8 DTC: DCEN4 (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_DTC_DTCC_Pos \ - (6UL) /*!< CCU8_CC8 DTC: DTCC (Bit 6) */ -#define CCU8_CC8_DTC_DTCC_Msk \ - (0xc0UL) /*!< CCU8_CC8 DTC: DTCC (Bitfield-Mask: 0x03) */ - -/* -------------------------------- CCU8_CC8_DC1R ------------------------------- */ -#define CCU8_CC8_DC1R_DT1R_Pos \ - (0UL) /*!< CCU8_CC8 DC1R: DT1R (Bit 0) */ -#define CCU8_CC8_DC1R_DT1R_Msk \ - (0xffUL) /*!< CCU8_CC8 DC1R: DT1R (Bitfield-Mask: 0xff) */ -#define CCU8_CC8_DC1R_DT1F_Pos \ - (8UL) /*!< CCU8_CC8 DC1R: DT1F (Bit 8) */ -#define CCU8_CC8_DC1R_DT1F_Msk \ - (0xff00UL) /*!< CCU8_CC8 DC1R: DT1F (Bitfield-Mask: 0xff) */ - -/* -------------------------------- CCU8_CC8_DC2R ------------------------------- */ -#define CCU8_CC8_DC2R_DT2R_Pos \ - (0UL) /*!< CCU8_CC8 DC2R: DT2R (Bit 0) */ -#define CCU8_CC8_DC2R_DT2R_Msk \ - (0xffUL) /*!< CCU8_CC8 DC2R: DT2R (Bitfield-Mask: 0xff) */ -#define CCU8_CC8_DC2R_DT2F_Pos \ - (8UL) /*!< CCU8_CC8 DC2R: DT2F (Bit 8) */ -#define CCU8_CC8_DC2R_DT2F_Msk \ - (0xff00UL) /*!< CCU8_CC8 DC2R: DT2F (Bitfield-Mask: 0xff) */ - -/* ------------------------------- CCU8_CC8_TIMER ------------------------------- */ -#define CCU8_CC8_TIMER_TVAL_Pos \ - (0UL) /*!< CCU8_CC8 TIMER: TVAL (Bit 0) */ -#define CCU8_CC8_TIMER_TVAL_Msk \ - (0xffffUL) /*!< CCU8_CC8 TIMER: TVAL (Bitfield-Mask: 0xffff) */ - -/* --------------------------------- CCU8_CC8_CV -------------------------------- */ -#define CCU8_CC8_CV_CAPTV_Pos \ - (0UL) /*!< CCU8_CC8 CV: CAPTV (Bit 0) */ -#define CCU8_CC8_CV_CAPTV_Msk \ - (0xffffUL) /*!< CCU8_CC8 CV: CAPTV (Bitfield-Mask: 0xffff) */ -#define CCU8_CC8_CV_FPCV_Pos \ - (16UL) /*!< CCU8_CC8 CV: FPCV (Bit 16) */ -#define CCU8_CC8_CV_FPCV_Msk \ - (0xf0000UL) /*!< CCU8_CC8 CV: FPCV (Bitfield-Mask: 0x0f) */ -#define CCU8_CC8_CV_FFL_Pos \ - (20UL) /*!< CCU8_CC8 CV: FFL (Bit 20) */ -#define CCU8_CC8_CV_FFL_Msk \ - (0x100000UL) /*!< CCU8_CC8 CV: FFL (Bitfield-Mask: 0x01) */ - -/* -------------------------------- CCU8_CC8_INTS ------------------------------- */ -#define CCU8_CC8_INTS_PMUS_Pos \ - (0UL) /*!< CCU8_CC8 INTS: PMUS (Bit 0) */ -#define CCU8_CC8_INTS_PMUS_Msk \ - (0x1UL) /*!< CCU8_CC8 INTS: PMUS (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_INTS_OMDS_Pos \ - (1UL) /*!< CCU8_CC8 INTS: OMDS (Bit 1) */ -#define CCU8_CC8_INTS_OMDS_Msk \ - (0x2UL) /*!< CCU8_CC8 INTS: OMDS (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_INTS_CMU1S_Pos \ - (2UL) /*!< CCU8_CC8 INTS: CMU1S (Bit 2) */ -#define CCU8_CC8_INTS_CMU1S_Msk \ - (0x4UL) /*!< CCU8_CC8 INTS: CMU1S (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_INTS_CMD1S_Pos \ - (3UL) /*!< CCU8_CC8 INTS: CMD1S (Bit 3) */ -#define CCU8_CC8_INTS_CMD1S_Msk \ - (0x8UL) /*!< CCU8_CC8 INTS: CMD1S (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_INTS_CMU2S_Pos \ - (4UL) /*!< CCU8_CC8 INTS: CMU2S (Bit 4) */ -#define CCU8_CC8_INTS_CMU2S_Msk \ - (0x10UL) /*!< CCU8_CC8 INTS: CMU2S (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_INTS_CMD2S_Pos \ - (5UL) /*!< CCU8_CC8 INTS: CMD2S (Bit 5) */ -#define CCU8_CC8_INTS_CMD2S_Msk \ - (0x20UL) /*!< CCU8_CC8 INTS: CMD2S (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_INTS_E0AS_Pos \ - (8UL) /*!< CCU8_CC8 INTS: E0AS (Bit 8) */ -#define CCU8_CC8_INTS_E0AS_Msk \ - (0x100UL) /*!< CCU8_CC8 INTS: E0AS (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_INTS_E1AS_Pos \ - (9UL) /*!< CCU8_CC8 INTS: E1AS (Bit 9) */ -#define CCU8_CC8_INTS_E1AS_Msk \ - (0x200UL) /*!< CCU8_CC8 INTS: E1AS (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_INTS_E2AS_Pos \ - (10UL) /*!< CCU8_CC8 INTS: E2AS (Bit 10) */ -#define CCU8_CC8_INTS_E2AS_Msk \ - (0x400UL) /*!< CCU8_CC8 INTS: E2AS (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_INTS_TRPF_Pos \ - (11UL) /*!< CCU8_CC8 INTS: TRPF (Bit 11) */ -#define CCU8_CC8_INTS_TRPF_Msk \ - (0x800UL) /*!< CCU8_CC8 INTS: TRPF (Bitfield-Mask: 0x01) */ - -/* -------------------------------- CCU8_CC8_INTE ------------------------------- */ -#define CCU8_CC8_INTE_PME_Pos \ - (0UL) /*!< CCU8_CC8 INTE: PME (Bit 0) */ -#define CCU8_CC8_INTE_PME_Msk \ - (0x1UL) /*!< CCU8_CC8 INTE: PME (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_INTE_OME_Pos \ - (1UL) /*!< CCU8_CC8 INTE: OME (Bit 1) */ -#define CCU8_CC8_INTE_OME_Msk \ - (0x2UL) /*!< CCU8_CC8 INTE: OME (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_INTE_CMU1E_Pos \ - (2UL) /*!< CCU8_CC8 INTE: CMU1E (Bit 2) */ -#define CCU8_CC8_INTE_CMU1E_Msk \ - (0x4UL) /*!< CCU8_CC8 INTE: CMU1E (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_INTE_CMD1E_Pos \ - (3UL) /*!< CCU8_CC8 INTE: CMD1E (Bit 3) */ -#define CCU8_CC8_INTE_CMD1E_Msk \ - (0x8UL) /*!< CCU8_CC8 INTE: CMD1E (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_INTE_CMU2E_Pos \ - (4UL) /*!< CCU8_CC8 INTE: CMU2E (Bit 4) */ -#define CCU8_CC8_INTE_CMU2E_Msk \ - (0x10UL) /*!< CCU8_CC8 INTE: CMU2E (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_INTE_CMD2E_Pos \ - (5UL) /*!< CCU8_CC8 INTE: CMD2E (Bit 5) */ -#define CCU8_CC8_INTE_CMD2E_Msk \ - (0x20UL) /*!< CCU8_CC8 INTE: CMD2E (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_INTE_E0AE_Pos \ - (8UL) /*!< CCU8_CC8 INTE: E0AE (Bit 8) */ -#define CCU8_CC8_INTE_E0AE_Msk \ - (0x100UL) /*!< CCU8_CC8 INTE: E0AE (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_INTE_E1AE_Pos \ - (9UL) /*!< CCU8_CC8 INTE: E1AE (Bit 9) */ -#define CCU8_CC8_INTE_E1AE_Msk \ - (0x200UL) /*!< CCU8_CC8 INTE: E1AE (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_INTE_E2AE_Pos \ - (10UL) /*!< CCU8_CC8 INTE: E2AE (Bit 10) */ -#define CCU8_CC8_INTE_E2AE_Msk \ - (0x400UL) /*!< CCU8_CC8 INTE: E2AE (Bitfield-Mask: 0x01) */ - -/* -------------------------------- CCU8_CC8_SRS -------------------------------- */ -#define CCU8_CC8_SRS_POSR_Pos \ - (0UL) /*!< CCU8_CC8 SRS: POSR (Bit 0) */ -#define CCU8_CC8_SRS_POSR_Msk \ - (0x3UL) /*!< CCU8_CC8 SRS: POSR (Bitfield-Mask: 0x03) */ -#define CCU8_CC8_SRS_CM1SR_Pos \ - (2UL) /*!< CCU8_CC8 SRS: CM1SR (Bit 2) */ -#define CCU8_CC8_SRS_CM1SR_Msk \ - (0xcUL) /*!< CCU8_CC8 SRS: CM1SR (Bitfield-Mask: 0x03) */ -#define CCU8_CC8_SRS_CM2SR_Pos \ - (4UL) /*!< CCU8_CC8 SRS: CM2SR (Bit 4) */ -#define CCU8_CC8_SRS_CM2SR_Msk \ - (0x30UL) /*!< CCU8_CC8 SRS: CM2SR (Bitfield-Mask: 0x03) */ -#define CCU8_CC8_SRS_E0SR_Pos \ - (8UL) /*!< CCU8_CC8 SRS: E0SR (Bit 8) */ -#define CCU8_CC8_SRS_E0SR_Msk \ - (0x300UL) /*!< CCU8_CC8 SRS: E0SR (Bitfield-Mask: 0x03) */ -#define CCU8_CC8_SRS_E1SR_Pos \ - (10UL) /*!< CCU8_CC8 SRS: E1SR (Bit 10) */ -#define CCU8_CC8_SRS_E1SR_Msk \ - (0xc00UL) /*!< CCU8_CC8 SRS: E1SR (Bitfield-Mask: 0x03) */ -#define CCU8_CC8_SRS_E2SR_Pos \ - (12UL) /*!< CCU8_CC8 SRS: E2SR (Bit 12) */ -#define CCU8_CC8_SRS_E2SR_Msk \ - (0x3000UL) /*!< CCU8_CC8 SRS: E2SR (Bitfield-Mask: 0x03) */ - -/* -------------------------------- CCU8_CC8_SWS -------------------------------- */ -#define CCU8_CC8_SWS_SPM_Pos \ - (0UL) /*!< CCU8_CC8 SWS: SPM (Bit 0) */ -#define CCU8_CC8_SWS_SPM_Msk \ - (0x1UL) /*!< CCU8_CC8 SWS: SPM (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_SWS_SOM_Pos \ - (1UL) /*!< CCU8_CC8 SWS: SOM (Bit 1) */ -#define CCU8_CC8_SWS_SOM_Msk \ - (0x2UL) /*!< CCU8_CC8 SWS: SOM (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_SWS_SCM1U_Pos \ - (2UL) /*!< CCU8_CC8 SWS: SCM1U (Bit 2) */ -#define CCU8_CC8_SWS_SCM1U_Msk \ - (0x4UL) /*!< CCU8_CC8 SWS: SCM1U (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_SWS_SCM1D_Pos \ - (3UL) /*!< CCU8_CC8 SWS: SCM1D (Bit 3) */ -#define CCU8_CC8_SWS_SCM1D_Msk \ - (0x8UL) /*!< CCU8_CC8 SWS: SCM1D (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_SWS_SCM2U_Pos \ - (4UL) /*!< CCU8_CC8 SWS: SCM2U (Bit 4) */ -#define CCU8_CC8_SWS_SCM2U_Msk \ - (0x10UL) /*!< CCU8_CC8 SWS: SCM2U (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_SWS_SCM2D_Pos \ - (5UL) /*!< CCU8_CC8 SWS: SCM2D (Bit 5) */ -#define CCU8_CC8_SWS_SCM2D_Msk \ - (0x20UL) /*!< CCU8_CC8 SWS: SCM2D (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_SWS_SE0A_Pos \ - (8UL) /*!< CCU8_CC8 SWS: SE0A (Bit 8) */ -#define CCU8_CC8_SWS_SE0A_Msk \ - (0x100UL) /*!< CCU8_CC8 SWS: SE0A (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_SWS_SE1A_Pos \ - (9UL) /*!< CCU8_CC8 SWS: SE1A (Bit 9) */ -#define CCU8_CC8_SWS_SE1A_Msk \ - (0x200UL) /*!< CCU8_CC8 SWS: SE1A (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_SWS_SE2A_Pos \ - (10UL) /*!< CCU8_CC8 SWS: SE2A (Bit 10) */ -#define CCU8_CC8_SWS_SE2A_Msk \ - (0x400UL) /*!< CCU8_CC8 SWS: SE2A (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_SWS_STRPF_Pos \ - (11UL) /*!< CCU8_CC8 SWS: STRPF (Bit 11) */ -#define CCU8_CC8_SWS_STRPF_Msk \ - (0x800UL) /*!< CCU8_CC8 SWS: STRPF (Bitfield-Mask: 0x01) */ - -/* -------------------------------- CCU8_CC8_SWR -------------------------------- */ -#define CCU8_CC8_SWR_RPM_Pos \ - (0UL) /*!< CCU8_CC8 SWR: RPM (Bit 0) */ -#define CCU8_CC8_SWR_RPM_Msk \ - (0x1UL) /*!< CCU8_CC8 SWR: RPM (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_SWR_ROM_Pos \ - (1UL) /*!< CCU8_CC8 SWR: ROM (Bit 1) */ -#define CCU8_CC8_SWR_ROM_Msk \ - (0x2UL) /*!< CCU8_CC8 SWR: ROM (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_SWR_RCM1U_Pos \ - (2UL) /*!< CCU8_CC8 SWR: RCM1U (Bit 2) */ -#define CCU8_CC8_SWR_RCM1U_Msk \ - (0x4UL) /*!< CCU8_CC8 SWR: RCM1U (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_SWR_RCM1D_Pos \ - (3UL) /*!< CCU8_CC8 SWR: RCM1D (Bit 3) */ -#define CCU8_CC8_SWR_RCM1D_Msk \ - (0x8UL) /*!< CCU8_CC8 SWR: RCM1D (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_SWR_RCM2U_Pos \ - (4UL) /*!< CCU8_CC8 SWR: RCM2U (Bit 4) */ -#define CCU8_CC8_SWR_RCM2U_Msk \ - (0x10UL) /*!< CCU8_CC8 SWR: RCM2U (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_SWR_RCM2D_Pos \ - (5UL) /*!< CCU8_CC8 SWR: RCM2D (Bit 5) */ -#define CCU8_CC8_SWR_RCM2D_Msk \ - (0x20UL) /*!< CCU8_CC8 SWR: RCM2D (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_SWR_RE0A_Pos \ - (8UL) /*!< CCU8_CC8 SWR: RE0A (Bit 8) */ -#define CCU8_CC8_SWR_RE0A_Msk \ - (0x100UL) /*!< CCU8_CC8 SWR: RE0A (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_SWR_RE1A_Pos \ - (9UL) /*!< CCU8_CC8 SWR: RE1A (Bit 9) */ -#define CCU8_CC8_SWR_RE1A_Msk \ - (0x200UL) /*!< CCU8_CC8 SWR: RE1A (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_SWR_RE2A_Pos \ - (10UL) /*!< CCU8_CC8 SWR: RE2A (Bit 10) */ -#define CCU8_CC8_SWR_RE2A_Msk \ - (0x400UL) /*!< CCU8_CC8 SWR: RE2A (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_SWR_RTRPF_Pos \ - (11UL) /*!< CCU8_CC8 SWR: RTRPF (Bit 11) */ -#define CCU8_CC8_SWR_RTRPF_Msk \ - (0x800UL) /*!< CCU8_CC8 SWR: RTRPF (Bitfield-Mask: 0x01) */ - -/* -------------------------------- CCU8_CC8_STC -------------------------------- */ -#define CCU8_CC8_STC_CSE_Pos \ - (0UL) /*!< CCU8_CC8 STC: CSE (Bit 0) */ -#define CCU8_CC8_STC_CSE_Msk \ - (0x1UL) /*!< CCU8_CC8 STC: CSE (Bitfield-Mask: 0x01) */ -#define CCU8_CC8_STC_STM_Pos \ - (1UL) /*!< CCU8_CC8 STC: STM (Bit 1) */ -#define CCU8_CC8_STC_STM_Msk \ - (0x6UL) /*!< CCU8_CC8 STC: STM (Bitfield-Mask: 0x03) */ - -/* ================================================================================ */ -/* ================ struct 'HRPWM0' Position & Mask ================ */ -/* ================================================================================ */ - -/* -------------------------------- HRPWM0_HRBSC -------------------------------- */ -#define HRPWM0_HRBSC_SUSCFG_Pos \ - (0UL) /*!< HRPWM0 HRBSC: SUSCFG (Bit 0) */ -#define HRPWM0_HRBSC_SUSCFG_Msk \ - (0x7UL) /*!< HRPWM0 HRBSC: SUSCFG (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRBSC_HRBE_Pos \ - (8UL) /*!< HRPWM0 HRBSC: HRBE (Bit 8) */ -#define HRPWM0_HRBSC_HRBE_Msk \ - (0x100UL) /*!< HRPWM0 HRBSC: HRBE (Bitfield-Mask: 0x01) */ - -/* --------------------------------- HRPWM0_MIDR -------------------------------- */ -#define HRPWM0_MIDR_MODR_Pos \ - (0UL) /*!< HRPWM0 MIDR: MODR (Bit 0) */ -#define HRPWM0_MIDR_MODR_Msk \ - (0xffUL) /*!< HRPWM0 MIDR: MODR (Bitfield-Mask: 0xff) */ -#define HRPWM0_MIDR_MODT_Pos \ - (8UL) /*!< HRPWM0 MIDR: MODT (Bit 8) */ -#define HRPWM0_MIDR_MODT_Msk \ - (0xff00UL) /*!< HRPWM0 MIDR: MODT (Bitfield-Mask: 0xff) */ -#define HRPWM0_MIDR_MODN_Pos \ - (16UL) /*!< HRPWM0 MIDR: MODN (Bit 16) */ -#define HRPWM0_MIDR_MODN_Msk \ - (0xffff0000UL) /*!< HRPWM0 MIDR: MODN (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- HRPWM0_GLBANA ------------------------------- */ -#define HRPWM0_GLBANA_SLDLY_Pos \ - (0UL) /*!< HRPWM0 GLBANA: SLDLY (Bit 0) */ -#define HRPWM0_GLBANA_SLDLY_Msk \ - (0x3UL) /*!< HRPWM0 GLBANA: SLDLY (Bitfield-Mask: 0x03) */ -#define HRPWM0_GLBANA_FUP_Pos \ - (2UL) /*!< HRPWM0 GLBANA: FUP (Bit 2) */ -#define HRPWM0_GLBANA_FUP_Msk \ - (0x4UL) /*!< HRPWM0 GLBANA: FUP (Bitfield-Mask: 0x01) */ -#define HRPWM0_GLBANA_FDN_Pos \ - (3UL) /*!< HRPWM0 GLBANA: FDN (Bit 3) */ -#define HRPWM0_GLBANA_FDN_Msk \ - (0x8UL) /*!< HRPWM0 GLBANA: FDN (Bitfield-Mask: 0x01) */ -#define HRPWM0_GLBANA_SLCP_Pos \ - (6UL) /*!< HRPWM0 GLBANA: SLCP (Bit 6) */ -#define HRPWM0_GLBANA_SLCP_Msk \ - (0x1c0UL) /*!< HRPWM0 GLBANA: SLCP (Bitfield-Mask: 0x07) */ -#define HRPWM0_GLBANA_SLIBLDO_Pos \ - (9UL) /*!< HRPWM0 GLBANA: SLIBLDO (Bit 9) */ -#define HRPWM0_GLBANA_SLIBLDO_Msk \ - (0x600UL) /*!< HRPWM0 GLBANA: SLIBLDO (Bitfield-Mask: 0x03) */ -#define HRPWM0_GLBANA_SLIBLF_Pos \ - (11UL) /*!< HRPWM0 GLBANA: SLIBLF (Bit 11) */ -#define HRPWM0_GLBANA_SLIBLF_Msk \ - (0x1800UL) /*!< HRPWM0 GLBANA: SLIBLF (Bitfield-Mask: 0x03) */ -#define HRPWM0_GLBANA_SLVREF_Pos \ - (13UL) /*!< HRPWM0 GLBANA: SLVREF (Bit 13) */ -#define HRPWM0_GLBANA_SLVREF_Msk \ - (0xe000UL) /*!< HRPWM0 GLBANA: SLVREF (Bitfield-Mask: 0x07) */ -#define HRPWM0_GLBANA_TRIBIAS_Pos \ - (16UL) /*!< HRPWM0 GLBANA: TRIBIAS (Bit 16) */ -#define HRPWM0_GLBANA_TRIBIAS_Msk \ - (0x30000UL) /*!< HRPWM0 GLBANA: TRIBIAS (Bitfield-Mask: 0x03) */ -#define HRPWM0_GLBANA_GHREN_Pos \ - (18UL) /*!< HRPWM0 GLBANA: GHREN (Bit 18) */ -#define HRPWM0_GLBANA_GHREN_Msk \ - (0x40000UL) /*!< HRPWM0 GLBANA: GHREN (Bitfield-Mask: 0x01) */ - -/* -------------------------------- HRPWM0_CSGCFG ------------------------------- */ -#define HRPWM0_CSGCFG_C0PM_Pos \ - (0UL) /*!< HRPWM0 CSGCFG: C0PM (Bit 0) */ -#define HRPWM0_CSGCFG_C0PM_Msk \ - (0x3UL) /*!< HRPWM0 CSGCFG: C0PM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSGCFG_C1PM_Pos \ - (2UL) /*!< HRPWM0 CSGCFG: C1PM (Bit 2) */ -#define HRPWM0_CSGCFG_C1PM_Msk \ - (0xcUL) /*!< HRPWM0 CSGCFG: C1PM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSGCFG_C2PM_Pos \ - (4UL) /*!< HRPWM0 CSGCFG: C2PM (Bit 4) */ -#define HRPWM0_CSGCFG_C2PM_Msk \ - (0x30UL) /*!< HRPWM0 CSGCFG: C2PM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSGCFG_C0CD_Pos \ - (16UL) /*!< HRPWM0 CSGCFG: C0CD (Bit 16) */ -#define HRPWM0_CSGCFG_C0CD_Msk \ - (0x10000UL) /*!< HRPWM0 CSGCFG: C0CD (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGCFG_C1CD_Pos \ - (17UL) /*!< HRPWM0 CSGCFG: C1CD (Bit 17) */ -#define HRPWM0_CSGCFG_C1CD_Msk \ - (0x20000UL) /*!< HRPWM0 CSGCFG: C1CD (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGCFG_C2CD_Pos \ - (18UL) /*!< HRPWM0 CSGCFG: C2CD (Bit 18) */ -#define HRPWM0_CSGCFG_C2CD_Msk \ - (0x40000UL) /*!< HRPWM0 CSGCFG: C2CD (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_CSGSETG ------------------------------- */ -#define HRPWM0_CSGSETG_SD0R_Pos \ - (0UL) /*!< HRPWM0 CSGSETG: SD0R (Bit 0) */ -#define HRPWM0_CSGSETG_SD0R_Msk \ - (0x1UL) /*!< HRPWM0 CSGSETG: SD0R (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGSETG_SC0R_Pos \ - (1UL) /*!< HRPWM0 CSGSETG: SC0R (Bit 1) */ -#define HRPWM0_CSGSETG_SC0R_Msk \ - (0x2UL) /*!< HRPWM0 CSGSETG: SC0R (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGSETG_SC0P_Pos \ - (2UL) /*!< HRPWM0 CSGSETG: SC0P (Bit 2) */ -#define HRPWM0_CSGSETG_SC0P_Msk \ - (0x4UL) /*!< HRPWM0 CSGSETG: SC0P (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGSETG_SD1R_Pos \ - (4UL) /*!< HRPWM0 CSGSETG: SD1R (Bit 4) */ -#define HRPWM0_CSGSETG_SD1R_Msk \ - (0x10UL) /*!< HRPWM0 CSGSETG: SD1R (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGSETG_SC1R_Pos \ - (5UL) /*!< HRPWM0 CSGSETG: SC1R (Bit 5) */ -#define HRPWM0_CSGSETG_SC1R_Msk \ - (0x20UL) /*!< HRPWM0 CSGSETG: SC1R (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGSETG_SC1P_Pos \ - (6UL) /*!< HRPWM0 CSGSETG: SC1P (Bit 6) */ -#define HRPWM0_CSGSETG_SC1P_Msk \ - (0x40UL) /*!< HRPWM0 CSGSETG: SC1P (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGSETG_SD2R_Pos \ - (8UL) /*!< HRPWM0 CSGSETG: SD2R (Bit 8) */ -#define HRPWM0_CSGSETG_SD2R_Msk \ - (0x100UL) /*!< HRPWM0 CSGSETG: SD2R (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGSETG_SC2R_Pos \ - (9UL) /*!< HRPWM0 CSGSETG: SC2R (Bit 9) */ -#define HRPWM0_CSGSETG_SC2R_Msk \ - (0x200UL) /*!< HRPWM0 CSGSETG: SC2R (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGSETG_SC2P_Pos \ - (10UL) /*!< HRPWM0 CSGSETG: SC2P (Bit 10) */ -#define HRPWM0_CSGSETG_SC2P_Msk \ - (0x400UL) /*!< HRPWM0 CSGSETG: SC2P (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_CSGCLRG ------------------------------- */ -#define HRPWM0_CSGCLRG_CD0R_Pos \ - (0UL) /*!< HRPWM0 CSGCLRG: CD0R (Bit 0) */ -#define HRPWM0_CSGCLRG_CD0R_Msk \ - (0x1UL) /*!< HRPWM0 CSGCLRG: CD0R (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGCLRG_CC0R_Pos \ - (1UL) /*!< HRPWM0 CSGCLRG: CC0R (Bit 1) */ -#define HRPWM0_CSGCLRG_CC0R_Msk \ - (0x2UL) /*!< HRPWM0 CSGCLRG: CC0R (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGCLRG_CC0P_Pos \ - (2UL) /*!< HRPWM0 CSGCLRG: CC0P (Bit 2) */ -#define HRPWM0_CSGCLRG_CC0P_Msk \ - (0x4UL) /*!< HRPWM0 CSGCLRG: CC0P (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGCLRG_CD1R_Pos \ - (4UL) /*!< HRPWM0 CSGCLRG: CD1R (Bit 4) */ -#define HRPWM0_CSGCLRG_CD1R_Msk \ - (0x10UL) /*!< HRPWM0 CSGCLRG: CD1R (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGCLRG_CC1R_Pos \ - (5UL) /*!< HRPWM0 CSGCLRG: CC1R (Bit 5) */ -#define HRPWM0_CSGCLRG_CC1R_Msk \ - (0x20UL) /*!< HRPWM0 CSGCLRG: CC1R (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGCLRG_CC1P_Pos \ - (6UL) /*!< HRPWM0 CSGCLRG: CC1P (Bit 6) */ -#define HRPWM0_CSGCLRG_CC1P_Msk \ - (0x40UL) /*!< HRPWM0 CSGCLRG: CC1P (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGCLRG_CD2R_Pos \ - (8UL) /*!< HRPWM0 CSGCLRG: CD2R (Bit 8) */ -#define HRPWM0_CSGCLRG_CD2R_Msk \ - (0x100UL) /*!< HRPWM0 CSGCLRG: CD2R (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGCLRG_CC2R_Pos \ - (9UL) /*!< HRPWM0 CSGCLRG: CC2R (Bit 9) */ -#define HRPWM0_CSGCLRG_CC2R_Msk \ - (0x200UL) /*!< HRPWM0 CSGCLRG: CC2R (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGCLRG_CC2P_Pos \ - (10UL) /*!< HRPWM0 CSGCLRG: CC2P (Bit 10) */ -#define HRPWM0_CSGCLRG_CC2P_Msk \ - (0x400UL) /*!< HRPWM0 CSGCLRG: CC2P (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_CSGSTATG ------------------------------ */ -#define HRPWM0_CSGSTATG_D0RB_Pos \ - (0UL) /*!< HRPWM0 CSGSTATG: D0RB (Bit 0) */ -#define HRPWM0_CSGSTATG_D0RB_Msk \ - (0x1UL) /*!< HRPWM0 CSGSTATG: D0RB (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGSTATG_C0RB_Pos \ - (1UL) /*!< HRPWM0 CSGSTATG: C0RB (Bit 1) */ -#define HRPWM0_CSGSTATG_C0RB_Msk \ - (0x2UL) /*!< HRPWM0 CSGSTATG: C0RB (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGSTATG_PSLS0_Pos \ - (2UL) /*!< HRPWM0 CSGSTATG: PSLS0 (Bit 2) */ -#define HRPWM0_CSGSTATG_PSLS0_Msk \ - (0x4UL) /*!< HRPWM0 CSGSTATG: PSLS0 (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGSTATG_D1RB_Pos \ - (4UL) /*!< HRPWM0 CSGSTATG: D1RB (Bit 4) */ -#define HRPWM0_CSGSTATG_D1RB_Msk \ - (0x10UL) /*!< HRPWM0 CSGSTATG: D1RB (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGSTATG_C1RB_Pos \ - (5UL) /*!< HRPWM0 CSGSTATG: C1RB (Bit 5) */ -#define HRPWM0_CSGSTATG_C1RB_Msk \ - (0x20UL) /*!< HRPWM0 CSGSTATG: C1RB (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGSTATG_PSLS1_Pos \ - (6UL) /*!< HRPWM0 CSGSTATG: PSLS1 (Bit 6) */ -#define HRPWM0_CSGSTATG_PSLS1_Msk \ - (0x40UL) /*!< HRPWM0 CSGSTATG: PSLS1 (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGSTATG_D2RB_Pos \ - (8UL) /*!< HRPWM0 CSGSTATG: D2RB (Bit 8) */ -#define HRPWM0_CSGSTATG_D2RB_Msk \ - (0x100UL) /*!< HRPWM0 CSGSTATG: D2RB (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGSTATG_C2RB_Pos \ - (9UL) /*!< HRPWM0 CSGSTATG: C2RB (Bit 9) */ -#define HRPWM0_CSGSTATG_C2RB_Msk \ - (0x200UL) /*!< HRPWM0 CSGSTATG: C2RB (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGSTATG_PSLS2_Pos \ - (10UL) /*!< HRPWM0 CSGSTATG: PSLS2 (Bit 10) */ -#define HRPWM0_CSGSTATG_PSLS2_Msk \ - (0x400UL) /*!< HRPWM0 CSGSTATG: PSLS2 (Bitfield-Mask: 0x01) */ - -/* -------------------------------- HRPWM0_CSGFCG ------------------------------- */ -#define HRPWM0_CSGFCG_S0STR_Pos \ - (0UL) /*!< HRPWM0 CSGFCG: S0STR (Bit 0) */ -#define HRPWM0_CSGFCG_S0STR_Msk \ - (0x1UL) /*!< HRPWM0 CSGFCG: S0STR (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGFCG_S0STP_Pos \ - (1UL) /*!< HRPWM0 CSGFCG: S0STP (Bit 1) */ -#define HRPWM0_CSGFCG_S0STP_Msk \ - (0x2UL) /*!< HRPWM0 CSGFCG: S0STP (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGFCG_PS0STR_Pos \ - (2UL) /*!< HRPWM0 CSGFCG: PS0STR (Bit 2) */ -#define HRPWM0_CSGFCG_PS0STR_Msk \ - (0x4UL) /*!< HRPWM0 CSGFCG: PS0STR (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGFCG_PS0STP_Pos \ - (3UL) /*!< HRPWM0 CSGFCG: PS0STP (Bit 3) */ -#define HRPWM0_CSGFCG_PS0STP_Msk \ - (0x8UL) /*!< HRPWM0 CSGFCG: PS0STP (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGFCG_PS0CLR_Pos \ - (4UL) /*!< HRPWM0 CSGFCG: PS0CLR (Bit 4) */ -#define HRPWM0_CSGFCG_PS0CLR_Msk \ - (0x10UL) /*!< HRPWM0 CSGFCG: PS0CLR (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGFCG_S1STR_Pos \ - (8UL) /*!< HRPWM0 CSGFCG: S1STR (Bit 8) */ -#define HRPWM0_CSGFCG_S1STR_Msk \ - (0x100UL) /*!< HRPWM0 CSGFCG: S1STR (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGFCG_S1STP_Pos \ - (9UL) /*!< HRPWM0 CSGFCG: S1STP (Bit 9) */ -#define HRPWM0_CSGFCG_S1STP_Msk \ - (0x200UL) /*!< HRPWM0 CSGFCG: S1STP (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGFCG_PS1STR_Pos \ - (10UL) /*!< HRPWM0 CSGFCG: PS1STR (Bit 10) */ -#define HRPWM0_CSGFCG_PS1STR_Msk \ - (0x400UL) /*!< HRPWM0 CSGFCG: PS1STR (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGFCG_PS1STP_Pos \ - (11UL) /*!< HRPWM0 CSGFCG: PS1STP (Bit 11) */ -#define HRPWM0_CSGFCG_PS1STP_Msk \ - (0x800UL) /*!< HRPWM0 CSGFCG: PS1STP (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGFCG_PS1CLR_Pos \ - (12UL) /*!< HRPWM0 CSGFCG: PS1CLR (Bit 12) */ -#define HRPWM0_CSGFCG_PS1CLR_Msk \ - (0x1000UL) /*!< HRPWM0 CSGFCG: PS1CLR (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGFCG_S2STR_Pos \ - (16UL) /*!< HRPWM0 CSGFCG: S2STR (Bit 16) */ -#define HRPWM0_CSGFCG_S2STR_Msk \ - (0x10000UL) /*!< HRPWM0 CSGFCG: S2STR (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGFCG_S2STP_Pos \ - (17UL) /*!< HRPWM0 CSGFCG: S2STP (Bit 17) */ -#define HRPWM0_CSGFCG_S2STP_Msk \ - (0x20000UL) /*!< HRPWM0 CSGFCG: S2STP (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGFCG_PS2STR_Pos \ - (18UL) /*!< HRPWM0 CSGFCG: PS2STR (Bit 18) */ -#define HRPWM0_CSGFCG_PS2STR_Msk \ - (0x40000UL) /*!< HRPWM0 CSGFCG: PS2STR (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGFCG_PS2STP_Pos \ - (19UL) /*!< HRPWM0 CSGFCG: PS2STP (Bit 19) */ -#define HRPWM0_CSGFCG_PS2STP_Msk \ - (0x80000UL) /*!< HRPWM0 CSGFCG: PS2STP (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGFCG_PS2CLR_Pos \ - (20UL) /*!< HRPWM0 CSGFCG: PS2CLR (Bit 20) */ -#define HRPWM0_CSGFCG_PS2CLR_Msk \ - (0x100000UL) /*!< HRPWM0 CSGFCG: PS2CLR (Bitfield-Mask: 0x01) */ - -/* -------------------------------- HRPWM0_CSGFSG ------------------------------- */ -#define HRPWM0_CSGFSG_S0RB_Pos \ - (0UL) /*!< HRPWM0 CSGFSG: S0RB (Bit 0) */ -#define HRPWM0_CSGFSG_S0RB_Msk \ - (0x1UL) /*!< HRPWM0 CSGFSG: S0RB (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGFSG_P0RB_Pos \ - (1UL) /*!< HRPWM0 CSGFSG: P0RB (Bit 1) */ -#define HRPWM0_CSGFSG_P0RB_Msk \ - (0x2UL) /*!< HRPWM0 CSGFSG: P0RB (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGFSG_S1RB_Pos \ - (8UL) /*!< HRPWM0 CSGFSG: S1RB (Bit 8) */ -#define HRPWM0_CSGFSG_S1RB_Msk \ - (0x100UL) /*!< HRPWM0 CSGFSG: S1RB (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGFSG_P1RB_Pos \ - (9UL) /*!< HRPWM0 CSGFSG: P1RB (Bit 9) */ -#define HRPWM0_CSGFSG_P1RB_Msk \ - (0x200UL) /*!< HRPWM0 CSGFSG: P1RB (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGFSG_S2RB_Pos \ - (16UL) /*!< HRPWM0 CSGFSG: S2RB (Bit 16) */ -#define HRPWM0_CSGFSG_S2RB_Msk \ - (0x10000UL) /*!< HRPWM0 CSGFSG: S2RB (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGFSG_P2RB_Pos \ - (17UL) /*!< HRPWM0 CSGFSG: P2RB (Bit 17) */ -#define HRPWM0_CSGFSG_P2RB_Msk \ - (0x20000UL) /*!< HRPWM0 CSGFSG: P2RB (Bitfield-Mask: 0x01) */ - -/* -------------------------------- HRPWM0_CSGTRG ------------------------------- */ -#define HRPWM0_CSGTRG_D0SES_Pos \ - (0UL) /*!< HRPWM0 CSGTRG: D0SES (Bit 0) */ -#define HRPWM0_CSGTRG_D0SES_Msk \ - (0x1UL) /*!< HRPWM0 CSGTRG: D0SES (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGTRG_D0SVS_Pos \ - (1UL) /*!< HRPWM0 CSGTRG: D0SVS (Bit 1) */ -#define HRPWM0_CSGTRG_D0SVS_Msk \ - (0x2UL) /*!< HRPWM0 CSGTRG: D0SVS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGTRG_D1SES_Pos \ - (4UL) /*!< HRPWM0 CSGTRG: D1SES (Bit 4) */ -#define HRPWM0_CSGTRG_D1SES_Msk \ - (0x10UL) /*!< HRPWM0 CSGTRG: D1SES (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGTRG_D1SVS_Pos \ - (5UL) /*!< HRPWM0 CSGTRG: D1SVS (Bit 5) */ -#define HRPWM0_CSGTRG_D1SVS_Msk \ - (0x20UL) /*!< HRPWM0 CSGTRG: D1SVS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGTRG_D2SES_Pos \ - (8UL) /*!< HRPWM0 CSGTRG: D2SES (Bit 8) */ -#define HRPWM0_CSGTRG_D2SES_Msk \ - (0x100UL) /*!< HRPWM0 CSGTRG: D2SES (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGTRG_D2SVS_Pos \ - (9UL) /*!< HRPWM0 CSGTRG: D2SVS (Bit 9) */ -#define HRPWM0_CSGTRG_D2SVS_Msk \ - (0x200UL) /*!< HRPWM0 CSGTRG: D2SVS (Bitfield-Mask: 0x01) */ - -/* -------------------------------- HRPWM0_CSGTRC ------------------------------- */ -#define HRPWM0_CSGTRC_D0SEC_Pos \ - (0UL) /*!< HRPWM0 CSGTRC: D0SEC (Bit 0) */ -#define HRPWM0_CSGTRC_D0SEC_Msk \ - (0x1UL) /*!< HRPWM0 CSGTRC: D0SEC (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGTRC_D1SEC_Pos \ - (4UL) /*!< HRPWM0 CSGTRC: D1SEC (Bit 4) */ -#define HRPWM0_CSGTRC_D1SEC_Msk \ - (0x10UL) /*!< HRPWM0 CSGTRC: D1SEC (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGTRC_D2SEC_Pos \ - (8UL) /*!< HRPWM0 CSGTRC: D2SEC (Bit 8) */ -#define HRPWM0_CSGTRC_D2SEC_Msk \ - (0x100UL) /*!< HRPWM0 CSGTRC: D2SEC (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_CSGTRSG ------------------------------- */ -#define HRPWM0_CSGTRSG_D0STE_Pos \ - (0UL) /*!< HRPWM0 CSGTRSG: D0STE (Bit 0) */ -#define HRPWM0_CSGTRSG_D0STE_Msk \ - (0x1UL) /*!< HRPWM0 CSGTRSG: D0STE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGTRSG_SW0ST_Pos \ - (1UL) /*!< HRPWM0 CSGTRSG: SW0ST (Bit 1) */ -#define HRPWM0_CSGTRSG_SW0ST_Msk \ - (0x2UL) /*!< HRPWM0 CSGTRSG: SW0ST (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGTRSG_D1STE_Pos \ - (4UL) /*!< HRPWM0 CSGTRSG: D1STE (Bit 4) */ -#define HRPWM0_CSGTRSG_D1STE_Msk \ - (0x10UL) /*!< HRPWM0 CSGTRSG: D1STE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGTRSG_SW1ST_Pos \ - (5UL) /*!< HRPWM0 CSGTRSG: SW1ST (Bit 5) */ -#define HRPWM0_CSGTRSG_SW1ST_Msk \ - (0x20UL) /*!< HRPWM0 CSGTRSG: SW1ST (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGTRSG_D2STE_Pos \ - (8UL) /*!< HRPWM0 CSGTRSG: D2STE (Bit 8) */ -#define HRPWM0_CSGTRSG_D2STE_Msk \ - (0x100UL) /*!< HRPWM0 CSGTRSG: D2STE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSGTRSG_SW2ST_Pos \ - (9UL) /*!< HRPWM0 CSGTRSG: SW2ST (Bit 9) */ -#define HRPWM0_CSGTRSG_SW2ST_Msk \ - (0x200UL) /*!< HRPWM0 CSGTRSG: SW2ST (Bitfield-Mask: 0x01) */ - -/* -------------------------------- HRPWM0_HRCCFG ------------------------------- */ -#define HRPWM0_HRCCFG_HRCPM_Pos \ - (0UL) /*!< HRPWM0 HRCCFG: HRCPM (Bit 0) */ -#define HRPWM0_HRCCFG_HRCPM_Msk \ - (0x1UL) /*!< HRPWM0 HRCCFG: HRCPM (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCCFG_HRC0E_Pos \ - (4UL) /*!< HRPWM0 HRCCFG: HRC0E (Bit 4) */ -#define HRPWM0_HRCCFG_HRC0E_Msk \ - (0x10UL) /*!< HRPWM0 HRCCFG: HRC0E (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCCFG_HRC1E_Pos \ - (5UL) /*!< HRPWM0 HRCCFG: HRC1E (Bit 5) */ -#define HRPWM0_HRCCFG_HRC1E_Msk \ - (0x20UL) /*!< HRPWM0 HRCCFG: HRC1E (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCCFG_HRC2E_Pos \ - (6UL) /*!< HRPWM0 HRCCFG: HRC2E (Bit 6) */ -#define HRPWM0_HRCCFG_HRC2E_Msk \ - (0x40UL) /*!< HRPWM0 HRCCFG: HRC2E (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCCFG_HRC3E_Pos \ - (7UL) /*!< HRPWM0 HRCCFG: HRC3E (Bit 7) */ -#define HRPWM0_HRCCFG_HRC3E_Msk \ - (0x80UL) /*!< HRPWM0 HRCCFG: HRC3E (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCCFG_CLKC_Pos \ - (16UL) /*!< HRPWM0 HRCCFG: CLKC (Bit 16) */ -#define HRPWM0_HRCCFG_CLKC_Msk \ - (0x70000UL) /*!< HRPWM0 HRCCFG: CLKC (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRCCFG_LRC0E_Pos \ - (20UL) /*!< HRPWM0 HRCCFG: LRC0E (Bit 20) */ -#define HRPWM0_HRCCFG_LRC0E_Msk \ - (0x100000UL) /*!< HRPWM0 HRCCFG: LRC0E (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCCFG_LRC1E_Pos \ - (21UL) /*!< HRPWM0 HRCCFG: LRC1E (Bit 21) */ -#define HRPWM0_HRCCFG_LRC1E_Msk \ - (0x200000UL) /*!< HRPWM0 HRCCFG: LRC1E (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCCFG_LRC2E_Pos \ - (22UL) /*!< HRPWM0 HRCCFG: LRC2E (Bit 22) */ -#define HRPWM0_HRCCFG_LRC2E_Msk \ - (0x400000UL) /*!< HRPWM0 HRCCFG: LRC2E (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCCFG_LRC3E_Pos \ - (23UL) /*!< HRPWM0 HRCCFG: LRC3E (Bit 23) */ -#define HRPWM0_HRCCFG_LRC3E_Msk \ - (0x800000UL) /*!< HRPWM0 HRCCFG: LRC3E (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_HRCSTRG ------------------------------- */ -#define HRPWM0_HRCSTRG_H0ES_Pos \ - (0UL) /*!< HRPWM0 HRCSTRG: H0ES (Bit 0) */ -#define HRPWM0_HRCSTRG_H0ES_Msk \ - (0x1UL) /*!< HRPWM0 HRCSTRG: H0ES (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCSTRG_H0DES_Pos \ - (1UL) /*!< HRPWM0 HRCSTRG: H0DES (Bit 1) */ -#define HRPWM0_HRCSTRG_H0DES_Msk \ - (0x2UL) /*!< HRPWM0 HRCSTRG: H0DES (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCSTRG_H1ES_Pos \ - (4UL) /*!< HRPWM0 HRCSTRG: H1ES (Bit 4) */ -#define HRPWM0_HRCSTRG_H1ES_Msk \ - (0x10UL) /*!< HRPWM0 HRCSTRG: H1ES (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCSTRG_H1DES_Pos \ - (5UL) /*!< HRPWM0 HRCSTRG: H1DES (Bit 5) */ -#define HRPWM0_HRCSTRG_H1DES_Msk \ - (0x20UL) /*!< HRPWM0 HRCSTRG: H1DES (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCSTRG_H2ES_Pos \ - (8UL) /*!< HRPWM0 HRCSTRG: H2ES (Bit 8) */ -#define HRPWM0_HRCSTRG_H2ES_Msk \ - (0x100UL) /*!< HRPWM0 HRCSTRG: H2ES (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCSTRG_H2DES_Pos \ - (9UL) /*!< HRPWM0 HRCSTRG: H2DES (Bit 9) */ -#define HRPWM0_HRCSTRG_H2DES_Msk \ - (0x200UL) /*!< HRPWM0 HRCSTRG: H2DES (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCSTRG_H3ES_Pos \ - (12UL) /*!< HRPWM0 HRCSTRG: H3ES (Bit 12) */ -#define HRPWM0_HRCSTRG_H3ES_Msk \ - (0x1000UL) /*!< HRPWM0 HRCSTRG: H3ES (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCSTRG_H3DES_Pos \ - (13UL) /*!< HRPWM0 HRCSTRG: H3DES (Bit 13) */ -#define HRPWM0_HRCSTRG_H3DES_Msk \ - (0x2000UL) /*!< HRPWM0 HRCSTRG: H3DES (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_HRCCTRG ------------------------------- */ -#define HRPWM0_HRCCTRG_H0EC_Pos \ - (0UL) /*!< HRPWM0 HRCCTRG: H0EC (Bit 0) */ -#define HRPWM0_HRCCTRG_H0EC_Msk \ - (0x1UL) /*!< HRPWM0 HRCCTRG: H0EC (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCCTRG_H0DEC_Pos \ - (1UL) /*!< HRPWM0 HRCCTRG: H0DEC (Bit 1) */ -#define HRPWM0_HRCCTRG_H0DEC_Msk \ - (0x2UL) /*!< HRPWM0 HRCCTRG: H0DEC (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCCTRG_H1EC_Pos \ - (4UL) /*!< HRPWM0 HRCCTRG: H1EC (Bit 4) */ -#define HRPWM0_HRCCTRG_H1EC_Msk \ - (0x10UL) /*!< HRPWM0 HRCCTRG: H1EC (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCCTRG_H1DEC_Pos \ - (5UL) /*!< HRPWM0 HRCCTRG: H1DEC (Bit 5) */ -#define HRPWM0_HRCCTRG_H1DEC_Msk \ - (0x20UL) /*!< HRPWM0 HRCCTRG: H1DEC (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCCTRG_H2CEC_Pos \ - (8UL) /*!< HRPWM0 HRCCTRG: H2CEC (Bit 8) */ -#define HRPWM0_HRCCTRG_H2CEC_Msk \ - (0x100UL) /*!< HRPWM0 HRCCTRG: H2CEC (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCCTRG_H2DEC_Pos \ - (9UL) /*!< HRPWM0 HRCCTRG: H2DEC (Bit 9) */ -#define HRPWM0_HRCCTRG_H2DEC_Msk \ - (0x200UL) /*!< HRPWM0 HRCCTRG: H2DEC (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCCTRG_H3EC_Pos \ - (12UL) /*!< HRPWM0 HRCCTRG: H3EC (Bit 12) */ -#define HRPWM0_HRCCTRG_H3EC_Msk \ - (0x1000UL) /*!< HRPWM0 HRCCTRG: H3EC (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCCTRG_H3DEC_Pos \ - (13UL) /*!< HRPWM0 HRCCTRG: H3DEC (Bit 13) */ -#define HRPWM0_HRCCTRG_H3DEC_Msk \ - (0x2000UL) /*!< HRPWM0 HRCCTRG: H3DEC (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_HRCSTSG ------------------------------- */ -#define HRPWM0_HRCSTSG_H0STE_Pos \ - (0UL) /*!< HRPWM0 HRCSTSG: H0STE (Bit 0) */ -#define HRPWM0_HRCSTSG_H0STE_Msk \ - (0x1UL) /*!< HRPWM0 HRCSTSG: H0STE (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCSTSG_H0DSTE_Pos \ - (1UL) /*!< HRPWM0 HRCSTSG: H0DSTE (Bit 1) */ -#define HRPWM0_HRCSTSG_H0DSTE_Msk \ - (0x2UL) /*!< HRPWM0 HRCSTSG: H0DSTE (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCSTSG_H1STE_Pos \ - (4UL) /*!< HRPWM0 HRCSTSG: H1STE (Bit 4) */ -#define HRPWM0_HRCSTSG_H1STE_Msk \ - (0x10UL) /*!< HRPWM0 HRCSTSG: H1STE (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCSTSG_H1DSTE_Pos \ - (5UL) /*!< HRPWM0 HRCSTSG: H1DSTE (Bit 5) */ -#define HRPWM0_HRCSTSG_H1DSTE_Msk \ - (0x20UL) /*!< HRPWM0 HRCSTSG: H1DSTE (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCSTSG_H2STE_Pos \ - (8UL) /*!< HRPWM0 HRCSTSG: H2STE (Bit 8) */ -#define HRPWM0_HRCSTSG_H2STE_Msk \ - (0x100UL) /*!< HRPWM0 HRCSTSG: H2STE (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCSTSG_H2DSTE_Pos \ - (9UL) /*!< HRPWM0 HRCSTSG: H2DSTE (Bit 9) */ -#define HRPWM0_HRCSTSG_H2DSTE_Msk \ - (0x200UL) /*!< HRPWM0 HRCSTSG: H2DSTE (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCSTSG_H3STE_Pos \ - (12UL) /*!< HRPWM0 HRCSTSG: H3STE (Bit 12) */ -#define HRPWM0_HRCSTSG_H3STE_Msk \ - (0x1000UL) /*!< HRPWM0 HRCSTSG: H3STE (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRCSTSG_H3DSTE_Pos \ - (13UL) /*!< HRPWM0 HRCSTSG: H3DSTE (Bit 13) */ -#define HRPWM0_HRCSTSG_H3DSTE_Msk \ - (0x2000UL) /*!< HRPWM0 HRCSTSG: H3DSTE (Bitfield-Mask: 0x01) */ - -/* -------------------------------- HRPWM0_HRGHRS ------------------------------- */ -#define HRPWM0_HRGHRS_HRGR_Pos \ - (0UL) /*!< HRPWM0 HRGHRS: HRGR (Bit 0) */ -#define HRPWM0_HRGHRS_HRGR_Msk \ - (0x1UL) /*!< HRPWM0 HRGHRS: HRGR (Bitfield-Mask: 0x01) */ - -/* ================================================================================ */ -/* ================ Group 'HRPWM0_CSG' Position & Mask ================ */ -/* ================================================================================ */ - -/* ------------------------------- HRPWM0_CSG_DCI ------------------------------- */ -#define HRPWM0_CSG_DCI_SVIS_Pos \ - (0UL) /*!< HRPWM0_CSG DCI: SVIS (Bit 0) */ -#define HRPWM0_CSG_DCI_SVIS_Msk \ - (0xfUL) /*!< HRPWM0_CSG DCI: SVIS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG_DCI_STRIS_Pos \ - (4UL) /*!< HRPWM0_CSG DCI: STRIS (Bit 4) */ -#define HRPWM0_CSG_DCI_STRIS_Msk \ - (0xf0UL) /*!< HRPWM0_CSG DCI: STRIS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG_DCI_STPIS_Pos \ - (8UL) /*!< HRPWM0_CSG DCI: STPIS (Bit 8) */ -#define HRPWM0_CSG_DCI_STPIS_Msk \ - (0xf00UL) /*!< HRPWM0_CSG DCI: STPIS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG_DCI_TRGIS_Pos \ - (12UL) /*!< HRPWM0_CSG DCI: TRGIS (Bit 12) */ -#define HRPWM0_CSG_DCI_TRGIS_Msk \ - (0xf000UL) /*!< HRPWM0_CSG DCI: TRGIS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG_DCI_STIS_Pos \ - (16UL) /*!< HRPWM0_CSG DCI: STIS (Bit 16) */ -#define HRPWM0_CSG_DCI_STIS_Msk \ - (0xf0000UL) /*!< HRPWM0_CSG DCI: STIS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG_DCI_SCS_Pos \ - (20UL) /*!< HRPWM0_CSG DCI: SCS (Bit 20) */ -#define HRPWM0_CSG_DCI_SCS_Msk \ - (0x300000UL) /*!< HRPWM0_CSG DCI: SCS (Bitfield-Mask: 0x03) */ - -/* ------------------------------- HRPWM0_CSG_IES ------------------------------- */ -#define HRPWM0_CSG_IES_SVLS_Pos \ - (0UL) /*!< HRPWM0_CSG IES: SVLS (Bit 0) */ -#define HRPWM0_CSG_IES_SVLS_Msk \ - (0x3UL) /*!< HRPWM0_CSG IES: SVLS (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG_IES_STRES_Pos \ - (2UL) /*!< HRPWM0_CSG IES: STRES (Bit 2) */ -#define HRPWM0_CSG_IES_STRES_Msk \ - (0xcUL) /*!< HRPWM0_CSG IES: STRES (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG_IES_STPES_Pos \ - (4UL) /*!< HRPWM0_CSG IES: STPES (Bit 4) */ -#define HRPWM0_CSG_IES_STPES_Msk \ - (0x30UL) /*!< HRPWM0_CSG IES: STPES (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG_IES_TRGES_Pos \ - (6UL) /*!< HRPWM0_CSG IES: TRGES (Bit 6) */ -#define HRPWM0_CSG_IES_TRGES_Msk \ - (0xc0UL) /*!< HRPWM0_CSG IES: TRGES (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG_IES_STES_Pos \ - (8UL) /*!< HRPWM0_CSG IES: STES (Bit 8) */ -#define HRPWM0_CSG_IES_STES_Msk \ - (0x300UL) /*!< HRPWM0_CSG IES: STES (Bitfield-Mask: 0x03) */ - -/* -------------------------------- HRPWM0_CSG_SC ------------------------------- */ -#define HRPWM0_CSG_SC_PSRM_Pos \ - (0UL) /*!< HRPWM0_CSG SC: PSRM (Bit 0) */ -#define HRPWM0_CSG_SC_PSRM_Msk \ - (0x3UL) /*!< HRPWM0_CSG SC: PSRM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG_SC_PSTM_Pos \ - (2UL) /*!< HRPWM0_CSG SC: PSTM (Bit 2) */ -#define HRPWM0_CSG_SC_PSTM_Msk \ - (0xcUL) /*!< HRPWM0_CSG SC: PSTM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG_SC_FPD_Pos \ - (4UL) /*!< HRPWM0_CSG SC: FPD (Bit 4) */ -#define HRPWM0_CSG_SC_FPD_Msk \ - (0x10UL) /*!< HRPWM0_CSG SC: FPD (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SC_PSV_Pos \ - (5UL) /*!< HRPWM0_CSG SC: PSV (Bit 5) */ -#define HRPWM0_CSG_SC_PSV_Msk \ - (0x60UL) /*!< HRPWM0_CSG SC: PSV (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG_SC_SCM_Pos \ - (8UL) /*!< HRPWM0_CSG SC: SCM (Bit 8) */ -#define HRPWM0_CSG_SC_SCM_Msk \ - (0x300UL) /*!< HRPWM0_CSG SC: SCM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG_SC_SSRM_Pos \ - (10UL) /*!< HRPWM0_CSG SC: SSRM (Bit 10) */ -#define HRPWM0_CSG_SC_SSRM_Msk \ - (0xc00UL) /*!< HRPWM0_CSG SC: SSRM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG_SC_SSTM_Pos \ - (12UL) /*!< HRPWM0_CSG SC: SSTM (Bit 12) */ -#define HRPWM0_CSG_SC_SSTM_Msk \ - (0x3000UL) /*!< HRPWM0_CSG SC: SSTM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG_SC_SVSC_Pos \ - (14UL) /*!< HRPWM0_CSG SC: SVSC (Bit 14) */ -#define HRPWM0_CSG_SC_SVSC_Msk \ - (0xc000UL) /*!< HRPWM0_CSG SC: SVSC (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG_SC_SWSM_Pos \ - (16UL) /*!< HRPWM0_CSG SC: SWSM (Bit 16) */ -#define HRPWM0_CSG_SC_SWSM_Msk \ - (0x30000UL) /*!< HRPWM0_CSG SC: SWSM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG_SC_GCFG_Pos \ - (18UL) /*!< HRPWM0_CSG SC: GCFG (Bit 18) */ -#define HRPWM0_CSG_SC_GCFG_Msk \ - (0xc0000UL) /*!< HRPWM0_CSG SC: GCFG (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG_SC_IST_Pos \ - (20UL) /*!< HRPWM0_CSG SC: IST (Bit 20) */ -#define HRPWM0_CSG_SC_IST_Msk \ - (0x100000UL) /*!< HRPWM0_CSG SC: IST (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SC_PSE_Pos \ - (21UL) /*!< HRPWM0_CSG SC: PSE (Bit 21) */ -#define HRPWM0_CSG_SC_PSE_Msk \ - (0x200000UL) /*!< HRPWM0_CSG SC: PSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SC_PSWM_Pos \ - (24UL) /*!< HRPWM0_CSG SC: PSWM (Bit 24) */ -#define HRPWM0_CSG_SC_PSWM_Msk \ - (0x3000000UL) /*!< HRPWM0_CSG SC: PSWM (Bitfield-Mask: 0x03) */ - -/* -------------------------------- HRPWM0_CSG_PC ------------------------------- */ -#define HRPWM0_CSG_PC_PSWV_Pos \ - (0UL) /*!< HRPWM0_CSG PC: PSWV (Bit 0) */ -#define HRPWM0_CSG_PC_PSWV_Msk \ - (0x3fUL) /*!< HRPWM0_CSG PC: PSWV (Bitfield-Mask: 0x3f) */ - -/* ------------------------------- HRPWM0_CSG_DSV1 ------------------------------ */ -#define HRPWM0_CSG_DSV1_DSV1_Pos \ - (0UL) /*!< HRPWM0_CSG DSV1: DSV1 (Bit 0) */ -#define HRPWM0_CSG_DSV1_DSV1_Msk \ - (0x3ffUL) /*!< HRPWM0_CSG DSV1: DSV1 (Bitfield-Mask: 0x3ff) */ - -/* ------------------------------- HRPWM0_CSG_DSV2 ------------------------------ */ -#define HRPWM0_CSG_DSV2_DSV2_Pos \ - (0UL) /*!< HRPWM0_CSG DSV2: DSV2 (Bit 0) */ -#define HRPWM0_CSG_DSV2_DSV2_Msk \ - (0x3ffUL) /*!< HRPWM0_CSG DSV2: DSV2 (Bitfield-Mask: 0x3ff) */ - -/* ------------------------------ HRPWM0_CSG_SDSV1 ------------------------------ */ -#define HRPWM0_CSG_SDSV1_SDSV1_Pos \ - (0UL) /*!< HRPWM0_CSG SDSV1: SDSV1 (Bit 0) */ -#define HRPWM0_CSG_SDSV1_SDSV1_Msk \ - (0x3ffUL) /*!< HRPWM0_CSG SDSV1: SDSV1 (Bitfield-Mask: 0x3ff) */ - -/* ------------------------------- HRPWM0_CSG_SPC ------------------------------- */ -#define HRPWM0_CSG_SPC_SPSWV_Pos \ - (0UL) /*!< HRPWM0_CSG SPC: SPSWV (Bit 0) */ -#define HRPWM0_CSG_SPC_SPSWV_Msk \ - (0x3fUL) /*!< HRPWM0_CSG SPC: SPSWV (Bitfield-Mask: 0x3f) */ - -/* -------------------------------- HRPWM0_CSG_CC ------------------------------- */ -#define HRPWM0_CSG_CC_IBS_Pos \ - (0UL) /*!< HRPWM0_CSG CC: IBS (Bit 0) */ -#define HRPWM0_CSG_CC_IBS_Msk \ - (0xfUL) /*!< HRPWM0_CSG CC: IBS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG_CC_IMCS_Pos \ - (8UL) /*!< HRPWM0_CSG CC: IMCS (Bit 8) */ -#define HRPWM0_CSG_CC_IMCS_Msk \ - (0x100UL) /*!< HRPWM0_CSG CC: IMCS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_CC_IMCC_Pos \ - (9UL) /*!< HRPWM0_CSG CC: IMCC (Bit 9) */ -#define HRPWM0_CSG_CC_IMCC_Msk \ - (0x600UL) /*!< HRPWM0_CSG CC: IMCC (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG_CC_ESE_Pos \ - (11UL) /*!< HRPWM0_CSG CC: ESE (Bit 11) */ -#define HRPWM0_CSG_CC_ESE_Msk \ - (0x800UL) /*!< HRPWM0_CSG CC: ESE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_CC_OIE_Pos \ - (12UL) /*!< HRPWM0_CSG CC: OIE (Bit 12) */ -#define HRPWM0_CSG_CC_OIE_Msk \ - (0x1000UL) /*!< HRPWM0_CSG CC: OIE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_CC_OSE_Pos \ - (13UL) /*!< HRPWM0_CSG CC: OSE (Bit 13) */ -#define HRPWM0_CSG_CC_OSE_Msk \ - (0x2000UL) /*!< HRPWM0_CSG CC: OSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_CC_BLMC_Pos \ - (14UL) /*!< HRPWM0_CSG CC: BLMC (Bit 14) */ -#define HRPWM0_CSG_CC_BLMC_Msk \ - (0xc000UL) /*!< HRPWM0_CSG CC: BLMC (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG_CC_EBE_Pos \ - (16UL) /*!< HRPWM0_CSG CC: EBE (Bit 16) */ -#define HRPWM0_CSG_CC_EBE_Msk \ - (0x10000UL) /*!< HRPWM0_CSG CC: EBE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_CC_COFE_Pos \ - (17UL) /*!< HRPWM0_CSG CC: COFE (Bit 17) */ -#define HRPWM0_CSG_CC_COFE_Msk \ - (0x20000UL) /*!< HRPWM0_CSG CC: COFE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_CC_COFM_Pos \ - (18UL) /*!< HRPWM0_CSG CC: COFM (Bit 18) */ -#define HRPWM0_CSG_CC_COFM_Msk \ - (0x3c0000UL) /*!< HRPWM0_CSG CC: COFM (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG_CC_COFC_Pos \ - (24UL) /*!< HRPWM0_CSG CC: COFC (Bit 24) */ -#define HRPWM0_CSG_CC_COFC_Msk \ - (0x3000000UL) /*!< HRPWM0_CSG CC: COFC (Bitfield-Mask: 0x03) */ - -/* ------------------------------- HRPWM0_CSG_PLC ------------------------------- */ -#define HRPWM0_CSG_PLC_IPLS_Pos \ - (0UL) /*!< HRPWM0_CSG PLC: IPLS (Bit 0) */ -#define HRPWM0_CSG_PLC_IPLS_Msk \ - (0xfUL) /*!< HRPWM0_CSG PLC: IPLS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG_PLC_PLCL_Pos \ - (8UL) /*!< HRPWM0_CSG PLC: PLCL (Bit 8) */ -#define HRPWM0_CSG_PLC_PLCL_Msk \ - (0x300UL) /*!< HRPWM0_CSG PLC: PLCL (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG_PLC_PSL_Pos \ - (10UL) /*!< HRPWM0_CSG PLC: PSL (Bit 10) */ -#define HRPWM0_CSG_PLC_PSL_Msk \ - (0x400UL) /*!< HRPWM0_CSG PLC: PSL (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_PLC_PLSW_Pos \ - (11UL) /*!< HRPWM0_CSG PLC: PLSW (Bit 11) */ -#define HRPWM0_CSG_PLC_PLSW_Msk \ - (0x800UL) /*!< HRPWM0_CSG PLC: PLSW (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_PLC_PLEC_Pos \ - (12UL) /*!< HRPWM0_CSG PLC: PLEC (Bit 12) */ -#define HRPWM0_CSG_PLC_PLEC_Msk \ - (0x3000UL) /*!< HRPWM0_CSG PLC: PLEC (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG_PLC_PLXC_Pos \ - (14UL) /*!< HRPWM0_CSG PLC: PLXC (Bit 14) */ -#define HRPWM0_CSG_PLC_PLXC_Msk \ - (0xc000UL) /*!< HRPWM0_CSG PLC: PLXC (Bitfield-Mask: 0x03) */ - -/* ------------------------------- HRPWM0_CSG_BLV ------------------------------- */ -#define HRPWM0_CSG_BLV_BLV_Pos \ - (0UL) /*!< HRPWM0_CSG BLV: BLV (Bit 0) */ -#define HRPWM0_CSG_BLV_BLV_Msk \ - (0xffUL) /*!< HRPWM0_CSG BLV: BLV (Bitfield-Mask: 0xff) */ - -/* ------------------------------- HRPWM0_CSG_SRE ------------------------------- */ -#define HRPWM0_CSG_SRE_VLS1E_Pos \ - (0UL) /*!< HRPWM0_CSG SRE: VLS1E (Bit 0) */ -#define HRPWM0_CSG_SRE_VLS1E_Msk \ - (0x1UL) /*!< HRPWM0_CSG SRE: VLS1E (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SRE_VLS2E_Pos \ - (1UL) /*!< HRPWM0_CSG SRE: VLS2E (Bit 1) */ -#define HRPWM0_CSG_SRE_VLS2E_Msk \ - (0x2UL) /*!< HRPWM0_CSG SRE: VLS2E (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SRE_TRGSE_Pos \ - (2UL) /*!< HRPWM0_CSG SRE: TRGSE (Bit 2) */ -#define HRPWM0_CSG_SRE_TRGSE_Msk \ - (0x4UL) /*!< HRPWM0_CSG SRE: TRGSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SRE_STRSE_Pos \ - (3UL) /*!< HRPWM0_CSG SRE: STRSE (Bit 3) */ -#define HRPWM0_CSG_SRE_STRSE_Msk \ - (0x8UL) /*!< HRPWM0_CSG SRE: STRSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SRE_STPSE_Pos \ - (4UL) /*!< HRPWM0_CSG SRE: STPSE (Bit 4) */ -#define HRPWM0_CSG_SRE_STPSE_Msk \ - (0x10UL) /*!< HRPWM0_CSG SRE: STPSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SRE_STDE_Pos \ - (5UL) /*!< HRPWM0_CSG SRE: STDE (Bit 5) */ -#define HRPWM0_CSG_SRE_STDE_Msk \ - (0x20UL) /*!< HRPWM0_CSG SRE: STDE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SRE_CRSE_Pos \ - (6UL) /*!< HRPWM0_CSG SRE: CRSE (Bit 6) */ -#define HRPWM0_CSG_SRE_CRSE_Msk \ - (0x40UL) /*!< HRPWM0_CSG SRE: CRSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SRE_CFSE_Pos \ - (7UL) /*!< HRPWM0_CSG SRE: CFSE (Bit 7) */ -#define HRPWM0_CSG_SRE_CFSE_Msk \ - (0x80UL) /*!< HRPWM0_CSG SRE: CFSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SRE_CSEE_Pos \ - (8UL) /*!< HRPWM0_CSG SRE: CSEE (Bit 8) */ -#define HRPWM0_CSG_SRE_CSEE_Msk \ - (0x100UL) /*!< HRPWM0_CSG SRE: CSEE (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_CSG_SRS ------------------------------- */ -#define HRPWM0_CSG_SRS_VLS1S_Pos \ - (0UL) /*!< HRPWM0_CSG SRS: VLS1S (Bit 0) */ -#define HRPWM0_CSG_SRS_VLS1S_Msk \ - (0x3UL) /*!< HRPWM0_CSG SRS: VLS1S (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG_SRS_VLS2S_Pos \ - (2UL) /*!< HRPWM0_CSG SRS: VLS2S (Bit 2) */ -#define HRPWM0_CSG_SRS_VLS2S_Msk \ - (0xcUL) /*!< HRPWM0_CSG SRS: VLS2S (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG_SRS_TRLS_Pos \ - (4UL) /*!< HRPWM0_CSG SRS: TRLS (Bit 4) */ -#define HRPWM0_CSG_SRS_TRLS_Msk \ - (0x30UL) /*!< HRPWM0_CSG SRS: TRLS (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG_SRS_SSLS_Pos \ - (6UL) /*!< HRPWM0_CSG SRS: SSLS (Bit 6) */ -#define HRPWM0_CSG_SRS_SSLS_Msk \ - (0xc0UL) /*!< HRPWM0_CSG SRS: SSLS (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG_SRS_STLS_Pos \ - (8UL) /*!< HRPWM0_CSG SRS: STLS (Bit 8) */ -#define HRPWM0_CSG_SRS_STLS_Msk \ - (0x300UL) /*!< HRPWM0_CSG SRS: STLS (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG_SRS_CRFLS_Pos \ - (10UL) /*!< HRPWM0_CSG SRS: CRFLS (Bit 10) */ -#define HRPWM0_CSG_SRS_CRFLS_Msk \ - (0xc00UL) /*!< HRPWM0_CSG SRS: CRFLS (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG_SRS_CSLS_Pos \ - (12UL) /*!< HRPWM0_CSG SRS: CSLS (Bit 12) */ -#define HRPWM0_CSG_SRS_CSLS_Msk \ - (0x3000UL) /*!< HRPWM0_CSG SRS: CSLS (Bitfield-Mask: 0x03) */ - -/* ------------------------------- HRPWM0_CSG_SWS ------------------------------- */ -#define HRPWM0_CSG_SWS_SVLS1_Pos \ - (0UL) /*!< HRPWM0_CSG SWS: SVLS1 (Bit 0) */ -#define HRPWM0_CSG_SWS_SVLS1_Msk \ - (0x1UL) /*!< HRPWM0_CSG SWS: SVLS1 (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SWS_SVLS2_Pos \ - (1UL) /*!< HRPWM0_CSG SWS: SVLS2 (Bit 1) */ -#define HRPWM0_CSG_SWS_SVLS2_Msk \ - (0x2UL) /*!< HRPWM0_CSG SWS: SVLS2 (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SWS_STRGS_Pos \ - (2UL) /*!< HRPWM0_CSG SWS: STRGS (Bit 2) */ -#define HRPWM0_CSG_SWS_STRGS_Msk \ - (0x4UL) /*!< HRPWM0_CSG SWS: STRGS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SWS_SSTRS_Pos \ - (3UL) /*!< HRPWM0_CSG SWS: SSTRS (Bit 3) */ -#define HRPWM0_CSG_SWS_SSTRS_Msk \ - (0x8UL) /*!< HRPWM0_CSG SWS: SSTRS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SWS_SSTPS_Pos \ - (4UL) /*!< HRPWM0_CSG SWS: SSTPS (Bit 4) */ -#define HRPWM0_CSG_SWS_SSTPS_Msk \ - (0x10UL) /*!< HRPWM0_CSG SWS: SSTPS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SWS_SSTD_Pos \ - (5UL) /*!< HRPWM0_CSG SWS: SSTD (Bit 5) */ -#define HRPWM0_CSG_SWS_SSTD_Msk \ - (0x20UL) /*!< HRPWM0_CSG SWS: SSTD (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SWS_SCRS_Pos \ - (6UL) /*!< HRPWM0_CSG SWS: SCRS (Bit 6) */ -#define HRPWM0_CSG_SWS_SCRS_Msk \ - (0x40UL) /*!< HRPWM0_CSG SWS: SCRS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SWS_SCFS_Pos \ - (7UL) /*!< HRPWM0_CSG SWS: SCFS (Bit 7) */ -#define HRPWM0_CSG_SWS_SCFS_Msk \ - (0x80UL) /*!< HRPWM0_CSG SWS: SCFS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SWS_SCSS_Pos \ - (8UL) /*!< HRPWM0_CSG SWS: SCSS (Bit 8) */ -#define HRPWM0_CSG_SWS_SCSS_Msk \ - (0x100UL) /*!< HRPWM0_CSG SWS: SCSS (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_CSG_SWC ------------------------------- */ -#define HRPWM0_CSG_SWC_CVLS1_Pos \ - (0UL) /*!< HRPWM0_CSG SWC: CVLS1 (Bit 0) */ -#define HRPWM0_CSG_SWC_CVLS1_Msk \ - (0x1UL) /*!< HRPWM0_CSG SWC: CVLS1 (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SWC_CVLS2_Pos \ - (1UL) /*!< HRPWM0_CSG SWC: CVLS2 (Bit 1) */ -#define HRPWM0_CSG_SWC_CVLS2_Msk \ - (0x2UL) /*!< HRPWM0_CSG SWC: CVLS2 (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SWC_CTRGS_Pos \ - (2UL) /*!< HRPWM0_CSG SWC: CTRGS (Bit 2) */ -#define HRPWM0_CSG_SWC_CTRGS_Msk \ - (0x4UL) /*!< HRPWM0_CSG SWC: CTRGS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SWC_CSTRS_Pos \ - (3UL) /*!< HRPWM0_CSG SWC: CSTRS (Bit 3) */ -#define HRPWM0_CSG_SWC_CSTRS_Msk \ - (0x8UL) /*!< HRPWM0_CSG SWC: CSTRS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SWC_CSTPS_Pos \ - (4UL) /*!< HRPWM0_CSG SWC: CSTPS (Bit 4) */ -#define HRPWM0_CSG_SWC_CSTPS_Msk \ - (0x10UL) /*!< HRPWM0_CSG SWC: CSTPS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SWC_CSTD_Pos \ - (5UL) /*!< HRPWM0_CSG SWC: CSTD (Bit 5) */ -#define HRPWM0_CSG_SWC_CSTD_Msk \ - (0x20UL) /*!< HRPWM0_CSG SWC: CSTD (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SWC_CCRS_Pos \ - (6UL) /*!< HRPWM0_CSG SWC: CCRS (Bit 6) */ -#define HRPWM0_CSG_SWC_CCRS_Msk \ - (0x40UL) /*!< HRPWM0_CSG SWC: CCRS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SWC_CCFS_Pos \ - (7UL) /*!< HRPWM0_CSG SWC: CCFS (Bit 7) */ -#define HRPWM0_CSG_SWC_CCFS_Msk \ - (0x80UL) /*!< HRPWM0_CSG SWC: CCFS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_SWC_CCSS_Pos \ - (8UL) /*!< HRPWM0_CSG SWC: CCSS (Bit 8) */ -#define HRPWM0_CSG_SWC_CCSS_Msk \ - (0x100UL) /*!< HRPWM0_CSG SWC: CCSS (Bitfield-Mask: 0x01) */ - -/* ------------------------------ HRPWM0_CSG_ISTAT ------------------------------ */ -#define HRPWM0_CSG_ISTAT_VLS1S_Pos \ - (0UL) /*!< HRPWM0_CSG ISTAT: VLS1S (Bit 0) */ -#define HRPWM0_CSG_ISTAT_VLS1S_Msk \ - (0x1UL) /*!< HRPWM0_CSG ISTAT: VLS1S (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_ISTAT_VLS2S_Pos \ - (1UL) /*!< HRPWM0_CSG ISTAT: VLS2S (Bit 1) */ -#define HRPWM0_CSG_ISTAT_VLS2S_Msk \ - (0x2UL) /*!< HRPWM0_CSG ISTAT: VLS2S (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_ISTAT_TRGSS_Pos \ - (2UL) /*!< HRPWM0_CSG ISTAT: TRGSS (Bit 2) */ -#define HRPWM0_CSG_ISTAT_TRGSS_Msk \ - (0x4UL) /*!< HRPWM0_CSG ISTAT: TRGSS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_ISTAT_STRSS_Pos \ - (3UL) /*!< HRPWM0_CSG ISTAT: STRSS (Bit 3) */ -#define HRPWM0_CSG_ISTAT_STRSS_Msk \ - (0x8UL) /*!< HRPWM0_CSG ISTAT: STRSS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_ISTAT_STPSS_Pos \ - (4UL) /*!< HRPWM0_CSG ISTAT: STPSS (Bit 4) */ -#define HRPWM0_CSG_ISTAT_STPSS_Msk \ - (0x10UL) /*!< HRPWM0_CSG ISTAT: STPSS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_ISTAT_STDS_Pos \ - (5UL) /*!< HRPWM0_CSG ISTAT: STDS (Bit 5) */ -#define HRPWM0_CSG_ISTAT_STDS_Msk \ - (0x20UL) /*!< HRPWM0_CSG ISTAT: STDS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_ISTAT_CRSS_Pos \ - (6UL) /*!< HRPWM0_CSG ISTAT: CRSS (Bit 6) */ -#define HRPWM0_CSG_ISTAT_CRSS_Msk \ - (0x40UL) /*!< HRPWM0_CSG ISTAT: CRSS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_ISTAT_CFSS_Pos \ - (7UL) /*!< HRPWM0_CSG ISTAT: CFSS (Bit 7) */ -#define HRPWM0_CSG_ISTAT_CFSS_Msk \ - (0x80UL) /*!< HRPWM0_CSG ISTAT: CFSS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG_ISTAT_CSES_Pos \ - (8UL) /*!< HRPWM0_CSG ISTAT: CSES (Bit 8) */ -#define HRPWM0_CSG_ISTAT_CSES_Msk \ - (0x100UL) /*!< HRPWM0_CSG ISTAT: CSES (Bitfield-Mask: 0x01) */ - -/* ================================================================================ */ -/* ================ struct 'HRPWM0_CSG0' Position & Mask ================ */ -/* ================================================================================ */ - -/* ------------------------------- HRPWM0_CSG0_DCI ------------------------------ */ -#define HRPWM0_CSG0_DCI_SVIS_Pos \ - (0UL) /*!< HRPWM0_CSG0 DCI: SVIS (Bit 0) */ -#define HRPWM0_CSG0_DCI_SVIS_Msk \ - (0xfUL) /*!< HRPWM0_CSG0 DCI: SVIS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG0_DCI_STRIS_Pos \ - (4UL) /*!< HRPWM0_CSG0 DCI: STRIS (Bit 4) */ -#define HRPWM0_CSG0_DCI_STRIS_Msk \ - (0xf0UL) /*!< HRPWM0_CSG0 DCI: STRIS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG0_DCI_STPIS_Pos \ - (8UL) /*!< HRPWM0_CSG0 DCI: STPIS (Bit 8) */ -#define HRPWM0_CSG0_DCI_STPIS_Msk \ - (0xf00UL) /*!< HRPWM0_CSG0 DCI: STPIS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG0_DCI_TRGIS_Pos \ - (12UL) /*!< HRPWM0_CSG0 DCI: TRGIS (Bit 12) */ -#define HRPWM0_CSG0_DCI_TRGIS_Msk \ - (0xf000UL) /*!< HRPWM0_CSG0 DCI: TRGIS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG0_DCI_STIS_Pos \ - (16UL) /*!< HRPWM0_CSG0 DCI: STIS (Bit 16) */ -#define HRPWM0_CSG0_DCI_STIS_Msk \ - (0xf0000UL) /*!< HRPWM0_CSG0 DCI: STIS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG0_DCI_SCS_Pos \ - (20UL) /*!< HRPWM0_CSG0 DCI: SCS (Bit 20) */ -#define HRPWM0_CSG0_DCI_SCS_Msk \ - (0x300000UL) /*!< HRPWM0_CSG0 DCI: SCS (Bitfield-Mask: 0x03) */ - -/* ------------------------------- HRPWM0_CSG0_IES ------------------------------ */ -#define HRPWM0_CSG0_IES_SVLS_Pos \ - (0UL) /*!< HRPWM0_CSG0 IES: SVLS (Bit 0) */ -#define HRPWM0_CSG0_IES_SVLS_Msk \ - (0x3UL) /*!< HRPWM0_CSG0 IES: SVLS (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG0_IES_STRES_Pos \ - (2UL) /*!< HRPWM0_CSG0 IES: STRES (Bit 2) */ -#define HRPWM0_CSG0_IES_STRES_Msk \ - (0xcUL) /*!< HRPWM0_CSG0 IES: STRES (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG0_IES_STPES_Pos \ - (4UL) /*!< HRPWM0_CSG0 IES: STPES (Bit 4) */ -#define HRPWM0_CSG0_IES_STPES_Msk \ - (0x30UL) /*!< HRPWM0_CSG0 IES: STPES (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG0_IES_TRGES_Pos \ - (6UL) /*!< HRPWM0_CSG0 IES: TRGES (Bit 6) */ -#define HRPWM0_CSG0_IES_TRGES_Msk \ - (0xc0UL) /*!< HRPWM0_CSG0 IES: TRGES (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG0_IES_STES_Pos \ - (8UL) /*!< HRPWM0_CSG0 IES: STES (Bit 8) */ -#define HRPWM0_CSG0_IES_STES_Msk \ - (0x300UL) /*!< HRPWM0_CSG0 IES: STES (Bitfield-Mask: 0x03) */ - -/* ------------------------------- HRPWM0_CSG0_SC ------------------------------- */ -#define HRPWM0_CSG0_SC_PSRM_Pos \ - (0UL) /*!< HRPWM0_CSG0 SC: PSRM (Bit 0) */ -#define HRPWM0_CSG0_SC_PSRM_Msk \ - (0x3UL) /*!< HRPWM0_CSG0 SC: PSRM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG0_SC_PSTM_Pos \ - (2UL) /*!< HRPWM0_CSG0 SC: PSTM (Bit 2) */ -#define HRPWM0_CSG0_SC_PSTM_Msk \ - (0xcUL) /*!< HRPWM0_CSG0 SC: PSTM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG0_SC_FPD_Pos \ - (4UL) /*!< HRPWM0_CSG0 SC: FPD (Bit 4) */ -#define HRPWM0_CSG0_SC_FPD_Msk \ - (0x10UL) /*!< HRPWM0_CSG0 SC: FPD (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SC_PSV_Pos \ - (5UL) /*!< HRPWM0_CSG0 SC: PSV (Bit 5) */ -#define HRPWM0_CSG0_SC_PSV_Msk \ - (0x60UL) /*!< HRPWM0_CSG0 SC: PSV (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG0_SC_SCM_Pos \ - (8UL) /*!< HRPWM0_CSG0 SC: SCM (Bit 8) */ -#define HRPWM0_CSG0_SC_SCM_Msk \ - (0x300UL) /*!< HRPWM0_CSG0 SC: SCM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG0_SC_SSRM_Pos \ - (10UL) /*!< HRPWM0_CSG0 SC: SSRM (Bit 10) */ -#define HRPWM0_CSG0_SC_SSRM_Msk \ - (0xc00UL) /*!< HRPWM0_CSG0 SC: SSRM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG0_SC_SSTM_Pos \ - (12UL) /*!< HRPWM0_CSG0 SC: SSTM (Bit 12) */ -#define HRPWM0_CSG0_SC_SSTM_Msk \ - (0x3000UL) /*!< HRPWM0_CSG0 SC: SSTM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG0_SC_SVSC_Pos \ - (14UL) /*!< HRPWM0_CSG0 SC: SVSC (Bit 14) */ -#define HRPWM0_CSG0_SC_SVSC_Msk \ - (0xc000UL) /*!< HRPWM0_CSG0 SC: SVSC (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG0_SC_SWSM_Pos \ - (16UL) /*!< HRPWM0_CSG0 SC: SWSM (Bit 16) */ -#define HRPWM0_CSG0_SC_SWSM_Msk \ - (0x30000UL) /*!< HRPWM0_CSG0 SC: SWSM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG0_SC_GCFG_Pos \ - (18UL) /*!< HRPWM0_CSG0 SC: GCFG (Bit 18) */ -#define HRPWM0_CSG0_SC_GCFG_Msk \ - (0xc0000UL) /*!< HRPWM0_CSG0 SC: GCFG (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG0_SC_IST_Pos \ - (20UL) /*!< HRPWM0_CSG0 SC: IST (Bit 20) */ -#define HRPWM0_CSG0_SC_IST_Msk \ - (0x100000UL) /*!< HRPWM0_CSG0 SC: IST (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SC_PSE_Pos \ - (21UL) /*!< HRPWM0_CSG0 SC: PSE (Bit 21) */ -#define HRPWM0_CSG0_SC_PSE_Msk \ - (0x200000UL) /*!< HRPWM0_CSG0 SC: PSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SC_PSWM_Pos \ - (24UL) /*!< HRPWM0_CSG0 SC: PSWM (Bit 24) */ -#define HRPWM0_CSG0_SC_PSWM_Msk \ - (0x3000000UL) /*!< HRPWM0_CSG0 SC: PSWM (Bitfield-Mask: 0x03) */ - -/* ------------------------------- HRPWM0_CSG0_PC ------------------------------- */ -#define HRPWM0_CSG0_PC_PSWV_Pos \ - (0UL) /*!< HRPWM0_CSG0 PC: PSWV (Bit 0) */ -#define HRPWM0_CSG0_PC_PSWV_Msk \ - (0x3fUL) /*!< HRPWM0_CSG0 PC: PSWV (Bitfield-Mask: 0x3f) */ - -/* ------------------------------ HRPWM0_CSG0_DSV1 ------------------------------ */ -#define HRPWM0_CSG0_DSV1_DSV1_Pos \ - (0UL) /*!< HRPWM0_CSG0 DSV1: DSV1 (Bit 0) */ -#define HRPWM0_CSG0_DSV1_DSV1_Msk \ - (0x3ffUL) /*!< HRPWM0_CSG0 DSV1: DSV1 (Bitfield-Mask: 0x3ff) */ - -/* ------------------------------ HRPWM0_CSG0_DSV2 ------------------------------ */ -#define HRPWM0_CSG0_DSV2_DSV2_Pos \ - (0UL) /*!< HRPWM0_CSG0 DSV2: DSV2 (Bit 0) */ -#define HRPWM0_CSG0_DSV2_DSV2_Msk \ - (0x3ffUL) /*!< HRPWM0_CSG0 DSV2: DSV2 (Bitfield-Mask: 0x3ff) */ - -/* ------------------------------ HRPWM0_CSG0_SDSV1 ----------------------------- */ -#define HRPWM0_CSG0_SDSV1_SDSV1_Pos \ - (0UL) /*!< HRPWM0_CSG0 SDSV1: SDSV1 (Bit 0) */ -#define HRPWM0_CSG0_SDSV1_SDSV1_Msk \ - (0x3ffUL) /*!< HRPWM0_CSG0 SDSV1: SDSV1 (Bitfield-Mask: 0x3ff) */ - -/* ------------------------------- HRPWM0_CSG0_SPC ------------------------------ */ -#define HRPWM0_CSG0_SPC_SPSWV_Pos \ - (0UL) /*!< HRPWM0_CSG0 SPC: SPSWV (Bit 0) */ -#define HRPWM0_CSG0_SPC_SPSWV_Msk \ - (0x3fUL) /*!< HRPWM0_CSG0 SPC: SPSWV (Bitfield-Mask: 0x3f) */ - -/* ------------------------------- HRPWM0_CSG0_CC ------------------------------- */ -#define HRPWM0_CSG0_CC_IBS_Pos \ - (0UL) /*!< HRPWM0_CSG0 CC: IBS (Bit 0) */ -#define HRPWM0_CSG0_CC_IBS_Msk \ - (0xfUL) /*!< HRPWM0_CSG0 CC: IBS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG0_CC_IMCS_Pos \ - (8UL) /*!< HRPWM0_CSG0 CC: IMCS (Bit 8) */ -#define HRPWM0_CSG0_CC_IMCS_Msk \ - (0x100UL) /*!< HRPWM0_CSG0 CC: IMCS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_CC_IMCC_Pos \ - (9UL) /*!< HRPWM0_CSG0 CC: IMCC (Bit 9) */ -#define HRPWM0_CSG0_CC_IMCC_Msk \ - (0x600UL) /*!< HRPWM0_CSG0 CC: IMCC (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG0_CC_ESE_Pos \ - (11UL) /*!< HRPWM0_CSG0 CC: ESE (Bit 11) */ -#define HRPWM0_CSG0_CC_ESE_Msk \ - (0x800UL) /*!< HRPWM0_CSG0 CC: ESE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_CC_OIE_Pos \ - (12UL) /*!< HRPWM0_CSG0 CC: OIE (Bit 12) */ -#define HRPWM0_CSG0_CC_OIE_Msk \ - (0x1000UL) /*!< HRPWM0_CSG0 CC: OIE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_CC_OSE_Pos \ - (13UL) /*!< HRPWM0_CSG0 CC: OSE (Bit 13) */ -#define HRPWM0_CSG0_CC_OSE_Msk \ - (0x2000UL) /*!< HRPWM0_CSG0 CC: OSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_CC_BLMC_Pos \ - (14UL) /*!< HRPWM0_CSG0 CC: BLMC (Bit 14) */ -#define HRPWM0_CSG0_CC_BLMC_Msk \ - (0xc000UL) /*!< HRPWM0_CSG0 CC: BLMC (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG0_CC_EBE_Pos \ - (16UL) /*!< HRPWM0_CSG0 CC: EBE (Bit 16) */ -#define HRPWM0_CSG0_CC_EBE_Msk \ - (0x10000UL) /*!< HRPWM0_CSG0 CC: EBE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_CC_COFE_Pos \ - (17UL) /*!< HRPWM0_CSG0 CC: COFE (Bit 17) */ -#define HRPWM0_CSG0_CC_COFE_Msk \ - (0x20000UL) /*!< HRPWM0_CSG0 CC: COFE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_CC_COFM_Pos \ - (18UL) /*!< HRPWM0_CSG0 CC: COFM (Bit 18) */ -#define HRPWM0_CSG0_CC_COFM_Msk \ - (0x3c0000UL) /*!< HRPWM0_CSG0 CC: COFM (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG0_CC_COFC_Pos \ - (24UL) /*!< HRPWM0_CSG0 CC: COFC (Bit 24) */ -#define HRPWM0_CSG0_CC_COFC_Msk \ - (0x3000000UL) /*!< HRPWM0_CSG0 CC: COFC (Bitfield-Mask: 0x03) */ - -/* ------------------------------- HRPWM0_CSG0_PLC ------------------------------ */ -#define HRPWM0_CSG0_PLC_IPLS_Pos \ - (0UL) /*!< HRPWM0_CSG0 PLC: IPLS (Bit 0) */ -#define HRPWM0_CSG0_PLC_IPLS_Msk \ - (0xfUL) /*!< HRPWM0_CSG0 PLC: IPLS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG0_PLC_PLCL_Pos \ - (8UL) /*!< HRPWM0_CSG0 PLC: PLCL (Bit 8) */ -#define HRPWM0_CSG0_PLC_PLCL_Msk \ - (0x300UL) /*!< HRPWM0_CSG0 PLC: PLCL (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG0_PLC_PSL_Pos \ - (10UL) /*!< HRPWM0_CSG0 PLC: PSL (Bit 10) */ -#define HRPWM0_CSG0_PLC_PSL_Msk \ - (0x400UL) /*!< HRPWM0_CSG0 PLC: PSL (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_PLC_PLSW_Pos \ - (11UL) /*!< HRPWM0_CSG0 PLC: PLSW (Bit 11) */ -#define HRPWM0_CSG0_PLC_PLSW_Msk \ - (0x800UL) /*!< HRPWM0_CSG0 PLC: PLSW (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_PLC_PLEC_Pos \ - (12UL) /*!< HRPWM0_CSG0 PLC: PLEC (Bit 12) */ -#define HRPWM0_CSG0_PLC_PLEC_Msk \ - (0x3000UL) /*!< HRPWM0_CSG0 PLC: PLEC (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG0_PLC_PLXC_Pos \ - (14UL) /*!< HRPWM0_CSG0 PLC: PLXC (Bit 14) */ -#define HRPWM0_CSG0_PLC_PLXC_Msk \ - (0xc000UL) /*!< HRPWM0_CSG0 PLC: PLXC (Bitfield-Mask: 0x03) */ - -/* ------------------------------- HRPWM0_CSG0_BLV ------------------------------ */ -#define HRPWM0_CSG0_BLV_BLV_Pos \ - (0UL) /*!< HRPWM0_CSG0 BLV: BLV (Bit 0) */ -#define HRPWM0_CSG0_BLV_BLV_Msk \ - (0xffUL) /*!< HRPWM0_CSG0 BLV: BLV (Bitfield-Mask: 0xff) */ - -/* ------------------------------- HRPWM0_CSG0_SRE ------------------------------ */ -#define HRPWM0_CSG0_SRE_VLS1E_Pos \ - (0UL) /*!< HRPWM0_CSG0 SRE: VLS1E (Bit 0) */ -#define HRPWM0_CSG0_SRE_VLS1E_Msk \ - (0x1UL) /*!< HRPWM0_CSG0 SRE: VLS1E (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SRE_VLS2E_Pos \ - (1UL) /*!< HRPWM0_CSG0 SRE: VLS2E (Bit 1) */ -#define HRPWM0_CSG0_SRE_VLS2E_Msk \ - (0x2UL) /*!< HRPWM0_CSG0 SRE: VLS2E (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SRE_TRGSE_Pos \ - (2UL) /*!< HRPWM0_CSG0 SRE: TRGSE (Bit 2) */ -#define HRPWM0_CSG0_SRE_TRGSE_Msk \ - (0x4UL) /*!< HRPWM0_CSG0 SRE: TRGSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SRE_STRSE_Pos \ - (3UL) /*!< HRPWM0_CSG0 SRE: STRSE (Bit 3) */ -#define HRPWM0_CSG0_SRE_STRSE_Msk \ - (0x8UL) /*!< HRPWM0_CSG0 SRE: STRSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SRE_STPSE_Pos \ - (4UL) /*!< HRPWM0_CSG0 SRE: STPSE (Bit 4) */ -#define HRPWM0_CSG0_SRE_STPSE_Msk \ - (0x10UL) /*!< HRPWM0_CSG0 SRE: STPSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SRE_STDE_Pos \ - (5UL) /*!< HRPWM0_CSG0 SRE: STDE (Bit 5) */ -#define HRPWM0_CSG0_SRE_STDE_Msk \ - (0x20UL) /*!< HRPWM0_CSG0 SRE: STDE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SRE_CRSE_Pos \ - (6UL) /*!< HRPWM0_CSG0 SRE: CRSE (Bit 6) */ -#define HRPWM0_CSG0_SRE_CRSE_Msk \ - (0x40UL) /*!< HRPWM0_CSG0 SRE: CRSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SRE_CFSE_Pos \ - (7UL) /*!< HRPWM0_CSG0 SRE: CFSE (Bit 7) */ -#define HRPWM0_CSG0_SRE_CFSE_Msk \ - (0x80UL) /*!< HRPWM0_CSG0 SRE: CFSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SRE_CSEE_Pos \ - (8UL) /*!< HRPWM0_CSG0 SRE: CSEE (Bit 8) */ -#define HRPWM0_CSG0_SRE_CSEE_Msk \ - (0x100UL) /*!< HRPWM0_CSG0 SRE: CSEE (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_CSG0_SRS ------------------------------ */ -#define HRPWM0_CSG0_SRS_VLS1S_Pos \ - (0UL) /*!< HRPWM0_CSG0 SRS: VLS1S (Bit 0) */ -#define HRPWM0_CSG0_SRS_VLS1S_Msk \ - (0x3UL) /*!< HRPWM0_CSG0 SRS: VLS1S (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG0_SRS_VLS2S_Pos \ - (2UL) /*!< HRPWM0_CSG0 SRS: VLS2S (Bit 2) */ -#define HRPWM0_CSG0_SRS_VLS2S_Msk \ - (0xcUL) /*!< HRPWM0_CSG0 SRS: VLS2S (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG0_SRS_TRLS_Pos \ - (4UL) /*!< HRPWM0_CSG0 SRS: TRLS (Bit 4) */ -#define HRPWM0_CSG0_SRS_TRLS_Msk \ - (0x30UL) /*!< HRPWM0_CSG0 SRS: TRLS (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG0_SRS_SSLS_Pos \ - (6UL) /*!< HRPWM0_CSG0 SRS: SSLS (Bit 6) */ -#define HRPWM0_CSG0_SRS_SSLS_Msk \ - (0xc0UL) /*!< HRPWM0_CSG0 SRS: SSLS (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG0_SRS_STLS_Pos \ - (8UL) /*!< HRPWM0_CSG0 SRS: STLS (Bit 8) */ -#define HRPWM0_CSG0_SRS_STLS_Msk \ - (0x300UL) /*!< HRPWM0_CSG0 SRS: STLS (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG0_SRS_CRFLS_Pos \ - (10UL) /*!< HRPWM0_CSG0 SRS: CRFLS (Bit 10) */ -#define HRPWM0_CSG0_SRS_CRFLS_Msk \ - (0xc00UL) /*!< HRPWM0_CSG0 SRS: CRFLS (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG0_SRS_CSLS_Pos \ - (12UL) /*!< HRPWM0_CSG0 SRS: CSLS (Bit 12) */ -#define HRPWM0_CSG0_SRS_CSLS_Msk \ - (0x3000UL) /*!< HRPWM0_CSG0 SRS: CSLS (Bitfield-Mask: 0x03) */ - -/* ------------------------------- HRPWM0_CSG0_SWS ------------------------------ */ -#define HRPWM0_CSG0_SWS_SVLS1_Pos \ - (0UL) /*!< HRPWM0_CSG0 SWS: SVLS1 (Bit 0) */ -#define HRPWM0_CSG0_SWS_SVLS1_Msk \ - (0x1UL) /*!< HRPWM0_CSG0 SWS: SVLS1 (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SWS_SVLS2_Pos \ - (1UL) /*!< HRPWM0_CSG0 SWS: SVLS2 (Bit 1) */ -#define HRPWM0_CSG0_SWS_SVLS2_Msk \ - (0x2UL) /*!< HRPWM0_CSG0 SWS: SVLS2 (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SWS_STRGS_Pos \ - (2UL) /*!< HRPWM0_CSG0 SWS: STRGS (Bit 2) */ -#define HRPWM0_CSG0_SWS_STRGS_Msk \ - (0x4UL) /*!< HRPWM0_CSG0 SWS: STRGS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SWS_SSTRS_Pos \ - (3UL) /*!< HRPWM0_CSG0 SWS: SSTRS (Bit 3) */ -#define HRPWM0_CSG0_SWS_SSTRS_Msk \ - (0x8UL) /*!< HRPWM0_CSG0 SWS: SSTRS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SWS_SSTPS_Pos \ - (4UL) /*!< HRPWM0_CSG0 SWS: SSTPS (Bit 4) */ -#define HRPWM0_CSG0_SWS_SSTPS_Msk \ - (0x10UL) /*!< HRPWM0_CSG0 SWS: SSTPS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SWS_SSTD_Pos \ - (5UL) /*!< HRPWM0_CSG0 SWS: SSTD (Bit 5) */ -#define HRPWM0_CSG0_SWS_SSTD_Msk \ - (0x20UL) /*!< HRPWM0_CSG0 SWS: SSTD (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SWS_SCRS_Pos \ - (6UL) /*!< HRPWM0_CSG0 SWS: SCRS (Bit 6) */ -#define HRPWM0_CSG0_SWS_SCRS_Msk \ - (0x40UL) /*!< HRPWM0_CSG0 SWS: SCRS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SWS_SCFS_Pos \ - (7UL) /*!< HRPWM0_CSG0 SWS: SCFS (Bit 7) */ -#define HRPWM0_CSG0_SWS_SCFS_Msk \ - (0x80UL) /*!< HRPWM0_CSG0 SWS: SCFS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SWS_SCSS_Pos \ - (8UL) /*!< HRPWM0_CSG0 SWS: SCSS (Bit 8) */ -#define HRPWM0_CSG0_SWS_SCSS_Msk \ - (0x100UL) /*!< HRPWM0_CSG0 SWS: SCSS (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_CSG0_SWC ------------------------------ */ -#define HRPWM0_CSG0_SWC_CVLS1_Pos \ - (0UL) /*!< HRPWM0_CSG0 SWC: CVLS1 (Bit 0) */ -#define HRPWM0_CSG0_SWC_CVLS1_Msk \ - (0x1UL) /*!< HRPWM0_CSG0 SWC: CVLS1 (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SWC_CVLS2_Pos \ - (1UL) /*!< HRPWM0_CSG0 SWC: CVLS2 (Bit 1) */ -#define HRPWM0_CSG0_SWC_CVLS2_Msk \ - (0x2UL) /*!< HRPWM0_CSG0 SWC: CVLS2 (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SWC_CTRGS_Pos \ - (2UL) /*!< HRPWM0_CSG0 SWC: CTRGS (Bit 2) */ -#define HRPWM0_CSG0_SWC_CTRGS_Msk \ - (0x4UL) /*!< HRPWM0_CSG0 SWC: CTRGS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SWC_CSTRS_Pos \ - (3UL) /*!< HRPWM0_CSG0 SWC: CSTRS (Bit 3) */ -#define HRPWM0_CSG0_SWC_CSTRS_Msk \ - (0x8UL) /*!< HRPWM0_CSG0 SWC: CSTRS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SWC_CSTPS_Pos \ - (4UL) /*!< HRPWM0_CSG0 SWC: CSTPS (Bit 4) */ -#define HRPWM0_CSG0_SWC_CSTPS_Msk \ - (0x10UL) /*!< HRPWM0_CSG0 SWC: CSTPS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SWC_CSTD_Pos \ - (5UL) /*!< HRPWM0_CSG0 SWC: CSTD (Bit 5) */ -#define HRPWM0_CSG0_SWC_CSTD_Msk \ - (0x20UL) /*!< HRPWM0_CSG0 SWC: CSTD (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SWC_CCRS_Pos \ - (6UL) /*!< HRPWM0_CSG0 SWC: CCRS (Bit 6) */ -#define HRPWM0_CSG0_SWC_CCRS_Msk \ - (0x40UL) /*!< HRPWM0_CSG0 SWC: CCRS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SWC_CCFS_Pos \ - (7UL) /*!< HRPWM0_CSG0 SWC: CCFS (Bit 7) */ -#define HRPWM0_CSG0_SWC_CCFS_Msk \ - (0x80UL) /*!< HRPWM0_CSG0 SWC: CCFS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_SWC_CCSS_Pos \ - (8UL) /*!< HRPWM0_CSG0 SWC: CCSS (Bit 8) */ -#define HRPWM0_CSG0_SWC_CCSS_Msk \ - (0x100UL) /*!< HRPWM0_CSG0 SWC: CCSS (Bitfield-Mask: 0x01) */ - -/* ------------------------------ HRPWM0_CSG0_ISTAT ----------------------------- */ -#define HRPWM0_CSG0_ISTAT_VLS1S_Pos \ - (0UL) /*!< HRPWM0_CSG0 ISTAT: VLS1S (Bit 0) */ -#define HRPWM0_CSG0_ISTAT_VLS1S_Msk \ - (0x1UL) /*!< HRPWM0_CSG0 ISTAT: VLS1S (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_ISTAT_VLS2S_Pos \ - (1UL) /*!< HRPWM0_CSG0 ISTAT: VLS2S (Bit 1) */ -#define HRPWM0_CSG0_ISTAT_VLS2S_Msk \ - (0x2UL) /*!< HRPWM0_CSG0 ISTAT: VLS2S (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_ISTAT_TRGSS_Pos \ - (2UL) /*!< HRPWM0_CSG0 ISTAT: TRGSS (Bit 2) */ -#define HRPWM0_CSG0_ISTAT_TRGSS_Msk \ - (0x4UL) /*!< HRPWM0_CSG0 ISTAT: TRGSS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_ISTAT_STRSS_Pos \ - (3UL) /*!< HRPWM0_CSG0 ISTAT: STRSS (Bit 3) */ -#define HRPWM0_CSG0_ISTAT_STRSS_Msk \ - (0x8UL) /*!< HRPWM0_CSG0 ISTAT: STRSS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_ISTAT_STPSS_Pos \ - (4UL) /*!< HRPWM0_CSG0 ISTAT: STPSS (Bit 4) */ -#define HRPWM0_CSG0_ISTAT_STPSS_Msk \ - (0x10UL) /*!< HRPWM0_CSG0 ISTAT: STPSS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_ISTAT_STDS_Pos \ - (5UL) /*!< HRPWM0_CSG0 ISTAT: STDS (Bit 5) */ -#define HRPWM0_CSG0_ISTAT_STDS_Msk \ - (0x20UL) /*!< HRPWM0_CSG0 ISTAT: STDS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_ISTAT_CRSS_Pos \ - (6UL) /*!< HRPWM0_CSG0 ISTAT: CRSS (Bit 6) */ -#define HRPWM0_CSG0_ISTAT_CRSS_Msk \ - (0x40UL) /*!< HRPWM0_CSG0 ISTAT: CRSS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_ISTAT_CFSS_Pos \ - (7UL) /*!< HRPWM0_CSG0 ISTAT: CFSS (Bit 7) */ -#define HRPWM0_CSG0_ISTAT_CFSS_Msk \ - (0x80UL) /*!< HRPWM0_CSG0 ISTAT: CFSS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG0_ISTAT_CSES_Pos \ - (8UL) /*!< HRPWM0_CSG0 ISTAT: CSES (Bit 8) */ -#define HRPWM0_CSG0_ISTAT_CSES_Msk \ - (0x100UL) /*!< HRPWM0_CSG0 ISTAT: CSES (Bitfield-Mask: 0x01) */ - -/* ================================================================================ */ -/* ================ struct 'HRPWM0_CSG1' Position & Mask ================ */ -/* ================================================================================ */ - -/* ------------------------------- HRPWM0_CSG1_DCI ------------------------------ */ -#define HRPWM0_CSG1_DCI_SVIS_Pos \ - (0UL) /*!< HRPWM0_CSG1 DCI: SVIS (Bit 0) */ -#define HRPWM0_CSG1_DCI_SVIS_Msk \ - (0xfUL) /*!< HRPWM0_CSG1 DCI: SVIS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG1_DCI_STRIS_Pos \ - (4UL) /*!< HRPWM0_CSG1 DCI: STRIS (Bit 4) */ -#define HRPWM0_CSG1_DCI_STRIS_Msk \ - (0xf0UL) /*!< HRPWM0_CSG1 DCI: STRIS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG1_DCI_STPIS_Pos \ - (8UL) /*!< HRPWM0_CSG1 DCI: STPIS (Bit 8) */ -#define HRPWM0_CSG1_DCI_STPIS_Msk \ - (0xf00UL) /*!< HRPWM0_CSG1 DCI: STPIS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG1_DCI_TRGIS_Pos \ - (12UL) /*!< HRPWM0_CSG1 DCI: TRGIS (Bit 12) */ -#define HRPWM0_CSG1_DCI_TRGIS_Msk \ - (0xf000UL) /*!< HRPWM0_CSG1 DCI: TRGIS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG1_DCI_STIS_Pos \ - (16UL) /*!< HRPWM0_CSG1 DCI: STIS (Bit 16) */ -#define HRPWM0_CSG1_DCI_STIS_Msk \ - (0xf0000UL) /*!< HRPWM0_CSG1 DCI: STIS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG1_DCI_SCS_Pos \ - (20UL) /*!< HRPWM0_CSG1 DCI: SCS (Bit 20) */ -#define HRPWM0_CSG1_DCI_SCS_Msk \ - (0x300000UL) /*!< HRPWM0_CSG1 DCI: SCS (Bitfield-Mask: 0x03) */ - -/* ------------------------------- HRPWM0_CSG1_IES ------------------------------ */ -#define HRPWM0_CSG1_IES_SVLS_Pos \ - (0UL) /*!< HRPWM0_CSG1 IES: SVLS (Bit 0) */ -#define HRPWM0_CSG1_IES_SVLS_Msk \ - (0x3UL) /*!< HRPWM0_CSG1 IES: SVLS (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG1_IES_STRES_Pos \ - (2UL) /*!< HRPWM0_CSG1 IES: STRES (Bit 2) */ -#define HRPWM0_CSG1_IES_STRES_Msk \ - (0xcUL) /*!< HRPWM0_CSG1 IES: STRES (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG1_IES_STPES_Pos \ - (4UL) /*!< HRPWM0_CSG1 IES: STPES (Bit 4) */ -#define HRPWM0_CSG1_IES_STPES_Msk \ - (0x30UL) /*!< HRPWM0_CSG1 IES: STPES (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG1_IES_TRGES_Pos \ - (6UL) /*!< HRPWM0_CSG1 IES: TRGES (Bit 6) */ -#define HRPWM0_CSG1_IES_TRGES_Msk \ - (0xc0UL) /*!< HRPWM0_CSG1 IES: TRGES (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG1_IES_STES_Pos \ - (8UL) /*!< HRPWM0_CSG1 IES: STES (Bit 8) */ -#define HRPWM0_CSG1_IES_STES_Msk \ - (0x300UL) /*!< HRPWM0_CSG1 IES: STES (Bitfield-Mask: 0x03) */ - -/* ------------------------------- HRPWM0_CSG1_SC ------------------------------- */ -#define HRPWM0_CSG1_SC_PSRM_Pos \ - (0UL) /*!< HRPWM0_CSG1 SC: PSRM (Bit 0) */ -#define HRPWM0_CSG1_SC_PSRM_Msk \ - (0x3UL) /*!< HRPWM0_CSG1 SC: PSRM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG1_SC_PSTM_Pos \ - (2UL) /*!< HRPWM0_CSG1 SC: PSTM (Bit 2) */ -#define HRPWM0_CSG1_SC_PSTM_Msk \ - (0xcUL) /*!< HRPWM0_CSG1 SC: PSTM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG1_SC_FPD_Pos \ - (4UL) /*!< HRPWM0_CSG1 SC: FPD (Bit 4) */ -#define HRPWM0_CSG1_SC_FPD_Msk \ - (0x10UL) /*!< HRPWM0_CSG1 SC: FPD (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SC_PSV_Pos \ - (5UL) /*!< HRPWM0_CSG1 SC: PSV (Bit 5) */ -#define HRPWM0_CSG1_SC_PSV_Msk \ - (0x60UL) /*!< HRPWM0_CSG1 SC: PSV (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG1_SC_SCM_Pos \ - (8UL) /*!< HRPWM0_CSG1 SC: SCM (Bit 8) */ -#define HRPWM0_CSG1_SC_SCM_Msk \ - (0x300UL) /*!< HRPWM0_CSG1 SC: SCM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG1_SC_SSRM_Pos \ - (10UL) /*!< HRPWM0_CSG1 SC: SSRM (Bit 10) */ -#define HRPWM0_CSG1_SC_SSRM_Msk \ - (0xc00UL) /*!< HRPWM0_CSG1 SC: SSRM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG1_SC_SSTM_Pos \ - (12UL) /*!< HRPWM0_CSG1 SC: SSTM (Bit 12) */ -#define HRPWM0_CSG1_SC_SSTM_Msk \ - (0x3000UL) /*!< HRPWM0_CSG1 SC: SSTM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG1_SC_SVSC_Pos \ - (14UL) /*!< HRPWM0_CSG1 SC: SVSC (Bit 14) */ -#define HRPWM0_CSG1_SC_SVSC_Msk \ - (0xc000UL) /*!< HRPWM0_CSG1 SC: SVSC (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG1_SC_SWSM_Pos \ - (16UL) /*!< HRPWM0_CSG1 SC: SWSM (Bit 16) */ -#define HRPWM0_CSG1_SC_SWSM_Msk \ - (0x30000UL) /*!< HRPWM0_CSG1 SC: SWSM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG1_SC_GCFG_Pos \ - (18UL) /*!< HRPWM0_CSG1 SC: GCFG (Bit 18) */ -#define HRPWM0_CSG1_SC_GCFG_Msk \ - (0xc0000UL) /*!< HRPWM0_CSG1 SC: GCFG (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG1_SC_IST_Pos \ - (20UL) /*!< HRPWM0_CSG1 SC: IST (Bit 20) */ -#define HRPWM0_CSG1_SC_IST_Msk \ - (0x100000UL) /*!< HRPWM0_CSG1 SC: IST (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SC_PSE_Pos \ - (21UL) /*!< HRPWM0_CSG1 SC: PSE (Bit 21) */ -#define HRPWM0_CSG1_SC_PSE_Msk \ - (0x200000UL) /*!< HRPWM0_CSG1 SC: PSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SC_PSWM_Pos \ - (24UL) /*!< HRPWM0_CSG1 SC: PSWM (Bit 24) */ -#define HRPWM0_CSG1_SC_PSWM_Msk \ - (0x3000000UL) /*!< HRPWM0_CSG1 SC: PSWM (Bitfield-Mask: 0x03) */ - -/* ------------------------------- HRPWM0_CSG1_PC ------------------------------- */ -#define HRPWM0_CSG1_PC_PSWV_Pos \ - (0UL) /*!< HRPWM0_CSG1 PC: PSWV (Bit 0) */ -#define HRPWM0_CSG1_PC_PSWV_Msk \ - (0x3fUL) /*!< HRPWM0_CSG1 PC: PSWV (Bitfield-Mask: 0x3f) */ - -/* ------------------------------ HRPWM0_CSG1_DSV1 ------------------------------ */ -#define HRPWM0_CSG1_DSV1_DSV1_Pos \ - (0UL) /*!< HRPWM0_CSG1 DSV1: DSV1 (Bit 0) */ -#define HRPWM0_CSG1_DSV1_DSV1_Msk \ - (0x3ffUL) /*!< HRPWM0_CSG1 DSV1: DSV1 (Bitfield-Mask: 0x3ff) */ - -/* ------------------------------ HRPWM0_CSG1_DSV2 ------------------------------ */ -#define HRPWM0_CSG1_DSV2_DSV2_Pos \ - (0UL) /*!< HRPWM0_CSG1 DSV2: DSV2 (Bit 0) */ -#define HRPWM0_CSG1_DSV2_DSV2_Msk \ - (0x3ffUL) /*!< HRPWM0_CSG1 DSV2: DSV2 (Bitfield-Mask: 0x3ff) */ - -/* ------------------------------ HRPWM0_CSG1_SDSV1 ----------------------------- */ -#define HRPWM0_CSG1_SDSV1_SDSV1_Pos \ - (0UL) /*!< HRPWM0_CSG1 SDSV1: SDSV1 (Bit 0) */ -#define HRPWM0_CSG1_SDSV1_SDSV1_Msk \ - (0x3ffUL) /*!< HRPWM0_CSG1 SDSV1: SDSV1 (Bitfield-Mask: 0x3ff) */ - -/* ------------------------------- HRPWM0_CSG1_SPC ------------------------------ */ -#define HRPWM0_CSG1_SPC_SPSWV_Pos \ - (0UL) /*!< HRPWM0_CSG1 SPC: SPSWV (Bit 0) */ -#define HRPWM0_CSG1_SPC_SPSWV_Msk \ - (0x3fUL) /*!< HRPWM0_CSG1 SPC: SPSWV (Bitfield-Mask: 0x3f) */ - -/* ------------------------------- HRPWM0_CSG1_CC ------------------------------- */ -#define HRPWM0_CSG1_CC_IBS_Pos \ - (0UL) /*!< HRPWM0_CSG1 CC: IBS (Bit 0) */ -#define HRPWM0_CSG1_CC_IBS_Msk \ - (0xfUL) /*!< HRPWM0_CSG1 CC: IBS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG1_CC_IMCS_Pos \ - (8UL) /*!< HRPWM0_CSG1 CC: IMCS (Bit 8) */ -#define HRPWM0_CSG1_CC_IMCS_Msk \ - (0x100UL) /*!< HRPWM0_CSG1 CC: IMCS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_CC_IMCC_Pos \ - (9UL) /*!< HRPWM0_CSG1 CC: IMCC (Bit 9) */ -#define HRPWM0_CSG1_CC_IMCC_Msk \ - (0x600UL) /*!< HRPWM0_CSG1 CC: IMCC (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG1_CC_ESE_Pos \ - (11UL) /*!< HRPWM0_CSG1 CC: ESE (Bit 11) */ -#define HRPWM0_CSG1_CC_ESE_Msk \ - (0x800UL) /*!< HRPWM0_CSG1 CC: ESE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_CC_OIE_Pos \ - (12UL) /*!< HRPWM0_CSG1 CC: OIE (Bit 12) */ -#define HRPWM0_CSG1_CC_OIE_Msk \ - (0x1000UL) /*!< HRPWM0_CSG1 CC: OIE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_CC_OSE_Pos \ - (13UL) /*!< HRPWM0_CSG1 CC: OSE (Bit 13) */ -#define HRPWM0_CSG1_CC_OSE_Msk \ - (0x2000UL) /*!< HRPWM0_CSG1 CC: OSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_CC_BLMC_Pos \ - (14UL) /*!< HRPWM0_CSG1 CC: BLMC (Bit 14) */ -#define HRPWM0_CSG1_CC_BLMC_Msk \ - (0xc000UL) /*!< HRPWM0_CSG1 CC: BLMC (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG1_CC_EBE_Pos \ - (16UL) /*!< HRPWM0_CSG1 CC: EBE (Bit 16) */ -#define HRPWM0_CSG1_CC_EBE_Msk \ - (0x10000UL) /*!< HRPWM0_CSG1 CC: EBE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_CC_COFE_Pos \ - (17UL) /*!< HRPWM0_CSG1 CC: COFE (Bit 17) */ -#define HRPWM0_CSG1_CC_COFE_Msk \ - (0x20000UL) /*!< HRPWM0_CSG1 CC: COFE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_CC_COFM_Pos \ - (18UL) /*!< HRPWM0_CSG1 CC: COFM (Bit 18) */ -#define HRPWM0_CSG1_CC_COFM_Msk \ - (0x3c0000UL) /*!< HRPWM0_CSG1 CC: COFM (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG1_CC_COFC_Pos \ - (24UL) /*!< HRPWM0_CSG1 CC: COFC (Bit 24) */ -#define HRPWM0_CSG1_CC_COFC_Msk \ - (0x3000000UL) /*!< HRPWM0_CSG1 CC: COFC (Bitfield-Mask: 0x03) */ - -/* ------------------------------- HRPWM0_CSG1_PLC ------------------------------ */ -#define HRPWM0_CSG1_PLC_IPLS_Pos \ - (0UL) /*!< HRPWM0_CSG1 PLC: IPLS (Bit 0) */ -#define HRPWM0_CSG1_PLC_IPLS_Msk \ - (0xfUL) /*!< HRPWM0_CSG1 PLC: IPLS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG1_PLC_PLCL_Pos \ - (8UL) /*!< HRPWM0_CSG1 PLC: PLCL (Bit 8) */ -#define HRPWM0_CSG1_PLC_PLCL_Msk \ - (0x300UL) /*!< HRPWM0_CSG1 PLC: PLCL (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG1_PLC_PSL_Pos \ - (10UL) /*!< HRPWM0_CSG1 PLC: PSL (Bit 10) */ -#define HRPWM0_CSG1_PLC_PSL_Msk \ - (0x400UL) /*!< HRPWM0_CSG1 PLC: PSL (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_PLC_PLSW_Pos \ - (11UL) /*!< HRPWM0_CSG1 PLC: PLSW (Bit 11) */ -#define HRPWM0_CSG1_PLC_PLSW_Msk \ - (0x800UL) /*!< HRPWM0_CSG1 PLC: PLSW (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_PLC_PLEC_Pos \ - (12UL) /*!< HRPWM0_CSG1 PLC: PLEC (Bit 12) */ -#define HRPWM0_CSG1_PLC_PLEC_Msk \ - (0x3000UL) /*!< HRPWM0_CSG1 PLC: PLEC (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG1_PLC_PLXC_Pos \ - (14UL) /*!< HRPWM0_CSG1 PLC: PLXC (Bit 14) */ -#define HRPWM0_CSG1_PLC_PLXC_Msk \ - (0xc000UL) /*!< HRPWM0_CSG1 PLC: PLXC (Bitfield-Mask: 0x03) */ - -/* ------------------------------- HRPWM0_CSG1_BLV ------------------------------ */ -#define HRPWM0_CSG1_BLV_BLV_Pos \ - (0UL) /*!< HRPWM0_CSG1 BLV: BLV (Bit 0) */ -#define HRPWM0_CSG1_BLV_BLV_Msk \ - (0xffUL) /*!< HRPWM0_CSG1 BLV: BLV (Bitfield-Mask: 0xff) */ - -/* ------------------------------- HRPWM0_CSG1_SRE ------------------------------ */ -#define HRPWM0_CSG1_SRE_VLS1E_Pos \ - (0UL) /*!< HRPWM0_CSG1 SRE: VLS1E (Bit 0) */ -#define HRPWM0_CSG1_SRE_VLS1E_Msk \ - (0x1UL) /*!< HRPWM0_CSG1 SRE: VLS1E (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SRE_VLS2E_Pos \ - (1UL) /*!< HRPWM0_CSG1 SRE: VLS2E (Bit 1) */ -#define HRPWM0_CSG1_SRE_VLS2E_Msk \ - (0x2UL) /*!< HRPWM0_CSG1 SRE: VLS2E (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SRE_TRGSE_Pos \ - (2UL) /*!< HRPWM0_CSG1 SRE: TRGSE (Bit 2) */ -#define HRPWM0_CSG1_SRE_TRGSE_Msk \ - (0x4UL) /*!< HRPWM0_CSG1 SRE: TRGSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SRE_STRSE_Pos \ - (3UL) /*!< HRPWM0_CSG1 SRE: STRSE (Bit 3) */ -#define HRPWM0_CSG1_SRE_STRSE_Msk \ - (0x8UL) /*!< HRPWM0_CSG1 SRE: STRSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SRE_STPSE_Pos \ - (4UL) /*!< HRPWM0_CSG1 SRE: STPSE (Bit 4) */ -#define HRPWM0_CSG1_SRE_STPSE_Msk \ - (0x10UL) /*!< HRPWM0_CSG1 SRE: STPSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SRE_STDE_Pos \ - (5UL) /*!< HRPWM0_CSG1 SRE: STDE (Bit 5) */ -#define HRPWM0_CSG1_SRE_STDE_Msk \ - (0x20UL) /*!< HRPWM0_CSG1 SRE: STDE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SRE_CRSE_Pos \ - (6UL) /*!< HRPWM0_CSG1 SRE: CRSE (Bit 6) */ -#define HRPWM0_CSG1_SRE_CRSE_Msk \ - (0x40UL) /*!< HRPWM0_CSG1 SRE: CRSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SRE_CFSE_Pos \ - (7UL) /*!< HRPWM0_CSG1 SRE: CFSE (Bit 7) */ -#define HRPWM0_CSG1_SRE_CFSE_Msk \ - (0x80UL) /*!< HRPWM0_CSG1 SRE: CFSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SRE_CSEE_Pos \ - (8UL) /*!< HRPWM0_CSG1 SRE: CSEE (Bit 8) */ -#define HRPWM0_CSG1_SRE_CSEE_Msk \ - (0x100UL) /*!< HRPWM0_CSG1 SRE: CSEE (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_CSG1_SRS ------------------------------ */ -#define HRPWM0_CSG1_SRS_VLS1S_Pos \ - (0UL) /*!< HRPWM0_CSG1 SRS: VLS1S (Bit 0) */ -#define HRPWM0_CSG1_SRS_VLS1S_Msk \ - (0x3UL) /*!< HRPWM0_CSG1 SRS: VLS1S (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG1_SRS_VLS2S_Pos \ - (2UL) /*!< HRPWM0_CSG1 SRS: VLS2S (Bit 2) */ -#define HRPWM0_CSG1_SRS_VLS2S_Msk \ - (0xcUL) /*!< HRPWM0_CSG1 SRS: VLS2S (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG1_SRS_TRLS_Pos \ - (4UL) /*!< HRPWM0_CSG1 SRS: TRLS (Bit 4) */ -#define HRPWM0_CSG1_SRS_TRLS_Msk \ - (0x30UL) /*!< HRPWM0_CSG1 SRS: TRLS (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG1_SRS_SSLS_Pos \ - (6UL) /*!< HRPWM0_CSG1 SRS: SSLS (Bit 6) */ -#define HRPWM0_CSG1_SRS_SSLS_Msk \ - (0xc0UL) /*!< HRPWM0_CSG1 SRS: SSLS (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG1_SRS_STLS_Pos \ - (8UL) /*!< HRPWM0_CSG1 SRS: STLS (Bit 8) */ -#define HRPWM0_CSG1_SRS_STLS_Msk \ - (0x300UL) /*!< HRPWM0_CSG1 SRS: STLS (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG1_SRS_CRFLS_Pos \ - (10UL) /*!< HRPWM0_CSG1 SRS: CRFLS (Bit 10) */ -#define HRPWM0_CSG1_SRS_CRFLS_Msk \ - (0xc00UL) /*!< HRPWM0_CSG1 SRS: CRFLS (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG1_SRS_CSLS_Pos \ - (12UL) /*!< HRPWM0_CSG1 SRS: CSLS (Bit 12) */ -#define HRPWM0_CSG1_SRS_CSLS_Msk \ - (0x3000UL) /*!< HRPWM0_CSG1 SRS: CSLS (Bitfield-Mask: 0x03) */ - -/* ------------------------------- HRPWM0_CSG1_SWS ------------------------------ */ -#define HRPWM0_CSG1_SWS_SVLS1_Pos \ - (0UL) /*!< HRPWM0_CSG1 SWS: SVLS1 (Bit 0) */ -#define HRPWM0_CSG1_SWS_SVLS1_Msk \ - (0x1UL) /*!< HRPWM0_CSG1 SWS: SVLS1 (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SWS_SVLS2_Pos \ - (1UL) /*!< HRPWM0_CSG1 SWS: SVLS2 (Bit 1) */ -#define HRPWM0_CSG1_SWS_SVLS2_Msk \ - (0x2UL) /*!< HRPWM0_CSG1 SWS: SVLS2 (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SWS_STRGS_Pos \ - (2UL) /*!< HRPWM0_CSG1 SWS: STRGS (Bit 2) */ -#define HRPWM0_CSG1_SWS_STRGS_Msk \ - (0x4UL) /*!< HRPWM0_CSG1 SWS: STRGS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SWS_SSTRS_Pos \ - (3UL) /*!< HRPWM0_CSG1 SWS: SSTRS (Bit 3) */ -#define HRPWM0_CSG1_SWS_SSTRS_Msk \ - (0x8UL) /*!< HRPWM0_CSG1 SWS: SSTRS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SWS_SSTPS_Pos \ - (4UL) /*!< HRPWM0_CSG1 SWS: SSTPS (Bit 4) */ -#define HRPWM0_CSG1_SWS_SSTPS_Msk \ - (0x10UL) /*!< HRPWM0_CSG1 SWS: SSTPS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SWS_SSTD_Pos \ - (5UL) /*!< HRPWM0_CSG1 SWS: SSTD (Bit 5) */ -#define HRPWM0_CSG1_SWS_SSTD_Msk \ - (0x20UL) /*!< HRPWM0_CSG1 SWS: SSTD (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SWS_SCRS_Pos \ - (6UL) /*!< HRPWM0_CSG1 SWS: SCRS (Bit 6) */ -#define HRPWM0_CSG1_SWS_SCRS_Msk \ - (0x40UL) /*!< HRPWM0_CSG1 SWS: SCRS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SWS_SCFS_Pos \ - (7UL) /*!< HRPWM0_CSG1 SWS: SCFS (Bit 7) */ -#define HRPWM0_CSG1_SWS_SCFS_Msk \ - (0x80UL) /*!< HRPWM0_CSG1 SWS: SCFS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SWS_SCSS_Pos \ - (8UL) /*!< HRPWM0_CSG1 SWS: SCSS (Bit 8) */ -#define HRPWM0_CSG1_SWS_SCSS_Msk \ - (0x100UL) /*!< HRPWM0_CSG1 SWS: SCSS (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_CSG1_SWC ------------------------------ */ -#define HRPWM0_CSG1_SWC_CVLS1_Pos \ - (0UL) /*!< HRPWM0_CSG1 SWC: CVLS1 (Bit 0) */ -#define HRPWM0_CSG1_SWC_CVLS1_Msk \ - (0x1UL) /*!< HRPWM0_CSG1 SWC: CVLS1 (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SWC_CVLS2_Pos \ - (1UL) /*!< HRPWM0_CSG1 SWC: CVLS2 (Bit 1) */ -#define HRPWM0_CSG1_SWC_CVLS2_Msk \ - (0x2UL) /*!< HRPWM0_CSG1 SWC: CVLS2 (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SWC_CTRGS_Pos \ - (2UL) /*!< HRPWM0_CSG1 SWC: CTRGS (Bit 2) */ -#define HRPWM0_CSG1_SWC_CTRGS_Msk \ - (0x4UL) /*!< HRPWM0_CSG1 SWC: CTRGS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SWC_CSTRS_Pos \ - (3UL) /*!< HRPWM0_CSG1 SWC: CSTRS (Bit 3) */ -#define HRPWM0_CSG1_SWC_CSTRS_Msk \ - (0x8UL) /*!< HRPWM0_CSG1 SWC: CSTRS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SWC_CSTPS_Pos \ - (4UL) /*!< HRPWM0_CSG1 SWC: CSTPS (Bit 4) */ -#define HRPWM0_CSG1_SWC_CSTPS_Msk \ - (0x10UL) /*!< HRPWM0_CSG1 SWC: CSTPS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SWC_CSTD_Pos \ - (5UL) /*!< HRPWM0_CSG1 SWC: CSTD (Bit 5) */ -#define HRPWM0_CSG1_SWC_CSTD_Msk \ - (0x20UL) /*!< HRPWM0_CSG1 SWC: CSTD (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SWC_CCRS_Pos \ - (6UL) /*!< HRPWM0_CSG1 SWC: CCRS (Bit 6) */ -#define HRPWM0_CSG1_SWC_CCRS_Msk \ - (0x40UL) /*!< HRPWM0_CSG1 SWC: CCRS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SWC_CCFS_Pos \ - (7UL) /*!< HRPWM0_CSG1 SWC: CCFS (Bit 7) */ -#define HRPWM0_CSG1_SWC_CCFS_Msk \ - (0x80UL) /*!< HRPWM0_CSG1 SWC: CCFS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_SWC_CCSS_Pos \ - (8UL) /*!< HRPWM0_CSG1 SWC: CCSS (Bit 8) */ -#define HRPWM0_CSG1_SWC_CCSS_Msk \ - (0x100UL) /*!< HRPWM0_CSG1 SWC: CCSS (Bitfield-Mask: 0x01) */ - -/* ------------------------------ HRPWM0_CSG1_ISTAT ----------------------------- */ -#define HRPWM0_CSG1_ISTAT_VLS1S_Pos \ - (0UL) /*!< HRPWM0_CSG1 ISTAT: VLS1S (Bit 0) */ -#define HRPWM0_CSG1_ISTAT_VLS1S_Msk \ - (0x1UL) /*!< HRPWM0_CSG1 ISTAT: VLS1S (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_ISTAT_VLS2S_Pos \ - (1UL) /*!< HRPWM0_CSG1 ISTAT: VLS2S (Bit 1) */ -#define HRPWM0_CSG1_ISTAT_VLS2S_Msk \ - (0x2UL) /*!< HRPWM0_CSG1 ISTAT: VLS2S (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_ISTAT_TRGSS_Pos \ - (2UL) /*!< HRPWM0_CSG1 ISTAT: TRGSS (Bit 2) */ -#define HRPWM0_CSG1_ISTAT_TRGSS_Msk \ - (0x4UL) /*!< HRPWM0_CSG1 ISTAT: TRGSS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_ISTAT_STRSS_Pos \ - (3UL) /*!< HRPWM0_CSG1 ISTAT: STRSS (Bit 3) */ -#define HRPWM0_CSG1_ISTAT_STRSS_Msk \ - (0x8UL) /*!< HRPWM0_CSG1 ISTAT: STRSS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_ISTAT_STPSS_Pos \ - (4UL) /*!< HRPWM0_CSG1 ISTAT: STPSS (Bit 4) */ -#define HRPWM0_CSG1_ISTAT_STPSS_Msk \ - (0x10UL) /*!< HRPWM0_CSG1 ISTAT: STPSS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_ISTAT_STDS_Pos \ - (5UL) /*!< HRPWM0_CSG1 ISTAT: STDS (Bit 5) */ -#define HRPWM0_CSG1_ISTAT_STDS_Msk \ - (0x20UL) /*!< HRPWM0_CSG1 ISTAT: STDS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_ISTAT_CRSS_Pos \ - (6UL) /*!< HRPWM0_CSG1 ISTAT: CRSS (Bit 6) */ -#define HRPWM0_CSG1_ISTAT_CRSS_Msk \ - (0x40UL) /*!< HRPWM0_CSG1 ISTAT: CRSS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_ISTAT_CFSS_Pos \ - (7UL) /*!< HRPWM0_CSG1 ISTAT: CFSS (Bit 7) */ -#define HRPWM0_CSG1_ISTAT_CFSS_Msk \ - (0x80UL) /*!< HRPWM0_CSG1 ISTAT: CFSS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG1_ISTAT_CSES_Pos \ - (8UL) /*!< HRPWM0_CSG1 ISTAT: CSES (Bit 8) */ -#define HRPWM0_CSG1_ISTAT_CSES_Msk \ - (0x100UL) /*!< HRPWM0_CSG1 ISTAT: CSES (Bitfield-Mask: 0x01) */ - -/* ================================================================================ */ -/* ================ struct 'HRPWM0_CSG2' Position & Mask ================ */ -/* ================================================================================ */ - -/* ------------------------------- HRPWM0_CSG2_DCI ------------------------------ */ -#define HRPWM0_CSG2_DCI_SVIS_Pos \ - (0UL) /*!< HRPWM0_CSG2 DCI: SVIS (Bit 0) */ -#define HRPWM0_CSG2_DCI_SVIS_Msk \ - (0xfUL) /*!< HRPWM0_CSG2 DCI: SVIS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG2_DCI_STRIS_Pos \ - (4UL) /*!< HRPWM0_CSG2 DCI: STRIS (Bit 4) */ -#define HRPWM0_CSG2_DCI_STRIS_Msk \ - (0xf0UL) /*!< HRPWM0_CSG2 DCI: STRIS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG2_DCI_STPIS_Pos \ - (8UL) /*!< HRPWM0_CSG2 DCI: STPIS (Bit 8) */ -#define HRPWM0_CSG2_DCI_STPIS_Msk \ - (0xf00UL) /*!< HRPWM0_CSG2 DCI: STPIS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG2_DCI_TRGIS_Pos \ - (12UL) /*!< HRPWM0_CSG2 DCI: TRGIS (Bit 12) */ -#define HRPWM0_CSG2_DCI_TRGIS_Msk \ - (0xf000UL) /*!< HRPWM0_CSG2 DCI: TRGIS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG2_DCI_STIS_Pos \ - (16UL) /*!< HRPWM0_CSG2 DCI: STIS (Bit 16) */ -#define HRPWM0_CSG2_DCI_STIS_Msk \ - (0xf0000UL) /*!< HRPWM0_CSG2 DCI: STIS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG2_DCI_SCS_Pos \ - (20UL) /*!< HRPWM0_CSG2 DCI: SCS (Bit 20) */ -#define HRPWM0_CSG2_DCI_SCS_Msk \ - (0x300000UL) /*!< HRPWM0_CSG2 DCI: SCS (Bitfield-Mask: 0x03) */ - -/* ------------------------------- HRPWM0_CSG2_IES ------------------------------ */ -#define HRPWM0_CSG2_IES_SVLS_Pos \ - (0UL) /*!< HRPWM0_CSG2 IES: SVLS (Bit 0) */ -#define HRPWM0_CSG2_IES_SVLS_Msk \ - (0x3UL) /*!< HRPWM0_CSG2 IES: SVLS (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG2_IES_STRES_Pos \ - (2UL) /*!< HRPWM0_CSG2 IES: STRES (Bit 2) */ -#define HRPWM0_CSG2_IES_STRES_Msk \ - (0xcUL) /*!< HRPWM0_CSG2 IES: STRES (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG2_IES_STPES_Pos \ - (4UL) /*!< HRPWM0_CSG2 IES: STPES (Bit 4) */ -#define HRPWM0_CSG2_IES_STPES_Msk \ - (0x30UL) /*!< HRPWM0_CSG2 IES: STPES (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG2_IES_TRGES_Pos \ - (6UL) /*!< HRPWM0_CSG2 IES: TRGES (Bit 6) */ -#define HRPWM0_CSG2_IES_TRGES_Msk \ - (0xc0UL) /*!< HRPWM0_CSG2 IES: TRGES (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG2_IES_STES_Pos \ - (8UL) /*!< HRPWM0_CSG2 IES: STES (Bit 8) */ -#define HRPWM0_CSG2_IES_STES_Msk \ - (0x300UL) /*!< HRPWM0_CSG2 IES: STES (Bitfield-Mask: 0x03) */ - -/* ------------------------------- HRPWM0_CSG2_SC ------------------------------- */ -#define HRPWM0_CSG2_SC_PSRM_Pos \ - (0UL) /*!< HRPWM0_CSG2 SC: PSRM (Bit 0) */ -#define HRPWM0_CSG2_SC_PSRM_Msk \ - (0x3UL) /*!< HRPWM0_CSG2 SC: PSRM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG2_SC_PSTM_Pos \ - (2UL) /*!< HRPWM0_CSG2 SC: PSTM (Bit 2) */ -#define HRPWM0_CSG2_SC_PSTM_Msk \ - (0xcUL) /*!< HRPWM0_CSG2 SC: PSTM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG2_SC_FPD_Pos \ - (4UL) /*!< HRPWM0_CSG2 SC: FPD (Bit 4) */ -#define HRPWM0_CSG2_SC_FPD_Msk \ - (0x10UL) /*!< HRPWM0_CSG2 SC: FPD (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SC_PSV_Pos \ - (5UL) /*!< HRPWM0_CSG2 SC: PSV (Bit 5) */ -#define HRPWM0_CSG2_SC_PSV_Msk \ - (0x60UL) /*!< HRPWM0_CSG2 SC: PSV (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG2_SC_SCM_Pos \ - (8UL) /*!< HRPWM0_CSG2 SC: SCM (Bit 8) */ -#define HRPWM0_CSG2_SC_SCM_Msk \ - (0x300UL) /*!< HRPWM0_CSG2 SC: SCM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG2_SC_SSRM_Pos \ - (10UL) /*!< HRPWM0_CSG2 SC: SSRM (Bit 10) */ -#define HRPWM0_CSG2_SC_SSRM_Msk \ - (0xc00UL) /*!< HRPWM0_CSG2 SC: SSRM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG2_SC_SSTM_Pos \ - (12UL) /*!< HRPWM0_CSG2 SC: SSTM (Bit 12) */ -#define HRPWM0_CSG2_SC_SSTM_Msk \ - (0x3000UL) /*!< HRPWM0_CSG2 SC: SSTM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG2_SC_SVSC_Pos \ - (14UL) /*!< HRPWM0_CSG2 SC: SVSC (Bit 14) */ -#define HRPWM0_CSG2_SC_SVSC_Msk \ - (0xc000UL) /*!< HRPWM0_CSG2 SC: SVSC (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG2_SC_SWSM_Pos \ - (16UL) /*!< HRPWM0_CSG2 SC: SWSM (Bit 16) */ -#define HRPWM0_CSG2_SC_SWSM_Msk \ - (0x30000UL) /*!< HRPWM0_CSG2 SC: SWSM (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG2_SC_GCFG_Pos \ - (18UL) /*!< HRPWM0_CSG2 SC: GCFG (Bit 18) */ -#define HRPWM0_CSG2_SC_GCFG_Msk \ - (0xc0000UL) /*!< HRPWM0_CSG2 SC: GCFG (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG2_SC_IST_Pos \ - (20UL) /*!< HRPWM0_CSG2 SC: IST (Bit 20) */ -#define HRPWM0_CSG2_SC_IST_Msk \ - (0x100000UL) /*!< HRPWM0_CSG2 SC: IST (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SC_PSE_Pos \ - (21UL) /*!< HRPWM0_CSG2 SC: PSE (Bit 21) */ -#define HRPWM0_CSG2_SC_PSE_Msk \ - (0x200000UL) /*!< HRPWM0_CSG2 SC: PSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SC_PSWM_Pos \ - (24UL) /*!< HRPWM0_CSG2 SC: PSWM (Bit 24) */ -#define HRPWM0_CSG2_SC_PSWM_Msk \ - (0x3000000UL) /*!< HRPWM0_CSG2 SC: PSWM (Bitfield-Mask: 0x03) */ - -/* ------------------------------- HRPWM0_CSG2_PC ------------------------------- */ -#define HRPWM0_CSG2_PC_PSWV_Pos \ - (0UL) /*!< HRPWM0_CSG2 PC: PSWV (Bit 0) */ -#define HRPWM0_CSG2_PC_PSWV_Msk \ - (0x3fUL) /*!< HRPWM0_CSG2 PC: PSWV (Bitfield-Mask: 0x3f) */ - -/* ------------------------------ HRPWM0_CSG2_DSV1 ------------------------------ */ -#define HRPWM0_CSG2_DSV1_DSV1_Pos \ - (0UL) /*!< HRPWM0_CSG2 DSV1: DSV1 (Bit 0) */ -#define HRPWM0_CSG2_DSV1_DSV1_Msk \ - (0x3ffUL) /*!< HRPWM0_CSG2 DSV1: DSV1 (Bitfield-Mask: 0x3ff) */ - -/* ------------------------------ HRPWM0_CSG2_DSV2 ------------------------------ */ -#define HRPWM0_CSG2_DSV2_DSV2_Pos \ - (0UL) /*!< HRPWM0_CSG2 DSV2: DSV2 (Bit 0) */ -#define HRPWM0_CSG2_DSV2_DSV2_Msk \ - (0x3ffUL) /*!< HRPWM0_CSG2 DSV2: DSV2 (Bitfield-Mask: 0x3ff) */ - -/* ------------------------------ HRPWM0_CSG2_SDSV1 ----------------------------- */ -#define HRPWM0_CSG2_SDSV1_SDSV1_Pos \ - (0UL) /*!< HRPWM0_CSG2 SDSV1: SDSV1 (Bit 0) */ -#define HRPWM0_CSG2_SDSV1_SDSV1_Msk \ - (0x3ffUL) /*!< HRPWM0_CSG2 SDSV1: SDSV1 (Bitfield-Mask: 0x3ff) */ - -/* ------------------------------- HRPWM0_CSG2_SPC ------------------------------ */ -#define HRPWM0_CSG2_SPC_SPSWV_Pos \ - (0UL) /*!< HRPWM0_CSG2 SPC: SPSWV (Bit 0) */ -#define HRPWM0_CSG2_SPC_SPSWV_Msk \ - (0x3fUL) /*!< HRPWM0_CSG2 SPC: SPSWV (Bitfield-Mask: 0x3f) */ - -/* ------------------------------- HRPWM0_CSG2_CC ------------------------------- */ -#define HRPWM0_CSG2_CC_IBS_Pos \ - (0UL) /*!< HRPWM0_CSG2 CC: IBS (Bit 0) */ -#define HRPWM0_CSG2_CC_IBS_Msk \ - (0xfUL) /*!< HRPWM0_CSG2 CC: IBS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG2_CC_IMCS_Pos \ - (8UL) /*!< HRPWM0_CSG2 CC: IMCS (Bit 8) */ -#define HRPWM0_CSG2_CC_IMCS_Msk \ - (0x100UL) /*!< HRPWM0_CSG2 CC: IMCS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_CC_IMCC_Pos \ - (9UL) /*!< HRPWM0_CSG2 CC: IMCC (Bit 9) */ -#define HRPWM0_CSG2_CC_IMCC_Msk \ - (0x600UL) /*!< HRPWM0_CSG2 CC: IMCC (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG2_CC_ESE_Pos \ - (11UL) /*!< HRPWM0_CSG2 CC: ESE (Bit 11) */ -#define HRPWM0_CSG2_CC_ESE_Msk \ - (0x800UL) /*!< HRPWM0_CSG2 CC: ESE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_CC_OIE_Pos \ - (12UL) /*!< HRPWM0_CSG2 CC: OIE (Bit 12) */ -#define HRPWM0_CSG2_CC_OIE_Msk \ - (0x1000UL) /*!< HRPWM0_CSG2 CC: OIE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_CC_OSE_Pos \ - (13UL) /*!< HRPWM0_CSG2 CC: OSE (Bit 13) */ -#define HRPWM0_CSG2_CC_OSE_Msk \ - (0x2000UL) /*!< HRPWM0_CSG2 CC: OSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_CC_BLMC_Pos \ - (14UL) /*!< HRPWM0_CSG2 CC: BLMC (Bit 14) */ -#define HRPWM0_CSG2_CC_BLMC_Msk \ - (0xc000UL) /*!< HRPWM0_CSG2 CC: BLMC (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG2_CC_EBE_Pos \ - (16UL) /*!< HRPWM0_CSG2 CC: EBE (Bit 16) */ -#define HRPWM0_CSG2_CC_EBE_Msk \ - (0x10000UL) /*!< HRPWM0_CSG2 CC: EBE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_CC_COFE_Pos \ - (17UL) /*!< HRPWM0_CSG2 CC: COFE (Bit 17) */ -#define HRPWM0_CSG2_CC_COFE_Msk \ - (0x20000UL) /*!< HRPWM0_CSG2 CC: COFE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_CC_COFM_Pos \ - (18UL) /*!< HRPWM0_CSG2 CC: COFM (Bit 18) */ -#define HRPWM0_CSG2_CC_COFM_Msk \ - (0x3c0000UL) /*!< HRPWM0_CSG2 CC: COFM (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG2_CC_COFC_Pos \ - (24UL) /*!< HRPWM0_CSG2 CC: COFC (Bit 24) */ -#define HRPWM0_CSG2_CC_COFC_Msk \ - (0x3000000UL) /*!< HRPWM0_CSG2 CC: COFC (Bitfield-Mask: 0x03) */ - -/* ------------------------------- HRPWM0_CSG2_PLC ------------------------------ */ -#define HRPWM0_CSG2_PLC_IPLS_Pos \ - (0UL) /*!< HRPWM0_CSG2 PLC: IPLS (Bit 0) */ -#define HRPWM0_CSG2_PLC_IPLS_Msk \ - (0xfUL) /*!< HRPWM0_CSG2 PLC: IPLS (Bitfield-Mask: 0x0f) */ -#define HRPWM0_CSG2_PLC_PLCL_Pos \ - (8UL) /*!< HRPWM0_CSG2 PLC: PLCL (Bit 8) */ -#define HRPWM0_CSG2_PLC_PLCL_Msk \ - (0x300UL) /*!< HRPWM0_CSG2 PLC: PLCL (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG2_PLC_PSL_Pos \ - (10UL) /*!< HRPWM0_CSG2 PLC: PSL (Bit 10) */ -#define HRPWM0_CSG2_PLC_PSL_Msk \ - (0x400UL) /*!< HRPWM0_CSG2 PLC: PSL (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_PLC_PLSW_Pos \ - (11UL) /*!< HRPWM0_CSG2 PLC: PLSW (Bit 11) */ -#define HRPWM0_CSG2_PLC_PLSW_Msk \ - (0x800UL) /*!< HRPWM0_CSG2 PLC: PLSW (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_PLC_PLEC_Pos \ - (12UL) /*!< HRPWM0_CSG2 PLC: PLEC (Bit 12) */ -#define HRPWM0_CSG2_PLC_PLEC_Msk \ - (0x3000UL) /*!< HRPWM0_CSG2 PLC: PLEC (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG2_PLC_PLXC_Pos \ - (14UL) /*!< HRPWM0_CSG2 PLC: PLXC (Bit 14) */ -#define HRPWM0_CSG2_PLC_PLXC_Msk \ - (0xc000UL) /*!< HRPWM0_CSG2 PLC: PLXC (Bitfield-Mask: 0x03) */ - -/* ------------------------------- HRPWM0_CSG2_BLV ------------------------------ */ -#define HRPWM0_CSG2_BLV_BLV_Pos \ - (0UL) /*!< HRPWM0_CSG2 BLV: BLV (Bit 0) */ -#define HRPWM0_CSG2_BLV_BLV_Msk \ - (0xffUL) /*!< HRPWM0_CSG2 BLV: BLV (Bitfield-Mask: 0xff) */ - -/* ------------------------------- HRPWM0_CSG2_SRE ------------------------------ */ -#define HRPWM0_CSG2_SRE_VLS1E_Pos \ - (0UL) /*!< HRPWM0_CSG2 SRE: VLS1E (Bit 0) */ -#define HRPWM0_CSG2_SRE_VLS1E_Msk \ - (0x1UL) /*!< HRPWM0_CSG2 SRE: VLS1E (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SRE_VLS2E_Pos \ - (1UL) /*!< HRPWM0_CSG2 SRE: VLS2E (Bit 1) */ -#define HRPWM0_CSG2_SRE_VLS2E_Msk \ - (0x2UL) /*!< HRPWM0_CSG2 SRE: VLS2E (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SRE_TRGSE_Pos \ - (2UL) /*!< HRPWM0_CSG2 SRE: TRGSE (Bit 2) */ -#define HRPWM0_CSG2_SRE_TRGSE_Msk \ - (0x4UL) /*!< HRPWM0_CSG2 SRE: TRGSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SRE_STRSE_Pos \ - (3UL) /*!< HRPWM0_CSG2 SRE: STRSE (Bit 3) */ -#define HRPWM0_CSG2_SRE_STRSE_Msk \ - (0x8UL) /*!< HRPWM0_CSG2 SRE: STRSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SRE_STPSE_Pos \ - (4UL) /*!< HRPWM0_CSG2 SRE: STPSE (Bit 4) */ -#define HRPWM0_CSG2_SRE_STPSE_Msk \ - (0x10UL) /*!< HRPWM0_CSG2 SRE: STPSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SRE_STDE_Pos \ - (5UL) /*!< HRPWM0_CSG2 SRE: STDE (Bit 5) */ -#define HRPWM0_CSG2_SRE_STDE_Msk \ - (0x20UL) /*!< HRPWM0_CSG2 SRE: STDE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SRE_CRSE_Pos \ - (6UL) /*!< HRPWM0_CSG2 SRE: CRSE (Bit 6) */ -#define HRPWM0_CSG2_SRE_CRSE_Msk \ - (0x40UL) /*!< HRPWM0_CSG2 SRE: CRSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SRE_CFSE_Pos \ - (7UL) /*!< HRPWM0_CSG2 SRE: CFSE (Bit 7) */ -#define HRPWM0_CSG2_SRE_CFSE_Msk \ - (0x80UL) /*!< HRPWM0_CSG2 SRE: CFSE (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SRE_CSEE_Pos \ - (8UL) /*!< HRPWM0_CSG2 SRE: CSEE (Bit 8) */ -#define HRPWM0_CSG2_SRE_CSEE_Msk \ - (0x100UL) /*!< HRPWM0_CSG2 SRE: CSEE (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_CSG2_SRS ------------------------------ */ -#define HRPWM0_CSG2_SRS_VLS1S_Pos \ - (0UL) /*!< HRPWM0_CSG2 SRS: VLS1S (Bit 0) */ -#define HRPWM0_CSG2_SRS_VLS1S_Msk \ - (0x3UL) /*!< HRPWM0_CSG2 SRS: VLS1S (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG2_SRS_VLS2S_Pos \ - (2UL) /*!< HRPWM0_CSG2 SRS: VLS2S (Bit 2) */ -#define HRPWM0_CSG2_SRS_VLS2S_Msk \ - (0xcUL) /*!< HRPWM0_CSG2 SRS: VLS2S (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG2_SRS_TRLS_Pos \ - (4UL) /*!< HRPWM0_CSG2 SRS: TRLS (Bit 4) */ -#define HRPWM0_CSG2_SRS_TRLS_Msk \ - (0x30UL) /*!< HRPWM0_CSG2 SRS: TRLS (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG2_SRS_SSLS_Pos \ - (6UL) /*!< HRPWM0_CSG2 SRS: SSLS (Bit 6) */ -#define HRPWM0_CSG2_SRS_SSLS_Msk \ - (0xc0UL) /*!< HRPWM0_CSG2 SRS: SSLS (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG2_SRS_STLS_Pos \ - (8UL) /*!< HRPWM0_CSG2 SRS: STLS (Bit 8) */ -#define HRPWM0_CSG2_SRS_STLS_Msk \ - (0x300UL) /*!< HRPWM0_CSG2 SRS: STLS (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG2_SRS_CRFLS_Pos \ - (10UL) /*!< HRPWM0_CSG2 SRS: CRFLS (Bit 10) */ -#define HRPWM0_CSG2_SRS_CRFLS_Msk \ - (0xc00UL) /*!< HRPWM0_CSG2 SRS: CRFLS (Bitfield-Mask: 0x03) */ -#define HRPWM0_CSG2_SRS_CSLS_Pos \ - (12UL) /*!< HRPWM0_CSG2 SRS: CSLS (Bit 12) */ -#define HRPWM0_CSG2_SRS_CSLS_Msk \ - (0x3000UL) /*!< HRPWM0_CSG2 SRS: CSLS (Bitfield-Mask: 0x03) */ - -/* ------------------------------- HRPWM0_CSG2_SWS ------------------------------ */ -#define HRPWM0_CSG2_SWS_SVLS1_Pos \ - (0UL) /*!< HRPWM0_CSG2 SWS: SVLS1 (Bit 0) */ -#define HRPWM0_CSG2_SWS_SVLS1_Msk \ - (0x1UL) /*!< HRPWM0_CSG2 SWS: SVLS1 (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SWS_SVLS2_Pos \ - (1UL) /*!< HRPWM0_CSG2 SWS: SVLS2 (Bit 1) */ -#define HRPWM0_CSG2_SWS_SVLS2_Msk \ - (0x2UL) /*!< HRPWM0_CSG2 SWS: SVLS2 (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SWS_STRGS_Pos \ - (2UL) /*!< HRPWM0_CSG2 SWS: STRGS (Bit 2) */ -#define HRPWM0_CSG2_SWS_STRGS_Msk \ - (0x4UL) /*!< HRPWM0_CSG2 SWS: STRGS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SWS_SSTRS_Pos \ - (3UL) /*!< HRPWM0_CSG2 SWS: SSTRS (Bit 3) */ -#define HRPWM0_CSG2_SWS_SSTRS_Msk \ - (0x8UL) /*!< HRPWM0_CSG2 SWS: SSTRS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SWS_SSTPS_Pos \ - (4UL) /*!< HRPWM0_CSG2 SWS: SSTPS (Bit 4) */ -#define HRPWM0_CSG2_SWS_SSTPS_Msk \ - (0x10UL) /*!< HRPWM0_CSG2 SWS: SSTPS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SWS_SSTD_Pos \ - (5UL) /*!< HRPWM0_CSG2 SWS: SSTD (Bit 5) */ -#define HRPWM0_CSG2_SWS_SSTD_Msk \ - (0x20UL) /*!< HRPWM0_CSG2 SWS: SSTD (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SWS_SCRS_Pos \ - (6UL) /*!< HRPWM0_CSG2 SWS: SCRS (Bit 6) */ -#define HRPWM0_CSG2_SWS_SCRS_Msk \ - (0x40UL) /*!< HRPWM0_CSG2 SWS: SCRS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SWS_SCFS_Pos \ - (7UL) /*!< HRPWM0_CSG2 SWS: SCFS (Bit 7) */ -#define HRPWM0_CSG2_SWS_SCFS_Msk \ - (0x80UL) /*!< HRPWM0_CSG2 SWS: SCFS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SWS_SCSS_Pos \ - (8UL) /*!< HRPWM0_CSG2 SWS: SCSS (Bit 8) */ -#define HRPWM0_CSG2_SWS_SCSS_Msk \ - (0x100UL) /*!< HRPWM0_CSG2 SWS: SCSS (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_CSG2_SWC ------------------------------ */ -#define HRPWM0_CSG2_SWC_CVLS1_Pos \ - (0UL) /*!< HRPWM0_CSG2 SWC: CVLS1 (Bit 0) */ -#define HRPWM0_CSG2_SWC_CVLS1_Msk \ - (0x1UL) /*!< HRPWM0_CSG2 SWC: CVLS1 (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SWC_CVLS2_Pos \ - (1UL) /*!< HRPWM0_CSG2 SWC: CVLS2 (Bit 1) */ -#define HRPWM0_CSG2_SWC_CVLS2_Msk \ - (0x2UL) /*!< HRPWM0_CSG2 SWC: CVLS2 (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SWC_CTRGS_Pos \ - (2UL) /*!< HRPWM0_CSG2 SWC: CTRGS (Bit 2) */ -#define HRPWM0_CSG2_SWC_CTRGS_Msk \ - (0x4UL) /*!< HRPWM0_CSG2 SWC: CTRGS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SWC_CSTRS_Pos \ - (3UL) /*!< HRPWM0_CSG2 SWC: CSTRS (Bit 3) */ -#define HRPWM0_CSG2_SWC_CSTRS_Msk \ - (0x8UL) /*!< HRPWM0_CSG2 SWC: CSTRS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SWC_CSTPS_Pos \ - (4UL) /*!< HRPWM0_CSG2 SWC: CSTPS (Bit 4) */ -#define HRPWM0_CSG2_SWC_CSTPS_Msk \ - (0x10UL) /*!< HRPWM0_CSG2 SWC: CSTPS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SWC_CSTD_Pos \ - (5UL) /*!< HRPWM0_CSG2 SWC: CSTD (Bit 5) */ -#define HRPWM0_CSG2_SWC_CSTD_Msk \ - (0x20UL) /*!< HRPWM0_CSG2 SWC: CSTD (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SWC_CCRS_Pos \ - (6UL) /*!< HRPWM0_CSG2 SWC: CCRS (Bit 6) */ -#define HRPWM0_CSG2_SWC_CCRS_Msk \ - (0x40UL) /*!< HRPWM0_CSG2 SWC: CCRS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SWC_CCFS_Pos \ - (7UL) /*!< HRPWM0_CSG2 SWC: CCFS (Bit 7) */ -#define HRPWM0_CSG2_SWC_CCFS_Msk \ - (0x80UL) /*!< HRPWM0_CSG2 SWC: CCFS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_SWC_CCSS_Pos \ - (8UL) /*!< HRPWM0_CSG2 SWC: CCSS (Bit 8) */ -#define HRPWM0_CSG2_SWC_CCSS_Msk \ - (0x100UL) /*!< HRPWM0_CSG2 SWC: CCSS (Bitfield-Mask: 0x01) */ - -/* ------------------------------ HRPWM0_CSG2_ISTAT ----------------------------- */ -#define HRPWM0_CSG2_ISTAT_VLS1S_Pos \ - (0UL) /*!< HRPWM0_CSG2 ISTAT: VLS1S (Bit 0) */ -#define HRPWM0_CSG2_ISTAT_VLS1S_Msk \ - (0x1UL) /*!< HRPWM0_CSG2 ISTAT: VLS1S (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_ISTAT_VLS2S_Pos \ - (1UL) /*!< HRPWM0_CSG2 ISTAT: VLS2S (Bit 1) */ -#define HRPWM0_CSG2_ISTAT_VLS2S_Msk \ - (0x2UL) /*!< HRPWM0_CSG2 ISTAT: VLS2S (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_ISTAT_TRGSS_Pos \ - (2UL) /*!< HRPWM0_CSG2 ISTAT: TRGSS (Bit 2) */ -#define HRPWM0_CSG2_ISTAT_TRGSS_Msk \ - (0x4UL) /*!< HRPWM0_CSG2 ISTAT: TRGSS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_ISTAT_STRSS_Pos \ - (3UL) /*!< HRPWM0_CSG2 ISTAT: STRSS (Bit 3) */ -#define HRPWM0_CSG2_ISTAT_STRSS_Msk \ - (0x8UL) /*!< HRPWM0_CSG2 ISTAT: STRSS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_ISTAT_STPSS_Pos \ - (4UL) /*!< HRPWM0_CSG2 ISTAT: STPSS (Bit 4) */ -#define HRPWM0_CSG2_ISTAT_STPSS_Msk \ - (0x10UL) /*!< HRPWM0_CSG2 ISTAT: STPSS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_ISTAT_STDS_Pos \ - (5UL) /*!< HRPWM0_CSG2 ISTAT: STDS (Bit 5) */ -#define HRPWM0_CSG2_ISTAT_STDS_Msk \ - (0x20UL) /*!< HRPWM0_CSG2 ISTAT: STDS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_ISTAT_CRSS_Pos \ - (6UL) /*!< HRPWM0_CSG2 ISTAT: CRSS (Bit 6) */ -#define HRPWM0_CSG2_ISTAT_CRSS_Msk \ - (0x40UL) /*!< HRPWM0_CSG2 ISTAT: CRSS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_ISTAT_CFSS_Pos \ - (7UL) /*!< HRPWM0_CSG2 ISTAT: CFSS (Bit 7) */ -#define HRPWM0_CSG2_ISTAT_CFSS_Msk \ - (0x80UL) /*!< HRPWM0_CSG2 ISTAT: CFSS (Bitfield-Mask: 0x01) */ -#define HRPWM0_CSG2_ISTAT_CSES_Pos \ - (8UL) /*!< HRPWM0_CSG2 ISTAT: CSES (Bit 8) */ -#define HRPWM0_CSG2_ISTAT_CSES_Msk \ - (0x100UL) /*!< HRPWM0_CSG2 ISTAT: CSES (Bitfield-Mask: 0x01) */ - -/* ================================================================================ */ -/* ================ Group 'HRPWM0_HRC' Position & Mask ================ */ -/* ================================================================================ */ - -/* -------------------------------- HRPWM0_HRC_GC ------------------------------- */ -#define HRPWM0_HRC_GC_HRM0_Pos \ - (0UL) /*!< HRPWM0_HRC GC: HRM0 (Bit 0) */ -#define HRPWM0_HRC_GC_HRM0_Msk \ - (0x3UL) /*!< HRPWM0_HRC GC: HRM0 (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC_GC_HRM1_Pos \ - (2UL) /*!< HRPWM0_HRC GC: HRM1 (Bit 2) */ -#define HRPWM0_HRC_GC_HRM1_Msk \ - (0xcUL) /*!< HRPWM0_HRC GC: HRM1 (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC_GC_DTE_Pos \ - (8UL) /*!< HRPWM0_HRC GC: DTE (Bit 8) */ -#define HRPWM0_HRC_GC_DTE_Msk \ - (0x100UL) /*!< HRPWM0_HRC GC: DTE (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC_GC_TR0E_Pos \ - (9UL) /*!< HRPWM0_HRC GC: TR0E (Bit 9) */ -#define HRPWM0_HRC_GC_TR0E_Msk \ - (0x200UL) /*!< HRPWM0_HRC GC: TR0E (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC_GC_TR1E_Pos \ - (10UL) /*!< HRPWM0_HRC GC: TR1E (Bit 10) */ -#define HRPWM0_HRC_GC_TR1E_Msk \ - (0x400UL) /*!< HRPWM0_HRC GC: TR1E (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC_GC_STC_Pos \ - (11UL) /*!< HRPWM0_HRC GC: STC (Bit 11) */ -#define HRPWM0_HRC_GC_STC_Msk \ - (0x800UL) /*!< HRPWM0_HRC GC: STC (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC_GC_DSTC_Pos \ - (12UL) /*!< HRPWM0_HRC GC: DSTC (Bit 12) */ -#define HRPWM0_HRC_GC_DSTC_Msk \ - (0x1000UL) /*!< HRPWM0_HRC GC: DSTC (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC_GC_OCS0_Pos \ - (13UL) /*!< HRPWM0_HRC GC: OCS0 (Bit 13) */ -#define HRPWM0_HRC_GC_OCS0_Msk \ - (0x2000UL) /*!< HRPWM0_HRC GC: OCS0 (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC_GC_OCS1_Pos \ - (14UL) /*!< HRPWM0_HRC GC: OCS1 (Bit 14) */ -#define HRPWM0_HRC_GC_OCS1_Msk \ - (0x4000UL) /*!< HRPWM0_HRC GC: OCS1 (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC_GC_DTUS_Pos \ - (16UL) /*!< HRPWM0_HRC GC: DTUS (Bit 16) */ -#define HRPWM0_HRC_GC_DTUS_Msk \ - (0x10000UL) /*!< HRPWM0_HRC GC: DTUS (Bitfield-Mask: 0x01) */ - -/* -------------------------------- HRPWM0_HRC_PL ------------------------------- */ -#define HRPWM0_HRC_PL_PSL0_Pos \ - (0UL) /*!< HRPWM0_HRC PL: PSL0 (Bit 0) */ -#define HRPWM0_HRC_PL_PSL0_Msk \ - (0x1UL) /*!< HRPWM0_HRC PL: PSL0 (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC_PL_PSL1_Pos \ - (1UL) /*!< HRPWM0_HRC PL: PSL1 (Bit 1) */ -#define HRPWM0_HRC_PL_PSL1_Msk \ - (0x2UL) /*!< HRPWM0_HRC PL: PSL1 (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_HRC_GSEL ------------------------------ */ -#define HRPWM0_HRC_GSEL_C0SS_Pos \ - (0UL) /*!< HRPWM0_HRC GSEL: C0SS (Bit 0) */ -#define HRPWM0_HRC_GSEL_C0SS_Msk \ - (0x7UL) /*!< HRPWM0_HRC GSEL: C0SS (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC_GSEL_C0CS_Pos \ - (3UL) /*!< HRPWM0_HRC GSEL: C0CS (Bit 3) */ -#define HRPWM0_HRC_GSEL_C0CS_Msk \ - (0x38UL) /*!< HRPWM0_HRC GSEL: C0CS (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC_GSEL_S0M_Pos \ - (6UL) /*!< HRPWM0_HRC GSEL: S0M (Bit 6) */ -#define HRPWM0_HRC_GSEL_S0M_Msk \ - (0xc0UL) /*!< HRPWM0_HRC GSEL: S0M (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC_GSEL_C0M_Pos \ - (8UL) /*!< HRPWM0_HRC GSEL: C0M (Bit 8) */ -#define HRPWM0_HRC_GSEL_C0M_Msk \ - (0x300UL) /*!< HRPWM0_HRC GSEL: C0M (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC_GSEL_S0ES_Pos \ - (10UL) /*!< HRPWM0_HRC GSEL: S0ES (Bit 10) */ -#define HRPWM0_HRC_GSEL_S0ES_Msk \ - (0xc00UL) /*!< HRPWM0_HRC GSEL: S0ES (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC_GSEL_C0ES_Pos \ - (12UL) /*!< HRPWM0_HRC GSEL: C0ES (Bit 12) */ -#define HRPWM0_HRC_GSEL_C0ES_Msk \ - (0x3000UL) /*!< HRPWM0_HRC GSEL: C0ES (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC_GSEL_C1SS_Pos \ - (16UL) /*!< HRPWM0_HRC GSEL: C1SS (Bit 16) */ -#define HRPWM0_HRC_GSEL_C1SS_Msk \ - (0x70000UL) /*!< HRPWM0_HRC GSEL: C1SS (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC_GSEL_C1CS_Pos \ - (19UL) /*!< HRPWM0_HRC GSEL: C1CS (Bit 19) */ -#define HRPWM0_HRC_GSEL_C1CS_Msk \ - (0x380000UL) /*!< HRPWM0_HRC GSEL: C1CS (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC_GSEL_S1M_Pos \ - (22UL) /*!< HRPWM0_HRC GSEL: S1M (Bit 22) */ -#define HRPWM0_HRC_GSEL_S1M_Msk \ - (0xc00000UL) /*!< HRPWM0_HRC GSEL: S1M (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC_GSEL_C1M_Pos \ - (24UL) /*!< HRPWM0_HRC GSEL: C1M (Bit 24) */ -#define HRPWM0_HRC_GSEL_C1M_Msk \ - (0x3000000UL) /*!< HRPWM0_HRC GSEL: C1M (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC_GSEL_S1ES_Pos \ - (26UL) /*!< HRPWM0_HRC GSEL: S1ES (Bit 26) */ -#define HRPWM0_HRC_GSEL_S1ES_Msk \ - (0xc000000UL) /*!< HRPWM0_HRC GSEL: S1ES (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC_GSEL_C1ES_Pos \ - (28UL) /*!< HRPWM0_HRC GSEL: C1ES (Bit 28) */ -#define HRPWM0_HRC_GSEL_C1ES_Msk \ - (0x30000000UL) /*!< HRPWM0_HRC GSEL: C1ES (Bitfield-Mask: 0x03) */ - -/* ------------------------------- HRPWM0_HRC_TSEL ------------------------------ */ -#define HRPWM0_HRC_TSEL_TSEL0_Pos \ - (0UL) /*!< HRPWM0_HRC TSEL: TSEL0 (Bit 0) */ -#define HRPWM0_HRC_TSEL_TSEL0_Msk \ - (0x7UL) /*!< HRPWM0_HRC TSEL: TSEL0 (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC_TSEL_TSEL1_Pos \ - (3UL) /*!< HRPWM0_HRC TSEL: TSEL1 (Bit 3) */ -#define HRPWM0_HRC_TSEL_TSEL1_Msk \ - (0x38UL) /*!< HRPWM0_HRC TSEL: TSEL1 (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC_TSEL_TS0E_Pos \ - (16UL) /*!< HRPWM0_HRC TSEL: TS0E (Bit 16) */ -#define HRPWM0_HRC_TSEL_TS0E_Msk \ - (0x10000UL) /*!< HRPWM0_HRC TSEL: TS0E (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC_TSEL_TS1E_Pos \ - (17UL) /*!< HRPWM0_HRC TSEL: TS1E (Bit 17) */ -#define HRPWM0_HRC_TSEL_TS1E_Msk \ - (0x20000UL) /*!< HRPWM0_HRC TSEL: TS1E (Bitfield-Mask: 0x01) */ - -/* -------------------------------- HRPWM0_HRC_SC ------------------------------- */ -#define HRPWM0_HRC_SC_ST_Pos \ - (0UL) /*!< HRPWM0_HRC SC: ST (Bit 0) */ -#define HRPWM0_HRC_SC_ST_Msk \ - (0x1UL) /*!< HRPWM0_HRC SC: ST (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_HRC_DCR ------------------------------- */ -#define HRPWM0_HRC_DCR_DTRV_Pos \ - (0UL) /*!< HRPWM0_HRC DCR: DTRV (Bit 0) */ -#define HRPWM0_HRC_DCR_DTRV_Msk \ - (0xffffUL) /*!< HRPWM0_HRC DCR: DTRV (Bitfield-Mask: 0xffff) */ - -/* ------------------------------- HRPWM0_HRC_DCF ------------------------------- */ -#define HRPWM0_HRC_DCF_DTFV_Pos \ - (0UL) /*!< HRPWM0_HRC DCF: DTFV (Bit 0) */ -#define HRPWM0_HRC_DCF_DTFV_Msk \ - (0xffffUL) /*!< HRPWM0_HRC DCF: DTFV (Bitfield-Mask: 0xffff) */ - -/* ------------------------------- HRPWM0_HRC_CR1 ------------------------------- */ -#define HRPWM0_HRC_CR1_CR1_Pos \ - (0UL) /*!< HRPWM0_HRC CR1: CR1 (Bit 0) */ -#define HRPWM0_HRC_CR1_CR1_Msk \ - (0xffUL) /*!< HRPWM0_HRC CR1: CR1 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- HRPWM0_HRC_CR2 ------------------------------- */ -#define HRPWM0_HRC_CR2_CR2_Pos \ - (0UL) /*!< HRPWM0_HRC CR2: CR2 (Bit 0) */ -#define HRPWM0_HRC_CR2_CR2_Msk \ - (0xffUL) /*!< HRPWM0_HRC CR2: CR2 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- HRPWM0_HRC_SSC ------------------------------- */ -#define HRPWM0_HRC_SSC_SST_Pos \ - (0UL) /*!< HRPWM0_HRC SSC: SST (Bit 0) */ -#define HRPWM0_HRC_SSC_SST_Msk \ - (0x1UL) /*!< HRPWM0_HRC SSC: SST (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_HRC_SDCR ------------------------------ */ -#define HRPWM0_HRC_SDCR_SDTRV_Pos \ - (0UL) /*!< HRPWM0_HRC SDCR: SDTRV (Bit 0) */ -#define HRPWM0_HRC_SDCR_SDTRV_Msk \ - (0xffffUL) /*!< HRPWM0_HRC SDCR: SDTRV (Bitfield-Mask: 0xffff) */ - -/* ------------------------------- HRPWM0_HRC_SDCF ------------------------------ */ -#define HRPWM0_HRC_SDCF_SDTFV_Pos \ - (0UL) /*!< HRPWM0_HRC SDCF: SDTFV (Bit 0) */ -#define HRPWM0_HRC_SDCF_SDTFV_Msk \ - (0xffffUL) /*!< HRPWM0_HRC SDCF: SDTFV (Bitfield-Mask: 0xffff) */ - -/* ------------------------------- HRPWM0_HRC_SCR1 ------------------------------ */ -#define HRPWM0_HRC_SCR1_SCR1_Pos \ - (0UL) /*!< HRPWM0_HRC SCR1: SCR1 (Bit 0) */ -#define HRPWM0_HRC_SCR1_SCR1_Msk \ - (0xffUL) /*!< HRPWM0_HRC SCR1: SCR1 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- HRPWM0_HRC_SCR2 ------------------------------ */ -#define HRPWM0_HRC_SCR2_SCR2_Pos \ - (0UL) /*!< HRPWM0_HRC SCR2: SCR2 (Bit 0) */ -#define HRPWM0_HRC_SCR2_SCR2_Msk \ - (0xffUL) /*!< HRPWM0_HRC SCR2: SCR2 (Bitfield-Mask: 0xff) */ - -/* ================================================================================ */ -/* ================ struct 'HRPWM0_HRC0' Position & Mask ================ */ -/* ================================================================================ */ - -/* ------------------------------- HRPWM0_HRC0_GC ------------------------------- */ -#define HRPWM0_HRC0_GC_HRM0_Pos \ - (0UL) /*!< HRPWM0_HRC0 GC: HRM0 (Bit 0) */ -#define HRPWM0_HRC0_GC_HRM0_Msk \ - (0x3UL) /*!< HRPWM0_HRC0 GC: HRM0 (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC0_GC_HRM1_Pos \ - (2UL) /*!< HRPWM0_HRC0 GC: HRM1 (Bit 2) */ -#define HRPWM0_HRC0_GC_HRM1_Msk \ - (0xcUL) /*!< HRPWM0_HRC0 GC: HRM1 (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC0_GC_DTE_Pos \ - (8UL) /*!< HRPWM0_HRC0 GC: DTE (Bit 8) */ -#define HRPWM0_HRC0_GC_DTE_Msk \ - (0x100UL) /*!< HRPWM0_HRC0 GC: DTE (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC0_GC_TR0E_Pos \ - (9UL) /*!< HRPWM0_HRC0 GC: TR0E (Bit 9) */ -#define HRPWM0_HRC0_GC_TR0E_Msk \ - (0x200UL) /*!< HRPWM0_HRC0 GC: TR0E (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC0_GC_TR1E_Pos \ - (10UL) /*!< HRPWM0_HRC0 GC: TR1E (Bit 10) */ -#define HRPWM0_HRC0_GC_TR1E_Msk \ - (0x400UL) /*!< HRPWM0_HRC0 GC: TR1E (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC0_GC_STC_Pos \ - (11UL) /*!< HRPWM0_HRC0 GC: STC (Bit 11) */ -#define HRPWM0_HRC0_GC_STC_Msk \ - (0x800UL) /*!< HRPWM0_HRC0 GC: STC (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC0_GC_DSTC_Pos \ - (12UL) /*!< HRPWM0_HRC0 GC: DSTC (Bit 12) */ -#define HRPWM0_HRC0_GC_DSTC_Msk \ - (0x1000UL) /*!< HRPWM0_HRC0 GC: DSTC (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC0_GC_OCS0_Pos \ - (13UL) /*!< HRPWM0_HRC0 GC: OCS0 (Bit 13) */ -#define HRPWM0_HRC0_GC_OCS0_Msk \ - (0x2000UL) /*!< HRPWM0_HRC0 GC: OCS0 (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC0_GC_OCS1_Pos \ - (14UL) /*!< HRPWM0_HRC0 GC: OCS1 (Bit 14) */ -#define HRPWM0_HRC0_GC_OCS1_Msk \ - (0x4000UL) /*!< HRPWM0_HRC0 GC: OCS1 (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC0_GC_DTUS_Pos \ - (16UL) /*!< HRPWM0_HRC0 GC: DTUS (Bit 16) */ -#define HRPWM0_HRC0_GC_DTUS_Msk \ - (0x10000UL) /*!< HRPWM0_HRC0 GC: DTUS (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_HRC0_PL ------------------------------- */ -#define HRPWM0_HRC0_PL_PSL0_Pos \ - (0UL) /*!< HRPWM0_HRC0 PL: PSL0 (Bit 0) */ -#define HRPWM0_HRC0_PL_PSL0_Msk \ - (0x1UL) /*!< HRPWM0_HRC0 PL: PSL0 (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC0_PL_PSL1_Pos \ - (1UL) /*!< HRPWM0_HRC0 PL: PSL1 (Bit 1) */ -#define HRPWM0_HRC0_PL_PSL1_Msk \ - (0x2UL) /*!< HRPWM0_HRC0 PL: PSL1 (Bitfield-Mask: 0x01) */ - -/* ------------------------------ HRPWM0_HRC0_GSEL ------------------------------ */ -#define HRPWM0_HRC0_GSEL_C0SS_Pos \ - (0UL) /*!< HRPWM0_HRC0 GSEL: C0SS (Bit 0) */ -#define HRPWM0_HRC0_GSEL_C0SS_Msk \ - (0x7UL) /*!< HRPWM0_HRC0 GSEL: C0SS (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC0_GSEL_C0CS_Pos \ - (3UL) /*!< HRPWM0_HRC0 GSEL: C0CS (Bit 3) */ -#define HRPWM0_HRC0_GSEL_C0CS_Msk \ - (0x38UL) /*!< HRPWM0_HRC0 GSEL: C0CS (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC0_GSEL_S0M_Pos \ - (6UL) /*!< HRPWM0_HRC0 GSEL: S0M (Bit 6) */ -#define HRPWM0_HRC0_GSEL_S0M_Msk \ - (0xc0UL) /*!< HRPWM0_HRC0 GSEL: S0M (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC0_GSEL_C0M_Pos \ - (8UL) /*!< HRPWM0_HRC0 GSEL: C0M (Bit 8) */ -#define HRPWM0_HRC0_GSEL_C0M_Msk \ - (0x300UL) /*!< HRPWM0_HRC0 GSEL: C0M (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC0_GSEL_S0ES_Pos \ - (10UL) /*!< HRPWM0_HRC0 GSEL: S0ES (Bit 10) */ -#define HRPWM0_HRC0_GSEL_S0ES_Msk \ - (0xc00UL) /*!< HRPWM0_HRC0 GSEL: S0ES (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC0_GSEL_C0ES_Pos \ - (12UL) /*!< HRPWM0_HRC0 GSEL: C0ES (Bit 12) */ -#define HRPWM0_HRC0_GSEL_C0ES_Msk \ - (0x3000UL) /*!< HRPWM0_HRC0 GSEL: C0ES (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC0_GSEL_C1SS_Pos \ - (16UL) /*!< HRPWM0_HRC0 GSEL: C1SS (Bit 16) */ -#define HRPWM0_HRC0_GSEL_C1SS_Msk \ - (0x70000UL) /*!< HRPWM0_HRC0 GSEL: C1SS (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC0_GSEL_C1CS_Pos \ - (19UL) /*!< HRPWM0_HRC0 GSEL: C1CS (Bit 19) */ -#define HRPWM0_HRC0_GSEL_C1CS_Msk \ - (0x380000UL) /*!< HRPWM0_HRC0 GSEL: C1CS (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC0_GSEL_S1M_Pos \ - (22UL) /*!< HRPWM0_HRC0 GSEL: S1M (Bit 22) */ -#define HRPWM0_HRC0_GSEL_S1M_Msk \ - (0xc00000UL) /*!< HRPWM0_HRC0 GSEL: S1M (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC0_GSEL_C1M_Pos \ - (24UL) /*!< HRPWM0_HRC0 GSEL: C1M (Bit 24) */ -#define HRPWM0_HRC0_GSEL_C1M_Msk \ - (0x3000000UL) /*!< HRPWM0_HRC0 GSEL: C1M (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC0_GSEL_S1ES_Pos \ - (26UL) /*!< HRPWM0_HRC0 GSEL: S1ES (Bit 26) */ -#define HRPWM0_HRC0_GSEL_S1ES_Msk \ - (0xc000000UL) /*!< HRPWM0_HRC0 GSEL: S1ES (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC0_GSEL_C1ES_Pos \ - (28UL) /*!< HRPWM0_HRC0 GSEL: C1ES (Bit 28) */ -#define HRPWM0_HRC0_GSEL_C1ES_Msk \ - (0x30000000UL) /*!< HRPWM0_HRC0 GSEL: C1ES (Bitfield-Mask: 0x03) */ - -/* ------------------------------ HRPWM0_HRC0_TSEL ------------------------------ */ -#define HRPWM0_HRC0_TSEL_TSEL0_Pos \ - (0UL) /*!< HRPWM0_HRC0 TSEL: TSEL0 (Bit 0) */ -#define HRPWM0_HRC0_TSEL_TSEL0_Msk \ - (0x7UL) /*!< HRPWM0_HRC0 TSEL: TSEL0 (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC0_TSEL_TSEL1_Pos \ - (3UL) /*!< HRPWM0_HRC0 TSEL: TSEL1 (Bit 3) */ -#define HRPWM0_HRC0_TSEL_TSEL1_Msk \ - (0x38UL) /*!< HRPWM0_HRC0 TSEL: TSEL1 (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC0_TSEL_TS0E_Pos \ - (16UL) /*!< HRPWM0_HRC0 TSEL: TS0E (Bit 16) */ -#define HRPWM0_HRC0_TSEL_TS0E_Msk \ - (0x10000UL) /*!< HRPWM0_HRC0 TSEL: TS0E (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC0_TSEL_TS1E_Pos \ - (17UL) /*!< HRPWM0_HRC0 TSEL: TS1E (Bit 17) */ -#define HRPWM0_HRC0_TSEL_TS1E_Msk \ - (0x20000UL) /*!< HRPWM0_HRC0 TSEL: TS1E (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_HRC0_SC ------------------------------- */ -#define HRPWM0_HRC0_SC_ST_Pos \ - (0UL) /*!< HRPWM0_HRC0 SC: ST (Bit 0) */ -#define HRPWM0_HRC0_SC_ST_Msk \ - (0x1UL) /*!< HRPWM0_HRC0 SC: ST (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_HRC0_DCR ------------------------------ */ -#define HRPWM0_HRC0_DCR_DTRV_Pos \ - (0UL) /*!< HRPWM0_HRC0 DCR: DTRV (Bit 0) */ -#define HRPWM0_HRC0_DCR_DTRV_Msk \ - (0xffffUL) /*!< HRPWM0_HRC0 DCR: DTRV (Bitfield-Mask: 0xffff) */ - -/* ------------------------------- HRPWM0_HRC0_DCF ------------------------------ */ -#define HRPWM0_HRC0_DCF_DTFV_Pos \ - (0UL) /*!< HRPWM0_HRC0 DCF: DTFV (Bit 0) */ -#define HRPWM0_HRC0_DCF_DTFV_Msk \ - (0xffffUL) /*!< HRPWM0_HRC0 DCF: DTFV (Bitfield-Mask: 0xffff) */ - -/* ------------------------------- HRPWM0_HRC0_CR1 ------------------------------ */ -#define HRPWM0_HRC0_CR1_CR1_Pos \ - (0UL) /*!< HRPWM0_HRC0 CR1: CR1 (Bit 0) */ -#define HRPWM0_HRC0_CR1_CR1_Msk \ - (0xffUL) /*!< HRPWM0_HRC0 CR1: CR1 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- HRPWM0_HRC0_CR2 ------------------------------ */ -#define HRPWM0_HRC0_CR2_CR2_Pos \ - (0UL) /*!< HRPWM0_HRC0 CR2: CR2 (Bit 0) */ -#define HRPWM0_HRC0_CR2_CR2_Msk \ - (0xffUL) /*!< HRPWM0_HRC0 CR2: CR2 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- HRPWM0_HRC0_SSC ------------------------------ */ -#define HRPWM0_HRC0_SSC_SST_Pos \ - (0UL) /*!< HRPWM0_HRC0 SSC: SST (Bit 0) */ -#define HRPWM0_HRC0_SSC_SST_Msk \ - (0x1UL) /*!< HRPWM0_HRC0 SSC: SST (Bitfield-Mask: 0x01) */ - -/* ------------------------------ HRPWM0_HRC0_SDCR ------------------------------ */ -#define HRPWM0_HRC0_SDCR_SDTRV_Pos \ - (0UL) /*!< HRPWM0_HRC0 SDCR: SDTRV (Bit 0) */ -#define HRPWM0_HRC0_SDCR_SDTRV_Msk \ - (0xffffUL) /*!< HRPWM0_HRC0 SDCR: SDTRV (Bitfield-Mask: 0xffff) */ - -/* ------------------------------ HRPWM0_HRC0_SDCF ------------------------------ */ -#define HRPWM0_HRC0_SDCF_SDTFV_Pos \ - (0UL) /*!< HRPWM0_HRC0 SDCF: SDTFV (Bit 0) */ -#define HRPWM0_HRC0_SDCF_SDTFV_Msk \ - (0xffffUL) /*!< HRPWM0_HRC0 SDCF: SDTFV (Bitfield-Mask: 0xffff) */ - -/* ------------------------------ HRPWM0_HRC0_SCR1 ------------------------------ */ -#define HRPWM0_HRC0_SCR1_SCR1_Pos \ - (0UL) /*!< HRPWM0_HRC0 SCR1: SCR1 (Bit 0) */ -#define HRPWM0_HRC0_SCR1_SCR1_Msk \ - (0xffUL) /*!< HRPWM0_HRC0 SCR1: SCR1 (Bitfield-Mask: 0xff) */ - -/* ------------------------------ HRPWM0_HRC0_SCR2 ------------------------------ */ -#define HRPWM0_HRC0_SCR2_SCR2_Pos \ - (0UL) /*!< HRPWM0_HRC0 SCR2: SCR2 (Bit 0) */ -#define HRPWM0_HRC0_SCR2_SCR2_Msk \ - (0xffUL) /*!< HRPWM0_HRC0 SCR2: SCR2 (Bitfield-Mask: 0xff) */ - -/* ================================================================================ */ -/* ================ struct 'HRPWM0_HRC1' Position & Mask ================ */ -/* ================================================================================ */ - -/* ------------------------------- HRPWM0_HRC1_GC ------------------------------- */ -#define HRPWM0_HRC1_GC_HRM0_Pos \ - (0UL) /*!< HRPWM0_HRC1 GC: HRM0 (Bit 0) */ -#define HRPWM0_HRC1_GC_HRM0_Msk \ - (0x3UL) /*!< HRPWM0_HRC1 GC: HRM0 (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC1_GC_HRM1_Pos \ - (2UL) /*!< HRPWM0_HRC1 GC: HRM1 (Bit 2) */ -#define HRPWM0_HRC1_GC_HRM1_Msk \ - (0xcUL) /*!< HRPWM0_HRC1 GC: HRM1 (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC1_GC_DTE_Pos \ - (8UL) /*!< HRPWM0_HRC1 GC: DTE (Bit 8) */ -#define HRPWM0_HRC1_GC_DTE_Msk \ - (0x100UL) /*!< HRPWM0_HRC1 GC: DTE (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC1_GC_TR0E_Pos \ - (9UL) /*!< HRPWM0_HRC1 GC: TR0E (Bit 9) */ -#define HRPWM0_HRC1_GC_TR0E_Msk \ - (0x200UL) /*!< HRPWM0_HRC1 GC: TR0E (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC1_GC_TR1E_Pos \ - (10UL) /*!< HRPWM0_HRC1 GC: TR1E (Bit 10) */ -#define HRPWM0_HRC1_GC_TR1E_Msk \ - (0x400UL) /*!< HRPWM0_HRC1 GC: TR1E (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC1_GC_STC_Pos \ - (11UL) /*!< HRPWM0_HRC1 GC: STC (Bit 11) */ -#define HRPWM0_HRC1_GC_STC_Msk \ - (0x800UL) /*!< HRPWM0_HRC1 GC: STC (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC1_GC_DSTC_Pos \ - (12UL) /*!< HRPWM0_HRC1 GC: DSTC (Bit 12) */ -#define HRPWM0_HRC1_GC_DSTC_Msk \ - (0x1000UL) /*!< HRPWM0_HRC1 GC: DSTC (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC1_GC_OCS0_Pos \ - (13UL) /*!< HRPWM0_HRC1 GC: OCS0 (Bit 13) */ -#define HRPWM0_HRC1_GC_OCS0_Msk \ - (0x2000UL) /*!< HRPWM0_HRC1 GC: OCS0 (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC1_GC_OCS1_Pos \ - (14UL) /*!< HRPWM0_HRC1 GC: OCS1 (Bit 14) */ -#define HRPWM0_HRC1_GC_OCS1_Msk \ - (0x4000UL) /*!< HRPWM0_HRC1 GC: OCS1 (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC1_GC_DTUS_Pos \ - (16UL) /*!< HRPWM0_HRC1 GC: DTUS (Bit 16) */ -#define HRPWM0_HRC1_GC_DTUS_Msk \ - (0x10000UL) /*!< HRPWM0_HRC1 GC: DTUS (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_HRC1_PL ------------------------------- */ -#define HRPWM0_HRC1_PL_PSL0_Pos \ - (0UL) /*!< HRPWM0_HRC1 PL: PSL0 (Bit 0) */ -#define HRPWM0_HRC1_PL_PSL0_Msk \ - (0x1UL) /*!< HRPWM0_HRC1 PL: PSL0 (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC1_PL_PSL1_Pos \ - (1UL) /*!< HRPWM0_HRC1 PL: PSL1 (Bit 1) */ -#define HRPWM0_HRC1_PL_PSL1_Msk \ - (0x2UL) /*!< HRPWM0_HRC1 PL: PSL1 (Bitfield-Mask: 0x01) */ - -/* ------------------------------ HRPWM0_HRC1_GSEL ------------------------------ */ -#define HRPWM0_HRC1_GSEL_C0SS_Pos \ - (0UL) /*!< HRPWM0_HRC1 GSEL: C0SS (Bit 0) */ -#define HRPWM0_HRC1_GSEL_C0SS_Msk \ - (0x7UL) /*!< HRPWM0_HRC1 GSEL: C0SS (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC1_GSEL_C0CS_Pos \ - (3UL) /*!< HRPWM0_HRC1 GSEL: C0CS (Bit 3) */ -#define HRPWM0_HRC1_GSEL_C0CS_Msk \ - (0x38UL) /*!< HRPWM0_HRC1 GSEL: C0CS (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC1_GSEL_S0M_Pos \ - (6UL) /*!< HRPWM0_HRC1 GSEL: S0M (Bit 6) */ -#define HRPWM0_HRC1_GSEL_S0M_Msk \ - (0xc0UL) /*!< HRPWM0_HRC1 GSEL: S0M (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC1_GSEL_C0M_Pos \ - (8UL) /*!< HRPWM0_HRC1 GSEL: C0M (Bit 8) */ -#define HRPWM0_HRC1_GSEL_C0M_Msk \ - (0x300UL) /*!< HRPWM0_HRC1 GSEL: C0M (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC1_GSEL_S0ES_Pos \ - (10UL) /*!< HRPWM0_HRC1 GSEL: S0ES (Bit 10) */ -#define HRPWM0_HRC1_GSEL_S0ES_Msk \ - (0xc00UL) /*!< HRPWM0_HRC1 GSEL: S0ES (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC1_GSEL_C0ES_Pos \ - (12UL) /*!< HRPWM0_HRC1 GSEL: C0ES (Bit 12) */ -#define HRPWM0_HRC1_GSEL_C0ES_Msk \ - (0x3000UL) /*!< HRPWM0_HRC1 GSEL: C0ES (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC1_GSEL_C1SS_Pos \ - (16UL) /*!< HRPWM0_HRC1 GSEL: C1SS (Bit 16) */ -#define HRPWM0_HRC1_GSEL_C1SS_Msk \ - (0x70000UL) /*!< HRPWM0_HRC1 GSEL: C1SS (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC1_GSEL_C1CS_Pos \ - (19UL) /*!< HRPWM0_HRC1 GSEL: C1CS (Bit 19) */ -#define HRPWM0_HRC1_GSEL_C1CS_Msk \ - (0x380000UL) /*!< HRPWM0_HRC1 GSEL: C1CS (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC1_GSEL_S1M_Pos \ - (22UL) /*!< HRPWM0_HRC1 GSEL: S1M (Bit 22) */ -#define HRPWM0_HRC1_GSEL_S1M_Msk \ - (0xc00000UL) /*!< HRPWM0_HRC1 GSEL: S1M (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC1_GSEL_C1M_Pos \ - (24UL) /*!< HRPWM0_HRC1 GSEL: C1M (Bit 24) */ -#define HRPWM0_HRC1_GSEL_C1M_Msk \ - (0x3000000UL) /*!< HRPWM0_HRC1 GSEL: C1M (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC1_GSEL_S1ES_Pos \ - (26UL) /*!< HRPWM0_HRC1 GSEL: S1ES (Bit 26) */ -#define HRPWM0_HRC1_GSEL_S1ES_Msk \ - (0xc000000UL) /*!< HRPWM0_HRC1 GSEL: S1ES (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC1_GSEL_C1ES_Pos \ - (28UL) /*!< HRPWM0_HRC1 GSEL: C1ES (Bit 28) */ -#define HRPWM0_HRC1_GSEL_C1ES_Msk \ - (0x30000000UL) /*!< HRPWM0_HRC1 GSEL: C1ES (Bitfield-Mask: 0x03) */ - -/* ------------------------------ HRPWM0_HRC1_TSEL ------------------------------ */ -#define HRPWM0_HRC1_TSEL_TSEL0_Pos \ - (0UL) /*!< HRPWM0_HRC1 TSEL: TSEL0 (Bit 0) */ -#define HRPWM0_HRC1_TSEL_TSEL0_Msk \ - (0x7UL) /*!< HRPWM0_HRC1 TSEL: TSEL0 (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC1_TSEL_TSEL1_Pos \ - (3UL) /*!< HRPWM0_HRC1 TSEL: TSEL1 (Bit 3) */ -#define HRPWM0_HRC1_TSEL_TSEL1_Msk \ - (0x38UL) /*!< HRPWM0_HRC1 TSEL: TSEL1 (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC1_TSEL_TS0E_Pos \ - (16UL) /*!< HRPWM0_HRC1 TSEL: TS0E (Bit 16) */ -#define HRPWM0_HRC1_TSEL_TS0E_Msk \ - (0x10000UL) /*!< HRPWM0_HRC1 TSEL: TS0E (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC1_TSEL_TS1E_Pos \ - (17UL) /*!< HRPWM0_HRC1 TSEL: TS1E (Bit 17) */ -#define HRPWM0_HRC1_TSEL_TS1E_Msk \ - (0x20000UL) /*!< HRPWM0_HRC1 TSEL: TS1E (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_HRC1_SC ------------------------------- */ -#define HRPWM0_HRC1_SC_ST_Pos \ - (0UL) /*!< HRPWM0_HRC1 SC: ST (Bit 0) */ -#define HRPWM0_HRC1_SC_ST_Msk \ - (0x1UL) /*!< HRPWM0_HRC1 SC: ST (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_HRC1_DCR ------------------------------ */ -#define HRPWM0_HRC1_DCR_DTRV_Pos \ - (0UL) /*!< HRPWM0_HRC1 DCR: DTRV (Bit 0) */ -#define HRPWM0_HRC1_DCR_DTRV_Msk \ - (0xffffUL) /*!< HRPWM0_HRC1 DCR: DTRV (Bitfield-Mask: 0xffff) */ - -/* ------------------------------- HRPWM0_HRC1_DCF ------------------------------ */ -#define HRPWM0_HRC1_DCF_DTFV_Pos \ - (0UL) /*!< HRPWM0_HRC1 DCF: DTFV (Bit 0) */ -#define HRPWM0_HRC1_DCF_DTFV_Msk \ - (0xffffUL) /*!< HRPWM0_HRC1 DCF: DTFV (Bitfield-Mask: 0xffff) */ - -/* ------------------------------- HRPWM0_HRC1_CR1 ------------------------------ */ -#define HRPWM0_HRC1_CR1_CR1_Pos \ - (0UL) /*!< HRPWM0_HRC1 CR1: CR1 (Bit 0) */ -#define HRPWM0_HRC1_CR1_CR1_Msk \ - (0xffUL) /*!< HRPWM0_HRC1 CR1: CR1 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- HRPWM0_HRC1_CR2 ------------------------------ */ -#define HRPWM0_HRC1_CR2_CR2_Pos \ - (0UL) /*!< HRPWM0_HRC1 CR2: CR2 (Bit 0) */ -#define HRPWM0_HRC1_CR2_CR2_Msk \ - (0xffUL) /*!< HRPWM0_HRC1 CR2: CR2 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- HRPWM0_HRC1_SSC ------------------------------ */ -#define HRPWM0_HRC1_SSC_SST_Pos \ - (0UL) /*!< HRPWM0_HRC1 SSC: SST (Bit 0) */ -#define HRPWM0_HRC1_SSC_SST_Msk \ - (0x1UL) /*!< HRPWM0_HRC1 SSC: SST (Bitfield-Mask: 0x01) */ - -/* ------------------------------ HRPWM0_HRC1_SDCR ------------------------------ */ -#define HRPWM0_HRC1_SDCR_SDTRV_Pos \ - (0UL) /*!< HRPWM0_HRC1 SDCR: SDTRV (Bit 0) */ -#define HRPWM0_HRC1_SDCR_SDTRV_Msk \ - (0xffffUL) /*!< HRPWM0_HRC1 SDCR: SDTRV (Bitfield-Mask: 0xffff) */ - -/* ------------------------------ HRPWM0_HRC1_SDCF ------------------------------ */ -#define HRPWM0_HRC1_SDCF_SDTFV_Pos \ - (0UL) /*!< HRPWM0_HRC1 SDCF: SDTFV (Bit 0) */ -#define HRPWM0_HRC1_SDCF_SDTFV_Msk \ - (0xffffUL) /*!< HRPWM0_HRC1 SDCF: SDTFV (Bitfield-Mask: 0xffff) */ - -/* ------------------------------ HRPWM0_HRC1_SCR1 ------------------------------ */ -#define HRPWM0_HRC1_SCR1_SCR1_Pos \ - (0UL) /*!< HRPWM0_HRC1 SCR1: SCR1 (Bit 0) */ -#define HRPWM0_HRC1_SCR1_SCR1_Msk \ - (0xffUL) /*!< HRPWM0_HRC1 SCR1: SCR1 (Bitfield-Mask: 0xff) */ - -/* ------------------------------ HRPWM0_HRC1_SCR2 ------------------------------ */ -#define HRPWM0_HRC1_SCR2_SCR2_Pos \ - (0UL) /*!< HRPWM0_HRC1 SCR2: SCR2 (Bit 0) */ -#define HRPWM0_HRC1_SCR2_SCR2_Msk \ - (0xffUL) /*!< HRPWM0_HRC1 SCR2: SCR2 (Bitfield-Mask: 0xff) */ - -/* ================================================================================ */ -/* ================ struct 'HRPWM0_HRC2' Position & Mask ================ */ -/* ================================================================================ */ - -/* ------------------------------- HRPWM0_HRC2_GC ------------------------------- */ -#define HRPWM0_HRC2_GC_HRM0_Pos \ - (0UL) /*!< HRPWM0_HRC2 GC: HRM0 (Bit 0) */ -#define HRPWM0_HRC2_GC_HRM0_Msk \ - (0x3UL) /*!< HRPWM0_HRC2 GC: HRM0 (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC2_GC_HRM1_Pos \ - (2UL) /*!< HRPWM0_HRC2 GC: HRM1 (Bit 2) */ -#define HRPWM0_HRC2_GC_HRM1_Msk \ - (0xcUL) /*!< HRPWM0_HRC2 GC: HRM1 (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC2_GC_DTE_Pos \ - (8UL) /*!< HRPWM0_HRC2 GC: DTE (Bit 8) */ -#define HRPWM0_HRC2_GC_DTE_Msk \ - (0x100UL) /*!< HRPWM0_HRC2 GC: DTE (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC2_GC_TR0E_Pos \ - (9UL) /*!< HRPWM0_HRC2 GC: TR0E (Bit 9) */ -#define HRPWM0_HRC2_GC_TR0E_Msk \ - (0x200UL) /*!< HRPWM0_HRC2 GC: TR0E (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC2_GC_TR1E_Pos \ - (10UL) /*!< HRPWM0_HRC2 GC: TR1E (Bit 10) */ -#define HRPWM0_HRC2_GC_TR1E_Msk \ - (0x400UL) /*!< HRPWM0_HRC2 GC: TR1E (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC2_GC_STC_Pos \ - (11UL) /*!< HRPWM0_HRC2 GC: STC (Bit 11) */ -#define HRPWM0_HRC2_GC_STC_Msk \ - (0x800UL) /*!< HRPWM0_HRC2 GC: STC (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC2_GC_DSTC_Pos \ - (12UL) /*!< HRPWM0_HRC2 GC: DSTC (Bit 12) */ -#define HRPWM0_HRC2_GC_DSTC_Msk \ - (0x1000UL) /*!< HRPWM0_HRC2 GC: DSTC (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC2_GC_OCS0_Pos \ - (13UL) /*!< HRPWM0_HRC2 GC: OCS0 (Bit 13) */ -#define HRPWM0_HRC2_GC_OCS0_Msk \ - (0x2000UL) /*!< HRPWM0_HRC2 GC: OCS0 (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC2_GC_OCS1_Pos \ - (14UL) /*!< HRPWM0_HRC2 GC: OCS1 (Bit 14) */ -#define HRPWM0_HRC2_GC_OCS1_Msk \ - (0x4000UL) /*!< HRPWM0_HRC2 GC: OCS1 (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC2_GC_DTUS_Pos \ - (16UL) /*!< HRPWM0_HRC2 GC: DTUS (Bit 16) */ -#define HRPWM0_HRC2_GC_DTUS_Msk \ - (0x10000UL) /*!< HRPWM0_HRC2 GC: DTUS (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_HRC2_PL ------------------------------- */ -#define HRPWM0_HRC2_PL_PSL0_Pos \ - (0UL) /*!< HRPWM0_HRC2 PL: PSL0 (Bit 0) */ -#define HRPWM0_HRC2_PL_PSL0_Msk \ - (0x1UL) /*!< HRPWM0_HRC2 PL: PSL0 (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC2_PL_PSL1_Pos \ - (1UL) /*!< HRPWM0_HRC2 PL: PSL1 (Bit 1) */ -#define HRPWM0_HRC2_PL_PSL1_Msk \ - (0x2UL) /*!< HRPWM0_HRC2 PL: PSL1 (Bitfield-Mask: 0x01) */ - -/* ------------------------------ HRPWM0_HRC2_GSEL ------------------------------ */ -#define HRPWM0_HRC2_GSEL_C0SS_Pos \ - (0UL) /*!< HRPWM0_HRC2 GSEL: C0SS (Bit 0) */ -#define HRPWM0_HRC2_GSEL_C0SS_Msk \ - (0x7UL) /*!< HRPWM0_HRC2 GSEL: C0SS (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC2_GSEL_C0CS_Pos \ - (3UL) /*!< HRPWM0_HRC2 GSEL: C0CS (Bit 3) */ -#define HRPWM0_HRC2_GSEL_C0CS_Msk \ - (0x38UL) /*!< HRPWM0_HRC2 GSEL: C0CS (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC2_GSEL_S0M_Pos \ - (6UL) /*!< HRPWM0_HRC2 GSEL: S0M (Bit 6) */ -#define HRPWM0_HRC2_GSEL_S0M_Msk \ - (0xc0UL) /*!< HRPWM0_HRC2 GSEL: S0M (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC2_GSEL_C0M_Pos \ - (8UL) /*!< HRPWM0_HRC2 GSEL: C0M (Bit 8) */ -#define HRPWM0_HRC2_GSEL_C0M_Msk \ - (0x300UL) /*!< HRPWM0_HRC2 GSEL: C0M (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC2_GSEL_S0ES_Pos \ - (10UL) /*!< HRPWM0_HRC2 GSEL: S0ES (Bit 10) */ -#define HRPWM0_HRC2_GSEL_S0ES_Msk \ - (0xc00UL) /*!< HRPWM0_HRC2 GSEL: S0ES (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC2_GSEL_C0ES_Pos \ - (12UL) /*!< HRPWM0_HRC2 GSEL: C0ES (Bit 12) */ -#define HRPWM0_HRC2_GSEL_C0ES_Msk \ - (0x3000UL) /*!< HRPWM0_HRC2 GSEL: C0ES (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC2_GSEL_C1SS_Pos \ - (16UL) /*!< HRPWM0_HRC2 GSEL: C1SS (Bit 16) */ -#define HRPWM0_HRC2_GSEL_C1SS_Msk \ - (0x70000UL) /*!< HRPWM0_HRC2 GSEL: C1SS (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC2_GSEL_C1CS_Pos \ - (19UL) /*!< HRPWM0_HRC2 GSEL: C1CS (Bit 19) */ -#define HRPWM0_HRC2_GSEL_C1CS_Msk \ - (0x380000UL) /*!< HRPWM0_HRC2 GSEL: C1CS (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC2_GSEL_S1M_Pos \ - (22UL) /*!< HRPWM0_HRC2 GSEL: S1M (Bit 22) */ -#define HRPWM0_HRC2_GSEL_S1M_Msk \ - (0xc00000UL) /*!< HRPWM0_HRC2 GSEL: S1M (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC2_GSEL_C1M_Pos \ - (24UL) /*!< HRPWM0_HRC2 GSEL: C1M (Bit 24) */ -#define HRPWM0_HRC2_GSEL_C1M_Msk \ - (0x3000000UL) /*!< HRPWM0_HRC2 GSEL: C1M (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC2_GSEL_S1ES_Pos \ - (26UL) /*!< HRPWM0_HRC2 GSEL: S1ES (Bit 26) */ -#define HRPWM0_HRC2_GSEL_S1ES_Msk \ - (0xc000000UL) /*!< HRPWM0_HRC2 GSEL: S1ES (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC2_GSEL_C1ES_Pos \ - (28UL) /*!< HRPWM0_HRC2 GSEL: C1ES (Bit 28) */ -#define HRPWM0_HRC2_GSEL_C1ES_Msk \ - (0x30000000UL) /*!< HRPWM0_HRC2 GSEL: C1ES (Bitfield-Mask: 0x03) */ - -/* ------------------------------ HRPWM0_HRC2_TSEL ------------------------------ */ -#define HRPWM0_HRC2_TSEL_TSEL0_Pos \ - (0UL) /*!< HRPWM0_HRC2 TSEL: TSEL0 (Bit 0) */ -#define HRPWM0_HRC2_TSEL_TSEL0_Msk \ - (0x7UL) /*!< HRPWM0_HRC2 TSEL: TSEL0 (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC2_TSEL_TSEL1_Pos \ - (3UL) /*!< HRPWM0_HRC2 TSEL: TSEL1 (Bit 3) */ -#define HRPWM0_HRC2_TSEL_TSEL1_Msk \ - (0x38UL) /*!< HRPWM0_HRC2 TSEL: TSEL1 (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC2_TSEL_TS0E_Pos \ - (16UL) /*!< HRPWM0_HRC2 TSEL: TS0E (Bit 16) */ -#define HRPWM0_HRC2_TSEL_TS0E_Msk \ - (0x10000UL) /*!< HRPWM0_HRC2 TSEL: TS0E (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC2_TSEL_TS1E_Pos \ - (17UL) /*!< HRPWM0_HRC2 TSEL: TS1E (Bit 17) */ -#define HRPWM0_HRC2_TSEL_TS1E_Msk \ - (0x20000UL) /*!< HRPWM0_HRC2 TSEL: TS1E (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_HRC2_SC ------------------------------- */ -#define HRPWM0_HRC2_SC_ST_Pos \ - (0UL) /*!< HRPWM0_HRC2 SC: ST (Bit 0) */ -#define HRPWM0_HRC2_SC_ST_Msk \ - (0x1UL) /*!< HRPWM0_HRC2 SC: ST (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_HRC2_DCR ------------------------------ */ -#define HRPWM0_HRC2_DCR_DTRV_Pos \ - (0UL) /*!< HRPWM0_HRC2 DCR: DTRV (Bit 0) */ -#define HRPWM0_HRC2_DCR_DTRV_Msk \ - (0xffffUL) /*!< HRPWM0_HRC2 DCR: DTRV (Bitfield-Mask: 0xffff) */ - -/* ------------------------------- HRPWM0_HRC2_DCF ------------------------------ */ -#define HRPWM0_HRC2_DCF_DTFV_Pos \ - (0UL) /*!< HRPWM0_HRC2 DCF: DTFV (Bit 0) */ -#define HRPWM0_HRC2_DCF_DTFV_Msk \ - (0xffffUL) /*!< HRPWM0_HRC2 DCF: DTFV (Bitfield-Mask: 0xffff) */ - -/* ------------------------------- HRPWM0_HRC2_CR1 ------------------------------ */ -#define HRPWM0_HRC2_CR1_CR1_Pos \ - (0UL) /*!< HRPWM0_HRC2 CR1: CR1 (Bit 0) */ -#define HRPWM0_HRC2_CR1_CR1_Msk \ - (0xffUL) /*!< HRPWM0_HRC2 CR1: CR1 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- HRPWM0_HRC2_CR2 ------------------------------ */ -#define HRPWM0_HRC2_CR2_CR2_Pos \ - (0UL) /*!< HRPWM0_HRC2 CR2: CR2 (Bit 0) */ -#define HRPWM0_HRC2_CR2_CR2_Msk \ - (0xffUL) /*!< HRPWM0_HRC2 CR2: CR2 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- HRPWM0_HRC2_SSC ------------------------------ */ -#define HRPWM0_HRC2_SSC_SST_Pos \ - (0UL) /*!< HRPWM0_HRC2 SSC: SST (Bit 0) */ -#define HRPWM0_HRC2_SSC_SST_Msk \ - (0x1UL) /*!< HRPWM0_HRC2 SSC: SST (Bitfield-Mask: 0x01) */ - -/* ------------------------------ HRPWM0_HRC2_SDCR ------------------------------ */ -#define HRPWM0_HRC2_SDCR_SDTRV_Pos \ - (0UL) /*!< HRPWM0_HRC2 SDCR: SDTRV (Bit 0) */ -#define HRPWM0_HRC2_SDCR_SDTRV_Msk \ - (0xffffUL) /*!< HRPWM0_HRC2 SDCR: SDTRV (Bitfield-Mask: 0xffff) */ - -/* ------------------------------ HRPWM0_HRC2_SDCF ------------------------------ */ -#define HRPWM0_HRC2_SDCF_SDTFV_Pos \ - (0UL) /*!< HRPWM0_HRC2 SDCF: SDTFV (Bit 0) */ -#define HRPWM0_HRC2_SDCF_SDTFV_Msk \ - (0xffffUL) /*!< HRPWM0_HRC2 SDCF: SDTFV (Bitfield-Mask: 0xffff) */ - -/* ------------------------------ HRPWM0_HRC2_SCR1 ------------------------------ */ -#define HRPWM0_HRC2_SCR1_SCR1_Pos \ - (0UL) /*!< HRPWM0_HRC2 SCR1: SCR1 (Bit 0) */ -#define HRPWM0_HRC2_SCR1_SCR1_Msk \ - (0xffUL) /*!< HRPWM0_HRC2 SCR1: SCR1 (Bitfield-Mask: 0xff) */ - -/* ------------------------------ HRPWM0_HRC2_SCR2 ------------------------------ */ -#define HRPWM0_HRC2_SCR2_SCR2_Pos \ - (0UL) /*!< HRPWM0_HRC2 SCR2: SCR2 (Bit 0) */ -#define HRPWM0_HRC2_SCR2_SCR2_Msk \ - (0xffUL) /*!< HRPWM0_HRC2 SCR2: SCR2 (Bitfield-Mask: 0xff) */ - -/* ================================================================================ */ -/* ================ struct 'HRPWM0_HRC3' Position & Mask ================ */ -/* ================================================================================ */ - -/* ------------------------------- HRPWM0_HRC3_GC ------------------------------- */ -#define HRPWM0_HRC3_GC_HRM0_Pos \ - (0UL) /*!< HRPWM0_HRC3 GC: HRM0 (Bit 0) */ -#define HRPWM0_HRC3_GC_HRM0_Msk \ - (0x3UL) /*!< HRPWM0_HRC3 GC: HRM0 (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC3_GC_HRM1_Pos \ - (2UL) /*!< HRPWM0_HRC3 GC: HRM1 (Bit 2) */ -#define HRPWM0_HRC3_GC_HRM1_Msk \ - (0xcUL) /*!< HRPWM0_HRC3 GC: HRM1 (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC3_GC_DTE_Pos \ - (8UL) /*!< HRPWM0_HRC3 GC: DTE (Bit 8) */ -#define HRPWM0_HRC3_GC_DTE_Msk \ - (0x100UL) /*!< HRPWM0_HRC3 GC: DTE (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC3_GC_TR0E_Pos \ - (9UL) /*!< HRPWM0_HRC3 GC: TR0E (Bit 9) */ -#define HRPWM0_HRC3_GC_TR0E_Msk \ - (0x200UL) /*!< HRPWM0_HRC3 GC: TR0E (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC3_GC_TR1E_Pos \ - (10UL) /*!< HRPWM0_HRC3 GC: TR1E (Bit 10) */ -#define HRPWM0_HRC3_GC_TR1E_Msk \ - (0x400UL) /*!< HRPWM0_HRC3 GC: TR1E (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC3_GC_STC_Pos \ - (11UL) /*!< HRPWM0_HRC3 GC: STC (Bit 11) */ -#define HRPWM0_HRC3_GC_STC_Msk \ - (0x800UL) /*!< HRPWM0_HRC3 GC: STC (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC3_GC_DSTC_Pos \ - (12UL) /*!< HRPWM0_HRC3 GC: DSTC (Bit 12) */ -#define HRPWM0_HRC3_GC_DSTC_Msk \ - (0x1000UL) /*!< HRPWM0_HRC3 GC: DSTC (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC3_GC_OCS0_Pos \ - (13UL) /*!< HRPWM0_HRC3 GC: OCS0 (Bit 13) */ -#define HRPWM0_HRC3_GC_OCS0_Msk \ - (0x2000UL) /*!< HRPWM0_HRC3 GC: OCS0 (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC3_GC_OCS1_Pos \ - (14UL) /*!< HRPWM0_HRC3 GC: OCS1 (Bit 14) */ -#define HRPWM0_HRC3_GC_OCS1_Msk \ - (0x4000UL) /*!< HRPWM0_HRC3 GC: OCS1 (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC3_GC_DTUS_Pos \ - (16UL) /*!< HRPWM0_HRC3 GC: DTUS (Bit 16) */ -#define HRPWM0_HRC3_GC_DTUS_Msk \ - (0x10000UL) /*!< HRPWM0_HRC3 GC: DTUS (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_HRC3_PL ------------------------------- */ -#define HRPWM0_HRC3_PL_PSL0_Pos \ - (0UL) /*!< HRPWM0_HRC3 PL: PSL0 (Bit 0) */ -#define HRPWM0_HRC3_PL_PSL0_Msk \ - (0x1UL) /*!< HRPWM0_HRC3 PL: PSL0 (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC3_PL_PSL1_Pos \ - (1UL) /*!< HRPWM0_HRC3 PL: PSL1 (Bit 1) */ -#define HRPWM0_HRC3_PL_PSL1_Msk \ - (0x2UL) /*!< HRPWM0_HRC3 PL: PSL1 (Bitfield-Mask: 0x01) */ - -/* ------------------------------ HRPWM0_HRC3_GSEL ------------------------------ */ -#define HRPWM0_HRC3_GSEL_C0SS_Pos \ - (0UL) /*!< HRPWM0_HRC3 GSEL: C0SS (Bit 0) */ -#define HRPWM0_HRC3_GSEL_C0SS_Msk \ - (0x7UL) /*!< HRPWM0_HRC3 GSEL: C0SS (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC3_GSEL_C0CS_Pos \ - (3UL) /*!< HRPWM0_HRC3 GSEL: C0CS (Bit 3) */ -#define HRPWM0_HRC3_GSEL_C0CS_Msk \ - (0x38UL) /*!< HRPWM0_HRC3 GSEL: C0CS (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC3_GSEL_S0M_Pos \ - (6UL) /*!< HRPWM0_HRC3 GSEL: S0M (Bit 6) */ -#define HRPWM0_HRC3_GSEL_S0M_Msk \ - (0xc0UL) /*!< HRPWM0_HRC3 GSEL: S0M (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC3_GSEL_C0M_Pos \ - (8UL) /*!< HRPWM0_HRC3 GSEL: C0M (Bit 8) */ -#define HRPWM0_HRC3_GSEL_C0M_Msk \ - (0x300UL) /*!< HRPWM0_HRC3 GSEL: C0M (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC3_GSEL_S0ES_Pos \ - (10UL) /*!< HRPWM0_HRC3 GSEL: S0ES (Bit 10) */ -#define HRPWM0_HRC3_GSEL_S0ES_Msk \ - (0xc00UL) /*!< HRPWM0_HRC3 GSEL: S0ES (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC3_GSEL_C0ES_Pos \ - (12UL) /*!< HRPWM0_HRC3 GSEL: C0ES (Bit 12) */ -#define HRPWM0_HRC3_GSEL_C0ES_Msk \ - (0x3000UL) /*!< HRPWM0_HRC3 GSEL: C0ES (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC3_GSEL_C1SS_Pos \ - (16UL) /*!< HRPWM0_HRC3 GSEL: C1SS (Bit 16) */ -#define HRPWM0_HRC3_GSEL_C1SS_Msk \ - (0x70000UL) /*!< HRPWM0_HRC3 GSEL: C1SS (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC3_GSEL_C1CS_Pos \ - (19UL) /*!< HRPWM0_HRC3 GSEL: C1CS (Bit 19) */ -#define HRPWM0_HRC3_GSEL_C1CS_Msk \ - (0x380000UL) /*!< HRPWM0_HRC3 GSEL: C1CS (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC3_GSEL_S1M_Pos \ - (22UL) /*!< HRPWM0_HRC3 GSEL: S1M (Bit 22) */ -#define HRPWM0_HRC3_GSEL_S1M_Msk \ - (0xc00000UL) /*!< HRPWM0_HRC3 GSEL: S1M (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC3_GSEL_C1M_Pos \ - (24UL) /*!< HRPWM0_HRC3 GSEL: C1M (Bit 24) */ -#define HRPWM0_HRC3_GSEL_C1M_Msk \ - (0x3000000UL) /*!< HRPWM0_HRC3 GSEL: C1M (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC3_GSEL_S1ES_Pos \ - (26UL) /*!< HRPWM0_HRC3 GSEL: S1ES (Bit 26) */ -#define HRPWM0_HRC3_GSEL_S1ES_Msk \ - (0xc000000UL) /*!< HRPWM0_HRC3 GSEL: S1ES (Bitfield-Mask: 0x03) */ -#define HRPWM0_HRC3_GSEL_C1ES_Pos \ - (28UL) /*!< HRPWM0_HRC3 GSEL: C1ES (Bit 28) */ -#define HRPWM0_HRC3_GSEL_C1ES_Msk \ - (0x30000000UL) /*!< HRPWM0_HRC3 GSEL: C1ES (Bitfield-Mask: 0x03) */ - -/* ------------------------------ HRPWM0_HRC3_TSEL ------------------------------ */ -#define HRPWM0_HRC3_TSEL_TSEL0_Pos \ - (0UL) /*!< HRPWM0_HRC3 TSEL: TSEL0 (Bit 0) */ -#define HRPWM0_HRC3_TSEL_TSEL0_Msk \ - (0x7UL) /*!< HRPWM0_HRC3 TSEL: TSEL0 (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC3_TSEL_TSEL1_Pos \ - (3UL) /*!< HRPWM0_HRC3 TSEL: TSEL1 (Bit 3) */ -#define HRPWM0_HRC3_TSEL_TSEL1_Msk \ - (0x38UL) /*!< HRPWM0_HRC3 TSEL: TSEL1 (Bitfield-Mask: 0x07) */ -#define HRPWM0_HRC3_TSEL_TS0E_Pos \ - (16UL) /*!< HRPWM0_HRC3 TSEL: TS0E (Bit 16) */ -#define HRPWM0_HRC3_TSEL_TS0E_Msk \ - (0x10000UL) /*!< HRPWM0_HRC3 TSEL: TS0E (Bitfield-Mask: 0x01) */ -#define HRPWM0_HRC3_TSEL_TS1E_Pos \ - (17UL) /*!< HRPWM0_HRC3 TSEL: TS1E (Bit 17) */ -#define HRPWM0_HRC3_TSEL_TS1E_Msk \ - (0x20000UL) /*!< HRPWM0_HRC3 TSEL: TS1E (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_HRC3_SC ------------------------------- */ -#define HRPWM0_HRC3_SC_ST_Pos \ - (0UL) /*!< HRPWM0_HRC3 SC: ST (Bit 0) */ -#define HRPWM0_HRC3_SC_ST_Msk \ - (0x1UL) /*!< HRPWM0_HRC3 SC: ST (Bitfield-Mask: 0x01) */ - -/* ------------------------------- HRPWM0_HRC3_DCR ------------------------------ */ -#define HRPWM0_HRC3_DCR_DTRV_Pos \ - (0UL) /*!< HRPWM0_HRC3 DCR: DTRV (Bit 0) */ -#define HRPWM0_HRC3_DCR_DTRV_Msk \ - (0xffffUL) /*!< HRPWM0_HRC3 DCR: DTRV (Bitfield-Mask: 0xffff) */ - -/* ------------------------------- HRPWM0_HRC3_DCF ------------------------------ */ -#define HRPWM0_HRC3_DCF_DTFV_Pos \ - (0UL) /*!< HRPWM0_HRC3 DCF: DTFV (Bit 0) */ -#define HRPWM0_HRC3_DCF_DTFV_Msk \ - (0xffffUL) /*!< HRPWM0_HRC3 DCF: DTFV (Bitfield-Mask: 0xffff) */ - -/* ------------------------------- HRPWM0_HRC3_CR1 ------------------------------ */ -#define HRPWM0_HRC3_CR1_CR1_Pos \ - (0UL) /*!< HRPWM0_HRC3 CR1: CR1 (Bit 0) */ -#define HRPWM0_HRC3_CR1_CR1_Msk \ - (0xffUL) /*!< HRPWM0_HRC3 CR1: CR1 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- HRPWM0_HRC3_CR2 ------------------------------ */ -#define HRPWM0_HRC3_CR2_CR2_Pos \ - (0UL) /*!< HRPWM0_HRC3 CR2: CR2 (Bit 0) */ -#define HRPWM0_HRC3_CR2_CR2_Msk \ - (0xffUL) /*!< HRPWM0_HRC3 CR2: CR2 (Bitfield-Mask: 0xff) */ - -/* ------------------------------- HRPWM0_HRC3_SSC ------------------------------ */ -#define HRPWM0_HRC3_SSC_SST_Pos \ - (0UL) /*!< HRPWM0_HRC3 SSC: SST (Bit 0) */ -#define HRPWM0_HRC3_SSC_SST_Msk \ - (0x1UL) /*!< HRPWM0_HRC3 SSC: SST (Bitfield-Mask: 0x01) */ - -/* ------------------------------ HRPWM0_HRC3_SDCR ------------------------------ */ -#define HRPWM0_HRC3_SDCR_SDTRV_Pos \ - (0UL) /*!< HRPWM0_HRC3 SDCR: SDTRV (Bit 0) */ -#define HRPWM0_HRC3_SDCR_SDTRV_Msk \ - (0xffffUL) /*!< HRPWM0_HRC3 SDCR: SDTRV (Bitfield-Mask: 0xffff) */ - -/* ------------------------------ HRPWM0_HRC3_SDCF ------------------------------ */ -#define HRPWM0_HRC3_SDCF_SDTFV_Pos \ - (0UL) /*!< HRPWM0_HRC3 SDCF: SDTFV (Bit 0) */ -#define HRPWM0_HRC3_SDCF_SDTFV_Msk \ - (0xffffUL) /*!< HRPWM0_HRC3 SDCF: SDTFV (Bitfield-Mask: 0xffff) */ - -/* ------------------------------ HRPWM0_HRC3_SCR1 ------------------------------ */ -#define HRPWM0_HRC3_SCR1_SCR1_Pos \ - (0UL) /*!< HRPWM0_HRC3 SCR1: SCR1 (Bit 0) */ -#define HRPWM0_HRC3_SCR1_SCR1_Msk \ - (0xffUL) /*!< HRPWM0_HRC3 SCR1: SCR1 (Bitfield-Mask: 0xff) */ - -/* ------------------------------ HRPWM0_HRC3_SCR2 ------------------------------ */ -#define HRPWM0_HRC3_SCR2_SCR2_Pos \ - (0UL) /*!< HRPWM0_HRC3 SCR2: SCR2 (Bit 0) */ -#define HRPWM0_HRC3_SCR2_SCR2_Msk \ - (0xffUL) /*!< HRPWM0_HRC3 SCR2: SCR2 (Bitfield-Mask: 0xff) */ - -/* ================================================================================ */ -/* ================ Group 'POSIF' Position & Mask ================ */ -/* ================================================================================ */ - -/* --------------------------------- POSIF_PCONF -------------------------------- */ -#define POSIF_PCONF_FSEL_Pos \ - (0UL) /*!< POSIF PCONF: FSEL (Bit 0) */ -#define POSIF_PCONF_FSEL_Msk \ - (0x3UL) /*!< POSIF PCONF: FSEL (Bitfield-Mask: 0x03) */ -#define POSIF_PCONF_QDCM_Pos \ - (2UL) /*!< POSIF PCONF: QDCM (Bit 2) */ -#define POSIF_PCONF_QDCM_Msk \ - (0x4UL) /*!< POSIF PCONF: QDCM (Bitfield-Mask: 0x01) */ -#define POSIF_PCONF_HIDG_Pos \ - (4UL) /*!< POSIF PCONF: HIDG (Bit 4) */ -#define POSIF_PCONF_HIDG_Msk \ - (0x10UL) /*!< POSIF PCONF: HIDG (Bitfield-Mask: 0x01) */ -#define POSIF_PCONF_MCUE_Pos \ - (5UL) /*!< POSIF PCONF: MCUE (Bit 5) */ -#define POSIF_PCONF_MCUE_Msk \ - (0x20UL) /*!< POSIF PCONF: MCUE (Bitfield-Mask: 0x01) */ -#define POSIF_PCONF_INSEL0_Pos \ - (8UL) /*!< POSIF PCONF: INSEL0 (Bit 8) */ -#define POSIF_PCONF_INSEL0_Msk \ - (0x300UL) /*!< POSIF PCONF: INSEL0 (Bitfield-Mask: 0x03) */ -#define POSIF_PCONF_INSEL1_Pos \ - (10UL) /*!< POSIF PCONF: INSEL1 (Bit 10) */ -#define POSIF_PCONF_INSEL1_Msk \ - (0xc00UL) /*!< POSIF PCONF: INSEL1 (Bitfield-Mask: 0x03) */ -#define POSIF_PCONF_INSEL2_Pos \ - (12UL) /*!< POSIF PCONF: INSEL2 (Bit 12) */ -#define POSIF_PCONF_INSEL2_Msk \ - (0x3000UL) /*!< POSIF PCONF: INSEL2 (Bitfield-Mask: 0x03) */ -#define POSIF_PCONF_DSEL_Pos \ - (16UL) /*!< POSIF PCONF: DSEL (Bit 16) */ -#define POSIF_PCONF_DSEL_Msk \ - (0x10000UL) /*!< POSIF PCONF: DSEL (Bitfield-Mask: 0x01) */ -#define POSIF_PCONF_SPES_Pos \ - (17UL) /*!< POSIF PCONF: SPES (Bit 17) */ -#define POSIF_PCONF_SPES_Msk \ - (0x20000UL) /*!< POSIF PCONF: SPES (Bitfield-Mask: 0x01) */ -#define POSIF_PCONF_MSETS_Pos \ - (18UL) /*!< POSIF PCONF: MSETS (Bit 18) */ -#define POSIF_PCONF_MSETS_Msk \ - (0x1c0000UL) /*!< POSIF PCONF: MSETS (Bitfield-Mask: 0x07) */ -#define POSIF_PCONF_MSES_Pos \ - (21UL) /*!< POSIF PCONF: MSES (Bit 21) */ -#define POSIF_PCONF_MSES_Msk \ - (0x200000UL) /*!< POSIF PCONF: MSES (Bitfield-Mask: 0x01) */ -#define POSIF_PCONF_MSYNS_Pos \ - (22UL) /*!< POSIF PCONF: MSYNS (Bit 22) */ -#define POSIF_PCONF_MSYNS_Msk \ - (0xc00000UL) /*!< POSIF PCONF: MSYNS (Bitfield-Mask: 0x03) */ -#define POSIF_PCONF_EWIS_Pos \ - (24UL) /*!< POSIF PCONF: EWIS (Bit 24) */ -#define POSIF_PCONF_EWIS_Msk \ - (0x3000000UL) /*!< POSIF PCONF: EWIS (Bitfield-Mask: 0x03) */ -#define POSIF_PCONF_EWIE_Pos \ - (26UL) /*!< POSIF PCONF: EWIE (Bit 26) */ -#define POSIF_PCONF_EWIE_Msk \ - (0x4000000UL) /*!< POSIF PCONF: EWIE (Bitfield-Mask: 0x01) */ -#define POSIF_PCONF_EWIL_Pos \ - (27UL) /*!< POSIF PCONF: EWIL (Bit 27) */ -#define POSIF_PCONF_EWIL_Msk \ - (0x8000000UL) /*!< POSIF PCONF: EWIL (Bitfield-Mask: 0x01) */ -#define POSIF_PCONF_LPC_Pos \ - (28UL) /*!< POSIF PCONF: LPC (Bit 28) */ -#define POSIF_PCONF_LPC_Msk \ - (0x70000000UL) /*!< POSIF PCONF: LPC (Bitfield-Mask: 0x07) */ - -/* --------------------------------- POSIF_PSUS --------------------------------- */ -#define POSIF_PSUS_QSUS_Pos \ - (0UL) /*!< POSIF PSUS: QSUS (Bit 0) */ -#define POSIF_PSUS_QSUS_Msk \ - (0x3UL) /*!< POSIF PSUS: QSUS (Bitfield-Mask: 0x03) */ -#define POSIF_PSUS_MSUS_Pos \ - (2UL) /*!< POSIF PSUS: MSUS (Bit 2) */ -#define POSIF_PSUS_MSUS_Msk \ - (0xcUL) /*!< POSIF PSUS: MSUS (Bitfield-Mask: 0x03) */ - -/* --------------------------------- POSIF_PRUNS -------------------------------- */ -#define POSIF_PRUNS_SRB_Pos \ - (0UL) /*!< POSIF PRUNS: SRB (Bit 0) */ -#define POSIF_PRUNS_SRB_Msk \ - (0x1UL) /*!< POSIF PRUNS: SRB (Bitfield-Mask: 0x01) */ - -/* --------------------------------- POSIF_PRUNC -------------------------------- */ -#define POSIF_PRUNC_CRB_Pos \ - (0UL) /*!< POSIF PRUNC: CRB (Bit 0) */ -#define POSIF_PRUNC_CRB_Msk \ - (0x1UL) /*!< POSIF PRUNC: CRB (Bitfield-Mask: 0x01) */ -#define POSIF_PRUNC_CSM_Pos \ - (1UL) /*!< POSIF PRUNC: CSM (Bit 1) */ -#define POSIF_PRUNC_CSM_Msk \ - (0x2UL) /*!< POSIF PRUNC: CSM (Bitfield-Mask: 0x01) */ - -/* --------------------------------- POSIF_PRUN --------------------------------- */ -#define POSIF_PRUN_RB_Pos (0UL) /*!< POSIF PRUN: RB (Bit 0) */ -#define POSIF_PRUN_RB_Msk \ - (0x1UL) /*!< POSIF PRUN: RB (Bitfield-Mask: 0x01) */ - -/* --------------------------------- POSIF_MIDR --------------------------------- */ -#define POSIF_MIDR_MODR_Pos \ - (0UL) /*!< POSIF MIDR: MODR (Bit 0) */ -#define POSIF_MIDR_MODR_Msk \ - (0xffUL) /*!< POSIF MIDR: MODR (Bitfield-Mask: 0xff) */ -#define POSIF_MIDR_MODT_Pos \ - (8UL) /*!< POSIF MIDR: MODT (Bit 8) */ -#define POSIF_MIDR_MODT_Msk \ - (0xff00UL) /*!< POSIF MIDR: MODT (Bitfield-Mask: 0xff) */ -#define POSIF_MIDR_MODN_Pos \ - (16UL) /*!< POSIF MIDR: MODN (Bit 16) */ -#define POSIF_MIDR_MODN_Msk \ - (0xffff0000UL) /*!< POSIF MIDR: MODN (Bitfield-Mask: 0xffff) */ - -/* --------------------------------- POSIF_HALP --------------------------------- */ -#define POSIF_HALP_HCP_Pos (0UL) /*!< POSIF HALP: HCP (Bit 0) */ -#define POSIF_HALP_HCP_Msk \ - (0x7UL) /*!< POSIF HALP: HCP (Bitfield-Mask: 0x07) */ -#define POSIF_HALP_HEP_Pos (3UL) /*!< POSIF HALP: HEP (Bit 3) */ -#define POSIF_HALP_HEP_Msk \ - (0x38UL) /*!< POSIF HALP: HEP (Bitfield-Mask: 0x07) */ - -/* --------------------------------- POSIF_HALPS -------------------------------- */ -#define POSIF_HALPS_HCPS_Pos \ - (0UL) /*!< POSIF HALPS: HCPS (Bit 0) */ -#define POSIF_HALPS_HCPS_Msk \ - (0x7UL) /*!< POSIF HALPS: HCPS (Bitfield-Mask: 0x07) */ -#define POSIF_HALPS_HEPS_Pos \ - (3UL) /*!< POSIF HALPS: HEPS (Bit 3) */ -#define POSIF_HALPS_HEPS_Msk \ - (0x38UL) /*!< POSIF HALPS: HEPS (Bitfield-Mask: 0x07) */ - -/* ---------------------------------- POSIF_MCM --------------------------------- */ -#define POSIF_MCM_MCMP_Pos (0UL) /*!< POSIF MCM: MCMP (Bit 0) */ -#define POSIF_MCM_MCMP_Msk \ - (0xffffUL) /*!< POSIF MCM: MCMP (Bitfield-Mask: 0xffff) */ - -/* --------------------------------- POSIF_MCSM --------------------------------- */ -#define POSIF_MCSM_MCMPS_Pos \ - (0UL) /*!< POSIF MCSM: MCMPS (Bit 0) */ -#define POSIF_MCSM_MCMPS_Msk \ - (0xffffUL) /*!< POSIF MCSM: MCMPS (Bitfield-Mask: 0xffff) */ - -/* --------------------------------- POSIF_MCMS --------------------------------- */ -#define POSIF_MCMS_MNPS_Pos \ - (0UL) /*!< POSIF MCMS: MNPS (Bit 0) */ -#define POSIF_MCMS_MNPS_Msk \ - (0x1UL) /*!< POSIF MCMS: MNPS (Bitfield-Mask: 0x01) */ -#define POSIF_MCMS_STHR_Pos \ - (1UL) /*!< POSIF MCMS: STHR (Bit 1) */ -#define POSIF_MCMS_STHR_Msk \ - (0x2UL) /*!< POSIF MCMS: STHR (Bitfield-Mask: 0x01) */ -#define POSIF_MCMS_STMR_Pos \ - (2UL) /*!< POSIF MCMS: STMR (Bit 2) */ -#define POSIF_MCMS_STMR_Msk \ - (0x4UL) /*!< POSIF MCMS: STMR (Bitfield-Mask: 0x01) */ - -/* --------------------------------- POSIF_MCMC --------------------------------- */ -#define POSIF_MCMC_MNPC_Pos \ - (0UL) /*!< POSIF MCMC: MNPC (Bit 0) */ -#define POSIF_MCMC_MNPC_Msk \ - (0x1UL) /*!< POSIF MCMC: MNPC (Bitfield-Mask: 0x01) */ -#define POSIF_MCMC_MPC_Pos (1UL) /*!< POSIF MCMC: MPC (Bit 1) */ -#define POSIF_MCMC_MPC_Msk \ - (0x2UL) /*!< POSIF MCMC: MPC (Bitfield-Mask: 0x01) */ - -/* --------------------------------- POSIF_MCMF --------------------------------- */ -#define POSIF_MCMF_MSS_Pos (0UL) /*!< POSIF MCMF: MSS (Bit 0) */ -#define POSIF_MCMF_MSS_Msk \ - (0x1UL) /*!< POSIF MCMF: MSS (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- POSIF_QDC --------------------------------- */ -#define POSIF_QDC_PALS_Pos (0UL) /*!< POSIF QDC: PALS (Bit 0) */ -#define POSIF_QDC_PALS_Msk \ - (0x1UL) /*!< POSIF QDC: PALS (Bitfield-Mask: 0x01) */ -#define POSIF_QDC_PBLS_Pos (1UL) /*!< POSIF QDC: PBLS (Bit 1) */ -#define POSIF_QDC_PBLS_Msk \ - (0x2UL) /*!< POSIF QDC: PBLS (Bitfield-Mask: 0x01) */ -#define POSIF_QDC_PHS_Pos (2UL) /*!< POSIF QDC: PHS (Bit 2) */ -#define POSIF_QDC_PHS_Msk \ - (0x4UL) /*!< POSIF QDC: PHS (Bitfield-Mask: 0x01) */ -#define POSIF_QDC_ICM_Pos (4UL) /*!< POSIF QDC: ICM (Bit 4) */ -#define POSIF_QDC_ICM_Msk \ - (0x30UL) /*!< POSIF QDC: ICM (Bitfield-Mask: 0x03) */ -#define POSIF_QDC_DVAL_Pos (8UL) /*!< POSIF QDC: DVAL (Bit 8) */ -#define POSIF_QDC_DVAL_Msk \ - (0x100UL) /*!< POSIF QDC: DVAL (Bitfield-Mask: 0x01) */ - -/* --------------------------------- POSIF_PFLG --------------------------------- */ -#define POSIF_PFLG_CHES_Pos \ - (0UL) /*!< POSIF PFLG: CHES (Bit 0) */ -#define POSIF_PFLG_CHES_Msk \ - (0x1UL) /*!< POSIF PFLG: CHES (Bitfield-Mask: 0x01) */ -#define POSIF_PFLG_WHES_Pos \ - (1UL) /*!< POSIF PFLG: WHES (Bit 1) */ -#define POSIF_PFLG_WHES_Msk \ - (0x2UL) /*!< POSIF PFLG: WHES (Bitfield-Mask: 0x01) */ -#define POSIF_PFLG_HIES_Pos \ - (2UL) /*!< POSIF PFLG: HIES (Bit 2) */ -#define POSIF_PFLG_HIES_Msk \ - (0x4UL) /*!< POSIF PFLG: HIES (Bitfield-Mask: 0x01) */ -#define POSIF_PFLG_MSTS_Pos \ - (4UL) /*!< POSIF PFLG: MSTS (Bit 4) */ -#define POSIF_PFLG_MSTS_Msk \ - (0x10UL) /*!< POSIF PFLG: MSTS (Bitfield-Mask: 0x01) */ -#define POSIF_PFLG_INDXS_Pos \ - (8UL) /*!< POSIF PFLG: INDXS (Bit 8) */ -#define POSIF_PFLG_INDXS_Msk \ - (0x100UL) /*!< POSIF PFLG: INDXS (Bitfield-Mask: 0x01) */ -#define POSIF_PFLG_ERRS_Pos \ - (9UL) /*!< POSIF PFLG: ERRS (Bit 9) */ -#define POSIF_PFLG_ERRS_Msk \ - (0x200UL) /*!< POSIF PFLG: ERRS (Bitfield-Mask: 0x01) */ -#define POSIF_PFLG_CNTS_Pos \ - (10UL) /*!< POSIF PFLG: CNTS (Bit 10) */ -#define POSIF_PFLG_CNTS_Msk \ - (0x400UL) /*!< POSIF PFLG: CNTS (Bitfield-Mask: 0x01) */ -#define POSIF_PFLG_DIRS_Pos \ - (11UL) /*!< POSIF PFLG: DIRS (Bit 11) */ -#define POSIF_PFLG_DIRS_Msk \ - (0x800UL) /*!< POSIF PFLG: DIRS (Bitfield-Mask: 0x01) */ -#define POSIF_PFLG_PCLKS_Pos \ - (12UL) /*!< POSIF PFLG: PCLKS (Bit 12) */ -#define POSIF_PFLG_PCLKS_Msk \ - (0x1000UL) /*!< POSIF PFLG: PCLKS (Bitfield-Mask: 0x01) */ - -/* --------------------------------- POSIF_PFLGE -------------------------------- */ -#define POSIF_PFLGE_ECHE_Pos \ - (0UL) /*!< POSIF PFLGE: ECHE (Bit 0) */ -#define POSIF_PFLGE_ECHE_Msk \ - (0x1UL) /*!< POSIF PFLGE: ECHE (Bitfield-Mask: 0x01) */ -#define POSIF_PFLGE_EWHE_Pos \ - (1UL) /*!< POSIF PFLGE: EWHE (Bit 1) */ -#define POSIF_PFLGE_EWHE_Msk \ - (0x2UL) /*!< POSIF PFLGE: EWHE (Bitfield-Mask: 0x01) */ -#define POSIF_PFLGE_EHIE_Pos \ - (2UL) /*!< POSIF PFLGE: EHIE (Bit 2) */ -#define POSIF_PFLGE_EHIE_Msk \ - (0x4UL) /*!< POSIF PFLGE: EHIE (Bitfield-Mask: 0x01) */ -#define POSIF_PFLGE_EMST_Pos \ - (4UL) /*!< POSIF PFLGE: EMST (Bit 4) */ -#define POSIF_PFLGE_EMST_Msk \ - (0x10UL) /*!< POSIF PFLGE: EMST (Bitfield-Mask: 0x01) */ -#define POSIF_PFLGE_EINDX_Pos \ - (8UL) /*!< POSIF PFLGE: EINDX (Bit 8) */ -#define POSIF_PFLGE_EINDX_Msk \ - (0x100UL) /*!< POSIF PFLGE: EINDX (Bitfield-Mask: 0x01) */ -#define POSIF_PFLGE_EERR_Pos \ - (9UL) /*!< POSIF PFLGE: EERR (Bit 9) */ -#define POSIF_PFLGE_EERR_Msk \ - (0x200UL) /*!< POSIF PFLGE: EERR (Bitfield-Mask: 0x01) */ -#define POSIF_PFLGE_ECNT_Pos \ - (10UL) /*!< POSIF PFLGE: ECNT (Bit 10) */ -#define POSIF_PFLGE_ECNT_Msk \ - (0x400UL) /*!< POSIF PFLGE: ECNT (Bitfield-Mask: 0x01) */ -#define POSIF_PFLGE_EDIR_Pos \ - (11UL) /*!< POSIF PFLGE: EDIR (Bit 11) */ -#define POSIF_PFLGE_EDIR_Msk \ - (0x800UL) /*!< POSIF PFLGE: EDIR (Bitfield-Mask: 0x01) */ -#define POSIF_PFLGE_EPCLK_Pos \ - (12UL) /*!< POSIF PFLGE: EPCLK (Bit 12) */ -#define POSIF_PFLGE_EPCLK_Msk \ - (0x1000UL) /*!< POSIF PFLGE: EPCLK (Bitfield-Mask: 0x01) */ -#define POSIF_PFLGE_CHESEL_Pos \ - (16UL) /*!< POSIF PFLGE: CHESEL (Bit 16) */ -#define POSIF_PFLGE_CHESEL_Msk \ - (0x10000UL) /*!< POSIF PFLGE: CHESEL (Bitfield-Mask: 0x01) */ -#define POSIF_PFLGE_WHESEL_Pos \ - (17UL) /*!< POSIF PFLGE: WHESEL (Bit 17) */ -#define POSIF_PFLGE_WHESEL_Msk \ - (0x20000UL) /*!< POSIF PFLGE: WHESEL (Bitfield-Mask: 0x01) */ -#define POSIF_PFLGE_HIESEL_Pos \ - (18UL) /*!< POSIF PFLGE: HIESEL (Bit 18) */ -#define POSIF_PFLGE_HIESEL_Msk \ - (0x40000UL) /*!< POSIF PFLGE: HIESEL (Bitfield-Mask: 0x01) */ -#define POSIF_PFLGE_MSTSEL_Pos \ - (20UL) /*!< POSIF PFLGE: MSTSEL (Bit 20) */ -#define POSIF_PFLGE_MSTSEL_Msk \ - (0x100000UL) /*!< POSIF PFLGE: MSTSEL (Bitfield-Mask: 0x01) */ -#define POSIF_PFLGE_INDSEL_Pos \ - (24UL) /*!< POSIF PFLGE: INDSEL (Bit 24) */ -#define POSIF_PFLGE_INDSEL_Msk \ - (0x1000000UL) /*!< POSIF PFLGE: INDSEL (Bitfield-Mask: 0x01) */ -#define POSIF_PFLGE_ERRSEL_Pos \ - (25UL) /*!< POSIF PFLGE: ERRSEL (Bit 25) */ -#define POSIF_PFLGE_ERRSEL_Msk \ - (0x2000000UL) /*!< POSIF PFLGE: ERRSEL (Bitfield-Mask: 0x01) */ -#define POSIF_PFLGE_CNTSEL_Pos \ - (26UL) /*!< POSIF PFLGE: CNTSEL (Bit 26) */ -#define POSIF_PFLGE_CNTSEL_Msk \ - (0x4000000UL) /*!< POSIF PFLGE: CNTSEL (Bitfield-Mask: 0x01) */ -#define POSIF_PFLGE_DIRSEL_Pos \ - (27UL) /*!< POSIF PFLGE: DIRSEL (Bit 27) */ -#define POSIF_PFLGE_DIRSEL_Msk \ - (0x8000000UL) /*!< POSIF PFLGE: DIRSEL (Bitfield-Mask: 0x01) */ -#define POSIF_PFLGE_PCLSEL_Pos \ - (28UL) /*!< POSIF PFLGE: PCLSEL (Bit 28) */ -#define POSIF_PFLGE_PCLSEL_Msk \ - (0x10000000UL) /*!< POSIF PFLGE: PCLSEL (Bitfield-Mask: 0x01) */ - -/* --------------------------------- POSIF_SPFLG -------------------------------- */ -#define POSIF_SPFLG_SCHE_Pos \ - (0UL) /*!< POSIF SPFLG: SCHE (Bit 0) */ -#define POSIF_SPFLG_SCHE_Msk \ - (0x1UL) /*!< POSIF SPFLG: SCHE (Bitfield-Mask: 0x01) */ -#define POSIF_SPFLG_SWHE_Pos \ - (1UL) /*!< POSIF SPFLG: SWHE (Bit 1) */ -#define POSIF_SPFLG_SWHE_Msk \ - (0x2UL) /*!< POSIF SPFLG: SWHE (Bitfield-Mask: 0x01) */ -#define POSIF_SPFLG_SHIE_Pos \ - (2UL) /*!< POSIF SPFLG: SHIE (Bit 2) */ -#define POSIF_SPFLG_SHIE_Msk \ - (0x4UL) /*!< POSIF SPFLG: SHIE (Bitfield-Mask: 0x01) */ -#define POSIF_SPFLG_SMST_Pos \ - (4UL) /*!< POSIF SPFLG: SMST (Bit 4) */ -#define POSIF_SPFLG_SMST_Msk \ - (0x10UL) /*!< POSIF SPFLG: SMST (Bitfield-Mask: 0x01) */ -#define POSIF_SPFLG_SINDX_Pos \ - (8UL) /*!< POSIF SPFLG: SINDX (Bit 8) */ -#define POSIF_SPFLG_SINDX_Msk \ - (0x100UL) /*!< POSIF SPFLG: SINDX (Bitfield-Mask: 0x01) */ -#define POSIF_SPFLG_SERR_Pos \ - (9UL) /*!< POSIF SPFLG: SERR (Bit 9) */ -#define POSIF_SPFLG_SERR_Msk \ - (0x200UL) /*!< POSIF SPFLG: SERR (Bitfield-Mask: 0x01) */ -#define POSIF_SPFLG_SCNT_Pos \ - (10UL) /*!< POSIF SPFLG: SCNT (Bit 10) */ -#define POSIF_SPFLG_SCNT_Msk \ - (0x400UL) /*!< POSIF SPFLG: SCNT (Bitfield-Mask: 0x01) */ -#define POSIF_SPFLG_SDIR_Pos \ - (11UL) /*!< POSIF SPFLG: SDIR (Bit 11) */ -#define POSIF_SPFLG_SDIR_Msk \ - (0x800UL) /*!< POSIF SPFLG: SDIR (Bitfield-Mask: 0x01) */ -#define POSIF_SPFLG_SPCLK_Pos \ - (12UL) /*!< POSIF SPFLG: SPCLK (Bit 12) */ -#define POSIF_SPFLG_SPCLK_Msk \ - (0x1000UL) /*!< POSIF SPFLG: SPCLK (Bitfield-Mask: 0x01) */ - -/* --------------------------------- POSIF_RPFLG -------------------------------- */ -#define POSIF_RPFLG_RCHE_Pos \ - (0UL) /*!< POSIF RPFLG: RCHE (Bit 0) */ -#define POSIF_RPFLG_RCHE_Msk \ - (0x1UL) /*!< POSIF RPFLG: RCHE (Bitfield-Mask: 0x01) */ -#define POSIF_RPFLG_RWHE_Pos \ - (1UL) /*!< POSIF RPFLG: RWHE (Bit 1) */ -#define POSIF_RPFLG_RWHE_Msk \ - (0x2UL) /*!< POSIF RPFLG: RWHE (Bitfield-Mask: 0x01) */ -#define POSIF_RPFLG_RHIE_Pos \ - (2UL) /*!< POSIF RPFLG: RHIE (Bit 2) */ -#define POSIF_RPFLG_RHIE_Msk \ - (0x4UL) /*!< POSIF RPFLG: RHIE (Bitfield-Mask: 0x01) */ -#define POSIF_RPFLG_RMST_Pos \ - (4UL) /*!< POSIF RPFLG: RMST (Bit 4) */ -#define POSIF_RPFLG_RMST_Msk \ - (0x10UL) /*!< POSIF RPFLG: RMST (Bitfield-Mask: 0x01) */ -#define POSIF_RPFLG_RINDX_Pos \ - (8UL) /*!< POSIF RPFLG: RINDX (Bit 8) */ -#define POSIF_RPFLG_RINDX_Msk \ - (0x100UL) /*!< POSIF RPFLG: RINDX (Bitfield-Mask: 0x01) */ -#define POSIF_RPFLG_RERR_Pos \ - (9UL) /*!< POSIF RPFLG: RERR (Bit 9) */ -#define POSIF_RPFLG_RERR_Msk \ - (0x200UL) /*!< POSIF RPFLG: RERR (Bitfield-Mask: 0x01) */ -#define POSIF_RPFLG_RCNT_Pos \ - (10UL) /*!< POSIF RPFLG: RCNT (Bit 10) */ -#define POSIF_RPFLG_RCNT_Msk \ - (0x400UL) /*!< POSIF RPFLG: RCNT (Bitfield-Mask: 0x01) */ -#define POSIF_RPFLG_RDIR_Pos \ - (11UL) /*!< POSIF RPFLG: RDIR (Bit 11) */ -#define POSIF_RPFLG_RDIR_Msk \ - (0x800UL) /*!< POSIF RPFLG: RDIR (Bitfield-Mask: 0x01) */ -#define POSIF_RPFLG_RPCLK_Pos \ - (12UL) /*!< POSIF RPFLG: RPCLK (Bit 12) */ -#define POSIF_RPFLG_RPCLK_Msk \ - (0x1000UL) /*!< POSIF RPFLG: RPCLK (Bitfield-Mask: 0x01) */ - -/* --------------------------------- POSIF_PDBG --------------------------------- */ -#define POSIF_PDBG_QCSV_Pos \ - (0UL) /*!< POSIF PDBG: QCSV (Bit 0) */ -#define POSIF_PDBG_QCSV_Msk \ - (0x3UL) /*!< POSIF PDBG: QCSV (Bitfield-Mask: 0x03) */ -#define POSIF_PDBG_QPSV_Pos \ - (2UL) /*!< POSIF PDBG: QPSV (Bit 2) */ -#define POSIF_PDBG_QPSV_Msk \ - (0xcUL) /*!< POSIF PDBG: QPSV (Bitfield-Mask: 0x03) */ -#define POSIF_PDBG_IVAL_Pos \ - (4UL) /*!< POSIF PDBG: IVAL (Bit 4) */ -#define POSIF_PDBG_IVAL_Msk \ - (0x10UL) /*!< POSIF PDBG: IVAL (Bitfield-Mask: 0x01) */ -#define POSIF_PDBG_HSP_Pos (5UL) /*!< POSIF PDBG: HSP (Bit 5) */ -#define POSIF_PDBG_HSP_Msk \ - (0xe0UL) /*!< POSIF PDBG: HSP (Bitfield-Mask: 0x07) */ -#define POSIF_PDBG_LPP0_Pos \ - (8UL) /*!< POSIF PDBG: LPP0 (Bit 8) */ -#define POSIF_PDBG_LPP0_Msk \ - (0x3f00UL) /*!< POSIF PDBG: LPP0 (Bitfield-Mask: 0x3f) */ -#define POSIF_PDBG_LPP1_Pos \ - (16UL) /*!< POSIF PDBG: LPP1 (Bit 16) */ -#define POSIF_PDBG_LPP1_Msk \ - (0x3f0000UL) /*!< POSIF PDBG: LPP1 (Bitfield-Mask: 0x3f) */ -#define POSIF_PDBG_LPP2_Pos \ - (22UL) /*!< POSIF PDBG: LPP2 (Bit 22) */ -#define POSIF_PDBG_LPP2_Msk \ - (0xfc00000UL) /*!< POSIF PDBG: LPP2 (Bitfield-Mask: 0x3f) */ - -/* ================================================================================ */ -/* ================ struct 'PORT0' Position & Mask ================ */ -/* ================================================================================ */ - -/* ---------------------------------- PORT0_OUT --------------------------------- */ -#define PORT0_OUT_P0_Pos (0UL) /*!< PORT0 OUT: P0 (Bit 0) */ -#define PORT0_OUT_P0_Msk (0x1UL) /*!< PORT0 OUT: P0 (Bitfield-Mask: 0x01) */ -#define PORT0_OUT_P1_Pos (1UL) /*!< PORT0 OUT: P1 (Bit 1) */ -#define PORT0_OUT_P1_Msk (0x2UL) /*!< PORT0 OUT: P1 (Bitfield-Mask: 0x01) */ -#define PORT0_OUT_P2_Pos (2UL) /*!< PORT0 OUT: P2 (Bit 2) */ -#define PORT0_OUT_P2_Msk (0x4UL) /*!< PORT0 OUT: P2 (Bitfield-Mask: 0x01) */ -#define PORT0_OUT_P3_Pos (3UL) /*!< PORT0 OUT: P3 (Bit 3) */ -#define PORT0_OUT_P3_Msk (0x8UL) /*!< PORT0 OUT: P3 (Bitfield-Mask: 0x01) */ -#define PORT0_OUT_P4_Pos (4UL) /*!< PORT0 OUT: P4 (Bit 4) */ -#define PORT0_OUT_P4_Msk \ - (0x10UL) /*!< PORT0 OUT: P4 (Bitfield-Mask: 0x01) */ -#define PORT0_OUT_P5_Pos (5UL) /*!< PORT0 OUT: P5 (Bit 5) */ -#define PORT0_OUT_P5_Msk \ - (0x20UL) /*!< PORT0 OUT: P5 (Bitfield-Mask: 0x01) */ -#define PORT0_OUT_P6_Pos (6UL) /*!< PORT0 OUT: P6 (Bit 6) */ -#define PORT0_OUT_P6_Msk \ - (0x40UL) /*!< PORT0 OUT: P6 (Bitfield-Mask: 0x01) */ -#define PORT0_OUT_P7_Pos (7UL) /*!< PORT0 OUT: P7 (Bit 7) */ -#define PORT0_OUT_P7_Msk \ - (0x80UL) /*!< PORT0 OUT: P7 (Bitfield-Mask: 0x01) */ -#define PORT0_OUT_P8_Pos (8UL) /*!< PORT0 OUT: P8 (Bit 8) */ -#define PORT0_OUT_P8_Msk \ - (0x100UL) /*!< PORT0 OUT: P8 (Bitfield-Mask: 0x01) */ -#define PORT0_OUT_P9_Pos (9UL) /*!< PORT0 OUT: P9 (Bit 9) */ -#define PORT0_OUT_P9_Msk \ - (0x200UL) /*!< PORT0 OUT: P9 (Bitfield-Mask: 0x01) */ -#define PORT0_OUT_P10_Pos (10UL) /*!< PORT0 OUT: P10 (Bit 10) */ -#define PORT0_OUT_P10_Msk \ - (0x400UL) /*!< PORT0 OUT: P10 (Bitfield-Mask: 0x01) */ -#define PORT0_OUT_P11_Pos (11UL) /*!< PORT0 OUT: P11 (Bit 11) */ -#define PORT0_OUT_P11_Msk \ - (0x800UL) /*!< PORT0 OUT: P11 (Bitfield-Mask: 0x01) */ -#define PORT0_OUT_P12_Pos (12UL) /*!< PORT0 OUT: P12 (Bit 12) */ -#define PORT0_OUT_P12_Msk \ - (0x1000UL) /*!< PORT0 OUT: P12 (Bitfield-Mask: 0x01) */ -#define PORT0_OUT_P13_Pos (13UL) /*!< PORT0 OUT: P13 (Bit 13) */ -#define PORT0_OUT_P13_Msk \ - (0x2000UL) /*!< PORT0 OUT: P13 (Bitfield-Mask: 0x01) */ -#define PORT0_OUT_P14_Pos (14UL) /*!< PORT0 OUT: P14 (Bit 14) */ -#define PORT0_OUT_P14_Msk \ - (0x4000UL) /*!< PORT0 OUT: P14 (Bitfield-Mask: 0x01) */ -#define PORT0_OUT_P15_Pos (15UL) /*!< PORT0 OUT: P15 (Bit 15) */ -#define PORT0_OUT_P15_Msk \ - (0x8000UL) /*!< PORT0 OUT: P15 (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- PORT0_OMR --------------------------------- */ -#define PORT0_OMR_PS0_Pos (0UL) /*!< PORT0 OMR: PS0 (Bit 0) */ -#define PORT0_OMR_PS0_Msk \ - (0x1UL) /*!< PORT0 OMR: PS0 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PS1_Pos (1UL) /*!< PORT0 OMR: PS1 (Bit 1) */ -#define PORT0_OMR_PS1_Msk \ - (0x2UL) /*!< PORT0 OMR: PS1 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PS2_Pos (2UL) /*!< PORT0 OMR: PS2 (Bit 2) */ -#define PORT0_OMR_PS2_Msk \ - (0x4UL) /*!< PORT0 OMR: PS2 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PS3_Pos (3UL) /*!< PORT0 OMR: PS3 (Bit 3) */ -#define PORT0_OMR_PS3_Msk \ - (0x8UL) /*!< PORT0 OMR: PS3 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PS4_Pos (4UL) /*!< PORT0 OMR: PS4 (Bit 4) */ -#define PORT0_OMR_PS4_Msk \ - (0x10UL) /*!< PORT0 OMR: PS4 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PS5_Pos (5UL) /*!< PORT0 OMR: PS5 (Bit 5) */ -#define PORT0_OMR_PS5_Msk \ - (0x20UL) /*!< PORT0 OMR: PS5 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PS6_Pos (6UL) /*!< PORT0 OMR: PS6 (Bit 6) */ -#define PORT0_OMR_PS6_Msk \ - (0x40UL) /*!< PORT0 OMR: PS6 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PS7_Pos (7UL) /*!< PORT0 OMR: PS7 (Bit 7) */ -#define PORT0_OMR_PS7_Msk \ - (0x80UL) /*!< PORT0 OMR: PS7 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PS8_Pos (8UL) /*!< PORT0 OMR: PS8 (Bit 8) */ -#define PORT0_OMR_PS8_Msk \ - (0x100UL) /*!< PORT0 OMR: PS8 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PS9_Pos (9UL) /*!< PORT0 OMR: PS9 (Bit 9) */ -#define PORT0_OMR_PS9_Msk \ - (0x200UL) /*!< PORT0 OMR: PS9 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PS10_Pos \ - (10UL) /*!< PORT0 OMR: PS10 (Bit 10) */ -#define PORT0_OMR_PS10_Msk \ - (0x400UL) /*!< PORT0 OMR: PS10 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PS11_Pos \ - (11UL) /*!< PORT0 OMR: PS11 (Bit 11) */ -#define PORT0_OMR_PS11_Msk \ - (0x800UL) /*!< PORT0 OMR: PS11 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PS12_Pos \ - (12UL) /*!< PORT0 OMR: PS12 (Bit 12) */ -#define PORT0_OMR_PS12_Msk \ - (0x1000UL) /*!< PORT0 OMR: PS12 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PS13_Pos \ - (13UL) /*!< PORT0 OMR: PS13 (Bit 13) */ -#define PORT0_OMR_PS13_Msk \ - (0x2000UL) /*!< PORT0 OMR: PS13 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PS14_Pos \ - (14UL) /*!< PORT0 OMR: PS14 (Bit 14) */ -#define PORT0_OMR_PS14_Msk \ - (0x4000UL) /*!< PORT0 OMR: PS14 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PS15_Pos \ - (15UL) /*!< PORT0 OMR: PS15 (Bit 15) */ -#define PORT0_OMR_PS15_Msk \ - (0x8000UL) /*!< PORT0 OMR: PS15 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PR0_Pos (16UL) /*!< PORT0 OMR: PR0 (Bit 16) */ -#define PORT0_OMR_PR0_Msk \ - (0x10000UL) /*!< PORT0 OMR: PR0 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PR1_Pos (17UL) /*!< PORT0 OMR: PR1 (Bit 17) */ -#define PORT0_OMR_PR1_Msk \ - (0x20000UL) /*!< PORT0 OMR: PR1 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PR2_Pos (18UL) /*!< PORT0 OMR: PR2 (Bit 18) */ -#define PORT0_OMR_PR2_Msk \ - (0x40000UL) /*!< PORT0 OMR: PR2 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PR3_Pos (19UL) /*!< PORT0 OMR: PR3 (Bit 19) */ -#define PORT0_OMR_PR3_Msk \ - (0x80000UL) /*!< PORT0 OMR: PR3 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PR4_Pos (20UL) /*!< PORT0 OMR: PR4 (Bit 20) */ -#define PORT0_OMR_PR4_Msk \ - (0x100000UL) /*!< PORT0 OMR: PR4 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PR5_Pos (21UL) /*!< PORT0 OMR: PR5 (Bit 21) */ -#define PORT0_OMR_PR5_Msk \ - (0x200000UL) /*!< PORT0 OMR: PR5 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PR6_Pos (22UL) /*!< PORT0 OMR: PR6 (Bit 22) */ -#define PORT0_OMR_PR6_Msk \ - (0x400000UL) /*!< PORT0 OMR: PR6 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PR7_Pos (23UL) /*!< PORT0 OMR: PR7 (Bit 23) */ -#define PORT0_OMR_PR7_Msk \ - (0x800000UL) /*!< PORT0 OMR: PR7 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PR8_Pos (24UL) /*!< PORT0 OMR: PR8 (Bit 24) */ -#define PORT0_OMR_PR8_Msk \ - (0x1000000UL) /*!< PORT0 OMR: PR8 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PR9_Pos (25UL) /*!< PORT0 OMR: PR9 (Bit 25) */ -#define PORT0_OMR_PR9_Msk \ - (0x2000000UL) /*!< PORT0 OMR: PR9 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PR10_Pos \ - (26UL) /*!< PORT0 OMR: PR10 (Bit 26) */ -#define PORT0_OMR_PR10_Msk \ - (0x4000000UL) /*!< PORT0 OMR: PR10 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PR11_Pos \ - (27UL) /*!< PORT0 OMR: PR11 (Bit 27) */ -#define PORT0_OMR_PR11_Msk \ - (0x8000000UL) /*!< PORT0 OMR: PR11 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PR12_Pos \ - (28UL) /*!< PORT0 OMR: PR12 (Bit 28) */ -#define PORT0_OMR_PR12_Msk \ - (0x10000000UL) /*!< PORT0 OMR: PR12 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PR13_Pos \ - (29UL) /*!< PORT0 OMR: PR13 (Bit 29) */ -#define PORT0_OMR_PR13_Msk \ - (0x20000000UL) /*!< PORT0 OMR: PR13 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PR14_Pos \ - (30UL) /*!< PORT0 OMR: PR14 (Bit 30) */ -#define PORT0_OMR_PR14_Msk \ - (0x40000000UL) /*!< PORT0 OMR: PR14 (Bitfield-Mask: 0x01) */ -#define PORT0_OMR_PR15_Pos \ - (31UL) /*!< PORT0 OMR: PR15 (Bit 31) */ -#define PORT0_OMR_PR15_Msk \ - (0x80000000UL) /*!< PORT0 OMR: PR15 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- PORT0_IOCR0 -------------------------------- */ -#define PORT0_IOCR0_PC0_Pos \ - (3UL) /*!< PORT0 IOCR0: PC0 (Bit 3) */ -#define PORT0_IOCR0_PC0_Msk \ - (0xf8UL) /*!< PORT0 IOCR0: PC0 (Bitfield-Mask: 0x1f) */ -#define PORT0_IOCR0_PC1_Pos \ - (11UL) /*!< PORT0 IOCR0: PC1 (Bit 11) */ -#define PORT0_IOCR0_PC1_Msk \ - (0xf800UL) /*!< PORT0 IOCR0: PC1 (Bitfield-Mask: 0x1f) */ -#define PORT0_IOCR0_PC2_Pos \ - (19UL) /*!< PORT0 IOCR0: PC2 (Bit 19) */ -#define PORT0_IOCR0_PC2_Msk \ - (0xf80000UL) /*!< PORT0 IOCR0: PC2 (Bitfield-Mask: 0x1f) */ -#define PORT0_IOCR0_PC3_Pos \ - (27UL) /*!< PORT0 IOCR0: PC3 (Bit 27) */ -#define PORT0_IOCR0_PC3_Msk \ - (0xf8000000UL) /*!< PORT0 IOCR0: PC3 (Bitfield-Mask: 0x1f) */ - -/* --------------------------------- PORT0_IOCR4 -------------------------------- */ -#define PORT0_IOCR4_PC4_Pos \ - (3UL) /*!< PORT0 IOCR4: PC4 (Bit 3) */ -#define PORT0_IOCR4_PC4_Msk \ - (0xf8UL) /*!< PORT0 IOCR4: PC4 (Bitfield-Mask: 0x1f) */ -#define PORT0_IOCR4_PC5_Pos \ - (11UL) /*!< PORT0 IOCR4: PC5 (Bit 11) */ -#define PORT0_IOCR4_PC5_Msk \ - (0xf800UL) /*!< PORT0 IOCR4: PC5 (Bitfield-Mask: 0x1f) */ -#define PORT0_IOCR4_PC6_Pos \ - (19UL) /*!< PORT0 IOCR4: PC6 (Bit 19) */ -#define PORT0_IOCR4_PC6_Msk \ - (0xf80000UL) /*!< PORT0 IOCR4: PC6 (Bitfield-Mask: 0x1f) */ -#define PORT0_IOCR4_PC7_Pos \ - (27UL) /*!< PORT0 IOCR4: PC7 (Bit 27) */ -#define PORT0_IOCR4_PC7_Msk \ - (0xf8000000UL) /*!< PORT0 IOCR4: PC7 (Bitfield-Mask: 0x1f) */ - -/* --------------------------------- PORT0_IOCR8 -------------------------------- */ -#define PORT0_IOCR8_PC8_Pos \ - (3UL) /*!< PORT0 IOCR8: PC8 (Bit 3) */ -#define PORT0_IOCR8_PC8_Msk \ - (0xf8UL) /*!< PORT0 IOCR8: PC8 (Bitfield-Mask: 0x1f) */ -#define PORT0_IOCR8_PC9_Pos \ - (11UL) /*!< PORT0 IOCR8: PC9 (Bit 11) */ -#define PORT0_IOCR8_PC9_Msk \ - (0xf800UL) /*!< PORT0 IOCR8: PC9 (Bitfield-Mask: 0x1f) */ -#define PORT0_IOCR8_PC10_Pos \ - (19UL) /*!< PORT0 IOCR8: PC10 (Bit 19) */ -#define PORT0_IOCR8_PC10_Msk \ - (0xf80000UL) /*!< PORT0 IOCR8: PC10 (Bitfield-Mask: 0x1f) */ -#define PORT0_IOCR8_PC11_Pos \ - (27UL) /*!< PORT0 IOCR8: PC11 (Bit 27) */ -#define PORT0_IOCR8_PC11_Msk \ - (0xf8000000UL) /*!< PORT0 IOCR8: PC11 (Bitfield-Mask: 0x1f) */ - -/* -------------------------------- PORT0_IOCR12 -------------------------------- */ -#define PORT0_IOCR12_PC12_Pos \ - (3UL) /*!< PORT0 IOCR12: PC12 (Bit 3) */ -#define PORT0_IOCR12_PC12_Msk \ - (0xf8UL) /*!< PORT0 IOCR12: PC12 (Bitfield-Mask: 0x1f) */ -#define PORT0_IOCR12_PC13_Pos \ - (11UL) /*!< PORT0 IOCR12: PC13 (Bit 11) */ -#define PORT0_IOCR12_PC13_Msk \ - (0xf800UL) /*!< PORT0 IOCR12: PC13 (Bitfield-Mask: 0x1f) */ -#define PORT0_IOCR12_PC14_Pos \ - (19UL) /*!< PORT0 IOCR12: PC14 (Bit 19) */ -#define PORT0_IOCR12_PC14_Msk \ - (0xf80000UL) /*!< PORT0 IOCR12: PC14 (Bitfield-Mask: 0x1f) */ -#define PORT0_IOCR12_PC15_Pos \ - (27UL) /*!< PORT0 IOCR12: PC15 (Bit 27) */ -#define PORT0_IOCR12_PC15_Msk \ - (0xf8000000UL) /*!< PORT0 IOCR12: PC15 (Bitfield-Mask: 0x1f) */ - -/* ---------------------------------- PORT0_IN ---------------------------------- */ -#define PORT0_IN_P0_Pos (0UL) /*!< PORT0 IN: P0 (Bit 0) */ -#define PORT0_IN_P0_Msk (0x1UL) /*!< PORT0 IN: P0 (Bitfield-Mask: 0x01) */ -#define PORT0_IN_P1_Pos (1UL) /*!< PORT0 IN: P1 (Bit 1) */ -#define PORT0_IN_P1_Msk (0x2UL) /*!< PORT0 IN: P1 (Bitfield-Mask: 0x01) */ -#define PORT0_IN_P2_Pos (2UL) /*!< PORT0 IN: P2 (Bit 2) */ -#define PORT0_IN_P2_Msk (0x4UL) /*!< PORT0 IN: P2 (Bitfield-Mask: 0x01) */ -#define PORT0_IN_P3_Pos (3UL) /*!< PORT0 IN: P3 (Bit 3) */ -#define PORT0_IN_P3_Msk (0x8UL) /*!< PORT0 IN: P3 (Bitfield-Mask: 0x01) */ -#define PORT0_IN_P4_Pos (4UL) /*!< PORT0 IN: P4 (Bit 4) */ -#define PORT0_IN_P4_Msk (0x10UL) /*!< PORT0 IN: P4 (Bitfield-Mask: 0x01) */ -#define PORT0_IN_P5_Pos (5UL) /*!< PORT0 IN: P5 (Bit 5) */ -#define PORT0_IN_P5_Msk (0x20UL) /*!< PORT0 IN: P5 (Bitfield-Mask: 0x01) */ -#define PORT0_IN_P6_Pos (6UL) /*!< PORT0 IN: P6 (Bit 6) */ -#define PORT0_IN_P6_Msk (0x40UL) /*!< PORT0 IN: P6 (Bitfield-Mask: 0x01) */ -#define PORT0_IN_P7_Pos (7UL) /*!< PORT0 IN: P7 (Bit 7) */ -#define PORT0_IN_P7_Msk (0x80UL) /*!< PORT0 IN: P7 (Bitfield-Mask: 0x01) */ -#define PORT0_IN_P8_Pos (8UL) /*!< PORT0 IN: P8 (Bit 8) */ -#define PORT0_IN_P8_Msk \ - (0x100UL) /*!< PORT0 IN: P8 (Bitfield-Mask: 0x01) */ -#define PORT0_IN_P9_Pos (9UL) /*!< PORT0 IN: P9 (Bit 9) */ -#define PORT0_IN_P9_Msk \ - (0x200UL) /*!< PORT0 IN: P9 (Bitfield-Mask: 0x01) */ -#define PORT0_IN_P10_Pos (10UL) /*!< PORT0 IN: P10 (Bit 10) */ -#define PORT0_IN_P10_Msk \ - (0x400UL) /*!< PORT0 IN: P10 (Bitfield-Mask: 0x01) */ -#define PORT0_IN_P11_Pos (11UL) /*!< PORT0 IN: P11 (Bit 11) */ -#define PORT0_IN_P11_Msk \ - (0x800UL) /*!< PORT0 IN: P11 (Bitfield-Mask: 0x01) */ -#define PORT0_IN_P12_Pos (12UL) /*!< PORT0 IN: P12 (Bit 12) */ -#define PORT0_IN_P12_Msk \ - (0x1000UL) /*!< PORT0 IN: P12 (Bitfield-Mask: 0x01) */ -#define PORT0_IN_P13_Pos (13UL) /*!< PORT0 IN: P13 (Bit 13) */ -#define PORT0_IN_P13_Msk \ - (0x2000UL) /*!< PORT0 IN: P13 (Bitfield-Mask: 0x01) */ -#define PORT0_IN_P14_Pos (14UL) /*!< PORT0 IN: P14 (Bit 14) */ -#define PORT0_IN_P14_Msk \ - (0x4000UL) /*!< PORT0 IN: P14 (Bitfield-Mask: 0x01) */ -#define PORT0_IN_P15_Pos (15UL) /*!< PORT0 IN: P15 (Bit 15) */ -#define PORT0_IN_P15_Msk \ - (0x8000UL) /*!< PORT0 IN: P15 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- PORT0_PDR0 --------------------------------- */ -#define PORT0_PDR0_PD0_Pos (0UL) /*!< PORT0 PDR0: PD0 (Bit 0) */ -#define PORT0_PDR0_PD0_Msk \ - (0x7UL) /*!< PORT0 PDR0: PD0 (Bitfield-Mask: 0x07) */ -#define PORT0_PDR0_PD1_Pos (4UL) /*!< PORT0 PDR0: PD1 (Bit 4) */ -#define PORT0_PDR0_PD1_Msk \ - (0x70UL) /*!< PORT0 PDR0: PD1 (Bitfield-Mask: 0x07) */ -#define PORT0_PDR0_PD2_Pos (8UL) /*!< PORT0 PDR0: PD2 (Bit 8) */ -#define PORT0_PDR0_PD2_Msk \ - (0x700UL) /*!< PORT0 PDR0: PD2 (Bitfield-Mask: 0x07) */ -#define PORT0_PDR0_PD3_Pos \ - (12UL) /*!< PORT0 PDR0: PD3 (Bit 12) */ -#define PORT0_PDR0_PD3_Msk \ - (0x7000UL) /*!< PORT0 PDR0: PD3 (Bitfield-Mask: 0x07) */ -#define PORT0_PDR0_PD4_Pos \ - (16UL) /*!< PORT0 PDR0: PD4 (Bit 16) */ -#define PORT0_PDR0_PD4_Msk \ - (0x70000UL) /*!< PORT0 PDR0: PD4 (Bitfield-Mask: 0x07) */ -#define PORT0_PDR0_PD5_Pos \ - (20UL) /*!< PORT0 PDR0: PD5 (Bit 20) */ -#define PORT0_PDR0_PD5_Msk \ - (0x700000UL) /*!< PORT0 PDR0: PD5 (Bitfield-Mask: 0x07) */ -#define PORT0_PDR0_PD6_Pos \ - (24UL) /*!< PORT0 PDR0: PD6 (Bit 24) */ -#define PORT0_PDR0_PD6_Msk \ - (0x7000000UL) /*!< PORT0 PDR0: PD6 (Bitfield-Mask: 0x07) */ -#define PORT0_PDR0_PD7_Pos \ - (28UL) /*!< PORT0 PDR0: PD7 (Bit 28) */ -#define PORT0_PDR0_PD7_Msk \ - (0x70000000UL) /*!< PORT0 PDR0: PD7 (Bitfield-Mask: 0x07) */ - -/* --------------------------------- PORT0_PDR1 --------------------------------- */ -#define PORT0_PDR1_PD8_Pos (0UL) /*!< PORT0 PDR1: PD8 (Bit 0) */ -#define PORT0_PDR1_PD8_Msk \ - (0x7UL) /*!< PORT0 PDR1: PD8 (Bitfield-Mask: 0x07) */ -#define PORT0_PDR1_PD9_Pos (4UL) /*!< PORT0 PDR1: PD9 (Bit 4) */ -#define PORT0_PDR1_PD9_Msk \ - (0x70UL) /*!< PORT0 PDR1: PD9 (Bitfield-Mask: 0x07) */ -#define PORT0_PDR1_PD10_Pos \ - (8UL) /*!< PORT0 PDR1: PD10 (Bit 8) */ -#define PORT0_PDR1_PD10_Msk \ - (0x700UL) /*!< PORT0 PDR1: PD10 (Bitfield-Mask: 0x07) */ -#define PORT0_PDR1_PD11_Pos \ - (12UL) /*!< PORT0 PDR1: PD11 (Bit 12) */ -#define PORT0_PDR1_PD11_Msk \ - (0x7000UL) /*!< PORT0 PDR1: PD11 (Bitfield-Mask: 0x07) */ -#define PORT0_PDR1_PD12_Pos \ - (16UL) /*!< PORT0 PDR1: PD12 (Bit 16) */ -#define PORT0_PDR1_PD12_Msk \ - (0x70000UL) /*!< PORT0 PDR1: PD12 (Bitfield-Mask: 0x07) */ -#define PORT0_PDR1_PD13_Pos \ - (20UL) /*!< PORT0 PDR1: PD13 (Bit 20) */ -#define PORT0_PDR1_PD13_Msk \ - (0x700000UL) /*!< PORT0 PDR1: PD13 (Bitfield-Mask: 0x07) */ -#define PORT0_PDR1_PD14_Pos \ - (24UL) /*!< PORT0 PDR1: PD14 (Bit 24) */ -#define PORT0_PDR1_PD14_Msk \ - (0x7000000UL) /*!< PORT0 PDR1: PD14 (Bitfield-Mask: 0x07) */ -#define PORT0_PDR1_PD15_Pos \ - (28UL) /*!< PORT0 PDR1: PD15 (Bit 28) */ -#define PORT0_PDR1_PD15_Msk \ - (0x70000000UL) /*!< PORT0 PDR1: PD15 (Bitfield-Mask: 0x07) */ - -/* --------------------------------- PORT0_PDISC -------------------------------- */ -#define PORT0_PDISC_PDIS0_Pos \ - (0UL) /*!< PORT0 PDISC: PDIS0 (Bit 0) */ -#define PORT0_PDISC_PDIS0_Msk \ - (0x1UL) /*!< PORT0 PDISC: PDIS0 (Bitfield-Mask: 0x01) */ -#define PORT0_PDISC_PDIS1_Pos \ - (1UL) /*!< PORT0 PDISC: PDIS1 (Bit 1) */ -#define PORT0_PDISC_PDIS1_Msk \ - (0x2UL) /*!< PORT0 PDISC: PDIS1 (Bitfield-Mask: 0x01) */ -#define PORT0_PDISC_PDIS2_Pos \ - (2UL) /*!< PORT0 PDISC: PDIS2 (Bit 2) */ -#define PORT0_PDISC_PDIS2_Msk \ - (0x4UL) /*!< PORT0 PDISC: PDIS2 (Bitfield-Mask: 0x01) */ -#define PORT0_PDISC_PDIS3_Pos \ - (3UL) /*!< PORT0 PDISC: PDIS3 (Bit 3) */ -#define PORT0_PDISC_PDIS3_Msk \ - (0x8UL) /*!< PORT0 PDISC: PDIS3 (Bitfield-Mask: 0x01) */ -#define PORT0_PDISC_PDIS4_Pos \ - (4UL) /*!< PORT0 PDISC: PDIS4 (Bit 4) */ -#define PORT0_PDISC_PDIS4_Msk \ - (0x10UL) /*!< PORT0 PDISC: PDIS4 (Bitfield-Mask: 0x01) */ -#define PORT0_PDISC_PDIS5_Pos \ - (5UL) /*!< PORT0 PDISC: PDIS5 (Bit 5) */ -#define PORT0_PDISC_PDIS5_Msk \ - (0x20UL) /*!< PORT0 PDISC: PDIS5 (Bitfield-Mask: 0x01) */ -#define PORT0_PDISC_PDIS6_Pos \ - (6UL) /*!< PORT0 PDISC: PDIS6 (Bit 6) */ -#define PORT0_PDISC_PDIS6_Msk \ - (0x40UL) /*!< PORT0 PDISC: PDIS6 (Bitfield-Mask: 0x01) */ -#define PORT0_PDISC_PDIS7_Pos \ - (7UL) /*!< PORT0 PDISC: PDIS7 (Bit 7) */ -#define PORT0_PDISC_PDIS7_Msk \ - (0x80UL) /*!< PORT0 PDISC: PDIS7 (Bitfield-Mask: 0x01) */ -#define PORT0_PDISC_PDIS8_Pos \ - (8UL) /*!< PORT0 PDISC: PDIS8 (Bit 8) */ -#define PORT0_PDISC_PDIS8_Msk \ - (0x100UL) /*!< PORT0 PDISC: PDIS8 (Bitfield-Mask: 0x01) */ -#define PORT0_PDISC_PDIS9_Pos \ - (9UL) /*!< PORT0 PDISC: PDIS9 (Bit 9) */ -#define PORT0_PDISC_PDIS9_Msk \ - (0x200UL) /*!< PORT0 PDISC: PDIS9 (Bitfield-Mask: 0x01) */ -#define PORT0_PDISC_PDIS10_Pos \ - (10UL) /*!< PORT0 PDISC: PDIS10 (Bit 10) */ -#define PORT0_PDISC_PDIS10_Msk \ - (0x400UL) /*!< PORT0 PDISC: PDIS10 (Bitfield-Mask: 0x01) */ -#define PORT0_PDISC_PDIS11_Pos \ - (11UL) /*!< PORT0 PDISC: PDIS11 (Bit 11) */ -#define PORT0_PDISC_PDIS11_Msk \ - (0x800UL) /*!< PORT0 PDISC: PDIS11 (Bitfield-Mask: 0x01) */ -#define PORT0_PDISC_PDIS12_Pos \ - (12UL) /*!< PORT0 PDISC: PDIS12 (Bit 12) */ -#define PORT0_PDISC_PDIS12_Msk \ - (0x1000UL) /*!< PORT0 PDISC: PDIS12 (Bitfield-Mask: 0x01) */ -#define PORT0_PDISC_PDIS13_Pos \ - (13UL) /*!< PORT0 PDISC: PDIS13 (Bit 13) */ -#define PORT0_PDISC_PDIS13_Msk \ - (0x2000UL) /*!< PORT0 PDISC: PDIS13 (Bitfield-Mask: 0x01) */ -#define PORT0_PDISC_PDIS14_Pos \ - (14UL) /*!< PORT0 PDISC: PDIS14 (Bit 14) */ -#define PORT0_PDISC_PDIS14_Msk \ - (0x4000UL) /*!< PORT0 PDISC: PDIS14 (Bitfield-Mask: 0x01) */ -#define PORT0_PDISC_PDIS15_Pos \ - (15UL) /*!< PORT0 PDISC: PDIS15 (Bit 15) */ -#define PORT0_PDISC_PDIS15_Msk \ - (0x8000UL) /*!< PORT0 PDISC: PDIS15 (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- PORT0_PPS --------------------------------- */ -#define PORT0_PPS_PPS0_Pos (0UL) /*!< PORT0 PPS: PPS0 (Bit 0) */ -#define PORT0_PPS_PPS0_Msk \ - (0x1UL) /*!< PORT0 PPS: PPS0 (Bitfield-Mask: 0x01) */ -#define PORT0_PPS_PPS1_Pos (1UL) /*!< PORT0 PPS: PPS1 (Bit 1) */ -#define PORT0_PPS_PPS1_Msk \ - (0x2UL) /*!< PORT0 PPS: PPS1 (Bitfield-Mask: 0x01) */ -#define PORT0_PPS_PPS2_Pos (2UL) /*!< PORT0 PPS: PPS2 (Bit 2) */ -#define PORT0_PPS_PPS2_Msk \ - (0x4UL) /*!< PORT0 PPS: PPS2 (Bitfield-Mask: 0x01) */ -#define PORT0_PPS_PPS3_Pos (3UL) /*!< PORT0 PPS: PPS3 (Bit 3) */ -#define PORT0_PPS_PPS3_Msk \ - (0x8UL) /*!< PORT0 PPS: PPS3 (Bitfield-Mask: 0x01) */ -#define PORT0_PPS_PPS4_Pos (4UL) /*!< PORT0 PPS: PPS4 (Bit 4) */ -#define PORT0_PPS_PPS4_Msk \ - (0x10UL) /*!< PORT0 PPS: PPS4 (Bitfield-Mask: 0x01) */ -#define PORT0_PPS_PPS5_Pos (5UL) /*!< PORT0 PPS: PPS5 (Bit 5) */ -#define PORT0_PPS_PPS5_Msk \ - (0x20UL) /*!< PORT0 PPS: PPS5 (Bitfield-Mask: 0x01) */ -#define PORT0_PPS_PPS6_Pos (6UL) /*!< PORT0 PPS: PPS6 (Bit 6) */ -#define PORT0_PPS_PPS6_Msk \ - (0x40UL) /*!< PORT0 PPS: PPS6 (Bitfield-Mask: 0x01) */ -#define PORT0_PPS_PPS7_Pos (7UL) /*!< PORT0 PPS: PPS7 (Bit 7) */ -#define PORT0_PPS_PPS7_Msk \ - (0x80UL) /*!< PORT0 PPS: PPS7 (Bitfield-Mask: 0x01) */ -#define PORT0_PPS_PPS8_Pos (8UL) /*!< PORT0 PPS: PPS8 (Bit 8) */ -#define PORT0_PPS_PPS8_Msk \ - (0x100UL) /*!< PORT0 PPS: PPS8 (Bitfield-Mask: 0x01) */ -#define PORT0_PPS_PPS9_Pos (9UL) /*!< PORT0 PPS: PPS9 (Bit 9) */ -#define PORT0_PPS_PPS9_Msk \ - (0x200UL) /*!< PORT0 PPS: PPS9 (Bitfield-Mask: 0x01) */ -#define PORT0_PPS_PPS10_Pos \ - (10UL) /*!< PORT0 PPS: PPS10 (Bit 10) */ -#define PORT0_PPS_PPS10_Msk \ - (0x400UL) /*!< PORT0 PPS: PPS10 (Bitfield-Mask: 0x01) */ -#define PORT0_PPS_PPS11_Pos \ - (11UL) /*!< PORT0 PPS: PPS11 (Bit 11) */ -#define PORT0_PPS_PPS11_Msk \ - (0x800UL) /*!< PORT0 PPS: PPS11 (Bitfield-Mask: 0x01) */ -#define PORT0_PPS_PPS12_Pos \ - (12UL) /*!< PORT0 PPS: PPS12 (Bit 12) */ -#define PORT0_PPS_PPS12_Msk \ - (0x1000UL) /*!< PORT0 PPS: PPS12 (Bitfield-Mask: 0x01) */ -#define PORT0_PPS_PPS13_Pos \ - (13UL) /*!< PORT0 PPS: PPS13 (Bit 13) */ -#define PORT0_PPS_PPS13_Msk \ - (0x2000UL) /*!< PORT0 PPS: PPS13 (Bitfield-Mask: 0x01) */ -#define PORT0_PPS_PPS14_Pos \ - (14UL) /*!< PORT0 PPS: PPS14 (Bit 14) */ -#define PORT0_PPS_PPS14_Msk \ - (0x4000UL) /*!< PORT0 PPS: PPS14 (Bitfield-Mask: 0x01) */ -#define PORT0_PPS_PPS15_Pos \ - (15UL) /*!< PORT0 PPS: PPS15 (Bit 15) */ -#define PORT0_PPS_PPS15_Msk \ - (0x8000UL) /*!< PORT0 PPS: PPS15 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- PORT0_HWSEL -------------------------------- */ -#define PORT0_HWSEL_HW0_Pos \ - (0UL) /*!< PORT0 HWSEL: HW0 (Bit 0) */ -#define PORT0_HWSEL_HW0_Msk \ - (0x3UL) /*!< PORT0 HWSEL: HW0 (Bitfield-Mask: 0x03) */ -#define PORT0_HWSEL_HW1_Pos \ - (2UL) /*!< PORT0 HWSEL: HW1 (Bit 2) */ -#define PORT0_HWSEL_HW1_Msk \ - (0xcUL) /*!< PORT0 HWSEL: HW1 (Bitfield-Mask: 0x03) */ -#define PORT0_HWSEL_HW2_Pos \ - (4UL) /*!< PORT0 HWSEL: HW2 (Bit 4) */ -#define PORT0_HWSEL_HW2_Msk \ - (0x30UL) /*!< PORT0 HWSEL: HW2 (Bitfield-Mask: 0x03) */ -#define PORT0_HWSEL_HW3_Pos \ - (6UL) /*!< PORT0 HWSEL: HW3 (Bit 6) */ -#define PORT0_HWSEL_HW3_Msk \ - (0xc0UL) /*!< PORT0 HWSEL: HW3 (Bitfield-Mask: 0x03) */ -#define PORT0_HWSEL_HW4_Pos \ - (8UL) /*!< PORT0 HWSEL: HW4 (Bit 8) */ -#define PORT0_HWSEL_HW4_Msk \ - (0x300UL) /*!< PORT0 HWSEL: HW4 (Bitfield-Mask: 0x03) */ -#define PORT0_HWSEL_HW5_Pos \ - (10UL) /*!< PORT0 HWSEL: HW5 (Bit 10) */ -#define PORT0_HWSEL_HW5_Msk \ - (0xc00UL) /*!< PORT0 HWSEL: HW5 (Bitfield-Mask: 0x03) */ -#define PORT0_HWSEL_HW6_Pos \ - (12UL) /*!< PORT0 HWSEL: HW6 (Bit 12) */ -#define PORT0_HWSEL_HW6_Msk \ - (0x3000UL) /*!< PORT0 HWSEL: HW6 (Bitfield-Mask: 0x03) */ -#define PORT0_HWSEL_HW7_Pos \ - (14UL) /*!< PORT0 HWSEL: HW7 (Bit 14) */ -#define PORT0_HWSEL_HW7_Msk \ - (0xc000UL) /*!< PORT0 HWSEL: HW7 (Bitfield-Mask: 0x03) */ -#define PORT0_HWSEL_HW8_Pos \ - (16UL) /*!< PORT0 HWSEL: HW8 (Bit 16) */ -#define PORT0_HWSEL_HW8_Msk \ - (0x30000UL) /*!< PORT0 HWSEL: HW8 (Bitfield-Mask: 0x03) */ -#define PORT0_HWSEL_HW9_Pos \ - (18UL) /*!< PORT0 HWSEL: HW9 (Bit 18) */ -#define PORT0_HWSEL_HW9_Msk \ - (0xc0000UL) /*!< PORT0 HWSEL: HW9 (Bitfield-Mask: 0x03) */ -#define PORT0_HWSEL_HW10_Pos \ - (20UL) /*!< PORT0 HWSEL: HW10 (Bit 20) */ -#define PORT0_HWSEL_HW10_Msk \ - (0x300000UL) /*!< PORT0 HWSEL: HW10 (Bitfield-Mask: 0x03) */ -#define PORT0_HWSEL_HW11_Pos \ - (22UL) /*!< PORT0 HWSEL: HW11 (Bit 22) */ -#define PORT0_HWSEL_HW11_Msk \ - (0xc00000UL) /*!< PORT0 HWSEL: HW11 (Bitfield-Mask: 0x03) */ -#define PORT0_HWSEL_HW12_Pos \ - (24UL) /*!< PORT0 HWSEL: HW12 (Bit 24) */ -#define PORT0_HWSEL_HW12_Msk \ - (0x3000000UL) /*!< PORT0 HWSEL: HW12 (Bitfield-Mask: 0x03) */ -#define PORT0_HWSEL_HW13_Pos \ - (26UL) /*!< PORT0 HWSEL: HW13 (Bit 26) */ -#define PORT0_HWSEL_HW13_Msk \ - (0xc000000UL) /*!< PORT0 HWSEL: HW13 (Bitfield-Mask: 0x03) */ -#define PORT0_HWSEL_HW14_Pos \ - (28UL) /*!< PORT0 HWSEL: HW14 (Bit 28) */ -#define PORT0_HWSEL_HW14_Msk \ - (0x30000000UL) /*!< PORT0 HWSEL: HW14 (Bitfield-Mask: 0x03) */ -#define PORT0_HWSEL_HW15_Pos \ - (30UL) /*!< PORT0 HWSEL: HW15 (Bit 30) */ -#define PORT0_HWSEL_HW15_Msk \ - (0xc0000000UL) /*!< PORT0 HWSEL: HW15 (Bitfield-Mask: 0x03) */ - -/* ================================================================================ */ -/* ================ struct 'PORT1' Position & Mask ================ */ -/* ================================================================================ */ - -/* ---------------------------------- PORT1_OUT --------------------------------- */ -#define PORT1_OUT_P0_Pos (0UL) /*!< PORT1 OUT: P0 (Bit 0) */ -#define PORT1_OUT_P0_Msk (0x1UL) /*!< PORT1 OUT: P0 (Bitfield-Mask: 0x01) */ -#define PORT1_OUT_P1_Pos (1UL) /*!< PORT1 OUT: P1 (Bit 1) */ -#define PORT1_OUT_P1_Msk (0x2UL) /*!< PORT1 OUT: P1 (Bitfield-Mask: 0x01) */ -#define PORT1_OUT_P2_Pos (2UL) /*!< PORT1 OUT: P2 (Bit 2) */ -#define PORT1_OUT_P2_Msk (0x4UL) /*!< PORT1 OUT: P2 (Bitfield-Mask: 0x01) */ -#define PORT1_OUT_P3_Pos (3UL) /*!< PORT1 OUT: P3 (Bit 3) */ -#define PORT1_OUT_P3_Msk (0x8UL) /*!< PORT1 OUT: P3 (Bitfield-Mask: 0x01) */ -#define PORT1_OUT_P4_Pos (4UL) /*!< PORT1 OUT: P4 (Bit 4) */ -#define PORT1_OUT_P4_Msk \ - (0x10UL) /*!< PORT1 OUT: P4 (Bitfield-Mask: 0x01) */ -#define PORT1_OUT_P5_Pos (5UL) /*!< PORT1 OUT: P5 (Bit 5) */ -#define PORT1_OUT_P5_Msk \ - (0x20UL) /*!< PORT1 OUT: P5 (Bitfield-Mask: 0x01) */ -#define PORT1_OUT_P6_Pos (6UL) /*!< PORT1 OUT: P6 (Bit 6) */ -#define PORT1_OUT_P6_Msk \ - (0x40UL) /*!< PORT1 OUT: P6 (Bitfield-Mask: 0x01) */ -#define PORT1_OUT_P7_Pos (7UL) /*!< PORT1 OUT: P7 (Bit 7) */ -#define PORT1_OUT_P7_Msk \ - (0x80UL) /*!< PORT1 OUT: P7 (Bitfield-Mask: 0x01) */ -#define PORT1_OUT_P8_Pos (8UL) /*!< PORT1 OUT: P8 (Bit 8) */ -#define PORT1_OUT_P8_Msk \ - (0x100UL) /*!< PORT1 OUT: P8 (Bitfield-Mask: 0x01) */ -#define PORT1_OUT_P9_Pos (9UL) /*!< PORT1 OUT: P9 (Bit 9) */ -#define PORT1_OUT_P9_Msk \ - (0x200UL) /*!< PORT1 OUT: P9 (Bitfield-Mask: 0x01) */ -#define PORT1_OUT_P10_Pos (10UL) /*!< PORT1 OUT: P10 (Bit 10) */ -#define PORT1_OUT_P10_Msk \ - (0x400UL) /*!< PORT1 OUT: P10 (Bitfield-Mask: 0x01) */ -#define PORT1_OUT_P11_Pos (11UL) /*!< PORT1 OUT: P11 (Bit 11) */ -#define PORT1_OUT_P11_Msk \ - (0x800UL) /*!< PORT1 OUT: P11 (Bitfield-Mask: 0x01) */ -#define PORT1_OUT_P12_Pos (12UL) /*!< PORT1 OUT: P12 (Bit 12) */ -#define PORT1_OUT_P12_Msk \ - (0x1000UL) /*!< PORT1 OUT: P12 (Bitfield-Mask: 0x01) */ -#define PORT1_OUT_P13_Pos (13UL) /*!< PORT1 OUT: P13 (Bit 13) */ -#define PORT1_OUT_P13_Msk \ - (0x2000UL) /*!< PORT1 OUT: P13 (Bitfield-Mask: 0x01) */ -#define PORT1_OUT_P14_Pos (14UL) /*!< PORT1 OUT: P14 (Bit 14) */ -#define PORT1_OUT_P14_Msk \ - (0x4000UL) /*!< PORT1 OUT: P14 (Bitfield-Mask: 0x01) */ -#define PORT1_OUT_P15_Pos (15UL) /*!< PORT1 OUT: P15 (Bit 15) */ -#define PORT1_OUT_P15_Msk \ - (0x8000UL) /*!< PORT1 OUT: P15 (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- PORT1_OMR --------------------------------- */ -#define PORT1_OMR_PS0_Pos (0UL) /*!< PORT1 OMR: PS0 (Bit 0) */ -#define PORT1_OMR_PS0_Msk \ - (0x1UL) /*!< PORT1 OMR: PS0 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PS1_Pos (1UL) /*!< PORT1 OMR: PS1 (Bit 1) */ -#define PORT1_OMR_PS1_Msk \ - (0x2UL) /*!< PORT1 OMR: PS1 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PS2_Pos (2UL) /*!< PORT1 OMR: PS2 (Bit 2) */ -#define PORT1_OMR_PS2_Msk \ - (0x4UL) /*!< PORT1 OMR: PS2 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PS3_Pos (3UL) /*!< PORT1 OMR: PS3 (Bit 3) */ -#define PORT1_OMR_PS3_Msk \ - (0x8UL) /*!< PORT1 OMR: PS3 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PS4_Pos (4UL) /*!< PORT1 OMR: PS4 (Bit 4) */ -#define PORT1_OMR_PS4_Msk \ - (0x10UL) /*!< PORT1 OMR: PS4 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PS5_Pos (5UL) /*!< PORT1 OMR: PS5 (Bit 5) */ -#define PORT1_OMR_PS5_Msk \ - (0x20UL) /*!< PORT1 OMR: PS5 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PS6_Pos (6UL) /*!< PORT1 OMR: PS6 (Bit 6) */ -#define PORT1_OMR_PS6_Msk \ - (0x40UL) /*!< PORT1 OMR: PS6 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PS7_Pos (7UL) /*!< PORT1 OMR: PS7 (Bit 7) */ -#define PORT1_OMR_PS7_Msk \ - (0x80UL) /*!< PORT1 OMR: PS7 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PS8_Pos (8UL) /*!< PORT1 OMR: PS8 (Bit 8) */ -#define PORT1_OMR_PS8_Msk \ - (0x100UL) /*!< PORT1 OMR: PS8 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PS9_Pos (9UL) /*!< PORT1 OMR: PS9 (Bit 9) */ -#define PORT1_OMR_PS9_Msk \ - (0x200UL) /*!< PORT1 OMR: PS9 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PS10_Pos \ - (10UL) /*!< PORT1 OMR: PS10 (Bit 10) */ -#define PORT1_OMR_PS10_Msk \ - (0x400UL) /*!< PORT1 OMR: PS10 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PS11_Pos \ - (11UL) /*!< PORT1 OMR: PS11 (Bit 11) */ -#define PORT1_OMR_PS11_Msk \ - (0x800UL) /*!< PORT1 OMR: PS11 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PS12_Pos \ - (12UL) /*!< PORT1 OMR: PS12 (Bit 12) */ -#define PORT1_OMR_PS12_Msk \ - (0x1000UL) /*!< PORT1 OMR: PS12 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PS13_Pos \ - (13UL) /*!< PORT1 OMR: PS13 (Bit 13) */ -#define PORT1_OMR_PS13_Msk \ - (0x2000UL) /*!< PORT1 OMR: PS13 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PS14_Pos \ - (14UL) /*!< PORT1 OMR: PS14 (Bit 14) */ -#define PORT1_OMR_PS14_Msk \ - (0x4000UL) /*!< PORT1 OMR: PS14 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PS15_Pos \ - (15UL) /*!< PORT1 OMR: PS15 (Bit 15) */ -#define PORT1_OMR_PS15_Msk \ - (0x8000UL) /*!< PORT1 OMR: PS15 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PR0_Pos (16UL) /*!< PORT1 OMR: PR0 (Bit 16) */ -#define PORT1_OMR_PR0_Msk \ - (0x10000UL) /*!< PORT1 OMR: PR0 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PR1_Pos (17UL) /*!< PORT1 OMR: PR1 (Bit 17) */ -#define PORT1_OMR_PR1_Msk \ - (0x20000UL) /*!< PORT1 OMR: PR1 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PR2_Pos (18UL) /*!< PORT1 OMR: PR2 (Bit 18) */ -#define PORT1_OMR_PR2_Msk \ - (0x40000UL) /*!< PORT1 OMR: PR2 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PR3_Pos (19UL) /*!< PORT1 OMR: PR3 (Bit 19) */ -#define PORT1_OMR_PR3_Msk \ - (0x80000UL) /*!< PORT1 OMR: PR3 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PR4_Pos (20UL) /*!< PORT1 OMR: PR4 (Bit 20) */ -#define PORT1_OMR_PR4_Msk \ - (0x100000UL) /*!< PORT1 OMR: PR4 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PR5_Pos (21UL) /*!< PORT1 OMR: PR5 (Bit 21) */ -#define PORT1_OMR_PR5_Msk \ - (0x200000UL) /*!< PORT1 OMR: PR5 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PR6_Pos (22UL) /*!< PORT1 OMR: PR6 (Bit 22) */ -#define PORT1_OMR_PR6_Msk \ - (0x400000UL) /*!< PORT1 OMR: PR6 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PR7_Pos (23UL) /*!< PORT1 OMR: PR7 (Bit 23) */ -#define PORT1_OMR_PR7_Msk \ - (0x800000UL) /*!< PORT1 OMR: PR7 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PR8_Pos (24UL) /*!< PORT1 OMR: PR8 (Bit 24) */ -#define PORT1_OMR_PR8_Msk \ - (0x1000000UL) /*!< PORT1 OMR: PR8 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PR9_Pos (25UL) /*!< PORT1 OMR: PR9 (Bit 25) */ -#define PORT1_OMR_PR9_Msk \ - (0x2000000UL) /*!< PORT1 OMR: PR9 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PR10_Pos \ - (26UL) /*!< PORT1 OMR: PR10 (Bit 26) */ -#define PORT1_OMR_PR10_Msk \ - (0x4000000UL) /*!< PORT1 OMR: PR10 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PR11_Pos \ - (27UL) /*!< PORT1 OMR: PR11 (Bit 27) */ -#define PORT1_OMR_PR11_Msk \ - (0x8000000UL) /*!< PORT1 OMR: PR11 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PR12_Pos \ - (28UL) /*!< PORT1 OMR: PR12 (Bit 28) */ -#define PORT1_OMR_PR12_Msk \ - (0x10000000UL) /*!< PORT1 OMR: PR12 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PR13_Pos \ - (29UL) /*!< PORT1 OMR: PR13 (Bit 29) */ -#define PORT1_OMR_PR13_Msk \ - (0x20000000UL) /*!< PORT1 OMR: PR13 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PR14_Pos \ - (30UL) /*!< PORT1 OMR: PR14 (Bit 30) */ -#define PORT1_OMR_PR14_Msk \ - (0x40000000UL) /*!< PORT1 OMR: PR14 (Bitfield-Mask: 0x01) */ -#define PORT1_OMR_PR15_Pos \ - (31UL) /*!< PORT1 OMR: PR15 (Bit 31) */ -#define PORT1_OMR_PR15_Msk \ - (0x80000000UL) /*!< PORT1 OMR: PR15 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- PORT1_IOCR0 -------------------------------- */ -#define PORT1_IOCR0_PC0_Pos \ - (3UL) /*!< PORT1 IOCR0: PC0 (Bit 3) */ -#define PORT1_IOCR0_PC0_Msk \ - (0xf8UL) /*!< PORT1 IOCR0: PC0 (Bitfield-Mask: 0x1f) */ -#define PORT1_IOCR0_PC1_Pos \ - (11UL) /*!< PORT1 IOCR0: PC1 (Bit 11) */ -#define PORT1_IOCR0_PC1_Msk \ - (0xf800UL) /*!< PORT1 IOCR0: PC1 (Bitfield-Mask: 0x1f) */ -#define PORT1_IOCR0_PC2_Pos \ - (19UL) /*!< PORT1 IOCR0: PC2 (Bit 19) */ -#define PORT1_IOCR0_PC2_Msk \ - (0xf80000UL) /*!< PORT1 IOCR0: PC2 (Bitfield-Mask: 0x1f) */ -#define PORT1_IOCR0_PC3_Pos \ - (27UL) /*!< PORT1 IOCR0: PC3 (Bit 27) */ -#define PORT1_IOCR0_PC3_Msk \ - (0xf8000000UL) /*!< PORT1 IOCR0: PC3 (Bitfield-Mask: 0x1f) */ - -/* --------------------------------- PORT1_IOCR4 -------------------------------- */ -#define PORT1_IOCR4_PC4_Pos \ - (3UL) /*!< PORT1 IOCR4: PC4 (Bit 3) */ -#define PORT1_IOCR4_PC4_Msk \ - (0xf8UL) /*!< PORT1 IOCR4: PC4 (Bitfield-Mask: 0x1f) */ -#define PORT1_IOCR4_PC5_Pos \ - (11UL) /*!< PORT1 IOCR4: PC5 (Bit 11) */ -#define PORT1_IOCR4_PC5_Msk \ - (0xf800UL) /*!< PORT1 IOCR4: PC5 (Bitfield-Mask: 0x1f) */ -#define PORT1_IOCR4_PC6_Pos \ - (19UL) /*!< PORT1 IOCR4: PC6 (Bit 19) */ -#define PORT1_IOCR4_PC6_Msk \ - (0xf80000UL) /*!< PORT1 IOCR4: PC6 (Bitfield-Mask: 0x1f) */ -#define PORT1_IOCR4_PC7_Pos \ - (27UL) /*!< PORT1 IOCR4: PC7 (Bit 27) */ -#define PORT1_IOCR4_PC7_Msk \ - (0xf8000000UL) /*!< PORT1 IOCR4: PC7 (Bitfield-Mask: 0x1f) */ - -/* --------------------------------- PORT1_IOCR8 -------------------------------- */ -#define PORT1_IOCR8_PC8_Pos \ - (3UL) /*!< PORT1 IOCR8: PC8 (Bit 3) */ -#define PORT1_IOCR8_PC8_Msk \ - (0xf8UL) /*!< PORT1 IOCR8: PC8 (Bitfield-Mask: 0x1f) */ -#define PORT1_IOCR8_PC9_Pos \ - (11UL) /*!< PORT1 IOCR8: PC9 (Bit 11) */ -#define PORT1_IOCR8_PC9_Msk \ - (0xf800UL) /*!< PORT1 IOCR8: PC9 (Bitfield-Mask: 0x1f) */ -#define PORT1_IOCR8_PC10_Pos \ - (19UL) /*!< PORT1 IOCR8: PC10 (Bit 19) */ -#define PORT1_IOCR8_PC10_Msk \ - (0xf80000UL) /*!< PORT1 IOCR8: PC10 (Bitfield-Mask: 0x1f) */ -#define PORT1_IOCR8_PC11_Pos \ - (27UL) /*!< PORT1 IOCR8: PC11 (Bit 27) */ -#define PORT1_IOCR8_PC11_Msk \ - (0xf8000000UL) /*!< PORT1 IOCR8: PC11 (Bitfield-Mask: 0x1f) */ - -/* -------------------------------- PORT1_IOCR12 -------------------------------- */ -#define PORT1_IOCR12_PC12_Pos \ - (3UL) /*!< PORT1 IOCR12: PC12 (Bit 3) */ -#define PORT1_IOCR12_PC12_Msk \ - (0xf8UL) /*!< PORT1 IOCR12: PC12 (Bitfield-Mask: 0x1f) */ -#define PORT1_IOCR12_PC13_Pos \ - (11UL) /*!< PORT1 IOCR12: PC13 (Bit 11) */ -#define PORT1_IOCR12_PC13_Msk \ - (0xf800UL) /*!< PORT1 IOCR12: PC13 (Bitfield-Mask: 0x1f) */ -#define PORT1_IOCR12_PC14_Pos \ - (19UL) /*!< PORT1 IOCR12: PC14 (Bit 19) */ -#define PORT1_IOCR12_PC14_Msk \ - (0xf80000UL) /*!< PORT1 IOCR12: PC14 (Bitfield-Mask: 0x1f) */ -#define PORT1_IOCR12_PC15_Pos \ - (27UL) /*!< PORT1 IOCR12: PC15 (Bit 27) */ -#define PORT1_IOCR12_PC15_Msk \ - (0xf8000000UL) /*!< PORT1 IOCR12: PC15 (Bitfield-Mask: 0x1f) */ - -/* ---------------------------------- PORT1_IN ---------------------------------- */ -#define PORT1_IN_P0_Pos (0UL) /*!< PORT1 IN: P0 (Bit 0) */ -#define PORT1_IN_P0_Msk (0x1UL) /*!< PORT1 IN: P0 (Bitfield-Mask: 0x01) */ -#define PORT1_IN_P1_Pos (1UL) /*!< PORT1 IN: P1 (Bit 1) */ -#define PORT1_IN_P1_Msk (0x2UL) /*!< PORT1 IN: P1 (Bitfield-Mask: 0x01) */ -#define PORT1_IN_P2_Pos (2UL) /*!< PORT1 IN: P2 (Bit 2) */ -#define PORT1_IN_P2_Msk (0x4UL) /*!< PORT1 IN: P2 (Bitfield-Mask: 0x01) */ -#define PORT1_IN_P3_Pos (3UL) /*!< PORT1 IN: P3 (Bit 3) */ -#define PORT1_IN_P3_Msk (0x8UL) /*!< PORT1 IN: P3 (Bitfield-Mask: 0x01) */ -#define PORT1_IN_P4_Pos (4UL) /*!< PORT1 IN: P4 (Bit 4) */ -#define PORT1_IN_P4_Msk (0x10UL) /*!< PORT1 IN: P4 (Bitfield-Mask: 0x01) */ -#define PORT1_IN_P5_Pos (5UL) /*!< PORT1 IN: P5 (Bit 5) */ -#define PORT1_IN_P5_Msk (0x20UL) /*!< PORT1 IN: P5 (Bitfield-Mask: 0x01) */ -#define PORT1_IN_P6_Pos (6UL) /*!< PORT1 IN: P6 (Bit 6) */ -#define PORT1_IN_P6_Msk (0x40UL) /*!< PORT1 IN: P6 (Bitfield-Mask: 0x01) */ -#define PORT1_IN_P7_Pos (7UL) /*!< PORT1 IN: P7 (Bit 7) */ -#define PORT1_IN_P7_Msk (0x80UL) /*!< PORT1 IN: P7 (Bitfield-Mask: 0x01) */ -#define PORT1_IN_P8_Pos (8UL) /*!< PORT1 IN: P8 (Bit 8) */ -#define PORT1_IN_P8_Msk \ - (0x100UL) /*!< PORT1 IN: P8 (Bitfield-Mask: 0x01) */ -#define PORT1_IN_P9_Pos (9UL) /*!< PORT1 IN: P9 (Bit 9) */ -#define PORT1_IN_P9_Msk \ - (0x200UL) /*!< PORT1 IN: P9 (Bitfield-Mask: 0x01) */ -#define PORT1_IN_P10_Pos (10UL) /*!< PORT1 IN: P10 (Bit 10) */ -#define PORT1_IN_P10_Msk \ - (0x400UL) /*!< PORT1 IN: P10 (Bitfield-Mask: 0x01) */ -#define PORT1_IN_P11_Pos (11UL) /*!< PORT1 IN: P11 (Bit 11) */ -#define PORT1_IN_P11_Msk \ - (0x800UL) /*!< PORT1 IN: P11 (Bitfield-Mask: 0x01) */ -#define PORT1_IN_P12_Pos (12UL) /*!< PORT1 IN: P12 (Bit 12) */ -#define PORT1_IN_P12_Msk \ - (0x1000UL) /*!< PORT1 IN: P12 (Bitfield-Mask: 0x01) */ -#define PORT1_IN_P13_Pos (13UL) /*!< PORT1 IN: P13 (Bit 13) */ -#define PORT1_IN_P13_Msk \ - (0x2000UL) /*!< PORT1 IN: P13 (Bitfield-Mask: 0x01) */ -#define PORT1_IN_P14_Pos (14UL) /*!< PORT1 IN: P14 (Bit 14) */ -#define PORT1_IN_P14_Msk \ - (0x4000UL) /*!< PORT1 IN: P14 (Bitfield-Mask: 0x01) */ -#define PORT1_IN_P15_Pos (15UL) /*!< PORT1 IN: P15 (Bit 15) */ -#define PORT1_IN_P15_Msk \ - (0x8000UL) /*!< PORT1 IN: P15 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- PORT1_PDR0 --------------------------------- */ -#define PORT1_PDR0_PD0_Pos (0UL) /*!< PORT1 PDR0: PD0 (Bit 0) */ -#define PORT1_PDR0_PD0_Msk \ - (0x7UL) /*!< PORT1 PDR0: PD0 (Bitfield-Mask: 0x07) */ -#define PORT1_PDR0_PD1_Pos (4UL) /*!< PORT1 PDR0: PD1 (Bit 4) */ -#define PORT1_PDR0_PD1_Msk \ - (0x70UL) /*!< PORT1 PDR0: PD1 (Bitfield-Mask: 0x07) */ -#define PORT1_PDR0_PD2_Pos (8UL) /*!< PORT1 PDR0: PD2 (Bit 8) */ -#define PORT1_PDR0_PD2_Msk \ - (0x700UL) /*!< PORT1 PDR0: PD2 (Bitfield-Mask: 0x07) */ -#define PORT1_PDR0_PD3_Pos \ - (12UL) /*!< PORT1 PDR0: PD3 (Bit 12) */ -#define PORT1_PDR0_PD3_Msk \ - (0x7000UL) /*!< PORT1 PDR0: PD3 (Bitfield-Mask: 0x07) */ -#define PORT1_PDR0_PD4_Pos \ - (16UL) /*!< PORT1 PDR0: PD4 (Bit 16) */ -#define PORT1_PDR0_PD4_Msk \ - (0x70000UL) /*!< PORT1 PDR0: PD4 (Bitfield-Mask: 0x07) */ -#define PORT1_PDR0_PD5_Pos \ - (20UL) /*!< PORT1 PDR0: PD5 (Bit 20) */ -#define PORT1_PDR0_PD5_Msk \ - (0x700000UL) /*!< PORT1 PDR0: PD5 (Bitfield-Mask: 0x07) */ -#define PORT1_PDR0_PD6_Pos \ - (24UL) /*!< PORT1 PDR0: PD6 (Bit 24) */ -#define PORT1_PDR0_PD6_Msk \ - (0x7000000UL) /*!< PORT1 PDR0: PD6 (Bitfield-Mask: 0x07) */ -#define PORT1_PDR0_PD7_Pos \ - (28UL) /*!< PORT1 PDR0: PD7 (Bit 28) */ -#define PORT1_PDR0_PD7_Msk \ - (0x70000000UL) /*!< PORT1 PDR0: PD7 (Bitfield-Mask: 0x07) */ - -/* --------------------------------- PORT1_PDR1 --------------------------------- */ -#define PORT1_PDR1_PD8_Pos (0UL) /*!< PORT1 PDR1: PD8 (Bit 0) */ -#define PORT1_PDR1_PD8_Msk \ - (0x7UL) /*!< PORT1 PDR1: PD8 (Bitfield-Mask: 0x07) */ -#define PORT1_PDR1_PD9_Pos (4UL) /*!< PORT1 PDR1: PD9 (Bit 4) */ -#define PORT1_PDR1_PD9_Msk \ - (0x70UL) /*!< PORT1 PDR1: PD9 (Bitfield-Mask: 0x07) */ -#define PORT1_PDR1_PD10_Pos \ - (8UL) /*!< PORT1 PDR1: PD10 (Bit 8) */ -#define PORT1_PDR1_PD10_Msk \ - (0x700UL) /*!< PORT1 PDR1: PD10 (Bitfield-Mask: 0x07) */ -#define PORT1_PDR1_PD11_Pos \ - (12UL) /*!< PORT1 PDR1: PD11 (Bit 12) */ -#define PORT1_PDR1_PD11_Msk \ - (0x7000UL) /*!< PORT1 PDR1: PD11 (Bitfield-Mask: 0x07) */ -#define PORT1_PDR1_PD12_Pos \ - (16UL) /*!< PORT1 PDR1: PD12 (Bit 16) */ -#define PORT1_PDR1_PD12_Msk \ - (0x70000UL) /*!< PORT1 PDR1: PD12 (Bitfield-Mask: 0x07) */ -#define PORT1_PDR1_PD13_Pos \ - (20UL) /*!< PORT1 PDR1: PD13 (Bit 20) */ -#define PORT1_PDR1_PD13_Msk \ - (0x700000UL) /*!< PORT1 PDR1: PD13 (Bitfield-Mask: 0x07) */ -#define PORT1_PDR1_PD14_Pos \ - (24UL) /*!< PORT1 PDR1: PD14 (Bit 24) */ -#define PORT1_PDR1_PD14_Msk \ - (0x7000000UL) /*!< PORT1 PDR1: PD14 (Bitfield-Mask: 0x07) */ -#define PORT1_PDR1_PD15_Pos \ - (28UL) /*!< PORT1 PDR1: PD15 (Bit 28) */ -#define PORT1_PDR1_PD15_Msk \ - (0x70000000UL) /*!< PORT1 PDR1: PD15 (Bitfield-Mask: 0x07) */ - -/* --------------------------------- PORT1_PDISC -------------------------------- */ -#define PORT1_PDISC_PDIS0_Pos \ - (0UL) /*!< PORT1 PDISC: PDIS0 (Bit 0) */ -#define PORT1_PDISC_PDIS0_Msk \ - (0x1UL) /*!< PORT1 PDISC: PDIS0 (Bitfield-Mask: 0x01) */ -#define PORT1_PDISC_PDIS1_Pos \ - (1UL) /*!< PORT1 PDISC: PDIS1 (Bit 1) */ -#define PORT1_PDISC_PDIS1_Msk \ - (0x2UL) /*!< PORT1 PDISC: PDIS1 (Bitfield-Mask: 0x01) */ -#define PORT1_PDISC_PDIS2_Pos \ - (2UL) /*!< PORT1 PDISC: PDIS2 (Bit 2) */ -#define PORT1_PDISC_PDIS2_Msk \ - (0x4UL) /*!< PORT1 PDISC: PDIS2 (Bitfield-Mask: 0x01) */ -#define PORT1_PDISC_PDIS3_Pos \ - (3UL) /*!< PORT1 PDISC: PDIS3 (Bit 3) */ -#define PORT1_PDISC_PDIS3_Msk \ - (0x8UL) /*!< PORT1 PDISC: PDIS3 (Bitfield-Mask: 0x01) */ -#define PORT1_PDISC_PDIS4_Pos \ - (4UL) /*!< PORT1 PDISC: PDIS4 (Bit 4) */ -#define PORT1_PDISC_PDIS4_Msk \ - (0x10UL) /*!< PORT1 PDISC: PDIS4 (Bitfield-Mask: 0x01) */ -#define PORT1_PDISC_PDIS5_Pos \ - (5UL) /*!< PORT1 PDISC: PDIS5 (Bit 5) */ -#define PORT1_PDISC_PDIS5_Msk \ - (0x20UL) /*!< PORT1 PDISC: PDIS5 (Bitfield-Mask: 0x01) */ -#define PORT1_PDISC_PDIS6_Pos \ - (6UL) /*!< PORT1 PDISC: PDIS6 (Bit 6) */ -#define PORT1_PDISC_PDIS6_Msk \ - (0x40UL) /*!< PORT1 PDISC: PDIS6 (Bitfield-Mask: 0x01) */ -#define PORT1_PDISC_PDIS7_Pos \ - (7UL) /*!< PORT1 PDISC: PDIS7 (Bit 7) */ -#define PORT1_PDISC_PDIS7_Msk \ - (0x80UL) /*!< PORT1 PDISC: PDIS7 (Bitfield-Mask: 0x01) */ -#define PORT1_PDISC_PDIS8_Pos \ - (8UL) /*!< PORT1 PDISC: PDIS8 (Bit 8) */ -#define PORT1_PDISC_PDIS8_Msk \ - (0x100UL) /*!< PORT1 PDISC: PDIS8 (Bitfield-Mask: 0x01) */ -#define PORT1_PDISC_PDIS9_Pos \ - (9UL) /*!< PORT1 PDISC: PDIS9 (Bit 9) */ -#define PORT1_PDISC_PDIS9_Msk \ - (0x200UL) /*!< PORT1 PDISC: PDIS9 (Bitfield-Mask: 0x01) */ -#define PORT1_PDISC_PDIS10_Pos \ - (10UL) /*!< PORT1 PDISC: PDIS10 (Bit 10) */ -#define PORT1_PDISC_PDIS10_Msk \ - (0x400UL) /*!< PORT1 PDISC: PDIS10 (Bitfield-Mask: 0x01) */ -#define PORT1_PDISC_PDIS11_Pos \ - (11UL) /*!< PORT1 PDISC: PDIS11 (Bit 11) */ -#define PORT1_PDISC_PDIS11_Msk \ - (0x800UL) /*!< PORT1 PDISC: PDIS11 (Bitfield-Mask: 0x01) */ -#define PORT1_PDISC_PDIS12_Pos \ - (12UL) /*!< PORT1 PDISC: PDIS12 (Bit 12) */ -#define PORT1_PDISC_PDIS12_Msk \ - (0x1000UL) /*!< PORT1 PDISC: PDIS12 (Bitfield-Mask: 0x01) */ -#define PORT1_PDISC_PDIS13_Pos \ - (13UL) /*!< PORT1 PDISC: PDIS13 (Bit 13) */ -#define PORT1_PDISC_PDIS13_Msk \ - (0x2000UL) /*!< PORT1 PDISC: PDIS13 (Bitfield-Mask: 0x01) */ -#define PORT1_PDISC_PDIS14_Pos \ - (14UL) /*!< PORT1 PDISC: PDIS14 (Bit 14) */ -#define PORT1_PDISC_PDIS14_Msk \ - (0x4000UL) /*!< PORT1 PDISC: PDIS14 (Bitfield-Mask: 0x01) */ -#define PORT1_PDISC_PDIS15_Pos \ - (15UL) /*!< PORT1 PDISC: PDIS15 (Bit 15) */ -#define PORT1_PDISC_PDIS15_Msk \ - (0x8000UL) /*!< PORT1 PDISC: PDIS15 (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- PORT1_PPS --------------------------------- */ -#define PORT1_PPS_PPS0_Pos (0UL) /*!< PORT1 PPS: PPS0 (Bit 0) */ -#define PORT1_PPS_PPS0_Msk \ - (0x1UL) /*!< PORT1 PPS: PPS0 (Bitfield-Mask: 0x01) */ -#define PORT1_PPS_PPS1_Pos (1UL) /*!< PORT1 PPS: PPS1 (Bit 1) */ -#define PORT1_PPS_PPS1_Msk \ - (0x2UL) /*!< PORT1 PPS: PPS1 (Bitfield-Mask: 0x01) */ -#define PORT1_PPS_PPS2_Pos (2UL) /*!< PORT1 PPS: PPS2 (Bit 2) */ -#define PORT1_PPS_PPS2_Msk \ - (0x4UL) /*!< PORT1 PPS: PPS2 (Bitfield-Mask: 0x01) */ -#define PORT1_PPS_PPS3_Pos (3UL) /*!< PORT1 PPS: PPS3 (Bit 3) */ -#define PORT1_PPS_PPS3_Msk \ - (0x8UL) /*!< PORT1 PPS: PPS3 (Bitfield-Mask: 0x01) */ -#define PORT1_PPS_PPS4_Pos (4UL) /*!< PORT1 PPS: PPS4 (Bit 4) */ -#define PORT1_PPS_PPS4_Msk \ - (0x10UL) /*!< PORT1 PPS: PPS4 (Bitfield-Mask: 0x01) */ -#define PORT1_PPS_PPS5_Pos (5UL) /*!< PORT1 PPS: PPS5 (Bit 5) */ -#define PORT1_PPS_PPS5_Msk \ - (0x20UL) /*!< PORT1 PPS: PPS5 (Bitfield-Mask: 0x01) */ -#define PORT1_PPS_PPS6_Pos (6UL) /*!< PORT1 PPS: PPS6 (Bit 6) */ -#define PORT1_PPS_PPS6_Msk \ - (0x40UL) /*!< PORT1 PPS: PPS6 (Bitfield-Mask: 0x01) */ -#define PORT1_PPS_PPS7_Pos (7UL) /*!< PORT1 PPS: PPS7 (Bit 7) */ -#define PORT1_PPS_PPS7_Msk \ - (0x80UL) /*!< PORT1 PPS: PPS7 (Bitfield-Mask: 0x01) */ -#define PORT1_PPS_PPS8_Pos (8UL) /*!< PORT1 PPS: PPS8 (Bit 8) */ -#define PORT1_PPS_PPS8_Msk \ - (0x100UL) /*!< PORT1 PPS: PPS8 (Bitfield-Mask: 0x01) */ -#define PORT1_PPS_PPS9_Pos (9UL) /*!< PORT1 PPS: PPS9 (Bit 9) */ -#define PORT1_PPS_PPS9_Msk \ - (0x200UL) /*!< PORT1 PPS: PPS9 (Bitfield-Mask: 0x01) */ -#define PORT1_PPS_PPS10_Pos \ - (10UL) /*!< PORT1 PPS: PPS10 (Bit 10) */ -#define PORT1_PPS_PPS10_Msk \ - (0x400UL) /*!< PORT1 PPS: PPS10 (Bitfield-Mask: 0x01) */ -#define PORT1_PPS_PPS11_Pos \ - (11UL) /*!< PORT1 PPS: PPS11 (Bit 11) */ -#define PORT1_PPS_PPS11_Msk \ - (0x800UL) /*!< PORT1 PPS: PPS11 (Bitfield-Mask: 0x01) */ -#define PORT1_PPS_PPS12_Pos \ - (12UL) /*!< PORT1 PPS: PPS12 (Bit 12) */ -#define PORT1_PPS_PPS12_Msk \ - (0x1000UL) /*!< PORT1 PPS: PPS12 (Bitfield-Mask: 0x01) */ -#define PORT1_PPS_PPS13_Pos \ - (13UL) /*!< PORT1 PPS: PPS13 (Bit 13) */ -#define PORT1_PPS_PPS13_Msk \ - (0x2000UL) /*!< PORT1 PPS: PPS13 (Bitfield-Mask: 0x01) */ -#define PORT1_PPS_PPS14_Pos \ - (14UL) /*!< PORT1 PPS: PPS14 (Bit 14) */ -#define PORT1_PPS_PPS14_Msk \ - (0x4000UL) /*!< PORT1 PPS: PPS14 (Bitfield-Mask: 0x01) */ -#define PORT1_PPS_PPS15_Pos \ - (15UL) /*!< PORT1 PPS: PPS15 (Bit 15) */ -#define PORT1_PPS_PPS15_Msk \ - (0x8000UL) /*!< PORT1 PPS: PPS15 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- PORT1_HWSEL -------------------------------- */ -#define PORT1_HWSEL_HW0_Pos \ - (0UL) /*!< PORT1 HWSEL: HW0 (Bit 0) */ -#define PORT1_HWSEL_HW0_Msk \ - (0x3UL) /*!< PORT1 HWSEL: HW0 (Bitfield-Mask: 0x03) */ -#define PORT1_HWSEL_HW1_Pos \ - (2UL) /*!< PORT1 HWSEL: HW1 (Bit 2) */ -#define PORT1_HWSEL_HW1_Msk \ - (0xcUL) /*!< PORT1 HWSEL: HW1 (Bitfield-Mask: 0x03) */ -#define PORT1_HWSEL_HW2_Pos \ - (4UL) /*!< PORT1 HWSEL: HW2 (Bit 4) */ -#define PORT1_HWSEL_HW2_Msk \ - (0x30UL) /*!< PORT1 HWSEL: HW2 (Bitfield-Mask: 0x03) */ -#define PORT1_HWSEL_HW3_Pos \ - (6UL) /*!< PORT1 HWSEL: HW3 (Bit 6) */ -#define PORT1_HWSEL_HW3_Msk \ - (0xc0UL) /*!< PORT1 HWSEL: HW3 (Bitfield-Mask: 0x03) */ -#define PORT1_HWSEL_HW4_Pos \ - (8UL) /*!< PORT1 HWSEL: HW4 (Bit 8) */ -#define PORT1_HWSEL_HW4_Msk \ - (0x300UL) /*!< PORT1 HWSEL: HW4 (Bitfield-Mask: 0x03) */ -#define PORT1_HWSEL_HW5_Pos \ - (10UL) /*!< PORT1 HWSEL: HW5 (Bit 10) */ -#define PORT1_HWSEL_HW5_Msk \ - (0xc00UL) /*!< PORT1 HWSEL: HW5 (Bitfield-Mask: 0x03) */ -#define PORT1_HWSEL_HW6_Pos \ - (12UL) /*!< PORT1 HWSEL: HW6 (Bit 12) */ -#define PORT1_HWSEL_HW6_Msk \ - (0x3000UL) /*!< PORT1 HWSEL: HW6 (Bitfield-Mask: 0x03) */ -#define PORT1_HWSEL_HW7_Pos \ - (14UL) /*!< PORT1 HWSEL: HW7 (Bit 14) */ -#define PORT1_HWSEL_HW7_Msk \ - (0xc000UL) /*!< PORT1 HWSEL: HW7 (Bitfield-Mask: 0x03) */ -#define PORT1_HWSEL_HW8_Pos \ - (16UL) /*!< PORT1 HWSEL: HW8 (Bit 16) */ -#define PORT1_HWSEL_HW8_Msk \ - (0x30000UL) /*!< PORT1 HWSEL: HW8 (Bitfield-Mask: 0x03) */ -#define PORT1_HWSEL_HW9_Pos \ - (18UL) /*!< PORT1 HWSEL: HW9 (Bit 18) */ -#define PORT1_HWSEL_HW9_Msk \ - (0xc0000UL) /*!< PORT1 HWSEL: HW9 (Bitfield-Mask: 0x03) */ -#define PORT1_HWSEL_HW10_Pos \ - (20UL) /*!< PORT1 HWSEL: HW10 (Bit 20) */ -#define PORT1_HWSEL_HW10_Msk \ - (0x300000UL) /*!< PORT1 HWSEL: HW10 (Bitfield-Mask: 0x03) */ -#define PORT1_HWSEL_HW11_Pos \ - (22UL) /*!< PORT1 HWSEL: HW11 (Bit 22) */ -#define PORT1_HWSEL_HW11_Msk \ - (0xc00000UL) /*!< PORT1 HWSEL: HW11 (Bitfield-Mask: 0x03) */ -#define PORT1_HWSEL_HW12_Pos \ - (24UL) /*!< PORT1 HWSEL: HW12 (Bit 24) */ -#define PORT1_HWSEL_HW12_Msk \ - (0x3000000UL) /*!< PORT1 HWSEL: HW12 (Bitfield-Mask: 0x03) */ -#define PORT1_HWSEL_HW13_Pos \ - (26UL) /*!< PORT1 HWSEL: HW13 (Bit 26) */ -#define PORT1_HWSEL_HW13_Msk \ - (0xc000000UL) /*!< PORT1 HWSEL: HW13 (Bitfield-Mask: 0x03) */ -#define PORT1_HWSEL_HW14_Pos \ - (28UL) /*!< PORT1 HWSEL: HW14 (Bit 28) */ -#define PORT1_HWSEL_HW14_Msk \ - (0x30000000UL) /*!< PORT1 HWSEL: HW14 (Bitfield-Mask: 0x03) */ -#define PORT1_HWSEL_HW15_Pos \ - (30UL) /*!< PORT1 HWSEL: HW15 (Bit 30) */ -#define PORT1_HWSEL_HW15_Msk \ - (0xc0000000UL) /*!< PORT1 HWSEL: HW15 (Bitfield-Mask: 0x03) */ - -/* ================================================================================ */ -/* ================ struct 'PORT2' Position & Mask ================ */ -/* ================================================================================ */ - -/* ---------------------------------- PORT2_OUT --------------------------------- */ -#define PORT2_OUT_P0_Pos (0UL) /*!< PORT2 OUT: P0 (Bit 0) */ -#define PORT2_OUT_P0_Msk (0x1UL) /*!< PORT2 OUT: P0 (Bitfield-Mask: 0x01) */ -#define PORT2_OUT_P1_Pos (1UL) /*!< PORT2 OUT: P1 (Bit 1) */ -#define PORT2_OUT_P1_Msk (0x2UL) /*!< PORT2 OUT: P1 (Bitfield-Mask: 0x01) */ -#define PORT2_OUT_P2_Pos (2UL) /*!< PORT2 OUT: P2 (Bit 2) */ -#define PORT2_OUT_P2_Msk (0x4UL) /*!< PORT2 OUT: P2 (Bitfield-Mask: 0x01) */ -#define PORT2_OUT_P3_Pos (3UL) /*!< PORT2 OUT: P3 (Bit 3) */ -#define PORT2_OUT_P3_Msk (0x8UL) /*!< PORT2 OUT: P3 (Bitfield-Mask: 0x01) */ -#define PORT2_OUT_P4_Pos (4UL) /*!< PORT2 OUT: P4 (Bit 4) */ -#define PORT2_OUT_P4_Msk \ - (0x10UL) /*!< PORT2 OUT: P4 (Bitfield-Mask: 0x01) */ -#define PORT2_OUT_P5_Pos (5UL) /*!< PORT2 OUT: P5 (Bit 5) */ -#define PORT2_OUT_P5_Msk \ - (0x20UL) /*!< PORT2 OUT: P5 (Bitfield-Mask: 0x01) */ -#define PORT2_OUT_P6_Pos (6UL) /*!< PORT2 OUT: P6 (Bit 6) */ -#define PORT2_OUT_P6_Msk \ - (0x40UL) /*!< PORT2 OUT: P6 (Bitfield-Mask: 0x01) */ -#define PORT2_OUT_P7_Pos (7UL) /*!< PORT2 OUT: P7 (Bit 7) */ -#define PORT2_OUT_P7_Msk \ - (0x80UL) /*!< PORT2 OUT: P7 (Bitfield-Mask: 0x01) */ -#define PORT2_OUT_P8_Pos (8UL) /*!< PORT2 OUT: P8 (Bit 8) */ -#define PORT2_OUT_P8_Msk \ - (0x100UL) /*!< PORT2 OUT: P8 (Bitfield-Mask: 0x01) */ -#define PORT2_OUT_P9_Pos (9UL) /*!< PORT2 OUT: P9 (Bit 9) */ -#define PORT2_OUT_P9_Msk \ - (0x200UL) /*!< PORT2 OUT: P9 (Bitfield-Mask: 0x01) */ -#define PORT2_OUT_P10_Pos (10UL) /*!< PORT2 OUT: P10 (Bit 10) */ -#define PORT2_OUT_P10_Msk \ - (0x400UL) /*!< PORT2 OUT: P10 (Bitfield-Mask: 0x01) */ -#define PORT2_OUT_P11_Pos (11UL) /*!< PORT2 OUT: P11 (Bit 11) */ -#define PORT2_OUT_P11_Msk \ - (0x800UL) /*!< PORT2 OUT: P11 (Bitfield-Mask: 0x01) */ -#define PORT2_OUT_P12_Pos (12UL) /*!< PORT2 OUT: P12 (Bit 12) */ -#define PORT2_OUT_P12_Msk \ - (0x1000UL) /*!< PORT2 OUT: P12 (Bitfield-Mask: 0x01) */ -#define PORT2_OUT_P13_Pos (13UL) /*!< PORT2 OUT: P13 (Bit 13) */ -#define PORT2_OUT_P13_Msk \ - (0x2000UL) /*!< PORT2 OUT: P13 (Bitfield-Mask: 0x01) */ -#define PORT2_OUT_P14_Pos (14UL) /*!< PORT2 OUT: P14 (Bit 14) */ -#define PORT2_OUT_P14_Msk \ - (0x4000UL) /*!< PORT2 OUT: P14 (Bitfield-Mask: 0x01) */ -#define PORT2_OUT_P15_Pos (15UL) /*!< PORT2 OUT: P15 (Bit 15) */ -#define PORT2_OUT_P15_Msk \ - (0x8000UL) /*!< PORT2 OUT: P15 (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- PORT2_OMR --------------------------------- */ -#define PORT2_OMR_PS0_Pos (0UL) /*!< PORT2 OMR: PS0 (Bit 0) */ -#define PORT2_OMR_PS0_Msk \ - (0x1UL) /*!< PORT2 OMR: PS0 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PS1_Pos (1UL) /*!< PORT2 OMR: PS1 (Bit 1) */ -#define PORT2_OMR_PS1_Msk \ - (0x2UL) /*!< PORT2 OMR: PS1 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PS2_Pos (2UL) /*!< PORT2 OMR: PS2 (Bit 2) */ -#define PORT2_OMR_PS2_Msk \ - (0x4UL) /*!< PORT2 OMR: PS2 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PS3_Pos (3UL) /*!< PORT2 OMR: PS3 (Bit 3) */ -#define PORT2_OMR_PS3_Msk \ - (0x8UL) /*!< PORT2 OMR: PS3 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PS4_Pos (4UL) /*!< PORT2 OMR: PS4 (Bit 4) */ -#define PORT2_OMR_PS4_Msk \ - (0x10UL) /*!< PORT2 OMR: PS4 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PS5_Pos (5UL) /*!< PORT2 OMR: PS5 (Bit 5) */ -#define PORT2_OMR_PS5_Msk \ - (0x20UL) /*!< PORT2 OMR: PS5 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PS6_Pos (6UL) /*!< PORT2 OMR: PS6 (Bit 6) */ -#define PORT2_OMR_PS6_Msk \ - (0x40UL) /*!< PORT2 OMR: PS6 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PS7_Pos (7UL) /*!< PORT2 OMR: PS7 (Bit 7) */ -#define PORT2_OMR_PS7_Msk \ - (0x80UL) /*!< PORT2 OMR: PS7 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PS8_Pos (8UL) /*!< PORT2 OMR: PS8 (Bit 8) */ -#define PORT2_OMR_PS8_Msk \ - (0x100UL) /*!< PORT2 OMR: PS8 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PS9_Pos (9UL) /*!< PORT2 OMR: PS9 (Bit 9) */ -#define PORT2_OMR_PS9_Msk \ - (0x200UL) /*!< PORT2 OMR: PS9 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PS10_Pos \ - (10UL) /*!< PORT2 OMR: PS10 (Bit 10) */ -#define PORT2_OMR_PS10_Msk \ - (0x400UL) /*!< PORT2 OMR: PS10 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PS11_Pos \ - (11UL) /*!< PORT2 OMR: PS11 (Bit 11) */ -#define PORT2_OMR_PS11_Msk \ - (0x800UL) /*!< PORT2 OMR: PS11 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PS12_Pos \ - (12UL) /*!< PORT2 OMR: PS12 (Bit 12) */ -#define PORT2_OMR_PS12_Msk \ - (0x1000UL) /*!< PORT2 OMR: PS12 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PS13_Pos \ - (13UL) /*!< PORT2 OMR: PS13 (Bit 13) */ -#define PORT2_OMR_PS13_Msk \ - (0x2000UL) /*!< PORT2 OMR: PS13 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PS14_Pos \ - (14UL) /*!< PORT2 OMR: PS14 (Bit 14) */ -#define PORT2_OMR_PS14_Msk \ - (0x4000UL) /*!< PORT2 OMR: PS14 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PS15_Pos \ - (15UL) /*!< PORT2 OMR: PS15 (Bit 15) */ -#define PORT2_OMR_PS15_Msk \ - (0x8000UL) /*!< PORT2 OMR: PS15 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PR0_Pos (16UL) /*!< PORT2 OMR: PR0 (Bit 16) */ -#define PORT2_OMR_PR0_Msk \ - (0x10000UL) /*!< PORT2 OMR: PR0 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PR1_Pos (17UL) /*!< PORT2 OMR: PR1 (Bit 17) */ -#define PORT2_OMR_PR1_Msk \ - (0x20000UL) /*!< PORT2 OMR: PR1 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PR2_Pos (18UL) /*!< PORT2 OMR: PR2 (Bit 18) */ -#define PORT2_OMR_PR2_Msk \ - (0x40000UL) /*!< PORT2 OMR: PR2 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PR3_Pos (19UL) /*!< PORT2 OMR: PR3 (Bit 19) */ -#define PORT2_OMR_PR3_Msk \ - (0x80000UL) /*!< PORT2 OMR: PR3 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PR4_Pos (20UL) /*!< PORT2 OMR: PR4 (Bit 20) */ -#define PORT2_OMR_PR4_Msk \ - (0x100000UL) /*!< PORT2 OMR: PR4 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PR5_Pos (21UL) /*!< PORT2 OMR: PR5 (Bit 21) */ -#define PORT2_OMR_PR5_Msk \ - (0x200000UL) /*!< PORT2 OMR: PR5 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PR6_Pos (22UL) /*!< PORT2 OMR: PR6 (Bit 22) */ -#define PORT2_OMR_PR6_Msk \ - (0x400000UL) /*!< PORT2 OMR: PR6 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PR7_Pos (23UL) /*!< PORT2 OMR: PR7 (Bit 23) */ -#define PORT2_OMR_PR7_Msk \ - (0x800000UL) /*!< PORT2 OMR: PR7 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PR8_Pos (24UL) /*!< PORT2 OMR: PR8 (Bit 24) */ -#define PORT2_OMR_PR8_Msk \ - (0x1000000UL) /*!< PORT2 OMR: PR8 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PR9_Pos (25UL) /*!< PORT2 OMR: PR9 (Bit 25) */ -#define PORT2_OMR_PR9_Msk \ - (0x2000000UL) /*!< PORT2 OMR: PR9 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PR10_Pos \ - (26UL) /*!< PORT2 OMR: PR10 (Bit 26) */ -#define PORT2_OMR_PR10_Msk \ - (0x4000000UL) /*!< PORT2 OMR: PR10 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PR11_Pos \ - (27UL) /*!< PORT2 OMR: PR11 (Bit 27) */ -#define PORT2_OMR_PR11_Msk \ - (0x8000000UL) /*!< PORT2 OMR: PR11 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PR12_Pos \ - (28UL) /*!< PORT2 OMR: PR12 (Bit 28) */ -#define PORT2_OMR_PR12_Msk \ - (0x10000000UL) /*!< PORT2 OMR: PR12 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PR13_Pos \ - (29UL) /*!< PORT2 OMR: PR13 (Bit 29) */ -#define PORT2_OMR_PR13_Msk \ - (0x20000000UL) /*!< PORT2 OMR: PR13 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PR14_Pos \ - (30UL) /*!< PORT2 OMR: PR14 (Bit 30) */ -#define PORT2_OMR_PR14_Msk \ - (0x40000000UL) /*!< PORT2 OMR: PR14 (Bitfield-Mask: 0x01) */ -#define PORT2_OMR_PR15_Pos \ - (31UL) /*!< PORT2 OMR: PR15 (Bit 31) */ -#define PORT2_OMR_PR15_Msk \ - (0x80000000UL) /*!< PORT2 OMR: PR15 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- PORT2_IOCR0 -------------------------------- */ -#define PORT2_IOCR0_PC0_Pos \ - (3UL) /*!< PORT2 IOCR0: PC0 (Bit 3) */ -#define PORT2_IOCR0_PC0_Msk \ - (0xf8UL) /*!< PORT2 IOCR0: PC0 (Bitfield-Mask: 0x1f) */ -#define PORT2_IOCR0_PC1_Pos \ - (11UL) /*!< PORT2 IOCR0: PC1 (Bit 11) */ -#define PORT2_IOCR0_PC1_Msk \ - (0xf800UL) /*!< PORT2 IOCR0: PC1 (Bitfield-Mask: 0x1f) */ -#define PORT2_IOCR0_PC2_Pos \ - (19UL) /*!< PORT2 IOCR0: PC2 (Bit 19) */ -#define PORT2_IOCR0_PC2_Msk \ - (0xf80000UL) /*!< PORT2 IOCR0: PC2 (Bitfield-Mask: 0x1f) */ -#define PORT2_IOCR0_PC3_Pos \ - (27UL) /*!< PORT2 IOCR0: PC3 (Bit 27) */ -#define PORT2_IOCR0_PC3_Msk \ - (0xf8000000UL) /*!< PORT2 IOCR0: PC3 (Bitfield-Mask: 0x1f) */ - -/* --------------------------------- PORT2_IOCR4 -------------------------------- */ -#define PORT2_IOCR4_PC4_Pos \ - (3UL) /*!< PORT2 IOCR4: PC4 (Bit 3) */ -#define PORT2_IOCR4_PC4_Msk \ - (0xf8UL) /*!< PORT2 IOCR4: PC4 (Bitfield-Mask: 0x1f) */ -#define PORT2_IOCR4_PC5_Pos \ - (11UL) /*!< PORT2 IOCR4: PC5 (Bit 11) */ -#define PORT2_IOCR4_PC5_Msk \ - (0xf800UL) /*!< PORT2 IOCR4: PC5 (Bitfield-Mask: 0x1f) */ -#define PORT2_IOCR4_PC6_Pos \ - (19UL) /*!< PORT2 IOCR4: PC6 (Bit 19) */ -#define PORT2_IOCR4_PC6_Msk \ - (0xf80000UL) /*!< PORT2 IOCR4: PC6 (Bitfield-Mask: 0x1f) */ -#define PORT2_IOCR4_PC7_Pos \ - (27UL) /*!< PORT2 IOCR4: PC7 (Bit 27) */ -#define PORT2_IOCR4_PC7_Msk \ - (0xf8000000UL) /*!< PORT2 IOCR4: PC7 (Bitfield-Mask: 0x1f) */ - -/* --------------------------------- PORT2_IOCR8 -------------------------------- */ -#define PORT2_IOCR8_PC8_Pos \ - (3UL) /*!< PORT2 IOCR8: PC8 (Bit 3) */ -#define PORT2_IOCR8_PC8_Msk \ - (0xf8UL) /*!< PORT2 IOCR8: PC8 (Bitfield-Mask: 0x1f) */ -#define PORT2_IOCR8_PC9_Pos \ - (11UL) /*!< PORT2 IOCR8: PC9 (Bit 11) */ -#define PORT2_IOCR8_PC9_Msk \ - (0xf800UL) /*!< PORT2 IOCR8: PC9 (Bitfield-Mask: 0x1f) */ -#define PORT2_IOCR8_PC10_Pos \ - (19UL) /*!< PORT2 IOCR8: PC10 (Bit 19) */ -#define PORT2_IOCR8_PC10_Msk \ - (0xf80000UL) /*!< PORT2 IOCR8: PC10 (Bitfield-Mask: 0x1f) */ -#define PORT2_IOCR8_PC11_Pos \ - (27UL) /*!< PORT2 IOCR8: PC11 (Bit 27) */ -#define PORT2_IOCR8_PC11_Msk \ - (0xf8000000UL) /*!< PORT2 IOCR8: PC11 (Bitfield-Mask: 0x1f) */ - -/* -------------------------------- PORT2_IOCR12 -------------------------------- */ -#define PORT2_IOCR12_PC12_Pos \ - (3UL) /*!< PORT2 IOCR12: PC12 (Bit 3) */ -#define PORT2_IOCR12_PC12_Msk \ - (0xf8UL) /*!< PORT2 IOCR12: PC12 (Bitfield-Mask: 0x1f) */ -#define PORT2_IOCR12_PC13_Pos \ - (11UL) /*!< PORT2 IOCR12: PC13 (Bit 11) */ -#define PORT2_IOCR12_PC13_Msk \ - (0xf800UL) /*!< PORT2 IOCR12: PC13 (Bitfield-Mask: 0x1f) */ -#define PORT2_IOCR12_PC14_Pos \ - (19UL) /*!< PORT2 IOCR12: PC14 (Bit 19) */ -#define PORT2_IOCR12_PC14_Msk \ - (0xf80000UL) /*!< PORT2 IOCR12: PC14 (Bitfield-Mask: 0x1f) */ -#define PORT2_IOCR12_PC15_Pos \ - (27UL) /*!< PORT2 IOCR12: PC15 (Bit 27) */ -#define PORT2_IOCR12_PC15_Msk \ - (0xf8000000UL) /*!< PORT2 IOCR12: PC15 (Bitfield-Mask: 0x1f) */ - -/* ---------------------------------- PORT2_IN ---------------------------------- */ -#define PORT2_IN_P0_Pos (0UL) /*!< PORT2 IN: P0 (Bit 0) */ -#define PORT2_IN_P0_Msk (0x1UL) /*!< PORT2 IN: P0 (Bitfield-Mask: 0x01) */ -#define PORT2_IN_P1_Pos (1UL) /*!< PORT2 IN: P1 (Bit 1) */ -#define PORT2_IN_P1_Msk (0x2UL) /*!< PORT2 IN: P1 (Bitfield-Mask: 0x01) */ -#define PORT2_IN_P2_Pos (2UL) /*!< PORT2 IN: P2 (Bit 2) */ -#define PORT2_IN_P2_Msk (0x4UL) /*!< PORT2 IN: P2 (Bitfield-Mask: 0x01) */ -#define PORT2_IN_P3_Pos (3UL) /*!< PORT2 IN: P3 (Bit 3) */ -#define PORT2_IN_P3_Msk (0x8UL) /*!< PORT2 IN: P3 (Bitfield-Mask: 0x01) */ -#define PORT2_IN_P4_Pos (4UL) /*!< PORT2 IN: P4 (Bit 4) */ -#define PORT2_IN_P4_Msk (0x10UL) /*!< PORT2 IN: P4 (Bitfield-Mask: 0x01) */ -#define PORT2_IN_P5_Pos (5UL) /*!< PORT2 IN: P5 (Bit 5) */ -#define PORT2_IN_P5_Msk (0x20UL) /*!< PORT2 IN: P5 (Bitfield-Mask: 0x01) */ -#define PORT2_IN_P6_Pos (6UL) /*!< PORT2 IN: P6 (Bit 6) */ -#define PORT2_IN_P6_Msk (0x40UL) /*!< PORT2 IN: P6 (Bitfield-Mask: 0x01) */ -#define PORT2_IN_P7_Pos (7UL) /*!< PORT2 IN: P7 (Bit 7) */ -#define PORT2_IN_P7_Msk (0x80UL) /*!< PORT2 IN: P7 (Bitfield-Mask: 0x01) */ -#define PORT2_IN_P8_Pos (8UL) /*!< PORT2 IN: P8 (Bit 8) */ -#define PORT2_IN_P8_Msk \ - (0x100UL) /*!< PORT2 IN: P8 (Bitfield-Mask: 0x01) */ -#define PORT2_IN_P9_Pos (9UL) /*!< PORT2 IN: P9 (Bit 9) */ -#define PORT2_IN_P9_Msk \ - (0x200UL) /*!< PORT2 IN: P9 (Bitfield-Mask: 0x01) */ -#define PORT2_IN_P10_Pos (10UL) /*!< PORT2 IN: P10 (Bit 10) */ -#define PORT2_IN_P10_Msk \ - (0x400UL) /*!< PORT2 IN: P10 (Bitfield-Mask: 0x01) */ -#define PORT2_IN_P11_Pos (11UL) /*!< PORT2 IN: P11 (Bit 11) */ -#define PORT2_IN_P11_Msk \ - (0x800UL) /*!< PORT2 IN: P11 (Bitfield-Mask: 0x01) */ -#define PORT2_IN_P12_Pos (12UL) /*!< PORT2 IN: P12 (Bit 12) */ -#define PORT2_IN_P12_Msk \ - (0x1000UL) /*!< PORT2 IN: P12 (Bitfield-Mask: 0x01) */ -#define PORT2_IN_P13_Pos (13UL) /*!< PORT2 IN: P13 (Bit 13) */ -#define PORT2_IN_P13_Msk \ - (0x2000UL) /*!< PORT2 IN: P13 (Bitfield-Mask: 0x01) */ -#define PORT2_IN_P14_Pos (14UL) /*!< PORT2 IN: P14 (Bit 14) */ -#define PORT2_IN_P14_Msk \ - (0x4000UL) /*!< PORT2 IN: P14 (Bitfield-Mask: 0x01) */ -#define PORT2_IN_P15_Pos (15UL) /*!< PORT2 IN: P15 (Bit 15) */ -#define PORT2_IN_P15_Msk \ - (0x8000UL) /*!< PORT2 IN: P15 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- PORT2_PDR0 --------------------------------- */ -#define PORT2_PDR0_PD0_Pos (0UL) /*!< PORT2 PDR0: PD0 (Bit 0) */ -#define PORT2_PDR0_PD0_Msk \ - (0x7UL) /*!< PORT2 PDR0: PD0 (Bitfield-Mask: 0x07) */ -#define PORT2_PDR0_PD1_Pos (4UL) /*!< PORT2 PDR0: PD1 (Bit 4) */ -#define PORT2_PDR0_PD1_Msk \ - (0x70UL) /*!< PORT2 PDR0: PD1 (Bitfield-Mask: 0x07) */ -#define PORT2_PDR0_PD2_Pos (8UL) /*!< PORT2 PDR0: PD2 (Bit 8) */ -#define PORT2_PDR0_PD2_Msk \ - (0x700UL) /*!< PORT2 PDR0: PD2 (Bitfield-Mask: 0x07) */ -#define PORT2_PDR0_PD3_Pos \ - (12UL) /*!< PORT2 PDR0: PD3 (Bit 12) */ -#define PORT2_PDR0_PD3_Msk \ - (0x7000UL) /*!< PORT2 PDR0: PD3 (Bitfield-Mask: 0x07) */ -#define PORT2_PDR0_PD4_Pos \ - (16UL) /*!< PORT2 PDR0: PD4 (Bit 16) */ -#define PORT2_PDR0_PD4_Msk \ - (0x70000UL) /*!< PORT2 PDR0: PD4 (Bitfield-Mask: 0x07) */ -#define PORT2_PDR0_PD5_Pos \ - (20UL) /*!< PORT2 PDR0: PD5 (Bit 20) */ -#define PORT2_PDR0_PD5_Msk \ - (0x700000UL) /*!< PORT2 PDR0: PD5 (Bitfield-Mask: 0x07) */ -#define PORT2_PDR0_PD6_Pos \ - (24UL) /*!< PORT2 PDR0: PD6 (Bit 24) */ -#define PORT2_PDR0_PD6_Msk \ - (0x7000000UL) /*!< PORT2 PDR0: PD6 (Bitfield-Mask: 0x07) */ -#define PORT2_PDR0_PD7_Pos \ - (28UL) /*!< PORT2 PDR0: PD7 (Bit 28) */ -#define PORT2_PDR0_PD7_Msk \ - (0x70000000UL) /*!< PORT2 PDR0: PD7 (Bitfield-Mask: 0x07) */ - -/* --------------------------------- PORT2_PDR1 --------------------------------- */ -#define PORT2_PDR1_PD8_Pos (0UL) /*!< PORT2 PDR1: PD8 (Bit 0) */ -#define PORT2_PDR1_PD8_Msk \ - (0x7UL) /*!< PORT2 PDR1: PD8 (Bitfield-Mask: 0x07) */ -#define PORT2_PDR1_PD9_Pos (4UL) /*!< PORT2 PDR1: PD9 (Bit 4) */ -#define PORT2_PDR1_PD9_Msk \ - (0x70UL) /*!< PORT2 PDR1: PD9 (Bitfield-Mask: 0x07) */ -#define PORT2_PDR1_PD10_Pos \ - (8UL) /*!< PORT2 PDR1: PD10 (Bit 8) */ -#define PORT2_PDR1_PD10_Msk \ - (0x700UL) /*!< PORT2 PDR1: PD10 (Bitfield-Mask: 0x07) */ -#define PORT2_PDR1_PD11_Pos \ - (12UL) /*!< PORT2 PDR1: PD11 (Bit 12) */ -#define PORT2_PDR1_PD11_Msk \ - (0x7000UL) /*!< PORT2 PDR1: PD11 (Bitfield-Mask: 0x07) */ -#define PORT2_PDR1_PD12_Pos \ - (16UL) /*!< PORT2 PDR1: PD12 (Bit 16) */ -#define PORT2_PDR1_PD12_Msk \ - (0x70000UL) /*!< PORT2 PDR1: PD12 (Bitfield-Mask: 0x07) */ -#define PORT2_PDR1_PD13_Pos \ - (20UL) /*!< PORT2 PDR1: PD13 (Bit 20) */ -#define PORT2_PDR1_PD13_Msk \ - (0x700000UL) /*!< PORT2 PDR1: PD13 (Bitfield-Mask: 0x07) */ -#define PORT2_PDR1_PD14_Pos \ - (24UL) /*!< PORT2 PDR1: PD14 (Bit 24) */ -#define PORT2_PDR1_PD14_Msk \ - (0x7000000UL) /*!< PORT2 PDR1: PD14 (Bitfield-Mask: 0x07) */ -#define PORT2_PDR1_PD15_Pos \ - (28UL) /*!< PORT2 PDR1: PD15 (Bit 28) */ -#define PORT2_PDR1_PD15_Msk \ - (0x70000000UL) /*!< PORT2 PDR1: PD15 (Bitfield-Mask: 0x07) */ - -/* --------------------------------- PORT2_PDISC -------------------------------- */ -#define PORT2_PDISC_PDIS0_Pos \ - (0UL) /*!< PORT2 PDISC: PDIS0 (Bit 0) */ -#define PORT2_PDISC_PDIS0_Msk \ - (0x1UL) /*!< PORT2 PDISC: PDIS0 (Bitfield-Mask: 0x01) */ -#define PORT2_PDISC_PDIS1_Pos \ - (1UL) /*!< PORT2 PDISC: PDIS1 (Bit 1) */ -#define PORT2_PDISC_PDIS1_Msk \ - (0x2UL) /*!< PORT2 PDISC: PDIS1 (Bitfield-Mask: 0x01) */ -#define PORT2_PDISC_PDIS2_Pos \ - (2UL) /*!< PORT2 PDISC: PDIS2 (Bit 2) */ -#define PORT2_PDISC_PDIS2_Msk \ - (0x4UL) /*!< PORT2 PDISC: PDIS2 (Bitfield-Mask: 0x01) */ -#define PORT2_PDISC_PDIS3_Pos \ - (3UL) /*!< PORT2 PDISC: PDIS3 (Bit 3) */ -#define PORT2_PDISC_PDIS3_Msk \ - (0x8UL) /*!< PORT2 PDISC: PDIS3 (Bitfield-Mask: 0x01) */ -#define PORT2_PDISC_PDIS4_Pos \ - (4UL) /*!< PORT2 PDISC: PDIS4 (Bit 4) */ -#define PORT2_PDISC_PDIS4_Msk \ - (0x10UL) /*!< PORT2 PDISC: PDIS4 (Bitfield-Mask: 0x01) */ -#define PORT2_PDISC_PDIS5_Pos \ - (5UL) /*!< PORT2 PDISC: PDIS5 (Bit 5) */ -#define PORT2_PDISC_PDIS5_Msk \ - (0x20UL) /*!< PORT2 PDISC: PDIS5 (Bitfield-Mask: 0x01) */ -#define PORT2_PDISC_PDIS6_Pos \ - (6UL) /*!< PORT2 PDISC: PDIS6 (Bit 6) */ -#define PORT2_PDISC_PDIS6_Msk \ - (0x40UL) /*!< PORT2 PDISC: PDIS6 (Bitfield-Mask: 0x01) */ -#define PORT2_PDISC_PDIS7_Pos \ - (7UL) /*!< PORT2 PDISC: PDIS7 (Bit 7) */ -#define PORT2_PDISC_PDIS7_Msk \ - (0x80UL) /*!< PORT2 PDISC: PDIS7 (Bitfield-Mask: 0x01) */ -#define PORT2_PDISC_PDIS8_Pos \ - (8UL) /*!< PORT2 PDISC: PDIS8 (Bit 8) */ -#define PORT2_PDISC_PDIS8_Msk \ - (0x100UL) /*!< PORT2 PDISC: PDIS8 (Bitfield-Mask: 0x01) */ -#define PORT2_PDISC_PDIS9_Pos \ - (9UL) /*!< PORT2 PDISC: PDIS9 (Bit 9) */ -#define PORT2_PDISC_PDIS9_Msk \ - (0x200UL) /*!< PORT2 PDISC: PDIS9 (Bitfield-Mask: 0x01) */ -#define PORT2_PDISC_PDIS10_Pos \ - (10UL) /*!< PORT2 PDISC: PDIS10 (Bit 10) */ -#define PORT2_PDISC_PDIS10_Msk \ - (0x400UL) /*!< PORT2 PDISC: PDIS10 (Bitfield-Mask: 0x01) */ -#define PORT2_PDISC_PDIS11_Pos \ - (11UL) /*!< PORT2 PDISC: PDIS11 (Bit 11) */ -#define PORT2_PDISC_PDIS11_Msk \ - (0x800UL) /*!< PORT2 PDISC: PDIS11 (Bitfield-Mask: 0x01) */ -#define PORT2_PDISC_PDIS12_Pos \ - (12UL) /*!< PORT2 PDISC: PDIS12 (Bit 12) */ -#define PORT2_PDISC_PDIS12_Msk \ - (0x1000UL) /*!< PORT2 PDISC: PDIS12 (Bitfield-Mask: 0x01) */ -#define PORT2_PDISC_PDIS13_Pos \ - (13UL) /*!< PORT2 PDISC: PDIS13 (Bit 13) */ -#define PORT2_PDISC_PDIS13_Msk \ - (0x2000UL) /*!< PORT2 PDISC: PDIS13 (Bitfield-Mask: 0x01) */ -#define PORT2_PDISC_PDIS14_Pos \ - (14UL) /*!< PORT2 PDISC: PDIS14 (Bit 14) */ -#define PORT2_PDISC_PDIS14_Msk \ - (0x4000UL) /*!< PORT2 PDISC: PDIS14 (Bitfield-Mask: 0x01) */ -#define PORT2_PDISC_PDIS15_Pos \ - (15UL) /*!< PORT2 PDISC: PDIS15 (Bit 15) */ -#define PORT2_PDISC_PDIS15_Msk \ - (0x8000UL) /*!< PORT2 PDISC: PDIS15 (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- PORT2_PPS --------------------------------- */ -#define PORT2_PPS_PPS0_Pos (0UL) /*!< PORT2 PPS: PPS0 (Bit 0) */ -#define PORT2_PPS_PPS0_Msk \ - (0x1UL) /*!< PORT2 PPS: PPS0 (Bitfield-Mask: 0x01) */ -#define PORT2_PPS_PPS1_Pos (1UL) /*!< PORT2 PPS: PPS1 (Bit 1) */ -#define PORT2_PPS_PPS1_Msk \ - (0x2UL) /*!< PORT2 PPS: PPS1 (Bitfield-Mask: 0x01) */ -#define PORT2_PPS_PPS2_Pos (2UL) /*!< PORT2 PPS: PPS2 (Bit 2) */ -#define PORT2_PPS_PPS2_Msk \ - (0x4UL) /*!< PORT2 PPS: PPS2 (Bitfield-Mask: 0x01) */ -#define PORT2_PPS_PPS3_Pos (3UL) /*!< PORT2 PPS: PPS3 (Bit 3) */ -#define PORT2_PPS_PPS3_Msk \ - (0x8UL) /*!< PORT2 PPS: PPS3 (Bitfield-Mask: 0x01) */ -#define PORT2_PPS_PPS4_Pos (4UL) /*!< PORT2 PPS: PPS4 (Bit 4) */ -#define PORT2_PPS_PPS4_Msk \ - (0x10UL) /*!< PORT2 PPS: PPS4 (Bitfield-Mask: 0x01) */ -#define PORT2_PPS_PPS5_Pos (5UL) /*!< PORT2 PPS: PPS5 (Bit 5) */ -#define PORT2_PPS_PPS5_Msk \ - (0x20UL) /*!< PORT2 PPS: PPS5 (Bitfield-Mask: 0x01) */ -#define PORT2_PPS_PPS6_Pos (6UL) /*!< PORT2 PPS: PPS6 (Bit 6) */ -#define PORT2_PPS_PPS6_Msk \ - (0x40UL) /*!< PORT2 PPS: PPS6 (Bitfield-Mask: 0x01) */ -#define PORT2_PPS_PPS7_Pos (7UL) /*!< PORT2 PPS: PPS7 (Bit 7) */ -#define PORT2_PPS_PPS7_Msk \ - (0x80UL) /*!< PORT2 PPS: PPS7 (Bitfield-Mask: 0x01) */ -#define PORT2_PPS_PPS8_Pos (8UL) /*!< PORT2 PPS: PPS8 (Bit 8) */ -#define PORT2_PPS_PPS8_Msk \ - (0x100UL) /*!< PORT2 PPS: PPS8 (Bitfield-Mask: 0x01) */ -#define PORT2_PPS_PPS9_Pos (9UL) /*!< PORT2 PPS: PPS9 (Bit 9) */ -#define PORT2_PPS_PPS9_Msk \ - (0x200UL) /*!< PORT2 PPS: PPS9 (Bitfield-Mask: 0x01) */ -#define PORT2_PPS_PPS10_Pos \ - (10UL) /*!< PORT2 PPS: PPS10 (Bit 10) */ -#define PORT2_PPS_PPS10_Msk \ - (0x400UL) /*!< PORT2 PPS: PPS10 (Bitfield-Mask: 0x01) */ -#define PORT2_PPS_PPS11_Pos \ - (11UL) /*!< PORT2 PPS: PPS11 (Bit 11) */ -#define PORT2_PPS_PPS11_Msk \ - (0x800UL) /*!< PORT2 PPS: PPS11 (Bitfield-Mask: 0x01) */ -#define PORT2_PPS_PPS12_Pos \ - (12UL) /*!< PORT2 PPS: PPS12 (Bit 12) */ -#define PORT2_PPS_PPS12_Msk \ - (0x1000UL) /*!< PORT2 PPS: PPS12 (Bitfield-Mask: 0x01) */ -#define PORT2_PPS_PPS13_Pos \ - (13UL) /*!< PORT2 PPS: PPS13 (Bit 13) */ -#define PORT2_PPS_PPS13_Msk \ - (0x2000UL) /*!< PORT2 PPS: PPS13 (Bitfield-Mask: 0x01) */ -#define PORT2_PPS_PPS14_Pos \ - (14UL) /*!< PORT2 PPS: PPS14 (Bit 14) */ -#define PORT2_PPS_PPS14_Msk \ - (0x4000UL) /*!< PORT2 PPS: PPS14 (Bitfield-Mask: 0x01) */ -#define PORT2_PPS_PPS15_Pos \ - (15UL) /*!< PORT2 PPS: PPS15 (Bit 15) */ -#define PORT2_PPS_PPS15_Msk \ - (0x8000UL) /*!< PORT2 PPS: PPS15 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- PORT2_HWSEL -------------------------------- */ -#define PORT2_HWSEL_HW0_Pos \ - (0UL) /*!< PORT2 HWSEL: HW0 (Bit 0) */ -#define PORT2_HWSEL_HW0_Msk \ - (0x3UL) /*!< PORT2 HWSEL: HW0 (Bitfield-Mask: 0x03) */ -#define PORT2_HWSEL_HW1_Pos \ - (2UL) /*!< PORT2 HWSEL: HW1 (Bit 2) */ -#define PORT2_HWSEL_HW1_Msk \ - (0xcUL) /*!< PORT2 HWSEL: HW1 (Bitfield-Mask: 0x03) */ -#define PORT2_HWSEL_HW2_Pos \ - (4UL) /*!< PORT2 HWSEL: HW2 (Bit 4) */ -#define PORT2_HWSEL_HW2_Msk \ - (0x30UL) /*!< PORT2 HWSEL: HW2 (Bitfield-Mask: 0x03) */ -#define PORT2_HWSEL_HW3_Pos \ - (6UL) /*!< PORT2 HWSEL: HW3 (Bit 6) */ -#define PORT2_HWSEL_HW3_Msk \ - (0xc0UL) /*!< PORT2 HWSEL: HW3 (Bitfield-Mask: 0x03) */ -#define PORT2_HWSEL_HW4_Pos \ - (8UL) /*!< PORT2 HWSEL: HW4 (Bit 8) */ -#define PORT2_HWSEL_HW4_Msk \ - (0x300UL) /*!< PORT2 HWSEL: HW4 (Bitfield-Mask: 0x03) */ -#define PORT2_HWSEL_HW5_Pos \ - (10UL) /*!< PORT2 HWSEL: HW5 (Bit 10) */ -#define PORT2_HWSEL_HW5_Msk \ - (0xc00UL) /*!< PORT2 HWSEL: HW5 (Bitfield-Mask: 0x03) */ -#define PORT2_HWSEL_HW6_Pos \ - (12UL) /*!< PORT2 HWSEL: HW6 (Bit 12) */ -#define PORT2_HWSEL_HW6_Msk \ - (0x3000UL) /*!< PORT2 HWSEL: HW6 (Bitfield-Mask: 0x03) */ -#define PORT2_HWSEL_HW7_Pos \ - (14UL) /*!< PORT2 HWSEL: HW7 (Bit 14) */ -#define PORT2_HWSEL_HW7_Msk \ - (0xc000UL) /*!< PORT2 HWSEL: HW7 (Bitfield-Mask: 0x03) */ -#define PORT2_HWSEL_HW8_Pos \ - (16UL) /*!< PORT2 HWSEL: HW8 (Bit 16) */ -#define PORT2_HWSEL_HW8_Msk \ - (0x30000UL) /*!< PORT2 HWSEL: HW8 (Bitfield-Mask: 0x03) */ -#define PORT2_HWSEL_HW9_Pos \ - (18UL) /*!< PORT2 HWSEL: HW9 (Bit 18) */ -#define PORT2_HWSEL_HW9_Msk \ - (0xc0000UL) /*!< PORT2 HWSEL: HW9 (Bitfield-Mask: 0x03) */ -#define PORT2_HWSEL_HW10_Pos \ - (20UL) /*!< PORT2 HWSEL: HW10 (Bit 20) */ -#define PORT2_HWSEL_HW10_Msk \ - (0x300000UL) /*!< PORT2 HWSEL: HW10 (Bitfield-Mask: 0x03) */ -#define PORT2_HWSEL_HW11_Pos \ - (22UL) /*!< PORT2 HWSEL: HW11 (Bit 22) */ -#define PORT2_HWSEL_HW11_Msk \ - (0xc00000UL) /*!< PORT2 HWSEL: HW11 (Bitfield-Mask: 0x03) */ -#define PORT2_HWSEL_HW12_Pos \ - (24UL) /*!< PORT2 HWSEL: HW12 (Bit 24) */ -#define PORT2_HWSEL_HW12_Msk \ - (0x3000000UL) /*!< PORT2 HWSEL: HW12 (Bitfield-Mask: 0x03) */ -#define PORT2_HWSEL_HW13_Pos \ - (26UL) /*!< PORT2 HWSEL: HW13 (Bit 26) */ -#define PORT2_HWSEL_HW13_Msk \ - (0xc000000UL) /*!< PORT2 HWSEL: HW13 (Bitfield-Mask: 0x03) */ -#define PORT2_HWSEL_HW14_Pos \ - (28UL) /*!< PORT2 HWSEL: HW14 (Bit 28) */ -#define PORT2_HWSEL_HW14_Msk \ - (0x30000000UL) /*!< PORT2 HWSEL: HW14 (Bitfield-Mask: 0x03) */ -#define PORT2_HWSEL_HW15_Pos \ - (30UL) /*!< PORT2 HWSEL: HW15 (Bit 30) */ -#define PORT2_HWSEL_HW15_Msk \ - (0xc0000000UL) /*!< PORT2 HWSEL: HW15 (Bitfield-Mask: 0x03) */ - -/* ================================================================================ */ -/* ================ struct 'PORT3' Position & Mask ================ */ -/* ================================================================================ */ - -/* ---------------------------------- PORT3_OUT --------------------------------- */ -#define PORT3_OUT_P0_Pos (0UL) /*!< PORT3 OUT: P0 (Bit 0) */ -#define PORT3_OUT_P0_Msk (0x1UL) /*!< PORT3 OUT: P0 (Bitfield-Mask: 0x01) */ -#define PORT3_OUT_P1_Pos (1UL) /*!< PORT3 OUT: P1 (Bit 1) */ -#define PORT3_OUT_P1_Msk (0x2UL) /*!< PORT3 OUT: P1 (Bitfield-Mask: 0x01) */ -#define PORT3_OUT_P2_Pos (2UL) /*!< PORT3 OUT: P2 (Bit 2) */ -#define PORT3_OUT_P2_Msk (0x4UL) /*!< PORT3 OUT: P2 (Bitfield-Mask: 0x01) */ -#define PORT3_OUT_P3_Pos (3UL) /*!< PORT3 OUT: P3 (Bit 3) */ -#define PORT3_OUT_P3_Msk (0x8UL) /*!< PORT3 OUT: P3 (Bitfield-Mask: 0x01) */ -#define PORT3_OUT_P4_Pos (4UL) /*!< PORT3 OUT: P4 (Bit 4) */ -#define PORT3_OUT_P4_Msk \ - (0x10UL) /*!< PORT3 OUT: P4 (Bitfield-Mask: 0x01) */ -#define PORT3_OUT_P5_Pos (5UL) /*!< PORT3 OUT: P5 (Bit 5) */ -#define PORT3_OUT_P5_Msk \ - (0x20UL) /*!< PORT3 OUT: P5 (Bitfield-Mask: 0x01) */ -#define PORT3_OUT_P6_Pos (6UL) /*!< PORT3 OUT: P6 (Bit 6) */ -#define PORT3_OUT_P6_Msk \ - (0x40UL) /*!< PORT3 OUT: P6 (Bitfield-Mask: 0x01) */ -#define PORT3_OUT_P7_Pos (7UL) /*!< PORT3 OUT: P7 (Bit 7) */ -#define PORT3_OUT_P7_Msk \ - (0x80UL) /*!< PORT3 OUT: P7 (Bitfield-Mask: 0x01) */ -#define PORT3_OUT_P8_Pos (8UL) /*!< PORT3 OUT: P8 (Bit 8) */ -#define PORT3_OUT_P8_Msk \ - (0x100UL) /*!< PORT3 OUT: P8 (Bitfield-Mask: 0x01) */ -#define PORT3_OUT_P9_Pos (9UL) /*!< PORT3 OUT: P9 (Bit 9) */ -#define PORT3_OUT_P9_Msk \ - (0x200UL) /*!< PORT3 OUT: P9 (Bitfield-Mask: 0x01) */ -#define PORT3_OUT_P10_Pos (10UL) /*!< PORT3 OUT: P10 (Bit 10) */ -#define PORT3_OUT_P10_Msk \ - (0x400UL) /*!< PORT3 OUT: P10 (Bitfield-Mask: 0x01) */ -#define PORT3_OUT_P11_Pos (11UL) /*!< PORT3 OUT: P11 (Bit 11) */ -#define PORT3_OUT_P11_Msk \ - (0x800UL) /*!< PORT3 OUT: P11 (Bitfield-Mask: 0x01) */ -#define PORT3_OUT_P12_Pos (12UL) /*!< PORT3 OUT: P12 (Bit 12) */ -#define PORT3_OUT_P12_Msk \ - (0x1000UL) /*!< PORT3 OUT: P12 (Bitfield-Mask: 0x01) */ -#define PORT3_OUT_P13_Pos (13UL) /*!< PORT3 OUT: P13 (Bit 13) */ -#define PORT3_OUT_P13_Msk \ - (0x2000UL) /*!< PORT3 OUT: P13 (Bitfield-Mask: 0x01) */ -#define PORT3_OUT_P14_Pos (14UL) /*!< PORT3 OUT: P14 (Bit 14) */ -#define PORT3_OUT_P14_Msk \ - (0x4000UL) /*!< PORT3 OUT: P14 (Bitfield-Mask: 0x01) */ -#define PORT3_OUT_P15_Pos (15UL) /*!< PORT3 OUT: P15 (Bit 15) */ -#define PORT3_OUT_P15_Msk \ - (0x8000UL) /*!< PORT3 OUT: P15 (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- PORT3_OMR --------------------------------- */ -#define PORT3_OMR_PS0_Pos (0UL) /*!< PORT3 OMR: PS0 (Bit 0) */ -#define PORT3_OMR_PS0_Msk \ - (0x1UL) /*!< PORT3 OMR: PS0 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PS1_Pos (1UL) /*!< PORT3 OMR: PS1 (Bit 1) */ -#define PORT3_OMR_PS1_Msk \ - (0x2UL) /*!< PORT3 OMR: PS1 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PS2_Pos (2UL) /*!< PORT3 OMR: PS2 (Bit 2) */ -#define PORT3_OMR_PS2_Msk \ - (0x4UL) /*!< PORT3 OMR: PS2 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PS3_Pos (3UL) /*!< PORT3 OMR: PS3 (Bit 3) */ -#define PORT3_OMR_PS3_Msk \ - (0x8UL) /*!< PORT3 OMR: PS3 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PS4_Pos (4UL) /*!< PORT3 OMR: PS4 (Bit 4) */ -#define PORT3_OMR_PS4_Msk \ - (0x10UL) /*!< PORT3 OMR: PS4 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PS5_Pos (5UL) /*!< PORT3 OMR: PS5 (Bit 5) */ -#define PORT3_OMR_PS5_Msk \ - (0x20UL) /*!< PORT3 OMR: PS5 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PS6_Pos (6UL) /*!< PORT3 OMR: PS6 (Bit 6) */ -#define PORT3_OMR_PS6_Msk \ - (0x40UL) /*!< PORT3 OMR: PS6 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PS7_Pos (7UL) /*!< PORT3 OMR: PS7 (Bit 7) */ -#define PORT3_OMR_PS7_Msk \ - (0x80UL) /*!< PORT3 OMR: PS7 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PS8_Pos (8UL) /*!< PORT3 OMR: PS8 (Bit 8) */ -#define PORT3_OMR_PS8_Msk \ - (0x100UL) /*!< PORT3 OMR: PS8 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PS9_Pos (9UL) /*!< PORT3 OMR: PS9 (Bit 9) */ -#define PORT3_OMR_PS9_Msk \ - (0x200UL) /*!< PORT3 OMR: PS9 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PS10_Pos \ - (10UL) /*!< PORT3 OMR: PS10 (Bit 10) */ -#define PORT3_OMR_PS10_Msk \ - (0x400UL) /*!< PORT3 OMR: PS10 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PS11_Pos \ - (11UL) /*!< PORT3 OMR: PS11 (Bit 11) */ -#define PORT3_OMR_PS11_Msk \ - (0x800UL) /*!< PORT3 OMR: PS11 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PS12_Pos \ - (12UL) /*!< PORT3 OMR: PS12 (Bit 12) */ -#define PORT3_OMR_PS12_Msk \ - (0x1000UL) /*!< PORT3 OMR: PS12 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PS13_Pos \ - (13UL) /*!< PORT3 OMR: PS13 (Bit 13) */ -#define PORT3_OMR_PS13_Msk \ - (0x2000UL) /*!< PORT3 OMR: PS13 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PS14_Pos \ - (14UL) /*!< PORT3 OMR: PS14 (Bit 14) */ -#define PORT3_OMR_PS14_Msk \ - (0x4000UL) /*!< PORT3 OMR: PS14 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PS15_Pos \ - (15UL) /*!< PORT3 OMR: PS15 (Bit 15) */ -#define PORT3_OMR_PS15_Msk \ - (0x8000UL) /*!< PORT3 OMR: PS15 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PR0_Pos (16UL) /*!< PORT3 OMR: PR0 (Bit 16) */ -#define PORT3_OMR_PR0_Msk \ - (0x10000UL) /*!< PORT3 OMR: PR0 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PR1_Pos (17UL) /*!< PORT3 OMR: PR1 (Bit 17) */ -#define PORT3_OMR_PR1_Msk \ - (0x20000UL) /*!< PORT3 OMR: PR1 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PR2_Pos (18UL) /*!< PORT3 OMR: PR2 (Bit 18) */ -#define PORT3_OMR_PR2_Msk \ - (0x40000UL) /*!< PORT3 OMR: PR2 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PR3_Pos (19UL) /*!< PORT3 OMR: PR3 (Bit 19) */ -#define PORT3_OMR_PR3_Msk \ - (0x80000UL) /*!< PORT3 OMR: PR3 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PR4_Pos (20UL) /*!< PORT3 OMR: PR4 (Bit 20) */ -#define PORT3_OMR_PR4_Msk \ - (0x100000UL) /*!< PORT3 OMR: PR4 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PR5_Pos (21UL) /*!< PORT3 OMR: PR5 (Bit 21) */ -#define PORT3_OMR_PR5_Msk \ - (0x200000UL) /*!< PORT3 OMR: PR5 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PR6_Pos (22UL) /*!< PORT3 OMR: PR6 (Bit 22) */ -#define PORT3_OMR_PR6_Msk \ - (0x400000UL) /*!< PORT3 OMR: PR6 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PR7_Pos (23UL) /*!< PORT3 OMR: PR7 (Bit 23) */ -#define PORT3_OMR_PR7_Msk \ - (0x800000UL) /*!< PORT3 OMR: PR7 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PR8_Pos (24UL) /*!< PORT3 OMR: PR8 (Bit 24) */ -#define PORT3_OMR_PR8_Msk \ - (0x1000000UL) /*!< PORT3 OMR: PR8 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PR9_Pos (25UL) /*!< PORT3 OMR: PR9 (Bit 25) */ -#define PORT3_OMR_PR9_Msk \ - (0x2000000UL) /*!< PORT3 OMR: PR9 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PR10_Pos \ - (26UL) /*!< PORT3 OMR: PR10 (Bit 26) */ -#define PORT3_OMR_PR10_Msk \ - (0x4000000UL) /*!< PORT3 OMR: PR10 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PR11_Pos \ - (27UL) /*!< PORT3 OMR: PR11 (Bit 27) */ -#define PORT3_OMR_PR11_Msk \ - (0x8000000UL) /*!< PORT3 OMR: PR11 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PR12_Pos \ - (28UL) /*!< PORT3 OMR: PR12 (Bit 28) */ -#define PORT3_OMR_PR12_Msk \ - (0x10000000UL) /*!< PORT3 OMR: PR12 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PR13_Pos \ - (29UL) /*!< PORT3 OMR: PR13 (Bit 29) */ -#define PORT3_OMR_PR13_Msk \ - (0x20000000UL) /*!< PORT3 OMR: PR13 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PR14_Pos \ - (30UL) /*!< PORT3 OMR: PR14 (Bit 30) */ -#define PORT3_OMR_PR14_Msk \ - (0x40000000UL) /*!< PORT3 OMR: PR14 (Bitfield-Mask: 0x01) */ -#define PORT3_OMR_PR15_Pos \ - (31UL) /*!< PORT3 OMR: PR15 (Bit 31) */ -#define PORT3_OMR_PR15_Msk \ - (0x80000000UL) /*!< PORT3 OMR: PR15 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- PORT3_IOCR0 -------------------------------- */ -#define PORT3_IOCR0_PC0_Pos \ - (3UL) /*!< PORT3 IOCR0: PC0 (Bit 3) */ -#define PORT3_IOCR0_PC0_Msk \ - (0xf8UL) /*!< PORT3 IOCR0: PC0 (Bitfield-Mask: 0x1f) */ -#define PORT3_IOCR0_PC1_Pos \ - (11UL) /*!< PORT3 IOCR0: PC1 (Bit 11) */ -#define PORT3_IOCR0_PC1_Msk \ - (0xf800UL) /*!< PORT3 IOCR0: PC1 (Bitfield-Mask: 0x1f) */ -#define PORT3_IOCR0_PC2_Pos \ - (19UL) /*!< PORT3 IOCR0: PC2 (Bit 19) */ -#define PORT3_IOCR0_PC2_Msk \ - (0xf80000UL) /*!< PORT3 IOCR0: PC2 (Bitfield-Mask: 0x1f) */ -#define PORT3_IOCR0_PC3_Pos \ - (27UL) /*!< PORT3 IOCR0: PC3 (Bit 27) */ -#define PORT3_IOCR0_PC3_Msk \ - (0xf8000000UL) /*!< PORT3 IOCR0: PC3 (Bitfield-Mask: 0x1f) */ - -/* --------------------------------- PORT3_IOCR4 -------------------------------- */ -#define PORT3_IOCR4_PC4_Pos \ - (3UL) /*!< PORT3 IOCR4: PC4 (Bit 3) */ -#define PORT3_IOCR4_PC4_Msk \ - (0xf8UL) /*!< PORT3 IOCR4: PC4 (Bitfield-Mask: 0x1f) */ -#define PORT3_IOCR4_PC5_Pos \ - (11UL) /*!< PORT3 IOCR4: PC5 (Bit 11) */ -#define PORT3_IOCR4_PC5_Msk \ - (0xf800UL) /*!< PORT3 IOCR4: PC5 (Bitfield-Mask: 0x1f) */ -#define PORT3_IOCR4_PC6_Pos \ - (19UL) /*!< PORT3 IOCR4: PC6 (Bit 19) */ -#define PORT3_IOCR4_PC6_Msk \ - (0xf80000UL) /*!< PORT3 IOCR4: PC6 (Bitfield-Mask: 0x1f) */ -#define PORT3_IOCR4_PC7_Pos \ - (27UL) /*!< PORT3 IOCR4: PC7 (Bit 27) */ -#define PORT3_IOCR4_PC7_Msk \ - (0xf8000000UL) /*!< PORT3 IOCR4: PC7 (Bitfield-Mask: 0x1f) */ - -/* ---------------------------------- PORT3_IN ---------------------------------- */ -#define PORT3_IN_P0_Pos (0UL) /*!< PORT3 IN: P0 (Bit 0) */ -#define PORT3_IN_P0_Msk (0x1UL) /*!< PORT3 IN: P0 (Bitfield-Mask: 0x01) */ -#define PORT3_IN_P1_Pos (1UL) /*!< PORT3 IN: P1 (Bit 1) */ -#define PORT3_IN_P1_Msk (0x2UL) /*!< PORT3 IN: P1 (Bitfield-Mask: 0x01) */ -#define PORT3_IN_P2_Pos (2UL) /*!< PORT3 IN: P2 (Bit 2) */ -#define PORT3_IN_P2_Msk (0x4UL) /*!< PORT3 IN: P2 (Bitfield-Mask: 0x01) */ -#define PORT3_IN_P3_Pos (3UL) /*!< PORT3 IN: P3 (Bit 3) */ -#define PORT3_IN_P3_Msk (0x8UL) /*!< PORT3 IN: P3 (Bitfield-Mask: 0x01) */ -#define PORT3_IN_P4_Pos (4UL) /*!< PORT3 IN: P4 (Bit 4) */ -#define PORT3_IN_P4_Msk (0x10UL) /*!< PORT3 IN: P4 (Bitfield-Mask: 0x01) */ -#define PORT3_IN_P5_Pos (5UL) /*!< PORT3 IN: P5 (Bit 5) */ -#define PORT3_IN_P5_Msk (0x20UL) /*!< PORT3 IN: P5 (Bitfield-Mask: 0x01) */ -#define PORT3_IN_P6_Pos (6UL) /*!< PORT3 IN: P6 (Bit 6) */ -#define PORT3_IN_P6_Msk (0x40UL) /*!< PORT3 IN: P6 (Bitfield-Mask: 0x01) */ -#define PORT3_IN_P7_Pos (7UL) /*!< PORT3 IN: P7 (Bit 7) */ -#define PORT3_IN_P7_Msk (0x80UL) /*!< PORT3 IN: P7 (Bitfield-Mask: 0x01) */ -#define PORT3_IN_P8_Pos (8UL) /*!< PORT3 IN: P8 (Bit 8) */ -#define PORT3_IN_P8_Msk \ - (0x100UL) /*!< PORT3 IN: P8 (Bitfield-Mask: 0x01) */ -#define PORT3_IN_P9_Pos (9UL) /*!< PORT3 IN: P9 (Bit 9) */ -#define PORT3_IN_P9_Msk \ - (0x200UL) /*!< PORT3 IN: P9 (Bitfield-Mask: 0x01) */ -#define PORT3_IN_P10_Pos (10UL) /*!< PORT3 IN: P10 (Bit 10) */ -#define PORT3_IN_P10_Msk \ - (0x400UL) /*!< PORT3 IN: P10 (Bitfield-Mask: 0x01) */ -#define PORT3_IN_P11_Pos (11UL) /*!< PORT3 IN: P11 (Bit 11) */ -#define PORT3_IN_P11_Msk \ - (0x800UL) /*!< PORT3 IN: P11 (Bitfield-Mask: 0x01) */ -#define PORT3_IN_P12_Pos (12UL) /*!< PORT3 IN: P12 (Bit 12) */ -#define PORT3_IN_P12_Msk \ - (0x1000UL) /*!< PORT3 IN: P12 (Bitfield-Mask: 0x01) */ -#define PORT3_IN_P13_Pos (13UL) /*!< PORT3 IN: P13 (Bit 13) */ -#define PORT3_IN_P13_Msk \ - (0x2000UL) /*!< PORT3 IN: P13 (Bitfield-Mask: 0x01) */ -#define PORT3_IN_P14_Pos (14UL) /*!< PORT3 IN: P14 (Bit 14) */ -#define PORT3_IN_P14_Msk \ - (0x4000UL) /*!< PORT3 IN: P14 (Bitfield-Mask: 0x01) */ -#define PORT3_IN_P15_Pos (15UL) /*!< PORT3 IN: P15 (Bit 15) */ -#define PORT3_IN_P15_Msk \ - (0x8000UL) /*!< PORT3 IN: P15 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- PORT3_PDR0 --------------------------------- */ -#define PORT3_PDR0_PD0_Pos (0UL) /*!< PORT3 PDR0: PD0 (Bit 0) */ -#define PORT3_PDR0_PD0_Msk \ - (0x7UL) /*!< PORT3 PDR0: PD0 (Bitfield-Mask: 0x07) */ -#define PORT3_PDR0_PD1_Pos (4UL) /*!< PORT3 PDR0: PD1 (Bit 4) */ -#define PORT3_PDR0_PD1_Msk \ - (0x70UL) /*!< PORT3 PDR0: PD1 (Bitfield-Mask: 0x07) */ -#define PORT3_PDR0_PD2_Pos (8UL) /*!< PORT3 PDR0: PD2 (Bit 8) */ -#define PORT3_PDR0_PD2_Msk \ - (0x700UL) /*!< PORT3 PDR0: PD2 (Bitfield-Mask: 0x07) */ -#define PORT3_PDR0_PD3_Pos \ - (12UL) /*!< PORT3 PDR0: PD3 (Bit 12) */ -#define PORT3_PDR0_PD3_Msk \ - (0x7000UL) /*!< PORT3 PDR0: PD3 (Bitfield-Mask: 0x07) */ -#define PORT3_PDR0_PD4_Pos \ - (16UL) /*!< PORT3 PDR0: PD4 (Bit 16) */ -#define PORT3_PDR0_PD4_Msk \ - (0x70000UL) /*!< PORT3 PDR0: PD4 (Bitfield-Mask: 0x07) */ -#define PORT3_PDR0_PD5_Pos \ - (20UL) /*!< PORT3 PDR0: PD5 (Bit 20) */ -#define PORT3_PDR0_PD5_Msk \ - (0x700000UL) /*!< PORT3 PDR0: PD5 (Bitfield-Mask: 0x07) */ -#define PORT3_PDR0_PD6_Pos \ - (24UL) /*!< PORT3 PDR0: PD6 (Bit 24) */ -#define PORT3_PDR0_PD6_Msk \ - (0x7000000UL) /*!< PORT3 PDR0: PD6 (Bitfield-Mask: 0x07) */ -#define PORT3_PDR0_PD7_Pos \ - (28UL) /*!< PORT3 PDR0: PD7 (Bit 28) */ -#define PORT3_PDR0_PD7_Msk \ - (0x70000000UL) /*!< PORT3 PDR0: PD7 (Bitfield-Mask: 0x07) */ - -/* --------------------------------- PORT3_PDISC -------------------------------- */ -#define PORT3_PDISC_PDIS0_Pos \ - (0UL) /*!< PORT3 PDISC: PDIS0 (Bit 0) */ -#define PORT3_PDISC_PDIS0_Msk \ - (0x1UL) /*!< PORT3 PDISC: PDIS0 (Bitfield-Mask: 0x01) */ -#define PORT3_PDISC_PDIS1_Pos \ - (1UL) /*!< PORT3 PDISC: PDIS1 (Bit 1) */ -#define PORT3_PDISC_PDIS1_Msk \ - (0x2UL) /*!< PORT3 PDISC: PDIS1 (Bitfield-Mask: 0x01) */ -#define PORT3_PDISC_PDIS2_Pos \ - (2UL) /*!< PORT3 PDISC: PDIS2 (Bit 2) */ -#define PORT3_PDISC_PDIS2_Msk \ - (0x4UL) /*!< PORT3 PDISC: PDIS2 (Bitfield-Mask: 0x01) */ -#define PORT3_PDISC_PDIS3_Pos \ - (3UL) /*!< PORT3 PDISC: PDIS3 (Bit 3) */ -#define PORT3_PDISC_PDIS3_Msk \ - (0x8UL) /*!< PORT3 PDISC: PDIS3 (Bitfield-Mask: 0x01) */ -#define PORT3_PDISC_PDIS4_Pos \ - (4UL) /*!< PORT3 PDISC: PDIS4 (Bit 4) */ -#define PORT3_PDISC_PDIS4_Msk \ - (0x10UL) /*!< PORT3 PDISC: PDIS4 (Bitfield-Mask: 0x01) */ -#define PORT3_PDISC_PDIS5_Pos \ - (5UL) /*!< PORT3 PDISC: PDIS5 (Bit 5) */ -#define PORT3_PDISC_PDIS5_Msk \ - (0x20UL) /*!< PORT3 PDISC: PDIS5 (Bitfield-Mask: 0x01) */ -#define PORT3_PDISC_PDIS6_Pos \ - (6UL) /*!< PORT3 PDISC: PDIS6 (Bit 6) */ -#define PORT3_PDISC_PDIS6_Msk \ - (0x40UL) /*!< PORT3 PDISC: PDIS6 (Bitfield-Mask: 0x01) */ -#define PORT3_PDISC_PDIS7_Pos \ - (7UL) /*!< PORT3 PDISC: PDIS7 (Bit 7) */ -#define PORT3_PDISC_PDIS7_Msk \ - (0x80UL) /*!< PORT3 PDISC: PDIS7 (Bitfield-Mask: 0x01) */ -#define PORT3_PDISC_PDIS8_Pos \ - (8UL) /*!< PORT3 PDISC: PDIS8 (Bit 8) */ -#define PORT3_PDISC_PDIS8_Msk \ - (0x100UL) /*!< PORT3 PDISC: PDIS8 (Bitfield-Mask: 0x01) */ -#define PORT3_PDISC_PDIS9_Pos \ - (9UL) /*!< PORT3 PDISC: PDIS9 (Bit 9) */ -#define PORT3_PDISC_PDIS9_Msk \ - (0x200UL) /*!< PORT3 PDISC: PDIS9 (Bitfield-Mask: 0x01) */ -#define PORT3_PDISC_PDIS10_Pos \ - (10UL) /*!< PORT3 PDISC: PDIS10 (Bit 10) */ -#define PORT3_PDISC_PDIS10_Msk \ - (0x400UL) /*!< PORT3 PDISC: PDIS10 (Bitfield-Mask: 0x01) */ -#define PORT3_PDISC_PDIS11_Pos \ - (11UL) /*!< PORT3 PDISC: PDIS11 (Bit 11) */ -#define PORT3_PDISC_PDIS11_Msk \ - (0x800UL) /*!< PORT3 PDISC: PDIS11 (Bitfield-Mask: 0x01) */ -#define PORT3_PDISC_PDIS12_Pos \ - (12UL) /*!< PORT3 PDISC: PDIS12 (Bit 12) */ -#define PORT3_PDISC_PDIS12_Msk \ - (0x1000UL) /*!< PORT3 PDISC: PDIS12 (Bitfield-Mask: 0x01) */ -#define PORT3_PDISC_PDIS13_Pos \ - (13UL) /*!< PORT3 PDISC: PDIS13 (Bit 13) */ -#define PORT3_PDISC_PDIS13_Msk \ - (0x2000UL) /*!< PORT3 PDISC: PDIS13 (Bitfield-Mask: 0x01) */ -#define PORT3_PDISC_PDIS14_Pos \ - (14UL) /*!< PORT3 PDISC: PDIS14 (Bit 14) */ -#define PORT3_PDISC_PDIS14_Msk \ - (0x4000UL) /*!< PORT3 PDISC: PDIS14 (Bitfield-Mask: 0x01) */ -#define PORT3_PDISC_PDIS15_Pos \ - (15UL) /*!< PORT3 PDISC: PDIS15 (Bit 15) */ -#define PORT3_PDISC_PDIS15_Msk \ - (0x8000UL) /*!< PORT3 PDISC: PDIS15 (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- PORT3_PPS --------------------------------- */ -#define PORT3_PPS_PPS0_Pos (0UL) /*!< PORT3 PPS: PPS0 (Bit 0) */ -#define PORT3_PPS_PPS0_Msk \ - (0x1UL) /*!< PORT3 PPS: PPS0 (Bitfield-Mask: 0x01) */ -#define PORT3_PPS_PPS1_Pos (1UL) /*!< PORT3 PPS: PPS1 (Bit 1) */ -#define PORT3_PPS_PPS1_Msk \ - (0x2UL) /*!< PORT3 PPS: PPS1 (Bitfield-Mask: 0x01) */ -#define PORT3_PPS_PPS2_Pos (2UL) /*!< PORT3 PPS: PPS2 (Bit 2) */ -#define PORT3_PPS_PPS2_Msk \ - (0x4UL) /*!< PORT3 PPS: PPS2 (Bitfield-Mask: 0x01) */ -#define PORT3_PPS_PPS3_Pos (3UL) /*!< PORT3 PPS: PPS3 (Bit 3) */ -#define PORT3_PPS_PPS3_Msk \ - (0x8UL) /*!< PORT3 PPS: PPS3 (Bitfield-Mask: 0x01) */ -#define PORT3_PPS_PPS4_Pos (4UL) /*!< PORT3 PPS: PPS4 (Bit 4) */ -#define PORT3_PPS_PPS4_Msk \ - (0x10UL) /*!< PORT3 PPS: PPS4 (Bitfield-Mask: 0x01) */ -#define PORT3_PPS_PPS5_Pos (5UL) /*!< PORT3 PPS: PPS5 (Bit 5) */ -#define PORT3_PPS_PPS5_Msk \ - (0x20UL) /*!< PORT3 PPS: PPS5 (Bitfield-Mask: 0x01) */ -#define PORT3_PPS_PPS6_Pos (6UL) /*!< PORT3 PPS: PPS6 (Bit 6) */ -#define PORT3_PPS_PPS6_Msk \ - (0x40UL) /*!< PORT3 PPS: PPS6 (Bitfield-Mask: 0x01) */ -#define PORT3_PPS_PPS7_Pos (7UL) /*!< PORT3 PPS: PPS7 (Bit 7) */ -#define PORT3_PPS_PPS7_Msk \ - (0x80UL) /*!< PORT3 PPS: PPS7 (Bitfield-Mask: 0x01) */ -#define PORT3_PPS_PPS8_Pos (8UL) /*!< PORT3 PPS: PPS8 (Bit 8) */ -#define PORT3_PPS_PPS8_Msk \ - (0x100UL) /*!< PORT3 PPS: PPS8 (Bitfield-Mask: 0x01) */ -#define PORT3_PPS_PPS9_Pos (9UL) /*!< PORT3 PPS: PPS9 (Bit 9) */ -#define PORT3_PPS_PPS9_Msk \ - (0x200UL) /*!< PORT3 PPS: PPS9 (Bitfield-Mask: 0x01) */ -#define PORT3_PPS_PPS10_Pos \ - (10UL) /*!< PORT3 PPS: PPS10 (Bit 10) */ -#define PORT3_PPS_PPS10_Msk \ - (0x400UL) /*!< PORT3 PPS: PPS10 (Bitfield-Mask: 0x01) */ -#define PORT3_PPS_PPS11_Pos \ - (11UL) /*!< PORT3 PPS: PPS11 (Bit 11) */ -#define PORT3_PPS_PPS11_Msk \ - (0x800UL) /*!< PORT3 PPS: PPS11 (Bitfield-Mask: 0x01) */ -#define PORT3_PPS_PPS12_Pos \ - (12UL) /*!< PORT3 PPS: PPS12 (Bit 12) */ -#define PORT3_PPS_PPS12_Msk \ - (0x1000UL) /*!< PORT3 PPS: PPS12 (Bitfield-Mask: 0x01) */ -#define PORT3_PPS_PPS13_Pos \ - (13UL) /*!< PORT3 PPS: PPS13 (Bit 13) */ -#define PORT3_PPS_PPS13_Msk \ - (0x2000UL) /*!< PORT3 PPS: PPS13 (Bitfield-Mask: 0x01) */ -#define PORT3_PPS_PPS14_Pos \ - (14UL) /*!< PORT3 PPS: PPS14 (Bit 14) */ -#define PORT3_PPS_PPS14_Msk \ - (0x4000UL) /*!< PORT3 PPS: PPS14 (Bitfield-Mask: 0x01) */ -#define PORT3_PPS_PPS15_Pos \ - (15UL) /*!< PORT3 PPS: PPS15 (Bit 15) */ -#define PORT3_PPS_PPS15_Msk \ - (0x8000UL) /*!< PORT3 PPS: PPS15 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- PORT3_HWSEL -------------------------------- */ -#define PORT3_HWSEL_HW0_Pos \ - (0UL) /*!< PORT3 HWSEL: HW0 (Bit 0) */ -#define PORT3_HWSEL_HW0_Msk \ - (0x3UL) /*!< PORT3 HWSEL: HW0 (Bitfield-Mask: 0x03) */ -#define PORT3_HWSEL_HW1_Pos \ - (2UL) /*!< PORT3 HWSEL: HW1 (Bit 2) */ -#define PORT3_HWSEL_HW1_Msk \ - (0xcUL) /*!< PORT3 HWSEL: HW1 (Bitfield-Mask: 0x03) */ -#define PORT3_HWSEL_HW2_Pos \ - (4UL) /*!< PORT3 HWSEL: HW2 (Bit 4) */ -#define PORT3_HWSEL_HW2_Msk \ - (0x30UL) /*!< PORT3 HWSEL: HW2 (Bitfield-Mask: 0x03) */ -#define PORT3_HWSEL_HW3_Pos \ - (6UL) /*!< PORT3 HWSEL: HW3 (Bit 6) */ -#define PORT3_HWSEL_HW3_Msk \ - (0xc0UL) /*!< PORT3 HWSEL: HW3 (Bitfield-Mask: 0x03) */ -#define PORT3_HWSEL_HW4_Pos \ - (8UL) /*!< PORT3 HWSEL: HW4 (Bit 8) */ -#define PORT3_HWSEL_HW4_Msk \ - (0x300UL) /*!< PORT3 HWSEL: HW4 (Bitfield-Mask: 0x03) */ -#define PORT3_HWSEL_HW5_Pos \ - (10UL) /*!< PORT3 HWSEL: HW5 (Bit 10) */ -#define PORT3_HWSEL_HW5_Msk \ - (0xc00UL) /*!< PORT3 HWSEL: HW5 (Bitfield-Mask: 0x03) */ -#define PORT3_HWSEL_HW6_Pos \ - (12UL) /*!< PORT3 HWSEL: HW6 (Bit 12) */ -#define PORT3_HWSEL_HW6_Msk \ - (0x3000UL) /*!< PORT3 HWSEL: HW6 (Bitfield-Mask: 0x03) */ -#define PORT3_HWSEL_HW7_Pos \ - (14UL) /*!< PORT3 HWSEL: HW7 (Bit 14) */ -#define PORT3_HWSEL_HW7_Msk \ - (0xc000UL) /*!< PORT3 HWSEL: HW7 (Bitfield-Mask: 0x03) */ -#define PORT3_HWSEL_HW8_Pos \ - (16UL) /*!< PORT3 HWSEL: HW8 (Bit 16) */ -#define PORT3_HWSEL_HW8_Msk \ - (0x30000UL) /*!< PORT3 HWSEL: HW8 (Bitfield-Mask: 0x03) */ -#define PORT3_HWSEL_HW9_Pos \ - (18UL) /*!< PORT3 HWSEL: HW9 (Bit 18) */ -#define PORT3_HWSEL_HW9_Msk \ - (0xc0000UL) /*!< PORT3 HWSEL: HW9 (Bitfield-Mask: 0x03) */ -#define PORT3_HWSEL_HW10_Pos \ - (20UL) /*!< PORT3 HWSEL: HW10 (Bit 20) */ -#define PORT3_HWSEL_HW10_Msk \ - (0x300000UL) /*!< PORT3 HWSEL: HW10 (Bitfield-Mask: 0x03) */ -#define PORT3_HWSEL_HW11_Pos \ - (22UL) /*!< PORT3 HWSEL: HW11 (Bit 22) */ -#define PORT3_HWSEL_HW11_Msk \ - (0xc00000UL) /*!< PORT3 HWSEL: HW11 (Bitfield-Mask: 0x03) */ -#define PORT3_HWSEL_HW12_Pos \ - (24UL) /*!< PORT3 HWSEL: HW12 (Bit 24) */ -#define PORT3_HWSEL_HW12_Msk \ - (0x3000000UL) /*!< PORT3 HWSEL: HW12 (Bitfield-Mask: 0x03) */ -#define PORT3_HWSEL_HW13_Pos \ - (26UL) /*!< PORT3 HWSEL: HW13 (Bit 26) */ -#define PORT3_HWSEL_HW13_Msk \ - (0xc000000UL) /*!< PORT3 HWSEL: HW13 (Bitfield-Mask: 0x03) */ -#define PORT3_HWSEL_HW14_Pos \ - (28UL) /*!< PORT3 HWSEL: HW14 (Bit 28) */ -#define PORT3_HWSEL_HW14_Msk \ - (0x30000000UL) /*!< PORT3 HWSEL: HW14 (Bitfield-Mask: 0x03) */ -#define PORT3_HWSEL_HW15_Pos \ - (30UL) /*!< PORT3 HWSEL: HW15 (Bit 30) */ -#define PORT3_HWSEL_HW15_Msk \ - (0xc0000000UL) /*!< PORT3 HWSEL: HW15 (Bitfield-Mask: 0x03) */ - -/* ================================================================================ */ -/* ================ struct 'PORT4' Position & Mask ================ */ -/* ================================================================================ */ - -/* ---------------------------------- PORT4_OUT --------------------------------- */ -#define PORT4_OUT_P0_Pos (0UL) /*!< PORT4 OUT: P0 (Bit 0) */ -#define PORT4_OUT_P0_Msk (0x1UL) /*!< PORT4 OUT: P0 (Bitfield-Mask: 0x01) */ -#define PORT4_OUT_P1_Pos (1UL) /*!< PORT4 OUT: P1 (Bit 1) */ -#define PORT4_OUT_P1_Msk (0x2UL) /*!< PORT4 OUT: P1 (Bitfield-Mask: 0x01) */ -#define PORT4_OUT_P2_Pos (2UL) /*!< PORT4 OUT: P2 (Bit 2) */ -#define PORT4_OUT_P2_Msk (0x4UL) /*!< PORT4 OUT: P2 (Bitfield-Mask: 0x01) */ -#define PORT4_OUT_P3_Pos (3UL) /*!< PORT4 OUT: P3 (Bit 3) */ -#define PORT4_OUT_P3_Msk (0x8UL) /*!< PORT4 OUT: P3 (Bitfield-Mask: 0x01) */ -#define PORT4_OUT_P4_Pos (4UL) /*!< PORT4 OUT: P4 (Bit 4) */ -#define PORT4_OUT_P4_Msk \ - (0x10UL) /*!< PORT4 OUT: P4 (Bitfield-Mask: 0x01) */ -#define PORT4_OUT_P5_Pos (5UL) /*!< PORT4 OUT: P5 (Bit 5) */ -#define PORT4_OUT_P5_Msk \ - (0x20UL) /*!< PORT4 OUT: P5 (Bitfield-Mask: 0x01) */ -#define PORT4_OUT_P6_Pos (6UL) /*!< PORT4 OUT: P6 (Bit 6) */ -#define PORT4_OUT_P6_Msk \ - (0x40UL) /*!< PORT4 OUT: P6 (Bitfield-Mask: 0x01) */ -#define PORT4_OUT_P7_Pos (7UL) /*!< PORT4 OUT: P7 (Bit 7) */ -#define PORT4_OUT_P7_Msk \ - (0x80UL) /*!< PORT4 OUT: P7 (Bitfield-Mask: 0x01) */ -#define PORT4_OUT_P8_Pos (8UL) /*!< PORT4 OUT: P8 (Bit 8) */ -#define PORT4_OUT_P8_Msk \ - (0x100UL) /*!< PORT4 OUT: P8 (Bitfield-Mask: 0x01) */ -#define PORT4_OUT_P9_Pos (9UL) /*!< PORT4 OUT: P9 (Bit 9) */ -#define PORT4_OUT_P9_Msk \ - (0x200UL) /*!< PORT4 OUT: P9 (Bitfield-Mask: 0x01) */ -#define PORT4_OUT_P10_Pos (10UL) /*!< PORT4 OUT: P10 (Bit 10) */ -#define PORT4_OUT_P10_Msk \ - (0x400UL) /*!< PORT4 OUT: P10 (Bitfield-Mask: 0x01) */ -#define PORT4_OUT_P11_Pos (11UL) /*!< PORT4 OUT: P11 (Bit 11) */ -#define PORT4_OUT_P11_Msk \ - (0x800UL) /*!< PORT4 OUT: P11 (Bitfield-Mask: 0x01) */ -#define PORT4_OUT_P12_Pos (12UL) /*!< PORT4 OUT: P12 (Bit 12) */ -#define PORT4_OUT_P12_Msk \ - (0x1000UL) /*!< PORT4 OUT: P12 (Bitfield-Mask: 0x01) */ -#define PORT4_OUT_P13_Pos (13UL) /*!< PORT4 OUT: P13 (Bit 13) */ -#define PORT4_OUT_P13_Msk \ - (0x2000UL) /*!< PORT4 OUT: P13 (Bitfield-Mask: 0x01) */ -#define PORT4_OUT_P14_Pos (14UL) /*!< PORT4 OUT: P14 (Bit 14) */ -#define PORT4_OUT_P14_Msk \ - (0x4000UL) /*!< PORT4 OUT: P14 (Bitfield-Mask: 0x01) */ -#define PORT4_OUT_P15_Pos (15UL) /*!< PORT4 OUT: P15 (Bit 15) */ -#define PORT4_OUT_P15_Msk \ - (0x8000UL) /*!< PORT4 OUT: P15 (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- PORT4_OMR --------------------------------- */ -#define PORT4_OMR_PS0_Pos (0UL) /*!< PORT4 OMR: PS0 (Bit 0) */ -#define PORT4_OMR_PS0_Msk \ - (0x1UL) /*!< PORT4 OMR: PS0 (Bitfield-Mask: 0x01) */ -#define PORT4_OMR_PS1_Pos (1UL) /*!< PORT4 OMR: PS1 (Bit 1) */ -#define PORT4_OMR_PS1_Msk \ - (0x2UL) /*!< PORT4 OMR: PS1 (Bitfield-Mask: 0x01) */ -#define PORT4_OMR_PS2_Pos (2UL) /*!< PORT4 OMR: PS2 (Bit 2) */ -#define PORT4_OMR_PS2_Msk \ - (0x4UL) /*!< PORT4 OMR: PS2 (Bitfield-Mask: 0x01) */ -#define PORT4_OMR_PS3_Pos (3UL) /*!< PORT4 OMR: PS3 (Bit 3) */ -#define PORT4_OMR_PS3_Msk \ - (0x8UL) /*!< PORT4 OMR: PS3 (Bitfield-Mask: 0x01) */ -#define PORT4_OMR_PS4_Pos (4UL) /*!< PORT4 OMR: PS4 (Bit 4) */ -#define PORT4_OMR_PS4_Msk \ - (0x10UL) /*!< PORT4 OMR: PS4 (Bitfield-Mask: 0x01) */ -#define PORT4_OMR_PS5_Pos (5UL) /*!< PORT4 OMR: PS5 (Bit 5) */ -#define PORT4_OMR_PS5_Msk \ - (0x20UL) /*!< PORT4 OMR: PS5 (Bitfield-Mask: 0x01) */ -#define PORT4_OMR_PS6_Pos (6UL) /*!< PORT4 OMR: PS6 (Bit 6) */ -#define PORT4_OMR_PS6_Msk \ - (0x40UL) /*!< PORT4 OMR: PS6 (Bitfield-Mask: 0x01) */ -#define PORT4_OMR_PS7_Pos (7UL) /*!< PORT4 OMR: PS7 (Bit 7) */ -#define PORT4_OMR_PS7_Msk \ - (0x80UL) /*!< PORT4 OMR: PS7 (Bitfield-Mask: 0x01) */ -#define PORT4_OMR_PS8_Pos (8UL) /*!< PORT4 OMR: PS8 (Bit 8) */ -#define PORT4_OMR_PS8_Msk \ - (0x100UL) /*!< PORT4 OMR: PS8 (Bitfield-Mask: 0x01) */ -#define PORT4_OMR_PS9_Pos (9UL) /*!< PORT4 OMR: PS9 (Bit 9) */ -#define PORT4_OMR_PS9_Msk \ - (0x200UL) /*!< PORT4 OMR: PS9 (Bitfield-Mask: 0x01) */ -#define PORT4_OMR_PS10_Pos \ - (10UL) /*!< PORT4 OMR: PS10 (Bit 10) */ -#define PORT4_OMR_PS10_Msk \ - (0x400UL) /*!< PORT4 OMR: PS10 (Bitfield-Mask: 0x01) */ -#define PORT4_OMR_PS11_Pos \ - (11UL) /*!< PORT4 OMR: PS11 (Bit 11) */ -#define PORT4_OMR_PS11_Msk \ - (0x800UL) /*!< PORT4 OMR: PS11 (Bitfield-Mask: 0x01) */ -#define PORT4_OMR_PS12_Pos \ - (12UL) /*!< PORT4 OMR: PS12 (Bit 12) */ -#define PORT4_OMR_PS12_Msk \ - (0x1000UL) /*!< PORT4 OMR: PS12 (Bitfield-Mask: 0x01) */ -#define PORT4_OMR_PS13_Pos \ - (13UL) /*!< PORT4 OMR: PS13 (Bit 13) */ -#define PORT4_OMR_PS13_Msk \ - (0x2000UL) /*!< PORT4 OMR: PS13 (Bitfield-Mask: 0x01) */ -#define PORT4_OMR_PS14_Pos \ - (14UL) /*!< PORT4 OMR: PS14 (Bit 14) */ -#define PORT4_OMR_PS14_Msk \ - (0x4000UL) /*!< PORT4 OMR: PS14 (Bitfield-Mask: 0x01) */ -#define PORT4_OMR_PS15_Pos \ - (15UL) /*!< PORT4 OMR: PS15 (Bit 15) */ -#define PORT4_OMR_PS15_Msk \ - (0x8000UL) /*!< PORT4 OMR: PS15 (Bitfield-Mask: 0x01) */ -#define PORT4_OMR_PR0_Pos (16UL) /*!< PORT4 OMR: PR0 (Bit 16) */ -#define PORT4_OMR_PR0_Msk \ - (0x10000UL) /*!< PORT4 OMR: PR0 (Bitfield-Mask: 0x01) */ -#define PORT4_OMR_PR1_Pos (17UL) /*!< PORT4 OMR: PR1 (Bit 17) */ -#define PORT4_OMR_PR1_Msk \ - (0x20000UL) /*!< PORT4 OMR: PR1 (Bitfield-Mask: 0x01) */ -#define PORT4_OMR_PR2_Pos (18UL) /*!< PORT4 OMR: PR2 (Bit 18) */ -#define PORT4_OMR_PR2_Msk \ - (0x40000UL) /*!< PORT4 OMR: PR2 (Bitfield-Mask: 0x01) */ -#define PORT4_OMR_PR3_Pos (19UL) /*!< PORT4 OMR: PR3 (Bit 19) */ -#define PORT4_OMR_PR3_Msk \ - (0x80000UL) /*!< PORT4 OMR: PR3 (Bitfield-Mask: 0x01) */ -#define PORT4_OMR_PR4_Pos (20UL) /*!< PORT4 OMR: PR4 (Bit 20) */ -#define PORT4_OMR_PR4_Msk \ - (0x100000UL) /*!< PORT4 OMR: PR4 (Bitfield-Mask: 0x01) */ -#define PORT4_OMR_PR5_Pos (21UL) /*!< PORT4 OMR: PR5 (Bit 21) */ -#define PORT4_OMR_PR5_Msk \ - (0x200000UL) /*!< PORT4 OMR: PR5 (Bitfield-Mask: 0x01) */ -#define PORT4_OMR_PR6_Pos (22UL) /*!< PORT4 OMR: PR6 (Bit 22) */ -#define PORT4_OMR_PR6_Msk \ - (0x400000UL) /*!< PORT4 OMR: PR6 (Bitfield-Mask: 0x01) */ -#define PORT4_OMR_PR7_Pos (23UL) /*!< PORT4 OMR: PR7 (Bit 23) */ -#define PORT4_OMR_PR7_Msk \ - (0x800000UL) /*!< PORT4 OMR: PR7 (Bitfield-Mask: 0x01) */ -#define PORT4_OMR_PR8_Pos (24UL) /*!< PORT4 OMR: PR8 (Bit 24) */ -#define PORT4_OMR_PR8_Msk \ - (0x1000000UL) /*!< PORT4 OMR: PR8 (Bitfield-Mask: 0x01) */ -#define PORT4_OMR_PR9_Pos (25UL) /*!< PORT4 OMR: PR9 (Bit 25) */ -#define PORT4_OMR_PR9_Msk \ - (0x2000000UL) /*!< PORT4 OMR: PR9 (Bitfield-Mask: 0x01) */ -#define PORT4_OMR_PR10_Pos \ - (26UL) /*!< PORT4 OMR: PR10 (Bit 26) */ -#define PORT4_OMR_PR10_Msk \ - (0x4000000UL) /*!< PORT4 OMR: PR10 (Bitfield-Mask: 0x01) */ -#define PORT4_OMR_PR11_Pos \ - (27UL) /*!< PORT4 OMR: PR11 (Bit 27) */ -#define PORT4_OMR_PR11_Msk \ - (0x8000000UL) /*!< PORT4 OMR: PR11 (Bitfield-Mask: 0x01) */ -#define PORT4_OMR_PR12_Pos \ - (28UL) /*!< PORT4 OMR: PR12 (Bit 28) */ -#define PORT4_OMR_PR12_Msk \ - (0x10000000UL) /*!< PORT4 OMR: PR12 (Bitfield-Mask: 0x01) */ -#define PORT4_OMR_PR13_Pos \ - (29UL) /*!< PORT4 OMR: PR13 (Bit 29) */ -#define PORT4_OMR_PR13_Msk \ - (0x20000000UL) /*!< PORT4 OMR: PR13 (Bitfield-Mask: 0x01) */ -#define PORT4_OMR_PR14_Pos \ - (30UL) /*!< PORT4 OMR: PR14 (Bit 30) */ -#define PORT4_OMR_PR14_Msk \ - (0x40000000UL) /*!< PORT4 OMR: PR14 (Bitfield-Mask: 0x01) */ -#define PORT4_OMR_PR15_Pos \ - (31UL) /*!< PORT4 OMR: PR15 (Bit 31) */ -#define PORT4_OMR_PR15_Msk \ - (0x80000000UL) /*!< PORT4 OMR: PR15 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- PORT4_IOCR0 -------------------------------- */ -#define PORT4_IOCR0_PC0_Pos \ - (3UL) /*!< PORT4 IOCR0: PC0 (Bit 3) */ -#define PORT4_IOCR0_PC0_Msk \ - (0xf8UL) /*!< PORT4 IOCR0: PC0 (Bitfield-Mask: 0x1f) */ -#define PORT4_IOCR0_PC1_Pos \ - (11UL) /*!< PORT4 IOCR0: PC1 (Bit 11) */ -#define PORT4_IOCR0_PC1_Msk \ - (0xf800UL) /*!< PORT4 IOCR0: PC1 (Bitfield-Mask: 0x1f) */ -#define PORT4_IOCR0_PC2_Pos \ - (19UL) /*!< PORT4 IOCR0: PC2 (Bit 19) */ -#define PORT4_IOCR0_PC2_Msk \ - (0xf80000UL) /*!< PORT4 IOCR0: PC2 (Bitfield-Mask: 0x1f) */ -#define PORT4_IOCR0_PC3_Pos \ - (27UL) /*!< PORT4 IOCR0: PC3 (Bit 27) */ -#define PORT4_IOCR0_PC3_Msk \ - (0xf8000000UL) /*!< PORT4 IOCR0: PC3 (Bitfield-Mask: 0x1f) */ - -/* ---------------------------------- PORT4_IN ---------------------------------- */ -#define PORT4_IN_P0_Pos (0UL) /*!< PORT4 IN: P0 (Bit 0) */ -#define PORT4_IN_P0_Msk (0x1UL) /*!< PORT4 IN: P0 (Bitfield-Mask: 0x01) */ -#define PORT4_IN_P1_Pos (1UL) /*!< PORT4 IN: P1 (Bit 1) */ -#define PORT4_IN_P1_Msk (0x2UL) /*!< PORT4 IN: P1 (Bitfield-Mask: 0x01) */ -#define PORT4_IN_P2_Pos (2UL) /*!< PORT4 IN: P2 (Bit 2) */ -#define PORT4_IN_P2_Msk (0x4UL) /*!< PORT4 IN: P2 (Bitfield-Mask: 0x01) */ -#define PORT4_IN_P3_Pos (3UL) /*!< PORT4 IN: P3 (Bit 3) */ -#define PORT4_IN_P3_Msk (0x8UL) /*!< PORT4 IN: P3 (Bitfield-Mask: 0x01) */ -#define PORT4_IN_P4_Pos (4UL) /*!< PORT4 IN: P4 (Bit 4) */ -#define PORT4_IN_P4_Msk (0x10UL) /*!< PORT4 IN: P4 (Bitfield-Mask: 0x01) */ -#define PORT4_IN_P5_Pos (5UL) /*!< PORT4 IN: P5 (Bit 5) */ -#define PORT4_IN_P5_Msk (0x20UL) /*!< PORT4 IN: P5 (Bitfield-Mask: 0x01) */ -#define PORT4_IN_P6_Pos (6UL) /*!< PORT4 IN: P6 (Bit 6) */ -#define PORT4_IN_P6_Msk (0x40UL) /*!< PORT4 IN: P6 (Bitfield-Mask: 0x01) */ -#define PORT4_IN_P7_Pos (7UL) /*!< PORT4 IN: P7 (Bit 7) */ -#define PORT4_IN_P7_Msk (0x80UL) /*!< PORT4 IN: P7 (Bitfield-Mask: 0x01) */ -#define PORT4_IN_P8_Pos (8UL) /*!< PORT4 IN: P8 (Bit 8) */ -#define PORT4_IN_P8_Msk \ - (0x100UL) /*!< PORT4 IN: P8 (Bitfield-Mask: 0x01) */ -#define PORT4_IN_P9_Pos (9UL) /*!< PORT4 IN: P9 (Bit 9) */ -#define PORT4_IN_P9_Msk \ - (0x200UL) /*!< PORT4 IN: P9 (Bitfield-Mask: 0x01) */ -#define PORT4_IN_P10_Pos (10UL) /*!< PORT4 IN: P10 (Bit 10) */ -#define PORT4_IN_P10_Msk \ - (0x400UL) /*!< PORT4 IN: P10 (Bitfield-Mask: 0x01) */ -#define PORT4_IN_P11_Pos (11UL) /*!< PORT4 IN: P11 (Bit 11) */ -#define PORT4_IN_P11_Msk \ - (0x800UL) /*!< PORT4 IN: P11 (Bitfield-Mask: 0x01) */ -#define PORT4_IN_P12_Pos (12UL) /*!< PORT4 IN: P12 (Bit 12) */ -#define PORT4_IN_P12_Msk \ - (0x1000UL) /*!< PORT4 IN: P12 (Bitfield-Mask: 0x01) */ -#define PORT4_IN_P13_Pos (13UL) /*!< PORT4 IN: P13 (Bit 13) */ -#define PORT4_IN_P13_Msk \ - (0x2000UL) /*!< PORT4 IN: P13 (Bitfield-Mask: 0x01) */ -#define PORT4_IN_P14_Pos (14UL) /*!< PORT4 IN: P14 (Bit 14) */ -#define PORT4_IN_P14_Msk \ - (0x4000UL) /*!< PORT4 IN: P14 (Bitfield-Mask: 0x01) */ -#define PORT4_IN_P15_Pos (15UL) /*!< PORT4 IN: P15 (Bit 15) */ -#define PORT4_IN_P15_Msk \ - (0x8000UL) /*!< PORT4 IN: P15 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- PORT4_PDR0 --------------------------------- */ -#define PORT4_PDR0_PD0_Pos (0UL) /*!< PORT4 PDR0: PD0 (Bit 0) */ -#define PORT4_PDR0_PD0_Msk \ - (0x7UL) /*!< PORT4 PDR0: PD0 (Bitfield-Mask: 0x07) */ -#define PORT4_PDR0_PD1_Pos (4UL) /*!< PORT4 PDR0: PD1 (Bit 4) */ -#define PORT4_PDR0_PD1_Msk \ - (0x70UL) /*!< PORT4 PDR0: PD1 (Bitfield-Mask: 0x07) */ -#define PORT4_PDR0_PD2_Pos (8UL) /*!< PORT4 PDR0: PD2 (Bit 8) */ -#define PORT4_PDR0_PD2_Msk \ - (0x700UL) /*!< PORT4 PDR0: PD2 (Bitfield-Mask: 0x07) */ -#define PORT4_PDR0_PD3_Pos \ - (12UL) /*!< PORT4 PDR0: PD3 (Bit 12) */ -#define PORT4_PDR0_PD3_Msk \ - (0x7000UL) /*!< PORT4 PDR0: PD3 (Bitfield-Mask: 0x07) */ -#define PORT4_PDR0_PD4_Pos \ - (16UL) /*!< PORT4 PDR0: PD4 (Bit 16) */ -#define PORT4_PDR0_PD4_Msk \ - (0x70000UL) /*!< PORT4 PDR0: PD4 (Bitfield-Mask: 0x07) */ -#define PORT4_PDR0_PD5_Pos \ - (20UL) /*!< PORT4 PDR0: PD5 (Bit 20) */ -#define PORT4_PDR0_PD5_Msk \ - (0x700000UL) /*!< PORT4 PDR0: PD5 (Bitfield-Mask: 0x07) */ -#define PORT4_PDR0_PD6_Pos \ - (24UL) /*!< PORT4 PDR0: PD6 (Bit 24) */ -#define PORT4_PDR0_PD6_Msk \ - (0x7000000UL) /*!< PORT4 PDR0: PD6 (Bitfield-Mask: 0x07) */ -#define PORT4_PDR0_PD7_Pos \ - (28UL) /*!< PORT4 PDR0: PD7 (Bit 28) */ -#define PORT4_PDR0_PD7_Msk \ - (0x70000000UL) /*!< PORT4 PDR0: PD7 (Bitfield-Mask: 0x07) */ - -/* --------------------------------- PORT4_PDISC -------------------------------- */ -#define PORT4_PDISC_PDIS0_Pos \ - (0UL) /*!< PORT4 PDISC: PDIS0 (Bit 0) */ -#define PORT4_PDISC_PDIS0_Msk \ - (0x1UL) /*!< PORT4 PDISC: PDIS0 (Bitfield-Mask: 0x01) */ -#define PORT4_PDISC_PDIS1_Pos \ - (1UL) /*!< PORT4 PDISC: PDIS1 (Bit 1) */ -#define PORT4_PDISC_PDIS1_Msk \ - (0x2UL) /*!< PORT4 PDISC: PDIS1 (Bitfield-Mask: 0x01) */ -#define PORT4_PDISC_PDIS2_Pos \ - (2UL) /*!< PORT4 PDISC: PDIS2 (Bit 2) */ -#define PORT4_PDISC_PDIS2_Msk \ - (0x4UL) /*!< PORT4 PDISC: PDIS2 (Bitfield-Mask: 0x01) */ -#define PORT4_PDISC_PDIS3_Pos \ - (3UL) /*!< PORT4 PDISC: PDIS3 (Bit 3) */ -#define PORT4_PDISC_PDIS3_Msk \ - (0x8UL) /*!< PORT4 PDISC: PDIS3 (Bitfield-Mask: 0x01) */ -#define PORT4_PDISC_PDIS4_Pos \ - (4UL) /*!< PORT4 PDISC: PDIS4 (Bit 4) */ -#define PORT4_PDISC_PDIS4_Msk \ - (0x10UL) /*!< PORT4 PDISC: PDIS4 (Bitfield-Mask: 0x01) */ -#define PORT4_PDISC_PDIS5_Pos \ - (5UL) /*!< PORT4 PDISC: PDIS5 (Bit 5) */ -#define PORT4_PDISC_PDIS5_Msk \ - (0x20UL) /*!< PORT4 PDISC: PDIS5 (Bitfield-Mask: 0x01) */ -#define PORT4_PDISC_PDIS6_Pos \ - (6UL) /*!< PORT4 PDISC: PDIS6 (Bit 6) */ -#define PORT4_PDISC_PDIS6_Msk \ - (0x40UL) /*!< PORT4 PDISC: PDIS6 (Bitfield-Mask: 0x01) */ -#define PORT4_PDISC_PDIS7_Pos \ - (7UL) /*!< PORT4 PDISC: PDIS7 (Bit 7) */ -#define PORT4_PDISC_PDIS7_Msk \ - (0x80UL) /*!< PORT4 PDISC: PDIS7 (Bitfield-Mask: 0x01) */ -#define PORT4_PDISC_PDIS8_Pos \ - (8UL) /*!< PORT4 PDISC: PDIS8 (Bit 8) */ -#define PORT4_PDISC_PDIS8_Msk \ - (0x100UL) /*!< PORT4 PDISC: PDIS8 (Bitfield-Mask: 0x01) */ -#define PORT4_PDISC_PDIS9_Pos \ - (9UL) /*!< PORT4 PDISC: PDIS9 (Bit 9) */ -#define PORT4_PDISC_PDIS9_Msk \ - (0x200UL) /*!< PORT4 PDISC: PDIS9 (Bitfield-Mask: 0x01) */ -#define PORT4_PDISC_PDIS10_Pos \ - (10UL) /*!< PORT4 PDISC: PDIS10 (Bit 10) */ -#define PORT4_PDISC_PDIS10_Msk \ - (0x400UL) /*!< PORT4 PDISC: PDIS10 (Bitfield-Mask: 0x01) */ -#define PORT4_PDISC_PDIS11_Pos \ - (11UL) /*!< PORT4 PDISC: PDIS11 (Bit 11) */ -#define PORT4_PDISC_PDIS11_Msk \ - (0x800UL) /*!< PORT4 PDISC: PDIS11 (Bitfield-Mask: 0x01) */ -#define PORT4_PDISC_PDIS12_Pos \ - (12UL) /*!< PORT4 PDISC: PDIS12 (Bit 12) */ -#define PORT4_PDISC_PDIS12_Msk \ - (0x1000UL) /*!< PORT4 PDISC: PDIS12 (Bitfield-Mask: 0x01) */ -#define PORT4_PDISC_PDIS13_Pos \ - (13UL) /*!< PORT4 PDISC: PDIS13 (Bit 13) */ -#define PORT4_PDISC_PDIS13_Msk \ - (0x2000UL) /*!< PORT4 PDISC: PDIS13 (Bitfield-Mask: 0x01) */ -#define PORT4_PDISC_PDIS14_Pos \ - (14UL) /*!< PORT4 PDISC: PDIS14 (Bit 14) */ -#define PORT4_PDISC_PDIS14_Msk \ - (0x4000UL) /*!< PORT4 PDISC: PDIS14 (Bitfield-Mask: 0x01) */ -#define PORT4_PDISC_PDIS15_Pos \ - (15UL) /*!< PORT4 PDISC: PDIS15 (Bit 15) */ -#define PORT4_PDISC_PDIS15_Msk \ - (0x8000UL) /*!< PORT4 PDISC: PDIS15 (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- PORT4_PPS --------------------------------- */ -#define PORT4_PPS_PPS0_Pos (0UL) /*!< PORT4 PPS: PPS0 (Bit 0) */ -#define PORT4_PPS_PPS0_Msk \ - (0x1UL) /*!< PORT4 PPS: PPS0 (Bitfield-Mask: 0x01) */ -#define PORT4_PPS_PPS1_Pos (1UL) /*!< PORT4 PPS: PPS1 (Bit 1) */ -#define PORT4_PPS_PPS1_Msk \ - (0x2UL) /*!< PORT4 PPS: PPS1 (Bitfield-Mask: 0x01) */ -#define PORT4_PPS_PPS2_Pos (2UL) /*!< PORT4 PPS: PPS2 (Bit 2) */ -#define PORT4_PPS_PPS2_Msk \ - (0x4UL) /*!< PORT4 PPS: PPS2 (Bitfield-Mask: 0x01) */ -#define PORT4_PPS_PPS3_Pos (3UL) /*!< PORT4 PPS: PPS3 (Bit 3) */ -#define PORT4_PPS_PPS3_Msk \ - (0x8UL) /*!< PORT4 PPS: PPS3 (Bitfield-Mask: 0x01) */ -#define PORT4_PPS_PPS4_Pos (4UL) /*!< PORT4 PPS: PPS4 (Bit 4) */ -#define PORT4_PPS_PPS4_Msk \ - (0x10UL) /*!< PORT4 PPS: PPS4 (Bitfield-Mask: 0x01) */ -#define PORT4_PPS_PPS5_Pos (5UL) /*!< PORT4 PPS: PPS5 (Bit 5) */ -#define PORT4_PPS_PPS5_Msk \ - (0x20UL) /*!< PORT4 PPS: PPS5 (Bitfield-Mask: 0x01) */ -#define PORT4_PPS_PPS6_Pos (6UL) /*!< PORT4 PPS: PPS6 (Bit 6) */ -#define PORT4_PPS_PPS6_Msk \ - (0x40UL) /*!< PORT4 PPS: PPS6 (Bitfield-Mask: 0x01) */ -#define PORT4_PPS_PPS7_Pos (7UL) /*!< PORT4 PPS: PPS7 (Bit 7) */ -#define PORT4_PPS_PPS7_Msk \ - (0x80UL) /*!< PORT4 PPS: PPS7 (Bitfield-Mask: 0x01) */ -#define PORT4_PPS_PPS8_Pos (8UL) /*!< PORT4 PPS: PPS8 (Bit 8) */ -#define PORT4_PPS_PPS8_Msk \ - (0x100UL) /*!< PORT4 PPS: PPS8 (Bitfield-Mask: 0x01) */ -#define PORT4_PPS_PPS9_Pos (9UL) /*!< PORT4 PPS: PPS9 (Bit 9) */ -#define PORT4_PPS_PPS9_Msk \ - (0x200UL) /*!< PORT4 PPS: PPS9 (Bitfield-Mask: 0x01) */ -#define PORT4_PPS_PPS10_Pos \ - (10UL) /*!< PORT4 PPS: PPS10 (Bit 10) */ -#define PORT4_PPS_PPS10_Msk \ - (0x400UL) /*!< PORT4 PPS: PPS10 (Bitfield-Mask: 0x01) */ -#define PORT4_PPS_PPS11_Pos \ - (11UL) /*!< PORT4 PPS: PPS11 (Bit 11) */ -#define PORT4_PPS_PPS11_Msk \ - (0x800UL) /*!< PORT4 PPS: PPS11 (Bitfield-Mask: 0x01) */ -#define PORT4_PPS_PPS12_Pos \ - (12UL) /*!< PORT4 PPS: PPS12 (Bit 12) */ -#define PORT4_PPS_PPS12_Msk \ - (0x1000UL) /*!< PORT4 PPS: PPS12 (Bitfield-Mask: 0x01) */ -#define PORT4_PPS_PPS13_Pos \ - (13UL) /*!< PORT4 PPS: PPS13 (Bit 13) */ -#define PORT4_PPS_PPS13_Msk \ - (0x2000UL) /*!< PORT4 PPS: PPS13 (Bitfield-Mask: 0x01) */ -#define PORT4_PPS_PPS14_Pos \ - (14UL) /*!< PORT4 PPS: PPS14 (Bit 14) */ -#define PORT4_PPS_PPS14_Msk \ - (0x4000UL) /*!< PORT4 PPS: PPS14 (Bitfield-Mask: 0x01) */ -#define PORT4_PPS_PPS15_Pos \ - (15UL) /*!< PORT4 PPS: PPS15 (Bit 15) */ -#define PORT4_PPS_PPS15_Msk \ - (0x8000UL) /*!< PORT4 PPS: PPS15 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- PORT4_HWSEL -------------------------------- */ -#define PORT4_HWSEL_HW0_Pos \ - (0UL) /*!< PORT4 HWSEL: HW0 (Bit 0) */ -#define PORT4_HWSEL_HW0_Msk \ - (0x3UL) /*!< PORT4 HWSEL: HW0 (Bitfield-Mask: 0x03) */ -#define PORT4_HWSEL_HW1_Pos \ - (2UL) /*!< PORT4 HWSEL: HW1 (Bit 2) */ -#define PORT4_HWSEL_HW1_Msk \ - (0xcUL) /*!< PORT4 HWSEL: HW1 (Bitfield-Mask: 0x03) */ -#define PORT4_HWSEL_HW2_Pos \ - (4UL) /*!< PORT4 HWSEL: HW2 (Bit 4) */ -#define PORT4_HWSEL_HW2_Msk \ - (0x30UL) /*!< PORT4 HWSEL: HW2 (Bitfield-Mask: 0x03) */ -#define PORT4_HWSEL_HW3_Pos \ - (6UL) /*!< PORT4 HWSEL: HW3 (Bit 6) */ -#define PORT4_HWSEL_HW3_Msk \ - (0xc0UL) /*!< PORT4 HWSEL: HW3 (Bitfield-Mask: 0x03) */ -#define PORT4_HWSEL_HW4_Pos \ - (8UL) /*!< PORT4 HWSEL: HW4 (Bit 8) */ -#define PORT4_HWSEL_HW4_Msk \ - (0x300UL) /*!< PORT4 HWSEL: HW4 (Bitfield-Mask: 0x03) */ -#define PORT4_HWSEL_HW5_Pos \ - (10UL) /*!< PORT4 HWSEL: HW5 (Bit 10) */ -#define PORT4_HWSEL_HW5_Msk \ - (0xc00UL) /*!< PORT4 HWSEL: HW5 (Bitfield-Mask: 0x03) */ -#define PORT4_HWSEL_HW6_Pos \ - (12UL) /*!< PORT4 HWSEL: HW6 (Bit 12) */ -#define PORT4_HWSEL_HW6_Msk \ - (0x3000UL) /*!< PORT4 HWSEL: HW6 (Bitfield-Mask: 0x03) */ -#define PORT4_HWSEL_HW7_Pos \ - (14UL) /*!< PORT4 HWSEL: HW7 (Bit 14) */ -#define PORT4_HWSEL_HW7_Msk \ - (0xc000UL) /*!< PORT4 HWSEL: HW7 (Bitfield-Mask: 0x03) */ -#define PORT4_HWSEL_HW8_Pos \ - (16UL) /*!< PORT4 HWSEL: HW8 (Bit 16) */ -#define PORT4_HWSEL_HW8_Msk \ - (0x30000UL) /*!< PORT4 HWSEL: HW8 (Bitfield-Mask: 0x03) */ -#define PORT4_HWSEL_HW9_Pos \ - (18UL) /*!< PORT4 HWSEL: HW9 (Bit 18) */ -#define PORT4_HWSEL_HW9_Msk \ - (0xc0000UL) /*!< PORT4 HWSEL: HW9 (Bitfield-Mask: 0x03) */ -#define PORT4_HWSEL_HW10_Pos \ - (20UL) /*!< PORT4 HWSEL: HW10 (Bit 20) */ -#define PORT4_HWSEL_HW10_Msk \ - (0x300000UL) /*!< PORT4 HWSEL: HW10 (Bitfield-Mask: 0x03) */ -#define PORT4_HWSEL_HW11_Pos \ - (22UL) /*!< PORT4 HWSEL: HW11 (Bit 22) */ -#define PORT4_HWSEL_HW11_Msk \ - (0xc00000UL) /*!< PORT4 HWSEL: HW11 (Bitfield-Mask: 0x03) */ -#define PORT4_HWSEL_HW12_Pos \ - (24UL) /*!< PORT4 HWSEL: HW12 (Bit 24) */ -#define PORT4_HWSEL_HW12_Msk \ - (0x3000000UL) /*!< PORT4 HWSEL: HW12 (Bitfield-Mask: 0x03) */ -#define PORT4_HWSEL_HW13_Pos \ - (26UL) /*!< PORT4 HWSEL: HW13 (Bit 26) */ -#define PORT4_HWSEL_HW13_Msk \ - (0xc000000UL) /*!< PORT4 HWSEL: HW13 (Bitfield-Mask: 0x03) */ -#define PORT4_HWSEL_HW14_Pos \ - (28UL) /*!< PORT4 HWSEL: HW14 (Bit 28) */ -#define PORT4_HWSEL_HW14_Msk \ - (0x30000000UL) /*!< PORT4 HWSEL: HW14 (Bitfield-Mask: 0x03) */ -#define PORT4_HWSEL_HW15_Pos \ - (30UL) /*!< PORT4 HWSEL: HW15 (Bit 30) */ -#define PORT4_HWSEL_HW15_Msk \ - (0xc0000000UL) /*!< PORT4 HWSEL: HW15 (Bitfield-Mask: 0x03) */ - -/* ================================================================================ */ -/* ================ struct 'PORT5' Position & Mask ================ */ -/* ================================================================================ */ - -/* ---------------------------------- PORT5_OUT --------------------------------- */ -#define PORT5_OUT_P0_Pos (0UL) /*!< PORT5 OUT: P0 (Bit 0) */ -#define PORT5_OUT_P0_Msk (0x1UL) /*!< PORT5 OUT: P0 (Bitfield-Mask: 0x01) */ -#define PORT5_OUT_P1_Pos (1UL) /*!< PORT5 OUT: P1 (Bit 1) */ -#define PORT5_OUT_P1_Msk (0x2UL) /*!< PORT5 OUT: P1 (Bitfield-Mask: 0x01) */ -#define PORT5_OUT_P2_Pos (2UL) /*!< PORT5 OUT: P2 (Bit 2) */ -#define PORT5_OUT_P2_Msk (0x4UL) /*!< PORT5 OUT: P2 (Bitfield-Mask: 0x01) */ -#define PORT5_OUT_P3_Pos (3UL) /*!< PORT5 OUT: P3 (Bit 3) */ -#define PORT5_OUT_P3_Msk (0x8UL) /*!< PORT5 OUT: P3 (Bitfield-Mask: 0x01) */ -#define PORT5_OUT_P4_Pos (4UL) /*!< PORT5 OUT: P4 (Bit 4) */ -#define PORT5_OUT_P4_Msk \ - (0x10UL) /*!< PORT5 OUT: P4 (Bitfield-Mask: 0x01) */ -#define PORT5_OUT_P5_Pos (5UL) /*!< PORT5 OUT: P5 (Bit 5) */ -#define PORT5_OUT_P5_Msk \ - (0x20UL) /*!< PORT5 OUT: P5 (Bitfield-Mask: 0x01) */ -#define PORT5_OUT_P6_Pos (6UL) /*!< PORT5 OUT: P6 (Bit 6) */ -#define PORT5_OUT_P6_Msk \ - (0x40UL) /*!< PORT5 OUT: P6 (Bitfield-Mask: 0x01) */ -#define PORT5_OUT_P7_Pos (7UL) /*!< PORT5 OUT: P7 (Bit 7) */ -#define PORT5_OUT_P7_Msk \ - (0x80UL) /*!< PORT5 OUT: P7 (Bitfield-Mask: 0x01) */ -#define PORT5_OUT_P8_Pos (8UL) /*!< PORT5 OUT: P8 (Bit 8) */ -#define PORT5_OUT_P8_Msk \ - (0x100UL) /*!< PORT5 OUT: P8 (Bitfield-Mask: 0x01) */ -#define PORT5_OUT_P9_Pos (9UL) /*!< PORT5 OUT: P9 (Bit 9) */ -#define PORT5_OUT_P9_Msk \ - (0x200UL) /*!< PORT5 OUT: P9 (Bitfield-Mask: 0x01) */ -#define PORT5_OUT_P10_Pos (10UL) /*!< PORT5 OUT: P10 (Bit 10) */ -#define PORT5_OUT_P10_Msk \ - (0x400UL) /*!< PORT5 OUT: P10 (Bitfield-Mask: 0x01) */ -#define PORT5_OUT_P11_Pos (11UL) /*!< PORT5 OUT: P11 (Bit 11) */ -#define PORT5_OUT_P11_Msk \ - (0x800UL) /*!< PORT5 OUT: P11 (Bitfield-Mask: 0x01) */ -#define PORT5_OUT_P12_Pos (12UL) /*!< PORT5 OUT: P12 (Bit 12) */ -#define PORT5_OUT_P12_Msk \ - (0x1000UL) /*!< PORT5 OUT: P12 (Bitfield-Mask: 0x01) */ -#define PORT5_OUT_P13_Pos (13UL) /*!< PORT5 OUT: P13 (Bit 13) */ -#define PORT5_OUT_P13_Msk \ - (0x2000UL) /*!< PORT5 OUT: P13 (Bitfield-Mask: 0x01) */ -#define PORT5_OUT_P14_Pos (14UL) /*!< PORT5 OUT: P14 (Bit 14) */ -#define PORT5_OUT_P14_Msk \ - (0x4000UL) /*!< PORT5 OUT: P14 (Bitfield-Mask: 0x01) */ -#define PORT5_OUT_P15_Pos (15UL) /*!< PORT5 OUT: P15 (Bit 15) */ -#define PORT5_OUT_P15_Msk \ - (0x8000UL) /*!< PORT5 OUT: P15 (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- PORT5_OMR --------------------------------- */ -#define PORT5_OMR_PS0_Pos (0UL) /*!< PORT5 OMR: PS0 (Bit 0) */ -#define PORT5_OMR_PS0_Msk \ - (0x1UL) /*!< PORT5 OMR: PS0 (Bitfield-Mask: 0x01) */ -#define PORT5_OMR_PS1_Pos (1UL) /*!< PORT5 OMR: PS1 (Bit 1) */ -#define PORT5_OMR_PS1_Msk \ - (0x2UL) /*!< PORT5 OMR: PS1 (Bitfield-Mask: 0x01) */ -#define PORT5_OMR_PS2_Pos (2UL) /*!< PORT5 OMR: PS2 (Bit 2) */ -#define PORT5_OMR_PS2_Msk \ - (0x4UL) /*!< PORT5 OMR: PS2 (Bitfield-Mask: 0x01) */ -#define PORT5_OMR_PS3_Pos (3UL) /*!< PORT5 OMR: PS3 (Bit 3) */ -#define PORT5_OMR_PS3_Msk \ - (0x8UL) /*!< PORT5 OMR: PS3 (Bitfield-Mask: 0x01) */ -#define PORT5_OMR_PS4_Pos (4UL) /*!< PORT5 OMR: PS4 (Bit 4) */ -#define PORT5_OMR_PS4_Msk \ - (0x10UL) /*!< PORT5 OMR: PS4 (Bitfield-Mask: 0x01) */ -#define PORT5_OMR_PS5_Pos (5UL) /*!< PORT5 OMR: PS5 (Bit 5) */ -#define PORT5_OMR_PS5_Msk \ - (0x20UL) /*!< PORT5 OMR: PS5 (Bitfield-Mask: 0x01) */ -#define PORT5_OMR_PS6_Pos (6UL) /*!< PORT5 OMR: PS6 (Bit 6) */ -#define PORT5_OMR_PS6_Msk \ - (0x40UL) /*!< PORT5 OMR: PS6 (Bitfield-Mask: 0x01) */ -#define PORT5_OMR_PS7_Pos (7UL) /*!< PORT5 OMR: PS7 (Bit 7) */ -#define PORT5_OMR_PS7_Msk \ - (0x80UL) /*!< PORT5 OMR: PS7 (Bitfield-Mask: 0x01) */ -#define PORT5_OMR_PS8_Pos (8UL) /*!< PORT5 OMR: PS8 (Bit 8) */ -#define PORT5_OMR_PS8_Msk \ - (0x100UL) /*!< PORT5 OMR: PS8 (Bitfield-Mask: 0x01) */ -#define PORT5_OMR_PS9_Pos (9UL) /*!< PORT5 OMR: PS9 (Bit 9) */ -#define PORT5_OMR_PS9_Msk \ - (0x200UL) /*!< PORT5 OMR: PS9 (Bitfield-Mask: 0x01) */ -#define PORT5_OMR_PS10_Pos \ - (10UL) /*!< PORT5 OMR: PS10 (Bit 10) */ -#define PORT5_OMR_PS10_Msk \ - (0x400UL) /*!< PORT5 OMR: PS10 (Bitfield-Mask: 0x01) */ -#define PORT5_OMR_PS11_Pos \ - (11UL) /*!< PORT5 OMR: PS11 (Bit 11) */ -#define PORT5_OMR_PS11_Msk \ - (0x800UL) /*!< PORT5 OMR: PS11 (Bitfield-Mask: 0x01) */ -#define PORT5_OMR_PS12_Pos \ - (12UL) /*!< PORT5 OMR: PS12 (Bit 12) */ -#define PORT5_OMR_PS12_Msk \ - (0x1000UL) /*!< PORT5 OMR: PS12 (Bitfield-Mask: 0x01) */ -#define PORT5_OMR_PS13_Pos \ - (13UL) /*!< PORT5 OMR: PS13 (Bit 13) */ -#define PORT5_OMR_PS13_Msk \ - (0x2000UL) /*!< PORT5 OMR: PS13 (Bitfield-Mask: 0x01) */ -#define PORT5_OMR_PS14_Pos \ - (14UL) /*!< PORT5 OMR: PS14 (Bit 14) */ -#define PORT5_OMR_PS14_Msk \ - (0x4000UL) /*!< PORT5 OMR: PS14 (Bitfield-Mask: 0x01) */ -#define PORT5_OMR_PS15_Pos \ - (15UL) /*!< PORT5 OMR: PS15 (Bit 15) */ -#define PORT5_OMR_PS15_Msk \ - (0x8000UL) /*!< PORT5 OMR: PS15 (Bitfield-Mask: 0x01) */ -#define PORT5_OMR_PR0_Pos (16UL) /*!< PORT5 OMR: PR0 (Bit 16) */ -#define PORT5_OMR_PR0_Msk \ - (0x10000UL) /*!< PORT5 OMR: PR0 (Bitfield-Mask: 0x01) */ -#define PORT5_OMR_PR1_Pos (17UL) /*!< PORT5 OMR: PR1 (Bit 17) */ -#define PORT5_OMR_PR1_Msk \ - (0x20000UL) /*!< PORT5 OMR: PR1 (Bitfield-Mask: 0x01) */ -#define PORT5_OMR_PR2_Pos (18UL) /*!< PORT5 OMR: PR2 (Bit 18) */ -#define PORT5_OMR_PR2_Msk \ - (0x40000UL) /*!< PORT5 OMR: PR2 (Bitfield-Mask: 0x01) */ -#define PORT5_OMR_PR3_Pos (19UL) /*!< PORT5 OMR: PR3 (Bit 19) */ -#define PORT5_OMR_PR3_Msk \ - (0x80000UL) /*!< PORT5 OMR: PR3 (Bitfield-Mask: 0x01) */ -#define PORT5_OMR_PR4_Pos (20UL) /*!< PORT5 OMR: PR4 (Bit 20) */ -#define PORT5_OMR_PR4_Msk \ - (0x100000UL) /*!< PORT5 OMR: PR4 (Bitfield-Mask: 0x01) */ -#define PORT5_OMR_PR5_Pos (21UL) /*!< PORT5 OMR: PR5 (Bit 21) */ -#define PORT5_OMR_PR5_Msk \ - (0x200000UL) /*!< PORT5 OMR: PR5 (Bitfield-Mask: 0x01) */ -#define PORT5_OMR_PR6_Pos (22UL) /*!< PORT5 OMR: PR6 (Bit 22) */ -#define PORT5_OMR_PR6_Msk \ - (0x400000UL) /*!< PORT5 OMR: PR6 (Bitfield-Mask: 0x01) */ -#define PORT5_OMR_PR7_Pos (23UL) /*!< PORT5 OMR: PR7 (Bit 23) */ -#define PORT5_OMR_PR7_Msk \ - (0x800000UL) /*!< PORT5 OMR: PR7 (Bitfield-Mask: 0x01) */ -#define PORT5_OMR_PR8_Pos (24UL) /*!< PORT5 OMR: PR8 (Bit 24) */ -#define PORT5_OMR_PR8_Msk \ - (0x1000000UL) /*!< PORT5 OMR: PR8 (Bitfield-Mask: 0x01) */ -#define PORT5_OMR_PR9_Pos (25UL) /*!< PORT5 OMR: PR9 (Bit 25) */ -#define PORT5_OMR_PR9_Msk \ - (0x2000000UL) /*!< PORT5 OMR: PR9 (Bitfield-Mask: 0x01) */ -#define PORT5_OMR_PR10_Pos \ - (26UL) /*!< PORT5 OMR: PR10 (Bit 26) */ -#define PORT5_OMR_PR10_Msk \ - (0x4000000UL) /*!< PORT5 OMR: PR10 (Bitfield-Mask: 0x01) */ -#define PORT5_OMR_PR11_Pos \ - (27UL) /*!< PORT5 OMR: PR11 (Bit 27) */ -#define PORT5_OMR_PR11_Msk \ - (0x8000000UL) /*!< PORT5 OMR: PR11 (Bitfield-Mask: 0x01) */ -#define PORT5_OMR_PR12_Pos \ - (28UL) /*!< PORT5 OMR: PR12 (Bit 28) */ -#define PORT5_OMR_PR12_Msk \ - (0x10000000UL) /*!< PORT5 OMR: PR12 (Bitfield-Mask: 0x01) */ -#define PORT5_OMR_PR13_Pos \ - (29UL) /*!< PORT5 OMR: PR13 (Bit 29) */ -#define PORT5_OMR_PR13_Msk \ - (0x20000000UL) /*!< PORT5 OMR: PR13 (Bitfield-Mask: 0x01) */ -#define PORT5_OMR_PR14_Pos \ - (30UL) /*!< PORT5 OMR: PR14 (Bit 30) */ -#define PORT5_OMR_PR14_Msk \ - (0x40000000UL) /*!< PORT5 OMR: PR14 (Bitfield-Mask: 0x01) */ -#define PORT5_OMR_PR15_Pos \ - (31UL) /*!< PORT5 OMR: PR15 (Bit 31) */ -#define PORT5_OMR_PR15_Msk \ - (0x80000000UL) /*!< PORT5 OMR: PR15 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- PORT5_IOCR0 -------------------------------- */ -#define PORT5_IOCR0_PC0_Pos \ - (3UL) /*!< PORT5 IOCR0: PC0 (Bit 3) */ -#define PORT5_IOCR0_PC0_Msk \ - (0xf8UL) /*!< PORT5 IOCR0: PC0 (Bitfield-Mask: 0x1f) */ -#define PORT5_IOCR0_PC1_Pos \ - (11UL) /*!< PORT5 IOCR0: PC1 (Bit 11) */ -#define PORT5_IOCR0_PC1_Msk \ - (0xf800UL) /*!< PORT5 IOCR0: PC1 (Bitfield-Mask: 0x1f) */ -#define PORT5_IOCR0_PC2_Pos \ - (19UL) /*!< PORT5 IOCR0: PC2 (Bit 19) */ -#define PORT5_IOCR0_PC2_Msk \ - (0xf80000UL) /*!< PORT5 IOCR0: PC2 (Bitfield-Mask: 0x1f) */ -#define PORT5_IOCR0_PC3_Pos \ - (27UL) /*!< PORT5 IOCR0: PC3 (Bit 27) */ -#define PORT5_IOCR0_PC3_Msk \ - (0xf8000000UL) /*!< PORT5 IOCR0: PC3 (Bitfield-Mask: 0x1f) */ - -/* --------------------------------- PORT5_IOCR4 -------------------------------- */ -#define PORT5_IOCR4_PC4_Pos \ - (3UL) /*!< PORT5 IOCR4: PC4 (Bit 3) */ -#define PORT5_IOCR4_PC4_Msk \ - (0xf8UL) /*!< PORT5 IOCR4: PC4 (Bitfield-Mask: 0x1f) */ -#define PORT5_IOCR4_PC5_Pos \ - (11UL) /*!< PORT5 IOCR4: PC5 (Bit 11) */ -#define PORT5_IOCR4_PC5_Msk \ - (0xf800UL) /*!< PORT5 IOCR4: PC5 (Bitfield-Mask: 0x1f) */ -#define PORT5_IOCR4_PC6_Pos \ - (19UL) /*!< PORT5 IOCR4: PC6 (Bit 19) */ -#define PORT5_IOCR4_PC6_Msk \ - (0xf80000UL) /*!< PORT5 IOCR4: PC6 (Bitfield-Mask: 0x1f) */ -#define PORT5_IOCR4_PC7_Pos \ - (27UL) /*!< PORT5 IOCR4: PC7 (Bit 27) */ -#define PORT5_IOCR4_PC7_Msk \ - (0xf8000000UL) /*!< PORT5 IOCR4: PC7 (Bitfield-Mask: 0x1f) */ - -/* ---------------------------------- PORT5_IN ---------------------------------- */ -#define PORT5_IN_P0_Pos (0UL) /*!< PORT5 IN: P0 (Bit 0) */ -#define PORT5_IN_P0_Msk (0x1UL) /*!< PORT5 IN: P0 (Bitfield-Mask: 0x01) */ -#define PORT5_IN_P1_Pos (1UL) /*!< PORT5 IN: P1 (Bit 1) */ -#define PORT5_IN_P1_Msk (0x2UL) /*!< PORT5 IN: P1 (Bitfield-Mask: 0x01) */ -#define PORT5_IN_P2_Pos (2UL) /*!< PORT5 IN: P2 (Bit 2) */ -#define PORT5_IN_P2_Msk (0x4UL) /*!< PORT5 IN: P2 (Bitfield-Mask: 0x01) */ -#define PORT5_IN_P3_Pos (3UL) /*!< PORT5 IN: P3 (Bit 3) */ -#define PORT5_IN_P3_Msk (0x8UL) /*!< PORT5 IN: P3 (Bitfield-Mask: 0x01) */ -#define PORT5_IN_P4_Pos (4UL) /*!< PORT5 IN: P4 (Bit 4) */ -#define PORT5_IN_P4_Msk (0x10UL) /*!< PORT5 IN: P4 (Bitfield-Mask: 0x01) */ -#define PORT5_IN_P5_Pos (5UL) /*!< PORT5 IN: P5 (Bit 5) */ -#define PORT5_IN_P5_Msk (0x20UL) /*!< PORT5 IN: P5 (Bitfield-Mask: 0x01) */ -#define PORT5_IN_P6_Pos (6UL) /*!< PORT5 IN: P6 (Bit 6) */ -#define PORT5_IN_P6_Msk (0x40UL) /*!< PORT5 IN: P6 (Bitfield-Mask: 0x01) */ -#define PORT5_IN_P7_Pos (7UL) /*!< PORT5 IN: P7 (Bit 7) */ -#define PORT5_IN_P7_Msk (0x80UL) /*!< PORT5 IN: P7 (Bitfield-Mask: 0x01) */ -#define PORT5_IN_P8_Pos (8UL) /*!< PORT5 IN: P8 (Bit 8) */ -#define PORT5_IN_P8_Msk \ - (0x100UL) /*!< PORT5 IN: P8 (Bitfield-Mask: 0x01) */ -#define PORT5_IN_P9_Pos (9UL) /*!< PORT5 IN: P9 (Bit 9) */ -#define PORT5_IN_P9_Msk \ - (0x200UL) /*!< PORT5 IN: P9 (Bitfield-Mask: 0x01) */ -#define PORT5_IN_P10_Pos (10UL) /*!< PORT5 IN: P10 (Bit 10) */ -#define PORT5_IN_P10_Msk \ - (0x400UL) /*!< PORT5 IN: P10 (Bitfield-Mask: 0x01) */ -#define PORT5_IN_P11_Pos (11UL) /*!< PORT5 IN: P11 (Bit 11) */ -#define PORT5_IN_P11_Msk \ - (0x800UL) /*!< PORT5 IN: P11 (Bitfield-Mask: 0x01) */ -#define PORT5_IN_P12_Pos (12UL) /*!< PORT5 IN: P12 (Bit 12) */ -#define PORT5_IN_P12_Msk \ - (0x1000UL) /*!< PORT5 IN: P12 (Bitfield-Mask: 0x01) */ -#define PORT5_IN_P13_Pos (13UL) /*!< PORT5 IN: P13 (Bit 13) */ -#define PORT5_IN_P13_Msk \ - (0x2000UL) /*!< PORT5 IN: P13 (Bitfield-Mask: 0x01) */ -#define PORT5_IN_P14_Pos (14UL) /*!< PORT5 IN: P14 (Bit 14) */ -#define PORT5_IN_P14_Msk \ - (0x4000UL) /*!< PORT5 IN: P14 (Bitfield-Mask: 0x01) */ -#define PORT5_IN_P15_Pos (15UL) /*!< PORT5 IN: P15 (Bit 15) */ -#define PORT5_IN_P15_Msk \ - (0x8000UL) /*!< PORT5 IN: P15 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- PORT5_PDR0 --------------------------------- */ -#define PORT5_PDR0_PD0_Pos (0UL) /*!< PORT5 PDR0: PD0 (Bit 0) */ -#define PORT5_PDR0_PD0_Msk \ - (0x7UL) /*!< PORT5 PDR0: PD0 (Bitfield-Mask: 0x07) */ -#define PORT5_PDR0_PD1_Pos (4UL) /*!< PORT5 PDR0: PD1 (Bit 4) */ -#define PORT5_PDR0_PD1_Msk \ - (0x70UL) /*!< PORT5 PDR0: PD1 (Bitfield-Mask: 0x07) */ -#define PORT5_PDR0_PD2_Pos (8UL) /*!< PORT5 PDR0: PD2 (Bit 8) */ -#define PORT5_PDR0_PD2_Msk \ - (0x700UL) /*!< PORT5 PDR0: PD2 (Bitfield-Mask: 0x07) */ -#define PORT5_PDR0_PD3_Pos \ - (12UL) /*!< PORT5 PDR0: PD3 (Bit 12) */ -#define PORT5_PDR0_PD3_Msk \ - (0x7000UL) /*!< PORT5 PDR0: PD3 (Bitfield-Mask: 0x07) */ -#define PORT5_PDR0_PD4_Pos \ - (16UL) /*!< PORT5 PDR0: PD4 (Bit 16) */ -#define PORT5_PDR0_PD4_Msk \ - (0x70000UL) /*!< PORT5 PDR0: PD4 (Bitfield-Mask: 0x07) */ -#define PORT5_PDR0_PD5_Pos \ - (20UL) /*!< PORT5 PDR0: PD5 (Bit 20) */ -#define PORT5_PDR0_PD5_Msk \ - (0x700000UL) /*!< PORT5 PDR0: PD5 (Bitfield-Mask: 0x07) */ -#define PORT5_PDR0_PD6_Pos \ - (24UL) /*!< PORT5 PDR0: PD6 (Bit 24) */ -#define PORT5_PDR0_PD6_Msk \ - (0x7000000UL) /*!< PORT5 PDR0: PD6 (Bitfield-Mask: 0x07) */ -#define PORT5_PDR0_PD7_Pos \ - (28UL) /*!< PORT5 PDR0: PD7 (Bit 28) */ -#define PORT5_PDR0_PD7_Msk \ - (0x70000000UL) /*!< PORT5 PDR0: PD7 (Bitfield-Mask: 0x07) */ - -/* --------------------------------- PORT5_PDISC -------------------------------- */ -#define PORT5_PDISC_PDIS0_Pos \ - (0UL) /*!< PORT5 PDISC: PDIS0 (Bit 0) */ -#define PORT5_PDISC_PDIS0_Msk \ - (0x1UL) /*!< PORT5 PDISC: PDIS0 (Bitfield-Mask: 0x01) */ -#define PORT5_PDISC_PDIS1_Pos \ - (1UL) /*!< PORT5 PDISC: PDIS1 (Bit 1) */ -#define PORT5_PDISC_PDIS1_Msk \ - (0x2UL) /*!< PORT5 PDISC: PDIS1 (Bitfield-Mask: 0x01) */ -#define PORT5_PDISC_PDIS2_Pos \ - (2UL) /*!< PORT5 PDISC: PDIS2 (Bit 2) */ -#define PORT5_PDISC_PDIS2_Msk \ - (0x4UL) /*!< PORT5 PDISC: PDIS2 (Bitfield-Mask: 0x01) */ -#define PORT5_PDISC_PDIS3_Pos \ - (3UL) /*!< PORT5 PDISC: PDIS3 (Bit 3) */ -#define PORT5_PDISC_PDIS3_Msk \ - (0x8UL) /*!< PORT5 PDISC: PDIS3 (Bitfield-Mask: 0x01) */ -#define PORT5_PDISC_PDIS4_Pos \ - (4UL) /*!< PORT5 PDISC: PDIS4 (Bit 4) */ -#define PORT5_PDISC_PDIS4_Msk \ - (0x10UL) /*!< PORT5 PDISC: PDIS4 (Bitfield-Mask: 0x01) */ -#define PORT5_PDISC_PDIS5_Pos \ - (5UL) /*!< PORT5 PDISC: PDIS5 (Bit 5) */ -#define PORT5_PDISC_PDIS5_Msk \ - (0x20UL) /*!< PORT5 PDISC: PDIS5 (Bitfield-Mask: 0x01) */ -#define PORT5_PDISC_PDIS6_Pos \ - (6UL) /*!< PORT5 PDISC: PDIS6 (Bit 6) */ -#define PORT5_PDISC_PDIS6_Msk \ - (0x40UL) /*!< PORT5 PDISC: PDIS6 (Bitfield-Mask: 0x01) */ -#define PORT5_PDISC_PDIS7_Pos \ - (7UL) /*!< PORT5 PDISC: PDIS7 (Bit 7) */ -#define PORT5_PDISC_PDIS7_Msk \ - (0x80UL) /*!< PORT5 PDISC: PDIS7 (Bitfield-Mask: 0x01) */ -#define PORT5_PDISC_PDIS8_Pos \ - (8UL) /*!< PORT5 PDISC: PDIS8 (Bit 8) */ -#define PORT5_PDISC_PDIS8_Msk \ - (0x100UL) /*!< PORT5 PDISC: PDIS8 (Bitfield-Mask: 0x01) */ -#define PORT5_PDISC_PDIS9_Pos \ - (9UL) /*!< PORT5 PDISC: PDIS9 (Bit 9) */ -#define PORT5_PDISC_PDIS9_Msk \ - (0x200UL) /*!< PORT5 PDISC: PDIS9 (Bitfield-Mask: 0x01) */ -#define PORT5_PDISC_PDIS10_Pos \ - (10UL) /*!< PORT5 PDISC: PDIS10 (Bit 10) */ -#define PORT5_PDISC_PDIS10_Msk \ - (0x400UL) /*!< PORT5 PDISC: PDIS10 (Bitfield-Mask: 0x01) */ -#define PORT5_PDISC_PDIS11_Pos \ - (11UL) /*!< PORT5 PDISC: PDIS11 (Bit 11) */ -#define PORT5_PDISC_PDIS11_Msk \ - (0x800UL) /*!< PORT5 PDISC: PDIS11 (Bitfield-Mask: 0x01) */ -#define PORT5_PDISC_PDIS12_Pos \ - (12UL) /*!< PORT5 PDISC: PDIS12 (Bit 12) */ -#define PORT5_PDISC_PDIS12_Msk \ - (0x1000UL) /*!< PORT5 PDISC: PDIS12 (Bitfield-Mask: 0x01) */ -#define PORT5_PDISC_PDIS13_Pos \ - (13UL) /*!< PORT5 PDISC: PDIS13 (Bit 13) */ -#define PORT5_PDISC_PDIS13_Msk \ - (0x2000UL) /*!< PORT5 PDISC: PDIS13 (Bitfield-Mask: 0x01) */ -#define PORT5_PDISC_PDIS14_Pos \ - (14UL) /*!< PORT5 PDISC: PDIS14 (Bit 14) */ -#define PORT5_PDISC_PDIS14_Msk \ - (0x4000UL) /*!< PORT5 PDISC: PDIS14 (Bitfield-Mask: 0x01) */ -#define PORT5_PDISC_PDIS15_Pos \ - (15UL) /*!< PORT5 PDISC: PDIS15 (Bit 15) */ -#define PORT5_PDISC_PDIS15_Msk \ - (0x8000UL) /*!< PORT5 PDISC: PDIS15 (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- PORT5_PPS --------------------------------- */ -#define PORT5_PPS_PPS0_Pos (0UL) /*!< PORT5 PPS: PPS0 (Bit 0) */ -#define PORT5_PPS_PPS0_Msk \ - (0x1UL) /*!< PORT5 PPS: PPS0 (Bitfield-Mask: 0x01) */ -#define PORT5_PPS_PPS1_Pos (1UL) /*!< PORT5 PPS: PPS1 (Bit 1) */ -#define PORT5_PPS_PPS1_Msk \ - (0x2UL) /*!< PORT5 PPS: PPS1 (Bitfield-Mask: 0x01) */ -#define PORT5_PPS_PPS2_Pos (2UL) /*!< PORT5 PPS: PPS2 (Bit 2) */ -#define PORT5_PPS_PPS2_Msk \ - (0x4UL) /*!< PORT5 PPS: PPS2 (Bitfield-Mask: 0x01) */ -#define PORT5_PPS_PPS3_Pos (3UL) /*!< PORT5 PPS: PPS3 (Bit 3) */ -#define PORT5_PPS_PPS3_Msk \ - (0x8UL) /*!< PORT5 PPS: PPS3 (Bitfield-Mask: 0x01) */ -#define PORT5_PPS_PPS4_Pos (4UL) /*!< PORT5 PPS: PPS4 (Bit 4) */ -#define PORT5_PPS_PPS4_Msk \ - (0x10UL) /*!< PORT5 PPS: PPS4 (Bitfield-Mask: 0x01) */ -#define PORT5_PPS_PPS5_Pos (5UL) /*!< PORT5 PPS: PPS5 (Bit 5) */ -#define PORT5_PPS_PPS5_Msk \ - (0x20UL) /*!< PORT5 PPS: PPS5 (Bitfield-Mask: 0x01) */ -#define PORT5_PPS_PPS6_Pos (6UL) /*!< PORT5 PPS: PPS6 (Bit 6) */ -#define PORT5_PPS_PPS6_Msk \ - (0x40UL) /*!< PORT5 PPS: PPS6 (Bitfield-Mask: 0x01) */ -#define PORT5_PPS_PPS7_Pos (7UL) /*!< PORT5 PPS: PPS7 (Bit 7) */ -#define PORT5_PPS_PPS7_Msk \ - (0x80UL) /*!< PORT5 PPS: PPS7 (Bitfield-Mask: 0x01) */ -#define PORT5_PPS_PPS8_Pos (8UL) /*!< PORT5 PPS: PPS8 (Bit 8) */ -#define PORT5_PPS_PPS8_Msk \ - (0x100UL) /*!< PORT5 PPS: PPS8 (Bitfield-Mask: 0x01) */ -#define PORT5_PPS_PPS9_Pos (9UL) /*!< PORT5 PPS: PPS9 (Bit 9) */ -#define PORT5_PPS_PPS9_Msk \ - (0x200UL) /*!< PORT5 PPS: PPS9 (Bitfield-Mask: 0x01) */ -#define PORT5_PPS_PPS10_Pos \ - (10UL) /*!< PORT5 PPS: PPS10 (Bit 10) */ -#define PORT5_PPS_PPS10_Msk \ - (0x400UL) /*!< PORT5 PPS: PPS10 (Bitfield-Mask: 0x01) */ -#define PORT5_PPS_PPS11_Pos \ - (11UL) /*!< PORT5 PPS: PPS11 (Bit 11) */ -#define PORT5_PPS_PPS11_Msk \ - (0x800UL) /*!< PORT5 PPS: PPS11 (Bitfield-Mask: 0x01) */ -#define PORT5_PPS_PPS12_Pos \ - (12UL) /*!< PORT5 PPS: PPS12 (Bit 12) */ -#define PORT5_PPS_PPS12_Msk \ - (0x1000UL) /*!< PORT5 PPS: PPS12 (Bitfield-Mask: 0x01) */ -#define PORT5_PPS_PPS13_Pos \ - (13UL) /*!< PORT5 PPS: PPS13 (Bit 13) */ -#define PORT5_PPS_PPS13_Msk \ - (0x2000UL) /*!< PORT5 PPS: PPS13 (Bitfield-Mask: 0x01) */ -#define PORT5_PPS_PPS14_Pos \ - (14UL) /*!< PORT5 PPS: PPS14 (Bit 14) */ -#define PORT5_PPS_PPS14_Msk \ - (0x4000UL) /*!< PORT5 PPS: PPS14 (Bitfield-Mask: 0x01) */ -#define PORT5_PPS_PPS15_Pos \ - (15UL) /*!< PORT5 PPS: PPS15 (Bit 15) */ -#define PORT5_PPS_PPS15_Msk \ - (0x8000UL) /*!< PORT5 PPS: PPS15 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- PORT5_HWSEL -------------------------------- */ -#define PORT5_HWSEL_HW0_Pos \ - (0UL) /*!< PORT5 HWSEL: HW0 (Bit 0) */ -#define PORT5_HWSEL_HW0_Msk \ - (0x3UL) /*!< PORT5 HWSEL: HW0 (Bitfield-Mask: 0x03) */ -#define PORT5_HWSEL_HW1_Pos \ - (2UL) /*!< PORT5 HWSEL: HW1 (Bit 2) */ -#define PORT5_HWSEL_HW1_Msk \ - (0xcUL) /*!< PORT5 HWSEL: HW1 (Bitfield-Mask: 0x03) */ -#define PORT5_HWSEL_HW2_Pos \ - (4UL) /*!< PORT5 HWSEL: HW2 (Bit 4) */ -#define PORT5_HWSEL_HW2_Msk \ - (0x30UL) /*!< PORT5 HWSEL: HW2 (Bitfield-Mask: 0x03) */ -#define PORT5_HWSEL_HW3_Pos \ - (6UL) /*!< PORT5 HWSEL: HW3 (Bit 6) */ -#define PORT5_HWSEL_HW3_Msk \ - (0xc0UL) /*!< PORT5 HWSEL: HW3 (Bitfield-Mask: 0x03) */ -#define PORT5_HWSEL_HW4_Pos \ - (8UL) /*!< PORT5 HWSEL: HW4 (Bit 8) */ -#define PORT5_HWSEL_HW4_Msk \ - (0x300UL) /*!< PORT5 HWSEL: HW4 (Bitfield-Mask: 0x03) */ -#define PORT5_HWSEL_HW5_Pos \ - (10UL) /*!< PORT5 HWSEL: HW5 (Bit 10) */ -#define PORT5_HWSEL_HW5_Msk \ - (0xc00UL) /*!< PORT5 HWSEL: HW5 (Bitfield-Mask: 0x03) */ -#define PORT5_HWSEL_HW6_Pos \ - (12UL) /*!< PORT5 HWSEL: HW6 (Bit 12) */ -#define PORT5_HWSEL_HW6_Msk \ - (0x3000UL) /*!< PORT5 HWSEL: HW6 (Bitfield-Mask: 0x03) */ -#define PORT5_HWSEL_HW7_Pos \ - (14UL) /*!< PORT5 HWSEL: HW7 (Bit 14) */ -#define PORT5_HWSEL_HW7_Msk \ - (0xc000UL) /*!< PORT5 HWSEL: HW7 (Bitfield-Mask: 0x03) */ -#define PORT5_HWSEL_HW8_Pos \ - (16UL) /*!< PORT5 HWSEL: HW8 (Bit 16) */ -#define PORT5_HWSEL_HW8_Msk \ - (0x30000UL) /*!< PORT5 HWSEL: HW8 (Bitfield-Mask: 0x03) */ -#define PORT5_HWSEL_HW9_Pos \ - (18UL) /*!< PORT5 HWSEL: HW9 (Bit 18) */ -#define PORT5_HWSEL_HW9_Msk \ - (0xc0000UL) /*!< PORT5 HWSEL: HW9 (Bitfield-Mask: 0x03) */ -#define PORT5_HWSEL_HW10_Pos \ - (20UL) /*!< PORT5 HWSEL: HW10 (Bit 20) */ -#define PORT5_HWSEL_HW10_Msk \ - (0x300000UL) /*!< PORT5 HWSEL: HW10 (Bitfield-Mask: 0x03) */ -#define PORT5_HWSEL_HW11_Pos \ - (22UL) /*!< PORT5 HWSEL: HW11 (Bit 22) */ -#define PORT5_HWSEL_HW11_Msk \ - (0xc00000UL) /*!< PORT5 HWSEL: HW11 (Bitfield-Mask: 0x03) */ -#define PORT5_HWSEL_HW12_Pos \ - (24UL) /*!< PORT5 HWSEL: HW12 (Bit 24) */ -#define PORT5_HWSEL_HW12_Msk \ - (0x3000000UL) /*!< PORT5 HWSEL: HW12 (Bitfield-Mask: 0x03) */ -#define PORT5_HWSEL_HW13_Pos \ - (26UL) /*!< PORT5 HWSEL: HW13 (Bit 26) */ -#define PORT5_HWSEL_HW13_Msk \ - (0xc000000UL) /*!< PORT5 HWSEL: HW13 (Bitfield-Mask: 0x03) */ -#define PORT5_HWSEL_HW14_Pos \ - (28UL) /*!< PORT5 HWSEL: HW14 (Bit 28) */ -#define PORT5_HWSEL_HW14_Msk \ - (0x30000000UL) /*!< PORT5 HWSEL: HW14 (Bitfield-Mask: 0x03) */ -#define PORT5_HWSEL_HW15_Pos \ - (30UL) /*!< PORT5 HWSEL: HW15 (Bit 30) */ -#define PORT5_HWSEL_HW15_Msk \ - (0xc0000000UL) /*!< PORT5 HWSEL: HW15 (Bitfield-Mask: 0x03) */ - -/* ================================================================================ */ -/* ================ struct 'PORT14' Position & Mask ================ */ -/* ================================================================================ */ - -/* --------------------------------- PORT14_OUT --------------------------------- */ -#define PORT14_OUT_P0_Pos (0UL) /*!< PORT14 OUT: P0 (Bit 0) */ -#define PORT14_OUT_P0_Msk \ - (0x1UL) /*!< PORT14 OUT: P0 (Bitfield-Mask: 0x01) */ -#define PORT14_OUT_P1_Pos (1UL) /*!< PORT14 OUT: P1 (Bit 1) */ -#define PORT14_OUT_P1_Msk \ - (0x2UL) /*!< PORT14 OUT: P1 (Bitfield-Mask: 0x01) */ -#define PORT14_OUT_P2_Pos (2UL) /*!< PORT14 OUT: P2 (Bit 2) */ -#define PORT14_OUT_P2_Msk \ - (0x4UL) /*!< PORT14 OUT: P2 (Bitfield-Mask: 0x01) */ -#define PORT14_OUT_P3_Pos (3UL) /*!< PORT14 OUT: P3 (Bit 3) */ -#define PORT14_OUT_P3_Msk \ - (0x8UL) /*!< PORT14 OUT: P3 (Bitfield-Mask: 0x01) */ -#define PORT14_OUT_P4_Pos (4UL) /*!< PORT14 OUT: P4 (Bit 4) */ -#define PORT14_OUT_P4_Msk \ - (0x10UL) /*!< PORT14 OUT: P4 (Bitfield-Mask: 0x01) */ -#define PORT14_OUT_P5_Pos (5UL) /*!< PORT14 OUT: P5 (Bit 5) */ -#define PORT14_OUT_P5_Msk \ - (0x20UL) /*!< PORT14 OUT: P5 (Bitfield-Mask: 0x01) */ -#define PORT14_OUT_P6_Pos (6UL) /*!< PORT14 OUT: P6 (Bit 6) */ -#define PORT14_OUT_P6_Msk \ - (0x40UL) /*!< PORT14 OUT: P6 (Bitfield-Mask: 0x01) */ -#define PORT14_OUT_P7_Pos (7UL) /*!< PORT14 OUT: P7 (Bit 7) */ -#define PORT14_OUT_P7_Msk \ - (0x80UL) /*!< PORT14 OUT: P7 (Bitfield-Mask: 0x01) */ -#define PORT14_OUT_P8_Pos (8UL) /*!< PORT14 OUT: P8 (Bit 8) */ -#define PORT14_OUT_P8_Msk \ - (0x100UL) /*!< PORT14 OUT: P8 (Bitfield-Mask: 0x01) */ -#define PORT14_OUT_P9_Pos (9UL) /*!< PORT14 OUT: P9 (Bit 9) */ -#define PORT14_OUT_P9_Msk \ - (0x200UL) /*!< PORT14 OUT: P9 (Bitfield-Mask: 0x01) */ -#define PORT14_OUT_P10_Pos \ - (10UL) /*!< PORT14 OUT: P10 (Bit 10) */ -#define PORT14_OUT_P10_Msk \ - (0x400UL) /*!< PORT14 OUT: P10 (Bitfield-Mask: 0x01) */ -#define PORT14_OUT_P11_Pos \ - (11UL) /*!< PORT14 OUT: P11 (Bit 11) */ -#define PORT14_OUT_P11_Msk \ - (0x800UL) /*!< PORT14 OUT: P11 (Bitfield-Mask: 0x01) */ -#define PORT14_OUT_P12_Pos \ - (12UL) /*!< PORT14 OUT: P12 (Bit 12) */ -#define PORT14_OUT_P12_Msk \ - (0x1000UL) /*!< PORT14 OUT: P12 (Bitfield-Mask: 0x01) */ -#define PORT14_OUT_P13_Pos \ - (13UL) /*!< PORT14 OUT: P13 (Bit 13) */ -#define PORT14_OUT_P13_Msk \ - (0x2000UL) /*!< PORT14 OUT: P13 (Bitfield-Mask: 0x01) */ -#define PORT14_OUT_P14_Pos \ - (14UL) /*!< PORT14 OUT: P14 (Bit 14) */ -#define PORT14_OUT_P14_Msk \ - (0x4000UL) /*!< PORT14 OUT: P14 (Bitfield-Mask: 0x01) */ -#define PORT14_OUT_P15_Pos \ - (15UL) /*!< PORT14 OUT: P15 (Bit 15) */ -#define PORT14_OUT_P15_Msk \ - (0x8000UL) /*!< PORT14 OUT: P15 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- PORT14_OMR --------------------------------- */ -#define PORT14_OMR_PS0_Pos (0UL) /*!< PORT14 OMR: PS0 (Bit 0) */ -#define PORT14_OMR_PS0_Msk \ - (0x1UL) /*!< PORT14 OMR: PS0 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PS1_Pos (1UL) /*!< PORT14 OMR: PS1 (Bit 1) */ -#define PORT14_OMR_PS1_Msk \ - (0x2UL) /*!< PORT14 OMR: PS1 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PS2_Pos (2UL) /*!< PORT14 OMR: PS2 (Bit 2) */ -#define PORT14_OMR_PS2_Msk \ - (0x4UL) /*!< PORT14 OMR: PS2 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PS3_Pos (3UL) /*!< PORT14 OMR: PS3 (Bit 3) */ -#define PORT14_OMR_PS3_Msk \ - (0x8UL) /*!< PORT14 OMR: PS3 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PS4_Pos (4UL) /*!< PORT14 OMR: PS4 (Bit 4) */ -#define PORT14_OMR_PS4_Msk \ - (0x10UL) /*!< PORT14 OMR: PS4 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PS5_Pos (5UL) /*!< PORT14 OMR: PS5 (Bit 5) */ -#define PORT14_OMR_PS5_Msk \ - (0x20UL) /*!< PORT14 OMR: PS5 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PS6_Pos (6UL) /*!< PORT14 OMR: PS6 (Bit 6) */ -#define PORT14_OMR_PS6_Msk \ - (0x40UL) /*!< PORT14 OMR: PS6 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PS7_Pos (7UL) /*!< PORT14 OMR: PS7 (Bit 7) */ -#define PORT14_OMR_PS7_Msk \ - (0x80UL) /*!< PORT14 OMR: PS7 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PS8_Pos (8UL) /*!< PORT14 OMR: PS8 (Bit 8) */ -#define PORT14_OMR_PS8_Msk \ - (0x100UL) /*!< PORT14 OMR: PS8 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PS9_Pos (9UL) /*!< PORT14 OMR: PS9 (Bit 9) */ -#define PORT14_OMR_PS9_Msk \ - (0x200UL) /*!< PORT14 OMR: PS9 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PS10_Pos \ - (10UL) /*!< PORT14 OMR: PS10 (Bit 10) */ -#define PORT14_OMR_PS10_Msk \ - (0x400UL) /*!< PORT14 OMR: PS10 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PS11_Pos \ - (11UL) /*!< PORT14 OMR: PS11 (Bit 11) */ -#define PORT14_OMR_PS11_Msk \ - (0x800UL) /*!< PORT14 OMR: PS11 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PS12_Pos \ - (12UL) /*!< PORT14 OMR: PS12 (Bit 12) */ -#define PORT14_OMR_PS12_Msk \ - (0x1000UL) /*!< PORT14 OMR: PS12 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PS13_Pos \ - (13UL) /*!< PORT14 OMR: PS13 (Bit 13) */ -#define PORT14_OMR_PS13_Msk \ - (0x2000UL) /*!< PORT14 OMR: PS13 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PS14_Pos \ - (14UL) /*!< PORT14 OMR: PS14 (Bit 14) */ -#define PORT14_OMR_PS14_Msk \ - (0x4000UL) /*!< PORT14 OMR: PS14 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PS15_Pos \ - (15UL) /*!< PORT14 OMR: PS15 (Bit 15) */ -#define PORT14_OMR_PS15_Msk \ - (0x8000UL) /*!< PORT14 OMR: PS15 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PR0_Pos \ - (16UL) /*!< PORT14 OMR: PR0 (Bit 16) */ -#define PORT14_OMR_PR0_Msk \ - (0x10000UL) /*!< PORT14 OMR: PR0 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PR1_Pos \ - (17UL) /*!< PORT14 OMR: PR1 (Bit 17) */ -#define PORT14_OMR_PR1_Msk \ - (0x20000UL) /*!< PORT14 OMR: PR1 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PR2_Pos \ - (18UL) /*!< PORT14 OMR: PR2 (Bit 18) */ -#define PORT14_OMR_PR2_Msk \ - (0x40000UL) /*!< PORT14 OMR: PR2 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PR3_Pos \ - (19UL) /*!< PORT14 OMR: PR3 (Bit 19) */ -#define PORT14_OMR_PR3_Msk \ - (0x80000UL) /*!< PORT14 OMR: PR3 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PR4_Pos \ - (20UL) /*!< PORT14 OMR: PR4 (Bit 20) */ -#define PORT14_OMR_PR4_Msk \ - (0x100000UL) /*!< PORT14 OMR: PR4 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PR5_Pos \ - (21UL) /*!< PORT14 OMR: PR5 (Bit 21) */ -#define PORT14_OMR_PR5_Msk \ - (0x200000UL) /*!< PORT14 OMR: PR5 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PR6_Pos \ - (22UL) /*!< PORT14 OMR: PR6 (Bit 22) */ -#define PORT14_OMR_PR6_Msk \ - (0x400000UL) /*!< PORT14 OMR: PR6 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PR7_Pos \ - (23UL) /*!< PORT14 OMR: PR7 (Bit 23) */ -#define PORT14_OMR_PR7_Msk \ - (0x800000UL) /*!< PORT14 OMR: PR7 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PR8_Pos \ - (24UL) /*!< PORT14 OMR: PR8 (Bit 24) */ -#define PORT14_OMR_PR8_Msk \ - (0x1000000UL) /*!< PORT14 OMR: PR8 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PR9_Pos \ - (25UL) /*!< PORT14 OMR: PR9 (Bit 25) */ -#define PORT14_OMR_PR9_Msk \ - (0x2000000UL) /*!< PORT14 OMR: PR9 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PR10_Pos \ - (26UL) /*!< PORT14 OMR: PR10 (Bit 26) */ -#define PORT14_OMR_PR10_Msk \ - (0x4000000UL) /*!< PORT14 OMR: PR10 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PR11_Pos \ - (27UL) /*!< PORT14 OMR: PR11 (Bit 27) */ -#define PORT14_OMR_PR11_Msk \ - (0x8000000UL) /*!< PORT14 OMR: PR11 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PR12_Pos \ - (28UL) /*!< PORT14 OMR: PR12 (Bit 28) */ -#define PORT14_OMR_PR12_Msk \ - (0x10000000UL) /*!< PORT14 OMR: PR12 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PR13_Pos \ - (29UL) /*!< PORT14 OMR: PR13 (Bit 29) */ -#define PORT14_OMR_PR13_Msk \ - (0x20000000UL) /*!< PORT14 OMR: PR13 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PR14_Pos \ - (30UL) /*!< PORT14 OMR: PR14 (Bit 30) */ -#define PORT14_OMR_PR14_Msk \ - (0x40000000UL) /*!< PORT14 OMR: PR14 (Bitfield-Mask: 0x01) */ -#define PORT14_OMR_PR15_Pos \ - (31UL) /*!< PORT14 OMR: PR15 (Bit 31) */ -#define PORT14_OMR_PR15_Msk \ - (0x80000000UL) /*!< PORT14 OMR: PR15 (Bitfield-Mask: 0x01) */ - -/* -------------------------------- PORT14_IOCR0 -------------------------------- */ -#define PORT14_IOCR0_PC0_Pos \ - (3UL) /*!< PORT14 IOCR0: PC0 (Bit 3) */ -#define PORT14_IOCR0_PC0_Msk \ - (0xf8UL) /*!< PORT14 IOCR0: PC0 (Bitfield-Mask: 0x1f) */ -#define PORT14_IOCR0_PC1_Pos \ - (11UL) /*!< PORT14 IOCR0: PC1 (Bit 11) */ -#define PORT14_IOCR0_PC1_Msk \ - (0xf800UL) /*!< PORT14 IOCR0: PC1 (Bitfield-Mask: 0x1f) */ -#define PORT14_IOCR0_PC2_Pos \ - (19UL) /*!< PORT14 IOCR0: PC2 (Bit 19) */ -#define PORT14_IOCR0_PC2_Msk \ - (0xf80000UL) /*!< PORT14 IOCR0: PC2 (Bitfield-Mask: 0x1f) */ -#define PORT14_IOCR0_PC3_Pos \ - (27UL) /*!< PORT14 IOCR0: PC3 (Bit 27) */ -#define PORT14_IOCR0_PC3_Msk \ - (0xf8000000UL) /*!< PORT14 IOCR0: PC3 (Bitfield-Mask: 0x1f) */ - -/* -------------------------------- PORT14_IOCR4 -------------------------------- */ -#define PORT14_IOCR4_PC4_Pos \ - (3UL) /*!< PORT14 IOCR4: PC4 (Bit 3) */ -#define PORT14_IOCR4_PC4_Msk \ - (0xf8UL) /*!< PORT14 IOCR4: PC4 (Bitfield-Mask: 0x1f) */ -#define PORT14_IOCR4_PC5_Pos \ - (11UL) /*!< PORT14 IOCR4: PC5 (Bit 11) */ -#define PORT14_IOCR4_PC5_Msk \ - (0xf800UL) /*!< PORT14 IOCR4: PC5 (Bitfield-Mask: 0x1f) */ -#define PORT14_IOCR4_PC6_Pos \ - (19UL) /*!< PORT14 IOCR4: PC6 (Bit 19) */ -#define PORT14_IOCR4_PC6_Msk \ - (0xf80000UL) /*!< PORT14 IOCR4: PC6 (Bitfield-Mask: 0x1f) */ -#define PORT14_IOCR4_PC7_Pos \ - (27UL) /*!< PORT14 IOCR4: PC7 (Bit 27) */ -#define PORT14_IOCR4_PC7_Msk \ - (0xf8000000UL) /*!< PORT14 IOCR4: PC7 (Bitfield-Mask: 0x1f) */ - -/* -------------------------------- PORT14_IOCR8 -------------------------------- */ -#define PORT14_IOCR8_PC8_Pos \ - (3UL) /*!< PORT14 IOCR8: PC8 (Bit 3) */ -#define PORT14_IOCR8_PC8_Msk \ - (0xf8UL) /*!< PORT14 IOCR8: PC8 (Bitfield-Mask: 0x1f) */ -#define PORT14_IOCR8_PC9_Pos \ - (11UL) /*!< PORT14 IOCR8: PC9 (Bit 11) */ -#define PORT14_IOCR8_PC9_Msk \ - (0xf800UL) /*!< PORT14 IOCR8: PC9 (Bitfield-Mask: 0x1f) */ -#define PORT14_IOCR8_PC10_Pos \ - (19UL) /*!< PORT14 IOCR8: PC10 (Bit 19) */ -#define PORT14_IOCR8_PC10_Msk \ - (0xf80000UL) /*!< PORT14 IOCR8: PC10 (Bitfield-Mask: 0x1f) */ -#define PORT14_IOCR8_PC11_Pos \ - (27UL) /*!< PORT14 IOCR8: PC11 (Bit 27) */ -#define PORT14_IOCR8_PC11_Msk \ - (0xf8000000UL) /*!< PORT14 IOCR8: PC11 (Bitfield-Mask: 0x1f) */ - -/* -------------------------------- PORT14_IOCR12 ------------------------------- */ -#define PORT14_IOCR12_PC12_Pos \ - (3UL) /*!< PORT14 IOCR12: PC12 (Bit 3) */ -#define PORT14_IOCR12_PC12_Msk \ - (0xf8UL) /*!< PORT14 IOCR12: PC12 (Bitfield-Mask: 0x1f) */ -#define PORT14_IOCR12_PC13_Pos \ - (11UL) /*!< PORT14 IOCR12: PC13 (Bit 11) */ -#define PORT14_IOCR12_PC13_Msk \ - (0xf800UL) /*!< PORT14 IOCR12: PC13 (Bitfield-Mask: 0x1f) */ -#define PORT14_IOCR12_PC14_Pos \ - (19UL) /*!< PORT14 IOCR12: PC14 (Bit 19) */ -#define PORT14_IOCR12_PC14_Msk \ - (0xf80000UL) /*!< PORT14 IOCR12: PC14 (Bitfield-Mask: 0x1f) */ -#define PORT14_IOCR12_PC15_Pos \ - (27UL) /*!< PORT14 IOCR12: PC15 (Bit 27) */ -#define PORT14_IOCR12_PC15_Msk \ - (0xf8000000UL) /*!< PORT14 IOCR12: PC15 (Bitfield-Mask: 0x1f) */ - -/* ---------------------------------- PORT14_IN --------------------------------- */ -#define PORT14_IN_P0_Pos (0UL) /*!< PORT14 IN: P0 (Bit 0) */ -#define PORT14_IN_P0_Msk (0x1UL) /*!< PORT14 IN: P0 (Bitfield-Mask: 0x01) */ -#define PORT14_IN_P1_Pos (1UL) /*!< PORT14 IN: P1 (Bit 1) */ -#define PORT14_IN_P1_Msk (0x2UL) /*!< PORT14 IN: P1 (Bitfield-Mask: 0x01) */ -#define PORT14_IN_P2_Pos (2UL) /*!< PORT14 IN: P2 (Bit 2) */ -#define PORT14_IN_P2_Msk (0x4UL) /*!< PORT14 IN: P2 (Bitfield-Mask: 0x01) */ -#define PORT14_IN_P3_Pos (3UL) /*!< PORT14 IN: P3 (Bit 3) */ -#define PORT14_IN_P3_Msk (0x8UL) /*!< PORT14 IN: P3 (Bitfield-Mask: 0x01) */ -#define PORT14_IN_P4_Pos (4UL) /*!< PORT14 IN: P4 (Bit 4) */ -#define PORT14_IN_P4_Msk \ - (0x10UL) /*!< PORT14 IN: P4 (Bitfield-Mask: 0x01) */ -#define PORT14_IN_P5_Pos (5UL) /*!< PORT14 IN: P5 (Bit 5) */ -#define PORT14_IN_P5_Msk \ - (0x20UL) /*!< PORT14 IN: P5 (Bitfield-Mask: 0x01) */ -#define PORT14_IN_P6_Pos (6UL) /*!< PORT14 IN: P6 (Bit 6) */ -#define PORT14_IN_P6_Msk \ - (0x40UL) /*!< PORT14 IN: P6 (Bitfield-Mask: 0x01) */ -#define PORT14_IN_P7_Pos (7UL) /*!< PORT14 IN: P7 (Bit 7) */ -#define PORT14_IN_P7_Msk \ - (0x80UL) /*!< PORT14 IN: P7 (Bitfield-Mask: 0x01) */ -#define PORT14_IN_P8_Pos (8UL) /*!< PORT14 IN: P8 (Bit 8) */ -#define PORT14_IN_P8_Msk \ - (0x100UL) /*!< PORT14 IN: P8 (Bitfield-Mask: 0x01) */ -#define PORT14_IN_P9_Pos (9UL) /*!< PORT14 IN: P9 (Bit 9) */ -#define PORT14_IN_P9_Msk \ - (0x200UL) /*!< PORT14 IN: P9 (Bitfield-Mask: 0x01) */ -#define PORT14_IN_P10_Pos (10UL) /*!< PORT14 IN: P10 (Bit 10) */ -#define PORT14_IN_P10_Msk \ - (0x400UL) /*!< PORT14 IN: P10 (Bitfield-Mask: 0x01) */ -#define PORT14_IN_P11_Pos (11UL) /*!< PORT14 IN: P11 (Bit 11) */ -#define PORT14_IN_P11_Msk \ - (0x800UL) /*!< PORT14 IN: P11 (Bitfield-Mask: 0x01) */ -#define PORT14_IN_P12_Pos (12UL) /*!< PORT14 IN: P12 (Bit 12) */ -#define PORT14_IN_P12_Msk \ - (0x1000UL) /*!< PORT14 IN: P12 (Bitfield-Mask: 0x01) */ -#define PORT14_IN_P13_Pos (13UL) /*!< PORT14 IN: P13 (Bit 13) */ -#define PORT14_IN_P13_Msk \ - (0x2000UL) /*!< PORT14 IN: P13 (Bitfield-Mask: 0x01) */ -#define PORT14_IN_P14_Pos (14UL) /*!< PORT14 IN: P14 (Bit 14) */ -#define PORT14_IN_P14_Msk \ - (0x4000UL) /*!< PORT14 IN: P14 (Bitfield-Mask: 0x01) */ -#define PORT14_IN_P15_Pos (15UL) /*!< PORT14 IN: P15 (Bit 15) */ -#define PORT14_IN_P15_Msk \ - (0x8000UL) /*!< PORT14 IN: P15 (Bitfield-Mask: 0x01) */ - -/* -------------------------------- PORT14_PDISC -------------------------------- */ -#define PORT14_PDISC_PDIS0_Pos \ - (0UL) /*!< PORT14 PDISC: PDIS0 (Bit 0) */ -#define PORT14_PDISC_PDIS0_Msk \ - (0x1UL) /*!< PORT14 PDISC: PDIS0 (Bitfield-Mask: 0x01) */ -#define PORT14_PDISC_PDIS1_Pos \ - (1UL) /*!< PORT14 PDISC: PDIS1 (Bit 1) */ -#define PORT14_PDISC_PDIS1_Msk \ - (0x2UL) /*!< PORT14 PDISC: PDIS1 (Bitfield-Mask: 0x01) */ -#define PORT14_PDISC_PDIS2_Pos \ - (2UL) /*!< PORT14 PDISC: PDIS2 (Bit 2) */ -#define PORT14_PDISC_PDIS2_Msk \ - (0x4UL) /*!< PORT14 PDISC: PDIS2 (Bitfield-Mask: 0x01) */ -#define PORT14_PDISC_PDIS3_Pos \ - (3UL) /*!< PORT14 PDISC: PDIS3 (Bit 3) */ -#define PORT14_PDISC_PDIS3_Msk \ - (0x8UL) /*!< PORT14 PDISC: PDIS3 (Bitfield-Mask: 0x01) */ -#define PORT14_PDISC_PDIS4_Pos \ - (4UL) /*!< PORT14 PDISC: PDIS4 (Bit 4) */ -#define PORT14_PDISC_PDIS4_Msk \ - (0x10UL) /*!< PORT14 PDISC: PDIS4 (Bitfield-Mask: 0x01) */ -#define PORT14_PDISC_PDIS5_Pos \ - (5UL) /*!< PORT14 PDISC: PDIS5 (Bit 5) */ -#define PORT14_PDISC_PDIS5_Msk \ - (0x20UL) /*!< PORT14 PDISC: PDIS5 (Bitfield-Mask: 0x01) */ -#define PORT14_PDISC_PDIS6_Pos \ - (6UL) /*!< PORT14 PDISC: PDIS6 (Bit 6) */ -#define PORT14_PDISC_PDIS6_Msk \ - (0x40UL) /*!< PORT14 PDISC: PDIS6 (Bitfield-Mask: 0x01) */ -#define PORT14_PDISC_PDIS7_Pos \ - (7UL) /*!< PORT14 PDISC: PDIS7 (Bit 7) */ -#define PORT14_PDISC_PDIS7_Msk \ - (0x80UL) /*!< PORT14 PDISC: PDIS7 (Bitfield-Mask: 0x01) */ -#define PORT14_PDISC_PDIS8_Pos \ - (8UL) /*!< PORT14 PDISC: PDIS8 (Bit 8) */ -#define PORT14_PDISC_PDIS8_Msk \ - (0x100UL) /*!< PORT14 PDISC: PDIS8 (Bitfield-Mask: 0x01) */ -#define PORT14_PDISC_PDIS9_Pos \ - (9UL) /*!< PORT14 PDISC: PDIS9 (Bit 9) */ -#define PORT14_PDISC_PDIS9_Msk \ - (0x200UL) /*!< PORT14 PDISC: PDIS9 (Bitfield-Mask: 0x01) */ -#define PORT14_PDISC_PDIS10_Pos \ - (10UL) /*!< PORT14 PDISC: PDIS10 (Bit 10) */ -#define PORT14_PDISC_PDIS10_Msk \ - (0x400UL) /*!< PORT14 PDISC: PDIS10 (Bitfield-Mask: 0x01) */ -#define PORT14_PDISC_PDIS11_Pos \ - (11UL) /*!< PORT14 PDISC: PDIS11 (Bit 11) */ -#define PORT14_PDISC_PDIS11_Msk \ - (0x800UL) /*!< PORT14 PDISC: PDIS11 (Bitfield-Mask: 0x01) */ -#define PORT14_PDISC_PDIS12_Pos \ - (12UL) /*!< PORT14 PDISC: PDIS12 (Bit 12) */ -#define PORT14_PDISC_PDIS12_Msk \ - (0x1000UL) /*!< PORT14 PDISC: PDIS12 (Bitfield-Mask: 0x01) */ -#define PORT14_PDISC_PDIS13_Pos \ - (13UL) /*!< PORT14 PDISC: PDIS13 (Bit 13) */ -#define PORT14_PDISC_PDIS13_Msk \ - (0x2000UL) /*!< PORT14 PDISC: PDIS13 (Bitfield-Mask: 0x01) */ -#define PORT14_PDISC_PDIS14_Pos \ - (14UL) /*!< PORT14 PDISC: PDIS14 (Bit 14) */ -#define PORT14_PDISC_PDIS14_Msk \ - (0x4000UL) /*!< PORT14 PDISC: PDIS14 (Bitfield-Mask: 0x01) */ -#define PORT14_PDISC_PDIS15_Pos \ - (15UL) /*!< PORT14 PDISC: PDIS15 (Bit 15) */ -#define PORT14_PDISC_PDIS15_Msk \ - (0x8000UL) /*!< PORT14 PDISC: PDIS15 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- PORT14_PPS --------------------------------- */ -#define PORT14_PPS_PPS0_Pos \ - (0UL) /*!< PORT14 PPS: PPS0 (Bit 0) */ -#define PORT14_PPS_PPS0_Msk \ - (0x1UL) /*!< PORT14 PPS: PPS0 (Bitfield-Mask: 0x01) */ -#define PORT14_PPS_PPS1_Pos \ - (1UL) /*!< PORT14 PPS: PPS1 (Bit 1) */ -#define PORT14_PPS_PPS1_Msk \ - (0x2UL) /*!< PORT14 PPS: PPS1 (Bitfield-Mask: 0x01) */ -#define PORT14_PPS_PPS2_Pos \ - (2UL) /*!< PORT14 PPS: PPS2 (Bit 2) */ -#define PORT14_PPS_PPS2_Msk \ - (0x4UL) /*!< PORT14 PPS: PPS2 (Bitfield-Mask: 0x01) */ -#define PORT14_PPS_PPS3_Pos \ - (3UL) /*!< PORT14 PPS: PPS3 (Bit 3) */ -#define PORT14_PPS_PPS3_Msk \ - (0x8UL) /*!< PORT14 PPS: PPS3 (Bitfield-Mask: 0x01) */ -#define PORT14_PPS_PPS4_Pos \ - (4UL) /*!< PORT14 PPS: PPS4 (Bit 4) */ -#define PORT14_PPS_PPS4_Msk \ - (0x10UL) /*!< PORT14 PPS: PPS4 (Bitfield-Mask: 0x01) */ -#define PORT14_PPS_PPS5_Pos \ - (5UL) /*!< PORT14 PPS: PPS5 (Bit 5) */ -#define PORT14_PPS_PPS5_Msk \ - (0x20UL) /*!< PORT14 PPS: PPS5 (Bitfield-Mask: 0x01) */ -#define PORT14_PPS_PPS6_Pos \ - (6UL) /*!< PORT14 PPS: PPS6 (Bit 6) */ -#define PORT14_PPS_PPS6_Msk \ - (0x40UL) /*!< PORT14 PPS: PPS6 (Bitfield-Mask: 0x01) */ -#define PORT14_PPS_PPS7_Pos \ - (7UL) /*!< PORT14 PPS: PPS7 (Bit 7) */ -#define PORT14_PPS_PPS7_Msk \ - (0x80UL) /*!< PORT14 PPS: PPS7 (Bitfield-Mask: 0x01) */ -#define PORT14_PPS_PPS8_Pos \ - (8UL) /*!< PORT14 PPS: PPS8 (Bit 8) */ -#define PORT14_PPS_PPS8_Msk \ - (0x100UL) /*!< PORT14 PPS: PPS8 (Bitfield-Mask: 0x01) */ -#define PORT14_PPS_PPS9_Pos \ - (9UL) /*!< PORT14 PPS: PPS9 (Bit 9) */ -#define PORT14_PPS_PPS9_Msk \ - (0x200UL) /*!< PORT14 PPS: PPS9 (Bitfield-Mask: 0x01) */ -#define PORT14_PPS_PPS10_Pos \ - (10UL) /*!< PORT14 PPS: PPS10 (Bit 10) */ -#define PORT14_PPS_PPS10_Msk \ - (0x400UL) /*!< PORT14 PPS: PPS10 (Bitfield-Mask: 0x01) */ -#define PORT14_PPS_PPS11_Pos \ - (11UL) /*!< PORT14 PPS: PPS11 (Bit 11) */ -#define PORT14_PPS_PPS11_Msk \ - (0x800UL) /*!< PORT14 PPS: PPS11 (Bitfield-Mask: 0x01) */ -#define PORT14_PPS_PPS12_Pos \ - (12UL) /*!< PORT14 PPS: PPS12 (Bit 12) */ -#define PORT14_PPS_PPS12_Msk \ - (0x1000UL) /*!< PORT14 PPS: PPS12 (Bitfield-Mask: 0x01) */ -#define PORT14_PPS_PPS13_Pos \ - (13UL) /*!< PORT14 PPS: PPS13 (Bit 13) */ -#define PORT14_PPS_PPS13_Msk \ - (0x2000UL) /*!< PORT14 PPS: PPS13 (Bitfield-Mask: 0x01) */ -#define PORT14_PPS_PPS14_Pos \ - (14UL) /*!< PORT14 PPS: PPS14 (Bit 14) */ -#define PORT14_PPS_PPS14_Msk \ - (0x4000UL) /*!< PORT14 PPS: PPS14 (Bitfield-Mask: 0x01) */ -#define PORT14_PPS_PPS15_Pos \ - (15UL) /*!< PORT14 PPS: PPS15 (Bit 15) */ -#define PORT14_PPS_PPS15_Msk \ - (0x8000UL) /*!< PORT14 PPS: PPS15 (Bitfield-Mask: 0x01) */ - -/* -------------------------------- PORT14_HWSEL -------------------------------- */ -#define PORT14_HWSEL_HW0_Pos \ - (0UL) /*!< PORT14 HWSEL: HW0 (Bit 0) */ -#define PORT14_HWSEL_HW0_Msk \ - (0x3UL) /*!< PORT14 HWSEL: HW0 (Bitfield-Mask: 0x03) */ -#define PORT14_HWSEL_HW1_Pos \ - (2UL) /*!< PORT14 HWSEL: HW1 (Bit 2) */ -#define PORT14_HWSEL_HW1_Msk \ - (0xcUL) /*!< PORT14 HWSEL: HW1 (Bitfield-Mask: 0x03) */ -#define PORT14_HWSEL_HW2_Pos \ - (4UL) /*!< PORT14 HWSEL: HW2 (Bit 4) */ -#define PORT14_HWSEL_HW2_Msk \ - (0x30UL) /*!< PORT14 HWSEL: HW2 (Bitfield-Mask: 0x03) */ -#define PORT14_HWSEL_HW3_Pos \ - (6UL) /*!< PORT14 HWSEL: HW3 (Bit 6) */ -#define PORT14_HWSEL_HW3_Msk \ - (0xc0UL) /*!< PORT14 HWSEL: HW3 (Bitfield-Mask: 0x03) */ -#define PORT14_HWSEL_HW4_Pos \ - (8UL) /*!< PORT14 HWSEL: HW4 (Bit 8) */ -#define PORT14_HWSEL_HW4_Msk \ - (0x300UL) /*!< PORT14 HWSEL: HW4 (Bitfield-Mask: 0x03) */ -#define PORT14_HWSEL_HW5_Pos \ - (10UL) /*!< PORT14 HWSEL: HW5 (Bit 10) */ -#define PORT14_HWSEL_HW5_Msk \ - (0xc00UL) /*!< PORT14 HWSEL: HW5 (Bitfield-Mask: 0x03) */ -#define PORT14_HWSEL_HW6_Pos \ - (12UL) /*!< PORT14 HWSEL: HW6 (Bit 12) */ -#define PORT14_HWSEL_HW6_Msk \ - (0x3000UL) /*!< PORT14 HWSEL: HW6 (Bitfield-Mask: 0x03) */ -#define PORT14_HWSEL_HW7_Pos \ - (14UL) /*!< PORT14 HWSEL: HW7 (Bit 14) */ -#define PORT14_HWSEL_HW7_Msk \ - (0xc000UL) /*!< PORT14 HWSEL: HW7 (Bitfield-Mask: 0x03) */ -#define PORT14_HWSEL_HW8_Pos \ - (16UL) /*!< PORT14 HWSEL: HW8 (Bit 16) */ -#define PORT14_HWSEL_HW8_Msk \ - (0x30000UL) /*!< PORT14 HWSEL: HW8 (Bitfield-Mask: 0x03) */ -#define PORT14_HWSEL_HW9_Pos \ - (18UL) /*!< PORT14 HWSEL: HW9 (Bit 18) */ -#define PORT14_HWSEL_HW9_Msk \ - (0xc0000UL) /*!< PORT14 HWSEL: HW9 (Bitfield-Mask: 0x03) */ -#define PORT14_HWSEL_HW10_Pos \ - (20UL) /*!< PORT14 HWSEL: HW10 (Bit 20) */ -#define PORT14_HWSEL_HW10_Msk \ - (0x300000UL) /*!< PORT14 HWSEL: HW10 (Bitfield-Mask: 0x03) */ -#define PORT14_HWSEL_HW11_Pos \ - (22UL) /*!< PORT14 HWSEL: HW11 (Bit 22) */ -#define PORT14_HWSEL_HW11_Msk \ - (0xc00000UL) /*!< PORT14 HWSEL: HW11 (Bitfield-Mask: 0x03) */ -#define PORT14_HWSEL_HW12_Pos \ - (24UL) /*!< PORT14 HWSEL: HW12 (Bit 24) */ -#define PORT14_HWSEL_HW12_Msk \ - (0x3000000UL) /*!< PORT14 HWSEL: HW12 (Bitfield-Mask: 0x03) */ -#define PORT14_HWSEL_HW13_Pos \ - (26UL) /*!< PORT14 HWSEL: HW13 (Bit 26) */ -#define PORT14_HWSEL_HW13_Msk \ - (0xc000000UL) /*!< PORT14 HWSEL: HW13 (Bitfield-Mask: 0x03) */ -#define PORT14_HWSEL_HW14_Pos \ - (28UL) /*!< PORT14 HWSEL: HW14 (Bit 28) */ -#define PORT14_HWSEL_HW14_Msk \ - (0x30000000UL) /*!< PORT14 HWSEL: HW14 (Bitfield-Mask: 0x03) */ -#define PORT14_HWSEL_HW15_Pos \ - (30UL) /*!< PORT14 HWSEL: HW15 (Bit 30) */ -#define PORT14_HWSEL_HW15_Msk \ - (0xc0000000UL) /*!< PORT14 HWSEL: HW15 (Bitfield-Mask: 0x03) */ - -/* ================================================================================ */ -/* ================ struct 'PORT15' Position & Mask ================ */ -/* ================================================================================ */ - -/* --------------------------------- PORT15_OUT --------------------------------- */ -#define PORT15_OUT_P0_Pos (0UL) /*!< PORT15 OUT: P0 (Bit 0) */ -#define PORT15_OUT_P0_Msk \ - (0x1UL) /*!< PORT15 OUT: P0 (Bitfield-Mask: 0x01) */ -#define PORT15_OUT_P1_Pos (1UL) /*!< PORT15 OUT: P1 (Bit 1) */ -#define PORT15_OUT_P1_Msk \ - (0x2UL) /*!< PORT15 OUT: P1 (Bitfield-Mask: 0x01) */ -#define PORT15_OUT_P2_Pos (2UL) /*!< PORT15 OUT: P2 (Bit 2) */ -#define PORT15_OUT_P2_Msk \ - (0x4UL) /*!< PORT15 OUT: P2 (Bitfield-Mask: 0x01) */ -#define PORT15_OUT_P3_Pos (3UL) /*!< PORT15 OUT: P3 (Bit 3) */ -#define PORT15_OUT_P3_Msk \ - (0x8UL) /*!< PORT15 OUT: P3 (Bitfield-Mask: 0x01) */ -#define PORT15_OUT_P4_Pos (4UL) /*!< PORT15 OUT: P4 (Bit 4) */ -#define PORT15_OUT_P4_Msk \ - (0x10UL) /*!< PORT15 OUT: P4 (Bitfield-Mask: 0x01) */ -#define PORT15_OUT_P5_Pos (5UL) /*!< PORT15 OUT: P5 (Bit 5) */ -#define PORT15_OUT_P5_Msk \ - (0x20UL) /*!< PORT15 OUT: P5 (Bitfield-Mask: 0x01) */ -#define PORT15_OUT_P6_Pos (6UL) /*!< PORT15 OUT: P6 (Bit 6) */ -#define PORT15_OUT_P6_Msk \ - (0x40UL) /*!< PORT15 OUT: P6 (Bitfield-Mask: 0x01) */ -#define PORT15_OUT_P7_Pos (7UL) /*!< PORT15 OUT: P7 (Bit 7) */ -#define PORT15_OUT_P7_Msk \ - (0x80UL) /*!< PORT15 OUT: P7 (Bitfield-Mask: 0x01) */ -#define PORT15_OUT_P8_Pos (8UL) /*!< PORT15 OUT: P8 (Bit 8) */ -#define PORT15_OUT_P8_Msk \ - (0x100UL) /*!< PORT15 OUT: P8 (Bitfield-Mask: 0x01) */ -#define PORT15_OUT_P9_Pos (9UL) /*!< PORT15 OUT: P9 (Bit 9) */ -#define PORT15_OUT_P9_Msk \ - (0x200UL) /*!< PORT15 OUT: P9 (Bitfield-Mask: 0x01) */ -#define PORT15_OUT_P10_Pos \ - (10UL) /*!< PORT15 OUT: P10 (Bit 10) */ -#define PORT15_OUT_P10_Msk \ - (0x400UL) /*!< PORT15 OUT: P10 (Bitfield-Mask: 0x01) */ -#define PORT15_OUT_P11_Pos \ - (11UL) /*!< PORT15 OUT: P11 (Bit 11) */ -#define PORT15_OUT_P11_Msk \ - (0x800UL) /*!< PORT15 OUT: P11 (Bitfield-Mask: 0x01) */ -#define PORT15_OUT_P12_Pos \ - (12UL) /*!< PORT15 OUT: P12 (Bit 12) */ -#define PORT15_OUT_P12_Msk \ - (0x1000UL) /*!< PORT15 OUT: P12 (Bitfield-Mask: 0x01) */ -#define PORT15_OUT_P13_Pos \ - (13UL) /*!< PORT15 OUT: P13 (Bit 13) */ -#define PORT15_OUT_P13_Msk \ - (0x2000UL) /*!< PORT15 OUT: P13 (Bitfield-Mask: 0x01) */ -#define PORT15_OUT_P14_Pos \ - (14UL) /*!< PORT15 OUT: P14 (Bit 14) */ -#define PORT15_OUT_P14_Msk \ - (0x4000UL) /*!< PORT15 OUT: P14 (Bitfield-Mask: 0x01) */ -#define PORT15_OUT_P15_Pos \ - (15UL) /*!< PORT15 OUT: P15 (Bit 15) */ -#define PORT15_OUT_P15_Msk \ - (0x8000UL) /*!< PORT15 OUT: P15 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- PORT15_OMR --------------------------------- */ -#define PORT15_OMR_PS0_Pos (0UL) /*!< PORT15 OMR: PS0 (Bit 0) */ -#define PORT15_OMR_PS0_Msk \ - (0x1UL) /*!< PORT15 OMR: PS0 (Bitfield-Mask: 0x01) */ -#define PORT15_OMR_PS1_Pos (1UL) /*!< PORT15 OMR: PS1 (Bit 1) */ -#define PORT15_OMR_PS1_Msk \ - (0x2UL) /*!< PORT15 OMR: PS1 (Bitfield-Mask: 0x01) */ -#define PORT15_OMR_PS2_Pos (2UL) /*!< PORT15 OMR: PS2 (Bit 2) */ -#define PORT15_OMR_PS2_Msk \ - (0x4UL) /*!< PORT15 OMR: PS2 (Bitfield-Mask: 0x01) */ -#define PORT15_OMR_PS3_Pos (3UL) /*!< PORT15 OMR: PS3 (Bit 3) */ -#define PORT15_OMR_PS3_Msk \ - (0x8UL) /*!< PORT15 OMR: PS3 (Bitfield-Mask: 0x01) */ -#define PORT15_OMR_PS4_Pos (4UL) /*!< PORT15 OMR: PS4 (Bit 4) */ -#define PORT15_OMR_PS4_Msk \ - (0x10UL) /*!< PORT15 OMR: PS4 (Bitfield-Mask: 0x01) */ -#define PORT15_OMR_PS5_Pos (5UL) /*!< PORT15 OMR: PS5 (Bit 5) */ -#define PORT15_OMR_PS5_Msk \ - (0x20UL) /*!< PORT15 OMR: PS5 (Bitfield-Mask: 0x01) */ -#define PORT15_OMR_PS6_Pos (6UL) /*!< PORT15 OMR: PS6 (Bit 6) */ -#define PORT15_OMR_PS6_Msk \ - (0x40UL) /*!< PORT15 OMR: PS6 (Bitfield-Mask: 0x01) */ -#define PORT15_OMR_PS7_Pos (7UL) /*!< PORT15 OMR: PS7 (Bit 7) */ -#define PORT15_OMR_PS7_Msk \ - (0x80UL) /*!< PORT15 OMR: PS7 (Bitfield-Mask: 0x01) */ -#define PORT15_OMR_PS8_Pos (8UL) /*!< PORT15 OMR: PS8 (Bit 8) */ -#define PORT15_OMR_PS8_Msk \ - (0x100UL) /*!< PORT15 OMR: PS8 (Bitfield-Mask: 0x01) */ -#define PORT15_OMR_PS9_Pos (9UL) /*!< PORT15 OMR: PS9 (Bit 9) */ -#define PORT15_OMR_PS9_Msk \ - (0x200UL) /*!< PORT15 OMR: PS9 (Bitfield-Mask: 0x01) */ -#define PORT15_OMR_PS10_Pos \ - (10UL) /*!< PORT15 OMR: PS10 (Bit 10) */ -#define PORT15_OMR_PS10_Msk \ - (0x400UL) /*!< PORT15 OMR: PS10 (Bitfield-Mask: 0x01) */ -#define PORT15_OMR_PS11_Pos \ - (11UL) /*!< PORT15 OMR: PS11 (Bit 11) */ -#define PORT15_OMR_PS11_Msk \ - (0x800UL) /*!< PORT15 OMR: PS11 (Bitfield-Mask: 0x01) */ -#define PORT15_OMR_PS12_Pos \ - (12UL) /*!< PORT15 OMR: PS12 (Bit 12) */ -#define PORT15_OMR_PS12_Msk \ - (0x1000UL) /*!< PORT15 OMR: PS12 (Bitfield-Mask: 0x01) */ -#define PORT15_OMR_PS13_Pos \ - (13UL) /*!< PORT15 OMR: PS13 (Bit 13) */ -#define PORT15_OMR_PS13_Msk \ - (0x2000UL) /*!< PORT15 OMR: PS13 (Bitfield-Mask: 0x01) */ -#define PORT15_OMR_PS14_Pos \ - (14UL) /*!< PORT15 OMR: PS14 (Bit 14) */ -#define PORT15_OMR_PS14_Msk \ - (0x4000UL) /*!< PORT15 OMR: PS14 (Bitfield-Mask: 0x01) */ -#define PORT15_OMR_PS15_Pos \ - (15UL) /*!< PORT15 OMR: PS15 (Bit 15) */ -#define PORT15_OMR_PS15_Msk \ - (0x8000UL) /*!< PORT15 OMR: PS15 (Bitfield-Mask: 0x01) */ -#define PORT15_OMR_PR0_Pos \ - (16UL) /*!< PORT15 OMR: PR0 (Bit 16) */ -#define PORT15_OMR_PR0_Msk \ - (0x10000UL) /*!< PORT15 OMR: PR0 (Bitfield-Mask: 0x01) */ -#define PORT15_OMR_PR1_Pos \ - (17UL) /*!< PORT15 OMR: PR1 (Bit 17) */ -#define PORT15_OMR_PR1_Msk \ - (0x20000UL) /*!< PORT15 OMR: PR1 (Bitfield-Mask: 0x01) */ -#define PORT15_OMR_PR2_Pos \ - (18UL) /*!< PORT15 OMR: PR2 (Bit 18) */ -#define PORT15_OMR_PR2_Msk \ - (0x40000UL) /*!< PORT15 OMR: PR2 (Bitfield-Mask: 0x01) */ -#define PORT15_OMR_PR3_Pos \ - (19UL) /*!< PORT15 OMR: PR3 (Bit 19) */ -#define PORT15_OMR_PR3_Msk \ - (0x80000UL) /*!< PORT15 OMR: PR3 (Bitfield-Mask: 0x01) */ -#define PORT15_OMR_PR4_Pos \ - (20UL) /*!< PORT15 OMR: PR4 (Bit 20) */ -#define PORT15_OMR_PR4_Msk \ - (0x100000UL) /*!< PORT15 OMR: PR4 (Bitfield-Mask: 0x01) */ -#define PORT15_OMR_PR5_Pos \ - (21UL) /*!< PORT15 OMR: PR5 (Bit 21) */ -#define PORT15_OMR_PR5_Msk \ - (0x200000UL) /*!< PORT15 OMR: PR5 (Bitfield-Mask: 0x01) */ -#define PORT15_OMR_PR6_Pos \ - (22UL) /*!< PORT15 OMR: PR6 (Bit 22) */ -#define PORT15_OMR_PR6_Msk \ - (0x400000UL) /*!< PORT15 OMR: PR6 (Bitfield-Mask: 0x01) */ -#define PORT15_OMR_PR7_Pos \ - (23UL) /*!< PORT15 OMR: PR7 (Bit 23) */ -#define PORT15_OMR_PR7_Msk \ - (0x800000UL) /*!< PORT15 OMR: PR7 (Bitfield-Mask: 0x01) */ -#define PORT15_OMR_PR8_Pos \ - (24UL) /*!< PORT15 OMR: PR8 (Bit 24) */ -#define PORT15_OMR_PR8_Msk \ - (0x1000000UL) /*!< PORT15 OMR: PR8 (Bitfield-Mask: 0x01) */ -#define PORT15_OMR_PR9_Pos \ - (25UL) /*!< PORT15 OMR: PR9 (Bit 25) */ -#define PORT15_OMR_PR9_Msk \ - (0x2000000UL) /*!< PORT15 OMR: PR9 (Bitfield-Mask: 0x01) */ -#define PORT15_OMR_PR10_Pos \ - (26UL) /*!< PORT15 OMR: PR10 (Bit 26) */ -#define PORT15_OMR_PR10_Msk \ - (0x4000000UL) /*!< PORT15 OMR: PR10 (Bitfield-Mask: 0x01) */ -#define PORT15_OMR_PR11_Pos \ - (27UL) /*!< PORT15 OMR: PR11 (Bit 27) */ -#define PORT15_OMR_PR11_Msk \ - (0x8000000UL) /*!< PORT15 OMR: PR11 (Bitfield-Mask: 0x01) */ -#define PORT15_OMR_PR12_Pos \ - (28UL) /*!< PORT15 OMR: PR12 (Bit 28) */ -#define PORT15_OMR_PR12_Msk \ - (0x10000000UL) /*!< PORT15 OMR: PR12 (Bitfield-Mask: 0x01) */ -#define PORT15_OMR_PR13_Pos \ - (29UL) /*!< PORT15 OMR: PR13 (Bit 29) */ -#define PORT15_OMR_PR13_Msk \ - (0x20000000UL) /*!< PORT15 OMR: PR13 (Bitfield-Mask: 0x01) */ -#define PORT15_OMR_PR14_Pos \ - (30UL) /*!< PORT15 OMR: PR14 (Bit 30) */ -#define PORT15_OMR_PR14_Msk \ - (0x40000000UL) /*!< PORT15 OMR: PR14 (Bitfield-Mask: 0x01) */ -#define PORT15_OMR_PR15_Pos \ - (31UL) /*!< PORT15 OMR: PR15 (Bit 31) */ -#define PORT15_OMR_PR15_Msk \ - (0x80000000UL) /*!< PORT15 OMR: PR15 (Bitfield-Mask: 0x01) */ - -/* -------------------------------- PORT15_IOCR0 -------------------------------- */ -#define PORT15_IOCR0_PC0_Pos \ - (3UL) /*!< PORT15 IOCR0: PC0 (Bit 3) */ -#define PORT15_IOCR0_PC0_Msk \ - (0xf8UL) /*!< PORT15 IOCR0: PC0 (Bitfield-Mask: 0x1f) */ -#define PORT15_IOCR0_PC1_Pos \ - (11UL) /*!< PORT15 IOCR0: PC1 (Bit 11) */ -#define PORT15_IOCR0_PC1_Msk \ - (0xf800UL) /*!< PORT15 IOCR0: PC1 (Bitfield-Mask: 0x1f) */ -#define PORT15_IOCR0_PC2_Pos \ - (19UL) /*!< PORT15 IOCR0: PC2 (Bit 19) */ -#define PORT15_IOCR0_PC2_Msk \ - (0xf80000UL) /*!< PORT15 IOCR0: PC2 (Bitfield-Mask: 0x1f) */ -#define PORT15_IOCR0_PC3_Pos \ - (27UL) /*!< PORT15 IOCR0: PC3 (Bit 27) */ -#define PORT15_IOCR0_PC3_Msk \ - (0xf8000000UL) /*!< PORT15 IOCR0: PC3 (Bitfield-Mask: 0x1f) */ - -/* -------------------------------- PORT15_IOCR4 -------------------------------- */ -#define PORT15_IOCR4_PC4_Pos \ - (3UL) /*!< PORT15 IOCR4: PC4 (Bit 3) */ -#define PORT15_IOCR4_PC4_Msk \ - (0xf8UL) /*!< PORT15 IOCR4: PC4 (Bitfield-Mask: 0x1f) */ -#define PORT15_IOCR4_PC5_Pos \ - (11UL) /*!< PORT15 IOCR4: PC5 (Bit 11) */ -#define PORT15_IOCR4_PC5_Msk \ - (0xf800UL) /*!< PORT15 IOCR4: PC5 (Bitfield-Mask: 0x1f) */ -#define PORT15_IOCR4_PC6_Pos \ - (19UL) /*!< PORT15 IOCR4: PC6 (Bit 19) */ -#define PORT15_IOCR4_PC6_Msk \ - (0xf80000UL) /*!< PORT15 IOCR4: PC6 (Bitfield-Mask: 0x1f) */ -#define PORT15_IOCR4_PC7_Pos \ - (27UL) /*!< PORT15 IOCR4: PC7 (Bit 27) */ -#define PORT15_IOCR4_PC7_Msk \ - (0xf8000000UL) /*!< PORT15 IOCR4: PC7 (Bitfield-Mask: 0x1f) */ - -/* -------------------------------- PORT15_IOCR8 -------------------------------- */ -#define PORT15_IOCR8_PC8_Pos \ - (3UL) /*!< PORT15 IOCR8: PC8 (Bit 3) */ -#define PORT15_IOCR8_PC8_Msk \ - (0xf8UL) /*!< PORT15 IOCR8: PC8 (Bitfield-Mask: 0x1f) */ -#define PORT15_IOCR8_PC9_Pos \ - (11UL) /*!< PORT15 IOCR8: PC9 (Bit 11) */ -#define PORT15_IOCR8_PC9_Msk \ - (0xf800UL) /*!< PORT15 IOCR8: PC9 (Bitfield-Mask: 0x1f) */ -#define PORT15_IOCR8_PC10_Pos \ - (19UL) /*!< PORT15 IOCR8: PC10 (Bit 19) */ -#define PORT15_IOCR8_PC10_Msk \ - (0xf80000UL) /*!< PORT15 IOCR8: PC10 (Bitfield-Mask: 0x1f) */ -#define PORT15_IOCR8_PC11_Pos \ - (27UL) /*!< PORT15 IOCR8: PC11 (Bit 27) */ -#define PORT15_IOCR8_PC11_Msk \ - (0xf8000000UL) /*!< PORT15 IOCR8: PC11 (Bitfield-Mask: 0x1f) */ - -/* ---------------------------------- PORT15_IN --------------------------------- */ -#define PORT15_IN_P0_Pos (0UL) /*!< PORT15 IN: P0 (Bit 0) */ -#define PORT15_IN_P0_Msk (0x1UL) /*!< PORT15 IN: P0 (Bitfield-Mask: 0x01) */ -#define PORT15_IN_P1_Pos (1UL) /*!< PORT15 IN: P1 (Bit 1) */ -#define PORT15_IN_P1_Msk (0x2UL) /*!< PORT15 IN: P1 (Bitfield-Mask: 0x01) */ -#define PORT15_IN_P2_Pos (2UL) /*!< PORT15 IN: P2 (Bit 2) */ -#define PORT15_IN_P2_Msk (0x4UL) /*!< PORT15 IN: P2 (Bitfield-Mask: 0x01) */ -#define PORT15_IN_P3_Pos (3UL) /*!< PORT15 IN: P3 (Bit 3) */ -#define PORT15_IN_P3_Msk (0x8UL) /*!< PORT15 IN: P3 (Bitfield-Mask: 0x01) */ -#define PORT15_IN_P4_Pos (4UL) /*!< PORT15 IN: P4 (Bit 4) */ -#define PORT15_IN_P4_Msk \ - (0x10UL) /*!< PORT15 IN: P4 (Bitfield-Mask: 0x01) */ -#define PORT15_IN_P5_Pos (5UL) /*!< PORT15 IN: P5 (Bit 5) */ -#define PORT15_IN_P5_Msk \ - (0x20UL) /*!< PORT15 IN: P5 (Bitfield-Mask: 0x01) */ -#define PORT15_IN_P6_Pos (6UL) /*!< PORT15 IN: P6 (Bit 6) */ -#define PORT15_IN_P6_Msk \ - (0x40UL) /*!< PORT15 IN: P6 (Bitfield-Mask: 0x01) */ -#define PORT15_IN_P7_Pos (7UL) /*!< PORT15 IN: P7 (Bit 7) */ -#define PORT15_IN_P7_Msk \ - (0x80UL) /*!< PORT15 IN: P7 (Bitfield-Mask: 0x01) */ -#define PORT15_IN_P8_Pos (8UL) /*!< PORT15 IN: P8 (Bit 8) */ -#define PORT15_IN_P8_Msk \ - (0x100UL) /*!< PORT15 IN: P8 (Bitfield-Mask: 0x01) */ -#define PORT15_IN_P9_Pos (9UL) /*!< PORT15 IN: P9 (Bit 9) */ -#define PORT15_IN_P9_Msk \ - (0x200UL) /*!< PORT15 IN: P9 (Bitfield-Mask: 0x01) */ -#define PORT15_IN_P10_Pos (10UL) /*!< PORT15 IN: P10 (Bit 10) */ -#define PORT15_IN_P10_Msk \ - (0x400UL) /*!< PORT15 IN: P10 (Bitfield-Mask: 0x01) */ -#define PORT15_IN_P11_Pos (11UL) /*!< PORT15 IN: P11 (Bit 11) */ -#define PORT15_IN_P11_Msk \ - (0x800UL) /*!< PORT15 IN: P11 (Bitfield-Mask: 0x01) */ -#define PORT15_IN_P12_Pos (12UL) /*!< PORT15 IN: P12 (Bit 12) */ -#define PORT15_IN_P12_Msk \ - (0x1000UL) /*!< PORT15 IN: P12 (Bitfield-Mask: 0x01) */ -#define PORT15_IN_P13_Pos (13UL) /*!< PORT15 IN: P13 (Bit 13) */ -#define PORT15_IN_P13_Msk \ - (0x2000UL) /*!< PORT15 IN: P13 (Bitfield-Mask: 0x01) */ -#define PORT15_IN_P14_Pos (14UL) /*!< PORT15 IN: P14 (Bit 14) */ -#define PORT15_IN_P14_Msk \ - (0x4000UL) /*!< PORT15 IN: P14 (Bitfield-Mask: 0x01) */ -#define PORT15_IN_P15_Pos (15UL) /*!< PORT15 IN: P15 (Bit 15) */ -#define PORT15_IN_P15_Msk \ - (0x8000UL) /*!< PORT15 IN: P15 (Bitfield-Mask: 0x01) */ - -/* -------------------------------- PORT15_PDISC -------------------------------- */ -#define PORT15_PDISC_PDIS0_Pos \ - (0UL) /*!< PORT15 PDISC: PDIS0 (Bit 0) */ -#define PORT15_PDISC_PDIS0_Msk \ - (0x1UL) /*!< PORT15 PDISC: PDIS0 (Bitfield-Mask: 0x01) */ -#define PORT15_PDISC_PDIS1_Pos \ - (1UL) /*!< PORT15 PDISC: PDIS1 (Bit 1) */ -#define PORT15_PDISC_PDIS1_Msk \ - (0x2UL) /*!< PORT15 PDISC: PDIS1 (Bitfield-Mask: 0x01) */ -#define PORT15_PDISC_PDIS2_Pos \ - (2UL) /*!< PORT15 PDISC: PDIS2 (Bit 2) */ -#define PORT15_PDISC_PDIS2_Msk \ - (0x4UL) /*!< PORT15 PDISC: PDIS2 (Bitfield-Mask: 0x01) */ -#define PORT15_PDISC_PDIS3_Pos \ - (3UL) /*!< PORT15 PDISC: PDIS3 (Bit 3) */ -#define PORT15_PDISC_PDIS3_Msk \ - (0x8UL) /*!< PORT15 PDISC: PDIS3 (Bitfield-Mask: 0x01) */ -#define PORT15_PDISC_PDIS4_Pos \ - (4UL) /*!< PORT15 PDISC: PDIS4 (Bit 4) */ -#define PORT15_PDISC_PDIS4_Msk \ - (0x10UL) /*!< PORT15 PDISC: PDIS4 (Bitfield-Mask: 0x01) */ -#define PORT15_PDISC_PDIS5_Pos \ - (5UL) /*!< PORT15 PDISC: PDIS5 (Bit 5) */ -#define PORT15_PDISC_PDIS5_Msk \ - (0x20UL) /*!< PORT15 PDISC: PDIS5 (Bitfield-Mask: 0x01) */ -#define PORT15_PDISC_PDIS6_Pos \ - (6UL) /*!< PORT15 PDISC: PDIS6 (Bit 6) */ -#define PORT15_PDISC_PDIS6_Msk \ - (0x40UL) /*!< PORT15 PDISC: PDIS6 (Bitfield-Mask: 0x01) */ -#define PORT15_PDISC_PDIS7_Pos \ - (7UL) /*!< PORT15 PDISC: PDIS7 (Bit 7) */ -#define PORT15_PDISC_PDIS7_Msk \ - (0x80UL) /*!< PORT15 PDISC: PDIS7 (Bitfield-Mask: 0x01) */ -#define PORT15_PDISC_PDIS8_Pos \ - (8UL) /*!< PORT15 PDISC: PDIS8 (Bit 8) */ -#define PORT15_PDISC_PDIS8_Msk \ - (0x100UL) /*!< PORT15 PDISC: PDIS8 (Bitfield-Mask: 0x01) */ -#define PORT15_PDISC_PDIS9_Pos \ - (9UL) /*!< PORT15 PDISC: PDIS9 (Bit 9) */ -#define PORT15_PDISC_PDIS9_Msk \ - (0x200UL) /*!< PORT15 PDISC: PDIS9 (Bitfield-Mask: 0x01) */ -#define PORT15_PDISC_PDIS10_Pos \ - (10UL) /*!< PORT15 PDISC: PDIS10 (Bit 10) */ -#define PORT15_PDISC_PDIS10_Msk \ - (0x400UL) /*!< PORT15 PDISC: PDIS10 (Bitfield-Mask: 0x01) */ -#define PORT15_PDISC_PDIS11_Pos \ - (11UL) /*!< PORT15 PDISC: PDIS11 (Bit 11) */ -#define PORT15_PDISC_PDIS11_Msk \ - (0x800UL) /*!< PORT15 PDISC: PDIS11 (Bitfield-Mask: 0x01) */ -#define PORT15_PDISC_PDIS12_Pos \ - (12UL) /*!< PORT15 PDISC: PDIS12 (Bit 12) */ -#define PORT15_PDISC_PDIS12_Msk \ - (0x1000UL) /*!< PORT15 PDISC: PDIS12 (Bitfield-Mask: 0x01) */ -#define PORT15_PDISC_PDIS13_Pos \ - (13UL) /*!< PORT15 PDISC: PDIS13 (Bit 13) */ -#define PORT15_PDISC_PDIS13_Msk \ - (0x2000UL) /*!< PORT15 PDISC: PDIS13 (Bitfield-Mask: 0x01) */ -#define PORT15_PDISC_PDIS14_Pos \ - (14UL) /*!< PORT15 PDISC: PDIS14 (Bit 14) */ -#define PORT15_PDISC_PDIS14_Msk \ - (0x4000UL) /*!< PORT15 PDISC: PDIS14 (Bitfield-Mask: 0x01) */ -#define PORT15_PDISC_PDIS15_Pos \ - (15UL) /*!< PORT15 PDISC: PDIS15 (Bit 15) */ -#define PORT15_PDISC_PDIS15_Msk \ - (0x8000UL) /*!< PORT15 PDISC: PDIS15 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- PORT15_PPS --------------------------------- */ -#define PORT15_PPS_PPS0_Pos \ - (0UL) /*!< PORT15 PPS: PPS0 (Bit 0) */ -#define PORT15_PPS_PPS0_Msk \ - (0x1UL) /*!< PORT15 PPS: PPS0 (Bitfield-Mask: 0x01) */ -#define PORT15_PPS_PPS1_Pos \ - (1UL) /*!< PORT15 PPS: PPS1 (Bit 1) */ -#define PORT15_PPS_PPS1_Msk \ - (0x2UL) /*!< PORT15 PPS: PPS1 (Bitfield-Mask: 0x01) */ -#define PORT15_PPS_PPS2_Pos \ - (2UL) /*!< PORT15 PPS: PPS2 (Bit 2) */ -#define PORT15_PPS_PPS2_Msk \ - (0x4UL) /*!< PORT15 PPS: PPS2 (Bitfield-Mask: 0x01) */ -#define PORT15_PPS_PPS3_Pos \ - (3UL) /*!< PORT15 PPS: PPS3 (Bit 3) */ -#define PORT15_PPS_PPS3_Msk \ - (0x8UL) /*!< PORT15 PPS: PPS3 (Bitfield-Mask: 0x01) */ -#define PORT15_PPS_PPS4_Pos \ - (4UL) /*!< PORT15 PPS: PPS4 (Bit 4) */ -#define PORT15_PPS_PPS4_Msk \ - (0x10UL) /*!< PORT15 PPS: PPS4 (Bitfield-Mask: 0x01) */ -#define PORT15_PPS_PPS5_Pos \ - (5UL) /*!< PORT15 PPS: PPS5 (Bit 5) */ -#define PORT15_PPS_PPS5_Msk \ - (0x20UL) /*!< PORT15 PPS: PPS5 (Bitfield-Mask: 0x01) */ -#define PORT15_PPS_PPS6_Pos \ - (6UL) /*!< PORT15 PPS: PPS6 (Bit 6) */ -#define PORT15_PPS_PPS6_Msk \ - (0x40UL) /*!< PORT15 PPS: PPS6 (Bitfield-Mask: 0x01) */ -#define PORT15_PPS_PPS7_Pos \ - (7UL) /*!< PORT15 PPS: PPS7 (Bit 7) */ -#define PORT15_PPS_PPS7_Msk \ - (0x80UL) /*!< PORT15 PPS: PPS7 (Bitfield-Mask: 0x01) */ -#define PORT15_PPS_PPS8_Pos \ - (8UL) /*!< PORT15 PPS: PPS8 (Bit 8) */ -#define PORT15_PPS_PPS8_Msk \ - (0x100UL) /*!< PORT15 PPS: PPS8 (Bitfield-Mask: 0x01) */ -#define PORT15_PPS_PPS9_Pos \ - (9UL) /*!< PORT15 PPS: PPS9 (Bit 9) */ -#define PORT15_PPS_PPS9_Msk \ - (0x200UL) /*!< PORT15 PPS: PPS9 (Bitfield-Mask: 0x01) */ -#define PORT15_PPS_PPS10_Pos \ - (10UL) /*!< PORT15 PPS: PPS10 (Bit 10) */ -#define PORT15_PPS_PPS10_Msk \ - (0x400UL) /*!< PORT15 PPS: PPS10 (Bitfield-Mask: 0x01) */ -#define PORT15_PPS_PPS11_Pos \ - (11UL) /*!< PORT15 PPS: PPS11 (Bit 11) */ -#define PORT15_PPS_PPS11_Msk \ - (0x800UL) /*!< PORT15 PPS: PPS11 (Bitfield-Mask: 0x01) */ -#define PORT15_PPS_PPS12_Pos \ - (12UL) /*!< PORT15 PPS: PPS12 (Bit 12) */ -#define PORT15_PPS_PPS12_Msk \ - (0x1000UL) /*!< PORT15 PPS: PPS12 (Bitfield-Mask: 0x01) */ -#define PORT15_PPS_PPS13_Pos \ - (13UL) /*!< PORT15 PPS: PPS13 (Bit 13) */ -#define PORT15_PPS_PPS13_Msk \ - (0x2000UL) /*!< PORT15 PPS: PPS13 (Bitfield-Mask: 0x01) */ -#define PORT15_PPS_PPS14_Pos \ - (14UL) /*!< PORT15 PPS: PPS14 (Bit 14) */ -#define PORT15_PPS_PPS14_Msk \ - (0x4000UL) /*!< PORT15 PPS: PPS14 (Bitfield-Mask: 0x01) */ -#define PORT15_PPS_PPS15_Pos \ - (15UL) /*!< PORT15 PPS: PPS15 (Bit 15) */ -#define PORT15_PPS_PPS15_Msk \ - (0x8000UL) /*!< PORT15 PPS: PPS15 (Bitfield-Mask: 0x01) */ - -/* -------------------------------- PORT15_HWSEL -------------------------------- */ -#define PORT15_HWSEL_HW0_Pos \ - (0UL) /*!< PORT15 HWSEL: HW0 (Bit 0) */ -#define PORT15_HWSEL_HW0_Msk \ - (0x3UL) /*!< PORT15 HWSEL: HW0 (Bitfield-Mask: 0x03) */ -#define PORT15_HWSEL_HW1_Pos \ - (2UL) /*!< PORT15 HWSEL: HW1 (Bit 2) */ -#define PORT15_HWSEL_HW1_Msk \ - (0xcUL) /*!< PORT15 HWSEL: HW1 (Bitfield-Mask: 0x03) */ -#define PORT15_HWSEL_HW2_Pos \ - (4UL) /*!< PORT15 HWSEL: HW2 (Bit 4) */ -#define PORT15_HWSEL_HW2_Msk \ - (0x30UL) /*!< PORT15 HWSEL: HW2 (Bitfield-Mask: 0x03) */ -#define PORT15_HWSEL_HW3_Pos \ - (6UL) /*!< PORT15 HWSEL: HW3 (Bit 6) */ -#define PORT15_HWSEL_HW3_Msk \ - (0xc0UL) /*!< PORT15 HWSEL: HW3 (Bitfield-Mask: 0x03) */ -#define PORT15_HWSEL_HW4_Pos \ - (8UL) /*!< PORT15 HWSEL: HW4 (Bit 8) */ -#define PORT15_HWSEL_HW4_Msk \ - (0x300UL) /*!< PORT15 HWSEL: HW4 (Bitfield-Mask: 0x03) */ -#define PORT15_HWSEL_HW5_Pos \ - (10UL) /*!< PORT15 HWSEL: HW5 (Bit 10) */ -#define PORT15_HWSEL_HW5_Msk \ - (0xc00UL) /*!< PORT15 HWSEL: HW5 (Bitfield-Mask: 0x03) */ -#define PORT15_HWSEL_HW6_Pos \ - (12UL) /*!< PORT15 HWSEL: HW6 (Bit 12) */ -#define PORT15_HWSEL_HW6_Msk \ - (0x3000UL) /*!< PORT15 HWSEL: HW6 (Bitfield-Mask: 0x03) */ -#define PORT15_HWSEL_HW7_Pos \ - (14UL) /*!< PORT15 HWSEL: HW7 (Bit 14) */ -#define PORT15_HWSEL_HW7_Msk \ - (0xc000UL) /*!< PORT15 HWSEL: HW7 (Bitfield-Mask: 0x03) */ -#define PORT15_HWSEL_HW8_Pos \ - (16UL) /*!< PORT15 HWSEL: HW8 (Bit 16) */ -#define PORT15_HWSEL_HW8_Msk \ - (0x30000UL) /*!< PORT15 HWSEL: HW8 (Bitfield-Mask: 0x03) */ -#define PORT15_HWSEL_HW9_Pos \ - (18UL) /*!< PORT15 HWSEL: HW9 (Bit 18) */ -#define PORT15_HWSEL_HW9_Msk \ - (0xc0000UL) /*!< PORT15 HWSEL: HW9 (Bitfield-Mask: 0x03) */ -#define PORT15_HWSEL_HW10_Pos \ - (20UL) /*!< PORT15 HWSEL: HW10 (Bit 20) */ -#define PORT15_HWSEL_HW10_Msk \ - (0x300000UL) /*!< PORT15 HWSEL: HW10 (Bitfield-Mask: 0x03) */ -#define PORT15_HWSEL_HW11_Pos \ - (22UL) /*!< PORT15 HWSEL: HW11 (Bit 22) */ -#define PORT15_HWSEL_HW11_Msk \ - (0xc00000UL) /*!< PORT15 HWSEL: HW11 (Bitfield-Mask: 0x03) */ -#define PORT15_HWSEL_HW12_Pos \ - (24UL) /*!< PORT15 HWSEL: HW12 (Bit 24) */ -#define PORT15_HWSEL_HW12_Msk \ - (0x3000000UL) /*!< PORT15 HWSEL: HW12 (Bitfield-Mask: 0x03) */ -#define PORT15_HWSEL_HW13_Pos \ - (26UL) /*!< PORT15 HWSEL: HW13 (Bit 26) */ -#define PORT15_HWSEL_HW13_Msk \ - (0xc000000UL) /*!< PORT15 HWSEL: HW13 (Bitfield-Mask: 0x03) */ -#define PORT15_HWSEL_HW14_Pos \ - (28UL) /*!< PORT15 HWSEL: HW14 (Bit 28) */ -#define PORT15_HWSEL_HW14_Msk \ - (0x30000000UL) /*!< PORT15 HWSEL: HW14 (Bitfield-Mask: 0x03) */ -#define PORT15_HWSEL_HW15_Pos \ - (30UL) /*!< PORT15 HWSEL: HW15 (Bit 30) */ -#define PORT15_HWSEL_HW15_Msk \ - (0xc0000000UL) /*!< PORT15 HWSEL: HW15 (Bitfield-Mask: 0x03) */ - -/* ================================================================================ */ -/* ================ Peripheral memory map ================ */ -/* ================================================================================ */ - -#define PPB_BASE 0xE000E000UL -#define DLR_BASE 0x50004900UL -#define ERU0_BASE 0x50004800UL -#define ERU1_BASE 0x40044000UL -#define GPDMA0_BASE 0x500142C0UL -#define GPDMA0_CH0_BASE 0x50014000UL -#define GPDMA0_CH1_BASE 0x50014058UL -#define GPDMA0_CH2_BASE 0x500140B0UL -#define GPDMA0_CH3_BASE 0x50014108UL -#define GPDMA0_CH4_BASE 0x50014160UL -#define GPDMA0_CH5_BASE 0x500141B8UL -#define GPDMA0_CH6_BASE 0x50014210UL -#define GPDMA0_CH7_BASE 0x50014268UL -#define FCE_BASE 0x50020000UL -#define FCE_KE0_BASE 0x50020020UL -#define FCE_KE1_BASE 0x50020040UL -#define FCE_KE2_BASE 0x50020060UL -#define FCE_KE3_BASE 0x50020080UL -#define PBA0_BASE 0x40000000UL -#define PBA1_BASE 0x48000000UL -#define FLASH0_BASE 0x58001000UL -#define PREF_BASE 0x58004000UL -#define PMU0_BASE 0x58000508UL -#define WDT_BASE 0x50008000UL -#define RTC_BASE 0x50004A00UL -#define SCU_CLK_BASE 0x50004600UL -#define SCU_OSC_BASE 0x50004700UL -#define SCU_PLL_BASE 0x50004710UL -#define SCU_GENERAL_BASE 0x50004000UL -#define SCU_INTERRUPT_BASE 0x50004074UL -#define SCU_PARITY_BASE 0x5000413CUL -#define SCU_TRAP_BASE 0x50004160UL -#define SCU_HIBERNATE_BASE 0x50004300UL -#define SCU_POWER_BASE 0x50004200UL -#define SCU_RESET_BASE 0x50004400UL -#define LEDTS0_BASE 0x48010000UL -#define ETH0_CON_BASE 0x50004040UL -#define ETH0_BASE 0x5000C000UL -#define USB0_BASE 0x50040000UL -#define USB_EP_BASE 0x50040900UL -#define USB0_EP1_BASE 0x50040920UL -#define USB0_EP2_BASE 0x50040940UL -#define USB0_EP3_BASE 0x50040960UL -#define USB0_EP4_BASE 0x50040980UL -#define USB0_EP5_BASE 0x500409A0UL -#define USB0_EP6_BASE 0x500409C0UL -#define USB0_CH0_BASE 0x50040500UL -#define USB0_CH1_BASE 0x50040520UL -#define USB0_CH2_BASE 0x50040540UL -#define USB0_CH3_BASE 0x50040560UL -#define USB0_CH4_BASE 0x50040580UL -#define USB0_CH5_BASE 0x500405A0UL -#define USB0_CH6_BASE 0x500405C0UL -#define USB0_CH7_BASE 0x500405E0UL -#define USB0_CH8_BASE 0x50040600UL -#define USB0_CH9_BASE 0x50040620UL -#define USB0_CH10_BASE 0x50040640UL -#define USB0_CH11_BASE 0x50040660UL -#define USB0_CH12_BASE 0x50040680UL -#define USB0_CH13_BASE 0x500406A0UL -#define USIC0_BASE 0x40030008UL -#define USIC1_BASE 0x48020008UL -#define USIC0_CH0_BASE 0x40030000UL -#define USIC0_CH1_BASE 0x40030200UL -#define USIC1_CH0_BASE 0x48020000UL -#define USIC1_CH1_BASE 0x48020200UL -#define CAN_BASE 0x48014000UL -#define CAN_NODE0_BASE 0x48014200UL -#define CAN_NODE1_BASE 0x48014300UL -#define CAN_MO0_BASE 0x48015000UL -#define CAN_MO1_BASE 0x48015020UL -#define CAN_MO2_BASE 0x48015040UL -#define CAN_MO3_BASE 0x48015060UL -#define CAN_MO4_BASE 0x48015080UL -#define CAN_MO5_BASE 0x480150A0UL -#define CAN_MO6_BASE 0x480150C0UL -#define CAN_MO7_BASE 0x480150E0UL -#define CAN_MO8_BASE 0x48015100UL -#define CAN_MO9_BASE 0x48015120UL -#define CAN_MO10_BASE 0x48015140UL -#define CAN_MO11_BASE 0x48015160UL -#define CAN_MO12_BASE 0x48015180UL -#define CAN_MO13_BASE 0x480151A0UL -#define CAN_MO14_BASE 0x480151C0UL -#define CAN_MO15_BASE 0x480151E0UL -#define CAN_MO16_BASE 0x48015200UL -#define CAN_MO17_BASE 0x48015220UL -#define CAN_MO18_BASE 0x48015240UL -#define CAN_MO19_BASE 0x48015260UL -#define CAN_MO20_BASE 0x48015280UL -#define CAN_MO21_BASE 0x480152A0UL -#define CAN_MO22_BASE 0x480152C0UL -#define CAN_MO23_BASE 0x480152E0UL -#define CAN_MO24_BASE 0x48015300UL -#define CAN_MO25_BASE 0x48015320UL -#define CAN_MO26_BASE 0x48015340UL -#define CAN_MO27_BASE 0x48015360UL -#define CAN_MO28_BASE 0x48015380UL -#define CAN_MO29_BASE 0x480153A0UL -#define CAN_MO30_BASE 0x480153C0UL -#define CAN_MO31_BASE 0x480153E0UL -#define CAN_MO32_BASE 0x48015400UL -#define CAN_MO33_BASE 0x48015420UL -#define CAN_MO34_BASE 0x48015440UL -#define CAN_MO35_BASE 0x48015460UL -#define CAN_MO36_BASE 0x48015480UL -#define CAN_MO37_BASE 0x480154A0UL -#define CAN_MO38_BASE 0x480154C0UL -#define CAN_MO39_BASE 0x480154E0UL -#define CAN_MO40_BASE 0x48015500UL -#define CAN_MO41_BASE 0x48015520UL -#define CAN_MO42_BASE 0x48015540UL -#define CAN_MO43_BASE 0x48015560UL -#define CAN_MO44_BASE 0x48015580UL -#define CAN_MO45_BASE 0x480155A0UL -#define CAN_MO46_BASE 0x480155C0UL -#define CAN_MO47_BASE 0x480155E0UL -#define CAN_MO48_BASE 0x48015600UL -#define CAN_MO49_BASE 0x48015620UL -#define CAN_MO50_BASE 0x48015640UL -#define CAN_MO51_BASE 0x48015660UL -#define CAN_MO52_BASE 0x48015680UL -#define CAN_MO53_BASE 0x480156A0UL -#define CAN_MO54_BASE 0x480156C0UL -#define CAN_MO55_BASE 0x480156E0UL -#define CAN_MO56_BASE 0x48015700UL -#define CAN_MO57_BASE 0x48015720UL -#define CAN_MO58_BASE 0x48015740UL -#define CAN_MO59_BASE 0x48015760UL -#define CAN_MO60_BASE 0x48015780UL -#define CAN_MO61_BASE 0x480157A0UL -#define CAN_MO62_BASE 0x480157C0UL -#define CAN_MO63_BASE 0x480157E0UL -#define VADC_BASE 0x40004000UL -#define VADC_G0_BASE 0x40004400UL -#define VADC_G1_BASE 0x40004800UL -#define VADC_G2_BASE 0x40004C00UL -#define VADC_G3_BASE 0x40005000UL -#define DSD_BASE 0x40008000UL -#define DSD_CH0_BASE 0x40008100UL -#define DSD_CH1_BASE 0x40008200UL -#define DSD_CH2_BASE 0x40008300UL -#define DSD_CH3_BASE 0x40008400UL -#define DAC_BASE 0x48018000UL -#define CCU40_BASE 0x4000C000UL -#define CCU41_BASE 0x40010000UL -#define CCU42_BASE 0x40014000UL -#define CCU43_BASE 0x48004000UL -#define CCU40_CC40_BASE 0x4000C100UL -#define CCU40_CC41_BASE 0x4000C200UL -#define CCU40_CC42_BASE 0x4000C300UL -#define CCU40_CC43_BASE 0x4000C400UL -#define CCU41_CC40_BASE 0x40010100UL -#define CCU41_CC41_BASE 0x40010200UL -#define CCU41_CC42_BASE 0x40010300UL -#define CCU41_CC43_BASE 0x40010400UL -#define CCU42_CC40_BASE 0x40014100UL -#define CCU42_CC41_BASE 0x40014200UL -#define CCU42_CC42_BASE 0x40014300UL -#define CCU42_CC43_BASE 0x40014400UL -#define CCU43_CC40_BASE 0x48004100UL -#define CCU43_CC41_BASE 0x48004200UL -#define CCU43_CC42_BASE 0x48004300UL -#define CCU43_CC43_BASE 0x48004400UL -#define CCU80_BASE 0x40020000UL -#define CCU81_BASE 0x40024000UL -#define CCU80_CC80_BASE 0x40020100UL -#define CCU80_CC81_BASE 0x40020200UL -#define CCU80_CC82_BASE 0x40020300UL -#define CCU80_CC83_BASE 0x40020400UL -#define CCU81_CC80_BASE 0x40024100UL -#define CCU81_CC81_BASE 0x40024200UL -#define CCU81_CC82_BASE 0x40024300UL -#define CCU81_CC83_BASE 0x40024400UL -#define HRPWM0_BASE 0x40020900UL -#define HRPWM0_CSG0_BASE 0x40020A00UL -#define HRPWM0_CSG1_BASE 0x40020B00UL -#define HRPWM0_CSG2_BASE 0x40020C00UL -#define HRPWM0_HRC0_BASE 0x40021300UL -#define HRPWM0_HRC1_BASE 0x40021400UL -#define HRPWM0_HRC2_BASE 0x40021500UL -#define HRPWM0_HRC3_BASE 0x40021600UL -#define POSIF0_BASE 0x40028000UL -#define POSIF1_BASE 0x4002C000UL -#define PORT0_BASE 0x48028000UL -#define PORT1_BASE 0x48028100UL -#define PORT2_BASE 0x48028200UL -#define PORT3_BASE 0x48028300UL -#define PORT4_BASE 0x48028400UL -#define PORT5_BASE 0x48028500UL -#define PORT14_BASE 0x48028E00UL -#define PORT15_BASE 0x48028F00UL - -/* ================================================================================ */ -/* ================ Peripheral declaration ================ */ -/* ================================================================================ */ - -#define PPB ((PPB_Type *)PPB_BASE) -#define DLR ((DLR_GLOBAL_TypeDef *)DLR_BASE) -#define ERU0 ((ERU_GLOBAL_TypeDef *)ERU0_BASE) -#define ERU1 ((ERU_GLOBAL_TypeDef *)ERU1_BASE) -#define GPDMA0 ((GPDMA0_GLOBAL_TypeDef *)GPDMA0_BASE) -#define GPDMA0_CH0 ((GPDMA0_CH_TypeDef *)GPDMA0_CH0_BASE) -#define GPDMA0_CH1 ((GPDMA0_CH_TypeDef *)GPDMA0_CH1_BASE) -#define GPDMA0_CH2 ((GPDMA0_CH_TypeDef *)GPDMA0_CH2_BASE) -#define GPDMA0_CH3 ((GPDMA0_CH_TypeDef *)GPDMA0_CH3_BASE) -#define GPDMA0_CH4 ((GPDMA0_CH_TypeDef *)GPDMA0_CH4_BASE) -#define GPDMA0_CH5 ((GPDMA0_CH_TypeDef *)GPDMA0_CH5_BASE) -#define GPDMA0_CH6 ((GPDMA0_CH_TypeDef *)GPDMA0_CH6_BASE) -#define GPDMA0_CH7 ((GPDMA0_CH_TypeDef *)GPDMA0_CH7_BASE) -#define FCE ((FCE_GLOBAL_TypeDef *)FCE_BASE) -#define FCE_KE0 ((FCE_KE_TypeDef *)FCE_KE0_BASE) -#define FCE_KE1 ((FCE_KE_TypeDef *)FCE_KE1_BASE) -#define FCE_KE2 ((FCE_KE_TypeDef *)FCE_KE2_BASE) -#define FCE_KE3 ((FCE_KE_TypeDef *)FCE_KE3_BASE) -#define PBA0 ((PBA_GLOBAL_TypeDef *)PBA0_BASE) -#define PBA1 ((PBA_GLOBAL_TypeDef *)PBA1_BASE) -#define FLASH0 ((FLASH0_GLOBAL_TypeDef *)FLASH0_BASE) -#define PREF ((PREF_GLOBAL_TypeDef *)PREF_BASE) -#define PMU0 ((PMU0_GLOBAL_TypeDef *)PMU0_BASE) -#define WDT ((WDT_GLOBAL_TypeDef *)WDT_BASE) -#define RTC ((RTC_GLOBAL_TypeDef *)RTC_BASE) -#define SCU_CLK ((SCU_CLK_TypeDef *)SCU_CLK_BASE) -#define SCU_OSC ((SCU_OSC_TypeDef *)SCU_OSC_BASE) -#define SCU_PLL ((SCU_PLL_TypeDef *)SCU_PLL_BASE) -#define SCU_GENERAL ((SCU_GENERAL_TypeDef *)SCU_GENERAL_BASE) -#define SCU_INTERRUPT ((SCU_INTERRUPT_TypeDef *)SCU_INTERRUPT_BASE) -#define SCU_PARITY ((SCU_PARITY_TypeDef *)SCU_PARITY_BASE) -#define SCU_TRAP ((SCU_TRAP_TypeDef *)SCU_TRAP_BASE) -#define SCU_HIBERNATE ((SCU_HIBERNATE_TypeDef *)SCU_HIBERNATE_BASE) -#define SCU_POWER ((SCU_POWER_TypeDef *)SCU_POWER_BASE) -#define SCU_RESET ((SCU_RESET_TypeDef *)SCU_RESET_BASE) -#define LEDTS0 ((LEDTS0_GLOBAL_TypeDef *)LEDTS0_BASE) -#if UC_DEVICE == XMC4400 - #define ETH0_CON ((ETH0_CON_GLOBAL_TypeDef *)ETH0_CON_BASE) - #define ETH0 ((ETH_GLOBAL_TypeDef *)ETH0_BASE) -#endif -#define USB0 ((USB0_GLOBAL_TypeDef *)USB0_BASE) -#define USB0_EP0 ((USB0_EP0_TypeDef *)USB_EP_BASE) -#define USB0_EP1 ((USB0_EP_TypeDef *)USB0_EP1_BASE) -#define USB0_EP2 ((USB0_EP_TypeDef *)USB0_EP2_BASE) -#define USB0_EP3 ((USB0_EP_TypeDef *)USB0_EP3_BASE) -#define USB0_EP4 ((USB0_EP_TypeDef *)USB0_EP4_BASE) -#define USB0_EP5 ((USB0_EP_TypeDef *)USB0_EP5_BASE) -#define USB0_EP6 ((USB0_EP_TypeDef *)USB0_EP6_BASE) -#define USB0_CH0 ((USB0_CH_TypeDef *)USB0_CH0_BASE) -#define USB0_CH1 ((USB0_CH_TypeDef *)USB0_CH1_BASE) -#define USB0_CH2 ((USB0_CH_TypeDef *)USB0_CH2_BASE) -#define USB0_CH3 ((USB0_CH_TypeDef *)USB0_CH3_BASE) -#define USB0_CH4 ((USB0_CH_TypeDef *)USB0_CH4_BASE) -#define USB0_CH5 ((USB0_CH_TypeDef *)USB0_CH5_BASE) -#define USB0_CH6 ((USB0_CH_TypeDef *)USB0_CH6_BASE) -#define USB0_CH7 ((USB0_CH_TypeDef *)USB0_CH7_BASE) -#define USB0_CH8 ((USB0_CH_TypeDef *)USB0_CH8_BASE) -#define USB0_CH9 ((USB0_CH_TypeDef *)USB0_CH9_BASE) -#define USB0_CH10 ((USB0_CH_TypeDef *)USB0_CH10_BASE) -#define USB0_CH11 ((USB0_CH_TypeDef *)USB0_CH11_BASE) -#define USB0_CH12 ((USB0_CH_TypeDef *)USB0_CH12_BASE) -#define USB0_CH13 ((USB0_CH_TypeDef *)USB0_CH13_BASE) -#define USIC0 ((USIC_GLOBAL_TypeDef *)USIC0_BASE) -#define USIC1 ((USIC_GLOBAL_TypeDef *)USIC1_BASE) -#define USIC0_CH0 ((USIC_CH_TypeDef *)USIC0_CH0_BASE) -#define USIC0_CH1 ((USIC_CH_TypeDef *)USIC0_CH1_BASE) -#define USIC1_CH0 ((USIC_CH_TypeDef *)USIC1_CH0_BASE) -#define USIC1_CH1 ((USIC_CH_TypeDef *)USIC1_CH1_BASE) -#define CAN_xmc ((CAN_GLOBAL_TypeDef *)CAN_BASE) -#define CAN_NODE0 ((CAN_NODE_TypeDef *)CAN_NODE0_BASE) -#define CAN_NODE1 ((CAN_NODE_TypeDef *)CAN_NODE1_BASE) -#define CAN_MO0 ((CAN_MO_TypeDef *)CAN_MO0_BASE) -#define CAN_MO1 ((CAN_MO_TypeDef *)CAN_MO1_BASE) -#define CAN_MO2 ((CAN_MO_TypeDef *)CAN_MO2_BASE) -#define CAN_MO3 ((CAN_MO_TypeDef *)CAN_MO3_BASE) -#define CAN_MO4 ((CAN_MO_TypeDef *)CAN_MO4_BASE) -#define CAN_MO5 ((CAN_MO_TypeDef *)CAN_MO5_BASE) -#define CAN_MO6 ((CAN_MO_TypeDef *)CAN_MO6_BASE) -#define CAN_MO7 ((CAN_MO_TypeDef *)CAN_MO7_BASE) -#define CAN_MO8 ((CAN_MO_TypeDef *)CAN_MO8_BASE) -#define CAN_MO9 ((CAN_MO_TypeDef *)CAN_MO9_BASE) -#define CAN_MO10 ((CAN_MO_TypeDef *)CAN_MO10_BASE) -#define CAN_MO11 ((CAN_MO_TypeDef *)CAN_MO11_BASE) -#define CAN_MO12 ((CAN_MO_TypeDef *)CAN_MO12_BASE) -#define CAN_MO13 ((CAN_MO_TypeDef *)CAN_MO13_BASE) -#define CAN_MO14 ((CAN_MO_TypeDef *)CAN_MO14_BASE) -#define CAN_MO15 ((CAN_MO_TypeDef *)CAN_MO15_BASE) -#define CAN_MO16 ((CAN_MO_TypeDef *)CAN_MO16_BASE) -#define CAN_MO17 ((CAN_MO_TypeDef *)CAN_MO17_BASE) -#define CAN_MO18 ((CAN_MO_TypeDef *)CAN_MO18_BASE) -#define CAN_MO19 ((CAN_MO_TypeDef *)CAN_MO19_BASE) -#define CAN_MO20 ((CAN_MO_TypeDef *)CAN_MO20_BASE) -#define CAN_MO21 ((CAN_MO_TypeDef *)CAN_MO21_BASE) -#define CAN_MO22 ((CAN_MO_TypeDef *)CAN_MO22_BASE) -#define CAN_MO23 ((CAN_MO_TypeDef *)CAN_MO23_BASE) -#define CAN_MO24 ((CAN_MO_TypeDef *)CAN_MO24_BASE) -#define CAN_MO25 ((CAN_MO_TypeDef *)CAN_MO25_BASE) -#define CAN_MO26 ((CAN_MO_TypeDef *)CAN_MO26_BASE) -#define CAN_MO27 ((CAN_MO_TypeDef *)CAN_MO27_BASE) -#define CAN_MO28 ((CAN_MO_TypeDef *)CAN_MO28_BASE) -#define CAN_MO29 ((CAN_MO_TypeDef *)CAN_MO29_BASE) -#define CAN_MO30 ((CAN_MO_TypeDef *)CAN_MO30_BASE) -#define CAN_MO31 ((CAN_MO_TypeDef *)CAN_MO31_BASE) -#define CAN_MO32 ((CAN_MO_TypeDef *)CAN_MO32_BASE) -#define CAN_MO33 ((CAN_MO_TypeDef *)CAN_MO33_BASE) -#define CAN_MO34 ((CAN_MO_TypeDef *)CAN_MO34_BASE) -#define CAN_MO35 ((CAN_MO_TypeDef *)CAN_MO35_BASE) -#define CAN_MO36 ((CAN_MO_TypeDef *)CAN_MO36_BASE) -#define CAN_MO37 ((CAN_MO_TypeDef *)CAN_MO37_BASE) -#define CAN_MO38 ((CAN_MO_TypeDef *)CAN_MO38_BASE) -#define CAN_MO39 ((CAN_MO_TypeDef *)CAN_MO39_BASE) -#define CAN_MO40 ((CAN_MO_TypeDef *)CAN_MO40_BASE) -#define CAN_MO41 ((CAN_MO_TypeDef *)CAN_MO41_BASE) -#define CAN_MO42 ((CAN_MO_TypeDef *)CAN_MO42_BASE) -#define CAN_MO43 ((CAN_MO_TypeDef *)CAN_MO43_BASE) -#define CAN_MO44 ((CAN_MO_TypeDef *)CAN_MO44_BASE) -#define CAN_MO45 ((CAN_MO_TypeDef *)CAN_MO45_BASE) -#define CAN_MO46 ((CAN_MO_TypeDef *)CAN_MO46_BASE) -#define CAN_MO47 ((CAN_MO_TypeDef *)CAN_MO47_BASE) -#define CAN_MO48 ((CAN_MO_TypeDef *)CAN_MO48_BASE) -#define CAN_MO49 ((CAN_MO_TypeDef *)CAN_MO49_BASE) -#define CAN_MO50 ((CAN_MO_TypeDef *)CAN_MO50_BASE) -#define CAN_MO51 ((CAN_MO_TypeDef *)CAN_MO51_BASE) -#define CAN_MO52 ((CAN_MO_TypeDef *)CAN_MO52_BASE) -#define CAN_MO53 ((CAN_MO_TypeDef *)CAN_MO53_BASE) -#define CAN_MO54 ((CAN_MO_TypeDef *)CAN_MO54_BASE) -#define CAN_MO55 ((CAN_MO_TypeDef *)CAN_MO55_BASE) -#define CAN_MO56 ((CAN_MO_TypeDef *)CAN_MO56_BASE) -#define CAN_MO57 ((CAN_MO_TypeDef *)CAN_MO57_BASE) -#define CAN_MO58 ((CAN_MO_TypeDef *)CAN_MO58_BASE) -#define CAN_MO59 ((CAN_MO_TypeDef *)CAN_MO59_BASE) -#define CAN_MO60 ((CAN_MO_TypeDef *)CAN_MO60_BASE) -#define CAN_MO61 ((CAN_MO_TypeDef *)CAN_MO61_BASE) -#define CAN_MO62 ((CAN_MO_TypeDef *)CAN_MO62_BASE) -#define CAN_MO63 ((CAN_MO_TypeDef *)CAN_MO63_BASE) -#define VADC ((VADC_GLOBAL_TypeDef *)VADC_BASE) -#define VADC_G0 ((VADC_G_TypeDef *)VADC_G0_BASE) -#define VADC_G1 ((VADC_G_TypeDef *)VADC_G1_BASE) -#define VADC_G2 ((VADC_G_TypeDef *)VADC_G2_BASE) -#define VADC_G3 ((VADC_G_TypeDef *)VADC_G3_BASE) -#define DSD ((DSD_GLOBAL_TypeDef *)DSD_BASE) -#define DSD_CH0 ((DSD_CH_TypeDef *)DSD_CH0_BASE) -#define DSD_CH1 ((DSD_CH_TypeDef *)DSD_CH1_BASE) -#define DSD_CH2 ((DSD_CH_TypeDef *)DSD_CH2_BASE) -#define DSD_CH3 ((DSD_CH_TypeDef *)DSD_CH3_BASE) -#define DAC ((DAC_GLOBAL_TypeDef *)DAC_BASE) -#define CCU40 ((CCU4_GLOBAL_TypeDef *)CCU40_BASE) -#define CCU41 ((CCU4_GLOBAL_TypeDef *)CCU41_BASE) -#define CCU42 ((CCU4_GLOBAL_TypeDef *)CCU42_BASE) -#define CCU43 ((CCU4_GLOBAL_TypeDef *)CCU43_BASE) -#define CCU40_CC40 ((CCU4_CC4_TypeDef *)CCU40_CC40_BASE) -#define CCU40_CC41 ((CCU4_CC4_TypeDef *)CCU40_CC41_BASE) -#define CCU40_CC42 ((CCU4_CC4_TypeDef *)CCU40_CC42_BASE) -#define CCU40_CC43 ((CCU4_CC4_TypeDef *)CCU40_CC43_BASE) -#define CCU41_CC40 ((CCU4_CC4_TypeDef *)CCU41_CC40_BASE) -#define CCU41_CC41 ((CCU4_CC4_TypeDef *)CCU41_CC41_BASE) -#define CCU41_CC42 ((CCU4_CC4_TypeDef *)CCU41_CC42_BASE) -#define CCU41_CC43 ((CCU4_CC4_TypeDef *)CCU41_CC43_BASE) -#define CCU42_CC40 ((CCU4_CC4_TypeDef *)CCU42_CC40_BASE) -#define CCU42_CC41 ((CCU4_CC4_TypeDef *)CCU42_CC41_BASE) -#define CCU42_CC42 ((CCU4_CC4_TypeDef *)CCU42_CC42_BASE) -#define CCU42_CC43 ((CCU4_CC4_TypeDef *)CCU42_CC43_BASE) -#define CCU43_CC40 ((CCU4_CC4_TypeDef *)CCU43_CC40_BASE) -#define CCU43_CC41 ((CCU4_CC4_TypeDef *)CCU43_CC41_BASE) -#define CCU43_CC42 ((CCU4_CC4_TypeDef *)CCU43_CC42_BASE) -#define CCU43_CC43 ((CCU4_CC4_TypeDef *)CCU43_CC43_BASE) -#define CCU80 ((CCU8_GLOBAL_TypeDef *)CCU80_BASE) -#define CCU81 ((CCU8_GLOBAL_TypeDef *)CCU81_BASE) -#define CCU80_CC80 ((CCU8_CC8_TypeDef *)CCU80_CC80_BASE) -#define CCU80_CC81 ((CCU8_CC8_TypeDef *)CCU80_CC81_BASE) -#define CCU80_CC82 ((CCU8_CC8_TypeDef *)CCU80_CC82_BASE) -#define CCU80_CC83 ((CCU8_CC8_TypeDef *)CCU80_CC83_BASE) -#define CCU81_CC80 ((CCU8_CC8_TypeDef *)CCU81_CC80_BASE) -#define CCU81_CC81 ((CCU8_CC8_TypeDef *)CCU81_CC81_BASE) -#define CCU81_CC82 ((CCU8_CC8_TypeDef *)CCU81_CC82_BASE) -#define CCU81_CC83 ((CCU8_CC8_TypeDef *)CCU81_CC83_BASE) -#define HRPWM0 ((HRPWM0_Type *)HRPWM0_BASE) -#define HRPWM0_CSG0 ((HRPWM0_CSG_Type *)HRPWM0_CSG0_BASE) -#define HRPWM0_CSG1 ((HRPWM0_CSG_Type *)HRPWM0_CSG1_BASE) -#define HRPWM0_CSG2 ((HRPWM0_CSG_Type *)HRPWM0_CSG2_BASE) -#define HRPWM0_HRC0 ((HRPWM0_HRC_Type *)HRPWM0_HRC0_BASE) -#define HRPWM0_HRC1 ((HRPWM0_HRC_Type *)HRPWM0_HRC1_BASE) -#define HRPWM0_HRC2 ((HRPWM0_HRC_Type *)HRPWM0_HRC2_BASE) -#define HRPWM0_HRC3 ((HRPWM0_HRC_Type *)HRPWM0_HRC3_BASE) -#define POSIF0 ((POSIF_GLOBAL_TypeDef *)POSIF0_BASE) -#define POSIF1 ((POSIF_GLOBAL_TypeDef *)POSIF1_BASE) -#define PORT0 ((PORT0_Type *)PORT0_BASE) -#define PORT1 ((PORT1_Type *)PORT1_BASE) -#define PORT2 ((PORT2_Type *)PORT2_BASE) -#define PORT3 ((PORT3_Type *)PORT3_BASE) -#define PORT4 ((PORT4_Type *)PORT4_BASE) -#define PORT5 ((PORT5_Type *)PORT5_BASE) -#define PORT14 ((PORT14_Type *)PORT14_BASE) -#define PORT15 ((PORT15_Type *)PORT15_BASE) - -/** @} */ /* End of group Device_Peripheral_Registers */ -/** @} */ /* End of group XMC4400 */ -/** @} */ /* End of group Infineon */ - -#ifdef __cplusplus -} -#endif - -#endif /* XMC4400_H */ diff --git a/variants/XMC4400/config/XMC4400_Platform2GO/pins_arduino.h b/variants/XMC4400/config/XMC4400_Platform2GO/pins_arduino.h deleted file mode 100644 index 8f404dfc..00000000 --- a/variants/XMC4400/config/XMC4400_Platform2GO/pins_arduino.h +++ /dev/null @@ -1,448 +0,0 @@ -/* - pins_arduino.h - Pin definition functions for Arduino - Part of Arduino - http://www.arduino.cc/ - - Copyright (c) 2007 David A. Mellis - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General - Public License along with this library; if not, write to the - Free Software Foundation, Inc., 59 Temple Place, Suite 330, - Boston, MA 02111-1307 USA - - Copyright (c) 2019 Infineon Technologies AG - This file has been modified for the XMC microcontroller series. -*/ -#ifndef PINS_ARDUINO_H_ -#define PINS_ARDUINO_H_ - -//**************************************************************************** -// @Project Includes -//**************************************************************************** -#include - -//**************************************************************************** -// @Defines -//**************************************************************************** -#define XMC_BOARD XMC 4400 Platform 2GO - -/* On board LED is ON when digital output is 1, HIGH, TRUE, ON */ -#define XMC_LED_ON 1 - -// Following were defines now evaluated by compilation as const variables -// After definitions of associated mapping arrays -extern const uint8_t NUM_DIGITAL; -extern const uint8_t GND; -extern const uint8_t NUM_PWM4; -extern const uint8_t NUM_PWM8; -extern const uint8_t NUM_PWM; -extern const uint8_t NUM_INTERRUPT; -extern const uint8_t NUM_ANALOG_INPUTS; -#ifdef DAC -extern const uint8_t NUM_ANALOG_OUTPUTS; -#endif -#define NUM_LEDS 2 -#define NUM_BUTTONS 2 -#define NUM_SERIAL 1 -#define NUM_TONE_PINS 16 -#define NUM_TASKS_VARIANT 32 -#define NUM_SPI 1 -#define NUM_I2C 1 - -// Indicate unit has RTC/Alarm -#define HAS_RTC 1 - -// Generate 490Hz @fCCU=144MHz -#define PWM4_TIMER_PERIOD (0x11EF) -// Generate 490Hz @fCCU=144MHz -#define PWM8_TIMER_PERIOD (0x11EF) - -#define PCLK 64000000u - -#define PIN_SPI_SS 10 -#define PIN_SPI_MOSI 11 -#define PIN_SPI_MISO 12 -#define PIN_SPI_SCK 13 - -extern uint8_t SS; -extern uint8_t MOSI; -extern uint8_t MISO; -extern uint8_t SCK; - -#define A0 0 -#define A1 1 -#define A2 2 -#define A3 3 -#define A4 4 -#define A5 5 -// Additional ADC ports starting here -#define A6 6 -#define A7 7 -#define A8 8 -#define A9 9 -#define A10 10 -#define A11 11 -#define A12 12 -#define A13 13 -#define A14 14 -#define A15 15 -#define A16 16 -#define A17 17 - -#define LED1 65 -#define LED2 62 -#define LED_BUILTIN LED1 - -#define BUTTON1 68 -#define BUTTON2 57 - -#define digitalPinToInterrupt(p) ((p) == 2 ? 0 : ((p) == 3 ? 1 : NOT_AN_INTERRUPT)) - -#ifdef ARDUINO_MAIN -// Mapping of digital pins and comments -const XMC_PORT_PIN_t mapping_port_pin[] = { - /* 0 */ {XMC_GPIO_PORT2, 15}, // RX P2.15 X1-4 - /* 1 */ {XMC_GPIO_PORT2, 14}, // TX P2.14 X1-3 - /* 2 */ {XMC_GPIO_PORT1, 0}, // GPIO / External INT 0 P1.0 X1-11 - /* 3 */ {XMC_GPIO_PORT3, 6}, // PWM42-0 / PWM0 / External INT 1 P3.6 X2-6 - /* 4 */ {XMC_GPIO_PORT1, 6}, // GPIO / IO_0 P1.6 X1-7 - /* 5 */ {XMC_GPIO_PORT3, 3}, // PWM42-3 output / PWM1 P3.3 X2-5 - /* 6 */ {XMC_GPIO_PORT3, 4}, // PWM42-2 output / PWM2 P3.4 X2-8 - /* 7 */ {XMC_GPIO_PORT1, 14}, // GPIO / IO_1 P1.14 X1-21 - /* 8 */ {XMC_GPIO_PORT4, 1}, // GPIO / IO_2 P4.1 X1-6 - /* 9 */ {XMC_GPIO_PORT0, 11}, // PWM80-31 output / PWM3 P0.11 X2-7 - /* 10 */ {XMC_GPIO_PORT0, 2}, // SPI-SS / PWM80-01 / PWM4 P0.2 X2-16 - /* 11 */ {XMC_GPIO_PORT1, 9}, // SPI-MOSI P1.9 X1-10 - /* 12 */ {XMC_GPIO_PORT0, 0}, // SPI-MISO P0.0 X2-18 - /* 13 */ {XMC_GPIO_PORT1, 8}, // SPI-SCK / GPIO P1.8 X1-9 - /* 14 */ {XMC_GPIO_PORT2, 5}, // I2C Data / Address SDA / A4 / PWM41-0 P2.5 (Hardwired to A4) - // X1-34 - /* 15 */ {XMC_GPIO_PORT3, 0}, // I2C Clock SCL / A5 - ADC Input P3.0 (Hardwired to A5) - // X2-19 - /* 16 */ {XMC_GPIO_PORT14, 0}, // A0 / ADC Input P14.0 (INPUT ONLY) - /* 17 */ {XMC_GPIO_PORT14, 1}, // A1 / ADC Input P14.1 (INPUT ONLY) - /* 18 */ {XMC_GPIO_PORT14, 2}, // A2 / ADC Input P14.2 (INPUT ONLY) - /* 19 */ {XMC_GPIO_PORT14, 3}, // A3 / ADC Input P14.3 (INPUT ONLY) - // X2-31 - /* 20 */ {XMC_GPIO_PORT14, 4}, // A4 / ADC Input / SDA / GPIO P14.4 (Hardwired to - // SDA) X2-24 - /* 21 */ {XMC_GPIO_PORT14, 5}, // A5 / ADC Input / SCL P14.5 (Hardwired to - // SCL) X2-30 - /* 22 */ {XMC_GPIO_PORT1, 15}, // USB Debug RX P1.15 X1-22 - /* 23 */ {XMC_GPIO_PORT0, 5}, // USB Debug TX P0.5 X2-9 - - // Additional pins for port X1 starting here - /* 24 */ {XMC_GPIO_PORT2, 10}, // GPIO / ETH_LED P2.10 X1-37 - /* 25 */ {XMC_GPIO_PORT2, 8}, // GPIO / ETH_TXDO / PWM80-32 P2.8 X1-35 - /* 26 */ {XMC_GPIO_PORT2, 4}, // GPIO / ETH_RXER / PWM41-1 P2.4 X1-33 - /* 27 */ {XMC_GPIO_PORT2, 3}, // ETH_RXD1 / PWM41-2 P2.3 X1-32 - /* 28 */ {XMC_GPIO_PORT2, 2}, // GPIO / ETH_RXDO / PWM41-3 P2.2 X1-31 - /* 29 */ {XMC_GPIO_PORT2, 0}, // GPIO / ETH_MDIO / PWM81-21 P2.0 X1-29 - /* 30 */ {XMC_GPIO_PORT2, 6}, // PWM80-13 / GPIO4_2GO_2 P2.6 X1-27 - /* 31 */ {XMC_GPIO_PORT5, 2}, // GPIO / RST P5.2 X1-25 - /* 32 */ {XMC_GPIO_PORT5, 0}, // GPIO1_2GO_1 P5.0 X1-23 - /* 33 */ {XMC_GPIO_PORT1, 12}, // GPIO / CAN_TX P1.12 X1-19 - /* 34 */ {XMC_GPIO_PORT1, 10}, // GPIO / GPIO2_2GO_1 P1.10 X1-17 - /* 35 */ {XMC_GPIO_PORT1, 4}, // GPIO / QSPI_IO1 P1.4 X1-15 - /* 36 */ {XMC_GPIO_PORT1, 2}, // GPIO / QSPI_IO3 P1.2 X1-13 - /* 37 */ {XMC_GPIO_PORT4, 0}, // GPIO / GPIO2_2GO_2 P4.0 X1-5 - /* 38 */ {XMC_GPIO_PORT1, 7}, // GPIO / SPI_CS_2GO_2 P1.7 (Chip Select - Slot - // 2) X1-8 - /* 39 */ {XMC_GPIO_PORT1, 1}, // GPIO1_2GO_2 P1.1 X1-12 - /* 40 */ {XMC_GPIO_PORT1, 3}, // GPIO / QSPI_IO3 P1.3 X1-14 - /* 41 */ {XMC_GPIO_PORT1, 5}, // GPIO / QSPI_IO0 P1.5 X1-16 - /* 42 */ {XMC_GPIO_PORT1, 11}, // GPIO / QSPI_CS P1.11 X1-18 - /* 43 */ {XMC_GPIO_PORT1, 13}, // GPIO / CAN_RX P1.13 X1-20 - /* 44 */ {XMC_GPIO_PORT5, 1}, // GPIO / ETH_INT P5.1 X1-24 - /* 45 */ {XMC_GPIO_PORT5, 7}, // PWM81-02 P5.7 X1-26 - /* 46 */ {XMC_GPIO_PORT2, 7}, // PWM80-03 / ETH_MDC P2.7 X1-28 - /* 47 */ {XMC_GPIO_PORT2, 1}, // SWV ""DEBUG Do NOT Use ** P2.1 X1-30 - /* 48 */ {XMC_GPIO_PORT2, 9}, // PWM80-22 / ETH_TXD1 P2.9 X1-36 - /* 49 */ {XMC_GPIO_PORT15, 8}, // A16 / ETH_CLK P15.8 X1-38 - - // Additional pins for port X2 starting here - /* 50 */ {XMC_GPIO_PORT14, 8}, // A14 / DAC 0 Output P14.8 X2-33 - /* 51 */ {XMC_GPIO_PORT15, 2}, // A12 - ADC Input P15.2 (INPUT ONLY) X2-32 - /* 52 */ {XMC_GPIO_PORT14, 15}, // A11 - ADC Input P14.15 (INPUT ONLY) - // X2-29 - /* 53 */ {XMC_GPIO_PORT15, 9}, // A17 - ADC Input / ETH_CRS P15.9 X2-27 - /* 54 */ {XMC_GPIO_PORT14, 6}, // A6 / AN1_2GO_1 - ADC Input P14.6 (INPUT ONLY) X2-25 - /* 55 */ {XMC_GPIO_PORT14, 12}, // A8 / AN1_2GO_2 - ADC Input P14.12 (INPUT ONLY) - // X2-23 - /* 56 */ {XMC_GPIO_PORT14, 14}, // A10 / ADC Input P14.14 (INPUT ONLY) - // X2-21 - /* 57 */ {XMC_GPIO_PORT3, 2}, // BUTTON2 P3.2 X2-17 - /* 58 */ {XMC_GPIO_PORT0, 10}, // INT / GPIO3_2GO_1 P0.10 X2-15 - /* 59 */ {XMC_GPIO_PORT0, 1}, // INT P0.1 X2-13 - /* 60 */ {XMC_GPIO_PORT0, 3}, // INT / GPIO3_2GO_2 P0.3 X2-11 - /* 61 */ {XMC_GPIO_PORT3, 5}, // CS_2GO_1 P3.5 (Chip Select - Slot - // 1) X2-3 - /* 62 */ {XMC_GPIO_PORT0, 7}, // LED2 P0.7 X2-1 - /* 63 */ {XMC_GPIO_PORT0, 8}, // QSPI_CLK P0.8 X2-4 - /* 64 */ {XMC_GPIO_PORT0, 12}, // CS_MB P0.12 (Chip Select - - // MikroBUS) X2-10 - /* 65 */ {XMC_GPIO_PORT0, 6}, // LED1 P0.6 X2-12 - /* 66 */ {XMC_GPIO_PORT0, 4}, // ETH_TXEN P0.4 X2-14 - /* 67 */ {XMC_GPIO_PORT0, 9}, // GPIO4_2GO_1 / PWM80-12 / PWM P0.9 X2-20 - /* 68 */ {XMC_GPIO_PORT3, 1}, // BUTTON1 P3.1 X2-22 - /* 69 */ {XMC_GPIO_PORT14, 13}, // A9 / AN2_2GO_2 - ADC Input P14.13 (INPUT ONLY) - // X2-26 - /* 70 */ {XMC_GPIO_PORT14, 7}, // A7 / AN2_2GO_1 - ADC Input P14.7 (INPUT ONLY) X2-28 - /* 71 */ {XMC_GPIO_PORT15, 3}, // A13 - ADC Input P15.3 (INPUT ONLY) X2-34 - /* 72 */ {XMC_GPIO_PORT14, 9} // A15 / DAC 1 Output P14.9 X2-36 -}; -const uint8_t GND = (sizeof(mapping_port_pin) / sizeof(XMC_PORT_PIN_t)); -const uint8_t NUM_DIGITAL = (sizeof(mapping_port_pin) / sizeof(XMC_PORT_PIN_t)); -; - -const XMC_PIN_INTERRUPT_t mapping_interrupt[] = { - /* 0 */ {CCU40, CCU40_CC43, 3, 0, CCU40_IN3_P1_0}, - /* 1 */ {CCU42, CCU42_CC40, 0, 1, CCU42_IN0_P3_6}}; -const uint8_t NUM_INTERRUPT = (sizeof(mapping_interrupt) / sizeof(XMC_PIN_INTERRUPT_t)); - -/* Mapping of Arduino Pins to PWM4 channels as pin and index in PWM4 channel - mapping array XMC_PWM4_t mapping_pwm4[] - last entry 255 for both parts. - Putting both parts in array means if a PWM4 channel gets reassigned for - another function later a gap in channel numbers will not mess things up */ -const uint8_t mapping_pin_PWM4[][2] = {{3, 0}, // PWM0 - {5, 1}, // PWM1 - {6, 2}, // PWM2 - {14, 3}, // PWM - {26, 4}, // PWM - {27, 5}, // PWM - {28, 6}, // PWM - {255, 255}}; - -/* Configurations of PWM channels for CCU4 type */ -XMC_PWM4_t mapping_pwm4[] = { - {CCU42, CCU42_CC40, 0, mapping_port_pin[3], P3_6_AF_CCU42_OUT0, XMC_CCU4_SLICE_PRESCALER_64, - PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 3 P3.6 - {CCU42, CCU42_CC43, 3, mapping_port_pin[5], P3_3_AF_CCU42_OUT3, XMC_CCU4_SLICE_PRESCALER_64, - PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 5 P3.3 - {CCU42, CCU42_CC42, 2, mapping_port_pin[6], P3_4_AF_CCU42_OUT2, XMC_CCU4_SLICE_PRESCALER_64, - PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 6 P3.4 - {CCU41, CCU41_CC40, 0, mapping_port_pin[14], P2_5_AF_CCU41_OUT0, XMC_CCU4_SLICE_PRESCALER_64, - PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 14 P2.5 - {CCU41, CCU41_CC41, 1, mapping_port_pin[26], P2_4_AF_CCU41_OUT1, XMC_CCU4_SLICE_PRESCALER_64, - PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 26 P2.4 - {CCU41, CCU41_CC42, 2, mapping_port_pin[27], P2_3_AF_CCU41_OUT2, XMC_CCU4_SLICE_PRESCALER_64, - PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 27 P2.3 - {CCU41, CCU41_CC43, 3, mapping_port_pin[28], P2_2_AF_CCU41_OUT3, XMC_CCU4_SLICE_PRESCALER_64, - PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 28 P2.2 -}; -const uint8_t NUM_PWM4 = (sizeof(mapping_pwm4) / sizeof(XMC_PWM4_t)); - -/* Mapping in same manner as PWM4 for PWM8 channels */ -const uint8_t mapping_pin_PWM8[][2] = {{9, 0}, // PWM3 - {10, 1}, // PWM4 - {25, 2}, // PWM - {29, 3}, // PWM - {30, 4}, // PWM - {45, 5}, // PWM - {46, 6}, // PWM - {48, 7}, // PWM - {67, 8}, // PWM - {255, 255}}; - -/* Configurations of PWM channels for CCU8 type */ -XMC_PWM8_t mapping_pwm8[] = { - {CCU80, CCU80_CC83, 3, XMC_CCU8_SLICE_COMPARE_CHANNEL_1, mapping_port_pin[9], - P0_11_AF_CCU80_OUT31, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, - DISABLED}, // PWM disabled 9 P0.11 - {CCU80, CCU80_CC80, 0, XMC_CCU8_SLICE_COMPARE_CHANNEL_1, mapping_port_pin[10], - P0_2_AF_CCU80_OUT01, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, - DISABLED}, // PWM disabled 10 P0.2 - // additional pwm outputs starting here - {CCU80, CCU80_CC83, 3, XMC_CCU8_SLICE_COMPARE_CHANNEL_2, mapping_port_pin[25], - P2_8_AF_CCU80_OUT32, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, - DISABLED}, // PWM disabled 25 P2.8 - {CCU81, CCU81_CC82, 2, XMC_CCU8_SLICE_COMPARE_CHANNEL_1, mapping_port_pin[29], - P2_0_AF_CCU81_OUT21, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, - DISABLED}, // PWM disabled 29 P2.0 - {CCU80, CCU80_CC81, 1, XMC_CCU8_SLICE_COMPARE_CHANNEL_2, mapping_port_pin[30], - P2_6_AF_CCU80_OUT13, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, - DISABLED}, // PWM disabled 30 P2.6 - {CCU81, CCU81_CC80, 0, XMC_CCU8_SLICE_COMPARE_CHANNEL_2, mapping_port_pin[45], - P5_7_AF_CCU81_OUT02, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, - DISABLED}, // PWM disabled 45 P5.7 - {CCU80, CCU80_CC80, 0, XMC_CCU8_SLICE_COMPARE_CHANNEL_2, mapping_port_pin[46], - P2_7_AF_CCU80_OUT03, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, - DISABLED}, // PWM disabled 46 P2.7 - {CCU80, CCU80_CC82, 2, XMC_CCU8_SLICE_COMPARE_CHANNEL_2, mapping_port_pin[48], - P2_9_AF_CCU80_OUT22, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, - DISABLED}, // PWM disabled 48 P2.9 - {CCU80, CCU80_CC81, 1, XMC_CCU8_SLICE_COMPARE_CHANNEL_2, mapping_port_pin[67], - P0_9_AF_CCU80_OUT12, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, - DISABLED} // PWM disabled 67 P0.9 -}; - -const uint8_t NUM_PWM8 = (sizeof(mapping_pwm8) / sizeof(XMC_PWM8_t)); -const uint8_t NUM_PWM = - (sizeof(mapping_pwm4) / sizeof(XMC_PWM4_t)) + (sizeof(mapping_pwm8) / sizeof(XMC_PWM8_t)); - - /* Analog Pin mappings and configurations */ - #ifdef DAC -const uint8_t mapping_pin_DAC[][2] = {{50, 0}, {72, 1}, {255, 255}}; - -/* Analog Pin mappings and configurations */ -XMC_ARD_DAC_t mapping_dac[] = {{XMC_DAC0, 1, 12}, {XMC_DAC0, 0, 12}}; -const uint8_t NUM_ANALOG_OUTPUTS = (sizeof(mapping_dac) / sizeof(XMC_ARD_DAC_t)); - #endif - -// Result reg numbers are now equal to channel numbers -XMC_ADC_t mapping_adc[] = { - {VADC, 0, VADC_G0, 0, 0, DISABLED}, {VADC, 1, VADC_G0, 0, 1, DISABLED}, - {VADC, 2, VADC_G1, 1, 2, DISABLED}, {VADC, 3, VADC_G1, 1, 3, DISABLED}, - {VADC, 0, VADC_G2, 2, 0, DISABLED}, {VADC, 1, VADC_G2, 2, 1, DISABLED}, - {VADC, 6, VADC_G2, 2, 6, DISABLED}, {VADC, 5, VADC_G2, 2, 5, DISABLED}, - {VADC, 3, VADC_G2, 2, 3, DISABLED}, {VADC, 7, VADC_G1, 1, 7, DISABLED}, - {VADC, 5, VADC_G1, 1, 5, DISABLED}, {VADC, 7, VADC_G0, 0, 7, DISABLED}, - {VADC, 7, VADC_G3, 3, 7, DISABLED}, {VADC, 1, VADC_G1, 1, 1, DISABLED}, - {VADC, 0, VADC_G1, 1, 0, DISABLED}, {VADC, 6, VADC_G3, 3, 6, DISABLED}, - {VADC, 6, VADC_G0, 0, 6, DISABLED}, {VADC, 4, VADC_G1, 1, 4, DISABLED}, -}; -const uint8_t NUM_ANALOG_INPUTS = (sizeof(mapping_adc) / sizeof(XMC_ADC_t)); - -/* - * UART objects - * - * See many XMC1x00 pins_arduino.h for proper way to handle HOSTPC - * NUM_SERIAL defines number of PHYSICAL ports NOT configurations - */ -RingBuffer rx_buffer_0; -RingBuffer tx_buffer_0; - -XMC_UART_t XMC_UART_0 = { - .channel = XMC_UART1_CH0, - .rx = - { - #ifdef SERIAL_HOSTPC - .port = (XMC_GPIO_PORT_t *)PORT0_BASE, .pin = (uint8_t)5 - #elif SERIAL_ONBOARD - .port = (XMC_GPIO_PORT_t *)PORT2_BASE, .pin = (uint8_t)15 - #endif - }, - .rx_config = {.mode = XMC_GPIO_MODE_INPUT_TRISTATE, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .output_strength = XMC_GPIO_OUTPUT_STRENGTH_STRONG_SOFT_EDGE}, - .tx = - { - #ifdef SERIAL_HOSTPC - .port = (XMC_GPIO_PORT_t *)PORT1_BASE, .pin = (uint8_t)15 - #elif SERIAL_ONBOARD - .port = (XMC_GPIO_PORT_t *)PORT2_BASE, .pin = (uint8_t)14 - #endif - }, - .tx_config = - { - #ifdef SERIAL_HOSTPC - .mode = (XMC_GPIO_MODE_t)XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT4, - #elif SERIAL_ONBOARD - .mode = (XMC_GPIO_MODE_t)XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT2, - #endif - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .output_strength = XMC_GPIO_OUTPUT_STRENGTH_STRONG_SOFT_EDGE}, - #ifdef SERIAL_HOSTPC - .input_source_dx0 = (XMC_USIC_INPUT_t)USIC1_C0_DX0_P0_5, - #elif SERIAL_ONBOARD - .input_source_dx0 = (XMC_USIC_INPUT_t)USIC1_C0_DX0_P2_15, - #endif - .input_source_dx1 = XMC_INPUT_INVALID, - .input_source_dx2 = XMC_INPUT_INVALID, - .input_source_dx3 = XMC_INPUT_INVALID, - .irq_num = USIC1_0_IRQn, - .irq_service_request = 0}; - -// Single Hardware Serial object for both UART interfaces -HardwareSerial Serial(&XMC_UART_0, &rx_buffer_0, &tx_buffer_0); - -// SPI instance -XMC_SPI_t XMC_SPI_0 = { - .channel = XMC_SPI1_CH1, - .channel_config = {.baudrate = 20003906U, - .bus_mode = (XMC_SPI_CH_BUS_MODE_t)XMC_SPI_CH_BUS_MODE_MASTER, - .selo_inversion = XMC_SPI_CH_SLAVE_SEL_INV_TO_MSLS, - .parity_mode = XMC_USIC_CH_PARITY_MODE_NONE}, - .mosi = {.port = (XMC_GPIO_PORT_t *)PORT1_BASE, .pin = (uint8_t)9}, - .mosi_config = {.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT4, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .output_strength = XMC_GPIO_OUTPUT_STRENGTH_MEDIUM}, - .miso = {.port = (XMC_GPIO_PORT_t *)PORT0_BASE, .pin = (uint8_t)0}, - .miso_config = - { - .mode = XMC_GPIO_MODE_INPUT_TRISTATE, - }, - .input_source = XMC_INPUT_D, - .sclkout = {.port = (XMC_GPIO_PORT_t *)PORT1_BASE, .pin = (uint8_t)8}, - .sclkout_config = {.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT4, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .output_strength = XMC_GPIO_OUTPUT_STRENGTH_MEDIUM}, -}; - -// I2C instance -XMC_I2C_t XMC_I2C_0 = {.channel = XMC_I2C0_CH1, - .channel_config = {.baudrate = (uint32_t)(100000U), .address = 0U}, - .sda = {.port = (XMC_GPIO_PORT_t *)PORT2_BASE, .pin = (uint8_t)5}, - .sda_config = {.mode = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT2, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH}, - .scl = {.port = (XMC_GPIO_PORT_t *)PORT3_BASE, .pin = (uint8_t)0}, - .scl_config = {.mode = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT2, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH}, - .input_source_dx0 = XMC_INPUT_B, - .input_source_dx1 = XMC_INPUT_B, - .slave_receive_irq_num = (IRQn_Type)91, - .slave_receive_irq_service_request = 1, - .protocol_irq_num = (IRQn_Type)92, - .protocol_irq_service_request = 2}; - - // XMC CAN instance - #ifdef CAN_xmc -XMC_ARD_CAN_t XMC_CAN_0 = {.can_node = CAN_NODE1, - .can_node_num = XMC_NODE_NUM_1, - .can_clock = XMC_CAN_CANCLKSRC_FPERI, - .can_frequency = (uint32_t)144000000, - .rx = {.port = (XMC_GPIO_PORT_t *)PORT1_BASE, .pin = (uint8_t)13}, - .rx_config = {.mode = XMC_GPIO_MODE_INPUT_TRISTATE}, - .tx = {.port = (XMC_GPIO_PORT_t *)PORT1_BASE, .pin = (uint8_t)12}, - .tx_config = {.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT2}, - .node_input = CAN_NODE1_RXD_P1_13, - .irq_num = CAN0_7_IRQn, - .irq_service_request = 7u}; - #endif - - // Serial Interrupt and event handling - #ifdef __cplusplus -extern "C" { - #endif -void serialEventRun(); -void serialEvent() __attribute__((weak)); - -void serialEventRun() { - if (serialEvent) { - if (Serial.available()) - serialEvent(); - } -} - -void USIC1_0_IRQHandler() { Serial.IrqHandler(); } - - #ifdef __cplusplus -} - #endif -#endif /* ARDUINO_MAIN*/ - -#ifdef __cplusplus -extern HardwareSerial Serial; -#endif /* cplusplus */ - -#endif diff --git a/variants/XMC4400/linker_script.ld b/variants/XMC4400/linker_script.ld deleted file mode 100644 index e38b8e94..00000000 --- a/variants/XMC4400/linker_script.ld +++ /dev/null @@ -1,292 +0,0 @@ -/** - * @file XMC4400x512.ld - * @date 2017-04-20 - * - * @cond - ********************************************************************************************************************* - * Linker file for the GNU C Compiler v1.8 - * Supported devices: XMC4400-F100x512 - * XMC4400-F64x512 - * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* - * - * Change History - * -------------- - * - * 2015-07-07: - * - Product splitting - * - Copyright notice update - * - * 2015-11-24: - * - Compatibility with GCC 4.9 2015q2 - * - * 2016-03-08: - * - Fix size of BSS and DATA sections to be multiple of 4 - * - Add assertion to check that region SRAM_combined does not overflowed no_init section - * - * 2017-04-07: - * - Added new symbols __text_size and eText - * - * 2017-04-20: - * - Change vtable location to flash area to save ram - * - * @endcond - * - */ - -OUTPUT_FORMAT("elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(Reset_Handler) - -MEMORY -{ - FLASH_1_cached(RX) : ORIGIN = 0x08000000, LENGTH = 0x80000 - FLASH_1_uncached(RX) : ORIGIN = 0x0C000000, LENGTH = 0x80000 - PSRAM_1(!RX) : ORIGIN = 0x1FFFC000, LENGTH = 0x4000 - DSRAM_1_system(!RX) : ORIGIN = 0x20000000, LENGTH = 0x8000 - DSRAM_2_comm(!RX) : ORIGIN = 0x20008000, LENGTH = 0x8000 - SRAM_combined(!RX) : ORIGIN = 0x1FFFC000, LENGTH = 0x14000 -} - -stack_size = DEFINED(stack_size) ? stack_size : 2048; -no_init_size = 64; - -SECTIONS -{ - /* TEXT section */ - - .text : - { - sText = .; - KEEP(*(.reset)); - *(.text .text.* .gnu.linkonce.t.*); - - /* C++ Support */ - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata .rodata.*) - *(.gnu.linkonce.r*) - - *(vtable) - - . = ALIGN(4); - } > FLASH_1_cached AT > FLASH_1_uncached - - .eh_frame_hdr : ALIGN (4) - { - KEEP (*(.eh_frame_hdr)) - } > FLASH_1_cached AT > FLASH_1_uncached - - .eh_frame : ALIGN (4) - { - KEEP (*(.eh_frame)) - } > FLASH_1_cached AT > FLASH_1_uncached - - /* Exception handling, exidx needs a dedicated section */ - .ARM.extab : ALIGN (4) - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH_1_cached AT > FLASH_1_uncached - - . = ALIGN(4); - __exidx_start = .; - .ARM.exidx : ALIGN (4) - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH_1_cached AT > FLASH_1_uncached - __exidx_end = .; - . = ALIGN(4); - - /* DSRAM layout (Lowest to highest)*/ - Stack (NOLOAD) : - { - __stack_start = .; - . = . + stack_size; - __stack_end = .; - __initial_sp = .; - } > SRAM_combined - - /* functions with __attribute__((section(".ram_code"))) */ - .ram_code : - { - . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */ - __ram_code_start = .; - *(.ram_code) - . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */ - __ram_code_end = .; - } > SRAM_combined AT > FLASH_1_uncached - __ram_code_load = LOADADDR (.ram_code); - __ram_code_size = __ram_code_end - __ram_code_start; - - /* Standard DATA and user defined DATA/BSS/CONST sections */ - .data : - { - . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */ - __data_start = .; - * (.data); - * (.data*); - *(*.data); - *(.gnu.linkonce.d*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */ - __data_end = .; - } > SRAM_combined AT > FLASH_1_uncached - __data_load = LOADADDR (.data); - __data_size = __data_end - __data_start; - - __text_size = (__exidx_end - sText) + __data_size + __ram_code_size; - eText = sText + __text_size; - - /* BSS section */ - .bss (NOLOAD) : - { - . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */ - __bss_start = .; - * (.bss); - * (.bss*); - * (COMMON); - *(.gnu.linkonce.b*) - . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */ - __bss_end = .; - } > SRAM_combined - __bss_size = __bss_end - __bss_start; - - /* Shift location counter, so that ETH_RAM and USB_RAM are located above DSRAM_1_system */ - __shift_loc = (__bss_end >= ORIGIN(DSRAM_1_system)) ? 0 : (ORIGIN(DSRAM_1_system) - __bss_end); - - USB_RAM (__bss_end + __shift_loc) (NOLOAD) : - { - . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */ - USB_RAM_start = .; - *(USB_RAM) - . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */ - USB_RAM_end = .; - } > SRAM_combined - USB_RAM_size = USB_RAM_end - USB_RAM_start; - - ETH_RAM (USB_RAM_end) (NOLOAD) : - { - . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */ - ETH_RAM_start = .; - *(ETH_RAM) - . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */ - ETH_RAM_end = .; - . = ALIGN(8); - Heap_Bank1_Start = .; - } > SRAM_combined - ETH_RAM_size = ETH_RAM_end - ETH_RAM_start; - - /* .no_init section contains chipid, SystemCoreClock and trimming data. See system.c file */ - .no_init ORIGIN(SRAM_combined) + LENGTH(SRAM_combined) - no_init_size (NOLOAD) : - { - Heap_Bank1_End = .; - * (.no_init); - } > SRAM_combined - - /* Heap - Bank1*/ - Heap_Bank1_Size = Heap_Bank1_End - Heap_Bank1_Start; - - ASSERT(Heap_Bank1_Start <= Heap_Bank1_End, "region SRAM_combined overflowed no_init section") - - /DISCARD/ : - { - *(.comment) - } - - .stab 0 (NOLOAD) : { *(.stab) } - .stabstr 0 (NOLOAD) : { *(.stabstr) } - - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_pubtypes 0 : { *(.debug_pubtypes) } - - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - - /* DWARF 2.1 */ - .debug_ranges 0 : { *(.debug_ranges) } - - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - - /* Build attributes */ - .build_attributes 0 : { *(.ARM.attributes) } -} diff --git a/variants/XMC4400/startup_XMC4400.S b/variants/XMC4400/startup_XMC4400.S deleted file mode 100644 index 9440ee47..00000000 --- a/variants/XMC4400/startup_XMC4400.S +++ /dev/null @@ -1,452 +0,0 @@ -/********************************************************************************************************************* - * @file startup_XMC4400.S - * @brief CMSIS Core Device Startup File for Infineon XMC4400 Device Series - * @version V1.0 - * @date 01 June 2016 - * - * @cond - ********************************************************************************************************************* - * Copyright (c) 2012-2016, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* - * - **************************** Change history ******************************** - * V0.1,Sep, 13, 2012 ES : initial version - * V0.2,Oct, 12, 2012 PKB: C++ support - * V0.3,Jan, 26, 2013 PKB: Workaround for prefetch bug - * V0.4,Jul, 29, 2013 PKB: AAPCS violation in V0.3 fixed - * V0.5,Feb, 05, 2014 PKB: Removed redundant alignment code from copy+clear funcs - * V0.6,May, 05, 2014 JFT: Added ram_code section - * V0.7,Nov, 25, 2014 JFT: CPU workaround disabled. Single default handler. - * Removed DAVE3 dependency - * V0.8,Jan, 05, 2016 JFT: Fix .reset section attributes - * V0.9,March,04,2016 JFT: Fix weak definition of Veneers. - * Only relevant for AA, which needs ENABLE_PMU_CM_001_WORKAROUND - * V1.0,June ,01,2016 JFT: Rename ENABLE_CPU_CM_001_WORKAROUND to ENABLE_PMU_CM_001_WORKAROUND - * Action required: If using AA step, use ENABLE_PMU_CM_001_WORKAROUND instead of ENABLE_CPU_CM_001_WORKAROUND - * @endcond - */ - -/* ===========START : MACRO DEFINITION MACRO DEFINITION ================== */ - -.macro Entry Handler -#if defined(ENABLE_PMU_CM_001_WORKAROUND) - .long \Handler\()_Veneer -#else - .long \Handler -#endif -.endm - -.macro Insert_ExceptionHandler Handler_Func - .weak \Handler_Func - .thumb_set \Handler_Func, Default_Handler - -#if defined(ENABLE_PMU_CM_001_WORKAROUND) - .weak \Handler_Func\()_Veneer - .type \Handler_Func\()_Veneer, %function -\Handler_Func\()_Veneer: - push {r0, lr} - ldr r0, =\Handler_Func - blx r0 - pop {r0, pc} - .size \Handler_Func\()_Veneer, . - \Handler_Func\()_Veneer -#endif -.endm - -/* =============END : MACRO DEFINITION MACRO DEFINITION ================== */ - -/* ================== START OF VECTOR TABLE DEFINITION ====================== */ -/* Vector Table - This gets programed into VTOR register by onchip BootROM */ - .syntax unified - - .section .reset, "a", %progbits - - .align 2 - .globl __Vectors - .type __Vectors, %object -__Vectors: - .long __initial_sp /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - - Entry NMI_Handler /* NMI Handler */ - Entry HardFault_Handler /* Hard Fault Handler */ - Entry MemManage_Handler /* MPU Fault Handler */ - Entry BusFault_Handler /* Bus Fault Handler */ - Entry UsageFault_Handler /* Usage Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - Entry SVC_Handler /* SVCall Handler */ - Entry DebugMon_Handler /* Debug Monitor Handler */ - .long 0 /* Reserved */ - Entry PendSV_Handler /* PendSV Handler */ - Entry SysTick_Handler /* SysTick Handler */ - - /* Interrupt Handlers for Service Requests (SR) from XMC4400 Peripherals */ - Entry SCU_0_IRQHandler /* Handler name for SR SCU_0 */ - Entry ERU0_0_IRQHandler /* Handler name for SR ERU0_0 */ - Entry ERU0_1_IRQHandler /* Handler name for SR ERU0_1 */ - Entry ERU0_2_IRQHandler /* Handler name for SR ERU0_2 */ - Entry ERU0_3_IRQHandler /* Handler name for SR ERU0_3 */ - Entry ERU1_0_IRQHandler /* Handler name for SR ERU1_0 */ - Entry ERU1_1_IRQHandler /* Handler name for SR ERU1_1 */ - Entry ERU1_2_IRQHandler /* Handler name for SR ERU1_2 */ - Entry ERU1_3_IRQHandler /* Handler name for SR ERU1_3 */ - .long 0 /* Not Available */ - .long 0 /* Not Available */ - .long 0 /* Not Available */ - Entry PMU0_0_IRQHandler /* Handler name for SR PMU0_0 */ - .long 0 /* Not Available */ - Entry VADC0_C0_0_IRQHandler /* Handler name for SR VADC0_C0_0 */ - Entry VADC0_C0_1_IRQHandler /* Handler name for SR VADC0_C0_1 */ - Entry VADC0_C0_2_IRQHandler /* Handler name for SR VADC0_C0_1 */ - Entry VADC0_C0_3_IRQHandler /* Handler name for SR VADC0_C0_3 */ - Entry VADC0_G0_0_IRQHandler /* Handler name for SR VADC0_G0_0 */ - Entry VADC0_G0_1_IRQHandler /* Handler name for SR VADC0_G0_1 */ - Entry VADC0_G0_2_IRQHandler /* Handler name for SR VADC0_G0_2 */ - Entry VADC0_G0_3_IRQHandler /* Handler name for SR VADC0_G0_3 */ - Entry VADC0_G1_0_IRQHandler /* Handler name for SR VADC0_G1_0 */ - Entry VADC0_G1_1_IRQHandler /* Handler name for SR VADC0_G1_1 */ - Entry VADC0_G1_2_IRQHandler /* Handler name for SR VADC0_G1_2 */ - Entry VADC0_G1_3_IRQHandler /* Handler name for SR VADC0_G1_3 */ - Entry VADC0_G2_0_IRQHandler /* Handler name for SR VADC0_G2_0 */ - Entry VADC0_G2_1_IRQHandler /* Handler name for SR VADC0_G2_1 */ - Entry VADC0_G2_2_IRQHandler /* Handler name for SR VADC0_G2_2 */ - Entry VADC0_G2_3_IRQHandler /* Handler name for SR VADC0_G2_3 */ - Entry VADC0_G3_0_IRQHandler /* Handler name for SR VADC0_G3_0 */ - Entry VADC0_G3_1_IRQHandler /* Handler name for SR VADC0_G3_1 */ - Entry VADC0_G3_2_IRQHandler /* Handler name for SR VADC0_G3_2 */ - Entry VADC0_G3_3_IRQHandler /* Handler name for SR VADC0_G3_3 */ - Entry DSD0_0_IRQHandler /* Handler name for SR DSD_SRM_0 */ - Entry DSD0_1_IRQHandler /* Handler name for SR DSD_SRM_1 */ - Entry DSD0_2_IRQHandler /* Handler name for SR DSD_SRM_2 */ - Entry DSD0_3_IRQHandler /* Handler name for SR DSD_SRM_3 */ - Entry DSD0_4_IRQHandler /* Handler name for SR DSD_SRA_0 */ - Entry DSD0_5_IRQHandler /* Handler name for SR DSD_SRA_1 */ - Entry DSD0_6_IRQHandler /* Handler name for SR DSD_SRA_2 */ - Entry DSD0_7_IRQHandler /* Handler name for SR DSD_SRA_3 */ - Entry DAC0_0_IRQHandler /* Handler name for SR DAC0_0 */ - Entry DAC0_1_IRQHandler /* Handler name for SR DAC0_1 */ - Entry CCU40_0_IRQHandler /* Handler name for SR CCU40_0 */ - Entry CCU40_1_IRQHandler /* Handler name for SR CCU40_1 */ - Entry CCU40_2_IRQHandler /* Handler name for SR CCU40_2 */ - Entry CCU40_3_IRQHandler /* Handler name for SR CCU40_3 */ - Entry CCU41_0_IRQHandler /* Handler name for SR CCU41_0 */ - Entry CCU41_1_IRQHandler /* Handler name for SR CCU41_1 */ - Entry CCU41_2_IRQHandler /* Handler name for SR CCU41_2 */ - Entry CCU41_3_IRQHandler /* Handler name for SR CCU41_3 */ - Entry CCU42_0_IRQHandler /* Handler name for SR CCU42_0 */ - Entry CCU42_1_IRQHandler /* Handler name for SR CCU42_1 */ - Entry CCU42_2_IRQHandler /* Handler name for SR CCU42_2 */ - Entry CCU42_3_IRQHandler /* Handler name for SR CCU42_3 */ - Entry CCU43_0_IRQHandler /* Handler name for SR CCU43_0 */ - Entry CCU43_1_IRQHandler /* Handler name for SR CCU43_1 */ - Entry CCU43_2_IRQHandler /* Handler name for SR CCU43_2 */ - Entry CCU43_3_IRQHandler /* Handler name for SR CCU43_3 */ - Entry CCU80_0_IRQHandler /* Handler name for SR CCU80_0 */ - Entry CCU80_1_IRQHandler /* Handler name for SR CCU80_1 */ - Entry CCU80_2_IRQHandler /* Handler name for SR CCU80_2 */ - Entry CCU80_3_IRQHandler /* Handler name for SR CCU80_3 */ - Entry CCU81_0_IRQHandler /* Handler name for SR CCU81_0 */ - Entry CCU81_1_IRQHandler /* Handler name for SR CCU81_1 */ - Entry CCU81_2_IRQHandler /* Handler name for SR CCU81_2 */ - Entry CCU81_3_IRQHandler /* Handler name for SR CCU81_3 */ - Entry POSIF0_0_IRQHandler /* Handler name for SR POSIF0_0 */ - Entry POSIF0_1_IRQHandler /* Handler name for SR POSIF0_1 */ - Entry POSIF1_0_IRQHandler /* Handler name for SR POSIF1_0 */ - Entry POSIF1_1_IRQHandler /* Handler name for SR POSIF1_1 */ - Entry HRPWM_0_IRQHandler /* Handler name for SR HRPWM_0 */ - Entry HRPWM_1_IRQHandler /* Handler name for SR HRPWM_1 */ - Entry HRPWM_2_IRQHandler /* Handler name for SR HRPWM_2 */ - Entry HRPWM_3_IRQHandler /* Handler name for SR HRPWM_3 */ - Entry CAN0_0_IRQHandler /* Handler name for SR CAN0_0 */ - Entry CAN0_1_IRQHandler /* Handler name for SR CAN0_1 */ - Entry CAN0_2_IRQHandler /* Handler name for SR CAN0_2 */ - Entry CAN0_3_IRQHandler /* Handler name for SR CAN0_3 */ - Entry CAN0_4_IRQHandler /* Handler name for SR CAN0_4 */ - Entry CAN0_5_IRQHandler /* Handler name for SR CAN0_5 */ - Entry CAN0_6_IRQHandler /* Handler name for SR CAN0_6 */ - Entry CAN0_7_IRQHandler /* Handler name for SR CAN0_7 */ - Entry USIC0_0_IRQHandler /* Handler name for SR USIC0_0 */ - Entry USIC0_1_IRQHandler /* Handler name for SR USIC0_1 */ - Entry USIC0_2_IRQHandler /* Handler name for SR USIC0_2 */ - Entry USIC0_3_IRQHandler /* Handler name for SR USIC0_3 */ - Entry USIC0_4_IRQHandler /* Handler name for SR USIC0_4 */ - Entry USIC0_5_IRQHandler /* Handler name for SR USIC0_5 */ - Entry USIC1_0_IRQHandler /* Handler name for SR USIC1_0 */ - Entry USIC1_1_IRQHandler /* Handler name for SR USIC1_1 */ - Entry USIC1_2_IRQHandler /* Handler name for SR USIC1_2 */ - Entry USIC1_3_IRQHandler /* Handler name for SR USIC1_3 */ - Entry USIC1_4_IRQHandler /* Handler name for SR USIC1_4 */ - Entry USIC1_5_IRQHandler /* Handler name for SR USIC1_5 */ - .long 0 /* Not Available */ - .long 0 /* Not Available */ - .long 0 /* Not Available */ - .long 0 /* Not Available */ - .long 0 /* Not Available */ - .long 0 /* Not Available */ - Entry LEDTS0_0_IRQHandler /* Handler name for SR LEDTS0_0 */ - .long 0 /* Not Available */ - Entry FCE0_0_IRQHandler /* Handler name for SR FCE0_0 */ - Entry GPDMA0_0_IRQHandler /* Handler name for SR GPDMA0_0 */ - .long 0 /* Not Available */ - Entry USB0_0_IRQHandler /* Handler name for SR USB0_0 */ - Entry ETH0_0_IRQHandler /* Handler name for SR ETH0_0 */ - .long 0 /* Not Available */ - .long 0 /* Not Available */ - .long 0 /* Not Available */ - - .size __Vectors, . - __Vectors -/* ================== END OF VECTOR TABLE DEFINITION ======================= */ - -/* ================== START OF VECTOR ROUTINES ============================= */ - - .align 1 - .thumb - -/* Reset Handler */ - .thumb_func - .globl Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - ldr sp,=__initial_sp - -#ifndef __SKIP_SYSTEM_INIT - ldr r0, =SystemInit - blx r0 -#endif - -/* Initialize data - * - * Between symbol address __copy_table_start__ and __copy_table_end__, - * there are array of triplets, each of which specify: - * offset 0: LMA of start of a section to copy from - * offset 4: VMA of start of a section to copy to - * offset 8: size of the section to copy. Must be multiply of 4 - * - * All addresses must be aligned to 4 bytes boundary. - */ - ldr r4, =__copy_table_start__ - ldr r5, =__copy_table_end__ - -.L_loop0: - cmp r4, r5 - bge .L_loop0_done - ldr r1, [r4] - ldr r2, [r4, #4] - ldr r3, [r4, #8] - -.L_loop0_0: - subs r3, #4 - ittt ge - ldrge r0, [r1, r3] - strge r0, [r2, r3] - bge .L_loop0_0 - - adds r4, #12 - b .L_loop0 - -.L_loop0_done: - -/* Zero initialized data - * Between symbol address __zero_table_start__ and __zero_table_end__, - * there are array of tuples specifying: - * offset 0: Start of a BSS section - * offset 4: Size of this BSS section. Must be multiply of 4 - * - * Define __SKIP_BSS_CLEAR to disable zeroing uninitialzed data in startup. - */ -#ifndef __SKIP_BSS_CLEAR - ldr r3, =__zero_table_start__ - ldr r4, =__zero_table_end__ - -.L_loop2: - cmp r3, r4 - bge .L_loop2_done - ldr r1, [r3] - ldr r2, [r3, #4] - movs r0, 0 - -.L_loop2_0: - subs r2, #4 - itt ge - strge r0, [r1, r2] - bge .L_loop2_0 - - adds r3, #8 - b .L_loop2 -.L_loop2_done: -#endif /* __SKIP_BSS_CLEAR */ - -#ifndef __SKIP_LIBC_INIT_ARRAY - ldr r0, =__libc_init_array - blx r0 -#endif - - ldr r0, =main - blx r0 - -.align 2 -__copy_table_start__: - .long __data_load, __data_start, __data_size - .long __ram_code_load, __ram_code_start, __ram_code_size -__copy_table_end__: - -__zero_table_start__: - .long __bss_start, __bss_size - .long USB_RAM_start, USB_RAM_size - .long ETH_RAM_start, ETH_RAM_size -__zero_table_end__: - - .pool - .size Reset_Handler,.-Reset_Handler - -/* ======================================================================== */ -/* ========== START OF EXCEPTION HANDLER DEFINITION ======================== */ - -/* Default exception Handlers - Users may override this default functionality by - defining handlers of the same name in their C code */ - - .align 1 - .thumb_func - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - b . - .size Default_Handler, . - Default_Handler - - Insert_ExceptionHandler NMI_Handler - Insert_ExceptionHandler HardFault_Handler - Insert_ExceptionHandler MemManage_Handler - Insert_ExceptionHandler BusFault_Handler - Insert_ExceptionHandler UsageFault_Handler - Insert_ExceptionHandler SVC_Handler - Insert_ExceptionHandler DebugMon_Handler - Insert_ExceptionHandler PendSV_Handler - Insert_ExceptionHandler SysTick_Handler - - Insert_ExceptionHandler SCU_0_IRQHandler - Insert_ExceptionHandler ERU0_0_IRQHandler - Insert_ExceptionHandler ERU0_1_IRQHandler - Insert_ExceptionHandler ERU0_2_IRQHandler - Insert_ExceptionHandler ERU0_3_IRQHandler - Insert_ExceptionHandler ERU1_0_IRQHandler - Insert_ExceptionHandler ERU1_1_IRQHandler - Insert_ExceptionHandler ERU1_2_IRQHandler - Insert_ExceptionHandler ERU1_3_IRQHandler - Insert_ExceptionHandler PMU0_0_IRQHandler - Insert_ExceptionHandler VADC0_C0_0_IRQHandler - Insert_ExceptionHandler VADC0_C0_1_IRQHandler - Insert_ExceptionHandler VADC0_C0_2_IRQHandler - Insert_ExceptionHandler VADC0_C0_3_IRQHandler - Insert_ExceptionHandler VADC0_G0_0_IRQHandler - Insert_ExceptionHandler VADC0_G0_1_IRQHandler - Insert_ExceptionHandler VADC0_G0_2_IRQHandler - Insert_ExceptionHandler VADC0_G0_3_IRQHandler - Insert_ExceptionHandler VADC0_G1_0_IRQHandler - Insert_ExceptionHandler VADC0_G1_1_IRQHandler - Insert_ExceptionHandler VADC0_G1_2_IRQHandler - Insert_ExceptionHandler VADC0_G1_3_IRQHandler - Insert_ExceptionHandler VADC0_G2_0_IRQHandler - Insert_ExceptionHandler VADC0_G2_1_IRQHandler - Insert_ExceptionHandler VADC0_G2_2_IRQHandler - Insert_ExceptionHandler VADC0_G2_3_IRQHandler - Insert_ExceptionHandler VADC0_G3_0_IRQHandler - Insert_ExceptionHandler VADC0_G3_1_IRQHandler - Insert_ExceptionHandler VADC0_G3_2_IRQHandler - Insert_ExceptionHandler VADC0_G3_3_IRQHandler - Insert_ExceptionHandler DSD0_0_IRQHandler - Insert_ExceptionHandler DSD0_1_IRQHandler - Insert_ExceptionHandler DSD0_2_IRQHandler - Insert_ExceptionHandler DSD0_3_IRQHandler - Insert_ExceptionHandler DSD0_4_IRQHandler - Insert_ExceptionHandler DSD0_5_IRQHandler - Insert_ExceptionHandler DSD0_6_IRQHandler - Insert_ExceptionHandler DSD0_7_IRQHandler - Insert_ExceptionHandler DAC0_0_IRQHandler - Insert_ExceptionHandler DAC0_1_IRQHandler - Insert_ExceptionHandler CCU40_0_IRQHandler - Insert_ExceptionHandler CCU40_1_IRQHandler - Insert_ExceptionHandler CCU40_2_IRQHandler - Insert_ExceptionHandler CCU40_3_IRQHandler - Insert_ExceptionHandler CCU41_0_IRQHandler - Insert_ExceptionHandler CCU41_1_IRQHandler - Insert_ExceptionHandler CCU41_2_IRQHandler - Insert_ExceptionHandler CCU41_3_IRQHandler - Insert_ExceptionHandler CCU42_0_IRQHandler - Insert_ExceptionHandler CCU42_1_IRQHandler - Insert_ExceptionHandler CCU42_2_IRQHandler - Insert_ExceptionHandler CCU42_3_IRQHandler - Insert_ExceptionHandler CCU43_0_IRQHandler - Insert_ExceptionHandler CCU43_1_IRQHandler - Insert_ExceptionHandler CCU43_2_IRQHandler - Insert_ExceptionHandler CCU43_3_IRQHandler - Insert_ExceptionHandler CCU80_0_IRQHandler - Insert_ExceptionHandler CCU80_1_IRQHandler - Insert_ExceptionHandler CCU80_2_IRQHandler - Insert_ExceptionHandler CCU80_3_IRQHandler - Insert_ExceptionHandler CCU81_0_IRQHandler - Insert_ExceptionHandler CCU81_1_IRQHandler - Insert_ExceptionHandler CCU81_2_IRQHandler - Insert_ExceptionHandler CCU81_3_IRQHandler - Insert_ExceptionHandler POSIF0_0_IRQHandler - Insert_ExceptionHandler POSIF0_1_IRQHandler - Insert_ExceptionHandler POSIF1_0_IRQHandler - Insert_ExceptionHandler POSIF1_1_IRQHandler - Insert_ExceptionHandler HRPWM_0_IRQHandler - Insert_ExceptionHandler HRPWM_1_IRQHandler - Insert_ExceptionHandler HRPWM_2_IRQHandler - Insert_ExceptionHandler HRPWM_3_IRQHandler - Insert_ExceptionHandler CAN0_0_IRQHandler - Insert_ExceptionHandler CAN0_1_IRQHandler - Insert_ExceptionHandler CAN0_2_IRQHandler - Insert_ExceptionHandler CAN0_3_IRQHandler - Insert_ExceptionHandler CAN0_4_IRQHandler - Insert_ExceptionHandler CAN0_5_IRQHandler - Insert_ExceptionHandler CAN0_6_IRQHandler - Insert_ExceptionHandler CAN0_7_IRQHandler - Insert_ExceptionHandler USIC0_0_IRQHandler - Insert_ExceptionHandler USIC0_1_IRQHandler - Insert_ExceptionHandler USIC0_2_IRQHandler - Insert_ExceptionHandler USIC0_3_IRQHandler - Insert_ExceptionHandler USIC0_4_IRQHandler - Insert_ExceptionHandler USIC0_5_IRQHandler - Insert_ExceptionHandler USIC1_0_IRQHandler - Insert_ExceptionHandler USIC1_1_IRQHandler - Insert_ExceptionHandler USIC1_2_IRQHandler - Insert_ExceptionHandler USIC1_3_IRQHandler - Insert_ExceptionHandler USIC1_4_IRQHandler - Insert_ExceptionHandler USIC1_5_IRQHandler - Insert_ExceptionHandler LEDTS0_0_IRQHandler - Insert_ExceptionHandler FCE0_0_IRQHandler - Insert_ExceptionHandler GPDMA0_0_IRQHandler - Insert_ExceptionHandler USB0_0_IRQHandler - Insert_ExceptionHandler ETH0_0_IRQHandler - -/* ============= END OF INTERRUPT HANDLER DEFINITION ====================== */ - - .end diff --git a/variants/XMC4400/system_XMC4400.c b/variants/XMC4400/system_XMC4400.c deleted file mode 100644 index 13132a4d..00000000 --- a/variants/XMC4400/system_XMC4400.c +++ /dev/null @@ -1,651 +0,0 @@ -/********************************************************************************************************************* - * @file system_XMC4400.c - * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File for the Infineon XMC4400 - *Device Series - * @version V3.1.3 - * @date 26. Sep 2017 - * - * @cond - ********************************************************************************************************************* - * Copyright (c) 2014-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted - *provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions - *and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions - *and the following disclaimer in the documentation and/or other materials provided with the - *distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to - *endorse or promote products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - *IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - *FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - *CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - *DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - *DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER - *IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - *OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements - *or bug fixes with Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* - * - ********************** Version History *************************************** - * V3.1.0, Dec 2014, Added options to configure clock settings - * V3.1.1, 01. Jun 2016, Fix masking of OSCHPCTRL value - * V3.1.2, 19. Jun 2017, Rely on cmsis_compiler.h instead of defining __WEAK - * Added support for ARM Compiler 6 (armclang) - * V3.1.3, 26. Sep 2017, Disable FPU if FPU_USED is zero - ****************************************************************************** - * @endcond - */ - -/******************************************************************************* - * HEADER FILES - *******************************************************************************/ -#include - -#include -#include "system_XMC4400.h" - -/******************************************************************************* - * MACROS - *******************************************************************************/ -#define CHIPID_LOC ((uint8_t *)0x20000000UL) -#define HRPWM_CHARDATA_LOC ((uint8_t *)0x20000084UL) - -#define PMU_FLASH_WS (0x3U) - -#define FPLL_FREQUENCY (120000000U) -#define FOSCREF (2500000U) -#define DELAY_CNT_50US_50MHZ (2500UL) -#define DELAY_CNT_150US_50MHZ (7500UL) -#define DELAY_CNT_50US_60MHZ (3000UL) -#define DELAY_CNT_50US_90MHZ (4500UL) -#define DELAY_CNT_50US_120MHZ (6000UL) - -#define SCU_PLL_PLLSTAT_OSC_USABLE \ - (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk | SCU_PLL_PLLSTAT_PLLSP_Msk) - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -*/ - -/* -// Clock configuration -*/ - -/* -// External crystal frequency [Hz] -// <8000000=> 8MHz -// <12000000=> 12MHz -// <16000000=> 16MHz -// Defines external crystal frequency -// Default: 8MHz -*/ -#define OSCHP_FREQUENCY (12000000U) - -#if OSCHP_FREQUENCY == 8000000U - #define USB_PDIV (1U) - #define USB_NDIV (95U) - #define USB_DIV (3U) - -#elif OSCHP_FREQUENCY == 12000000U - #define USB_PDIV (1U) - #define USB_NDIV (63U) - #define USB_DIV (3U) - -#elif OSCHP_FREQUENCY == 16000000U - #define USB_PDIV (1U) - #define USB_NDIV (47U) - #define USB_DIV (3U) - -#else - #error "External crystal frequency not supported" - -#endif - -/* -// System clock (fSYS) source selection -// <0=> Backup clock (24MHz) -// <1=> Maximum clock frequency using PLL (120MHz) -// Default: Maximum clock frequency using PLL (120MHz) -*/ -#define SYS_CLOCK_SRC 1 -#define SYS_CLOCK_SRC_OFI 0 -#define SYS_CLOCK_SRC_PLL 1 - -/* -// Backup clock calibration mode -// <0=> Factory calibration -// <1=> Automatic calibration -// Default: Automatic calibration -*/ -#define FOFI_CALIBRATION_MODE 1 -#define FOFI_CALIBRATION_MODE_FACTORY 0 -#define FOFI_CALIBRATION_MODE_AUTOMATIC 1 - -/* -// Standby clock (fSTDBY) source selection -// <0=> Internal slow oscillator (32768Hz) -// <1=> External crystal (32768Hz) -// Default: Internal slow oscillator (32768Hz) -*/ -#define STDBY_CLOCK_SRC 0 -#define STDBY_CLOCK_SRC_OSI 0 -#define STDBY_CLOCK_SRC_OSCULP 1 - -/* -// PLL clock source selection -// <0=> External crystal -// <1=> External direct input -// <2=> Internal fast oscillator -// Default: External crystal -*/ -#define PLL_CLOCK_SRC 0 -#define PLL_CLOCK_SRC_EXT_XTAL 0 -#define PLL_CLOCK_SRC_EXT_DIRECT 1 -#define PLL_CLOCK_SRC_OFI 2 - -#if PLL_CLOCK_SRC == PLL_CLOCK_SRC_EXT_XTAL - #if OSCHP_FREQUENCY == 8000000U - #define PLL_PDIV (1U) - #define PLL_NDIV (89U) - #define PLL_K2DIV (2U) - - #elif OSCHP_FREQUENCY == 12000000U - #define PLL_PDIV (1U) - #define PLL_NDIV (79U) - #define PLL_K2DIV (3U) - - #elif OSCHP_FREQUENCY == 16000000U - #define PLL_PDIV (1U) - #define PLL_NDIV (59U) - #define PLL_K2DIV (3U) - - #else - #error "External crystal frequency not supported" - - #endif - - #define VCO ((OSCHP_FREQUENCY / (PLL_PDIV + 1UL)) * (PLL_NDIV + 1UL)) - -#else /* PLL_CLOCK_SRC == PLL_CLOCK_SRC_EXT_XTAL */ - - #define PLL_PDIV (1U) - #define PLL_NDIV (39U) - #define PLL_K2DIV (3U) - - #define VCO ((OFI_FREQUENCY / (PLL_PDIV + 1UL)) * (PLL_NDIV + 1UL)) - -#endif /* PLL_CLOCK_SRC == PLL_CLOCK_SRC_OFI */ - -#define PLL_K2DIV_0 ((VCO / OFI_FREQUENCY) - 1UL) -#define PLL_K2DIV_1 ((VCO / 60000000U) - 1UL) -#define PLL_K2DIV_2 ((VCO / 90000000U) - 1UL) - -#define SCU_CLK_CLKCLR_ENABLE_USBCLK SCU_CLK_CLKCLR_USBCDI_Msk -#define SCU_CLK_CLKCLR_ENABLE_ETHCLK SCU_CLK_CLKCLR_ETH0CDI_Msk -#define SCU_CLK_CLKCLR_ENABLE_CCUCLK SCU_CLK_CLKCLR_CCUCDI_Msk -#define SCU_CLK_CLKCLR_ENABLE_WDTCLK SCU_CLK_CLKCLR_WDTCDI_Msk - -#define SCU_CLK_USBCLKCR_USBSEL_USBPLL (0U << SCU_CLK_USBCLKCR_USBSEL_Pos) -#define SCU_CLK_USBCLKCR_USBSEL_PLL (1U << SCU_CLK_USBCLKCR_USBSEL_Pos) - -#define SCU_CLK_WDTCLKCR_WDTSEL_OFI (0U << SCU_CLK_WDTCLKCR_WDTSEL_Pos) -#define SCU_CLK_WDTCLKCR_WDTSEL_STANDBY (1U << SCU_CLK_WDTCLKCR_WDTSEL_Pos) -#define SCU_CLK_WDTCLKCR_WDTSEL_PLL (2U << SCU_CLK_WDTCLKCR_WDTSEL_Pos) - -#define SCU_CLK_EXTCLKCR_ECKSEL_SYS (0U << SCU_CLK_EXTCLKCR_ECKSEL_Pos) -#define SCU_CLK_EXTCLKCR_ECKSEL_USBPLL (2U << SCU_CLK_EXTCLKCR_ECKSEL_Pos) -#define SCU_CLK_EXTCLKCR_ECKSEL_PLL (3U << SCU_CLK_EXTCLKCR_ECKSEL_Pos) -#define SCU_CLK_EXTCLKCR_ECKSEL_STANDBY (4U << SCU_CLK_EXTCLKCR_ECKSEL_Pos) - -#define EXTCLK_PIN_P0_8 (0) -#define EXTCLK_PIN_P1_15 (1) - -/* -// Clock tree -// CPU clock divider -// <0=> fCPU = fSYS -// <1=> fCPU = fSYS / 2 -// Peripheral clock divider -// <0=> fPB = fCPU -// <1=> fPB = fCPU / 2 -// Enable CCU clock -// CCU clock divider -// <0=> fCCU = fCPU -// <1=> fCCU = fCPU / 2 -// -// Enable WDT clock -// WDT clock divider <1-256><#-1> -// WDT clock source <0=> fOFI -// <1=> fSTDBY -// <2=> fPLL -// -// Enable ETH clock -// -// Enable USB clock -// USB clock source <0=> USBPLL -// <1=> PLL -// -// External Clock configuration -// External clock source selection -// <0=> System clock -// <2=> USB PLL clock -// <3=> PLL clock -// <4=> Standby clock -// External clock divider <1-512><#-1> -// Only valid for USB PLL and PLL clocks -// External Pin Selection -// <0=> P0.8 -// <1=> P1.15 -// -// -*/ -#define ENABLE_SCUCLK (0U) -#define CPUCLKDIV (0U) -#define PBCLKDIV (0U) -#define CCUCLKDIV (0U) -#define WDTCLKDIV (0U | SCU_CLK_WDTCLKCR_WDTSEL_OFI) -#define USBCLKDIV (0U | SCU_CLK_USBCLKCR_USBSEL_USBPLL | USB_DIV) - -#define ENABLE_EXTCLK (0U) -#define EXTCLKDIV (0U | SCU_CLK_EXTCLKCR_ECKSEL_SYS) -#define EXTCLK_PIN (0U) - -#define ENABLE_PLL \ - (SYS_CLOCK_SRC == SYS_CLOCK_SRC_PLL) || \ - (((ENABLE_SCUCLK & SCU_CLK_CLKSET_USBCEN_Msk) != 0) && \ - ((USBCLKDIV & SCU_CLK_USBCLKCR_USBSEL_Msk) == SCU_CLK_USBCLKCR_USBSEL_PLL)) || \ - (((ENABLE_SCUCLK & SCU_CLK_CLKSET_WDTCEN_Msk) != 0) && \ - ((WDTCLKDIV & SCU_CLK_WDTCLKCR_WDTSEL_Msk) == SCU_CLK_WDTCLKCR_WDTSEL_PLL)) - -/* -// -*/ - -/* -//-------- <<< end of configuration section >>> ------------------ -*/ - -/******************************************************************************* - * GLOBAL VARIABLES - *******************************************************************************/ -#if defined(__CC_ARM) -uint32_t SystemCoreClock __attribute__((at(0x2000FFC0))); -uint8_t g_chipid[16] __attribute__((at(0x2000FFC4))); -uint32_t g_hrpwm_char_data[3] __attribute__((at(0x2000FFD4))); -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -uint32_t SystemCoreClock __attribute__((section(".ARM.__at_0x2000FFC0"))); -uint8_t g_chipid[16] __attribute__((section(".ARM.__at_0x2000FFC4"))); -uint32_t g_hrpwm_char_data[3] __attribute__((section(".ARM.__at_0x2000FFD4"))); -#elif defined(__ICCARM__) -__no_init uint32_t SystemCoreClock; -__no_init uint8_t g_chipid[16]; -__no_init uint32_t g_hrpwm_char_data[3]; -#elif defined(__GNUC__) -uint32_t SystemCoreClock __attribute__((section(".no_init"))); -uint8_t g_chipid[16] __attribute__((section(".no_init"))); -uint32_t g_hrpwm_char_data[3] __attribute__((section(".no_init"))); -#elif defined(__TASKING__) -uint32_t SystemCoreClock __at(0x2000FFC0); -uint8_t g_chipid[16] __at(0x2000FFC4); -uint32_t g_hrpwm_char_data[3] __at(0x2000FFD4); -#endif - -extern uint32_t __Vectors; - -/******************************************************************************* - * LOCAL FUNCTIONS - *******************************************************************************/ -static void delay(uint32_t cycles) { - volatile uint32_t i; - - for (i = 0UL; i < cycles; ++i) { - __NOP(); - } -} - -/******************************************************************************* - * API IMPLEMENTATION - *******************************************************************************/ - -__WEAK void SystemInit(void) { - memcpy(g_chipid, CHIPID_LOC, 16); - memcpy(g_hrpwm_char_data, HRPWM_CHARDATA_LOC, 12); - - SystemCoreSetup(); - SystemCoreClockSetup(); -} - -__WEAK void SystemCoreSetup(void) { - uint32_t temp; - - /* relocate vector table */ - __disable_irq(); - SCB->VTOR = (uint32_t)(&__Vectors); - __DSB(); - __enable_irq(); - - /* __FPU_PRESENT = 1 defined in device header file */ - /* __FPU_USED value depends on compiler/linker options. */ - /* __FPU_USED = 0 if -mfloat-abi=soft is selected */ - /* __FPU_USED = 1 if -mfloat-abi=softfp or –mfloat-abi=hard */ - -#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) - SCB->CPACR |= ((3UL << 10 * 2) | /* set CP10 Full Access */ - (3UL << 11 * 2)); /* set CP11 Full Access */ -#else - SCB->CPACR = 0; -#endif - - /* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */ - SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk); - - temp = FLASH0->FCON; - temp &= ~FLASH_FCON_WSPFLASH_Msk; - temp |= PMU_FLASH_WS; - FLASH0->FCON = temp; -} - -__WEAK void SystemCoreClockSetup(void) { -#if FOFI_CALIBRATION_MODE == FOFI_CALIBRATION_MODE_FACTORY - /* Enable factory calibration */ - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FOTR_Msk; -#else - /* Automatic calibration uses the fSTDBY */ - - /* Enable HIB domain */ - /* Power up HIB domain if and only if it is currently powered down */ - if ((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0) { - SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk; - - while ((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0) { - /* wait until HIB domain is enabled */ - } - } - - /* Remove the reset only if HIB domain were in a state of reset */ - if ((SCU_RESET->RSTSTAT) & SCU_RESET_RSTSTAT_HIBRS_Msk) { - SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; - delay(DELAY_CNT_150US_50MHZ); - } - - #if STDBY_CLOCK_SRC == STDBY_CLOCK_SRC_OSCULP - /* Enable OSC_ULP */ - if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk) != 0UL) { - /*enable OSC_ULP*/ - while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk) { - /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ - } - SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; - - /* Check if the clock is OK using OSCULP Oscillator Watchdog*/ - while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk) { - /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ - } - SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk; - - /* wait till clock is stable */ - do { - while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk) { - /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ - } - SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk; - - delay(DELAY_CNT_50US_50MHZ); - - } while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk) != 0UL); - } - - /* now OSC_ULP is running and can be used*/ - /* Select OSC_ULP as the clock source for RTC and STDBY*/ - while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk) { - /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ - } - SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk | SCU_HIBERNATE_HDCR_STDBYSEL_Msk; - - #endif /* STDBY_CLOCK_SRC == STDBY_CLOCK_SRC_OSCULP */ - - /* Enable automatic calibration of internal fast oscillator */ - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk; -#endif /* FOFI_CALIBRATION_MODE == FOFI_CALIBRATION_MODE_AUTOMATIC */ - - delay(DELAY_CNT_50US_50MHZ); - -#if ENABLE_PLL - - /* enable PLL */ - SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk); - - #if PLL_CLOCK_SRC != PLL_CLOCK_SRC_OFI - /* enable OSC_HP */ - if ((SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk) != 0U) { - SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_OSCHPCTRL_MODE_Msk | SCU_OSC_OSCHPCTRL_OSCVAL_Msk); - SCU_OSC->OSCHPCTRL |= ((OSCHP_GetFrequency() / FOSCREF) - 1UL) - << SCU_OSC_OSCHPCTRL_OSCVAL_Pos; - - /* select OSC_HP clock as PLL input */ - SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk; - - /* restart OSC Watchdog */ - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; - - while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_OSC_USABLE) != SCU_PLL_PLLSTAT_OSC_USABLE) { - /* wait till OSC_HP output frequency is usable */ - } - } - #else /* PLL_CLOCK_SRC != PLL_CLOCK_SRC_OFI */ - - /* select backup clock as PLL input */ - SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk; - #endif - - /* Go to bypass the Main PLL */ - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk; - - /* disconnect Oscillator from PLL */ - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk; - - /* Setup divider settings for main PLL */ - SCU_PLL->PLLCON1 = - ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) | (PLL_K2DIV_0 << SCU_PLL_PLLCON1_K2DIV_Pos) | - (PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos)); - - /* Set OSCDISCDIS */ - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk; - - /* connect Oscillator to PLL */ - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk; - - /* restart PLL Lock detection */ - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk; - - while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk) == 0U) { - /* wait for PLL Lock */ - } - - /* Disable bypass- put PLL clock back */ - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk; - while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOBYST_Msk) != 0U) { - /* wait for normal mode */ - } -#endif /* ENABLE_PLL */ - -#if (SYS_CLOCK_SRC == SYS_CLOCK_SRC_PLL) - /* Switch system clock to PLL */ - SCU_CLK->SYSCLKCR |= SCU_CLK_SYSCLKCR_SYSSEL_Msk; -#else - /* Switch system clock to backup clock */ - SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk; -#endif - - /* Before scaling to final frequency we need to setup the clock dividers */ - SCU_CLK->PBCLKCR = PBCLKDIV; - SCU_CLK->CPUCLKCR = CPUCLKDIV; - SCU_CLK->CCUCLKCR = CCUCLKDIV; - SCU_CLK->WDTCLKCR = WDTCLKDIV; - SCU_CLK->USBCLKCR = USBCLKDIV; - -#if ENABLE_PLL - /* PLL frequency stepping...*/ - /* Reset OSCDISCDIS */ - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk; - - SCU_PLL->PLLCON1 = - ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) | (PLL_K2DIV_1 << SCU_PLL_PLLCON1_K2DIV_Pos) | - (PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos)); - - delay(DELAY_CNT_50US_60MHZ); - while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk) == 0U) { - /* wait for PLL Lock */ - } - - SCU_PLL->PLLCON1 = - ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) | (PLL_K2DIV_2 << SCU_PLL_PLLCON1_K2DIV_Pos) | - (PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos)); - - delay(DELAY_CNT_50US_90MHZ); - while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk) == 0U) { - /* wait for PLL Lock */ - } - - SCU_PLL->PLLCON1 = - ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) | (PLL_K2DIV << SCU_PLL_PLLCON1_K2DIV_Pos) | - (PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos)); - - delay(DELAY_CNT_50US_120MHZ); - while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk) == 0U) { - /* wait for PLL Lock */ - } - - SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; -#endif /* ENABLE_PLL */ - -#if (((ENABLE_SCUCLK & SCU_CLK_CLKSET_USBCEN_Msk) != 0) && \ - ((USBCLKDIV & SCU_CLK_USBCLKCR_USBSEL_Msk) == SCU_CLK_USBCLKCR_USBSEL_USBPLL)) - /* enable USB PLL first */ - SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk); - - /* USB PLL uses as clock input the OSC_HP */ - /* check and if not already running enable OSC_HP */ - if ((SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk) != 0U) { - /* check if Main PLL is switched on for OSC WDG*/ - if ((SCU_PLL->PLLCON0 & (SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0UL) { - /* enable PLL first */ - SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk); - } - - SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_OSCHPCTRL_MODE_Msk | SCU_OSC_OSCHPCTRL_OSCVAL_Msk); - SCU_OSC->OSCHPCTRL |= ((OSCHP_GetFrequency() / FOSCREF) - 1UL) - << SCU_OSC_OSCHPCTRL_OSCVAL_Pos; - - /* restart OSC Watchdog */ - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; - - while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_OSC_USABLE) != SCU_PLL_PLLSTAT_OSC_USABLE) { - /* wait till OSC_HP output frequency is usable */ - } - } - - /* Setup USB PLL */ - /* Go to bypass the USB PLL */ - SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk; - - /* disconnect Oscillator from USB PLL */ - SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk; - - /* Setup Divider settings for USB PLL */ - SCU_PLL->USBPLLCON = - ((USB_NDIV << SCU_PLL_USBPLLCON_NDIV_Pos) | (USB_PDIV << SCU_PLL_USBPLLCON_PDIV_Pos)); - - /* Set OSCDISCDIS */ - SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk; - - /* connect Oscillator to USB PLL */ - SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk; - - /* restart PLL Lock detection */ - SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk; - - while ((SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk) == 0U) { - /* wait for PLL Lock */ - } -#endif /* (USBCLKDIV & SCU_CLK_USBCLKCR_USBSEL_Msk) */ - - /* Enable selected clocks */ - SCU_CLK->CLKSET = ENABLE_SCUCLK; - -#if ENABLE_EXTCLK == 1 - /* Configure external clock */ - SCU_CLK->EXTCLKCR = EXTCLKDIV; - - #if EXTCLK_PIN == EXTCLK_PIN_P1_15 - /* P1.15 */ - PORT1->PDR1 &= ~PORT1_PDR1_PD15_Msk; - PORT1->IOCR12 = (PORT1->IOCR12 & ~PORT0_IOCR12_PC15_Msk) | (0x11U << PORT0_IOCR12_PC15_Pos); - #else - /* P0.8 */ - PORT0->HWSEL &= ~PORT0_HWSEL_HW8_Msk; - PORT0->PDR1 &= ~PORT0_PDR1_PD8_Msk; - PORT0->IOCR8 = (PORT0->IOCR8 & ~PORT0_IOCR8_PC8_Msk) | (0x11U << PORT0_IOCR8_PC8_Pos); - #endif - -#endif /* ENABLE_EXTCLK == 1 */ - - SystemCoreClockUpdate(); -} - -__WEAK void SystemCoreClockUpdate(void) { - uint32_t pdiv; - uint32_t ndiv; - uint32_t kdiv; - uint32_t temp; - - if (SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) { - /* fPLL is clock source for fSYS */ - if (SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk) { - /* PLL input clock is the backup clock (fOFI) */ - temp = OFI_FREQUENCY; - } else { - /* PLL input clock is the high performance osicllator (fOSCHP) */ - temp = OSCHP_GetFrequency(); - } - - /* check if PLL is locked */ - if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk) { - /* PLL normal mode */ - /* read back divider settings */ - pdiv = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk) >> SCU_PLL_PLLCON1_PDIV_Pos) + 1; - ndiv = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk) >> SCU_PLL_PLLCON1_NDIV_Pos) + 1; - kdiv = - ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk) >> SCU_PLL_PLLCON1_K2DIV_Pos) + 1; - - temp = (temp / (pdiv * kdiv)) * ndiv; - } else { - /* PLL prescalar mode */ - /* read back divider settings */ - kdiv = - ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K1DIV_Msk) >> SCU_PLL_PLLCON1_K1DIV_Pos) + 1; - - temp = (temp / kdiv); - } - } else { - /* fOFI is clock source for fSYS */ - temp = OFI_FREQUENCY; - } - - temp = temp / ((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk) + 1); - temp = temp / ((SCU_CLK->CPUCLKCR & SCU_CLK_CPUCLKCR_CPUDIV_Msk) + 1); - - SystemCoreClock = temp; -} - -__WEAK uint32_t OSCHP_GetFrequency(void) { return OSCHP_FREQUENCY; } diff --git a/variants/XMC4400/system_XMC4400.h b/variants/XMC4400/system_XMC4400.h deleted file mode 100644 index 490a4872..00000000 --- a/variants/XMC4400/system_XMC4400.h +++ /dev/null @@ -1,109 +0,0 @@ -/********************************************************************************************************************* - * @file system_XMC4400.h - * @brief Device specific initialization for the XMC4400-Series according to CMSIS - * @version V1.7 - * @date 10 February 2015 - * - * @cond - ********************************************************************************************************************* - * Copyright (c) 2012-2016, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted - *provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions - *and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions - *and the following disclaimer in the documentation and/or other materials provided with the - *distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to - *endorse or promote products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - *IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - *FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - *CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - *DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - *DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER - *IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - *OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements - *or bug fixes with Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* - * - **************************** Change history ********************************* - ***************************************************************************** - * @endcond - */ - -#ifndef SYSTEM_XMC4400_H -#define SYSTEM_XMC4400_H - -/******************************************************************************* - * HEADER FILES - *******************************************************************************/ - -#include - -/******************************************************************************* - * MACROS - *******************************************************************************/ - -#define OFI_FREQUENCY (24000000UL) /**< 24MHz Backup Clock (fOFI) frequency. */ -#define OSI_FREQUENCY (32768UL) /**< 32KHz Internal Slow Clock source (fOSI) frequency. */ - -/******************************************************************************* - * GLOBAL VARIABLES - *******************************************************************************/ - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ -extern uint8_t g_chipid[16]; /*!< Unique chip ID */ -extern uint32_t g_hrpwm_char_data[3]; /*!< HRPWM characterization data */ - -/******************************************************************************* - * API PROTOTYPES - *******************************************************************************/ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Initialize the system - * - */ -void SystemInit(void); - -/** - * @brief Initialize CPU settings - * - */ -void SystemCoreSetup(void); - -/** - * @brief Initialize clock - * - */ -void SystemCoreClockSetup(void); - -/** - * @brief Update SystemCoreClock variable - * - */ -void SystemCoreClockUpdate(void); - -/** - * @brief Returns frequency of the high performace oscillator - * User needs to overload this function to return the correct oscillator frequency - */ -uint32_t OSCHP_GetFrequency(void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/variants/XMC4700/config/XMC4700_Relax_Kit/pins_arduino.h b/variants/XMC4700/config/KIT_XMC47_RELAX/pins_arduino.h similarity index 81% rename from variants/XMC4700/config/XMC4700_Relax_Kit/pins_arduino.h rename to variants/XMC4700/config/KIT_XMC47_RELAX/pins_arduino.h index 22878e88..5c53d21d 100644 --- a/variants/XMC4700/config/XMC4700_Relax_Kit/pins_arduino.h +++ b/variants/XMC4700/config/KIT_XMC47_RELAX/pins_arduino.h @@ -36,8 +36,11 @@ // XMC_BOARD for stringifying into serial or other text outputs/logs // Note the actual name XMC and number MUST have a character between // to avoid issues with other defined macros e.g. XMC1100 -#define XMC_BOARD XMC 4700 Relax Kit +#define XMC_BOARD KIT_XMC47_RELAX +// Define USE_XMC_RELAX_KIT_SD allows to use the SD Lib to communicate with a SD Card over +// the on-board SD Card Slot. This feature is only available on XMC4700 RelaxKits. +#define USE_XMC_RELAX_KIT_SD /* On board LED is ON when digital output is 1, HIGH, TRUE, ON */ #define XMC_LED_ON 1 @@ -60,7 +63,6 @@ extern const uint8_t NUM_ANALOG_OUTPUTS; #define NUM_TASKS_VARIANT 32 #define NUM_SPI 3 #define NUM_I2C 2 - // to use SPI_for_xmc_SD if desired by user #define XMC_SPI_for_xmc_SD XMC_SPI_1 #define SDCARD_SPI SPI1 @@ -111,33 +113,55 @@ static const uint8_t SCK_SD = SDCARD_SCK_PIN; #define MASTER_SCLK PORT3, 9 #define MASTER_WACLK PORT3, 10 -#define A0 0 -#define A1 1 -#define A2 2 -#define A3 3 -#define A4 4 -#define A5 5 +#define PIN_A0 0 +#define PIN_A1 1 +#define PIN_A2 2 +#define PIN_A3 3 +#define PIN_A4 4 +#define PIN_A5 5 // Additional ADC ports starting here -#define A6 6 -#define A7 7 -#define A8 8 -#define A9 9 -#define A10 10 -#define A11 11 -#define A12 12 -#define A13 13 -#define A14 14 -#define A15 15 -#define A16 16 -#define A17 17 -#define A18 18 -#define A19 19 -#define A20 20 -#define A21 21 +#define PIN_A6 6 +#define PIN_A7 7 +#define PIN_A8 8 +#define PIN_A9 9 +#define PIN_A10 10 +#define PIN_A11 11 +#define PIN_A12 12 +#define PIN_A13 13 +#define PIN_A14 14 +#define PIN_A15 15 +#define PIN_A16 16 +#define PIN_A17 17 +#define PIN_A18 18 +#define PIN_A19 19 +#define PIN_A20 20 +#define PIN_A21 21 // ADC G3CH0 on P15.8 not available // ADC G3CH1 on P15.9 not available // ADC G3CH4 on P15.12 button // ADC G3CH5 on P15.13 button +static const uint8_t A0 = PIN_A0; +static const uint8_t A1 = PIN_A1; +static const uint8_t A2 = PIN_A2; +static const uint8_t A3 = PIN_A3; +static const uint8_t A4 = PIN_A4; +static const uint8_t A5 = PIN_A5; +static const uint8_t A6 = PIN_A6; +static const uint8_t A7 = PIN_A7; +static const uint8_t A8 = PIN_A8; +static const uint8_t A9 = PIN_A9; +static const uint8_t A10 = PIN_A10; +static const uint8_t A11 = PIN_A11; +static const uint8_t A12 = PIN_A12; +static const uint8_t A13 = PIN_A13; +static const uint8_t A14 = PIN_A14; +static const uint8_t A15 = PIN_A15; +static const uint8_t A16 = PIN_A16; +static const uint8_t A17 = PIN_A17; +static const uint8_t A18 = PIN_A18; +static const uint8_t A19 = PIN_A19; +static const uint8_t A20 = PIN_A20; +static const uint8_t A21 = PIN_A21; #define LED1 22 #define LED2 23 @@ -146,7 +170,7 @@ static const uint8_t SCK_SD = SDCARD_SCK_PIN; #define BUTTON1 24 #define BUTTON2 25 -#define digitalPinToInterrupt(p) ((p) == 2 ? 0 : ((p) == 3 ? 1 : NOT_AN_INTERRUPT)) +#define digitalPinToInterrupt(p) ((p) == 2 ? 0 : ((p) == 3 ? 1 : -1)) #ifdef ARDUINO_MAIN // Mapping of digital pins and comments @@ -257,6 +281,7 @@ const XMC_PORT_PIN_t mapping_port_pin[] = { }; const uint8_t GND = (sizeof(mapping_port_pin) / sizeof(XMC_PORT_PIN_t)); const uint8_t NUM_DIGITAL = (sizeof(mapping_port_pin) / sizeof(XMC_PORT_PIN_t)); +bool gpio_current_value[NUM_DIGITAL] = {false}; ; const XMC_PIN_INTERRUPT_t mapping_interrupt[] = { @@ -285,27 +310,27 @@ const uint8_t mapping_pin_PWM4[][2] = {{3, 0}, // PWM0 /* Configurations of PWM channels for CCU4 type */ XMC_PWM4_t mapping_pwm4[] = { {CCU40, CCU40_CC42, 2, mapping_port_pin[3], P1_1_AF_CCU40_OUT2, XMC_CCU4_SLICE_PRESCALER_64, - PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 3 P1.1 + PWM4_TIMER_PERIOD, 0, false}, // PWM disabled 3 P1.1 {CCU41, CCU41_CC40, 0, mapping_port_pin[10], P3_10_AF_CCU41_OUT0, XMC_CCU4_SLICE_PRESCALER_64, - PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 10 P3.10 + PWM4_TIMER_PERIOD, 0, false}, // PWM disabled 10 P3.10 {CCU41, CCU41_CC42, 2, mapping_port_pin[11], P3_8_AF_CCU41_OUT2, XMC_CCU4_SLICE_PRESCALER_64, - PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 11 P3.8 + PWM4_TIMER_PERIOD, 0, false}, // PWM disabled 11 P3.8 {CCU40, CCU40_CC40, 0, mapping_port_pin[93], P0_15_AF_CCU40_OUT0, XMC_CCU4_SLICE_PRESCALER_64, - PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 93 P0.15 + PWM4_TIMER_PERIOD, 0, false}, // PWM disabled 93 P0.15 {CCU40, CCU40_CC41, 1, mapping_port_pin[70], P0_14_AF_CCU40_OUT1, XMC_CCU4_SLICE_PRESCALER_64, - PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 70 P0.14 + PWM4_TIMER_PERIOD, 0, false}, // PWM disabled 70 P0.14 {CCU40, CCU40_CC43, 3, mapping_port_pin[94], P0_12_AF_CCU40_OUT3, XMC_CCU4_SLICE_PRESCALER_64, - PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 94 P0.12 + PWM4_TIMER_PERIOD, 0, false}, // PWM disabled 94 P0.12 {CCU42, CCU42_CC40, 0, mapping_port_pin[61], P3_0_AF_CCU42_OUT0, XMC_CCU4_SLICE_PRESCALER_64, - PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 61 P3.0 + PWM4_TIMER_PERIOD, 0, false}, // PWM disabled 61 P3.0 {CCU42, CCU42_CC42, 2, mapping_port_pin[34], P3_4_AF_CCU42_OUT2, XMC_CCU4_SLICE_PRESCALER_64, - PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 34 P3.4 + PWM4_TIMER_PERIOD, 0, false}, // PWM disabled 34 P3.4 {CCU43, CCU43_CC40, 0, mapping_port_pin[76], P6_5_AF_CCU43_OUT0, XMC_CCU4_SLICE_PRESCALER_64, - PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 76 P6.5 + PWM4_TIMER_PERIOD, 0, false}, // PWM disabled 76 P6.5 {CCU43, CCU43_CC41, 1, mapping_port_pin[88], P6_4_AF_CCU43_OUT1, XMC_CCU4_SLICE_PRESCALER_64, - PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 88 P6.4 + PWM4_TIMER_PERIOD, 0, false}, // PWM disabled 88 P6.4 {CCU43, CCU43_CC43, 3, mapping_port_pin[89], P6_2_AF_CCU43_OUT3, XMC_CCU4_SLICE_PRESCALER_64, - PWM4_TIMER_PERIOD, DISABLED} // PWM disabled 89 P6.2 + PWM4_TIMER_PERIOD, 0, false} // PWM disabled 89 P6.2 }; const uint8_t NUM_PWM4 = (sizeof(mapping_pwm4) / sizeof(XMC_PWM4_t)); @@ -327,41 +352,41 @@ const uint8_t mapping_pin_PWM8[][2] = {{5, 0}, // PWM1 /* Configurations of PWM channels for CCU8 type */ XMC_PWM8_t mapping_pwm8[] = { {CCU81, CCU81_CC83, 3, XMC_CCU8_SLICE_COMPARE_CHANNEL_2, mapping_port_pin[5], - P2_12_AF_CCU81_OUT33, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, - DISABLED}, // PWM disabled 5 P2.12 + P2_12_AF_CCU81_OUT33, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, 0, + false}, // PWM disabled 5 P2.12 {CCU80, CCU80_CC82, 2, XMC_CCU8_SLICE_COMPARE_CHANNEL_2, mapping_port_pin[6], - P2_11_AF_CCU80_OUT22, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, - DISABLED}, // PWM disabled 6 P2.11 + P2_11_AF_CCU80_OUT22, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, 0, + false}, // PWM disabled 6 P2.11 {CCU81, CCU81_CC81, 1, XMC_CCU8_SLICE_COMPARE_CHANNEL_1, mapping_port_pin[9], - P1_11_AF_CCU81_OUT11, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, - DISABLED}, // PWM disabled 9 P1.11 + P1_11_AF_CCU81_OUT11, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, 0, + false}, // PWM disabled 9 P1.11 {CCU80, CCU80_CC80, 0, XMC_CCU8_SLICE_COMPARE_CHANNEL_1, mapping_port_pin[51], - P5_11_AF_CCU80_OUT00, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, - DISABLED}, // PWM disabled 51 P5.11 + P5_11_AF_CCU80_OUT00, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, 0, + false}, // PWM disabled 51 P5.11 {CCU80, CCU80_CC81, 1, XMC_CCU8_SLICE_COMPARE_CHANNEL_1, mapping_port_pin[37], - P0_1_AF_CCU80_OUT11, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, - DISABLED}, // PWM disabled 37 P0.1 + P0_1_AF_CCU80_OUT11, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, 0, + false}, // PWM disabled 37 P0.1 {CCU80, CCU80_CC81, 1, XMC_CCU8_SLICE_COMPARE_CHANNEL_2, mapping_port_pin[62], - P0_9_AF_CCU80_OUT12, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, - DISABLED}, // PWM disabled 62 P0.9 + P0_9_AF_CCU80_OUT12, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, 0, + false}, // PWM disabled 62 P0.9 {CCU80, CCU80_CC82, 2, XMC_CCU8_SLICE_COMPARE_CHANNEL_1, mapping_port_pin[36], - P0_3_AF_CCU80_OUT20, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, - DISABLED}, // PWM disabled 36 P0.3 + P0_3_AF_CCU80_OUT20, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, 0, + false}, // PWM disabled 36 P0.3 {CCU80, CCU80_CC83, 3, XMC_CCU8_SLICE_COMPARE_CHANNEL_1, mapping_port_pin[66], - P0_6_AF_CCU80_OUT30, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, - DISABLED}, // PWM disabled 66 P0.6 + P0_6_AF_CCU80_OUT30, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, 0, + false}, // PWM disabled 66 P0.6 {CCU81, CCU81_CC80, 0, XMC_CCU8_SLICE_COMPARE_CHANNEL_1, mapping_port_pin[77], - P1_15_AF_CCU81_OUT00, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, - DISABLED}, // PWM disabled 77 P1.15 + P1_15_AF_CCU81_OUT00, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, 0, + false}, // PWM disabled 77 P1.15 {CCU81, CCU81_CC80, 0, XMC_CCU8_SLICE_COMPARE_CHANNEL_2, mapping_port_pin[81], - P5_7_AF_CCU81_OUT02, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, - DISABLED}, // PWM disabled 81 P5.7 + P5_7_AF_CCU81_OUT02, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, 0, + false}, // PWM disabled 81 P5.7 {CCU81, CCU81_CC81, 1, XMC_CCU8_SLICE_COMPARE_CHANNEL_2, mapping_port_pin[80], - P5_5_AF_CCU81_OUT12, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, - DISABLED}, // PWM disabled 80 P5.5 + P5_5_AF_CCU81_OUT12, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, 0, + false}, // PWM disabled 80 P5.5 {CCU81, CCU81_CC82, 2, XMC_CCU8_SLICE_COMPARE_CHANNEL_2, mapping_port_pin[79], - P5_3_AF_CCU81_OUT22, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, - DISABLED} // PWM disabled 79 P5.3 + P5_3_AF_CCU81_OUT22, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, 0, + false} // PWM disabled 79 P5.3 }; const uint8_t NUM_PWM8 = (sizeof(mapping_pwm8) / sizeof(XMC_PWM8_t)); const uint8_t NUM_PWM = @@ -375,30 +400,19 @@ const uint8_t NUM_ANALOG_OUTPUTS = (sizeof(mapping_dac) / sizeof(XMC_ARD_DAC_t)) #endif // Result reg numbers are now equal to channel numbers -XMC_ADC_t mapping_adc[] = {{VADC, 0, VADC_G0, 0, 0, DISABLED}, {VADC, 1, VADC_G0, 0, 1, DISABLED}, - {VADC, 2, VADC_G1, 1, 2, DISABLED}, {VADC, 3, VADC_G1, 1, 3, DISABLED}, - {VADC, 0, VADC_G2, 2, 0, DISABLED}, {VADC, 1, VADC_G2, 2, 1, DISABLED}, - {VADC, 6, VADC_G2, 2, 6, DISABLED}, {VADC, 5, VADC_G2, 2, 5, DISABLED}, - {VADC, 3, VADC_G2, 2, 3, DISABLED}, {VADC, 7, VADC_G1, 1, 7, DISABLED}, - {VADC, 5, VADC_G1, 1, 5, DISABLED}, {VADC, 7, VADC_G0, 0, 7, DISABLED}, - {VADC, 7, VADC_G3, 3, 7, DISABLED}, {VADC, 1, VADC_G1, 1, 1, DISABLED}, - {VADC, 0, VADC_G1, 1, 0, DISABLED}, {VADC, 6, VADC_G3, 3, 6, DISABLED}, - {VADC, 6, VADC_G0, 0, 6, DISABLED}, {VADC, 4, VADC_G1, 1, 4, DISABLED}, - {VADC, 6, VADC_G1, 1, 6, DISABLED}, {VADC, 2, VADC_G2, 2, 2, DISABLED}, - {VADC, 4, VADC_G2, 2, 4, DISABLED}, {VADC, 7, VADC_G2, 2, 7, DISABLED}}; +XMC_ADC_t mapping_adc[] = {{VADC, 0, VADC_G0, 0, 0, false}, {VADC, 1, VADC_G0, 0, 1, false}, + {VADC, 2, VADC_G1, 1, 2, false}, {VADC, 3, VADC_G1, 1, 3, false}, + {VADC, 0, VADC_G2, 2, 0, false}, {VADC, 1, VADC_G2, 2, 1, false}, + {VADC, 6, VADC_G2, 2, 6, false}, {VADC, 5, VADC_G2, 2, 5, false}, + {VADC, 3, VADC_G2, 2, 3, false}, {VADC, 7, VADC_G1, 1, 7, false}, + {VADC, 5, VADC_G1, 1, 5, false}, {VADC, 7, VADC_G0, 0, 7, false}, + {VADC, 7, VADC_G3, 3, 7, false}, {VADC, 1, VADC_G1, 1, 1, false}, + {VADC, 0, VADC_G1, 1, 0, false}, {VADC, 6, VADC_G3, 3, 6, false}, + {VADC, 6, VADC_G0, 0, 6, false}, {VADC, 4, VADC_G1, 1, 4, false}, + {VADC, 6, VADC_G1, 1, 6, false}, {VADC, 2, VADC_G2, 2, 2, false}, + {VADC, 4, VADC_G2, 2, 4, false}, {VADC, 7, VADC_G2, 2, 7, false}}; const uint8_t NUM_ANALOG_INPUTS = (sizeof(mapping_adc) / sizeof(XMC_ADC_t)); -/* - * UART objects - * - * Serial 0 is Debug port - * Serial 1 is on-board port - */ -RingBuffer rx_buffer_0; -RingBuffer tx_buffer_0; -RingBuffer rx_buffer_1; -RingBuffer tx_buffer_1; - XMC_UART_t XMC_UART_0 = { .channel = XMC_UART0_CH0, .rx = {.port = (XMC_GPIO_PORT_t *)PORT1_BASE, .pin = (uint8_t)4}, @@ -434,9 +448,9 @@ XMC_UART_t XMC_UART_1 = { .irq_service_request = 0}; // Debug port -HardwareSerial Serial(&XMC_UART_0, &rx_buffer_0, &tx_buffer_0); -// On-board port -HardwareSerial Serial1(&XMC_UART_1, &rx_buffer_1, &tx_buffer_1); +Uart Serial(&XMC_UART_0); +// On-Board port +Uart Serial1(&XMC_UART_1); // Three SPI instances possible XMC_SPI_t XMC_SPI_0 = { @@ -508,80 +522,50 @@ XMC_SPI_t XMC_SPI_2 = { // Only two serial objects are possible: Serial and Serial1 so anymore serial interfaces has to // overwrite/reuse the existing serial objects // Will overwrite Serial -// XMC_SPI_t XMC_SPI_3 = -//{ -// .channel = XMC_SPI0_CH0, -// .channel_config = { -// .baudrate = 20003906U, -// .bus_mode = (XMC_SPI_CH_BUS_MODE_t)XMC_SPI_CH_BUS_MODE_MASTER, -// .selo_inversion = XMC_SPI_CH_SLAVE_SEL_INV_TO_MSLS, -// .parity_mode = XMC_USIC_CH_PARITY_MODE_NONE -// }, -// .mosi = { -// .port = (XMC_GPIO_PORT_t*)PORT5_BASE, -// .pin = (uint8_t)1 -// }, -// .mosi_config = { -// .mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT1, -// .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, -// .output_strength = XMC_GPIO_OUTPUT_STRENGTH_MEDIUM -// }, -// .miso = { -// .port = (XMC_GPIO_PORT_t*)PORT5_BASE, -// .pin = (uint8_t)0 -// }, -// .miso_config = { -// .mode = XMC_GPIO_MODE_INPUT_TRISTATE, -// }, -// .input_source = XMC_INPUT_D, -// .sclkout = { -// .port = (XMC_GPIO_PORT_t*)PORT0_BASE, -// .pin = (uint8_t)8 -// }, -// .sclkout_config = { -// .mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT2, -// .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, -// .output_strength = XMC_GPIO_OUTPUT_STRENGTH_MEDIUM -// }, -// }; +XMC_SPI_t XMC_SPI_3 = { + .channel = XMC_SPI0_CH0, + .channel_config = {.baudrate = 20003906U, + .bus_mode = (XMC_SPI_CH_BUS_MODE_t)XMC_SPI_CH_BUS_MODE_MASTER, + .selo_inversion = XMC_SPI_CH_SLAVE_SEL_INV_TO_MSLS, + .parity_mode = XMC_USIC_CH_PARITY_MODE_NONE}, + .mosi = {.port = (XMC_GPIO_PORT_t *)PORT5_BASE, .pin = (uint8_t)1}, + .mosi_config = {.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT1, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, + .output_strength = XMC_GPIO_OUTPUT_STRENGTH_MEDIUM}, + .miso = {.port = (XMC_GPIO_PORT_t *)PORT5_BASE, .pin = (uint8_t)0}, + .miso_config = + { + .mode = XMC_GPIO_MODE_INPUT_TRISTATE, + }, + .input_source = XMC_INPUT_D, + .sclkout = {.port = (XMC_GPIO_PORT_t *)PORT0_BASE, .pin = (uint8_t)8}, + .sclkout_config = {.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT2, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, + .output_strength = XMC_GPIO_OUTPUT_STRENGTH_MEDIUM}, +}; // Will overwrite Serial1 -// XMC_SPI_t XMC_SPI_4 = -//{ -// .channel = XMC_SPI1_CH0, -// .channel_config = { -// .baudrate = 20003906U, -// .bus_mode = (XMC_SPI_CH_BUS_MODE_t)XMC_SPI_CH_BUS_MODE_MASTER, -// .selo_inversion = XMC_SPI_CH_SLAVE_SEL_INV_TO_MSLS, -// .parity_mode = XMC_USIC_CH_PARITY_MODE_NONE -// }, -// .mosi = { -// .port = (XMC_GPIO_PORT_t*)PORT0_BASE, -// .pin = (uint8_t)5 -// }, -// .mosi_config = { -// .mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT2, -// .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, -// .output_strength = XMC_GPIO_OUTPUT_STRENGTH_MEDIUM -// }, -// .miso = { -// .port = (XMC_GPIO_PORT_t*)PORT0_BASE, -// .pin = (uint8_t)4 -// }, -// .miso_config = { -// .mode = XMC_GPIO_MODE_INPUT_TRISTATE, -// }, -// .input_source = XMC_INPUT_A, -// .sclkout = { -// .port = (XMC_GPIO_PORT_t*)PORT0_BASE, -// .pin = (uint8_t)11 -// }, -// .sclkout_config = { -// .mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT2, -// .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, -// .output_strength = XMC_GPIO_OUTPUT_STRENGTH_MEDIUM -// }, -//}; +XMC_SPI_t XMC_SPI_4 = { + .channel = XMC_SPI1_CH0, + .channel_config = {.baudrate = 20003906U, + .bus_mode = (XMC_SPI_CH_BUS_MODE_t)XMC_SPI_CH_BUS_MODE_MASTER, + .selo_inversion = XMC_SPI_CH_SLAVE_SEL_INV_TO_MSLS, + .parity_mode = XMC_USIC_CH_PARITY_MODE_NONE}, + .mosi = {.port = (XMC_GPIO_PORT_t *)PORT0_BASE, .pin = (uint8_t)5}, + .mosi_config = {.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT2, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, + .output_strength = XMC_GPIO_OUTPUT_STRENGTH_MEDIUM}, + .miso = {.port = (XMC_GPIO_PORT_t *)PORT0_BASE, .pin = (uint8_t)4}, + .miso_config = + { + .mode = XMC_GPIO_MODE_INPUT_TRISTATE, + }, + .input_source = XMC_INPUT_A, + .sclkout = {.port = (XMC_GPIO_PORT_t *)PORT0_BASE, .pin = (uint8_t)11}, + .sclkout_config = {.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT2, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, + .output_strength = XMC_GPIO_OUTPUT_STRENGTH_MEDIUM}, +}; // Two I2C instances possible XMC_I2C_t XMC_I2C_0 = {.channel = XMC_I2C1_CH1, @@ -663,11 +647,7 @@ void USIC1_0_IRQHandler() { Serial1.IrqHandler(); } #ifdef __cplusplus } #endif -#endif /* ARDUINO_MAIN */ -#ifdef __cplusplus -extern HardwareSerial Serial; -extern HardwareSerial Serial1; -#endif /* cplusplus */ +#endif /* ARDUINO_MAIN */ #endif /* PINS_ARDUINO_H_ */