This project is a VHDL implementation of a 5 stages pipelined CPU core using the ARMv3 instruction set. It was a Toy project I used to learn VHDL and cpu architecture.
I successfully ran a simple program (led blink) with this design at 50MHz on a Cyclone IV FPGA. And some test programs in simulation.
The chip was first simulated with ghdl and synthesised with the Alliance CAD tool :
