Single-cycle-RISC-V-CPU/Control_Unit.v at main · P3p111n0/Single-cycle-RISC-V-CPU · GitHub

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//    field    | width
// -----------|----
// BranchBeq  | 1b
// BranchJal  | 1b
// BranchJalr | 1b
// RegWrite   | 1b
// MemToReg   | 1b
// MemWrite   | 1b
// ALUControl | 4b
// ALUSrc     | 1b
// immControl | 3b
// -----------|----
//    total:  | 14 bits => out_control is 14 bits wide
module ControlUnit(input [31:0] instruction, output reg [13:0] out_control);
    always @(instruction) begin
        case(instruction[6:0]) // bits 6:0 contain the opcode
            7'b0000011: out_control = 14'b00011000001000; // lw
            7'b0100011: out_control = 14'b00000100001001; // sw
            7'b0110011: begin
                case(instruction[14:12]) // func3
                    3'b000: begin
                        case (instruction[31:25]) // func7, add or sub
                            7'b0000000: out_control = 14'b00010000000000; // add
                            7'b0100000: out_control = 14'b00010000010000; // sub
                            default: out_control = 0;
                            endcase
                    end
                    3'b010: out_control = 14'b00010001010000; // slt
                    3'b110: begin
                        case (instruction[31:25]) // func7, 'or' or rem
                            7'b0000000: out_control = 14'b00010001000000; // or
                            7'b0000001: out_control = 14'b00010001100000; // rem
                            default: out_control = 0;
                            endcase
                    end
                    3'b111: out_control = 14'b00010000110000; // and
                    3'b100: out_control = 14'b00010000100000; // div
                    default: out_control = 0;
                    endcase
                end
            7'b1100010: out_control = 14'b10000000010010; // beq
            7'b1101111: out_control = 14'b01010000000100; // jal
            7'b1100111: out_control = 14'b00110000001000; // jalr
            7'b0010011: out_control = 14'b00010000001000; // addi
            7'b0110111: out_control = 14'b00010001111011; // lui
            7'b1100011: out_control = 14'b10000001010010; // blt
            default: out_control = 0;
            endcase
    end
endmodule