From 6fa2a371dad45e31a9bfd772af714a5f690365cd Mon Sep 17 00:00:00 2001 From: GuEe-GUI <2991707448@qq.com> Date: Thu, 26 Mar 2026 19:30:26 +0800 Subject: [PATCH] [bsp][rockchip] support RK3528 1. CLK for RK3528 2. Pinctrl for RK3528 3. hwrng for RK-RNG 4. OTP for RK3528 5. TSADC for RK3528 Signed-off-by: GuEe-GUI <2991707448@qq.com> --- bsp/rockchip/dm/adc/adc-rockchip_saradc.c | 18 + bsp/rockchip/dm/clk/Kconfig | 5 + bsp/rockchip/dm/clk/SConscript | 3 + bsp/rockchip/dm/clk/clk-rk3528.c | 1131 +++++++++++++++++ bsp/rockchip/dm/hwcrypto/hw-rng-rockchip.c | 70 + .../dm/include/dt-bindings/clock/rk3528-cru.h | 746 +++++++++++ bsp/rockchip/dm/include/pinctrl-rockchip.h | 2 + bsp/rockchip/dm/nvmem/nvmem-rockchip-otp.c | 7 + bsp/rockchip/dm/pinctrl/pinctrl-rockchip.c | 217 +++- .../dm/thermal/thermal-rockchip_tsadc.c | 111 ++ bsp/rockchip/rk3500/.config | 23 +- bsp/rockchip/rk3500/README.md | 5 +- bsp/rockchip/rk3500/README_ZH.md | 3 +- bsp/rockchip/rk3500/rtconfig.h | 16 +- bsp/rockchip/rk3500/rtconfig.py | 5 +- 15 files changed, 2332 insertions(+), 30 deletions(-) create mode 100755 bsp/rockchip/dm/clk/clk-rk3528.c create mode 100755 bsp/rockchip/dm/include/dt-bindings/clock/rk3528-cru.h diff --git a/bsp/rockchip/dm/adc/adc-rockchip_saradc.c b/bsp/rockchip/dm/adc/adc-rockchip_saradc.c index 953b706f24d..fdb119d4c23 100755 --- a/bsp/rockchip/dm/adc/adc-rockchip_saradc.c +++ b/bsp/rockchip/dm/adc/adc-rockchip_saradc.c @@ -223,6 +223,23 @@ static const struct rockchip_saradc_soc_data rk3399_saradc_data = .power_down = rockchip_saradc_power_down_v1, }; +static const struct saradc_channel rockchip_rk3528_channels[] = +{ + SARADC_CHANNEL(0, "adc0", 10), + SARADC_CHANNEL(1, "adc1", 10), + SARADC_CHANNEL(2, "adc2", 10), + SARADC_CHANNEL(3, "adc3", 10), +}; + +static const struct rockchip_saradc_soc_data rk3528_saradc_data = +{ + .channels = rockchip_rk3528_channels, + .num_channels = RT_ARRAY_SIZE(rockchip_rk3528_channels), + .clk_rate = 1000000, + .start = rockchip_saradc_start_v2, + .read = rockchip_saradc_read_v2, +}; + static const struct saradc_channel rk3568_saradc_channels[] = { SARADC_CHANNEL(0, "adc0", 10), @@ -503,6 +520,7 @@ static const struct rt_ofw_node_id rockchip_saradc_ofw_ids[] = { .compatible = "rockchip,saradc", .data = &saradc_data }, { .compatible = "rockchip,rk3066-tsadc", .data = &rk3066_tsadc_data }, { .compatible = "rockchip,rk3399-saradc", .data = &rk3399_saradc_data }, + { .compatible = "rockchip,rk3528-saradc", .data = &rk3528_saradc_data, }, { .compatible = "rockchip,rk3568-saradc", .data = &rk3568_saradc_data }, { .compatible = "rockchip,rk3588-saradc", .data = &rk3588_saradc_data, }, { /* sentinel */ } diff --git a/bsp/rockchip/dm/clk/Kconfig b/bsp/rockchip/dm/clk/Kconfig index cb56f669cc1..70a49f8ff0c 100755 --- a/bsp/rockchip/dm/clk/Kconfig +++ b/bsp/rockchip/dm/clk/Kconfig @@ -20,6 +20,11 @@ config RT_CLK_ROCKCHIP_RK3308 depends on RT_CLK_ROCKCHIP default n +config RT_CLK_ROCKCHIP_RK3528 + bool "Rockchip RK3528 clock controller support" + depends on RT_CLK_ROCKCHIP + default n + config RT_CLK_ROCKCHIP_RK3568 bool "Rockchip RK3568 clock controller support" depends on RT_CLK_ROCKCHIP diff --git a/bsp/rockchip/dm/clk/SConscript b/bsp/rockchip/dm/clk/SConscript index 5b25e43f474..cdfbbccc51f 100755 --- a/bsp/rockchip/dm/clk/SConscript +++ b/bsp/rockchip/dm/clk/SConscript @@ -19,6 +19,9 @@ if GetDepend(['RT_CLK_ROCKCHIP']): if GetDepend(['RT_CLK_ROCKCHIP_RK3308']): src += ['clk-rk3308.c'] +if GetDepend(['RT_CLK_ROCKCHIP_RK3528']): + src += ['clk-rk3528.c'] + if GetDepend(['RT_CLK_ROCKCHIP_RK3568']): src += ['clk-rk3568.c'] diff --git a/bsp/rockchip/dm/clk/clk-rk3528.c b/bsp/rockchip/dm/clk/clk-rk3528.c new file mode 100755 index 00000000000..c77e74d3602 --- /dev/null +++ b/bsp/rockchip/dm/clk/clk-rk3528.c @@ -0,0 +1,1131 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-3-15 GuEe-GUI the first version + */ + +#include "clk-rk-composite.h" +#include "clk-rk-cpu.h" +#include "clk-rk-divider.h" +#include "clk-rk-factor.h" +#include "clk-rk-fraction-divider.h" +#include "clk-rk-gate.h" +#include "clk-rk.h" +#include "clk-rk-half-divider.h" +#include "clk-rk-mmc-phase.h" +#include "clk-rk-muxgrf.h" +#include "clk-rk-mux.h" +#include "clk-rk-pll.h" + +#define DBG_TAG "clk.rk3528" +#define DBG_LVL DBG_INFO +#include + +#include + +#define RK3528_GRF_SOC_STATUS0 0x1a0 + +#define RK3528_PMU_CRU_BASE 0x10000 +#define RK3528_PCIE_CRU_BASE 0x20000 +#define RK3528_DDRPHY_CRU_BASE 0x28000 +#define RK3528_VPU_GRF_BASE 0x40000 +#define RK3528_VO_GRF_BASE 0x60000 +#define RK3528_SDMMC_CON0 (RK3528_VO_GRF_BASE + 0x24) +#define RK3528_SDMMC_CON1 (RK3528_VO_GRF_BASE + 0x28) +#define RK3528_SDIO0_CON0 (RK3528_VPU_GRF_BASE + 0x4) +#define RK3528_SDIO0_CON1 (RK3528_VPU_GRF_BASE + 0x8) +#define RK3528_SDIO1_CON0 (RK3528_VPU_GRF_BASE + 0xc) +#define RK3528_SDIO1_CON1 (RK3528_VPU_GRF_BASE + 0x10) +#define RK3528_PLL_CON(x) ((x) * 0x4) +#define RK3528_PCIE_PLL_CON(x) ((x) * 0x4 + RK3528_PCIE_CRU_BASE) +#define RK3528_DDRPHY_PLL_CON(x) ((x) * 0x4 + RK3528_DDRPHY_CRU_BASE) +#define RK3528_MODE_CON 0x280 +#define RK3528_CLKSEL_CON(x) ((x) * 0x4 + 0x300) +#define RK3528_CLKGATE_CON(x) ((x) * 0x4 + 0x800) +#define RK3528_SOFTRST_CON(x) ((x) * 0x4 + 0xa00) +#define RK3528_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PMU_CRU_BASE) +#define RK3528_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_PMU_CRU_BASE) +#define RK3528_PCIE_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PCIE_CRU_BASE) +#define RK3528_PCIE_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_PCIE_CRU_BASE) +#define RK3528_DDRPHY_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_DDRPHY_CRU_BASE) +#define RK3528_DDRPHY_MODE_CON (0x280 + RK3528_DDRPHY_CRU_BASE) +#define RK3528_GLB_CNT_TH 0xc00 +#define RK3528_GLB_SRST_FST 0xc08 +#define RK3528_GLB_SRST_SND 0xc0c + +#define RK3528_DIV_ACLK_M_CORE_MASK 0x1f +#define RK3528_DIV_ACLK_M_CORE_SHIFT 11 +#define RK3528_DIV_PCLK_DBG_MASK 0x1f +#define RK3528_DIV_PCLK_DBG_SHIFT 1 + +struct clk_rk3528_cru +{ + struct rt_clk_node clk_parent; + struct rt_reset_controller rstc_parent; + + struct rockchip_clk_provider provider; +}; + +static struct rockchip_pll_rate_table rk3528_pll_rates[] = +{ + /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ + RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0), + RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0), + RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0), + RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), + RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), + RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), + RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), + RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), + RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0), /* GPLL */ + RK3036_PLL_RATE(1092000000, 2, 91, 1, 1, 1, 0), + RK3036_PLL_RATE(1008000000, 1, 42, 1, 1, 1, 0), + RK3036_PLL_RATE(1000000000, 1, 125, 3, 1, 1, 0), /* PPLL */ + RK3036_PLL_RATE(996000000, 2, 83, 1, 1, 1, 0), /* CPLL */ + RK3036_PLL_RATE(960000000, 1, 40, 1, 1, 1, 0), + RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0), + RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0), + RK3036_PLL_RATE(600000000, 1, 50, 2, 1, 1, 0), + RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0), + RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0), + RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0), + RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0), + RK3036_PLL_RATE(96000000, 1, 24, 3, 2, 1, 0), + { /* sentinel */ }, +}; + +#define RK3528_CLKSEL39(_aclk_m_core) \ +{ \ + .reg = RK3528_CLKSEL_CON(39), \ + .val = HIWORD_UPDATE(_aclk_m_core, RK3528_DIV_ACLK_M_CORE_MASK, \ + RK3528_DIV_ACLK_M_CORE_SHIFT), \ +} + +#define RK3528_CLKSEL40(_pclk_dbg) \ +{ \ + .reg = RK3528_CLKSEL_CON(40), \ + .val = HIWORD_UPDATE(_pclk_dbg, RK3528_DIV_PCLK_DBG_MASK, \ + RK3528_DIV_PCLK_DBG_SHIFT), \ +} + +#define RK3528_CPUCLK_RATE(_prate, _aclk_m_core, _pclk_dbg) \ +{ \ + .prate = _prate, \ + .divs = \ + { \ + RK3528_CLKSEL39(_aclk_m_core), \ + RK3528_CLKSEL40(_pclk_dbg), \ + } \ +} + +static struct rockchip_cpu_clk_rate_table rk3528_cpu_clk_rates[] = +{ + RK3528_CPUCLK_RATE(1896000000, 1, 13), + RK3528_CPUCLK_RATE(1800000000, 1, 12), + RK3528_CPUCLK_RATE(1704000000, 1, 11), + RK3528_CPUCLK_RATE(1608000000, 1, 11), + RK3528_CPUCLK_RATE(1512000000, 1, 11), + RK3528_CPUCLK_RATE(1416000000, 1, 9), + RK3528_CPUCLK_RATE(1296000000, 1, 8), + RK3528_CPUCLK_RATE(1200000000, 1, 8), + RK3528_CPUCLK_RATE(1188000000, 1, 8), + RK3528_CPUCLK_RATE(1092000000, 1, 7), + RK3528_CPUCLK_RATE(1008000000, 1, 6), + RK3528_CPUCLK_RATE(1000000000, 1, 6), + RK3528_CPUCLK_RATE(996000000, 1, 6), + RK3528_CPUCLK_RATE(960000000, 1, 6), + RK3528_CPUCLK_RATE(912000000, 1, 6), + RK3528_CPUCLK_RATE(816000000, 1, 5), + RK3528_CPUCLK_RATE(600000000, 1, 3), + RK3528_CPUCLK_RATE(594000000, 1, 3), + RK3528_CPUCLK_RATE(408000000, 1, 2), + RK3528_CPUCLK_RATE(312000000, 1, 2), + RK3528_CPUCLK_RATE(216000000, 1, 1), + RK3528_CPUCLK_RATE(96000000, 1, 0), +}; + +static const struct rockchip_cpu_clk_reg_data rk3528_cpu_clk_data = +{ + .core_reg[0] = RK3528_CLKSEL_CON(39), + .div_core_shift[0] = 5, + .div_core_mask[0] = 0x1f, + .num_cores = 1, + .mux_core_alt = 1, + .mux_core_main = 0, + .mux_core_shift = 10, + .mux_core_mask = 0x1, +}; + +PNAME(mux_pll_p) = "xin24m"; +PNAMES(mux_24m_32k_p) = { "xin24m", "clk_32k" }; +PNAMES(mux_gpll_cpll_p) = { "gpll", "cpll" }; +PNAMES(mux_gpll_cpll_xin24m_p) = { "gpll", "cpll", "xin24m" }; +PNAMES(mux_100m_50m_24m_p) = { "clk_100m_src", "clk_50m_src", "xin24m" }; +PNAMES(mux_150m_100m_24m_p) = { "clk_150m_src", "clk_100m_src", "xin24m" }; +PNAMES(mux_200m_100m_24m_p) = { "clk_200m_src", "clk_100m_src", "xin24m" }; +PNAMES(mux_200m_100m_50m_24m_p) = { "clk_200m_src", "clk_100m_src", "clk_50m_src", "xin24m" }; +PNAMES(mux_300m_200m_100m_24m_p) = { "clk_300m_src", "clk_200m_src", "clk_100m_src", "xin24m" }; +PNAMES(mux_339m_200m_100m_24m_p) = { "clk_339m_src", "clk_200m_src", "clk_100m_src", "xin24m" }; +PNAMES(mux_500m_200m_100m_24m_p) = { "clk_500m_src", "clk_200m_src", "clk_100m_src", "xin24m" }; +PNAMES(mux_500m_300m_100m_24m_p) = { "clk_500m_src", "clk_300m_src", "clk_100m_src", "xin24m" }; +PNAMES(mux_600m_300m_200m_24m_p) = { "clk_600m_src", "clk_300m_src", "clk_200m_src", "xin24m" }; +PNAMES(aclk_gpu_p) = { "aclk_gpu_root", "clk_gpu_pvtpll_src" }; +PNAMES(aclk_rkvdec_pvtmux_root_p) = { "aclk_rkvdec_root", "clk_rkvdec_pvtpll_src" }; +PNAMES(clk_i2c2_p) = { "clk_200m_src", "clk_100m_src", "xin24m", "clk_32k" }; +PNAMES(clk_ref_pcie_inner_phy_p) = { "clk_ppll_100m_src", "xin24m" }; +PNAMES(dclk_vop0_p) = { "dclk_vop_src0", "clk_hdmiphy_pixel_io" }; +PNAMES(mclk_i2s0_2ch_sai_src_p) = { "clk_i2s0_2ch_src", "clk_i2s0_2ch_frac", "xin12m" }; +PNAMES(mclk_i2s1_8ch_sai_src_p) = { "clk_i2s1_8ch_src", "clk_i2s1_8ch_frac", "xin12m" }; +PNAMES(mclk_i2s2_2ch_sai_src_p) = { "clk_i2s2_2ch_src", "clk_i2s2_2ch_frac", "xin12m" }; +PNAMES(mclk_i2s3_8ch_sai_src_p) = { "clk_i2s3_8ch_src", "clk_i2s3_8ch_frac", "xin12m" }; +PNAMES(mclk_sai_i2s0_p) = { "mclk_i2s0_2ch_sai_src", "i2s0_mclkin" }; +PNAMES(mclk_sai_i2s1_p) = { "mclk_i2s1_8ch_sai_src", "i2s1_mclkin" }; +PNAMES(mclk_spdif_src_p) = { "clk_spdif_src", "clk_spdif_frac", "xin12m" }; +PNAMES(sclk_uart0_src_p) = { "clk_uart0_src", "clk_uart0_frac", "xin24m" }; +PNAMES(sclk_uart1_src_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" }; +PNAMES(sclk_uart2_src_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" }; +PNAMES(sclk_uart3_src_p) = { "clk_uart3_src", "clk_uart3_frac", "xin24m" }; +PNAMES(sclk_uart4_src_p) = { "clk_uart4_src", "clk_uart4_frac", "xin24m" }; +PNAMES(sclk_uart5_src_p) = { "clk_uart5_src", "clk_uart5_frac", "xin24m" }; +PNAMES(sclk_uart6_src_p) = { "clk_uart6_src", "clk_uart6_frac", "xin24m" }; +PNAMES(sclk_uart7_src_p) = { "clk_uart7_src", "clk_uart7_frac", "xin24m" }; +PNAMES(clk_32k_p) = { "xin_osc0_div", "clk_pvtm_32k" }; + +#define MFLAGS CLK_MUX_HIWORD_MASK +#define DFLAGS CLK_DIVIDER_HIWORD_MASK +#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) + +static struct rockchip_pll_clk_cell rk3528_pll_apll = + PLL_RAW(pll_type_rk3328, PLL_APLL, "apll", mux_pll_p, 1, RT_CLK_F_IS_CRITICAL, RK3528_PLL_CON(0), RK3528_MODE_CON, + 0, 0, RK3528_GRF_SOC_STATUS0, 0, rk3528_pll_rates); +static struct rockchip_pll_clk_cell rk3528_pll_cpll = + PLL_RAW(pll_type_rk3328, PLL_CPLL, "cpll", mux_pll_p, 1, RT_CLK_F_IS_CRITICAL, RK3528_PLL_CON(8), RK3528_MODE_CON, + 2, 0, RK3528_GRF_SOC_STATUS0, 0, rk3528_pll_rates); +static struct rockchip_pll_clk_cell rk3528_pll_gpll = + PLL_RAW(pll_type_rk3328, PLL_GPLL, "gpll", mux_pll_p, 1, RT_CLK_F_IS_CRITICAL, RK3528_PLL_CON(24), RK3528_MODE_CON, + 4, 0, RK3528_GRF_SOC_STATUS0, 0, rk3528_pll_rates); +static struct rockchip_pll_clk_cell rk3528_pll_ppll = + PLL_RAW(pll_type_rk3328, PLL_PPLL, "ppll", mux_pll_p, 1, RT_CLK_F_IS_CRITICAL, RK3528_PCIE_PLL_CON(32), RK3528_MODE_CON, + 6, 0, RK3528_GRF_SOC_STATUS0, ROCKCHIP_PLL_FIXED_MODE, rk3528_pll_rates); +static struct rockchip_pll_clk_cell rk3528_pll_dpll = + PLL_RAW(pll_type_rk3328, PLL_DPLL, "dpll", mux_pll_p, 1, RT_CLK_F_IGNORE_UNUSED, RK3528_DDRPHY_PLL_CON(16), RK3528_DDRPHY_MODE_CON, + 0, 0, RK3528_GRF_SOC_STATUS0, 0, rk3528_pll_rates); + +static struct rockchip_clk_cell rk3528_uart0_fracmux = + MUX_RAW(CLK_UART0, "clk_uart0", sclk_uart0_src_p, RT_CLK_F_SET_RATE_PARENT, + RK3528_CLKSEL_CON(6), 0, 2, MFLAGS); + +static struct rockchip_clk_cell rk3528_uart1_fracmux = + MUX_RAW(CLK_UART1, "clk_uart1", sclk_uart1_src_p, RT_CLK_F_SET_RATE_PARENT, + RK3528_CLKSEL_CON(8), 0, 2, MFLAGS); + +static struct rockchip_clk_cell rk3528_uart2_fracmux = + MUX_RAW(CLK_UART2, "clk_uart2", sclk_uart2_src_p, RT_CLK_F_SET_RATE_PARENT, + RK3528_CLKSEL_CON(10), 0, 2, MFLAGS); + +static struct rockchip_clk_cell rk3528_uart3_fracmux = + MUX_RAW(CLK_UART3, "clk_uart3", sclk_uart3_src_p, RT_CLK_F_SET_RATE_PARENT, + RK3528_CLKSEL_CON(12), 0, 2, MFLAGS); + +static struct rockchip_clk_cell rk3528_uart4_fracmux = + MUX_RAW(CLK_UART4, "clk_uart4", sclk_uart4_src_p, RT_CLK_F_SET_RATE_PARENT, + RK3528_CLKSEL_CON(14), 0, 2, MFLAGS); + +static struct rockchip_clk_cell rk3528_uart5_fracmux = + MUX_RAW(CLK_UART5, "clk_uart5", sclk_uart5_src_p, RT_CLK_F_SET_RATE_PARENT, + RK3528_CLKSEL_CON(16), 0, 2, MFLAGS); + +static struct rockchip_clk_cell rk3528_uart6_fracmux = + MUX_RAW(CLK_UART6, "clk_uart6", sclk_uart6_src_p, RT_CLK_F_SET_RATE_PARENT, + RK3528_CLKSEL_CON(18), 0, 2, MFLAGS); + +static struct rockchip_clk_cell rk3528_uart7_fracmux = + MUX_RAW(CLK_UART7, "clk_uart7", sclk_uart7_src_p, RT_CLK_F_SET_RATE_PARENT, + RK3528_CLKSEL_CON(20), 0, 2, MFLAGS); + +static struct rockchip_clk_cell mclk_i2s0_2ch_sai_src_fracmux = + MUX_RAW(MCLK_I2S0_2CH_SAI_SRC_PRE, "mclk_i2s0_2ch_sai_src_pre", mclk_i2s0_2ch_sai_src_p, RT_CLK_F_SET_RATE_PARENT, + RK3528_CLKSEL_CON(22), 0, 2, MFLAGS); + +static struct rockchip_clk_cell mclk_i2s1_8ch_sai_src_fracmux = + MUX_RAW(MCLK_I2S1_8CH_SAI_SRC_PRE, "mclk_i2s1_8ch_sai_src_pre", mclk_i2s1_8ch_sai_src_p, RT_CLK_F_SET_RATE_PARENT, + RK3528_CLKSEL_CON(26), 0, 2, MFLAGS); + +static struct rockchip_clk_cell mclk_i2s2_2ch_sai_src_fracmux = + MUX_RAW(MCLK_I2S2_2CH_SAI_SRC_PRE, "mclk_i2s2_2ch_sai_src_pre", mclk_i2s2_2ch_sai_src_p, RT_CLK_F_SET_RATE_PARENT, + RK3528_CLKSEL_CON(28), 0, 2, MFLAGS); + +static struct rockchip_clk_cell mclk_i2s3_8ch_sai_src_fracmux = + MUX_RAW(MCLK_I2S3_8CH_SAI_SRC_PRE, "mclk_i2s3_8ch_sai_src_pre", mclk_i2s3_8ch_sai_src_p, RT_CLK_F_SET_RATE_PARENT, + RK3528_CLKSEL_CON(24), 0, 2, MFLAGS); + +static struct rockchip_clk_cell mclk_spdif_src_fracmux = + MUX_RAW(MCLK_SDPDIF_SRC_PRE, "mclk_spdif_src_pre", mclk_spdif_src_p, RT_CLK_F_SET_RATE_PARENT, + RK3528_CLKSEL_CON(32), 0, 2, MFLAGS); + +static struct rt_clk_cell *rk3528_clk_cells[] = +{ + [PLL_APLL] = &rk3528_pll_apll.rk_cell.cell, + [PLL_CPLL] = &rk3528_pll_cpll.rk_cell.cell, + [PLL_GPLL] = &rk3528_pll_gpll.rk_cell.cell, + [PLL_PPLL] = &rk3528_pll_ppll.rk_cell.cell, + [PLL_DPLL] = &rk3528_pll_dpll.rk_cell.cell, + [ARMCLK] = CPU(ARMCLK, "armclk", &rk3528_pll_apll.rk_cell, &rk3528_pll_gpll.rk_cell, + rk3528_cpu_clk_rates, RT_ARRAY_SIZE(rk3528_cpu_clk_rates), &rk3528_cpu_clk_data), + /* top */ + [CLK_MATRIX_250M_SRC] = COMPOSITE(CLK_MATRIX_250M_SRC, "clk_250m_src", mux_gpll_cpll_p, RT_CLK_F_IS_CRITICAL, + RK3528_CLKSEL_CON(1), 15, 1, MFLAGS, 10, 5, DFLAGS, + RK3528_CLKGATE_CON(0), 5, GFLAGS), + [CLK_MATRIX_500M_SRC] = COMPOSITE(CLK_MATRIX_500M_SRC, "clk_500m_src", mux_gpll_cpll_p, RT_CLK_F_IS_CRITICAL, + RK3528_CLKSEL_CON(3), 11, 1, MFLAGS, 6, 5, DFLAGS, + RK3528_CLKGATE_CON(0), 10, GFLAGS), + [CLK_MATRIX_50M_SRC] = COMPOSITE_NOMUX(CLK_MATRIX_50M_SRC, "clk_50m_src", "cpll", RT_CLK_F_IS_CRITICAL, + RK3528_CLKSEL_CON(0), 2, 5, DFLAGS, + RK3528_CLKGATE_CON(0), 1, GFLAGS), + [CLK_MATRIX_100M_SRC] = COMPOSITE_NOMUX(CLK_MATRIX_100M_SRC, "clk_100m_src", "cpll", RT_CLK_F_IS_CRITICAL, + RK3528_CLKSEL_CON(0), 7, 5, DFLAGS, + RK3528_CLKGATE_CON(0), 2, GFLAGS), + [CLK_MATRIX_150M_SRC] = COMPOSITE_NOMUX(CLK_MATRIX_150M_SRC, "clk_150m_src", "gpll", RT_CLK_F_IS_CRITICAL, + RK3528_CLKSEL_CON(1), 0, 5, DFLAGS, + RK3528_CLKGATE_CON(0), 3, GFLAGS), + [CLK_MATRIX_200M_SRC] = COMPOSITE_NOMUX(CLK_MATRIX_200M_SRC, "clk_200m_src", "gpll", RT_CLK_F_IS_CRITICAL, + RK3528_CLKSEL_CON(1), 5, 5, DFLAGS, + RK3528_CLKGATE_CON(0), 4, GFLAGS), + [CLK_MATRIX_300M_SRC] = COMPOSITE_NOMUX(CLK_MATRIX_300M_SRC, "clk_300m_src", "gpll", RT_CLK_F_IS_CRITICAL, + RK3528_CLKSEL_CON(2), 0, 5, DFLAGS, + RK3528_CLKGATE_CON(0), 6, GFLAGS), + [CLK_MATRIX_339M_SRC] = COMPOSITE_NOMUX_HALFDIV(CLK_MATRIX_339M_SRC, "clk_339m_src", "gpll", RT_CLK_F_IS_CRITICAL, + RK3528_CLKSEL_CON(2), 5, 5, DFLAGS, + RK3528_CLKGATE_CON(0), 7, GFLAGS), + [CLK_MATRIX_400M_SRC] = COMPOSITE_NOMUX(CLK_MATRIX_400M_SRC, "clk_400m_src", "gpll", RT_CLK_F_IGNORE_UNUSED, + RK3528_CLKSEL_CON(2), 10, 5, DFLAGS, + RK3528_CLKGATE_CON(0), 8, GFLAGS), + [CLK_MATRIX_600M_SRC] = COMPOSITE_NOMUX(CLK_MATRIX_600M_SRC, "clk_600m_src", "gpll", RT_CLK_F_IS_CRITICAL, + RK3528_CLKSEL_CON(4), 0, 5, DFLAGS, + RK3528_CLKGATE_CON(0), 11, GFLAGS), + [DCLK_VOP_SRC0] = COMPOSITE(DCLK_VOP_SRC0, "dclk_vop_src0", mux_gpll_cpll_p, 0, + RK3528_CLKSEL_CON(32), 10, 1, MFLAGS, 2, 8, DFLAGS, + RK3528_CLKGATE_CON(3), 7, GFLAGS), + [DCLK_VOP_SRC1] = COMPOSITE(DCLK_VOP_SRC1, "dclk_vop_src1", mux_gpll_cpll_p, 0, + RK3528_CLKSEL_CON(33), 8, 1, MFLAGS, 0, 8, DFLAGS, + RK3528_CLKGATE_CON(3), 8, GFLAGS), + [CLK_HSM] = COMPOSITE_NOMUX(CLK_HSM, "clk_hsm", "xin24m", 0, + RK3528_CLKSEL_CON(36), 5, 5, DFLAGS, + RK3528_CLKGATE_CON(3), 13, GFLAGS), + [CLK_UART0_SRC] = COMPOSITE_NOMUX(CLK_UART0_SRC, "clk_uart0_src", "gpll", 0, + RK3528_CLKSEL_CON(4), 5, 5, DFLAGS, + RK3528_CLKGATE_CON(0), 12, GFLAGS), + [CLK_UART0_FRAC] = COMPOSITE_FRACMUX(CLK_UART0_FRAC, "clk_uart0_frac", "clk_uart0_src", RT_CLK_F_SET_RATE_PARENT, + RK3528_CLKSEL_CON(5), 0, + RK3528_CLKGATE_CON(0), 13, GFLAGS, &rk3528_uart0_fracmux), + [SCLK_UART0] = GATE(SCLK_UART0, "sclk_uart0", "clk_uart0", 0, + RK3528_CLKGATE_CON(0), 14, GFLAGS), + [CLK_UART1_SRC] = COMPOSITE_NOMUX(CLK_UART1_SRC, "clk_uart1_src", "gpll", 0, + RK3528_CLKSEL_CON(6), 2, 5, DFLAGS, + RK3528_CLKGATE_CON(0), 15, GFLAGS), + [CLK_UART1_FRAC] = COMPOSITE_FRACMUX(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", RT_CLK_F_SET_RATE_PARENT, + RK3528_CLKSEL_CON(7), 0, + RK3528_CLKGATE_CON(1), 0, GFLAGS, &rk3528_uart1_fracmux), + [SCLK_UART1] = GATE(SCLK_UART1, "sclk_uart1", "clk_uart1", 0, + RK3528_CLKGATE_CON(1), 1, GFLAGS), + [CLK_UART2_SRC] = COMPOSITE_NOMUX(CLK_UART2_SRC, "clk_uart2_src", "gpll", 0, + RK3528_CLKSEL_CON(8), 2, 5, DFLAGS, + RK3528_CLKGATE_CON(1), 2, GFLAGS), + [CLK_UART2_FRAC] = COMPOSITE_FRACMUX(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", RT_CLK_F_SET_RATE_PARENT, + RK3528_CLKSEL_CON(9), 0, + RK3528_CLKGATE_CON(1), 3, GFLAGS, &rk3528_uart2_fracmux), + [SCLK_UART2] = GATE(SCLK_UART2, "sclk_uart2", "clk_uart2", 0, + RK3528_CLKGATE_CON(1), 4, GFLAGS), + [CLK_UART3_SRC] = COMPOSITE_NOMUX(CLK_UART3_SRC, "clk_uart3_src", "gpll", 0, + RK3528_CLKSEL_CON(10), 2, 5, DFLAGS, + RK3528_CLKGATE_CON(1), 5, GFLAGS), + [CLK_UART3_FRAC] = COMPOSITE_FRACMUX(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_src", RT_CLK_F_SET_RATE_PARENT, + RK3528_CLKSEL_CON(11), 0, + RK3528_CLKGATE_CON(1), 6, GFLAGS, &rk3528_uart3_fracmux), + [SCLK_UART3] = GATE(SCLK_UART3, "sclk_uart3", "clk_uart3", 0, + RK3528_CLKGATE_CON(1), 7, GFLAGS), + [CLK_UART4_SRC] = COMPOSITE_NOMUX(CLK_UART4_SRC, "clk_uart4_src", "gpll", 0, + RK3528_CLKSEL_CON(12), 2, 5, DFLAGS, + RK3528_CLKGATE_CON(1), 8, GFLAGS), + [CLK_UART4_FRAC] = COMPOSITE_FRACMUX(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_src", RT_CLK_F_SET_RATE_PARENT, + RK3528_CLKSEL_CON(13), 0, + RK3528_CLKGATE_CON(1), 9, GFLAGS, &rk3528_uart4_fracmux), + [SCLK_UART4] = GATE(SCLK_UART4, "sclk_uart4", "clk_uart4", 0, + RK3528_CLKGATE_CON(1), 10, GFLAGS), + [CLK_UART5_SRC] = COMPOSITE_NOMUX(CLK_UART5_SRC, "clk_uart5_src", "gpll", 0, + RK3528_CLKSEL_CON(14), 2, 5, DFLAGS, + RK3528_CLKGATE_CON(1), 11, GFLAGS), + [CLK_UART5_FRAC] = COMPOSITE_FRACMUX(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_src", RT_CLK_F_SET_RATE_PARENT, + RK3528_CLKSEL_CON(15), 0, + RK3528_CLKGATE_CON(1), 12, GFLAGS, &rk3528_uart5_fracmux), + [SCLK_UART5] = GATE(SCLK_UART5, "sclk_uart5", "clk_uart5", 0, + RK3528_CLKGATE_CON(1), 13, GFLAGS), + [CLK_UART6_SRC] = COMPOSITE_NOMUX(CLK_UART6_SRC, "clk_uart6_src", "gpll", 0, + RK3528_CLKSEL_CON(16), 2, 5, DFLAGS, + RK3528_CLKGATE_CON(1), 14, GFLAGS), + [CLK_UART6_FRAC] = COMPOSITE_FRACMUX(CLK_UART6_FRAC, "clk_uart6_frac", "clk_uart6_src", RT_CLK_F_SET_RATE_PARENT, + RK3528_CLKSEL_CON(17), 0, + RK3528_CLKGATE_CON(1), 15, GFLAGS, &rk3528_uart6_fracmux), + [SCLK_UART6] = GATE(SCLK_UART6, "sclk_uart6", "clk_uart6", 0, + RK3528_CLKGATE_CON(2), 0, GFLAGS), + [CLK_UART7_SRC] = COMPOSITE_NOMUX(CLK_UART7_SRC, "clk_uart7_src", "gpll", 0, + RK3528_CLKSEL_CON(18), 2, 5, DFLAGS, + RK3528_CLKGATE_CON(2), 1, GFLAGS), + [CLK_UART7_FRAC] = COMPOSITE_FRACMUX(CLK_UART7_FRAC, "clk_uart7_frac", "clk_uart7_src", RT_CLK_F_SET_RATE_PARENT, + RK3528_CLKSEL_CON(19), 0, + RK3528_CLKGATE_CON(2), 2, GFLAGS, &rk3528_uart7_fracmux), + [SCLK_UART7] = GATE(SCLK_UART7, "sclk_uart7", "clk_uart7", 0, + RK3528_CLKGATE_CON(2), 3, GFLAGS), + [CLK_I2S0_2CH_SRC] = COMPOSITE_NOMUX(CLK_I2S0_2CH_SRC, "clk_i2s0_2ch_src", "gpll", 0, + RK3528_CLKSEL_CON(20), 8, 5, DFLAGS, + RK3528_CLKGATE_CON(2), 5, GFLAGS), + [CLK_I2S0_2CH_FRAC] = COMPOSITE_FRACMUX(CLK_I2S0_2CH_FRAC, "clk_i2s0_2ch_frac", "clk_i2s0_2ch_src", RT_CLK_F_SET_RATE_PARENT, + RK3528_CLKSEL_CON(21), 0, + RK3528_CLKGATE_CON(2), 6, GFLAGS, &mclk_i2s0_2ch_sai_src_fracmux), + [MCLK_I2S0_2CH_SAI_SRC] = GATE(MCLK_I2S0_2CH_SAI_SRC, "mclk_i2s0_2ch_sai_src", "mclk_i2s0_2ch_sai_src_pre", 0, + RK3528_CLKGATE_CON(2), 7, GFLAGS), + [CLK_I2S1_8CH_SRC] = COMPOSITE_NOMUX(CLK_I2S1_8CH_SRC, "clk_i2s1_8ch_src", "gpll", 0, + RK3528_CLKSEL_CON(24), 3, 5, DFLAGS, + RK3528_CLKGATE_CON(2), 11, GFLAGS), + [CLK_I2S1_8CH_FRAC] = COMPOSITE_FRACMUX(CLK_I2S1_8CH_FRAC, "clk_i2s1_8ch_frac", "clk_i2s1_8ch_src", RT_CLK_F_SET_RATE_PARENT, + RK3528_CLKSEL_CON(25), 0, + RK3528_CLKGATE_CON(2), 12, GFLAGS, &mclk_i2s1_8ch_sai_src_fracmux), + [MCLK_I2S1_8CH_SAI_SRC] = GATE(MCLK_I2S1_8CH_SAI_SRC, "mclk_i2s1_8ch_sai_src", "mclk_i2s1_8ch_sai_src_pre", 0, + RK3528_CLKGATE_CON(2), 13, GFLAGS), + [CLK_I2S2_2CH_SRC] = COMPOSITE_NOMUX(CLK_I2S2_2CH_SRC, "clk_i2s2_2ch_src", "gpll", 0, + RK3528_CLKSEL_CON(26), 3, 5, DFLAGS, + RK3528_CLKGATE_CON(2), 14, GFLAGS), + [CLK_I2S2_2CH_FRAC] = COMPOSITE_FRACMUX(CLK_I2S2_2CH_FRAC, "clk_i2s2_2ch_frac", "clk_i2s2_2ch_src", RT_CLK_F_SET_RATE_PARENT, + RK3528_CLKSEL_CON(27), 0, + RK3528_CLKGATE_CON(2), 15, GFLAGS, &mclk_i2s2_2ch_sai_src_fracmux), + [MCLK_I2S2_2CH_SAI_SRC] = GATE(MCLK_I2S2_2CH_SAI_SRC, "mclk_i2s2_2ch_sai_src", "mclk_i2s2_2ch_sai_src_pre", 0, + RK3528_CLKGATE_CON(3), 0, GFLAGS), + [CLK_I2S3_8CH_SRC] = COMPOSITE_NOMUX(CLK_I2S3_8CH_SRC, "clk_i2s3_8ch_src", "gpll", 0, + RK3528_CLKSEL_CON(22), 3, 5, DFLAGS, + RK3528_CLKGATE_CON(2), 8, GFLAGS), + [CLK_I2S3_8CH_FRAC] = COMPOSITE_FRACMUX(CLK_I2S3_8CH_FRAC, "clk_i2s3_8ch_frac", "clk_i2s3_8ch_src", RT_CLK_F_SET_RATE_PARENT, + RK3528_CLKSEL_CON(23), 0, + RK3528_CLKGATE_CON(2), 9, GFLAGS, &mclk_i2s3_8ch_sai_src_fracmux), + [MCLK_I2S3_8CH_SAI_SRC] = GATE(MCLK_I2S3_8CH_SAI_SRC, "mclk_i2s3_8ch_sai_src", "mclk_i2s3_8ch_sai_src_pre", 0, + RK3528_CLKGATE_CON(2), 10, GFLAGS), + [CLK_SPDIF_SRC] = COMPOSITE_NOMUX(CLK_SPDIF_SRC, "clk_spdif_src", "gpll", 0, + RK3528_CLKSEL_CON(30), 2, 5, DFLAGS, + RK3528_CLKGATE_CON(3), 4, GFLAGS), + [CLK_SPDIF_FRAC] = COMPOSITE_FRACMUX(CLK_SPDIF_FRAC, "clk_spdif_frac", "clk_spdif_src", RT_CLK_F_SET_RATE_PARENT, + RK3528_CLKSEL_CON(31), 0, + RK3528_CLKGATE_CON(3), 5, GFLAGS, &mclk_spdif_src_fracmux), + [MCLK_SPDIF_SRC] = GATE(MCLK_SPDIF_SRC, "mclk_spdif_src", "mclk_spdif_src_pre", 0, + RK3528_CLKGATE_CON(3), 6, GFLAGS), + /* bus */ + [ACLK_BUS_M_ROOT] = COMPOSITE_NODIV(ACLK_BUS_M_ROOT, "aclk_bus_m_root", mux_300m_200m_100m_24m_p, RT_CLK_F_IS_CRITICAL, + RK3528_CLKSEL_CON(43), 12, 2, MFLAGS, + RK3528_CLKGATE_CON(8), 7, GFLAGS), + [ACLK_GIC] = GATE(ACLK_GIC, "aclk_gic", "aclk_bus_m_root", RT_CLK_F_IS_CRITICAL, + RK3528_CLKGATE_CON(9), 1, GFLAGS), + [ACLK_BUS_ROOT] = COMPOSITE_NODIV(ACLK_BUS_ROOT, "aclk_bus_root", mux_200m_100m_24m_p, RT_CLK_F_IS_CRITICAL, + RK3528_CLKSEL_CON(43), 6, 2, MFLAGS, + RK3528_CLKGATE_CON(8), 4, GFLAGS), + [ACLK_SPINLOCK] = GATE(ACLK_SPINLOCK, "aclk_spinlock", "aclk_bus_root", 0, + RK3528_CLKGATE_CON(9), 2, GFLAGS), + [ACLK_DMAC] = GATE(ACLK_DMAC, "aclk_dmac", "aclk_bus_root", 0, + RK3528_CLKGATE_CON(9), 4, GFLAGS), + [ACLK_DCF] = GATE(ACLK_DCF, "aclk_dcf", "aclk_bus_root", 0, + RK3528_CLKGATE_CON(11), 11, GFLAGS), + [ACLK_BUS_VOPGL_ROOT] = COMPOSITE(ACLK_BUS_VOPGL_ROOT, "aclk_bus_vopgl_root", mux_gpll_cpll_p, RT_CLK_F_IS_CRITICAL, + RK3528_CLKSEL_CON(43), 3, 1, MFLAGS, 0, 3, DFLAGS, + RK3528_CLKGATE_CON(8), 0, GFLAGS), + [ACLK_BUS_H_ROOT] = COMPOSITE_NODIV(ACLK_BUS_H_ROOT, "aclk_bus_h_root", mux_500m_200m_100m_24m_p, RT_CLK_F_IS_CRITICAL, + RK3528_CLKSEL_CON(43), 4, 2, MFLAGS, + RK3528_CLKGATE_CON(8), 2, GFLAGS), + [ACLK_DMA2DDR] = GATE(ACLK_DMA2DDR, "aclk_dma2ddr", "aclk_bus_h_root", 0, + RK3528_CLKGATE_CON(10), 14, GFLAGS), + [HCLK_BUS_ROOT] = COMPOSITE_NODIV(HCLK_BUS_ROOT, "hclk_bus_root", mux_200m_100m_50m_24m_p, RT_CLK_F_IS_CRITICAL, + RK3528_CLKSEL_CON(43), 8, 2, MFLAGS, + RK3528_CLKGATE_CON(8), 5, GFLAGS), + [PCLK_BUS_ROOT] = COMPOSITE_NODIV(PCLK_BUS_ROOT, "pclk_bus_root", mux_100m_50m_24m_p, RT_CLK_F_IS_CRITICAL, + RK3528_CLKSEL_CON(43), 10, 2, MFLAGS, + RK3528_CLKGATE_CON(8), 6, GFLAGS), + [PCLK_DFT2APB] = GATE(PCLK_DFT2APB, "pclk_dft2apb", "pclk_bus_root", 0, + RK3528_CLKGATE_CON(8), 13, GFLAGS), + [PCLK_BUS_GRF] = GATE(PCLK_BUS_GRF, "pclk_bus_grf", "pclk_bus_root", RT_CLK_F_IS_CRITICAL, + RK3528_CLKGATE_CON(8), 15, GFLAGS), + [PCLK_TIMER] = GATE(PCLK_TIMER, "pclk_timer", "pclk_bus_root", 0, + RK3528_CLKGATE_CON(9), 5, GFLAGS), + [PCLK_JDBCK_DAP] = GATE(PCLK_JDBCK_DAP, "pclk_jdbck_dap", "pclk_bus_root", 0, + RK3528_CLKGATE_CON(9), 12, GFLAGS), + [PCLK_WDT_NS] = GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_bus_root", 0, + RK3528_CLKGATE_CON(9), 15, GFLAGS), + [PCLK_UART0] = GATE(PCLK_UART0, "pclk_uart0", "pclk_bus_root", 0, + RK3528_CLKGATE_CON(10), 7, GFLAGS), + [PCLK_PWM0] = GATE(PCLK_PWM0, "pclk_pwm0", "pclk_bus_root", 0, + RK3528_CLKGATE_CON(11), 4, GFLAGS), + [PCLK_PWM1] = GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus_root", 0, + RK3528_CLKGATE_CON(11), 7, GFLAGS), + [PCLK_DMA2DDR] = GATE(PCLK_DMA2DDR, "pclk_dma2ddr", "pclk_bus_root", 0, + RK3528_CLKGATE_CON(10), 13, GFLAGS), + [PCLK_SCR] = GATE(PCLK_SCR, "pclk_scr", "pclk_bus_root", 0, + RK3528_CLKGATE_CON(11), 10, GFLAGS), + [PCLK_INTMUX] = GATE(PCLK_INTMUX, "pclk_intmux", "pclk_bus_root", RT_CLK_F_IGNORE_UNUSED, + RK3528_CLKGATE_CON(11), 12, GFLAGS), + [CLK_PWM0] = COMPOSITE_NODIV(CLK_PWM0, "clk_pwm0", mux_100m_50m_24m_p, 0, + RK3528_CLKSEL_CON(44), 6, 2, MFLAGS, + RK3528_CLKGATE_CON(11), 5, GFLAGS), + [CLK_PWM1] = COMPOSITE_NODIV(CLK_PWM1, "clk_pwm1", mux_100m_50m_24m_p, 0, + RK3528_CLKSEL_CON(44), 8, 2, MFLAGS, + RK3528_CLKGATE_CON(11), 8, GFLAGS), + [CLK_CAPTURE_PWM1] = GATE(CLK_CAPTURE_PWM1, "clk_capture_pwm1", "xin24m", 0, + RK3528_CLKGATE_CON(11), 9, GFLAGS), + [CLK_CAPTURE_PWM0] = GATE(CLK_CAPTURE_PWM0, "clk_capture_pwm0", "xin24m", 0, + RK3528_CLKGATE_CON(11), 6, GFLAGS), + [CLK_JDBCK_DAP] = GATE(CLK_JDBCK_DAP, "clk_jdbck_dap", "xin24m", 0, + RK3528_CLKGATE_CON(9), 13, GFLAGS), + [TCLK_WDT_NS] = GATE(TCLK_WDT_NS, "tclk_wdt_ns", "xin24m", 0, + RK3528_CLKGATE_CON(10), 0, GFLAGS), + [CLK_TIMER_ROOT] = GATE(CLK_TIMER_ROOT, "clk_timer_root", "xin24m", 0, + RK3528_CLKGATE_CON(8), 9, GFLAGS), + [CLK_TIMER0] = GATE(CLK_TIMER0, "clk_timer0", "clk_timer_root", 0, + RK3528_CLKGATE_CON(9), 6, GFLAGS), + [CLK_TIMER1] = GATE(CLK_TIMER1, "clk_timer1", "clk_timer_root", 0, + RK3528_CLKGATE_CON(9), 7, GFLAGS), + [CLK_TIMER2] = GATE(CLK_TIMER2, "clk_timer2", "clk_timer_root", 0, + RK3528_CLKGATE_CON(9), 8, GFLAGS), + [CLK_TIMER3] = GATE(CLK_TIMER3, "clk_timer3", "clk_timer_root", 0, + RK3528_CLKGATE_CON(9), 9, GFLAGS), + [CLK_TIMER4] = GATE(CLK_TIMER4, "clk_timer4", "clk_timer_root", 0, + RK3528_CLKGATE_CON(9), 10, GFLAGS), + [CLK_TIMER5] = GATE(CLK_TIMER5, "clk_timer5", "clk_timer_root", 0, + RK3528_CLKGATE_CON(9), 11, GFLAGS), + /* pmu */ + [HCLK_PMU_ROOT] = GATE(HCLK_PMU_ROOT, "hclk_pmu_root", "clk_100m_src", RT_CLK_F_IGNORE_UNUSED, + RK3528_PMU_CLKGATE_CON(0), 1, GFLAGS), + [PCLK_PMU_ROOT] = GATE(PCLK_PMU_ROOT, "pclk_pmu_root", "clk_100m_src", RT_CLK_F_IGNORE_UNUSED, + RK3528_PMU_CLKGATE_CON(0), 0, GFLAGS), + [FCLK_MCU] = GATE(FCLK_MCU, "fclk_mcu", "hclk_pmu_root", 0, + RK3528_PMU_CLKGATE_CON(0), 7, GFLAGS), + [HCLK_PMU_SRAM] = GATE(HCLK_PMU_SRAM, "hclk_pmu_sram", "hclk_pmu_root", RT_CLK_F_IS_CRITICAL, + RK3528_PMU_CLKGATE_CON(5), 4, GFLAGS), + [PCLK_I2C2] = GATE(PCLK_I2C2, "pclk_i2c2", "pclk_pmu_root", 0, + RK3528_PMU_CLKGATE_CON(0), 2, GFLAGS), + [PCLK_PMU_HP_TIMER] = GATE(PCLK_PMU_HP_TIMER, "pclk_pmu_hp_timer", "pclk_pmu_root", 0, + RK3528_PMU_CLKGATE_CON(1), 2, GFLAGS), + [PCLK_PMU_IOC] = GATE(PCLK_PMU_IOC, "pclk_pmu_ioc", "pclk_pmu_root", RT_CLK_F_IS_CRITICAL, + RK3528_PMU_CLKGATE_CON(1), 5, GFLAGS), + [PCLK_PMU_CRU] = GATE(PCLK_PMU_CRU, "pclk_pmu_cru", "pclk_pmu_root", RT_CLK_F_IS_CRITICAL, + RK3528_PMU_CLKGATE_CON(1), 6, GFLAGS), + [PCLK_PMU_GRF] = GATE(PCLK_PMU_GRF, "pclk_pmu_grf", "pclk_pmu_root", RT_CLK_F_IS_CRITICAL, + RK3528_PMU_CLKGATE_CON(1), 7, GFLAGS), + [PCLK_PMU_WDT] = GATE(PCLK_PMU_WDT, "pclk_pmu_wdt", "pclk_pmu_root", 0, + RK3528_PMU_CLKGATE_CON(1), 10, GFLAGS), + [PCLK_PMU] = GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_root", RT_CLK_F_IS_CRITICAL, + RK3528_PMU_CLKGATE_CON(0), 13, GFLAGS), + [PCLK_GPIO0] = GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pmu_root", 0, + RK3528_PMU_CLKGATE_CON(0), 14, GFLAGS), + [PCLK_OSCCHK] = GATE(PCLK_OSCCHK, "pclk_oscchk", "pclk_pmu_root", 0, + RK3528_PMU_CLKGATE_CON(0), 9, GFLAGS), + [PCLK_PMU_MAILBOX] = GATE(PCLK_PMU_MAILBOX, "pclk_pmu_mailbox", "pclk_pmu_root", 0, + RK3528_PMU_CLKGATE_CON(1), 12, GFLAGS), + [PCLK_SCRKEYGEN] = GATE(PCLK_SCRKEYGEN, "pclk_scrkeygen", "pclk_pmu_root", 0, + RK3528_PMU_CLKGATE_CON(1), 15, GFLAGS), + [PCLK_PVTM_PMU] = GATE(PCLK_PVTM_PMU, "pclk_pvtm_pmu", "pclk_pmu_root", 0, + RK3528_PMU_CLKGATE_CON(5), 1, GFLAGS), + [CLK_I2C2] = COMPOSITE_NODIV(CLK_I2C2, "clk_i2c2", clk_i2c2_p, 0, + RK3528_PMU_CLKSEL_CON(0), 0, 2, MFLAGS, + RK3528_PMU_CLKGATE_CON(0), 3, GFLAGS), + [CLK_REFOUT] = GATE(CLK_REFOUT, "clk_refout", "xin24m", 0, + RK3528_PMU_CLKGATE_CON(2), 4, GFLAGS), + [CLK_PVTM_PMU] = COMPOSITE_NOMUX(CLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", 0, + RK3528_PMU_CLKSEL_CON(5), 0, 5, DFLAGS, + RK3528_PMU_CLKGATE_CON(5), 0, GFLAGS), + [XIN_OSC0_DIV] = COMPOSITE_FRAC(XIN_OSC0_DIV, "xin_osc0_div", "xin24m", 0, + RK3528_PMU_CLKSEL_CON(1), 0, + RK3528_PMU_CLKGATE_CON(1), 0, GFLAGS), + /* clk_32k */ + [CLK_DEEPSLOW] = MUX(CLK_DEEPSLOW, "clk_32k", clk_32k_p, RT_CLK_F_IS_CRITICAL, + RK3528_PMU_CLKSEL_CON(2), 0, 1, MFLAGS), + [RTC_CLK_MCU] = GATE(RTC_CLK_MCU, "rtc_clk_mcu", "clk_32k", 0, + RK3528_PMU_CLKGATE_CON(0), 8, GFLAGS), + [CLK_DDR_FAIL_SAFE] = GATE(CLK_DDR_FAIL_SAFE, "clk_ddr_fail_safe", "xin24m", RT_CLK_F_IGNORE_UNUSED, + RK3528_PMU_CLKGATE_CON(1), 1, GFLAGS), + [DBCLK_GPIO0] = COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", mux_24m_32k_p, 0, + RK3528_PMU_CLKSEL_CON(0), 2, 1, MFLAGS, + RK3528_PMU_CLKGATE_CON(0), 15, GFLAGS), + [TCLK_PMU_WDT] = COMPOSITE_NODIV(TCLK_PMU_WDT, "tclk_pmu_wdt", mux_24m_32k_p, 0, + RK3528_PMU_CLKSEL_CON(2), 1, 1, MFLAGS, + RK3528_PMU_CLKGATE_CON(1), 11, GFLAGS), + /* core */ + [ACLK_M_CORE_BIU] = COMPOSITE_NOMUX(ACLK_M_CORE_BIU, "aclk_m_core", "armclk", RT_CLK_F_IS_CRITICAL, + RK3528_CLKSEL_CON(39), 11, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3528_CLKGATE_CON(5), 12, GFLAGS), + [PCLK_DBG] = COMPOSITE_NOMUX(PCLK_DBG, "pclk_dbg", "armclk", RT_CLK_F_IS_CRITICAL, + RK3528_CLKSEL_CON(40), 1, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3528_CLKGATE_CON(5), 13, GFLAGS), + [PCLK_CPU_ROOT] = GATE(PCLK_CPU_ROOT, "pclk_cpu_root", "pclk_dbg", RT_CLK_F_IS_CRITICAL, + RK3528_CLKGATE_CON(6), 1, GFLAGS), + [PCLK_CORE_GRF] = GATE(PCLK_CORE_GRF, "pclk_core_grf", "pclk_cpu_root", RT_CLK_F_IS_CRITICAL, + RK3528_CLKGATE_CON(6), 2, GFLAGS), + /* ddr */ + [CLK_DDRC_SRC] = GATE(CLK_DDRC_SRC, "clk_ddrc_src", "dpll", RT_CLK_F_IS_CRITICAL, + RK3528_DDRPHY_CLKGATE_CON(0), 0, GFLAGS), + [CLK_DDR_PHY] = GATE(CLK_DDR_PHY, "clk_ddr_phy", "dpll", RT_CLK_F_IS_CRITICAL, + RK3528_DDRPHY_CLKGATE_CON(0), 1, GFLAGS), + [PCLK_DDR_ROOT] = COMPOSITE_NODIV(PCLK_DDR_ROOT, "pclk_ddr_root", mux_100m_50m_24m_p, RT_CLK_F_IS_CRITICAL, + RK3528_CLKSEL_CON(90), 0, 2, MFLAGS, + RK3528_CLKGATE_CON(45), 0, GFLAGS), + [PCLK_DDRMON] = GATE(PCLK_DDRMON, "pclk_ddrmon", "pclk_ddr_root", RT_CLK_F_IGNORE_UNUSED, + RK3528_CLKGATE_CON(45), 3, GFLAGS), + [PCLK_DDR_HWLP] = GATE(PCLK_DDR_HWLP, "pclk_ddr_hwlp", "pclk_ddr_root", RT_CLK_F_IGNORE_UNUSED, + RK3528_CLKGATE_CON(45), 8, GFLAGS), + [CLK_TIMER_DDRMON] = GATE(CLK_TIMER_DDRMON, "clk_timer_ddrmon", "xin24m", RT_CLK_F_IGNORE_UNUSED, + RK3528_CLKGATE_CON(45), 4, GFLAGS), + [PCLK_DDRC] = GATE(PCLK_DDRC, "pclk_ddrc", "pclk_ddr_root", RT_CLK_F_IS_CRITICAL, + RK3528_CLKGATE_CON(45), 2, GFLAGS), + [PCLK_DDR_GRF] = GATE(PCLK_DDR_GRF, "pclk_ddr_grf", "pclk_ddr_root", RT_CLK_F_IS_CRITICAL, + RK3528_CLKGATE_CON(45), 6, GFLAGS), + [PCLK_DDRPHY] = GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_ddr_root", RT_CLK_F_IS_CRITICAL, + RK3528_CLKGATE_CON(45), 9, GFLAGS), + [ACLK_DDR_UPCTL] = GATE(ACLK_DDR_UPCTL, "aclk_ddr_upctl", "clk_ddrc_src", RT_CLK_F_IS_CRITICAL, + RK3528_CLKGATE_CON(45), 11, GFLAGS), + [CLK_DDR_UPCTL] = GATE(CLK_DDR_UPCTL, "clk_ddr_upctl", "clk_ddrc_src", RT_CLK_F_IS_CRITICAL, + RK3528_CLKGATE_CON(45), 12, GFLAGS), + [CLK_DDRMON] = GATE(CLK_DDRMON, "clk_ddrmon", "clk_ddrc_src", RT_CLK_F_IS_CRITICAL, + RK3528_CLKGATE_CON(45), 13, GFLAGS), + [ACLK_DDR_SCRAMBLE] = GATE(ACLK_DDR_SCRAMBLE, "aclk_ddr_scramble", "clk_ddrc_src", RT_CLK_F_IS_CRITICAL, + RK3528_CLKGATE_CON(45), 14, GFLAGS), + [ACLK_SPLIT] = GATE(ACLK_SPLIT, "aclk_split", "clk_ddrc_src", RT_CLK_F_IS_CRITICAL, + RK3528_CLKGATE_CON(45), 15, GFLAGS), + /* gpu */ + [ACLK_GPU_ROOT] = COMPOSITE_NODIV(ACLK_GPU_ROOT, "aclk_gpu_root", mux_500m_300m_100m_24m_p, RT_CLK_F_IS_CRITICAL, + RK3528_CLKSEL_CON(76), 0, 2, MFLAGS, + RK3528_CLKGATE_CON(34), 0, GFLAGS), + [ACLK_GPU] = COMPOSITE_NODIV(ACLK_GPU, "aclk_gpu", aclk_gpu_p, RT_CLK_F_SET_RATE_PARENT, + RK3528_CLKSEL_CON(76), 6, 1, MFLAGS, + RK3528_CLKGATE_CON(34), 7, GFLAGS), + [ACLK_GPU_MALI] = GATE(ACLK_GPU_MALI, "aclk_gpu_mali", "aclk_gpu", 0, + RK3528_CLKGATE_CON(34), 8, GFLAGS), + [PCLK_GPU_ROOT] = COMPOSITE_NODIV(PCLK_GPU_ROOT, "pclk_gpu_root", mux_100m_50m_24m_p, RT_CLK_F_IS_CRITICAL, + RK3528_CLKSEL_CON(76), 4, 2, MFLAGS, + RK3528_CLKGATE_CON(34), 2, GFLAGS), + /* rkvdec */ + [ACLK_RKVDEC_ROOT_NDFT] = COMPOSITE_NODIV(ACLK_RKVDEC_ROOT_NDFT, "aclk_rkvdec_root", mux_339m_200m_100m_24m_p, RT_CLK_F_IS_CRITICAL, + RK3528_CLKSEL_CON(88), 6, 2, MFLAGS, + RK3528_CLKGATE_CON(44), 3, GFLAGS), + [HCLK_RKVDEC_ROOT] = COMPOSITE_NODIV(HCLK_RKVDEC_ROOT, "hclk_rkvdec_root", mux_200m_100m_50m_24m_p, RT_CLK_F_IS_CRITICAL, + RK3528_CLKSEL_CON(88), 4, 2, MFLAGS, + RK3528_CLKGATE_CON(44), 2, GFLAGS), + [PCLK_DDRPHY_CRU] = GATE(PCLK_DDRPHY_CRU, "pclk_ddrphy_cru", "hclk_rkvdec_root", RT_CLK_F_IS_CRITICAL, + RK3528_CLKGATE_CON(44), 4, GFLAGS), + [HCLK_RKVDEC] = GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_root", 0, + RK3528_CLKGATE_CON(44), 9, GFLAGS), + [CLK_HEVC_CA_RKVDEC] = COMPOSITE_NODIV(CLK_HEVC_CA_RKVDEC, "clk_hevc_ca_rkvdec", mux_600m_300m_200m_24m_p, 0, + RK3528_CLKSEL_CON(88), 11, 2, MFLAGS, + RK3528_CLKGATE_CON(44), 11, GFLAGS), + [ACLK_RKVDEC_PVTMUX_ROOT] = MUX(ACLK_RKVDEC_PVTMUX_ROOT, "aclk_rkvdec_pvtmux_root", aclk_rkvdec_pvtmux_root_p, RT_CLK_F_IS_CRITICAL | RT_CLK_F_SET_RATE_PARENT, + RK3528_CLKSEL_CON(88), 13, 1, MFLAGS), + [ACLK_RKVDEC] = GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pvtmux_root", 0, + RK3528_CLKGATE_CON(44), 8, GFLAGS), + /* rkvenc */ + [ACLK_RKVENC_ROOT] = COMPOSITE_NODIV(ACLK_RKVENC_ROOT, "aclk_rkvenc_root", mux_300m_200m_100m_24m_p, RT_CLK_F_IS_CRITICAL, + RK3528_CLKSEL_CON(79), 2, 2, MFLAGS, + RK3528_CLKGATE_CON(36), 1, GFLAGS), + [ACLK_RKVENC] = GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_root", 0, + RK3528_CLKGATE_CON(36), 7, GFLAGS), + [PCLK_RKVENC_ROOT] = COMPOSITE_NODIV(PCLK_RKVENC_ROOT, "pclk_rkvenc_root", mux_100m_50m_24m_p, RT_CLK_F_IS_CRITICAL, + RK3528_CLKSEL_CON(79), 4, 2, MFLAGS, + RK3528_CLKGATE_CON(36), 2, GFLAGS), + [PCLK_RKVENC_IOC] = GATE(PCLK_RKVENC_IOC, "pclk_rkvenc_ioc", "pclk_rkvenc_root", RT_CLK_F_IS_CRITICAL, + RK3528_CLKGATE_CON(37), 10, GFLAGS), + [PCLK_RKVENC_GRF] = GATE(PCLK_RKVENC_GRF, "pclk_rkvenc_grf", "pclk_rkvenc_root", RT_CLK_F_IS_CRITICAL, + RK3528_CLKGATE_CON(38), 6, GFLAGS), + [PCLK_I2C1] = GATE(PCLK_I2C1, "pclk_i2c1", "pclk_rkvenc_root", 0, + RK3528_CLKGATE_CON(36), 11, GFLAGS), + [PCLK_I2C0] = GATE(PCLK_I2C0, "pclk_i2c0", "pclk_rkvenc_root", 0, + RK3528_CLKGATE_CON(36), 13, GFLAGS), + [PCLK_SPI0] = GATE(PCLK_SPI0, "pclk_spi0", "pclk_rkvenc_root", 0, + RK3528_CLKGATE_CON(37), 2, GFLAGS), + [PCLK_GPIO4] = GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_rkvenc_root", 0, + RK3528_CLKGATE_CON(37), 8, GFLAGS), + [PCLK_UART1] = GATE(PCLK_UART1, "pclk_uart1", "pclk_rkvenc_root", 0, + RK3528_CLKGATE_CON(38), 2, GFLAGS), + [PCLK_UART3] = GATE(PCLK_UART3, "pclk_uart3", "pclk_rkvenc_root", 0, + RK3528_CLKGATE_CON(38), 4, GFLAGS), + [PCLK_CAN0] = GATE(PCLK_CAN0, "pclk_can0", "pclk_rkvenc_root", 0, + RK3528_CLKGATE_CON(38), 7, GFLAGS), + [PCLK_CAN1] = GATE(PCLK_CAN1, "pclk_can1", "pclk_rkvenc_root", 0, + RK3528_CLKGATE_CON(38), 9, GFLAGS), + [MCLK_PDM] = COMPOSITE_NODIV(MCLK_PDM, "mclk_pdm", mux_150m_100m_24m_p, 0, + RK3528_CLKSEL_CON(80), 12, 2, MFLAGS, + RK3528_CLKGATE_CON(38), 1, GFLAGS), + [CLK_CAN0] = COMPOSITE(CLK_CAN0, "clk_can0", mux_gpll_cpll_p, 0, + RK3528_CLKSEL_CON(81), 6, 1, MFLAGS, 0, 6, DFLAGS, + RK3528_CLKGATE_CON(38), 8, GFLAGS), + [CLK_CAN1] = COMPOSITE(CLK_CAN1, "clk_can1", mux_gpll_cpll_p, 0, + RK3528_CLKSEL_CON(81), 13, 1, MFLAGS, 7, 6, DFLAGS, + RK3528_CLKGATE_CON(38), 10, GFLAGS), + [HCLK_RKVENC_ROOT] = COMPOSITE_NODIV(HCLK_RKVENC_ROOT, "hclk_rkvenc_root", mux_200m_100m_50m_24m_p, RT_CLK_F_IS_CRITICAL, + RK3528_CLKSEL_CON(79), 0, 2, MFLAGS, + RK3528_CLKGATE_CON(36), 0, GFLAGS), + [HCLK_SAI_I2S1] = GATE(HCLK_SAI_I2S1, "hclk_sai_i2s1", "hclk_rkvenc_root", 0, + RK3528_CLKGATE_CON(36), 9, GFLAGS), + [HCLK_SPDIF] = GATE(HCLK_SPDIF, "hclk_spdif", "hclk_rkvenc_root", 0, + RK3528_CLKGATE_CON(37), 14, GFLAGS), + [HCLK_PDM] = GATE(HCLK_PDM, "hclk_pdm", "hclk_rkvenc_root", 0, + RK3528_CLKGATE_CON(38), 0, GFLAGS), + [HCLK_RKVENC] = GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_rkvenc_root", 0, + RK3528_CLKGATE_CON(36), 6, GFLAGS), + [CLK_CORE_RKVENC] = COMPOSITE_NODIV(CLK_CORE_RKVENC, "clk_core_rkvenc", mux_300m_200m_100m_24m_p, 0, + RK3528_CLKSEL_CON(79), 6, 2, MFLAGS, + RK3528_CLKGATE_CON(36), 8, GFLAGS), + [CLK_I2C0] = COMPOSITE_NODIV(CLK_I2C0, "clk_i2c0", mux_200m_100m_50m_24m_p, 0, + RK3528_CLKSEL_CON(79), 11, 2, MFLAGS, + RK3528_CLKGATE_CON(36), 14, GFLAGS), + [CLK_I2C1] = COMPOSITE_NODIV(CLK_I2C1, "clk_i2c1", mux_200m_100m_50m_24m_p, 0, + RK3528_CLKSEL_CON(79), 9, 2, MFLAGS, + RK3528_CLKGATE_CON(36), 12, GFLAGS), + [CLK_SPI0] = COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", mux_200m_100m_50m_24m_p, 0, + RK3528_CLKSEL_CON(79), 13, 2, MFLAGS, + RK3528_CLKGATE_CON(37), 3, GFLAGS), + [MCLK_SAI_I2S1] = COMPOSITE_NODIV(MCLK_SAI_I2S1, "mclk_sai_i2s1", mclk_sai_i2s1_p, RT_CLK_F_SET_RATE_PARENT, + RK3528_CLKSEL_CON(79), 8, 1, MFLAGS, + RK3528_CLKGATE_CON(36), 10, GFLAGS), + [DBCLK_GPIO4] = GATE(DBCLK_GPIO4, "dbclk_gpio4", "xin24m", 0, + RK3528_CLKGATE_CON(37), 9, GFLAGS), + /* vo */ + [HCLK_VO_ROOT] = COMPOSITE_NODIV(HCLK_VO_ROOT, "hclk_vo_root", mux_150m_100m_24m_p, RT_CLK_F_IS_CRITICAL, + RK3528_CLKSEL_CON(83), 2, 2, MFLAGS, + RK3528_CLKGATE_CON(39), 1, GFLAGS), + [HCLK_VOP] = GATE(HCLK_VOP, "hclk_vop", "hclk_vo_root", 0, + RK3528_CLKGATE_CON(40), 2, GFLAGS), + [HCLK_USBHOST] = GATE(HCLK_USBHOST, "hclk_usbhost", "hclk_vo_root", 0, + RK3528_CLKGATE_CON(43), 3, GFLAGS), + [HCLK_JPEG_DECODER] = GATE(HCLK_JPEG_DECODER, "hclk_jpeg_decoder", "hclk_vo_root", 0, + RK3528_CLKGATE_CON(41), 7, GFLAGS), + [HCLK_VDPP] = GATE(HCLK_VDPP, "hclk_vdpp", "hclk_vo_root", 0, + RK3528_CLKGATE_CON(39), 10, GFLAGS), + [HCLK_CVBS] = GATE(HCLK_CVBS, "hclk_cvbs", "hclk_vo_root", 0, + RK3528_CLKGATE_CON(41), 3, GFLAGS), + [HCLK_USBHOST_ARB] = GATE(HCLK_USBHOST_ARB, "hclk_usbhost_arb", "hclk_vo_root", 0, + RK3528_CLKGATE_CON(43), 4, GFLAGS), + [HCLK_SAI_I2S3] = GATE(HCLK_SAI_I2S3, "hclk_sai_i2s3", "hclk_vo_root", 0, + RK3528_CLKGATE_CON(42), 1, GFLAGS), + [HCLK_HDCP] = GATE(HCLK_HDCP, "hclk_hdcp", "hclk_vo_root", 0, + RK3528_CLKGATE_CON(41), 1, GFLAGS), + [HCLK_RGA2E] = GATE(HCLK_RGA2E, "hclk_rga2e", "hclk_vo_root", 0, + RK3528_CLKGATE_CON(39), 7, GFLAGS), + [HCLK_SDMMC0] = GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_vo_root", 0, + RK3528_CLKGATE_CON(42), 9, GFLAGS), + [HCLK_HDCP_KEY] = GATE(HCLK_HDCP_KEY, "hclk_hdcp_key", "hclk_vo_root", 0, + RK3528_CLKGATE_CON(40), 15, GFLAGS), + [ACLK_VO_L_ROOT] = COMPOSITE_NODIV(ACLK_VO_L_ROOT, "aclk_vo_l_root", mux_150m_100m_24m_p, RT_CLK_F_IS_CRITICAL, + RK3528_CLKSEL_CON(84), 1, 2, MFLAGS, + RK3528_CLKGATE_CON(41), 8, GFLAGS), + [ACLK_MAC_VO] = GATE(ACLK_MAC_VO, "aclk_gmac0", "aclk_vo_l_root", 0, + RK3528_CLKGATE_CON(41), 10, GFLAGS), + [PCLK_VO_ROOT] = COMPOSITE_NODIV(PCLK_VO_ROOT, "pclk_vo_root", mux_100m_50m_24m_p, RT_CLK_F_IS_CRITICAL, + RK3528_CLKSEL_CON(83), 4, 2, MFLAGS, + RK3528_CLKGATE_CON(39), 2, GFLAGS), + [PCLK_MAC_VO] = GATE(PCLK_MAC_VO, "pclk_gmac0", "pclk_vo_root", 0, + RK3528_CLKGATE_CON(41), 11, GFLAGS), + [PCLK_VCDCPHY] = GATE(PCLK_VCDCPHY, "pclk_vcdcphy", "pclk_vo_root", 0, + RK3528_CLKGATE_CON(42), 4, GFLAGS), + [PCLK_GPIO2] = GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_vo_root", 0, + RK3528_CLKGATE_CON(42), 5, GFLAGS), + [PCLK_VO_IOC] = GATE(PCLK_VO_IOC, "pclk_vo_ioc", "pclk_vo_root", RT_CLK_F_IS_CRITICAL, + RK3528_CLKGATE_CON(42), 7, GFLAGS), + [PCLK_OTPC_NS] = GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_vo_root", 0, + RK3528_CLKGATE_CON(42), 11, GFLAGS), + [PCLK_UART4] = GATE(PCLK_UART4, "pclk_uart4", "pclk_vo_root", 0, + RK3528_CLKGATE_CON(43), 7, GFLAGS), + [PCLK_I2C4] = GATE(PCLK_I2C4, "pclk_i2c4", "pclk_vo_root", 0, + RK3528_CLKGATE_CON(43), 9, GFLAGS), + [PCLK_I2C7] = GATE(PCLK_I2C7, "pclk_i2c7", "pclk_vo_root", 0, + RK3528_CLKGATE_CON(43), 11, GFLAGS), + [PCLK_USBPHY] = GATE(PCLK_USBPHY, "pclk_usbphy", "pclk_vo_root", 0, + RK3528_CLKGATE_CON(43), 13, GFLAGS), + [PCLK_VO_GRF] = GATE(PCLK_VO_GRF, "pclk_vo_grf", "pclk_vo_root", RT_CLK_F_IS_CRITICAL, + RK3528_CLKGATE_CON(39), 13, GFLAGS), + [PCLK_CRU] = GATE(PCLK_CRU, "pclk_cru", "pclk_vo_root", RT_CLK_F_IS_CRITICAL, + RK3528_CLKGATE_CON(39), 15, GFLAGS), + [PCLK_HDMI] = GATE(PCLK_HDMI, "pclk_hdmi", "pclk_vo_root", 0, + RK3528_CLKGATE_CON(40), 6, GFLAGS), + [PCLK_HDMIPHY] = GATE(PCLK_HDMIPHY, "pclk_hdmiphy", "pclk_vo_root", 0, + RK3528_CLKGATE_CON(40), 14, GFLAGS), + [PCLK_HDCP] = GATE(PCLK_HDCP, "pclk_hdcp", "pclk_vo_root", 0, + RK3528_CLKGATE_CON(41), 2, GFLAGS), + [CLK_CORE_VDPP] = COMPOSITE_NODIV(CLK_CORE_VDPP, "clk_core_vdpp", mux_339m_200m_100m_24m_p, 0, + RK3528_CLKSEL_CON(83), 10, 2, MFLAGS, + RK3528_CLKGATE_CON(39), 12, GFLAGS), + [CLK_CORE_RGA2E] = COMPOSITE_NODIV(CLK_CORE_RGA2E, "clk_core_rga2e", mux_339m_200m_100m_24m_p, 0, + RK3528_CLKSEL_CON(83), 8, 2, MFLAGS, + RK3528_CLKGATE_CON(39), 9, GFLAGS), + [ACLK_JPEG_ROOT] = COMPOSITE_NODIV(ACLK_JPEG_ROOT, "aclk_jpeg_root", mux_339m_200m_100m_24m_p, RT_CLK_F_IS_CRITICAL, + RK3528_CLKSEL_CON(84), 9, 2, MFLAGS, + RK3528_CLKGATE_CON(41), 15, GFLAGS), + [ACLK_JPEG_DECODER] = GATE(ACLK_JPEG_DECODER, "aclk_jpeg_decoder", "aclk_jpeg_root", 0, + RK3528_CLKGATE_CON(41), 6, GFLAGS), + [ACLK_VO_ROOT] = COMPOSITE_NODIV(ACLK_VO_ROOT, "aclk_vo_root", mux_339m_200m_100m_24m_p, RT_CLK_F_IS_CRITICAL, + RK3528_CLKSEL_CON(83), 0, 2, MFLAGS, + RK3528_CLKGATE_CON(39), 0, GFLAGS), + [ACLK_RGA2E] = GATE_NO_SET_RATE(ACLK_RGA2E, "aclk_rga2e", "aclk_vo_root", 0, + RK3528_CLKGATE_CON(39), 8, GFLAGS), + [ACLK_VDPP] = GATE_NO_SET_RATE(ACLK_VDPP, "aclk_vdpp", "aclk_vo_root", 0, + RK3528_CLKGATE_CON(39), 11, GFLAGS), + [ACLK_HDCP] = GATE_NO_SET_RATE(ACLK_HDCP, "aclk_hdcp", "aclk_vo_root", 0, + RK3528_CLKGATE_CON(41), 0, GFLAGS), + [CCLK_SRC_SDMMC0] = COMPOSITE(CCLK_SRC_SDMMC0, "cclk_src_sdmmc0", mux_gpll_cpll_xin24m_p, 0, + RK3528_CLKSEL_CON(85), 6, 2, MFLAGS, 0, 6, DFLAGS, + RK3528_CLKGATE_CON(42), 8, GFLAGS), + [ACLK_VOP_ROOT] = COMPOSITE(ACLK_VOP_ROOT, "aclk_vop_root", mux_gpll_cpll_p, RT_CLK_F_IS_CRITICAL, + RK3528_CLKSEL_CON(83), 15, 1, MFLAGS, 12, 3, DFLAGS, + RK3528_CLKGATE_CON(40), 0, GFLAGS), + [ACLK_VOP] = GATE(ACLK_VOP, "aclk_vop", "aclk_vop_root", 0, + RK3528_CLKGATE_CON(40), 5, GFLAGS), + [CLK_I2C4] = COMPOSITE_NODIV(CLK_I2C4, "clk_i2c4", mux_200m_100m_50m_24m_p, 0, + RK3528_CLKSEL_CON(85), 13, 2, MFLAGS, + RK3528_CLKGATE_CON(43), 10, GFLAGS), + [CLK_I2C7] = COMPOSITE_NODIV(CLK_I2C7, "clk_i2c7", mux_200m_100m_50m_24m_p, 0, + RK3528_CLKSEL_CON(86), 0, 2, MFLAGS, + RK3528_CLKGATE_CON(43), 12, GFLAGS), + [DBCLK_GPIO2] = GATE(DBCLK_GPIO2, "dbclk_gpio2", "xin24m", 0, + RK3528_CLKGATE_CON(42), 6, GFLAGS), + [CLK_HDMIHDP0] = GATE(CLK_HDMIHDP0, "clk_hdmihdp0", "xin24m", 0, + RK3528_CLKGATE_CON(43), 2, GFLAGS), + [CLK_MACPHY] = GATE(CLK_MACPHY, "clk_macphy", "xin24m", 0, + RK3528_CLKGATE_CON(42), 3, GFLAGS), + [CLK_REF_USBPHY] = GATE(CLK_REF_USBPHY, "clk_ref_usbphy", "xin24m", 0, + RK3528_CLKGATE_CON(43), 14, GFLAGS), + [CLK_SBPI_OTPC_NS] = GATE(CLK_SBPI_OTPC_NS, "clk_sbpi_otpc_ns", "xin24m", 0, + RK3528_CLKGATE_CON(42), 12, GFLAGS), + [CLK_USER_OTPC_NS] = FACTOR(CLK_USER_OTPC_NS, "clk_user_otpc_ns", "clk_sbpi_otpc_ns", 0, 1, 2), + [MCLK_SAI_I2S3] = GATE(MCLK_SAI_I2S3, "mclk_sai_i2s3", "mclk_i2s3_8ch_sai_src", 0, + RK3528_CLKGATE_CON(42), 2, GFLAGS), + [DCLK_VOP0] = COMPOSITE_NODIV(DCLK_VOP0, "dclk_vop0", dclk_vop0_p, RT_CLK_F_SET_RATE_PARENT, + RK3528_CLKSEL_CON(84), 0, 1, MFLAGS, + RK3528_CLKGATE_CON(40), 3, GFLAGS), + [DCLK_VOP1] = GATE(DCLK_VOP1, "dclk_vop1", "dclk_vop_src1", RT_CLK_F_SET_RATE_PARENT, + RK3528_CLKGATE_CON(40), 4, GFLAGS), + [DCLK_CVBS] = FACTOR_GATE(DCLK_CVBS, "dclk_cvbs", "dclk_vop1", 0, 1, 4, + RK3528_CLKGATE_CON(41), 4, GFLAGS), + [DCLK_4X_CVBS] = GATE(DCLK_4X_CVBS, "dclk_4x_cvbs", "dclk_vop1", 0, + RK3528_CLKGATE_CON(41), 5, GFLAGS), + [CLK_SFR_HDMI] = FACTOR_GATE(CLK_SFR_HDMI, "clk_sfr_hdmi", "dclk_vop_src1", 0, 1, 4, + RK3528_CLKGATE_CON(40), 7, GFLAGS), + [CLK_SPDIF_HDMI] = GATE(CLK_SPDIF_HDMI, "clk_spdif_hdmi", "mclk_spdif_src", 0, + RK3528_CLKGATE_CON(40), 10, GFLAGS), + [MCLK_SPDIF] = GATE(MCLK_SPDIF, "mclk_spdif", "mclk_spdif_src", 0, + RK3528_CLKGATE_CON(37), 15, GFLAGS), + [CLK_CEC_HDMI] = GATE(CLK_CEC_HDMI, "clk_cec_hdmi", "clk_32k", 0, + RK3528_CLKGATE_CON(40), 8, GFLAGS), + /* vpu */ + [DBCLK_GPIO1] = GATE(DBCLK_GPIO1, "dbclk_gpio1", "xin24m", 0, + RK3528_CLKGATE_CON(26), 5, GFLAGS), + [DBCLK_GPIO3] = GATE(DBCLK_GPIO3, "dbclk_gpio3", "xin24m", 0, + RK3528_CLKGATE_CON(27), 1, GFLAGS), + [CLK_SUSPEND_USB3OTG] = GATE(CLK_SUSPEND_USB3OTG, "clk_suspend_usb3otg", "xin24m", 0, + RK3528_CLKGATE_CON(33), 4, GFLAGS), + [CLK_PCIE_AUX] = GATE(CLK_PCIE_AUX, "clk_pcie_aux", "xin24m", 0, + RK3528_CLKGATE_CON(30), 2, GFLAGS), + [TCLK_EMMC] = GATE(TCLK_EMMC, "tclk_emmc", "xin24m", 0, + RK3528_CLKGATE_CON(26), 3, GFLAGS), + [CLK_REF_USB3OTG] = GATE(CLK_REF_USB3OTG, "clk_ref_usb3otg", "xin24m", 0, + RK3528_CLKGATE_CON(33), 2, GFLAGS), + [CCLK_SRC_SDIO0] = COMPOSITE(CCLK_SRC_SDIO0, "cclk_src_sdio0", mux_gpll_cpll_xin24m_p, 0, + RK3528_CLKSEL_CON(72), 6, 2, MFLAGS, 0, 6, DFLAGS, + RK3528_CLKGATE_CON(32), 1, GFLAGS), + [PCLK_VPU_ROOT] = COMPOSITE_NODIV(PCLK_VPU_ROOT, "pclk_vpu_root", mux_100m_50m_24m_p, RT_CLK_F_IS_CRITICAL, + RK3528_CLKSEL_CON(61), 4, 2, MFLAGS, + RK3528_CLKGATE_CON(25), 5, GFLAGS), + [PCLK_VPU_GRF] = GATE(PCLK_VPU_GRF, "pclk_vpu_grf", "pclk_vpu_root", RT_CLK_F_IS_CRITICAL, + RK3528_CLKGATE_CON(25), 12, GFLAGS), + [PCLK_CRU_PCIE] = GATE(PCLK_CRU_PCIE, "pclk_cru_pcie", "pclk_vpu_root", RT_CLK_F_IS_CRITICAL, + RK3528_CLKGATE_CON(25), 11, GFLAGS), + [PCLK_UART6] = GATE(PCLK_UART6, "pclk_uart6", "pclk_vpu_root", 0, + RK3528_CLKGATE_CON(27), 11, GFLAGS), + [PCLK_CAN2] = GATE(PCLK_CAN2, "pclk_can2", "pclk_vpu_root", 0, + RK3528_CLKGATE_CON(32), 7, GFLAGS), + [PCLK_SPI1] = GATE(PCLK_SPI1, "pclk_spi1", "pclk_vpu_root", 0, + RK3528_CLKGATE_CON(27), 4, GFLAGS), + [PCLK_CAN3] = GATE(PCLK_CAN3, "pclk_can3", "pclk_vpu_root", 0, + RK3528_CLKGATE_CON(32), 9, GFLAGS), + [PCLK_GPIO3] = GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_vpu_root", 0, + RK3528_CLKGATE_CON(27), 0, GFLAGS), + [PCLK_GPIO1] = GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_vpu_root", 0, + RK3528_CLKGATE_CON(26), 4, GFLAGS), + [PCLK_SARADC] = GATE(PCLK_SARADC, "pclk_saradc", "pclk_vpu_root", 0, + RK3528_CLKGATE_CON(32), 11, GFLAGS), + [PCLK_ACODEC] = GATE(PCLK_ACODEC, "pclk_acodec", "pclk_vpu_root", 0, + RK3528_CLKGATE_CON(26), 13, GFLAGS), + [PCLK_UART7] = GATE(PCLK_UART7, "pclk_uart7", "pclk_vpu_root", 0, + RK3528_CLKGATE_CON(27), 13, GFLAGS), + [PCLK_UART5] = GATE(PCLK_UART5, "pclk_uart5", "pclk_vpu_root", 0, + RK3528_CLKGATE_CON(27), 9, GFLAGS), + [PCLK_TSADC] = GATE(PCLK_TSADC, "pclk_tsadc", "pclk_vpu_root", 0, + RK3528_CLKGATE_CON(32), 14, GFLAGS), + [PCLK_PCIE] = GATE(PCLK_PCIE, "pclk_pcie", "pclk_vpu_root", 0, + RK3528_CLKGATE_CON(30), 1, GFLAGS), + [PCLK_UART2] = GATE(PCLK_UART2, "pclk_uart2", "pclk_vpu_root", 0, + RK3528_CLKGATE_CON(27), 7, GFLAGS), + [PCLK_VPU_IOC] = GATE(PCLK_VPU_IOC, "pclk_vpu_ioc", "pclk_vpu_root", RT_CLK_F_IS_CRITICAL, + RK3528_CLKGATE_CON(26), 8, GFLAGS), + [PCLK_PIPE_GRF] = GATE(PCLK_PIPE_GRF, "pclk_pipe_grf", "pclk_vpu_root", RT_CLK_F_IS_CRITICAL, + RK3528_CLKGATE_CON(30), 7, GFLAGS), + [PCLK_I2C5] = GATE(PCLK_I2C5, "pclk_i2c5", "pclk_vpu_root", 0, + RK3528_CLKGATE_CON(28), 1, GFLAGS), + [PCLK_PCIE_PHY] = GATE(PCLK_PCIE_PHY, "pclk_pcie_phy", "pclk_vpu_root", 0, + RK3528_CLKGATE_CON(30), 6, GFLAGS), + [PCLK_I2C3] = GATE(PCLK_I2C3, "pclk_i2c3", "pclk_vpu_root", 0, + RK3528_CLKGATE_CON(27), 15, GFLAGS), + [PCLK_MAC_VPU] = GATE(PCLK_MAC_VPU, "pclk_gmac1", "pclk_vpu_root", RT_CLK_F_IS_CRITICAL, + RK3528_CLKGATE_CON(28), 6, GFLAGS), + [PCLK_I2C6] = GATE(PCLK_I2C6, "pclk_i2c6", "pclk_vpu_root", 0, + RK3528_CLKGATE_CON(28), 3, GFLAGS), + [ACLK_VPU_L_ROOT] = COMPOSITE_NODIV(ACLK_VPU_L_ROOT, "aclk_vpu_l_root", mux_200m_100m_24m_p, RT_CLK_F_IS_CRITICAL, + RK3528_CLKSEL_CON(60), 0, 2, MFLAGS, + RK3528_CLKGATE_CON(25), 0, GFLAGS), + [ACLK_EMMC] = GATE_NO_SET_RATE(ACLK_EMMC, "aclk_emmc", "aclk_vpu_l_root", 0, + RK3528_CLKGATE_CON(26), 1, GFLAGS), + [ACLK_MAC_VPU] = GATE_NO_SET_RATE(ACLK_MAC_VPU, "aclk_gmac1", "aclk_vpu_l_root", 0, + RK3528_CLKGATE_CON(28), 5, GFLAGS), + [ACLK_PCIE] = GATE_NO_SET_RATE(ACLK_PCIE, "aclk_pcie", "aclk_vpu_l_root", 0, + RK3528_CLKGATE_CON(30), 3, GFLAGS), + [ACLK_USB3OTG] = GATE_NO_SET_RATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_vpu_l_root", 0, + RK3528_CLKGATE_CON(33), 1, GFLAGS), + [HCLK_VPU_ROOT] = COMPOSITE_NODIV(HCLK_VPU_ROOT, "hclk_vpu_root", mux_200m_100m_50m_24m_p, RT_CLK_F_IS_CRITICAL, + RK3528_CLKSEL_CON(61), 2, 2, MFLAGS, + RK3528_CLKGATE_CON(25), 4, GFLAGS), + [HCLK_VPU] = GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_root", 0, + RK3528_CLKGATE_CON(25), 10, GFLAGS), + [HCLK_SFC] = GATE(HCLK_SFC, "hclk_sfc", "hclk_vpu_root", 0, + RK3528_CLKGATE_CON(25), 13, GFLAGS), + [HCLK_EMMC] = GATE(HCLK_EMMC, "hclk_emmc", "hclk_vpu_root", 0, + RK3528_CLKGATE_CON(26), 0, GFLAGS), + [HCLK_SAI_I2S0] = GATE(HCLK_SAI_I2S0, "hclk_sai_i2s0", "hclk_vpu_root", 0, + RK3528_CLKGATE_CON(26), 9, GFLAGS), + [HCLK_SAI_I2S2] = GATE(HCLK_SAI_I2S2, "hclk_sai_i2s2", "hclk_vpu_root", 0, + RK3528_CLKGATE_CON(26), 11, GFLAGS), + [HCLK_PCIE_SLV] = GATE(HCLK_PCIE_SLV, "hclk_pcie_slv", "hclk_vpu_root", 0, + RK3528_CLKGATE_CON(30), 4, GFLAGS), + [HCLK_PCIE_DBI] = GATE(HCLK_PCIE_DBI, "hclk_pcie_dbi", "hclk_vpu_root", 0, + RK3528_CLKGATE_CON(30), 5, GFLAGS), + [HCLK_SDIO0] = GATE(HCLK_SDIO0, "hclk_sdio0", "hclk_vpu_root", 0, + RK3528_CLKGATE_CON(32), 2, GFLAGS), + [HCLK_SDIO1] = GATE(HCLK_SDIO1, "hclk_sdio1", "hclk_vpu_root", 0, + RK3528_CLKGATE_CON(32), 4, GFLAGS), + [CLK_GMAC1_VPU_25M] = COMPOSITE_NOMUX(CLK_GMAC1_VPU_25M, "clk_gmac1_25m", "ppll", 0, + RK3528_CLKSEL_CON(60), 2, 8, DFLAGS, + RK3528_CLKGATE_CON(25), 1, GFLAGS), + [CLK_PPLL_125M_MATRIX] = COMPOSITE_NOMUX(CLK_PPLL_125M_MATRIX, "clk_ppll_125m_src", "ppll", 0, + RK3528_CLKSEL_CON(60), 10, 5, DFLAGS, + RK3528_CLKGATE_CON(25), 2, GFLAGS), + [CLK_CAN3] = COMPOSITE(CLK_CAN3, "clk_can3", mux_gpll_cpll_p, 0, + RK3528_CLKSEL_CON(73), 13, 1, MFLAGS, 7, 6, DFLAGS, + RK3528_CLKGATE_CON(32), 10, GFLAGS), + [CLK_I2C6] = COMPOSITE_NODIV(CLK_I2C6, "clk_i2c6", mux_200m_100m_50m_24m_p, 0, + RK3528_CLKSEL_CON(64), 0, 2, MFLAGS, + RK3528_CLKGATE_CON(28), 4, GFLAGS), + [SCLK_SFC] = COMPOSITE(SCLK_SFC, "sclk_sfc", mux_gpll_cpll_xin24m_p, 0, + RK3528_CLKSEL_CON(61), 12, 2, MFLAGS, 6, 6, DFLAGS, + RK3528_CLKGATE_CON(25), 14, GFLAGS), + [CCLK_SRC_EMMC] = COMPOSITE(CCLK_SRC_EMMC, "cclk_src_emmc", mux_gpll_cpll_xin24m_p, 0, + RK3528_CLKSEL_CON(62), 6, 2, MFLAGS, 0, 6, DFLAGS, + RK3528_CLKGATE_CON(25), 15, GFLAGS), + [ACLK_VPU_ROOT] = COMPOSITE_NODIV(ACLK_VPU_ROOT, "aclk_vpu_root", mux_300m_200m_100m_24m_p, RT_CLK_F_IS_CRITICAL, + RK3528_CLKSEL_CON(61), 0, 2, MFLAGS, + RK3528_CLKGATE_CON(25), 3, GFLAGS), + [ACLK_VPU] = GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_root", 0, + RK3528_CLKGATE_CON(25), 9, GFLAGS), + [CLK_SPI1] = COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_200m_100m_50m_24m_p, 0, + RK3528_CLKSEL_CON(63), 10, 2, MFLAGS, + RK3528_CLKGATE_CON(27), 5, GFLAGS), + [CCLK_SRC_SDIO1] = COMPOSITE(CCLK_SRC_SDIO1, "cclk_src_sdio1", mux_gpll_cpll_xin24m_p, 0, + RK3528_CLKSEL_CON(72), 14, 2, MFLAGS, 8, 6, DFLAGS, + RK3528_CLKGATE_CON(32), 3, GFLAGS), + [CLK_CAN2] = COMPOSITE(CLK_CAN2, "clk_can2", mux_gpll_cpll_p, 0, + RK3528_CLKSEL_CON(73), 6, 1, MFLAGS, 0, 6, DFLAGS, + RK3528_CLKGATE_CON(32), 8, GFLAGS), + [CLK_TSADC] = COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "xin24m", 0, + RK3528_CLKSEL_CON(74), 3, 5, DFLAGS, + RK3528_CLKGATE_CON(32), 15, GFLAGS), + [CLK_SARADC] = COMPOSITE_NOMUX(CLK_SARADC, "clk_saradc", "xin24m", 0, + RK3528_CLKSEL_CON(74), 0, 3, DFLAGS, + RK3528_CLKGATE_CON(32), 12, GFLAGS), + [CLK_TSADC_TSEN] = COMPOSITE_NOMUX(CLK_TSADC_TSEN, "clk_tsadc_tsen", "xin24m", 0, + RK3528_CLKSEL_CON(74), 8, 5, DFLAGS, + RK3528_CLKGATE_CON(33), 0, GFLAGS), + [BCLK_EMMC] = COMPOSITE_NODIV(BCLK_EMMC, "bclk_emmc", mux_200m_100m_50m_24m_p, 0, + RK3528_CLKSEL_CON(62), 8, 2, MFLAGS, + RK3528_CLKGATE_CON(26), 2, GFLAGS), + [MCLK_ACODEC_TX] = COMPOSITE_NOMUX(MCLK_ACODEC_TX, "mclk_acodec_tx", "mclk_i2s2_2ch_sai_src", 0, + RK3528_CLKSEL_CON(63), 0, 8, DFLAGS, + RK3528_CLKGATE_CON(26), 14, GFLAGS), + [CLK_I2C3] = COMPOSITE_NODIV(CLK_I2C3, "clk_i2c3", mux_200m_100m_50m_24m_p, 0, + RK3528_CLKSEL_CON(63), 12, 2, MFLAGS, + RK3528_CLKGATE_CON(28), 0, GFLAGS), + [CLK_I2C5] = COMPOSITE_NODIV(CLK_I2C5, "clk_i2c5", mux_200m_100m_50m_24m_p, 0, + RK3528_CLKSEL_CON(63), 14, 2, MFLAGS, + RK3528_CLKGATE_CON(28), 2, GFLAGS), + [MCLK_SAI_I2S0] = COMPOSITE_NODIV(MCLK_SAI_I2S0, "mclk_sai_i2s0", mclk_sai_i2s0_p, RT_CLK_F_SET_RATE_PARENT, + RK3528_CLKSEL_CON(62), 10, 1, MFLAGS, + RK3528_CLKGATE_CON(26), 10, GFLAGS), + [MCLK_SAI_I2S2] = GATE(MCLK_SAI_I2S2, "mclk_sai_i2s2", "mclk_i2s2_2ch_sai_src", 0, + RK3528_CLKGATE_CON(26), 12, GFLAGS), + /* pcie */ + [CLK_PPLL_100M_MATRIX] = COMPOSITE_NOMUX(CLK_PPLL_100M_MATRIX, "clk_ppll_100m_src", "ppll", RT_CLK_F_IS_CRITICAL, + RK3528_PCIE_CLKSEL_CON(1), 2, 5, DFLAGS, + RK3528_PCIE_CLKGATE_CON(0), 1, GFLAGS), + [CLK_PPLL_50M_MATRIX] = COMPOSITE_NOMUX(CLK_PPLL_50M_MATRIX, "clk_ppll_50m_src", "ppll", RT_CLK_F_IS_CRITICAL, + RK3528_PCIE_CLKSEL_CON(1), 7, 5, DFLAGS, + RK3528_PCIE_CLKGATE_CON(0), 2, GFLAGS), + [CLK_REF_PCIE_INNER_PHY] = MUX(CLK_REF_PCIE_INNER_PHY, "clk_ref_pcie_inner_phy", clk_ref_pcie_inner_phy_p, 0, + RK3528_PCIE_CLKSEL_CON(1), 13, 1, MFLAGS), + [CLK_REF_PCIE_100M_PHY] = FACTOR(CLK_REF_PCIE_100M_PHY, "clk_ref_pcie_100m_phy", "clk_ppll_100m_src", 0, 1, 1), + /* gmac */ + [CLK_GMAC1_RMII_VPU] = FACTOR(CLK_GMAC1_RMII_VPU, "clk_gmac1_50m", "clk_ppll_50m_src", 0, 1, 1), + [CLK_GMAC1_SRC_VPU] = FACTOR(CLK_GMAC1_SRC_VPU, "clk_gmac1_125m", "clk_ppll_125m_src", 0, 1, 1), + [CLK_GMAC0_SRC] = DIV(CLK_GMAC0_SRC, "clk_gmac0_src", "clk_gmac0_io_i", 0, + RK3528_CLKSEL_CON(84), 3, 6, DFLAGS), + [CLK_GMAC0_TX] = GATE(CLK_GMAC0_TX, "clk_gmac0_tx", "clk_gmac0_src", 0, + RK3528_CLKGATE_CON(41), 13, GFLAGS), + [CLK_GMAC0_RX] = GATE(CLK_GMAC0_RX, "clk_gmac0_rx", "clk_gmac0_src", 0, + RK3528_CLKGATE_CON(41), 14, GFLAGS), + [CLK_GMAC0_RMII_50M] = GATE(CLK_GMAC0_RMII_50M, "clk_gmac0_rmii_50m", "clk_gmac0_io_i", 0, + RK3528_CLKGATE_CON(41), 12, GFLAGS), + [CLK_SCRKEYGEN] = GATE(CLK_SCRKEYGEN, "clk_scrkeygen", "clk_pmupvtm_out", 0, + RK3528_PMU_CLKGATE_CON(2), 0, GFLAGS), + [CLK_PVTM_OSCCHK] = GATE(CLK_PVTM_OSCCHK, "clk_pvtm_oscchk", "clk_pmupvtm_out", 0, + RK3528_PMU_CLKGATE_CON(2), 1, GFLAGS), + + [CLK_UART0] = &rk3528_uart0_fracmux.cell, + [CLK_UART1] = &rk3528_uart1_fracmux.cell, + [CLK_UART2] = &rk3528_uart2_fracmux.cell, + [CLK_UART3] = &rk3528_uart3_fracmux.cell, + [CLK_UART4] = &rk3528_uart4_fracmux.cell, + [CLK_UART5] = &rk3528_uart5_fracmux.cell, + [CLK_UART6] = &rk3528_uart6_fracmux.cell, + [CLK_UART7] = &rk3528_uart7_fracmux.cell, + [MCLK_I2S0_2CH_SAI_SRC_PRE] = &mclk_i2s0_2ch_sai_src_fracmux.cell, + [MCLK_I2S1_8CH_SAI_SRC_PRE] = &mclk_i2s1_8ch_sai_src_fracmux.cell, + [MCLK_I2S2_2CH_SAI_SRC_PRE] = &mclk_i2s2_2ch_sai_src_fracmux.cell, + [MCLK_I2S3_8CH_SAI_SRC_PRE] = &mclk_i2s3_8ch_sai_src_fracmux.cell, + [MCLK_SDPDIF_SRC_PRE] = &mclk_spdif_src_fracmux.cell, + + [0] = FACTOR(0, "xin12m", "xin24m", 0, 1, 2), +}; + +static struct rt_clk_cell *rk3528_grfclk_cells[] = +{ + [SCLK_SDMMC_DRV] = MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "cclk_src_sdmmc0", RK3528_SDMMC_CON0, 1), + [SCLK_SDMMC_SAMPLE] = MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "cclk_src_sdmmc0", RK3528_SDMMC_CON1, 1), + [SCLK_SDIO0_DRV] = MMC(SCLK_SDIO0_DRV, "sdio0_drv", "cclk_src_sdio0", RK3528_SDIO0_CON0, 1), + [SCLK_SDIO0_SAMPLE] = MMC(SCLK_SDIO0_SAMPLE, "sdio0_sample", "cclk_src_sdio0", RK3528_SDIO0_CON1, 1), + [SCLK_SDIO1_DRV] = MMC(SCLK_SDIO1_DRV, "sdio1_drv", "cclk_src_sdio1", RK3528_SDIO1_CON0, 1), + [SCLK_SDIO1_SAMPLE] = MMC(SCLK_SDIO1_SAMPLE, "sdio1_sample", "cclk_src_sdio1", RK3528_SDIO1_CON1, 1), +}; + +static rt_err_t clk_rk3528_cru_init(struct clk_rk3528_cru *cru) +{ + cru->clk_parent.cells = rk3528_clk_cells; + cru->clk_parent.cells_nr = RT_ARRAY_SIZE(rk3528_clk_cells); + + return RT_EOK; +} + +static rt_err_t clk_rk3528_grfcru_init(struct clk_rk3528_cru *cru) +{ + cru->clk_parent.cells = rk3528_grfclk_cells; + cru->clk_parent.cells_nr = RT_ARRAY_SIZE(rk3528_grfclk_cells); + + return RT_EOK; +} + +static rt_err_t clk_rk3528_probe(struct rt_platform_device *pdev) +{ + rt_err_t err; + struct rt_device *dev = &pdev->parent; + struct clk_rk3528_cru *cru = rt_calloc(1, sizeof(*cru)); + rt_err_t (*init)(struct clk_rk3528_cru *cru) = (void *)pdev->id->data; + + if (!cru) + { + return -RT_ENOMEM; + } + + cru->provider.reg_base = rt_dm_dev_iomap(dev, 0); + + if (!cru->provider.reg_base) + { + err = -RT_EIO; + goto _fail; + } + + cru->provider.grf = rt_syscon_find_by_ofw_phandle(dev->ofw_node, "rockchip,grf"); + cru->provider.pmugrf = rt_syscon_find_by_ofw_phandle(dev->ofw_node, "rockchip,pmugrf"); + + cru->clk_parent.dev = dev; + + if ((err = init(cru))) + { + goto _fail; + } + + rockchip_clk_init(&cru->provider, cru->clk_parent.cells, cru->clk_parent.cells_nr); + + if ((err = rt_clk_register(&cru->clk_parent))) + { + goto _fail; + } + + rockchip_clk_setup(&cru->provider, cru->clk_parent.cells, cru->clk_parent.cells_nr); + + if (init == clk_rk3528_cru_init) + { + if ((err = rockchip_register_softrst(&cru->rstc_parent, dev->ofw_node, RT_NULL, + cru->provider.reg_base + RK3528_SOFTRST_CON(0), ROCKCHIP_SOFTRST_HIWORD_MASK))) + { + goto _clk_unregister; + } + + rockchip_register_restart_notifier(&cru->provider, RK3528_GLB_SRST_FST, RT_NULL); + } + + return RT_EOK; + +_clk_unregister: + rt_clk_unregister(&cru->clk_parent); + +_fail: + if (cru->provider.reg_base) + { + rt_iounmap(cru->provider.reg_base); + } + + rt_free(cru); + + return err; +} + +static const struct rt_ofw_node_id clk_rk3528_ofw_ids[] = +{ + { .compatible = "rockchip,rk3528-cru", .data = (void *)clk_rk3528_cru_init }, + { .compatible = "rockchip,rk3528-grf-cru", .data = (void *)clk_rk3528_grfcru_init }, + { /* sentinel */ } +}; + +static struct rt_platform_driver clk_rk3528_driver = +{ + .name = "clk-rk3528", + .ids = clk_rk3528_ofw_ids, + + .probe = clk_rk3528_probe, +}; + +static int clk_rk3528_register(void) +{ + rt_platform_driver_register(&clk_rk3528_driver); + + return 0; +} +INIT_SUBSYS_EXPORT(clk_rk3528_register); diff --git a/bsp/rockchip/dm/hwcrypto/hw-rng-rockchip.c b/bsp/rockchip/dm/hwcrypto/hw-rng-rockchip.c index 80c2b5dd8a5..ce672addb03 100755 --- a/bsp/rockchip/dm/hwcrypto/hw-rng-rockchip.c +++ b/bsp/rockchip/dm/hwcrypto/hw-rng-rockchip.c @@ -86,6 +86,25 @@ #define TRNG_v1_VERSION_CODE 0x46bc /* end of TRNG_V1 register define */ +/* start of RKRNG register define */ +#define RKRNG_CTRL 0x0010 +#define RKRNG_CTRL_INST_REQ RT_BIT(0) +#define RKRNG_CTRL_RESEED_REQ RT_BIT(1) +#define RKRNG_CTRL_TEST_REQ RT_BIT(2) +#define RKRNG_CTRL_SW_DRNG_REQ RT_BIT(3) +#define RKRNG_CTRL_SW_TRNG_REQ RT_BIT(4) + +#define RKRNG_STATE 0x0014 +#define RKRNG_STATE_INST_ACK RT_BIT(0) +#define RKRNG_STATE_RESEED_ACK RT_BIT(1) +#define RKRNG_STATE_TEST_ACK RT_BIT(2) +#define RKRNG_STATE_SW_DRNG_ACK RT_BIT(3) +#define RKRNG_STATE_SW_TRNG_ACK RT_BIT(4) + +/* DRNG_DATA_0 ~ DNG_DATA_7 */ +#define RKRNG_DRNG_DATA_0 0x0070 +#define RKRNG_DRNG_DATA_7 0x008C + struct rockchip_rng; struct rockchip_rng_soc_data @@ -319,6 +338,49 @@ static rt_uint32_t rockchip_trng_v1_read(struct rockchip_rng *rk_rng, void *buf, return res; } +static rt_err_t rkrng_init(struct rockchip_rng *rk_rng) +{ + rt_uint32_t reg; + + rockchip_rng_writel(rk_rng, HIWORD_UPDATE(0, 0xffff, 0), RKRNG_CTRL); + reg = rockchip_rng_readl(rk_rng, RKRNG_STATE); + rockchip_rng_writel(rk_rng, reg, RKRNG_STATE); + + return 0; +} + +static rt_uint32_t rkrng_read(struct rockchip_rng *rk_rng, void *buf, + rt_size_t max, rt_bool_t wait) +{ + rt_err_t err; + rt_uint32_t reg_ctrl = RKRNG_CTRL_SW_DRNG_REQ; + + rockchip_rng_writel(rk_rng, HIWORD_UPDATE(reg_ctrl, 0xffff, 0), RKRNG_CTRL); + + err = readl_poll_timeout(rk_rng->regs + RKRNG_STATE, reg_ctrl, + (reg_ctrl & RKRNG_STATE_SW_DRNG_ACK), + ROCKCHIP_POLL_PERIOD_US, + ROCKCHIP_POLL_TIMEOUT_US); + + if (err) + { + goto _exit; + } + + + rockchip_rng_writel(rk_rng, reg_ctrl, RKRNG_STATE); + + err = rt_min_t(rt_size_t, max, RK_MAX_RNG_BYTE); + + rockchip_rng_read_regs(rk_rng, RKRNG_DRNG_DATA_0, buf, err); + +_exit: + /* Close TRNG */ + rockchip_rng_writel(rk_rng, HIWORD_UPDATE(0, 0xffff, 0), RKRNG_CTRL); + + return err; +} + static rt_uint32_t rockchip_rng_read(struct rockchip_rng *rk_rng, void *buf, rt_size_t max, rt_bool_t wait) { @@ -546,11 +608,19 @@ static const struct rockchip_rng_soc_data rk_trng_v1_soc_data = .read = rockchip_trng_v1_read, }; +static const struct rockchip_rng_soc_data rkrng_soc_data = +{ + .default_offset = 0, + .init = rkrng_init, + .read = rkrng_read, +}; + static const struct rt_ofw_node_id rockchip_rng_ofw_ids[] = { { .compatible = "rockchip,cryptov1-rng", .data = &rk_crypto_v1_soc_data, }, { .compatible = "rockchip,cryptov2-rng", .data = &rk_crypto_v2_soc_data, }, { .compatible = "rockchip,trngv1", .data = &rk_trng_v1_soc_data, }, + { .compatible = "rockchip,rkrng", .data = &rkrng_soc_data, }, { /* sentinel */ } }; diff --git a/bsp/rockchip/dm/include/dt-bindings/clock/rk3528-cru.h b/bsp/rockchip/dm/include/dt-bindings/clock/rk3528-cru.h new file mode 100755 index 00000000000..129e65e7ced --- /dev/null +++ b/bsp/rockchip/dm/include/dt-bindings/clock/rk3528-cru.h @@ -0,0 +1,746 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __DT_BINDINGS_CLK_ROCKCHIP_RK3528_H__ +#define __DT_BINDINGS_CLK_ROCKCHIP_RK3528_H__ + +/* cru-clocks indices */ + +/* core clocks */ +#define PLL_APLL 1 +#define PLL_CPLL 2 +#define PLL_GPLL 3 +#define PLL_PPLL 4 +#define PLL_DPLL 5 +#define ARMCLK 6 + +#define XIN_OSC0_HALF 8 +#define CLK_MATRIX_50M_SRC 9 +#define CLK_MATRIX_100M_SRC 10 +#define CLK_MATRIX_150M_SRC 11 +#define CLK_MATRIX_200M_SRC 12 +#define CLK_MATRIX_250M_SRC 13 +#define CLK_MATRIX_300M_SRC 14 +#define CLK_MATRIX_339M_SRC 15 +#define CLK_MATRIX_400M_SRC 16 +#define CLK_MATRIX_500M_SRC 17 +#define CLK_MATRIX_600M_SRC 18 +#define CLK_UART0_SRC 19 +#define CLK_UART0_FRAC 20 +#define SCLK_UART0 21 +#define CLK_UART1_SRC 22 +#define CLK_UART1_FRAC 23 +#define SCLK_UART1 24 +#define CLK_UART2_SRC 25 +#define CLK_UART2_FRAC 26 +#define SCLK_UART2 27 +#define CLK_UART3_SRC 28 +#define CLK_UART3_FRAC 29 +#define SCLK_UART3 30 +#define CLK_UART4_SRC 31 +#define CLK_UART4_FRAC 32 +#define SCLK_UART4 33 +#define CLK_UART5_SRC 34 +#define CLK_UART5_FRAC 35 +#define SCLK_UART5 36 +#define CLK_UART6_SRC 37 +#define CLK_UART6_FRAC 38 +#define SCLK_UART6 39 +#define CLK_UART7_SRC 40 +#define CLK_UART7_FRAC 41 +#define SCLK_UART7 42 +#define CLK_I2S0_2CH_SRC 43 +#define CLK_I2S0_2CH_FRAC 44 +#define MCLK_I2S0_2CH_SAI_SRC 45 +#define CLK_I2S3_8CH_SRC 46 +#define CLK_I2S3_8CH_FRAC 47 +#define MCLK_I2S3_8CH_SAI_SRC 48 +#define CLK_I2S1_8CH_SRC 49 +#define CLK_I2S1_8CH_FRAC 50 +#define MCLK_I2S1_8CH_SAI_SRC 51 +#define CLK_I2S2_2CH_SRC 52 +#define CLK_I2S2_2CH_FRAC 53 +#define MCLK_I2S2_2CH_SAI_SRC 54 +#define CLK_SPDIF_SRC 55 +#define CLK_SPDIF_FRAC 56 +#define MCLK_SPDIF_SRC 57 +#define DCLK_VOP_SRC0 58 +#define DCLK_VOP_SRC1 59 +#define CLK_HSM 60 +#define CLK_CORE_SRC_ACS 63 +#define CLK_CORE_SRC_PVTMUX 65 +#define CLK_CORE_SRC 66 +#define CLK_CORE 67 +#define ACLK_M_CORE_BIU 68 +#define CLK_CORE_PVTPLL_SRC 69 +#define PCLK_DBG 70 +#define SWCLKTCK 71 +#define CLK_SCANHS_CORE 72 +#define CLK_SCANHS_ACLKM_CORE 73 +#define CLK_SCANHS_PCLK_DBG 74 +#define CLK_SCANHS_PCLK_CPU_BIU 76 +#define PCLK_CPU_ROOT 77 +#define PCLK_CORE_GRF 78 +#define PCLK_DAPLITE_BIU 79 +#define PCLK_CPU_BIU 80 +#define CLK_REF_PVTPLL_CORE 81 +#define ACLK_BUS_VOPGL_ROOT 85 +#define ACLK_BUS_VOPGL_BIU 86 +#define ACLK_BUS_H_ROOT 87 +#define ACLK_BUS_H_BIU 88 +#define ACLK_BUS_ROOT 89 +#define HCLK_BUS_ROOT 90 +#define PCLK_BUS_ROOT 91 +#define ACLK_BUS_M_ROOT 92 +#define ACLK_SYSMEM_BIU 93 +#define CLK_TIMER_ROOT 95 +#define ACLK_BUS_BIU 96 +#define HCLK_BUS_BIU 97 +#define PCLK_BUS_BIU 98 +#define PCLK_DFT2APB 99 +#define PCLK_BUS_GRF 100 +#define ACLK_BUS_M_BIU 101 +#define ACLK_GIC 102 +#define ACLK_SPINLOCK 103 +#define ACLK_DMAC 104 +#define PCLK_TIMER 105 +#define CLK_TIMER0 106 +#define CLK_TIMER1 107 +#define CLK_TIMER2 108 +#define CLK_TIMER3 109 +#define CLK_TIMER4 110 +#define CLK_TIMER5 111 +#define PCLK_JDBCK_DAP 112 +#define CLK_JDBCK_DAP 113 +#define PCLK_WDT_NS 114 +#define TCLK_WDT_NS 115 +#define HCLK_TRNG_NS 116 +#define PCLK_UART0 117 +#define PCLK_DMA2DDR 123 +#define ACLK_DMA2DDR 124 +#define PCLK_PWM0 126 +#define CLK_PWM0 127 +#define CLK_CAPTURE_PWM0 128 +#define PCLK_PWM1 129 +#define CLK_PWM1 130 +#define CLK_CAPTURE_PWM1 131 +#define PCLK_SCR 134 +#define ACLK_DCF 135 +#define PCLK_INTMUX 138 +#define CLK_PPLL_I 141 +#define CLK_PPLL_MUX 142 +#define CLK_PPLL_100M_MATRIX 143 +#define CLK_PPLL_50M_MATRIX 144 +#define CLK_REF_PCIE_INNER_PHY 145 +#define CLK_REF_PCIE_100M_PHY 146 +#define ACLK_VPU_L_ROOT 147 +#define CLK_GMAC1_VPU_25M 148 +#define CLK_PPLL_125M_MATRIX 149 +#define ACLK_VPU_ROOT 150 +#define HCLK_VPU_ROOT 151 +#define PCLK_VPU_ROOT 152 +#define ACLK_VPU_BIU 153 +#define HCLK_VPU_BIU 154 +#define PCLK_VPU_BIU 155 +#define ACLK_VPU 156 +#define HCLK_VPU 157 +#define PCLK_CRU_PCIE 158 +#define PCLK_VPU_GRF 159 +#define HCLK_SFC 160 +#define SCLK_SFC 161 +#define CCLK_SRC_EMMC 163 +#define HCLK_EMMC 164 +#define ACLK_EMMC 165 +#define BCLK_EMMC 166 +#define TCLK_EMMC 167 +#define PCLK_GPIO1 168 +#define DBCLK_GPIO1 169 +#define ACLK_VPU_L_BIU 172 +#define PCLK_VPU_IOC 173 +#define HCLK_SAI_I2S0 174 +#define MCLK_SAI_I2S0 175 +#define HCLK_SAI_I2S2 176 +#define MCLK_SAI_I2S2 177 +#define PCLK_ACODEC 178 +#define MCLK_ACODEC_TX 179 +#define PCLK_GPIO3 186 +#define DBCLK_GPIO3 187 +#define PCLK_SPI1 189 +#define CLK_SPI1 190 +#define SCLK_IN_SPI1 191 +#define PCLK_UART2 192 +#define PCLK_UART5 194 +#define PCLK_UART6 196 +#define PCLK_UART7 198 +#define PCLK_I2C3 200 +#define CLK_I2C3 201 +#define PCLK_I2C5 202 +#define CLK_I2C5 203 +#define PCLK_I2C6 204 +#define CLK_I2C6 205 +#define ACLK_MAC_VPU 206 +#define PCLK_MAC_VPU 207 +#define CLK_GMAC1_RMII_VPU 209 +#define CLK_GMAC1_SRC_VPU 210 +#define PCLK_PCIE 215 +#define CLK_PCIE_AUX 216 +#define ACLK_PCIE 217 +#define HCLK_PCIE_SLV 218 +#define HCLK_PCIE_DBI 219 +#define PCLK_PCIE_PHY 220 +#define PCLK_PIPE_GRF 221 +#define CLK_PIPE_USB3OTG_COMBO 230 +#define CLK_UTMI_USB3OTG 232 +#define CLK_PCIE_PIPE_PHY 235 +#define CCLK_SRC_SDIO0 240 +#define HCLK_SDIO0 241 +#define CCLK_SRC_SDIO1 244 +#define HCLK_SDIO1 245 +#define CLK_TS_0 246 +#define CLK_TS_1 247 +#define PCLK_CAN2 250 +#define CLK_CAN2 251 +#define PCLK_CAN3 252 +#define CLK_CAN3 253 +#define PCLK_SARADC 256 +#define CLK_SARADC 257 +#define PCLK_TSADC 258 +#define CLK_TSADC 259 +#define CLK_TSADC_TSEN 260 +#define ACLK_USB3OTG 261 +#define CLK_REF_USB3OTG 262 +#define CLK_SUSPEND_USB3OTG 263 +#define ACLK_GPU_ROOT 269 +#define PCLK_GPU_ROOT 270 +#define ACLK_GPU_BIU 271 +#define PCLK_GPU_BIU 272 +#define ACLK_GPU 273 +#define CLK_GPU_PVTPLL_SRC 274 +#define ACLK_GPU_MALI 275 +#define HCLK_RKVENC_ROOT 281 +#define ACLK_RKVENC_ROOT 282 +#define PCLK_RKVENC_ROOT 283 +#define HCLK_RKVENC_BIU 284 +#define ACLK_RKVENC_BIU 285 +#define PCLK_RKVENC_BIU 286 +#define HCLK_RKVENC 287 +#define ACLK_RKVENC 288 +#define CLK_CORE_RKVENC 289 +#define HCLK_SAI_I2S1 290 +#define MCLK_SAI_I2S1 291 +#define PCLK_I2C1 292 +#define CLK_I2C1 293 +#define PCLK_I2C0 294 +#define CLK_I2C0 295 +#define CLK_UART_JTAG 296 +#define PCLK_SPI0 297 +#define CLK_SPI0 298 +#define SCLK_IN_SPI0 299 +#define PCLK_GPIO4 300 +#define DBCLK_GPIO4 301 +#define PCLK_RKVENC_IOC 302 +#define HCLK_SPDIF 308 +#define MCLK_SPDIF 309 +#define HCLK_PDM 310 +#define MCLK_PDM 311 +#define PCLK_UART1 315 +#define PCLK_UART3 317 +#define PCLK_RKVENC_GRF 319 +#define PCLK_CAN0 320 +#define CLK_CAN0 321 +#define PCLK_CAN1 322 +#define CLK_CAN1 323 +#define ACLK_VO_ROOT 324 +#define HCLK_VO_ROOT 325 +#define PCLK_VO_ROOT 326 +#define ACLK_VO_BIU 327 +#define HCLK_VO_BIU 328 +#define PCLK_VO_BIU 329 +#define HCLK_RGA2E 330 +#define ACLK_RGA2E 331 +#define CLK_CORE_RGA2E 332 +#define HCLK_VDPP 333 +#define ACLK_VDPP 334 +#define CLK_CORE_VDPP 335 +#define PCLK_VO_GRF 336 +#define PCLK_CRU 337 +#define ACLK_VOP_ROOT 338 +#define ACLK_VOP_BIU 339 +#define HCLK_VOP 340 +#define DCLK_VOP0 341 +#define DCLK_VOP1 342 +#define ACLK_VOP 343 +#define PCLK_HDMI 344 +#define CLK_SFR_HDMI 345 +#define CLK_CEC_HDMI 346 +#define CLK_SPDIF_HDMI 347 +#define CLK_HDMIPHY_TMDSSRC 348 +#define CLK_HDMIPHY_PREP 349 +#define PCLK_HDMIPHY 352 +#define HCLK_HDCP_KEY 354 +#define ACLK_HDCP 355 +#define HCLK_HDCP 356 +#define PCLK_HDCP 357 +#define HCLK_CVBS 358 +#define DCLK_CVBS 359 +#define DCLK_4X_CVBS 360 +#define ACLK_JPEG_DECODER 361 +#define HCLK_JPEG_DECODER 362 +#define ACLK_VO_L_ROOT 375 +#define ACLK_VO_L_BIU 376 +#define ACLK_MAC_VO 377 +#define PCLK_MAC_VO 378 +#define CLK_GMAC0_SRC 379 +#define CLK_GMAC0_RMII_50M 380 +#define CLK_GMAC0_TX 381 +#define CLK_GMAC0_RX 382 +#define ACLK_JPEG_ROOT 385 +#define ACLK_JPEG_BIU 386 +#define HCLK_SAI_I2S3 387 +#define MCLK_SAI_I2S3 388 +#define CLK_MACPHY 398 +#define PCLK_VCDCPHY 399 +#define PCLK_GPIO2 404 +#define DBCLK_GPIO2 405 +#define PCLK_VO_IOC 406 +#define CCLK_SRC_SDMMC0 407 +#define HCLK_SDMMC0 408 +#define PCLK_OTPC_NS 411 +#define CLK_SBPI_OTPC_NS 412 +#define CLK_USER_OTPC_NS 413 +#define CLK_HDMIHDP0 415 +#define HCLK_USBHOST 416 +#define HCLK_USBHOST_ARB 417 +#define CLK_USBHOST_OHCI 418 +#define CLK_USBHOST_UTMI 419 +#define PCLK_UART4 420 +#define PCLK_I2C4 422 +#define CLK_I2C4 423 +#define PCLK_I2C7 424 +#define CLK_I2C7 425 +#define PCLK_USBPHY 426 +#define CLK_REF_USBPHY 427 +#define HCLK_RKVDEC_ROOT 433 +#define ACLK_RKVDEC_ROOT_NDFT 434 +#define PCLK_DDRPHY_CRU 435 +#define HCLK_RKVDEC_BIU 436 +#define ACLK_RKVDEC_BIU 437 +#define ACLK_RKVDEC 439 +#define HCLK_RKVDEC 440 +#define CLK_HEVC_CA_RKVDEC 441 +#define ACLK_RKVDEC_PVTMUX_ROOT 442 +#define CLK_RKVDEC_PVTPLL_SRC 443 +#define PCLK_DDR_ROOT 449 +#define PCLK_DDR_BIU 450 +#define PCLK_DDRC 451 +#define PCLK_DDRMON 452 +#define CLK_TIMER_DDRMON 453 +#define PCLK_MSCH_BIU 454 +#define PCLK_DDR_GRF 455 +#define PCLK_DDR_HWLP 456 +#define PCLK_DDRPHY 457 +#define CLK_MSCH_BIU 463 +#define ACLK_DDR_UPCTL 464 +#define CLK_DDR_UPCTL 465 +#define CLK_DDRMON 466 +#define ACLK_DDR_SCRAMBLE 467 +#define ACLK_SPLIT 468 +#define CLK_DDRC_SRC 470 +#define CLK_DDR_PHY 471 +#define PCLK_OTPC_S 472 +#define CLK_SBPI_OTPC_S 473 +#define CLK_USER_OTPC_S 474 +#define PCLK_KEYREADER 475 +#define PCLK_BUS_SGRF 476 +#define PCLK_STIMER 477 +#define CLK_STIMER0 478 +#define CLK_STIMER1 479 +#define PCLK_WDT_S 480 +#define TCLK_WDT_S 481 +#define HCLK_TRNG_S 482 +#define HCLK_BOOTROM 486 +#define PCLK_DCF 487 +#define ACLK_SYSMEM 488 +#define HCLK_TSP 489 +#define ACLK_TSP 490 +#define CLK_CORE_TSP 491 +#define CLK_OTPC_ARB 492 +#define PCLK_OTP_MASK 493 +#define CLK_PMC_OTP 494 +#define PCLK_PMU_ROOT 495 +#define HCLK_PMU_ROOT 496 +#define PCLK_I2C2 497 +#define CLK_I2C2 498 +#define HCLK_PMU_BIU 500 +#define PCLK_PMU_BIU 501 +#define FCLK_MCU 502 +#define RTC_CLK_MCU 504 +#define PCLK_OSCCHK 505 +#define CLK_PMU_MCU_JTAG 506 +#define PCLK_PMU 508 +#define PCLK_GPIO0 509 +#define DBCLK_GPIO0 510 +#define XIN_OSC0_DIV 511 +#define CLK_DEEPSLOW 512 +#define CLK_DDR_FAIL_SAFE 513 +#define PCLK_PMU_HP_TIMER 514 +#define CLK_PMU_HP_TIMER 515 +#define CLK_PMU_32K_HP_TIMER 516 +#define PCLK_PMU_IOC 517 +#define PCLK_PMU_CRU 518 +#define PCLK_PMU_GRF 519 +#define PCLK_PMU_WDT 520 +#define TCLK_PMU_WDT 521 +#define PCLK_PMU_MAILBOX 522 +#define PCLK_SCRKEYGEN 524 +#define CLK_SCRKEYGEN 525 +#define CLK_PVTM_OSCCHK 526 +#define CLK_REFOUT 530 +#define CLK_PVTM_PMU 532 +#define PCLK_PVTM_PMU 533 +#define PCLK_PMU_SGRF 534 +#define HCLK_PMU_SRAM 535 +#define CLK_UART0 536 +#define CLK_UART1 537 +#define CLK_UART2 538 +#define CLK_UART3 539 +#define CLK_UART4 540 +#define CLK_UART5 541 +#define CLK_UART6 542 +#define CLK_UART7 543 +#define MCLK_I2S0_2CH_SAI_SRC_PRE 544 +#define MCLK_I2S1_8CH_SAI_SRC_PRE 545 +#define MCLK_I2S2_2CH_SAI_SRC_PRE 546 +#define MCLK_I2S3_8CH_SAI_SRC_PRE 547 +#define MCLK_SDPDIF_SRC_PRE 548 +#define CLK_NR_CLKS (MCLK_SDPDIF_SRC_PRE + 1) + +/* grf-clocks indices */ +#define SCLK_SDMMC_DRV 1 +#define SCLK_SDMMC_SAMPLE 2 +#define SCLK_SDIO0_DRV 3 +#define SCLK_SDIO0_SAMPLE 4 +#define SCLK_SDIO1_DRV 5 +#define SCLK_SDIO1_SAMPLE 6 +#define CLK_NR_GRF_CLKS (SCLK_SDIO1_SAMPLE + 1) + +/* scmi-clocks indices */ +#define SCMI_PCLK_KEYREADER 0 +#define SCMI_HCLK_KLAD 1 +#define SCMI_PCLK_KLAD 2 +#define SCMI_HCLK_TRNG_S 3 +#define SCMI_HCLK_CRYPTO_S 4 +#define SCMI_PCLK_WDT_S 5 +#define SCMI_TCLK_WDT_S 6 +#define SCMI_PCLK_STIMER 7 +#define SCMI_CLK_STIMER0 8 +#define SCMI_CLK_STIMER1 9 +#define SCMI_PCLK_OTP_MASK 10 +#define SCMI_PCLK_OTPC_S 11 +#define SCMI_CLK_SBPI_OTPC_S 12 +#define SCMI_CLK_USER_OTPC_S 13 +#define SCMI_CLK_PMC_OTP 14 +#define SCMI_CLK_OTPC_ARB 15 +#define SCMI_CLK_CORE_TSP 16 +#define SCMI_ACLK_TSP 17 +#define SCMI_HCLK_TSP 18 +#define SCMI_PCLK_DCF 19 +#define SCMI_CLK_DDR 20 +#define SCMI_CLK_CPU 21 +#define SCMI_CLK_GPU 22 +#define SCMI_CORE_CRYPTO 23 +#define SCMI_ACLK_CRYPTO 24 +#define SCMI_PKA_CRYPTO 25 +#define SCMI_HCLK_CRYPTO 26 +#define SCMI_CORE_CRYPTO_S 27 +#define SCMI_ACLK_CRYPTO_S 28 +#define SCMI_PKA_CRYPTO_S 29 +#define SCMI_CORE_KLAD 30 +#define SCMI_ACLK_KLAD 31 +#define SCMI_HCLK_TRNG 32 + +/* CRU_SOFTRST_CON03 (Offset: 0xa0c) */ +#define SRST_NCOREPORESET0 0x00000030 +#define SRST_NCOREPORESET1 0x00000031 +#define SRST_NCOREPORESET2 0x00000032 +#define SRST_NCOREPORESET3 0x00000033 +#define SRST_NCORESET0 0x00000034 +#define SRST_NCORESET1 0x00000035 +#define SRST_NCORESET2 0x00000036 +#define SRST_NCORESET3 0x00000037 +#define SRST_NL2RESET 0x00000038 +#define SRST_ARESETN_M_CORE_BIU 0x00000039 +#define SRST_RESETN_CORE_CRYPTO 0x0000003a + +/* CRU_SOFTRST_CON05 (Offset: 0xa14) */ +#define SRST_PRESETN_DBG 0x0000005d +#define SRST_POTRESETN_DBG 0x0000005e +#define SRST_NTRESETN_DBG 0x0000005f + +/* CRU_SOFTRST_CON06 (Offset: 0xa18) */ +#define SRST_PRESETN_CORE_GRF 0x00000062 +#define SRST_PRESETN_DAPLITE_BIU 0x00000063 +#define SRST_PRESETN_CPU_BIU 0x00000064 +#define SRST_RESETN_REF_PVTPLL_CORE 0x00000067 + +/* CRU_SOFTRST_CON08 (Offset: 0xa20) */ +#define SRST_ARESETN_BUS_VOPGL_BIU 0x00000081 +#define SRST_ARESETN_BUS_H_BIU 0x00000083 +#define SRST_ARESETN_SYSMEM_BIU 0x00000088 +#define SRST_ARESETN_BUS_BIU 0x0000008a +#define SRST_HRESETN_BUS_BIU 0x0000008b +#define SRST_PRESETN_BUS_BIU 0x0000008c +#define SRST_PRESETN_DFT2APB 0x0000008d +#define SRST_PRESETN_BUS_GRF 0x0000008f + +/* CRU_SOFTRST_CON09 (Offset: 0xa24) */ +#define SRST_ARESETN_BUS_M_BIU 0x00000090 +#define SRST_ARESETN_GIC 0x00000091 +#define SRST_ARESETN_SPINLOCK 0x00000092 +#define SRST_ARESETN_DMAC 0x00000094 +#define SRST_PRESETN_TIMER 0x00000095 +#define SRST_RESETN_TIMER0 0x00000096 +#define SRST_RESETN_TIMER1 0x00000097 +#define SRST_RESETN_TIMER2 0x00000098 +#define SRST_RESETN_TIMER3 0x00000099 +#define SRST_RESETN_TIMER4 0x0000009a +#define SRST_RESETN_TIMER5 0x0000009b +#define SRST_PRESETN_JDBCK_DAP 0x0000009c +#define SRST_RESETN_JDBCK_DAP 0x0000009d +#define SRST_PRESETN_WDT_NS 0x0000009f + +/* CRU_SOFTRST_CON10 (Offset: 0xa28) */ +#define SRST_TRESETN_WDT_NS 0x000000a0 +#define SRST_HRESETN_TRNG_NS 0x000000a3 +#define SRST_PRESETN_UART0 0x000000a7 +#define SRST_SRESETN_UART0 0x000000a8 +#define SRST_RESETN_PKA_CRYPTO 0x000000aa +#define SRST_ARESETN_CRYPTO 0x000000ab +#define SRST_HRESETN_CRYPTO 0x000000ac +#define SRST_PRESETN_DMA2DDR 0x000000ad +#define SRST_ARESETN_DMA2DDR 0x000000ae + +/* CRU_SOFTRST_CON11 (Offset: 0xa2c) */ +#define SRST_PRESETN_PWM0 0x000000b4 +#define SRST_RESETN_PWM0 0x000000b5 +#define SRST_PRESETN_PWM1 0x000000b7 +#define SRST_RESETN_PWM1 0x000000b8 +#define SRST_PRESETN_SCR 0x000000ba +#define SRST_ARESETN_DCF 0x000000bb +#define SRST_PRESETN_INTMUX 0x000000bc + +/* CRU_SOFTRST_CON25 (Offset: 0xa64) */ +#define SRST_ARESETN_VPU_BIU 0x00000196 +#define SRST_HRESETN_VPU_BIU 0x00000197 +#define SRST_PRESETN_VPU_BIU 0x00000198 +#define SRST_ARESETN_VPU 0x00000199 +#define SRST_HRESETN_VPU 0x0000019a +#define SRST_PRESETN_CRU_PCIE 0x0000019b +#define SRST_PRESETN_VPU_GRF 0x0000019c +#define SRST_HRESETN_SFC 0x0000019d +#define SRST_SRESETN_SFC 0x0000019e +#define SRST_CRESETN_EMMC 0x0000019f + +/* CRU_SOFTRST_CON26 (Offset: 0xa68) */ +#define SRST_HRESETN_EMMC 0x000001a0 +#define SRST_ARESETN_EMMC 0x000001a1 +#define SRST_BRESETN_EMMC 0x000001a2 +#define SRST_TRESETN_EMMC 0x000001a3 +#define SRST_PRESETN_GPIO1 0x000001a4 +#define SRST_DBRESETN_GPIO1 0x000001a5 +#define SRST_ARESETN_VPU_L_BIU 0x000001a6 +#define SRST_PRESETN_VPU_IOC 0x000001a8 +#define SRST_HRESETN_SAI_I2S0 0x000001a9 +#define SRST_MRESETN_SAI_I2S0 0x000001aa +#define SRST_HRESETN_SAI_I2S2 0x000001ab +#define SRST_MRESETN_SAI_I2S2 0x000001ac +#define SRST_PRESETN_ACODEC 0x000001ad + +/* CRU_SOFTRST_CON27 (Offset: 0xa6c) */ +#define SRST_PRESETN_GPIO3 0x000001b0 +#define SRST_DBRESETN_GPIO3 0x000001b1 +#define SRST_PRESETN_SPI1 0x000001b4 +#define SRST_RESETN_SPI1 0x000001b5 +#define SRST_PRESETN_UART2 0x000001b7 +#define SRST_SRESETN_UART2 0x000001b8 +#define SRST_PRESETN_UART5 0x000001b9 +#define SRST_SRESETN_UART5 0x000001ba +#define SRST_PRESETN_UART6 0x000001bb +#define SRST_SRESETN_UART6 0x000001bc +#define SRST_PRESETN_UART7 0x000001bd +#define SRST_SRESETN_UART7 0x000001be +#define SRST_PRESETN_I2C3 0x000001bf + +/* CRU_SOFTRST_CON28 (Offset: 0xa70) */ +#define SRST_RESETN_I2C3 0x000001c0 +#define SRST_PRESETN_I2C5 0x000001c1 +#define SRST_RESETN_I2C5 0x000001c2 +#define SRST_PRESETN_I2C6 0x000001c3 +#define SRST_RESETN_I2C6 0x000001c4 +#define SRST_ARESETN_MAC 0x000001c5 + +/* CRU_SOFTRST_CON30 (Offset: 0xa78) */ +#define SRST_PRESETN_PCIE 0x000001e1 +#define SRST_RESETN_PCIE_PIPE_PHY 0x000001e2 +#define SRST_RESETN_PCIE_POWER_UP 0x000001e3 +#define SRST_PRESETN_PCIE_PHY 0x000001e6 +#define SRST_PRESETN_PIPE_GRF 0x000001e7 + +/* CRU_SOFTRST_CON32 (Offset: 0xa80) */ +#define SRST_HRESETN_SDIO0 0x00000202 +#define SRST_HRESETN_SDIO1 0x00000204 +#define SRST_RESETN_TS_0 0x00000205 +#define SRST_RESETN_TS_1 0x00000206 +#define SRST_PRESETN_CAN2 0x00000207 +#define SRST_RESETN_CAN2 0x00000208 +#define SRST_PRESETN_CAN3 0x00000209 +#define SRST_RESETN_CAN3 0x0000020a +#define SRST_PRESETN_SARADC 0x0000020b +#define SRST_RESETN_SARADC 0x0000020c +#define SRST_RESETN_SARADC_PHY 0x0000020d +#define SRST_PRESETN_TSADC 0x0000020e +#define SRST_RESETN_TSADC 0x0000020f + +/* CRU_SOFTRST_CON33 (Offset: 0xa84) */ +#define SRST_ARESETN_USB3OTG 0x00000211 + +/* CRU_SOFTRST_CON34 (Offset: 0xa88) */ +#define SRST_ARESETN_GPU_BIU 0x00000223 +#define SRST_PRESETN_GPU_BIU 0x00000225 +#define SRST_ARESETN_GPU 0x00000228 +#define SRST_RESETN_REF_PVTPLL_GPU 0x00000229 + +/* CRU_SOFTRST_CON36 (Offset: 0xa90) */ +#define SRST_HRESETN_RKVENC_BIU 0x00000243 +#define SRST_ARESETN_RKVENC_BIU 0x00000244 +#define SRST_PRESETN_RKVENC_BIU 0x00000245 +#define SRST_HRESETN_RKVENC 0x00000246 +#define SRST_ARESETN_RKVENC 0x00000247 +#define SRST_RESETN_CORE_RKVENC 0x00000248 +#define SRST_HRESETN_SAI_I2S1 0x00000249 +#define SRST_MRESETN_SAI_I2S1 0x0000024a +#define SRST_PRESETN_I2C1 0x0000024b +#define SRST_RESETN_I2C1 0x0000024c +#define SRST_PRESETN_I2C0 0x0000024d +#define SRST_RESETN_I2C0 0x0000024e + +/* CRU_SOFTRST_CON37 (Offset: 0xa94) */ +#define SRST_PRESETN_SPI0 0x00000252 +#define SRST_RESETN_SPI0 0x00000253 +#define SRST_PRESETN_GPIO4 0x00000258 +#define SRST_DBRESETN_GPIO4 0x00000259 +#define SRST_PRESETN_RKVENC_IOC 0x0000025a +#define SRST_HRESETN_SPDIF 0x0000025e +#define SRST_MRESETN_SPDIF 0x0000025f + +/* CRU_SOFTRST_CON38 (Offset: 0xa98) */ +#define SRST_HRESETN_PDM 0x00000260 +#define SRST_MRESETN_PDM 0x00000261 +#define SRST_PRESETN_UART1 0x00000262 +#define SRST_SRESETN_UART1 0x00000263 +#define SRST_PRESETN_UART3 0x00000264 +#define SRST_SRESETN_UART3 0x00000265 +#define SRST_PRESETN_RKVENC_GRF 0x00000266 +#define SRST_PRESETN_CAN0 0x00000267 +#define SRST_RESETN_CAN0 0x00000268 +#define SRST_PRESETN_CAN1 0x00000269 +#define SRST_RESETN_CAN1 0x0000026a + +/* CRU_SOFTRST_CON39 (Offset: 0xa9c) */ +#define SRST_ARESETN_VO_BIU 0x00000273 +#define SRST_HRESETN_VO_BIU 0x00000274 +#define SRST_PRESETN_VO_BIU 0x00000275 +#define SRST_HRESETN_RGA2E 0x00000277 +#define SRST_ARESETN_RGA2E 0x00000278 +#define SRST_RESETN_CORE_RGA2E 0x00000279 +#define SRST_HRESETN_VDPP 0x0000027a +#define SRST_ARESETN_VDPP 0x0000027b +#define SRST_RESETN_CORE_VDPP 0x0000027c +#define SRST_PRESETN_VO_GRF 0x0000027d +#define SRST_PRESETN_CRU 0x0000027f + +/* CRU_SOFTRST_CON40 (Offset: 0xaa0) */ +#define SRST_ARESETN_VOP_BIU 0x00000281 +#define SRST_HRESETN_VOP 0x00000282 +#define SRST_DRESETN_VOP0 0x00000283 +#define SRST_DRESETN_VOP1 0x00000284 +#define SRST_ARESETN_VOP 0x00000285 +#define SRST_PRESETN_HDMI 0x00000286 +#define SRST_HDMI_RESETN 0x00000287 +#define SRST_PRESETN_HDMIPHY 0x0000028e +#define SRST_HRESETN_HDCP_KEY 0x0000028f + +/* CRU_SOFTRST_CON41 (Offset: 0xaa4) */ +#define SRST_ARESETN_HDCP 0x00000290 +#define SRST_HRESETN_HDCP 0x00000291 +#define SRST_PRESETN_HDCP 0x00000292 +#define SRST_HRESETN_CVBS 0x00000293 +#define SRST_DRESETN_CVBS_VOP 0x00000294 +#define SRST_DRESETN_4X_CVBS_VOP 0x00000295 +#define SRST_ARESETN_JPEG_DECODER 0x00000296 +#define SRST_HRESETN_JPEG_DECODER 0x00000297 +#define SRST_ARESETN_VO_L_BIU 0x00000299 +#define SRST_ARESETN_MAC_VO 0x0000029a + +/* CRU_SOFTRST_CON42 (Offset: 0xaa8) */ +#define SRST_ARESETN_JPEG_BIU 0x000002a0 +#define SRST_HRESETN_SAI_I2S3 0x000002a1 +#define SRST_MRESETN_SAI_I2S3 0x000002a2 +#define SRST_RESETN_MACPHY 0x000002a3 +#define SRST_PRESETN_VCDCPHY 0x000002a4 +#define SRST_PRESETN_GPIO2 0x000002a5 +#define SRST_DBRESETN_GPIO2 0x000002a6 +#define SRST_PRESETN_VO_IOC 0x000002a7 +#define SRST_HRESETN_SDMMC0 0x000002a9 +#define SRST_PRESETN_OTPC_NS 0x000002ab +#define SRST_RESETN_SBPI_OTPC_NS 0x000002ac +#define SRST_RESETN_USER_OTPC_NS 0x000002ad + +/* CRU_SOFTRST_CON43 (Offset: 0xaac) */ +#define SRST_RESETN_HDMIHDP0 0x000002b2 +#define SRST_HRESETN_USBHOST 0x000002b3 +#define SRST_HRESETN_USBHOST_ARB 0x000002b4 +#define SRST_RESETN_HOST_UTMI 0x000002b6 +#define SRST_PRESETN_UART4 0x000002b7 +#define SRST_SRESETN_UART4 0x000002b8 +#define SRST_PRESETN_I2C4 0x000002b9 +#define SRST_RESETN_I2C4 0x000002ba +#define SRST_PRESETN_I2C7 0x000002bb +#define SRST_RESETN_I2C7 0x000002bc +#define SRST_PRESETN_USBPHY 0x000002bd +#define SRST_RESETN_USBPHY_POR 0x000002be +#define SRST_RESETN_USBPHY_OTG 0x000002bf + +/* CRU_SOFTRST_CON44 (Offset: 0xab0) */ +#define SRST_RESETN_USBPHY_HOST 0x000002c0 +#define SRST_PRESETN_DDRPHY_CRU 0x000002c4 +#define SRST_HRESETN_RKVDEC_BIU 0x000002c6 +#define SRST_ARESETN_RKVDEC_BIU 0x000002c7 +#define SRST_ARESETN_RKVDEC 0x000002c8 +#define SRST_HRESETN_RKVDEC 0x000002c9 +#define SRST_RESETN_HEVC_CA_RKVDEC 0x000002cb +#define SRST_RESETN_REF_PVTPLL_RKVDEC 0x000002cc + +/* CRU_SOFTRST_CON45 (Offset: 0xab4) */ +#define SRST_PRESETN_DDR_BIU 0x000002d1 +#define SRST_PRESETN_DDRC 0x000002d2 +#define SRST_PRESETN_DDRMON 0x000002d3 +#define SRST_RESETN_TIMER_DDRMON 0x000002d4 +#define SRST_PRESETN_MSCH_BIU 0x000002d5 +#define SRST_PRESETN_DDR_GRF 0x000002d6 +#define SRST_PRESETN_DDR_HWLP 0x000002d8 +#define SRST_PRESETN_DDRPHY 0x000002d9 +#define SRST_RESETN_MSCH_BIU 0x000002da +#define SRST_ARESETN_DDR_UPCTL 0x000002db +#define SRST_RESETN_DDR_UPCTL 0x000002dc +#define SRST_RESETN_DDRMON 0x000002dd +#define SRST_ARESETN_DDR_SCRAMBLE 0x000002de +#define SRST_ARESETN_SPLIT 0x000002df + +/* CRU_SOFTRST_CON46 (Offset: 0xab8) */ +#define SRST_RESETN_DDR_PHY 0x000002e0 + +#endif /* __DT_BINDINGS_CLK_ROCKCHIP_RK3528_H__ */ diff --git a/bsp/rockchip/dm/include/pinctrl-rockchip.h b/bsp/rockchip/dm/include/pinctrl-rockchip.h index 0e008963624..0ec0d9fdb93 100755 --- a/bsp/rockchip/dm/include/pinctrl-rockchip.h +++ b/bsp/rockchip/dm/include/pinctrl-rockchip.h @@ -46,7 +46,9 @@ enum rockchip_pin_pull_type enum rockchip_pinctrl_type { RK3308, + RK3528, RK3568, + RK3576, RK3588, }; diff --git a/bsp/rockchip/dm/nvmem/nvmem-rockchip-otp.c b/bsp/rockchip/dm/nvmem/nvmem-rockchip-otp.c index e879582ce92..e6441eb8830 100755 --- a/bsp/rockchip/dm/nvmem/nvmem-rockchip-otp.c +++ b/bsp/rockchip/dm/nvmem/nvmem-rockchip-otp.c @@ -880,6 +880,12 @@ static const struct rockchip_otp_data px30s_data = .read = px30s_otp_read, }; +static const struct rockchip_otp_data rk3528_data = +{ + .size = 0x80, + .read = rk3568_otp_read, +}; + static const struct rockchip_otp_data rk3568_data = { .size = 0x80, @@ -1018,6 +1024,7 @@ static const struct rt_ofw_node_id rockchip_otp_ofw_ids[] = { .compatible = "rockchip,px30s-otp", .data = &px30s_data, }, { .compatible = "rockchip,rk3308-otp", .data = &px30_data, }, { .compatible = "rockchip,rk3308bs-otp", .data = &px30s_data, }, + { .compatible = "rockchip,rk3528-otp", .data = &rk3528_data, }, { .compatible = "rockchip,rk3568-otp", .data = &rk3568_data, }, { .compatible = "rockchip,rk3576-otp", .data = &rk3576_data, }, { .compatible = "rockchip,rk3588-otp", .data = &rk3588_data, }, diff --git a/bsp/rockchip/dm/pinctrl/pinctrl-rockchip.c b/bsp/rockchip/dm/pinctrl/pinctrl-rockchip.c index 2bb2fede47c..aa2d697a52e 100755 --- a/bsp/rockchip/dm/pinctrl/pinctrl-rockchip.c +++ b/bsp/rockchip/dm/pinctrl/pinctrl-rockchip.c @@ -77,6 +77,22 @@ .pull_type[3] = PULL3, \ } +#define PIN_BANK_IOMUX_FLAGS_OFFSET(ID, \ + PINS, LABEL, IOM0, IOM1, IOM2, IOM3, \ + OFFSET0, OFFSET1, OFFSET2, OFFSET3) \ +{ \ + .bank_num = ID, \ + .nr_pins = PINS, \ + .name = LABEL, \ + .iomux = \ + { \ + { .type = IOM0, .offset = OFFSET0 }, \ + { .type = IOM1, .offset = OFFSET1 }, \ + { .type = IOM2, .offset = OFFSET2 }, \ + { .type = IOM3, .offset = OFFSET3 }, \ + }, \ +} + #define PIN_BANK_IOMUX_FLAGS_OFFSET_PULL_FLAGS( \ ID, PINS, LABEL, IOM0, IOM1, IOM2, IOM3, \ OFFSET0, OFFSET1, OFFSET2, OFFSET3, PULL0, \ @@ -434,6 +450,202 @@ static struct rockchip_pin_ctrl rk3308_pin_ctrl = .set_schmitt = rk3308_set_schmitt, }; +static rt_err_t rk3528_set_mux(struct rockchip_pin_bank *pin_bank, int pin, int mux) +{ + rt_uint8_t bit; + rt_uint32_t data; + int iomux_num = (pin / 8), reg, mask; + struct rt_syscon *regmap; + struct rockchip_pin_data *drvdata = pin_bank->drvdata; + + regmap = drvdata->regmap_base; + reg = pin_bank->iomux[iomux_num].offset; + if ((pin % 8) >= 4) + { + reg += 0x4; + } + bit = (pin % 4) * 4; + mask = 0xf; + + data = (mask << (bit + 16)); + data |= (mux & mask) << bit; + + return rt_syscon_write(regmap, reg, data); +} + +#define RK3528_PULL_BITS_PER_PIN 2 +#define RK3528_PULL_PINS_PER_REG 8 +#define RK3528_PULL_GPIO0_OFFSET 0x200 +#define RK3528_PULL_GPIO1_OFFSET 0x20210 +#define RK3528_PULL_GPIO2_OFFSET 0x30220 +#define RK3528_PULL_GPIO3_OFFSET 0x20230 +#define RK3528_PULL_GPIO4_OFFSET 0x10240 + +static const int rk3528_pull_offsets[] = +{ + RK3528_PULL_GPIO0_OFFSET, + RK3528_PULL_GPIO1_OFFSET, + RK3528_PULL_GPIO2_OFFSET, + RK3528_PULL_GPIO3_OFFSET, + RK3528_PULL_GPIO4_OFFSET, +}; + +static rt_err_t rk3528_set_pull(struct rockchip_pin_bank *pin_bank, int pin, int pull) +{ + int reg, pull_value; + rt_uint32_t data; + rt_uint8_t bit, type; + struct rt_syscon *regmap; + struct rockchip_pin_data *drvdata = pin_bank->drvdata; + + if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT) + { + return -RT_ENOSYS; + } + + if (pin_bank->bank_num >= RT_ARRAY_SIZE(rk3528_pull_offsets)) + { + LOG_E("Unsupported bank_num %d", pin_bank->bank_num); + return -RT_EINVAL; + } + + regmap = drvdata->regmap_base; + reg = rk3528_pull_offsets[pin_bank->bank_num]; + reg += ((pin / RK3528_PULL_PINS_PER_REG) * 4); + bit = (pin % RK3528_PULL_PINS_PER_REG); + bit *= RK3528_PULL_BITS_PER_PIN; + + type = pin_bank->pull_type[pin / 8]; + pull_value = rockchip_translate_pull_value(type, pull); + + if (pull_value < 0) + { + LOG_E("Not supported pull = %d, fixup the code or firmware", pull); + return pull_value; + } + + /* enable the write to the equivalent lower bits */ + data = ((1 << RK3528_PULL_BITS_PER_PIN) - 1) << (bit + 16); + data |= (pull_value << bit); + + return rt_syscon_write(regmap, reg, data); +} + +#define RK3528_DRV_BITS_PER_PIN 8 +#define RK3528_DRV_PINS_PER_REG 2 +#define RK3528_DRV_GPIO0_OFFSET 0x100 +#define RK3528_DRV_GPIO1_OFFSET 0x20120 +#define RK3528_DRV_GPIO2_OFFSET 0x30160 +#define RK3528_DRV_GPIO3_OFFSET 0x20190 +#define RK3528_DRV_GPIO4_OFFSET 0x101C0 + +static const int rk3528_drv_offsets[] = +{ + RK3528_DRV_GPIO0_OFFSET, + RK3528_DRV_GPIO1_OFFSET, + RK3528_DRV_GPIO2_OFFSET, + RK3528_DRV_GPIO3_OFFSET, + RK3528_DRV_GPIO4_OFFSET, +}; + +static rt_err_t rk3528_set_drive(struct rockchip_pin_bank *pin_bank, int pin, int strength) +{ + int reg, drv = (1 << (strength + 1)) - 1; + rt_uint8_t bit; + rt_uint32_t data; + struct rt_syscon *regmap; + struct rockchip_pin_data *drvdata = pin_bank->drvdata; + + if (pin_bank->bank_num >= RT_ARRAY_SIZE(rk3528_drv_offsets)) + { + LOG_E("Unsupported bank_num %d", pin_bank->bank_num); + return -RT_EINVAL; + } + + regmap = drvdata->regmap_base; + reg = rk3528_drv_offsets[pin_bank->bank_num]; + reg += ((pin / RK3528_DRV_PINS_PER_REG) * 4); + bit = pin % RK3528_DRV_PINS_PER_REG; + bit *= RK3528_DRV_BITS_PER_PIN; + + /* enable the write to the equivalent lower bits */ + data = ((1 << RK3528_DRV_BITS_PER_PIN) - 1) << (bit + 16); + data |= (drv << bit); + + return rt_syscon_write(regmap, reg, data); +} + +#define RK3528_SMT_BITS_PER_PIN 1 +#define RK3528_SMT_PINS_PER_REG 8 +#define RK3528_SMT_GPIO0_OFFSET 0x400 +#define RK3528_SMT_GPIO1_OFFSET 0x20410 +#define RK3528_SMT_GPIO2_OFFSET 0x30420 +#define RK3528_SMT_GPIO3_OFFSET 0x20430 +#define RK3528_SMT_GPIO4_OFFSET 0x10440 + +static const int rk3528_smt_offsets[] = +{ + RK3528_SMT_GPIO0_OFFSET, + RK3528_SMT_GPIO1_OFFSET, + RK3528_SMT_GPIO2_OFFSET, + RK3528_SMT_GPIO3_OFFSET, + RK3528_SMT_GPIO4_OFFSET, +}; + +static rt_err_t rk3528_set_schmitt(struct rockchip_pin_bank *pin_bank, int pin, int enable) +{ + int reg; + rt_uint8_t bit; + rt_uint32_t data; + struct rt_syscon *regmap; + struct rockchip_pin_data *drvdata = pin_bank->drvdata; + + if (pin_bank->bank_num >= RT_ARRAY_SIZE(rk3528_smt_offsets)) + { + LOG_E("Unsupported bank_num %d", pin_bank->bank_num); + return -RT_EINVAL; + } + + regmap = drvdata->regmap_base; + reg = rk3528_smt_offsets[pin_bank->bank_num]; + reg += ((pin / RK3528_SMT_PINS_PER_REG) * 4); + bit = pin % RK3528_SMT_PINS_PER_REG; + bit *= RK3528_SMT_BITS_PER_PIN; + + /* enable the write to the equivalent lower bits */ + data = ((1 << RK3528_SMT_BITS_PER_PIN) - 1) << (bit + 16); + data |= (enable << bit); + + return rt_syscon_write(regmap, reg, data); +} + +static struct rockchip_pin_bank rk3528_pin_banks[] = +{ + PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0", IOMUX_WIDTH_4BIT, IOMUX_WIDTH_4BIT, IOMUX_WIDTH_4BIT, IOMUX_WIDTH_4BIT, + 0, 0, 0, 0), + PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_WIDTH_4BIT, IOMUX_WIDTH_4BIT, IOMUX_WIDTH_4BIT, IOMUX_WIDTH_4BIT, + 0x20020, 0x20028, 0x20030, 0x20038), + PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2", IOMUX_WIDTH_4BIT, IOMUX_WIDTH_4BIT, IOMUX_WIDTH_4BIT, IOMUX_WIDTH_4BIT, + 0x30040, 0, 0, 0), + PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3", IOMUX_WIDTH_4BIT, IOMUX_WIDTH_4BIT, IOMUX_WIDTH_4BIT, IOMUX_WIDTH_4BIT, + 0x20060, 0x20068, 0x20070, 0), + PIN_BANK_IOMUX_FLAGS_OFFSET(4, 32, "gpio4", IOMUX_WIDTH_4BIT, IOMUX_WIDTH_4BIT, IOMUX_WIDTH_4BIT, IOMUX_WIDTH_4BIT, + 0x10080, 0x10088, 0x10090, 0x10098), +}; + +static struct rockchip_pin_ctrl rk3528_pin_ctrl = +{ + .pin_banks = rk3528_pin_banks, + .banks_nr = RT_ARRAY_SIZE(rk3528_pin_banks), + .label = "RK3528-GPIO", + .type = RK3528, + .grf_mux_offset = 0x0, + .set_mux = rk3528_set_mux, + .set_pull = rk3528_set_pull, + .set_drive = rk3528_set_drive, + .set_schmitt = rk3528_set_schmitt, +}; + static struct rockchip_mux_route_data rk3568_mux_route_data[] = { RK_MUXROUTE_PMU(0, RK_PB7, 1, 0x0110, WRITE_MASK_VAL(1, 0, 0)), /* PWM0 IO mux M0 */ @@ -1071,10 +1283,12 @@ static struct rockchip_pin_bank rk3576_pin_banks[] = PIN_BANK_OFFSET4(4, "gpio4", 0x4080, 0x4088, 0xA390, 0xB398), }; -static const struct rockchip_pin_ctrl rk3576_pin_ctrl = +static struct rockchip_pin_ctrl rk3576_pin_ctrl = { .pin_banks = rk3576_pin_banks, .banks_nr = RT_ARRAY_SIZE(rk3576_pin_banks), + .label = "RK3576-GPIO", + .type = RK3576, .pins_nr = 160, .grf_mux_offset = 0x0, .set_mux = rk3576_set_mux, @@ -1740,6 +1954,7 @@ static rt_err_t rockchip_pinctrl_probe(struct rt_platform_device *pdev) static const struct rt_ofw_node_id rockchip_pinctrl_ofw_ids[] = { { .compatible = "rockchip,rk3308-pinctrl", .data = &rk3308_pin_ctrl }, + { .compatible = "rockchip,rk3528-pinctrl", .data = &rk3528_pin_ctrl }, { .compatible = "rockchip,rk3568-pinctrl", .data = &rk3568_pin_ctrl }, { .compatible = "rockchip,rk3576-pinctrl", .data = &rk3576_pin_ctrl }, { .compatible = "rockchip,rk3588-pinctrl", .data = &rk3588_pin_ctrl }, diff --git a/bsp/rockchip/dm/thermal/thermal-rockchip_tsadc.c b/bsp/rockchip/dm/thermal/thermal-rockchip_tsadc.c index 4d9252a097e..a3055c31577 100755 --- a/bsp/rockchip/dm/thermal/thermal-rockchip_tsadc.c +++ b/bsp/rockchip/dm/thermal/thermal-rockchip_tsadc.c @@ -46,6 +46,7 @@ #define TSADCV2_AUTO_PERIOD_HT 0x6c #define TSADCV3_AUTO_PERIOD 0x154 #define TSADCV3_AUTO_PERIOD_HT 0x158 +#define TSADCV9_Q_MAX 0x210 #define TSADCV2_AUTO_EN RT_BIT(0) #define TSADCV2_AUTO_EN_MASK RT_BIT(16) @@ -56,6 +57,7 @@ #define TSADCV2_AUTO_TSHUT_POLARITY_MASK RT_BIT(24) #define TSADCV3_AUTO_Q_SEL_EN RT_BIT(1) +#define TSADCV3_AUTO_Q_SEL_EN_MASK RT_BIT(17) #define TSADCV2_INT_SRC_EN(chn) RT_BIT(chn) #define TSADCV2_INT_SRC_EN_MASK(chn) RT_BIT(16 + (chn)) @@ -69,6 +71,7 @@ #define TSADCV2_DATA_MASK 0xfff #define TSADCV3_DATA_MASK 0x3ff #define TSADCV4_DATA_MASK 0x1ff +#define TSADCV5_DATA_MASK 0x7ff #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4 @@ -81,6 +84,10 @@ #define TSADCV5_AUTO_PERIOD_HT_TIME 1622 /* 2.5ms */ #define TSADCV6_AUTO_PERIOD_TIME 5000 /* 2.5ms */ #define TSADCV6_AUTO_PERIOD_HT_TIME 5000 /* 2.5ms */ +#define TSADCV7_AUTO_PERIOD_TIME 3000 /* 2.5ms */ +#define TSADCV7_AUTO_PERIOD_HT_TIME 3000 /* 2.5ms */ + +#define TSADCV3_Q_MAX_VAL 0x7ff /* 11bit 2047 */ #define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */ #define TSADCV5_USER_INTER_PD_SOC 0xfc0 /* 97us, at least 90us */ @@ -91,6 +98,8 @@ #define PX30_GRF_SOC_CON2 0x0408 +#define RK3528_GRF_TSADC_CON 0x40030 + #define RK3568_GRF_TSADC_CON 0x0600 #define RK3568_GRF_TSADC_ANA_REG0 (0x10001 << 0) #define RK3568_GRF_TSADC_ANA_REG1 (0x10001 << 1) @@ -502,6 +511,38 @@ static void rk_tsadcv8_initialize(struct rt_syscon *grf, void *regs, } } +static void rk_tsadcv11_initialize(struct rt_syscon *grf, void *regs, + enum tshut_polarity tshut_polarity) +{ + HWREG32(regs + TSADCV3_AUTO_PERIOD) = TSADCV7_AUTO_PERIOD_TIME; + HWREG32(regs + TSADCV3_AUTO_PERIOD_HT) = TSADCV7_AUTO_PERIOD_HT_TIME; + HWREG32(regs + TSADCV3_HIGHT_INT_DEBOUNCE) = TSADCV2_HIGHT_INT_DEBOUNCE_COUNT; + HWREG32(regs + TSADCV3_HIGHT_TSHUT_DEBOUNCE) = TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT; + HWREG32(regs + TSADCV9_Q_MAX) = TSADCV3_Q_MAX_VAL; + HWREG32(regs + TSADCV2_AUTO_CON) = TSADCV3_AUTO_Q_SEL_EN | TSADCV3_AUTO_Q_SEL_EN_MASK; + + if (tshut_polarity == TSHUT_HIGH_ACTIVE) + { + HWREG32(regs + TSADCV2_AUTO_CON) = TSADCV2_AUTO_TSHUT_POLARITY_HIGH | + TSADCV2_AUTO_TSHUT_POLARITY_MASK; + } + else + { + HWREG32(regs + TSADCV2_AUTO_CON) = TSADCV2_AUTO_TSHUT_POLARITY_MASK; + } + + if (grf) + { + rt_syscon_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_TSEN); + rt_hw_us_delay(15); + + rt_syscon_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG0); + rt_syscon_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG1); + rt_syscon_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG2); + rt_hw_us_delay(150); + } +} + static void rk_tsadcv2_irq_ack(void *regs) { rt_uint32_t val; @@ -1250,6 +1291,75 @@ static const struct rockchip_tsadc_chip rk3399_tsadc_data = }, }; +static const struct tsadc_table rk3528_code_table[] = +{ + { 0, -60000 }, + { 1386, -60000 }, + { 1410, -40000 }, + { 1419, -35000 }, + { 1428, -30000 }, + { 1436, -25000 }, + { 1445, -20000 }, + { 1454, -15000 }, + { 1463, -10000 }, + { 1471, -5000 }, + { 1480, 0 }, + { 1489, 5000 }, + { 1498, 10000 }, + { 1506, 15000 }, + { 1515, 20000 }, + { 1524, 25000 }, + { 1533, 30000 }, + { 1541, 35000 }, + { 1550, 40000 }, + { 1558, 45000 }, + { 1567, 50000 }, + { 1575, 55000 }, + { 1584, 60000 }, + { 1593, 65000 }, + { 1602, 70000 }, + { 1610, 75000 }, + { 1619, 80000 }, + { 1628, 85000 }, + { 1637, 90000 }, + { 1646, 95000 }, + { 1654, 100000 }, + { 1663, 105000 }, + { 1672, 110000 }, + { 1680, 115000 }, + { 1689, 120000 }, + { 1697, 125000 }, + { 1790, 180000 }, + { TSADCV5_DATA_MASK, 180000 }, +}; + +static const struct rockchip_tsadc_chip rk3528_tsadc_data = +{ + .chn_offset = 0, + .chn_num = 1, /* one channels for tsadc */ + .chn_name = chn_name_common, + + .tshut_mode = TSHUT_MODE_OTP, /* default TSHUT via GPIO give PMIC */ + .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ + .tshut_temp = 95000, + + .initialize = rk_tsadcv11_initialize, + .irq_ack = rk_tsadcv4_irq_ack, + .control = rk_tsadcv4_control, + .get_temp = rk_tsadcv4_get_temp, + .set_alarm_temp = rk_tsadcv3_alarm_temp, + .set_tshut_temp = rk_tsadcv3_tshut_temp, + .set_tshut_mode = rk_tsadcv4_tshut_mode, + + .table = + { + .id = rk3528_code_table, + .length = RT_ARRAY_SIZE(rk3528_code_table), + .data_mask = TSADCV2_DATA_MASK, + .mode = ADC_INCREMENT, + }, +}; + static const struct tsadc_table rk3568_code_table[] = { { 0, -40000 }, @@ -1678,6 +1788,7 @@ static const struct rt_ofw_node_id rockchip_tsadc_ofw_ids[] = { .compatible = "rockchip,rk3366-tsadc", .data = &rk3366_tsadc_data, }, { .compatible = "rockchip,rk3368-tsadc", .data = &rk3368_tsadc_data, }, { .compatible = "rockchip,rk3399-tsadc", .data = &rk3399_tsadc_data, }, + { .compatible = "rockchip,rk3528-tsadc", .data = &rk3528_tsadc_data, }, { .compatible = "rockchip,rk3568-tsadc", .data = &rk3568_tsadc_data, }, { .compatible = "rockchip,rk3576-tsadc", .data = &rk3576_tsadc_data, }, { .compatible = "rockchip,rk3588-tsadc", .data = &rk3588_tsadc_data, }, diff --git a/bsp/rockchip/rk3500/.config b/bsp/rockchip/rk3500/.config index 2a186892faa..4ec0c9be97e 100644 --- a/bsp/rockchip/rk3500/.config +++ b/bsp/rockchip/rk3500/.config @@ -11,18 +11,8 @@ # rt_vsnprintf options # # CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set -CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG=y -CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD=y -CONFIG_RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS=y -CONFIG_RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS=y -CONFIG_RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER=y -CONFIG_RT_KLIBC_USING_VSNPRINTF_CHECK_NUL_IN_FORMAT_SPECIFIER=y -# CONFIG_RT_KLIBC_USING_VSNPRINTF_MSVC_STYLE_INTEGER_SPECIFIERS is not set -CONFIG_RT_KLIBC_USING_VSNPRINTF_INTEGER_BUFFER_SIZE=32 -CONFIG_RT_KLIBC_USING_VSNPRINTF_DECIMAL_BUFFER_SIZE=32 -CONFIG_RT_KLIBC_USING_VSNPRINTF_FLOAT_PRECISION=6 -CONFIG_RT_KLIBC_USING_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL=9 -CONFIG_RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS=4 +# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set # end of rt_vsnprintf options # @@ -192,11 +182,12 @@ CONFIG_RT_USING_HEAP=y CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_DEVICE_OPS=y -# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_INTERRUPT_INFO=y CONFIG_RT_USING_THREADSAFE_PRINTF=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=1024 CONFIG_RT_CONSOLE_DEVICE_NAME="uart2" +CONFIG_RT_USING_CONSOLE_OUTPUT_CTL=y CONFIG_RT_VER_NUM=0x50300 CONFIG_RT_USING_STDC_ATOMIC=y CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 @@ -513,11 +504,14 @@ CONFIG_RT_PCI_DW_HOST=y CONFIG_RT_PCI_DW_EP=y CONFIG_RT_PCI_DW_ROCKCHIP=y CONFIG_RT_USING_PIC=y +# CONFIG_RT_USING_PIC_STATISTICS is not set CONFIG_MAX_HANDLERS=2048 -# CONFIG_RT_PIC_ARM_GIC is not set +CONFIG_RT_PIC_ARM_GIC=y +# CONFIG_RT_PIC_ARM_GIC_V2M is not set CONFIG_RT_PIC_ARM_GIC_V3=y CONFIG_RT_PIC_ARM_GIC_V3_ITS=y CONFIG_RT_PIC_ARM_GIC_V3_ITS_IRQ_MAX=256 +CONFIG_RT_PIC_ARM_GIC_MAX_NR=1 CONFIG_RT_USING_PIN=y # CONFIG_RT_PIN_PL061 is not set CONFIG_RT_PIN_ROCKCHIP=y @@ -532,6 +526,7 @@ CONFIG_RT_CLK_ROCKCHIP_RK8XX_CLKOUT=y CONFIG_RT_CLK_ROCKCHIP_LINK=y CONFIG_RT_CLK_ROCKCHIP=y # CONFIG_RT_CLK_ROCKCHIP_RK3308 is not set +CONFIG_RT_CLK_ROCKCHIP_RK3528=y CONFIG_RT_CLK_ROCKCHIP_RK3568=y CONFIG_RT_CLK_ROCKCHIP_RK3576=y CONFIG_RT_CLK_ROCKCHIP_RK3588=y diff --git a/bsp/rockchip/rk3500/README.md b/bsp/rockchip/rk3500/README.md index 33f5c9e60ca..25e40c20bc5 100644 --- a/bsp/rockchip/rk3500/README.md +++ b/bsp/rockchip/rk3500/README.md @@ -11,14 +11,15 @@ https://www.rock-chips.com/a/cn/product/RK35xilie/index.html ### Condition | SoC | Condition | Earlycon | -| ------ | ---- | ---- | +| ------ | ---- | ---- | | RK3576 | Support | earlycon=uart8250,mmio32,0x2ad40000 | | RK3588 | Support | earlycon=uart8250,mmio32,0xfeb50000 | | RK3562 | - | - | | RK3568J | Support | earlycon=uart8250,mmio32,0xfe660000 | | RK3568 | Support | earlycon=uart8250,mmio32,0xfe660000 | | RK3566 | Support | earlycon=uart8250,mmio32,0xfe660000 | -| RK3506 | - | +| RK3528 | Support | earlycon=uart8250,mmio32,0xff9f0000 | +| RK3506 | - | - | ## 2. Compiling diff --git a/bsp/rockchip/rk3500/README_ZH.md b/bsp/rockchip/rk3500/README_ZH.md index 9feff420d9d..74cfe95b2b1 100644 --- a/bsp/rockchip/rk3500/README_ZH.md +++ b/bsp/rockchip/rk3500/README_ZH.md @@ -11,13 +11,14 @@ https://www.rock-chips.com/a/cn/product/RK35xilie/index.html ### 支持列表 | 驱动 | 支持情况 | Earlycon | -| ------ | ---- | ---- | +| ------ | ---- | ---- | | RK3576 | 支持 | earlycon=uart8250,mmio32,0x2ad40000 | | RK3588 | 支持 | earlycon=uart8250,mmio32,0xfeb50000 | | RK3562 | - | - | | RK3568J | 支持 | earlycon=uart8250,mmio32,0xfe660000 | | RK3568 | 支持 | earlycon=uart8250,mmio32,0xfe660000 | | RK3566 | 支持 | earlycon=uart8250,mmio32,0xfe660000 | +| RK3528 | 支持 | earlycon=uart8250,mmio32,0xff9f0000 | | RK3506 | - | - | ## 2. 编译 diff --git a/bsp/rockchip/rk3500/rtconfig.h b/bsp/rockchip/rk3500/rtconfig.h index 54ff974a0cc..3ba507746d1 100644 --- a/bsp/rockchip/rk3500/rtconfig.h +++ b/bsp/rockchip/rk3500/rtconfig.h @@ -7,17 +7,6 @@ /* rt_vsnprintf options */ -#define RT_KLIBC_USING_VSNPRINTF_LONGLONG -#define RT_KLIBC_USING_VSNPRINTF_STANDARD -#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS -#define RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS -#define RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER -#define RT_KLIBC_USING_VSNPRINTF_CHECK_NUL_IN_FORMAT_SPECIFIER -#define RT_KLIBC_USING_VSNPRINTF_INTEGER_BUFFER_SIZE 32 -#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_BUFFER_SIZE 32 -#define RT_KLIBC_USING_VSNPRINTF_FLOAT_PRECISION 6 -#define RT_KLIBC_USING_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL 9 -#define RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS 4 /* end of rt_vsnprintf options */ /* rt_vsscanf options */ @@ -120,10 +109,12 @@ /* end of Memory Management */ #define RT_USING_DEVICE #define RT_USING_DEVICE_OPS +#define RT_USING_INTERRUPT_INFO #define RT_USING_THREADSAFE_PRINTF #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 1024 #define RT_CONSOLE_DEVICE_NAME "uart2" +#define RT_USING_CONSOLE_OUTPUT_CTL #define RT_VER_NUM 0x50300 #define RT_USING_STDC_ATOMIC #define RT_BACKTRACE_LEVEL_MAX_NR 32 @@ -346,9 +337,11 @@ #define RT_PCI_DW_ROCKCHIP #define RT_USING_PIC #define MAX_HANDLERS 2048 +#define RT_PIC_ARM_GIC #define RT_PIC_ARM_GIC_V3 #define RT_PIC_ARM_GIC_V3_ITS #define RT_PIC_ARM_GIC_V3_ITS_IRQ_MAX 256 +#define RT_PIC_ARM_GIC_MAX_NR 1 #define RT_USING_PIN #define RT_PIN_ROCKCHIP #define RT_USING_PINCTRL @@ -359,6 +352,7 @@ #define RT_CLK_ROCKCHIP_RK8XX_CLKOUT #define RT_CLK_ROCKCHIP_LINK #define RT_CLK_ROCKCHIP +#define RT_CLK_ROCKCHIP_RK3528 #define RT_CLK_ROCKCHIP_RK3568 #define RT_CLK_ROCKCHIP_RK3576 #define RT_CLK_ROCKCHIP_RK3588 diff --git a/bsp/rockchip/rk3500/rtconfig.py b/bsp/rockchip/rk3500/rtconfig.py index 82c78e8c64c..70773ac7bce 100644 --- a/bsp/rockchip/rk3500/rtconfig.py +++ b/bsp/rockchip/rk3500/rtconfig.py @@ -34,7 +34,10 @@ OBJDUMP = PREFIX + 'objdump' OBJCPY = PREFIX + 'objcopy' - DEVICE = ' -g -march=armv8.2-a -mtune=cortex-a55 -fdiagnostics-color=always' + # For Cortex-A55/A76 + # DEVICE = ' -g -march=armv8.2-a -mtune=cortex-a55 -fdiagnostics-color=always' + # For Cortex-A53/A72 + DEVICE = ' -g -mcpu=cortex-a53 -fdiagnostics-color=always' CPPFLAGS= ' -nostdinc -undef -E -P -x assembler-with-cpp' CFLAGS = DEVICE + ' -Wall -Wno-cpp' AFLAGS = ' -c' + ' -x assembler-with-cpp -D__ASSEMBLY__'