diff --git a/.github/ALL_BSP_COMPILE.json b/.github/ALL_BSP_COMPILE.json index eeb2c9a4e8f..e232cd16ad7 100644 --- a/.github/ALL_BSP_COMPILE.json +++ b/.github/ALL_BSP_COMPILE.json @@ -244,6 +244,7 @@ "nxp/imx/imxrt/imxrt1064-nxp-evk", "nxp/imx/imxrt/imxrt1021-nxp-evk", "nxp/imx/imxrt/imxrt1170-nxp-evk", + "nxp/imx/imxrt/imxrt1180-nxp-evk", "nxp/mcx/mcxn/frdm-mcxn947", "nxp/mcx/mcxn/frdm-mcxn236", "nxp/mcx/mcxc/frdm-mcxc444", diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/README_zh.md b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/README_zh.md new file mode 100644 index 00000000000..38107730bf2 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/README_zh.md @@ -0,0 +1,114 @@ +# i.MX RT1180 EVK 开发板 BSP 说明 + +## 简介 + +本文档为 NXP i.MX RT1180 EVK 开发板提供的 BSP (板级支持包) 的初步说明。 + +目前支持CM33和CM7的独立编译，CM33作为主核，CM7作为从核。CM33的工程可以从External Flash直接XIP，CM7的工程可以从ITCM加载运行。 + +CM33对CM7的kick off将在后续版本中支持。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 开发板介绍 + +双核i.MX RT1180采用主频达800MHz的Cortex®-M7内核和主频达240MHz的Arm Cortex-M33，同时提供一流的安全保障以及丰富的网络连接功能，包括双千兆以太网和多种工业通信接口。i.MX RT1180 MCU支持宽温度范围，适用于工业控制、电机驱动等市场。 + +## 外设支持 + +本 BSP 目前对外设仅支持UART，作为第一次push的测试，之后会逐步完善。外设支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :----------------- | :----------: | :------------------------------------| +| USB 转串口 | 暂不支持 | | +| SPI Flash | 暂不支持 | | +| 以太网 | 暂不支持 | | +| **片上外设** | **支持情况** | **备注** | +| GPIO | 暂不支持 | | +| UART | 支持 | | +| SPI | 暂不支持 | | +| I2C | 暂不支持 | | +| SDIO | 暂不支持 | | +| RTC | 暂不支持 | | +| PWM | 暂不支持 | | +| CAN | 暂不支持 | | + + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + + +### 快速上手 + +本 BSP 为开发者提供 MDK5 、IAR 以及 GCC 工程。下面以 IAR 开发环境为例，介绍如何将系统运行起来。 + +**请注意！！！** + +在执行编译工作前请先打开ENV执行以下指令（该指令用于拉取必要的库，否则无法通过编译）： + +```bash +pkgs --update +``` + +生成IAR工程：scons --target=iar +生成KEIL MDK5工程：scons --target=mdk5 +或者直接编译GCC工程：scons -j8 + +#### 硬件连接 + +使用数据线连接开发板到 PC，打开电源开关。 + +#### 编译下载 + +双击 project.eww 文件，打开 IAR 工程，编译并下载程序到开发板。 + +> 工程默认配置使用 CMSIS-DAP 下载程序，在通过 CMSIS-DAP 连接开发板的基础上，点击下载按钮即可下载程序到开发板 + +#### 运行结果 + +下载程序成功之后，系统会自动运行。 + +连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: + +``` + \ | / +- RT - Thread Operating System + / | \ 5.2.2 build May 15 2026 17:19:35 + 2006 - 2024 Copyright by RT-Thread team +``` + + +### 进阶使用 + +此 BSP 默认只开启了串口 1 的功能，如果需使用更多高级外设功能，需要利用 ENV 工具对 BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入 `menuconfig` 命令配置工程，配置好之后保存退出。 + +3. 输入 `pkgs --update` 命令更新软件包。 + +4. 输入 `scons --target=mdk5/iar` 命令重新生成工程。 + +## 注意事项 + +暂无 + +## 联系人信息 + +维护人: diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/.config b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/.config new file mode 100644 index 00000000000..67ad7a718e3 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/.config @@ -0,0 +1,1488 @@ + +# +# RT-Thread Kernel +# + +# +# klibc options +# + +# +# rt_vsnprintf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set +# end of rt_vsnprintf options + +# +# rt_vsscanf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSSCANF is not set +# end of rt_vsscanf options + +# +# rt_memset options +# +# CONFIG_RT_KLIBC_USING_USER_MEMSET is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMSET is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMSET is not set +# end of rt_memset options + +# +# rt_memcpy options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMCPY is not set +# end of rt_memcpy options + +# +# rt_memmove options +# +# CONFIG_RT_KLIBC_USING_USER_MEMMOVE is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMMOVE is not set +# end of rt_memmove options + +# +# rt_memcmp options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCMP is not set +# end of rt_memcmp options + +# +# rt_strstr options +# +# CONFIG_RT_KLIBC_USING_USER_STRSTR is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRSTR is not set +# end of rt_strstr options + +# +# rt_strcasecmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCASECMP is not set +# end of rt_strcasecmp options + +# +# rt_strncpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCPY is not set +# end of rt_strncpy options + +# +# rt_strcpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCPY is not set +# end of rt_strcpy options + +# +# rt_strncmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCMP is not set +# end of rt_strncmp options + +# +# rt_strcmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCMP is not set +# end of rt_strcmp options + +# +# rt_strlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRLEN is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRLEN is not set +# end of rt_strlen options + +# +# rt_strnlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set +# end of rt_strnlen options +# end of klibc options + +CONFIG_RT_NAME_MAX=12 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=4096 +# CONFIG_RT_USING_TIMER_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set + +# +# kservice options +# +CONFIG_RT_USING_TINY_FFS=y +# end of kservice options + +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_ASSERT=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_AUTO_INIT is not set +# CONFIG_RT_USING_CI_ACTION is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set +# end of Inter-Thread communication + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +# end of Memory Management + +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x50201 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# end of RT-Thread Kernel + +CONFIG_RT_USING_HW_ATOMIC=y +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_FPU=y +CONFIG_ARCH_ARM_CORTEX_SECURE=y +CONFIG_ARCH_ARM_CORTEX_M33=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=4096 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +# CONFIG_FINSH_USING_WORD_OPERATION is not set +# CONFIG_FINSH_USING_FUNC_EXT is not set +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# end of DFS: device virtual file system + +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_DEV_BUS is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_SERIAL_BYPASS is not set +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_PHY_V2 is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_BLK is not set +# CONFIG_RT_USING_VIRTIO is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_KTIME is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CHERRYUSB is not set +# end of Device Drivers + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 +# end of Timezone and Daylight Saving Time +# end of ISO-ANSI C layer + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# end of Interprocess Communication (IPC) +# end of POSIX (Portable Operating System Interface) layer + +# CONFIG_RT_USING_CPLUSPLUS is not set +# end of C/C++ and POSIX layer + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set +# end of Network + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set +# end of Memory protection + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# end of Utilities + +# CONFIG_RT_USING_VBUS is not set + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set +# end of RT-Thread Components + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set +# end of RT-Thread Utestcases + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set +# CONFIG_PKG_USING_ESP_HOSTED is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set +# end of Marvell WiFi + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# end of Wiced WiFi + +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set +# end of CYW43012 WiFi + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set +# end of BL808 WiFi + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# end of CYW43439 WiFi +# end of Wi-Fi + +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# end of IoT Cloud + +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set +# CONFIG_PKG_USING_PNET is not set +# CONFIG_PKG_USING_OPENER is not set +# CONFIG_PKG_USING_FREEMQTT is not set +# end of IoT - internet of things + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set +# end of security packages + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set +# CONFIG_PKG_USING_RYAN_JSON is not set +# end of JSON: JavaScript Object Notation, a lightweight data-interchange format + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# end of XML: Extensible Markup Language + +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set +# end of language packages + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set +# end of LVGL: powerful and easy-to-use embedded GUI library + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# end of u8g2: a monochrome graphic library + +# CONFIG_PKG_USING_NES_SIMULATOR is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set +# end of multimedia packages + +# +# tools packages +# +# CONFIG_PKG_USING_VECTOR is not set +CONFIG_PKG_USING_CMBACKTRACE=y +# CONFIG_PKG_CMBACKTRACE_PLATFORM_M0_M0PLUS is not set +# CONFIG_PKG_CMBACKTRACE_PLATFORM_M3 is not set +# CONFIG_PKG_CMBACKTRACE_PLATFORM_M4 is not set +# CONFIG_PKG_CMBACKTRACE_PLATFORM_M7 is not set +CONFIG_PKG_CMBACKTRACE_PLATFORM_M33=y +# CONFIG_PKG_CMBACKTRACE_PLATFORM_NOT_SELECTED is not set +CONFIG_PKG_CMBACKTRACE_DUMP_STACK=y +CONFIG_PKG_CMBACKTRACE_PRINT_ENGLISH=y +# CONFIG_PKG_CMBACKTRACE_PRINT_CHINESE is not set +# CONFIG_PKG_CMBACKTRACE_PRINT_CHINESE_UTF8 is not set +# CONFIG_CMB_USING_FAL_FLASH_LOG is not set +CONFIG_PKG_CMBACKTRACE_PATH="/packages/tools/CmBacktrace" +CONFIG_PKG_USING_CMBACKTRACE_V10401=y +# CONFIG_PKG_USING_CMBACKTRACE_V10400 is not set +# CONFIG_PKG_USING_CMBACKTRACE_V10300 is not set +# CONFIG_PKG_USING_CMBACKTRACE_V10202 is not set +# CONFIG_PKG_USING_CMBACKTRACE_V10200 is not set +# CONFIG_PKG_USING_CMBACKTRACE_LATEST_VERSION is not set +CONFIG_PKG_CMBACKTRACE_VER="v1.4.1" +CONFIG_PKG_CMBACKTRACE_VER_NUM=0x10401 +# CONFIG_PKG_USING_MCOREDUMP is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_ZDEBUG is not set +# CONFIG_PKG_USING_RVBACKTRACE is not set +# CONFIG_PKG_USING_HPATCHLITE is not set +# CONFIG_PKG_USING_THREAD_METRIC is not set +# CONFIG_PKG_USING_UORB is not set +# CONFIG_PKG_USING_RT_TUNNEL is not set +# CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set +# end of tools packages + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# end of enhanced kernel services + +# CONFIG_PKG_USING_AUNITY is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# end of acceleration: Assembly language or algorithmic acceleration packages + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_CORE is not set +# CONFIG_PKG_USING_CMSIS_NN is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set +# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# end of Micrium: Micrium software products porting for RT-Thread + +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_UART_FRAMEWORK is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_RMP is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set +# CONFIG_PKG_USING_HEARTBEAT is not set +# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# CONFIG_PKG_USING_CHERRYECAT is not set +# end of system packages + +# +# peripheral libraries and drivers +# + +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32F0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_STM32WL_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WL_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set +# end of STM32 HAL & SDK Drivers + +# +# Infineon HAL Packages +# +# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set +# CONFIG_PKG_USING_INFINEON_CMSIS is not set +# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set +# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_ESP_IDF is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# end of Kendryte SDK + +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_MM32 is not set + +# +# WCH HAL & SDK Drivers +# +# CONFIG_PKG_USING_CH32V20x_SDK is not set +# CONFIG_PKG_USING_CH32V307_SDK is not set +# end of WCH HAL & SDK Drivers + +# +# AT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_AT32A403A_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A403A_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_CMSIS_DRIVER is not set +# end of AT32 HAL & SDK Drivers + +# +# HC32 DDL Drivers +# +# CONFIG_PKG_USING_HC32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F3_SERIES_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_SERIES_DRIVER is not set +# end of HC32 DDL Drivers + +# +# NXP HAL & SDK Drivers +# +# CONFIG_PKG_USING_NXP_MCX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NXP_MCX_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC55S_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6SX_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set +CONFIG_PKG_USING_NXP_IMXRT_DRIVER=y +CONFIG_PKG_NXP_IMXRT_DRIVER_PATH="/packages/peripherals/hal-sdk/nxp/nxp-imxrt-sdk" +CONFIG_PKG_USING_NXP_IMXRT_DRIVER_LATEST_VERSION=y +CONFIG_PKG_NXP_IMXRT_DRIVER_VER="latest" +# end of NXP HAL & SDK Drivers + +# +# NUVOTON Drivers +# +# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set +# end of NUVOTON Drivers + +# +# GD32 Drivers +# +# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32_RISCV_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32VW55X_WIFI is not set +# end of GD32 Drivers + +# +# HPMicro SDK +# +# CONFIG_PKG_USING_HPM_SDK is not set +# end of HPMicro SDK + +# +# FT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_FT32F0_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set +# end of FT32 HAL & SDK Drivers +# end of HAL & SDK Drivers + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_MAX31855 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90384 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90396 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set +# CONFIG_PKG_USING_P3T1755 is not set +# CONFIG_PKG_USING_QMI8658 is not set +# CONFIG_PKG_USING_ICM20948 is not set +# CONFIG_PKG_USING_SCD4X is not set +# end of sensors drivers + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# end of touch drivers + +# CONFIG_PKG_USING_LCD_SPI_DRIVER is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_BT_MX02 is not set +# CONFIG_PKG_USING_GC9A01 is not set +# CONFIG_PKG_USING_IK485 is not set +# CONFIG_PKG_USING_SERVO is not set +# CONFIG_PKG_USING_SEAN_WS2812B is not set +# CONFIG_PKG_USING_IC74HC165 is not set +# CONFIG_PKG_USING_IST8310 is not set +# CONFIG_PKG_USING_ST7789_SPI is not set +# CONFIG_PKG_USING_CAN_UDS is not set +# CONFIG_PKG_USING_ISOTP_C is not set +# CONFIG_PKG_USING_IKUNLED is not set +# CONFIG_PKG_USING_INS5T8025 is not set +# CONFIG_PKG_USING_ST7305 is not set +# CONFIG_PKG_USING_TM1668 is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set +# end of peripheral libraries and drivers + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set +# CONFIG_PKG_USING_LLMCHAT is not set +# end of AI packages + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_APID is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set +# CONFIG_PKG_USING_CMSIS_DSP is not set +# end of Signal Processing and Control Algorithm Packages + +# +# miscellaneous packages +# + +# +# project laboratory +# +# end of project laboratory + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# end of samples: kernel and components samples + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# CONFIG_PKG_USING_TINYSQUARE is not set +# end of entertainment: terminal games and other interesting software packages + +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LIBCRC is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set +# CONFIG_PKG_USING_DRMP is not set +# end of miscellaneous packages + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_RTDUINO_SENSORFUSION_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set +# end of Projects and Demos + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set +# end of Sensors + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set +# end of Display + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set +# end of Timing + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set +# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set +# end of Data Processing + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set +# end of Communication + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# end of Device Control + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# end of Other + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set +# end of Signal IO + +# +# Uncategorized +# +# end of Arduino libraries +# end of RT-Thread online packages + +CONFIG_SOC_IMXRT1180_SERIES=y + +# +# Hardware Drivers Config +# +CONFIG_BSP_USING_QSPIFLASH=y +CONFIG_SOC_MIMXRT1189CVM8C=y +CONFIG_SOC_MIMXRT1189CVM8C_CM33=y + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_DMA=y +# CONFIG_BSP_USING_GPIO is not set +# CONFIG_BSP_USING_RTC is not set +# CONFIG_BSP_USING_USB is not set +# CONFIG_BSP_USING_SDIO is not set +CONFIG_BSP_USING_LPUART=y +CONFIG_BSP_USING_LPUART1=y +# CONFIG_BSP_LPUART1_RX_USING_DMA is not set +# CONFIG_BSP_LPUART1_TX_USING_DMA is not set +# CONFIG_BSP_USING_LPUART3 is not set +# CONFIG_BSP_USING_CAN is not set +# CONFIG_BSP_USING_FLEXSPI is not set +# end of On-chip Peripheral Drivers + +# +# Onboard Peripheral Drivers +# +# CONFIG_BSP_USING_SDRAM is not set +# CONFIG_BSP_USING_ETH is not set +# CONFIG_BSP_USING_FS is not set +# end of Onboard Peripheral Drivers + +# +# Board extended module Drivers +# +# end of Hardware Drivers Config diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/JLinkLog.txt b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/JLinkLog.txt new file mode 100644 index 00000000000..f9bf938c59e --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/JLinkLog.txt @@ -0,0 +1,16871 @@ +T714C 000:006.630 SEGGER J-Link V7.98c Log File +T714C 000:007.255 DLL Compiled: Aug 7 2024 15:37:06 +T714C 000:007.291 Logging started @ 2026-05-15 07:19 +T714C 000:007.309 Process: C:\Users\nxg01727\AppData\Local\Keil_v5\UV4\UV4.exe +T714C 000:007.331 - 7.326ms +T714C 000:007.366 JLINK_SetWarnOutHandler(...) +T714C 000:007.390 - 0.025ms +T714C 000:007.414 JLINK_OpenEx(...) +T714C 000:011.585 Firmware: J-Link V13 compiled Apr 1 2025 10:02:49 +T714C 000:012.156 Firmware: J-Link V13 compiled Apr 1 2025 10:02:49 +T714C 000:013.450 Hardware: V13.00 +T714C 000:013.492 S/N: 603001820 +T714C 000:013.516 OEM: SEGGER +T714C 000:013.539 Feature(s): RDI, FlashBP, FlashDL, JFlash, GDB +T714C 000:014.718 Bootloader: (FW returned invalid version) +T714C 000:015.079 USB speed mode: High speed (480 MBit/s) +T714C 000:015.474 TELNET listener socket opened on port 19021 +T714C 000:015.849 WEBSRV WEBSRV_Init(): Starting webserver thread(s) +T714C 000:016.374 WEBSRV Webserver running on local port 19080 +T714C 000:016.678 Looking for J-Link GUI Server exe at: C:\Users\nxg01727\AppData\Local\Keil_v5\ARM\Segger\JLinkGUIServer.exe +T714C 000:016.960 Looking for J-Link GUI Server exe at: C:\Program Files\SEGGER\JLink\JLinkGUIServer.exe +T714C 000:017.135 Forking J-Link GUI Server: C:\Program Files\SEGGER\JLink\JLinkGUIServer.exe +T714C 000:102.553 J-Link GUI Server info: "J-Link GUI server V8.44 " +T714C 000:126.103 - 118.674ms returns "O.K." +T714C 000:126.308 JLINK_GetEmuCaps() +T714C 000:126.422 - 0.107ms returns 0xB9FF7BBF +T714C 000:126.468 JLINK_TIF_GetAvailable(...) +T714C 000:126.692 - 0.223ms +T714C 000:126.752 JLINK_SetErrorOutHandler(...) +T714C 000:126.785 - 0.033ms +T714C 000:126.815 JLINK_ExecCommand("ProjectFile = "C:\0.RanChen\2.Projects\RT-Thread\rt-thread\bsp\nxp\imx\imxrt\imxrt1180-nxp-evk_sdk2506\cm33\JLinkSettings.ini"", ...). +T714C 000:148.664 Flash bank @ 0x28000000: SFL: Parsing sectorization info from ELF file +T714C 000:148.845 FlashDevice.SectorInfo[0]: .SectorSize = 0x00010000, .SectorStartAddr = 0x00000000 +T714C 000:159.493 Flash bank @ 0x38000000: SFL: Parsing sectorization info from ELF file +T714C 000:159.777 FlashDevice.SectorInfo[0]: .SectorSize = 0x00010000, .SectorStartAddr = 0x00000000 +T714C 000:174.967 Device "MIMXRT1189XXX8_M33" selected. +T714C 000:177.154 - 50.339ms returns 0x00 +T714C 000:181.095 JLINK_ExecCommand("Device = MIMXRT1189CVM8C:cm33", ...). +T714C 000:184.954 Flash bank @ 0x28000000: SFL: Parsing sectorization info from ELF file +T714C 000:185.059 FlashDevice.SectorInfo[0]: .SectorSize = 0x00010000, .SectorStartAddr = 0x00000000 +T714C 000:196.493 Flash bank @ 0x38000000: SFL: Parsing sectorization info from ELF file +T714C 000:196.674 FlashDevice.SectorInfo[0]: .SectorSize = 0x00010000, .SectorStartAddr = 0x00000000 +T714C 000:209.364 Device "MIMXRT1189XXX8_M33" selected. +T714C 000:211.551 - 30.369ms returns 0x00 +T714C 000:212.250 JLINK_ExecCommand("DisableConnectionTimeout", ...). +T714C 000:212.391 ERROR: Unknown command +T714C 000:212.418 - 0.028ms returns 0x01 +T714C 000:212.437 JLINK_GetHardwareVersion() +T714C 000:212.465 - 0.017ms returns 130000 +T714C 000:212.482 JLINK_GetDLLVersion() +T714C 000:212.498 - 0.016ms returns 79803 +T714C 000:212.515 JLINK_GetOEMString(...) +T714C 000:212.533 JLINK_GetFirmwareString(...) +T714C 000:212.549 - 0.015ms +T714C 000:219.962 JLINK_GetDLLVersion() +T714C 000:220.037 - 0.074ms returns 79803 +T714C 000:220.055 JLINK_GetCompileDateTime() +T714C 000:220.071 - 0.015ms +T714C 000:224.036 JLINK_GetFirmwareString(...) +T714C 000:224.104 - 0.067ms +T714C 000:226.128 JLINK_GetHardwareVersion() +T714C 000:226.194 - 0.065ms returns 130000 +T714C 000:228.110 JLINK_GetSN() +T714C 000:228.166 - 0.055ms returns 603001820 +T714C 000:230.171 JLINK_GetOEMString(...) +T714C 000:234.214 JLINK_TIF_Select(JLINKARM_TIF_SWD) +T714C 000:237.155 - 2.939ms returns 0x00 +T714C 000:237.269 JLINK_HasError() +T714C 000:237.315 JLINK_SetSpeed(5000) +T714C 000:237.489 - 0.176ms +T714C 000:237.549 JLINK_GetId() +T714C 000:240.950 ConfigTargetSettings() start +T714C 000:241.043 J-Link Script File: Executing ConfigTargetSettings() +T714C 000:243.284 ConfigTargetSettings() end - Took 38us +T714C 000:245.491 Found SW-DP with ID 0x5BA02477 +T714C 000:251.249 DPIDR: 0x5BA02477 +T714C 000:254.434 CoreSight SoC-400 or earlier +T714C 000:257.494 AP map detection skipped. Manually configured AP map found. +T714C 000:259.515 AP[0]: AHB-AP (IDR: Not set) +T714C 000:261.181 AP[1]: APB-AP (IDR: Not set) +T714C 000:262.880 AP[2]: AHB-AP (IDR: Not set) +T714C 000:265.040 AP[3]: AHB-AP (IDR: Not set) +T714C 000:267.539 AP[4]: APB-AP (IDR: Not set) +T714C 000:271.559 AP[5]: APB-AP (IDR: Not set) +T714C 000:274.934 AP[6]: APB-AP (IDR: Not set) +T714C 000:277.592 AP[3]: Core found +T714C 000:279.624 AP[3]: AHB-AP ROM base: 0xE00FF000 +T714C 000:282.041 CPUID register: 0x411FD210. Implementer code: 0x41 (ARM) +T714C 000:285.784 Feature set: Mainline +T714C 000:288.163 Cache: No cache +T714C 000:290.657 Found Cortex-M33 r1p0, Little endian. +T714C 000:291.085 -- Max. mem block: 0x00005B30 +T714C 000:291.580 CPU_ReadMem(4 bytes @ 0xE000EDF0) +T714C 000:291.877 CPU_WriteMem(4 bytes @ 0xE000EDF0) +T714C 000:292.158 CPU_ReadMem(4 bytes @ 0xE0002000) +T714C 000:294.243 FPUnit: 8 code (BP) slots and 0 literal slots +T714C 000:294.301 CPU_ReadMem(4 bytes @ 0xE000EDFC) +T714C 000:294.581 CPU_WriteMem(4 bytes @ 0xE000EDFC) +T714C 000:294.838 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 000:295.083 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 000:295.326 CPU_ReadMem(4 bytes @ 0xE0001028) +T714C 000:295.622 CPU_ReadMem(4 bytes @ 0xE0001038) +T714C 000:295.871 CPU_ReadMem(4 bytes @ 0xE0001048) +T714C 000:296.120 CPU_ReadMem(4 bytes @ 0xE0001058) +T714C 000:296.383 CPU_WriteMem(4 bytes @ 0xE0001000) +T714C 000:296.619 CPU_ReadMem(4 bytes @ 0xE000ED88) +T714C 000:296.869 CPU_WriteMem(4 bytes @ 0xE000ED88) +T714C 000:297.119 CPU_ReadMem(4 bytes @ 0xE000ED88) +T714C 000:297.421 CPU_WriteMem(4 bytes @ 0xE000ED88) +T714C 000:297.842 CPU_ReadMem(4 bytes @ 0xE000EFB8) +T714C 000:301.914 Security extension: implemented +T714C 000:304.419 Secure debug: enabled +T714C 000:306.511 CoreSight components: +T714C 000:308.265 ROMTbl[0] @ E00FF000 +T714C 000:308.351 CPU_ReadMem(64 bytes @ 0xE00FF000) +T714C 000:308.797 CPU_ReadMem(32 bytes @ 0xE000EFE0) +T714C 000:309.163 CPU_ReadMem(4 bytes @ 0xE000EFBC) +T714C 000:309.462 CPU_ReadMem(4 bytes @ 0xE000EFCC) +T714C 000:311.418 [0][0]: E000E000 CID B105900D PID 000BBD21 DEVARCH 47702A04 DEVTYPE 00 Cortex-M33 +T714C 000:311.476 CPU_ReadMem(32 bytes @ 0xE0001FE0) +T714C 000:311.842 CPU_ReadMem(4 bytes @ 0xE0001FBC) +T714C 000:312.104 CPU_ReadMem(4 bytes @ 0xE0001FCC) +T714C 000:316.572 [0][1]: E0001000 CID B105900D PID 000BBD21 DEVARCH 47701A02 DEVTYPE 00 DWT +T714C 000:316.656 CPU_ReadMem(32 bytes @ 0xE0002FE0) +T714C 000:317.048 CPU_ReadMem(4 bytes @ 0xE0002FBC) +T714C 000:317.358 CPU_ReadMem(4 bytes @ 0xE0002FCC) +T714C 000:320.382 [0][2]: E0002000 CID B105900D PID 000BBD21 DEVARCH 47701A03 DEVTYPE 00 FPB +T714C 000:320.493 CPU_ReadMem(32 bytes @ 0xE0000FE0) +T714C 000:320.845 CPU_ReadMem(4 bytes @ 0xE0000FBC) +T714C 000:321.111 CPU_ReadMem(4 bytes @ 0xE0000FCC) +T714C 000:323.319 [0][3]: E0000000 CID B105900D PID 000BBD21 DEVARCH 47701A01 DEVTYPE 43 ITM +T714C 000:323.387 CPU_ReadMem(32 bytes @ 0xE0041FE0) +T714C 000:323.761 CPU_ReadMem(4 bytes @ 0xE0041FBC) +T714C 000:324.040 CPU_ReadMem(4 bytes @ 0xE0041FCC) +T714C 000:326.196 [0][5]: E0041000 CID B105900D PID 002BBD21 DEVARCH 47724A13 DEVTYPE 13 ETM +T714C 000:326.252 CPU_ReadMem(32 bytes @ 0xE0042FE0) +T714C 000:326.634 CPU_ReadMem(4 bytes @ 0xE0042FBC) +T714C 000:326.903 CPU_ReadMem(4 bytes @ 0xE0042FCC) +T714C 000:329.114 [0][6]: E0042000 CID B105900D PID 000BBD21 DEVARCH 47701A14 DEVTYPE 14 CSS600-CTI +T714C 000:331.475 SetupTarget() start +T714C 000:331.544 J-Link Script File: Executing SetupTarget() +T714C 000:333.817 CPU_WriteMem(4 bytes @ 0x20000000) +T714C 000:334.115 CPU_WriteMem(4 bytes @ 0x20000004) +T714C 000:334.358 CPU_WriteMem(4 bytes @ 0x20000008) +T714C 000:334.687 CPU_WriteMem(4 bytes @ 0x2000000C) +T714C 000:337.415 Initializing ECC RAM... +T714C 000:339.326 RAMCodeAddr: 0x20000000 +T714C 000:340.970 RAMInitAddr: 0x20000010 +T714C 000:342.719 RAMInitSize: 0x0001FFF0 +T714C 000:345.082 InitPattern: 0xDEADBEEF +T714C 000:345.260 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 000:345.576 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 000:346.002 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 000:346.527 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 000:346.883 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 000:347.239 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 000:347.614 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 000:348.075 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 000:348.443 CPU_WriteMem(10 bytes @ 0x20000000) +T714C 000:348.847 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 000:354.906 ECC RAM initialized successfully +T714C 000:355.024 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 000:355.305 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 000:355.585 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 000:355.832 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 000:356.092 CPU_WriteMem(64 bytes @ 0xE000E180) +T714C 000:356.487 CPU_WriteMem(64 bytes @ 0xE000E280) +T714C 000:358.756 SetupTarget() end - Took 25.4ms +T714C 000:359.134 - 121.584ms returns 0x5BA02477 +T714C 000:359.187 JLINK_GetDLLVersion() +T714C 000:359.219 - 0.032ms returns 79803 +T714C 000:359.245 JLINK_CORE_GetFound() +T714C 000:359.262 - 0.017ms returns 0xE0200FF +T714C 000:359.303 JLINK_GetDebugInfo(0x100 = JLINKARM_ROM_TABLE_ADDR_INDEX) +T714C 000:359.322 Value=0xE00FF000 +T714C 000:359.346 - 0.043ms returns 0 +T714C 000:361.408 JLINK_GetDebugInfo(0x100 = JLINKARM_ROM_TABLE_ADDR_INDEX) +T714C 000:361.467 Value=0xE00FF000 +T714C 000:361.491 - 0.083ms returns 0 +T714C 000:361.509 JLINK_GetDebugInfo(0x101 = JLINKARM_DEBUG_INFO_ETM_ADDR_INDEX) +T714C 000:361.525 Value=0xE0041000 +T714C 000:361.550 - 0.041ms returns 0 +T714C 000:361.568 JLINK_ReadMemEx(0xE0041FD0, 0x20 Bytes, Flags = 0x02000004) +T714C 000:361.594 CPU_ReadMem(32 bytes @ 0xE0041FD0) +T714C 000:361.979 Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... +T714C 000:362.016 - 0.448ms returns 32 (0x20) +T714C 000:362.035 JLINK_ReadMemU32(0xE0041FBC, 0x1 Items) +T714C 000:362.115 CPU_ReadMem(4 bytes @ 0xE0041FBC) +T714C 000:362.432 Data: 13 4A 72 47 +T714C 000:362.465 - 0.429ms returns 1 (0x1) +T714C 000:362.483 JLINK_GetDebugInfo(0x102 = JLINKARM_DEBUG_INFO_MTB_ADDR_INDEX) +T714C 000:362.500 Value=0x00000000 +T714C 000:362.524 - 0.041ms returns 0 +T714C 000:362.541 JLINK_GetDebugInfo(0x103 = JLINKARM_DEBUG_INFO_TPIU_ADDR_INDEX) +T714C 000:362.557 Value=0x00000000 +T714C 000:362.581 - 0.039ms returns 0 +T714C 000:362.598 JLINK_GetDebugInfo(0x104 = JLINKARM_DEBUG_INFO_ITM_ADDR_INDEX) +T714C 000:362.613 Value=0xE0000000 +T714C 000:362.637 - 0.039ms returns 0 +T714C 000:362.653 JLINK_GetDebugInfo(0x105 = JLINKARM_DEBUG_INFO_DWT_ADDR_INDEX) +T714C 000:362.669 Value=0xE0001000 +T714C 000:362.693 - 0.039ms returns 0 +T714C 000:362.710 JLINK_GetDebugInfo(0x106 = JLINKARM_DEBUG_INFO_FPB_ADDR_INDEX) +T714C 000:362.726 Value=0xE0002000 +T714C 000:362.749 - 0.039ms returns 0 +T714C 000:362.766 JLINK_GetDebugInfo(0x107 = JLINKARM_DEBUG_INFO_NVIC_ADDR_INDEX) +T714C 000:362.782 Value=0xE000E000 +T714C 000:362.805 - 0.039ms returns 0 +T714C 000:362.822 JLINK_GetDebugInfo(0x10C = JLINKARM_DEBUG_INFO_DBG_ADDR_INDEX) +T714C 000:362.837 Value=0xE000EDF0 +T714C 000:362.861 - 0.039ms returns 0 +T714C 000:362.877 JLINK_GetDebugInfo(0x01 = Unknown) +T714C 000:362.894 Value=0x00000001 +T714C 000:362.918 - 0.040ms returns 0 +T714C 000:362.934 JLINK_ReadMemU32(0xE000ED00, 0x1 Items) +T714C 000:362.953 CPU_ReadMem(4 bytes @ 0xE000ED00) +T714C 000:363.229 Data: 10 D2 1F 41 +T714C 000:363.259 Debug reg: CPUID +T714C 000:363.282 - 0.348ms returns 1 (0x1) +T714C 000:363.300 JLINK_GetDebugInfo(0x10F = JLINKARM_DEBUG_INFO_HAS_CORTEX_M_SECURITY_EXT_INDEX) +T714C 000:363.322 Value=0x00000001 +T714C 000:363.348 - 0.048ms returns 0 +T714C 000:363.365 JLINK_ReadMemU32(0xE000EFB8, 0x1 Items) +T714C 000:363.383 CPU_ReadMem(4 bytes @ 0xE000EFB8) +T714C 000:363.670 Data: FF 00 00 00 +T714C 000:363.700 - 0.335ms returns 1 (0x1) +T714C 000:363.718 JLINK_ReadMemU32(0xE000EDF0, 0x1 Items) +T714C 000:363.735 CPU_ReadMem(4 bytes @ 0xE000EDF0) +T714C 000:364.024 Data: 03 00 13 00 +T714C 000:364.052 Debug reg: DHCSR +T714C 000:364.076 - 0.358ms returns 1 (0x1) +T714C 000:364.094 JLINK_ReadMemU32(0xE000EE08, 0x1 Items) +T714C 000:364.112 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 000:364.380 Data: 00 00 03 00 +T714C 000:364.408 Debug reg: DSCSR +T714C 000:364.432 - 0.338ms returns 1 (0x1) +T714C 000:364.450 JLINK_ReadMemEx(0xE000ED74, 0x4 Bytes, Flags = 0x02000004) +T714C 000:364.468 CPU_ReadMem(4 bytes @ 0xE000ED74) +T714C 000:364.739 Data: 00 00 00 00 +T714C 000:364.768 - 0.318ms returns 4 (0x4) +T714C 000:368.298 JLINK_HasError() +T714C 000:368.372 JLINK_SetResetType(JLINKARM_CM3_RESET_TYPE_NORMAL) +T714C 000:368.391 - 0.018ms returns JLINKARM_CM3_RESET_TYPE_NORMAL +T714C 000:368.408 JLINK_Reset() +T714C 000:370.069 ResetTarget() start +T714C 000:370.125 J-Link Script File: Executing ResetTarget() +T714C 000:372.016 Skipping ResetTarget() +T714C 000:373.617 ResetTarget() end - Took 1.94ms +T714C 000:376.120 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 000:376.434 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 000:376.676 CPU_ReadMem(4 bytes @ 0xE000EDFC) +T714C 000:376.930 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 000:377.152 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 000:377.380 - 8.972ms +T714C 000:377.412 JLINK_Halt() +T714C 000:377.429 - 0.017ms returns 0x00 +T714C 000:377.447 JLINK_ReadMemU32(0xE000EFB8, 0x1 Items) +T714C 000:377.468 CPU_ReadMem(4 bytes @ 0xE000EFB8) +T714C 000:377.707 Data: FF 00 00 00 +T714C 000:377.736 - 0.289ms returns 1 (0x1) +T714C 000:377.754 JLINK_ReadMemU32(0xE000EDF0, 0x1 Items) +T714C 000:377.771 CPU_ReadMem(4 bytes @ 0xE000EDF0) +T714C 000:378.028 Data: 03 00 13 00 +T714C 000:378.055 Debug reg: DHCSR +T714C 000:378.080 - 0.325ms returns 1 (0x1) +T714C 000:378.098 JLINK_ReadMemU32(0xE000EDF0, 0x1 Items) +T714C 000:378.115 CPU_ReadMem(4 bytes @ 0xE000EDF0) +T714C 000:378.311 Data: 03 00 13 00 +T714C 000:378.338 Debug reg: DHCSR +T714C 000:378.361 - 0.263ms returns 1 (0x1) +T714C 000:378.379 JLINK_WriteU32_64(0xE000EDF0, 0xA05F0003) +T714C 000:378.395 Debug reg: DHCSR +T714C 000:378.687 CPU_WriteMem(4 bytes @ 0xE000EDF0) +T714C 000:379.015 - 0.635ms returns 0 (0x00000000) +T714C 000:379.040 JLINK_WriteU32_64(0xE000EDFC, 0x01000000) +T714C 000:379.056 Debug reg: DEMCR +T714C 000:379.082 CPU_WriteMem(4 bytes @ 0xE000EDFC) +T714C 000:379.335 - 0.294ms returns 0 (0x00000000) +T714C 000:385.932 JLINK_GetHWStatus(...) +T714C 000:386.229 - 0.305ms returns 0 +T714C 000:391.966 JLINK_GetNumBPUnits(Type = 0xFFFFFF00) +T714C 000:392.034 - 0.068ms returns 0x08 +T714C 000:392.053 JLINK_GetNumBPUnits(Type = 0xF0) +T714C 000:392.071 - 0.017ms returns 0x2000 +T714C 000:392.087 JLINK_GetNumWPUnits() +T714C 000:392.103 - 0.015ms returns 4 +T714C 000:396.530 JLINK_GetSpeed() +T714C 000:396.584 - 0.054ms returns 5000 +T714C 000:399.498 JLINK_ReadMemU32(0xE000E004, 0x1 Items) +T714C 000:399.562 CPU_ReadMem(4 bytes @ 0xE000E004) +T714C 000:399.884 Data: 07 00 00 00 +T714C 000:399.940 - 0.443ms returns 1 (0x1) +T714C 000:399.960 JLINK_ReadMemU32(0xE000E004, 0x1 Items) +T714C 000:399.981 CPU_ReadMem(4 bytes @ 0xE000E004) +T714C 000:400.231 Data: 07 00 00 00 +T714C 000:400.260 - 0.300ms returns 1 (0x1) +T714C 000:400.279 JLINK_WriteMemEx(0xE0001000, 0x0000001C Bytes, Flags = 0x02000004) +T714C 000:400.323 Data: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... +T714C 000:400.352 CPU_WriteMem(28 bytes @ 0xE0001000) +T714C 000:400.629 - 0.350ms returns 0x1C +T714C 000:400.654 JLINK_Halt() +T714C 000:400.670 - 0.015ms returns 0x00 +T714C 000:400.686 JLINK_IsHalted() +T714C 000:400.767 - 0.080ms returns TRUE +T714C 000:404.699 JLINK_WriteMem(0x30500000, 0x460 Bytes, ...) +T714C 000:404.746 Data: 00 BE 0A E0 0D 78 2D 06 68 40 08 24 40 00 00 D3 ... +T714C 000:405.146 CPU_WriteMem(1120 bytes @ 0x30500000) +T714C 000:408.723 - 4.023ms returns 0x460 +T714C 000:408.836 JLINK_HasError() +T714C 000:408.866 JLINK_WriteReg(R0, 0x28000000) +T714C 000:408.890 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 000:409.157 - 0.297ms returns 0 +T714C 000:409.179 JLINK_WriteReg(R1, 0x01F78A40) +T714C 000:409.197 - 0.017ms returns 0 +T714C 000:409.214 JLINK_WriteReg(R2, 0x00000001) +T714C 000:409.230 - 0.016ms returns 0 +T714C 000:409.247 JLINK_WriteReg(R3, 0x00000000) +T714C 000:409.263 - 0.016ms returns 0 +T714C 000:409.279 JLINK_WriteReg(R4, 0x00000000) +T714C 000:409.296 - 0.016ms returns 0 +T714C 000:409.312 JLINK_WriteReg(R5, 0x00000000) +T714C 000:409.329 - 0.017ms returns 0 +T714C 000:409.346 JLINK_WriteReg(R6, 0x00000000) +T714C 000:409.362 - 0.016ms returns 0 +T714C 000:409.379 JLINK_WriteReg(R7, 0x00000000) +T714C 000:409.395 - 0.016ms returns 0 +T714C 000:409.414 JLINK_WriteReg(R8, 0x00000000) +T714C 000:409.431 - 0.019ms returns 0 +T714C 000:409.448 JLINK_WriteReg(R9, 0x30500458) +T714C 000:409.464 - 0.015ms returns 0 +T714C 000:409.480 JLINK_WriteReg(R10, 0x00000000) +T714C 000:409.496 - 0.015ms returns 0 +T714C 000:409.512 JLINK_WriteReg(R11, 0x00000000) +T714C 000:409.528 - 0.015ms returns 0 +T714C 000:409.545 JLINK_WriteReg(R12, 0x00000000) +T714C 000:409.561 - 0.015ms returns 0 +T714C 000:409.577 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 000:409.594 - 0.017ms returns 0 +T714C 000:409.611 JLINK_WriteReg(R14, 0x30500001) +T714C 000:409.628 - 0.016ms returns 0 +T714C 000:409.647 JLINK_WriteReg(R15 (PC), 0x30500038) +T714C 000:409.664 - 0.018ms returns 0 +T714C 000:409.680 JLINK_WriteReg(XPSR, 0x01000000) +T714C 000:409.697 - 0.017ms returns 0 +T714C 000:409.713 JLINK_WriteReg(MSP, 0x30508000) +T714C 000:409.729 - 0.016ms returns 0 +T714C 000:409.746 JLINK_WriteReg(PSP, 0x30508000) +T714C 000:409.763 - 0.016ms returns 0 +T714C 000:409.788 JLINK_WriteReg(CFBP, 0x00000000) +T714C 000:409.805 - 0.017ms returns 0 +T714C 000:409.824 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 000:409.842 - 0.018ms returns 0x00000001 +T714C 000:409.861 JLINK_Go() +T714C 000:409.880 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 000:410.133 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 000:410.390 CPU_WriteMem(4 bytes @ 0xE0002008) +T714C 000:410.419 CPU_WriteMem(4 bytes @ 0xE000200C) +T714C 000:410.442 CPU_WriteMem(4 bytes @ 0xE0002010) +T714C 000:410.465 CPU_WriteMem(4 bytes @ 0xE0002014) +T714C 000:410.488 CPU_WriteMem(4 bytes @ 0xE0002018) +T714C 000:410.511 CPU_WriteMem(4 bytes @ 0xE000201C) +T714C 000:410.535 CPU_WriteMem(4 bytes @ 0xE0002020) +T714C 000:410.558 CPU_WriteMem(4 bytes @ 0xE0002024) +T714C 000:411.571 CPU_WriteMem(4 bytes @ 0xE0001004) +T714C 000:415.450 Memory map 'after startup completion point' is active +T714C 000:415.510 - 5.648ms +T714C 000:415.538 JLINK_IsHalted() +T714C 000:417.658 - 2.119ms returns TRUE +T714C 000:417.728 JLINK_ReadReg(R15 (PC)) +T714C 000:417.774 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 000:418.120 - 0.392ms returns 0x30500000 +T714C 000:418.149 JLINK_ClrBPEx(BPHandle = 0x00000001) +T714C 000:418.167 - 0.018ms returns 0x00 +T714C 000:418.187 JLINK_ReadReg(R0) +T714C 000:418.206 - 0.019ms returns 0x00000000 +T714C 000:418.836 JLINK_HasError() +T714C 000:418.888 JLINK_WriteReg(R0, 0x28000000) +T714C 000:418.910 - 0.022ms returns 0 +T714C 000:418.929 JLINK_WriteReg(R1, 0x00001000) +T714C 000:418.947 - 0.017ms returns 0 +T714C 000:418.965 JLINK_WriteReg(R2, 0x000000FF) +T714C 000:418.989 - 0.024ms returns 0 +T714C 000:419.017 JLINK_WriteReg(R3, 0x00000000) +T714C 000:419.047 - 0.030ms returns 0 +T714C 000:419.073 JLINK_WriteReg(R4, 0x00000000) +T714C 000:419.100 - 0.026ms returns 0 +T714C 000:419.119 JLINK_WriteReg(R5, 0x00000000) +T714C 000:419.186 - 0.065ms returns 0 +T714C 000:419.208 JLINK_WriteReg(R6, 0x00000000) +T714C 000:419.227 - 0.018ms returns 0 +T714C 000:419.252 JLINK_WriteReg(R7, 0x00000000) +T714C 000:419.269 - 0.017ms returns 0 +T714C 000:419.287 JLINK_WriteReg(R8, 0x00000000) +T714C 000:419.303 - 0.016ms returns 0 +T714C 000:419.320 JLINK_WriteReg(R9, 0x30500458) +T714C 000:419.337 - 0.016ms returns 0 +T714C 000:419.362 JLINK_WriteReg(R10, 0x00000000) +T714C 000:419.379 - 0.016ms returns 0 +T714C 000:419.395 JLINK_WriteReg(R11, 0x00000000) +T714C 000:419.412 - 0.016ms returns 0 +T714C 000:419.429 JLINK_WriteReg(R12, 0x00000000) +T714C 000:419.446 - 0.016ms returns 0 +T714C 000:419.463 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 000:419.480 - 0.017ms returns 0 +T714C 000:419.496 JLINK_WriteReg(R14, 0x30500001) +T714C 000:419.520 - 0.023ms returns 0 +T714C 000:419.567 JLINK_WriteReg(R15 (PC), 0x30500020) +T714C 000:419.600 - 0.033ms returns 0 +T714C 000:419.619 JLINK_WriteReg(XPSR, 0x01000000) +T714C 000:419.636 - 0.017ms returns 0 +T714C 000:419.653 JLINK_WriteReg(MSP, 0x30508000) +T714C 000:419.670 - 0.016ms returns 0 +T714C 000:419.688 JLINK_WriteReg(PSP, 0x30508000) +T714C 000:419.704 - 0.016ms returns 0 +T714C 000:419.722 JLINK_WriteReg(CFBP, 0x00000000) +T714C 000:419.738 - 0.016ms returns 0 +T714C 000:419.766 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 000:419.784 - 0.018ms returns 0x00000002 +T714C 000:419.801 JLINK_Go() +T714C 000:419.821 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 000:420.163 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 000:422.258 - 2.457ms +T714C 000:422.298 JLINK_IsHalted() +T714C 000:422.595 - 0.297ms returns FALSE +T714C 000:422.623 JLINK_HasError() +T714C 000:432.381 JLINK_IsHalted() +T714C 000:435.065 - 2.676ms returns TRUE +T714C 000:435.489 JLINK_ReadReg(R15 (PC)) +T714C 000:435.578 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 000:436.342 - 0.851ms returns 0x30500000 +T714C 000:436.391 JLINK_ClrBPEx(BPHandle = 0x00000002) +T714C 000:436.420 - 0.029ms returns 0x00 +T714C 000:436.455 JLINK_ReadReg(R0) +T714C 000:436.482 - 0.028ms returns 0x00000001 +T714C 000:436.511 JLINK_HasError() +T714C 000:436.537 JLINK_WriteReg(R0, 0x28000000) +T714C 000:436.565 - 0.027ms returns 0 +T714C 000:436.585 JLINK_WriteReg(R1, 0x00001000) +T714C 000:436.605 - 0.019ms returns 0 +T714C 000:436.622 JLINK_WriteReg(R2, 0x000000FF) +T714C 000:436.642 - 0.020ms returns 0 +T714C 000:436.661 JLINK_WriteReg(R3, 0x00000000) +T714C 000:436.681 - 0.019ms returns 0 +T714C 000:436.701 JLINK_WriteReg(R4, 0x00000000) +T714C 000:436.723 - 0.021ms returns 0 +T714C 000:436.742 JLINK_WriteReg(R5, 0x00000000) +T714C 000:436.762 - 0.019ms returns 0 +T714C 000:436.784 JLINK_WriteReg(R6, 0x00000000) +T714C 000:436.802 - 0.018ms returns 0 +T714C 000:436.820 JLINK_WriteReg(R7, 0x00000000) +T714C 000:436.840 - 0.020ms returns 0 +T714C 000:436.864 JLINK_WriteReg(R8, 0x00000000) +T714C 000:436.883 - 0.019ms returns 0 +T714C 000:436.902 JLINK_WriteReg(R9, 0x30500458) +T714C 000:436.920 - 0.018ms returns 0 +T714C 000:436.938 JLINK_WriteReg(R10, 0x00000000) +T714C 000:436.954 - 0.016ms returns 0 +T714C 000:436.972 JLINK_WriteReg(R11, 0x00000000) +T714C 000:436.988 - 0.015ms returns 0 +T714C 000:437.004 JLINK_WriteReg(R12, 0x00000000) +T714C 000:437.021 - 0.016ms returns 0 +T714C 000:437.038 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 000:437.057 - 0.019ms returns 0 +T714C 000:437.075 JLINK_WriteReg(R14, 0x30500001) +T714C 000:437.091 - 0.016ms returns 0 +T714C 000:437.108 JLINK_WriteReg(R15 (PC), 0x30500274) +T714C 000:437.124 - 0.016ms returns 0 +T714C 000:437.142 JLINK_WriteReg(XPSR, 0x01000000) +T714C 000:437.159 - 0.017ms returns 0 +T714C 000:437.176 JLINK_WriteReg(MSP, 0x30508000) +T714C 000:437.192 - 0.016ms returns 0 +T714C 000:437.209 JLINK_WriteReg(PSP, 0x30508000) +T714C 000:437.226 - 0.016ms returns 0 +T714C 000:437.242 JLINK_WriteReg(CFBP, 0x00000000) +T714C 000:437.258 - 0.016ms returns 0 +T714C 000:437.276 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 000:437.293 - 0.017ms returns 0x00000003 +T714C 000:437.310 JLINK_Go() +T714C 000:437.329 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 000:437.621 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 000:439.598 - 2.287ms +T714C 000:439.654 JLINK_IsHalted() +T714C 000:439.932 - 0.277ms returns FALSE +T714C 000:439.955 JLINK_HasError() +T714C 000:441.269 JLINK_IsHalted() +T714C 000:441.620 - 0.350ms returns FALSE +T714C 000:441.643 JLINK_HasError() +T714C 000:443.218 JLINK_IsHalted() +T714C 000:443.688 - 0.472ms returns FALSE +T714C 000:443.746 JLINK_HasError() +T714C 000:445.297 JLINK_IsHalted() +T714C 000:445.652 - 0.354ms returns FALSE +T714C 000:445.688 JLINK_HasError() +T714C 000:447.215 JLINK_IsHalted() +T714C 000:447.666 - 0.451ms returns FALSE +T714C 000:447.687 JLINK_HasError() +T714C 000:449.193 JLINK_IsHalted() +T714C 000:449.556 - 0.362ms returns FALSE +T714C 000:449.625 JLINK_HasError() +T714C 000:451.480 JLINK_IsHalted() +T714C 000:451.779 - 0.298ms returns FALSE +T714C 000:451.809 JLINK_HasError() +T714C 000:453.435 JLINK_IsHalted() +T714C 000:453.762 - 0.326ms returns FALSE +T714C 000:453.841 JLINK_HasError() +T714C 000:454.939 JLINK_IsHalted() +T714C 000:455.238 - 0.299ms returns FALSE +T714C 000:455.267 JLINK_HasError() +T714C 000:456.968 JLINK_IsHalted() +T714C 000:457.233 - 0.264ms returns FALSE +T714C 000:457.273 JLINK_HasError() +T714C 000:459.016 JLINK_IsHalted() +T714C 000:459.314 - 0.298ms returns FALSE +T714C 000:459.336 JLINK_HasError() +T714C 000:461.015 JLINK_IsHalted() +T714C 000:461.256 - 0.243ms returns FALSE +T714C 000:461.278 JLINK_HasError() +T714C 000:463.014 JLINK_IsHalted() +T714C 000:463.270 - 0.255ms returns FALSE +T714C 000:463.290 JLINK_HasError() +T714C 000:464.987 JLINK_IsHalted() +T714C 000:465.290 - 0.303ms returns FALSE +T714C 000:465.316 JLINK_HasError() +T714C 000:466.993 JLINK_IsHalted() +T714C 000:467.290 - 0.296ms returns FALSE +T714C 000:467.313 JLINK_HasError() +T714C 000:468.983 JLINK_IsHalted() +T714C 000:469.229 - 0.246ms returns FALSE +T714C 000:469.251 JLINK_HasError() +T714C 000:471.015 JLINK_IsHalted() +T714C 000:471.288 - 0.273ms returns FALSE +T714C 000:471.310 JLINK_HasError() +T714C 000:473.012 JLINK_IsHalted() +T714C 000:473.287 - 0.277ms returns FALSE +T714C 000:473.307 JLINK_HasError() +T714C 000:475.008 JLINK_IsHalted() +T714C 000:475.289 - 0.281ms returns FALSE +T714C 000:475.313 JLINK_HasError() +T714C 000:477.003 JLINK_IsHalted() +T714C 000:477.242 - 0.238ms returns FALSE +T714C 000:477.268 JLINK_HasError() +T714C 000:478.987 JLINK_IsHalted() +T714C 000:479.391 - 0.403ms returns FALSE +T714C 000:479.439 JLINK_HasError() +T714C 000:480.961 JLINK_IsHalted() +T714C 000:481.347 - 0.386ms returns FALSE +T714C 000:481.384 JLINK_HasError() +T714C 000:483.011 JLINK_IsHalted() +T714C 000:483.343 - 0.332ms returns FALSE +T714C 000:483.376 JLINK_HasError() +T714C 000:485.003 JLINK_IsHalted() +T714C 000:485.291 - 0.287ms returns FALSE +T714C 000:485.316 JLINK_HasError() +T714C 000:487.002 JLINK_IsHalted() +T714C 000:489.274 - 2.273ms returns TRUE +T714C 000:489.315 JLINK_ReadReg(R15 (PC)) +T714C 000:489.347 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 000:489.638 - 0.323ms returns 0x30500000 +T714C 000:489.675 JLINK_ClrBPEx(BPHandle = 0x00000003) +T714C 000:489.705 - 0.029ms returns 0x00 +T714C 000:489.737 JLINK_ReadReg(R0) +T714C 000:489.765 - 0.028ms returns 0x00000000 +T714C 000:490.748 JLINK_HasError() +T714C 000:490.812 JLINK_WriteReg(R0, 0x28001000) +T714C 000:490.844 - 0.032ms returns 0 +T714C 000:490.870 JLINK_WriteReg(R1, 0x00001000) +T714C 000:490.894 - 0.024ms returns 0 +T714C 000:490.918 JLINK_WriteReg(R2, 0x000000FF) +T714C 000:490.942 - 0.024ms returns 0 +T714C 000:490.967 JLINK_WriteReg(R3, 0x00000000) +T714C 000:490.991 - 0.024ms returns 0 +T714C 000:491.022 JLINK_WriteReg(R4, 0x00000000) +T714C 000:491.046 - 0.024ms returns 0 +T714C 000:491.071 JLINK_WriteReg(R5, 0x00000000) +T714C 000:491.095 - 0.023ms returns 0 +T714C 000:491.120 JLINK_WriteReg(R6, 0x00000000) +T714C 000:491.144 - 0.024ms returns 0 +T714C 000:491.166 JLINK_WriteReg(R7, 0x00000000) +T714C 000:491.187 - 0.021ms returns 0 +T714C 000:491.209 JLINK_WriteReg(R8, 0x00000000) +T714C 000:491.230 - 0.021ms returns 0 +T714C 000:491.253 JLINK_WriteReg(R9, 0x30500458) +T714C 000:491.281 - 0.028ms returns 0 +T714C 000:491.306 JLINK_WriteReg(R10, 0x00000000) +T714C 000:491.328 - 0.021ms returns 0 +T714C 000:491.349 JLINK_WriteReg(R11, 0x00000000) +T714C 000:491.388 - 0.039ms returns 0 +T714C 000:491.409 JLINK_WriteReg(R12, 0x00000000) +T714C 000:491.429 - 0.020ms returns 0 +T714C 000:491.450 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 000:491.471 - 0.021ms returns 0 +T714C 000:491.493 JLINK_WriteReg(R14, 0x30500001) +T714C 000:491.513 - 0.020ms returns 0 +T714C 000:491.533 JLINK_WriteReg(R15 (PC), 0x30500020) +T714C 000:491.553 - 0.020ms returns 0 +T714C 000:491.574 JLINK_WriteReg(XPSR, 0x01000000) +T714C 000:491.595 - 0.021ms returns 0 +T714C 000:491.617 JLINK_WriteReg(MSP, 0x30508000) +T714C 000:491.636 - 0.018ms returns 0 +T714C 000:491.655 JLINK_WriteReg(PSP, 0x30508000) +T714C 000:491.674 - 0.019ms returns 0 +T714C 000:491.692 JLINK_WriteReg(CFBP, 0x00000000) +T714C 000:491.711 - 0.018ms returns 0 +T714C 000:491.731 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 000:491.750 - 0.019ms returns 0x00000004 +T714C 000:491.768 JLINK_Go() +T714C 000:491.789 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 000:492.097 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 000:494.024 - 2.255ms +T714C 000:494.208 JLINK_IsHalted() +T714C 000:496.495 - 2.287ms returns TRUE +T714C 000:496.548 JLINK_ReadReg(R15 (PC)) +T714C 000:496.569 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 000:496.816 - 0.269ms returns 0x30500000 +T714C 000:496.842 JLINK_ClrBPEx(BPHandle = 0x00000004) +T714C 000:496.860 - 0.018ms returns 0x00 +T714C 000:496.879 JLINK_ReadReg(R0) +T714C 000:496.898 - 0.019ms returns 0x00000001 +T714C 000:496.918 JLINK_HasError() +T714C 000:496.940 JLINK_WriteReg(R0, 0x28001000) +T714C 000:496.958 - 0.018ms returns 0 +T714C 000:496.977 JLINK_WriteReg(R1, 0x00001000) +T714C 000:496.995 - 0.017ms returns 0 +T714C 000:497.013 JLINK_WriteReg(R2, 0x000000FF) +T714C 000:497.031 - 0.017ms returns 0 +T714C 000:497.049 JLINK_WriteReg(R3, 0x00000000) +T714C 000:497.067 - 0.017ms returns 0 +T714C 000:497.085 JLINK_WriteReg(R4, 0x00000000) +T714C 000:497.102 - 0.017ms returns 0 +T714C 000:497.120 JLINK_WriteReg(R5, 0x00000000) +T714C 000:497.138 - 0.017ms returns 0 +T714C 000:497.156 JLINK_WriteReg(R6, 0x00000000) +T714C 000:497.173 - 0.017ms returns 0 +T714C 000:497.191 JLINK_WriteReg(R7, 0x00000000) +T714C 000:497.208 - 0.017ms returns 0 +T714C 000:497.226 JLINK_WriteReg(R8, 0x00000000) +T714C 000:497.244 - 0.017ms returns 0 +T714C 000:497.262 JLINK_WriteReg(R9, 0x30500458) +T714C 000:497.280 - 0.017ms returns 0 +T714C 000:497.298 JLINK_WriteReg(R10, 0x00000000) +T714C 000:497.315 - 0.017ms returns 0 +T714C 000:497.334 JLINK_WriteReg(R11, 0x00000000) +T714C 000:497.351 - 0.017ms returns 0 +T714C 000:497.369 JLINK_WriteReg(R12, 0x00000000) +T714C 000:497.387 - 0.018ms returns 0 +T714C 000:497.406 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 000:497.424 - 0.018ms returns 0 +T714C 000:497.442 JLINK_WriteReg(R14, 0x30500001) +T714C 000:497.460 - 0.017ms returns 0 +T714C 000:497.479 JLINK_WriteReg(R15 (PC), 0x30500274) +T714C 000:497.496 - 0.017ms returns 0 +T714C 000:497.516 JLINK_WriteReg(XPSR, 0x01000000) +T714C 000:497.533 - 0.018ms returns 0 +T714C 000:497.553 JLINK_WriteReg(MSP, 0x30508000) +T714C 000:497.570 - 0.017ms returns 0 +T714C 000:497.589 JLINK_WriteReg(PSP, 0x30508000) +T714C 000:497.605 - 0.016ms returns 0 +T714C 000:497.625 JLINK_WriteReg(CFBP, 0x00000000) +T714C 000:497.642 - 0.017ms returns 0 +T714C 000:497.661 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 000:497.679 - 0.017ms returns 0x00000005 +T714C 000:497.697 JLINK_Go() +T714C 000:497.717 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 000:497.980 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 000:499.878 - 2.180ms +T714C 000:499.925 JLINK_IsHalted() +T714C 000:500.223 - 0.297ms returns FALSE +T714C 000:500.278 JLINK_HasError() +T714C 000:501.990 JLINK_IsHalted() +T714C 000:502.264 - 0.272ms returns FALSE +T714C 000:502.295 JLINK_HasError() +T714C 000:504.047 JLINK_IsHalted() +T714C 000:504.394 - 0.347ms returns FALSE +T714C 000:504.419 JLINK_HasError() +T714C 000:506.007 JLINK_IsHalted() +T714C 000:506.225 - 0.217ms returns FALSE +T714C 000:506.246 JLINK_HasError() +T714C 000:507.950 JLINK_IsHalted() +T714C 000:508.226 - 0.276ms returns FALSE +T714C 000:508.253 JLINK_HasError() +T714C 000:509.960 JLINK_IsHalted() +T714C 000:510.322 - 0.361ms returns FALSE +T714C 000:510.357 JLINK_HasError() +T714C 000:514.957 JLINK_IsHalted() +T714C 000:515.346 - 0.388ms returns FALSE +T714C 000:515.376 JLINK_HasError() +T714C 000:520.987 JLINK_IsHalted() +T714C 000:521.301 - 0.313ms returns FALSE +T714C 000:521.326 JLINK_HasError() +T714C 000:524.496 JLINK_IsHalted() +T714C 000:524.808 - 0.311ms returns FALSE +T714C 000:524.854 JLINK_HasError() +T714C 000:568.690 JLINK_IsHalted() +T714C 000:570.989 - 2.298ms returns TRUE +T714C 000:571.099 JLINK_ReadReg(R15 (PC)) +T714C 000:571.126 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 000:571.446 - 0.346ms returns 0x30500000 +T714C 000:571.480 JLINK_ClrBPEx(BPHandle = 0x00000005) +T714C 000:571.498 - 0.017ms returns 0x00 +T714C 000:571.517 JLINK_ReadReg(R0) +T714C 000:571.553 - 0.036ms returns 0x00000000 +T714C 000:572.367 JLINK_HasError() +T714C 000:572.423 JLINK_WriteReg(R0, 0x2800B000) +T714C 000:572.445 - 0.022ms returns 0 +T714C 000:572.463 JLINK_WriteReg(R1, 0x00001000) +T714C 000:572.479 - 0.016ms returns 0 +T714C 000:572.496 JLINK_WriteReg(R2, 0x000000FF) +T714C 000:572.513 - 0.017ms returns 0 +T714C 000:572.557 JLINK_WriteReg(R3, 0x00000000) +T714C 000:572.574 - 0.017ms returns 0 +T714C 000:572.591 JLINK_WriteReg(R4, 0x00000000) +T714C 000:572.608 - 0.016ms returns 0 +T714C 000:572.625 JLINK_WriteReg(R5, 0x00000000) +T714C 000:572.642 - 0.016ms returns 0 +T714C 000:572.659 JLINK_WriteReg(R6, 0x00000000) +T714C 000:572.675 - 0.016ms returns 0 +T714C 000:572.692 JLINK_WriteReg(R7, 0x00000000) +T714C 000:572.708 - 0.016ms returns 0 +T714C 000:572.725 JLINK_WriteReg(R8, 0x00000000) +T714C 000:572.742 - 0.016ms returns 0 +T714C 000:572.759 JLINK_WriteReg(R9, 0x30500458) +T714C 000:572.792 - 0.032ms returns 0 +T714C 000:572.809 JLINK_WriteReg(R10, 0x00000000) +T714C 000:572.826 - 0.017ms returns 0 +T714C 000:572.843 JLINK_WriteReg(R11, 0x00000000) +T714C 000:572.859 - 0.016ms returns 0 +T714C 000:572.876 JLINK_WriteReg(R12, 0x00000000) +T714C 000:572.894 - 0.017ms returns 0 +T714C 000:572.912 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 000:572.931 - 0.019ms returns 0 +T714C 000:572.948 JLINK_WriteReg(R14, 0x30500001) +T714C 000:572.966 - 0.017ms returns 0 +T714C 000:572.984 JLINK_WriteReg(R15 (PC), 0x30500020) +T714C 000:573.001 - 0.017ms returns 0 +T714C 000:573.032 JLINK_WriteReg(XPSR, 0x01000000) +T714C 000:573.050 - 0.017ms returns 0 +T714C 000:573.068 JLINK_WriteReg(MSP, 0x30508000) +T714C 000:573.085 - 0.017ms returns 0 +T714C 000:573.103 JLINK_WriteReg(PSP, 0x30508000) +T714C 000:573.120 - 0.017ms returns 0 +T714C 000:573.138 JLINK_WriteReg(CFBP, 0x00000000) +T714C 000:573.156 - 0.017ms returns 0 +T714C 000:573.183 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 000:573.202 - 0.019ms returns 0x00000006 +T714C 000:573.220 JLINK_Go() +T714C 000:573.240 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 000:573.603 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 000:575.607 - 2.386ms +T714C 000:575.661 JLINK_IsHalted() +T714C 000:577.805 - 2.143ms returns TRUE +T714C 000:577.839 JLINK_ReadReg(R15 (PC)) +T714C 000:577.862 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 000:578.112 - 0.272ms returns 0x30500000 +T714C 000:578.134 JLINK_ClrBPEx(BPHandle = 0x00000006) +T714C 000:578.152 - 0.017ms returns 0x00 +T714C 000:578.169 JLINK_ReadReg(R0) +T714C 000:578.186 - 0.018ms returns 0x00000001 +T714C 000:578.205 JLINK_HasError() +T714C 000:578.222 JLINK_WriteReg(R0, 0x2800B000) +T714C 000:578.239 - 0.016ms returns 0 +T714C 000:578.255 JLINK_WriteReg(R1, 0x00001000) +T714C 000:578.272 - 0.016ms returns 0 +T714C 000:578.288 JLINK_WriteReg(R2, 0x000000FF) +T714C 000:578.304 - 0.015ms returns 0 +T714C 000:578.320 JLINK_WriteReg(R3, 0x00000000) +T714C 000:578.335 - 0.015ms returns 0 +T714C 000:578.352 JLINK_WriteReg(R4, 0x00000000) +T714C 000:578.372 - 0.020ms returns 0 +T714C 000:578.391 JLINK_WriteReg(R5, 0x00000000) +T714C 000:578.407 - 0.015ms returns 0 +T714C 000:578.423 JLINK_WriteReg(R6, 0x00000000) +T714C 000:578.439 - 0.016ms returns 0 +T714C 000:578.456 JLINK_WriteReg(R7, 0x00000000) +T714C 000:578.472 - 0.016ms returns 0 +T714C 000:578.488 JLINK_WriteReg(R8, 0x00000000) +T714C 000:578.504 - 0.015ms returns 0 +T714C 000:578.520 JLINK_WriteReg(R9, 0x30500458) +T714C 000:578.535 - 0.015ms returns 0 +T714C 000:578.553 JLINK_WriteReg(R10, 0x00000000) +T714C 000:578.569 - 0.016ms returns 0 +T714C 000:578.585 JLINK_WriteReg(R11, 0x00000000) +T714C 000:578.601 - 0.015ms returns 0 +T714C 000:578.617 JLINK_WriteReg(R12, 0x00000000) +T714C 000:578.633 - 0.016ms returns 0 +T714C 000:578.649 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 000:578.666 - 0.016ms returns 0 +T714C 000:578.682 JLINK_WriteReg(R14, 0x30500001) +T714C 000:578.698 - 0.015ms returns 0 +T714C 000:578.714 JLINK_WriteReg(R15 (PC), 0x30500274) +T714C 000:578.731 - 0.017ms returns 0 +T714C 000:578.748 JLINK_WriteReg(XPSR, 0x01000000) +T714C 000:578.764 - 0.015ms returns 0 +T714C 000:578.781 JLINK_WriteReg(MSP, 0x30508000) +T714C 000:578.797 - 0.016ms returns 0 +T714C 000:578.814 JLINK_WriteReg(PSP, 0x30508000) +T714C 000:578.830 - 0.016ms returns 0 +T714C 000:578.847 JLINK_WriteReg(CFBP, 0x00000000) +T714C 000:578.863 - 0.016ms returns 0 +T714C 000:578.879 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 000:578.896 - 0.017ms returns 0x00000007 +T714C 000:578.913 JLINK_Go() +T714C 000:578.931 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 000:579.182 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 000:581.039 - 2.125ms +T714C 000:581.737 JLINK_IsHalted() +T714C 000:581.985 - 0.247ms returns FALSE +T714C 000:582.008 JLINK_HasError() +T714C 000:592.446 JLINK_IsHalted() +T714C 000:592.795 - 0.348ms returns FALSE +T714C 000:592.823 JLINK_HasError() +T714C 000:595.486 JLINK_IsHalted() +T714C 000:595.824 - 0.338ms returns FALSE +T714C 000:595.849 JLINK_HasError() +T714C 000:597.437 JLINK_IsHalted() +T714C 000:597.715 - 0.277ms returns FALSE +T714C 000:597.738 JLINK_HasError() +T714C 000:600.440 JLINK_IsHalted() +T714C 000:600.767 - 0.326ms returns FALSE +T714C 000:600.897 JLINK_HasError() +T714C 000:603.455 JLINK_IsHalted() +T714C 000:603.794 - 0.339ms returns FALSE +T714C 000:603.821 JLINK_HasError() +T714C 000:606.457 JLINK_IsHalted() +T714C 000:606.841 - 0.383ms returns FALSE +T714C 000:606.901 JLINK_HasError() +T714C 000:609.460 JLINK_IsHalted() +T714C 000:609.793 - 0.332ms returns FALSE +T714C 000:609.819 JLINK_HasError() +T714C 000:613.465 JLINK_IsHalted() +T714C 000:613.836 - 0.370ms returns FALSE +T714C 000:613.887 JLINK_HasError() +T714C 000:620.428 JLINK_IsHalted() +T714C 000:620.874 - 0.444ms returns FALSE +T714C 000:620.940 JLINK_HasError() +T714C 000:628.971 JLINK_IsHalted() +T714C 000:629.302 - 0.330ms returns FALSE +T714C 000:629.327 JLINK_HasError() +T714C 000:643.998 JLINK_IsHalted() +T714C 000:646.340 - 2.341ms returns TRUE +T714C 000:646.420 JLINK_ReadReg(R15 (PC)) +T714C 000:646.445 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 000:646.724 - 0.304ms returns 0x30500000 +T714C 000:646.760 JLINK_ClrBPEx(BPHandle = 0x00000007) +T714C 000:646.798 - 0.037ms returns 0x00 +T714C 000:646.816 JLINK_ReadReg(R0) +T714C 000:646.834 - 0.018ms returns 0x00000000 +T714C 000:647.591 JLINK_HasError() +T714C 000:647.639 JLINK_WriteReg(R0, 0x2800C000) +T714C 000:647.661 - 0.021ms returns 0 +T714C 000:647.678 JLINK_WriteReg(R1, 0x00001000) +T714C 000:647.695 - 0.016ms returns 0 +T714C 000:647.712 JLINK_WriteReg(R2, 0x000000FF) +T714C 000:647.728 - 0.016ms returns 0 +T714C 000:647.745 JLINK_WriteReg(R3, 0x00000000) +T714C 000:647.781 - 0.036ms returns 0 +T714C 000:647.800 JLINK_WriteReg(R4, 0x00000000) +T714C 000:647.816 - 0.016ms returns 0 +T714C 000:647.833 JLINK_WriteReg(R5, 0x00000000) +T714C 000:647.850 - 0.016ms returns 0 +T714C 000:647.866 JLINK_WriteReg(R6, 0x00000000) +T714C 000:647.883 - 0.016ms returns 0 +T714C 000:647.900 JLINK_WriteReg(R7, 0x00000000) +T714C 000:647.916 - 0.016ms returns 0 +T714C 000:647.938 JLINK_WriteReg(R8, 0x00000000) +T714C 000:647.957 - 0.018ms returns 0 +T714C 000:647.975 JLINK_WriteReg(R9, 0x30500458) +T714C 000:647.991 - 0.016ms returns 0 +T714C 000:648.008 JLINK_WriteReg(R10, 0x00000000) +T714C 000:648.039 - 0.031ms returns 0 +T714C 000:648.056 JLINK_WriteReg(R11, 0x00000000) +T714C 000:648.073 - 0.017ms returns 0 +T714C 000:648.090 JLINK_WriteReg(R12, 0x00000000) +T714C 000:648.108 - 0.017ms returns 0 +T714C 000:648.125 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 000:648.143 - 0.018ms returns 0 +T714C 000:648.159 JLINK_WriteReg(R14, 0x30500001) +T714C 000:648.176 - 0.016ms returns 0 +T714C 000:648.193 JLINK_WriteReg(R15 (PC), 0x30500020) +T714C 000:648.209 - 0.016ms returns 0 +T714C 000:648.226 JLINK_WriteReg(XPSR, 0x01000000) +T714C 000:648.243 - 0.016ms returns 0 +T714C 000:648.259 JLINK_WriteReg(MSP, 0x30508000) +T714C 000:648.290 - 0.030ms returns 0 +T714C 000:648.308 JLINK_WriteReg(PSP, 0x30508000) +T714C 000:648.332 - 0.023ms returns 0 +T714C 000:648.349 JLINK_WriteReg(CFBP, 0x00000000) +T714C 000:648.366 - 0.017ms returns 0 +T714C 000:648.383 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 000:648.401 - 0.017ms returns 0x00000008 +T714C 000:648.417 JLINK_Go() +T714C 000:648.438 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 000:648.793 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 000:650.851 - 2.433ms +T714C 000:650.949 JLINK_IsHalted() +T714C 000:653.191 - 2.241ms returns TRUE +T714C 000:653.234 JLINK_ReadReg(R15 (PC)) +T714C 000:653.260 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 000:653.595 - 0.361ms returns 0x30500000 +T714C 000:653.624 JLINK_ClrBPEx(BPHandle = 0x00000008) +T714C 000:653.643 - 0.018ms returns 0x00 +T714C 000:653.660 JLINK_ReadReg(R0) +T714C 000:653.677 - 0.017ms returns 0x00000001 +T714C 000:653.695 JLINK_HasError() +T714C 000:653.712 JLINK_WriteReg(R0, 0x2800C000) +T714C 000:653.731 - 0.019ms returns 0 +T714C 000:653.748 JLINK_WriteReg(R1, 0x00001000) +T714C 000:653.765 - 0.016ms returns 0 +T714C 000:653.782 JLINK_WriteReg(R2, 0x000000FF) +T714C 000:653.799 - 0.016ms returns 0 +T714C 000:653.815 JLINK_WriteReg(R3, 0x00000000) +T714C 000:653.831 - 0.015ms returns 0 +T714C 000:653.848 JLINK_WriteReg(R4, 0x00000000) +T714C 000:653.865 - 0.016ms returns 0 +T714C 000:653.881 JLINK_WriteReg(R5, 0x00000000) +T714C 000:653.897 - 0.016ms returns 0 +T714C 000:653.913 JLINK_WriteReg(R6, 0x00000000) +T714C 000:653.929 - 0.016ms returns 0 +T714C 000:653.946 JLINK_WriteReg(R7, 0x00000000) +T714C 000:653.962 - 0.015ms returns 0 +T714C 000:653.978 JLINK_WriteReg(R8, 0x00000000) +T714C 000:653.994 - 0.016ms returns 0 +T714C 000:654.011 JLINK_WriteReg(R9, 0x30500458) +T714C 000:654.027 - 0.016ms returns 0 +T714C 000:654.044 JLINK_WriteReg(R10, 0x00000000) +T714C 000:654.060 - 0.016ms returns 0 +T714C 000:654.077 JLINK_WriteReg(R11, 0x00000000) +T714C 000:654.093 - 0.015ms returns 0 +T714C 000:654.109 JLINK_WriteReg(R12, 0x00000000) +T714C 000:654.125 - 0.016ms returns 0 +T714C 000:654.142 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 000:654.159 - 0.016ms returns 0 +T714C 000:654.175 JLINK_WriteReg(R14, 0x30500001) +T714C 000:654.192 - 0.016ms returns 0 +T714C 000:654.208 JLINK_WriteReg(R15 (PC), 0x30500274) +T714C 000:654.224 - 0.016ms returns 0 +T714C 000:654.241 JLINK_WriteReg(XPSR, 0x01000000) +T714C 000:654.256 - 0.015ms returns 0 +T714C 000:654.272 JLINK_WriteReg(MSP, 0x30508000) +T714C 000:654.288 - 0.016ms returns 0 +T714C 000:654.305 JLINK_WriteReg(PSP, 0x30508000) +T714C 000:654.321 - 0.016ms returns 0 +T714C 000:654.338 JLINK_WriteReg(CFBP, 0x00000000) +T714C 000:654.353 - 0.015ms returns 0 +T714C 000:654.370 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 000:654.387 - 0.017ms returns 0x00000009 +T714C 000:654.404 JLINK_Go() +T714C 000:654.422 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 000:654.679 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 000:656.461 - 2.056ms +T714C 000:656.503 JLINK_IsHalted() +T714C 000:656.742 - 0.238ms returns FALSE +T714C 000:656.763 JLINK_HasError() +T714C 000:660.341 JLINK_IsHalted() +T714C 000:660.657 - 0.315ms returns FALSE +T714C 000:660.701 JLINK_HasError() +T714C 000:666.858 JLINK_IsHalted() +T714C 000:667.164 - 0.305ms returns FALSE +T714C 000:667.194 JLINK_HasError() +T714C 000:669.851 JLINK_IsHalted() +T714C 000:670.154 - 0.302ms returns FALSE +T714C 000:670.179 JLINK_HasError() +T714C 000:674.848 JLINK_IsHalted() +T714C 000:675.157 - 0.307ms returns FALSE +T714C 000:675.189 JLINK_HasError() +T714C 000:677.849 JLINK_IsHalted() +T714C 000:678.156 - 0.306ms returns FALSE +T714C 000:678.184 JLINK_HasError() +T714C 000:682.352 JLINK_IsHalted() +T714C 000:682.657 - 0.305ms returns FALSE +T714C 000:682.691 JLINK_HasError() +T714C 000:685.365 JLINK_IsHalted() +T714C 000:685.659 - 0.294ms returns FALSE +T714C 000:685.684 JLINK_HasError() +T714C 000:688.344 JLINK_IsHalted() +T714C 000:688.600 - 0.255ms returns FALSE +T714C 000:688.624 JLINK_HasError() +T714C 000:693.369 JLINK_IsHalted() +T714C 000:693.705 - 0.336ms returns FALSE +T714C 000:693.736 JLINK_HasError() +T714C 000:699.356 JLINK_IsHalted() +T714C 000:699.694 - 0.337ms returns FALSE +T714C 000:699.736 JLINK_HasError() +T714C 000:702.348 JLINK_IsHalted() +T714C 000:702.687 - 0.338ms returns FALSE +T714C 000:702.724 JLINK_HasError() +T714C 000:705.350 JLINK_IsHalted() +T714C 000:707.707 - 2.356ms returns TRUE +T714C 000:707.823 JLINK_ReadReg(R15 (PC)) +T714C 000:707.853 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 000:708.125 - 0.301ms returns 0x30500000 +T714C 000:708.179 JLINK_ClrBPEx(BPHandle = 0x00000009) +T714C 000:708.197 - 0.018ms returns 0x00 +T714C 000:708.215 JLINK_ReadReg(R0) +T714C 000:708.233 - 0.018ms returns 0x00000000 +T714C 000:708.936 JLINK_HasError() +T714C 000:708.980 JLINK_WriteReg(R0, 0x2800D000) +T714C 000:709.001 - 0.021ms returns 0 +T714C 000:709.019 JLINK_WriteReg(R1, 0x00001000) +T714C 000:709.035 - 0.016ms returns 0 +T714C 000:709.052 JLINK_WriteReg(R2, 0x000000FF) +T714C 000:709.069 - 0.016ms returns 0 +T714C 000:709.087 JLINK_WriteReg(R3, 0x00000000) +T714C 000:709.103 - 0.016ms returns 0 +T714C 000:709.120 JLINK_WriteReg(R4, 0x00000000) +T714C 000:709.136 - 0.016ms returns 0 +T714C 000:709.153 JLINK_WriteReg(R5, 0x00000000) +T714C 000:709.169 - 0.016ms returns 0 +T714C 000:709.185 JLINK_WriteReg(R6, 0x00000000) +T714C 000:709.201 - 0.015ms returns 0 +T714C 000:709.218 JLINK_WriteReg(R7, 0x00000000) +T714C 000:709.234 - 0.016ms returns 0 +T714C 000:709.251 JLINK_WriteReg(R8, 0x00000000) +T714C 000:709.268 - 0.016ms returns 0 +T714C 000:709.284 JLINK_WriteReg(R9, 0x30500458) +T714C 000:709.300 - 0.016ms returns 0 +T714C 000:709.316 JLINK_WriteReg(R10, 0x00000000) +T714C 000:709.333 - 0.016ms returns 0 +T714C 000:709.349 JLINK_WriteReg(R11, 0x00000000) +T714C 000:709.365 - 0.016ms returns 0 +T714C 000:709.382 JLINK_WriteReg(R12, 0x00000000) +T714C 000:709.398 - 0.016ms returns 0 +T714C 000:709.415 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 000:709.433 - 0.018ms returns 0 +T714C 000:709.451 JLINK_WriteReg(R14, 0x30500001) +T714C 000:709.467 - 0.016ms returns 0 +T714C 000:709.484 JLINK_WriteReg(R15 (PC), 0x30500020) +T714C 000:709.500 - 0.016ms returns 0 +T714C 000:709.516 JLINK_WriteReg(XPSR, 0x01000000) +T714C 000:709.532 - 0.016ms returns 0 +T714C 000:709.549 JLINK_WriteReg(MSP, 0x30508000) +T714C 000:709.565 - 0.016ms returns 0 +T714C 000:709.582 JLINK_WriteReg(PSP, 0x30508000) +T714C 000:709.598 - 0.016ms returns 0 +T714C 000:709.615 JLINK_WriteReg(CFBP, 0x00000000) +T714C 000:709.631 - 0.016ms returns 0 +T714C 000:709.681 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 000:709.698 - 0.017ms returns 0x0000000A +T714C 000:709.714 JLINK_Go() +T714C 000:709.733 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 000:709.991 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 000:711.937 - 2.222ms +T714C 000:712.636 JLINK_IsHalted() +T714C 000:714.739 - 2.102ms returns TRUE +T714C 000:714.785 JLINK_ReadReg(R15 (PC)) +T714C 000:714.804 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 000:715.088 - 0.303ms returns 0x30500000 +T714C 000:715.117 JLINK_ClrBPEx(BPHandle = 0x0000000A) +T714C 000:715.136 - 0.019ms returns 0x00 +T714C 000:715.153 JLINK_ReadReg(R0) +T714C 000:715.177 - 0.023ms returns 0x00000001 +T714C 000:715.197 JLINK_HasError() +T714C 000:715.214 JLINK_WriteReg(R0, 0x2800D000) +T714C 000:715.234 - 0.020ms returns 0 +T714C 000:715.251 JLINK_WriteReg(R1, 0x00001000) +T714C 000:715.267 - 0.016ms returns 0 +T714C 000:715.283 JLINK_WriteReg(R2, 0x000000FF) +T714C 000:715.299 - 0.015ms returns 0 +T714C 000:715.316 JLINK_WriteReg(R3, 0x00000000) +T714C 000:715.332 - 0.015ms returns 0 +T714C 000:715.349 JLINK_WriteReg(R4, 0x00000000) +T714C 000:715.365 - 0.016ms returns 0 +T714C 000:715.381 JLINK_WriteReg(R5, 0x00000000) +T714C 000:715.397 - 0.016ms returns 0 +T714C 000:715.414 JLINK_WriteReg(R6, 0x00000000) +T714C 000:715.430 - 0.016ms returns 0 +T714C 000:715.447 JLINK_WriteReg(R7, 0x00000000) +T714C 000:715.464 - 0.016ms returns 0 +T714C 000:715.481 JLINK_WriteReg(R8, 0x00000000) +T714C 000:715.497 - 0.016ms returns 0 +T714C 000:715.513 JLINK_WriteReg(R9, 0x30500458) +T714C 000:715.530 - 0.016ms returns 0 +T714C 000:715.546 JLINK_WriteReg(R10, 0x00000000) +T714C 000:715.562 - 0.016ms returns 0 +T714C 000:715.578 JLINK_WriteReg(R11, 0x00000000) +T714C 000:715.594 - 0.015ms returns 0 +T714C 000:715.611 JLINK_WriteReg(R12, 0x00000000) +T714C 000:715.628 - 0.017ms returns 0 +T714C 000:715.645 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 000:715.662 - 0.016ms returns 0 +T714C 000:715.679 JLINK_WriteReg(R14, 0x30500001) +T714C 000:715.696 - 0.016ms returns 0 +T714C 000:715.713 JLINK_WriteReg(R15 (PC), 0x30500274) +T714C 000:715.729 - 0.016ms returns 0 +T714C 000:715.745 JLINK_WriteReg(XPSR, 0x01000000) +T714C 000:715.761 - 0.015ms returns 0 +T714C 000:715.777 JLINK_WriteReg(MSP, 0x30508000) +T714C 000:715.793 - 0.016ms returns 0 +T714C 000:715.809 JLINK_WriteReg(PSP, 0x30508000) +T714C 000:715.825 - 0.015ms returns 0 +T714C 000:715.842 JLINK_WriteReg(CFBP, 0x00000000) +T714C 000:715.858 - 0.016ms returns 0 +T714C 000:715.876 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 000:715.893 - 0.017ms returns 0x0000000B +T714C 000:715.909 JLINK_Go() +T714C 000:715.927 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 000:716.246 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 000:718.342 - 2.432ms +T714C 000:718.400 JLINK_IsHalted() +T714C 000:718.655 - 0.254ms returns FALSE +T714C 000:718.677 JLINK_HasError() +T714C 000:728.256 JLINK_IsHalted() +T714C 000:728.576 - 0.319ms returns FALSE +T714C 000:728.606 JLINK_HasError() +T714C 000:731.252 JLINK_IsHalted() +T714C 000:731.548 - 0.296ms returns FALSE +T714C 000:731.573 JLINK_HasError() +T714C 000:739.306 JLINK_IsHalted() +T714C 000:739.933 - 0.626ms returns FALSE +T714C 000:739.996 JLINK_HasError() +T714C 000:754.988 JLINK_IsHalted() +T714C 000:755.350 - 0.361ms returns FALSE +T714C 000:755.385 JLINK_HasError() +T714C 000:780.594 JLINK_IsHalted() +T714C 000:782.852 - 2.257ms returns TRUE +T714C 000:782.903 JLINK_ReadReg(R15 (PC)) +T714C 000:782.925 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 000:783.191 - 0.288ms returns 0x30500000 +T714C 000:783.224 JLINK_ClrBPEx(BPHandle = 0x0000000B) +T714C 000:783.243 - 0.019ms returns 0x00 +T714C 000:783.261 JLINK_ReadReg(R0) +T714C 000:783.278 - 0.017ms returns 0x00000000 +T714C 000:784.506 JLINK_HasError() +T714C 000:784.597 JLINK_WriteReg(R0, 0x2800E000) +T714C 000:784.641 - 0.043ms returns 0 +T714C 000:784.676 JLINK_WriteReg(R1, 0x00001000) +T714C 000:784.709 - 0.033ms returns 0 +T714C 000:784.743 JLINK_WriteReg(R2, 0x000000FF) +T714C 000:784.775 - 0.032ms returns 0 +T714C 000:784.810 JLINK_WriteReg(R3, 0x00000000) +T714C 000:784.842 - 0.032ms returns 0 +T714C 000:784.876 JLINK_WriteReg(R4, 0x00000000) +T714C 000:784.909 - 0.033ms returns 0 +T714C 000:784.942 JLINK_WriteReg(R5, 0x00000000) +T714C 000:784.975 - 0.032ms returns 0 +T714C 000:785.008 JLINK_WriteReg(R6, 0x00000000) +T714C 000:785.041 - 0.032ms returns 0 +T714C 000:785.074 JLINK_WriteReg(R7, 0x00000000) +T714C 000:785.108 - 0.034ms returns 0 +T714C 000:785.142 JLINK_WriteReg(R8, 0x00000000) +T714C 000:785.175 - 0.032ms returns 0 +T714C 000:785.208 JLINK_WriteReg(R9, 0x30500458) +T714C 000:785.241 - 0.033ms returns 0 +T714C 000:785.275 JLINK_WriteReg(R10, 0x00000000) +T714C 000:785.318 - 0.043ms returns 0 +T714C 000:785.352 JLINK_WriteReg(R11, 0x00000000) +T714C 000:785.386 - 0.034ms returns 0 +T714C 000:785.420 JLINK_WriteReg(R12, 0x00000000) +T714C 000:785.453 - 0.033ms returns 0 +T714C 000:785.487 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 000:785.525 - 0.038ms returns 0 +T714C 000:785.560 JLINK_WriteReg(R14, 0x30500001) +T714C 000:785.593 - 0.033ms returns 0 +T714C 000:785.627 JLINK_WriteReg(R15 (PC), 0x30500020) +T714C 000:785.660 - 0.033ms returns 0 +T714C 000:785.693 JLINK_WriteReg(XPSR, 0x01000000) +T714C 000:785.778 - 0.084ms returns 0 +T714C 000:785.811 JLINK_WriteReg(MSP, 0x30508000) +T714C 000:785.828 - 0.017ms returns 0 +T714C 000:785.846 JLINK_WriteReg(PSP, 0x30508000) +T714C 000:785.865 - 0.019ms returns 0 +T714C 000:785.882 JLINK_WriteReg(CFBP, 0x00000000) +T714C 000:785.898 - 0.015ms returns 0 +T714C 000:785.915 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 000:785.933 - 0.018ms returns 0x0000000C +T714C 000:785.950 JLINK_Go() +T714C 000:785.970 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 000:786.238 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 000:788.037 - 2.087ms +T714C 000:788.072 JLINK_IsHalted() +T714C 000:790.237 - 2.164ms returns TRUE +T714C 000:790.907 JLINK_ReadReg(R15 (PC)) +T714C 000:790.938 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 000:791.157 - 0.249ms returns 0x30500000 +T714C 000:791.201 JLINK_ClrBPEx(BPHandle = 0x0000000C) +T714C 000:791.219 - 0.017ms returns 0x00 +T714C 000:791.237 JLINK_ReadReg(R0) +T714C 000:791.255 - 0.018ms returns 0x00000001 +T714C 000:791.272 JLINK_HasError() +T714C 000:791.291 JLINK_WriteReg(R0, 0x2800E000) +T714C 000:791.307 - 0.016ms returns 0 +T714C 000:791.324 JLINK_WriteReg(R1, 0x00001000) +T714C 000:791.341 - 0.016ms returns 0 +T714C 000:791.357 JLINK_WriteReg(R2, 0x000000FF) +T714C 000:791.373 - 0.016ms returns 0 +T714C 000:791.390 JLINK_WriteReg(R3, 0x00000000) +T714C 000:791.406 - 0.016ms returns 0 +T714C 000:791.422 JLINK_WriteReg(R4, 0x00000000) +T714C 000:791.439 - 0.016ms returns 0 +T714C 000:791.455 JLINK_WriteReg(R5, 0x00000000) +T714C 000:791.471 - 0.015ms returns 0 +T714C 000:791.487 JLINK_WriteReg(R6, 0x00000000) +T714C 000:791.503 - 0.015ms returns 0 +T714C 000:791.519 JLINK_WriteReg(R7, 0x00000000) +T714C 000:791.535 - 0.015ms returns 0 +T714C 000:791.552 JLINK_WriteReg(R8, 0x00000000) +T714C 000:791.569 - 0.016ms returns 0 +T714C 000:791.586 JLINK_WriteReg(R9, 0x30500458) +T714C 000:791.602 - 0.016ms returns 0 +T714C 000:791.618 JLINK_WriteReg(R10, 0x00000000) +T714C 000:791.635 - 0.016ms returns 0 +T714C 000:791.651 JLINK_WriteReg(R11, 0x00000000) +T714C 000:791.667 - 0.016ms returns 0 +T714C 000:791.684 JLINK_WriteReg(R12, 0x00000000) +T714C 000:791.700 - 0.016ms returns 0 +T714C 000:791.717 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 000:791.734 - 0.017ms returns 0 +T714C 000:791.750 JLINK_WriteReg(R14, 0x30500001) +T714C 000:791.766 - 0.016ms returns 0 +T714C 000:791.782 JLINK_WriteReg(R15 (PC), 0x30500274) +T714C 000:791.799 - 0.016ms returns 0 +T714C 000:791.815 JLINK_WriteReg(XPSR, 0x01000000) +T714C 000:791.831 - 0.016ms returns 0 +T714C 000:791.847 JLINK_WriteReg(MSP, 0x30508000) +T714C 000:791.863 - 0.016ms returns 0 +T714C 000:791.879 JLINK_WriteReg(PSP, 0x30508000) +T714C 000:791.896 - 0.016ms returns 0 +T714C 000:791.913 JLINK_WriteReg(CFBP, 0x00000000) +T714C 000:791.928 - 0.015ms returns 0 +T714C 000:791.945 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 000:791.962 - 0.016ms returns 0x0000000D +T714C 000:791.979 JLINK_Go() +T714C 000:791.997 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 000:792.324 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 000:794.153 - 2.174ms +T714C 000:794.188 JLINK_IsHalted() +T714C 000:794.439 - 0.250ms returns FALSE +T714C 000:794.460 JLINK_HasError() +T714C 000:798.216 JLINK_IsHalted() +T714C 000:798.553 - 0.336ms returns FALSE +T714C 000:798.577 JLINK_HasError() +T714C 000:809.619 JLINK_IsHalted() +T714C 000:809.949 - 0.328ms returns FALSE +T714C 000:809.989 JLINK_HasError() +T714C 000:852.849 JLINK_IsHalted() +T714C 000:855.014 - 2.164ms returns TRUE +T714C 000:855.064 JLINK_ReadReg(R15 (PC)) +T714C 000:855.087 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 000:855.347 - 0.281ms returns 0x30500000 +T714C 000:855.404 JLINK_ClrBPEx(BPHandle = 0x0000000D) +T714C 000:855.423 - 0.019ms returns 0x00 +T714C 000:855.443 JLINK_ReadReg(R0) +T714C 000:855.461 - 0.018ms returns 0x00000000 +T714C 000:856.132 JLINK_HasError() +T714C 000:856.173 JLINK_WriteReg(R0, 0x2800F000) +T714C 000:856.193 - 0.020ms returns 0 +T714C 000:856.210 JLINK_WriteReg(R1, 0x00001000) +T714C 000:856.226 - 0.016ms returns 0 +T714C 000:856.244 JLINK_WriteReg(R2, 0x000000FF) +T714C 000:856.260 - 0.016ms returns 0 +T714C 000:856.301 JLINK_WriteReg(R3, 0x00000000) +T714C 000:856.318 - 0.017ms returns 0 +T714C 000:856.335 JLINK_WriteReg(R4, 0x00000000) +T714C 000:856.352 - 0.017ms returns 0 +T714C 000:856.369 JLINK_WriteReg(R5, 0x00000000) +T714C 000:856.386 - 0.016ms returns 0 +T714C 000:856.403 JLINK_WriteReg(R6, 0x00000000) +T714C 000:856.420 - 0.016ms returns 0 +T714C 000:856.436 JLINK_WriteReg(R7, 0x00000000) +T714C 000:856.453 - 0.016ms returns 0 +T714C 000:856.469 JLINK_WriteReg(R8, 0x00000000) +T714C 000:856.486 - 0.016ms returns 0 +T714C 000:856.502 JLINK_WriteReg(R9, 0x30500458) +T714C 000:856.519 - 0.016ms returns 0 +T714C 000:856.558 JLINK_WriteReg(R10, 0x00000000) +T714C 000:856.575 - 0.017ms returns 0 +T714C 000:856.591 JLINK_WriteReg(R11, 0x00000000) +T714C 000:856.607 - 0.016ms returns 0 +T714C 000:856.624 JLINK_WriteReg(R12, 0x00000000) +T714C 000:856.640 - 0.016ms returns 0 +T714C 000:856.656 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 000:856.674 - 0.017ms returns 0 +T714C 000:856.690 JLINK_WriteReg(R14, 0x30500001) +T714C 000:856.706 - 0.016ms returns 0 +T714C 000:856.722 JLINK_WriteReg(R15 (PC), 0x30500020) +T714C 000:856.738 - 0.016ms returns 0 +T714C 000:856.755 JLINK_WriteReg(XPSR, 0x01000000) +T714C 000:856.786 - 0.030ms returns 0 +T714C 000:856.802 JLINK_WriteReg(MSP, 0x30508000) +T714C 000:856.819 - 0.016ms returns 0 +T714C 000:856.835 JLINK_WriteReg(PSP, 0x30508000) +T714C 000:856.884 - 0.049ms returns 0 +T714C 000:856.902 JLINK_WriteReg(CFBP, 0x00000000) +T714C 000:856.919 - 0.016ms returns 0 +T714C 000:856.937 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 000:856.954 - 0.017ms returns 0x0000000E +T714C 000:856.970 JLINK_Go() +T714C 000:856.989 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 000:857.305 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 000:859.214 - 2.243ms +T714C 000:859.247 JLINK_IsHalted() +T714C 000:861.489 - 2.240ms returns TRUE +T714C 000:861.595 JLINK_ReadReg(R15 (PC)) +T714C 000:861.642 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 000:861.982 - 0.384ms returns 0x30500000 +T714C 000:862.033 JLINK_ClrBPEx(BPHandle = 0x0000000E) +T714C 000:862.061 - 0.028ms returns 0x00 +T714C 000:862.080 JLINK_ReadReg(R0) +T714C 000:862.099 - 0.019ms returns 0x00000001 +T714C 000:862.119 JLINK_HasError() +T714C 000:862.138 JLINK_WriteReg(R0, 0x2800F000) +T714C 000:862.156 - 0.018ms returns 0 +T714C 000:862.174 JLINK_WriteReg(R1, 0x00001000) +T714C 000:862.192 - 0.018ms returns 0 +T714C 000:862.210 JLINK_WriteReg(R2, 0x000000FF) +T714C 000:862.227 - 0.017ms returns 0 +T714C 000:862.244 JLINK_WriteReg(R3, 0x00000000) +T714C 000:862.262 - 0.017ms returns 0 +T714C 000:862.280 JLINK_WriteReg(R4, 0x00000000) +T714C 000:862.296 - 0.016ms returns 0 +T714C 000:862.313 JLINK_WriteReg(R5, 0x00000000) +T714C 000:862.331 - 0.017ms returns 0 +T714C 000:862.349 JLINK_WriteReg(R6, 0x00000000) +T714C 000:862.366 - 0.016ms returns 0 +T714C 000:862.382 JLINK_WriteReg(R7, 0x00000000) +T714C 000:862.398 - 0.016ms returns 0 +T714C 000:862.415 JLINK_WriteReg(R8, 0x00000000) +T714C 000:862.433 - 0.017ms returns 0 +T714C 000:862.450 JLINK_WriteReg(R9, 0x30500458) +T714C 000:862.467 - 0.016ms returns 0 +T714C 000:862.484 JLINK_WriteReg(R10, 0x00000000) +T714C 000:862.501 - 0.016ms returns 0 +T714C 000:862.518 JLINK_WriteReg(R11, 0x00000000) +T714C 000:862.534 - 0.016ms returns 0 +T714C 000:862.552 JLINK_WriteReg(R12, 0x00000000) +T714C 000:862.569 - 0.017ms returns 0 +T714C 000:862.590 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 000:862.611 - 0.020ms returns 0 +T714C 000:862.628 JLINK_WriteReg(R14, 0x30500001) +T714C 000:862.645 - 0.016ms returns 0 +T714C 000:862.667 JLINK_WriteReg(R15 (PC), 0x30500274) +T714C 000:862.683 - 0.016ms returns 0 +T714C 000:862.705 JLINK_WriteReg(XPSR, 0x01000000) +T714C 000:862.722 - 0.017ms returns 0 +T714C 000:862.743 JLINK_WriteReg(MSP, 0x30508000) +T714C 000:862.760 - 0.016ms returns 0 +T714C 000:862.777 JLINK_WriteReg(PSP, 0x30508000) +T714C 000:862.793 - 0.016ms returns 0 +T714C 000:862.810 JLINK_WriteReg(CFBP, 0x00000000) +T714C 000:862.827 - 0.016ms returns 0 +T714C 000:862.846 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 000:862.864 - 0.018ms returns 0x0000000F +T714C 000:862.882 JLINK_Go() +T714C 000:862.902 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 000:863.225 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 000:865.817 - 2.934ms +T714C 000:865.921 JLINK_IsHalted() +T714C 000:866.261 - 0.339ms returns FALSE +T714C 000:866.346 JLINK_HasError() +T714C 000:873.122 JLINK_IsHalted() +T714C 000:873.450 - 0.326ms returns FALSE +T714C 000:873.484 JLINK_HasError() +T714C 000:876.472 JLINK_IsHalted() +T714C 000:876.926 - 0.451ms returns FALSE +T714C 000:877.014 JLINK_HasError() +T714C 000:880.478 JLINK_IsHalted() +T714C 000:880.791 - 0.312ms returns FALSE +T714C 000:880.817 JLINK_HasError() +T714C 000:884.473 JLINK_IsHalted() +T714C 000:884.839 - 0.364ms returns FALSE +T714C 000:884.865 JLINK_HasError() +T714C 000:886.468 JLINK_IsHalted() +T714C 000:886.716 - 0.247ms returns FALSE +T714C 000:886.740 JLINK_HasError() +T714C 000:888.470 JLINK_IsHalted() +T714C 000:888.711 - 0.240ms returns FALSE +T714C 000:888.732 JLINK_HasError() +T714C 000:891.488 JLINK_IsHalted() +T714C 000:891.791 - 0.303ms returns FALSE +T714C 000:891.816 JLINK_HasError() +T714C 000:893.473 JLINK_IsHalted() +T714C 000:893.788 - 0.315ms returns FALSE +T714C 000:894.476 JLINK_HasError() +T714C 000:896.470 JLINK_IsHalted() +T714C 000:896.714 - 0.244ms returns FALSE +T714C 000:896.737 JLINK_HasError() +T714C 000:898.471 JLINK_IsHalted() +T714C 000:898.735 - 0.264ms returns FALSE +T714C 000:898.758 JLINK_HasError() +T714C 000:900.469 JLINK_IsHalted() +T714C 000:900.687 - 0.217ms returns FALSE +T714C 000:900.710 JLINK_HasError() +T714C 000:902.469 JLINK_IsHalted() +T714C 000:902.755 - 0.285ms returns FALSE +T714C 000:902.777 JLINK_HasError() +T714C 000:904.469 JLINK_IsHalted() +T714C 000:904.689 - 0.220ms returns FALSE +T714C 000:904.711 JLINK_HasError() +T714C 000:906.650 JLINK_IsHalted() +T714C 000:907.103 - 0.452ms returns FALSE +T714C 000:907.153 JLINK_HasError() +T714C 000:908.647 JLINK_IsHalted() +T714C 000:908.908 - 0.259ms returns FALSE +T714C 000:908.932 JLINK_HasError() +T714C 000:910.654 JLINK_IsHalted() +T714C 000:910.903 - 0.249ms returns FALSE +T714C 000:910.926 JLINK_HasError() +T714C 000:912.670 JLINK_IsHalted() +T714C 000:912.904 - 0.233ms returns FALSE +T714C 000:912.926 JLINK_HasError() +T714C 000:914.667 JLINK_IsHalted() +T714C 000:914.904 - 0.236ms returns FALSE +T714C 000:914.928 JLINK_HasError() +T714C 000:916.668 JLINK_IsHalted() +T714C 000:918.794 - 2.125ms returns TRUE +T714C 000:918.831 JLINK_ReadReg(R15 (PC)) +T714C 000:918.852 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 000:919.073 - 0.241ms returns 0x30500000 +T714C 000:919.094 JLINK_ClrBPEx(BPHandle = 0x0000000F) +T714C 000:919.111 - 0.017ms returns 0x00 +T714C 000:919.128 JLINK_ReadReg(R0) +T714C 000:919.146 - 0.017ms returns 0x00000000 +T714C 000:920.324 JLINK_HasError() +T714C 000:920.372 JLINK_WriteReg(R0, 0x28010000) +T714C 000:920.399 - 0.027ms returns 0 +T714C 000:920.417 JLINK_WriteReg(R1, 0x00001000) +T714C 000:920.436 - 0.018ms returns 0 +T714C 000:920.452 JLINK_WriteReg(R2, 0x000000FF) +T714C 000:920.469 - 0.016ms returns 0 +T714C 000:920.486 JLINK_WriteReg(R3, 0x00000000) +T714C 000:920.502 - 0.015ms returns 0 +T714C 000:920.518 JLINK_WriteReg(R4, 0x00000000) +T714C 000:920.535 - 0.016ms returns 0 +T714C 000:920.552 JLINK_WriteReg(R5, 0x00000000) +T714C 000:920.567 - 0.015ms returns 0 +T714C 000:920.646 JLINK_WriteReg(R6, 0x00000000) +T714C 000:920.666 - 0.019ms returns 0 +T714C 000:920.682 JLINK_WriteReg(R7, 0x00000000) +T714C 000:920.698 - 0.015ms returns 0 +T714C 000:920.714 JLINK_WriteReg(R8, 0x00000000) +T714C 000:920.730 - 0.016ms returns 0 +T714C 000:920.747 JLINK_WriteReg(R9, 0x30500458) +T714C 000:920.763 - 0.016ms returns 0 +T714C 000:920.780 JLINK_WriteReg(R10, 0x00000000) +T714C 000:920.797 - 0.016ms returns 0 +T714C 000:920.814 JLINK_WriteReg(R11, 0x00000000) +T714C 000:920.842 - 0.028ms returns 0 +T714C 000:920.866 JLINK_WriteReg(R12, 0x00000000) +T714C 000:920.892 - 0.026ms returns 0 +T714C 000:920.919 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 000:920.944 - 0.026ms returns 0 +T714C 000:920.963 JLINK_WriteReg(R14, 0x30500001) +T714C 000:920.979 - 0.016ms returns 0 +T714C 000:920.998 JLINK_WriteReg(R15 (PC), 0x30500020) +T714C 000:921.016 - 0.018ms returns 0 +T714C 000:921.034 JLINK_WriteReg(XPSR, 0x01000000) +T714C 000:921.054 - 0.020ms returns 0 +T714C 000:921.072 JLINK_WriteReg(MSP, 0x30508000) +T714C 000:921.089 - 0.017ms returns 0 +T714C 000:921.107 JLINK_WriteReg(PSP, 0x30508000) +T714C 000:921.125 - 0.017ms returns 0 +T714C 000:921.142 JLINK_WriteReg(CFBP, 0x00000000) +T714C 000:921.158 - 0.016ms returns 0 +T714C 000:921.176 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 000:921.194 - 0.019ms returns 0x00000010 +T714C 000:921.212 JLINK_Go() +T714C 000:921.232 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 000:921.503 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 000:923.412 - 2.200ms +T714C 000:923.448 JLINK_IsHalted() +T714C 000:925.544 - 2.095ms returns TRUE +T714C 000:925.585 JLINK_ReadReg(R15 (PC)) +T714C 000:925.605 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 000:925.852 - 0.267ms returns 0x30500000 +T714C 000:925.873 JLINK_ClrBPEx(BPHandle = 0x00000010) +T714C 000:925.891 - 0.017ms returns 0x00 +T714C 000:925.908 JLINK_ReadReg(R0) +T714C 000:925.925 - 0.017ms returns 0x00000001 +T714C 000:925.942 JLINK_HasError() +T714C 000:925.959 JLINK_WriteReg(R0, 0x28010000) +T714C 000:925.976 - 0.016ms returns 0 +T714C 000:925.993 JLINK_WriteReg(R1, 0x00001000) +T714C 000:926.009 - 0.016ms returns 0 +T714C 000:926.025 JLINK_WriteReg(R2, 0x000000FF) +T714C 000:926.041 - 0.016ms returns 0 +T714C 000:926.058 JLINK_WriteReg(R3, 0x00000000) +T714C 000:926.074 - 0.016ms returns 0 +T714C 000:926.090 JLINK_WriteReg(R4, 0x00000000) +T714C 000:926.106 - 0.016ms returns 0 +T714C 000:926.122 JLINK_WriteReg(R5, 0x00000000) +T714C 000:926.138 - 0.015ms returns 0 +T714C 000:926.154 JLINK_WriteReg(R6, 0x00000000) +T714C 000:926.170 - 0.016ms returns 0 +T714C 000:926.186 JLINK_WriteReg(R7, 0x00000000) +T714C 000:926.202 - 0.015ms returns 0 +T714C 000:926.218 JLINK_WriteReg(R8, 0x00000000) +T714C 000:926.234 - 0.016ms returns 0 +T714C 000:926.250 JLINK_WriteReg(R9, 0x30500458) +T714C 000:926.265 - 0.015ms returns 0 +T714C 000:926.282 JLINK_WriteReg(R10, 0x00000000) +T714C 000:926.298 - 0.016ms returns 0 +T714C 000:926.314 JLINK_WriteReg(R11, 0x00000000) +T714C 000:926.330 - 0.016ms returns 0 +T714C 000:926.347 JLINK_WriteReg(R12, 0x00000000) +T714C 000:926.363 - 0.016ms returns 0 +T714C 000:926.379 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 000:926.396 - 0.017ms returns 0 +T714C 000:926.412 JLINK_WriteReg(R14, 0x30500001) +T714C 000:926.429 - 0.016ms returns 0 +T714C 000:926.446 JLINK_WriteReg(R15 (PC), 0x30500274) +T714C 000:926.462 - 0.016ms returns 0 +T714C 000:926.479 JLINK_WriteReg(XPSR, 0x01000000) +T714C 000:926.495 - 0.016ms returns 0 +T714C 000:926.512 JLINK_WriteReg(MSP, 0x30508000) +T714C 000:926.528 - 0.016ms returns 0 +T714C 000:926.545 JLINK_WriteReg(PSP, 0x30508000) +T714C 000:926.561 - 0.015ms returns 0 +T714C 000:926.577 JLINK_WriteReg(CFBP, 0x00000000) +T714C 000:926.593 - 0.015ms returns 0 +T714C 000:926.610 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 000:926.626 - 0.016ms returns 0x00000011 +T714C 000:926.643 JLINK_Go() +T714C 000:926.661 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 000:926.928 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 000:928.785 - 2.142ms +T714C 000:928.829 JLINK_IsHalted() +T714C 000:929.099 - 0.269ms returns FALSE +T714C 000:929.120 JLINK_HasError() +T714C 000:931.330 JLINK_IsHalted() +T714C 000:931.626 - 0.295ms returns FALSE +T714C 000:931.670 JLINK_HasError() +T714C 000:934.274 JLINK_IsHalted() +T714C 000:934.612 - 0.337ms returns FALSE +T714C 000:934.637 JLINK_HasError() +T714C 000:937.257 JLINK_IsHalted() +T714C 000:937.701 - 0.442ms returns FALSE +T714C 000:937.763 JLINK_HasError() +T714C 000:941.248 JLINK_IsHalted() +T714C 000:941.633 - 0.384ms returns FALSE +T714C 000:941.666 JLINK_HasError() +T714C 000:945.915 JLINK_IsHalted() +T714C 000:946.235 - 0.318ms returns FALSE +T714C 000:946.283 JLINK_HasError() +T714C 000:949.258 JLINK_IsHalted() +T714C 000:949.727 - 0.468ms returns FALSE +T714C 000:949.820 JLINK_HasError() +T714C 000:959.618 JLINK_IsHalted() +T714C 000:959.909 - 0.291ms returns FALSE +T714C 000:959.936 JLINK_HasError() +T714C 000:963.597 JLINK_IsHalted() +T714C 000:963.905 - 0.308ms returns FALSE +T714C 000:963.928 JLINK_HasError() +T714C 000:967.838 JLINK_IsHalted() +T714C 000:968.162 - 0.323ms returns FALSE +T714C 000:968.196 JLINK_HasError() +T714C 000:971.856 JLINK_IsHalted() +T714C 000:972.192 - 0.335ms returns FALSE +T714C 000:972.220 JLINK_HasError() +T714C 000:975.850 JLINK_IsHalted() +T714C 000:976.158 - 0.307ms returns FALSE +T714C 000:976.194 JLINK_HasError() +T714C 000:978.844 JLINK_IsHalted() +T714C 000:981.053 - 2.207ms returns TRUE +T714C 000:981.100 JLINK_ReadReg(R15 (PC)) +T714C 000:981.123 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 000:981.395 - 0.295ms returns 0x30500000 +T714C 000:981.427 JLINK_ClrBPEx(BPHandle = 0x00000011) +T714C 000:981.448 - 0.020ms returns 0x00 +T714C 000:981.465 JLINK_ReadReg(R0) +T714C 000:981.482 - 0.017ms returns 0x00000000 +T714C 000:982.587 JLINK_HasError() +T714C 000:982.663 JLINK_WriteReg(R0, 0x28011000) +T714C 000:982.688 - 0.024ms returns 0 +T714C 000:982.706 JLINK_WriteReg(R1, 0x00001000) +T714C 000:982.723 - 0.016ms returns 0 +T714C 000:982.740 JLINK_WriteReg(R2, 0x000000FF) +T714C 000:982.756 - 0.016ms returns 0 +T714C 000:982.779 JLINK_WriteReg(R3, 0x00000000) +T714C 000:982.803 - 0.023ms returns 0 +T714C 000:982.820 JLINK_WriteReg(R4, 0x00000000) +T714C 000:982.840 - 0.020ms returns 0 +T714C 000:982.862 JLINK_WriteReg(R5, 0x00000000) +T714C 000:982.879 - 0.017ms returns 0 +T714C 000:982.899 JLINK_WriteReg(R6, 0x00000000) +T714C 000:982.922 - 0.023ms returns 0 +T714C 000:982.939 JLINK_WriteReg(R7, 0x00000000) +T714C 000:982.956 - 0.016ms returns 0 +T714C 000:982.973 JLINK_WriteReg(R8, 0x00000000) +T714C 000:982.990 - 0.017ms returns 0 +T714C 000:983.007 JLINK_WriteReg(R9, 0x30500458) +T714C 000:983.029 - 0.022ms returns 0 +T714C 000:983.055 JLINK_WriteReg(R10, 0x00000000) +T714C 000:983.076 - 0.021ms returns 0 +T714C 000:983.099 JLINK_WriteReg(R11, 0x00000000) +T714C 000:983.118 - 0.018ms returns 0 +T714C 000:983.135 JLINK_WriteReg(R12, 0x00000000) +T714C 000:983.152 - 0.016ms returns 0 +T714C 000:983.169 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 000:983.187 - 0.018ms returns 0 +T714C 000:983.206 JLINK_WriteReg(R14, 0x30500001) +T714C 000:983.222 - 0.016ms returns 0 +T714C 000:983.240 JLINK_WriteReg(R15 (PC), 0x30500020) +T714C 000:983.257 - 0.017ms returns 0 +T714C 000:983.277 JLINK_WriteReg(XPSR, 0x01000000) +T714C 000:983.302 - 0.025ms returns 0 +T714C 000:983.326 JLINK_WriteReg(MSP, 0x30508000) +T714C 000:983.352 - 0.025ms returns 0 +T714C 000:983.374 JLINK_WriteReg(PSP, 0x30508000) +T714C 000:983.390 - 0.016ms returns 0 +T714C 000:983.407 JLINK_WriteReg(CFBP, 0x00000000) +T714C 000:983.424 - 0.016ms returns 0 +T714C 000:983.441 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 000:983.462 - 0.020ms returns 0x00000012 +T714C 000:983.484 JLINK_Go() +T714C 000:983.504 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 000:983.847 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 000:985.873 - 2.389ms +T714C 000:985.916 JLINK_IsHalted() +T714C 000:988.115 - 2.198ms returns TRUE +T714C 000:988.163 JLINK_ReadReg(R15 (PC)) +T714C 000:988.183 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 000:988.440 - 0.276ms returns 0x30500000 +T714C 000:988.488 JLINK_ClrBPEx(BPHandle = 0x00000012) +T714C 000:988.509 - 0.020ms returns 0x00 +T714C 000:988.526 JLINK_ReadReg(R0) +T714C 000:988.544 - 0.018ms returns 0x00000001 +T714C 000:988.562 JLINK_HasError() +T714C 000:988.579 JLINK_WriteReg(R0, 0x28011000) +T714C 000:988.595 - 0.016ms returns 0 +T714C 000:988.612 JLINK_WriteReg(R1, 0x00001000) +T714C 000:988.628 - 0.016ms returns 0 +T714C 000:988.644 JLINK_WriteReg(R2, 0x000000FF) +T714C 000:988.660 - 0.015ms returns 0 +T714C 000:988.678 JLINK_WriteReg(R3, 0x00000000) +T714C 000:988.693 - 0.015ms returns 0 +T714C 000:988.710 JLINK_WriteReg(R4, 0x00000000) +T714C 000:988.725 - 0.015ms returns 0 +T714C 000:988.741 JLINK_WriteReg(R5, 0x00000000) +T714C 000:988.757 - 0.015ms returns 0 +T714C 000:988.773 JLINK_WriteReg(R6, 0x00000000) +T714C 000:988.789 - 0.016ms returns 0 +T714C 000:988.806 JLINK_WriteReg(R7, 0x00000000) +T714C 000:988.822 - 0.016ms returns 0 +T714C 000:988.838 JLINK_WriteReg(R8, 0x00000000) +T714C 000:988.854 - 0.015ms returns 0 +T714C 000:988.870 JLINK_WriteReg(R9, 0x30500458) +T714C 000:988.886 - 0.015ms returns 0 +T714C 000:988.903 JLINK_WriteReg(R10, 0x00000000) +T714C 000:988.920 - 0.016ms returns 0 +T714C 000:988.936 JLINK_WriteReg(R11, 0x00000000) +T714C 000:988.952 - 0.015ms returns 0 +T714C 000:988.968 JLINK_WriteReg(R12, 0x00000000) +T714C 000:988.985 - 0.016ms returns 0 +T714C 000:989.001 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 000:989.018 - 0.017ms returns 0 +T714C 000:989.035 JLINK_WriteReg(R14, 0x30500001) +T714C 000:989.051 - 0.016ms returns 0 +T714C 000:989.067 JLINK_WriteReg(R15 (PC), 0x30500274) +T714C 000:989.083 - 0.016ms returns 0 +T714C 000:989.101 JLINK_WriteReg(XPSR, 0x01000000) +T714C 000:989.117 - 0.016ms returns 0 +T714C 000:989.133 JLINK_WriteReg(MSP, 0x30508000) +T714C 000:989.149 - 0.016ms returns 0 +T714C 000:989.166 JLINK_WriteReg(PSP, 0x30508000) +T714C 000:989.183 - 0.016ms returns 0 +T714C 000:989.199 JLINK_WriteReg(CFBP, 0x00000000) +T714C 000:989.216 - 0.016ms returns 0 +T714C 000:989.233 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 000:989.250 - 0.017ms returns 0x00000013 +T714C 000:989.267 JLINK_Go() +T714C 000:989.285 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 000:989.582 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 000:991.486 - 2.218ms +T714C 000:991.522 JLINK_IsHalted() +T714C 000:991.785 - 0.262ms returns FALSE +T714C 000:991.805 JLINK_HasError() +T714C 000:997.166 JLINK_IsHalted() +T714C 000:997.535 - 0.367ms returns FALSE +T714C 000:997.585 JLINK_HasError() +T714C 000:999.544 JLINK_IsHalted() +T714C 000:999.860 - 0.316ms returns FALSE +T714C 000:999.902 JLINK_HasError() +T714C 001:001.554 JLINK_IsHalted() +T714C 001:001.871 - 0.316ms returns FALSE +T714C 001:001.894 JLINK_HasError() +T714C 001:003.542 JLINK_IsHalted() +T714C 001:003.809 - 0.266ms returns FALSE +T714C 001:003.830 JLINK_HasError() +T714C 001:005.575 JLINK_IsHalted() +T714C 001:005.839 - 0.264ms returns FALSE +T714C 001:005.860 JLINK_HasError() +T714C 001:007.570 JLINK_IsHalted() +T714C 001:007.821 - 0.250ms returns FALSE +T714C 001:007.847 JLINK_HasError() +T714C 001:009.576 JLINK_IsHalted() +T714C 001:009.836 - 0.259ms returns FALSE +T714C 001:009.857 JLINK_HasError() +T714C 001:011.610 JLINK_IsHalted() +T714C 001:011.849 - 0.239ms returns FALSE +T714C 001:011.871 JLINK_HasError() +T714C 001:013.851 JLINK_IsHalted() +T714C 001:014.190 - 0.338ms returns FALSE +T714C 001:014.242 JLINK_HasError() +T714C 001:016.071 JLINK_IsHalted() +T714C 001:016.385 - 0.313ms returns FALSE +T714C 001:016.417 JLINK_HasError() +T714C 001:018.105 JLINK_IsHalted() +T714C 001:018.415 - 0.309ms returns FALSE +T714C 001:018.443 JLINK_HasError() +T714C 001:020.069 JLINK_IsHalted() +T714C 001:020.352 - 0.282ms returns FALSE +T714C 001:020.382 JLINK_HasError() +T714C 001:022.117 JLINK_IsHalted() +T714C 001:022.418 - 0.300ms returns FALSE +T714C 001:023.095 JLINK_HasError() +T714C 001:024.612 JLINK_IsHalted() +T714C 001:024.868 - 0.256ms returns FALSE +T714C 001:024.891 JLINK_HasError() +T714C 001:026.644 JLINK_IsHalted() +T714C 001:026.901 - 0.257ms returns FALSE +T714C 001:026.922 JLINK_HasError() +T714C 001:028.620 JLINK_IsHalted() +T714C 001:028.911 - 0.290ms returns FALSE +T714C 001:028.952 JLINK_HasError() +T714C 001:030.618 JLINK_IsHalted() +T714C 001:030.838 - 0.220ms returns FALSE +T714C 001:030.860 JLINK_HasError() +T714C 001:032.652 JLINK_IsHalted() +T714C 001:032.867 - 0.214ms returns FALSE +T714C 001:032.888 JLINK_HasError() +T714C 001:034.644 JLINK_IsHalted() +T714C 001:034.921 - 0.276ms returns FALSE +T714C 001:034.942 JLINK_HasError() +T714C 001:036.644 JLINK_IsHalted() +T714C 001:038.846 - 2.200ms returns TRUE +T714C 001:038.885 JLINK_ReadReg(R15 (PC)) +T714C 001:038.906 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:039.154 - 0.269ms returns 0x30500000 +T714C 001:039.177 JLINK_ClrBPEx(BPHandle = 0x00000013) +T714C 001:039.194 - 0.016ms returns 0x00 +T714C 001:039.212 JLINK_ReadReg(R0) +T714C 001:039.230 - 0.017ms returns 0x00000000 +T714C 001:039.892 JLINK_HasError() +T714C 001:039.933 JLINK_WriteReg(R0, 0x28012000) +T714C 001:039.987 - 0.054ms returns 0 +T714C 001:040.004 JLINK_WriteReg(R1, 0x00001000) +T714C 001:040.021 - 0.017ms returns 0 +T714C 001:040.038 JLINK_WriteReg(R2, 0x000000FF) +T714C 001:040.054 - 0.016ms returns 0 +T714C 001:040.070 JLINK_WriteReg(R3, 0x00000000) +T714C 001:040.086 - 0.015ms returns 0 +T714C 001:040.103 JLINK_WriteReg(R4, 0x00000000) +T714C 001:040.119 - 0.015ms returns 0 +T714C 001:040.135 JLINK_WriteReg(R5, 0x00000000) +T714C 001:040.151 - 0.016ms returns 0 +T714C 001:040.168 JLINK_WriteReg(R6, 0x00000000) +T714C 001:040.184 - 0.016ms returns 0 +T714C 001:040.201 JLINK_WriteReg(R7, 0x00000000) +T714C 001:040.216 - 0.015ms returns 0 +T714C 001:040.233 JLINK_WriteReg(R8, 0x00000000) +T714C 001:040.249 - 0.016ms returns 0 +T714C 001:040.266 JLINK_WriteReg(R9, 0x30500458) +T714C 001:040.283 - 0.016ms returns 0 +T714C 001:040.299 JLINK_WriteReg(R10, 0x00000000) +T714C 001:040.316 - 0.016ms returns 0 +T714C 001:040.332 JLINK_WriteReg(R11, 0x00000000) +T714C 001:040.348 - 0.015ms returns 0 +T714C 001:040.364 JLINK_WriteReg(R12, 0x00000000) +T714C 001:040.380 - 0.015ms returns 0 +T714C 001:040.396 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:040.413 - 0.017ms returns 0 +T714C 001:040.429 JLINK_WriteReg(R14, 0x30500001) +T714C 001:040.446 - 0.016ms returns 0 +T714C 001:040.463 JLINK_WriteReg(R15 (PC), 0x30500020) +T714C 001:040.479 - 0.016ms returns 0 +T714C 001:040.495 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:040.512 - 0.017ms returns 0 +T714C 001:040.529 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:040.546 - 0.016ms returns 0 +T714C 001:040.562 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:040.579 - 0.016ms returns 0 +T714C 001:040.595 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:040.611 - 0.016ms returns 0 +T714C 001:040.628 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:040.644 - 0.016ms returns 0x00000014 +T714C 001:040.660 JLINK_Go() +T714C 001:040.679 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:040.945 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:042.830 - 2.168ms +T714C 001:042.922 JLINK_IsHalted() +T714C 001:045.242 - 2.318ms returns TRUE +T714C 001:045.294 JLINK_ReadReg(R15 (PC)) +T714C 001:045.318 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:045.615 - 0.321ms returns 0x30500000 +T714C 001:045.638 JLINK_ClrBPEx(BPHandle = 0x00000014) +T714C 001:045.656 - 0.017ms returns 0x00 +T714C 001:045.674 JLINK_ReadReg(R0) +T714C 001:045.691 - 0.016ms returns 0x00000001 +T714C 001:045.708 JLINK_HasError() +T714C 001:045.725 JLINK_WriteReg(R0, 0x28012000) +T714C 001:045.742 - 0.016ms returns 0 +T714C 001:045.759 JLINK_WriteReg(R1, 0x00001000) +T714C 001:045.775 - 0.016ms returns 0 +T714C 001:045.792 JLINK_WriteReg(R2, 0x000000FF) +T714C 001:045.810 - 0.017ms returns 0 +T714C 001:045.826 JLINK_WriteReg(R3, 0x00000000) +T714C 001:045.843 - 0.016ms returns 0 +T714C 001:045.860 JLINK_WriteReg(R4, 0x00000000) +T714C 001:045.875 - 0.016ms returns 0 +T714C 001:045.892 JLINK_WriteReg(R5, 0x00000000) +T714C 001:045.908 - 0.015ms returns 0 +T714C 001:045.924 JLINK_WriteReg(R6, 0x00000000) +T714C 001:045.945 - 0.021ms returns 0 +T714C 001:045.961 JLINK_WriteReg(R7, 0x00000000) +T714C 001:045.978 - 0.016ms returns 0 +T714C 001:045.994 JLINK_WriteReg(R8, 0x00000000) +T714C 001:046.010 - 0.015ms returns 0 +T714C 001:046.027 JLINK_WriteReg(R9, 0x30500458) +T714C 001:046.042 - 0.015ms returns 0 +T714C 001:046.058 JLINK_WriteReg(R10, 0x00000000) +T714C 001:046.074 - 0.015ms returns 0 +T714C 001:046.091 JLINK_WriteReg(R11, 0x00000000) +T714C 001:046.106 - 0.015ms returns 0 +T714C 001:046.123 JLINK_WriteReg(R12, 0x00000000) +T714C 001:046.138 - 0.015ms returns 0 +T714C 001:046.155 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:046.172 - 0.017ms returns 0 +T714C 001:046.188 JLINK_WriteReg(R14, 0x30500001) +T714C 001:046.204 - 0.016ms returns 0 +T714C 001:046.220 JLINK_WriteReg(R15 (PC), 0x30500274) +T714C 001:046.236 - 0.015ms returns 0 +T714C 001:046.252 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:046.268 - 0.015ms returns 0 +T714C 001:046.284 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:046.300 - 0.015ms returns 0 +T714C 001:046.317 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:046.334 - 0.017ms returns 0 +T714C 001:046.351 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:046.367 - 0.016ms returns 0 +T714C 001:046.384 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:046.400 - 0.016ms returns 0x00000015 +T714C 001:046.418 JLINK_Go() +T714C 001:046.438 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:046.749 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:048.693 - 2.274ms +T714C 001:048.723 JLINK_IsHalted() +T714C 001:049.042 - 0.319ms returns FALSE +T714C 001:049.073 JLINK_HasError() +T714C 001:050.930 JLINK_IsHalted() +T714C 001:051.269 - 0.338ms returns FALSE +T714C 001:051.292 JLINK_HasError() +T714C 001:052.922 JLINK_IsHalted() +T714C 001:053.209 - 0.286ms returns FALSE +T714C 001:053.230 JLINK_HasError() +T714C 001:054.924 JLINK_IsHalted() +T714C 001:055.192 - 0.267ms returns FALSE +T714C 001:055.212 JLINK_HasError() +T714C 001:056.926 JLINK_IsHalted() +T714C 001:057.158 - 0.231ms returns FALSE +T714C 001:057.178 JLINK_HasError() +T714C 001:058.986 JLINK_IsHalted() +T714C 001:059.483 - 0.496ms returns FALSE +T714C 001:059.517 JLINK_HasError() +T714C 001:061.005 JLINK_IsHalted() +T714C 001:061.385 - 0.380ms returns FALSE +T714C 001:061.407 JLINK_HasError() +T714C 001:063.004 JLINK_IsHalted() +T714C 001:063.544 - 0.540ms returns FALSE +T714C 001:063.568 JLINK_HasError() +T714C 001:065.034 JLINK_IsHalted() +T714C 001:065.530 - 0.495ms returns FALSE +T714C 001:065.555 JLINK_HasError() +T714C 001:067.018 JLINK_IsHalted() +T714C 001:067.343 - 0.324ms returns FALSE +T714C 001:067.398 JLINK_HasError() +T714C 001:069.020 JLINK_IsHalted() +T714C 001:069.523 - 0.502ms returns FALSE +T714C 001:069.552 JLINK_HasError() +T714C 001:071.034 JLINK_IsHalted() +T714C 001:071.533 - 0.499ms returns FALSE +T714C 001:071.567 JLINK_HasError() +T714C 001:073.032 JLINK_IsHalted() +T714C 001:073.360 - 0.327ms returns FALSE +T714C 001:073.551 JLINK_HasError() +T714C 001:077.024 JLINK_IsHalted() +T714C 001:077.501 - 0.477ms returns FALSE +T714C 001:077.549 JLINK_HasError() +T714C 001:079.077 JLINK_IsHalted() +T714C 001:079.504 - 0.426ms returns FALSE +T714C 001:079.552 JLINK_HasError() +T714C 001:081.139 JLINK_IsHalted() +T714C 001:081.663 - 0.524ms returns FALSE +T714C 001:081.706 JLINK_HasError() +T714C 001:083.234 JLINK_IsHalted() +T714C 001:083.788 - 0.553ms returns FALSE +T714C 001:083.830 JLINK_HasError() +T714C 001:085.217 JLINK_IsHalted() +T714C 001:085.780 - 0.562ms returns FALSE +T714C 001:085.824 JLINK_HasError() +T714C 001:087.225 JLINK_IsHalted() +T714C 001:087.662 - 0.436ms returns FALSE +T714C 001:087.705 JLINK_HasError() +T714C 001:089.094 JLINK_IsHalted() +T714C 001:089.517 - 0.423ms returns FALSE +T714C 001:089.573 JLINK_HasError() +T714C 001:091.058 JLINK_IsHalted() +T714C 001:091.342 - 0.283ms returns FALSE +T714C 001:091.390 JLINK_HasError() +T714C 001:093.045 JLINK_IsHalted() +T714C 001:093.355 - 0.309ms returns FALSE +T714C 001:093.375 JLINK_HasError() +T714C 001:095.023 JLINK_IsHalted() +T714C 001:095.311 - 0.287ms returns FALSE +T714C 001:095.333 JLINK_HasError() +T714C 001:097.016 JLINK_IsHalted() +T714C 001:099.160 - 2.143ms returns TRUE +T714C 001:099.184 JLINK_ReadReg(R15 (PC)) +T714C 001:099.204 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:099.465 - 0.281ms returns 0x30500000 +T714C 001:099.487 JLINK_ClrBPEx(BPHandle = 0x00000015) +T714C 001:099.505 - 0.018ms returns 0x00 +T714C 001:099.524 JLINK_ReadReg(R0) +T714C 001:099.542 - 0.018ms returns 0x00000000 +T714C 001:100.671 JLINK_HasError() +T714C 001:100.719 JLINK_WriteReg(R0, 0x28013000) +T714C 001:100.743 - 0.023ms returns 0 +T714C 001:100.764 JLINK_WriteReg(R1, 0x00001000) +T714C 001:100.782 - 0.018ms returns 0 +T714C 001:100.802 JLINK_WriteReg(R2, 0x000000FF) +T714C 001:100.820 - 0.018ms returns 0 +T714C 001:100.839 JLINK_WriteReg(R3, 0x00000000) +T714C 001:100.858 - 0.018ms returns 0 +T714C 001:100.876 JLINK_WriteReg(R4, 0x00000000) +T714C 001:100.894 - 0.018ms returns 0 +T714C 001:100.913 JLINK_WriteReg(R5, 0x00000000) +T714C 001:100.932 - 0.018ms returns 0 +T714C 001:100.950 JLINK_WriteReg(R6, 0x00000000) +T714C 001:100.970 - 0.019ms returns 0 +T714C 001:100.988 JLINK_WriteReg(R7, 0x00000000) +T714C 001:101.007 - 0.018ms returns 0 +T714C 001:101.025 JLINK_WriteReg(R8, 0x00000000) +T714C 001:101.043 - 0.018ms returns 0 +T714C 001:101.062 JLINK_WriteReg(R9, 0x30500458) +T714C 001:101.081 - 0.018ms returns 0 +T714C 001:101.100 JLINK_WriteReg(R10, 0x00000000) +T714C 001:101.119 - 0.018ms returns 0 +T714C 001:101.137 JLINK_WriteReg(R11, 0x00000000) +T714C 001:101.155 - 0.018ms returns 0 +T714C 001:101.174 JLINK_WriteReg(R12, 0x00000000) +T714C 001:101.192 - 0.017ms returns 0 +T714C 001:101.215 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:101.233 - 0.018ms returns 0 +T714C 001:101.281 JLINK_WriteReg(R14, 0x30500001) +T714C 001:101.297 - 0.017ms returns 0 +T714C 001:101.314 JLINK_WriteReg(R15 (PC), 0x30500020) +T714C 001:101.331 - 0.016ms returns 0 +T714C 001:101.348 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:101.365 - 0.016ms returns 0 +T714C 001:101.382 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:101.400 - 0.017ms returns 0 +T714C 001:101.417 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:101.434 - 0.016ms returns 0 +T714C 001:101.452 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:101.468 - 0.016ms returns 0 +T714C 001:101.485 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:101.501 - 0.016ms returns 0x00000016 +T714C 001:101.517 JLINK_Go() +T714C 001:101.537 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:101.834 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:103.719 - 2.201ms +T714C 001:103.788 JLINK_IsHalted() +T714C 001:105.957 - 2.169ms returns TRUE +T714C 001:106.015 JLINK_ReadReg(R15 (PC)) +T714C 001:106.037 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:106.316 - 0.301ms returns 0x30500000 +T714C 001:106.350 JLINK_ClrBPEx(BPHandle = 0x00000016) +T714C 001:106.368 - 0.017ms returns 0x00 +T714C 001:106.385 JLINK_ReadReg(R0) +T714C 001:106.403 - 0.017ms returns 0x00000001 +T714C 001:106.421 JLINK_HasError() +T714C 001:106.439 JLINK_WriteReg(R0, 0x28013000) +T714C 001:106.456 - 0.016ms returns 0 +T714C 001:106.472 JLINK_WriteReg(R1, 0x00001000) +T714C 001:106.488 - 0.016ms returns 0 +T714C 001:106.504 JLINK_WriteReg(R2, 0x000000FF) +T714C 001:106.520 - 0.015ms returns 0 +T714C 001:106.536 JLINK_WriteReg(R3, 0x00000000) +T714C 001:106.552 - 0.015ms returns 0 +T714C 001:106.568 JLINK_WriteReg(R4, 0x00000000) +T714C 001:106.584 - 0.016ms returns 0 +T714C 001:106.600 JLINK_WriteReg(R5, 0x00000000) +T714C 001:106.616 - 0.015ms returns 0 +T714C 001:106.632 JLINK_WriteReg(R6, 0x00000000) +T714C 001:106.647 - 0.015ms returns 0 +T714C 001:106.664 JLINK_WriteReg(R7, 0x00000000) +T714C 001:106.679 - 0.015ms returns 0 +T714C 001:106.696 JLINK_WriteReg(R8, 0x00000000) +T714C 001:106.713 - 0.017ms returns 0 +T714C 001:106.729 JLINK_WriteReg(R9, 0x30500458) +T714C 001:106.745 - 0.016ms returns 0 +T714C 001:106.762 JLINK_WriteReg(R10, 0x00000000) +T714C 001:106.777 - 0.015ms returns 0 +T714C 001:106.794 JLINK_WriteReg(R11, 0x00000000) +T714C 001:106.815 - 0.021ms returns 0 +T714C 001:106.834 JLINK_WriteReg(R12, 0x00000000) +T714C 001:106.849 - 0.016ms returns 0 +T714C 001:106.866 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:106.883 - 0.017ms returns 0 +T714C 001:106.900 JLINK_WriteReg(R14, 0x30500001) +T714C 001:106.915 - 0.015ms returns 0 +T714C 001:106.932 JLINK_WriteReg(R15 (PC), 0x30500274) +T714C 001:106.948 - 0.016ms returns 0 +T714C 001:106.964 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:106.981 - 0.016ms returns 0 +T714C 001:106.997 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:107.012 - 0.015ms returns 0 +T714C 001:107.029 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:107.044 - 0.015ms returns 0 +T714C 001:107.061 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:107.077 - 0.016ms returns 0 +T714C 001:107.096 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:107.113 - 0.017ms returns 0x00000017 +T714C 001:107.129 JLINK_Go() +T714C 001:107.148 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:107.464 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:109.503 - 2.374ms +T714C 001:109.527 JLINK_IsHalted() +T714C 001:109.718 - 0.190ms returns FALSE +T714C 001:109.738 JLINK_HasError() +T714C 001:111.563 JLINK_IsHalted() +T714C 001:111.832 - 0.269ms returns FALSE +T714C 001:111.851 JLINK_HasError() +T714C 001:113.583 JLINK_IsHalted() +T714C 001:113.838 - 0.255ms returns FALSE +T714C 001:113.859 JLINK_HasError() +T714C 001:115.481 JLINK_IsHalted() +T714C 001:115.735 - 0.253ms returns FALSE +T714C 001:115.776 JLINK_HasError() +T714C 001:117.561 JLINK_IsHalted() +T714C 001:117.871 - 0.309ms returns FALSE +T714C 001:117.893 JLINK_HasError() +T714C 001:119.852 JLINK_IsHalted() +T714C 001:120.220 - 0.366ms returns FALSE +T714C 001:120.260 JLINK_HasError() +T714C 001:122.266 JLINK_IsHalted() +T714C 001:122.714 - 0.447ms returns FALSE +T714C 001:122.759 JLINK_HasError() +T714C 001:124.844 JLINK_IsHalted() +T714C 001:125.115 - 0.270ms returns FALSE +T714C 001:125.142 JLINK_HasError() +T714C 001:126.791 JLINK_IsHalted() +T714C 001:127.080 - 0.288ms returns FALSE +T714C 001:127.103 JLINK_HasError() +T714C 001:128.807 JLINK_IsHalted() +T714C 001:129.090 - 0.282ms returns FALSE +T714C 001:129.112 JLINK_HasError() +T714C 001:130.939 JLINK_IsHalted() +T714C 001:131.339 - 0.399ms returns FALSE +T714C 001:131.387 JLINK_HasError() +T714C 001:132.928 JLINK_IsHalted() +T714C 001:133.273 - 0.344ms returns FALSE +T714C 001:133.319 JLINK_HasError() +T714C 001:134.823 JLINK_IsHalted() +T714C 001:135.210 - 0.386ms returns FALSE +T714C 001:135.255 JLINK_HasError() +T714C 001:137.306 JLINK_IsHalted() +T714C 001:137.701 - 0.395ms returns FALSE +T714C 001:137.753 JLINK_HasError() +T714C 001:139.251 JLINK_IsHalted() +T714C 001:139.618 - 0.366ms returns FALSE +T714C 001:139.667 JLINK_HasError() +T714C 001:141.238 JLINK_IsHalted() +T714C 001:141.589 - 0.350ms returns FALSE +T714C 001:141.635 JLINK_HasError() +T714C 001:143.225 JLINK_IsHalted() +T714C 001:143.629 - 0.403ms returns FALSE +T714C 001:143.675 JLINK_HasError() +T714C 001:145.231 JLINK_IsHalted() +T714C 001:145.589 - 0.357ms returns FALSE +T714C 001:145.635 JLINK_HasError() +T714C 001:147.237 JLINK_IsHalted() +T714C 001:147.588 - 0.351ms returns FALSE +T714C 001:147.636 JLINK_HasError() +T714C 001:149.331 JLINK_IsHalted() +T714C 001:149.689 - 0.357ms returns FALSE +T714C 001:149.737 JLINK_HasError() +T714C 001:151.082 JLINK_IsHalted() +T714C 001:153.405 - 2.322ms returns TRUE +T714C 001:154.126 JLINK_ReadReg(R15 (PC)) +T714C 001:154.184 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:154.442 - 0.316ms returns 0x30500000 +T714C 001:154.470 JLINK_ClrBPEx(BPHandle = 0x00000017) +T714C 001:154.487 - 0.017ms returns 0x00 +T714C 001:154.504 JLINK_ReadReg(R0) +T714C 001:154.522 - 0.018ms returns 0x00000000 +T714C 001:155.187 JLINK_HasError() +T714C 001:155.222 JLINK_WriteReg(R0, 0x28014000) +T714C 001:155.243 - 0.020ms returns 0 +T714C 001:155.260 JLINK_WriteReg(R1, 0x00001000) +T714C 001:155.276 - 0.017ms returns 0 +T714C 001:155.294 JLINK_WriteReg(R2, 0x000000FF) +T714C 001:155.310 - 0.016ms returns 0 +T714C 001:155.327 JLINK_WriteReg(R3, 0x00000000) +T714C 001:155.349 - 0.021ms returns 0 +T714C 001:155.368 JLINK_WriteReg(R4, 0x00000000) +T714C 001:155.384 - 0.016ms returns 0 +T714C 001:155.400 JLINK_WriteReg(R5, 0x00000000) +T714C 001:155.416 - 0.015ms returns 0 +T714C 001:155.432 JLINK_WriteReg(R6, 0x00000000) +T714C 001:155.449 - 0.016ms returns 0 +T714C 001:155.465 JLINK_WriteReg(R7, 0x00000000) +T714C 001:155.482 - 0.016ms returns 0 +T714C 001:155.498 JLINK_WriteReg(R8, 0x00000000) +T714C 001:155.514 - 0.016ms returns 0 +T714C 001:155.530 JLINK_WriteReg(R9, 0x30500458) +T714C 001:155.546 - 0.015ms returns 0 +T714C 001:155.562 JLINK_WriteReg(R10, 0x00000000) +T714C 001:155.578 - 0.016ms returns 0 +T714C 001:155.594 JLINK_WriteReg(R11, 0x00000000) +T714C 001:155.610 - 0.016ms returns 0 +T714C 001:155.627 JLINK_WriteReg(R12, 0x00000000) +T714C 001:155.643 - 0.015ms returns 0 +T714C 001:155.659 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:155.676 - 0.017ms returns 0 +T714C 001:155.692 JLINK_WriteReg(R14, 0x30500001) +T714C 001:155.708 - 0.016ms returns 0 +T714C 001:155.725 JLINK_WriteReg(R15 (PC), 0x30500020) +T714C 001:155.741 - 0.015ms returns 0 +T714C 001:155.757 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:155.773 - 0.016ms returns 0 +T714C 001:155.790 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:155.806 - 0.016ms returns 0 +T714C 001:155.822 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:155.837 - 0.015ms returns 0 +T714C 001:155.854 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:155.870 - 0.016ms returns 0 +T714C 001:155.887 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:155.903 - 0.016ms returns 0x00000018 +T714C 001:155.919 JLINK_Go() +T714C 001:155.939 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:156.239 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:158.310 - 2.390ms +T714C 001:158.363 JLINK_IsHalted() +T714C 001:160.667 - 2.304ms returns TRUE +T714C 001:160.717 JLINK_ReadReg(R15 (PC)) +T714C 001:160.739 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:161.033 - 0.315ms returns 0x30500000 +T714C 001:161.080 JLINK_ClrBPEx(BPHandle = 0x00000018) +T714C 001:161.098 - 0.018ms returns 0x00 +T714C 001:161.116 JLINK_ReadReg(R0) +T714C 001:161.133 - 0.017ms returns 0x00000001 +T714C 001:161.150 JLINK_HasError() +T714C 001:161.167 JLINK_WriteReg(R0, 0x28014000) +T714C 001:161.183 - 0.016ms returns 0 +T714C 001:161.199 JLINK_WriteReg(R1, 0x00001000) +T714C 001:161.215 - 0.015ms returns 0 +T714C 001:161.231 JLINK_WriteReg(R2, 0x000000FF) +T714C 001:161.246 - 0.015ms returns 0 +T714C 001:161.262 JLINK_WriteReg(R3, 0x00000000) +T714C 001:161.278 - 0.016ms returns 0 +T714C 001:161.294 JLINK_WriteReg(R4, 0x00000000) +T714C 001:161.310 - 0.015ms returns 0 +T714C 001:161.326 JLINK_WriteReg(R5, 0x00000000) +T714C 001:161.342 - 0.015ms returns 0 +T714C 001:161.358 JLINK_WriteReg(R6, 0x00000000) +T714C 001:161.374 - 0.015ms returns 0 +T714C 001:161.390 JLINK_WriteReg(R7, 0x00000000) +T714C 001:161.405 - 0.015ms returns 0 +T714C 001:161.421 JLINK_WriteReg(R8, 0x00000000) +T714C 001:161.437 - 0.016ms returns 0 +T714C 001:161.452 JLINK_WriteReg(R9, 0x30500458) +T714C 001:161.468 - 0.015ms returns 0 +T714C 001:161.484 JLINK_WriteReg(R10, 0x00000000) +T714C 001:161.500 - 0.016ms returns 0 +T714C 001:161.516 JLINK_WriteReg(R11, 0x00000000) +T714C 001:161.531 - 0.015ms returns 0 +T714C 001:161.547 JLINK_WriteReg(R12, 0x00000000) +T714C 001:161.563 - 0.015ms returns 0 +T714C 001:161.578 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:161.595 - 0.017ms returns 0 +T714C 001:161.611 JLINK_WriteReg(R14, 0x30500001) +T714C 001:161.627 - 0.015ms returns 0 +T714C 001:161.643 JLINK_WriteReg(R15 (PC), 0x30500274) +T714C 001:161.659 - 0.016ms returns 0 +T714C 001:161.675 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:161.691 - 0.015ms returns 0 +T714C 001:161.707 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:161.747 - 0.039ms returns 0 +T714C 001:161.763 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:161.778 - 0.015ms returns 0 +T714C 001:161.794 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:161.809 - 0.015ms returns 0 +T714C 001:161.826 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:161.846 - 0.020ms returns 0x00000019 +T714C 001:161.864 JLINK_Go() +T714C 001:161.881 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:162.174 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:164.279 - 2.413ms +T714C 001:164.367 JLINK_IsHalted() +T714C 001:164.711 - 0.343ms returns FALSE +T714C 001:164.760 JLINK_HasError() +T714C 001:166.275 JLINK_IsHalted() +T714C 001:166.733 - 0.457ms returns FALSE +T714C 001:166.786 JLINK_HasError() +T714C 001:168.473 JLINK_IsHalted() +T714C 001:168.828 - 0.354ms returns FALSE +T714C 001:168.875 JLINK_HasError() +T714C 001:170.453 JLINK_IsHalted() +T714C 001:170.754 - 0.300ms returns FALSE +T714C 001:170.801 JLINK_HasError() +T714C 001:172.449 JLINK_IsHalted() +T714C 001:172.767 - 0.317ms returns FALSE +T714C 001:172.815 JLINK_HasError() +T714C 001:174.456 JLINK_IsHalted() +T714C 001:174.791 - 0.334ms returns FALSE +T714C 001:174.839 JLINK_HasError() +T714C 001:176.449 JLINK_IsHalted() +T714C 001:176.781 - 0.331ms returns FALSE +T714C 001:176.828 JLINK_HasError() +T714C 001:178.451 JLINK_IsHalted() +T714C 001:178.811 - 0.360ms returns FALSE +T714C 001:178.859 JLINK_HasError() +T714C 001:180.795 JLINK_IsHalted() +T714C 001:181.124 - 0.327ms returns FALSE +T714C 001:181.153 JLINK_HasError() +T714C 001:183.787 JLINK_IsHalted() +T714C 001:184.075 - 0.287ms returns FALSE +T714C 001:184.123 JLINK_HasError() +T714C 001:186.813 JLINK_IsHalted() +T714C 001:187.114 - 0.300ms returns FALSE +T714C 001:187.145 JLINK_HasError() +T714C 001:188.810 JLINK_IsHalted() +T714C 001:189.097 - 0.285ms returns FALSE +T714C 001:189.123 JLINK_HasError() +T714C 001:190.812 JLINK_IsHalted() +T714C 001:191.071 - 0.258ms returns FALSE +T714C 001:191.096 JLINK_HasError() +T714C 001:192.813 JLINK_IsHalted() +T714C 001:193.071 - 0.257ms returns FALSE +T714C 001:193.096 JLINK_HasError() +T714C 001:195.789 JLINK_IsHalted() +T714C 001:196.116 - 0.326ms returns FALSE +T714C 001:196.141 JLINK_HasError() +T714C 001:198.820 JLINK_IsHalted() +T714C 001:199.111 - 0.289ms returns FALSE +T714C 001:199.166 JLINK_HasError() +T714C 001:200.813 JLINK_IsHalted() +T714C 001:201.074 - 0.260ms returns FALSE +T714C 001:201.100 JLINK_HasError() +T714C 001:202.810 JLINK_IsHalted() +T714C 001:203.086 - 0.275ms returns FALSE +T714C 001:203.114 JLINK_HasError() +T714C 001:205.818 JLINK_IsHalted() +T714C 001:206.083 - 0.264ms returns FALSE +T714C 001:206.126 JLINK_HasError() +T714C 001:207.812 JLINK_IsHalted() +T714C 001:208.072 - 0.260ms returns FALSE +T714C 001:208.097 JLINK_HasError() +T714C 001:209.787 JLINK_IsHalted() +T714C 001:210.135 - 0.346ms returns FALSE +T714C 001:210.193 JLINK_HasError() +T714C 001:214.854 JLINK_IsHalted() +T714C 001:215.195 - 0.340ms returns FALSE +T714C 001:215.225 JLINK_HasError() +T714C 001:216.850 JLINK_IsHalted() +T714C 001:217.119 - 0.268ms returns FALSE +T714C 001:217.209 JLINK_HasError() +T714C 001:219.847 JLINK_IsHalted() +T714C 001:221.963 - 2.114ms returns TRUE +T714C 001:221.996 JLINK_ReadReg(R15 (PC)) +T714C 001:222.018 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:222.265 - 0.268ms returns 0x30500000 +T714C 001:222.287 JLINK_ClrBPEx(BPHandle = 0x00000019) +T714C 001:222.304 - 0.017ms returns 0x00 +T714C 001:222.321 JLINK_ReadReg(R0) +T714C 001:222.338 - 0.017ms returns 0x00000000 +T714C 001:222.855 JLINK_HasError() +T714C 001:222.895 JLINK_WriteReg(R0, 0x28015000) +T714C 001:222.916 - 0.021ms returns 0 +T714C 001:222.934 JLINK_WriteReg(R1, 0x00001000) +T714C 001:222.950 - 0.016ms returns 0 +T714C 001:222.967 JLINK_WriteReg(R2, 0x000000FF) +T714C 001:222.983 - 0.016ms returns 0 +T714C 001:223.000 JLINK_WriteReg(R3, 0x00000000) +T714C 001:223.016 - 0.015ms returns 0 +T714C 001:223.032 JLINK_WriteReg(R4, 0x00000000) +T714C 001:223.048 - 0.016ms returns 0 +T714C 001:223.065 JLINK_WriteReg(R5, 0x00000000) +T714C 001:223.081 - 0.016ms returns 0 +T714C 001:223.097 JLINK_WriteReg(R6, 0x00000000) +T714C 001:223.114 - 0.016ms returns 0 +T714C 001:223.130 JLINK_WriteReg(R7, 0x00000000) +T714C 001:223.146 - 0.015ms returns 0 +T714C 001:223.162 JLINK_WriteReg(R8, 0x00000000) +T714C 001:223.179 - 0.016ms returns 0 +T714C 001:223.205 JLINK_WriteReg(R9, 0x30500458) +T714C 001:223.222 - 0.016ms returns 0 +T714C 001:223.238 JLINK_WriteReg(R10, 0x00000000) +T714C 001:223.255 - 0.016ms returns 0 +T714C 001:223.271 JLINK_WriteReg(R11, 0x00000000) +T714C 001:223.287 - 0.015ms returns 0 +T714C 001:223.303 JLINK_WriteReg(R12, 0x00000000) +T714C 001:223.319 - 0.015ms returns 0 +T714C 001:223.336 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:223.353 - 0.017ms returns 0 +T714C 001:223.370 JLINK_WriteReg(R14, 0x30500001) +T714C 001:223.386 - 0.016ms returns 0 +T714C 001:223.403 JLINK_WriteReg(R15 (PC), 0x30500020) +T714C 001:223.419 - 0.016ms returns 0 +T714C 001:223.436 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:223.452 - 0.015ms returns 0 +T714C 001:223.469 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:223.485 - 0.016ms returns 0 +T714C 001:223.501 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:223.517 - 0.015ms returns 0 +T714C 001:223.534 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:223.551 - 0.016ms returns 0 +T714C 001:223.568 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:223.584 - 0.017ms returns 0x0000001A +T714C 001:223.601 JLINK_Go() +T714C 001:223.620 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:223.849 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:225.732 - 2.130ms +T714C 001:225.786 JLINK_IsHalted() +T714C 001:227.847 - 2.060ms returns TRUE +T714C 001:227.886 JLINK_ReadReg(R15 (PC)) +T714C 001:227.907 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:228.152 - 0.266ms returns 0x30500000 +T714C 001:228.174 JLINK_ClrBPEx(BPHandle = 0x0000001A) +T714C 001:228.191 - 0.016ms returns 0x00 +T714C 001:228.208 JLINK_ReadReg(R0) +T714C 001:228.225 - 0.017ms returns 0x00000001 +T714C 001:228.242 JLINK_HasError() +T714C 001:228.259 JLINK_WriteReg(R0, 0x28015000) +T714C 001:228.276 - 0.017ms returns 0 +T714C 001:228.292 JLINK_WriteReg(R1, 0x00001000) +T714C 001:228.309 - 0.016ms returns 0 +T714C 001:228.325 JLINK_WriteReg(R2, 0x000000FF) +T714C 001:228.341 - 0.015ms returns 0 +T714C 001:228.358 JLINK_WriteReg(R3, 0x00000000) +T714C 001:228.374 - 0.015ms returns 0 +T714C 001:228.390 JLINK_WriteReg(R4, 0x00000000) +T714C 001:228.407 - 0.016ms returns 0 +T714C 001:228.423 JLINK_WriteReg(R5, 0x00000000) +T714C 001:228.439 - 0.016ms returns 0 +T714C 001:228.456 JLINK_WriteReg(R6, 0x00000000) +T714C 001:228.472 - 0.016ms returns 0 +T714C 001:228.488 JLINK_WriteReg(R7, 0x00000000) +T714C 001:228.504 - 0.015ms returns 0 +T714C 001:228.520 JLINK_WriteReg(R8, 0x00000000) +T714C 001:228.536 - 0.016ms returns 0 +T714C 001:228.580 JLINK_WriteReg(R9, 0x30500458) +T714C 001:228.596 - 0.015ms returns 0 +T714C 001:228.612 JLINK_WriteReg(R10, 0x00000000) +T714C 001:228.628 - 0.015ms returns 0 +T714C 001:228.644 JLINK_WriteReg(R11, 0x00000000) +T714C 001:228.659 - 0.015ms returns 0 +T714C 001:228.675 JLINK_WriteReg(R12, 0x00000000) +T714C 001:228.691 - 0.015ms returns 0 +T714C 001:228.708 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:228.724 - 0.016ms returns 0 +T714C 001:228.740 JLINK_WriteReg(R14, 0x30500001) +T714C 001:228.756 - 0.015ms returns 0 +T714C 001:228.773 JLINK_WriteReg(R15 (PC), 0x30500274) +T714C 001:228.789 - 0.016ms returns 0 +T714C 001:228.805 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:228.821 - 0.016ms returns 0 +T714C 001:228.837 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:228.853 - 0.015ms returns 0 +T714C 001:228.869 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:228.885 - 0.015ms returns 0 +T714C 001:228.901 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:228.917 - 0.015ms returns 0 +T714C 001:228.933 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:228.949 - 0.016ms returns 0x0000001B +T714C 001:228.965 JLINK_Go() +T714C 001:228.984 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:229.231 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:231.235 - 2.269ms +T714C 001:231.279 JLINK_IsHalted() +T714C 001:231.574 - 0.295ms returns FALSE +T714C 001:231.599 JLINK_HasError() +T714C 001:234.180 JLINK_IsHalted() +T714C 001:234.508 - 0.327ms returns FALSE +T714C 001:234.533 JLINK_HasError() +T714C 001:237.178 JLINK_IsHalted() +T714C 001:237.446 - 0.267ms returns FALSE +T714C 001:237.474 JLINK_HasError() +T714C 001:239.172 JLINK_IsHalted() +T714C 001:239.437 - 0.264ms returns FALSE +T714C 001:239.460 JLINK_HasError() +T714C 001:241.186 JLINK_IsHalted() +T714C 001:241.579 - 0.392ms returns FALSE +T714C 001:241.603 JLINK_HasError() +T714C 001:243.157 JLINK_IsHalted() +T714C 001:243.411 - 0.254ms returns FALSE +T714C 001:243.432 JLINK_HasError() +T714C 001:245.150 JLINK_IsHalted() +T714C 001:245.374 - 0.223ms returns FALSE +T714C 001:245.402 JLINK_HasError() +T714C 001:247.151 JLINK_IsHalted() +T714C 001:247.433 - 0.282ms returns FALSE +T714C 001:247.454 JLINK_HasError() +T714C 001:249.259 JLINK_IsHalted() +T714C 001:249.598 - 0.339ms returns FALSE +T714C 001:249.653 JLINK_HasError() +T714C 001:251.221 JLINK_IsHalted() +T714C 001:251.577 - 0.356ms returns FALSE +T714C 001:251.613 JLINK_HasError() +T714C 001:253.213 JLINK_IsHalted() +T714C 001:253.481 - 0.267ms returns FALSE +T714C 001:253.503 JLINK_HasError() +T714C 001:255.246 JLINK_IsHalted() +T714C 001:255.599 - 0.351ms returns FALSE +T714C 001:255.700 JLINK_HasError() +T714C 001:257.165 JLINK_IsHalted() +T714C 001:257.499 - 0.334ms returns FALSE +T714C 001:257.529 JLINK_HasError() +T714C 001:259.157 JLINK_IsHalted() +T714C 001:259.447 - 0.289ms returns FALSE +T714C 001:259.492 JLINK_HasError() +T714C 001:261.161 JLINK_IsHalted() +T714C 001:261.421 - 0.259ms returns FALSE +T714C 001:261.442 JLINK_HasError() +T714C 001:263.181 JLINK_IsHalted() +T714C 001:263.420 - 0.239ms returns FALSE +T714C 001:263.443 JLINK_HasError() +T714C 001:266.230 JLINK_IsHalted() +T714C 001:266.702 - 0.471ms returns FALSE +T714C 001:266.777 JLINK_HasError() +T714C 001:268.191 JLINK_IsHalted() +T714C 001:268.486 - 0.295ms returns FALSE +T714C 001:268.509 JLINK_HasError() +T714C 001:270.152 JLINK_IsHalted() +T714C 001:270.505 - 0.352ms returns FALSE +T714C 001:270.562 JLINK_HasError() +T714C 001:272.894 JLINK_IsHalted() +T714C 001:273.256 - 0.362ms returns FALSE +T714C 001:273.283 JLINK_HasError() +T714C 001:276.036 JLINK_IsHalted() +T714C 001:278.170 - 2.132ms returns TRUE +T714C 001:278.200 JLINK_ReadReg(R15 (PC)) +T714C 001:278.221 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:278.482 - 0.282ms returns 0x30500000 +T714C 001:278.504 JLINK_ClrBPEx(BPHandle = 0x0000001B) +T714C 001:278.521 - 0.017ms returns 0x00 +T714C 001:278.538 JLINK_ReadReg(R0) +T714C 001:278.556 - 0.017ms returns 0x00000000 +T714C 001:279.128 JLINK_HasError() +T714C 001:279.167 JLINK_WriteReg(R0, 0x28016000) +T714C 001:279.186 - 0.019ms returns 0 +T714C 001:279.203 JLINK_WriteReg(R1, 0x00001000) +T714C 001:279.220 - 0.016ms returns 0 +T714C 001:279.236 JLINK_WriteReg(R2, 0x000000FF) +T714C 001:279.252 - 0.016ms returns 0 +T714C 001:279.269 JLINK_WriteReg(R3, 0x00000000) +T714C 001:279.284 - 0.015ms returns 0 +T714C 001:279.301 JLINK_WriteReg(R4, 0x00000000) +T714C 001:279.317 - 0.015ms returns 0 +T714C 001:279.333 JLINK_WriteReg(R5, 0x00000000) +T714C 001:279.349 - 0.016ms returns 0 +T714C 001:279.365 JLINK_WriteReg(R6, 0x00000000) +T714C 001:279.381 - 0.015ms returns 0 +T714C 001:279.397 JLINK_WriteReg(R7, 0x00000000) +T714C 001:279.413 - 0.016ms returns 0 +T714C 001:279.430 JLINK_WriteReg(R8, 0x00000000) +T714C 001:279.446 - 0.016ms returns 0 +T714C 001:279.462 JLINK_WriteReg(R9, 0x30500458) +T714C 001:279.479 - 0.016ms returns 0 +T714C 001:279.495 JLINK_WriteReg(R10, 0x00000000) +T714C 001:279.511 - 0.015ms returns 0 +T714C 001:279.527 JLINK_WriteReg(R11, 0x00000000) +T714C 001:279.543 - 0.015ms returns 0 +T714C 001:279.559 JLINK_WriteReg(R12, 0x00000000) +T714C 001:279.575 - 0.016ms returns 0 +T714C 001:279.592 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:279.608 - 0.016ms returns 0 +T714C 001:279.624 JLINK_WriteReg(R14, 0x30500001) +T714C 001:279.640 - 0.015ms returns 0 +T714C 001:279.657 JLINK_WriteReg(R15 (PC), 0x30500020) +T714C 001:279.673 - 0.015ms returns 0 +T714C 001:279.689 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:279.705 - 0.016ms returns 0 +T714C 001:279.721 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:279.737 - 0.016ms returns 0 +T714C 001:279.761 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:279.777 - 0.015ms returns 0 +T714C 001:279.793 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:279.809 - 0.016ms returns 0 +T714C 001:279.827 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:279.844 - 0.017ms returns 0x0000001C +T714C 001:279.860 JLINK_Go() +T714C 001:279.879 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:280.171 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:282.100 - 2.239ms +T714C 001:282.136 JLINK_IsHalted() +T714C 001:284.355 - 2.218ms returns TRUE +T714C 001:284.414 JLINK_ReadReg(R15 (PC)) +T714C 001:284.435 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:284.662 - 0.248ms returns 0x30500000 +T714C 001:284.688 JLINK_ClrBPEx(BPHandle = 0x0000001C) +T714C 001:284.706 - 0.018ms returns 0x00 +T714C 001:284.725 JLINK_ReadReg(R0) +T714C 001:284.744 - 0.019ms returns 0x00000001 +T714C 001:284.764 JLINK_HasError() +T714C 001:284.784 JLINK_WriteReg(R0, 0x28016000) +T714C 001:284.802 - 0.017ms returns 0 +T714C 001:284.820 JLINK_WriteReg(R1, 0x00001000) +T714C 001:284.837 - 0.017ms returns 0 +T714C 001:284.855 JLINK_WriteReg(R2, 0x000000FF) +T714C 001:284.873 - 0.017ms returns 0 +T714C 001:284.891 JLINK_WriteReg(R3, 0x00000000) +T714C 001:284.908 - 0.017ms returns 0 +T714C 001:284.926 JLINK_WriteReg(R4, 0x00000000) +T714C 001:284.943 - 0.017ms returns 0 +T714C 001:284.962 JLINK_WriteReg(R5, 0x00000000) +T714C 001:284.979 - 0.017ms returns 0 +T714C 001:284.997 JLINK_WriteReg(R6, 0x00000000) +T714C 001:285.014 - 0.017ms returns 0 +T714C 001:285.033 JLINK_WriteReg(R7, 0x00000000) +T714C 001:285.049 - 0.016ms returns 0 +T714C 001:285.069 JLINK_WriteReg(R8, 0x00000000) +T714C 001:285.085 - 0.016ms returns 0 +T714C 001:285.103 JLINK_WriteReg(R9, 0x30500458) +T714C 001:285.119 - 0.016ms returns 0 +T714C 001:285.136 JLINK_WriteReg(R10, 0x00000000) +T714C 001:285.153 - 0.016ms returns 0 +T714C 001:285.170 JLINK_WriteReg(R11, 0x00000000) +T714C 001:285.185 - 0.015ms returns 0 +T714C 001:285.202 JLINK_WriteReg(R12, 0x00000000) +T714C 001:285.218 - 0.015ms returns 0 +T714C 001:285.234 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:285.252 - 0.017ms returns 0 +T714C 001:285.269 JLINK_WriteReg(R14, 0x30500001) +T714C 001:285.291 - 0.022ms returns 0 +T714C 001:285.315 JLINK_WriteReg(R15 (PC), 0x30500274) +T714C 001:285.338 - 0.023ms returns 0 +T714C 001:285.438 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:285.457 - 0.019ms returns 0 +T714C 001:285.477 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:285.495 - 0.017ms returns 0 +T714C 001:285.513 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:285.529 - 0.016ms returns 0 +T714C 001:285.548 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:285.564 - 0.016ms returns 0 +T714C 001:285.582 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:285.598 - 0.016ms returns 0x0000001D +T714C 001:285.616 JLINK_Go() +T714C 001:285.636 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:285.946 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:287.874 - 2.256ms +T714C 001:287.954 JLINK_IsHalted() +T714C 001:288.214 - 0.259ms returns FALSE +T714C 001:288.249 JLINK_HasError() +T714C 001:291.775 JLINK_IsHalted() +T714C 001:292.062 - 0.286ms returns FALSE +T714C 001:292.086 JLINK_HasError() +T714C 001:293.773 JLINK_IsHalted() +T714C 001:294.026 - 0.252ms returns FALSE +T714C 001:294.047 JLINK_HasError() +T714C 001:295.775 JLINK_IsHalted() +T714C 001:296.002 - 0.226ms returns FALSE +T714C 001:296.021 JLINK_HasError() +T714C 001:297.875 JLINK_IsHalted() +T714C 001:298.102 - 0.227ms returns FALSE +T714C 001:298.125 JLINK_HasError() +T714C 001:299.773 JLINK_IsHalted() +T714C 001:300.159 - 0.385ms returns FALSE +T714C 001:300.206 JLINK_HasError() +T714C 001:301.780 JLINK_IsHalted() +T714C 001:302.049 - 0.269ms returns FALSE +T714C 001:302.071 JLINK_HasError() +T714C 001:303.777 JLINK_IsHalted() +T714C 001:304.026 - 0.249ms returns FALSE +T714C 001:304.048 JLINK_HasError() +T714C 001:305.770 JLINK_IsHalted() +T714C 001:306.026 - 0.255ms returns FALSE +T714C 001:306.046 JLINK_HasError() +T714C 001:307.777 JLINK_IsHalted() +T714C 001:308.026 - 0.248ms returns FALSE +T714C 001:308.048 JLINK_HasError() +T714C 001:309.776 JLINK_IsHalted() +T714C 001:310.026 - 0.249ms returns FALSE +T714C 001:310.047 JLINK_HasError() +T714C 001:311.810 JLINK_IsHalted() +T714C 001:312.058 - 0.248ms returns FALSE +T714C 001:312.081 JLINK_HasError() +T714C 001:314.468 JLINK_IsHalted() +T714C 001:314.742 - 0.274ms returns FALSE +T714C 001:314.781 JLINK_HasError() +T714C 001:315.905 JLINK_IsHalted() +T714C 001:316.199 - 0.293ms returns FALSE +T714C 001:316.226 JLINK_HasError() +T714C 001:317.966 JLINK_IsHalted() +T714C 001:318.247 - 0.280ms returns FALSE +T714C 001:318.271 JLINK_HasError() +T714C 001:319.994 JLINK_IsHalted() +T714C 001:320.244 - 0.249ms returns FALSE +T714C 001:320.291 JLINK_HasError() +T714C 001:321.993 JLINK_IsHalted() +T714C 001:322.256 - 0.262ms returns FALSE +T714C 001:322.279 JLINK_HasError() +T714C 001:324.000 JLINK_IsHalted() +T714C 001:324.249 - 0.249ms returns FALSE +T714C 001:324.270 JLINK_HasError() +T714C 001:325.536 JLINK_IsHalted() +T714C 001:325.776 - 0.239ms returns FALSE +T714C 001:325.796 JLINK_HasError() +T714C 001:327.580 JLINK_IsHalted() +T714C 001:327.808 - 0.227ms returns FALSE +T714C 001:327.828 JLINK_HasError() +T714C 001:329.735 JLINK_IsHalted() +T714C 001:330.081 - 0.346ms returns FALSE +T714C 001:330.120 JLINK_HasError() +T714C 001:331.564 JLINK_IsHalted() +T714C 001:333.763 - 2.198ms returns TRUE +T714C 001:333.804 JLINK_ReadReg(R15 (PC)) +T714C 001:333.824 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:334.077 - 0.273ms returns 0x30500000 +T714C 001:334.099 JLINK_ClrBPEx(BPHandle = 0x0000001D) +T714C 001:334.116 - 0.016ms returns 0x00 +T714C 001:334.133 JLINK_ReadReg(R0) +T714C 001:334.150 - 0.017ms returns 0x00000000 +T714C 001:334.787 JLINK_HasError() +T714C 001:334.823 JLINK_WriteReg(R0, 0x28017000) +T714C 001:334.843 - 0.020ms returns 0 +T714C 001:334.860 JLINK_WriteReg(R1, 0x00001000) +T714C 001:334.876 - 0.015ms returns 0 +T714C 001:334.892 JLINK_WriteReg(R2, 0x000000FF) +T714C 001:334.909 - 0.016ms returns 0 +T714C 001:334.926 JLINK_WriteReg(R3, 0x00000000) +T714C 001:334.942 - 0.016ms returns 0 +T714C 001:334.959 JLINK_WriteReg(R4, 0x00000000) +T714C 001:334.974 - 0.015ms returns 0 +T714C 001:334.991 JLINK_WriteReg(R5, 0x00000000) +T714C 001:335.006 - 0.015ms returns 0 +T714C 001:335.022 JLINK_WriteReg(R6, 0x00000000) +T714C 001:335.039 - 0.017ms returns 0 +T714C 001:335.056 JLINK_WriteReg(R7, 0x00000000) +T714C 001:335.072 - 0.016ms returns 0 +T714C 001:335.088 JLINK_WriteReg(R8, 0x00000000) +T714C 001:335.104 - 0.015ms returns 0 +T714C 001:335.120 JLINK_WriteReg(R9, 0x30500458) +T714C 001:335.137 - 0.016ms returns 0 +T714C 001:335.153 JLINK_WriteReg(R10, 0x00000000) +T714C 001:335.169 - 0.016ms returns 0 +T714C 001:335.185 JLINK_WriteReg(R11, 0x00000000) +T714C 001:335.201 - 0.015ms returns 0 +T714C 001:335.217 JLINK_WriteReg(R12, 0x00000000) +T714C 001:335.233 - 0.015ms returns 0 +T714C 001:335.249 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:335.266 - 0.016ms returns 0 +T714C 001:335.283 JLINK_WriteReg(R14, 0x30500001) +T714C 001:335.299 - 0.015ms returns 0 +T714C 001:335.315 JLINK_WriteReg(R15 (PC), 0x30500020) +T714C 001:335.331 - 0.015ms returns 0 +T714C 001:335.347 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:335.363 - 0.016ms returns 0 +T714C 001:335.379 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:335.395 - 0.015ms returns 0 +T714C 001:335.411 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:335.427 - 0.015ms returns 0 +T714C 001:335.444 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:335.459 - 0.015ms returns 0 +T714C 001:335.476 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:335.493 - 0.017ms returns 0x0000001E +T714C 001:335.509 JLINK_Go() +T714C 001:335.528 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:335.786 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:337.724 - 2.215ms +T714C 001:337.747 JLINK_IsHalted() +T714C 001:339.869 - 2.121ms returns TRUE +T714C 001:340.504 JLINK_ReadReg(R15 (PC)) +T714C 001:340.525 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:340.778 - 0.273ms returns 0x30500000 +T714C 001:340.802 JLINK_ClrBPEx(BPHandle = 0x0000001E) +T714C 001:340.821 - 0.018ms returns 0x00 +T714C 001:340.838 JLINK_ReadReg(R0) +T714C 001:340.854 - 0.016ms returns 0x00000001 +T714C 001:340.870 JLINK_HasError() +T714C 001:340.887 JLINK_WriteReg(R0, 0x28017000) +T714C 001:340.903 - 0.016ms returns 0 +T714C 001:340.919 JLINK_WriteReg(R1, 0x00001000) +T714C 001:340.935 - 0.015ms returns 0 +T714C 001:340.952 JLINK_WriteReg(R2, 0x000000FF) +T714C 001:340.967 - 0.015ms returns 0 +T714C 001:340.983 JLINK_WriteReg(R3, 0x00000000) +T714C 001:341.000 - 0.016ms returns 0 +T714C 001:341.017 JLINK_WriteReg(R4, 0x00000000) +T714C 001:341.033 - 0.016ms returns 0 +T714C 001:341.049 JLINK_WriteReg(R5, 0x00000000) +T714C 001:341.065 - 0.015ms returns 0 +T714C 001:341.081 JLINK_WriteReg(R6, 0x00000000) +T714C 001:341.097 - 0.016ms returns 0 +T714C 001:341.113 JLINK_WriteReg(R7, 0x00000000) +T714C 001:341.129 - 0.015ms returns 0 +T714C 001:341.145 JLINK_WriteReg(R8, 0x00000000) +T714C 001:341.161 - 0.015ms returns 0 +T714C 001:341.178 JLINK_WriteReg(R9, 0x30500458) +T714C 001:341.194 - 0.015ms returns 0 +T714C 001:341.210 JLINK_WriteReg(R10, 0x00000000) +T714C 001:341.226 - 0.015ms returns 0 +T714C 001:341.242 JLINK_WriteReg(R11, 0x00000000) +T714C 001:341.258 - 0.016ms returns 0 +T714C 001:341.275 JLINK_WriteReg(R12, 0x00000000) +T714C 001:341.290 - 0.015ms returns 0 +T714C 001:341.306 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:341.323 - 0.016ms returns 0 +T714C 001:341.339 JLINK_WriteReg(R14, 0x30500001) +T714C 001:341.355 - 0.016ms returns 0 +T714C 001:341.371 JLINK_WriteReg(R15 (PC), 0x30500274) +T714C 001:341.386 - 0.015ms returns 0 +T714C 001:341.403 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:341.418 - 0.015ms returns 0 +T714C 001:341.434 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:341.450 - 0.016ms returns 0 +T714C 001:341.466 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:341.482 - 0.015ms returns 0 +T714C 001:341.498 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:341.514 - 0.015ms returns 0 +T714C 001:341.531 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:341.546 - 0.016ms returns 0x0000001F +T714C 001:341.562 JLINK_Go() +T714C 001:341.579 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:341.841 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:343.747 - 2.184ms +T714C 001:343.773 JLINK_IsHalted() +T714C 001:344.026 - 0.252ms returns FALSE +T714C 001:344.046 JLINK_HasError() +T714C 001:345.590 JLINK_IsHalted() +T714C 001:345.969 - 0.378ms returns FALSE +T714C 001:346.019 JLINK_HasError() +T714C 001:347.935 JLINK_IsHalted() +T714C 001:348.219 - 0.283ms returns FALSE +T714C 001:348.277 JLINK_HasError() +T714C 001:349.912 JLINK_IsHalted() +T714C 001:350.155 - 0.242ms returns FALSE +T714C 001:350.176 JLINK_HasError() +T714C 001:351.870 JLINK_IsHalted() +T714C 001:352.166 - 0.295ms returns FALSE +T714C 001:352.196 JLINK_HasError() +T714C 001:354.870 JLINK_IsHalted() +T714C 001:355.162 - 0.292ms returns FALSE +T714C 001:355.186 JLINK_HasError() +T714C 001:356.872 JLINK_IsHalted() +T714C 001:357.161 - 0.288ms returns FALSE +T714C 001:357.182 JLINK_HasError() +T714C 001:358.866 JLINK_IsHalted() +T714C 001:359.113 - 0.247ms returns FALSE +T714C 001:359.133 JLINK_HasError() +T714C 001:361.090 JLINK_IsHalted() +T714C 001:361.444 - 0.354ms returns FALSE +T714C 001:361.477 JLINK_HasError() +T714C 001:363.627 JLINK_IsHalted() +T714C 001:363.976 - 0.346ms returns FALSE +T714C 001:364.068 JLINK_HasError() +T714C 001:365.633 JLINK_IsHalted() +T714C 001:365.968 - 0.334ms returns FALSE +T714C 001:366.000 JLINK_HasError() +T714C 001:367.624 JLINK_IsHalted() +T714C 001:367.905 - 0.279ms returns FALSE +T714C 001:368.048 JLINK_HasError() +T714C 001:369.668 JLINK_IsHalted() +T714C 001:369.967 - 0.298ms returns FALSE +T714C 001:370.000 JLINK_HasError() +T714C 001:371.651 JLINK_IsHalted() +T714C 001:371.952 - 0.300ms returns FALSE +T714C 001:371.996 JLINK_HasError() +T714C 001:373.622 JLINK_IsHalted() +T714C 001:373.888 - 0.264ms returns FALSE +T714C 001:374.008 JLINK_HasError() +T714C 001:376.003 JLINK_IsHalted() +T714C 001:376.316 - 0.313ms returns FALSE +T714C 001:376.355 JLINK_HasError() +T714C 001:378.055 JLINK_IsHalted() +T714C 001:378.362 - 0.307ms returns FALSE +T714C 001:378.387 JLINK_HasError() +T714C 001:380.056 JLINK_IsHalted() +T714C 001:380.342 - 0.286ms returns FALSE +T714C 001:380.365 JLINK_HasError() +T714C 001:382.089 JLINK_IsHalted() +T714C 001:382.343 - 0.254ms returns FALSE +T714C 001:382.367 JLINK_HasError() +T714C 001:384.085 JLINK_IsHalted() +T714C 001:384.312 - 0.226ms returns FALSE +T714C 001:384.332 JLINK_HasError() +T714C 001:386.084 JLINK_IsHalted() +T714C 001:388.349 - 2.264ms returns TRUE +T714C 001:388.385 JLINK_ReadReg(R15 (PC)) +T714C 001:388.423 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:388.713 - 0.327ms returns 0x30500000 +T714C 001:388.765 JLINK_ClrBPEx(BPHandle = 0x0000001F) +T714C 001:388.795 - 0.029ms returns 0x00 +T714C 001:388.817 JLINK_ReadReg(R0) +T714C 001:388.834 - 0.017ms returns 0x00000000 +T714C 001:389.303 JLINK_HasError() +T714C 001:389.336 JLINK_WriteReg(R0, 0x00000001) +T714C 001:389.357 - 0.020ms returns 0 +T714C 001:389.374 JLINK_WriteReg(R1, 0x00001000) +T714C 001:389.390 - 0.016ms returns 0 +T714C 001:389.406 JLINK_WriteReg(R2, 0x000000FF) +T714C 001:389.423 - 0.016ms returns 0 +T714C 001:389.439 JLINK_WriteReg(R3, 0x00000000) +T714C 001:389.456 - 0.017ms returns 0 +T714C 001:389.472 JLINK_WriteReg(R4, 0x00000000) +T714C 001:389.488 - 0.015ms returns 0 +T714C 001:389.504 JLINK_WriteReg(R5, 0x00000000) +T714C 001:389.520 - 0.016ms returns 0 +T714C 001:389.536 JLINK_WriteReg(R6, 0x00000000) +T714C 001:389.552 - 0.015ms returns 0 +T714C 001:389.568 JLINK_WriteReg(R7, 0x00000000) +T714C 001:389.584 - 0.016ms returns 0 +T714C 001:389.601 JLINK_WriteReg(R8, 0x00000000) +T714C 001:389.617 - 0.016ms returns 0 +T714C 001:389.633 JLINK_WriteReg(R9, 0x30500458) +T714C 001:389.649 - 0.016ms returns 0 +T714C 001:389.665 JLINK_WriteReg(R10, 0x00000000) +T714C 001:389.681 - 0.016ms returns 0 +T714C 001:389.697 JLINK_WriteReg(R11, 0x00000000) +T714C 001:389.713 - 0.015ms returns 0 +T714C 001:389.729 JLINK_WriteReg(R12, 0x00000000) +T714C 001:389.745 - 0.016ms returns 0 +T714C 001:389.762 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:389.779 - 0.017ms returns 0 +T714C 001:389.795 JLINK_WriteReg(R14, 0x30500001) +T714C 001:389.811 - 0.016ms returns 0 +T714C 001:389.827 JLINK_WriteReg(R15 (PC), 0x30500254) +T714C 001:389.843 - 0.015ms returns 0 +T714C 001:389.859 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:389.875 - 0.015ms returns 0 +T714C 001:389.891 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:389.907 - 0.015ms returns 0 +T714C 001:389.923 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:389.939 - 0.016ms returns 0 +T714C 001:389.956 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:389.972 - 0.016ms returns 0 +T714C 001:389.990 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:390.006 - 0.016ms returns 0x00000020 +T714C 001:390.023 JLINK_Go() +T714C 001:390.041 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:390.381 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:392.390 - 2.367ms +T714C 001:392.461 JLINK_IsHalted() +T714C 001:394.711 - 2.248ms returns TRUE +T714C 001:394.811 JLINK_ReadReg(R15 (PC)) +T714C 001:394.858 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:395.164 - 0.351ms returns 0x30500000 +T714C 001:395.236 JLINK_ClrBPEx(BPHandle = 0x00000020) +T714C 001:395.257 - 0.020ms returns 0x00 +T714C 001:395.277 JLINK_ReadReg(R0) +T714C 001:395.296 - 0.018ms returns 0x00000000 +T714C 001:454.581 JLINK_WriteMem(0x30500000, 0x460 Bytes, ...) +T714C 001:454.624 Data: 00 BE 0A E0 0D 78 2D 06 68 40 08 24 40 00 00 D3 ... +T714C 001:454.662 CPU_WriteMem(1120 bytes @ 0x30500000) +T714C 001:458.172 - 3.591ms returns 0x460 +T714C 001:458.274 JLINK_HasError() +T714C 001:458.294 JLINK_WriteReg(R0, 0x28000000) +T714C 001:458.313 - 0.019ms returns 0 +T714C 001:458.330 JLINK_WriteReg(R1, 0x01F78A40) +T714C 001:458.346 - 0.016ms returns 0 +T714C 001:458.362 JLINK_WriteReg(R2, 0x00000002) +T714C 001:458.378 - 0.015ms returns 0 +T714C 001:458.394 JLINK_WriteReg(R3, 0x00000000) +T714C 001:458.410 - 0.016ms returns 0 +T714C 001:458.432 JLINK_WriteReg(R4, 0x00000000) +T714C 001:458.450 - 0.018ms returns 0 +T714C 001:458.466 JLINK_WriteReg(R5, 0x00000000) +T714C 001:458.482 - 0.015ms returns 0 +T714C 001:458.498 JLINK_WriteReg(R6, 0x00000000) +T714C 001:458.514 - 0.015ms returns 0 +T714C 001:458.529 JLINK_WriteReg(R7, 0x00000000) +T714C 001:458.545 - 0.015ms returns 0 +T714C 001:458.560 JLINK_WriteReg(R8, 0x00000000) +T714C 001:458.576 - 0.015ms returns 0 +T714C 001:458.592 JLINK_WriteReg(R9, 0x30500458) +T714C 001:458.607 - 0.015ms returns 0 +T714C 001:458.622 JLINK_WriteReg(R10, 0x00000000) +T714C 001:458.638 - 0.015ms returns 0 +T714C 001:458.654 JLINK_WriteReg(R11, 0x00000000) +T714C 001:458.670 - 0.015ms returns 0 +T714C 001:458.686 JLINK_WriteReg(R12, 0x00000000) +T714C 001:458.701 - 0.015ms returns 0 +T714C 001:458.717 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:458.734 - 0.017ms returns 0 +T714C 001:458.750 JLINK_WriteReg(R14, 0x30500001) +T714C 001:458.766 - 0.015ms returns 0 +T714C 001:458.782 JLINK_WriteReg(R15 (PC), 0x30500038) +T714C 001:458.797 - 0.015ms returns 0 +T714C 001:458.813 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:458.828 - 0.015ms returns 0 +T714C 001:458.844 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:458.860 - 0.016ms returns 0 +T714C 001:458.876 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:458.892 - 0.016ms returns 0 +T714C 001:458.909 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:458.924 - 0.015ms returns 0 +T714C 001:458.941 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:458.958 - 0.017ms returns 0x00000021 +T714C 001:458.974 JLINK_Go() +T714C 001:458.992 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:459.311 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:461.471 - 2.496ms +T714C 001:461.520 JLINK_IsHalted() +T714C 001:461.760 - 0.239ms returns FALSE +T714C 001:461.808 JLINK_HasError() +T714C 001:465.210 JLINK_IsHalted() +T714C 001:467.552 - 2.341ms returns TRUE +T714C 001:467.612 JLINK_ReadReg(R15 (PC)) +T714C 001:467.634 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:467.912 - 0.299ms returns 0x30500000 +T714C 001:467.960 JLINK_ClrBPEx(BPHandle = 0x00000021) +T714C 001:467.979 - 0.018ms returns 0x00 +T714C 001:467.996 JLINK_ReadReg(R0) +T714C 001:468.014 - 0.017ms returns 0x00000000 +T714C 001:468.505 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:468.539 Data: 46 43 46 42 00 04 01 56 00 00 00 00 01 03 03 00 ... +T714C 001:468.587 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:469.701 - 1.196ms returns 0x100 +T714C 001:469.751 JLINK_HasError() +T714C 001:469.768 JLINK_WriteReg(R0, 0x28000400) +T714C 001:469.788 - 0.019ms returns 0 +T714C 001:469.804 JLINK_WriteReg(R1, 0x00000100) +T714C 001:469.820 - 0.015ms returns 0 +T714C 001:469.836 JLINK_WriteReg(R2, 0x30500674) +T714C 001:469.852 - 0.015ms returns 0 +T714C 001:469.868 JLINK_WriteReg(R3, 0x00000000) +T714C 001:469.883 - 0.015ms returns 0 +T714C 001:469.899 JLINK_WriteReg(R4, 0x00000000) +T714C 001:469.915 - 0.015ms returns 0 +T714C 001:469.931 JLINK_WriteReg(R5, 0x00000000) +T714C 001:469.947 - 0.015ms returns 0 +T714C 001:469.963 JLINK_WriteReg(R6, 0x00000000) +T714C 001:469.978 - 0.015ms returns 0 +T714C 001:469.994 JLINK_WriteReg(R7, 0x00000000) +T714C 001:470.010 - 0.016ms returns 0 +T714C 001:470.026 JLINK_WriteReg(R8, 0x00000000) +T714C 001:470.041 - 0.015ms returns 0 +T714C 001:470.057 JLINK_WriteReg(R9, 0x30500458) +T714C 001:470.073 - 0.015ms returns 0 +T714C 001:470.089 JLINK_WriteReg(R10, 0x00000000) +T714C 001:470.104 - 0.015ms returns 0 +T714C 001:470.120 JLINK_WriteReg(R11, 0x00000000) +T714C 001:470.135 - 0.015ms returns 0 +T714C 001:470.151 JLINK_WriteReg(R12, 0x00000000) +T714C 001:470.166 - 0.015ms returns 0 +T714C 001:470.182 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:470.199 - 0.016ms returns 0 +T714C 001:470.215 JLINK_WriteReg(R14, 0x30500001) +T714C 001:470.231 - 0.016ms returns 0 +T714C 001:470.247 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:470.263 - 0.015ms returns 0 +T714C 001:470.279 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:470.294 - 0.015ms returns 0 +T714C 001:470.310 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:470.375 - 0.064ms returns 0 +T714C 001:470.394 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:470.409 - 0.015ms returns 0 +T714C 001:470.425 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:470.441 - 0.016ms returns 0 +T714C 001:470.459 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:470.496 - 0.038ms returns 0x00000022 +T714C 001:470.513 JLINK_Go() +T714C 001:470.531 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:470.839 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:472.888 - 2.375ms +T714C 001:473.523 JLINK_IsHalted() +T714C 001:475.700 - 2.177ms returns TRUE +T714C 001:475.722 JLINK_ReadReg(R15 (PC)) +T714C 001:475.741 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:476.006 - 0.283ms returns 0x30500000 +T714C 001:476.055 JLINK_ClrBPEx(BPHandle = 0x00000022) +T714C 001:476.073 - 0.018ms returns 0x00 +T714C 001:476.091 JLINK_ReadReg(R0) +T714C 001:476.108 - 0.017ms returns 0x00000000 +T714C 001:476.689 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:476.721 Data: D8 04 18 08 00 00 00 00 00 00 00 00 00 00 00 00 ... +T714C 001:476.750 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:477.868 - 1.179ms returns 0x100 +T714C 001:477.915 JLINK_HasError() +T714C 001:477.933 JLINK_WriteReg(R0, 0x28000500) +T714C 001:477.952 - 0.018ms returns 0 +T714C 001:477.968 JLINK_WriteReg(R1, 0x00000100) +T714C 001:477.984 - 0.016ms returns 0 +T714C 001:478.000 JLINK_WriteReg(R2, 0x30500674) +T714C 001:478.017 - 0.016ms returns 0 +T714C 001:478.033 JLINK_WriteReg(R3, 0x00000000) +T714C 001:478.049 - 0.016ms returns 0 +T714C 001:478.066 JLINK_WriteReg(R4, 0x00000000) +T714C 001:478.081 - 0.015ms returns 0 +T714C 001:478.096 JLINK_WriteReg(R5, 0x00000000) +T714C 001:478.112 - 0.015ms returns 0 +T714C 001:478.128 JLINK_WriteReg(R6, 0x00000000) +T714C 001:478.143 - 0.015ms returns 0 +T714C 001:478.159 JLINK_WriteReg(R7, 0x00000000) +T714C 001:478.174 - 0.015ms returns 0 +T714C 001:478.190 JLINK_WriteReg(R8, 0x00000000) +T714C 001:478.207 - 0.016ms returns 0 +T714C 001:478.222 JLINK_WriteReg(R9, 0x30500458) +T714C 001:478.238 - 0.015ms returns 0 +T714C 001:478.254 JLINK_WriteReg(R10, 0x00000000) +T714C 001:478.269 - 0.015ms returns 0 +T714C 001:478.285 JLINK_WriteReg(R11, 0x00000000) +T714C 001:478.301 - 0.015ms returns 0 +T714C 001:478.316 JLINK_WriteReg(R12, 0x00000000) +T714C 001:478.332 - 0.015ms returns 0 +T714C 001:478.348 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:478.364 - 0.016ms returns 0 +T714C 001:478.380 JLINK_WriteReg(R14, 0x30500001) +T714C 001:478.395 - 0.015ms returns 0 +T714C 001:478.411 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:478.427 - 0.016ms returns 0 +T714C 001:478.443 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:478.458 - 0.015ms returns 0 +T714C 001:478.474 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:478.490 - 0.015ms returns 0 +T714C 001:478.506 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:478.522 - 0.016ms returns 0 +T714C 001:478.537 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:478.553 - 0.015ms returns 0 +T714C 001:478.569 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:478.586 - 0.016ms returns 0x00000023 +T714C 001:478.602 JLINK_Go() +T714C 001:478.619 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:478.930 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:480.969 - 2.365ms +T714C 001:481.017 JLINK_IsHalted() +T714C 001:481.313 - 0.295ms returns FALSE +T714C 001:481.343 JLINK_HasError() +T714C 001:482.972 JLINK_IsHalted() +T714C 001:485.381 - 2.408ms returns TRUE +T714C 001:485.432 JLINK_ReadReg(R15 (PC)) +T714C 001:485.453 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:485.707 - 0.275ms returns 0x30500000 +T714C 001:485.729 JLINK_ClrBPEx(BPHandle = 0x00000023) +T714C 001:485.746 - 0.017ms returns 0x00 +T714C 001:485.763 JLINK_ReadReg(R0) +T714C 001:485.780 - 0.016ms returns 0x00000000 +T714C 001:486.394 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:486.429 Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... +T714C 001:486.460 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:487.388 - 0.994ms returns 0x100 +T714C 001:487.417 JLINK_HasError() +T714C 001:487.442 JLINK_WriteReg(R0, 0x28000600) +T714C 001:487.491 - 0.049ms returns 0 +T714C 001:487.508 JLINK_WriteReg(R1, 0x00000100) +T714C 001:487.524 - 0.016ms returns 0 +T714C 001:487.540 JLINK_WriteReg(R2, 0x30500674) +T714C 001:487.556 - 0.015ms returns 0 +T714C 001:487.572 JLINK_WriteReg(R3, 0x00000000) +T714C 001:487.588 - 0.015ms returns 0 +T714C 001:487.604 JLINK_WriteReg(R4, 0x00000000) +T714C 001:487.620 - 0.015ms returns 0 +T714C 001:487.637 JLINK_WriteReg(R5, 0x00000000) +T714C 001:487.652 - 0.015ms returns 0 +T714C 001:487.668 JLINK_WriteReg(R6, 0x00000000) +T714C 001:487.683 - 0.015ms returns 0 +T714C 001:487.699 JLINK_WriteReg(R7, 0x00000000) +T714C 001:487.715 - 0.015ms returns 0 +T714C 001:487.732 JLINK_WriteReg(R8, 0x00000000) +T714C 001:487.748 - 0.016ms returns 0 +T714C 001:487.764 JLINK_WriteReg(R9, 0x30500458) +T714C 001:487.780 - 0.015ms returns 0 +T714C 001:487.796 JLINK_WriteReg(R10, 0x00000000) +T714C 001:487.812 - 0.015ms returns 0 +T714C 001:487.828 JLINK_WriteReg(R11, 0x00000000) +T714C 001:487.844 - 0.016ms returns 0 +T714C 001:487.860 JLINK_WriteReg(R12, 0x00000000) +T714C 001:487.876 - 0.016ms returns 0 +T714C 001:487.892 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:487.909 - 0.017ms returns 0 +T714C 001:487.926 JLINK_WriteReg(R14, 0x30500001) +T714C 001:487.942 - 0.015ms returns 0 +T714C 001:487.958 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:487.974 - 0.016ms returns 0 +T714C 001:487.991 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:488.007 - 0.016ms returns 0 +T714C 001:488.023 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:488.039 - 0.015ms returns 0 +T714C 001:488.055 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:488.071 - 0.016ms returns 0 +T714C 001:488.087 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:488.103 - 0.015ms returns 0 +T714C 001:488.121 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:488.137 - 0.017ms returns 0x00000024 +T714C 001:488.154 JLINK_Go() +T714C 001:488.172 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:488.425 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:490.198 - 2.044ms +T714C 001:490.227 JLINK_IsHalted() +T714C 001:490.479 - 0.251ms returns FALSE +T714C 001:490.498 JLINK_HasError() +T714C 001:492.240 JLINK_IsHalted() +T714C 001:494.365 - 2.124ms returns TRUE +T714C 001:494.388 JLINK_ReadReg(R15 (PC)) +T714C 001:494.406 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:494.660 - 0.272ms returns 0x30500000 +T714C 001:494.680 JLINK_ClrBPEx(BPHandle = 0x00000024) +T714C 001:494.697 - 0.017ms returns 0x00 +T714C 001:494.714 JLINK_ReadReg(R0) +T714C 001:494.730 - 0.016ms returns 0x00000000 +T714C 001:495.187 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:495.219 Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... +T714C 001:495.248 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:496.263 - 1.076ms returns 0x100 +T714C 001:496.299 JLINK_HasError() +T714C 001:496.318 JLINK_WriteReg(R0, 0x28000700) +T714C 001:496.337 - 0.019ms returns 0 +T714C 001:496.354 JLINK_WriteReg(R1, 0x00000100) +T714C 001:496.370 - 0.016ms returns 0 +T714C 001:496.387 JLINK_WriteReg(R2, 0x30500674) +T714C 001:496.404 - 0.016ms returns 0 +T714C 001:496.420 JLINK_WriteReg(R3, 0x00000000) +T714C 001:496.436 - 0.016ms returns 0 +T714C 001:496.453 JLINK_WriteReg(R4, 0x00000000) +T714C 001:496.469 - 0.016ms returns 0 +T714C 001:496.485 JLINK_WriteReg(R5, 0x00000000) +T714C 001:496.501 - 0.016ms returns 0 +T714C 001:496.517 JLINK_WriteReg(R6, 0x00000000) +T714C 001:496.532 - 0.015ms returns 0 +T714C 001:496.548 JLINK_WriteReg(R7, 0x00000000) +T714C 001:496.564 - 0.015ms returns 0 +T714C 001:496.580 JLINK_WriteReg(R8, 0x00000000) +T714C 001:496.596 - 0.016ms returns 0 +T714C 001:496.612 JLINK_WriteReg(R9, 0x30500458) +T714C 001:496.629 - 0.016ms returns 0 +T714C 001:496.645 JLINK_WriteReg(R10, 0x00000000) +T714C 001:496.661 - 0.016ms returns 0 +T714C 001:496.677 JLINK_WriteReg(R11, 0x00000000) +T714C 001:496.693 - 0.015ms returns 0 +T714C 001:496.709 JLINK_WriteReg(R12, 0x00000000) +T714C 001:496.725 - 0.016ms returns 0 +T714C 001:496.741 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:496.766 - 0.024ms returns 0 +T714C 001:496.783 JLINK_WriteReg(R14, 0x30500001) +T714C 001:496.800 - 0.016ms returns 0 +T714C 001:496.817 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:496.833 - 0.016ms returns 0 +T714C 001:496.848 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:496.864 - 0.015ms returns 0 +T714C 001:496.881 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:496.897 - 0.016ms returns 0 +T714C 001:496.914 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:496.930 - 0.016ms returns 0 +T714C 001:496.946 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:496.962 - 0.015ms returns 0 +T714C 001:496.978 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:496.994 - 0.016ms returns 0x00000025 +T714C 001:497.010 JLINK_Go() +T714C 001:497.028 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:497.258 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:499.215 - 2.204ms +T714C 001:499.263 JLINK_IsHalted() +T714C 001:499.554 - 0.290ms returns FALSE +T714C 001:500.577 JLINK_HasError() +T714C 001:501.919 JLINK_IsHalted() +T714C 001:504.036 - 2.116ms returns TRUE +T714C 001:504.066 JLINK_ReadReg(R15 (PC)) +T714C 001:504.085 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:504.313 - 0.247ms returns 0x30500000 +T714C 001:504.334 JLINK_ClrBPEx(BPHandle = 0x00000025) +T714C 001:504.351 - 0.017ms returns 0x00 +T714C 001:504.368 JLINK_ReadReg(R0) +T714C 001:504.385 - 0.017ms returns 0x00000000 +T714C 001:505.002 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:505.034 Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... +T714C 001:505.065 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:505.999 - 0.998ms returns 0x100 +T714C 001:506.023 JLINK_HasError() +T714C 001:506.042 JLINK_WriteReg(R0, 0x28000800) +T714C 001:506.060 - 0.018ms returns 0 +T714C 001:506.076 JLINK_WriteReg(R1, 0x00000100) +T714C 001:506.093 - 0.016ms returns 0 +T714C 001:506.110 JLINK_WriteReg(R2, 0x30500674) +T714C 001:506.125 - 0.015ms returns 0 +T714C 001:506.142 JLINK_WriteReg(R3, 0x00000000) +T714C 001:506.158 - 0.016ms returns 0 +T714C 001:506.174 JLINK_WriteReg(R4, 0x00000000) +T714C 001:506.190 - 0.016ms returns 0 +T714C 001:506.206 JLINK_WriteReg(R5, 0x00000000) +T714C 001:506.222 - 0.015ms returns 0 +T714C 001:506.238 JLINK_WriteReg(R6, 0x00000000) +T714C 001:506.254 - 0.015ms returns 0 +T714C 001:506.270 JLINK_WriteReg(R7, 0x00000000) +T714C 001:506.287 - 0.016ms returns 0 +T714C 001:506.303 JLINK_WriteReg(R8, 0x00000000) +T714C 001:506.319 - 0.016ms returns 0 +T714C 001:506.335 JLINK_WriteReg(R9, 0x30500458) +T714C 001:506.350 - 0.015ms returns 0 +T714C 001:506.367 JLINK_WriteReg(R10, 0x00000000) +T714C 001:506.382 - 0.015ms returns 0 +T714C 001:506.398 JLINK_WriteReg(R11, 0x00000000) +T714C 001:506.414 - 0.015ms returns 0 +T714C 001:506.430 JLINK_WriteReg(R12, 0x00000000) +T714C 001:506.446 - 0.015ms returns 0 +T714C 001:506.462 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:506.479 - 0.016ms returns 0 +T714C 001:506.495 JLINK_WriteReg(R14, 0x30500001) +T714C 001:506.511 - 0.016ms returns 0 +T714C 001:506.528 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:506.545 - 0.016ms returns 0 +T714C 001:506.561 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:506.577 - 0.015ms returns 0 +T714C 001:506.593 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:506.609 - 0.015ms returns 0 +T714C 001:506.625 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:506.640 - 0.015ms returns 0 +T714C 001:506.656 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:506.672 - 0.015ms returns 0 +T714C 001:506.689 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:506.705 - 0.016ms returns 0x00000026 +T714C 001:506.721 JLINK_Go() +T714C 001:506.739 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:506.963 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:508.809 - 2.087ms +T714C 001:508.840 JLINK_IsHalted() +T714C 001:509.073 - 0.233ms returns FALSE +T714C 001:509.093 JLINK_HasError() +T714C 001:510.924 JLINK_IsHalted() +T714C 001:513.377 - 2.452ms returns TRUE +T714C 001:513.514 JLINK_ReadReg(R15 (PC)) +T714C 001:513.558 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:513.837 - 0.322ms returns 0x30500000 +T714C 001:513.905 JLINK_ClrBPEx(BPHandle = 0x00000026) +T714C 001:513.925 - 0.039ms returns 0x00 +T714C 001:513.943 JLINK_ReadReg(R0) +T714C 001:513.961 - 0.018ms returns 0x00000000 +T714C 001:514.622 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:514.689 Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... +T714C 001:514.721 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:515.708 - 1.085ms returns 0x100 +T714C 001:515.760 JLINK_HasError() +T714C 001:515.779 JLINK_WriteReg(R0, 0x28000900) +T714C 001:515.800 - 0.021ms returns 0 +T714C 001:515.817 JLINK_WriteReg(R1, 0x00000100) +T714C 001:515.833 - 0.016ms returns 0 +T714C 001:515.850 JLINK_WriteReg(R2, 0x30500674) +T714C 001:515.866 - 0.016ms returns 0 +T714C 001:515.883 JLINK_WriteReg(R3, 0x00000000) +T714C 001:515.920 - 0.036ms returns 0 +T714C 001:515.936 JLINK_WriteReg(R4, 0x00000000) +T714C 001:515.963 - 0.027ms returns 0 +T714C 001:515.981 JLINK_WriteReg(R5, 0x00000000) +T714C 001:515.997 - 0.016ms returns 0 +T714C 001:516.014 JLINK_WriteReg(R6, 0x00000000) +T714C 001:516.030 - 0.016ms returns 0 +T714C 001:516.046 JLINK_WriteReg(R7, 0x00000000) +T714C 001:516.062 - 0.015ms returns 0 +T714C 001:516.078 JLINK_WriteReg(R8, 0x00000000) +T714C 001:516.094 - 0.016ms returns 0 +T714C 001:516.111 JLINK_WriteReg(R9, 0x30500458) +T714C 001:516.126 - 0.015ms returns 0 +T714C 001:516.159 JLINK_WriteReg(R10, 0x00000000) +T714C 001:516.176 - 0.017ms returns 0 +T714C 001:516.193 JLINK_WriteReg(R11, 0x00000000) +T714C 001:516.209 - 0.016ms returns 0 +T714C 001:516.226 JLINK_WriteReg(R12, 0x00000000) +T714C 001:516.242 - 0.016ms returns 0 +T714C 001:516.258 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:516.275 - 0.017ms returns 0 +T714C 001:516.291 JLINK_WriteReg(R14, 0x30500001) +T714C 001:516.308 - 0.016ms returns 0 +T714C 001:516.325 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:516.341 - 0.017ms returns 0 +T714C 001:516.358 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:516.374 - 0.016ms returns 0 +T714C 001:516.391 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:516.424 - 0.033ms returns 0 +T714C 001:516.441 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:516.458 - 0.016ms returns 0 +T714C 001:516.474 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:516.490 - 0.016ms returns 0 +T714C 001:516.542 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:516.559 - 0.017ms returns 0x00000027 +T714C 001:516.575 JLINK_Go() +T714C 001:516.594 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:516.847 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:518.710 - 2.134ms +T714C 001:518.747 JLINK_IsHalted() +T714C 001:519.030 - 0.282ms returns FALSE +T714C 001:519.078 JLINK_HasError() +T714C 001:521.166 JLINK_IsHalted() +T714C 001:523.296 - 2.128ms returns TRUE +T714C 001:523.321 JLINK_ReadReg(R15 (PC)) +T714C 001:523.343 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:523.567 - 0.245ms returns 0x30500000 +T714C 001:523.596 JLINK_ClrBPEx(BPHandle = 0x00000027) +T714C 001:523.614 - 0.018ms returns 0x00 +T714C 001:523.631 JLINK_ReadReg(R0) +T714C 001:523.649 - 0.017ms returns 0x00000000 +T714C 001:524.198 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:524.269 Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... +T714C 001:524.300 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:525.394 - 1.196ms returns 0x100 +T714C 001:525.428 JLINK_HasError() +T714C 001:525.447 JLINK_WriteReg(R0, 0x28000A00) +T714C 001:525.466 - 0.018ms returns 0 +T714C 001:525.486 JLINK_WriteReg(R1, 0x00000100) +T714C 001:525.504 - 0.017ms returns 0 +T714C 001:525.520 JLINK_WriteReg(R2, 0x30500674) +T714C 001:525.536 - 0.016ms returns 0 +T714C 001:525.554 JLINK_WriteReg(R3, 0x00000000) +T714C 001:525.571 - 0.017ms returns 0 +T714C 001:525.590 JLINK_WriteReg(R4, 0x00000000) +T714C 001:525.607 - 0.016ms returns 0 +T714C 001:525.626 JLINK_WriteReg(R5, 0x00000000) +T714C 001:525.643 - 0.016ms returns 0 +T714C 001:526.276 JLINK_WriteReg(R6, 0x00000000) +T714C 001:526.303 - 0.027ms returns 0 +T714C 001:526.321 JLINK_WriteReg(R7, 0x00000000) +T714C 001:526.338 - 0.016ms returns 0 +T714C 001:526.362 JLINK_WriteReg(R8, 0x00000000) +T714C 001:526.378 - 0.016ms returns 0 +T714C 001:526.394 JLINK_WriteReg(R9, 0x30500458) +T714C 001:526.410 - 0.015ms returns 0 +T714C 001:526.426 JLINK_WriteReg(R10, 0x00000000) +T714C 001:526.442 - 0.015ms returns 0 +T714C 001:526.459 JLINK_WriteReg(R11, 0x00000000) +T714C 001:526.476 - 0.016ms returns 0 +T714C 001:526.492 JLINK_WriteReg(R12, 0x00000000) +T714C 001:526.509 - 0.016ms returns 0 +T714C 001:526.525 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:526.542 - 0.017ms returns 0 +T714C 001:526.558 JLINK_WriteReg(R14, 0x30500001) +T714C 001:526.574 - 0.015ms returns 0 +T714C 001:526.590 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:526.607 - 0.016ms returns 0 +T714C 001:526.624 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:526.640 - 0.016ms returns 0 +T714C 001:526.656 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:526.673 - 0.016ms returns 0 +T714C 001:526.690 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:526.712 - 0.021ms returns 0 +T714C 001:526.737 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:526.812 - 0.075ms returns 0 +T714C 001:526.847 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:526.877 - 0.031ms returns 0x00000028 +T714C 001:526.900 JLINK_Go() +T714C 001:526.925 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:527.269 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:529.218 - 2.316ms +T714C 001:529.275 JLINK_IsHalted() +T714C 001:529.505 - 0.229ms returns FALSE +T714C 001:529.527 JLINK_HasError() +T714C 001:531.191 JLINK_IsHalted() +T714C 001:533.361 - 2.170ms returns TRUE +T714C 001:533.420 JLINK_ReadReg(R15 (PC)) +T714C 001:533.441 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:533.704 - 0.283ms returns 0x30500000 +T714C 001:533.727 JLINK_ClrBPEx(BPHandle = 0x00000028) +T714C 001:533.744 - 0.017ms returns 0x00 +T714C 001:533.760 JLINK_ReadReg(R0) +T714C 001:533.778 - 0.017ms returns 0x00000000 +T714C 001:534.431 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:534.470 Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... +T714C 001:534.503 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:535.537 - 1.106ms returns 0x100 +T714C 001:535.562 JLINK_HasError() +T714C 001:535.580 JLINK_WriteReg(R0, 0x28000B00) +T714C 001:535.599 - 0.019ms returns 0 +T714C 001:535.616 JLINK_WriteReg(R1, 0x00000100) +T714C 001:535.632 - 0.016ms returns 0 +T714C 001:535.648 JLINK_WriteReg(R2, 0x30500674) +T714C 001:535.665 - 0.016ms returns 0 +T714C 001:535.681 JLINK_WriteReg(R3, 0x00000000) +T714C 001:535.697 - 0.016ms returns 0 +T714C 001:535.714 JLINK_WriteReg(R4, 0x00000000) +T714C 001:535.731 - 0.017ms returns 0 +T714C 001:535.748 JLINK_WriteReg(R5, 0x00000000) +T714C 001:535.763 - 0.015ms returns 0 +T714C 001:535.779 JLINK_WriteReg(R6, 0x00000000) +T714C 001:535.795 - 0.015ms returns 0 +T714C 001:535.811 JLINK_WriteReg(R7, 0x00000000) +T714C 001:535.827 - 0.015ms returns 0 +T714C 001:535.843 JLINK_WriteReg(R8, 0x00000000) +T714C 001:535.859 - 0.016ms returns 0 +T714C 001:535.875 JLINK_WriteReg(R9, 0x30500458) +T714C 001:535.890 - 0.015ms returns 0 +T714C 001:535.907 JLINK_WriteReg(R10, 0x00000000) +T714C 001:535.923 - 0.016ms returns 0 +T714C 001:535.939 JLINK_WriteReg(R11, 0x00000000) +T714C 001:535.955 - 0.016ms returns 0 +T714C 001:535.971 JLINK_WriteReg(R12, 0x00000000) +T714C 001:535.987 - 0.016ms returns 0 +T714C 001:536.003 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:536.020 - 0.016ms returns 0 +T714C 001:536.036 JLINK_WriteReg(R14, 0x30500001) +T714C 001:536.052 - 0.015ms returns 0 +T714C 001:536.068 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:536.083 - 0.015ms returns 0 +T714C 001:536.100 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:536.115 - 0.016ms returns 0 +T714C 001:536.132 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:536.148 - 0.016ms returns 0 +T714C 001:536.165 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:536.180 - 0.015ms returns 0 +T714C 001:536.197 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:536.213 - 0.015ms returns 0 +T714C 001:536.230 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:536.246 - 0.016ms returns 0x00000029 +T714C 001:536.270 JLINK_Go() +T714C 001:536.287 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:536.570 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:538.446 - 2.176ms +T714C 001:538.468 JLINK_IsHalted() +T714C 001:538.703 - 0.235ms returns FALSE +T714C 001:538.723 JLINK_HasError() +T714C 001:540.247 JLINK_IsHalted() +T714C 001:542.393 - 2.144ms returns TRUE +T714C 001:542.478 JLINK_ReadReg(R15 (PC)) +T714C 001:542.504 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:542.786 - 0.307ms returns 0x30500000 +T714C 001:542.826 JLINK_ClrBPEx(BPHandle = 0x00000029) +T714C 001:542.844 - 0.017ms returns 0x00 +T714C 001:542.861 JLINK_ReadReg(R0) +T714C 001:542.878 - 0.017ms returns 0x00000000 +T714C 001:543.393 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:543.425 Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... +T714C 001:543.456 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:544.529 - 1.135ms returns 0x100 +T714C 001:544.565 JLINK_HasError() +T714C 001:544.583 JLINK_WriteReg(R0, 0x28000C00) +T714C 001:544.602 - 0.018ms returns 0 +T714C 001:544.619 JLINK_WriteReg(R1, 0x00000100) +T714C 001:544.635 - 0.016ms returns 0 +T714C 001:544.652 JLINK_WriteReg(R2, 0x30500674) +T714C 001:544.668 - 0.016ms returns 0 +T714C 001:544.685 JLINK_WriteReg(R3, 0x00000000) +T714C 001:544.701 - 0.016ms returns 0 +T714C 001:544.718 JLINK_WriteReg(R4, 0x00000000) +T714C 001:544.734 - 0.016ms returns 0 +T714C 001:544.751 JLINK_WriteReg(R5, 0x00000000) +T714C 001:544.767 - 0.016ms returns 0 +T714C 001:544.783 JLINK_WriteReg(R6, 0x00000000) +T714C 001:544.799 - 0.016ms returns 0 +T714C 001:544.815 JLINK_WriteReg(R7, 0x00000000) +T714C 001:544.831 - 0.016ms returns 0 +T714C 001:544.848 JLINK_WriteReg(R8, 0x00000000) +T714C 001:544.873 - 0.025ms returns 0 +T714C 001:544.889 JLINK_WriteReg(R9, 0x30500458) +T714C 001:544.905 - 0.015ms returns 0 +T714C 001:544.922 JLINK_WriteReg(R10, 0x00000000) +T714C 001:544.938 - 0.016ms returns 0 +T714C 001:544.954 JLINK_WriteReg(R11, 0x00000000) +T714C 001:544.970 - 0.015ms returns 0 +T714C 001:544.986 JLINK_WriteReg(R12, 0x00000000) +T714C 001:545.002 - 0.015ms returns 0 +T714C 001:545.018 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:545.035 - 0.016ms returns 0 +T714C 001:545.051 JLINK_WriteReg(R14, 0x30500001) +T714C 001:545.066 - 0.015ms returns 0 +T714C 001:545.083 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:545.099 - 0.016ms returns 0 +T714C 001:545.115 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:545.130 - 0.015ms returns 0 +T714C 001:545.146 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:545.162 - 0.015ms returns 0 +T714C 001:545.178 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:545.194 - 0.015ms returns 0 +T714C 001:545.210 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:545.226 - 0.016ms returns 0 +T714C 001:545.243 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:545.259 - 0.016ms returns 0x0000002A +T714C 001:545.275 JLINK_Go() +T714C 001:545.294 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:545.586 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:547.496 - 2.220ms +T714C 001:547.518 JLINK_IsHalted() +T714C 001:547.742 - 0.224ms returns FALSE +T714C 001:547.763 JLINK_HasError() +T714C 001:549.541 JLINK_IsHalted() +T714C 001:551.792 - 2.250ms returns TRUE +T714C 001:551.851 JLINK_ReadReg(R15 (PC)) +T714C 001:551.872 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:552.131 - 0.279ms returns 0x30500000 +T714C 001:552.796 JLINK_ClrBPEx(BPHandle = 0x0000002A) +T714C 001:552.820 - 0.023ms returns 0x00 +T714C 001:552.837 JLINK_ReadReg(R0) +T714C 001:552.855 - 0.017ms returns 0x00000000 +T714C 001:553.401 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:553.432 Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... +T714C 001:553.462 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:554.534 - 1.132ms returns 0x100 +T714C 001:554.561 JLINK_HasError() +T714C 001:554.579 JLINK_WriteReg(R0, 0x28000D00) +T714C 001:554.597 - 0.018ms returns 0 +T714C 001:554.613 JLINK_WriteReg(R1, 0x00000100) +T714C 001:554.629 - 0.016ms returns 0 +T714C 001:554.647 JLINK_WriteReg(R2, 0x30500674) +T714C 001:554.669 - 0.022ms returns 0 +T714C 001:554.685 JLINK_WriteReg(R3, 0x00000000) +T714C 001:554.701 - 0.015ms returns 0 +T714C 001:554.718 JLINK_WriteReg(R4, 0x00000000) +T714C 001:554.734 - 0.016ms returns 0 +T714C 001:554.751 JLINK_WriteReg(R5, 0x00000000) +T714C 001:554.768 - 0.017ms returns 0 +T714C 001:554.785 JLINK_WriteReg(R6, 0x00000000) +T714C 001:554.801 - 0.015ms returns 0 +T714C 001:554.817 JLINK_WriteReg(R7, 0x00000000) +T714C 001:554.832 - 0.015ms returns 0 +T714C 001:554.848 JLINK_WriteReg(R8, 0x00000000) +T714C 001:554.864 - 0.015ms returns 0 +T714C 001:554.881 JLINK_WriteReg(R9, 0x30500458) +T714C 001:554.896 - 0.015ms returns 0 +T714C 001:554.912 JLINK_WriteReg(R10, 0x00000000) +T714C 001:554.928 - 0.016ms returns 0 +T714C 001:554.944 JLINK_WriteReg(R11, 0x00000000) +T714C 001:554.960 - 0.015ms returns 0 +T714C 001:554.976 JLINK_WriteReg(R12, 0x00000000) +T714C 001:554.992 - 0.015ms returns 0 +T714C 001:555.008 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:555.025 - 0.016ms returns 0 +T714C 001:555.041 JLINK_WriteReg(R14, 0x30500001) +T714C 001:555.056 - 0.015ms returns 0 +T714C 001:555.072 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:555.088 - 0.016ms returns 0 +T714C 001:555.104 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:555.120 - 0.016ms returns 0 +T714C 001:555.137 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:555.152 - 0.015ms returns 0 +T714C 001:555.169 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:555.184 - 0.015ms returns 0 +T714C 001:555.201 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:555.216 - 0.015ms returns 0 +T714C 001:555.233 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:555.249 - 0.017ms returns 0x0000002B +T714C 001:555.265 JLINK_Go() +T714C 001:555.283 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:555.570 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:557.497 - 2.232ms +T714C 001:557.522 JLINK_IsHalted() +T714C 001:557.962 - 0.439ms returns FALSE +T714C 001:558.004 JLINK_HasError() +T714C 001:559.553 JLINK_IsHalted() +T714C 001:561.800 - 2.246ms returns TRUE +T714C 001:561.826 JLINK_ReadReg(R15 (PC)) +T714C 001:561.845 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:562.119 - 0.293ms returns 0x30500000 +T714C 001:562.143 JLINK_ClrBPEx(BPHandle = 0x0000002B) +T714C 001:562.159 - 0.016ms returns 0x00 +T714C 001:562.177 JLINK_ReadReg(R0) +T714C 001:562.193 - 0.016ms returns 0x00000000 +T714C 001:562.722 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:562.758 Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... +T714C 001:562.790 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:563.830 - 1.108ms returns 0x100 +T714C 001:563.859 JLINK_HasError() +T714C 001:563.876 JLINK_WriteReg(R0, 0x28000E00) +T714C 001:563.894 - 0.017ms returns 0 +T714C 001:563.910 JLINK_WriteReg(R1, 0x00000100) +T714C 001:563.926 - 0.016ms returns 0 +T714C 001:563.943 JLINK_WriteReg(R2, 0x30500674) +T714C 001:563.958 - 0.015ms returns 0 +T714C 001:563.975 JLINK_WriteReg(R3, 0x00000000) +T714C 001:563.991 - 0.016ms returns 0 +T714C 001:564.007 JLINK_WriteReg(R4, 0x00000000) +T714C 001:564.023 - 0.015ms returns 0 +T714C 001:564.039 JLINK_WriteReg(R5, 0x00000000) +T714C 001:564.056 - 0.016ms returns 0 +T714C 001:564.072 JLINK_WriteReg(R6, 0x00000000) +T714C 001:564.088 - 0.015ms returns 0 +T714C 001:564.105 JLINK_WriteReg(R7, 0x00000000) +T714C 001:564.121 - 0.016ms returns 0 +T714C 001:564.137 JLINK_WriteReg(R8, 0x00000000) +T714C 001:564.153 - 0.015ms returns 0 +T714C 001:564.169 JLINK_WriteReg(R9, 0x30500458) +T714C 001:564.184 - 0.015ms returns 0 +T714C 001:564.201 JLINK_WriteReg(R10, 0x00000000) +T714C 001:564.217 - 0.016ms returns 0 +T714C 001:564.233 JLINK_WriteReg(R11, 0x00000000) +T714C 001:564.249 - 0.015ms returns 0 +T714C 001:564.265 JLINK_WriteReg(R12, 0x00000000) +T714C 001:564.281 - 0.016ms returns 0 +T714C 001:564.297 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:564.314 - 0.017ms returns 0 +T714C 001:564.330 JLINK_WriteReg(R14, 0x30500001) +T714C 001:564.346 - 0.016ms returns 0 +T714C 001:564.362 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:564.382 - 0.020ms returns 0 +T714C 001:564.400 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:564.416 - 0.015ms returns 0 +T714C 001:564.432 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:564.448 - 0.015ms returns 0 +T714C 001:564.464 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:564.480 - 0.016ms returns 0 +T714C 001:564.496 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:564.512 - 0.015ms returns 0 +T714C 001:564.529 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:564.545 - 0.016ms returns 0x0000002C +T714C 001:564.562 JLINK_Go() +T714C 001:564.580 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:564.883 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:566.951 - 2.388ms +T714C 001:567.006 JLINK_IsHalted() +T714C 001:567.263 - 0.256ms returns FALSE +T714C 001:567.309 JLINK_HasError() +T714C 001:568.679 JLINK_IsHalted() +T714C 001:570.997 - 2.317ms returns TRUE +T714C 001:571.044 JLINK_ReadReg(R15 (PC)) +T714C 001:571.063 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:571.385 - 0.340ms returns 0x30500000 +T714C 001:571.432 JLINK_ClrBPEx(BPHandle = 0x0000002C) +T714C 001:571.450 - 0.018ms returns 0x00 +T714C 001:571.467 JLINK_ReadReg(R0) +T714C 001:571.484 - 0.016ms returns 0x00000000 +T714C 001:572.035 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:572.066 Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... +T714C 001:572.096 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:573.130 - 1.095ms returns 0x100 +T714C 001:573.184 JLINK_HasError() +T714C 001:573.204 JLINK_WriteReg(R0, 0x28000F00) +T714C 001:573.224 - 0.019ms returns 0 +T714C 001:573.252 JLINK_WriteReg(R1, 0x00000100) +T714C 001:573.269 - 0.017ms returns 0 +T714C 001:573.285 JLINK_WriteReg(R2, 0x30500674) +T714C 001:573.301 - 0.016ms returns 0 +T714C 001:573.318 JLINK_WriteReg(R3, 0x00000000) +T714C 001:573.334 - 0.015ms returns 0 +T714C 001:573.351 JLINK_WriteReg(R4, 0x00000000) +T714C 001:573.365 - 0.014ms returns 0 +T714C 001:573.380 JLINK_WriteReg(R5, 0x00000000) +T714C 001:573.404 - 0.024ms returns 0 +T714C 001:573.421 JLINK_WriteReg(R6, 0x00000000) +T714C 001:573.437 - 0.016ms returns 0 +T714C 001:573.454 JLINK_WriteReg(R7, 0x00000000) +T714C 001:573.470 - 0.016ms returns 0 +T714C 001:573.487 JLINK_WriteReg(R8, 0x00000000) +T714C 001:573.572 - 0.085ms returns 0 +T714C 001:573.589 JLINK_WriteReg(R9, 0x30500458) +T714C 001:573.606 - 0.016ms returns 0 +T714C 001:573.622 JLINK_WriteReg(R10, 0x00000000) +T714C 001:573.639 - 0.017ms returns 0 +T714C 001:573.655 JLINK_WriteReg(R11, 0x00000000) +T714C 001:573.674 - 0.018ms returns 0 +T714C 001:573.691 JLINK_WriteReg(R12, 0x00000000) +T714C 001:573.708 - 0.016ms returns 0 +T714C 001:573.770 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:573.793 - 0.022ms returns 0 +T714C 001:573.829 JLINK_WriteReg(R14, 0x30500001) +T714C 001:573.845 - 0.016ms returns 0 +T714C 001:573.861 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:573.876 - 0.015ms returns 0 +T714C 001:573.891 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:573.906 - 0.014ms returns 0 +T714C 001:573.921 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:573.936 - 0.014ms returns 0 +T714C 001:573.951 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:573.967 - 0.015ms returns 0 +T714C 001:573.984 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:574.045 - 0.060ms returns 0 +T714C 001:574.079 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:574.101 - 0.022ms returns 0x0000002D +T714C 001:574.120 JLINK_Go() +T714C 001:574.143 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:574.531 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:576.527 - 2.405ms +T714C 001:576.574 JLINK_IsHalted() +T714C 001:576.824 - 0.249ms returns FALSE +T714C 001:576.846 JLINK_HasError() +T714C 001:578.596 JLINK_IsHalted() +T714C 001:580.815 - 2.218ms returns TRUE +T714C 001:580.840 JLINK_ReadReg(R15 (PC)) +T714C 001:580.859 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:581.090 - 0.249ms returns 0x30500000 +T714C 001:581.112 JLINK_ClrBPEx(BPHandle = 0x0000002D) +T714C 001:581.128 - 0.016ms returns 0x00 +T714C 001:581.146 JLINK_ReadReg(R0) +T714C 001:581.164 - 0.018ms returns 0x00000000 +T714C 001:582.002 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:582.043 Data: 00 A0 00 87 00 00 00 00 00 00 00 01 90 00 00 00 ... +T714C 001:582.074 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:583.069 - 1.065ms returns 0x100 +T714C 001:583.133 JLINK_HasError() +T714C 001:583.168 JLINK_WriteReg(R0, 0x28001000) +T714C 001:583.190 - 0.022ms returns 0 +T714C 001:583.208 JLINK_WriteReg(R1, 0x000000A0) +T714C 001:583.227 - 0.018ms returns 0 +T714C 001:583.244 JLINK_WriteReg(R2, 0x30500674) +T714C 001:583.262 - 0.017ms returns 0 +T714C 001:583.281 JLINK_WriteReg(R3, 0x00000000) +T714C 001:583.297 - 0.016ms returns 0 +T714C 001:583.313 JLINK_WriteReg(R4, 0x00000000) +T714C 001:583.329 - 0.016ms returns 0 +T714C 001:583.346 JLINK_WriteReg(R5, 0x00000000) +T714C 001:583.362 - 0.015ms returns 0 +T714C 001:583.378 JLINK_WriteReg(R6, 0x00000000) +T714C 001:583.395 - 0.016ms returns 0 +T714C 001:583.411 JLINK_WriteReg(R7, 0x00000000) +T714C 001:583.428 - 0.016ms returns 0 +T714C 001:583.445 JLINK_WriteReg(R8, 0x00000000) +T714C 001:583.461 - 0.016ms returns 0 +T714C 001:583.477 JLINK_WriteReg(R9, 0x30500458) +T714C 001:583.493 - 0.016ms returns 0 +T714C 001:583.510 JLINK_WriteReg(R10, 0x00000000) +T714C 001:583.526 - 0.016ms returns 0 +T714C 001:583.542 JLINK_WriteReg(R11, 0x00000000) +T714C 001:583.559 - 0.016ms returns 0 +T714C 001:583.576 JLINK_WriteReg(R12, 0x00000000) +T714C 001:583.592 - 0.016ms returns 0 +T714C 001:583.609 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:583.627 - 0.017ms returns 0 +T714C 001:583.643 JLINK_WriteReg(R14, 0x30500001) +T714C 001:583.660 - 0.016ms returns 0 +T714C 001:583.677 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:583.693 - 0.016ms returns 0 +T714C 001:583.710 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:583.726 - 0.016ms returns 0 +T714C 001:583.779 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:583.797 - 0.017ms returns 0 +T714C 001:583.814 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:583.830 - 0.016ms returns 0 +T714C 001:583.847 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:583.863 - 0.016ms returns 0 +T714C 001:583.880 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:583.897 - 0.017ms returns 0x0000002E +T714C 001:583.913 JLINK_Go() +T714C 001:583.932 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:584.223 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:586.101 - 2.187ms +T714C 001:586.126 JLINK_IsHalted() +T714C 001:586.377 - 0.250ms returns FALSE +T714C 001:586.398 JLINK_HasError() +T714C 001:587.614 JLINK_IsHalted() +T714C 001:589.952 - 2.337ms returns TRUE +T714C 001:590.008 JLINK_ReadReg(R15 (PC)) +T714C 001:590.030 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:590.257 - 0.247ms returns 0x30500000 +T714C 001:590.278 JLINK_ClrBPEx(BPHandle = 0x0000002E) +T714C 001:590.295 - 0.017ms returns 0x00 +T714C 001:590.312 JLINK_ReadReg(R0) +T714C 001:590.328 - 0.016ms returns 0x00000000 +T714C 001:590.776 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:590.809 Data: 00 00 02 20 FD B5 00 28 35 B6 00 28 51 B5 00 28 ... +T714C 001:590.839 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:591.890 - 1.113ms returns 0x100 +T714C 001:591.920 JLINK_HasError() +T714C 001:591.939 JLINK_WriteReg(R0, 0x2800B000) +T714C 001:591.957 - 0.018ms returns 0 +T714C 001:591.973 JLINK_WriteReg(R1, 0x00000100) +T714C 001:591.991 - 0.018ms returns 0 +T714C 001:592.007 JLINK_WriteReg(R2, 0x30500674) +T714C 001:592.023 - 0.016ms returns 0 +T714C 001:592.039 JLINK_WriteReg(R3, 0x00000000) +T714C 001:592.055 - 0.015ms returns 0 +T714C 001:592.071 JLINK_WriteReg(R4, 0x00000000) +T714C 001:592.087 - 0.015ms returns 0 +T714C 001:592.103 JLINK_WriteReg(R5, 0x00000000) +T714C 001:592.120 - 0.016ms returns 0 +T714C 001:592.136 JLINK_WriteReg(R6, 0x00000000) +T714C 001:592.151 - 0.015ms returns 0 +T714C 001:592.168 JLINK_WriteReg(R7, 0x00000000) +T714C 001:592.184 - 0.016ms returns 0 +T714C 001:592.200 JLINK_WriteReg(R8, 0x00000000) +T714C 001:592.216 - 0.016ms returns 0 +T714C 001:592.232 JLINK_WriteReg(R9, 0x30500458) +T714C 001:592.248 - 0.015ms returns 0 +T714C 001:592.264 JLINK_WriteReg(R10, 0x00000000) +T714C 001:592.288 - 0.023ms returns 0 +T714C 001:592.304 JLINK_WriteReg(R11, 0x00000000) +T714C 001:592.320 - 0.015ms returns 0 +T714C 001:592.336 JLINK_WriteReg(R12, 0x00000000) +T714C 001:592.352 - 0.015ms returns 0 +T714C 001:592.368 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:592.385 - 0.017ms returns 0 +T714C 001:592.402 JLINK_WriteReg(R14, 0x30500001) +T714C 001:592.417 - 0.015ms returns 0 +T714C 001:592.433 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:592.449 - 0.016ms returns 0 +T714C 001:592.466 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:592.482 - 0.015ms returns 0 +T714C 001:592.498 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:592.515 - 0.016ms returns 0 +T714C 001:592.531 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:592.547 - 0.016ms returns 0 +T714C 001:592.563 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:592.579 - 0.016ms returns 0 +T714C 001:592.596 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:592.613 - 0.017ms returns 0x0000002F +T714C 001:592.629 JLINK_Go() +T714C 001:592.647 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:592.909 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:594.819 - 2.190ms +T714C 001:594.843 JLINK_IsHalted() +T714C 001:595.074 - 0.230ms returns FALSE +T714C 001:595.096 JLINK_HasError() +T714C 001:597.632 JLINK_IsHalted() +T714C 001:599.919 - 2.286ms returns TRUE +T714C 001:599.952 JLINK_ReadReg(R15 (PC)) +T714C 001:599.972 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:600.220 - 0.268ms returns 0x30500000 +T714C 001:600.241 JLINK_ClrBPEx(BPHandle = 0x0000002F) +T714C 001:600.259 - 0.017ms returns 0x00 +T714C 001:600.276 JLINK_ReadReg(R0) +T714C 001:600.292 - 0.016ms returns 0x00000000 +T714C 001:600.832 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:600.873 Data: 31 B6 00 28 31 B6 00 28 31 B6 00 28 81 B6 00 28 ... +T714C 001:600.906 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:601.922 - 1.090ms returns 0x100 +T714C 001:601.946 JLINK_HasError() +T714C 001:601.964 JLINK_WriteReg(R0, 0x2800B100) +T714C 001:601.982 - 0.018ms returns 0 +T714C 001:601.998 JLINK_WriteReg(R1, 0x00000100) +T714C 001:602.047 - 0.048ms returns 0 +T714C 001:602.063 JLINK_WriteReg(R2, 0x30500674) +T714C 001:602.079 - 0.016ms returns 0 +T714C 001:602.095 JLINK_WriteReg(R3, 0x00000000) +T714C 001:602.111 - 0.015ms returns 0 +T714C 001:602.127 JLINK_WriteReg(R4, 0x00000000) +T714C 001:602.143 - 0.015ms returns 0 +T714C 001:602.159 JLINK_WriteReg(R5, 0x00000000) +T714C 001:602.175 - 0.015ms returns 0 +T714C 001:602.191 JLINK_WriteReg(R6, 0x00000000) +T714C 001:602.207 - 0.015ms returns 0 +T714C 001:602.223 JLINK_WriteReg(R7, 0x00000000) +T714C 001:602.239 - 0.015ms returns 0 +T714C 001:602.255 JLINK_WriteReg(R8, 0x00000000) +T714C 001:602.270 - 0.015ms returns 0 +T714C 001:602.287 JLINK_WriteReg(R9, 0x30500458) +T714C 001:602.303 - 0.015ms returns 0 +T714C 001:602.319 JLINK_WriteReg(R10, 0x00000000) +T714C 001:602.334 - 0.015ms returns 0 +T714C 001:602.350 JLINK_WriteReg(R11, 0x00000000) +T714C 001:602.366 - 0.015ms returns 0 +T714C 001:602.383 JLINK_WriteReg(R12, 0x00000000) +T714C 001:602.399 - 0.016ms returns 0 +T714C 001:602.415 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:602.432 - 0.017ms returns 0 +T714C 001:602.448 JLINK_WriteReg(R14, 0x30500001) +T714C 001:602.464 - 0.016ms returns 0 +T714C 001:602.481 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:602.497 - 0.016ms returns 0 +T714C 001:602.513 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:602.529 - 0.016ms returns 0 +T714C 001:602.546 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:602.561 - 0.015ms returns 0 +T714C 001:602.577 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:602.593 - 0.015ms returns 0 +T714C 001:602.610 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:602.626 - 0.016ms returns 0 +T714C 001:602.643 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:602.659 - 0.016ms returns 0x00000030 +T714C 001:602.676 JLINK_Go() +T714C 001:602.694 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:603.048 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:604.974 - 2.297ms +T714C 001:605.656 JLINK_IsHalted() +T714C 001:607.809 - 2.152ms returns TRUE +T714C 001:607.837 JLINK_ReadReg(R15 (PC)) +T714C 001:607.856 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:608.086 - 0.248ms returns 0x30500000 +T714C 001:608.107 JLINK_ClrBPEx(BPHandle = 0x00000030) +T714C 001:608.124 - 0.017ms returns 0x00 +T714C 001:608.142 JLINK_ReadReg(R0) +T714C 001:608.159 - 0.017ms returns 0x00000000 +T714C 001:608.784 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:608.817 Data: 0D B7 00 28 11 B7 00 28 15 B7 00 28 19 B7 00 28 ... +T714C 001:608.848 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:609.922 - 1.138ms returns 0x100 +T714C 001:609.945 JLINK_HasError() +T714C 001:609.962 JLINK_WriteReg(R0, 0x2800B200) +T714C 001:609.980 - 0.017ms returns 0 +T714C 001:609.997 JLINK_WriteReg(R1, 0x00000100) +T714C 001:610.013 - 0.016ms returns 0 +T714C 001:610.030 JLINK_WriteReg(R2, 0x30500674) +T714C 001:610.046 - 0.016ms returns 0 +T714C 001:610.062 JLINK_WriteReg(R3, 0x00000000) +T714C 001:610.079 - 0.016ms returns 0 +T714C 001:610.095 JLINK_WriteReg(R4, 0x00000000) +T714C 001:610.111 - 0.015ms returns 0 +T714C 001:610.127 JLINK_WriteReg(R5, 0x00000000) +T714C 001:610.143 - 0.015ms returns 0 +T714C 001:610.159 JLINK_WriteReg(R6, 0x00000000) +T714C 001:610.175 - 0.016ms returns 0 +T714C 001:610.191 JLINK_WriteReg(R7, 0x00000000) +T714C 001:610.206 - 0.015ms returns 0 +T714C 001:610.223 JLINK_WriteReg(R8, 0x00000000) +T714C 001:610.239 - 0.016ms returns 0 +T714C 001:610.257 JLINK_WriteReg(R9, 0x30500458) +T714C 001:610.274 - 0.017ms returns 0 +T714C 001:610.296 JLINK_WriteReg(R10, 0x00000000) +T714C 001:610.313 - 0.016ms returns 0 +T714C 001:610.329 JLINK_WriteReg(R11, 0x00000000) +T714C 001:610.346 - 0.016ms returns 0 +T714C 001:610.362 JLINK_WriteReg(R12, 0x00000000) +T714C 001:610.377 - 0.015ms returns 0 +T714C 001:610.394 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:610.411 - 0.017ms returns 0 +T714C 001:610.427 JLINK_WriteReg(R14, 0x30500001) +T714C 001:610.443 - 0.015ms returns 0 +T714C 001:610.459 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:610.475 - 0.016ms returns 0 +T714C 001:610.491 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:610.507 - 0.016ms returns 0 +T714C 001:610.523 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:610.540 - 0.016ms returns 0 +T714C 001:610.556 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:610.572 - 0.015ms returns 0 +T714C 001:610.588 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:610.604 - 0.015ms returns 0 +T714C 001:610.621 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:610.637 - 0.016ms returns 0x00000031 +T714C 001:610.653 JLINK_Go() +T714C 001:610.670 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:610.940 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:612.915 - 2.261ms +T714C 001:612.938 JLINK_IsHalted() +T714C 001:613.155 - 0.216ms returns FALSE +T714C 001:613.175 JLINK_HasError() +T714C 001:614.455 JLINK_IsHalted() +T714C 001:616.564 - 2.109ms returns TRUE +T714C 001:616.603 JLINK_ReadReg(R15 (PC)) +T714C 001:616.622 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:616.865 - 0.262ms returns 0x30500000 +T714C 001:616.887 JLINK_ClrBPEx(BPHandle = 0x00000031) +T714C 001:616.904 - 0.016ms returns 0x00 +T714C 001:616.921 JLINK_ReadReg(R0) +T714C 001:616.937 - 0.016ms returns 0x00000000 +T714C 001:618.008 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:618.062 Data: 31 B6 00 28 31 B6 00 28 31 B6 00 28 31 B6 00 28 ... +T714C 001:618.097 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:619.110 - 1.100ms returns 0x100 +T714C 001:619.170 JLINK_HasError() +T714C 001:619.189 JLINK_WriteReg(R0, 0x2800B300) +T714C 001:619.212 - 0.022ms returns 0 +T714C 001:619.229 JLINK_WriteReg(R1, 0x00000100) +T714C 001:619.248 - 0.019ms returns 0 +T714C 001:619.266 JLINK_WriteReg(R2, 0x30500674) +T714C 001:619.282 - 0.016ms returns 0 +T714C 001:619.299 JLINK_WriteReg(R3, 0x00000000) +T714C 001:619.315 - 0.016ms returns 0 +T714C 001:619.331 JLINK_WriteReg(R4, 0x00000000) +T714C 001:619.347 - 0.016ms returns 0 +T714C 001:619.363 JLINK_WriteReg(R5, 0x00000000) +T714C 001:619.379 - 0.015ms returns 0 +T714C 001:619.401 JLINK_WriteReg(R6, 0x00000000) +T714C 001:619.420 - 0.019ms returns 0 +T714C 001:619.435 JLINK_WriteReg(R7, 0x00000000) +T714C 001:619.452 - 0.016ms returns 0 +T714C 001:619.468 JLINK_WriteReg(R8, 0x00000000) +T714C 001:619.484 - 0.016ms returns 0 +T714C 001:619.500 JLINK_WriteReg(R9, 0x30500458) +T714C 001:619.516 - 0.015ms returns 0 +T714C 001:619.532 JLINK_WriteReg(R10, 0x00000000) +T714C 001:619.549 - 0.016ms returns 0 +T714C 001:619.565 JLINK_WriteReg(R11, 0x00000000) +T714C 001:619.582 - 0.016ms returns 0 +T714C 001:619.598 JLINK_WriteReg(R12, 0x00000000) +T714C 001:619.613 - 0.015ms returns 0 +T714C 001:619.630 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:619.647 - 0.017ms returns 0 +T714C 001:619.663 JLINK_WriteReg(R14, 0x30500001) +T714C 001:619.679 - 0.015ms returns 0 +T714C 001:619.695 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:619.711 - 0.016ms returns 0 +T714C 001:619.727 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:619.744 - 0.016ms returns 0 +T714C 001:619.762 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:619.778 - 0.016ms returns 0 +T714C 001:619.795 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:619.811 - 0.016ms returns 0 +T714C 001:619.828 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:619.844 - 0.015ms returns 0 +T714C 001:619.861 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:619.877 - 0.017ms returns 0x00000032 +T714C 001:619.894 JLINK_Go() +T714C 001:619.913 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:620.194 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:622.212 - 2.317ms +T714C 001:622.275 JLINK_IsHalted() +T714C 001:622.540 - 0.264ms returns FALSE +T714C 001:622.560 JLINK_HasError() +T714C 001:625.268 JLINK_IsHalted() +T714C 001:627.532 - 2.264ms returns TRUE +T714C 001:627.558 JLINK_ReadReg(R15 (PC)) +T714C 001:627.576 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:627.824 - 0.265ms returns 0x30500000 +T714C 001:627.845 JLINK_ClrBPEx(BPHandle = 0x00000032) +T714C 001:627.862 - 0.016ms returns 0x00 +T714C 001:627.878 JLINK_ReadReg(R0) +T714C 001:627.895 - 0.016ms returns 0x00000000 +T714C 001:628.399 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:628.430 Data: DF F8 0C D0 00 F0 6C FE 00 48 00 47 85 C1 00 28 ... +T714C 001:628.461 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:629.515 - 1.116ms returns 0x100 +T714C 001:629.538 JLINK_HasError() +T714C 001:629.555 JLINK_WriteReg(R0, 0x2800B400) +T714C 001:629.573 - 0.017ms returns 0 +T714C 001:629.590 JLINK_WriteReg(R1, 0x00000100) +T714C 001:629.605 - 0.015ms returns 0 +T714C 001:629.621 JLINK_WriteReg(R2, 0x30500674) +T714C 001:629.638 - 0.016ms returns 0 +T714C 001:629.655 JLINK_WriteReg(R3, 0x00000000) +T714C 001:629.671 - 0.016ms returns 0 +T714C 001:629.688 JLINK_WriteReg(R4, 0x00000000) +T714C 001:629.704 - 0.016ms returns 0 +T714C 001:629.720 JLINK_WriteReg(R5, 0x00000000) +T714C 001:629.736 - 0.015ms returns 0 +T714C 001:629.784 JLINK_WriteReg(R6, 0x00000000) +T714C 001:629.799 - 0.015ms returns 0 +T714C 001:629.815 JLINK_WriteReg(R7, 0x00000000) +T714C 001:629.831 - 0.015ms returns 0 +T714C 001:629.847 JLINK_WriteReg(R8, 0x00000000) +T714C 001:629.863 - 0.015ms returns 0 +T714C 001:629.880 JLINK_WriteReg(R9, 0x30500458) +T714C 001:629.895 - 0.015ms returns 0 +T714C 001:629.911 JLINK_WriteReg(R10, 0x00000000) +T714C 001:629.927 - 0.016ms returns 0 +T714C 001:629.943 JLINK_WriteReg(R11, 0x00000000) +T714C 001:629.959 - 0.015ms returns 0 +T714C 001:629.975 JLINK_WriteReg(R12, 0x00000000) +T714C 001:629.992 - 0.016ms returns 0 +T714C 001:630.007 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:630.025 - 0.017ms returns 0 +T714C 001:630.041 JLINK_WriteReg(R14, 0x30500001) +T714C 001:630.057 - 0.015ms returns 0 +T714C 001:630.073 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:630.089 - 0.016ms returns 0 +T714C 001:630.105 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:630.121 - 0.015ms returns 0 +T714C 001:630.137 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:630.153 - 0.015ms returns 0 +T714C 001:630.169 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:630.184 - 0.015ms returns 0 +T714C 001:630.201 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:630.222 - 0.021ms returns 0 +T714C 001:630.242 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:630.258 - 0.016ms returns 0x00000033 +T714C 001:630.275 JLINK_Go() +T714C 001:630.292 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:630.595 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:632.363 - 2.088ms +T714C 001:632.402 JLINK_IsHalted() +T714C 001:632.733 - 0.329ms returns FALSE +T714C 001:632.872 JLINK_HasError() +T714C 001:634.761 JLINK_IsHalted() +T714C 001:637.136 - 2.375ms returns TRUE +T714C 001:637.175 JLINK_ReadReg(R15 (PC)) +T714C 001:637.197 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:637.488 - 0.312ms returns 0x30500000 +T714C 001:637.532 JLINK_ClrBPEx(BPHandle = 0x00000033) +T714C 001:637.551 - 0.018ms returns 0x00 +T714C 001:637.569 JLINK_ReadReg(R0) +T714C 001:637.586 - 0.017ms returns 0x00000000 +T714C 001:638.181 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:638.215 Data: 70 47 2A 49 08 60 EF F3 14 82 22 F0 04 02 82 F3 ... +T714C 001:638.247 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:639.330 - 1.148ms returns 0x100 +T714C 001:639.354 JLINK_HasError() +T714C 001:639.371 JLINK_WriteReg(R0, 0x2800B500) +T714C 001:639.389 - 0.017ms returns 0 +T714C 001:639.405 JLINK_WriteReg(R1, 0x00000100) +T714C 001:639.421 - 0.016ms returns 0 +T714C 001:639.437 JLINK_WriteReg(R2, 0x30500674) +T714C 001:639.453 - 0.015ms returns 0 +T714C 001:639.469 JLINK_WriteReg(R3, 0x00000000) +T714C 001:639.485 - 0.015ms returns 0 +T714C 001:639.500 JLINK_WriteReg(R4, 0x00000000) +T714C 001:639.517 - 0.016ms returns 0 +T714C 001:639.533 JLINK_WriteReg(R5, 0x00000000) +T714C 001:639.550 - 0.016ms returns 0 +T714C 001:639.566 JLINK_WriteReg(R6, 0x00000000) +T714C 001:639.582 - 0.016ms returns 0 +T714C 001:639.598 JLINK_WriteReg(R7, 0x00000000) +T714C 001:639.614 - 0.015ms returns 0 +T714C 001:639.631 JLINK_WriteReg(R8, 0x00000000) +T714C 001:639.646 - 0.015ms returns 0 +T714C 001:639.662 JLINK_WriteReg(R9, 0x30500458) +T714C 001:639.678 - 0.016ms returns 0 +T714C 001:639.694 JLINK_WriteReg(R10, 0x00000000) +T714C 001:639.711 - 0.016ms returns 0 +T714C 001:639.727 JLINK_WriteReg(R11, 0x00000000) +T714C 001:639.742 - 0.015ms returns 0 +T714C 001:639.759 JLINK_WriteReg(R12, 0x00000000) +T714C 001:639.775 - 0.016ms returns 0 +T714C 001:639.791 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:639.808 - 0.016ms returns 0 +T714C 001:639.825 JLINK_WriteReg(R14, 0x30500001) +T714C 001:639.841 - 0.016ms returns 0 +T714C 001:639.857 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:639.873 - 0.016ms returns 0 +T714C 001:639.889 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:639.904 - 0.015ms returns 0 +T714C 001:639.921 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:639.937 - 0.015ms returns 0 +T714C 001:639.953 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:639.969 - 0.015ms returns 0 +T714C 001:639.985 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:640.000 - 0.015ms returns 0 +T714C 001:640.017 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:640.033 - 0.016ms returns 0x00000034 +T714C 001:640.049 JLINK_Go() +T714C 001:640.067 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:640.340 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:642.276 - 2.226ms +T714C 001:642.298 JLINK_IsHalted() +T714C 001:642.539 - 0.240ms returns FALSE +T714C 001:642.560 JLINK_HasError() +T714C 001:643.774 JLINK_IsHalted() +T714C 001:645.961 - 2.189ms returns TRUE +T714C 001:645.983 JLINK_ReadReg(R15 (PC)) +T714C 001:646.000 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:646.228 - 0.244ms returns 0x30500000 +T714C 001:646.248 JLINK_ClrBPEx(BPHandle = 0x00000034) +T714C 001:646.264 - 0.016ms returns 0x00 +T714C 001:646.280 JLINK_ReadReg(R0) +T714C 001:646.298 - 0.017ms returns 0x00000000 +T714C 001:646.721 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:646.753 Data: 07 49 01 60 0A 68 82 F3 08 88 06 48 80 F3 0A 88 ... +T714C 001:646.781 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:647.789 - 1.068ms returns 0x100 +T714C 001:647.821 JLINK_HasError() +T714C 001:647.838 JLINK_WriteReg(R0, 0x2800B600) +T714C 001:647.862 - 0.023ms returns 0 +T714C 001:647.881 JLINK_WriteReg(R1, 0x00000100) +T714C 001:647.898 - 0.017ms returns 0 +T714C 001:647.914 JLINK_WriteReg(R2, 0x30500674) +T714C 001:647.936 - 0.021ms returns 0 +T714C 001:647.968 JLINK_WriteReg(R3, 0x00000000) +T714C 001:647.991 - 0.023ms returns 0 +T714C 001:648.016 JLINK_WriteReg(R4, 0x00000000) +T714C 001:648.033 - 0.017ms returns 0 +T714C 001:648.050 JLINK_WriteReg(R5, 0x00000000) +T714C 001:648.067 - 0.017ms returns 0 +T714C 001:648.084 JLINK_WriteReg(R6, 0x00000000) +T714C 001:648.101 - 0.017ms returns 0 +T714C 001:648.118 JLINK_WriteReg(R7, 0x00000000) +T714C 001:648.134 - 0.016ms returns 0 +T714C 001:648.151 JLINK_WriteReg(R8, 0x00000000) +T714C 001:648.168 - 0.017ms returns 0 +T714C 001:648.186 JLINK_WriteReg(R9, 0x30500458) +T714C 001:648.202 - 0.016ms returns 0 +T714C 001:648.219 JLINK_WriteReg(R10, 0x00000000) +T714C 001:648.272 - 0.052ms returns 0 +T714C 001:648.292 JLINK_WriteReg(R11, 0x00000000) +T714C 001:648.311 - 0.019ms returns 0 +T714C 001:648.329 JLINK_WriteReg(R12, 0x00000000) +T714C 001:648.351 - 0.022ms returns 0 +T714C 001:648.402 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:648.447 - 0.044ms returns 0 +T714C 001:648.466 JLINK_WriteReg(R14, 0x30500001) +T714C 001:648.482 - 0.016ms returns 0 +T714C 001:648.499 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:648.515 - 0.016ms returns 0 +T714C 001:648.532 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:648.548 - 0.016ms returns 0 +T714C 001:648.564 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:648.581 - 0.017ms returns 0 +T714C 001:648.598 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:648.614 - 0.016ms returns 0 +T714C 001:648.631 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:648.646 - 0.015ms returns 0 +T714C 001:648.664 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:648.689 - 0.025ms returns 0x00000035 +T714C 001:648.707 JLINK_Go() +T714C 001:648.725 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:649.053 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:651.152 - 2.444ms +T714C 001:651.203 JLINK_IsHalted() +T714C 001:651.410 - 0.207ms returns FALSE +T714C 001:651.431 JLINK_HasError() +T714C 001:653.516 JLINK_IsHalted() +T714C 001:655.816 - 2.299ms returns TRUE +T714C 001:655.866 JLINK_ReadReg(R15 (PC)) +T714C 001:655.885 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:656.136 - 0.269ms returns 0x30500000 +T714C 001:656.182 JLINK_ClrBPEx(BPHandle = 0x00000035) +T714C 001:656.201 - 0.018ms returns 0x00 +T714C 001:656.218 JLINK_ReadReg(R0) +T714C 001:656.235 - 0.017ms returns 0x00000000 +T714C 001:656.845 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:656.876 Data: 67 48 00 47 67 48 00 47 67 48 00 47 67 48 00 47 ... +T714C 001:656.908 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:657.992 - 1.147ms returns 0x100 +T714C 001:658.038 JLINK_HasError() +T714C 001:658.057 JLINK_WriteReg(R0, 0x2800B700) +T714C 001:658.077 - 0.019ms returns 0 +T714C 001:658.093 JLINK_WriteReg(R1, 0x00000100) +T714C 001:658.109 - 0.015ms returns 0 +T714C 001:658.124 JLINK_WriteReg(R2, 0x30500674) +T714C 001:658.140 - 0.015ms returns 0 +T714C 001:658.156 JLINK_WriteReg(R3, 0x00000000) +T714C 001:658.171 - 0.015ms returns 0 +T714C 001:658.187 JLINK_WriteReg(R4, 0x00000000) +T714C 001:658.203 - 0.015ms returns 0 +T714C 001:658.219 JLINK_WriteReg(R5, 0x00000000) +T714C 001:658.234 - 0.015ms returns 0 +T714C 001:658.250 JLINK_WriteReg(R6, 0x00000000) +T714C 001:658.266 - 0.016ms returns 0 +T714C 001:658.282 JLINK_WriteReg(R7, 0x00000000) +T714C 001:658.298 - 0.015ms returns 0 +T714C 001:658.314 JLINK_WriteReg(R8, 0x00000000) +T714C 001:658.330 - 0.016ms returns 0 +T714C 001:658.346 JLINK_WriteReg(R9, 0x30500458) +T714C 001:658.361 - 0.015ms returns 0 +T714C 001:658.377 JLINK_WriteReg(R10, 0x00000000) +T714C 001:658.393 - 0.016ms returns 0 +T714C 001:658.409 JLINK_WriteReg(R11, 0x00000000) +T714C 001:658.424 - 0.015ms returns 0 +T714C 001:658.440 JLINK_WriteReg(R12, 0x00000000) +T714C 001:658.456 - 0.016ms returns 0 +T714C 001:658.472 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:658.488 - 0.016ms returns 0 +T714C 001:658.508 JLINK_WriteReg(R14, 0x30500001) +T714C 001:658.526 - 0.017ms returns 0 +T714C 001:658.542 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:658.558 - 0.015ms returns 0 +T714C 001:658.573 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:658.589 - 0.015ms returns 0 +T714C 001:658.604 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:658.620 - 0.015ms returns 0 +T714C 001:658.636 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:658.651 - 0.015ms returns 0 +T714C 001:658.667 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:658.682 - 0.015ms returns 0 +T714C 001:658.699 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:658.715 - 0.017ms returns 0x00000036 +T714C 001:658.732 JLINK_Go() +T714C 001:658.749 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:659.081 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:661.270 - 2.537ms +T714C 001:661.959 JLINK_IsHalted() +T714C 001:664.213 - 2.253ms returns TRUE +T714C 001:664.281 JLINK_ReadReg(R15 (PC)) +T714C 001:664.303 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:664.550 - 0.268ms returns 0x30500000 +T714C 001:664.589 JLINK_ClrBPEx(BPHandle = 0x00000036) +T714C 001:664.607 - 0.018ms returns 0x00 +T714C 001:664.624 JLINK_ReadReg(R0) +T714C 001:664.642 - 0.018ms returns 0x00000000 +T714C 001:665.455 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:665.501 Data: 31 B6 00 28 B9 D3 00 28 15 D4 00 28 31 B6 00 28 ... +T714C 001:665.580 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:666.601 - 1.145ms returns 0x100 +T714C 001:666.662 JLINK_HasError() +T714C 001:666.681 JLINK_WriteReg(R0, 0x2800B800) +T714C 001:666.702 - 0.021ms returns 0 +T714C 001:666.718 JLINK_WriteReg(R1, 0x00000100) +T714C 001:666.769 - 0.051ms returns 0 +T714C 001:666.786 JLINK_WriteReg(R2, 0x30500674) +T714C 001:666.803 - 0.016ms returns 0 +T714C 001:666.819 JLINK_WriteReg(R3, 0x00000000) +T714C 001:666.835 - 0.015ms returns 0 +T714C 001:666.851 JLINK_WriteReg(R4, 0x00000000) +T714C 001:666.867 - 0.016ms returns 0 +T714C 001:666.883 JLINK_WriteReg(R5, 0x00000000) +T714C 001:666.900 - 0.017ms returns 0 +T714C 001:666.916 JLINK_WriteReg(R6, 0x00000000) +T714C 001:666.932 - 0.015ms returns 0 +T714C 001:666.949 JLINK_WriteReg(R7, 0x00000000) +T714C 001:666.964 - 0.015ms returns 0 +T714C 001:666.981 JLINK_WriteReg(R8, 0x00000000) +T714C 001:666.997 - 0.016ms returns 0 +T714C 001:667.013 JLINK_WriteReg(R9, 0x30500458) +T714C 001:667.029 - 0.015ms returns 0 +T714C 001:667.045 JLINK_WriteReg(R10, 0x00000000) +T714C 001:667.061 - 0.016ms returns 0 +T714C 001:667.077 JLINK_WriteReg(R11, 0x00000000) +T714C 001:667.093 - 0.015ms returns 0 +T714C 001:667.109 JLINK_WriteReg(R12, 0x00000000) +T714C 001:667.125 - 0.015ms returns 0 +T714C 001:667.141 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:667.158 - 0.017ms returns 0 +T714C 001:667.174 JLINK_WriteReg(R14, 0x30500001) +T714C 001:667.191 - 0.016ms returns 0 +T714C 001:667.207 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:667.224 - 0.016ms returns 0 +T714C 001:667.240 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:667.256 - 0.016ms returns 0 +T714C 001:667.272 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:667.288 - 0.015ms returns 0 +T714C 001:667.304 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:667.320 - 0.015ms returns 0 +T714C 001:667.336 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:667.352 - 0.016ms returns 0 +T714C 001:667.369 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:667.386 - 0.017ms returns 0x00000037 +T714C 001:667.403 JLINK_Go() +T714C 001:667.421 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:667.717 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:669.671 - 2.268ms +T714C 001:669.693 JLINK_IsHalted() +T714C 001:669.900 - 0.206ms returns FALSE +T714C 001:669.920 JLINK_HasError() +T714C 001:671.788 JLINK_IsHalted() +T714C 001:673.998 - 2.211ms returns TRUE +T714C 001:674.019 JLINK_ReadReg(R15 (PC)) +T714C 001:674.036 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:674.278 - 0.258ms returns 0x30500000 +T714C 001:674.327 JLINK_ClrBPEx(BPHandle = 0x00000037) +T714C 001:674.346 - 0.019ms returns 0x00 +T714C 001:674.362 JLINK_ReadReg(R0) +T714C 001:674.385 - 0.022ms returns 0x00000000 +T714C 001:674.927 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:674.959 Data: 31 B6 00 28 31 B6 00 28 31 B6 00 28 31 B6 00 28 ... +T714C 001:674.988 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:676.122 - 1.194ms returns 0x100 +T714C 001:676.169 JLINK_HasError() +T714C 001:676.187 JLINK_WriteReg(R0, 0x2800B900) +T714C 001:676.206 - 0.018ms returns 0 +T714C 001:676.223 JLINK_WriteReg(R1, 0x00000100) +T714C 001:676.239 - 0.016ms returns 0 +T714C 001:676.255 JLINK_WriteReg(R2, 0x30500674) +T714C 001:676.270 - 0.015ms returns 0 +T714C 001:676.287 JLINK_WriteReg(R3, 0x00000000) +T714C 001:676.303 - 0.015ms returns 0 +T714C 001:676.318 JLINK_WriteReg(R4, 0x00000000) +T714C 001:676.334 - 0.015ms returns 0 +T714C 001:676.350 JLINK_WriteReg(R5, 0x00000000) +T714C 001:676.365 - 0.015ms returns 0 +T714C 001:676.382 JLINK_WriteReg(R6, 0x00000000) +T714C 001:676.397 - 0.015ms returns 0 +T714C 001:676.413 JLINK_WriteReg(R7, 0x00000000) +T714C 001:676.429 - 0.015ms returns 0 +T714C 001:676.445 JLINK_WriteReg(R8, 0x00000000) +T714C 001:676.461 - 0.015ms returns 0 +T714C 001:676.476 JLINK_WriteReg(R9, 0x30500458) +T714C 001:676.492 - 0.015ms returns 0 +T714C 001:676.508 JLINK_WriteReg(R10, 0x00000000) +T714C 001:676.524 - 0.016ms returns 0 +T714C 001:676.540 JLINK_WriteReg(R11, 0x00000000) +T714C 001:676.555 - 0.015ms returns 0 +T714C 001:676.571 JLINK_WriteReg(R12, 0x00000000) +T714C 001:676.586 - 0.015ms returns 0 +T714C 001:676.602 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:676.619 - 0.016ms returns 0 +T714C 001:676.635 JLINK_WriteReg(R14, 0x30500001) +T714C 001:676.650 - 0.015ms returns 0 +T714C 001:676.667 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:676.682 - 0.015ms returns 0 +T714C 001:676.699 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:676.714 - 0.015ms returns 0 +T714C 001:676.730 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:676.747 - 0.016ms returns 0 +T714C 001:676.763 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:676.779 - 0.015ms returns 0 +T714C 001:676.794 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:676.810 - 0.015ms returns 0 +T714C 001:676.826 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:676.842 - 0.016ms returns 0x00000038 +T714C 001:676.859 JLINK_Go() +T714C 001:676.876 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:677.204 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:679.218 - 2.358ms +T714C 001:679.281 JLINK_IsHalted() +T714C 001:679.564 - 0.282ms returns FALSE +T714C 001:679.593 JLINK_HasError() +T714C 001:681.002 JLINK_IsHalted() +T714C 001:683.136 - 2.132ms returns TRUE +T714C 001:683.190 JLINK_ReadReg(R15 (PC)) +T714C 001:683.211 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:683.482 - 0.291ms returns 0x30500000 +T714C 001:683.536 JLINK_ClrBPEx(BPHandle = 0x00000038) +T714C 001:683.554 - 0.018ms returns 0x00 +T714C 001:683.572 JLINK_ReadReg(R0) +T714C 001:683.590 - 0.018ms returns 0x00000000 +T714C 001:684.245 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:684.281 Data: 01 4B 52 1E F9 D2 10 BD D2 B2 01 E0 00 F8 01 2B ... +T714C 001:684.314 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:685.403 - 1.157ms returns 0x100 +T714C 001:685.428 JLINK_HasError() +T714C 001:685.445 JLINK_WriteReg(R0, 0x2800BA00) +T714C 001:685.463 - 0.018ms returns 0 +T714C 001:685.480 JLINK_WriteReg(R1, 0x00000100) +T714C 001:685.496 - 0.016ms returns 0 +T714C 001:685.512 JLINK_WriteReg(R2, 0x30500674) +T714C 001:685.528 - 0.015ms returns 0 +T714C 001:685.545 JLINK_WriteReg(R3, 0x00000000) +T714C 001:685.561 - 0.016ms returns 0 +T714C 001:685.578 JLINK_WriteReg(R4, 0x00000000) +T714C 001:685.595 - 0.016ms returns 0 +T714C 001:685.611 JLINK_WriteReg(R5, 0x00000000) +T714C 001:685.627 - 0.015ms returns 0 +T714C 001:685.643 JLINK_WriteReg(R6, 0x00000000) +T714C 001:685.658 - 0.015ms returns 0 +T714C 001:685.675 JLINK_WriteReg(R7, 0x00000000) +T714C 001:685.691 - 0.015ms returns 0 +T714C 001:685.707 JLINK_WriteReg(R8, 0x00000000) +T714C 001:685.723 - 0.015ms returns 0 +T714C 001:685.739 JLINK_WriteReg(R9, 0x30500458) +T714C 001:685.755 - 0.015ms returns 0 +T714C 001:685.833 JLINK_WriteReg(R10, 0x00000000) +T714C 001:685.853 - 0.020ms returns 0 +T714C 001:685.870 JLINK_WriteReg(R11, 0x00000000) +T714C 001:685.886 - 0.016ms returns 0 +T714C 001:685.903 JLINK_WriteReg(R12, 0x00000000) +T714C 001:685.919 - 0.016ms returns 0 +T714C 001:685.936 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:685.968 - 0.032ms returns 0 +T714C 001:685.985 JLINK_WriteReg(R14, 0x30500001) +T714C 001:686.002 - 0.017ms returns 0 +T714C 001:686.020 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:686.036 - 0.016ms returns 0 +T714C 001:686.052 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:686.068 - 0.016ms returns 0 +T714C 001:686.084 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:686.100 - 0.015ms returns 0 +T714C 001:686.117 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:686.132 - 0.015ms returns 0 +T714C 001:686.149 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:686.165 - 0.016ms returns 0 +T714C 001:686.181 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:686.198 - 0.017ms returns 0x00000039 +T714C 001:686.215 JLINK_Go() +T714C 001:686.233 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:686.548 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:688.511 - 2.296ms +T714C 001:689.128 JLINK_IsHalted() +T714C 001:691.294 - 2.165ms returns TRUE +T714C 001:691.318 JLINK_ReadReg(R15 (PC)) +T714C 001:691.336 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:691.540 - 0.222ms returns 0x30500000 +T714C 001:691.560 JLINK_ClrBPEx(BPHandle = 0x00000039) +T714C 001:691.578 - 0.017ms returns 0x00 +T714C 001:691.595 JLINK_ReadReg(R0) +T714C 001:691.612 - 0.016ms returns 0x00000000 +T714C 001:692.110 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:692.146 Data: 00 21 CA F8 00 10 5A 46 39 46 20 46 00 F0 03 FA ... +T714C 001:692.175 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:693.104 - 0.994ms returns 0x100 +T714C 001:693.156 JLINK_HasError() +T714C 001:693.183 JLINK_WriteReg(R0, 0x2800BB00) +T714C 001:693.213 - 0.029ms returns 0 +T714C 001:693.238 JLINK_WriteReg(R1, 0x00000100) +T714C 001:693.261 - 0.023ms returns 0 +T714C 001:693.285 JLINK_WriteReg(R2, 0x30500674) +T714C 001:693.309 - 0.023ms returns 0 +T714C 001:693.336 JLINK_WriteReg(R3, 0x00000000) +T714C 001:693.355 - 0.019ms returns 0 +T714C 001:693.377 JLINK_WriteReg(R4, 0x00000000) +T714C 001:693.397 - 0.019ms returns 0 +T714C 001:693.418 JLINK_WriteReg(R5, 0x00000000) +T714C 001:693.436 - 0.017ms returns 0 +T714C 001:693.453 JLINK_WriteReg(R6, 0x00000000) +T714C 001:693.472 - 0.019ms returns 0 +T714C 001:693.490 JLINK_WriteReg(R7, 0x00000000) +T714C 001:693.508 - 0.017ms returns 0 +T714C 001:693.526 JLINK_WriteReg(R8, 0x00000000) +T714C 001:693.543 - 0.017ms returns 0 +T714C 001:693.561 JLINK_WriteReg(R9, 0x30500458) +T714C 001:693.578 - 0.017ms returns 0 +T714C 001:693.601 JLINK_WriteReg(R10, 0x00000000) +T714C 001:693.620 - 0.019ms returns 0 +T714C 001:693.639 JLINK_WriteReg(R11, 0x00000000) +T714C 001:693.657 - 0.018ms returns 0 +T714C 001:693.674 JLINK_WriteReg(R12, 0x00000000) +T714C 001:693.693 - 0.018ms returns 0 +T714C 001:693.714 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:693.735 - 0.020ms returns 0 +T714C 001:693.753 JLINK_WriteReg(R14, 0x30500001) +T714C 001:693.770 - 0.016ms returns 0 +T714C 001:693.786 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:693.803 - 0.016ms returns 0 +T714C 001:693.821 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:693.840 - 0.018ms returns 0 +T714C 001:693.858 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:693.876 - 0.017ms returns 0 +T714C 001:693.895 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:693.915 - 0.020ms returns 0 +T714C 001:693.938 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:693.963 - 0.025ms returns 0 +T714C 001:693.987 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:694.008 - 0.020ms returns 0x0000003A +T714C 001:694.026 JLINK_Go() +T714C 001:694.050 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:694.379 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:696.476 - 2.448ms +T714C 001:696.543 JLINK_IsHalted() +T714C 001:696.839 - 0.296ms returns FALSE +T714C 001:696.870 JLINK_HasError() +T714C 001:698.023 JLINK_IsHalted() +T714C 001:700.426 - 2.402ms returns TRUE +T714C 001:700.494 JLINK_ReadReg(R15 (PC)) +T714C 001:700.523 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:700.814 - 0.320ms returns 0x30500000 +T714C 001:700.849 JLINK_ClrBPEx(BPHandle = 0x0000003A) +T714C 001:700.867 - 0.018ms returns 0x00 +T714C 001:700.885 JLINK_ReadReg(R0) +T714C 001:700.903 - 0.018ms returns 0x00000000 +T714C 001:701.596 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:701.640 Data: 02 EA 07 52 CD E9 00 42 00 1C 41 F5 80 11 32 46 ... +T714C 001:701.679 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:702.727 - 1.130ms returns 0x100 +T714C 001:702.767 JLINK_HasError() +T714C 001:702.787 JLINK_WriteReg(R0, 0x2800BC00) +T714C 001:702.808 - 0.021ms returns 0 +T714C 001:702.825 JLINK_WriteReg(R1, 0x00000100) +T714C 001:702.842 - 0.016ms returns 0 +T714C 001:702.859 JLINK_WriteReg(R2, 0x30500674) +T714C 001:702.876 - 0.016ms returns 0 +T714C 001:702.893 JLINK_WriteReg(R3, 0x00000000) +T714C 001:702.910 - 0.016ms returns 0 +T714C 001:702.927 JLINK_WriteReg(R4, 0x00000000) +T714C 001:702.944 - 0.017ms returns 0 +T714C 001:702.961 JLINK_WriteReg(R5, 0x00000000) +T714C 001:702.977 - 0.016ms returns 0 +T714C 001:702.994 JLINK_WriteReg(R6, 0x00000000) +T714C 001:703.011 - 0.017ms returns 0 +T714C 001:703.028 JLINK_WriteReg(R7, 0x00000000) +T714C 001:703.044 - 0.016ms returns 0 +T714C 001:703.061 JLINK_WriteReg(R8, 0x00000000) +T714C 001:703.078 - 0.016ms returns 0 +T714C 001:703.097 JLINK_WriteReg(R9, 0x30500458) +T714C 001:703.114 - 0.017ms returns 0 +T714C 001:703.131 JLINK_WriteReg(R10, 0x00000000) +T714C 001:703.147 - 0.016ms returns 0 +T714C 001:703.164 JLINK_WriteReg(R11, 0x00000000) +T714C 001:703.180 - 0.016ms returns 0 +T714C 001:703.196 JLINK_WriteReg(R12, 0x00000000) +T714C 001:703.212 - 0.015ms returns 0 +T714C 001:703.229 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:703.251 - 0.022ms returns 0 +T714C 001:703.267 JLINK_WriteReg(R14, 0x30500001) +T714C 001:703.284 - 0.016ms returns 0 +T714C 001:703.301 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:703.317 - 0.016ms returns 0 +T714C 001:703.334 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:703.351 - 0.016ms returns 0 +T714C 001:703.367 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:703.384 - 0.016ms returns 0 +T714C 001:703.400 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:703.416 - 0.016ms returns 0 +T714C 001:703.437 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:703.453 - 0.016ms returns 0 +T714C 001:703.471 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:703.488 - 0.017ms returns 0x0000003B +T714C 001:703.505 JLINK_Go() +T714C 001:703.523 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:703.865 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:705.728 - 2.223ms +T714C 001:705.776 JLINK_IsHalted() +T714C 001:706.003 - 0.226ms returns FALSE +T714C 001:706.025 JLINK_HasError() +T714C 001:707.399 JLINK_IsHalted() +T714C 001:709.628 - 2.227ms returns TRUE +T714C 001:709.725 JLINK_ReadReg(R15 (PC)) +T714C 001:709.767 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:710.103 - 0.377ms returns 0x30500000 +T714C 001:710.174 JLINK_ClrBPEx(BPHandle = 0x0000003B) +T714C 001:710.212 - 0.037ms returns 0x00 +T714C 001:710.248 JLINK_ReadReg(R0) +T714C 001:710.284 - 0.035ms returns 0x00000000 +T714C 001:711.103 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:711.150 Data: 47 EA 83 57 A4 FB 07 68 02 95 8D 0A 05 FB 07 85 ... +T714C 001:711.191 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:712.226 - 1.122ms returns 0x100 +T714C 001:712.290 JLINK_HasError() +T714C 001:712.322 JLINK_WriteReg(R0, 0x2800BD00) +T714C 001:712.346 - 0.024ms returns 0 +T714C 001:712.364 JLINK_WriteReg(R1, 0x00000100) +T714C 001:712.380 - 0.016ms returns 0 +T714C 001:712.397 JLINK_WriteReg(R2, 0x30500674) +T714C 001:712.413 - 0.016ms returns 0 +T714C 001:712.430 JLINK_WriteReg(R3, 0x00000000) +T714C 001:712.490 - 0.060ms returns 0 +T714C 001:712.507 JLINK_WriteReg(R4, 0x00000000) +T714C 001:712.524 - 0.016ms returns 0 +T714C 001:712.540 JLINK_WriteReg(R5, 0x00000000) +T714C 001:712.563 - 0.022ms returns 0 +T714C 001:712.581 JLINK_WriteReg(R6, 0x00000000) +T714C 001:712.598 - 0.016ms returns 0 +T714C 001:712.614 JLINK_WriteReg(R7, 0x00000000) +T714C 001:712.631 - 0.016ms returns 0 +T714C 001:712.648 JLINK_WriteReg(R8, 0x00000000) +T714C 001:712.671 - 0.023ms returns 0 +T714C 001:712.688 JLINK_WriteReg(R9, 0x30500458) +T714C 001:712.704 - 0.016ms returns 0 +T714C 001:712.721 JLINK_WriteReg(R10, 0x00000000) +T714C 001:712.737 - 0.016ms returns 0 +T714C 001:712.754 JLINK_WriteReg(R11, 0x00000000) +T714C 001:712.770 - 0.016ms returns 0 +T714C 001:712.787 JLINK_WriteReg(R12, 0x00000000) +T714C 001:712.804 - 0.016ms returns 0 +T714C 001:712.822 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:712.840 - 0.018ms returns 0 +T714C 001:712.856 JLINK_WriteReg(R14, 0x30500001) +T714C 001:712.872 - 0.016ms returns 0 +T714C 001:712.889 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:712.906 - 0.016ms returns 0 +T714C 001:712.923 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:712.939 - 0.016ms returns 0 +T714C 001:712.956 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:712.972 - 0.016ms returns 0 +T714C 001:712.989 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:713.006 - 0.016ms returns 0 +T714C 001:713.023 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:713.039 - 0.016ms returns 0 +T714C 001:713.057 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:713.075 - 0.018ms returns 0x0000003C +T714C 001:713.092 JLINK_Go() +T714C 001:713.112 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:713.466 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:715.819 - 2.726ms +T714C 001:715.964 JLINK_IsHalted() +T714C 001:716.278 - 0.313ms returns FALSE +T714C 001:716.366 JLINK_HasError() +T714C 001:719.687 JLINK_IsHalted() +T714C 001:722.146 - 2.457ms returns TRUE +T714C 001:722.232 JLINK_ReadReg(R15 (PC)) +T714C 001:722.275 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:722.659 - 0.426ms returns 0x30500000 +T714C 001:722.734 JLINK_ClrBPEx(BPHandle = 0x0000003C) +T714C 001:722.772 - 0.038ms returns 0x00 +T714C 001:722.808 JLINK_ReadReg(R0) +T714C 001:722.844 - 0.035ms returns 0x00000000 +T714C 001:724.765 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:724.873 Data: 17 1B 73 EB 05 07 05 D3 12 1B 63 EB 05 03 06 43 ... +T714C 001:724.935 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:726.062 - 1.297ms returns 0x100 +T714C 001:726.178 JLINK_HasError() +T714C 001:726.229 JLINK_WriteReg(R0, 0x2800BE00) +T714C 001:726.276 - 0.048ms returns 0 +T714C 001:726.314 JLINK_WriteReg(R1, 0x00000100) +T714C 001:726.354 - 0.040ms returns 0 +T714C 001:726.392 JLINK_WriteReg(R2, 0x30500674) +T714C 001:726.428 - 0.035ms returns 0 +T714C 001:726.464 JLINK_WriteReg(R3, 0x00000000) +T714C 001:726.501 - 0.036ms returns 0 +T714C 001:726.540 JLINK_WriteReg(R4, 0x00000000) +T714C 001:726.625 - 0.084ms returns 0 +T714C 001:726.648 JLINK_WriteReg(R5, 0x00000000) +T714C 001:726.665 - 0.017ms returns 0 +T714C 001:726.682 JLINK_WriteReg(R6, 0x00000000) +T714C 001:726.698 - 0.016ms returns 0 +T714C 001:726.715 JLINK_WriteReg(R7, 0x00000000) +T714C 001:726.732 - 0.017ms returns 0 +T714C 001:726.749 JLINK_WriteReg(R8, 0x00000000) +T714C 001:726.765 - 0.016ms returns 0 +T714C 001:726.782 JLINK_WriteReg(R9, 0x30500458) +T714C 001:726.798 - 0.016ms returns 0 +T714C 001:726.815 JLINK_WriteReg(R10, 0x00000000) +T714C 001:726.832 - 0.017ms returns 0 +T714C 001:726.849 JLINK_WriteReg(R11, 0x00000000) +T714C 001:726.865 - 0.016ms returns 0 +T714C 001:726.883 JLINK_WriteReg(R12, 0x00000000) +T714C 001:726.900 - 0.016ms returns 0 +T714C 001:726.917 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:726.935 - 0.018ms returns 0 +T714C 001:726.952 JLINK_WriteReg(R14, 0x30500001) +T714C 001:726.969 - 0.016ms returns 0 +T714C 001:726.986 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:727.002 - 0.016ms returns 0 +T714C 001:727.020 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:727.036 - 0.016ms returns 0 +T714C 001:727.052 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:727.068 - 0.016ms returns 0 +T714C 001:727.085 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:727.102 - 0.016ms returns 0 +T714C 001:727.124 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:727.144 - 0.020ms returns 0 +T714C 001:727.163 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:727.182 - 0.020ms returns 0x0000003D +T714C 001:727.203 JLINK_Go() +T714C 001:727.226 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:727.607 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:729.900 - 2.696ms +T714C 001:730.000 JLINK_IsHalted() +T714C 001:730.398 - 0.396ms returns FALSE +T714C 001:730.451 JLINK_HasError() +T714C 001:733.413 JLINK_IsHalted() +T714C 001:736.036 - 2.621ms returns TRUE +T714C 001:736.148 JLINK_ReadReg(R15 (PC)) +T714C 001:736.174 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:736.514 - 0.366ms returns 0x30500000 +T714C 001:736.593 JLINK_ClrBPEx(BPHandle = 0x0000003D) +T714C 001:736.630 - 0.036ms returns 0x00 +T714C 001:736.664 JLINK_ReadReg(R0) +T714C 001:736.700 - 0.035ms returns 0x00000000 +T714C 001:737.646 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:737.698 Data: E0 73 06 E0 41 FA 02 F3 D0 40 C2 F1 20 02 91 40 ... +T714C 001:737.734 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:738.809 - 1.162ms returns 0x100 +T714C 001:738.898 JLINK_HasError() +T714C 001:738.936 JLINK_WriteReg(R0, 0x2800BF00) +T714C 001:739.000 - 0.064ms returns 0 +T714C 001:739.036 JLINK_WriteReg(R1, 0x00000100) +T714C 001:739.070 - 0.034ms returns 0 +T714C 001:739.105 JLINK_WriteReg(R2, 0x30500674) +T714C 001:739.138 - 0.033ms returns 0 +T714C 001:739.172 JLINK_WriteReg(R3, 0x00000000) +T714C 001:739.214 - 0.041ms returns 0 +T714C 001:739.247 JLINK_WriteReg(R4, 0x00000000) +T714C 001:739.280 - 0.033ms returns 0 +T714C 001:739.313 JLINK_WriteReg(R5, 0x00000000) +T714C 001:739.346 - 0.032ms returns 0 +T714C 001:739.379 JLINK_WriteReg(R6, 0x00000000) +T714C 001:739.412 - 0.033ms returns 0 +T714C 001:739.448 JLINK_WriteReg(R7, 0x00000000) +T714C 001:739.482 - 0.034ms returns 0 +T714C 001:739.519 JLINK_WriteReg(R8, 0x00000000) +T714C 001:739.554 - 0.035ms returns 0 +T714C 001:739.589 JLINK_WriteReg(R9, 0x30500458) +T714C 001:739.623 - 0.034ms returns 0 +T714C 001:739.660 JLINK_WriteReg(R10, 0x00000000) +T714C 001:739.695 - 0.035ms returns 0 +T714C 001:739.731 JLINK_WriteReg(R11, 0x00000000) +T714C 001:739.766 - 0.034ms returns 0 +T714C 001:739.802 JLINK_WriteReg(R12, 0x00000000) +T714C 001:739.837 - 0.034ms returns 0 +T714C 001:739.871 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:739.908 - 0.036ms returns 0 +T714C 001:739.943 JLINK_WriteReg(R14, 0x30500001) +T714C 001:739.980 - 0.037ms returns 0 +T714C 001:740.015 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:740.050 - 0.035ms returns 0 +T714C 001:740.086 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:740.122 - 0.036ms returns 0 +T714C 001:740.158 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:740.194 - 0.036ms returns 0 +T714C 001:740.229 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:740.263 - 0.033ms returns 0 +T714C 001:740.297 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:740.331 - 0.034ms returns 0 +T714C 001:740.368 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:740.466 - 0.097ms returns 0x0000003E +T714C 001:740.488 JLINK_Go() +T714C 001:740.511 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:740.832 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:743.060 - 2.572ms +T714C 001:743.114 JLINK_IsHalted() +T714C 001:743.466 - 0.351ms returns FALSE +T714C 001:743.543 JLINK_HasError() +T714C 001:745.499 JLINK_IsHalted() +T714C 001:747.832 - 2.332ms returns TRUE +T714C 001:747.887 JLINK_ReadReg(R15 (PC)) +T714C 001:747.908 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:748.355 - 0.467ms returns 0x30500000 +T714C 001:748.456 JLINK_ClrBPEx(BPHandle = 0x0000003E) +T714C 001:748.478 - 0.022ms returns 0x00 +T714C 001:748.495 JLINK_ReadReg(R0) +T714C 001:748.524 - 0.028ms returns 0x00000000 +T714C 001:749.218 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:749.256 Data: 03 DD 09 F0 D1 FA 04 60 A0 07 BD E8 F0 87 46 F4 ... +T714C 001:749.287 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:750.338 - 1.119ms returns 0x100 +T714C 001:750.418 JLINK_HasError() +T714C 001:750.455 JLINK_WriteReg(R0, 0x2800C000) +T714C 001:750.505 - 0.050ms returns 0 +T714C 001:750.570 JLINK_WriteReg(R1, 0x00000100) +T714C 001:750.594 - 0.024ms returns 0 +T714C 001:750.612 JLINK_WriteReg(R2, 0x30500674) +T714C 001:750.628 - 0.016ms returns 0 +T714C 001:750.645 JLINK_WriteReg(R3, 0x00000000) +T714C 001:750.661 - 0.016ms returns 0 +T714C 001:750.678 JLINK_WriteReg(R4, 0x00000000) +T714C 001:750.694 - 0.016ms returns 0 +T714C 001:750.711 JLINK_WriteReg(R5, 0x00000000) +T714C 001:750.728 - 0.016ms returns 0 +T714C 001:750.745 JLINK_WriteReg(R6, 0x00000000) +T714C 001:750.761 - 0.016ms returns 0 +T714C 001:750.778 JLINK_WriteReg(R7, 0x00000000) +T714C 001:750.794 - 0.016ms returns 0 +T714C 001:750.812 JLINK_WriteReg(R8, 0x00000000) +T714C 001:750.828 - 0.016ms returns 0 +T714C 001:750.844 JLINK_WriteReg(R9, 0x30500458) +T714C 001:750.861 - 0.016ms returns 0 +T714C 001:750.877 JLINK_WriteReg(R10, 0x00000000) +T714C 001:750.893 - 0.016ms returns 0 +T714C 001:750.911 JLINK_WriteReg(R11, 0x00000000) +T714C 001:750.927 - 0.016ms returns 0 +T714C 001:750.986 JLINK_WriteReg(R12, 0x00000000) +T714C 001:751.002 - 0.016ms returns 0 +T714C 001:751.019 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:751.036 - 0.017ms returns 0 +T714C 001:751.053 JLINK_WriteReg(R14, 0x30500001) +T714C 001:751.069 - 0.016ms returns 0 +T714C 001:751.086 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:751.102 - 0.016ms returns 0 +T714C 001:751.119 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:751.135 - 0.016ms returns 0 +T714C 001:751.152 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:751.168 - 0.016ms returns 0 +T714C 001:751.186 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:751.202 - 0.016ms returns 0 +T714C 001:751.219 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:751.236 - 0.017ms returns 0 +T714C 001:751.253 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:751.271 - 0.019ms returns 0x0000003F +T714C 001:751.289 JLINK_Go() +T714C 001:751.309 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:751.689 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:753.830 - 2.540ms +T714C 001:753.967 JLINK_IsHalted() +T714C 001:754.290 - 0.322ms returns FALSE +T714C 001:754.470 JLINK_HasError() +T714C 001:756.571 JLINK_IsHalted() +T714C 001:758.912 - 2.339ms returns TRUE +T714C 001:758.960 JLINK_ReadReg(R15 (PC)) +T714C 001:758.983 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:759.234 - 0.273ms returns 0x30500000 +T714C 001:759.258 JLINK_ClrBPEx(BPHandle = 0x0000003F) +T714C 001:759.276 - 0.018ms returns 0x00 +T714C 001:759.295 JLINK_ReadReg(R0) +T714C 001:759.313 - 0.017ms returns 0x00000000 +T714C 001:759.986 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:760.035 Data: F6 D3 FF F7 81 F9 00 00 30 74 01 28 60 74 01 28 ... +T714C 001:760.066 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:761.074 - 1.087ms returns 0x100 +T714C 001:761.100 JLINK_HasError() +T714C 001:761.120 JLINK_WriteReg(R0, 0x2800C100) +T714C 001:761.140 - 0.020ms returns 0 +T714C 001:761.157 JLINK_WriteReg(R1, 0x00000100) +T714C 001:761.174 - 0.016ms returns 0 +T714C 001:761.190 JLINK_WriteReg(R2, 0x30500674) +T714C 001:761.207 - 0.017ms returns 0 +T714C 001:761.224 JLINK_WriteReg(R3, 0x00000000) +T714C 001:761.240 - 0.015ms returns 0 +T714C 001:761.257 JLINK_WriteReg(R4, 0x00000000) +T714C 001:761.273 - 0.016ms returns 0 +T714C 001:761.289 JLINK_WriteReg(R5, 0x00000000) +T714C 001:761.305 - 0.016ms returns 0 +T714C 001:761.321 JLINK_WriteReg(R6, 0x00000000) +T714C 001:761.338 - 0.016ms returns 0 +T714C 001:761.354 JLINK_WriteReg(R7, 0x00000000) +T714C 001:761.370 - 0.016ms returns 0 +T714C 001:761.386 JLINK_WriteReg(R8, 0x00000000) +T714C 001:761.402 - 0.016ms returns 0 +T714C 001:761.418 JLINK_WriteReg(R9, 0x30500458) +T714C 001:761.435 - 0.016ms returns 0 +T714C 001:761.452 JLINK_WriteReg(R10, 0x00000000) +T714C 001:761.468 - 0.016ms returns 0 +T714C 001:761.485 JLINK_WriteReg(R11, 0x00000000) +T714C 001:761.501 - 0.016ms returns 0 +T714C 001:761.518 JLINK_WriteReg(R12, 0x00000000) +T714C 001:761.533 - 0.015ms returns 0 +T714C 001:761.549 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:761.571 - 0.021ms returns 0 +T714C 001:761.588 JLINK_WriteReg(R14, 0x30500001) +T714C 001:761.604 - 0.015ms returns 0 +T714C 001:761.620 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:761.636 - 0.016ms returns 0 +T714C 001:761.653 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:761.668 - 0.016ms returns 0 +T714C 001:761.686 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:761.701 - 0.015ms returns 0 +T714C 001:761.718 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:761.733 - 0.015ms returns 0 +T714C 001:761.750 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:761.766 - 0.015ms returns 0 +T714C 001:761.782 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:761.799 - 0.017ms returns 0x00000040 +T714C 001:761.815 JLINK_Go() +T714C 001:761.833 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:762.194 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:764.495 - 2.679ms +T714C 001:764.588 JLINK_IsHalted() +T714C 001:764.952 - 0.363ms returns FALSE +T714C 001:765.050 JLINK_HasError() +T714C 001:766.574 JLINK_IsHalted() +T714C 001:769.104 - 2.529ms returns TRUE +T714C 001:769.227 JLINK_ReadReg(R15 (PC)) +T714C 001:769.274 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:769.644 - 0.416ms returns 0x30500000 +T714C 001:769.726 JLINK_ClrBPEx(BPHandle = 0x00000040) +T714C 001:769.766 - 0.040ms returns 0x00 +T714C 001:769.806 JLINK_ReadReg(R0) +T714C 001:769.844 - 0.037ms returns 0x00000000 +T714C 001:771.024 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:771.099 Data: 00 21 1B 22 00 F0 60 FD 02 20 01 21 10 22 4F F0 ... +T714C 001:771.161 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:772.252 - 1.227ms returns 0x100 +T714C 001:772.328 JLINK_HasError() +T714C 001:772.368 JLINK_WriteReg(R0, 0x2800C200) +T714C 001:772.415 - 0.047ms returns 0 +T714C 001:772.449 JLINK_WriteReg(R1, 0x00000100) +T714C 001:772.532 - 0.082ms returns 0 +T714C 001:772.564 JLINK_WriteReg(R2, 0x30500674) +T714C 001:772.582 - 0.019ms returns 0 +T714C 001:772.600 JLINK_WriteReg(R3, 0x00000000) +T714C 001:772.616 - 0.016ms returns 0 +T714C 001:772.633 JLINK_WriteReg(R4, 0x00000000) +T714C 001:772.650 - 0.016ms returns 0 +T714C 001:772.668 JLINK_WriteReg(R5, 0x00000000) +T714C 001:772.684 - 0.017ms returns 0 +T714C 001:772.701 JLINK_WriteReg(R6, 0x00000000) +T714C 001:772.718 - 0.016ms returns 0 +T714C 001:772.734 JLINK_WriteReg(R7, 0x00000000) +T714C 001:772.750 - 0.015ms returns 0 +T714C 001:772.766 JLINK_WriteReg(R8, 0x00000000) +T714C 001:772.782 - 0.015ms returns 0 +T714C 001:772.798 JLINK_WriteReg(R9, 0x30500458) +T714C 001:772.815 - 0.016ms returns 0 +T714C 001:772.832 JLINK_WriteReg(R10, 0x00000000) +T714C 001:772.852 - 0.019ms returns 0 +T714C 001:772.869 JLINK_WriteReg(R11, 0x00000000) +T714C 001:772.885 - 0.016ms returns 0 +T714C 001:772.902 JLINK_WriteReg(R12, 0x00000000) +T714C 001:772.918 - 0.016ms returns 0 +T714C 001:772.934 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:772.952 - 0.017ms returns 0 +T714C 001:772.968 JLINK_WriteReg(R14, 0x30500001) +T714C 001:772.984 - 0.015ms returns 0 +T714C 001:773.000 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:773.017 - 0.016ms returns 0 +T714C 001:773.033 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:773.050 - 0.016ms returns 0 +T714C 001:773.066 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:773.082 - 0.016ms returns 0 +T714C 001:773.100 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:773.117 - 0.017ms returns 0 +T714C 001:773.134 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:773.151 - 0.016ms returns 0 +T714C 001:773.169 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:773.187 - 0.018ms returns 0x00000041 +T714C 001:773.204 JLINK_Go() +T714C 001:773.224 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:773.622 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:775.782 - 2.577ms +T714C 001:775.865 JLINK_IsHalted() +T714C 001:776.245 - 0.379ms returns FALSE +T714C 001:776.307 JLINK_HasError() +T714C 001:777.549 JLINK_IsHalted() +T714C 001:780.098 - 2.548ms returns TRUE +T714C 001:780.153 JLINK_ReadReg(R15 (PC)) +T714C 001:780.175 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:780.623 - 0.469ms returns 0x30500000 +T714C 001:780.674 JLINK_ClrBPEx(BPHandle = 0x00000041) +T714C 001:780.693 - 0.019ms returns 0x00 +T714C 001:780.711 JLINK_ReadReg(R0) +T714C 001:780.728 - 0.018ms returns 0x00000000 +T714C 001:781.611 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:781.659 Data: 4F 8F BF F3 6F 8F D4 F8 00 05 C4 F8 80 55 BF F3 ... +T714C 001:781.696 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:782.802 - 1.190ms returns 0x100 +T714C 001:782.881 JLINK_HasError() +T714C 001:782.919 JLINK_WriteReg(R0, 0x2800C300) +T714C 001:782.958 - 0.039ms returns 0 +T714C 001:782.993 JLINK_WriteReg(R1, 0x00000100) +T714C 001:783.026 - 0.033ms returns 0 +T714C 001:783.059 JLINK_WriteReg(R2, 0x30500674) +T714C 001:783.092 - 0.032ms returns 0 +T714C 001:783.125 JLINK_WriteReg(R3, 0x00000000) +T714C 001:783.157 - 0.032ms returns 0 +T714C 001:783.190 JLINK_WriteReg(R4, 0x00000000) +T714C 001:783.223 - 0.033ms returns 0 +T714C 001:783.257 JLINK_WriteReg(R5, 0x00000000) +T714C 001:783.297 - 0.040ms returns 0 +T714C 001:783.381 JLINK_WriteReg(R6, 0x00000000) +T714C 001:783.410 - 0.029ms returns 0 +T714C 001:783.427 JLINK_WriteReg(R7, 0x00000000) +T714C 001:783.445 - 0.017ms returns 0 +T714C 001:783.462 JLINK_WriteReg(R8, 0x00000000) +T714C 001:783.479 - 0.017ms returns 0 +T714C 001:783.497 JLINK_WriteReg(R9, 0x30500458) +T714C 001:783.513 - 0.016ms returns 0 +T714C 001:783.530 JLINK_WriteReg(R10, 0x00000000) +T714C 001:783.547 - 0.016ms returns 0 +T714C 001:783.629 JLINK_WriteReg(R11, 0x00000000) +T714C 001:783.654 - 0.024ms returns 0 +T714C 001:783.677 JLINK_WriteReg(R12, 0x00000000) +T714C 001:783.693 - 0.016ms returns 0 +T714C 001:783.720 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:783.739 - 0.019ms returns 0 +T714C 001:783.756 JLINK_WriteReg(R14, 0x30500001) +T714C 001:783.773 - 0.016ms returns 0 +T714C 001:783.790 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:783.806 - 0.016ms returns 0 +T714C 001:783.824 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:783.844 - 0.019ms returns 0 +T714C 001:783.861 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:783.878 - 0.017ms returns 0 +T714C 001:783.894 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:783.911 - 0.016ms returns 0 +T714C 001:783.928 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:783.944 - 0.016ms returns 0 +T714C 001:783.961 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:783.982 - 0.020ms returns 0x00000042 +T714C 001:783.999 JLINK_Go() +T714C 001:784.020 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:784.420 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:786.658 - 2.657ms +T714C 001:786.740 JLINK_IsHalted() +T714C 001:787.038 - 0.297ms returns FALSE +T714C 001:787.122 JLINK_HasError() +T714C 001:788.493 JLINK_IsHalted() +T714C 001:790.877 - 2.384ms returns TRUE +T714C 001:790.934 JLINK_ReadReg(R15 (PC)) +T714C 001:790.956 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:791.258 - 0.323ms returns 0x30500000 +T714C 001:791.281 JLINK_ClrBPEx(BPHandle = 0x00000042) +T714C 001:791.298 - 0.017ms returns 0x00 +T714C 001:791.315 JLINK_ReadReg(R0) +T714C 001:791.332 - 0.016ms returns 0x00000000 +T714C 001:791.957 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:791.990 Data: 09 20 C4 F8 00 0D BF F3 4F 8F BF F3 6F 8F D4 F8 ... +T714C 001:792.021 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:793.060 - 1.103ms returns 0x100 +T714C 001:793.088 JLINK_HasError() +T714C 001:793.106 JLINK_WriteReg(R0, 0x2800C400) +T714C 001:793.124 - 0.018ms returns 0 +T714C 001:793.140 JLINK_WriteReg(R1, 0x00000100) +T714C 001:793.157 - 0.016ms returns 0 +T714C 001:793.174 JLINK_WriteReg(R2, 0x30500674) +T714C 001:793.191 - 0.016ms returns 0 +T714C 001:793.207 JLINK_WriteReg(R3, 0x00000000) +T714C 001:793.223 - 0.016ms returns 0 +T714C 001:793.239 JLINK_WriteReg(R4, 0x00000000) +T714C 001:793.255 - 0.016ms returns 0 +T714C 001:793.272 JLINK_WriteReg(R5, 0x00000000) +T714C 001:793.288 - 0.016ms returns 0 +T714C 001:793.305 JLINK_WriteReg(R6, 0x00000000) +T714C 001:793.321 - 0.015ms returns 0 +T714C 001:793.337 JLINK_WriteReg(R7, 0x00000000) +T714C 001:793.352 - 0.016ms returns 0 +T714C 001:793.369 JLINK_WriteReg(R8, 0x00000000) +T714C 001:793.391 - 0.022ms returns 0 +T714C 001:793.408 JLINK_WriteReg(R9, 0x30500458) +T714C 001:793.423 - 0.015ms returns 0 +T714C 001:793.439 JLINK_WriteReg(R10, 0x00000000) +T714C 001:793.456 - 0.016ms returns 0 +T714C 001:793.472 JLINK_WriteReg(R11, 0x00000000) +T714C 001:793.488 - 0.016ms returns 0 +T714C 001:793.504 JLINK_WriteReg(R12, 0x00000000) +T714C 001:793.520 - 0.016ms returns 0 +T714C 001:793.542 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:793.559 - 0.017ms returns 0 +T714C 001:793.576 JLINK_WriteReg(R14, 0x30500001) +T714C 001:793.592 - 0.015ms returns 0 +T714C 001:793.608 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:793.624 - 0.015ms returns 0 +T714C 001:793.640 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:793.657 - 0.016ms returns 0 +T714C 001:793.675 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:793.695 - 0.019ms returns 0 +T714C 001:793.711 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:793.727 - 0.016ms returns 0 +T714C 001:793.744 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:793.760 - 0.016ms returns 0 +T714C 001:793.777 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:793.794 - 0.017ms returns 0x00000043 +T714C 001:793.811 JLINK_Go() +T714C 001:793.830 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:794.114 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:796.118 - 2.306ms +T714C 001:796.157 JLINK_IsHalted() +T714C 001:796.469 - 0.312ms returns FALSE +T714C 001:796.495 JLINK_HasError() +T714C 001:798.491 JLINK_IsHalted() +T714C 001:800.912 - 2.419ms returns TRUE +T714C 001:800.983 JLINK_ReadReg(R15 (PC)) +T714C 001:801.006 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:801.289 - 0.306ms returns 0x30500000 +T714C 001:801.314 JLINK_ClrBPEx(BPHandle = 0x00000043) +T714C 001:801.332 - 0.017ms returns 0x00 +T714C 001:801.349 JLINK_ReadReg(R0) +T714C 001:801.367 - 0.018ms returns 0x00000000 +T714C 001:802.023 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:802.061 Data: 6F 8F D1 F8 80 24 C1 F8 00 95 BF F3 4F 8F BF F3 ... +T714C 001:802.094 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:803.065 - 1.042ms returns 0x100 +T714C 001:803.106 JLINK_HasError() +T714C 001:803.125 JLINK_WriteReg(R0, 0x2800C500) +T714C 001:803.190 - 0.064ms returns 0 +T714C 001:803.208 JLINK_WriteReg(R1, 0x00000100) +T714C 001:803.225 - 0.017ms returns 0 +T714C 001:803.242 JLINK_WriteReg(R2, 0x30500674) +T714C 001:803.258 - 0.016ms returns 0 +T714C 001:803.276 JLINK_WriteReg(R3, 0x00000000) +T714C 001:803.292 - 0.016ms returns 0 +T714C 001:803.308 JLINK_WriteReg(R4, 0x00000000) +T714C 001:803.324 - 0.016ms returns 0 +T714C 001:803.340 JLINK_WriteReg(R5, 0x00000000) +T714C 001:803.356 - 0.016ms returns 0 +T714C 001:803.380 JLINK_WriteReg(R6, 0x00000000) +T714C 001:803.396 - 0.015ms returns 0 +T714C 001:803.412 JLINK_WriteReg(R7, 0x00000000) +T714C 001:803.428 - 0.016ms returns 0 +T714C 001:803.444 JLINK_WriteReg(R8, 0x00000000) +T714C 001:803.460 - 0.015ms returns 0 +T714C 001:803.476 JLINK_WriteReg(R9, 0x30500458) +T714C 001:803.493 - 0.016ms returns 0 +T714C 001:803.509 JLINK_WriteReg(R10, 0x00000000) +T714C 001:803.525 - 0.016ms returns 0 +T714C 001:803.542 JLINK_WriteReg(R11, 0x00000000) +T714C 001:803.571 - 0.028ms returns 0 +T714C 001:803.588 JLINK_WriteReg(R12, 0x00000000) +T714C 001:803.603 - 0.015ms returns 0 +T714C 001:803.620 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:803.637 - 0.017ms returns 0 +T714C 001:803.653 JLINK_WriteReg(R14, 0x30500001) +T714C 001:803.672 - 0.018ms returns 0 +T714C 001:803.695 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:803.711 - 0.024ms returns 0 +T714C 001:803.728 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:803.834 - 0.106ms returns 0 +T714C 001:803.851 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:803.867 - 0.016ms returns 0 +T714C 001:803.884 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:803.900 - 0.016ms returns 0 +T714C 001:803.916 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:803.934 - 0.017ms returns 0 +T714C 001:803.966 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:803.982 - 0.017ms returns 0x00000044 +T714C 001:804.004 JLINK_Go() +T714C 001:804.025 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:804.330 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:806.420 - 2.416ms +T714C 001:806.500 JLINK_IsHalted() +T714C 001:806.785 - 0.284ms returns FALSE +T714C 001:806.859 JLINK_HasError() +T714C 001:808.534 JLINK_IsHalted() +T714C 001:810.828 - 2.292ms returns TRUE +T714C 001:810.916 JLINK_ReadReg(R15 (PC)) +T714C 001:810.940 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:811.294 - 0.377ms returns 0x30500000 +T714C 001:811.342 JLINK_ClrBPEx(BPHandle = 0x00000044) +T714C 001:811.360 - 0.018ms returns 0x00 +T714C 001:811.377 JLINK_ReadReg(R0) +T714C 001:811.395 - 0.017ms returns 0x00000000 +T714C 001:812.288 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:812.332 Data: 00 11 BF F3 4F 8F BF F3 6F 8F D0 F8 00 21 C0 F8 ... +T714C 001:812.370 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:813.373 - 1.085ms returns 0x100 +T714C 001:813.415 JLINK_HasError() +T714C 001:813.468 JLINK_WriteReg(R0, 0x2800C600) +T714C 001:813.489 - 0.020ms returns 0 +T714C 001:813.506 JLINK_WriteReg(R1, 0x00000100) +T714C 001:813.522 - 0.016ms returns 0 +T714C 001:813.539 JLINK_WriteReg(R2, 0x30500674) +T714C 001:813.556 - 0.016ms returns 0 +T714C 001:813.627 JLINK_WriteReg(R3, 0x00000000) +T714C 001:813.704 - 0.076ms returns 0 +T714C 001:813.756 JLINK_WriteReg(R4, 0x00000000) +T714C 001:813.779 - 0.023ms returns 0 +T714C 001:813.805 JLINK_WriteReg(R5, 0x00000000) +T714C 001:813.828 - 0.023ms returns 0 +T714C 001:813.852 JLINK_WriteReg(R6, 0x00000000) +T714C 001:813.876 - 0.023ms returns 0 +T714C 001:813.899 JLINK_WriteReg(R7, 0x00000000) +T714C 001:813.922 - 0.023ms returns 0 +T714C 001:813.944 JLINK_WriteReg(R8, 0x00000000) +T714C 001:813.972 - 0.028ms returns 0 +T714C 001:813.996 JLINK_WriteReg(R9, 0x30500458) +T714C 001:814.015 - 0.019ms returns 0 +T714C 001:814.032 JLINK_WriteReg(R10, 0x00000000) +T714C 001:814.050 - 0.017ms returns 0 +T714C 001:814.066 JLINK_WriteReg(R11, 0x00000000) +T714C 001:814.082 - 0.016ms returns 0 +T714C 001:814.100 JLINK_WriteReg(R12, 0x00000000) +T714C 001:814.118 - 0.017ms returns 0 +T714C 001:814.141 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:814.160 - 0.018ms returns 0 +T714C 001:814.176 JLINK_WriteReg(R14, 0x30500001) +T714C 001:814.193 - 0.016ms returns 0 +T714C 001:814.210 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:814.226 - 0.016ms returns 0 +T714C 001:814.243 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:814.259 - 0.016ms returns 0 +T714C 001:814.276 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:814.292 - 0.015ms returns 0 +T714C 001:814.309 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:814.324 - 0.015ms returns 0 +T714C 001:814.340 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:814.356 - 0.015ms returns 0 +T714C 001:814.374 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:814.391 - 0.017ms returns 0x00000045 +T714C 001:814.407 JLINK_Go() +T714C 001:814.426 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:814.754 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:817.026 - 2.617ms +T714C 001:817.092 JLINK_IsHalted() +T714C 001:817.448 - 0.352ms returns FALSE +T714C 001:817.483 JLINK_HasError() +T714C 001:818.768 JLINK_IsHalted() +T714C 001:821.222 - 2.456ms returns TRUE +T714C 001:821.246 JLINK_ReadReg(R15 (PC)) +T714C 001:821.264 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:821.574 - 0.327ms returns 0x30500000 +T714C 001:821.618 JLINK_ClrBPEx(BPHandle = 0x00000045) +T714C 001:821.634 - 0.019ms returns 0x00 +T714C 001:821.651 JLINK_ReadReg(R0) +T714C 001:821.672 - 0.020ms returns 0x00000000 +T714C 001:822.324 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:822.359 Data: B0 FB F1 F0 40 F2 04 01 C2 F2 00 01 08 60 BD E8 ... +T714C 001:822.393 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:823.507 - 1.182ms returns 0x100 +T714C 001:823.541 JLINK_HasError() +T714C 001:823.562 JLINK_WriteReg(R0, 0x2800C700) +T714C 001:823.581 - 0.019ms returns 0 +T714C 001:823.600 JLINK_WriteReg(R1, 0x00000100) +T714C 001:823.617 - 0.017ms returns 0 +T714C 001:823.636 JLINK_WriteReg(R2, 0x30500674) +T714C 001:823.659 - 0.023ms returns 0 +T714C 001:823.680 JLINK_WriteReg(R3, 0x00000000) +T714C 001:823.698 - 0.017ms returns 0 +T714C 001:823.716 JLINK_WriteReg(R4, 0x00000000) +T714C 001:823.734 - 0.017ms returns 0 +T714C 001:823.752 JLINK_WriteReg(R5, 0x00000000) +T714C 001:823.769 - 0.017ms returns 0 +T714C 001:823.788 JLINK_WriteReg(R6, 0x00000000) +T714C 001:823.804 - 0.016ms returns 0 +T714C 001:823.823 JLINK_WriteReg(R7, 0x00000000) +T714C 001:823.839 - 0.016ms returns 0 +T714C 001:823.859 JLINK_WriteReg(R8, 0x00000000) +T714C 001:823.876 - 0.018ms returns 0 +T714C 001:823.895 JLINK_WriteReg(R9, 0x30500458) +T714C 001:823.912 - 0.016ms returns 0 +T714C 001:823.930 JLINK_WriteReg(R10, 0x00000000) +T714C 001:823.947 - 0.017ms returns 0 +T714C 001:823.965 JLINK_WriteReg(R11, 0x00000000) +T714C 001:823.982 - 0.016ms returns 0 +T714C 001:824.000 JLINK_WriteReg(R12, 0x00000000) +T714C 001:824.017 - 0.017ms returns 0 +T714C 001:824.035 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:824.053 - 0.018ms returns 0 +T714C 001:824.071 JLINK_WriteReg(R14, 0x30500001) +T714C 001:824.088 - 0.017ms returns 0 +T714C 001:824.107 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:824.124 - 0.017ms returns 0 +T714C 001:824.142 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:824.159 - 0.017ms returns 0 +T714C 001:824.177 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:824.194 - 0.017ms returns 0 +T714C 001:824.212 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:824.229 - 0.017ms returns 0 +T714C 001:824.247 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:824.264 - 0.017ms returns 0 +T714C 001:824.282 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:824.300 - 0.018ms returns 0x00000046 +T714C 001:824.318 JLINK_Go() +T714C 001:824.338 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:824.611 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:826.580 - 2.261ms +T714C 001:826.607 JLINK_IsHalted() +T714C 001:826.835 - 0.228ms returns FALSE +T714C 001:826.858 JLINK_HasError() +T714C 001:828.292 JLINK_IsHalted() +T714C 001:830.638 - 2.344ms returns TRUE +T714C 001:830.696 JLINK_ReadReg(R15 (PC)) +T714C 001:830.718 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:830.958 - 0.262ms returns 0x30500000 +T714C 001:830.981 JLINK_ClrBPEx(BPHandle = 0x00000046) +T714C 001:830.997 - 0.016ms returns 0x00 +T714C 001:831.015 JLINK_ReadReg(R0) +T714C 001:831.032 - 0.017ms returns 0x00000000 +T714C 001:831.607 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:831.652 Data: C7 F6 FF 70 B0 60 40 F2 00 00 40 F2 00 01 C2 F2 ... +T714C 001:831.687 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:832.639 - 1.033ms returns 0x100 +T714C 001:832.696 JLINK_HasError() +T714C 001:832.716 JLINK_WriteReg(R0, 0x2800C800) +T714C 001:832.738 - 0.022ms returns 0 +T714C 001:832.754 JLINK_WriteReg(R1, 0x00000100) +T714C 001:832.771 - 0.016ms returns 0 +T714C 001:832.787 JLINK_WriteReg(R2, 0x30500674) +T714C 001:832.804 - 0.016ms returns 0 +T714C 001:832.820 JLINK_WriteReg(R3, 0x00000000) +T714C 001:832.836 - 0.016ms returns 0 +T714C 001:832.853 JLINK_WriteReg(R4, 0x00000000) +T714C 001:832.869 - 0.016ms returns 0 +T714C 001:832.886 JLINK_WriteReg(R5, 0x00000000) +T714C 001:832.902 - 0.016ms returns 0 +T714C 001:832.919 JLINK_WriteReg(R6, 0x00000000) +T714C 001:832.935 - 0.016ms returns 0 +T714C 001:832.952 JLINK_WriteReg(R7, 0x00000000) +T714C 001:832.968 - 0.015ms returns 0 +T714C 001:832.984 JLINK_WriteReg(R8, 0x00000000) +T714C 001:833.001 - 0.017ms returns 0 +T714C 001:833.023 JLINK_WriteReg(R9, 0x30500458) +T714C 001:833.040 - 0.016ms returns 0 +T714C 001:833.056 JLINK_WriteReg(R10, 0x00000000) +T714C 001:833.073 - 0.016ms returns 0 +T714C 001:833.090 JLINK_WriteReg(R11, 0x00000000) +T714C 001:833.108 - 0.018ms returns 0 +T714C 001:833.125 JLINK_WriteReg(R12, 0x00000000) +T714C 001:833.141 - 0.016ms returns 0 +T714C 001:833.158 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:833.176 - 0.018ms returns 0 +T714C 001:833.194 JLINK_WriteReg(R14, 0x30500001) +T714C 001:833.245 - 0.051ms returns 0 +T714C 001:833.264 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:833.280 - 0.016ms returns 0 +T714C 001:833.302 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:833.320 - 0.018ms returns 0 +T714C 001:833.336 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:833.352 - 0.015ms returns 0 +T714C 001:833.368 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:833.385 - 0.016ms returns 0 +T714C 001:833.402 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:833.418 - 0.016ms returns 0 +T714C 001:833.436 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:833.453 - 0.017ms returns 0x00000047 +T714C 001:833.470 JLINK_Go() +T714C 001:833.488 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:833.759 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:835.754 - 2.284ms +T714C 001:835.784 JLINK_IsHalted() +T714C 001:836.026 - 0.241ms returns FALSE +T714C 001:836.047 JLINK_HasError() +T714C 001:838.390 JLINK_IsHalted() +T714C 001:840.654 - 2.263ms returns TRUE +T714C 001:840.680 JLINK_ReadReg(R15 (PC)) +T714C 001:840.699 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:840.904 - 0.224ms returns 0x30500000 +T714C 001:840.924 JLINK_ClrBPEx(BPHandle = 0x00000047) +T714C 001:840.941 - 0.016ms returns 0x00 +T714C 001:840.958 JLINK_ReadReg(R0) +T714C 001:840.974 - 0.016ms returns 0x00000000 +T714C 001:841.473 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:841.504 Data: 48 F6 C0 20 C4 F2 45 40 01 68 C9 07 06 D1 01 21 ... +T714C 001:841.535 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:842.600 - 1.126ms returns 0x100 +T714C 001:842.624 JLINK_HasError() +T714C 001:842.643 JLINK_WriteReg(R0, 0x2800C900) +T714C 001:842.661 - 0.018ms returns 0 +T714C 001:842.678 JLINK_WriteReg(R1, 0x00000100) +T714C 001:842.694 - 0.016ms returns 0 +T714C 001:842.711 JLINK_WriteReg(R2, 0x30500674) +T714C 001:842.727 - 0.015ms returns 0 +T714C 001:842.743 JLINK_WriteReg(R3, 0x00000000) +T714C 001:842.761 - 0.017ms returns 0 +T714C 001:842.777 JLINK_WriteReg(R4, 0x00000000) +T714C 001:842.793 - 0.015ms returns 0 +T714C 001:842.809 JLINK_WriteReg(R5, 0x00000000) +T714C 001:842.826 - 0.016ms returns 0 +T714C 001:842.842 JLINK_WriteReg(R6, 0x00000000) +T714C 001:842.864 - 0.021ms returns 0 +T714C 001:842.881 JLINK_WriteReg(R7, 0x00000000) +T714C 001:842.897 - 0.016ms returns 0 +T714C 001:842.914 JLINK_WriteReg(R8, 0x00000000) +T714C 001:842.929 - 0.015ms returns 0 +T714C 001:842.946 JLINK_WriteReg(R9, 0x30500458) +T714C 001:842.962 - 0.016ms returns 0 +T714C 001:842.978 JLINK_WriteReg(R10, 0x00000000) +T714C 001:842.994 - 0.015ms returns 0 +T714C 001:843.010 JLINK_WriteReg(R11, 0x00000000) +T714C 001:843.026 - 0.015ms returns 0 +T714C 001:843.042 JLINK_WriteReg(R12, 0x00000000) +T714C 001:843.058 - 0.015ms returns 0 +T714C 001:843.074 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:843.091 - 0.016ms returns 0 +T714C 001:843.107 JLINK_WriteReg(R14, 0x30500001) +T714C 001:843.122 - 0.015ms returns 0 +T714C 001:843.139 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:843.154 - 0.015ms returns 0 +T714C 001:843.171 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:843.187 - 0.016ms returns 0 +T714C 001:843.203 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:843.220 - 0.016ms returns 0 +T714C 001:843.236 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:843.252 - 0.016ms returns 0 +T714C 001:843.268 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:843.284 - 0.016ms returns 0 +T714C 001:843.301 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:843.318 - 0.017ms returns 0x00000048 +T714C 001:843.334 JLINK_Go() +T714C 001:843.352 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:843.716 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:845.812 - 2.477ms +T714C 001:845.851 JLINK_IsHalted() +T714C 001:846.098 - 0.247ms returns FALSE +T714C 001:846.119 JLINK_HasError() +T714C 001:847.421 JLINK_IsHalted() +T714C 001:849.587 - 2.165ms returns TRUE +T714C 001:849.631 JLINK_ReadReg(R15 (PC)) +T714C 001:849.651 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:849.905 - 0.274ms returns 0x30500000 +T714C 001:849.926 JLINK_ClrBPEx(BPHandle = 0x00000048) +T714C 001:849.943 - 0.016ms returns 0x00 +T714C 001:849.961 JLINK_ReadReg(R0) +T714C 001:849.977 - 0.016ms returns 0x00000000 +T714C 001:850.554 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:850.601 Data: C0 F2 5B 02 C9 B2 22 FA 00 F0 00 FB 01 F0 BD E8 ... +T714C 001:850.632 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:851.684 - 1.130ms returns 0x100 +T714C 001:851.707 JLINK_HasError() +T714C 001:851.725 JLINK_WriteReg(R0, 0x2800CA00) +T714C 001:851.743 - 0.018ms returns 0 +T714C 001:851.759 JLINK_WriteReg(R1, 0x00000100) +T714C 001:851.775 - 0.015ms returns 0 +T714C 001:851.792 JLINK_WriteReg(R2, 0x30500674) +T714C 001:851.807 - 0.015ms returns 0 +T714C 001:851.824 JLINK_WriteReg(R3, 0x00000000) +T714C 001:851.839 - 0.015ms returns 0 +T714C 001:851.886 JLINK_WriteReg(R4, 0x00000000) +T714C 001:851.902 - 0.016ms returns 0 +T714C 001:851.918 JLINK_WriteReg(R5, 0x00000000) +T714C 001:851.934 - 0.015ms returns 0 +T714C 001:851.950 JLINK_WriteReg(R6, 0x00000000) +T714C 001:851.965 - 0.015ms returns 0 +T714C 001:851.981 JLINK_WriteReg(R7, 0x00000000) +T714C 001:851.997 - 0.015ms returns 0 +T714C 001:852.014 JLINK_WriteReg(R8, 0x00000000) +T714C 001:852.029 - 0.015ms returns 0 +T714C 001:852.045 JLINK_WriteReg(R9, 0x30500458) +T714C 001:852.061 - 0.015ms returns 0 +T714C 001:852.077 JLINK_WriteReg(R10, 0x00000000) +T714C 001:852.094 - 0.016ms returns 0 +T714C 001:852.110 JLINK_WriteReg(R11, 0x00000000) +T714C 001:852.126 - 0.016ms returns 0 +T714C 001:852.142 JLINK_WriteReg(R12, 0x00000000) +T714C 001:852.158 - 0.015ms returns 0 +T714C 001:852.174 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:852.191 - 0.016ms returns 0 +T714C 001:852.207 JLINK_WriteReg(R14, 0x30500001) +T714C 001:852.222 - 0.015ms returns 0 +T714C 001:852.238 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:852.254 - 0.015ms returns 0 +T714C 001:852.270 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:852.287 - 0.016ms returns 0 +T714C 001:852.302 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:852.318 - 0.015ms returns 0 +T714C 001:852.334 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:852.350 - 0.015ms returns 0 +T714C 001:852.371 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:852.388 - 0.017ms returns 0 +T714C 001:852.407 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:852.424 - 0.017ms returns 0x00000049 +T714C 001:852.442 JLINK_Go() +T714C 001:852.461 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:852.716 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:854.605 - 2.162ms +T714C 001:854.633 JLINK_IsHalted() +T714C 001:854.868 - 0.235ms returns FALSE +T714C 001:854.893 JLINK_HasError() +T714C 001:856.446 JLINK_IsHalted() +T714C 001:858.617 - 2.169ms returns TRUE +T714C 001:858.652 JLINK_ReadReg(R15 (PC)) +T714C 001:858.672 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:858.905 - 0.253ms returns 0x30500000 +T714C 001:858.926 JLINK_ClrBPEx(BPHandle = 0x00000049) +T714C 001:858.942 - 0.016ms returns 0x00 +T714C 001:858.960 JLINK_ReadReg(R0) +T714C 001:858.976 - 0.016ms returns 0x00000000 +T714C 001:859.475 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:859.506 Data: F0 87 44 F2 00 00 C4 F2 48 40 00 6B C0 F3 05 44 ... +T714C 001:859.536 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:860.586 - 1.110ms returns 0x100 +T714C 001:860.609 JLINK_HasError() +T714C 001:860.626 JLINK_WriteReg(R0, 0x2800CB00) +T714C 001:860.644 - 0.018ms returns 0 +T714C 001:860.660 JLINK_WriteReg(R1, 0x00000100) +T714C 001:860.677 - 0.016ms returns 0 +T714C 001:860.693 JLINK_WriteReg(R2, 0x30500674) +T714C 001:860.709 - 0.016ms returns 0 +T714C 001:860.726 JLINK_WriteReg(R3, 0x00000000) +T714C 001:860.742 - 0.016ms returns 0 +T714C 001:860.758 JLINK_WriteReg(R4, 0x00000000) +T714C 001:860.776 - 0.017ms returns 0 +T714C 001:860.792 JLINK_WriteReg(R5, 0x00000000) +T714C 001:860.807 - 0.015ms returns 0 +T714C 001:860.823 JLINK_WriteReg(R6, 0x00000000) +T714C 001:860.839 - 0.015ms returns 0 +T714C 001:860.855 JLINK_WriteReg(R7, 0x00000000) +T714C 001:860.872 - 0.016ms returns 0 +T714C 001:860.888 JLINK_WriteReg(R8, 0x00000000) +T714C 001:860.903 - 0.015ms returns 0 +T714C 001:860.919 JLINK_WriteReg(R9, 0x30500458) +T714C 001:860.935 - 0.015ms returns 0 +T714C 001:860.951 JLINK_WriteReg(R10, 0x00000000) +T714C 001:860.971 - 0.020ms returns 0 +T714C 001:860.989 JLINK_WriteReg(R11, 0x00000000) +T714C 001:861.005 - 0.015ms returns 0 +T714C 001:861.021 JLINK_WriteReg(R12, 0x00000000) +T714C 001:861.036 - 0.015ms returns 0 +T714C 001:861.053 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:861.070 - 0.017ms returns 0 +T714C 001:861.086 JLINK_WriteReg(R14, 0x30500001) +T714C 001:861.102 - 0.015ms returns 0 +T714C 001:861.118 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:861.134 - 0.016ms returns 0 +T714C 001:861.150 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:861.166 - 0.016ms returns 0 +T714C 001:861.183 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:861.200 - 0.016ms returns 0 +T714C 001:861.216 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:861.231 - 0.015ms returns 0 +T714C 001:861.248 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:861.263 - 0.015ms returns 0 +T714C 001:861.280 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:861.296 - 0.016ms returns 0x0000004A +T714C 001:861.312 JLINK_Go() +T714C 001:861.329 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:861.627 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:863.556 - 2.244ms +T714C 001:863.578 JLINK_IsHalted() +T714C 001:863.825 - 0.246ms returns FALSE +T714C 001:863.845 JLINK_HasError() +T714C 001:865.240 JLINK_IsHalted() +T714C 001:867.524 - 2.283ms returns TRUE +T714C 001:867.589 JLINK_ReadReg(R15 (PC)) +T714C 001:867.609 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:867.920 - 0.330ms returns 0x30500000 +T714C 001:867.969 JLINK_ClrBPEx(BPHandle = 0x0000004A) +T714C 001:867.986 - 0.017ms returns 0x00 +T714C 001:868.003 JLINK_ReadReg(R0) +T714C 001:868.020 - 0.017ms returns 0x00000000 +T714C 001:868.547 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:868.580 Data: 00 00 00 80 DF 17 00 42 00 00 00 40 DC B3 01 42 ... +T714C 001:868.610 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:869.772 - 1.224ms returns 0x100 +T714C 001:869.820 JLINK_HasError() +T714C 001:869.838 JLINK_WriteReg(R0, 0x2800CC00) +T714C 001:869.857 - 0.019ms returns 0 +T714C 001:869.874 JLINK_WriteReg(R1, 0x00000100) +T714C 001:869.890 - 0.016ms returns 0 +T714C 001:869.906 JLINK_WriteReg(R2, 0x30500674) +T714C 001:869.922 - 0.015ms returns 0 +T714C 001:869.938 JLINK_WriteReg(R3, 0x00000000) +T714C 001:869.954 - 0.015ms returns 0 +T714C 001:869.969 JLINK_WriteReg(R4, 0x00000000) +T714C 001:869.985 - 0.015ms returns 0 +T714C 001:870.001 JLINK_WriteReg(R5, 0x00000000) +T714C 001:870.016 - 0.015ms returns 0 +T714C 001:870.032 JLINK_WriteReg(R6, 0x00000000) +T714C 001:870.048 - 0.015ms returns 0 +T714C 001:870.063 JLINK_WriteReg(R7, 0x00000000) +T714C 001:870.079 - 0.015ms returns 0 +T714C 001:870.095 JLINK_WriteReg(R8, 0x00000000) +T714C 001:870.110 - 0.015ms returns 0 +T714C 001:870.127 JLINK_WriteReg(R9, 0x30500458) +T714C 001:870.142 - 0.015ms returns 0 +T714C 001:870.158 JLINK_WriteReg(R10, 0x00000000) +T714C 001:870.174 - 0.016ms returns 0 +T714C 001:870.190 JLINK_WriteReg(R11, 0x00000000) +T714C 001:870.206 - 0.015ms returns 0 +T714C 001:870.222 JLINK_WriteReg(R12, 0x00000000) +T714C 001:870.237 - 0.015ms returns 0 +T714C 001:870.253 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:870.269 - 0.016ms returns 0 +T714C 001:870.285 JLINK_WriteReg(R14, 0x30500001) +T714C 001:870.301 - 0.016ms returns 0 +T714C 001:870.317 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:870.333 - 0.016ms returns 0 +T714C 001:870.349 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:870.364 - 0.015ms returns 0 +T714C 001:870.380 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:870.396 - 0.015ms returns 0 +T714C 001:870.414 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:870.430 - 0.015ms returns 0 +T714C 001:870.445 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:870.461 - 0.015ms returns 0 +T714C 001:870.477 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:870.494 - 0.016ms returns 0x0000004B +T714C 001:870.510 JLINK_Go() +T714C 001:870.528 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:870.832 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:872.955 - 2.444ms +T714C 001:873.003 JLINK_IsHalted() +T714C 001:873.301 - 0.296ms returns FALSE +T714C 001:873.381 JLINK_HasError() +T714C 001:875.250 JLINK_IsHalted() +T714C 001:877.633 - 2.381ms returns TRUE +T714C 001:877.689 JLINK_ReadReg(R15 (PC)) +T714C 001:877.711 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:878.300 - 0.611ms returns 0x30500000 +T714C 001:878.370 JLINK_ClrBPEx(BPHandle = 0x0000004B) +T714C 001:878.388 - 0.018ms returns 0x00 +T714C 001:878.405 JLINK_ReadReg(R0) +T714C 001:878.424 - 0.018ms returns 0x00000000 +T714C 001:879.808 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:879.851 Data: 2C 40 DC 40 4F F0 80 0E 06 68 A2 42 0E FA 03 FE ... +T714C 001:879.886 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:880.857 - 1.049ms returns 0x100 +T714C 001:880.904 JLINK_HasError() +T714C 001:880.925 JLINK_WriteReg(R0, 0x2800CD00) +T714C 001:880.948 - 0.022ms returns 0 +T714C 001:880.965 JLINK_WriteReg(R1, 0x00000100) +T714C 001:880.982 - 0.017ms returns 0 +T714C 001:881.000 JLINK_WriteReg(R2, 0x30500674) +T714C 001:881.017 - 0.017ms returns 0 +T714C 001:881.034 JLINK_WriteReg(R3, 0x00000000) +T714C 001:881.051 - 0.017ms returns 0 +T714C 001:881.069 JLINK_WriteReg(R4, 0x00000000) +T714C 001:881.085 - 0.016ms returns 0 +T714C 001:881.102 JLINK_WriteReg(R5, 0x00000000) +T714C 001:881.119 - 0.017ms returns 0 +T714C 001:881.172 JLINK_WriteReg(R6, 0x00000000) +T714C 001:881.197 - 0.025ms returns 0 +T714C 001:881.216 JLINK_WriteReg(R7, 0x00000000) +T714C 001:881.233 - 0.017ms returns 0 +T714C 001:881.260 JLINK_WriteReg(R8, 0x00000000) +T714C 001:881.278 - 0.018ms returns 0 +T714C 001:881.298 JLINK_WriteReg(R9, 0x30500458) +T714C 001:881.316 - 0.018ms returns 0 +T714C 001:881.334 JLINK_WriteReg(R10, 0x00000000) +T714C 001:881.351 - 0.016ms returns 0 +T714C 001:881.370 JLINK_WriteReg(R11, 0x00000000) +T714C 001:881.387 - 0.017ms returns 0 +T714C 001:881.410 JLINK_WriteReg(R12, 0x00000000) +T714C 001:881.428 - 0.018ms returns 0 +T714C 001:881.447 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:881.466 - 0.019ms returns 0 +T714C 001:881.483 JLINK_WriteReg(R14, 0x30500001) +T714C 001:881.666 - 0.183ms returns 0 +T714C 001:881.696 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:881.715 - 0.019ms returns 0 +T714C 001:881.732 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:881.749 - 0.017ms returns 0 +T714C 001:881.766 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:881.782 - 0.016ms returns 0 +T714C 001:883.032 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:883.152 - 0.120ms returns 0 +T714C 001:883.171 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:883.188 - 0.017ms returns 0 +T714C 001:883.206 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:883.224 - 0.018ms returns 0x0000004C +T714C 001:883.241 JLINK_Go() +T714C 001:883.263 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:883.640 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:885.865 - 2.624ms +T714C 001:885.894 JLINK_IsHalted() +T714C 001:886.100 - 0.205ms returns FALSE +T714C 001:886.122 JLINK_HasError() +T714C 001:887.749 JLINK_IsHalted() +T714C 001:889.934 - 2.208ms returns TRUE +T714C 001:889.975 JLINK_ReadReg(R15 (PC)) +T714C 001:889.995 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:890.234 - 0.259ms returns 0x30500000 +T714C 001:890.255 JLINK_ClrBPEx(BPHandle = 0x0000004C) +T714C 001:890.272 - 0.017ms returns 0x00 +T714C 001:890.290 JLINK_ReadReg(R0) +T714C 001:890.306 - 0.016ms returns 0x00000000 +T714C 001:890.947 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:890.986 Data: 00 F0 74 FD C6 F8 88 70 30 68 80 00 FC D5 4F F4 ... +T714C 001:891.017 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:892.130 - 1.182ms returns 0x100 +T714C 001:892.153 JLINK_HasError() +T714C 001:892.200 JLINK_WriteReg(R0, 0x2800CE00) +T714C 001:892.218 - 0.018ms returns 0 +T714C 001:892.235 JLINK_WriteReg(R1, 0x00000100) +T714C 001:892.252 - 0.016ms returns 0 +T714C 001:892.268 JLINK_WriteReg(R2, 0x30500674) +T714C 001:892.284 - 0.016ms returns 0 +T714C 001:892.300 JLINK_WriteReg(R3, 0x00000000) +T714C 001:892.316 - 0.016ms returns 0 +T714C 001:892.332 JLINK_WriteReg(R4, 0x00000000) +T714C 001:892.349 - 0.016ms returns 0 +T714C 001:892.365 JLINK_WriteReg(R5, 0x00000000) +T714C 001:892.391 - 0.025ms returns 0 +T714C 001:892.407 JLINK_WriteReg(R6, 0x00000000) +T714C 001:892.422 - 0.015ms returns 0 +T714C 001:892.439 JLINK_WriteReg(R7, 0x00000000) +T714C 001:892.455 - 0.015ms returns 0 +T714C 001:892.471 JLINK_WriteReg(R8, 0x00000000) +T714C 001:892.487 - 0.016ms returns 0 +T714C 001:892.503 JLINK_WriteReg(R9, 0x30500458) +T714C 001:892.519 - 0.016ms returns 0 +T714C 001:892.536 JLINK_WriteReg(R10, 0x00000000) +T714C 001:892.552 - 0.016ms returns 0 +T714C 001:892.568 JLINK_WriteReg(R11, 0x00000000) +T714C 001:892.584 - 0.015ms returns 0 +T714C 001:892.600 JLINK_WriteReg(R12, 0x00000000) +T714C 001:892.616 - 0.015ms returns 0 +T714C 001:892.633 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:892.649 - 0.016ms returns 0 +T714C 001:892.666 JLINK_WriteReg(R14, 0x30500001) +T714C 001:892.682 - 0.016ms returns 0 +T714C 001:892.698 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:892.714 - 0.016ms returns 0 +T714C 001:892.730 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:892.746 - 0.015ms returns 0 +T714C 001:892.762 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:892.778 - 0.015ms returns 0 +T714C 001:892.794 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:892.810 - 0.015ms returns 0 +T714C 001:892.826 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:892.842 - 0.016ms returns 0 +T714C 001:892.859 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:892.875 - 0.016ms returns 0x0000004D +T714C 001:892.892 JLINK_Go() +T714C 001:892.909 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:893.211 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:895.140 - 2.248ms +T714C 001:895.164 JLINK_IsHalted() +T714C 001:895.376 - 0.211ms returns FALSE +T714C 001:895.396 JLINK_HasError() +T714C 001:896.725 JLINK_IsHalted() +T714C 001:898.818 - 2.094ms returns TRUE +T714C 001:898.841 JLINK_ReadReg(R15 (PC)) +T714C 001:898.858 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:899.154 - 0.312ms returns 0x30500000 +T714C 001:899.177 JLINK_ClrBPEx(BPHandle = 0x0000004D) +T714C 001:899.194 - 0.016ms returns 0x00 +T714C 001:899.211 JLINK_ReadReg(R0) +T714C 001:899.228 - 0.016ms returns 0x00000000 +T714C 001:899.778 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:899.815 Data: 41 F6 00 44 08 26 C0 F6 4E 64 C4 F2 00 06 40 F6 ... +T714C 001:899.845 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:900.901 - 1.122ms returns 0x100 +T714C 001:900.923 JLINK_HasError() +T714C 001:900.941 JLINK_WriteReg(R0, 0x2800CF00) +T714C 001:900.959 - 0.017ms returns 0 +T714C 001:900.975 JLINK_WriteReg(R1, 0x00000100) +T714C 001:900.991 - 0.016ms returns 0 +T714C 001:901.008 JLINK_WriteReg(R2, 0x30500674) +T714C 001:901.025 - 0.016ms returns 0 +T714C 001:901.041 JLINK_WriteReg(R3, 0x00000000) +T714C 001:901.059 - 0.018ms returns 0 +T714C 001:901.075 JLINK_WriteReg(R4, 0x00000000) +T714C 001:901.090 - 0.015ms returns 0 +T714C 001:901.107 JLINK_WriteReg(R5, 0x00000000) +T714C 001:901.123 - 0.015ms returns 0 +T714C 001:901.139 JLINK_WriteReg(R6, 0x00000000) +T714C 001:901.155 - 0.016ms returns 0 +T714C 001:901.172 JLINK_WriteReg(R7, 0x00000000) +T714C 001:901.187 - 0.016ms returns 0 +T714C 001:901.204 JLINK_WriteReg(R8, 0x00000000) +T714C 001:901.220 - 0.016ms returns 0 +T714C 001:901.237 JLINK_WriteReg(R9, 0x30500458) +T714C 001:901.252 - 0.016ms returns 0 +T714C 001:901.268 JLINK_WriteReg(R10, 0x00000000) +T714C 001:901.284 - 0.015ms returns 0 +T714C 001:901.300 JLINK_WriteReg(R11, 0x00000000) +T714C 001:901.316 - 0.015ms returns 0 +T714C 001:901.332 JLINK_WriteReg(R12, 0x00000000) +T714C 001:901.348 - 0.015ms returns 0 +T714C 001:901.364 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:901.381 - 0.016ms returns 0 +T714C 001:901.398 JLINK_WriteReg(R14, 0x30500001) +T714C 001:901.413 - 0.015ms returns 0 +T714C 001:901.430 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:901.446 - 0.016ms returns 0 +T714C 001:901.461 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:901.478 - 0.016ms returns 0 +T714C 001:901.494 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:901.510 - 0.015ms returns 0 +T714C 001:901.526 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:901.548 - 0.021ms returns 0 +T714C 001:901.567 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:901.582 - 0.015ms returns 0 +T714C 001:901.599 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:901.615 - 0.016ms returns 0x0000004E +T714C 001:901.631 JLINK_Go() +T714C 001:901.648 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:901.906 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:903.869 - 2.236ms +T714C 001:903.968 JLINK_IsHalted() +T714C 001:904.188 - 0.219ms returns FALSE +T714C 001:904.219 JLINK_HasError() +T714C 001:905.960 JLINK_IsHalted() +T714C 001:908.106 - 2.146ms returns TRUE +T714C 001:908.765 JLINK_ReadReg(R15 (PC)) +T714C 001:908.787 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:909.030 - 0.265ms returns 0x30500000 +T714C 001:909.052 JLINK_ClrBPEx(BPHandle = 0x0000004E) +T714C 001:909.068 - 0.016ms returns 0x00 +T714C 001:909.084 JLINK_ReadReg(R0) +T714C 001:909.101 - 0.016ms returns 0x00000000 +T714C 001:909.619 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:909.654 Data: 22 F4 A0 62 04 D0 28 B9 42 F4 80 72 0A 60 70 47 ... +T714C 001:909.686 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:910.788 - 1.169ms returns 0x100 +T714C 001:910.811 JLINK_HasError() +T714C 001:910.829 JLINK_WriteReg(R0, 0x2800D000) +T714C 001:910.847 - 0.018ms returns 0 +T714C 001:910.864 JLINK_WriteReg(R1, 0x00000100) +T714C 001:910.880 - 0.016ms returns 0 +T714C 001:910.896 JLINK_WriteReg(R2, 0x30500674) +T714C 001:910.912 - 0.016ms returns 0 +T714C 001:910.929 JLINK_WriteReg(R3, 0x00000000) +T714C 001:910.944 - 0.015ms returns 0 +T714C 001:910.961 JLINK_WriteReg(R4, 0x00000000) +T714C 001:910.977 - 0.016ms returns 0 +T714C 001:910.994 JLINK_WriteReg(R5, 0x00000000) +T714C 001:911.009 - 0.015ms returns 0 +T714C 001:911.025 JLINK_WriteReg(R6, 0x00000000) +T714C 001:911.041 - 0.015ms returns 0 +T714C 001:911.057 JLINK_WriteReg(R7, 0x00000000) +T714C 001:911.073 - 0.015ms returns 0 +T714C 001:911.089 JLINK_WriteReg(R8, 0x00000000) +T714C 001:911.105 - 0.016ms returns 0 +T714C 001:911.122 JLINK_WriteReg(R9, 0x30500458) +T714C 001:911.138 - 0.015ms returns 0 +T714C 001:911.154 JLINK_WriteReg(R10, 0x00000000) +T714C 001:911.170 - 0.016ms returns 0 +T714C 001:911.186 JLINK_WriteReg(R11, 0x00000000) +T714C 001:911.203 - 0.016ms returns 0 +T714C 001:911.219 JLINK_WriteReg(R12, 0x00000000) +T714C 001:911.234 - 0.015ms returns 0 +T714C 001:911.251 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:911.267 - 0.016ms returns 0 +T714C 001:911.283 JLINK_WriteReg(R14, 0x30500001) +T714C 001:911.299 - 0.016ms returns 0 +T714C 001:911.316 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:911.331 - 0.015ms returns 0 +T714C 001:911.347 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:911.363 - 0.015ms returns 0 +T714C 001:911.379 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:911.395 - 0.015ms returns 0 +T714C 001:911.412 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:911.427 - 0.015ms returns 0 +T714C 001:911.444 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:911.460 - 0.015ms returns 0 +T714C 001:911.477 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:911.493 - 0.016ms returns 0x0000004F +T714C 001:911.510 JLINK_Go() +T714C 001:911.527 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:911.781 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:913.716 - 2.206ms +T714C 001:913.744 JLINK_IsHalted() +T714C 001:913.967 - 0.223ms returns FALSE +T714C 001:913.988 JLINK_HasError() +T714C 001:916.044 JLINK_IsHalted() +T714C 001:918.318 - 2.270ms returns TRUE +T714C 001:918.372 JLINK_ReadReg(R15 (PC)) +T714C 001:918.392 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:918.683 - 0.310ms returns 0x30500000 +T714C 001:918.704 JLINK_ClrBPEx(BPHandle = 0x0000004F) +T714C 001:918.720 - 0.016ms returns 0x00 +T714C 001:918.737 JLINK_ReadReg(R0) +T714C 001:918.753 - 0.016ms returns 0x00000000 +T714C 001:919.614 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:919.667 Data: 00 28 E5 D1 DD E9 00 12 06 F1 4A 40 48 40 82 F0 ... +T714C 001:919.709 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:920.772 - 1.156ms returns 0x100 +T714C 001:920.948 JLINK_HasError() +T714C 001:920.969 JLINK_WriteReg(R0, 0x2800D100) +T714C 001:920.996 - 0.027ms returns 0 +T714C 001:921.014 JLINK_WriteReg(R1, 0x00000100) +T714C 001:921.048 - 0.033ms returns 0 +T714C 001:921.065 JLINK_WriteReg(R2, 0x30500674) +T714C 001:921.082 - 0.016ms returns 0 +T714C 001:921.100 JLINK_WriteReg(R3, 0x00000000) +T714C 001:921.150 - 0.050ms returns 0 +T714C 001:921.182 JLINK_WriteReg(R4, 0x00000000) +T714C 001:921.201 - 0.019ms returns 0 +T714C 001:921.256 JLINK_WriteReg(R5, 0x00000000) +T714C 001:921.275 - 0.019ms returns 0 +T714C 001:921.293 JLINK_WriteReg(R6, 0x00000000) +T714C 001:921.310 - 0.017ms returns 0 +T714C 001:921.327 JLINK_WriteReg(R7, 0x00000000) +T714C 001:921.376 - 0.048ms returns 0 +T714C 001:921.395 JLINK_WriteReg(R8, 0x00000000) +T714C 001:921.508 - 0.111ms returns 0 +T714C 001:921.581 JLINK_WriteReg(R9, 0x30500458) +T714C 001:921.720 - 0.140ms returns 0 +T714C 001:921.766 JLINK_WriteReg(R10, 0x00000000) +T714C 001:921.845 - 0.079ms returns 0 +T714C 001:921.911 JLINK_WriteReg(R11, 0x00000000) +T714C 001:921.931 - 0.020ms returns 0 +T714C 001:921.950 JLINK_WriteReg(R12, 0x00000000) +T714C 001:921.968 - 0.018ms returns 0 +T714C 001:921.984 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:922.004 - 0.020ms returns 0 +T714C 001:922.100 JLINK_WriteReg(R14, 0x30500001) +T714C 001:922.149 - 0.049ms returns 0 +T714C 001:922.167 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:922.185 - 0.017ms returns 0 +T714C 001:922.202 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:922.223 - 0.021ms returns 0 +T714C 001:922.328 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:922.368 - 0.040ms returns 0 +T714C 001:922.389 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:922.406 - 0.016ms returns 0 +T714C 001:922.423 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:922.441 - 0.017ms returns 0 +T714C 001:922.472 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:922.491 - 0.019ms returns 0x00000050 +T714C 001:922.509 JLINK_Go() +T714C 001:922.530 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:922.878 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:925.074 - 2.565ms +T714C 001:925.113 JLINK_IsHalted() +T714C 001:925.381 - 0.268ms returns FALSE +T714C 001:925.402 JLINK_HasError() +T714C 001:926.518 JLINK_IsHalted() +T714C 001:928.610 - 2.093ms returns TRUE +T714C 001:928.633 JLINK_ReadReg(R15 (PC)) +T714C 001:928.650 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:928.902 - 0.269ms returns 0x30500000 +T714C 001:928.923 JLINK_ClrBPEx(BPHandle = 0x00000050) +T714C 001:928.938 - 0.016ms returns 0x00 +T714C 001:928.955 JLINK_ReadReg(R0) +T714C 001:928.972 - 0.016ms returns 0x00000000 +T714C 001:929.597 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:929.632 Data: FF F7 BE FB 39 68 01 22 52 FA 81 F1 B0 FB F1 F0 ... +T714C 001:929.663 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:930.719 - 1.122ms returns 0x100 +T714C 001:930.742 JLINK_HasError() +T714C 001:930.760 JLINK_WriteReg(R0, 0x2800D200) +T714C 001:930.778 - 0.018ms returns 0 +T714C 001:930.795 JLINK_WriteReg(R1, 0x00000100) +T714C 001:930.811 - 0.016ms returns 0 +T714C 001:930.828 JLINK_WriteReg(R2, 0x30500674) +T714C 001:930.844 - 0.016ms returns 0 +T714C 001:930.861 JLINK_WriteReg(R3, 0x00000000) +T714C 001:930.878 - 0.016ms returns 0 +T714C 001:930.896 JLINK_WriteReg(R4, 0x00000000) +T714C 001:930.911 - 0.015ms returns 0 +T714C 001:930.928 JLINK_WriteReg(R5, 0x00000000) +T714C 001:930.944 - 0.016ms returns 0 +T714C 001:930.960 JLINK_WriteReg(R6, 0x00000000) +T714C 001:930.975 - 0.015ms returns 0 +T714C 001:930.992 JLINK_WriteReg(R7, 0x00000000) +T714C 001:931.008 - 0.015ms returns 0 +T714C 001:931.024 JLINK_WriteReg(R8, 0x00000000) +T714C 001:931.039 - 0.015ms returns 0 +T714C 001:931.055 JLINK_WriteReg(R9, 0x30500458) +T714C 001:931.071 - 0.015ms returns 0 +T714C 001:931.087 JLINK_WriteReg(R10, 0x00000000) +T714C 001:931.103 - 0.015ms returns 0 +T714C 001:931.119 JLINK_WriteReg(R11, 0x00000000) +T714C 001:931.135 - 0.015ms returns 0 +T714C 001:931.151 JLINK_WriteReg(R12, 0x00000000) +T714C 001:931.167 - 0.015ms returns 0 +T714C 001:931.183 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:931.204 - 0.020ms returns 0 +T714C 001:931.220 JLINK_WriteReg(R14, 0x30500001) +T714C 001:931.236 - 0.016ms returns 0 +T714C 001:931.252 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:931.268 - 0.016ms returns 0 +T714C 001:931.284 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:931.301 - 0.016ms returns 0 +T714C 001:931.318 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:931.333 - 0.015ms returns 0 +T714C 001:931.350 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:931.366 - 0.015ms returns 0 +T714C 001:931.382 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:931.398 - 0.015ms returns 0 +T714C 001:931.414 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:931.430 - 0.016ms returns 0x00000051 +T714C 001:931.447 JLINK_Go() +T714C 001:931.465 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:931.715 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:933.604 - 2.156ms +T714C 001:933.651 JLINK_IsHalted() +T714C 001:933.900 - 0.249ms returns FALSE +T714C 001:933.925 JLINK_HasError() +T714C 001:935.574 JLINK_IsHalted() +T714C 001:937.798 - 2.223ms returns TRUE +T714C 001:937.822 JLINK_ReadReg(R15 (PC)) +T714C 001:937.841 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:938.080 - 0.258ms returns 0x30500000 +T714C 001:938.102 JLINK_ClrBPEx(BPHandle = 0x00000051) +T714C 001:938.118 - 0.016ms returns 0x00 +T714C 001:938.136 JLINK_ReadReg(R0) +T714C 001:938.153 - 0.016ms returns 0x00000000 +T714C 001:938.938 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:938.991 Data: C4 F2 45 44 20 68 1B 21 1A E0 40 F6 80 50 C4 F2 ... +T714C 001:939.025 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:940.087 - 1.149ms returns 0x100 +T714C 001:940.114 JLINK_HasError() +T714C 001:940.133 JLINK_WriteReg(R0, 0x2800D300) +T714C 001:940.186 - 0.053ms returns 0 +T714C 001:940.204 JLINK_WriteReg(R1, 0x00000100) +T714C 001:940.221 - 0.016ms returns 0 +T714C 001:940.237 JLINK_WriteReg(R2, 0x30500674) +T714C 001:940.253 - 0.015ms returns 0 +T714C 001:940.270 JLINK_WriteReg(R3, 0x00000000) +T714C 001:940.286 - 0.016ms returns 0 +T714C 001:940.304 JLINK_WriteReg(R4, 0x00000000) +T714C 001:940.320 - 0.016ms returns 0 +T714C 001:940.337 JLINK_WriteReg(R5, 0x00000000) +T714C 001:940.353 - 0.016ms returns 0 +T714C 001:940.370 JLINK_WriteReg(R6, 0x00000000) +T714C 001:940.386 - 0.016ms returns 0 +T714C 001:940.403 JLINK_WriteReg(R7, 0x00000000) +T714C 001:940.419 - 0.016ms returns 0 +T714C 001:940.435 JLINK_WriteReg(R8, 0x00000000) +T714C 001:940.452 - 0.016ms returns 0 +T714C 001:940.468 JLINK_WriteReg(R9, 0x30500458) +T714C 001:940.484 - 0.016ms returns 0 +T714C 001:940.501 JLINK_WriteReg(R10, 0x00000000) +T714C 001:940.517 - 0.016ms returns 0 +T714C 001:940.534 JLINK_WriteReg(R11, 0x00000000) +T714C 001:940.550 - 0.016ms returns 0 +T714C 001:940.566 JLINK_WriteReg(R12, 0x00000000) +T714C 001:940.582 - 0.016ms returns 0 +T714C 001:940.598 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:940.615 - 0.017ms returns 0 +T714C 001:940.632 JLINK_WriteReg(R14, 0x30500001) +T714C 001:940.648 - 0.016ms returns 0 +T714C 001:940.664 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:940.681 - 0.016ms returns 0 +T714C 001:940.697 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:940.713 - 0.016ms returns 0 +T714C 001:940.730 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:940.746 - 0.015ms returns 0 +T714C 001:940.762 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:940.778 - 0.015ms returns 0 +T714C 001:940.826 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:940.846 - 0.020ms returns 0 +T714C 001:940.863 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:940.880 - 0.017ms returns 0x00000052 +T714C 001:940.896 JLINK_Go() +T714C 001:940.914 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:941.303 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:943.336 - 2.439ms +T714C 001:943.359 JLINK_IsHalted() +T714C 001:943.601 - 0.241ms returns FALSE +T714C 001:943.621 JLINK_HasError() +T714C 001:945.680 JLINK_IsHalted() +T714C 001:947.842 - 2.161ms returns TRUE +T714C 001:947.864 JLINK_ReadReg(R15 (PC)) +T714C 001:947.882 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:948.088 - 0.223ms returns 0x30500000 +T714C 001:948.109 JLINK_ClrBPEx(BPHandle = 0x00000052) +T714C 001:948.125 - 0.016ms returns 0x00 +T714C 001:948.143 JLINK_ReadReg(R0) +T714C 001:948.159 - 0.016ms returns 0x00000000 +T714C 001:948.705 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:948.741 Data: 60 68 4F F4 00 21 00 F0 75 F8 BD E8 10 40 04 F0 ... +T714C 001:948.771 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:949.854 - 1.149ms returns 0x100 +T714C 001:949.912 JLINK_HasError() +T714C 001:949.935 JLINK_WriteReg(R0, 0x2800D400) +T714C 001:949.957 - 0.023ms returns 0 +T714C 001:949.974 JLINK_WriteReg(R1, 0x00000100) +T714C 001:949.991 - 0.016ms returns 0 +T714C 001:950.008 JLINK_WriteReg(R2, 0x30500674) +T714C 001:950.024 - 0.016ms returns 0 +T714C 001:950.043 JLINK_WriteReg(R3, 0x00000000) +T714C 001:950.059 - 0.015ms returns 0 +T714C 001:950.075 JLINK_WriteReg(R4, 0x00000000) +T714C 001:950.091 - 0.015ms returns 0 +T714C 001:950.107 JLINK_WriteReg(R5, 0x00000000) +T714C 001:950.123 - 0.015ms returns 0 +T714C 001:950.139 JLINK_WriteReg(R6, 0x00000000) +T714C 001:950.155 - 0.016ms returns 0 +T714C 001:950.172 JLINK_WriteReg(R7, 0x00000000) +T714C 001:950.189 - 0.016ms returns 0 +T714C 001:950.206 JLINK_WriteReg(R8, 0x00000000) +T714C 001:950.222 - 0.016ms returns 0 +T714C 001:950.239 JLINK_WriteReg(R9, 0x30500458) +T714C 001:950.255 - 0.015ms returns 0 +T714C 001:950.271 JLINK_WriteReg(R10, 0x00000000) +T714C 001:950.287 - 0.016ms returns 0 +T714C 001:950.303 JLINK_WriteReg(R11, 0x00000000) +T714C 001:950.319 - 0.015ms returns 0 +T714C 001:950.335 JLINK_WriteReg(R12, 0x00000000) +T714C 001:950.360 - 0.024ms returns 0 +T714C 001:950.376 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:950.394 - 0.017ms returns 0 +T714C 001:950.410 JLINK_WriteReg(R14, 0x30500001) +T714C 001:950.427 - 0.016ms returns 0 +T714C 001:950.443 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:950.459 - 0.016ms returns 0 +T714C 001:950.476 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:950.492 - 0.016ms returns 0 +T714C 001:950.508 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:950.524 - 0.016ms returns 0 +T714C 001:950.540 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:950.556 - 0.015ms returns 0 +T714C 001:950.573 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:950.590 - 0.016ms returns 0 +T714C 001:950.608 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:950.625 - 0.018ms returns 0x00000053 +T714C 001:950.642 JLINK_Go() +T714C 001:950.660 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:950.980 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:953.004 - 2.361ms +T714C 001:953.030 JLINK_IsHalted() +T714C 001:953.314 - 0.283ms returns FALSE +T714C 001:953.335 JLINK_HasError() +T714C 001:955.882 JLINK_IsHalted() +T714C 001:958.155 - 2.272ms returns TRUE +T714C 001:958.179 JLINK_ReadReg(R15 (PC)) +T714C 001:958.198 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:958.461 - 0.281ms returns 0x30500000 +T714C 001:958.482 JLINK_ClrBPEx(BPHandle = 0x00000053) +T714C 001:958.499 - 0.017ms returns 0x00 +T714C 001:958.519 JLINK_ReadReg(R0) +T714C 001:958.535 - 0.016ms returns 0x00000000 +T714C 001:959.076 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:959.110 Data: 70 32 42 EA 03 42 82 62 4C F2 03 02 43 69 CC F2 ... +T714C 001:959.140 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:960.160 - 1.084ms returns 0x100 +T714C 001:960.769 JLINK_HasError() +T714C 001:960.819 JLINK_WriteReg(R0, 0x2800D500) +T714C 001:960.838 - 0.018ms returns 0 +T714C 001:960.855 JLINK_WriteReg(R1, 0x00000100) +T714C 001:960.872 - 0.016ms returns 0 +T714C 001:960.888 JLINK_WriteReg(R2, 0x30500674) +T714C 001:960.904 - 0.016ms returns 0 +T714C 001:960.920 JLINK_WriteReg(R3, 0x00000000) +T714C 001:960.936 - 0.015ms returns 0 +T714C 001:960.952 JLINK_WriteReg(R4, 0x00000000) +T714C 001:960.968 - 0.016ms returns 0 +T714C 001:960.985 JLINK_WriteReg(R5, 0x00000000) +T714C 001:961.001 - 0.015ms returns 0 +T714C 001:961.017 JLINK_WriteReg(R6, 0x00000000) +T714C 001:961.033 - 0.015ms returns 0 +T714C 001:961.049 JLINK_WriteReg(R7, 0x00000000) +T714C 001:961.069 - 0.020ms returns 0 +T714C 001:961.085 JLINK_WriteReg(R8, 0x00000000) +T714C 001:961.102 - 0.016ms returns 0 +T714C 001:961.119 JLINK_WriteReg(R9, 0x30500458) +T714C 001:961.135 - 0.016ms returns 0 +T714C 001:961.151 JLINK_WriteReg(R10, 0x00000000) +T714C 001:961.167 - 0.016ms returns 0 +T714C 001:961.183 JLINK_WriteReg(R11, 0x00000000) +T714C 001:961.199 - 0.016ms returns 0 +T714C 001:961.216 JLINK_WriteReg(R12, 0x00000000) +T714C 001:961.231 - 0.015ms returns 0 +T714C 001:961.247 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:961.264 - 0.017ms returns 0 +T714C 001:961.281 JLINK_WriteReg(R14, 0x30500001) +T714C 001:961.296 - 0.015ms returns 0 +T714C 001:961.313 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:961.328 - 0.015ms returns 0 +T714C 001:961.345 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:961.360 - 0.016ms returns 0 +T714C 001:961.377 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:961.393 - 0.016ms returns 0 +T714C 001:961.409 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:961.425 - 0.016ms returns 0 +T714C 001:961.442 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:961.457 - 0.015ms returns 0 +T714C 001:961.474 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:961.491 - 0.016ms returns 0x00000054 +T714C 001:961.508 JLINK_Go() +T714C 001:961.526 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:961.784 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:963.750 - 2.242ms +T714C 001:963.775 JLINK_IsHalted() +T714C 001:963.989 - 0.213ms returns FALSE +T714C 001:964.012 JLINK_HasError() +T714C 001:966.053 JLINK_IsHalted() +T714C 001:968.400 - 2.347ms returns TRUE +T714C 001:968.457 JLINK_ReadReg(R15 (PC)) +T714C 001:968.480 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:968.709 - 0.251ms returns 0x30500000 +T714C 001:968.730 JLINK_ClrBPEx(BPHandle = 0x00000054) +T714C 001:968.747 - 0.016ms returns 0x00 +T714C 001:968.764 JLINK_ReadReg(R0) +T714C 001:968.781 - 0.016ms returns 0x00000000 +T714C 001:969.379 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:969.414 Data: 04 07 38 BF A4 EB 0E 07 5F 45 9C BF B2 46 9C 46 ... +T714C 001:969.446 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:970.570 - 1.191ms returns 0x100 +T714C 001:970.595 JLINK_HasError() +T714C 001:970.613 JLINK_WriteReg(R0, 0x2800D600) +T714C 001:970.631 - 0.018ms returns 0 +T714C 001:970.648 JLINK_WriteReg(R1, 0x00000100) +T714C 001:970.664 - 0.016ms returns 0 +T714C 001:970.681 JLINK_WriteReg(R2, 0x30500674) +T714C 001:970.697 - 0.015ms returns 0 +T714C 001:970.716 JLINK_WriteReg(R3, 0x00000000) +T714C 001:970.731 - 0.015ms returns 0 +T714C 001:970.748 JLINK_WriteReg(R4, 0x00000000) +T714C 001:970.764 - 0.016ms returns 0 +T714C 001:970.780 JLINK_WriteReg(R5, 0x00000000) +T714C 001:970.796 - 0.015ms returns 0 +T714C 001:970.812 JLINK_WriteReg(R6, 0x00000000) +T714C 001:970.828 - 0.015ms returns 0 +T714C 001:970.844 JLINK_WriteReg(R7, 0x00000000) +T714C 001:970.860 - 0.016ms returns 0 +T714C 001:970.876 JLINK_WriteReg(R8, 0x00000000) +T714C 001:970.892 - 0.015ms returns 0 +T714C 001:970.908 JLINK_WriteReg(R9, 0x30500458) +T714C 001:970.924 - 0.015ms returns 0 +T714C 001:970.940 JLINK_WriteReg(R10, 0x00000000) +T714C 001:970.956 - 0.015ms returns 0 +T714C 001:970.972 JLINK_WriteReg(R11, 0x00000000) +T714C 001:970.988 - 0.015ms returns 0 +T714C 001:971.005 JLINK_WriteReg(R12, 0x00000000) +T714C 001:971.021 - 0.015ms returns 0 +T714C 001:971.037 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:971.055 - 0.018ms returns 0 +T714C 001:971.071 JLINK_WriteReg(R14, 0x30500001) +T714C 001:971.087 - 0.016ms returns 0 +T714C 001:971.103 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:971.120 - 0.016ms returns 0 +T714C 001:971.137 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:971.153 - 0.015ms returns 0 +T714C 001:971.169 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:971.184 - 0.015ms returns 0 +T714C 001:971.200 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:971.216 - 0.016ms returns 0 +T714C 001:971.233 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:971.249 - 0.016ms returns 0 +T714C 001:971.266 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:971.288 - 0.023ms returns 0x00000055 +T714C 001:971.305 JLINK_Go() +T714C 001:971.323 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:971.604 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:973.555 - 2.250ms +T714C 001:973.578 JLINK_IsHalted() +T714C 001:973.831 - 0.252ms returns FALSE +T714C 001:973.852 JLINK_HasError() +T714C 001:975.496 JLINK_IsHalted() +T714C 001:977.771 - 2.274ms returns TRUE +T714C 001:977.818 JLINK_ReadReg(R15 (PC)) +T714C 001:977.838 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:978.098 - 0.279ms returns 0x30500000 +T714C 001:978.148 JLINK_ClrBPEx(BPHandle = 0x00000055) +T714C 001:978.167 - 0.019ms returns 0x00 +T714C 001:978.187 JLINK_ReadReg(R0) +T714C 001:978.205 - 0.018ms returns 0x00000000 +T714C 001:978.677 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:978.707 Data: 03 02 03 E0 00 2F 18 BF 46 F0 10 02 4B 7D 00 2B ... +T714C 001:978.736 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:979.874 - 1.196ms returns 0x100 +T714C 001:979.921 JLINK_HasError() +T714C 001:979.939 JLINK_WriteReg(R0, 0x2800D700) +T714C 001:979.958 - 0.018ms returns 0 +T714C 001:979.974 JLINK_WriteReg(R1, 0x00000100) +T714C 001:979.990 - 0.015ms returns 0 +T714C 001:980.006 JLINK_WriteReg(R2, 0x30500674) +T714C 001:980.022 - 0.015ms returns 0 +T714C 001:980.038 JLINK_WriteReg(R3, 0x00000000) +T714C 001:980.053 - 0.015ms returns 0 +T714C 001:980.069 JLINK_WriteReg(R4, 0x00000000) +T714C 001:980.085 - 0.016ms returns 0 +T714C 001:980.101 JLINK_WriteReg(R5, 0x00000000) +T714C 001:980.116 - 0.015ms returns 0 +T714C 001:980.132 JLINK_WriteReg(R6, 0x00000000) +T714C 001:980.147 - 0.015ms returns 0 +T714C 001:980.164 JLINK_WriteReg(R7, 0x00000000) +T714C 001:980.179 - 0.015ms returns 0 +T714C 001:980.195 JLINK_WriteReg(R8, 0x00000000) +T714C 001:980.211 - 0.015ms returns 0 +T714C 001:980.227 JLINK_WriteReg(R9, 0x30500458) +T714C 001:980.242 - 0.015ms returns 0 +T714C 001:980.258 JLINK_WriteReg(R10, 0x00000000) +T714C 001:980.274 - 0.015ms returns 0 +T714C 001:980.290 JLINK_WriteReg(R11, 0x00000000) +T714C 001:980.305 - 0.015ms returns 0 +T714C 001:980.321 JLINK_WriteReg(R12, 0x00000000) +T714C 001:980.336 - 0.015ms returns 0 +T714C 001:980.353 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:980.370 - 0.017ms returns 0 +T714C 001:980.386 JLINK_WriteReg(R14, 0x30500001) +T714C 001:980.401 - 0.015ms returns 0 +T714C 001:980.418 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:980.433 - 0.015ms returns 0 +T714C 001:980.449 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:980.464 - 0.015ms returns 0 +T714C 001:980.481 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:980.497 - 0.016ms returns 0 +T714C 001:980.514 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:980.639 - 0.124ms returns 0 +T714C 001:980.690 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:980.716 - 0.025ms returns 0 +T714C 001:980.743 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:980.771 - 0.027ms returns 0x00000056 +T714C 001:980.797 JLINK_Go() +T714C 001:980.834 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:981.254 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:983.406 - 2.608ms +T714C 001:983.472 JLINK_IsHalted() +T714C 001:983.762 - 0.289ms returns FALSE +T714C 001:983.810 JLINK_HasError() +T714C 001:985.639 JLINK_IsHalted() +T714C 001:988.129 - 2.489ms returns TRUE +T714C 001:988.825 JLINK_ReadReg(R15 (PC)) +T714C 001:988.879 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:989.203 - 0.377ms returns 0x30500000 +T714C 001:989.250 JLINK_ClrBPEx(BPHandle = 0x00000056) +T714C 001:989.267 - 0.017ms returns 0x00 +T714C 001:989.284 JLINK_ReadReg(R0) +T714C 001:989.301 - 0.016ms returns 0x00000000 +T714C 001:989.913 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 001:989.944 Data: 75 F8 20 68 20 F0 04 00 20 60 10 BD 13 78 63 B1 ... +T714C 001:989.975 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 001:990.973 - 1.059ms returns 0x100 +T714C 001:991.021 JLINK_HasError() +T714C 001:991.038 JLINK_WriteReg(R0, 0x2800D800) +T714C 001:991.057 - 0.018ms returns 0 +T714C 001:991.073 JLINK_WriteReg(R1, 0x00000100) +T714C 001:991.090 - 0.016ms returns 0 +T714C 001:991.106 JLINK_WriteReg(R2, 0x30500674) +T714C 001:991.129 - 0.022ms returns 0 +T714C 001:991.145 JLINK_WriteReg(R3, 0x00000000) +T714C 001:991.161 - 0.016ms returns 0 +T714C 001:991.177 JLINK_WriteReg(R4, 0x00000000) +T714C 001:991.192 - 0.015ms returns 0 +T714C 001:991.208 JLINK_WriteReg(R5, 0x00000000) +T714C 001:991.224 - 0.015ms returns 0 +T714C 001:991.240 JLINK_WriteReg(R6, 0x00000000) +T714C 001:991.255 - 0.015ms returns 0 +T714C 001:991.304 JLINK_WriteReg(R7, 0x00000000) +T714C 001:991.320 - 0.015ms returns 0 +T714C 001:991.336 JLINK_WriteReg(R8, 0x00000000) +T714C 001:991.352 - 0.015ms returns 0 +T714C 001:991.368 JLINK_WriteReg(R9, 0x30500458) +T714C 001:991.383 - 0.015ms returns 0 +T714C 001:991.399 JLINK_WriteReg(R10, 0x00000000) +T714C 001:991.414 - 0.015ms returns 0 +T714C 001:991.430 JLINK_WriteReg(R11, 0x00000000) +T714C 001:991.446 - 0.015ms returns 0 +T714C 001:991.462 JLINK_WriteReg(R12, 0x00000000) +T714C 001:991.477 - 0.015ms returns 0 +T714C 001:991.493 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 001:991.509 - 0.016ms returns 0 +T714C 001:991.524 JLINK_WriteReg(R14, 0x30500001) +T714C 001:991.540 - 0.015ms returns 0 +T714C 001:991.556 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 001:991.572 - 0.015ms returns 0 +T714C 001:991.600 JLINK_WriteReg(XPSR, 0x01000000) +T714C 001:991.616 - 0.016ms returns 0 +T714C 001:991.632 JLINK_WriteReg(MSP, 0x30508000) +T714C 001:991.647 - 0.015ms returns 0 +T714C 001:991.663 JLINK_WriteReg(PSP, 0x30508000) +T714C 001:991.678 - 0.015ms returns 0 +T714C 001:991.694 JLINK_WriteReg(CFBP, 0x00000000) +T714C 001:991.709 - 0.015ms returns 0 +T714C 001:991.726 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 001:991.743 - 0.016ms returns 0x00000057 +T714C 001:991.759 JLINK_Go() +T714C 001:991.776 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 001:992.082 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 001:994.312 - 2.552ms +T714C 001:994.358 JLINK_IsHalted() +T714C 001:994.662 - 0.302ms returns FALSE +T714C 001:994.707 JLINK_HasError() +T714C 001:996.784 JLINK_IsHalted() +T714C 001:999.065 - 2.280ms returns TRUE +T714C 001:999.110 JLINK_ReadReg(R15 (PC)) +T714C 001:999.130 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 001:999.440 - 0.329ms returns 0x30500000 +T714C 001:999.467 JLINK_ClrBPEx(BPHandle = 0x00000057) +T714C 001:999.484 - 0.017ms returns 0x00 +T714C 001:999.501 JLINK_ReadReg(R0) +T714C 001:999.518 - 0.017ms returns 0x00000000 +T714C 002:000.188 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:000.222 Data: 00 23 FE F7 37 F8 00 46 40 1E 00 28 FC D1 80 BD ... +T714C 002:000.252 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:001.529 - 1.340ms returns 0x100 +T714C 002:001.580 JLINK_HasError() +T714C 002:001.598 JLINK_WriteReg(R0, 0x2800D900) +T714C 002:001.618 - 0.020ms returns 0 +T714C 002:001.634 JLINK_WriteReg(R1, 0x00000100) +T714C 002:001.650 - 0.015ms returns 0 +T714C 002:001.666 JLINK_WriteReg(R2, 0x30500674) +T714C 002:001.684 - 0.017ms returns 0 +T714C 002:001.700 JLINK_WriteReg(R3, 0x00000000) +T714C 002:001.716 - 0.015ms returns 0 +T714C 002:001.732 JLINK_WriteReg(R4, 0x00000000) +T714C 002:001.748 - 0.015ms returns 0 +T714C 002:001.764 JLINK_WriteReg(R5, 0x00000000) +T714C 002:001.779 - 0.015ms returns 0 +T714C 002:001.795 JLINK_WriteReg(R6, 0x00000000) +T714C 002:001.812 - 0.017ms returns 0 +T714C 002:001.828 JLINK_WriteReg(R7, 0x00000000) +T714C 002:001.844 - 0.015ms returns 0 +T714C 002:001.860 JLINK_WriteReg(R8, 0x00000000) +T714C 002:001.875 - 0.015ms returns 0 +T714C 002:001.891 JLINK_WriteReg(R9, 0x30500458) +T714C 002:001.907 - 0.015ms returns 0 +T714C 002:001.923 JLINK_WriteReg(R10, 0x00000000) +T714C 002:001.938 - 0.015ms returns 0 +T714C 002:001.954 JLINK_WriteReg(R11, 0x00000000) +T714C 002:001.970 - 0.015ms returns 0 +T714C 002:001.986 JLINK_WriteReg(R12, 0x00000000) +T714C 002:002.001 - 0.015ms returns 0 +T714C 002:002.018 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:002.034 - 0.016ms returns 0 +T714C 002:002.050 JLINK_WriteReg(R14, 0x30500001) +T714C 002:002.065 - 0.015ms returns 0 +T714C 002:002.081 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:002.101 - 0.020ms returns 0 +T714C 002:002.117 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:002.134 - 0.016ms returns 0 +T714C 002:002.150 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:002.165 - 0.015ms returns 0 +T714C 002:002.181 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:002.196 - 0.015ms returns 0 +T714C 002:002.212 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:002.228 - 0.016ms returns 0 +T714C 002:002.244 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:002.260 - 0.016ms returns 0x00000058 +T714C 002:002.276 JLINK_Go() +T714C 002:002.294 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:002.620 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:004.712 - 2.435ms +T714C 002:004.759 JLINK_IsHalted() +T714C 002:005.040 - 0.280ms returns FALSE +T714C 002:005.086 JLINK_HasError() +T714C 002:006.893 JLINK_IsHalted() +T714C 002:009.217 - 2.323ms returns TRUE +T714C 002:009.265 JLINK_ReadReg(R15 (PC)) +T714C 002:009.284 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:009.591 - 0.325ms returns 0x30500000 +T714C 002:009.638 JLINK_ClrBPEx(BPHandle = 0x00000058) +T714C 002:009.656 - 0.017ms returns 0x00 +T714C 002:009.673 JLINK_ReadReg(R0) +T714C 002:009.690 - 0.016ms returns 0x00000000 +T714C 002:010.164 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:010.194 Data: 4D F6 28 11 4F F6 FF 70 51 60 90 60 10 68 40 F0 ... +T714C 002:010.223 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:011.220 - 1.055ms returns 0x100 +T714C 002:011.264 JLINK_HasError() +T714C 002:011.288 JLINK_WriteReg(R0, 0x2800DA00) +T714C 002:011.306 - 0.018ms returns 0 +T714C 002:011.334 JLINK_WriteReg(R1, 0x00000100) +T714C 002:011.351 - 0.016ms returns 0 +T714C 002:011.368 JLINK_WriteReg(R2, 0x30500674) +T714C 002:011.384 - 0.016ms returns 0 +T714C 002:011.400 JLINK_WriteReg(R3, 0x00000000) +T714C 002:011.416 - 0.016ms returns 0 +T714C 002:011.433 JLINK_WriteReg(R4, 0x00000000) +T714C 002:011.451 - 0.018ms returns 0 +T714C 002:011.466 JLINK_WriteReg(R5, 0x00000000) +T714C 002:011.481 - 0.014ms returns 0 +T714C 002:011.496 JLINK_WriteReg(R6, 0x00000000) +T714C 002:011.518 - 0.022ms returns 0 +T714C 002:011.535 JLINK_WriteReg(R7, 0x00000000) +T714C 002:011.551 - 0.016ms returns 0 +T714C 002:011.568 JLINK_WriteReg(R8, 0x00000000) +T714C 002:011.587 - 0.019ms returns 0 +T714C 002:011.602 JLINK_WriteReg(R9, 0x30500458) +T714C 002:011.617 - 0.014ms returns 0 +T714C 002:011.632 JLINK_WriteReg(R10, 0x00000000) +T714C 002:011.646 - 0.014ms returns 0 +T714C 002:011.661 JLINK_WriteReg(R11, 0x00000000) +T714C 002:011.676 - 0.014ms returns 0 +T714C 002:011.691 JLINK_WriteReg(R12, 0x00000000) +T714C 002:011.707 - 0.015ms returns 0 +T714C 002:011.722 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:011.737 - 0.015ms returns 0 +T714C 002:011.752 JLINK_WriteReg(R14, 0x30500001) +T714C 002:011.772 - 0.019ms returns 0 +T714C 002:011.787 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:011.801 - 0.014ms returns 0 +T714C 002:011.816 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:011.830 - 0.014ms returns 0 +T714C 002:011.845 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:011.860 - 0.014ms returns 0 +T714C 002:011.874 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:011.889 - 0.014ms returns 0 +T714C 002:011.904 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:011.919 - 0.015ms returns 0 +T714C 002:011.935 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:011.950 - 0.015ms returns 0x00000059 +T714C 002:011.965 JLINK_Go() +T714C 002:011.982 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:012.431 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:014.545 - 2.579ms +T714C 002:015.336 JLINK_IsHalted() +T714C 002:017.685 - 2.348ms returns TRUE +T714C 002:017.736 JLINK_ReadReg(R15 (PC)) +T714C 002:017.755 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:018.030 - 0.293ms returns 0x30500000 +T714C 002:018.053 JLINK_ClrBPEx(BPHandle = 0x00000059) +T714C 002:018.069 - 0.016ms returns 0x00 +T714C 002:018.086 JLINK_ReadReg(R0) +T714C 002:018.103 - 0.017ms returns 0x00000000 +T714C 002:018.706 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:018.738 Data: F0 B5 83 B0 0C 46 09 68 6F 46 05 46 38 46 0B 22 ... +T714C 002:018.774 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:019.853 - 1.146ms returns 0x100 +T714C 002:019.877 JLINK_HasError() +T714C 002:019.894 JLINK_WriteReg(R0, 0x2800DB00) +T714C 002:019.912 - 0.018ms returns 0 +T714C 002:019.928 JLINK_WriteReg(R1, 0x00000100) +T714C 002:019.945 - 0.016ms returns 0 +T714C 002:019.961 JLINK_WriteReg(R2, 0x30500674) +T714C 002:019.977 - 0.016ms returns 0 +T714C 002:019.993 JLINK_WriteReg(R3, 0x00000000) +T714C 002:020.009 - 0.015ms returns 0 +T714C 002:020.025 JLINK_WriteReg(R4, 0x00000000) +T714C 002:020.042 - 0.017ms returns 0 +T714C 002:020.058 JLINK_WriteReg(R5, 0x00000000) +T714C 002:020.074 - 0.015ms returns 0 +T714C 002:020.090 JLINK_WriteReg(R6, 0x00000000) +T714C 002:020.106 - 0.016ms returns 0 +T714C 002:020.122 JLINK_WriteReg(R7, 0x00000000) +T714C 002:020.138 - 0.015ms returns 0 +T714C 002:020.154 JLINK_WriteReg(R8, 0x00000000) +T714C 002:020.170 - 0.016ms returns 0 +T714C 002:020.187 JLINK_WriteReg(R9, 0x30500458) +T714C 002:020.202 - 0.015ms returns 0 +T714C 002:020.219 JLINK_WriteReg(R10, 0x00000000) +T714C 002:020.234 - 0.015ms returns 0 +T714C 002:020.251 JLINK_WriteReg(R11, 0x00000000) +T714C 002:020.267 - 0.015ms returns 0 +T714C 002:020.283 JLINK_WriteReg(R12, 0x00000000) +T714C 002:020.299 - 0.015ms returns 0 +T714C 002:020.315 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:020.332 - 0.017ms returns 0 +T714C 002:020.348 JLINK_WriteReg(R14, 0x30500001) +T714C 002:020.364 - 0.015ms returns 0 +T714C 002:020.380 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:020.396 - 0.016ms returns 0 +T714C 002:020.414 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:020.431 - 0.016ms returns 0 +T714C 002:020.448 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:020.465 - 0.016ms returns 0 +T714C 002:020.481 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:020.497 - 0.016ms returns 0 +T714C 002:020.514 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:020.529 - 0.015ms returns 0 +T714C 002:020.546 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:020.562 - 0.016ms returns 0x0000005A +T714C 002:020.578 JLINK_Go() +T714C 002:020.596 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:020.881 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:023.042 - 2.463ms +T714C 002:023.089 JLINK_IsHalted() +T714C 002:023.311 - 0.221ms returns FALSE +T714C 002:023.332 JLINK_HasError() +T714C 002:025.363 JLINK_IsHalted() +T714C 002:027.614 - 2.251ms returns TRUE +T714C 002:027.666 JLINK_ReadReg(R15 (PC)) +T714C 002:027.685 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:027.904 - 0.237ms returns 0x30500000 +T714C 002:027.926 JLINK_ClrBPEx(BPHandle = 0x0000005A) +T714C 002:027.942 - 0.016ms returns 0x00 +T714C 002:027.959 JLINK_ReadReg(R0) +T714C 002:027.976 - 0.016ms returns 0x00000000 +T714C 002:028.520 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:028.554 Data: 70 40 04 F0 F3 B9 40 F2 74 25 C2 F2 00 05 A9 6C ... +T714C 002:028.587 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:029.728 - 1.207ms returns 0x100 +T714C 002:029.775 JLINK_HasError() +T714C 002:029.793 JLINK_WriteReg(R0, 0x2800DC00) +T714C 002:029.813 - 0.019ms returns 0 +T714C 002:029.829 JLINK_WriteReg(R1, 0x00000100) +T714C 002:029.845 - 0.016ms returns 0 +T714C 002:029.862 JLINK_WriteReg(R2, 0x30500674) +T714C 002:029.877 - 0.015ms returns 0 +T714C 002:029.893 JLINK_WriteReg(R3, 0x00000000) +T714C 002:029.909 - 0.015ms returns 0 +T714C 002:029.925 JLINK_WriteReg(R4, 0x00000000) +T714C 002:029.940 - 0.015ms returns 0 +T714C 002:029.956 JLINK_WriteReg(R5, 0x00000000) +T714C 002:029.972 - 0.015ms returns 0 +T714C 002:029.987 JLINK_WriteReg(R6, 0x00000000) +T714C 002:030.003 - 0.016ms returns 0 +T714C 002:030.044 JLINK_WriteReg(R7, 0x00000000) +T714C 002:030.059 - 0.015ms returns 0 +T714C 002:030.075 JLINK_WriteReg(R8, 0x00000000) +T714C 002:030.090 - 0.015ms returns 0 +T714C 002:030.106 JLINK_WriteReg(R9, 0x30500458) +T714C 002:030.122 - 0.015ms returns 0 +T714C 002:030.138 JLINK_WriteReg(R10, 0x00000000) +T714C 002:030.153 - 0.015ms returns 0 +T714C 002:030.170 JLINK_WriteReg(R11, 0x00000000) +T714C 002:030.190 - 0.020ms returns 0 +T714C 002:030.205 JLINK_WriteReg(R12, 0x00000000) +T714C 002:030.221 - 0.015ms returns 0 +T714C 002:030.236 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:030.253 - 0.016ms returns 0 +T714C 002:030.268 JLINK_WriteReg(R14, 0x30500001) +T714C 002:030.284 - 0.015ms returns 0 +T714C 002:030.300 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:030.330 - 0.029ms returns 0 +T714C 002:030.346 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:030.363 - 0.016ms returns 0 +T714C 002:030.380 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:030.397 - 0.016ms returns 0 +T714C 002:030.414 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:030.431 - 0.017ms returns 0 +T714C 002:030.447 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:030.462 - 0.015ms returns 0 +T714C 002:030.478 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:030.494 - 0.016ms returns 0x0000005B +T714C 002:030.510 JLINK_Go() +T714C 002:030.528 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:030.832 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:032.846 - 2.336ms +T714C 002:032.899 JLINK_IsHalted() +T714C 002:033.160 - 0.260ms returns FALSE +T714C 002:033.208 JLINK_HasError() +T714C 002:034.708 JLINK_IsHalted() +T714C 002:037.042 - 2.333ms returns TRUE +T714C 002:037.088 JLINK_ReadReg(R15 (PC)) +T714C 002:037.108 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:037.388 - 0.299ms returns 0x30500000 +T714C 002:037.434 JLINK_ClrBPEx(BPHandle = 0x0000005B) +T714C 002:037.452 - 0.018ms returns 0x00 +T714C 002:037.469 JLINK_ReadReg(R0) +T714C 002:037.486 - 0.016ms returns 0x00000000 +T714C 002:038.018 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:038.048 Data: 4E A0 06 F0 DD F9 A0 B1 E1 68 4E A0 06 F0 D8 F9 ... +T714C 002:038.078 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:039.258 - 1.240ms returns 0x100 +T714C 002:039.305 JLINK_HasError() +T714C 002:039.323 JLINK_WriteReg(R0, 0x2800DD00) +T714C 002:039.342 - 0.018ms returns 0 +T714C 002:039.358 JLINK_WriteReg(R1, 0x00000100) +T714C 002:039.374 - 0.015ms returns 0 +T714C 002:039.390 JLINK_WriteReg(R2, 0x30500674) +T714C 002:039.405 - 0.015ms returns 0 +T714C 002:039.421 JLINK_WriteReg(R3, 0x00000000) +T714C 002:039.437 - 0.016ms returns 0 +T714C 002:039.453 JLINK_WriteReg(R4, 0x00000000) +T714C 002:039.469 - 0.015ms returns 0 +T714C 002:039.486 JLINK_WriteReg(R5, 0x00000000) +T714C 002:039.501 - 0.015ms returns 0 +T714C 002:039.517 JLINK_WriteReg(R6, 0x00000000) +T714C 002:039.533 - 0.016ms returns 0 +T714C 002:039.549 JLINK_WriteReg(R7, 0x00000000) +T714C 002:039.564 - 0.015ms returns 0 +T714C 002:039.580 JLINK_WriteReg(R8, 0x00000000) +T714C 002:039.596 - 0.015ms returns 0 +T714C 002:039.611 JLINK_WriteReg(R9, 0x30500458) +T714C 002:039.627 - 0.015ms returns 0 +T714C 002:039.642 JLINK_WriteReg(R10, 0x00000000) +T714C 002:039.658 - 0.015ms returns 0 +T714C 002:039.674 JLINK_WriteReg(R11, 0x00000000) +T714C 002:039.690 - 0.015ms returns 0 +T714C 002:039.705 JLINK_WriteReg(R12, 0x00000000) +T714C 002:039.721 - 0.015ms returns 0 +T714C 002:039.737 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:039.754 - 0.017ms returns 0 +T714C 002:039.770 JLINK_WriteReg(R14, 0x30500001) +T714C 002:039.786 - 0.015ms returns 0 +T714C 002:039.802 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:039.817 - 0.015ms returns 0 +T714C 002:039.833 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:039.849 - 0.015ms returns 0 +T714C 002:039.864 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:039.880 - 0.015ms returns 0 +T714C 002:039.897 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:039.913 - 0.015ms returns 0 +T714C 002:039.929 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:039.944 - 0.015ms returns 0 +T714C 002:039.962 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:039.977 - 0.016ms returns 0x0000005C +T714C 002:039.993 JLINK_Go() +T714C 002:040.010 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:040.346 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:042.303 - 2.309ms +T714C 002:042.364 JLINK_IsHalted() +T714C 002:042.715 - 0.349ms returns FALSE +T714C 002:042.769 JLINK_HasError() +T714C 002:044.653 JLINK_IsHalted() +T714C 002:047.147 - 2.493ms returns TRUE +T714C 002:047.193 JLINK_ReadReg(R15 (PC)) +T714C 002:047.213 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:047.486 - 0.292ms returns 0x30500000 +T714C 002:047.534 JLINK_ClrBPEx(BPHandle = 0x0000005C) +T714C 002:047.552 - 0.017ms returns 0x00 +T714C 002:047.568 JLINK_ReadReg(R0) +T714C 002:047.585 - 0.016ms returns 0x00000000 +T714C 002:048.116 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:048.147 Data: 68 69 67 68 00 00 00 00 6F 6E 00 00 6C 6F 77 00 ... +T714C 002:048.179 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:049.269 - 1.152ms returns 0x100 +T714C 002:049.381 JLINK_HasError() +T714C 002:049.424 JLINK_WriteReg(R0, 0x2800DE00) +T714C 002:049.445 - 0.021ms returns 0 +T714C 002:049.462 JLINK_WriteReg(R1, 0x00000100) +T714C 002:049.478 - 0.015ms returns 0 +T714C 002:049.494 JLINK_WriteReg(R2, 0x30500674) +T714C 002:049.510 - 0.015ms returns 0 +T714C 002:049.526 JLINK_WriteReg(R3, 0x00000000) +T714C 002:049.542 - 0.015ms returns 0 +T714C 002:049.558 JLINK_WriteReg(R4, 0x00000000) +T714C 002:049.574 - 0.015ms returns 0 +T714C 002:049.590 JLINK_WriteReg(R5, 0x00000000) +T714C 002:049.606 - 0.015ms returns 0 +T714C 002:049.621 JLINK_WriteReg(R6, 0x00000000) +T714C 002:049.637 - 0.015ms returns 0 +T714C 002:049.653 JLINK_WriteReg(R7, 0x00000000) +T714C 002:049.668 - 0.015ms returns 0 +T714C 002:049.685 JLINK_WriteReg(R8, 0x00000000) +T714C 002:049.701 - 0.015ms returns 0 +T714C 002:049.717 JLINK_WriteReg(R9, 0x30500458) +T714C 002:049.732 - 0.015ms returns 0 +T714C 002:049.748 JLINK_WriteReg(R10, 0x00000000) +T714C 002:049.765 - 0.016ms returns 0 +T714C 002:049.781 JLINK_WriteReg(R11, 0x00000000) +T714C 002:049.798 - 0.016ms returns 0 +T714C 002:049.814 JLINK_WriteReg(R12, 0x00000000) +T714C 002:049.829 - 0.015ms returns 0 +T714C 002:049.845 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:049.861 - 0.016ms returns 0 +T714C 002:049.877 JLINK_WriteReg(R14, 0x30500001) +T714C 002:049.893 - 0.015ms returns 0 +T714C 002:049.909 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:049.924 - 0.015ms returns 0 +T714C 002:049.940 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:049.955 - 0.015ms returns 0 +T714C 002:049.971 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:049.987 - 0.015ms returns 0 +T714C 002:050.002 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:050.018 - 0.015ms returns 0 +T714C 002:050.034 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:050.050 - 0.015ms returns 0 +T714C 002:050.066 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:050.083 - 0.017ms returns 0x0000005D +T714C 002:050.099 JLINK_Go() +T714C 002:050.116 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:050.513 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:052.656 - 2.557ms +T714C 002:052.703 JLINK_IsHalted() +T714C 002:052.962 - 0.258ms returns FALSE +T714C 002:053.010 JLINK_HasError() +T714C 002:054.652 JLINK_IsHalted() +T714C 002:056.897 - 2.244ms returns TRUE +T714C 002:056.977 JLINK_ReadReg(R15 (PC)) +T714C 002:057.019 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:057.385 - 0.408ms returns 0x30500000 +T714C 002:057.462 JLINK_ClrBPEx(BPHandle = 0x0000005D) +T714C 002:057.489 - 0.027ms returns 0x00 +T714C 002:057.512 JLINK_ReadReg(R0) +T714C 002:057.537 - 0.024ms returns 0x00000000 +T714C 002:059.404 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:059.510 Data: A0 6C 81 69 00 29 08 BF 10 BD 23 A0 BD E8 10 40 ... +T714C 002:059.571 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:060.681 - 1.276ms returns 0x100 +T714C 002:060.745 JLINK_HasError() +T714C 002:060.766 JLINK_WriteReg(R0, 0x2800DF00) +T714C 002:060.789 - 0.023ms returns 0 +T714C 002:060.806 JLINK_WriteReg(R1, 0x00000100) +T714C 002:060.823 - 0.017ms returns 0 +T714C 002:060.841 JLINK_WriteReg(R2, 0x30500674) +T714C 002:060.857 - 0.016ms returns 0 +T714C 002:060.874 JLINK_WriteReg(R3, 0x00000000) +T714C 002:060.890 - 0.016ms returns 0 +T714C 002:060.907 JLINK_WriteReg(R4, 0x00000000) +T714C 002:060.924 - 0.016ms returns 0 +T714C 002:060.940 JLINK_WriteReg(R5, 0x00000000) +T714C 002:060.956 - 0.016ms returns 0 +T714C 002:060.978 JLINK_WriteReg(R6, 0x00000000) +T714C 002:060.995 - 0.017ms returns 0 +T714C 002:061.011 JLINK_WriteReg(R7, 0x00000000) +T714C 002:061.028 - 0.016ms returns 0 +T714C 002:061.046 JLINK_WriteReg(R8, 0x00000000) +T714C 002:061.062 - 0.016ms returns 0 +T714C 002:061.079 JLINK_WriteReg(R9, 0x30500458) +T714C 002:061.095 - 0.015ms returns 0 +T714C 002:061.112 JLINK_WriteReg(R10, 0x00000000) +T714C 002:061.129 - 0.017ms returns 0 +T714C 002:061.145 JLINK_WriteReg(R11, 0x00000000) +T714C 002:061.161 - 0.016ms returns 0 +T714C 002:061.178 JLINK_WriteReg(R12, 0x00000000) +T714C 002:061.194 - 0.016ms returns 0 +T714C 002:061.218 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:061.235 - 0.017ms returns 0 +T714C 002:061.252 JLINK_WriteReg(R14, 0x30500001) +T714C 002:061.268 - 0.016ms returns 0 +T714C 002:061.285 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:061.301 - 0.016ms returns 0 +T714C 002:061.317 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:061.334 - 0.016ms returns 0 +T714C 002:061.350 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:061.366 - 0.015ms returns 0 +T714C 002:061.382 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:061.398 - 0.015ms returns 0 +T714C 002:061.414 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:061.431 - 0.016ms returns 0 +T714C 002:061.448 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:061.464 - 0.017ms returns 0x0000005E +T714C 002:061.481 JLINK_Go() +T714C 002:061.502 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:061.781 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:063.889 - 2.406ms +T714C 002:063.946 JLINK_IsHalted() +T714C 002:064.233 - 0.286ms returns FALSE +T714C 002:064.264 JLINK_HasError() +T714C 002:067.205 JLINK_IsHalted() +T714C 002:069.616 - 2.410ms returns TRUE +T714C 002:070.391 JLINK_ReadReg(R15 (PC)) +T714C 002:070.450 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:070.769 - 0.377ms returns 0x30500000 +T714C 002:070.817 JLINK_ClrBPEx(BPHandle = 0x0000005E) +T714C 002:070.836 - 0.018ms returns 0x00 +T714C 002:070.853 JLINK_ReadReg(R0) +T714C 002:070.871 - 0.018ms returns 0x00000000 +T714C 002:071.489 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:071.521 Data: 02 F0 28 FF 03 F0 D0 FF 98 B1 46 F2 17 45 45 F6 ... +T714C 002:071.552 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:072.559 - 1.069ms returns 0x100 +T714C 002:072.620 JLINK_HasError() +T714C 002:072.640 JLINK_WriteReg(R0, 0x2800E000) +T714C 002:072.663 - 0.022ms returns 0 +T714C 002:072.680 JLINK_WriteReg(R1, 0x00000100) +T714C 002:072.696 - 0.016ms returns 0 +T714C 002:072.713 JLINK_WriteReg(R2, 0x30500674) +T714C 002:072.729 - 0.016ms returns 0 +T714C 002:072.746 JLINK_WriteReg(R3, 0x00000000) +T714C 002:072.769 - 0.022ms returns 0 +T714C 002:072.789 JLINK_WriteReg(R4, 0x00000000) +T714C 002:072.812 - 0.023ms returns 0 +T714C 002:072.833 JLINK_WriteReg(R5, 0x00000000) +T714C 002:072.849 - 0.016ms returns 0 +T714C 002:072.867 JLINK_WriteReg(R6, 0x00000000) +T714C 002:072.888 - 0.021ms returns 0 +T714C 002:072.907 JLINK_WriteReg(R7, 0x00000000) +T714C 002:072.927 - 0.020ms returns 0 +T714C 002:072.946 JLINK_WriteReg(R8, 0x00000000) +T714C 002:072.963 - 0.016ms returns 0 +T714C 002:072.980 JLINK_WriteReg(R9, 0x30500458) +T714C 002:072.998 - 0.017ms returns 0 +T714C 002:073.027 JLINK_WriteReg(R10, 0x00000000) +T714C 002:073.049 - 0.022ms returns 0 +T714C 002:073.069 JLINK_WriteReg(R11, 0x00000000) +T714C 002:073.090 - 0.021ms returns 0 +T714C 002:073.113 JLINK_WriteReg(R12, 0x00000000) +T714C 002:073.135 - 0.022ms returns 0 +T714C 002:073.157 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:073.176 - 0.019ms returns 0 +T714C 002:073.199 JLINK_WriteReg(R14, 0x30500001) +T714C 002:073.228 - 0.029ms returns 0 +T714C 002:073.250 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:073.274 - 0.023ms returns 0 +T714C 002:073.295 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:073.317 - 0.022ms returns 0 +T714C 002:073.337 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:073.358 - 0.020ms returns 0 +T714C 002:073.380 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:073.407 - 0.026ms returns 0 +T714C 002:073.426 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:073.450 - 0.024ms returns 0 +T714C 002:073.474 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:073.500 - 0.026ms returns 0x0000005F +T714C 002:073.519 JLINK_Go() +T714C 002:073.544 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:073.876 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:075.851 - 2.330ms +T714C 002:075.898 JLINK_IsHalted() +T714C 002:076.152 - 0.253ms returns FALSE +T714C 002:076.173 JLINK_HasError() +T714C 002:077.742 JLINK_IsHalted() +T714C 002:079.879 - 2.136ms returns TRUE +T714C 002:079.901 JLINK_ReadReg(R15 (PC)) +T714C 002:079.919 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:080.156 - 0.255ms returns 0x30500000 +T714C 002:080.177 JLINK_ClrBPEx(BPHandle = 0x0000005F) +T714C 002:080.193 - 0.016ms returns 0x00 +T714C 002:080.210 JLINK_ReadReg(R0) +T714C 002:080.226 - 0.016ms returns 0x00000000 +T714C 002:080.798 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:080.831 Data: 00 F0 F6 FA 56 F8 80 0F 21 46 41 F8 28 0F 41 60 ... +T714C 002:080.892 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:081.953 - 1.155ms returns 0x100 +T714C 002:081.978 JLINK_HasError() +T714C 002:081.996 JLINK_WriteReg(R0, 0x2800E100) +T714C 002:082.015 - 0.018ms returns 0 +T714C 002:082.031 JLINK_WriteReg(R1, 0x00000100) +T714C 002:082.047 - 0.015ms returns 0 +T714C 002:082.064 JLINK_WriteReg(R2, 0x30500674) +T714C 002:082.081 - 0.016ms returns 0 +T714C 002:082.097 JLINK_WriteReg(R3, 0x00000000) +T714C 002:082.113 - 0.015ms returns 0 +T714C 002:082.129 JLINK_WriteReg(R4, 0x00000000) +T714C 002:082.145 - 0.016ms returns 0 +T714C 002:082.161 JLINK_WriteReg(R5, 0x00000000) +T714C 002:082.177 - 0.016ms returns 0 +T714C 002:082.194 JLINK_WriteReg(R6, 0x00000000) +T714C 002:082.210 - 0.016ms returns 0 +T714C 002:082.228 JLINK_WriteReg(R7, 0x00000000) +T714C 002:082.244 - 0.016ms returns 0 +T714C 002:082.261 JLINK_WriteReg(R8, 0x00000000) +T714C 002:082.277 - 0.016ms returns 0 +T714C 002:082.294 JLINK_WriteReg(R9, 0x30500458) +T714C 002:082.311 - 0.017ms returns 0 +T714C 002:082.329 JLINK_WriteReg(R10, 0x00000000) +T714C 002:082.345 - 0.016ms returns 0 +T714C 002:082.362 JLINK_WriteReg(R11, 0x00000000) +T714C 002:082.379 - 0.017ms returns 0 +T714C 002:082.396 JLINK_WriteReg(R12, 0x00000000) +T714C 002:082.412 - 0.016ms returns 0 +T714C 002:082.429 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:082.446 - 0.017ms returns 0 +T714C 002:082.463 JLINK_WriteReg(R14, 0x30500001) +T714C 002:082.479 - 0.016ms returns 0 +T714C 002:082.496 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:082.513 - 0.016ms returns 0 +T714C 002:082.529 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:082.546 - 0.016ms returns 0 +T714C 002:082.563 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:082.581 - 0.018ms returns 0 +T714C 002:082.599 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:082.616 - 0.017ms returns 0 +T714C 002:082.633 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:082.652 - 0.018ms returns 0 +T714C 002:082.670 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:082.687 - 0.018ms returns 0x00000060 +T714C 002:082.704 JLINK_Go() +T714C 002:082.723 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:083.102 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:085.185 - 2.479ms +T714C 002:085.212 JLINK_IsHalted() +T714C 002:085.468 - 0.255ms returns FALSE +T714C 002:085.488 JLINK_HasError() +T714C 002:086.728 JLINK_IsHalted() +T714C 002:088.910 - 2.183ms returns TRUE +T714C 002:088.972 JLINK_ReadReg(R15 (PC)) +T714C 002:088.994 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:089.293 - 0.320ms returns 0x30500000 +T714C 002:089.332 JLINK_ClrBPEx(BPHandle = 0x00000060) +T714C 002:089.351 - 0.018ms returns 0x00 +T714C 002:089.368 JLINK_ReadReg(R0) +T714C 002:089.386 - 0.017ms returns 0x00000000 +T714C 002:089.963 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:089.997 Data: 73 FE 57 F8 80 1F B9 42 10 D0 00 BF 11 F8 08 5C ... +T714C 002:090.031 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:091.107 - 1.143ms returns 0x100 +T714C 002:091.132 JLINK_HasError() +T714C 002:091.150 JLINK_WriteReg(R0, 0x2800E200) +T714C 002:091.174 - 0.023ms returns 0 +T714C 002:091.194 JLINK_WriteReg(R1, 0x00000100) +T714C 002:091.209 - 0.016ms returns 0 +T714C 002:091.226 JLINK_WriteReg(R2, 0x30500674) +T714C 002:091.242 - 0.015ms returns 0 +T714C 002:091.259 JLINK_WriteReg(R3, 0x00000000) +T714C 002:091.275 - 0.016ms returns 0 +T714C 002:091.291 JLINK_WriteReg(R4, 0x00000000) +T714C 002:091.307 - 0.015ms returns 0 +T714C 002:091.323 JLINK_WriteReg(R5, 0x00000000) +T714C 002:091.339 - 0.016ms returns 0 +T714C 002:091.356 JLINK_WriteReg(R6, 0x00000000) +T714C 002:091.372 - 0.015ms returns 0 +T714C 002:091.388 JLINK_WriteReg(R7, 0x00000000) +T714C 002:091.404 - 0.015ms returns 0 +T714C 002:091.420 JLINK_WriteReg(R8, 0x00000000) +T714C 002:091.436 - 0.015ms returns 0 +T714C 002:091.452 JLINK_WriteReg(R9, 0x30500458) +T714C 002:091.468 - 0.015ms returns 0 +T714C 002:091.484 JLINK_WriteReg(R10, 0x00000000) +T714C 002:091.500 - 0.015ms returns 0 +T714C 002:091.516 JLINK_WriteReg(R11, 0x00000000) +T714C 002:091.532 - 0.016ms returns 0 +T714C 002:091.548 JLINK_WriteReg(R12, 0x00000000) +T714C 002:091.564 - 0.015ms returns 0 +T714C 002:091.581 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:091.599 - 0.018ms returns 0 +T714C 002:091.615 JLINK_WriteReg(R14, 0x30500001) +T714C 002:091.631 - 0.016ms returns 0 +T714C 002:091.648 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:091.663 - 0.015ms returns 0 +T714C 002:091.680 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:091.696 - 0.016ms returns 0 +T714C 002:091.713 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:091.729 - 0.016ms returns 0 +T714C 002:091.745 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:091.761 - 0.015ms returns 0 +T714C 002:091.777 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:091.793 - 0.016ms returns 0 +T714C 002:091.810 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:091.827 - 0.017ms returns 0x00000061 +T714C 002:091.844 JLINK_Go() +T714C 002:091.862 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:092.122 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:094.064 - 2.220ms +T714C 002:094.095 JLINK_IsHalted() +T714C 002:094.336 - 0.241ms returns FALSE +T714C 002:094.359 JLINK_HasError() +T714C 002:095.984 JLINK_IsHalted() +T714C 002:098.124 - 2.139ms returns TRUE +T714C 002:098.182 JLINK_ReadReg(R15 (PC)) +T714C 002:098.205 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:098.511 - 0.329ms returns 0x30500000 +T714C 002:098.544 JLINK_ClrBPEx(BPHandle = 0x00000061) +T714C 002:098.564 - 0.020ms returns 0x00 +T714C 002:098.584 JLINK_ReadReg(R0) +T714C 002:098.603 - 0.018ms returns 0x00000000 +T714C 002:099.784 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:099.838 Data: C2 F6 01 00 29 46 03 F0 71 FE 46 F2 B1 10 C2 F6 ... +T714C 002:099.886 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:101.019 - 1.234ms returns 0x100 +T714C 002:101.044 JLINK_HasError() +T714C 002:101.062 JLINK_WriteReg(R0, 0x2800E300) +T714C 002:101.080 - 0.018ms returns 0 +T714C 002:101.096 JLINK_WriteReg(R1, 0x00000100) +T714C 002:101.112 - 0.016ms returns 0 +T714C 002:101.129 JLINK_WriteReg(R2, 0x30500674) +T714C 002:101.145 - 0.016ms returns 0 +T714C 002:101.162 JLINK_WriteReg(R3, 0x00000000) +T714C 002:101.178 - 0.015ms returns 0 +T714C 002:101.194 JLINK_WriteReg(R4, 0x00000000) +T714C 002:101.210 - 0.016ms returns 0 +T714C 002:101.226 JLINK_WriteReg(R5, 0x00000000) +T714C 002:101.241 - 0.015ms returns 0 +T714C 002:101.259 JLINK_WriteReg(R6, 0x00000000) +T714C 002:101.274 - 0.015ms returns 0 +T714C 002:101.291 JLINK_WriteReg(R7, 0x00000000) +T714C 002:101.307 - 0.016ms returns 0 +T714C 002:101.324 JLINK_WriteReg(R8, 0x00000000) +T714C 002:101.339 - 0.016ms returns 0 +T714C 002:101.356 JLINK_WriteReg(R9, 0x30500458) +T714C 002:101.373 - 0.016ms returns 0 +T714C 002:101.389 JLINK_WriteReg(R10, 0x00000000) +T714C 002:101.405 - 0.015ms returns 0 +T714C 002:101.421 JLINK_WriteReg(R11, 0x00000000) +T714C 002:101.438 - 0.016ms returns 0 +T714C 002:101.453 JLINK_WriteReg(R12, 0x00000000) +T714C 002:101.470 - 0.016ms returns 0 +T714C 002:101.486 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:101.503 - 0.016ms returns 0 +T714C 002:101.525 JLINK_WriteReg(R14, 0x30500001) +T714C 002:101.541 - 0.015ms returns 0 +T714C 002:101.557 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:101.573 - 0.016ms returns 0 +T714C 002:101.589 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:101.605 - 0.016ms returns 0 +T714C 002:101.622 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:101.638 - 0.015ms returns 0 +T714C 002:101.655 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:101.671 - 0.016ms returns 0 +T714C 002:101.687 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:101.704 - 0.016ms returns 0 +T714C 002:101.721 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:101.738 - 0.016ms returns 0x00000062 +T714C 002:101.754 JLINK_Go() +T714C 002:101.772 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:102.056 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:104.035 - 2.280ms +T714C 002:104.090 JLINK_IsHalted() +T714C 002:104.339 - 0.248ms returns FALSE +T714C 002:104.360 JLINK_HasError() +T714C 002:105.870 JLINK_IsHalted() +T714C 002:108.109 - 2.240ms returns TRUE +T714C 002:108.139 JLINK_ReadReg(R15 (PC)) +T714C 002:108.159 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:108.416 - 0.277ms returns 0x30500000 +T714C 002:108.439 JLINK_ClrBPEx(BPHandle = 0x00000062) +T714C 002:108.456 - 0.016ms returns 0x00 +T714C 002:108.472 JLINK_ReadReg(R0) +T714C 002:108.489 - 0.016ms returns 0x00000000 +T714C 002:109.128 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:109.166 Data: 00 21 CD F8 00 90 06 F0 9B FB 40 46 06 F0 D0 FC ... +T714C 002:109.199 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:110.265 - 1.136ms returns 0x100 +T714C 002:110.290 JLINK_HasError() +T714C 002:110.307 JLINK_WriteReg(R0, 0x2800E400) +T714C 002:110.327 - 0.019ms returns 0 +T714C 002:110.376 JLINK_WriteReg(R1, 0x00000100) +T714C 002:110.392 - 0.016ms returns 0 +T714C 002:110.408 JLINK_WriteReg(R2, 0x30500674) +T714C 002:110.425 - 0.016ms returns 0 +T714C 002:110.443 JLINK_WriteReg(R3, 0x00000000) +T714C 002:110.459 - 0.016ms returns 0 +T714C 002:110.475 JLINK_WriteReg(R4, 0x00000000) +T714C 002:110.491 - 0.016ms returns 0 +T714C 002:110.508 JLINK_WriteReg(R5, 0x00000000) +T714C 002:110.525 - 0.016ms returns 0 +T714C 002:110.541 JLINK_WriteReg(R6, 0x00000000) +T714C 002:110.558 - 0.017ms returns 0 +T714C 002:110.575 JLINK_WriteReg(R7, 0x00000000) +T714C 002:110.592 - 0.016ms returns 0 +T714C 002:110.608 JLINK_WriteReg(R8, 0x00000000) +T714C 002:110.625 - 0.016ms returns 0 +T714C 002:110.641 JLINK_WriteReg(R9, 0x30500458) +T714C 002:110.657 - 0.016ms returns 0 +T714C 002:110.674 JLINK_WriteReg(R10, 0x00000000) +T714C 002:110.690 - 0.016ms returns 0 +T714C 002:110.706 JLINK_WriteReg(R11, 0x00000000) +T714C 002:110.722 - 0.015ms returns 0 +T714C 002:110.738 JLINK_WriteReg(R12, 0x00000000) +T714C 002:110.754 - 0.016ms returns 0 +T714C 002:110.771 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:110.788 - 0.017ms returns 0 +T714C 002:110.805 JLINK_WriteReg(R14, 0x30500001) +T714C 002:110.821 - 0.016ms returns 0 +T714C 002:110.839 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:110.857 - 0.018ms returns 0 +T714C 002:110.873 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:110.890 - 0.017ms returns 0 +T714C 002:110.907 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:110.923 - 0.016ms returns 0 +T714C 002:110.940 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:110.956 - 0.016ms returns 0 +T714C 002:110.975 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:110.991 - 0.016ms returns 0 +T714C 002:111.008 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:111.025 - 0.016ms returns 0x00000063 +T714C 002:111.041 JLINK_Go() +T714C 002:111.059 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:111.385 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:113.284 - 2.242ms +T714C 002:113.311 JLINK_IsHalted() +T714C 002:113.539 - 0.227ms returns FALSE +T714C 002:113.559 JLINK_HasError() +T714C 002:114.974 JLINK_IsHalted() +T714C 002:117.264 - 2.289ms returns TRUE +T714C 002:117.316 JLINK_ReadReg(R15 (PC)) +T714C 002:117.337 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:117.566 - 0.250ms returns 0x30500000 +T714C 002:117.588 JLINK_ClrBPEx(BPHandle = 0x00000063) +T714C 002:117.611 - 0.022ms returns 0x00 +T714C 002:117.629 JLINK_ReadReg(R0) +T714C 002:117.647 - 0.017ms returns 0x00000000 +T714C 002:119.957 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:120.065 Data: E1 FE 80 B1 47 F2 0E 05 C2 F6 01 05 34 A0 29 46 ... +T714C 002:120.108 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:121.147 - 1.189ms returns 0x100 +T714C 002:121.202 JLINK_HasError() +T714C 002:121.223 JLINK_WriteReg(R0, 0x2800E500) +T714C 002:121.245 - 0.022ms returns 0 +T714C 002:121.263 JLINK_WriteReg(R1, 0x00000100) +T714C 002:121.279 - 0.016ms returns 0 +T714C 002:121.299 JLINK_WriteReg(R2, 0x30500674) +T714C 002:121.315 - 0.016ms returns 0 +T714C 002:121.332 JLINK_WriteReg(R3, 0x00000000) +T714C 002:121.349 - 0.016ms returns 0 +T714C 002:121.366 JLINK_WriteReg(R4, 0x00000000) +T714C 002:121.382 - 0.016ms returns 0 +T714C 002:121.399 JLINK_WriteReg(R5, 0x00000000) +T714C 002:121.415 - 0.016ms returns 0 +T714C 002:121.432 JLINK_WriteReg(R6, 0x00000000) +T714C 002:121.448 - 0.016ms returns 0 +T714C 002:121.465 JLINK_WriteReg(R7, 0x00000000) +T714C 002:121.483 - 0.017ms returns 0 +T714C 002:121.502 JLINK_WriteReg(R8, 0x00000000) +T714C 002:121.518 - 0.016ms returns 0 +T714C 002:121.534 JLINK_WriteReg(R9, 0x30500458) +T714C 002:121.550 - 0.015ms returns 0 +T714C 002:121.566 JLINK_WriteReg(R10, 0x00000000) +T714C 002:121.583 - 0.016ms returns 0 +T714C 002:121.600 JLINK_WriteReg(R11, 0x00000000) +T714C 002:121.616 - 0.016ms returns 0 +T714C 002:121.632 JLINK_WriteReg(R12, 0x00000000) +T714C 002:121.648 - 0.016ms returns 0 +T714C 002:121.665 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:121.682 - 0.017ms returns 0 +T714C 002:121.699 JLINK_WriteReg(R14, 0x30500001) +T714C 002:121.715 - 0.016ms returns 0 +T714C 002:121.732 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:121.748 - 0.016ms returns 0 +T714C 002:121.765 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:121.780 - 0.015ms returns 0 +T714C 002:121.797 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:121.813 - 0.016ms returns 0 +T714C 002:121.829 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:121.846 - 0.016ms returns 0 +T714C 002:121.862 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:121.878 - 0.016ms returns 0 +T714C 002:121.895 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:121.914 - 0.018ms returns 0x00000064 +T714C 002:121.931 JLINK_Go() +T714C 002:121.951 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:122.264 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:124.299 - 2.367ms +T714C 002:124.918 JLINK_IsHalted() +T714C 002:127.018 - 2.099ms returns TRUE +T714C 002:127.043 JLINK_ReadReg(R15 (PC)) +T714C 002:127.062 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:127.312 - 0.268ms returns 0x30500000 +T714C 002:127.332 JLINK_ClrBPEx(BPHandle = 0x00000064) +T714C 002:127.349 - 0.016ms returns 0x00 +T714C 002:127.366 JLINK_ReadReg(R0) +T714C 002:127.384 - 0.017ms returns 0x00000000 +T714C 002:127.979 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:128.016 Data: 76 61 69 6C 61 62 6C 65 0A 00 00 00 46 75 6E 63 ... +T714C 002:128.048 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:128.981 - 1.001ms returns 0x100 +T714C 002:129.006 JLINK_HasError() +T714C 002:129.025 JLINK_WriteReg(R0, 0x2800E600) +T714C 002:129.047 - 0.022ms returns 0 +T714C 002:129.066 JLINK_WriteReg(R1, 0x00000100) +T714C 002:129.083 - 0.017ms returns 0 +T714C 002:129.099 JLINK_WriteReg(R2, 0x30500674) +T714C 002:129.115 - 0.016ms returns 0 +T714C 002:129.132 JLINK_WriteReg(R3, 0x00000000) +T714C 002:129.148 - 0.016ms returns 0 +T714C 002:129.165 JLINK_WriteReg(R4, 0x00000000) +T714C 002:129.181 - 0.016ms returns 0 +T714C 002:129.198 JLINK_WriteReg(R5, 0x00000000) +T714C 002:129.215 - 0.017ms returns 0 +T714C 002:129.232 JLINK_WriteReg(R6, 0x00000000) +T714C 002:129.248 - 0.016ms returns 0 +T714C 002:129.265 JLINK_WriteReg(R7, 0x00000000) +T714C 002:129.281 - 0.016ms returns 0 +T714C 002:129.298 JLINK_WriteReg(R8, 0x00000000) +T714C 002:129.315 - 0.017ms returns 0 +T714C 002:129.332 JLINK_WriteReg(R9, 0x30500458) +T714C 002:129.350 - 0.018ms returns 0 +T714C 002:129.375 JLINK_WriteReg(R10, 0x00000000) +T714C 002:129.390 - 0.015ms returns 0 +T714C 002:129.407 JLINK_WriteReg(R11, 0x00000000) +T714C 002:129.423 - 0.016ms returns 0 +T714C 002:129.439 JLINK_WriteReg(R12, 0x00000000) +T714C 002:129.455 - 0.015ms returns 0 +T714C 002:129.472 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:129.491 - 0.018ms returns 0 +T714C 002:129.508 JLINK_WriteReg(R14, 0x30500001) +T714C 002:129.525 - 0.017ms returns 0 +T714C 002:129.541 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:129.558 - 0.016ms returns 0 +T714C 002:129.574 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:129.590 - 0.016ms returns 0 +T714C 002:129.607 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:129.624 - 0.017ms returns 0 +T714C 002:129.640 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:129.656 - 0.015ms returns 0 +T714C 002:129.672 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:129.688 - 0.016ms returns 0 +T714C 002:129.705 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:129.722 - 0.017ms returns 0x00000065 +T714C 002:129.740 JLINK_Go() +T714C 002:129.758 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:130.004 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:131.969 - 2.229ms +T714C 002:132.024 JLINK_IsHalted() +T714C 002:132.288 - 0.263ms returns FALSE +T714C 002:132.316 JLINK_HasError() +T714C 002:134.354 JLINK_IsHalted() +T714C 002:136.491 - 2.135ms returns TRUE +T714C 002:136.520 JLINK_ReadReg(R15 (PC)) +T714C 002:136.539 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:136.743 - 0.223ms returns 0x30500000 +T714C 002:136.764 JLINK_ClrBPEx(BPHandle = 0x00000065) +T714C 002:136.780 - 0.016ms returns 0x00 +T714C 002:136.798 JLINK_ReadReg(R0) +T714C 002:136.814 - 0.016ms returns 0x00000000 +T714C 002:137.394 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:137.433 Data: BD E8 F0 8F 46 F2 77 59 C2 F6 01 09 04 E0 00 BF ... +T714C 002:137.465 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:138.544 - 1.150ms returns 0x100 +T714C 002:138.584 JLINK_HasError() +T714C 002:138.602 JLINK_WriteReg(R0, 0x2800E700) +T714C 002:138.622 - 0.019ms returns 0 +T714C 002:138.638 JLINK_WriteReg(R1, 0x00000100) +T714C 002:138.655 - 0.016ms returns 0 +T714C 002:138.671 JLINK_WriteReg(R2, 0x30500674) +T714C 002:138.687 - 0.016ms returns 0 +T714C 002:138.704 JLINK_WriteReg(R3, 0x00000000) +T714C 002:138.720 - 0.015ms returns 0 +T714C 002:138.736 JLINK_WriteReg(R4, 0x00000000) +T714C 002:138.753 - 0.016ms returns 0 +T714C 002:138.769 JLINK_WriteReg(R5, 0x00000000) +T714C 002:138.787 - 0.017ms returns 0 +T714C 002:138.836 JLINK_WriteReg(R6, 0x00000000) +T714C 002:138.852 - 0.016ms returns 0 +T714C 002:138.868 JLINK_WriteReg(R7, 0x00000000) +T714C 002:138.884 - 0.016ms returns 0 +T714C 002:138.900 JLINK_WriteReg(R8, 0x00000000) +T714C 002:138.916 - 0.016ms returns 0 +T714C 002:138.933 JLINK_WriteReg(R9, 0x30500458) +T714C 002:138.949 - 0.016ms returns 0 +T714C 002:138.965 JLINK_WriteReg(R10, 0x00000000) +T714C 002:138.981 - 0.016ms returns 0 +T714C 002:138.998 JLINK_WriteReg(R11, 0x00000000) +T714C 002:139.013 - 0.015ms returns 0 +T714C 002:139.030 JLINK_WriteReg(R12, 0x00000000) +T714C 002:139.045 - 0.015ms returns 0 +T714C 002:139.062 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:139.079 - 0.017ms returns 0 +T714C 002:139.095 JLINK_WriteReg(R14, 0x30500001) +T714C 002:139.111 - 0.016ms returns 0 +T714C 002:139.128 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:139.144 - 0.016ms returns 0 +T714C 002:139.160 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:139.176 - 0.016ms returns 0 +T714C 002:139.192 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:139.208 - 0.015ms returns 0 +T714C 002:139.225 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:139.241 - 0.015ms returns 0 +T714C 002:139.257 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:139.273 - 0.016ms returns 0 +T714C 002:139.290 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:139.308 - 0.017ms returns 0x00000066 +T714C 002:139.324 JLINK_Go() +T714C 002:139.342 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:139.664 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:141.617 - 2.293ms +T714C 002:141.642 JLINK_IsHalted() +T714C 002:141.843 - 0.200ms returns FALSE +T714C 002:141.864 JLINK_HasError() +T714C 002:143.410 JLINK_IsHalted() +T714C 002:145.583 - 2.174ms returns TRUE +T714C 002:145.608 JLINK_ReadReg(R15 (PC)) +T714C 002:145.626 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:145.869 - 0.260ms returns 0x30500000 +T714C 002:145.890 JLINK_ClrBPEx(BPHandle = 0x00000066) +T714C 002:145.922 - 0.033ms returns 0x00 +T714C 002:145.941 JLINK_ReadReg(R0) +T714C 002:145.959 - 0.018ms returns 0x00000000 +T714C 002:146.501 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:146.540 Data: DB F8 24 A0 31 46 50 46 04 F0 36 FB 00 28 3F F4 ... +T714C 002:146.570 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:147.543 - 1.041ms returns 0x100 +T714C 002:147.567 JLINK_HasError() +T714C 002:147.584 JLINK_WriteReg(R0, 0x2800E800) +T714C 002:147.602 - 0.018ms returns 0 +T714C 002:147.619 JLINK_WriteReg(R1, 0x00000100) +T714C 002:147.635 - 0.016ms returns 0 +T714C 002:147.652 JLINK_WriteReg(R2, 0x30500674) +T714C 002:147.669 - 0.016ms returns 0 +T714C 002:147.686 JLINK_WriteReg(R3, 0x00000000) +T714C 002:147.702 - 0.015ms returns 0 +T714C 002:147.718 JLINK_WriteReg(R4, 0x00000000) +T714C 002:147.735 - 0.016ms returns 0 +T714C 002:147.752 JLINK_WriteReg(R5, 0x00000000) +T714C 002:147.768 - 0.016ms returns 0 +T714C 002:147.784 JLINK_WriteReg(R6, 0x00000000) +T714C 002:147.800 - 0.016ms returns 0 +T714C 002:147.816 JLINK_WriteReg(R7, 0x00000000) +T714C 002:147.833 - 0.016ms returns 0 +T714C 002:147.851 JLINK_WriteReg(R8, 0x00000000) +T714C 002:147.868 - 0.017ms returns 0 +T714C 002:147.884 JLINK_WriteReg(R9, 0x30500458) +T714C 002:147.901 - 0.016ms returns 0 +T714C 002:147.917 JLINK_WriteReg(R10, 0x00000000) +T714C 002:147.933 - 0.015ms returns 0 +T714C 002:147.950 JLINK_WriteReg(R11, 0x00000000) +T714C 002:147.966 - 0.016ms returns 0 +T714C 002:147.982 JLINK_WriteReg(R12, 0x00000000) +T714C 002:147.998 - 0.015ms returns 0 +T714C 002:148.014 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:148.031 - 0.016ms returns 0 +T714C 002:148.047 JLINK_WriteReg(R14, 0x30500001) +T714C 002:148.063 - 0.015ms returns 0 +T714C 002:148.080 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:148.096 - 0.016ms returns 0 +T714C 002:148.113 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:148.130 - 0.016ms returns 0 +T714C 002:148.147 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:148.164 - 0.017ms returns 0 +T714C 002:148.180 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:148.197 - 0.016ms returns 0 +T714C 002:148.215 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:148.231 - 0.016ms returns 0 +T714C 002:148.248 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:148.264 - 0.017ms returns 0x00000067 +T714C 002:148.280 JLINK_Go() +T714C 002:148.298 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:148.574 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:150.582 - 2.300ms +T714C 002:150.633 JLINK_IsHalted() +T714C 002:150.869 - 0.235ms returns FALSE +T714C 002:150.894 JLINK_HasError() +T714C 002:152.462 JLINK_IsHalted() +T714C 002:154.682 - 2.219ms returns TRUE +T714C 002:154.706 JLINK_ReadReg(R15 (PC)) +T714C 002:154.726 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:154.966 - 0.260ms returns 0x30500000 +T714C 002:154.987 JLINK_ClrBPEx(BPHandle = 0x00000067) +T714C 002:155.004 - 0.017ms returns 0x00 +T714C 002:155.021 JLINK_ReadReg(R0) +T714C 002:155.038 - 0.016ms returns 0x00000000 +T714C 002:155.694 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:155.732 Data: 73 65 3A 20 62 61 63 6B 74 72 61 63 65 20 5B 74 ... +T714C 002:155.766 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:156.816 - 1.122ms returns 0x100 +T714C 002:156.843 JLINK_HasError() +T714C 002:156.860 JLINK_WriteReg(R0, 0x2800E900) +T714C 002:156.879 - 0.019ms returns 0 +T714C 002:156.896 JLINK_WriteReg(R1, 0x00000100) +T714C 002:156.912 - 0.016ms returns 0 +T714C 002:156.928 JLINK_WriteReg(R2, 0x30500674) +T714C 002:156.944 - 0.015ms returns 0 +T714C 002:156.960 JLINK_WriteReg(R3, 0x00000000) +T714C 002:156.977 - 0.017ms returns 0 +T714C 002:156.994 JLINK_WriteReg(R4, 0x00000000) +T714C 002:157.073 - 0.078ms returns 0 +T714C 002:157.090 JLINK_WriteReg(R5, 0x00000000) +T714C 002:157.106 - 0.016ms returns 0 +T714C 002:157.122 JLINK_WriteReg(R6, 0x00000000) +T714C 002:157.138 - 0.016ms returns 0 +T714C 002:157.154 JLINK_WriteReg(R7, 0x00000000) +T714C 002:157.170 - 0.015ms returns 0 +T714C 002:157.187 JLINK_WriteReg(R8, 0x00000000) +T714C 002:157.202 - 0.015ms returns 0 +T714C 002:157.219 JLINK_WriteReg(R9, 0x30500458) +T714C 002:157.235 - 0.015ms returns 0 +T714C 002:157.251 JLINK_WriteReg(R10, 0x00000000) +T714C 002:157.268 - 0.017ms returns 0 +T714C 002:157.284 JLINK_WriteReg(R11, 0x00000000) +T714C 002:157.301 - 0.016ms returns 0 +T714C 002:157.317 JLINK_WriteReg(R12, 0x00000000) +T714C 002:157.333 - 0.016ms returns 0 +T714C 002:157.350 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:157.367 - 0.017ms returns 0 +T714C 002:157.383 JLINK_WriteReg(R14, 0x30500001) +T714C 002:157.399 - 0.016ms returns 0 +T714C 002:157.416 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:157.432 - 0.016ms returns 0 +T714C 002:157.450 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:157.466 - 0.016ms returns 0 +T714C 002:157.483 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:157.499 - 0.016ms returns 0 +T714C 002:157.516 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:157.532 - 0.016ms returns 0 +T714C 002:157.548 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:157.564 - 0.016ms returns 0 +T714C 002:157.581 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:157.598 - 0.016ms returns 0x00000068 +T714C 002:157.614 JLINK_Go() +T714C 002:157.632 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:157.845 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:159.744 - 2.129ms +T714C 002:159.766 JLINK_IsHalted() +T714C 002:159.953 - 0.186ms returns FALSE +T714C 002:159.973 JLINK_HasError() +T714C 002:161.490 JLINK_IsHalted() +T714C 002:163.690 - 2.199ms returns TRUE +T714C 002:163.742 JLINK_ReadReg(R15 (PC)) +T714C 002:163.767 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:164.152 - 0.408ms returns 0x30500000 +T714C 002:164.243 JLINK_ClrBPEx(BPHandle = 0x00000068) +T714C 002:164.264 - 0.021ms returns 0x00 +T714C 002:164.283 JLINK_ReadReg(R0) +T714C 002:164.304 - 0.021ms returns 0x00000000 +T714C 002:165.356 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:165.410 Data: 00 20 80 BD 00 F0 AC FF 00 20 80 BD 00 F0 5C FD ... +T714C 002:165.452 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:166.529 - 1.172ms returns 0x100 +T714C 002:166.631 JLINK_HasError() +T714C 002:166.660 JLINK_WriteReg(R0, 0x2800EA00) +T714C 002:166.697 - 0.037ms returns 0 +T714C 002:166.725 JLINK_WriteReg(R1, 0x00000100) +T714C 002:166.748 - 0.023ms returns 0 +T714C 002:166.772 JLINK_WriteReg(R2, 0x30500674) +T714C 002:166.797 - 0.025ms returns 0 +T714C 002:166.825 JLINK_WriteReg(R3, 0x00000000) +T714C 002:166.848 - 0.023ms returns 0 +T714C 002:166.872 JLINK_WriteReg(R4, 0x00000000) +T714C 002:166.895 - 0.022ms returns 0 +T714C 002:166.914 JLINK_WriteReg(R5, 0x00000000) +T714C 002:166.934 - 0.020ms returns 0 +T714C 002:166.955 JLINK_WriteReg(R6, 0x00000000) +T714C 002:166.974 - 0.019ms returns 0 +T714C 002:166.996 JLINK_WriteReg(R7, 0x00000000) +T714C 002:167.014 - 0.017ms returns 0 +T714C 002:167.038 JLINK_WriteReg(R8, 0x00000000) +T714C 002:167.062 - 0.024ms returns 0 +T714C 002:167.086 JLINK_WriteReg(R9, 0x30500458) +T714C 002:167.112 - 0.025ms returns 0 +T714C 002:167.137 JLINK_WriteReg(R10, 0x00000000) +T714C 002:167.161 - 0.024ms returns 0 +T714C 002:167.186 JLINK_WriteReg(R11, 0x00000000) +T714C 002:167.210 - 0.024ms returns 0 +T714C 002:167.236 JLINK_WriteReg(R12, 0x00000000) +T714C 002:167.261 - 0.024ms returns 0 +T714C 002:167.287 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:167.314 - 0.027ms returns 0 +T714C 002:167.339 JLINK_WriteReg(R14, 0x30500001) +T714C 002:167.362 - 0.023ms returns 0 +T714C 002:167.386 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:167.410 - 0.024ms returns 0 +T714C 002:167.434 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:167.459 - 0.025ms returns 0 +T714C 002:167.490 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:167.611 - 0.121ms returns 0 +T714C 002:167.646 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:167.673 - 0.026ms returns 0 +T714C 002:167.699 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:167.726 - 0.027ms returns 0 +T714C 002:167.754 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:167.784 - 0.030ms returns 0x00000069 +T714C 002:167.811 JLINK_Go() +T714C 002:167.863 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:168.251 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:170.432 - 2.618ms +T714C 002:170.500 JLINK_IsHalted() +T714C 002:170.745 - 0.244ms returns FALSE +T714C 002:170.768 JLINK_HasError() +T714C 002:173.488 JLINK_IsHalted() +T714C 002:175.758 - 2.271ms returns TRUE +T714C 002:175.789 JLINK_ReadReg(R15 (PC)) +T714C 002:175.810 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:176.065 - 0.275ms returns 0x30500000 +T714C 002:176.089 JLINK_ClrBPEx(BPHandle = 0x00000069) +T714C 002:176.106 - 0.017ms returns 0x00 +T714C 002:176.123 JLINK_ReadReg(R0) +T714C 002:176.140 - 0.016ms returns 0x00000000 +T714C 002:176.690 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:176.723 Data: A9 F9 30 68 D0 F8 18 42 34 B3 0D F1 07 02 20 46 ... +T714C 002:176.754 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:177.849 - 1.158ms returns 0x100 +T714C 002:178.760 JLINK_HasError() +T714C 002:178.830 JLINK_WriteReg(R0, 0x2800EB00) +T714C 002:178.856 - 0.026ms returns 0 +T714C 002:178.874 JLINK_WriteReg(R1, 0x00000100) +T714C 002:178.903 - 0.029ms returns 0 +T714C 002:178.920 JLINK_WriteReg(R2, 0x30500674) +T714C 002:178.936 - 0.016ms returns 0 +T714C 002:178.953 JLINK_WriteReg(R3, 0x00000000) +T714C 002:178.969 - 0.016ms returns 0 +T714C 002:178.985 JLINK_WriteReg(R4, 0x00000000) +T714C 002:179.001 - 0.015ms returns 0 +T714C 002:179.018 JLINK_WriteReg(R5, 0x00000000) +T714C 002:179.034 - 0.015ms returns 0 +T714C 002:179.050 JLINK_WriteReg(R6, 0x00000000) +T714C 002:179.066 - 0.016ms returns 0 +T714C 002:179.082 JLINK_WriteReg(R7, 0x00000000) +T714C 002:179.099 - 0.016ms returns 0 +T714C 002:179.116 JLINK_WriteReg(R8, 0x00000000) +T714C 002:179.133 - 0.017ms returns 0 +T714C 002:179.149 JLINK_WriteReg(R9, 0x30500458) +T714C 002:179.165 - 0.016ms returns 0 +T714C 002:179.182 JLINK_WriteReg(R10, 0x00000000) +T714C 002:179.198 - 0.016ms returns 0 +T714C 002:179.215 JLINK_WriteReg(R11, 0x00000000) +T714C 002:179.231 - 0.016ms returns 0 +T714C 002:179.247 JLINK_WriteReg(R12, 0x00000000) +T714C 002:179.264 - 0.016ms returns 0 +T714C 002:179.280 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:179.298 - 0.018ms returns 0 +T714C 002:179.314 JLINK_WriteReg(R14, 0x30500001) +T714C 002:179.330 - 0.016ms returns 0 +T714C 002:179.346 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:179.363 - 0.016ms returns 0 +T714C 002:179.379 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:179.395 - 0.016ms returns 0 +T714C 002:179.412 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:179.428 - 0.016ms returns 0 +T714C 002:179.445 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:179.461 - 0.016ms returns 0 +T714C 002:179.478 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:179.495 - 0.016ms returns 0 +T714C 002:179.512 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:179.530 - 0.018ms returns 0x0000006A +T714C 002:179.550 JLINK_Go() +T714C 002:179.568 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:179.977 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:182.037 - 2.486ms +T714C 002:182.087 JLINK_IsHalted() +T714C 002:182.375 - 0.288ms returns FALSE +T714C 002:182.398 JLINK_HasError() +T714C 002:184.579 JLINK_IsHalted() +T714C 002:186.931 - 2.351ms returns TRUE +T714C 002:186.979 JLINK_ReadReg(R15 (PC)) +T714C 002:186.999 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:187.308 - 0.328ms returns 0x30500000 +T714C 002:187.359 JLINK_ClrBPEx(BPHandle = 0x0000006A) +T714C 002:187.378 - 0.018ms returns 0x00 +T714C 002:187.396 JLINK_ReadReg(R0) +T714C 002:187.415 - 0.019ms returns 0x00000000 +T714C 002:188.023 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:188.054 Data: 02 F0 CC FC 30 68 00 21 00 F5 E1 70 51 22 00 25 ... +T714C 002:188.085 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:189.291 - 1.267ms returns 0x100 +T714C 002:189.339 JLINK_HasError() +T714C 002:189.357 JLINK_WriteReg(R0, 0x2800EC00) +T714C 002:189.376 - 0.018ms returns 0 +T714C 002:189.392 JLINK_WriteReg(R1, 0x00000100) +T714C 002:189.408 - 0.015ms returns 0 +T714C 002:189.424 JLINK_WriteReg(R2, 0x30500674) +T714C 002:189.439 - 0.015ms returns 0 +T714C 002:189.456 JLINK_WriteReg(R3, 0x00000000) +T714C 002:189.472 - 0.015ms returns 0 +T714C 002:189.489 JLINK_WriteReg(R4, 0x00000000) +T714C 002:189.504 - 0.015ms returns 0 +T714C 002:189.520 JLINK_WriteReg(R5, 0x00000000) +T714C 002:189.536 - 0.015ms returns 0 +T714C 002:189.552 JLINK_WriteReg(R6, 0x00000000) +T714C 002:189.568 - 0.015ms returns 0 +T714C 002:189.584 JLINK_WriteReg(R7, 0x00000000) +T714C 002:189.600 - 0.015ms returns 0 +T714C 002:189.616 JLINK_WriteReg(R8, 0x00000000) +T714C 002:189.631 - 0.015ms returns 0 +T714C 002:189.647 JLINK_WriteReg(R9, 0x30500458) +T714C 002:189.663 - 0.016ms returns 0 +T714C 002:189.679 JLINK_WriteReg(R10, 0x00000000) +T714C 002:189.695 - 0.015ms returns 0 +T714C 002:189.712 JLINK_WriteReg(R11, 0x00000000) +T714C 002:189.727 - 0.015ms returns 0 +T714C 002:189.743 JLINK_WriteReg(R12, 0x00000000) +T714C 002:189.759 - 0.015ms returns 0 +T714C 002:189.775 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:189.792 - 0.016ms returns 0 +T714C 002:189.808 JLINK_WriteReg(R14, 0x30500001) +T714C 002:189.823 - 0.015ms returns 0 +T714C 002:189.839 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:189.854 - 0.015ms returns 0 +T714C 002:189.871 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:189.886 - 0.015ms returns 0 +T714C 002:189.902 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:189.918 - 0.015ms returns 0 +T714C 002:189.935 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:189.950 - 0.015ms returns 0 +T714C 002:189.966 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:189.982 - 0.015ms returns 0 +T714C 002:189.998 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:190.015 - 0.016ms returns 0x0000006B +T714C 002:190.031 JLINK_Go() +T714C 002:190.049 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:190.394 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:192.569 - 2.537ms +T714C 002:192.617 JLINK_IsHalted() +T714C 002:192.888 - 0.271ms returns FALSE +T714C 002:192.934 JLINK_HasError() +T714C 002:194.559 JLINK_IsHalted() +T714C 002:196.933 - 2.374ms returns TRUE +T714C 002:197.008 JLINK_ReadReg(R15 (PC)) +T714C 002:197.030 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:197.354 - 0.344ms returns 0x30500000 +T714C 002:197.403 JLINK_ClrBPEx(BPHandle = 0x0000006B) +T714C 002:197.423 - 0.020ms returns 0x00 +T714C 002:197.440 JLINK_ReadReg(R0) +T714C 002:197.458 - 0.018ms returns 0x00000000 +T714C 002:198.043 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:198.077 Data: 02 01 80 F8 2D 10 1C BF 20 46 05 F0 2F FD 00 20 ... +T714C 002:198.111 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:199.324 - 1.280ms returns 0x100 +T714C 002:199.394 JLINK_HasError() +T714C 002:199.412 JLINK_WriteReg(R0, 0x2800ED00) +T714C 002:199.435 - 0.022ms returns 0 +T714C 002:199.451 JLINK_WriteReg(R1, 0x00000100) +T714C 002:199.467 - 0.016ms returns 0 +T714C 002:199.484 JLINK_WriteReg(R2, 0x30500674) +T714C 002:199.499 - 0.015ms returns 0 +T714C 002:199.519 JLINK_WriteReg(R3, 0x00000000) +T714C 002:199.535 - 0.015ms returns 0 +T714C 002:199.551 JLINK_WriteReg(R4, 0x00000000) +T714C 002:199.567 - 0.016ms returns 0 +T714C 002:199.584 JLINK_WriteReg(R5, 0x00000000) +T714C 002:199.600 - 0.016ms returns 0 +T714C 002:199.616 JLINK_WriteReg(R6, 0x00000000) +T714C 002:199.632 - 0.015ms returns 0 +T714C 002:199.648 JLINK_WriteReg(R7, 0x00000000) +T714C 002:199.663 - 0.015ms returns 0 +T714C 002:199.679 JLINK_WriteReg(R8, 0x00000000) +T714C 002:199.695 - 0.016ms returns 0 +T714C 002:199.712 JLINK_WriteReg(R9, 0x30500458) +T714C 002:199.728 - 0.016ms returns 0 +T714C 002:199.744 JLINK_WriteReg(R10, 0x00000000) +T714C 002:199.760 - 0.015ms returns 0 +T714C 002:199.777 JLINK_WriteReg(R11, 0x00000000) +T714C 002:199.793 - 0.016ms returns 0 +T714C 002:199.809 JLINK_WriteReg(R12, 0x00000000) +T714C 002:199.883 - 0.074ms returns 0 +T714C 002:199.900 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:199.918 - 0.018ms returns 0 +T714C 002:199.934 JLINK_WriteReg(R14, 0x30500001) +T714C 002:199.950 - 0.016ms returns 0 +T714C 002:199.967 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:199.983 - 0.015ms returns 0 +T714C 002:200.000 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:200.016 - 0.015ms returns 0 +T714C 002:200.032 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:200.047 - 0.015ms returns 0 +T714C 002:200.064 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:200.079 - 0.015ms returns 0 +T714C 002:200.095 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:200.111 - 0.015ms returns 0 +T714C 002:200.127 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:200.144 - 0.017ms returns 0x0000006C +T714C 002:200.160 JLINK_Go() +T714C 002:200.179 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:200.579 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:202.859 - 2.697ms +T714C 002:202.910 JLINK_IsHalted() +T714C 002:203.166 - 0.255ms returns FALSE +T714C 002:203.214 JLINK_HasError() +T714C 002:205.136 JLINK_IsHalted() +T714C 002:207.643 - 2.506ms returns TRUE +T714C 002:207.692 JLINK_ReadReg(R15 (PC)) +T714C 002:207.712 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:208.015 - 0.322ms returns 0x30500000 +T714C 002:208.065 JLINK_ClrBPEx(BPHandle = 0x0000006C) +T714C 002:208.083 - 0.018ms returns 0x00 +T714C 002:208.100 JLINK_ReadReg(R0) +T714C 002:208.117 - 0.017ms returns 0x00000000 +T714C 002:210.476 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:210.547 Data: 92 00 92 00 BB 00 FB 00 5B 00 92 00 92 00 5B 00 ... +T714C 002:210.583 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:211.718 - 1.241ms returns 0x100 +T714C 002:211.769 JLINK_HasError() +T714C 002:211.788 JLINK_WriteReg(R0, 0x2800EE00) +T714C 002:211.808 - 0.019ms returns 0 +T714C 002:211.853 JLINK_WriteReg(R1, 0x00000100) +T714C 002:211.869 - 0.016ms returns 0 +T714C 002:211.885 JLINK_WriteReg(R2, 0x30500674) +T714C 002:211.900 - 0.015ms returns 0 +T714C 002:211.916 JLINK_WriteReg(R3, 0x00000000) +T714C 002:211.932 - 0.016ms returns 0 +T714C 002:211.948 JLINK_WriteReg(R4, 0x00000000) +T714C 002:211.964 - 0.015ms returns 0 +T714C 002:211.980 JLINK_WriteReg(R5, 0x00000000) +T714C 002:211.995 - 0.015ms returns 0 +T714C 002:212.011 JLINK_WriteReg(R6, 0x00000000) +T714C 002:212.027 - 0.015ms returns 0 +T714C 002:212.043 JLINK_WriteReg(R7, 0x00000000) +T714C 002:212.059 - 0.015ms returns 0 +T714C 002:212.075 JLINK_WriteReg(R8, 0x00000000) +T714C 002:212.093 - 0.018ms returns 0 +T714C 002:212.110 JLINK_WriteReg(R9, 0x30500458) +T714C 002:212.127 - 0.017ms returns 0 +T714C 002:212.143 JLINK_WriteReg(R10, 0x00000000) +T714C 002:212.159 - 0.015ms returns 0 +T714C 002:212.175 JLINK_WriteReg(R11, 0x00000000) +T714C 002:212.192 - 0.017ms returns 0 +T714C 002:212.207 JLINK_WriteReg(R12, 0x00000000) +T714C 002:212.222 - 0.015ms returns 0 +T714C 002:212.239 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:212.255 - 0.016ms returns 0 +T714C 002:212.271 JLINK_WriteReg(R14, 0x30500001) +T714C 002:212.286 - 0.015ms returns 0 +T714C 002:212.302 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:212.318 - 0.015ms returns 0 +T714C 002:212.334 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:212.349 - 0.015ms returns 0 +T714C 002:212.365 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:212.380 - 0.015ms returns 0 +T714C 002:212.396 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:212.412 - 0.015ms returns 0 +T714C 002:212.428 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:212.443 - 0.015ms returns 0 +T714C 002:212.460 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:212.476 - 0.016ms returns 0x0000006D +T714C 002:212.492 JLINK_Go() +T714C 002:212.511 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:212.830 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:215.005 - 2.511ms +T714C 002:215.065 JLINK_IsHalted() +T714C 002:215.366 - 0.300ms returns FALSE +T714C 002:215.414 JLINK_HasError() +T714C 002:218.581 JLINK_IsHalted() +T714C 002:220.937 - 2.355ms returns TRUE +T714C 002:221.094 JLINK_ReadReg(R15 (PC)) +T714C 002:221.122 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:221.405 - 0.311ms returns 0x30500000 +T714C 002:221.456 JLINK_ClrBPEx(BPHandle = 0x0000006D) +T714C 002:221.475 - 0.018ms returns 0x00 +T714C 002:221.492 JLINK_ReadReg(R0) +T714C 002:221.509 - 0.017ms returns 0x00000000 +T714C 002:222.163 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:222.196 Data: 41 46 03 F0 09 F9 05 20 CD E0 B8 F1 7F 0F 2C D0 ... +T714C 002:222.228 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:223.401 - 1.237ms returns 0x100 +T714C 002:223.452 JLINK_HasError() +T714C 002:223.471 JLINK_WriteReg(R0, 0x2800EF00) +T714C 002:223.496 - 0.025ms returns 0 +T714C 002:223.519 JLINK_WriteReg(R1, 0x00000100) +T714C 002:223.535 - 0.016ms returns 0 +T714C 002:223.554 JLINK_WriteReg(R2, 0x30500674) +T714C 002:223.570 - 0.016ms returns 0 +T714C 002:223.587 JLINK_WriteReg(R3, 0x00000000) +T714C 002:223.605 - 0.018ms returns 0 +T714C 002:223.630 JLINK_WriteReg(R4, 0x00000000) +T714C 002:223.652 - 0.022ms returns 0 +T714C 002:223.672 JLINK_WriteReg(R5, 0x00000000) +T714C 002:223.693 - 0.020ms returns 0 +T714C 002:223.714 JLINK_WriteReg(R6, 0x00000000) +T714C 002:223.737 - 0.023ms returns 0 +T714C 002:223.760 JLINK_WriteReg(R7, 0x00000000) +T714C 002:223.780 - 0.019ms returns 0 +T714C 002:223.796 JLINK_WriteReg(R8, 0x00000000) +T714C 002:223.872 - 0.075ms returns 0 +T714C 002:223.892 JLINK_WriteReg(R9, 0x30500458) +T714C 002:223.910 - 0.018ms returns 0 +T714C 002:223.927 JLINK_WriteReg(R10, 0x00000000) +T714C 002:223.944 - 0.016ms returns 0 +T714C 002:223.961 JLINK_WriteReg(R11, 0x00000000) +T714C 002:223.979 - 0.017ms returns 0 +T714C 002:223.995 JLINK_WriteReg(R12, 0x00000000) +T714C 002:224.011 - 0.016ms returns 0 +T714C 002:224.028 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:224.046 - 0.018ms returns 0 +T714C 002:224.063 JLINK_WriteReg(R14, 0x30500001) +T714C 002:224.079 - 0.015ms returns 0 +T714C 002:224.095 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:224.111 - 0.015ms returns 0 +T714C 002:224.128 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:224.144 - 0.016ms returns 0 +T714C 002:224.160 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:224.177 - 0.016ms returns 0 +T714C 002:224.193 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:224.209 - 0.015ms returns 0 +T714C 002:224.225 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:224.241 - 0.016ms returns 0 +T714C 002:224.259 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:224.276 - 0.017ms returns 0x0000006E +T714C 002:224.293 JLINK_Go() +T714C 002:224.313 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:224.607 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:226.866 - 2.573ms +T714C 002:226.914 JLINK_IsHalted() +T714C 002:227.165 - 0.250ms returns FALSE +T714C 002:227.216 JLINK_HasError() +T714C 002:228.740 JLINK_IsHalted() +T714C 002:231.201 - 2.459ms returns TRUE +T714C 002:231.988 JLINK_ReadReg(R15 (PC)) +T714C 002:232.042 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:232.364 - 0.374ms returns 0x30500000 +T714C 002:232.412 JLINK_ClrBPEx(BPHandle = 0x0000006E) +T714C 002:232.430 - 0.018ms returns 0x00 +T714C 002:232.447 JLINK_ReadReg(R0) +T714C 002:232.465 - 0.017ms returns 0x00000000 +T714C 002:233.138 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:233.172 Data: 00 00 01 34 B0 F8 16 12 8C 42 F5 D3 00 F5 E1 76 ... +T714C 002:233.203 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:234.380 - 1.242ms returns 0x100 +T714C 002:234.432 JLINK_HasError() +T714C 002:234.451 JLINK_WriteReg(R0, 0x2800F000) +T714C 002:234.472 - 0.020ms returns 0 +T714C 002:234.489 JLINK_WriteReg(R1, 0x00000100) +T714C 002:234.504 - 0.015ms returns 0 +T714C 002:234.521 JLINK_WriteReg(R2, 0x30500674) +T714C 002:234.537 - 0.016ms returns 0 +T714C 002:234.554 JLINK_WriteReg(R3, 0x00000000) +T714C 002:234.570 - 0.015ms returns 0 +T714C 002:234.587 JLINK_WriteReg(R4, 0x00000000) +T714C 002:234.603 - 0.016ms returns 0 +T714C 002:234.620 JLINK_WriteReg(R5, 0x00000000) +T714C 002:234.636 - 0.015ms returns 0 +T714C 002:234.652 JLINK_WriteReg(R6, 0x00000000) +T714C 002:234.668 - 0.015ms returns 0 +T714C 002:234.694 JLINK_WriteReg(R7, 0x00000000) +T714C 002:234.710 - 0.015ms returns 0 +T714C 002:234.726 JLINK_WriteReg(R8, 0x00000000) +T714C 002:234.742 - 0.016ms returns 0 +T714C 002:234.758 JLINK_WriteReg(R9, 0x30500458) +T714C 002:234.774 - 0.016ms returns 0 +T714C 002:234.790 JLINK_WriteReg(R10, 0x00000000) +T714C 002:234.806 - 0.015ms returns 0 +T714C 002:234.821 JLINK_WriteReg(R11, 0x00000000) +T714C 002:234.838 - 0.016ms returns 0 +T714C 002:234.854 JLINK_WriteReg(R12, 0x00000000) +T714C 002:234.869 - 0.015ms returns 0 +T714C 002:234.886 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:234.902 - 0.017ms returns 0 +T714C 002:234.919 JLINK_WriteReg(R14, 0x30500001) +T714C 002:234.934 - 0.015ms returns 0 +T714C 002:234.951 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:234.966 - 0.016ms returns 0 +T714C 002:234.982 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:234.998 - 0.015ms returns 0 +T714C 002:235.014 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:235.030 - 0.016ms returns 0 +T714C 002:235.046 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:235.062 - 0.015ms returns 0 +T714C 002:235.077 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:235.093 - 0.015ms returns 0 +T714C 002:235.110 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:235.126 - 0.016ms returns 0x0000006F +T714C 002:235.142 JLINK_Go() +T714C 002:235.160 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:235.468 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:237.678 - 2.535ms +T714C 002:237.727 JLINK_IsHalted() +T714C 002:237.980 - 0.252ms returns FALSE +T714C 002:238.027 JLINK_HasError() +T714C 002:239.619 JLINK_IsHalted() +T714C 002:241.990 - 2.371ms returns TRUE +T714C 002:242.024 JLINK_ReadReg(R15 (PC)) +T714C 002:242.044 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:242.385 - 0.361ms returns 0x30500000 +T714C 002:242.408 JLINK_ClrBPEx(BPHandle = 0x0000006F) +T714C 002:242.426 - 0.018ms returns 0x00 +T714C 002:242.443 JLINK_ReadReg(R0) +T714C 002:242.460 - 0.017ms returns 0x00000000 +T714C 002:243.085 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:243.122 Data: 00 80 D9 F8 00 00 90 F8 2D 00 C0 07 06 D0 46 F2 ... +T714C 002:243.155 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:244.244 - 1.159ms returns 0x100 +T714C 002:244.270 JLINK_HasError() +T714C 002:244.288 JLINK_WriteReg(R0, 0x2800F100) +T714C 002:244.308 - 0.019ms returns 0 +T714C 002:244.324 JLINK_WriteReg(R1, 0x00000100) +T714C 002:244.341 - 0.016ms returns 0 +T714C 002:244.359 JLINK_WriteReg(R2, 0x30500674) +T714C 002:244.375 - 0.016ms returns 0 +T714C 002:244.435 JLINK_WriteReg(R3, 0x00000000) +T714C 002:244.451 - 0.015ms returns 0 +T714C 002:244.475 JLINK_WriteReg(R4, 0x00000000) +T714C 002:244.492 - 0.016ms returns 0 +T714C 002:244.509 JLINK_WriteReg(R5, 0x00000000) +T714C 002:244.525 - 0.016ms returns 0 +T714C 002:244.542 JLINK_WriteReg(R6, 0x00000000) +T714C 002:244.558 - 0.016ms returns 0 +T714C 002:244.575 JLINK_WriteReg(R7, 0x00000000) +T714C 002:244.591 - 0.016ms returns 0 +T714C 002:244.608 JLINK_WriteReg(R8, 0x00000000) +T714C 002:244.624 - 0.016ms returns 0 +T714C 002:244.641 JLINK_WriteReg(R9, 0x30500458) +T714C 002:244.657 - 0.016ms returns 0 +T714C 002:244.674 JLINK_WriteReg(R10, 0x00000000) +T714C 002:244.690 - 0.016ms returns 0 +T714C 002:244.706 JLINK_WriteReg(R11, 0x00000000) +T714C 002:244.723 - 0.016ms returns 0 +T714C 002:244.740 JLINK_WriteReg(R12, 0x00000000) +T714C 002:244.756 - 0.016ms returns 0 +T714C 002:244.773 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:244.791 - 0.018ms returns 0 +T714C 002:244.807 JLINK_WriteReg(R14, 0x30500001) +T714C 002:244.823 - 0.016ms returns 0 +T714C 002:244.840 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:244.857 - 0.017ms returns 0 +T714C 002:244.873 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:244.889 - 0.016ms returns 0 +T714C 002:244.906 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:244.922 - 0.016ms returns 0 +T714C 002:244.938 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:244.954 - 0.016ms returns 0 +T714C 002:244.971 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:244.987 - 0.016ms returns 0 +T714C 002:245.010 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:245.029 - 0.019ms returns 0x00000070 +T714C 002:245.046 JLINK_Go() +T714C 002:245.064 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:245.468 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:247.576 - 2.530ms +T714C 002:247.603 JLINK_IsHalted() +T714C 002:247.933 - 0.329ms returns FALSE +T714C 002:247.955 JLINK_HasError() +T714C 002:249.662 JLINK_IsHalted() +T714C 002:252.256 - 2.594ms returns TRUE +T714C 002:252.316 JLINK_ReadReg(R15 (PC)) +T714C 002:252.338 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:252.818 - 0.501ms returns 0x30500000 +T714C 002:252.866 JLINK_ClrBPEx(BPHandle = 0x00000070) +T714C 002:252.884 - 0.018ms returns 0x00 +T714C 002:252.902 JLINK_ReadReg(R0) +T714C 002:252.920 - 0.018ms returns 0x00000000 +T714C 002:253.538 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:253.570 Data: 89 00 11 FA 80 F1 04 F5 E1 70 04 EB 01 11 50 22 ... +T714C 002:253.600 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:254.839 - 1.300ms returns 0x100 +T714C 002:254.917 JLINK_HasError() +T714C 002:254.937 JLINK_WriteReg(R0, 0x2800F200) +T714C 002:254.960 - 0.022ms returns 0 +T714C 002:254.977 JLINK_WriteReg(R1, 0x00000100) +T714C 002:254.994 - 0.016ms returns 0 +T714C 002:255.010 JLINK_WriteReg(R2, 0x30500674) +T714C 002:255.026 - 0.016ms returns 0 +T714C 002:255.042 JLINK_WriteReg(R3, 0x00000000) +T714C 002:255.058 - 0.016ms returns 0 +T714C 002:255.074 JLINK_WriteReg(R4, 0x00000000) +T714C 002:255.094 - 0.019ms returns 0 +T714C 002:255.110 JLINK_WriteReg(R5, 0x00000000) +T714C 002:255.126 - 0.016ms returns 0 +T714C 002:255.142 JLINK_WriteReg(R6, 0x00000000) +T714C 002:255.158 - 0.015ms returns 0 +T714C 002:255.174 JLINK_WriteReg(R7, 0x00000000) +T714C 002:255.190 - 0.015ms returns 0 +T714C 002:255.206 JLINK_WriteReg(R8, 0x00000000) +T714C 002:255.221 - 0.016ms returns 0 +T714C 002:255.238 JLINK_WriteReg(R9, 0x30500458) +T714C 002:255.254 - 0.016ms returns 0 +T714C 002:255.270 JLINK_WriteReg(R10, 0x00000000) +T714C 002:255.286 - 0.016ms returns 0 +T714C 002:255.302 JLINK_WriteReg(R11, 0x00000000) +T714C 002:255.318 - 0.015ms returns 0 +T714C 002:255.336 JLINK_WriteReg(R12, 0x00000000) +T714C 002:255.352 - 0.016ms returns 0 +T714C 002:255.368 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:255.385 - 0.017ms returns 0 +T714C 002:255.401 JLINK_WriteReg(R14, 0x30500001) +T714C 002:255.417 - 0.015ms returns 0 +T714C 002:255.434 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:255.450 - 0.016ms returns 0 +T714C 002:255.467 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:255.483 - 0.016ms returns 0 +T714C 002:255.499 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:255.515 - 0.015ms returns 0 +T714C 002:255.532 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:255.548 - 0.016ms returns 0 +T714C 002:255.565 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:255.582 - 0.017ms returns 0 +T714C 002:255.599 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:255.617 - 0.018ms returns 0x00000071 +T714C 002:255.635 JLINK_Go() +T714C 002:255.655 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:256.021 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:258.244 - 2.608ms +T714C 002:259.046 JLINK_IsHalted() +T714C 002:261.497 - 2.450ms returns TRUE +T714C 002:261.581 JLINK_ReadReg(R15 (PC)) +T714C 002:261.618 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:261.960 - 0.378ms returns 0x30500000 +T714C 002:262.012 JLINK_ClrBPEx(BPHandle = 0x00000071) +T714C 002:262.030 - 0.018ms returns 0x00 +T714C 002:262.047 JLINK_ReadReg(R0) +T714C 002:262.064 - 0.016ms returns 0x00000000 +T714C 002:262.740 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:262.772 Data: 20 46 29 46 FE F7 5A F9 00 20 06 B0 70 BD 45 F6 ... +T714C 002:262.806 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:263.928 - 1.187ms returns 0x100 +T714C 002:263.977 JLINK_HasError() +T714C 002:263.995 JLINK_WriteReg(R0, 0x2800F300) +T714C 002:264.014 - 0.019ms returns 0 +T714C 002:264.032 JLINK_WriteReg(R1, 0x00000100) +T714C 002:264.049 - 0.016ms returns 0 +T714C 002:264.065 JLINK_WriteReg(R2, 0x30500674) +T714C 002:264.086 - 0.021ms returns 0 +T714C 002:264.105 JLINK_WriteReg(R3, 0x00000000) +T714C 002:264.120 - 0.015ms returns 0 +T714C 002:264.137 JLINK_WriteReg(R4, 0x00000000) +T714C 002:264.152 - 0.015ms returns 0 +T714C 002:264.168 JLINK_WriteReg(R5, 0x00000000) +T714C 002:264.184 - 0.015ms returns 0 +T714C 002:264.200 JLINK_WriteReg(R6, 0x00000000) +T714C 002:264.216 - 0.015ms returns 0 +T714C 002:264.247 JLINK_WriteReg(R7, 0x00000000) +T714C 002:264.263 - 0.015ms returns 0 +T714C 002:264.279 JLINK_WriteReg(R8, 0x00000000) +T714C 002:264.294 - 0.015ms returns 0 +T714C 002:264.311 JLINK_WriteReg(R9, 0x30500458) +T714C 002:264.327 - 0.015ms returns 0 +T714C 002:264.344 JLINK_WriteReg(R10, 0x00000000) +T714C 002:264.360 - 0.016ms returns 0 +T714C 002:264.376 JLINK_WriteReg(R11, 0x00000000) +T714C 002:264.392 - 0.015ms returns 0 +T714C 002:264.408 JLINK_WriteReg(R12, 0x00000000) +T714C 002:264.423 - 0.015ms returns 0 +T714C 002:264.439 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:264.456 - 0.017ms returns 0 +T714C 002:264.472 JLINK_WriteReg(R14, 0x30500001) +T714C 002:264.488 - 0.015ms returns 0 +T714C 002:264.504 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:264.519 - 0.015ms returns 0 +T714C 002:264.535 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:264.551 - 0.015ms returns 0 +T714C 002:264.567 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:264.582 - 0.015ms returns 0 +T714C 002:264.598 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:264.614 - 0.015ms returns 0 +T714C 002:264.630 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:264.645 - 0.015ms returns 0 +T714C 002:264.661 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:264.678 - 0.016ms returns 0x00000072 +T714C 002:264.693 JLINK_Go() +T714C 002:264.715 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:265.158 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:267.451 - 2.756ms +T714C 002:267.505 JLINK_IsHalted() +T714C 002:267.827 - 0.321ms returns FALSE +T714C 002:267.876 JLINK_HasError() +T714C 002:269.838 JLINK_IsHalted() +T714C 002:273.667 - 3.827ms returns TRUE +T714C 002:273.718 JLINK_ReadReg(R15 (PC)) +T714C 002:273.742 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:273.953 - 0.234ms returns 0x30500000 +T714C 002:273.975 JLINK_ClrBPEx(BPHandle = 0x00000072) +T714C 002:273.992 - 0.017ms returns 0x00 +T714C 002:274.009 JLINK_ReadReg(R0) +T714C 002:274.026 - 0.016ms returns 0x00000000 +T714C 002:274.683 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:274.717 Data: 00 28 48 BF 01 F1 0C 03 1A 70 34 F9 04 0C 00 28 ... +T714C 002:274.749 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:275.757 - 1.074ms returns 0x100 +T714C 002:275.782 JLINK_HasError() +T714C 002:275.799 JLINK_WriteReg(R0, 0x2800F400) +T714C 002:275.818 - 0.018ms returns 0 +T714C 002:275.834 JLINK_WriteReg(R1, 0x00000100) +T714C 002:275.854 - 0.020ms returns 0 +T714C 002:275.871 JLINK_WriteReg(R2, 0x30500674) +T714C 002:275.887 - 0.015ms returns 0 +T714C 002:275.903 JLINK_WriteReg(R3, 0x00000000) +T714C 002:275.918 - 0.015ms returns 0 +T714C 002:275.934 JLINK_WriteReg(R4, 0x00000000) +T714C 002:275.950 - 0.016ms returns 0 +T714C 002:275.966 JLINK_WriteReg(R5, 0x00000000) +T714C 002:275.981 - 0.015ms returns 0 +T714C 002:275.998 JLINK_WriteReg(R6, 0x00000000) +T714C 002:276.013 - 0.015ms returns 0 +T714C 002:276.029 JLINK_WriteReg(R7, 0x00000000) +T714C 002:276.044 - 0.015ms returns 0 +T714C 002:276.060 JLINK_WriteReg(R8, 0x00000000) +T714C 002:276.076 - 0.015ms returns 0 +T714C 002:276.092 JLINK_WriteReg(R9, 0x30500458) +T714C 002:276.107 - 0.015ms returns 0 +T714C 002:276.123 JLINK_WriteReg(R10, 0x00000000) +T714C 002:276.139 - 0.015ms returns 0 +T714C 002:276.154 JLINK_WriteReg(R11, 0x00000000) +T714C 002:276.170 - 0.015ms returns 0 +T714C 002:276.187 JLINK_WriteReg(R12, 0x00000000) +T714C 002:276.202 - 0.015ms returns 0 +T714C 002:276.219 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:276.235 - 0.016ms returns 0 +T714C 002:276.277 JLINK_WriteReg(R14, 0x30500001) +T714C 002:276.293 - 0.015ms returns 0 +T714C 002:276.310 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:276.326 - 0.015ms returns 0 +T714C 002:276.349 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:276.365 - 0.016ms returns 0 +T714C 002:276.381 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:276.396 - 0.015ms returns 0 +T714C 002:276.412 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:276.427 - 0.015ms returns 0 +T714C 002:276.443 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:276.458 - 0.015ms returns 0 +T714C 002:276.475 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:276.491 - 0.016ms returns 0x00000073 +T714C 002:276.507 JLINK_Go() +T714C 002:276.525 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:276.776 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:278.592 - 2.084ms +T714C 002:278.614 JLINK_IsHalted() +T714C 002:278.822 - 0.207ms returns FALSE +T714C 002:278.841 JLINK_HasError() +T714C 002:281.696 JLINK_IsHalted() +T714C 002:283.908 - 2.210ms returns TRUE +T714C 002:284.560 JLINK_ReadReg(R15 (PC)) +T714C 002:284.594 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:284.823 - 0.264ms returns 0x30500000 +T714C 002:284.846 JLINK_ClrBPEx(BPHandle = 0x00000073) +T714C 002:284.863 - 0.016ms returns 0x00 +T714C 002:284.883 JLINK_ReadReg(R0) +T714C 002:284.900 - 0.017ms returns 0x00000000 +T714C 002:285.521 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:285.556 Data: 04 F1 04 0A 02 F0 72 FD 04 F1 10 09 00 25 01 E0 ... +T714C 002:285.586 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:286.616 - 1.095ms returns 0x100 +T714C 002:286.640 JLINK_HasError() +T714C 002:286.658 JLINK_WriteReg(R0, 0x2800F500) +T714C 002:286.676 - 0.018ms returns 0 +T714C 002:286.692 JLINK_WriteReg(R1, 0x00000100) +T714C 002:286.709 - 0.016ms returns 0 +T714C 002:286.726 JLINK_WriteReg(R2, 0x30500674) +T714C 002:286.743 - 0.016ms returns 0 +T714C 002:286.759 JLINK_WriteReg(R3, 0x00000000) +T714C 002:286.776 - 0.016ms returns 0 +T714C 002:286.792 JLINK_WriteReg(R4, 0x00000000) +T714C 002:286.808 - 0.016ms returns 0 +T714C 002:286.824 JLINK_WriteReg(R5, 0x00000000) +T714C 002:286.840 - 0.015ms returns 0 +T714C 002:286.856 JLINK_WriteReg(R6, 0x00000000) +T714C 002:286.872 - 0.015ms returns 0 +T714C 002:286.888 JLINK_WriteReg(R7, 0x00000000) +T714C 002:286.904 - 0.015ms returns 0 +T714C 002:286.920 JLINK_WriteReg(R8, 0x00000000) +T714C 002:286.936 - 0.015ms returns 0 +T714C 002:286.952 JLINK_WriteReg(R9, 0x30500458) +T714C 002:286.969 - 0.017ms returns 0 +T714C 002:286.986 JLINK_WriteReg(R10, 0x00000000) +T714C 002:287.001 - 0.015ms returns 0 +T714C 002:287.017 JLINK_WriteReg(R11, 0x00000000) +T714C 002:287.033 - 0.015ms returns 0 +T714C 002:287.049 JLINK_WriteReg(R12, 0x00000000) +T714C 002:287.065 - 0.015ms returns 0 +T714C 002:287.081 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:287.098 - 0.017ms returns 0 +T714C 002:287.114 JLINK_WriteReg(R14, 0x30500001) +T714C 002:287.130 - 0.015ms returns 0 +T714C 002:287.146 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:287.162 - 0.016ms returns 0 +T714C 002:287.179 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:287.194 - 0.015ms returns 0 +T714C 002:287.210 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:287.227 - 0.016ms returns 0 +T714C 002:287.243 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:287.259 - 0.016ms returns 0 +T714C 002:287.275 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:287.291 - 0.016ms returns 0 +T714C 002:287.308 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:287.323 - 0.016ms returns 0x00000074 +T714C 002:287.340 JLINK_Go() +T714C 002:287.357 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:287.579 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:289.443 - 2.103ms +T714C 002:289.467 JLINK_IsHalted() +T714C 002:289.667 - 0.200ms returns FALSE +T714C 002:289.687 JLINK_HasError() +T714C 002:291.526 JLINK_IsHalted() +T714C 002:293.678 - 2.152ms returns TRUE +T714C 002:293.699 JLINK_ReadReg(R15 (PC)) +T714C 002:293.716 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:293.918 - 0.218ms returns 0x30500000 +T714C 002:293.938 JLINK_ClrBPEx(BPHandle = 0x00000074) +T714C 002:293.954 - 0.016ms returns 0x00 +T714C 002:293.971 JLINK_ReadReg(R0) +T714C 002:293.987 - 0.016ms returns 0x00000000 +T714C 002:294.429 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:294.470 Data: 2D 2D 2D 2D 0A 00 00 00 55 6E 6B 6E 6F 77 6E 00 ... +T714C 002:294.500 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:295.532 - 1.102ms returns 0x100 +T714C 002:295.562 JLINK_HasError() +T714C 002:295.579 JLINK_WriteReg(R0, 0x2800F600) +T714C 002:295.597 - 0.017ms returns 0 +T714C 002:295.614 JLINK_WriteReg(R1, 0x00000100) +T714C 002:295.630 - 0.016ms returns 0 +T714C 002:295.647 JLINK_WriteReg(R2, 0x30500674) +T714C 002:295.662 - 0.016ms returns 0 +T714C 002:295.678 JLINK_WriteReg(R3, 0x00000000) +T714C 002:295.695 - 0.016ms returns 0 +T714C 002:295.711 JLINK_WriteReg(R4, 0x00000000) +T714C 002:295.728 - 0.016ms returns 0 +T714C 002:295.744 JLINK_WriteReg(R5, 0x00000000) +T714C 002:295.760 - 0.015ms returns 0 +T714C 002:295.776 JLINK_WriteReg(R6, 0x00000000) +T714C 002:295.792 - 0.015ms returns 0 +T714C 002:295.808 JLINK_WriteReg(R7, 0x00000000) +T714C 002:295.824 - 0.015ms returns 0 +T714C 002:295.840 JLINK_WriteReg(R8, 0x00000000) +T714C 002:295.856 - 0.015ms returns 0 +T714C 002:295.872 JLINK_WriteReg(R9, 0x30500458) +T714C 002:295.888 - 0.016ms returns 0 +T714C 002:295.904 JLINK_WriteReg(R10, 0x00000000) +T714C 002:295.920 - 0.016ms returns 0 +T714C 002:295.936 JLINK_WriteReg(R11, 0x00000000) +T714C 002:295.952 - 0.015ms returns 0 +T714C 002:295.968 JLINK_WriteReg(R12, 0x00000000) +T714C 002:295.983 - 0.015ms returns 0 +T714C 002:296.000 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:296.016 - 0.016ms returns 0 +T714C 002:296.032 JLINK_WriteReg(R14, 0x30500001) +T714C 002:296.048 - 0.015ms returns 0 +T714C 002:296.064 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:296.080 - 0.016ms returns 0 +T714C 002:296.097 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:296.113 - 0.016ms returns 0 +T714C 002:296.129 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:296.144 - 0.015ms returns 0 +T714C 002:296.161 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:296.177 - 0.015ms returns 0 +T714C 002:296.193 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:296.209 - 0.015ms returns 0 +T714C 002:296.225 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:296.241 - 0.016ms returns 0x00000075 +T714C 002:296.257 JLINK_Go() +T714C 002:296.275 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:296.569 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:298.631 - 2.373ms +T714C 002:298.691 JLINK_IsHalted() +T714C 002:298.978 - 0.286ms returns FALSE +T714C 002:299.016 JLINK_HasError() +T714C 002:300.715 JLINK_IsHalted() +T714C 002:303.019 - 2.302ms returns TRUE +T714C 002:303.069 JLINK_ReadReg(R15 (PC)) +T714C 002:303.091 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:303.327 - 0.257ms returns 0x30500000 +T714C 002:303.378 JLINK_ClrBPEx(BPHandle = 0x00000075) +T714C 002:303.398 - 0.019ms returns 0x00 +T714C 002:303.416 JLINK_ReadReg(R0) +T714C 002:303.434 - 0.017ms returns 0x00000000 +T714C 002:304.029 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:304.060 Data: 10 03 55 F8 08 0F AF 68 A8 42 DF D0 4F F0 FF 34 ... +T714C 002:304.090 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:305.204 - 1.174ms returns 0x100 +T714C 002:305.255 JLINK_HasError() +T714C 002:305.272 JLINK_WriteReg(R0, 0x2800F700) +T714C 002:305.292 - 0.019ms returns 0 +T714C 002:305.312 JLINK_WriteReg(R1, 0x00000100) +T714C 002:305.328 - 0.015ms returns 0 +T714C 002:305.345 JLINK_WriteReg(R2, 0x30500674) +T714C 002:305.360 - 0.015ms returns 0 +T714C 002:305.376 JLINK_WriteReg(R3, 0x00000000) +T714C 002:305.391 - 0.015ms returns 0 +T714C 002:305.407 JLINK_WriteReg(R4, 0x00000000) +T714C 002:305.423 - 0.015ms returns 0 +T714C 002:305.439 JLINK_WriteReg(R5, 0x00000000) +T714C 002:305.454 - 0.015ms returns 0 +T714C 002:305.470 JLINK_WriteReg(R6, 0x00000000) +T714C 002:305.486 - 0.015ms returns 0 +T714C 002:305.501 JLINK_WriteReg(R7, 0x00000000) +T714C 002:305.516 - 0.015ms returns 0 +T714C 002:305.532 JLINK_WriteReg(R8, 0x00000000) +T714C 002:305.548 - 0.015ms returns 0 +T714C 002:305.564 JLINK_WriteReg(R9, 0x30500458) +T714C 002:305.580 - 0.015ms returns 0 +T714C 002:305.596 JLINK_WriteReg(R10, 0x00000000) +T714C 002:305.616 - 0.020ms returns 0 +T714C 002:305.634 JLINK_WriteReg(R11, 0x00000000) +T714C 002:305.650 - 0.015ms returns 0 +T714C 002:305.666 JLINK_WriteReg(R12, 0x00000000) +T714C 002:305.681 - 0.015ms returns 0 +T714C 002:305.697 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:305.714 - 0.016ms returns 0 +T714C 002:305.729 JLINK_WriteReg(R14, 0x30500001) +T714C 002:305.745 - 0.015ms returns 0 +T714C 002:305.761 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:305.805 - 0.043ms returns 0 +T714C 002:305.821 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:305.836 - 0.015ms returns 0 +T714C 002:305.852 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:305.867 - 0.015ms returns 0 +T714C 002:305.883 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:305.898 - 0.015ms returns 0 +T714C 002:305.914 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:305.929 - 0.015ms returns 0 +T714C 002:305.946 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:305.962 - 0.016ms returns 0x00000076 +T714C 002:305.978 JLINK_Go() +T714C 002:305.995 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:306.277 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:308.268 - 2.290ms +T714C 002:308.316 JLINK_IsHalted() +T714C 002:308.590 - 0.273ms returns FALSE +T714C 002:308.636 JLINK_HasError() +T714C 002:310.373 JLINK_IsHalted() +T714C 002:312.758 - 2.385ms returns TRUE +T714C 002:312.805 JLINK_ReadReg(R15 (PC)) +T714C 002:312.824 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:313.124 - 0.318ms returns 0x30500000 +T714C 002:313.171 JLINK_ClrBPEx(BPHandle = 0x00000076) +T714C 002:313.189 - 0.017ms returns 0x00 +T714C 002:313.207 JLINK_ReadReg(R0) +T714C 002:313.224 - 0.017ms returns 0x00000000 +T714C 002:313.738 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:313.771 Data: 02 E0 00 BF 00 2E 6E D0 20 46 35 46 00 2E 08 BF ... +T714C 002:313.931 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:314.988 - 1.249ms returns 0x100 +T714C 002:315.072 JLINK_HasError() +T714C 002:315.131 JLINK_WriteReg(R0, 0x2800F800) +T714C 002:315.343 - 0.210ms returns 0 +T714C 002:315.384 JLINK_WriteReg(R1, 0x00000100) +T714C 002:315.404 - 0.019ms returns 0 +T714C 002:315.474 JLINK_WriteReg(R2, 0x30500674) +T714C 002:315.517 - 0.043ms returns 0 +T714C 002:315.609 JLINK_WriteReg(R3, 0x00000000) +T714C 002:315.869 - 0.259ms returns 0 +T714C 002:315.963 JLINK_WriteReg(R4, 0x00000000) +T714C 002:316.050 - 0.086ms returns 0 +T714C 002:316.085 JLINK_WriteReg(R5, 0x00000000) +T714C 002:316.269 - 0.183ms returns 0 +T714C 002:316.407 JLINK_WriteReg(R6, 0x00000000) +T714C 002:316.433 - 0.026ms returns 0 +T714C 002:316.464 JLINK_WriteReg(R7, 0x00000000) +T714C 002:316.483 - 0.018ms returns 0 +T714C 002:316.595 JLINK_WriteReg(R8, 0x00000000) +T714C 002:316.642 - 0.047ms returns 0 +T714C 002:316.761 JLINK_WriteReg(R9, 0x30500458) +T714C 002:316.899 - 0.137ms returns 0 +T714C 002:316.953 JLINK_WriteReg(R10, 0x00000000) +T714C 002:316.984 - 0.031ms returns 0 +T714C 002:317.002 JLINK_WriteReg(R11, 0x00000000) +T714C 002:317.023 - 0.021ms returns 0 +T714C 002:317.071 JLINK_WriteReg(R12, 0x00000000) +T714C 002:317.092 - 0.020ms returns 0 +T714C 002:317.110 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:317.129 - 0.019ms returns 0 +T714C 002:317.158 JLINK_WriteReg(R14, 0x30500001) +T714C 002:317.207 - 0.048ms returns 0 +T714C 002:317.225 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:317.243 - 0.018ms returns 0 +T714C 002:317.261 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:317.281 - 0.020ms returns 0 +T714C 002:317.300 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:317.318 - 0.018ms returns 0 +T714C 002:317.363 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:317.444 - 0.081ms returns 0 +T714C 002:317.521 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:317.646 - 0.124ms returns 0 +T714C 002:317.740 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:317.846 - 0.106ms returns 0x00000077 +T714C 002:317.899 JLINK_Go() +T714C 002:317.945 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:318.526 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:320.435 - 2.535ms +T714C 002:320.489 JLINK_IsHalted() +T714C 002:320.693 - 0.204ms returns FALSE +T714C 002:320.718 JLINK_HasError() +T714C 002:322.344 JLINK_IsHalted() +T714C 002:324.492 - 2.147ms returns TRUE +T714C 002:324.516 JLINK_ReadReg(R15 (PC)) +T714C 002:324.534 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:324.743 - 0.227ms returns 0x30500000 +T714C 002:324.764 JLINK_ClrBPEx(BPHandle = 0x00000077) +T714C 002:324.781 - 0.017ms returns 0x00 +T714C 002:324.798 JLINK_ReadReg(R0) +T714C 002:324.814 - 0.016ms returns 0x00000000 +T714C 002:325.475 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:325.514 Data: 65 20 73 75 73 70 65 6E 64 20 74 68 72 65 61 64 ... +T714C 002:325.545 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:326.632 - 1.156ms returns 0x100 +T714C 002:326.658 JLINK_HasError() +T714C 002:326.677 JLINK_WriteReg(R0, 0x2800F900) +T714C 002:326.695 - 0.018ms returns 0 +T714C 002:326.712 JLINK_WriteReg(R1, 0x00000100) +T714C 002:326.728 - 0.016ms returns 0 +T714C 002:326.744 JLINK_WriteReg(R2, 0x30500674) +T714C 002:326.760 - 0.016ms returns 0 +T714C 002:326.777 JLINK_WriteReg(R3, 0x00000000) +T714C 002:326.794 - 0.016ms returns 0 +T714C 002:326.811 JLINK_WriteReg(R4, 0x00000000) +T714C 002:326.827 - 0.016ms returns 0 +T714C 002:326.844 JLINK_WriteReg(R5, 0x00000000) +T714C 002:326.860 - 0.016ms returns 0 +T714C 002:326.877 JLINK_WriteReg(R6, 0x00000000) +T714C 002:326.892 - 0.016ms returns 0 +T714C 002:326.909 JLINK_WriteReg(R7, 0x00000000) +T714C 002:326.924 - 0.015ms returns 0 +T714C 002:326.941 JLINK_WriteReg(R8, 0x00000000) +T714C 002:326.957 - 0.016ms returns 0 +T714C 002:326.973 JLINK_WriteReg(R9, 0x30500458) +T714C 002:326.989 - 0.015ms returns 0 +T714C 002:327.005 JLINK_WriteReg(R10, 0x00000000) +T714C 002:327.021 - 0.016ms returns 0 +T714C 002:327.037 JLINK_WriteReg(R11, 0x00000000) +T714C 002:327.053 - 0.016ms returns 0 +T714C 002:327.069 JLINK_WriteReg(R12, 0x00000000) +T714C 002:327.085 - 0.015ms returns 0 +T714C 002:327.102 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:327.119 - 0.017ms returns 0 +T714C 002:327.136 JLINK_WriteReg(R14, 0x30500001) +T714C 002:327.151 - 0.015ms returns 0 +T714C 002:327.168 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:327.184 - 0.015ms returns 0 +T714C 002:327.200 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:327.216 - 0.015ms returns 0 +T714C 002:327.232 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:327.248 - 0.016ms returns 0 +T714C 002:327.264 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:327.280 - 0.016ms returns 0 +T714C 002:327.296 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:327.312 - 0.015ms returns 0 +T714C 002:327.328 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:327.344 - 0.016ms returns 0x00000078 +T714C 002:327.360 JLINK_Go() +T714C 002:327.378 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:327.661 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:329.495 - 2.133ms +T714C 002:329.538 JLINK_IsHalted() +T714C 002:329.826 - 0.288ms returns FALSE +T714C 002:329.851 JLINK_HasError() +T714C 002:331.034 JLINK_IsHalted() +T714C 002:333.141 - 2.105ms returns TRUE +T714C 002:333.198 JLINK_ReadReg(R15 (PC)) +T714C 002:333.222 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:333.456 - 0.258ms returns 0x30500000 +T714C 002:333.478 JLINK_ClrBPEx(BPHandle = 0x00000078) +T714C 002:333.496 - 0.017ms returns 0x00 +T714C 002:333.513 JLINK_ReadReg(R0) +T714C 002:333.529 - 0.016ms returns 0x00000000 +T714C 002:334.159 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:334.195 Data: D4 DB 4F F0 00 09 0D E0 CD E9 01 21 03 90 3C A0 ... +T714C 002:334.227 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:335.231 - 1.072ms returns 0x100 +T714C 002:335.861 JLINK_HasError() +T714C 002:335.883 JLINK_WriteReg(R0, 0x2800FA00) +T714C 002:335.902 - 0.019ms returns 0 +T714C 002:335.919 JLINK_WriteReg(R1, 0x00000100) +T714C 002:335.935 - 0.016ms returns 0 +T714C 002:335.952 JLINK_WriteReg(R2, 0x30500674) +T714C 002:335.968 - 0.016ms returns 0 +T714C 002:335.984 JLINK_WriteReg(R3, 0x00000000) +T714C 002:336.001 - 0.016ms returns 0 +T714C 002:336.017 JLINK_WriteReg(R4, 0x00000000) +T714C 002:336.033 - 0.016ms returns 0 +T714C 002:336.056 JLINK_WriteReg(R5, 0x00000000) +T714C 002:336.075 - 0.018ms returns 0 +T714C 002:336.092 JLINK_WriteReg(R6, 0x00000000) +T714C 002:336.108 - 0.015ms returns 0 +T714C 002:336.124 JLINK_WriteReg(R7, 0x00000000) +T714C 002:336.142 - 0.017ms returns 0 +T714C 002:336.158 JLINK_WriteReg(R8, 0x00000000) +T714C 002:336.174 - 0.015ms returns 0 +T714C 002:336.190 JLINK_WriteReg(R9, 0x30500458) +T714C 002:336.206 - 0.015ms returns 0 +T714C 002:336.222 JLINK_WriteReg(R10, 0x00000000) +T714C 002:336.238 - 0.016ms returns 0 +T714C 002:336.255 JLINK_WriteReg(R11, 0x00000000) +T714C 002:336.271 - 0.016ms returns 0 +T714C 002:336.287 JLINK_WriteReg(R12, 0x00000000) +T714C 002:336.303 - 0.016ms returns 0 +T714C 002:336.319 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:336.336 - 0.017ms returns 0 +T714C 002:336.353 JLINK_WriteReg(R14, 0x30500001) +T714C 002:336.368 - 0.015ms returns 0 +T714C 002:336.384 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:336.400 - 0.015ms returns 0 +T714C 002:336.417 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:336.432 - 0.015ms returns 0 +T714C 002:336.448 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:336.464 - 0.015ms returns 0 +T714C 002:336.480 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:336.496 - 0.016ms returns 0 +T714C 002:336.512 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:336.528 - 0.015ms returns 0 +T714C 002:336.546 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:336.562 - 0.016ms returns 0x00000079 +T714C 002:336.579 JLINK_Go() +T714C 002:336.597 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:336.832 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:338.663 - 2.083ms +T714C 002:338.686 JLINK_IsHalted() +T714C 002:338.896 - 0.209ms returns FALSE +T714C 002:338.916 JLINK_HasError() +T714C 002:340.055 JLINK_IsHalted() +T714C 002:342.275 - 2.221ms returns TRUE +T714C 002:342.297 JLINK_ReadReg(R15 (PC)) +T714C 002:342.314 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:342.540 - 0.243ms returns 0x30500000 +T714C 002:342.560 JLINK_ClrBPEx(BPHandle = 0x00000079) +T714C 002:342.577 - 0.016ms returns 0x00 +T714C 002:342.594 JLINK_ReadReg(R0) +T714C 002:342.610 - 0.016ms returns 0x00000000 +T714C 002:343.072 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:343.107 Data: 25 2D 2A 2E 2A 73 20 25 30 34 64 20 20 25 30 34 ... +T714C 002:343.136 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:344.198 - 1.125ms returns 0x100 +T714C 002:344.242 JLINK_HasError() +T714C 002:344.270 JLINK_WriteReg(R0, 0x2800FB00) +T714C 002:344.299 - 0.029ms returns 0 +T714C 002:344.323 JLINK_WriteReg(R1, 0x00000100) +T714C 002:344.348 - 0.025ms returns 0 +T714C 002:344.377 JLINK_WriteReg(R2, 0x30500674) +T714C 002:344.407 - 0.029ms returns 0 +T714C 002:344.431 JLINK_WriteReg(R3, 0x00000000) +T714C 002:344.456 - 0.026ms returns 0 +T714C 002:344.481 JLINK_WriteReg(R4, 0x00000000) +T714C 002:344.507 - 0.025ms returns 0 +T714C 002:344.532 JLINK_WriteReg(R5, 0x00000000) +T714C 002:344.611 - 0.078ms returns 0 +T714C 002:344.644 JLINK_WriteReg(R6, 0x00000000) +T714C 002:344.672 - 0.028ms returns 0 +T714C 002:344.698 JLINK_WriteReg(R7, 0x00000000) +T714C 002:344.723 - 0.024ms returns 0 +T714C 002:344.748 JLINK_WriteReg(R8, 0x00000000) +T714C 002:344.773 - 0.025ms returns 0 +T714C 002:344.797 JLINK_WriteReg(R9, 0x30500458) +T714C 002:344.822 - 0.024ms returns 0 +T714C 002:344.845 JLINK_WriteReg(R10, 0x00000000) +T714C 002:344.872 - 0.027ms returns 0 +T714C 002:344.897 JLINK_WriteReg(R11, 0x00000000) +T714C 002:344.921 - 0.024ms returns 0 +T714C 002:344.944 JLINK_WriteReg(R12, 0x00000000) +T714C 002:344.967 - 0.022ms returns 0 +T714C 002:344.990 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:345.017 - 0.026ms returns 0 +T714C 002:345.042 JLINK_WriteReg(R14, 0x30500001) +T714C 002:345.067 - 0.025ms returns 0 +T714C 002:345.092 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:345.117 - 0.025ms returns 0 +T714C 002:345.144 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:345.173 - 0.028ms returns 0 +T714C 002:345.198 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:345.223 - 0.024ms returns 0 +T714C 002:345.248 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:345.278 - 0.030ms returns 0 +T714C 002:345.302 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:345.325 - 0.023ms returns 0 +T714C 002:345.349 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:345.373 - 0.024ms returns 0x0000007A +T714C 002:345.396 JLINK_Go() +T714C 002:345.430 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:345.708 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:347.779 - 2.382ms +T714C 002:347.830 JLINK_IsHalted() +T714C 002:348.085 - 0.254ms returns FALSE +T714C 002:348.134 JLINK_HasError() +T714C 002:350.116 JLINK_IsHalted() +T714C 002:352.450 - 2.334ms returns TRUE +T714C 002:352.498 JLINK_ReadReg(R15 (PC)) +T714C 002:352.520 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:352.748 - 0.249ms returns 0x30500000 +T714C 002:352.795 JLINK_ClrBPEx(BPHandle = 0x0000007A) +T714C 002:352.812 - 0.018ms returns 0x00 +T714C 002:352.830 JLINK_ReadReg(R0) +T714C 002:352.847 - 0.017ms returns 0x00000000 +T714C 002:353.453 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:353.487 Data: 00 68 01 34 A8 42 FB D1 1E A0 0C 21 0C 22 CD E9 ... +T714C 002:353.517 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:354.610 - 1.156ms returns 0x100 +T714C 002:354.657 JLINK_HasError() +T714C 002:354.675 JLINK_WriteReg(R0, 0x2800FC00) +T714C 002:354.694 - 0.018ms returns 0 +T714C 002:354.710 JLINK_WriteReg(R1, 0x00000100) +T714C 002:354.725 - 0.015ms returns 0 +T714C 002:354.742 JLINK_WriteReg(R2, 0x30500674) +T714C 002:354.758 - 0.016ms returns 0 +T714C 002:354.774 JLINK_WriteReg(R3, 0x00000000) +T714C 002:354.789 - 0.015ms returns 0 +T714C 002:354.805 JLINK_WriteReg(R4, 0x00000000) +T714C 002:354.821 - 0.015ms returns 0 +T714C 002:354.837 JLINK_WriteReg(R5, 0x00000000) +T714C 002:354.852 - 0.015ms returns 0 +T714C 002:354.868 JLINK_WriteReg(R6, 0x00000000) +T714C 002:354.884 - 0.015ms returns 0 +T714C 002:354.899 JLINK_WriteReg(R7, 0x00000000) +T714C 002:354.915 - 0.015ms returns 0 +T714C 002:354.931 JLINK_WriteReg(R8, 0x00000000) +T714C 002:354.947 - 0.015ms returns 0 +T714C 002:354.962 JLINK_WriteReg(R9, 0x30500458) +T714C 002:354.978 - 0.015ms returns 0 +T714C 002:354.994 JLINK_WriteReg(R10, 0x00000000) +T714C 002:355.010 - 0.015ms returns 0 +T714C 002:355.026 JLINK_WriteReg(R11, 0x00000000) +T714C 002:355.043 - 0.016ms returns 0 +T714C 002:355.059 JLINK_WriteReg(R12, 0x00000000) +T714C 002:355.074 - 0.015ms returns 0 +T714C 002:355.090 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:355.106 - 0.016ms returns 0 +T714C 002:355.122 JLINK_WriteReg(R14, 0x30500001) +T714C 002:355.137 - 0.015ms returns 0 +T714C 002:355.154 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:355.169 - 0.015ms returns 0 +T714C 002:355.185 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:355.200 - 0.015ms returns 0 +T714C 002:355.216 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:355.232 - 0.015ms returns 0 +T714C 002:355.247 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:355.263 - 0.015ms returns 0 +T714C 002:355.278 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:355.294 - 0.015ms returns 0 +T714C 002:355.310 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:355.326 - 0.016ms returns 0x0000007B +T714C 002:355.343 JLINK_Go() +T714C 002:355.361 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:355.714 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:357.784 - 2.441ms +T714C 002:357.832 JLINK_IsHalted() +T714C 002:358.075 - 0.243ms returns FALSE +T714C 002:358.122 JLINK_HasError() +T714C 002:360.586 JLINK_IsHalted() +T714C 002:362.813 - 2.226ms returns TRUE +T714C 002:363.464 JLINK_ReadReg(R15 (PC)) +T714C 002:363.488 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:363.696 - 0.231ms returns 0x30500000 +T714C 002:363.716 JLINK_ClrBPEx(BPHandle = 0x0000007B) +T714C 002:363.732 - 0.016ms returns 0x00 +T714C 002:363.748 JLINK_ReadReg(R0) +T714C 002:363.765 - 0.016ms returns 0x00000000 +T714C 002:364.319 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:364.352 Data: 8F 80 20 46 4D 46 B9 F1 00 0F 08 BF B1 46 04 F0 ... +T714C 002:364.383 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:365.324 - 1.004ms returns 0x100 +T714C 002:365.373 JLINK_HasError() +T714C 002:365.393 JLINK_WriteReg(R0, 0x2800FD00) +T714C 002:365.412 - 0.019ms returns 0 +T714C 002:365.429 JLINK_WriteReg(R1, 0x00000100) +T714C 002:365.445 - 0.016ms returns 0 +T714C 002:365.462 JLINK_WriteReg(R2, 0x30500674) +T714C 002:365.478 - 0.016ms returns 0 +T714C 002:365.494 JLINK_WriteReg(R3, 0x00000000) +T714C 002:365.510 - 0.016ms returns 0 +T714C 002:365.527 JLINK_WriteReg(R4, 0x00000000) +T714C 002:365.543 - 0.016ms returns 0 +T714C 002:365.560 JLINK_WriteReg(R5, 0x00000000) +T714C 002:365.576 - 0.016ms returns 0 +T714C 002:365.592 JLINK_WriteReg(R6, 0x00000000) +T714C 002:365.608 - 0.016ms returns 0 +T714C 002:365.625 JLINK_WriteReg(R7, 0x00000000) +T714C 002:365.641 - 0.015ms returns 0 +T714C 002:365.657 JLINK_WriteReg(R8, 0x00000000) +T714C 002:365.673 - 0.016ms returns 0 +T714C 002:365.689 JLINK_WriteReg(R9, 0x30500458) +T714C 002:365.705 - 0.016ms returns 0 +T714C 002:365.723 JLINK_WriteReg(R10, 0x00000000) +T714C 002:365.739 - 0.016ms returns 0 +T714C 002:365.755 JLINK_WriteReg(R11, 0x00000000) +T714C 002:365.772 - 0.016ms returns 0 +T714C 002:365.789 JLINK_WriteReg(R12, 0x00000000) +T714C 002:365.805 - 0.015ms returns 0 +T714C 002:365.821 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:365.838 - 0.017ms returns 0 +T714C 002:365.855 JLINK_WriteReg(R14, 0x30500001) +T714C 002:365.872 - 0.016ms returns 0 +T714C 002:365.888 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:365.905 - 0.016ms returns 0 +T714C 002:365.922 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:365.938 - 0.016ms returns 0 +T714C 002:365.955 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:365.971 - 0.016ms returns 0 +T714C 002:365.988 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:366.004 - 0.016ms returns 0 +T714C 002:366.021 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:366.037 - 0.016ms returns 0 +T714C 002:366.054 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:366.070 - 0.016ms returns 0x0000007C +T714C 002:366.087 JLINK_Go() +T714C 002:366.105 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:366.332 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:368.199 - 2.111ms +T714C 002:368.224 JLINK_IsHalted() +T714C 002:368.417 - 0.192ms returns FALSE +T714C 002:368.437 JLINK_HasError() +T714C 002:369.740 JLINK_IsHalted() +T714C 002:371.854 - 2.114ms returns TRUE +T714C 002:371.876 JLINK_ReadReg(R15 (PC)) +T714C 002:371.893 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:372.156 - 0.280ms returns 0x30500000 +T714C 002:372.177 JLINK_ClrBPEx(BPHandle = 0x0000007C) +T714C 002:372.194 - 0.016ms returns 0x00 +T714C 002:372.210 JLINK_ReadReg(R0) +T714C 002:372.226 - 0.016ms returns 0x00000000 +T714C 002:372.750 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:372.781 Data: 2A 46 0C 25 CD E9 02 10 45 F6 27 60 CD E9 00 52 ... +T714C 002:372.812 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:373.824 - 1.073ms returns 0x100 +T714C 002:373.891 JLINK_HasError() +T714C 002:373.917 JLINK_WriteReg(R0, 0x2800FE00) +T714C 002:373.960 - 0.043ms returns 0 +T714C 002:373.983 JLINK_WriteReg(R1, 0x00000100) +T714C 002:374.007 - 0.024ms returns 0 +T714C 002:374.036 JLINK_WriteReg(R2, 0x30500674) +T714C 002:374.061 - 0.025ms returns 0 +T714C 002:374.085 JLINK_WriteReg(R3, 0x00000000) +T714C 002:374.108 - 0.023ms returns 0 +T714C 002:374.133 JLINK_WriteReg(R4, 0x00000000) +T714C 002:374.155 - 0.021ms returns 0 +T714C 002:374.179 JLINK_WriteReg(R5, 0x00000000) +T714C 002:374.197 - 0.018ms returns 0 +T714C 002:374.220 JLINK_WriteReg(R6, 0x00000000) +T714C 002:374.238 - 0.017ms returns 0 +T714C 002:374.264 JLINK_WriteReg(R7, 0x00000000) +T714C 002:374.280 - 0.016ms returns 0 +T714C 002:374.303 JLINK_WriteReg(R8, 0x00000000) +T714C 002:374.324 - 0.021ms returns 0 +T714C 002:374.348 JLINK_WriteReg(R9, 0x30500458) +T714C 002:374.370 - 0.022ms returns 0 +T714C 002:374.394 JLINK_WriteReg(R10, 0x00000000) +T714C 002:374.416 - 0.021ms returns 0 +T714C 002:374.438 JLINK_WriteReg(R11, 0x00000000) +T714C 002:374.462 - 0.024ms returns 0 +T714C 002:374.489 JLINK_WriteReg(R12, 0x00000000) +T714C 002:374.514 - 0.025ms returns 0 +T714C 002:374.549 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:374.578 - 0.029ms returns 0 +T714C 002:374.602 JLINK_WriteReg(R14, 0x30500001) +T714C 002:374.626 - 0.024ms returns 0 +T714C 002:374.650 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:374.673 - 0.023ms returns 0 +T714C 002:374.696 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:374.720 - 0.023ms returns 0 +T714C 002:374.746 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:374.771 - 0.024ms returns 0 +T714C 002:374.810 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:374.834 - 0.024ms returns 0 +T714C 002:374.859 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:374.884 - 0.024ms returns 0 +T714C 002:374.910 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:374.938 - 0.028ms returns 0x0000007D +T714C 002:374.964 JLINK_Go() +T714C 002:374.990 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:375.343 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:377.212 - 2.246ms +T714C 002:377.266 JLINK_IsHalted() +T714C 002:377.560 - 0.294ms returns FALSE +T714C 002:377.584 JLINK_HasError() +T714C 002:379.669 JLINK_IsHalted() +T714C 002:381.884 - 2.214ms returns TRUE +T714C 002:381.932 JLINK_ReadReg(R15 (PC)) +T714C 002:381.953 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:382.322 - 0.388ms returns 0x30500000 +T714C 002:382.372 JLINK_ClrBPEx(BPHandle = 0x0000007D) +T714C 002:382.390 - 0.017ms returns 0x00 +T714C 002:382.408 JLINK_ReadReg(R0) +T714C 002:382.425 - 0.017ms returns 0x00000000 +T714C 002:383.123 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:383.159 Data: 4F F0 00 08 36 68 AE 42 12 D0 4A F8 28 60 08 F1 ... +T714C 002:383.201 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:384.337 - 1.214ms returns 0x100 +T714C 002:384.363 JLINK_HasError() +T714C 002:384.381 JLINK_WriteReg(R0, 0x2800FF00) +T714C 002:384.399 - 0.018ms returns 0 +T714C 002:384.416 JLINK_WriteReg(R1, 0x00000100) +T714C 002:384.432 - 0.016ms returns 0 +T714C 002:384.449 JLINK_WriteReg(R2, 0x30500674) +T714C 002:384.465 - 0.016ms returns 0 +T714C 002:384.482 JLINK_WriteReg(R3, 0x00000000) +T714C 002:384.498 - 0.015ms returns 0 +T714C 002:384.514 JLINK_WriteReg(R4, 0x00000000) +T714C 002:384.530 - 0.016ms returns 0 +T714C 002:384.547 JLINK_WriteReg(R5, 0x00000000) +T714C 002:384.563 - 0.016ms returns 0 +T714C 002:384.579 JLINK_WriteReg(R6, 0x00000000) +T714C 002:384.595 - 0.016ms returns 0 +T714C 002:384.611 JLINK_WriteReg(R7, 0x00000000) +T714C 002:384.627 - 0.015ms returns 0 +T714C 002:384.644 JLINK_WriteReg(R8, 0x00000000) +T714C 002:384.660 - 0.016ms returns 0 +T714C 002:384.676 JLINK_WriteReg(R9, 0x30500458) +T714C 002:384.693 - 0.016ms returns 0 +T714C 002:384.709 JLINK_WriteReg(R10, 0x00000000) +T714C 002:384.726 - 0.016ms returns 0 +T714C 002:384.742 JLINK_WriteReg(R11, 0x00000000) +T714C 002:384.759 - 0.016ms returns 0 +T714C 002:384.775 JLINK_WriteReg(R12, 0x00000000) +T714C 002:384.791 - 0.015ms returns 0 +T714C 002:384.808 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:384.825 - 0.017ms returns 0 +T714C 002:384.841 JLINK_WriteReg(R14, 0x30500001) +T714C 002:384.858 - 0.016ms returns 0 +T714C 002:384.874 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:384.890 - 0.016ms returns 0 +T714C 002:384.906 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:384.922 - 0.015ms returns 0 +T714C 002:384.938 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:384.954 - 0.015ms returns 0 +T714C 002:384.970 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:384.986 - 0.016ms returns 0 +T714C 002:385.002 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:385.018 - 0.015ms returns 0 +T714C 002:385.034 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:385.051 - 0.016ms returns 0x0000007E +T714C 002:385.067 JLINK_Go() +T714C 002:385.086 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:385.489 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:387.743 - 2.675ms +T714C 002:387.774 JLINK_IsHalted() +T714C 002:388.101 - 0.326ms returns FALSE +T714C 002:388.122 JLINK_HasError() +T714C 002:390.081 JLINK_IsHalted() +T714C 002:392.454 - 2.373ms returns TRUE +T714C 002:392.498 JLINK_ReadReg(R15 (PC)) +T714C 002:392.517 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:392.761 - 0.263ms returns 0x30500000 +T714C 002:392.809 JLINK_ClrBPEx(BPHandle = 0x0000007E) +T714C 002:392.827 - 0.018ms returns 0x00 +T714C 002:392.844 JLINK_ReadReg(R0) +T714C 002:392.862 - 0.017ms returns 0x00000000 +T714C 002:393.412 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:393.444 Data: 2D 2D 2D 2D 2D 2D 2D 0A 00 00 00 00 25 2D 2A 2E ... +T714C 002:393.474 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:394.532 - 1.120ms returns 0x100 +T714C 002:394.556 JLINK_HasError() +T714C 002:394.574 JLINK_WriteReg(R0, 0x28010000) +T714C 002:394.592 - 0.018ms returns 0 +T714C 002:394.609 JLINK_WriteReg(R1, 0x00000100) +T714C 002:394.625 - 0.016ms returns 0 +T714C 002:394.645 JLINK_WriteReg(R2, 0x30500674) +T714C 002:394.661 - 0.016ms returns 0 +T714C 002:394.678 JLINK_WriteReg(R3, 0x00000000) +T714C 002:394.694 - 0.015ms returns 0 +T714C 002:394.710 JLINK_WriteReg(R4, 0x00000000) +T714C 002:394.726 - 0.015ms returns 0 +T714C 002:394.742 JLINK_WriteReg(R5, 0x00000000) +T714C 002:394.758 - 0.016ms returns 0 +T714C 002:394.774 JLINK_WriteReg(R6, 0x00000000) +T714C 002:394.790 - 0.015ms returns 0 +T714C 002:394.806 JLINK_WriteReg(R7, 0x00000000) +T714C 002:394.822 - 0.015ms returns 0 +T714C 002:394.838 JLINK_WriteReg(R8, 0x00000000) +T714C 002:394.854 - 0.015ms returns 0 +T714C 002:394.870 JLINK_WriteReg(R9, 0x30500458) +T714C 002:394.886 - 0.015ms returns 0 +T714C 002:394.902 JLINK_WriteReg(R10, 0x00000000) +T714C 002:394.918 - 0.015ms returns 0 +T714C 002:394.934 JLINK_WriteReg(R11, 0x00000000) +T714C 002:394.950 - 0.015ms returns 0 +T714C 002:394.966 JLINK_WriteReg(R12, 0x00000000) +T714C 002:394.982 - 0.015ms returns 0 +T714C 002:394.998 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:395.015 - 0.016ms returns 0 +T714C 002:395.031 JLINK_WriteReg(R14, 0x30500001) +T714C 002:395.046 - 0.015ms returns 0 +T714C 002:395.063 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:395.079 - 0.016ms returns 0 +T714C 002:395.095 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:395.111 - 0.015ms returns 0 +T714C 002:395.127 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:395.143 - 0.015ms returns 0 +T714C 002:395.159 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:395.175 - 0.015ms returns 0 +T714C 002:395.191 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:395.207 - 0.016ms returns 0 +T714C 002:395.224 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:395.265 - 0.041ms returns 0x0000007F +T714C 002:395.281 JLINK_Go() +T714C 002:395.299 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:395.594 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:397.513 - 2.231ms +T714C 002:397.535 JLINK_IsHalted() +T714C 002:397.776 - 0.240ms returns FALSE +T714C 002:397.795 JLINK_HasError() +T714C 002:399.442 JLINK_IsHalted() +T714C 002:401.791 - 2.349ms returns TRUE +T714C 002:401.821 JLINK_ReadReg(R15 (PC)) +T714C 002:401.841 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:402.242 - 0.420ms returns 0x30500000 +T714C 002:402.263 JLINK_ClrBPEx(BPHandle = 0x0000007F) +T714C 002:402.280 - 0.016ms returns 0x00 +T714C 002:402.297 JLINK_ReadReg(R0) +T714C 002:402.314 - 0.017ms returns 0x00000000 +T714C 002:402.858 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:402.891 Data: 47 F8 28 A0 08 F1 01 08 B8 F1 08 0F F4 D1 4F F0 ... +T714C 002:402.921 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:404.065 - 1.206ms returns 0x100 +T714C 002:404.102 JLINK_HasError() +T714C 002:404.120 JLINK_WriteReg(R0, 0x28010100) +T714C 002:404.139 - 0.018ms returns 0 +T714C 002:404.156 JLINK_WriteReg(R1, 0x00000100) +T714C 002:404.172 - 0.016ms returns 0 +T714C 002:404.189 JLINK_WriteReg(R2, 0x30500674) +T714C 002:404.206 - 0.016ms returns 0 +T714C 002:404.223 JLINK_WriteReg(R3, 0x00000000) +T714C 002:404.239 - 0.016ms returns 0 +T714C 002:404.255 JLINK_WriteReg(R4, 0x00000000) +T714C 002:404.271 - 0.015ms returns 0 +T714C 002:404.288 JLINK_WriteReg(R5, 0x00000000) +T714C 002:404.304 - 0.016ms returns 0 +T714C 002:404.320 JLINK_WriteReg(R6, 0x00000000) +T714C 002:404.336 - 0.015ms returns 0 +T714C 002:404.352 JLINK_WriteReg(R7, 0x00000000) +T714C 002:404.373 - 0.020ms returns 0 +T714C 002:404.390 JLINK_WriteReg(R8, 0x00000000) +T714C 002:404.406 - 0.016ms returns 0 +T714C 002:404.423 JLINK_WriteReg(R9, 0x30500458) +T714C 002:404.439 - 0.016ms returns 0 +T714C 002:404.455 JLINK_WriteReg(R10, 0x00000000) +T714C 002:404.471 - 0.015ms returns 0 +T714C 002:404.487 JLINK_WriteReg(R11, 0x00000000) +T714C 002:404.503 - 0.015ms returns 0 +T714C 002:404.519 JLINK_WriteReg(R12, 0x00000000) +T714C 002:404.535 - 0.016ms returns 0 +T714C 002:404.588 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:404.605 - 0.017ms returns 0 +T714C 002:404.622 JLINK_WriteReg(R14, 0x30500001) +T714C 002:404.637 - 0.015ms returns 0 +T714C 002:404.654 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:404.670 - 0.016ms returns 0 +T714C 002:404.686 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:404.702 - 0.016ms returns 0 +T714C 002:404.719 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:404.736 - 0.016ms returns 0 +T714C 002:404.751 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:404.767 - 0.015ms returns 0 +T714C 002:404.783 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:404.799 - 0.016ms returns 0 +T714C 002:404.816 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:404.833 - 0.016ms returns 0x00000080 +T714C 002:404.849 JLINK_Go() +T714C 002:404.867 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:405.119 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:407.028 - 2.178ms +T714C 002:407.070 JLINK_IsHalted() +T714C 002:407.339 - 0.269ms returns FALSE +T714C 002:407.364 JLINK_HasError() +T714C 002:409.125 JLINK_IsHalted() +T714C 002:411.294 - 2.168ms returns TRUE +T714C 002:411.320 JLINK_ReadReg(R15 (PC)) +T714C 002:411.337 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:411.601 - 0.281ms returns 0x30500000 +T714C 002:411.624 JLINK_ClrBPEx(BPHandle = 0x00000080) +T714C 002:411.640 - 0.016ms returns 0x00 +T714C 002:411.657 JLINK_ReadReg(R0) +T714C 002:411.673 - 0.016ms returns 0x00000000 +T714C 002:412.205 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:412.240 Data: F0 8F 00 BF 20 2D 2D 2D 20 20 2D 2D 2D 2D 2D 2D ... +T714C 002:412.269 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:413.346 - 1.141ms returns 0x100 +T714C 002:413.395 JLINK_HasError() +T714C 002:413.412 JLINK_WriteReg(R0, 0x28010200) +T714C 002:413.432 - 0.019ms returns 0 +T714C 002:413.448 JLINK_WriteReg(R1, 0x00000100) +T714C 002:413.465 - 0.016ms returns 0 +T714C 002:413.482 JLINK_WriteReg(R2, 0x30500674) +T714C 002:413.497 - 0.015ms returns 0 +T714C 002:413.513 JLINK_WriteReg(R3, 0x00000000) +T714C 002:413.529 - 0.015ms returns 0 +T714C 002:413.545 JLINK_WriteReg(R4, 0x00000000) +T714C 002:413.561 - 0.016ms returns 0 +T714C 002:413.577 JLINK_WriteReg(R5, 0x00000000) +T714C 002:413.592 - 0.015ms returns 0 +T714C 002:413.609 JLINK_WriteReg(R6, 0x00000000) +T714C 002:413.624 - 0.015ms returns 0 +T714C 002:413.640 JLINK_WriteReg(R7, 0x00000000) +T714C 002:413.657 - 0.017ms returns 0 +T714C 002:413.674 JLINK_WriteReg(R8, 0x00000000) +T714C 002:413.689 - 0.015ms returns 0 +T714C 002:413.705 JLINK_WriteReg(R9, 0x30500458) +T714C 002:413.720 - 0.015ms returns 0 +T714C 002:413.737 JLINK_WriteReg(R10, 0x00000000) +T714C 002:413.752 - 0.015ms returns 0 +T714C 002:413.768 JLINK_WriteReg(R11, 0x00000000) +T714C 002:413.784 - 0.015ms returns 0 +T714C 002:413.801 JLINK_WriteReg(R12, 0x00000000) +T714C 002:413.816 - 0.015ms returns 0 +T714C 002:413.832 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:413.849 - 0.016ms returns 0 +T714C 002:413.865 JLINK_WriteReg(R14, 0x30500001) +T714C 002:413.881 - 0.015ms returns 0 +T714C 002:413.896 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:413.912 - 0.015ms returns 0 +T714C 002:413.928 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:413.943 - 0.015ms returns 0 +T714C 002:413.959 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:413.975 - 0.015ms returns 0 +T714C 002:413.991 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:414.006 - 0.015ms returns 0 +T714C 002:414.022 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:414.038 - 0.015ms returns 0 +T714C 002:414.054 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:414.074 - 0.020ms returns 0x00000081 +T714C 002:414.093 JLINK_Go() +T714C 002:414.110 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:414.400 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:416.536 - 2.442ms +T714C 002:417.256 JLINK_IsHalted() +T714C 002:419.519 - 2.263ms returns TRUE +T714C 002:419.567 JLINK_ReadReg(R15 (PC)) +T714C 002:419.588 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:419.813 - 0.246ms returns 0x30500000 +T714C 002:419.837 JLINK_ClrBPEx(BPHandle = 0x00000081) +T714C 002:419.855 - 0.017ms returns 0x00 +T714C 002:419.876 JLINK_ReadReg(R0) +T714C 002:419.891 - 0.015ms returns 0x00000000 +T714C 002:420.626 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:420.665 Data: 00 0B 03 AA D8 F8 00 80 80 45 11 D0 42 F8 2B 80 ... +T714C 002:420.697 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:421.714 - 1.088ms returns 0x100 +T714C 002:421.741 JLINK_HasError() +T714C 002:421.759 JLINK_WriteReg(R0, 0x28010300) +T714C 002:421.778 - 0.019ms returns 0 +T714C 002:421.795 JLINK_WriteReg(R1, 0x00000100) +T714C 002:421.811 - 0.016ms returns 0 +T714C 002:421.828 JLINK_WriteReg(R2, 0x30500674) +T714C 002:421.844 - 0.016ms returns 0 +T714C 002:421.861 JLINK_WriteReg(R3, 0x00000000) +T714C 002:421.878 - 0.017ms returns 0 +T714C 002:421.895 JLINK_WriteReg(R4, 0x00000000) +T714C 002:421.911 - 0.016ms returns 0 +T714C 002:421.928 JLINK_WriteReg(R5, 0x00000000) +T714C 002:421.944 - 0.016ms returns 0 +T714C 002:421.960 JLINK_WriteReg(R6, 0x00000000) +T714C 002:421.977 - 0.016ms returns 0 +T714C 002:421.994 JLINK_WriteReg(R7, 0x00000000) +T714C 002:422.010 - 0.015ms returns 0 +T714C 002:422.026 JLINK_WriteReg(R8, 0x00000000) +T714C 002:422.042 - 0.016ms returns 0 +T714C 002:422.059 JLINK_WriteReg(R9, 0x30500458) +T714C 002:422.075 - 0.016ms returns 0 +T714C 002:422.092 JLINK_WriteReg(R10, 0x00000000) +T714C 002:422.107 - 0.015ms returns 0 +T714C 002:422.123 JLINK_WriteReg(R11, 0x00000000) +T714C 002:422.139 - 0.015ms returns 0 +T714C 002:422.155 JLINK_WriteReg(R12, 0x00000000) +T714C 002:422.171 - 0.015ms returns 0 +T714C 002:422.188 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:422.205 - 0.017ms returns 0 +T714C 002:422.221 JLINK_WriteReg(R14, 0x30500001) +T714C 002:422.237 - 0.016ms returns 0 +T714C 002:422.253 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:422.269 - 0.016ms returns 0 +T714C 002:422.286 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:422.302 - 0.016ms returns 0 +T714C 002:422.318 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:422.334 - 0.016ms returns 0 +T714C 002:422.350 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:422.366 - 0.015ms returns 0 +T714C 002:422.382 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:422.398 - 0.016ms returns 0 +T714C 002:422.415 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:422.431 - 0.016ms returns 0x00000082 +T714C 002:422.449 JLINK_Go() +T714C 002:422.467 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:422.730 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:424.664 - 2.215ms +T714C 002:424.688 JLINK_IsHalted() +T714C 002:424.903 - 0.214ms returns FALSE +T714C 002:424.923 JLINK_HasError() +T714C 002:426.176 JLINK_IsHalted() +T714C 002:428.382 - 2.206ms returns TRUE +T714C 002:428.404 JLINK_ReadReg(R15 (PC)) +T714C 002:428.422 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:428.652 - 0.248ms returns 0x30500000 +T714C 002:428.673 JLINK_ClrBPEx(BPHandle = 0x00000082) +T714C 002:428.689 - 0.016ms returns 0x00 +T714C 002:428.705 JLINK_ReadReg(R0) +T714C 002:428.722 - 0.016ms returns 0x00000000 +T714C 002:429.222 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:429.254 Data: 6D 6F 64 65 0A 00 00 00 20 2D 2D 2D 2D 2D 2D 2D ... +T714C 002:429.284 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:430.388 - 1.166ms returns 0x100 +T714C 002:430.411 JLINK_HasError() +T714C 002:430.432 JLINK_WriteReg(R0, 0x28010400) +T714C 002:430.450 - 0.017ms returns 0 +T714C 002:430.466 JLINK_WriteReg(R1, 0x00000100) +T714C 002:430.482 - 0.015ms returns 0 +T714C 002:430.498 JLINK_WriteReg(R2, 0x30500674) +T714C 002:430.514 - 0.015ms returns 0 +T714C 002:430.530 JLINK_WriteReg(R3, 0x00000000) +T714C 002:430.554 - 0.024ms returns 0 +T714C 002:430.571 JLINK_WriteReg(R4, 0x00000000) +T714C 002:430.588 - 0.016ms returns 0 +T714C 002:430.604 JLINK_WriteReg(R5, 0x00000000) +T714C 002:430.620 - 0.015ms returns 0 +T714C 002:430.636 JLINK_WriteReg(R6, 0x00000000) +T714C 002:430.652 - 0.015ms returns 0 +T714C 002:430.668 JLINK_WriteReg(R7, 0x00000000) +T714C 002:430.684 - 0.016ms returns 0 +T714C 002:430.701 JLINK_WriteReg(R8, 0x00000000) +T714C 002:430.717 - 0.016ms returns 0 +T714C 002:430.733 JLINK_WriteReg(R9, 0x30500458) +T714C 002:430.749 - 0.015ms returns 0 +T714C 002:430.765 JLINK_WriteReg(R10, 0x00000000) +T714C 002:430.780 - 0.015ms returns 0 +T714C 002:430.796 JLINK_WriteReg(R11, 0x00000000) +T714C 002:430.812 - 0.015ms returns 0 +T714C 002:430.828 JLINK_WriteReg(R12, 0x00000000) +T714C 002:430.844 - 0.015ms returns 0 +T714C 002:430.860 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:430.877 - 0.017ms returns 0 +T714C 002:430.893 JLINK_WriteReg(R14, 0x30500001) +T714C 002:430.909 - 0.016ms returns 0 +T714C 002:430.926 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:430.941 - 0.016ms returns 0 +T714C 002:430.958 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:430.974 - 0.016ms returns 0 +T714C 002:430.990 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:431.007 - 0.016ms returns 0 +T714C 002:431.023 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:431.038 - 0.015ms returns 0 +T714C 002:431.055 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:431.071 - 0.015ms returns 0 +T714C 002:431.087 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:431.103 - 0.016ms returns 0x00000083 +T714C 002:431.119 JLINK_Go() +T714C 002:431.136 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:431.514 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:433.434 - 2.313ms +T714C 002:433.470 JLINK_IsHalted() +T714C 002:433.705 - 0.235ms returns FALSE +T714C 002:433.726 JLINK_HasError() +T714C 002:435.657 JLINK_IsHalted() +T714C 002:437.918 - 2.260ms returns TRUE +T714C 002:438.021 JLINK_ReadReg(R15 (PC)) +T714C 002:438.063 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:438.407 - 0.385ms returns 0x30500000 +T714C 002:438.467 JLINK_ClrBPEx(BPHandle = 0x00000083) +T714C 002:438.487 - 0.020ms returns 0x00 +T714C 002:438.518 JLINK_ReadReg(R0) +T714C 002:438.537 - 0.019ms returns 0x00000000 +T714C 002:439.232 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:439.271 Data: A8 42 B8 BF 05 46 40 46 31 46 01 F0 6F FD DA F8 ... +T714C 002:439.303 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:440.315 - 1.082ms returns 0x100 +T714C 002:440.344 JLINK_HasError() +T714C 002:440.363 JLINK_WriteReg(R0, 0x28010500) +T714C 002:440.381 - 0.018ms returns 0 +T714C 002:440.398 JLINK_WriteReg(R1, 0x00000100) +T714C 002:440.414 - 0.016ms returns 0 +T714C 002:440.431 JLINK_WriteReg(R2, 0x30500674) +T714C 002:440.447 - 0.016ms returns 0 +T714C 002:440.463 JLINK_WriteReg(R3, 0x00000000) +T714C 002:440.480 - 0.016ms returns 0 +T714C 002:440.496 JLINK_WriteReg(R4, 0x00000000) +T714C 002:440.512 - 0.016ms returns 0 +T714C 002:440.528 JLINK_WriteReg(R5, 0x00000000) +T714C 002:440.545 - 0.016ms returns 0 +T714C 002:440.562 JLINK_WriteReg(R6, 0x00000000) +T714C 002:440.579 - 0.017ms returns 0 +T714C 002:440.595 JLINK_WriteReg(R7, 0x00000000) +T714C 002:440.611 - 0.016ms returns 0 +T714C 002:440.628 JLINK_WriteReg(R8, 0x00000000) +T714C 002:440.644 - 0.016ms returns 0 +T714C 002:440.660 JLINK_WriteReg(R9, 0x30500458) +T714C 002:440.678 - 0.017ms returns 0 +T714C 002:440.694 JLINK_WriteReg(R10, 0x00000000) +T714C 002:440.711 - 0.016ms returns 0 +T714C 002:440.727 JLINK_WriteReg(R11, 0x00000000) +T714C 002:440.743 - 0.016ms returns 0 +T714C 002:440.759 JLINK_WriteReg(R12, 0x00000000) +T714C 002:440.775 - 0.015ms returns 0 +T714C 002:440.792 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:440.809 - 0.017ms returns 0 +T714C 002:440.825 JLINK_WriteReg(R14, 0x30500001) +T714C 002:440.841 - 0.016ms returns 0 +T714C 002:440.857 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:440.873 - 0.015ms returns 0 +T714C 002:440.889 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:440.910 - 0.021ms returns 0 +T714C 002:440.928 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:440.944 - 0.016ms returns 0 +T714C 002:440.961 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:440.977 - 0.015ms returns 0 +T714C 002:440.993 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:441.009 - 0.016ms returns 0 +T714C 002:441.026 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:441.043 - 0.017ms returns 0x00000084 +T714C 002:441.060 JLINK_Go() +T714C 002:441.077 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:441.384 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:443.308 - 2.248ms +T714C 002:443.363 JLINK_IsHalted() +T714C 002:443.703 - 0.340ms returns FALSE +T714C 002:443.730 JLINK_HasError() +T714C 002:445.830 JLINK_IsHalted() +T714C 002:448.178 - 2.347ms returns TRUE +T714C 002:448.226 JLINK_ReadReg(R15 (PC)) +T714C 002:448.245 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:448.573 - 0.346ms returns 0x30500000 +T714C 002:448.642 JLINK_ClrBPEx(BPHandle = 0x00000084) +T714C 002:448.662 - 0.019ms returns 0x00 +T714C 002:448.680 JLINK_ReadReg(R0) +T714C 002:448.699 - 0.018ms returns 0x00000000 +T714C 002:449.275 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:449.335 Data: 00 20 70 BD 56 F8 04 0C 70 BD 00 00 00 29 04 BF ... +T714C 002:449.367 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:450.435 - 1.159ms returns 0x100 +T714C 002:450.502 JLINK_HasError() +T714C 002:450.528 JLINK_WriteReg(R0, 0x28010600) +T714C 002:450.560 - 0.032ms returns 0 +T714C 002:450.596 JLINK_WriteReg(R1, 0x00000100) +T714C 002:450.623 - 0.027ms returns 0 +T714C 002:450.648 JLINK_WriteReg(R2, 0x30500674) +T714C 002:450.671 - 0.023ms returns 0 +T714C 002:450.694 JLINK_WriteReg(R3, 0x00000000) +T714C 002:450.717 - 0.022ms returns 0 +T714C 002:450.742 JLINK_WriteReg(R4, 0x00000000) +T714C 002:450.764 - 0.022ms returns 0 +T714C 002:450.787 JLINK_WriteReg(R5, 0x00000000) +T714C 002:450.810 - 0.023ms returns 0 +T714C 002:450.834 JLINK_WriteReg(R6, 0x00000000) +T714C 002:450.858 - 0.023ms returns 0 +T714C 002:450.881 JLINK_WriteReg(R7, 0x00000000) +T714C 002:450.902 - 0.021ms returns 0 +T714C 002:450.924 JLINK_WriteReg(R8, 0x00000000) +T714C 002:450.940 - 0.016ms returns 0 +T714C 002:450.957 JLINK_WriteReg(R9, 0x30500458) +T714C 002:450.974 - 0.018ms returns 0 +T714C 002:450.994 JLINK_WriteReg(R10, 0x00000000) +T714C 002:451.017 - 0.022ms returns 0 +T714C 002:451.040 JLINK_WriteReg(R11, 0x00000000) +T714C 002:451.058 - 0.017ms returns 0 +T714C 002:451.075 JLINK_WriteReg(R12, 0x00000000) +T714C 002:451.092 - 0.016ms returns 0 +T714C 002:451.112 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:451.136 - 0.023ms returns 0 +T714C 002:451.153 JLINK_WriteReg(R14, 0x30500001) +T714C 002:451.170 - 0.017ms returns 0 +T714C 002:451.186 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:451.206 - 0.020ms returns 0 +T714C 002:451.223 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:451.239 - 0.016ms returns 0 +T714C 002:451.256 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:451.273 - 0.017ms returns 0 +T714C 002:451.290 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:451.307 - 0.016ms returns 0 +T714C 002:451.323 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:451.340 - 0.016ms returns 0 +T714C 002:451.357 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:451.376 - 0.018ms returns 0x00000085 +T714C 002:451.392 JLINK_Go() +T714C 002:451.413 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:451.788 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:454.150 - 2.756ms +T714C 002:454.204 JLINK_IsHalted() +T714C 002:454.508 - 0.304ms returns FALSE +T714C 002:454.556 JLINK_HasError() +T714C 002:456.165 JLINK_IsHalted() +T714C 002:458.562 - 2.396ms returns TRUE +T714C 002:458.610 JLINK_ReadReg(R15 (PC)) +T714C 002:458.630 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:458.887 - 0.276ms returns 0x30500000 +T714C 002:458.934 JLINK_ClrBPEx(BPHandle = 0x00000085) +T714C 002:458.952 - 0.017ms returns 0x00 +T714C 002:458.969 JLINK_ReadReg(R0) +T714C 002:458.989 - 0.020ms returns 0x00000000 +T714C 002:459.618 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:459.649 Data: 64 D2 22 29 07 F1 01 00 1C D1 49 F8 27 30 19 78 ... +T714C 002:459.688 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:460.879 - 1.260ms returns 0x100 +T714C 002:460.927 JLINK_HasError() +T714C 002:460.945 JLINK_WriteReg(R0, 0x28010700) +T714C 002:460.964 - 0.019ms returns 0 +T714C 002:460.982 JLINK_WriteReg(R1, 0x00000100) +T714C 002:460.998 - 0.016ms returns 0 +T714C 002:461.014 JLINK_WriteReg(R2, 0x30500674) +T714C 002:461.029 - 0.015ms returns 0 +T714C 002:461.046 JLINK_WriteReg(R3, 0x00000000) +T714C 002:461.061 - 0.015ms returns 0 +T714C 002:461.077 JLINK_WriteReg(R4, 0x00000000) +T714C 002:461.093 - 0.015ms returns 0 +T714C 002:461.109 JLINK_WriteReg(R5, 0x00000000) +T714C 002:461.124 - 0.015ms returns 0 +T714C 002:461.140 JLINK_WriteReg(R6, 0x00000000) +T714C 002:461.156 - 0.016ms returns 0 +T714C 002:461.172 JLINK_WriteReg(R7, 0x00000000) +T714C 002:461.187 - 0.015ms returns 0 +T714C 002:461.203 JLINK_WriteReg(R8, 0x00000000) +T714C 002:461.219 - 0.015ms returns 0 +T714C 002:461.235 JLINK_WriteReg(R9, 0x30500458) +T714C 002:461.250 - 0.015ms returns 0 +T714C 002:461.267 JLINK_WriteReg(R10, 0x00000000) +T714C 002:461.283 - 0.015ms returns 0 +T714C 002:461.298 JLINK_WriteReg(R11, 0x00000000) +T714C 002:461.314 - 0.015ms returns 0 +T714C 002:461.330 JLINK_WriteReg(R12, 0x00000000) +T714C 002:461.346 - 0.015ms returns 0 +T714C 002:461.362 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:461.379 - 0.016ms returns 0 +T714C 002:461.394 JLINK_WriteReg(R14, 0x30500001) +T714C 002:461.410 - 0.015ms returns 0 +T714C 002:461.426 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:461.442 - 0.016ms returns 0 +T714C 002:461.457 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:461.473 - 0.015ms returns 0 +T714C 002:461.489 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:461.504 - 0.015ms returns 0 +T714C 002:461.521 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:461.536 - 0.015ms returns 0 +T714C 002:461.552 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:461.568 - 0.015ms returns 0 +T714C 002:461.584 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:461.600 - 0.016ms returns 0x00000086 +T714C 002:461.616 JLINK_Go() +T714C 002:461.633 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:461.956 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:464.126 - 2.509ms +T714C 002:464.174 JLINK_IsHalted() +T714C 002:464.484 - 0.309ms returns FALSE +T714C 002:464.534 JLINK_HasError() +T714C 002:466.138 JLINK_IsHalted() +T714C 002:468.610 - 2.471ms returns TRUE +T714C 002:468.665 JLINK_ReadReg(R15 (PC)) +T714C 002:468.686 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:468.906 - 0.241ms returns 0x30500000 +T714C 002:468.929 JLINK_ClrBPEx(BPHandle = 0x00000086) +T714C 002:468.946 - 0.017ms returns 0x00 +T714C 002:468.963 JLINK_ReadReg(R0) +T714C 002:468.980 - 0.017ms returns 0x00000000 +T714C 002:469.566 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:469.599 Data: 20 61 72 67 73 20 21 20 57 65 20 6F 6E 6C 79 20 ... +T714C 002:469.631 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:470.641 - 1.075ms returns 0x100 +T714C 002:471.257 JLINK_HasError() +T714C 002:471.279 JLINK_WriteReg(R0, 0x28010800) +T714C 002:471.298 - 0.019ms returns 0 +T714C 002:471.316 JLINK_WriteReg(R1, 0x00000100) +T714C 002:471.332 - 0.016ms returns 0 +T714C 002:471.348 JLINK_WriteReg(R2, 0x30500674) +T714C 002:471.364 - 0.015ms returns 0 +T714C 002:471.380 JLINK_WriteReg(R3, 0x00000000) +T714C 002:471.397 - 0.016ms returns 0 +T714C 002:471.413 JLINK_WriteReg(R4, 0x00000000) +T714C 002:471.432 - 0.018ms returns 0 +T714C 002:471.448 JLINK_WriteReg(R5, 0x00000000) +T714C 002:471.464 - 0.015ms returns 0 +T714C 002:471.480 JLINK_WriteReg(R6, 0x00000000) +T714C 002:471.496 - 0.015ms returns 0 +T714C 002:471.512 JLINK_WriteReg(R7, 0x00000000) +T714C 002:471.529 - 0.016ms returns 0 +T714C 002:471.545 JLINK_WriteReg(R8, 0x00000000) +T714C 002:471.561 - 0.015ms returns 0 +T714C 002:471.577 JLINK_WriteReg(R9, 0x30500458) +T714C 002:471.593 - 0.015ms returns 0 +T714C 002:471.609 JLINK_WriteReg(R10, 0x00000000) +T714C 002:471.626 - 0.016ms returns 0 +T714C 002:471.642 JLINK_WriteReg(R11, 0x00000000) +T714C 002:471.664 - 0.022ms returns 0 +T714C 002:471.681 JLINK_WriteReg(R12, 0x00000000) +T714C 002:471.697 - 0.015ms returns 0 +T714C 002:471.714 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:471.730 - 0.016ms returns 0 +T714C 002:471.747 JLINK_WriteReg(R14, 0x30500001) +T714C 002:471.762 - 0.015ms returns 0 +T714C 002:471.779 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:471.795 - 0.016ms returns 0 +T714C 002:471.812 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:471.827 - 0.016ms returns 0 +T714C 002:471.844 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:471.860 - 0.016ms returns 0 +T714C 002:471.877 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:471.893 - 0.016ms returns 0 +T714C 002:471.910 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:471.925 - 0.016ms returns 0 +T714C 002:471.942 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:471.959 - 0.017ms returns 0x00000087 +T714C 002:471.975 JLINK_Go() +T714C 002:471.993 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:472.272 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:474.136 - 2.160ms +T714C 002:474.158 JLINK_IsHalted() +T714C 002:474.377 - 0.219ms returns FALSE +T714C 002:474.400 JLINK_HasError() +T714C 002:476.286 JLINK_IsHalted() +T714C 002:478.477 - 2.190ms returns TRUE +T714C 002:478.500 JLINK_ReadReg(R15 (PC)) +T714C 002:478.516 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:478.836 - 0.336ms returns 0x30500000 +T714C 002:478.907 JLINK_ClrBPEx(BPHandle = 0x00000087) +T714C 002:478.924 - 0.017ms returns 0x00 +T714C 002:478.941 JLINK_ReadReg(R0) +T714C 002:478.957 - 0.016ms returns 0x00000000 +T714C 002:479.439 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:479.469 Data: 01 78 41 F0 20 01 20 29 1C BF 01 37 81 46 01 30 ... +T714C 002:479.500 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:480.493 - 1.053ms returns 0x100 +T714C 002:480.544 JLINK_HasError() +T714C 002:480.562 JLINK_WriteReg(R0, 0x28010900) +T714C 002:480.582 - 0.019ms returns 0 +T714C 002:480.598 JLINK_WriteReg(R1, 0x00000100) +T714C 002:480.614 - 0.016ms returns 0 +T714C 002:480.631 JLINK_WriteReg(R2, 0x30500674) +T714C 002:480.647 - 0.016ms returns 0 +T714C 002:480.663 JLINK_WriteReg(R3, 0x00000000) +T714C 002:480.679 - 0.015ms returns 0 +T714C 002:480.695 JLINK_WriteReg(R4, 0x00000000) +T714C 002:480.711 - 0.015ms returns 0 +T714C 002:480.727 JLINK_WriteReg(R5, 0x00000000) +T714C 002:480.743 - 0.015ms returns 0 +T714C 002:480.759 JLINK_WriteReg(R6, 0x00000000) +T714C 002:480.775 - 0.016ms returns 0 +T714C 002:480.791 JLINK_WriteReg(R7, 0x00000000) +T714C 002:480.807 - 0.015ms returns 0 +T714C 002:480.823 JLINK_WriteReg(R8, 0x00000000) +T714C 002:480.839 - 0.015ms returns 0 +T714C 002:480.855 JLINK_WriteReg(R9, 0x30500458) +T714C 002:480.871 - 0.015ms returns 0 +T714C 002:480.887 JLINK_WriteReg(R10, 0x00000000) +T714C 002:480.903 - 0.015ms returns 0 +T714C 002:480.918 JLINK_WriteReg(R11, 0x00000000) +T714C 002:480.934 - 0.015ms returns 0 +T714C 002:480.951 JLINK_WriteReg(R12, 0x00000000) +T714C 002:480.966 - 0.015ms returns 0 +T714C 002:480.984 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:481.001 - 0.017ms returns 0 +T714C 002:481.017 JLINK_WriteReg(R14, 0x30500001) +T714C 002:481.033 - 0.015ms returns 0 +T714C 002:481.049 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:481.066 - 0.016ms returns 0 +T714C 002:481.082 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:481.123 - 0.041ms returns 0 +T714C 002:481.139 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:481.155 - 0.015ms returns 0 +T714C 002:481.171 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:481.186 - 0.015ms returns 0 +T714C 002:481.202 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:481.218 - 0.015ms returns 0 +T714C 002:481.235 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:481.251 - 0.016ms returns 0x00000088 +T714C 002:481.266 JLINK_Go() +T714C 002:481.284 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:481.603 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:483.601 - 2.334ms +T714C 002:483.651 JLINK_IsHalted() +T714C 002:483.868 - 0.216ms returns FALSE +T714C 002:483.888 JLINK_HasError() +T714C 002:485.211 JLINK_IsHalted() +T714C 002:487.456 - 2.248ms returns TRUE +T714C 002:487.480 JLINK_ReadReg(R15 (PC)) +T714C 002:487.498 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:487.793 - 0.313ms returns 0x30500000 +T714C 002:487.840 JLINK_ClrBPEx(BPHandle = 0x00000088) +T714C 002:487.858 - 0.017ms returns 0x00 +T714C 002:487.875 JLINK_ReadReg(R0) +T714C 002:487.892 - 0.017ms returns 0x00000000 +T714C 002:488.470 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:488.501 Data: 01 04 00 BF D5 E9 04 12 20 46 01 F0 EF FA A8 69 ... +T714C 002:488.549 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:489.688 - 1.217ms returns 0x100 +T714C 002:489.734 JLINK_HasError() +T714C 002:489.752 JLINK_WriteReg(R0, 0x28010A00) +T714C 002:489.770 - 0.018ms returns 0 +T714C 002:489.787 JLINK_WriteReg(R1, 0x00000100) +T714C 002:489.803 - 0.016ms returns 0 +T714C 002:489.819 JLINK_WriteReg(R2, 0x30500674) +T714C 002:489.835 - 0.015ms returns 0 +T714C 002:489.851 JLINK_WriteReg(R3, 0x00000000) +T714C 002:489.866 - 0.015ms returns 0 +T714C 002:489.882 JLINK_WriteReg(R4, 0x00000000) +T714C 002:489.898 - 0.015ms returns 0 +T714C 002:489.913 JLINK_WriteReg(R5, 0x00000000) +T714C 002:489.929 - 0.015ms returns 0 +T714C 002:489.944 JLINK_WriteReg(R6, 0x00000000) +T714C 002:489.960 - 0.015ms returns 0 +T714C 002:489.976 JLINK_WriteReg(R7, 0x00000000) +T714C 002:489.991 - 0.015ms returns 0 +T714C 002:490.009 JLINK_WriteReg(R8, 0x00000000) +T714C 002:490.024 - 0.015ms returns 0 +T714C 002:490.040 JLINK_WriteReg(R9, 0x30500458) +T714C 002:490.056 - 0.015ms returns 0 +T714C 002:490.072 JLINK_WriteReg(R10, 0x00000000) +T714C 002:490.087 - 0.015ms returns 0 +T714C 002:490.103 JLINK_WriteReg(R11, 0x00000000) +T714C 002:490.119 - 0.015ms returns 0 +T714C 002:490.134 JLINK_WriteReg(R12, 0x00000000) +T714C 002:490.150 - 0.015ms returns 0 +T714C 002:490.166 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:490.183 - 0.017ms returns 0 +T714C 002:490.201 JLINK_WriteReg(R14, 0x30500001) +T714C 002:490.216 - 0.015ms returns 0 +T714C 002:490.232 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:490.248 - 0.015ms returns 0 +T714C 002:490.264 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:490.280 - 0.015ms returns 0 +T714C 002:490.295 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:490.311 - 0.015ms returns 0 +T714C 002:490.327 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:490.343 - 0.016ms returns 0 +T714C 002:490.359 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:490.374 - 0.015ms returns 0 +T714C 002:490.391 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:490.407 - 0.016ms returns 0x00000089 +T714C 002:490.422 JLINK_Go() +T714C 002:490.440 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:490.764 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:492.915 - 2.492ms +T714C 002:492.962 JLINK_IsHalted() +T714C 002:493.235 - 0.272ms returns FALSE +T714C 002:493.282 JLINK_HasError() +T714C 002:495.282 JLINK_IsHalted() +T714C 002:497.575 - 2.292ms returns TRUE +T714C 002:497.644 JLINK_ReadReg(R15 (PC)) +T714C 002:497.668 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:497.993 - 0.348ms returns 0x30500000 +T714C 002:498.053 JLINK_ClrBPEx(BPHandle = 0x00000089) +T714C 002:498.074 - 0.020ms returns 0x00 +T714C 002:498.106 JLINK_ReadReg(R0) +T714C 002:498.158 - 0.051ms returns 0x00000000 +T714C 002:499.266 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:499.317 Data: 0C 35 00 28 F6 D1 BD E8 B0 40 70 47 20 20 20 20 ... +T714C 002:499.353 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:500.521 - 1.254ms returns 0x100 +T714C 002:500.574 JLINK_HasError() +T714C 002:500.592 JLINK_WriteReg(R0, 0x28010B00) +T714C 002:500.612 - 0.019ms returns 0 +T714C 002:500.629 JLINK_WriteReg(R1, 0x00000100) +T714C 002:500.645 - 0.016ms returns 0 +T714C 002:500.662 JLINK_WriteReg(R2, 0x30500674) +T714C 002:500.678 - 0.016ms returns 0 +T714C 002:500.694 JLINK_WriteReg(R3, 0x00000000) +T714C 002:500.710 - 0.015ms returns 0 +T714C 002:500.725 JLINK_WriteReg(R4, 0x00000000) +T714C 002:500.741 - 0.015ms returns 0 +T714C 002:500.757 JLINK_WriteReg(R5, 0x00000000) +T714C 002:500.775 - 0.017ms returns 0 +T714C 002:500.798 JLINK_WriteReg(R6, 0x00000000) +T714C 002:500.815 - 0.016ms returns 0 +T714C 002:500.833 JLINK_WriteReg(R7, 0x00000000) +T714C 002:500.848 - 0.015ms returns 0 +T714C 002:500.865 JLINK_WriteReg(R8, 0x00000000) +T714C 002:500.882 - 0.017ms returns 0 +T714C 002:500.898 JLINK_WriteReg(R9, 0x30500458) +T714C 002:500.915 - 0.016ms returns 0 +T714C 002:500.931 JLINK_WriteReg(R10, 0x00000000) +T714C 002:500.947 - 0.015ms returns 0 +T714C 002:500.962 JLINK_WriteReg(R11, 0x00000000) +T714C 002:500.978 - 0.015ms returns 0 +T714C 002:500.994 JLINK_WriteReg(R12, 0x00000000) +T714C 002:501.009 - 0.015ms returns 0 +T714C 002:501.025 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:501.042 - 0.016ms returns 0 +T714C 002:501.057 JLINK_WriteReg(R14, 0x30500001) +T714C 002:501.074 - 0.016ms returns 0 +T714C 002:501.090 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:501.106 - 0.016ms returns 0 +T714C 002:501.122 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:501.137 - 0.015ms returns 0 +T714C 002:501.154 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:501.169 - 0.015ms returns 0 +T714C 002:501.185 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:501.201 - 0.015ms returns 0 +T714C 002:501.217 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:501.233 - 0.015ms returns 0 +T714C 002:501.249 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:501.265 - 0.016ms returns 0x0000008A +T714C 002:501.282 JLINK_Go() +T714C 002:501.300 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:501.642 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:503.790 - 2.507ms +T714C 002:503.837 JLINK_IsHalted() +T714C 002:504.131 - 0.293ms returns FALSE +T714C 002:504.178 JLINK_HasError() +T714C 002:507.372 JLINK_IsHalted() +T714C 002:509.717 - 2.344ms returns TRUE +T714C 002:509.765 JLINK_ReadReg(R15 (PC)) +T714C 002:509.785 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:510.046 - 0.281ms returns 0x30500000 +T714C 002:510.094 JLINK_ClrBPEx(BPHandle = 0x0000008A) +T714C 002:510.112 - 0.018ms returns 0x00 +T714C 002:510.128 JLINK_ReadReg(R0) +T714C 002:510.145 - 0.017ms returns 0x00000000 +T714C 002:512.583 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:512.669 Data: 58 E0 4F F0 00 0B 5F EA 4E 67 88 A7 8C A6 CD F8 ... +T714C 002:512.718 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:513.844 - 1.260ms returns 0x100 +T714C 002:513.964 JLINK_HasError() +T714C 002:514.044 JLINK_WriteReg(R0, 0x28010C00) +T714C 002:514.092 - 0.048ms returns 0 +T714C 002:514.110 JLINK_WriteReg(R1, 0x00000100) +T714C 002:514.186 - 0.076ms returns 0 +T714C 002:514.248 JLINK_WriteReg(R2, 0x30500674) +T714C 002:514.306 - 0.057ms returns 0 +T714C 002:514.326 JLINK_WriteReg(R3, 0x00000000) +T714C 002:514.344 - 0.017ms returns 0 +T714C 002:514.361 JLINK_WriteReg(R4, 0x00000000) +T714C 002:514.380 - 0.019ms returns 0 +T714C 002:514.397 JLINK_WriteReg(R5, 0x00000000) +T714C 002:514.416 - 0.020ms returns 0 +T714C 002:514.432 JLINK_WriteReg(R6, 0x00000000) +T714C 002:514.447 - 0.015ms returns 0 +T714C 002:514.462 JLINK_WriteReg(R7, 0x00000000) +T714C 002:514.513 - 0.015ms returns 0 +T714C 002:514.530 JLINK_WriteReg(R8, 0x00000000) +T714C 002:514.554 - 0.024ms returns 0 +T714C 002:514.571 JLINK_WriteReg(R9, 0x30500458) +T714C 002:514.588 - 0.016ms returns 0 +T714C 002:514.604 JLINK_WriteReg(R10, 0x00000000) +T714C 002:514.651 - 0.047ms returns 0 +T714C 002:514.680 JLINK_WriteReg(R11, 0x00000000) +T714C 002:514.699 - 0.019ms returns 0 +T714C 002:514.723 JLINK_WriteReg(R12, 0x00000000) +T714C 002:514.742 - 0.018ms returns 0 +T714C 002:514.760 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:514.780 - 0.019ms returns 0 +T714C 002:514.797 JLINK_WriteReg(R14, 0x30500001) +T714C 002:514.814 - 0.017ms returns 0 +T714C 002:514.833 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:514.849 - 0.016ms returns 0 +T714C 002:514.866 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:514.883 - 0.017ms returns 0 +T714C 002:514.901 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:514.918 - 0.017ms returns 0 +T714C 002:514.936 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:514.953 - 0.017ms returns 0 +T714C 002:514.982 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:515.003 - 0.021ms returns 0 +T714C 002:515.023 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:515.044 - 0.021ms returns 0x0000008B +T714C 002:515.064 JLINK_Go() +T714C 002:515.087 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:515.458 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:517.459 - 2.395ms +T714C 002:517.495 JLINK_IsHalted() +T714C 002:517.698 - 0.202ms returns FALSE +T714C 002:517.719 JLINK_HasError() +T714C 002:519.273 JLINK_IsHalted() +T714C 002:521.423 - 2.149ms returns TRUE +T714C 002:521.447 JLINK_ReadReg(R15 (PC)) +T714C 002:521.467 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:521.760 - 0.312ms returns 0x30500000 +T714C 002:521.784 JLINK_ClrBPEx(BPHandle = 0x0000008B) +T714C 002:521.802 - 0.018ms returns 0x00 +T714C 002:521.821 JLINK_ReadReg(R0) +T714C 002:521.839 - 0.018ms returns 0x00000000 +T714C 002:522.588 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:522.637 Data: 01 9D BB F1 00 0F 05 D0 88 42 38 BF 80 F8 00 B0 ... +T714C 002:522.670 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:523.694 - 1.106ms returns 0x100 +T714C 002:523.744 JLINK_HasError() +T714C 002:523.761 JLINK_WriteReg(R0, 0x28010D00) +T714C 002:523.780 - 0.019ms returns 0 +T714C 002:523.797 JLINK_WriteReg(R1, 0x00000100) +T714C 002:523.813 - 0.016ms returns 0 +T714C 002:523.829 JLINK_WriteReg(R2, 0x30500674) +T714C 002:523.846 - 0.016ms returns 0 +T714C 002:523.862 JLINK_WriteReg(R3, 0x00000000) +T714C 002:523.878 - 0.016ms returns 0 +T714C 002:523.894 JLINK_WriteReg(R4, 0x00000000) +T714C 002:523.913 - 0.018ms returns 0 +T714C 002:523.930 JLINK_WriteReg(R5, 0x00000000) +T714C 002:523.946 - 0.016ms returns 0 +T714C 002:523.962 JLINK_WriteReg(R6, 0x00000000) +T714C 002:523.978 - 0.015ms returns 0 +T714C 002:523.994 JLINK_WriteReg(R7, 0x00000000) +T714C 002:524.009 - 0.015ms returns 0 +T714C 002:524.026 JLINK_WriteReg(R8, 0x00000000) +T714C 002:524.042 - 0.016ms returns 0 +T714C 002:524.058 JLINK_WriteReg(R9, 0x30500458) +T714C 002:524.074 - 0.015ms returns 0 +T714C 002:524.090 JLINK_WriteReg(R10, 0x00000000) +T714C 002:524.106 - 0.015ms returns 0 +T714C 002:524.151 JLINK_WriteReg(R11, 0x00000000) +T714C 002:524.166 - 0.015ms returns 0 +T714C 002:524.182 JLINK_WriteReg(R12, 0x00000000) +T714C 002:524.198 - 0.015ms returns 0 +T714C 002:524.214 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:524.232 - 0.018ms returns 0 +T714C 002:524.248 JLINK_WriteReg(R14, 0x30500001) +T714C 002:524.264 - 0.016ms returns 0 +T714C 002:524.286 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:524.303 - 0.017ms returns 0 +T714C 002:524.322 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:524.339 - 0.017ms returns 0 +T714C 002:524.357 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:524.374 - 0.017ms returns 0 +T714C 002:524.393 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:524.410 - 0.017ms returns 0 +T714C 002:524.428 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:524.445 - 0.017ms returns 0 +T714C 002:524.464 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:524.482 - 0.018ms returns 0x0000008C +T714C 002:524.500 JLINK_Go() +T714C 002:524.518 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:524.834 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:526.828 - 2.328ms +T714C 002:526.886 JLINK_IsHalted() +T714C 002:527.151 - 0.264ms returns FALSE +T714C 002:527.176 JLINK_HasError() +T714C 002:528.396 JLINK_IsHalted() +T714C 002:530.624 - 2.227ms returns TRUE +T714C 002:530.655 JLINK_ReadReg(R15 (PC)) +T714C 002:530.674 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:530.903 - 0.247ms returns 0x30500000 +T714C 002:530.923 JLINK_ClrBPEx(BPHandle = 0x0000008C) +T714C 002:530.940 - 0.017ms returns 0x00 +T714C 002:530.958 JLINK_ReadReg(R0) +T714C 002:530.974 - 0.016ms returns 0x00000000 +T714C 002:531.606 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:531.639 Data: 00 F1 01 00 01 D0 01 3F F4 DC 01 2A 0A DB 01 32 ... +T714C 002:531.669 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:532.685 - 1.079ms returns 0x100 +T714C 002:532.717 JLINK_HasError() +T714C 002:532.735 JLINK_WriteReg(R0, 0x28010E00) +T714C 002:532.766 - 0.030ms returns 0 +T714C 002:532.782 JLINK_WriteReg(R1, 0x00000100) +T714C 002:532.799 - 0.016ms returns 0 +T714C 002:532.816 JLINK_WriteReg(R2, 0x30500674) +T714C 002:532.834 - 0.017ms returns 0 +T714C 002:532.852 JLINK_WriteReg(R3, 0x00000000) +T714C 002:532.869 - 0.016ms returns 0 +T714C 002:532.886 JLINK_WriteReg(R4, 0x00000000) +T714C 002:532.901 - 0.015ms returns 0 +T714C 002:532.917 JLINK_WriteReg(R5, 0x00000000) +T714C 002:532.934 - 0.016ms returns 0 +T714C 002:532.950 JLINK_WriteReg(R6, 0x00000000) +T714C 002:532.966 - 0.015ms returns 0 +T714C 002:532.982 JLINK_WriteReg(R7, 0x00000000) +T714C 002:532.999 - 0.016ms returns 0 +T714C 002:533.016 JLINK_WriteReg(R8, 0x00000000) +T714C 002:533.033 - 0.017ms returns 0 +T714C 002:533.051 JLINK_WriteReg(R9, 0x30500458) +T714C 002:533.069 - 0.018ms returns 0 +T714C 002:533.087 JLINK_WriteReg(R10, 0x00000000) +T714C 002:533.103 - 0.015ms returns 0 +T714C 002:533.119 JLINK_WriteReg(R11, 0x00000000) +T714C 002:533.135 - 0.016ms returns 0 +T714C 002:533.152 JLINK_WriteReg(R12, 0x00000000) +T714C 002:533.168 - 0.016ms returns 0 +T714C 002:533.185 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:533.202 - 0.017ms returns 0 +T714C 002:533.219 JLINK_WriteReg(R14, 0x30500001) +T714C 002:533.235 - 0.015ms returns 0 +T714C 002:533.252 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:533.269 - 0.017ms returns 0 +T714C 002:533.285 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:533.301 - 0.015ms returns 0 +T714C 002:533.317 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:533.332 - 0.016ms returns 0 +T714C 002:533.349 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:533.366 - 0.016ms returns 0 +T714C 002:533.382 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:533.398 - 0.015ms returns 0 +T714C 002:533.415 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:533.431 - 0.016ms returns 0x0000008D +T714C 002:533.448 JLINK_Go() +T714C 002:533.466 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:533.739 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:535.578 - 2.129ms +T714C 002:535.622 JLINK_IsHalted() +T714C 002:535.866 - 0.243ms returns FALSE +T714C 002:535.893 JLINK_HasError() +T714C 002:537.352 JLINK_IsHalted() +T714C 002:539.586 - 2.234ms returns TRUE +T714C 002:539.632 JLINK_ReadReg(R15 (PC)) +T714C 002:539.651 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:539.870 - 0.238ms returns 0x30500000 +T714C 002:539.890 JLINK_ClrBPEx(BPHandle = 0x0000008D) +T714C 002:539.907 - 0.017ms returns 0x00 +T714C 002:539.924 JLINK_ReadReg(R0) +T714C 002:539.940 - 0.016ms returns 0x00000000 +T714C 002:540.986 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:541.037 Data: 18 B9 00 2F A7 F1 01 07 F2 D1 45 F6 BA 60 C2 F6 ... +T714C 002:541.072 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:542.040 - 1.054ms returns 0x100 +T714C 002:542.064 JLINK_HasError() +T714C 002:542.082 JLINK_WriteReg(R0, 0x28010F00) +T714C 002:542.101 - 0.018ms returns 0 +T714C 002:542.117 JLINK_WriteReg(R1, 0x00000100) +T714C 002:542.133 - 0.016ms returns 0 +T714C 002:542.150 JLINK_WriteReg(R2, 0x30500674) +T714C 002:542.167 - 0.016ms returns 0 +T714C 002:542.183 JLINK_WriteReg(R3, 0x00000000) +T714C 002:542.199 - 0.015ms returns 0 +T714C 002:542.215 JLINK_WriteReg(R4, 0x00000000) +T714C 002:542.231 - 0.015ms returns 0 +T714C 002:542.248 JLINK_WriteReg(R5, 0x00000000) +T714C 002:542.264 - 0.016ms returns 0 +T714C 002:542.280 JLINK_WriteReg(R6, 0x00000000) +T714C 002:542.297 - 0.016ms returns 0 +T714C 002:542.313 JLINK_WriteReg(R7, 0x00000000) +T714C 002:542.329 - 0.016ms returns 0 +T714C 002:542.347 JLINK_WriteReg(R8, 0x00000000) +T714C 002:542.364 - 0.016ms returns 0 +T714C 002:542.380 JLINK_WriteReg(R9, 0x30500458) +T714C 002:542.396 - 0.015ms returns 0 +T714C 002:542.412 JLINK_WriteReg(R10, 0x00000000) +T714C 002:542.427 - 0.015ms returns 0 +T714C 002:542.443 JLINK_WriteReg(R11, 0x00000000) +T714C 002:542.459 - 0.015ms returns 0 +T714C 002:542.475 JLINK_WriteReg(R12, 0x00000000) +T714C 002:542.491 - 0.015ms returns 0 +T714C 002:542.507 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:542.530 - 0.022ms returns 0 +T714C 002:542.548 JLINK_WriteReg(R14, 0x30500001) +T714C 002:542.564 - 0.015ms returns 0 +T714C 002:542.580 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:542.596 - 0.016ms returns 0 +T714C 002:542.612 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:542.628 - 0.016ms returns 0 +T714C 002:542.645 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:542.662 - 0.016ms returns 0 +T714C 002:542.678 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:542.694 - 0.015ms returns 0 +T714C 002:542.710 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:542.726 - 0.015ms returns 0 +T714C 002:542.742 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:542.759 - 0.016ms returns 0x0000008E +T714C 002:542.776 JLINK_Go() +T714C 002:542.795 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:543.042 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:544.903 - 2.126ms +T714C 002:544.938 JLINK_IsHalted() +T714C 002:545.156 - 0.218ms returns FALSE +T714C 002:545.177 JLINK_HasError() +T714C 002:546.356 JLINK_IsHalted() +T714C 002:548.474 - 2.117ms returns TRUE +T714C 002:548.551 JLINK_ReadReg(R15 (PC)) +T714C 002:548.573 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:548.851 - 0.300ms returns 0x30500000 +T714C 002:548.933 JLINK_ClrBPEx(BPHandle = 0x0000008E) +T714C 002:548.970 - 0.037ms returns 0x00 +T714C 002:549.005 JLINK_ReadReg(R0) +T714C 002:549.039 - 0.034ms returns 0x00000000 +T714C 002:549.848 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:549.890 Data: C2 F6 01 00 29 46 00 F0 F1 FF 46 F2 B1 10 C2 F6 ... +T714C 002:549.922 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:550.908 - 1.059ms returns 0x100 +T714C 002:550.955 JLINK_HasError() +T714C 002:550.973 JLINK_WriteReg(R0, 0x28011000) +T714C 002:550.993 - 0.019ms returns 0 +T714C 002:551.010 JLINK_WriteReg(R1, 0x00000100) +T714C 002:551.027 - 0.016ms returns 0 +T714C 002:551.043 JLINK_WriteReg(R2, 0x30500674) +T714C 002:551.059 - 0.016ms returns 0 +T714C 002:551.076 JLINK_WriteReg(R3, 0x00000000) +T714C 002:551.092 - 0.015ms returns 0 +T714C 002:551.108 JLINK_WriteReg(R4, 0x00000000) +T714C 002:551.125 - 0.017ms returns 0 +T714C 002:551.141 JLINK_WriteReg(R5, 0x00000000) +T714C 002:551.157 - 0.015ms returns 0 +T714C 002:551.173 JLINK_WriteReg(R6, 0x00000000) +T714C 002:551.189 - 0.015ms returns 0 +T714C 002:551.206 JLINK_WriteReg(R7, 0x00000000) +T714C 002:551.222 - 0.015ms returns 0 +T714C 002:551.238 JLINK_WriteReg(R8, 0x00000000) +T714C 002:551.255 - 0.016ms returns 0 +T714C 002:551.272 JLINK_WriteReg(R9, 0x30500458) +T714C 002:551.288 - 0.016ms returns 0 +T714C 002:551.304 JLINK_WriteReg(R10, 0x00000000) +T714C 002:551.320 - 0.016ms returns 0 +T714C 002:551.336 JLINK_WriteReg(R11, 0x00000000) +T714C 002:551.352 - 0.016ms returns 0 +T714C 002:551.369 JLINK_WriteReg(R12, 0x00000000) +T714C 002:551.384 - 0.015ms returns 0 +T714C 002:551.401 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:551.417 - 0.016ms returns 0 +T714C 002:551.434 JLINK_WriteReg(R14, 0x30500001) +T714C 002:551.449 - 0.015ms returns 0 +T714C 002:551.466 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:551.482 - 0.016ms returns 0 +T714C 002:551.498 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:551.514 - 0.015ms returns 0 +T714C 002:551.530 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:551.546 - 0.016ms returns 0 +T714C 002:551.562 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:551.578 - 0.016ms returns 0 +T714C 002:551.594 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:551.611 - 0.016ms returns 0 +T714C 002:551.628 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:551.645 - 0.017ms returns 0x0000008F +T714C 002:551.661 JLINK_Go() +T714C 002:551.679 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:551.962 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:553.934 - 2.272ms +T714C 002:554.567 JLINK_IsHalted() +T714C 002:556.719 - 2.151ms returns TRUE +T714C 002:556.773 JLINK_ReadReg(R15 (PC)) +T714C 002:556.793 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:557.090 - 0.316ms returns 0x30500000 +T714C 002:557.112 JLINK_ClrBPEx(BPHandle = 0x0000008F) +T714C 002:557.128 - 0.016ms returns 0x00 +T714C 002:557.145 JLINK_ReadReg(R0) +T714C 002:557.169 - 0.024ms returns 0x00000000 +T714C 002:557.781 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:557.821 Data: 0A D0 21 68 C8 07 9B D0 06 E0 4F F0 00 08 03 E0 ... +T714C 002:557.852 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:558.840 - 1.059ms returns 0x100 +T714C 002:558.874 JLINK_HasError() +T714C 002:558.891 JLINK_WriteReg(R0, 0x28011100) +T714C 002:558.910 - 0.018ms returns 0 +T714C 002:558.927 JLINK_WriteReg(R1, 0x00000100) +T714C 002:558.943 - 0.016ms returns 0 +T714C 002:558.960 JLINK_WriteReg(R2, 0x30500674) +T714C 002:558.976 - 0.016ms returns 0 +T714C 002:558.992 JLINK_WriteReg(R3, 0x00000000) +T714C 002:559.008 - 0.016ms returns 0 +T714C 002:559.025 JLINK_WriteReg(R4, 0x00000000) +T714C 002:559.041 - 0.016ms returns 0 +T714C 002:559.058 JLINK_WriteReg(R5, 0x00000000) +T714C 002:559.076 - 0.017ms returns 0 +T714C 002:559.092 JLINK_WriteReg(R6, 0x00000000) +T714C 002:559.108 - 0.015ms returns 0 +T714C 002:559.124 JLINK_WriteReg(R7, 0x00000000) +T714C 002:559.140 - 0.015ms returns 0 +T714C 002:559.156 JLINK_WriteReg(R8, 0x00000000) +T714C 002:559.171 - 0.015ms returns 0 +T714C 002:559.188 JLINK_WriteReg(R9, 0x30500458) +T714C 002:559.203 - 0.015ms returns 0 +T714C 002:559.219 JLINK_WriteReg(R10, 0x00000000) +T714C 002:559.236 - 0.016ms returns 0 +T714C 002:559.252 JLINK_WriteReg(R11, 0x00000000) +T714C 002:559.268 - 0.016ms returns 0 +T714C 002:559.285 JLINK_WriteReg(R12, 0x00000000) +T714C 002:559.301 - 0.016ms returns 0 +T714C 002:559.317 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:559.334 - 0.016ms returns 0 +T714C 002:559.350 JLINK_WriteReg(R14, 0x30500001) +T714C 002:559.366 - 0.015ms returns 0 +T714C 002:559.382 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:559.397 - 0.016ms returns 0 +T714C 002:559.414 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:559.430 - 0.016ms returns 0 +T714C 002:559.446 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:559.462 - 0.016ms returns 0 +T714C 002:559.478 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:559.494 - 0.015ms returns 0 +T714C 002:559.511 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:559.527 - 0.016ms returns 0 +T714C 002:559.544 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:559.560 - 0.016ms returns 0x00000090 +T714C 002:559.576 JLINK_Go() +T714C 002:559.594 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:559.836 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:561.687 - 2.111ms +T714C 002:561.719 JLINK_IsHalted() +T714C 002:561.933 - 0.213ms returns FALSE +T714C 002:561.953 JLINK_HasError() +T714C 002:563.600 JLINK_IsHalted() +T714C 002:565.918 - 2.318ms returns TRUE +T714C 002:566.054 JLINK_ReadReg(R15 (PC)) +T714C 002:566.127 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:566.444 - 0.389ms returns 0x30500000 +T714C 002:566.492 JLINK_ClrBPEx(BPHandle = 0x00000090) +T714C 002:566.511 - 0.018ms returns 0x00 +T714C 002:566.528 JLINK_ReadReg(R0) +T714C 002:566.546 - 0.017ms returns 0x00000000 +T714C 002:567.137 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:567.170 Data: 40 F2 44 20 C2 F2 00 00 29 46 02 F0 4F FF 30 46 ... +T714C 002:567.201 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:568.126 - 0.989ms returns 0x100 +T714C 002:568.158 JLINK_HasError() +T714C 002:568.176 JLINK_WriteReg(R0, 0x28011200) +T714C 002:568.195 - 0.019ms returns 0 +T714C 002:568.211 JLINK_WriteReg(R1, 0x00000100) +T714C 002:568.228 - 0.017ms returns 0 +T714C 002:568.245 JLINK_WriteReg(R2, 0x30500674) +T714C 002:568.264 - 0.019ms returns 0 +T714C 002:568.281 JLINK_WriteReg(R3, 0x00000000) +T714C 002:568.297 - 0.015ms returns 0 +T714C 002:568.313 JLINK_WriteReg(R4, 0x00000000) +T714C 002:568.329 - 0.016ms returns 0 +T714C 002:568.345 JLINK_WriteReg(R5, 0x00000000) +T714C 002:568.361 - 0.015ms returns 0 +T714C 002:568.377 JLINK_WriteReg(R6, 0x00000000) +T714C 002:568.393 - 0.016ms returns 0 +T714C 002:568.409 JLINK_WriteReg(R7, 0x00000000) +T714C 002:568.425 - 0.015ms returns 0 +T714C 002:568.441 JLINK_WriteReg(R8, 0x00000000) +T714C 002:568.458 - 0.016ms returns 0 +T714C 002:568.474 JLINK_WriteReg(R9, 0x30500458) +T714C 002:568.496 - 0.022ms returns 0 +T714C 002:568.514 JLINK_WriteReg(R10, 0x00000000) +T714C 002:568.530 - 0.016ms returns 0 +T714C 002:568.589 JLINK_WriteReg(R11, 0x00000000) +T714C 002:568.615 - 0.025ms returns 0 +T714C 002:568.632 JLINK_WriteReg(R12, 0x00000000) +T714C 002:568.648 - 0.016ms returns 0 +T714C 002:568.666 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:568.683 - 0.017ms returns 0 +T714C 002:568.699 JLINK_WriteReg(R14, 0x30500001) +T714C 002:568.716 - 0.017ms returns 0 +T714C 002:568.732 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:568.749 - 0.016ms returns 0 +T714C 002:568.786 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:568.804 - 0.017ms returns 0 +T714C 002:568.820 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:568.838 - 0.017ms returns 0 +T714C 002:568.854 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:568.870 - 0.016ms returns 0 +T714C 002:568.887 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:568.903 - 0.016ms returns 0 +T714C 002:568.920 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:568.936 - 0.016ms returns 0x00000091 +T714C 002:568.953 JLINK_Go() +T714C 002:568.971 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:569.327 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:571.287 - 2.333ms +T714C 002:571.334 JLINK_IsHalted() +T714C 002:571.598 - 0.263ms returns FALSE +T714C 002:571.628 JLINK_HasError() +T714C 002:573.019 JLINK_IsHalted() +T714C 002:575.266 - 2.246ms returns TRUE +T714C 002:575.298 JLINK_ReadReg(R15 (PC)) +T714C 002:575.317 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:575.590 - 0.290ms returns 0x30500000 +T714C 002:575.628 JLINK_ClrBPEx(BPHandle = 0x00000091) +T714C 002:575.646 - 0.017ms returns 0x00 +T714C 002:575.663 JLINK_ReadReg(R0) +T714C 002:575.681 - 0.018ms returns 0x00000000 +T714C 002:576.354 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:576.387 Data: 00 22 20 46 02 F0 D2 FE 00 2D 08 BF BD E8 F0 81 ... +T714C 002:576.419 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:577.421 - 1.067ms returns 0x100 +T714C 002:577.455 JLINK_HasError() +T714C 002:577.472 JLINK_WriteReg(R0, 0x28011300) +T714C 002:577.490 - 0.018ms returns 0 +T714C 002:577.508 JLINK_WriteReg(R1, 0x00000100) +T714C 002:577.525 - 0.016ms returns 0 +T714C 002:577.544 JLINK_WriteReg(R2, 0x30500674) +T714C 002:577.561 - 0.016ms returns 0 +T714C 002:577.577 JLINK_WriteReg(R3, 0x00000000) +T714C 002:577.593 - 0.015ms returns 0 +T714C 002:577.609 JLINK_WriteReg(R4, 0x00000000) +T714C 002:577.625 - 0.015ms returns 0 +T714C 002:577.641 JLINK_WriteReg(R5, 0x00000000) +T714C 002:577.657 - 0.016ms returns 0 +T714C 002:577.673 JLINK_WriteReg(R6, 0x00000000) +T714C 002:577.689 - 0.016ms returns 0 +T714C 002:577.706 JLINK_WriteReg(R7, 0x00000000) +T714C 002:577.721 - 0.015ms returns 0 +T714C 002:577.738 JLINK_WriteReg(R8, 0x00000000) +T714C 002:577.754 - 0.015ms returns 0 +T714C 002:577.770 JLINK_WriteReg(R9, 0x30500458) +T714C 002:577.786 - 0.015ms returns 0 +T714C 002:577.802 JLINK_WriteReg(R10, 0x00000000) +T714C 002:577.818 - 0.016ms returns 0 +T714C 002:577.835 JLINK_WriteReg(R11, 0x00000000) +T714C 002:577.851 - 0.016ms returns 0 +T714C 002:577.867 JLINK_WriteReg(R12, 0x00000000) +T714C 002:577.883 - 0.016ms returns 0 +T714C 002:577.899 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:577.916 - 0.016ms returns 0 +T714C 002:577.932 JLINK_WriteReg(R14, 0x30500001) +T714C 002:577.948 - 0.015ms returns 0 +T714C 002:577.964 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:577.980 - 0.015ms returns 0 +T714C 002:577.997 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:578.012 - 0.016ms returns 0 +T714C 002:578.029 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:578.045 - 0.015ms returns 0 +T714C 002:578.061 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:578.077 - 0.015ms returns 0 +T714C 002:578.093 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:578.109 - 0.015ms returns 0 +T714C 002:578.125 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:578.141 - 0.016ms returns 0x00000092 +T714C 002:578.157 JLINK_Go() +T714C 002:578.175 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:578.439 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:580.185 - 2.028ms +T714C 002:580.810 JLINK_IsHalted() +T714C 002:582.962 - 2.152ms returns TRUE +T714C 002:583.014 JLINK_ReadReg(R15 (PC)) +T714C 002:583.035 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:583.316 - 0.302ms returns 0x30500000 +T714C 002:583.339 JLINK_ClrBPEx(BPHandle = 0x00000092) +T714C 002:583.356 - 0.017ms returns 0x00 +T714C 002:583.372 JLINK_ReadReg(R0) +T714C 002:583.389 - 0.016ms returns 0x00000000 +T714C 002:584.227 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:584.314 Data: C2 F6 01 00 C2 F6 01 01 E4 22 FF F7 23 FD 60 8B ... +T714C 002:584.349 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:585.324 - 1.097ms returns 0x100 +T714C 002:585.365 JLINK_HasError() +T714C 002:585.383 JLINK_WriteReg(R0, 0x28011400) +T714C 002:585.405 - 0.021ms returns 0 +T714C 002:585.422 JLINK_WriteReg(R1, 0x00000100) +T714C 002:585.438 - 0.016ms returns 0 +T714C 002:585.455 JLINK_WriteReg(R2, 0x30500674) +T714C 002:585.471 - 0.016ms returns 0 +T714C 002:585.487 JLINK_WriteReg(R3, 0x00000000) +T714C 002:585.503 - 0.015ms returns 0 +T714C 002:585.520 JLINK_WriteReg(R4, 0x00000000) +T714C 002:585.535 - 0.015ms returns 0 +T714C 002:585.552 JLINK_WriteReg(R5, 0x00000000) +T714C 002:585.567 - 0.015ms returns 0 +T714C 002:585.583 JLINK_WriteReg(R6, 0x00000000) +T714C 002:585.599 - 0.015ms returns 0 +T714C 002:585.615 JLINK_WriteReg(R7, 0x00000000) +T714C 002:585.631 - 0.015ms returns 0 +T714C 002:585.647 JLINK_WriteReg(R8, 0x00000000) +T714C 002:585.663 - 0.015ms returns 0 +T714C 002:585.679 JLINK_WriteReg(R9, 0x30500458) +T714C 002:585.695 - 0.015ms returns 0 +T714C 002:585.711 JLINK_WriteReg(R10, 0x00000000) +T714C 002:585.727 - 0.015ms returns 0 +T714C 002:585.743 JLINK_WriteReg(R11, 0x00000000) +T714C 002:585.759 - 0.015ms returns 0 +T714C 002:585.775 JLINK_WriteReg(R12, 0x00000000) +T714C 002:585.790 - 0.015ms returns 0 +T714C 002:585.807 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:585.823 - 0.016ms returns 0 +T714C 002:585.840 JLINK_WriteReg(R14, 0x30500001) +T714C 002:585.856 - 0.015ms returns 0 +T714C 002:585.872 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:585.889 - 0.016ms returns 0 +T714C 002:585.906 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:585.922 - 0.016ms returns 0 +T714C 002:585.938 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:585.954 - 0.016ms returns 0 +T714C 002:585.971 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:585.987 - 0.015ms returns 0 +T714C 002:586.002 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:586.019 - 0.016ms returns 0 +T714C 002:586.035 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:586.082 - 0.046ms returns 0x00000093 +T714C 002:586.098 JLINK_Go() +T714C 002:586.116 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:586.421 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:588.320 - 2.221ms +T714C 002:588.362 JLINK_IsHalted() +T714C 002:588.652 - 0.289ms returns FALSE +T714C 002:588.683 JLINK_HasError() +T714C 002:589.821 JLINK_IsHalted() +T714C 002:591.945 - 2.123ms returns TRUE +T714C 002:591.984 JLINK_ReadReg(R15 (PC)) +T714C 002:592.003 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:592.325 - 0.341ms returns 0x30500000 +T714C 002:592.348 JLINK_ClrBPEx(BPHandle = 0x00000093) +T714C 002:592.364 - 0.016ms returns 0x00 +T714C 002:592.381 JLINK_ReadReg(R0) +T714C 002:592.398 - 0.016ms returns 0x00000000 +T714C 002:592.992 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:593.026 Data: 01 00 C2 F6 01 01 40 F2 57 12 FF F7 A3 FC 30 46 ... +T714C 002:593.061 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:594.061 - 1.068ms returns 0x100 +T714C 002:594.085 JLINK_HasError() +T714C 002:594.102 JLINK_WriteReg(R0, 0x28011500) +T714C 002:594.120 - 0.018ms returns 0 +T714C 002:594.137 JLINK_WriteReg(R1, 0x00000100) +T714C 002:594.153 - 0.016ms returns 0 +T714C 002:594.169 JLINK_WriteReg(R2, 0x30500674) +T714C 002:594.185 - 0.015ms returns 0 +T714C 002:594.202 JLINK_WriteReg(R3, 0x00000000) +T714C 002:594.218 - 0.016ms returns 0 +T714C 002:594.235 JLINK_WriteReg(R4, 0x00000000) +T714C 002:594.251 - 0.016ms returns 0 +T714C 002:594.267 JLINK_WriteReg(R5, 0x00000000) +T714C 002:594.345 - 0.077ms returns 0 +T714C 002:594.364 JLINK_WriteReg(R6, 0x00000000) +T714C 002:594.380 - 0.016ms returns 0 +T714C 002:594.397 JLINK_WriteReg(R7, 0x00000000) +T714C 002:594.412 - 0.015ms returns 0 +T714C 002:594.429 JLINK_WriteReg(R8, 0x00000000) +T714C 002:594.445 - 0.016ms returns 0 +T714C 002:594.461 JLINK_WriteReg(R9, 0x30500458) +T714C 002:594.477 - 0.015ms returns 0 +T714C 002:594.493 JLINK_WriteReg(R10, 0x00000000) +T714C 002:594.508 - 0.015ms returns 0 +T714C 002:594.538 JLINK_WriteReg(R11, 0x00000000) +T714C 002:594.555 - 0.016ms returns 0 +T714C 002:594.573 JLINK_WriteReg(R12, 0x00000000) +T714C 002:594.590 - 0.016ms returns 0 +T714C 002:594.607 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:594.625 - 0.018ms returns 0 +T714C 002:594.643 JLINK_WriteReg(R14, 0x30500001) +T714C 002:594.660 - 0.017ms returns 0 +T714C 002:594.678 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:594.695 - 0.017ms returns 0 +T714C 002:594.713 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:594.729 - 0.015ms returns 0 +T714C 002:594.745 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:594.762 - 0.016ms returns 0 +T714C 002:594.778 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:594.793 - 0.015ms returns 0 +T714C 002:594.810 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:594.826 - 0.016ms returns 0 +T714C 002:594.843 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:594.859 - 0.016ms returns 0x00000094 +T714C 002:594.875 JLINK_Go() +T714C 002:594.893 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:595.163 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:597.073 - 2.198ms +T714C 002:597.096 JLINK_IsHalted() +T714C 002:597.344 - 0.248ms returns FALSE +T714C 002:597.366 JLINK_HasError() +T714C 002:598.824 JLINK_IsHalted() +T714C 002:601.058 - 2.234ms returns TRUE +T714C 002:601.123 JLINK_ReadReg(R15 (PC)) +T714C 002:601.151 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:601.415 - 0.293ms returns 0x30500000 +T714C 002:601.443 JLINK_ClrBPEx(BPHandle = 0x00000094) +T714C 002:601.460 - 0.017ms returns 0x00 +T714C 002:601.478 JLINK_ReadReg(R0) +T714C 002:601.494 - 0.016ms returns 0x00000000 +T714C 002:602.645 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:602.695 Data: 01 01 4F F4 C1 72 FF F7 25 FC 30 46 01 F0 C8 FA ... +T714C 002:602.730 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:603.708 - 1.062ms returns 0x100 +T714C 002:603.747 JLINK_HasError() +T714C 002:603.876 JLINK_WriteReg(R0, 0x28011600) +T714C 002:603.897 - 0.020ms returns 0 +T714C 002:603.914 JLINK_WriteReg(R1, 0x00000100) +T714C 002:603.931 - 0.016ms returns 0 +T714C 002:603.948 JLINK_WriteReg(R2, 0x30500674) +T714C 002:603.964 - 0.015ms returns 0 +T714C 002:603.981 JLINK_WriteReg(R3, 0x00000000) +T714C 002:603.997 - 0.016ms returns 0 +T714C 002:604.027 JLINK_WriteReg(R4, 0x00000000) +T714C 002:604.045 - 0.017ms returns 0 +T714C 002:604.062 JLINK_WriteReg(R5, 0x00000000) +T714C 002:604.078 - 0.016ms returns 0 +T714C 002:604.094 JLINK_WriteReg(R6, 0x00000000) +T714C 002:604.111 - 0.017ms returns 0 +T714C 002:604.127 JLINK_WriteReg(R7, 0x00000000) +T714C 002:604.143 - 0.016ms returns 0 +T714C 002:604.160 JLINK_WriteReg(R8, 0x00000000) +T714C 002:604.176 - 0.016ms returns 0 +T714C 002:604.192 JLINK_WriteReg(R9, 0x30500458) +T714C 002:604.208 - 0.015ms returns 0 +T714C 002:604.225 JLINK_WriteReg(R10, 0x00000000) +T714C 002:604.241 - 0.016ms returns 0 +T714C 002:604.257 JLINK_WriteReg(R11, 0x00000000) +T714C 002:604.287 - 0.029ms returns 0 +T714C 002:604.304 JLINK_WriteReg(R12, 0x00000000) +T714C 002:604.320 - 0.016ms returns 0 +T714C 002:604.336 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:604.354 - 0.017ms returns 0 +T714C 002:604.370 JLINK_WriteReg(R14, 0x30500001) +T714C 002:604.386 - 0.015ms returns 0 +T714C 002:604.402 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:604.419 - 0.017ms returns 0 +T714C 002:604.436 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:604.454 - 0.018ms returns 0 +T714C 002:604.471 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:604.488 - 0.017ms returns 0 +T714C 002:604.506 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:604.596 - 0.089ms returns 0 +T714C 002:604.616 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:604.632 - 0.016ms returns 0 +T714C 002:604.650 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:604.667 - 0.016ms returns 0x00000095 +T714C 002:604.684 JLINK_Go() +T714C 002:604.703 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:604.962 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:606.905 - 2.220ms +T714C 002:606.954 JLINK_IsHalted() +T714C 002:607.186 - 0.231ms returns FALSE +T714C 002:607.211 JLINK_HasError() +T714C 002:610.820 JLINK_IsHalted() +T714C 002:612.910 - 2.089ms returns TRUE +T714C 002:612.937 JLINK_ReadReg(R15 (PC)) +T714C 002:612.957 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:613.188 - 0.250ms returns 0x30500000 +T714C 002:613.209 JLINK_ClrBPEx(BPHandle = 0x00000095) +T714C 002:613.225 - 0.016ms returns 0x00 +T714C 002:613.242 JLINK_ReadReg(R0) +T714C 002:613.258 - 0.016ms returns 0x00000000 +T714C 002:613.753 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:613.787 Data: 00 00 03 68 7B B1 46 F6 D9 10 46 F6 59 21 C2 F6 ... +T714C 002:613.818 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:614.792 - 1.039ms returns 0x100 +T714C 002:614.822 JLINK_HasError() +T714C 002:614.840 JLINK_WriteReg(R0, 0x28011700) +T714C 002:614.858 - 0.018ms returns 0 +T714C 002:614.875 JLINK_WriteReg(R1, 0x00000100) +T714C 002:614.892 - 0.016ms returns 0 +T714C 002:614.909 JLINK_WriteReg(R2, 0x30500674) +T714C 002:614.926 - 0.016ms returns 0 +T714C 002:614.942 JLINK_WriteReg(R3, 0x00000000) +T714C 002:614.958 - 0.015ms returns 0 +T714C 002:614.974 JLINK_WriteReg(R4, 0x00000000) +T714C 002:614.990 - 0.015ms returns 0 +T714C 002:615.006 JLINK_WriteReg(R5, 0x00000000) +T714C 002:615.022 - 0.015ms returns 0 +T714C 002:615.038 JLINK_WriteReg(R6, 0x00000000) +T714C 002:615.053 - 0.015ms returns 0 +T714C 002:615.070 JLINK_WriteReg(R7, 0x00000000) +T714C 002:615.087 - 0.017ms returns 0 +T714C 002:615.103 JLINK_WriteReg(R8, 0x00000000) +T714C 002:615.120 - 0.016ms returns 0 +T714C 002:615.136 JLINK_WriteReg(R9, 0x30500458) +T714C 002:615.152 - 0.016ms returns 0 +T714C 002:615.169 JLINK_WriteReg(R10, 0x00000000) +T714C 002:615.185 - 0.016ms returns 0 +T714C 002:615.201 JLINK_WriteReg(R11, 0x00000000) +T714C 002:615.217 - 0.015ms returns 0 +T714C 002:615.234 JLINK_WriteReg(R12, 0x00000000) +T714C 002:615.250 - 0.015ms returns 0 +T714C 002:615.266 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:615.283 - 0.017ms returns 0 +T714C 002:615.299 JLINK_WriteReg(R14, 0x30500001) +T714C 002:615.315 - 0.016ms returns 0 +T714C 002:615.331 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:615.347 - 0.015ms returns 0 +T714C 002:615.363 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:615.379 - 0.015ms returns 0 +T714C 002:615.396 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:615.411 - 0.015ms returns 0 +T714C 002:615.428 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:615.444 - 0.015ms returns 0 +T714C 002:615.460 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:615.476 - 0.015ms returns 0 +T714C 002:615.495 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:615.512 - 0.017ms returns 0x00000096 +T714C 002:615.528 JLINK_Go() +T714C 002:615.546 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:615.926 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:617.937 - 2.408ms +T714C 002:617.995 JLINK_IsHalted() +T714C 002:618.248 - 0.253ms returns FALSE +T714C 002:618.318 JLINK_HasError() +T714C 002:620.317 JLINK_IsHalted() +T714C 002:622.446 - 2.127ms returns TRUE +T714C 002:622.476 JLINK_ReadReg(R15 (PC)) +T714C 002:622.496 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:622.737 - 0.260ms returns 0x30500000 +T714C 002:622.757 JLINK_ClrBPEx(BPHandle = 0x00000096) +T714C 002:622.774 - 0.017ms returns 0x00 +T714C 002:622.790 JLINK_ReadReg(R0) +T714C 002:622.807 - 0.016ms returns 0x00000000 +T714C 002:623.422 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:623.456 Data: F5 FB 46 F6 43 20 C2 F6 01 00 06 A1 00 F0 EE FB ... +T714C 002:623.490 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:624.474 - 1.051ms returns 0x100 +T714C 002:624.506 JLINK_HasError() +T714C 002:624.534 JLINK_WriteReg(R0, 0x28011800) +T714C 002:624.553 - 0.019ms returns 0 +T714C 002:624.570 JLINK_WriteReg(R1, 0x00000100) +T714C 002:624.587 - 0.016ms returns 0 +T714C 002:624.603 JLINK_WriteReg(R2, 0x30500674) +T714C 002:624.620 - 0.016ms returns 0 +T714C 002:624.636 JLINK_WriteReg(R3, 0x00000000) +T714C 002:624.652 - 0.015ms returns 0 +T714C 002:624.668 JLINK_WriteReg(R4, 0x00000000) +T714C 002:624.684 - 0.015ms returns 0 +T714C 002:624.700 JLINK_WriteReg(R5, 0x00000000) +T714C 002:624.716 - 0.016ms returns 0 +T714C 002:624.732 JLINK_WriteReg(R6, 0x00000000) +T714C 002:624.748 - 0.016ms returns 0 +T714C 002:624.764 JLINK_WriteReg(R7, 0x00000000) +T714C 002:624.780 - 0.015ms returns 0 +T714C 002:624.798 JLINK_WriteReg(R8, 0x00000000) +T714C 002:624.814 - 0.016ms returns 0 +T714C 002:624.830 JLINK_WriteReg(R9, 0x30500458) +T714C 002:624.846 - 0.015ms returns 0 +T714C 002:624.863 JLINK_WriteReg(R10, 0x00000000) +T714C 002:624.879 - 0.015ms returns 0 +T714C 002:624.895 JLINK_WriteReg(R11, 0x00000000) +T714C 002:624.911 - 0.015ms returns 0 +T714C 002:624.927 JLINK_WriteReg(R12, 0x00000000) +T714C 002:624.942 - 0.015ms returns 0 +T714C 002:624.958 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:624.976 - 0.017ms returns 0 +T714C 002:624.992 JLINK_WriteReg(R14, 0x30500001) +T714C 002:625.008 - 0.015ms returns 0 +T714C 002:625.024 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:625.068 - 0.044ms returns 0 +T714C 002:625.085 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:625.100 - 0.016ms returns 0 +T714C 002:625.117 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:625.133 - 0.015ms returns 0 +T714C 002:625.149 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:625.164 - 0.015ms returns 0 +T714C 002:625.181 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:625.196 - 0.015ms returns 0 +T714C 002:625.213 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:625.230 - 0.017ms returns 0x00000097 +T714C 002:625.246 JLINK_Go() +T714C 002:625.265 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:625.580 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:627.412 - 2.165ms +T714C 002:627.435 JLINK_IsHalted() +T714C 002:627.653 - 0.218ms returns FALSE +T714C 002:627.673 JLINK_HasError() +T714C 002:628.886 JLINK_IsHalted() +T714C 002:630.920 - 2.033ms returns TRUE +T714C 002:630.949 JLINK_ReadReg(R15 (PC)) +T714C 002:630.977 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:631.298 - 0.347ms returns 0x30500000 +T714C 002:631.381 JLINK_ClrBPEx(BPHandle = 0x00000097) +T714C 002:631.407 - 0.026ms returns 0x00 +T714C 002:631.431 JLINK_ReadReg(R0) +T714C 002:631.453 - 0.022ms returns 0x00000000 +T714C 002:632.257 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:632.316 Data: 6F 63 6B 3A 20 25 64 20 48 7A 0A 00 48 65 61 70 ... +T714C 002:632.366 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:633.372 - 1.114ms returns 0x100 +T714C 002:633.430 JLINK_HasError() +T714C 002:633.452 JLINK_WriteReg(R0, 0x28011900) +T714C 002:633.474 - 0.021ms returns 0 +T714C 002:633.492 JLINK_WriteReg(R1, 0x00000100) +T714C 002:633.510 - 0.017ms returns 0 +T714C 002:633.529 JLINK_WriteReg(R2, 0x30500674) +T714C 002:633.547 - 0.017ms returns 0 +T714C 002:633.566 JLINK_WriteReg(R3, 0x00000000) +T714C 002:633.584 - 0.017ms returns 0 +T714C 002:633.604 JLINK_WriteReg(R4, 0x00000000) +T714C 002:633.621 - 0.017ms returns 0 +T714C 002:633.639 JLINK_WriteReg(R5, 0x00000000) +T714C 002:633.656 - 0.016ms returns 0 +T714C 002:633.675 JLINK_WriteReg(R6, 0x00000000) +T714C 002:633.692 - 0.017ms returns 0 +T714C 002:633.712 JLINK_WriteReg(R7, 0x00000000) +T714C 002:633.729 - 0.017ms returns 0 +T714C 002:633.748 JLINK_WriteReg(R8, 0x00000000) +T714C 002:633.765 - 0.017ms returns 0 +T714C 002:633.782 JLINK_WriteReg(R9, 0x30500458) +T714C 002:633.798 - 0.016ms returns 0 +T714C 002:633.816 JLINK_WriteReg(R10, 0x00000000) +T714C 002:633.834 - 0.017ms returns 0 +T714C 002:633.852 JLINK_WriteReg(R11, 0x00000000) +T714C 002:633.869 - 0.017ms returns 0 +T714C 002:633.888 JLINK_WriteReg(R12, 0x00000000) +T714C 002:633.905 - 0.017ms returns 0 +T714C 002:633.923 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:633.950 - 0.027ms returns 0 +T714C 002:633.969 JLINK_WriteReg(R14, 0x30500001) +T714C 002:633.986 - 0.017ms returns 0 +T714C 002:634.004 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:634.021 - 0.017ms returns 0 +T714C 002:634.040 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:634.057 - 0.017ms returns 0 +T714C 002:634.075 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:634.092 - 0.017ms returns 0 +T714C 002:634.110 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:634.128 - 0.017ms returns 0 +T714C 002:634.146 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:634.163 - 0.017ms returns 0 +T714C 002:634.182 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:634.200 - 0.018ms returns 0x00000098 +T714C 002:634.218 JLINK_Go() +T714C 002:634.239 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:634.513 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:636.436 - 2.217ms +T714C 002:636.473 JLINK_IsHalted() +T714C 002:636.680 - 0.206ms returns FALSE +T714C 002:636.703 JLINK_HasError() +T714C 002:637.871 JLINK_IsHalted() +T714C 002:639.963 - 2.091ms returns TRUE +T714C 002:639.996 JLINK_ReadReg(R15 (PC)) +T714C 002:640.015 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:640.263 - 0.266ms returns 0x30500000 +T714C 002:640.284 JLINK_ClrBPEx(BPHandle = 0x00000098) +T714C 002:640.300 - 0.016ms returns 0x00 +T714C 002:640.317 JLINK_ReadReg(R0) +T714C 002:640.334 - 0.017ms returns 0x00000000 +T714C 002:640.894 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:640.929 Data: C2 10 C2 F6 01 00 00 F0 F1 FA 0A E0 02 F0 A8 FE ... +T714C 002:640.960 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:641.906 - 1.011ms returns 0x100 +T714C 002:641.931 JLINK_HasError() +T714C 002:641.948 JLINK_WriteReg(R0, 0x28011A00) +T714C 002:641.967 - 0.018ms returns 0 +T714C 002:641.984 JLINK_WriteReg(R1, 0x00000100) +T714C 002:642.000 - 0.016ms returns 0 +T714C 002:642.018 JLINK_WriteReg(R2, 0x30500674) +T714C 002:642.034 - 0.016ms returns 0 +T714C 002:642.050 JLINK_WriteReg(R3, 0x00000000) +T714C 002:642.066 - 0.015ms returns 0 +T714C 002:642.082 JLINK_WriteReg(R4, 0x00000000) +T714C 002:642.098 - 0.015ms returns 0 +T714C 002:642.114 JLINK_WriteReg(R5, 0x00000000) +T714C 002:642.130 - 0.015ms returns 0 +T714C 002:642.147 JLINK_WriteReg(R6, 0x00000000) +T714C 002:642.162 - 0.015ms returns 0 +T714C 002:642.178 JLINK_WriteReg(R7, 0x00000000) +T714C 002:642.195 - 0.016ms returns 0 +T714C 002:642.212 JLINK_WriteReg(R8, 0x00000000) +T714C 002:642.227 - 0.015ms returns 0 +T714C 002:642.243 JLINK_WriteReg(R9, 0x30500458) +T714C 002:642.259 - 0.015ms returns 0 +T714C 002:642.275 JLINK_WriteReg(R10, 0x00000000) +T714C 002:642.291 - 0.015ms returns 0 +T714C 002:642.307 JLINK_WriteReg(R11, 0x00000000) +T714C 002:642.323 - 0.015ms returns 0 +T714C 002:642.339 JLINK_WriteReg(R12, 0x00000000) +T714C 002:642.354 - 0.015ms returns 0 +T714C 002:642.371 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:642.387 - 0.016ms returns 0 +T714C 002:642.404 JLINK_WriteReg(R14, 0x30500001) +T714C 002:642.420 - 0.015ms returns 0 +T714C 002:642.436 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:642.452 - 0.016ms returns 0 +T714C 002:642.469 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:642.485 - 0.016ms returns 0 +T714C 002:642.501 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:642.517 - 0.015ms returns 0 +T714C 002:642.533 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:642.548 - 0.015ms returns 0 +T714C 002:642.564 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:642.580 - 0.015ms returns 0 +T714C 002:642.597 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:642.614 - 0.017ms returns 0x00000099 +T714C 002:642.630 JLINK_Go() +T714C 002:642.648 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:642.906 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:644.836 - 2.205ms +T714C 002:644.858 JLINK_IsHalted() +T714C 002:645.085 - 0.226ms returns FALSE +T714C 002:645.104 JLINK_HasError() +T714C 002:646.890 JLINK_IsHalted() +T714C 002:649.099 - 2.208ms returns TRUE +T714C 002:649.160 JLINK_ReadReg(R15 (PC)) +T714C 002:649.181 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:649.505 - 0.344ms returns 0x30500000 +T714C 002:649.553 JLINK_ClrBPEx(BPHandle = 0x00000099) +T714C 002:649.571 - 0.018ms returns 0x00 +T714C 002:649.589 JLINK_ReadReg(R0) +T714C 002:649.606 - 0.017ms returns 0x00000000 +T714C 002:650.234 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:650.268 Data: 07 20 C2 F6 01 00 00 F0 71 FA 14 F8 01 1C 47 F2 ... +T714C 002:650.303 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:651.366 - 1.132ms returns 0x100 +T714C 002:651.390 JLINK_HasError() +T714C 002:651.408 JLINK_WriteReg(R0, 0x28011B00) +T714C 002:651.426 - 0.018ms returns 0 +T714C 002:651.443 JLINK_WriteReg(R1, 0x00000100) +T714C 002:651.459 - 0.016ms returns 0 +T714C 002:651.475 JLINK_WriteReg(R2, 0x30500674) +T714C 002:651.491 - 0.015ms returns 0 +T714C 002:651.508 JLINK_WriteReg(R3, 0x00000000) +T714C 002:651.524 - 0.016ms returns 0 +T714C 002:651.540 JLINK_WriteReg(R4, 0x00000000) +T714C 002:651.556 - 0.016ms returns 0 +T714C 002:651.572 JLINK_WriteReg(R5, 0x00000000) +T714C 002:651.589 - 0.016ms returns 0 +T714C 002:651.605 JLINK_WriteReg(R6, 0x00000000) +T714C 002:651.621 - 0.016ms returns 0 +T714C 002:651.637 JLINK_WriteReg(R7, 0x00000000) +T714C 002:651.653 - 0.015ms returns 0 +T714C 002:651.670 JLINK_WriteReg(R8, 0x00000000) +T714C 002:651.686 - 0.016ms returns 0 +T714C 002:651.702 JLINK_WriteReg(R9, 0x30500458) +T714C 002:651.718 - 0.015ms returns 0 +T714C 002:651.734 JLINK_WriteReg(R10, 0x00000000) +T714C 002:651.750 - 0.016ms returns 0 +T714C 002:651.766 JLINK_WriteReg(R11, 0x00000000) +T714C 002:651.783 - 0.016ms returns 0 +T714C 002:651.799 JLINK_WriteReg(R12, 0x00000000) +T714C 002:651.814 - 0.015ms returns 0 +T714C 002:651.831 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:651.848 - 0.017ms returns 0 +T714C 002:651.864 JLINK_WriteReg(R14, 0x30500001) +T714C 002:651.879 - 0.015ms returns 0 +T714C 002:651.896 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:651.912 - 0.016ms returns 0 +T714C 002:651.928 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:651.945 - 0.016ms returns 0 +T714C 002:651.961 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:651.976 - 0.015ms returns 0 +T714C 002:651.992 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:652.008 - 0.015ms returns 0 +T714C 002:652.024 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:652.040 - 0.015ms returns 0 +T714C 002:652.057 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:652.073 - 0.016ms returns 0x0000009A +T714C 002:652.089 JLINK_Go() +T714C 002:652.107 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:652.417 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:654.300 - 2.211ms +T714C 002:654.323 JLINK_IsHalted() +T714C 002:654.581 - 0.257ms returns FALSE +T714C 002:654.601 JLINK_HasError() +T714C 002:656.329 JLINK_IsHalted() +T714C 002:658.535 - 2.206ms returns TRUE +T714C 002:658.557 JLINK_ReadReg(R15 (PC)) +T714C 002:658.574 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:658.844 - 0.287ms returns 0x30500000 +T714C 002:658.865 JLINK_ClrBPEx(BPHandle = 0x0000009A) +T714C 002:658.881 - 0.016ms returns 0x00 +T714C 002:658.897 JLINK_ReadReg(R0) +T714C 002:658.913 - 0.016ms returns 0x00000000 +T714C 002:659.348 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:659.380 Data: 01 00 00 F0 F3 F9 B4 F8 01 00 C0 05 05 D5 47 F2 ... +T714C 002:659.408 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:660.457 - 1.109ms returns 0x100 +T714C 002:660.481 JLINK_HasError() +T714C 002:660.498 JLINK_WriteReg(R0, 0x28011C00) +T714C 002:660.515 - 0.017ms returns 0 +T714C 002:660.532 JLINK_WriteReg(R1, 0x00000100) +T714C 002:660.548 - 0.016ms returns 0 +T714C 002:660.564 JLINK_WriteReg(R2, 0x30500674) +T714C 002:660.580 - 0.016ms returns 0 +T714C 002:660.596 JLINK_WriteReg(R3, 0x00000000) +T714C 002:660.611 - 0.015ms returns 0 +T714C 002:660.627 JLINK_WriteReg(R4, 0x00000000) +T714C 002:660.643 - 0.016ms returns 0 +T714C 002:660.660 JLINK_WriteReg(R5, 0x00000000) +T714C 002:660.677 - 0.016ms returns 0 +T714C 002:660.693 JLINK_WriteReg(R6, 0x00000000) +T714C 002:660.709 - 0.016ms returns 0 +T714C 002:660.725 JLINK_WriteReg(R7, 0x00000000) +T714C 002:660.741 - 0.015ms returns 0 +T714C 002:660.764 JLINK_WriteReg(R8, 0x00000000) +T714C 002:660.780 - 0.015ms returns 0 +T714C 002:660.796 JLINK_WriteReg(R9, 0x30500458) +T714C 002:660.812 - 0.016ms returns 0 +T714C 002:660.829 JLINK_WriteReg(R10, 0x00000000) +T714C 002:660.844 - 0.015ms returns 0 +T714C 002:660.860 JLINK_WriteReg(R11, 0x00000000) +T714C 002:660.876 - 0.015ms returns 0 +T714C 002:660.892 JLINK_WriteReg(R12, 0x00000000) +T714C 002:660.908 - 0.015ms returns 0 +T714C 002:660.924 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:660.941 - 0.016ms returns 0 +T714C 002:660.957 JLINK_WriteReg(R14, 0x30500001) +T714C 002:660.973 - 0.015ms returns 0 +T714C 002:660.989 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:661.005 - 0.015ms returns 0 +T714C 002:661.021 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:661.036 - 0.015ms returns 0 +T714C 002:661.053 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:661.068 - 0.015ms returns 0 +T714C 002:661.085 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:661.101 - 0.016ms returns 0 +T714C 002:661.118 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:661.134 - 0.015ms returns 0 +T714C 002:661.150 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:661.166 - 0.016ms returns 0x0000009B +T714C 002:661.182 JLINK_Go() +T714C 002:661.199 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:661.565 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:663.608 - 2.424ms +T714C 002:663.668 JLINK_IsHalted() +T714C 002:663.934 - 0.266ms returns FALSE +T714C 002:663.987 JLINK_HasError() +T714C 002:666.176 JLINK_IsHalted() +T714C 002:668.393 - 2.216ms returns TRUE +T714C 002:668.445 JLINK_ReadReg(R15 (PC)) +T714C 002:668.467 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:668.714 - 0.269ms returns 0x30500000 +T714C 002:668.740 JLINK_ClrBPEx(BPHandle = 0x0000009B) +T714C 002:668.757 - 0.016ms returns 0x00 +T714C 002:668.791 JLINK_ReadReg(R0) +T714C 002:668.809 - 0.017ms returns 0x00000000 +T714C 002:669.565 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:669.603 Data: 81 B0 C9 B2 02 29 83 46 77 D0 01 29 40 F0 89 80 ... +T714C 002:669.635 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:670.582 - 1.017ms returns 0x100 +T714C 002:670.622 JLINK_HasError() +T714C 002:670.641 JLINK_WriteReg(R0, 0x28011D00) +T714C 002:670.660 - 0.019ms returns 0 +T714C 002:670.677 JLINK_WriteReg(R1, 0x00000100) +T714C 002:670.694 - 0.017ms returns 0 +T714C 002:670.722 JLINK_WriteReg(R2, 0x30500674) +T714C 002:670.739 - 0.016ms returns 0 +T714C 002:670.755 JLINK_WriteReg(R3, 0x00000000) +T714C 002:670.792 - 0.036ms returns 0 +T714C 002:670.808 JLINK_WriteReg(R4, 0x00000000) +T714C 002:670.825 - 0.016ms returns 0 +T714C 002:670.842 JLINK_WriteReg(R5, 0x00000000) +T714C 002:670.859 - 0.016ms returns 0 +T714C 002:670.876 JLINK_WriteReg(R6, 0x00000000) +T714C 002:670.892 - 0.016ms returns 0 +T714C 002:670.908 JLINK_WriteReg(R7, 0x00000000) +T714C 002:670.924 - 0.016ms returns 0 +T714C 002:670.940 JLINK_WriteReg(R8, 0x00000000) +T714C 002:670.957 - 0.017ms returns 0 +T714C 002:670.973 JLINK_WriteReg(R9, 0x30500458) +T714C 002:670.989 - 0.016ms returns 0 +T714C 002:671.005 JLINK_WriteReg(R10, 0x00000000) +T714C 002:671.035 - 0.030ms returns 0 +T714C 002:671.052 JLINK_WriteReg(R11, 0x00000000) +T714C 002:671.068 - 0.016ms returns 0 +T714C 002:671.084 JLINK_WriteReg(R12, 0x00000000) +T714C 002:671.101 - 0.017ms returns 0 +T714C 002:671.118 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:671.135 - 0.017ms returns 0 +T714C 002:671.151 JLINK_WriteReg(R14, 0x30500001) +T714C 002:671.174 - 0.022ms returns 0 +T714C 002:671.190 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:671.206 - 0.016ms returns 0 +T714C 002:671.222 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:671.238 - 0.016ms returns 0 +T714C 002:671.254 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:671.291 - 0.036ms returns 0 +T714C 002:671.308 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:671.325 - 0.016ms returns 0 +T714C 002:671.374 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:671.391 - 0.016ms returns 0 +T714C 002:671.407 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:671.424 - 0.017ms returns 0x0000009C +T714C 002:671.448 JLINK_Go() +T714C 002:671.466 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:671.714 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:673.724 - 2.276ms +T714C 002:673.775 JLINK_IsHalted() +T714C 002:673.997 - 0.221ms returns FALSE +T714C 002:674.019 JLINK_HasError() +T714C 002:675.710 JLINK_IsHalted() +T714C 002:677.839 - 2.128ms returns TRUE +T714C 002:677.882 JLINK_ReadReg(R15 (PC)) +T714C 002:677.902 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:678.190 - 0.308ms returns 0x30500000 +T714C 002:678.218 JLINK_ClrBPEx(BPHandle = 0x0000009C) +T714C 002:678.236 - 0.017ms returns 0x00 +T714C 002:678.256 JLINK_ReadReg(R0) +T714C 002:678.273 - 0.017ms returns 0x00000000 +T714C 002:678.922 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:678.962 Data: BD E8 F0 4F FF F7 9A B8 D6 1A 28 46 02 F0 4E F9 ... +T714C 002:678.993 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:679.978 - 1.056ms returns 0x100 +T714C 002:680.019 JLINK_HasError() +T714C 002:680.037 JLINK_WriteReg(R0, 0x28011E00) +T714C 002:680.056 - 0.018ms returns 0 +T714C 002:680.072 JLINK_WriteReg(R1, 0x00000100) +T714C 002:680.089 - 0.016ms returns 0 +T714C 002:680.105 JLINK_WriteReg(R2, 0x30500674) +T714C 002:680.121 - 0.016ms returns 0 +T714C 002:680.137 JLINK_WriteReg(R3, 0x00000000) +T714C 002:680.154 - 0.016ms returns 0 +T714C 002:680.170 JLINK_WriteReg(R4, 0x00000000) +T714C 002:680.186 - 0.016ms returns 0 +T714C 002:680.203 JLINK_WriteReg(R5, 0x00000000) +T714C 002:680.218 - 0.015ms returns 0 +T714C 002:680.235 JLINK_WriteReg(R6, 0x00000000) +T714C 002:680.251 - 0.015ms returns 0 +T714C 002:680.267 JLINK_WriteReg(R7, 0x00000000) +T714C 002:680.283 - 0.015ms returns 0 +T714C 002:680.299 JLINK_WriteReg(R8, 0x00000000) +T714C 002:680.315 - 0.015ms returns 0 +T714C 002:680.332 JLINK_WriteReg(R9, 0x30500458) +T714C 002:680.348 - 0.016ms returns 0 +T714C 002:680.364 JLINK_WriteReg(R10, 0x00000000) +T714C 002:680.380 - 0.016ms returns 0 +T714C 002:680.397 JLINK_WriteReg(R11, 0x00000000) +T714C 002:680.414 - 0.017ms returns 0 +T714C 002:680.430 JLINK_WriteReg(R12, 0x00000000) +T714C 002:680.446 - 0.016ms returns 0 +T714C 002:680.463 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:680.480 - 0.017ms returns 0 +T714C 002:680.497 JLINK_WriteReg(R14, 0x30500001) +T714C 002:680.512 - 0.015ms returns 0 +T714C 002:680.529 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:680.545 - 0.016ms returns 0 +T714C 002:680.561 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:680.577 - 0.016ms returns 0 +T714C 002:680.593 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:680.609 - 0.015ms returns 0 +T714C 002:680.625 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:680.642 - 0.016ms returns 0 +T714C 002:680.658 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:680.674 - 0.016ms returns 0 +T714C 002:680.690 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:680.707 - 0.016ms returns 0x0000009D +T714C 002:680.723 JLINK_Go() +T714C 002:680.741 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:680.969 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:683.007 - 2.283ms +T714C 002:683.063 JLINK_IsHalted() +T714C 002:683.340 - 0.276ms returns FALSE +T714C 002:683.362 JLINK_HasError() +T714C 002:685.208 JLINK_IsHalted() +T714C 002:687.366 - 2.157ms returns TRUE +T714C 002:687.400 JLINK_ReadReg(R15 (PC)) +T714C 002:687.421 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:687.658 - 0.258ms returns 0x30500000 +T714C 002:687.680 JLINK_ClrBPEx(BPHandle = 0x0000009D) +T714C 002:687.696 - 0.016ms returns 0x00 +T714C 002:687.714 JLINK_ReadReg(R0) +T714C 002:687.730 - 0.016ms returns 0x00000000 +T714C 002:688.315 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:688.350 Data: 53 02 CD F6 AD 64 00 BF 0E EB 02 05 04 32 16 1D ... +T714C 002:688.382 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:689.360 - 1.044ms returns 0x100 +T714C 002:689.385 JLINK_HasError() +T714C 002:689.402 JLINK_WriteReg(R0, 0x28011F00) +T714C 002:689.421 - 0.018ms returns 0 +T714C 002:689.437 JLINK_WriteReg(R1, 0x00000100) +T714C 002:689.453 - 0.016ms returns 0 +T714C 002:689.469 JLINK_WriteReg(R2, 0x30500674) +T714C 002:689.491 - 0.021ms returns 0 +T714C 002:689.509 JLINK_WriteReg(R3, 0x00000000) +T714C 002:689.524 - 0.015ms returns 0 +T714C 002:689.541 JLINK_WriteReg(R4, 0x00000000) +T714C 002:689.557 - 0.016ms returns 0 +T714C 002:689.574 JLINK_WriteReg(R5, 0x00000000) +T714C 002:689.590 - 0.015ms returns 0 +T714C 002:689.608 JLINK_WriteReg(R6, 0x00000000) +T714C 002:689.624 - 0.015ms returns 0 +T714C 002:689.640 JLINK_WriteReg(R7, 0x00000000) +T714C 002:689.657 - 0.016ms returns 0 +T714C 002:689.673 JLINK_WriteReg(R8, 0x00000000) +T714C 002:689.688 - 0.015ms returns 0 +T714C 002:689.704 JLINK_WriteReg(R9, 0x30500458) +T714C 002:689.720 - 0.015ms returns 0 +T714C 002:689.736 JLINK_WriteReg(R10, 0x00000000) +T714C 002:689.752 - 0.015ms returns 0 +T714C 002:689.768 JLINK_WriteReg(R11, 0x00000000) +T714C 002:689.784 - 0.015ms returns 0 +T714C 002:689.800 JLINK_WriteReg(R12, 0x00000000) +T714C 002:689.816 - 0.015ms returns 0 +T714C 002:689.832 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:689.848 - 0.016ms returns 0 +T714C 002:689.864 JLINK_WriteReg(R14, 0x30500001) +T714C 002:689.880 - 0.015ms returns 0 +T714C 002:689.896 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:689.912 - 0.015ms returns 0 +T714C 002:689.928 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:689.944 - 0.015ms returns 0 +T714C 002:689.960 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:689.977 - 0.017ms returns 0 +T714C 002:689.993 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:690.009 - 0.016ms returns 0 +T714C 002:690.025 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:690.042 - 0.016ms returns 0 +T714C 002:690.060 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:690.076 - 0.016ms returns 0x0000009E +T714C 002:690.092 JLINK_Go() +T714C 002:690.109 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:690.383 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:692.187 - 2.094ms +T714C 002:692.949 JLINK_IsHalted() +T714C 002:695.086 - 2.136ms returns TRUE +T714C 002:695.120 JLINK_ReadReg(R15 (PC)) +T714C 002:695.139 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:695.384 - 0.263ms returns 0x30500000 +T714C 002:695.405 JLINK_ClrBPEx(BPHandle = 0x0000009E) +T714C 002:695.422 - 0.016ms returns 0x00 +T714C 002:695.441 JLINK_ReadReg(R0) +T714C 002:695.458 - 0.017ms returns 0x00000000 +T714C 002:696.176 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:696.222 Data: 00 00 7F 21 22 46 00 93 7F 24 03 F0 21 F8 01 46 ... +T714C 002:696.253 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:697.262 - 1.086ms returns 0x100 +T714C 002:697.298 JLINK_HasError() +T714C 002:697.315 JLINK_WriteReg(R0, 0x28012000) +T714C 002:697.333 - 0.018ms returns 0 +T714C 002:697.350 JLINK_WriteReg(R1, 0x00000100) +T714C 002:697.397 - 0.047ms returns 0 +T714C 002:697.413 JLINK_WriteReg(R2, 0x30500674) +T714C 002:697.430 - 0.016ms returns 0 +T714C 002:697.446 JLINK_WriteReg(R3, 0x00000000) +T714C 002:697.465 - 0.018ms returns 0 +T714C 002:697.482 JLINK_WriteReg(R4, 0x00000000) +T714C 002:697.498 - 0.016ms returns 0 +T714C 002:697.514 JLINK_WriteReg(R5, 0x00000000) +T714C 002:697.530 - 0.016ms returns 0 +T714C 002:697.546 JLINK_WriteReg(R6, 0x00000000) +T714C 002:697.562 - 0.016ms returns 0 +T714C 002:697.578 JLINK_WriteReg(R7, 0x00000000) +T714C 002:697.594 - 0.015ms returns 0 +T714C 002:697.610 JLINK_WriteReg(R8, 0x00000000) +T714C 002:697.626 - 0.016ms returns 0 +T714C 002:697.642 JLINK_WriteReg(R9, 0x30500458) +T714C 002:697.658 - 0.016ms returns 0 +T714C 002:697.675 JLINK_WriteReg(R10, 0x00000000) +T714C 002:697.690 - 0.015ms returns 0 +T714C 002:697.707 JLINK_WriteReg(R11, 0x00000000) +T714C 002:697.722 - 0.015ms returns 0 +T714C 002:697.739 JLINK_WriteReg(R12, 0x00000000) +T714C 002:697.754 - 0.015ms returns 0 +T714C 002:697.770 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:697.788 - 0.017ms returns 0 +T714C 002:697.804 JLINK_WriteReg(R14, 0x30500001) +T714C 002:697.819 - 0.015ms returns 0 +T714C 002:697.835 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:697.851 - 0.015ms returns 0 +T714C 002:697.867 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:697.883 - 0.015ms returns 0 +T714C 002:697.909 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:697.927 - 0.018ms returns 0 +T714C 002:697.943 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:697.959 - 0.015ms returns 0 +T714C 002:697.975 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:697.990 - 0.015ms returns 0 +T714C 002:698.008 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:698.025 - 0.017ms returns 0x0000009F +T714C 002:698.041 JLINK_Go() +T714C 002:698.059 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:698.347 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:700.211 - 2.169ms +T714C 002:700.272 JLINK_IsHalted() +T714C 002:700.575 - 0.302ms returns FALSE +T714C 002:700.602 JLINK_HasError() +T714C 002:702.637 JLINK_IsHalted() +T714C 002:704.720 - 2.082ms returns TRUE +T714C 002:704.744 JLINK_ReadReg(R15 (PC)) +T714C 002:704.762 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:704.991 - 0.247ms returns 0x30500000 +T714C 002:705.011 JLINK_ClrBPEx(BPHandle = 0x0000009F) +T714C 002:705.028 - 0.017ms returns 0x00 +T714C 002:705.046 JLINK_ReadReg(R0) +T714C 002:705.062 - 0.016ms returns 0x00000000 +T714C 002:705.597 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:705.631 Data: EC 40 C2 F2 00 00 02 68 12 B1 68 46 21 46 90 47 ... +T714C 002:705.666 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:706.606 - 1.009ms returns 0x100 +T714C 002:706.629 JLINK_HasError() +T714C 002:706.646 JLINK_WriteReg(R0, 0x28012100) +T714C 002:706.664 - 0.018ms returns 0 +T714C 002:706.680 JLINK_WriteReg(R1, 0x00000100) +T714C 002:706.696 - 0.015ms returns 0 +T714C 002:706.713 JLINK_WriteReg(R2, 0x30500674) +T714C 002:706.728 - 0.015ms returns 0 +T714C 002:706.744 JLINK_WriteReg(R3, 0x00000000) +T714C 002:706.760 - 0.015ms returns 0 +T714C 002:706.776 JLINK_WriteReg(R4, 0x00000000) +T714C 002:706.793 - 0.016ms returns 0 +T714C 002:706.809 JLINK_WriteReg(R5, 0x00000000) +T714C 002:706.825 - 0.015ms returns 0 +T714C 002:706.841 JLINK_WriteReg(R6, 0x00000000) +T714C 002:706.857 - 0.016ms returns 0 +T714C 002:706.873 JLINK_WriteReg(R7, 0x00000000) +T714C 002:706.889 - 0.016ms returns 0 +T714C 002:706.906 JLINK_WriteReg(R8, 0x00000000) +T714C 002:706.921 - 0.015ms returns 0 +T714C 002:706.937 JLINK_WriteReg(R9, 0x30500458) +T714C 002:706.953 - 0.015ms returns 0 +T714C 002:706.969 JLINK_WriteReg(R10, 0x00000000) +T714C 002:706.985 - 0.016ms returns 0 +T714C 002:707.002 JLINK_WriteReg(R11, 0x00000000) +T714C 002:707.018 - 0.016ms returns 0 +T714C 002:707.034 JLINK_WriteReg(R12, 0x00000000) +T714C 002:707.050 - 0.015ms returns 0 +T714C 002:707.067 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:707.084 - 0.017ms returns 0 +T714C 002:707.100 JLINK_WriteReg(R14, 0x30500001) +T714C 002:707.116 - 0.016ms returns 0 +T714C 002:707.132 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:707.148 - 0.016ms returns 0 +T714C 002:707.164 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:707.181 - 0.016ms returns 0 +T714C 002:707.197 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:707.212 - 0.015ms returns 0 +T714C 002:707.228 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:707.244 - 0.015ms returns 0 +T714C 002:707.260 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:707.276 - 0.015ms returns 0 +T714C 002:707.292 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:707.309 - 0.016ms returns 0x000000A0 +T714C 002:707.325 JLINK_Go() +T714C 002:707.342 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:707.610 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:709.560 - 2.234ms +T714C 002:709.622 JLINK_IsHalted() +T714C 002:709.911 - 0.288ms returns FALSE +T714C 002:710.010 JLINK_HasError() +T714C 002:713.244 JLINK_IsHalted() +T714C 002:715.429 - 2.184ms returns TRUE +T714C 002:715.459 JLINK_ReadReg(R15 (PC)) +T714C 002:715.480 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:715.909 - 0.450ms returns 0x30500000 +T714C 002:715.938 JLINK_ClrBPEx(BPHandle = 0x000000A0) +T714C 002:715.956 - 0.017ms returns 0x00 +T714C 002:715.974 JLINK_ReadReg(R0) +T714C 002:715.991 - 0.017ms returns 0x00000000 +T714C 002:716.600 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:716.639 Data: 40 F2 C0 20 C2 F2 00 00 4F F0 FF 31 00 F0 B8 FA ... +T714C 002:716.682 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:717.700 - 1.095ms returns 0x100 +T714C 002:717.759 JLINK_HasError() +T714C 002:718.421 JLINK_WriteReg(R0, 0x28012200) +T714C 002:718.444 - 0.022ms returns 0 +T714C 002:718.461 JLINK_WriteReg(R1, 0x00000100) +T714C 002:718.477 - 0.016ms returns 0 +T714C 002:718.493 JLINK_WriteReg(R2, 0x30500674) +T714C 002:718.510 - 0.016ms returns 0 +T714C 002:718.526 JLINK_WriteReg(R3, 0x00000000) +T714C 002:718.542 - 0.015ms returns 0 +T714C 002:718.559 JLINK_WriteReg(R4, 0x00000000) +T714C 002:718.575 - 0.016ms returns 0 +T714C 002:718.591 JLINK_WriteReg(R5, 0x00000000) +T714C 002:718.607 - 0.015ms returns 0 +T714C 002:718.623 JLINK_WriteReg(R6, 0x00000000) +T714C 002:718.640 - 0.017ms returns 0 +T714C 002:718.657 JLINK_WriteReg(R7, 0x00000000) +T714C 002:718.673 - 0.016ms returns 0 +T714C 002:718.689 JLINK_WriteReg(R8, 0x00000000) +T714C 002:718.705 - 0.015ms returns 0 +T714C 002:718.721 JLINK_WriteReg(R9, 0x30500458) +T714C 002:718.738 - 0.016ms returns 0 +T714C 002:718.755 JLINK_WriteReg(R10, 0x00000000) +T714C 002:718.771 - 0.016ms returns 0 +T714C 002:718.787 JLINK_WriteReg(R11, 0x00000000) +T714C 002:718.804 - 0.016ms returns 0 +T714C 002:718.820 JLINK_WriteReg(R12, 0x00000000) +T714C 002:718.835 - 0.015ms returns 0 +T714C 002:718.852 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:718.869 - 0.017ms returns 0 +T714C 002:718.885 JLINK_WriteReg(R14, 0x30500001) +T714C 002:718.901 - 0.015ms returns 0 +T714C 002:718.917 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:718.932 - 0.015ms returns 0 +T714C 002:718.949 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:718.965 - 0.016ms returns 0 +T714C 002:718.981 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:718.997 - 0.015ms returns 0 +T714C 002:719.013 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:719.029 - 0.015ms returns 0 +T714C 002:719.045 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:719.061 - 0.016ms returns 0 +T714C 002:719.079 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:719.096 - 0.016ms returns 0x000000A1 +T714C 002:719.112 JLINK_Go() +T714C 002:719.129 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:719.440 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:721.404 - 2.291ms +T714C 002:721.426 JLINK_IsHalted() +T714C 002:721.655 - 0.229ms returns FALSE +T714C 002:721.676 JLINK_HasError() +T714C 002:723.245 JLINK_IsHalted() +T714C 002:725.803 - 2.559ms returns TRUE +T714C 002:725.854 JLINK_ReadReg(R15 (PC)) +T714C 002:725.874 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:726.087 - 0.233ms returns 0x30500000 +T714C 002:726.109 JLINK_ClrBPEx(BPHandle = 0x000000A1) +T714C 002:726.126 - 0.017ms returns 0x00 +T714C 002:726.143 JLINK_ReadReg(R0) +T714C 002:726.160 - 0.017ms returns 0x00000000 +T714C 002:726.672 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:726.704 Data: 04 2A 09 D3 A3 F1 04 0C 00 9B 04 3A 4C F8 04 3F ... +T714C 002:726.735 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:727.796 - 1.124ms returns 0x100 +T714C 002:727.820 JLINK_HasError() +T714C 002:727.838 JLINK_WriteReg(R0, 0x28012300) +T714C 002:727.855 - 0.017ms returns 0 +T714C 002:727.874 JLINK_WriteReg(R1, 0x00000100) +T714C 002:727.890 - 0.016ms returns 0 +T714C 002:727.937 JLINK_WriteReg(R2, 0x30500674) +T714C 002:727.952 - 0.015ms returns 0 +T714C 002:727.969 JLINK_WriteReg(R3, 0x00000000) +T714C 002:727.984 - 0.015ms returns 0 +T714C 002:728.001 JLINK_WriteReg(R4, 0x00000000) +T714C 002:728.017 - 0.016ms returns 0 +T714C 002:728.033 JLINK_WriteReg(R5, 0x00000000) +T714C 002:728.049 - 0.015ms returns 0 +T714C 002:728.065 JLINK_WriteReg(R6, 0x00000000) +T714C 002:728.081 - 0.016ms returns 0 +T714C 002:728.097 JLINK_WriteReg(R7, 0x00000000) +T714C 002:728.113 - 0.015ms returns 0 +T714C 002:728.130 JLINK_WriteReg(R8, 0x00000000) +T714C 002:728.146 - 0.015ms returns 0 +T714C 002:728.163 JLINK_WriteReg(R9, 0x30500458) +T714C 002:728.179 - 0.016ms returns 0 +T714C 002:728.195 JLINK_WriteReg(R10, 0x00000000) +T714C 002:728.211 - 0.016ms returns 0 +T714C 002:728.227 JLINK_WriteReg(R11, 0x00000000) +T714C 002:728.248 - 0.021ms returns 0 +T714C 002:728.266 JLINK_WriteReg(R12, 0x00000000) +T714C 002:728.283 - 0.016ms returns 0 +T714C 002:728.299 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:728.315 - 0.016ms returns 0 +T714C 002:728.331 JLINK_WriteReg(R14, 0x30500001) +T714C 002:728.347 - 0.015ms returns 0 +T714C 002:728.364 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:728.380 - 0.015ms returns 0 +T714C 002:728.396 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:728.412 - 0.016ms returns 0 +T714C 002:728.428 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:728.444 - 0.015ms returns 0 +T714C 002:728.460 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:728.477 - 0.016ms returns 0 +T714C 002:728.493 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:728.509 - 0.015ms returns 0 +T714C 002:728.526 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:728.542 - 0.016ms returns 0x000000A2 +T714C 002:728.559 JLINK_Go() +T714C 002:728.576 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:728.839 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:730.708 - 2.149ms +T714C 002:730.734 JLINK_IsHalted() +T714C 002:730.964 - 0.229ms returns FALSE +T714C 002:730.986 JLINK_HasError() +T714C 002:732.411 JLINK_IsHalted() +T714C 002:734.681 - 2.269ms returns TRUE +T714C 002:734.716 JLINK_ReadReg(R15 (PC)) +T714C 002:734.736 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:734.963 - 0.246ms returns 0x30500000 +T714C 002:734.985 JLINK_ClrBPEx(BPHandle = 0x000000A2) +T714C 002:735.002 - 0.016ms returns 0x00 +T714C 002:735.021 JLINK_ReadReg(R0) +T714C 002:735.038 - 0.016ms returns 0x00000000 +T714C 002:735.567 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:735.600 Data: 46 F2 E7 31 1F A0 C2 F6 01 01 4F F4 88 62 FE F7 ... +T714C 002:735.631 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:736.581 - 1.013ms returns 0x100 +T714C 002:736.604 JLINK_HasError() +T714C 002:736.621 JLINK_WriteReg(R0, 0x28012400) +T714C 002:736.639 - 0.018ms returns 0 +T714C 002:736.656 JLINK_WriteReg(R1, 0x00000100) +T714C 002:736.672 - 0.016ms returns 0 +T714C 002:736.688 JLINK_WriteReg(R2, 0x30500674) +T714C 002:736.704 - 0.016ms returns 0 +T714C 002:736.720 JLINK_WriteReg(R3, 0x00000000) +T714C 002:736.736 - 0.016ms returns 0 +T714C 002:736.753 JLINK_WriteReg(R4, 0x00000000) +T714C 002:736.768 - 0.015ms returns 0 +T714C 002:736.785 JLINK_WriteReg(R5, 0x00000000) +T714C 002:736.802 - 0.016ms returns 0 +T714C 002:736.818 JLINK_WriteReg(R6, 0x00000000) +T714C 002:736.834 - 0.016ms returns 0 +T714C 002:736.850 JLINK_WriteReg(R7, 0x00000000) +T714C 002:736.867 - 0.016ms returns 0 +T714C 002:736.883 JLINK_WriteReg(R8, 0x00000000) +T714C 002:736.899 - 0.015ms returns 0 +T714C 002:736.915 JLINK_WriteReg(R9, 0x30500458) +T714C 002:736.932 - 0.017ms returns 0 +T714C 002:736.948 JLINK_WriteReg(R10, 0x00000000) +T714C 002:736.964 - 0.015ms returns 0 +T714C 002:736.980 JLINK_WriteReg(R11, 0x00000000) +T714C 002:736.997 - 0.016ms returns 0 +T714C 002:737.013 JLINK_WriteReg(R12, 0x00000000) +T714C 002:737.029 - 0.015ms returns 0 +T714C 002:737.045 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:737.062 - 0.016ms returns 0 +T714C 002:737.078 JLINK_WriteReg(R14, 0x30500001) +T714C 002:737.094 - 0.015ms returns 0 +T714C 002:737.109 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:737.125 - 0.015ms returns 0 +T714C 002:737.142 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:737.158 - 0.015ms returns 0 +T714C 002:737.174 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:737.190 - 0.015ms returns 0 +T714C 002:737.205 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:737.221 - 0.015ms returns 0 +T714C 002:737.237 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:737.253 - 0.015ms returns 0 +T714C 002:737.270 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:737.287 - 0.016ms returns 0x000000A3 +T714C 002:737.303 JLINK_Go() +T714C 002:737.320 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:737.590 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:739.401 - 2.097ms +T714C 002:739.447 JLINK_IsHalted() +T714C 002:739.653 - 0.206ms returns FALSE +T714C 002:739.674 JLINK_HasError() +T714C 002:741.448 JLINK_IsHalted() +T714C 002:743.632 - 2.185ms returns TRUE +T714C 002:743.666 JLINK_ReadReg(R15 (PC)) +T714C 002:743.685 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:743.958 - 0.292ms returns 0x30500000 +T714C 002:743.985 JLINK_ClrBPEx(BPHandle = 0x000000A3) +T714C 002:744.003 - 0.017ms returns 0x00 +T714C 002:744.022 JLINK_ReadReg(R0) +T714C 002:744.040 - 0.017ms returns 0x00000000 +T714C 002:744.635 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:744.673 Data: 84 F8 22 00 C4 E9 09 01 01 20 60 73 04 F1 30 00 ... +T714C 002:744.704 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:745.694 - 1.058ms returns 0x100 +T714C 002:745.718 JLINK_HasError() +T714C 002:745.735 JLINK_WriteReg(R0, 0x28012500) +T714C 002:745.753 - 0.018ms returns 0 +T714C 002:745.769 JLINK_WriteReg(R1, 0x00000100) +T714C 002:745.785 - 0.016ms returns 0 +T714C 002:745.802 JLINK_WriteReg(R2, 0x30500674) +T714C 002:745.817 - 0.015ms returns 0 +T714C 002:745.834 JLINK_WriteReg(R3, 0x00000000) +T714C 002:745.849 - 0.015ms returns 0 +T714C 002:745.865 JLINK_WriteReg(R4, 0x00000000) +T714C 002:745.882 - 0.017ms returns 0 +T714C 002:745.899 JLINK_WriteReg(R5, 0x00000000) +T714C 002:745.914 - 0.015ms returns 0 +T714C 002:745.931 JLINK_WriteReg(R6, 0x00000000) +T714C 002:745.947 - 0.016ms returns 0 +T714C 002:745.963 JLINK_WriteReg(R7, 0x00000000) +T714C 002:745.980 - 0.016ms returns 0 +T714C 002:745.996 JLINK_WriteReg(R8, 0x00000000) +T714C 002:746.012 - 0.015ms returns 0 +T714C 002:746.028 JLINK_WriteReg(R9, 0x30500458) +T714C 002:746.043 - 0.015ms returns 0 +T714C 002:746.060 JLINK_WriteReg(R10, 0x00000000) +T714C 002:746.075 - 0.015ms returns 0 +T714C 002:746.092 JLINK_WriteReg(R11, 0x00000000) +T714C 002:746.108 - 0.016ms returns 0 +T714C 002:746.125 JLINK_WriteReg(R12, 0x00000000) +T714C 002:746.141 - 0.016ms returns 0 +T714C 002:746.158 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:746.174 - 0.016ms returns 0 +T714C 002:746.190 JLINK_WriteReg(R14, 0x30500001) +T714C 002:746.206 - 0.015ms returns 0 +T714C 002:746.222 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:746.238 - 0.015ms returns 0 +T714C 002:746.254 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:746.270 - 0.016ms returns 0 +T714C 002:746.286 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:746.302 - 0.015ms returns 0 +T714C 002:746.318 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:746.334 - 0.015ms returns 0 +T714C 002:746.350 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:746.366 - 0.015ms returns 0 +T714C 002:746.383 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:746.400 - 0.017ms returns 0x000000A4 +T714C 002:746.416 JLINK_Go() +T714C 002:746.433 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:746.717 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:748.483 - 2.067ms +T714C 002:748.510 JLINK_IsHalted() +T714C 002:748.745 - 0.235ms returns FALSE +T714C 002:748.768 JLINK_HasError() +T714C 002:750.484 JLINK_IsHalted() +T714C 002:752.682 - 2.197ms returns TRUE +T714C 002:752.706 JLINK_ReadReg(R15 (PC)) +T714C 002:752.724 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:752.965 - 0.259ms returns 0x30500000 +T714C 002:752.986 JLINK_ClrBPEx(BPHandle = 0x000000A4) +T714C 002:753.002 - 0.015ms returns 0x00 +T714C 002:753.018 JLINK_ReadReg(R0) +T714C 002:753.035 - 0.016ms returns 0x00000000 +T714C 002:753.988 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:754.047 Data: A1 E0 97 F8 22 00 01 38 01 06 87 F8 22 00 02 D0 ... +T714C 002:754.085 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:755.076 - 1.087ms returns 0x100 +T714C 002:755.120 JLINK_HasError() +T714C 002:755.140 JLINK_WriteReg(R0, 0x28012600) +T714C 002:755.160 - 0.020ms returns 0 +T714C 002:755.177 JLINK_WriteReg(R1, 0x00000100) +T714C 002:755.194 - 0.016ms returns 0 +T714C 002:755.210 JLINK_WriteReg(R2, 0x30500674) +T714C 002:755.227 - 0.016ms returns 0 +T714C 002:755.244 JLINK_WriteReg(R3, 0x00000000) +T714C 002:755.260 - 0.015ms returns 0 +T714C 002:755.276 JLINK_WriteReg(R4, 0x00000000) +T714C 002:755.293 - 0.016ms returns 0 +T714C 002:755.317 JLINK_WriteReg(R5, 0x00000000) +T714C 002:755.333 - 0.016ms returns 0 +T714C 002:755.357 JLINK_WriteReg(R6, 0x00000000) +T714C 002:755.375 - 0.017ms returns 0 +T714C 002:755.391 JLINK_WriteReg(R7, 0x00000000) +T714C 002:755.408 - 0.016ms returns 0 +T714C 002:755.425 JLINK_WriteReg(R8, 0x00000000) +T714C 002:755.441 - 0.016ms returns 0 +T714C 002:755.457 JLINK_WriteReg(R9, 0x30500458) +T714C 002:755.473 - 0.016ms returns 0 +T714C 002:755.490 JLINK_WriteReg(R10, 0x00000000) +T714C 002:755.506 - 0.015ms returns 0 +T714C 002:755.523 JLINK_WriteReg(R11, 0x00000000) +T714C 002:755.539 - 0.016ms returns 0 +T714C 002:755.555 JLINK_WriteReg(R12, 0x00000000) +T714C 002:755.571 - 0.016ms returns 0 +T714C 002:755.588 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:755.606 - 0.018ms returns 0 +T714C 002:755.623 JLINK_WriteReg(R14, 0x30500001) +T714C 002:755.639 - 0.016ms returns 0 +T714C 002:755.656 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:755.672 - 0.016ms returns 0 +T714C 002:755.688 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:755.704 - 0.016ms returns 0 +T714C 002:755.720 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:755.736 - 0.015ms returns 0 +T714C 002:755.753 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:755.769 - 0.015ms returns 0 +T714C 002:755.785 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:755.801 - 0.016ms returns 0 +T714C 002:755.818 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:755.835 - 0.017ms returns 0x000000A5 +T714C 002:755.851 JLINK_Go() +T714C 002:755.869 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:756.127 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:758.119 - 2.267ms +T714C 002:758.153 JLINK_IsHalted() +T714C 002:758.429 - 0.275ms returns FALSE +T714C 002:758.451 JLINK_HasError() +T714C 002:760.250 JLINK_IsHalted() +T714C 002:762.362 - 2.112ms returns TRUE +T714C 002:762.388 JLINK_ReadReg(R15 (PC)) +T714C 002:762.406 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:762.650 - 0.262ms returns 0x30500000 +T714C 002:762.673 JLINK_ClrBPEx(BPHandle = 0x000000A5) +T714C 002:762.691 - 0.017ms returns 0x00 +T714C 002:762.708 JLINK_ReadReg(R0) +T714C 002:762.726 - 0.017ms returns 0x00000000 +T714C 002:763.282 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:763.319 Data: C8 F8 00 B0 B8 69 00 21 A0 42 7E 62 87 F8 22 A0 ... +T714C 002:763.348 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:764.350 - 1.068ms returns 0x100 +T714C 002:764.376 JLINK_HasError() +T714C 002:764.394 JLINK_WriteReg(R0, 0x28012700) +T714C 002:764.412 - 0.018ms returns 0 +T714C 002:764.429 JLINK_WriteReg(R1, 0x00000100) +T714C 002:764.446 - 0.017ms returns 0 +T714C 002:764.464 JLINK_WriteReg(R2, 0x30500674) +T714C 002:764.479 - 0.015ms returns 0 +T714C 002:764.496 JLINK_WriteReg(R3, 0x00000000) +T714C 002:764.520 - 0.023ms returns 0 +T714C 002:764.567 JLINK_WriteReg(R4, 0x00000000) +T714C 002:764.584 - 0.017ms returns 0 +T714C 002:764.600 JLINK_WriteReg(R5, 0x00000000) +T714C 002:764.616 - 0.016ms returns 0 +T714C 002:764.633 JLINK_WriteReg(R6, 0x00000000) +T714C 002:764.649 - 0.016ms returns 0 +T714C 002:764.666 JLINK_WriteReg(R7, 0x00000000) +T714C 002:764.682 - 0.016ms returns 0 +T714C 002:764.699 JLINK_WriteReg(R8, 0x00000000) +T714C 002:764.715 - 0.016ms returns 0 +T714C 002:764.731 JLINK_WriteReg(R9, 0x30500458) +T714C 002:764.747 - 0.016ms returns 0 +T714C 002:764.764 JLINK_WriteReg(R10, 0x00000000) +T714C 002:764.781 - 0.016ms returns 0 +T714C 002:764.798 JLINK_WriteReg(R11, 0x00000000) +T714C 002:764.814 - 0.015ms returns 0 +T714C 002:764.830 JLINK_WriteReg(R12, 0x00000000) +T714C 002:764.846 - 0.015ms returns 0 +T714C 002:764.863 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:764.880 - 0.017ms returns 0 +T714C 002:764.897 JLINK_WriteReg(R14, 0x30500001) +T714C 002:764.913 - 0.015ms returns 0 +T714C 002:764.929 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:764.946 - 0.016ms returns 0 +T714C 002:764.962 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:764.978 - 0.016ms returns 0 +T714C 002:764.995 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:765.011 - 0.015ms returns 0 +T714C 002:765.027 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:765.086 - 0.058ms returns 0 +T714C 002:765.102 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:765.122 - 0.020ms returns 0 +T714C 002:765.141 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:765.158 - 0.017ms returns 0x000000A6 +T714C 002:765.174 JLINK_Go() +T714C 002:765.193 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:765.473 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:767.580 - 2.405ms +T714C 002:767.640 JLINK_IsHalted() +T714C 002:767.916 - 0.275ms returns FALSE +T714C 002:767.964 JLINK_HasError() +T714C 002:769.338 JLINK_IsHalted() +T714C 002:771.819 - 2.480ms returns TRUE +T714C 002:772.559 JLINK_ReadReg(R15 (PC)) +T714C 002:772.612 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:772.840 - 0.281ms returns 0x30500000 +T714C 002:772.882 JLINK_ClrBPEx(BPHandle = 0x000000A6) +T714C 002:772.900 - 0.018ms returns 0x00 +T714C 002:772.918 JLINK_ReadReg(R0) +T714C 002:772.935 - 0.017ms returns 0x00000000 +T714C 002:773.641 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:773.679 Data: 25 FC 00 28 4F F0 00 04 04 BF 00 20 BD E8 F0 81 ... +T714C 002:773.711 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:774.772 - 1.131ms returns 0x100 +T714C 002:774.804 JLINK_HasError() +T714C 002:774.823 JLINK_WriteReg(R0, 0x28012800) +T714C 002:774.842 - 0.019ms returns 0 +T714C 002:774.858 JLINK_WriteReg(R1, 0x00000100) +T714C 002:774.874 - 0.016ms returns 0 +T714C 002:774.891 JLINK_WriteReg(R2, 0x30500674) +T714C 002:774.907 - 0.016ms returns 0 +T714C 002:774.956 JLINK_WriteReg(R3, 0x00000000) +T714C 002:774.972 - 0.016ms returns 0 +T714C 002:774.989 JLINK_WriteReg(R4, 0x00000000) +T714C 002:775.005 - 0.016ms returns 0 +T714C 002:775.022 JLINK_WriteReg(R5, 0x00000000) +T714C 002:775.038 - 0.016ms returns 0 +T714C 002:775.054 JLINK_WriteReg(R6, 0x00000000) +T714C 002:775.071 - 0.016ms returns 0 +T714C 002:775.087 JLINK_WriteReg(R7, 0x00000000) +T714C 002:775.103 - 0.015ms returns 0 +T714C 002:775.120 JLINK_WriteReg(R8, 0x00000000) +T714C 002:775.136 - 0.015ms returns 0 +T714C 002:775.154 JLINK_WriteReg(R9, 0x30500458) +T714C 002:775.170 - 0.016ms returns 0 +T714C 002:775.186 JLINK_WriteReg(R10, 0x00000000) +T714C 002:775.202 - 0.016ms returns 0 +T714C 002:775.220 JLINK_WriteReg(R11, 0x00000000) +T714C 002:775.236 - 0.015ms returns 0 +T714C 002:775.252 JLINK_WriteReg(R12, 0x00000000) +T714C 002:775.268 - 0.015ms returns 0 +T714C 002:775.284 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:775.301 - 0.017ms returns 0 +T714C 002:775.317 JLINK_WriteReg(R14, 0x30500001) +T714C 002:775.333 - 0.015ms returns 0 +T714C 002:775.349 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:775.365 - 0.016ms returns 0 +T714C 002:775.382 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:775.398 - 0.016ms returns 0 +T714C 002:775.414 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:775.430 - 0.016ms returns 0 +T714C 002:775.446 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:775.462 - 0.015ms returns 0 +T714C 002:775.478 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:775.494 - 0.016ms returns 0 +T714C 002:775.512 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:775.528 - 0.016ms returns 0x000000A7 +T714C 002:775.545 JLINK_Go() +T714C 002:775.563 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:775.832 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:777.749 - 2.203ms +T714C 002:777.780 JLINK_IsHalted() +T714C 002:778.151 - 0.371ms returns FALSE +T714C 002:778.174 JLINK_HasError() +T714C 002:779.379 JLINK_IsHalted() +T714C 002:781.574 - 2.193ms returns TRUE +T714C 002:781.605 JLINK_ReadReg(R15 (PC)) +T714C 002:781.622 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:781.917 - 0.311ms returns 0x30500000 +T714C 002:782.009 JLINK_ClrBPEx(BPHandle = 0x000000A7) +T714C 002:782.050 - 0.041ms returns 0x00 +T714C 002:782.086 JLINK_ReadReg(R0) +T714C 002:782.122 - 0.035ms returns 0x00000000 +T714C 002:782.996 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:783.041 Data: 00 00 01 68 00 29 1C BF 20 46 88 47 20 7B 40 F2 ... +T714C 002:783.075 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:784.101 - 1.104ms returns 0x100 +T714C 002:784.160 JLINK_HasError() +T714C 002:784.179 JLINK_WriteReg(R0, 0x28012900) +T714C 002:784.208 - 0.028ms returns 0 +T714C 002:784.227 JLINK_WriteReg(R1, 0x00000100) +T714C 002:784.244 - 0.017ms returns 0 +T714C 002:784.260 JLINK_WriteReg(R2, 0x30500674) +T714C 002:784.288 - 0.027ms returns 0 +T714C 002:784.304 JLINK_WriteReg(R3, 0x00000000) +T714C 002:784.321 - 0.016ms returns 0 +T714C 002:784.337 JLINK_WriteReg(R4, 0x00000000) +T714C 002:784.353 - 0.015ms returns 0 +T714C 002:784.369 JLINK_WriteReg(R5, 0x00000000) +T714C 002:784.385 - 0.015ms returns 0 +T714C 002:784.401 JLINK_WriteReg(R6, 0x00000000) +T714C 002:784.417 - 0.015ms returns 0 +T714C 002:784.434 JLINK_WriteReg(R7, 0x00000000) +T714C 002:784.450 - 0.016ms returns 0 +T714C 002:784.466 JLINK_WriteReg(R8, 0x00000000) +T714C 002:784.483 - 0.016ms returns 0 +T714C 002:784.499 JLINK_WriteReg(R9, 0x30500458) +T714C 002:784.515 - 0.016ms returns 0 +T714C 002:784.532 JLINK_WriteReg(R10, 0x00000000) +T714C 002:784.548 - 0.015ms returns 0 +T714C 002:784.564 JLINK_WriteReg(R11, 0x00000000) +T714C 002:784.580 - 0.016ms returns 0 +T714C 002:784.596 JLINK_WriteReg(R12, 0x00000000) +T714C 002:784.612 - 0.015ms returns 0 +T714C 002:784.629 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:784.646 - 0.017ms returns 0 +T714C 002:784.662 JLINK_WriteReg(R14, 0x30500001) +T714C 002:784.678 - 0.016ms returns 0 +T714C 002:784.694 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:784.710 - 0.016ms returns 0 +T714C 002:784.727 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:784.743 - 0.016ms returns 0 +T714C 002:784.760 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:784.775 - 0.015ms returns 0 +T714C 002:784.792 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:784.808 - 0.016ms returns 0 +T714C 002:784.825 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:784.840 - 0.015ms returns 0 +T714C 002:784.857 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:784.874 - 0.017ms returns 0x000000A8 +T714C 002:784.891 JLINK_Go() +T714C 002:784.910 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:785.201 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:787.218 - 2.327ms +T714C 002:787.243 JLINK_IsHalted() +T714C 002:787.475 - 0.232ms returns FALSE +T714C 002:787.496 JLINK_HasError() +T714C 002:788.873 JLINK_IsHalted() +T714C 002:791.009 - 2.136ms returns TRUE +T714C 002:791.041 JLINK_ReadReg(R15 (PC)) +T714C 002:791.060 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:791.316 - 0.274ms returns 0x30500000 +T714C 002:791.340 JLINK_ClrBPEx(BPHandle = 0x000000A8) +T714C 002:791.357 - 0.017ms returns 0x00 +T714C 002:791.374 JLINK_ReadReg(R0) +T714C 002:791.392 - 0.017ms returns 0x00000000 +T714C 002:792.029 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:792.070 Data: 15 18 5D B9 46 F6 E4 50 46 F6 53 61 C2 F6 01 00 ... +T714C 002:792.104 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:793.188 - 1.158ms returns 0x100 +T714C 002:793.213 JLINK_HasError() +T714C 002:793.231 JLINK_WriteReg(R0, 0x28012A00) +T714C 002:793.250 - 0.019ms returns 0 +T714C 002:793.267 JLINK_WriteReg(R1, 0x00000100) +T714C 002:793.283 - 0.015ms returns 0 +T714C 002:793.300 JLINK_WriteReg(R2, 0x30500674) +T714C 002:793.316 - 0.015ms returns 0 +T714C 002:793.332 JLINK_WriteReg(R3, 0x00000000) +T714C 002:793.348 - 0.016ms returns 0 +T714C 002:793.364 JLINK_WriteReg(R4, 0x00000000) +T714C 002:793.380 - 0.016ms returns 0 +T714C 002:793.397 JLINK_WriteReg(R5, 0x00000000) +T714C 002:793.413 - 0.015ms returns 0 +T714C 002:793.429 JLINK_WriteReg(R6, 0x00000000) +T714C 002:793.445 - 0.016ms returns 0 +T714C 002:793.462 JLINK_WriteReg(R7, 0x00000000) +T714C 002:793.478 - 0.016ms returns 0 +T714C 002:793.494 JLINK_WriteReg(R8, 0x00000000) +T714C 002:793.510 - 0.016ms returns 0 +T714C 002:793.526 JLINK_WriteReg(R9, 0x30500458) +T714C 002:793.542 - 0.015ms returns 0 +T714C 002:793.558 JLINK_WriteReg(R10, 0x00000000) +T714C 002:793.574 - 0.015ms returns 0 +T714C 002:793.591 JLINK_WriteReg(R11, 0x00000000) +T714C 002:793.607 - 0.016ms returns 0 +T714C 002:793.623 JLINK_WriteReg(R12, 0x00000000) +T714C 002:793.639 - 0.016ms returns 0 +T714C 002:793.656 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:793.673 - 0.017ms returns 0 +T714C 002:793.696 JLINK_WriteReg(R14, 0x30500001) +T714C 002:793.715 - 0.018ms returns 0 +T714C 002:793.731 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:793.747 - 0.016ms returns 0 +T714C 002:793.764 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:793.780 - 0.015ms returns 0 +T714C 002:793.796 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:793.812 - 0.016ms returns 0 +T714C 002:793.829 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:793.844 - 0.015ms returns 0 +T714C 002:793.861 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:793.876 - 0.015ms returns 0 +T714C 002:793.893 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:793.910 - 0.016ms returns 0x000000A9 +T714C 002:793.927 JLINK_Go() +T714C 002:793.945 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:794.215 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:796.138 - 2.211ms +T714C 002:796.163 JLINK_IsHalted() +T714C 002:796.414 - 0.250ms returns FALSE +T714C 002:796.435 JLINK_HasError() +T714C 002:797.875 JLINK_IsHalted() +T714C 002:799.941 - 2.066ms returns TRUE +T714C 002:800.656 JLINK_ReadReg(R15 (PC)) +T714C 002:800.686 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:800.955 - 0.298ms returns 0x30500000 +T714C 002:800.976 JLINK_ClrBPEx(BPHandle = 0x000000A9) +T714C 002:800.993 - 0.017ms returns 0x00 +T714C 002:801.010 JLINK_ReadReg(R0) +T714C 002:801.027 - 0.016ms returns 0x00000000 +T714C 002:801.644 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:801.684 Data: 53 FA 98 B1 46 F6 40 66 45 F6 0F 30 C2 F6 01 06 ... +T714C 002:801.716 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:802.712 - 1.067ms returns 0x100 +T714C 002:802.737 JLINK_HasError() +T714C 002:802.755 JLINK_WriteReg(R0, 0x28012B00) +T714C 002:802.774 - 0.019ms returns 0 +T714C 002:802.791 JLINK_WriteReg(R1, 0x00000100) +T714C 002:802.807 - 0.016ms returns 0 +T714C 002:802.824 JLINK_WriteReg(R2, 0x30500674) +T714C 002:802.839 - 0.015ms returns 0 +T714C 002:802.856 JLINK_WriteReg(R3, 0x00000000) +T714C 002:802.872 - 0.015ms returns 0 +T714C 002:802.888 JLINK_WriteReg(R4, 0x00000000) +T714C 002:802.904 - 0.016ms returns 0 +T714C 002:802.921 JLINK_WriteReg(R5, 0x00000000) +T714C 002:802.938 - 0.017ms returns 0 +T714C 002:802.955 JLINK_WriteReg(R6, 0x00000000) +T714C 002:802.971 - 0.015ms returns 0 +T714C 002:802.987 JLINK_WriteReg(R7, 0x00000000) +T714C 002:803.005 - 0.017ms returns 0 +T714C 002:803.021 JLINK_WriteReg(R8, 0x00000000) +T714C 002:803.039 - 0.017ms returns 0 +T714C 002:803.055 JLINK_WriteReg(R9, 0x30500458) +T714C 002:803.070 - 0.015ms returns 0 +T714C 002:803.087 JLINK_WriteReg(R10, 0x00000000) +T714C 002:803.103 - 0.016ms returns 0 +T714C 002:803.118 JLINK_WriteReg(R11, 0x00000000) +T714C 002:803.134 - 0.015ms returns 0 +T714C 002:803.150 JLINK_WriteReg(R12, 0x00000000) +T714C 002:803.166 - 0.015ms returns 0 +T714C 002:803.183 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:803.200 - 0.017ms returns 0 +T714C 002:803.216 JLINK_WriteReg(R14, 0x30500001) +T714C 002:803.232 - 0.016ms returns 0 +T714C 002:803.248 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:803.264 - 0.015ms returns 0 +T714C 002:803.280 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:803.296 - 0.016ms returns 0 +T714C 002:803.312 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:803.328 - 0.016ms returns 0 +T714C 002:803.344 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:803.360 - 0.015ms returns 0 +T714C 002:803.376 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:803.392 - 0.015ms returns 0 +T714C 002:803.409 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:803.426 - 0.017ms returns 0x000000AA +T714C 002:803.442 JLINK_Go() +T714C 002:803.460 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:803.740 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:805.725 - 2.281ms +T714C 002:805.753 JLINK_IsHalted() +T714C 002:805.990 - 0.237ms returns FALSE +T714C 002:806.012 JLINK_HasError() +T714C 002:807.340 JLINK_IsHalted() +T714C 002:809.499 - 2.158ms returns TRUE +T714C 002:809.526 JLINK_ReadReg(R15 (PC)) +T714C 002:809.542 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:809.778 - 0.253ms returns 0x30500000 +T714C 002:809.801 JLINK_ClrBPEx(BPHandle = 0x000000AA) +T714C 002:809.871 - 0.069ms returns 0x00 +T714C 002:809.887 JLINK_ReadReg(R0) +T714C 002:809.904 - 0.016ms returns 0x00000000 +T714C 002:810.406 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:810.438 Data: 00 92 5D B9 46 F6 E4 50 46 F6 64 61 C2 F6 01 00 ... +T714C 002:810.467 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:811.531 - 1.125ms returns 0x100 +T714C 002:811.556 JLINK_HasError() +T714C 002:811.574 JLINK_WriteReg(R0, 0x28012C00) +T714C 002:811.591 - 0.017ms returns 0 +T714C 002:811.608 JLINK_WriteReg(R1, 0x00000100) +T714C 002:811.636 - 0.028ms returns 0 +T714C 002:811.654 JLINK_WriteReg(R2, 0x30500674) +T714C 002:811.671 - 0.016ms returns 0 +T714C 002:811.689 JLINK_WriteReg(R3, 0x00000000) +T714C 002:811.706 - 0.017ms returns 0 +T714C 002:811.723 JLINK_WriteReg(R4, 0x00000000) +T714C 002:811.740 - 0.017ms returns 0 +T714C 002:811.758 JLINK_WriteReg(R5, 0x00000000) +T714C 002:811.774 - 0.016ms returns 0 +T714C 002:811.792 JLINK_WriteReg(R6, 0x00000000) +T714C 002:811.808 - 0.015ms returns 0 +T714C 002:811.824 JLINK_WriteReg(R7, 0x00000000) +T714C 002:811.839 - 0.015ms returns 0 +T714C 002:811.856 JLINK_WriteReg(R8, 0x00000000) +T714C 002:811.871 - 0.016ms returns 0 +T714C 002:811.888 JLINK_WriteReg(R9, 0x30500458) +T714C 002:811.904 - 0.016ms returns 0 +T714C 002:811.920 JLINK_WriteReg(R10, 0x00000000) +T714C 002:811.937 - 0.017ms returns 0 +T714C 002:811.953 JLINK_WriteReg(R11, 0x00000000) +T714C 002:811.969 - 0.016ms returns 0 +T714C 002:811.985 JLINK_WriteReg(R12, 0x00000000) +T714C 002:812.001 - 0.015ms returns 0 +T714C 002:812.017 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:812.033 - 0.016ms returns 0 +T714C 002:812.049 JLINK_WriteReg(R14, 0x30500001) +T714C 002:812.065 - 0.016ms returns 0 +T714C 002:812.081 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:812.097 - 0.015ms returns 0 +T714C 002:812.114 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:812.130 - 0.015ms returns 0 +T714C 002:812.146 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:812.162 - 0.015ms returns 0 +T714C 002:812.178 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:812.194 - 0.015ms returns 0 +T714C 002:812.210 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:812.225 - 0.015ms returns 0 +T714C 002:812.242 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:812.258 - 0.016ms returns 0x000000AB +T714C 002:812.274 JLINK_Go() +T714C 002:812.291 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:812.546 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:814.477 - 2.202ms +T714C 002:814.593 JLINK_IsHalted() +T714C 002:814.869 - 0.275ms returns FALSE +T714C 002:814.900 JLINK_HasError() +T714C 002:819.011 JLINK_IsHalted() +T714C 002:821.489 - 2.477ms returns TRUE +T714C 002:821.545 JLINK_ReadReg(R15 (PC)) +T714C 002:821.567 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:821.877 - 0.331ms returns 0x30500000 +T714C 002:821.925 JLINK_ClrBPEx(BPHandle = 0x000000AB) +T714C 002:821.943 - 0.018ms returns 0x00 +T714C 002:821.961 JLINK_ReadReg(R0) +T714C 002:821.978 - 0.017ms returns 0x00000000 +T714C 002:822.583 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:822.614 Data: 6F 62 6A 20 21 3D 20 6F 62 6A 65 63 74 00 00 00 ... +T714C 002:822.649 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:823.718 - 1.134ms returns 0x100 +T714C 002:823.766 JLINK_HasError() +T714C 002:823.784 JLINK_WriteReg(R0, 0x28012D00) +T714C 002:823.803 - 0.018ms returns 0 +T714C 002:823.819 JLINK_WriteReg(R1, 0x00000100) +T714C 002:823.836 - 0.016ms returns 0 +T714C 002:823.852 JLINK_WriteReg(R2, 0x30500674) +T714C 002:823.868 - 0.015ms returns 0 +T714C 002:823.884 JLINK_WriteReg(R3, 0x00000000) +T714C 002:823.899 - 0.015ms returns 0 +T714C 002:823.915 JLINK_WriteReg(R4, 0x00000000) +T714C 002:823.931 - 0.016ms returns 0 +T714C 002:823.947 JLINK_WriteReg(R5, 0x00000000) +T714C 002:823.963 - 0.016ms returns 0 +T714C 002:823.980 JLINK_WriteReg(R6, 0x00000000) +T714C 002:823.997 - 0.016ms returns 0 +T714C 002:824.013 JLINK_WriteReg(R7, 0x00000000) +T714C 002:824.029 - 0.015ms returns 0 +T714C 002:824.045 JLINK_WriteReg(R8, 0x00000000) +T714C 002:824.065 - 0.020ms returns 0 +T714C 002:824.081 JLINK_WriteReg(R9, 0x30500458) +T714C 002:824.096 - 0.015ms returns 0 +T714C 002:824.112 JLINK_WriteReg(R10, 0x00000000) +T714C 002:824.128 - 0.015ms returns 0 +T714C 002:824.144 JLINK_WriteReg(R11, 0x00000000) +T714C 002:824.160 - 0.016ms returns 0 +T714C 002:824.176 JLINK_WriteReg(R12, 0x00000000) +T714C 002:824.191 - 0.015ms returns 0 +T714C 002:824.207 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:824.224 - 0.017ms returns 0 +T714C 002:824.240 JLINK_WriteReg(R14, 0x30500001) +T714C 002:824.255 - 0.015ms returns 0 +T714C 002:824.271 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:824.286 - 0.015ms returns 0 +T714C 002:824.302 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:824.318 - 0.015ms returns 0 +T714C 002:824.334 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:824.349 - 0.015ms returns 0 +T714C 002:824.365 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:824.381 - 0.016ms returns 0 +T714C 002:824.396 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:824.412 - 0.015ms returns 0 +T714C 002:824.428 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:824.444 - 0.016ms returns 0x000000AC +T714C 002:824.460 JLINK_Go() +T714C 002:824.477 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:824.788 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:827.020 - 2.559ms +T714C 002:827.709 JLINK_IsHalted() +T714C 002:829.891 - 2.181ms returns TRUE +T714C 002:829.939 JLINK_ReadReg(R15 (PC)) +T714C 002:829.960 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:830.264 - 0.323ms returns 0x30500000 +T714C 002:830.313 JLINK_ClrBPEx(BPHandle = 0x000000AC) +T714C 002:830.332 - 0.018ms returns 0x00 +T714C 002:830.351 JLINK_ReadReg(R0) +T714C 002:830.369 - 0.017ms returns 0x00000000 +T714C 002:830.948 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:830.981 Data: 04 46 F8 F7 07 FB 20 60 00 20 10 BD B0 B5 05 46 ... +T714C 002:831.012 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:832.201 - 1.253ms returns 0x100 +T714C 002:832.260 JLINK_HasError() +T714C 002:832.279 JLINK_WriteReg(R0, 0x28012E00) +T714C 002:832.300 - 0.020ms returns 0 +T714C 002:832.317 JLINK_WriteReg(R1, 0x00000100) +T714C 002:832.333 - 0.016ms returns 0 +T714C 002:832.349 JLINK_WriteReg(R2, 0x30500674) +T714C 002:832.365 - 0.016ms returns 0 +T714C 002:832.381 JLINK_WriteReg(R3, 0x00000000) +T714C 002:832.397 - 0.016ms returns 0 +T714C 002:832.413 JLINK_WriteReg(R4, 0x00000000) +T714C 002:832.429 - 0.016ms returns 0 +T714C 002:832.444 JLINK_WriteReg(R5, 0x00000000) +T714C 002:832.460 - 0.015ms returns 0 +T714C 002:832.476 JLINK_WriteReg(R6, 0x00000000) +T714C 002:832.492 - 0.015ms returns 0 +T714C 002:832.508 JLINK_WriteReg(R7, 0x00000000) +T714C 002:832.524 - 0.015ms returns 0 +T714C 002:832.541 JLINK_WriteReg(R8, 0x00000000) +T714C 002:832.556 - 0.015ms returns 0 +T714C 002:832.572 JLINK_WriteReg(R9, 0x30500458) +T714C 002:832.589 - 0.017ms returns 0 +T714C 002:832.606 JLINK_WriteReg(R10, 0x00000000) +T714C 002:832.621 - 0.015ms returns 0 +T714C 002:832.637 JLINK_WriteReg(R11, 0x00000000) +T714C 002:832.652 - 0.015ms returns 0 +T714C 002:832.668 JLINK_WriteReg(R12, 0x00000000) +T714C 002:832.684 - 0.015ms returns 0 +T714C 002:832.701 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:832.718 - 0.016ms returns 0 +T714C 002:832.734 JLINK_WriteReg(R14, 0x30500001) +T714C 002:832.750 - 0.015ms returns 0 +T714C 002:832.766 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:832.782 - 0.016ms returns 0 +T714C 002:832.798 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:832.814 - 0.015ms returns 0 +T714C 002:832.830 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:832.845 - 0.015ms returns 0 +T714C 002:832.861 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:832.877 - 0.015ms returns 0 +T714C 002:832.893 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:832.908 - 0.015ms returns 0 +T714C 002:832.925 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:832.941 - 0.016ms returns 0x000000AD +T714C 002:832.957 JLINK_Go() +T714C 002:832.976 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:833.292 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:835.624 - 2.666ms +T714C 002:835.680 JLINK_IsHalted() +T714C 002:835.950 - 0.269ms returns FALSE +T714C 002:835.997 JLINK_HasError() +T714C 002:837.705 JLINK_IsHalted() +T714C 002:840.074 - 2.368ms returns TRUE +T714C 002:840.120 JLINK_ReadReg(R15 (PC)) +T714C 002:840.142 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:840.464 - 0.343ms returns 0x30500000 +T714C 002:840.511 JLINK_ClrBPEx(BPHandle = 0x000000AD) +T714C 002:840.529 - 0.017ms returns 0x00 +T714C 002:840.546 JLINK_ReadReg(R0) +T714C 002:840.563 - 0.016ms returns 0x00000000 +T714C 002:841.188 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:841.220 Data: 38 30 00 F0 01 B8 00 00 70 B5 16 46 0C 46 05 46 ... +T714C 002:841.252 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:842.434 - 1.245ms returns 0x100 +T714C 002:842.482 JLINK_HasError() +T714C 002:842.500 JLINK_WriteReg(R0, 0x28012F00) +T714C 002:842.518 - 0.018ms returns 0 +T714C 002:842.535 JLINK_WriteReg(R1, 0x00000100) +T714C 002:842.551 - 0.016ms returns 0 +T714C 002:842.567 JLINK_WriteReg(R2, 0x30500674) +T714C 002:842.583 - 0.015ms returns 0 +T714C 002:842.599 JLINK_WriteReg(R3, 0x00000000) +T714C 002:842.614 - 0.015ms returns 0 +T714C 002:842.659 JLINK_WriteReg(R4, 0x00000000) +T714C 002:842.675 - 0.016ms returns 0 +T714C 002:842.691 JLINK_WriteReg(R5, 0x00000000) +T714C 002:842.706 - 0.015ms returns 0 +T714C 002:842.722 JLINK_WriteReg(R6, 0x00000000) +T714C 002:842.737 - 0.015ms returns 0 +T714C 002:842.753 JLINK_WriteReg(R7, 0x00000000) +T714C 002:842.768 - 0.015ms returns 0 +T714C 002:842.784 JLINK_WriteReg(R8, 0x00000000) +T714C 002:842.799 - 0.015ms returns 0 +T714C 002:842.814 JLINK_WriteReg(R9, 0x30500458) +T714C 002:842.830 - 0.015ms returns 0 +T714C 002:842.846 JLINK_WriteReg(R10, 0x00000000) +T714C 002:842.861 - 0.015ms returns 0 +T714C 002:842.877 JLINK_WriteReg(R11, 0x00000000) +T714C 002:842.892 - 0.015ms returns 0 +T714C 002:842.908 JLINK_WriteReg(R12, 0x00000000) +T714C 002:842.924 - 0.015ms returns 0 +T714C 002:842.940 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:842.956 - 0.016ms returns 0 +T714C 002:842.972 JLINK_WriteReg(R14, 0x30500001) +T714C 002:842.987 - 0.015ms returns 0 +T714C 002:843.004 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:843.019 - 0.015ms returns 0 +T714C 002:843.035 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:843.050 - 0.015ms returns 0 +T714C 002:843.066 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:843.081 - 0.015ms returns 0 +T714C 002:843.098 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:843.113 - 0.015ms returns 0 +T714C 002:843.129 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:843.144 - 0.015ms returns 0 +T714C 002:843.161 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:843.177 - 0.016ms returns 0x000000AE +T714C 002:843.193 JLINK_Go() +T714C 002:843.210 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:843.530 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:845.527 - 2.333ms +T714C 002:845.598 JLINK_IsHalted() +T714C 002:845.903 - 0.305ms returns FALSE +T714C 002:845.937 JLINK_HasError() +T714C 002:847.606 JLINK_IsHalted() +T714C 002:849.968 - 2.361ms returns TRUE +T714C 002:850.030 JLINK_ReadReg(R15 (PC)) +T714C 002:850.054 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:850.317 - 0.285ms returns 0x30500000 +T714C 002:850.341 JLINK_ClrBPEx(BPHandle = 0x000000AE) +T714C 002:850.358 - 0.017ms returns 0x00 +T714C 002:850.375 JLINK_ReadReg(R0) +T714C 002:850.393 - 0.017ms returns 0x00000000 +T714C 002:851.049 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:851.087 Data: 81 F8 39 20 70 47 00 00 90 F8 39 10 89 07 5C BF ... +T714C 002:851.118 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:852.151 - 1.101ms returns 0x100 +T714C 002:852.176 JLINK_HasError() +T714C 002:852.194 JLINK_WriteReg(R0, 0x28013000) +T714C 002:852.212 - 0.018ms returns 0 +T714C 002:852.230 JLINK_WriteReg(R1, 0x00000100) +T714C 002:852.249 - 0.019ms returns 0 +T714C 002:852.266 JLINK_WriteReg(R2, 0x30500674) +T714C 002:852.281 - 0.015ms returns 0 +T714C 002:852.298 JLINK_WriteReg(R3, 0x00000000) +T714C 002:852.313 - 0.015ms returns 0 +T714C 002:852.329 JLINK_WriteReg(R4, 0x00000000) +T714C 002:852.350 - 0.021ms returns 0 +T714C 002:852.366 JLINK_WriteReg(R5, 0x00000000) +T714C 002:852.382 - 0.015ms returns 0 +T714C 002:852.398 JLINK_WriteReg(R6, 0x00000000) +T714C 002:852.415 - 0.016ms returns 0 +T714C 002:852.431 JLINK_WriteReg(R7, 0x00000000) +T714C 002:852.446 - 0.015ms returns 0 +T714C 002:852.463 JLINK_WriteReg(R8, 0x00000000) +T714C 002:852.479 - 0.015ms returns 0 +T714C 002:852.495 JLINK_WriteReg(R9, 0x30500458) +T714C 002:852.511 - 0.016ms returns 0 +T714C 002:852.527 JLINK_WriteReg(R10, 0x00000000) +T714C 002:852.543 - 0.015ms returns 0 +T714C 002:852.559 JLINK_WriteReg(R11, 0x00000000) +T714C 002:852.575 - 0.015ms returns 0 +T714C 002:852.591 JLINK_WriteReg(R12, 0x00000000) +T714C 002:852.607 - 0.015ms returns 0 +T714C 002:852.628 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:852.647 - 0.018ms returns 0 +T714C 002:852.666 JLINK_WriteReg(R14, 0x30500001) +T714C 002:852.682 - 0.016ms returns 0 +T714C 002:852.701 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:852.719 - 0.018ms returns 0 +T714C 002:852.737 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:852.754 - 0.016ms returns 0 +T714C 002:852.772 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:852.790 - 0.017ms returns 0 +T714C 002:852.808 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:852.825 - 0.017ms returns 0 +T714C 002:852.843 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:852.860 - 0.017ms returns 0 +T714C 002:852.880 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:852.898 - 0.018ms returns 0x000000AF +T714C 002:852.916 JLINK_Go() +T714C 002:852.935 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:853.195 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:855.094 - 2.178ms +T714C 002:855.121 JLINK_IsHalted() +T714C 002:855.377 - 0.255ms returns FALSE +T714C 002:855.399 JLINK_HasError() +T714C 002:856.626 JLINK_IsHalted() +T714C 002:858.832 - 2.206ms returns TRUE +T714C 002:858.854 JLINK_ReadReg(R15 (PC)) +T714C 002:858.871 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:859.172 - 0.317ms returns 0x30500000 +T714C 002:859.226 JLINK_ClrBPEx(BPHandle = 0x000000AF) +T714C 002:859.244 - 0.017ms returns 0x00 +T714C 002:859.262 JLINK_ReadReg(R0) +T714C 002:859.281 - 0.019ms returns 0x00000000 +T714C 002:860.244 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:860.329 Data: 0A D1 95 F8 44 20 90 42 69 D9 01 27 2E 46 AE 42 ... +T714C 002:860.365 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:861.344 - 1.099ms returns 0x100 +T714C 002:861.393 JLINK_HasError() +T714C 002:861.412 JLINK_WriteReg(R0, 0x28013100) +T714C 002:861.431 - 0.019ms returns 0 +T714C 002:861.448 JLINK_WriteReg(R1, 0x00000100) +T714C 002:861.465 - 0.016ms returns 0 +T714C 002:861.482 JLINK_WriteReg(R2, 0x30500674) +T714C 002:861.498 - 0.016ms returns 0 +T714C 002:861.514 JLINK_WriteReg(R3, 0x00000000) +T714C 002:861.530 - 0.015ms returns 0 +T714C 002:861.546 JLINK_WriteReg(R4, 0x00000000) +T714C 002:861.562 - 0.015ms returns 0 +T714C 002:861.578 JLINK_WriteReg(R5, 0x00000000) +T714C 002:861.594 - 0.016ms returns 0 +T714C 002:861.610 JLINK_WriteReg(R6, 0x00000000) +T714C 002:861.626 - 0.015ms returns 0 +T714C 002:861.642 JLINK_WriteReg(R7, 0x00000000) +T714C 002:861.658 - 0.016ms returns 0 +T714C 002:861.674 JLINK_WriteReg(R8, 0x00000000) +T714C 002:861.690 - 0.016ms returns 0 +T714C 002:861.706 JLINK_WriteReg(R9, 0x30500458) +T714C 002:861.723 - 0.016ms returns 0 +T714C 002:861.739 JLINK_WriteReg(R10, 0x00000000) +T714C 002:861.755 - 0.015ms returns 0 +T714C 002:861.771 JLINK_WriteReg(R11, 0x00000000) +T714C 002:861.787 - 0.016ms returns 0 +T714C 002:861.804 JLINK_WriteReg(R12, 0x00000000) +T714C 002:861.820 - 0.015ms returns 0 +T714C 002:861.836 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:861.852 - 0.016ms returns 0 +T714C 002:861.869 JLINK_WriteReg(R14, 0x30500001) +T714C 002:861.885 - 0.016ms returns 0 +T714C 002:861.901 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:861.917 - 0.015ms returns 0 +T714C 002:861.933 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:861.948 - 0.015ms returns 0 +T714C 002:861.965 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:861.980 - 0.015ms returns 0 +T714C 002:862.001 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:862.017 - 0.015ms returns 0 +T714C 002:862.033 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:862.049 - 0.015ms returns 0 +T714C 002:862.066 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:862.082 - 0.016ms returns 0x000000B0 +T714C 002:862.100 JLINK_Go() +T714C 002:862.119 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:862.340 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:864.186 - 2.085ms +T714C 002:864.214 JLINK_IsHalted() +T714C 002:864.433 - 0.218ms returns FALSE +T714C 002:864.454 JLINK_HasError() +T714C 002:866.294 JLINK_IsHalted() +T714C 002:868.471 - 2.177ms returns TRUE +T714C 002:868.506 JLINK_ReadReg(R15 (PC)) +T714C 002:868.526 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:868.787 - 0.281ms returns 0x30500000 +T714C 002:868.808 JLINK_ClrBPEx(BPHandle = 0x000000B0) +T714C 002:868.824 - 0.016ms returns 0x00 +T714C 002:868.841 JLINK_ReadReg(R0) +T714C 002:868.858 - 0.017ms returns 0x00000000 +T714C 002:869.426 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:869.462 Data: 01 00 C2 F6 01 01 40 F2 22 22 FD F7 23 FE F8 F7 ... +T714C 002:869.492 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:870.491 - 1.064ms returns 0x100 +T714C 002:870.515 JLINK_HasError() +T714C 002:870.532 JLINK_WriteReg(R0, 0x28013200) +T714C 002:870.551 - 0.018ms returns 0 +T714C 002:870.568 JLINK_WriteReg(R1, 0x00000100) +T714C 002:870.584 - 0.016ms returns 0 +T714C 002:870.601 JLINK_WriteReg(R2, 0x30500674) +T714C 002:870.617 - 0.016ms returns 0 +T714C 002:870.634 JLINK_WriteReg(R3, 0x00000000) +T714C 002:870.650 - 0.016ms returns 0 +T714C 002:870.666 JLINK_WriteReg(R4, 0x00000000) +T714C 002:870.682 - 0.016ms returns 0 +T714C 002:870.698 JLINK_WriteReg(R5, 0x00000000) +T714C 002:870.713 - 0.015ms returns 0 +T714C 002:870.730 JLINK_WriteReg(R6, 0x00000000) +T714C 002:870.746 - 0.015ms returns 0 +T714C 002:870.763 JLINK_WriteReg(R7, 0x00000000) +T714C 002:870.778 - 0.015ms returns 0 +T714C 002:870.794 JLINK_WriteReg(R8, 0x00000000) +T714C 002:870.810 - 0.016ms returns 0 +T714C 002:870.826 JLINK_WriteReg(R9, 0x30500458) +T714C 002:870.842 - 0.015ms returns 0 +T714C 002:870.858 JLINK_WriteReg(R10, 0x00000000) +T714C 002:870.874 - 0.015ms returns 0 +T714C 002:870.890 JLINK_WriteReg(R11, 0x00000000) +T714C 002:870.934 - 0.043ms returns 0 +T714C 002:870.950 JLINK_WriteReg(R12, 0x00000000) +T714C 002:870.965 - 0.015ms returns 0 +T714C 002:870.981 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:870.997 - 0.016ms returns 0 +T714C 002:871.014 JLINK_WriteReg(R14, 0x30500001) +T714C 002:871.029 - 0.015ms returns 0 +T714C 002:871.045 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:871.062 - 0.016ms returns 0 +T714C 002:871.078 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:871.093 - 0.015ms returns 0 +T714C 002:871.109 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:871.125 - 0.015ms returns 0 +T714C 002:871.141 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:871.156 - 0.015ms returns 0 +T714C 002:871.173 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:871.188 - 0.015ms returns 0 +T714C 002:871.205 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:871.222 - 0.017ms returns 0x000000B1 +T714C 002:871.238 JLINK_Go() +T714C 002:871.256 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:871.573 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:873.451 - 2.212ms +T714C 002:873.475 JLINK_IsHalted() +T714C 002:873.803 - 0.328ms returns FALSE +T714C 002:873.824 JLINK_HasError() +T714C 002:875.804 JLINK_IsHalted() +T714C 002:877.957 - 2.153ms returns TRUE +T714C 002:877.998 JLINK_ReadReg(R15 (PC)) +T714C 002:878.077 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:878.359 - 0.361ms returns 0x30500000 +T714C 002:878.397 JLINK_ClrBPEx(BPHandle = 0x000000B1) +T714C 002:878.416 - 0.018ms returns 0x00 +T714C 002:878.434 JLINK_ReadReg(R0) +T714C 002:878.450 - 0.016ms returns 0x00000000 +T714C 002:879.017 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:879.050 Data: 10 BD 13 A0 FE F7 72 FE 17 A0 21 46 FE F7 6E FE ... +T714C 002:879.081 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:880.082 - 1.064ms returns 0x100 +T714C 002:880.106 JLINK_HasError() +T714C 002:880.124 JLINK_WriteReg(R0, 0x28013300) +T714C 002:880.142 - 0.017ms returns 0 +T714C 002:880.158 JLINK_WriteReg(R1, 0x00000100) +T714C 002:880.174 - 0.016ms returns 0 +T714C 002:880.191 JLINK_WriteReg(R2, 0x30500674) +T714C 002:880.207 - 0.015ms returns 0 +T714C 002:880.223 JLINK_WriteReg(R3, 0x00000000) +T714C 002:880.239 - 0.016ms returns 0 +T714C 002:880.257 JLINK_WriteReg(R4, 0x00000000) +T714C 002:880.273 - 0.015ms returns 0 +T714C 002:880.290 JLINK_WriteReg(R5, 0x00000000) +T714C 002:880.306 - 0.015ms returns 0 +T714C 002:880.322 JLINK_WriteReg(R6, 0x00000000) +T714C 002:880.337 - 0.015ms returns 0 +T714C 002:880.354 JLINK_WriteReg(R7, 0x00000000) +T714C 002:880.370 - 0.016ms returns 0 +T714C 002:880.386 JLINK_WriteReg(R8, 0x00000000) +T714C 002:880.402 - 0.015ms returns 0 +T714C 002:880.418 JLINK_WriteReg(R9, 0x30500458) +T714C 002:880.434 - 0.015ms returns 0 +T714C 002:880.450 JLINK_WriteReg(R10, 0x00000000) +T714C 002:880.466 - 0.015ms returns 0 +T714C 002:880.482 JLINK_WriteReg(R11, 0x00000000) +T714C 002:880.498 - 0.015ms returns 0 +T714C 002:880.514 JLINK_WriteReg(R12, 0x00000000) +T714C 002:880.530 - 0.016ms returns 0 +T714C 002:880.547 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:880.564 - 0.017ms returns 0 +T714C 002:880.580 JLINK_WriteReg(R14, 0x30500001) +T714C 002:880.596 - 0.016ms returns 0 +T714C 002:880.613 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:880.629 - 0.016ms returns 0 +T714C 002:880.645 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:880.661 - 0.016ms returns 0 +T714C 002:880.678 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:880.694 - 0.016ms returns 0 +T714C 002:880.710 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:880.726 - 0.015ms returns 0 +T714C 002:880.742 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:880.758 - 0.015ms returns 0 +T714C 002:880.775 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:880.791 - 0.017ms returns 0x000000B2 +T714C 002:881.467 JLINK_Go() +T714C 002:881.494 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:881.753 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:883.688 - 2.220ms +T714C 002:883.736 JLINK_IsHalted() +T714C 002:883.960 - 0.222ms returns FALSE +T714C 002:884.033 JLINK_HasError() +T714C 002:885.818 JLINK_IsHalted() +T714C 002:887.943 - 2.125ms returns TRUE +T714C 002:887.966 JLINK_ReadReg(R15 (PC)) +T714C 002:887.985 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:888.295 - 0.329ms returns 0x30500000 +T714C 002:888.316 JLINK_ClrBPEx(BPHandle = 0x000000B2) +T714C 002:888.333 - 0.017ms returns 0x00 +T714C 002:888.350 JLINK_ReadReg(R0) +T714C 002:888.366 - 0.016ms returns 0x00000000 +T714C 002:888.920 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:888.953 Data: 46 F2 1F 30 46 F2 6D 61 C2 F6 01 00 C2 F6 01 01 ... +T714C 002:888.983 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:889.936 - 1.015ms returns 0x100 +T714C 002:890.002 JLINK_HasError() +T714C 002:890.028 JLINK_WriteReg(R0, 0x28013400) +T714C 002:890.050 - 0.021ms returns 0 +T714C 002:890.067 JLINK_WriteReg(R1, 0x00000100) +T714C 002:890.084 - 0.016ms returns 0 +T714C 002:890.101 JLINK_WriteReg(R2, 0x30500674) +T714C 002:890.117 - 0.016ms returns 0 +T714C 002:890.139 JLINK_WriteReg(R3, 0x00000000) +T714C 002:890.156 - 0.017ms returns 0 +T714C 002:890.173 JLINK_WriteReg(R4, 0x00000000) +T714C 002:890.190 - 0.016ms returns 0 +T714C 002:890.207 JLINK_WriteReg(R5, 0x00000000) +T714C 002:890.223 - 0.016ms returns 0 +T714C 002:890.240 JLINK_WriteReg(R6, 0x00000000) +T714C 002:890.257 - 0.016ms returns 0 +T714C 002:890.274 JLINK_WriteReg(R7, 0x00000000) +T714C 002:890.292 - 0.017ms returns 0 +T714C 002:890.309 JLINK_WriteReg(R8, 0x00000000) +T714C 002:890.338 - 0.026ms returns 0 +T714C 002:890.434 JLINK_WriteReg(R9, 0x30500458) +T714C 002:890.462 - 0.027ms returns 0 +T714C 002:890.479 JLINK_WriteReg(R10, 0x00000000) +T714C 002:890.496 - 0.016ms returns 0 +T714C 002:890.513 JLINK_WriteReg(R11, 0x00000000) +T714C 002:890.562 - 0.048ms returns 0 +T714C 002:890.579 JLINK_WriteReg(R12, 0x00000000) +T714C 002:890.602 - 0.023ms returns 0 +T714C 002:890.620 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:890.639 - 0.019ms returns 0 +T714C 002:890.656 JLINK_WriteReg(R14, 0x30500001) +T714C 002:890.673 - 0.016ms returns 0 +T714C 002:890.690 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:890.707 - 0.016ms returns 0 +T714C 002:890.728 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:890.744 - 0.016ms returns 0 +T714C 002:890.774 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:890.793 - 0.019ms returns 0 +T714C 002:890.815 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:890.831 - 0.016ms returns 0 +T714C 002:890.849 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:890.873 - 0.024ms returns 0 +T714C 002:890.893 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:890.913 - 0.020ms returns 0x000000B3 +T714C 002:890.930 JLINK_Go() +T714C 002:890.950 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:891.224 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:893.238 - 2.307ms +T714C 002:893.307 JLINK_IsHalted() +T714C 002:893.632 - 0.323ms returns FALSE +T714C 002:893.721 JLINK_HasError() +T714C 002:895.786 JLINK_IsHalted() +T714C 002:897.991 - 2.204ms returns TRUE +T714C 002:898.064 JLINK_ReadReg(R15 (PC)) +T714C 002:898.088 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:898.414 - 0.349ms returns 0x30500000 +T714C 002:898.492 JLINK_ClrBPEx(BPHandle = 0x000000B3) +T714C 002:898.531 - 0.038ms returns 0x00 +T714C 002:898.568 JLINK_ReadReg(R0) +T714C 002:898.607 - 0.038ms returns 0x00000000 +T714C 002:899.452 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:899.504 Data: 00 28 04 BF 00 20 44 F8 04 0C 01 98 FF F7 B2 FD ... +T714C 002:899.539 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:900.552 - 1.099ms returns 0x100 +T714C 002:900.592 JLINK_HasError() +T714C 002:900.611 JLINK_WriteReg(R0, 0x28013500) +T714C 002:900.630 - 0.019ms returns 0 +T714C 002:900.646 JLINK_WriteReg(R1, 0x00000100) +T714C 002:900.663 - 0.016ms returns 0 +T714C 002:900.683 JLINK_WriteReg(R2, 0x30500674) +T714C 002:900.699 - 0.016ms returns 0 +T714C 002:900.715 JLINK_WriteReg(R3, 0x00000000) +T714C 002:900.731 - 0.015ms returns 0 +T714C 002:900.748 JLINK_WriteReg(R4, 0x00000000) +T714C 002:900.763 - 0.015ms returns 0 +T714C 002:900.781 JLINK_WriteReg(R5, 0x00000000) +T714C 002:900.796 - 0.015ms returns 0 +T714C 002:900.812 JLINK_WriteReg(R6, 0x00000000) +T714C 002:900.828 - 0.015ms returns 0 +T714C 002:900.844 JLINK_WriteReg(R7, 0x00000000) +T714C 002:900.860 - 0.015ms returns 0 +T714C 002:900.876 JLINK_WriteReg(R8, 0x00000000) +T714C 002:900.892 - 0.015ms returns 0 +T714C 002:900.908 JLINK_WriteReg(R9, 0x30500458) +T714C 002:900.925 - 0.016ms returns 0 +T714C 002:900.942 JLINK_WriteReg(R10, 0x00000000) +T714C 002:900.958 - 0.016ms returns 0 +T714C 002:900.974 JLINK_WriteReg(R11, 0x00000000) +T714C 002:900.990 - 0.015ms returns 0 +T714C 002:901.008 JLINK_WriteReg(R12, 0x00000000) +T714C 002:901.024 - 0.016ms returns 0 +T714C 002:901.040 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:901.057 - 0.017ms returns 0 +T714C 002:901.073 JLINK_WriteReg(R14, 0x30500001) +T714C 002:901.089 - 0.016ms returns 0 +T714C 002:901.106 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:901.122 - 0.016ms returns 0 +T714C 002:901.138 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:901.154 - 0.016ms returns 0 +T714C 002:901.170 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:901.186 - 0.015ms returns 0 +T714C 002:901.202 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:901.218 - 0.015ms returns 0 +T714C 002:901.234 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:901.250 - 0.016ms returns 0 +T714C 002:901.266 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:901.284 - 0.017ms returns 0x000000B4 +T714C 002:901.300 JLINK_Go() +T714C 002:901.317 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:901.598 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:903.481 - 2.181ms +T714C 002:903.504 JLINK_IsHalted() +T714C 002:903.882 - 0.378ms returns FALSE +T714C 002:903.903 JLINK_HasError() +T714C 002:905.064 JLINK_IsHalted() +T714C 002:907.200 - 2.135ms returns TRUE +T714C 002:907.924 JLINK_ReadReg(R15 (PC)) +T714C 002:907.964 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:908.235 - 0.311ms returns 0x30500000 +T714C 002:908.262 JLINK_ClrBPEx(BPHandle = 0x000000B4) +T714C 002:908.279 - 0.017ms returns 0x00 +T714C 002:908.296 JLINK_ReadReg(R0) +T714C 002:908.317 - 0.020ms returns 0x00000000 +T714C 002:908.880 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:908.913 Data: 00 22 98 47 60 8B 20 F0 10 00 60 83 00 20 B0 BD ... +T714C 002:908.944 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:909.876 - 0.996ms returns 0x100 +T714C 002:909.899 JLINK_HasError() +T714C 002:909.916 JLINK_WriteReg(R0, 0x28013600) +T714C 002:909.934 - 0.018ms returns 0 +T714C 002:909.951 JLINK_WriteReg(R1, 0x00000100) +T714C 002:909.968 - 0.016ms returns 0 +T714C 002:909.984 JLINK_WriteReg(R2, 0x30500674) +T714C 002:910.000 - 0.016ms returns 0 +T714C 002:910.017 JLINK_WriteReg(R3, 0x00000000) +T714C 002:910.033 - 0.016ms returns 0 +T714C 002:910.080 JLINK_WriteReg(R4, 0x00000000) +T714C 002:910.096 - 0.016ms returns 0 +T714C 002:910.112 JLINK_WriteReg(R5, 0x00000000) +T714C 002:910.128 - 0.015ms returns 0 +T714C 002:910.144 JLINK_WriteReg(R6, 0x00000000) +T714C 002:910.160 - 0.016ms returns 0 +T714C 002:910.176 JLINK_WriteReg(R7, 0x00000000) +T714C 002:910.192 - 0.015ms returns 0 +T714C 002:910.208 JLINK_WriteReg(R8, 0x00000000) +T714C 002:910.224 - 0.016ms returns 0 +T714C 002:910.240 JLINK_WriteReg(R9, 0x30500458) +T714C 002:910.256 - 0.016ms returns 0 +T714C 002:910.272 JLINK_WriteReg(R10, 0x00000000) +T714C 002:910.289 - 0.016ms returns 0 +T714C 002:910.305 JLINK_WriteReg(R11, 0x00000000) +T714C 002:910.321 - 0.015ms returns 0 +T714C 002:910.337 JLINK_WriteReg(R12, 0x00000000) +T714C 002:910.353 - 0.015ms returns 0 +T714C 002:910.369 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:910.386 - 0.017ms returns 0 +T714C 002:910.402 JLINK_WriteReg(R14, 0x30500001) +T714C 002:910.418 - 0.015ms returns 0 +T714C 002:910.434 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:910.451 - 0.016ms returns 0 +T714C 002:910.468 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:910.484 - 0.015ms returns 0 +T714C 002:910.500 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:910.516 - 0.016ms returns 0 +T714C 002:910.532 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:910.548 - 0.015ms returns 0 +T714C 002:910.564 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:910.580 - 0.015ms returns 0 +T714C 002:910.597 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:910.613 - 0.017ms returns 0x000000B5 +T714C 002:910.629 JLINK_Go() +T714C 002:910.647 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:910.933 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:912.817 - 2.188ms +T714C 002:912.839 JLINK_IsHalted() +T714C 002:913.072 - 0.232ms returns FALSE +T714C 002:913.124 JLINK_HasError() +T714C 002:915.133 JLINK_IsHalted() +T714C 002:917.369 - 2.235ms returns TRUE +T714C 002:917.408 JLINK_ReadReg(R15 (PC)) +T714C 002:917.428 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:917.654 - 0.245ms returns 0x30500000 +T714C 002:917.676 JLINK_ClrBPEx(BPHandle = 0x000000B5) +T714C 002:917.692 - 0.016ms returns 0x00 +T714C 002:917.709 JLINK_ReadReg(R0) +T714C 002:917.727 - 0.017ms returns 0x00000000 +T714C 002:918.434 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:918.478 Data: 00 20 C4 E9 15 00 04 F1 64 00 00 21 08 22 FE F7 ... +T714C 002:918.510 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:919.488 - 1.054ms returns 0x100 +T714C 002:919.527 JLINK_HasError() +T714C 002:919.546 JLINK_WriteReg(R0, 0x28013700) +T714C 002:919.566 - 0.019ms returns 0 +T714C 002:919.583 JLINK_WriteReg(R1, 0x00000100) +T714C 002:919.599 - 0.016ms returns 0 +T714C 002:919.616 JLINK_WriteReg(R2, 0x30500674) +T714C 002:919.632 - 0.016ms returns 0 +T714C 002:919.649 JLINK_WriteReg(R3, 0x00000000) +T714C 002:919.665 - 0.015ms returns 0 +T714C 002:919.681 JLINK_WriteReg(R4, 0x00000000) +T714C 002:919.697 - 0.015ms returns 0 +T714C 002:919.714 JLINK_WriteReg(R5, 0x00000000) +T714C 002:919.729 - 0.016ms returns 0 +T714C 002:919.745 JLINK_WriteReg(R6, 0x00000000) +T714C 002:919.762 - 0.016ms returns 0 +T714C 002:919.783 JLINK_WriteReg(R7, 0x00000000) +T714C 002:919.799 - 0.015ms returns 0 +T714C 002:919.817 JLINK_WriteReg(R8, 0x00000000) +T714C 002:919.833 - 0.016ms returns 0 +T714C 002:919.850 JLINK_WriteReg(R9, 0x30500458) +T714C 002:919.865 - 0.015ms returns 0 +T714C 002:919.882 JLINK_WriteReg(R10, 0x00000000) +T714C 002:919.898 - 0.016ms returns 0 +T714C 002:919.914 JLINK_WriteReg(R11, 0x00000000) +T714C 002:919.930 - 0.016ms returns 0 +T714C 002:919.946 JLINK_WriteReg(R12, 0x00000000) +T714C 002:919.962 - 0.015ms returns 0 +T714C 002:919.978 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:919.995 - 0.017ms returns 0 +T714C 002:920.025 JLINK_WriteReg(R14, 0x30500001) +T714C 002:920.041 - 0.016ms returns 0 +T714C 002:920.059 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:920.076 - 0.017ms returns 0 +T714C 002:920.092 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:920.108 - 0.015ms returns 0 +T714C 002:920.125 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:920.142 - 0.016ms returns 0 +T714C 002:920.159 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:920.344 - 0.184ms returns 0 +T714C 002:920.372 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:920.395 - 0.024ms returns 0 +T714C 002:920.419 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:920.453 - 0.034ms returns 0x000000B6 +T714C 002:920.474 JLINK_Go() +T714C 002:920.502 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:920.838 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:922.724 - 2.248ms +T714C 002:922.791 JLINK_IsHalted() +T714C 002:923.082 - 0.291ms returns FALSE +T714C 002:923.112 JLINK_HasError() +T714C 002:925.574 JLINK_IsHalted() +T714C 002:927.720 - 2.145ms returns TRUE +T714C 002:927.754 JLINK_ReadReg(R15 (PC)) +T714C 002:927.775 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:928.003 - 0.248ms returns 0x30500000 +T714C 002:928.024 JLINK_ClrBPEx(BPHandle = 0x000000B6) +T714C 002:928.044 - 0.020ms returns 0x00 +T714C 002:928.061 JLINK_ReadReg(R0) +T714C 002:928.077 - 0.016ms returns 0x00000000 +T714C 002:928.608 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:928.642 Data: 28 60 B1 78 32 88 00 26 42 EA 01 41 C1 F3 8F 02 ... +T714C 002:928.674 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:929.630 - 1.021ms returns 0x100 +T714C 002:929.654 JLINK_HasError() +T714C 002:929.672 JLINK_WriteReg(R0, 0x28013800) +T714C 002:929.691 - 0.019ms returns 0 +T714C 002:929.708 JLINK_WriteReg(R1, 0x00000100) +T714C 002:929.724 - 0.016ms returns 0 +T714C 002:929.741 JLINK_WriteReg(R2, 0x30500674) +T714C 002:929.757 - 0.016ms returns 0 +T714C 002:929.773 JLINK_WriteReg(R3, 0x00000000) +T714C 002:929.789 - 0.015ms returns 0 +T714C 002:929.805 JLINK_WriteReg(R4, 0x00000000) +T714C 002:929.821 - 0.016ms returns 0 +T714C 002:929.839 JLINK_WriteReg(R5, 0x00000000) +T714C 002:929.854 - 0.015ms returns 0 +T714C 002:929.871 JLINK_WriteReg(R6, 0x00000000) +T714C 002:929.887 - 0.015ms returns 0 +T714C 002:929.903 JLINK_WriteReg(R7, 0x00000000) +T714C 002:929.918 - 0.015ms returns 0 +T714C 002:929.935 JLINK_WriteReg(R8, 0x00000000) +T714C 002:929.951 - 0.016ms returns 0 +T714C 002:929.968 JLINK_WriteReg(R9, 0x30500458) +T714C 002:929.985 - 0.016ms returns 0 +T714C 002:930.001 JLINK_WriteReg(R10, 0x00000000) +T714C 002:930.017 - 0.016ms returns 0 +T714C 002:930.033 JLINK_WriteReg(R11, 0x00000000) +T714C 002:930.049 - 0.015ms returns 0 +T714C 002:930.065 JLINK_WriteReg(R12, 0x00000000) +T714C 002:930.081 - 0.016ms returns 0 +T714C 002:930.098 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:930.115 - 0.016ms returns 0 +T714C 002:930.131 JLINK_WriteReg(R14, 0x30500001) +T714C 002:930.147 - 0.015ms returns 0 +T714C 002:930.163 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:930.179 - 0.015ms returns 0 +T714C 002:930.196 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:930.211 - 0.015ms returns 0 +T714C 002:930.227 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:930.243 - 0.015ms returns 0 +T714C 002:930.259 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:930.275 - 0.015ms returns 0 +T714C 002:930.291 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:930.307 - 0.015ms returns 0 +T714C 002:930.324 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:930.345 - 0.022ms returns 0x000000B7 +T714C 002:930.363 JLINK_Go() +T714C 002:930.380 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:930.658 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:932.556 - 2.193ms +T714C 002:932.618 JLINK_IsHalted() +T714C 002:932.856 - 0.237ms returns FALSE +T714C 002:932.890 JLINK_HasError() +T714C 002:934.236 JLINK_IsHalted() +T714C 002:936.424 - 2.188ms returns TRUE +T714C 002:936.462 JLINK_ReadReg(R15 (PC)) +T714C 002:936.482 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:936.720 - 0.258ms returns 0x30500000 +T714C 002:936.742 JLINK_ClrBPEx(BPHandle = 0x000000B7) +T714C 002:936.758 - 0.016ms returns 0x00 +T714C 002:936.776 JLINK_ReadReg(R0) +T714C 002:936.793 - 0.016ms returns 0x00000000 +T714C 002:937.410 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:937.443 Data: C2 F6 01 00 38 A1 40 F2 7E 32 FD F7 A3 FA B8 F1 ... +T714C 002:937.474 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:938.438 - 1.027ms returns 0x100 +T714C 002:938.461 JLINK_HasError() +T714C 002:938.480 JLINK_WriteReg(R0, 0x28013900) +T714C 002:938.498 - 0.018ms returns 0 +T714C 002:938.515 JLINK_WriteReg(R1, 0x00000100) +T714C 002:938.531 - 0.016ms returns 0 +T714C 002:938.548 JLINK_WriteReg(R2, 0x30500674) +T714C 002:938.564 - 0.016ms returns 0 +T714C 002:938.581 JLINK_WriteReg(R3, 0x00000000) +T714C 002:938.597 - 0.016ms returns 0 +T714C 002:938.613 JLINK_WriteReg(R4, 0x00000000) +T714C 002:938.632 - 0.019ms returns 0 +T714C 002:938.648 JLINK_WriteReg(R5, 0x00000000) +T714C 002:938.664 - 0.016ms returns 0 +T714C 002:938.680 JLINK_WriteReg(R6, 0x00000000) +T714C 002:938.696 - 0.015ms returns 0 +T714C 002:938.712 JLINK_WriteReg(R7, 0x00000000) +T714C 002:938.727 - 0.015ms returns 0 +T714C 002:938.744 JLINK_WriteReg(R8, 0x00000000) +T714C 002:938.760 - 0.015ms returns 0 +T714C 002:938.776 JLINK_WriteReg(R9, 0x30500458) +T714C 002:938.792 - 0.015ms returns 0 +T714C 002:938.808 JLINK_WriteReg(R10, 0x00000000) +T714C 002:938.824 - 0.016ms returns 0 +T714C 002:938.841 JLINK_WriteReg(R11, 0x00000000) +T714C 002:938.857 - 0.016ms returns 0 +T714C 002:938.874 JLINK_WriteReg(R12, 0x00000000) +T714C 002:938.890 - 0.016ms returns 0 +T714C 002:938.907 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:938.924 - 0.016ms returns 0 +T714C 002:938.940 JLINK_WriteReg(R14, 0x30500001) +T714C 002:938.955 - 0.015ms returns 0 +T714C 002:938.972 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:938.988 - 0.015ms returns 0 +T714C 002:939.004 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:939.050 - 0.046ms returns 0 +T714C 002:939.068 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:939.084 - 0.016ms returns 0 +T714C 002:939.101 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:939.117 - 0.015ms returns 0 +T714C 002:939.133 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:939.149 - 0.015ms returns 0 +T714C 002:939.166 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:939.182 - 0.017ms returns 0x000000B8 +T714C 002:939.198 JLINK_Go() +T714C 002:939.216 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:939.462 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:941.294 - 2.095ms +T714C 002:941.323 JLINK_IsHalted() +T714C 002:941.574 - 0.250ms returns FALSE +T714C 002:941.595 JLINK_HasError() +T714C 002:943.646 JLINK_IsHalted() +T714C 002:945.731 - 2.085ms returns TRUE +T714C 002:945.760 JLINK_ReadReg(R15 (PC)) +T714C 002:945.777 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:946.003 - 0.243ms returns 0x30500000 +T714C 002:946.024 JLINK_ClrBPEx(BPHandle = 0x000000B8) +T714C 002:946.041 - 0.016ms returns 0x00 +T714C 002:946.057 JLINK_ReadReg(R0) +T714C 002:946.074 - 0.016ms returns 0x00000000 +T714C 002:946.549 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:946.579 Data: 70 6F 6C 6C 5F 72 78 00 2D E9 F0 43 81 B0 98 46 ... +T714C 002:946.608 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:947.575 - 1.026ms returns 0x100 +T714C 002:947.598 JLINK_HasError() +T714C 002:947.615 JLINK_WriteReg(R0, 0x28013A00) +T714C 002:947.632 - 0.017ms returns 0 +T714C 002:947.649 JLINK_WriteReg(R1, 0x00000100) +T714C 002:947.670 - 0.021ms returns 0 +T714C 002:947.687 JLINK_WriteReg(R2, 0x30500674) +T714C 002:947.703 - 0.016ms returns 0 +T714C 002:947.719 JLINK_WriteReg(R3, 0x00000000) +T714C 002:947.735 - 0.016ms returns 0 +T714C 002:947.751 JLINK_WriteReg(R4, 0x00000000) +T714C 002:947.767 - 0.016ms returns 0 +T714C 002:947.783 JLINK_WriteReg(R5, 0x00000000) +T714C 002:947.799 - 0.016ms returns 0 +T714C 002:947.816 JLINK_WriteReg(R6, 0x00000000) +T714C 002:947.832 - 0.015ms returns 0 +T714C 002:947.848 JLINK_WriteReg(R7, 0x00000000) +T714C 002:947.864 - 0.015ms returns 0 +T714C 002:947.880 JLINK_WriteReg(R8, 0x00000000) +T714C 002:947.897 - 0.016ms returns 0 +T714C 002:947.914 JLINK_WriteReg(R9, 0x30500458) +T714C 002:947.931 - 0.017ms returns 0 +T714C 002:947.950 JLINK_WriteReg(R10, 0x00000000) +T714C 002:947.967 - 0.017ms returns 0 +T714C 002:947.984 JLINK_WriteReg(R11, 0x00000000) +T714C 002:948.000 - 0.016ms returns 0 +T714C 002:948.016 JLINK_WriteReg(R12, 0x00000000) +T714C 002:948.032 - 0.015ms returns 0 +T714C 002:948.050 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:948.066 - 0.016ms returns 0 +T714C 002:948.083 JLINK_WriteReg(R14, 0x30500001) +T714C 002:948.098 - 0.015ms returns 0 +T714C 002:948.115 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:948.130 - 0.015ms returns 0 +T714C 002:948.147 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:948.163 - 0.016ms returns 0 +T714C 002:948.179 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:948.195 - 0.015ms returns 0 +T714C 002:948.211 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:948.227 - 0.016ms returns 0 +T714C 002:948.243 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:948.259 - 0.016ms returns 0 +T714C 002:948.276 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:948.292 - 0.017ms returns 0x000000B9 +T714C 002:948.309 JLINK_Go() +T714C 002:948.327 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:948.653 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:950.575 - 2.266ms +T714C 002:950.625 JLINK_IsHalted() +T714C 002:950.882 - 0.256ms returns FALSE +T714C 002:950.946 JLINK_HasError() +T714C 002:953.083 JLINK_IsHalted() +T714C 002:955.308 - 2.225ms returns TRUE +T714C 002:955.346 JLINK_ReadReg(R15 (PC)) +T714C 002:955.367 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:955.598 - 0.251ms returns 0x30500000 +T714C 002:955.620 JLINK_ClrBPEx(BPHandle = 0x000000B9) +T714C 002:955.637 - 0.017ms returns 0x00 +T714C 002:955.658 JLINK_ReadReg(R0) +T714C 002:955.675 - 0.017ms returns 0x00000000 +T714C 002:956.369 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:956.407 Data: 31 78 82 68 28 46 90 47 01 30 F3 D0 B9 F1 01 09 ... +T714C 002:956.439 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:957.424 - 1.055ms returns 0x100 +T714C 002:957.448 JLINK_HasError() +T714C 002:957.465 JLINK_WriteReg(R0, 0x28013B00) +T714C 002:957.483 - 0.017ms returns 0 +T714C 002:957.500 JLINK_WriteReg(R1, 0x00000100) +T714C 002:957.516 - 0.016ms returns 0 +T714C 002:957.532 JLINK_WriteReg(R2, 0x30500674) +T714C 002:957.549 - 0.016ms returns 0 +T714C 002:957.566 JLINK_WriteReg(R3, 0x00000000) +T714C 002:957.582 - 0.015ms returns 0 +T714C 002:957.598 JLINK_WriteReg(R4, 0x00000000) +T714C 002:957.614 - 0.015ms returns 0 +T714C 002:957.630 JLINK_WriteReg(R5, 0x00000000) +T714C 002:957.646 - 0.016ms returns 0 +T714C 002:957.663 JLINK_WriteReg(R6, 0x00000000) +T714C 002:957.679 - 0.016ms returns 0 +T714C 002:957.696 JLINK_WriteReg(R7, 0x00000000) +T714C 002:957.711 - 0.015ms returns 0 +T714C 002:957.728 JLINK_WriteReg(R8, 0x00000000) +T714C 002:957.744 - 0.016ms returns 0 +T714C 002:957.761 JLINK_WriteReg(R9, 0x30500458) +T714C 002:957.777 - 0.016ms returns 0 +T714C 002:957.794 JLINK_WriteReg(R10, 0x00000000) +T714C 002:957.810 - 0.016ms returns 0 +T714C 002:957.826 JLINK_WriteReg(R11, 0x00000000) +T714C 002:957.842 - 0.015ms returns 0 +T714C 002:957.858 JLINK_WriteReg(R12, 0x00000000) +T714C 002:957.874 - 0.015ms returns 0 +T714C 002:957.890 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:957.907 - 0.016ms returns 0 +T714C 002:957.923 JLINK_WriteReg(R14, 0x30500001) +T714C 002:957.938 - 0.015ms returns 0 +T714C 002:957.960 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:957.976 - 0.015ms returns 0 +T714C 002:957.992 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:958.008 - 0.015ms returns 0 +T714C 002:958.024 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:958.040 - 0.016ms returns 0 +T714C 002:958.056 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:958.073 - 0.016ms returns 0 +T714C 002:958.089 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:958.105 - 0.016ms returns 0 +T714C 002:958.122 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:958.138 - 0.016ms returns 0x000000BA +T714C 002:958.155 JLINK_Go() +T714C 002:958.172 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:958.436 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:960.188 - 2.033ms +T714C 002:960.825 JLINK_IsHalted() +T714C 002:962.940 - 2.114ms returns TRUE +T714C 002:962.970 JLINK_ReadReg(R15 (PC)) +T714C 002:962.989 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:963.224 - 0.253ms returns 0x30500000 +T714C 002:963.244 JLINK_ClrBPEx(BPHandle = 0x000000BA) +T714C 002:963.260 - 0.016ms returns 0x00 +T714C 002:963.277 JLINK_ReadReg(R0) +T714C 002:963.293 - 0.016ms returns 0x00000000 +T714C 002:963.743 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:963.774 Data: 62 75 69 6C 64 20 25 73 20 25 73 0A 00 00 00 00 ... +T714C 002:963.804 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:964.780 - 1.037ms returns 0x100 +T714C 002:964.803 JLINK_HasError() +T714C 002:964.820 JLINK_WriteReg(R0, 0x28013C00) +T714C 002:964.838 - 0.017ms returns 0 +T714C 002:964.854 JLINK_WriteReg(R1, 0x00000100) +T714C 002:964.870 - 0.016ms returns 0 +T714C 002:964.886 JLINK_WriteReg(R2, 0x30500674) +T714C 002:964.903 - 0.016ms returns 0 +T714C 002:964.919 JLINK_WriteReg(R3, 0x00000000) +T714C 002:964.935 - 0.015ms returns 0 +T714C 002:964.951 JLINK_WriteReg(R4, 0x00000000) +T714C 002:964.968 - 0.016ms returns 0 +T714C 002:964.984 JLINK_WriteReg(R5, 0x00000000) +T714C 002:965.000 - 0.016ms returns 0 +T714C 002:965.018 JLINK_WriteReg(R6, 0x00000000) +T714C 002:965.034 - 0.016ms returns 0 +T714C 002:965.050 JLINK_WriteReg(R7, 0x00000000) +T714C 002:965.066 - 0.015ms returns 0 +T714C 002:965.082 JLINK_WriteReg(R8, 0x00000000) +T714C 002:965.098 - 0.015ms returns 0 +T714C 002:965.114 JLINK_WriteReg(R9, 0x30500458) +T714C 002:965.130 - 0.016ms returns 0 +T714C 002:965.146 JLINK_WriteReg(R10, 0x00000000) +T714C 002:965.162 - 0.016ms returns 0 +T714C 002:965.178 JLINK_WriteReg(R11, 0x00000000) +T714C 002:965.194 - 0.015ms returns 0 +T714C 002:965.210 JLINK_WriteReg(R12, 0x00000000) +T714C 002:965.226 - 0.015ms returns 0 +T714C 002:965.243 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:965.260 - 0.017ms returns 0 +T714C 002:965.276 JLINK_WriteReg(R14, 0x30500001) +T714C 002:965.292 - 0.015ms returns 0 +T714C 002:965.308 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:965.324 - 0.016ms returns 0 +T714C 002:965.340 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:965.356 - 0.016ms returns 0 +T714C 002:965.373 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:965.388 - 0.015ms returns 0 +T714C 002:965.405 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:965.421 - 0.016ms returns 0 +T714C 002:965.438 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:965.453 - 0.016ms returns 0 +T714C 002:965.471 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:965.487 - 0.016ms returns 0x000000BB +T714C 002:965.503 JLINK_Go() +T714C 002:965.520 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:965.881 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:967.875 - 2.371ms +T714C 002:967.976 JLINK_IsHalted() +T714C 002:968.225 - 0.249ms returns FALSE +T714C 002:968.257 JLINK_HasError() +T714C 002:969.453 JLINK_IsHalted() +T714C 002:971.629 - 2.175ms returns TRUE +T714C 002:971.673 JLINK_ReadReg(R15 (PC)) +T714C 002:971.694 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:971.905 - 0.232ms returns 0x30500000 +T714C 002:971.926 JLINK_ClrBPEx(BPHandle = 0x000000BB) +T714C 002:971.942 - 0.016ms returns 0x00 +T714C 002:971.960 JLINK_ReadReg(R0) +T714C 002:971.976 - 0.017ms returns 0x00000000 +T714C 002:972.582 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:972.622 Data: 19 44 13 E0 B9 19 42 18 C2 E9 01 43 69 60 53 68 ... +T714C 002:972.655 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:973.645 - 1.063ms returns 0x100 +T714C 002:973.669 JLINK_HasError() +T714C 002:973.687 JLINK_WriteReg(R0, 0x28013D00) +T714C 002:973.705 - 0.018ms returns 0 +T714C 002:973.722 JLINK_WriteReg(R1, 0x00000100) +T714C 002:973.738 - 0.016ms returns 0 +T714C 002:973.757 JLINK_WriteReg(R2, 0x30500674) +T714C 002:973.773 - 0.016ms returns 0 +T714C 002:973.789 JLINK_WriteReg(R3, 0x00000000) +T714C 002:973.805 - 0.015ms returns 0 +T714C 002:973.821 JLINK_WriteReg(R4, 0x00000000) +T714C 002:973.837 - 0.015ms returns 0 +T714C 002:973.853 JLINK_WriteReg(R5, 0x00000000) +T714C 002:973.869 - 0.015ms returns 0 +T714C 002:973.885 JLINK_WriteReg(R6, 0x00000000) +T714C 002:973.901 - 0.015ms returns 0 +T714C 002:973.917 JLINK_WriteReg(R7, 0x00000000) +T714C 002:973.933 - 0.015ms returns 0 +T714C 002:973.949 JLINK_WriteReg(R8, 0x00000000) +T714C 002:973.965 - 0.015ms returns 0 +T714C 002:973.981 JLINK_WriteReg(R9, 0x30500458) +T714C 002:973.997 - 0.016ms returns 0 +T714C 002:974.013 JLINK_WriteReg(R10, 0x00000000) +T714C 002:974.029 - 0.015ms returns 0 +T714C 002:974.045 JLINK_WriteReg(R11, 0x00000000) +T714C 002:974.061 - 0.015ms returns 0 +T714C 002:974.077 JLINK_WriteReg(R12, 0x00000000) +T714C 002:974.093 - 0.016ms returns 0 +T714C 002:974.110 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:974.126 - 0.016ms returns 0 +T714C 002:974.143 JLINK_WriteReg(R14, 0x30500001) +T714C 002:974.159 - 0.016ms returns 0 +T714C 002:974.176 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:974.192 - 0.016ms returns 0 +T714C 002:974.209 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:974.225 - 0.015ms returns 0 +T714C 002:974.241 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:974.257 - 0.016ms returns 0 +T714C 002:974.274 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:974.289 - 0.015ms returns 0 +T714C 002:974.305 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:974.321 - 0.015ms returns 0 +T714C 002:974.338 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:974.354 - 0.016ms returns 0x000000BC +T714C 002:974.370 JLINK_Go() +T714C 002:974.388 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:974.680 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:976.563 - 2.193ms +T714C 002:976.586 JLINK_IsHalted() +T714C 002:976.824 - 0.237ms returns FALSE +T714C 002:976.845 JLINK_HasError() +T714C 002:978.446 JLINK_IsHalted() +T714C 002:980.672 - 2.227ms returns TRUE +T714C 002:980.694 JLINK_ReadReg(R15 (PC)) +T714C 002:980.711 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:980.948 - 0.254ms returns 0x30500000 +T714C 002:980.968 JLINK_ClrBPEx(BPHandle = 0x000000BC) +T714C 002:980.984 - 0.016ms returns 0x00 +T714C 002:981.001 JLINK_ReadReg(R0) +T714C 002:981.018 - 0.016ms returns 0x00000000 +T714C 002:981.473 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:981.505 Data: BD E8 F0 83 28 28 28 72 74 5F 75 69 6E 74 70 74 ... +T714C 002:981.533 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:982.597 - 1.121ms returns 0x100 +T714C 002:982.665 JLINK_HasError() +T714C 002:982.686 JLINK_WriteReg(R0, 0x28013E00) +T714C 002:982.708 - 0.022ms returns 0 +T714C 002:982.724 JLINK_WriteReg(R1, 0x00000100) +T714C 002:982.752 - 0.028ms returns 0 +T714C 002:982.770 JLINK_WriteReg(R2, 0x30500674) +T714C 002:982.786 - 0.016ms returns 0 +T714C 002:982.810 JLINK_WriteReg(R3, 0x00000000) +T714C 002:982.826 - 0.016ms returns 0 +T714C 002:982.876 JLINK_WriteReg(R4, 0x00000000) +T714C 002:982.894 - 0.018ms returns 0 +T714C 002:982.910 JLINK_WriteReg(R5, 0x00000000) +T714C 002:982.926 - 0.016ms returns 0 +T714C 002:982.942 JLINK_WriteReg(R6, 0x00000000) +T714C 002:982.959 - 0.016ms returns 0 +T714C 002:982.975 JLINK_WriteReg(R7, 0x00000000) +T714C 002:982.991 - 0.016ms returns 0 +T714C 002:983.008 JLINK_WriteReg(R8, 0x00000000) +T714C 002:983.024 - 0.016ms returns 0 +T714C 002:983.040 JLINK_WriteReg(R9, 0x30500458) +T714C 002:983.056 - 0.015ms returns 0 +T714C 002:983.072 JLINK_WriteReg(R10, 0x00000000) +T714C 002:983.092 - 0.020ms returns 0 +T714C 002:983.108 JLINK_WriteReg(R11, 0x00000000) +T714C 002:983.124 - 0.016ms returns 0 +T714C 002:983.141 JLINK_WriteReg(R12, 0x00000000) +T714C 002:983.157 - 0.016ms returns 0 +T714C 002:983.173 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:983.190 - 0.017ms returns 0 +T714C 002:983.212 JLINK_WriteReg(R14, 0x30500001) +T714C 002:983.229 - 0.016ms returns 0 +T714C 002:983.247 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:983.264 - 0.016ms returns 0 +T714C 002:983.280 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:983.296 - 0.016ms returns 0 +T714C 002:983.312 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:983.328 - 0.015ms returns 0 +T714C 002:983.344 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:983.360 - 0.015ms returns 0 +T714C 002:983.376 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:983.392 - 0.015ms returns 0 +T714C 002:983.409 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:983.426 - 0.017ms returns 0x000000BD +T714C 002:983.442 JLINK_Go() +T714C 002:983.461 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:983.750 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:985.722 - 2.279ms +T714C 002:986.362 JLINK_IsHalted() +T714C 002:988.485 - 2.122ms returns TRUE +T714C 002:988.523 JLINK_ReadReg(R15 (PC)) +T714C 002:988.542 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:988.779 - 0.255ms returns 0x30500000 +T714C 002:988.802 JLINK_ClrBPEx(BPHandle = 0x000000BD) +T714C 002:988.820 - 0.017ms returns 0x00 +T714C 002:988.836 JLINK_ReadReg(R0) +T714C 002:988.853 - 0.016ms returns 0x00000000 +T714C 002:989.477 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:989.513 Data: B0 42 0B D0 46 F6 A4 40 46 F6 88 41 C2 F6 01 00 ... +T714C 002:989.545 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:990.629 - 1.152ms returns 0x100 +T714C 002:990.653 JLINK_HasError() +T714C 002:990.671 JLINK_WriteReg(R0, 0x28013F00) +T714C 002:990.689 - 0.018ms returns 0 +T714C 002:990.706 JLINK_WriteReg(R1, 0x00000100) +T714C 002:990.723 - 0.017ms returns 0 +T714C 002:990.739 JLINK_WriteReg(R2, 0x30500674) +T714C 002:990.758 - 0.018ms returns 0 +T714C 002:990.774 JLINK_WriteReg(R3, 0x00000000) +T714C 002:990.790 - 0.016ms returns 0 +T714C 002:990.806 JLINK_WriteReg(R4, 0x00000000) +T714C 002:990.822 - 0.015ms returns 0 +T714C 002:990.838 JLINK_WriteReg(R5, 0x00000000) +T714C 002:990.854 - 0.015ms returns 0 +T714C 002:990.870 JLINK_WriteReg(R6, 0x00000000) +T714C 002:990.886 - 0.016ms returns 0 +T714C 002:990.903 JLINK_WriteReg(R7, 0x00000000) +T714C 002:990.919 - 0.015ms returns 0 +T714C 002:990.935 JLINK_WriteReg(R8, 0x00000000) +T714C 002:990.951 - 0.015ms returns 0 +T714C 002:990.967 JLINK_WriteReg(R9, 0x30500458) +T714C 002:990.983 - 0.015ms returns 0 +T714C 002:990.999 JLINK_WriteReg(R10, 0x00000000) +T714C 002:991.015 - 0.015ms returns 0 +T714C 002:991.030 JLINK_WriteReg(R11, 0x00000000) +T714C 002:991.046 - 0.016ms returns 0 +T714C 002:991.063 JLINK_WriteReg(R12, 0x00000000) +T714C 002:991.078 - 0.016ms returns 0 +T714C 002:991.095 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 002:991.111 - 0.016ms returns 0 +T714C 002:991.128 JLINK_WriteReg(R14, 0x30500001) +T714C 002:991.143 - 0.015ms returns 0 +T714C 002:991.159 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 002:991.175 - 0.015ms returns 0 +T714C 002:991.191 JLINK_WriteReg(XPSR, 0x01000000) +T714C 002:991.208 - 0.016ms returns 0 +T714C 002:991.224 JLINK_WriteReg(MSP, 0x30508000) +T714C 002:991.240 - 0.016ms returns 0 +T714C 002:991.256 JLINK_WriteReg(PSP, 0x30508000) +T714C 002:991.272 - 0.015ms returns 0 +T714C 002:991.288 JLINK_WriteReg(CFBP, 0x00000000) +T714C 002:991.304 - 0.016ms returns 0 +T714C 002:991.321 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 002:991.337 - 0.016ms returns 0x000000BE +T714C 002:991.353 JLINK_Go() +T714C 002:991.370 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 002:991.628 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 002:993.525 - 2.171ms +T714C 002:993.548 JLINK_IsHalted() +T714C 002:993.775 - 0.226ms returns FALSE +T714C 002:993.794 JLINK_HasError() +T714C 002:995.280 JLINK_IsHalted() +T714C 002:997.457 - 2.177ms returns TRUE +T714C 002:997.560 JLINK_ReadReg(R15 (PC)) +T714C 002:997.604 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 002:997.910 - 0.349ms returns 0x30500000 +T714C 002:997.951 JLINK_ClrBPEx(BPHandle = 0x000000BE) +T714C 002:997.970 - 0.018ms returns 0x00 +T714C 002:997.986 JLINK_ReadReg(R0) +T714C 002:998.004 - 0.017ms returns 0x00000000 +T714C 002:998.548 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 002:998.581 Data: A9 F1 10 01 44 F0 01 02 33 46 C7 E9 00 41 43 F8 ... +T714C 002:998.611 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 002:999.615 - 1.066ms returns 0x100 +T714C 002:999.673 JLINK_HasError() +T714C 002:999.692 JLINK_WriteReg(R0, 0x28014000) +T714C 002:999.712 - 0.020ms returns 0 +T714C 002:999.729 JLINK_WriteReg(R1, 0x00000100) +T714C 002:999.746 - 0.017ms returns 0 +T714C 002:999.762 JLINK_WriteReg(R2, 0x30500674) +T714C 002:999.778 - 0.015ms returns 0 +T714C 002:999.794 JLINK_WriteReg(R3, 0x00000000) +T714C 002:999.810 - 0.015ms returns 0 +T714C 002:999.826 JLINK_WriteReg(R4, 0x00000000) +T714C 002:999.843 - 0.016ms returns 0 +T714C 002:999.859 JLINK_WriteReg(R5, 0x00000000) +T714C 002:999.875 - 0.016ms returns 0 +T714C 002:999.891 JLINK_WriteReg(R6, 0x00000000) +T714C 002:999.907 - 0.016ms returns 0 +T714C 002:999.923 JLINK_WriteReg(R7, 0x00000000) +T714C 002:999.940 - 0.016ms returns 0 +T714C 002:999.956 JLINK_WriteReg(R8, 0x00000000) +T714C 002:999.972 - 0.015ms returns 0 +T714C 002:999.988 JLINK_WriteReg(R9, 0x30500458) +T714C 003:000.004 - 0.016ms returns 0 +T714C 003:000.021 JLINK_WriteReg(R10, 0x00000000) +T714C 003:000.037 - 0.016ms returns 0 +T714C 003:000.054 JLINK_WriteReg(R11, 0x00000000) +T714C 003:000.070 - 0.016ms returns 0 +T714C 003:000.086 JLINK_WriteReg(R12, 0x00000000) +T714C 003:000.102 - 0.015ms returns 0 +T714C 003:000.119 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:000.136 - 0.016ms returns 0 +T714C 003:000.152 JLINK_WriteReg(R14, 0x30500001) +T714C 003:000.167 - 0.015ms returns 0 +T714C 003:000.183 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:000.199 - 0.015ms returns 0 +T714C 003:000.215 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:000.231 - 0.015ms returns 0 +T714C 003:000.247 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:000.262 - 0.015ms returns 0 +T714C 003:000.278 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:000.321 - 0.043ms returns 0 +T714C 003:000.337 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:000.353 - 0.015ms returns 0 +T714C 003:000.370 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:000.387 - 0.017ms returns 0x000000BF +T714C 003:000.403 JLINK_Go() +T714C 003:000.421 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:000.665 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:002.620 - 2.217ms +T714C 003:002.643 JLINK_IsHalted() +T714C 003:002.832 - 0.188ms returns FALSE +T714C 003:002.852 JLINK_HasError() +T714C 003:004.783 JLINK_IsHalted() +T714C 003:006.944 - 2.162ms returns TRUE +T714C 003:006.966 JLINK_ReadReg(R15 (PC)) +T714C 003:006.984 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:007.212 - 0.246ms returns 0x30500000 +T714C 003:007.238 JLINK_ClrBPEx(BPHandle = 0x000000BF) +T714C 003:007.254 - 0.016ms returns 0x00 +T714C 003:007.271 JLINK_ReadReg(R0) +T714C 003:007.287 - 0.016ms returns 0x00000000 +T714C 003:007.852 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:007.887 Data: F8 D1 60 46 70 47 03 EB C2 00 D0 F8 04 C0 60 46 ... +T714C 003:007.917 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:008.904 - 1.052ms returns 0x100 +T714C 003:008.931 JLINK_HasError() +T714C 003:008.948 JLINK_WriteReg(R0, 0x28014100) +T714C 003:008.966 - 0.017ms returns 0 +T714C 003:008.982 JLINK_WriteReg(R1, 0x00000100) +T714C 003:008.998 - 0.016ms returns 0 +T714C 003:009.014 JLINK_WriteReg(R2, 0x30500674) +T714C 003:009.030 - 0.015ms returns 0 +T714C 003:009.046 JLINK_WriteReg(R3, 0x00000000) +T714C 003:009.062 - 0.015ms returns 0 +T714C 003:009.078 JLINK_WriteReg(R4, 0x00000000) +T714C 003:009.094 - 0.016ms returns 0 +T714C 003:009.110 JLINK_WriteReg(R5, 0x00000000) +T714C 003:009.127 - 0.016ms returns 0 +T714C 003:009.143 JLINK_WriteReg(R6, 0x00000000) +T714C 003:009.165 - 0.022ms returns 0 +T714C 003:009.182 JLINK_WriteReg(R7, 0x00000000) +T714C 003:009.198 - 0.016ms returns 0 +T714C 003:009.214 JLINK_WriteReg(R8, 0x00000000) +T714C 003:009.230 - 0.015ms returns 0 +T714C 003:009.247 JLINK_WriteReg(R9, 0x30500458) +T714C 003:009.262 - 0.015ms returns 0 +T714C 003:009.279 JLINK_WriteReg(R10, 0x00000000) +T714C 003:009.295 - 0.016ms returns 0 +T714C 003:009.311 JLINK_WriteReg(R11, 0x00000000) +T714C 003:009.327 - 0.015ms returns 0 +T714C 003:009.344 JLINK_WriteReg(R12, 0x00000000) +T714C 003:009.360 - 0.015ms returns 0 +T714C 003:009.376 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:009.393 - 0.016ms returns 0 +T714C 003:009.409 JLINK_WriteReg(R14, 0x30500001) +T714C 003:009.425 - 0.016ms returns 0 +T714C 003:009.441 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:009.457 - 0.015ms returns 0 +T714C 003:009.473 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:009.489 - 0.015ms returns 0 +T714C 003:009.505 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:009.521 - 0.016ms returns 0 +T714C 003:009.537 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:009.553 - 0.015ms returns 0 +T714C 003:009.569 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:009.584 - 0.016ms returns 0 +T714C 003:009.601 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:009.618 - 0.017ms returns 0x000000C0 +T714C 003:009.634 JLINK_Go() +T714C 003:009.652 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:009.961 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:011.846 - 2.212ms +T714C 003:011.877 JLINK_IsHalted() +T714C 003:012.123 - 0.246ms returns FALSE +T714C 003:012.149 JLINK_HasError() +T714C 003:015.060 JLINK_IsHalted() +T714C 003:017.475 - 2.414ms returns TRUE +T714C 003:017.542 JLINK_ReadReg(R15 (PC)) +T714C 003:017.565 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:017.839 - 0.296ms returns 0x30500000 +T714C 003:017.865 JLINK_ClrBPEx(BPHandle = 0x000000C0) +T714C 003:017.882 - 0.017ms returns 0x00 +T714C 003:017.899 JLINK_ReadReg(R0) +T714C 003:017.916 - 0.017ms returns 0x00000000 +T714C 003:018.518 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:018.558 Data: A7 F1 30 02 28 46 0C 21 FD F7 F0 FE 38 68 A0 42 ... +T714C 003:018.594 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:019.617 - 1.099ms returns 0x100 +T714C 003:019.644 JLINK_HasError() +T714C 003:019.662 JLINK_WriteReg(R0, 0x28014200) +T714C 003:019.681 - 0.019ms returns 0 +T714C 003:019.699 JLINK_WriteReg(R1, 0x00000100) +T714C 003:019.716 - 0.016ms returns 0 +T714C 003:019.733 JLINK_WriteReg(R2, 0x30500674) +T714C 003:019.749 - 0.015ms returns 0 +T714C 003:019.765 JLINK_WriteReg(R3, 0x00000000) +T714C 003:019.781 - 0.015ms returns 0 +T714C 003:019.798 JLINK_WriteReg(R4, 0x00000000) +T714C 003:019.814 - 0.016ms returns 0 +T714C 003:019.830 JLINK_WriteReg(R5, 0x00000000) +T714C 003:019.846 - 0.016ms returns 0 +T714C 003:019.862 JLINK_WriteReg(R6, 0x00000000) +T714C 003:019.878 - 0.015ms returns 0 +T714C 003:019.894 JLINK_WriteReg(R7, 0x00000000) +T714C 003:019.910 - 0.016ms returns 0 +T714C 003:019.926 JLINK_WriteReg(R8, 0x00000000) +T714C 003:019.942 - 0.016ms returns 0 +T714C 003:019.959 JLINK_WriteReg(R9, 0x30500458) +T714C 003:019.975 - 0.015ms returns 0 +T714C 003:019.991 JLINK_WriteReg(R10, 0x00000000) +T714C 003:020.007 - 0.016ms returns 0 +T714C 003:020.023 JLINK_WriteReg(R11, 0x00000000) +T714C 003:020.039 - 0.015ms returns 0 +T714C 003:020.056 JLINK_WriteReg(R12, 0x00000000) +T714C 003:020.072 - 0.015ms returns 0 +T714C 003:020.088 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:020.105 - 0.016ms returns 0 +T714C 003:020.121 JLINK_WriteReg(R14, 0x30500001) +T714C 003:020.137 - 0.015ms returns 0 +T714C 003:020.153 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:020.169 - 0.016ms returns 0 +T714C 003:020.185 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:020.201 - 0.015ms returns 0 +T714C 003:020.217 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:020.232 - 0.015ms returns 0 +T714C 003:020.249 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:020.264 - 0.015ms returns 0 +T714C 003:020.281 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:020.296 - 0.015ms returns 0 +T714C 003:020.384 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:020.401 - 0.017ms returns 0x000000C1 +T714C 003:020.418 JLINK_Go() +T714C 003:020.440 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:020.720 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:022.643 - 2.225ms +T714C 003:022.667 JLINK_IsHalted() +T714C 003:022.866 - 0.198ms returns FALSE +T714C 003:022.889 JLINK_HasError() +T714C 003:024.234 JLINK_IsHalted() +T714C 003:026.460 - 2.226ms returns TRUE +T714C 003:026.487 JLINK_ReadReg(R15 (PC)) +T714C 003:026.504 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:026.736 - 0.249ms returns 0x30500000 +T714C 003:026.774 JLINK_ClrBPEx(BPHandle = 0x000000C1) +T714C 003:026.793 - 0.018ms returns 0x00 +T714C 003:026.811 JLINK_ReadReg(R0) +T714C 003:026.830 - 0.019ms returns 0x00000000 +T714C 003:027.310 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:027.344 Data: 01 60 70 47 F0 B5 81 B0 41 F2 18 65 C2 F2 00 05 ... +T714C 003:027.374 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:028.472 - 1.162ms returns 0x100 +T714C 003:028.523 JLINK_HasError() +T714C 003:028.542 JLINK_WriteReg(R0, 0x28014300) +T714C 003:028.562 - 0.020ms returns 0 +T714C 003:028.579 JLINK_WriteReg(R1, 0x00000100) +T714C 003:028.595 - 0.016ms returns 0 +T714C 003:028.612 JLINK_WriteReg(R2, 0x30500674) +T714C 003:028.628 - 0.016ms returns 0 +T714C 003:028.645 JLINK_WriteReg(R3, 0x00000000) +T714C 003:028.661 - 0.016ms returns 0 +T714C 003:028.677 JLINK_WriteReg(R4, 0x00000000) +T714C 003:028.693 - 0.016ms returns 0 +T714C 003:028.709 JLINK_WriteReg(R5, 0x00000000) +T714C 003:028.725 - 0.016ms returns 0 +T714C 003:028.742 JLINK_WriteReg(R6, 0x00000000) +T714C 003:028.806 - 0.064ms returns 0 +T714C 003:028.824 JLINK_WriteReg(R7, 0x00000000) +T714C 003:028.840 - 0.016ms returns 0 +T714C 003:028.856 JLINK_WriteReg(R8, 0x00000000) +T714C 003:028.873 - 0.016ms returns 0 +T714C 003:028.889 JLINK_WriteReg(R9, 0x30500458) +T714C 003:028.914 - 0.024ms returns 0 +T714C 003:028.930 JLINK_WriteReg(R10, 0x00000000) +T714C 003:028.946 - 0.016ms returns 0 +T714C 003:028.962 JLINK_WriteReg(R11, 0x00000000) +T714C 003:028.978 - 0.016ms returns 0 +T714C 003:028.995 JLINK_WriteReg(R12, 0x00000000) +T714C 003:029.011 - 0.015ms returns 0 +T714C 003:029.027 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:029.044 - 0.017ms returns 0 +T714C 003:029.061 JLINK_WriteReg(R14, 0x30500001) +T714C 003:029.076 - 0.015ms returns 0 +T714C 003:029.093 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:029.108 - 0.015ms returns 0 +T714C 003:029.124 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:029.140 - 0.015ms returns 0 +T714C 003:029.156 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:029.172 - 0.015ms returns 0 +T714C 003:029.189 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:029.205 - 0.015ms returns 0 +T714C 003:029.221 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:029.237 - 0.016ms returns 0 +T714C 003:029.254 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:029.271 - 0.016ms returns 0x000000C2 +T714C 003:029.287 JLINK_Go() +T714C 003:029.305 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:029.719 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:031.839 - 2.551ms +T714C 003:031.891 JLINK_IsHalted() +T714C 003:032.149 - 0.257ms returns FALSE +T714C 003:032.196 JLINK_HasError() +T714C 003:033.970 JLINK_IsHalted() +T714C 003:036.387 - 2.416ms returns TRUE +T714C 003:036.434 JLINK_ReadReg(R15 (PC)) +T714C 003:036.453 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:036.758 - 0.324ms returns 0x30500000 +T714C 003:036.806 JLINK_ClrBPEx(BPHandle = 0x000000C2) +T714C 003:036.823 - 0.017ms returns 0x00 +T714C 003:036.840 JLINK_ReadReg(R0) +T714C 003:036.857 - 0.017ms returns 0x00000000 +T714C 003:037.466 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:037.503 Data: 73 65 6C 66 28 29 20 7C 7C 20 72 74 5F 63 72 69 ... +T714C 003:037.533 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:038.679 - 1.212ms returns 0x100 +T714C 003:038.728 JLINK_HasError() +T714C 003:038.746 JLINK_WriteReg(R0, 0x28014400) +T714C 003:038.765 - 0.019ms returns 0 +T714C 003:038.788 JLINK_WriteReg(R1, 0x00000100) +T714C 003:038.807 - 0.019ms returns 0 +T714C 003:038.823 JLINK_WriteReg(R2, 0x30500674) +T714C 003:038.838 - 0.015ms returns 0 +T714C 003:038.854 JLINK_WriteReg(R3, 0x00000000) +T714C 003:038.870 - 0.015ms returns 0 +T714C 003:038.886 JLINK_WriteReg(R4, 0x00000000) +T714C 003:038.902 - 0.016ms returns 0 +T714C 003:038.918 JLINK_WriteReg(R5, 0x00000000) +T714C 003:038.934 - 0.015ms returns 0 +T714C 003:038.949 JLINK_WriteReg(R6, 0x00000000) +T714C 003:038.965 - 0.015ms returns 0 +T714C 003:038.981 JLINK_WriteReg(R7, 0x00000000) +T714C 003:038.996 - 0.015ms returns 0 +T714C 003:039.013 JLINK_WriteReg(R8, 0x00000000) +T714C 003:039.059 - 0.046ms returns 0 +T714C 003:039.075 JLINK_WriteReg(R9, 0x30500458) +T714C 003:039.090 - 0.015ms returns 0 +T714C 003:039.107 JLINK_WriteReg(R10, 0x00000000) +T714C 003:039.122 - 0.015ms returns 0 +T714C 003:039.138 JLINK_WriteReg(R11, 0x00000000) +T714C 003:039.154 - 0.015ms returns 0 +T714C 003:039.170 JLINK_WriteReg(R12, 0x00000000) +T714C 003:039.185 - 0.015ms returns 0 +T714C 003:039.201 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:039.218 - 0.016ms returns 0 +T714C 003:039.234 JLINK_WriteReg(R14, 0x30500001) +T714C 003:039.249 - 0.015ms returns 0 +T714C 003:039.265 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:039.280 - 0.015ms returns 0 +T714C 003:039.296 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:039.311 - 0.015ms returns 0 +T714C 003:039.327 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:039.343 - 0.015ms returns 0 +T714C 003:039.359 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:039.374 - 0.015ms returns 0 +T714C 003:039.390 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:039.405 - 0.015ms returns 0 +T714C 003:039.421 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:039.437 - 0.016ms returns 0x000000C3 +T714C 003:039.453 JLINK_Go() +T714C 003:039.470 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:039.800 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:042.002 - 2.548ms +T714C 003:042.057 JLINK_IsHalted() +T714C 003:042.336 - 0.278ms returns FALSE +T714C 003:042.389 JLINK_HasError() +T714C 003:044.264 JLINK_IsHalted() +T714C 003:046.600 - 2.335ms returns TRUE +T714C 003:046.638 JLINK_ReadReg(R15 (PC)) +T714C 003:046.658 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:046.933 - 0.295ms returns 0x30500000 +T714C 003:046.962 JLINK_ClrBPEx(BPHandle = 0x000000C3) +T714C 003:046.981 - 0.018ms returns 0x00 +T714C 003:046.999 JLINK_ReadReg(R0) +T714C 003:047.016 - 0.017ms returns 0x00000000 +T714C 003:047.610 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:047.643 Data: 64 5F 63 72 65 61 74 65 00 00 00 00 B0 B5 40 F2 ... +T714C 003:047.694 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:048.713 - 1.102ms returns 0x100 +T714C 003:048.760 JLINK_HasError() +T714C 003:048.779 JLINK_WriteReg(R0, 0x28014500) +T714C 003:048.800 - 0.020ms returns 0 +T714C 003:048.816 JLINK_WriteReg(R1, 0x00000100) +T714C 003:048.833 - 0.016ms returns 0 +T714C 003:048.849 JLINK_WriteReg(R2, 0x30500674) +T714C 003:048.865 - 0.016ms returns 0 +T714C 003:048.893 JLINK_WriteReg(R3, 0x00000000) +T714C 003:048.909 - 0.016ms returns 0 +T714C 003:048.926 JLINK_WriteReg(R4, 0x00000000) +T714C 003:048.942 - 0.016ms returns 0 +T714C 003:048.958 JLINK_WriteReg(R5, 0x00000000) +T714C 003:048.974 - 0.015ms returns 0 +T714C 003:048.990 JLINK_WriteReg(R6, 0x00000000) +T714C 003:049.006 - 0.015ms returns 0 +T714C 003:049.022 JLINK_WriteReg(R7, 0x00000000) +T714C 003:049.037 - 0.015ms returns 0 +T714C 003:049.054 JLINK_WriteReg(R8, 0x00000000) +T714C 003:049.069 - 0.015ms returns 0 +T714C 003:049.086 JLINK_WriteReg(R9, 0x30500458) +T714C 003:049.103 - 0.017ms returns 0 +T714C 003:049.119 JLINK_WriteReg(R10, 0x00000000) +T714C 003:049.135 - 0.016ms returns 0 +T714C 003:049.152 JLINK_WriteReg(R11, 0x00000000) +T714C 003:049.168 - 0.015ms returns 0 +T714C 003:049.184 JLINK_WriteReg(R12, 0x00000000) +T714C 003:049.200 - 0.015ms returns 0 +T714C 003:049.216 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:049.233 - 0.017ms returns 0 +T714C 003:049.249 JLINK_WriteReg(R14, 0x30500001) +T714C 003:049.271 - 0.022ms returns 0 +T714C 003:049.290 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:049.307 - 0.016ms returns 0 +T714C 003:049.324 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:049.342 - 0.018ms returns 0 +T714C 003:049.358 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:049.375 - 0.016ms returns 0 +T714C 003:049.390 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:049.404 - 0.014ms returns 0 +T714C 003:049.419 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:049.434 - 0.014ms returns 0 +T714C 003:049.450 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:049.465 - 0.016ms returns 0x000000C4 +T714C 003:049.480 JLINK_Go() +T714C 003:049.497 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:049.895 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:051.999 - 2.518ms +T714C 003:052.046 JLINK_IsHalted() +T714C 003:052.358 - 0.311ms returns FALSE +T714C 003:052.404 JLINK_HasError() +T714C 003:054.824 JLINK_IsHalted() +T714C 003:057.149 - 2.324ms returns TRUE +T714C 003:057.196 JLINK_ReadReg(R15 (PC)) +T714C 003:057.215 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:057.473 - 0.276ms returns 0x30500000 +T714C 003:057.520 JLINK_ClrBPEx(BPHandle = 0x000000C4) +T714C 003:057.538 - 0.018ms returns 0x00 +T714C 003:057.555 JLINK_ReadReg(R0) +T714C 003:057.572 - 0.016ms returns 0x00000000 +T714C 003:058.507 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:058.546 Data: FC F7 28 FC 0D 9E BA F1 00 0F 0B D1 46 F6 09 70 ... +T714C 003:058.576 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:059.719 - 1.210ms returns 0x100 +T714C 003:059.776 JLINK_HasError() +T714C 003:059.795 JLINK_WriteReg(R0, 0x28014600) +T714C 003:059.816 - 0.020ms returns 0 +T714C 003:059.833 JLINK_WriteReg(R1, 0x00000100) +T714C 003:059.850 - 0.016ms returns 0 +T714C 003:059.866 JLINK_WriteReg(R2, 0x30500674) +T714C 003:059.882 - 0.016ms returns 0 +T714C 003:059.899 JLINK_WriteReg(R3, 0x00000000) +T714C 003:059.915 - 0.016ms returns 0 +T714C 003:059.932 JLINK_WriteReg(R4, 0x00000000) +T714C 003:059.948 - 0.016ms returns 0 +T714C 003:059.964 JLINK_WriteReg(R5, 0x00000000) +T714C 003:059.981 - 0.017ms returns 0 +T714C 003:060.006 JLINK_WriteReg(R6, 0x00000000) +T714C 003:060.022 - 0.016ms returns 0 +T714C 003:060.039 JLINK_WriteReg(R7, 0x00000000) +T714C 003:060.054 - 0.015ms returns 0 +T714C 003:060.071 JLINK_WriteReg(R8, 0x00000000) +T714C 003:060.094 - 0.023ms returns 0 +T714C 003:060.111 JLINK_WriteReg(R9, 0x30500458) +T714C 003:060.127 - 0.016ms returns 0 +T714C 003:060.143 JLINK_WriteReg(R10, 0x00000000) +T714C 003:060.159 - 0.015ms returns 0 +T714C 003:060.175 JLINK_WriteReg(R11, 0x00000000) +T714C 003:060.191 - 0.016ms returns 0 +T714C 003:060.208 JLINK_WriteReg(R12, 0x00000000) +T714C 003:060.224 - 0.016ms returns 0 +T714C 003:060.241 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:060.258 - 0.017ms returns 0 +T714C 003:060.274 JLINK_WriteReg(R14, 0x30500001) +T714C 003:060.290 - 0.015ms returns 0 +T714C 003:060.307 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:060.322 - 0.015ms returns 0 +T714C 003:060.339 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:060.355 - 0.016ms returns 0 +T714C 003:060.371 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:060.387 - 0.015ms returns 0 +T714C 003:060.403 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:060.419 - 0.015ms returns 0 +T714C 003:060.435 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:060.451 - 0.016ms returns 0 +T714C 003:060.468 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:060.484 - 0.016ms returns 0x000000C5 +T714C 003:060.500 JLINK_Go() +T714C 003:060.519 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:060.784 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:062.936 - 2.435ms +T714C 003:062.986 JLINK_IsHalted() +T714C 003:063.272 - 0.285ms returns FALSE +T714C 003:063.318 JLINK_HasError() +T714C 003:064.988 JLINK_IsHalted() +T714C 003:067.315 - 2.326ms returns TRUE +T714C 003:067.364 JLINK_ReadReg(R15 (PC)) +T714C 003:067.384 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:067.706 - 0.342ms returns 0x30500000 +T714C 003:067.730 JLINK_ClrBPEx(BPHandle = 0x000000C5) +T714C 003:067.752 - 0.022ms returns 0x00 +T714C 003:067.771 JLINK_ReadReg(R0) +T714C 003:067.788 - 0.016ms returns 0x00000000 +T714C 003:068.615 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:068.651 Data: 20 46 FE F7 4D FA 01 28 0B D0 46 F6 57 70 46 F6 ... +T714C 003:068.683 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:069.728 - 1.113ms returns 0x100 +T714C 003:069.777 JLINK_HasError() +T714C 003:069.796 JLINK_WriteReg(R0, 0x28014700) +T714C 003:069.815 - 0.019ms returns 0 +T714C 003:069.832 JLINK_WriteReg(R1, 0x00000100) +T714C 003:069.848 - 0.016ms returns 0 +T714C 003:069.865 JLINK_WriteReg(R2, 0x30500674) +T714C 003:069.880 - 0.015ms returns 0 +T714C 003:069.897 JLINK_WriteReg(R3, 0x00000000) +T714C 003:069.913 - 0.016ms returns 0 +T714C 003:069.929 JLINK_WriteReg(R4, 0x00000000) +T714C 003:069.944 - 0.015ms returns 0 +T714C 003:069.960 JLINK_WriteReg(R5, 0x00000000) +T714C 003:069.976 - 0.015ms returns 0 +T714C 003:069.991 JLINK_WriteReg(R6, 0x00000000) +T714C 003:070.007 - 0.015ms returns 0 +T714C 003:070.022 JLINK_WriteReg(R7, 0x00000000) +T714C 003:070.038 - 0.015ms returns 0 +T714C 003:070.053 JLINK_WriteReg(R8, 0x00000000) +T714C 003:070.069 - 0.015ms returns 0 +T714C 003:070.085 JLINK_WriteReg(R9, 0x30500458) +T714C 003:070.100 - 0.015ms returns 0 +T714C 003:070.116 JLINK_WriteReg(R10, 0x00000000) +T714C 003:070.133 - 0.016ms returns 0 +T714C 003:070.149 JLINK_WriteReg(R11, 0x00000000) +T714C 003:070.165 - 0.015ms returns 0 +T714C 003:070.180 JLINK_WriteReg(R12, 0x00000000) +T714C 003:070.196 - 0.016ms returns 0 +T714C 003:070.212 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:070.229 - 0.016ms returns 0 +T714C 003:070.245 JLINK_WriteReg(R14, 0x30500001) +T714C 003:070.260 - 0.015ms returns 0 +T714C 003:070.276 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:070.292 - 0.015ms returns 0 +T714C 003:070.308 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:070.324 - 0.015ms returns 0 +T714C 003:070.340 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:070.356 - 0.015ms returns 0 +T714C 003:070.372 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:070.387 - 0.015ms returns 0 +T714C 003:070.403 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:070.419 - 0.015ms returns 0 +T714C 003:070.438 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:070.454 - 0.017ms returns 0x000000C6 +T714C 003:070.470 JLINK_Go() +T714C 003:070.487 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:070.799 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:072.947 - 2.476ms +T714C 003:072.994 JLINK_IsHalted() +T714C 003:073.318 - 0.324ms returns FALSE +T714C 003:073.376 JLINK_HasError() +T714C 003:075.004 JLINK_IsHalted() +T714C 003:077.284 - 2.280ms returns TRUE +T714C 003:077.335 JLINK_ReadReg(R15 (PC)) +T714C 003:077.354 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:077.566 - 0.230ms returns 0x30500000 +T714C 003:077.587 JLINK_ClrBPEx(BPHandle = 0x000000C6) +T714C 003:077.604 - 0.016ms returns 0x00 +T714C 003:077.620 JLINK_ReadReg(R0) +T714C 003:077.637 - 0.016ms returns 0x00000000 +T714C 003:078.231 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:078.265 Data: 29 FB 20 46 FE F7 CC F9 01 28 0B D0 46 F6 57 70 ... +T714C 003:078.295 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:079.383 - 1.151ms returns 0x100 +T714C 003:079.408 JLINK_HasError() +T714C 003:079.425 JLINK_WriteReg(R0, 0x28014800) +T714C 003:079.444 - 0.018ms returns 0 +T714C 003:079.461 JLINK_WriteReg(R1, 0x00000100) +T714C 003:079.477 - 0.015ms returns 0 +T714C 003:079.494 JLINK_WriteReg(R2, 0x30500674) +T714C 003:079.510 - 0.016ms returns 0 +T714C 003:079.526 JLINK_WriteReg(R3, 0x00000000) +T714C 003:079.542 - 0.016ms returns 0 +T714C 003:079.559 JLINK_WriteReg(R4, 0x00000000) +T714C 003:079.575 - 0.016ms returns 0 +T714C 003:079.591 JLINK_WriteReg(R5, 0x00000000) +T714C 003:079.607 - 0.016ms returns 0 +T714C 003:079.623 JLINK_WriteReg(R6, 0x00000000) +T714C 003:079.639 - 0.016ms returns 0 +T714C 003:079.657 JLINK_WriteReg(R7, 0x00000000) +T714C 003:079.672 - 0.015ms returns 0 +T714C 003:079.688 JLINK_WriteReg(R8, 0x00000000) +T714C 003:079.704 - 0.016ms returns 0 +T714C 003:079.726 JLINK_WriteReg(R9, 0x30500458) +T714C 003:079.745 - 0.018ms returns 0 +T714C 003:079.762 JLINK_WriteReg(R10, 0x00000000) +T714C 003:079.777 - 0.015ms returns 0 +T714C 003:079.793 JLINK_WriteReg(R11, 0x00000000) +T714C 003:079.809 - 0.016ms returns 0 +T714C 003:079.825 JLINK_WriteReg(R12, 0x00000000) +T714C 003:079.841 - 0.015ms returns 0 +T714C 003:079.858 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:079.874 - 0.017ms returns 0 +T714C 003:079.890 JLINK_WriteReg(R14, 0x30500001) +T714C 003:079.906 - 0.015ms returns 0 +T714C 003:079.922 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:079.938 - 0.016ms returns 0 +T714C 003:079.954 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:079.970 - 0.016ms returns 0 +T714C 003:079.987 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:080.003 - 0.016ms returns 0 +T714C 003:080.019 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:080.036 - 0.016ms returns 0 +T714C 003:080.052 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:080.068 - 0.016ms returns 0 +T714C 003:080.085 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:080.103 - 0.017ms returns 0x000000C7 +T714C 003:080.122 JLINK_Go() +T714C 003:080.140 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:080.477 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:082.417 - 2.295ms +T714C 003:082.469 JLINK_IsHalted() +T714C 003:082.702 - 0.233ms returns FALSE +T714C 003:082.724 JLINK_HasError() +T714C 003:084.021 JLINK_IsHalted() +T714C 003:086.244 - 2.224ms returns TRUE +T714C 003:086.266 JLINK_ReadReg(R15 (PC)) +T714C 003:086.284 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:086.541 - 0.274ms returns 0x30500000 +T714C 003:086.561 JLINK_ClrBPEx(BPHandle = 0x000000C7) +T714C 003:086.578 - 0.016ms returns 0x00 +T714C 003:086.594 JLINK_ReadReg(R0) +T714C 003:086.611 - 0.016ms returns 0x00000000 +T714C 003:087.185 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:087.219 Data: 1C BF 20 46 88 47 00 20 01 B0 F0 BD 74 68 72 65 ... +T714C 003:087.251 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:088.163 - 0.977ms returns 0x100 +T714C 003:088.238 JLINK_HasError() +T714C 003:088.264 JLINK_WriteReg(R0, 0x28014900) +T714C 003:088.290 - 0.025ms returns 0 +T714C 003:088.315 JLINK_WriteReg(R1, 0x00000100) +T714C 003:088.339 - 0.023ms returns 0 +T714C 003:088.359 JLINK_WriteReg(R2, 0x30500674) +T714C 003:088.379 - 0.020ms returns 0 +T714C 003:088.396 JLINK_WriteReg(R3, 0x00000000) +T714C 003:088.412 - 0.015ms returns 0 +T714C 003:088.429 JLINK_WriteReg(R4, 0x00000000) +T714C 003:088.445 - 0.015ms returns 0 +T714C 003:088.461 JLINK_WriteReg(R5, 0x00000000) +T714C 003:088.477 - 0.015ms returns 0 +T714C 003:088.493 JLINK_WriteReg(R6, 0x00000000) +T714C 003:088.508 - 0.015ms returns 0 +T714C 003:088.524 JLINK_WriteReg(R7, 0x00000000) +T714C 003:088.540 - 0.015ms returns 0 +T714C 003:088.556 JLINK_WriteReg(R8, 0x00000000) +T714C 003:088.572 - 0.015ms returns 0 +T714C 003:088.588 JLINK_WriteReg(R9, 0x30500458) +T714C 003:088.604 - 0.015ms returns 0 +T714C 003:088.620 JLINK_WriteReg(R10, 0x00000000) +T714C 003:088.644 - 0.023ms returns 0 +T714C 003:088.660 JLINK_WriteReg(R11, 0x00000000) +T714C 003:088.676 - 0.016ms returns 0 +T714C 003:088.693 JLINK_WriteReg(R12, 0x00000000) +T714C 003:088.708 - 0.015ms returns 0 +T714C 003:088.725 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:088.742 - 0.017ms returns 0 +T714C 003:088.758 JLINK_WriteReg(R14, 0x30500001) +T714C 003:088.774 - 0.016ms returns 0 +T714C 003:088.791 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:088.806 - 0.015ms returns 0 +T714C 003:088.823 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:088.839 - 0.016ms returns 0 +T714C 003:088.855 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:088.871 - 0.015ms returns 0 +T714C 003:088.887 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:088.903 - 0.015ms returns 0 +T714C 003:088.919 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:088.935 - 0.015ms returns 0 +T714C 003:088.951 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:088.968 - 0.016ms returns 0x000000C8 +T714C 003:088.984 JLINK_Go() +T714C 003:089.002 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:089.295 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:091.249 - 2.265ms +T714C 003:091.284 JLINK_IsHalted() +T714C 003:091.608 - 0.323ms returns FALSE +T714C 003:091.641 JLINK_HasError() +T714C 003:093.043 JLINK_IsHalted() +T714C 003:095.268 - 2.224ms returns TRUE +T714C 003:095.914 JLINK_ReadReg(R15 (PC)) +T714C 003:095.936 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:096.182 - 0.267ms returns 0x30500000 +T714C 003:096.202 JLINK_ClrBPEx(BPHandle = 0x000000C8) +T714C 003:096.221 - 0.018ms returns 0x00 +T714C 003:096.238 JLINK_ReadReg(R0) +T714C 003:096.254 - 0.016ms returns 0x00000000 +T714C 003:096.806 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:096.839 Data: 16 E0 00 BF 40 F2 0C 33 C2 F2 00 03 19 68 02 68 ... +T714C 003:096.869 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:097.874 - 1.068ms returns 0x100 +T714C 003:097.897 JLINK_HasError() +T714C 003:097.915 JLINK_WriteReg(R0, 0x28014A00) +T714C 003:097.932 - 0.017ms returns 0 +T714C 003:097.950 JLINK_WriteReg(R1, 0x00000100) +T714C 003:097.966 - 0.016ms returns 0 +T714C 003:097.982 JLINK_WriteReg(R2, 0x30500674) +T714C 003:097.998 - 0.016ms returns 0 +T714C 003:098.015 JLINK_WriteReg(R3, 0x00000000) +T714C 003:098.030 - 0.015ms returns 0 +T714C 003:098.046 JLINK_WriteReg(R4, 0x00000000) +T714C 003:098.063 - 0.016ms returns 0 +T714C 003:098.079 JLINK_WriteReg(R5, 0x00000000) +T714C 003:098.095 - 0.016ms returns 0 +T714C 003:098.112 JLINK_WriteReg(R6, 0x00000000) +T714C 003:098.128 - 0.015ms returns 0 +T714C 003:098.144 JLINK_WriteReg(R7, 0x00000000) +T714C 003:098.161 - 0.016ms returns 0 +T714C 003:098.177 JLINK_WriteReg(R8, 0x00000000) +T714C 003:098.192 - 0.015ms returns 0 +T714C 003:098.209 JLINK_WriteReg(R9, 0x30500458) +T714C 003:098.225 - 0.016ms returns 0 +T714C 003:098.241 JLINK_WriteReg(R10, 0x00000000) +T714C 003:098.257 - 0.015ms returns 0 +T714C 003:098.273 JLINK_WriteReg(R11, 0x00000000) +T714C 003:098.289 - 0.015ms returns 0 +T714C 003:098.306 JLINK_WriteReg(R12, 0x00000000) +T714C 003:098.322 - 0.015ms returns 0 +T714C 003:098.338 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:098.355 - 0.017ms returns 0 +T714C 003:098.371 JLINK_WriteReg(R14, 0x30500001) +T714C 003:098.388 - 0.016ms returns 0 +T714C 003:098.404 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:098.419 - 0.015ms returns 0 +T714C 003:098.436 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:098.452 - 0.016ms returns 0 +T714C 003:098.468 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:098.484 - 0.016ms returns 0 +T714C 003:098.500 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:098.515 - 0.015ms returns 0 +T714C 003:098.532 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:098.547 - 0.015ms returns 0 +T714C 003:098.564 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:098.581 - 0.016ms returns 0x000000C9 +T714C 003:098.597 JLINK_Go() +T714C 003:098.615 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:098.926 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:100.946 - 2.347ms +T714C 003:100.997 JLINK_IsHalted() +T714C 003:101.261 - 0.264ms returns FALSE +T714C 003:101.288 JLINK_HasError() +T714C 003:102.993 JLINK_IsHalted() +T714C 003:105.328 - 2.334ms returns TRUE +T714C 003:105.399 JLINK_ReadReg(R15 (PC)) +T714C 003:105.428 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:105.714 - 0.315ms returns 0x30500000 +T714C 003:105.747 JLINK_ClrBPEx(BPHandle = 0x000000C9) +T714C 003:105.842 - 0.094ms returns 0x00 +T714C 003:105.861 JLINK_ReadReg(R0) +T714C 003:105.879 - 0.018ms returns 0x00000000 +T714C 003:106.676 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:106.719 Data: 40 F2 6C 20 C2 F2 00 00 21 46 FF F7 CF FA 03 B0 ... +T714C 003:106.753 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:107.752 - 1.075ms returns 0x100 +T714C 003:107.783 JLINK_HasError() +T714C 003:107.817 JLINK_WriteReg(R0, 0x28014B00) +T714C 003:107.836 - 0.019ms returns 0 +T714C 003:107.853 JLINK_WriteReg(R1, 0x00000100) +T714C 003:107.869 - 0.016ms returns 0 +T714C 003:107.886 JLINK_WriteReg(R2, 0x30500674) +T714C 003:107.902 - 0.016ms returns 0 +T714C 003:107.918 JLINK_WriteReg(R3, 0x00000000) +T714C 003:107.939 - 0.021ms returns 0 +T714C 003:107.958 JLINK_WriteReg(R4, 0x00000000) +T714C 003:107.973 - 0.015ms returns 0 +T714C 003:107.991 JLINK_WriteReg(R5, 0x00000000) +T714C 003:108.007 - 0.016ms returns 0 +T714C 003:108.038 JLINK_WriteReg(R6, 0x00000000) +T714C 003:108.054 - 0.016ms returns 0 +T714C 003:108.071 JLINK_WriteReg(R7, 0x00000000) +T714C 003:108.087 - 0.016ms returns 0 +T714C 003:108.103 JLINK_WriteReg(R8, 0x00000000) +T714C 003:108.119 - 0.016ms returns 0 +T714C 003:108.136 JLINK_WriteReg(R9, 0x30500458) +T714C 003:108.152 - 0.016ms returns 0 +T714C 003:108.168 JLINK_WriteReg(R10, 0x00000000) +T714C 003:108.184 - 0.016ms returns 0 +T714C 003:108.201 JLINK_WriteReg(R11, 0x00000000) +T714C 003:108.216 - 0.015ms returns 0 +T714C 003:108.234 JLINK_WriteReg(R12, 0x00000000) +T714C 003:108.250 - 0.015ms returns 0 +T714C 003:108.266 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:108.297 - 0.030ms returns 0 +T714C 003:108.314 JLINK_WriteReg(R14, 0x30500001) +T714C 003:108.330 - 0.016ms returns 0 +T714C 003:108.346 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:108.363 - 0.016ms returns 0 +T714C 003:108.379 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:108.400 - 0.021ms returns 0 +T714C 003:108.416 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:108.432 - 0.015ms returns 0 +T714C 003:108.448 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:108.464 - 0.016ms returns 0 +T714C 003:108.480 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:108.496 - 0.015ms returns 0 +T714C 003:108.514 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:108.545 - 0.031ms returns 0x000000CA +T714C 003:108.561 JLINK_Go() +T714C 003:108.579 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:108.840 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:110.672 - 2.111ms +T714C 003:110.700 JLINK_IsHalted() +T714C 003:110.930 - 0.230ms returns FALSE +T714C 003:110.952 JLINK_HasError() +T714C 003:112.187 JLINK_IsHalted() +T714C 003:114.482 - 2.294ms returns TRUE +T714C 003:114.528 JLINK_ReadReg(R15 (PC)) +T714C 003:114.549 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:114.841 - 0.312ms returns 0x30500000 +T714C 003:114.886 JLINK_ClrBPEx(BPHandle = 0x000000CA) +T714C 003:114.947 - 0.061ms returns 0x00 +T714C 003:114.965 JLINK_ReadReg(R0) +T714C 003:114.983 - 0.018ms returns 0x00000000 +T714C 003:115.771 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:115.822 Data: 0E E0 68 7B 40 F0 02 00 68 73 09 E0 2C 62 07 E0 ... +T714C 003:115.858 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:116.830 - 1.060ms returns 0x100 +T714C 003:116.867 JLINK_HasError() +T714C 003:116.886 JLINK_WriteReg(R0, 0x28014C00) +T714C 003:116.906 - 0.020ms returns 0 +T714C 003:116.922 JLINK_WriteReg(R1, 0x00000100) +T714C 003:116.938 - 0.016ms returns 0 +T714C 003:116.955 JLINK_WriteReg(R2, 0x30500674) +T714C 003:116.971 - 0.016ms returns 0 +T714C 003:116.988 JLINK_WriteReg(R3, 0x00000000) +T714C 003:117.004 - 0.016ms returns 0 +T714C 003:117.020 JLINK_WriteReg(R4, 0x00000000) +T714C 003:117.040 - 0.019ms returns 0 +T714C 003:117.056 JLINK_WriteReg(R5, 0x00000000) +T714C 003:117.072 - 0.015ms returns 0 +T714C 003:117.088 JLINK_WriteReg(R6, 0x00000000) +T714C 003:117.104 - 0.016ms returns 0 +T714C 003:117.120 JLINK_WriteReg(R7, 0x00000000) +T714C 003:117.136 - 0.016ms returns 0 +T714C 003:117.152 JLINK_WriteReg(R8, 0x00000000) +T714C 003:117.168 - 0.015ms returns 0 +T714C 003:117.185 JLINK_WriteReg(R9, 0x30500458) +T714C 003:117.200 - 0.015ms returns 0 +T714C 003:117.217 JLINK_WriteReg(R10, 0x00000000) +T714C 003:117.233 - 0.015ms returns 0 +T714C 003:117.249 JLINK_WriteReg(R11, 0x00000000) +T714C 003:117.265 - 0.015ms returns 0 +T714C 003:117.281 JLINK_WriteReg(R12, 0x00000000) +T714C 003:117.297 - 0.015ms returns 0 +T714C 003:117.313 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:117.330 - 0.017ms returns 0 +T714C 003:117.346 JLINK_WriteReg(R14, 0x30500001) +T714C 003:117.362 - 0.015ms returns 0 +T714C 003:117.378 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:117.394 - 0.015ms returns 0 +T714C 003:117.410 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:117.426 - 0.016ms returns 0 +T714C 003:117.448 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:117.464 - 0.016ms returns 0 +T714C 003:117.482 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:117.498 - 0.016ms returns 0 +T714C 003:117.514 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:117.531 - 0.016ms returns 0 +T714C 003:117.548 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:117.564 - 0.016ms returns 0x000000CB +T714C 003:117.580 JLINK_Go() +T714C 003:117.598 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:117.854 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:119.905 - 2.323ms +T714C 003:119.978 JLINK_IsHalted() +T714C 003:120.306 - 0.327ms returns FALSE +T714C 003:120.366 JLINK_HasError() +T714C 003:121.813 JLINK_IsHalted() +T714C 003:124.106 - 2.291ms returns TRUE +T714C 003:124.166 JLINK_ReadReg(R15 (PC)) +T714C 003:124.189 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:124.444 - 0.278ms returns 0x30500000 +T714C 003:124.468 JLINK_ClrBPEx(BPHandle = 0x000000CB) +T714C 003:124.484 - 0.016ms returns 0x00 +T714C 003:124.501 JLINK_ReadReg(R0) +T714C 003:124.518 - 0.017ms returns 0x00000000 +T714C 003:125.121 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:125.157 Data: 74 65 6D 6F 62 6A 65 63 74 28 26 74 69 6D 65 72 ... +T714C 003:125.188 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:126.166 - 1.044ms returns 0x100 +T714C 003:126.199 JLINK_HasError() +T714C 003:126.218 JLINK_WriteReg(R0, 0x28014D00) +T714C 003:126.238 - 0.019ms returns 0 +T714C 003:126.254 JLINK_WriteReg(R1, 0x00000100) +T714C 003:126.270 - 0.016ms returns 0 +T714C 003:126.322 JLINK_WriteReg(R2, 0x30500674) +T714C 003:126.338 - 0.016ms returns 0 +T714C 003:126.354 JLINK_WriteReg(R3, 0x00000000) +T714C 003:126.370 - 0.016ms returns 0 +T714C 003:126.387 JLINK_WriteReg(R4, 0x00000000) +T714C 003:126.402 - 0.015ms returns 0 +T714C 003:126.419 JLINK_WriteReg(R5, 0x00000000) +T714C 003:126.435 - 0.015ms returns 0 +T714C 003:126.451 JLINK_WriteReg(R6, 0x00000000) +T714C 003:126.468 - 0.017ms returns 0 +T714C 003:126.484 JLINK_WriteReg(R7, 0x00000000) +T714C 003:126.500 - 0.015ms returns 0 +T714C 003:126.516 JLINK_WriteReg(R8, 0x00000000) +T714C 003:126.532 - 0.015ms returns 0 +T714C 003:126.548 JLINK_WriteReg(R9, 0x30500458) +T714C 003:126.564 - 0.016ms returns 0 +T714C 003:126.580 JLINK_WriteReg(R10, 0x00000000) +T714C 003:126.596 - 0.016ms returns 0 +T714C 003:126.613 JLINK_WriteReg(R11, 0x00000000) +T714C 003:126.629 - 0.016ms returns 0 +T714C 003:126.645 JLINK_WriteReg(R12, 0x00000000) +T714C 003:126.662 - 0.017ms returns 0 +T714C 003:126.679 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:126.696 - 0.016ms returns 0 +T714C 003:126.712 JLINK_WriteReg(R14, 0x30500001) +T714C 003:126.727 - 0.015ms returns 0 +T714C 003:126.744 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:126.759 - 0.016ms returns 0 +T714C 003:126.776 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:126.791 - 0.015ms returns 0 +T714C 003:126.807 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:126.823 - 0.015ms returns 0 +T714C 003:126.840 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:126.856 - 0.016ms returns 0 +T714C 003:126.872 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:126.888 - 0.015ms returns 0 +T714C 003:126.905 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:126.921 - 0.016ms returns 0x000000CC +T714C 003:126.937 JLINK_Go() +T714C 003:126.956 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:127.195 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:129.044 - 2.106ms +T714C 003:129.076 JLINK_IsHalted() +T714C 003:129.332 - 0.256ms returns FALSE +T714C 003:129.354 JLINK_HasError() +T714C 003:131.382 JLINK_IsHalted() +T714C 003:133.524 - 2.141ms returns TRUE +T714C 003:133.628 JLINK_ReadReg(R15 (PC)) +T714C 003:133.659 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:134.011 - 0.382ms returns 0x30500000 +T714C 003:134.063 JLINK_ClrBPEx(BPHandle = 0x000000CC) +T714C 003:134.081 - 0.018ms returns 0x00 +T714C 003:134.100 JLINK_ReadReg(R0) +T714C 003:134.119 - 0.019ms returns 0x00000000 +T714C 003:135.573 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:135.624 Data: 00 00 FF F7 47 F9 26 46 56 F8 18 1F 80 46 72 68 ... +T714C 003:135.668 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:136.635 - 1.062ms returns 0x100 +T714C 003:136.666 JLINK_HasError() +T714C 003:136.685 JLINK_WriteReg(R0, 0x28014E00) +T714C 003:136.705 - 0.019ms returns 0 +T714C 003:136.722 JLINK_WriteReg(R1, 0x00000100) +T714C 003:136.738 - 0.016ms returns 0 +T714C 003:136.755 JLINK_WriteReg(R2, 0x30500674) +T714C 003:136.771 - 0.016ms returns 0 +T714C 003:136.788 JLINK_WriteReg(R3, 0x00000000) +T714C 003:136.804 - 0.016ms returns 0 +T714C 003:136.820 JLINK_WriteReg(R4, 0x00000000) +T714C 003:136.836 - 0.016ms returns 0 +T714C 003:136.853 JLINK_WriteReg(R5, 0x00000000) +T714C 003:136.869 - 0.016ms returns 0 +T714C 003:136.898 JLINK_WriteReg(R6, 0x00000000) +T714C 003:136.915 - 0.017ms returns 0 +T714C 003:136.933 JLINK_WriteReg(R7, 0x00000000) +T714C 003:136.952 - 0.019ms returns 0 +T714C 003:136.970 JLINK_WriteReg(R8, 0x00000000) +T714C 003:136.988 - 0.018ms returns 0 +T714C 003:137.005 JLINK_WriteReg(R9, 0x30500458) +T714C 003:137.022 - 0.017ms returns 0 +T714C 003:137.040 JLINK_WriteReg(R10, 0x00000000) +T714C 003:137.056 - 0.016ms returns 0 +T714C 003:137.073 JLINK_WriteReg(R11, 0x00000000) +T714C 003:137.089 - 0.016ms returns 0 +T714C 003:137.105 JLINK_WriteReg(R12, 0x00000000) +T714C 003:137.121 - 0.015ms returns 0 +T714C 003:137.137 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:137.154 - 0.017ms returns 0 +T714C 003:137.170 JLINK_WriteReg(R14, 0x30500001) +T714C 003:137.187 - 0.016ms returns 0 +T714C 003:137.203 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:137.219 - 0.016ms returns 0 +T714C 003:137.236 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:137.252 - 0.016ms returns 0 +T714C 003:137.268 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:137.284 - 0.015ms returns 0 +T714C 003:137.300 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:137.316 - 0.015ms returns 0 +T714C 003:137.332 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:137.348 - 0.015ms returns 0 +T714C 003:137.365 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:137.382 - 0.017ms returns 0x000000CD +T714C 003:137.398 JLINK_Go() +T714C 003:137.418 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:137.723 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:139.727 - 2.328ms +T714C 003:139.771 JLINK_IsHalted() +T714C 003:140.002 - 0.230ms returns FALSE +T714C 003:140.023 JLINK_HasError() +T714C 003:141.187 JLINK_IsHalted() +T714C 003:143.243 - 2.055ms returns TRUE +T714C 003:143.271 JLINK_ReadReg(R15 (PC)) +T714C 003:143.289 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:143.556 - 0.285ms returns 0x30500000 +T714C 003:143.576 JLINK_ClrBPEx(BPHandle = 0x000000CD) +T714C 003:143.593 - 0.016ms returns 0x00 +T714C 003:143.610 JLINK_ReadReg(R0) +T714C 003:143.627 - 0.016ms returns 0x00000000 +T714C 003:144.175 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:144.212 Data: FF F7 1C FD 40 F2 04 35 A1 6A C2 F2 00 05 6A 68 ... +T714C 003:144.243 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:145.268 - 1.092ms returns 0x100 +T714C 003:145.310 JLINK_HasError() +T714C 003:145.329 JLINK_WriteReg(R0, 0x28014F00) +T714C 003:145.349 - 0.019ms returns 0 +T714C 003:145.365 JLINK_WriteReg(R1, 0x00000100) +T714C 003:145.381 - 0.015ms returns 0 +T714C 003:145.401 JLINK_WriteReg(R2, 0x30500674) +T714C 003:145.417 - 0.016ms returns 0 +T714C 003:145.433 JLINK_WriteReg(R3, 0x00000000) +T714C 003:145.449 - 0.015ms returns 0 +T714C 003:145.465 JLINK_WriteReg(R4, 0x00000000) +T714C 003:145.481 - 0.016ms returns 0 +T714C 003:145.498 JLINK_WriteReg(R5, 0x00000000) +T714C 003:145.513 - 0.015ms returns 0 +T714C 003:145.530 JLINK_WriteReg(R6, 0x00000000) +T714C 003:145.546 - 0.016ms returns 0 +T714C 003:145.562 JLINK_WriteReg(R7, 0x00000000) +T714C 003:145.578 - 0.015ms returns 0 +T714C 003:145.594 JLINK_WriteReg(R8, 0x00000000) +T714C 003:145.610 - 0.016ms returns 0 +T714C 003:145.627 JLINK_WriteReg(R9, 0x30500458) +T714C 003:145.643 - 0.015ms returns 0 +T714C 003:145.659 JLINK_WriteReg(R10, 0x00000000) +T714C 003:145.675 - 0.015ms returns 0 +T714C 003:145.691 JLINK_WriteReg(R11, 0x00000000) +T714C 003:145.712 - 0.021ms returns 0 +T714C 003:145.730 JLINK_WriteReg(R12, 0x00000000) +T714C 003:145.746 - 0.016ms returns 0 +T714C 003:145.763 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:145.781 - 0.018ms returns 0 +T714C 003:145.797 JLINK_WriteReg(R14, 0x30500001) +T714C 003:145.813 - 0.016ms returns 0 +T714C 003:145.830 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:145.846 - 0.016ms returns 0 +T714C 003:145.863 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:145.878 - 0.015ms returns 0 +T714C 003:145.895 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:145.910 - 0.015ms returns 0 +T714C 003:145.926 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:145.942 - 0.015ms returns 0 +T714C 003:145.958 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:145.974 - 0.016ms returns 0 +T714C 003:145.991 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:146.008 - 0.017ms returns 0x000000CE +T714C 003:146.024 JLINK_Go() +T714C 003:146.042 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:146.343 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:148.240 - 2.214ms +T714C 003:149.007 JLINK_IsHalted() +T714C 003:151.218 - 2.210ms returns TRUE +T714C 003:151.272 JLINK_ReadReg(R15 (PC)) +T714C 003:151.296 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:151.608 - 0.335ms returns 0x30500000 +T714C 003:151.638 JLINK_ClrBPEx(BPHandle = 0x000000CE) +T714C 003:151.656 - 0.018ms returns 0x00 +T714C 003:151.673 JLINK_ReadReg(R0) +T714C 003:151.690 - 0.017ms returns 0x00000000 +T714C 003:152.344 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:152.383 Data: 6F F0 FE 04 17 E0 41 F2 F8 40 C2 F2 00 00 01 68 ... +T714C 003:152.415 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:153.363 - 1.019ms returns 0x100 +T714C 003:153.388 JLINK_HasError() +T714C 003:153.405 JLINK_WriteReg(R0, 0x28015000) +T714C 003:153.424 - 0.018ms returns 0 +T714C 003:153.440 JLINK_WriteReg(R1, 0x00000100) +T714C 003:153.456 - 0.016ms returns 0 +T714C 003:153.472 JLINK_WriteReg(R2, 0x30500674) +T714C 003:153.489 - 0.016ms returns 0 +T714C 003:153.505 JLINK_WriteReg(R3, 0x00000000) +T714C 003:153.521 - 0.016ms returns 0 +T714C 003:153.538 JLINK_WriteReg(R4, 0x00000000) +T714C 003:153.554 - 0.015ms returns 0 +T714C 003:153.569 JLINK_WriteReg(R5, 0x00000000) +T714C 003:153.585 - 0.016ms returns 0 +T714C 003:153.632 JLINK_WriteReg(R6, 0x00000000) +T714C 003:153.648 - 0.015ms returns 0 +T714C 003:153.664 JLINK_WriteReg(R7, 0x00000000) +T714C 003:153.680 - 0.016ms returns 0 +T714C 003:153.696 JLINK_WriteReg(R8, 0x00000000) +T714C 003:153.712 - 0.015ms returns 0 +T714C 003:153.728 JLINK_WriteReg(R9, 0x30500458) +T714C 003:153.744 - 0.016ms returns 0 +T714C 003:153.761 JLINK_WriteReg(R10, 0x00000000) +T714C 003:153.777 - 0.015ms returns 0 +T714C 003:153.793 JLINK_WriteReg(R11, 0x00000000) +T714C 003:153.810 - 0.017ms returns 0 +T714C 003:153.827 JLINK_WriteReg(R12, 0x00000000) +T714C 003:153.843 - 0.016ms returns 0 +T714C 003:153.861 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:153.878 - 0.017ms returns 0 +T714C 003:153.894 JLINK_WriteReg(R14, 0x30500001) +T714C 003:153.910 - 0.015ms returns 0 +T714C 003:153.926 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:153.942 - 0.016ms returns 0 +T714C 003:153.959 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:153.975 - 0.016ms returns 0 +T714C 003:153.991 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:154.007 - 0.015ms returns 0 +T714C 003:154.023 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:154.039 - 0.016ms returns 0 +T714C 003:154.056 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:154.072 - 0.015ms returns 0 +T714C 003:154.088 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:154.105 - 0.016ms returns 0x000000CF +T714C 003:154.121 JLINK_Go() +T714C 003:154.138 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:154.457 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:156.461 - 2.338ms +T714C 003:156.505 JLINK_IsHalted() +T714C 003:156.740 - 0.235ms returns FALSE +T714C 003:156.765 JLINK_HasError() +T714C 003:159.302 JLINK_IsHalted() +T714C 003:161.477 - 2.174ms returns TRUE +T714C 003:161.503 JLINK_ReadReg(R15 (PC)) +T714C 003:161.527 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:161.786 - 0.283ms returns 0x30500000 +T714C 003:161.808 JLINK_ClrBPEx(BPHandle = 0x000000CF) +T714C 003:161.825 - 0.017ms returns 0x00 +T714C 003:161.842 JLINK_ReadReg(R0) +T714C 003:161.858 - 0.016ms returns 0x00000000 +T714C 003:162.384 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:162.416 Data: 2A 2B 09 D1 5A F8 04 1B 01 34 B1 F1 FF 3F DC BF ... +T714C 003:162.447 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:163.379 - 0.994ms returns 0x100 +T714C 003:163.409 JLINK_HasError() +T714C 003:163.430 JLINK_WriteReg(R0, 0x28015100) +T714C 003:163.452 - 0.022ms returns 0 +T714C 003:163.476 JLINK_WriteReg(R1, 0x00000100) +T714C 003:163.503 - 0.027ms returns 0 +T714C 003:163.528 JLINK_WriteReg(R2, 0x30500674) +T714C 003:163.556 - 0.027ms returns 0 +T714C 003:163.580 JLINK_WriteReg(R3, 0x00000000) +T714C 003:163.608 - 0.027ms returns 0 +T714C 003:163.634 JLINK_WriteReg(R4, 0x00000000) +T714C 003:163.654 - 0.020ms returns 0 +T714C 003:163.673 JLINK_WriteReg(R5, 0x00000000) +T714C 003:163.692 - 0.019ms returns 0 +T714C 003:163.716 JLINK_WriteReg(R6, 0x00000000) +T714C 003:163.736 - 0.019ms returns 0 +T714C 003:163.758 JLINK_WriteReg(R7, 0x00000000) +T714C 003:163.776 - 0.018ms returns 0 +T714C 003:163.795 JLINK_WriteReg(R8, 0x00000000) +T714C 003:163.813 - 0.018ms returns 0 +T714C 003:163.832 JLINK_WriteReg(R9, 0x30500458) +T714C 003:163.850 - 0.017ms returns 0 +T714C 003:163.869 JLINK_WriteReg(R10, 0x00000000) +T714C 003:163.886 - 0.017ms returns 0 +T714C 003:163.902 JLINK_WriteReg(R11, 0x00000000) +T714C 003:163.918 - 0.016ms returns 0 +T714C 003:163.935 JLINK_WriteReg(R12, 0x00000000) +T714C 003:163.951 - 0.016ms returns 0 +T714C 003:163.968 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:163.986 - 0.018ms returns 0 +T714C 003:164.003 JLINK_WriteReg(R14, 0x30500001) +T714C 003:164.019 - 0.016ms returns 0 +T714C 003:164.036 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:164.052 - 0.016ms returns 0 +T714C 003:164.070 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:164.088 - 0.017ms returns 0 +T714C 003:164.104 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:164.121 - 0.016ms returns 0 +T714C 003:164.137 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:164.153 - 0.015ms returns 0 +T714C 003:164.170 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:164.186 - 0.016ms returns 0 +T714C 003:164.203 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:164.220 - 0.018ms returns 0x000000D0 +T714C 003:164.237 JLINK_Go() +T714C 003:164.255 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:164.586 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:166.549 - 2.312ms +T714C 003:166.616 JLINK_IsHalted() +T714C 003:166.837 - 0.220ms returns FALSE +T714C 003:166.859 JLINK_HasError() +T714C 003:168.131 JLINK_IsHalted() +T714C 003:170.220 - 2.089ms returns TRUE +T714C 003:170.249 JLINK_ReadReg(R15 (PC)) +T714C 003:170.269 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:170.549 - 0.299ms returns 0x30500000 +T714C 003:170.570 JLINK_ClrBPEx(BPHandle = 0x000000D0) +T714C 003:170.588 - 0.017ms returns 0x00 +T714C 003:170.605 JLINK_ReadReg(R0) +T714C 003:170.621 - 0.016ms returns 0x00000000 +T714C 003:171.238 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:171.275 Data: 5A 00 5A 00 5A 00 5A 00 5A 00 5A 00 5A 00 8E 00 ... +T714C 003:171.306 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:172.299 - 1.061ms returns 0x100 +T714C 003:172.333 JLINK_HasError() +T714C 003:172.352 JLINK_WriteReg(R0, 0x28015200) +T714C 003:172.371 - 0.019ms returns 0 +T714C 003:172.388 JLINK_WriteReg(R1, 0x00000100) +T714C 003:172.409 - 0.021ms returns 0 +T714C 003:172.425 JLINK_WriteReg(R2, 0x30500674) +T714C 003:172.441 - 0.016ms returns 0 +T714C 003:172.457 JLINK_WriteReg(R3, 0x00000000) +T714C 003:172.473 - 0.015ms returns 0 +T714C 003:172.489 JLINK_WriteReg(R4, 0x00000000) +T714C 003:172.505 - 0.015ms returns 0 +T714C 003:172.521 JLINK_WriteReg(R5, 0x00000000) +T714C 003:172.537 - 0.015ms returns 0 +T714C 003:172.553 JLINK_WriteReg(R6, 0x00000000) +T714C 003:172.568 - 0.015ms returns 0 +T714C 003:172.584 JLINK_WriteReg(R7, 0x00000000) +T714C 003:172.609 - 0.024ms returns 0 +T714C 003:172.626 JLINK_WriteReg(R8, 0x00000000) +T714C 003:172.642 - 0.016ms returns 0 +T714C 003:172.658 JLINK_WriteReg(R9, 0x30500458) +T714C 003:172.675 - 0.016ms returns 0 +T714C 003:172.691 JLINK_WriteReg(R10, 0x00000000) +T714C 003:172.707 - 0.015ms returns 0 +T714C 003:172.723 JLINK_WriteReg(R11, 0x00000000) +T714C 003:172.738 - 0.015ms returns 0 +T714C 003:172.755 JLINK_WriteReg(R12, 0x00000000) +T714C 003:172.771 - 0.016ms returns 0 +T714C 003:172.787 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:172.804 - 0.017ms returns 0 +T714C 003:172.820 JLINK_WriteReg(R14, 0x30500001) +T714C 003:172.836 - 0.016ms returns 0 +T714C 003:172.852 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:172.869 - 0.017ms returns 0 +T714C 003:172.885 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:172.901 - 0.016ms returns 0 +T714C 003:172.917 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:172.933 - 0.015ms returns 0 +T714C 003:172.949 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:172.964 - 0.015ms returns 0 +T714C 003:172.980 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:172.996 - 0.015ms returns 0 +T714C 003:173.013 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:173.030 - 0.016ms returns 0x000000D1 +T714C 003:173.046 JLINK_Go() +T714C 003:173.063 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:173.342 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:175.236 - 2.190ms +T714C 003:175.272 JLINK_IsHalted() +T714C 003:175.562 - 0.290ms returns FALSE +T714C 003:175.589 JLINK_HasError() +T714C 003:177.191 JLINK_IsHalted() +T714C 003:179.378 - 2.186ms returns TRUE +T714C 003:179.441 JLINK_ReadReg(R15 (PC)) +T714C 003:179.461 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:179.740 - 0.298ms returns 0x30500000 +T714C 003:179.774 JLINK_ClrBPEx(BPHandle = 0x000000D1) +T714C 003:179.792 - 0.018ms returns 0x00 +T714C 003:179.809 JLINK_ReadReg(R0) +T714C 003:179.826 - 0.017ms returns 0x00000000 +T714C 003:180.386 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:180.424 Data: 80 F2 60 80 58 45 38 BF 80 F8 00 80 01 39 8D 42 ... +T714C 003:180.455 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:181.424 - 1.038ms returns 0x100 +T714C 003:181.449 JLINK_HasError() +T714C 003:181.466 JLINK_WriteReg(R0, 0x28015300) +T714C 003:181.484 - 0.018ms returns 0 +T714C 003:181.501 JLINK_WriteReg(R1, 0x00000100) +T714C 003:181.517 - 0.016ms returns 0 +T714C 003:181.534 JLINK_WriteReg(R2, 0x30500674) +T714C 003:181.550 - 0.016ms returns 0 +T714C 003:181.566 JLINK_WriteReg(R3, 0x00000000) +T714C 003:181.619 - 0.053ms returns 0 +T714C 003:181.635 JLINK_WriteReg(R4, 0x00000000) +T714C 003:181.651 - 0.015ms returns 0 +T714C 003:181.668 JLINK_WriteReg(R5, 0x00000000) +T714C 003:181.684 - 0.016ms returns 0 +T714C 003:181.700 JLINK_WriteReg(R6, 0x00000000) +T714C 003:181.716 - 0.016ms returns 0 +T714C 003:181.732 JLINK_WriteReg(R7, 0x00000000) +T714C 003:181.748 - 0.015ms returns 0 +T714C 003:181.764 JLINK_WriteReg(R8, 0x00000000) +T714C 003:181.780 - 0.015ms returns 0 +T714C 003:181.796 JLINK_WriteReg(R9, 0x30500458) +T714C 003:181.812 - 0.015ms returns 0 +T714C 003:181.828 JLINK_WriteReg(R10, 0x00000000) +T714C 003:181.844 - 0.016ms returns 0 +T714C 003:181.860 JLINK_WriteReg(R11, 0x00000000) +T714C 003:181.878 - 0.017ms returns 0 +T714C 003:181.894 JLINK_WriteReg(R12, 0x00000000) +T714C 003:181.910 - 0.015ms returns 0 +T714C 003:181.926 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:181.944 - 0.017ms returns 0 +T714C 003:181.960 JLINK_WriteReg(R14, 0x30500001) +T714C 003:181.976 - 0.016ms returns 0 +T714C 003:181.993 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:182.009 - 0.016ms returns 0 +T714C 003:182.025 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:182.042 - 0.016ms returns 0 +T714C 003:182.058 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:182.074 - 0.016ms returns 0 +T714C 003:182.090 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:182.106 - 0.016ms returns 0 +T714C 003:182.122 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:182.138 - 0.016ms returns 0 +T714C 003:182.155 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:182.178 - 0.022ms returns 0x000000D2 +T714C 003:182.198 JLINK_Go() +T714C 003:182.216 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:182.516 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:184.582 - 2.384ms +T714C 003:184.626 JLINK_IsHalted() +T714C 003:184.814 - 0.187ms returns FALSE +T714C 003:184.834 JLINK_HasError() +T714C 003:186.142 JLINK_IsHalted() +T714C 003:188.391 - 2.247ms returns TRUE +T714C 003:188.414 JLINK_ReadReg(R15 (PC)) +T714C 003:188.433 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:188.675 - 0.261ms returns 0x30500000 +T714C 003:188.695 JLINK_ClrBPEx(BPHandle = 0x000000D2) +T714C 003:188.712 - 0.017ms returns 0x00 +T714C 003:188.729 JLINK_ReadReg(R0) +T714C 003:188.745 - 0.016ms returns 0x00000000 +T714C 003:189.306 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:189.340 Data: D9 43 31 B1 01 46 00 22 58 45 28 BF AB F1 01 01 ... +T714C 003:189.370 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:190.407 - 1.100ms returns 0x100 +T714C 003:190.431 JLINK_HasError() +T714C 003:190.448 JLINK_WriteReg(R0, 0x28015400) +T714C 003:190.466 - 0.017ms returns 0 +T714C 003:190.482 JLINK_WriteReg(R1, 0x00000100) +T714C 003:190.498 - 0.015ms returns 0 +T714C 003:190.515 JLINK_WriteReg(R2, 0x30500674) +T714C 003:190.531 - 0.016ms returns 0 +T714C 003:190.547 JLINK_WriteReg(R3, 0x00000000) +T714C 003:190.563 - 0.015ms returns 0 +T714C 003:190.579 JLINK_WriteReg(R4, 0x00000000) +T714C 003:190.596 - 0.016ms returns 0 +T714C 003:190.612 JLINK_WriteReg(R5, 0x00000000) +T714C 003:190.629 - 0.017ms returns 0 +T714C 003:190.646 JLINK_WriteReg(R6, 0x00000000) +T714C 003:190.662 - 0.016ms returns 0 +T714C 003:190.678 JLINK_WriteReg(R7, 0x00000000) +T714C 003:190.693 - 0.015ms returns 0 +T714C 003:190.709 JLINK_WriteReg(R8, 0x00000000) +T714C 003:190.725 - 0.016ms returns 0 +T714C 003:190.741 JLINK_WriteReg(R9, 0x30500458) +T714C 003:190.757 - 0.015ms returns 0 +T714C 003:190.773 JLINK_WriteReg(R10, 0x00000000) +T714C 003:190.789 - 0.016ms returns 0 +T714C 003:190.806 JLINK_WriteReg(R11, 0x00000000) +T714C 003:190.821 - 0.015ms returns 0 +T714C 003:190.838 JLINK_WriteReg(R12, 0x00000000) +T714C 003:190.853 - 0.015ms returns 0 +T714C 003:190.870 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:190.886 - 0.016ms returns 0 +T714C 003:190.902 JLINK_WriteReg(R14, 0x30500001) +T714C 003:190.918 - 0.015ms returns 0 +T714C 003:190.934 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:190.950 - 0.015ms returns 0 +T714C 003:190.966 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:190.982 - 0.015ms returns 0 +T714C 003:190.999 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:191.015 - 0.016ms returns 0 +T714C 003:191.031 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:191.047 - 0.015ms returns 0 +T714C 003:191.063 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:191.079 - 0.016ms returns 0 +T714C 003:191.096 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:191.112 - 0.016ms returns 0x000000D3 +T714C 003:191.128 JLINK_Go() +T714C 003:191.145 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:191.415 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:193.318 - 2.190ms +T714C 003:193.416 JLINK_IsHalted() +T714C 003:193.659 - 0.242ms returns FALSE +T714C 003:193.703 JLINK_HasError() +T714C 003:195.446 JLINK_IsHalted() +T714C 003:197.835 - 2.389ms returns TRUE +T714C 003:197.893 JLINK_ReadReg(R15 (PC)) +T714C 003:197.914 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:198.158 - 0.265ms returns 0x30500000 +T714C 003:198.180 JLINK_ClrBPEx(BPHandle = 0x000000D3) +T714C 003:198.197 - 0.016ms returns 0x00 +T714C 003:198.214 JLINK_ReadReg(R0) +T714C 003:198.231 - 0.017ms returns 0x00000000 +T714C 003:198.818 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:198.853 Data: 01 FF 00 20 02 B0 10 BD 5B 73 74 61 72 74 75 70 ... +T714C 003:198.886 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:199.858 - 1.039ms returns 0x100 +T714C 003:199.906 JLINK_HasError() +T714C 003:199.928 JLINK_WriteReg(R0, 0x28015500) +T714C 003:199.948 - 0.020ms returns 0 +T714C 003:199.964 JLINK_WriteReg(R1, 0x00000100) +T714C 003:199.981 - 0.017ms returns 0 +T714C 003:200.008 JLINK_WriteReg(R2, 0x30500674) +T714C 003:200.024 - 0.016ms returns 0 +T714C 003:200.040 JLINK_WriteReg(R3, 0x00000000) +T714C 003:200.056 - 0.016ms returns 0 +T714C 003:200.073 JLINK_WriteReg(R4, 0x00000000) +T714C 003:200.089 - 0.016ms returns 0 +T714C 003:200.105 JLINK_WriteReg(R5, 0x00000000) +T714C 003:200.121 - 0.015ms returns 0 +T714C 003:200.137 JLINK_WriteReg(R6, 0x00000000) +T714C 003:200.153 - 0.015ms returns 0 +T714C 003:200.170 JLINK_WriteReg(R7, 0x00000000) +T714C 003:200.186 - 0.016ms returns 0 +T714C 003:200.202 JLINK_WriteReg(R8, 0x00000000) +T714C 003:200.218 - 0.015ms returns 0 +T714C 003:200.235 JLINK_WriteReg(R9, 0x30500458) +T714C 003:200.251 - 0.015ms returns 0 +T714C 003:200.267 JLINK_WriteReg(R10, 0x00000000) +T714C 003:200.283 - 0.015ms returns 0 +T714C 003:200.299 JLINK_WriteReg(R11, 0x00000000) +T714C 003:200.315 - 0.016ms returns 0 +T714C 003:200.331 JLINK_WriteReg(R12, 0x00000000) +T714C 003:200.347 - 0.015ms returns 0 +T714C 003:200.363 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:200.380 - 0.017ms returns 0 +T714C 003:200.396 JLINK_WriteReg(R14, 0x30500001) +T714C 003:200.413 - 0.016ms returns 0 +T714C 003:200.429 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:200.444 - 0.015ms returns 0 +T714C 003:200.461 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:200.476 - 0.015ms returns 0 +T714C 003:200.492 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:200.508 - 0.015ms returns 0 +T714C 003:200.524 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:200.540 - 0.015ms returns 0 +T714C 003:200.556 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:200.572 - 0.015ms returns 0 +T714C 003:200.590 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:200.606 - 0.016ms returns 0x000000D4 +T714C 003:200.622 JLINK_Go() +T714C 003:200.641 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:200.910 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:202.856 - 2.233ms +T714C 003:203.463 JLINK_IsHalted() +T714C 003:205.636 - 2.172ms returns TRUE +T714C 003:205.658 JLINK_ReadReg(R15 (PC)) +T714C 003:205.675 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:205.904 - 0.246ms returns 0x30500000 +T714C 003:205.942 JLINK_ClrBPEx(BPHandle = 0x000000D4) +T714C 003:205.958 - 0.016ms returns 0x00 +T714C 003:205.975 JLINK_ReadReg(R0) +T714C 003:205.994 - 0.018ms returns 0x00000000 +T714C 003:206.576 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:206.615 Data: 20 20 20 20 20 20 20 20 20 02 02 02 02 02 02 02 ... +T714C 003:206.646 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:207.744 - 1.168ms returns 0x100 +T714C 003:207.769 JLINK_HasError() +T714C 003:207.786 JLINK_WriteReg(R0, 0x28015600) +T714C 003:207.806 - 0.018ms returns 0 +T714C 003:207.822 JLINK_WriteReg(R1, 0x00000100) +T714C 003:207.838 - 0.016ms returns 0 +T714C 003:207.854 JLINK_WriteReg(R2, 0x30500674) +T714C 003:207.870 - 0.015ms returns 0 +T714C 003:207.886 JLINK_WriteReg(R3, 0x00000000) +T714C 003:207.903 - 0.016ms returns 0 +T714C 003:207.919 JLINK_WriteReg(R4, 0x00000000) +T714C 003:207.940 - 0.021ms returns 0 +T714C 003:208.018 JLINK_WriteReg(R5, 0x00000000) +T714C 003:208.042 - 0.024ms returns 0 +T714C 003:208.065 JLINK_WriteReg(R6, 0x00000000) +T714C 003:208.083 - 0.017ms returns 0 +T714C 003:208.100 JLINK_WriteReg(R7, 0x00000000) +T714C 003:208.124 - 0.024ms returns 0 +T714C 003:208.142 JLINK_WriteReg(R8, 0x00000000) +T714C 003:208.158 - 0.016ms returns 0 +T714C 003:208.176 JLINK_WriteReg(R9, 0x30500458) +T714C 003:208.192 - 0.015ms returns 0 +T714C 003:208.209 JLINK_WriteReg(R10, 0x00000000) +T714C 003:208.225 - 0.016ms returns 0 +T714C 003:208.241 JLINK_WriteReg(R11, 0x00000000) +T714C 003:208.258 - 0.016ms returns 0 +T714C 003:208.274 JLINK_WriteReg(R12, 0x00000000) +T714C 003:208.292 - 0.016ms returns 0 +T714C 003:208.315 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:208.334 - 0.018ms returns 0 +T714C 003:208.349 JLINK_WriteReg(R14, 0x30500001) +T714C 003:208.371 - 0.021ms returns 0 +T714C 003:208.388 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:208.404 - 0.016ms returns 0 +T714C 003:208.420 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:208.444 - 0.023ms returns 0 +T714C 003:208.463 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:208.479 - 0.015ms returns 0 +T714C 003:208.495 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:208.511 - 0.015ms returns 0 +T714C 003:208.527 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:208.543 - 0.016ms returns 0 +T714C 003:208.560 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:208.577 - 0.017ms returns 0x000000D5 +T714C 003:208.595 JLINK_Go() +T714C 003:208.614 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:208.944 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:210.906 - 2.311ms +T714C 003:210.932 JLINK_IsHalted() +T714C 003:211.155 - 0.223ms returns FALSE +T714C 003:211.176 JLINK_HasError() +T714C 003:213.959 JLINK_IsHalted() +T714C 003:216.188 - 2.228ms returns TRUE +T714C 003:216.280 JLINK_ReadReg(R15 (PC)) +T714C 003:216.358 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:216.658 - 0.377ms returns 0x30500000 +T714C 003:216.690 JLINK_ClrBPEx(BPHandle = 0x000000D5) +T714C 003:216.710 - 0.019ms returns 0x00 +T714C 003:216.727 JLINK_ReadReg(R0) +T714C 003:216.745 - 0.017ms returns 0x00000000 +T714C 003:217.314 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:217.347 Data: 61 72 00 63 6C 65 61 72 20 74 68 65 20 74 65 72 ... +T714C 003:217.378 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:218.477 - 1.163ms returns 0x100 +T714C 003:218.502 JLINK_HasError() +T714C 003:218.519 JLINK_WriteReg(R0, 0x28015700) +T714C 003:218.538 - 0.018ms returns 0 +T714C 003:218.554 JLINK_WriteReg(R1, 0x00000100) +T714C 003:218.570 - 0.016ms returns 0 +T714C 003:218.586 JLINK_WriteReg(R2, 0x30500674) +T714C 003:218.602 - 0.015ms returns 0 +T714C 003:218.618 JLINK_WriteReg(R3, 0x00000000) +T714C 003:218.634 - 0.015ms returns 0 +T714C 003:218.651 JLINK_WriteReg(R4, 0x00000000) +T714C 003:218.667 - 0.015ms returns 0 +T714C 003:218.683 JLINK_WriteReg(R5, 0x00000000) +T714C 003:218.699 - 0.015ms returns 0 +T714C 003:218.715 JLINK_WriteReg(R6, 0x00000000) +T714C 003:218.731 - 0.015ms returns 0 +T714C 003:218.747 JLINK_WriteReg(R7, 0x00000000) +T714C 003:218.765 - 0.017ms returns 0 +T714C 003:218.781 JLINK_WriteReg(R8, 0x00000000) +T714C 003:218.797 - 0.016ms returns 0 +T714C 003:218.813 JLINK_WriteReg(R9, 0x30500458) +T714C 003:218.829 - 0.015ms returns 0 +T714C 003:218.845 JLINK_WriteReg(R10, 0x00000000) +T714C 003:218.861 - 0.015ms returns 0 +T714C 003:218.877 JLINK_WriteReg(R11, 0x00000000) +T714C 003:218.893 - 0.016ms returns 0 +T714C 003:218.909 JLINK_WriteReg(R12, 0x00000000) +T714C 003:218.924 - 0.015ms returns 0 +T714C 003:218.940 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:218.957 - 0.016ms returns 0 +T714C 003:218.973 JLINK_WriteReg(R14, 0x30500001) +T714C 003:218.989 - 0.015ms returns 0 +T714C 003:219.005 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:219.021 - 0.015ms returns 0 +T714C 003:219.037 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:219.053 - 0.016ms returns 0 +T714C 003:219.069 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:219.085 - 0.015ms returns 0 +T714C 003:219.101 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:219.117 - 0.016ms returns 0 +T714C 003:219.133 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:219.149 - 0.015ms returns 0 +T714C 003:219.166 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:219.182 - 0.017ms returns 0x000000D6 +T714C 003:219.199 JLINK_Go() +T714C 003:219.217 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:219.509 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:221.382 - 2.183ms +T714C 003:221.405 JLINK_IsHalted() +T714C 003:221.671 - 0.266ms returns FALSE +T714C 003:221.692 JLINK_HasError() +T714C 003:222.959 JLINK_IsHalted() +T714C 003:225.228 - 2.268ms returns TRUE +T714C 003:225.278 JLINK_ReadReg(R15 (PC)) +T714C 003:225.297 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:225.542 - 0.264ms returns 0x30500000 +T714C 003:225.563 JLINK_ClrBPEx(BPHandle = 0x000000D6) +T714C 003:225.580 - 0.016ms returns 0x00 +T714C 003:225.596 JLINK_ReadReg(R0) +T714C 003:225.613 - 0.016ms returns 0x00000000 +T714C 003:226.112 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:226.149 Data: A2 71 01 28 44 00 00 00 BA 71 01 28 06 00 00 00 ... +T714C 003:226.183 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:227.228 - 1.115ms returns 0x100 +T714C 003:227.261 JLINK_HasError() +T714C 003:227.280 JLINK_WriteReg(R0, 0x28015800) +T714C 003:227.301 - 0.020ms returns 0 +T714C 003:227.318 JLINK_WriteReg(R1, 0x00000100) +T714C 003:227.336 - 0.017ms returns 0 +T714C 003:227.353 JLINK_WriteReg(R2, 0x30500674) +T714C 003:227.370 - 0.017ms returns 0 +T714C 003:227.387 JLINK_WriteReg(R3, 0x00000000) +T714C 003:227.403 - 0.016ms returns 0 +T714C 003:227.420 JLINK_WriteReg(R4, 0x00000000) +T714C 003:227.436 - 0.017ms returns 0 +T714C 003:227.453 JLINK_WriteReg(R5, 0x00000000) +T714C 003:227.469 - 0.016ms returns 0 +T714C 003:227.486 JLINK_WriteReg(R6, 0x00000000) +T714C 003:227.502 - 0.016ms returns 0 +T714C 003:227.519 JLINK_WriteReg(R7, 0x00000000) +T714C 003:227.536 - 0.016ms returns 0 +T714C 003:227.571 JLINK_WriteReg(R8, 0x00000000) +T714C 003:227.588 - 0.017ms returns 0 +T714C 003:227.604 JLINK_WriteReg(R9, 0x30500458) +T714C 003:227.620 - 0.015ms returns 0 +T714C 003:227.636 JLINK_WriteReg(R10, 0x00000000) +T714C 003:227.653 - 0.016ms returns 0 +T714C 003:227.669 JLINK_WriteReg(R11, 0x00000000) +T714C 003:227.686 - 0.016ms returns 0 +T714C 003:227.703 JLINK_WriteReg(R12, 0x00000000) +T714C 003:227.720 - 0.016ms returns 0 +T714C 003:227.736 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:227.753 - 0.017ms returns 0 +T714C 003:227.770 JLINK_WriteReg(R14, 0x30500001) +T714C 003:227.786 - 0.016ms returns 0 +T714C 003:227.802 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:227.818 - 0.015ms returns 0 +T714C 003:227.834 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:227.850 - 0.016ms returns 0 +T714C 003:227.867 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:227.883 - 0.016ms returns 0 +T714C 003:227.900 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:227.916 - 0.016ms returns 0 +T714C 003:227.932 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:227.948 - 0.016ms returns 0 +T714C 003:227.965 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:227.982 - 0.017ms returns 0x000000D7 +T714C 003:227.998 JLINK_Go() +T714C 003:228.016 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:228.319 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:230.222 - 2.223ms +T714C 003:230.251 JLINK_IsHalted() +T714C 003:230.501 - 0.250ms returns FALSE +T714C 003:230.526 JLINK_HasError() +T714C 003:232.041 JLINK_IsHalted() +T714C 003:234.334 - 2.292ms returns TRUE +T714C 003:234.366 JLINK_ReadReg(R15 (PC)) +T714C 003:234.384 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:234.634 - 0.267ms returns 0x30500000 +T714C 003:234.655 JLINK_ClrBPEx(BPHandle = 0x000000D7) +T714C 003:234.671 - 0.016ms returns 0x00 +T714C 003:234.688 JLINK_ReadReg(R0) +T714C 003:234.705 - 0.017ms returns 0x00000000 +T714C 003:235.294 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:235.332 Data: 00 01 0A 16 00 01 0A 16 00 01 14 08 00 01 0E 0B ... +T714C 003:235.366 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:236.452 - 1.157ms returns 0x100 +T714C 003:236.474 JLINK_HasError() +T714C 003:236.491 JLINK_WriteReg(R0, 0x28015900) +T714C 003:236.509 - 0.018ms returns 0 +T714C 003:236.526 JLINK_WriteReg(R1, 0x00000100) +T714C 003:236.542 - 0.016ms returns 0 +T714C 003:236.558 JLINK_WriteReg(R2, 0x30500674) +T714C 003:236.574 - 0.016ms returns 0 +T714C 003:236.591 JLINK_WriteReg(R3, 0x00000000) +T714C 003:236.607 - 0.016ms returns 0 +T714C 003:236.624 JLINK_WriteReg(R4, 0x00000000) +T714C 003:236.669 - 0.045ms returns 0 +T714C 003:236.686 JLINK_WriteReg(R5, 0x00000000) +T714C 003:236.701 - 0.015ms returns 0 +T714C 003:236.717 JLINK_WriteReg(R6, 0x00000000) +T714C 003:236.733 - 0.015ms returns 0 +T714C 003:236.749 JLINK_WriteReg(R7, 0x00000000) +T714C 003:236.765 - 0.015ms returns 0 +T714C 003:236.781 JLINK_WriteReg(R8, 0x00000000) +T714C 003:236.797 - 0.015ms returns 0 +T714C 003:236.813 JLINK_WriteReg(R9, 0x30500458) +T714C 003:236.828 - 0.015ms returns 0 +T714C 003:236.845 JLINK_WriteReg(R10, 0x00000000) +T714C 003:236.861 - 0.015ms returns 0 +T714C 003:236.938 JLINK_WriteReg(R11, 0x00000000) +T714C 003:236.958 - 0.019ms returns 0 +T714C 003:236.974 JLINK_WriteReg(R12, 0x00000000) +T714C 003:236.990 - 0.016ms returns 0 +T714C 003:237.007 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:237.024 - 0.017ms returns 0 +T714C 003:237.041 JLINK_WriteReg(R14, 0x30500001) +T714C 003:237.057 - 0.015ms returns 0 +T714C 003:237.073 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:237.089 - 0.016ms returns 0 +T714C 003:237.110 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:237.127 - 0.017ms returns 0 +T714C 003:237.146 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:237.162 - 0.016ms returns 0 +T714C 003:237.179 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:237.195 - 0.016ms returns 0 +T714C 003:237.232 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:237.250 - 0.018ms returns 0 +T714C 003:237.271 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:237.288 - 0.017ms returns 0x000000D8 +T714C 003:237.304 JLINK_Go() +T714C 003:237.322 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:237.643 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:239.605 - 2.300ms +T714C 003:239.652 JLINK_IsHalted() +T714C 003:239.863 - 0.211ms returns FALSE +T714C 003:239.889 JLINK_HasError() +T714C 003:241.568 JLINK_IsHalted() +T714C 003:243.755 - 2.188ms returns TRUE +T714C 003:243.778 JLINK_ReadReg(R15 (PC)) +T714C 003:243.795 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:244.029 - 0.250ms returns 0x30500000 +T714C 003:244.049 JLINK_ClrBPEx(BPHandle = 0x000000D8) +T714C 003:244.066 - 0.016ms returns 0x00 +T714C 003:244.082 JLINK_ReadReg(R0) +T714C 003:244.099 - 0.016ms returns 0x00000000 +T714C 003:244.672 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:244.703 Data: 64 65 76 69 63 65 3A 25 2E 2A 73 20 66 61 69 6C ... +T714C 003:244.733 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:245.739 - 1.067ms returns 0x100 +T714C 003:245.761 JLINK_HasError() +T714C 003:245.779 JLINK_WriteReg(R0, 0x28015A00) +T714C 003:245.797 - 0.018ms returns 0 +T714C 003:245.814 JLINK_WriteReg(R1, 0x00000100) +T714C 003:245.830 - 0.016ms returns 0 +T714C 003:245.846 JLINK_WriteReg(R2, 0x30500674) +T714C 003:245.862 - 0.016ms returns 0 +T714C 003:245.879 JLINK_WriteReg(R3, 0x00000000) +T714C 003:245.894 - 0.015ms returns 0 +T714C 003:245.911 JLINK_WriteReg(R4, 0x00000000) +T714C 003:245.926 - 0.015ms returns 0 +T714C 003:245.943 JLINK_WriteReg(R5, 0x00000000) +T714C 003:245.959 - 0.015ms returns 0 +T714C 003:245.975 JLINK_WriteReg(R6, 0x00000000) +T714C 003:245.991 - 0.015ms returns 0 +T714C 003:246.007 JLINK_WriteReg(R7, 0x00000000) +T714C 003:246.023 - 0.016ms returns 0 +T714C 003:246.040 JLINK_WriteReg(R8, 0x00000000) +T714C 003:246.056 - 0.016ms returns 0 +T714C 003:246.072 JLINK_WriteReg(R9, 0x30500458) +T714C 003:246.088 - 0.016ms returns 0 +T714C 003:246.105 JLINK_WriteReg(R10, 0x00000000) +T714C 003:246.121 - 0.015ms returns 0 +T714C 003:246.137 JLINK_WriteReg(R11, 0x00000000) +T714C 003:246.153 - 0.016ms returns 0 +T714C 003:246.169 JLINK_WriteReg(R12, 0x00000000) +T714C 003:246.184 - 0.015ms returns 0 +T714C 003:246.200 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:246.217 - 0.016ms returns 0 +T714C 003:246.233 JLINK_WriteReg(R14, 0x30500001) +T714C 003:246.249 - 0.016ms returns 0 +T714C 003:246.266 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:246.281 - 0.015ms returns 0 +T714C 003:246.297 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:246.313 - 0.015ms returns 0 +T714C 003:246.329 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:246.345 - 0.015ms returns 0 +T714C 003:246.361 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:246.377 - 0.015ms returns 0 +T714C 003:246.394 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:246.410 - 0.015ms returns 0 +T714C 003:246.426 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:246.442 - 0.016ms returns 0x000000D9 +T714C 003:246.459 JLINK_Go() +T714C 003:246.476 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:246.753 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:248.692 - 2.232ms +T714C 003:248.778 JLINK_IsHalted() +T714C 003:249.128 - 0.349ms returns FALSE +T714C 003:249.255 JLINK_HasError() +T714C 003:250.563 JLINK_IsHalted() +T714C 003:253.007 - 2.443ms returns TRUE +T714C 003:253.038 JLINK_ReadReg(R15 (PC)) +T714C 003:253.057 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:253.315 - 0.277ms returns 0x30500000 +T714C 003:253.336 JLINK_ClrBPEx(BPHandle = 0x000000D9) +T714C 003:253.352 - 0.016ms returns 0x00 +T714C 003:253.370 JLINK_ReadReg(R0) +T714C 003:253.386 - 0.016ms returns 0x00000000 +T714C 003:254.918 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:255.000 Data: 64 65 76 69 63 65 5F 64 65 73 74 72 6F 79 00 46 ... +T714C 003:255.051 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:256.134 - 1.216ms returns 0x100 +T714C 003:256.195 JLINK_HasError() +T714C 003:256.214 JLINK_WriteReg(R0, 0x28015B00) +T714C 003:256.237 - 0.022ms returns 0 +T714C 003:256.257 JLINK_WriteReg(R1, 0x00000100) +T714C 003:256.273 - 0.016ms returns 0 +T714C 003:256.292 JLINK_WriteReg(R2, 0x30500674) +T714C 003:256.309 - 0.016ms returns 0 +T714C 003:256.327 JLINK_WriteReg(R3, 0x00000000) +T714C 003:256.343 - 0.016ms returns 0 +T714C 003:256.359 JLINK_WriteReg(R4, 0x00000000) +T714C 003:256.376 - 0.016ms returns 0 +T714C 003:256.392 JLINK_WriteReg(R5, 0x00000000) +T714C 003:256.408 - 0.016ms returns 0 +T714C 003:256.425 JLINK_WriteReg(R6, 0x00000000) +T714C 003:256.441 - 0.016ms returns 0 +T714C 003:256.457 JLINK_WriteReg(R7, 0x00000000) +T714C 003:256.482 - 0.024ms returns 0 +T714C 003:256.498 JLINK_WriteReg(R8, 0x00000000) +T714C 003:256.514 - 0.016ms returns 0 +T714C 003:256.530 JLINK_WriteReg(R9, 0x30500458) +T714C 003:256.546 - 0.015ms returns 0 +T714C 003:256.571 JLINK_WriteReg(R10, 0x00000000) +T714C 003:256.588 - 0.017ms returns 0 +T714C 003:256.606 JLINK_WriteReg(R11, 0x00000000) +T714C 003:256.622 - 0.015ms returns 0 +T714C 003:256.640 JLINK_WriteReg(R12, 0x00000000) +T714C 003:256.657 - 0.017ms returns 0 +T714C 003:256.673 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:256.690 - 0.017ms returns 0 +T714C 003:256.708 JLINK_WriteReg(R14, 0x30500001) +T714C 003:256.724 - 0.015ms returns 0 +T714C 003:256.742 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:256.759 - 0.017ms returns 0 +T714C 003:256.826 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:256.844 - 0.018ms returns 0 +T714C 003:256.863 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:256.880 - 0.017ms returns 0 +T714C 003:256.899 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:256.916 - 0.017ms returns 0 +T714C 003:256.934 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:256.951 - 0.017ms returns 0 +T714C 003:256.970 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:256.988 - 0.018ms returns 0x000000DA +T714C 003:257.011 JLINK_Go() +T714C 003:257.032 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:257.345 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:259.496 - 2.484ms +T714C 003:260.123 JLINK_IsHalted() +T714C 003:262.279 - 2.156ms returns TRUE +T714C 003:262.305 JLINK_ReadReg(R15 (PC)) +T714C 003:262.324 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:262.581 - 0.275ms returns 0x30500000 +T714C 003:262.604 JLINK_ClrBPEx(BPHandle = 0x000000DA) +T714C 003:262.621 - 0.016ms returns 0x00 +T714C 003:262.642 JLINK_ReadReg(R0) +T714C 003:262.658 - 0.016ms returns 0x00000000 +T714C 003:263.283 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:263.318 Data: 64 6F 77 6E 2F 6F 75 74 70 75 74 5F 6F 64 0A 00 ... +T714C 003:263.349 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:264.417 - 1.133ms returns 0x100 +T714C 003:264.445 JLINK_HasError() +T714C 003:264.463 JLINK_WriteReg(R0, 0x28015C00) +T714C 003:264.482 - 0.019ms returns 0 +T714C 003:264.498 JLINK_WriteReg(R1, 0x00000100) +T714C 003:264.514 - 0.016ms returns 0 +T714C 003:264.531 JLINK_WriteReg(R2, 0x30500674) +T714C 003:264.547 - 0.016ms returns 0 +T714C 003:264.563 JLINK_WriteReg(R3, 0x00000000) +T714C 003:264.580 - 0.017ms returns 0 +T714C 003:264.598 JLINK_WriteReg(R4, 0x00000000) +T714C 003:264.613 - 0.015ms returns 0 +T714C 003:264.630 JLINK_WriteReg(R5, 0x00000000) +T714C 003:264.646 - 0.016ms returns 0 +T714C 003:264.663 JLINK_WriteReg(R6, 0x00000000) +T714C 003:264.678 - 0.015ms returns 0 +T714C 003:264.764 JLINK_WriteReg(R7, 0x00000000) +T714C 003:264.780 - 0.016ms returns 0 +T714C 003:264.796 JLINK_WriteReg(R8, 0x00000000) +T714C 003:264.812 - 0.015ms returns 0 +T714C 003:264.828 JLINK_WriteReg(R9, 0x30500458) +T714C 003:264.844 - 0.016ms returns 0 +T714C 003:264.862 JLINK_WriteReg(R10, 0x00000000) +T714C 003:264.878 - 0.015ms returns 0 +T714C 003:264.894 JLINK_WriteReg(R11, 0x00000000) +T714C 003:264.910 - 0.016ms returns 0 +T714C 003:264.927 JLINK_WriteReg(R12, 0x00000000) +T714C 003:264.943 - 0.016ms returns 0 +T714C 003:264.960 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:264.977 - 0.017ms returns 0 +T714C 003:264.993 JLINK_WriteReg(R14, 0x30500001) +T714C 003:265.010 - 0.016ms returns 0 +T714C 003:265.026 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:265.042 - 0.016ms returns 0 +T714C 003:265.058 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:265.074 - 0.016ms returns 0 +T714C 003:265.090 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:265.106 - 0.015ms returns 0 +T714C 003:265.122 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:265.138 - 0.016ms returns 0 +T714C 003:265.155 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:265.171 - 0.016ms returns 0 +T714C 003:265.188 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:265.205 - 0.017ms returns 0x000000DB +T714C 003:265.221 JLINK_Go() +T714C 003:265.238 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:265.600 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:267.663 - 2.442ms +T714C 003:267.699 JLINK_IsHalted() +T714C 003:267.995 - 0.295ms returns FALSE +T714C 003:268.032 JLINK_HasError() +T714C 003:270.986 JLINK_IsHalted() +T714C 003:273.280 - 2.293ms returns TRUE +T714C 003:273.333 JLINK_ReadReg(R15 (PC)) +T714C 003:273.355 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:273.661 - 0.328ms returns 0x30500000 +T714C 003:273.683 JLINK_ClrBPEx(BPHandle = 0x000000DB) +T714C 003:273.700 - 0.017ms returns 0x00 +T714C 003:273.747 JLINK_ReadReg(R0) +T714C 003:273.765 - 0.017ms returns 0x00000000 +T714C 003:274.356 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:274.391 Data: 20 52 54 5F 4E 55 4C 4C 00 72 74 5F 70 69 6E 5F ... +T714C 003:274.422 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:275.506 - 1.149ms returns 0x100 +T714C 003:275.531 JLINK_HasError() +T714C 003:275.549 JLINK_WriteReg(R0, 0x28015D00) +T714C 003:275.568 - 0.018ms returns 0 +T714C 003:275.584 JLINK_WriteReg(R1, 0x00000100) +T714C 003:275.601 - 0.016ms returns 0 +T714C 003:275.618 JLINK_WriteReg(R2, 0x30500674) +T714C 003:275.635 - 0.016ms returns 0 +T714C 003:275.652 JLINK_WriteReg(R3, 0x00000000) +T714C 003:275.668 - 0.016ms returns 0 +T714C 003:275.684 JLINK_WriteReg(R4, 0x00000000) +T714C 003:275.700 - 0.016ms returns 0 +T714C 003:275.720 JLINK_WriteReg(R5, 0x00000000) +T714C 003:275.736 - 0.015ms returns 0 +T714C 003:275.752 JLINK_WriteReg(R6, 0x00000000) +T714C 003:275.768 - 0.016ms returns 0 +T714C 003:275.784 JLINK_WriteReg(R7, 0x00000000) +T714C 003:275.801 - 0.016ms returns 0 +T714C 003:275.817 JLINK_WriteReg(R8, 0x00000000) +T714C 003:275.833 - 0.015ms returns 0 +T714C 003:275.849 JLINK_WriteReg(R9, 0x30500458) +T714C 003:275.866 - 0.016ms returns 0 +T714C 003:275.882 JLINK_WriteReg(R10, 0x00000000) +T714C 003:275.898 - 0.016ms returns 0 +T714C 003:275.915 JLINK_WriteReg(R11, 0x00000000) +T714C 003:275.931 - 0.016ms returns 0 +T714C 003:275.947 JLINK_WriteReg(R12, 0x00000000) +T714C 003:275.964 - 0.016ms returns 0 +T714C 003:275.981 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:275.998 - 0.017ms returns 0 +T714C 003:276.014 JLINK_WriteReg(R14, 0x30500001) +T714C 003:276.030 - 0.015ms returns 0 +T714C 003:276.047 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:276.063 - 0.016ms returns 0 +T714C 003:276.080 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:276.096 - 0.016ms returns 0 +T714C 003:276.112 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:276.128 - 0.016ms returns 0 +T714C 003:276.145 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:276.161 - 0.016ms returns 0 +T714C 003:276.178 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:276.194 - 0.016ms returns 0 +T714C 003:276.270 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:276.290 - 0.019ms returns 0x000000DC +T714C 003:276.306 JLINK_Go() +T714C 003:276.325 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:276.615 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:278.464 - 2.157ms +T714C 003:278.503 JLINK_IsHalted() +T714C 003:278.736 - 0.233ms returns FALSE +T714C 003:278.759 JLINK_HasError() +T714C 003:280.156 JLINK_IsHalted() +T714C 003:282.333 - 2.177ms returns TRUE +T714C 003:282.371 JLINK_ReadReg(R15 (PC)) +T714C 003:282.391 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:282.712 - 0.340ms returns 0x30500000 +T714C 003:282.738 JLINK_ClrBPEx(BPHandle = 0x000000DC) +T714C 003:282.755 - 0.017ms returns 0x00 +T714C 003:282.772 JLINK_ReadReg(R0) +T714C 003:282.790 - 0.017ms returns 0x00000000 +T714C 003:283.375 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:283.411 Data: 78 00 5F 73 65 72 69 61 6C 5F 69 6E 74 5F 74 78 ... +T714C 003:283.442 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:284.447 - 1.072ms returns 0x100 +T714C 003:284.504 JLINK_HasError() +T714C 003:284.524 JLINK_WriteReg(R0, 0x28015E00) +T714C 003:284.544 - 0.021ms returns 0 +T714C 003:284.562 JLINK_WriteReg(R1, 0x00000100) +T714C 003:284.583 - 0.021ms returns 0 +T714C 003:284.600 JLINK_WriteReg(R2, 0x30500674) +T714C 003:284.617 - 0.017ms returns 0 +T714C 003:284.635 JLINK_WriteReg(R3, 0x00000000) +T714C 003:284.651 - 0.016ms returns 0 +T714C 003:284.669 JLINK_WriteReg(R4, 0x00000000) +T714C 003:284.697 - 0.027ms returns 0 +T714C 003:284.713 JLINK_WriteReg(R5, 0x00000000) +T714C 003:284.729 - 0.016ms returns 0 +T714C 003:284.746 JLINK_WriteReg(R6, 0x00000000) +T714C 003:284.762 - 0.016ms returns 0 +T714C 003:284.779 JLINK_WriteReg(R7, 0x00000000) +T714C 003:284.795 - 0.016ms returns 0 +T714C 003:284.812 JLINK_WriteReg(R8, 0x00000000) +T714C 003:284.829 - 0.017ms returns 0 +T714C 003:284.846 JLINK_WriteReg(R9, 0x30500458) +T714C 003:284.862 - 0.016ms returns 0 +T714C 003:284.878 JLINK_WriteReg(R10, 0x00000000) +T714C 003:284.895 - 0.016ms returns 0 +T714C 003:284.912 JLINK_WriteReg(R11, 0x00000000) +T714C 003:284.928 - 0.016ms returns 0 +T714C 003:284.944 JLINK_WriteReg(R12, 0x00000000) +T714C 003:284.960 - 0.015ms returns 0 +T714C 003:284.977 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:284.995 - 0.018ms returns 0 +T714C 003:285.638 JLINK_WriteReg(R14, 0x30500001) +T714C 003:285.661 - 0.023ms returns 0 +T714C 003:285.678 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:285.694 - 0.016ms returns 0 +T714C 003:285.711 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:285.727 - 0.016ms returns 0 +T714C 003:285.744 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:285.760 - 0.016ms returns 0 +T714C 003:285.777 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:285.793 - 0.016ms returns 0 +T714C 003:285.810 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:285.826 - 0.016ms returns 0 +T714C 003:285.843 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:285.860 - 0.017ms returns 0x000000DD +T714C 003:285.877 JLINK_Go() +T714C 003:285.896 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:286.161 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:288.140 - 2.262ms +T714C 003:288.222 JLINK_IsHalted() +T714C 003:288.514 - 0.292ms returns FALSE +T714C 003:288.551 JLINK_HasError() +T714C 003:290.675 JLINK_IsHalted() +T714C 003:292.872 - 2.196ms returns TRUE +T714C 003:292.896 JLINK_ReadReg(R15 (PC)) +T714C 003:292.916 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:293.158 - 0.261ms returns 0x30500000 +T714C 003:293.178 JLINK_ClrBPEx(BPHandle = 0x000000DD) +T714C 003:293.195 - 0.016ms returns 0x00 +T714C 003:293.212 JLINK_ReadReg(R0) +T714C 003:293.228 - 0.016ms returns 0x00000000 +T714C 003:293.850 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:293.887 Data: 44 65 76 69 63 65 00 4D 54 44 20 44 65 76 69 63 ... +T714C 003:293.918 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:294.996 - 1.145ms returns 0x100 +T714C 003:295.020 JLINK_HasError() +T714C 003:295.038 JLINK_WriteReg(R0, 0x28015F00) +T714C 003:295.056 - 0.018ms returns 0 +T714C 003:295.073 JLINK_WriteReg(R1, 0x00000100) +T714C 003:295.151 - 0.078ms returns 0 +T714C 003:295.168 JLINK_WriteReg(R2, 0x30500674) +T714C 003:295.184 - 0.016ms returns 0 +T714C 003:295.201 JLINK_WriteReg(R3, 0x00000000) +T714C 003:295.216 - 0.015ms returns 0 +T714C 003:295.233 JLINK_WriteReg(R4, 0x00000000) +T714C 003:295.249 - 0.015ms returns 0 +T714C 003:295.265 JLINK_WriteReg(R5, 0x00000000) +T714C 003:295.281 - 0.015ms returns 0 +T714C 003:295.298 JLINK_WriteReg(R6, 0x00000000) +T714C 003:295.315 - 0.017ms returns 0 +T714C 003:295.331 JLINK_WriteReg(R7, 0x00000000) +T714C 003:295.347 - 0.016ms returns 0 +T714C 003:295.364 JLINK_WriteReg(R8, 0x00000000) +T714C 003:295.380 - 0.015ms returns 0 +T714C 003:295.396 JLINK_WriteReg(R9, 0x30500458) +T714C 003:295.412 - 0.015ms returns 0 +T714C 003:295.428 JLINK_WriteReg(R10, 0x00000000) +T714C 003:295.444 - 0.016ms returns 0 +T714C 003:295.460 JLINK_WriteReg(R11, 0x00000000) +T714C 003:295.476 - 0.016ms returns 0 +T714C 003:295.493 JLINK_WriteReg(R12, 0x00000000) +T714C 003:295.509 - 0.016ms returns 0 +T714C 003:295.525 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:295.542 - 0.017ms returns 0 +T714C 003:295.559 JLINK_WriteReg(R14, 0x30500001) +T714C 003:295.574 - 0.015ms returns 0 +T714C 003:295.591 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:295.607 - 0.016ms returns 0 +T714C 003:295.624 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:295.640 - 0.016ms returns 0 +T714C 003:295.656 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:295.671 - 0.015ms returns 0 +T714C 003:295.688 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:295.704 - 0.015ms returns 0 +T714C 003:295.720 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:295.736 - 0.016ms returns 0 +T714C 003:295.753 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:295.769 - 0.016ms returns 0x000000DE +T714C 003:295.785 JLINK_Go() +T714C 003:295.803 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:296.090 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:297.949 - 2.163ms +T714C 003:297.973 JLINK_IsHalted() +T714C 003:298.211 - 0.238ms returns FALSE +T714C 003:298.234 JLINK_HasError() +T714C 003:299.678 JLINK_IsHalted() +T714C 003:301.998 - 2.319ms returns TRUE +T714C 003:302.046 JLINK_ReadReg(R15 (PC)) +T714C 003:302.067 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:302.314 - 0.268ms returns 0x30500000 +T714C 003:302.336 JLINK_ClrBPEx(BPHandle = 0x000000DE) +T714C 003:302.352 - 0.017ms returns 0x00 +T714C 003:302.370 JLINK_ReadReg(R0) +T714C 003:302.390 - 0.020ms returns 0x00000000 +T714C 003:302.993 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:303.029 Data: 44 65 76 69 63 65 00 50 68 79 20 44 65 76 69 63 ... +T714C 003:303.060 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:304.067 - 1.074ms returns 0x100 +T714C 003:304.091 JLINK_HasError() +T714C 003:304.109 JLINK_WriteReg(R0, 0x28016000) +T714C 003:304.128 - 0.019ms returns 0 +T714C 003:304.146 JLINK_WriteReg(R1, 0x00000100) +T714C 003:304.162 - 0.016ms returns 0 +T714C 003:304.178 JLINK_WriteReg(R2, 0x30500674) +T714C 003:304.195 - 0.016ms returns 0 +T714C 003:304.211 JLINK_WriteReg(R3, 0x00000000) +T714C 003:304.227 - 0.016ms returns 0 +T714C 003:304.244 JLINK_WriteReg(R4, 0x00000000) +T714C 003:304.260 - 0.016ms returns 0 +T714C 003:304.276 JLINK_WriteReg(R5, 0x00000000) +T714C 003:304.292 - 0.015ms returns 0 +T714C 003:304.308 JLINK_WriteReg(R6, 0x00000000) +T714C 003:304.324 - 0.015ms returns 0 +T714C 003:304.340 JLINK_WriteReg(R7, 0x00000000) +T714C 003:304.357 - 0.016ms returns 0 +T714C 003:304.373 JLINK_WriteReg(R8, 0x00000000) +T714C 003:304.389 - 0.016ms returns 0 +T714C 003:304.406 JLINK_WriteReg(R9, 0x30500458) +T714C 003:304.421 - 0.015ms returns 0 +T714C 003:304.439 JLINK_WriteReg(R10, 0x00000000) +T714C 003:304.455 - 0.015ms returns 0 +T714C 003:304.471 JLINK_WriteReg(R11, 0x00000000) +T714C 003:304.487 - 0.016ms returns 0 +T714C 003:304.504 JLINK_WriteReg(R12, 0x00000000) +T714C 003:304.519 - 0.015ms returns 0 +T714C 003:304.536 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:304.552 - 0.017ms returns 0 +T714C 003:304.568 JLINK_WriteReg(R14, 0x30500001) +T714C 003:304.584 - 0.015ms returns 0 +T714C 003:304.668 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:304.684 - 0.016ms returns 0 +T714C 003:304.726 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:304.742 - 0.016ms returns 0 +T714C 003:304.758 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:304.774 - 0.016ms returns 0 +T714C 003:304.791 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:304.807 - 0.015ms returns 0 +T714C 003:304.824 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:304.840 - 0.015ms returns 0 +T714C 003:304.857 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:304.874 - 0.017ms returns 0x000000DF +T714C 003:304.890 JLINK_Go() +T714C 003:304.907 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:305.192 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:307.138 - 2.248ms +T714C 003:307.160 JLINK_IsHalted() +T714C 003:307.377 - 0.216ms returns FALSE +T714C 003:307.396 JLINK_HasError() +T714C 003:309.111 JLINK_IsHalted() +T714C 003:311.274 - 2.162ms returns TRUE +T714C 003:311.323 JLINK_ReadReg(R15 (PC)) +T714C 003:311.343 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:311.599 - 0.276ms returns 0x30500000 +T714C 003:311.624 JLINK_ClrBPEx(BPHandle = 0x000000DF) +T714C 003:311.642 - 0.017ms returns 0x00 +T714C 003:311.661 JLINK_ReadReg(R0) +T714C 003:311.679 - 0.017ms returns 0x00000000 +T714C 003:312.314 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:312.349 Data: 42 20 48 6F 73 74 20 42 75 73 00 6C 69 73 74 20 ... +T714C 003:312.380 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:313.476 - 1.162ms returns 0x100 +T714C 003:313.498 JLINK_HasError() +T714C 003:313.516 JLINK_WriteReg(R0, 0x28016100) +T714C 003:313.533 - 0.017ms returns 0 +T714C 003:313.550 JLINK_WriteReg(R1, 0x00000100) +T714C 003:313.567 - 0.016ms returns 0 +T714C 003:313.583 JLINK_WriteReg(R2, 0x30500674) +T714C 003:313.599 - 0.016ms returns 0 +T714C 003:313.616 JLINK_WriteReg(R3, 0x00000000) +T714C 003:313.631 - 0.015ms returns 0 +T714C 003:313.647 JLINK_WriteReg(R4, 0x00000000) +T714C 003:313.665 - 0.017ms returns 0 +T714C 003:313.681 JLINK_WriteReg(R5, 0x00000000) +T714C 003:313.697 - 0.015ms returns 0 +T714C 003:313.713 JLINK_WriteReg(R6, 0x00000000) +T714C 003:313.729 - 0.016ms returns 0 +T714C 003:313.746 JLINK_WriteReg(R7, 0x00000000) +T714C 003:313.762 - 0.016ms returns 0 +T714C 003:313.778 JLINK_WriteReg(R8, 0x00000000) +T714C 003:313.794 - 0.016ms returns 0 +T714C 003:313.811 JLINK_WriteReg(R9, 0x30500458) +T714C 003:313.827 - 0.016ms returns 0 +T714C 003:313.843 JLINK_WriteReg(R10, 0x00000000) +T714C 003:313.859 - 0.016ms returns 0 +T714C 003:313.876 JLINK_WriteReg(R11, 0x00000000) +T714C 003:313.892 - 0.016ms returns 0 +T714C 003:313.908 JLINK_WriteReg(R12, 0x00000000) +T714C 003:313.923 - 0.015ms returns 0 +T714C 003:313.939 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:313.958 - 0.018ms returns 0 +T714C 003:313.974 JLINK_WriteReg(R14, 0x30500001) +T714C 003:313.990 - 0.016ms returns 0 +T714C 003:314.006 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:314.023 - 0.016ms returns 0 +T714C 003:314.039 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:314.055 - 0.016ms returns 0 +T714C 003:314.071 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:314.087 - 0.015ms returns 0 +T714C 003:314.103 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:314.119 - 0.016ms returns 0 +T714C 003:314.136 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:314.152 - 0.016ms returns 0 +T714C 003:314.169 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:314.185 - 0.016ms returns 0x000000E0 +T714C 003:314.201 JLINK_Go() +T714C 003:314.219 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:314.547 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:316.491 - 2.289ms +T714C 003:316.623 JLINK_IsHalted() +T714C 003:316.950 - 0.326ms returns FALSE +T714C 003:316.983 JLINK_HasError() +T714C 003:318.737 JLINK_IsHalted() +T714C 003:320.955 - 2.217ms returns TRUE +T714C 003:321.008 JLINK_ReadReg(R15 (PC)) +T714C 003:321.030 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:321.277 - 0.269ms returns 0x30500000 +T714C 003:321.300 JLINK_ClrBPEx(BPHandle = 0x000000E0) +T714C 003:321.318 - 0.017ms returns 0x00 +T714C 003:321.397 JLINK_ReadReg(R0) +T714C 003:321.418 - 0.021ms returns 0x00000000 +T714C 003:322.066 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:322.104 Data: 73 74 61 72 74 75 70 5D 20 42 6F 61 72 64 20 69 ... +T714C 003:322.137 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:323.113 - 1.046ms returns 0x100 +T714C 003:323.138 JLINK_HasError() +T714C 003:323.156 JLINK_WriteReg(R0, 0x28016200) +T714C 003:323.175 - 0.018ms returns 0 +T714C 003:323.192 JLINK_WriteReg(R1, 0x00000100) +T714C 003:323.213 - 0.021ms returns 0 +T714C 003:323.230 JLINK_WriteReg(R2, 0x30500674) +T714C 003:323.246 - 0.016ms returns 0 +T714C 003:323.263 JLINK_WriteReg(R3, 0x00000000) +T714C 003:323.279 - 0.016ms returns 0 +T714C 003:323.295 JLINK_WriteReg(R4, 0x00000000) +T714C 003:323.311 - 0.015ms returns 0 +T714C 003:323.327 JLINK_WriteReg(R5, 0x00000000) +T714C 003:323.343 - 0.015ms returns 0 +T714C 003:323.359 JLINK_WriteReg(R6, 0x00000000) +T714C 003:323.375 - 0.016ms returns 0 +T714C 003:323.392 JLINK_WriteReg(R7, 0x00000000) +T714C 003:323.408 - 0.016ms returns 0 +T714C 003:323.425 JLINK_WriteReg(R8, 0x00000000) +T714C 003:323.440 - 0.015ms returns 0 +T714C 003:323.459 JLINK_WriteReg(R9, 0x30500458) +T714C 003:323.475 - 0.015ms returns 0 +T714C 003:323.491 JLINK_WriteReg(R10, 0x00000000) +T714C 003:323.507 - 0.016ms returns 0 +T714C 003:323.524 JLINK_WriteReg(R11, 0x00000000) +T714C 003:323.540 - 0.016ms returns 0 +T714C 003:323.557 JLINK_WriteReg(R12, 0x00000000) +T714C 003:323.574 - 0.017ms returns 0 +T714C 003:323.590 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:323.607 - 0.017ms returns 0 +T714C 003:323.623 JLINK_WriteReg(R14, 0x30500001) +T714C 003:323.639 - 0.015ms returns 0 +T714C 003:323.655 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:323.672 - 0.016ms returns 0 +T714C 003:323.688 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:323.704 - 0.016ms returns 0 +T714C 003:323.720 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:323.736 - 0.015ms returns 0 +T714C 003:323.752 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:323.768 - 0.016ms returns 0 +T714C 003:323.785 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:323.801 - 0.015ms returns 0 +T714C 003:323.818 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:323.834 - 0.017ms returns 0x000000E1 +T714C 003:323.850 JLINK_Go() +T714C 003:323.869 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:324.126 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:325.942 - 2.091ms +T714C 003:325.990 JLINK_IsHalted() +T714C 003:326.197 - 0.207ms returns FALSE +T714C 003:326.218 JLINK_HasError() +T714C 003:327.351 JLINK_IsHalted() +T714C 003:329.455 - 2.103ms returns TRUE +T714C 003:329.481 JLINK_ReadReg(R15 (PC)) +T714C 003:329.498 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:329.695 - 0.214ms returns 0x30500000 +T714C 003:329.717 JLINK_ClrBPEx(BPHandle = 0x000000E1) +T714C 003:329.734 - 0.016ms returns 0x00 +T714C 003:329.750 JLINK_ReadReg(R0) +T714C 003:329.769 - 0.018ms returns 0x00000000 +T714C 003:330.274 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:330.308 Data: 65 20 75 73 65 64 20 62 65 66 6F 72 65 20 73 63 ... +T714C 003:330.339 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:331.476 - 1.202ms returns 0x100 +T714C 003:331.544 JLINK_HasError() +T714C 003:331.564 JLINK_WriteReg(R0, 0x28016300) +T714C 003:331.588 - 0.023ms returns 0 +T714C 003:331.605 JLINK_WriteReg(R1, 0x00000100) +T714C 003:331.622 - 0.016ms returns 0 +T714C 003:331.638 JLINK_WriteReg(R2, 0x30500674) +T714C 003:331.654 - 0.016ms returns 0 +T714C 003:331.671 JLINK_WriteReg(R3, 0x00000000) +T714C 003:331.687 - 0.016ms returns 0 +T714C 003:331.703 JLINK_WriteReg(R4, 0x00000000) +T714C 003:331.719 - 0.015ms returns 0 +T714C 003:331.737 JLINK_WriteReg(R5, 0x00000000) +T714C 003:331.754 - 0.016ms returns 0 +T714C 003:331.770 JLINK_WriteReg(R6, 0x00000000) +T714C 003:331.786 - 0.016ms returns 0 +T714C 003:331.803 JLINK_WriteReg(R7, 0x00000000) +T714C 003:331.819 - 0.016ms returns 0 +T714C 003:331.837 JLINK_WriteReg(R8, 0x00000000) +T714C 003:331.853 - 0.016ms returns 0 +T714C 003:331.869 JLINK_WriteReg(R9, 0x30500458) +T714C 003:331.944 - 0.074ms returns 0 +T714C 003:331.962 JLINK_WriteReg(R10, 0x00000000) +T714C 003:331.979 - 0.016ms returns 0 +T714C 003:331.995 JLINK_WriteReg(R11, 0x00000000) +T714C 003:332.012 - 0.016ms returns 0 +T714C 003:332.028 JLINK_WriteReg(R12, 0x00000000) +T714C 003:332.044 - 0.015ms returns 0 +T714C 003:332.060 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:332.078 - 0.017ms returns 0 +T714C 003:332.094 JLINK_WriteReg(R14, 0x30500001) +T714C 003:332.110 - 0.016ms returns 0 +T714C 003:332.127 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:332.143 - 0.016ms returns 0 +T714C 003:332.160 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:332.176 - 0.016ms returns 0 +T714C 003:332.192 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:332.209 - 0.016ms returns 0 +T714C 003:332.225 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:332.242 - 0.016ms returns 0 +T714C 003:332.258 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:332.318 - 0.060ms returns 0 +T714C 003:332.335 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:332.353 - 0.018ms returns 0x000000E2 +T714C 003:332.369 JLINK_Go() +T714C 003:332.389 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:332.707 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:334.756 - 2.386ms +T714C 003:334.792 JLINK_IsHalted() +T714C 003:335.026 - 0.233ms returns FALSE +T714C 003:335.047 JLINK_HasError() +T714C 003:336.631 JLINK_IsHalted() +T714C 003:338.829 - 2.198ms returns TRUE +T714C 003:338.859 JLINK_ReadReg(R15 (PC)) +T714C 003:338.878 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:339.111 - 0.252ms returns 0x30500000 +T714C 003:339.137 JLINK_ClrBPEx(BPHandle = 0x000000E2) +T714C 003:339.155 - 0.017ms returns 0x00 +T714C 003:339.172 JLINK_ReadReg(R0) +T714C 003:339.188 - 0.016ms returns 0x00000000 +T714C 003:339.868 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:339.909 Data: 76 65 6E 74 5F 73 65 6E 64 00 5F 72 74 5F 73 65 ... +T714C 003:339.941 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:340.940 - 1.071ms returns 0x100 +T714C 003:340.963 JLINK_HasError() +T714C 003:340.981 JLINK_WriteReg(R0, 0x28016400) +T714C 003:340.998 - 0.018ms returns 0 +T714C 003:341.015 JLINK_WriteReg(R1, 0x00000100) +T714C 003:341.031 - 0.016ms returns 0 +T714C 003:341.048 JLINK_WriteReg(R2, 0x30500674) +T714C 003:341.064 - 0.016ms returns 0 +T714C 003:341.081 JLINK_WriteReg(R3, 0x00000000) +T714C 003:341.097 - 0.016ms returns 0 +T714C 003:341.114 JLINK_WriteReg(R4, 0x00000000) +T714C 003:341.130 - 0.016ms returns 0 +T714C 003:341.147 JLINK_WriteReg(R5, 0x00000000) +T714C 003:341.163 - 0.016ms returns 0 +T714C 003:341.181 JLINK_WriteReg(R6, 0x00000000) +T714C 003:341.197 - 0.016ms returns 0 +T714C 003:341.214 JLINK_WriteReg(R7, 0x00000000) +T714C 003:341.230 - 0.016ms returns 0 +T714C 003:341.249 JLINK_WriteReg(R8, 0x00000000) +T714C 003:341.265 - 0.016ms returns 0 +T714C 003:341.282 JLINK_WriteReg(R9, 0x30500458) +T714C 003:341.298 - 0.016ms returns 0 +T714C 003:341.316 JLINK_WriteReg(R10, 0x00000000) +T714C 003:341.333 - 0.016ms returns 0 +T714C 003:341.349 JLINK_WriteReg(R11, 0x00000000) +T714C 003:341.366 - 0.016ms returns 0 +T714C 003:341.382 JLINK_WriteReg(R12, 0x00000000) +T714C 003:341.399 - 0.016ms returns 0 +T714C 003:341.423 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:341.442 - 0.019ms returns 0 +T714C 003:341.460 JLINK_WriteReg(R14, 0x30500001) +T714C 003:341.476 - 0.016ms returns 0 +T714C 003:341.494 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:341.510 - 0.016ms returns 0 +T714C 003:341.526 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:341.543 - 0.016ms returns 0 +T714C 003:341.559 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:341.576 - 0.016ms returns 0 +T714C 003:341.593 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:341.610 - 0.016ms returns 0 +T714C 003:341.626 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:341.644 - 0.017ms returns 0 +T714C 003:341.663 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:341.680 - 0.018ms returns 0x000000E3 +T714C 003:341.698 JLINK_Go() +T714C 003:341.717 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:342.001 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:344.085 - 2.387ms +T714C 003:344.120 JLINK_IsHalted() +T714C 003:344.357 - 0.236ms returns FALSE +T714C 003:344.378 JLINK_HasError() +T714C 003:346.150 JLINK_IsHalted() +T714C 003:348.378 - 2.228ms returns TRUE +T714C 003:348.437 JLINK_ReadReg(R15 (PC)) +T714C 003:348.459 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:348.780 - 0.342ms returns 0x30500000 +T714C 003:348.804 JLINK_ClrBPEx(BPHandle = 0x000000E3) +T714C 003:348.823 - 0.019ms returns 0x00 +T714C 003:348.842 JLINK_ReadReg(R0) +T714C 003:348.858 - 0.017ms returns 0x00000000 +T714C 003:349.663 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:349.709 Data: 65 6E 74 5F 64 65 6C 65 74 65 00 72 74 5F 6D 75 ... +T714C 003:349.745 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:350.845 - 1.181ms returns 0x100 +T714C 003:350.896 JLINK_HasError() +T714C 003:350.915 JLINK_WriteReg(R0, 0x28016500) +T714C 003:350.935 - 0.020ms returns 0 +T714C 003:350.951 JLINK_WriteReg(R1, 0x00000100) +T714C 003:350.968 - 0.016ms returns 0 +T714C 003:350.984 JLINK_WriteReg(R2, 0x30500674) +T714C 003:351.000 - 0.016ms returns 0 +T714C 003:351.016 JLINK_WriteReg(R3, 0x00000000) +T714C 003:351.032 - 0.015ms returns 0 +T714C 003:351.049 JLINK_WriteReg(R4, 0x00000000) +T714C 003:351.066 - 0.017ms returns 0 +T714C 003:351.082 JLINK_WriteReg(R5, 0x00000000) +T714C 003:351.098 - 0.016ms returns 0 +T714C 003:351.114 JLINK_WriteReg(R6, 0x00000000) +T714C 003:351.130 - 0.015ms returns 0 +T714C 003:351.147 JLINK_WriteReg(R7, 0x00000000) +T714C 003:351.165 - 0.018ms returns 0 +T714C 003:351.181 JLINK_WriteReg(R8, 0x00000000) +T714C 003:351.197 - 0.016ms returns 0 +T714C 003:351.213 JLINK_WriteReg(R9, 0x30500458) +T714C 003:351.229 - 0.015ms returns 0 +T714C 003:351.246 JLINK_WriteReg(R10, 0x00000000) +T714C 003:351.262 - 0.016ms returns 0 +T714C 003:351.278 JLINK_WriteReg(R11, 0x00000000) +T714C 003:351.294 - 0.016ms returns 0 +T714C 003:351.311 JLINK_WriteReg(R12, 0x00000000) +T714C 003:351.328 - 0.016ms returns 0 +T714C 003:351.345 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:351.362 - 0.017ms returns 0 +T714C 003:351.378 JLINK_WriteReg(R14, 0x30500001) +T714C 003:351.395 - 0.016ms returns 0 +T714C 003:351.412 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:351.428 - 0.016ms returns 0 +T714C 003:351.445 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:351.461 - 0.016ms returns 0 +T714C 003:351.477 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:351.493 - 0.016ms returns 0 +T714C 003:351.510 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:351.525 - 0.015ms returns 0 +T714C 003:351.542 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:351.559 - 0.017ms returns 0 +T714C 003:351.580 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:351.598 - 0.017ms returns 0x000000E4 +T714C 003:351.615 JLINK_Go() +T714C 003:351.636 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:351.936 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:353.781 - 2.165ms +T714C 003:353.822 JLINK_IsHalted() +T714C 003:354.059 - 0.236ms returns FALSE +T714C 003:354.080 JLINK_HasError() +T714C 003:355.305 JLINK_IsHalted() +T714C 003:357.519 - 2.213ms returns TRUE +T714C 003:357.540 JLINK_ReadReg(R15 (PC)) +T714C 003:357.559 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:357.777 - 0.236ms returns 0x30500000 +T714C 003:357.797 JLINK_ClrBPEx(BPHandle = 0x000000E4) +T714C 003:357.814 - 0.017ms returns 0x00 +T714C 003:357.831 JLINK_ReadReg(R0) +T714C 003:357.848 - 0.016ms returns 0x00000000 +T714C 003:358.473 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:358.508 Data: 61 63 68 00 72 74 5F 6D 62 5F 63 6F 6E 74 72 6F ... +T714C 003:358.540 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:359.637 - 1.164ms returns 0x100 +T714C 003:359.660 JLINK_HasError() +T714C 003:359.678 JLINK_WriteReg(R0, 0x28016600) +T714C 003:359.696 - 0.018ms returns 0 +T714C 003:359.713 JLINK_WriteReg(R1, 0x00000100) +T714C 003:359.730 - 0.016ms returns 0 +T714C 003:359.746 JLINK_WriteReg(R2, 0x30500674) +T714C 003:359.762 - 0.016ms returns 0 +T714C 003:359.778 JLINK_WriteReg(R3, 0x00000000) +T714C 003:359.797 - 0.018ms returns 0 +T714C 003:359.821 JLINK_WriteReg(R4, 0x00000000) +T714C 003:359.837 - 0.016ms returns 0 +T714C 003:359.854 JLINK_WriteReg(R5, 0x00000000) +T714C 003:359.869 - 0.015ms returns 0 +T714C 003:359.885 JLINK_WriteReg(R6, 0x00000000) +T714C 003:359.901 - 0.016ms returns 0 +T714C 003:359.917 JLINK_WriteReg(R7, 0x00000000) +T714C 003:359.933 - 0.015ms returns 0 +T714C 003:359.949 JLINK_WriteReg(R8, 0x00000000) +T714C 003:359.965 - 0.016ms returns 0 +T714C 003:359.981 JLINK_WriteReg(R9, 0x30500458) +T714C 003:359.997 - 0.016ms returns 0 +T714C 003:360.013 JLINK_WriteReg(R10, 0x00000000) +T714C 003:360.029 - 0.016ms returns 0 +T714C 003:360.046 JLINK_WriteReg(R11, 0x00000000) +T714C 003:360.061 - 0.015ms returns 0 +T714C 003:360.078 JLINK_WriteReg(R12, 0x00000000) +T714C 003:360.094 - 0.016ms returns 0 +T714C 003:360.111 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:360.128 - 0.017ms returns 0 +T714C 003:360.144 JLINK_WriteReg(R14, 0x30500001) +T714C 003:360.161 - 0.016ms returns 0 +T714C 003:360.177 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:360.193 - 0.016ms returns 0 +T714C 003:360.210 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:360.226 - 0.016ms returns 0 +T714C 003:360.242 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:360.258 - 0.016ms returns 0 +T714C 003:360.275 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:360.290 - 0.015ms returns 0 +T714C 003:360.308 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:360.324 - 0.016ms returns 0 +T714C 003:360.341 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:360.357 - 0.016ms returns 0x000000E5 +T714C 003:360.376 JLINK_Go() +T714C 003:360.404 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:360.726 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:362.777 - 2.400ms +T714C 003:362.836 JLINK_IsHalted() +T714C 003:363.150 - 0.314ms returns FALSE +T714C 003:363.174 JLINK_HasError() +T714C 003:365.450 JLINK_IsHalted() +T714C 003:367.851 - 2.400ms returns TRUE +T714C 003:367.897 JLINK_ReadReg(R15 (PC)) +T714C 003:367.919 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:368.160 - 0.261ms returns 0x30500000 +T714C 003:368.181 JLINK_ClrBPEx(BPHandle = 0x000000E5) +T714C 003:368.198 - 0.016ms returns 0x00 +T714C 003:368.218 JLINK_ReadReg(R0) +T714C 003:368.235 - 0.016ms returns 0x00000000 +T714C 003:368.875 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:368.910 Data: 71 5F 72 65 63 76 00 5F 72 74 5F 65 76 65 6E 74 ... +T714C 003:368.942 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:369.998 - 1.123ms returns 0x100 +T714C 003:370.027 JLINK_HasError() +T714C 003:370.044 JLINK_WriteReg(R0, 0x28016700) +T714C 003:370.063 - 0.018ms returns 0 +T714C 003:370.079 JLINK_WriteReg(R1, 0x00000100) +T714C 003:370.095 - 0.016ms returns 0 +T714C 003:370.112 JLINK_WriteReg(R2, 0x30500674) +T714C 003:370.128 - 0.016ms returns 0 +T714C 003:370.145 JLINK_WriteReg(R3, 0x00000000) +T714C 003:370.161 - 0.016ms returns 0 +T714C 003:370.178 JLINK_WriteReg(R4, 0x00000000) +T714C 003:370.194 - 0.016ms returns 0 +T714C 003:370.210 JLINK_WriteReg(R5, 0x00000000) +T714C 003:370.226 - 0.015ms returns 0 +T714C 003:370.242 JLINK_WriteReg(R6, 0x00000000) +T714C 003:370.258 - 0.016ms returns 0 +T714C 003:370.274 JLINK_WriteReg(R7, 0x00000000) +T714C 003:370.290 - 0.015ms returns 0 +T714C 003:370.306 JLINK_WriteReg(R8, 0x00000000) +T714C 003:370.322 - 0.015ms returns 0 +T714C 003:370.338 JLINK_WriteReg(R9, 0x30500458) +T714C 003:370.354 - 0.016ms returns 0 +T714C 003:370.372 JLINK_WriteReg(R10, 0x00000000) +T714C 003:370.388 - 0.015ms returns 0 +T714C 003:370.404 JLINK_WriteReg(R11, 0x00000000) +T714C 003:370.420 - 0.015ms returns 0 +T714C 003:370.436 JLINK_WriteReg(R12, 0x00000000) +T714C 003:370.454 - 0.018ms returns 0 +T714C 003:370.470 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:370.488 - 0.017ms returns 0 +T714C 003:370.504 JLINK_WriteReg(R14, 0x30500001) +T714C 003:370.520 - 0.015ms returns 0 +T714C 003:370.536 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:370.552 - 0.017ms returns 0 +T714C 003:370.568 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:370.584 - 0.015ms returns 0 +T714C 003:370.606 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:370.624 - 0.018ms returns 0 +T714C 003:370.641 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:370.657 - 0.015ms returns 0 +T714C 003:370.672 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:370.689 - 0.016ms returns 0 +T714C 003:370.707 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:370.723 - 0.017ms returns 0x000000E6 +T714C 003:370.740 JLINK_Go() +T714C 003:370.758 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:371.006 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:372.853 - 2.109ms +T714C 003:372.914 JLINK_IsHalted() +T714C 003:373.108 - 0.193ms returns FALSE +T714C 003:373.128 JLINK_HasError() +T714C 003:374.503 JLINK_IsHalted() +T714C 003:376.621 - 2.120ms returns TRUE +T714C 003:376.662 JLINK_ReadReg(R15 (PC)) +T714C 003:376.684 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:376.928 - 0.266ms returns 0x30500000 +T714C 003:376.950 JLINK_ClrBPEx(BPHandle = 0x000000E6) +T714C 003:376.966 - 0.016ms returns 0x00 +T714C 003:376.983 JLINK_ReadReg(R0) +T714C 003:377.000 - 0.017ms returns 0x00000000 +T714C 003:377.588 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:377.621 Data: 63 6F 6D 6D 61 6E 64 73 20 6C 69 6B 65 3A 20 62 ... +T714C 003:377.653 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:378.724 - 1.136ms returns 0x100 +T714C 003:378.749 JLINK_HasError() +T714C 003:378.767 JLINK_WriteReg(R0, 0x28016800) +T714C 003:378.786 - 0.019ms returns 0 +T714C 003:378.804 JLINK_WriteReg(R1, 0x00000100) +T714C 003:378.820 - 0.016ms returns 0 +T714C 003:378.836 JLINK_WriteReg(R2, 0x30500674) +T714C 003:378.855 - 0.019ms returns 0 +T714C 003:378.871 JLINK_WriteReg(R3, 0x00000000) +T714C 003:378.887 - 0.015ms returns 0 +T714C 003:378.903 JLINK_WriteReg(R4, 0x00000000) +T714C 003:378.919 - 0.016ms returns 0 +T714C 003:378.935 JLINK_WriteReg(R5, 0x00000000) +T714C 003:378.951 - 0.015ms returns 0 +T714C 003:378.967 JLINK_WriteReg(R6, 0x00000000) +T714C 003:378.983 - 0.015ms returns 0 +T714C 003:378.999 JLINK_WriteReg(R7, 0x00000000) +T714C 003:379.015 - 0.015ms returns 0 +T714C 003:379.032 JLINK_WriteReg(R8, 0x00000000) +T714C 003:379.048 - 0.015ms returns 0 +T714C 003:379.064 JLINK_WriteReg(R9, 0x30500458) +T714C 003:379.080 - 0.015ms returns 0 +T714C 003:379.096 JLINK_WriteReg(R10, 0x00000000) +T714C 003:379.112 - 0.015ms returns 0 +T714C 003:379.128 JLINK_WriteReg(R11, 0x00000000) +T714C 003:379.144 - 0.015ms returns 0 +T714C 003:379.160 JLINK_WriteReg(R12, 0x00000000) +T714C 003:379.176 - 0.016ms returns 0 +T714C 003:379.192 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:379.208 - 0.017ms returns 0 +T714C 003:379.225 JLINK_WriteReg(R14, 0x30500001) +T714C 003:379.240 - 0.015ms returns 0 +T714C 003:379.257 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:379.272 - 0.015ms returns 0 +T714C 003:379.288 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:379.305 - 0.016ms returns 0 +T714C 003:379.321 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:379.337 - 0.015ms returns 0 +T714C 003:379.354 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:379.370 - 0.016ms returns 0 +T714C 003:379.386 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:379.402 - 0.015ms returns 0 +T714C 003:379.419 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:379.435 - 0.016ms returns 0x000000E7 +T714C 003:379.451 JLINK_Go() +T714C 003:379.469 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:379.748 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:381.564 - 2.112ms +T714C 003:381.617 JLINK_IsHalted() +T714C 003:381.904 - 0.286ms returns FALSE +T714C 003:381.927 JLINK_HasError() +T714C 003:383.409 JLINK_IsHalted() +T714C 003:385.615 - 2.205ms returns TRUE +T714C 003:385.656 JLINK_ReadReg(R15 (PC)) +T714C 003:385.676 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:385.879 - 0.222ms returns 0x30500000 +T714C 003:385.900 JLINK_ClrBPEx(BPHandle = 0x000000E7) +T714C 003:385.917 - 0.016ms returns 0x00 +T714C 003:385.934 JLINK_ReadReg(R0) +T714C 003:385.950 - 0.016ms returns 0x00000000 +T714C 003:386.550 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:386.584 Data: 70 75 5F 72 65 73 65 74 28 29 20 64 6F 65 73 6E ... +T714C 003:386.624 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:387.679 - 1.129ms returns 0x100 +T714C 003:387.704 JLINK_HasError() +T714C 003:387.721 JLINK_WriteReg(R0, 0x28016900) +T714C 003:387.741 - 0.019ms returns 0 +T714C 003:387.757 JLINK_WriteReg(R1, 0x00000100) +T714C 003:387.774 - 0.016ms returns 0 +T714C 003:387.790 JLINK_WriteReg(R2, 0x30500674) +T714C 003:387.806 - 0.016ms returns 0 +T714C 003:387.822 JLINK_WriteReg(R3, 0x00000000) +T714C 003:387.838 - 0.016ms returns 0 +T714C 003:387.854 JLINK_WriteReg(R4, 0x00000000) +T714C 003:387.870 - 0.015ms returns 0 +T714C 003:387.886 JLINK_WriteReg(R5, 0x00000000) +T714C 003:387.902 - 0.015ms returns 0 +T714C 003:387.918 JLINK_WriteReg(R6, 0x00000000) +T714C 003:387.934 - 0.015ms returns 0 +T714C 003:387.950 JLINK_WriteReg(R7, 0x00000000) +T714C 003:387.966 - 0.015ms returns 0 +T714C 003:387.982 JLINK_WriteReg(R8, 0x00000000) +T714C 003:387.998 - 0.016ms returns 0 +T714C 003:388.015 JLINK_WriteReg(R9, 0x30500458) +T714C 003:388.030 - 0.015ms returns 0 +T714C 003:388.047 JLINK_WriteReg(R10, 0x00000000) +T714C 003:388.062 - 0.015ms returns 0 +T714C 003:388.080 JLINK_WriteReg(R11, 0x00000000) +T714C 003:388.096 - 0.016ms returns 0 +T714C 003:388.112 JLINK_WriteReg(R12, 0x00000000) +T714C 003:388.129 - 0.016ms returns 0 +T714C 003:388.145 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:388.162 - 0.016ms returns 0 +T714C 003:388.178 JLINK_WriteReg(R14, 0x30500001) +T714C 003:388.194 - 0.015ms returns 0 +T714C 003:388.210 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:388.237 - 0.027ms returns 0 +T714C 003:388.253 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:388.269 - 0.015ms returns 0 +T714C 003:388.286 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:388.301 - 0.015ms returns 0 +T714C 003:388.318 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:388.333 - 0.015ms returns 0 +T714C 003:388.350 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:388.366 - 0.015ms returns 0 +T714C 003:388.383 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:388.399 - 0.016ms returns 0x000000E8 +T714C 003:388.415 JLINK_Go() +T714C 003:388.433 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:388.713 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:390.585 - 2.170ms +T714C 003:390.632 JLINK_IsHalted() +T714C 003:390.933 - 0.301ms returns FALSE +T714C 003:390.970 JLINK_HasError() +T714C 003:392.420 JLINK_IsHalted() +T714C 003:394.603 - 2.183ms returns TRUE +T714C 003:394.679 JLINK_ReadReg(R15 (PC)) +T714C 003:394.700 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:394.997 - 0.318ms returns 0x30500000 +T714C 003:395.020 JLINK_ClrBPEx(BPHandle = 0x000000E8) +T714C 003:395.037 - 0.016ms returns 0x00 +T714C 003:395.054 JLINK_ReadReg(R0) +T714C 003:395.071 - 0.017ms returns 0x00000000 +T714C 003:395.706 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:395.740 Data: 65 72 69 63 00 72 74 5F 6F 62 6A 65 63 74 5F 67 ... +T714C 003:395.770 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:396.774 - 1.068ms returns 0x100 +T714C 003:396.798 JLINK_HasError() +T714C 003:396.815 JLINK_WriteReg(R0, 0x28016A00) +T714C 003:396.834 - 0.018ms returns 0 +T714C 003:396.850 JLINK_WriteReg(R1, 0x00000100) +T714C 003:396.866 - 0.016ms returns 0 +T714C 003:396.882 JLINK_WriteReg(R2, 0x30500674) +T714C 003:396.898 - 0.015ms returns 0 +T714C 003:396.916 JLINK_WriteReg(R3, 0x00000000) +T714C 003:396.932 - 0.016ms returns 0 +T714C 003:396.948 JLINK_WriteReg(R4, 0x00000000) +T714C 003:396.966 - 0.018ms returns 0 +T714C 003:396.982 JLINK_WriteReg(R5, 0x00000000) +T714C 003:396.998 - 0.015ms returns 0 +T714C 003:397.014 JLINK_WriteReg(R6, 0x00000000) +T714C 003:397.031 - 0.016ms returns 0 +T714C 003:397.047 JLINK_WriteReg(R7, 0x00000000) +T714C 003:397.063 - 0.015ms returns 0 +T714C 003:397.079 JLINK_WriteReg(R8, 0x00000000) +T714C 003:397.094 - 0.015ms returns 0 +T714C 003:397.111 JLINK_WriteReg(R9, 0x30500458) +T714C 003:397.127 - 0.015ms returns 0 +T714C 003:397.143 JLINK_WriteReg(R10, 0x00000000) +T714C 003:397.159 - 0.016ms returns 0 +T714C 003:397.176 JLINK_WriteReg(R11, 0x00000000) +T714C 003:397.191 - 0.015ms returns 0 +T714C 003:397.216 JLINK_WriteReg(R12, 0x00000000) +T714C 003:397.232 - 0.015ms returns 0 +T714C 003:397.248 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:397.265 - 0.017ms returns 0 +T714C 003:397.282 JLINK_WriteReg(R14, 0x30500001) +T714C 003:397.298 - 0.015ms returns 0 +T714C 003:397.314 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:397.330 - 0.016ms returns 0 +T714C 003:397.346 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:397.362 - 0.016ms returns 0 +T714C 003:397.378 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:397.394 - 0.015ms returns 0 +T714C 003:397.410 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:397.426 - 0.016ms returns 0 +T714C 003:397.442 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:397.458 - 0.016ms returns 0 +T714C 003:397.475 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:397.491 - 0.016ms returns 0x000000E9 +T714C 003:397.508 JLINK_Go() +T714C 003:397.525 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:397.908 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:399.724 - 2.216ms +T714C 003:399.764 JLINK_IsHalted() +T714C 003:400.028 - 0.264ms returns FALSE +T714C 003:400.050 JLINK_HasError() +T714C 003:402.016 JLINK_IsHalted() +T714C 003:404.235 - 2.218ms returns TRUE +T714C 003:404.267 JLINK_ReadReg(R15 (PC)) +T714C 003:404.286 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:404.569 - 0.302ms returns 0x30500000 +T714C 003:404.606 JLINK_ClrBPEx(BPHandle = 0x000000E9) +T714C 003:404.626 - 0.019ms returns 0x00 +T714C 003:404.644 JLINK_ReadReg(R0) +T714C 003:404.661 - 0.017ms returns 0x00000000 +T714C 003:405.250 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:405.285 Data: 29 29 00 72 74 5F 6F 62 6A 65 63 74 5F 69 73 5F ... +T714C 003:405.316 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:406.326 - 1.076ms returns 0x100 +T714C 003:406.378 JLINK_HasError() +T714C 003:406.398 JLINK_WriteReg(R0, 0x28016B00) +T714C 003:406.418 - 0.020ms returns 0 +T714C 003:406.434 JLINK_WriteReg(R1, 0x00000100) +T714C 003:406.452 - 0.017ms returns 0 +T714C 003:406.536 JLINK_WriteReg(R2, 0x30500674) +T714C 003:406.557 - 0.021ms returns 0 +T714C 003:406.575 JLINK_WriteReg(R3, 0x00000000) +T714C 003:406.592 - 0.016ms returns 0 +T714C 003:406.608 JLINK_WriteReg(R4, 0x00000000) +T714C 003:406.624 - 0.016ms returns 0 +T714C 003:406.641 JLINK_WriteReg(R5, 0x00000000) +T714C 003:406.656 - 0.015ms returns 0 +T714C 003:406.673 JLINK_WriteReg(R6, 0x00000000) +T714C 003:406.689 - 0.016ms returns 0 +T714C 003:406.705 JLINK_WriteReg(R7, 0x00000000) +T714C 003:406.721 - 0.015ms returns 0 +T714C 003:406.738 JLINK_WriteReg(R8, 0x00000000) +T714C 003:406.753 - 0.015ms returns 0 +T714C 003:406.769 JLINK_WriteReg(R9, 0x30500458) +T714C 003:406.788 - 0.018ms returns 0 +T714C 003:406.805 JLINK_WriteReg(R10, 0x00000000) +T714C 003:406.821 - 0.016ms returns 0 +T714C 003:406.838 JLINK_WriteReg(R11, 0x00000000) +T714C 003:406.854 - 0.016ms returns 0 +T714C 003:406.872 JLINK_WriteReg(R12, 0x00000000) +T714C 003:406.888 - 0.016ms returns 0 +T714C 003:406.904 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:406.922 - 0.018ms returns 0 +T714C 003:406.939 JLINK_WriteReg(R14, 0x30500001) +T714C 003:406.955 - 0.016ms returns 0 +T714C 003:406.973 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:406.990 - 0.016ms returns 0 +T714C 003:407.006 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:407.022 - 0.016ms returns 0 +T714C 003:407.039 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:407.056 - 0.016ms returns 0 +T714C 003:407.072 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:407.089 - 0.016ms returns 0 +T714C 003:407.105 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:407.122 - 0.016ms returns 0 +T714C 003:407.139 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:407.156 - 0.017ms returns 0x000000EA +T714C 003:407.172 JLINK_Go() +T714C 003:407.194 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:407.445 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:409.422 - 2.249ms +T714C 003:409.479 JLINK_IsHalted() +T714C 003:409.711 - 0.231ms returns FALSE +T714C 003:409.732 JLINK_HasError() +T714C 003:411.008 JLINK_IsHalted() +T714C 003:413.139 - 2.130ms returns TRUE +T714C 003:413.194 JLINK_ReadReg(R15 (PC)) +T714C 003:413.214 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:413.498 - 0.303ms returns 0x30500000 +T714C 003:413.520 JLINK_ClrBPEx(BPHandle = 0x000000EA) +T714C 003:413.536 - 0.016ms returns 0x00 +T714C 003:413.553 JLINK_ReadReg(R0) +T714C 003:413.570 - 0.016ms returns 0x00000000 +T714C 003:414.215 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:414.250 Data: 72 74 5F 75 69 6E 74 38 5F 74 20 2A 29 72 6D 65 ... +T714C 003:414.282 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:415.298 - 1.083ms returns 0x100 +T714C 003:415.332 JLINK_HasError() +T714C 003:415.350 JLINK_WriteReg(R0, 0x28016C00) +T714C 003:415.370 - 0.020ms returns 0 +T714C 003:415.386 JLINK_WriteReg(R1, 0x00000100) +T714C 003:415.402 - 0.016ms returns 0 +T714C 003:415.420 JLINK_WriteReg(R2, 0x30500674) +T714C 003:415.436 - 0.016ms returns 0 +T714C 003:415.452 JLINK_WriteReg(R3, 0x00000000) +T714C 003:415.468 - 0.015ms returns 0 +T714C 003:415.484 JLINK_WriteReg(R4, 0x00000000) +T714C 003:415.500 - 0.016ms returns 0 +T714C 003:415.516 JLINK_WriteReg(R5, 0x00000000) +T714C 003:415.532 - 0.015ms returns 0 +T714C 003:415.549 JLINK_WriteReg(R6, 0x00000000) +T714C 003:415.564 - 0.015ms returns 0 +T714C 003:415.580 JLINK_WriteReg(R7, 0x00000000) +T714C 003:415.596 - 0.015ms returns 0 +T714C 003:415.612 JLINK_WriteReg(R8, 0x00000000) +T714C 003:415.630 - 0.017ms returns 0 +T714C 003:415.647 JLINK_WriteReg(R9, 0x30500458) +T714C 003:415.663 - 0.016ms returns 0 +T714C 003:415.680 JLINK_WriteReg(R10, 0x00000000) +T714C 003:415.696 - 0.016ms returns 0 +T714C 003:415.712 JLINK_WriteReg(R11, 0x00000000) +T714C 003:415.728 - 0.015ms returns 0 +T714C 003:415.744 JLINK_WriteReg(R12, 0x00000000) +T714C 003:415.760 - 0.015ms returns 0 +T714C 003:415.776 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:415.793 - 0.017ms returns 0 +T714C 003:415.810 JLINK_WriteReg(R14, 0x30500001) +T714C 003:415.825 - 0.015ms returns 0 +T714C 003:415.842 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:415.858 - 0.015ms returns 0 +T714C 003:415.875 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:415.891 - 0.016ms returns 0 +T714C 003:415.907 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:415.923 - 0.016ms returns 0 +T714C 003:415.939 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:415.955 - 0.015ms returns 0 +T714C 003:415.971 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:415.987 - 0.015ms returns 0 +T714C 003:416.003 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:416.020 - 0.017ms returns 0x000000EB +T714C 003:416.036 JLINK_Go() +T714C 003:416.054 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:416.294 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:418.188 - 2.151ms +T714C 003:418.217 JLINK_IsHalted() +T714C 003:418.463 - 0.245ms returns FALSE +T714C 003:418.487 JLINK_HasError() +T714C 003:420.039 JLINK_IsHalted() +T714C 003:422.252 - 2.214ms returns TRUE +T714C 003:422.315 JLINK_ReadReg(R15 (PC)) +T714C 003:422.338 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:422.690 - 0.374ms returns 0x30500000 +T714C 003:422.800 JLINK_ClrBPEx(BPHandle = 0x000000EB) +T714C 003:422.823 - 0.022ms returns 0x00 +T714C 003:422.840 JLINK_ReadReg(R0) +T714C 003:422.860 - 0.019ms returns 0x00000000 +T714C 003:423.567 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:423.603 Data: 6D 65 6D 2D 3E 70 61 72 65 6E 74 2E 70 61 72 65 ... +T714C 003:423.636 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:424.680 - 1.111ms returns 0x100 +T714C 003:424.787 JLINK_HasError() +T714C 003:424.808 JLINK_WriteReg(R0, 0x28016D00) +T714C 003:424.830 - 0.021ms returns 0 +T714C 003:424.846 JLINK_WriteReg(R1, 0x00000100) +T714C 003:424.864 - 0.018ms returns 0 +T714C 003:424.881 JLINK_WriteReg(R2, 0x30500674) +T714C 003:424.898 - 0.017ms returns 0 +T714C 003:424.915 JLINK_WriteReg(R3, 0x00000000) +T714C 003:424.931 - 0.016ms returns 0 +T714C 003:424.948 JLINK_WriteReg(R4, 0x00000000) +T714C 003:424.966 - 0.018ms returns 0 +T714C 003:424.983 JLINK_WriteReg(R5, 0x00000000) +T714C 003:424.999 - 0.015ms returns 0 +T714C 003:425.015 JLINK_WriteReg(R6, 0x00000000) +T714C 003:425.040 - 0.024ms returns 0 +T714C 003:425.056 JLINK_WriteReg(R7, 0x00000000) +T714C 003:425.073 - 0.016ms returns 0 +T714C 003:425.090 JLINK_WriteReg(R8, 0x00000000) +T714C 003:425.106 - 0.016ms returns 0 +T714C 003:425.122 JLINK_WriteReg(R9, 0x30500458) +T714C 003:425.139 - 0.016ms returns 0 +T714C 003:425.155 JLINK_WriteReg(R10, 0x00000000) +T714C 003:425.171 - 0.016ms returns 0 +T714C 003:425.187 JLINK_WriteReg(R11, 0x00000000) +T714C 003:425.203 - 0.015ms returns 0 +T714C 003:425.219 JLINK_WriteReg(R12, 0x00000000) +T714C 003:425.235 - 0.016ms returns 0 +T714C 003:425.252 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:425.269 - 0.017ms returns 0 +T714C 003:425.286 JLINK_WriteReg(R14, 0x30500001) +T714C 003:425.302 - 0.016ms returns 0 +T714C 003:425.319 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:425.335 - 0.016ms returns 0 +T714C 003:425.352 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:425.368 - 0.016ms returns 0 +T714C 003:425.384 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:425.400 - 0.015ms returns 0 +T714C 003:425.416 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:425.433 - 0.016ms returns 0 +T714C 003:425.449 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:425.465 - 0.016ms returns 0 +T714C 003:425.483 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:425.500 - 0.017ms returns 0x000000EC +T714C 003:425.516 JLINK_Go() +T714C 003:425.535 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:425.832 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:427.713 - 2.196ms +T714C 003:427.778 JLINK_IsHalted() +T714C 003:428.038 - 0.259ms returns FALSE +T714C 003:428.125 JLINK_HasError() +T714C 003:429.544 JLINK_IsHalted() +T714C 003:431.792 - 2.249ms returns TRUE +T714C 003:431.844 JLINK_ReadReg(R15 (PC)) +T714C 003:431.866 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:432.200 - 0.343ms returns 0x30500000 +T714C 003:432.226 JLINK_ClrBPEx(BPHandle = 0x000000EC) +T714C 003:432.245 - 0.018ms returns 0x00 +T714C 003:432.262 JLINK_ReadReg(R0) +T714C 003:432.280 - 0.018ms returns 0x00000000 +T714C 003:432.997 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:433.036 Data: 74 20 21 3D 20 52 54 5F 4E 55 4C 4C 00 72 74 5F ... +T714C 003:433.067 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:434.145 - 1.147ms returns 0x100 +T714C 003:434.196 JLINK_HasError() +T714C 003:434.214 JLINK_WriteReg(R0, 0x28016E00) +T714C 003:434.234 - 0.020ms returns 0 +T714C 003:434.251 JLINK_WriteReg(R1, 0x00000100) +T714C 003:434.267 - 0.016ms returns 0 +T714C 003:434.283 JLINK_WriteReg(R2, 0x30500674) +T714C 003:434.300 - 0.016ms returns 0 +T714C 003:434.316 JLINK_WriteReg(R3, 0x00000000) +T714C 003:434.332 - 0.015ms returns 0 +T714C 003:434.349 JLINK_WriteReg(R4, 0x00000000) +T714C 003:434.365 - 0.016ms returns 0 +T714C 003:434.381 JLINK_WriteReg(R5, 0x00000000) +T714C 003:434.397 - 0.015ms returns 0 +T714C 003:434.413 JLINK_WriteReg(R6, 0x00000000) +T714C 003:434.431 - 0.017ms returns 0 +T714C 003:434.447 JLINK_WriteReg(R7, 0x00000000) +T714C 003:434.463 - 0.016ms returns 0 +T714C 003:434.479 JLINK_WriteReg(R8, 0x00000000) +T714C 003:434.495 - 0.015ms returns 0 +T714C 003:434.511 JLINK_WriteReg(R9, 0x30500458) +T714C 003:434.527 - 0.016ms returns 0 +T714C 003:434.544 JLINK_WriteReg(R10, 0x00000000) +T714C 003:434.560 - 0.016ms returns 0 +T714C 003:434.577 JLINK_WriteReg(R11, 0x00000000) +T714C 003:434.593 - 0.016ms returns 0 +T714C 003:434.609 JLINK_WriteReg(R12, 0x00000000) +T714C 003:434.625 - 0.016ms returns 0 +T714C 003:434.644 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:434.661 - 0.017ms returns 0 +T714C 003:434.678 JLINK_WriteReg(R14, 0x30500001) +T714C 003:434.695 - 0.016ms returns 0 +T714C 003:434.712 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:434.728 - 0.016ms returns 0 +T714C 003:434.744 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:434.761 - 0.016ms returns 0 +T714C 003:434.777 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:434.793 - 0.016ms returns 0 +T714C 003:434.810 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:434.826 - 0.015ms returns 0 +T714C 003:434.843 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:434.866 - 0.023ms returns 0 +T714C 003:434.886 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:434.904 - 0.018ms returns 0x000000ED +T714C 003:434.920 JLINK_Go() +T714C 003:434.939 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:435.228 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:437.261 - 2.339ms +T714C 003:437.310 JLINK_IsHalted() +T714C 003:437.605 - 0.295ms returns FALSE +T714C 003:437.627 JLINK_HasError() +T714C 003:439.542 JLINK_IsHalted() +T714C 003:441.826 - 2.284ms returns TRUE +T714C 003:441.860 JLINK_ReadReg(R15 (PC)) +T714C 003:441.880 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:442.090 - 0.230ms returns 0x30500000 +T714C 003:442.149 JLINK_ClrBPEx(BPHandle = 0x000000ED) +T714C 003:442.166 - 0.016ms returns 0x00 +T714C 003:442.183 JLINK_ReadReg(R0) +T714C 003:442.199 - 0.016ms returns 0x00000000 +T714C 003:442.832 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:442.877 Data: 65 5F 74 68 72 65 61 64 00 74 69 63 6B 20 21 3D ... +T714C 003:442.910 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:443.996 - 1.163ms returns 0x100 +T714C 003:444.020 JLINK_HasError() +T714C 003:444.039 JLINK_WriteReg(R0, 0x28016F00) +T714C 003:444.056 - 0.017ms returns 0 +T714C 003:444.076 JLINK_WriteReg(R1, 0x00000100) +T714C 003:444.093 - 0.016ms returns 0 +T714C 003:444.109 JLINK_WriteReg(R2, 0x30500674) +T714C 003:444.125 - 0.016ms returns 0 +T714C 003:444.141 JLINK_WriteReg(R3, 0x00000000) +T714C 003:444.157 - 0.016ms returns 0 +T714C 003:444.174 JLINK_WriteReg(R4, 0x00000000) +T714C 003:444.189 - 0.015ms returns 0 +T714C 003:444.205 JLINK_WriteReg(R5, 0x00000000) +T714C 003:444.221 - 0.015ms returns 0 +T714C 003:444.237 JLINK_WriteReg(R6, 0x00000000) +T714C 003:444.253 - 0.016ms returns 0 +T714C 003:444.270 JLINK_WriteReg(R7, 0x00000000) +T714C 003:444.286 - 0.015ms returns 0 +T714C 003:444.302 JLINK_WriteReg(R8, 0x00000000) +T714C 003:444.318 - 0.015ms returns 0 +T714C 003:444.334 JLINK_WriteReg(R9, 0x30500458) +T714C 003:444.349 - 0.015ms returns 0 +T714C 003:444.366 JLINK_WriteReg(R10, 0x00000000) +T714C 003:444.382 - 0.016ms returns 0 +T714C 003:444.399 JLINK_WriteReg(R11, 0x00000000) +T714C 003:444.414 - 0.015ms returns 0 +T714C 003:444.431 JLINK_WriteReg(R12, 0x00000000) +T714C 003:444.447 - 0.016ms returns 0 +T714C 003:444.464 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:444.481 - 0.017ms returns 0 +T714C 003:444.497 JLINK_WriteReg(R14, 0x30500001) +T714C 003:444.514 - 0.016ms returns 0 +T714C 003:444.532 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:444.548 - 0.016ms returns 0 +T714C 003:444.573 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:444.592 - 0.018ms returns 0 +T714C 003:444.610 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:444.626 - 0.017ms returns 0 +T714C 003:444.645 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:444.662 - 0.017ms returns 0 +T714C 003:444.680 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:444.697 - 0.017ms returns 0 +T714C 003:444.716 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:444.733 - 0.017ms returns 0x000000EE +T714C 003:444.751 JLINK_Go() +T714C 003:444.770 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:445.032 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:446.908 - 2.156ms +T714C 003:446.956 JLINK_IsHalted() +T714C 003:447.156 - 0.199ms returns FALSE +T714C 003:447.180 JLINK_HasError() +T714C 003:448.558 JLINK_IsHalted() +T714C 003:450.938 - 2.381ms returns TRUE +T714C 003:450.992 JLINK_ReadReg(R15 (PC)) +T714C 003:451.014 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:451.292 - 0.299ms returns 0x30500000 +T714C 003:451.314 JLINK_ClrBPEx(BPHandle = 0x000000EE) +T714C 003:451.330 - 0.016ms returns 0x00 +T714C 003:451.348 JLINK_ReadReg(R0) +T714C 003:451.364 - 0.016ms returns 0x00000000 +T714C 003:452.562 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:452.620 Data: 68 72 65 61 64 5F 63 6F 6E 74 72 6F 6C 00 5F 74 ... +T714C 003:452.660 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:453.772 - 1.208ms returns 0x100 +T714C 003:453.849 JLINK_HasError() +T714C 003:453.871 JLINK_WriteReg(R0, 0x28017000) +T714C 003:453.893 - 0.022ms returns 0 +T714C 003:453.920 JLINK_WriteReg(R1, 0x00000100) +T714C 003:453.937 - 0.016ms returns 0 +T714C 003:453.954 JLINK_WriteReg(R2, 0x30500674) +T714C 003:453.972 - 0.017ms returns 0 +T714C 003:453.988 JLINK_WriteReg(R3, 0x00000000) +T714C 003:454.004 - 0.016ms returns 0 +T714C 003:454.022 JLINK_WriteReg(R4, 0x00000000) +T714C 003:454.038 - 0.016ms returns 0 +T714C 003:454.054 JLINK_WriteReg(R5, 0x00000000) +T714C 003:454.070 - 0.016ms returns 0 +T714C 003:454.087 JLINK_WriteReg(R6, 0x00000000) +T714C 003:454.109 - 0.022ms returns 0 +T714C 003:454.128 JLINK_WriteReg(R7, 0x00000000) +T714C 003:454.144 - 0.016ms returns 0 +T714C 003:454.160 JLINK_WriteReg(R8, 0x00000000) +T714C 003:454.176 - 0.016ms returns 0 +T714C 003:454.192 JLINK_WriteReg(R9, 0x30500458) +T714C 003:454.225 - 0.032ms returns 0 +T714C 003:454.245 JLINK_WriteReg(R10, 0x00000000) +T714C 003:454.263 - 0.017ms returns 0 +T714C 003:454.281 JLINK_WriteReg(R11, 0x00000000) +T714C 003:454.298 - 0.017ms returns 0 +T714C 003:454.315 JLINK_WriteReg(R12, 0x00000000) +T714C 003:454.331 - 0.016ms returns 0 +T714C 003:454.348 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:454.365 - 0.017ms returns 0 +T714C 003:454.382 JLINK_WriteReg(R14, 0x30500001) +T714C 003:454.398 - 0.016ms returns 0 +T714C 003:454.414 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:454.430 - 0.015ms returns 0 +T714C 003:454.447 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:454.463 - 0.016ms returns 0 +T714C 003:454.480 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:454.497 - 0.016ms returns 0 +T714C 003:454.514 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:454.531 - 0.017ms returns 0 +T714C 003:454.548 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:454.566 - 0.017ms returns 0 +T714C 003:454.584 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:454.604 - 0.020ms returns 0x000000EF +T714C 003:454.621 JLINK_Go() +T714C 003:454.642 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:454.972 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:456.860 - 2.236ms +T714C 003:456.917 JLINK_IsHalted() +T714C 003:457.230 - 0.312ms returns FALSE +T714C 003:457.290 JLINK_HasError() +T714C 003:458.574 JLINK_IsHalted() +T714C 003:460.874 - 2.299ms returns TRUE +T714C 003:460.913 JLINK_ReadReg(R15 (PC)) +T714C 003:460.934 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:461.190 - 0.276ms returns 0x30500000 +T714C 003:461.212 JLINK_ClrBPEx(BPHandle = 0x000000EF) +T714C 003:461.229 - 0.016ms returns 0x00 +T714C 003:461.246 JLINK_ReadReg(R0) +T714C 003:461.263 - 0.016ms returns 0x00000000 +T714C 003:461.910 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:461.951 Data: 79 70 65 28 26 74 69 6D 65 72 2D 3E 70 61 72 65 ... +T714C 003:461.984 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:463.053 - 1.143ms returns 0x100 +T714C 003:463.078 JLINK_HasError() +T714C 003:463.098 JLINK_WriteReg(R0, 0x28017100) +T714C 003:463.117 - 0.019ms returns 0 +T714C 003:463.133 JLINK_WriteReg(R1, 0x00000100) +T714C 003:463.150 - 0.017ms returns 0 +T714C 003:463.166 JLINK_WriteReg(R2, 0x30500674) +T714C 003:463.182 - 0.016ms returns 0 +T714C 003:463.199 JLINK_WriteReg(R3, 0x00000000) +T714C 003:463.215 - 0.015ms returns 0 +T714C 003:463.234 JLINK_WriteReg(R4, 0x00000000) +T714C 003:463.250 - 0.015ms returns 0 +T714C 003:463.266 JLINK_WriteReg(R5, 0x00000000) +T714C 003:463.283 - 0.016ms returns 0 +T714C 003:463.299 JLINK_WriteReg(R6, 0x00000000) +T714C 003:463.314 - 0.015ms returns 0 +T714C 003:463.331 JLINK_WriteReg(R7, 0x00000000) +T714C 003:463.346 - 0.016ms returns 0 +T714C 003:463.362 JLINK_WriteReg(R8, 0x00000000) +T714C 003:463.379 - 0.016ms returns 0 +T714C 003:463.395 JLINK_WriteReg(R9, 0x30500458) +T714C 003:463.410 - 0.015ms returns 0 +T714C 003:463.427 JLINK_WriteReg(R10, 0x00000000) +T714C 003:463.442 - 0.015ms returns 0 +T714C 003:463.459 JLINK_WriteReg(R11, 0x00000000) +T714C 003:463.475 - 0.015ms returns 0 +T714C 003:463.491 JLINK_WriteReg(R12, 0x00000000) +T714C 003:463.508 - 0.016ms returns 0 +T714C 003:463.524 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:463.540 - 0.017ms returns 0 +T714C 003:463.556 JLINK_WriteReg(R14, 0x30500001) +T714C 003:463.583 - 0.026ms returns 0 +T714C 003:463.599 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:463.615 - 0.016ms returns 0 +T714C 003:463.632 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:463.648 - 0.016ms returns 0 +T714C 003:463.665 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:463.681 - 0.015ms returns 0 +T714C 003:463.698 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:463.714 - 0.015ms returns 0 +T714C 003:463.730 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:463.746 - 0.016ms returns 0 +T714C 003:463.763 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:463.779 - 0.016ms returns 0x000000F0 +T714C 003:463.795 JLINK_Go() +T714C 003:463.813 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:464.061 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:465.956 - 2.159ms +T714C 003:465.995 JLINK_IsHalted() +T714C 003:466.228 - 0.233ms returns FALSE +T714C 003:466.248 JLINK_HasError() +T714C 003:467.503 JLINK_IsHalted() +T714C 003:469.805 - 2.302ms returns TRUE +T714C 003:469.850 JLINK_ReadReg(R15 (PC)) +T714C 003:469.871 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:470.121 - 0.270ms returns 0x30500000 +T714C 003:470.143 JLINK_ClrBPEx(BPHandle = 0x000000F0) +T714C 003:470.160 - 0.016ms returns 0x00 +T714C 003:470.177 JLINK_ReadReg(R0) +T714C 003:470.197 - 0.020ms returns 0x00000000 +T714C 003:470.822 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:470.855 Data: 69 76 65 21 0D 0A 00 6D 65 6D 20 6D 61 6E 61 67 ... +T714C 003:470.887 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:471.944 - 1.122ms returns 0x100 +T714C 003:471.967 JLINK_HasError() +T714C 003:471.985 JLINK_WriteReg(R0, 0x28017200) +T714C 003:472.003 - 0.018ms returns 0 +T714C 003:472.020 JLINK_WriteReg(R1, 0x00000100) +T714C 003:472.036 - 0.016ms returns 0 +T714C 003:472.054 JLINK_WriteReg(R2, 0x30500674) +T714C 003:472.070 - 0.016ms returns 0 +T714C 003:472.086 JLINK_WriteReg(R3, 0x00000000) +T714C 003:472.101 - 0.015ms returns 0 +T714C 003:472.118 JLINK_WriteReg(R4, 0x00000000) +T714C 003:472.134 - 0.016ms returns 0 +T714C 003:472.150 JLINK_WriteReg(R5, 0x00000000) +T714C 003:472.166 - 0.016ms returns 0 +T714C 003:472.182 JLINK_WriteReg(R6, 0x00000000) +T714C 003:472.198 - 0.016ms returns 0 +T714C 003:472.215 JLINK_WriteReg(R7, 0x00000000) +T714C 003:472.230 - 0.015ms returns 0 +T714C 003:472.246 JLINK_WriteReg(R8, 0x00000000) +T714C 003:472.262 - 0.016ms returns 0 +T714C 003:472.279 JLINK_WriteReg(R9, 0x30500458) +T714C 003:472.294 - 0.015ms returns 0 +T714C 003:472.310 JLINK_WriteReg(R10, 0x00000000) +T714C 003:472.328 - 0.017ms returns 0 +T714C 003:472.344 JLINK_WriteReg(R11, 0x00000000) +T714C 003:472.360 - 0.015ms returns 0 +T714C 003:472.376 JLINK_WriteReg(R12, 0x00000000) +T714C 003:472.392 - 0.015ms returns 0 +T714C 003:472.408 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:472.425 - 0.017ms returns 0 +T714C 003:472.442 JLINK_WriteReg(R14, 0x30500001) +T714C 003:472.458 - 0.015ms returns 0 +T714C 003:472.474 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:472.490 - 0.016ms returns 0 +T714C 003:472.506 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:472.522 - 0.016ms returns 0 +T714C 003:473.113 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:473.134 - 0.020ms returns 0 +T714C 003:473.150 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:473.166 - 0.016ms returns 0 +T714C 003:473.182 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:473.199 - 0.016ms returns 0 +T714C 003:473.216 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:473.232 - 0.016ms returns 0x000000F1 +T714C 003:473.248 JLINK_Go() +T714C 003:473.265 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:473.570 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:475.579 - 2.331ms +T714C 003:475.605 JLINK_IsHalted() +T714C 003:475.833 - 0.228ms returns FALSE +T714C 003:475.854 JLINK_HasError() +T714C 003:477.578 JLINK_IsHalted() +T714C 003:480.027 - 2.449ms returns TRUE +T714C 003:480.074 JLINK_ReadReg(R15 (PC)) +T714C 003:480.094 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:480.356 - 0.281ms returns 0x30500000 +T714C 003:480.377 JLINK_ClrBPEx(BPHandle = 0x000000F1) +T714C 003:480.399 - 0.022ms returns 0x00 +T714C 003:480.418 JLINK_ReadReg(R0) +T714C 003:480.435 - 0.016ms returns 0x00000000 +T714C 003:480.962 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:480.998 Data: 4F 43 50 20 00 4D 53 54 4B 45 52 52 20 00 4D 55 ... +T714C 003:481.028 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:482.035 - 1.071ms returns 0x100 +T714C 003:482.092 JLINK_HasError() +T714C 003:482.110 JLINK_WriteReg(R0, 0x28017300) +T714C 003:482.130 - 0.021ms returns 0 +T714C 003:482.148 JLINK_WriteReg(R1, 0x00000100) +T714C 003:482.164 - 0.016ms returns 0 +T714C 003:482.182 JLINK_WriteReg(R2, 0x30500674) +T714C 003:482.199 - 0.016ms returns 0 +T714C 003:482.216 JLINK_WriteReg(R3, 0x00000000) +T714C 003:482.235 - 0.019ms returns 0 +T714C 003:482.252 JLINK_WriteReg(R4, 0x00000000) +T714C 003:482.268 - 0.015ms returns 0 +T714C 003:482.285 JLINK_WriteReg(R5, 0x00000000) +T714C 003:482.301 - 0.016ms returns 0 +T714C 003:482.317 JLINK_WriteReg(R6, 0x00000000) +T714C 003:482.334 - 0.016ms returns 0 +T714C 003:482.445 JLINK_WriteReg(R7, 0x00000000) +T714C 003:482.504 - 0.058ms returns 0 +T714C 003:482.523 JLINK_WriteReg(R8, 0x00000000) +T714C 003:482.540 - 0.016ms returns 0 +T714C 003:482.556 JLINK_WriteReg(R9, 0x30500458) +T714C 003:482.573 - 0.016ms returns 0 +T714C 003:482.589 JLINK_WriteReg(R10, 0x00000000) +T714C 003:482.606 - 0.017ms returns 0 +T714C 003:482.622 JLINK_WriteReg(R11, 0x00000000) +T714C 003:482.638 - 0.015ms returns 0 +T714C 003:482.654 JLINK_WriteReg(R12, 0x00000000) +T714C 003:482.669 - 0.015ms returns 0 +T714C 003:482.686 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:482.703 - 0.017ms returns 0 +T714C 003:482.720 JLINK_WriteReg(R14, 0x30500001) +T714C 003:482.736 - 0.016ms returns 0 +T714C 003:482.753 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:482.769 - 0.016ms returns 0 +T714C 003:482.785 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:482.801 - 0.016ms returns 0 +T714C 003:482.818 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:482.835 - 0.016ms returns 0 +T714C 003:482.852 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:482.867 - 0.015ms returns 0 +T714C 003:482.884 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:482.900 - 0.016ms returns 0 +T714C 003:482.916 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:482.934 - 0.017ms returns 0x000000F2 +T714C 003:482.951 JLINK_Go() +T714C 003:482.970 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:483.297 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:485.257 - 2.306ms +T714C 003:485.284 JLINK_IsHalted() +T714C 003:485.540 - 0.255ms returns FALSE +T714C 003:485.560 JLINK_HasError() +T714C 003:487.708 JLINK_IsHalted() +T714C 003:490.098 - 2.389ms returns TRUE +T714C 003:490.144 JLINK_ReadReg(R15 (PC)) +T714C 003:490.165 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:490.435 - 0.290ms returns 0x30500000 +T714C 003:490.456 JLINK_ClrBPEx(BPHandle = 0x000000F2) +T714C 003:490.473 - 0.017ms returns 0x00 +T714C 003:490.490 JLINK_ReadReg(R0) +T714C 003:490.506 - 0.016ms returns 0x00000000 +T714C 003:491.065 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:491.099 Data: 74 57 01 28 77 57 01 28 00 00 00 00 51 EA 00 28 ... +T714C 003:491.130 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:492.192 - 1.127ms returns 0x100 +T714C 003:492.217 JLINK_HasError() +T714C 003:492.235 JLINK_WriteReg(R0, 0x28017400) +T714C 003:492.253 - 0.018ms returns 0 +T714C 003:492.270 JLINK_WriteReg(R1, 0x00000100) +T714C 003:492.286 - 0.016ms returns 0 +T714C 003:492.303 JLINK_WriteReg(R2, 0x30500674) +T714C 003:492.319 - 0.016ms returns 0 +T714C 003:492.335 JLINK_WriteReg(R3, 0x00000000) +T714C 003:492.351 - 0.016ms returns 0 +T714C 003:492.367 JLINK_WriteReg(R4, 0x00000000) +T714C 003:492.383 - 0.015ms returns 0 +T714C 003:492.399 JLINK_WriteReg(R5, 0x00000000) +T714C 003:492.414 - 0.015ms returns 0 +T714C 003:492.430 JLINK_WriteReg(R6, 0x00000000) +T714C 003:492.446 - 0.015ms returns 0 +T714C 003:492.462 JLINK_WriteReg(R7, 0x00000000) +T714C 003:492.478 - 0.016ms returns 0 +T714C 003:492.494 JLINK_WriteReg(R8, 0x00000000) +T714C 003:492.510 - 0.015ms returns 0 +T714C 003:492.536 JLINK_WriteReg(R9, 0x30500458) +T714C 003:492.552 - 0.015ms returns 0 +T714C 003:492.568 JLINK_WriteReg(R10, 0x00000000) +T714C 003:492.584 - 0.016ms returns 0 +T714C 003:492.601 JLINK_WriteReg(R11, 0x00000000) +T714C 003:492.616 - 0.015ms returns 0 +T714C 003:492.633 JLINK_WriteReg(R12, 0x00000000) +T714C 003:492.648 - 0.015ms returns 0 +T714C 003:492.665 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:492.681 - 0.016ms returns 0 +T714C 003:492.698 JLINK_WriteReg(R14, 0x30500001) +T714C 003:492.714 - 0.016ms returns 0 +T714C 003:492.730 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:492.746 - 0.015ms returns 0 +T714C 003:492.762 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:492.778 - 0.016ms returns 0 +T714C 003:492.794 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:492.810 - 0.016ms returns 0 +T714C 003:492.826 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:492.842 - 0.015ms returns 0 +T714C 003:492.858 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:492.874 - 0.015ms returns 0 +T714C 003:492.891 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:492.933 - 0.042ms returns 0x000000F3 +T714C 003:492.949 JLINK_Go() +T714C 003:492.967 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:493.257 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:495.162 - 2.212ms +T714C 003:495.185 JLINK_IsHalted() +T714C 003:495.409 - 0.223ms returns FALSE +T714C 003:495.428 JLINK_HasError() +T714C 003:496.663 JLINK_IsHalted() +T714C 003:499.050 - 2.386ms returns TRUE +T714C 003:499.787 JLINK_ReadReg(R15 (PC)) +T714C 003:499.848 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:500.093 - 0.305ms returns 0x30500000 +T714C 003:500.139 JLINK_ClrBPEx(BPHandle = 0x000000F3) +T714C 003:500.157 - 0.018ms returns 0x00 +T714C 003:500.174 JLINK_ReadReg(R0) +T714C 003:500.192 - 0.018ms returns 0x00000000 +T714C 003:500.851 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:500.884 Data: 01 03 00 2B 11 46 9E 46 EE D1 00 20 BC F1 03 0F ... +T714C 003:500.917 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:501.950 - 1.099ms returns 0x100 +T714C 003:501.974 JLINK_HasError() +T714C 003:501.992 JLINK_WriteReg(R0, 0x28017500) +T714C 003:502.010 - 0.018ms returns 0 +T714C 003:502.027 JLINK_WriteReg(R1, 0x00000100) +T714C 003:502.043 - 0.016ms returns 0 +T714C 003:502.059 JLINK_WriteReg(R2, 0x30500674) +T714C 003:502.075 - 0.016ms returns 0 +T714C 003:502.091 JLINK_WriteReg(R3, 0x00000000) +T714C 003:502.107 - 0.015ms returns 0 +T714C 003:502.123 JLINK_WriteReg(R4, 0x00000000) +T714C 003:502.139 - 0.016ms returns 0 +T714C 003:502.156 JLINK_WriteReg(R5, 0x00000000) +T714C 003:502.172 - 0.016ms returns 0 +T714C 003:502.190 JLINK_WriteReg(R6, 0x00000000) +T714C 003:502.207 - 0.016ms returns 0 +T714C 003:502.223 JLINK_WriteReg(R7, 0x00000000) +T714C 003:502.238 - 0.015ms returns 0 +T714C 003:502.255 JLINK_WriteReg(R8, 0x00000000) +T714C 003:502.271 - 0.016ms returns 0 +T714C 003:502.286 JLINK_WriteReg(R9, 0x30500458) +T714C 003:502.302 - 0.015ms returns 0 +T714C 003:502.319 JLINK_WriteReg(R10, 0x00000000) +T714C 003:502.334 - 0.015ms returns 0 +T714C 003:502.350 JLINK_WriteReg(R11, 0x00000000) +T714C 003:502.366 - 0.015ms returns 0 +T714C 003:502.382 JLINK_WriteReg(R12, 0x00000000) +T714C 003:502.398 - 0.015ms returns 0 +T714C 003:502.414 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:502.432 - 0.017ms returns 0 +T714C 003:502.448 JLINK_WriteReg(R14, 0x30500001) +T714C 003:502.464 - 0.015ms returns 0 +T714C 003:502.480 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:502.496 - 0.015ms returns 0 +T714C 003:502.512 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:502.528 - 0.016ms returns 0 +T714C 003:502.544 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:502.559 - 0.015ms returns 0 +T714C 003:502.575 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:502.591 - 0.016ms returns 0 +T714C 003:502.608 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:502.624 - 0.015ms returns 0 +T714C 003:502.640 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:502.657 - 0.017ms returns 0x000000F4 +T714C 003:502.673 JLINK_Go() +T714C 003:502.691 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:502.975 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:504.936 - 2.263ms +T714C 003:504.959 JLINK_IsHalted() +T714C 003:505.209 - 0.249ms returns FALSE +T714C 003:505.228 JLINK_HasError() +T714C 003:506.652 JLINK_IsHalted() +T714C 003:508.831 - 2.179ms returns TRUE +T714C 003:508.853 JLINK_ReadReg(R15 (PC)) +T714C 003:508.870 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:509.121 - 0.267ms returns 0x30500000 +T714C 003:509.145 JLINK_ClrBPEx(BPHandle = 0x000000F4) +T714C 003:509.161 - 0.016ms returns 0x00 +T714C 003:509.177 JLINK_ReadReg(R0) +T714C 003:509.194 - 0.017ms returns 0x00000000 +T714C 003:509.824 JLINK_WriteMem(0x30500674, 0x100 Bytes, ...) +T714C 003:509.860 Data: F0 43 FF F7 59 BF 01 B0 BD E8 F0 83 00 00 00 00 ... +T714C 003:509.889 CPU_WriteMem(256 bytes @ 0x30500674) +T714C 003:510.936 - 1.112ms returns 0x100 +T714C 003:510.971 JLINK_HasError() +T714C 003:510.988 JLINK_WriteReg(R0, 0x28017600) +T714C 003:511.008 - 0.019ms returns 0 +T714C 003:511.025 JLINK_WriteReg(R1, 0x000000E0) +T714C 003:511.040 - 0.015ms returns 0 +T714C 003:511.058 JLINK_WriteReg(R2, 0x30500674) +T714C 003:511.073 - 0.015ms returns 0 +T714C 003:511.090 JLINK_WriteReg(R3, 0x00000000) +T714C 003:511.106 - 0.016ms returns 0 +T714C 003:511.122 JLINK_WriteReg(R4, 0x00000000) +T714C 003:511.138 - 0.016ms returns 0 +T714C 003:511.154 JLINK_WriteReg(R5, 0x00000000) +T714C 003:511.169 - 0.015ms returns 0 +T714C 003:511.185 JLINK_WriteReg(R6, 0x00000000) +T714C 003:511.201 - 0.015ms returns 0 +T714C 003:511.217 JLINK_WriteReg(R7, 0x00000000) +T714C 003:511.233 - 0.015ms returns 0 +T714C 003:511.249 JLINK_WriteReg(R8, 0x00000000) +T714C 003:511.265 - 0.015ms returns 0 +T714C 003:511.281 JLINK_WriteReg(R9, 0x30500458) +T714C 003:511.296 - 0.015ms returns 0 +T714C 003:511.313 JLINK_WriteReg(R10, 0x00000000) +T714C 003:511.329 - 0.015ms returns 0 +T714C 003:511.345 JLINK_WriteReg(R11, 0x00000000) +T714C 003:511.361 - 0.015ms returns 0 +T714C 003:511.377 JLINK_WriteReg(R12, 0x00000000) +T714C 003:511.393 - 0.016ms returns 0 +T714C 003:511.409 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:511.426 - 0.017ms returns 0 +T714C 003:511.443 JLINK_WriteReg(R14, 0x30500001) +T714C 003:511.459 - 0.016ms returns 0 +T714C 003:511.475 JLINK_WriteReg(R15 (PC), 0x305002A4) +T714C 003:511.491 - 0.015ms returns 0 +T714C 003:511.507 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:511.522 - 0.015ms returns 0 +T714C 003:511.539 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:511.554 - 0.015ms returns 0 +T714C 003:511.571 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:511.587 - 0.015ms returns 0 +T714C 003:511.603 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:511.619 - 0.016ms returns 0 +T714C 003:511.636 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:511.652 - 0.016ms returns 0x000000F5 +T714C 003:511.669 JLINK_Go() +T714C 003:511.687 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:511.983 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:514.462 - 2.791ms +T714C 003:514.527 JLINK_IsHalted() +T714C 003:514.834 - 0.307ms returns FALSE +T714C 003:514.881 JLINK_HasError() +T714C 003:516.664 JLINK_IsHalted() +T714C 003:518.888 - 2.223ms returns TRUE +T714C 003:518.913 JLINK_ReadReg(R15 (PC)) +T714C 003:518.934 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:519.208 - 0.294ms returns 0x30500000 +T714C 003:519.255 JLINK_ClrBPEx(BPHandle = 0x000000F5) +T714C 003:519.276 - 0.021ms returns 0x00 +T714C 003:519.294 JLINK_ReadReg(R0) +T714C 003:519.310 - 0.016ms returns 0x00000000 +T714C 003:519.328 JLINK_HasError() +T714C 003:519.345 JLINK_WriteReg(R0, 0x00000002) +T714C 003:519.361 - 0.016ms returns 0 +T714C 003:519.378 JLINK_WriteReg(R1, 0x000000E0) +T714C 003:519.394 - 0.015ms returns 0 +T714C 003:519.410 JLINK_WriteReg(R2, 0x30500674) +T714C 003:519.425 - 0.015ms returns 0 +T714C 003:519.441 JLINK_WriteReg(R3, 0x00000000) +T714C 003:519.457 - 0.015ms returns 0 +T714C 003:519.473 JLINK_WriteReg(R4, 0x00000000) +T714C 003:519.488 - 0.015ms returns 0 +T714C 003:519.505 JLINK_WriteReg(R5, 0x00000000) +T714C 003:519.520 - 0.015ms returns 0 +T714C 003:519.542 JLINK_WriteReg(R6, 0x00000000) +T714C 003:519.560 - 0.018ms returns 0 +T714C 003:519.576 JLINK_WriteReg(R7, 0x00000000) +T714C 003:519.592 - 0.015ms returns 0 +T714C 003:519.608 JLINK_WriteReg(R8, 0x00000000) +T714C 003:519.623 - 0.015ms returns 0 +T714C 003:519.640 JLINK_WriteReg(R9, 0x30500458) +T714C 003:519.655 - 0.015ms returns 0 +T714C 003:519.671 JLINK_WriteReg(R10, 0x00000000) +T714C 003:519.686 - 0.015ms returns 0 +T714C 003:519.702 JLINK_WriteReg(R11, 0x00000000) +T714C 003:519.718 - 0.015ms returns 0 +T714C 003:519.736 JLINK_WriteReg(R12, 0x00000000) +T714C 003:519.752 - 0.016ms returns 0 +T714C 003:519.768 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:519.785 - 0.016ms returns 0 +T714C 003:519.802 JLINK_WriteReg(R14, 0x30500001) +T714C 003:519.818 - 0.015ms returns 0 +T714C 003:519.834 JLINK_WriteReg(R15 (PC), 0x30500254) +T714C 003:519.850 - 0.016ms returns 0 +T714C 003:519.867 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:519.882 - 0.015ms returns 0 +T714C 003:519.898 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:519.913 - 0.015ms returns 0 +T714C 003:519.929 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:519.945 - 0.015ms returns 0 +T714C 003:519.961 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:519.977 - 0.015ms returns 0 +T714C 003:519.993 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:520.009 - 0.016ms returns 0x000000F6 +T714C 003:520.025 JLINK_Go() +T714C 003:520.044 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:520.388 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:522.546 - 2.520ms +T714C 003:522.594 JLINK_IsHalted() +T714C 003:524.769 - 2.174ms returns TRUE +T714C 003:524.823 JLINK_ReadReg(R15 (PC)) +T714C 003:524.843 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:525.176 - 0.352ms returns 0x30500000 +T714C 003:525.232 JLINK_ClrBPEx(BPHandle = 0x000000F6) +T714C 003:525.250 - 0.019ms returns 0x00 +T714C 003:525.269 JLINK_ReadReg(R0) +T714C 003:525.287 - 0.018ms returns 0x00000000 +T714C 003:583.469 JLINK_WriteMem(0x30500000, 0x460 Bytes, ...) +T714C 003:583.504 Data: 00 BE 0A E0 0D 78 2D 06 68 40 08 24 40 00 00 D3 ... +T714C 003:583.540 CPU_WriteMem(1120 bytes @ 0x30500000) +T714C 003:587.156 - 3.686ms returns 0x460 +T714C 003:587.279 JLINK_HasError() +T714C 003:587.299 JLINK_WriteReg(R0, 0x28000000) +T714C 003:587.321 - 0.022ms returns 0 +T714C 003:587.338 JLINK_WriteReg(R1, 0x01F78A40) +T714C 003:587.354 - 0.016ms returns 0 +T714C 003:587.370 JLINK_WriteReg(R2, 0x00000003) +T714C 003:587.386 - 0.016ms returns 0 +T714C 003:587.402 JLINK_WriteReg(R3, 0x00000000) +T714C 003:587.418 - 0.015ms returns 0 +T714C 003:587.434 JLINK_WriteReg(R4, 0x00000000) +T714C 003:587.450 - 0.016ms returns 0 +T714C 003:587.467 JLINK_WriteReg(R5, 0x00000000) +T714C 003:587.482 - 0.015ms returns 0 +T714C 003:587.499 JLINK_WriteReg(R6, 0x00000000) +T714C 003:587.514 - 0.015ms returns 0 +T714C 003:587.530 JLINK_WriteReg(R7, 0x00000000) +T714C 003:587.546 - 0.015ms returns 0 +T714C 003:587.562 JLINK_WriteReg(R8, 0x00000000) +T714C 003:587.578 - 0.015ms returns 0 +T714C 003:587.594 JLINK_WriteReg(R9, 0x30500458) +T714C 003:587.610 - 0.015ms returns 0 +T714C 003:587.626 JLINK_WriteReg(R10, 0x00000000) +T714C 003:587.643 - 0.016ms returns 0 +T714C 003:587.689 JLINK_WriteReg(R11, 0x00000000) +T714C 003:587.709 - 0.019ms returns 0 +T714C 003:587.726 JLINK_WriteReg(R12, 0x00000000) +T714C 003:587.742 - 0.016ms returns 0 +T714C 003:587.760 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:587.777 - 0.017ms returns 0 +T714C 003:587.793 JLINK_WriteReg(R14, 0x30500001) +T714C 003:587.809 - 0.015ms returns 0 +T714C 003:587.826 JLINK_WriteReg(R15 (PC), 0x30500038) +T714C 003:587.848 - 0.022ms returns 0 +T714C 003:587.864 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:587.880 - 0.015ms returns 0 +T714C 003:587.897 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:587.913 - 0.015ms returns 0 +T714C 003:587.930 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:587.946 - 0.016ms returns 0 +T714C 003:587.962 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:587.978 - 0.016ms returns 0 +T714C 003:587.996 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:588.019 - 0.023ms returns 0x000000F7 +T714C 003:588.037 JLINK_Go() +T714C 003:588.058 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:588.428 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:590.600 - 2.563ms +T714C 003:590.654 JLINK_IsHalted() +T714C 003:590.923 - 0.268ms returns FALSE +T714C 003:590.970 JLINK_HasError() +T714C 003:594.425 JLINK_IsHalted() +T714C 003:597.214 - 2.788ms returns TRUE +T714C 003:597.259 JLINK_ReadReg(R15 (PC)) +T714C 003:597.279 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:597.706 - 0.446ms returns 0x30500000 +T714C 003:597.754 JLINK_ClrBPEx(BPHandle = 0x000000F7) +T714C 003:597.774 - 0.020ms returns 0x00 +T714C 003:597.790 JLINK_ReadReg(R0) +T714C 003:597.806 - 0.015ms returns 0x00000000 +T714C 003:597.821 JLINK_HasError() +T714C 003:597.837 JLINK_WriteReg(R0, 0xFFFFFFFF) +T714C 003:597.852 - 0.015ms returns 0 +T714C 003:597.868 JLINK_WriteReg(R1, 0x28000400) +T714C 003:597.883 - 0.014ms returns 0 +T714C 003:597.898 JLINK_WriteReg(R2, 0x00000CA0) +T714C 003:597.912 - 0.014ms returns 0 +T714C 003:597.927 JLINK_WriteReg(R3, 0x04C11DB7) +T714C 003:597.941 - 0.014ms returns 0 +T714C 003:597.956 JLINK_WriteReg(R4, 0x00000000) +T714C 003:597.973 - 0.016ms returns 0 +T714C 003:597.989 JLINK_WriteReg(R5, 0x00000000) +T714C 003:598.003 - 0.014ms returns 0 +T714C 003:598.017 JLINK_WriteReg(R6, 0x00000000) +T714C 003:598.032 - 0.014ms returns 0 +T714C 003:598.046 JLINK_WriteReg(R7, 0x00000000) +T714C 003:598.060 - 0.013ms returns 0 +T714C 003:598.075 JLINK_WriteReg(R8, 0x00000000) +T714C 003:598.089 - 0.014ms returns 0 +T714C 003:598.104 JLINK_WriteReg(R9, 0x30500458) +T714C 003:598.118 - 0.013ms returns 0 +T714C 003:598.132 JLINK_WriteReg(R10, 0x00000000) +T714C 003:598.146 - 0.014ms returns 0 +T714C 003:598.160 JLINK_WriteReg(R11, 0x00000000) +T714C 003:598.174 - 0.014ms returns 0 +T714C 003:598.189 JLINK_WriteReg(R12, 0x00000000) +T714C 003:598.203 - 0.014ms returns 0 +T714C 003:598.228 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:598.245 - 0.017ms returns 0 +T714C 003:598.261 JLINK_WriteReg(R14, 0x30500001) +T714C 003:598.276 - 0.015ms returns 0 +T714C 003:598.292 JLINK_WriteReg(R15 (PC), 0x30500002) +T714C 003:598.307 - 0.015ms returns 0 +T714C 003:598.323 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:598.338 - 0.015ms returns 0 +T714C 003:598.355 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:598.371 - 0.015ms returns 0 +T714C 003:598.387 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:598.403 - 0.016ms returns 0 +T714C 003:598.419 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:598.435 - 0.016ms returns 0 +T714C 003:598.450 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:598.464 - 0.014ms returns 0x000000F8 +T714C 003:598.479 JLINK_Go() +T714C 003:598.495 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:598.856 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:601.234 - 2.754ms +T714C 003:601.285 JLINK_IsHalted() +T714C 003:601.557 - 0.271ms returns FALSE +T714C 003:601.604 JLINK_HasError() +T714C 003:603.557 JLINK_IsHalted() +T714C 003:603.998 - 0.439ms returns FALSE +T714C 003:604.716 JLINK_HasError() +T714C 003:607.733 JLINK_IsHalted() +T714C 003:608.078 - 0.344ms returns FALSE +T714C 003:608.125 JLINK_HasError() +T714C 003:609.654 JLINK_IsHalted() +T714C 003:609.996 - 0.342ms returns FALSE +T714C 003:610.043 JLINK_HasError() +T714C 003:611.732 JLINK_IsHalted() +T714C 003:612.075 - 0.343ms returns FALSE +T714C 003:612.122 JLINK_HasError() +T714C 003:613.624 JLINK_IsHalted() +T714C 003:616.006 - 2.387ms returns TRUE +T714C 003:616.055 JLINK_ReadReg(R15 (PC)) +T714C 003:616.076 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:616.387 - 0.332ms returns 0x30500000 +T714C 003:616.433 JLINK_ClrBPEx(BPHandle = 0x000000F8) +T714C 003:616.451 - 0.018ms returns 0x00 +T714C 003:616.468 JLINK_ReadReg(R0) +T714C 003:616.486 - 0.017ms returns 0x28F689C0 +T714C 003:617.165 JLINK_HasError() +T714C 003:617.199 JLINK_WriteReg(R0, 0xFFFFFFFF) +T714C 003:617.218 - 0.018ms returns 0 +T714C 003:617.235 JLINK_WriteReg(R1, 0x2800B000) +T714C 003:617.251 - 0.016ms returns 0 +T714C 003:617.267 JLINK_WriteReg(R2, 0x00005000) +T714C 003:617.292 - 0.025ms returns 0 +T714C 003:617.308 JLINK_WriteReg(R3, 0x04C11DB7) +T714C 003:617.323 - 0.015ms returns 0 +T714C 003:617.339 JLINK_WriteReg(R4, 0x00000000) +T714C 003:617.355 - 0.015ms returns 0 +T714C 003:617.372 JLINK_WriteReg(R5, 0x00000000) +T714C 003:617.387 - 0.015ms returns 0 +T714C 003:617.403 JLINK_WriteReg(R6, 0x00000000) +T714C 003:617.419 - 0.015ms returns 0 +T714C 003:617.434 JLINK_WriteReg(R7, 0x00000000) +T714C 003:617.450 - 0.015ms returns 0 +T714C 003:617.466 JLINK_WriteReg(R8, 0x00000000) +T714C 003:617.482 - 0.016ms returns 0 +T714C 003:617.528 JLINK_WriteReg(R9, 0x30500458) +T714C 003:617.544 - 0.016ms returns 0 +T714C 003:617.560 JLINK_WriteReg(R10, 0x00000000) +T714C 003:617.576 - 0.015ms returns 0 +T714C 003:617.592 JLINK_WriteReg(R11, 0x00000000) +T714C 003:617.614 - 0.022ms returns 0 +T714C 003:617.634 JLINK_WriteReg(R12, 0x00000000) +T714C 003:617.649 - 0.015ms returns 0 +T714C 003:617.666 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:617.685 - 0.019ms returns 0 +T714C 003:617.705 JLINK_WriteReg(R14, 0x30500001) +T714C 003:617.728 - 0.022ms returns 0 +T714C 003:617.751 JLINK_WriteReg(R15 (PC), 0x30500002) +T714C 003:617.774 - 0.023ms returns 0 +T714C 003:617.796 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:617.820 - 0.024ms returns 0 +T714C 003:617.846 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:617.871 - 0.024ms returns 0 +T714C 003:617.893 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:617.919 - 0.026ms returns 0 +T714C 003:617.946 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:617.967 - 0.021ms returns 0 +T714C 003:617.985 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:618.003 - 0.018ms returns 0x000000F9 +T714C 003:618.020 JLINK_Go() +T714C 003:618.038 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:618.322 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:620.468 - 2.447ms +T714C 003:620.518 JLINK_IsHalted() +T714C 003:620.778 - 0.259ms returns FALSE +T714C 003:620.800 JLINK_HasError() +T714C 003:622.032 JLINK_IsHalted() +T714C 003:622.308 - 0.276ms returns FALSE +T714C 003:622.328 JLINK_HasError() +T714C 003:624.012 JLINK_IsHalted() +T714C 003:624.290 - 0.277ms returns FALSE +T714C 003:624.312 JLINK_HasError() +T714C 003:626.056 JLINK_IsHalted() +T714C 003:626.336 - 0.279ms returns FALSE +T714C 003:626.356 JLINK_HasError() +T714C 003:627.569 JLINK_IsHalted() +T714C 003:627.827 - 0.259ms returns FALSE +T714C 003:627.847 JLINK_HasError() +T714C 003:629.576 JLINK_IsHalted() +T714C 003:629.854 - 0.279ms returns FALSE +T714C 003:629.874 JLINK_HasError() +T714C 003:631.532 JLINK_IsHalted() +T714C 003:631.932 - 0.400ms returns FALSE +T714C 003:631.955 JLINK_HasError() +T714C 003:633.564 JLINK_IsHalted() +T714C 003:633.968 - 0.403ms returns FALSE +T714C 003:634.010 JLINK_HasError() +T714C 003:635.555 JLINK_IsHalted() +T714C 003:635.828 - 0.271ms returns FALSE +T714C 003:635.875 JLINK_HasError() +T714C 003:637.601 JLINK_IsHalted() +T714C 003:637.858 - 0.257ms returns FALSE +T714C 003:637.878 JLINK_HasError() +T714C 003:639.595 JLINK_IsHalted() +T714C 003:639.840 - 0.245ms returns FALSE +T714C 003:639.860 JLINK_HasError() +T714C 003:641.596 JLINK_IsHalted() +T714C 003:641.858 - 0.261ms returns FALSE +T714C 003:641.879 JLINK_HasError() +T714C 003:643.696 JLINK_IsHalted() +T714C 003:644.138 - 0.441ms returns FALSE +T714C 003:644.222 JLINK_HasError() +T714C 003:645.570 JLINK_IsHalted() +T714C 003:645.834 - 0.263ms returns FALSE +T714C 003:645.855 JLINK_HasError() +T714C 003:647.583 JLINK_IsHalted() +T714C 003:647.875 - 0.293ms returns FALSE +T714C 003:647.926 JLINK_HasError() +T714C 003:649.572 JLINK_IsHalted() +T714C 003:649.945 - 0.371ms returns FALSE +T714C 003:649.976 JLINK_HasError() +T714C 003:651.563 JLINK_IsHalted() +T714C 003:651.825 - 0.261ms returns FALSE +T714C 003:651.845 JLINK_HasError() +T714C 003:653.599 JLINK_IsHalted() +T714C 003:653.865 - 0.267ms returns FALSE +T714C 003:653.886 JLINK_HasError() +T714C 003:655.561 JLINK_IsHalted() +T714C 003:655.852 - 0.290ms returns FALSE +T714C 003:656.494 JLINK_HasError() +T714C 003:658.606 JLINK_IsHalted() +T714C 003:658.860 - 0.253ms returns FALSE +T714C 003:658.880 JLINK_HasError() +T714C 003:660.597 JLINK_IsHalted() +T714C 003:660.824 - 0.226ms returns FALSE +T714C 003:660.845 JLINK_HasError() +T714C 003:662.593 JLINK_IsHalted() +T714C 003:662.938 - 0.344ms returns FALSE +T714C 003:662.984 JLINK_HasError() +T714C 003:664.646 JLINK_IsHalted() +T714C 003:665.119 - 0.471ms returns FALSE +T714C 003:665.178 JLINK_HasError() +T714C 003:667.206 JLINK_IsHalted() +T714C 003:667.544 - 0.337ms returns FALSE +T714C 003:667.566 JLINK_HasError() +T714C 003:669.195 JLINK_IsHalted() +T714C 003:669.473 - 0.279ms returns FALSE +T714C 003:669.494 JLINK_HasError() +T714C 003:671.196 JLINK_IsHalted() +T714C 003:671.478 - 0.283ms returns FALSE +T714C 003:671.499 JLINK_HasError() +T714C 003:673.198 JLINK_IsHalted() +T714C 003:673.486 - 0.289ms returns FALSE +T714C 003:673.508 JLINK_HasError() +T714C 003:675.219 JLINK_IsHalted() +T714C 003:675.649 - 0.429ms returns FALSE +T714C 003:675.678 JLINK_HasError() +T714C 003:677.332 JLINK_IsHalted() +T714C 003:677.704 - 0.372ms returns FALSE +T714C 003:677.741 JLINK_HasError() +T714C 003:679.494 JLINK_IsHalted() +T714C 003:679.786 - 0.291ms returns FALSE +T714C 003:679.807 JLINK_HasError() +T714C 003:681.504 JLINK_IsHalted() +T714C 003:681.750 - 0.246ms returns FALSE +T714C 003:681.794 JLINK_HasError() +T714C 003:683.532 JLINK_IsHalted() +T714C 003:683.844 - 0.310ms returns FALSE +T714C 003:683.879 JLINK_HasError() +T714C 003:685.564 JLINK_IsHalted() +T714C 003:685.971 - 0.406ms returns FALSE +T714C 003:686.019 JLINK_HasError() +T714C 003:687.519 JLINK_IsHalted() +T714C 003:687.830 - 0.311ms returns FALSE +T714C 003:687.855 JLINK_HasError() +T714C 003:689.644 JLINK_IsHalted() +T714C 003:690.075 - 0.431ms returns FALSE +T714C 003:690.125 JLINK_HasError() +T714C 003:691.616 JLINK_IsHalted() +T714C 003:693.814 - 2.196ms returns TRUE +T714C 003:693.864 JLINK_ReadReg(R15 (PC)) +T714C 003:693.888 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:694.216 - 0.351ms returns 0x30500000 +T714C 003:694.267 JLINK_ClrBPEx(BPHandle = 0x000000F9) +T714C 003:694.286 - 0.018ms returns 0x00 +T714C 003:694.302 JLINK_ReadReg(R0) +T714C 003:694.320 - 0.017ms returns 0x54CE763E +T714C 003:695.489 JLINK_HasError() +T714C 003:695.522 JLINK_WriteReg(R0, 0xFFFFFFFF) +T714C 003:695.542 - 0.019ms returns 0 +T714C 003:695.560 JLINK_WriteReg(R1, 0x28010000) +T714C 003:695.576 - 0.015ms returns 0 +T714C 003:695.592 JLINK_WriteReg(R2, 0x000076E0) +T714C 003:695.608 - 0.016ms returns 0 +T714C 003:695.624 JLINK_WriteReg(R3, 0x04C11DB7) +T714C 003:695.639 - 0.015ms returns 0 +T714C 003:695.658 JLINK_WriteReg(R4, 0x00000000) +T714C 003:695.673 - 0.015ms returns 0 +T714C 003:695.689 JLINK_WriteReg(R5, 0x00000000) +T714C 003:695.704 - 0.015ms returns 0 +T714C 003:695.720 JLINK_WriteReg(R6, 0x00000000) +T714C 003:695.736 - 0.015ms returns 0 +T714C 003:695.752 JLINK_WriteReg(R7, 0x00000000) +T714C 003:695.768 - 0.016ms returns 0 +T714C 003:695.784 JLINK_WriteReg(R8, 0x00000000) +T714C 003:695.800 - 0.015ms returns 0 +T714C 003:695.840 JLINK_WriteReg(R9, 0x30500458) +T714C 003:695.857 - 0.016ms returns 0 +T714C 003:695.874 JLINK_WriteReg(R10, 0x00000000) +T714C 003:695.892 - 0.017ms returns 0 +T714C 003:695.909 JLINK_WriteReg(R11, 0x00000000) +T714C 003:695.924 - 0.015ms returns 0 +T714C 003:695.951 JLINK_WriteReg(R12, 0x00000000) +T714C 003:695.968 - 0.017ms returns 0 +T714C 003:695.988 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:696.006 - 0.017ms returns 0 +T714C 003:696.022 JLINK_WriteReg(R14, 0x30500001) +T714C 003:696.040 - 0.017ms returns 0 +T714C 003:696.056 JLINK_WriteReg(R15 (PC), 0x30500002) +T714C 003:696.073 - 0.016ms returns 0 +T714C 003:696.091 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:696.108 - 0.017ms returns 0 +T714C 003:696.127 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:696.144 - 0.016ms returns 0 +T714C 003:696.200 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:696.218 - 0.018ms returns 0 +T714C 003:696.235 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:696.251 - 0.016ms returns 0 +T714C 003:696.269 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:696.295 - 0.025ms returns 0x000000FA +T714C 003:696.312 JLINK_Go() +T714C 003:696.331 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:696.632 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:698.626 - 2.313ms +T714C 003:698.664 JLINK_IsHalted() +T714C 003:698.932 - 0.268ms returns FALSE +T714C 003:698.960 JLINK_HasError() +T714C 003:701.932 JLINK_IsHalted() +T714C 003:702.340 - 0.407ms returns FALSE +T714C 003:702.388 JLINK_HasError() +T714C 003:703.953 JLINK_IsHalted() +T714C 003:704.288 - 0.334ms returns FALSE +T714C 003:704.336 JLINK_HasError() +T714C 003:705.927 JLINK_IsHalted() +T714C 003:706.372 - 0.443ms returns FALSE +T714C 003:706.445 JLINK_HasError() +T714C 003:708.692 JLINK_IsHalted() +T714C 003:709.046 - 0.353ms returns FALSE +T714C 003:709.092 JLINK_HasError() +T714C 003:712.012 JLINK_IsHalted() +T714C 003:712.426 - 0.415ms returns FALSE +T714C 003:712.472 JLINK_HasError() +T714C 003:714.039 JLINK_IsHalted() +T714C 003:714.386 - 0.346ms returns FALSE +T714C 003:714.432 JLINK_HasError() +T714C 003:715.968 JLINK_IsHalted() +T714C 003:716.365 - 0.394ms returns FALSE +T714C 003:716.489 JLINK_HasError() +T714C 003:718.442 JLINK_IsHalted() +T714C 003:718.835 - 0.387ms returns FALSE +T714C 003:718.892 JLINK_HasError() +T714C 003:720.432 JLINK_IsHalted() +T714C 003:720.756 - 0.324ms returns FALSE +T714C 003:720.803 JLINK_HasError() +T714C 003:722.425 JLINK_IsHalted() +T714C 003:722.730 - 0.304ms returns FALSE +T714C 003:722.778 JLINK_HasError() +T714C 003:724.705 JLINK_IsHalted() +T714C 003:725.021 - 0.316ms returns FALSE +T714C 003:725.068 JLINK_HasError() +T714C 003:726.834 JLINK_IsHalted() +T714C 003:727.233 - 0.399ms returns FALSE +T714C 003:727.319 JLINK_HasError() +T714C 003:729.381 JLINK_IsHalted() +T714C 003:729.711 - 0.329ms returns FALSE +T714C 003:729.765 JLINK_HasError() +T714C 003:731.379 JLINK_IsHalted() +T714C 003:731.652 - 0.272ms returns FALSE +T714C 003:731.672 JLINK_HasError() +T714C 003:733.404 JLINK_IsHalted() +T714C 003:733.650 - 0.245ms returns FALSE +T714C 003:734.254 JLINK_HasError() +T714C 003:735.370 JLINK_IsHalted() +T714C 003:735.625 - 0.254ms returns FALSE +T714C 003:735.646 JLINK_HasError() +T714C 003:737.376 JLINK_IsHalted() +T714C 003:737.676 - 0.301ms returns FALSE +T714C 003:737.748 JLINK_HasError() +T714C 003:739.705 JLINK_IsHalted() +T714C 003:740.031 - 0.325ms returns FALSE +T714C 003:740.054 JLINK_HasError() +T714C 003:741.736 JLINK_IsHalted() +T714C 003:741.968 - 0.232ms returns FALSE +T714C 003:741.989 JLINK_HasError() +T714C 003:743.724 JLINK_IsHalted() +T714C 003:743.967 - 0.244ms returns FALSE +T714C 003:743.989 JLINK_HasError() +T714C 003:745.719 JLINK_IsHalted() +T714C 003:745.970 - 0.251ms returns FALSE +T714C 003:745.998 JLINK_HasError() +T714C 003:747.728 JLINK_IsHalted() +T714C 003:748.124 - 0.394ms returns FALSE +T714C 003:748.205 JLINK_HasError() +T714C 003:749.732 JLINK_IsHalted() +T714C 003:749.990 - 0.257ms returns FALSE +T714C 003:750.011 JLINK_HasError() +T714C 003:751.726 JLINK_IsHalted() +T714C 003:751.969 - 0.244ms returns FALSE +T714C 003:751.992 JLINK_HasError() +T714C 003:753.723 JLINK_IsHalted() +T714C 003:754.054 - 0.332ms returns FALSE +T714C 003:754.120 JLINK_HasError() +T714C 003:755.695 JLINK_IsHalted() +T714C 003:756.134 - 0.439ms returns FALSE +T714C 003:756.188 JLINK_HasError() +T714C 003:757.699 JLINK_IsHalted() +T714C 003:757.932 - 0.232ms returns FALSE +T714C 003:757.995 JLINK_HasError() +T714C 003:759.685 JLINK_IsHalted() +T714C 003:759.953 - 0.266ms returns FALSE +T714C 003:759.976 JLINK_HasError() +T714C 003:761.789 JLINK_IsHalted() +T714C 003:762.058 - 0.330ms returns FALSE +T714C 003:762.083 JLINK_HasError() +T714C 003:763.724 JLINK_IsHalted() +T714C 003:763.968 - 0.245ms returns FALSE +T714C 003:763.988 JLINK_HasError() +T714C 003:765.683 JLINK_IsHalted() +T714C 003:766.124 - 0.440ms returns FALSE +T714C 003:766.168 JLINK_HasError() +T714C 003:767.733 JLINK_IsHalted() +T714C 003:768.005 - 0.274ms returns FALSE +T714C 003:768.028 JLINK_HasError() +T714C 003:769.798 JLINK_IsHalted() +T714C 003:770.093 - 0.293ms returns FALSE +T714C 003:770.180 JLINK_HasError() +T714C 003:771.911 JLINK_IsHalted() +T714C 003:772.181 - 0.269ms returns FALSE +T714C 003:772.222 JLINK_HasError() +T714C 003:773.912 JLINK_IsHalted() +T714C 003:774.189 - 0.278ms returns FALSE +T714C 003:774.210 JLINK_HasError() +T714C 003:775.909 JLINK_IsHalted() +T714C 003:776.184 - 0.276ms returns FALSE +T714C 003:776.205 JLINK_HasError() +T714C 003:777.907 JLINK_IsHalted() +T714C 003:778.190 - 0.284ms returns FALSE +T714C 003:778.213 JLINK_HasError() +T714C 003:779.865 JLINK_IsHalted() +T714C 003:780.402 - 0.536ms returns FALSE +T714C 003:780.448 JLINK_HasError() +T714C 003:781.863 JLINK_IsHalted() +T714C 003:782.290 - 0.426ms returns FALSE +T714C 003:782.313 JLINK_HasError() +T714C 003:783.876 JLINK_IsHalted() +T714C 003:784.212 - 0.334ms returns FALSE +T714C 003:784.262 JLINK_HasError() +T714C 003:786.785 JLINK_IsHalted() +T714C 003:787.062 - 0.277ms returns FALSE +T714C 003:787.090 JLINK_HasError() +T714C 003:788.796 JLINK_IsHalted() +T714C 003:789.028 - 0.232ms returns FALSE +T714C 003:789.050 JLINK_HasError() +T714C 003:790.837 JLINK_IsHalted() +T714C 003:791.144 - 0.306ms returns FALSE +T714C 003:791.224 JLINK_HasError() +T714C 003:792.804 JLINK_IsHalted() +T714C 003:793.053 - 0.248ms returns FALSE +T714C 003:793.075 JLINK_HasError() +T714C 003:794.795 JLINK_IsHalted() +T714C 003:795.059 - 0.263ms returns FALSE +T714C 003:795.080 JLINK_HasError() +T714C 003:796.792 JLINK_IsHalted() +T714C 003:796.986 - 0.194ms returns FALSE +T714C 003:797.006 JLINK_HasError() +T714C 003:798.793 JLINK_IsHalted() +T714C 003:799.233 - 0.438ms returns FALSE +T714C 003:799.314 JLINK_HasError() +T714C 003:802.003 JLINK_IsHalted() +T714C 003:802.357 - 0.352ms returns FALSE +T714C 003:802.394 JLINK_HasError() +T714C 003:803.997 JLINK_IsHalted() +T714C 003:806.208 - 2.208ms returns TRUE +T714C 003:806.259 JLINK_ReadReg(R15 (PC)) +T714C 003:806.280 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:806.544 - 0.285ms returns 0x30500000 +T714C 003:806.567 JLINK_ClrBPEx(BPHandle = 0x000000FA) +T714C 003:806.584 - 0.017ms returns 0x00 +T714C 003:806.600 JLINK_ReadReg(R0) +T714C 003:806.618 - 0.017ms returns 0x260B3A23 +T714C 003:808.125 JLINK_HasError() +T714C 003:808.165 JLINK_WriteReg(R0, 0x00000003) +T714C 003:808.186 - 0.020ms returns 0 +T714C 003:808.202 JLINK_WriteReg(R1, 0x28010000) +T714C 003:808.219 - 0.016ms returns 0 +T714C 003:808.235 JLINK_WriteReg(R2, 0x000076E0) +T714C 003:808.252 - 0.016ms returns 0 +T714C 003:808.268 JLINK_WriteReg(R3, 0x04C11DB7) +T714C 003:808.297 - 0.028ms returns 0 +T714C 003:808.313 JLINK_WriteReg(R4, 0x00000000) +T714C 003:808.330 - 0.016ms returns 0 +T714C 003:808.346 JLINK_WriteReg(R5, 0x00000000) +T714C 003:808.393 - 0.046ms returns 0 +T714C 003:808.409 JLINK_WriteReg(R6, 0x00000000) +T714C 003:808.425 - 0.015ms returns 0 +T714C 003:808.441 JLINK_WriteReg(R7, 0x00000000) +T714C 003:808.457 - 0.015ms returns 0 +T714C 003:808.473 JLINK_WriteReg(R8, 0x00000000) +T714C 003:808.490 - 0.017ms returns 0 +T714C 003:808.507 JLINK_WriteReg(R9, 0x30500458) +T714C 003:808.523 - 0.016ms returns 0 +T714C 003:808.541 JLINK_WriteReg(R10, 0x00000000) +T714C 003:808.557 - 0.016ms returns 0 +T714C 003:808.573 JLINK_WriteReg(R11, 0x00000000) +T714C 003:808.589 - 0.015ms returns 0 +T714C 003:808.605 JLINK_WriteReg(R12, 0x00000000) +T714C 003:808.621 - 0.015ms returns 0 +T714C 003:808.638 JLINK_WriteReg(R13 (SP), 0x30508000) +T714C 003:808.655 - 0.017ms returns 0 +T714C 003:808.671 JLINK_WriteReg(R14, 0x30500001) +T714C 003:808.687 - 0.015ms returns 0 +T714C 003:808.703 JLINK_WriteReg(R15 (PC), 0x30500254) +T714C 003:808.719 - 0.015ms returns 0 +T714C 003:808.736 JLINK_WriteReg(XPSR, 0x01000000) +T714C 003:808.752 - 0.016ms returns 0 +T714C 003:808.768 JLINK_WriteReg(MSP, 0x30508000) +T714C 003:808.784 - 0.016ms returns 0 +T714C 003:808.800 JLINK_WriteReg(PSP, 0x30508000) +T714C 003:808.816 - 0.015ms returns 0 +T714C 003:808.832 JLINK_WriteReg(CFBP, 0x00000000) +T714C 003:808.848 - 0.015ms returns 0 +T714C 003:808.865 JLINK_SetBPEx(Addr = 0x30500000, Type = 0xFFFFFFF2) +T714C 003:808.888 - 0.022ms returns 0x000000FB +T714C 003:808.906 JLINK_Go() +T714C 003:808.924 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:809.165 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:811.059 - 2.153ms +T714C 003:811.090 JLINK_IsHalted() +T714C 003:813.250 - 2.158ms returns TRUE +T714C 003:813.298 JLINK_ReadReg(R15 (PC)) +T714C 003:813.320 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:813.566 - 0.267ms returns 0x30500000 +T714C 003:813.590 JLINK_ClrBPEx(BPHandle = 0x000000FB) +T714C 003:813.608 - 0.018ms returns 0x00 +T714C 003:813.627 JLINK_ReadReg(R0) +T714C 003:813.646 - 0.018ms returns 0x00000000 +T714C 003:867.636 JLINK_WriteMemEx(0x30500000, 0x00000002 Bytes, Flags = 0x02000000) +T714C 003:867.707 Data: FE E7 +T714C 003:867.745 CPU_WriteMem(2 bytes @ 0x30500000) +T714C 003:868.040 - 0.403ms returns 0x2 +T714C 003:868.098 JLINK_HasError() +T714C 003:868.116 JLINK_HasError() +T714C 003:868.138 JLINK_SetResetType(JLINKARM_CM3_RESET_TYPE_NORMAL) +T714C 003:868.154 - 0.016ms returns JLINKARM_CM3_RESET_TYPE_NORMAL +T714C 003:868.171 JLINK_Reset() +T714C 003:869.745 Memory map 'before startup completion point' is active +T714C 003:871.253 ResetTarget() start +T714C 003:871.311 J-Link Script File: Executing ResetTarget() +T714C 003:872.939 Skipping ResetTarget() +T714C 003:874.408 ResetTarget() end - Took 1.68ms +T714C 003:876.967 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:877.276 CPU_WriteMem(4 bytes @ 0xE0002000) +T714C 003:877.565 CPU_ReadMem(4 bytes @ 0xE000EDFC) +T714C 003:877.778 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:878.027 CPU_ReadMem(4 bytes @ 0xE000EE08) +T714C 003:878.260 - 10.089ms +T714C 003:878.284 JLINK_Go() +T714C 003:878.312 CPU_ReadMem(4 bytes @ 0xE0001000) +T714C 003:878.564 CPU_WriteMem(4 bytes @ 0xE0002008) +T714C 003:878.590 CPU_WriteMem(4 bytes @ 0xE000200C) +T714C 003:878.613 CPU_WriteMem(4 bytes @ 0xE0002010) +T714C 003:878.636 CPU_WriteMem(4 bytes @ 0xE0002014) +T714C 003:878.659 CPU_WriteMem(4 bytes @ 0xE0002018) +T714C 003:878.682 CPU_WriteMem(4 bytes @ 0xE000201C) +T714C 003:878.705 CPU_WriteMem(4 bytes @ 0xE0002020) +T714C 003:878.728 CPU_WriteMem(4 bytes @ 0xE0002024) +T714C 003:879.744 CPU_WriteMem(4 bytes @ 0xE0001004) +T714C 003:882.356 Memory map 'after startup completion point' is active +T714C 003:882.420 - 4.135ms +T714C 003:887.248 JLINK_Close() +T714C 003:888.164 CPU is running +T714C 003:888.224 CPU_WriteMem(4 bytes @ 0xE0002008) +T714C 003:888.566 CPU is running +T714C 003:888.595 CPU_WriteMem(4 bytes @ 0xE000200C) +T714C 003:888.809 CPU is running +T714C 003:888.836 CPU_WriteMem(4 bytes @ 0xE0002010) +T714C 003:889.073 CPU is running +T714C 003:889.100 CPU_WriteMem(4 bytes @ 0xE0002014) +T714C 003:889.377 CPU is running +T714C 003:889.404 CPU_WriteMem(4 bytes @ 0xE0002018) +T714C 003:889.620 CPU is running +T714C 003:889.647 CPU_WriteMem(4 bytes @ 0xE000201C) +T714C 003:889.866 CPU is running +T714C 003:889.894 CPU_WriteMem(4 bytes @ 0xE0002020) +T714C 003:890.135 CPU is running +T714C 003:890.162 CPU_WriteMem(4 bytes @ 0xE0002024) +T714C 003:913.884 - 26.634ms +T714C 003:914.034 +T714C 003:914.054 Closed diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/JLinkSettings.ini b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/JLinkSettings.ini new file mode 100644 index 00000000000..fb02d5216cd --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/JLinkSettings.ini @@ -0,0 +1,47 @@ +[BREAKPOINTS] +ForceImpTypeAny = 0 +ShowInfoWin = 1 +EnableFlashBP = 2 +BPDuringExecution = 0 +[CFI] +CFISize = 0x00 +CFIAddr = 0x00 +[CPU] +MonModeVTableAddr = 0xFFFFFFFF +MonModeDebug = 0 +MaxNumAPs = 0 +LowPowerHandlingMode = 0 +OverrideMemMap = 0 +AllowSimulation = 1 +ScriptFile="" +[FLASH] +RMWThreshold = 0x400 +Loaders="" +EraseType = 0x00 +CacheExcludeSize = 0x00 +CacheExcludeAddr = 0x00 +MinNumBytesFlashDL = 0 +SkipProgOnCRCMatch = 1 +VerifyDownload = 1 +AllowCaching = 1 +EnableFlashDL = 2 +Override = 1 +Device="MIMXRT1189xxx8_M33" +[GENERAL] +WorkRAMSize = 0x00 +WorkRAMAddr = 0x00 +RAMUsageLimit = 0x00 +[SWO] +SWOLogFile="" +[MEM] +RdOverrideOrMask = 0x00 +RdOverrideAndMask = 0xFFFFFFFF +RdOverrideAddr = 0xFFFFFFFF +WrOverrideOrMask = 0x00 +WrOverrideAndMask = 0xFFFFFFFF +WrOverrideAddr = 0xFFFFFFFF +[RAM] +VerifyDownload = 0x00 +[MEM_MAP] +[DYN_MEM_MAP] +NumUserRegion = 0x00 diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/Kconfig b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/Kconfig new file mode 100644 index 00000000000..f94ad65eabc --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/Kconfig @@ -0,0 +1,11 @@ +mainmenu "RT-Thread Configuration" + +RTT_DIR := ../../../../../.. + +PKGS_DIR := packages + +source "$(RTT_DIR)/Kconfig" +osource "$PKGS_DIR/Kconfig" +rsource "../../libraries/Kconfig" +rsource "board/Kconfig" + diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/SConscript b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/SConscript new file mode 100644 index 00000000000..c7ef7659ece --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/SConstruct b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/SConstruct new file mode 100644 index 00000000000..644e0534ecc --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/SConstruct @@ -0,0 +1,88 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +def bsp_pkg_check(): + import subprocess + + check_paths = [ + os.path.join("..", "packages", "nxp-imxrt-sdk-latest"), + ] + + need_update = not all(os.path.exists(p) for p in check_paths) + + if need_update: + print("\n===============================================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") + print("===============================================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT +DefaultEnvironment(tools=[]) +if rtconfig.PLATFORM == 'armcc': + env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, + # overwrite cflags, because cflags has '--C99' + CXXCOM = '$CXX -o $TARGET --cpp -c $CXXFLAGS $_CCCOMCOM $SOURCES') +else: + env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, + CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES') + +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM in ['iccarm']: + env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./..') +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +imxrt_library = 'MIMXRT1180' +rtconfig.BSP_LIBRARY_TYPE = imxrt_library + +# include libraries +objs.extend(SConscript(os.path.join("..", "packages/nxp-imxrt-sdk-latest", imxrt_library, 'SConscript'))) + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/SConscript b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/SConscript new file mode 100644 index 00000000000..050054c59fd --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/SConscript @@ -0,0 +1,22 @@ +import rtconfig +from building import * +import os + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +# add for startup script +if rtconfig.PLATFORM in ['gcc']: + CPPDEFINES = ['__START=entry'] +else: + CPPDEFINES = [] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) + +list = os.listdir(cwd) +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + group = group + SConscript(os.path.join(item, 'SConscript')) + +Return('group') diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/main.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/main.c new file mode 100644 index 00000000000..e984eda8395 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/main.c @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-05-06 tyustli first version + * + */ + +#include +#include +#include +#include + +int main(void) +{ + rt_kprintf("MIMXRT1180_CM33 Hello_World\r\n"); + + while (1) + { + rt_thread_mdelay(500); + } +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/mnt.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/mnt.c new file mode 100644 index 00000000000..bb7a9406502 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/mnt.c @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-09-19 Gavin first version + * + */ + +#include +#ifdef RT_USING_DFS_RAMFS +#include + +extern struct dfs_ramfs *dfs_ramfs_create(rt_uint8_t *pool, rt_size_t size); + +int mnt_init(void) +{ + rt_uint8_t *pool = RT_NULL; + rt_size_t size = 8*1024*1024; + + pool = rt_malloc(size); + if (pool == RT_NULL) + return 0; + + if (dfs_mount(RT_NULL, "/", "ram", 0, (const void *)dfs_ramfs_create(pool, size)) == 0) + rt_kprintf("RAM file system initializated!\n"); + else + rt_kprintf("RAM file system initializate failed!\n"); + + return 0; +} +INIT_ENV_EXPORT(mnt_init); +#endif + +#ifdef BSP_USING_SDCARD_FATFS +#include +#include +#define DBG_TAG "app.filesystem" +#define DBG_LVL DBG_INFO +#include +static int filesystem_mount(void) +{ + while(rt_device_find("sd0") == RT_NULL) + { + rt_thread_mdelay(1); + } + + int ret = dfs_mount("sd0", "/", "elm", 0, 0); + if (ret != 0) + { + rt_kprintf("ret: %d\n",ret); + LOG_E("sd0 mount to '/' failed!"); + return ret; + } + + return RT_EOK; +} +INIT_ENV_EXPORT(filesystem_mount); +#endif diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/Kconfig b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/Kconfig new file mode 100644 index 00000000000..c0d69a291d9 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/Kconfig @@ -0,0 +1,239 @@ +menu "Hardware Drivers Config" + +config BSP_USING_QSPIFLASH + bool + default n + +config SOC_MIMXRT1189CVM8C + bool + select SOC_IMXRT1180_SERIES + select BSP_USING_QSPIFLASH + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +config SOC_MIMXRT1189CVM8C_CM33 + bool + default y + depends on SOC_MIMXRT1189CVM8C + select ARCH_ARM_CORTEX_M33 + select ARCH_ARM_CORTEX_SECURE + +menu "On-chip Peripheral Drivers" + + config BSP_USING_DMA + bool "Enable DMA" + default n + + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + config BSP_USING_RTC + bool "Enable RTC" + select RT_USING_RTC + default n + + config BSP_USING_USB + bool "Enable USB" + select RT_USING_USB_HOST + default n + + if BSP_USING_USB + config BSP_USB0_HOST + bool "Enable USB0" + default n + + config BSP_USB1_HOST + bool "Enable USB1" + default n + endif + + config BSP_USING_SDIO + bool "Enable SDIO" + select RT_USING_SDIO + select RT_USING_DFS + default n + + if BSP_USING_SDIO + config CODE_STORED_ON_SDCARD + bool "Enable Code STORED On SDCARD" + default n + help + "SD CARD work as boot devive" + endif + + menuconfig BSP_USING_LPUART + bool "Enable UART" + select RT_USING_SERIAL + default y + + if BSP_USING_LPUART + config BSP_USING_LPUART1 + bool "Enable LPUART1" + default y + + config BSP_LPUART1_RX_USING_DMA + bool "Enable LPUART1 RX DMA" + depends on BSP_USING_LPUART1 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART1_RX_DMA_CHANNEL + depends on BSP_LPUART1_RX_USING_DMA + int "Set LPUART1 RX DMA channel (0-32)" + default 0 + + config BSP_LPUART1_TX_USING_DMA + bool "Enable LPUART1 TX DMA" + depends on BSP_USING_LPUART1 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART1_TX_DMA_CHANNEL + depends on BSP_LPUART1_TX_USING_DMA + int "Set LPUART1 TX DMA channel (0-32)" + default 1 + + config BSP_USING_LPUART3 + bool "Enable LPUART3" + default n + + config BSP_LPUART3_RX_USING_DMA + bool "Enable LPUART3 RX DMA" + depends on BSP_USING_LPUART3 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART3_RX_DMA_CHANNEL + depends on BSP_LPUART3_RX_USING_DMA + int "Set LPUART3 RX DMA channel (0-32)" + default 0 + + config BSP_LPUART3_TX_USING_DMA + bool "Enable LPUART3 TX DMA" + depends on BSP_USING_LPUART3 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART3_TX_DMA_CHANNEL + depends on BSP_LPUART3_TX_USING_DMA + int "Set LPUART3 TX DMA channel (0-32)" + default 1 + endif + + menuconfig BSP_USING_CAN + bool "Enable CAN" + select RT_USING_CAN + default n + if BSP_USING_CAN + config BSP_USING_CAN3 + bool "Enable FLEXCAN3" + default n + endif + + menuconfig BSP_USING_FLEXSPI + bool "Enable FLEXSPI" + default n + if BSP_USING_FLEXSPI + config BSP_USING_FLEXSPI1 + bool "Enable FLEXSPI1" + default n + config BSP_USING_FLEXSPI2 + bool "Enable FLEXSPI2" + default n + endif +endmenu + +menu "Onboard Peripheral Drivers" + + config BSP_USING_SDRAM + bool "Enable SDRAM" + default n + + menuconfig BSP_USING_ETH + bool "Enable Ethernet" + select RT_USING_NETDEV + select RT_USING_LWIP + default n + + + if BSP_USING_ETH + config BSP_USING_PHY + select RT_USING_PHY + bool "Enable ethernet phy" + default y + + if BSP_USING_PHY + config PHY_USING_KSZ8081 + bool "i.MX RT1189EVK uses ksz8081 phy" + default y + + if PHY_USING_KSZ8081 + config PHY_KSZ8081_ADDRESS + int "Specify address of phy device" + default 2 + + config PHY_RESET_KSZ8081_PORT + int "indicate port of reset" + default 6 + + config PHY_RESET_KSZ8081_PIN + int "indicate pin of reset" + default 12 + + config FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE + bool "Enable the PHY ksz8081 RMII50M mode" + depends on PHY_USING_KSZ8081 + default y + endif + endif + + if BSP_USING_PHY + config PHY_USING_RTL8211F + bool "i.MX RT1189EVK uses rtl8211f phy" + default y + + if PHY_USING_RTL8211F + config PHY_RTL8211F_ADDRESS + int "Specify address of phy device" + default 1 + + config PHY_RESET_RTL8211F_PORT + int "indicate port of reset" + default 5 + + config PHY_RESET_RTL8211F_PIN + int "indicate pin of reset" + default 14 + + endif + endif + endif + + menuconfig BSP_USING_FS + bool "Enable File System" + select RT_USING_DFS_DEVFS + select RT_USING_DFS + default n + + if BSP_USING_FS + config BSP_USING_SDCARD_FATFS + bool "Enable SDCARD (FATFS)" + select BSP_USING_SDIO + select RT_USING_DFS_ELMFAT + default n + endif + +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/clock_config.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/clock_config.c new file mode 100644 index 00000000000..80da6cdf90d --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/clock_config.c @@ -0,0 +1,839 @@ +/* + * Copyright 2022-2025 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * How to setup clock using clock driver functions: + * + * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock. + * + * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock. + * + * 3. Call CLOCK_SetRootClock() to configure corresponding module clock source and divider. + * + */ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v13.0 +processor: MIMXRT1189xxxxx +package_id: MIMXRT1189CVM8C +mcu_data: ksdk2_0 +processor_version: 0.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +#include "clock_config.h" +#include "fsl_misc.h" +#include "fsl_dcdc.h" +#include "fsl_pmu.h" +#include "fsl_clock.h" +#include "fsl_ele_base_api.h" + +#include "fsl_cache.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*FUNCTION********************************************************************** + * + * Function Name : BOARD_FlexspiClockSafeConfig + * Description : FLEXSPI clock source safe configuration weak function. + * Called before clock source configuration. + * Note : Users need override this function to change FLEXSPI clock source to stable source when executing + * code on FLEXSPI memory(XIP). If XIP, the function should runs in RAM and move the FLEXSPI clock source + * to a stable clock to avoid instruction/data fetch issue during clock updating. + *END**************************************************************************/ +__attribute__((weak)) void BOARD_FlexspiClockSafeConfig(void) +{ +} + +/*FUNCTION********************************************************************** + * + * Function Name : BOARD_SetFlexspiClock + * Description : This function should be overridden if executing code on FLEXSPI memory(XIP). + * To Change FLEXSPI clock, should move to run from RAM and then configure FLEXSPI clock source. + * After the clock is changed and stable, move back to run on FLEXSPI. + * Param base : FLEXSPI peripheral base address. + * Param src : FLEXSPI clock source. + * Param divider : FLEXSPI clock divider. + *END**************************************************************************/ +__attribute__((weak)) void BOARD_SetFlexspiClock(FLEXSPI_Type *base, uint8_t src, uint32_t divider) +{ +} + +/*FUNCTION********************************************************************** + * + * Function Name : EdgeLock_SetClock + * Description : Set EdgeLock clock via safe method + * Note : It requires specific sequence to change edgelock clock source, + * otherwise the soc behavior is unpredictable. + *END**************************************************************************/ +__attribute__((weak)) void EdgeLock_SetClock(uint8_t mux, uint8_t div) +{ +} + +/*FUNCTION********************************************************************** + * + * Function Name : DCDC_SetVoltage + * Description : Set DCDC voltage via safe method + * Note : It requires specific sequence to change DCDC voltage when GDET + * is enabled, otherwise the soc behavior is unpredictable. + *END**************************************************************************/ +__attribute__((weak)) void DCDC_SetVoltage(uint8_t core, uint8_t targetVoltage) +{ +} + + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockRUN(); +} + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockRUN +called_from_default_init: true +outputs: +- {id: ACMP_CLK_ROOT.outFreq, value: 240 MHz} +- {id: ADC1_CLK_ROOT.outFreq, value: 80 MHz} +- {id: ADC2_CLK_ROOT.outFreq, value: 80 MHz} +- {id: ARM_PLL_CLK.outFreq, value: 792 MHz} +- {id: ASRC_CLK_ROOT.outFreq, value: 240 MHz} +- {id: BUS_AON_CLK_ROOT.outFreq, value: 132 MHz} +- {id: BUS_WAKEUP_CLK_ROOT.outFreq, value: 132 MHz} +- {id: CAN1_CLK_ROOT.outFreq, value: 80 MHz} +- {id: CAN2_CLK_ROOT.outFreq, value: 80 MHz} +- {id: CAN3_CLK_ROOT.outFreq, value: 80 MHz} +- {id: CCM_CKO1_CLK_ROOT.outFreq, value: 80 MHz} +- {id: CCM_CKO2_CLK_ROOT.outFreq, value: 50 MHz} +- {id: CLK_1M.outFreq, value: 1 MHz} +- {id: ECAT_CLK_ROOT.outFreq, value: 100 MHz} +- {id: ECAT_PORT0_REF_CLK.outFreq, value: 50 MHz} +- {id: ECAT_PORT1_REF_CLK.outFreq, value: 50 MHz} +- {id: EDGELOCK_CLK_ROOT.outFreq, value: 200 MHz} +- {id: ENET_REFCLK_ROOT.outFreq, value: 125 MHz} +- {id: FLEXIO1_CLK_ROOT.outFreq, value: 120 MHz} +- {id: FLEXIO2_CLK_ROOT.outFreq, value: 48 MHz} +- {id: FLEXSPI1_CLK_ROOT.outFreq, value: 1440/11 MHz} +- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 2160/11 MHz} +- {id: FLEXSPI_SLV_CLK_ROOT.outFreq, value: 132 MHz} +- {id: GPT1_CLK_ROOT.outFreq, value: 240 MHz} +- {id: GPT2_CLK_ROOT.outFreq, value: 240 MHz} +- {id: I3C1_CLK_ROOT.outFreq, value: 24 MHz} +- {id: I3C2_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPI2C0102_CLK_ROOT.outFreq, value: 60 MHz} +- {id: LPI2C0304_CLK_ROOT.outFreq, value: 60 MHz} +- {id: LPI2C0506_CLK_ROOT.outFreq, value: 60 MHz} +- {id: LPIT3_CLK_ROOT.outFreq, value: 80 MHz} +- {id: LPSPI0102_CLK_ROOT.outFreq, value: 1440/11 MHz} +- {id: LPSPI0304_CLK_ROOT.outFreq, value: 1440/11 MHz} +- {id: LPSPI0506_CLK_ROOT.outFreq, value: 1440/11 MHz} +- {id: LPTMR1_CLK_ROOT.outFreq, value: 80 MHz} +- {id: LPTMR2_CLK_ROOT.outFreq, value: 80 MHz} +- {id: LPTMR3_CLK_ROOT.outFreq, value: 80 MHz} +- {id: LPUART0102_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART0304_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART0506_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART0708_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART0910_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART1112_CLK_ROOT.outFreq, value: 24 MHz} +- {id: M33_CLK_ROOT.outFreq, value: 240 MHz} +- {id: M33_SYSTICK_CLK_ROOT.outFreq, value: 100 kHz} +- {id: M7_CLK_ROOT.outFreq, value: 792 MHz} +- {id: M7_SYSTICK_CLK_ROOT.outFreq, value: 100 kHz} +- {id: MAC0_CLK_ROOT.outFreq, value: 50 MHz} +- {id: MAC1_CLK_ROOT.outFreq, value: 125 MHz} +- {id: MAC2_CLK_ROOT.outFreq, value: 125 MHz} +- {id: MAC3_CLK_ROOT.outFreq, value: 125 MHz} +- {id: MAC4_CLK_ROOT.outFreq, value: 50 MHz} +- {id: MIC_CLK_ROOT.outFreq, value: 80 MHz} +- {id: NETC_CLK_ROOT.outFreq, value: 240 MHz} +- {id: NETC_PORT0_REF_CLK.outFreq, value: 50 MHz} +- {id: NETC_PORT1_REF_CLK.outFreq, value: 50 MHz} +- {id: NETC_PORT2_REF_CLK.outFreq, value: 50 MHz} +- {id: NETC_PORT3_REF_CLK.outFreq, value: 50 MHz} +- {id: NETC_PORT4_REF_CLK.outFreq, value: 50 MHz} +- {id: OSC_24M.outFreq, value: 24 MHz} +- {id: OSC_32K.outFreq, value: 32.768 kHz} +- {id: OSC_RC_24M.outFreq, value: 24 MHz} +- {id: OSC_RC_400M.outFreq, value: 400 MHz} +- {id: SEMC_CLK_ROOT.outFreq, value: 200 MHz} +- {id: SWO_TRACE_CLK_ROOT.outFreq, value: 80 MHz} +- {id: SYS_PLL1_CLK.outFreq, value: 1 GHz} +- {id: SYS_PLL1_DIV2_CLK.outFreq, value: 500 MHz} +- {id: SYS_PLL1_DIV5_CLK.outFreq, value: 200 MHz} +- {id: SYS_PLL2_CLK.outFreq, value: 528 MHz} +- {id: SYS_PLL2_PFD0_CLK.outFreq, value: 352 MHz} +- {id: SYS_PLL2_PFD1_CLK.outFreq, value: 594 MHz} +- {id: SYS_PLL2_PFD2_CLK.outFreq, value: 396 MHz} +- {id: SYS_PLL2_PFD3_CLK.outFreq, value: 297 MHz} +- {id: SYS_PLL3_CLK.outFreq, value: 480 MHz} +- {id: SYS_PLL3_DIV2_CLK.outFreq, value: 240 MHz} +- {id: SYS_PLL3_PFD0_CLK.outFreq, value: 4320/11 MHz} +- {id: SYS_PLL3_PFD1_CLK.outFreq, value: 2880/11 MHz} +- {id: SYS_PLL3_PFD2_CLK.outFreq, value: 4320/11 MHz} +- {id: SYS_PLL3_PFD3_CLK.outFreq, value: 480 MHz} +- {id: TMR_1588_CLK_ROOT.outFreq, value: 240 MHz} +- {id: TMR_1588_REF_CLK.outFreq, value: 240 MHz} +- {id: TPM2_CLK_ROOT.outFreq, value: 80 MHz} +- {id: TPM4_CLK_ROOT.outFreq, value: 80 MHz} +- {id: TPM5_CLK_ROOT.outFreq, value: 80 MHz} +- {id: TPM6_CLK_ROOT.outFreq, value: 80 MHz} +- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz} +- {id: USDHC2_CLK_ROOT.outFreq, value: 396 MHz} +- {id: WAKEUP_AXI_CLK_ROOT.outFreq, value: 240 MHz} +settings: +- {id: AONDomainVoltage, value: OD} +- {id: CoreClockRootsInitializationConfig, value: selectedCore} +- {id: SOCDomainVoltage, value: OD} +- {id: ANADIG_OSC_OSC_24M_CTRL_LP_EN_CFG, value: Low} +- {id: ANADIG_OSC_OSC_24M_CTRL_OSC_EN_CFG, value: Enabled} +- {id: ANADIG_PLL.ARM_PLL_POST_DIV.scale, value: '2', locked: true} +- {id: ANADIG_PLL.ARM_PLL_PREDIV.scale, value: '1', locked: true} +- {id: ANADIG_PLL.ARM_PLL_VDIV.scale, value: '132', locked: true} +- {id: ANADIG_PLL.PLL_AUDIO_BYPASS.sel, value: ANADIG_OSC.OSC_24M} +- {id: ANADIG_PLL.SYS_PLL2.denom, value: '268435455', locked: true} +- {id: ANADIG_PLL.SYS_PLL2.div, value: '22'} +- {id: ANADIG_PLL.SYS_PLL2.num, value: '0'} +- {id: ANADIG_PLL.SYS_PLL2_SS_DIV.scale, value: '268435455'} +- {id: ANADIG_PLL.SYS_PLL3_PFD0_DIV.scale, value: '22'} +- {id: ANADIG_PLL.SYS_PLL3_PFD1_DIV.scale, value: '33', locked: true} +- {id: ANADIG_PLL.SYS_PLL3_PFD1_MUL.scale, value: '18', locked: true} +- {id: ANADIG_PLL.SYS_PLL3_PFD2_DIV.scale, value: '22', locked: true} +- {id: ANADIG_PLL.SYS_PLL3_PFD2_MUL.scale, value: '18', locked: true} +- {id: ANADIG_PLL.SYS_PLL3_PFD3_DIV.scale, value: '18'} +- {id: ANADIG_PLL_ARM_PLL_CTRL_POWERUP_CFG, value: Enabled} +- {id: ANADIG_PLL_PLL_AUDIO_CTRL_GATE_CFG, value: Disabled} +- {id: ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CFG, value: Enabled} +- {id: ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CFG, value: Enabled} +- {id: ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_CFG, value: Enabled} +- {id: ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_CFG, value: Enabled} +- {id: ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CFG, value: Enabled} +- {id: CCM.CLOCK_ROOT0.DIV.scale, value: '1', locked: true} +- {id: CCM.CLOCK_ROOT0.MUX.sel, value: ANADIG_PLL.ARM_PLL_CLK} +- {id: CCM.CLOCK_ROOT1.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT1.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} +- {id: CCM.CLOCK_ROOT10.DIV.scale, value: '5', locked: true} +- {id: CCM.CLOCK_ROOT10.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT11.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT11.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT12.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT12.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT13.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT13.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT14.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT14.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT15.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT15.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT16.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT16.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT17.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT17.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT18.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT18.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT19.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT2.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT2.MUX.sel, value: ANADIG_OSC.OSC_RC_400M} +- {id: CCM.CLOCK_ROOT20.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT21.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT21.MUX.sel, value: ANADIG_PLL.SYS_PLL3_PFD0_CLK} +- {id: CCM.CLOCK_ROOT22.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT22.MUX.sel, value: ANADIG_PLL.SYS_PLL3_PFD2_CLK} +- {id: CCM.CLOCK_ROOT23.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT23.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK} +- {id: CCM.CLOCK_ROOT24.DIV.scale, value: '6', locked: true} +- {id: CCM.CLOCK_ROOT24.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} +- {id: CCM.CLOCK_ROOT25.DIV.scale, value: '6', locked: true} +- {id: CCM.CLOCK_ROOT25.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} +- {id: CCM.CLOCK_ROOT26.DIV.scale, value: '6', locked: true} +- {id: CCM.CLOCK_ROOT26.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} +- {id: CCM.CLOCK_ROOT27.DIV.scale, value: '10', locked: true} +- {id: CCM.CLOCK_ROOT27.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT28.DIV.scale, value: '10', locked: true} +- {id: CCM.CLOCK_ROOT28.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT29.DIV.scale, value: '10', locked: true} +- {id: CCM.CLOCK_ROOT29.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT3.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT3.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK} +- {id: CCM.CLOCK_ROOT30.DIV.scale, value: '10', locked: true} +- {id: CCM.CLOCK_ROOT30.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT31.DIV.scale, value: '10', locked: true} +- {id: CCM.CLOCK_ROOT31.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT32.DIV.scale, value: '10', locked: true} +- {id: CCM.CLOCK_ROOT32.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT33.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT33.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT34.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT34.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT35.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT35.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT36.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT36.MUX.sel, value: ANADIG_PLL.SYS_PLL3_PFD1_CLK} +- {id: CCM.CLOCK_ROOT37.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT37.MUX.sel, value: ANADIG_PLL.SYS_PLL3_PFD1_CLK} +- {id: CCM.CLOCK_ROOT38.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT38.MUX.sel, value: ANADIG_PLL.SYS_PLL3_PFD1_CLK} +- {id: CCM.CLOCK_ROOT39.DIV.scale, value: '10', locked: true} +- {id: CCM.CLOCK_ROOT39.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT4.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT4.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK} +- {id: CCM.CLOCK_ROOT40.DIV.scale, value: '10', locked: true} +- {id: CCM.CLOCK_ROOT40.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT41.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT41.MUX.sel, value: ANADIG_PLL.SYS_PLL2_PFD2_CLK} +- {id: CCM.CLOCK_ROOT42.MUX.sel, value: ANADIG_PLL.SYS_PLL2_PFD2_CLK} +- {id: CCM.CLOCK_ROOT43.DIV.scale, value: '5', locked: true} +- {id: CCM.CLOCK_ROOT43.MUX.sel, value: ANADIG_PLL.SYS_PLL1_CLK} +- {id: CCM.CLOCK_ROOT44.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT44.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT45.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT45.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT46.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT46.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} +- {id: CCM.CLOCK_ROOT47.DIV.scale, value: '5', locked: true} +- {id: CCM.CLOCK_ROOT47.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV2_CLK} +- {id: CCM.CLOCK_ROOT48.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT48.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV2_CLK} +- {id: CCM.CLOCK_ROOT49.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT49.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} +- {id: CCM.CLOCK_ROOT5.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT5.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} +- {id: CCM.CLOCK_ROOT50.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT50.MUX.sel, value: ANADIG_PLL.SYS_PLL3_PFD3_CLK} +- {id: CCM.CLOCK_ROOT51.DIV.scale, value: '10', locked: true} +- {id: CCM.CLOCK_ROOT51.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV2_CLK} +- {id: CCM.CLOCK_ROOT52.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT52.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV2_CLK} +- {id: CCM.CLOCK_ROOT53.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT53.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV2_CLK} +- {id: CCM.CLOCK_ROOT54.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT54.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV2_CLK} +- {id: CCM.CLOCK_ROOT55.DIV.scale, value: '10', locked: true} +- {id: CCM.CLOCK_ROOT55.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV2_CLK} +- {id: CCM.CLOCK_ROOT6.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT6.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT65.DIV.scale, value: '12', locked: true} +- {id: CCM.CLOCK_ROOT65.MUX.sel, value: ANADIG_PLL.PLL_AUDIO_CLK} +- {id: CCM.CLOCK_ROOT66.DIV.scale, value: '12', locked: true} +- {id: CCM.CLOCK_ROOT66.MUX.sel, value: ANADIG_PLL.PLL_AUDIO_CLK} +- {id: CCM.CLOCK_ROOT67.DIV.scale, value: '12', locked: true} +- {id: CCM.CLOCK_ROOT67.MUX.sel, value: ANADIG_PLL.PLL_AUDIO_CLK} +- {id: CCM.CLOCK_ROOT68.DIV.scale, value: '12', locked: true} +- {id: CCM.CLOCK_ROOT68.MUX.sel, value: ANADIG_PLL.PLL_AUDIO_CLK} +- {id: CCM.CLOCK_ROOT69.DIV.scale, value: '12', locked: true} +- {id: CCM.CLOCK_ROOT69.MUX.sel, value: ANADIG_PLL.PLL_AUDIO_CLK} +- {id: CCM.CLOCK_ROOT7.DIV.scale, value: '240', locked: true} +- {id: CCM.CLOCK_ROOT7.MUX.sel, value: ANADIG_OSC.OSC_24M} +- {id: CCM.CLOCK_ROOT70.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT70.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} +- {id: CCM.CLOCK_ROOT71.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT71.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT72.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT72.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT73.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT73.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV5_CLK} +- {id: CCM.CLOCK_ROOT8.DIV.scale, value: '240', locked: true} +- {id: CCM.CLOCK_ROOT8.MUX.sel, value: ANADIG_OSC.OSC_24M} +- {id: CCM.CLOCK_ROOT9.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT9.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +sources: +- {id: BLK_CTRL_WAKEUPMIX.ECAT_PORT0_REF_CLK_EXT.outFreq, value: 50 MHz, enabled: true} +- {id: BLK_CTRL_WAKEUPMIX.ECAT_PORT1_REF_CLK_EXT.outFreq, value: 50 MHz, enabled: true} +- {id: BLK_CTRL_WAKEUPMIX.NETC_PORT0_REF_CLK_EXT.outFreq, value: 50 MHz, enabled: true} +- {id: BLK_CTRL_WAKEUPMIX.NETC_PORT1_REF_CLK_EXT.outFreq, value: 50 MHz, enabled: true} +- {id: BLK_CTRL_WAKEUPMIX.NETC_PORT2_REF_CLK_EXT.outFreq, value: 50 MHz, enabled: true} +- {id: BLK_CTRL_WAKEUPMIX.NETC_PORT3_REF_CLK_EXT.outFreq, value: 50 MHz, enabled: true} +- {id: BLK_CTRL_WAKEUPMIX.NETC_PORT4_REF_CLK_EXT.outFreq, value: 50 MHz, enabled: true} +- {id: BLK_CTRL_WAKEUPMIX.SAI1_MCLK_EXT.outFreq, value: 100 kHz} +- {id: BLK_CTRL_WAKEUPMIX.SAI2_MCLK_EXT.outFreq, value: 200 kHz} +- {id: BLK_CTRL_WAKEUPMIX.SAI3_MCLK_EXT.outFreq, value: 300 kHz} +- {id: BLK_CTRL_WAKEUPMIX.SAI4_MCLK_EXT.outFreq, value: 400 kHz} +- {id: BLK_CTRL_WAKEUPMIX.SPDIF_CLK_EXT.outFreq, value: 2 MHz} +- {id: BLK_CTRL_WAKEUPMIX.TMR_1588_REF_CLK_EXT.outFreq, value: 50 MHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/******************************************************************************* + * Variables for BOARD_BootClockRUN configuration + ******************************************************************************/ +const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = { + .postDivider = kCLOCK_PllPostDiv2, /* Post divider, 0 - DIV by 2, 1 - DIV by 4, 2 - DIV by 8, 3 - DIV by 1 */ + .loopDivider = 132, /* PLL Loop divider, Fout = Fin * ( loopDivider / ( 2 * postDivider ) ) */ + }; + +const clock_sys_pll1_config_t sysPll1Config_BOARD_BootClockRUN = { + .pllDiv2En = 1, /* Enable Sys Pll1 divide-by-2 clock or not */ + .pllDiv5En = 1, /* Enable Sys Pll1 divide-by-5 clock or not */ + .ss = NULL, /* Spread spectrum parameter */ + .ssEnable = false, /* Enable spread spectrum or not */ + }; + +const clock_sys_pll2_config_t sysPll2Config_BOARD_BootClockRUN = { + .mfd = 268435455, /* Denominator of spread spectrum */ + .ss = NULL, /* Spread spectrum parameter */ + .ssEnable = false, /* Enable spread spectrum or not */ + }; + +/******************************************************************************* + * Code for BOARD_BootClockRUN configuration + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + clock_root_config_t rootCfg = {0}; + + /* Init OSC RC 400M */ + CLOCK_OSC_EnableOscRc400M(); + + /* Switch both core to OscRC400M first */ +#if (__CORTEX_M == 7) + rootCfg.mux = kCLOCK_M7_ClockRoot_MuxOscRc400M; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg); +#endif + +#if (__CORTEX_M == 33) + /* When FlexSPI2 is used, CM33 root clock must be higher than 1/4 + of FlexSPI2 root clock, so set it to OSC RC 400M(but not OSC RC 24M) + firstly as common setting */ + rootCfg.mux = kCLOCK_M33_ClockRoot_MuxOscRc400M; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_M33, &rootCfg); +#endif + +#if (__CORTEX_M == 7) + DCDC_SetVoltage(kDCDC_CORE0, kDCDC_1P0Target1P125V); + DCDC_SetVoltage(kDCDC_CORE1, kDCDC_1P0Target1P125V); + /* FBB need to be enabled in OverDrive(OD) mode */ + PMU_EnableFBB(ANADIG_PMU, true); +#endif + + /* Config CLK_1M */ + CLOCK_OSC_Set1MHzOutputBehavior(kCLOCK_1MHzOutEnableFreeRunning1Mhz); + + /* Init OSC RC 24M */ + CLOCK_OSC_EnableOscRc24M(true); + + /* Config OSC 24M */ + ANADIG_OSC->OSC_24M_CTRL |= ANADIG_OSC_OSC_24M_CTRL_OSC_EN(1) | ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN(0) | ANADIG_OSC_OSC_24M_CTRL_LP_EN(1) | ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE(0); + /* Wait for 24M OSC to be stable. */ + while (ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK != + (ANADIG_OSC->OSC_24M_CTRL & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK)) + { + } + + /* Call function BOARD_FlexspiClockSafeConfig() to move FlexSPI clock to a stable clock source to avoid + instruction/data fetch issue when updating PLL if XIP(execute code on FLEXSPI memory). */ + BOARD_FlexspiClockSafeConfig(); + + /* Init Arm Pll. */ + CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN); + + /* Init Sys Pll1. */ + CLOCK_InitSysPll1(&sysPll1Config_BOARD_BootClockRUN); + + +#ifndef USE_SDRAM + /* Init Sys Pll2. */ + CLOCK_InitSysPll2(&sysPll2Config_BOARD_BootClockRUN); + /* Init System Pll2 pfd0. */ + CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd0, 27); +#endif + /* Init System Pll2 pfd1. */ + CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd1, 16); + /* Init System Pll2 pfd2. */ + CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd2, 24); + /* Init System Pll2 pfd3. */ + CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd3, 32); + +#ifndef USE_HYPERRAM + /* Init Sys Pll3. */ + CLOCK_InitSysPll3(); +#endif + /* Init System Pll3 pfd0. */ + CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd0, 22); + /* Init System Pll3 pfd1. */ + CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd1, 33); +#ifndef USE_HYPERRAM + /* Init System Pll3 pfd2. */ + CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd2, 22); +#endif + /* Init System Pll3 pfd3. */ + CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd3, 18); + + /* Bypass Audio Pll. */ + CLOCK_SetPllBypass(kCLOCK_PllAudio, true); + /* DeInit Audio Pll. */ + CLOCK_DeinitAudioPll(); + + /* Module clock root configurations. */ + /* Configure M7 using ARM_PLL_CLK */ +#if (__CORTEX_M == 7) + rootCfg.mux = kCLOCK_M7_ClockRoot_MuxArmPllOut; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg); +#endif + + /* Configure M33 using SYS_PLL3_CLK */ +#if (__CORTEX_M == 33) + rootCfg.mux = kCLOCK_M33_ClockRoot_MuxSysPll3Out; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_M33, &rootCfg); +#endif + + /* Configure EDGELOCK using OSC_RC_400M */ + EdgeLock_SetClock(kCLOCK_EDGELOCK_ClockRoot_MuxOscRc400M, 2); + + /* Configure BUS_AON using SYS_PLL2_CLK */ + rootCfg.mux = kCLOCK_BUS_AON_ClockRoot_MuxSysPll2Out; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Bus_Aon, &rootCfg); + + /* Configure BUS_WAKEUP using SYS_PLL2_CLK */ + rootCfg.mux = kCLOCK_BUS_WAKEUP_ClockRoot_MuxSysPll2Out; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Bus_Wakeup, &rootCfg); + + /* Configure WAKEUP_AXI using SYS_PLL3_CLK */ + rootCfg.mux = kCLOCK_WAKEUP_AXI_ClockRoot_MuxSysPll3Out; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Wakeup_Axi, &rootCfg); + + /* Configure SWO_TRACE using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_SWO_TRACE_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Swo_Trace, &rootCfg); + + /* Configure M33_SYSTICK using OSC_24M */ +#if (__CORTEX_M == 33) + rootCfg.mux = kCLOCK_M33_SYSTICK_ClockRoot_MuxOsc24MOut; + rootCfg.div = 240; + CLOCK_SetRootClock(kCLOCK_Root_M33_Systick, &rootCfg); +#endif + + /* Configure M7_SYSTICK using OSC_24M */ +#if (__CORTEX_M == 7) + rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOsc24MOut; + rootCfg.div = 240; + CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg); +#endif + + /* Configure FLEXIO1 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_FLEXIO1_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Flexio1, &rootCfg); + + /* Configure FLEXIO2 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_FLEXIO2_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 5; + CLOCK_SetRootClock(kCLOCK_Root_Flexio2, &rootCfg); + + /* Configure LPIT3 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPIT3_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Lpit3, &rootCfg); + + /* Configure LPTIMER1 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPTIMER1_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Lptimer1, &rootCfg); + + /* Configure LPTIMER2 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPTIMER2_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Lptimer2, &rootCfg); + + /* Configure LPTIMER3 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPTIMER3_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Lptimer3, &rootCfg); + + /* Configure TPM2 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_TPM2_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Tpm2, &rootCfg); + + /* Configure TPM4 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_TPM4_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Tpm4, &rootCfg); + + /* Configure TPM5 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_TPM5_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Tpm5, &rootCfg); + + /* Configure TPM6 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_TPM6_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Tpm6, &rootCfg); + + /* Configure GPT1 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_GPT1_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Gpt1, &rootCfg); + + /* Configure GPT2 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_GPT2_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Gpt2, &rootCfg); + + /* Configure FLEXSPI1 using SYS_PLL3_PFD0_CLK */ + BOARD_SetFlexspiClock(FLEXSPI1, kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll3Pfd0, 3U); + + /* Configure FLEXSPI2 using SYS_PLL3_PFD2_CLK */ +#ifndef USE_HYPERRAM + BOARD_SetFlexspiClock(FLEXSPI2, kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll3Pfd2, 2U); +#endif + + /* Configure FLEXSPI_SLV using SYS_PLL2_CLK */ + rootCfg.mux = kCLOCK_FLEXSPI_SLV_ClockRoot_MuxSysPll2Out; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Flexspi_Slv, &rootCfg); + + /* Configure CAN1 using SYS_PLL3_CLK */ + rootCfg.mux = kCLOCK_CAN1_ClockRoot_MuxSysPll3Out; + rootCfg.div = 6; + CLOCK_SetRootClock(kCLOCK_Root_Can1, &rootCfg); + + /* Configure CAN2 using SYS_PLL3_CLK */ + rootCfg.mux = kCLOCK_CAN2_ClockRoot_MuxSysPll3Out; + rootCfg.div = 6; + CLOCK_SetRootClock(kCLOCK_Root_Can2, &rootCfg); + + /* Configure CAN3 using SYS_PLL3_CLK */ + rootCfg.mux = kCLOCK_CAN3_ClockRoot_MuxSysPll3Out; + rootCfg.div = 6; + CLOCK_SetRootClock(kCLOCK_Root_Can3, &rootCfg); + + /* Configure LPUART0102 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPUART0102_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart0102, &rootCfg); + + /* Configure LPUART0304 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPUART0304_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart0304, &rootCfg); + + /* Configure LPUART0506 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPUART0506_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart0506, &rootCfg); + + /* Configure LPUART0708 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPUART0708_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart0708, &rootCfg); + + /* Configure LPUART0910 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPUART0910_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart0910, &rootCfg); + + /* Configure LPUART1112 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPUART1112_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart1112, &rootCfg); + + /* Configure LPI2C0102 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPI2C0102_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Lpi2c0102, &rootCfg); + + /* Configure LPI2C0304 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPI2C0304_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Lpi2c0304, &rootCfg); + + /* Configure LPI2C0506 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPI2C0506_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Lpi2c0506, &rootCfg); + + /* Configure LPSPI0102 using SYS_PLL3_PFD1_CLK */ + rootCfg.mux = kCLOCK_LPSPI0102_ClockRoot_MuxSysPll3Pfd1; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Lpspi0102, &rootCfg); + + /* Configure LPSPI0304 using SYS_PLL3_PFD1_CLK */ + rootCfg.mux = kCLOCK_LPSPI0304_ClockRoot_MuxSysPll3Pfd1; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Lpspi0304, &rootCfg); + + /* Configure LPSPI0506 using SYS_PLL3_PFD1_CLK */ + rootCfg.mux = kCLOCK_LPSPI0506_ClockRoot_MuxSysPll3Pfd1; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Lpspi0506, &rootCfg); + + /* Configure I3C1 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_I3C1_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_I3c1, &rootCfg); + + /* Configure I3C2 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_I3C2_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_I3c2, &rootCfg); + + /* Configure USDHC1 using SYS_PLL2_PFD2_CLK */ + rootCfg.mux = kCLOCK_USDHC1_ClockRoot_MuxSysPll2Pfd2; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Usdhc1, &rootCfg); + + /* Configure USDHC2 using SYS_PLL2_PFD2_CLK */ + rootCfg.mux = kCLOCK_USDHC2_ClockRoot_MuxSysPll2Pfd2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Usdhc2, &rootCfg); + + /* Configure SEMC using SYS_PLL1_CLK */ +#ifndef USE_SDRAM + rootCfg.mux = kCLOCK_SEMC_ClockRoot_MuxSysPll1Out; + rootCfg.div = 5; + CLOCK_SetRootClock(kCLOCK_Root_Semc, &rootCfg); +#endif + + /* Configure ADC1 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_ADC1_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Adc1, &rootCfg); + + /* Configure ADC2 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_ADC2_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Adc2, &rootCfg); + + /* Configure ACMP using SYS_PLL3_CLK */ + rootCfg.mux = kCLOCK_ACMP_ClockRoot_MuxSysPll3Out; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Acmp, &rootCfg); + + /* Configure ECAT using SYS_PLL1_DIV2_CLK */ + rootCfg.mux = kCLOCK_ECAT_ClockRoot_MuxSysPll1Div2; + rootCfg.div = 5; + CLOCK_SetRootClock(kCLOCK_Root_Ecat, &rootCfg); + + /* Configure ENET using SYS_PLL1_DIV2_CLK */ + rootCfg.mux = kCLOCK_ENET_ClockRoot_MuxSysPll1Div2; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Enet, &rootCfg); + + /* Configure TMR_1588 using SYS_PLL3_CLK */ + rootCfg.mux = kCLOCK_TMR_1588_ClockRoot_MuxSysPll3Out; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Tmr_1588, &rootCfg); + + /* Configure NETC using SYS_PLL3_PFD3_CLK */ + rootCfg.mux = kCLOCK_NETC_ClockRoot_MuxSysPll3Pfd3; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Netc, &rootCfg); + + /* Configure MAC0 using SYS_PLL1_DIV2_CLK */ + rootCfg.mux = kCLOCK_MAC0_ClockRoot_MuxSysPll1Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_Mac0, &rootCfg); + + /* Configure MAC1 using SYS_PLL1_DIV2_CLK */ + rootCfg.mux = kCLOCK_MAC1_ClockRoot_MuxSysPll1Div2; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Mac1, &rootCfg); + + /* Configure MAC2 using SYS_PLL1_DIV2_CLK */ + rootCfg.mux = kCLOCK_MAC2_ClockRoot_MuxSysPll1Div2; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Mac2, &rootCfg); + + /* Configure MAC3 using SYS_PLL1_DIV2_CLK */ + rootCfg.mux = kCLOCK_MAC3_ClockRoot_MuxSysPll1Div2; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Mac3, &rootCfg); + + /* Configure MAC4 using SYS_PLL1_DIV2_CLK */ + rootCfg.mux = kCLOCK_MAC4_ClockRoot_MuxSysPll1Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_Mac4, &rootCfg); + + /* Configure SAI1 using PLL_AUDIO_CLK */ + rootCfg.mux = kCLOCK_SAI1_ClockRoot_MuxAudioPllOut; + rootCfg.div = 12; + CLOCK_SetRootClock(kCLOCK_Root_Sai1, &rootCfg); + + /* Configure SAI2 using PLL_AUDIO_CLK */ + rootCfg.mux = kCLOCK_SAI2_ClockRoot_MuxAudioPllOut; + rootCfg.div = 12; + CLOCK_SetRootClock(kCLOCK_Root_Sai2, &rootCfg); + + /* Configure SAI3 using PLL_AUDIO_CLK */ + rootCfg.mux = kCLOCK_SAI3_ClockRoot_MuxAudioPllOut; + rootCfg.div = 12; + CLOCK_SetRootClock(kCLOCK_Root_Sai3, &rootCfg); + + /* Configure SAI4 using PLL_AUDIO_CLK */ + rootCfg.mux = kCLOCK_SAI4_ClockRoot_MuxAudioPllOut; + rootCfg.div = 12; + CLOCK_SetRootClock(kCLOCK_Root_Sai4, &rootCfg); + + /* Configure SPDIF using PLL_AUDIO_CLK */ + rootCfg.mux = kCLOCK_SPDIF_ClockRoot_MuxAudioPllOut; + rootCfg.div = 12; + CLOCK_SetRootClock(kCLOCK_Root_Spdif, &rootCfg); + + /* Configure ASRC using SYS_PLL3_CLK */ + rootCfg.mux = kCLOCK_ASRC_ClockRoot_MuxSysPll3Out; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Asrc, &rootCfg); + + /* Configure MIC using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_MIC_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Mic, &rootCfg); + + /* Configure CKO1 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_CKO1_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Cko1, &rootCfg); + + /* Configure CKO2 using SYS_PLL1_DIV5_CLK */ + rootCfg.mux = kCLOCK_CKO2_ClockRoot_MuxSysPll1Div5; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Cko2, &rootCfg); + + /* Set SAI MCLK clock source. */ + BLK_CTRL_SetSaiMClkClockSource(BLK_CTRL_WAKEUPMIX, kBLK_CTRL_SAI2MClk3Sel, 0); + BLK_CTRL_SetSaiMClkClockSource(BLK_CTRL_WAKEUPMIX, kBLK_CTRL_SAI3MClk3Sel, 0); + BLK_CTRL_SetSaiMClkClockSource(BLK_CTRL_WAKEUPMIX, kBLK_CTRL_SAI4MClk1Sel, 0); + BLK_CTRL_SetSaiMClkClockSource(BLK_CTRL_WAKEUPMIX, kBLK_CTRL_SAI4MClk2Sel, 0); + BLK_CTRL_SetSaiMClkClockSource(BLK_CTRL_WAKEUPMIX, kBLK_CTRL_SAI4MClk3Sel, 0); + + /* Set ECAT PORT Ref clock source. */ + BLK_CTRL_WAKEUPMIX->ECAT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_RMII_REF_CLK_DIR0_MASK; + BLK_CTRL_WAKEUPMIX->ECAT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_RMII_REF_CLK_DIR1_MASK; + + /* Set NETC PORT Ref clock source. */ + BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT0_RMII_REF_CLK_DIR_MASK; + BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT1_RMII_REF_CLK_DIR_MASK; + BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT2_RMII_REF_CLK_DIR_MASK; + BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT3_RMII_REF_CLK_DIR_MASK; + BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT4_RMII_REF_CLK_DIR_MASK; + + /* Set TMR 1588 Ref clock source. */ + BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG |= BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_TMR_EXT_CLK_SEL_MASK; + +#if (__CORTEX_M == 7) + SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M7); +#else + SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M33); +#endif +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/clock_config.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/clock_config.h new file mode 100644 index 00000000000..ae0e622606d --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/clock_config.h @@ -0,0 +1,366 @@ +/* + * Copyright 2022 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ + +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if __CORTEX_M == 7 + #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 792000000UL /*!< CM7 Core clock frequency: 792000000Hz */ +#else + #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 240000000UL /*!< CM33 Core clock frequency: 240000000Hz */ +#endif + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKRUN_ACMP_CLK_ROOT 240000000UL /* Clock consumers of ACMP_CLK_ROOT output : CMP1, CMP2, CMP3, CMP4 */ +#define BOARD_BOOTCLOCKRUN_ADC1_CLK_ROOT 80000000UL /* Clock consumers of ADC1_CLK_ROOT output : ADC1 */ +#define BOARD_BOOTCLOCKRUN_ADC2_CLK_ROOT 80000000UL /* Clock consumers of ADC2_CLK_ROOT output : ADC2 */ +#define BOARD_BOOTCLOCKRUN_ARM_PLL_CLK 792000000UL /* Clock consumers of ARM_PLL_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_ASRC_CLK_ROOT 240000000UL /* Clock consumers of ASRC_CLK_ROOT output : ASRC */ +#define BOARD_BOOTCLOCKRUN_BUS_AON_CLK_ROOT 132000000UL /* Clock consumers of BUS_AON_CLK_ROOT output : CAN1, CAN3, I3C1, IOMUXC_AON, LPI2C1, LPI2C2, LPIT1, LPSPI1, LPSPI2, LPTMR1, LPUART1, LPUART2, LPUART7, LPUART8, MU2_MUA, MU2_MUB, RTWDOG1, RTWDOG2, RTWDOG3, RTWDOG4, RTWDOG5, SAI1, SEMA1, TPM1, TPM2, TSTMR1_TSTMRA */ +#define BOARD_BOOTCLOCKRUN_BUS_WAKEUP_CLK_ROOT 132000000UL /* Clock consumers of BUS_WAKEUP_CLK_ROOT output : ADC1, ADC2, AOI1, AOI2, AOI3, AOI4, CAN2, CMP1, CMP2, CMP3, CMP4, DAC, EQDC1, EQDC2, EQDC3, EQDC4, EWM, FLEXIO1, FLEXIO2, I3C2, IOMUXC, KPP, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPIT2, LPIT3, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPTMR2, LPTMR3, LPUART10, LPUART11, LPUART12, LPUART3, LPUART4, LPUART5, LPUART6, LPUART9, MECC1, MECC2, MU1_MUA, MU1_MUB, PDM, PWM1, PWM2, PWM3, PWM4, RGPIO2, RGPIO3, RGPIO4, RGPIO5, RGPIO6, RTWDOG3, SAI2, SAI3, SAI4, SEMA2, SINC1, SINC2, SINC3, SPDIF, TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8, TPM3, TPM4, TPM5, TPM6, TSTMR2_TSTMRA, USBPHY1, USBPHY2, USDHC1, USDHC2, XBAR1, XBAR2, XBAR3 */ +#define BOARD_BOOTCLOCKRUN_CAN1_CLK_ROOT 80000000UL /* Clock consumers of CAN1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_CAN2_CLK_ROOT 80000000UL /* Clock consumers of CAN2_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_CAN3_CLK_ROOT 80000000UL /* Clock consumers of CAN3_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_CCM_CKO1_CLK_ROOT 80000000UL /* Clock consumers of CCM_CKO1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_CCM_CKO2_CLK_ROOT 50000000UL /* Clock consumers of CCM_CKO2_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, GPT1, GPT2 */ +#define BOARD_BOOTCLOCKRUN_ECAT_CLK_ROOT 100000000UL /* Clock consumers of ECAT_CLK_ROOT output : ECAT */ +#define BOARD_BOOTCLOCKRUN_ECAT_PORT0_REF_CLK 50000000UL /* Clock consumers of ECAT_PORT0_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_ECAT_PORT1_REF_CLK 50000000UL /* Clock consumers of ECAT_PORT1_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_EDGELOCK_CLK_ROOT 200000000UL /* Clock consumers of EDGELOCK_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_ENET_REFCLK_ROOT 125000000UL /* Clock consumers of ENET_REFCLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 120000000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */ +#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 48000000UL /* Clock consumers of FLEXIO2_CLK_ROOT output : FLEXIO2 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI1_CLK_ROOT 130909090UL /* Clock consumers of FLEXSPI1_CLK_ROOT output : FLEXSPI1 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 196363636UL /* Clock consumers of FLEXSPI2_CLK_ROOT output : FLEXSPI2 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI_SLV_CLK_ROOT 132000000UL /* Clock consumers of FLEXSPI_SLV_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_GPT1_CLK_ROOT 240000000UL /* Clock consumers of GPT1_CLK_ROOT output : GPT1 */ +#define BOARD_BOOTCLOCKRUN_GPT2_CLK_ROOT 240000000UL /* Clock consumers of GPT2_CLK_ROOT output : GPT2 */ +#define BOARD_BOOTCLOCKRUN_I3C1_CLK_ROOT 24000000UL /* Clock consumers of I3C1_CLK_ROOT output : I3C1 */ +#define BOARD_BOOTCLOCKRUN_I3C2_CLK_ROOT 24000000UL /* Clock consumers of I3C2_CLK_ROOT output : I3C2 */ +#define BOARD_BOOTCLOCKRUN_LPI2C0102_CLK_ROOT 60000000UL /* Clock consumers of LPI2C0102_CLK_ROOT output : LPI2C1, LPI2C2 */ +#define BOARD_BOOTCLOCKRUN_LPI2C0304_CLK_ROOT 60000000UL /* Clock consumers of LPI2C0304_CLK_ROOT output : LPI2C3, LPI2C4 */ +#define BOARD_BOOTCLOCKRUN_LPI2C0506_CLK_ROOT 60000000UL /* Clock consumers of LPI2C0506_CLK_ROOT output : LPI2C5, LPI2C6 */ +#define BOARD_BOOTCLOCKRUN_LPIT3_CLK_ROOT 80000000UL /* Clock consumers of LPIT3_CLK_ROOT output : LPIT3 */ +#define BOARD_BOOTCLOCKRUN_LPSPI0102_CLK_ROOT 130909090UL /* Clock consumers of LPSPI0102_CLK_ROOT output : LPSPI1, LPSPI2 */ +#define BOARD_BOOTCLOCKRUN_LPSPI0304_CLK_ROOT 130909090UL /* Clock consumers of LPSPI0304_CLK_ROOT output : LPSPI3, LPSPI4 */ +#define BOARD_BOOTCLOCKRUN_LPSPI0506_CLK_ROOT 130909090UL /* Clock consumers of LPSPI0506_CLK_ROOT output : LPSPI5, LPSPI6 */ +#define BOARD_BOOTCLOCKRUN_LPTMR1_CLK_ROOT 80000000UL /* Clock consumers of LPTMR1_CLK_ROOT output : LPTMR1 */ +#define BOARD_BOOTCLOCKRUN_LPTMR2_CLK_ROOT 80000000UL /* Clock consumers of LPTMR2_CLK_ROOT output : LPTMR2 */ +#define BOARD_BOOTCLOCKRUN_LPTMR3_CLK_ROOT 80000000UL /* Clock consumers of LPTMR3_CLK_ROOT output : LPTMR3 */ +#define BOARD_BOOTCLOCKRUN_LPUART0102_CLK_ROOT 24000000UL /* Clock consumers of LPUART0102_CLK_ROOT output : LPUART1, LPUART2 */ +#define BOARD_BOOTCLOCKRUN_LPUART0304_CLK_ROOT 24000000UL /* Clock consumers of LPUART0304_CLK_ROOT output : LPUART3, LPUART4 */ +#define BOARD_BOOTCLOCKRUN_LPUART0506_CLK_ROOT 24000000UL /* Clock consumers of LPUART0506_CLK_ROOT output : LPUART5, LPUART6 */ +#define BOARD_BOOTCLOCKRUN_LPUART0708_CLK_ROOT 24000000UL /* Clock consumers of LPUART0708_CLK_ROOT output : LPUART7, LPUART8 */ +#define BOARD_BOOTCLOCKRUN_LPUART0910_CLK_ROOT 24000000UL /* Clock consumers of LPUART0910_CLK_ROOT output : LPUART10, LPUART9 */ +#define BOARD_BOOTCLOCKRUN_LPUART1112_CLK_ROOT 24000000UL /* Clock consumers of LPUART1112_CLK_ROOT output : LPUART11, LPUART12 */ +#define BOARD_BOOTCLOCKRUN_M33_CLK_ROOT 240000000UL /* Clock consumers of M33_CLK_ROOT output : ARM, DMA3, FLEXSPI2, RGPIO1, SysTick0 */ +#define BOARD_BOOTCLOCKRUN_M33_SYSTICK_CLK_ROOT 100000UL /* Clock consumers of M33_SYSTICK_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_M7_CLK_ROOT 792000000UL /* Clock consumers of M7_CLK_ROOT output : ARM, SysTick1 */ +#define BOARD_BOOTCLOCKRUN_M7_SYSTICK_CLK_ROOT 100000UL /* Clock consumers of M7_SYSTICK_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_MAC0_CLK_ROOT 50000000UL /* Clock consumers of MAC0_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_MAC1_CLK_ROOT 125000000UL /* Clock consumers of MAC1_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_MAC2_CLK_ROOT 125000000UL /* Clock consumers of MAC2_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_MAC3_CLK_ROOT 125000000UL /* Clock consumers of MAC3_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_MAC4_CLK_ROOT 50000000UL /* Clock consumers of MAC4_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_MIC_CLK_ROOT 80000000UL /* Clock consumers of MIC_CLK_ROOT output : PDM, SPDIF */ +#define BOARD_BOOTCLOCKRUN_NETC_CLK_ROOT 240000000UL /* Clock consumers of NETC_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_NETC_PORT0_REF_CLK 50000000UL /* Clock consumers of NETC_PORT0_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_NETC_PORT1_REF_CLK 50000000UL /* Clock consumers of NETC_PORT1_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_NETC_PORT2_REF_CLK 50000000UL /* Clock consumers of NETC_PORT2_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_NETC_PORT3_REF_CLK 50000000UL /* Clock consumers of NETC_PORT3_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_NETC_PORT4_REF_CLK 50000000UL /* Clock consumers of NETC_PORT4_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_OSC_24M 24000000UL /* Clock consumers of OSC_24M output : CAN1, CAN2, CAN3, DAC, GPT1, GPT2, SPDIF, TMPSNS */ +#define BOARD_BOOTCLOCKRUN_OSC_32K 32768UL /* Clock consumers of OSC_32K output : CMP1, CMP2, CMP3, CMP4, EWM, GPT1, GPT2, KPP, LPTMR1, LPTMR2, LPTMR3, RTWDOG1, RTWDOG2, RTWDOG3, RTWDOG4, RTWDOG5, USBPHY1, USBPHY2, USB_OTG1, USB_OTG2, USDHC1, USDHC2 */ +#define BOARD_BOOTCLOCKRUN_OSC_RC_24M 24000000UL /* Clock consumers of OSC_RC_24M output : DCDC, EWM, RTWDOG1, RTWDOG2, RTWDOG3, RTWDOG4, RTWDOG5 */ +#define BOARD_BOOTCLOCKRUN_OSC_RC_400M 400000000UL /* Clock consumers of OSC_RC_400M output : N/A */ +#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_CLK 0UL /* Clock consumers of PLL_AUDIO_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_MODULATION 0UL /* Clock consumers of PLL_AUDIO_SS_MODULATION output : N/A */ +#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_RANGE 0UL /* Clock consumers of PLL_AUDIO_SS_RANGE output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 0UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 0UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 0UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 0UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 0UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 0UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 0UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 0UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 0UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI4_CLK_ROOT 0UL /* Clock consumers of SAI4_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI4_MCLK1 0UL /* Clock consumers of SAI4_MCLK1 output : SAI4 */ +#define BOARD_BOOTCLOCKRUN_SAI4_MCLK2 0UL /* Clock consumers of SAI4_MCLK2 output : SAI4 */ +#define BOARD_BOOTCLOCKRUN_SAI4_MCLK3 0UL /* Clock consumers of SAI4_MCLK3 output : SAI4 */ +#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 200000000UL /* Clock consumers of SEMC_CLK_ROOT output : SEMC */ +#define BOARD_BOOTCLOCKRUN_SPDIF_CLK_ROOT 0UL /* Clock consumers of SPDIF_CLK_ROOT output : SPDIF */ +#define BOARD_BOOTCLOCKRUN_SPDIF_EXTCLK_OUT 0UL /* Clock consumers of SPDIF_EXTCLK_OUT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SWO_TRACE_CLK_ROOT 80000000UL /* Clock consumers of SWO_TRACE_CLK_ROOT output : ARM */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_CLK 1000000000UL /* Clock consumers of SYS_PLL1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV2_CLK 500000000UL /* Clock consumers of SYS_PLL1_DIV2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV5_CLK 200000000UL /* Clock consumers of SYS_PLL1_DIV5_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_MODULATION 0UL /* Clock consumers of SYS_PLL1_SS_MODULATION output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_RANGE 0UL /* Clock consumers of SYS_PLL1_SS_RANGE output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_CLK 528000000UL /* Clock consumers of SYS_PLL2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD0_CLK 352000000UL /* Clock consumers of SYS_PLL2_PFD0_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD1_CLK 594000000UL /* Clock consumers of SYS_PLL2_PFD1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD2_CLK 396000000UL /* Clock consumers of SYS_PLL2_PFD2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD3_CLK 297000000UL /* Clock consumers of SYS_PLL2_PFD3_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_MODULATION 0UL /* Clock consumers of SYS_PLL2_SS_MODULATION output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_RANGE 0UL /* Clock consumers of SYS_PLL2_SS_RANGE output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_CLK 480000000UL /* Clock consumers of SYS_PLL3_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_DIV2_CLK 240000000UL /* Clock consumers of SYS_PLL3_DIV2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD0_CLK 392727272UL /* Clock consumers of SYS_PLL3_PFD0_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD1_CLK 261818181UL /* Clock consumers of SYS_PLL3_PFD1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD2_CLK 392727272UL /* Clock consumers of SYS_PLL3_PFD2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD3_CLK 480000000UL /* Clock consumers of SYS_PLL3_PFD3_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_TMR_1588_CLK_ROOT 240000000UL /* Clock consumers of TMR_1588_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_TMR_1588_REF_CLK 240000000UL /* Clock consumers of TMR_1588_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_TPM2_CLK_ROOT 80000000UL /* Clock consumers of TPM2_CLK_ROOT output : TPM2 */ +#define BOARD_BOOTCLOCKRUN_TPM4_CLK_ROOT 80000000UL /* Clock consumers of TPM4_CLK_ROOT output : TPM4 */ +#define BOARD_BOOTCLOCKRUN_TPM5_CLK_ROOT 80000000UL /* Clock consumers of TPM5_CLK_ROOT output : TPM5 */ +#define BOARD_BOOTCLOCKRUN_TPM6_CLK_ROOT 80000000UL /* Clock consumers of TPM6_CLK_ROOT output : TPM6 */ +#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */ +#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 396000000UL /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */ +#define BOARD_BOOTCLOCKRUN_WAKEUP_AXI_CLK_ROOT 240000000UL /* Clock consumers of WAKEUP_AXI_CLK_ROOT output : DMA4, FLEXSPI1, IEE, MECC1, MECC2, USB_OTG1, USB_OTG2, USDHC1, USDHC2 */ + + +/******************************************************************************* + * API for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ + +/* + * Copyright 2022 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ + +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if __CORTEX_M == 7 + #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 792000000UL /*!< CM7 Core clock frequency: 792000000Hz */ +#else + #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 240000000UL /*!< CM33 Core clock frequency: 240000000Hz */ +#endif + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKRUN_ACMP_CLK_ROOT 240000000UL /* Clock consumers of ACMP_CLK_ROOT output : CMP1, CMP2, CMP3, CMP4 */ +#define BOARD_BOOTCLOCKRUN_ADC1_CLK_ROOT 80000000UL /* Clock consumers of ADC1_CLK_ROOT output : ADC1 */ +#define BOARD_BOOTCLOCKRUN_ADC2_CLK_ROOT 80000000UL /* Clock consumers of ADC2_CLK_ROOT output : ADC2 */ +#define BOARD_BOOTCLOCKRUN_ARM_PLL_CLK 792000000UL /* Clock consumers of ARM_PLL_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_ASRC_CLK_ROOT 240000000UL /* Clock consumers of ASRC_CLK_ROOT output : ASRC */ +#define BOARD_BOOTCLOCKRUN_BUS_AON_CLK_ROOT 132000000UL /* Clock consumers of BUS_AON_CLK_ROOT output : CAN1, CAN3, I3C1, IOMUXC_AON, LPI2C1, LPI2C2, LPIT1, LPSPI1, LPSPI2, LPTMR1, LPUART1, LPUART2, LPUART7, LPUART8, MU2_MUA, MU2_MUB, RTWDOG1, RTWDOG2, RTWDOG3, RTWDOG4, RTWDOG5, SAI1, SEMA1, TPM1, TPM2, TSTMR1_TSTMRA */ +#define BOARD_BOOTCLOCKRUN_BUS_WAKEUP_CLK_ROOT 132000000UL /* Clock consumers of BUS_WAKEUP_CLK_ROOT output : ADC1, ADC2, AOI1, AOI2, AOI3, AOI4, CAN2, CMP1, CMP2, CMP3, CMP4, DAC, EQDC1, EQDC2, EQDC3, EQDC4, EWM, FLEXIO1, FLEXIO2, I3C2, IOMUXC, KPP, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPIT2, LPIT3, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPTMR2, LPTMR3, LPUART10, LPUART11, LPUART12, LPUART3, LPUART4, LPUART5, LPUART6, LPUART9, MECC1, MECC2, MU1_MUA, MU1_MUB, PDM, PWM1, PWM2, PWM3, PWM4, RGPIO2, RGPIO3, RGPIO4, RGPIO5, RGPIO6, RTWDOG3, SAI2, SAI3, SAI4, SEMA2, SINC1, SINC2, SINC3, SPDIF, TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8, TPM3, TPM4, TPM5, TPM6, TSTMR2_TSTMRA, USBPHY1, USBPHY2, USDHC1, USDHC2, XBAR1, XBAR2, XBAR3 */ +#define BOARD_BOOTCLOCKRUN_CAN1_CLK_ROOT 80000000UL /* Clock consumers of CAN1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_CAN2_CLK_ROOT 80000000UL /* Clock consumers of CAN2_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_CAN3_CLK_ROOT 80000000UL /* Clock consumers of CAN3_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_CCM_CKO1_CLK_ROOT 80000000UL /* Clock consumers of CCM_CKO1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_CCM_CKO2_CLK_ROOT 50000000UL /* Clock consumers of CCM_CKO2_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, GPT1, GPT2 */ +#define BOARD_BOOTCLOCKRUN_ECAT_CLK_ROOT 100000000UL /* Clock consumers of ECAT_CLK_ROOT output : ECAT */ +#define BOARD_BOOTCLOCKRUN_ECAT_PORT0_REF_CLK 50000000UL /* Clock consumers of ECAT_PORT0_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_ECAT_PORT1_REF_CLK 50000000UL /* Clock consumers of ECAT_PORT1_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_EDGELOCK_CLK_ROOT 200000000UL /* Clock consumers of EDGELOCK_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_ENET_REFCLK_ROOT 125000000UL /* Clock consumers of ENET_REFCLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 120000000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */ +#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 48000000UL /* Clock consumers of FLEXIO2_CLK_ROOT output : FLEXIO2 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI1_CLK_ROOT 130909090UL /* Clock consumers of FLEXSPI1_CLK_ROOT output : FLEXSPI1 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 196363636UL /* Clock consumers of FLEXSPI2_CLK_ROOT output : FLEXSPI2 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI_SLV_CLK_ROOT 132000000UL /* Clock consumers of FLEXSPI_SLV_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_GPT1_CLK_ROOT 240000000UL /* Clock consumers of GPT1_CLK_ROOT output : GPT1 */ +#define BOARD_BOOTCLOCKRUN_GPT2_CLK_ROOT 240000000UL /* Clock consumers of GPT2_CLK_ROOT output : GPT2 */ +#define BOARD_BOOTCLOCKRUN_I3C1_CLK_ROOT 24000000UL /* Clock consumers of I3C1_CLK_ROOT output : I3C1 */ +#define BOARD_BOOTCLOCKRUN_I3C2_CLK_ROOT 24000000UL /* Clock consumers of I3C2_CLK_ROOT output : I3C2 */ +#define BOARD_BOOTCLOCKRUN_LPI2C0102_CLK_ROOT 60000000UL /* Clock consumers of LPI2C0102_CLK_ROOT output : LPI2C1, LPI2C2 */ +#define BOARD_BOOTCLOCKRUN_LPI2C0304_CLK_ROOT 60000000UL /* Clock consumers of LPI2C0304_CLK_ROOT output : LPI2C3, LPI2C4 */ +#define BOARD_BOOTCLOCKRUN_LPI2C0506_CLK_ROOT 60000000UL /* Clock consumers of LPI2C0506_CLK_ROOT output : LPI2C5, LPI2C6 */ +#define BOARD_BOOTCLOCKRUN_LPIT3_CLK_ROOT 80000000UL /* Clock consumers of LPIT3_CLK_ROOT output : LPIT3 */ +#define BOARD_BOOTCLOCKRUN_LPSPI0102_CLK_ROOT 130909090UL /* Clock consumers of LPSPI0102_CLK_ROOT output : LPSPI1, LPSPI2 */ +#define BOARD_BOOTCLOCKRUN_LPSPI0304_CLK_ROOT 130909090UL /* Clock consumers of LPSPI0304_CLK_ROOT output : LPSPI3, LPSPI4 */ +#define BOARD_BOOTCLOCKRUN_LPSPI0506_CLK_ROOT 130909090UL /* Clock consumers of LPSPI0506_CLK_ROOT output : LPSPI5, LPSPI6 */ +#define BOARD_BOOTCLOCKRUN_LPTMR1_CLK_ROOT 80000000UL /* Clock consumers of LPTMR1_CLK_ROOT output : LPTMR1 */ +#define BOARD_BOOTCLOCKRUN_LPTMR2_CLK_ROOT 80000000UL /* Clock consumers of LPTMR2_CLK_ROOT output : LPTMR2 */ +#define BOARD_BOOTCLOCKRUN_LPTMR3_CLK_ROOT 80000000UL /* Clock consumers of LPTMR3_CLK_ROOT output : LPTMR3 */ +#define BOARD_BOOTCLOCKRUN_LPUART0102_CLK_ROOT 24000000UL /* Clock consumers of LPUART0102_CLK_ROOT output : LPUART1, LPUART2 */ +#define BOARD_BOOTCLOCKRUN_LPUART0304_CLK_ROOT 24000000UL /* Clock consumers of LPUART0304_CLK_ROOT output : LPUART3, LPUART4 */ +#define BOARD_BOOTCLOCKRUN_LPUART0506_CLK_ROOT 24000000UL /* Clock consumers of LPUART0506_CLK_ROOT output : LPUART5, LPUART6 */ +#define BOARD_BOOTCLOCKRUN_LPUART0708_CLK_ROOT 24000000UL /* Clock consumers of LPUART0708_CLK_ROOT output : LPUART7, LPUART8 */ +#define BOARD_BOOTCLOCKRUN_LPUART0910_CLK_ROOT 24000000UL /* Clock consumers of LPUART0910_CLK_ROOT output : LPUART10, LPUART9 */ +#define BOARD_BOOTCLOCKRUN_LPUART1112_CLK_ROOT 24000000UL /* Clock consumers of LPUART1112_CLK_ROOT output : LPUART11, LPUART12 */ +#define BOARD_BOOTCLOCKRUN_M33_CLK_ROOT 240000000UL /* Clock consumers of M33_CLK_ROOT output : ARM, DMA3, FLEXSPI2, RGPIO1, SysTick0 */ +#define BOARD_BOOTCLOCKRUN_M33_SYSTICK_CLK_ROOT 100000UL /* Clock consumers of M33_SYSTICK_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_M7_CLK_ROOT 792000000UL /* Clock consumers of M7_CLK_ROOT output : ARM, SysTick1 */ +#define BOARD_BOOTCLOCKRUN_M7_SYSTICK_CLK_ROOT 100000UL /* Clock consumers of M7_SYSTICK_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_MAC0_CLK_ROOT 50000000UL /* Clock consumers of MAC0_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_MAC1_CLK_ROOT 125000000UL /* Clock consumers of MAC1_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_MAC2_CLK_ROOT 125000000UL /* Clock consumers of MAC2_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_MAC3_CLK_ROOT 125000000UL /* Clock consumers of MAC3_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_MAC4_CLK_ROOT 50000000UL /* Clock consumers of MAC4_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_MIC_CLK_ROOT 80000000UL /* Clock consumers of MIC_CLK_ROOT output : PDM, SPDIF */ +#define BOARD_BOOTCLOCKRUN_NETC_CLK_ROOT 240000000UL /* Clock consumers of NETC_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_NETC_PORT0_REF_CLK 50000000UL /* Clock consumers of NETC_PORT0_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_NETC_PORT1_REF_CLK 50000000UL /* Clock consumers of NETC_PORT1_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_NETC_PORT2_REF_CLK 50000000UL /* Clock consumers of NETC_PORT2_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_NETC_PORT3_REF_CLK 50000000UL /* Clock consumers of NETC_PORT3_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_NETC_PORT4_REF_CLK 50000000UL /* Clock consumers of NETC_PORT4_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_OSC_24M 24000000UL /* Clock consumers of OSC_24M output : CAN1, CAN2, CAN3, DAC, GPT1, GPT2, SPDIF, TMPSNS */ +#define BOARD_BOOTCLOCKRUN_OSC_32K 32768UL /* Clock consumers of OSC_32K output : CMP1, CMP2, CMP3, CMP4, EWM, GPT1, GPT2, KPP, LPTMR1, LPTMR2, LPTMR3, RTWDOG1, RTWDOG2, RTWDOG3, RTWDOG4, RTWDOG5, USBPHY1, USBPHY2, USB_OTG1, USB_OTG2, USDHC1, USDHC2 */ +#define BOARD_BOOTCLOCKRUN_OSC_RC_24M 24000000UL /* Clock consumers of OSC_RC_24M output : DCDC, EWM, RTWDOG1, RTWDOG2, RTWDOG3, RTWDOG4, RTWDOG5 */ +#define BOARD_BOOTCLOCKRUN_OSC_RC_400M 400000000UL /* Clock consumers of OSC_RC_400M output : N/A */ +#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_CLK 0UL /* Clock consumers of PLL_AUDIO_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_MODULATION 0UL /* Clock consumers of PLL_AUDIO_SS_MODULATION output : N/A */ +#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_RANGE 0UL /* Clock consumers of PLL_AUDIO_SS_RANGE output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 0UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 0UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 0UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 0UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 0UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 0UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 0UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 0UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 0UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI4_CLK_ROOT 0UL /* Clock consumers of SAI4_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI4_MCLK1 0UL /* Clock consumers of SAI4_MCLK1 output : SAI4 */ +#define BOARD_BOOTCLOCKRUN_SAI4_MCLK2 0UL /* Clock consumers of SAI4_MCLK2 output : SAI4 */ +#define BOARD_BOOTCLOCKRUN_SAI4_MCLK3 0UL /* Clock consumers of SAI4_MCLK3 output : SAI4 */ +#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 200000000UL /* Clock consumers of SEMC_CLK_ROOT output : SEMC */ +#define BOARD_BOOTCLOCKRUN_SPDIF_CLK_ROOT 0UL /* Clock consumers of SPDIF_CLK_ROOT output : SPDIF */ +#define BOARD_BOOTCLOCKRUN_SPDIF_EXTCLK_OUT 0UL /* Clock consumers of SPDIF_EXTCLK_OUT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SWO_TRACE_CLK_ROOT 80000000UL /* Clock consumers of SWO_TRACE_CLK_ROOT output : ARM */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_CLK 1000000000UL /* Clock consumers of SYS_PLL1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV2_CLK 500000000UL /* Clock consumers of SYS_PLL1_DIV2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV5_CLK 200000000UL /* Clock consumers of SYS_PLL1_DIV5_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_MODULATION 0UL /* Clock consumers of SYS_PLL1_SS_MODULATION output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_RANGE 0UL /* Clock consumers of SYS_PLL1_SS_RANGE output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_CLK 528000000UL /* Clock consumers of SYS_PLL2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD0_CLK 352000000UL /* Clock consumers of SYS_PLL2_PFD0_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD1_CLK 594000000UL /* Clock consumers of SYS_PLL2_PFD1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD2_CLK 396000000UL /* Clock consumers of SYS_PLL2_PFD2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD3_CLK 297000000UL /* Clock consumers of SYS_PLL2_PFD3_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_MODULATION 0UL /* Clock consumers of SYS_PLL2_SS_MODULATION output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_RANGE 0UL /* Clock consumers of SYS_PLL2_SS_RANGE output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_CLK 480000000UL /* Clock consumers of SYS_PLL3_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_DIV2_CLK 240000000UL /* Clock consumers of SYS_PLL3_DIV2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD0_CLK 392727272UL /* Clock consumers of SYS_PLL3_PFD0_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD1_CLK 261818181UL /* Clock consumers of SYS_PLL3_PFD1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD2_CLK 392727272UL /* Clock consumers of SYS_PLL3_PFD2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD3_CLK 480000000UL /* Clock consumers of SYS_PLL3_PFD3_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_TMR_1588_CLK_ROOT 240000000UL /* Clock consumers of TMR_1588_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_TMR_1588_REF_CLK 240000000UL /* Clock consumers of TMR_1588_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_TPM2_CLK_ROOT 80000000UL /* Clock consumers of TPM2_CLK_ROOT output : TPM2 */ +#define BOARD_BOOTCLOCKRUN_TPM4_CLK_ROOT 80000000UL /* Clock consumers of TPM4_CLK_ROOT output : TPM4 */ +#define BOARD_BOOTCLOCKRUN_TPM5_CLK_ROOT 80000000UL /* Clock consumers of TPM5_CLK_ROOT output : TPM5 */ +#define BOARD_BOOTCLOCKRUN_TPM6_CLK_ROOT 80000000UL /* Clock consumers of TPM6_CLK_ROOT output : TPM6 */ +#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */ +#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 396000000UL /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */ +#define BOARD_BOOTCLOCKRUN_WAKEUP_AXI_CLK_ROOT 240000000UL /* Clock consumers of WAKEUP_AXI_CLK_ROOT output : DMA4, FLEXSPI1, IEE, MECC1, MECC2, USB_OTG1, USB_OTG2, USDHC1, USDHC2 */ + + +/******************************************************************************* + * API for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ + diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/pin_mux.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/pin_mux.c new file mode 100644 index 00000000000..9ef62aca0ed --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/pin_mux.c @@ -0,0 +1,113 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v15.0 +processor: MIMXRT1189xxxxx +package_id: MIMXRT1189CVM8C +mcu_data: ksdk2_0 +processor_version: 0.15.9 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "fsl_rgpio.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) { + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm33, enableClock: 'true'} +- pin_list: + - {pin_num: A5, peripheral: LPUART1, signal: RXD, pin_signal: GPIO_AON_09, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper, open_drain: Disable, drive_strength: High, + slew_rate: Slow} + - {pin_num: B1, peripheral: LPUART1, signal: TXD, pin_signal: GPIO_AON_08, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper, open_drain: Disable, drive_strength: High, + slew_rate: Slow} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins, assigned for the Cortex-M33 core. + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc1); /* Turn on LPCG: LPCG is ON. */ + CLOCK_EnableClock(kCLOCK_Iomuxc2); /* Turn on LPCG: LPCG is ON. */ + +// /* GPIO configuration on GPIO_AD_27 (pin M16) */ +// rgpio_pin_config_t gpio4_pinM16_config = { +// .pinDirection = kRGPIO_DigitalOutput, +// .outputLogic = 1U, +// }; +// /* Initialize GPIO functionality on GPIO_AD_27 (pin M16) */ +// RGPIO_PinInit(RGPIO4, 27U, &gpio4_pinM16_config); + +// IOMUXC_SetPinMux( +// IOMUXC_GPIO_AD_27_GPIO4_IO27, /* GPIO_AD_27 is configured as GPIO4_IO27 */ +// 0U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_AON_08_LPUART1_TX, /* GPIO_AON_08 is configured as LPUART1_TX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AON_09_LPUART1_RX, /* GPIO_AON_09 is configured as LPUART1_RX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AON_08_LPUART1_TX, /* GPIO_AON_08 PAD functional properties : */ + 0x02U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: high driver + Pull / Keep Select Field: Pull Disable, Highz + Pull Up / Down Config. Field: Weak pull down + Open Drain Field: Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AON_09_LPUART1_RX, /* GPIO_AON_09 PAD functional properties : */ + 0x02U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: high driver + Pull / Keep Select Field: Pull Disable, Highz + Pull Up / Down Config. Field: Weak pull down + Open Drain Field: Disabled */ +} + +void BOARD_InitLeds(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc1); /* Turn on LPCG: LPCG is ON. */ + CLOCK_EnableClock(kCLOCK_Iomuxc2); /* Turn on LPCG: LPCG is ON. */ + + /* GPIO configuration on GPIO_AD_27 (pin M16) */ + rgpio_pin_config_t gpio4_pinM16_config = { + .pinDirection = kRGPIO_DigitalOutput, + .outputLogic = 1U, + }; + /* Initialize GPIO functionality on GPIO_AD_27 (pin M16) */ + RGPIO_PinInit(RGPIO4, 27U, &gpio4_pinM16_config); + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_27_GPIO4_IO27, /* GPIO_AD_27 is configured as GPIO4_IO27 */ + 0U); +} + + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/pin_mux.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/pin_mux.h new file mode 100644 index 00000000000..03590a1759b --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/pin_mux.h @@ -0,0 +1,53 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /* Function assigned for the Cortex-M33 */ + +void BOARD_InitLeds(void); + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/SConscript b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/SConscript new file mode 100644 index 00000000000..3a19cec3677 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/SConscript @@ -0,0 +1,34 @@ +Import('rtconfig') + +from building import * +import rtconfig + +cwd = GetCurrentDir() + +# add the general drivers. +src = Split(""" +board.c +MCUX_Config/clock_config.c +MCUX_Config/pin_mux.c +""") + +# if GetDepend(['BSP_USING_VGLITE']): +# src += ['display_support.c', 'vglite_support.c', 'vglite_window.c'] + +CPPPATH = [cwd,cwd + '/MCUX_Config',cwd + '/ports'] +CPPDEFINES = ['CPU_MIMXRT1189CVM8C_cm33', 'MCUXPRESSO_SDK', 'MCUX_META_BUILD', 'MIMXRT1189_cm33_SERIES', 'XIP_BOOT_HEADER_ENABLE=1', 'XIP_BOOT_HEADER_DCD_ENABLE=1', 'XIP_EXTERNAL_FLASH=1', 'ARM_MATH_CM33'] + +if rtconfig.PLATFORM in ['gcc']: + CPPDEFINES += ['__STARTUP_INITIALIZE_RAMFUNCTION'] + +if rtconfig.PLATFORM in ['armcc', 'armclang']: + # CPPDEFINES += ['SDK_DEBUGCONSOLE'] + CPPDEFINES += ['NDEBUG'] + +if rtconfig.PLATFORM in ['iccarm']: + CPPDEFINES += ['NDEBUG'] + # CPPDEFINES += ['FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE=1'] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) + +Return('group') diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.c new file mode 100644 index 00000000000..2557a72bc40 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.c @@ -0,0 +1,1284 @@ +/* + * Copyright 2021-2025 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include "drv_uart.h" + +#include "fsl_common.h" +#include "board.h" +#if defined(SDK_NETC_USED) && SDK_NETC_USED + #include "fsl_netc_soc.h" + #include "fsl_netc_ierb.h" +#endif /* SDK_NETC_USED */ +#include "fsl_iomuxc.h" +#include "fsl_cache.h" +#include "fsl_ele_base_api.h" +#include "fsl_dcdc.h" +#include "fsl_trdc.h" +#include "fsl_rgpio.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_FLEXSPI_DLL_LOCK_RETRY (10) + +/******************************************************************************* + * Variables + ******************************************************************************/ + +AT_QUICKACCESS_SECTION_DATA(volatile uint32_t g_systickCounter); + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* MPU configuration. */ +#if __CORTEX_M == 7 +void BOARD_ConfigMPU(void) +{ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Image$$RW_m_ncache$$Base[]; + /* RW_m_ncache_aux is a auxiliary region which is used to get the whole size of noncache section */ + extern uint32_t Image$$RW_m_ncache_aux$$Base[]; + uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base; + uint32_t nonCacheSize = ((uint32_t)Image$$RW_m_ncache_aux$$Base) - nonCacheStart; +#elif defined(__MCUXPRESSO) + extern uint32_t __base_NCACHE_REGION; + extern uint32_t __top_NCACHE_REGION; + uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION); + uint32_t nonCacheSize = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart; +#elif defined(__ICCARM__) || defined(__GNUC__) + extern uint32_t __NCACHE_REGION_START[]; + extern uint32_t __NCACHE_REGION_SIZE[]; + uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START; + uint32_t nonCacheSize = (uint32_t)__NCACHE_REGION_SIZE; +#endif +#if defined(__USE_SHMEM) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Image$$RPMSG_SH_MEM$$Base[]; + /* RPMSG_SH_MEM_aux is a auxiliary region which is used to get the whole size of RPMSG_SH_MEM section */ + extern uint32_t Image$$RPMSG_SH_MEM_aux$$Base[]; + uint32_t rpmsgShmemStart = (uint32_t)Image$$RPMSG_SH_MEM$$Base; + uint32_t rpmsgShmemSize = ((uint32_t)Image$$RPMSG_SH_MEM_aux$$Base) - rpmsgShmemStart; +#elif defined(__MCUXPRESSO) + extern uint32_t __base_SHMEM_REGION; + extern uint32_t __top_SHMEM_REGION; + uint32_t rpmsgShmemStart = (uint32_t)(&__base_SHMEM_REGION); + uint32_t rpmsgShmemSize = (uint32_t)(&__top_SHMEM_REGION) - rpmsgShmemStart; +#elif defined(__ICCARM__) || defined(__GNUC__) + extern uint32_t __RPMSG_SH_MEM_START[]; + extern uint32_t __RPMSG_SH_MEM_SIZE[]; + uint32_t rpmsgShmemStart = (uint32_t)__RPMSG_SH_MEM_START; + uint32_t rpmsgShmemSize = (uint32_t)__RPMSG_SH_MEM_SIZE; +#endif +#endif + volatile uint32_t i; + + /* Disable I cache and D cache */ + L1CACHE_DisableICache(); + L1CACHE_DisableDCache(); + + /* Disable MPU */ + ARM_MPU_Disable(); + + /* clang-format off */ + + /* MPU configure: + * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) + * API in mpu_armv7.h. + * param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches disabled. + * param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. + * Use MACROS defined in mpu_armv7.h: + * ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO + * + * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes. + * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribute Shareability Cache + * 0 x 0 0 Strongly Ordered shareable + * 0 x 0 1 Device shareable + * 0 0 1 0 Normal not shareable Outer and inner write + * through no write allocate + * 0 0 1 1 Normal not shareable Outer and inner write + * back no write allocate + * 0 1 1 0 Normal shareable Outer and inner write + * through no write allocate + * 0 1 1 1 Normal shareable Outer and inner write + * back no write allocate + * 1 0 0 0 Normal not shareable outer and inner + * noncache + * 1 1 0 0 Normal shareable outer and inner + * noncache + * 1 0 1 1 Normal not shareable outer and inner write + * back write/read acllocate + * 1 1 1 1 Normal shareable outer and inner write + * back write/read acllocate + * 2 x 0 0 Device not shareable + * Above are normal use settings, if your want to see more details or want to config different inner/outer cache + * policy, please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide + * + * param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled. + * param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in mpu_armv7.h. + */ + + /* clang-format on */ + + /* + * Add default region to deny access to whole address space to workaround speculative prefetch. + * Refer to Arm errata 1013783-B for more details. + */ + + /* Region 0 setting: Instruction access disabled, No data access permission. */ + MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U); + MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_NONE, 0, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB); + + /* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */ + MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB); + + /* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */ + MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2GB); + + /* Region 4 setting: Memory with Normal type, not shareable, outer/inner write back */ /*ITCM*/ + MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB); + + /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */ /*DTCM*/ + MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB); + + MPU->RBAR = ARM_MPU_RBAR(6, 0x20480000U); +#if defined(CACHE_MODE_WRITE_THROUGH) + /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write through */ /*OCRAM1*/ + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_512KB); +#else + /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */ /*OCRAM1*/ + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512KB); +#endif + + MPU->RBAR = ARM_MPU_RBAR(7, 0x20500000U); +#if defined(CACHE_MODE_WRITE_THROUGH) + /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write through */ /*OCRAM2*/ + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_256KB); +#else + /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */ /*OCRAM2*/ + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB); +#endif + +#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1) + /* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back. */ /*FSPI1*/ + MPU->RBAR = ARM_MPU_RBAR(8, 0x28000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_16MB); +#endif + +#if defined(USE_HYPERRAM) + MPU->RBAR = ARM_MPU_RBAR(9, 0x04000000U); +#if defined(CACHE_MODE_WRITE_THROUGH) + /* Region 9 setting: Memory with Normal type, not shareable, outer/inner write through. */ /*FSPI2*/ + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_8MB); +#else + /* Region 9 setting: Memory with Normal type, not shareable, outer/inner write back. */ /*FSPI2*/ + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_8MB); +#endif +#endif + +#if defined(USE_SDRAM) + MPU->RBAR = ARM_MPU_RBAR(10, 0x80000000U); +#if defined(CACHE_MODE_WRITE_THROUGH) + /* Region 10 setting: Memory with Normal type, not shareable, outer/inner write through */ + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_64MB); +#else + /* Region 10 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64MB); +#endif +#endif + + i = 0; + while ((nonCacheSize >> i) > 0x1U) + { + i++; + } + + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert(!(nonCacheStart % nonCacheSize)); + assert(nonCacheSize == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Region 11 setting: Memory with Normal type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(11, nonCacheStart); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1); + } + +#if defined(__USE_SHMEM) + i = 0; + while ((rpmsgShmemSize >> i) > 0x1U) + { + i++; + } + + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert(!(rpmsgShmemStart % rpmsgShmemSize)); + assert(rpmsgShmemSize == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Region 12 setting: Memory with Normal type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(12, rpmsgShmemStart); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1); + } +#endif + + /* Enable MPU */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk); + + /* Enable I cache and D cache */ + L1CACHE_EnableDCache(); + L1CACHE_EnableICache(); +} +#elif __CORTEX_M == 33 +void BOARD_ConfigMPU(void) +{ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Image$$RW_m_ncache$$Base[]; + /* RW_m_ncache_aux is a auxiliary region which is used to get the whole size of noncache section */ + extern uint32_t Image$$RW_m_ncache_aux$$Base[]; + uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base; + uint32_t nonCacheSize = ((uint32_t)Image$$RW_m_ncache_aux$$Base) - nonCacheStart; +#elif defined(__MCUXPRESSO) + extern uint32_t __base_NCACHE_REGION; + extern uint32_t __top_NCACHE_REGION; + uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION); + uint32_t nonCacheSize = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart; +#elif defined(__ICCARM__) || defined(__GNUC__) + extern uint32_t __NCACHE_REGION_START[]; + extern uint32_t __NCACHE_REGION_SIZE[]; + uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START; + uint32_t nonCacheSize = (uint32_t)__NCACHE_REGION_SIZE; +#endif +#if defined(__USE_SHMEM) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Image$$RPMSG_SH_MEM$$Base[]; + /* RPMSG_SH_MEM_aux is a auxiliary region which is used to get the whole size of RPMSG_SH_MEM section */ + extern uint32_t Image$$RPMSG_SH_MEM_aux$$Base[]; + uint32_t rpmsgShmemStart = (uint32_t)Image$$RPMSG_SH_MEM$$Base; + uint32_t rpmsgShmemSize = (uint32_t)Image$$RPMSG_SH_MEM_aux$$Base - rpmsgShmemStart; +#elif defined(__MCUXPRESSO) + extern uint32_t __base_SHMEM_REGION; + extern uint32_t __top_SHMEM_REGION; + uint32_t rpmsgShmemStart = (uint32_t)(&__base_SHMEM_REGION); + uint32_t rpmsgShmemSize = (uint32_t)(&__top_SHMEM_REGION) - rpmsgShmemStart; +#elif defined(__ICCARM__) || defined(__GNUC__) + extern uint32_t __RPMSG_SH_MEM_START[]; + extern uint32_t __RPMSG_SH_MEM_SIZE[]; + uint32_t rpmsgShmemStart = (uint32_t)__RPMSG_SH_MEM_START; + uint32_t rpmsgShmemSize = (uint32_t)__RPMSG_SH_MEM_SIZE; +#endif +#endif + uint32_t i; + uint8_t attr; + + /* Disable code & system cache */ + XCACHE_DisableCache(XCACHE_PC); + XCACHE_DisableCache(XCACHE_PS); + + /* Disable MPU */ + ARM_MPU_Disable(); + + /* Attr0: device. */ + ARM_MPU_SetMemAttr(0U, ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE)); + + /* Attr1: non cacheable. */ + ARM_MPU_SetMemAttr(1U, ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE)); + + /* Attr2: non transient, write through, read allocate. */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 0U, 1U, 0U); + ARM_MPU_SetMemAttr(2U, ARM_MPU_ATTR(attr, attr)); + + /* Attr3: non transient, write back, read/write allocate. */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 1U, 1U, 1U); + ARM_MPU_SetMemAttr(3U, ARM_MPU_ATTR(attr, attr)); + + /* NOTE: + * 1. When memory regions overlap, the processor generates a fault if a core access hits the overlapping regions + */ + +#if defined(USE_HYPERRAM) + /* + The default attribute of the background system address map for this address space: + normal, write through, read allocate, non-shareable, read/write in privilege and non-privilege, executable + */ + + /* Region 0 (FlexSPI2, Hyperram): [0x04000000, 0x047FFFFFF, 8M] */ +#if !defined(CACHE_MODE_WRITE_THROUGH) + /* non-shareable, read/write in privilege and non-privilege, executable. Attr 3 */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x04000000, ARM_MPU_SH_NON, 0U, 1U, 0U), ARM_MPU_RLAR(0x047FFFFF, 3U)); +#endif +#endif + + /* Region 1 (Code TCM): [0x0FFE0000, 0x0FFFFFFF, 128K] */ + /* non-shareable, read/write in privilege and non-privilege, executable. Attr 2 */ + ARM_MPU_SetRegion(1U, ARM_MPU_RBAR(0x0FFE0000, ARM_MPU_SH_NON, 0U, 1U, 0U), ARM_MPU_RLAR(0x0FFFFFFF, 2U)); + + /* Region 2 (System TCM): [0x20000000, 0x2001FFFF, 128K] */ + /* non-shareable, read/write in privilege and non-privilege, executable. Attr 3 */ + ARM_MPU_SetRegion(2U, ARM_MPU_RBAR(0x20000000, ARM_MPU_SH_NON, 0U, 1U, 0U), ARM_MPU_RLAR(0x2001FFFF, 3U)); + + /* Region 3 (CM7 I/D TCM): [0x203C0000, 0x2043FFFF, 512K] */ + /* non-shareable, read/write in privilege and non-privilege, execute-never. Attr 1 (non cacheable). */ + ARM_MPU_SetRegion(3U, ARM_MPU_RBAR(0x203C0000, ARM_MPU_SH_NON, 0U, 1U, 1U), ARM_MPU_RLAR(0x2043FFFF, 1U)); + + /* Region 4 (CM7 I/D TCM): [0x303C0000, 0x3043FFFF, 512K] */ + /* non-shareable, read/write in privilege and non-privilege, execute-never. Attr 1 (non cacheable). */ + ARM_MPU_SetRegion(4U, ARM_MPU_RBAR(0x303C0000, ARM_MPU_SH_NON, 0U, 1U, 1U), ARM_MPU_RLAR(0x3043FFFF, 1U)); + + /* + As common setting, not set this region to avoid potential overlapping setting with NCACHE(region 8) + and SHMEM(region 9) for specific build configuration, but use the default attribute of the background + system address map. + The default attribute of the background system address map for this address space: + normal, write back, write/read allocate, non-shareable, read/write in privilege and non-privilege, executable + + If application needs to fine tune MPU settings, here is an example: + // Region 11 (OCRAM1): [0x20480000, 0x204FFFFF, 512K] + // non-shareable, read/write in privilege and non-privilege, executable. Attr 3 + ARM_MPU_SetRegion(11U, ARM_MPU_RBAR(0x20480000, ARM_MPU_SH_NON, 0U, 1U, 0U), ARM_MPU_RLAR(0x204FFFFF, 3U)); + + // Region 12 (OCRAM2): [0x20500000, 0x2053FFFF, 256K] + // non-shareable, read/write in privilege and non-privilege, executable. Attr 3 + ARM_MPU_SetRegion(12U, ARM_MPU_RBAR(0x20500000, ARM_MPU_SH_NON, 0U, 1U, 0U), ARM_MPU_RLAR(0x2053FFFF, 3U)); + */ + + /* Region 5 (FlexSPI1, Nor Flash): [0x28000000, 0x28FFFFFF, 16M] */ + /* non-shareable, read only in privilege and non-privileged, executable. Attr 2 */ + ARM_MPU_SetRegion(5U, ARM_MPU_RBAR(0x28000000, ARM_MPU_SH_NON, 1U, 1U, 0U), ARM_MPU_RLAR(0x28FFFFFF, 2U)); + + /* Region 6 (Peripherals): [0x40000000, 0x7FFFFFFF, 1G ] */ + /* non-shareable, read/write in privilege and non-privileged, execute-never. Attr 0 (device). */ + ARM_MPU_SetRegion(6U, ARM_MPU_RBAR(0x40000000, ARM_MPU_SH_NON, 0U, 1U, 1U), ARM_MPU_RLAR(0x7FFFFFFF, 0U)); + +#if defined(USE_SDRAM) + /* + As common setting, not set this region to avoid potential overlapping setting with NCACHE(region 8) + and SHMEM(region 9) for specific build configuration, but use the default attribute of the background + system address map. + The default attribute of the background system address map for this address space: + normal, write through, read allocate, non-shareable, read/write in privilege and non-privilege, executable + + If application needs to fine tune MPU settings, here is an example: + // Region 7 (SEMC, SDRAM): [0x80000000, 0x81FFFFFF, 32M] + // non-shareable, read/write in privilege and non-privilege, executable. Attr 3 + ARM_MPU_SetRegion(7U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_NON, 0U, 1U, 0U), ARM_MPU_RLAR(0x81FFFFFF, 3U)); + */ +#endif + + i = 0; + while ((nonCacheSize >> i) > 0x1U) + { + i++; + } + + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32 */ + assert(nonCacheSize == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Region 8: non-shareable, read/write in privilege and non-privilege, executable. Attr 1(non-cacheable) */ + ARM_MPU_SetRegion(8U, ARM_MPU_RBAR(nonCacheStart, ARM_MPU_SH_NON, 0U, 1U, 0U), + ARM_MPU_RLAR(nonCacheStart + nonCacheSize - 1, 1U)); + } + +#if defined(__USE_SHMEM) + i = 0; + while ((rpmsgShmemSize >> i) > 0x1U) + { + i++; + } + + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert(!(rpmsgShmemStart % rpmsgShmemSize)); + assert(rpmsgShmemSize == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Region 9: non-shareable, read/write in privilege and non-privilege, executable. Attr 1(non-cacheable) */ + ARM_MPU_SetRegion(9U, ARM_MPU_RBAR(rpmsgShmemStart, ARM_MPU_SH_NON, 0U, 1U, 0U), + ARM_MPU_RLAR(rpmsgShmemStart + rpmsgShmemSize - 1, 1U)); + } +#endif + +#if defined(CACHE_MODE_WRITE_THROUGH) + /* + * CM33 MPU settings can't overlay, so the common MPU settings for CM33 can't handle the + * CACHE_MODE_WRITE_THROUGH, otherwise it may conflict(overlay) with NCACHE and SHMEN. + * + * Assume the NCACHE/SHMEM region are located in OCRAM. + * This is a workaround that disable the cache of OCRAM1 and OCRAM 2, based on current link settings. + * It impacts the performance, application may fine tune MPU according to its own linkage. + */ + + // Region 8 (OCRAM1): [0x20480000, 0x204FFFFF, 512K] + // non-shareable, read/write in privilege and non-privilege, executable. Attr 1 + ARM_MPU_SetRegion(8U, ARM_MPU_RBAR(0x20480000, ARM_MPU_SH_NON, 0U, 1U, 0U), ARM_MPU_RLAR(0x204FFFFF, 1U)); + + // Region 9 (OCRAM2): [0x20500000, 0x2053FFFF, 256K] + // non-shareable, read/write in privilege and non-privilege, executable. Attr 1 + ARM_MPU_SetRegion(9U, ARM_MPU_RBAR(0x20500000, ARM_MPU_SH_NON, 0U, 1U, 0U), ARM_MPU_RLAR(0x2053FFFF, 1U)); +#endif + + // Region 11 (OCRAM1): [0x20480000, 0x204FFFFF, 512K] + // non-shareable, read/write in privilege and non-privilege, executable. Attr 3 + ARM_MPU_SetRegion(11U, ARM_MPU_RBAR(0x20480000, ARM_MPU_SH_NON, 0U, 1U, 0U), ARM_MPU_RLAR(0x204FFFFF, 2U)); + + // Region 12 (OCRAM2): [0x20500000, 0x2053FFFF, 256K] + // non-shareable, read/write in privilege and non-privilege, executable. Attr 3 + ARM_MPU_SetRegion(12U, ARM_MPU_RBAR(0x20500000, ARM_MPU_SH_NON, 0U, 1U, 0U), ARM_MPU_RLAR(0x2053FFFF, 2U)); + + /* Enable MPU */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk); + + /* Enable code & system cache */ + XCACHE_EnableCache(XCACHE_PS); + XCACHE_EnableCache(XCACHE_PC); +} +#endif + +void BOARD_DeinitFlash(FLEXSPI_Type *base) +{ +#if (__CORTEX_M == 7) + if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR)) + { + SCB_DisableICache(); + } +#endif + +#if (__CORTEX_M == 33) + if ((XCACHE_PC->CCR & XCACHE_CCR_ENCACHE_MASK) == 1U) /* disabled if enabled */ + { + /* Enable the to push all modified lines. */ + XCACHE_PC->CCR |= XCACHE_CCR_PUSHW0_MASK | XCACHE_CCR_PUSHW1_MASK | XCACHE_CCR_GO_MASK; + /* Wait until the cache command completes. */ + while ((XCACHE_PC->CCR & XCACHE_CCR_GO_MASK) != 0x00U) + { + } + /* As a precaution clear the bits to avoid inadvertently re-running this command. */ + XCACHE_PC->CCR &= ~(XCACHE_CCR_PUSHW0_MASK | XCACHE_CCR_PUSHW1_MASK); + XCACHE_PC->CCR &= ~XCACHE_CCR_ENCACHE_MASK; + __ISB(); + __DSB(); + } +#endif + + /* Enable FLEXSPI module */ + base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; + + /* Wait until FLEXSPI is not busy */ + while (!((base->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && (base->STS0 & FLEXSPI_STS0_SEQIDLE_MASK))) + { + } + /* Disable module during the reset procedure */ + base->MCR0 |= FLEXSPI_MCR0_MDIS_MASK; +} + +void BOARD_InitFlash(FLEXSPI_Type *base) +{ + uint32_t status; + uint32_t lastStatus; + uint32_t retry; + + /* If serial root clock is >= 100 MHz, DLLEN set to 1, OVRDEN set to 0, then SLVDLYTARGET setting of 0x0 is + * recommended. */ + base->DLLCR[0] = 0x1U; + + /* Enable FLEXSPI module */ + base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; + + base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK; + while (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK) + { + } + + /* Need to wait DLL locked if DLL enabled */ + if (0U != (base->DLLCR[0] & FLEXSPI_DLLCR_DLLEN_MASK)) + { + lastStatus = base->STS2; + retry = BOARD_FLEXSPI_DLL_LOCK_RETRY; + /* Wait slave delay line locked and slave reference delay line locked. */ + do + { + status = base->STS2; + if ((status & (FLEXSPI_STS2_AREFLOCK_MASK | FLEXSPI_STS2_ASLVLOCK_MASK)) == + (FLEXSPI_STS2_AREFLOCK_MASK | FLEXSPI_STS2_ASLVLOCK_MASK)) + { + /* Locked */ + retry = 100; + break; + } + else if (status == lastStatus) + { + /* Same delay cell number in calibration */ + retry--; + } + else + { + retry = BOARD_FLEXSPI_DLL_LOCK_RETRY; + lastStatus = status; + } + } + while (retry > 0); + /* According to ERR011377, need to delay at least 100 NOPs to ensure the DLL is locked. */ + for (; retry > 0U; retry--) + { + __NOP(); + } + } + +#if (__CORTEX_M == 7) + SCB_EnableICache(); +#endif + +#if (__CORTEX_M == 33) + if ((XCACHE_PC->CCR & XCACHE_CCR_ENCACHE_MASK) == 0U) + { + /* set command to invalidate all ways and write GO bit to initiate command */ + XCACHE_PC->CCR = XCACHE_CCR_INVW1_MASK | XCACHE_CCR_INVW0_MASK; + XCACHE_PC->CCR |= XCACHE_CCR_GO_MASK; + /* Wait until the command completes */ + while ((XCACHE_PC->CCR & XCACHE_CCR_GO_MASK) != 0U) + { + } + /* Enable cache */ + XCACHE_PC->CCR = XCACHE_CCR_ENCACHE_MASK; + __ISB(); + __DSB(); + } +#endif +} + +/* BOARD_SetFlexspiClock run in RAM used to configure FlexSPI clock source and divider when XIP. */ +void BOARD_SetFlexspiClock(FLEXSPI_Type *base, uint8_t src, uint32_t divider) +{ + clock_root_t root; + clock_lpcg_t lpcg; + + if (base == FLEXSPI1) + { + root = kCLOCK_Root_Flexspi1; + lpcg = kCLOCK_Flexspi1; + } + else if (base == FLEXSPI2) + { + root = kCLOCK_Root_Flexspi2; + lpcg = kCLOCK_Flexspi2; + } + else + { + return; + } + + if (((CCM->CLOCK_ROOT[root].CONTROL & CCM_CLOCK_ROOT_CONTROL_MUX_MASK) != CCM_CLOCK_ROOT_CONTROL_MUX(src)) || + ((CCM->CLOCK_ROOT[root].CONTROL & CCM_CLOCK_ROOT_CONTROL_DIV_MASK) != CCM_CLOCK_ROOT_CONTROL_DIV(divider - 1))) + { + /* Always deinit FLEXSPI and init FLEXSPI for the flash to make sure the flash works correctly after the + FLEXSPI root clock changed as the default FLEXSPI configuration may does not work for the new root clock + frequency. */ + BOARD_DeinitFlash(base); + + /* Disable clock before changing clock source */ + CCM->LPCG[lpcg].DIRECT &= ~CCM_LPCG_DIRECT_ON_MASK; + __DSB(); + __ISB(); + while (CCM->LPCG[lpcg].STATUS0 & CCM_LPCG_STATUS0_ON_MASK) + { + } + + /* Update flexspi clock. */ + CCM->CLOCK_ROOT[root].CONTROL = CCM_CLOCK_ROOT_CONTROL_MUX(src) | CCM_CLOCK_ROOT_CONTROL_DIV(divider - 1); + __DSB(); + __ISB(); + (void)CCM->CLOCK_ROOT[root].CONTROL; + + /* Enable FLEXSPI clock again */ + CCM->LPCG[lpcg].DIRECT |= CCM_LPCG_DIRECT_ON_MASK; + __DSB(); + __ISB(); + while (!(CCM->LPCG[lpcg].STATUS0 & CCM_LPCG_STATUS0_ON_MASK)) + { + } + + BOARD_InitFlash(base); + } +} + +/* This function is used to change FlexSPI clock to a stable source before clock sources(Such as PLL and Main clock) + * updating in case XIP(execute code on FLEXSPI memory.) */ +void BOARD_FlexspiClockSafeConfig(void) +{ + /* Move FLEXSPI clock source to OSC_RC_24M to avoid instruction/data fetch issue in XIP when updating PLL. */ + BOARD_SetFlexspiClock(FLEXSPI1, 0U, 1U); +} + +/* This function is used to set EdgeLock clock via safe method */ +void EdgeLock_SetClock(uint8_t mux, uint8_t div) +{ + if ((CLOCK_GetRootClockDiv(kCLOCK_Root_Edgelock) != (uint32_t)div) || + (CLOCK_GetRootClockMux(kCLOCK_Root_Edgelock) != (uint32_t)mux)) + { + status_t sts; + uint32_t ele_clk_mhz; + + clock_root_config_t rootCfg = + { + .div = div, + .mux = mux, + .clockOff = false, + }; + + do + { + sts = ELE_BaseAPI_ClockChangeStart(MU_RT_S3MUA); + } + while (sts != kStatus_Success); + + CLOCK_SetRootClock(kCLOCK_Root_Edgelock, &rootCfg); + + ele_clk_mhz = CLOCK_GetRootClockFreq(kCLOCK_Root_Edgelock) / 1000000UL; + do + { + sts = ELE_BaseAPI_ClockChangeFinish(MU_RT_S3MUA, ele_clk_mhz, 0); + } + while (sts != kStatus_Success); + } +} + +/* This function is used to set DCDC output voltage via safe method */ +void DCDC_SetVoltage(uint8_t core, uint8_t targetVoltage) +{ + /* + * When GDET is enabled, it is required to work with special ELE FW, which + * support ELE API VOLTAGE_CHANGE_START and VOLTAGE_CHANGE_FINISH, and + * DCDC voltage setting must be guarded with VOLTAGE_CHANGE_START and + * VOLTAGE_CHANGE_FINISH. + * + * For those ELE FW or ELE ROM, which doesn't support ELE API VOLTAGE_CHANGE_START + * and VOLTAGE_CHANGE_FINISH, there is no side effect to send such API command, + * since ELE just responde with ERROR and ingore the API command. + */ + ELE_BaseAPI_VoltageChangeStart(MU_RT_S3MUA); + + DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC, (dcdc_core_slice_t)core, (dcdc_1P0_target_vol_t)targetVoltage); + + ELE_BaseAPI_VoltageChangeFinish(MU_RT_S3MUA); +} + +#if defined(SDK_NETC_USED) && SDK_NETC_USED +void BOARD_NETC_Init(void) +{ + /* EP and Switch port 0 use RMII interface. */ + NETC_SocSetMiiMode(kNETC_SocLinkEp0, kNETC_RmiiMode); + NETC_SocSetMiiMode(kNETC_SocLinkSwitchPort0, kNETC_RmiiMode); + + /* Switch port 1~3 use RGMII interface. */ + NETC_SocSetMiiMode(kNETC_SocLinkSwitchPort1, kNETC_RgmiiMode); + NETC_SocSetMiiMode(kNETC_SocLinkSwitchPort2, kNETC_RgmiiMode); + NETC_SocSetMiiMode(kNETC_SocLinkSwitchPort3, kNETC_RgmiiMode); + + /* Output reference clock for RMII interface. */ + NETC_SocSetRmiiRefClk(kNETC_SocLinkEp0, true); + NETC_SocSetRmiiRefClk(kNETC_SocLinkSwitchPort0, true); + + /* Unlock the IERB. It will warm reset whole NETC. */ + if (NETC_IERBUnlock() == kStatus_Success) + { + while (!NETC_IERBIsUnlockOver()) + { + } + } + + /* Set the access attribute, otherwise MSIX access will be blocked. */ + NETC_IERB->ARRAY_NUM_RC[0].RCMSIAMQR &= ~(7U << 27); + NETC_IERB->ARRAY_NUM_RC[0].RCMSIAMQR |= (1U << 27); + + /* Set PHY address in IERB to use MAC port MDIO, otherwise the access will be blocked. */ + NETC_SocSetLinkAddr(kNETC_SocLinkEp0, BOARD_EP0_PHY_ADDR); + NETC_SocSetLinkAddr(kNETC_SocLinkSwitchPort0, BOARD_SWT_PORT0_PHY_ADDR); + NETC_SocSetLinkAddr(kNETC_SocLinkSwitchPort1, BOARD_SWT_PORT1_PHY_ADDR); + NETC_SocSetLinkAddr(kNETC_SocLinkSwitchPort2, BOARD_SWT_PORT2_PHY_ADDR); + NETC_SocSetLinkAddr(kNETC_SocLinkSwitchPort3, BOARD_SWT_PORT3_PHY_ADDR); + + /* Lock the IERB. */ + assert(NETC_IERBLock() == kStatus_Success); + while (!NETC_IERBIsLockOver()) + { + } +} +#endif /* SDK_NETC_USED */ + +void BOARD_RequestTRDC(bool bRequestAON, bool bRequestWakeup, bool bReqeustMega) +{ +#define ELE_TRDC_AON_ID 0x74 +#define ELE_TRDC_WAKEUP_ID 0x78 +#define ELE_TRDC_MEGA_ID 0x82 +#define ELE_CORE_CM33_ID 0x1 +#define ELE_CORE_CM7_ID 0x2 + +#if (__CORTEX_M == 33) + uint8_t ele_core_id = ELE_CORE_CM33_ID; +#elif (__CORTEX_M == 7) + uint8_t ele_core_id = ELE_CORE_CM7_ID; +#endif + + uint32_t ele_fw_sts; + + /* Get ELE FW status */ + ELE_BaseAPI_GetFwStatus(MU_RT_S3MUA, &ele_fw_sts); + + if (bRequestAON) + { + /* Release TRDC AON to current core */ + ELE_BaseAPI_ReleaseRDC(MU_RT_S3MUA, ELE_TRDC_AON_ID, ele_core_id); + } + + /* + * TRDC MEGA request must be prior to TRDC WAKEUP, as TRDC MEGA access + * is controlled by the TRDC WAKEUP. + * note: + * If TRDC WAKEUP has been release to one core firstly, then it will fail + * to release TRDC MEGA to same/another core. + */ + if (bReqeustMega) + { + /* Release TRDC MEGA to current core */ + ELE_BaseAPI_ReleaseRDC(MU_RT_S3MUA, ELE_TRDC_MEGA_ID, ele_core_id); + } + + if (bRequestWakeup) + { + /* Release TRDC WAKEUP to current core */ + ELE_BaseAPI_ReleaseRDC(MU_RT_S3MUA, ELE_TRDC_WAKEUP_ID, ele_core_id); + } +} + +void APP_CommonTrdcDACSetting(void) +{ + trdc_processor_domain_assignment_t procAssign = {.domainId = 0U, + .domainIdSelect = kTRDC_DidInput, + .pidDomainHitConfig = kTRDC_pidDomainHitNone0, + .pidMask = 0U, + .secureAttr = kTRDC_ForceSecure, + .pid = 0U, + .lock = false + }; + + trdc_non_processor_domain_assignment_t nonProcAssign = {.domainId = 0U, + .privilegeAttr = kTRDC_ForcePrivilege, + .secureAttr = kTRDC_ForceSecure, + .bypassDomainId = true, + .lock = false + }; + + /* 1. Set the MDAC Configuration in TRDC1. */ + /* Configure the access control for CM33(master 1 for TRDC1, MDAC_A1). */ + procAssign.domainId = 0x2U; + TRDC_SetProcessorDomainAssignment(TRDC1, (uint8_t)kTRDC1_MasterCM33, 0U, &procAssign); + /* Configure the access control for eDMA3(master 2 for TRDC1, MDAC_A2). */ + nonProcAssign.domainId = 0x7U; + TRDC_SetNonProcessorDomainAssignment(TRDC1, (uint8_t)kTRDC1_MasterDMA3, &nonProcAssign); + + /* 2. Set the MDAC Configuration in TRDC2. */ + /* Configure the access control for CM7 AHBP(master 0 for TRDC2, MDAC_W0). */ + procAssign.domainId = 0x4U; + TRDC_SetProcessorDomainAssignment(TRDC2, (uint8_t)kTRDC2_MasterCM7AHBP, 0U, &procAssign); + /* Configure the access control for CM7 AXI(master 1 for TRDC2, MDAC_W1). */ + TRDC_SetProcessorDomainAssignment(TRDC2, (uint8_t)kTRDC2_MasterCM7AXI, 0U, &procAssign); + /* Configure the access control for DAP AHB_AP_SYS(master 2 for TRDC2, MDAC_W2). */ + nonProcAssign.domainId = 0x9U; + TRDC_SetNonProcessorDomainAssignment(TRDC2, (uint8_t)kTRDC2_MasterDAP, &nonProcAssign); + /* Configure the access control for CoreSight(master 3 for TRDC2, MDAC_W3). */ + nonProcAssign.domainId = 0x8U; + TRDC_SetNonProcessorDomainAssignment(TRDC2, (uint8_t)kTRDC2_MasterCoreSight, &nonProcAssign); + /* Configure the access control for DMA4(master 4 for TRDC2, MDAC_W4). */ + nonProcAssign.domainId = 0x7U; + TRDC_SetNonProcessorDomainAssignment(TRDC2, (uint8_t)kTRDC2_MasterDMA4, &nonProcAssign); + /* Configure the access control for NETC(master 5 for TRDC2, MDAC_W5). */ + procAssign.domainId = 0xAU; + TRDC_SetProcessorDomainAssignment(TRDC2, (uint8_t)kTRDC2_MasterNETC, 0U, &procAssign); + + /* 3. Set the MDAC Configuration in TRDC3. */ + /* Configure the access control for uSDHC1(master 0 for TRDC3, MDAC_M0). */ + nonProcAssign.domainId = 0x5U; + TRDC_SetNonProcessorDomainAssignment(TRDC3, (uint8_t)kTRDC3_MasterUSDHC1, &nonProcAssign); + /* Configure the access control for uSDHC2(master 1 for TRDC3, MDAC_M1). */ + nonProcAssign.domainId = 0x6U; + TRDC_SetNonProcessorDomainAssignment(TRDC3, (uint8_t)kTRDC3_MasterUSDHC2, &nonProcAssign); + /* Configure the access control for USB(master 3 for TRDC3, MDAC_M3). */ + nonProcAssign.domainId = 0xBU; + TRDC_SetNonProcessorDomainAssignment(TRDC3, (uint8_t)kTRDC3_MasterUsb, &nonProcAssign); + /* Configure the access control for FlexSPI_FLR(master 4 for TRDC3, MDAC_M4). */ + nonProcAssign.domainId = 0xAU; + TRDC_SetNonProcessorDomainAssignment(TRDC3, (uint8_t)kTRDC3_MasterFlexspiFlr, &nonProcAssign); +} + +static bool TRDC_IsValidDomain(TRDC_Type *trdc, uint8_t domain) +{ + bool r = true; + + if ((domain > 11) || (domain < 2) || (domain == 3)) + { + r = false; + } + return r; +} + +static bool TRDC_IsValidMbc(TRDC_Type *trdc, uint8_t mbc) +{ + bool r = false; + if (trdc == TRDC1) + { + switch (mbc) + { + case 0: /* TRDC1 MBC_A0 */ + case 1: /* TRDC1 MBC_A1 */ + r = true; + break; + default: + break; + } + } + else if (trdc == TRDC2) + { + switch (mbc) + { + case 0: /* TRDC2 MBC_W0 */ + case 1: /* TRDC2 MBC_W1 */ + r = true; + break; + default: + break; + } + } + return r; +} + +static uint32_t TRDC_GetMbcMemNum(TRDC_Type *trdc, uint32_t mbc) +{ + uint32_t memNumber = 0U; + if (trdc == TRDC1) + { + uint8_t MemNum[2] = {3, 2}; + switch (mbc) + { + case 0: /* TRDC1 MBC_A0 AIPS1/Edgelock/GPIO1 */ + case 1: /* TRDC1 MBC_A1 CM33 Code-TCM/CM33 System-TCM */ + memNumber = MemNum[mbc]; + break; + default: + break; + } + } + else if (trdc == TRDC2) + { + uint8_t MemNum[2] = {4, 4}; + switch (mbc) + { + case 0: /* TRDC2 MBC_A0 AIPS2/GPIO2, GPIO4, GPIO6/GPIO3, GPIO5/DAP (Debug) */ + case 1: /* TRDC2 MBC_A1 AIPS3/AHB_ISPAP/NIC_MAIN GPV/SRAMC */ + memNumber = MemNum[mbc]; + break; + default: + break; + } + } + return memNumber; +} + +static bool TRDC_IsValidMbcMem(TRDC_Type *trdc, uint8_t mbc, uint8_t mem) +{ + bool r = false; + if (trdc == TRDC1) + { + switch (mbc) + { + case 0: /* TRDC1 MBC_A0 */ + switch (mem) + { + case 0: /* TRDC1 MBC_A0 AIPS1 */ + r = true; + break; + case 1: /* TRDC1 MBC_A0 Edgelock */ + break; /* Intentional, Edgelock region not touched. */ + case 2: /* TRDC1 MBC_A0 GPIO1 */ + r = true; + break; + default: + break; + } + break; + case 1: /* TRDC1 MBC_A1 */ + switch (mem) + { + case 0: /* TRDC1 MBC_A1 CM33 Code-TCM */ + case 1: /* TRDC1 MBC_A1 CM33 System-TCM */ + r = true; + break; + default: + break; + } + break; + default: + break; + } + } + else if (trdc == TRDC2) + { + switch (mbc) + { + case 0: /* TRDC2 MBC_W0 */ + switch (mem) + { + case 0: /* TRDC2 MBC_W0 AIPS2 */ + case 1: /* TRDC2 MBC_W0 GPIO2, GPIO4, GPIO6 */ + case 2: /* TRDC2 MBC_W0 GPIO3, GPIO5 */ + case 3: /* TRDC2 MBC_W0 DAP (Debug) */ + r = true; + break; + + default: + break; + } + break; + case 1: /* TRDC2 MBC_W1 */ + switch (mem) + { + case 0: /* TRDC2 MBC_W1 AIPS3 */ + case 1: /* TRDC2 MBC_W1 AHB_ISPAP */ + case 2: /* TRDC2 MBC_W1 NIC_MAIN GPV */ + case 3: /* TRDC2 MBC_W1 SRAMC */ + r = true; + break; + + default: + break; + } + break; + default: + break; + } + } + return r; +} + +static bool TRDC_IsValidMrc(TRDC_Type *trdc, uint8_t mrc) +{ + bool r = false; + if (trdc == TRDC1) + { + switch (mrc) + { + case 0: /* TRDC1 MRC_A0 */ + case 1: /* TRDC1 MRC_A1 */ + r = true; + break; + default: + break; + } + } + else if (trdc == TRDC2) + { + switch (mrc) + { + case 1: /* TRDC2 MRC_W1 */ + case 2: /* TRDC2 MRC_W2 */ + case 3: /* TRDC2 MRC_W3 */ + case 4: /* TRDC2 MRC_W4 */ + case 5: /* TRDC2 MRC_W5 */ + case 6: /* TRDC2 MRC_W6 */ + r = true; + break; + default: + break; + } + } + return r; +} + +static bool TRDC_GetMrcRegionAddr(TRDC_Type *trdc, uint8_t mrc, uint32_t *pStartAddr, uint32_t *pStopAddr) +{ + bool r = true; + if (trdc == TRDC1) + { + switch (mrc) + { + case 0: /* TRDC1 MRC_A0 CM33 ROM */ + *pStartAddr = 0x00000000UL; + *pStopAddr = 0x00027FFFUL; + break; + case 1: /* TRDC1 MRC_A1 FlexSPI2 */ + *pStartAddr = 0x04000000UL; + *pStopAddr = 0x07FFFFFFUL; + break; + default: + r = false; + break; + } + } + else if (trdc == TRDC2) + { + switch (mrc) + { + case 1: /* TRDC2 MRC_W1 FlexSPI1 */ + *pStartAddr = 0x28000000UL; + *pStopAddr = 0x2FFFFFFFUL; + break; + case 2: /* TRDC2 MRC_W2 CM7 I-TCM D-TCM */ + *pStartAddr = 0x203C0000UL; + *pStopAddr = 0x2043FFFFUL; + break; + case 3: /* TRDC2 MRC_W3 OCRAM1 */ + *pStartAddr = 0x20480000UL; + *pStopAddr = 0x204FFFFFUL; + break; + case 4: /* TRDC2 MRC_W4 OCRAM2 */ + *pStartAddr = 0x20500000UL; + *pStopAddr = 0x2053FFFFUL; + break; + case 5: /* TRDC2 MRC_W5 SEMC */ + *pStartAddr = 0x80000000UL; + *pStopAddr = 0x8FFFFFFFUL; + break; + case 6: /* TRDC2 MRC_W6 NETC */ + *pStartAddr = 0x60000000UL; + *pStopAddr = 0x60FFFFFFUL; + break; + default: + r = false; + break; + } + } + return r; +} + +void APP_CommonTrdcAccessControlSetting(TRDC_Type *trdc) +{ + trdc_hardware_config_t hwConfig; + trdc_memory_access_control_config_t memAccessConfig; + trdc_mbc_memory_block_config_t mbcBlockConfig; + trdc_mrc_region_descriptor_config_t mrcRegionConfig; + + TRDC_GetHardwareConfig(trdc, &hwConfig); + + /* Enable all read/write/execute access for MRC/MBC access control. */ + (void)memset(&memAccessConfig, 0, sizeof(memAccessConfig)); + memAccessConfig.nonsecureUsrX = 1U; + memAccessConfig.nonsecureUsrW = 1U; + memAccessConfig.nonsecureUsrR = 1U; + memAccessConfig.nonsecurePrivX = 1U; + memAccessConfig.nonsecurePrivW = 1U; + memAccessConfig.nonsecurePrivR = 1U; + memAccessConfig.secureUsrX = 1U; + memAccessConfig.secureUsrW = 1U; + memAccessConfig.secureUsrR = 1U; + memAccessConfig.securePrivX = 1U; + memAccessConfig.securePrivW = 1U; + memAccessConfig.securePrivR = 1U; + + for (uint32_t mrc = 0U; mrc < hwConfig.mrcNumber; mrc++) + { + if (TRDC_IsValidMrc(trdc, mrc)) + { + for (uint32_t i = 0U; i < 8U; i++) + { + TRDC_MrcSetMemoryAccessConfig(trdc, &memAccessConfig, mrc, i); + } + } + } + + for (uint32_t mbc = 0U; mbc < hwConfig.mbcNumber; mbc++) + { + if (TRDC_IsValidMbc(trdc, mbc)) + { + for (uint32_t i = 0U; i < 8U; i++) + { + TRDC_MbcSetMemoryAccessConfig(trdc, &memAccessConfig, mbc, i); + } + } + } + + memset(&mbcBlockConfig, 0, sizeof(mbcBlockConfig)); + mbcBlockConfig.nseEnable = false; + mbcBlockConfig.memoryAccessControlSelect = 0; + + memset(&mrcRegionConfig, 0, sizeof(mrcRegionConfig)); + mrcRegionConfig.memoryAccessControlSelect = 0U; + mrcRegionConfig.valid = true; + mrcRegionConfig.nseEnable = false; + mrcRegionConfig.regionIdx = 0U; + + for (uint32_t domain = 0; domain < hwConfig.domainNumber; domain++) + { + if (TRDC_IsValidDomain(trdc, domain)) + { + /* Set the configuration for MBC. */ + for (uint32_t mbc = 0U; mbc < hwConfig.mbcNumber; mbc++) + { + if (TRDC_IsValidMbc(trdc, mbc)) + { + uint32_t mem_num = TRDC_GetMbcMemNum(trdc, mbc); + for (uint32_t mem = 0; mem < mem_num; mem++) + { + if (TRDC_IsValidMbcMem(trdc, mbc, mem)) + { + trdc_slave_memory_hardware_config_t mbcHwConfig; + TRDC_GetMbcHardwareConfig(trdc, &mbcHwConfig, mbc, mem); + for (uint32_t block = 0; block < mbcHwConfig.blockNum; block++) + { + mbcBlockConfig.domainIdx = domain; + mbcBlockConfig.mbcIdx = mbc; + mbcBlockConfig.slaveMemoryIdx = mem; + mbcBlockConfig.memoryBlockIdx = block; + TRDC_MbcSetMemoryBlockConfig(trdc, &mbcBlockConfig); + } + } + } + } + } + + /* Set the configuration for MRC. */ + for (uint32_t mrc = 0U; mrc < hwConfig.mrcNumber; mrc++) + { + if (TRDC_IsValidMrc(trdc, mrc)) + { + uint32_t start_addr, end_addr; + + if (TRDC_GetMrcRegionAddr(trdc, mrc, &start_addr, &end_addr)) + { + mrcRegionConfig.startAddr = start_addr; + mrcRegionConfig.endAddr = end_addr; + mrcRegionConfig.domainIdx = domain; + mrcRegionConfig.mrcIdx = mrc; + TRDC_MrcSetRegionDescriptorConfig(trdc, &mrcRegionConfig); + } + else + { + assert(false); + } + } + } + } + } +} + +void BOARD_GrantTRDCFullPermissions(void) +{ + /* 1. Request TRDC ownership */ + BOARD_RequestTRDC(true, true, true); + + /* 2. Config DAC. */ + APP_CommonTrdcDACSetting(); + + /* 3. Enable all access control */ + APP_CommonTrdcAccessControlSetting(TRDC1); + APP_CommonTrdcAccessControlSetting(TRDC2); +} + +void BOARD_CommonSetting(void) +{ + BOARD_GrantTRDCFullPermissions(); +} + +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); + +} + +#ifdef BSP_USING_LPUART +void imxrt_uart_pins_init(void) +{ +#ifdef BSP_USING_LPUART1 + CLOCK_EnableClock(kCLOCK_Iomuxc2); /* Turn on LPCG: LPCG is ON. */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AON_08_LPUART1_TX, /* GPIO_AON_08 is configured as LPUART1_TX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AON_09_LPUART1_RX, /* GPIO_AON_09 is configured as LPUART1_RX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AON_08_LPUART1_TX, /* GPIO_AON_08 PAD functional properties : */ + 0x02U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: high driver + Pull / Keep Select Field: Pull Disable, Highz + Pull Up / Down Config. Field: Weak pull down + Open Drain Field: Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AON_09_LPUART1_RX, /* GPIO_AON_09 PAD functional properties : */ + 0x02U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: high driver + Pull / Keep Select Field: Pull Disable, Highz + Pull Up / Down Config. Field: Weak pull down + Open Drain Field: Disabled */ + +#endif + +} +#endif /* BSP_USING_LPUART */ + +#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority + 4 bits for subpriority */ +#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority + 3 bits for subpriority */ +#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority + 2 bits for subpriority */ +#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority + 1 bits for subpriority */ +#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority + 0 bits for subpriority */ + +void rt_hw_board_init() +{ +// BOARD_CommonSetting(); + BOARD_ConfigMPU(); + BOARD_InitPins(); + + BOARD_InitLeds(); + BOARD_BootClockRUN(); + + NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); + + /*init uart device*/ + rt_hw_uart_init(); + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif + +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + +#ifdef RT_USING_HEAP + rt_kprintf("SystemCoreClock: %d Hz\n", SystemCoreClock); + rt_kprintf("Heap: 0x%08x - 0x%08x (Size: %d bytes)\n", + HEAP_BEGIN, HEAP_END, + (uint32_t)HEAP_END - (uint32_t)HEAP_BEGIN); + + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif + +} + diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.h new file mode 100644 index 00000000000..46f34985b9e --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.h @@ -0,0 +1,191 @@ +/* + * Copyright 2021-2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "clock_config.h" +#include "pin_mux.h" +#include "fsl_common.h" +#include "fsl_rgpio.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "MIMXRT1180-EVK" +#ifndef DEBUG_CONSOLE_UART_INDEX +#define DEBUG_CONSOLE_UART_INDEX 1 +#endif + +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_CLK_FREQ BOARD_DebugConsoleSrcFreq() +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#ifndef BOARD_DEBUG_UART_CLK_ROOT +#define BOARD_DEBUG_UART_CLK_ROOT kCLOCK_Root_Lpuart0102 +#endif +#ifndef BOARD_DEBUG_UART_BASEADDR +#define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART1 +#endif +#ifndef BOARD_DEBUG_UART_INSTANCE +#define BOARD_DEBUG_UART_INSTANCE 1U +#endif +#ifndef BOARD_UART_IRQ +#define BOARD_UART_IRQ LPUART1_IRQn +#endif +#ifndef BOARD_UART_IRQ_HANDLER +#define BOARD_UART_IRQ_HANDLER LPUART1_IRQHandler +#endif +#ifndef BOARD_DEBUG_UART_BAUDRATE +#define BOARD_DEBUG_UART_BAUDRATE (115200U) +#endif + +/* Definitions for eRPC MU transport layer */ +#if defined(FSL_FEATURE_MU_SIDE_A) +#define MU_BASE MU1_MUA +#define MU_IRQ MU1_IRQn +#define MU_IRQ_HANDLER MU1_IRQHandler +#endif +#if defined(FSL_FEATURE_MU_SIDE_B) +#define MU_BASE MU1_MUB +#define MU_IRQ MU1_IRQn +#define MU_IRQ_HANDLER MU1_IRQHandler +#endif +#define MU_IRQ_PRIORITY (2) + +/*! @brief The USER_LED used for board */ +#define LOGIC_LED_ON (1U) +#define LOGIC_LED_OFF (0U) +#ifndef BOARD_USER_LED_GPIO +#define BOARD_USER_LED_GPIO RGPIO4 +#endif +#ifndef BOARD_USER_LED_GPIO_PIN +#define BOARD_USER_LED_GPIO_PIN (27U) +#endif + +#define USER_LED_INIT(output) \ + RGPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, output); \ + BOARD_USER_LED_GPIO->PDDR |= (1U << BOARD_USER_LED_GPIO_PIN) /*!< Enable target USER_LED */ +#define USER_LED_OFF() \ + RGPIO_PortClear(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!< Turn off target USER_LED */ +#define USER_LED_ON() RGPIO_PortSet(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!*/ +#if defined(__ARMCC_VERSION) +extern int Image$$ARM_LIB_HEAP$$ZI$$Base; +extern int Image$$ARM_LIB_HEAP$$ZI$$Limit; +#define HEAP_BEGIN ((void *)&Image$$ARM_LIB_HEAP$$ZI$$Base) +#define HEAP_END ((void*)&Image$$ARM_LIB_HEAP$$ZI$$Limit) +#elif defined(__ICCARM__) +#pragma section="HEAP" +#define HEAP_BEGIN (__section_begin("HEAP")) +#define HEAP_END (__section_end("HEAP")) +#elif defined(__GNUC__) +extern int __HeapBase; +extern int __HeapLimit; +#define HEAP_BEGIN ((void *)&__HeapBase) +#define HEAP_END ((void *)&__HeapLimit) +#endif + +/*! @brief The board flash size */ +#define BOARD_FLASH_SIZE (0x1000000U) + +void rt_hw_board_init(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/evkmimxrt1180_cm33.jlinkscript b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/evkmimxrt1180_cm33.jlinkscript new file mode 100644 index 00000000000..23137a7f748 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/evkmimxrt1180_cm33.jlinkscript @@ -0,0 +1,1041 @@ +__constant U32 _INDEX_AHB_AP_CORTEX_M33 = 3; +__constant U32 _AHB_ACC_32BIT_AUTO_INC = (1 << 29) | (1 << 25) | (1 << 24) | (1 << 4) | (2 << 0); +__constant U32 _AHB_ACC_16BIT_AUTO_INC = (1 << 29) | (1 << 25) | (1 << 24) | (1 << 4) | (1 << 0); // HMASTER = DEBUG, Private access, no Auto-increment, Access size: half word; +__constant U32 _ACCESS_AP = 1; +__constant U32 _CM33_CPUID = 0xD210; +__constant U32 _CM7_CPUID = 0x0C27; + +/* ROM trap address for CM33 core, after system reset */ +__constant U32 _ROM_TRAP0_ADDR = 0x10002932; +__constant U32 _ROM_TRAP1_ADDR = 0x100025D4; +__constant U32 _ROM_TRAP2_ADDR = 0x100025D4; + +__constant U32 _SRC_SRSR_ADDR = 0x44460050; +__constant U32 _SRC_SRMASK_ADDR = 0x44460018; +__constant U32 _SRC_SCR_ADDR = 0x44460010; +__constant U32 _SRC_AUTHEN_CTRL_ADDR = 0x44460004; +__constant U32 _SRC_SBMR2_ADDR = 0x44460044; +__constant U32 _BLK_M7_CFG_ADDR = 0x444F0080; + +__constant U32 _DWT_COMP0_ADDR = 0xE0001020; +__constant U32 _DWT_FUNC0_ADDR = 0xE0001028; + +__constant U32 _DCB_DHCSR_ADDR = 0xE000EDF0; +__constant U32 _DCB_DEMCR_ADDR = 0xE000EDFC; + +__constant U32 _SCB_AIRCR_ADDR = 0xE000ED0C; + +__constant U32 _XCACHE_PC_CCR_ADDR = 0x44400000; +__constant U32 _XCACHE_PS_CCR_ADDR = 0x44400800; + +__constant U32 _CM33_MPU_CTRL_ADDR = 0xE000ED94; + +__constant U32 _SI_VER_ADDR = 0x5751804C; + +unsigned int cpuID; +unsigned int rom_trap_addr; + +static int _WriteViaCM33AP16(U32 Addr, U16 Data) { + int r; + + JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 4) | (_INDEX_AHB_AP_CORTEX_M33 << 24)); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL, _AHB_ACC_16BIT_AUTO_INC); + Data = (Data & 0xFFFF) | ((Data & 0xFFFF) << 16); + r = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, Addr); + r |= JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, Data); + return r; +} + +static U32 _ReadViaCM33AP16(U32 Addr) { + U32 r; + + JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 4) | (_INDEX_AHB_AP_CORTEX_M33 << 24)); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL, _AHB_ACC_16BIT_AUTO_INC); + JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, Addr); + JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, &r); + return r; +} + +static int _WriteViaCM33AP32(U32 Addr, U32 Data) { + int r; + + JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 4) | (_INDEX_AHB_AP_CORTEX_M33 << 24)); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL, _AHB_ACC_32BIT_AUTO_INC); + r = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, Addr); + r |= JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, Data); + return r; +} + +static U32 _ReadViaCM33AP32(U32 Addr) { + int r; + + JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 4) | (_INDEX_AHB_AP_CORTEX_M33 << 24)); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL, _AHB_ACC_32BIT_AUTO_INC); + r = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, Addr); + r |= JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, &r); + return r; +} + +/* For Debug Start */ +__constant U32 _DCB_DCRSR_ADDR = 0xE000EDF4; +__constant U32 _DCB_DCRDR_ADDR = 0xE000EDF8; +__constant U32 _SCB_DFSR_ADDR = 0xE000ED30; + +__constant U32 _REG_R0 = 0x0; +__constant U32 _REG_R1 = 0x1; +__constant U32 _REG_R2 = 0x2; +__constant U32 _REG_R3 = 0x3; +__constant U32 _REG_R4 = 0x4; +__constant U32 _REG_R5 = 0x5; +__constant U32 _REG_R6 = 0x6; +__constant U32 _REG_R7 = 0x7; +__constant U32 _REG_R8 = 0x8; +__constant U32 _REG_R9 = 0x9; +__constant U32 _REG_R10 = 0xA; +__constant U32 _REG_R11 = 0xB; +__constant U32 _REG_R12 = 0xC; +__constant U32 _REG_SP = 0xD; +__constant U32 _REG_LR = 0xE; +__constant U32 _REG_PC = 0xF; +__constant U32 _REG_SP_main = 0x11; +__constant U32 _REG_SP_process = 0x12; +__constant U32 _REG_MSPLIM_S = 0x1C; +__constant U32 _REG_PSPLIM_S = 0x1D; +__constant U32 _REG_MSPLIM_NS = 0x1E; +__constant U32 _REG_PSPLIM_NS = 0x1F; + +static U32 _ReadCPUReg(int RegIndex) { + U32 v; + + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_ADDR, _DCB_DCRSR_ADDR); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_DATA, RegIndex); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_ADDR, _DCB_DCRDR_ADDR); + v = JLINK_CORESIGHT_ReadAP(JLINK_CORESIGHT_AP_REG_DATA); + return v; +} + +static U32 _ReadCPURegViaAP(int AP, int RegIndex) { + int r; + + JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 4) | (AP << 24)); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL, _AHB_ACC_32BIT_AUTO_INC); + + r = _ReadCPUReg(RegIndex); + return r; +} + +int debug = 0; + +void ShowDAPInfo(void) +{ + int r; + + if ( debug ) + { + JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 4) | (_INDEX_AHB_AP_CORTEX_M33 << 24)); + r = JLINK_CORESIGHT_ReadAP(JLINK_CORESIGHT_AP_REG_CTRL); + JLINK_SYS_Report1("CM33 AP CSW = ", r); + } +} + +void DBG_ShowCM33Reg(void) +{ + int r, sp, pc; + + r = _ReadViaCM33AP32(_CM33_MPU_CTRL_ADDR); + JLINK_SYS_Report1(" CM33 MPU_CTRL = ", r); + r = _ReadViaCM33AP32(_XCACHE_PC_CCR_ADDR); + JLINK_SYS_Report1(" XCACHE_PC_CCR = ", r); + r = _ReadViaCM33AP32(_XCACHE_PS_CCR_ADDR); + JLINK_SYS_Report1(" XCACHE_PS_CCR = ", r); + + r = _ReadViaCM33AP32(_DWT_COMP0_ADDR); + JLINK_SYS_Report1(" CM33 DWT_COMP0 = ", r); + r = _ReadViaCM33AP32(_DWT_FUNC0_ADDR); + JLINK_SYS_Report1(" CM33 DWT_FUNC0 = ", r); + + r = _ReadViaCM33AP32(_SCB_DFSR_ADDR); + JLINK_SYS_Report1(" CM33 DFSR = ", r); + r = _ReadViaCM33AP32(_DCB_DEMCR_ADDR); + JLINK_SYS_Report1(" CM33 DEMCR = ", r); + r = _ReadViaCM33AP32(_DCB_DHCSR_ADDR); + JLINK_SYS_Report1(" CM33 DHCSR = ", r); + if ( (r & 0x02) != 0) + { + sp = _ReadCPURegViaAP(_INDEX_AHB_AP_CORTEX_M33, _REG_SP); + pc = _ReadCPURegViaAP(_INDEX_AHB_AP_CORTEX_M33, _REG_PC); + JLINK_SYS_Report1(" CM33 PC = ", pc); + JLINK_SYS_Report1(" CM33 SP = ", sp); + } + else + { + JLINK_SYS_Report(" CM33 core is not halted!"); + } +} + +void DBG_ShowCoreReg(void) +{ + int r, sp, pc; + + r = JLINK_MEM_ReadU32(_SCB_DFSR_ADDR); + JLINK_SYS_Report1(" DFSR = ", r); + r = JLINK_MEM_ReadU32(_DCB_DHCSR_ADDR); + JLINK_SYS_Report1(" DHCSR = ", r); + if ( (r & 0x02) != 0) + { + sp = _ReadCPUReg(_REG_SP); + pc = _ReadCPUReg(_REG_PC); + JLINK_SYS_Report1(" PC = ", pc); + JLINK_SYS_Report1(" SP = ", sp); + } + else + { + JLINK_SYS_Report(" Core is not halted!"); + } +} + +void DBG_ShowReg(int seq) +{ + int r; + if( debug ) + { + JLINK_SYS_Report1("Seq: ", seq); + + r = _ReadViaCM33AP32(_SRC_AUTHEN_CTRL_ADDR); + JLINK_SYS_Report1(" AUTHEN_CTRL = ", r); + r = _ReadViaCM33AP32(_SRC_SRSR_ADDR); + JLINK_SYS_Report1(" SRSR = ", r); + r = _ReadViaCM33AP32(_SRC_SRMASK_ADDR); + JLINK_SYS_Report1(" SRMASK = ", r); + r = _ReadViaCM33AP32(_SRC_SCR_ADDR); + JLINK_SYS_Report1(" SCR = ", r); + r = _ReadViaCM33AP32(_BLK_M7_CFG_ADDR); + JLINK_SYS_Report1(" M7_CFG = ", r); + + if(cpuID == _CM7_CPUID) + { + if((r & 0x10) == 0) + { + DBG_ShowCoreReg(); + } + + } + + DBG_ShowCM33Reg(); + } +} +/* For Debug End */ + +void _FLEXSPI1_ModuleReset() +{ + unsigned int reg; + + reg = MEM_ReadU32(0x425E0000); // FlexSPI1->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + reg = MEM_ReadU32(0x425E0000); + MEM_WriteU32(0x425E0000, (reg | 0x1)); + do + { + reg = MEM_ReadU32(0x425E0000); + } while ((reg & 0x1) != 0); + } +} + +void _FLEXSPI1_WaitBusIdle() +{ + unsigned int reg; + reg = MEM_ReadU32(0x425E0000); // FlexSPI1->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + do + { + reg = MEM_ReadU32(0x425E00E0); + } while ((reg & 0x3) != 0x3); + } +} + +void _FLEXSPI1_ClockInit() +{ + _WriteViaCM33AP32(0x54484350, 0x0); // ROSC400M_CTRL1 + + // Set flexspi1 root clock, use ROSC400, div = 4 = 1+3 + MEM_WriteU32(0x54450A80, 0x103); // CLOCK_ROOT[21].CONTROL, FlexSPI1 +} + +void _FLEXSPI1_SetPinForQuadMode(void) { + // Set 4 Pin Mode for JLink + // IOMUXC_GPIO_B2_07_FLEXSPI1_BUS2BIT_A_DQS + MEM_WriteU32(0x42A1023C, 0x17); + MEM_WriteU32(0x42A10544, 0x1); + // IOMUXC_GPIO_B2_08_FLEXSPI1_BUS2BIT_A_SCLK + MEM_WriteU32(0x42A10240, 0x17); + // IOMUXC_GPIO_B2_09_FLEXSPI1_BUS2BIT_A_SS0_B + MEM_WriteU32(0x42A10244, 0x17); + // IOMUXC_GPIO_B2_10_FLEXSPI1_BUS2BIT_A_DATA00 + MEM_WriteU32(0x42A10248, 0x17); + // IOMUXC_GPIO_B2_11_FLEXSPI1_BUS2BIT_A_DATA01 + MEM_WriteU32(0x42A1024C, 0x17); + // IOMUXC_GPIO_B2_12_FLEXSPI1_BUS2BIT_A_DATA02 + MEM_WriteU32(0x42A10250, 0x17); + // IOMUXC_GPIO_B2_13_FLEXSPI1_BUS2BIT_A_DATA03 + MEM_WriteU32(0x42A10254, 0x17); +} + +void _FLEXSPI1_ModuleInit(void) { + + unsigned int reg; + reg = MEM_ReadU32(0x425E0000); + MEM_WriteU32(0x425E0000, (reg & 0xFFFFFFFD)); + + //FLEXSPI1->MCR0 = 0xFFFF8010; + MEM_WriteU32(0x425E0000, 0xFFFF8010); + //FLEXSPI1->MCR2 = 0x200001F7; + MEM_WriteU32(0x425E0008, 0x200001F7); + //FLEXSPI1->AHBCR = 0x78; + MEM_WriteU32(0x425E000C, 0x78); + + //FLEXSPI1->FLSHCR0[0] = 0x00004000; + MEM_WriteU32(0x425E0060, 0x00004000); + + + //FLEXSPI1->FLSHCR4 = 0xC3; + MEM_WriteU32(0x425E0094, 0xC3); + //FLEXSPI1->IPRXFCR = 0x1C; + MEM_WriteU32(0x425E00B8, 0x1C); + + //FLEXSPI1->LUTKEY = 0x5AF05AF0UL; + MEM_WriteU32(0x425E0018, 0x5AF05AF0); + //FLEXSPI1->LUTCR = 0x02; + MEM_WriteU32(0x425E001C, 0x02); + + //FLEXSPI1->LUT[0] = 0x0A1804EB; // AHB Quad Read Change to use Fast Read Quad + MEM_WriteU32(0x425E0200, 0x0A1804EB); + //FLEXSPI1->LUT[1] = 0x26043206; + MEM_WriteU32(0x425E0204, 0x26043206); + //FLEXSPI1->LUT[2] = 0x00000000; + MEM_WriteU32(0x425E0208, 0x00000000); + //FLEXSPI1->LUT[3] = 0x00000000; + MEM_WriteU32(0x425E020C, 0x00000000); + + //FLEXSPI1->LUT[4] = 0x00000406; // Write Enable + MEM_WriteU32(0x425E0210, 0x00000406); + //FLEXSPI1->LUT[5] = 0x00000000; + MEM_WriteU32(0x425E0214, 0x00000000); + //FLEXSPI1->LUT[6] = 0x00000000; + MEM_WriteU32(0x425E0218, 0x00000000); + //FLEXSPI1->LUT[7] = 0x00000000; + MEM_WriteU32(0x425E021C, 0x00000000); + + //FLEXSPI1->LUT[8] = 0x20040401; // Wirte s1 + MEM_WriteU32(0x425E0220, 0x20040401); + //FLEXSPI1->LUT[9] = 0x00000000; + MEM_WriteU32(0x425E0224, 0x00000000); + //FLEXSPI1->LUT[10] = 0x00000000; + MEM_WriteU32(0x425E0228, 0x00000000); + //FLEXSPI1->LUT[11] = 0x00000000; + MEM_WriteU32(0x425E022C, 0x00000000); + + //FLEXSPI1->LUT[12] = 0x24040405; // Read s1 + MEM_WriteU32(0x425E0230, 0x24040405); + //FLEXSPI1->LUT[13] = 0x00000000; + MEM_WriteU32(0x425E0234, 0x00000000); + //FLEXSPI1->LUT[14] = 0x00000000; + MEM_WriteU32(0x425E0238, 0x00000000); + //FLEXSPI1->LUT[15] = 0x00000000; + MEM_WriteU32(0x425E023C, 0x00000000); + + //FLEXSPI1->LUT[16] = 0x00000404; // Write Disable + MEM_WriteU32(0x425E0240, 0x00000404); + //FLEXSPI1->LUT[17] = 0x00000000; + MEM_WriteU32(0x425E0244, 0x00000000); + //FLEXSPI1->LUT[18] = 0x00000000; + MEM_WriteU32(0x425E0248, 0x00000000); + //FLEXSPI1->LUT[19] = 0x00000000; + MEM_WriteU32(0x425E024C, 0x00000000); + + //FLEXSPI1->LUT[20] = 0x20040431; // Wirte s2 + MEM_WriteU32(0x425E0250, 0x20040431); + //FLEXSPI1->LUT[21] = 0x00000000; + MEM_WriteU32(0x425E0254, 0x00000000); + //FLEXSPI1->LUT[22] = 0x00000000; + MEM_WriteU32(0x425E0258, 0x00000000); + //FLEXSPI1->LUT[23] = 0x00000000; + MEM_WriteU32(0x425E025C, 0x00000000); + + //FLEXSPI1->LUT[24] = 0x24040435; // Read s2 + MEM_WriteU32(0x425E0260, 0x24040435); + //FLEXSPI1->LUT[25] = 0x00000000; + MEM_WriteU32(0x425E0264, 0x00000000); + //FLEXSPI1->LUT[26] = 0x00000000; + MEM_WriteU32(0x425E0268, 0x00000000); + //FLEXSPI1->LUT[27] = 0x00000000; + MEM_WriteU32(0x425E026C, 0x00000000); + + //FLEXSPI1->LUT[28] = 0x00000450; // Write Enable Volatile + MEM_WriteU32(0x425E0270, 0x00000450); + //FLEXSPI1->LUT[29] = 0x00000000; + MEM_WriteU32(0x425E0274, 0x00000000); + //FLEXSPI1->LUT[30] = 0x00000000; + MEM_WriteU32(0x425E0278, 0x00000000); + //FLEXSPI1->LUT[31] = 0x00000000; + MEM_WriteU32(0x425E027C, 0x00000000); + + //FLEXSPI1->LUTKEY = 0x5AF05AF0UL; + MEM_WriteU32(0x425E0018, 0x5AF05AF0); + //FLEXSPI1->LUTCR = 0x01; + MEM_WriteU32(0x425E001C, 0x01); +} + +void _FLEXSPI2_ModuleReset() +{ + unsigned int reg; + + reg = MEM_ReadU32(0x445E0000); // FlexSPI2->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + reg = MEM_ReadU32(0x445E0000); + MEM_WriteU32(0x445E0000, (reg | 0x1)); + do + { + reg = MEM_ReadU32(0x445E0000); + } while ((reg & 0x1) != 0); + } +} + +void _FLEXSPI2_WaitBusIdle() +{ + unsigned int reg; + + reg = MEM_ReadU32(0x445E0000); // FlexSPI2->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + do + { + reg = MEM_ReadU32(0x445E00E0); + } while ((reg & 0x3) != 0x3); + } +} + +void _FlexSPI2_SetPinForOctalMode() +{ + // Config IOMUX for FlexSPI2 + MEM_WriteU32(0x42A10088, 0x00000013); // FLEXSPI2_B_DATA03 + MEM_WriteU32(0x42A1008C, 0x00000013); // FLEXSPI2_B_DATA02 + MEM_WriteU32(0x42A10090, 0x00000013); // FLEXSPI2_B_DATA01 + MEM_WriteU32(0x42A10094, 0x00000013); // FLEXSPI2_B_DATA00 + MEM_WriteU32(0x42A1009C, 0x00000013); // FLEXSPI2_A_DATA00 + MEM_WriteU32(0x42A100A0, 0x00000013); // FLEXSPI2_A_DATA01 + MEM_WriteU32(0x42A100A4, 0x00000013); // FLEXSPI2_A_DATA02 + MEM_WriteU32(0x42A100A8, 0x00000013); // FLEXSPI2_A_DATA03 + MEM_WriteU32(0x42A100AC, 0x00000013); // FLEXSPI2_A_SS0_B + MEM_WriteU32(0x42A100B0, 0x00000013); // FLEXSPI2_A_DQS + MEM_WriteU32(0x42A100B4, 0x00000013); // FLEXSPI2_A_SCLK + + //The input daisy!! + MEM_WriteU32(0x42A10594, 0x00000001); // FLEXSPI2_B_DATA03 + MEM_WriteU32(0x42A10590, 0x00000001); // FLEXSPI2_B_DATA02 + MEM_WriteU32(0x42A1058C, 0x00000001); // FLEXSPI2_B_DATA01 + MEM_WriteU32(0x42A10588, 0x00000001); // FLEXSPI2_B_DATA00 + MEM_WriteU32(0x42A10578, 0x00000000); // FLEXSPI2_A_DATA00 + MEM_WriteU32(0x42A1057C, 0x00000000); // FLEXSPI2_A_DATA01 + MEM_WriteU32(0x42A10580, 0x00000000); // FLEXSPI2_A_DATA02 + MEM_WriteU32(0x42A10584, 0x00000000); // FLEXSPI2_A_DATA03 + MEM_WriteU32(0x42A10570, 0x00000000); // FLEXSPI2_A_DQS + MEM_WriteU32(0x42A10598, 0x00000000); // FLEXSPI2_A_SCLK + + // PAD ctrl + MEM_WriteU32(0x42A102D0, 0x00000008); // FLEXSPI2_B_DATA03 + MEM_WriteU32(0x42A102D4, 0x00000008); // FLEXSPI2_B_DATA02 + MEM_WriteU32(0x42A102D8, 0x00000008); // FLEXSPI2_B_DATA01 + MEM_WriteU32(0x42A102DC, 0x00000008); // FLEXSPI2_B_DATA00 + MEM_WriteU32(0x42A102E4, 0x00000008); // FLEXSPI2_A_DATA00 + MEM_WriteU32(0x42A102E8, 0x00000008); // FLEXSPI2_A_DATA01 + MEM_WriteU32(0x42A102EC, 0x00000008); // FLEXSPI2_A_DATA02 + MEM_WriteU32(0x42A102F0, 0x00000008); // FLEXSPI2_A_DATA03 + MEM_WriteU32(0x42A102F4, 0x00000008); // FLEXSPI2_A_SS0_B + MEM_WriteU32(0x42A102F8, 0x00000008); // FLEXSPI2_A_DQS + MEM_WriteU32(0x42A102FC, 0x00000008); // FLEXSPI2_A_SCLK +} + +void _FLEXSPI2_ClockInit() +{ + _WriteViaCM33AP32(0x54484350, 0x0); // ROSC400M_CTRL1 + + // Set flexspi2 root clock, use ROSC400, div = 2 = 1+1 + MEM_WriteU32(0x44450B00, 0x101); // CLOCK_ROOT[22].CONTROL, FlexSPI2 +} + +void _FLEXSPI2_ModuleInit() +{ + // Config FlexSPI2 Registers + + unsigned int reg; + reg = MEM_ReadU32(0x445E0000); + MEM_WriteU32(0x445E0000, (reg & 0xFFFFFFFD)); + + _FLEXSPI2_ModuleReset(); + + MEM_WriteU32(0x445E0000, 0xFFFF3032); // MCR0 + MEM_WriteU32(0x445E0004, 0xFFFFFFFF); // MCR1 + MEM_WriteU32(0x445E0008, 0x200001F7); // MCR2 + MEM_WriteU32(0x445E000C, 0x00000078); // AHBCR prefetch enable + MEM_WriteU32(0x445E0020, 0x800F0000); // AHBRXBUF0CR0 + MEM_WriteU32(0x445E0024, 0x800F0000); // AHBRXBUF1CR0 + MEM_WriteU32(0x445E0028, 0x800F0000); // AHBRXBUF2CR0 + MEM_WriteU32(0x445E002C, 0x800F0000); // AHBRXBUF3CR0 + MEM_WriteU32(0x445E0030, 0x800F0000); // AHBRXBUF4CR0 + MEM_WriteU32(0x445E0034, 0x800F0000); // AHBRXBUF5CR0 + MEM_WriteU32(0x445E0038, 0x80000020); // AHBRXBUF6CR0 + MEM_WriteU32(0x445E003C, 0x80000020); // AHBRXBUF7CR0 + MEM_WriteU32(0x445E00B8, 0x00000000); // IPRXFCR + MEM_WriteU32(0x445E00BC, 0x00000000); // IPTXFCR + + MEM_WriteU32(0x445E0060, 0x00000000); // FLASHA1CR0 + MEM_WriteU32(0x445E0064, 0x00000000); // FLASHA2CR0 + MEM_WriteU32(0x445E0068, 0x00000000); // FLASHB1CR0 + MEM_WriteU32(0x445E006C, 0x00000000); // FLASHB2CR0 + + _FLEXSPI2_WaitBusIdle(); + + MEM_WriteU32(0x445E0060, 0x00002000); // FLASHA1CR0 + MEM_WriteU32(0x445E0070, 0x00021C63); // FLASHA1CR1 + MEM_WriteU32(0x445E0080, 0x00000100); // FLASHA1CR2 + + _FLEXSPI2_WaitBusIdle(); + + MEM_WriteU32(0x445E00C0, 0x00000079); // DLLCRA + MEM_WriteU32(0x445E0000, 0xFFFF3030); // MCR0 + + do + { + reg = MEM_ReadU32(0x445E00E8); + } while (0x3 != (reg & 0x3)); + JLINK_SYS_Sleep(1); + // __delay(100);//100us + + MEM_WriteU32(0x445E0000, 0xFFFF3032); // MCR0 + MEM_WriteU32(0x445E0094, 0x000000C2); // FLASHCR4 + MEM_WriteU32(0x445E0094, 0x000000C6); // FLASHCR4 + MEM_WriteU32(0x445E0000, 0xFFFF3030); // MCR0 + + _FLEXSPI2_WaitBusIdle(); + + MEM_WriteU32(0x445E0018, 0x5AF05AF0); // LUTKEY + MEM_WriteU32(0x445E001C, 0x00000002); // LUTCR + MEM_WriteU32(0x445E0200, 0x8B1887A0); // LUT[0] + MEM_WriteU32(0x445E0204, 0xB7078F10); // LUT[1] + MEM_WriteU32(0x445E0208, 0x0000A704); // LUT[2] + MEM_WriteU32(0x445E020C, 0x00000000); // LUT[3] + MEM_WriteU32(0x445E0210, 0x8B188720); // LUT[4] + MEM_WriteU32(0x445E0214, 0xB7078F10); // LUT[5] + MEM_WriteU32(0x445E0218, 0x0000A304); // LUT[6] + MEM_WriteU32(0x445E021C, 0x00000000); // LUT[7] + MEM_WriteU32(0x445E0220, 0x8B1887E0); // LUT[8] + MEM_WriteU32(0x445E0224, 0xB7078F10); // LUT[9] + MEM_WriteU32(0x445E0228, 0x0000A704); // LUT[10] + MEM_WriteU32(0x445E022C, 0x00000000); // LUT[11] + MEM_WriteU32(0x445E0230, 0x8B188760); // LUT[12] + MEM_WriteU32(0x445E0234, 0xA3028F10); // LUT[13] + MEM_WriteU32(0x445E0238, 0x00000000); // LUT[14] + MEM_WriteU32(0x445E023C, 0x00000000); // LUT[15] + MEM_WriteU32(0x445E0240, 0x00000000); // LUT[16] + MEM_WriteU32(0x445E0244, 0x00000000); // LUT[17] + MEM_WriteU32(0x445E0248, 0x00000000); // LUT[18] + MEM_WriteU32(0x445E024C, 0x00000000); // LUT[19] + MEM_WriteU32(0x445E0018, 0x5AF05AF0); // LUTKEY + MEM_WriteU32(0x445E001C, 0x00000001); // LUTCR + + /* Restore hyperram CR0 register */ + MEM_WriteU32(0x445E00A0, 0x00001000); // IPCR0 + MEM_WriteU32(0x445E00A4, 0x00030002); // IPCR1 + MEM_WriteU32(0x445E00BC, 0x00000001); // IPTXFCR + MEM_WriteU32(0x445E0180, 0x2F8F2F8F); // TFDR 0x8F2F is default value of W756/7x of CR0 + MEM_WriteU32(0x445E0014, 0x00000040); // INTR + MEM_WriteU32(0x445E00B0, 0x00000001); // IPCMD + do + { + reg = MEM_ReadU32(0x445E0014); // INTR + } while ((reg & 0x1) == 0x0); + MEM_WriteU32(0x445E0014, 0x00000001); // INTR + + /* Restore hyperram CR1 register */ + MEM_WriteU32(0x445E00A0, 0x00001002); // IPCR0 + MEM_WriteU32(0x445E00A4, 0x00030002); // IPCR1 + MEM_WriteU32(0x445E00BC, 0x00000001); // IPTXFCR + MEM_WriteU32(0x445E0180, 0xC1FFC1FF); // TFDR 0xFFC1 is default value of W756/7x of CR1 + MEM_WriteU32(0x445E0014, 0x00000040); // INTR + MEM_WriteU32(0x445E00B0, 0x00000001); // IPCMD + do + { + reg = MEM_ReadU32(0x445E0014); // INTR + } while ((reg & 0x1) == 0x0); + MEM_WriteU32(0x445E0014, 0x00000001); // INTR + + _FLEXSPI2_ModuleReset(); +} + +void CM7_InitTCM(U32 targetAddr, U32 size) { + U32 reg; + + reg = _ReadViaCM33AP32(0x52010000); // DMA4->TDC[0].CH_CSR + + if((reg & 0x80000000) != 0) + { + // DMA channel is active, wait it get finished + do + { + reg = _ReadViaCM33AP32(0x52010000); // DMA4->TDC[0].CH_CSR + } while((reg & 0x40000000) == 0); + } + + _WriteViaCM33AP32(0x52010000, 0x40000000); // DMA4->TDC[0].CH_CSR, clear DONE flag + + _WriteViaCM33AP32(0x5201002C, 0x00000000); // DMA4->TCD[0].SLAST_SGA + _WriteViaCM33AP32(0x52010038, 0x00000000); // DMA4->TCD[0].DLAST_SGA + + _WriteViaCM33AP32(0x52010000, 0x40000000); // DMA4->TCD[0].CH_CSR + + _WriteViaCM33AP32(0x52010020, 0x20484000); // DMA4->TCD[0].SADDR + _WriteViaCM33AP32(0x52010030, targetAddr); // DMA4->TCD[0].DADDR + _WriteViaCM33AP32(0x52010028, size); // DMA4->TCD[0].NBYTES_MLOFFNO + _WriteViaCM33AP16(0x52010036, 0x1); // DMA4->TCD[0].ELINKNO + _WriteViaCM33AP16(0x5201003E, 0x1); // DMA4->TCD[0].BITER_ELINKNO + _WriteViaCM33AP16(0x52010026, 0x0303); // DMA4->TCD[0].ATTR + _WriteViaCM33AP16(0x52010024, 0x0); // DMA4->TCD[0].SOFF + _WriteViaCM33AP16(0x52010034, 0x8); // DMA4->TCD[0].DOFF + _WriteViaCM33AP32(0x52010000, 0x7); // DMA4->TDC[0].CH_CSR + _WriteViaCM33AP16(0x5201003C, 0x8); // DMA4->TCD[0].CSR + _WriteViaCM33AP16(0x5201003C, 0x9); // DMA4->TCD[0].CSR + + do + { + reg = _ReadViaCM33AP32(0x52010000); // DMA4->TDC[0].CH_CSR + } while((reg & 0x40000000) == 0); + _WriteViaCM33AP32(0x52010000, 0x40000000); // DMA4->TDC[0].CH_CSR, clear DONE flag +} + +void CM7_KickOff(int ecc_init) +{ + U32 reg, resp1, resp2; + + reg = _ReadViaCM33AP32(_BLK_M7_CFG_ADDR); + if((reg & 0x10) == 0) + { + JLINK_SYS_Report("CM7 is running already"); + } + else + { + JLINK_SYS_Report("************* Begin Operations to Enable CM7 ***********************"); + + // Clock Preparation + JLINK_SYS_Report("******** Prepare Clock *********"); + _WriteViaCM33AP32(0x54484350, 0x0); // ROSC400M_CTRL1 + _WriteViaCM33AP32(0x54450000, 0x100); // CLOCK_ROOT[0].CONTROL, CM7 + + // Release CM7 + _WriteViaCM33AP32(_SRC_SCR_ADDR, 0x1); + + if (ecc_init) + { + // DMA initialization + JLINK_SYS_Report("******** DMA operation *********"); + CM7_InitTCM(0x303C0000, 0x40000); + CM7_InitTCM(0x30400000, 0x40000); + } + + // Making Landing Zone + JLINK_SYS_Report("******** Creating Landing Zone *********"); + _WriteViaCM33AP32(0x303C0000, 0x20020000); + _WriteViaCM33AP32(0x303C0004, 0x00000009); + _WriteViaCM33AP32(0x303C0008, 0xE7FEE7FE); + + // VTOR 0x00 + _WriteViaCM33AP32(_BLK_M7_CFG_ADDR, 0x0010); + + // Trigger ELE + JLINK_SYS_Report("******** ELE Trigger *********"); + _WriteViaCM33AP32(0x57540200, 0x17d20106); // MU_RT_S3MUA->TR[0] + resp1 = _ReadViaCM33AP32(0x57540280); // MU_RT_S3MUA->RR[0] + resp2 = _ReadViaCM33AP32(0x57540284); // MU_RT_S3MUA->RR[1] + JLINK_SYS_Report1("ELE RESP1 : ", resp1); + JLINK_SYS_Report1("ELE RESP2 : ", resp2); + + // Deassert CM7 Wait + JLINK_SYS_Report("******** Kickoff CM7 *********"); + _WriteViaCM33AP32(_BLK_M7_CFG_ADDR, 0x0); + } +} + +void DAP_Init(void) +{ + JLINK_CORESIGHT_Configure(""); + + CORESIGHT_AddAP(0, CORESIGHT_AHB_AP); + CORESIGHT_AddAP(1, CORESIGHT_APB_AP); + CORESIGHT_AddAP(2, CORESIGHT_AHB_AP); + CORESIGHT_AddAP(3, CORESIGHT_AHB_AP); + CORESIGHT_AddAP(4, CORESIGHT_APB_AP); + CORESIGHT_AddAP(5, CORESIGHT_APB_AP); + CORESIGHT_AddAP(6, CORESIGHT_APB_AP); + + JLINK_SYS_Report("***************************************************"); + if(cpuID == _CM7_CPUID) + { + CPU = CORTEX_M7; + CORESIGHT_IndexAHBAPToUse = 2; + JLINK_SYS_Report("Current core is CM7"); + } + else if(cpuID == _CM33_CPUID) + { + CPU = CORTEX_M33; + CORESIGHT_IndexAHBAPToUse = 3; + JLINK_SYS_Report("Current core is CM33"); + + ShowDAPInfo(); + CORESIGHT_AHBAPCSWDefaultSettings = (1<<29)|(1<<25)|(1<<24); + } + else + { + JLINK_SYS_Report1("Wrong CPU ID: ", cpuID); + } + JLINK_SYS_Report("***************************************************"); +} + +void CM33_Halt(void) +{ + U32 reg; + + reg = (_ReadViaCM33AP32(_SRC_SBMR2_ADDR) >> 24) & 0x3F; + + if((reg == 8) || (reg == 9)) // Serial Download Mode, or Boot From Fuse + { + JLINK_SYS_Report("Not flash execution mode, check if CM33 is halted..."); + + reg = _ReadViaCM33AP32(_DCB_DHCSR_ADDR); + + if(0 == (reg & 0x02)) + { + JLINK_SYS_Report1("CM33 is not halted, trying to halt it. CM33 DHCSR: ", reg); + + _WriteViaCM33AP32(_DCB_DHCSR_ADDR, 0xA05F0001); // Enable CM33 debug control + _WriteViaCM33AP32(_DCB_DHCSR_ADDR, 0xA05F0003); // Halt CM33 + reg = _ReadViaCM33AP32(_DCB_DHCSR_ADDR); + if(0 != (reg & 0x02)) + { + JLINK_SYS_Report1("CM33 is halted now. CM33 DHCSR: ", reg); + } + else + { + JLINK_SYS_Report1("CM33 still running, halt failed. CM33 DHCSR: ", reg); + } + } + else + { + JLINK_SYS_Report1("CM33 is halted. CM33 DHCSR: ", reg); + } + } + else + { + JLINK_SYS_Report("Flash execution mode, leave CM33 run status as it was..."); + } +} + +void Flash_Init() { + JLINK_SYS_Report("***************************************************"); + JLINK_SYS_Report("Init Flash"); + + _FLEXSPI1_WaitBusIdle(); + _FLEXSPI1_ModuleReset(); + + _FLEXSPI1_SetPinForQuadMode(); + _FLEXSPI1_ClockInit(); + _FLEXSPI1_ModuleInit(); + + JLINK_SYS_Report("***************************************************"); +} + +void HyperRAM_Init() +{ + JLINK_SYS_Report("***************************************************"); + JLINK_SYS_Report("Init HyperRAM"); + + _FLEXSPI2_WaitBusIdle(); + _FLEXSPI2_ModuleReset(); + + _FlexSPI2_SetPinForOctalMode(); + _FLEXSPI2_ClockInit(); + _FLEXSPI2_ModuleInit(); + + JLINK_SYS_Report("***************************************************"); +} + +void CM33_ClearNVIC(void) { + JLINK_SYS_Report("***************************************************"); + JLINK_SYS_Report("Clear NVIC"); + JLINK_SYS_Report("***************************************************"); + JLINK_MEM_Fill(0xE000E180, 0x40, 0xFF); + JLINK_MEM_Fill(0xE000E280, 0x40, 0xFF); +} + +int InitTarget(void) +{ + int r; + cpuID = _CM33_CPUID; + + DAP_Init(); + + if(cpuID == _CM7_CPUID) + { + CM33_Halt(); + CM7_KickOff(1); + + /* Avoid to access TPIU to prevent soc hang */ + JLINK_ExecCommand("map region 0xE0040000-0xE0040FFF X"); // Mark region as illegal + } + + r = _ReadViaCM33AP32(_SI_VER_ADDR) & 0xF; + + if ( r == 1 ) + { + rom_trap_addr = _ROM_TRAP1_ADDR; + } + else if ( r == 2 ) + { + rom_trap_addr = _ROM_TRAP2_ADDR; + } + else + { + rom_trap_addr = _ROM_TRAP0_ADDR; + } + JLINK_SYS_Report1("SI_VER = ", r); + JLINK_SYS_Report1("TRAP = ", rom_trap_addr); + + return 0; +} + +int SetupTarget(void) +{ + return 0; +} + +void ResetTarget_CM33(void) +{ + int r, w; + int comp, func; + int core_reset_request_bit_mask; + + core_reset_request_bit_mask = 0x100; /* for CM33 core */ + + DBG_ShowReg(0); + + /* Halt the CPU and wait sometime for possible peripheral operation finish */ + JLINK_TARGET_Halt(); + JLINK_SYS_Sleep(10); + + r = JLINK_TARGET_IsHalted(); + if (r != 1) + { + JLINK_SYS_Report("ERR: CM33 core can't be halted!"); + } + + DBG_ShowReg(1); + + /* check and enable core request system reset */ + r = JLINK_MEM_ReadU32(_SRC_SRMASK_ADDR); + if ( (r & core_reset_request_bit_mask) != 0 ) + { + if ( (r & (core_reset_request_bit_mask<<16)) == 0 ) + { + w = r & (~core_reset_request_bit_mask); + r = JLINK_MEM_ReadU32(_SRC_AUTHEN_CTRL_ADDR); + if ( (r & 0x80) == 0 ) + { + JLINK_SYS_Report("Enable system reset via CM33 core reset"); + JLINK_MEM_WriteU32(_SRC_SRMASK_ADDR, w); + ShowDAPInfo(); + } + else + { + JLINK_SYS_Report("ERR: Core reset request is masked and all mask are locked!"); + } + } + else + { + JLINK_SYS_Report("ERR: Core reset request is masked and locked!"); + } + } + + DBG_ShowReg(2); + + JLINK_SYS_Report("Set CM33 watch point"); + comp = JLINK_MEM_ReadU32(_DWT_COMP0_ADDR); /* Save the DWT register and restore them later */ + func = JLINK_MEM_ReadU32(_DWT_FUNC0_ADDR); + JLINK_MEM_WriteU32(_DWT_COMP0_ADDR, rom_trap_addr); + JLINK_MEM_WriteU32(_DWT_FUNC0_ADDR, 0x00000412); + + /* Clear the reset status to avoid ROM clean the core TCM after reset */ + r = JLINK_MEM_ReadU32(_SRC_SRSR_ADDR); + JLINK_MEM_WriteU32(_SRC_SRSR_ADDR, r); + + DBG_ShowReg(3); + + JLINK_SYS_Report("Execute SYSRESETREQ via AIRCR"); + JLINK_MEM_WriteU32(_SCB_AIRCR_ADDR, 0x05FA0004); + JLINK_SYS_Sleep(100); + + r = JLINK_MEM_ReadU32(_DWT_FUNC0_ADDR); + if ((r & 0x01000000) == 0) + { + JLINK_SYS_Report("ERR: CM33 core is not trapped!"); + } + + DBG_ShowReg(4); + + r = JLINK_TARGET_IsHalted(); + if (r == 1) + { + JLINK_SYS_Report("restore CM33 watch point"); + JLINK_MEM_WriteU32(_DWT_COMP0_ADDR, comp); + JLINK_MEM_WriteU32(_DWT_FUNC0_ADDR, func); + } + else + { + JLINK_SYS_Report("ERR: CM33 is not halted after reset!"); + } +} + +void ResetTarget_CM7(void) +{ + int r, w; + int comp, func; + int core_reset_request_bit_mask; + int mem_0, mem_1, mem_2; + + core_reset_request_bit_mask = 0x400; /* for CM7 core */ + + DBG_ShowReg(0); + + /* Halt the CPU and wait sometime for possible peripheral operation finish */ + JLINK_TARGET_Halt(); + JLINK_SYS_Sleep(10); + + r = JLINK_TARGET_IsHalted(); + if (r != 1) + { + JLINK_SYS_Report("ERR: CM7 core can't be halted!"); + } + + DBG_ShowReg(1); + + /* check and enable core request system reset */ + r = JLINK_MEM_ReadU32(_SRC_SRMASK_ADDR); + if ( (r & core_reset_request_bit_mask) != 0 ) + { + if ( (r & (core_reset_request_bit_mask<<16)) == 0 ) + { + w = r & (~core_reset_request_bit_mask); + r = JLINK_MEM_ReadU32(_SRC_AUTHEN_CTRL_ADDR); + if ( (r & 0x80) == 0 ) + { + JLINK_SYS_Report("Enable system reset via CM7 core reset"); + JLINK_MEM_WriteU32(_SRC_SRMASK_ADDR, w); + } + else + { + JLINK_SYS_Report("ERR: Core reset request is masked and all mask are locked!"); + } + } + else + { + JLINK_SYS_Report("ERR: Core reset request is masked and locked!"); + } + } + + DBG_ShowReg(2); + + /* Clear the reset status to avoid ROM clean the core TCM after reset */ + r = JLINK_MEM_ReadU32(_SRC_SRSR_ADDR); + JLINK_MEM_WriteU32(_SRC_SRSR_ADDR, r); + + DBG_ShowReg(3); + + /* CM7_KickOff will use the first 3 words(32bits) of CM7 ITCM, save and restore them later */ + mem_0 = JLINK_MEM_ReadU32(0); + mem_1 = JLINK_MEM_ReadU32(4); + mem_2 = JLINK_MEM_ReadU32(8); + + JLINK_SYS_Report("Set CM33 watch point"); + _WriteViaCM33AP32(_DCB_DHCSR_ADDR, 0xA05F0003); // Enable Debug and halt CM33 core + comp = _ReadViaCM33AP32(_DWT_COMP0_ADDR); /* Save the DWT register and restore them later after reset */ + func = _ReadViaCM33AP32(_DWT_FUNC0_ADDR); + _WriteViaCM33AP32(_DCB_DEMCR_ADDR, 0x01000000); // Enable DWT of CM33 core + _WriteViaCM33AP32(_DWT_COMP0_ADDR, rom_trap_addr); + _WriteViaCM33AP32(_DWT_FUNC0_ADDR, 0x00000412); + + DBG_ShowReg(4); + + JLINK_SYS_Report("Execute SYSRESETREQ via AIRCR"); + JLINK_MEM_WriteU32(_SCB_AIRCR_ADDR, 0x05FA0004); + JLINK_SYS_Sleep(100); + + r = _ReadViaCM33AP32(_DWT_FUNC0_ADDR); + if ((r & 0x01000000) == 0) + { + JLINK_SYS_Report("ERR: CM33 core is not trapped after reset!"); + } + + DBG_ShowReg(5); + + CM7_KickOff(0); + + // Halt CM7 core + JLINK_MEM_WriteU32(_DCB_DHCSR_ADDR, 0xA05F0003); + + DBG_ShowReg(6); + + r = JLINK_TARGET_IsHalted(); + if (r == 1) + { + JLINK_SYS_Report("restore CM7 ITCM"); + + JLINK_MEM_WriteU32(0, mem_0); + JLINK_MEM_WriteU32(4, mem_1); + JLINK_MEM_WriteU32(8, mem_2); + + JLINK_SYS_Report("restore CM33 watch points"); + _WriteViaCM33AP32(_DWT_COMP0_ADDR, comp); + _WriteViaCM33AP32(_DWT_FUNC0_ADDR, func); + } + else + { + JLINK_SYS_Report("ERR: CM7 core can not be halted!"); + } +} + +void ResetTarget(void) { + if(cpuID == _CM7_CPUID) + { + ResetTarget_CM7(); + } + else if(cpuID == _CM33_CPUID) + { + ResetTarget_CM33(); + } +} + +int AfterResetTarget(void) +{ + U32 reg; + + if(cpuID == _CM33_CPUID) + { + // CM33 NVIC may be enabled by ROM after reset + CM33_ClearNVIC(); + } + + Flash_Init(); + HyperRAM_Init(); + + return 0; +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/evkmimxrt1180_flexspi_nor_cm33.ini b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/evkmimxrt1180_flexspi_nor_cm33.ini new file mode 100644 index 00000000000..993fb2be1ea --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/evkmimxrt1180_flexspi_nor_cm33.ini @@ -0,0 +1,417 @@ +/* + * Copyright 2023-2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +FUNC void _FLEXSPI1_ModuleReset(void) +{ + unsigned int reg; + + reg = _RDWORD(0x425E0000); // FlexSPI1->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + reg = _RDWORD(0x425E0000); + _WDWORD(0x425E0000, (reg | 0x1)); + do + { + reg = _RDWORD(0x425E0000); + } while ((reg & 0x1) != 0); + } +} + +FUNC void _FLEXSPI1_WaitBusIdle(void) +{ + unsigned int reg; + reg = _RDWORD(0x425E0000); // FlexSPI1->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + do + { + reg = _RDWORD(0x425E00E0); + } while ((reg & 0x3) != 0x3); + } +} + +FUNC void _FLEXSPI1_ClockInit(void) +{ + _WDWORD(0x54484350, 0x0); // ROSC400M_CTRL1 + + // Set flexspi1 root clock, use ROSC400, div = 4 = 1+3 + _WDWORD(0x54450A80, 0x103); // CLOCK_ROOT[21].CONTROL, FlexSPI1 +} + +FUNC void _FLEXSPI1_SetPinForQuadMode(void) { + // Set 4 Pin Mode + // IOMUXC_GPIO_B2_07_FLEXSPI1_BUS2BIT_A_DQS + _WDWORD(0x42A1023C, 0x17); + _WDWORD(0x42A10544, 0x1); + // IOMUXC_GPIO_B2_08_FLEXSPI1_BUS2BIT_A_SCLK + _WDWORD(0x42A10240, 0x17); + // IOMUXC_GPIO_B2_09_FLEXSPI1_BUS2BIT_A_SS0_B + _WDWORD(0x42A10244, 0x17); + // IOMUXC_GPIO_B2_10_FLEXSPI1_BUS2BIT_A_DATA00 + _WDWORD(0x42A10248, 0x17); + // IOMUXC_GPIO_B2_11_FLEXSPI1_BUS2BIT_A_DATA01 + _WDWORD(0x42A1024C, 0x17); + // IOMUXC_GPIO_B2_12_FLEXSPI1_BUS2BIT_A_DATA02 + _WDWORD(0x42A10250, 0x17); + // IOMUXC_GPIO_B2_13_FLEXSPI1_BUS2BIT_A_DATA03 + _WDWORD(0x42A10254, 0x17); +} + +FUNC void _FLEXSPI1_ModuleInit(void) { + + unsigned int reg; + reg = _RDWORD(0x425E0000); + _WDWORD(0x425E0000, (reg & 0xFFFFFFFD)); + + //FLEXSPI1->MCR0 = 0xFFFF8010; + _WDWORD(0x425E0000, 0xFFFF8010); + //FLEXSPI1->MCR2 = 0x200001F7; + _WDWORD(0x425E0008, 0x200001F7); + //FLEXSPI1->AHBCR = 0x78; + _WDWORD(0x425E000C, 0x78); + + //FLEXSPI1->FLSHCR0[0] = 0x00004000; + _WDWORD(0x425E0060, 0x00004000); + + //FLEXSPI1->FLSHCR4 = 0xC3; + _WDWORD(0x425E0094, 0xC3); + //FLEXSPI1->IPRXFCR = 0x1C; + _WDWORD(0x425E00B8, 0x1C); + + //FLEXSPI1->LUTKEY = 0x5AF05AF0UL; + _WDWORD(0x425E0018, 0x5AF05AF0); + //FLEXSPI1->LUTCR = 0x02; + _WDWORD(0x425E001C, 0x02); + + //FLEXSPI1->LUT[0] = 0x0A1804EB; // AHB Quad Read Change to use Fast Read Quad + _WDWORD(0x425E0200, 0x0A1804EB); + //FLEXSPI1->LUT[1] = 0x26043206; + _WDWORD(0x425E0204, 0x26043206); + //FLEXSPI1->LUT[2] = 0x00000000; + _WDWORD(0x425E0208, 0x00000000); + //FLEXSPI1->LUT[3] = 0x00000000; + _WDWORD(0x425E020C, 0x00000000); + + //FLEXSPI1->LUT[4] = 0x00000406; // Write Enable + _WDWORD(0x425E0210, 0x00000406); + //FLEXSPI1->LUT[5] = 0x00000000; + _WDWORD(0x425E0214, 0x00000000); + //FLEXSPI1->LUT[6] = 0x00000000; + _WDWORD(0x425E0218, 0x00000000); + //FLEXSPI1->LUT[7] = 0x00000000; + _WDWORD(0x425E021C, 0x00000000); + + //FLEXSPI1->LUT[8] = 0x20040401; // Wirte s1 + _WDWORD(0x425E0220, 0x20040401); + //FLEXSPI1->LUT[9] = 0x00000000; + _WDWORD(0x425E0224, 0x00000000); + //FLEXSPI1->LUT[10] = 0x00000000; + _WDWORD(0x425E0228, 0x00000000); + //FLEXSPI1->LUT[11] = 0x00000000; + _WDWORD(0x425E022C, 0x00000000); + + //FLEXSPI1->LUT[12] = 0x24040405; // Read s1 + _WDWORD(0x425E0230, 0x24040405); + //FLEXSPI1->LUT[13] = 0x00000000; + _WDWORD(0x425E0234, 0x00000000); + //FLEXSPI1->LUT[14] = 0x00000000; + _WDWORD(0x425E0238, 0x00000000); + //FLEXSPI1->LUT[15] = 0x00000000; + _WDWORD(0x425E023C, 0x00000000); + + //FLEXSPI1->LUT[16] = 0x00000404; // Write Disable + _WDWORD(0x425E0240, 0x00000404); + //FLEXSPI1->LUT[17] = 0x00000000; + _WDWORD(0x425E0244, 0x00000000); + //FLEXSPI1->LUT[18] = 0x00000000; + _WDWORD(0x425E0248, 0x00000000); + //FLEXSPI1->LUT[19] = 0x00000000; + _WDWORD(0x425E024C, 0x00000000); + + //FLEXSPI1->LUT[20] = 0x20040431; // Wirte s2 + _WDWORD(0x425E0250, 0x20040431); + //FLEXSPI1->LUT[21] = 0x00000000; + _WDWORD(0x425E0254, 0x00000000); + //FLEXSPI1->LUT[22] = 0x00000000; + _WDWORD(0x425E0258, 0x00000000); + //FLEXSPI1->LUT[23] = 0x00000000; + _WDWORD(0x425E025C, 0x00000000); + + //FLEXSPI1->LUT[24] = 0x24040435; // Read s2 + _WDWORD(0x425E0260, 0x24040435); + //FLEXSPI1->LUT[25] = 0x00000000; + _WDWORD(0x425E0264, 0x00000000); + //FLEXSPI1->LUT[26] = 0x00000000; + _WDWORD(0x425E0268, 0x00000000); + //FLEXSPI1->LUT[27] = 0x00000000; + _WDWORD(0x425E026C, 0x00000000); + + //FLEXSPI1->LUT[28] = 0x00000450; // Write Enable Volatile + _WDWORD(0x425E0270, 0x00000450); + //FLEXSPI1->LUT[29] = 0x00000000; + _WDWORD(0x425E0274, 0x00000000); + //FLEXSPI1->LUT[30] = 0x00000000; + _WDWORD(0x425E0278, 0x00000000); + //FLEXSPI1->LUT[31] = 0x00000000; + _WDWORD(0x425E027C, 0x00000000); + + //FLEXSPI1->LUTKEY = 0x5AF05AF0UL; + _WDWORD(0x425E0018, 0x5AF05AF0); + //FLEXSPI1->LUTCR = 0x01; + _WDWORD(0x425E001C, 0x01); +} + +FUNC void _FLEXSPI2_ModuleReset(void) +{ + unsigned int reg; + + reg = _RDWORD(0x445E0000); // FlexSPI2->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + reg = _RDWORD(0x445E0000); + _WDWORD(0x445E0000, (reg | 0x1)); + do + { + reg = _RDWORD(0x445E0000); + } while ((reg & 0x1) != 0); + } +} + +FUNC void _FLEXSPI2_WaitBusIdle(void) +{ + unsigned int reg; + + reg = _RDWORD(0x445E0000); // FlexSPI2->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + do + { + reg = _RDWORD(0x445E00E0); + } while ((reg & 0x3) != 0x3); + } +} + +FUNC void _FlexSPI2_SetPinForOctalMode(void) +{ + // Config IOMUX for FlexSPI2 + _WDWORD(0x42A10088, 0x00000013); // FLEXSPI2_B_DATA03 + _WDWORD(0x42A1008C, 0x00000013); // FLEXSPI2_B_DATA02 + _WDWORD(0x42A10090, 0x00000013); // FLEXSPI2_B_DATA01 + _WDWORD(0x42A10094, 0x00000013); // FLEXSPI2_B_DATA00 + _WDWORD(0x42A1009C, 0x00000013); // FLEXSPI2_A_DATA00 + _WDWORD(0x42A100A0, 0x00000013); // FLEXSPI2_A_DATA01 + _WDWORD(0x42A100A4, 0x00000013); // FLEXSPI2_A_DATA02 + _WDWORD(0x42A100A8, 0x00000013); // FLEXSPI2_A_DATA03 + _WDWORD(0x42A100AC, 0x00000013); // FLEXSPI2_A_SS0_B + _WDWORD(0x42A100B0, 0x00000013); // FLEXSPI2_A_DQS + _WDWORD(0x42A100B4, 0x00000013); // FLEXSPI2_A_SCLK + + //The input daisy!! + _WDWORD(0x42A10594, 0x00000001); // FLEXSPI2_B_DATA03 + _WDWORD(0x42A10590, 0x00000001); // FLEXSPI2_B_DATA02 + _WDWORD(0x42A1058C, 0x00000001); // FLEXSPI2_B_DATA01 + _WDWORD(0x42A10588, 0x00000001); // FLEXSPI2_B_DATA00 + _WDWORD(0x42A10578, 0x00000000); // FLEXSPI2_A_DATA00 + _WDWORD(0x42A1057C, 0x00000000); // FLEXSPI2_A_DATA01 + _WDWORD(0x42A10580, 0x00000000); // FLEXSPI2_A_DATA02 + _WDWORD(0x42A10584, 0x00000000); // FLEXSPI2_A_DATA03 + _WDWORD(0x42A10570, 0x00000000); // FLEXSPI2_A_DQS + _WDWORD(0x42A10598, 0x00000000); // FLEXSPI2_A_SCLK + + // PAD ctrl + _WDWORD(0x42A102D0, 0x00000008); // FLEXSPI2_B_DATA03 + _WDWORD(0x42A102D4, 0x00000008); // FLEXSPI2_B_DATA02 + _WDWORD(0x42A102D8, 0x00000008); // FLEXSPI2_B_DATA01 + _WDWORD(0x42A102DC, 0x00000008); // FLEXSPI2_B_DATA00 + _WDWORD(0x42A102E4, 0x00000008); // FLEXSPI2_A_DATA00 + _WDWORD(0x42A102E8, 0x00000008); // FLEXSPI2_A_DATA01 + _WDWORD(0x42A102EC, 0x00000008); // FLEXSPI2_A_DATA02 + _WDWORD(0x42A102F0, 0x00000008); // FLEXSPI2_A_DATA03 + _WDWORD(0x42A102F4, 0x00000008); // FLEXSPI2_A_SS0_B + _WDWORD(0x42A102F8, 0x00000008); // FLEXSPI2_A_DQS + _WDWORD(0x42A102FC, 0x00000008); // FLEXSPI2_A_SCLK +} + +FUNC void _FLEXSPI2_ClockInit(void) +{ + _WDWORD(0x54484350, 0x0); // ROSC400M_CTRL1 + + // Set flexspi2 root clock, use ROSC400, div = 2 = 1+1 + _WDWORD(0x44450B00, 0x101); // CLOCK_ROOT[22].CONTROL, FlexSPI2 +} + +FUNC void _FLEXSPI2_ModuleInit(void) +{ + // Config FlexSPI2 Registers + + unsigned int reg; + reg = _RDWORD(0x445E0000); + _WDWORD(0x445E0000, (reg & 0xFFFFFFFD)); + + _FLEXSPI2_ModuleReset(); + + _WDWORD(0x445E0000, 0xFFFF3032); // MCR0 + _WDWORD(0x445E0004, 0xFFFFFFFF); // MCR1 + _WDWORD(0x445E0008, 0x200001F7); // MCR2 + _WDWORD(0x445E000C, 0x00000078); // AHBCR prefetch enable + _WDWORD(0x445E0020, 0x800F0000); // AHBRXBUF0CR0 + _WDWORD(0x445E0024, 0x800F0000); // AHBRXBUF1CR0 + _WDWORD(0x445E0028, 0x800F0000); // AHBRXBUF2CR0 + _WDWORD(0x445E002C, 0x800F0000); // AHBRXBUF3CR0 + _WDWORD(0x445E0030, 0x800F0000); // AHBRXBUF4CR0 + _WDWORD(0x445E0034, 0x800F0000); // AHBRXBUF5CR0 + _WDWORD(0x445E0038, 0x80000020); // AHBRXBUF6CR0 + _WDWORD(0x445E003C, 0x80000020); // AHBRXBUF7CR0 + _WDWORD(0x445E00B8, 0x00000000); // IPRXFCR + _WDWORD(0x445E00BC, 0x00000000); // IPTXFCR + + _WDWORD(0x445E0060, 0x00000000); // FLASHA1CR0 + _WDWORD(0x445E0064, 0x00000000); // FLASHA2CR0 + _WDWORD(0x445E0068, 0x00000000); // FLASHB1CR0 + _WDWORD(0x445E006C, 0x00000000); // FLASHB2CR0 + + _FLEXSPI2_WaitBusIdle(); + + _WDWORD(0x445E0060, 0x00002000); // FLASHA1CR0 + _WDWORD(0x445E0070, 0x00021C63); // FLASHA1CR1 + _WDWORD(0x445E0080, 0x00000100); // FLASHA1CR2 + + _FLEXSPI2_WaitBusIdle(); + + _WDWORD(0x445E00C0, 0x00000079); // DLLCRA + _WDWORD(0x445E0000, 0xFFFF3030); // MCR0 + + do + { + reg = _RDWORD(0x445E00E8); + } while (0x3 != (reg & 0x3)); + _Sleep_(1); + // __delay(100);//100us + + _WDWORD(0x445E0000, 0xFFFF3032); // MCR0 + _WDWORD(0x445E0094, 0x000000C2); // FLASHCR4 + _WDWORD(0x445E0094, 0x000000C6); // FLASHCR4 + _WDWORD(0x445E0000, 0xFFFF3030); // MCR0 + + _FLEXSPI2_WaitBusIdle(); + + _WDWORD(0x445E0018, 0x5AF05AF0); // LUTKEY + _WDWORD(0x445E001C, 0x00000002); // LUTCR + _WDWORD(0x445E0200, 0x8B1887A0); // LUT[0] + _WDWORD(0x445E0204, 0xB7078F10); // LUT[1] + _WDWORD(0x445E0208, 0x0000A704); // LUT[2] + _WDWORD(0x445E020C, 0x00000000); // LUT[3] + _WDWORD(0x445E0210, 0x8B188720); // LUT[4] + _WDWORD(0x445E0214, 0xB7078F10); // LUT[5] + _WDWORD(0x445E0218, 0x0000A304); // LUT[6] + _WDWORD(0x445E021C, 0x00000000); // LUT[7] + _WDWORD(0x445E0220, 0x8B1887E0); // LUT[8] + _WDWORD(0x445E0224, 0xB7078F10); // LUT[9] + _WDWORD(0x445E0228, 0x0000A704); // LUT[10] + _WDWORD(0x445E022C, 0x00000000); // LUT[11] + _WDWORD(0x445E0230, 0x8B188760); // LUT[12] + _WDWORD(0x445E0234, 0xA3028F10); // LUT[13] + _WDWORD(0x445E0238, 0x00000000); // LUT[14] + _WDWORD(0x445E023C, 0x00000000); // LUT[15] + _WDWORD(0x445E0240, 0x00000000); // LUT[16] + _WDWORD(0x445E0244, 0x00000000); // LUT[17] + _WDWORD(0x445E0248, 0x00000000); // LUT[18] + _WDWORD(0x445E024C, 0x00000000); // LUT[19] + _WDWORD(0x445E0018, 0x5AF05AF0); // LUTKEY + _WDWORD(0x445E001C, 0x00000001); // LUTCR + + /* Restore hyperram CR0 register */ + _WDWORD(0x445E00A0, 0x00001000); // IPCR0 + _WDWORD(0x445E00A4, 0x00030002); // IPCR1 + _WDWORD(0x445E00BC, 0x00000001); // IPTXFCR + _WDWORD(0x445E0180, 0x2F8F2F8F); // TFDR 0x8F2F is default value of W756/7x of CR0 + _WDWORD(0x445E0014, 0x00000040); // INTR + _WDWORD(0x445E00B0, 0x00000001); // IPCMD + do + { + reg = _RDWORD(0x445E0014); // INTR + } while ((reg & 0x1) == 0x0); + _WDWORD(0x445E0014, 0x00000001); // INTR + + /* Restore hyperram CR1 register */ + _WDWORD(0x445E00A0, 0x00001002); // IPCR0 + _WDWORD(0x445E00A4, 0x00030002); // IPCR1 + _WDWORD(0x445E00BC, 0x00000001); // IPTXFCR + _WDWORD(0x445E0180, 0xC1FFC1FF); // TFDR 0xFFC1 is default value of W756/7x of CR1 + _WDWORD(0x445E0014, 0x00000040); // INTR + _WDWORD(0x445E00B0, 0x00000001); // IPCMD + do + { + reg = _RDWORD(0x445E0014); // INTR + } while ((reg & 0x1) == 0x0); + _WDWORD(0x445E0014, 0x00000001); // INTR + + _FLEXSPI2_ModuleReset(); +} + +FUNC void Flash_Init(void) +{ + printf("***************************************************\r\n"); + printf("Init Flash\r\n"); + + _FLEXSPI1_WaitBusIdle(); + _FLEXSPI1_ModuleReset(); + + _FLEXSPI1_SetPinForQuadMode(); + _FLEXSPI1_ClockInit(); + _FLEXSPI1_ModuleInit(); + + printf("***************************************************\r\n"); +} + +FUNC void HyperRAM_Init(void) +{ + printf("***************************************************\r\n"); + printf("Init HyperRAM\r\n"); + + _FLEXSPI2_WaitBusIdle(); + _FLEXSPI2_ModuleReset(); + + _FlexSPI2_SetPinForOctalMode(); + _FLEXSPI2_ClockInit(); + _FLEXSPI2_ModuleInit(); + + printf("***************************************************\r\n"); +} + +FUNC void ClearNVIC(void) { + printf("***************************************************\r\n"); + printf("Clear NVIC\r\n"); + printf("***************************************************\r\n"); + memset(0xE000E180, 0x40, 0xFF); + memset(0xE000E280, 0x40, 0xFF); +} + +FUNC void Setup_PC_SP(void) +{ + SP = _RDWORD(0x2800B000); // Setup Stack Pointer + PC = _RDWORD(0x2800B004); // Setup Program Counter + _WDWORD(0xE000ED08, 0x2800B000); // Setup Vector Table Offset Register +} + +FUNC void Setup (void) { + ClearNVIC(); + Flash_Init(); + HyperRAM_Init(); + Setup_PC_SP(); +} + +FUNC void OnResetExec (void) +{ + // executes upon RESET + Setup(); +} + +// Disable the software breakpoint for nor flash memory region +SBC 0x28000000, 0x28FFFFFF, 0 + +Setup(); diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/link.icf b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/link.icf new file mode 100644 index 00000000000..9dc0fc389dc --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/link.icf @@ -0,0 +1,183 @@ +/* +** ################################################################### +** Processors: MIMXRT1189CVM8B_cm33 +** MIMXRT1189CVM8C_cm33 +** MIMXRT1189XVM8B_cm33 +** MIMXRT1189XVM8C_cm33 +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: IMXRT1180RM, Rev 5, 01/2024 +** Version: rev. 2.0, 2024-01-18 +** Build: b250310 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Board memory map */ + +define symbol m_code_tcm_start = 0x0FFE0000; +define symbol m_code_tcm_size = 0x00020000; + +define symbol m_system_tcm_start = 0x20000000; +define symbol m_system_tcm_size = 0x00020000; + +define symbol m_ocram1_start = 0x20484000; /* OCRAM1 first 16K access is blocked by TRDC */ +define symbol m_ocram1_size = 0x0007C000; + +define symbol m_ocram2_start = 0x20500000; +define symbol m_ocram2_size = 0x00040000; + +/* CM33 use last 2M bytes space of sdram and hyperram for dual image framework */ +define symbol m_sdram_start = isdefinedsymbol(__dual_image__) ? 0x81E00000 : 0x80000000; +define symbol m_sdram_size = isdefinedsymbol(__dual_image__) ? 0x00200000 : 0x02000000; +define symbol m_hyperram_start = isdefinedsymbol(__dual_image__) ? 0x04600000 : 0x04000000; +define symbol m_hyperram_size = isdefinedsymbol(__dual_image__) ? 0x00200000 : 0x00800000; +define symbol m_flash_start = 0x28000000; +define symbol m_flash_size = 0x00800000; + +define symbol m_core1_image_maximum_size = 0x00040000; + +/* General definition */ +define symbol m_fcb_offset = 0x400; +define symbol m_fcb_size = 0x200; +define symbol m_fcb_start = m_flash_start + m_fcb_offset; +define symbol m_fcb_end = m_fcb_start + m_fcb_size - 1; + +define symbol m_xmcd_offset = 0x800; +define symbol m_xmcd_size = 0x400; +define symbol m_xmcd_start = m_flash_start + m_xmcd_offset; +define symbol m_xmcd_end = m_xmcd_start + m_xmcd_size - 1; + +define symbol m_container_offset = 0x1000; +define symbol m_container_size = 0x2000; +define symbol m_container_start = m_flash_start + m_container_offset; +define symbol m_container_end = m_container_start + m_container_size - 1; + +define symbol app_image_offset = 0x0000B000; +define symbol vector_table_size = 0x00000400; +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x01000; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x04000; +} + +define symbol m_qacode_start = m_code_tcm_start + (isdefinedsymbol(__ram_vector_table__) ? vector_table_size : 0); +define symbol m_qacode_end = m_code_tcm_start + m_code_tcm_size - 1; +define symbol m_qadata_start = m_system_tcm_start; +define symbol m_qadata_end = m_system_tcm_start + m_system_tcm_size - 1; +define symbol m_ram_vector_table_start = m_code_tcm_start; + +/* Target specific definition, code & data allocation */ +define symbol m_code_size = m_flash_size - app_image_offset; +define symbol m_data_size = m_system_tcm_size; +define symbol m_ncache_size = isdefinedsymbol(__multicore__) ? 0x20000 : 0x40000; /* m_ncache_size must be 2^N */ +define symbol m_shmem_size = m_ocram2_size; /* m_shmem_size must be 2^N */ + +define symbol m_ocram1_size_for_cm7 = isdefinedsymbol(__multicore__) ? 0x40000 : 0; + +define symbol m_ram_vector_table_size = isdefinedsymbol(__ram_vector_table__) ? vector_table_size : 0; + +define symbol m_text_start = m_flash_start + app_image_offset; +define symbol m_text_end = m_text_start + m_code_size - 1; +define symbol m_interrupts_start = m_text_start; + +define symbol m_data_start = m_system_tcm_start; +define symbol m_data_end = m_data_start + m_data_size - 1; + +define symbol m_ncache_start = m_ocram1_start + m_ocram1_size - m_ocram1_size_for_cm7 - m_ncache_size; +define symbol m_ncache_end = m_ncache_start + m_ncache_size - 1; + +define symbol m_heap_start = m_ocram1_start; +define symbol m_heap_end = m_ncache_start - 1; + +if (isdefinedsymbol(__use_shmem__)) { + define symbol m_rpmsg_sh_mem_start = m_ocram2_start; + define symbol m_rpmsg_sh_mem_end = m_rpmsg_sh_mem_start + m_shmem_size - 1; +} + +/* Region definition */ +define memory mem with size = 4G; +define region FCB_region = mem:[from m_fcb_start to m_fcb_end]; +define region XMCD_region = mem:[from m_xmcd_start to m_xmcd_end]; +define region CONTAINER_region = mem:[from m_container_start to m_container_end]; +define region TEXT_region = mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; +define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; +define region HEAP_region = mem:[from m_heap_start to m_heap_end]; +define region QACODE_region = mem:[from m_qacode_start to m_qacode_end]; +define region QADATA_region = mem:[from m_qadata_start to m_qadata_end]; +if (isdefinedsymbol(__use_shmem__)) { + define region rpmsg_sh_mem_region = mem:[from m_rpmsg_sh_mem_start to m_rpmsg_sh_mem_end]; +} + +/* Exported symbol definition */ +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = m_ram_vector_table_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = m_ram_vector_table_size; +define exported symbol __NCACHE_REGION_START = m_ncache_start; +define exported symbol __NCACHE_REGION_SIZE = m_ncache_end - m_ncache_start + 1; +define exported symbol __CONTAINER_IMG_OFFSET = start(TEXT_region) - start(CONTAINER_region); +define exported symbol __CONTAINER_IMG_LOAD_ADDR = start(TEXT_region); +define exported symbol __CONTAINER_IMG_ENTRY_ADDR = start(TEXT_region); +if (isdefinedsymbol(__use_shmem__)) { + define exported symbol rpmsg_sh_mem_start = m_rpmsg_sh_mem_start; + define exported symbol rpmsg_sh_mem_end = m_rpmsg_sh_mem_end; + define exported symbol __RPMSG_SH_MEM_START = m_rpmsg_sh_mem_start; + define exported symbol __RPMSG_SH_MEM_SIZE = m_rpmsg_sh_mem_end - m_rpmsg_sh_mem_start + 1; +} + +/* Block definition */ +define block RW { readwrite }; +define block ZI { zi }; +define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; +define block QACCESS_CODE { section CodeQuickAccess }; +define block QACCESS_DATA { section DataQuickAccess }; +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block CORE1_IMAGE_BLOCK with alignment = 16, maximum size = m_core1_image_maximum_size { section __core1_image }; + +define block RO with fixed order { readonly section .intvec, readonly, block CORE1_IMAGE_BLOCK }; + +initialize by copy { readwrite, section .textrw, section DataQuickAccess, section CodeQuickAccess }; +do not initialize { section .noinit }; +if (isdefinedsymbol(__use_shmem__)) { + do not initialize { section rpmsg_sh_mem_section }; +} + +keep{ section .boot_hdr.conf, section .boot_hdr.xmcd_data, section .boot_hdr.container }; + +place in FCB_region { section .boot_hdr.conf }; +place in XMCD_region { section .boot_hdr.xmcd_data }; +place in CONTAINER_region { section .boot_hdr.container }; +place in TEXT_region { first block RO }; +place in QACODE_region { section .textrw, block QACCESS_CODE }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { block QACCESS_DATA }; +place in NCACHE_region { block NCACHE_VAR }; +place in CSTACK_region { block CSTACK }; +if (isdefinedsymbol(__heap_noncacheable__)) { + place in NCACHE_region { last block HEAP }; +} else { + place in HEAP_region { last block HEAP }; +} +if (isdefinedsymbol(__use_shmem__)) { + place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/link.lds b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/link.lds new file mode 100644 index 00000000000..890bc3f5764 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/link.lds @@ -0,0 +1,376 @@ +/* +** ################################################################### +** Processors: MIMXRT1189CVM8B_cm33 +** MIMXRT1189XVM8B_cm33 +** +** Compiler: GNU C Compiler +** Reference manual: IMXRT1180RM, Rev 2, 12/2022 +** Version: rev. 0.1, 2021-03-09 +** Build: b240109 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2024 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Board memory map */ +m_code_tcm_start = 0x0FFE0000; +m_code_tcm_size = 0x00020000; +m_system_tcm_start = 0x20000000; +m_system_tcm_size = 0x00020000; +m_ocram1_start = 0x20484000; /* OCRAM1 first 16K access is blocked by TRDC */ +m_ocram1_size = 0x0007C000; +m_ocram2_start = 0x20500000; +m_ocram2_size = 0x00040000; + +/* CM33 use last 2M bytes space of sdram and hyperram for dual image framework */ +m_sdram_start = DEFINED(__dual_image__) ? 0x81E00000 : 0x80000000; +m_sdram_size = DEFINED(__dual_image__) ? 0x00200000 : 0x02000000; +m_hyperram_start = DEFINED(__dual_image__) ? 0x04600000 : 0x04000000; +m_hyperram_size = DEFINED(__dual_image__) ? 0x00200000 : 0x00800000; +m_flash_start = 0x28000000; +m_flash_size = 0x01000000; + +m_core1_image_maximum_size = 0x00040000; + +/* General definition */ +m_fcb_offset = 0x400; +m_fcb_size = 0x200; +m_xmcd_offset = 0x800; +m_xmcd_size = 0x400; +m_container_offset = 0x1000; +m_container_size = 0x2000; + +m_fcb_start = m_flash_start + m_fcb_offset; +m_fcb_end = m_fcb_start + m_fcb_size - 1; +m_xmcd_start = m_flash_start + m_xmcd_offset; +m_xmcd_end = m_xmcd_start + m_xmcd_size - 1; +m_container_start = m_flash_start + m_container_offset; +m_container_end = m_container_start + m_container_size - 1; + +app_image_offset = DEFINED(__dual_image__) ? 0x0010B000 : 0x0000B000; +vector_table_size = 0x00000400; +m_qacode_start = m_code_tcm_start + (DEFINED(__ram_vector_table__) ? vector_table_size : 0); +m_qacode_end = m_code_tcm_start + m_code_tcm_size - 1; +m_qadata_start = m_system_tcm_start; +m_qadata_end = m_system_tcm_start + m_system_tcm_size - 1; +m_ram_vector_table_start = m_code_tcm_start; +m_stack_size = DEFINED(__stack_size__) ? __stack_size__ : 0x1000; +m_heap_size = DEFINED(__heap_size__) ? __heap_size__ : 0x4000; + +/* Target specific definition, code & data allocation */ +m_code_size = m_flash_size - app_image_offset - vector_table_size; +m_data_size = m_system_tcm_size; +m_ncache_size = DEFINED(__multicore__) ? 0x20000 : 0x40000; /* m_ncache_size must be 2^N */ +m_shmem_size = m_ocram2_size; /* m_shmem_size must be 2^N */ + +m_ocram1_size_for_cm7 = DEFINED(__multicore__) ? 0x40000 : 0; + +m_ram_vector_table_size = DEFINED(__ram_vector_table__) ? vector_table_size : 0; + +m_interrupts_start = m_flash_start + app_image_offset; +m_interrupts_end = m_interrupts_start + vector_table_size - 1; + +m_text_start = m_interrupts_end + 1; +m_text_end = m_text_start + m_code_size - 1; + +m_data_start = m_system_tcm_start; +m_data_end = m_data_start + m_data_size - 1; + +m_ncache_start = m_ocram1_start + m_ocram1_size - m_ocram1_size_for_cm7 - m_ncache_size; +m_ncache_end = m_ncache_start + m_ncache_size - 1 - (DEFINED(__heap_noncacheable__) ? m_heap_size : 0); + +m_heap_start = DEFINED(__heap_noncacheable__) ? m_ncache_end + 1 : m_ocram1_start; +m_heap_end = m_heap_start + m_heap_size - 1; + +m_rpmsg_sh_mem_start = m_ocram2_start; +m_rpmsg_sh_mem_end = m_rpmsg_sh_mem_start + m_shmem_size - 1; + +/* Exported symbol definition */ +__VECTOR_TABLE = m_interrupts_start; +__VECTOR_RAM = m_ram_vector_table_start; +__RAM_VECTOR_TABLE_SIZE_BYTES = m_ram_vector_table_size; +__CONTAINER_IMG_OFFSET = m_interrupts_start - m_container_start; + +__NCACHE_REGION_START = m_ncache_start; +__NCACHE_REGION_SIZE = m_ncache_size; +__RPMSG_SH_MEM_START = DEFINED(__use_shmem__)? m_rpmsg_sh_mem_start : 0; +__RPMSG_SH_MEM_SIZE = DEFINED(__use_shmem__)? m_rpmsg_sh_mem_end - m_rpmsg_sh_mem_start + 1 : 0; + +/* Specify the memory areas */ +MEMORY +{ + m_fcb_data (RX) : ORIGIN = m_fcb_start, LENGTH = m_fcb_end - m_fcb_start + 1 + m_xmcd_data (RX) : ORIGIN = m_xmcd_start, LENGTH = m_xmcd_end - m_xmcd_start + 1 + m_container_data (RX) : ORIGIN = m_container_start, LENGTH = m_container_end - m_container_start + 1 + m_interrupts_ram (RX) : ORIGIN = m_ram_vector_table_start, LENGTH = __RAM_VECTOR_TABLE_SIZE_BYTES + m_interrupts (RX) : ORIGIN = m_interrupts_start, LENGTH = m_interrupts_end - m_interrupts_start + 1 + m_text (RX) : ORIGIN = m_text_start, LENGTH = m_text_end - m_text_start + 1 + m_data (RW) : ORIGIN = m_data_start, LENGTH = m_data_end - m_data_start + 1 + m_ncache (RW) : ORIGIN = m_ncache_start, LENGTH = m_ncache_end - m_ncache_start + 1 + m_heap (RW) : ORIGIN = m_heap_start, LENGTH = m_heap_end - m_heap_start + 1 + m_qacode (RX) : ORIGIN = m_qacode_start, LENGTH = m_qacode_end - m_qacode_start + 1 + m_qadata (RW) : ORIGIN = m_qadata_start, LENGTH = m_qadata_end - m_qadata_start + 1 + m_rpmsg (RW) : ORIGIN = m_rpmsg_sh_mem_start, LENGTH = m_rpmsg_sh_mem_end - m_rpmsg_sh_mem_start + 1 +} + +/* Define output sections */ +SECTIONS +{ + .fcb : + { + KEEP(*(.boot_hdr.conf)) + } > m_fcb_data + + .xmcd : + { + KEEP(*(.boot_hdr.xmcd_data)) + } > m_xmcd_data + + .container : + { + KEEP(*(.boot_hdr.container)) + } > m_container_data + + /* The startup code goes first */ + .interrupts : + { + . = ALIGN(4); + __Vectors = .; + KEEP(*(.isr_vector)) /* Vector table and startup code */ + . = ALIGN(4); + } > m_interrupts + + .interrupts_ram : + { + . = ALIGN(4); + . += __RAM_VECTOR_TABLE_SIZE_BYTES; + . = ALIGN(4); + } > m_interrupts_ram + + /* The program code */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + . = ALIGN(16); + core1_image_start = .; + KEEP (*(.core1_code)) + *(.core1_code*) + core1_image_end = .; + . = ALIGN(4) ; + } > m_text + + ASSERT((core1_image_end - core1_image_start) <= m_core1_image_maximum_size, "Core1 image size exceeds the limit") + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + + __data_flash_start = .; /* Symbol is used by startup for data initialization */ + .data : AT(__data_flash_start) + { + . = ALIGN(4); + __data_start__ = .; /* create a global symbol at data start */ + *(m_usb_dma_init_data) + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(DataQuickAccess) /* quick access data section */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __ram_function_flash_start = __data_flash_start + (__data_end__ - __data_start__); /* Symbol is used by startup for TCM code initialization */ + .ram_function : AT(__ram_function_flash_start) + { + . = ALIGN(32); + __ram_function_start__ = .; + *(CodeQuickAccess) + . = ALIGN(128); + __ram_function_end__ = .; + } > m_qacode + + __noncache_data_flash_start = __ram_function_flash_start + (__ram_function_end__ - __ram_function_start__); + .ncache.init : AT(__noncache_data_flash_start) + { + . = ALIGN(4); + __noncache_data_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncache_data_end__ = .; /* create a global symbol at ncache data end */ + } > m_ncache + + .ncache : + { + . = ALIGN(4); + __noncache_bss_start__ = .; /* define a global symbol at ncache bss start */ + *(NonCacheable) + . = ALIGN(4); + __noncache_bss_end__ = .; /* define a global symbol at ncache bss end */ + } > m_ncache + + __qadata_flash_start = __noncache_data_flash_start + (__noncache_data_end__ - __noncache_data_start__); + .qadata : AT(__qadata_flash_start) + { + . = ALIGN(4); + __qadata_start__ = .; + . = ALIGN(4); + __qadata_end__ = .; + } > m_qadata + + text_data_end = __qadata_flash_start + (__qadata_end__ - __qadata_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(text_data_end < text_end, "region m_text overflowed with text and data") + + __CONTAINER_IMG_SIZE = text_data_end - m_interrupts_start; + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __bss_start__ = .; + *(m_usb_dma_noninit_data) + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > m_data + + .rpmsg : + { + *(.noinit.$rpmsg_sh_mem) + } > m_rpmsg + + .heap : + { + . = ALIGN(8); + __HeapBase = .; + end = .; + . += m_heap_size; + __HeapLimit = .; /* Add for _sbrk */ + } > m_heap + + .stack : + { + . = ALIGN(8); + __StackStart = .; + . += m_stack_size; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - m_stack_size; + PROVIDE(__stack = __StackTop); + PROVIDE (__stack_size = m_stack_size); + ASSERT(__StackLimit >= __StackStart, "region m_data overflowed with stack and heap") + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/link.scf b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/link.scf new file mode 100644 index 00000000000..9ee6de8571d --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/link.scf @@ -0,0 +1,232 @@ +#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m33 -E -x c +/* +** ################################################################### +** Processors: MIMXRT1189CVM8B_cm33 +** MIMXRT1189CVM8C_cm33 +** MIMXRT1189XVM8B_cm33 +** MIMXRT1189XVM8C_cm33 +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: IMXRT1180RM, Rev 5, 01/2024 +** Version: rev. 2.0, 2024-01-18 +** Build: b250310 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* Board memory map */ + +#define m_code_tcm_start 0x0FFE0000 +#define m_code_tcm_size 0x00020000 + +#define m_system_tcm_start 0x20000000 +#define m_system_tcm_size 0x00020000 + +#define m_ocram1_start 0x20484000 /* OCRAM1 first 16K access is blocked by TRDC */ +#define m_ocram1_size 0x0007C000 + +#define m_ocram2_start 0x20500000 +#define m_ocram2_size 0x00040000 + +#if defined(__dual_image__) +/* CM33 use last 2M bytes space of sdram and hyperram for dual image framework */ +#define m_sdram_start 0x81E00000 +#define m_sdram_size 0x00200000 +#define m_hyperram_start 0x04600000 +#define m_hyperram_size 0x00200000 +#else +#define m_sdram_start 0x80000000 +#define m_sdram_size 0x02000000 +#define m_hyperram_start 0x04000000 +#define m_hyperram_size 0x00800000 +#endif + +#define m_flash_start 0x28000000 +#define m_flash_size 0x00800000 +#define m_core1_image_maximum_size 0x00040000 + +/* General definition */ +#define app_image_offset 0x0000B000 + +#define m_fcb_offset 0x400 +#define m_fcb_size 0x200 +#define m_xmcd_offset 0x800 +#define m_xmcd_size 0x400 +#define m_container_offset 0x1000 +#define m_container_size 0x2000 + +#define vector_table_size 0x400 +#define m_ram_vector_table_start m_code_tcm_start + +#if defined(__stack_size__) + #define stack_size __stack_size__ +#else + #define stack_size 0x01000 +#endif + +#if defined(__heap_size__) + #define heap_size __heap_size__ +#else + #define heap_size 0x04000 +#endif + +/* Target specific definition, code & data allocation */ +#if defined(__ram_vector_table__) +#define m_ram_vector_table_size vector_table_size +#else +#define m_ram_vector_table_size 0 +#endif + +#define m_qacode_start m_code_tcm_start + m_ram_vector_table_size +#define m_qadata_start m_system_tcm_start +#define m_qacode_size m_code_tcm_size - (m_qacode_start - m_code_tcm_start) +#define m_qadata_size 0 + +#define m_text_size m_flash_size - app_image_offset +#define m_data_size m_system_tcm_size +#if defined(__multicore__) +#define m_ncache_size 0x20000 /* m_ncache_size must be 2^N */ +#define m_ocram1_size_for_cm7 0x40000 +#else +#define m_ncache_size 0x40000 /* m_ncache_size must be 2^N */ +#define m_ocram1_size_for_cm7 0 +#endif +#define m_shmem_size m_ocram2_size /* m_shmem_size must be 2^N */ + +#define m_fcb_start m_flash_start + m_fcb_offset +#define m_xmcd_start m_flash_start + m_xmcd_offset +#define m_container_start m_flash_start + m_container_offset +#define m_text_start m_flash_start + app_image_offset +#define m_interrupts_start m_text_start +#define m_data_start m_system_tcm_start +#define m_ncache_start m_ocram1_start + m_ocram1_size - m_ocram1_size_for_cm7 - m_ncache_size +#define m_heap_start m_ocram1_start + +#if defined(__use_shmem__) +#define m_shmem_start m_ocram2_start +#endif + +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +; load region +LR_m_header m_fcb_start (m_container_start) + (m_container_size) - (m_fcb_start) +{ + ; Flash Configuration Block + FCB m_fcb_start FIXED m_fcb_size + { + .ANY (.boot_hdr.conf) + } + + ; XMCD Block + XMCD m_xmcd_start FIXED m_xmcd_size + { + .ANY (.boot_hdr.xmcd_data) + } + + ; Container + Container m_container_start FIXED m_container_size + { + .ANY (.boot_hdr.container) + } + + ; Empty region added for container configuration + ER_m_container_image_offset (m_text_start) - (m_container_start) EMPTY 0 + { + } +} +#endif + +; load region +LR_m_text m_text_start m_text_size +{ + ; load address = execution address + VECTOR_ROM m_interrupts_start FIXED vector_table_size + { + * (.isr_vector,+FIRST) + } + + VECTOR_RAM m_ram_vector_table_start EMPTY m_ram_vector_table_size + { + } + + ; load address = execution address + ER_m_text m_text_start + vector_table_size FIXED m_text_size - vector_table_size + { + * (InRoot$$Sections) + .ANY (+RO) + } + + CORE1_REGION +0 ALIGN 16 m_core1_image_maximum_size + { + .ANY (.core1_code) + } + + ER_m_QuickAccessCode m_qacode_start m_qacode_size + { + .ANY (CodeQuickAccess) + } + + ER_m_QuickAccessData m_qadata_start EMPTY m_qadata_size + { + } + + RW_m_data m_data_start m_data_size-stack_size + { + .ANY (+RW +ZI) + .ANY (DataQuickAccess) + } + + ; ncache data + RW_m_ncache m_ncache_start m_ncache_size + { + .ANY (NonCacheable.init) + .ANY (.bss.NonCacheable) + } + +#if defined(__heap_noncacheable__) + ; Heap region growing up + ARM_LIB_HEAP +0 ALIGN 0x100 EMPTY heap_size + { + } +#endif + + ; Empty region added for MPU configuration + RW_m_ncache_aux m_ncache_start + m_ncache_size EMPTY 0 + { + } + +#if defined(__use_shmem__) + ; shared memory data + RPMSG_SH_MEM m_shmem_start m_shmem_size + { + .ANY (rpmsg_sh_mem_section) + } + + ; Empty region added for MPU configuration + RPMSG_SH_MEM_aux m_shmem_start + m_shmem_size EMPTY 0 + { + } +#endif + +#if !defined(__heap_noncacheable__) + ; Heap region growing up + ARM_LIB_HEAP m_heap_start EMPTY heap_size + { + } +#endif + + ; Stack region growing down + ARM_LIB_STACK m_data_start+m_data_size EMPTY -stack_size + { + } +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/evkmimxrt1180_cm33.jlinkscript b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/evkmimxrt1180_cm33.jlinkscript new file mode 100644 index 00000000000..23137a7f748 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/evkmimxrt1180_cm33.jlinkscript @@ -0,0 +1,1041 @@ +__constant U32 _INDEX_AHB_AP_CORTEX_M33 = 3; +__constant U32 _AHB_ACC_32BIT_AUTO_INC = (1 << 29) | (1 << 25) | (1 << 24) | (1 << 4) | (2 << 0); +__constant U32 _AHB_ACC_16BIT_AUTO_INC = (1 << 29) | (1 << 25) | (1 << 24) | (1 << 4) | (1 << 0); // HMASTER = DEBUG, Private access, no Auto-increment, Access size: half word; +__constant U32 _ACCESS_AP = 1; +__constant U32 _CM33_CPUID = 0xD210; +__constant U32 _CM7_CPUID = 0x0C27; + +/* ROM trap address for CM33 core, after system reset */ +__constant U32 _ROM_TRAP0_ADDR = 0x10002932; +__constant U32 _ROM_TRAP1_ADDR = 0x100025D4; +__constant U32 _ROM_TRAP2_ADDR = 0x100025D4; + +__constant U32 _SRC_SRSR_ADDR = 0x44460050; +__constant U32 _SRC_SRMASK_ADDR = 0x44460018; +__constant U32 _SRC_SCR_ADDR = 0x44460010; +__constant U32 _SRC_AUTHEN_CTRL_ADDR = 0x44460004; +__constant U32 _SRC_SBMR2_ADDR = 0x44460044; +__constant U32 _BLK_M7_CFG_ADDR = 0x444F0080; + +__constant U32 _DWT_COMP0_ADDR = 0xE0001020; +__constant U32 _DWT_FUNC0_ADDR = 0xE0001028; + +__constant U32 _DCB_DHCSR_ADDR = 0xE000EDF0; +__constant U32 _DCB_DEMCR_ADDR = 0xE000EDFC; + +__constant U32 _SCB_AIRCR_ADDR = 0xE000ED0C; + +__constant U32 _XCACHE_PC_CCR_ADDR = 0x44400000; +__constant U32 _XCACHE_PS_CCR_ADDR = 0x44400800; + +__constant U32 _CM33_MPU_CTRL_ADDR = 0xE000ED94; + +__constant U32 _SI_VER_ADDR = 0x5751804C; + +unsigned int cpuID; +unsigned int rom_trap_addr; + +static int _WriteViaCM33AP16(U32 Addr, U16 Data) { + int r; + + JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 4) | (_INDEX_AHB_AP_CORTEX_M33 << 24)); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL, _AHB_ACC_16BIT_AUTO_INC); + Data = (Data & 0xFFFF) | ((Data & 0xFFFF) << 16); + r = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, Addr); + r |= JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, Data); + return r; +} + +static U32 _ReadViaCM33AP16(U32 Addr) { + U32 r; + + JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 4) | (_INDEX_AHB_AP_CORTEX_M33 << 24)); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL, _AHB_ACC_16BIT_AUTO_INC); + JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, Addr); + JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, &r); + return r; +} + +static int _WriteViaCM33AP32(U32 Addr, U32 Data) { + int r; + + JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 4) | (_INDEX_AHB_AP_CORTEX_M33 << 24)); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL, _AHB_ACC_32BIT_AUTO_INC); + r = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, Addr); + r |= JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, Data); + return r; +} + +static U32 _ReadViaCM33AP32(U32 Addr) { + int r; + + JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 4) | (_INDEX_AHB_AP_CORTEX_M33 << 24)); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL, _AHB_ACC_32BIT_AUTO_INC); + r = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, Addr); + r |= JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, &r); + return r; +} + +/* For Debug Start */ +__constant U32 _DCB_DCRSR_ADDR = 0xE000EDF4; +__constant U32 _DCB_DCRDR_ADDR = 0xE000EDF8; +__constant U32 _SCB_DFSR_ADDR = 0xE000ED30; + +__constant U32 _REG_R0 = 0x0; +__constant U32 _REG_R1 = 0x1; +__constant U32 _REG_R2 = 0x2; +__constant U32 _REG_R3 = 0x3; +__constant U32 _REG_R4 = 0x4; +__constant U32 _REG_R5 = 0x5; +__constant U32 _REG_R6 = 0x6; +__constant U32 _REG_R7 = 0x7; +__constant U32 _REG_R8 = 0x8; +__constant U32 _REG_R9 = 0x9; +__constant U32 _REG_R10 = 0xA; +__constant U32 _REG_R11 = 0xB; +__constant U32 _REG_R12 = 0xC; +__constant U32 _REG_SP = 0xD; +__constant U32 _REG_LR = 0xE; +__constant U32 _REG_PC = 0xF; +__constant U32 _REG_SP_main = 0x11; +__constant U32 _REG_SP_process = 0x12; +__constant U32 _REG_MSPLIM_S = 0x1C; +__constant U32 _REG_PSPLIM_S = 0x1D; +__constant U32 _REG_MSPLIM_NS = 0x1E; +__constant U32 _REG_PSPLIM_NS = 0x1F; + +static U32 _ReadCPUReg(int RegIndex) { + U32 v; + + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_ADDR, _DCB_DCRSR_ADDR); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_DATA, RegIndex); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_ADDR, _DCB_DCRDR_ADDR); + v = JLINK_CORESIGHT_ReadAP(JLINK_CORESIGHT_AP_REG_DATA); + return v; +} + +static U32 _ReadCPURegViaAP(int AP, int RegIndex) { + int r; + + JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 4) | (AP << 24)); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL, _AHB_ACC_32BIT_AUTO_INC); + + r = _ReadCPUReg(RegIndex); + return r; +} + +int debug = 0; + +void ShowDAPInfo(void) +{ + int r; + + if ( debug ) + { + JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 4) | (_INDEX_AHB_AP_CORTEX_M33 << 24)); + r = JLINK_CORESIGHT_ReadAP(JLINK_CORESIGHT_AP_REG_CTRL); + JLINK_SYS_Report1("CM33 AP CSW = ", r); + } +} + +void DBG_ShowCM33Reg(void) +{ + int r, sp, pc; + + r = _ReadViaCM33AP32(_CM33_MPU_CTRL_ADDR); + JLINK_SYS_Report1(" CM33 MPU_CTRL = ", r); + r = _ReadViaCM33AP32(_XCACHE_PC_CCR_ADDR); + JLINK_SYS_Report1(" XCACHE_PC_CCR = ", r); + r = _ReadViaCM33AP32(_XCACHE_PS_CCR_ADDR); + JLINK_SYS_Report1(" XCACHE_PS_CCR = ", r); + + r = _ReadViaCM33AP32(_DWT_COMP0_ADDR); + JLINK_SYS_Report1(" CM33 DWT_COMP0 = ", r); + r = _ReadViaCM33AP32(_DWT_FUNC0_ADDR); + JLINK_SYS_Report1(" CM33 DWT_FUNC0 = ", r); + + r = _ReadViaCM33AP32(_SCB_DFSR_ADDR); + JLINK_SYS_Report1(" CM33 DFSR = ", r); + r = _ReadViaCM33AP32(_DCB_DEMCR_ADDR); + JLINK_SYS_Report1(" CM33 DEMCR = ", r); + r = _ReadViaCM33AP32(_DCB_DHCSR_ADDR); + JLINK_SYS_Report1(" CM33 DHCSR = ", r); + if ( (r & 0x02) != 0) + { + sp = _ReadCPURegViaAP(_INDEX_AHB_AP_CORTEX_M33, _REG_SP); + pc = _ReadCPURegViaAP(_INDEX_AHB_AP_CORTEX_M33, _REG_PC); + JLINK_SYS_Report1(" CM33 PC = ", pc); + JLINK_SYS_Report1(" CM33 SP = ", sp); + } + else + { + JLINK_SYS_Report(" CM33 core is not halted!"); + } +} + +void DBG_ShowCoreReg(void) +{ + int r, sp, pc; + + r = JLINK_MEM_ReadU32(_SCB_DFSR_ADDR); + JLINK_SYS_Report1(" DFSR = ", r); + r = JLINK_MEM_ReadU32(_DCB_DHCSR_ADDR); + JLINK_SYS_Report1(" DHCSR = ", r); + if ( (r & 0x02) != 0) + { + sp = _ReadCPUReg(_REG_SP); + pc = _ReadCPUReg(_REG_PC); + JLINK_SYS_Report1(" PC = ", pc); + JLINK_SYS_Report1(" SP = ", sp); + } + else + { + JLINK_SYS_Report(" Core is not halted!"); + } +} + +void DBG_ShowReg(int seq) +{ + int r; + if( debug ) + { + JLINK_SYS_Report1("Seq: ", seq); + + r = _ReadViaCM33AP32(_SRC_AUTHEN_CTRL_ADDR); + JLINK_SYS_Report1(" AUTHEN_CTRL = ", r); + r = _ReadViaCM33AP32(_SRC_SRSR_ADDR); + JLINK_SYS_Report1(" SRSR = ", r); + r = _ReadViaCM33AP32(_SRC_SRMASK_ADDR); + JLINK_SYS_Report1(" SRMASK = ", r); + r = _ReadViaCM33AP32(_SRC_SCR_ADDR); + JLINK_SYS_Report1(" SCR = ", r); + r = _ReadViaCM33AP32(_BLK_M7_CFG_ADDR); + JLINK_SYS_Report1(" M7_CFG = ", r); + + if(cpuID == _CM7_CPUID) + { + if((r & 0x10) == 0) + { + DBG_ShowCoreReg(); + } + + } + + DBG_ShowCM33Reg(); + } +} +/* For Debug End */ + +void _FLEXSPI1_ModuleReset() +{ + unsigned int reg; + + reg = MEM_ReadU32(0x425E0000); // FlexSPI1->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + reg = MEM_ReadU32(0x425E0000); + MEM_WriteU32(0x425E0000, (reg | 0x1)); + do + { + reg = MEM_ReadU32(0x425E0000); + } while ((reg & 0x1) != 0); + } +} + +void _FLEXSPI1_WaitBusIdle() +{ + unsigned int reg; + reg = MEM_ReadU32(0x425E0000); // FlexSPI1->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + do + { + reg = MEM_ReadU32(0x425E00E0); + } while ((reg & 0x3) != 0x3); + } +} + +void _FLEXSPI1_ClockInit() +{ + _WriteViaCM33AP32(0x54484350, 0x0); // ROSC400M_CTRL1 + + // Set flexspi1 root clock, use ROSC400, div = 4 = 1+3 + MEM_WriteU32(0x54450A80, 0x103); // CLOCK_ROOT[21].CONTROL, FlexSPI1 +} + +void _FLEXSPI1_SetPinForQuadMode(void) { + // Set 4 Pin Mode for JLink + // IOMUXC_GPIO_B2_07_FLEXSPI1_BUS2BIT_A_DQS + MEM_WriteU32(0x42A1023C, 0x17); + MEM_WriteU32(0x42A10544, 0x1); + // IOMUXC_GPIO_B2_08_FLEXSPI1_BUS2BIT_A_SCLK + MEM_WriteU32(0x42A10240, 0x17); + // IOMUXC_GPIO_B2_09_FLEXSPI1_BUS2BIT_A_SS0_B + MEM_WriteU32(0x42A10244, 0x17); + // IOMUXC_GPIO_B2_10_FLEXSPI1_BUS2BIT_A_DATA00 + MEM_WriteU32(0x42A10248, 0x17); + // IOMUXC_GPIO_B2_11_FLEXSPI1_BUS2BIT_A_DATA01 + MEM_WriteU32(0x42A1024C, 0x17); + // IOMUXC_GPIO_B2_12_FLEXSPI1_BUS2BIT_A_DATA02 + MEM_WriteU32(0x42A10250, 0x17); + // IOMUXC_GPIO_B2_13_FLEXSPI1_BUS2BIT_A_DATA03 + MEM_WriteU32(0x42A10254, 0x17); +} + +void _FLEXSPI1_ModuleInit(void) { + + unsigned int reg; + reg = MEM_ReadU32(0x425E0000); + MEM_WriteU32(0x425E0000, (reg & 0xFFFFFFFD)); + + //FLEXSPI1->MCR0 = 0xFFFF8010; + MEM_WriteU32(0x425E0000, 0xFFFF8010); + //FLEXSPI1->MCR2 = 0x200001F7; + MEM_WriteU32(0x425E0008, 0x200001F7); + //FLEXSPI1->AHBCR = 0x78; + MEM_WriteU32(0x425E000C, 0x78); + + //FLEXSPI1->FLSHCR0[0] = 0x00004000; + MEM_WriteU32(0x425E0060, 0x00004000); + + + //FLEXSPI1->FLSHCR4 = 0xC3; + MEM_WriteU32(0x425E0094, 0xC3); + //FLEXSPI1->IPRXFCR = 0x1C; + MEM_WriteU32(0x425E00B8, 0x1C); + + //FLEXSPI1->LUTKEY = 0x5AF05AF0UL; + MEM_WriteU32(0x425E0018, 0x5AF05AF0); + //FLEXSPI1->LUTCR = 0x02; + MEM_WriteU32(0x425E001C, 0x02); + + //FLEXSPI1->LUT[0] = 0x0A1804EB; // AHB Quad Read Change to use Fast Read Quad + MEM_WriteU32(0x425E0200, 0x0A1804EB); + //FLEXSPI1->LUT[1] = 0x26043206; + MEM_WriteU32(0x425E0204, 0x26043206); + //FLEXSPI1->LUT[2] = 0x00000000; + MEM_WriteU32(0x425E0208, 0x00000000); + //FLEXSPI1->LUT[3] = 0x00000000; + MEM_WriteU32(0x425E020C, 0x00000000); + + //FLEXSPI1->LUT[4] = 0x00000406; // Write Enable + MEM_WriteU32(0x425E0210, 0x00000406); + //FLEXSPI1->LUT[5] = 0x00000000; + MEM_WriteU32(0x425E0214, 0x00000000); + //FLEXSPI1->LUT[6] = 0x00000000; + MEM_WriteU32(0x425E0218, 0x00000000); + //FLEXSPI1->LUT[7] = 0x00000000; + MEM_WriteU32(0x425E021C, 0x00000000); + + //FLEXSPI1->LUT[8] = 0x20040401; // Wirte s1 + MEM_WriteU32(0x425E0220, 0x20040401); + //FLEXSPI1->LUT[9] = 0x00000000; + MEM_WriteU32(0x425E0224, 0x00000000); + //FLEXSPI1->LUT[10] = 0x00000000; + MEM_WriteU32(0x425E0228, 0x00000000); + //FLEXSPI1->LUT[11] = 0x00000000; + MEM_WriteU32(0x425E022C, 0x00000000); + + //FLEXSPI1->LUT[12] = 0x24040405; // Read s1 + MEM_WriteU32(0x425E0230, 0x24040405); + //FLEXSPI1->LUT[13] = 0x00000000; + MEM_WriteU32(0x425E0234, 0x00000000); + //FLEXSPI1->LUT[14] = 0x00000000; + MEM_WriteU32(0x425E0238, 0x00000000); + //FLEXSPI1->LUT[15] = 0x00000000; + MEM_WriteU32(0x425E023C, 0x00000000); + + //FLEXSPI1->LUT[16] = 0x00000404; // Write Disable + MEM_WriteU32(0x425E0240, 0x00000404); + //FLEXSPI1->LUT[17] = 0x00000000; + MEM_WriteU32(0x425E0244, 0x00000000); + //FLEXSPI1->LUT[18] = 0x00000000; + MEM_WriteU32(0x425E0248, 0x00000000); + //FLEXSPI1->LUT[19] = 0x00000000; + MEM_WriteU32(0x425E024C, 0x00000000); + + //FLEXSPI1->LUT[20] = 0x20040431; // Wirte s2 + MEM_WriteU32(0x425E0250, 0x20040431); + //FLEXSPI1->LUT[21] = 0x00000000; + MEM_WriteU32(0x425E0254, 0x00000000); + //FLEXSPI1->LUT[22] = 0x00000000; + MEM_WriteU32(0x425E0258, 0x00000000); + //FLEXSPI1->LUT[23] = 0x00000000; + MEM_WriteU32(0x425E025C, 0x00000000); + + //FLEXSPI1->LUT[24] = 0x24040435; // Read s2 + MEM_WriteU32(0x425E0260, 0x24040435); + //FLEXSPI1->LUT[25] = 0x00000000; + MEM_WriteU32(0x425E0264, 0x00000000); + //FLEXSPI1->LUT[26] = 0x00000000; + MEM_WriteU32(0x425E0268, 0x00000000); + //FLEXSPI1->LUT[27] = 0x00000000; + MEM_WriteU32(0x425E026C, 0x00000000); + + //FLEXSPI1->LUT[28] = 0x00000450; // Write Enable Volatile + MEM_WriteU32(0x425E0270, 0x00000450); + //FLEXSPI1->LUT[29] = 0x00000000; + MEM_WriteU32(0x425E0274, 0x00000000); + //FLEXSPI1->LUT[30] = 0x00000000; + MEM_WriteU32(0x425E0278, 0x00000000); + //FLEXSPI1->LUT[31] = 0x00000000; + MEM_WriteU32(0x425E027C, 0x00000000); + + //FLEXSPI1->LUTKEY = 0x5AF05AF0UL; + MEM_WriteU32(0x425E0018, 0x5AF05AF0); + //FLEXSPI1->LUTCR = 0x01; + MEM_WriteU32(0x425E001C, 0x01); +} + +void _FLEXSPI2_ModuleReset() +{ + unsigned int reg; + + reg = MEM_ReadU32(0x445E0000); // FlexSPI2->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + reg = MEM_ReadU32(0x445E0000); + MEM_WriteU32(0x445E0000, (reg | 0x1)); + do + { + reg = MEM_ReadU32(0x445E0000); + } while ((reg & 0x1) != 0); + } +} + +void _FLEXSPI2_WaitBusIdle() +{ + unsigned int reg; + + reg = MEM_ReadU32(0x445E0000); // FlexSPI2->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + do + { + reg = MEM_ReadU32(0x445E00E0); + } while ((reg & 0x3) != 0x3); + } +} + +void _FlexSPI2_SetPinForOctalMode() +{ + // Config IOMUX for FlexSPI2 + MEM_WriteU32(0x42A10088, 0x00000013); // FLEXSPI2_B_DATA03 + MEM_WriteU32(0x42A1008C, 0x00000013); // FLEXSPI2_B_DATA02 + MEM_WriteU32(0x42A10090, 0x00000013); // FLEXSPI2_B_DATA01 + MEM_WriteU32(0x42A10094, 0x00000013); // FLEXSPI2_B_DATA00 + MEM_WriteU32(0x42A1009C, 0x00000013); // FLEXSPI2_A_DATA00 + MEM_WriteU32(0x42A100A0, 0x00000013); // FLEXSPI2_A_DATA01 + MEM_WriteU32(0x42A100A4, 0x00000013); // FLEXSPI2_A_DATA02 + MEM_WriteU32(0x42A100A8, 0x00000013); // FLEXSPI2_A_DATA03 + MEM_WriteU32(0x42A100AC, 0x00000013); // FLEXSPI2_A_SS0_B + MEM_WriteU32(0x42A100B0, 0x00000013); // FLEXSPI2_A_DQS + MEM_WriteU32(0x42A100B4, 0x00000013); // FLEXSPI2_A_SCLK + + //The input daisy!! + MEM_WriteU32(0x42A10594, 0x00000001); // FLEXSPI2_B_DATA03 + MEM_WriteU32(0x42A10590, 0x00000001); // FLEXSPI2_B_DATA02 + MEM_WriteU32(0x42A1058C, 0x00000001); // FLEXSPI2_B_DATA01 + MEM_WriteU32(0x42A10588, 0x00000001); // FLEXSPI2_B_DATA00 + MEM_WriteU32(0x42A10578, 0x00000000); // FLEXSPI2_A_DATA00 + MEM_WriteU32(0x42A1057C, 0x00000000); // FLEXSPI2_A_DATA01 + MEM_WriteU32(0x42A10580, 0x00000000); // FLEXSPI2_A_DATA02 + MEM_WriteU32(0x42A10584, 0x00000000); // FLEXSPI2_A_DATA03 + MEM_WriteU32(0x42A10570, 0x00000000); // FLEXSPI2_A_DQS + MEM_WriteU32(0x42A10598, 0x00000000); // FLEXSPI2_A_SCLK + + // PAD ctrl + MEM_WriteU32(0x42A102D0, 0x00000008); // FLEXSPI2_B_DATA03 + MEM_WriteU32(0x42A102D4, 0x00000008); // FLEXSPI2_B_DATA02 + MEM_WriteU32(0x42A102D8, 0x00000008); // FLEXSPI2_B_DATA01 + MEM_WriteU32(0x42A102DC, 0x00000008); // FLEXSPI2_B_DATA00 + MEM_WriteU32(0x42A102E4, 0x00000008); // FLEXSPI2_A_DATA00 + MEM_WriteU32(0x42A102E8, 0x00000008); // FLEXSPI2_A_DATA01 + MEM_WriteU32(0x42A102EC, 0x00000008); // FLEXSPI2_A_DATA02 + MEM_WriteU32(0x42A102F0, 0x00000008); // FLEXSPI2_A_DATA03 + MEM_WriteU32(0x42A102F4, 0x00000008); // FLEXSPI2_A_SS0_B + MEM_WriteU32(0x42A102F8, 0x00000008); // FLEXSPI2_A_DQS + MEM_WriteU32(0x42A102FC, 0x00000008); // FLEXSPI2_A_SCLK +} + +void _FLEXSPI2_ClockInit() +{ + _WriteViaCM33AP32(0x54484350, 0x0); // ROSC400M_CTRL1 + + // Set flexspi2 root clock, use ROSC400, div = 2 = 1+1 + MEM_WriteU32(0x44450B00, 0x101); // CLOCK_ROOT[22].CONTROL, FlexSPI2 +} + +void _FLEXSPI2_ModuleInit() +{ + // Config FlexSPI2 Registers + + unsigned int reg; + reg = MEM_ReadU32(0x445E0000); + MEM_WriteU32(0x445E0000, (reg & 0xFFFFFFFD)); + + _FLEXSPI2_ModuleReset(); + + MEM_WriteU32(0x445E0000, 0xFFFF3032); // MCR0 + MEM_WriteU32(0x445E0004, 0xFFFFFFFF); // MCR1 + MEM_WriteU32(0x445E0008, 0x200001F7); // MCR2 + MEM_WriteU32(0x445E000C, 0x00000078); // AHBCR prefetch enable + MEM_WriteU32(0x445E0020, 0x800F0000); // AHBRXBUF0CR0 + MEM_WriteU32(0x445E0024, 0x800F0000); // AHBRXBUF1CR0 + MEM_WriteU32(0x445E0028, 0x800F0000); // AHBRXBUF2CR0 + MEM_WriteU32(0x445E002C, 0x800F0000); // AHBRXBUF3CR0 + MEM_WriteU32(0x445E0030, 0x800F0000); // AHBRXBUF4CR0 + MEM_WriteU32(0x445E0034, 0x800F0000); // AHBRXBUF5CR0 + MEM_WriteU32(0x445E0038, 0x80000020); // AHBRXBUF6CR0 + MEM_WriteU32(0x445E003C, 0x80000020); // AHBRXBUF7CR0 + MEM_WriteU32(0x445E00B8, 0x00000000); // IPRXFCR + MEM_WriteU32(0x445E00BC, 0x00000000); // IPTXFCR + + MEM_WriteU32(0x445E0060, 0x00000000); // FLASHA1CR0 + MEM_WriteU32(0x445E0064, 0x00000000); // FLASHA2CR0 + MEM_WriteU32(0x445E0068, 0x00000000); // FLASHB1CR0 + MEM_WriteU32(0x445E006C, 0x00000000); // FLASHB2CR0 + + _FLEXSPI2_WaitBusIdle(); + + MEM_WriteU32(0x445E0060, 0x00002000); // FLASHA1CR0 + MEM_WriteU32(0x445E0070, 0x00021C63); // FLASHA1CR1 + MEM_WriteU32(0x445E0080, 0x00000100); // FLASHA1CR2 + + _FLEXSPI2_WaitBusIdle(); + + MEM_WriteU32(0x445E00C0, 0x00000079); // DLLCRA + MEM_WriteU32(0x445E0000, 0xFFFF3030); // MCR0 + + do + { + reg = MEM_ReadU32(0x445E00E8); + } while (0x3 != (reg & 0x3)); + JLINK_SYS_Sleep(1); + // __delay(100);//100us + + MEM_WriteU32(0x445E0000, 0xFFFF3032); // MCR0 + MEM_WriteU32(0x445E0094, 0x000000C2); // FLASHCR4 + MEM_WriteU32(0x445E0094, 0x000000C6); // FLASHCR4 + MEM_WriteU32(0x445E0000, 0xFFFF3030); // MCR0 + + _FLEXSPI2_WaitBusIdle(); + + MEM_WriteU32(0x445E0018, 0x5AF05AF0); // LUTKEY + MEM_WriteU32(0x445E001C, 0x00000002); // LUTCR + MEM_WriteU32(0x445E0200, 0x8B1887A0); // LUT[0] + MEM_WriteU32(0x445E0204, 0xB7078F10); // LUT[1] + MEM_WriteU32(0x445E0208, 0x0000A704); // LUT[2] + MEM_WriteU32(0x445E020C, 0x00000000); // LUT[3] + MEM_WriteU32(0x445E0210, 0x8B188720); // LUT[4] + MEM_WriteU32(0x445E0214, 0xB7078F10); // LUT[5] + MEM_WriteU32(0x445E0218, 0x0000A304); // LUT[6] + MEM_WriteU32(0x445E021C, 0x00000000); // LUT[7] + MEM_WriteU32(0x445E0220, 0x8B1887E0); // LUT[8] + MEM_WriteU32(0x445E0224, 0xB7078F10); // LUT[9] + MEM_WriteU32(0x445E0228, 0x0000A704); // LUT[10] + MEM_WriteU32(0x445E022C, 0x00000000); // LUT[11] + MEM_WriteU32(0x445E0230, 0x8B188760); // LUT[12] + MEM_WriteU32(0x445E0234, 0xA3028F10); // LUT[13] + MEM_WriteU32(0x445E0238, 0x00000000); // LUT[14] + MEM_WriteU32(0x445E023C, 0x00000000); // LUT[15] + MEM_WriteU32(0x445E0240, 0x00000000); // LUT[16] + MEM_WriteU32(0x445E0244, 0x00000000); // LUT[17] + MEM_WriteU32(0x445E0248, 0x00000000); // LUT[18] + MEM_WriteU32(0x445E024C, 0x00000000); // LUT[19] + MEM_WriteU32(0x445E0018, 0x5AF05AF0); // LUTKEY + MEM_WriteU32(0x445E001C, 0x00000001); // LUTCR + + /* Restore hyperram CR0 register */ + MEM_WriteU32(0x445E00A0, 0x00001000); // IPCR0 + MEM_WriteU32(0x445E00A4, 0x00030002); // IPCR1 + MEM_WriteU32(0x445E00BC, 0x00000001); // IPTXFCR + MEM_WriteU32(0x445E0180, 0x2F8F2F8F); // TFDR 0x8F2F is default value of W756/7x of CR0 + MEM_WriteU32(0x445E0014, 0x00000040); // INTR + MEM_WriteU32(0x445E00B0, 0x00000001); // IPCMD + do + { + reg = MEM_ReadU32(0x445E0014); // INTR + } while ((reg & 0x1) == 0x0); + MEM_WriteU32(0x445E0014, 0x00000001); // INTR + + /* Restore hyperram CR1 register */ + MEM_WriteU32(0x445E00A0, 0x00001002); // IPCR0 + MEM_WriteU32(0x445E00A4, 0x00030002); // IPCR1 + MEM_WriteU32(0x445E00BC, 0x00000001); // IPTXFCR + MEM_WriteU32(0x445E0180, 0xC1FFC1FF); // TFDR 0xFFC1 is default value of W756/7x of CR1 + MEM_WriteU32(0x445E0014, 0x00000040); // INTR + MEM_WriteU32(0x445E00B0, 0x00000001); // IPCMD + do + { + reg = MEM_ReadU32(0x445E0014); // INTR + } while ((reg & 0x1) == 0x0); + MEM_WriteU32(0x445E0014, 0x00000001); // INTR + + _FLEXSPI2_ModuleReset(); +} + +void CM7_InitTCM(U32 targetAddr, U32 size) { + U32 reg; + + reg = _ReadViaCM33AP32(0x52010000); // DMA4->TDC[0].CH_CSR + + if((reg & 0x80000000) != 0) + { + // DMA channel is active, wait it get finished + do + { + reg = _ReadViaCM33AP32(0x52010000); // DMA4->TDC[0].CH_CSR + } while((reg & 0x40000000) == 0); + } + + _WriteViaCM33AP32(0x52010000, 0x40000000); // DMA4->TDC[0].CH_CSR, clear DONE flag + + _WriteViaCM33AP32(0x5201002C, 0x00000000); // DMA4->TCD[0].SLAST_SGA + _WriteViaCM33AP32(0x52010038, 0x00000000); // DMA4->TCD[0].DLAST_SGA + + _WriteViaCM33AP32(0x52010000, 0x40000000); // DMA4->TCD[0].CH_CSR + + _WriteViaCM33AP32(0x52010020, 0x20484000); // DMA4->TCD[0].SADDR + _WriteViaCM33AP32(0x52010030, targetAddr); // DMA4->TCD[0].DADDR + _WriteViaCM33AP32(0x52010028, size); // DMA4->TCD[0].NBYTES_MLOFFNO + _WriteViaCM33AP16(0x52010036, 0x1); // DMA4->TCD[0].ELINKNO + _WriteViaCM33AP16(0x5201003E, 0x1); // DMA4->TCD[0].BITER_ELINKNO + _WriteViaCM33AP16(0x52010026, 0x0303); // DMA4->TCD[0].ATTR + _WriteViaCM33AP16(0x52010024, 0x0); // DMA4->TCD[0].SOFF + _WriteViaCM33AP16(0x52010034, 0x8); // DMA4->TCD[0].DOFF + _WriteViaCM33AP32(0x52010000, 0x7); // DMA4->TDC[0].CH_CSR + _WriteViaCM33AP16(0x5201003C, 0x8); // DMA4->TCD[0].CSR + _WriteViaCM33AP16(0x5201003C, 0x9); // DMA4->TCD[0].CSR + + do + { + reg = _ReadViaCM33AP32(0x52010000); // DMA4->TDC[0].CH_CSR + } while((reg & 0x40000000) == 0); + _WriteViaCM33AP32(0x52010000, 0x40000000); // DMA4->TDC[0].CH_CSR, clear DONE flag +} + +void CM7_KickOff(int ecc_init) +{ + U32 reg, resp1, resp2; + + reg = _ReadViaCM33AP32(_BLK_M7_CFG_ADDR); + if((reg & 0x10) == 0) + { + JLINK_SYS_Report("CM7 is running already"); + } + else + { + JLINK_SYS_Report("************* Begin Operations to Enable CM7 ***********************"); + + // Clock Preparation + JLINK_SYS_Report("******** Prepare Clock *********"); + _WriteViaCM33AP32(0x54484350, 0x0); // ROSC400M_CTRL1 + _WriteViaCM33AP32(0x54450000, 0x100); // CLOCK_ROOT[0].CONTROL, CM7 + + // Release CM7 + _WriteViaCM33AP32(_SRC_SCR_ADDR, 0x1); + + if (ecc_init) + { + // DMA initialization + JLINK_SYS_Report("******** DMA operation *********"); + CM7_InitTCM(0x303C0000, 0x40000); + CM7_InitTCM(0x30400000, 0x40000); + } + + // Making Landing Zone + JLINK_SYS_Report("******** Creating Landing Zone *********"); + _WriteViaCM33AP32(0x303C0000, 0x20020000); + _WriteViaCM33AP32(0x303C0004, 0x00000009); + _WriteViaCM33AP32(0x303C0008, 0xE7FEE7FE); + + // VTOR 0x00 + _WriteViaCM33AP32(_BLK_M7_CFG_ADDR, 0x0010); + + // Trigger ELE + JLINK_SYS_Report("******** ELE Trigger *********"); + _WriteViaCM33AP32(0x57540200, 0x17d20106); // MU_RT_S3MUA->TR[0] + resp1 = _ReadViaCM33AP32(0x57540280); // MU_RT_S3MUA->RR[0] + resp2 = _ReadViaCM33AP32(0x57540284); // MU_RT_S3MUA->RR[1] + JLINK_SYS_Report1("ELE RESP1 : ", resp1); + JLINK_SYS_Report1("ELE RESP2 : ", resp2); + + // Deassert CM7 Wait + JLINK_SYS_Report("******** Kickoff CM7 *********"); + _WriteViaCM33AP32(_BLK_M7_CFG_ADDR, 0x0); + } +} + +void DAP_Init(void) +{ + JLINK_CORESIGHT_Configure(""); + + CORESIGHT_AddAP(0, CORESIGHT_AHB_AP); + CORESIGHT_AddAP(1, CORESIGHT_APB_AP); + CORESIGHT_AddAP(2, CORESIGHT_AHB_AP); + CORESIGHT_AddAP(3, CORESIGHT_AHB_AP); + CORESIGHT_AddAP(4, CORESIGHT_APB_AP); + CORESIGHT_AddAP(5, CORESIGHT_APB_AP); + CORESIGHT_AddAP(6, CORESIGHT_APB_AP); + + JLINK_SYS_Report("***************************************************"); + if(cpuID == _CM7_CPUID) + { + CPU = CORTEX_M7; + CORESIGHT_IndexAHBAPToUse = 2; + JLINK_SYS_Report("Current core is CM7"); + } + else if(cpuID == _CM33_CPUID) + { + CPU = CORTEX_M33; + CORESIGHT_IndexAHBAPToUse = 3; + JLINK_SYS_Report("Current core is CM33"); + + ShowDAPInfo(); + CORESIGHT_AHBAPCSWDefaultSettings = (1<<29)|(1<<25)|(1<<24); + } + else + { + JLINK_SYS_Report1("Wrong CPU ID: ", cpuID); + } + JLINK_SYS_Report("***************************************************"); +} + +void CM33_Halt(void) +{ + U32 reg; + + reg = (_ReadViaCM33AP32(_SRC_SBMR2_ADDR) >> 24) & 0x3F; + + if((reg == 8) || (reg == 9)) // Serial Download Mode, or Boot From Fuse + { + JLINK_SYS_Report("Not flash execution mode, check if CM33 is halted..."); + + reg = _ReadViaCM33AP32(_DCB_DHCSR_ADDR); + + if(0 == (reg & 0x02)) + { + JLINK_SYS_Report1("CM33 is not halted, trying to halt it. CM33 DHCSR: ", reg); + + _WriteViaCM33AP32(_DCB_DHCSR_ADDR, 0xA05F0001); // Enable CM33 debug control + _WriteViaCM33AP32(_DCB_DHCSR_ADDR, 0xA05F0003); // Halt CM33 + reg = _ReadViaCM33AP32(_DCB_DHCSR_ADDR); + if(0 != (reg & 0x02)) + { + JLINK_SYS_Report1("CM33 is halted now. CM33 DHCSR: ", reg); + } + else + { + JLINK_SYS_Report1("CM33 still running, halt failed. CM33 DHCSR: ", reg); + } + } + else + { + JLINK_SYS_Report1("CM33 is halted. CM33 DHCSR: ", reg); + } + } + else + { + JLINK_SYS_Report("Flash execution mode, leave CM33 run status as it was..."); + } +} + +void Flash_Init() { + JLINK_SYS_Report("***************************************************"); + JLINK_SYS_Report("Init Flash"); + + _FLEXSPI1_WaitBusIdle(); + _FLEXSPI1_ModuleReset(); + + _FLEXSPI1_SetPinForQuadMode(); + _FLEXSPI1_ClockInit(); + _FLEXSPI1_ModuleInit(); + + JLINK_SYS_Report("***************************************************"); +} + +void HyperRAM_Init() +{ + JLINK_SYS_Report("***************************************************"); + JLINK_SYS_Report("Init HyperRAM"); + + _FLEXSPI2_WaitBusIdle(); + _FLEXSPI2_ModuleReset(); + + _FlexSPI2_SetPinForOctalMode(); + _FLEXSPI2_ClockInit(); + _FLEXSPI2_ModuleInit(); + + JLINK_SYS_Report("***************************************************"); +} + +void CM33_ClearNVIC(void) { + JLINK_SYS_Report("***************************************************"); + JLINK_SYS_Report("Clear NVIC"); + JLINK_SYS_Report("***************************************************"); + JLINK_MEM_Fill(0xE000E180, 0x40, 0xFF); + JLINK_MEM_Fill(0xE000E280, 0x40, 0xFF); +} + +int InitTarget(void) +{ + int r; + cpuID = _CM33_CPUID; + + DAP_Init(); + + if(cpuID == _CM7_CPUID) + { + CM33_Halt(); + CM7_KickOff(1); + + /* Avoid to access TPIU to prevent soc hang */ + JLINK_ExecCommand("map region 0xE0040000-0xE0040FFF X"); // Mark region as illegal + } + + r = _ReadViaCM33AP32(_SI_VER_ADDR) & 0xF; + + if ( r == 1 ) + { + rom_trap_addr = _ROM_TRAP1_ADDR; + } + else if ( r == 2 ) + { + rom_trap_addr = _ROM_TRAP2_ADDR; + } + else + { + rom_trap_addr = _ROM_TRAP0_ADDR; + } + JLINK_SYS_Report1("SI_VER = ", r); + JLINK_SYS_Report1("TRAP = ", rom_trap_addr); + + return 0; +} + +int SetupTarget(void) +{ + return 0; +} + +void ResetTarget_CM33(void) +{ + int r, w; + int comp, func; + int core_reset_request_bit_mask; + + core_reset_request_bit_mask = 0x100; /* for CM33 core */ + + DBG_ShowReg(0); + + /* Halt the CPU and wait sometime for possible peripheral operation finish */ + JLINK_TARGET_Halt(); + JLINK_SYS_Sleep(10); + + r = JLINK_TARGET_IsHalted(); + if (r != 1) + { + JLINK_SYS_Report("ERR: CM33 core can't be halted!"); + } + + DBG_ShowReg(1); + + /* check and enable core request system reset */ + r = JLINK_MEM_ReadU32(_SRC_SRMASK_ADDR); + if ( (r & core_reset_request_bit_mask) != 0 ) + { + if ( (r & (core_reset_request_bit_mask<<16)) == 0 ) + { + w = r & (~core_reset_request_bit_mask); + r = JLINK_MEM_ReadU32(_SRC_AUTHEN_CTRL_ADDR); + if ( (r & 0x80) == 0 ) + { + JLINK_SYS_Report("Enable system reset via CM33 core reset"); + JLINK_MEM_WriteU32(_SRC_SRMASK_ADDR, w); + ShowDAPInfo(); + } + else + { + JLINK_SYS_Report("ERR: Core reset request is masked and all mask are locked!"); + } + } + else + { + JLINK_SYS_Report("ERR: Core reset request is masked and locked!"); + } + } + + DBG_ShowReg(2); + + JLINK_SYS_Report("Set CM33 watch point"); + comp = JLINK_MEM_ReadU32(_DWT_COMP0_ADDR); /* Save the DWT register and restore them later */ + func = JLINK_MEM_ReadU32(_DWT_FUNC0_ADDR); + JLINK_MEM_WriteU32(_DWT_COMP0_ADDR, rom_trap_addr); + JLINK_MEM_WriteU32(_DWT_FUNC0_ADDR, 0x00000412); + + /* Clear the reset status to avoid ROM clean the core TCM after reset */ + r = JLINK_MEM_ReadU32(_SRC_SRSR_ADDR); + JLINK_MEM_WriteU32(_SRC_SRSR_ADDR, r); + + DBG_ShowReg(3); + + JLINK_SYS_Report("Execute SYSRESETREQ via AIRCR"); + JLINK_MEM_WriteU32(_SCB_AIRCR_ADDR, 0x05FA0004); + JLINK_SYS_Sleep(100); + + r = JLINK_MEM_ReadU32(_DWT_FUNC0_ADDR); + if ((r & 0x01000000) == 0) + { + JLINK_SYS_Report("ERR: CM33 core is not trapped!"); + } + + DBG_ShowReg(4); + + r = JLINK_TARGET_IsHalted(); + if (r == 1) + { + JLINK_SYS_Report("restore CM33 watch point"); + JLINK_MEM_WriteU32(_DWT_COMP0_ADDR, comp); + JLINK_MEM_WriteU32(_DWT_FUNC0_ADDR, func); + } + else + { + JLINK_SYS_Report("ERR: CM33 is not halted after reset!"); + } +} + +void ResetTarget_CM7(void) +{ + int r, w; + int comp, func; + int core_reset_request_bit_mask; + int mem_0, mem_1, mem_2; + + core_reset_request_bit_mask = 0x400; /* for CM7 core */ + + DBG_ShowReg(0); + + /* Halt the CPU and wait sometime for possible peripheral operation finish */ + JLINK_TARGET_Halt(); + JLINK_SYS_Sleep(10); + + r = JLINK_TARGET_IsHalted(); + if (r != 1) + { + JLINK_SYS_Report("ERR: CM7 core can't be halted!"); + } + + DBG_ShowReg(1); + + /* check and enable core request system reset */ + r = JLINK_MEM_ReadU32(_SRC_SRMASK_ADDR); + if ( (r & core_reset_request_bit_mask) != 0 ) + { + if ( (r & (core_reset_request_bit_mask<<16)) == 0 ) + { + w = r & (~core_reset_request_bit_mask); + r = JLINK_MEM_ReadU32(_SRC_AUTHEN_CTRL_ADDR); + if ( (r & 0x80) == 0 ) + { + JLINK_SYS_Report("Enable system reset via CM7 core reset"); + JLINK_MEM_WriteU32(_SRC_SRMASK_ADDR, w); + } + else + { + JLINK_SYS_Report("ERR: Core reset request is masked and all mask are locked!"); + } + } + else + { + JLINK_SYS_Report("ERR: Core reset request is masked and locked!"); + } + } + + DBG_ShowReg(2); + + /* Clear the reset status to avoid ROM clean the core TCM after reset */ + r = JLINK_MEM_ReadU32(_SRC_SRSR_ADDR); + JLINK_MEM_WriteU32(_SRC_SRSR_ADDR, r); + + DBG_ShowReg(3); + + /* CM7_KickOff will use the first 3 words(32bits) of CM7 ITCM, save and restore them later */ + mem_0 = JLINK_MEM_ReadU32(0); + mem_1 = JLINK_MEM_ReadU32(4); + mem_2 = JLINK_MEM_ReadU32(8); + + JLINK_SYS_Report("Set CM33 watch point"); + _WriteViaCM33AP32(_DCB_DHCSR_ADDR, 0xA05F0003); // Enable Debug and halt CM33 core + comp = _ReadViaCM33AP32(_DWT_COMP0_ADDR); /* Save the DWT register and restore them later after reset */ + func = _ReadViaCM33AP32(_DWT_FUNC0_ADDR); + _WriteViaCM33AP32(_DCB_DEMCR_ADDR, 0x01000000); // Enable DWT of CM33 core + _WriteViaCM33AP32(_DWT_COMP0_ADDR, rom_trap_addr); + _WriteViaCM33AP32(_DWT_FUNC0_ADDR, 0x00000412); + + DBG_ShowReg(4); + + JLINK_SYS_Report("Execute SYSRESETREQ via AIRCR"); + JLINK_MEM_WriteU32(_SCB_AIRCR_ADDR, 0x05FA0004); + JLINK_SYS_Sleep(100); + + r = _ReadViaCM33AP32(_DWT_FUNC0_ADDR); + if ((r & 0x01000000) == 0) + { + JLINK_SYS_Report("ERR: CM33 core is not trapped after reset!"); + } + + DBG_ShowReg(5); + + CM7_KickOff(0); + + // Halt CM7 core + JLINK_MEM_WriteU32(_DCB_DHCSR_ADDR, 0xA05F0003); + + DBG_ShowReg(6); + + r = JLINK_TARGET_IsHalted(); + if (r == 1) + { + JLINK_SYS_Report("restore CM7 ITCM"); + + JLINK_MEM_WriteU32(0, mem_0); + JLINK_MEM_WriteU32(4, mem_1); + JLINK_MEM_WriteU32(8, mem_2); + + JLINK_SYS_Report("restore CM33 watch points"); + _WriteViaCM33AP32(_DWT_COMP0_ADDR, comp); + _WriteViaCM33AP32(_DWT_FUNC0_ADDR, func); + } + else + { + JLINK_SYS_Report("ERR: CM7 core can not be halted!"); + } +} + +void ResetTarget(void) { + if(cpuID == _CM7_CPUID) + { + ResetTarget_CM7(); + } + else if(cpuID == _CM33_CPUID) + { + ResetTarget_CM33(); + } +} + +int AfterResetTarget(void) +{ + U32 reg; + + if(cpuID == _CM33_CPUID) + { + // CM33 NVIC may be enabled by ROM after reset + CM33_ClearNVIC(); + } + + Flash_Init(); + HyperRAM_Init(); + + return 0; +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.h new file mode 100644 index 00000000000..3de0cab792c --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.h @@ -0,0 +1,437 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* RT-Thread Kernel */ + +/* klibc options */ + +/* rt_vsnprintf options */ + +/* end of rt_vsnprintf options */ + +/* rt_vsscanf options */ + +/* end of rt_vsscanf options */ + +/* rt_memset options */ + +/* end of rt_memset options */ + +/* rt_memcpy options */ + +/* end of rt_memcpy options */ + +/* rt_memmove options */ + +/* end of rt_memmove options */ + +/* rt_memcmp options */ + +/* end of rt_memcmp options */ + +/* rt_strstr options */ + +/* end of rt_strstr options */ + +/* rt_strcasecmp options */ + +/* end of rt_strcasecmp options */ + +/* rt_strncpy options */ + +/* end of rt_strncpy options */ + +/* rt_strcpy options */ + +/* end of rt_strcpy options */ + +/* rt_strncmp options */ + +/* end of rt_strncmp options */ + +/* rt_strcmp options */ + +/* end of rt_strcmp options */ + +/* rt_strlen options */ + +/* end of rt_strlen options */ + +/* rt_strnlen options */ + +/* end of rt_strnlen options */ +/* end of klibc options */ +#define RT_NAME_MAX 12 +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 4096 + +/* kservice options */ + +#define RT_USING_TINY_FFS +/* end of kservice options */ +#define RT_USING_DEBUG +#define RT_DEBUGING_ASSERT +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +/* end of Inter-Thread communication */ + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP +/* end of Memory Management */ +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x50201 +#define RT_BACKTRACE_LEVEL_MAX_NR 32 +/* end of RT-Thread Kernel */ +#define RT_USING_HW_ATOMIC +#define RT_USING_CPU_FFS +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_FPU +#define ARCH_ARM_CORTEX_SECURE +#define ARCH_ARM_CORTEX_M33 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 4096 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + +/* end of DFS: device virtual file system */ + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN +/* end of Device Drivers */ + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 +/* end of Timezone and Daylight Saving Time */ +/* end of ISO-ANSI C layer */ + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + +/* end of Interprocess Communication (IPC) */ +/* end of POSIX (Portable Operating System Interface) layer */ +/* end of C/C++ and POSIX layer */ + +/* Network */ + +/* end of Network */ + +/* Memory protection */ + +/* end of Memory protection */ + +/* Utilities */ + +/* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ +/* end of RT-Thread Components */ + +/* RT-Thread Utestcases */ + +/* end of RT-Thread Utestcases */ + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + +/* end of Marvell WiFi */ + +/* Wiced WiFi */ + +/* end of Wiced WiFi */ + +/* CYW43012 WiFi */ + +/* end of CYW43012 WiFi */ + +/* BL808 WiFi */ + +/* end of BL808 WiFi */ + +/* CYW43439 WiFi */ + +/* end of CYW43439 WiFi */ +/* end of Wi-Fi */ + +/* IoT Cloud */ + +/* end of IoT Cloud */ +/* end of IoT - internet of things */ + +/* security packages */ + +/* end of security packages */ + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* XML: Extensible Markup Language */ + +/* end of XML: Extensible Markup Language */ +/* end of language packages */ + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + +/* end of LVGL: powerful and easy-to-use embedded GUI library */ + +/* u8g2: a monochrome graphic library */ + +/* end of u8g2: a monochrome graphic library */ +/* end of multimedia packages */ + +/* tools packages */ + +#define PKG_USING_CMBACKTRACE +#define PKG_CMBACKTRACE_PLATFORM_M33 +#define PKG_CMBACKTRACE_DUMP_STACK +#define PKG_CMBACKTRACE_PRINT_ENGLISH +#define PKG_USING_CMBACKTRACE_V10401 +#define PKG_CMBACKTRACE_VER_NUM 0x10401 +/* end of tools packages */ + +/* system packages */ + +/* enhanced kernel services */ + +/* end of enhanced kernel services */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + +/* end of acceleration: Assembly language or algorithmic acceleration packages */ + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* Micrium: Micrium software products porting for RT-Thread */ + +/* end of Micrium: Micrium software products porting for RT-Thread */ +/* end of system packages */ + +/* peripheral libraries and drivers */ + +/* HAL & SDK Drivers */ + +/* STM32 HAL & SDK Drivers */ + +/* end of STM32 HAL & SDK Drivers */ + +/* Infineon HAL Packages */ + +/* end of Infineon HAL Packages */ + +/* Kendryte SDK */ + +/* end of Kendryte SDK */ + +/* WCH HAL & SDK Drivers */ + +/* end of WCH HAL & SDK Drivers */ + +/* AT32 HAL & SDK Drivers */ + +/* end of AT32 HAL & SDK Drivers */ + +/* HC32 DDL Drivers */ + +/* end of HC32 DDL Drivers */ + +/* NXP HAL & SDK Drivers */ + +#define PKG_USING_NXP_IMXRT_DRIVER +#define PKG_USING_NXP_IMXRT_DRIVER_LATEST_VERSION +/* end of NXP HAL & SDK Drivers */ + +/* NUVOTON Drivers */ + +/* end of NUVOTON Drivers */ + +/* GD32 Drivers */ + +/* end of GD32 Drivers */ + +/* HPMicro SDK */ + +/* end of HPMicro SDK */ + +/* FT32 HAL & SDK Drivers */ + +/* end of FT32 HAL & SDK Drivers */ +/* end of HAL & SDK Drivers */ + +/* sensors drivers */ + +/* end of sensors drivers */ + +/* touch drivers */ + +/* end of touch drivers */ +/* end of peripheral libraries and drivers */ + +/* AI packages */ + +/* end of AI packages */ + +/* Signal Processing and Control Algorithm Packages */ + +/* end of Signal Processing and Control Algorithm Packages */ + +/* miscellaneous packages */ + +/* project laboratory */ + +/* end of project laboratory */ + +/* samples: kernel and components samples */ + +/* end of samples: kernel and components samples */ + +/* entertainment: terminal games and other interesting software packages */ + +/* end of entertainment: terminal games and other interesting software packages */ +/* end of miscellaneous packages */ + +/* Arduino libraries */ + + +/* Projects and Demos */ + +/* end of Projects and Demos */ + +/* Sensors */ + +/* end of Sensors */ + +/* Display */ + +/* end of Display */ + +/* Timing */ + +/* end of Timing */ + +/* Data Processing */ + +/* end of Data Processing */ + +/* Data Storage */ + +/* Communication */ + +/* end of Communication */ + +/* Device Control */ + +/* end of Device Control */ + +/* Other */ + +/* end of Other */ + +/* Signal IO */ + +/* end of Signal IO */ + +/* Uncategorized */ + +/* end of Arduino libraries */ +/* end of RT-Thread online packages */ +#define SOC_IMXRT1180_SERIES + +/* Hardware Drivers Config */ + +#define BSP_USING_QSPIFLASH +#define SOC_MIMXRT1189CVM8C +#define SOC_MIMXRT1189CVM8C_CM33 + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_DMA +#define BSP_USING_LPUART +#define BSP_USING_LPUART1 +/* end of On-chip Peripheral Drivers */ + +/* Onboard Peripheral Drivers */ + +/* end of Onboard Peripheral Drivers */ + +/* Board extended module Drivers */ + +/* end of Hardware Drivers Config */ + +#endif diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.py b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.py new file mode 100644 index 00000000000..6de1ec9d9aa --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.py @@ -0,0 +1,198 @@ +import os +import sys + +# toolchains options +ARCH='arm' +CPU='cortex-m33' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armclang' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iccarm' + EXEC_PATH = r'C:/Program Files/IAR Systems/Embedded Workbench 9.2' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' +# BUILD = 'release' + +if PLATFORM == 'gcc': + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + STRIP = PREFIX + 'strip' + + DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=fpv5-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + + CFLAGS = DEVICE + ' -Wall -D__FPU_PRESENT' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -D__START=entry -D__STARTUP_CLEAR_BSS' + LFLAGS = DEVICE + ' -specs=nano.specs -specs=nosys.specs -Wl,--gc-sections,-Map=rtthread.map,--print-memory-usage -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + # AFLAGS += ' -D__STARTUP_INITIALIZE_NONCACHEDATA' + # AFLAGS += ' -D__STARTUP_CLEAR_BSS' + + if BUILD == 'debug': + CFLAGS += ' -g' + AFLAGS += ' -g' + # CFLAGS += ' -O1' + CFLAGS += ' -O0' + else: + CFLAGS += ' -O2 -Os' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + + # module setting + CXXFLAGS = ' -Woverloaded-virtual -fno-exceptions -fno-rtti ' + CXXFLAGS += CFLAGS + + M_CFLAGS = CFLAGS + ' -mlong-calls -fPIC ' + M_CXXFLAGS = CXXFLAGS + ' -mlong-calls -fPIC' + M_LFLAGS = DEVICE + CXXFLAGS + ' -Wl,--gc-sections,-z,max-page-size=0x4' +\ + ' -shared -fPIC -nostartfiles -static-libgcc' + M_POST_ACTION = STRIP + ' -R .hash $TARGET\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu ' + CPU + '.fp.sp' + CFLAGS = DEVICE + ' --apcs=interwork' + AFLAGS = DEVICE + LFLAGS = DEVICE + ' --libpath "' + EXEC_PATH + '\ARM\ARMCC\lib" --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter "board\linker_scripts\link.scf"' + + LFLAGS += ' --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab)' + + CFLAGS += ' --diag_suppress=66,1296,186,6314' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' + LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' + + EXEC_PATH += '/arm/bin40/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' --c99' + + POST_ACTION = 'fromelf -z $TARGET' + # POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + + +elif PLATFORM == 'armclang': + # toolchains + CC = 'armclang' + CXX = 'armclang' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu ' + CPU + CFLAGS = ' --target=arm-arm-none-eabi' + CFLAGS += ' -mcpu=' + CPU + CFLAGS += ' -mfpu=fpv5-sp-d16' + CFLAGS += ' -mfloat-abi=hard' + CFLAGS += ' -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar ' + CFLAGS += ' -gdwarf-3 -ffunction-sections ' + AFLAGS = DEVICE + ' --apcs=interwork ' + AFLAGS += ' -x assembler-with-cpp' + AFLAGS += ' -Wa,-mimplicit-it=thumb' + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers ' + LFLAGS += ' --list rt-thread.map ' + LFLAGS += r' --strict --scatter "board/linker_scripts/link" ' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib' + + EXEC_PATH += '/ARM/ARMCLANG/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O1' # armclang recommend + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iccarm': + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = ' -D__FPU_PRESENT' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=' + CPU + CFLAGS += ' -e' + CFLAGS += ' --fpu=VFPv5_sp' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + + AFLAGS = '' + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu ' + CPU + AFLAGS += ' --fpu VFPv5_sp' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --redirect _Printf=_PrintfTiny' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + # sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) + \ No newline at end of file diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.ewp b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.ewp new file mode 100644 index 00000000000..6de7ddc90f8 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.ewp @@ -0,0 +1,2172 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 36 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 38 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + ILINK + 0 + + 27 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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mode 100644 index 00000000000..0dab8ecf45e --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.uvoptx @@ -0,0 +1,1188 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp; *.cc; *.cxx + 0 + + + + 0 + 0 + + + + rtthread + 0x4 + ARM-ADS + + 33000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + JL2CM3 + -U603001820 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(5BA02477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD30500000 -FC8000 -FN1 -FF0MIMXRT1180_EVK_FSPI1_QSPI_CM33.FMIMXRT1180 CM33 FLEXSPI -FS028000000 -FL01000000 -FP0($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM33.FLM) + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 -FD20000000 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..\..\..\..\..\libcpu\arm\common\div0.c + + + showmem.c + 1 + ..\..\..\..\..\libcpu\arm\common\showmem.c + + + context_rvds.S + 2 + ..\..\..\..\..\libcpu\arm\cortex-m33\context_rvds.S + + + cpuport.c + 1 + ..\..\..\..\..\libcpu\arm\cortex-m33\cpuport.c + + + syscall_rvds.S + 2 + ..\..\..\..\..\libcpu\arm\cortex-m33\syscall_rvds.S + + + trustzone.c + 1 + ..\..\..\..\..\libcpu\arm\cortex-m33\trustzone.c + + + + + Libraries + + + fsl_memory.c + 1 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_memory.c + + + fsl_pmu.c + 1 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_pmu.c + + + fsl_assert.c + 1 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\utilities\debug_console_lite\fsl_assert.c + + + fsl_cache.c + 1 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\cm33\fsl_cache.c + + + fsl_gpc.c + 1 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_gpc.c + + + fsl_soc_src.c + 1 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_soc_src.c + + + fsl_trdc.c + 1 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_trdc.c + + + fsl_rgpio.c + 1 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_rgpio.c + + + fsl_ele_base_api.c + 1 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_ele_base_api.c + + + startup_MIMXRT1189_cm33.s + 2 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\arm\startup_MIMXRT1189_cm33.s + + + system_MIMXRT1189_cm33.c + 1 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\system_MIMXRT1189_cm33.c + + + fsl_clock.c + 1 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_clock.c + + + fsl_common.c + 1 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_common.c + + + fsl_lpuart.c + 1 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_lpuart.c + + + fsl_dcdc.c + 1 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_dcdc.c + + + fsl_common_arm.c + 1 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_common_arm.c + + + fsl_s3mu.c + 1 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_s3mu.c + + + + + xip + + + fsl_flexspi_nor_boot.c + 1 + xip\fsl_flexspi_nor_boot.c + + + evkmimxrt1180_flexspi_nor_config.c + 1 + xip\evkmimxrt1180_flexspi_nor_config.c + + + + + + + + + + + + + + + + + <Project Info> + 0 + 1 + + + + + diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/xip/SConscript b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/xip/SConscript new file mode 100644 index 00000000000..88aa7fb12a7 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/xip/SConscript @@ -0,0 +1,20 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +if GetDepend('BSP_USING_QSPIFLASH'): + cwd = GetCurrentDir() + src = Glob('*.c') + CPPPATH = [cwd] + LINKFLAGS = '' + + if rtconfig.PLATFORM in ['armcc', 'armclang']: + LINKFLAGS += ' --keep=*(.boot_hdr.container)' + # LINKFLAGS += ' --keep=*(.boot_hdr.xmcd_data)' + LINKFLAGS += ' --keep=*(.boot_hdr.conf)' + LINKFLAGS += ' --entry=Reset_Handler ' + LINKFLAGS += ' --predefine="-DXIP_BOOT_HEADER_ENABLE=1"' + LINKFLAGS += ' --predefine="-DXIP_EXTERNAL_FLASH=1"' + + group = DefineGroup('xip', src, depend = [''], CPPPATH = CPPPATH, LINKFLAGS = LINKFLAGS) + Return('group') diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/xip/evkmimxrt1180_flexspi_nor_config.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/xip/evkmimxrt1180_flexspi_nor_config.c new file mode 100644 index 00000000000..b40c379460f --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/xip/evkmimxrt1180_flexspi_nor_config.c @@ -0,0 +1,120 @@ +/* + * Copyright 2018-2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "evkmimxrt1180_flexspi_nor_config.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_board" +#endif + +/* clang-format off */ +#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1) && \ + defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +/* clang-format on */ + +#if defined(USE_HYPERRAM) + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.xmcd_data"), used)) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.xmcd_data" +#endif + +const uint32_t xmcd_data[] = { + 0xC002000C, /* FlexSPI instance 2 */ + 0xC1000800, /* Option words = 2 */ + 0x00010000 /* PINMUX Secondary group */ +}; + +#endif + +#if defined(USE_SDRAM) + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.xmcd_data"), used)) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.xmcd_data" +#endif + +const uint32_t xmcd_data[] = { + 0xC010000D, /* SEMC -> SDRAM */ + 0xA60001A1, /* SDRAM config */ + 0x00008000, /* SDRAM config */ + 0X00000001 /* SDRAM config */ +}; + +#endif + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.conf"), used)) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.conf" +#endif + +/* + * FlexSPI nor flash configuration block + * Note: + * Below setting is special for EVK board flash, to achieve maximum access performance. + * For other boards or flash, may leave it 0 or delete fdcb_data, which means auto probe. + */ + +/* clang-format off */ +#define FLASH_DUMMY_CYCLES 0x06 + +const flexspi_nor_config_t qspi_flash_nor_config = { + .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + // Enable DDR mode, Wordaddassable, Safe configuration, Differential clock + .controllerMiscOption = 0x10, + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_133MHz, + .sflashA1Size = 16u * 1024u * 1024u, + + .configModeType[0] = kDeviceConfigCmdType_Generic, + + .lookupTable = + { + // Read LUTs + [0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18), + [1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, FLASH_DUMMY_CYCLES, READ_SDR, FLEXSPI_4PAD, 0x04), + + // Read Status LUTs + [4 * 1 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x04), + + // Write Enable LUTs + [4 * 3 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, FLEXSPI_1PAD, 0x0), + + // Erase Sector LUTs + [4 * 5 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20, RADDR_SDR, FLEXSPI_1PAD, 0x18), + + // Erase Block LUTs + [4 * 8 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8, RADDR_SDR, FLEXSPI_1PAD, 0x18), + + // Pape Program LUTs + [4 * 9 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02, RADDR_SDR, FLEXSPI_1PAD, 0x18), + [4 * 9 + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0), + + // Erase Chip LUTs + [4 * 11 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60, STOP, FLEXSPI_1PAD, 0x0), + }, + }, + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .ipcmdSerialClkFreq = 0x1, + .blockSize = 64u * 1024u, + .isUniformBlockSize = false, +}; +/* clang-format on */ + +#endif diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/xip/evkmimxrt1180_flexspi_nor_config.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/xip/evkmimxrt1180_flexspi_nor_config.h new file mode 100644 index 00000000000..9b73d5947c1 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/xip/evkmimxrt1180_flexspi_nor_config.h @@ -0,0 +1,190 @@ +/* + * Copyright 2018-2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __EVKMIMXRT1180_FLEXSPI_NOR_CONFIG__ +#define __EVKMIMXRT1180_FLEXSPI_NOR_CONFIG__ + +#include "fsl_common.h" + +/*! @name Driver version */ +/*@{*/ +/*! @brief XIP_DEVICE driver version 2.0.4. */ +#define FSL_XIP_DEVICE_DRIVER_VERSION (MAKE_VERSION(2, 0, 4)) +/*@}*/ + +#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian +#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 + +#define CMD_SDR 0x01 +#define CMD_DDR 0x21 +#define RADDR_SDR 0x02 +#define RADDR_DDR 0x22 +#define CADDR_SDR 0x03 +#define CADDR_DDR 0x23 +#define MODE1_SDR 0x04 +#define MODE1_DDR 0x24 +#define MODE2_SDR 0x05 +#define MODE2_DDR 0x25 +#define MODE4_SDR 0x06 +#define MODE4_DDR 0x26 +#define MODE8_SDR 0x07 +#define MODE8_DDR 0x27 +#define WRITE_SDR 0x08 +#define WRITE_DDR 0x28 +#define READ_SDR 0x09 +#define READ_DDR 0x29 +#define LEARN_SDR 0x0A +#define LEARN_DDR 0x2A +#define DATSZ_SDR 0x0B +#define DATSZ_DDR 0x2B +#define DUMMY_SDR 0x0C +#define DUMMY_DDR 0x2C +#define DUMMY_RWDS_SDR 0x0D +#define DUMMY_RWDS_DDR 0x2D +#define JMP_ON_CS 0x1F +#define STOP 0 + +#define FLEXSPI_1PAD 0 +#define FLEXSPI_2PAD 1 +#define FLEXSPI_4PAD 2 +#define FLEXSPI_8PAD 3 + +#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ + FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) + +//!@brief FlexSPI Read Sample Clock Source definition +typedef enum _FlashReadSampleClkSource +{ + kFlexSPIReadSampleClk_LoopbackInternally = 0, + kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, + kFlexSPIReadSampleClk_Reversed = 2, + kFlexSPIReadSampleClk_FlashProvidedDqs = 3, +} flexspi_read_sample_clk_t; + +//!@brief Flash Type Definition +enum +{ + kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR + kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND + kFlexSpiDeviceType_SerialRAM = 3 //!< Flash devices are Serial RAM/HyperFLASH +}; + +//!@brief Flash Pad Definitions +enum +{ + kSerialFlash_1Pad = 1, + kSerialFlash_2Pads = 2, + kSerialFlash_4Pads = 4, + kSerialFlash_8Pads = 8, +}; + +//!@brief Definitions for FlexSPI Serial Clock Frequency +typedef enum _FlexSpiSerialClockFreq +{ + kFlexSpiSerialClk_30MHz = 1, + kFlexSpiSerialClk_50MHz = 2, + kFlexSpiSerialClk_60MHz = 3, + kFlexSpiSerialClk_80MHz = 4, + kFlexSpiSerialClk_100MHz = 5, + kFlexSpiSerialClk_120MHz = 6, + kFlexSpiSerialClk_133MHz = 7, + kFlexSpiSerialClk_166MHz = 8, +} flexspi_serial_clk_freq_t; + +//!@brief Flash Configuration Command Type +enum +{ + kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc + kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command + kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode + kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode + kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode + kDeviceConfigCmdType_Reset, //!< Reset device command +}; + +//!@brief FlexSPI LUT Sequence structure +typedef struct _lut_sequence +{ + uint8_t seqNum; //!< Sequence Number, valid number: 1-16 + uint8_t seqId; //!< Sequence Index, valid number: 0-15 + uint16_t reserved; +} flexspi_lut_seq_t; + +//!@brief FlexSPI Memory Configuration Block +typedef struct _FlexSPIConfig +{ + uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL + uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix + uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use + uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 + uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 + uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 + uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For + //! Serial NAND, need to refer to datasheet + uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable + uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, + //! Generic configuration, etc. + uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for + //! DPI/QPI/OPI switch or reset command + flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt + //! sequence number, [31:16] Reserved + uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration + uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable + uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe + flexspi_lut_seq_t + configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq + uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use + uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands + uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use + uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more + //! details + uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details + uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal + uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot + //! Chapter for more details + uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot + //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH + uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use + uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 + uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 + uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 + uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 + uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value + uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value + uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value + uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value + uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command + uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands + uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns + uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 + uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - + //! busy flag is 0 when flash device is busy + uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences + flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences + uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use +} flexspi_mem_config_t; + +/* + * Serial NOR configuration block + */ +typedef struct _flexspi_nor_config +{ + flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI + uint32_t pageSize; //!< Page size of Serial NOR + uint32_t sectorSize; //!< Sector size of Serial NOR + uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command + uint8_t isUniformBlockSize; //!< Sector/Block size is the same + uint8_t isDataOrderSwapped; //!< The data order is swapped in OPI DDR mode + uint8_t reserved0[5]; //!< Reserved for future use + uint32_t blockSize; //!< Block size + uint32_t FlashStateCtx; //!< Flash State Context after being configured + uint32_t reserve1[10]; //!< Reserved for future use +} flexspi_nor_config_t; + + +#endif /* __EVKMIMXRT1180_FLEXSPI_NOR_CONFIG__ */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/xip/fsl_flexspi_nor_boot.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/xip/fsl_flexspi_nor_boot.c new file mode 100644 index 00000000000..773275023cf --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/xip/fsl_flexspi_nor_boot.c @@ -0,0 +1,64 @@ +/* + * Copyright 2021-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexspi_nor_boot.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_device" +#endif + +/* clang-format off */ +#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1) && \ + defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +/* clang-format on */ + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.container"), used)) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.container" +#endif + +/* clang-format off */ +const container container_data = +{ + { + CNT_VERSION, + CNT_SIZE, + CNT_TAG_HEADER, + CNT_FLAGS, + CNT_SW_VER, + CNT_FUSE_VER, + CNT_NUM_IMG, + sizeof(cnt_hdr) + CNT_NUM_IMG * sizeof(image_entry), + 0 + }, + {{ + IMAGE_OFFSET, + IMAGE_SIZE, + IMAGE_LOAD_ADDRESS, + 0x00000000, + IMAGE_ENTRY_ADDRESS, + 0x00000000, + IMG_FLAGS, + 0x0, + {0}, + {0} + }}, + { + SGNBK_VERSION, + SGNBK_SIZE, + SGNBK_TAG, + 0x0, + 0x0, + 0x0, + 0x0 + } +}; +/* clang-format on */ + +#endif \ No newline at end of file diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/xip/fsl_flexspi_nor_boot.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/xip/fsl_flexspi_nor_boot.h new file mode 100644 index 00000000000..587b18b7f28 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/xip/fsl_flexspi_nor_boot.h @@ -0,0 +1,122 @@ +/* + * Copyright 2021-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __FLEXSPI_NOR_BOOT_H__ +#define __FLEXSPI_NOR_BOOT_H__ + +#include "fsl_common.h" + +/************************************* + * Container + *************************************/ +/* Container header */ +#define CNT_TAG_HEADER 0x87 +#define CNT_SIZE (uint16_t)(sizeof(container)) +#define CNT_VERSION 0x00 +#define CNT_NUM_IMG 1 +#define CNT_FUSE_VER 0 +#define CNT_SW_VER 0 +#define CNT_FLAGS 0x00000000 // Container not authenticated + +#define IMG_FLAGS 0x00000213 // Non-encrypted, SHA512, CM33, Executable + +#define SGNBK_TAG 0x90 +#define SGNBK_SIZE (uint16_t)(sizeof(sign_block)) +#define SGNBK_VERSION 0x00 + +typedef struct __attribute__((packed)) _cnt_hdr_ +{ + uint8_t version; + uint16_t length; + uint8_t tag; + + uint32_t flags; + + uint16_t sw_ver; + uint8_t fuse_ver; + uint8_t num_images; + + uint16_t sign_blk_offset; + uint16_t reserved1; +} cnt_hdr; + +typedef struct __attribute__((packed)) _img_entry_ +{ + uint32_t offset; + uint32_t size; + uint32_t load_addr; + uint32_t reserved1; + uint32_t entry; + uint32_t reserved2; + uint32_t flags; + uint32_t metadata; + uint8_t hash[64]; + uint8_t iv[32]; +} image_entry; + +typedef struct __attribute__((packed)) _sign_block_ +{ + uint8_t version; + uint16_t length; + uint8_t tag; + + uint16_t cert_offset; + uint16_t srk_offset; + uint16_t sign_offset; + uint16_t blob_offset; + uint32_t reserved1; + uint8_t data[0]; +} sign_block; + +typedef struct __attribute__((packed)) _container_ +{ + cnt_hdr hdr; + image_entry array[CNT_NUM_IMG]; + sign_block sign_block; +} container; + +/* Set resume entry */ +#if defined(__MCUXPRESSO) +extern uint32_t app_image_offset[]; +extern uint32_t _image_size[]; +extern uint32_t _image_loadaddr[]; +extern uint32_t ResetISR[]; +#define IMAGE_OFFSET ((uint32_t)app_image_offset) +#define IMAGE_SIZE ((uint32_t)_image_size) +#define IMAGE_LOAD_ADDRESS ((uint32_t)_image_loadaddr) +#define IMAGE_ENTRY_ADDRESS ((uint32_t)ResetISR) + +#elif defined(__ICCARM__) +#pragma section = "RO" +extern uint32_t __CONTAINER_IMG_OFFSET[]; +extern uint32_t __CONTAINER_IMG_LOAD_ADDR[]; +extern uint32_t __CONTAINER_IMG_ENTRY_ADDR[]; +#define IMAGE_OFFSET ((uint32_t)__CONTAINER_IMG_OFFSET) +#define IMAGE_SIZE ((uint32_t)__section_size("RO")) +#define IMAGE_LOAD_ADDRESS ((uint32_t)__CONTAINER_IMG_LOAD_ADDR) +#define IMAGE_ENTRY_ADDRESS ((uint32_t)__CONTAINER_IMG_ENTRY_ADDR) + +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern uint32_t Image$$ER_m_container_image_offset$$ZI$$Base[]; +extern uint32_t Image$$VECTOR_ROM$$Base[]; +extern uint32_t Load$$LR$$LR_m_text$$Length[]; +#define IMAGE_OFFSET ((uint32_t)Image$$ER_m_container_image_offset$$ZI$$Base) +#define IMAGE_SIZE ((uint32_t)Load$$LR$$LR_m_text$$Length) +#define IMAGE_LOAD_ADDRESS ((uint32_t)Image$$VECTOR_ROM$$Base) +#define IMAGE_ENTRY_ADDRESS ((uint32_t)Image$$VECTOR_ROM$$Base) + +#elif defined(__GNUC__) +extern uint32_t __CONTAINER_IMG_OFFSET[]; +extern uint32_t __CONTAINER_IMG_SIZE[]; +extern uint32_t __VECTOR_TABLE[]; +#define IMAGE_OFFSET ((uint32_t)__CONTAINER_IMG_OFFSET) +#define IMAGE_SIZE ((uint32_t)__CONTAINER_IMG_SIZE) +#define IMAGE_LOAD_ADDRESS ((uint32_t)__VECTOR_TABLE) +#define IMAGE_ENTRY_ADDRESS ((uint32_t)__VECTOR_TABLE) +#endif + +#endif /* __FLEXSPI_NOR_BOOT_H__ */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.config b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.config new file mode 100644 index 00000000000..865c32e1af5 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.config @@ -0,0 +1,1471 @@ + +# +# RT-Thread Kernel +# + +# +# klibc options +# + +# +# rt_vsnprintf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set +# end of rt_vsnprintf options + +# +# rt_vsscanf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSSCANF is not set +# end of rt_vsscanf options + +# +# rt_memset options +# +# CONFIG_RT_KLIBC_USING_USER_MEMSET is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMSET is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMSET is not set +# end of rt_memset options + +# +# rt_memcpy options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMCPY is not set +# end of rt_memcpy options + +# +# rt_memmove options +# +# CONFIG_RT_KLIBC_USING_USER_MEMMOVE is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMMOVE is not set +# end of rt_memmove options + +# +# rt_memcmp options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCMP is not set +# end of rt_memcmp options + +# +# rt_strstr options +# +# CONFIG_RT_KLIBC_USING_USER_STRSTR is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRSTR is not set +# end of rt_strstr options + +# +# rt_strcasecmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCASECMP is not set +# end of rt_strcasecmp options + +# +# rt_strncpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCPY is not set +# end of rt_strncpy options + +# +# rt_strcpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCPY is not set +# end of rt_strcpy options + +# +# rt_strncmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCMP is not set +# end of rt_strncmp options + +# +# rt_strcmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCMP is not set +# end of rt_strcmp options + +# +# rt_strlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRLEN is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRLEN is not set +# end of rt_strlen options + +# +# rt_strnlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set +# end of rt_strnlen options +# end of klibc options + +CONFIG_RT_NAME_MAX=12 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=4096 +# CONFIG_RT_USING_TIMER_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set + +# +# kservice options +# +# CONFIG_RT_USING_TINY_FFS is not set +# end of kservice options + +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_ASSERT=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_AUTO_INIT is not set +# CONFIG_RT_USING_CI_ACTION is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set +# end of Inter-Thread communication + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_SMALL_MEM is not set +# CONFIG_RT_USING_SLAB is not set +CONFIG_RT_USING_MEMHEAP=y +CONFIG_RT_MEMHEAP_FAST_MODE=y +# CONFIG_RT_MEMHEAP_BEST_MODE is not set +# CONFIG_RT_USING_SMALL_MEM_AS_HEAP is not set +CONFIG_RT_USING_MEMHEAP_AS_HEAP=y +CONFIG_RT_USING_MEMHEAP_AUTO_BINDING=y +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +# end of Memory Management + +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x50201 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# end of RT-Thread Kernel + +CONFIG_RT_USING_HW_ATOMIC=y +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_FPU=y +CONFIG_ARCH_ARM_CORTEX_M33=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=4096 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +# CONFIG_FINSH_USING_WORD_OPERATION is not set +# CONFIG_FINSH_USING_FUNC_EXT is not set +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# end of DFS: device virtual file system + +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_DEV_BUS is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_SERIAL_BYPASS is not set +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_PHY_V2 is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_BLK is not set +# CONFIG_RT_USING_VIRTIO is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_KTIME is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CHERRYUSB is not set +# end of Device Drivers + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 +# end of Timezone and Daylight Saving Time +# end of ISO-ANSI C layer + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# end of Interprocess Communication (IPC) +# end of POSIX (Portable Operating System Interface) layer + +# CONFIG_RT_USING_CPLUSPLUS is not set +# end of C/C++ and POSIX layer + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set +# end of Network + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set +# end of Memory protection + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# end of Utilities + +# CONFIG_RT_USING_VBUS is not set + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set +# end of RT-Thread Components + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set +# end of RT-Thread Utestcases + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set +# CONFIG_PKG_USING_ESP_HOSTED is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set +# end of Marvell WiFi + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# end of Wiced WiFi + +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set +# end of CYW43012 WiFi + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set +# end of BL808 WiFi + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# end of CYW43439 WiFi +# end of Wi-Fi + +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# end of IoT Cloud + +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set +# CONFIG_PKG_USING_PNET is not set +# CONFIG_PKG_USING_OPENER is not set +# CONFIG_PKG_USING_FREEMQTT is not set +# end of IoT - internet of things + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set +# end of security packages + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set +# CONFIG_PKG_USING_RYAN_JSON is not set +# end of JSON: JavaScript Object Notation, a lightweight data-interchange format + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# end of XML: Extensible Markup Language + +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set +# end of language packages + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set +# end of LVGL: powerful and easy-to-use embedded GUI library + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# end of u8g2: a monochrome graphic library + +# CONFIG_PKG_USING_NES_SIMULATOR is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set +# end of multimedia packages + +# +# tools packages +# +# CONFIG_PKG_USING_VECTOR is not set +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_MCOREDUMP is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_ZDEBUG is not set +# CONFIG_PKG_USING_RVBACKTRACE is not set +# CONFIG_PKG_USING_HPATCHLITE is not set +# CONFIG_PKG_USING_THREAD_METRIC is not set +# CONFIG_PKG_USING_UORB is not set +# CONFIG_PKG_USING_RT_TUNNEL is not set +# CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set +# end of tools packages + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# end of enhanced kernel services + +# CONFIG_PKG_USING_AUNITY is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# end of acceleration: Assembly language or algorithmic acceleration packages + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_CORE is not set +# CONFIG_PKG_USING_CMSIS_NN is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set +# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# end of Micrium: Micrium software products porting for RT-Thread + +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_UART_FRAMEWORK is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_RMP is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set +# CONFIG_PKG_USING_HEARTBEAT is not set +# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# CONFIG_PKG_USING_CHERRYECAT is not set +# end of system packages + +# +# peripheral libraries and drivers +# + +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32F0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_STM32WL_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WL_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set +# end of STM32 HAL & SDK Drivers + +# +# Infineon HAL Packages +# +# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set +# CONFIG_PKG_USING_INFINEON_CMSIS is not set +# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set +# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_ESP_IDF is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# end of Kendryte SDK + +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_MM32 is not set + +# +# WCH HAL & SDK Drivers +# +# CONFIG_PKG_USING_CH32V20x_SDK is not set +# CONFIG_PKG_USING_CH32V307_SDK is not set +# end of WCH HAL & SDK Drivers + +# +# AT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_AT32A403A_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A403A_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_CMSIS_DRIVER is not set +# end of AT32 HAL & SDK Drivers + +# +# HC32 DDL Drivers +# +# CONFIG_PKG_USING_HC32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F3_SERIES_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_SERIES_DRIVER is not set +# end of HC32 DDL Drivers + +# +# NXP HAL & SDK Drivers +# +# CONFIG_PKG_USING_NXP_MCX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NXP_MCX_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC55S_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6SX_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set +CONFIG_PKG_USING_NXP_IMXRT_DRIVER=y +CONFIG_PKG_NXP_IMXRT_DRIVER_PATH="/packages/peripherals/hal-sdk/nxp/nxp-imxrt-sdk" +CONFIG_PKG_USING_NXP_IMXRT_DRIVER_LATEST_VERSION=y +CONFIG_PKG_NXP_IMXRT_DRIVER_VER="latest" +# end of NXP HAL & SDK Drivers + +# +# NUVOTON Drivers +# +# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set +# end of NUVOTON Drivers + +# +# GD32 Drivers +# +# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32_RISCV_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32VW55X_WIFI is not set +# end of GD32 Drivers + +# +# HPMicro SDK +# +# CONFIG_PKG_USING_HPM_SDK is not set +# end of HPMicro SDK + +# +# FT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_FT32F0_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set +# end of FT32 HAL & SDK Drivers +# end of HAL & SDK Drivers + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_MAX31855 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90384 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90396 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set +# CONFIG_PKG_USING_P3T1755 is not set +# CONFIG_PKG_USING_QMI8658 is not set +# CONFIG_PKG_USING_ICM20948 is not set +# CONFIG_PKG_USING_SCD4X is not set +# end of sensors drivers + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# end of touch drivers + +# CONFIG_PKG_USING_LCD_SPI_DRIVER is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_BT_MX02 is not set +# CONFIG_PKG_USING_GC9A01 is not set +# CONFIG_PKG_USING_IK485 is not set +# CONFIG_PKG_USING_SERVO is not set +# CONFIG_PKG_USING_SEAN_WS2812B is not set +# CONFIG_PKG_USING_IC74HC165 is not set +# CONFIG_PKG_USING_IST8310 is not set +# CONFIG_PKG_USING_ST7789_SPI is not set +# CONFIG_PKG_USING_CAN_UDS is not set +# CONFIG_PKG_USING_ISOTP_C is not set +# CONFIG_PKG_USING_IKUNLED is not set +# CONFIG_PKG_USING_INS5T8025 is not set +# CONFIG_PKG_USING_ST7305 is not set +# CONFIG_PKG_USING_TM1668 is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set +# end of peripheral libraries and drivers + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set +# CONFIG_PKG_USING_LLMCHAT is not set +# end of AI packages + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_APID is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set +# CONFIG_PKG_USING_CMSIS_DSP is not set +# end of Signal Processing and Control Algorithm Packages + +# +# miscellaneous packages +# + +# +# project laboratory +# +# end of project laboratory + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# end of samples: kernel and components samples + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# CONFIG_PKG_USING_TINYSQUARE is not set +# end of entertainment: terminal games and other interesting software packages + +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LIBCRC is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set +# CONFIG_PKG_USING_DRMP is not set +# end of miscellaneous packages + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_RTDUINO_SENSORFUSION_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set +# end of Projects and Demos + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set +# end of Sensors + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set +# end of Display + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set +# end of Timing + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set +# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set +# end of Data Processing + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set +# end of Communication + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# end of Device Control + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# end of Other + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set +# end of Signal IO + +# +# Uncategorized +# +# end of Arduino libraries +# end of RT-Thread online packages + +CONFIG_SOC_IMXRT1180_SERIES=y + +# +# Hardware Drivers Config +# +CONFIG_BSP_USING_QSPIFLASH=y +CONFIG_SOC_MIMXRT1189CVM8C=y +CONFIG_SOC_MIMXRT1189CVM8C_CM7=y + +# +# On-chip Peripheral Drivers +# +# CONFIG_BSP_USING_DMA is not set +CONFIG_BSP_USING_GPIO=y +# CONFIG_BSP_USING_RTC is not set +# CONFIG_BSP_USING_USB is not set +# CONFIG_BSP_USING_SDIO is not set +CONFIG_BSP_USING_LPUART=y +CONFIG_BSP_USING_LPUART1=y +# CONFIG_BSP_LPUART1_RX_USING_DMA is not set +# CONFIG_BSP_LPUART1_TX_USING_DMA is not set +# CONFIG_BSP_USING_LPUART3 is not set +# CONFIG_BSP_USING_CAN is not set +# CONFIG_BSP_USING_FLEXSPI is not set +# end of On-chip Peripheral Drivers + +# +# Onboard Peripheral Drivers +# +# CONFIG_BSP_USING_SDRAM is not set +# CONFIG_BSP_USING_ETH is not set +# CONFIG_BSP_USING_FS is not set +# CONFIG_BSP_USING_VGLITE is not set +# end of Onboard Peripheral Drivers + +# +# Board extended module Drivers +# +# end of Hardware Drivers Config diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/Kconfig b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/Kconfig new file mode 100644 index 00000000000..91fa11dd5da --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/Kconfig @@ -0,0 +1,10 @@ +mainmenu "RT-Thread Configuration" + +RTT_DIR := ../../../../../.. + +PKGS_DIR := packages + +source "$(RTT_DIR)/Kconfig" +osource "$PKGS_DIR/Kconfig" +rsource "../../libraries/Kconfig" +rsource "board/Kconfig" diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/SConscript b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/SConscript new file mode 100644 index 00000000000..c7ef7659ece --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/SConstruct b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/SConstruct new file mode 100644 index 00000000000..644e0534ecc --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/SConstruct @@ -0,0 +1,88 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +def bsp_pkg_check(): + import subprocess + + check_paths = [ + os.path.join("..", "packages", "nxp-imxrt-sdk-latest"), + ] + + need_update = not all(os.path.exists(p) for p in check_paths) + + if need_update: + print("\n===============================================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") + print("===============================================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT +DefaultEnvironment(tools=[]) +if rtconfig.PLATFORM == 'armcc': + env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, + # overwrite cflags, because cflags has '--C99' + CXXCOM = '$CXX -o $TARGET --cpp -c $CXXFLAGS $_CCCOMCOM $SOURCES') +else: + env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, + CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES') + +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM in ['iccarm']: + env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./..') +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +imxrt_library = 'MIMXRT1180' +rtconfig.BSP_LIBRARY_TYPE = imxrt_library + +# include libraries +objs.extend(SConscript(os.path.join("..", "packages/nxp-imxrt-sdk-latest", imxrt_library, 'SConscript'))) + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/SConscript b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/SConscript new file mode 100644 index 00000000000..050054c59fd --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/SConscript @@ -0,0 +1,22 @@ +import rtconfig +from building import * +import os + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +# add for startup script +if rtconfig.PLATFORM in ['gcc']: + CPPDEFINES = ['__START=entry'] +else: + CPPDEFINES = [] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) + +list = os.listdir(cwd) +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + group = group + SConscript(os.path.join(item, 'SConscript')) + +Return('group') diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/main.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/main.c new file mode 100644 index 00000000000..5c4b4373dfd --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/main.c @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-05-06 tyustli first version + * + */ + +#include +#include +#include +#include + +int main(void) +{ + rt_kprintf("MIMXRT1180_CM7 Hello_World\r\n"); + + while (1) + { + rt_thread_mdelay(500); + } +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/mnt.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/mnt.c new file mode 100644 index 00000000000..bb7a9406502 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/mnt.c @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-09-19 Gavin first version + * + */ + +#include +#ifdef RT_USING_DFS_RAMFS +#include + +extern struct dfs_ramfs *dfs_ramfs_create(rt_uint8_t *pool, rt_size_t size); + +int mnt_init(void) +{ + rt_uint8_t *pool = RT_NULL; + rt_size_t size = 8*1024*1024; + + pool = rt_malloc(size); + if (pool == RT_NULL) + return 0; + + if (dfs_mount(RT_NULL, "/", "ram", 0, (const void *)dfs_ramfs_create(pool, size)) == 0) + rt_kprintf("RAM file system initializated!\n"); + else + rt_kprintf("RAM file system initializate failed!\n"); + + return 0; +} +INIT_ENV_EXPORT(mnt_init); +#endif + +#ifdef BSP_USING_SDCARD_FATFS +#include +#include +#define DBG_TAG "app.filesystem" +#define DBG_LVL DBG_INFO +#include +static int filesystem_mount(void) +{ + while(rt_device_find("sd0") == RT_NULL) + { + rt_thread_mdelay(1); + } + + int ret = dfs_mount("sd0", "/", "elm", 0, 0); + if (ret != 0) + { + rt_kprintf("ret: %d\n",ret); + LOG_E("sd0 mount to '/' failed!"); + return ret; + } + + return RT_EOK; +} +INIT_ENV_EXPORT(filesystem_mount); +#endif diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/Kconfig b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/Kconfig new file mode 100644 index 00000000000..d2cdad35fc1 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/Kconfig @@ -0,0 +1,278 @@ +menu "Hardware Drivers Config" + +config BSP_USING_QSPIFLASH + bool + default n + +config SOC_MIMXRT1189CVM8C + bool + select SOC_IMXRT1180_SERIES + select BSP_USING_QSPIFLASH + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +config SOC_MIMXRT1189CVM8C_CM7 + bool + default y + depends on SOC_MIMXRT1189CVM8C + +config BSP_USING_LCD_MIPI + bool + default n + +menu "On-chip Peripheral Drivers" + + config BSP_USING_DMA + bool "Enable DMA" + default n + + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + config BSP_USING_RTC + bool "Enable RTC" + select RT_USING_RTC + default n + + config BSP_USING_USB + bool "Enable USB" + select RT_USING_USB_HOST + default n + + if BSP_USING_USB + config BSP_USB0_HOST + bool "Enable USB0" + default n + + config BSP_USB1_HOST + bool "Enable USB1" + default n + endif + + config BSP_USING_SDIO + bool "Enable SDIO" + select RT_USING_SDIO + select RT_USING_DFS + default n + + if BSP_USING_SDIO + config CODE_STORED_ON_SDCARD + bool "Enable Code STORED On SDCARD" + default n + help + "SD CARD work as boot devive" + endif + + menuconfig BSP_USING_LPUART + bool "Enable UART" + select RT_USING_SERIAL + default y + + if BSP_USING_LPUART + config BSP_USING_LPUART1 + bool "Enable LPUART1" + default y + + config BSP_LPUART1_RX_USING_DMA + bool "Enable LPUART1 RX DMA" + depends on BSP_USING_LPUART1 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART1_RX_DMA_CHANNEL + depends on BSP_LPUART1_RX_USING_DMA + int "Set LPUART1 RX DMA channel (0-32)" + default 0 + + config BSP_LPUART1_TX_USING_DMA + bool "Enable LPUART1 TX DMA" + depends on BSP_USING_LPUART1 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART1_TX_DMA_CHANNEL + depends on BSP_LPUART1_TX_USING_DMA + int "Set LPUART1 TX DMA channel (0-32)" + default 1 + + config BSP_USING_LPUART3 + bool "Enable LPUART3" + default n + + config BSP_LPUART3_RX_USING_DMA + bool "Enable LPUART3 RX DMA" + depends on BSP_USING_LPUART3 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART3_RX_DMA_CHANNEL + depends on BSP_LPUART3_RX_USING_DMA + int "Set LPUART3 RX DMA channel (0-32)" + default 0 + + config BSP_LPUART3_TX_USING_DMA + bool "Enable LPUART3 TX DMA" + depends on BSP_USING_LPUART3 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART3_TX_DMA_CHANNEL + depends on BSP_LPUART3_TX_USING_DMA + int "Set LPUART3 TX DMA channel (0-32)" + default 1 + endif + + menuconfig BSP_USING_CAN + bool "Enable CAN" + select RT_USING_CAN + default n + if BSP_USING_CAN + config BSP_USING_CAN3 + bool "Enable FLEXCAN3" + default n + endif + + menuconfig BSP_USING_FLEXSPI + bool "Enable FLEXSPI" + default n + if BSP_USING_FLEXSPI + config BSP_USING_FLEXSPI1 + bool "Enable FLEXSPI1" + default n + config BSP_USING_FLEXSPI2 + bool "Enable FLEXSPI2" + default n + endif +endmenu + +menu "Onboard Peripheral Drivers" + + config BSP_USING_SDRAM + bool "Enable SDRAM" + default n + + menuconfig BSP_USING_ETH + bool "Enable Ethernet" + select RT_USING_NETDEV + select RT_USING_LWIP + default n + + + if BSP_USING_ETH + config BSP_USING_PHY + select RT_USING_PHY + bool "Enable ethernet phy" + default y + + if BSP_USING_PHY + config PHY_USING_KSZ8081 + bool "i.MX RT1176EVK uses ksz8081 phy" + default y + + if PHY_USING_KSZ8081 + config PHY_KSZ8081_ADDRESS + int "Specify address of phy device" + default 2 + + config PHY_RESET_KSZ8081_PORT + int "indicate port of reset" + default 6 + + config PHY_RESET_KSZ8081_PIN + int "indicate pin of reset" + default 12 + + config FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE + bool "Enable the PHY ksz8081 RMII50M mode" + depends on PHY_USING_KSZ8081 + default y + endif + endif + + if BSP_USING_PHY + config PHY_USING_RTL8211F + bool "i.MX RT1176EVK uses rtl8211f phy" + default y + + if PHY_USING_RTL8211F + config PHY_RTL8211F_ADDRESS + int "Specify address of phy device" + default 1 + + config PHY_RESET_RTL8211F_PORT + int "indicate port of reset" + default 5 + + config PHY_RESET_RTL8211F_PIN + int "indicate pin of reset" + default 14 + + endif + endif + endif + + menuconfig BSP_USING_FS + bool "Enable File System" + select RT_USING_DFS_DEVFS + select RT_USING_DFS + default n + + if BSP_USING_FS + config BSP_USING_SDCARD_FATFS + bool "Enable SDCARD (FATFS)" + select BSP_USING_SDIO + select RT_USING_DFS_ELMFAT + default n + endif + + menuconfig BSP_USING_VGLITE + bool "Enable VGLite" + select RT_USING_PIN + select BSP_USING_LCD_MIPI + default n + + if BSP_USING_VGLITE + choice + prompt "Select display panel" + default DISPLAY_USING_RK055AHD091 + + config DISPLAY_USING_RK055AHD091 + bool "RK055AHD091-CTG (RK055HDMIPI4M 720 * 1280)" + + config DISPLAY_USING_RK055IQH091 + bool "RK055IQH091-CTG (540 * 960)" + + config DISPLAY_USING_RK055MHD091 + bool "RK055MHD091A0-CTG (RK055HDMIPI4MA0 720 * 1280)" + endchoice + + choice + prompt "Select display controller" + default BSP_USING_LCDIFV2 + + config BSP_USING_ELCDIF + bool "ELCDIF" + + config BSP_USING_LCDIFV2 + bool "LCDIFV2" + endchoice + + config VGLITE_USING_ELM + bool "Enable Elementary" + default y + endif + +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/MCUX_Config.mex b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/MCUX_Config.mex new file mode 100644 index 00000000000..85d03f19933 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/MCUX_Config.mex @@ -0,0 +1,596 @@ + + + + MIMXRT1176xxxxx + MIMXRT1176DVMAA + ksdk2_0 + + + + + + + + true + false + false + true + false + + + + + 12.0.0 + + + + + Configures pin routing and optionally pin electrical features. + + true + cm7 + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 12.0.0 + + + + + + + + + true + + + + + INPUT + + + + + true + + + + + OUTPUT + + + + + true + + + + + INPUT + + + + + true + + + + + OUTPUT + + + + + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + true + + + + + + 12.0.0 + c_array + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 12.0.0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + N/A + + + + \ No newline at end of file diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/clock_config.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/clock_config.c new file mode 100644 index 00000000000..7c1d7f6afdf --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/clock_config.c @@ -0,0 +1,836 @@ +/* + * Copyright 2022-2025 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * How to setup clock using clock driver functions: + * + * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock. + * + * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock. + * + * 3. Call CLOCK_SetRootClock() to configure corresponding module clock source and divider. + * + */ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v13.0 +processor: MIMXRT1189xxxxx +package_id: MIMXRT1189CVM8C +mcu_data: ksdk2_0 +processor_version: 0.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +#include "clock_config.h" +#include "fsl_misc.h" +#include "fsl_dcdc.h" +#include "fsl_pmu.h" +#include "fsl_clock.h" +#include "fsl_ele_base_api.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*FUNCTION********************************************************************** + * + * Function Name : BOARD_FlexspiClockSafeConfig + * Description : FLEXSPI clock source safe configuration weak function. + * Called before clock source configuration. + * Note : Users need override this function to change FLEXSPI clock source to stable source when executing + * code on FLEXSPI memory(XIP). If XIP, the function should runs in RAM and move the FLEXSPI clock source + * to a stable clock to avoid instruction/data fetch issue during clock updating. + *END**************************************************************************/ +__attribute__((weak)) void BOARD_FlexspiClockSafeConfig(void) +{ +} + +/*FUNCTION********************************************************************** + * + * Function Name : BOARD_SetFlexspiClock + * Description : This function should be overridden if executing code on FLEXSPI memory(XIP). + * To Change FLEXSPI clock, should move to run from RAM and then configure FLEXSPI clock source. + * After the clock is changed and stable, move back to run on FLEXSPI. + * Param base : FLEXSPI peripheral base address. + * Param src : FLEXSPI clock source. + * Param divider : FLEXSPI clock divider. + *END**************************************************************************/ +__attribute__((weak)) void BOARD_SetFlexspiClock(FLEXSPI_Type *base, uint8_t src, uint32_t divider) +{ +} + +/*FUNCTION********************************************************************** + * + * Function Name : EdgeLock_SetClock + * Description : Set EdgeLock clock via safe method + * Note : It requires specific sequence to change edgelock clock source, + * otherwise the soc behavior is unpredictable. + *END**************************************************************************/ +__attribute__((weak)) void EdgeLock_SetClock(uint8_t mux, uint8_t div) +{ +} + +/*FUNCTION********************************************************************** + * + * Function Name : DCDC_SetVoltage + * Description : Set DCDC voltage via safe method + * Note : It requires specific sequence to change DCDC voltage when GDET + * is enabled, otherwise the soc behavior is unpredictable. + *END**************************************************************************/ +__attribute__((weak)) void DCDC_SetVoltage(uint8_t core, uint8_t targetVoltage) +{ +} + + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockRUN(); +} + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockRUN +called_from_default_init: true +outputs: +- {id: ACMP_CLK_ROOT.outFreq, value: 240 MHz} +- {id: ADC1_CLK_ROOT.outFreq, value: 80 MHz} +- {id: ADC2_CLK_ROOT.outFreq, value: 80 MHz} +- {id: ARM_PLL_CLK.outFreq, value: 792 MHz} +- {id: ASRC_CLK_ROOT.outFreq, value: 240 MHz} +- {id: BUS_AON_CLK_ROOT.outFreq, value: 132 MHz} +- {id: BUS_WAKEUP_CLK_ROOT.outFreq, value: 132 MHz} +- {id: CAN1_CLK_ROOT.outFreq, value: 80 MHz} +- {id: CAN2_CLK_ROOT.outFreq, value: 80 MHz} +- {id: CAN3_CLK_ROOT.outFreq, value: 80 MHz} +- {id: CCM_CKO1_CLK_ROOT.outFreq, value: 80 MHz} +- {id: CCM_CKO2_CLK_ROOT.outFreq, value: 50 MHz} +- {id: CLK_1M.outFreq, value: 1 MHz} +- {id: ECAT_CLK_ROOT.outFreq, value: 100 MHz} +- {id: ECAT_PORT0_REF_CLK.outFreq, value: 50 MHz} +- {id: ECAT_PORT1_REF_CLK.outFreq, value: 50 MHz} +- {id: EDGELOCK_CLK_ROOT.outFreq, value: 200 MHz} +- {id: ENET_REFCLK_ROOT.outFreq, value: 125 MHz} +- {id: FLEXIO1_CLK_ROOT.outFreq, value: 120 MHz} +- {id: FLEXIO2_CLK_ROOT.outFreq, value: 48 MHz} +- {id: FLEXSPI1_CLK_ROOT.outFreq, value: 1440/11 MHz} +- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 2160/11 MHz} +- {id: FLEXSPI_SLV_CLK_ROOT.outFreq, value: 132 MHz} +- {id: GPT1_CLK_ROOT.outFreq, value: 240 MHz} +- {id: GPT2_CLK_ROOT.outFreq, value: 240 MHz} +- {id: I3C1_CLK_ROOT.outFreq, value: 24 MHz} +- {id: I3C2_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPI2C0102_CLK_ROOT.outFreq, value: 60 MHz} +- {id: LPI2C0304_CLK_ROOT.outFreq, value: 60 MHz} +- {id: LPI2C0506_CLK_ROOT.outFreq, value: 60 MHz} +- {id: LPIT3_CLK_ROOT.outFreq, value: 80 MHz} +- {id: LPSPI0102_CLK_ROOT.outFreq, value: 1440/11 MHz} +- {id: LPSPI0304_CLK_ROOT.outFreq, value: 1440/11 MHz} +- {id: LPSPI0506_CLK_ROOT.outFreq, value: 1440/11 MHz} +- {id: LPTMR1_CLK_ROOT.outFreq, value: 80 MHz} +- {id: LPTMR2_CLK_ROOT.outFreq, value: 80 MHz} +- {id: LPTMR3_CLK_ROOT.outFreq, value: 80 MHz} +- {id: LPUART0102_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART0304_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART0506_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART0708_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART0910_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART1112_CLK_ROOT.outFreq, value: 24 MHz} +- {id: M33_CLK_ROOT.outFreq, value: 240 MHz} +- {id: M33_SYSTICK_CLK_ROOT.outFreq, value: 100 kHz} +- {id: M7_CLK_ROOT.outFreq, value: 792 MHz} +- {id: M7_SYSTICK_CLK_ROOT.outFreq, value: 100 kHz} +- {id: MAC0_CLK_ROOT.outFreq, value: 50 MHz} +- {id: MAC1_CLK_ROOT.outFreq, value: 125 MHz} +- {id: MAC2_CLK_ROOT.outFreq, value: 125 MHz} +- {id: MAC3_CLK_ROOT.outFreq, value: 125 MHz} +- {id: MAC4_CLK_ROOT.outFreq, value: 50 MHz} +- {id: MIC_CLK_ROOT.outFreq, value: 80 MHz} +- {id: NETC_CLK_ROOT.outFreq, value: 240 MHz} +- {id: NETC_PORT0_REF_CLK.outFreq, value: 50 MHz} +- {id: NETC_PORT1_REF_CLK.outFreq, value: 50 MHz} +- {id: NETC_PORT2_REF_CLK.outFreq, value: 50 MHz} +- {id: NETC_PORT3_REF_CLK.outFreq, value: 50 MHz} +- {id: NETC_PORT4_REF_CLK.outFreq, value: 50 MHz} +- {id: OSC_24M.outFreq, value: 24 MHz} +- {id: OSC_32K.outFreq, value: 32.768 kHz} +- {id: OSC_RC_24M.outFreq, value: 24 MHz} +- {id: OSC_RC_400M.outFreq, value: 400 MHz} +- {id: SEMC_CLK_ROOT.outFreq, value: 200 MHz} +- {id: SWO_TRACE_CLK_ROOT.outFreq, value: 80 MHz} +- {id: SYS_PLL1_CLK.outFreq, value: 1 GHz} +- {id: SYS_PLL1_DIV2_CLK.outFreq, value: 500 MHz} +- {id: SYS_PLL1_DIV5_CLK.outFreq, value: 200 MHz} +- {id: SYS_PLL2_CLK.outFreq, value: 528 MHz} +- {id: SYS_PLL2_PFD0_CLK.outFreq, value: 352 MHz} +- {id: SYS_PLL2_PFD1_CLK.outFreq, value: 594 MHz} +- {id: SYS_PLL2_PFD2_CLK.outFreq, value: 396 MHz} +- {id: SYS_PLL2_PFD3_CLK.outFreq, value: 297 MHz} +- {id: SYS_PLL3_CLK.outFreq, value: 480 MHz} +- {id: SYS_PLL3_DIV2_CLK.outFreq, value: 240 MHz} +- {id: SYS_PLL3_PFD0_CLK.outFreq, value: 4320/11 MHz} +- {id: SYS_PLL3_PFD1_CLK.outFreq, value: 2880/11 MHz} +- {id: SYS_PLL3_PFD2_CLK.outFreq, value: 4320/11 MHz} +- {id: SYS_PLL3_PFD3_CLK.outFreq, value: 480 MHz} +- {id: TMR_1588_CLK_ROOT.outFreq, value: 240 MHz} +- {id: TMR_1588_REF_CLK.outFreq, value: 240 MHz} +- {id: TPM2_CLK_ROOT.outFreq, value: 80 MHz} +- {id: TPM4_CLK_ROOT.outFreq, value: 80 MHz} +- {id: TPM5_CLK_ROOT.outFreq, value: 80 MHz} +- {id: TPM6_CLK_ROOT.outFreq, value: 80 MHz} +- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz} +- {id: USDHC2_CLK_ROOT.outFreq, value: 396 MHz} +- {id: WAKEUP_AXI_CLK_ROOT.outFreq, value: 240 MHz} +settings: +- {id: AONDomainVoltage, value: OD} +- {id: CoreClockRootsInitializationConfig, value: selectedCore} +- {id: SOCDomainVoltage, value: OD} +- {id: ANADIG_OSC_OSC_24M_CTRL_LP_EN_CFG, value: Low} +- {id: ANADIG_OSC_OSC_24M_CTRL_OSC_EN_CFG, value: Enabled} +- {id: ANADIG_PLL.ARM_PLL_POST_DIV.scale, value: '2', locked: true} +- {id: ANADIG_PLL.ARM_PLL_PREDIV.scale, value: '1', locked: true} +- {id: ANADIG_PLL.ARM_PLL_VDIV.scale, value: '132', locked: true} +- {id: ANADIG_PLL.PLL_AUDIO_BYPASS.sel, value: ANADIG_OSC.OSC_24M} +- {id: ANADIG_PLL.SYS_PLL2.denom, value: '268435455', locked: true} +- {id: ANADIG_PLL.SYS_PLL2.div, value: '22'} +- {id: ANADIG_PLL.SYS_PLL2.num, value: '0'} +- {id: ANADIG_PLL.SYS_PLL2_SS_DIV.scale, value: '268435455'} +- {id: ANADIG_PLL.SYS_PLL3_PFD0_DIV.scale, value: '22'} +- {id: ANADIG_PLL.SYS_PLL3_PFD1_DIV.scale, value: '33', locked: true} +- {id: ANADIG_PLL.SYS_PLL3_PFD1_MUL.scale, value: '18', locked: true} +- {id: ANADIG_PLL.SYS_PLL3_PFD2_DIV.scale, value: '22', locked: true} +- {id: ANADIG_PLL.SYS_PLL3_PFD2_MUL.scale, value: '18', locked: true} +- {id: ANADIG_PLL.SYS_PLL3_PFD3_DIV.scale, value: '18'} +- {id: ANADIG_PLL_ARM_PLL_CTRL_POWERUP_CFG, value: Enabled} +- {id: ANADIG_PLL_PLL_AUDIO_CTRL_GATE_CFG, value: Disabled} +- {id: ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CFG, value: Enabled} +- {id: ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CFG, value: Enabled} +- {id: ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_CFG, value: Enabled} +- {id: ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_CFG, value: Enabled} +- {id: ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CFG, value: Enabled} +- {id: CCM.CLOCK_ROOT0.DIV.scale, value: '1', locked: true} +- {id: CCM.CLOCK_ROOT0.MUX.sel, value: ANADIG_PLL.ARM_PLL_CLK} +- {id: CCM.CLOCK_ROOT1.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT1.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} +- {id: CCM.CLOCK_ROOT10.DIV.scale, value: '5', locked: true} +- {id: CCM.CLOCK_ROOT10.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT11.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT11.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT12.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT12.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT13.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT13.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT14.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT14.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT15.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT15.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT16.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT16.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT17.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT17.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT18.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT18.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT19.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT2.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT2.MUX.sel, value: ANADIG_OSC.OSC_RC_400M} +- {id: CCM.CLOCK_ROOT20.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT21.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT21.MUX.sel, value: ANADIG_PLL.SYS_PLL3_PFD0_CLK} +- {id: CCM.CLOCK_ROOT22.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT22.MUX.sel, value: ANADIG_PLL.SYS_PLL3_PFD2_CLK} +- {id: CCM.CLOCK_ROOT23.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT23.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK} +- {id: CCM.CLOCK_ROOT24.DIV.scale, value: '6', locked: true} +- {id: CCM.CLOCK_ROOT24.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} +- {id: CCM.CLOCK_ROOT25.DIV.scale, value: '6', locked: true} +- {id: CCM.CLOCK_ROOT25.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} +- {id: CCM.CLOCK_ROOT26.DIV.scale, value: '6', locked: true} +- {id: CCM.CLOCK_ROOT26.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} +- {id: CCM.CLOCK_ROOT27.DIV.scale, value: '10', locked: true} +- {id: CCM.CLOCK_ROOT27.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT28.DIV.scale, value: '10', locked: true} +- {id: CCM.CLOCK_ROOT28.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT29.DIV.scale, value: '10', locked: true} +- {id: CCM.CLOCK_ROOT29.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT3.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT3.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK} +- {id: CCM.CLOCK_ROOT30.DIV.scale, value: '10', locked: true} +- {id: CCM.CLOCK_ROOT30.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT31.DIV.scale, value: '10', locked: true} +- {id: CCM.CLOCK_ROOT31.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT32.DIV.scale, value: '10', locked: true} +- {id: CCM.CLOCK_ROOT32.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT33.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT33.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT34.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT34.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT35.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT35.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT36.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT36.MUX.sel, value: ANADIG_PLL.SYS_PLL3_PFD1_CLK} +- {id: CCM.CLOCK_ROOT37.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT37.MUX.sel, value: ANADIG_PLL.SYS_PLL3_PFD1_CLK} +- {id: CCM.CLOCK_ROOT38.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT38.MUX.sel, value: ANADIG_PLL.SYS_PLL3_PFD1_CLK} +- {id: CCM.CLOCK_ROOT39.DIV.scale, value: '10', locked: true} +- {id: CCM.CLOCK_ROOT39.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT4.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT4.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK} +- {id: CCM.CLOCK_ROOT40.DIV.scale, value: '10', locked: true} +- {id: CCM.CLOCK_ROOT40.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT41.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT41.MUX.sel, value: ANADIG_PLL.SYS_PLL2_PFD2_CLK} +- {id: CCM.CLOCK_ROOT42.MUX.sel, value: ANADIG_PLL.SYS_PLL2_PFD2_CLK} +- {id: CCM.CLOCK_ROOT43.DIV.scale, value: '5', locked: true} +- {id: CCM.CLOCK_ROOT43.MUX.sel, value: ANADIG_PLL.SYS_PLL1_CLK} +- {id: CCM.CLOCK_ROOT44.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT44.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT45.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT45.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT46.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT46.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} +- {id: CCM.CLOCK_ROOT47.DIV.scale, value: '5', locked: true} +- {id: CCM.CLOCK_ROOT47.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV2_CLK} +- {id: CCM.CLOCK_ROOT48.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT48.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV2_CLK} +- {id: CCM.CLOCK_ROOT49.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT49.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} +- {id: CCM.CLOCK_ROOT5.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT5.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} +- {id: CCM.CLOCK_ROOT50.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT50.MUX.sel, value: ANADIG_PLL.SYS_PLL3_PFD3_CLK} +- {id: CCM.CLOCK_ROOT51.DIV.scale, value: '10', locked: true} +- {id: CCM.CLOCK_ROOT51.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV2_CLK} +- {id: CCM.CLOCK_ROOT52.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT52.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV2_CLK} +- {id: CCM.CLOCK_ROOT53.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT53.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV2_CLK} +- {id: CCM.CLOCK_ROOT54.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT54.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV2_CLK} +- {id: CCM.CLOCK_ROOT55.DIV.scale, value: '10', locked: true} +- {id: CCM.CLOCK_ROOT55.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV2_CLK} +- {id: CCM.CLOCK_ROOT6.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT6.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT65.DIV.scale, value: '12', locked: true} +- {id: CCM.CLOCK_ROOT65.MUX.sel, value: ANADIG_PLL.PLL_AUDIO_CLK} +- {id: CCM.CLOCK_ROOT66.DIV.scale, value: '12', locked: true} +- {id: CCM.CLOCK_ROOT66.MUX.sel, value: ANADIG_PLL.PLL_AUDIO_CLK} +- {id: CCM.CLOCK_ROOT67.DIV.scale, value: '12', locked: true} +- {id: CCM.CLOCK_ROOT67.MUX.sel, value: ANADIG_PLL.PLL_AUDIO_CLK} +- {id: CCM.CLOCK_ROOT68.DIV.scale, value: '12', locked: true} +- {id: CCM.CLOCK_ROOT68.MUX.sel, value: ANADIG_PLL.PLL_AUDIO_CLK} +- {id: CCM.CLOCK_ROOT69.DIV.scale, value: '12', locked: true} +- {id: CCM.CLOCK_ROOT69.MUX.sel, value: ANADIG_PLL.PLL_AUDIO_CLK} +- {id: CCM.CLOCK_ROOT7.DIV.scale, value: '240', locked: true} +- {id: CCM.CLOCK_ROOT7.MUX.sel, value: ANADIG_OSC.OSC_24M} +- {id: CCM.CLOCK_ROOT70.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT70.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} +- {id: CCM.CLOCK_ROOT71.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT71.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT72.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT72.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT73.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT73.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV5_CLK} +- {id: CCM.CLOCK_ROOT8.DIV.scale, value: '240', locked: true} +- {id: CCM.CLOCK_ROOT8.MUX.sel, value: ANADIG_OSC.OSC_24M} +- {id: CCM.CLOCK_ROOT9.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT9.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +sources: +- {id: BLK_CTRL_WAKEUPMIX.ECAT_PORT0_REF_CLK_EXT.outFreq, value: 50 MHz, enabled: true} +- {id: BLK_CTRL_WAKEUPMIX.ECAT_PORT1_REF_CLK_EXT.outFreq, value: 50 MHz, enabled: true} +- {id: BLK_CTRL_WAKEUPMIX.NETC_PORT0_REF_CLK_EXT.outFreq, value: 50 MHz, enabled: true} +- {id: BLK_CTRL_WAKEUPMIX.NETC_PORT1_REF_CLK_EXT.outFreq, value: 50 MHz, enabled: true} +- {id: BLK_CTRL_WAKEUPMIX.NETC_PORT2_REF_CLK_EXT.outFreq, value: 50 MHz, enabled: true} +- {id: BLK_CTRL_WAKEUPMIX.NETC_PORT3_REF_CLK_EXT.outFreq, value: 50 MHz, enabled: true} +- {id: BLK_CTRL_WAKEUPMIX.NETC_PORT4_REF_CLK_EXT.outFreq, value: 50 MHz, enabled: true} +- {id: BLK_CTRL_WAKEUPMIX.SAI1_MCLK_EXT.outFreq, value: 100 kHz} +- {id: BLK_CTRL_WAKEUPMIX.SAI2_MCLK_EXT.outFreq, value: 200 kHz} +- {id: BLK_CTRL_WAKEUPMIX.SAI3_MCLK_EXT.outFreq, value: 300 kHz} +- {id: BLK_CTRL_WAKEUPMIX.SAI4_MCLK_EXT.outFreq, value: 400 kHz} +- {id: BLK_CTRL_WAKEUPMIX.SPDIF_CLK_EXT.outFreq, value: 2 MHz} +- {id: BLK_CTRL_WAKEUPMIX.TMR_1588_REF_CLK_EXT.outFreq, value: 50 MHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/******************************************************************************* + * Variables for BOARD_BootClockRUN configuration + ******************************************************************************/ +const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = { + .postDivider = kCLOCK_PllPostDiv2, /* Post divider, 0 - DIV by 2, 1 - DIV by 4, 2 - DIV by 8, 3 - DIV by 1 */ + .loopDivider = 132, /* PLL Loop divider, Fout = Fin * ( loopDivider / ( 2 * postDivider ) ) */ + }; + +const clock_sys_pll1_config_t sysPll1Config_BOARD_BootClockRUN = { + .pllDiv2En = 1, /* Enable Sys Pll1 divide-by-2 clock or not */ + .pllDiv5En = 1, /* Enable Sys Pll1 divide-by-5 clock or not */ + .ss = NULL, /* Spread spectrum parameter */ + .ssEnable = false, /* Enable spread spectrum or not */ + }; + +const clock_sys_pll2_config_t sysPll2Config_BOARD_BootClockRUN = { + .mfd = 268435455, /* Denominator of spread spectrum */ + .ss = NULL, /* Spread spectrum parameter */ + .ssEnable = false, /* Enable spread spectrum or not */ + }; + +/******************************************************************************* + * Code for BOARD_BootClockRUN configuration + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + clock_root_config_t rootCfg = {0}; + + /* Init OSC RC 400M */ + CLOCK_OSC_EnableOscRc400M(); + + /* Switch both core to OscRC400M first */ +#if (__CORTEX_M == 7) + rootCfg.mux = kCLOCK_M7_ClockRoot_MuxOscRc400M; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg); +#endif + +#if (__CORTEX_M == 33) + /* When FlexSPI2 is used, CM33 root clock must be higher than 1/4 + of FlexSPI2 root clock, so set it to OSC RC 400M(but not OSC RC 24M) + firstly as common setting */ + rootCfg.mux = kCLOCK_M33_ClockRoot_MuxOscRc400M; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_M33, &rootCfg); +#endif + +#if (__CORTEX_M == 7) + DCDC_SetVoltage(kDCDC_CORE0, kDCDC_1P0Target1P1V); + DCDC_SetVoltage(kDCDC_CORE1, kDCDC_1P0Target1P1V); + /* FBB need to be enabled in OverDrive(OD) mode */ + PMU_EnableFBB(ANADIG_PMU, true); +#endif + + /* Config CLK_1M */ + CLOCK_OSC_Set1MHzOutputBehavior(kCLOCK_1MHzOutEnableFreeRunning1Mhz); + + /* Init OSC RC 24M */ + CLOCK_OSC_EnableOscRc24M(true); + + /* Config OSC 24M */ + ANADIG_OSC->OSC_24M_CTRL |= ANADIG_OSC_OSC_24M_CTRL_OSC_EN(1) | ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN(0) | ANADIG_OSC_OSC_24M_CTRL_LP_EN(1) | ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE(0); + /* Wait for 24M OSC to be stable. */ + while (ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK != + (ANADIG_OSC->OSC_24M_CTRL & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK)) + { + } + + /* Call function BOARD_FlexspiClockSafeConfig() to move FlexSPI clock to a stable clock source to avoid + instruction/data fetch issue when updating PLL if XIP(execute code on FLEXSPI memory). */ + BOARD_FlexspiClockSafeConfig(); + + /* Init Arm Pll. */ + CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN); + + /* Init Sys Pll1. */ + CLOCK_InitSysPll1(&sysPll1Config_BOARD_BootClockRUN); + +#ifndef USE_SDRAM + /* Init Sys Pll2. */ + CLOCK_InitSysPll2(&sysPll2Config_BOARD_BootClockRUN); + /* Init System Pll2 pfd0. */ + CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd0, 27); +#endif + /* Init System Pll2 pfd1. */ + CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd1, 16); + /* Init System Pll2 pfd2. */ + CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd2, 24); + /* Init System Pll2 pfd3. */ + CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd3, 32); + +#ifndef USE_HYPERRAM + /* Init Sys Pll3. */ + CLOCK_InitSysPll3(); +#endif + /* Init System Pll3 pfd0. */ + CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd0, 22); + /* Init System Pll3 pfd1. */ + CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd1, 33); +#ifndef USE_HYPERRAM + /* Init System Pll3 pfd2. */ + CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd2, 22); +#endif + /* Init System Pll3 pfd3. */ + CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd3, 18); + + /* Bypass Audio Pll. */ + CLOCK_SetPllBypass(kCLOCK_PllAudio, true); + /* DeInit Audio Pll. */ + CLOCK_DeinitAudioPll(); + + /* Module clock root configurations. */ + /* Configure M7 using ARM_PLL_CLK */ +#if (__CORTEX_M == 7) + rootCfg.mux = kCLOCK_M7_ClockRoot_MuxArmPllOut; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg); +#endif + + /* Configure M33 using SYS_PLL3_CLK */ +#if (__CORTEX_M == 33) + rootCfg.mux = kCLOCK_M33_ClockRoot_MuxSysPll3Out; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_M33, &rootCfg); +#endif + + /* Configure EDGELOCK using OSC_RC_400M */ + EdgeLock_SetClock(kCLOCK_EDGELOCK_ClockRoot_MuxOscRc400M, 2); + + /* Configure BUS_AON using SYS_PLL2_CLK */ + rootCfg.mux = kCLOCK_BUS_AON_ClockRoot_MuxSysPll2Out; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Bus_Aon, &rootCfg); + + /* Configure BUS_WAKEUP using SYS_PLL2_CLK */ + rootCfg.mux = kCLOCK_BUS_WAKEUP_ClockRoot_MuxSysPll2Out; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Bus_Wakeup, &rootCfg); + + /* Configure WAKEUP_AXI using SYS_PLL3_CLK */ + rootCfg.mux = kCLOCK_WAKEUP_AXI_ClockRoot_MuxSysPll3Out; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Wakeup_Axi, &rootCfg); + + /* Configure SWO_TRACE using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_SWO_TRACE_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Swo_Trace, &rootCfg); + + /* Configure M33_SYSTICK using OSC_24M */ +#if (__CORTEX_M == 33) + rootCfg.mux = kCLOCK_M33_SYSTICK_ClockRoot_MuxOsc24MOut; + rootCfg.div = 240; + CLOCK_SetRootClock(kCLOCK_Root_M33_Systick, &rootCfg); +#endif + + /* Configure M7_SYSTICK using OSC_24M */ +#if (__CORTEX_M == 7) + rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOsc24MOut; + rootCfg.div = 240; + CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg); +#endif + + /* Configure FLEXIO1 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_FLEXIO1_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Flexio1, &rootCfg); + + /* Configure FLEXIO2 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_FLEXIO2_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 5; + CLOCK_SetRootClock(kCLOCK_Root_Flexio2, &rootCfg); + + /* Configure LPIT3 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPIT3_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Lpit3, &rootCfg); + + /* Configure LPTIMER1 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPTIMER1_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Lptimer1, &rootCfg); + + /* Configure LPTIMER2 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPTIMER2_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Lptimer2, &rootCfg); + + /* Configure LPTIMER3 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPTIMER3_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Lptimer3, &rootCfg); + + /* Configure TPM2 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_TPM2_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Tpm2, &rootCfg); + + /* Configure TPM4 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_TPM4_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Tpm4, &rootCfg); + + /* Configure TPM5 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_TPM5_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Tpm5, &rootCfg); + + /* Configure TPM6 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_TPM6_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Tpm6, &rootCfg); + + /* Configure GPT1 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_GPT1_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Gpt1, &rootCfg); + + /* Configure GPT2 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_GPT2_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Gpt2, &rootCfg); + + /* Configure FLEXSPI1 using SYS_PLL3_PFD0_CLK */ + BOARD_SetFlexspiClock(FLEXSPI1, kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll3Pfd0, 3U); + + /* Configure FLEXSPI2 using SYS_PLL3_PFD2_CLK */ +#ifndef USE_HYPERRAM + BOARD_SetFlexspiClock(FLEXSPI2, kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll3Pfd2, 2U); +#endif + + /* Configure FLEXSPI_SLV using SYS_PLL2_CLK */ + rootCfg.mux = kCLOCK_FLEXSPI_SLV_ClockRoot_MuxSysPll2Out; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Flexspi_Slv, &rootCfg); + + /* Configure CAN1 using SYS_PLL3_CLK */ + rootCfg.mux = kCLOCK_CAN1_ClockRoot_MuxSysPll3Out; + rootCfg.div = 6; + CLOCK_SetRootClock(kCLOCK_Root_Can1, &rootCfg); + + /* Configure CAN2 using SYS_PLL3_CLK */ + rootCfg.mux = kCLOCK_CAN2_ClockRoot_MuxSysPll3Out; + rootCfg.div = 6; + CLOCK_SetRootClock(kCLOCK_Root_Can2, &rootCfg); + + /* Configure CAN3 using SYS_PLL3_CLK */ + rootCfg.mux = kCLOCK_CAN3_ClockRoot_MuxSysPll3Out; + rootCfg.div = 6; + CLOCK_SetRootClock(kCLOCK_Root_Can3, &rootCfg); + + /* Configure LPUART0102 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPUART0102_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart0102, &rootCfg); + + /* Configure LPUART0304 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPUART0304_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart0304, &rootCfg); + + /* Configure LPUART0506 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPUART0506_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart0506, &rootCfg); + + /* Configure LPUART0708 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPUART0708_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart0708, &rootCfg); + + /* Configure LPUART0910 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPUART0910_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart0910, &rootCfg); + + /* Configure LPUART1112 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPUART1112_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart1112, &rootCfg); + + /* Configure LPI2C0102 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPI2C0102_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Lpi2c0102, &rootCfg); + + /* Configure LPI2C0304 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPI2C0304_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Lpi2c0304, &rootCfg); + + /* Configure LPI2C0506 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPI2C0506_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Lpi2c0506, &rootCfg); + + /* Configure LPSPI0102 using SYS_PLL3_PFD1_CLK */ + rootCfg.mux = kCLOCK_LPSPI0102_ClockRoot_MuxSysPll3Pfd1; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Lpspi0102, &rootCfg); + + /* Configure LPSPI0304 using SYS_PLL3_PFD1_CLK */ + rootCfg.mux = kCLOCK_LPSPI0304_ClockRoot_MuxSysPll3Pfd1; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Lpspi0304, &rootCfg); + + /* Configure LPSPI0506 using SYS_PLL3_PFD1_CLK */ + rootCfg.mux = kCLOCK_LPSPI0506_ClockRoot_MuxSysPll3Pfd1; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Lpspi0506, &rootCfg); + + /* Configure I3C1 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_I3C1_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_I3c1, &rootCfg); + + /* Configure I3C2 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_I3C2_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_I3c2, &rootCfg); + + /* Configure USDHC1 using SYS_PLL2_PFD2_CLK */ + rootCfg.mux = kCLOCK_USDHC1_ClockRoot_MuxSysPll2Pfd2; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Usdhc1, &rootCfg); + + /* Configure USDHC2 using SYS_PLL2_PFD2_CLK */ + rootCfg.mux = kCLOCK_USDHC2_ClockRoot_MuxSysPll2Pfd2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Usdhc2, &rootCfg); + + /* Configure SEMC using SYS_PLL1_CLK */ +#ifndef USE_SDRAM + rootCfg.mux = kCLOCK_SEMC_ClockRoot_MuxSysPll1Out; + rootCfg.div = 5; + CLOCK_SetRootClock(kCLOCK_Root_Semc, &rootCfg); +#endif + + /* Configure ADC1 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_ADC1_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Adc1, &rootCfg); + + /* Configure ADC2 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_ADC2_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Adc2, &rootCfg); + + /* Configure ACMP using SYS_PLL3_CLK */ + rootCfg.mux = kCLOCK_ACMP_ClockRoot_MuxSysPll3Out; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Acmp, &rootCfg); + + /* Configure ECAT using SYS_PLL1_DIV2_CLK */ + rootCfg.mux = kCLOCK_ECAT_ClockRoot_MuxSysPll1Div2; + rootCfg.div = 5; + CLOCK_SetRootClock(kCLOCK_Root_Ecat, &rootCfg); + + /* Configure ENET using SYS_PLL1_DIV2_CLK */ + rootCfg.mux = kCLOCK_ENET_ClockRoot_MuxSysPll1Div2; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Enet, &rootCfg); + + /* Configure TMR_1588 using SYS_PLL3_CLK */ + rootCfg.mux = kCLOCK_TMR_1588_ClockRoot_MuxSysPll3Out; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Tmr_1588, &rootCfg); + + /* Configure NETC using SYS_PLL3_PFD3_CLK */ + rootCfg.mux = kCLOCK_NETC_ClockRoot_MuxSysPll3Pfd3; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Netc, &rootCfg); + + /* Configure MAC0 using SYS_PLL1_DIV2_CLK */ + rootCfg.mux = kCLOCK_MAC0_ClockRoot_MuxSysPll1Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_Mac0, &rootCfg); + + /* Configure MAC1 using SYS_PLL1_DIV2_CLK */ + rootCfg.mux = kCLOCK_MAC1_ClockRoot_MuxSysPll1Div2; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Mac1, &rootCfg); + + /* Configure MAC2 using SYS_PLL1_DIV2_CLK */ + rootCfg.mux = kCLOCK_MAC2_ClockRoot_MuxSysPll1Div2; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Mac2, &rootCfg); + + /* Configure MAC3 using SYS_PLL1_DIV2_CLK */ + rootCfg.mux = kCLOCK_MAC3_ClockRoot_MuxSysPll1Div2; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Mac3, &rootCfg); + + /* Configure MAC4 using SYS_PLL1_DIV2_CLK */ + rootCfg.mux = kCLOCK_MAC4_ClockRoot_MuxSysPll1Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_Mac4, &rootCfg); + + /* Configure SAI1 using PLL_AUDIO_CLK */ + rootCfg.mux = kCLOCK_SAI1_ClockRoot_MuxAudioPllOut; + rootCfg.div = 12; + CLOCK_SetRootClock(kCLOCK_Root_Sai1, &rootCfg); + + /* Configure SAI2 using PLL_AUDIO_CLK */ + rootCfg.mux = kCLOCK_SAI2_ClockRoot_MuxAudioPllOut; + rootCfg.div = 12; + CLOCK_SetRootClock(kCLOCK_Root_Sai2, &rootCfg); + + /* Configure SAI3 using PLL_AUDIO_CLK */ + rootCfg.mux = kCLOCK_SAI3_ClockRoot_MuxAudioPllOut; + rootCfg.div = 12; + CLOCK_SetRootClock(kCLOCK_Root_Sai3, &rootCfg); + + /* Configure SAI4 using PLL_AUDIO_CLK */ + rootCfg.mux = kCLOCK_SAI4_ClockRoot_MuxAudioPllOut; + rootCfg.div = 12; + CLOCK_SetRootClock(kCLOCK_Root_Sai4, &rootCfg); + + /* Configure SPDIF using PLL_AUDIO_CLK */ + rootCfg.mux = kCLOCK_SPDIF_ClockRoot_MuxAudioPllOut; + rootCfg.div = 12; + CLOCK_SetRootClock(kCLOCK_Root_Spdif, &rootCfg); + + /* Configure ASRC using SYS_PLL3_CLK */ + rootCfg.mux = kCLOCK_ASRC_ClockRoot_MuxSysPll3Out; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Asrc, &rootCfg); + + /* Configure MIC using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_MIC_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Mic, &rootCfg); + + /* Configure CKO1 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_CKO1_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Cko1, &rootCfg); + + /* Configure CKO2 using SYS_PLL1_DIV5_CLK */ + rootCfg.mux = kCLOCK_CKO2_ClockRoot_MuxSysPll1Div5; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Cko2, &rootCfg); + + /* Set SAI MCLK clock source. */ + BLK_CTRL_SetSaiMClkClockSource(BLK_CTRL_WAKEUPMIX, kBLK_CTRL_SAI2MClk3Sel, 0); + BLK_CTRL_SetSaiMClkClockSource(BLK_CTRL_WAKEUPMIX, kBLK_CTRL_SAI3MClk3Sel, 0); + BLK_CTRL_SetSaiMClkClockSource(BLK_CTRL_WAKEUPMIX, kBLK_CTRL_SAI4MClk1Sel, 0); + BLK_CTRL_SetSaiMClkClockSource(BLK_CTRL_WAKEUPMIX, kBLK_CTRL_SAI4MClk2Sel, 0); + BLK_CTRL_SetSaiMClkClockSource(BLK_CTRL_WAKEUPMIX, kBLK_CTRL_SAI4MClk3Sel, 0); + + /* Set ECAT PORT Ref clock source. */ + BLK_CTRL_WAKEUPMIX->ECAT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_RMII_REF_CLK_DIR0_MASK; + BLK_CTRL_WAKEUPMIX->ECAT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_RMII_REF_CLK_DIR1_MASK; + + /* Set NETC PORT Ref clock source. */ + BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT0_RMII_REF_CLK_DIR_MASK; + BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT1_RMII_REF_CLK_DIR_MASK; + BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT2_RMII_REF_CLK_DIR_MASK; + BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT3_RMII_REF_CLK_DIR_MASK; + BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT4_RMII_REF_CLK_DIR_MASK; + + /* Set TMR 1588 Ref clock source. */ + BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG |= BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_TMR_EXT_CLK_SEL_MASK; + +#if (__CORTEX_M == 7) + SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M7); +#else + SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M33); +#endif +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/clock_config.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/clock_config.h new file mode 100644 index 00000000000..80bb10092db --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/clock_config.h @@ -0,0 +1,183 @@ +/* + * Copyright 2022 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ + +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if __CORTEX_M == 7 + #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 792000000UL /*!< CM7 Core clock frequency: 792000000Hz */ +#else + #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 240000000UL /*!< CM33 Core clock frequency: 240000000Hz */ +#endif + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKRUN_ACMP_CLK_ROOT 240000000UL /* Clock consumers of ACMP_CLK_ROOT output : CMP1, CMP2, CMP3, CMP4 */ +#define BOARD_BOOTCLOCKRUN_ADC1_CLK_ROOT 80000000UL /* Clock consumers of ADC1_CLK_ROOT output : ADC1 */ +#define BOARD_BOOTCLOCKRUN_ADC2_CLK_ROOT 80000000UL /* Clock consumers of ADC2_CLK_ROOT output : ADC2 */ +#define BOARD_BOOTCLOCKRUN_ARM_PLL_CLK 792000000UL /* Clock consumers of ARM_PLL_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_ASRC_CLK_ROOT 240000000UL /* Clock consumers of ASRC_CLK_ROOT output : ASRC */ +#define BOARD_BOOTCLOCKRUN_BUS_AON_CLK_ROOT 132000000UL /* Clock consumers of BUS_AON_CLK_ROOT output : CAN1, CAN3, I3C1, IOMUXC_AON, LPI2C1, LPI2C2, LPIT1, LPSPI1, LPSPI2, LPTMR1, LPUART1, LPUART2, LPUART7, LPUART8, MU2_MUA, MU2_MUB, RTWDOG1, RTWDOG2, RTWDOG3, RTWDOG4, RTWDOG5, SAI1, SEMA1, TPM1, TPM2, TSTMR1_TSTMRA */ +#define BOARD_BOOTCLOCKRUN_BUS_WAKEUP_CLK_ROOT 132000000UL /* Clock consumers of BUS_WAKEUP_CLK_ROOT output : ADC1, ADC2, AOI1, AOI2, AOI3, AOI4, CAN2, CMP1, CMP2, CMP3, CMP4, DAC, EQDC1, EQDC2, EQDC3, EQDC4, EWM, FLEXIO1, FLEXIO2, I3C2, IOMUXC, KPP, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPIT2, LPIT3, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPTMR2, LPTMR3, LPUART10, LPUART11, LPUART12, LPUART3, LPUART4, LPUART5, LPUART6, LPUART9, MECC1, MECC2, MU1_MUA, MU1_MUB, PDM, PWM1, PWM2, PWM3, PWM4, RGPIO2, RGPIO3, RGPIO4, RGPIO5, RGPIO6, RTWDOG3, SAI2, SAI3, SAI4, SEMA2, SINC1, SINC2, SINC3, SPDIF, TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8, TPM3, TPM4, TPM5, TPM6, TSTMR2_TSTMRA, USBPHY1, USBPHY2, USDHC1, USDHC2, XBAR1, XBAR2, XBAR3 */ +#define BOARD_BOOTCLOCKRUN_CAN1_CLK_ROOT 80000000UL /* Clock consumers of CAN1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_CAN2_CLK_ROOT 80000000UL /* Clock consumers of CAN2_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_CAN3_CLK_ROOT 80000000UL /* Clock consumers of CAN3_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_CCM_CKO1_CLK_ROOT 80000000UL /* Clock consumers of CCM_CKO1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_CCM_CKO2_CLK_ROOT 50000000UL /* Clock consumers of CCM_CKO2_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, GPT1, GPT2 */ +#define BOARD_BOOTCLOCKRUN_ECAT_CLK_ROOT 100000000UL /* Clock consumers of ECAT_CLK_ROOT output : ECAT */ +#define BOARD_BOOTCLOCKRUN_ECAT_PORT0_REF_CLK 50000000UL /* Clock consumers of ECAT_PORT0_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_ECAT_PORT1_REF_CLK 50000000UL /* Clock consumers of ECAT_PORT1_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_EDGELOCK_CLK_ROOT 200000000UL /* Clock consumers of EDGELOCK_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_ENET_REFCLK_ROOT 125000000UL /* Clock consumers of ENET_REFCLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 120000000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */ +#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 48000000UL /* Clock consumers of FLEXIO2_CLK_ROOT output : FLEXIO2 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI1_CLK_ROOT 130909090UL /* Clock consumers of FLEXSPI1_CLK_ROOT output : FLEXSPI1 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 196363636UL /* Clock consumers of FLEXSPI2_CLK_ROOT output : FLEXSPI2 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI_SLV_CLK_ROOT 132000000UL /* Clock consumers of FLEXSPI_SLV_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_GPT1_CLK_ROOT 240000000UL /* Clock consumers of GPT1_CLK_ROOT output : GPT1 */ +#define BOARD_BOOTCLOCKRUN_GPT2_CLK_ROOT 240000000UL /* Clock consumers of GPT2_CLK_ROOT output : GPT2 */ +#define BOARD_BOOTCLOCKRUN_I3C1_CLK_ROOT 24000000UL /* Clock consumers of I3C1_CLK_ROOT output : I3C1 */ +#define BOARD_BOOTCLOCKRUN_I3C2_CLK_ROOT 24000000UL /* Clock consumers of I3C2_CLK_ROOT output : I3C2 */ +#define BOARD_BOOTCLOCKRUN_LPI2C0102_CLK_ROOT 60000000UL /* Clock consumers of LPI2C0102_CLK_ROOT output : LPI2C1, LPI2C2 */ +#define BOARD_BOOTCLOCKRUN_LPI2C0304_CLK_ROOT 60000000UL /* Clock consumers of LPI2C0304_CLK_ROOT output : LPI2C3, LPI2C4 */ +#define BOARD_BOOTCLOCKRUN_LPI2C0506_CLK_ROOT 60000000UL /* Clock consumers of LPI2C0506_CLK_ROOT output : LPI2C5, LPI2C6 */ +#define BOARD_BOOTCLOCKRUN_LPIT3_CLK_ROOT 80000000UL /* Clock consumers of LPIT3_CLK_ROOT output : LPIT3 */ +#define BOARD_BOOTCLOCKRUN_LPSPI0102_CLK_ROOT 130909090UL /* Clock consumers of LPSPI0102_CLK_ROOT output : LPSPI1, LPSPI2 */ +#define BOARD_BOOTCLOCKRUN_LPSPI0304_CLK_ROOT 130909090UL /* Clock consumers of LPSPI0304_CLK_ROOT output : LPSPI3, LPSPI4 */ +#define BOARD_BOOTCLOCKRUN_LPSPI0506_CLK_ROOT 130909090UL /* Clock consumers of LPSPI0506_CLK_ROOT output : LPSPI5, LPSPI6 */ +#define BOARD_BOOTCLOCKRUN_LPTMR1_CLK_ROOT 80000000UL /* Clock consumers of LPTMR1_CLK_ROOT output : LPTMR1 */ +#define BOARD_BOOTCLOCKRUN_LPTMR2_CLK_ROOT 80000000UL /* Clock consumers of LPTMR2_CLK_ROOT output : LPTMR2 */ +#define BOARD_BOOTCLOCKRUN_LPTMR3_CLK_ROOT 80000000UL /* Clock consumers of LPTMR3_CLK_ROOT output : LPTMR3 */ +#define BOARD_BOOTCLOCKRUN_LPUART0102_CLK_ROOT 24000000UL /* Clock consumers of LPUART0102_CLK_ROOT output : LPUART1, LPUART2 */ +#define BOARD_BOOTCLOCKRUN_LPUART0304_CLK_ROOT 24000000UL /* Clock consumers of LPUART0304_CLK_ROOT output : LPUART3, LPUART4 */ +#define BOARD_BOOTCLOCKRUN_LPUART0506_CLK_ROOT 24000000UL /* Clock consumers of LPUART0506_CLK_ROOT output : LPUART5, LPUART6 */ +#define BOARD_BOOTCLOCKRUN_LPUART0708_CLK_ROOT 24000000UL /* Clock consumers of LPUART0708_CLK_ROOT output : LPUART7, LPUART8 */ +#define BOARD_BOOTCLOCKRUN_LPUART0910_CLK_ROOT 24000000UL /* Clock consumers of LPUART0910_CLK_ROOT output : LPUART10, LPUART9 */ +#define BOARD_BOOTCLOCKRUN_LPUART1112_CLK_ROOT 24000000UL /* Clock consumers of LPUART1112_CLK_ROOT output : LPUART11, LPUART12 */ +#define BOARD_BOOTCLOCKRUN_M33_CLK_ROOT 240000000UL /* Clock consumers of M33_CLK_ROOT output : ARM, DMA3, FLEXSPI2, RGPIO1, SysTick0 */ +#define BOARD_BOOTCLOCKRUN_M33_SYSTICK_CLK_ROOT 100000UL /* Clock consumers of M33_SYSTICK_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_M7_CLK_ROOT 792000000UL /* Clock consumers of M7_CLK_ROOT output : ARM, SysTick1 */ +#define BOARD_BOOTCLOCKRUN_M7_SYSTICK_CLK_ROOT 100000UL /* Clock consumers of M7_SYSTICK_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_MAC0_CLK_ROOT 50000000UL /* Clock consumers of MAC0_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_MAC1_CLK_ROOT 125000000UL /* Clock consumers of MAC1_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_MAC2_CLK_ROOT 125000000UL /* Clock consumers of MAC2_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_MAC3_CLK_ROOT 125000000UL /* Clock consumers of MAC3_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_MAC4_CLK_ROOT 50000000UL /* Clock consumers of MAC4_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_MIC_CLK_ROOT 80000000UL /* Clock consumers of MIC_CLK_ROOT output : PDM, SPDIF */ +#define BOARD_BOOTCLOCKRUN_NETC_CLK_ROOT 240000000UL /* Clock consumers of NETC_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_NETC_PORT0_REF_CLK 50000000UL /* Clock consumers of NETC_PORT0_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_NETC_PORT1_REF_CLK 50000000UL /* Clock consumers of NETC_PORT1_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_NETC_PORT2_REF_CLK 50000000UL /* Clock consumers of NETC_PORT2_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_NETC_PORT3_REF_CLK 50000000UL /* Clock consumers of NETC_PORT3_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_NETC_PORT4_REF_CLK 50000000UL /* Clock consumers of NETC_PORT4_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_OSC_24M 24000000UL /* Clock consumers of OSC_24M output : CAN1, CAN2, CAN3, DAC, GPT1, GPT2, SPDIF, TMPSNS */ +#define BOARD_BOOTCLOCKRUN_OSC_32K 32768UL /* Clock consumers of OSC_32K output : CMP1, CMP2, CMP3, CMP4, EWM, GPT1, GPT2, KPP, LPTMR1, LPTMR2, LPTMR3, RTWDOG1, RTWDOG2, RTWDOG3, RTWDOG4, RTWDOG5, USBPHY1, USBPHY2, USB_OTG1, USB_OTG2, USDHC1, USDHC2 */ +#define BOARD_BOOTCLOCKRUN_OSC_RC_24M 24000000UL /* Clock consumers of OSC_RC_24M output : DCDC, EWM, RTWDOG1, RTWDOG2, RTWDOG3, RTWDOG4, RTWDOG5 */ +#define BOARD_BOOTCLOCKRUN_OSC_RC_400M 400000000UL /* Clock consumers of OSC_RC_400M output : N/A */ +#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_CLK 0UL /* Clock consumers of PLL_AUDIO_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_MODULATION 0UL /* Clock consumers of PLL_AUDIO_SS_MODULATION output : N/A */ +#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_RANGE 0UL /* Clock consumers of PLL_AUDIO_SS_RANGE output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 0UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 0UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 0UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 0UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 0UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 0UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 0UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 0UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 0UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI4_CLK_ROOT 0UL /* Clock consumers of SAI4_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI4_MCLK1 0UL /* Clock consumers of SAI4_MCLK1 output : SAI4 */ +#define BOARD_BOOTCLOCKRUN_SAI4_MCLK2 0UL /* Clock consumers of SAI4_MCLK2 output : SAI4 */ +#define BOARD_BOOTCLOCKRUN_SAI4_MCLK3 0UL /* Clock consumers of SAI4_MCLK3 output : SAI4 */ +#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 200000000UL /* Clock consumers of SEMC_CLK_ROOT output : SEMC */ +#define BOARD_BOOTCLOCKRUN_SPDIF_CLK_ROOT 0UL /* Clock consumers of SPDIF_CLK_ROOT output : SPDIF */ +#define BOARD_BOOTCLOCKRUN_SPDIF_EXTCLK_OUT 0UL /* Clock consumers of SPDIF_EXTCLK_OUT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SWO_TRACE_CLK_ROOT 80000000UL /* Clock consumers of SWO_TRACE_CLK_ROOT output : ARM */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_CLK 1000000000UL /* Clock consumers of SYS_PLL1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV2_CLK 500000000UL /* Clock consumers of SYS_PLL1_DIV2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV5_CLK 200000000UL /* Clock consumers of SYS_PLL1_DIV5_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_MODULATION 0UL /* Clock consumers of SYS_PLL1_SS_MODULATION output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_RANGE 0UL /* Clock consumers of SYS_PLL1_SS_RANGE output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_CLK 528000000UL /* Clock consumers of SYS_PLL2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD0_CLK 352000000UL /* Clock consumers of SYS_PLL2_PFD0_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD1_CLK 594000000UL /* Clock consumers of SYS_PLL2_PFD1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD2_CLK 396000000UL /* Clock consumers of SYS_PLL2_PFD2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD3_CLK 297000000UL /* Clock consumers of SYS_PLL2_PFD3_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_MODULATION 0UL /* Clock consumers of SYS_PLL2_SS_MODULATION output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_RANGE 0UL /* Clock consumers of SYS_PLL2_SS_RANGE output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_CLK 480000000UL /* Clock consumers of SYS_PLL3_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_DIV2_CLK 240000000UL /* Clock consumers of SYS_PLL3_DIV2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD0_CLK 392727272UL /* Clock consumers of SYS_PLL3_PFD0_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD1_CLK 261818181UL /* Clock consumers of SYS_PLL3_PFD1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD2_CLK 392727272UL /* Clock consumers of SYS_PLL3_PFD2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD3_CLK 480000000UL /* Clock consumers of SYS_PLL3_PFD3_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_TMR_1588_CLK_ROOT 240000000UL /* Clock consumers of TMR_1588_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_TMR_1588_REF_CLK 240000000UL /* Clock consumers of TMR_1588_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_TPM2_CLK_ROOT 80000000UL /* Clock consumers of TPM2_CLK_ROOT output : TPM2 */ +#define BOARD_BOOTCLOCKRUN_TPM4_CLK_ROOT 80000000UL /* Clock consumers of TPM4_CLK_ROOT output : TPM4 */ +#define BOARD_BOOTCLOCKRUN_TPM5_CLK_ROOT 80000000UL /* Clock consumers of TPM5_CLK_ROOT output : TPM5 */ +#define BOARD_BOOTCLOCKRUN_TPM6_CLK_ROOT 80000000UL /* Clock consumers of TPM6_CLK_ROOT output : TPM6 */ +#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */ +#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 396000000UL /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */ +#define BOARD_BOOTCLOCKRUN_WAKEUP_AXI_CLK_ROOT 240000000UL /* Clock consumers of WAKEUP_AXI_CLK_ROOT output : DMA4, FLEXSPI1, IEE, MECC1, MECC2, USB_OTG1, USB_OTG2, USDHC1, USDHC2 */ + + +/******************************************************************************* + * API for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ + diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/pin_mux.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/pin_mux.c new file mode 100644 index 00000000000..ff39c120f77 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/pin_mux.c @@ -0,0 +1,82 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v15.0 +processor: MIMXRT1189xxxxx +package_id: MIMXRT1189CVM8C +mcu_data: ksdk2_0 +processor_version: 0.15.9 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) { + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm33, enableClock: 'true'} +- pin_list: + - {pin_num: A5, peripheral: LPUART1, signal: RXD, pin_signal: GPIO_AON_09, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper, open_drain: Disable, drive_strength: High, + slew_rate: Slow} + - {pin_num: B1, peripheral: LPUART1, signal: TXD, pin_signal: GPIO_AON_08, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper, open_drain: Disable, drive_strength: High, + slew_rate: Slow} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins, assigned for the Cortex-M33 core. + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc2); /* Turn on LPCG: LPCG is ON. */ + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AON_08_LPUART1_TX, /* GPIO_AON_08 is configured as LPUART1_TX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AON_09_LPUART1_RX, /* GPIO_AON_09 is configured as LPUART1_RX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AON_08_LPUART1_TX, /* GPIO_AON_08 PAD functional properties : */ + 0x02U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: high driver + Pull / Keep Select Field: Pull Disable, Highz + Pull Up / Down Config. Field: Weak pull down + Open Drain Field: Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AON_09_LPUART1_RX, /* GPIO_AON_09 PAD functional properties : */ + 0x02U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: high driver + Pull / Keep Select Field: Pull Disable, Highz + Pull Up / Down Config. Field: Weak pull down + Open Drain Field: Disabled */ +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/pin_mux.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/pin_mux.h new file mode 100644 index 00000000000..cc4b717363b --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/pin_mux.h @@ -0,0 +1,51 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /* Function assigned for the Cortex-M33 */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/SConscript b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/SConscript new file mode 100644 index 00000000000..c97de856d48 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/SConscript @@ -0,0 +1,21 @@ +from building import * + +cwd = GetCurrentDir() + +# add the general drivers. +src = Split(""" +board.c +dcd.c +MCUX_Config/clock_config.c +MCUX_Config/pin_mux.c +""") + +if GetDepend(['BSP_USING_VGLITE']): + src += ['display_support.c', 'vglite_support.c', 'vglite_window.c'] + +CPPPATH = [cwd,cwd + '/MCUX_Config',cwd + '/ports'] +CPPDEFINES = ['CPU_MIMXRT1189CVM8C_cm7', 'MIMXRT1189_cm7_SERIES', 'XIP_BOOT_HEADER_ENABLE=0', 'XIP_BOOT_HEADER_DCD_ENABLE=0', 'FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1','XIP_EXTERNAL_FLASH=0','ARM_MATH_CM7','USE_SDRAM'] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) + +Return('group') diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/board.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/board.c new file mode 100644 index 00000000000..dc70b82e874 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/board.c @@ -0,0 +1,331 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2009-01-05 Bernard first implementation + * 2022-08-15 xjy198903 add sdram pin config + * 2022-08-17 xjy198903 add rgmii pins + * 2022-09-01 xjy198903 add can pins + * 2022-09-07 xjy198903 add sdio pins + * 2022-09-14 xjy198903 add flexspi pins + */ + +#include +#include +#include "board.h" +#include "pin_mux.h" +#include "fsl_iomuxc.h" +#include "fsl_rgpio.h" +#include "fsl_cache.h" + +#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority + 4 bits for subpriority */ +#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority + 3 bits for subpriority */ +#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority + 2 bits for subpriority */ +#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority + 1 bits for subpriority */ +#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority + 0 bits for subpriority */ + +/* MPU configuration. */ +void BOARD_ConfigMPU(void) +{ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Image$$RW_m_ncache$$Base[]; + /* RW_m_ncache_aux is a auxiliary region which is used to get the whole size of noncache section */ + extern uint32_t Image$$RW_m_ncache_aux$$Base[]; + uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base; + uint32_t nonCacheSize = ((uint32_t)Image$$RW_m_ncache_aux$$Base) - nonCacheStart; +#elif defined(__MCUXPRESSO) + extern uint32_t __base_NCACHE_REGION; + extern uint32_t __top_NCACHE_REGION; + uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION); + uint32_t nonCacheSize = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart; +#elif defined(__ICCARM__) || defined(__GNUC__) + extern uint32_t __NCACHE_REGION_START[]; + extern uint32_t __NCACHE_REGION_SIZE[]; + uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START; + uint32_t nonCacheSize = (uint32_t)__NCACHE_REGION_SIZE; +#endif +#if defined(__USE_SHMEM) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Image$$RPMSG_SH_MEM$$Base[]; + /* RPMSG_SH_MEM_aux is a auxiliary region which is used to get the whole size of RPMSG_SH_MEM section */ + extern uint32_t Image$$RPMSG_SH_MEM_aux$$Base[]; + uint32_t rpmsgShmemStart = (uint32_t)Image$$RPMSG_SH_MEM$$Base; + uint32_t rpmsgShmemSize = ((uint32_t)Image$$RPMSG_SH_MEM_aux$$Base) - rpmsgShmemStart; +#elif defined(__MCUXPRESSO) + extern uint32_t __base_SHMEM_REGION; + extern uint32_t __top_SHMEM_REGION; + uint32_t rpmsgShmemStart = (uint32_t)(&__base_SHMEM_REGION); + uint32_t rpmsgShmemSize = (uint32_t)(&__top_SHMEM_REGION) - rpmsgShmemStart; +#elif defined(__ICCARM__) || defined(__GNUC__) + extern uint32_t __RPMSG_SH_MEM_START[]; + extern uint32_t __RPMSG_SH_MEM_SIZE[]; + uint32_t rpmsgShmemStart = (uint32_t)__RPMSG_SH_MEM_START; + uint32_t rpmsgShmemSize = (uint32_t)__RPMSG_SH_MEM_SIZE; +#endif +#endif + volatile uint32_t i; + + /* Disable I cache and D cache */ + L1CACHE_DisableICache(); + L1CACHE_DisableDCache(); + + /* Disable MPU */ + ARM_MPU_Disable(); + + /* clang-format off */ + + /* MPU configure: + * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) + * API in mpu_armv7.h. + * param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches disabled. + * param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. + * Use MACROS defined in mpu_armv7.h: + * ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO + * + * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes. + * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribute Shareability Cache + * 0 x 0 0 Strongly Ordered shareable + * 0 x 0 1 Device shareable + * 0 0 1 0 Normal not shareable Outer and inner write + * through no write allocate + * 0 0 1 1 Normal not shareable Outer and inner write + * back no write allocate + * 0 1 1 0 Normal shareable Outer and inner write + * through no write allocate + * 0 1 1 1 Normal shareable Outer and inner write + * back no write allocate + * 1 0 0 0 Normal not shareable outer and inner + * noncache + * 1 1 0 0 Normal shareable outer and inner + * noncache + * 1 0 1 1 Normal not shareable outer and inner write + * back write/read acllocate + * 1 1 1 1 Normal shareable outer and inner write + * back write/read acllocate + * 2 x 0 0 Device not shareable + * Above are normal use settings, if your want to see more details or want to config different inner/outer cache + * policy, please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide + * + * param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled. + * param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in mpu_armv7.h. + */ + + /* clang-format on */ + + /* + * Add default region to deny access to whole address space to workaround speculative prefetch. + * Refer to Arm errata 1013783-B for more details. + */ + + /* Region 0 setting: Instruction access disabled, No data access permission. */ + MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U); + MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_NONE, 0, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB); + + /* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */ + MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB); + + /* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */ + MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2GB); + + /* Region 4 setting: Memory with Normal type, not shareable, outer/inner write back */ /*ITCM*/ + MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB); + + /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */ /*DTCM*/ + MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB); + + MPU->RBAR = ARM_MPU_RBAR(6, 0x20480000U); +#if defined(CACHE_MODE_WRITE_THROUGH) + /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write through */ /*OCRAM1*/ + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_512KB); +#else + /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */ /*OCRAM1*/ + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512KB); +#endif + + MPU->RBAR = ARM_MPU_RBAR(7, 0x20500000U); +#if defined(CACHE_MODE_WRITE_THROUGH) + /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write through */ /*OCRAM2*/ + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_256KB); +#else + /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */ /*OCRAM2*/ + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB); +#endif + +#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1) + /* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back. */ /*FSPI1*/ + MPU->RBAR = ARM_MPU_RBAR(8, 0x28000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_16MB); +#endif + +#if defined(USE_HYPERRAM) + MPU->RBAR = ARM_MPU_RBAR(9, 0x04000000U); +#if defined(CACHE_MODE_WRITE_THROUGH) + /* Region 9 setting: Memory with Normal type, not shareable, outer/inner write through. */ /*FSPI2*/ + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_8MB); +#else + /* Region 9 setting: Memory with Normal type, not shareable, outer/inner write back. */ /*FSPI2*/ + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_8MB); +#endif +#endif + +#if defined(USE_SDRAM) + MPU->RBAR = ARM_MPU_RBAR(10, 0x80000000U); +#if defined(CACHE_MODE_WRITE_THROUGH) + /* Region 10 setting: Memory with Normal type, not shareable, outer/inner write through */ + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_64MB); +#else + /* Region 10 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64MB); +#endif +#endif + + i = 0; + while ((nonCacheSize >> i) > 0x1U) + { + i++; + } + + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert(!(nonCacheStart % nonCacheSize)); + assert(nonCacheSize == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Region 11 setting: Memory with Normal type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(11, nonCacheStart); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1); + } + +#if defined(__USE_SHMEM) + i = 0; + while ((rpmsgShmemSize >> i) > 0x1U) + { + i++; + } + + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert(!(rpmsgShmemStart % rpmsgShmemSize)); + assert(rpmsgShmemSize == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Region 12 setting: Memory with Normal type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(12, rpmsgShmemStart); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1); + } +#endif + + /* Enable MPU */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk); + + /* Enable I cache and D cache */ + L1CACHE_EnableDCache(); + L1CACHE_EnableICache(); +} + +/* This is the timer interrupt service routine. */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + + + +void imxrt_uart_pins_init(void) +{ +#ifdef BSP_USING_LPUART1 + + CLOCK_EnableClock(kCLOCK_Iomuxc2); /* Turn on LPCG: LPCG is ON. */ + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AON_08_LPUART1_TX, /* GPIO_AON_08 is configured as LPUART1_TX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AON_09_LPUART1_RX, /* GPIO_AON_09 is configured as LPUART1_RX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AON_08_LPUART1_TX, /* GPIO_AON_08 PAD functional properties : */ + 0x02U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: high driver + Pull / Keep Select Field: Pull Disable, Highz + Pull Up / Down Config. Field: Weak pull down + Open Drain Field: Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AON_09_LPUART1_RX, /* GPIO_AON_09 PAD functional properties : */ + 0x02U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: high driver + Pull / Keep Select Field: Pull Disable, Highz + Pull Up / Down Config. Field: Weak pull down + Open Drain Field: Disabled */ + +#endif +} + +void rt_hw_board_init() +{ + BOARD_ConfigMPU(); + BOARD_InitPins(); + BOARD_BootClockRUN(); + + NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); + +#ifdef BSP_USING_LPUART + imxrt_uart_pins_init(); +#endif + +#ifdef BSP_USING_SDRAM + imxrt_sdram_pins_init(); +#endif + +#ifdef RT_USING_HEAP + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif + +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + +#ifdef BSP_USING_SDIO + imxrt_SDcard_pins_init(); +#endif + +#ifdef BSP_USING_ETH + imxrt_eth_pins_init(); +#endif + +#ifdef BSP_USING_CAN + imxrt_can_pins_init(); +#endif + +#ifdef BSP_USING_FLEXSPI + imxrt_flexspi_pins_init(); +#endif + + +} + diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/board.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/board.h new file mode 100644 index 00000000000..88a683de836 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/board.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2009-09-22 Bernard add board.h to this bsp + */ + +// <<< Use Configuration Wizard in Context Menu >>> +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include "clock_config.h" +#include "pin_mux.h" +#include "fsl_common.h" +#include "fsl_rgpio.h" +#include "fsl_clock.h" + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern int Image$$RTT_HEAP$$ZI$$Base; +extern int Image$$RTT_HEAP$$ZI$$Limit; +#define HEAP_BEGIN (&Image$$RTT_HEAP$$ZI$$Base) +#define HEAP_END (&Image$$RTT_HEAP$$ZI$$Limit) +s's +#elif __ICCARM__ +#pragma section="HEAP" +#define HEAP_BEGIN 0x20530000//(__segment_end("HEAP")) +extern void __RTT_HEAP_END; +#define HEAP_END (&__RTT_HEAP_END) + +#else +extern int heap_start; +extern int heap_end; +#define HEAP_BEGIN (&heap_start) +#define HEAP_END (&heap_end) +#endif + +#define HEAP_SIZE ((uint32_t)HEAP_END - (uint32_t)HEAP_BEGIN) + +/*! @brief The board flash size */ +#define BOARD_FLASH_SIZE (0x1000000U) + +void rt_hw_board_init(void); + +#endif + diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/dcd.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/dcd.c new file mode 100644 index 00000000000..b7e60a294bf --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/dcd.c @@ -0,0 +1,401 @@ +/* + * Copyright 2020-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#include "dcd.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_board" +#endif + +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.dcd_data"), used)) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.dcd_data" +#endif + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: DCDx v3.0 +processor: MIMXRT1176xxxxx +package_id: MIMXRT1176DVMAA +mcu_data: ksdk2_0 +processor_version: 12.0.0 +output_format: c_array + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */ +const uint8_t dcd_data[] = { + /* HEADER */ + /* Tag */ + 0xD2, + /* Image Length */ + 0x05, 0x10, + /* Version */ + 0x41, + + /* COMMANDS */ + + /* group: 'Imported Commands' */ + /* #1.1-139, command header bytes for merged 'Write - value' command */ + 0xCC, 0x04, 0x5C, 0x04, + /* #1.1, command: write_value, address: CCM_CLOCK_ROOT4_CONTROL, value: 0x602, size: 4 */ + 0x40, 0xCC, 0x02, 0x00, 0x00, 0x00, 0x06, 0x02, + /* #1.2, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_00, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x10, 0x00, 0x00, 0x00, 0x00, + /* #1.3, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_01, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, + /* #1.4, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_02, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00, + /* #1.5, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_03, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00, + /* #1.6, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_04, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00, + /* #1.7, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_05, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00, + /* #1.8, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_06, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00, + /* #1.9, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_07, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00, + /* #1.10, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_08, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00, + /* #1.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_09, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00, + /* #1.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_10, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00, + /* #1.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_11, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00, + /* #1.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_12, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00, + /* #1.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_13, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00, + /* #1.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_14, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00, + /* #1.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_15, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00, + /* #1.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_16, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00, + /* #1.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_17, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00, + /* #1.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_18, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00, + /* #1.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_19, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00, + /* #1.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_20, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00, + /* #1.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_21, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00, + /* #1.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_22, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00, + /* #1.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_23, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00, + /* #1.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_24, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00, + /* #1.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_25, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00, + /* #1.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_26, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00, + /* #1.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_27, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00, + /* #1.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_28, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, + /* #1.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_29, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00, + /* #1.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_30, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00, + /* #1.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_31, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00, + /* #1.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_32, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00, + /* #1.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_33, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00, + /* #1.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_34, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00, + /* #1.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_35, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00, + /* #1.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_36, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00, + /* #1.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_37, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00, + /* #1.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_38, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00, + /* #1.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_39, value: 0x10, size: 4 */ + 0x40, 0x0E, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x10, + /* #1.42, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_40, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x00, + /* #1.43, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_41, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0xB4, 0x00, 0x00, 0x00, 0x00, + /* #1.44, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_00, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0xB8, 0x00, 0x00, 0x00, 0x00, + /* #1.45, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_01, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0xBC, 0x00, 0x00, 0x00, 0x00, + /* #1.46, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_02, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0xC0, 0x00, 0x00, 0x00, 0x00, + /* #1.47, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_03, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0xC4, 0x00, 0x00, 0x00, 0x00, + /* #1.48, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_04, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0xC8, 0x00, 0x00, 0x00, 0x00, + /* #1.49, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_05, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0xCC, 0x00, 0x00, 0x00, 0x00, + /* #1.50, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_06, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0xD0, 0x00, 0x00, 0x00, 0x00, + /* #1.51, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_07, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0xD4, 0x00, 0x00, 0x00, 0x00, + /* #1.52, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_08, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0xD8, 0x00, 0x00, 0x00, 0x00, + /* #1.53, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_09, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0xDC, 0x00, 0x00, 0x00, 0x00, + /* #1.54, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_10, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0xE0, 0x00, 0x00, 0x00, 0x00, + /* #1.55, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_11, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0xE4, 0x00, 0x00, 0x00, 0x00, + /* #1.56, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_12, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0xE8, 0x00, 0x00, 0x00, 0x00, + /* #1.57, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_13, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0xEC, 0x00, 0x00, 0x00, 0x00, + /* #1.58, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_14, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0xF0, 0x00, 0x00, 0x00, 0x00, + /* #1.59, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_15, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0xF4, 0x00, 0x00, 0x00, 0x00, + /* #1.60, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_16, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0xF8, 0x00, 0x00, 0x00, 0x00, + /* #1.61, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_17, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x80, 0xFC, 0x00, 0x00, 0x00, 0x00, + /* #1.62, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_18, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, + /* #1.63, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_19, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x81, 0x04, 0x00, 0x00, 0x00, 0x00, + /* #1.64, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_20, value: 0x00, size: 4 */ + 0x40, 0x0E, 0x81, 0x08, 0x00, 0x00, 0x00, 0x00, + /* #1.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_00, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0x54, 0x00, 0x00, 0x00, 0x08, + /* #1.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_01, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0x58, 0x00, 0x00, 0x00, 0x08, + /* #1.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_02, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0x5C, 0x00, 0x00, 0x00, 0x08, + /* #1.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_03, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0x60, 0x00, 0x00, 0x00, 0x08, + /* #1.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_04, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0x64, 0x00, 0x00, 0x00, 0x08, + /* #1.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_05, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0x68, 0x00, 0x00, 0x00, 0x08, + /* #1.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_06, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0x6C, 0x00, 0x00, 0x00, 0x08, + /* #1.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_07, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0x70, 0x00, 0x00, 0x00, 0x08, + /* #1.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_08, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0x74, 0x00, 0x00, 0x00, 0x08, + /* #1.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_09, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0x78, 0x00, 0x00, 0x00, 0x08, + /* #1.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_10, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0x7C, 0x00, 0x00, 0x00, 0x08, + /* #1.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_11, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0x80, 0x00, 0x00, 0x00, 0x08, + /* #1.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_12, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0x84, 0x00, 0x00, 0x00, 0x08, + /* #1.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_13, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0x88, 0x00, 0x00, 0x00, 0x08, + /* #1.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_14, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0x8C, 0x00, 0x00, 0x00, 0x08, + /* #1.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_15, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0x90, 0x00, 0x00, 0x00, 0x08, + /* #1.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_16, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0x94, 0x00, 0x00, 0x00, 0x08, + /* #1.82, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_17, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0x98, 0x00, 0x00, 0x00, 0x08, + /* #1.83, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_18, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0x9C, 0x00, 0x00, 0x00, 0x08, + /* #1.84, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_19, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0xA0, 0x00, 0x00, 0x00, 0x08, + /* #1.85, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_20, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0xA4, 0x00, 0x00, 0x00, 0x08, + /* #1.86, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_21, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0xA8, 0x00, 0x00, 0x00, 0x08, + /* #1.87, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_22, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0xAC, 0x00, 0x00, 0x00, 0x08, + /* #1.88, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_23, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0xB0, 0x00, 0x00, 0x00, 0x08, + /* #1.89, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_24, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0xB4, 0x00, 0x00, 0x00, 0x08, + /* #1.90, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_25, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0xB8, 0x00, 0x00, 0x00, 0x08, + /* #1.91, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_26, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0xBC, 0x00, 0x00, 0x00, 0x08, + /* #1.92, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_27, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0xC0, 0x00, 0x00, 0x00, 0x08, + /* #1.93, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_28, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0xC4, 0x00, 0x00, 0x00, 0x08, + /* #1.94, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_29, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0xC8, 0x00, 0x00, 0x00, 0x08, + /* #1.95, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_30, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0xCC, 0x00, 0x00, 0x00, 0x08, + /* #1.96, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_31, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0xD0, 0x00, 0x00, 0x00, 0x08, + /* #1.97, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_32, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0xD4, 0x00, 0x00, 0x00, 0x08, + /* #1.98, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_33, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0xD8, 0x00, 0x00, 0x00, 0x08, + /* #1.99, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_34, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0xDC, 0x00, 0x00, 0x00, 0x08, + /* #1.100, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_35, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0xE0, 0x00, 0x00, 0x00, 0x08, + /* #1.101, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_36, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0xE4, 0x00, 0x00, 0x00, 0x08, + /* #1.102, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_37, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0xE8, 0x00, 0x00, 0x00, 0x08, + /* #1.103, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_38, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0xEC, 0x00, 0x00, 0x00, 0x08, + /* #1.104, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_39, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0xF0, 0x00, 0x00, 0x00, 0x08, + /* #1.105, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_40, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0xF4, 0x00, 0x00, 0x00, 0x08, + /* #1.106, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_41, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0xF8, 0x00, 0x00, 0x00, 0x08, + /* #1.107, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_00, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x82, 0xFC, 0x00, 0x00, 0x00, 0x08, + /* #1.108, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_01, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x83, 0x00, 0x00, 0x00, 0x00, 0x08, + /* #1.109, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_02, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x83, 0x04, 0x00, 0x00, 0x00, 0x08, + /* #1.110, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_03, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x83, 0x08, 0x00, 0x00, 0x00, 0x08, + /* #1.111, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_04, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x83, 0x0C, 0x00, 0x00, 0x00, 0x08, + /* #1.112, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_05, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x83, 0x10, 0x00, 0x00, 0x00, 0x08, + /* #1.113, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_06, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x83, 0x14, 0x00, 0x00, 0x00, 0x08, + /* #1.114, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_07, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x83, 0x18, 0x00, 0x00, 0x00, 0x08, + /* #1.115, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_08, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x83, 0x1C, 0x00, 0x00, 0x00, 0x08, + /* #1.116, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_09, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x83, 0x20, 0x00, 0x00, 0x00, 0x08, + /* #1.117, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_10, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x83, 0x24, 0x00, 0x00, 0x00, 0x08, + /* #1.118, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_11, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x83, 0x28, 0x00, 0x00, 0x00, 0x08, + /* #1.119, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_12, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x83, 0x2C, 0x00, 0x00, 0x00, 0x08, + /* #1.120, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_13, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x83, 0x30, 0x00, 0x00, 0x00, 0x08, + /* #1.121, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_14, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x83, 0x34, 0x00, 0x00, 0x00, 0x08, + /* #1.122, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_15, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x83, 0x38, 0x00, 0x00, 0x00, 0x08, + /* #1.123, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_16, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x83, 0x3C, 0x00, 0x00, 0x00, 0x08, + /* #1.124, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_02, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x84, 0x00, 0x00, 0x00, 0x00, 0x08, + /* #1.125, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_03, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x84, 0x04, 0x00, 0x00, 0x00, 0x08, + /* #1.126, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_04, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x84, 0x08, 0x00, 0x00, 0x00, 0x08, + /* #1.127, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_05, value: 0x08, size: 4 */ + 0x40, 0x0E, 0x84, 0x0C, 0x00, 0x00, 0x00, 0x08, + /* #1.128, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4 */ + 0x40, 0x0D, 0x40, 0x00, 0x10, 0x00, 0x00, 0x04, + /* #1.129, command: write_value, address: SEMC_BMCR0, value: 0x81, size: 4 */ + 0x40, 0x0D, 0x40, 0x08, 0x00, 0x00, 0x00, 0x81, + /* #1.130, command: write_value, address: SEMC_BMCR1, value: 0x81, size: 4 */ + 0x40, 0x0D, 0x40, 0x0C, 0x00, 0x00, 0x00, 0x81, + /* #1.131, command: write_value, address: SEMC_BR0, value: 0x8000001D, size: 4 */ + 0x40, 0x0D, 0x40, 0x10, 0x80, 0x00, 0x00, 0x1D, + /* #1.132, command: write_value, address: SEMC_SDRAMCR0, value: 0xF32, size: 4 */ + 0x40, 0x0D, 0x40, 0x40, 0x00, 0x00, 0x0F, 0x32, + /* #1.133, command: write_value, address: SEMC_SDRAMCR1, value: 0x772A22, size: 4 */ + 0x40, 0x0D, 0x40, 0x44, 0x00, 0x77, 0x2A, 0x22, + /* #1.134, command: write_value, address: SEMC_SDRAMCR2, value: 0x10A0D, size: 4 */ + 0x40, 0x0D, 0x40, 0x48, 0x00, 0x01, 0x0A, 0x0D, + /* #1.135, command: write_value, address: SEMC_SDRAMCR3, value: 0x21210408, size: 4 */ + 0x40, 0x0D, 0x40, 0x4C, 0x21, 0x21, 0x04, 0x08, + /* #1.136, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x0D, 0x40, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #1.137, command: write_value, address: SEMC_IPCR1, value: 0x02, size: 4 */ + 0x40, 0x0D, 0x40, 0x94, 0x00, 0x00, 0x00, 0x02, + /* #1.138, command: write_value, address: SEMC_IPCR2, value: 0x00, size: 4 */ + 0x40, 0x0D, 0x40, 0x98, 0x00, 0x00, 0x00, 0x00, + /* #1.139, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4 */ + 0x40, 0x0D, 0x40, 0x9C, 0xA5, 0x5A, 0x00, 0x0F, + /* #2, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #3, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #4, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #5, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #6, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #7.1-2, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x14, 0x04, + /* #7.1, command: write_value, address: SEMC_INTR, value: 0x03, size: 4 */ + 0x40, 0x0D, 0x40, 0x3C, 0x00, 0x00, 0x00, 0x03, + /* #7.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ + 0x40, 0x0D, 0x40, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, + /* #8, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #9, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #10, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #11, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #12, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #13.1-2, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x14, 0x04, + /* #13.1, command: write_value, address: SEMC_INTR, value: 0x03, size: 4 */ + 0x40, 0x0D, 0x40, 0x3C, 0x00, 0x00, 0x00, 0x03, + /* #13.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ + 0x40, 0x0D, 0x40, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, + /* #14, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #15, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #16, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #17, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #18, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #19.1-3, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x1C, 0x04, + /* #19.1, command: write_value, address: SEMC_INTR, value: 0x03, size: 4 */ + 0x40, 0x0D, 0x40, 0x3C, 0x00, 0x00, 0x00, 0x03, + /* #19.2, command: write_value, address: SEMC_IPTXDAT, value: 0x33, size: 4 */ + 0x40, 0x0D, 0x40, 0xA0, 0x00, 0x00, 0x00, 0x33, + /* #19.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4 */ + 0x40, 0x0D, 0x40, 0x9C, 0xA5, 0x5A, 0x00, 0x0A, + /* #20, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #21, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #22, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #23, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #24, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #25, command: write_value, address: SEMC_INTR, value: 0x03, size: 4 */ + 0xCC, 0x00, 0x0C, 0x04, 0x40, 0x0D, 0x40, 0x3C, 0x00, 0x00, 0x00, 0x03, + /* #26, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #27, command: write_value, address: SEMC_SDRAMCR3, value: 0x21210409, size: 4 */ + 0xCC, 0x00, 0x0C, 0x04, 0x40, 0x0D, 0x40, 0x4C, 0x21, 0x21, 0x04, 0x09}; +/* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */ + +#else +const uint8_t dcd_data[] = {0x00}; +#endif /* XIP_BOOT_HEADER_DCD_ENABLE */ +#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/dcd.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/dcd.h new file mode 100644 index 00000000000..77de9fa8b62 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/dcd.h @@ -0,0 +1,32 @@ +/* + * Copyright 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef __DCD__ +#define __DCD__ + +#include + +/*! @name Driver version */ +/*@{*/ +/*! @brief XIP_BOARD driver version 2.0.0. */ +#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/************************************* + * DCD Data + *************************************/ +#define DCD_TAG_HEADER (0xD2) +#define DCD_VERSION (0x41) +#define DCD_TAG_HEADER_SHIFT (24) +#define DCD_ARRAY_SIZE 1 + +#endif /* __DCD__ */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/display_support.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/display_support.c new file mode 100644 index 00000000000..5b574148e2b --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/display_support.c @@ -0,0 +1,468 @@ +/* + * Copyright 2019-2021, 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include +#include "display_support.h" +#include "fsl_gpio.h" +#include "fsl_mipi_dsi.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* + * The DPHY bit clock must be fast enough to send out the pixels, it should be + * larger than: + * + * (Pixel clock * bit per output pixel) / number of MIPI data lane + * + * Here the desired DPHY bit clock multiplied by ( 9 / 8 = 1.125) to ensure + * it is fast enough. + */ +#define DEMO_MIPI_DPHY_BIT_CLK_ENLARGE(origin) (((origin) / 8) * 9) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +static void BOARD_PullPanelResetPin(bool pullUp); +static void BOARD_PullPanelPowerPin(bool pullUp); +static void BOARD_InitLcdifClock(void); +static void BOARD_InitMipiDsiClock(void); +static status_t BOARD_DSI_Transfer(dsi_transfer_t *xfer); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +static uint32_t mipiDsiTxEscClkFreq_Hz; +static uint32_t mipiDsiDphyBitClkFreq_Hz; +static uint32_t mipiDsiDphyRefClkFreq_Hz; +static uint32_t mipiDsiDpiClkFreq_Hz; + +const MIPI_DSI_Type g_mipiDsi = { + .host = DSI_HOST, + .apb = DSI_HOST_APB_PKT_IF, + .dpi = DSI_HOST_DPI_INTFC, + .dphy = DSI_HOST_DPHY_INTFC, +}; + +#if defined(DISPLAY_USING_RK055AHD091) + +static mipi_dsi_device_t dsiDevice = { + .virtualChannel = 0, + .xferFunc = BOARD_DSI_Transfer, +}; + +static const rm68200_resource_t rm68200Resource = { + .dsiDevice = &dsiDevice, + .pullResetPin = BOARD_PullPanelResetPin, + .pullPowerPin = BOARD_PullPanelPowerPin, +}; + +static display_handle_t rm68200Handle = { + .resource = &rm68200Resource, + .ops = &rm68200_ops, +}; + +#elif defined(DISPLAY_USING_RK055MHD091) + +static mipi_dsi_device_t dsiDevice = { + .virtualChannel = 0, + .xferFunc = BOARD_DSI_Transfer, +}; + +static const hx8394_resource_t hx8394Resource = { + .dsiDevice = &dsiDevice, + .pullResetPin = BOARD_PullPanelResetPin, + .pullPowerPin = BOARD_PullPanelPowerPin, +}; + +static display_handle_t hx8394Handle = { + .resource = &hx8394Resource, + .ops = &hx8394_ops, +}; + +#elif defined(DISPLAY_USING_RK055IQH091) + +static mipi_dsi_device_t dsiDevice = { + .virtualChannel = 0, + .xferFunc = BOARD_DSI_Transfer, +}; + +static const rm68191_resource_t rm68191Resource = { + .dsiDevice = &dsiDevice, + .pullResetPin = BOARD_PullPanelResetPin, + .pullPowerPin = BOARD_PullPanelPowerPin, +}; + +static display_handle_t rm68191Handle = { + .resource = &rm68191Resource, + .ops = &rm68191_ops, +}; + +#endif + +#if defined(BSP_USING_LCDIFV2) +static dc_fb_lcdifv2_handle_t s_dcFbLcdifv2Handle = {0}; + +static const dc_fb_lcdifv2_config_t s_dcFbLcdifv2Config = { + .lcdifv2 = DEMO_LCDIF, + .width = LCD_MIPI_WIDTH, + .height = LCD_MIPI_HEIGHT, + .hsw = LCD_MIPI_HSW, + .hfp = LCD_MIPI_HFP, + .hbp = LCD_MIPI_HBP, + .vsw = LCD_MIPI_VSW, + .vfp = LCD_MIPI_VFP, + .vbp = LCD_MIPI_VBP, + .polarityFlags = DEMO_LCDIF_POL_FLAGS, + .lineOrder = kLCDIFV2_LineOrderRGB, +/* CM4 is domain 1, CM7 is domain 0. */ +#if (__CORTEX_M <= 4) + .domain = 1, +#else + .domain = 0, +#endif +}; + +const dc_fb_t g_dc = { + .ops = &g_dcFbOpsLcdifv2, + .prvData = &s_dcFbLcdifv2Handle, + .config = &s_dcFbLcdifv2Config, +}; + +#elif defined(BSP_USING_ELCDIF) + +dc_fb_elcdif_handle_t s_dcFbElcdifHandle = {0}; /* The handle must be initialized to 0. */ + +const dc_fb_elcdif_config_t s_dcFbElcdifConfig = { + .elcdif = DEMO_LCDIF, + .width = LCD_MIPI_WIDTH, + .height = LCD_MIPI_HEIGHT, + .hsw = LCD_MIPI_HSW, + .hfp = LCD_MIPI_HFP, + .hbp = LCD_MIPI_HBP, + .vsw = LCD_MIPI_VSW, + .vfp = LCD_MIPI_VFP, + .vbp = LCD_MIPI_VBP, + .polarityFlags = DEMO_LCDIF_POL_FLAGS, +#if (!DEMO_USE_XRGB8888) && (DEMO_USE_LUT8) + .dataBus = kELCDIF_DataBus8Bit, +#else + .dataBus = kELCDIF_DataBus24Bit, +#endif +}; + +const dc_fb_t g_dc = { + .ops = &g_dcFbOpsElcdif, + .prvData = &s_dcFbElcdifHandle, + .config = &s_dcFbElcdifConfig, +}; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void BOARD_PullPanelResetPin(bool pullUp) +{ + if (pullUp) + { + GPIO_PinWrite(BOARD_MIPI_PANEL_RST_GPIO, BOARD_MIPI_PANEL_RST_PIN, 1); + } + else + { + GPIO_PinWrite(BOARD_MIPI_PANEL_RST_GPIO, BOARD_MIPI_PANEL_RST_PIN, 0); + } +} + +static void BOARD_PullPanelPowerPin(bool pullUp) +{ + if (pullUp) + { + GPIO_PinWrite(BOARD_MIPI_PANEL_POWER_GPIO, BOARD_MIPI_PANEL_POWER_PIN, 1); + } + else + { + GPIO_PinWrite(BOARD_MIPI_PANEL_POWER_GPIO, BOARD_MIPI_PANEL_POWER_PIN, 0); + } +} + +static status_t BOARD_DSI_Transfer(dsi_transfer_t *xfer) +{ + return DSI_TransferBlocking(DEMO_LCD_MIPI, xfer); +} + +static void BOARD_InitLcdifClock(void) +{ + /* + * The pixel clock is (height + VSW + VFP + VBP) * (width + HSW + HFP + HBP) * frame rate. + * + * For 60Hz frame rate, the RK055IQH091 pixel clock should be 36MHz. + * the RK055AHD091 pixel clock should be 62MHz. + */ + const clock_root_config_t lcdifClockConfig = { + .clockOff = false, + .mux = 4, /*!< PLL_528. */ +#if (defined(DISPLAY_USING_RK055AHD091) || defined(DISPLAY_USING_RK055MHD091)) + .div = 9, +#elif defined(DISPLAY_USING_RK055IQH091) + .div = 15, +#endif + }; + +#if defined(BSP_USING_LCDIFV2) + CLOCK_SetRootClock(kCLOCK_Root_Lcdifv2, &lcdifClockConfig); + + mipiDsiDpiClkFreq_Hz = CLOCK_GetRootClockFreq(kCLOCK_Root_Lcdifv2); + +#elif defined(BSP_USING_ELCDIF) + + CLOCK_SetRootClock(kCLOCK_Root_Lcdif, &lcdifClockConfig); + + mipiDsiDpiClkFreq_Hz = CLOCK_GetRootClockFreq(kCLOCK_Root_Lcdif); +#endif +} + +static void BOARD_InitMipiDsiClock(void) +{ + uint32_t mipiDsiEscClkFreq_Hz; + + /* RxClkEsc max 60MHz, TxClkEsc 12 to 20MHz. */ + /* RxClkEsc = 528MHz / 11 = 48MHz. */ + /* TxClkEsc = 528MHz / 11 / 4 = 16MHz. */ + const clock_root_config_t mipiEscClockConfig = { + .clockOff = false, + .mux = 4, /*!< PLL_528. */ + .div = 11, + }; + + CLOCK_SetRootClock(kCLOCK_Root_Mipi_Esc, &mipiEscClockConfig); + + mipiDsiEscClkFreq_Hz = CLOCK_GetRootClockFreq(kCLOCK_Root_Mipi_Esc); + + const clock_group_config_t mipiEscClockGroupConfig = { + .clockOff = false, .resetDiv = 2, .div0 = 2, /* TX esc clock. */ + }; + + CLOCK_SetGroupConfig(kCLOCK_Group_MipiDsi, &mipiEscClockGroupConfig); + + mipiDsiTxEscClkFreq_Hz = mipiDsiEscClkFreq_Hz / 3; + + /* DPHY reference clock, use OSC 24MHz clock. */ + const clock_root_config_t mipiDphyRefClockConfig = { + .clockOff = false, + .mux = 1, /*!< OSC_24M. */ + .div = 1, + }; + + CLOCK_SetRootClock(kCLOCK_Root_Mipi_Ref, &mipiDphyRefClockConfig); + + mipiDsiDphyRefClkFreq_Hz = BOARD_XTAL0_CLK_HZ; +} + +static status_t BOARD_InitLcdPanel(void) +{ + status_t status; + + const gpio_pin_config_t pinConfig = {kGPIO_DigitalOutput, 0, kGPIO_NoIntmode}; + + const display_config_t displayConfig = { + .resolution = FSL_VIDEO_RESOLUTION(LCD_MIPI_WIDTH, LCD_MIPI_HEIGHT), + .hsw = LCD_MIPI_HSW, + .hfp = LCD_MIPI_HFP, + .hbp = LCD_MIPI_HBP, + .vsw = LCD_MIPI_VSW, + .vfp = LCD_MIPI_VFP, + .vbp = LCD_MIPI_VBP, + .controlFlags = 0, + .dsiLanes = DEMO_LCD_MIPI_LANE_NUM, + }; + + GPIO_PinInit(BOARD_MIPI_PANEL_POWER_GPIO, BOARD_MIPI_PANEL_POWER_PIN, &pinConfig); + GPIO_PinInit(BOARD_MIPI_PANEL_BL_GPIO, BOARD_MIPI_PANEL_BL_PIN, &pinConfig); + GPIO_PinInit(BOARD_MIPI_PANEL_RST_GPIO, BOARD_MIPI_PANEL_RST_PIN, &pinConfig); + +#if defined(DISPLAY_USING_RK055AHD091) + status = RM68200_Init(&rm68200Handle, &displayConfig); +#elif defined(DISPLAY_USING_RK055MHD091) + status = HX8394_Init(&hx8394Handle, &displayConfig); +#elif defined(DISPLAY_USING_RK055IQH091) + status = RM68191_Init(&rm68191Handle, &displayConfig); +#endif + + if (status == kStatus_Success) + { + GPIO_PinWrite(BOARD_MIPI_PANEL_BL_GPIO, BOARD_MIPI_PANEL_BL_PIN, 1); + } + + return status; +} + +static void BOARD_SetMipiDsiConfig(void) +{ + dsi_config_t dsiConfig; + dsi_dphy_config_t dphyConfig; + + const dsi_dpi_config_t dpiConfig = {.pixelPayloadSize = LCD_MIPI_WIDTH, + .dpiColorCoding = kDSI_Dpi24Bit, + .pixelPacket = kDSI_PixelPacket24Bit, + .videoMode = kDSI_DpiBurst, + .bllpMode = kDSI_DpiBllpLowPower, + .polarityFlags = kDSI_DpiVsyncActiveLow | kDSI_DpiHsyncActiveLow, + .hfp = LCD_MIPI_HFP, + .hbp = LCD_MIPI_HBP, + .hsw = LCD_MIPI_HSW, + .vfp = LCD_MIPI_VFP, + .vbp = LCD_MIPI_VBP, + .panelHeight = LCD_MIPI_HEIGHT, + .virtualChannel = 0}; + + /* + * dsiConfig.numLanes = 4; + * dsiConfig.enableNonContinuousHsClk = false; + * dsiConfig.autoInsertEoTp = true; + * dsiConfig.numExtraEoTp = 0; + * dsiConfig.htxTo_ByteClk = 0; + * dsiConfig.lrxHostTo_ByteClk = 0; + * dsiConfig.btaTo_ByteClk = 0; + */ + DSI_GetDefaultConfig(&dsiConfig); + dsiConfig.numLanes = DEMO_LCD_MIPI_LANE_NUM; + dsiConfig.autoInsertEoTp = true; + + /* Init the DSI module. */ + DSI_Init(DEMO_LCD_MIPI, &dsiConfig); + + /* Init DPHY. + * + * The DPHY bit clock must be fast enough to send out the pixels, it should be + * larger than: + * + * (Pixel clock * bit per output pixel) / number of MIPI data lane + * + * Here the desired DPHY bit clock multiplied by ( 9 / 8 = 1.125) to ensure + * it is fast enough. + * + * Note that the DSI output pixel is 24bit per pixel. + */ + mipiDsiDphyBitClkFreq_Hz = mipiDsiDpiClkFreq_Hz * (24 / DEMO_LCD_MIPI_LANE_NUM); + + mipiDsiDphyBitClkFreq_Hz = DEMO_MIPI_DPHY_BIT_CLK_ENLARGE(mipiDsiDphyBitClkFreq_Hz); + + DSI_GetDphyDefaultConfig(&dphyConfig, mipiDsiDphyBitClkFreq_Hz, mipiDsiTxEscClkFreq_Hz); + + mipiDsiDphyBitClkFreq_Hz = DSI_InitDphy(DEMO_LCD_MIPI, &dphyConfig, mipiDsiDphyRefClkFreq_Hz); + + /* Init DPI interface. */ + DSI_SetDpiConfig(DEMO_LCD_MIPI, &dpiConfig, DEMO_LCD_MIPI_LANE_NUM, mipiDsiDpiClkFreq_Hz, mipiDsiDphyBitClkFreq_Hz); +} + +status_t BOARD_InitDisplayInterface(void) +{ + CLOCK_EnableClock(kCLOCK_Video_Mux); + +#if defined(BSP_USING_LCDIFV2) + /* LCDIF v2 output to MIPI DSI. */ + VIDEO_MUX->VID_MUX_CTRL.SET = VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL_MASK; +#elif defined(BSP_USING_ELCDIF) + /* ELCDIF output to MIPI DSI. */ + VIDEO_MUX->VID_MUX_CTRL.CLR = VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL_MASK; +#endif + + /* 1. Power on and isolation off. */ + PGMC_BPC4->BPC_POWER_CTRL |= (PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_MASK | PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT_MASK); + + /* 2. Assert MIPI reset. */ + IOMUXC_GPR->GPR62 &= + ~(IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_MASK | IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_MASK | + IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_MASK | IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_MASK); + + /* 3. Setup clock. */ + BOARD_InitMipiDsiClock(); + + /* 4. Deassert PCLK and ESC reset. */ + IOMUXC_GPR->GPR62 |= + (IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_MASK | IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_MASK); + + /* 5. Configures peripheral. */ + BOARD_SetMipiDsiConfig(); + + /* 6. Deassert BYTE and DBI reset. */ + IOMUXC_GPR->GPR62 |= + (IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_MASK | IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_MASK); + + /* 7. Configure the panel. */ + return BOARD_InitLcdPanel(); +} + +#if defined(BSP_USING_LCDIFV2) +void LCDIFv2_IRQHandler(void) +{ + DC_FB_LCDIFV2_IRQHandler(&g_dc); +} +#elif defined(BSP_USING_ELCDIF) +void eLCDIF_IRQHandler(void) +{ + DC_FB_ELCDIF_IRQHandler(&g_dc); +} +#endif + +status_t BOARD_VerifyDisplayClockSource(void) +{ + status_t status; + uint32_t srcClkFreq; + + /* + * In this implementation, the SYSPLL2 (528M) clock is used as the source + * of LCDIFV2 pixel clock and MIPI DSI ESC clock. The OSC24M clock is used + * as the MIPI DSI DPHY PLL reference clock. This function checks the clock + * source are valid. OSC24M is always valid, so only verify the SYSPLL2. + */ + srcClkFreq = CLOCK_GetPllFreq(kCLOCK_PllSys2); + if (528 != (srcClkFreq / 1000000)) + { + status = kStatus_Fail; + } + else + { + status = kStatus_Success; + } + + return status; +} + +status_t BOARD_PrepareDisplayController(void) +{ + status_t status; + + status = BOARD_VerifyDisplayClockSource(); + + if (status != kStatus_Success) + { + return status; + } + + BOARD_InitLcdifClock(); + + status = BOARD_InitDisplayInterface(); + + if (kStatus_Success == status) + { +#if defined(BSP_USING_LCDIFV2) + NVIC_ClearPendingIRQ(LCDIFv2_IRQn); + NVIC_SetPriority(LCDIFv2_IRQn, 3); + EnableIRQ(LCDIFv2_IRQn); +#elif defined(BSP_USING_ELCDIF) + NVIC_ClearPendingIRQ(eLCDIF_IRQn); + NVIC_SetPriority(eLCDIF_IRQn, 3); + EnableIRQ(eLCDIF_IRQn); +#endif + } + + return kStatus_Success; +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/display_support.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/display_support.h new file mode 100644 index 00000000000..29c6f07a9ef --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/display_support.h @@ -0,0 +1,189 @@ +/* + * Copyright 2019-2021, 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _DISPLAY_SUPPORT_H_ +#define _DISPLAY_SUPPORT_H_ + +#include + +#include "fsl_dc_fb.h" + +#if defined(DISPLAY_USING_RK055AHD091) +#include "fsl_rm68200.h" +#elif defined(DISPLAY_USING_RK055IQH091) +#include "fsl_rm68191.h" +#elif defined(DISPLAY_USING_RK055MHD091) +#include "fsl_hx8394.h" +#else +#error "Please config lcd panel parameters." +#endif +#include "pin_mux.h" +#include "board.h" + +#if defined(BSP_USING_LCDIFV2) +#include "fsl_dc_fb_lcdifv2.h" +#elif defined(BSP_USING_ELCDIF) +#include "fsl_dc_fb_elcdif.h" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* @TEST_ANCHOR */ +#define DEMO_BUFFER_FIXED_ADDRESS 0 + +#if DEMO_BUFFER_FIXED_ADDRESS +#define DEMO_BUFFER0_ADDR 0x80000000 +#define DEMO_BUFFER1_ADDR 0x80200000 +#endif + +/* + * Use the MIPI dumb panel + */ + +/* Definitions for the frame buffer. */ +#define DEMO_BUFFER_COUNT 2 /* 2 is enough for DPI interface display. */ + +#ifndef DEMO_USE_XRGB8888 +#define DEMO_USE_XRGB8888 0 +#endif + +/* Use LCDIF LUT (or named color palette) which is 8-bit per-pixel */ +#ifndef DEMO_USE_LUT8 +#define DEMO_USE_LUT8 0 +#endif + +#if DEMO_USE_XRGB8888 +#define DEMO_BUFFER_PIXEL_FORMAT kVIDEO_PixelFormatXRGB8888 +#define DEMO_BUFFER_BYTE_PER_PIXEL 4 +#elif DEMO_USE_LUT8 +#define DEMO_BUFFER_PIXEL_FORMAT kVIDEO_PixelFormatLUT8 +#define DEMO_BUFFER_BYTE_PER_PIXEL 1 +#else +#define DEMO_BUFFER_PIXEL_FORMAT kVIDEO_PixelFormatRGB565 +#define DEMO_BUFFER_BYTE_PER_PIXEL 2 +#endif + +#if (defined(DISPLAY_USING_RK055AHD091) || defined(DISPLAY_USING_RK055MHD091)) + +#define LCD_MIPI_WIDTH (720) +#define LCD_MIPI_HEIGHT (1280) + +#elif defined(DISPLAY_USING_RK055IQH091) + +#define LCD_MIPI_WIDTH (540) +#define LCD_MIPI_HEIGHT (960) + +#endif + +#define DEMO_BUFFER_WIDTH LCD_MIPI_WIDTH +#define DEMO_BUFFER_HEIGHT LCD_MIPI_HEIGHT + +/* Where the frame buffer is shown in the screen. */ +#define DEMO_BUFFER_START_X 0U +#define DEMO_BUFFER_START_Y 0U + +#define DEMO_BUFFER_STRIDE_BYTE (DEMO_BUFFER_WIDTH * DEMO_BUFFER_BYTE_PER_PIXEL) +/* There is not frame buffer aligned requirement, consider the 64-bit AXI data + * bus width and 32-byte cache line size, the frame buffer alignment is set to + * 32 byte. + */ +#define FRAME_BUFFER_ALIGN 32 + +/* + * MIPI panel pin + */ +#define BOARD_MIPI_PANEL_RST_GPIO GPIO9 +#define BOARD_MIPI_PANEL_RST_PIN 1 +#define BOARD_MIPI_PANEL_POWER_GPIO GPIO11 +#define BOARD_MIPI_PANEL_POWER_PIN 16 +/* Back light pin. */ +#define BOARD_MIPI_PANEL_BL_GPIO GPIO9 +#define BOARD_MIPI_PANEL_BL_PIN 29 + +/* + * MIPI panel pin for RT-Thread + */ +#define GET_PIN(PORTx, PIN) (32 * (PORTx - 1) + (PIN & 31)) /* PORTx:1,2,3,4,5 */ +#define LCD_MIPI_RST_GPIO_PORT (3U) +#define LCD_MIPI_RST_GPIO_PIN (1U) +#define LCD_MIPI_RST_PIN GET_PIN(LCD_MIPI_RST_GPIO_PORT, LCD_MIPI_RST_GPIO_PIN) +/* Back light pin. */ +#define LCD_MIPI_BL_GPIO_PORT (3U) +#define LCD_MIPI_BL_GPIO_PIN (29U) +#define LCD_MIPI_BL_PIN GET_PIN(LCD_MIPI_BL_GPIO_PORT, LCD_MIPI_BL_GPIO_PIN) + +/* + * RK055AHD091 panel + */ + +#if defined(DISPLAY_USING_RK055AHD091) +#define LCD_MIPI_HSW 8 +#define LCD_MIPI_HFP 32 +#define LCD_MIPI_HBP 32 +#define LCD_MIPI_VSW 2 +#define LCD_MIPI_VFP 16 +#define LCD_MIPI_VBP 14 + +#elif defined(DISPLAY_USING_RK055IQH091) + +#define LCD_MIPI_HSW 2 +#define LCD_MIPI_HFP 32 +#define LCD_MIPI_HBP 30 +#define LCD_MIPI_VSW 2 +#define LCD_MIPI_VFP 16 +#define LCD_MIPI_VBP 14 + +#elif defined(DISPLAY_USING_RK055MHD091) + +#define LCD_MIPI_HSW 6 +#define LCD_MIPI_HFP 12 +#define LCD_MIPI_HBP 24 +#define LCD_MIPI_VSW 2 +#define LCD_MIPI_VFP 16 +#define LCD_MIPI_VBP 14 + +#endif + +#if defined(BSP_USING_LCDIFV2) + +#define DEMO_LCDIF_POL_FLAGS \ + (kLCDIFV2_DataEnableActiveHigh | kLCDIFV2_VsyncActiveLow | kLCDIFV2_HsyncActiveLow | \ + kLCDIFV2_DriveDataOnFallingClkEdge) + +#define DEMO_LCDIF LCDIFV2 + +#elif defined(BSP_USING_ELCDIF) + +#define DEMO_LCDIF_POL_FLAGS \ + (kELCDIF_DataEnableActiveHigh | kELCDIF_VsyncActiveLow | kELCDIF_HsyncActiveLow | kELCDIF_DriveDataOnFallingClkEdge) + +#define DEMO_LCDIF LCDIF + +#endif + +/* Definitions for MIPI. */ +#define DEMO_LCD_MIPI (&g_mipiDsi) +#define DEMO_LCD_MIPI_LANE_NUM 2 + +extern const dc_fb_t g_dc; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +status_t BOARD_PrepareDisplayController(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _DISPLAY_SUPPORT_H_ */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/evkmimxrt1170_flexspi_nor_sdram.ini b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/evkmimxrt1170_flexspi_nor_sdram.ini new file mode 100644 index 00000000000..c39b5460c89 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/evkmimxrt1170_flexspi_nor_sdram.ini @@ -0,0 +1,377 @@ +/* + * Copyright 2019-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +FUNC void restoreFlexRAM(void) +{ + unsigned int value; + + value = _RDWORD(0x400E4044); + value &= ~(0xFFFF); + value |= 0xFFAA; + _WDWORD(0x400E4044, value); + + value = _RDWORD(0x400E4048); + value &= ~(0xFFFF); + value |= 0xFFAA; + _WDWORD(0x400E4048, value); + + value = _RDWORD(0x400E4040); + value &= ~(0xFF << 8); + value |= 0x7 | (0xAA << 8); + _WDWORD(0x400E4040, value); +} + +FUNC void SDRAM_WaitIpCmdDone(void) +{ + unsigned long reg; + do + { + reg = _RDWORD(0x400D403C); + }while((reg & 0x3) == 0); + + _WDWORD(0x400D403C,0x00000003); // clear IPCMDERR and IPCMDDONE bits +} + +FUNC void EnableOSC400M(void) +{ + unsigned int reg; + // CTRL1: power down + reg = _RDWORD(0x40C84050); + reg &= ~0x1; + _WDWORD(0x40C84050,reg); + // CTRL2: enable clock + reg = _RDWORD(0x40C84060); + reg |= 0x1; + _WDWORD(0x40C84060,reg); +} + +FUNC void EnableOSC24M(void) +{ + unsigned int reg; + reg = _RDWORD(0x40C84020); + if(0 == (reg & 0x10)) + { + reg = 0x14; // OSC_EN and LP_EN + _WDWORD(0x40C84020,reg); + reg = _RDWORD(0x40C84020); + while (0 == (reg & 0x80000000)); + } +} + +FUNC void EnablePllLdo(void) +{ + unsigned int reg; + // CTRL_AI_CTRL + _WDWORD(0x40C84820,0x00000000); + // CTRL_AI_WDATA + _WDWORD(0x40C84830,0x00000105); + // PMU_LDO_PLL + reg = _RDWORD(0x40C84500); + reg |= 0x10000; + _WDWORD(0x40C84500,reg); + _Sleep_(100); + + // PMU_POWER_DETECT_CTRL + _WDWORD(0x40C84580,0x00000100); + _Sleep_(1); + // PMU_REF_CTRL + _WDWORD(0x40C84570,0x00000010); +} + +FUNC void InitSysPll2Pfd1(void) +{ + unsigned int reg; + unsigned int stable; + // ANADIG_PLL_PLL_528_PFD + reg = _RDWORD(0x40C84270); + if (((reg & 0x8000) != 0) || (((reg & 0x3F00) >> 8) != 16)) + { + stable = reg & 0x4000; + + reg |= 0x8000; + _WDWORD(0x40C84270,reg); + + reg = _RDWORD(0x40C84270); + reg &= ~0x3F00; + reg |= 16 << 8; + _WDWORD(0x40C84270,reg); + + reg = _RDWORD(0x40C84250); + reg ^= 0x4; + _WDWORD(0x40C84250,reg); + + reg = _RDWORD(0x40C84270); + reg &= ~0x8000; + _WDWORD(0x40C84270,reg); + do + { + reg = _RDWORD(0x40C84270) & 0x4000; + } while (reg == stable); + } + else + { + //syspll2 pfd1 has been initialized already + reg &= ~0x8000; + _WDWORD(0x40C84270,reg); + } +} + +FUNC void InitSysPll2(void) +{ + unsigned int reg; + + // ANADIG_PLL_PLL_528_CTRL + reg = _RDWORD(0x40C84240); + if (reg & 0x800000) + { + // SysPll2 has been initialized + reg &= ~0x40000000; + _WDWORD(0x40C84240, reg); + return; + } + + reg = _RDWORD(0x40C84270); + reg |= 0x80808080; + _WDWORD(0x40C84270, reg); + + reg = _RDWORD(0x40C84240); + reg &= ~(0x802000); + reg |= 0x40000000; + _WDWORD(0x40C84240, reg); + + // ANADIG_PLL_PLL_528_MFN + _WDWORD(0x40C84280, 0); + // ANADIG_PLL_PLL_528_MFI + _WDWORD(0x40C84290, 22); + // ANADIG_PLL_PLL_528_MFD + _WDWORD(0x40C842A0, 0x0FFFFFFF); + + // ANADIG_PLL_PLL_528_CTRL + _WDWORD(0x40C84240, 0x8 | 0x40000000); + _Sleep_(30); + + // ANADIG_PLL_PLL_528_CTRL + reg = _RDWORD(0x40C84240); + reg |= 0x800000 | 0x800; + _WDWORD(0x40C84240, reg); + _Sleep_(250); + + reg = _RDWORD(0x40C84240); + reg &= ~0x800; + _WDWORD(0x40C84240, reg); + + do + { + reg = _RDWORD(0x40C84240); + } while ((reg & 0x20000000) == 0); + + reg |= 0x2000; + _WDWORD(0x40C84240, reg); + + reg &= ~0x40000000; + _WDWORD(0x40C84240, reg); +} + +FUNC void SetSemcClock(void) +{ + //EnableOSC400M(); + EnablePllLdo(); + InitSysPll2(); + InitSysPll2Pfd1(); + + // Set SEMC root clock + // Use sys pll2 pfd1 divided by 3: 198Mhz + _WDWORD(0x40CC0200,0x00000602); +} + +FUNC void _clock_init(void) +{ + SetSemcClock(); +} + +FUNC void _sdr_Init(void) +{ + // Config IOMUX + _WDWORD(0x400E8010, 0x00000000); + _WDWORD(0x400E8014, 0x00000000); + _WDWORD(0x400E8018, 0x00000000); + _WDWORD(0x400E801C, 0x00000000); + _WDWORD(0x400E8020, 0x00000000); + _WDWORD(0x400E8024, 0x00000000); + _WDWORD(0x400E8028, 0x00000000); + _WDWORD(0x400E802C, 0x00000000); + _WDWORD(0x400E8030, 0x00000000); + _WDWORD(0x400E8034, 0x00000000); + _WDWORD(0x400E8038, 0x00000000); + _WDWORD(0x400E803C, 0x00000000); + _WDWORD(0x400E8040, 0x00000000); + _WDWORD(0x400E8044, 0x00000000); + _WDWORD(0x400E8048, 0x00000000); + _WDWORD(0x400E804C, 0x00000000); + _WDWORD(0x400E8050, 0x00000000); + _WDWORD(0x400E8054, 0x00000000); + _WDWORD(0x400E8058, 0x00000000); + _WDWORD(0x400E805C, 0x00000000); + _WDWORD(0x400E8060, 0x00000000); + _WDWORD(0x400E8064, 0x00000000); + _WDWORD(0x400E8068, 0x00000000); + _WDWORD(0x400E806C, 0x00000000); + _WDWORD(0x400E8070, 0x00000000); + _WDWORD(0x400E8074, 0x00000000); + _WDWORD(0x400E8078, 0x00000000); + _WDWORD(0x400E807C, 0x00000000); + _WDWORD(0x400E8080, 0x00000000); + _WDWORD(0x400E8084, 0x00000000); + _WDWORD(0x400E8088, 0x00000000); + _WDWORD(0x400E808C, 0x00000000); + _WDWORD(0x400E8090, 0x00000000); + _WDWORD(0x400E8094, 0x00000000); + _WDWORD(0x400E8098, 0x00000000); + _WDWORD(0x400E809C, 0x00000000); + _WDWORD(0x400E80A0, 0x00000000); + _WDWORD(0x400E80A4, 0x00000000); + _WDWORD(0x400E80A8, 0x00000000); + _WDWORD(0x400E80AC, 0x00000010); // EMC_39, DQS PIN, enable SION + _WDWORD(0x400E80B0, 0x00000000); + _WDWORD(0x400E80B4, 0x00000000); + _WDWORD(0x400E80B8, 0x00000000); + _WDWORD(0x400E80BC, 0x00000000); + _WDWORD(0x400E80C0, 0x00000000); + _WDWORD(0x400E80C4, 0x00000000); + _WDWORD(0x400E80C8, 0x00000000); + _WDWORD(0x400E80CC, 0x00000000); + _WDWORD(0x400E80D0, 0x00000000); + _WDWORD(0x400E80D4, 0x00000000); + _WDWORD(0x400E80D8, 0x00000000); + _WDWORD(0x400E80DC, 0x00000000); + _WDWORD(0x400E80E0, 0x00000000); + _WDWORD(0x400E80E4, 0x00000000); + _WDWORD(0x400E80E8, 0x00000000); + _WDWORD(0x400E80EC, 0x00000000); + _WDWORD(0x400E80F0, 0x00000000); + _WDWORD(0x400E80F4, 0x00000000); + _WDWORD(0x400E80F8, 0x00000000); + _WDWORD(0x400E80FC, 0x00000000); + _WDWORD(0x400E8100, 0x00000000); + _WDWORD(0x400E8104, 0x00000000); + _WDWORD(0x400E8108, 0x00000000); + + // PAD ctrl + // PDRV = 1b (normal); PULL = 10b (PD) + _WDWORD(0x400E8254, 0x00000008); + _WDWORD(0x400E8258, 0x00000008); + _WDWORD(0x400E825C, 0x00000008); + _WDWORD(0x400E8260, 0x00000008); + _WDWORD(0x400E8264, 0x00000008); + _WDWORD(0x400E8268, 0x00000008); + _WDWORD(0x400E826C, 0x00000008); + _WDWORD(0x400E8270, 0x00000008); + _WDWORD(0x400E8274, 0x00000008); + _WDWORD(0x400E8278, 0x00000008); + _WDWORD(0x400E827C, 0x00000008); + _WDWORD(0x400E8280, 0x00000008); + _WDWORD(0x400E8284, 0x00000008); + _WDWORD(0x400E8288, 0x00000008); + _WDWORD(0x400E828C, 0x00000008); + _WDWORD(0x400E8290, 0x00000008); + _WDWORD(0x400E8294, 0x00000008); + _WDWORD(0x400E8298, 0x00000008); + _WDWORD(0x400E829C, 0x00000008); + _WDWORD(0x400E82A0, 0x00000008); + _WDWORD(0x400E82A4, 0x00000008); + _WDWORD(0x400E82A8, 0x00000008); + _WDWORD(0x400E82AC, 0x00000008); + _WDWORD(0x400E82B0, 0x00000008); + _WDWORD(0x400E82B4, 0x00000008); + _WDWORD(0x400E82B8, 0x00000008); + _WDWORD(0x400E82BC, 0x00000008); + _WDWORD(0x400E82C0, 0x00000008); + _WDWORD(0x400E82C4, 0x00000008); + _WDWORD(0x400E82C8, 0x00000008); + _WDWORD(0x400E82CC, 0x00000008); + _WDWORD(0x400E82D0, 0x00000008); + _WDWORD(0x400E82D4, 0x00000008); + _WDWORD(0x400E82D8, 0x00000008); + _WDWORD(0x400E82DC, 0x00000008); + _WDWORD(0x400E82E0, 0x00000008); + _WDWORD(0x400E82E4, 0x00000008); + _WDWORD(0x400E82E8, 0x00000008); + _WDWORD(0x400E82EC, 0x00000008); + _WDWORD(0x400E82F0, 0x00000008); + _WDWORD(0x400E82F4, 0x00000008); + _WDWORD(0x400E82F8, 0x00000008); + _WDWORD(0x400E82FC, 0x00000008); + _WDWORD(0x400E8300, 0x00000008); + _WDWORD(0x400E8304, 0x00000008); + _WDWORD(0x400E8308, 0x00000008); + _WDWORD(0x400E830C, 0x00000008); + _WDWORD(0x400E8310, 0x00000008); + _WDWORD(0x400E8314, 0x00000008); + _WDWORD(0x400E8318, 0x00000008); + _WDWORD(0x400E831C, 0x00000008); + _WDWORD(0x400E8320, 0x00000008); + _WDWORD(0x400E8324, 0x00000008); + _WDWORD(0x400E8328, 0x00000008); + _WDWORD(0x400E832C, 0x00000008); + _WDWORD(0x400E8330, 0x00000008); + _WDWORD(0x400E8334, 0x00000008); + _WDWORD(0x400E8338, 0x00000008); + _WDWORD(0x400E833C, 0x00000008); + _WDWORD(0x400E8400, 0x00000008); + _WDWORD(0x400E8404, 0x00000008); + _WDWORD(0x400E8408, 0x00000008); + _WDWORD(0x400E840C, 0x00000008); + + // Config SDR Controller Registers/ + _WDWORD(0x400d4000,0x10000004); // MCR + _WDWORD(0x400d4008,0x00000081); // BMCR0 + _WDWORD(0x400d400C,0x00000081); // BMCR1 + _WDWORD(0x400d4010,0x8000001D); // BR0, 64MB + + _WDWORD(0x400d4040,0x00000F32); // SDRAMCR0, 32bit + _WDWORD(0x400d4044,0x00772A22); // SDRAMCR1 + _WDWORD(0x400d4048,0x00010A0D); // SDRAMCR2 + _WDWORD(0x400d404C,0x21210408); // SDRAMCR3 + + _WDWORD(0x400d4090,0x80000000); // IPCR0 + _WDWORD(0x400d4094,0x00000002); // IPCR1 + _WDWORD(0x400d4098,0x00000000); // IPCR2 + + + _WDWORD(0x400d409C,0xA55A000F); // IPCMD, SD_CC_IPREA + SDRAM_WaitIpCmdDone(); + _WDWORD(0x400d409C,0xA55A000C); // SD_CC_IAF + SDRAM_WaitIpCmdDone(); + _WDWORD(0x400d409C,0xA55A000C); // SD_CC_IAF + SDRAM_WaitIpCmdDone(); + _WDWORD(0x400d40A0,0x00000033); // IPTXDAT + _WDWORD(0x400d409C,0xA55A000A); // SD_CC_IMS + SDRAM_WaitIpCmdDone(); + _WDWORD(0x400d404C,0x21210409 ); // enable sdram self refresh again after initialization done. +} + +FUNC void Setup (void) { + SP = _RDWORD(0x30002000); // Setup Stack Pointer + PC = _RDWORD(0x30002004); // Setup Program Counter + _WDWORD(0xE000ED08, 0x30002000); // Setup Vector Table Offset Register +} + +FUNC void OnResetExec (void) { // executes upon software RESET + _clock_init(); + _sdr_Init(); + Setup(); // Setup for Running +} + +restoreFlexRAM(); +_clock_init(); +_sdr_Init(); + +LOAD %L INCREMENTAL // Download + +Setup(); // Setup for Running + +// g, main diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/link.lds b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/link.lds new file mode 100644 index 00000000000..8eea1a1dcc5 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/link.lds @@ -0,0 +1,278 @@ +/* +** ################################################################### +** Processors: MIMXRT1052CVL5A +** MIMXRT1052DVL6A +** +** Compiler: GNU C Compiler +** Reference manual: IMXRT1050RM Rev.C, 08/2017 +** Version: rev. 0.1, 2017-01-10 +** Build: b170927 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** 1. Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** 2. Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** 3. Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_boot_data (RX) : ORIGIN = 0x60000000, LENGTH = 0x00001000 + m_image_vertor_table (RX) : ORIGIN = 0x60001000, LENGTH = 0x00001000 + + m_interrupts (RX) : ORIGIN = 0x60002000, LENGTH = 0x00000400 + m_text (RX) : ORIGIN = 0x60002400, LENGTH = 0x1F7FDC00 + + m_itcm (RW) : ORIGIN = 0x00000000, LENGTH = 0x00020000 + m_dtcm (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_ocram (RW) : ORIGIN = 0x20200000, LENGTH = 0x00040000 + + m_sdram (RW) : ORIGIN = 0x80000000, LENGTH = 0x01E00000 + m_nocache (RW) : ORIGIN = 0x81E00000, LENGTH = 0x00200000 +} + +/* Define output sections */ +SECTIONS +{ + __NCACHE_REGION_START = ORIGIN(m_nocache); + __NCACHE_REGION_SIZE = LENGTH(m_nocache); + .boot_data : + { + KEEP(*(.boot_hdr.conf)) + } > m_boot_data + + .image_vertor_table : + { + KEEP(*(.boot_hdr.ivt)) + KEEP(*(.boot_hdr.boot_data)) + KEEP(*(.boot_hdr.dcd_data)) + } > m_image_vertor_table + + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + __VECTOR_RAM = __VECTOR_TABLE; + __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0; + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + PROVIDE(__ctors_start__ = .); + /* __CTOR_LIST__ = .; */ + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + /* __CTOR_END__ = .; */ + PROVIDE(__ctors_end__ = .); + } > m_text + + .dtors : + { + PROVIDE(__dtors_start__ = .); + /* __DTOR_LIST__ = .; */ + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + /* __DTOR_END__ = .; */ + PROVIDE(__dtors_end__ = .); + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(m_usb_dma_init_data) + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_dtcm + + __NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__); + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_nocache + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_nocache + + __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(m_usb_dma_noninit_data) + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_dtcm + + .stack : + { + . = ALIGN(8); + stack_start = .; + . += STACK_SIZE; + stack_end = .; + __StackTop = .; + } > m_dtcm + + .RTT_HEAP : + { + heap_start = .; + . = ALIGN(8); + } > m_dtcm + + PROVIDE(heap_end = ORIGIN(m_dtcm) + LENGTH(m_dtcm)); + + .ARM.attributes 0 : { *(.ARM.attributes) } + +} + diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/link.sct b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/link.sct new file mode 100644 index 00000000000..938f2a4a059 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/link.sct @@ -0,0 +1,140 @@ +#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m7 -E -x c +/* +** ################################################################### +** Processors: MIMXRT1176AVM8A_cm7 +** MIMXRT1176CVM8A_cm7 +** MIMXRT1176DVMAA_cm7 +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: IMXRT1170RM, Rev E, 12/2019 +** Version: rev. 0.1, 2018-03-05 +** Build: b200828 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +#if (defined(__ram_vector_table__)) + #define __ram_vector_table_size__ 0x00000400 +#else + #define __ram_vector_table_size__ 0x00000000 +#endif + +#define m_flash_config_start 0x30000400 +#define m_flash_config_size 0x00000C00 + +#define m_ivt_start 0x30001000 +#define m_ivt_size 0x00001000 + +#define m_interrupts_start 0x30002000 +#define m_interrupts_size 0x00000400 + +#define m_text_start 0x30002400 +#define m_text_size 0x00FFDC00 + +#define m_interrupts_ram_start 0x80000000 +#define m_interrupts_ram_size __ram_vector_table_size__ + +#define m_data_start (m_interrupts_ram_start + m_interrupts_ram_size) +#define m_data_size (0x03000000 - m_interrupts_ram_size) + +#define m_ncache_start 0x83000000 +#define m_ncache_size 0x01000000 + +#define m_data2_start 0x20000000 +#define m_data2_size 0x00040000 + +#define m_data3_start 0x202C0000 +#define m_data3_size 0x00080000 + +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x0400 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif +#include "../../rtconfig.h" +#define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK)) + +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +LR_m_text m_flash_config_start m_text_start+m_text_size-m_flash_config_start { ; load region size_region + RW_m_config_text m_flash_config_start FIXED m_flash_config_size { ; load address = execution address + * (.boot_hdr.conf, +FIRST) + } + + RW_m_ivt_text m_ivt_start FIXED m_ivt_size { ; load address = execution address + * (.boot_hdr.ivt, +FIRST) + * (.boot_hdr.boot_data) + * (.boot_hdr.dcd_data) + } +#else +LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region +#endif + VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address + * (.isr_vector,+FIRST) + } + ER_m_text m_text_start FIXED m_text_size { ; load address = execution address + * (InRoot$$Sections) + .ANY (+RO) + } +#if (defined(__ram_vector_table__)) + VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size { + } +#else + VECTOR_RAM m_interrupts_start EMPTY 0 { + } +#endif + RW_m_data2 m_data2_start m_data2_size { + * (RamFunction) + } +#if (defined(__heap_noncacheable__)) + RW_m_data m_data_start m_data_size-Stack_Size { ; RW data +#else + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data +#endif + .ANY (+RW +ZI) + *(*m_usb_dma_init_data) + *(*m_usb_dma_noninit_data) + } +#if (!defined(__heap_noncacheable__)) + ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up + } +#endif + ; ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down + ; } + ARM_LIB_STACK +0 EMPTY Stack_Size{} ; Stack region growing down + RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{} +#if (defined(__heap_noncacheable__)) + RW_m_ncache m_ncache_start m_ncache_size - Heap_Size { ; ncache RW data +#else + RW_m_ncache m_ncache_start m_ncache_size { ; ncache RW data +#endif + * (NonCacheable.init) + * (*NonCacheable) + } +#if (defined(__heap_noncacheable__)) + ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up + } + RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache)-Heap_Size { ; Empty region added for MPU configuration +#else + RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration +#endif + } +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/link_ram.icf b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/link_ram.icf new file mode 100644 index 00000000000..62301304f73 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/link_ram.icf @@ -0,0 +1,154 @@ +/* +** ################################################################### +** Processors: MIMXRT1189CVM8B_cm7 +** MIMXRT1189CVM8C_cm7 +** MIMXRT1189XVM8B_cm7 +** MIMXRT1189XVM8C_cm7 +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: IMXRT1180RM, Rev 5, 01/2024 +** Version: rev. 2.0, 2024-01-18 +** Build: b250310 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Board memory map */ +define symbol m_itcm_start = 0x00000000; +define symbol m_itcm_size = 0x00040000; + +define symbol m_dtcm_start = 0x20000000; +define symbol m_dtcm_size = 0x00040000; + +define symbol m_ocram1_start = 0x20484000; /* OCRAM1 first 16K access is blocked by TRDC */ +define symbol m_ocram1_size = 0x0007C000; + +define symbol m_ocram2_start = 0x20500000; +define symbol m_ocram2_size = 0x00040000; + +define symbol m_sdram_start = 0x80000000; +define symbol m_sdram_size = 0x01E00000; /* Reserved 2M for CM33 usage, so size = physical memory size - 2M */ +define symbol m_hyperram_start = 0x04000000; +define symbol m_hyperram_size = 0x00600000; /* Reserved 2M for CM33 usage, so size = physical memory size - 2M */ +define symbol m_flash_start = 0x28000000; +define symbol m_flash_size = 0x01000000; + +/* General definition */ +define symbol app_image_offset = 0x0000B000; +define symbol vector_table_size = 0x00000400; +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x1000; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x4000; +} + +define symbol m_qacode_start = m_itcm_start + (isdefinedsymbol(__ram_vector_table__) ? vector_table_size : 0); +define symbol m_qacode_end = m_itcm_start + m_itcm_size - 1; +define symbol m_qadata_start = m_dtcm_start; +define symbol m_qadata_end = m_dtcm_start + m_dtcm_size - 1; +define symbol m_ram_vector_table_start = m_itcm_start; + +/* Target specific definition, code & data allocation */ +define symbol m_code_size = m_itcm_size; +define symbol m_data_size = m_dtcm_size; +define symbol m_ncache_size = isdefinedsymbol(__multicore__) ? 0x20000 : 0x40000; /* m_ncache_size must be 2^N */ +define symbol m_shmem_size = m_ocram2_size; /* m_shmem_size must be 2^N */ + +define symbol m_ocram1_size_for_cm7 = isdefinedsymbol(__multicore__) ? 0x40000 : m_ocram1_size; + +define symbol m_ram_vector_table_size = isdefinedsymbol(__ram_vector_table__) ? 0 : 0; + +define symbol m_text_start = m_itcm_start; +define symbol m_text_end = m_text_start + m_code_size - 1; +define symbol m_interrupts_start = m_text_start; + +define symbol m_data_start = m_dtcm_start; +define symbol m_data_end = m_data_start + m_data_size - 1; + +define symbol m_ncache_start = m_ocram1_start + m_ocram1_size - m_ncache_size; /* (m_ncache_start % m_ncache_size) must be 0 */ +define symbol m_ncache_end = m_ncache_start + m_ncache_size - 1; + +define symbol m_heap_start = m_ocram1_start + m_ocram1_size - m_ocram1_size_for_cm7; +define symbol m_heap_end = m_ncache_start - 1; + +if (isdefinedsymbol(__use_shmem__)) { + define symbol m_rpmsg_sh_mem_start = m_ocram2_start; /* (m_rpmsg_sh_mem_start % m_shmem_size) must be 0 */ + define symbol m_rpmsg_sh_mem_end = m_rpmsg_sh_mem_start + m_shmem_size - 1; +} + +/* Exported symbol definition */ +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = m_ram_vector_table_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = m_ram_vector_table_size; +define exported symbol __NCACHE_REGION_START = m_ncache_start; +define exported symbol __NCACHE_REGION_SIZE = m_ncache_end - m_ncache_start + 1; +if (isdefinedsymbol(__use_shmem__)) { + define exported symbol rpmsg_sh_mem_start = m_rpmsg_sh_mem_start; + define exported symbol rpmsg_sh_mem_end = m_rpmsg_sh_mem_end; + define exported symbol __RPMSG_SH_MEM_START = m_rpmsg_sh_mem_start; + define exported symbol __RPMSG_SH_MEM_SIZE = m_rpmsg_sh_mem_end - m_rpmsg_sh_mem_start + 1; +} + +define exported symbol __RTT_HEAP_END = m_ocram2_start + m_ocram2_size - 1; + +/* Region definition */ +define memory mem with size = 4G; +define region TEXT_region = mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; +define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; +define region HEAP_region = mem:[from m_heap_start to m_heap_end]; +define region QACODE_region = mem:[from m_qacode_start to m_qacode_end]; +define region QADATA_region = mem:[from m_qadata_start to m_qadata_end]; +if (isdefinedsymbol(__use_shmem__)) { + define region rpmsg_sh_mem_region = mem:[from m_rpmsg_sh_mem_start to m_rpmsg_sh_mem_end]; +} + +/* Block definition */ +define block RW { readwrite }; +define block ZI { zi }; +define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; +define block QACCESS_CODE { section CodeQuickAccess }; +define block QACCESS_DATA { section DataQuickAccess }; +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; + +initialize by copy { readwrite, section .textrw, section DataQuickAccess }; +do not initialize { section .noinit }; +if (isdefinedsymbol(__use_shmem__)) { + do not initialize { section rpmsg_sh_mem_section }; +} + +place at address mem: m_interrupts_start { readonly section .intvec }; + +place in TEXT_region { readonly }; +place in TEXT_region { block QACCESS_CODE }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { block QACCESS_DATA }; +place in NCACHE_region { block NCACHE_VAR }; +place in CSTACK_region { block CSTACK }; +if (isdefinedsymbol(__heap_noncacheable__)) { + place in NCACHE_region { last block HEAP }; +} else { + place in HEAP_region { last block HEAP }; +} +if (isdefinedsymbol(__use_shmem__)) { + place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/flexspi_port.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/flexspi_port.h new file mode 100644 index 00000000000..60514484c9e --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/flexspi_port.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-08-15 xjy198903 The first version for rt1170 + */ + +#ifndef FLEXSPI_PORT_H__ +#define FLEXSPI_PORT_H__ + +/* parameters for flexpsi peripheral */ +#define FLEXSPI1_CONTROL_BASE FLEXSPI1 +#define FLEXSPI2_CONTROL_BASE FLEXSPI2 +#define FLEXSPI_ROOT_CLK (80000000U) /* serial root clk: 80MHz*/ +#define FLASH_SIZE (32 * 1024) /* device size 32*1024(KB) = 32MB */ +#define ARD_SEQ_NUMBER 1 /* Sequence number for AHB read command */ +#define ARD_SEQ_INDEX 0 /* Sequence ID for AHB read command */ +#define AWR_SEQ_NUMBER 1 /* Sequence number for AHB write command */ +#define AWR_SEQ_INDEX 1 /* Sequence ID for AHB write command */ +#define ARD_SEQ_CMD 0xBB /* cmd for read */ +#define AWR_SEQ_CMD 0xAA /* cmd for write */ +#define FLEXSPI_RX_SAMPLE_CLOCK kFLEXSPI_ReadSampleClkExternalInputFromDqsPad +#define FLASH_PORT kFLEXSPI_PortA1 +#define CLOCK_SRC kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc400M +#define CLOCK_DIV 5U +#define CUSTOM_LUT_LENGTH 64U +#define FLEXSPI1_AHB_DATA_ADDRESS (0x30000000U) +#define FLEXSPI2_AHB_DATA_ADDRESS (0x60000000U) +#endif /* FLEXSPI_PORT_H__ */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/sdram_port.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/sdram_port.h new file mode 100644 index 00000000000..9bdb3b617e3 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/ports/sdram_port.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-05 zylx The first version for STM32F4xx + * 2019-4-25 misonyo port to IMXRT + * 2022-08-15 xjy198903 add sdram config for rt1170 + */ + +#ifndef SDRAM_PORT_H__ +#define SDRAM_PORT_H__ + +/* parameters for sdram peripheral */ + +#define SDRAM_BANK_ADDR ((uint32_t)0x80000000U) +/* region#0/1/2/3: kSEMC_SDRAM_CS0/1/2/3 */ +#define SDRAM_REGION kSEMC_SDRAM_CS0 +/* CS pin: kSEMC_MUXCSX0/1/2/3 */ +#define SDRAM_CS_PIN kSEMC_MUXCSX0 +/* size(kbyte):64MB = 2*32*1024*1KBytes */ +#if defined(SOC_IMXRT1170_SERIES) +#define SDRAM_SIZE ((uint32_t)(0x10000)) +/* data width: kSEMC_PortSize8Bit,kSEMC_PortSize32Bit */ +#define SDRAM_DATA_WIDTH kSEMC_PortSize32Bit +#else +/* size(kbyte):32MB = 32*1024*1KBytes */ +#define SDRAM_SIZE ((uint32_t)0x8000) +/* data width: kSEMC_PortSize8Bit,kSEMC_PortSize16Bit */ +#define SDRAM_DATA_WIDTH kSEMC_PortSize16Bit +#endif +/* column bit numbers: kSEMC_SdramColunm_9/10/11/12bit */ +#define SDRAM_COLUMN_BITS kSEMC_SdramColunm_9bit +/* cas latency clock number: kSEMC_LatencyOne/Two/Three */ +#define SDRAM_CAS_LATENCY kSEMC_LatencyThree + +/* Timing configuration for W9825G6KH */ +/* TRP:precharge to active command time (ns) */ +#define SDRAM_TRP 18 +/* TRCD:active to read/write command delay time (ns) */ +#define SDRAM_TRCD 18 +/* The time between two refresh commands,Use the maximum of the (Trfc , Txsr).(ns) */ +#define SDRAM_REFRESH_RECOVERY 67 +/* TWR:write recovery time (ns). */ +#define SDRAM_TWR 12 +/* TRAS:active to precharge command time (ns). */ +#define SDRAM_TRAS 42 +/* TRC time (ns). */ +#define SDRAM_TRC 60 +/* active to active time (ns). */ +#define SDRAM_ACT2ACT 60 +/* refresh time (ns). 64ms */ +#define SDRAM_REFRESH_ROW 64 * 1000000 / 8192 + +#endif /* SDRAM_PORT_H__ */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/vglite_support.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/vglite_support.c new file mode 100644 index 00000000000..77ef33e1687 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/vglite_support.c @@ -0,0 +1,87 @@ +/* + * Copyright 2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "vglite_support.h" +#include "fsl_clock.h" +#include "vg_lite.h" +#include "vg_lite_platform.h" +#include "display_support.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define MAX_CONTIGUOUS_SIZE 0x200000 +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +static uint32_t registerMemBase = 0x41800000; +static uint32_t gpu_mem_base = 0x0; + +/* + * In case custom VGLite memory parameters are used, the application needs to + * allocate and publish the VGLite heap base, its size and the size of the + * command buffer(s) using the following global variables: + */ +extern void *vglite_heap_base; +extern uint32_t vglite_heap_size; + +#if (CUSTOM_VGLITE_MEMORY_CONFIG == 0) +/* VGLite driver heap */ +AT_NONCACHEABLE_SECTION_ALIGN(static uint8_t contiguous_mem[MAX_CONTIGUOUS_SIZE], FRAME_BUFFER_ALIGN); + +void *vglite_heap_base = &contiguous_mem; +uint32_t vglite_heap_size = MAX_CONTIGUOUS_SIZE; +#endif /* CUSTOM_VGLITE_MEMORY_CONFIG */ + +/******************************************************************************* + * Code + ******************************************************************************/ +void GPU2D_IRQHandler(void) +{ + vg_lite_IRQHandler(); +} + +static status_t BOARD_InitVGliteClock(void) +{ + const clock_root_config_t gc355ClockConfig = { + .clockOff = false, + .mux = kCLOCK_GC355_ClockRoot_MuxVideoPllOut, /*!< 984MHz */ + .div = 2, + }; + + CLOCK_SetRootClock(kCLOCK_Root_Gc355, &gc355ClockConfig); + + CLOCK_GetRootClockFreq(kCLOCK_Root_Gc355); + + CLOCK_EnableClock(kCLOCK_Gpu2d); + + NVIC_SetPriority(GPU2D_IRQn, 3); + + EnableIRQ(GPU2D_IRQn); + + return kStatus_Success; +} + +status_t BOARD_PrepareVGLiteController(void) +{ + status_t status; + + status = BOARD_InitVGliteClock(); + + if (kStatus_Success != status) + { + return status; + } + + vg_lite_init_mem(registerMemBase, gpu_mem_base, vglite_heap_base, vglite_heap_size); + + return kStatus_Success; +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/vglite_support.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/vglite_support.h new file mode 100644 index 00000000000..a2cfa43be63 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/vglite_support.h @@ -0,0 +1,36 @@ +/* + * Copyright 2019, 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _VGLITE_SUPPORT_H_ +#define _VGLITE_SUPPORT_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +#define VG_LITE_COMMAND_BUFFER_SIZE (256 << 10) /* 256 KB */ + +/* Default tessellation window width and height, in pixels */ +#define DEFAULT_VG_LITE_TW_WIDTH 128 /* pixels */ +#define DEFAULT_VG_LITE_TW_HEIGHT 128 /* pixels */ + +status_t BOARD_PrepareVGLiteController(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _VGLITE_SUPPORT_H_ */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/vglite_window.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/vglite_window.c new file mode 100644 index 00000000000..70c16fd63c7 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/vglite_window.c @@ -0,0 +1,180 @@ +/* + * Copyright 2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "vglite_support.h" +#include "vg_lite_platform.h" +#include "vglite_window.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#if !DEMO_BUFFER_FIXED_ADDRESS +AT_NONCACHEABLE_SECTION_ALIGN( + static uint8_t s_frameBuffer[APP_BUFFER_COUNT][DEMO_BUFFER_HEIGHT][DEMO_BUFFER_WIDTH][DEMO_BUFFER_BYTE_PER_PIXEL], + FRAME_BUFFER_ALIGN); + +#define DEMO_BUFFER0_ADDR (uint32_t) s_frameBuffer[0] + +#if APP_BUFFER_COUNT > 1 +#define DEMO_BUFFER1_ADDR (uint32_t) s_frameBuffer[1] +#endif + +#if APP_BUFFER_COUNT > 2 +#define DEMO_BUFFER2_ADDR (uint32_t) s_frameBuffer[2] +#endif + +#endif + +static const uint32_t s_frameBufferAddress[APP_BUFFER_COUNT] = {DEMO_BUFFER0_ADDR, +#if APP_BUFFER_COUNT > 1 + DEMO_BUFFER1_ADDR, +#endif +#if APP_BUFFER_COUNT > 2 + DEMO_BUFFER2_ADDR +#endif +}; +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +static vg_lite_buffer_format_t video_format_to_vglite(video_pixel_format_t format) +{ + vg_lite_buffer_format_t fmt; + switch (format) + { + case kVIDEO_PixelFormatRGB565: + fmt = VG_LITE_BGR565; + break; + + case kVIDEO_PixelFormatBGR565: + fmt = VG_LITE_RGB565; + break; + + case kVIDEO_PixelFormatXRGB8888: + fmt = VG_LITE_BGRX8888; + break; + + default: + fmt = VG_LITE_RGB565; + break; + } + + return fmt; +} + +vg_lite_error_t VGLITE_CreateDisplay(vg_lite_display_t *display) +{ + if (!display) + return VG_LITE_INVALID_ARGUMENT; + + FBDEV_Open(&display->g_fbdev, &g_dc, 0); + + return VG_LITE_SUCCESS; +} + +vg_lite_error_t VGLITE_CreateWindow(vg_lite_display_t *display, vg_lite_window_t *window) +{ + vg_lite_error_t ret = VG_LITE_SUCCESS; + status_t status; + void *buffer; + vg_lite_buffer_t *vg_buffer; + fbdev_t *g_fbdev = &(display->g_fbdev); + fbdev_fb_info_t *g_fbInfo = &(display->g_fbInfo); + + window->bufferCount = APP_BUFFER_COUNT; + window->display = display; + window->width = DEMO_BUFFER_WIDTH; + window->height = DEMO_BUFFER_HEIGHT; + window->current = -1; + FBDEV_GetFrameBufferInfo(g_fbdev, g_fbInfo); + + g_fbInfo->bufInfo.pixelFormat = DEMO_BUFFER_PIXEL_FORMAT; + g_fbInfo->bufInfo.startX = DEMO_BUFFER_START_X; + g_fbInfo->bufInfo.startY = DEMO_BUFFER_START_Y; + g_fbInfo->bufInfo.width = window->width; + g_fbInfo->bufInfo.height = window->height; + g_fbInfo->bufInfo.strideBytes = DEMO_BUFFER_STRIDE_BYTE; + + g_fbInfo->bufferCount = window->bufferCount; + for (uint8_t i = 0; i < window->bufferCount; i++) + { + vg_buffer = &(window->buffers[i]); + g_fbInfo->buffers[i] = (void *)s_frameBufferAddress[i]; + vg_buffer->memory = g_fbInfo->buffers[i]; + vg_buffer->address = s_frameBufferAddress[i]; + vg_buffer->width = g_fbInfo->bufInfo.width; + vg_buffer->height = g_fbInfo->bufInfo.height; + vg_buffer->stride = g_fbInfo->bufInfo.strideBytes; + vg_buffer->format = video_format_to_vglite(DEMO_BUFFER_PIXEL_FORMAT); + } + + status = FBDEV_SetFrameBufferInfo(g_fbdev, g_fbInfo); + if (status != kStatus_Success) + { + while (1) + ; + } + + buffer = FBDEV_GetFrameBuffer(g_fbdev, 0); + + assert(buffer != NULL); + + memset(buffer, 0, g_fbInfo->bufInfo.height * g_fbInfo->bufInfo.strideBytes); + + FBDEV_SetFrameBuffer(g_fbdev, buffer, 0); + + FBDEV_Enable(g_fbdev); + + return ret; +} + +vg_lite_error_t VGLITE_DestoryWindow(void) +{ + return VG_LITE_SUCCESS; +} + +vg_lite_error_t VGLITE_DestroyDisplay(void) +{ + return VG_LITE_SUCCESS; +} + +vg_lite_buffer_t *VGLITE_GetRenderTarget(vg_lite_window_t *window) +{ + vg_lite_buffer_t *rt = NULL; + void *memory = FBDEV_GetFrameBuffer(&window->display->g_fbdev, 0); + for (uint8_t i = 0; i < window->bufferCount; i++) + { + rt = &(window->buffers[i]); + if (memory == rt->memory) + { + window->current = i; + return rt; + } + } + return NULL; +} + +void VGLITE_SwapBuffers(vg_lite_window_t *window) +{ + vg_lite_buffer_t *rt; + if (window->current >= 0 && window->current < window->bufferCount) + rt = &(window->buffers[window->current]); + else + return; + + vg_lite_finish(); + + FBDEV_SetFrameBuffer(&window->display->g_fbdev, rt->memory, 0); +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/vglite_window.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/vglite_window.h new file mode 100644 index 00000000000..c617b61e22f --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/vglite_window.h @@ -0,0 +1,62 @@ +/* + * Copyright 2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _VGLITE_WINDOW_H_ +#define _VGLITE_WINDOW_H_ + +#include "fsl_common.h" +#include "vg_lite.h" +#include "vglite_support.h" +#include "display_support.h" +#include "fsl_fbdev.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define APP_BUFFER_COUNT 2 + +typedef struct vg_lite_display +{ + fbdev_t g_fbdev; + fbdev_fb_info_t g_fbInfo; +} vg_lite_display_t; + +typedef struct vg_lite_window +{ + vg_lite_display_t *display; + vg_lite_buffer_t buffers[APP_BUFFER_COUNT]; + int width; + int height; + int bufferCount; + int current; +} vg_lite_window_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +vg_lite_error_t VGLITE_CreateDisplay(vg_lite_display_t *display); + +vg_lite_error_t VGLITE_CreateWindow(vg_lite_display_t *display, vg_lite_window_t *window); + +vg_lite_error_t VGLITE_DestoryWindow(void); + +vg_lite_error_t VGLITE_DestroyDisplay(void); + +vg_lite_buffer_t *VGLITE_GetRenderTarget(vg_lite_window_t *window); + +void VGLITE_SwapBuffers(vg_lite_window_t *window); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _VGLITE_WINDOW_H_ */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/evkmimxrt1180.mac b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/evkmimxrt1180.mac new file mode 100644 index 00000000000..8b21a75c9e9 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/evkmimxrt1180.mac @@ -0,0 +1,430 @@ +/* + * Copyright 2023-2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +_FLEXSPI1_ModuleReset() +{ + __var reg; + + reg = __readMemory32(0x425E0000, "Memory"); // FlexSPI1->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + reg = __readMemory32(0x425E0000, "Memory"); + __writeMemory32((reg | 0x1), 0x425E0000, "Memory"); + do + { + reg = __readMemory32(0x425E0000, "Memory"); + } while ((reg & 0x1) != 0); + } +} + +_FLEXSPI1_WaitBusIdle() +{ + __var reg; + + reg = __readMemory32(0x425E0000, "Memory"); // FlexSPI1->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + do + { + reg = __readMemory32(0x425E00E0, "Memory"); + } while ((reg & 0x3) != 0x3); + } +} + +_FLEXSPI1_ClockInit() +{ + __writeMemory32(0x0, 0x54484350, "Memory"); // ROSC400M_CTRL1 + + // Set flexspi1 root clock, use ROSC400, div = 4 = 1+3 + __writeMemory32(0x103, 0x54450A80, "Memory"); // CLOCK_ROOT[21].CONTROL, FlexSPI1 +} + +_FLEXSPI1_SetPinForQuadMode() { + // Set 4 Pin Mode for JLink + __writeMemory32(0x17, 0x42A1023C, "Memory"); // IOMUXC_GPIO_B2_07_FLEXSPI1_BUS2BIT_A_DQS + __writeMemory32(0x1, 0x42A10544, "Memory"); + __writeMemory32(0x17, 0x42A10240, "Memory"); // IOMUXC_GPIO_B2_08_FLEXSPI1_BUS2BIT_A_SCLK + __writeMemory32(0x17, 0x42A10244, "Memory"); // IOMUXC_GPIO_B2_09_FLEXSPI1_BUS2BIT_A_SS0_B + __writeMemory32(0x17, 0x42A10248, "Memory"); // IOMUXC_GPIO_B2_10_FLEXSPI1_BUS2BIT_A_DATA00 + __writeMemory32(0x17, 0x42A1024C, "Memory"); // IOMUXC_GPIO_B2_11_FLEXSPI1_BUS2BIT_A_DATA01 + __writeMemory32(0x17, 0x42A10250, "Memory"); // IOMUXC_GPIO_B2_12_FLEXSPI1_BUS2BIT_A_DATA02 + __writeMemory32(0x17, 0x42A10254, "Memory"); // IOMUXC_GPIO_B2_13_FLEXSPI1_BUS2BIT_A_DATA03 +} + +_FLEXSPI1_ModuleInit() { + + __var reg; + + reg = __readMemory32(0x425E0000, "Memory"); + __writeMemory32((reg & 0xFFFFFFFD), 0x425E0000, "Memory"); + + //FLEXSPI1->MCR0 = 0xFFFF8010; + __writeMemory32(0xFFFF8010, 0x425E0000, "Memory"); + //FLEXSPI1->MCR2 = 0x200001F7; + __writeMemory32(0x200001F7, 0x425E0008, "Memory"); + //FLEXSPI1->AHBCR = 0x78; + __writeMemory32(0x78, 0x425E000C, "Memory"); + + //FLEXSPI1->FLSHCR0[0] = 0x00004000; + __writeMemory32(0x00004000, 0x425E0060, "Memory"); + + //FLEXSPI1->FLSHCR4 = 0xC3; + __writeMemory32(0xC3, 0x425E0094, "Memory"); + //FLEXSPI1->IPRXFCR = 0x1C; + __writeMemory32(0x1C, 0x425E00B8, "Memory"); + + //FLEXSPI1->LUTKEY = 0x5AF05AF0UL; + __writeMemory32(0x5AF05AF0, 0x425E0018, "Memory"); + //FLEXSPI1->LUTCR = 0x02; + __writeMemory32(0x02, 0x425E001C, "Memory"); + + //FLEXSPI1->LUT[0] = 0x0A1804EB; // AHB Quad Read Change to use Fast Read Quad + __writeMemory32(0x0A1804EB, 0x425E0200, "Memory"); + //FLEXSPI1->LUT[1] = 0x26043206; + __writeMemory32(0x26043206, 0x425E0204, "Memory"); + //FLEXSPI1->LUT[2] = 0x00000000; + __writeMemory32(0x00000000, 0x425E0208, "Memory"); + //FLEXSPI1->LUT[3] = 0x00000000; + __writeMemory32(0x00000000, 0x425E020C, "Memory"); + + //FLEXSPI1->LUT[4] = 0x00000406; // Write Enable + __writeMemory32(0x00000406, 0x425E0210, "Memory"); + //FLEXSPI1->LUT[5] = 0x00000000; + __writeMemory32(0x00000000, 0x425E0214, "Memory"); + //FLEXSPI1->LUT[6] = 0x00000000; + __writeMemory32(0x00000000, 0x425E0218, "Memory"); + //FLEXSPI1->LUT[7] = 0x00000000; + __writeMemory32(0x00000000, 0x425E021C, "Memory"); + + //FLEXSPI1->LUT[8] = 0x20040401; // Wirte s1 + __writeMemory32(0x20040401, 0x425E0220, "Memory"); + //FLEXSPI1->LUT[9] = 0x00000000; + __writeMemory32(0x00000000, 0x425E0224, "Memory"); + //FLEXSPI1->LUT[10] = 0x00000000; + __writeMemory32(0x00000000, 0x425E0228, "Memory"); + //FLEXSPI1->LUT[11] = 0x00000000; + __writeMemory32(0x00000000, 0x425E022C, "Memory"); + + //FLEXSPI1->LUT[12] = 0x24040405; // Read s1 + __writeMemory32(0x24040405, 0x425E0230, "Memory"); + //FLEXSPI1->LUT[13] = 0x00000000; + __writeMemory32(0x00000000, 0x425E0234, "Memory"); + //FLEXSPI1->LUT[14] = 0x00000000; + __writeMemory32(0x00000000, 0x425E0238, "Memory"); + //FLEXSPI1->LUT[15] = 0x00000000; + __writeMemory32(0x00000000, 0x425E023C, "Memory"); + + //FLEXSPI1->LUT[16] = 0x00000404; // Write Disable + __writeMemory32(0x00000404, 0x425E0240, "Memory"); + //FLEXSPI1->LUT[17] = 0x00000000; + __writeMemory32(0x00000000, 0x425E0244, "Memory"); + //FLEXSPI1->LUT[18] = 0x00000000; + __writeMemory32(0x00000000, 0x425E0248, "Memory"); + //FLEXSPI1->LUT[19] = 0x00000000; + __writeMemory32(0x00000000, 0x425E024C, "Memory"); + + //FLEXSPI1->LUT[20] = 0x20040431; // Wirte s2 + __writeMemory32(0x20040431, 0x425E0250, "Memory"); + //FLEXSPI1->LUT[21] = 0x00000000; + __writeMemory32(0x00000000, 0x425E0254, "Memory"); + //FLEXSPI1->LUT[22] = 0x00000000; + __writeMemory32(0x00000000, 0x425E0258, "Memory"); + //FLEXSPI1->LUT[23] = 0x00000000; + __writeMemory32(0x00000000, 0x425E025C, "Memory"); + + //FLEXSPI1->LUT[24] = 0x24040435; // Read s2 + __writeMemory32(0x24040435, 0x425E0260, "Memory"); + //FLEXSPI1->LUT[25] = 0x00000000; + __writeMemory32(0x00000000, 0x425E0264, "Memory"); + //FLEXSPI1->LUT[26] = 0x00000000; + __writeMemory32(0x00000000, 0x425E0268, "Memory"); + //FLEXSPI1->LUT[27] = 0x00000000; + __writeMemory32(0x00000000, 0x425E026C, "Memory"); + + //FLEXSPI1->LUT[28] = 0x00000450; // Write Enable Volatile + __writeMemory32(0x00000450, 0x425E0270, "Memory"); + //FLEXSPI1->LUT[29] = 0x00000000; + __writeMemory32(0x00000000, 0x425E0274, "Memory"); + //FLEXSPI1->LUT[30] = 0x00000000; + __writeMemory32(0x00000000, 0x425E0278, "Memory"); + //FLEXSPI1->LUT[31] = 0x00000000; + __writeMemory32(0x00000000, 0x425E027C, "Memory"); + + //FLEXSPI1->LUTKEY = 0x5AF05AF0UL; + __writeMemory32(0x5AF05AF0, 0x425E0018, "Memory"); + //FLEXSPI1->LUTCR = 0x01; + __writeMemory32(0x01, 0x425E001C, "Memory"); +} + +_FLEXSPI2_ModuleReset() +{ + __var reg; + + reg = __readMemory32(0x445E0000, "Memory"); // FlexSPI2->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + reg = __readMemory32(0x445E0000, "Memory"); + __writeMemory32((reg | 0x1), 0x445E0000, "Memory"); + do + { + reg = __readMemory32(0x445E0000, "Memory"); + } while ((reg & 0x1) != 0); + } +} + +_FLEXSPI2_WaitBusIdle() +{ + __var reg; + + reg = __readMemory32(0x445E0000, "Memory"); // FlexSPI2->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + do + { + reg = __readMemory32(0x445E00E0, "Memory"); + } while ((reg & 0x3) != 0x3); + } +} + +_FlexSPI2_SetPinForOctalMode() +{ + // Config IOMUX for HyperRAM + __writeMemory32(0x00000013, 0x42A10088, "Memory");// FLEXSPI2_B_DATA03 + __writeMemory32(0x00000013, 0x42A1008C, "Memory");// FLEXSPI2_B_DATA02 + __writeMemory32(0x00000013, 0x42A10090, "Memory");// FLEXSPI2_B_DATA01 + __writeMemory32(0x00000013, 0x42A10094, "Memory");// FLEXSPI2_B_DATA00 + __writeMemory32(0x00000013, 0x42A1009C, "Memory");// FLEXSPI2_A_DATA00 + __writeMemory32(0x00000013, 0x42A100A0, "Memory");// FLEXSPI2_A_DATA01 + __writeMemory32(0x00000013, 0x42A100A4, "Memory");// FLEXSPI2_A_DATA02 + __writeMemory32(0x00000013, 0x42A100A8, "Memory");// FLEXSPI2_A_DATA03 + __writeMemory32(0x00000013, 0x42A100AC, "Memory");// FLEXSPI2_A_SS0_B + __writeMemory32(0x00000013, 0x42A100B0, "Memory");// FLEXSPI2_A_DQS + __writeMemory32(0x00000013, 0x42A100B4, "Memory");// FLEXSPI2_A_SCLK + + //The input daisy!! + __writeMemory32(0x00000001, 0x42A10594, "Memory");// FLEXSPI2_B_DATA03 + __writeMemory32(0x00000001, 0x42A10590, "Memory");// FLEXSPI2_B_DATA02 + __writeMemory32(0x00000001, 0x42A1058C, "Memory");// FLEXSPI2_B_DATA01 + __writeMemory32(0x00000001, 0x42A10588, "Memory");// FLEXSPI2_B_DATA00 + __writeMemory32(0x00000000, 0x42A10578, "Memory");// FLEXSPI2_A_DATA00 + __writeMemory32(0x00000000, 0x42A1057C, "Memory");// FLEXSPI2_A_DATA01 + __writeMemory32(0x00000000, 0x42A10580, "Memory");// FLEXSPI2_A_DATA02 + __writeMemory32(0x00000000, 0x42A10584, "Memory");// FLEXSPI2_A_DATA03 + __writeMemory32(0x00000000, 0x42A10570, "Memory");// FLEXSPI2_A_DQS + __writeMemory32(0x00000000, 0x42A10598, "Memory");// FLEXSPI2_A_SCLK + + // PAD ctrl + __writeMemory32(0x00000008, 0x42A102D0, "Memory");// FLEXSPI2_B_DATA03 + __writeMemory32(0x00000008, 0x42A102D4, "Memory");// FLEXSPI2_B_DATA02 + __writeMemory32(0x00000008, 0x42A102D8, "Memory");// FLEXSPI2_B_DATA01 + __writeMemory32(0x00000008, 0x42A102DC, "Memory");// FLEXSPI2_B_DATA00 + __writeMemory32(0x00000008, 0x42A102E4, "Memory");// FLEXSPI2_A_DATA00 + __writeMemory32(0x00000008, 0x42A102E8, "Memory");// FLEXSPI2_A_DATA01 + __writeMemory32(0x00000008, 0x42A102EC, "Memory");// FLEXSPI2_A_DATA02 + __writeMemory32(0x00000008, 0x42A102F0, "Memory");// FLEXSPI2_A_DATA03 + __writeMemory32(0x00000008, 0x42A102F4, "Memory");// FLEXSPI2_A_SS0_B + __writeMemory32(0x00000008, 0x42A102F8, "Memory");// FLEXSPI2_A_DQS + __writeMemory32(0x00000008, 0x42A102FC, "Memory");// FLEXSPI2_A_SCLK +} + +_FLEXSPI2_ClockInit() +{ + __writeMemory32(0x0, 0x54484350, "Memory"); // ROSC400M_CTRL1 + + // Set flexspi2 root clock, use ROSC400, div = 2 = 1+1 + __writeMemory32(0x101, 0x44450B00, "Memory"); // CLOCK_ROOT[22].CONTROL, FlexSPI2 +} + +_FLEXSPI2_ModuleInit() +{ + // Config FlexSPI2 Registers + + __var reg; + reg = __readMemory32(0x445E0000, "Memory"); + __writeMemory32((reg & 0xFFFFFFFD), 0x445E0000, "Memory"); + + _FLEXSPI2_ModuleReset(); + + __writeMemory32(0xFFFF3032, 0x445E0000, "Memory"); // MCR0 + __writeMemory32(0xFFFFFFFF, 0x445E0004, "Memory"); // MCR1 + __writeMemory32(0x200001F7, 0x445E0008, "Memory"); // MCR2 + __writeMemory32(0x00000078, 0x445E000C, "Memory"); // AHBCR prefetch enable + __writeMemory32(0x800F0000, 0x445E0020, "Memory"); // AHBRXBUF0CR0 + __writeMemory32(0x800F0000, 0x445E0024, "Memory"); // AHBRXBUF1CR0 + __writeMemory32(0x800F0000, 0x445E0028, "Memory"); // AHBRXBUF2CR0 + __writeMemory32(0x800F0000, 0x445E002C, "Memory"); // AHBRXBUF3CR0 + __writeMemory32(0x800F0000, 0x445E0030, "Memory"); // AHBRXBUF4CR0 + __writeMemory32(0x800F0000, 0x445E0034, "Memory"); // AHBRXBUF5CR0 + __writeMemory32(0x80000020, 0x445E0038, "Memory"); // AHBRXBUF6CR0 + __writeMemory32(0x80000020, 0x445E003C, "Memory"); // AHBRXBUF7CR0 + __writeMemory32(0x00000000, 0x445E00B8, "Memory"); // IPRXFCR + __writeMemory32(0x00000000, 0x445E00BC, "Memory"); // IPTXFCR + + __writeMemory32(0x00000000, 0x445E0060, "Memory"); // FLASHA1CR0 + __writeMemory32(0x00000000, 0x445E0064, "Memory"); // FLASHA2CR0 + __writeMemory32(0x00000000, 0x445E0068, "Memory"); // FLASHB1CR0 + __writeMemory32(0x00000000, 0x445E006C, "Memory"); // FLASHB2CR0 + + _FLEXSPI2_WaitBusIdle(); + + __writeMemory32(0x00002000, 0x445E0060, "Memory"); // FLASHA1CR0 + __writeMemory32(0x00021C63, 0x445E0070, "Memory"); // FLASHA1CR1 + __writeMemory32(0x00000100, 0x445E0080, "Memory"); // FLASHA1CR2 + + _FLEXSPI2_WaitBusIdle(); + + __writeMemory32(0x00000079, 0x445E00C0, "Memory"); // DLLCRA + __writeMemory32(0xFFFF3030, 0x445E0000, "Memory"); // MCR0 + + do + { + reg = __readMemory32(0x445E00E8, "Memory"); + } while (0x3 != (reg & 0x3)); + __delay(1000); // 1ms + + __writeMemory32(0xFFFF3032, 0x445E0000, "Memory"); // MCR0 + __writeMemory32(0x000000C2, 0x445E0094, "Memory"); // FLASHCR4 + __writeMemory32(0x000000C6, 0x445E0094, "Memory"); // FLASHCR4 + __writeMemory32(0xFFFF3030, 0x445E0000, "Memory"); // MCR0 + + _FLEXSPI2_WaitBusIdle(); + + __writeMemory32(0x5AF05AF0, 0x445E0018, "Memory"); // LUTKEY + __writeMemory32(0x00000002, 0x445E001C, "Memory"); // LUTCR + __writeMemory32(0x8B1887A0, 0x445E0200, "Memory"); // LUT[0] + __writeMemory32(0xB7078F10, 0x445E0204, "Memory"); // LUT[1] + __writeMemory32(0x0000A704, 0x445E0208, "Memory"); // LUT[2] + __writeMemory32(0x00000000, 0x445E020C, "Memory"); // LUT[3] + __writeMemory32(0x8B188720, 0x445E0210, "Memory"); // LUT[4] + __writeMemory32(0xB7078F10, 0x445E0214, "Memory"); // LUT[5] + __writeMemory32(0x0000A304, 0x445E0218, "Memory"); // LUT[6] + __writeMemory32(0x00000000, 0x445E021C, "Memory"); // LUT[7] + __writeMemory32(0x8B1887E0, 0x445E0220, "Memory"); // LUT[8] + __writeMemory32(0xB7078F10, 0x445E0224, "Memory"); // LUT[9] + __writeMemory32(0x0000A704, 0x445E0228, "Memory"); // LUT[10] + __writeMemory32(0x00000000, 0x445E022C, "Memory"); // LUT[11] + __writeMemory32(0x8B188760, 0x445E0230, "Memory"); // LUT[12] + __writeMemory32(0xA3028F10, 0x445E0234, "Memory"); // LUT[13] + __writeMemory32(0x00000000, 0x445E0238, "Memory"); // LUT[14] + __writeMemory32(0x00000000, 0x445E023C, "Memory"); // LUT[15] + __writeMemory32(0x00000000, 0x445E0240, "Memory"); // LUT[16] + __writeMemory32(0x00000000, 0x445E0244, "Memory"); // LUT[17] + __writeMemory32(0x00000000, 0x445E0248, "Memory"); // LUT[18] + __writeMemory32(0x00000000, 0x445E024C, "Memory"); // LUT[19] + __writeMemory32(0x5AF05AF0, 0x445E0018, "Memory"); // LUTKEY + __writeMemory32(0x00000001, 0x445E001C, "Memory"); // LUTCR + + /* Restore hyperram CR0 register */ + __writeMemory32(0x00001000, 0x445E00A0, "Memory"); // IPCR0 + __writeMemory32(0x00030002, 0x445E00A4, "Memory"); // IPCR1 + __writeMemory32(0x00000001, 0x445E00BC, "Memory"); // IPTXFCR + __writeMemory32(0x2F8F2F8F, 0x445E0180, "Memory"); // TFDR 0x8F2F is default value of W756/7x of CR0 + __writeMemory32(0x00000040, 0x445E0014, "Memory"); // INTR + __writeMemory32(0x00000001, 0x445E00B0, "Memory"); // IPCMD + do + { + reg = __readMemory32(0x445E0014, "Memory"); // INTR + } while ((reg & 0x1) == 0x0); + __writeMemory32(0x00000001, 0x445E0014, "Memory"); // INTR + + /* Restore hyperram CR1 register */ + __writeMemory32(0x00001002, 0x445E00A0, "Memory"); // IPCR0 + __writeMemory32(0x00030002, 0x445E00A4, "Memory"); // IPCR1 + __writeMemory32(0x00000001, 0x445E00BC, "Memory"); // IPTXFCR + __writeMemory32(0xC1FFC1FF, 0x445E0180, "Memory"); // TFDR 0xFFC1 is default value of W756/7x of CR1 + __writeMemory32(0x00000040, 0x445E0014, "Memory"); // INTR + __writeMemory32(0x00000001, 0x445E00B0, "Memory"); // IPCMD + do + { + reg = __readMemory32(0x445E0014, "Memory"); // INTR + } while ((reg & 0x1) == 0x0); + __writeMemory32(0x00000001, 0x445E0014, "Memory"); // INTR + + _FLEXSPI2_ModuleReset(); +} + +HyperRAM_Init() +{ + __message "Init HyperRAM"; + + _FLEXSPI2_WaitBusIdle(); + _FLEXSPI2_ModuleReset(); + + _FlexSPI2_SetPinForOctalMode(); + _FLEXSPI2_ClockInit(); + _FLEXSPI2_ModuleInit(); + + __message "HyperRAM init done\n"; +} + +Flash_Init() +{ + __message "Init Flash"; + + _FLEXSPI1_WaitBusIdle(); + _FLEXSPI1_ModuleReset(); + + _FLEXSPI1_SetPinForQuadMode(); + _FLEXSPI1_ClockInit(); + _FLEXSPI1_ModuleInit(); + + __message "Flash init done\n"; +} + +execUserPreload() +{ + Flash_Init(); + HyperRAM_Init(); +} + +execUserReset() +{ + Flash_Init(); + HyperRAM_Init(); +} + +CleanInvalidateCache(cache) +{ + __var reg; + reg = __readMemory32(cache, "Memory"); + if((reg & 0x01) != 0) + { + __writeMemory32(0x0F000000 | reg, cache, "Memory"); + __writeMemory32(0x8F000000 | reg, cache, "Memory"); + + do + { + reg = __readMemory32(cache, "Memory"); + } while (( reg & 0x80000000) != 0); + } +} + +execUserExecutionStarted() +{ + /* + CMSIS-DAP probably use software breakpoint by default, + which fails debug for those code within cached memory, + e.g. hyperram_txt_debug/release. + With cache operation below, it helps debug for software + breakpoint, but still fails in assembly instruction + step debug, since execUserExecutionStarted is not invoked + in assembly instruction setp debug. + + The final solution for cached memory code debug, is to use + hardware breakpoint, which can be set in IAR project option: + Debug->CMSIS DAP->breakpoint. + */ + + __var reg; + reg = __readMemory32(0xE000ED00, "Memory"); // SCB->CPUID + if(__driverType("cmsisdap") && (reg == 0x411FD210)) + { + // CMSIS-DAP and CM33 core + CleanInvalidateCache(0x44400000); // XCACHE_PC_CCR + CleanInvalidateCache(0x44400800); // XCACHE_PS_CCR + } +} \ No newline at end of file diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/evkmimxrt1180_cm7.jlinkscript b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/evkmimxrt1180_cm7.jlinkscript new file mode 100644 index 00000000000..24be3e988fc --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/evkmimxrt1180_cm7.jlinkscript @@ -0,0 +1,1041 @@ +__constant U32 _INDEX_AHB_AP_CORTEX_M33 = 3; +__constant U32 _AHB_ACC_32BIT_AUTO_INC = (1 << 29) | (1 << 25) | (1 << 24) | (1 << 4) | (2 << 0); +__constant U32 _AHB_ACC_16BIT_AUTO_INC = (1 << 29) | (1 << 25) | (1 << 24) | (1 << 4) | (1 << 0); // HMASTER = DEBUG, Private access, no Auto-increment, Access size: half word; +__constant U32 _ACCESS_AP = 1; +__constant U32 _CM33_CPUID = 0xD210; +__constant U32 _CM7_CPUID = 0x0C27; + +/* ROM trap address for CM33 core, after system reset */ +__constant U32 _ROM_TRAP0_ADDR = 0x10002932; +__constant U32 _ROM_TRAP1_ADDR = 0x100025D4; +__constant U32 _ROM_TRAP2_ADDR = 0x100025D4; + +__constant U32 _SRC_SRSR_ADDR = 0x44460050; +__constant U32 _SRC_SRMASK_ADDR = 0x44460018; +__constant U32 _SRC_SCR_ADDR = 0x44460010; +__constant U32 _SRC_AUTHEN_CTRL_ADDR = 0x44460004; +__constant U32 _SRC_SBMR2_ADDR = 0x44460044; +__constant U32 _BLK_M7_CFG_ADDR = 0x444F0080; + +__constant U32 _DWT_COMP0_ADDR = 0xE0001020; +__constant U32 _DWT_FUNC0_ADDR = 0xE0001028; + +__constant U32 _DCB_DHCSR_ADDR = 0xE000EDF0; +__constant U32 _DCB_DEMCR_ADDR = 0xE000EDFC; + +__constant U32 _SCB_AIRCR_ADDR = 0xE000ED0C; + +__constant U32 _XCACHE_PC_CCR_ADDR = 0x44400000; +__constant U32 _XCACHE_PS_CCR_ADDR = 0x44400800; + +__constant U32 _CM33_MPU_CTRL_ADDR = 0xE000ED94; + +__constant U32 _SI_VER_ADDR = 0x5751804C; + +unsigned int cpuID; +unsigned int rom_trap_addr; + +static int _WriteViaCM33AP16(U32 Addr, U16 Data) { + int r; + + JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 4) | (_INDEX_AHB_AP_CORTEX_M33 << 24)); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL, _AHB_ACC_16BIT_AUTO_INC); + Data = (Data & 0xFFFF) | ((Data & 0xFFFF) << 16); + r = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, Addr); + r |= JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, Data); + return r; +} + +static U32 _ReadViaCM33AP16(U32 Addr) { + U32 r; + + JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 4) | (_INDEX_AHB_AP_CORTEX_M33 << 24)); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL, _AHB_ACC_16BIT_AUTO_INC); + JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, Addr); + JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, &r); + return r; +} + +static int _WriteViaCM33AP32(U32 Addr, U32 Data) { + int r; + + JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 4) | (_INDEX_AHB_AP_CORTEX_M33 << 24)); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL, _AHB_ACC_32BIT_AUTO_INC); + r = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, Addr); + r |= JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, Data); + return r; +} + +static U32 _ReadViaCM33AP32(U32 Addr) { + int r; + + JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 4) | (_INDEX_AHB_AP_CORTEX_M33 << 24)); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL, _AHB_ACC_32BIT_AUTO_INC); + r = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, Addr); + r |= JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, &r); + return r; +} + +/* For Debug Start */ +__constant U32 _DCB_DCRSR_ADDR = 0xE000EDF4; +__constant U32 _DCB_DCRDR_ADDR = 0xE000EDF8; +__constant U32 _SCB_DFSR_ADDR = 0xE000ED30; + +__constant U32 _REG_R0 = 0x0; +__constant U32 _REG_R1 = 0x1; +__constant U32 _REG_R2 = 0x2; +__constant U32 _REG_R3 = 0x3; +__constant U32 _REG_R4 = 0x4; +__constant U32 _REG_R5 = 0x5; +__constant U32 _REG_R6 = 0x6; +__constant U32 _REG_R7 = 0x7; +__constant U32 _REG_R8 = 0x8; +__constant U32 _REG_R9 = 0x9; +__constant U32 _REG_R10 = 0xA; +__constant U32 _REG_R11 = 0xB; +__constant U32 _REG_R12 = 0xC; +__constant U32 _REG_SP = 0xD; +__constant U32 _REG_LR = 0xE; +__constant U32 _REG_PC = 0xF; +__constant U32 _REG_SP_main = 0x11; +__constant U32 _REG_SP_process = 0x12; +__constant U32 _REG_MSPLIM_S = 0x1C; +__constant U32 _REG_PSPLIM_S = 0x1D; +__constant U32 _REG_MSPLIM_NS = 0x1E; +__constant U32 _REG_PSPLIM_NS = 0x1F; + +static U32 _ReadCPUReg(int RegIndex) { + U32 v; + + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_ADDR, _DCB_DCRSR_ADDR); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_DATA, RegIndex); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_ADDR, _DCB_DCRDR_ADDR); + v = JLINK_CORESIGHT_ReadAP(JLINK_CORESIGHT_AP_REG_DATA); + return v; +} + +static U32 _ReadCPURegViaAP(int AP, int RegIndex) { + int r; + + JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 4) | (AP << 24)); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL, _AHB_ACC_32BIT_AUTO_INC); + + r = _ReadCPUReg(RegIndex); + return r; +} + +int debug = 0; + +void ShowDAPInfo(void) +{ + int r; + + if ( debug ) + { + JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 4) | (_INDEX_AHB_AP_CORTEX_M33 << 24)); + r = JLINK_CORESIGHT_ReadAP(JLINK_CORESIGHT_AP_REG_CTRL); + JLINK_SYS_Report1("CM33 AP CSW = ", r); + } +} + +void DBG_ShowCM33Reg(void) +{ + int r, sp, pc; + + r = _ReadViaCM33AP32(_CM33_MPU_CTRL_ADDR); + JLINK_SYS_Report1(" CM33 MPU_CTRL = ", r); + r = _ReadViaCM33AP32(_XCACHE_PC_CCR_ADDR); + JLINK_SYS_Report1(" XCACHE_PC_CCR = ", r); + r = _ReadViaCM33AP32(_XCACHE_PS_CCR_ADDR); + JLINK_SYS_Report1(" XCACHE_PS_CCR = ", r); + + r = _ReadViaCM33AP32(_DWT_COMP0_ADDR); + JLINK_SYS_Report1(" CM33 DWT_COMP0 = ", r); + r = _ReadViaCM33AP32(_DWT_FUNC0_ADDR); + JLINK_SYS_Report1(" CM33 DWT_FUNC0 = ", r); + + r = _ReadViaCM33AP32(_SCB_DFSR_ADDR); + JLINK_SYS_Report1(" CM33 DFSR = ", r); + r = _ReadViaCM33AP32(_DCB_DEMCR_ADDR); + JLINK_SYS_Report1(" CM33 DEMCR = ", r); + r = _ReadViaCM33AP32(_DCB_DHCSR_ADDR); + JLINK_SYS_Report1(" CM33 DHCSR = ", r); + if ( (r & 0x02) != 0) + { + sp = _ReadCPURegViaAP(_INDEX_AHB_AP_CORTEX_M33, _REG_SP); + pc = _ReadCPURegViaAP(_INDEX_AHB_AP_CORTEX_M33, _REG_PC); + JLINK_SYS_Report1(" CM33 PC = ", pc); + JLINK_SYS_Report1(" CM33 SP = ", sp); + } + else + { + JLINK_SYS_Report(" CM33 core is not halted!"); + } +} + +void DBG_ShowCoreReg(void) +{ + int r, sp, pc; + + r = JLINK_MEM_ReadU32(_SCB_DFSR_ADDR); + JLINK_SYS_Report1(" DFSR = ", r); + r = JLINK_MEM_ReadU32(_DCB_DHCSR_ADDR); + JLINK_SYS_Report1(" DHCSR = ", r); + if ( (r & 0x02) != 0) + { + sp = _ReadCPUReg(_REG_SP); + pc = _ReadCPUReg(_REG_PC); + JLINK_SYS_Report1(" PC = ", pc); + JLINK_SYS_Report1(" SP = ", sp); + } + else + { + JLINK_SYS_Report(" Core is not halted!"); + } +} + +void DBG_ShowReg(int seq) +{ + int r; + if( debug ) + { + JLINK_SYS_Report1("Seq: ", seq); + + r = _ReadViaCM33AP32(_SRC_AUTHEN_CTRL_ADDR); + JLINK_SYS_Report1(" AUTHEN_CTRL = ", r); + r = _ReadViaCM33AP32(_SRC_SRSR_ADDR); + JLINK_SYS_Report1(" SRSR = ", r); + r = _ReadViaCM33AP32(_SRC_SRMASK_ADDR); + JLINK_SYS_Report1(" SRMASK = ", r); + r = _ReadViaCM33AP32(_SRC_SCR_ADDR); + JLINK_SYS_Report1(" SCR = ", r); + r = _ReadViaCM33AP32(_BLK_M7_CFG_ADDR); + JLINK_SYS_Report1(" M7_CFG = ", r); + + if(cpuID == _CM7_CPUID) + { + if((r & 0x10) == 0) + { + DBG_ShowCoreReg(); + } + + } + + DBG_ShowCM33Reg(); + } +} +/* For Debug End */ + +void _FLEXSPI1_ModuleReset() +{ + unsigned int reg; + + reg = MEM_ReadU32(0x425E0000); // FlexSPI1->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + reg = MEM_ReadU32(0x425E0000); + MEM_WriteU32(0x425E0000, (reg | 0x1)); + do + { + reg = MEM_ReadU32(0x425E0000); + } while ((reg & 0x1) != 0); + } +} + +void _FLEXSPI1_WaitBusIdle() +{ + unsigned int reg; + reg = MEM_ReadU32(0x425E0000); // FlexSPI1->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + do + { + reg = MEM_ReadU32(0x425E00E0); + } while ((reg & 0x3) != 0x3); + } +} + +void _FLEXSPI1_ClockInit() +{ + _WriteViaCM33AP32(0x54484350, 0x0); // ROSC400M_CTRL1 + + // Set flexspi1 root clock, use ROSC400, div = 4 = 1+3 + MEM_WriteU32(0x54450A80, 0x103); // CLOCK_ROOT[21].CONTROL, FlexSPI1 +} + +void _FLEXSPI1_SetPinForQuadMode(void) { + // Set 4 Pin Mode for JLink + // IOMUXC_GPIO_B2_07_FLEXSPI1_BUS2BIT_A_DQS + MEM_WriteU32(0x42A1023C, 0x17); + MEM_WriteU32(0x42A10544, 0x1); + // IOMUXC_GPIO_B2_08_FLEXSPI1_BUS2BIT_A_SCLK + MEM_WriteU32(0x42A10240, 0x17); + // IOMUXC_GPIO_B2_09_FLEXSPI1_BUS2BIT_A_SS0_B + MEM_WriteU32(0x42A10244, 0x17); + // IOMUXC_GPIO_B2_10_FLEXSPI1_BUS2BIT_A_DATA00 + MEM_WriteU32(0x42A10248, 0x17); + // IOMUXC_GPIO_B2_11_FLEXSPI1_BUS2BIT_A_DATA01 + MEM_WriteU32(0x42A1024C, 0x17); + // IOMUXC_GPIO_B2_12_FLEXSPI1_BUS2BIT_A_DATA02 + MEM_WriteU32(0x42A10250, 0x17); + // IOMUXC_GPIO_B2_13_FLEXSPI1_BUS2BIT_A_DATA03 + MEM_WriteU32(0x42A10254, 0x17); +} + +void _FLEXSPI1_ModuleInit(void) { + + unsigned int reg; + reg = MEM_ReadU32(0x425E0000); + MEM_WriteU32(0x425E0000, (reg & 0xFFFFFFFD)); + + //FLEXSPI1->MCR0 = 0xFFFF8010; + MEM_WriteU32(0x425E0000, 0xFFFF8010); + //FLEXSPI1->MCR2 = 0x200001F7; + MEM_WriteU32(0x425E0008, 0x200001F7); + //FLEXSPI1->AHBCR = 0x78; + MEM_WriteU32(0x425E000C, 0x78); + + //FLEXSPI1->FLSHCR0[0] = 0x00004000; + MEM_WriteU32(0x425E0060, 0x00004000); + + + //FLEXSPI1->FLSHCR4 = 0xC3; + MEM_WriteU32(0x425E0094, 0xC3); + //FLEXSPI1->IPRXFCR = 0x1C; + MEM_WriteU32(0x425E00B8, 0x1C); + + //FLEXSPI1->LUTKEY = 0x5AF05AF0UL; + MEM_WriteU32(0x425E0018, 0x5AF05AF0); + //FLEXSPI1->LUTCR = 0x02; + MEM_WriteU32(0x425E001C, 0x02); + + //FLEXSPI1->LUT[0] = 0x0A1804EB; // AHB Quad Read Change to use Fast Read Quad + MEM_WriteU32(0x425E0200, 0x0A1804EB); + //FLEXSPI1->LUT[1] = 0x26043206; + MEM_WriteU32(0x425E0204, 0x26043206); + //FLEXSPI1->LUT[2] = 0x00000000; + MEM_WriteU32(0x425E0208, 0x00000000); + //FLEXSPI1->LUT[3] = 0x00000000; + MEM_WriteU32(0x425E020C, 0x00000000); + + //FLEXSPI1->LUT[4] = 0x00000406; // Write Enable + MEM_WriteU32(0x425E0210, 0x00000406); + //FLEXSPI1->LUT[5] = 0x00000000; + MEM_WriteU32(0x425E0214, 0x00000000); + //FLEXSPI1->LUT[6] = 0x00000000; + MEM_WriteU32(0x425E0218, 0x00000000); + //FLEXSPI1->LUT[7] = 0x00000000; + MEM_WriteU32(0x425E021C, 0x00000000); + + //FLEXSPI1->LUT[8] = 0x20040401; // Wirte s1 + MEM_WriteU32(0x425E0220, 0x20040401); + //FLEXSPI1->LUT[9] = 0x00000000; + MEM_WriteU32(0x425E0224, 0x00000000); + //FLEXSPI1->LUT[10] = 0x00000000; + MEM_WriteU32(0x425E0228, 0x00000000); + //FLEXSPI1->LUT[11] = 0x00000000; + MEM_WriteU32(0x425E022C, 0x00000000); + + //FLEXSPI1->LUT[12] = 0x24040405; // Read s1 + MEM_WriteU32(0x425E0230, 0x24040405); + //FLEXSPI1->LUT[13] = 0x00000000; + MEM_WriteU32(0x425E0234, 0x00000000); + //FLEXSPI1->LUT[14] = 0x00000000; + MEM_WriteU32(0x425E0238, 0x00000000); + //FLEXSPI1->LUT[15] = 0x00000000; + MEM_WriteU32(0x425E023C, 0x00000000); + + //FLEXSPI1->LUT[16] = 0x00000404; // Write Disable + MEM_WriteU32(0x425E0240, 0x00000404); + //FLEXSPI1->LUT[17] = 0x00000000; + MEM_WriteU32(0x425E0244, 0x00000000); + //FLEXSPI1->LUT[18] = 0x00000000; + MEM_WriteU32(0x425E0248, 0x00000000); + //FLEXSPI1->LUT[19] = 0x00000000; + MEM_WriteU32(0x425E024C, 0x00000000); + + //FLEXSPI1->LUT[20] = 0x20040431; // Wirte s2 + MEM_WriteU32(0x425E0250, 0x20040431); + //FLEXSPI1->LUT[21] = 0x00000000; + MEM_WriteU32(0x425E0254, 0x00000000); + //FLEXSPI1->LUT[22] = 0x00000000; + MEM_WriteU32(0x425E0258, 0x00000000); + //FLEXSPI1->LUT[23] = 0x00000000; + MEM_WriteU32(0x425E025C, 0x00000000); + + //FLEXSPI1->LUT[24] = 0x24040435; // Read s2 + MEM_WriteU32(0x425E0260, 0x24040435); + //FLEXSPI1->LUT[25] = 0x00000000; + MEM_WriteU32(0x425E0264, 0x00000000); + //FLEXSPI1->LUT[26] = 0x00000000; + MEM_WriteU32(0x425E0268, 0x00000000); + //FLEXSPI1->LUT[27] = 0x00000000; + MEM_WriteU32(0x425E026C, 0x00000000); + + //FLEXSPI1->LUT[28] = 0x00000450; // Write Enable Volatile + MEM_WriteU32(0x425E0270, 0x00000450); + //FLEXSPI1->LUT[29] = 0x00000000; + MEM_WriteU32(0x425E0274, 0x00000000); + //FLEXSPI1->LUT[30] = 0x00000000; + MEM_WriteU32(0x425E0278, 0x00000000); + //FLEXSPI1->LUT[31] = 0x00000000; + MEM_WriteU32(0x425E027C, 0x00000000); + + //FLEXSPI1->LUTKEY = 0x5AF05AF0UL; + MEM_WriteU32(0x425E0018, 0x5AF05AF0); + //FLEXSPI1->LUTCR = 0x01; + MEM_WriteU32(0x425E001C, 0x01); +} + +void _FLEXSPI2_ModuleReset() +{ + unsigned int reg; + + reg = MEM_ReadU32(0x445E0000); // FlexSPI2->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + reg = MEM_ReadU32(0x445E0000); + MEM_WriteU32(0x445E0000, (reg | 0x1)); + do + { + reg = MEM_ReadU32(0x445E0000); + } while ((reg & 0x1) != 0); + } +} + +void _FLEXSPI2_WaitBusIdle() +{ + unsigned int reg; + + reg = MEM_ReadU32(0x445E0000); // FlexSPI2->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + do + { + reg = MEM_ReadU32(0x445E00E0); + } while ((reg & 0x3) != 0x3); + } +} + +void _FlexSPI2_SetPinForOctalMode() +{ + // Config IOMUX for FlexSPI2 + MEM_WriteU32(0x42A10088, 0x00000013); // FLEXSPI2_B_DATA03 + MEM_WriteU32(0x42A1008C, 0x00000013); // FLEXSPI2_B_DATA02 + MEM_WriteU32(0x42A10090, 0x00000013); // FLEXSPI2_B_DATA01 + MEM_WriteU32(0x42A10094, 0x00000013); // FLEXSPI2_B_DATA00 + MEM_WriteU32(0x42A1009C, 0x00000013); // FLEXSPI2_A_DATA00 + MEM_WriteU32(0x42A100A0, 0x00000013); // FLEXSPI2_A_DATA01 + MEM_WriteU32(0x42A100A4, 0x00000013); // FLEXSPI2_A_DATA02 + MEM_WriteU32(0x42A100A8, 0x00000013); // FLEXSPI2_A_DATA03 + MEM_WriteU32(0x42A100AC, 0x00000013); // FLEXSPI2_A_SS0_B + MEM_WriteU32(0x42A100B0, 0x00000013); // FLEXSPI2_A_DQS + MEM_WriteU32(0x42A100B4, 0x00000013); // FLEXSPI2_A_SCLK + + //The input daisy!! + MEM_WriteU32(0x42A10594, 0x00000001); // FLEXSPI2_B_DATA03 + MEM_WriteU32(0x42A10590, 0x00000001); // FLEXSPI2_B_DATA02 + MEM_WriteU32(0x42A1058C, 0x00000001); // FLEXSPI2_B_DATA01 + MEM_WriteU32(0x42A10588, 0x00000001); // FLEXSPI2_B_DATA00 + MEM_WriteU32(0x42A10578, 0x00000000); // FLEXSPI2_A_DATA00 + MEM_WriteU32(0x42A1057C, 0x00000000); // FLEXSPI2_A_DATA01 + MEM_WriteU32(0x42A10580, 0x00000000); // FLEXSPI2_A_DATA02 + MEM_WriteU32(0x42A10584, 0x00000000); // FLEXSPI2_A_DATA03 + MEM_WriteU32(0x42A10570, 0x00000000); // FLEXSPI2_A_DQS + MEM_WriteU32(0x42A10598, 0x00000000); // FLEXSPI2_A_SCLK + + // PAD ctrl + MEM_WriteU32(0x42A102D0, 0x00000008); // FLEXSPI2_B_DATA03 + MEM_WriteU32(0x42A102D4, 0x00000008); // FLEXSPI2_B_DATA02 + MEM_WriteU32(0x42A102D8, 0x00000008); // FLEXSPI2_B_DATA01 + MEM_WriteU32(0x42A102DC, 0x00000008); // FLEXSPI2_B_DATA00 + MEM_WriteU32(0x42A102E4, 0x00000008); // FLEXSPI2_A_DATA00 + MEM_WriteU32(0x42A102E8, 0x00000008); // FLEXSPI2_A_DATA01 + MEM_WriteU32(0x42A102EC, 0x00000008); // FLEXSPI2_A_DATA02 + MEM_WriteU32(0x42A102F0, 0x00000008); // FLEXSPI2_A_DATA03 + MEM_WriteU32(0x42A102F4, 0x00000008); // FLEXSPI2_A_SS0_B + MEM_WriteU32(0x42A102F8, 0x00000008); // FLEXSPI2_A_DQS + MEM_WriteU32(0x42A102FC, 0x00000008); // FLEXSPI2_A_SCLK +} + +void _FLEXSPI2_ClockInit() +{ + _WriteViaCM33AP32(0x54484350, 0x0); // ROSC400M_CTRL1 + + // Set flexspi2 root clock, use ROSC400, div = 2 = 1+1 + MEM_WriteU32(0x44450B00, 0x101); // CLOCK_ROOT[22].CONTROL, FlexSPI2 +} + +void _FLEXSPI2_ModuleInit() +{ + // Config FlexSPI2 Registers + + unsigned int reg; + reg = MEM_ReadU32(0x445E0000); + MEM_WriteU32(0x445E0000, (reg & 0xFFFFFFFD)); + + _FLEXSPI2_ModuleReset(); + + MEM_WriteU32(0x445E0000, 0xFFFF3032); // MCR0 + MEM_WriteU32(0x445E0004, 0xFFFFFFFF); // MCR1 + MEM_WriteU32(0x445E0008, 0x200001F7); // MCR2 + MEM_WriteU32(0x445E000C, 0x00000078); // AHBCR prefetch enable + MEM_WriteU32(0x445E0020, 0x800F0000); // AHBRXBUF0CR0 + MEM_WriteU32(0x445E0024, 0x800F0000); // AHBRXBUF1CR0 + MEM_WriteU32(0x445E0028, 0x800F0000); // AHBRXBUF2CR0 + MEM_WriteU32(0x445E002C, 0x800F0000); // AHBRXBUF3CR0 + MEM_WriteU32(0x445E0030, 0x800F0000); // AHBRXBUF4CR0 + MEM_WriteU32(0x445E0034, 0x800F0000); // AHBRXBUF5CR0 + MEM_WriteU32(0x445E0038, 0x80000020); // AHBRXBUF6CR0 + MEM_WriteU32(0x445E003C, 0x80000020); // AHBRXBUF7CR0 + MEM_WriteU32(0x445E00B8, 0x00000000); // IPRXFCR + MEM_WriteU32(0x445E00BC, 0x00000000); // IPTXFCR + + MEM_WriteU32(0x445E0060, 0x00000000); // FLASHA1CR0 + MEM_WriteU32(0x445E0064, 0x00000000); // FLASHA2CR0 + MEM_WriteU32(0x445E0068, 0x00000000); // FLASHB1CR0 + MEM_WriteU32(0x445E006C, 0x00000000); // FLASHB2CR0 + + _FLEXSPI2_WaitBusIdle(); + + MEM_WriteU32(0x445E0060, 0x00002000); // FLASHA1CR0 + MEM_WriteU32(0x445E0070, 0x00021C63); // FLASHA1CR1 + MEM_WriteU32(0x445E0080, 0x00000100); // FLASHA1CR2 + + _FLEXSPI2_WaitBusIdle(); + + MEM_WriteU32(0x445E00C0, 0x00000079); // DLLCRA + MEM_WriteU32(0x445E0000, 0xFFFF3030); // MCR0 + + do + { + reg = MEM_ReadU32(0x445E00E8); + } while (0x3 != (reg & 0x3)); + JLINK_SYS_Sleep(1); + // __delay(100);//100us + + MEM_WriteU32(0x445E0000, 0xFFFF3032); // MCR0 + MEM_WriteU32(0x445E0094, 0x000000C2); // FLASHCR4 + MEM_WriteU32(0x445E0094, 0x000000C6); // FLASHCR4 + MEM_WriteU32(0x445E0000, 0xFFFF3030); // MCR0 + + _FLEXSPI2_WaitBusIdle(); + + MEM_WriteU32(0x445E0018, 0x5AF05AF0); // LUTKEY + MEM_WriteU32(0x445E001C, 0x00000002); // LUTCR + MEM_WriteU32(0x445E0200, 0x8B1887A0); // LUT[0] + MEM_WriteU32(0x445E0204, 0xB7078F10); // LUT[1] + MEM_WriteU32(0x445E0208, 0x0000A704); // LUT[2] + MEM_WriteU32(0x445E020C, 0x00000000); // LUT[3] + MEM_WriteU32(0x445E0210, 0x8B188720); // LUT[4] + MEM_WriteU32(0x445E0214, 0xB7078F10); // LUT[5] + MEM_WriteU32(0x445E0218, 0x0000A304); // LUT[6] + MEM_WriteU32(0x445E021C, 0x00000000); // LUT[7] + MEM_WriteU32(0x445E0220, 0x8B1887E0); // LUT[8] + MEM_WriteU32(0x445E0224, 0xB7078F10); // LUT[9] + MEM_WriteU32(0x445E0228, 0x0000A704); // LUT[10] + MEM_WriteU32(0x445E022C, 0x00000000); // LUT[11] + MEM_WriteU32(0x445E0230, 0x8B188760); // LUT[12] + MEM_WriteU32(0x445E0234, 0xA3028F10); // LUT[13] + MEM_WriteU32(0x445E0238, 0x00000000); // LUT[14] + MEM_WriteU32(0x445E023C, 0x00000000); // LUT[15] + MEM_WriteU32(0x445E0240, 0x00000000); // LUT[16] + MEM_WriteU32(0x445E0244, 0x00000000); // LUT[17] + MEM_WriteU32(0x445E0248, 0x00000000); // LUT[18] + MEM_WriteU32(0x445E024C, 0x00000000); // LUT[19] + MEM_WriteU32(0x445E0018, 0x5AF05AF0); // LUTKEY + MEM_WriteU32(0x445E001C, 0x00000001); // LUTCR + + /* Restore hyperram CR0 register */ + MEM_WriteU32(0x445E00A0, 0x00001000); // IPCR0 + MEM_WriteU32(0x445E00A4, 0x00030002); // IPCR1 + MEM_WriteU32(0x445E00BC, 0x00000001); // IPTXFCR + MEM_WriteU32(0x445E0180, 0x2F8F2F8F); // TFDR 0x8F2F is default value of W756/7x of CR0 + MEM_WriteU32(0x445E0014, 0x00000040); // INTR + MEM_WriteU32(0x445E00B0, 0x00000001); // IPCMD + do + { + reg = MEM_ReadU32(0x445E0014); // INTR + } while ((reg & 0x1) == 0x0); + MEM_WriteU32(0x445E0014, 0x00000001); // INTR + + /* Restore hyperram CR1 register */ + MEM_WriteU32(0x445E00A0, 0x00001002); // IPCR0 + MEM_WriteU32(0x445E00A4, 0x00030002); // IPCR1 + MEM_WriteU32(0x445E00BC, 0x00000001); // IPTXFCR + MEM_WriteU32(0x445E0180, 0xC1FFC1FF); // TFDR 0xFFC1 is default value of W756/7x of CR1 + MEM_WriteU32(0x445E0014, 0x00000040); // INTR + MEM_WriteU32(0x445E00B0, 0x00000001); // IPCMD + do + { + reg = MEM_ReadU32(0x445E0014); // INTR + } while ((reg & 0x1) == 0x0); + MEM_WriteU32(0x445E0014, 0x00000001); // INTR + + _FLEXSPI2_ModuleReset(); +} + +void CM7_InitTCM(U32 targetAddr, U32 size) { + U32 reg; + + reg = _ReadViaCM33AP32(0x52010000); // DMA4->TDC[0].CH_CSR + + if((reg & 0x80000000) != 0) + { + // DMA channel is active, wait it get finished + do + { + reg = _ReadViaCM33AP32(0x52010000); // DMA4->TDC[0].CH_CSR + } while((reg & 0x40000000) == 0); + } + + _WriteViaCM33AP32(0x52010000, 0x40000000); // DMA4->TDC[0].CH_CSR, clear DONE flag + + _WriteViaCM33AP32(0x5201002C, 0x00000000); // DMA4->TCD[0].SLAST_SGA + _WriteViaCM33AP32(0x52010038, 0x00000000); // DMA4->TCD[0].DLAST_SGA + + _WriteViaCM33AP32(0x52010000, 0x40000000); // DMA4->TCD[0].CH_CSR + + _WriteViaCM33AP32(0x52010020, 0x20484000); // DMA4->TCD[0].SADDR + _WriteViaCM33AP32(0x52010030, targetAddr); // DMA4->TCD[0].DADDR + _WriteViaCM33AP32(0x52010028, size); // DMA4->TCD[0].NBYTES_MLOFFNO + _WriteViaCM33AP16(0x52010036, 0x1); // DMA4->TCD[0].ELINKNO + _WriteViaCM33AP16(0x5201003E, 0x1); // DMA4->TCD[0].BITER_ELINKNO + _WriteViaCM33AP16(0x52010026, 0x0303); // DMA4->TCD[0].ATTR + _WriteViaCM33AP16(0x52010024, 0x0); // DMA4->TCD[0].SOFF + _WriteViaCM33AP16(0x52010034, 0x8); // DMA4->TCD[0].DOFF + _WriteViaCM33AP32(0x52010000, 0x7); // DMA4->TDC[0].CH_CSR + _WriteViaCM33AP16(0x5201003C, 0x8); // DMA4->TCD[0].CSR + _WriteViaCM33AP16(0x5201003C, 0x9); // DMA4->TCD[0].CSR + + do + { + reg = _ReadViaCM33AP32(0x52010000); // DMA4->TDC[0].CH_CSR + } while((reg & 0x40000000) == 0); + _WriteViaCM33AP32(0x52010000, 0x40000000); // DMA4->TDC[0].CH_CSR, clear DONE flag +} + +void CM7_KickOff(int ecc_init) +{ + U32 reg, resp1, resp2; + + reg = _ReadViaCM33AP32(_BLK_M7_CFG_ADDR); + if((reg & 0x10) == 0) + { + JLINK_SYS_Report("CM7 is running already"); + } + else + { + JLINK_SYS_Report("************* Begin Operations to Enable CM7 ***********************"); + + // Clock Preparation + JLINK_SYS_Report("******** Prepare Clock *********"); + _WriteViaCM33AP32(0x54484350, 0x0); // ROSC400M_CTRL1 + _WriteViaCM33AP32(0x54450000, 0x100); // CLOCK_ROOT[0].CONTROL, CM7 + + // Release CM7 + _WriteViaCM33AP32(_SRC_SCR_ADDR, 0x1); + + if (ecc_init) + { + // DMA initialization + JLINK_SYS_Report("******** DMA operation *********"); + CM7_InitTCM(0x303C0000, 0x40000); + CM7_InitTCM(0x30400000, 0x40000); + } + + // Making Landing Zone + JLINK_SYS_Report("******** Creating Landing Zone *********"); + _WriteViaCM33AP32(0x303C0000, 0x20020000); + _WriteViaCM33AP32(0x303C0004, 0x00000009); + _WriteViaCM33AP32(0x303C0008, 0xE7FEE7FE); + + // VTOR 0x00 + _WriteViaCM33AP32(_BLK_M7_CFG_ADDR, 0x0010); + + // Trigger ELE + JLINK_SYS_Report("******** ELE Trigger *********"); + _WriteViaCM33AP32(0x57540200, 0x17d20106); // MU_RT_S3MUA->TR[0] + resp1 = _ReadViaCM33AP32(0x57540280); // MU_RT_S3MUA->RR[0] + resp2 = _ReadViaCM33AP32(0x57540284); // MU_RT_S3MUA->RR[1] + JLINK_SYS_Report1("ELE RESP1 : ", resp1); + JLINK_SYS_Report1("ELE RESP2 : ", resp2); + + // Deassert CM7 Wait + JLINK_SYS_Report("******** Kickoff CM7 *********"); + _WriteViaCM33AP32(_BLK_M7_CFG_ADDR, 0x0); + } +} + +void DAP_Init(void) +{ + JLINK_CORESIGHT_Configure(""); + + CORESIGHT_AddAP(0, CORESIGHT_AHB_AP); + CORESIGHT_AddAP(1, CORESIGHT_APB_AP); + CORESIGHT_AddAP(2, CORESIGHT_AHB_AP); + CORESIGHT_AddAP(3, CORESIGHT_AHB_AP); + CORESIGHT_AddAP(4, CORESIGHT_APB_AP); + CORESIGHT_AddAP(5, CORESIGHT_APB_AP); + CORESIGHT_AddAP(6, CORESIGHT_APB_AP); + + JLINK_SYS_Report("***************************************************"); + if(cpuID == _CM7_CPUID) + { + CPU = CORTEX_M7; + CORESIGHT_IndexAHBAPToUse = 2; + JLINK_SYS_Report("Current core is CM7"); + } + else if(cpuID == _CM33_CPUID) + { + CPU = CORTEX_M33; + CORESIGHT_IndexAHBAPToUse = 3; + JLINK_SYS_Report("Current core is CM33"); + + ShowDAPInfo(); + CORESIGHT_AHBAPCSWDefaultSettings = (1<<29)|(1<<25)|(1<<24); + } + else + { + JLINK_SYS_Report1("Wrong CPU ID: ", cpuID); + } + JLINK_SYS_Report("***************************************************"); +} + +void CM33_Halt(void) +{ + U32 reg; + + reg = (_ReadViaCM33AP32(_SRC_SBMR2_ADDR) >> 24) & 0x3F; + + if((reg == 8) || (reg == 9)) // Serial Download Mode, or Boot From Fuse + { + JLINK_SYS_Report("Not flash execution mode, check if CM33 is halted..."); + + reg = _ReadViaCM33AP32(_DCB_DHCSR_ADDR); + + if(0 == (reg & 0x02)) + { + JLINK_SYS_Report1("CM33 is not halted, trying to halt it. CM33 DHCSR: ", reg); + + _WriteViaCM33AP32(_DCB_DHCSR_ADDR, 0xA05F0001); // Enable CM33 debug control + _WriteViaCM33AP32(_DCB_DHCSR_ADDR, 0xA05F0003); // Halt CM33 + reg = _ReadViaCM33AP32(_DCB_DHCSR_ADDR); + if(0 != (reg & 0x02)) + { + JLINK_SYS_Report1("CM33 is halted now. CM33 DHCSR: ", reg); + } + else + { + JLINK_SYS_Report1("CM33 still running, halt failed. CM33 DHCSR: ", reg); + } + } + else + { + JLINK_SYS_Report1("CM33 is halted. CM33 DHCSR: ", reg); + } + } + else + { + JLINK_SYS_Report("Flash execution mode, leave CM33 run status as it was..."); + } +} + +void Flash_Init() { + JLINK_SYS_Report("***************************************************"); + JLINK_SYS_Report("Init Flash"); + + _FLEXSPI1_WaitBusIdle(); + _FLEXSPI1_ModuleReset(); + + _FLEXSPI1_SetPinForQuadMode(); + _FLEXSPI1_ClockInit(); + _FLEXSPI1_ModuleInit(); + + JLINK_SYS_Report("***************************************************"); +} + +void HyperRAM_Init() +{ + JLINK_SYS_Report("***************************************************"); + JLINK_SYS_Report("Init HyperRAM"); + + _FLEXSPI2_WaitBusIdle(); + _FLEXSPI2_ModuleReset(); + + _FlexSPI2_SetPinForOctalMode(); + _FLEXSPI2_ClockInit(); + _FLEXSPI2_ModuleInit(); + + JLINK_SYS_Report("***************************************************"); +} + +void CM33_ClearNVIC(void) { + JLINK_SYS_Report("***************************************************"); + JLINK_SYS_Report("Clear NVIC"); + JLINK_SYS_Report("***************************************************"); + JLINK_MEM_Fill(0xE000E180, 0x40, 0xFF); + JLINK_MEM_Fill(0xE000E280, 0x40, 0xFF); +} + +int InitTarget(void) +{ + int r; + cpuID = _CM7_CPUID; + + DAP_Init(); + + if(cpuID == _CM7_CPUID) + { + CM33_Halt(); + CM7_KickOff(1); + + /* Avoid to access TPIU to prevent soc hang */ + JLINK_ExecCommand("map region 0xE0040000-0xE0040FFF X"); // Mark region as illegal + } + + r = _ReadViaCM33AP32(_SI_VER_ADDR) & 0xF; + + if ( r == 1 ) + { + rom_trap_addr = _ROM_TRAP1_ADDR; + } + else if ( r == 2 ) + { + rom_trap_addr = _ROM_TRAP2_ADDR; + } + else + { + rom_trap_addr = _ROM_TRAP0_ADDR; + } + JLINK_SYS_Report1("SI_VER = ", r); + JLINK_SYS_Report1("TRAP = ", rom_trap_addr); + + return 0; +} + +int SetupTarget(void) +{ + return 0; +} + +void ResetTarget_CM33(void) +{ + int r, w; + int comp, func; + int core_reset_request_bit_mask; + + core_reset_request_bit_mask = 0x100; /* for CM33 core */ + + DBG_ShowReg(0); + + /* Halt the CPU and wait sometime for possible peripheral operation finish */ + JLINK_TARGET_Halt(); + JLINK_SYS_Sleep(10); + + r = JLINK_TARGET_IsHalted(); + if (r != 1) + { + JLINK_SYS_Report("ERR: CM33 core can't be halted!"); + } + + DBG_ShowReg(1); + + /* check and enable core request system reset */ + r = JLINK_MEM_ReadU32(_SRC_SRMASK_ADDR); + if ( (r & core_reset_request_bit_mask) != 0 ) + { + if ( (r & (core_reset_request_bit_mask<<16)) == 0 ) + { + w = r & (~core_reset_request_bit_mask); + r = JLINK_MEM_ReadU32(_SRC_AUTHEN_CTRL_ADDR); + if ( (r & 0x80) == 0 ) + { + JLINK_SYS_Report("Enable system reset via CM33 core reset"); + JLINK_MEM_WriteU32(_SRC_SRMASK_ADDR, w); + ShowDAPInfo(); + } + else + { + JLINK_SYS_Report("ERR: Core reset request is masked and all mask are locked!"); + } + } + else + { + JLINK_SYS_Report("ERR: Core reset request is masked and locked!"); + } + } + + DBG_ShowReg(2); + + JLINK_SYS_Report("Set CM33 watch point"); + comp = JLINK_MEM_ReadU32(_DWT_COMP0_ADDR); /* Save the DWT register and restore them later */ + func = JLINK_MEM_ReadU32(_DWT_FUNC0_ADDR); + JLINK_MEM_WriteU32(_DWT_COMP0_ADDR, rom_trap_addr); + JLINK_MEM_WriteU32(_DWT_FUNC0_ADDR, 0x00000412); + + /* Clear the reset status to avoid ROM clean the core TCM after reset */ + r = JLINK_MEM_ReadU32(_SRC_SRSR_ADDR); + JLINK_MEM_WriteU32(_SRC_SRSR_ADDR, r); + + DBG_ShowReg(3); + + JLINK_SYS_Report("Execute SYSRESETREQ via AIRCR"); + JLINK_MEM_WriteU32(_SCB_AIRCR_ADDR, 0x05FA0004); + JLINK_SYS_Sleep(100); + + r = JLINK_MEM_ReadU32(_DWT_FUNC0_ADDR); + if ((r & 0x01000000) == 0) + { + JLINK_SYS_Report("ERR: CM33 core is not trapped!"); + } + + DBG_ShowReg(4); + + r = JLINK_TARGET_IsHalted(); + if (r == 1) + { + JLINK_SYS_Report("restore CM33 watch point"); + JLINK_MEM_WriteU32(_DWT_COMP0_ADDR, comp); + JLINK_MEM_WriteU32(_DWT_FUNC0_ADDR, func); + } + else + { + JLINK_SYS_Report("ERR: CM33 is not halted after reset!"); + } +} + +void ResetTarget_CM7(void) +{ + int r, w; + int comp, func; + int core_reset_request_bit_mask; + int mem_0, mem_1, mem_2; + + core_reset_request_bit_mask = 0x400; /* for CM7 core */ + + DBG_ShowReg(0); + + /* Halt the CPU and wait sometime for possible peripheral operation finish */ + JLINK_TARGET_Halt(); + JLINK_SYS_Sleep(10); + + r = JLINK_TARGET_IsHalted(); + if (r != 1) + { + JLINK_SYS_Report("ERR: CM7 core can't be halted!"); + } + + DBG_ShowReg(1); + + /* check and enable core request system reset */ + r = JLINK_MEM_ReadU32(_SRC_SRMASK_ADDR); + if ( (r & core_reset_request_bit_mask) != 0 ) + { + if ( (r & (core_reset_request_bit_mask<<16)) == 0 ) + { + w = r & (~core_reset_request_bit_mask); + r = JLINK_MEM_ReadU32(_SRC_AUTHEN_CTRL_ADDR); + if ( (r & 0x80) == 0 ) + { + JLINK_SYS_Report("Enable system reset via CM7 core reset"); + JLINK_MEM_WriteU32(_SRC_SRMASK_ADDR, w); + } + else + { + JLINK_SYS_Report("ERR: Core reset request is masked and all mask are locked!"); + } + } + else + { + JLINK_SYS_Report("ERR: Core reset request is masked and locked!"); + } + } + + DBG_ShowReg(2); + + /* Clear the reset status to avoid ROM clean the core TCM after reset */ + r = JLINK_MEM_ReadU32(_SRC_SRSR_ADDR); + JLINK_MEM_WriteU32(_SRC_SRSR_ADDR, r); + + DBG_ShowReg(3); + + /* CM7_KickOff will use the first 3 words(32bits) of CM7 ITCM, save and restore them later */ + mem_0 = JLINK_MEM_ReadU32(0); + mem_1 = JLINK_MEM_ReadU32(4); + mem_2 = JLINK_MEM_ReadU32(8); + + JLINK_SYS_Report("Set CM33 watch point"); + _WriteViaCM33AP32(_DCB_DHCSR_ADDR, 0xA05F0003); // Enable Debug and halt CM33 core + comp = _ReadViaCM33AP32(_DWT_COMP0_ADDR); /* Save the DWT register and restore them later after reset */ + func = _ReadViaCM33AP32(_DWT_FUNC0_ADDR); + _WriteViaCM33AP32(_DCB_DEMCR_ADDR, 0x01000000); // Enable DWT of CM33 core + _WriteViaCM33AP32(_DWT_COMP0_ADDR, rom_trap_addr); + _WriteViaCM33AP32(_DWT_FUNC0_ADDR, 0x00000412); + + DBG_ShowReg(4); + + JLINK_SYS_Report("Execute SYSRESETREQ via AIRCR"); + JLINK_MEM_WriteU32(_SCB_AIRCR_ADDR, 0x05FA0004); + JLINK_SYS_Sleep(100); + + r = _ReadViaCM33AP32(_DWT_FUNC0_ADDR); + if ((r & 0x01000000) == 0) + { + JLINK_SYS_Report("ERR: CM33 core is not trapped after reset!"); + } + + DBG_ShowReg(5); + + CM7_KickOff(0); + + // Halt CM7 core + JLINK_MEM_WriteU32(_DCB_DHCSR_ADDR, 0xA05F0003); + + DBG_ShowReg(6); + + r = JLINK_TARGET_IsHalted(); + if (r == 1) + { + JLINK_SYS_Report("restore CM7 ITCM"); + + JLINK_MEM_WriteU32(0, mem_0); + JLINK_MEM_WriteU32(4, mem_1); + JLINK_MEM_WriteU32(8, mem_2); + + JLINK_SYS_Report("restore CM33 watch points"); + _WriteViaCM33AP32(_DWT_COMP0_ADDR, comp); + _WriteViaCM33AP32(_DWT_FUNC0_ADDR, func); + } + else + { + JLINK_SYS_Report("ERR: CM7 core can not be halted!"); + } +} + +void ResetTarget(void) { + if(cpuID == _CM7_CPUID) + { + ResetTarget_CM7(); + } + else if(cpuID == _CM33_CPUID) + { + ResetTarget_CM33(); + } +} + +int AfterResetTarget(void) +{ + U32 reg; + + if(cpuID == _CM33_CPUID) + { + // CM33 NVIC may be enabled by ROM after reset + CM33_ClearNVIC(); + } + + Flash_Init(); + HyperRAM_Init(); + + return 0; +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/figures/board.jpg b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/figures/board.jpg new file mode 100644 index 00000000000..e6517698d26 Binary files /dev/null and b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/figures/board.jpg differ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/rtconfig.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/rtconfig.h new file mode 100644 index 00000000000..4892c4d1fc4 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/rtconfig.h @@ -0,0 +1,431 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* RT-Thread Kernel */ + +/* klibc options */ + +/* rt_vsnprintf options */ + +/* end of rt_vsnprintf options */ + +/* rt_vsscanf options */ + +/* end of rt_vsscanf options */ + +/* rt_memset options */ + +/* end of rt_memset options */ + +/* rt_memcpy options */ + +/* end of rt_memcpy options */ + +/* rt_memmove options */ + +/* end of rt_memmove options */ + +/* rt_memcmp options */ + +/* end of rt_memcmp options */ + +/* rt_strstr options */ + +/* end of rt_strstr options */ + +/* rt_strcasecmp options */ + +/* end of rt_strcasecmp options */ + +/* rt_strncpy options */ + +/* end of rt_strncpy options */ + +/* rt_strcpy options */ + +/* end of rt_strcpy options */ + +/* rt_strncmp options */ + +/* end of rt_strncmp options */ + +/* rt_strcmp options */ + +/* end of rt_strcmp options */ + +/* rt_strlen options */ + +/* end of rt_strlen options */ + +/* rt_strnlen options */ + +/* end of rt_strnlen options */ +/* end of klibc options */ +#define RT_NAME_MAX 12 +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 4096 + +/* kservice options */ + +/* end of kservice options */ +#define RT_USING_DEBUG +#define RT_DEBUGING_ASSERT +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +/* end of Inter-Thread communication */ + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_MEMHEAP +#define RT_MEMHEAP_FAST_MODE +#define RT_USING_MEMHEAP_AS_HEAP +#define RT_USING_MEMHEAP_AUTO_BINDING +#define RT_USING_HEAP +/* end of Memory Management */ +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x50201 +#define RT_BACKTRACE_LEVEL_MAX_NR 32 +/* end of RT-Thread Kernel */ +#define RT_USING_HW_ATOMIC +#define RT_USING_CPU_FFS +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_FPU +#define ARCH_ARM_CORTEX_M33 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 4096 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + +/* end of DFS: device virtual file system */ + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN +/* end of Device Drivers */ + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 +/* end of Timezone and Daylight Saving Time */ +/* end of ISO-ANSI C layer */ + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + +/* end of Interprocess Communication (IPC) */ +/* end of POSIX (Portable Operating System Interface) layer */ +/* end of C/C++ and POSIX layer */ + +/* Network */ + +/* end of Network */ + +/* Memory protection */ + +/* end of Memory protection */ + +/* Utilities */ + +/* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ +/* end of RT-Thread Components */ + +/* RT-Thread Utestcases */ + +/* end of RT-Thread Utestcases */ + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + +/* end of Marvell WiFi */ + +/* Wiced WiFi */ + +/* end of Wiced WiFi */ + +/* CYW43012 WiFi */ + +/* end of CYW43012 WiFi */ + +/* BL808 WiFi */ + +/* end of BL808 WiFi */ + +/* CYW43439 WiFi */ + +/* end of CYW43439 WiFi */ +/* end of Wi-Fi */ + +/* IoT Cloud */ + +/* end of IoT Cloud */ +/* end of IoT - internet of things */ + +/* security packages */ + +/* end of security packages */ + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* XML: Extensible Markup Language */ + +/* end of XML: Extensible Markup Language */ +/* end of language packages */ + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + +/* end of LVGL: powerful and easy-to-use embedded GUI library */ + +/* u8g2: a monochrome graphic library */ + +/* end of u8g2: a monochrome graphic library */ +/* end of multimedia packages */ + +/* tools packages */ + +/* end of tools packages */ + +/* system packages */ + +/* enhanced kernel services */ + +/* end of enhanced kernel services */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + +/* end of acceleration: Assembly language or algorithmic acceleration packages */ + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* Micrium: Micrium software products porting for RT-Thread */ + +/* end of Micrium: Micrium software products porting for RT-Thread */ +/* end of system packages */ + +/* peripheral libraries and drivers */ + +/* HAL & SDK Drivers */ + +/* STM32 HAL & SDK Drivers */ + +/* end of STM32 HAL & SDK Drivers */ + +/* Infineon HAL Packages */ + +/* end of Infineon HAL Packages */ + +/* Kendryte SDK */ + +/* end of Kendryte SDK */ + +/* WCH HAL & SDK Drivers */ + +/* end of WCH HAL & SDK Drivers */ + +/* AT32 HAL & SDK Drivers */ + +/* end of AT32 HAL & SDK Drivers */ + +/* HC32 DDL Drivers */ + +/* end of HC32 DDL Drivers */ + +/* NXP HAL & SDK Drivers */ + +#define PKG_USING_NXP_IMXRT_DRIVER +#define PKG_USING_NXP_IMXRT_DRIVER_LATEST_VERSION +/* end of NXP HAL & SDK Drivers */ + +/* NUVOTON Drivers */ + +/* end of NUVOTON Drivers */ + +/* GD32 Drivers */ + +/* end of GD32 Drivers */ + +/* HPMicro SDK */ + +/* end of HPMicro SDK */ + +/* FT32 HAL & SDK Drivers */ + +/* end of FT32 HAL & SDK Drivers */ +/* end of HAL & SDK Drivers */ + +/* sensors drivers */ + +/* end of sensors drivers */ + +/* touch drivers */ + +/* end of touch drivers */ +/* end of peripheral libraries and drivers */ + +/* AI packages */ + +/* end of AI packages */ + +/* Signal Processing and Control Algorithm Packages */ + +/* end of Signal Processing and Control Algorithm Packages */ + +/* miscellaneous packages */ + +/* project laboratory */ + +/* end of project laboratory */ + +/* samples: kernel and components samples */ + +/* end of samples: kernel and components samples */ + +/* entertainment: terminal games and other interesting software packages */ + +/* end of entertainment: terminal games and other interesting software packages */ +/* end of miscellaneous packages */ + +/* Arduino libraries */ + + +/* Projects and Demos */ + +/* end of Projects and Demos */ + +/* Sensors */ + +/* end of Sensors */ + +/* Display */ + +/* end of Display */ + +/* Timing */ + +/* end of Timing */ + +/* Data Processing */ + +/* end of Data Processing */ + +/* Data Storage */ + +/* Communication */ + +/* end of Communication */ + +/* Device Control */ + +/* end of Device Control */ + +/* Other */ + +/* end of Other */ + +/* Signal IO */ + +/* end of Signal IO */ + +/* Uncategorized */ + +/* end of Arduino libraries */ +/* end of RT-Thread online packages */ +#define SOC_IMXRT1180_SERIES + +/* Hardware Drivers Config */ + +#define BSP_USING_QSPIFLASH +#define SOC_MIMXRT1189CVM8C +#define SOC_MIMXRT1189CVM8C_CM7 + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_LPUART +#define BSP_USING_LPUART1 +/* end of On-chip Peripheral Drivers */ + +/* Onboard Peripheral Drivers */ + +/* end of Onboard Peripheral Drivers */ + +/* Board extended module Drivers */ + +/* end of Hardware Drivers Config */ + +#endif diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/rtconfig.py b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/rtconfig.py new file mode 100644 index 00000000000..b450cbbefdf --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/rtconfig.py @@ -0,0 +1,165 @@ +import os +import sys + +# toolchains options +ARCH='arm' +CPU='cortex-m7' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iccarm' + EXEC_PATH = r'C:/Program Files/IAR Systems/Embedded Workbench 9.2' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +#BUILD = 'debug' +BUILD = 'release' + +if PLATFORM == 'gcc': + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + STRIP = PREFIX + 'strip' + + DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Wall -D__FPU_PRESENT -eentry' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb -D__START=entry' + LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + AFLAGS += ' -D__STARTUP_INITIALIZE_NONCACHEDATA' + AFLAGS += ' -D__STARTUP_CLEAR_BSS' + + if BUILD == 'debug': + CFLAGS += ' -gdwarf-2' + AFLAGS += ' -gdwarf-2' + CFLAGS += ' -O0' + else: + CFLAGS += ' -O2 -Os' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + + # module setting + CXXFLAGS = ' -Woverloaded-virtual -fno-exceptions -fno-rtti ' + M_CFLAGS = CFLAGS + ' -mlong-calls -fPIC ' + M_CXXFLAGS = CXXFLAGS + ' -mlong-calls -fPIC' + M_LFLAGS = DEVICE + CXXFLAGS + ' -Wl,--gc-sections,-z,max-page-size=0x4' +\ + ' -shared -fPIC -nostartfiles -static-libgcc' + M_POST_ACTION = STRIP + ' -R .hash $TARGET\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu ' + CPU + '.fp.sp' + CFLAGS = DEVICE + ' --apcs=interwork' + AFLAGS = DEVICE + LFLAGS = DEVICE + ' --libpath "' + EXEC_PATH + '\ARM\ARMCC\lib" --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter "board\linker_scripts\link.sct"' + + CFLAGS += ' --diag_suppress=66,1296,186,6314' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' + LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' + + EXEC_PATH += '/arm/bin40/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' --c99' + + POST_ACTION = 'fromelf -z $TARGET' + # POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iccarm': + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = ' -D__FPU_PRESENT' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --debug' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=' + CPU + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' -Ol' + CFLAGS += ' --use_c++_inline' + + AFLAGS = '' + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu ' + CPU + AFLAGS += ' --fpu None' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link_ram.icf"' + LFLAGS += ' --redirect _Printf=_PrintfTiny' + LFLAGS += ' --redirect _Scanf=_ScanfSmall' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + # sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) + \ No newline at end of file diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.ewd b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.ewd new file mode 100644 index 00000000000..f728737cac8 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.ewd @@ -0,0 +1,1620 @@ + + + 4 + + rtthread + + ARM + + 1 + + C-SPY + 2 + + 33 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + E2_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IJET_ID + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 3 + 1 + 1 + + + + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 1 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 1 + + + + + + + + STLINK_ID + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.ewp b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.ewp new file mode 100644 index 00000000000..d283c339789 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.ewp @@ -0,0 +1,1103 @@ + + + 4 + + rtthread + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.ewt b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.ewt new file mode 100644 index 00000000000..0a51a951d6d --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.ewt @@ -0,0 +1,1468 @@ + + + 4 + + rtthread + + ARM + + 1 + + C-STAT + 519 + + 519 + + 0 + + 1 + 600 + 0 + 2 + 0 + 1 + 100 + rtthread/C-STAT + + + 2.7.5 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rtthread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 8 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + .\board\linker_scripts\evkmimxrt1170_flexspi_nor_sdram.ini + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S8 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC40000 -FN1 -FF0MIMXRT117x_QuadSPI_4KB_SEC.FLM -FS030000000 -FL01000000 -FP0($$Device:MIMXRT1176DVMAA$arm\MIMXRT117x_QuadSPI_4KB_SEC.FLM) + + + 0 + JL2CM3 + -U600103734 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC8000 -FN1 -FF0MIMXRT117x_QuadSPI_4KB_SEC.FLM -FS030000000 -FL01000000 -FP0($$Device:MIMXRT1176DVMAA$arm\MIMXRT117x_QuadSPI_4KB_SEC.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC40000 -FN2 -FF0MIMXRT117x_QuadSPI_4KB_SEC -FS030000000 -FL01000000 -FF1MIMXRT117x_QuadSPI_4KB_SEC_Alias -FS18000000 -FL11000000 -FP0($$Device:MIMXRT1176DVMAA$arm\MIMXRT117x_QuadSPI_4KB_SEC.FLM) -FP1($$Device:MIMXRT1176DVMAA$arm\MIMXRT117x_QuadSPI_4KB_SEC_Alias.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 1 + 0 + 2 + 10000000 + + + + + diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.uvprojx b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.uvprojx new file mode 100644 index 00000000000..95a9d570eba --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.uvprojx @@ -0,0 +1,401 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rtthread + 0x4 + ARM-ADS + 6150000::V6.15::ARMCLANG + 1 + + + MIMXRT1176DVMAA:cm7 + NXP + NXP.MIMXRT1176_DFP.13.1.0 + https://mcuxpresso.nxp.com/cmsis_pack/repo/ + IRAM(0x20000000,0x020000) IRAM2(0x20000000,0x040000) IROM(0x00200000,0x040000) XRAM(0x1ffe0000,0x020000) XRAM2(0x00000000,0x040000) XRAM3(0x20240000,0x080000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC40000 -FN2 -FF0MIMXRT117x_QuadSPI_4KB_SEC -FS030000000 -FL01000000 -FF1MIMXRT117x_QuadSPI_4KB_SEC_Alias -FS18000000 -FL11000000 -FP0($$Device:MIMXRT1176DVMAA$arm\MIMXRT117x_QuadSPI_4KB_SEC.FLM) -FP1($$Device:MIMXRT1176DVMAA$arm\MIMXRT117x_QuadSPI_4KB_SEC_Alias.FLM)) + 0 + $$Device:MIMXRT1176DVMAA$fsl_device_registers.h + + + + + + + + + + $$Device:MIMXRT1176DVMAA$MIMXRT1176_cm7.xml + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rtthread + 1 + 0 + 0 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM7 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM7 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 0 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M7" + + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 3 + 0 + 0 + 1 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x200000 + 0x40000 + + + 1 + 0x1ffe0000 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x200000 + 0x40000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x1ffe0000 + 0x20000 + + + 0 + 0x0 + 0x40000 + + + 0 + 0x20240000 + 0x80000 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 5 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 1 + 0 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + -xc -std=gnu99 -mimplicit-float + RELOC_VECTOR + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x10000000 + + .\board\linker_scripts\link.sct + + + --legacyalign + + 6439,6314 + + + + + + + + + + + + + + + + <Project Info> + 0 + 1 + + + + + diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/SConscript b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/SConscript new file mode 100644 index 00000000000..77f19bf75d8 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/SConscript @@ -0,0 +1,38 @@ +from building import * + +src = [] +cwd = GetCurrentDir() +path = [cwd] +CPPDEFINES = [] + +if GetDepend(['BSP_USING_LCD_MIPI']): + + path += [cwd + '/display', cwd + '/display/dc', cwd + '/display/fbdev', cwd + '/display/mipi_dsi_cmd'] + + src += ['fsl_video_common.c'] + src += ['display/fbdev/fsl_fbdev.c'] + src += ['display/mipi_dsi_cmd/fsl_mipi_dsi_cmd.c'] + + if GetDepend(['BSP_USING_LCDIFV2']): + src += ['display/dc/lcdifv2/fsl_dc_fb_lcdifv2.c'] + path += [cwd + '/display/dc/lcdifv2'] + elif GetDepend(['BSP_USING_ELCDIF']): + src += ['display/dc/elcdif/fsl_dc_fb_elcdif.c'] + path += [cwd + '/display/dc/elcdif'] + + if GetDepend(['DISPLAY_USING_RK055AHD091']): + src += ['display/rm68200/fsl_rm68200.c'] + path += [cwd + '/display/rm68200'] + elif GetDepend(['DISPLAY_USING_RK055IQH091']): + src += ['display/rm68191/fsl_rm68191.c'] + path += [cwd + '/display/rm68191'] + elif GetDepend(['DISPLAY_USING_RK055MHD091']): + src += ['display/hx8394/fsl_hx8394.c'] + path += [cwd + '/display/hx8394'] + + group = DefineGroup('video', src, depend = [''], CPPPATH = path, CPPDEFINES=CPPDEFINES) + + Return('group') +else: + empty_list = [] + Return('empty_list') \ No newline at end of file diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/display/dc/elcdif/fsl_dc_fb_elcdif.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/display/dc/elcdif/fsl_dc_fb_elcdif.c new file mode 100644 index 00000000000..f0720c1684e --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/display/dc/elcdif/fsl_dc_fb_elcdif.c @@ -0,0 +1,264 @@ +/* + * Copyright 2019-2020, 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_dc_fb_elcdif.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +const dc_fb_ops_t g_dcFbOpsElcdif = { + .init = DC_FB_ELCDIF_Init, + .deinit = DC_FB_ELCDIF_Deinit, + .enableLayer = DC_FB_ELCDIF_EnableLayer, + .disableLayer = DC_FB_ELCDIF_DisableLayer, + .setLayerConfig = DC_FB_ELCDIF_SetLayerConfig, + .getLayerDefaultConfig = DC_FB_ELCDIF_GetLayerDefaultConfig, + .setFrameBuffer = DC_FB_ELCDIF_SetFrameBuffer, + .getProperty = DC_FB_ELCDIF_GetProperty, + .setCallback = DC_FB_ELCDIF_SetCallback, +}; + +typedef struct +{ + video_pixel_format_t videoFormat; + elcdif_pixel_format_t elcdifFormat; +} dc_fb_elcdif_pixel_foramt_map_t; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static status_t DC_FB_ELCDIF_GetPixelFormat(video_pixel_format_t input, elcdif_pixel_format_t *output); + +/******************************************************************************* + * Variables + ******************************************************************************/ +static const dc_fb_elcdif_pixel_foramt_map_t s_elcdifPixelFormatMap[] = { + {kVIDEO_PixelFormatLUT8, kELCDIF_PixelFormatRAW8}, + {kVIDEO_PixelFormatRGB565, kELCDIF_PixelFormatRGB565}, + { + kVIDEO_PixelFormatXRGB8888, + kELCDIF_PixelFormatXRGB8888, + }, + { + kVIDEO_PixelFormatRGB888, + kELCDIF_PixelFormatRGB888, + }}; + +/******************************************************************************* + * Code + ******************************************************************************/ +static status_t DC_FB_ELCDIF_GetPixelFormat(video_pixel_format_t input, elcdif_pixel_format_t *output) +{ + uint8_t i; + + for (i = 0; i < ARRAY_SIZE(s_elcdifPixelFormatMap); i++) + { + if (s_elcdifPixelFormatMap[i].videoFormat == input) + { + *output = s_elcdifPixelFormatMap[i].elcdifFormat; + return kStatus_Success; + } + } + + return kStatus_InvalidArgument; +} + +status_t DC_FB_ELCDIF_Init(const dc_fb_t *dc) +{ + const dc_fb_elcdif_config_t *dcConfig; + elcdif_rgb_mode_config_t elcdifConfig = {0}; + + dc_fb_elcdif_handle_t *dcHandle = dc->prvData; + + if (0U == dcHandle->initTimes++) + { + dcConfig = (const dc_fb_elcdif_config_t *)(dc->config); + + elcdifConfig.panelWidth = dcConfig->width; + elcdifConfig.panelHeight = dcConfig->height; + elcdifConfig.hsw = (uint8_t)dcConfig->hsw; + elcdifConfig.hfp = (uint8_t)dcConfig->hfp; + elcdifConfig.hbp = (uint8_t)dcConfig->hbp; + elcdifConfig.vsw = (uint8_t)dcConfig->vsw; + elcdifConfig.vfp = (uint8_t)dcConfig->vfp; + elcdifConfig.vbp = (uint8_t)dcConfig->vbp; + elcdifConfig.bufferAddr = 0; + elcdifConfig.dataBus = dcConfig->dataBus; + elcdifConfig.pixelFormat = DC_FB_ELCDIF_DEFAULT_PIXEL_FORMAT_ELCDIF; + elcdifConfig.polarityFlags = dcConfig->polarityFlags; + + dcHandle->height = dcConfig->height; + dcHandle->width = dcConfig->width; + dcHandle->elcdif = dcConfig->elcdif; + + ELCDIF_RgbModeInit(dcHandle->elcdif, &elcdifConfig); + } + + return kStatus_Success; +} + +status_t DC_FB_ELCDIF_Deinit(const dc_fb_t *dc) +{ + dc_fb_elcdif_handle_t *dcHandle = dc->prvData; + + if (dcHandle->initTimes > 0U) + { + if ((--dcHandle->initTimes) == 0U) + { + ELCDIF_Deinit(dcHandle->elcdif); + } + } + + return kStatus_Success; +} + +status_t DC_FB_ELCDIF_EnableLayer(const dc_fb_t *dc, uint8_t layer) +{ + assert(layer < DC_FB_ELCDIF_MAX_LAYER); + + status_t status = kStatus_Success; + dc_fb_elcdif_handle_t *dcHandle = dc->prvData; + + /* If the layer is already started. */ + if (!dcHandle->layers[layer].enabled) + { + /* Must have valid frame buffer to show. */ + if (dcHandle->layers[layer].activeBuffer == NULL) + { + status = kStatus_Fail; + } + else + { + ELCDIF_RgbModeStart(dcHandle->elcdif); + dcHandle->layers[layer].enabled = true; + ELCDIF_EnableInterrupts(dcHandle->elcdif, (uint32_t)kELCDIF_CurFrameDoneInterruptEnable); + } + } + + return status; +} + +status_t DC_FB_ELCDIF_DisableLayer(const dc_fb_t *dc, uint8_t layer) +{ + assert(layer < DC_FB_ELCDIF_MAX_LAYER); + + dc_fb_elcdif_handle_t *dcHandle = dc->prvData; + + if (dcHandle->layers[layer].enabled) + { + ELCDIF_RgbModeStop(dcHandle->elcdif); + dcHandle->layers[layer].enabled = false; + ELCDIF_DisableInterrupts(dcHandle->elcdif, (uint32_t)kELCDIF_CurFrameDoneInterruptEnable); + } + + return kStatus_Success; +} + +status_t DC_FB_ELCDIF_SetLayerConfig(const dc_fb_t *dc, uint8_t layer, dc_fb_info_t *fbInfo) +{ + assert(layer < DC_FB_ELCDIF_MAX_LAYER); + + elcdif_pixel_format_t pixelFormat; + status_t status; + + dc_fb_elcdif_handle_t *dcHandle = (dc_fb_elcdif_handle_t *)(dc->prvData); + + assert(fbInfo->startX == 0U); + assert(fbInfo->startY == 0U); + assert(fbInfo->width == dcHandle->width); + assert(fbInfo->height == dcHandle->height); + assert(fbInfo->strideBytes == VIDEO_GetPixelSizeBits(fbInfo->pixelFormat) * dcHandle->width / 8U); + + status = DC_FB_ELCDIF_GetPixelFormat(fbInfo->pixelFormat, &pixelFormat); + if (kStatus_Success != status) + { + return status; + } + + ELCDIF_RgbModeSetPixelFormat(dcHandle->elcdif, pixelFormat); + + return kStatus_Success; +} + +status_t DC_FB_ELCDIF_GetLayerDefaultConfig(const dc_fb_t *dc, uint8_t layer, dc_fb_info_t *fbInfo) +{ + assert(layer < DC_FB_ELCDIF_MAX_LAYER); + + dc_fb_elcdif_handle_t *dcHandle = (dc_fb_elcdif_handle_t *)(dc->prvData); + + fbInfo->startX = 0; + fbInfo->startY = 0; + fbInfo->width = dcHandle->width; + fbInfo->height = dcHandle->height; + fbInfo->strideBytes = 2U * dcHandle->width; + fbInfo->pixelFormat = DC_FB_ELCDIF_DEFAULT_PIXEL_FORMAT; + + return kStatus_Success; +} + +status_t DC_FB_ELCDIF_SetFrameBuffer(const dc_fb_t *dc, uint8_t layer, void *frameBuffer) +{ + assert(layer < DC_FB_ELCDIF_MAX_LAYER); + dc_fb_elcdif_handle_t *dcHandle = dc->prvData; + + ELCDIF_SetNextBufferAddr(dcHandle->elcdif, (uint32_t)(uint8_t *)frameBuffer); + dcHandle->layers[layer].inactiveBuffer = frameBuffer; + + /* + * If the layer is not started, set the current buffer and next buffer to + * new frame buffer, there is not pending frame. + * If the layer already started, only set the next buffer, and the new frameBuffer + * is pending until current buffer switched out. + */ + if (!dcHandle->layers[layer].enabled) + { + dcHandle->elcdif->CUR_BUF = ELCDIF_ADDR_CPU_2_IP((uint32_t)(uint8_t *)frameBuffer); + dcHandle->layers[layer].activeBuffer = frameBuffer; + } + else + { + dcHandle->layers[layer].framePending = true; + } + + return kStatus_Success; +} + +void DC_FB_ELCDIF_SetCallback(const dc_fb_t *dc, uint8_t layer, dc_fb_callback_t callback, void *param) +{ + assert(layer < DC_FB_ELCDIF_MAX_LAYER); + dc_fb_elcdif_handle_t *dcHandle = dc->prvData; + + dcHandle->layers[layer].callback = callback; + dcHandle->layers[layer].cbParam = param; +} + +uint32_t DC_FB_ELCDIF_GetProperty(const dc_fb_t *dc) +{ + return (uint32_t)kDC_FB_ReserveFrameBuffer; +} + +void DC_FB_ELCDIF_IRQHandler(const dc_fb_t *dc) +{ + dc_fb_elcdif_handle_t *dcHandle = dc->prvData; + dc_fb_elcdif_layer_t *layer; + void *oldActiveBuffer; + ELCDIF_ClearInterruptStatus(dcHandle->elcdif, (uint32_t)kELCDIF_CurFrameDone); + + for (uint8_t i = 0; i < DC_FB_ELCDIF_MAX_LAYER; i++) + { + if (dcHandle->layers[i].framePending) + { + layer = &dcHandle->layers[i]; + + oldActiveBuffer = layer->activeBuffer; + layer->activeBuffer = layer->inactiveBuffer; + dcHandle->layers[i].framePending = false; + + layer->callback(layer->cbParam, oldActiveBuffer); + } + } +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/display/dc/elcdif/fsl_dc_fb_elcdif.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/display/dc/elcdif/fsl_dc_fb_elcdif.h new file mode 100644 index 00000000000..09be2140522 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/display/dc/elcdif/fsl_dc_fb_elcdif.h @@ -0,0 +1,101 @@ +/* + * Copyright 2019-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_DC_FB_ELCDIF_H_ +#define _FSL_DC_FB_ELCDIF_H_ + +#include "fsl_dc_fb.h" +#include "fsl_elcdif.h" + +/* + * Change log: + * + * 1.0.1 + * - Fixed MISRA-C 2012 issues. + * + * 1.0.0 + * - Initial version + */ + +/*! + * @addtogroup dc_fb_elcdif + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define DC_FB_ELCDIF_MAX_LAYER 1U /* Only support one layer currently. */ +#define DC_FB_ELCDIF_DEFAULT_PIXEL_FORMAT kVIDEO_PixelFormatRGB565 +#define DC_FB_ELCDIF_DEFAULT_PIXEL_FORMAT_ELCDIF kELCDIF_PixelFormatRGB565 + +/*! @brief Data for ELCDIF display controller layer. */ +typedef struct _dc_fb_elcdif_layer +{ + bool enabled; /*!< The layer is enabled. */ + volatile bool framePending; /*!< New frame pending. */ + void *activeBuffer; /*!< The frame buffer which is shown. */ + void *inactiveBuffer; /*!< The frame buffer which will be shown. */ + dc_fb_callback_t callback; /*!< Callback for buffer switch off. */ + void *cbParam; /*!< Callback parameter. */ +} dc_fb_elcdif_layer_t; + +/*! @brief Data for ELCDIF display controller driver handle. */ +typedef struct _dc_fb_elcdif_handle +{ + LCDIF_Type *elcdif; /*!< eLCDIF peripheral. */ + uint8_t initTimes; /*!< How many times the DC is initialized. */ + uint16_t height; /*!< Panel height. */ + uint16_t width; /*!< Panel width. */ + dc_fb_elcdif_layer_t layers[DC_FB_ELCDIF_MAX_LAYER]; /*!< Information of the layer. */ +} dc_fb_elcdif_handle_t; + +/*! @brief Configuration for ELCDIF display controller driver handle. */ +typedef struct _dc_fb_elcdif_config +{ + LCDIF_Type *elcdif; /*!< ELCDIF peripheral. */ + uint16_t width; /*!< Width of the panel. */ + uint16_t height; /*!< Height of the panel. */ + uint16_t hsw; /*!< HSYNC pulse width. */ + uint16_t hfp; /*!< Horizontal front porch. */ + uint16_t hbp; /*!< Horizontal back porch. */ + uint16_t vsw; /*!< VSYNC pulse width. */ + uint16_t vfp; /*!< Vertical front porch. */ + uint16_t vbp; /*!< Vertical back porch. */ + uint32_t polarityFlags; /*!< Control flags, OR'ed value of @ref _elcdif_polarity_flags. */ + elcdif_lcd_data_bus_t dataBus; /*!< LCD data bus. */ +} dc_fb_elcdif_config_t; + +extern const dc_fb_ops_t g_dcFbOpsElcdif; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +status_t DC_FB_ELCDIF_Init(const dc_fb_t *dc); +status_t DC_FB_ELCDIF_Deinit(const dc_fb_t *dc); +status_t DC_FB_ELCDIF_EnableLayer(const dc_fb_t *dc, uint8_t layer); +status_t DC_FB_ELCDIF_DisableLayer(const dc_fb_t *dc, uint8_t layer); +status_t DC_FB_ELCDIF_SetLayerConfig(const dc_fb_t *dc, uint8_t layer, dc_fb_info_t *fbInfo); +status_t DC_FB_ELCDIF_GetLayerDefaultConfig(const dc_fb_t *dc, uint8_t layer, dc_fb_info_t *fbInfo); +status_t DC_FB_ELCDIF_SetFrameBuffer(const dc_fb_t *dc, uint8_t layer, void *frameBuffer); +uint32_t DC_FB_ELCDIF_GetProperty(const dc_fb_t *dc); +void DC_FB_ELCDIF_SetCallback(const dc_fb_t *dc, uint8_t layer, dc_fb_callback_t callback, void *param); +void DC_FB_ELCDIF_IRQHandler(const dc_fb_t *dc); + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_DC_FB_ELCDIF_H_ */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/display/dc/fsl_dc_fb.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/display/dc/fsl_dc_fb.h new file mode 100644 index 00000000000..87265a5f3be --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/display/dc/fsl_dc_fb.h @@ -0,0 +1,81 @@ +/* + * Copyright 2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_DC_FB_H_ +#define _FSL_DC_FB_H_ + +#include "fsl_video_common.h" + +/*! + * @addtogroup dc_fb + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief frame buffer information. */ +typedef struct _dc_fb_info +{ + uint16_t startX; /*!< The start position in the panel. */ + uint16_t startY; /*!< The start position in the panel. */ + uint16_t width; /*!< How many pixels in one line of the frame buffer.*/ + uint16_t height; /*!< How many lines in one frame buffer. */ + uint16_t strideBytes; /*!< Stride of the frame buffer */ + video_pixel_format_t pixelFormat; /*!< Pixel format of the frame buffer */ +} dc_fb_info_t; + +/*! @brief Display controller frame callback. */ +typedef void (*dc_fb_callback_t)(void *param, void *inactiveBuffer); + +/*! @brief Display controller. */ +typedef struct _dc_fb dc_fb_t; + +/*! @brief Display controller operations. */ +typedef struct _dc_fb_ops +{ + status_t (*init)(const dc_fb_t *dc); + status_t (*deinit)(const dc_fb_t *dc); + status_t (*enableLayer)(const dc_fb_t *dc, uint8_t layer); + status_t (*disableLayer)(const dc_fb_t *dc, uint8_t layer); + status_t (*setLayerConfig)(const dc_fb_t *dc, uint8_t layer, dc_fb_info_t *fbInfo); + status_t (*getLayerDefaultConfig)(const dc_fb_t *dc, uint8_t layer, dc_fb_info_t *fbInfo); + status_t (*setFrameBuffer)(const dc_fb_t *dc, uint8_t layer, void *frameBuffer); + uint32_t (*getProperty)(const dc_fb_t *dc); + void (*setCallback)(const dc_fb_t *dc, uint8_t layer, dc_fb_callback_t callback, void *param); +} dc_fb_ops_t; + +/*! @brief Display controller property. */ +enum _dc_fb_property +{ + kDC_FB_ReserveFrameBuffer = (1 << 0), /*< One frame buffer is always used as the DC active buffer. */ + kDC_FB_TwoDimensionMemoryWrite = (1 << 1), /*< Support writing memory to device in two dimension way. */ +}; + +/*! @brief Display controller driver handle. */ +struct _dc_fb +{ + const dc_fb_ops_t *ops; /* Display controller operations. */ + void *prvData; /* Private data for the display controller. */ + const void *config; /* Configuration for the display controller. */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_DC_FB_H_ */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/display/dc/lcdifv2/fsl_dc_fb_lcdifv2.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/display/dc/lcdifv2/fsl_dc_fb_lcdifv2.c new file mode 100644 index 00000000000..26efccc6adf --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/display/dc/lcdifv2/fsl_dc_fb_lcdifv2.c @@ -0,0 +1,288 @@ +/* + * Copyright (c) 2019-2020, 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_dc_fb_lcdifv2.h" +#if defined(USE_RTOS) +#include "rtthread.h" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ +const dc_fb_ops_t g_dcFbOpsLcdifv2 = { + .init = DC_FB_LCDIFV2_Init, + .deinit = DC_FB_LCDIFV2_Deinit, + .enableLayer = DC_FB_LCDIFV2_EnableLayer, + .disableLayer = DC_FB_LCDIFV2_DisableLayer, + .setLayerConfig = DC_FB_LCDIFV2_SetLayerConfig, + .getLayerDefaultConfig = DC_FB_LCDIFV2_GetLayerDefaultConfig, + .setFrameBuffer = DC_FB_LCDIFV2_SetFrameBuffer, + .getProperty = DC_FB_LCDIFV2_GetProperty, + .setCallback = DC_FB_LCDIFV2_SetCallback, +}; + +typedef struct +{ + video_pixel_format_t videoFormat; + lcdifv2_pixel_format_t lcdifv2Format; +} dc_fb_lcdifv2_pixel_foramt_map_t; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static status_t DC_FB_LCDIFV2_GetPixelFormat(video_pixel_format_t input, lcdifv2_pixel_format_t *output); + +/******************************************************************************* + * Variables + ******************************************************************************/ +static const dc_fb_lcdifv2_pixel_foramt_map_t s_lcdifv2PixelFormatMap[] = { + {kVIDEO_PixelFormatRGB565, kLCDIFV2_PixelFormatRGB565}, + {kVIDEO_PixelFormatRGB888, kLCDIFV2_PixelFormatRGB888}, + {kVIDEO_PixelFormatXRGB8888, kLCDIFV2_PixelFormatARGB8888}, + {kVIDEO_PixelFormatXBGR8888, kLCDIFV2_PixelFormatABGR8888}, + {kVIDEO_PixelFormatLUT8, kLCDIFV2_PixelFormatIndex8BPP}, + {kVIDEO_PixelFormatXRGB4444, kLCDIFV2_PixelFormatARGB4444}, + {kVIDEO_PixelFormatXRGB1555, kLCDIFV2_PixelFormatARGB1555}}; + +/******************************************************************************* + * Code + ******************************************************************************/ +static status_t DC_FB_LCDIFV2_GetPixelFormat(video_pixel_format_t input, lcdifv2_pixel_format_t *output) +{ + uint8_t i; + + for (i = 0; i < ARRAY_SIZE(s_lcdifv2PixelFormatMap); i++) + { + if (s_lcdifv2PixelFormatMap[i].videoFormat == input) + { + *output = s_lcdifv2PixelFormatMap[i].lcdifv2Format; + return kStatus_Success; + } + } + + return kStatus_InvalidArgument; +} + +status_t DC_FB_LCDIFV2_Init(const dc_fb_t *dc) +{ + status_t status = kStatus_Success; + const dc_fb_lcdifv2_config_t *dcConfig; + + lcdifv2_display_config_t lcdifv2Config = {0}; + + dc_fb_lcdifv2_handle_t *dcHandle = dc->prvData; + + if (0U == dcHandle->initTimes++) + { + dcConfig = (const dc_fb_lcdifv2_config_t *)(dc->config); + + LCDIFV2_DisplayGetDefaultConfig(&lcdifv2Config); + + lcdifv2Config.panelWidth = dcConfig->width; + lcdifv2Config.panelHeight = dcConfig->height; + lcdifv2Config.hsw = (uint8_t)dcConfig->hsw; + lcdifv2Config.hfp = (uint8_t)dcConfig->hfp; + lcdifv2Config.hbp = (uint8_t)dcConfig->hbp; + lcdifv2Config.vsw = (uint8_t)dcConfig->vsw; + lcdifv2Config.vfp = (uint8_t)dcConfig->vfp; + lcdifv2Config.vbp = (uint8_t)dcConfig->vbp; + lcdifv2Config.polarityFlags = dcConfig->polarityFlags; + lcdifv2Config.lineOrder = dcConfig->lineOrder; + + dcHandle->height = dcConfig->height; + dcHandle->width = dcConfig->width; + dcHandle->lcdifv2 = dcConfig->lcdifv2; + dcHandle->domain = dcConfig->domain; + + LCDIFV2_Init(dcHandle->lcdifv2); + + LCDIFV2_SetDisplayConfig(dcHandle->lcdifv2, &lcdifv2Config); + + LCDIFV2_EnableInterrupts(dcHandle->lcdifv2, dcHandle->domain, (uint32_t)kLCDIFV2_VerticalBlankingInterrupt); + + LCDIFV2_EnableDisplay(dcHandle->lcdifv2, true); + } + + return status; +} + +status_t DC_FB_LCDIFV2_Deinit(const dc_fb_t *dc) +{ + dc_fb_lcdifv2_handle_t *dcHandle = dc->prvData; + + if (dcHandle->initTimes > 0U) + { + if (--dcHandle->initTimes == 0U) + { + LCDIFV2_DisableInterrupts(dcHandle->lcdifv2, dcHandle->domain, + (uint32_t)kLCDIFV2_VerticalBlankingInterrupt); + LCDIFV2_Deinit(dcHandle->lcdifv2); + } + } + + return kStatus_Success; +} + +status_t DC_FB_LCDIFV2_EnableLayer(const dc_fb_t *dc, uint8_t layer) +{ + assert(layer < DC_FB_LCDIFV2_MAX_LAYER); + + status_t status = kStatus_Success; + dc_fb_lcdifv2_handle_t *dcHandle = dc->prvData; + + /* If the layer is not started. */ + if (!dcHandle->layers[layer].enabled) + { + LCDIFV2_SetLayerBackGroundColor(dcHandle->lcdifv2, layer, 0U); + LCDIFV2_EnableLayer(dcHandle->lcdifv2, layer, true); + LCDIFV2_TriggerLayerShadowLoad(dcHandle->lcdifv2, layer); + dcHandle->layers[layer].shadowLoadPending = true; + + while (true == dcHandle->layers[layer].shadowLoadPending) + { +#if defined(USE_RTOS) + rt_thread_delay(1); +#endif + } + + dcHandle->layers[layer].activeBuffer = dcHandle->layers[layer].inactiveBuffer; + dcHandle->layers[layer].enabled = true; + } + + return status; +} + +status_t DC_FB_LCDIFV2_DisableLayer(const dc_fb_t *dc, uint8_t layer) +{ + assert(layer < DC_FB_LCDIFV2_MAX_LAYER); + + dc_fb_lcdifv2_handle_t *dcHandle = dc->prvData; + + if (dcHandle->layers[layer].enabled) + { + LCDIFV2_EnableLayer(dcHandle->lcdifv2, layer, false); + LCDIFV2_TriggerLayerShadowLoad(dcHandle->lcdifv2, layer); + dcHandle->layers[layer].enabled = false; + } + + return kStatus_Success; +} + +status_t DC_FB_LCDIFV2_SetLayerConfig(const dc_fb_t *dc, uint8_t layer, dc_fb_info_t *fbInfo) +{ + assert(layer < DC_FB_LCDIFV2_MAX_LAYER); + + lcdifv2_buffer_config_t bufferConfig = {0}; + lcdifv2_pixel_format_t pixelFormat; + LCDIFV2_Type *lcdifv2; + status_t status; + + dc_fb_lcdifv2_handle_t *dcHandle = (dc_fb_lcdifv2_handle_t *)(dc->prvData); + + lcdifv2 = dcHandle->lcdifv2; + + status = DC_FB_LCDIFV2_GetPixelFormat(fbInfo->pixelFormat, &pixelFormat); + if (kStatus_Success != status) + { + return status; + } + + LCDIFV2_SetLayerSize(lcdifv2, layer, fbInfo->width, fbInfo->height); + LCDIFV2_SetLayerOffset(lcdifv2, layer, fbInfo->startX, fbInfo->startY); + + bufferConfig.strideBytes = fbInfo->strideBytes; + bufferConfig.pixelFormat = pixelFormat; + LCDIFV2_SetLayerBufferConfig(lcdifv2, layer, &bufferConfig); + + return kStatus_Success; +} + +status_t DC_FB_LCDIFV2_GetLayerDefaultConfig(const dc_fb_t *dc, uint8_t layer, dc_fb_info_t *fbInfo) +{ + assert(layer < DC_FB_LCDIFV2_MAX_LAYER); + + dc_fb_lcdifv2_handle_t *dcHandle = (dc_fb_lcdifv2_handle_t *)(dc->prvData); + + fbInfo->startX = 0; + fbInfo->startY = 0; + fbInfo->width = dcHandle->width; + fbInfo->height = dcHandle->height; + fbInfo->strideBytes = DC_FB_LCDIFV2_DEFAULT_BYTE_PER_PIXEL * dcHandle->width; + fbInfo->pixelFormat = DC_FB_LCDIFV2_DEFAULT_PIXEL_FORMAT; + + return kStatus_Success; +} + +status_t DC_FB_LCDIFV2_SetFrameBuffer(const dc_fb_t *dc, uint8_t layer, void *frameBuffer) +{ + assert(layer < DC_FB_LCDIFV2_MAX_LAYER); + dc_fb_lcdifv2_handle_t *dcHandle = dc->prvData; + + LCDIFV2_SetLayerBufferAddr(dcHandle->lcdifv2, layer, (uint32_t)(uint8_t *)frameBuffer); + dcHandle->layers[layer].inactiveBuffer = frameBuffer; + + if (dcHandle->layers[layer].enabled) + { + LCDIFV2_TriggerLayerShadowLoad(dcHandle->lcdifv2, layer); + dcHandle->layers[layer].shadowLoadPending = true; + dcHandle->layers[layer].framePending = true; + } + else + { + } + + return kStatus_Success; +} + +void DC_FB_LCDIFV2_SetCallback(const dc_fb_t *dc, uint8_t layer, dc_fb_callback_t callback, void *param) +{ + assert(layer < DC_FB_LCDIFV2_MAX_LAYER); + dc_fb_lcdifv2_handle_t *dcHandle = dc->prvData; + + dcHandle->layers[layer].callback = callback; + dcHandle->layers[layer].cbParam = param; +} + +uint32_t DC_FB_LCDIFV2_GetProperty(const dc_fb_t *dc) +{ + return (uint32_t)kDC_FB_ReserveFrameBuffer; +} + +void DC_FB_LCDIFV2_IRQHandler(const dc_fb_t *dc) +{ + uint32_t intStatus; + dc_fb_lcdifv2_handle_t *dcHandle = dc->prvData; + dc_fb_lcdifv2_layer_t *layer; + void *oldActiveBuffer; + + intStatus = LCDIFV2_GetInterruptStatus(dcHandle->lcdifv2, dcHandle->domain); + LCDIFV2_ClearInterruptStatus(dcHandle->lcdifv2, dcHandle->domain, intStatus); + + if (0U == (intStatus & (uint32_t)kLCDIFV2_VerticalBlankingInterrupt)) + { + return; + } + + for (uint8_t i = 0; i < DC_FB_LCDIFV2_MAX_LAYER; i++) + { + if (dcHandle->layers[i].shadowLoadPending) + { + dcHandle->layers[i].shadowLoadPending = false; + } + + if (dcHandle->layers[i].framePending) + { + layer = &dcHandle->layers[i]; + + oldActiveBuffer = layer->activeBuffer; + layer->activeBuffer = layer->inactiveBuffer; + dcHandle->layers[i].framePending = false; + + layer->callback(layer->cbParam, oldActiveBuffer); + } + } +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/display/dc/lcdifv2/fsl_dc_fb_lcdifv2.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/display/dc/lcdifv2/fsl_dc_fb_lcdifv2.h new file mode 100644 index 00000000000..190437e54d6 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/display/dc/lcdifv2/fsl_dc_fb_lcdifv2.h @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2019-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_DC_FB_LCDIFV2_H_ +#define _FSL_DC_FB_LCDIFV2_H_ + +#include "fsl_dc_fb.h" +#include "fsl_lcdifv2.h" + +/* + * Change log: + * + * 1.0.2 + * - Add more pixel format support. + * + * 1.0.1 + * - Fix MISRA-C 2012 issues. + * + * 1.0.0 + * - Initial version + */ + +/*! + * @addtogroup dc_fb_lcdifv2 + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define DC_FB_LCDIFV2_MAX_LAYER ((uint32_t)LCDIFV2_LAYER_COUNT) +#define DC_FB_LCDIFV2_DEFAULT_BUF_PER_LAYER 3U +#define DC_FB_LCDIFV2_DEFAULT_PIXEL_FORMAT kVIDEO_PixelFormatRGB565 +#define DC_FB_LCDIFV2_DEFAULT_PIXEL_FORMAT_LCDIFV2 kLCDIFV2_PixelFormatRGB565 +#define DC_FB_LCDIFV2_DEFAULT_BYTE_PER_PIXEL 2U + +/*! @brief Data for LCDIFV2 display controller layer. */ +typedef struct _dc_fb_lcdifv2_layer +{ + bool enabled; /*!< The layer is enabled. */ + volatile bool framePending; /*!< New frame pending. */ + volatile bool shadowLoadPending; /*!< Shadow load pending. */ + void *activeBuffer; /*!< The frame buffer which is shown. */ + void *inactiveBuffer; /*!< The frame buffer which will be shown. */ + dc_fb_callback_t callback; /*!< Callback for buffer switch off. */ + void *cbParam; /*!< Callback parameter. */ +} dc_fb_lcdifv2_layer_t; + +/*! @brief Data for LCDIFV2 display controller driver handle. */ +typedef struct _dc_fb_lcdifv2_handle +{ + LCDIFV2_Type *lcdifv2; /*!< LCDIFV2 peripheral. */ + uint8_t initTimes; /*!< How many times the DC is initialized. */ + uint16_t height; /*!< Panel height. */ + uint16_t width; /*!< Panel width. */ + uint8_t domain; /*!< Domain used for interrupt. */ + dc_fb_lcdifv2_layer_t layers[DC_FB_LCDIFV2_MAX_LAYER]; /*!< Information of the layer. */ +} dc_fb_lcdifv2_handle_t; + +/*! @brief Configuration for LCDIFV2 display controller driver handle. */ +typedef struct _dc_fb_lcdifv2_config +{ + LCDIFV2_Type *lcdifv2; /*!< LCDIFV2 peripheral. */ + uint16_t width; /*!< Width of the panel. */ + uint16_t height; /*!< Height of the panel. */ + uint16_t hsw; /*!< HSYNC pulse width. */ + uint16_t hfp; /*!< Horizontal front porch. */ + uint16_t hbp; /*!< Horizontal back porch. */ + uint16_t vsw; /*!< VSYNC pulse width. */ + uint16_t vfp; /*!< Vertical front porch. */ + uint16_t vbp; /*!< Vertical back porch. */ + uint32_t polarityFlags; /*!< Control flags, OR'ed value of @ref _lcdifv2_polarity_flags. */ + lcdifv2_line_order_t lineOrder; /*!< Line order. */ + uint8_t domain; /*!< Domain used to for interrupt. */ +} dc_fb_lcdifv2_config_t; + +extern const dc_fb_ops_t g_dcFbOpsLcdifv2; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +status_t DC_FB_LCDIFV2_Init(const dc_fb_t *dc); +status_t DC_FB_LCDIFV2_Deinit(const dc_fb_t *dc); +status_t DC_FB_LCDIFV2_EnableLayer(const dc_fb_t *dc, uint8_t layer); +status_t DC_FB_LCDIFV2_DisableLayer(const dc_fb_t *dc, uint8_t layer); +status_t DC_FB_LCDIFV2_SetLayerConfig(const dc_fb_t *dc, uint8_t layer, dc_fb_info_t *fbInfo); +status_t DC_FB_LCDIFV2_GetLayerDefaultConfig(const dc_fb_t *dc, uint8_t layer, dc_fb_info_t *fbInfo); +status_t DC_FB_LCDIFV2_SetFrameBuffer(const dc_fb_t *dc, uint8_t layer, void *frameBuffer); +uint32_t DC_FB_LCDIFV2_GetProperty(const dc_fb_t *dc); +void DC_FB_LCDIFV2_SetCallback(const dc_fb_t *dc, uint8_t layer, dc_fb_callback_t callback, void *param); +void DC_FB_LCDIFV2_IRQHandler(const dc_fb_t *dc); + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_DC_FB_LCDIFV2_H_ */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/display/fbdev/fsl_fbdev.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/display/fbdev/fsl_fbdev.c new file mode 100644 index 00000000000..a2a182d9fae --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/display/fbdev/fsl_fbdev.c @@ -0,0 +1,243 @@ +/* + * Copyright 2019-2021, 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_fbdev.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +static void FBDEV_BufferSwitchOffCallback(void *param, void *switchOffBuffer); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +status_t FBDEV_Open(fbdev_t *fbdev, const dc_fb_t *dc, uint8_t layer) +{ + status_t status; + + assert(NULL != fbdev); + + (void)memset(fbdev, 0, sizeof(fbdev_t)); + + fbdev->dc = dc; + + (void)VIDEO_STACK_Init(&fbdev->fbManager, fbdev->buffers, FBDEV_MAX_FRAME_BUFFER); + + /* Initialize the display controller. */ + status = dc->ops->init(dc); + if (kStatus_Success != status) + { + return status; + } + + fbdev->layer = layer; + + /* Initializes the dc_fb_info_t to the display controller default setting. */ + status = dc->ops->getLayerDefaultConfig(dc, layer, &fbdev->fbInfo.bufInfo); + if (kStatus_Success != status) + { + return status; + } + + fbdev->semaFramePending = rt_sem_create("fsfp", 0, RT_IPC_FLAG_PRIO); + if (NULL == fbdev->semaFramePending) + { + return kStatus_Fail; + } + + /* No frame pending. */ + (void)rt_sem_release(fbdev->semaFramePending); + + dc->ops->setCallback(dc, layer, FBDEV_BufferSwitchOffCallback, (void *)fbdev); + + return kStatus_Success; +} + +status_t FBDEV_Close(fbdev_t *fbdev) +{ + const dc_fb_t *dc = fbdev->dc; + + (void)dc->ops->deinit(dc); + + if (NULL != fbdev->semaFbManager) + { + rt_sem_delete(fbdev->semaFbManager); + fbdev->semaFbManager = NULL; + } + + if (NULL != fbdev->semaFramePending) + { + rt_sem_delete(fbdev->semaFramePending); + fbdev->semaFramePending = NULL; + } + + return kStatus_Success; +} + +status_t FBDEV_Enable(fbdev_t *fbdev) +{ + status_t status = kStatus_Success; + + const dc_fb_t *dc = fbdev->dc; + + if (!fbdev->enabled) + { + /* Wait for frame buffer sent to display controller video memory. */ + if ((dc->ops->getProperty(dc) & (uint32_t)kDC_FB_ReserveFrameBuffer) == 0U) + { + if (RT_EOK != rt_sem_take(fbdev->semaFramePending, RT_WAITING_FOREVER)) + { + status = kStatus_Fail; + } + } + + if (kStatus_Success == status) + { + /* No frame is pending. */ + (void)rt_sem_release(fbdev->semaFramePending); + + status = dc->ops->enableLayer(dc, fbdev->layer); + + if (kStatus_Success == status) + { + fbdev->enabled = true; + } + } + } + + return status; +} + +status_t FBDEV_Disable(fbdev_t *fbdev) +{ + status_t status = kStatus_Success; + + const dc_fb_t *dc = fbdev->dc; + + if (!fbdev->enabled) + { + /* Wait until no frame pending. */ + if (RT_EOK != rt_sem_take(fbdev->semaFramePending, RT_WAITING_FOREVER)) + { + status = kStatus_Fail; + } + + if (kStatus_Success == status) + { + (void)rt_sem_release(fbdev->semaFramePending); + + (void)dc->ops->disableLayer(dc, fbdev->layer); + + fbdev->enabled = false; + } + } + + return status; +} + +void FBDEV_GetFrameBufferInfo(fbdev_t *fbdev, fbdev_fb_info_t *info) +{ + *info = fbdev->fbInfo; +} + +status_t FBDEV_SetFrameBufferInfo(fbdev_t *fbdev, fbdev_fb_info_t *info) +{ + status_t status; + const dc_fb_t *dc = fbdev->dc; + + /* Should only change the frame buffer setting before enabling the fbdev. */ + if (fbdev->enabled) + { + return kStatus_Fail; + } + + fbdev->fbInfo = *info; + + status = dc->ops->setLayerConfig(dc, fbdev->layer, &fbdev->fbInfo.bufInfo); + + if (kStatus_Success != status) + { + return status; + } + + fbdev->semaFbManager = rt_sem_create("fsfm", 0, RT_IPC_FLAG_PRIO); + if (NULL == fbdev->semaFbManager) + { + return kStatus_Fail; + } + + for (uint8_t i = 0; i < info->bufferCount; i++) + { + /* Don't need to disable interrupt for the FB stack operation, because + the fbdev is not working, this is the only function to access FB stack. + */ + (void)VIDEO_STACK_Push(&fbdev->fbManager, info->buffers[i]); + (void)rt_sem_release(fbdev->semaFbManager); + } + + return kStatus_Success; +} + +void *FBDEV_GetFrameBuffer(fbdev_t *fbdev, uint32_t flags) +{ + rt_uint32_t tick; + void *fb; + + tick = ((flags & (uint32_t)kFBDEV_NoWait) != 0U) ? 0U : RT_WAITING_FOREVER; + + if (RT_EOK == rt_sem_take(fbdev->semaFbManager, tick)) + { + /* Disable interrupt to protect the FB stack. */ + rt_enter_critical(); + (void)VIDEO_STACK_Pop(&fbdev->fbManager, &fb); + rt_exit_critical(); + } + else + { + fb = NULL; + } + + return fb; +} + +status_t FBDEV_SetFrameBuffer(fbdev_t *fbdev, void *frameBuffer, uint32_t flags) +{ + rt_uint32_t tick; + const dc_fb_t *dc = fbdev->dc; + + tick = ((flags & (uint32_t)kFBDEV_NoWait) != 0U) ? 0U : RT_WAITING_FOREVER; + + if (RT_EOK == rt_sem_take(fbdev->semaFramePending, tick)) + { + return dc->ops->setFrameBuffer(dc, fbdev->layer, frameBuffer); + } + else + { + return kStatus_Fail; + } +} + +static void FBDEV_BufferSwitchOffCallback(void *param, void *switchOffBuffer) +{ + fbdev_t *fbdev = (fbdev_t *)param; + + /* This function should only be called in ISR, so don't need to protect the FB stack */ + (void)VIDEO_STACK_Push(&fbdev->fbManager, switchOffBuffer); + rt_sem_release(fbdev->semaFbManager); + + rt_sem_release(fbdev->semaFramePending); +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/display/fbdev/fsl_fbdev.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/display/fbdev/fsl_fbdev.h new file mode 100644 index 00000000000..556efa74861 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/display/fbdev/fsl_fbdev.h @@ -0,0 +1,227 @@ +/* + * Copyright 2019-2021, 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_FBDEV_H_ +#define _FSL_FBDEV_H_ + +#include "fsl_video_common.h" +#include "fsl_dc_fb.h" +#include "rtthread.h" + +/* + * Change Log: + * + * 1.0.3: + * - Bug Fixes: + * - Fixed the issue that frame buffer content changed when saved + * to free frame buffer list. + * + * 1.0.2: + * - Bug Fixes: + * - Fixed MISRA 2012 issues. + * + * 1.0.1: + * - Bug Fixes: + * - Fixed coverity warnings that return values unchedked. + * + * 1.0.0: + * - Initial version. + */ + +/*! + * @addtogroup fbdev + * @{ + * + * To use the fbdev, follow the workflow: + * + @code + uint8_t layer = 0; + fbdev_t fbdev; + fbdev_fb_info_t fbInfo; + extern const dc_fb_t dc; + + FBDEV_Open(&fbdev, &dc, layer); + + fbInfo.bufInfo.pixelFormat = DEMO_BUFFER_PIXEL_FORMAT; + fbInfo.bufInfo.width = DEMO_BUFFER_WIDTH; + fbInfo.bufInfo.height = DEMO_BUFFER_HEIGHT; + fbInfo.bufInfo.strideBytes = DEMO_BUFFER_STRIDE_BYTE; + fbInfo.buffers[0] = DEMO_BUFFER0_ADDR; + fbInfo.buffers[1] = DEMO_BUFFER1_ADDR; + + FBDEV_SetFrameBufferInfo(&fbdev, &fbInfo); + + buffer = FBDEV_GetFrameBuffer(&fbdev, 0); + + fill the buffer here. + + FBDEV_SetFrameBuffer(&fbdev, buffer, 0); + + FBDEV_Enable(&fbdev); + + buffer = FBDEV_GetFrameBuffer(&fbdev, 0); + + fill the buffer here. + + FBDEV_SetFrameBuffer(&fbdev, buffer, 0); + + ... + + @endcode + * + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief How many frame buffers used in each fbdev. */ +#ifndef FBDEV_MAX_FRAME_BUFFER +#define FBDEV_MAX_FRAME_BUFFER 3 +#endif + +#define FBDEV_DEFAULT_FRAME_BUFFER 2 + +/*! @brief Frame buffer information. */ +typedef struct _fbdev_fb_info +{ + uint8_t bufferCount; /*!< How many frame buffers used. */ + void *buffers[FBDEV_MAX_FRAME_BUFFER]; /*!< Address of the frame buffers */ + dc_fb_info_t bufInfo; /*!< Frame buffers information */ +} fbdev_fb_info_t; + +/*! @brief FBDEV handle, user should not touch the members directly. */ +typedef struct _fbdev +{ + fbdev_fb_info_t fbInfo; /*!< Frame buffer information. */ + video_stack_t fbManager; /*!< Manage the framebuffers used by this device. */ + void *buffers[FBDEV_MAX_FRAME_BUFFER]; /*!< Memory used by @ref fbManager, to save the free frame buffers. */ + const dc_fb_t *dc; /*!< Display controller handle. */ + uint8_t layer; /*!< Layer in the display controller. */ + bool enabled; /*!< The fbdev is enabled or not by @ref FBDEV_Enable. */ + rt_sem_t semaFbManager; /*!< Semaphore for the @ref fbManager. */ + rt_sem_t semaFramePending; /*!< Semaphore for the @ref framePending. */ +} fbdev_t; + +/*! @brief Flags used for FBDEV operations. */ +enum _fbdev_flag +{ + kFBDEV_NoWait = (1 << 0), /*!< Don't wait until available, but return directly. */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Open the FBDEV. + * + * @param fbdev The FBDEV handle. + * @param dc The display controller used. + * @param layer The layer in the display controller. + * @return Returns @ref kStatus_Success if success, otherwise returns + * error code. + */ +status_t FBDEV_Open(fbdev_t *fbdev, const dc_fb_t *dc, uint8_t layer); + +/*! + * @brief Close the FBDEV. + * + * @param fbdev The FBDEV handle. + * @return Returns @ref kStatus_Success if success, otherwise returns + * error code. + */ +status_t FBDEV_Close(fbdev_t *fbdev); + +/*! + * @brief Enable the FBDEV. + * + * After enabled, the FBDEV will be shown in the panel. This function should be + * called after @ref FBDEV_SetFrameBufferInfo. + * + * @param fbdev The FBDEV handle. + * @return Returns @ref kStatus_Success if success, otherwise returns + * error code. + */ +status_t FBDEV_Enable(fbdev_t *fbdev); + +/*! + * @brief Disable the FBDEV. + * + * After disabled, the FBDEV will not be shown in the panel. Don't call + * @ref FBDEV_SetFrameBuffer when the FBDEV is disabled. + * + * @param fbdev The FBDEV handle. + * @return Returns @ref kStatus_Success if success, otherwise returns + * error code. + */ +status_t FBDEV_Disable(fbdev_t *fbdev); + +/*! + * @brief Get the frame buffer information of the FBDEV. + * + * @param fbdev The FBDEV handle. + * @param info Pointer to the frame buffer information. + */ +void FBDEV_GetFrameBufferInfo(fbdev_t *fbdev, fbdev_fb_info_t *info); + +/*! + * @brief Set the frame buffer information of the FBDEV. + * + * This function could be used to configure the FRDEV, including set witdh, height, + * pixel format, frame buffers, and so on. This function should only be called once + * after @ref FBDEV_Open and before @ref FBDEV_Enable. + * + * @param fbdev The FBDEV handle. + * @param info Pointer to the frame buffer information. + * @return Returns @ref kStatus_Success if success, otherwise returns + * error code. + */ +status_t FBDEV_SetFrameBufferInfo(fbdev_t *fbdev, fbdev_fb_info_t *info); + +/*! + * @brief Get available frame buffer from the FBDEV. + * + * Upper layer could call this function to get an available frame buffer from + * the FBDEV, render send to show. + * + * @param fbdev The FBDEV handle. + * @param flags OR'ed value of @ref _fbdev_flag. If @ref kFBDEV_NoWait is used, + * the function returns NULL immediately if no available buffer. If @ref kFBDEV_NoWait + * is not used, this function waits until available. + * + * @return Returns the address of the frame buffer. If no available, returns NULL. + */ +void *FBDEV_GetFrameBuffer(fbdev_t *fbdev, uint32_t flags); + +/*! + * @brief Send frame buffer to the FBDEV. + * + * Upper layer could call this function to send a frame buffer to the FBDEV. This + * function should only be used when the FBDEV is enabled. + * + * @param fbdev The FBDEV handle. + * @param flags OR'ed value of @ref _fbdev_flag. If @ref kFBDEV_NoWait is used, + * the function returns NULL immediately if the previous frame buffer is pending. + * If @ref kFBDEV_NoWait is not used, this function waits until previous frame + * buffer not pending. + * + * @return Returns @ref kStatus_Success if success, otherwise returns + * error code. + */ +status_t FBDEV_SetFrameBuffer(fbdev_t *fbdev, void *frameBuffer, uint32_t flags); + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_FBDEV_H_ */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/display/fsl_display.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/display/fsl_display.h new file mode 100644 index 00000000000..c285cf7ab6d --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/display/fsl_display.h @@ -0,0 +1,140 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_DISPLAY_H_ +#define _FSL_DISPLAY_H_ + +#include "fsl_video_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Display common configuration. */ +typedef struct _display_common_cfg_t +{ + uint16_t width; + uint16_t height; + uint16_t hsw; /*!< HSYNC pulse width. */ + uint16_t hfp; /*!< Horizontal front porch. */ + uint16_t hbp; /*!< Horizontal back porch. */ + uint16_t vsw; /*!< VSYNC pulse width. */ + uint16_t vfp; /*!< Vrtical front porch. */ + uint16_t vbp; /*!< Vertical back porch. */ + uint32_t clock; /* !< pixecl clock in kHz>. */ +} display_common_cfg; + +/*! @brief Display control flags. */ +enum _display_flags +{ + kDISPLAY_VsyncActiveLow = 0U, /*!< VSYNC active low. */ + kDISPLAY_VsyncActiveHigh = (1U << 0U), /*!< VSYNC active high. */ + kDISPLAY_HsyncActiveLow = 0U, /*!< HSYNC active low. */ + kDISPLAY_HsyncActiveHigh = (1U << 1U), /*!< HSYNC active high. */ + kDISPLAY_DataEnableActiveHigh = 0U, /*!< Data enable line active high. */ + kDISPLAY_DataEnableActiveLow = (1U << 2U), /*!< Data enable line active low. */ + kDISPLAY_DataLatchOnRisingEdge = 0U, /*!< Latch data on rising clock edge. */ + kDISPLAY_DataLatchOnFallingEdge = (1U << 3U), /*!< Latch data on falling clock edge. */ +}; + +/*! @brief Display configuration. */ +typedef struct _display_config +{ + uint32_t resolution; /*!< Resolution, see @ref video_resolution_t and @ref FSL_VIDEO_RESOLUTION. */ + uint16_t hsw; /*!< HSYNC pulse width. */ + uint16_t hfp; /*!< Horizontal front porch. */ + uint16_t hbp; /*!< Horizontal back porch. */ + uint16_t vsw; /*!< VSYNC pulse width. */ + uint16_t vfp; /*!< Vrtical front porch. */ + uint16_t vbp; /*!< Vertical back porch. */ + uint32_t controlFlags; /*!< Control flags, OR'ed value of @ref _display_flags. */ + uint8_t dsiLanes; /*!< MIPI DSI data lanes number. */ + uint32_t pixelClock_Hz; /*!< Pixel clock in Hz. */ + video_pixel_format_t pixelFormat; /*!< Pixel format. */ +} display_config_t; + +typedef struct _display_handle display_handle_t; + +/*! @brief Display device operations. */ +typedef struct _display_operations +{ + status_t (*init)(display_handle_t *handle, const display_config_t *config); /*!< Init the device. */ + status_t (*deinit)(display_handle_t *handle); /*!< Deinit the device. */ + status_t (*start)(display_handle_t *handle); /*!< Start the device. */ + status_t (*stop)(display_handle_t *handle); /*!< Stop the device. */ +} display_operations_t; + +/*! @brief Display handle. */ +struct _display_handle +{ + const void *resource; + const display_operations_t *ops; + uint16_t width; + uint16_t height; + video_pixel_format_t pixelFormat; +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Initializes the display device with user defined configuration. + * + * @param handle Display device handle. + * @param config Pointer to the user-defined configuration structure. + * @return Returns @ref kStatus_Success if initialize success, otherwise returns + * error code. + */ +static inline status_t DISPLAY_Init(display_handle_t *handle, const display_config_t *config) +{ + return handle->ops->init(handle, config); +} + +/*! + * @brief Deinitialize the display device. + * + * @param handle Display device handle. + * @return Returns @ref kStatus_Success if success, otherwise returns error code. + */ +static inline status_t DISPLAY_Deinit(display_handle_t *handle) +{ + return handle->ops->deinit(handle); +} + +/*! + * @brief Start the display device. + * + * @param handle Display device handle. + * @return Returns @ref kStatus_Success if success, otherwise returns error code. + */ +static inline status_t DISPLAY_Start(display_handle_t *handle) +{ + return handle->ops->start(handle); +} + +/*! + * @brief Stop the display device. + * + * @param handle Display device handle. + * @return Returns @ref kStatus_Success if success, otherwise returns error code. + */ +static inline status_t DISPLAY_Stop(display_handle_t *handle) +{ + return handle->ops->stop(handle); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_DISPLAY_H_ */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/display/hx8394/fsl_hx8394.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/display/hx8394/fsl_hx8394.c new file mode 100644 index 00000000000..91303ce47c3 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/display/hx8394/fsl_hx8394.c @@ -0,0 +1,187 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_display.h" +#include "fsl_hx8394.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define HX8394_DelayMs VIDEO_DelayMs + +typedef struct +{ + const uint8_t *cmd; + uint8_t cmdLen; +} hx8394_cmd_t; + +/******************************************************************************* + * Variables + ******************************************************************************/ +const display_operations_t hx8394_ops = { + .init = HX8394_Init, + .deinit = HX8394_Deinit, + .start = HX8394_Start, + .stop = HX8394_Stop, +}; + +static const hx8394_cmd_t s_hx8394Cmds[] = { + {(const uint8_t[]){0x36U, 0x02U}, 2U}, + + {(const uint8_t[]){0xB1U, 0x48U, 0x12U, 0x72U, 0x09U, 0x32U, 0x54U, 0x71U, 0x71U, 0x57U, 0x47U}, 11U}, + + {(const uint8_t[]){0xB2U, 0x00U, 0x80U, 0x64U, 0x0CU, 0x0DU, 0x2FU}, 7U}, + + {(const uint8_t[]){0xB4U, 0x73U, 0x74U, 0x73U, 0x74U, 0x73U, 0x74U, 0x01U, 0x0CU, 0x86U, /* 10 */ + 0x75U, 0x00U, 0x3FU, 0x73U, 0x74U, 0x73U, 0x74U, 0x73U, 0x74U, 0x01U, /* 20 */ + 0x0CU, 0x86U}, + 22U}, + + {(const uint8_t[]){0xD3U, 0x00U, 0x00U, 0x07U, 0x07U, 0x40U, 0x07U, 0x0CU, 0x00U, 0x08U, /* 10 */ + 0x10U, 0x08U, 0x00U, 0x08U, 0x54U, 0x15U, 0x0AU, 0x05U, 0x0AU, 0x02U, /* 20 */ + 0x15U, 0x06U, 0x05U, 0x06U, 0x47U, 0x44U, 0x0AU, 0x0AU, 0x4BU, 0x10U, /* 30 */ + 0x07U, 0x07U, 0x0CU, 0x40U}, + 34U}, + + {(const uint8_t[]){0xD5U, 0x1CU, 0x1CU, 0x1DU, 0x1DU, 0x00U, 0x01U, 0x02U, 0x03U, 0x04U, /* 10 */ + 0x05U, 0x06U, 0x07U, 0x08U, 0x09U, 0x0AU, 0x0BU, 0x24U, 0x25U, 0x18U, /* 20 */ + 0x18U, 0x26U, 0x27U, 0x18U, 0x18U, 0x18U, 0x18U, 0x18U, 0x18U, 0x18U, /* 30 */ + 0x18U, 0x18U, 0x18U, 0x18U, 0x18U, 0x18U, 0x18U, 0x18U, 0x18U, 0x20U, /* 40 */ + 0x21U, 0x18U, 0x18U, 0x18U, 0x18U}, + 45U}, + + {(const uint8_t[]){0xD6U, 0x1CU, 0x1CU, 0x1DU, 0x1DU, 0x07U, 0x06U, 0x05U, 0x04U, 0x03U, /* 10 */ + 0x02U, 0x01U, 0x00U, 0x0BU, 0x0AU, 0x09U, 0x08U, 0x21U, 0x20U, 0x18U, /* 20 */ + 0x18U, 0x27U, 0x26U, 0x18U, 0x18U, 0x18U, 0x18U, 0x18U, 0x18U, 0x18U, /* 30 */ + 0x18U, 0x18U, 0x18U, 0x18U, 0x18U, 0x18U, 0x18U, 0x18U, 0x18U, 0x25U, /* 40 */ + 0x24U, 0x18U, 0x18U, 0x18U, 0x18U}, + 45U}, + + {(const uint8_t[]){0xB6U, 0x92U, 0x92U}, 3U}, + + {(const uint8_t[]){0xE0U, 0x00U, 0x0AU, 0x15U, 0x1BU, 0x1EU, 0x21U, 0x24U, 0x22U, 0x47U, /* 10 */ + 0x56U, 0x65U, 0x66U, 0x6EU, 0x82U, 0x88U, 0x8BU, 0x9AU, 0x9DU, 0x98U, /* 20 */ + 0xA8U, 0xB9U, 0x5DU, 0x5CU, 0x61U, 0x66U, 0x6AU, 0x6FU, 0x7FU, 0x7FU, /* 30 */ + 0x00U, 0x0AU, 0x15U, 0x1BU, 0x1EU, 0x21U, 0x24U, 0x22U, 0x47U, 0x56U, /* 40 */ + 0x65U, 0x65U, 0x6EU, 0x81U, 0x87U, 0x8BU, 0x98U, 0x9DU, 0x99U, 0xA8U, /* 50 */ + 0xBAU, 0x5DU, 0x5DU, 0x62U, 0x67U, 0x6BU, 0x72U, 0x7FU, 0x7FU}, + 59U}, + + {(const uint8_t[]){0xC0U, 0x1FU, 0x31U}, 3U}, + {(const uint8_t[]){0xCCU, 0x03U}, 2U}, + {(const uint8_t[]){0xD4U, 0x02U}, 2U}, + {(const uint8_t[]){0xBDU, 0x02U}, 2U}, + + {(const uint8_t[]){0xD8U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, /* 10 */ + 0xFFU, 0xFFU, 0xFFU}, + 13U}, + + {(const uint8_t[]){0xBDU, 0x00U}, 2U}, + {(const uint8_t[]){0xBDU, 0x01U}, 2U}, + {(const uint8_t[]){0xB1U, 0x00U}, 2U}, + {(const uint8_t[]){0xBDU, 0x00U}, 2U}, + + {(const uint8_t[]){0xBFU, 0x40U, 0x81U, 0x50U, 0x00U, 0x1AU, 0xFCU, 0x01}, 8U}, + + {(const uint8_t[]){0xC6U, 0xEDU}, 2U}, + + {(const uint8_t[]){0x35U, 0x00U}, 2U}, +}; + +/******************************************************************************* + * Code + ******************************************************************************/ + +status_t HX8394_Init(display_handle_t *handle, const display_config_t *config) +{ + uint8_t i; + status_t status = kStatus_Success; + const hx8394_resource_t *resource = (const hx8394_resource_t *)(handle->resource); + mipi_dsi_device_t *dsiDevice = resource->dsiDevice; + uint8_t setmipi[7] = {0xBAU, 0x60U, 0x03U, 0x68U, 0x6BU, 0xB2U, 0xC0U}; + + /* Only support 720 * 1280 */ + if (config->resolution != FSL_VIDEO_RESOLUTION(720, 1280)) + { + return kStatus_InvalidArgument; + } + + /* Power on. */ + resource->pullPowerPin(true); + HX8394_DelayMs(1); + + /* Perform reset. */ + resource->pullResetPin(false); + HX8394_DelayMs(1); + resource->pullResetPin(true); + HX8394_DelayMs(50U); + + status = MIPI_DSI_GenericWrite(dsiDevice, (const uint8_t[]){0xB9U, 0xFFU, 0x83U, 0x94U}, 4); + + setmipi[1] |= (config->dsiLanes - 1U); + + if (kStatus_Success == status) + { + status = MIPI_DSI_GenericWrite(dsiDevice, setmipi, 7); + } + + if (kStatus_Success == status) + { + for (i = 0; i < ARRAY_SIZE(s_hx8394Cmds); i++) + { + status = MIPI_DSI_GenericWrite(dsiDevice, s_hx8394Cmds[i].cmd, (int32_t)s_hx8394Cmds[i].cmdLen); + + if (kStatus_Success != status) + { + break; + } + } + } + + if (kStatus_Success == status) + { + status = MIPI_DSI_DCS_EnterSleepMode(dsiDevice, false); + } + + if (kStatus_Success == status) + { + HX8394_DelayMs(120U); + + status = MIPI_DSI_DCS_SetDisplayOn(dsiDevice, true); + } + + return status; +} + +status_t HX8394_Deinit(display_handle_t *handle) +{ + const hx8394_resource_t *resource = (const hx8394_resource_t *)(handle->resource); + mipi_dsi_device_t *dsiDevice = resource->dsiDevice; + + (void)MIPI_DSI_DCS_EnterSleepMode(dsiDevice, true); + + resource->pullResetPin(false); + resource->pullPowerPin(false); + + return kStatus_Success; +} + +status_t HX8394_Start(display_handle_t *handle) +{ + const hx8394_resource_t *resource = (const hx8394_resource_t *)(handle->resource); + mipi_dsi_device_t *dsiDevice = resource->dsiDevice; + + return MIPI_DSI_DCS_SetDisplayOn(dsiDevice, true); +} + +status_t HX8394_Stop(display_handle_t *handle) +{ + const hx8394_resource_t *resource = (const hx8394_resource_t *)(handle->resource); + mipi_dsi_device_t *dsiDevice = resource->dsiDevice; + + return MIPI_DSI_DCS_SetDisplayOn(dsiDevice, false); +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/display/hx8394/fsl_hx8394.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/display/hx8394/fsl_hx8394.h new file mode 100644 index 00000000000..b33aea98ac5 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/display/hx8394/fsl_hx8394.h @@ -0,0 +1,57 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_HX8394_H_ +#define _FSL_HX8394_H_ + +#include "fsl_display.h" +#include "fsl_mipi_dsi_cmd.h" + +/* + * Change log: + * + * 1.0.0 + * - Initial version + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief HX8394 resource. + */ +typedef struct _hx8394_resource +{ + mipi_dsi_device_t *dsiDevice; /*!< MIPI DSI device. */ + void (*pullResetPin)(bool pullUp); /*!< Function to pull reset pin high or low. */ + void (*pullPowerPin)(bool pullUp); /*!< Function to pull power pin high or low. */ +} hx8394_resource_t; + +extern const display_operations_t hx8394_ops; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +status_t HX8394_Init(display_handle_t *handle, const display_config_t *config); + +status_t HX8394_Deinit(display_handle_t *handle); + +status_t HX8394_Start(display_handle_t *handle); + +status_t HX8394_Stop(display_handle_t *handle); + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_HX8394_H_ */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/display/mipi_dsi_cmd/fsl_mipi_dsi_cmd.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/display/mipi_dsi_cmd/fsl_mipi_dsi_cmd.c new file mode 100644 index 00000000000..e9ff8f6561a --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/display/mipi_dsi_cmd/fsl_mipi_dsi_cmd.c @@ -0,0 +1,351 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_mipi_dsi_cmd.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +status_t MIPI_DSI_DCS_SoftReset(mipi_dsi_device_t *device) +{ + dsi_transfer_t dsiXfer = {0}; + uint8_t txData = (uint8_t)kMIPI_DCS_SoftReset; + + dsiXfer.virtualChannel = device->virtualChannel; + dsiXfer.txDataType = kDSI_TxDataDcsShortWrNoParam; + dsiXfer.txDataSize = 1; + dsiXfer.txData = &txData; + + return device->xferFunc(&dsiXfer); +} + +status_t MIPI_DSI_DCS_SetDisplayOn(mipi_dsi_device_t *device, bool on) +{ + dsi_transfer_t dsiXfer = {0}; + uint8_t txData; + + dsiXfer.virtualChannel = device->virtualChannel; + dsiXfer.txDataType = kDSI_TxDataDcsShortWrNoParam; + dsiXfer.txDataSize = 1; + dsiXfer.txData = &txData; + + if (on) + { + txData = (uint8_t)kMIPI_DCS_SetDisplayOn; + } + else + { + txData = (uint8_t)kMIPI_DCS_SetDisplayOff; + } + + return device->xferFunc(&dsiXfer); +} + +status_t MIPI_DSI_DCS_SetPixelFormat(mipi_dsi_device_t *device, + mipi_dsc_pixel_format_t dbiFormat, + mipi_dsc_pixel_format_t dpiFormat) +{ + dsi_transfer_t dsiXfer = {0}; + uint8_t txData[2]; + + dsiXfer.virtualChannel = device->virtualChannel; + dsiXfer.txDataType = kDSI_TxDataDcsShortWrOneParam; + dsiXfer.txDataSize = 2; + dsiXfer.txData = txData; + + txData[0] = (uint8_t)kMIPI_DCS_SetPixelFormat; + txData[1] = ((uint8_t)dbiFormat << 0U) | ((uint8_t)dpiFormat << 4U); + + return device->xferFunc(&dsiXfer); +} + +status_t MIPI_DSI_DCS_EnterSleepMode(mipi_dsi_device_t *device, bool enter) +{ + dsi_transfer_t dsiXfer = {0}; + uint8_t txData; + + dsiXfer.virtualChannel = device->virtualChannel; + dsiXfer.txDataType = kDSI_TxDataDcsShortWrNoParam; + dsiXfer.txDataSize = 1; + dsiXfer.txData = &txData; + + if (enter) + { + txData = (uint8_t)kMIPI_DCS_EnterSleepMode; + } + else + { + txData = (uint8_t)kMIPI_DCS_ExitSleepMode; + } + + return device->xferFunc(&dsiXfer); +} + +status_t MIPI_DSI_DCS_EnterPartialMode(mipi_dsi_device_t *device, bool enter) +{ + dsi_transfer_t dsiXfer = {0}; + uint8_t txData; + + dsiXfer.virtualChannel = device->virtualChannel; + dsiXfer.txDataType = kDSI_TxDataDcsShortWrNoParam; + dsiXfer.txDataSize = 1; + dsiXfer.txData = &txData; + + if (enter) + { + txData = (uint8_t)kMIPI_DCS_EnterPartialMode; + } + else + { + txData = (uint8_t)kMIPI_DCS_EnterNormalMode; + } + + return device->xferFunc(&dsiXfer); +} + +status_t MIPI_DSI_DCS_EnterInvertMode(mipi_dsi_device_t *device, bool enter) +{ + dsi_transfer_t dsiXfer = {0}; + uint8_t txData; + + dsiXfer.virtualChannel = device->virtualChannel; + dsiXfer.txDataType = kDSI_TxDataDcsShortWrNoParam; + dsiXfer.txDataSize = 1; + dsiXfer.txData = &txData; + + if (enter) + { + txData = (uint8_t)kMIPI_DCS_EnterInvertMode; + } + else + { + txData = (uint8_t)kMIPI_DCS_ExitInvertMode; + } + + return device->xferFunc(&dsiXfer); +} + +status_t MIPI_DSI_DCS_EnterIdleMode(mipi_dsi_device_t *device, bool enter) +{ + dsi_transfer_t dsiXfer = {0}; + uint8_t txData; + + dsiXfer.virtualChannel = device->virtualChannel; + dsiXfer.txDataType = kDSI_TxDataDcsShortWrNoParam; + dsiXfer.txDataSize = 1; + dsiXfer.txData = &txData; + + if (enter) + { + txData = (uint8_t)kMIPI_DCS_EnterIdleMode; + } + else + { + txData = (uint8_t)kMIPI_DCS_ExitIdleMode; + } + + return device->xferFunc(&dsiXfer); +} + +status_t MIPI_DSI_DCS_Write(mipi_dsi_device_t *device, const uint8_t *txData, int32_t txDataSize) +{ + dsi_transfer_t dsiXfer = {0}; + + dsiXfer.virtualChannel = device->virtualChannel; + dsiXfer.txDataSize = (uint16_t)txDataSize; + dsiXfer.txData = txData; + + if (0 == txDataSize) + { + /* For DSC command, the data size should not be 0. */ + return kStatus_InvalidArgument; + } + else if (1 == txDataSize) + { + dsiXfer.txDataType = kDSI_TxDataDcsShortWrNoParam; + } + else if (2 == txDataSize) + { + dsiXfer.txDataType = kDSI_TxDataDcsShortWrOneParam; + } + else + { + dsiXfer.txDataType = kDSI_TxDataDcsLongWr; + } + + return device->xferFunc(&dsiXfer); +} + +status_t MIPI_DSI_GenericWrite(mipi_dsi_device_t *device, const uint8_t *txData, int32_t txDataSize) +{ + dsi_transfer_t dsiXfer = {0}; + + dsiXfer.virtualChannel = device->virtualChannel; + dsiXfer.txDataSize = (uint16_t)txDataSize; + dsiXfer.txData = txData; + + if (0 == txDataSize) + { + dsiXfer.txDataType = kDSI_TxDataGenShortWrNoParam; + } + else if (1 == txDataSize) + { + dsiXfer.txDataType = kDSI_TxDataGenShortWrOneParam; + } + else if (2 == txDataSize) + { + dsiXfer.txDataType = kDSI_TxDataGenShortWrTwoParam; + } + else + { + dsiXfer.txDataType = kDSI_TxDataGenLongWr; + } + + return device->xferFunc(&dsiXfer); +} + +status_t MIPI_DSI_DCS_SetMaxReturnPktSize(mipi_dsi_device_t *device, uint16_t sizeBytes) +{ + dsi_transfer_t dsiXfer = {0}; + + dsiXfer.virtualChannel = device->virtualChannel; + dsiXfer.txDataType = kDSI_TxDataSetMaxReturnPktSize; + dsiXfer.txDataSize = 2; + dsiXfer.txData = (uint8_t *)&sizeBytes; + + return device->xferFunc(&dsiXfer); +} + +status_t MIPI_DSI_GenericRead( + mipi_dsi_device_t *device, const uint8_t *txData, int32_t txDataSize, uint8_t *rxData, int32_t *rxDataSize) +{ + status_t status; + dsi_transfer_t dsiXfer = {0}; + + dsiXfer.virtualChannel = device->virtualChannel; + dsiXfer.txDataSize = (uint16_t)txDataSize; + dsiXfer.txData = txData; + dsiXfer.rxDataSize = (uint16_t)*rxDataSize; + dsiXfer.rxData = rxData; + + *rxDataSize = 0; + + if (0 == txDataSize) + { + dsiXfer.txDataType = kDSI_TxDataGenShortRdNoParam; + } + else if (1 == txDataSize) + { + dsiXfer.txDataType = kDSI_TxDataGenShortRdOneParam; + } + else if (2 == txDataSize) + { + dsiXfer.txDataType = kDSI_TxDataGenShortRdTwoParam; + } + else + { + return kStatus_InvalidArgument; + } + + status = device->xferFunc(&dsiXfer); + + /* Return actual received size. */ + *rxDataSize = (int32_t)dsiXfer.rxDataSize; + + return status; +} + +status_t MIPI_DSI_ReadCMD(mipi_dsi_device_t *device, enum _mipi_dcs dcsCmd, uint8_t *rxData, int32_t *rxDataSize) +{ + uint8_t txData[2]; + status_t status = kStatus_Fail; + + txData[0] = (uint8_t)dcsCmd; + if (kStatus_Success == MIPI_DSI_DCS_SetMaxReturnPktSize(device, (uint16_t)*rxDataSize)) + { + status = MIPI_DSI_GenericRead(device, txData, 1, rxData, rxDataSize); + } + + return status; +} + +status_t MIPI_DSI_SelectArea(mipi_dsi_device_t *device, uint16_t startX, uint16_t startY, uint16_t endX, uint16_t endY) +{ + status_t status; + dsi_transfer_t dsiXfer = {0}; + uint8_t txData[4]; + + dsiXfer.virtualChannel = device->virtualChannel; + dsiXfer.txDataType = kDSI_TxDataDcsLongWr; + dsiXfer.txDataSize = 4; + dsiXfer.txData = txData; + dsiXfer.sendDscCmd = true; + dsiXfer.dscCmd = (uint8_t)kMIPI_DCS_SetColumnAddress; + + txData[0] = (uint8_t)((startX >> 8U) & 0xFFU); + txData[1] = (uint8_t)(startX & 0xFFU); + txData[2] = (uint8_t)((endX >> 8U) & 0xFFU); + txData[3] = (uint8_t)(endX & 0xFFU); + + status = device->xferFunc(&dsiXfer); + + if (kStatus_Success != status) + { + return status; + } + + dsiXfer.dscCmd = (uint8_t)kMIPI_DCS_SetPageAddress; + txData[0] = (uint8_t)((startY >> 8U) & 0xFFU); + txData[1] = (uint8_t)(startY & 0xFFU); + txData[2] = (uint8_t)((endY >> 8U) & 0xFFU); + txData[3] = (uint8_t)(endY & 0xFFU); + + return device->xferFunc(&dsiXfer); +} + +status_t MIPI_DSI_WriteMemory(mipi_dsi_device_t *device, const uint8_t *data, uint32_t length) +{ + return device->memWriteFunc(device->virtualChannel, data, length); +} + +status_t MIPI_DSI_WriteMemory2D( + mipi_dsi_device_t *device, const uint8_t *data, uint32_t minorLoop, uint32_t minorLoopOffset, uint32_t majorLoop) +{ + if (device->memWriteFunc2D != NULL) + { + return device->memWriteFunc2D(device->virtualChannel, data, minorLoop, minorLoopOffset, majorLoop); + } + else + { + return kStatus_Fail; + } +} + +void MIPI_DSI_SetMemoryDoneCallback(mipi_dsi_device_t *device, mipi_dsi_mem_done_callback_t callback, void *userData) +{ + device->callback = callback; + device->userData = userData; +} + +void MIPI_DSI_MemoryDoneDriverCallback(status_t status, void *userData) +{ + mipi_dsi_device_t *device = (mipi_dsi_device_t *)userData; + + if (NULL != device->callback) + { + device->callback(status, device->userData); + } +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/display/mipi_dsi_cmd/fsl_mipi_dsi_cmd.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/display/mipi_dsi_cmd/fsl_mipi_dsi_cmd.h new file mode 100644 index 00000000000..2843d8c55d7 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/display/mipi_dsi_cmd/fsl_mipi_dsi_cmd.h @@ -0,0 +1,354 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_MIPI_DSI_CMD_H_ +#define _FSL_MIPI_DSI_CMD_H_ + +#include "fsl_common.h" +#include "fsl_mipi_dsi.h" + +/* + * Change log: + * + * 1.0.2 + * - Fix MISRA-C 2012 issues. + * + * 1.0.1 + * - Add more functions for panel works in command mode. + * + * 1.0.0 + * - Initial version + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +enum _mipi_dcs +{ + kMIPI_DCS_Nop = 0x00, + kMIPI_DCS_SoftReset = 0x01, + kMIPI_DCS_GetRedChannel = 0x06, + kMIPI_DCS_GetGreenChannel = 0x07, + kMIPI_DCS_GetBlueChannel = 0x08, + kMIPI_DCS_GetPowerMode = 0x0A, + kMIPI_DCS_GetAddressMode = 0x0B, + kMIPI_DCS_GetPixelFormat = 0x0C, + kMIPI_DCS_GetDisplayMode = 0x0D, + kMIPI_DCS_GetSignalMode = 0x0E, + kMIPI_DCS_GetDiagnosticResult = 0x0F, + kMIPI_DCS_EnterSleepMode = 0x10, + kMIPI_DCS_ExitSleepMode = 0x11, + kMIPI_DCS_EnterPartialMode = 0x12, + kMIPI_DCS_EnterNormalMode = 0x13, + kMIPI_DCS_ExitInvertMode = 0x20, + kMIPI_DCS_EnterInvertMode = 0x21, + kMIPI_DCS_SetGammaCurve = 0x26, + kMIPI_DCS_SetDisplayOff = 0x28, + kMIPI_DCS_SetDisplayOn = 0x29, + kMIPI_DCS_SetColumnAddress = 0x2a, + kMIPI_DCS_SetPageAddress = 0x2b, + kMIPI_DCS_WriteMemoryStart = 0x2C, + kMIPI_DCS_WriteLUT = 0x2D, + kMIPI_DCS_ReadMemoryStart = 0x2E, + kMIPI_DCS_SetPartialRows = 0x30, + kMIPI_DCS_SetPartialColumns = 0x31, + kMIPI_DCS_SetScrollArea = 0x33, + kMIPI_DCS_SetTearOff = 0x34, + kMIPI_DCS_SetTearOn = 0x35, + kMIPI_DCS_SetAddressMode = 0x36, + kMIPI_DCS_SetScrollStart = 0x37, + kMIPI_DCS_ExitIdleMode = 0x38, + kMIPI_DCS_EnterIdleMode = 0x39, + kMIPI_DCS_SetPixelFormat = 0x3A, + kMIPI_DCS_WriteMemoryContinue = 0x3C, + kMIPI_DCS_Set3DControl = 0x3D, + kMIPI_DCS_ReadMemoryContinue = 0x3E, + kMIPI_DCS_Get3DControl = 0x3F, + kMIPI_DCS_SetVsyncTiming = 0x40, + kMIPI_DCS_SetTearScanline = 0x44, + kMIPI_DCS_GetScanline = 0x45, + kMIPI_DCS_SetDisplayBrightness = 0x51, + kMIPI_DCS_GetDisplayBrightness = 0x52, + kMIPI_DCS_WriteControlDisplay = 0x53, + kMIPI_DCS_GetControlDisplay = 0x54, + kMIPI_DCS_WritePowerSave = 0x55, + kMIPI_DCS_GetPowerSave = 0x56, + kMIPI_DCS_SetCABCMinBrightness = 0x5E, + kMIPI_DCS_GetCABCMinBrightness = 0x5F, + kMIPI_DCS_ReadDDBStart = 0xA1, + kMIPI_DCS_ReadDDBContinue = 0xA8, +}; + +/*! + * @brief Pixel format used by DSC command. + */ +typedef enum _mipi_dsc_pixel_format +{ + kMIPI_DCS_Pixel3Bits = 1U, /*!< 3-bit per pixel. */ + kMIPI_DCS_Pixel8Bits = 2U, /*!< 8-bit per pixel. */ + kMIPI_DCS_Pixel12Bits = 3U, /*!< 12-bit per pixel. */ + kMIPI_DCS_Pixel16Bits = 5U, /*!< 16-bit per pixel. */ + kMIPI_DCS_Pixel18Bits = 6U, /*!< 18-bit per pixel. */ + kMIPI_DCS_Pixel24Bits = 7U, /*!< 24-bit per pixel. */ +} mipi_dsc_pixel_format_t; + +/*! + * @brief Callback function when the write memory finished. + * + * If transfer done successfully, the @p status is kStatus_Success. + */ +typedef void (*mipi_dsi_mem_done_callback_t)(status_t status, void *userData); + +/*! @brief MIPI DSI transfer function. */ +typedef status_t (*mipi_dsi_transfer_func_t)(dsi_transfer_t *xfer); + +/*! @brief MIPI DSI memory write function. */ +typedef status_t (*mipi_dsi_mem_write_func_t)(uint8_t virtualChannel, const uint8_t *data, uint32_t length); + +/*! @brief MIPI DSI memory write function using 2-dimensional way. */ +typedef status_t (*mipi_dsi_mem_write_func_2D_t)( + uint8_t virtualChannel, const uint8_t *data, uint32_t minorLoop, uint32_t minorLoopOffset, uint32_t majorLoop); + +/*! @brief MIPI DSI device. */ +typedef struct _mipi_dsi_device +{ + uint8_t virtualChannel; + mipi_dsi_transfer_func_t xferFunc; + mipi_dsi_mem_write_func_t memWriteFunc; /*!< Function to write display memory, + it should be non-blocking function and + notify upper layer using callback when finished. + Not used when panel works in video mode. */ + mipi_dsi_mem_write_func_2D_t memWriteFunc2D; /*!< Function to write display memory using 2-dimensional way, + it should be non-blocking function and + notify upper layer using callback when finished. + Not used when panel works in video mode. */ + mipi_dsi_mem_done_callback_t callback; /*!< The callback function to notify upper layer + that memory write done. Not used when panel + works in video mode. */ + void *userData; /*!< Parameter for the memory write done callback. + not used when panel works in video mode. */ +} mipi_dsi_device_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Send software reset to MIPI DSI device. + * + * @param device The MIPI DSI device. + * @return Returns @ref kStatus_Success if success, otherwise returns error code. + */ +status_t MIPI_DSI_DCS_SoftReset(mipi_dsi_device_t *device); + +/*! + * @brief Set display on or off. + * + * @param device The MIPI DSI device. + * @param on Set true to turn on, false to turn off. + * @return Returns @ref kStatus_Success if success, otherwise returns error code. + */ +status_t MIPI_DSI_DCS_SetDisplayOn(mipi_dsi_device_t *device, bool on); + +/*! + * @brief Enter or exit sleep mode. + * + * @param device The MIPI DSI device. + * @param enter Set true to enter sleep mode, false to exit. + * @return Returns @ref kStatus_Success if success, otherwise returns error code. + */ +status_t MIPI_DSI_DCS_EnterSleepMode(mipi_dsi_device_t *device, bool enter); + +/*! + * @brief Enter or exit partial mode. + * + * @param device The MIPI DSI device. + * @param enter Set true to enter partial mode, false to exit. + * @return Returns @ref kStatus_Success if success, otherwise returns error code. + */ +status_t MIPI_DSI_DCS_EnterPartialMode(mipi_dsi_device_t *device, bool enter); + +/*! + * @brief Enter or exit invert mode. + * + * @param device The MIPI DSI device. + * @param enter Set true to enter invert mode, false to exit. + * @return Returns @ref kStatus_Success if success, otherwise returns error code. + */ +status_t MIPI_DSI_DCS_EnterInvertMode(mipi_dsi_device_t *device, bool enter); + +/*! + * @brief Enter or exit idle mode. + * + * @param device The MIPI DSI device. + * @param enter Set true to enter idle mode, false to exit. + * @return Returns @ref kStatus_Success if success, otherwise returns error code. + */ +status_t MIPI_DSI_DCS_EnterIdleMode(mipi_dsi_device_t *device, bool enter); + +/*! + * @brief Send DCS command. + * + * @param device The MIPI DSI device. + * @param txData The data to send. + * @param txDataSize Size of the data to send (in bytes). + * @return Returns @ref kStatus_Success if success, otherwise returns error code. + */ +status_t MIPI_DSI_DCS_Write(mipi_dsi_device_t *device, const uint8_t *txData, int32_t txDataSize); + +/*! + * @brief Send generic data. + * + * @param device The MIPI DSI device. + * @param txData The data to send. + * @param txDataSize Size of the data to send (in bytes). + * @return Returns @ref kStatus_Success if success, otherwise returns error code. + */ +status_t MIPI_DSI_GenericWrite(mipi_dsi_device_t *device, const uint8_t *txData, int32_t txDataSize); + +/*! + * @brief Set the maximum return data length. + * + * @param device The MIPI DSI device. + * @param sizeBytes Maximum return data length. + * @return Returns @ref kStatus_Success if success, otherwise returns error code. + */ +status_t MIPI_DSI_DCS_SetMaxReturnPktSize(mipi_dsi_device_t *device, uint16_t sizeBytes); + +/*! + * @brief Generic read. + * + * @param device The MIPI DSI device. + * @param txData The data to send before read. + * @param txDataSize Size of the data to send (in bytes). + * @param rxData The data to read. + * @param rxDataSize Size of the data to read (in bytes), after this function returns, + * it is the actual read length. + * @return Returns @ref kStatus_Success if success, otherwise returns error code. + */ +status_t MIPI_DSI_GenericRead( + mipi_dsi_device_t *device, const uint8_t *txData, int32_t txDataSize, uint8_t *rxData, int32_t *rxDataSize); + +/*! + * @brief Read DCS command(read type command, such as: Get Display ID). + * + * @param device The MIPI DSI device. + * @param dcsCmd The command to send before read. + * @param rxData The data to read. + * @param rxDataSize Size of the data to read (in bytes), after this function returns, + * it is the actual read length. + * @return Returns @ref kStatus_Success if success, otherwise returns error code. + */ +status_t MIPI_DSI_ReadCMD(mipi_dsi_device_t *device, enum _mipi_dcs dcsCmd, uint8_t *rxData, int32_t *rxDataSize); + +/*! + * @brief Set the panel pixel format. + * + * @param device The MIPI DSI device. + * @param dbiFormat The DBI interface pixel format. + * @param dpiFormat The DPI interface pixel format. + * @return Returns @ref kStatus_Success if success, otherwise returns error code. + */ +status_t MIPI_DSI_DCS_SetPixelFormat(mipi_dsi_device_t *device, + mipi_dsc_pixel_format_t dbiFormat, + mipi_dsc_pixel_format_t dpiFormat); + +/*! + * @brief Select area to write or read pixels. + * + * @param device The MIPI DSI device. + * @param startX Start point X coordination. + * @param startY Start point Y coordination. + * @param endX End point X coordination. + * @param endY End point Y coordination. + * @return Returns @ref kStatus_Success if success, otherwise returns error code. + */ +status_t MIPI_DSI_SelectArea(mipi_dsi_device_t *device, uint16_t startX, uint16_t startY, uint16_t endX, uint16_t endY); + +/*! + * @brief Send pixel data to the display controller's frame memory. + * + * The pixels will be shown in the region selected by @ref MIPI_DSI_SelectArea. + * This function is non-blocking function, user should install callback function + * using @ref MIPI_DSI_SetMemoryDoneCallback to get informed when write finished. + * + * @param device The MIPI DSI device. + * @param data The pixel data to send. + * @param length Length of the data in byte. + * @return Returns @ref kStatus_Success if success, otherwise returns error code. + */ +status_t MIPI_DSI_WriteMemory(mipi_dsi_device_t *device, const uint8_t *data, uint32_t length); + +/*! + * @brief Send pixel data to the display controller's frame memory in 2-dinmensional way. + * + * The pixels will be shown in the region selected by @ref MIPI_DSI_SelectArea. + * This function is non-blocking function, user should install callback function + * using @ref MIPI_DSI_SetMemoryDoneCallback to get informed when write finished. + * + * @verbatim + * +---------------------------------------------------+ + * | | + * | data | + * | +-------------------+ | + * | | minorLoop | | + * | | | | + * | | | majorLoop | + * | | | | + * | | | | + * | +-------------------+ | + * | | + * | minorLoop + minorLoopOffset | + * +---------------------------------------------------+ + * @endverbatim + * + * @param device The MIPI DSI device. + * @param data The pixel data to send. + * @param minorLoop Count of the data in one line in byte. + * @param minorLoopOffset The offset between line stride and the count of one line in byte. + * @param majorLoop Count of the lines in byte. + * @return Returns @ref kStatus_Success if success, otherwise returns error code. + */ +status_t MIPI_DSI_WriteMemory2D( + mipi_dsi_device_t *device, const uint8_t *data, uint32_t minorLoop, uint32_t minorLoopOffset, uint32_t majorLoop); + +/*! + * @brief Install the callback called when write memory finished. + * + * Upper layer should install callback function using this function to + * get memory write done notification. + * + * @param device The MIPI DSI device. + * @param callback The callback function to inform upper layer that memory write done. + * @param userData Parameter used by the callback. + * @return Returns @ref kStatus_Success if success, otherwise returns error code. + */ +void MIPI_DSI_SetMemoryDoneCallback(mipi_dsi_device_t *device, mipi_dsi_mem_done_callback_t callback, void *userData); + +/*! + * @brief The callback function lower layer should call when write memory finished. + * + * When implement the @ref mipi_dsi_device_t, this function should be called when + * the memory writing finished. The parameter @p userData should be pointer to the + * @ref mipi_dsi_device_t. + * + * @param status The memory writing result. @ref kStatus_Success if success. + * @param userData Must be pointer to the @ref mipi_dsi_device_t instance. + */ +void MIPI_DSI_MemoryDoneDriverCallback(status_t status, void *userData); + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_MIPI_DSI_CMD_H_ */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/display/rm68191/fsl_rm68191.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/display/rm68191/fsl_rm68191.c new file mode 100644 index 00000000000..3ca01fb28e9 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/display/rm68191/fsl_rm68191.c @@ -0,0 +1,251 @@ +/* + * Copyright 2019-2020 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_display.h" +#include "fsl_rm68191.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define RM68191_DelayMs VIDEO_DelayMs + +typedef struct _rm68191_setting +{ + const uint8_t *value; + uint8_t len; +} rm68191_setting_t; + +#define RM68191_MAKE_SETTING_ITEM(setting) \ + { \ + (setting), (uint8_t)sizeof(setting) \ + } + +/******************************************************************************* + * Variables + ******************************************************************************/ +static const uint8_t s_rm68191Cmd0[] = {0xF0, 0x55, 0xAA, 0x52, 0x08, 0x03}; +static const uint8_t s_rm68191Cmd1[] = {0x90, 0x05, 0x16, 0x09, 0x03, 0xCD, 0x00, 0x00, 0x00, 0x00}; +static const uint8_t s_rm68191Cmd2[] = {0x91, 0x05, 0x16, 0x0B, 0x03, 0xCF, 0x00, 0x00, 0x00, 0x00}; +static const uint8_t s_rm68191Cmd3[] = {0x92, 0x40, 0x0C, 0x0D, 0x0E, 0x0F, 0x00, 0x8F, 0x00, 0x00, 0x04, 0x08}; +static const uint8_t s_rm68191Cmd4[] = {0x94, 0x00, 0x08, 0x0C, 0x03, 0xD1, 0x03, 0xD2, 0x0C}; +static const uint8_t s_rm68191Cmd5[] = {0x95, 0x40, 0x10, 0x00, 0x11, 0x00, 0x12, 0x00, 0x13, + 0x00, 0x8F, 0x00, 0x00, 0x00, 0x04, 0x00, 0x08}; +static const uint8_t s_rm68191Cmd6[] = {0x99, 0x00, 0x00}; +static const uint8_t s_rm68191Cmd7[] = {0x9A, 0x80, 0x10, 0x03, 0xD5, 0x03, 0xD7, 0x00, 0x00, 0x00, 0x00, 0x50}; +static const uint8_t s_rm68191Cmd8[] = {0x9B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; +static const uint8_t s_rm68191Cmd9[] = {0x9C, 0x00, 0x00}; +static const uint8_t s_rm68191Cmd10[] = {0x9D, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00}; +static const uint8_t s_rm68191Cmd11[] = {0x9E, 0x00, 0x00}; +static const uint8_t s_rm68191Cmd12[] = {0xA0, 0x84, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, 0x08, 0x1F, 0x0A, 0x1F}; +static const uint8_t s_rm68191Cmd13[] = {0xA1, 0x1F, 0x1F, 0x1F, 0x1F, 0x0C, 0x1F, 0x0E, 0x1F, 0x1F, 0x1F}; +static const uint8_t s_rm68191Cmd14[] = {0xA2, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x02, 0x1F, 0x06, 0x1F}; +static const uint8_t s_rm68191Cmd15[] = {0xA3, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F}; +static const uint8_t s_rm68191Cmd16[] = {0xA4, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x07, 0x1F, 0x03, 0x1F, 0x0F}; +static const uint8_t s_rm68191Cmd17[] = {0xA5, 0x1F, 0x0D, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x0B, 0x1F, 0x09}; +static const uint8_t s_rm68191Cmd18[] = {0xA6, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x01, 0x05}; +static const uint8_t s_rm68191Cmd19[] = {0xA7, 0x03, 0x07, 0x1F, 0x1F, 0x1F, 0x1F, 0x0B, 0x1F, 0x09, 0x1F}; +static const uint8_t s_rm68191Cmd20[] = {0xA8, 0x1F, 0x1F, 0x1F, 0x1F, 0x0F, 0x1F, 0x0D, 0x1F, 0x1F, 0x1F}; +static const uint8_t s_rm68191Cmd21[] = {0xA9, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x05, 0x1F, 0x01, 0x1F}; +static const uint8_t s_rm68191Cmd22[] = {0xAA, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F}; +static const uint8_t s_rm68191Cmd23[] = {0xAB, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x1F, 0x04, 0x1F, 0x0C}; +static const uint8_t s_rm68191Cmd24[] = {0xAC, 0x1F, 0x0E, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x08, 0x1F, 0x0A}; +static const uint8_t s_rm68191Cmd25[] = {0xAD, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x06, 0x02}; +static const uint8_t s_rm68191Cmd26[] = {0xF0, 0x55, 0xAA, 0x52, 0x08, 0x02}; +static const uint8_t s_rm68191Cmd27[] = {0xEA, 0x7D}; +static const uint8_t s_rm68191Cmd28[] = {0xF0, 0x55, 0xAA, 0x52, 0x08, 0x00}; +static const uint8_t s_rm68191Cmd29[] = {0xBC, 0x00, 0x00, 0x00}; +static const uint8_t s_rm68191Cmd30[] = {0xB8, 0x01, 0xAF, 0x8F, 0x8F}; +static const uint8_t s_rm68191Cmd31[] = {0xF0, 0x55, 0xAA, 0x52, 0x08, 0x01}; +static const uint8_t s_rm68191Cmd32[] = {0xD1, 0x00, 0x00, 0x00, 0x26, 0x00, 0x5E, 0x00, 0x88, + 0x00, 0xA8, 0x00, 0xDB, 0x01, 0x02, 0x01, 0x3D}; +static const uint8_t s_rm68191Cmd33[] = {0xD2, 0x01, 0x67, 0x01, 0xA6, 0x01, 0xD3, 0x02, 0x16, + 0x02, 0x49, 0x02, 0x4B, 0x02, 0x7B, 0x02, 0xB3}; +static const uint8_t s_rm68191Cmd34[] = {0xD3, 0x02, 0xD9, 0x03, 0x0E, 0x03, 0x31, 0x03, 0x61, + 0x03, 0x80, 0x03, 0xA5, 0x03, 0xBD, 0x03, 0xD2}; +static const uint8_t s_rm68191Cmd35[] = {0xD4, 0x03, 0xE5, 0x03, 0xFF}; +static const uint8_t s_rm68191Cmd36[] = {0xD5, 0x00, 0x00, 0x00, 0x26, 0x00, 0x5E, 0x00, 0x88, + 0x00, 0xA8, 0x00, 0xDB, 0x01, 0x02, 0x01, 0x3D}; +static const uint8_t s_rm68191Cmd37[] = {0xD6, 0x01, 0x67, 0x01, 0xA6, 0x01, 0xD3, 0x02, 0x16, + 0x02, 0x49, 0x02, 0x4B, 0x02, 0x7B, 0x02, 0xB3}; +static const uint8_t s_rm68191Cmd38[] = {0xD7, 0x02, 0xD9, 0x03, 0x0E, 0x03, 0x31, 0x03, 0x61, + 0x03, 0x80, 0x03, 0xA5, 0x03, 0xBD, 0x03, 0xD2}; +static const uint8_t s_rm68191Cmd39[] = {0xD8, 0x03, 0xE5, 0x03, 0xFF}; +static const uint8_t s_rm68191Cmd40[] = {0xD9, 0x00, 0x00, 0x00, 0x26, 0x00, 0x5E, 0x00, 0x88, + 0x00, 0xA8, 0x00, 0xDB, 0x01, 0x02, 0x01, 0x3D}; +static const uint8_t s_rm68191Cmd41[] = {0xDD, 0x01, 0x67, 0x01, 0xA6, 0x01, 0xD3, 0x02, 0x16, + 0x02, 0x49, 0x02, 0x4B, 0x02, 0x7B, 0x02, 0xB3}; +static const uint8_t s_rm68191Cmd42[] = {0xDE, 0x02, 0xD9, 0x03, 0x0E, 0x03, 0x31, 0x03, 0x61, + 0x03, 0x80, 0x03, 0xA5, 0x03, 0xBD, 0x03, 0xD2}; +static const uint8_t s_rm68191Cmd43[] = {0xDF, 0x03, 0xE5, 0x03, 0xFF}; +static const uint8_t s_rm68191Cmd44[] = {0xE0, 0x00, 0x00, 0x00, 0x26, 0x00, 0x5E, 0x00, 0x88, + 0x00, 0xA8, 0x00, 0xDB, 0x01, 0x02, 0x01, 0x3D}; +static const uint8_t s_rm68191Cmd45[] = {0xE1, 0x01, 0x67, 0x01, 0xA6, 0x01, 0xD3, 0x02, 0x16, + 0x02, 0x49, 0x02, 0x4B, 0x02, 0x7B, 0x02, 0xB3}; +static const uint8_t s_rm68191Cmd46[] = {0xE2, 0x02, 0xD9, 0x03, 0x0E, 0x03, 0x31, 0x03, 0x61, + 0x03, 0x80, 0x03, 0xA5, 0x03, 0xBD, 0x03, 0xD2}; +static const uint8_t s_rm68191Cmd47[] = {0xE3, 0x03, 0xE5, 0x03, 0xFF}; +static const uint8_t s_rm68191Cmd48[] = {0xE4, 0x00, 0x00, 0x00, 0x26, 0x00, 0x5E, 0x00, 0x88, + 0x00, 0xA8, 0x00, 0xDB, 0x01, 0x02, 0x01, 0x3D}; +static const uint8_t s_rm68191Cmd49[] = {0xE5, 0x01, 0x67, 0x01, 0xA6, 0x01, 0xD3, 0x02, 0x16, + 0x02, 0x49, 0x02, 0x4B, 0x02, 0x7B, 0x02, 0xB3}; +static const uint8_t s_rm68191Cmd50[] = {0xE6, 0x02, 0xD9, 0x03, 0x0E, 0x03, 0x31, 0x03, 0x61, + 0x03, 0x80, 0x03, 0xA5, 0x03, 0xBD, 0x03, 0xD2}; +static const uint8_t s_rm68191Cmd51[] = {0xE7, 0x03, 0xE5, 0x03, 0xFF}; +static const uint8_t s_rm68191Cmd52[] = {0xE8, 0x00, 0x00, 0x00, 0x26, 0x00, 0x5E, 0x00, 0x88, + 0x00, 0xA8, 0x00, 0xDB, 0x01, 0x02, 0x01, 0x3D}; +static const uint8_t s_rm68191Cmd53[] = {0xE9, 0x01, 0x67, 0x01, 0xA6, 0x01, 0xD3, 0x02, 0x16, + 0x02, 0x49, 0x02, 0x4B, 0x02, 0x7B, 0x02, 0xB3}; +static const uint8_t s_rm68191Cmd54[] = {0xEA, 0x02, 0xD9, 0x03, 0x0E, 0x03, 0x31, 0x03, 0x61, + 0x03, 0x80, 0x03, 0xA5, 0x03, 0xBD, 0x03, 0xD2}; +static const uint8_t s_rm68191Cmd55[] = {0xEB, 0x03, 0xE5, 0x03, 0xFF}; +static const uint8_t s_rm68191Cmd56[] = {0xB0, 0x07, 0x07, 0x07}; +static const uint8_t s_rm68191Cmd57[] = {0xB1, 0x07, 0x07, 0x07}; +static const uint8_t s_rm68191Cmd58[] = {0xB3, 0x11, 0x11, 0x11}; +static const uint8_t s_rm68191Cmd59[] = {0xB4, 0x09, 0x09, 0x09}; +static const uint8_t s_rm68191Cmd60[] = {0xB6, 0x44, 0x44, 0x44}; +static const uint8_t s_rm68191Cmd61[] = {0xB7, 0x34, 0x34, 0x34}; +static const uint8_t s_rm68191Cmd62[] = {0xB9, 0x34, 0x34, 0x34}; +static const uint8_t s_rm68191Cmd63[] = {0xBA, 0x14, 0x14, 0x14}; +static const uint8_t s_rm68191Cmd64[] = {0xBC, 0x00, 0x98, 0x00}; +static const uint8_t s_rm68191Cmd65[] = {0xBD, 0x00, 0x98, 0x00}; +static const uint8_t s_rm68191Cmd66[] = {0xBE, 0x1D}; +static const uint8_t s_rm68191Cmd67[] = {0x35, 0x00}; + +static const rm68191_setting_t s_rm68191InitSetting[] = { + RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd0), RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd1), + RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd2), RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd3), + RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd4), RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd5), + RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd6), RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd7), + RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd8), RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd9), + RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd10), RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd11), + RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd12), RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd13), + RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd14), RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd15), + RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd16), RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd17), + RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd18), RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd19), + RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd20), RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd21), + RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd22), RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd23), + RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd24), RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd25), + RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd26), RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd27), + RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd28), RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd29), + RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd30), RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd31), + RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd32), RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd33), + RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd34), RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd35), + RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd36), RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd37), + RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd38), RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd39), + RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd40), RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd41), + RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd42), RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd43), + RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd44), RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd45), + RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd46), RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd47), + RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd48), RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd49), + RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd50), RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd51), + RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd52), RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd53), + RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd54), RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd55), + RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd56), RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd57), + RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd58), RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd59), + RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd60), RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd61), + RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd62), RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd63), + RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd64), RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd65), + RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd66), RM68191_MAKE_SETTING_ITEM(s_rm68191Cmd67), +}; + +const display_operations_t rm68191_ops = { + .init = RM68191_Init, + .deinit = RM68191_Deinit, + .start = RM68191_Start, + .stop = RM68191_Stop, +}; + +/******************************************************************************* + * Code + ******************************************************************************/ + +status_t RM68191_Init(display_handle_t *handle, const display_config_t *config) +{ + uint32_t i; + status_t status = kStatus_Success; + const rm68191_resource_t *resource = (const rm68191_resource_t *)(handle->resource); + mipi_dsi_device_t *dsiDevice = resource->dsiDevice; + + /* Only support 540 * 960 */ + if (config->resolution != FSL_VIDEO_RESOLUTION(540, 960)) + { + return kStatus_InvalidArgument; + } + + /* Power on. */ + resource->pullPowerPin(true); + RM68191_DelayMs(1); + + /* Perform reset. */ + resource->pullResetPin(false); + RM68191_DelayMs(1); + resource->pullResetPin(true); + RM68191_DelayMs(5); + + /* Set the LCM init settings. */ + for (i = 0; i < ARRAY_SIZE(s_rm68191InitSetting); i++) + { + status = MIPI_DSI_DCS_Write(dsiDevice, s_rm68191InitSetting[i].value, (int32_t)s_rm68191InitSetting[i].len); + + if (kStatus_Success != status) + { + return status; + } + } + + /* Exit sleep mode */ + status = MIPI_DSI_DCS_EnterSleepMode(dsiDevice, false); + + if (kStatus_Success != status) + { + return status; + } + + RM68191_DelayMs(200); + + /* Set display on. */ + status = MIPI_DSI_DCS_SetDisplayOn(dsiDevice, true); + + if (kStatus_Success != status) + { + return status; + } + + RM68191_DelayMs(200); + + return kStatus_Success; +} + +status_t RM68191_Deinit(display_handle_t *handle) +{ + const rm68191_resource_t *resource = (const rm68191_resource_t *)(handle->resource); + mipi_dsi_device_t *dsiDevice = resource->dsiDevice; + + (void)MIPI_DSI_DCS_EnterSleepMode(dsiDevice, true); + + resource->pullResetPin(false); + resource->pullPowerPin(false); + + return kStatus_Success; +} + +status_t RM68191_Start(display_handle_t *handle) +{ + const rm68191_resource_t *resource = (const rm68191_resource_t *)(handle->resource); + mipi_dsi_device_t *dsiDevice = resource->dsiDevice; + + return MIPI_DSI_DCS_SetDisplayOn(dsiDevice, true); +} + +status_t RM68191_Stop(display_handle_t *handle) +{ + const rm68191_resource_t *resource = (const rm68191_resource_t *)(handle->resource); + mipi_dsi_device_t *dsiDevice = resource->dsiDevice; + + return MIPI_DSI_DCS_SetDisplayOn(dsiDevice, false); +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/display/rm68191/fsl_rm68191.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/display/rm68191/fsl_rm68191.h new file mode 100644 index 00000000000..2f372da0028 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/display/rm68191/fsl_rm68191.h @@ -0,0 +1,62 @@ +/* + * Copyright 2019-2020 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_RM68191_H_ +#define _FSL_RM68191_H_ + +#include "fsl_display.h" +#include "fsl_mipi_dsi_cmd.h" + +/* + * Change log: + * + * 1.1.0 + * - Fix MISRA-C 2012 issues. + * - Change rm68191_resource_t structure. + * + * 1.0.0 + * - Initial version + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief RM68191 resource. + */ +typedef struct _rm68191_resource +{ + mipi_dsi_device_t *dsiDevice; /*!< MIPI DSI device. */ + void (*pullResetPin)(bool pullUp); /*!< Function to pull reset pin high or low. */ + void (*pullPowerPin)(bool pullUp); /*!< Function to pull power pin high or low. */ +} rm68191_resource_t; + +extern const display_operations_t rm68191_ops; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +status_t RM68191_Init(display_handle_t *handle, const display_config_t *config); + +status_t RM68191_Deinit(display_handle_t *handle); + +status_t RM68191_Start(display_handle_t *handle); + +status_t RM68191_Stop(display_handle_t *handle); + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_RM68191_H_ */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/display/rm68200/fsl_rm68200.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/display/rm68200/fsl_rm68200.c new file mode 100644 index 00000000000..1d8c2831f52 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/display/rm68200/fsl_rm68200.c @@ -0,0 +1,409 @@ +/* + * Copyright 2019-2021 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_display.h" +#include "fsl_rm68200.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define RM68200_DelayMs VIDEO_DelayMs + +/******************************************************************************* + * Variables + ******************************************************************************/ + +uint8_t RM68200_DDB_START[5] = {0x00, 0x00, 0x00, 0x00, 0xff}; + +static const uint8_t lcmInitPage0Setting[][2] = { + {0xFE, 0x01}, {0x24, 0xC0}, {0x25, 0x53}, {0x26, 0x00}, {0x2B, 0xE5}, {0x27, 0x0A}, + {0x29, 0x0A}, {0x16, 0x52}, {0x2F, 0x53}, {0x34, 0x5A}, {0x1B, 0x00}, {0x12, 0x0A}, + {0x1A, 0x06}, {0x46, 0x56}, {0x52, 0xA0}, {0x53, 0x00}, {0x54, 0xA0}, {0x55, 0x00}, +}; + +static const uint8_t lcmInitSetting[][2] = { + {0xFE, 0x03}, + {0x00, 0x05}, + {0x02, 0x0B}, + {0x03, 0x0F}, + {0x04, 0x7D}, + {0x05, 0x00}, + {0x06, 0x50}, + {0x07, 0x05}, + {0x08, 0x16}, + {0x09, 0x0D}, + {0x0A, 0x11}, + {0x0B, 0x7D}, + {0x0C, 0x00}, + {0x0D, 0x50}, + {0x0E, 0x07}, + {0x0F, 0x08}, + {0x10, 0x01}, + {0x11, 0x02}, + {0x12, 0x00}, + {0x13, 0x7D}, + {0x14, 0x00}, + {0x15, 0x85}, + {0x16, 0x08}, + {0x17, 0x03}, + {0x18, 0x04}, + {0x19, 0x05}, + {0x1A, 0x06}, + {0x1B, 0x00}, + {0x1C, 0x7D}, + {0x1D, 0x00}, + {0x1E, 0x85}, + {0x1F, 0x08}, + {0x20, 0x00}, + {0x21, 0x00}, + {0x22, 0x00}, + {0x23, 0x00}, + {0x24, 0x00}, + {0x25, 0x00}, + {0x26, 0x00}, + {0x27, 0x00}, + {0x28, 0x00}, + {0x29, 0x00}, + {0x2A, 0x07}, + {0x2B, 0x08}, + {0x2D, 0x01}, + {0x2F, 0x02}, + {0x30, 0x00}, + {0x31, 0x40}, + {0x32, 0x05}, + {0x33, 0x08}, + {0x34, 0x54}, + {0x35, 0x7D}, + {0x36, 0x00}, + {0x37, 0x03}, + {0x38, 0x04}, + {0x39, 0x05}, + {0x3A, 0x06}, + {0x3B, 0x00}, + {0x3D, 0x40}, + {0x3F, 0x05}, + {0x40, 0x08}, + {0x41, 0x54}, + {0x42, 0x7D}, + {0x43, 0x00}, + {0x44, 0x00}, + {0x45, 0x00}, + {0x46, 0x00}, + {0x47, 0x00}, + {0x48, 0x00}, + {0x49, 0x00}, + {0x4A, 0x00}, + {0x4B, 0x00}, + {0x4C, 0x00}, + {0x4D, 0x00}, + {0x4E, 0x00}, + {0x4F, 0x00}, + {0x50, 0x00}, + {0x51, 0x00}, + {0x52, 0x00}, + {0x53, 0x00}, + {0x54, 0x00}, + {0x55, 0x00}, + {0x56, 0x00}, + {0x58, 0x00}, + {0x59, 0x00}, + {0x5A, 0x00}, + {0x5B, 0x00}, + {0x5C, 0x00}, + {0x5D, 0x00}, + {0x5E, 0x00}, + {0x5F, 0x00}, + {0x60, 0x00}, + {0x61, 0x00}, + {0x62, 0x00}, + {0x63, 0x00}, + {0x64, 0x00}, + {0x65, 0x00}, + {0x66, 0x00}, + {0x67, 0x00}, + {0x68, 0x00}, + {0x69, 0x00}, + {0x6A, 0x00}, + {0x6B, 0x00}, + {0x6C, 0x00}, + {0x6D, 0x00}, + {0x6E, 0x00}, + {0x6F, 0x00}, + {0x70, 0x00}, + {0x71, 0x00}, + {0x72, 0x20}, + {0x73, 0x00}, + {0x74, 0x08}, + {0x75, 0x08}, + {0x76, 0x08}, + {0x77, 0x08}, + {0x78, 0x08}, + {0x79, 0x08}, + {0x7A, 0x00}, + {0x7B, 0x00}, + {0x7C, 0x00}, + {0x7D, 0x00}, + {0x7E, 0xBF}, + {0x7F, 0x02}, + {0x80, 0x06}, + {0x81, 0x14}, + {0x82, 0x10}, + {0x83, 0x16}, + {0x84, 0x12}, + {0x85, 0x08}, + {0x86, 0x3F}, + {0x87, 0x3F}, + {0x88, 0x3F}, + {0x89, 0x3F}, + {0x8A, 0x3F}, + {0x8B, 0x0C}, + {0x8C, 0x0A}, + {0x8D, 0x0E}, + {0x8E, 0x3F}, + {0x8F, 0x3F}, + {0x90, 0x00}, + {0x91, 0x04}, + {0x92, 0x3F}, + {0x93, 0x3F}, + {0x94, 0x3F}, + {0x95, 0x3F}, + {0x96, 0x05}, + {0x97, 0x01}, + {0x98, 0x3F}, + {0x99, 0x3F}, + {0x9A, 0x0F}, + {0x9B, 0x0B}, + {0x9C, 0x0D}, + {0x9D, 0x3F}, + {0x9E, 0x3F}, + {0x9F, 0x3F}, + {0xA0, 0x3F}, + {0xA2, 0x3F}, + {0xA3, 0x09}, + {0xA4, 0x13}, + {0xA5, 0x17}, + {0xA6, 0x11}, + {0xA7, 0x15}, + {0xA9, 0x07}, + {0xAA, 0x03}, + {0xAB, 0x3F}, + {0xAC, 0x3F}, + {0xAD, 0x05}, + {0xAE, 0x01}, + {0xAF, 0x17}, + {0xB0, 0x13}, + {0xB1, 0x15}, + {0xB2, 0x11}, + {0xB3, 0x0F}, + {0xB4, 0x3F}, + {0xB5, 0x3F}, + {0xB6, 0x3F}, + {0xB7, 0x3F}, + {0xB8, 0x3F}, + {0xB9, 0x0B}, + {0xBA, 0x0D}, + {0xBB, 0x09}, + {0xBC, 0x3F}, + {0xBD, 0x3F}, + {0xBE, 0x07}, + {0xBF, 0x03}, + {0xC0, 0x3F}, + {0xC1, 0x3F}, + {0xC2, 0x3F}, + {0xC3, 0x3F}, + {0xC4, 0x02}, + {0xC5, 0x06}, + {0xC6, 0x3F}, + {0xC7, 0x3F}, + {0xC8, 0x08}, + {0xC9, 0x0C}, + {0xCA, 0x0A}, + {0xCB, 0x3F}, + {0xCC, 0x3F}, + {0xCD, 0x3F}, + {0xCE, 0x3F}, + {0xCF, 0x3F}, + {0xD0, 0x0E}, + {0xD1, 0x10}, + {0xD2, 0x14}, + {0xD3, 0x12}, + {0xD4, 0x16}, + {0xD5, 0x00}, + {0xD6, 0x04}, + {0xD7, 0x3F}, + {0xDC, 0x02}, + {0xDE, 0x12}, + {0xFE, 0x0E}, + {0x01, 0x75}, + + /* Gamma Settings */ + {0xFE, 0x04}, + {0x60, 0x00}, + {0x61, 0x0C}, + {0x62, 0x12}, + {0x63, 0x0E}, + {0x64, 0x06}, + {0x65, 0x12}, + {0x66, 0x0E}, + {0x67, 0x0B}, + {0x68, 0x15}, + {0x69, 0x0B}, + {0x6A, 0x10}, + {0x6B, 0x07}, + {0x6C, 0x0F}, + {0x6D, 0x12}, + {0x6E, 0x0C}, + {0x6F, 0x00}, + {0x70, 0x00}, + {0x71, 0x0C}, + {0x72, 0x12}, + {0x73, 0x0E}, + {0x74, 0x06}, + {0x75, 0x12}, + {0x76, 0x0E}, + {0x77, 0x0B}, + {0x78, 0x15}, + {0x79, 0x0B}, + {0x7A, 0x10}, + {0x7B, 0x07}, + {0x7C, 0x0F}, + {0x7D, 0x12}, + {0x7E, 0x0C}, + {0x7F, 0x00}, + + /* Page 0. */ + {0xFE, 0x00}, + {0x11, 0x00}, +}; + +const display_operations_t rm68200_ops = { + .init = RM68200_Init, + .deinit = RM68200_Deinit, + .start = RM68200_Start, + .stop = RM68200_Stop, +}; + +/******************************************************************************* + * Code + ******************************************************************************/ + +status_t RM68200_Init(display_handle_t *handle, const display_config_t *config) +{ + uint32_t i; + uint8_t param[2]; + status_t status = kStatus_Success; + const rm68200_resource_t *resource = (const rm68200_resource_t *)(handle->resource); + mipi_dsi_device_t *dsiDevice = resource->dsiDevice; + + /* Only support 720 * 1280 */ + if (config->resolution != FSL_VIDEO_RESOLUTION(720, 1280)) + { + return kStatus_InvalidArgument; + } + + /* Power on. */ + resource->pullPowerPin(true); + RM68200_DelayMs(1); + + /* Perform reset. */ + resource->pullResetPin(false); + RM68200_DelayMs(1); + resource->pullResetPin(true); + RM68200_DelayMs(5); + + /* Set the LCM page0 init settings. */ + for (i = 0; i < ARRAY_SIZE(lcmInitPage0Setting); i++) + { + status = MIPI_DSI_GenericWrite(dsiDevice, lcmInitPage0Setting[i], 2); + + if (kStatus_Success != status) + { + return status; + } + } + + /* Data lane number selection. */ + param[0] = 0x5FU; + param[1] = 0x10U | (config->dsiLanes - 1U); + status = MIPI_DSI_GenericWrite(dsiDevice, param, 2); + if (kStatus_Success != status) + { + return status; + } + + /* Set the LCM init settings. */ + for (i = 0; i < ARRAY_SIZE(lcmInitSetting); i++) + { + status = MIPI_DSI_GenericWrite(dsiDevice, lcmInitSetting[i], 2); + + if (kStatus_Success != status) + { + return status; + } + } + + RM68200_DelayMs(200); + + param[0] = 0x29; + param[1] = 0x00; + status = MIPI_DSI_GenericWrite(dsiDevice, param, 2); + if (kStatus_Success != status) + { + return status; + } + + RM68200_DelayMs(100); + + param[0] = 0x2c; + status = MIPI_DSI_GenericWrite(dsiDevice, param, 1); + if (kStatus_Success != status) + { + return status; + } + + param[0] = 0x35; + param[1] = 0x00; + status = MIPI_DSI_GenericWrite(dsiDevice, param, 2); + if (kStatus_Success != status) + { + return status; + } + + RM68200_DelayMs(200); + + return kStatus_Success; +} + +status_t RM68200_Deinit(display_handle_t *handle) +{ + const rm68200_resource_t *resource = (const rm68200_resource_t *)(handle->resource); + mipi_dsi_device_t *dsiDevice = resource->dsiDevice; + + (void)MIPI_DSI_DCS_EnterSleepMode(dsiDevice, true); + + resource->pullResetPin(false); + resource->pullPowerPin(false); + + return kStatus_Success; +} + +status_t RM68200_Start(display_handle_t *handle) +{ + const rm68200_resource_t *resource = (const rm68200_resource_t *)(handle->resource); + mipi_dsi_device_t *dsiDevice = resource->dsiDevice; + + return MIPI_DSI_DCS_SetDisplayOn(dsiDevice, true); +} + +status_t RM68200_Stop(display_handle_t *handle) +{ + const rm68200_resource_t *resource = (const rm68200_resource_t *)(handle->resource); + mipi_dsi_device_t *dsiDevice = resource->dsiDevice; + + return MIPI_DSI_DCS_SetDisplayOn(dsiDevice, false); +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/display/rm68200/fsl_rm68200.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/display/rm68200/fsl_rm68200.h new file mode 100644 index 00000000000..f039e89e995 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/display/rm68200/fsl_rm68200.h @@ -0,0 +1,67 @@ +/* + * Copyright 2019-2021 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_RM68200_H_ +#define _FSL_RM68200_H_ + +#include "fsl_display.h" +#include "fsl_mipi_dsi_cmd.h" + +/* + * Change log: + * + * 1.1.1 + * - Support 1 lane to 4 lanes, previously only support 2 lanes. + * + * 1.1.0 + * - Fix MISRA-C 2012 issues. + * - Change rm68200_resource_t structure. + * + * 1.0.0 + * - Initial version + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief RM68200 resource. + */ +typedef struct _rm68200_resource +{ + mipi_dsi_device_t *dsiDevice; /*!< MIPI DSI device. */ + void (*pullResetPin)(bool pullUp); /*!< Function to pull reset pin high or low. */ + void (*pullPowerPin)(bool pullUp); /*!< Function to pull power pin high or low. */ +} rm68200_resource_t; + +extern const display_operations_t rm68200_ops; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +extern uint8_t RM68200_DDB_START[5]; + +status_t RM68200_Init(display_handle_t *handle, const display_config_t *config); + +status_t RM68200_Deinit(display_handle_t *handle); + +status_t RM68200_Start(display_handle_t *handle); + +status_t RM68200_Stop(display_handle_t *handle); + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_RM68200_H_ */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/fsl_video_common.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/fsl_video_common.c new file mode 100644 index 00000000000..326187d73a4 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/fsl_video_common.c @@ -0,0 +1,301 @@ +/* + * Copyright 2017, 2020-2021, 2023 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_video_common.h" +#if defined(USE_RTOS) +#include "rtthread.h" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +bool VIDEO_IsYUV(video_pixel_format_t format) +{ + if ((kVIDEO_PixelFormatYUYV == format) || (kVIDEO_PixelFormatYVYU == format) || + (kVIDEO_PixelFormatUYVY == format) || (kVIDEO_PixelFormatVYUY == format) || + (kVIDEO_PixelFormatXYVU == format) || (kVIDEO_PixelFormatXYUV == format)) + { + return true; + } + else + { + return false; + } +} + +void VIDEO_DelayMs(uint32_t ms) +{ +#if defined(USE_RTOS) + rt_thread_mdelay(ms); +#else + while (0U != (ms--)) + { + SDK_DelayAtLeastUs(1000U, SystemCoreClock); + } +#endif +} + +uint8_t VIDEO_GetPixelSizeBits(video_pixel_format_t pixelFormat) +{ + uint8_t ret; + + switch (pixelFormat) + { + case kVIDEO_PixelFormatXRGB8888: + case kVIDEO_PixelFormatRGBX8888: + case kVIDEO_PixelFormatXBGR8888: + case kVIDEO_PixelFormatBGRX8888: + case kVIDEO_PixelFormatXYUV: + case kVIDEO_PixelFormatXYVU: + ret = 32; + break; + + case kVIDEO_PixelFormatRGB888: + case kVIDEO_PixelFormatBGR888: + ret = 24; + break; + + case kVIDEO_PixelFormatRGB565: + case kVIDEO_PixelFormatBGR565: + case kVIDEO_PixelFormatXRGB1555: + case kVIDEO_PixelFormatRGBX5551: + case kVIDEO_PixelFormatXBGR1555: + case kVIDEO_PixelFormatBGRX5551: + case kVIDEO_PixelFormatXRGB4444: + case kVIDEO_PixelFormatRGBX4444: + case kVIDEO_PixelFormatXBGR4444: + case kVIDEO_PixelFormatBGRX4444: + case kVIDEO_PixelFormatYUYV: + case kVIDEO_PixelFormatYVYU: + case kVIDEO_PixelFormatUYVY: + case kVIDEO_PixelFormatVYUY: + ret = 16; + break; + + case kVIDEO_PixelFormatRAW8: + case kVIDEO_PixelFormatLUT8: + ret = 8; + break; + + default: + ret = 0; + break; + } + + return ret; +} + +status_t VIDEO_RINGBUF_Init(video_ringbuf_t *ringbuf, void **buf, uint32_t size) +{ + assert(ringbuf != NULL); + + ringbuf->rear = 0; + ringbuf->front = 0; + ringbuf->size = size; + ringbuf->buf = buf; + + return kStatus_Success; +} + +status_t VIDEO_RINGBUF_Get(video_ringbuf_t *ringbuf, void **item) +{ + uint32_t front_next; + + /* To fix IAR Pa082 warning. */ + uint32_t rear = ringbuf->rear; + uint32_t front = ringbuf->front; + + if (rear != front) + { + *item = ringbuf->buf[ringbuf->front]; + + /* + * Here don't use ringbuf->front = (ringbuf->front + 1) % ringbuf->size, + * because mod operation might be slow. + */ + front_next = (ringbuf->front + 1U); + + /* Use two steps to make sure ringbuf->front is always a valid value. */ + ringbuf->front = (front_next == ringbuf->size) ? 0UL : front_next; + + return kStatus_Success; + } + else + { + return kStatus_Fail; + } +} + +status_t VIDEO_RINGBUF_Put(video_ringbuf_t *ringbuf, void *item) +{ + /* + * Here don't use ringbuf->rear = (ringbuf->rear + 1) % ringbuf->size, + * because mod operation might be slow. + */ + uint32_t rear_next = ringbuf->rear + 1U; + + rear_next = (rear_next == ringbuf->size) ? 0U : rear_next; + + if (rear_next != ringbuf->front) + { + ringbuf->buf[ringbuf->rear] = item; + ringbuf->rear = rear_next; + + return kStatus_Success; + } + /* No room. */ + else + { + return kStatus_Fail; + } +} + +uint32_t VIDEO_RINGBUF_GetLength(video_ringbuf_t *ringbuf) +{ + uint32_t ret; + + /* To fix IAR Pa082 warning. */ + uint32_t rear = ringbuf->rear; + uint32_t front = ringbuf->front; + + ret = (rear + ringbuf->size) - front; + + if (ret >= ringbuf->size) + { + ret -= ringbuf->size; + } + + return ret; +} + +bool VIDEO_RINGBUF_IsEmpty(video_ringbuf_t *ringbuf) +{ + /* To fix IAR Pa082 warning. */ + uint32_t rear = ringbuf->rear; + uint32_t front = ringbuf->front; + + if (rear == front) + { + return true; + } + else + { + return false; + } +} + +bool VIDEO_RINGBUF_IsFull(video_ringbuf_t *ringbuf) +{ + uint32_t rear = ringbuf->rear; + uint32_t front = ringbuf->front; + + rear++; + + if (rear >= ringbuf->size) + { + rear = 0; + } + + if (rear == front) + { + return true; + } + else + { + return false; + } +} + +status_t VIDEO_MEMPOOL_Init(video_mempool_t *mempool, void *initMem, uint32_t size, uint32_t count) +{ + (void)memset(mempool, 0, sizeof(video_mempool_t)); + + while (0U != (count--)) + { + VIDEO_MEMPOOL_Put(mempool, initMem); + initMem = &((uint8_t *)initMem)[size]; + } + + return kStatus_Success; +} + +void VIDEO_MEMPOOL_InitEmpty(video_mempool_t *mempool) +{ + mempool->pool = NULL; + mempool->cnt = 0; +} + +void VIDEO_MEMPOOL_Put(video_mempool_t *mempool, void *mem) +{ + *(void **)mem = mempool->pool; + mempool->pool = mem; + mempool->cnt++; +} + +void *VIDEO_MEMPOOL_Get(video_mempool_t *mempool) +{ + void *mem = mempool->pool; + + if (NULL != mem) + { + mempool->cnt--; + mempool->pool = *(void **)mem; + } + + return mem; +} + +uint32_t VIDEO_MEMPOOL_GetCount(video_mempool_t *mempool) +{ + return mempool->cnt; +} + +status_t VIDEO_STACK_Init(video_stack_t *stack, void **buf, uint32_t size) +{ + stack->buf = buf; + stack->maxCount = size; + stack->top = 0U; + + return kStatus_Success; +} + +status_t VIDEO_STACK_Pop(video_stack_t *stack, void **item) +{ + status_t status; + + if (stack->top > 0U) + { + *item = stack->buf[--stack->top]; + status = kStatus_Success; + } + else + { + *item = NULL; + status = kStatus_Fail; + } + + return status; +} + +status_t VIDEO_STACK_Push(video_stack_t *stack, void *item) +{ + status_t status; + + if (stack->top < (stack->maxCount)) + { + stack->buf[stack->top++] = item; + status = kStatus_Success; + } + else + { + status = kStatus_Fail; + } + + return status; +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/fsl_video_common.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/fsl_video_common.h new file mode 100644 index 00000000000..e4097607f70 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/video/fsl_video_common.h @@ -0,0 +1,364 @@ +/* + * Copyright 2017, 2020-2021, 2023 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_VIDEO_COMMON_H_ +#define _FSL_VIDEO_COMMON_H_ + +#include "fsl_common.h" + +/* + * Change log: + * + * 1.1.0 + * - Add stack function which supports LIFO item management. + * + * 1.0.5 + * - Fix IAR Pa082 warning. + * + * 1.0.4 + * - Add LUT8 definition. + * + * 1.0.3 + * - Add RAW8 definition. + * + * 1.0.2 + * - Fixed MISRA-C 2012 issues. + * + * 1.0.1 + * - Update the VIDEO_DelayMs for bare metal. + * + * 1.0.0 + * - Initial version + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Pixel format FOURCC. */ +#define FSL_VIDEO_FOURCC(a, b, c, d) \ + ((uint32_t)(a) | ((uint32_t)(b) << 8U) | ((uint32_t)(c) << 16U) | ((uint32_t)(d) << 24U)) + +/*! @brief Macro to define resolution. */ +#define FSL_VIDEO_RESOLUTION(width, height) ((uint32_t)(width) | ((uint32_t)(height) << 16U)) + +#define FSL_VIDEO_EXTRACT_WIDTH(resolution) ((uint16_t)((resolution)&0xFFFFU)) +#define FSL_VIDEO_EXTRACT_HEIGHT(resolution) ((uint16_t)((resolution) >> 16U)) + +/*! @brief Pixel format definition. */ +typedef enum _video_pixel_format +{ + /* RAW */ + kVIDEO_PixelFormatRAW8 = FSL_VIDEO_FOURCC('G', 'R', 'B', 'G'), /*!< RAW8, GRBG. */ + + /* LUT/palette */ + kVIDEO_PixelFormatLUT8 = FSL_VIDEO_FOURCC('L', 'U', 'T', '8'), /*!< 8-bit Indexed Color. */ + + /* RGB */ + kVIDEO_PixelFormatXRGB8888 = FSL_VIDEO_FOURCC('X', 'R', '2', '4'), /*!< 32-bit XRGB8888. */ + kVIDEO_PixelFormatRGBX8888 = FSL_VIDEO_FOURCC('R', 'X', '2', '4'), /*!< 32-bit RGBX8888. */ + kVIDEO_PixelFormatXBGR8888 = FSL_VIDEO_FOURCC('X', 'B', '2', '4'), /*!< 32-bit XBGR8888. */ + kVIDEO_PixelFormatBGRX8888 = FSL_VIDEO_FOURCC('B', 'X', '2', '4'), /*!< 32-bit BGRX8888. */ + + kVIDEO_PixelFormatRGB888 = FSL_VIDEO_FOURCC('R', 'G', '2', '4'), /*!< 24-bit RGB888. */ + kVIDEO_PixelFormatBGR888 = FSL_VIDEO_FOURCC('B', 'G', '2', '4'), /*!< 24-bit BGR888. */ + + kVIDEO_PixelFormatRGB565 = FSL_VIDEO_FOURCC('R', 'G', '1', '6'), /*!< 16-bit RGB565. */ + kVIDEO_PixelFormatBGR565 = FSL_VIDEO_FOURCC('B', 'G', '1', '6'), /*!< 16-bit BGR565. */ + + kVIDEO_PixelFormatXRGB1555 = FSL_VIDEO_FOURCC('X', 'R', '1', '5'), /*!< 16-bit XRGB1555. */ + kVIDEO_PixelFormatRGBX5551 = FSL_VIDEO_FOURCC('R', 'X', '1', '5'), /*!< 16-bit RGBX5551. */ + kVIDEO_PixelFormatXBGR1555 = FSL_VIDEO_FOURCC('X', 'B', '1', '5'), /*!< 16-bit XBGR1555. */ + kVIDEO_PixelFormatBGRX5551 = FSL_VIDEO_FOURCC('B', 'X', '1', '5'), /*!< 16-bit BGRX5551. */ + + kVIDEO_PixelFormatXRGB4444 = FSL_VIDEO_FOURCC('X', 'R', '1', '2'), /*!< 16-bit XRGB4444. */ + kVIDEO_PixelFormatRGBX4444 = FSL_VIDEO_FOURCC('R', 'X', '1', '2'), /*!< 16-bit RGBX4444. */ + kVIDEO_PixelFormatXBGR4444 = FSL_VIDEO_FOURCC('X', 'B', '1', '2'), /*!< 16-bit XBGR4444. */ + kVIDEO_PixelFormatBGRX4444 = FSL_VIDEO_FOURCC('B', 'X', '1', '2'), /*!< 16-bit BGRX4444. */ + + /* YUV. */ + kVIDEO_PixelFormatYUYV = FSL_VIDEO_FOURCC('Y', 'U', 'Y', 'V'), /*!< YUV422, Y-U-Y-V. */ + kVIDEO_PixelFormatYVYU = FSL_VIDEO_FOURCC('Y', 'V', 'Y', 'U'), /*!< YUV422, Y-V-Y-U. */ + kVIDEO_PixelFormatUYVY = FSL_VIDEO_FOURCC('U', 'Y', 'V', 'Y'), /*!< YUV422, U-Y-V-Y. */ + kVIDEO_PixelFormatVYUY = FSL_VIDEO_FOURCC('V', 'Y', 'U', 'Y'), /*!< YUV422, V-Y-U-Y. */ + + kVIDEO_PixelFormatXYUV = FSL_VIDEO_FOURCC('X', 'Y', 'U', 'V'), /*!< YUV444, X-Y-U-V. */ + kVIDEO_PixelFormatXYVU = FSL_VIDEO_FOURCC('X', 'Y', 'V', 'U'), /*!< YUV444, X-Y-V-U. */ +} video_pixel_format_t; + +/*! @brief Resolution definition. */ +typedef enum _video_resolution +{ + kVIDEO_ResolutionVGA = FSL_VIDEO_RESOLUTION(640, 480), /*!< VGA, 640 * 480 */ + kVIDEO_ResolutionQVGA = FSL_VIDEO_RESOLUTION(320, 240), /*!< QVGA, 320 * 240 */ + kVIDEO_ResolutionQQVGA = FSL_VIDEO_RESOLUTION(160, 120), /*!< QQVGA, 160 * 120 */ + kVIDEO_ResolutionCIF = FSL_VIDEO_RESOLUTION(352, 288), /*!< CIF, 352 * 288 */ + kVIDEO_ResolutionQCIF = FSL_VIDEO_RESOLUTION(176, 144), /*!< QCIF, 176 * 144 */ + kVIDEO_ResolutionQQCIF = FSL_VIDEO_RESOLUTION(88, 72), /*!< QQCIF, 88 * 72 */ + kVIDEO_Resolution720P = FSL_VIDEO_RESOLUTION(1280, 720), /*!< 720P, 1280 * 720 */ + kVIDEO_Resolution1080P = FSL_VIDEO_RESOLUTION(1920, 1080), /*!< 1080P, 1920 * 1280*/ + kVIDEO_ResolutionWXGA = FSL_VIDEO_RESOLUTION(1280, 800), /*!< WXGA, 1280 * 800 */ +} video_resolution_t; + +/*! + * @brief Ring buffer structure. + * + * There is one empty room reserved in the ring buffer, used to distinguish + * whether the ring buffer is full or empty. When rear equals front, it is empty; + * when rear+1 equals front, it is full. + */ +typedef struct +{ + volatile uint32_t rear; /*!< Pointer to save the incoming item. */ + volatile uint32_t front; /*!< Pointer to read out the item. */ + void *volatile *buf; /*!< Memory to the ring buffer. */ + uint32_t size; /*!< Ring buffer total size. */ +} video_ringbuf_t; + +/*! + * @brief Memory pool structure. + */ +typedef struct +{ + void *volatile pool; /*!< Pointer to the pool. */ + volatile uint32_t cnt; /*!< Count of memory blocks in the pool. */ +} video_mempool_t; + +/*! + * @brief Stack structure. + */ +typedef struct +{ + void **buf; /*!< Pointer to the memory to store the items. */ + volatile uint32_t top; /*!< Current top stack top. */ + uint32_t maxCount; /*!< Maximal count of items can be stored in the stack. */ +} video_stack_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Common + * @{ + */ + +/*! + * @brief Check the pixel format is YUV or not. + * + * @param format Pixel format. + */ +bool VIDEO_IsYUV(video_pixel_format_t format); + +/*! + * @brief Delay the specific time. + * + * @param ms How many milli-second to delay. + */ +void VIDEO_DelayMs(uint32_t ms); + +/*! + * @brief Get the pixel size in bits. + * + * @param pixelFormat The pixel format. + * @return Bits per pixel. + */ +uint8_t VIDEO_GetPixelSizeBits(video_pixel_format_t pixelFormat); + +/* @} */ + +/*! + * @name Ring buffer. + * @{ + */ + +/*! + * @brief Initializes ring buffer. + * + * @param ringbuf Pointer to the ring buffer handle. + * @param buf Memory to save the items. + * @param size Size of the @p buf. + * @return Returns @ref kStatus_Success if initialize success, otherwise returns + * error code. + */ +status_t VIDEO_RINGBUF_Init(video_ringbuf_t *ringbuf, void **buf, uint32_t size); + +/*! + * @brief Get one item from the ring buffer. + * + * @param ringbuf Pointer to the ring buffer handle. + * @param item Memory to save the item. + * @return Returns @ref kStatus_Success if get success, otherwise returns + * error code. + */ +status_t VIDEO_RINGBUF_Get(video_ringbuf_t *ringbuf, void **item); + +/*! + * @brief Put one item to the ring buffer. + * + * @param ringbuf Pointer to the ring buffer handle. + * @param item The new item to save. + * @return Returns @ref kStatus_Success if put success, otherwise returns + * error code. + */ +status_t VIDEO_RINGBUF_Put(video_ringbuf_t *ringbuf, void *item); + +/*! + * @brief Get current count of items in the ring buffer. + * + * @param ringbuf Pointer to the ring buffer handle. + * @return Returns the item count. + */ +uint32_t VIDEO_RINGBUF_GetLength(video_ringbuf_t *ringbuf); + +/*! + * @brief Check whether the ring buffer is empty. + * + * @param ringbuf Pointer to the ring buffer handle. + * @return Returns true if the ring buffer is empty, otherwise returns false. + */ +bool VIDEO_RINGBUF_IsEmpty(video_ringbuf_t *ringbuf); + +/*! + * @brief Check whether the ring buffer is full. + * + * @param ringbuf Pointer to the ring buffer handle. + * @return Returns true if the ring buffer is full, otherwise returns false. + */ +bool VIDEO_RINGBUF_IsFull(video_ringbuf_t *ringbuf); +/* @} */ + +/*! + * @name Memory Pool + * + * User can put memory block to the pool, or get memory block from the pool. + * There is no count limitation to put memory block in to the pool. The memory + * content in the pool might be modified. + * + * The memory block should be 4-byte aligned, and the dividable by 4-byte. + * + * @{ + */ + +/*! + * @brief Initializes memory pool. + * + * Initializes memory pool. Initial memory blocks in the memory pool is optional. + * If initial blocks are used, user should specify the initial block size and count. + * + * @param mempool Pointer to the memory pool handle. + * @param initMem Initial memory blocks to saved in the pool. + * @param size Every memory block's size (bytes) in the @p initMem. + * @param count Number of memory blocks @p initMem. + * @return Returns @ref kStatus_Success if initialize success, otherwise returns + * error code. + */ +status_t VIDEO_MEMPOOL_Init(video_mempool_t *mempool, void *initMem, uint32_t size, uint32_t count); + +/*! + * @brief Create an empty memory pool. + * + * @param mempool Pointer to the memory pool handle. + */ +void VIDEO_MEMPOOL_InitEmpty(video_mempool_t *mempool); + +/*! + * @brief Put memory block in the pool. + * + * @param mempool Pointer to the memory pool handle. + * @param mem Pointer to the memory block. + */ +void VIDEO_MEMPOOL_Put(video_mempool_t *mempool, void *mem); + +/*! + * @brief Get memory block in the pool. + * + * @param mempool Pointer to the memory pool handle. + * @return The memory block get from pool. If the pool is empty, returns NULL. + */ +void *VIDEO_MEMPOOL_Get(video_mempool_t *mempool); + +/*! + * @brief How many memory blocks in the pool. + * + * @param mempool Pointer to the memory pool handle. + * @return The memory block count in the pool + */ +uint32_t VIDEO_MEMPOOL_GetCount(video_mempool_t *mempool); + +/* @} */ + +/*! + * @name Stack which supports LIFO item management. + * @{ + */ + +/*! + * @brief Initializes stack. + * + * @param stack Pointer to the stack handle. + * @param buf Memory to save the items. + * @param size Size of the @p buf. + * @return Returns @ref kStatus_Success if initialize success, otherwise returns + * error code. + */ +status_t VIDEO_STACK_Init(video_stack_t *stack, void **buf, uint32_t size); + +/*! + * @brief Pop one item from the stack. + * + * @param stack Pointer to the stack handle. + * @param item Memory to save the item. + * @return Returns @ref kStatus_Success if get success, returns + * kStatus_Fail if the stack is empty. + */ +status_t VIDEO_STACK_Pop(video_stack_t *stack, void **item); + +/*! + * @brief Put one item to the stack. + * + * @param stack Pointer to the stack handle. + * @param item The new item to save. + * @return Returns @ref kStatus_Success if put success, returns + * kStatus_Fail if the stack is full. + */ +status_t VIDEO_STACK_Push(video_stack_t *stack, void *item); + +/*! + * @brief Get current count of items in the stack. + * + * @param stack Pointer to the stack handle. + * @return Returns the item count. + */ +static inline uint32_t VIDEO_STACK_GetCount(video_stack_t *stack) +{ + return stack->top; +} + +/*! + * @brief Get maxiumal count of items in the stack. + * + * @param stack Pointer to the stack handle. + * @return Returns the maxiumal count of items in the stack. + */ +static inline uint32_t VIDEO_STACK_GetMaxCount(video_stack_t *stack) +{ + return stack->maxCount; +} + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_VIDEO_COMMON_H_ */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/xip/SConscript b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/xip/SConscript new file mode 100644 index 00000000000..84d2e8e4f86 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/xip/SConscript @@ -0,0 +1,20 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +if GetDepend('BSP_USING_QSPIFLASH'): + cwd = GetCurrentDir() + src = Glob('*.c') + CPPPATH = [cwd] + + if rtconfig.PLATFORM in ['armcc', 'armclang']: + LINKFLAGS = ' --keep=*(.boot_hdr.ivt)' + LINKFLAGS += ' --keep=*(.boot_hdr.boot_data)' + LINKFLAGS += ' --keep=*(.boot_hdr.dcd_data)' + LINKFLAGS += ' --keep=*(.boot_hdr.conf)' + LINKFLAGS += ' --predefine="-DXIP_BOOT_HEADER_ENABLE=1"' + else: + LINKFLAGS = '' + + group = DefineGroup('xip', src, depend = [''], CPPPATH = CPPPATH, LINKFLAGS = LINKFLAGS) + Return('group') diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/xip/evkmimxrt1170_flexspi_nor_config.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/xip/evkmimxrt1170_flexspi_nor_config.c new file mode 100644 index 00000000000..ff2b4cce429 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/xip/evkmimxrt1170_flexspi_nor_config.c @@ -0,0 +1,53 @@ +/* + * Copyright 2018-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "evkmimxrt1170_flexspi_nor_config.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_board" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.conf"), used)) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.conf" +#endif + +const flexspi_nor_config_t qspiflash_config = { + .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + // Enable DDR mode, Wordaddassable, Safe configuration, Differential clock + .controllerMiscOption = 0x10, + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_133MHz, + .sflashA1Size = 16u * 1024u * 1024u, + .lookupTable = + { + // Read LUTs + FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18), + FLEXSPI_LUT_SEQ(MODE8_SDR, FLEXSPI_4PAD, 0x00, DUMMY_SDR, FLEXSPI_4PAD, 0x04), + FLEXSPI_LUT_SEQ(READ_SDR, FLEXSPI_4PAD, 0x04, 0, 0, 0), + }, + }, + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .ipcmdSerialClkFreq = 0x1, + .blockSize = 256u * 1024u, + .isUniformBlockSize = false, +}; +#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/xip/evkmimxrt1170_flexspi_nor_config.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/xip/evkmimxrt1170_flexspi_nor_config.h new file mode 100644 index 00000000000..aa3383d5ee4 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/xip/evkmimxrt1170_flexspi_nor_config.h @@ -0,0 +1,268 @@ +/* + * Copyright 2018-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __EVKMIMXRT1170_FLEXSPI_NOR_CONFIG__ +#define __EVKMIMXRT1170_FLEXSPI_NOR_CONFIG__ + +#include +#include +#include "fsl_common.h" + +/*! @name Driver version */ +/*@{*/ +/*! @brief XIP_BOARD driver version 2.0.1. */ +#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/* FLEXSPI memory config block related defintions */ +#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian +#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 +#define FLEXSPI_CFG_BLK_SIZE (512) + +/* FLEXSPI Feature related definitions */ +#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 + +/* Lookup table related defintions */ +#define CMD_INDEX_READ 0 +#define CMD_INDEX_READSTATUS 1 +#define CMD_INDEX_WRITEENABLE 2 +#define CMD_INDEX_WRITE 4 + +#define CMD_LUT_SEQ_IDX_READ 0 +#define CMD_LUT_SEQ_IDX_READSTATUS 1 +#define CMD_LUT_SEQ_IDX_WRITEENABLE 3 +#define CMD_LUT_SEQ_IDX_WRITE 9 + +#define CMD_SDR 0x01 +#define CMD_DDR 0x21 +#define RADDR_SDR 0x02 +#define RADDR_DDR 0x22 +#define CADDR_SDR 0x03 +#define CADDR_DDR 0x23 +#define MODE1_SDR 0x04 +#define MODE1_DDR 0x24 +#define MODE2_SDR 0x05 +#define MODE2_DDR 0x25 +#define MODE4_SDR 0x06 +#define MODE4_DDR 0x26 +#define MODE8_SDR 0x07 +#define MODE8_DDR 0x27 +#define WRITE_SDR 0x08 +#define WRITE_DDR 0x28 +#define READ_SDR 0x09 +#define READ_DDR 0x29 +#define LEARN_SDR 0x0A +#define LEARN_DDR 0x2A +#define DATSZ_SDR 0x0B +#define DATSZ_DDR 0x2B +#define DUMMY_SDR 0x0C +#define DUMMY_DDR 0x2C +#define DUMMY_RWDS_SDR 0x0D +#define DUMMY_RWDS_DDR 0x2D +#define JMP_ON_CS 0x1F +#define STOP 0 + +#define FLEXSPI_1PAD 0 +#define FLEXSPI_2PAD 1 +#define FLEXSPI_4PAD 2 +#define FLEXSPI_8PAD 3 + +#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ + FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) + +//!@brief Definitions for FlexSPI Serial Clock Frequency +typedef enum _FlexSpiSerialClockFreq +{ + kFlexSpiSerialClk_30MHz = 1, + kFlexSpiSerialClk_50MHz = 2, + kFlexSpiSerialClk_60MHz = 3, + kFlexSpiSerialClk_80MHz = 4, + kFlexSpiSerialClk_100MHz = 5, + kFlexSpiSerialClk_120MHz = 6, + kFlexSpiSerialClk_133MHz = 7, + kFlexSpiSerialClk_166MHz = 8, + kFlexSpiSerialClk_200MHz = 9, +} flexspi_serial_clk_freq_t; + +//!@brief FlexSPI clock configuration type +enum +{ + kFlexSpiClk_SDR, //!< Clock configure for SDR mode + kFlexSpiClk_DDR, //!< Clock configurat for DDR mode +}; + +//!@brief FlexSPI Read Sample Clock Source definition +typedef enum _FlashReadSampleClkSource +{ + kFlexSPIReadSampleClk_LoopbackInternally = 0, + kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, + kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, + kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, +} flexspi_read_sample_clk_t; + +//!@brief Misc feature bit definitions +enum +{ + kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable + kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable + kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable + kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable + kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable + kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable + kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication. +}; + +//!@brief Flash Type Definition +enum +{ + kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR + kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND + kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH + kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND + kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs +}; + +//!@brief Flash Pad Definitions +enum +{ + kSerialFlash_1Pad = 1, + kSerialFlash_2Pads = 2, + kSerialFlash_4Pads = 4, + kSerialFlash_8Pads = 8, +}; + +//!@brief FlexSPI LUT Sequence structure +typedef struct _lut_sequence +{ + uint8_t seqNum; //!< Sequence Number, valid number: 1-16 + uint8_t seqId; //!< Sequence Index, valid number: 0-15 + uint16_t reserved; +} flexspi_lut_seq_t; + +//!@brief Flash Configuration Command Type +enum +{ + kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc + kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command + kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode + kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode + kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode + kDeviceConfigCmdType_Reset, //!< Reset device command +}; + +//!@brief FlexSPI Memory Configuration Block +typedef struct _FlexSPIConfig +{ + uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL + uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix + uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use + uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 + uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 + uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 + uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For + //! Serial NAND, need to refer to datasheet + uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable + uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, + //! Generic configuration, etc. + uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for + //! DPI/QPI/OPI switch or reset command + flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt + //! sequence number, [31:16] Reserved + uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration + uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable + uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe + flexspi_lut_seq_t + configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq + uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use + uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands + uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use + uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more + //! details + uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details + uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal + uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot + //! Chapter for more details + uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot + //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH + uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use + uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 + uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 + uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 + uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 + uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value + uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value + uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value + uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value + uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command + uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands + uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns + uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 + uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - + //! busy flag is 0 when flash device is busy + uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences + flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences + uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use +} flexspi_mem_config_t; + +/* */ +#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0 +#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1 +#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2 +#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3 +#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4 +#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5 +#define NOR_CMD_INDEX_DUMMY 6 //!< 6 +#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7 + +#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \ + CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ + 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \ + CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ + 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \ + CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ + 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ + 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk + +/* + * Serial NOR configuration block + */ +typedef struct _flexspi_nor_config +{ + flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI + uint32_t pageSize; //!< Page size of Serial NOR + uint32_t sectorSize; //!< Sector size of Serial NOR + uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command + uint8_t isUniformBlockSize; //!< Sector/Block size is the same + uint8_t reserved0[2]; //!< Reserved for future use + uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3 + uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command + uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false + uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution + uint32_t blockSize; //!< Block size + uint32_t reserve2[11]; //!< Reserved for future use +} flexspi_nor_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif +#endif /* __EVKMIMXRT1170_FLEXSPI_NOR_CONFIG__ */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/xip/fsl_flexspi_nor_boot.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/xip/fsl_flexspi_nor_boot.c new file mode 100644 index 00000000000..1a8307928d0 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/xip/fsl_flexspi_nor_boot.c @@ -0,0 +1,49 @@ +/* + * Copyright 2019-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexspi_nor_boot.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_device" +#endif + +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.ivt"), used)) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.ivt" +#endif +/************************************* + * IVT Data + *************************************/ +const ivt image_vector_table = { + IVT_HEADER, /* IVT Header */ + IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ + IVT_RSVD, /* Reserved = 0 */ + (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ + (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ + (uint32_t)IVT_ADDRESS, /* Pointer to IVT Self (absolute address) */ + (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ + IVT_RSVD /* Reserved = 0 */ +}; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.boot_data"), used)) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.boot_data" +#endif +/************************************* + * Boot Data + *************************************/ +const BOOT_DATA_T boot_data = { + BOOT_IMAGE_BASE, /* boot start location */ + BOOT_IMAGE_SIZE, /* size */ + PLUGIN_FLAG, /* Plugin flag*/ + 0xFFFFFFFFU /* empty - extra data word */ +}; +#endif diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/xip/fsl_flexspi_nor_boot.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/xip/fsl_flexspi_nor_boot.h new file mode 100644 index 00000000000..e586d750e01 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/xip/fsl_flexspi_nor_boot.h @@ -0,0 +1,147 @@ +/* + * Copyright 2019-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __FLEXSPI_NOR_BOOT_H__ +#define __FLEXSPI_NOR_BOOT_H__ + +#include +#include "board.h" +#include "fsl_common.h" + +/*! @name Driver version */ +/*@{*/ +/*! @brief XIP_DEVICE driver version 2.0.4. */ +#define FSL_XIP_DEVICE_DRIVER_VERSION (MAKE_VERSION(2, 0, 4)) +/*@}*/ + +/************************************* + * IVT Data + *************************************/ +typedef struct _ivt_ +{ + /** @ref hdr with tag #HAB_TAG_IVT, length and HAB version fields + * (see @ref data) + */ + uint32_t hdr; + /** Absolute address of the first instruction to execute from the + * image + */ + uint32_t entry; + /** Reserved in this version of HAB: should be NULL. */ + uint32_t reserved1; + /** Absolute address of the image DCD: may be NULL. */ + uint32_t dcd; + /** Absolute address of the Boot Data: may be NULL, but not interpreted + * any further by HAB + */ + uint32_t boot_data; + /** Absolute address of the IVT.*/ + uint32_t self; + /** Absolute address of the image CSF.*/ + uint32_t csf; + /** Reserved in this version of HAB: should be zero. */ + uint32_t reserved2; +} ivt; + +#define IVT_MAJOR_VERSION 0x4 +#define IVT_MAJOR_VERSION_SHIFT 0x4 +#define IVT_MAJOR_VERSION_MASK 0xF +#define IVT_MINOR_VERSION 0x1 +#define IVT_MINOR_VERSION_SHIFT 0x0 +#define IVT_MINOR_VERSION_MASK 0xF + +#define IVT_VERSION(major, minor) \ + ((((major)&IVT_MAJOR_VERSION_MASK) << IVT_MAJOR_VERSION_SHIFT) | \ + (((minor)&IVT_MINOR_VERSION_MASK) << IVT_MINOR_VERSION_SHIFT)) + +/* IVT header */ +#define IVT_TAG_HEADER 0xD1 /**< Image Vector Table */ +#define IVT_SIZE 0x2000 +#define IVT_PAR IVT_VERSION(IVT_MAJOR_VERSION, IVT_MINOR_VERSION) +#define IVT_HEADER (IVT_TAG_HEADER | (IVT_SIZE << 8) | (IVT_PAR << 24)) + +/* Set resume entry */ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern uint32_t Reset_Handler[]; +#define IMAGE_ENTRY_ADDRESS ((uint32_t)Reset_Handler) +#define BOOT_IMAGE_BASE ((uint32_t)FLASH_BASE) +#define BOOT_IMAGE_SIZE ((uint32_t)FLASH_SIZE) +#define BOOT_DATA_ADDRESS &boot_data +#define IVT_ADDRESS &image_vector_table +#define DCD_DATA_ADDRESS dcd_data +#elif defined(__MCUXPRESSO) +extern uint32_t ResetISR[]; +extern uint32_t __boot_hdr_start__[]; +extern uint32_t __boot_hdr_ivt_loadaddr__[]; +extern uint32_t __boot_hdr_boot_data_loadaddr__[]; +extern uint32_t __boot_hdr_dcd_loadaddr__[]; +extern uint32_t _boot_loadaddr[]; +extern uint32_t _boot_size[]; +#define IMAGE_ENTRY_ADDRESS ((uint32_t)ResetISR) +#define BOOT_IMAGE_BASE ((uint32_t)_boot_loadaddr) +#define BOOT_IMAGE_SIZE ((uint32_t)_boot_size) +#define BOOT_DATA_ADDRESS ((uint32_t)__boot_hdr_boot_data_loadaddr__) +#define IVT_ADDRESS ((uint32_t)__boot_hdr_ivt_loadaddr__) +#define DCD_DATA_ADDRESS ((uint32_t)__boot_hdr_dcd_loadaddr__) +#elif defined(__ICCARM__) +extern uint32_t Reset_Handler[]; +#define IMAGE_ENTRY_ADDRESS ((uint32_t)Reset_Handler) +#define BOOT_IMAGE_BASE ((uint32_t)FLASH_BASE) +#define BOOT_IMAGE_SIZE ((uint32_t)FLASH_SIZE) +#define BOOT_DATA_ADDRESS &boot_data +#define IVT_ADDRESS &image_vector_table +#define DCD_DATA_ADDRESS dcd_data +#elif defined(__GNUC__) +extern uint32_t Reset_Handler[]; +#define IMAGE_ENTRY_ADDRESS ((uint32_t)Reset_Handler) +#define BOOT_IMAGE_BASE ((uint32_t)FLASH_BASE) +#define BOOT_IMAGE_SIZE ((uint32_t)FLASH_SIZE) +#define BOOT_DATA_ADDRESS &boot_data +#define IVT_ADDRESS &image_vector_table +#define DCD_DATA_ADDRESS dcd_data +#endif +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (1 == XIP_BOOT_HEADER_DCD_ENABLE) +#define DCD_ADDRESS DCD_DATA_ADDRESS +#else +#define DCD_ADDRESS 0 +#endif +#endif +#define CSF_ADDRESS 0 +#define IVT_RSVD (uint32_t)(0x00000000) + +/************************************* + * Boot Data + *************************************/ +typedef struct _boot_data_ +{ + uint32_t start; /* boot start location */ + uint32_t size; /* size */ + uint32_t plugin; /* plugin flag - 1 if downloaded application is plugin */ + uint32_t placeholder; /* placehoder to make even 0x10 size */ +} BOOT_DATA_T; + +#if __CORTEX_M == 7 +#define FLASH_BASE FlexSPI1_AMBA_BASE +#elif __CORTEX_M == 4 +#define FLASH_BASE FlexSPI1_ALIAS_BASE +#endif + +#if defined(BOARD_FLASH_SIZE) +#define FLASH_SIZE BOARD_FLASH_SIZE +#else +#error "Please define macro BOARD_FLASH_SIZE" +#endif +#define PLUGIN_FLAG (uint32_t)0 + +/* External Variables */ +const BOOT_DATA_T boot_data; +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (1 == XIP_BOOT_HEADER_DCD_ENABLE) +extern const uint8_t dcd_data[]; +#endif + +#endif /* __FLEXSPI_NOR_BOOT_H__ */ diff --git a/bsp/nxp/imx/imxrt/libraries/Kconfig b/bsp/nxp/imx/imxrt/libraries/Kconfig index 0a804fb7c3c..92ba176f195 100644 --- a/bsp/nxp/imx/imxrt/libraries/Kconfig +++ b/bsp/nxp/imx/imxrt/libraries/Kconfig @@ -33,3 +33,9 @@ config SOC_IMXRT1170_SERIES select ARCH_ARM_CORTEX_M7 select ARCH_ARM_CORTEX_FPU select PKG_USING_NXP_IMXRT_DRIVER + +config SOC_IMXRT1180_SERIES + bool + select ARCH_ARM_CORTEX_M33 + select ARCH_ARM_CORTEX_FPU + select PKG_USING_NXP_IMXRT_DRIVER \ No newline at end of file diff --git a/bsp/nxp/imx/imxrt/libraries/drivers/drv_uart.c b/bsp/nxp/imx/imxrt/libraries/drivers/drv_uart.c index 3160e870b4d..95bbc0e80ce 100644 --- a/bsp/nxp/imx/imxrt/libraries/drivers/drv_uart.c +++ b/bsp/nxp/imx/imxrt/libraries/drivers/drv_uart.c @@ -7,8 +7,8 @@ * Date Author Notes * 2017-10-10 Tanek the first version * 2019-5-10 misonyo add DMA TX and RX function + * 2026-4-29 Ran Add RT1180 support. */ - #include #ifdef BSP_USING_LPUART @@ -18,7 +18,9 @@ #include "board.h" #include "fsl_lpuart.h" #include "fsl_lpuart_edma.h" +#ifndef SOC_IMXRT1180_SERIES #include "fsl_dmamux.h" +#endif #define LOG_TAG "drv.usart" #include @@ -497,22 +499,27 @@ void edma_tx_callback(LPUART_Type *base, lpuart_edma_handle_t *handle, status_t rt_hw_serial_isr(&uart->serial, RT_SERIAL_EVENT_TX_DMADONE); } } - -static void imxrt_dma_rx_config(struct imxrt_uart *uart) -{ - RT_ASSERT(uart != RT_NULL); - - edma_transfer_config_t xferConfig; - struct rt_serial_rx_fifo *rx_fifo; - - DMAMUX_SetSource(DMAMUX, uart->dma_rx->channel, uart->dma_rx->request); - DMAMUX_EnableChannel(DMAMUX, uart->dma_rx->channel); - EDMA_CreateHandle(&uart->dma_rx->edma, DMA0, uart->dma_rx->channel); - EDMA_SetCallback(&uart->dma_rx->edma, edma_rx_callback, uart); - - rx_fifo = (struct rt_serial_rx_fifo *)uart->serial.serial_rx; - - EDMA_PrepareTransfer(&xferConfig, + static void imxrt_dma_rx_config(struct imxrt_uart *uart) + { + RT_ASSERT(uart != RT_NULL); + + edma_transfer_config_t xferConfig; + struct rt_serial_rx_fifo *rx_fifo; + + #ifndef SOC_IMXRT1180_SERIES + DMAMUX_SetSource(DMAMUX, uart->dma_rx->channel, uart->dma_rx->request); + DMAMUX_EnableChannel(DMAMUX, uart->dma_rx->channel); + #else + /* RT1180 uses EDMA4, configure DMA request source differently */ + EDMA_SetChannelMux(DMA0, uart->dma_rx->channel, uart->dma_rx->request); + #endif + + EDMA_CreateHandle(&uart->dma_rx->edma, DMA0, uart->dma_rx->channel); + EDMA_SetCallback(&uart->dma_rx->edma, edma_rx_callback, uart); + + rx_fifo = (struct rt_serial_rx_fifo *)uart->serial.serial_rx; + + EDMA_PrepareTransfer(&xferConfig, (void *)LPUART_GetDataRegisterAddress(uart->uart_base), sizeof(uint8_t), rx_fifo->buffer, @@ -521,74 +528,123 @@ static void imxrt_dma_rx_config(struct imxrt_uart *uart) uart->serial.config.bufsz, kEDMA_PeripheralToMemory); - EDMA_SubmitTransfer(&uart->dma_rx->edma, &xferConfig); - EDMA_EnableChannelInterrupts(DMA0, uart->dma_rx->channel, kEDMA_MajorInterruptEnable | kEDMA_HalfInterruptEnable); - EDMA_EnableAutoStopRequest(DMA0, uart->dma_rx->channel, false); - /* complement to adjust final destination address */ - uart->dma_rx->edma.base->TCD[uart->dma_rx->channel].DLAST_SGA = -(uart->serial.config.bufsz); - EDMA_StartTransfer(&uart->dma_rx->edma); - LPUART_EnableRxDMA(uart->uart_base, true); - - LPUART_EnableInterrupts(uart->uart_base, kLPUART_IdleLineInterruptEnable); - NVIC_SetPriority(uart->irqn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 4, 0)); - EnableIRQ(uart->irqn); - - LOG_D("%s dma rx config done\n", uart->name); -} - -static void imxrt_dma_tx_config(struct imxrt_uart *uart) -{ - RT_ASSERT(uart != RT_NULL); - - DMAMUX_SetSource(DMAMUX, uart->dma_tx->channel, uart->dma_tx->request); - DMAMUX_EnableChannel(DMAMUX, uart->dma_tx->channel); - EDMA_CreateHandle(&uart->dma_tx->edma, DMA0, uart->dma_tx->channel); - - LPUART_TransferCreateHandleEDMA(uart->uart_base, - &uart->dma_tx->uart_edma, - edma_tx_callback, - uart, - &uart->dma_tx->edma, - RT_NULL); - - LOG_D("%s dma tx config done\n", uart->name); -} - -#endif - -uint32_t GetUartSrcFreq(LPUART_Type *uart_base) -{ - uint32_t freq; -#ifdef SOC_IMXRT1170_SERIES - uint32_t base = (uint32_t) uart_base; - switch (base) - { - case LPUART1_BASE: - freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart1); - break; - case LPUART12_BASE: - freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart12); - break; - default: - freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart2); - break; - } -#else - /* To make it simple, we assume default PLL and divider settings, and the only variable + EDMA_SubmitTransfer(&uart->dma_rx->edma, &xferConfig); + EDMA_EnableChannelInterrupts(DMA0, uart->dma_rx->channel, kEDMA_MajorInterruptEnable | kEDMA_HalfInterruptEnable); + EDMA_EnableAutoStopRequest(DMA0, uart->dma_rx->channel, false); + /* complement to adjust final destination address */ + uart->dma_rx->edma.base->TCD[uart->dma_rx->channel].DLAST_SGA = -(uart->serial.config.bufsz); + EDMA_StartTransfer(&uart->dma_rx->edma); + LPUART_EnableRxDMA(uart->uart_base, true); + + LPUART_EnableInterrupts(uart->uart_base, kLPUART_IdleLineInterruptEnable); + NVIC_SetPriority(uart->irqn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 4, 0)); + EnableIRQ(uart->irqn); + + LOG_D("%s dma rx config done\n", uart->name); + } + + static void imxrt_dma_tx_config(struct imxrt_uart *uart) + { + RT_ASSERT(uart != RT_NULL); + + #ifndef SOC_IMXRT1180_SERIES + DMAMUX_SetSource(DMAMUX, uart->dma_tx->channel, uart->dma_tx->request); + DMAMUX_EnableChannel(DMAMUX, uart->dma_tx->channel); + #else + /* RT1180 uses EDMA4, configure DMA request source differently */ + EDMA_SetChannelMux(DMA0, uart->dma_tx->channel, uart->dma_tx->request); + #endif + + EDMA_CreateHandle(&uart->dma_tx->edma, DMA0, uart->dma_tx->channel); + + LPUART_TransferCreateHandleEDMA(uart->uart_base, + &uart->dma_tx->uart_edma, + edma_tx_callback, + uart, + &uart->dma_tx->edma, + RT_NULL); + + LOG_D("%s dma tx config done\n", uart->name); + } +#endif + uint32_t GetUartSrcFreq(LPUART_Type *uart_base) + { + uint32_t freq; + #if defined(SOC_IMXRT1170_SERIES) + uint32_t base = (uint32_t) uart_base; + switch (base) + { + case LPUART1_BASE: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart1); + break; + case LPUART12_BASE: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart12); + break; + default: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart2); + break; + } + #elif defined(SOC_IMXRT1180_SERIES) + /* RT1180 uses different clock root architecture */ + uint32_t base = (uint32_t) uart_base; + switch (base) + { + case LPUART1_BASE: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0102); + break; + case LPUART2_BASE: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0102); + break; + case LPUART3_BASE: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0304); + break; + case LPUART4_BASE: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0304); + break; + case LPUART5_BASE: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0506); + break; + case LPUART6_BASE: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0506); + break; + case LPUART7_BASE: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0708); + break; + case LPUART8_BASE: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0708); + break; + case LPUART9_BASE: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0910); + break; + case LPUART10_BASE: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0910); + break; + case LPUART11_BASE: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart1112); + break; + case LPUART12_BASE: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart1112); + break; + + default: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0102); + break; + } + #else + /* To make it simple, we assume default PLL and divider settings, and the only variable from application is use PLL3 source or OSC source */ - if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */ - { - freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U); - } - else - { - freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U); - } -#endif - return freq; - -} - + if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */ + { + freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U); + } + else + { + freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U); + } + #endif + return freq; + + } static rt_err_t imxrt_configure(struct rt_serial_device *serial, struct serial_configure *cfg) { struct imxrt_uart *uart;