1. User Story
As a Simulation Engineer, I want to run RISC-V assembly code against both the standard reference model (Spike) and our RTL implementation, so that I can verify functional correctness, performance accuracy, and compliance with the RISC-V ISA specification.
2. Acceptance Criteria
Each criterion defines measurable conditions for successful validation of RTL execution against the reference model.
Functional Correctness Verification
- Condition: The RTL simulation must correctly execute all RISC-V instructions and match the behavior of the standard reference model (Spike).
- Test: Run RISC-V ISA compliance test cases and compare outputs between RTL and Spike.
- Satisfaction: No mismatches occur for standard test cases.
Cycle-Accurate Co-Simulation
- Condition: RTL simulation must match Spike cycle-for-cycle where applicable.
- Test: Instrument RTL to log execution cycle-by-cycle and compare with Spike.
- Satisfaction: Expected cycle counts align with architecture design.
Pipeline Behavior & Debugging
- Condition: Pipeline stages (fetch, decode, execute, memory, write-back) should exhibit expected behavior.
- Test: Run diagnostic test cases to validate pipeline operation, stalling, and forwarding.
- Satisfaction: No unexpected pipeline hazards or execution stalls.
Memory & Cache Validation
- Condition: Memory accesses should be correctly translated and executed in RTL.
- Test: Run memory-intensive workloads to check for cache coherence, data integrity, and latency.
- Satisfaction: RTL memory operations match reference model expectations.
Exception & Interrupt Handling
- Condition: The processor must correctly handle exceptions (e.g., misaligned access, illegal instructions) and interrupts.
- Test: Execute a set of exception/interrupt tests and observe correct trap handling.
- Satisfaction: RTL correctly traps and executes exception handlers.
Performance Benchmarking
- Condition: Measure IPC (Instructions Per Cycle) and compare with target expectations.
- Test: Execute benchmarks such as Dhrystone, CoreMark, and SPEC-like tests.
- Satisfaction: IPC is within expected performance range.
CI/CD Integration for Automated Testing
- Condition: Simulation should be automated within the CI/CD pipeline for continuous verification.
- Test: Ensure tests are automatically triggered on new commits, with pass/fail reports.
- Satisfaction: No regressions or failures across commits.
3. Definition of Done (DoD)
The simulation framework will be considered complete when it meets the following functional, non-functional, and validation criteria:
✅ Functional Requirements:
✔ Accurate execution of all RISC-V integer and memory operations.
✔ Ability to run real-world applications, benchmarks, and custom test programs.
✔ Cycle-accurate comparison with Spike and expected pipeline execution.
✅ Non-Functional Requirements:
✔ Efficient simulation runtime to minimize execution time.
✔ Scalable testbench supporting future design extensions.
✅ Testing & Validation:
✔ Passing results in RISC-V compliance tests.
✔ High coverage of instructions, branches, and memory operations.
✔ Verified exception handling and pipeline correctness.
✅ Documentation:
✔ Detailed setup guide for running and debugging simulations.
✔ Clear logs and debugging mechanisms for test failures.
✔ Weekly progress reports and test summaries.
4. Top-Level Tasks (GitHub Sub-Issues)
📌 Develop scripts to load and execute RISC-V binaries.
📌 Integrate automated test result comparison between RTL and Spike.
📌 Set up CI/CD automation for regression testing.
5. Dependencies & External Resources
📌 Spike RISC-V Emulator – [GitHub](https://github.com/riscv/riscv-isa-sim)
📌 Verilator RTL Simulator – [GitHub](https://github.com/verilator/verilator)
📌 RISC-V Compliance Tests – [GitHub](https://github.com/riscv/riscv-tests)
📌 Official RISC-V ISA Specification – [RISC-V.org](https://riscv.org/)
6. Additional Notes
🔹 This simulation effort is critical to ensuring correctness before synthesis and tape-out.
🔹 Collaboration with the CPU Design and Synthesis teams is required.
🔹 Weekly status updates should be provided in this issue.
1. User Story
As a Simulation Engineer, I want to run RISC-V assembly code against both the standard reference model (Spike) and our RTL implementation, so that I can verify functional correctness, performance accuracy, and compliance with the RISC-V ISA specification.
2. Acceptance Criteria
Each criterion defines measurable conditions for successful validation of RTL execution against the reference model.
Functional Correctness Verification
Cycle-Accurate Co-Simulation
Pipeline Behavior & Debugging
Memory & Cache Validation
Exception & Interrupt Handling
Performance Benchmarking
CI/CD Integration for Automated Testing
3. Definition of Done (DoD)
The simulation framework will be considered complete when it meets the following functional, non-functional, and validation criteria:
✅ Functional Requirements:
✔ Accurate execution of all RISC-V integer and memory operations.
✔ Ability to run real-world applications, benchmarks, and custom test programs.
✔ Cycle-accurate comparison with Spike and expected pipeline execution.
✅ Non-Functional Requirements:
✔ Efficient simulation runtime to minimize execution time.
✔ Scalable testbench supporting future design extensions.
✅ Testing & Validation:
✔ Passing results in RISC-V compliance tests.
✔ High coverage of instructions, branches, and memory operations.
✔ Verified exception handling and pipeline correctness.
✅ Documentation:
✔ Detailed setup guide for running and debugging simulations.
✔ Clear logs and debugging mechanisms for test failures.
✔ Weekly progress reports and test summaries.
4. Top-Level Tasks (GitHub Sub-Issues)
📌 Install and configure Verilator (or an equivalent RTL simulator).
📌 Set up Spike as a reference simulator.
📌 Define logging mechanisms for execution comparison.
📌 Develop scripts to load and execute RISC-V binaries.
📌 Integrate automated test result comparison between RTL and Spike.
📌 Set up CI/CD automation for regression testing.
📌 Execute and validate all RISC-V base instructions (RV32I, RV64I, etc.).
📌 Compare RTL execution trace with Spike reference model.
📌 Debug and fix mismatches in instruction execution.
📌 Instrument RTL to track pipeline behavior.
📌 Measure IPC and identify performance bottlenecks.
📌 Optimize execution flow for efficiency.
📌 Run memory consistency and cache validation tests.
📌 Execute exception/interrupt test cases.
📌 Verify correct trapping and exception handling.
📌 Write a detailed simulation user guide.
📌 Document known issues and debugging steps.
📌 Generate summary reports for verification progress.
5. Dependencies & External Resources
📌 Spike RISC-V Emulator – [GitHub](https://github.com/riscv/riscv-isa-sim)
📌 Verilator RTL Simulator – [GitHub](https://github.com/verilator/verilator)
📌 RISC-V Compliance Tests – [GitHub](https://github.com/riscv/riscv-tests)
📌 Official RISC-V ISA Specification – [RISC-V.org](https://riscv.org/)
6. Additional Notes
🔹 This simulation effort is critical to ensuring correctness before synthesis and tape-out.
🔹 Collaboration with the CPU Design and Synthesis teams is required.
🔹 Weekly status updates should be provided in this issue.