diff --git a/.github/dependabot.yml b/.github/dependabot.yml index fc85287baa7a..bea2e99f9405 100644 --- a/.github/dependabot.yml +++ b/.github/dependabot.yml @@ -5,6 +5,8 @@ updates: directory: "/" schedule: interval: "weekly" + cooldown: + default-days: 7 commit-message: prefix: "ci: github: " labels: [] @@ -17,6 +19,8 @@ updates: directory: "/doc" schedule: interval: "weekly" + cooldown: + default-days: 7 commit-message: prefix: "ci: doc: " labels: [] diff --git a/.github/workflows/assigner.yml b/.github/workflows/assigner.yml index e83f2422869d..a4670d05b800 100644 --- a/.github/workflows/assigner.yml +++ b/.github/workflows/assigner.yml @@ -28,7 +28,7 @@ jobs: steps: - name: Check out source code - uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 + uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2 with: fetch-depth: 0 persist-credentials: false @@ -40,7 +40,7 @@ jobs: - name: Fetch west.yml/Maintainer.yml from pull request if: > - github.event_name == 'pull_request_target' + github.event_name == 'pull_request_target' && github.base_ref == 'main' run: | git fetch origin pull/${{ github.event.pull_request.number }}/merge git show FETCH_HEAD:west.yml > pr_west.yml @@ -63,7 +63,11 @@ jobs: FLAGS+=" -r ${{ github.event.repository.name }}" FLAGS+=" -M MAINTAINERS.yml" if [ "${{ github.event_name }}" = "pull_request_target" ]; then - FLAGS+=" -P ${{ github.event.pull_request.number }} --updated-manifest pr_west.yml --updated-maintainer-file pr_MAINTAINERS.yml" + if [ "${{ github.base_ref }}" = "main" ]; then + FLAGS+=" -P ${{ github.event.pull_request.number }} --updated-manifest pr_west.yml --updated-maintainer-file pr_MAINTAINERS.yml" + else + FLAGS+=" -P ${{ github.event.pull_request.number }}" + fi elif [ "${{ github.event_name }}" = "issues" ]; then FLAGS+=" -I ${{ github.event.issue.number }}" elif [ "${{ github.event_name }}" = "schedule" ]; then @@ -76,7 +80,7 @@ jobs: - name: Check maintainer file changes if: > - github.event_name == 'pull_request_target' + github.event_name == 'pull_request_target' && github.base_ref == 'main' env: GITHUB_TOKEN: ${{ secrets.ZB_PR_ASSIGNER_GITHUB_TOKEN }} run: | diff --git a/.github/workflows/backport_issue_check.yml b/.github/workflows/backport_issue_check.yml index 7811f30d050a..34b5e4596392 100644 --- a/.github/workflows/backport_issue_check.yml +++ b/.github/workflows/backport_issue_check.yml @@ -26,10 +26,10 @@ jobs: steps: - name: Check out source code - uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 + uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2 - name: Set up Python - uses: actions/setup-python@e797f83bcb11b83ae66e0230d6156d7c80228e7c # v6.0.0 + uses: actions/setup-python@a309ff8b426b58ec0e2a45f0f869d46889d02405 # v6.2.0 with: python-version: 3.12 cache: pip diff --git a/.github/workflows/bsim-tests-publish.yaml b/.github/workflows/bsim-tests-publish.yaml index 17d424f18493..28d69b7bcc44 100644 --- a/.github/workflows/bsim-tests-publish.yaml +++ b/.github/workflows/bsim-tests-publish.yaml @@ -19,12 +19,12 @@ jobs: steps: - name: Download artifacts - uses: dawidd6/action-download-artifact@ac66b43f0e6a346234dd65d4d0c8fbb31cb316e5 # v11 + uses: dawidd6/action-download-artifact@0bd50d53a6d7fb5cb921e607957e9cc12b4ce392 # v12 with: run_id: ${{ github.event.workflow_run.id }} - name: Publish BabbleSim Test Results - uses: EnricoMi/publish-unit-test-result-action@34d7c956a59aed1bfebf31df77b8de55db9bbaaf # v2.21.0 + uses: EnricoMi/publish-unit-test-result-action@27d65e188ec43221b20d26de30f4892fad91df2f # v2.22.0 with: check_name: BabbleSim Test Results comment_mode: off diff --git a/.github/workflows/bsim-tests.yaml b/.github/workflows/bsim-tests.yaml index 37e2ca050164..7c8082fcd7c1 100644 --- a/.github/workflows/bsim-tests.yaml +++ b/.github/workflows/bsim-tests.yaml @@ -74,7 +74,7 @@ jobs: git remote set-url origin ${GITHUB_SERVER_URL}/${GITHUB_REPOSITORY} - name: Checkout - uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 + uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2 with: fetch-depth: 0 @@ -102,7 +102,7 @@ jobs: pip install -r scripts/requirements-actions.txt --require-hashes - name: Check common triggering files - uses: tj-actions/changed-files@24d32ffd492484c1d75e0c0b894501ddb9d30d62 # v47.0.0 + uses: tj-actions/changed-files@e0021407031f5be11a464abee9a0776171c79891 # v47.0.1 id: check-common-files with: files: | @@ -121,7 +121,7 @@ jobs: modules/hal_nordic/** - name: Check if Bluethooth files changed - uses: tj-actions/changed-files@24d32ffd492484c1d75e0c0b894501ddb9d30d62 # v47.0.0 + uses: tj-actions/changed-files@e0021407031f5be11a464abee9a0776171c79891 # v47.0.1 id: check-bluetooth-files with: files: | @@ -131,7 +131,7 @@ jobs: tests/bsim/bluetooth/ - name: Check if Networking files changed - uses: tj-actions/changed-files@24d32ffd492484c1d75e0c0b894501ddb9d30d62 # v47.0.0 + uses: tj-actions/changed-files@e0021407031f5be11a464abee9a0776171c79891 # v47.0.1 id: check-networking-files with: files: | @@ -144,7 +144,7 @@ jobs: include/zephyr/net/ieee802154* - name: Check if UART files changed - uses: tj-actions/changed-files@24d32ffd492484c1d75e0c0b894501ddb9d30d62 # v47.0.0 + uses: tj-actions/changed-files@e0021407031f5be11a464abee9a0776171c79891 # v47.0.1 id: check-uart-files with: files: | @@ -189,7 +189,7 @@ jobs: - name: Upload Unit Test Results in HTML if: always() - uses: actions/upload-artifact@330a01c490aca151604b8cf639adc76d48f6c5d4 # v5.0.0 + uses: actions/upload-artifact@b7c566a772e6b6bfb58ed0dc250532a479d7789f # v6.0.0 with: name: HTML Unit Test Results if-no-files-found: ignore @@ -197,7 +197,7 @@ jobs: junit.html - name: Publish Unit Test Results - uses: EnricoMi/publish-unit-test-result-action@34d7c956a59aed1bfebf31df77b8de55db9bbaaf # v2.21.0 + uses: EnricoMi/publish-unit-test-result-action@27d65e188ec43221b20d26de30f4892fad91df2f # v2.22.0 with: check_name: Bsim Test Results files: "junit.xml" @@ -205,7 +205,7 @@ jobs: - name: Upload Event Details if: always() - uses: actions/upload-artifact@330a01c490aca151604b8cf639adc76d48f6c5d4 # v5.0.0 + uses: actions/upload-artifact@b7c566a772e6b6bfb58ed0dc250532a479d7789f # v6.0.0 with: name: event path: | diff --git a/.github/workflows/bug_snapshot.yaml b/.github/workflows/bug_snapshot.yaml index 8ab3035bf036..f31ab42add98 100644 --- a/.github/workflows/bug_snapshot.yaml +++ b/.github/workflows/bug_snapshot.yaml @@ -23,10 +23,10 @@ jobs: steps: - name: Checkout - uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 + uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2 - name: Set up Python - uses: actions/setup-python@e797f83bcb11b83ae66e0230d6156d7c80228e7c # v6.0.0 + uses: actions/setup-python@a309ff8b426b58ec0e2a45f0f869d46889d02405 # v6.2.0 with: python-version: 3.12 cache: pip @@ -51,7 +51,7 @@ jobs: echo "BUGS_PICKLE_PATH=${BUGS_PICKLE_PATH}" >> ${GITHUB_ENV} - name: Configure AWS Credentials - uses: aws-actions/configure-aws-credentials@00943011d9042930efac3dcd3a170e4273319bc8 # v5.1.0 + uses: aws-actions/configure-aws-credentials@61815dcd50bd041e203e49132bacad1fd04d2708 # v5.1.1 with: aws-access-key-id: ${{ vars.AWS_BUILDS_ZEPHYR_BUG_SNAPSHOT_ACCESS_KEY_ID }} aws-secret-access-key: ${{ secrets.AWS_BUILDS_ZEPHYR_BUG_SNAPSHOT_SECRET_ACCESS_KEY }} diff --git a/.github/workflows/clang.yaml b/.github/workflows/clang.yaml index 91e9c6e27e91..4a75f5d0ec1f 100644 --- a/.github/workflows/clang.yaml +++ b/.github/workflows/clang.yaml @@ -53,7 +53,7 @@ jobs: git remote set-url origin ${GITHUB_SERVER_URL}/${GITHUB_REPOSITORY} - name: Checkout - uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 + uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2 with: fetch-depth: 0 persist-credentials: false @@ -123,7 +123,7 @@ jobs: - name: Upload Unit Test Results if: always() - uses: actions/upload-artifact@330a01c490aca151604b8cf639adc76d48f6c5d4 # v5.0.0 + uses: actions/upload-artifact@b7c566a772e6b6bfb58ed0dc250532a479d7789f # v6.0.0 with: name: Unit Test Results (Subset ${{ matrix.subset }}) path: | @@ -140,18 +140,18 @@ jobs: if: (success() || failure()) steps: - name: Checkout - uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 + uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2 with: fetch-depth: 0 persist-credentials: false - name: Download Artifacts - uses: actions/download-artifact@018cc2cf5baa6db3ef3c5f8a56943fffe632ef53 # v6.0.0 + uses: actions/download-artifact@37930b1c2abaa49bbe596cd826c3c89aef350131 # v7.0.0 with: path: artifacts - name: Set up Python - uses: actions/setup-python@e797f83bcb11b83ae66e0230d6156d7c80228e7c # v6.0.0 + uses: actions/setup-python@a309ff8b426b58ec0e2a45f0f869d46889d02405 # v6.2.0 with: python-version: 3.12 cache: pip @@ -168,7 +168,7 @@ jobs: - name: Upload Unit Test Results in HTML if: always() - uses: actions/upload-artifact@330a01c490aca151604b8cf639adc76d48f6c5d4 # v5.0.0 + uses: actions/upload-artifact@b7c566a772e6b6bfb58ed0dc250532a479d7789f # v6.0.0 with: name: HTML Unit Test Results if-no-files-found: ignore @@ -176,7 +176,7 @@ jobs: junit-clang.html - name: Publish Unit Test Results - uses: EnricoMi/publish-unit-test-result-action@34d7c956a59aed1bfebf31df77b8de55db9bbaaf # v2.21.0 + uses: EnricoMi/publish-unit-test-result-action@27d65e188ec43221b20d26de30f4892fad91df2f # v2.22.0 if: always() with: check_name: Unit Test Results diff --git a/.github/workflows/codecov.yaml b/.github/workflows/codecov.yaml index af14276612e0..09940c46bd11 100644 --- a/.github/workflows/codecov.yaml +++ b/.github/workflows/codecov.yaml @@ -67,12 +67,12 @@ jobs: git remote set-url origin ${GITHUB_SERVER_URL}/${GITHUB_REPOSITORY} - name: checkout - uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 + uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2 with: fetch-depth: 0 - name: Set up Python - uses: actions/setup-python@e797f83bcb11b83ae66e0230d6156d7c80228e7c # v6.0.0 + uses: actions/setup-python@a309ff8b426b58ec0e2a45f0f869d46889d02405 # v6.2.0 with: python-version: 3.12 cache: pip @@ -126,7 +126,7 @@ jobs: - name: Upload Doxygen Coverage Results if: matrix.platform == 'unit_testing' - uses: actions/upload-artifact@330a01c490aca151604b8cf639adc76d48f6c5d4 # v5.0.0 + uses: actions/upload-artifact@b7c566a772e6b6bfb58ed0dc250532a479d7789f # v6.0.0 with: name: doxygen-coverage-results path: | @@ -145,7 +145,7 @@ jobs: - name: Upload Coverage Results if: always() - uses: actions/upload-artifact@330a01c490aca151604b8cf639adc76d48f6c5d4 # v5.0.0 + uses: actions/upload-artifact@b7c566a772e6b6bfb58ed0dc250532a479d7789f # v6.0.0 with: name: Coverage Data (Subset ${{ matrix.normalized }}) path: | @@ -161,12 +161,12 @@ jobs: steps: - name: checkout - uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 + uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2 with: fetch-depth: 0 - name: Set up Python - uses: actions/setup-python@e797f83bcb11b83ae66e0230d6156d7c80228e7c # v6.0.0 + uses: actions/setup-python@a309ff8b426b58ec0e2a45f0f869d46889d02405 # v6.2.0 with: python-version: 3.12 cache: pip @@ -177,7 +177,7 @@ jobs: pip install -r scripts/requirements-actions.txt --require-hashes - name: Download Artifacts - uses: actions/download-artifact@018cc2cf5baa6db3ef3c5f8a56943fffe632ef53 # v6.0.0 + uses: actions/download-artifact@37930b1c2abaa49bbe596cd826c3c89aef350131 # v7.0.0 with: path: coverage/reports @@ -242,7 +242,7 @@ jobs: - name: Upload Merged Coverage Results and Report if: always() - uses: actions/upload-artifact@330a01c490aca151604b8cf639adc76d48f6c5d4 # v5.0.0 + uses: actions/upload-artifact@b7c566a772e6b6bfb58ed0dc250532a479d7789f # v6.0.0 with: name: Coverage Data and report path: | @@ -253,7 +253,7 @@ jobs: - name: Upload test coverage to Codecov if: always() - uses: codecov/codecov-action@5a1091511ad55cbe89839c7260b706298ca349f7 # v5.5.1 + uses: codecov/codecov-action@671740ac38dd9b0130fbe1cec585b89eea48d3de # v5.5.2 with: env_vars: OS,PYTHON fail_ci_if_error: false @@ -264,7 +264,7 @@ jobs: - name: Upload Doxygen coverage to Codecov if: always() - uses: codecov/codecov-action@5a1091511ad55cbe89839c7260b706298ca349f7 # v5.5.1 + uses: codecov/codecov-action@671740ac38dd9b0130fbe1cec585b89eea48d3de # v5.5.2 with: env_vars: OS,PYTHON fail_ci_if_error: false diff --git a/.github/workflows/codeql.yml b/.github/workflows/codeql.yml index dd3aa9b9f7d2..cefe4222440a 100644 --- a/.github/workflows/codeql.yml +++ b/.github/workflows/codeql.yml @@ -36,10 +36,10 @@ jobs: config: ./.github/codeql/codeql-js-config.yml steps: - name: Checkout - uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 + uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2 - name: Initialize CodeQL - uses: github/codeql-action/init@0499de31b99561a6d14a36a5f662c2a54f91beee # v4.31.2 + uses: github/codeql-action/init@cdefb33c0f6224e58673d9004f47f7cb3e328b89 # v4.31.10 with: languages: ${{ matrix.language }} build-mode: ${{ matrix.build-mode }} @@ -53,6 +53,6 @@ jobs: exit 0 - name: Perform CodeQL Analysis - uses: github/codeql-action/analyze@0499de31b99561a6d14a36a5f662c2a54f91beee # v4.31.2 + uses: github/codeql-action/analyze@cdefb33c0f6224e58673d9004f47f7cb3e328b89 # v4.31.10 with: category: "/language:${{matrix.language}}" diff --git a/.github/workflows/coding_guidelines.yml b/.github/workflows/coding_guidelines.yml index 258e80d1d5e4..07b78b5cae35 100644 --- a/.github/workflows/coding_guidelines.yml +++ b/.github/workflows/coding_guidelines.yml @@ -11,13 +11,13 @@ jobs: name: Run coding guidelines checks on patch series (PR) steps: - name: Checkout the code - uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 + uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2 with: ref: ${{ github.event.pull_request.head.sha }} fetch-depth: 0 - name: Set up Python - uses: actions/setup-python@e797f83bcb11b83ae66e0230d6156d7c80228e7c # v6.0.0 + uses: actions/setup-python@a309ff8b426b58ec0e2a45f0f869d46889d02405 # v6.2.0 with: python-version: 3.12 cache: pip diff --git a/.github/workflows/compliance.yml b/.github/workflows/compliance.yml index 26e41485ef67..8b7a8a2fb5fe 100644 --- a/.github/workflows/compliance.yml +++ b/.github/workflows/compliance.yml @@ -21,7 +21,7 @@ jobs: echo "$HOME/.local/bin" >> $GITHUB_PATH - name: Checkout the code - uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 + uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2 with: ref: ${{ github.event.pull_request.head.sha }} fetch-depth: 0 @@ -44,7 +44,7 @@ jobs: git log --pretty=oneline | head -n 10 - name: Set up Python - uses: actions/setup-python@e797f83bcb11b83ae66e0230d6156d7c80228e7c # v6.0.0 + uses: actions/setup-python@a309ff8b426b58ec0e2a45f0f869d46889d02405 # v6.2.0 with: python-version: 3.12 cache: pip @@ -61,7 +61,7 @@ jobs: west update -o=--depth=1 -n 2>&1 1> west.update.log || west update -o=--depth=1 -n 2>&1 1> west.update2.log - name: Setup Node.js - uses: actions/setup-node@2028fbc5c25fe9cf00d9f06a71cc4710d4507903 # v6.0.0 + uses: actions/setup-node@6044e13b5dc448c55e2357c09f80417699197238 # v6.2.0 with: node-version: "lts/*" cache: npm @@ -91,14 +91,14 @@ jobs: ./scripts/ci/check_compliance.py --annotate $excludes -c origin/${BASE_REF}.. - name: upload-results - uses: actions/upload-artifact@330a01c490aca151604b8cf639adc76d48f6c5d4 # v5.0.0 + uses: actions/upload-artifact@b7c566a772e6b6bfb58ed0dc250532a479d7789f # v6.0.0 continue-on-error: true with: name: compliance.xml path: compliance.xml - name: Upload dts linter patch - uses: actions/upload-artifact@330a01c490aca151604b8cf639adc76d48f6c5d4 # v5.0.0 + uses: actions/upload-artifact@b7c566a772e6b6bfb58ed0dc250532a479d7789f # v6.0.0 continue-on-error: true if: hashFiles('dts_linter.patch') != '' with: diff --git a/.github/workflows/daily_test_version.yml b/.github/workflows/daily_test_version.yml index d604c7fe9d3c..76911805b467 100644 --- a/.github/workflows/daily_test_version.yml +++ b/.github/workflows/daily_test_version.yml @@ -20,19 +20,19 @@ jobs: steps: - name: Configure AWS Credentials - uses: aws-actions/configure-aws-credentials@00943011d9042930efac3dcd3a170e4273319bc8 # v5.1.0 + uses: aws-actions/configure-aws-credentials@61815dcd50bd041e203e49132bacad1fd04d2708 # v5.1.1 with: aws-access-key-id: ${{ vars.AWS_TESTING_ACCESS_KEY_ID }} aws-secret-access-key: ${{ secrets.AWS_TESTING_SECRET_ACCESS_KEY }} aws-region: us-east-1 - name: checkout - uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 + uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2 with: fetch-depth: 0 - name: Set up Python - uses: actions/setup-python@e797f83bcb11b83ae66e0230d6156d7c80228e7c # v6.0.0 + uses: actions/setup-python@a309ff8b426b58ec0e2a45f0f869d46889d02405 # v6.2.0 with: python-version: 3.12 cache: pip diff --git a/.github/workflows/devicetree_checks.yml b/.github/workflows/devicetree_checks.yml index c0efa60951f0..9b94faaae79e 100644 --- a/.github/workflows/devicetree_checks.yml +++ b/.github/workflows/devicetree_checks.yml @@ -33,10 +33,10 @@ jobs: os: [ubuntu-22.04, macos-14, windows-2022] steps: - name: checkout - uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 + uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2 - name: Set up Python ${{ matrix.python-version }} - uses: actions/setup-python@e797f83bcb11b83ae66e0230d6156d7c80228e7c # v6.0.0 + uses: actions/setup-python@a309ff8b426b58ec0e2a45f0f869d46889d02405 # v6.2.0 with: python-version: ${{ matrix.python-version }} cache: pip diff --git a/.github/workflows/doc-build.yml b/.github/workflows/doc-build.yml index 5eb9c5534b7c..09a20e5bdf09 100644 --- a/.github/workflows/doc-build.yml +++ b/.github/workflows/doc-build.yml @@ -27,12 +27,12 @@ jobs: file_check: ${{ steps.check-doc-files.outputs.any_modified }} steps: - name: checkout - uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 + uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2 with: ref: ${{ github.event.pull_request.head.sha }} fetch-depth: 0 - name: Check if Documentation related files changed - uses: tj-actions/changed-files@24d32ffd492484c1d75e0c0b894501ddb9d30d62 # v47.0.0 + uses: tj-actions/changed-files@e0021407031f5be11a464abee9a0776171c79891 # v47.0.1 id: check-doc-files with: files: | @@ -92,7 +92,7 @@ jobs: git remote set-url origin ${GITHUB_SERVER_URL}/${GITHUB_REPOSITORY} - name: Checkout - uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 + uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2 with: ref: ${{ github.event.pull_request.head.sha }} fetch-depth: 0 @@ -156,13 +156,13 @@ jobs: tar --use-compress-program="xz -T0" -cf api-coverage.tar.xz coverage-report - name: Upload HTML output - uses: actions/upload-artifact@330a01c490aca151604b8cf639adc76d48f6c5d4 # v5.0.0 + uses: actions/upload-artifact@b7c566a772e6b6bfb58ed0dc250532a479d7789f # v6.0.0 with: name: html-output path: html-output.tar.xz - name: Upload Doxygen coverage artifacts - uses: actions/upload-artifact@330a01c490aca151604b8cf639adc76d48f6c5d4 # v5.0.0 + uses: actions/upload-artifact@b7c566a772e6b6bfb58ed0dc250532a479d7789f # v6.0.0 with: name: api-coverage path: api-coverage.tar.xz @@ -183,7 +183,7 @@ jobs: echo "API Coverage Report will be available shortly at: ${API_COVERAGE_URL}" >> $GITHUB_STEP_SUMMARY - name: Upload PR number - uses: actions/upload-artifact@330a01c490aca151604b8cf639adc76d48f6c5d4 # v5.0.0 + uses: actions/upload-artifact@b7c566a772e6b6bfb58ed0dc250532a479d7789f # v6.0.0 if: github.event_name == 'pull_request' with: name: pr_num @@ -202,12 +202,12 @@ jobs: steps: - name: checkout - uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 + uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2 with: path: zephyr - name: Set up Python - uses: actions/setup-python@e797f83bcb11b83ae66e0230d6156d7c80228e7c # v6.0.0 + uses: actions/setup-python@a309ff8b426b58ec0e2a45f0f869d46889d02405 # v6.2.0 with: python-version: 3.12 cache: pip @@ -230,7 +230,7 @@ jobs: echo "/opt/doxygen-${DOXYGEN_VERSION}/bin" >> $GITHUB_PATH - name: Setup Zephyr project - uses: zephyrproject-rtos/action-zephyr-setup@c125c5ebeeadbd727fa740b407f862734af1e52a # v1.0.9 + uses: zephyrproject-rtos/action-zephyr-setup@360ff9b36e58499d9eb28015cdcde7ca03a5b04d # v1.0.12 with: app-path: zephyr toolchains: 'arm-zephyr-eabi' @@ -259,7 +259,7 @@ jobs: - name: upload-build if: always() - uses: actions/upload-artifact@330a01c490aca151604b8cf639adc76d48f6c5d4 # v5.0.0 + uses: actions/upload-artifact@b7c566a772e6b6bfb58ed0dc250532a479d7789f # v6.0.0 with: name: pdf-output if-no-files-found: ignore diff --git a/.github/workflows/doc-publish-pr.yml b/.github/workflows/doc-publish-pr.yml index 054046815b2a..28ee3e6a81f5 100644 --- a/.github/workflows/doc-publish-pr.yml +++ b/.github/workflows/doc-publish-pr.yml @@ -25,7 +25,7 @@ jobs: steps: - name: Download artifacts id: download-artifacts - uses: dawidd6/action-download-artifact@ac66b43f0e6a346234dd65d4d0c8fbb31cb316e5 # v11 + uses: dawidd6/action-download-artifact@0bd50d53a6d7fb5cb921e607957e9cc12b4ce392 # v12 with: workflow: doc-build.yml run_id: ${{ github.event.workflow_run.id }} @@ -43,7 +43,7 @@ jobs: - name: Check PR number if: steps.download-artifacts.outputs.found_artifact == 'true' id: check-pr - uses: carpentries/actions/check-valid-pr@2e20fd5ee53b691e27455ce7ca3b16ea885140e8 # v0.15.0 + uses: carpentries/actions/check-valid-pr@083bb9952b1414bd2b9e10ecec1717c938aba4c5 # v0.17.0 with: pr: ${{ env.PR_NUM }} sha: ${{ github.event.workflow_run.head_sha }} @@ -66,7 +66,7 @@ jobs: - name: Configure AWS Credentials if: steps.download-artifacts.outputs.found_artifact == 'true' - uses: aws-actions/configure-aws-credentials@00943011d9042930efac3dcd3a170e4273319bc8 # v5.1.0 + uses: aws-actions/configure-aws-credentials@61815dcd50bd041e203e49132bacad1fd04d2708 # v5.1.1 with: aws-access-key-id: ${{ vars.AWS_BUILDS_ZEPHYR_PR_ACCESS_KEY_ID }} aws-secret-access-key: ${{ secrets.AWS_BUILDS_ZEPHYR_PR_SECRET_ACCESS_KEY }} diff --git a/.github/workflows/doc-publish.yml b/.github/workflows/doc-publish.yml index 14c620846e12..2df0b240675d 100644 --- a/.github/workflows/doc-publish.yml +++ b/.github/workflows/doc-publish.yml @@ -27,7 +27,7 @@ jobs: steps: - name: Download artifacts - uses: dawidd6/action-download-artifact@ac66b43f0e6a346234dd65d4d0c8fbb31cb316e5 # v11 + uses: dawidd6/action-download-artifact@0bd50d53a6d7fb5cb921e607957e9cc12b4ce392 # v12 with: workflow: doc-build.yml run_id: ${{ github.event.workflow_run.id }} @@ -40,7 +40,7 @@ jobs: fi - name: Configure AWS Credentials - uses: aws-actions/configure-aws-credentials@00943011d9042930efac3dcd3a170e4273319bc8 # v5.1.0 + uses: aws-actions/configure-aws-credentials@61815dcd50bd041e203e49132bacad1fd04d2708 # v5.1.1 with: aws-access-key-id: ${{ vars.AWS_DOCS_ACCESS_KEY_ID }} aws-secret-access-key: ${{ secrets.AWS_DOCS_SECRET_ACCESS_KEY }} diff --git a/.github/workflows/doxygen-coverage-delta.yml b/.github/workflows/doxygen-coverage-delta.yml new file mode 100644 index 000000000000..9aedc35f9761 --- /dev/null +++ b/.github/workflows/doxygen-coverage-delta.yml @@ -0,0 +1,100 @@ +# SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +# Workflow that triggers on changes impacting API documentation and that checks that any newly +# introduced API is properly documented. + +name: Doxygen Coverage Delta Check + +on: + pull_request: + paths: + - 'include/**' + - 'subsys/testsuite/include/**' + - 'subsys/testsuite/ztest/include/**' + - 'scripts/ci/doxygen_coverage_diff.py' + - '.github/workflows/doxygen-coverage-delta.yml' + branches: + - main + - v*-branch + - collab-* + +permissions: + contents: read + +jobs: + doc-coverage-diff: + name: "Doxygen Coverage Delta Check" + runs-on: + group: zephyr-runner-v2-linux-x64-4xlarge + container: + image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.28.7.20251127 + options: '--entrypoint /bin/bash' + timeout-minutes: 60 + env: + BASE_REF: ${{ github.base_ref }} + + steps: + - name: Apply container owner mismatch workaround + run: | + git config --global --add safe.directory ${GITHUB_WORKSPACE} + + - name: Clone cached Zephyr repository + continue-on-error: true + run: | + git clone --shared /repo-cache/zephyrproject/zephyr . + git remote set-url origin ${GITHUB_SERVER_URL}/${GITHUB_REPOSITORY} + + - name: Checkout PR Branch + uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2 + with: + ref: ${{ github.event.pull_request.head.sha }} + fetch-depth: 0 + + - name: Environment Setup + run: | + git config --global user.email "bot@zephyrproject.org" + git config --global user.name "Zephyr Builder" + git rebase origin/${BASE_REF} + git clean -f -d + + west init -l . || true + west update --path-cache /repo-cache/zephyrproject 2>&1 1> west.update.log || west update --path-cache /repo-cache/zephyrproject 2>&1 1> west.update.log || ( rm -rf ../modules ../bootloader ../tools && west update --path-cache /repo-cache/zephyrproject) + west forall -c 'git reset --hard HEAD' + + echo "ZEPHYR_SDK_INSTALL_DIR=/opt/toolchains/zephyr-sdk-$( cat SDK_VERSION )" >> $GITHUB_ENV + + - name: Install Python packages + run: | + pip install -r scripts/requirements-actions.txt --require-hashes + pip install -r doc/requirements.txt --require-hashes + + - name: Generate PR branch coverage JSON + run: | + make -C doc doxygen-coverage-json + mv doc/_build/doc-coverage.json pr-coverage.json + + - name: Generate Base branch coverage JSON + run: | + git worktree add --detach ../base-branch origin/${BASE_REF} + echo "BASE_ROOT=$(readlink -f ../base-branch)" >> $GITHUB_ENV + cd ../base-branch + west update + # Use the PR branch's doc build configuration to ensure consistent + # coverage generation between branches (plus, the target may not exist in base) + cp ${GITHUB_WORKSPACE}/doc/CMakeLists.txt ${GITHUB_WORKSPACE}/doc/Makefile doc/ + make -C doc doxygen-coverage-json + cp doc/_build/doc-coverage.json ${GITHUB_WORKSPACE}/base-coverage.json + + - name: Check for undocumented new API + run: | + PR_ROOT=$(pwd) + + python3 scripts/ci/doxygen_coverage_diff.py \ + --reference base-coverage.json \ + --comparison pr-coverage.json \ + --strip-reference-prefix "$BASE_ROOT" \ + --strip-comparison-prefix "$PR_ROOT" \ + --warn-paths "include/zephyr/dt-bindings" \ + --warn-paths "include/zephyr/posix" \ + --summary-file "$GITHUB_STEP_SUMMARY" diff --git a/.github/workflows/errno.yml b/.github/workflows/errno.yml index f717e62c68d7..1e71580341d3 100644 --- a/.github/workflows/errno.yml +++ b/.github/workflows/errno.yml @@ -15,12 +15,12 @@ jobs: runs-on: ubuntu-24.04 steps: - name: checkout - uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 + uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2 with: path: zephyr - name: Setup Zephyr project - uses: zephyrproject-rtos/action-zephyr-setup@c125c5ebeeadbd727fa740b407f862734af1e52a # v1.0.9 + uses: zephyrproject-rtos/action-zephyr-setup@360ff9b36e58499d9eb28015cdcde7ca03a5b04d # v1.0.12 with: app-path: zephyr toolchains: 'arm-zephyr-eabi' diff --git a/.github/workflows/footprint-tracking.yml b/.github/workflows/footprint-tracking.yml index 010ed9ec1b30..6d049f4580fd 100644 --- a/.github/workflows/footprint-tracking.yml +++ b/.github/workflows/footprint-tracking.yml @@ -62,13 +62,13 @@ jobs: sudo apt-get install -y python3-venv - name: checkout - uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 + uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2 with: ref: ${{ github.event.pull_request.head.sha }} fetch-depth: 0 - name: Set up Python - uses: actions/setup-python@e797f83bcb11b83ae66e0230d6156d7c80228e7c # v6.0.0 + uses: actions/setup-python@a309ff8b426b58ec0e2a45f0f869d46889d02405 # v6.2.0 with: python-version: 3.12 cache: pip @@ -89,7 +89,7 @@ jobs: west update 2>&1 1> west.update.log || west update 2>&1 1> west.update2.log - name: Configure AWS Credentials - uses: aws-actions/configure-aws-credentials@00943011d9042930efac3dcd3a170e4273319bc8 # v5.1.0 + uses: aws-actions/configure-aws-credentials@61815dcd50bd041e203e49132bacad1fd04d2708 # v5.1.1 with: aws-access-key-id: ${{ vars.AWS_TESTING_ACCESS_KEY_ID }} aws-secret-access-key: ${{ secrets.AWS_TESTING_SECRET_ACCESS_KEY }} diff --git a/.github/workflows/greet_first_time_contributor.yml b/.github/workflows/greet_first_time_contributor.yml index 6a499275461e..be0616d4194d 100644 --- a/.github/workflows/greet_first_time_contributor.yml +++ b/.github/workflows/greet_first_time_contributor.yml @@ -18,7 +18,7 @@ jobs: issues: write # to comment on issues steps: - - uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 + - uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2 - uses: zephyrproject-rtos/action-first-interaction@58853996b1ac504b8e0f6964301f369d2bb22e5c # v1.1.1+zephyr.6 with: repo-token: ${{ secrets.GITHUB_TOKEN }} diff --git a/.github/workflows/hello_world_multiplatform.yaml b/.github/workflows/hello_world_multiplatform.yaml index 6d4e5cf369bc..34ff7340f74d 100644 --- a/.github/workflows/hello_world_multiplatform.yaml +++ b/.github/workflows/hello_world_multiplatform.yaml @@ -32,7 +32,7 @@ jobs: runs-on: ${{ matrix.os }} steps: - name: Checkout - uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 + uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2 with: path: zephyr fetch-depth: 0 @@ -54,15 +54,15 @@ jobs: git log --graph --oneline HEAD...${PR_HEAD} - name: Set up Python - uses: actions/setup-python@e797f83bcb11b83ae66e0230d6156d7c80228e7c # v6.0.0 + uses: actions/setup-python@a309ff8b426b58ec0e2a45f0f869d46889d02405 # v6.2.0 with: python-version: 3.12 - name: Setup Zephyr project - uses: zephyrproject-rtos/action-zephyr-setup@c125c5ebeeadbd727fa740b407f862734af1e52a # v1.0.9 + uses: zephyrproject-rtos/action-zephyr-setup@360ff9b36e58499d9eb28015cdcde7ca03a5b04d # v1.0.12 with: app-path: zephyr - toolchains: aarch64-zephyr-elf:arc-zephyr-elf:arc64-zephyr-elf:arm-zephyr-eabi:mips-zephyr-elf:riscv64-zephyr-elf:sparc-zephyr-elf:x86_64-zephyr-elf:xtensa-dc233c_zephyr-elf:xtensa-sample_controller32_zephyr-elf:rx-zephyr-elf + toolchains: arm-zephyr-eabi:riscv64-zephyr-elf ccache-cache-key: hw-${{ matrix.os }} - name: Build firmware @@ -76,11 +76,19 @@ jobs: elif [ "${{ runner.os }}-${{ runner.arch }}" == "Linux-ARM64" ]; then EXTRA_TWISTER_FLAGS="--exclude-platform native_sim/native" fi - west twister --runtime-artifact-cleanup --force-color --inline-logs -T samples/hello_world -T samples/cpp/hello_world -v $EXTRA_TWISTER_FLAGS + west twister \ + -p native_sim -p qemu_cortex_m0 -p qemu_riscv32 -p qemu_riscv64 \ + --runtime-artifact-cleanup \ + --force-color \ + --inline-logs \ + -T samples/hello_world \ + -T samples/cpp/hello_world \ + -v \ + $EXTRA_TWISTER_FLAGS - name: Upload artifacts if: failure() - uses: actions/upload-artifact@330a01c490aca151604b8cf639adc76d48f6c5d4 # v5.0.0 + uses: actions/upload-artifact@b7c566a772e6b6bfb58ed0dc250532a479d7789f # v6.0.0 with: if-no-files-found: ignore path: diff --git a/.github/workflows/issue_count.yml b/.github/workflows/issue_count.yml index a7bfe9e2507c..830e41d34c1e 100644 --- a/.github/workflows/issue_count.yml +++ b/.github/workflows/issue_count.yml @@ -38,14 +38,14 @@ jobs: token: ${{ secrets.GITHUB_TOKEN }} - name: upload-stats - uses: actions/upload-artifact@330a01c490aca151604b8cf639adc76d48f6c5d4 # v5.0.0 + uses: actions/upload-artifact@b7c566a772e6b6bfb58ed0dc250532a479d7789f # v6.0.0 continue-on-error: true with: name: ${{ env.OUTPUT_FILE_NAME }} path: ${{ env.OUTPUT_FILE_NAME }} - name: Configure AWS Credentials - uses: aws-actions/configure-aws-credentials@00943011d9042930efac3dcd3a170e4273319bc8 # v5.1.0 + uses: aws-actions/configure-aws-credentials@61815dcd50bd041e203e49132bacad1fd04d2708 # v5.1.1 with: aws-access-key-id: ${{ vars.AWS_TESTING_ACCESS_KEY_ID }} aws-secret-access-key: ${{ secrets.AWS_TESTING_SECRET_ACCESS_KEY }} diff --git a/.github/workflows/license_check.yml b/.github/workflows/license_check.yml index b7547d95e65c..67751a067a9a 100644 --- a/.github/workflows/license_check.yml +++ b/.github/workflows/license_check.yml @@ -11,7 +11,7 @@ jobs: name: Scan code for licenses steps: - name: Checkout the code - uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 + uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2 with: fetch-depth: 0 - name: Scan the code @@ -20,7 +20,7 @@ jobs: with: directory-to-scan: 'scan/' - name: Artifact Upload - uses: actions/upload-artifact@330a01c490aca151604b8cf639adc76d48f6c5d4 # v5.0.0 + uses: actions/upload-artifact@b7c566a772e6b6bfb58ed0dc250532a479d7789f # v6.0.0 with: name: scancode path: ./artifacts diff --git a/.github/workflows/manifest.yml b/.github/workflows/manifest.yml index 3cbf007f187e..dee44f2cebe7 100644 --- a/.github/workflows/manifest.yml +++ b/.github/workflows/manifest.yml @@ -13,7 +13,7 @@ jobs: name: Manifest steps: - name: Checkout the code - uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 + uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2 with: path: zephyrproject/zephyr fetch-depth: 0 @@ -30,7 +30,7 @@ jobs: west init -l . || true - name: Manifest - uses: zephyrproject-rtos/action-manifest@09983f53d3d878791aa37a7755ae44d695f4c1e5 # v2.0.0 + uses: zephyrproject-rtos/action-manifest@9cda77710c1c49c6734490ec7233f6d2d43f9503 with: github-token: ${{ secrets.GITHUB_TOKEN }} manifest-path: 'west.yml' diff --git a/.github/workflows/pinned-gh-actions.yml b/.github/workflows/pinned-gh-actions.yml index f1d1bad4a43e..8cdc84780c69 100644 --- a/.github/workflows/pinned-gh-actions.yml +++ b/.github/workflows/pinned-gh-actions.yml @@ -14,6 +14,6 @@ jobs: runs-on: ubuntu-latest steps: - name: Checkout code - uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 + uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2 - name: Ensure SHA pinned actions - uses: zgosalvez/github-actions-ensure-sha-pinned-actions@9e9574ef04ea69da568d6249bd69539ccc704e74 # v4.0.0 + uses: zgosalvez/github-actions-ensure-sha-pinned-actions@6124774845927d14c601359ab8138699fa5b70c3 # v4.0.1 diff --git a/.github/workflows/pr_metadata_check.yml b/.github/workflows/pr_metadata_check.yml index bec49363375f..e8e297f8c17a 100644 --- a/.github/workflows/pr_metadata_check.yml +++ b/.github/workflows/pr_metadata_check.yml @@ -8,7 +8,6 @@ on: - reopened - labeled - unlabeled - - edited permissions: contents: read @@ -24,10 +23,10 @@ jobs: timeout-minutes: 30 steps: - name: Checkout - uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 + uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2 - name: Set up Python - uses: actions/setup-python@e797f83bcb11b83ae66e0230d6156d7c80228e7c # v6.0.0 + uses: actions/setup-python@a309ff8b426b58ec0e2a45f0f869d46889d02405 # v6.2.0 with: python-version: 3.12 cache: pip diff --git a/.github/workflows/pylib_tests.yml b/.github/workflows/pylib_tests.yml index dfd6d5d44eb5..e5c8e8966ae6 100644 --- a/.github/workflows/pylib_tests.yml +++ b/.github/workflows/pylib_tests.yml @@ -32,10 +32,10 @@ jobs: os: [ubuntu-24.04] steps: - name: checkout - uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 + uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2 - name: Set up Python ${{ matrix.python-version }} - uses: actions/setup-python@e797f83bcb11b83ae66e0230d6156d7c80228e7c # v6.0.0 + uses: actions/setup-python@a309ff8b426b58ec0e2a45f0f869d46889d02405 # v6.2.0 with: python-version: ${{ matrix.python-version }} cache: pip diff --git a/.github/workflows/release.yml b/.github/workflows/release.yml index dcaca963a016..a832d1e7b931 100644 --- a/.github/workflows/release.yml +++ b/.github/workflows/release.yml @@ -15,7 +15,7 @@ jobs: permissions: contents: write # to create GitHub release entry steps: - - uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 + - uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2 with: fetch-depth: 0 @@ -31,7 +31,7 @@ jobs: args: spdx -o zephyr-${{ steps.get_version.outputs.VERSION }}.spdx - name: upload-results - uses: actions/upload-artifact@330a01c490aca151604b8cf639adc76d48f6c5d4 # v5.0.0 + uses: actions/upload-artifact@b7c566a772e6b6bfb58ed0dc250532a479d7789f # v6.0.0 continue-on-error: true with: name: zephyr-${{ steps.get_version.outputs.VERSION }}.spdx diff --git a/.github/workflows/scorecards.yml b/.github/workflows/scorecards.yml index 8c35bee033e5..c9d3abc1b409 100644 --- a/.github/workflows/scorecards.yml +++ b/.github/workflows/scorecards.yml @@ -29,7 +29,7 @@ jobs: steps: - name: "Checkout code" - uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 + uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2 with: persist-credentials: false @@ -47,7 +47,7 @@ jobs: # uploads of run results in SARIF format to the repository Actions tab. # https://docs.github.com/en/actions/advanced-guides/storing-workflow-data-as-artifacts - name: "Upload artifact" - uses: actions/upload-artifact@330a01c490aca151604b8cf639adc76d48f6c5d4 # v5.0.0 + uses: actions/upload-artifact@b7c566a772e6b6bfb58ed0dc250532a479d7789f # v6.0.0 with: name: SARIF file path: results.sarif @@ -56,6 +56,6 @@ jobs: # Upload the results to GitHub's code scanning dashboard (optional). # Commenting out will disable upload of results to your repo's Code Scanning dashboard - name: "Upload to code-scanning" - uses: github/codeql-action/upload-sarif@0499de31b99561a6d14a36a5f662c2a54f91beee # v4.31.2 + uses: github/codeql-action/upload-sarif@cdefb33c0f6224e58673d9004f47f7cb3e328b89 # v4.31.10 with: sarif_file: results.sarif diff --git a/.github/workflows/scripts_tests.yml b/.github/workflows/scripts_tests.yml index f3acc3da4fcc..3f5efcbec18c 100644 --- a/.github/workflows/scripts_tests.yml +++ b/.github/workflows/scripts_tests.yml @@ -32,7 +32,7 @@ jobs: os: [ubuntu-24.04] steps: - name: checkout - uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 + uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2 with: ref: ${{ github.event.pull_request.head.sha }} fetch-depth: 0 @@ -52,7 +52,7 @@ jobs: git log --graph --oneline HEAD...${PR_HEAD} - name: Set up Python ${{ matrix.python-version }} - uses: actions/setup-python@e797f83bcb11b83ae66e0230d6156d7c80228e7c # v6.0.0 + uses: actions/setup-python@a309ff8b426b58ec0e2a45f0f869d46889d02405 # v6.2.0 with: python-version: ${{ matrix.python-version }} cache: pip diff --git a/.github/workflows/stale_issue.yml b/.github/workflows/stale_issue.yml index 96d38de631f0..fd3474c910ed 100644 --- a/.github/workflows/stale_issue.yml +++ b/.github/workflows/stale_issue.yml @@ -16,7 +16,7 @@ jobs: issues: write # to comment on stale issues steps: - - uses: actions/stale@5f858e3efba33a5ca4407a664cc011ad407f2008 # v10.1.0 + - uses: actions/stale@997185467fa4f803885201cee163a9f38240193d # v10.1.1 with: stale-pr-message: 'This pull request has been marked as stale because it has been open (more than) 60 days with no activity. Remove the stale label or add a comment saying that you diff --git a/.github/workflows/stats_merged_prs.yml b/.github/workflows/stats_merged_prs.yml index e18fc30f5c7d..2a04aafca98e 100644 --- a/.github/workflows/stats_merged_prs.yml +++ b/.github/workflows/stats_merged_prs.yml @@ -16,10 +16,10 @@ jobs: runs-on: ubuntu-24.04 steps: - name: checkout - uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 + uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2 - name: Set up Python - uses: actions/setup-python@e797f83bcb11b83ae66e0230d6156d7c80228e7c # v6.0.0 + uses: actions/setup-python@a309ff8b426b58ec0e2a45f0f869d46889d02405 # v6.2.0 with: python-version: 3.12 cache: pip diff --git a/.github/workflows/twister-publish.yaml b/.github/workflows/twister-publish.yaml index a6ff339df57e..87f350b88ce7 100644 --- a/.github/workflows/twister-publish.yaml +++ b/.github/workflows/twister-publish.yaml @@ -23,12 +23,12 @@ jobs: steps: # Needed for elasticearch and upload script - name: Checkout - uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 + uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2 with: fetch-depth: 0 persist-credentials: false - name: Set up Python - uses: actions/setup-python@e797f83bcb11b83ae66e0230d6156d7c80228e7c # v6.0.0 + uses: actions/setup-python@a309ff8b426b58ec0e2a45f0f869d46889d02405 # v6.2.0 with: python-version: 3.12 cache: pip @@ -39,7 +39,7 @@ jobs: - name: Download Artifacts id: download-artifacts - uses: dawidd6/action-download-artifact@ac66b43f0e6a346234dd65d4d0c8fbb31cb316e5 # v11 + uses: dawidd6/action-download-artifact@0bd50d53a6d7fb5cb921e607957e9cc12b4ce392 # v12 with: path: artifacts workflow: twister.yml diff --git a/.github/workflows/twister.yaml b/.github/workflows/twister.yaml index 186373b15c5f..90e46eef511b 100644 --- a/.github/workflows/twister.yaml +++ b/.github/workflows/twister.yaml @@ -42,7 +42,7 @@ jobs: steps: - name: Checkout if: github.event_name == 'pull_request' - uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 + uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2 with: ref: ${{ github.event.pull_request.head.sha }} fetch-depth: 0 @@ -51,7 +51,7 @@ jobs: - name: Set up Python if: github.event_name == 'pull_request' - uses: actions/setup-python@e797f83bcb11b83ae66e0230d6156d7c80228e7c # v6.0.0 + uses: actions/setup-python@a309ff8b426b58ec0e2a45f0f869d46889d02405 # v6.2.0 with: python-version: 3.12 cache: pip @@ -65,7 +65,7 @@ jobs: - name: Setup Zephyr project if: github.event_name == 'pull_request' - uses: zephyrproject-rtos/action-zephyr-setup@c125c5ebeeadbd727fa740b407f862734af1e52a # v1.0.9 + uses: zephyrproject-rtos/action-zephyr-setup@360ff9b36e58499d9eb28015cdcde7ca03a5b04d # v1.0.12 with: app-path: zephyr enable-ccache: false @@ -171,7 +171,7 @@ jobs: git remote set-url origin ${GITHUB_SERVER_URL}/${GITHUB_REPOSITORY} - name: Checkout - uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 + uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2 with: ref: ${{ github.event.pull_request.head.sha }} fetch-depth: 0 @@ -283,7 +283,7 @@ jobs: - name: Upload Unit Test Results if: always() - uses: actions/upload-artifact@330a01c490aca151604b8cf639adc76d48f6c5d4 # v5.0.0 + uses: actions/upload-artifact@b7c566a772e6b6bfb58ed0dc250532a479d7789f # v6.0.0 with: name: Unit Test Results (Subset ${{ matrix.subset }}) if-no-files-found: ignore @@ -305,7 +305,7 @@ jobs: - if: matrix.subset == 1 && github.event_name == 'push' name: Upload the list of Python packages - uses: actions/upload-artifact@330a01c490aca151604b8cf639adc76d48f6c5d4 # v5.0.0 + uses: actions/upload-artifact@b7c566a772e6b6bfb58ed0dc250532a479d7789f # v6.0.0 with: name: Frozen PIP package set path: | @@ -323,14 +323,14 @@ jobs: steps: - name: Check out source code - uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 + uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2 with: ref: ${{ github.event.pull_request.head.sha }} fetch-depth: 0 persist-credentials: false - name: Set up Python - uses: actions/setup-python@e797f83bcb11b83ae66e0230d6156d7c80228e7c # v6.0.0 + uses: actions/setup-python@a309ff8b426b58ec0e2a45f0f869d46889d02405 # v6.2.0 with: python-version: 3.12 cache: pip @@ -341,7 +341,7 @@ jobs: pip install -r scripts/requirements-actions.txt --require-hashes - name: Download Artifacts - uses: actions/download-artifact@018cc2cf5baa6db3ef3c5f8a56943fffe632ef53 # v6.0.0 + uses: actions/download-artifact@37930b1c2abaa49bbe596cd826c3c89aef350131 # v7.0.0 with: path: artifacts @@ -352,7 +352,7 @@ jobs: - name: Upload Unit Test Results if: always() - uses: actions/upload-artifact@330a01c490aca151604b8cf639adc76d48f6c5d4 # v5.0.0 + uses: actions/upload-artifact@b7c566a772e6b6bfb58ed0dc250532a479d7789f # v6.0.0 with: name: Unit Test Results if-no-files-found: ignore @@ -362,12 +362,12 @@ jobs: - name: Upload test results to Codecov if: ${{ !cancelled() && (github.event_name == 'push') }} - uses: codecov/test-results-action@47f89e9acb64b76debcd5ea40642d25a4adced9f # v1.1.1 + uses: codecov/test-results-action@0fa95f0e1eeaafde2c782583b36b28ad0d8c77d3 # v1.2.1 with: token: ${{ secrets.CODECOV_TOKEN }} - name: Publish Unit Test Results - uses: EnricoMi/publish-unit-test-result-action@34d7c956a59aed1bfebf31df77b8de55db9bbaaf # v2.21.0 + uses: EnricoMi/publish-unit-test-result-action@27d65e188ec43221b20d26de30f4892fad91df2f # v2.22.0 with: check_name: Unit Test Results files: "**/twister.xml" @@ -384,7 +384,7 @@ jobs: - name: Upload Twister Analysis Results if: needs.twister-build.result == 'failure' - uses: actions/upload-artifact@330a01c490aca151604b8cf639adc76d48f6c5d4 # v5.0.0 + uses: actions/upload-artifact@b7c566a772e6b6bfb58ed0dc250532a479d7789f # v6.0.0 with: name: Twister Analysis Results if-no-files-found: ignore diff --git a/.github/workflows/twister_tests.yml b/.github/workflows/twister_tests.yml index 7efdab39f03e..b19c31fe1023 100644 --- a/.github/workflows/twister_tests.yml +++ b/.github/workflows/twister_tests.yml @@ -39,10 +39,10 @@ jobs: os: [ubuntu-24.04] steps: - name: checkout - uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 + uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2 - name: Set up Python ${{ matrix.python-version }} - uses: actions/setup-python@e797f83bcb11b83ae66e0230d6156d7c80228e7c # v6.0.0 + uses: actions/setup-python@a309ff8b426b58ec0e2a45f0f869d46889d02405 # v6.2.0 with: python-version: ${{ matrix.python-version }} cache: pip diff --git a/.github/workflows/twister_tests_blackbox.yml b/.github/workflows/twister_tests_blackbox.yml index 279a68f672be..c175e41fb197 100644 --- a/.github/workflows/twister_tests_blackbox.yml +++ b/.github/workflows/twister_tests_blackbox.yml @@ -27,34 +27,32 @@ jobs: strategy: matrix: python-version: ['3.10', '3.11', '3.12', '3.13'] - os: [ubuntu-24.04, macos-14, windows-2022] fail-fast: false - runs-on: ${{ matrix.os }} + runs-on: ubuntu-24.04 steps: - name: Checkout - uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 + uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2 with: path: zephyr fetch-depth: 0 - name: Set Up Python ${{ matrix.python-version }} - uses: actions/setup-python@e797f83bcb11b83ae66e0230d6156d7c80228e7c # v6.0.0 + uses: actions/setup-python@a309ff8b426b58ec0e2a45f0f869d46889d02405 # v6.2.0 with: python-version: ${{ matrix.python-version }} cache: pip cache-dependency-path: scripts/requirements-actions.txt - name: Setup Zephyr project - uses: zephyrproject-rtos/action-zephyr-setup@c125c5ebeeadbd727fa740b407f862734af1e52a # v1.0.9 + uses: zephyrproject-rtos/action-zephyr-setup@360ff9b36e58499d9eb28015cdcde7ca03a5b04d # v1.0.12 with: app-path: zephyr - toolchains: all + toolchains: 'arm-zephyr-eabi:riscv64-zephyr-elf:x86_64-zephyr-elf' enable-ccache: false west-group-filter: -tools,-bootloader,-babblesim,-hal west-project-filter: -nrf_hw_models,+cmsis,+hal_xtensa,+cmsis_6 - name: Run Pytest For Twister Black Box Tests - if: ${{ runner.os == 'Linux' }} working-directory: zephyr shell: bash env: diff --git a/.github/workflows/west_cmds.yml b/.github/workflows/west_cmds.yml index e94b3138fe94..3070fc69aa43 100644 --- a/.github/workflows/west_cmds.yml +++ b/.github/workflows/west_cmds.yml @@ -36,10 +36,10 @@ jobs: os: [ubuntu-22.04, macos-14, windows-2022] steps: - name: checkout - uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 + uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2 - name: Set up Python ${{ matrix.python-version }} - uses: actions/setup-python@e797f83bcb11b83ae66e0230d6156d7c80228e7c # v6.0.0 + uses: actions/setup-python@a309ff8b426b58ec0e2a45f0f869d46889d02405 # v6.2.0 with: python-version: ${{ matrix.python-version }} cache: pip diff --git a/.gitignore b/.gitignore index da37ed2a238e..5ca55745f066 100644 --- a/.gitignore +++ b/.gitignore @@ -17,6 +17,7 @@ build*/ !doc/build/ !scripts/build +!share/sysbuild/build !tests/drivers/build_all !scripts/pylib/build_helpers cscope.* diff --git a/.ruff-excludes.toml b/.ruff-excludes.toml index 05c5eb408ed2..fe33de1daa20 100644 --- a/.ruff-excludes.toml +++ b/.ruff-excludes.toml @@ -128,57 +128,14 @@ "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes ] -"./scripts/coredump/coredump_gdbserver.py" = [ - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports -] "./scripts/coredump/coredump_parser/elf_parser.py" = [ - "E501", # https://docs.astral.sh/ruff/rules/line-too-long - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports "SIM115", # https://docs.astral.sh/ruff/rules/open-file-with-context-handler - "UP031", # https://docs.astral.sh/ruff/rules/printf-string-formatting - "UP039", # https://docs.astral.sh/ruff/rules/unnecessary-class-parentheses ] "./scripts/coredump/coredump_parser/log_parser.py" = [ - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports "SIM115", # https://docs.astral.sh/ruff/rules/open-file-with-context-handler - "UP030", # https://docs.astral.sh/ruff/rules/format-literals - "UP031", # https://docs.astral.sh/ruff/rules/printf-string-formatting - "UP032", # https://docs.astral.sh/ruff/rules/f-string ] "./scripts/coredump/coredump_serial_log_parser.py" = [ - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports "SIM115", # https://docs.astral.sh/ruff/rules/open-file-with-context-handler - "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes -] -"./scripts/coredump/gdbstubs/arch/arm64.py" = [ - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports - "UP039", # https://docs.astral.sh/ruff/rules/unnecessary-class-parentheses -] -"./scripts/coredump/gdbstubs/arch/arm_cortex_m.py" = [ - "E501", # https://docs.astral.sh/ruff/rules/line-too-long - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports - "UP039", # https://docs.astral.sh/ruff/rules/unnecessary-class-parentheses -] -"./scripts/coredump/gdbstubs/arch/risc_v.py" = [ - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports - "UP039", # https://docs.astral.sh/ruff/rules/unnecessary-class-parentheses -] -"./scripts/coredump/gdbstubs/arch/x86.py" = [ - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports - "UP039", # https://docs.astral.sh/ruff/rules/unnecessary-class-parentheses -] -"./scripts/coredump/gdbstubs/arch/x86_64.py" = [ - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports - "UP039", # https://docs.astral.sh/ruff/rules/unnecessary-class-parentheses -] -"./scripts/coredump/gdbstubs/arch/xtensa.py" = [ - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports - "SIM113", # https://docs.astral.sh/ruff/rules/enumerate-for-loop - "UP031", # https://docs.astral.sh/ruff/rules/printf-string-formatting -] -"./scripts/coredump/gdbstubs/gdbstub.py" = [ - "E501", # https://docs.astral.sh/ruff/rules/line-too-long - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports ] "./scripts/dts/gen_defines.py" = [ "B007", # https://docs.astral.sh/ruff/rules/unused-loop-control-variable @@ -190,12 +147,6 @@ "UP035", # https://docs.astral.sh/ruff/rules/deprecated-import "UP045", # https://docs.astral.sh/ruff/rules/non-pep604-annotation-optional ] -"./scripts/dts/gen_driver_kconfig_dts.py" = [ - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports -] -"./scripts/dts/gen_dts_cmake.py" = [ - "SIM118", # https://docs.astral.sh/ruff/rules/in-dict-keys -] "./scripts/dts/python-devicetree/src/devicetree/_private.py" = [ "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports "UP035", # https://docs.astral.sh/ruff/rules/deprecated-import @@ -353,32 +304,14 @@ "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes ] -"./scripts/pylib/pytest-twister-harness/src/twister_harness/device/binary_adapter.py" = [ - "E501", # https://docs.astral.sh/ruff/rules/line-too-long - "SIM103", # https://docs.astral.sh/ruff/rules/needless-bool -] -"./scripts/pylib/pytest-twister-harness/src/twister_harness/device/device_adapter.py" = [ - "E501", # https://docs.astral.sh/ruff/rules/line-too-long - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports -] "./scripts/pylib/pytest-twister-harness/src/twister_harness/device/factory.py" = [ "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports "UP006", # https://docs.astral.sh/ruff/rules/non-pep585-annotation "UP035", # https://docs.astral.sh/ruff/rules/deprecated-import ] "./scripts/pylib/pytest-twister-harness/src/twister_harness/device/fifo_handler.py" = [ - "E501", # https://docs.astral.sh/ruff/rules/line-too-long "SIM115", # https://docs.astral.sh/ruff/rules/open-file-with-context-handler ] -"./scripts/pylib/pytest-twister-harness/src/twister_harness/device/hardware_adapter.py" = [ - "E501", # https://docs.astral.sh/ruff/rules/line-too-long - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports - "UP024", # https://docs.astral.sh/ruff/rules/os-error-alias -] -"./scripts/pylib/pytest-twister-harness/src/twister_harness/device/qemu_adapter.py" = [ - "E501", # https://docs.astral.sh/ruff/rules/line-too-long - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports -] "./scripts/pylib/pytest-twister-harness/src/twister_harness/fixtures.py" = [ "E501", # https://docs.astral.sh/ruff/rules/line-too-long "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports @@ -965,20 +898,7 @@ exclude = [ "./samples/subsys/zbus/remote_mock/remote_mock.py", "./scripts/check_maintainers.py", "./scripts/ci/upload_test_results_es.py", - "./scripts/coredump/coredump_gdbserver.py", - "./scripts/coredump/coredump_parser/elf_parser.py", - "./scripts/coredump/coredump_parser/log_parser.py", - "./scripts/coredump/coredump_serial_log_parser.py", - "./scripts/coredump/gdbstubs/arch/arm64.py", - "./scripts/coredump/gdbstubs/arch/arm_cortex_m.py", - "./scripts/coredump/gdbstubs/arch/risc_v.py", - "./scripts/coredump/gdbstubs/arch/x86.py", - "./scripts/coredump/gdbstubs/arch/x86_64.py", - "./scripts/coredump/gdbstubs/arch/xtensa.py", - "./scripts/coredump/gdbstubs/gdbstub.py", "./scripts/dts/gen_defines.py", - "./scripts/dts/gen_driver_kconfig_dts.py", - "./scripts/dts/gen_dts_cmake.py", "./scripts/dts/gen_edt.py", "./scripts/dts/python-devicetree/src/devicetree/_private.py", "./scripts/dts/python-devicetree/src/devicetree/dtlib.py", @@ -1010,11 +930,6 @@ exclude = [ "./scripts/net/enumerate_http_status.py", "./scripts/profiling/stackcollapse.py", "./scripts/pylib/build_helpers/domains.py", - "./scripts/pylib/pytest-twister-harness/src/twister_harness/device/binary_adapter.py", - "./scripts/pylib/pytest-twister-harness/src/twister_harness/device/device_adapter.py", - "./scripts/pylib/pytest-twister-harness/src/twister_harness/device/fifo_handler.py", - "./scripts/pylib/pytest-twister-harness/src/twister_harness/device/hardware_adapter.py", - "./scripts/pylib/pytest-twister-harness/src/twister_harness/device/qemu_adapter.py", "./scripts/pylib/pytest-twister-harness/src/twister_harness/fixtures.py", "./scripts/pylib/pytest-twister-harness/src/twister_harness/helpers/mcumgr.py", "./scripts/pylib/pytest-twister-harness/src/twister_harness/plugin.py", diff --git a/CMakeLists.txt b/CMakeLists.txt index 2e38f42de789..4936962d3998 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -166,7 +166,7 @@ if(CONFIG_COMPILER_WARNINGS_AS_ERRORS) zephyr_link_libraries($) endif() -if(CONFIG_DEPRECATION_TEST) +if(CONFIG_DEPRECATION_TEST OR NOT CONFIG_WARN_DEPRECATED) zephyr_compile_options($<$:$>) zephyr_compile_options($<$:$>) zephyr_compile_options($<$:$>) @@ -232,42 +232,6 @@ get_property(LINKER_OPTIMIZE_FOR_SPEED_FLAG TARGET linker PROPERTY optimization_ get_property(LINKER_OPTIMIZE_FOR_SIZE_FLAG TARGET linker PROPERTY optimization_size) get_property(LINKER_OPTIMIZE_FOR_SIZE_AGGRESSIVE_FLAG TARGET linker PROPERTY optimization_size_aggressive) -# Let the assembler inherit the optimization flags of the compiler if it is -# not set explicitly. -if(NOT ASM_OPTIMIZE_FOR_NO_OPTIMIZATIONS_FLAG) - set(ASM_OPTIMIZE_FOR_NO_OPTIMIZATIONS_FLAG ${COMPILER_OPTIMIZE_FOR_NO_OPTIMIZATIONS_FLAG}) -endif() -if(NOT ASM_OPTIMIZE_FOR_DEBUG_FLAG) - set(ASM_OPTIMIZE_FOR_DEBUG_FLAG ${COMPILER_OPTIMIZE_FOR_DEBUG_FLAG}) -endif() -if(NOT ASM_OPTIMIZE_FOR_SPEED_FLAG) - set(ASM_OPTIMIZE_FOR_SPEED_FLAG ${COMPILER_OPTIMIZE_FOR_SPEED_FLAG}) -endif() -if(NOT ASM_OPTIMIZE_FOR_SIZE_FLAG) - set(ASM_OPTIMIZE_FOR_SIZE_FLAG ${COMPILER_OPTIMIZE_FOR_SIZE_FLAG}) -endif() -if(NOT ASM_OPTIMIZE_FOR_SIZE_AGGRESSIVE_FLAG) - set(ASM_OPTIMIZE_FOR_SIZE_AGGRESSIVE_FLAG ${COMPILER_OPTIMIZE_FOR_SIZE_AGGRESSIVE_FLAG}) -endif() - -# Let the linker inherit the optimization flags of the compiler if it is -# not set explicitly. -if(NOT LINKER_OPTIMIZE_FOR_NO_OPTIMIZATIONS_FLAG) - set(LINKER_OPTIMIZE_FOR_NO_OPTIMIZATIONS_FLAG ${COMPILER_OPTIMIZE_FOR_NO_OPTIMIZATIONS_FLAG}) -endif() -if(NOT LINKER_OPTIMIZE_FOR_DEBUG_FLAG) - set(LINKER_OPTIMIZE_FOR_DEBUG_FLAG ${COMPILER_OPTIMIZE_FOR_DEBUG_FLAG}) -endif() -if(NOT LINKER_OPTIMIZE_FOR_SPEED_FLAG) - set(LINKER_OPTIMIZE_FOR_SPEED_FLAG ${COMPILER_OPTIMIZE_FOR_SPEED_FLAG}) -endif() -if(NOT LINKER_OPTIMIZE_FOR_SIZE_FLAG) - set(LINKER_OPTIMIZE_FOR_SIZE_FLAG ${COMPILER_OPTIMIZE_FOR_SIZE_FLAG}) -endif() -if(NOT LINKER_OPTIMIZE_FOR_SIZE_AGGRESSIVE_FLAG) - set(LINKER_OPTIMIZE_FOR_SIZE_AGGRESSIVE_FLAG ${COMPILER_OPTIMIZE_FOR_SIZE_AGGRESSIVE_FLAG}) -endif() - # From kconfig choice, pick the actual OPTIMIZATION_FLAG to use. # Kconfig choice ensures only one of these CONFIG_*_OPTIMIZATIONS is set. if(CONFIG_NO_OPTIMIZATIONS) @@ -315,7 +279,9 @@ if(CONFIG_LTO) zephyr_compile_options($) add_link_options($) else() - zephyr_compile_options($) + set(genex_tgt_lto "$") + set(genex_lto "$") + zephyr_compile_options("$<$,${genex_tgt_lto}>:${genex_lto}>") add_link_options($) endif() endif() @@ -473,8 +439,6 @@ zephyr_compile_options( $<$:-D_ASMLANGUAGE> ) -find_package(Deprecated COMPONENTS toolchain_ld_base) - if(DEFINED TOOLCHAIN_LD_FLAGS) zephyr_ld_options(${TOOLCHAIN_LD_FLAGS}) endif() @@ -505,8 +469,6 @@ toolchain_ld_force_undefined_symbols( ) if(NOT CONFIG_NATIVE_BUILD) - find_package(Deprecated COMPONENTS toolchain_ld_baremetal) - zephyr_link_libraries(PROPERTY baremetal) # Note that some architectures will skip this flag if set to error, even @@ -531,10 +493,6 @@ if(NOT CONFIG_NATIVE_BUILD) endif() if(CONFIG_CPP) - if(NOT CONFIG_MINIMAL_LIBCPP AND NOT CONFIG_NATIVE_LIBRARY) - find_package(Deprecated COMPONENTS toolchain_ld_cpp) - endif() - zephyr_link_libraries(PROPERTY cpp_base) endif() @@ -601,6 +559,14 @@ if(CONFIG_INSTRUMENTATION) endif() endif() +if(CONFIG_COMPILER_CODEGEN_VLIW_ENABLED) + zephyr_compile_options($<$:$>) + zephyr_compile_options($<$:$>) +elseif(CONFIG_COMPILER_CODEGEN_VLIW_DISABLED) + zephyr_compile_options($<$:$>) + zephyr_compile_options($<$:$>) +endif() + # Allow the user to inject options when calling cmake, e.g. # 'cmake -DEXTRA_CFLAGS="-Werror -Wno-deprecated-declarations" ..' include(cmake/extra_flags.cmake) @@ -826,12 +792,12 @@ set(struct_tags_json ${CMAKE_CURRENT_BINARY_DIR}/misc/generated/struct_tags.json # The syscalls subdirs txt file is constructed by python containing a list of folders to use for # dependency handling, including empty folders. # Windows: The list is used to specify DIRECTORY list with CMAKE_CONFIGURE_DEPENDS attribute. -# Other OS: The list will update whenever a file is added/removed/modified and ensure a re-build. +# Other OS: The list file is updated whenever a directory is added or removed. set(syscalls_subdirs_txt ${CMAKE_CURRENT_BINARY_DIR}/misc/generated/syscalls_subdirs.txt) -# As syscalls_subdirs_txt is updated whenever a file is modified, this file can not be used for -# monitoring of added / removed folders. A trigger file is thus used for correct dependency -# handling. The trigger file will update when a folder is added / removed. +# As syscalls_subdirs_txt is updated only on directory add or remove, this file can not be used for +# monitoring of syscall changes. A trigger file is thus used for correct dependency handling. The +# trigger file will update when syscalls change. set(syscalls_subdirs_trigger ${CMAKE_CURRENT_BINARY_DIR}/misc/generated/syscalls_subdirs.trigger) if(NOT (${CMAKE_HOST_SYSTEM_NAME} STREQUAL Windows)) @@ -850,14 +816,13 @@ execute_process( ) file(STRINGS ${syscalls_subdirs_txt} PARSE_SYSCALLS_PATHS_DEPENDS ENCODING UTF-8) +# Each header file must be monitored as file modifications are not reflected on directory level. +file(GLOB_RECURSE PARSE_SYSCALLS_HEADER_DEPENDS ${ZEPHYR_BASE}/include/*.h) + if(${CMAKE_HOST_SYSTEM_NAME} STREQUAL Windows) # On windows only adding/removing files or folders will be reflected in depends. # Hence adding a file requires CMake to re-run to add this file to the file list. set_property(DIRECTORY APPEND PROPERTY CMAKE_CONFIGURE_DEPENDS ${PARSE_SYSCALLS_PATHS_DEPENDS}) - - # Also On Windows each header file must be monitored as file modifications are not reflected - # on directory level. - file(GLOB_RECURSE PARSE_SYSCALLS_HEADER_DEPENDS ${ZEPHYR_BASE}/include/*.h) else() # The syscall parsing depends on the folders in order to detect add/removed/modified files. # When a folder is removed, CMake will try to find a target that creates that dependency. @@ -888,10 +853,10 @@ else() file(WRITE ${syscalls_subdirs_txt} "") endif() - # On other OS'es, modifying a file is reflected on the folder timestamp and hence detected + # On other OS'es, using git checkout is reflected on the folder timestamp and hence detected # when using depend on directory level. # Thus CMake only needs to re-run when sub-directories are added / removed, which is indicated - # using a trigger file. + # by syscalls_subdirs_txt being updated. set_property(DIRECTORY APPEND PROPERTY CMAKE_CONFIGURE_DEPENDS ${syscalls_subdirs_txt}) endif() @@ -2144,17 +2109,29 @@ if(CONFIG_BUILD_OUTPUT_INFO_HEADER) ) endif() -if(CONFIG_LLEXT AND CONFIG_LLEXT_EXPORT_BUILTINS_BY_SLID) - #slidgen must be the first post-build command to be executed - #on the Zephyr ELF to ensure that all other commands, such as - #binary file generation, are operating on a preparated ELF. - list(PREPEND +if(CONFIG_LLEXT) + # Add discarded groups inspector to post-build commands + list(APPEND post_build_commands COMMAND ${PYTHON_EXECUTABLE} - ${ZEPHYR_BASE}/scripts/build/llext_prepare_exptab.py + ${ZEPHYR_BASE}/scripts/build/llext_inspect_discarded_groups.py --elf-file ${PROJECT_BINARY_DIR}/${KERNEL_ELF_NAME} - --slid-listing ${PROJECT_BINARY_DIR}/slid_listing.txt + --dotconfig-file ${DOTCONFIG} + --output-report ${PROJECT_BINARY_DIR}/llext_discarded_groups.txt ) + + if(CONFIG_LLEXT_EXPORT_BUILTINS_BY_SLID) + #slidgen must be the first post-build command to be executed + #on the Zephyr ELF to ensure that all other commands, such as + #binary file generation, are operating on a preparated ELF. + list(PREPEND + post_build_commands + COMMAND ${PYTHON_EXECUTABLE} + ${ZEPHYR_BASE}/scripts/build/llext_prepare_exptab.py + --elf-file ${PROJECT_BINARY_DIR}/${KERNEL_ELF_NAME} + --slid-listing ${PROJECT_BINARY_DIR}/slid_listing.txt + ) + endif() endif() if(NOT CMAKE_C_COMPILER_ID STREQUAL "ARMClang") @@ -2294,7 +2271,7 @@ endif() add_custom_command( TARGET ${logical_target_for_zephyr_elf} POST_BUILD - COMMAND ${CMAKE_COMMAND} -E echo "Generating files from ${PROJECT_BINARY_DIR}/${KERNEL_ELF_NAME} for board: ${BOARD}" + COMMAND ${CMAKE_COMMAND} -E echo "Generating files from ${PROJECT_BINARY_DIR}/${KERNEL_ELF_NAME} for board: ${BOARD}/${BOARD_QUALIFIERS}" ${post_build_commands} BYPRODUCTS ${post_build_byproducts} diff --git a/CODE_OF_CONDUCT.md b/CODE_OF_CONDUCT.md index f81c519c7831..1bd59a4aa177 100644 --- a/CODE_OF_CONDUCT.md +++ b/CODE_OF_CONDUCT.md @@ -1,4 +1,4 @@ -# Contributor Covenant Code of Conduct +# Zephyr Project Code of Conduct ## Our Pledge diff --git a/Kconfig.zephyr b/Kconfig.zephyr index fdf3a84087db..2682438f3393 100644 --- a/Kconfig.zephyr +++ b/Kconfig.zephyr @@ -9,6 +9,10 @@ source "Kconfig.constants" osource "$(APPLICATION_SOURCE_DIR)/VERSION" +# This should be sourced early since the autogen Kconfig.dts options +# and macros may get used by shields/boards/SoC defconfig or modules. +source "dts/Kconfig" + # Include Kconfig.defconfig files first so that they can override defaults and # other symbol/choice properties by adding extra symbol/choice definitions. # After merging all definitions for a symbol/choice, Kconfig picks the first @@ -33,10 +37,6 @@ osource "$(TOOLCHAIN_KCONFIG_DIR)/Kconfig.defconfig" # This loads the testsuite defconfig source "subsys/testsuite/Kconfig.defconfig" -# This should be early since the autogen Kconfig.dts symbols may get -# used by modules -source "dts/Kconfig" - menu "Modules" source "modules/Kconfig" @@ -98,11 +98,30 @@ config USE_DT_CODE_PARTITION # Workaround for not being able to have commas in macro arguments DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition +DT_CHOSEN_Z_FLASH := zephyr,flash + +config FLASH_CODE_PARTITION_ADDRESS_INVALID + bool + default y if XIP && $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) < FLASH_BASE_ADDRESS + select DEPRECATED + help + If this item is selected, it is likely selected because your board/SoC/base DTS files + are wrong and have a flash memory that does not start at absolute address 0x0 and: + * Do not have a ``ranges <>;`` property in the flash node passing down the address + and size to child nodes + * Do not have a ``ranges;`` property in the partitions node passing down the previous + ranges to child nodes + + Support for this will be removed and required that your files be updated correctly for + a future release, check the Zephyr 4.4 migration notes. config FLASH_LOAD_OFFSET # Only user-configurable when USE_DT_CODE_PARTITION is disabled hex "Kernel load offset" if !USE_DT_CODE_PARTITION - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) if USE_DT_CODE_PARTITION + default $(sub_hex, $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)), \ + $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))) if USE_DT_CODE_PARTITION && \ + !FLASH_CODE_PARTITION_ADDRESS_INVALID + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) if USE_DT_CODE_PARTITION default 0 help This option specifies the byte offset from the beginning of flash that @@ -629,6 +648,37 @@ config TOOLCHAIN_SUPPORTS_VLA_IN_STATEMENTS Hidden symbol to state if the toolchain can handle vla in statements. +menu "Code Generation" + +choice COMPILER_CODEGEN_VLIW + prompt "VLIW (Very Long Instruction Word)" + default COMPILER_CODEGEN_VLIW_AUTO + help + This option instructs the compiler whether to use VLIW + (Very Long Instruction Word) instructions. VLIW allows + the compiler to fuse instructions for parallel execution. + +config COMPILER_CODEGEN_VLIW_AUTO + bool "Auto" + help + Let the compiler decide whether to generate VLIW instructions. + + This usually means using the compiler defaults. + +config COMPILER_CODEGEN_VLIW_ENABLED + bool "Generate VLIW" + help + Explicitly instructs the compiler to generate VLIW instructions if possible. + +config COMPILER_CODEGEN_VLIW_DISABLED + bool "DO NOT generate VLIW" + help + Explicitly instructs the compiler to NEVER generate VLIW instructions. + +endchoice # COMPILER_CODEGEN_VLIW + +endmenu # Code Generation + endmenu choice @@ -1021,7 +1071,8 @@ config WARN_DEPRECATED prompt "Warn on deprecated usage" help Print a warning when the Kconfig tree is parsed if any deprecated - features are enabled. + features are enabled, or at compile time, when deprecated macros or + symbols are used. config EXPERIMENTAL bool @@ -1071,8 +1122,6 @@ menu "Boot Options" config IS_BOOTLOADER bool "Act as a bootloader" - depends on XIP - depends on ARM help This option indicates that Zephyr will act as a bootloader to execute a separate Zephyr image payload. diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index d3a54df7b78d..e6f4296ab784 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -302,7 +302,7 @@ Aesc Platform: files-regex: - ^drivers/.*aesc(\.c)?$ labels: - - "area: Aesc Silicon Platform" + - "platform: Aesc Silicon" Ambiq Platforms: status: maintained @@ -436,6 +436,20 @@ Binary Descriptors: tests: - bindesc +Biometrics Drivers: + status: maintained + maintainers: + - heronet + files: + - drivers/biometrics/ + - dts/bindings/biometrics/ + - include/zephyr/drivers/biometrics.h + - samples/drivers/biometrics/ + - tests/drivers/biometrics/ + - doc/hardware/peripherals/biometrics.rst + labels: + - "area: Biometrics" + Bluetooth Audio: status: maintained maintainers: @@ -486,7 +500,8 @@ Bluetooth Classic: - makeshi - chengkai15 files: - - doc/connectivity/bluetooth/shell/classic/a2dp.rst + - doc/connectivity/bluetooth/shell/classic/ + - doc/connectivity/bluetooth/api/classic/ - subsys/bluetooth/common/ - subsys/bluetooth/host/classic/ - include/zephyr/bluetooth/classic/ @@ -584,13 +599,15 @@ Bluetooth Host: - include/zephyr/bluetooth/iso.h - include/zephyr/bluetooth/controller.h - include/zephyr/bluetooth/mesh.h + - include/zephyr/bluetooth/sbc.h - doc/connectivity/bluetooth/bluetooth-ctlr-arch.rst - doc/connectivity/bluetooth/autopts/ - doc/connectivity/bluetooth/img/ctlr* - doc/connectivity/bluetooth/api/audio/ + - doc/connectivity/bluetooth/api/classic/ - doc/connectivity/bluetooth/api/mesh/ - doc/connectivity/bluetooth/api/controller.rst - - doc/connectivity/bluetooth/shell/classic/a2dp.rst + - doc/connectivity/bluetooth/shell/classic/ - doc/connectivity/bluetooth/shell/host/iso.rst - doc/connectivity/bluetooth/shell/audio/ - samples/bluetooth/bap*/ @@ -606,6 +623,7 @@ Bluetooth Host: - subsys/bluetooth/host/iso.c - subsys/bluetooth/host/iso_internal.h - subsys/bluetooth/host/shell/iso.c + - subsys/bluetooth/lib/sbc.c - tests/bluetooth/audio/ - tests/bluetooth/classic/ - tests/bluetooth/controller/ @@ -738,6 +756,7 @@ Bouffalolab Platforms: - josuah files: - boards/bflb/ + - boards/sipeed/maix_m0s_dock/ - drivers/*/*bflb* - dts/riscv/bflb/ - dts/bindings/*/bflb,* @@ -1135,6 +1154,8 @@ Devicetree: Devicetree Bindings: status: odd fixes + collaborators: + - JarmouniA files-regex: - ^dts/bindings/.*zephyr.* files: @@ -1142,7 +1163,7 @@ Devicetree Bindings: - include/zephyr/dt-bindings/ - scripts/bindings_properties_allowlist.yaml labels: - - "area: Devicetree Bindings" + - "area: Devicetree Binding" Disk: status: maintained @@ -1174,9 +1195,10 @@ Display drivers: maintainers: - JarmouniA collaborators: - - jfischer-no - danieldegrasse - VynDragon + - KATE-WANG-NXP + - avolmat-st files: - drivers/display/ - dts/bindings/display/ @@ -1217,6 +1239,7 @@ Documentation: - doc/substitutions.txt - doc/images/Zephyr-Kite-in-tree.png - doc/index-tex.rst + - doc/index.html - doc/index.rst - doc/kconfig.rst - doc/templates/sample.tmpl @@ -1253,6 +1276,7 @@ Documentation Infrastructure: status: odd fixes collaborators: - anangl + - ZhaoxiangJin files: - drivers/adc/ - include/zephyr/drivers/adc.h @@ -1312,9 +1336,13 @@ Documentation Infrastructure: - alexanderwachter - martinjaeger - str4t0m + - william-tang914 files: - boards/shields/canis_canpico/ - boards/shields/mcp2515/ + - boards/shields/mikroe_can_fd_6_click/ + - boards/shields/mikroe_mcp251x_click/ + - boards/shields/mikroe_mcp251xfd_click/ - boards/shields/tcan4550evm/ - doc/connectivity/canbus/ - doc/hardware/peripherals/can/ @@ -1446,6 +1474,9 @@ Documentation Infrastructure: status: maintained maintainers: - nordic-krch + collaborators: + - Holt-Sun + - FelixWang47831 files: - drivers/counter/ - include/zephyr/drivers/counter.h @@ -1505,6 +1536,7 @@ Documentation Infrastructure: - lgirdwood - iuliana-prodan - dbaluta + - abonislawski files: - drivers/dai/ - doc/hardware/peripherals/audio/dai.rst @@ -1561,6 +1593,8 @@ Documentation Infrastructure: status: maintained maintainers: - finikorg + collaborators: + - yvesll files: - drivers/edac/ - dts/bindings/edac/ @@ -1598,7 +1632,11 @@ Documentation Infrastructure: - albertofloyd collaborators: - VenkatKotakonda - - jvasanth1 + - AdiIntel + - scottwcpg + - Dino-Li + - ChiHuaL + - JhanBoChao-Realtek files: - drivers/espi/ - include/zephyr/drivers/espi.h @@ -1825,6 +1863,8 @@ Documentation Infrastructure: status: maintained maintainers: - teburd + collaborators: + - maass-hamburg files: - drivers/i2c/ - include/zephyr/drivers/i2c/ @@ -1842,11 +1882,10 @@ Documentation Infrastructure: - drivers.i2c "Drivers: I2S": - status: maintained - maintainers: - - anangl + status: odd fixes collaborators: - TomasBarakNXP + - anangl files: - doc/hardware/peripherals/audio/i2s.rst - drivers/i2s/ @@ -2010,6 +2049,7 @@ Documentation Infrastructure: collaborators: - JarmouniA - VynDragon + - KATE-WANG-NXP files: - drivers/mipi_dbi/ - include/zephyr/drivers/mipi_dbi.h @@ -2022,6 +2062,7 @@ Documentation Infrastructure: status: odd fixes collaborators: - JarmouniA + - KATE-WANG-NXP files: - drivers/mipi_dsi/ - include/zephyr/drivers/mipi_dsi.h @@ -2186,8 +2227,6 @@ Documentation Infrastructure: maintainers: - manuargue - Dat-NguyenDuy - collaborators: - - congnguyenhuu files: - drivers/psi5/ - include/zephyr/drivers/psi5/ @@ -2215,6 +2254,7 @@ Documentation Infrastructure: collaborators: - anangl - henrikbrixandersen + - FelixWang47831 files: - drivers/pwm/ - dts/bindings/pwm/ @@ -2252,6 +2292,8 @@ Documentation Infrastructure: status: maintained maintainers: - bjarki-andreasen + collaborators: + - Holt-Sun files: - drivers/rtc/ - include/zephyr/drivers/rtc/ @@ -2335,8 +2377,6 @@ Documentation Infrastructure: maintainers: - manuargue - Dat-NguyenDuy - collaborators: - - congnguyenhuu files: - drivers/sent/ - include/zephyr/drivers/sent/ @@ -2450,7 +2490,7 @@ Documentation Infrastructure: - include/zephyr/drivers/stepper/ - include/zephyr/drivers/stepper.h - dts/bindings/stepper/ - - doc/hardware/peripherals/stepper.rst + - doc/hardware/peripherals/stepper/ - samples/drivers/stepper/ - tests/drivers/build_all/stepper/ - tests/drivers/stepper/ @@ -2575,6 +2615,7 @@ Documentation Infrastructure: collaborators: - katsuster - martinjaeger + - yvesll files: - doc/hardware/peripherals/watchdog.rst - drivers/watchdog/ @@ -2623,6 +2664,7 @@ Documentation Infrastructure: - dts/bindings/wifi/nordic,nrf7000-spi.yaml - dts/bindings/wifi/nordic,nrf7001-qspi.yaml - dts/bindings/wifi/nordic,nrf7001-spi.yaml + - dts/bindings/wifi/nordic,nrf71-wifi.yaml - boards/shields/nrf7002ek/ labels: - "area: Wi-Fi" @@ -2753,6 +2795,7 @@ Filesystems: collaborators: - Laczen - nashif + - rghaddab files: - include/zephyr/fs/ - samples/subsys/fs/ @@ -3042,6 +3085,7 @@ Intel Platforms (Xtensa): - jxstelter - marcinszkudlinski - nashif + - abonislawski files: - boards/intel/adsp/ - soc/intel/intel_adsp/ @@ -3147,6 +3191,7 @@ Kernel: collaborators: - lyakh - pillo79 + - laurenmurphyx64 files: - cmake/llext-edk.cmake - samples/subsys/llext/ @@ -3365,6 +3410,7 @@ Microchip MEC Platforms: status: maintained maintainers: - jvasanth1 + - scottwcpg collaborators: - VenkatKotakonda - albertofloyd @@ -3385,13 +3431,17 @@ Microchip RISC-V Platforms: status: maintained maintainers: - fkokosinski + collaborators: - kgugala - tgorochowik + - con-pax files: - boards/microchip/m2gl025_miv/ - boards/microchip/mpfs_icicle/ + - boards/microchip/pic64gx_curiosity_kit/ - dts/riscv/microchip/ - soc/microchip/miv/ + - soc/microchip/pic64/ labels: - "platform: Microchip RISC-V" @@ -3489,6 +3539,7 @@ NXP Platform Drivers: - dbaluta - Holt-Sun - zejiang0jason + - butok files-regex: - ^drivers/.*nxp.* - ^drivers/.*mcux.* @@ -3587,6 +3638,7 @@ NXP Platforms (MCU): - mmahadevan108 collaborators: - butok + - DerekSnell files: - boards/nxp/mimxrt*/ - boards/nxp/frdm*/ @@ -3594,7 +3646,6 @@ NXP Platforms (MCU): - boards/nxp/lpcxpress*/ - boards/nxp/twr_*/ - boards/nxp/*rw*/ - - boards/nxp/hexiwear/ - boards/nxp/common/ - boards/nxp/* - soc/nxp/common/ @@ -3609,7 +3660,7 @@ NXP Platforms (MCU): - boards/nxp/rddrone_fmuk66/ - tests/boards/vmu_rt1170/ files-exclude: - - dts/arm/nxp/nxp_imx* + - dts/arm/nxp/imx/nxp_imx* - boards/nxp/frdm_imx*/ files-regex-exclude: - .*s32.* @@ -3638,14 +3689,14 @@ NXP Platforms (MCU): files: - boards/nxp/frdm_k*/ - soc/nxp/kinetis/ - - dts/arm/nxp/nxp_k* + - dts/arm/nxp/kinetis/nxp_k* - name: NXP LPC collaborators: - mmahadevan108 files: - boards/nxp/lpc*/ - soc/nxp/lpc/ - - dts/arm/nxp/nxp_lpc* + - dts/arm/nxp/lpc/nxp_lpc* - name: NXP MCU Xtensa collaborators: - iuliana-prodan @@ -3675,6 +3726,13 @@ NXP Platforms (MCU): - boards/nxp/vmu*/ - boards/nxp/rddrone_fmuk66/ - tests/boards/vmu_rt1170/ + - name: NXP MCU k32l + collaborators: + - iia + files: + - boards/nxp/frdm_k32l2b3/ + - dts/arm/nxp/kinetis/nxp_k32l2b3.dtsi + - soc/nxp/kinetis/k32lx/ labels: - "platform: NXP MCU" - "platform: NXP" @@ -3693,7 +3751,7 @@ NXP Platforms (MPU): - drivers/*/*imx* - include/zephyr/dt-bindings/rdc/ - dts/arm64/nxp/ - - dts/arm/nxp/nxp_imx* + - dts/arm/nxp/imx/nxp_imx* - soc/nxp/imx/ - soc/nxp/layerscape/ - boards/nxp/ls1046ardb/ @@ -3710,7 +3768,6 @@ NXP Platforms (S32): - manuargue collaborators: - Dat-NguyenDuy - - congnguyenhuu files: - boards/nxp/*s32*/ - boards/common/*nxp_s32* @@ -3718,7 +3775,7 @@ NXP Platforms (S32): - drivers/*/*nxp_s32* - drivers/misc/*nxp_s32*/ - dts/bindings/*/nxp,s32* - - dts/arm/nxp/*s32* + - dts/arm/nxp/s32/nxp_s32* - samples/boards/nxp/s32/ - include/zephyr/dt-bindings/*/nxp-s32* - include/zephyr/dt-bindings/*/nxp_s32* @@ -4124,11 +4181,12 @@ Nuvoton Numicro Numaker Platforms: - cyliangtw collaborators: - ssekar15 + - ccli8 files: - soc/nuvoton/numaker/ - soc/nuvoton/numicro/ - boards/nuvoton/numaker*/ - - dts/arm/nuvoton/ + - dts/arm/nuvoton/m* - dts/bindings/*/*numicro* - dts/bindings/*/*numaker* - drivers/*/*_numicro* @@ -4151,6 +4209,22 @@ OSDP: tests: - sample.mgmt.osdp +OTP: + status: odd fixes + collaborators: + - GseoC + - pdgendt + files: + - doc/hardware/peripherals/otp/ + - drivers/otp/ + - dts/bindings/otp/ + - include/zephyr/drivers/otp.h + - tests/subsys/nvmem/api/otp.overlay + labels: + - "area: OTP" + tests: + - nvmem + Octavo Systems Platforms: status: maintained maintainers: @@ -4215,6 +4289,7 @@ PMCI: collaborators: - nashif - kehintel + - edersondisouza files: - subsys/pmci/ - samples/subsys/pmci/ @@ -4284,6 +4359,16 @@ Power management: tests: - pm +QNX Hypervisor Platforms: + status: maintained + maintainers: + - soburi + files: + - boards/blackberry/qnxhv_vm/ + - soc/blackberry/qnxhv_vm/ + labels: + - "platform: QNX Hypervisor" + "Quicklogic Platform": status: odd fixes files: @@ -4382,7 +4467,6 @@ Raspberry Pi Pico Platforms: maintainers: - soburi collaborators: - - yonsch - threeeights - ajf58 files: @@ -4393,10 +4477,12 @@ Raspberry Pi Pico Platforms: - boards/pimoroni/pico_plus2/ - boards/seeed/xiao_rp2040/ - boards/sparkfun/pro_micro_rp2040/ + - boards/sparkfun/rp2040_mikrobus/ - boards/waveshare/rp2040_zero/ - boards/wiznet/w5500_evb_pico*/ - dts/arm/raspberrypi/rpi_pico/ - dts/bindings/*/raspberrypi,pico* + - dts/riscv/raspberrypi/ - drivers/*/*rpi_pico - drivers/*/*rpi_pico*/ - drivers/*/*rpi_pico*.c @@ -4404,6 +4490,20 @@ Raspberry Pi Pico Platforms: labels: - "platform: Raspberry Pi Pico" +Realtek Ameba Platforms: + status: maintained + maintainers: + - zjian-zhang + - Derek-RTK + files: + - drivers/*/*ameba* + - boards/realtek/ + - soc/realtek/ameba/ + - dts/arm/realtek/ameba*/ + - dts/bindings/*/*ameba* + labels: + - "platform: Ameba" + Realtek EC Platforms: status: maintained maintainers: @@ -4441,6 +4541,9 @@ Release: Release Notes: status: maintained maintainers: + - MaureenHelm + - stephanosio + collaborators: - kartben files: - doc/releases/migration-guide-* @@ -4657,6 +4760,8 @@ Safety: maintainers: - tobiaskaestner - parphane + collaborators: + - jkey-eng files: - doc/safety/ labels: @@ -4747,6 +4852,24 @@ Settings: - samples/subsys/settings/ - doc/services/storage/settings/ - tests/subsys/settings_commit_prio/ + file-groups: + - name: TF-M PSA backend + collaborators: + - dsseng + - seankyer + - tomi-font + files: + - subsys/settings/src/settings_tfm_psa* + - tests/subsys/settings/functional/tfm_psa/ + - tests/subsys/settings/tfm_psa/ + - name: ZMS backend + collaborators: + - rghaddab + files: + - subsys/settings/src/settings_zms.c + - subsys/settings/include/settings/settings_zms.h + - tests/subsys/settings/zms/ + - tests/subsys/settings/functional/zms/ labels: - "area: Settings" tests: @@ -4793,6 +4916,7 @@ SiFli SF32LB Platforms: collaborators: - cameled - ck-telecom + - HalfSweet files: - boards/sifli/ - drivers/*/*sf32lb* @@ -4850,6 +4974,17 @@ Silabs SiM3U Platforms: description: >- SiM3U SoCs, dts files, and related drivers. Boards based on SiM3U SoCs. +Space Cubics Platforms: + status: maintained + maintainers: + - yashi + files: + - boards/sc/ + labels: + - "platform: Space Cubics" + description: >- + Space Cubics on-board computers (OBCs). + State machine framework: status: maintained maintainers: @@ -5174,6 +5309,7 @@ Twister: - gchwier - LukaszMrugala - KamilxPaszkiet + - fundakol files: - scripts/twister - scripts/schemas/twister/ @@ -5220,7 +5356,6 @@ USB-C: status: maintained maintainers: - sambhurst - collaborators: - keith-zephyr files: - drivers/usb_c/ @@ -5238,6 +5373,20 @@ USB-C: tests: - sample.usbc +UUID: + status: maintained + maintainers: + - sorru94 + files: + - lib/uuid/ + - include/zephyr/sys/uuid.h + - tests/lib/uuid/ + - samples/subsys/uuid/ + labels: + - "area: UUID" + tests: + - libraries.uuid + Userspace: status: maintained maintainers: @@ -5318,11 +5467,10 @@ VFS: - filesystem WCH Platforms: - status: maintained - maintainers: + status: odd fixes + collaborators: - nzmichaelh - kholia - collaborators: - VynDragon files: - boards/wch/ @@ -5625,6 +5773,7 @@ West: collaborators: - ithinuel - ccli8 + - johan-alfven-arm files: - drivers/misc/ethos_u/ - modules/hal_ethos_u/ @@ -5644,6 +5793,7 @@ West: status: maintained maintainers: - sreeramIfx + - teburd collaborators: - parthitce - talih0 @@ -5689,10 +5839,9 @@ West: maintainers: - anangl - nika-nordic - - masz-nordic + - nordic-krch - carlescufi collaborators: - - nordic-krch - kl-cruz - magp-nordic - jaz1-nordic @@ -5753,6 +5902,15 @@ West: labels: - "platform: Quicklogic" +"West project: hal_realtek": + status: maintained + maintainers: + - zjian-zhang + - Derek-RTK + files: [] + labels: + - "platform: Ameba" + "West project: hal_renesas": status: maintained maintainers: @@ -5777,7 +5935,6 @@ West: maintainers: - soburi collaborators: - - yonsch - threeeights - ajf58 files: @@ -5931,6 +6088,7 @@ West: collaborators: - nashif - dkalowsk + - edersondisouza files: [] labels: - "area: MCTP" @@ -5951,6 +6109,8 @@ West: - MarkWangChinese files: - modules/libsbc/ + - include/zephyr/bluetooth/sbc.h + - subsys/bluetooth/lib/sbc.c labels: - "area: Audio" @@ -6111,7 +6271,6 @@ West: status: maintained maintainers: - eriktamlin - - aronlander-pe files: - modules/percepio/ labels: @@ -6290,6 +6449,7 @@ Xilinx Platforms: - henrikbrixandersen - ibirnbaum - kedareswararao + - neeliajay files: - boards/amd/ - drivers/*/*xilinx* @@ -6380,7 +6540,7 @@ nRF IronSide SE Platforms: - karstenkoenig - SebastianBoe files: - - soc/nordic/ironside/ + - modules/hal_nordic/ironside/ - soc/nordic/common/uicr/ labels: - "platform: nRF IronSide SE" @@ -6389,7 +6549,7 @@ nRF Platforms: status: maintained maintainers: - anangl - - masz-nordic + - nordic-krch - bjarki-andreasen collaborators: - jaz1-nordic diff --git a/REUSE.toml b/REUSE.toml index 6ff874b060d8..83f6d8fed7dd 100644 --- a/REUSE.toml +++ b/REUSE.toml @@ -1,6 +1,6 @@ version = 1 -# Declare default license and copyright text for files that typically do not include them. +# Declare default license and copyright text for files that typically do not or cannot include them. [[annotations]] path = [ # zephyr-keep-sorted-start @@ -9,6 +9,7 @@ path = [ "**/*.conf", "**/*.ecl", "**/*.html", + "**/*.json", "**/*.rst", "**/*.yaml", "**/*.yml", diff --git a/arch/Kconfig b/arch/Kconfig index 9a08a29cf38e..e14c24119c85 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -122,6 +122,7 @@ config RISCV select ARCH_HAS_DIRECTED_IPIS select BARRIER_OPERATIONS_BUILTIN select ARCH_HAS_THREAD_PRIV_STACK_SPACE_GET if USERSPACE + depends on DT_HAS_RISCV_ENABLED help RISCV architecture diff --git a/arch/arc/core/smp.c b/arch/arc/core/smp.c index bd317d2d9977..7bb3cee2bae5 100644 --- a/arch/arc/core/smp.c +++ b/arch/arc/core/smp.c @@ -117,9 +117,7 @@ void arch_secondary_cpu_init(int cpu_num) irq_enable(DT_IRQN(DT_NODELABEL(ici))); #endif -#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK soc_per_core_init_hook(); -#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */ /* call the function set by arch_cpu_start */ fn = arc_cpu_init[cpu_num].fn; diff --git a/arch/arc/core/thread.c b/arch/arc/core/thread.c index 387f983780b9..38aee4912027 100644 --- a/arch/arc/core/thread.c +++ b/arch/arc/core/thread.c @@ -318,7 +318,7 @@ void arc_dsp_disable(struct k_thread *thread, unsigned int options) k_spinlock_key_t key = k_spin_lock(&lock); /* Disable DSP or AGU capabilities for the thread */ - thread->base.user_options &= ~(uint8_t)options; + thread->base.user_options &= ~(uint16_t)options; k_spin_unlock(&lock, key); } @@ -329,7 +329,7 @@ void arc_dsp_enable(struct k_thread *thread, unsigned int options) k_spinlock_key_t key = k_spin_lock(&lock); /* Enable dsp or agu capabilities for the thread */ - thread->base.user_options |= (uint8_t)options; + thread->base.user_options |= (uint16_t)options; k_spin_unlock(&lock, key); } diff --git a/arch/arc/include/kernel_arch_func.h b/arch/arc/include/kernel_arch_func.h index 73bd352a2498..37a893605600 100644 --- a/arch/arc/include/kernel_arch_func.h +++ b/arch/arc/include/kernel_arch_func.h @@ -36,9 +36,7 @@ static ALWAYS_INLINE void arch_kernel_init(void) { z_irq_setup(); -#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK soc_per_core_init_hook(); -#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */ } diff --git a/arch/arc/include/v2/irq.h b/arch/arc/include/v2/irq.h index f24ac01315a5..df14ece1e54b 100644 --- a/arch/arc/include/v2/irq.h +++ b/arch/arc/include/v2/irq.h @@ -68,7 +68,7 @@ static ALWAYS_INLINE void z_irq_setup(void) #ifdef CONFIG_ARC_NORMAL_FIRMWARE /* normal mode cannot write irq_ctrl, ignore it */ - aux_irq_ctrl_value = aux_irq_ctrl_value; + ARG_UNUSED(aux_irq_ctrl_value); #else z_arc_v2_aux_reg_write(_ARC_V2_AUX_IRQ_CTRL, aux_irq_ctrl_value); #endif diff --git a/arch/arm/core/cortex_a_r/Kconfig b/arch/arm/core/cortex_a_r/Kconfig index e6fac222f614..8b28370b0e25 100644 --- a/arch/arm/core/cortex_a_r/Kconfig +++ b/arch/arm/core/cortex_a_r/Kconfig @@ -3,6 +3,7 @@ # Copyright (c) 2018 Marvell # Copyright (c) 2018 Lexmark International, Inc. # Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG +# Copyright (c) 2025 Siemens Mobility GmbH # # SPDX-License-Identifier: Apache-2.0 @@ -238,5 +239,15 @@ config ICACHE_LINE_SIZE endif # CPU_AARCH32_CORTEX_R +config CPU_USE_ONLY_ONE_CORE + bool "Only run code on one CPU core" + default n + help + Put every CPU that doesn't have the value 0 in the Multiprocessor Affinity + Register for the Affinity Level 0 bits into an endless loop. This is + useful, if a bootloader is used that boots multiple cores in a SMP + configuration on a SoC and there are problems with using SMP inside + Zephyr. In consequence only one CPU core will execute the code. + config TEST_EXTRA_STACK_SIZE default 1024 if SMP diff --git a/arch/arm/core/cortex_a_r/cache.c b/arch/arm/core/cortex_a_r/cache.c index eb0b2c39e680..b6cb6b4222c0 100644 --- a/arch/arm/core/cortex_a_r/cache.c +++ b/arch/arm/core/cortex_a_r/cache.c @@ -40,7 +40,7 @@ size_t arch_dcache_line_size_get(void) val = read_sysreg(ctr); dminline = (val >> CTR_DMINLINE_SHIFT) & CTR_DMINLINE_MASK; /* Log2 of the number of words */ - dcache_line_size = 2 << dminline; + dcache_line_size = 4 << dminline; } return dcache_line_size; diff --git a/arch/arm/core/cortex_a_r/reset.S b/arch/arm/core/cortex_a_r/reset.S index 1a58d76d3c77..66cea9b08fb3 100644 --- a/arch/arm/core/cortex_a_r/reset.S +++ b/arch/arm/core/cortex_a_r/reset.S @@ -2,6 +2,7 @@ * Copyright (c) 2013-2014 Wind River Systems, Inc. * Copyright (c) 2019 Stephanos Ioannidis * Copyright 2024 Arm Limited and/or its affiliates + * Copyright (c) 2025 Siemens Mobility GmbH * * SPDX-License-Identifier: Apache-2.0 */ @@ -49,6 +50,21 @@ GTEXT(soc_reset_hook) */ SECTION_SUBSEC_FUNC(TEXT, _reset_section, z_arm_reset) SECTION_SUBSEC_FUNC(TEXT, _reset_section, __start) + +#if defined(CONFIG_CPU_USE_ONLY_ONE_CORE) + /* Load multiprocessor affinity and isolate last 8 bit */ + mrc p15, 0, r0, c0, c0, 5 + and r0, #0xff + cmp r0, #0 + beq _continue_boot + + _not_main_cpu_boot_loop: + wfi + b _not_main_cpu_boot_loop + + _continue_boot: +#endif + #if defined(CONFIG_AARCH32_ARMV8_R) /* Check if we are starting in HYP mode */ mrs r0, cpsr diff --git a/arch/arm/core/cortex_a_r/smp.c b/arch/arm/core/cortex_a_r/smp.c index d0e31acb1ed8..fd8790e337b2 100644 --- a/arch/arm/core/cortex_a_r/smp.c +++ b/arch/arm/core/cortex_a_r/smp.c @@ -98,18 +98,18 @@ void arch_cpu_start(int cpu_num, k_thread_stack_t *stack, int sz, arch_cpustart_ { int cpu_count, i, j; uint32_t cpu_mpid = 0; - uint32_t master_core_mpid; + uint32_t primary_core_mpid; - /* Now it is on master core */ + /* Now it is on primary core */ __ASSERT(arch_curr_cpu()->id == 0, ""); - master_core_mpid = MPIDR_TO_CORE(GET_MPIDR()); + primary_core_mpid = MPIDR_TO_CORE(GET_MPIDR()); cpu_count = ARRAY_SIZE(cpu_node_list); __ASSERT(cpu_count == CONFIG_MP_MAX_NUM_CPUS, "The count of CPU Cores nodes in dts is not equal to CONFIG_MP_MAX_NUM_CPUS\n"); for (i = 0, j = 0; i < cpu_count; i++) { - if (cpu_node_list[i] == master_core_mpid) { + if (cpu_node_list[i] == primary_core_mpid) { continue; } if (j == cpu_num - 1) { @@ -199,9 +199,7 @@ void arch_secondary_cpu_init(void) */ #endif -#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK soc_per_core_init_hook(); -#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */ fn = arm_cpu_boot_params.fn; arg = arm_cpu_boot_params.arg; diff --git a/arch/arm/core/cortex_a_r/swap_helper.S b/arch/arm/core/cortex_a_r/swap_helper.S index 04b19f0b046b..9417073f311c 100644 --- a/arch/arm/core/cortex_a_r/swap_helper.S +++ b/arch/arm/core/cortex_a_r/swap_helper.S @@ -69,7 +69,7 @@ SECTION_FUNC(TEXT, z_arm_do_swap) cps #MODE_SVC #if defined(CONFIG_FPU_SHARING) - ldrb r0, [r2, #_thread_offset_to_user_options] + ldrh r0, [r2, #_thread_offset_to_user_options] tst r0, #K_FP_REGS /* _current->base.user_options & K_FP_REGS */ beq out_fp_inactive @@ -151,7 +151,7 @@ out_fp_inactive: cps #MODE_SVC #if defined(CONFIG_FPU_SHARING) - ldrb r0, [r2, #_thread_offset_to_user_options] + ldrh r0, [r2, #_thread_offset_to_user_options] tst r0, #K_FP_REGS /* _current->base.user_options & K_FP_REGS */ beq in_fp_inactive diff --git a/arch/arm/core/cortex_m/__aeabi_read_tp.S b/arch/arm/core/cortex_m/__aeabi_read_tp.S index 745fda73b9bf..1e08c803b22f 100644 --- a/arch/arm/core/cortex_m/__aeabi_read_tp.S +++ b/arch/arm/core/cortex_m/__aeabi_read_tp.S @@ -5,6 +5,7 @@ */ #include +#include _ASM_FILE_PROLOGUE diff --git a/arch/arm/core/cortex_m/pm_s2ram.S b/arch/arm/core/cortex_m/pm_s2ram.S index 530fc65835e3..3ede1452cfcc 100644 --- a/arch/arm/core/cortex_m/pm_s2ram.S +++ b/arch/arm/core/cortex_m/pm_s2ram.S @@ -13,6 +13,7 @@ #include #include #include +#include /** * Macro expanding to an integer literal equal to the offset of diff --git a/arch/arm/core/cortex_m/swap_helper.S b/arch/arm/core/cortex_m/swap_helper.S index 162208e04c6a..ddb0c531582b 100644 --- a/arch/arm/core/cortex_m/swap_helper.S +++ b/arch/arm/core/cortex_m/swap_helper.S @@ -460,28 +460,36 @@ SECTION_FUNC(TEXT, z_arm_svc) .L_oops: push {r0, lr} #if defined(CONFIG_EXTRA_EXCEPTION_INFO) -#if defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) /* Build _callee_saved_t. To match the struct * definition we push the psp & then r11-r4 */ mrs r1, PSP - push {r1, r2} + push {r1, r2} /* r2 for padding */ +#if defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) push {r4-r11} +#elif defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) + mov r1, r10 + mov r2, r11 + push {r1, r2} + mov r1, r8 + mov r2, r9 + push {r1, r2} + push {r4-r7} +#else +#error Unknown ARM architecture +#endif mov r1, sp /* pointer to _callee_saved_t */ -#endif /* CONFIG_ARMV7_M_ARMV8_M_MAINLINE */ #endif /* CONFIG_EXTRA_EXCEPTION_INFO */ mov r2, lr /* EXC_RETURN */ bl z_do_kernel_oops /* return from SVC exception is done here */ #if defined(CONFIG_EXTRA_EXCEPTION_INFO) -#if defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) /* We do not need to restore any register state here * because we did not use any callee-saved registers * in this routine. Therefore, we can just reset * the MSP to its value prior to entering the function */ add sp, #40 -#endif /* CONFIG_ARMV7_M_ARMV8_M_MAINLINE */ #endif /* CONFIG_EXTRA_EXCEPTION_INFO */ pop {r0, pc} diff --git a/arch/arm/core/cortex_m/timing.c b/arch/arm/core/cortex_m/timing.c index 2ce7f64552ba..621df0e4f200 100644 --- a/arch/arm/core/cortex_m/timing.c +++ b/arch/arm/core/cortex_m/timing.c @@ -75,7 +75,7 @@ static inline uint64_t z_arm_dwt_freq_get(void) dwt_frequency = (cyc_freq * ddwt) / dcyc; } return dwt_frequency; -#endif /* CONFIG_SOC_FAMILY_NORDIC_NRF */ +#endif } void arch_timing_init(void) diff --git a/arch/arm/core/fatal.c b/arch/arm/core/fatal.c index 78b3b5b50908..2568e956d21a 100644 --- a/arch/arm/core/fatal.c +++ b/arch/arm/core/fatal.c @@ -137,21 +137,11 @@ void z_do_kernel_oops(const struct arch_esf *esf, _callee_saved_t *callee_regs, struct arch_esf esf_copy; memcpy(&esf_copy, esf, offsetof(struct arch_esf, extra_info)); -#if defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) - /* extra exception info is collected in callee_reg param - * on CONFIG_ARMV7_M_ARMV8_M_MAINLINE - */ + /* extra exception info is collected in callee_reg. */ esf_copy.extra_info = (struct __extra_esf_info) { .callee = callee_regs, }; -#else - /* extra exception info is not collected for kernel oops - * path today so we make a copy of the ESF and zero out - * that information - */ - esf_copy.extra_info = (struct __extra_esf_info) { 0 }; -#endif /* CONFIG_ARMV7_M_ARMV8_M_MAINLINE */ z_arm_fatal_error(reason, &esf_copy); #endif /* CONFIG_EXTRA_EXCEPTION_INFO */ diff --git a/arch/arm/core/mpu/Kconfig b/arch/arm/core/mpu/Kconfig index 698b2bb270a8..828122e86b8e 100644 --- a/arch/arm/core/mpu/Kconfig +++ b/arch/arm/core/mpu/Kconfig @@ -79,6 +79,12 @@ config ARM_MPU_PXN unprivileged mode and executing such region from privileged mode will result in a Memory Management fault. +config ARM_MPU_SRAM_WRITE_THROUGH + bool "Use Write-Through cache policy for SRAM regions" + help + When enabled, SRAM regions will use Write-Through cache policy + instead of the default Write-Back policy. + endif # ARM_MPU endif # CPU_HAS_MPU diff --git a/arch/arm/core/mpu/arm_mpu.c b/arch/arm/core/mpu/arm_mpu.c index d37d36967c78..a72fea183e3d 100644 --- a/arch/arm/core/mpu/arm_mpu.c +++ b/arch/arm/core/mpu/arm_mpu.c @@ -156,6 +156,11 @@ static int mpu_configure_regions_from_dt(uint8_t *reg_index) case DT_MEM_ARM_MPU_EXTMEM: region_conf = _BUILD_REGION_CONF(region[idx], REGION_EXTMEM_ATTR); break; +#endif +#ifdef REGION_RAM_WT_ATTR + case DT_MEM_ARM_MPU_RAM_WT: + region_conf = _BUILD_REGION_CONF(region[idx], REGION_RAM_WT_ATTR); + break; #endif default: /* Attribute other than ARM-specific is set. @@ -205,11 +210,11 @@ static int mpu_configure_region(const uint8_t index, !defined(CONFIG_MPU_GAP_FILLING) /* This internal function programs a set of given MPU regions * over a background memory area, optionally performing a - * sanity check of the memory regions to be programmed. + * coherence check of the memory regions to be programmed. */ static int mpu_configure_regions(const struct z_arm_mpu_partition regions[], uint8_t regions_num, uint8_t start_reg_index, - bool do_sanity_check) + bool do_coherence_check) { int i; int reg_index = start_reg_index; @@ -220,9 +225,9 @@ static int mpu_configure_regions(const struct z_arm_mpu_partition } /* Non-empty region. */ - if (do_sanity_check && + if (do_coherence_check && (!mpu_partition_is_valid(®ions[i]))) { - LOG_ERR("Partition %u: sanity check failed.", i); + LOG_ERR("Partition %u: coherence check failed.", i); return -EINVAL; } @@ -615,7 +620,7 @@ int z_arm_mpu_init(void) #endif #endif /* CONFIG_NULL_POINTER_EXCEPTION_DETECTION_MPU */ - /* Sanity check for number of regions in Cortex-M0+, M3, and M4. */ + /* Coherence check for number of regions in Cortex-M0+, M3, and M4. */ #if defined(CONFIG_CPU_CORTEX_M0PLUS) || \ defined(CONFIG_CPU_CORTEX_M3) || \ defined(CONFIG_CPU_CORTEX_M4) diff --git a/arch/arm/core/mpu/arm_mpu_regions.c b/arch/arm/core/mpu/arm_mpu_regions.c index f5f725a75fb6..4771c5914ce6 100644 --- a/arch/arm/core/mpu/arm_mpu_regions.c +++ b/arch/arm/core/mpu/arm_mpu_regions.c @@ -9,6 +9,12 @@ #include +#ifdef CONFIG_ARM_MPU_SRAM_WRITE_THROUGH +#define ARM_MPU_SRAM_REGION_ATTR REGION_RAM_WT_ATTR +#else +#define ARM_MPU_SRAM_REGION_ATTR REGION_RAM_ATTR +#endif + static const struct arm_mpu_region mpu_regions[] = { #ifdef CONFIG_XIP /* Region 0 */ @@ -26,10 +32,10 @@ static const struct arm_mpu_region mpu_regions[] = { MPU_REGION_ENTRY("SRAM_0", CONFIG_SRAM_BASE_ADDRESS, #if defined(CONFIG_ARMV8_M_BASELINE) || defined(CONFIG_ARMV8_M_MAINLINE) - REGION_RAM_ATTR(CONFIG_SRAM_BASE_ADDRESS, \ + ARM_MPU_SRAM_REGION_ATTR(CONFIG_SRAM_BASE_ADDRESS, CONFIG_SRAM_SIZE * 1024)), #else - REGION_RAM_ATTR(REGION_SRAM_SIZE)), + ARM_MPU_SRAM_REGION_ATTR(REGION_SRAM_SIZE)), #endif }; diff --git a/arch/arm/core/mpu/arm_mpu_v7_internal.h b/arch/arm/core/mpu/arm_mpu_v7_internal.h index 40d03865d07c..17cf2cb38e62 100644 --- a/arch/arm/core/mpu/arm_mpu_v7_internal.h +++ b/arch/arm/core/mpu/arm_mpu_v7_internal.h @@ -52,9 +52,9 @@ static void region_init(const uint32_t index, #endif } -/* @brief Partition sanity check +/* @brief Partition coherence check * - * This internal function performs run-time sanity check for + * This internal function performs run-time coherence check for * MPU region start address and size. * * @param part Pointer to the data structure holding the partition @@ -207,7 +207,7 @@ static int mpu_configure_region(const uint8_t index, static int mpu_configure_regions(const struct z_arm_mpu_partition regions[], uint8_t regions_num, uint8_t start_reg_index, - bool do_sanity_check); + bool do_coherence_check); /* This internal function programs the static MPU regions. * diff --git a/arch/arm/core/mpu/arm_mpu_v8_internal.h b/arch/arm/core/mpu/arm_mpu_v8_internal.h index 2ce810047e1d..995263db2990 100644 --- a/arch/arm/core/mpu/arm_mpu_v8_internal.h +++ b/arch/arm/core/mpu/arm_mpu_v8_internal.h @@ -184,9 +184,9 @@ static void region_init(const uint32_t index, region_conf->attr.mair_idx, region_conf->attr.r_limit); } -/* @brief Partition sanity check +/* @brief Partition coherence check * - * This internal function performs run-time sanity check for + * This internal function performs run-time coherence check for * MPU region start address and size. * * @param part Pointer to the data structure holding the partition @@ -519,19 +519,19 @@ static int mpu_configure_region(const uint8_t index, #if !defined(CONFIG_MPU_GAP_FILLING) static int mpu_configure_regions(const struct z_arm_mpu_partition regions[], uint8_t regions_num, uint8_t start_reg_index, - bool do_sanity_check); + bool do_coherence_check); #endif /* This internal function programs a set of given MPU regions * over a background memory area, optionally performing a - * sanity check of the memory regions to be programmed. + * coherence check of the memory regions to be programmed. * * The function performs a full partition of the background memory * area, effectively, leaving no space in this area uncovered by MPU. */ static int mpu_configure_regions_and_partition(const struct z_arm_mpu_partition regions[], uint8_t regions_num, uint8_t start_reg_index, - bool do_sanity_check) + bool do_coherence_check) { int i; int reg_index = start_reg_index; @@ -542,9 +542,9 @@ static int mpu_configure_regions_and_partition(const struct z_arm_mpu_partition } /* Non-empty region. */ - if (do_sanity_check && + if (do_coherence_check && (!mpu_partition_is_valid(®ions[i]))) { - LOG_ERR("Partition %u: sanity check failed.", i); + LOG_ERR("Partition %u: coherence check failed.", i); return -EINVAL; } diff --git a/arch/arm/core/mpu/nxp_mpu.c b/arch/arm/core/mpu/nxp_mpu.c index ae893086901c..639a6f86b646 100644 --- a/arch/arm/core/mpu/nxp_mpu.c +++ b/arch/arm/core/mpu/nxp_mpu.c @@ -51,9 +51,9 @@ static inline uint8_t get_num_regions(void) return FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT; } -/* @brief Partition sanity check +/* @brief Partition coherence check * - * This internal function performs run-time sanity check for + * This internal function performs run-time coherence check for * MPU region start address and size. * * @param part Pointer to the data structure holding the partition @@ -297,11 +297,11 @@ static int mpu_sram_partitioning(uint8_t index, /* This internal function programs a set of given MPU regions * over a background memory area, optionally performing a - * sanity check of the memory regions to be programmed. + * coherence check of the memory regions to be programmed. */ static int mpu_configure_regions(const struct z_arm_mpu_partition regions[], uint8_t regions_num, uint8_t start_reg_index, - bool do_sanity_check) + bool do_coherence_check) { int i; int reg_index = start_reg_index; @@ -312,9 +312,9 @@ static int mpu_configure_regions(const struct z_arm_mpu_partition regions[], } /* Non-empty region. */ - if (do_sanity_check && + if (do_coherence_check && (!mpu_partition_is_valid(®ions[i]))) { - LOG_ERR("Partition %u: sanity check failed.", i); + LOG_ERR("Partition %u: coherence check failed.", i); return -EINVAL; } diff --git a/arch/arm/include/cortex_a_r/kernel_arch_func.h b/arch/arm/include/cortex_a_r/kernel_arch_func.h index 2a4a89a0ae90..9dd9173300e7 100644 --- a/arch/arm/include/cortex_a_r/kernel_arch_func.h +++ b/arch/arm/include/cortex_a_r/kernel_arch_func.h @@ -31,9 +31,7 @@ extern "C" { static ALWAYS_INLINE void arch_kernel_init(void) { -#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK soc_per_core_init_hook(); -#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */ } #ifndef CONFIG_USE_SWITCH diff --git a/arch/arm/include/cortex_m/kernel_arch_func.h b/arch/arm/include/cortex_m/kernel_arch_func.h index 59290cc54630..5a3e5e65116f 100644 --- a/arch/arm/include/cortex_m/kernel_arch_func.h +++ b/arch/arm/include/cortex_m/kernel_arch_func.h @@ -57,9 +57,7 @@ static ALWAYS_INLINE void arch_kernel_init(void) z_arm_configure_static_mpu_regions(); #endif /* CONFIG_ARM_MPU */ -#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK soc_per_core_init_hook(); -#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */ } static ALWAYS_INLINE void arch_thread_return_value_set(struct k_thread *thread, unsigned int value) diff --git a/arch/arm64/core/CMakeLists.txt b/arch/arm64/core/CMakeLists.txt index 436918ccb473..48d0b68bd84e 100644 --- a/arch/arm64/core/CMakeLists.txt +++ b/arch/arm64/core/CMakeLists.txt @@ -31,6 +31,7 @@ endif() zephyr_library_sources_ifdef(CONFIG_LLEXT elf.c) zephyr_library_sources_ifdef(CONFIG_FPU_SHARING fpu.c fpu.S) +zephyr_library_sources_ifdef(CONFIG_ARM_PAC_PER_THREAD pac.c) zephyr_library_sources_ifdef(CONFIG_ARM_MMU mmu.c mmu.S) zephyr_library_sources_ifdef(CONFIG_ARM_MPU cortex_r/arm_mpu.c) zephyr_library_sources_ifdef(CONFIG_USERSPACE userspace.S) diff --git a/arch/arm64/core/Kconfig b/arch/arm64/core/Kconfig index c7d0bac3aa19..b88e8d62f478 100644 --- a/arch/arm64/core/Kconfig +++ b/arch/arm64/core/Kconfig @@ -176,13 +176,6 @@ config ARM64_SAFE_EXCEPTION_STACK used for user stack overflow checking, because kernel stack support the checking work. -config ARM64_EXCEPTION_STACK_TRACE - bool - default y - depends on FRAME_POINTER - help - Internal config to enable runtime stack traces on fatal exceptions. - config ARM64_SAFE_EXCEPTION_STACK_SIZE int "The stack size of the safe exception stack" default 4096 diff --git a/arch/arm64/core/fatal.c b/arch/arm64/core/fatal.c index c9cb6827967c..70f58ead0319 100644 --- a/arch/arm64/core/fatal.c +++ b/arch/arm64/core/fatal.c @@ -25,6 +25,9 @@ #include #include "paging.h" +#ifdef CONFIG_ARM_PAC +#include +#endif LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); @@ -176,6 +179,9 @@ static void dump_esr(uint64_t esr, bool *dump_far) case 0b111100: /* 0x3c */ err = "BRK instruction execution in AArch64 state."; break; + case 0b011100: /* 0x1c */ + err = "FPAC - Pointer Authentication failure"; + break; default: err = "Unknown"; } @@ -363,6 +369,79 @@ static bool z_arm64_stack_corruption_check(struct arch_esf *esf, uint64_t esr, u } #endif +/** + * @brief Check if exception is a BTI violation + */ +static bool is_bti_violation(uint64_t esr) +{ +#ifdef CONFIG_ARM_BTI + /* BTI violations have Exception Class 0x0d */ + return (GET_ESR_EC(esr) == 0x0d); +#else + ARG_UNUSED(esr); + return false; +#endif +} + +/** + * @brief Check if exception is a PAC authentication failure + * + * PAC authentication failures typically manifest as FPAC exceptions + * with Exception Class (EC) 0x1c. + */ +static bool is_pac_failure(uint64_t esr, uint64_t far) +{ +#ifdef CONFIG_ARM_PAC + uint64_t ec = GET_ESR_EC(esr); + + /* Check for FPAC exception (EC 0x1c) - dedicated PAC authentication failure */ + if (ec == 0x1c) { + return true; + } +#else + ARG_UNUSED(esr); + ARG_UNUSED(far); +#endif + return false; +} + +/** + * @brief Handle PACBTI-related exceptions + * + * @param esf Exception stack frame + * @param esr Exception syndrome register value + * @param far Fault address register value + * @return true if this was a PACBTI exception and was handled, false otherwise + */ +static bool z_arm64_handle_pacbti_exception(struct arch_esf *esf, uint64_t esr, uint64_t far) +{ + ARG_UNUSED(esf); + + if (is_pac_failure(esr, far)) { + EXCEPTION_DUMP("PAC AUTHENTICATION FAILURE"); + EXCEPTION_DUMP("This indicates a potential ROP/JOP attack or corrupted pointer"); +#ifdef CONFIG_THREAD_NAME + EXCEPTION_DUMP("Thread: %s", _current ? _current->name : "unknown"); +#else + EXCEPTION_DUMP("Thread: %p", _current); +#endif + return true; /* Treat as fatal */ + } + + if (is_bti_violation(esr)) { + EXCEPTION_DUMP("BTI VIOLATION - Indirect branch to invalid target"); + EXCEPTION_DUMP("This indicates a potential JOP attack or software bug"); +#ifdef CONFIG_THREAD_NAME + EXCEPTION_DUMP("Thread: %s", _current ? _current->name : "unknown"); +#else + EXCEPTION_DUMP("Thread: %p", _current); +#endif + return true; /* Treat as fatal */ + } + + return false; +} + static bool is_recoverable(struct arch_esf *esf, uint64_t esr, uint64_t far, uint64_t elr) { @@ -421,6 +500,11 @@ void z_arm64_fatal_error(unsigned int reason, struct arch_esf *esf) } #endif + /* Check for PACBTI-related exceptions */ + if (z_arm64_handle_pacbti_exception(esf, esr, far)) { + reason = K_ERR_CPU_EXCEPTION; + } + if (IS_ENABLED(CONFIG_DEMAND_PAGING) && reason != K_ERR_STACK_CHK_FAIL && z_arm64_do_demand_paging(esf, esr, far)) { diff --git a/arch/arm64/core/fpu.c b/arch/arm64/core/fpu.c index 5ae9777ec3bc..78a9aab7b308 100644 --- a/arch/arm64/core/fpu.c +++ b/arch/arm64/core/fpu.c @@ -475,6 +475,8 @@ int arch_float_disable(struct k_thread *thread) { if (thread != NULL) { unsigned int key = arch_irq_lock(); + /* Clear FP options to indicate FPU mode is disabled */ + thread->base.user_options &= ~K_FP_REGS; #ifdef CONFIG_SMP flush_owned_fpu(thread); diff --git a/arch/arm64/core/mmu.c b/arch/arm64/core/mmu.c index 2656f4d3be5c..5118d563077b 100644 --- a/arch/arm64/core/mmu.c +++ b/arch/arm64/core/mmu.c @@ -728,6 +728,13 @@ static uint64_t get_region_desc(uint32_t attrs) desc |= PTE_BLOCK_DESC_UXN; } +#ifdef CONFIG_ARM_BTI + /* Set GP (Guarded Page) bit for executable pages to enable BTI */ + if (!(desc & PTE_BLOCK_DESC_PXN)) { + desc |= PTE_BLOCK_DESC_GP; + } +#endif + if (mem_type == MT_NORMAL) { desc |= PTE_BLOCK_DESC_INNER_SHARE; } else { @@ -988,6 +995,16 @@ static sys_slist_t domain_list; * This function provides the default configuration mechanism for the Memory * Management Unit (MMU). */ +#ifdef CONFIG_ARM_PAC +/* + * Disable PAC protection for MMU activation to prevent authentication + * failures. When PAC is enabled, return address authentication can fail + * during MMU activation because memory mapping changes affect the return address + * stored on the stack, causing the PAC authentication to fail on function + * return. This attribute ensures the MMU init can complete safely. + */ +__attribute__((target("branch-protection=none"))) +#endif void z_arm64_mm_init(bool is_primary_core) { unsigned int flags = 0U; diff --git a/arch/arm64/core/mmu.h b/arch/arm64/core/mmu.h index 47be42db6352..8bb1ac786579 100644 --- a/arch/arm64/core/mmu.h +++ b/arch/arm64/core/mmu.h @@ -118,6 +118,7 @@ #define PTE_BLOCK_DESC_INNER_SHARE (3ULL << 8) #define PTE_BLOCK_DESC_AF (1ULL << 10) #define PTE_BLOCK_DESC_NG (1ULL << 11) +#define PTE_BLOCK_DESC_GP (1ULL << 50) #define PTE_BLOCK_DESC_PXN (1ULL << 53) #define PTE_BLOCK_DESC_UXN (1ULL << 54) diff --git a/arch/arm64/core/pac.c b/arch/arm64/core/pac.c new file mode 100644 index 000000000000..d348aeb4d800 --- /dev/null +++ b/arch/arm64/core/pac.c @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2026 BayLibre SAS + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +/** + * @brief Generate random PAC keys + * + * Uses a single sys_rand_get() call for efficiency. + */ +void z_arm64_pac_keys_generate(struct pac_keys *keys) +{ + /* Generate all keys with a single random call using the union */ + sys_rand_get(keys->raw_bytes, sizeof(keys->raw_bytes)); +} + +/** + * @brief Save current PAC keys from hardware registers + */ +void z_arm64_pac_keys_save(struct pac_keys *keys) +{ + /* Save APIA key */ + keys->apia.lo = read_apiakeylo_el1(); + keys->apia.hi = read_apiakeyhi_el1(); + + /* Save APIB key */ + keys->apib.lo = read_apibkeylo_el1(); + keys->apib.hi = read_apibkeyhi_el1(); + + /* Save APDA key */ + keys->apda.lo = read_apdakeylo_el1(); + keys->apda.hi = read_apdakeyhi_el1(); + + /* Save APDB key */ + keys->apdb.lo = read_apdbkeylo_el1(); + keys->apdb.hi = read_apdbkeyhi_el1(); + + /* Save APGA key */ + keys->apga.lo = read_apgakeylo_el1(); + keys->apga.hi = read_apgakeyhi_el1(); +} + +/** + * @brief Restore PAC keys to hardware registers + * + * This function is compiled without branch protection because it modifies the PAC key + * registers. Return address authentication would fail on exit since the keys used to + * sign the return address on entry would no longer match the modified keys on exit. + */ +__attribute__((target("branch-protection=none"))) +void z_arm64_pac_keys_restore(const struct pac_keys *keys) +{ + /* Restore APIA key */ + write_apiakeylo_el1(keys->apia.lo); + write_apiakeyhi_el1(keys->apia.hi); + + /* Restore APIB key */ + write_apibkeylo_el1(keys->apib.lo); + write_apibkeyhi_el1(keys->apib.hi); + + /* Restore APDA key */ + write_apdakeylo_el1(keys->apda.lo); + write_apdakeyhi_el1(keys->apda.hi); + + /* Restore APDB key */ + write_apdbkeylo_el1(keys->apdb.lo); + write_apdbkeyhi_el1(keys->apdb.hi); + + /* Restore APGA key */ + write_apgakeylo_el1(keys->apga.lo); + write_apgakeyhi_el1(keys->apga.hi); +} + +/** + * @brief Handle PAC key context switching between threads + * + * Called from z_arm64_context_switch() assembly routine during thread switches. + * Saves the current thread's PAC keys and loads the next thread's PAC keys. + * This function is compiled without branch protection because it modifies the PAC key + * registers. Return address authentication would fail on exit since the keys used to + * sign the return address on entry would no longer match the modified keys on exit. + * + * @param new_thread Pointer to the thread being switched to + * @param old_thread Pointer to the thread being switched from + */ +__attribute__((target("branch-protection=none"))) +void z_arm64_pac_thread_context_switch(struct k_thread *new_thread, struct k_thread *old_thread) +{ + /* Save current thread's PAC keys */ + z_arm64_pac_keys_save(&old_thread->arch.pac_keys); + + /* Load new thread's PAC keys */ + z_arm64_pac_keys_restore(&new_thread->arch.pac_keys); +} diff --git a/arch/arm64/core/reset.c b/arch/arm64/core/reset.c index 3624715379b0..3ade7057bb64 100644 --- a/arch/arm64/core/reset.c +++ b/arch/arm64/core/reset.c @@ -108,6 +108,10 @@ void z_arm64_el3_init(void) SCR_ST_BIT | /* Do not trap EL1 accesses to timer */ SCR_HCE_BIT | /* Do not trap HVC */ SCR_SMD_BIT); /* Do not trap SMC */ +#ifdef CONFIG_ARM_PAC + reg |= (SCR_APK_BIT | /* Do not trap pointer authentication key accesses */ + SCR_API_BIT); /* Do not trap pointer authentication instructions */ +#endif write_scr_el3(reg); #if defined(CONFIG_GIC_V3) @@ -166,6 +170,12 @@ void z_arm64_el2_init(void) */ reg &= ~(HCR_IMO_BIT | HCR_AMO_BIT | HCR_TGE_BIT); reg |= HCR_RW_BIT; /* EL1 Execution state is AArch64 */ + +#ifdef CONFIG_ARM_PAC + /* Do not trap pointer authentication instructions and key registers */ + reg |= (HCR_API_BIT | HCR_APK_BIT); +#endif + write_hcr_el2(reg); reg = 0U; /* RES0 */ @@ -213,6 +223,9 @@ void z_arm64_el2_init(void) barrier_isync_fence_full(); } +#ifdef CONFIG_ARM_PAC +__attribute__((target("branch-protection=none"))) +#endif void z_arm64_el1_init(void) { uint64_t reg; @@ -244,7 +257,23 @@ void z_arm64_el1_init(void) SCTLR_I_BIT | /* Enable i-cache */ SCTLR_C_BIT | /* Enable d-cache */ SCTLR_SA_BIT); /* Enable SP alignment check */ + +#ifdef CONFIG_ARM_PAC + /* Set a default APIA key BEFORE enabling PAC */ + write_apiakeylo_el1(0x0123456789ABCDEFULL); + write_apiakeyhi_el1(0xFEDCBA9876543210ULL); + /* Now enable Pointer Authentication */ + reg |= SCTLR_EnIA_BIT; /* Enable instruction address signing using key A */ +#endif + +#ifdef CONFIG_ARM_BTI + /* Enable Branch Target Identification */ + reg |= SCTLR_BT0_BIT; /* Enable BTI for EL0 (userspace threads) */ + reg |= SCTLR_BT1_BIT; /* Enable BTI for EL1 (kernel) */ +#endif + write_sctlr_el1(reg); + barrier_isync_fence_full(); write_cntv_cval_el0(~(uint64_t)0); /* diff --git a/arch/arm64/core/smp.c b/arch/arm64/core/smp.c index a52223643091..2ff0655092dc 100644 --- a/arch/arm64/core/smp.c +++ b/arch/arm64/core/smp.c @@ -166,9 +166,7 @@ void arch_secondary_cpu_init(int cpu_num) #endif #endif -#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK soc_per_core_init_hook(); -#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */ fn = arm64_cpu_boot_params.fn; arg = arm64_cpu_boot_params.arg; diff --git a/arch/arm64/core/switch.S b/arch/arm64/core/switch.S index 38c7bf7b24e5..60c30ccb5e5e 100644 --- a/arch/arm64/core/switch.S +++ b/arch/arm64/core/switch.S @@ -74,6 +74,18 @@ SECTION_FUNC(TEXT, z_arm64_context_switch) ldp x0, x1, [sp], #16 #endif +#ifdef CONFIG_ARM_PAC_PER_THREAD + /* + * Save and restore PAC keys during context switch. + * This ensures each thread has its own unique PAC keys for security isolation. + * Now safe to call C function since PAC key management functions are compiled + * without PAC protection (branch-protection=none). + */ + stp x0, x1, [sp, #-16]! + bl z_arm64_pac_thread_context_switch + ldp x0, x1, [sp], #16 +#endif + #ifdef CONFIG_SMP /* Write barrier: ensure all preceding writes are executed * before writing the switch handle diff --git a/arch/arm64/core/thread.c b/arch/arm64/core/thread.c index 53cf707b584e..956f3160b5a4 100644 --- a/arch/arm64/core/thread.c +++ b/arch/arm64/core/thread.c @@ -14,6 +14,9 @@ #include #include #include +#ifdef CONFIG_ARM_PAC_PER_THREAD +#include +#endif /* * Note about stack usage: @@ -149,6 +152,11 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack, thread->arch.stack_limit = (uint64_t)stack + Z_ARM64_STACK_GUARD_SIZE; z_arm64_thread_mem_domains_init(thread); #endif + +#ifdef CONFIG_ARM_PAC_PER_THREAD + /* Generate unique PAC keys for this thread */ + z_arm64_pac_keys_generate(&thread->arch.pac_keys); +#endif } #ifdef CONFIG_USERSPACE diff --git a/arch/arm64/core/xen/CMakeLists.txt b/arch/arm64/core/xen/CMakeLists.txt index cbedb1204e19..619421f79cce 100644 --- a/arch/arm64/core/xen/CMakeLists.txt +++ b/arch/arm64/core/xen/CMakeLists.txt @@ -5,4 +5,4 @@ zephyr_compile_options($<$:-D__ASSEMBLY__>) zephyr_library_sources(hypercall.S) -zephyr_library_sources(enlighten.c) +zephyr_library_sources_ifdef(CONFIG_XEN_EVENTS enlighten.c) diff --git a/arch/arm64/include/kernel_arch_func.h b/arch/arm64/include/kernel_arch_func.h index 809775a0f5b5..4330bb446605 100644 --- a/arch/arm64/include/kernel_arch_func.h +++ b/arch/arm64/include/kernel_arch_func.h @@ -32,10 +32,7 @@ extern "C" { static ALWAYS_INLINE void arch_kernel_init(void) { - -#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK soc_per_core_init_hook(); -#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */ } static inline void arch_switch(void *switch_to, void **switched_from) diff --git a/arch/common/Kconfig b/arch/common/Kconfig index 54f52da62025..5f45301135ea 100644 --- a/arch/common/Kconfig +++ b/arch/common/Kconfig @@ -79,7 +79,8 @@ config ARM_MPU config ARM_PAC_PER_THREAD bool "Set cryptographically secure PAC key per thread" depends on ARM_PAC - depends on ENTROPY_DEVICE_RANDOM_GENERATOR || TIMER_RANDOM_GENERATOR + select CSPRNG_NEEDED + imply TEST_RANDOM_GENERATOR if !CSPRNG_ENABLED help Select this option to generate and use unique keys per thread to generate Pointer Authentication Code. @@ -99,19 +100,29 @@ config ARM_PAC config ARM_BTI bool + depends on MINIMAL_LIBC || PICOLIBC_USE_MODULE help This option signifies that Branch Target Identification is enabled. + Note: BTI requires that the C library be compiled with + -mbranch-protection to include BTI landing pads. Newlib from + toolchains lacks this support, so only minimal libc or picolibc + built from source (PICOLIBC_USE_MODULE) can be used with BTI. + choice ARM_PACBTI prompt "Pointer Authentication and Branch Target Identification (PACBTI)" default ARM_PACBTI_NONE - depends on ARMV8_1_M_MAINLINE + depends on ARMV8_1_M_MAINLINE || ARMV8_A || ARMV9_A help Select a PACBTI configuration to enable the compiler to insert the required Pointer Authentication and Branch Target Identification (PACBTI) instructions. This also sets the necessary configuration options to enable PACBTI bits in hardware. + On ARM32, PACBTI is available on ARMv8.1-M Mainline processors. + On ARM64, PAC requires ARMv8.3-A or later and BTI requires + ARMv8.5-A or later. ARMv9-A includes both as mandatory features. + config ARM_PACBTI_STANDARD bool "Standard (PACRET + LEAF + BTI)" select ARM_PAC diff --git a/arch/common/init.c b/arch/common/init.c index b5e83a0b8dc1..802c21464a93 100644 --- a/arch/common/init.c +++ b/arch/common/init.c @@ -55,11 +55,6 @@ void arch_bss_zero(void) } arch_early_memset(__bss_start, 0, __bss_end - __bss_start); -#if DT_NODE_HAS_STATUS_OKAY(DT_CHOSEN(zephyr_ccm)) - arch_early_memset(&__ccm_bss_start, 0, - (uintptr_t) &__ccm_bss_end - - (uintptr_t) &__ccm_bss_start); -#endif #if DT_NODE_HAS_STATUS_OKAY(DT_CHOSEN(zephyr_dtcm)) arch_early_memset(&__dtcm_bss_start, 0, (uintptr_t) &__dtcm_bss_end diff --git a/arch/common/xip.c b/arch/common/xip.c index 234d323118b5..10b8fda1d336 100644 --- a/arch/common/xip.c +++ b/arch/common/xip.c @@ -38,10 +38,6 @@ void arch_data_copy(void) (uintptr_t) &_nocache_load_ram_size); #endif /* CONFIG_NOCACHE_MEMORY */ #endif /* CONFIG_ARCH_HAS_NOCACHE_MEMORY_SUPPORT */ -#if DT_NODE_HAS_STATUS_OKAY(DT_CHOSEN(zephyr_ccm)) - arch_early_memcpy(&__ccm_data_start, &__ccm_data_load_start, - __ccm_data_end - __ccm_data_start); -#endif #if DT_NODE_HAS_STATUS_OKAY(DT_CHOSEN(zephyr_itcm)) arch_early_memcpy(&__itcm_start, &__itcm_load_start, (uintptr_t) &__itcm_size); diff --git a/arch/mips/include/kernel_arch_func.h b/arch/mips/include/kernel_arch_func.h index 63ed7a65cf26..5ac0bd95bef5 100644 --- a/arch/mips/include/kernel_arch_func.h +++ b/arch/mips/include/kernel_arch_func.h @@ -28,9 +28,7 @@ extern "C" { #ifndef _ASMLANGUAGE static ALWAYS_INLINE void arch_kernel_init(void) { -#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK soc_per_core_init_hook(); -#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */ } static ALWAYS_INLINE void diff --git a/arch/posix/CMakeLists.txt b/arch/posix/CMakeLists.txt index b4fb1e7d9f3c..290ec7fddecc 100644 --- a/arch/posix/CMakeLists.txt +++ b/arch/posix/CMakeLists.txt @@ -62,10 +62,11 @@ elseif(DEFINED NATIVE_TARGET_HOST) ) endif() -zephyr_compile_options( - ${ARCH_FLAG} - ) - +# We tell the compiler to mark all symbols to have hidden visibility by default. +# Later, after the image from all embedded code has been built, all these symbols will be made local +# (i.e. not linkable anymore from outside that embedded code library). +# If users want to be able to link to a symbol from outside the embedded image, they should annotate +# it with one of NATIVE_SIMULATOR_IF* zephyr_compile_options( -fvisibility=hidden ) @@ -99,17 +100,15 @@ if(NOT CONFIG_EXTERNAL_LIBC) $ $ ) +else() + # No freestanding compilation, i.e. we use the compiler default C library + zephyr_compile_options($) endif() if(CONFIG_COMPILER_WARNINGS_AS_ERRORS) target_compile_options(native_simulator INTERFACE $) endif() -if(CONFIG_EXTERNAL_LIBC) - # @Intent: Obtain compiler specific flags for no freestanding compilation - zephyr_compile_options($) -endif() - if(CONFIG_EXTERNAL_LIBCPP) target_link_options(native_simulator INTERFACE "-lstdc++") endif() diff --git a/arch/posix/core/CMakeLists.txt b/arch/posix/core/CMakeLists.txt index 8d5415fa02cd..1a09775b733b 100644 --- a/arch/posix/core/CMakeLists.txt +++ b/arch/posix/core/CMakeLists.txt @@ -1,7 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 zephyr_library() -zephyr_library_compile_definitions(NO_POSIX_CHEATS) zephyr_library_sources( cpuhalt.c fatal.c diff --git a/arch/posix/include/kernel_arch_func.h b/arch/posix/include/kernel_arch_func.h index ceba8a850934..2cfe05525f27 100644 --- a/arch/posix/include/kernel_arch_func.h +++ b/arch/posix/include/kernel_arch_func.h @@ -22,9 +22,7 @@ extern "C" { static inline void arch_kernel_init(void) { -#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK soc_per_core_init_hook(); -#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */ } static ALWAYS_INLINE void diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index b720faa35a2d..df5574609e5b 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -13,8 +13,11 @@ config FLOAT_HARD bool "Hard-float calling convention" default y depends on FPU + depends on !RISCV_ISA_RV32E + depends on RISCV_ISA_EXT_F help This option enables the hard-float calling convention. + Adds eight floating-point argument registers. choice RISCV_GP_PURPOSE prompt "Purpose of the global pointer (GP) register" diff --git a/arch/riscv/Kconfig.isa b/arch/riscv/Kconfig.isa index c5ee324464d8..c3b3c4044ae1 100644 --- a/arch/riscv/Kconfig.isa +++ b/arch/riscv/Kconfig.isa @@ -1,29 +1,37 @@ # Copyright (c) 2022 Carlo Caione # SPDX-License-Identifier: Apache-2.0 +RISCV_ISA_BASE_PROP := riscv,isa-base +RISCV_ISA_EXT_PROP := riscv,isa-extensions + config RISCV_ISA_RV32I bool + default y if $(dt_compat_all_has_prop,riscv,$(RISCV_ISA_BASE_PROP),rv32i) help RV32I Base Integer Instruction Set - 32bit config RISCV_ISA_RV32E bool + default y if $(dt_compat_all_has_prop,riscv,$(RISCV_ISA_BASE_PROP),rv32e) help RV32E Base Integer Instruction Set (Embedded) - 32bit config RISCV_ISA_RV64I bool + default y if $(dt_compat_all_has_prop,riscv,$(RISCV_ISA_BASE_PROP),rv64i) select 64BIT help RV64I Base Integer Instruction Set - 64bit config RISCV_ISA_RV128I bool + default y if $(dt_compat_all_has_prop,riscv,$(RISCV_ISA_BASE_PROP),rv128i) help RV128I Base Integer Instruction Set - 128bit config RISCV_ISA_EXT_M bool + default y if $(dt_compat_all_has_prop,riscv,$(RISCV_ISA_EXT_PROP),m) help (M) - Standard Extension for Integer Multiplication and Division @@ -33,6 +41,7 @@ config RISCV_ISA_EXT_M config RISCV_ISA_EXT_A bool + default y if $(dt_compat_all_has_prop,riscv,$(RISCV_ISA_EXT_PROP),a) imply RISCV_ISA_EXT_ZAAMO imply RISCV_ISA_EXT_ZALRSC help @@ -45,6 +54,7 @@ config RISCV_ISA_EXT_A config RISCV_ISA_EXT_F bool + default y if $(dt_compat_all_has_prop,riscv,$(RISCV_ISA_EXT_PROP),f) select CPU_HAS_FPU help (F) - Standard Extension for Single-Precision Floating-Point @@ -56,6 +66,7 @@ config RISCV_ISA_EXT_F config RISCV_ISA_EXT_D bool + default y if $(dt_compat_all_has_prop,riscv,$(RISCV_ISA_EXT_PROP),d) depends on RISCV_ISA_EXT_F select CPU_HAS_FPU_DOUBLE_PRECISION help @@ -79,6 +90,7 @@ config RISCV_ISA_EXT_G config RISCV_ISA_EXT_Q bool + default y if $(dt_compat_all_has_prop,riscv,$(RISCV_ISA_EXT_PROP),q) depends on RISCV_ISA_RV64I depends on RISCV_ISA_EXT_F depends on RISCV_ISA_EXT_D @@ -91,6 +103,7 @@ config RISCV_ISA_EXT_Q config RISCV_ISA_EXT_C bool + default y if $(dt_compat_all_has_prop,riscv,$(RISCV_ISA_EXT_PROP),c) select RISCV_ISA_EXT_ZCA select RISCV_ISA_EXT_ZCD if RISCV_ISA_EXT_D select RISCV_ISA_EXT_ZCF if RISCV_ISA_EXT_F && (RISCV_ISA_RV32I || RISCV_ISA_RV32E) @@ -103,6 +116,7 @@ config RISCV_ISA_EXT_C config RISCV_ISA_EXT_ZICNTR bool + default y if $(dt_compat_all_has_prop,riscv,$(RISCV_ISA_EXT_PROP),zicntr) depends on RISCV_ISA_EXT_ZICSR help (Zicntr) - Standard Extension for Base Counters and Timers @@ -113,6 +127,7 @@ config RISCV_ISA_EXT_ZICNTR config RISCV_ISA_EXT_ZICSR bool + default y if $(dt_compat_all_has_prop,riscv,$(RISCV_ISA_EXT_PROP),zicsr) help (Zicsr) - Standard Extension for Control and Status Register (CSR) Instructions @@ -121,6 +136,7 @@ config RISCV_ISA_EXT_ZICSR config RISCV_ISA_EXT_SMCSRIND bool + default y if $(dt_compat_all_has_prop,riscv,$(RISCV_ISA_EXT_PROP),smcsrind) depends on RISCV_ISA_EXT_ZICSR help (Smcsrind) - Standard Extension for Indirect CSR Access @@ -130,6 +146,7 @@ config RISCV_ISA_EXT_SMCSRIND config RISCV_ISA_EXT_ZIFENCEI bool + default y if $(dt_compat_all_has_prop,riscv,$(RISCV_ISA_EXT_PROP),zifencei) help (Zifencei) - Standard Extension for Instruction-Fetch Fence @@ -139,6 +156,7 @@ config RISCV_ISA_EXT_ZIFENCEI config RISCV_ISA_EXT_ZAAMO bool + default y if $(dt_compat_all_has_prop,riscv,$(RISCV_ISA_EXT_PROP),zaamo) help (Zaamo) - Atomic memory operation subset of the A extension @@ -146,6 +164,7 @@ config RISCV_ISA_EXT_ZAAMO config RISCV_ISA_EXT_ZALRSC bool + default y if $(dt_compat_all_has_prop,riscv,$(RISCV_ISA_EXT_PROP),zalrsc) help (Zalrsc) - Load-Reserved/Store-Conditional subset of the A extension @@ -153,6 +172,7 @@ config RISCV_ISA_EXT_ZALRSC config RISCV_ISA_EXT_ZCA bool + default y if $(dt_compat_all_has_prop,riscv,$(RISCV_ISA_EXT_PROP),zca) help (Zca) - Zba Extension for Compressed Instructions @@ -161,6 +181,7 @@ config RISCV_ISA_EXT_ZCA config RISCV_ISA_EXT_ZCB bool + default y if $(dt_compat_all_has_prop,riscv,$(RISCV_ISA_EXT_PROP),zcb) depends on RISCV_ISA_EXT_ZCA help (Zcb) - Zcb Extension for Simple Compressed Instructions @@ -170,6 +191,7 @@ config RISCV_ISA_EXT_ZCB config RISCV_ISA_EXT_ZCD bool + default y if $(dt_compat_all_has_prop,riscv,$(RISCV_ISA_EXT_PROP),zcd) depends on RISCV_ISA_EXT_D depends on RISCV_ISA_EXT_ZCA help @@ -180,6 +202,7 @@ config RISCV_ISA_EXT_ZCD config RISCV_ISA_EXT_ZCF bool + default y if $(dt_compat_all_has_prop,riscv,$(RISCV_ISA_EXT_PROP),zcf) depends on RISCV_ISA_RV32I || RISCV_ISA_RV32E depends on RISCV_ISA_EXT_F depends on RISCV_ISA_EXT_ZCA @@ -191,6 +214,7 @@ config RISCV_ISA_EXT_ZCF config RISCV_ISA_EXT_ZCMP bool + default y if $(dt_compat_all_has_prop,riscv,$(RISCV_ISA_EXT_PROP),zcmp) depends on RISCV_ISA_EXT_ZCA depends on !RISCV_ISA_EXT_ZCD help @@ -201,6 +225,7 @@ config RISCV_ISA_EXT_ZCMP config RISCV_ISA_EXT_ZCMT bool + default y if $(dt_compat_all_has_prop,riscv,$(RISCV_ISA_EXT_PROP),zcmt) depends on RISCV_ISA_EXT_ZICSR depends on RISCV_ISA_EXT_ZCA depends on !RISCV_ISA_EXT_ZCD @@ -212,6 +237,7 @@ config RISCV_ISA_EXT_ZCMT config RISCV_ISA_EXT_ZBA bool + default y if $(dt_compat_all_has_prop,riscv,$(RISCV_ISA_EXT_PROP),zba) help (Zba) - Zba BitManip Extension @@ -222,6 +248,7 @@ config RISCV_ISA_EXT_ZBA config RISCV_ISA_EXT_ZBB bool + default y if $(dt_compat_all_has_prop,riscv,$(RISCV_ISA_EXT_PROP),zbb) help (Zbb) - Zbb BitManip Extension (Basic bit-manipulation) @@ -231,14 +258,25 @@ config RISCV_ISA_EXT_ZBB config RISCV_ISA_EXT_ZBC bool + default y if $(dt_compat_all_has_prop,riscv,$(RISCV_ISA_EXT_PROP),zbc) help (Zbc) - Zbc BitManip Extension (Carry-less multiplication) The Zbc instructions can be used for carry-less multiplication that is the multiplication in the polynomial ring over GF(2). +config RISCV_ISA_EXT_ZBKB + bool + default y if $(dt_compat_all_has_prop,riscv,$(RISCV_ISA_EXT_PROP),zbkb) + help + (Zbkb) - Zbkb BitManip Extension (Bit-manipulation for Cryptography) + + The Zbkb instructions can be used for accelerating cryptography workloads + and contain rotation, reversion, packing and some advanced bit-manipulation. + config RISCV_ISA_EXT_ZBS bool + default y if $(dt_compat_all_has_prop,riscv,$(RISCV_ISA_EXT_PROP),zbs) help (Zbs) - Zbs BitManip Extension (Single-bit instructions) @@ -248,6 +286,7 @@ config RISCV_ISA_EXT_ZBS config RISCV_ISA_EXT_ZMMUL bool + default y if $(dt_compat_all_has_prop,riscv,$(RISCV_ISA_EXT_PROP),zmmul) help (Zmmul) - Zmmul Extension for Integer Multiplication diff --git a/arch/riscv/core/CMakeLists.txt b/arch/riscv/core/CMakeLists.txt index dafbe63ff0b9..f42b156e0e27 100644 --- a/arch/riscv/core/CMakeLists.txt +++ b/arch/riscv/core/CMakeLists.txt @@ -28,6 +28,7 @@ zephyr_library_sources_ifdef(CONFIG_DEBUG_COREDUMP coredump.c) zephyr_library_sources_ifdef(CONFIG_IRQ_OFFLOAD irq_offload.c) zephyr_library_sources_ifdef(CONFIG_USE_ISR_WRAPPER isr.S) zephyr_library_sources_ifdef(CONFIG_RISCV_PMP pmp.c pmp.S) +zephyr_linker_sources_ifdef(CONFIG_RISCV_PMP ROM_SECTIONS pmp.ld) zephyr_library_sources_ifdef(CONFIG_THREAD_LOCAL_STORAGE tls.c) zephyr_library_sources_ifdef(CONFIG_USERSPACE userspace.S) zephyr_library_sources_ifdef(CONFIG_SEMIHOST semihost.c) diff --git a/arch/riscv/core/fatal.c b/arch/riscv/core/fatal.c index 1f40c81fc37e..a1f9fd0af4a6 100644 --- a/arch/riscv/core/fatal.c +++ b/arch/riscv/core/fatal.c @@ -77,7 +77,7 @@ const char *z_riscv_mcause_str(unsigned long cause) return mcause_str[MIN(cause, ARRAY_SIZE(mcause_str) - 1)]; } -FUNC_NORETURN void z_riscv_fatal_error(unsigned int reason, +void z_riscv_fatal_error(unsigned int reason, const struct arch_esf *esf) { __maybe_unused _callee_saved_t *csf = NULL; @@ -142,7 +142,6 @@ FUNC_NORETURN void z_riscv_fatal_error(unsigned int reason, #endif /* CONFIG_EXCEPTION_STACK_TRACE */ z_fatal_error(reason, esf); - CODE_UNREACHABLE; } static bool bad_stack_pointer(struct arch_esf *esf) @@ -232,6 +231,7 @@ void z_riscv_fault(struct arch_esf *esf) } z_riscv_fatal_error(reason, esf); + CODE_UNREACHABLE; } #ifdef CONFIG_USERSPACE @@ -257,6 +257,7 @@ void z_impl_user_fault(unsigned int reason) reason = K_ERR_KERNEL_OOPS; } z_riscv_fatal_error(reason, oops_esf); + CODE_UNREACHABLE; } static void z_vrfy_user_fault(unsigned int reason) diff --git a/arch/riscv/core/irq_manage.c b/arch/riscv/core/irq_manage.c index 3d18ec59dba3..6d7fb57fbcb7 100644 --- a/arch/riscv/core/irq_manage.c +++ b/arch/riscv/core/irq_manage.c @@ -44,6 +44,7 @@ FUNC_NORETURN void z_irq_spurious(const void *unused) } #endif z_riscv_fatal_error(K_ERR_SPURIOUS_IRQ, NULL); + CODE_UNREACHABLE; #endif /* CONFIG_EMPTY_IRQ_SPURIOUS */ } diff --git a/arch/riscv/core/isr.S b/arch/riscv/core/isr.S index dfd68660ec0c..ff7e0585822a 100644 --- a/arch/riscv/core/isr.S +++ b/arch/riscv/core/isr.S @@ -479,7 +479,8 @@ do_fault: addi sp, sp, -__callee_saved_t_SIZEOF STORE_CALLEE_SAVED(a1) #endif /* CONFIG_EXCEPTION_DEBUG */ - tail z_riscv_fatal_error + call z_riscv_fatal_error + j check_reschedule #if defined(CONFIG_IRQ_OFFLOAD) do_irq_offload: diff --git a/arch/riscv/core/pmp.c b/arch/riscv/core/pmp.c index db5fd2b7e746..348c607cbb09 100644 --- a/arch/riscv/core/pmp.c +++ b/arch/riscv/core/pmp.c @@ -318,7 +318,7 @@ extern void z_riscv_write_pmp_entries(unsigned int start, unsigned int end, /** * @brief Write a range of PMP entries to corresponding PMP registers * - * This performs some sanity checks before calling z_riscv_write_pmp_entries(). + * This performs some coherence checks before calling z_riscv_write_pmp_entries(). * * @param start Start of the PMP range to be written * @param end End (exclusive) of the PMP range to be written @@ -617,6 +617,19 @@ void z_riscv_pmp_init(void) (size_t)__rom_region_size, pmp_addr, pmp_cfg, ARRAY_SIZE(pmp_addr)); + /* SoC-specific PMP regions defined via iterable sections */ + STRUCT_SECTION_FOREACH(pmp_soc_region, region) { + uintptr_t start = (uintptr_t)region->start; + size_t size = (uintptr_t)region->end - start; + + if (size > 0) { + set_pmp_entry(&index, region->perm | COND_CODE_1(CONFIG_PMP_NO_LOCK_GLOBAL, + (0x0), (PMP_L)), start, + size, pmp_addr, pmp_cfg, + ARRAY_SIZE(pmp_addr)); + } + } + #ifdef CONFIG_PMP_STACK_GUARD #ifdef CONFIG_MULTITHREADING /* diff --git a/arch/riscv/core/pmp.ld b/arch/riscv/core/pmp.ld new file mode 100644 index 000000000000..344091df78bf --- /dev/null +++ b/arch/riscv/core/pmp.ld @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +ITERABLE_SECTION_ROM(pmp_soc_region, Z_LINK_ITERABLE_SUBALIGN) diff --git a/arch/riscv/core/smp.c b/arch/riscv/core/smp.c index b91595fa1a8f..2136aa47dc06 100644 --- a/arch/riscv/core/smp.c +++ b/arch/riscv/core/smp.c @@ -12,6 +12,9 @@ #include #include #include +#if defined(CONFIG_RISCV_IMSIC) +#include +#endif volatile struct { arch_cpustart_t fn; @@ -79,8 +82,10 @@ void arch_secondary_cpu_init(int hartid) /* Enable on secondary cores so that they can respond to PLIC */ irq_enable(RISCV_IRQ_MEXT); #endif /* CONFIG_PLIC_IRQ_AFFINITY */ -#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK +#if defined(CONFIG_RISCV_IMSIC) && defined(CONFIG_SMP) + /* Initialize IMSIC on secondary CPU */ + z_riscv_imsic_secondary_init(); +#endif /* CONFIG_RISCV_IMSIC && CONFIG_SMP */ soc_per_core_init_hook(); -#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */ riscv_cpu_init[cpu_num].fn(riscv_cpu_init[cpu_num].arg); } diff --git a/arch/riscv/core/switch.S b/arch/riscv/core/switch.S index 81292748f838..b78289af68b6 100644 --- a/arch/riscv/core/switch.S +++ b/arch/riscv/core/switch.S @@ -73,7 +73,7 @@ SECTION_FUNC(TEXT, z_riscv_switch) * in effect while in m-mode. (it is done on every exception return * otherwise). */ - lb t0, _thread_offset_to_user_options(a0) + lh t0, _thread_offset_to_user_options(a0) andi t0, t0, K_USER beqz t0, not_user_task mv s0, a0 diff --git a/arch/riscv/custom/andes/pma.c b/arch/riscv/custom/andes/pma.c index 1e9d41c4f54f..11f2a46d02ec 100644 --- a/arch/riscv/custom/andes/pma.c +++ b/arch/riscv/custom/andes/pma.c @@ -141,7 +141,7 @@ static void region_init(const uint32_t index, } /* - * This internal function performs run-time sanity check for + * This internal function performs run-time coherence check for * PMA region start address and size. */ static int pma_region_is_valid(const struct pma_region *region) diff --git a/arch/riscv/custom/thead/Kconfig.core b/arch/riscv/custom/thead/Kconfig.core index 3550e91957fa..453325574767 100644 --- a/arch/riscv/custom/thead/Kconfig.core +++ b/arch/riscv/custom/thead/Kconfig.core @@ -8,12 +8,6 @@ config CPU_XUANTIE_E907 select RISCV_HAS_CLIC select RISCV_MACHINE_TIMER select RISCV_PRIVILEGED - select RISCV_ISA_RV32I - select RISCV_ISA_EXT_M - select RISCV_ISA_EXT_A - select RISCV_ISA_EXT_C - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI select RISCV_VECTORED_MODE select CPU_HAS_ICACHE select CPU_HAS_DCACHE diff --git a/arch/riscv/include/kernel_arch_func.h b/arch/riscv/include/kernel_arch_func.h index b2ce84bf176c..f3a28689d095 100644 --- a/arch/riscv/include/kernel_arch_func.h +++ b/arch/riscv/include/kernel_arch_func.h @@ -55,9 +55,7 @@ static ALWAYS_INLINE void arch_kernel_init(void) #ifdef CONFIG_RISCV_PMP z_riscv_pmp_init(); #endif -#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK soc_per_core_init_hook(); -#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */ } static ALWAYS_INLINE void @@ -74,7 +72,7 @@ arch_switch(void *switch_to, void **switched_from) #endif } -FUNC_NORETURN void z_riscv_fatal_error(unsigned int reason, +void z_riscv_fatal_error(unsigned int reason, const struct arch_esf *esf); static inline bool arch_is_in_isr(void) diff --git a/arch/riscv/include/pmp.h b/arch/riscv/include/pmp.h index 8367342bb9bb..d541730ef103 100644 --- a/arch/riscv/include/pmp.h +++ b/arch/riscv/include/pmp.h @@ -7,6 +7,7 @@ #ifndef PMP_H_ #define PMP_H_ +#include #include #define PMPCFG_STRIDE (__riscv_xlen / 8) diff --git a/arch/sparc/include/kernel_arch_func.h b/arch/sparc/include/kernel_arch_func.h index fc59fdf7aa69..43ed14a56eef 100644 --- a/arch/sparc/include/kernel_arch_func.h +++ b/arch/sparc/include/kernel_arch_func.h @@ -26,9 +26,7 @@ extern "C" { #ifndef _ASMLANGUAGE static ALWAYS_INLINE void arch_kernel_init(void) { -#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK soc_per_core_init_hook(); -#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */ } void z_sparc_context_switch(struct k_thread *newt, struct k_thread *oldt); diff --git a/arch/x86/core/ia32/float.c b/arch/x86/core/ia32/float.c index 9b6f4daa18e0..8219dc7593b8 100644 --- a/arch/x86/core/ia32/float.c +++ b/arch/x86/core/ia32/float.c @@ -179,7 +179,7 @@ void z_float_enable(struct k_thread *thread, unsigned int options) /* Indicate thread requires floating point context saving */ - thread->base.user_options |= (uint8_t)options; + thread->base.user_options |= (uint16_t)options; /* * The current thread might not allow FP instructions, so clear CR0[TS] * so we can use them. (CR0[TS] gets restored later on, if necessary.) diff --git a/arch/x86/core/ia32/swap.S b/arch/x86/core/ia32/swap.S index 4baa0070b9b8..f3433bfd0f0a 100644 --- a/arch/x86/core/ia32/swap.S +++ b/arch/x86/core/ia32/swap.S @@ -175,7 +175,7 @@ SECTION_FUNC(PINNED_TEXT, arch_swap) * _and_ whether the thread was context switched out preemptively. */ - testb $_FP_USER_MASK, _thread_offset_to_user_options(%eax) + testw $_FP_USER_MASK, _thread_offset_to_user_options(%eax) je restoreContext_NoFloatSwap @@ -216,7 +216,7 @@ SECTION_FUNC(PINNED_TEXT, arch_swap) #ifdef CONFIG_X86_SSE - testb $K_SSE_REGS, _thread_offset_to_user_options(%ebx) + testw $K_SSE_REGS, _thread_offset_to_user_options(%ebx) je x87FloatSave /* @@ -255,7 +255,7 @@ restoreContext_NoFloatSave: je restoreContext_NoFloatRestore #ifdef CONFIG_X86_SSE - testb $K_SSE_REGS, _thread_offset_to_user_options(%eax) + testw $K_SSE_REGS, _thread_offset_to_user_options(%eax) je x87FloatRestore fxrstor _thread_offset_to_preempFloatReg(%eax) @@ -290,7 +290,7 @@ restoreContext_NoFloatSwap: * registers */ - testb $_FP_USER_MASK, _thread_offset_to_user_options(%eax) + testw $_FP_USER_MASK, _thread_offset_to_user_options(%eax) jne CROHandlingDone /* diff --git a/arch/x86/core/x86_mmu.c b/arch/x86/core/x86_mmu.c index b2458d027674..9bece5dd9f5c 100644 --- a/arch/x86/core/x86_mmu.c +++ b/arch/x86/core/x86_mmu.c @@ -20,7 +20,6 @@ #include #include #include -#include #include LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); diff --git a/arch/x86/gen_idt.py b/arch/x86/gen_idt.py index a302c13bff55..f424f4eb9330 100755 --- a/arch/x86/gen_idt.py +++ b/arch/x86/gen_idt.py @@ -136,7 +136,7 @@ def setup_idt(spur_code, spur_nocode, intlist, max_vec, max_irq): irq_vec_map = [0 for i in range(max_irq)] vectors = [None for i in range(max_vec)] - # Pass 1: sanity check and set up hard-coded interrupt vectors + # Pass 1: coherence check and set up hard-coded interrupt vectors for handler, irq, prio, vec, dpl, tss in intlist: if vec == -1: if prio == -1: diff --git a/arch/x86/include/ia32/kernel_arch_data.h b/arch/x86/include/ia32/kernel_arch_data.h index 97de17cc9d5b..1a57010917cf 100644 --- a/arch/x86/include/ia32/kernel_arch_data.h +++ b/arch/x86/include/ia32/kernel_arch_data.h @@ -53,7 +53,6 @@ #ifndef _ASMLANGUAGE -#include #ifdef __cplusplus extern "C" { diff --git a/arch/x86/include/ia32/kernel_arch_func.h b/arch/x86/include/ia32/kernel_arch_func.h index 686bc18989b7..2762aaf5f615 100644 --- a/arch/x86/include/ia32/kernel_arch_func.h +++ b/arch/x86/include/ia32/kernel_arch_func.h @@ -22,9 +22,7 @@ extern "C" { static inline void arch_kernel_init(void) { -#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK soc_per_core_init_hook(); -#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */ } static ALWAYS_INLINE void diff --git a/arch/x86/include/intel64/kernel_arch_func.h b/arch/x86/include/intel64/kernel_arch_func.h index da553fd08ac7..1433ccc8e71c 100644 --- a/arch/x86/include/intel64/kernel_arch_func.h +++ b/arch/x86/include/intel64/kernel_arch_func.h @@ -29,9 +29,7 @@ extern void z_x86_ipi_setup(void); static inline void arch_kernel_init(void) { -#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK soc_per_core_init_hook(); -#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */ } FUNC_NORETURN void z_x86_cpu_init(struct x86_cpuboot *cpuboot); diff --git a/arch/xtensa/core/gen_zsr.py b/arch/xtensa/core/gen_zsr.py index cc2f243d3468..69537d08f1ee 100755 --- a/arch/xtensa/core/gen_zsr.py +++ b/arch/xtensa/core/gen_zsr.py @@ -36,7 +36,7 @@ def parse_args(): NEEDED = ["A0SAVE", "CPU"] if args.mmu: - NEEDED += ["DBLEXC", "DEPC_SAVE"] + NEEDED += ["DBLEXC", "DEPC_SAVE", "EXCCAUSE_SAVE"] if args.flush_reg: NEEDED += ["FLUSH"] diff --git a/arch/xtensa/core/mmu.c b/arch/xtensa/core/mmu.c index dd20136427a0..fd961f4df2f7 100644 --- a/arch/xtensa/core/mmu.c +++ b/arch/xtensa/core/mmu.c @@ -18,6 +18,15 @@ BUILD_ASSERT((CONFIG_PRIVILEGED_STACK_SIZE > 0) && extern uint32_t *xtensa_kernel_ptables; +/** + * @brief Precompute register values needed during page table switching. + * + * This precomputes the necessary values for registers that must be + * programmed when switching page tables. This is on a per-domain basis as + * each domain has a corresponding set of page tables. + * + * @param domain Pointer to the memory domain. + */ void xtensa_mmu_compute_domain_regs(struct arch_mem_domain *domain) { uint32_t vecbase = XTENSA_RSR("VECBASE"); @@ -60,7 +69,10 @@ void xtensa_mmu_compute_domain_regs(struct arch_mem_domain *domain) | XTENSA_MMU_VECBASE_WAY; } -/* Switch to a new page table. There are four items we have to set in +/** + * @brief Switch to new page tables of a memory domain. + * + * Switch to a new page table. There are four items that must be set in * the hardware: the PTE virtual address, the ring/ASID mapping * register, and two pinned entries in the data TLB handling refills * for the page tables and the vector handlers. @@ -74,6 +86,9 @@ void xtensa_mmu_compute_domain_regs(struct arch_mem_domain *domain) * holds our five instructions is sufficient to guarantee that: I * couldn't think of a way to do the alignment statically that also * interoperated well with inline assembly). + * + * @param domain Pointer to the memory domain containing the page tables + * to be used after switching. */ void xtensa_mmu_set_paging(struct arch_mem_domain *domain) { @@ -90,7 +105,12 @@ void xtensa_mmu_set_paging(struct arch_mem_domain *domain) "r"(domain->reg_vecpin_at), "r"(domain->reg_vecpin_as)); } -/* This is effectively the same algorithm from xtensa_mmu_set_paging(), +/** + * @brief Initialize paging to enable MMU. + * + * This routine initializes paging which enables MMU. + * + * This is effectively the same algorithm from xtensa_mmu_set_paging(), * but it also disables the hardware-initialized 512M TLB entries in * way 6 (because the hardware disallows duplicate TLB mappings). For * instruction fetches this produces a critical ordering constraint: diff --git a/arch/xtensa/core/ptables.c b/arch/xtensa/core/ptables.c index a78609b3ba18..2a5db93b4c93 100644 --- a/arch/xtensa/core/ptables.c +++ b/arch/xtensa/core/ptables.c @@ -126,36 +126,49 @@ #define PAGE_TABLE_IS_CACHED 1 #endif -/* Skip TLB IPI when updating page tables. +/** + * @brief Option to skip TLB IPI when updating page tables. + * + * Skip TLB IPI when updating page tables. + * * This allows us to send IPI only after the last * changes of a series. */ #define OPTION_NO_TLB_IPI BIT(0) -/* Restore the PTE attributes if they have been +/** + * @brief Option to restore PTE attributes. + * + * Restore the PTE attributes if they have been * stored in the SW bits part in the PTE. */ #define OPTION_RESTORE_ATTRS BIT(1) -/* Save the PTE attributes and ring in the SW bits part in the PTE. */ +/** + * @brief Option to save PTE attributes. + * + * Save the PTE attributes and ring in the SW bits part in the PTE. + */ #define OPTION_SAVE_ATTRS BIT(2) -/* Level 1 contains page table entries - * necessary to map the page table itself. +/** + * @brief Number of page table entries (PTE) in level 1 page tables. + * + * Level 1 contains page table entries necessary to map the page table itself. */ #define L1_PAGE_TABLE_NUM_ENTRIES 1024U -/* Size of level 1 page table. - */ +/** Size of one level 1 page table in bytes. */ #define L1_PAGE_TABLE_SIZE (L1_PAGE_TABLE_NUM_ENTRIES * sizeof(uint32_t)) -/* Level 2 contains page table entries - * necessary to map the page table itself. +/** + * @brief Number of page table entries (PTE) in level 2 page tables. + * + * Level 2 contains page table entries necessary to map memory pages. */ #define L2_PAGE_TABLE_NUM_ENTRIES 1024U -/* Size of level 2 page table. - */ +/** Size of one level 2 page table in bytes. */ #define L2_PAGE_TABLE_SIZE (L2_PAGE_TABLE_NUM_ENTRIES * sizeof(uint32_t)) LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); @@ -163,7 +176,9 @@ LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); BUILD_ASSERT(CONFIG_MMU_PAGE_SIZE == 0x1000, "MMU_PAGE_SIZE value is invalid, only 4 kB pages are supported\n"); -/* +/** + * @brief Array of level 1 page tables. + * * Level 1 page table has to be 4Kb to fit into one of the wired entries. * All entries are initialized as INVALID, so an attempt to read an unmapped * area will cause a double exception. @@ -174,19 +189,25 @@ BUILD_ASSERT(CONFIG_MMU_PAGE_SIZE == 0x1000, static uint32_t l1_page_tables[CONFIG_XTENSA_MMU_NUM_L1_TABLES][L1_PAGE_TABLE_NUM_ENTRIES] __aligned(KB(4)); -/* - * That is an alias for the page tables set used by the kernel. +/** + * @brief Alias for the page tables set used by the kernel. */ uint32_t *xtensa_kernel_ptables = (uint32_t *)l1_page_tables[0]; -/* +/** + * @brief Array of level 2 page tables. + * * Each table in the level 2 maps a 4Mb memory range. It consists of 1024 entries each one * covering a 4Kb page. */ static uint32_t l2_page_tables[CONFIG_XTENSA_MMU_NUM_L2_TABLES][L2_PAGE_TABLE_NUM_ENTRIES] __aligned(KB(4)); -/* +/** + * @brief Usage tracking for level 1 page tables. + * + * This is a bit mask of which L1 tables are being used. + * * This additional variable tracks which l1 tables are in use. This is kept separated from * the tables to keep alignment easier. * @@ -194,7 +215,12 @@ static uint32_t l2_page_tables[CONFIG_XTENSA_MMU_NUM_L2_TABLES][L2_PAGE_TABLE_NU */ static ATOMIC_DEFINE(l1_page_tables_track, CONFIG_XTENSA_MMU_NUM_L1_TABLES); -/* +/** + * @brief Usage tracking for level 2 page tables. + * + * This is an array of integer counter indicating how many times one L2 tables is + * referenced by L1 tables. + * * This additional variable tracks which l2 tables are in use. This is kept separated from * the tables to keep alignment easier. */ @@ -208,9 +234,7 @@ static uint32_t l1_page_tables_max_usage; static uint32_t l2_page_tables_max_usage; #endif /* CONFIG_XTENSA_MMU_PAGE_TABLE_STATS */ -/* - * Protects xtensa_domain_list and serializes access to page tables. - */ +/** Spin lock to protect xtensa_domain_list and serializes access to page tables. */ static struct k_spinlock xtensa_mmu_lock; /** Spin lock to guard update to page table counters. */ @@ -218,19 +242,22 @@ static struct k_spinlock xtensa_counter_lock; #ifdef CONFIG_USERSPACE -/* +/** + * @brief Number of ASIDs has been allocated. + * * Each domain has its own ASID. ASID can go through 1 (kernel) to 255. * When a TLB entry matches, the hw will check the ASID in the entry and finds * the correspondent position in the RASID register. This position will then be * compared with the current ring (CRING) to check the permission. + * + * This keeps track of how many ASIDs have been allocated for memory domains. */ static uint8_t asid_count = 3; -/* - * List with all active and initialized memory domains. - */ +/** Linked list with all active and initialized memory domains. */ static sys_slist_t xtensa_domain_list; +/** Actions when duplicating page tables. */ enum dup_action { /* Restore all entries when duplicating. */ RESTORE, @@ -246,7 +273,9 @@ static void dup_l2_table_if_needed(uint32_t *l1_table, uint32_t l1_pos, enum dup extern char _heap_end[]; extern char _heap_start[]; -/* +/** + * @brief Memory regions to initialize page tables at boot. + * * Static definition of all code & data memory regions of the * current Zephyr image. This information must be available & * processed upon MMU initialization. @@ -326,6 +355,26 @@ static void init_page_table(uint32_t *ptable, size_t num_entries, uint32_t val) } } +static void calc_l2_page_tables_usage(void) +{ +#ifdef CONFIG_XTENSA_MMU_PAGE_TABLE_STATS + uint32_t cur_l2_usage = 0; + + /* Calculate how many L2 page tables are being used now. */ + for (int idx = 0; idx < CONFIG_XTENSA_MMU_NUM_L2_TABLES; idx++) { + if (l2_page_tables_counter[idx] > 0) { + cur_l2_usage++; + } + } + + /* Store the bigger number. */ + l2_page_tables_max_usage = MAX(l2_page_tables_max_usage, cur_l2_usage); + + LOG_DBG("L2 page table usage %u/%u/%u", cur_l2_usage, l2_page_tables_max_usage, + CONFIG_XTENSA_MMU_NUM_L2_TABLES); +#endif /* CONFIG_XTENSA_MMU_PAGE_TABLE_STATS */ +} + /** * @brief Find the L2 table counter array index from L2 table pointer. * @@ -341,6 +390,14 @@ static inline int l2_table_to_counter_pos(uint32_t *l2_table) return (l2_table - (uint32_t *)l2_page_tables) / (L2_PAGE_TABLE_NUM_ENTRIES); } +/** + * @brief Allocate a level 2 page table from the L2 table array. + * + * This allocates a new level 2 page table from the L2 table array. + * + * @return Pointer to the newly allocated L2 table. NULL if no free table + * in the array. + */ static inline uint32_t *alloc_l2_table(void) { uint16_t idx; @@ -357,25 +414,23 @@ static inline uint32_t *alloc_l2_table(void) } } -#ifdef CONFIG_XTENSA_MMU_PAGE_TABLE_STATS - uint32_t cur_l2_usage = 0; - - /* Calculate how many L2 page tables are being used now. */ - for (idx = 0; idx < CONFIG_XTENSA_MMU_NUM_L2_TABLES; idx++) { - if (l2_page_tables_counter[idx] > 0) { - cur_l2_usage++; - } - } - - /* Store the bigger number. */ - l2_page_tables_max_usage = MAX(l2_page_tables_max_usage, cur_l2_usage); -#endif /* CONFIG_XTENSA_MMU_PAGE_TABLE_STATS */ + calc_l2_page_tables_usage(); k_spin_unlock(&xtensa_counter_lock, key); return ret; } +/** + * @brief Map memory in the kernel page tables. + * + * This is used during boot, and is to map a region of memory in the kernel page tables. + * + * @param[in] start Start address of the memory region. + * @param[in] end End address of the memory region. + * @param[in] attrs Page table attributes for the memory region. + * @param[in] options Options for the memory region. + */ static void map_memory_range(const uint32_t start, const uint32_t end, const uint32_t attrs, const uint32_t options) { @@ -399,6 +454,15 @@ static void map_memory_range(const uint32_t start, const uint32_t end, __ASSERT(l2_table != NULL, "There is no l2 page table available to map 0x%08x\n", page); + if (l2_table == NULL) { + /* This function is called during boot. If this cannot + * properly map all predefined memory regions, it is very + * unlikely for anything to run correctly. So forcibly + * halt the system in case assertion has been turned off. + */ + arch_system_halt(K_ERR_KERNEL_PANIC); + } + init_page_table(l2_table, L2_PAGE_TABLE_NUM_ENTRIES, PTE_L2_ILLEGAL); xtensa_kernel_ptables[l1_pos] = @@ -494,14 +558,15 @@ void xtensa_mmu_reinit(void) } #ifdef CONFIG_ARCH_HAS_RESERVED_PAGE_FRAMES -/* Zephyr's linker scripts for Xtensa usually puts - * something before z_mapped_start (aka .text), - * i.e. vecbase, so that we need to reserve those - * space or else k_mem_map() would be mapping those, - * resulting in faults. - */ __weak void arch_reserved_pages_update(void) { + /* Zephyr's linker scripts for Xtensa usually puts + * something before z_mapped_start (aka .text), + * i.e. vecbase, so that we need to reserve those + * space or else k_mem_map() would be mapping those, + * resulting in faults. + */ + uintptr_t page; int idx; @@ -513,6 +578,22 @@ __weak void arch_reserved_pages_update(void) } #endif /* CONFIG_ARCH_HAS_RESERVED_PAGE_FRAMES */ +/** + * @brief Map one memory page in the L2 table. + * + * This maps exactly one memory page in the L2 table. + * + * A new L2 table will be allocated if necessary. + * + * @param[in] l1_table Pointer to the level 1 page table. + * @param[in] vaddr Virtual address to be mapped. + * @param[in] phys Physical address to map to. + * @param[in] attrs Page table attributes (actual hardware attributes). + * @param[in] is_user True if this mapping can be used in user mode, false if kernel mode only. + * + * @retval true Mapping is successful. + * @retval false Mapping failed. Usually means there are no free L2 tables to be allocated. + */ static bool l2_page_table_map(uint32_t *l1_table, void *vaddr, uintptr_t phys, uint32_t attrs, bool is_user) { @@ -557,12 +638,23 @@ static bool l2_page_table_map(uint32_t *l1_table, void *vaddr, uintptr_t phys, return true; } +/** + * @brief Called by @ref arch_mem_map to map one memory page. + * + * @see arch_mem_map + * + * This should only be called by @ref arch_mem_map to perform the mapping in the L2 tables. + * + * @param[in] vaddr Virtual address to be mapped. + * @param[in] paddr Physical address to map to. + * @param[in] attrs Page table attributes (actual hardware attributes). + * @param[in] is_user True if mapping for user mode, false if kernel mode only. + */ static inline void __arch_mem_map(void *vaddr, uintptr_t paddr, uint32_t attrs, bool is_user) { bool ret; - ret = l2_page_table_map(xtensa_kernel_ptables, (void *)vaddr, paddr, - attrs, is_user); + ret = l2_page_table_map(xtensa_kernel_ptables, vaddr, paddr, attrs, is_user); __ASSERT(ret, "Cannot map virtual address (%p)", vaddr); #ifndef CONFIG_USERSPACE @@ -577,8 +669,7 @@ static inline void __arch_mem_map(void *vaddr, uintptr_t paddr, uint32_t attrs, SYS_SLIST_FOR_EACH_NODE(&xtensa_domain_list, node) { domain = CONTAINER_OF(node, struct arch_mem_domain, node); - ret = l2_page_table_map(domain->ptables, (void *)vaddr, paddr, - attrs, is_user); + ret = l2_page_table_map(domain->ptables, vaddr, paddr, attrs, is_user); __ASSERT(ret, "Cannot map virtual address (%p) for domain %p", vaddr, domain); @@ -718,6 +809,8 @@ static void l2_page_table_unmap(uint32_t *l1_table, void *vaddr) K_SPINLOCK(&xtensa_counter_lock) { l2_page_tables_counter_dec(l2_table); + + calc_l2_page_tables_usage(); } end: @@ -728,9 +821,18 @@ static void l2_page_table_unmap(uint32_t *l1_table, void *vaddr) } } +/** + * @brief Called by @ref arch_mem_unmap to unmap one memory page. + * + * @see arch_mem_unmap + * + * This should only be called by @ref arch_mem_unmap to remove the mapping in the L2 tables. + * + * @param[in] vaddr Virtual address to be unmapped. + */ static inline void __arch_mem_unmap(void *vaddr) { - l2_page_table_unmap(xtensa_kernel_ptables, (void *)vaddr); + l2_page_table_unmap(xtensa_kernel_ptables, vaddr); #ifdef CONFIG_USERSPACE sys_snode_t *node; @@ -741,7 +843,7 @@ static inline void __arch_mem_unmap(void *vaddr) SYS_SLIST_FOR_EACH_NODE(&xtensa_domain_list, node) { domain = CONTAINER_OF(node, struct arch_mem_domain, node); - (void)l2_page_table_unmap(domain->ptables, (void *)vaddr); + (void)l2_page_table_unmap(domain->ptables, vaddr); } k_spin_unlock(&z_mem_domain_lock, key); #endif /* CONFIG_USERSPACE */ @@ -899,6 +1001,11 @@ static bool is_l2_table_inside_array(uint32_t *l2_table) return (addr >= l2_table_begin) && (addr < l2_table_end); } +/** + * @brief Increment the tracking counter for one L2 table. + * + * @param[in] l2_table Pointer to the level 2 page table. + */ static ALWAYS_INLINE void l2_page_tables_counter_inc(uint32_t *l2_table) { if (is_l2_table_inside_array(l2_table)) { @@ -906,6 +1013,11 @@ static ALWAYS_INLINE void l2_page_tables_counter_inc(uint32_t *l2_table) } } +/** + * @brief Decrement the tracking counter for one L2 table. + * + * @param[in] l2_table Pointer to the level 2 page table. + */ static ALWAYS_INLINE void l2_page_tables_counter_dec(uint32_t *l2_table) { if (is_l2_table_inside_array(l2_table)) { @@ -915,6 +1027,13 @@ static ALWAYS_INLINE void l2_page_tables_counter_dec(uint32_t *l2_table) #ifdef CONFIG_USERSPACE +/** + * @brief Get the page table for the thread. + * + * @param[in] thread Pointer to the thread object. + * + * @return Pointer to the L1 table corresponding to the thread. + */ static inline uint32_t *thread_page_tables_get(const struct k_thread *thread) { if ((thread->base.user_options & K_USER) != 0U) { @@ -924,6 +1043,14 @@ static inline uint32_t *thread_page_tables_get(const struct k_thread *thread) return xtensa_kernel_ptables; } +/** + * @brief Allocate a level 1 page table from the L1 table array. + * + * This allocates a new level 1 page table from the L1 table array. + * + * @return Pointer to the newly allocated L2 table. NULL if no free table + * in the array. + */ static inline uint32_t *alloc_l1_table(void) { uint16_t idx; @@ -948,16 +1075,19 @@ static inline uint32_t *alloc_l1_table(void) /* Store the bigger number. */ l1_page_tables_max_usage = MAX(l1_page_tables_max_usage, cur_l1_usage); + + LOG_DBG("L1 page table usage %u/%u/%u", cur_l1_usage, l1_page_tables_max_usage, + CONFIG_XTENSA_MMU_NUM_L1_TABLES); #endif /* CONFIG_XTENSA_MMU_PAGE_TABLE_STATS */ return ret; } /** - * Given page table position, calculate the corresponding virtual address. + * @brief Given page table position, calculate the corresponding virtual address. * - * @param l1_pos Position in L1 page table. - * @param l2_pos Position in L2 page table. + * @param[in] l1_pos Position in L1 page table. + * @param[in] l2_pos Position in L2 page table. * @return Virtual address. */ static ALWAYS_INLINE uint32_t vaddr_from_pt_pos(uint32_t l1_pos, uint32_t l2_pos) @@ -965,13 +1095,32 @@ static ALWAYS_INLINE uint32_t vaddr_from_pt_pos(uint32_t l1_pos, uint32_t l2_pos return (l1_pos << 22U) | (l2_pos << 12U); } +/** + * @brief Duplicate an existing level 2 page table. + * + * This allocates a new level 2 page table and duplicates the PTEs from an existing + * L2 table. + * + * @param[in] src_l2_table Pointer to the source L2 table to be duplicated. + * @param[in] action Action during duplication. + * RESTORE to restore PTEs to the attributes stored in the backup bits. + * COPY to copy PTEs from source without modifications. + * + * @return Pointer to the newly duplicated L2 table. NULL if table allocation fails. + */ static uint32_t *dup_l2_table(uint32_t *src_l2_table, enum dup_action action) { uint32_t *l2_table; l2_table = alloc_l2_table(); + + /* Duplicating L2 tables is a must-have and must-success operation. + * If we are running out of free L2 tables to be allocated, we cannot + * continue. + */ + __ASSERT_NO_MSG(l2_table != NULL); if (l2_table == NULL) { - return NULL; + arch_system_halt(K_ERR_KERNEL_PANIC); } switch (action) { @@ -994,6 +1143,14 @@ static uint32_t *dup_l2_table(uint32_t *src_l2_table, enum dup_action action) return l2_table; } +/** + * @brief Duplicate the kernel page table into a new level 1 page table. + * + * This allocates a new level 1 page table and copy the PTEs from the kernel + * page table. + * + * @return Pointer to the newly duplicated L1 table. NULL if table allocation fails. + */ static uint32_t *dup_l1_table(void) { uint32_t *l1_table = alloc_l1_table(); @@ -1064,6 +1221,26 @@ static uint32_t *dup_l1_table(void) return l1_table; } +/** + * @brief Duplicate an existing level 2 page table if needed. + * + * If a L2 table is referenced by multiple L1 tables, we need to make a copy of + * the existing L2 table and modify the new table, basically a copy-on-write + * operation. + * + * If a new L2 table needs to be allocated, the corresponding PTE in the L1 table + * will be modified to point to the new table. + * + * If the L2 table is only referenced by exactly one L1 table, no duplication + * will be performed. + * + * @param[in] l1_table Pointer to the level 1 page table. + * @param[in] l1_pos Index of the PTE within the L1 table pointing to the L2 table + * to be examined. + * @param[in] action Action during duplication. + * RESTORE to restore PTEs to the attributes stored in the backup bits. + * COPY to copy PTEs from source without modifications. + */ static void dup_l2_table_if_needed(uint32_t *l1_table, uint32_t l1_pos, enum dup_action action) { uint32_t *l2_table, *src_l2_table; @@ -1139,8 +1316,22 @@ int arch_mem_domain_init(struct k_mem_domain *domain) return ret; } +/** + * @brief Update the mappings of a memory region. + * + * @note This does not lock the necessary spin locks to prevent simultaneous updates + * to the page tables. Use @ref update_region instead if locking is desired. + * + * @param[in] l1_table Pointer to the L1 table. + * @param[in] start Starting virtual address of the memory region to be updated. + * @param[in] size Size of the memory region to be updated. + * @param[in] ring Ring value to set to. + * @param[in] attrs Page table attributes to set to (not used if option is RESTORE). + * @param[in] option Option for the memory region. + * OPTION_RESTORE_ATTRS will restore the attributes from the backup bits. + */ static void region_map_update(uint32_t *l1_table, uintptr_t start, - size_t size, uint32_t ring, uint32_t flags, uint32_t option) + size_t size, uint32_t ring, uint32_t attrs, uint32_t option) { for (size_t offset = 0; offset < size; offset += CONFIG_MMU_PAGE_SIZE) { uint32_t *l2_table, pte; @@ -1171,7 +1362,7 @@ static void region_map_update(uint32_t *l1_table, uintptr_t start, new_attrs = PTE_BCKUP_ATTR_GET(pte); new_ring = PTE_BCKUP_RING_GET(pte); } else { - new_attrs = flags; + new_attrs = attrs; new_ring = ring; } @@ -1188,14 +1379,28 @@ static void region_map_update(uint32_t *l1_table, uintptr_t start, } } +/** + * @brief Update the attributes of the memory region. + * + * @note This locks the necessary spin locks to prevent simultaneous updates + * to the page tables. + * + * @param[in] ptables Pointer to the L1 table. + * @param[in] start Starting virtual address of the memory region to be updated. + * @param[in] size Size of the memory region to be updated. + * @param[in] ring Ring value to set to. + * @param[in] attrs Page table attributes to set to (not used if option is RESTORE). + * @param[in] option Option for the memory region. + * OPTION_RESTORE_ATTRS will restore the attributes from the backup bits. + */ static void update_region(uint32_t *ptables, uintptr_t start, size_t size, - uint32_t ring, uint32_t flags, uint32_t option) + uint32_t ring, uint32_t attrs, uint32_t option) { k_spinlock_key_t key; key = k_spin_lock(&xtensa_mmu_lock); - region_map_update(ptables, start, size, ring, flags, option); + region_map_update(ptables, start, size, ring, attrs, option); #if CONFIG_MP_MAX_NUM_CPUS > 1 if ((option & OPTION_NO_TLB_IPI) != OPTION_NO_TLB_IPI) { @@ -1209,6 +1414,22 @@ static void update_region(uint32_t *ptables, uintptr_t start, size_t size, k_spin_unlock(&xtensa_mmu_lock, key); } +/** + * @brief Reset the attributes of the memory region. + * + * This restores the ring and PTE attributes to the backup bits. + * Usually this restores the PTEs corresponding to the memory region to + * the ring and attributes at boot time just before MMU is enabled. + * + * @note This calls @ref update_region which locks the necessary spin locks to + * prevent simultaneous updates to the page tables. + * + * @param[in] ptables Pointer to the L1 table. + * @param[in] start Starting virtual address of the memory region to be updated. + * @param[in] size Size of the memory region to be updated. + * @param[in] option Option for the memory region. + * OPTION_RESTORE_ATTRS will restore the attributes from the backup bits. + */ static inline void reset_region(uint32_t *ptables, uintptr_t start, size_t size, uint32_t option) { update_region(ptables, start, size, RING_KERNEL, XTENSA_MMU_PERM_W, @@ -1260,7 +1481,6 @@ int arch_mem_domain_partition_add(struct k_mem_domain *domain, return 0; } -/* These APIs don't need to do anything */ int arch_mem_domain_thread_add(struct k_thread *thread) { bool is_user, is_migration; @@ -1345,6 +1565,17 @@ int arch_mem_domain_thread_remove(struct k_thread *thread) return 0; } +/** + * @brief Check if a page can be legally accessed. + * + * @param[in] ptables Pointer to the level 1 page table. + * @param[in] page Virtual address of the page to be checked. + * @param[in] ring Ring value for the access. + * @param[in] write True if the access needs to write to this page, false if read only. + * + * @retval true Access is legal. + * @retval false Access is not legal and will probably generate page fault. + */ static bool page_validate(uint32_t *ptables, uint32_t page, uint8_t ring, bool write) { uint8_t asid_ring; @@ -1383,6 +1614,20 @@ static bool page_validate(uint32_t *ptables, uint32_t page, uint8_t ring, bool w return true; } +/** + * @brief Check if a memory region can be legally accessed. + * + * @param[in] ptables Pointer to the level 1 page table. + * @param[in] addr Start virtual address of the memory region to be checked. + * @param[in] size Size of the memory region to be checked. + * @param[in] write True if the access needs to write to this page, false if read only. + * @param[in] ring Ring value for the access. + * + * @retval 0 Access is legal. + * @retval -1 Access is not legal and will probably generate page fault. + * + * @see arch_buffer_validate + */ static int mem_buffer_validate(const void *addr, size_t size, int write, int ring) { int ret = 0; @@ -1416,14 +1661,56 @@ int arch_buffer_validate(const void *addr, size_t size, int write) return mem_buffer_validate(addr, size, write, RING_USER); } -void xtensa_exc_dtlb_multihit_handle(void) +void xtensa_exc_dtlb_multihit_handle(void *vaddr) { - /* For some unknown reasons, using xtensa_dtlb_probe() would result in - * QEMU raising privileged instruction exception. So for now, just - * invalidate all auto-refilled DTLBs. + uint8_t way, i; + const uint8_t num_entries = BIT(XCHAL_DTLB_ARF_ENTRIES_LOG2); + + /* Each auto-refill way has a number of entries (4 or 8 depending on + * configuration). So we need to ignore the lowest bits of + * the virtual page number (VPN) to match the truncated VPN in + * each TLB entry. */ + const uint32_t excvaddr = + (uint32_t)vaddr & (XTENSA_MMU_PTE_VPN_MASK << XCHAL_DTLB_ARF_ENTRIES_LOG2); - xtensa_dtlb_autorefill_invalidate(); + for (way = 0; way < XTENSA_MMU_NUM_TLB_AUTOREFILL_WAYS; way++) { + for (i = 0; i < num_entries; i++) { + uint32_t entry = way + (i << XTENSA_MMU_PTE_PPN_SHIFT); + uint32_t tlb_vaddr = (uint32_t)xtensa_dtlb_vaddr_read(entry); + + if (tlb_vaddr == excvaddr) { + xtensa_dtlb_entry_invalidate(entry); + } + } + } + __asm__ volatile("isync"); +} + +void xtensa_exc_itlb_multihit_handle(void *vaddr) +{ + uint8_t way, i; + const uint8_t num_entries = BIT(XCHAL_ITLB_ARF_ENTRIES_LOG2); + + /* Each auto-refill way has a number of entries (4 or 8 depending on + * configuration). So we need to ignore the lowest bits of + * the virtual page number (VPN) to match the truncated VPN in + * each TLB entry. + */ + const uint32_t excvaddr = + (uint32_t)vaddr & (XTENSA_MMU_PTE_VPN_MASK << XCHAL_ITLB_ARF_ENTRIES_LOG2); + + for (way = 0; way < XTENSA_MMU_NUM_TLB_AUTOREFILL_WAYS; way++) { + for (i = 0; i < num_entries; i++) { + uint32_t entry = way + (i << XTENSA_MMU_PTE_PPN_SHIFT); + uint32_t tlb_vaddr = (uint32_t)xtensa_itlb_vaddr_read(entry); + + if (tlb_vaddr == excvaddr) { + xtensa_itlb_entry_invalidate(entry); + } + } + } + __asm__ volatile("isync"); } bool xtensa_exc_load_store_ring_error_check(void *bsa_p) diff --git a/arch/xtensa/core/vector_handlers.c b/arch/xtensa/core/vector_handlers.c index 0b66863ef59f..9c188e37ae01 100644 --- a/arch/xtensa/core/vector_handlers.c +++ b/arch/xtensa/core/vector_handlers.c @@ -16,7 +16,6 @@ #include #include -#include #include #include @@ -632,12 +631,16 @@ void *xtensa_excint1_c(void *esf) break; #endif /* CONFIG_XTENSA_LAZY_HIFI_SHARING */ #if defined(CONFIG_XTENSA_MMU) && defined(CONFIG_USERSPACE) + case EXCCAUSE_ITLB_MULTIHIT: + xtensa_exc_itlb_multihit_handle((void *)bsa->excvaddr); + goto return_to_interrupted; case EXCCAUSE_DTLB_MULTIHIT: - xtensa_exc_dtlb_multihit_handle(); + xtensa_exc_dtlb_multihit_handle((void *)bsa->excvaddr); + goto return_to_interrupted; break; case EXCCAUSE_LOAD_STORE_RING: if (!xtensa_exc_load_store_ring_error_check(bsa)) { - break; + goto return_to_interrupted; } __fallthrough; #endif /* CONFIG_XTENSA_MMU && CONFIG_USERSPACE */ @@ -705,23 +708,6 @@ void *xtensa_excint1_c(void *esf) break; } -#ifdef CONFIG_XTENSA_MMU - switch (cause) { - case EXCCAUSE_LEVEL1_INTERRUPT: -#ifndef CONFIG_USERSPACE - case EXCCAUSE_SYSCALL: -#endif /* !CONFIG_USERSPACE */ -#ifdef CONFIG_XTENSA_LAZY_HIFI_SHARING - case EXCCAUSE_CP_DISABLED(XCHAL_CP_ID_AUDIOENGINELX): -#endif /* CONFIG_XTENSA_LAZY_HIFI_SHARING */ - is_fatal_error = false; - break; - default: - is_fatal_error = true; - break; - } -#endif /* CONFIG_XTENSA_MMU */ - if (is_dblexc || is_fatal_error) { uint32_t ignore; @@ -758,6 +744,15 @@ void *xtensa_excint1_c(void *esf) #endif /* CONFIG_XTENSA_MMU */ return return_to(interrupted_stack); + +#if defined(CONFIG_XTENSA_MMU) && defined(CONFIG_USERSPACE) +return_to_interrupted: + if (is_dblexc) { + XTENSA_WSR(ZSR_DEPC_SAVE_STR, 0); + } + + return interrupted_stack; +#endif /* CONFIG_XTENSA_MMU && CONFIG_USERSPACE */ } #if defined(CONFIG_GDBSTUB) diff --git a/arch/xtensa/core/xtensa_asm2_util.S b/arch/xtensa/core/xtensa_asm2_util.S index 24893db692dc..377edcd590ab 100644 --- a/arch/xtensa/core/xtensa_asm2_util.S +++ b/arch/xtensa/core/xtensa_asm2_util.S @@ -344,7 +344,7 @@ noflush: /* Switch stack pointer and restore. The jump to * _restore_context does not return as such, but we arrange * for the restored "next" address to be immediately after for - * sanity. + * coherence. */ l32i a1, a2, ___xtensa_irq_bsa_t_a2_OFFSET @@ -580,6 +580,10 @@ _handle_tlb_miss_dblexc: rsr.ptevaddr a0 l32i a0, a0, 0 + /* Restore EXCCAUSE and a0 values */ + rsr a0, ZSR_EXCCAUSE_SAVE + wsr.exccause a0 + rsr a0, ZSR_DBLEXC rfde #endif diff --git a/arch/xtensa/include/kernel_arch_func.h b/arch/xtensa/include/kernel_arch_func.h index a53a81cb71cb..ffd12c740dce 100644 --- a/arch/xtensa/include/kernel_arch_func.h +++ b/arch/xtensa/include/kernel_arch_func.h @@ -26,9 +26,7 @@ K_KERNEL_STACK_ARRAY_DECLARE(z_interrupt_stacks, CONFIG_MP_MAX_NUM_CPUS, static ALWAYS_INLINE void arch_kernel_init(void) { -#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK soc_per_core_init_hook(); -#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */ } void xtensa_switch(void *switch_to, void **switched_from); diff --git a/arch/xtensa/include/xtensa_asm2.inc.S b/arch/xtensa/include/xtensa_asm2.inc.S index 9d8ce2bf7b8a..89582d1abb88 100644 --- a/arch/xtensa/include/xtensa_asm2.inc.S +++ b/arch/xtensa/include/xtensa_asm2.inc.S @@ -677,17 +677,20 @@ _Level\LVL\()Vector: .if \LVL == 1 /* If there are any TLB misses during interrupt handling, * the user/kernel/double exception vector will be triggered - * to handle these misses. This results in DEPC and EXCCAUSE - * being overwritten, and then execution returned back to - * this site of TLB misses. When it gets to the C handler, - * it will not see the original cause. So stash - * the EXCCAUSE here so C handler can see the original cause. + * to handle these misses. This results in DEPC, EXCCAUSE + * and EXCVADDR being overwritten, and then execution returned + * back to this site of TLB misses. When it gets to the C handler, + * it will not see the original cause. So stash the EXCCAUSE + * and EXCVADDR here so C handler can see the original cause. * * For double exception, DEPC in saved in earlier vector * code. */ wsr a0, ZSR_A0SAVE + rsr.exccause a0 + wsr a0, ZSR_EXCCAUSE_SAVE + esync rsr a0, ZSR_DEPC_SAVE @@ -717,24 +720,41 @@ _Level\LVL\()Vector: j _TripleFault _not_triple_fault: - rsr a0, ZSR_A0SAVE .endif #endif addi a1, a1, -___xtensa_irq_bsa_t_SIZEOF + +#ifdef CONFIG_XTENSA_MMU +.if \LVL == 1 + /* Save EXCVADDR register needed for handling the exception + * as this register can be overwritten during nested + * exceptions. It has to be saved first, because + * executing the store instruction may trigger a + * TLB miss, which will modify its value. + */ + rsr.excvaddr a0 + s32i a0, a1, ___xtensa_irq_bsa_t_excvaddr_OFFSET + rsr a0, ZSR_A0SAVE +.endif +#endif + s32i a0, a1, ___xtensa_irq_bsa_t_a0_OFFSET s32i a2, a1, ___xtensa_irq_bsa_t_a2_OFFSET s32i a3, a1, ___xtensa_irq_bsa_t_a3_OFFSET - /* Save registers needed for handling the exception as - * these registers can be overwritten during nested +#ifdef CONFIG_XTENSA_MMU +.if \LVL != 1 +#endif + /* Save register needed for handling the exception as + * this register can be overwritten during nested * exceptions. */ - rsr.exccause a0 - s32i a0, a1, ___xtensa_irq_bsa_t_exccause_OFFSET - rsr.excvaddr a0 s32i a0, a1, ___xtensa_irq_bsa_t_excvaddr_OFFSET +#ifdef CONFIG_XTENSA_MMU +.endif +#endif /* Level "1" is the exception handler, which uses a different * calling convention. No special register holds the diff --git a/arch/xtensa/include/xtensa_internal.h b/arch/xtensa/include/xtensa_internal.h index c56e1068afe3..815ab6460c69 100644 --- a/arch/xtensa/include/xtensa_internal.h +++ b/arch/xtensa/include/xtensa_internal.h @@ -77,10 +77,22 @@ bool xtensa_mem_kernel_has_access(const void *addr, size_t size, int write); /** * @brief Handle DTLB multihit exception. * - * Handle DTLB multihit exception by invalidating all auto-refilled DTLBs of + * Handle DTLB multihit exception by invalidating auto-refilled DTLBs of * a particular memory page. + * + * @param[in] vaddr Virtual address of data TLB to be invalidated. + */ +void xtensa_exc_dtlb_multihit_handle(void *vaddr); + +/** + * @brief Handle ITLB multihit exception. + * + * Handle ITLB multihit exception by invalidating all auto-refilled ITLBs of + * a particular memory page. + * + * @param[in] vaddr Virtual address of ITLB to be invalidated. */ -void xtensa_exc_dtlb_multihit_handle(void); +void xtensa_exc_itlb_multihit_handle(void *vaddr); /** * @brief Check if it is a true load/store ring exception. diff --git a/arch/xtensa/include/xtensa_mmu_priv.h b/arch/xtensa/include/xtensa_mmu_priv.h index 1f899a1c1242..ec8faf9b7a91 100644 --- a/arch/xtensa/include/xtensa_mmu_priv.h +++ b/arch/xtensa/include/xtensa_mmu_priv.h @@ -322,6 +322,28 @@ static inline void xtensa_dtlb_autorefill_invalidate(void) __asm__ volatile("isync"); } +/** + * @brief Invalidate all autorefill ITLB entries. + * + * This should be used carefully since all refill entries in + * the instruction TLBs are affected. + */ +static inline void xtensa_itlb_autorefill_invalidate(void) +{ + uint8_t way, i, entries; + + entries = BIT(XCHAL_ITLB_ARF_ENTRIES_LOG2); + + for (way = 0; way < XTENSA_MMU_NUM_TLB_AUTOREFILL_WAYS; way++) { + for (i = 0; i < entries; i++) { + uint32_t entry = way + (i << XTENSA_MMU_PTE_PPN_SHIFT); + + xtensa_itlb_entry_invalidate(entry); + } + } + __asm__ volatile("isync"); +} + /** * @brief Set the page tables. * diff --git a/boards/01space/esp32c3_042_oled/esp32c3_042_oled.dts b/boards/01space/esp32c3_042_oled/esp32c3_042_oled.dts index 70f83f398e75..d7c3b0960373 100644 --- a/boards/01space/esp32c3_042_oled/esp32c3_042_oled.dts +++ b/boards/01space/esp32c3_042_oled/esp32c3_042_oled.dts @@ -48,7 +48,7 @@ pinctrl-names = "default"; eastrising_72x40: ssd1306@3c { - compatible = "solomon,ssd1306fb"; + compatible = "solomon,ssd1306"; reg = <0x3c>; width = <72>; diff --git a/boards/01space/esp32c3_042_oled/support/openocd.cfg b/boards/01space/esp32c3_042_oled/support/openocd.cfg index 7421637880c7..cf1bc91bbf9f 100644 --- a/boards/01space/esp32c3_042_oled/support/openocd.cfg +++ b/boards/01space/esp32c3_042_oled/support/openocd.cfg @@ -1,4 +1,4 @@ -set ESP_RTOS none +set ESP_RTOS Zephyr source [find interface/esp_usb_jtag.cfg] diff --git a/boards/96boards/aerocore2/96b_aerocore2.dts b/boards/96boards/aerocore2/96b_aerocore2.dts index 339f61df6e03..225e99c0f8cc 100644 --- a/boards/96boards/aerocore2/96b_aerocore2.dts +++ b/boards/96boards/aerocore2/96b_aerocore2.dts @@ -18,7 +18,7 @@ zephyr,shell-uart = &uart7; zephyr,sram = &sram0; zephyr,flash = &flash0; - zephyr,ccm = &ccm0; + zephyr,dtcm = &ccm0; }; leds { diff --git a/boards/96boards/aerocore2/doc/index.rst b/boards/96boards/aerocore2/doc/index.rst index 489433e09f3b..ca7daa75cc04 100644 --- a/boards/96boards/aerocore2/doc/index.rst +++ b/boards/96boards/aerocore2/doc/index.rst @@ -24,7 +24,7 @@ Hardware 96Boards Aerocore2 provides the following hardware components: - STM32F427VIT6 in LQFP100 package -- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU +- ARM® 32-bit Cortex®-M4 CPU with FPU - 168 MHz max CPU frequency - VDD from 1.7 V to 3.6 V - 2048 KB Flash @@ -43,7 +43,8 @@ Hardware - DMA Controller More information about STM32F427VIT6 can be found here: - - `STM32F427 on www.st.com`_ + +- `STM32F427 on www.st.com`_ Supported Features ================== diff --git a/boards/96boards/argonkey/doc/index.rst b/boards/96boards/argonkey/doc/index.rst index f5cc913f3909..95a3e104f965 100644 --- a/boards/96boards/argonkey/doc/index.rst +++ b/boards/96boards/argonkey/doc/index.rst @@ -24,7 +24,7 @@ Hardware 96Boards Argonkey provides the following hardware components: - STM32F412CG in UFQFPN48 package -- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU +- ARM® 32-bit Cortex®-M4 CPU with FPU - 100 MHz max CPU frequency - 1.8V work voltage - 1024 KB Flash diff --git a/boards/96boards/carbon/doc/stm32f401xe.rst b/boards/96boards/carbon/doc/stm32f401xe.rst index c493c0a7fd62..38fe12785ea8 100644 --- a/boards/96boards/carbon/doc/stm32f401xe.rst +++ b/boards/96boards/carbon/doc/stm32f401xe.rst @@ -47,7 +47,7 @@ Hardware 96Boards Carbon provides the following hardware components: - STM32F401RET6 in LQFP64 package -- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU +- ARM® 32-bit Cortex®-M4 CPU with FPU - 84 MHz max CPU frequency - VDD from 1.7 V to 3.6 V - 512 KB Flash @@ -67,8 +67,9 @@ Hardware - Bluetooth LE over SPI, provided by nRF51822 More information about STM32F401RE can be found here: - - `STM32F401RE on www.st.com`_ - - `STM32F401 reference manual`_ + +- `STM32F401RE on www.st.com`_ +- `STM32F401 reference manual`_ Supported Features ================== diff --git a/boards/96boards/meerkat96/96b_meerkat96_mcimx7d_m4.dts b/boards/96boards/meerkat96/96b_meerkat96_mcimx7d_m4.dts index 8444e9e01afb..ca789203622c 100644 --- a/boards/96boards/meerkat96/96b_meerkat96_mcimx7d_m4.dts +++ b/boards/96boards/meerkat96/96b_meerkat96_mcimx7d_m4.dts @@ -5,7 +5,7 @@ */ /dts-v1/; -#include +#include #include "96b_meerkat96-pinctrl.dtsi" / { diff --git a/boards/96boards/neonkey/doc/index.rst b/boards/96boards/neonkey/doc/index.rst index b69b94a47120..b926a65a8c27 100644 --- a/boards/96boards/neonkey/doc/index.rst +++ b/boards/96boards/neonkey/doc/index.rst @@ -24,7 +24,7 @@ Hardware 96Boards Neonkey provides the following hardware components: - STM32F411CE in UFQFPN48 package -- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU +- ARM® 32-bit Cortex®-M4 CPU with FPU - 84 MHz max CPU frequency - 1.8V work voltage - 512 KB Flash diff --git a/boards/96boards/nitrogen/doc/index.rst b/boards/96boards/nitrogen/doc/index.rst index 398419230868..86c0a6051892 100644 --- a/boards/96boards/nitrogen/doc/index.rst +++ b/boards/96boards/nitrogen/doc/index.rst @@ -25,7 +25,7 @@ Hardware 96Boards Nitrogen provides the following hardware components: - nRF52832 microcontroller with 512kB Flash, 64kB RAM -- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU +- ARM® 32-bit Cortex®-M4 CPU with FPU - Bluetooth LE - NFC - LPC11U35 on board SWD debugger diff --git a/boards/96boards/stm32_sensor_mez/96b_stm32_sensor_mez.dts b/boards/96boards/stm32_sensor_mez/96b_stm32_sensor_mez.dts index d1f7d7ae4619..fe4f3e43d6bb 100644 --- a/boards/96boards/stm32_sensor_mez/96b_stm32_sensor_mez.dts +++ b/boards/96boards/stm32_sensor_mez/96b_stm32_sensor_mez.dts @@ -80,6 +80,7 @@ mul-n = <192>; div-r = <3>; div-q = <4>; + post-div-q = <1>; clocks = <&clk_hse>; status = "okay"; /* 48MHz on PLLI2SQ */ }; diff --git a/boards/96boards/stm32_sensor_mez/doc/index.rst b/boards/96boards/stm32_sensor_mez/doc/index.rst index 1539a8148a18..bf02b739e2cd 100644 --- a/boards/96boards/stm32_sensor_mez/doc/index.rst +++ b/boards/96boards/stm32_sensor_mez/doc/index.rst @@ -24,7 +24,7 @@ Hardware 96Boards STM32 Sensor Mezzanine provides the following hardware components: - STM32F446VE in LQFP100 package -- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU +- ARM® 32-bit Cortex®-M4 CPU with FPU - 180 MHz max CPU frequency - 1.8V work voltage - 512 KB Flash @@ -110,16 +110,19 @@ exposed via on-board Micro USB connector. Default settings are 115200 8N1. The default USART mappings for the remaining ones are: - USART1: Connected to AP via UART0 on the 96Boards Low-Speed Header. - - TX: PA9 - - RX: PA10 + + - TX: PA9 + - RX: PA10 - USART2: Connected to D0(RX) and D1(TX) on the Arduino Header. - - TX: PD5 - - RX: PD6 + + - TX: PD5 + - RX: PD6 - USART3: Broken out to Grove connector J10. - - TX: PD8 - - RX: PD9 + + - TX: PD8 + - RX: PD9 I2C --- diff --git a/boards/Kconfig b/boards/Kconfig index 71b3b9571ad2..19e237dc9451 100644 --- a/boards/Kconfig +++ b/boards/Kconfig @@ -20,8 +20,8 @@ config BOARD_REVISION config BOARD_TARGET string - default "$(BOARD)@$(BOARD_REVISION)$(BOARD_QUALIFIERS)" if "$(BOARD_REVISION)" != "" - default "$(BOARD)$(BOARD_QUALIFIERS)" + default "$(BOARD)@$(BOARD_REVISION)/$(BOARD_QUALIFIERS)" if "$(BOARD_REVISION)" != "" + default "$(BOARD)/$(BOARD_QUALIFIERS)" help Contains the board target (full string including name, revision, soc, cluster and variant) of the board being used. diff --git a/boards/Kconfig.v2 b/boards/Kconfig.v2 index 6fce9ccb99d5..609ebd536e4c 100644 --- a/boards/Kconfig.v2 +++ b/boards/Kconfig.v2 @@ -3,8 +3,7 @@ # SPDX-License-Identifier: Apache-2.0 BOARD_STRING := $(normalize_upper,$(BOARD)) -BOARD_TARGET_STRING := $(normalize_upper,$(BOARD)$(BOARD_QUALIFIERS)) -BOARD_QUALIFIERS_NO_SEPARATOR := $(substring,$(BOARD_QUALIFIERS),1) +BOARD_TARGET_STRING := $(normalize_upper,$(BOARD)/$(BOARD_QUALIFIERS)) config BOARD_$(BOARD_STRING) def_bool y @@ -18,7 +17,7 @@ config BOARD_$(BOARD_TARGET_STRING) config BOARD_QUALIFIERS string - default "$(BOARD_QUALIFIERS_NO_SEPARATOR)" + default "$(BOARD_QUALIFIERS)" help Contains the qualifiers of the board being used without the name of the board itself. diff --git a/boards/actinius/icarus/actinius_icarus_nrf9160_ns.dts b/boards/actinius/icarus/actinius_icarus_nrf9160_ns.dts index 14017067f584..e10b4a667cbc 100644 --- a/boards/actinius/icarus/actinius_icarus_nrf9160_ns.dts +++ b/boards/actinius/icarus/actinius_icarus_nrf9160_ns.dts @@ -5,7 +5,7 @@ */ /dts-v1/; -#include +#include #include "actinius_icarus_common.dtsi" / { diff --git a/boards/actinius/icarus_bee/actinius_icarus_bee_nrf9160_ns.dts b/boards/actinius/icarus_bee/actinius_icarus_bee_nrf9160_ns.dts index b9d1493053fc..1a40879e16d1 100644 --- a/boards/actinius/icarus_bee/actinius_icarus_bee_nrf9160_ns.dts +++ b/boards/actinius/icarus_bee/actinius_icarus_bee_nrf9160_ns.dts @@ -5,7 +5,7 @@ */ /dts-v1/; -#include +#include #include "actinius_icarus_bee_common.dtsi" / { diff --git a/boards/actinius/icarus_som/actinius_icarus_som_nrf9160_ns.dts b/boards/actinius/icarus_som/actinius_icarus_som_nrf9160_ns.dts index 4ae2ca17343a..1561f269014e 100644 --- a/boards/actinius/icarus_som/actinius_icarus_som_nrf9160_ns.dts +++ b/boards/actinius/icarus_som/actinius_icarus_som_nrf9160_ns.dts @@ -5,7 +5,7 @@ */ /dts-v1/; -#include +#include #include "actinius_icarus_som_common.dtsi" / { diff --git a/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_nrf9160_ns.dts b/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_nrf9160_ns.dts index 3fef59bf93bc..20a57865812f 100644 --- a/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_nrf9160_ns.dts +++ b/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_nrf9160_ns.dts @@ -5,7 +5,7 @@ */ /dts-v1/; -#include +#include #include "actinius_icarus_som_dk_common.dtsi" / { diff --git a/boards/adafruit/feather_adalogger_rp2040/adafruit_feather_adalogger_rp2040.dts b/boards/adafruit/feather_adalogger_rp2040/adafruit_feather_adalogger_rp2040.dts index 34eccd76b818..8104149dc03d 100644 --- a/boards/adafruit/feather_adalogger_rp2040/adafruit_feather_adalogger_rp2040.dts +++ b/boards/adafruit/feather_adalogger_rp2040/adafruit_feather_adalogger_rp2040.dts @@ -71,11 +71,13 @@ &flash0 { reg = <0x10000000 DT_SIZE_M(8)>; + ranges = <0x0 0x10000000 DT_SIZE_M(8)>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + ranges; /* Reserved memory for the second stage bootloader */ second_stage_bootloader: partition@0 { diff --git a/boards/adafruit/feather_canbus_rp2040/adafruit_feather_canbus_rp2040.dts b/boards/adafruit/feather_canbus_rp2040/adafruit_feather_canbus_rp2040.dts index cc16668a541e..32779162ad94 100644 --- a/boards/adafruit/feather_canbus_rp2040/adafruit_feather_canbus_rp2040.dts +++ b/boards/adafruit/feather_canbus_rp2040/adafruit_feather_canbus_rp2040.dts @@ -71,11 +71,13 @@ &flash0 { reg = <0x10000000 DT_SIZE_M(8)>; + ranges = <0x0 0x10000000 DT_SIZE_M(8)>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + ranges; /* Reserved memory for the second stage bootloader */ second_stage_bootloader: partition@0 { diff --git a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft.dts b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft.dts index 114a2d9cb91d..ae11a9e49b50 100644 --- a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft.dts +++ b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft.dts @@ -27,7 +27,7 @@ led1: led_1 { label = "TFT Backlight"; - gpios = <&gpio1 45 GPIO_ACTIVE_HIGH>; + gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; }; }; @@ -46,8 +46,8 @@ mipi_dbi { compatible = "zephyr,mipi-dbi-spi"; spi-dev = <&spi2>; - dc-gpios = <&gpio1 39 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio1 40 GPIO_ACTIVE_LOW>; + dc-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; write-only; #address-cells = <1>; #size-cells = <0>; @@ -76,9 +76,9 @@ porch-param = [0c 0c 00 33 33]; cmd2en-param = [5a 69 02 01]; pwctrl1-param = [a4 a1]; - pvgam-param = [70 2C 2E 15 10 09 48 33 53 0B 19 18 20 25]; - nvgam-param = [70 2C 2E 15 10 09 48 33 53 0B 19 18 20 25]; - ram-param = [00 F0]; + pvgam-param = [70 2c 2e 15 10 09 48 33 53 0b 19 18 20 25]; + nvgam-param = [70 2c 2e 15 10 09 48 33 53 0b 19 18 20 25]; + ram-param = [00 f0]; rgb-param = [40 02 14]; mipi-mode = "MIPI_DBI_MODE_SPI_4WIRE"; }; diff --git a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft_reverse.dts b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft_reverse.dts index fe6a7eba826d..037147ae9ab7 100644 --- a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft_reverse.dts +++ b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft_reverse.dts @@ -28,7 +28,7 @@ led1: led_1 { label = "TFT Backlight"; - gpios = <&gpio1 45 GPIO_ACTIVE_HIGH>; + gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; }; }; @@ -60,8 +60,8 @@ mipi_dbi { compatible = "zephyr,mipi-dbi-spi"; spi-dev = <&spi2>; - dc-gpios = <&gpio1 40 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio1 41 GPIO_ACTIVE_LOW>; + dc-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; write-only; #address-cells = <1>; #size-cells = <0>; @@ -90,9 +90,9 @@ porch-param = [0c 0c 00 33 33]; cmd2en-param = [5a 69 02 01]; pwctrl1-param = [a4 a1]; - pvgam-param = [70 2C 2E 15 10 09 48 33 53 0B 19 18 20 25]; - nvgam-param = [70 2C 2E 15 10 09 48 33 53 0B 19 18 20 25]; - ram-param = [00 F0]; + pvgam-param = [70 2c 2e 15 10 09 48 33 53 0b 19 18 20 25]; + nvgam-param = [70 2c 2e 15 10 09 48 33 53 0b 19 18 20 25]; + ram-param = [00 f0]; rgb-param = [40 02 14]; mipi-mode = "MIPI_DBI_MODE_SPI_4WIRE"; }; diff --git a/boards/adafruit/feather_esp32s2/feather_connector.dtsi b/boards/adafruit/feather_esp32s2/feather_connector.dtsi index dd39d9404dba..9893f46b834a 100644 --- a/boards/adafruit/feather_esp32s2/feather_connector.dtsi +++ b/boards/adafruit/feather_esp32s2/feather_connector.dtsi @@ -18,14 +18,14 @@ <3 0 &gpio0 15 0>, /* A3 */ <4 0 &gpio0 14 0>, /* A4 */ <5 0 &gpio0 8 0>, /* A5 */ - <6 0 &gpio1 36 0>, /* SCK */ - <7 0 &gpio1 35 0>, /* MOSI */ - <8 0 &gpio1 37 0>, /* MISO */ - <9 0 &gpio1 38 0>, /* RX */ - <10 0 &gpio1 39 0>, /* TX */ - <11 0 &gpio1 43 0>, /* DB */ - <12 0 &gpio1 3 0>, /* SDA */ - <13 0 &gpio1 4 0>, /* SCL */ + <6 0 &gpio1 4 0>, /* SCK */ + <7 0 &gpio1 3 0>, /* MOSI */ + <8 0 &gpio1 5 0>, /* MISO */ + <9 0 &gpio1 6 0>, /* RX */ + <10 0 &gpio1 7 0>, /* TX */ + <11 0 &gpio1 11 0>, /* DB */ + <12 0 &gpio0 3 0>, /* SDA */ + <13 0 &gpio0 4 0>, /* SCL */ <14 0 &gpio0 5 0>, /* D5 */ <15 0 &gpio0 6 0>, /* D6 */ <16 0 &gpio0 9 0>, /* D9 */ diff --git a/boards/adafruit/feather_esp32s2/feather_connector_tft.dtsi b/boards/adafruit/feather_esp32s2/feather_connector_tft.dtsi index 9c1083d1208c..b2f3d514ff41 100644 --- a/boards/adafruit/feather_esp32s2/feather_connector_tft.dtsi +++ b/boards/adafruit/feather_esp32s2/feather_connector_tft.dtsi @@ -18,14 +18,14 @@ <3 0 &gpio0 15 0>, /* A3 */ <4 0 &gpio0 14 0>, /* A4 */ <5 0 &gpio0 8 0>, /* A5 */ - <6 0 &gpio1 36 0>, /* SCK */ - <7 0 &gpio1 35 0>, /* MOSI */ - <8 0 &gpio1 37 0>, /* MISO */ + <6 0 &gpio1 4 0>, /* SCK */ + <7 0 &gpio1 3 0>, /* MOSI */ + <8 0 &gpio1 5 0>, /* MISO */ <9 0 &gpio0 2 0>, /* RX */ <10 0 &gpio0 1 0>, /* TX */ - <11 0 &gpio1 43 0>, /* DB */ - <12 0 &gpio1 42 0>, /* SDA */ - <13 0 &gpio1 41 0>, /* SCL */ + <11 0 &gpio1 11 0>, /* DB */ + <12 0 &gpio1 10 0>, /* SDA */ + <13 0 &gpio1 9 0>, /* SCL */ <14 0 &gpio0 5 0>, /* D5 */ <15 0 &gpio0 6 0>, /* D6 */ <16 0 &gpio0 9 0>, /* D9 */ diff --git a/boards/adafruit/feather_esp32s2/support/openocd.cfg b/boards/adafruit/feather_esp32s2/support/openocd.cfg index 2f740b4a36ab..b45e13c53d01 100644 --- a/boards/adafruit/feather_esp32s2/support/openocd.cfg +++ b/boards/adafruit/feather_esp32s2/support/openocd.cfg @@ -1,5 +1,5 @@ -set ESP_RTOS none -set ESP32_ONLYCPU 1 +set ESP_RTOS Zephyr +set ESP_ONLYCPU 1 # Source the JTAG interface configuration file source [find interface/esp_usb_jtag.cfg] diff --git a/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_procpu.dts b/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_procpu.dts index 0b671f220ef3..e4838ba5e62f 100644 --- a/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_procpu.dts +++ b/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_procpu.dts @@ -21,6 +21,11 @@ aliases { i2c-0 = &i2c0; watchdog0 = &wdt0; + uart-0 = &uart0; + sw0 = &button0; + led0 = &led0; + led-strip = &led_strip; + fuel-gauge0 = &max17048; }; chosen { @@ -32,15 +37,6 @@ zephyr,bt-hci = &esp32_bt_hci; }; - /* These aliases are provided for compatibility with samples */ - aliases { - uart-0 = &uart0; - sw0 = &button0; - led0 = &led0; - led-strip = &led_strip; - fuel-gauge0 = &max17048; - }; - buttons { compatible = "gpio-keys"; diff --git a/boards/adafruit/feather_esp32s3/feather_connector.dtsi b/boards/adafruit/feather_esp32s3/feather_connector.dtsi index d4c567e0830d..1d25345c80d3 100644 --- a/boards/adafruit/feather_esp32s3/feather_connector.dtsi +++ b/boards/adafruit/feather_esp32s3/feather_connector.dtsi @@ -17,12 +17,12 @@ <3 0 &gpio0 15 0>, /* A3 */ <4 0 &gpio0 14 0>, /* A4 */ <5 0 &gpio0 8 0>, /* A5 */ - <6 0 &gpio1 36 0>, /* SCK */ - <7 0 &gpio1 35 0>, /* MOSI */ - <8 0 &gpio1 37 0>, /* MISO */ - <9 0 &gpio1 38 0>, /* RX */ - <10 0 &gpio1 39 0>, /* TX */ - <11 0 &gpio1 44 0>, /* DB */ + <6 0 &gpio1 4 0>, /* SCK */ + <7 0 &gpio1 3 0>, /* MOSI */ + <8 0 &gpio1 5 0>, /* MISO */ + <9 0 &gpio1 6 0>, /* RX */ + <10 0 &gpio1 7 0>, /* TX */ + <11 0 &gpio1 12 0>, /* DB */ <12 0 &gpio0 3 0>, /* SDA */ <13 0 &gpio0 4 0>, /* SCL */ <14 0 &gpio0 5 0>, /* D5 */ diff --git a/boards/adafruit/feather_esp32s3/support/openocd.cfg b/boards/adafruit/feather_esp32s3/support/openocd.cfg index 2f740b4a36ab..b45e13c53d01 100644 --- a/boards/adafruit/feather_esp32s3/support/openocd.cfg +++ b/boards/adafruit/feather_esp32s3/support/openocd.cfg @@ -1,5 +1,5 @@ -set ESP_RTOS none -set ESP32_ONLYCPU 1 +set ESP_RTOS Zephyr +set ESP_ONLYCPU 1 # Source the JTAG interface configuration file source [find interface/esp_usb_jtag.cfg] diff --git a/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_procpu.dts b/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_procpu.dts index fdbffd5a4f80..3295356dbf66 100644 --- a/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_procpu.dts +++ b/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_procpu.dts @@ -23,6 +23,11 @@ i2c-0 = &i2c0; watchdog0 = &wdt0; fuel-gauge0 = &max17048; + uart-0 = &uart0; + sw0 = &button0; + led0 = &led0; + led-strip = &led_strip; + backlight = &led1; }; chosen { @@ -35,15 +40,6 @@ zephyr,display = &st7789v_tft; }; - /* These aliases are provided for compatibility with samples */ - aliases { - uart-0 = &uart0; - sw0 = &button0; - led0 = &led0; - led-strip = &led_strip; - backlight = &led1; - }; - buttons { compatible = "gpio-keys"; @@ -62,7 +58,7 @@ }; led1: led_1 { - gpios = <&gpio1 45 GPIO_ACTIVE_HIGH>; + gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; }; }; @@ -73,7 +69,7 @@ neopixel_pwr: neopixel_pwr { compatible = "power-domain-gpio"; #power-domain-cells = <0>; - enable-gpios = <&gpio1 34 GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; }; /* @@ -89,8 +85,8 @@ mipi_dbi { compatible = "zephyr,mipi-dbi-spi"; spi-dev = <&spi2>; - dc-gpios = <&gpio1 39 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio1 40 GPIO_ACTIVE_LOW>; + dc-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; write-only; #address-cells = <1>; #size-cells = <0>; @@ -119,9 +115,9 @@ porch-param = [0c 0c 00 33 33]; cmd2en-param = [5a 69 02 01]; pwctrl1-param = [a4 a1]; - pvgam-param = [70 2C 2E 15 10 09 48 33 53 0B 19 18 20 25]; - nvgam-param = [70 2C 2E 15 10 09 48 33 53 0B 19 18 20 25]; - ram-param = [00 F0]; + pvgam-param = [70 2c 2e 15 10 09 48 33 53 0b 19 18 20 25]; + nvgam-param = [70 2c 2e 15 10 09 48 33 53 0b 19 18 20 25]; + ram-param = [00 f0]; rgb-param = [40 02 14]; mipi-mode = "MIPI_DBI_MODE_SPI_4WIRE"; }; diff --git a/boards/adafruit/feather_esp32s3_tft/feather_connector.dtsi b/boards/adafruit/feather_esp32s3_tft/feather_connector.dtsi index 675ab2395f61..999591779a14 100644 --- a/boards/adafruit/feather_esp32s3_tft/feather_connector.dtsi +++ b/boards/adafruit/feather_esp32s3_tft/feather_connector.dtsi @@ -17,14 +17,14 @@ <3 0 &gpio0 15 0>, /* A3 */ <4 0 &gpio0 14 0>, /* A4 */ <5 0 &gpio0 8 0>, /* A5 */ - <6 0 &gpio1 36 0>, /* SCK */ - <7 0 &gpio1 35 0>, /* MOSI */ - <8 0 &gpio1 37 0>, /* MISO */ + <6 0 &gpio1 4 0>, /* SCK */ + <7 0 &gpio1 3 0>, /* MOSI */ + <8 0 &gpio1 5 0>, /* MISO */ <9 0 &gpio0 2 0>, /* RX */ <10 0 &gpio0 1 0>, /* TX */ - <11 0 &gpio1 44 0>, /* DB */ - <12 0 &gpio1 42 0>, /* SDA */ - <13 0 &gpio1 41 0>, /* SCL */ + <11 0 &gpio1 12 0>, /* DB */ + <12 0 &gpio1 10 0>, /* SDA */ + <13 0 &gpio1 9 0>, /* SCL */ <14 0 &gpio0 5 0>, /* D5 */ <15 0 &gpio0 6 0>, /* D6 */ <16 0 &gpio0 9 0>, /* D9 */ diff --git a/boards/adafruit/feather_esp32s3_tft/support/openocd.cfg b/boards/adafruit/feather_esp32s3_tft/support/openocd.cfg index 2f740b4a36ab..b45e13c53d01 100644 --- a/boards/adafruit/feather_esp32s3_tft/support/openocd.cfg +++ b/boards/adafruit/feather_esp32s3_tft/support/openocd.cfg @@ -1,5 +1,5 @@ -set ESP_RTOS none -set ESP32_ONLYCPU 1 +set ESP_RTOS Zephyr +set ESP_ONLYCPU 1 # Source the JTAG interface configuration file source [find interface/esp_usb_jtag.cfg] diff --git a/boards/adafruit/feather_esp32s3_tft_reverse/adafruit_feather_esp32s3_tft_reverse_procpu.dts b/boards/adafruit/feather_esp32s3_tft_reverse/adafruit_feather_esp32s3_tft_reverse_procpu.dts index 841e85761a15..5e3ec0ec24a9 100644 --- a/boards/adafruit/feather_esp32s3_tft_reverse/adafruit_feather_esp32s3_tft_reverse_procpu.dts +++ b/boards/adafruit/feather_esp32s3_tft_reverse/adafruit_feather_esp32s3_tft_reverse_procpu.dts @@ -75,7 +75,7 @@ led1: led_1 { label = "TFT Backlight"; - gpios = <&gpio1 45 GPIO_ACTIVE_HIGH>; + gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; }; }; @@ -103,8 +103,8 @@ mipi_dbi { compatible = "zephyr,mipi-dbi-spi"; spi-dev = <&spi2>; - dc-gpios = <&gpio1 40 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio1 41 GPIO_ACTIVE_LOW>; + dc-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; write-only; #address-cells = <1>; #size-cells = <0>; @@ -133,9 +133,9 @@ porch-param = [0c 0c 00 33 33]; cmd2en-param = [5a 69 02 01]; pwctrl1-param = [a4 a1]; - pvgam-param = [70 2C 2E 15 10 09 48 33 53 0B 19 18 20 25]; - nvgam-param = [70 2C 2E 15 10 09 48 33 53 0B 19 18 20 25]; - ram-param = [00 F0]; + pvgam-param = [70 2c 2e 15 10 09 48 33 53 0b 19 18 20 25]; + nvgam-param = [70 2c 2e 15 10 09 48 33 53 0b 19 18 20 25]; + ram-param = [00 f0]; rgb-param = [40 02 14]; mipi-mode = "MIPI_DBI_MODE_SPI_4WIRE"; }; diff --git a/boards/adafruit/feather_esp32s3_tft_reverse/feather_connector.dtsi b/boards/adafruit/feather_esp32s3_tft_reverse/feather_connector.dtsi index 6c24ae9d0bce..8be241dd24dc 100644 --- a/boards/adafruit/feather_esp32s3_tft_reverse/feather_connector.dtsi +++ b/boards/adafruit/feather_esp32s3_tft_reverse/feather_connector.dtsi @@ -18,12 +18,12 @@ <3 0 &gpio0 15 0>, /* A3 */ <4 0 &gpio0 14 0>, /* A4 */ <5 0 &gpio0 8 0>, /* A5 */ - <6 0 &gpio1 36 0>, /* SCK */ - <7 0 &gpio1 35 0>, /* MOSI */ - <8 0 &gpio1 37 0>, /* MISO */ - <9 0 &gpio1 38 0>, /* RX */ - <10 0 &gpio1 39 0>, /* TX */ - <11 0 &gpio1 46 0>, /* DB */ + <6 0 &gpio1 4 0>, /* SCK */ + <7 0 &gpio1 3 0>, /* MOSI */ + <8 0 &gpio1 5 0>, /* MISO */ + <9 0 &gpio1 6 0>, /* RX */ + <10 0 &gpio1 7 0>, /* TX */ + <11 0 &gpio1 14 0>, /* DB */ <12 0 &gpio0 3 0>, /* SDA */ <13 0 &gpio0 4 0>, /* SCL */ <14 0 &gpio0 5 0>, /* D5 */ diff --git a/boards/adafruit/feather_esp32s3_tft_reverse/support/openocd.cfg b/boards/adafruit/feather_esp32s3_tft_reverse/support/openocd.cfg index 2f740b4a36ab..b45e13c53d01 100644 --- a/boards/adafruit/feather_esp32s3_tft_reverse/support/openocd.cfg +++ b/boards/adafruit/feather_esp32s3_tft_reverse/support/openocd.cfg @@ -1,5 +1,5 @@ -set ESP_RTOS none -set ESP32_ONLYCPU 1 +set ESP_RTOS Zephyr +set ESP_ONLYCPU 1 # Source the JTAG interface configuration file source [find interface/esp_usb_jtag.cfg] diff --git a/boards/adafruit/feather_propmaker_rp2040/Kconfig b/boards/adafruit/feather_propmaker_rp2040/Kconfig new file mode 100644 index 000000000000..f03d09319fa3 --- /dev/null +++ b/boards/adafruit/feather_propmaker_rp2040/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ADAFRUIT_FEATHER_PROPMAKER_RP2040 + select RP2_FLASH_W25Q080 diff --git a/boards/adafruit/feather_propmaker_rp2040/Kconfig.adafruit_feather_propmaker_rp2040 b/boards/adafruit/feather_propmaker_rp2040/Kconfig.adafruit_feather_propmaker_rp2040 new file mode 100644 index 000000000000..465a1cffaa13 --- /dev/null +++ b/boards/adafruit/feather_propmaker_rp2040/Kconfig.adafruit_feather_propmaker_rp2040 @@ -0,0 +1,5 @@ +# Copyright (c) 2026 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ADAFRUIT_FEATHER_PROPMAKER_RP2040 + select SOC_RP2040 diff --git a/boards/adafruit/feather_propmaker_rp2040/Kconfig.defconfig b/boards/adafruit/feather_propmaker_rp2040/Kconfig.defconfig new file mode 100644 index 000000000000..af8ee9a0a6ab --- /dev/null +++ b/boards/adafruit/feather_propmaker_rp2040/Kconfig.defconfig @@ -0,0 +1,16 @@ +# Copyright (c) 2022 Peter Johanson +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ADAFRUIT_FEATHER_PROPMAKER_RP2040 + +if I2C_DW + +config I2C_DW_CLOCK_SPEED + default 125 + +endif # I2C_DW + +config USB_SELF_POWERED + default n + +endif # BOARD_ADAFRUIT_FEATHER_PROPMAKER_RP2040 diff --git a/boards/adafruit/feather_propmaker_rp2040/adafruit_feather_propmaker_rp2040-pinctrl.dtsi b/boards/adafruit/feather_propmaker_rp2040/adafruit_feather_propmaker_rp2040-pinctrl.dtsi new file mode 100644 index 000000000000..071772af6155 --- /dev/null +++ b/boards/adafruit/feather_propmaker_rp2040/adafruit_feather_propmaker_rp2040-pinctrl.dtsi @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2026 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + uart0_default: uart0_default { + group1 { + pinmux = ; + }; + + group2 { + pinmux = ; + input-enable; + }; + }; + + i2c1_default: i2c1_default { + group1 { + pinmux = , ; + input-enable; + }; + }; + + spi1_default: spi1_default { + group1 { + pinmux = , ; + }; + + group2 { + pinmux = ; + input-enable; + }; + }; + + adc_default: adc_default { + group1 { + pinmux = , , , ; + input-enable; + }; + }; + + ws2812_pio0_default: ws2812_pio0_default { + group1 { + pinmux = ; + }; + }; + + ws2812_pio1_default: ws2812_pio1_default { + group1 { + pinmux = ; + }; + }; + + pwm_default: pwm_default { + group1 { + pinmux = ; + }; + }; +}; diff --git a/boards/adafruit/feather_propmaker_rp2040/adafruit_feather_propmaker_rp2040.dts b/boards/adafruit/feather_propmaker_rp2040/adafruit_feather_propmaker_rp2040.dts new file mode 100644 index 000000000000..daa5f857f469 --- /dev/null +++ b/boards/adafruit/feather_propmaker_rp2040/adafruit_feather_propmaker_rp2040.dts @@ -0,0 +1,253 @@ +/* + * Copyright (c) 2021 Yonatan Schachter + * Copyright (c) 2022 Peter Johanson + * Copyright (c) 2025 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "adafruit_feather_propmaker_rp2040-pinctrl.dtsi" +#include "feather_connector.dtsi" + +/ { + model = "Adafruit Feather Prop-Maker RP2040"; + compatible = "adafruit,feather_propmaker_rp2040"; + + chosen { + zephyr,code-partition = &code_partition; + zephyr,console = &uart0; + zephyr,flash = &flash0; + zephyr,flash-controller = &ssi; + zephyr,shell-uart = &uart0; + zephyr,sram = &sram0; + }; + + aliases { + accel0 = &lis3dh; + led-strip = &onboard_ws2812; + led0 = &red_led; + sw0 = &onboard_button; + watchdog0 = &wdt0; + }; + + zephyr,user { + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>; + }; + + leds: leds { + compatible = "gpio-leds"; + + red_led: red_led { + gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; + label = "Red LED"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + onboard_button: onboard_button { + label = "on-board button"; + gpios = <&gpio0 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + zephyr,code = ; + }; + }; + + stemma_connector: stemma_connector { + compatible = "stemma-qt-connector"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 3 0>, /* SCL */ + <1 0 &gpio0 2 0>; /* SDA */ + }; +}; + +&flash0 { + reg = <0x10000000 DT_SIZE_M(8)>; + ranges = <0x0 0x10000000 DT_SIZE_M(8)>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* Reserved memory for the second stage bootloader */ + second_stage_bootloader: partition@0 { + label = "second_stage_bootloader"; + reg = <0x00000000 0x100>; + read-only; + }; + + /* + * Usable flash. Starts at 0x100, after the bootloader. The partition + * size is 8 MB minus the 0x100 bytes taken by the bootloader. + */ + code_partition: partition@100 { + label = "code-partition"; + reg = <0x100 (DT_SIZE_M(8) - 0x100)>; + read-only; + }; + }; +}; + +&gpio0 { + status = "okay"; + + /* Enable +5 Volt power to screw terminal output and to servo motor */ + servo-power-enable { + gpio-hog; + gpios = <23 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + +&pwm { + pinctrl-0 = <&pwm_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart0 { + current-speed = <115200>; + status = "okay"; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +zephyr_i2c: &i2c1 { + status = "okay"; + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; + clock-frequency = ; + + lis3dh: lis3dh@18 { + compatible = "st,lis3dh", "st,lis2dh"; + reg = <0x18>; + irq-gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; + }; +}; + +&spi1 { + pinctrl-0 = <&spi1_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&timer { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&adc { + status = "okay"; + pinctrl-0 = <&adc_default>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; + + channel@1 { + reg = <1>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; + + channel@2 { + reg = <2>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; + + channel@3 { + reg = <3>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; +}; + +&pio0 { + status = "okay"; + + pio0_ws2812 { + compatible = "worldsemi,ws2812-rpi_pico-pio"; + status = "okay"; + pinctrl-0 = <&ws2812_pio0_default>; + pinctrl-names = "default"; + bit-waveform = <3>, <3>, <4>; + + onboard_ws2812: onboard_ws2812 { + status = "okay"; + gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; + chain-length = <1>; + color-mapping = ; + reset-delay = <280>; + frequency = <800000>; + }; + }; +}; + +&pio1 { + status = "okay"; + + pio1_ws2812 { + compatible = "worldsemi,ws2812-rpi_pico-pio"; + status = "okay"; + pinctrl-0 = <&ws2812_pio1_default>; + pinctrl-names = "default"; + bit-waveform = <3>, <3>, <4>; + + external_ws2812: external_ws2812 { + status = "okay"; + gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; + chain-length = <4>; /* Adjust to your number of LEDs */ + color-mapping = ; + reset-delay = <280>; + frequency = <800000>; + }; + }; +}; + +zephyr_udc0: &usbd { + status = "okay"; +}; + +&die_temp { + status = "okay"; +}; + +&vreg { + regulator-always-on; + regulator-allowed-modes = ; +}; + +&xosc { + startup-delay-multiplier = <64>; +}; diff --git a/boards/adafruit/feather_propmaker_rp2040/adafruit_feather_propmaker_rp2040.yaml b/boards/adafruit/feather_propmaker_rp2040/adafruit_feather_propmaker_rp2040.yaml new file mode 100644 index 000000000000..0e755231a7e5 --- /dev/null +++ b/boards/adafruit/feather_propmaker_rp2040/adafruit_feather_propmaker_rp2040.yaml @@ -0,0 +1,22 @@ +identifier: adafruit_feather_propmaker_rp2040 +name: Adafruit RP2040 Prop-Maker Feather +type: mcu +arch: arm +flash: 8192 +ram: 264 +toolchain: + - zephyr + - gnuarmemb +supported: + - adc + - clock + - counter + - dma + - flash + - gpio + - hwinfo + - i2c + - pwm + - spi + - uart + - watchdog diff --git a/boards/adafruit/feather_propmaker_rp2040/adafruit_feather_propmaker_rp2040_defconfig b/boards/adafruit/feather_propmaker_rp2040/adafruit_feather_propmaker_rp2040_defconfig new file mode 100644 index 000000000000..45d6f7617058 --- /dev/null +++ b/boards/adafruit/feather_propmaker_rp2040/adafruit_feather_propmaker_rp2040_defconfig @@ -0,0 +1,14 @@ +# Copyright (c) 2026 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_BUILD_OUTPUT_UF2=y +CONFIG_CLOCK_CONTROL=y +CONFIG_CONSOLE=y +CONFIG_GPIO_HOGS=y +CONFIG_GPIO=y +CONFIG_PIO_RPI_PICO=y +CONFIG_RESET=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/adafruit/feather_propmaker_rp2040/board.cmake b/boards/adafruit/feather_propmaker_rp2040/board.cmake new file mode 100644 index 000000000000..affc290a869d --- /dev/null +++ b/boards/adafruit/feather_propmaker_rp2040/board.cmake @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2023 TOKITA Hiroshi + +board_runner_args(uf2 "--board-id=RPI-RP2") + +include(${ZEPHYR_BASE}/boards/common/uf2.board.cmake) diff --git a/boards/adafruit/feather_propmaker_rp2040/board.yml b/boards/adafruit/feather_propmaker_rp2040/board.yml new file mode 100644 index 000000000000..c28a46906bb5 --- /dev/null +++ b/boards/adafruit/feather_propmaker_rp2040/board.yml @@ -0,0 +1,6 @@ +board: + name: adafruit_feather_propmaker_rp2040 + full_name: RP2040 Prop-Maker Feather + vendor: adafruit + socs: + - name: rp2040 diff --git a/boards/adafruit/feather_propmaker_rp2040/doc/img/adafruit_feather_propmaker_rp2040.webp b/boards/adafruit/feather_propmaker_rp2040/doc/img/adafruit_feather_propmaker_rp2040.webp new file mode 100644 index 000000000000..ad9f7fcc2780 Binary files /dev/null and b/boards/adafruit/feather_propmaker_rp2040/doc/img/adafruit_feather_propmaker_rp2040.webp differ diff --git a/boards/adafruit/feather_propmaker_rp2040/doc/index.rst b/boards/adafruit/feather_propmaker_rp2040/doc/index.rst new file mode 100644 index 000000000000..eeee092e01b7 --- /dev/null +++ b/boards/adafruit/feather_propmaker_rp2040/doc/index.rst @@ -0,0 +1,249 @@ +.. zephyr:board:: adafruit_feather_propmaker_rp2040 + +Overview +******** + +The `Adafruit RP2040 Prop-Maker Feather`_ board is based on the RP2040 +microcontroller from Raspberry Pi Ltd. +It has an output for external RGB LEDs (Neopixels), an external button input and an I2S-based +speaker output. There is a Stemma QT connector for easy sensor usage. +It is compatible with the Feather board form factor, and has a USB type C connector. + + +Hardware +******** + +- Microcontroller Raspberry Pi RP2040, with a max frequency of 133 MHz +- Dual ARM Cortex M0+ cores +- 264 kByte SRAM +- 8 Mbyte QSPI flash +- 18 GPIO pins +- 4 ADC pins +- I2C +- SPI +- UART +- USB type C connector +- Reset and boot buttons +- On-board Red LED +- On-board RGB LED (Neopixel) +- Stemma QT I2C connector (also known as Qwiic) +- LIS3DH accelerometer +- Servo port +- Built-in lithium ion battery charger +- I2S amplifier and speaker output +- External button input +- External neopixel output + + +Default Zephyr Peripheral Mapping +================================= + ++------------------+--------+-----------------+-------------------+ +| Description | Pin | Default pin mux | Comment | ++==================+========+=================+===================+ +| Boot button | GPIO7 | | Alias sw0 | ++------------------+--------+-----------------+-------------------+ +| I2S DIN | GPIO16 | | | ++------------------+--------+-----------------+-------------------+ +| I2S BCLK | GPIO17 | | | ++------------------+--------+-----------------+-------------------+ +| I2S LRCLK | GPIO18 | | | ++------------------+--------+-----------------+-------------------+ +| Servo output | GPIO20 | PWM_2A | PWM name 4 | ++------------------+--------+-----------------+-------------------+ +| Accel. interrupt | GPIO22 | | | ++------------------+--------+-----------------+-------------------+ + + +Feather header: + ++-------+--------+-----------------+-------------------+ +| Label | Pin | Default pin mux | Also used by | ++=======+========+=================+===================+ +| A0 | GPIO26 | ADC0 | | ++-------+--------+-----------------+-------------------+ +| A1 | GPIO27 | ADC1 | | ++-------+--------+-----------------+-------------------+ +| A2 | GPIO28 | ADC2 | | ++-------+--------+-----------------+-------------------+ +| A3 | GPIO29 | ADC3 | | ++-------+--------+-----------------+-------------------+ +| 24 | GPIO24 | | | ++-------+--------+-----------------+-------------------+ +| 25 | GPIO25 | | | ++-------+--------+-----------------+-------------------+ +| SCK | GPIO14 | SPI1 SCK | | ++-------+--------+-----------------+-------------------+ +| MO | GPIO15 | SPI1 MOSI | | ++-------+--------+-----------------+-------------------+ +| MI | GPIO8 | SPI1 MISO | | ++-------+--------+-----------------+-------------------+ +| RX | GPIO1 | UART0 RX | | ++-------+--------+-----------------+-------------------+ +| TX | GPIO0 | UART0 TX | | ++-------+--------+-----------------+-------------------+ +| 4 | GPIO4 | PIO0 | On-board RGB LED | ++-------+--------+-----------------+-------------------+ +| SDA | GPIO2 | I2C1 SDA | Stemma QT | ++-------+--------+-----------------+-------------------+ +| SCL | GPIO3 | I2C1 SCL | Stemma QT | ++-------+--------+-----------------+-------------------+ +| 5 | GPIO5 | | | ++-------+--------+-----------------+-------------------+ +| 6 | GPIO6 | | | ++-------+--------+-----------------+-------------------+ +| 9 | GPIO9 | | | ++-------+--------+-----------------+-------------------+ +| 10 | GPIO10 | | | ++-------+--------+-----------------+-------------------+ +| 11 | GPIO11 | | | ++-------+--------+-----------------+-------------------+ +| 12 | GPIO12 | | | ++-------+--------+-----------------+-------------------+ +| 13 | GPIO13 | | Red user LED | ++-------+--------+-----------------+-------------------+ + + +Stemma QT I2C connector (pins also available in the Feather header): + ++-------+--------+-----------------+ +| Label | Pin | Default pin mux | ++=======+========+=================+ +| SDA | GPIO2 | I2C1 SDA | ++-------+--------+-----------------+ +| SCL | GPIO3 | I2C1 SCL | ++-------+--------+-----------------+ + +The LIS3DH accelerometer is connected to the I2C bus, and has the 7-bit address 0x18. + + +Output screw terminal: + ++-----+-------------------------------------------+-------------------------+ +| Pin | Description | Default pin mux | ++=====+===========================================+=========================+ +| 1 | RGB LED from GPIO21 | PIO1 | ++-----+-------------------------------------------+-------------------------+ +| 2 | GND | | ++-----+-------------------------------------------+-------------------------+ +| 3 | +5 Volt power output controlled by GPIO23 | gpio-hog always enabled | ++-----+-------------------------------------------+-------------------------+ +| 4 | Button input to GPIO19 | | ++-----+-------------------------------------------+-------------------------+ +| 5 | Speaker - | | ++-----+-------------------------------------------+-------------------------+ +| 6 | Speaker + | | ++-----+-------------------------------------------+-------------------------+ + +The +5V output is always enabled via a ``gpio-hog`` in the devicetree file. Remove the node +``servo-power-enable`` to avoid powering the output on startup. + +See also `pinout`_ and `schematic`_. + + +Supported Features +================== + +Note that the I2S-based speaker output is not yet supported. + +.. zephyr:board-supported-hw:: + + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +The Adafruit RP2040 Prop-Maker Feather board does not expose the SWDIO and SWCLK pins, so +programming must be done via the USB port. Press and hold the BOOT button, and then press +the RST button, and the device will appear as a USB mass storage unit. +Building your application will result in a :file:`build/zephyr/zephyr.uf2` file. +Drag and drop the file to the USB mass storage unit, and the board will be reprogrammed. + +For more details on programming RP2040-based boards, see :ref:`rpi_pico_programming_and_debugging`. + + +Flashing +======== + +To run the :zephyr:code-sample:`blinky` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky/ + :board: adafruit_feather_propmaker_rp2040 + :goals: build flash + +Try also the :zephyr:code-sample:`led-strip`, :zephyr:code-sample:`input-dump`, +:zephyr:code-sample:`button`, :zephyr:code-sample:`accel_polling`, +:zephyr:code-sample:`hello_world` and :zephyr:code-sample:`adc_dt` samples. + +The use of the Stemma QT I2C connector is demonstrated using the +:zephyr:code-sample:`light_sensor_polling` sample and a separate shield: + +.. zephyr-app-commands:: + :zephyr-app: samples/sensor/light_polling/ + :board: adafruit_feather_propmaker_rp2040 + :shield: adafruit_veml7700 + :goals: build flash + +Servo motor control is done via PWM outputs. The :zephyr:code-sample:`servo-motor` sample sets +servo position timing via an overlay file. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/servo_motor/ + :board: adafruit_feather_propmaker_rp2040 + :goals: build flash + +It is also possible to control the servo via the PWM shell: + +.. zephyr-app-commands:: + :zephyr-app: samples/sensor/sensor_shell/ + :board: adafruit_feather_propmaker_rp2040 + :gen-args: -DCONFIG_PWM=y -DCONFIG_PWM_SHELL=y + :goals: build flash + +Control the position via the pulse length. Most servos can handle pulse lengths between 0.8 +and 2 milliseconds: + +.. code-block:: shell + + pwm usec pwm@40050000 4 20000 800 + pwm usec pwm@40050000 4 20000 2000 + +In order to use external neopixels connected via the screw terminal, you need to adapt the +devicetree file to the number of pixels in your external light-strip. See the ``external_ws2812`` +node. You must also change the ``aliases`` attribute from ``led-strip = &onboard_ws2812;`` to +``led-strip = &external_ws2812;``. Then use the :zephyr:code-sample:`led-strip` sample. + +Read the external button via GPIO. + +.. zephyr-app-commands:: + :zephyr-app: samples/sensor/sensor_shell/ + :board: adafruit_feather_propmaker_rp2040 + :gen-args: -DCONFIG_GPIO_SHELL=y + :goals: build flash + +Use these shell commands to read the external button: + +.. code-block:: shell + + gpio conf gpio0 19 iul + gpio get gpio0 19 + +If you wish to map the external button to the Zephyr input subsystem, see how it is done for the +on-board button in the devicetree file. + + +References +********** + +.. target-notes:: + +.. _Adafruit RP2040 Prop-Maker Feather: + https://learn.adafruit.com/adafruit-rp2040-prop-maker-feather + +.. _pinout: + https://learn.adafruit.com/adafruit-rp2040-prop-maker-feather/pinouts + +.. _schematic: + https://learn.adafruit.com/adafruit-rp2040-prop-maker-feather/downloads-2 diff --git a/boards/adafruit/feather_propmaker_rp2040/feather_connector.dtsi b/boards/adafruit/feather_propmaker_rp2040/feather_connector.dtsi new file mode 100644 index 000000000000..ba69cb165fe2 --- /dev/null +++ b/boards/adafruit/feather_propmaker_rp2040/feather_connector.dtsi @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2026 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + feather_header: connector { + compatible = "adafruit-feather-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 26 0>, /* A0 */ + <1 0 &gpio0 27 0>, /* A1 */ + <2 0 &gpio0 28 0>, /* A2 */ + <3 0 &gpio0 29 0>, /* A3 */ + <4 0 &gpio0 24 0>, /* D24 */ + <5 0 &gpio0 25 0>, /* D25 */ + <6 0 &gpio0 14 0>, /* SCK */ + <7 0 &gpio0 15 0>, /* MOSI */ + <8 0 &gpio0 8 0>, /* MISO */ + <9 0 &gpio0 1 0>, /* RX */ + <10 0 &gpio0 0 0>, /* TX */ + <11 0 &gpio0 4 0>, /* D4 */ + <12 0 &gpio0 2 0>, /* SDA */ + <13 0 &gpio0 3 0>, /* SCL */ + <14 0 &gpio0 5 0>, /* D5 */ + <15 0 &gpio0 6 0>, /* D6 */ + <16 0 &gpio0 9 0>, /* D9 */ + <17 0 &gpio0 10 0>, /* D10 */ + <18 0 &gpio0 11 0>, /* D11 */ + <19 0 &gpio0 12 0>, /* D12 */ + <20 0 &gpio0 13 0>; /* D13 */ + }; +}; + +feather_serial: &uart0 {}; + +feather_i2c: &i2c1 {}; + +feather_spi: &spi1 {}; diff --git a/boards/adafruit/feather_rfm95_rp2040/adafruit_feather_rfm95_rp2040.dts b/boards/adafruit/feather_rfm95_rp2040/adafruit_feather_rfm95_rp2040.dts index b31c758b60ca..cb5349ceca28 100644 --- a/boards/adafruit/feather_rfm95_rp2040/adafruit_feather_rfm95_rp2040.dts +++ b/boards/adafruit/feather_rfm95_rp2040/adafruit_feather_rfm95_rp2040.dts @@ -71,11 +71,13 @@ &flash0 { reg = <0x10000000 DT_SIZE_M(8)>; + ranges = <0x0 0x10000000 DT_SIZE_M(8)>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + ranges; /* Reserved memory for the second stage bootloader */ second_stage_bootloader: partition@0 { diff --git a/boards/adafruit/feather_rp2040/adafruit_feather_rp2040.dts b/boards/adafruit/feather_rp2040/adafruit_feather_rp2040.dts index bbec5d120ad8..e07e1b3bb8ea 100644 --- a/boards/adafruit/feather_rp2040/adafruit_feather_rp2040.dts +++ b/boards/adafruit/feather_rp2040/adafruit_feather_rp2040.dts @@ -50,11 +50,13 @@ &flash0 { reg = <0x10000000 DT_SIZE_M(8)>; + ranges = <0x0 0x10000000 DT_SIZE_M(8)>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + ranges; /* Reserved memory for the second stage bootloader */ second_stage_bootloader: partition@0 { diff --git a/boards/adafruit/feather_scorpio_rp2040/Kconfig b/boards/adafruit/feather_scorpio_rp2040/Kconfig new file mode 100644 index 000000000000..515b47b08df4 --- /dev/null +++ b/boards/adafruit/feather_scorpio_rp2040/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2026 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ADAFRUIT_FEATHER_SCORPIO_RP2040 + select RP2_FLASH_W25Q080 diff --git a/boards/adafruit/feather_scorpio_rp2040/Kconfig.adafruit_feather_scorpio_rp2040 b/boards/adafruit/feather_scorpio_rp2040/Kconfig.adafruit_feather_scorpio_rp2040 new file mode 100644 index 000000000000..94dc4a07faff --- /dev/null +++ b/boards/adafruit/feather_scorpio_rp2040/Kconfig.adafruit_feather_scorpio_rp2040 @@ -0,0 +1,5 @@ +# Copyright (c) 2026 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ADAFRUIT_FEATHER_SCORPIO_RP2040 + select SOC_RP2040 diff --git a/boards/adafruit/feather_scorpio_rp2040/Kconfig.defconfig b/boards/adafruit/feather_scorpio_rp2040/Kconfig.defconfig new file mode 100644 index 000000000000..631008b037a3 --- /dev/null +++ b/boards/adafruit/feather_scorpio_rp2040/Kconfig.defconfig @@ -0,0 +1,16 @@ +# Copyright (c) 2022 Peter Johanson +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ADAFRUIT_FEATHER_SCORPIO_RP2040 + +if I2C_DW + +config I2C_DW_CLOCK_SPEED + default 125 + +endif # I2C_DW + +config USB_SELF_POWERED + default n + +endif # BOARD_ADAFRUIT_FEATHER_SCORPIO_RP2040 diff --git a/boards/adafruit/feather_scorpio_rp2040/adafruit_feather_scorpio_rp2040-pinctrl.dtsi b/boards/adafruit/feather_scorpio_rp2040/adafruit_feather_scorpio_rp2040-pinctrl.dtsi new file mode 100644 index 000000000000..ce09e7b470dd --- /dev/null +++ b/boards/adafruit/feather_scorpio_rp2040/adafruit_feather_scorpio_rp2040-pinctrl.dtsi @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2026 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + uart0_default: uart0_default { + group1 { + pinmux = ; + }; + + group2 { + pinmux = ; + input-enable; + }; + }; + + i2c1_default: i2c1_default { + group1 { + pinmux = , ; + input-enable; + }; + }; + + spi1_default: spi1_default { + group1 { + pinmux = , ; + }; + + group2 { + pinmux = ; + input-enable; + }; + }; + + adc_default: adc_default { + group1 { + pinmux = , , , ; + input-enable; + }; + }; + + ws2812_pio0_default: ws2812_pio0_default { + group1 { + pinmux = ; + }; + }; + + ws2812_pio1_default: ws2812_pio1_default { + group1 { + pinmux = ; + }; + }; +}; diff --git a/boards/adafruit/feather_scorpio_rp2040/adafruit_feather_scorpio_rp2040.dts b/boards/adafruit/feather_scorpio_rp2040/adafruit_feather_scorpio_rp2040.dts new file mode 100644 index 000000000000..d755b39cb24a --- /dev/null +++ b/boards/adafruit/feather_scorpio_rp2040/adafruit_feather_scorpio_rp2040.dts @@ -0,0 +1,237 @@ +/* + * Copyright (c) 2021 Yonatan Schachter + * Copyright (c) 2022 Peter Johanson + * Copyright (c) 2026 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "adafruit_feather_scorpio_rp2040-pinctrl.dtsi" +#include "feather_connector.dtsi" + +/ { + model = "Adafruit Feather Scorpio RP2040"; + compatible = "adafruit,feather_scorpio_rp2040"; + + chosen { + zephyr,code-partition = &code_partition; + zephyr,console = &uart0; + zephyr,flash = &flash0; + zephyr,flash-controller = &ssi; + zephyr,shell-uart = &uart0; + zephyr,sram = &sram0; + }; + + aliases { + led-strip = &onboard_ws2812; + led0 = &red_led; + sw0 = &onboard_button; + watchdog0 = &wdt0; + }; + + zephyr,user { + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>; + }; + + leds: leds { + compatible = "gpio-leds"; + + red_led: red_led { + gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; + label = "Red LED"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + onboard_button: onboard_button { + label = "on-board button"; + gpios = <&gpio0 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + zephyr,code = ; + }; + }; + + stemma_connector: stemma_connector { + compatible = "stemma-qt-connector"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 3 0>, /* SCL */ + <1 0 &gpio0 2 0>; /* SDA */ + }; +}; + +&flash0 { + reg = <0x10000000 DT_SIZE_M(8)>; + ranges = <0x0 0x10000000 DT_SIZE_M(8)>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* Reserved memory for the second stage bootloader */ + second_stage_bootloader: partition@0 { + label = "second_stage_bootloader"; + reg = <0x00000000 0x100>; + read-only; + }; + + /* + * Usable flash. Starts at 0x100, after the bootloader. The partition + * size is 8 MB minus the 0x100 bytes taken by the bootloader. + */ + code_partition: partition@100 { + label = "code-partition"; + reg = <0x100 (DT_SIZE_M(8) - 0x100)>; + read-only; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&pwm { + status = "okay"; +}; + +&uart0 { + current-speed = <115200>; + status = "okay"; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +zephyr_i2c: &i2c1 { + status = "okay"; + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; + clock-frequency = ; +}; + +&spi1 { + pinctrl-0 = <&spi1_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&timer { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&adc { + status = "okay"; + pinctrl-0 = <&adc_default>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; + + channel@1 { + reg = <1>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; + + channel@2 { + reg = <2>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; + + channel@3 { + reg = <3>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; +}; + +&pio0 { + status = "okay"; + + pio0_ws2812 { + compatible = "worldsemi,ws2812-rpi_pico-pio"; + status = "okay"; + pinctrl-0 = <&ws2812_pio0_default>; + pinctrl-names = "default"; + bit-waveform = <3>, <3>, <4>; + + onboard_ws2812: onboard_ws2812 { + status = "okay"; + gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; + chain-length = <1>; + color-mapping = ; + reset-delay = <280>; + frequency = <800000>; + }; + }; +}; + +&pio1 { + status = "okay"; + + pio1_ws2812 { + compatible = "worldsemi,ws2812-rpi_pico-pio"; + status = "okay"; + pinctrl-0 = <&ws2812_pio1_default>; + pinctrl-names = "default"; + bit-waveform = <3>, <3>, <4>; + + external_ws2812: external_ws2812 { + status = "okay"; + gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; + chain-length = <4>; /* Adjust to your number of LEDs */ + color-mapping = ; + reset-delay = <280>; + frequency = <800000>; + }; + }; +}; + +zephyr_udc0: &usbd { + status = "okay"; +}; + +&die_temp { + status = "okay"; +}; + +&vreg { + regulator-always-on; + regulator-allowed-modes = ; +}; + +&xosc { + startup-delay-multiplier = <64>; +}; diff --git a/boards/adafruit/feather_scorpio_rp2040/adafruit_feather_scorpio_rp2040.yaml b/boards/adafruit/feather_scorpio_rp2040/adafruit_feather_scorpio_rp2040.yaml new file mode 100644 index 000000000000..0d46d1877a83 --- /dev/null +++ b/boards/adafruit/feather_scorpio_rp2040/adafruit_feather_scorpio_rp2040.yaml @@ -0,0 +1,22 @@ +identifier: adafruit_feather_scorpio_rp2040 +name: Adafruit RP2040 Scorpio Feather +type: mcu +arch: arm +flash: 8192 +ram: 264 +toolchain: + - zephyr + - gnuarmemb +supported: + - adc + - clock + - counter + - dma + - flash + - gpio + - hwinfo + - i2c + - pwm + - spi + - uart + - watchdog diff --git a/boards/adafruit/feather_scorpio_rp2040/adafruit_feather_scorpio_rp2040_defconfig b/boards/adafruit/feather_scorpio_rp2040/adafruit_feather_scorpio_rp2040_defconfig new file mode 100644 index 000000000000..3c045b5537bf --- /dev/null +++ b/boards/adafruit/feather_scorpio_rp2040/adafruit_feather_scorpio_rp2040_defconfig @@ -0,0 +1,14 @@ +# Copyright (c) 2026 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_OUTPUT_UF2=y +CONFIG_CLOCK_CONTROL=y +CONFIG_CONSOLE=y +CONFIG_GPIO=y +CONFIG_PIO_RPI_PICO=y +CONFIG_RESET=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/adafruit/feather_scorpio_rp2040/board.cmake b/boards/adafruit/feather_scorpio_rp2040/board.cmake new file mode 100644 index 000000000000..5a702fc5e030 --- /dev/null +++ b/boards/adafruit/feather_scorpio_rp2040/board.cmake @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: Apache-2.0 +# Adapted from boards/raspberrypi/rpi_pico/board.cmake + +# This configuration allows selecting what debug adapter debugging rpi_pico +# by a command-line argument. +# It is mainly intended to support both the 'picoprobe' and 'raspberrypi-swd' +# adapter described in "Getting started with Raspberry Pi Pico". +# And any other SWD debug adapter might also be usable with this configuration. + +# Set RPI_PICO_DEBUG_ADAPTER to select debug adapter by command-line arguments. +# e.g.) west build -b rpi_pico -- -DRPI_PICO_DEBUG_ADAPTER=raspberrypi-swd +# The value is treated as a part of an interface file name that +# the debugger's configuration file. +# The value must be the 'stem' part of the name of one of the files +# in the openocd interface configuration file. +# The setting is store to CMakeCache.txt. +if("${RPI_PICO_DEBUG_ADAPTER}" STREQUAL "") + set(RPI_PICO_DEBUG_ADAPTER "cmsis-dap") +endif() + +board_runner_args(openocd --cmd-pre-init "source [find interface/${RPI_PICO_DEBUG_ADAPTER}.cfg]") +board_runner_args(openocd --cmd-pre-init "transport select swd") +board_runner_args(openocd --cmd-pre-init "source [find target/rp2040.cfg]") + +# The adapter speed is expected to be set by interface configuration. +# But if not so, set 2000 to adapter speed. +board_runner_args(openocd --cmd-pre-init "set_adapter_speed_if_not_set 2000") + +board_runner_args(jlink "--device=RP2040_M0_0") +board_runner_args(uf2 "--board-id=RPI-RP2") +board_runner_args(pyocd "--target=rp2040") + +# Default runner should be listed first +include(${ZEPHYR_BASE}/boards/common/uf2.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/blackmagicprobe.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/adafruit/feather_scorpio_rp2040/board.yml b/boards/adafruit/feather_scorpio_rp2040/board.yml new file mode 100644 index 000000000000..30bd48caa590 --- /dev/null +++ b/boards/adafruit/feather_scorpio_rp2040/board.yml @@ -0,0 +1,6 @@ +board: + name: adafruit_feather_scorpio_rp2040 + full_name: RP2040 Scorpio Feather + vendor: adafruit + socs: + - name: rp2040 diff --git a/boards/adafruit/feather_scorpio_rp2040/doc/img/adafruit_feather_scorpio_rp2040.webp b/boards/adafruit/feather_scorpio_rp2040/doc/img/adafruit_feather_scorpio_rp2040.webp new file mode 100644 index 000000000000..695bcdefd932 Binary files /dev/null and b/boards/adafruit/feather_scorpio_rp2040/doc/img/adafruit_feather_scorpio_rp2040.webp differ diff --git a/boards/adafruit/feather_scorpio_rp2040/doc/index.rst b/boards/adafruit/feather_scorpio_rp2040/doc/index.rst new file mode 100644 index 000000000000..a567514061b8 --- /dev/null +++ b/boards/adafruit/feather_scorpio_rp2040/doc/index.rst @@ -0,0 +1,198 @@ +.. zephyr:board:: adafruit_feather_scorpio_rp2040 + +Overview +******** + +The `Adafruit RP2040 Scorpio Feather`_ board is based on the RP2040 +microcontroller from Raspberry Pi Ltd. +It has 8 outputs for external RGB LEDs (Neopixels), and a Stemma QT connector for easy +sensor usage. It is compatible with the Feather board form factor, and has a USB type C connector. + + +Hardware +******** + +- Microcontroller Raspberry Pi RP2040, with a max frequency of 133 MHz +- Dual ARM Cortex M0+ cores +- 264 kByte SRAM +- 8 Mbyte QSPI flash +- 25 GPIO pins +- 4 ADC pins +- I2C +- SPI +- UART +- USB type C connector +- Reset and boot buttons +- On-board Red LED +- On-board RGB LED (Neopixel) +- Stemma QT I2C connector (also known as Qwiic) +- Built-in lithium ion battery charger +- 8 external neopixel outputs + + +Default Zephyr Peripheral Mapping +================================= + ++------------------+--------+-----------------+-------------------+ +| Description | Pin | Default pin mux | Comment | ++==================+========+=================+===================+ +| Boot button | GPIO7 | | Alias sw0 | ++------------------+--------+-----------------+-------------------+ + + +Feather header: + ++-------+--------+-----------------+-------------------+ +| Label | Pin | Default pin mux | Also used in | ++=======+========+=================+===================+ +| A0 | GPIO26 | ADC0 | | ++-------+--------+-----------------+-------------------+ +| A1 | GPIO27 | ADC1 | | ++-------+--------+-----------------+-------------------+ +| A2 | GPIO28 | ADC2 | | ++-------+--------+-----------------+-------------------+ +| A3 | GPIO29 | ADC3 | | ++-------+--------+-----------------+-------------------+ +| 24 | GPIO24 | | | ++-------+--------+-----------------+-------------------+ +| 25 | GPIO25 | | | ++-------+--------+-----------------+-------------------+ +| SCK | GPIO14 | SPI1 SCK | | ++-------+--------+-----------------+-------------------+ +| MO | GPIO15 | SPI1 MOSI | | ++-------+--------+-----------------+-------------------+ +| MI | GPIO8 | SPI1 MISO | | ++-------+--------+-----------------+-------------------+ +| R | GPIO1 | UART0 RX | | ++-------+--------+-----------------+-------------------+ +| T | GPIO0 | UART0 TX | | ++-------+--------+-----------------+-------------------+ +| 4 | GPIO4 | PIO0 | On-board Neopixel | ++-------+--------+-----------------+-------------------+ +| D | GPIO2 | I2C1 SDA | Stemma QT | ++-------+--------+-----------------+-------------------+ +| C | GPIO3 | I2C1 SCL | Stemma QT | ++-------+--------+-----------------+-------------------+ +| 5 | GPIO5 | | | ++-------+--------+-----------------+-------------------+ +| 6 | GPIO6 | | | ++-------+--------+-----------------+-------------------+ +| 9 | GPIO9 | | | ++-------+--------+-----------------+-------------------+ +| 10 | GPIO10 | | | ++-------+--------+-----------------+-------------------+ +| 11 | GPIO11 | | | ++-------+--------+-----------------+-------------------+ +| 12 | GPIO12 | | | ++-------+--------+-----------------+-------------------+ +| 13 | GPIO13 | | Red user LED | ++-------+--------+-----------------+-------------------+ + + +Stemma QT I2C connector (pins also available in the Feather header): + ++-------+--------+-----------------+ +| Label | Pin | Default pin mux | ++=======+========+=================+ +| SDA | GPIO2 | I2C1 SDA | ++-------+--------+-----------------+ +| SCL | GPIO3 | I2C1 SCL | ++-------+--------+-----------------+ + + +External Neopixel header: + ++-------+--------+-----------------+ +| Label | Pin | Default pin mux | ++=======+========+=================+ +| 0 | GPIO16 | PIO1 | ++-------+--------+-----------------+ +| 1 | GPIO17 | | ++-------+--------+-----------------+ +| 2 | GPIO18 | | ++-------+--------+-----------------+ +| 3 | GPIO19 | | ++-------+--------+-----------------+ +| 4 | GPIO20 | | ++-------+--------+-----------------+ +| 5 | GPIO21 | | ++-------+--------+-----------------+ +| 6 | GPIO22 | | ++-------+--------+-----------------+ +| 7 | GPIO23 | | ++-------+--------+-----------------+ + +See also `pinout`_ and `schematic`_. + + +Supported Features +================== + +.. zephyr:board-supported-hw:: + + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +By default programming is done via the USB connector. Press and hold the BOOT button, and then +press the RST button, and the device will appear as a USB mass storage unit. +Building your application will result in a :file:`build/zephyr/zephyr.uf2` file. +Drag and drop the file to the USB mass storage unit, and the board will be reprogrammed. + +It is also possible to program and debug the board via the SWDIO and SWCLK pins. +Then a separate programming hardware tool is required, and for example the :command:`openocd` +software is used. Typically the ``OPENOCD`` and ``OPENOCD_DEFAULT_PATH`` values should be set +when building, and the ``--runner openocd`` argument should be used when flashing. +For more details on programming RP2040-based boards, see :ref:`rpi_pico_programming_and_debugging`. + + +Flashing +======== + +To run the :zephyr:code-sample:`blinky` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky/ + :board: adafruit_feather_scorpio_rp2040 + :goals: build flash + +Try also the :zephyr:code-sample:`led-strip`, :zephyr:code-sample:`input-dump`, +:zephyr:code-sample:`hello_world` and :zephyr:code-sample:`adc_dt` samples. + +The :zephyr:code-sample:`button` sample might show spurious button presses, as the button is +connected to a line also used for the QSPI memory. + +The use of the Stemma QT I2C connector is demonstrated using the +:zephyr:code-sample:`light_sensor_polling` sample and a separate shield: + +.. zephyr-app-commands:: + :zephyr-app: samples/sensor/light_polling/ + :board: adafruit_feather_scorpio_rp2040 + :shield: adafruit_veml7700 + :goals: build flash + +As example usage of external Neopixels via the board edge header, the devicetree describes a +string of Neopixels connected to output 0. You need to adapt the number of pixels given in +the ``external_ws2812`` node to the actual number of pixels in your external light-strip. +You must also change the ``aliases`` attribute from ``led-strip = &onboard_ws2812;`` to +``led-strip = &external_ws2812;``. Then use the :zephyr:code-sample:`led-strip` sample. + +It is possible to enable Neopixel drivers for the other external output pins, by adjusting the +devicetree file in a similar manner. + + +References +********** + +.. target-notes:: + +.. _Adafruit RP2040 Scorpio Feather: + https://learn.adafruit.com/introducing-feather-rp2040-scorpio + +.. _pinout: + https://learn.adafruit.com/introducing-feather-rp2040-scorpio/pinouts + +.. _schematic: + https://learn.adafruit.com/introducing-feather-rp2040-scorpio/downloads diff --git a/boards/adafruit/feather_scorpio_rp2040/feather_connector.dtsi b/boards/adafruit/feather_scorpio_rp2040/feather_connector.dtsi new file mode 100644 index 000000000000..ba69cb165fe2 --- /dev/null +++ b/boards/adafruit/feather_scorpio_rp2040/feather_connector.dtsi @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2026 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + feather_header: connector { + compatible = "adafruit-feather-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 26 0>, /* A0 */ + <1 0 &gpio0 27 0>, /* A1 */ + <2 0 &gpio0 28 0>, /* A2 */ + <3 0 &gpio0 29 0>, /* A3 */ + <4 0 &gpio0 24 0>, /* D24 */ + <5 0 &gpio0 25 0>, /* D25 */ + <6 0 &gpio0 14 0>, /* SCK */ + <7 0 &gpio0 15 0>, /* MOSI */ + <8 0 &gpio0 8 0>, /* MISO */ + <9 0 &gpio0 1 0>, /* RX */ + <10 0 &gpio0 0 0>, /* TX */ + <11 0 &gpio0 4 0>, /* D4 */ + <12 0 &gpio0 2 0>, /* SDA */ + <13 0 &gpio0 3 0>, /* SCL */ + <14 0 &gpio0 5 0>, /* D5 */ + <15 0 &gpio0 6 0>, /* D6 */ + <16 0 &gpio0 9 0>, /* D9 */ + <17 0 &gpio0 10 0>, /* D10 */ + <18 0 &gpio0 11 0>, /* D11 */ + <19 0 &gpio0 12 0>, /* D12 */ + <20 0 &gpio0 13 0>; /* D13 */ + }; +}; + +feather_serial: &uart0 {}; + +feather_i2c: &i2c1 {}; + +feather_spi: &spi1 {}; diff --git a/boards/adafruit/feather_scorpio_rp2040/support/openocd.cfg b/boards/adafruit/feather_scorpio_rp2040/support/openocd.cfg new file mode 100644 index 000000000000..34ab592b1861 --- /dev/null +++ b/boards/adafruit/feather_scorpio_rp2040/support/openocd.cfg @@ -0,0 +1,11 @@ +# Copyright (c) 2022 Tokita, Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +# Checking and set 'adapter speed'. +# Set the adaptor speed, if unset, and given as an argument. +proc set_adapter_speed_if_not_set { speed } { + puts "checking adapter speed..." + if { [catch {adapter speed} ret] } { + adapter speed $speed + } +} diff --git a/boards/adafruit/feather_stm32f405/adafruit_feather_stm32f405.dts b/boards/adafruit/feather_stm32f405/adafruit_feather_stm32f405.dts index afa61648790a..bc53c5a583e5 100644 --- a/boards/adafruit/feather_stm32f405/adafruit_feather_stm32f405.dts +++ b/boards/adafruit/feather_stm32f405/adafruit_feather_stm32f405.dts @@ -18,7 +18,7 @@ zephyr,shell-uart = &usart3; zephyr,sram = &sram0; zephyr,flash = &flash0; - zephyr,ccm = &ccm0; + zephyr,dtcm = &ccm0; }; leds { diff --git a/boards/adafruit/itsybitsy_rp2040/adafruit_itsybitsy_rp2040.dts b/boards/adafruit/itsybitsy_rp2040/adafruit_itsybitsy_rp2040.dts index 6207e59f89e5..e97d2a06d284 100644 --- a/boards/adafruit/itsybitsy_rp2040/adafruit_itsybitsy_rp2040.dts +++ b/boards/adafruit/itsybitsy_rp2040/adafruit_itsybitsy_rp2040.dts @@ -60,11 +60,13 @@ &flash0 { reg = <0x10000000 DT_SIZE_M(8)>; + ranges = <0x0 0x10000000 DT_SIZE_M(8)>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + ranges; /* Reserved memory for the second stage bootloader */ second_stage_bootloader: partition@0 { diff --git a/boards/adafruit/macropad_rp2040/adafruit_macropad_rp2040.dts b/boards/adafruit/macropad_rp2040/adafruit_macropad_rp2040.dts index 13e4435f03bd..fe692abb2537 100644 --- a/boards/adafruit/macropad_rp2040/adafruit_macropad_rp2040.dts +++ b/boards/adafruit/macropad_rp2040/adafruit_macropad_rp2040.dts @@ -132,11 +132,13 @@ &flash0 { reg = <0x10000000 DT_SIZE_M(8)>; + ranges = <0x0 0x10000000 DT_SIZE_M(8)>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + ranges; /* Reserved memory for the second stage bootloader */ second_stage_bootloader: partition@0 { @@ -187,7 +189,7 @@ page-offset = <0>; display-offset = <0>; multiplex-ratio = <63>; - prechargep = <0x1F>; + prechargep = <0x1f>; segment-remap; com-invdir; inversion-on; diff --git a/boards/adafruit/metro_rp2040/adafruit_metro_rp2040.dts b/boards/adafruit/metro_rp2040/adafruit_metro_rp2040.dts index e25b20c485c2..e53ceea7caa0 100644 --- a/boards/adafruit/metro_rp2040/adafruit_metro_rp2040.dts +++ b/boards/adafruit/metro_rp2040/adafruit_metro_rp2040.dts @@ -60,11 +60,13 @@ &flash0 { reg = <0x10000000 DT_SIZE_M(16)>; + ranges = <0x0 0x10000000 DT_SIZE_M(16)>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + ranges; /* Reserved memory for the second stage bootloader */ second_stage_bootloader: partition@0 { diff --git a/boards/adafruit/nrf52_adafruit_feather/doc/index.rst b/boards/adafruit/nrf52_adafruit_feather/doc/index.rst index 4e318acd7935..c507fae1103a 100644 --- a/boards/adafruit/nrf52_adafruit_feather/doc/index.rst +++ b/boards/adafruit/nrf52_adafruit_feather/doc/index.rst @@ -62,12 +62,12 @@ Programming and Debugging The ``nrf52_adafruit_feather`` board is available in two different versions: -- `Adafruit Feather nRF52 Pro with myNewt Bootloader`_ +`Adafruit Feather nRF52 Pro with myNewt Bootloader`_ This board version is the recommended one to use. It has the SWD header already populated and comes with the Mynewt serial bootloader installed by default. -- `Adafruit Feather nRF52 Bluefruit LE`_ +`Adafruit Feather nRF52 Bluefruit LE`_ This board is identical to the board above, but the SWD header is not populated and ships with an Arduino friendly bootloader. To be able to work with this version a 2*5pin 0.5" SWD header (e.g. `Adafruit SWD connector`_) diff --git a/boards/adafruit/nrf52_adafruit_feather/nrf52_adafruit_feather.dts b/boards/adafruit/nrf52_adafruit_feather/nrf52_adafruit_feather.dts index 7c3694986705..05dbca9884db 100644 --- a/boards/adafruit/nrf52_adafruit_feather/nrf52_adafruit_feather.dts +++ b/boards/adafruit/nrf52_adafruit_feather/nrf52_adafruit_feather.dts @@ -120,12 +120,12 @@ slot0_partition: partition@c000 { label = "image-0"; - reg = <0x0000C000 0x32000>; + reg = <0x0000c000 0x32000>; }; slot1_partition: partition@3e000 { label = "image-1"; - reg = <0x0003E000 0x32000>; + reg = <0x0003e000 0x32000>; }; scratch_partition: partition@70000 { diff --git a/boards/adafruit/qt_py_esp32s3/support/openocd.cfg b/boards/adafruit/qt_py_esp32s3/support/openocd.cfg index 2f740b4a36ab..b45e13c53d01 100644 --- a/boards/adafruit/qt_py_esp32s3/support/openocd.cfg +++ b/boards/adafruit/qt_py_esp32s3/support/openocd.cfg @@ -1,5 +1,5 @@ -set ESP_RTOS none -set ESP32_ONLYCPU 1 +set ESP_RTOS Zephyr +set ESP_ONLYCPU 1 # Source the JTAG interface configuration file source [find interface/esp_usb_jtag.cfg] diff --git a/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040.dts b/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040.dts index d5717512f0df..78459f5fc1c5 100644 --- a/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040.dts +++ b/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040.dts @@ -40,11 +40,13 @@ &flash0 { reg = <0x10000000 DT_SIZE_M(8)>; + ranges = <0x0 0x10000000 DT_SIZE_M(8)>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + ranges; /* Reserved memory for the second stage bootloader */ second_stage_bootloader: partition@0 { diff --git a/boards/adafruit/trinket_m0/adafruit_trinket_m0.dts b/boards/adafruit/trinket_m0/adafruit_trinket_m0.dts index e130368f5d3d..d557aff3a79e 100644 --- a/boards/adafruit/trinket_m0/adafruit_trinket_m0.dts +++ b/boards/adafruit/trinket_m0/adafruit_trinket_m0.dts @@ -121,7 +121,7 @@ code_partition: partition@2000 { label = "code"; - reg = <0x2000 0x3A000>; + reg = <0x2000 0x3a000>; read-only; }; diff --git a/boards/adi/apard32690/apard32690_max32690_m4.dts b/boards/adi/apard32690/apard32690_max32690_m4.dts index 43575a724ac7..56beab32128c 100644 --- a/boards/adi/apard32690/apard32690_max32690_m4.dts +++ b/boards/adi/apard32690/apard32690_max32690_m4.dts @@ -259,7 +259,7 @@ pmod_spi: &spi4 { status = "okay"; port1 { - local-mac-address = [00 E0 22 FE DA C9]; + local-mac-address = [00 e0 22 fe da c9]; }; mdio { @@ -305,7 +305,7 @@ pmod_spi: &spi4 { * HPB doesn't support 7-clock latency which is default */ config-regs = <0x1000>; - config-reg-vals = <0x801F>; + config-reg-vals = <0x801f>; }; mem@1 { @@ -325,7 +325,7 @@ pmod_spi: &spi4 { * HPB doesn't support 7-clock latency which is default */ config-regs = <0x1000>; - config-reg-vals = <0x801F>; + config-reg-vals = <0x801f>; }; }; @@ -338,7 +338,7 @@ pmod_spi: &spi4 { compatible = "adi,max32-spixf-nor"; reg = <0x08000000 DT_SIZE_M(8)>; /* 64 Mbits */ qspi-max-frequency = <60000000>; - jedec-id = [c2 37 25]; + jedec-id = [c2 25 37]; sfdp-bfp = [e5 20 f1 ff ff ff ff 03 44 eb 08 6b 08 3b 04 bb fe ff ff ff ff ff 00 ff ff ff 44 eb 0c 20 0f 52 10 d8 00 ff d3 49 c9 00 83 a6 04 c4 44 03 17 38 diff --git a/boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz.dts b/boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz.dts index b8acb6ad6bf7..4358027c8494 100644 --- a/boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz.dts +++ b/boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz.dts @@ -130,12 +130,12 @@ slot1_partition: partition@8c000 { label = "image-1"; - reg = <0x0008C000 DT_SIZE_K(432)>; + reg = <0x0008c000 DT_SIZE_K(432)>; }; scratch_partition: partition@f8000 { label = "image-scratch"; - reg = <0x000F8000 DT_SIZE_K(16)>; + reg = <0x000f8000 DT_SIZE_K(16)>; }; storage_partition: partition@fc000 { @@ -221,7 +221,7 @@ spi-oa-protection; port1 { - local-mac-address = [00 E0 22 FE DA C8]; + local-mac-address = [00 e0 22 fe da c8]; }; mdio { diff --git a/boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz.yaml b/boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz.yaml index f7d2a100e2a5..818c6bf24ff7 100644 --- a/boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz.yaml +++ b/boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz.yaml @@ -1,5 +1,5 @@ identifier: adi_eval_adin1110ebz -name: ADI EVAL-ADIN1110EBZ evaulation board +name: ADI EVAL-ADIN1110EBZ evaluation board type: mcu arch: arm toolchain: diff --git a/boards/adi/eval_adin2111d1z/Kconfig.adi_eval_adin2111d1z b/boards/adi/eval_adin2111d1z/Kconfig.adi_eval_adin2111d1z new file mode 100644 index 000000000000..4a46363ecb72 --- /dev/null +++ b/boards/adi/eval_adin2111d1z/Kconfig.adi_eval_adin2111d1z @@ -0,0 +1,7 @@ +# EVAL ADIN2111D1Z board configuration + +# Copyright (c) 2023-2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ADI_EVAL_ADIN2111D1Z + select SOC_MAX32690_M4 diff --git a/boards/adi/eval_adin2111d1z/Kconfig.defconfig b/boards/adi/eval_adin2111d1z/Kconfig.defconfig new file mode 100644 index 000000000000..576d056d30f9 --- /dev/null +++ b/boards/adi/eval_adin2111d1z/Kconfig.defconfig @@ -0,0 +1,30 @@ +# ADI EVAL-ADIN2111D1Z board configuration + +# Copyright (c) 2024 BayLibre +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ADI_EVAL_ADIN2111D1Z + +config MDIO_INIT_PRIORITY + default 81 + depends on MDIO + +config PHY_INIT_PRIORITY + default 82 + depends on NET_L2_ETHERNET && ETH_DRIVER + +if NETWORKING + +config NET_L2_ETHERNET + default y + +if ETH_ADIN2111 + +config NET_IF_MAX_IPV4_COUNT + default 2 + +endif # ETH_ADIN2111 + +endif # NETWORKING + +endif # BOARD_ADI_EVAL_ADIN2111D1Z diff --git a/boards/adi/eval_adin2111d1z/adi_eval_adin2111d1z_max32690_m4.dts b/boards/adi/eval_adin2111d1z/adi_eval_adin2111d1z_max32690_m4.dts new file mode 100644 index 000000000000..61dbacef9b55 --- /dev/null +++ b/boards/adi/eval_adin2111d1z/adi_eval_adin2111d1z_max32690_m4.dts @@ -0,0 +1,193 @@ +/* + * Copyright (c) 2023-2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include + +/ { + model = "Analog Devices EVAL_ADIN2111D1Z"; + compatible = "adi,eval-adin2111d1z"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,code-partition = &code_partition; + }; + + bypass_relay: bypass_relay_uc { + compatible = "regulator-fixed"; + regulator-name = "bypass_relay"; + enable-gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + }; + + leds { + compatible = "gpio-leds"; + + orange_led: led_0 { + gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; + label = "LED0"; + }; + + green_led: led_1 { + gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; + label = "LED1"; + }; + + red_led: led_2 { + gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; + label = "LED2"; + }; + }; + + buttons { + compatible = "gpio-keys"; + + pb0: pb0 { + gpios = <&gpio4 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW2"; + zephyr,code = ; + }; + }; + + aliases { + bypassuc = &bypass_relay; + led0 = &orange_led; + led1 = &green_led; + led2 = &red_led; + sw0 = &pb0; + }; +}; + +&clk_ipo { + status = "okay"; +}; + +&clk_ibro { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0a_sda_p2_7 &i2c0a_scl_p2_8>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart0 { /*USB-C P4*/ + clock-source = ; + pinctrl-0 = <&uart0a_tx_p2_12 &uart0a_rx_p2_11>; + pinctrl-names = "default"; + current-speed = <115200>; + data-bits = <8>; + parity = "none"; + status = "okay"; +}; + +&spi0b_miso_p2_27 { + power-source = ; +}; + +&spi0b_mosi_p2_28 { + power-source = ; +}; + +&spi0b_sck_p2_29 { + power-source = ; +}; + +&spi0b_ss1_p2_26 { + power-source = ; +}; + +&spi0 { + pinctrl-0 = <&spi0b_miso_p2_27 &spi0b_mosi_p2_28 &spi0b_sck_p2_29>; + pinctrl-names = "default"; + cs-gpios = <&gpio2 26 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + status = "okay"; + + adin2111: adin2111@0 { + compatible = "adi,adin2111"; + reg = <0x0>; + spi-max-frequency = ; + int-gpios = <&gpio2 25 (GPIO_ACTIVE_LOW | MAX32_GPIO_VSEL_VDDIOH)>; + status = "okay"; + spi-oa; + spi-oa-protection; + + port1 { + local-mac-address = [00 aa 22 fe da c8]; + status = "okay"; + }; + + port2 { + local-mac-address = [00 aa 22 fe da c8]; + status = "okay"; + }; + + mdio { + compatible = "adi,adin2111-mdio"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ethernet-phy@1 { + reg = <0x1>; + compatible = "adi,adin2111-phy"; + status = "okay"; + }; + + ethernet-phy@2 { + reg = <0x2>; + compatible = "adi,adin2111-phy"; + status = "okay"; + }; + }; + }; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + code_partition: partition@0 { + label = "image"; + reg = <0x0 DT_SIZE_M(1)>; + }; + + storage_partition: partition@100000 { + label = "storage_partition"; + reg = <0x100000 DT_SIZE_K(256)>; + }; + }; +}; diff --git a/boards/adi/eval_adin2111d1z/adi_eval_adin2111d1z_max32690_m4.yaml b/boards/adi/eval_adin2111d1z/adi_eval_adin2111d1z_max32690_m4.yaml new file mode 100644 index 000000000000..86d641925c28 --- /dev/null +++ b/boards/adi/eval_adin2111d1z/adi_eval_adin2111d1z_max32690_m4.yaml @@ -0,0 +1,15 @@ +identifier: adi_eval_adin2111d1z/max32690/m4 +name: ADI EVAL-ADIN2111D1Z evaluation board +type: mcu +arch: arm +vendor: adi +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio + - serial + - spi + - i2c +ram: 1024 +flash: 3072 diff --git a/boards/adi/eval_adin2111d1z/adi_eval_adin2111d1z_max32690_m4_defconfig b/boards/adi/eval_adin2111d1z/adi_eval_adin2111d1z_max32690_m4_defconfig new file mode 100644 index 000000000000..d8802ba24c00 --- /dev/null +++ b/boards/adi/eval_adin2111d1z/adi_eval_adin2111d1z_max32690_m4_defconfig @@ -0,0 +1,21 @@ +# Copyright (c) 2023-2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable GPIO +CONFIG_GPIO=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable UART +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable regulators +CONFIG_REGULATOR=y + +CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/adi/eval_adin2111d1z/board.cmake b/boards/adi/eval_adin2111d1z/board.cmake new file mode 100644 index 000000000000..43b3efb7b59f --- /dev/null +++ b/boards/adi/eval_adin2111d1z/board.cmake @@ -0,0 +1,8 @@ +# Copyright (c) 2023-2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=MAX32690" "--reset-after-load") + +include(${ZEPHYR_BASE}/boards/common/openocd-adi-max32.boards.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/adi/eval_adin2111d1z/board.yml b/boards/adi/eval_adin2111d1z/board.yml new file mode 100644 index 000000000000..c7c1ceb5cb5d --- /dev/null +++ b/boards/adi/eval_adin2111d1z/board.yml @@ -0,0 +1,9 @@ +# Copyright (c) 2023-2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board: + name: adi_eval_adin2111d1z + full_name: EVAL-ADIN2111D1Z + vendor: adi + socs: + - name: max32690 diff --git a/boards/adi/eval_adin2111d1z/doc/img/adi_eval_adin2111d1z.webp b/boards/adi/eval_adin2111d1z/doc/img/adi_eval_adin2111d1z.webp new file mode 100644 index 000000000000..6812065532a3 Binary files /dev/null and b/boards/adi/eval_adin2111d1z/doc/img/adi_eval_adin2111d1z.webp differ diff --git a/boards/adi/eval_adin2111d1z/doc/index.rst b/boards/adi/eval_adin2111d1z/doc/index.rst new file mode 100644 index 000000000000..a34ec8907382 --- /dev/null +++ b/boards/adi/eval_adin2111d1z/doc/index.rst @@ -0,0 +1,218 @@ +.. zephyr:board:: adi_eval_adin2111d1z + +Overview +******** + +Board EVAL-ADIN2111D1Z is a small 4.5x6.5 cm board with ADIN2111 and MAX32690 +microcontroller. The board provides two 10BASE-T1L ports and acts as an +evaluation node in a daisy-chain configuration for both power and data. A +sensor can be connected to the board, analog or digital. In case of power loss, +data is forwarded to another node/board in the chain. The purpose is not to +create a power node, but to demonstrate the daisy-chaining and bypassing data +an on-board relay. + +Use-Cases +********* + +- Daisy-chained sensors (temperature, pressure, light, proximity, ....) using + 10BASE-T1L; in a room / building +- Daisy-chained power over a number (?) of boards +- Daisy-chain data over a number (?) of boards +- Read data from on-board temperature sensor ADT75 +- Demonstrate 10BASE-T1L communication over more nodes +- Use MAX32690 to control ADIN2111 over SPI interface + +Hardware +******** + ++---------------------------------------+----------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| Component | Function | Description | ++=======================================+==============================================+==================================================================================================================================================================================+ +| ADIN2111 | 2x 10BASE-T1L switch | Two port industrial ethernet switch with integrated 10BASE-T1L PHYs. Ultra-low power, various routing configurations. SPI communication to uC. | ++---------------------------------------+----------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| MAX32690 (68 TQFN-EP) | ARM M4 Microcontroller (uC) | Widely used across ADI, 120 MHz clock speed, 3 MB flash, 1 MB SRAM, 12-bit ADC, Bluetooth LE 5.2; security options; bootloader. Interfaces: 2x I2C; I2S; SPI; 2x UART; OWM; USB. | ++---------------------------------------+----------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| MAX17640 | DC/DC converter to 3.3V | Input +4.5V to +70V; output 400mA @3.3V. Temperature range -40 °C to +150 °C | ++---------------------------------------+----------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| MAX77324 | DC/DC converter to 1.8V | Input from MAX17640, output 1500mA @1.8V. VDDIO for ADIN2111 and uC, supply for other parts. | ++---------------------------------------+----------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| MAX77324 | DC/DC converter to 1.1V | Input from MAX17640, output 1500mA @1.1V. Supplies the uC and ADIN2111. | ++---------------------------------------+----------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| EEPROM Microchip AT24C64D | EEPROM memory I2C to uC | 64-Kbit (8192 x 8), 400 KHz Fast mode | ++---------------------------------------+----------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| Polarity correction (Bourns CD-HD201) | Bridge rectifier | VRRM 100V, IFSM 50A; IF(AV) 2A; VF(MAX) 0.85A. | ++---------------------------------------+----------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| Relay (TE IM21GR) | Bypasses data when power lost | VCOIL 3VDC, RCOIL 180 Ω; PCOIL 50 mW; Ultra highly sensitive. VSWITCH(MAX) 220VDC, ASWITCH(MAX) 2A. | ++---------------------------------------+----------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| Transformers (TDK ICI70CGI) | Ensures high impedance in power loss | LR 2.2 mH. Data and signal line chokes, without central tap. | ++---------------------------------------+----------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| Power inductors (Coilcraft MSD7342) | Power daisy-chain | L 47 μH; DCR(MAX) 0.42 Ω; SRF 9.5 MHz; ISAT(20% drop) 1.3 A; IRMS(both/one) = 0.61 / 0.86 A. | ++---------------------------------------+----------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| USB-C / JTAG | User / developer interfaces | | ++---------------------------------------+----------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| FTDI chip (FT230XQ-R) | Allows terminal connection to uC | USB to serial UART interface. | ++---------------------------------------+----------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| ADT75 temp. sensor | Temperature sensor | Range −25 °C to +100 °C, ±2 °C. Power consumption 79 μW @3.3V | ++---------------------------------------+----------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| PMOD | UART/SPI/I2C connection for external sensor | 12-pin female connector. | +| | OWM (1-wire) and one ADC input | Shares pins for ADC_0 and ADC_TRIG; OWM (1-wire) | ++---------------------------------------+----------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| 6 pin header | SPI pins for ADIN2111 | Only for testing | ++---------------------------------------+----------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| BLE antenna (Kyocera M310220) | 2.4 GHz on-board antenna | Freq. range 2400 –2485 MHz; G(PEAK) 1.7 dBi; linearly polarized. | ++---------------------------------------+----------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| Port 1/2 | 10BASE-T1L ports + DC power | 3-pin 2x Phoenix plug-in screw-terminal connectors | ++---------------------------------------+----------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| Ext. power | External power (not injected to T1L lines) | 2-pin Phoenix plug-in screw-terminal connector | ++---------------------------------------+----------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Why MAX32690? +============= + +Microcontroller ADI MAX32690 is an ARM Cortex-M4 device. It is ultra-efficient +and very low power, suitable for battery-powered devices. This microcontroller +(uC) is currently widely used across ADI. The uC has internal 3 MB flash +memory, which is necessary and enough for hosting a webpage and storing MAC and +IP addresses. Other uCs from the 326xx family have significantly less flash +memory (32670/1 has 384 KB; 32672 has 1 MB) and do not support external flash +memory. Other reasons for choosing MAX32690 are more GPIO pins, ability to +flash its firmware using USB interface and USB com port (not implemented yet at +the moment - planned), more security options; and also support for Bluetooth. + +Also, this evaluation board has a representative value showing off our uC, +ADIN2111 PHY, ADT75 temp. sensor, MAX17640 and MAX77324 DC/DC converters; all +connected on one board. + +Connectivity +============ + +- 2x 3 pin (+ - EARTH) Phoenix (P1, P2): Communication amplitude is 1V and 2.4V + as well. +- USB-C connector (P4) uses FTDI chip to talk to the uC. A terminal app UART + communication can be open to read/write to the uC. Also flashing a new + firmware for the uC might be done using UCB-C port and bootloader. +- JTAG/SWD (P5) exposed single wire debug interface of the uC to the connector. + A MAX32625PICO board can be used to download/debug the uC during firmware + development. +- Bluetooth: A Bluetooth connectivity is provided by the uC MAX32690 and an + integrated chip antenna on board. + +Sensors +======= + ++---------+-------+---------------+---------------------------------------------------------------------+ +| Analog | Type | Connector | Note | ++=========+=======+===============+=====================================================================+ +| Digital | I2C | PMOD (P6) | All share one PMOD connector. Only one protocol can be used at once | ++---------+-------+---------------+ | +| | SPI | PMOD (P6) | | ++---------+-------+---------------+ | +| | UART | PMOD (P6) | | ++---------+-------+---------------+---------------------------------------------------------------------+ +| | ADT75 | on-board (U5) | | ++---------+-------+---------------+---------------------------------------------------------------------+ +| | OWM | PMOD (P6) | | ++---------+-------+---------------+---------------------------------------------------------------------+ +| Analog | ADC | PMOD (P6) | 12-bit SAR. PMOD only ADC trigger and ADC_0 input. | ++---------+ +---------------+---------------------------------------------------------------------+ +| | | ADC_1 / ADC_4 | These pins available on the board (solder pins) for future use | ++---------+-------+---------------+---------------------------------------------------------------------+ + + +Power +===== + +There are three options to provide power to the board: USB-C, Ext. 2-pin +connector, 10BASE-T1L 3-pin connectors. + +The goal of the board is not to act as a power node, hence power provided from +different connectors will act differently. + +- USB-C (P4) + + - Only for board - NOT injected to PORT1/2 + - Powers up DC/DC → all circuitry with 3V3, 1V8 and 1V1 + +- Ext. 2 pin connector (P3) + + - 5V-58VDC + - Only for board - NOT injected to PORT1/2 + - Powers up DC/DC → all circuitry with 3V3, 1V8 and 1V1 + +- PORT 1 + + - IN/OUT power + - 7V-58VDC (voltage drop caused by bridge rectifier) + - Power for the board + - Powers up DC/DC → all circuitry with 3V3, 1V8 and 1V1 + - Forwarded to PORT 2 to daisy-chain power + +- PORT 2 + + - IN/OUT power + - 7V-58VDC (voltage drop caused by bridge rectifier) + - Power for the board + - Powers up DC/DC → all circuitry with 3V3, 1V8 and 1V1 + - Forwarded to PORT 1 to daisy-chain power + +Data/Power Bypass +================= + +- Power to PORT 1 + + - Board has power + - Relay connects PORT 1 and PORT 2 to ADIN2111 + - Power is also forwarded to PORT 2 + +- Power to PORT 1 is lost + + - Board does not have power + - Relay disconnects PORT 1 and PORT 2 from ADIN2111 + - Relay connects PORT 1 and PORT 2 together allowing daisy-chaining → data + goes to another node in the chain + - Power is NOT forwarded to PORT 2 + +- Data to PORT 1 + + - Board does not have power UNLESS power provided from Ext. or USB-C + - Relay connects PORT 1 and PORT 2 to ADIN2111 - Data from both ports goes + to ADIN2111 + - Transformers ensure ADIN2111 is disconnected from the lines, resistance + of lines connected to the transformers converges to infinite. + +- Data to PORT 1 and power is lost + + - Relay connects PORT 1 and PORT 2 together to daisy-chain data + - Relay connects PORT 1 and PORT 2 to ADIN2111 + - Power is NOT daisy-chained + - Data is processed by ADIN2111 + - Board does not have power and power is NOT provided from Ext. or USB-C + - Board does not have power, but power IS provided from Ext. or USB-C + +Relay Functionality +=================== + +- Relay is controlled by uC GPIO pin (pin 13 / P0.23) connected to N-FET + transistor + + - When configured correctly: + - if uC has power → relay has power → PORT 1 and PORT 2 connected to + ADIN2111 + - if uC hasn't got power → relay hasn't got power → PORT 1 and PORT 2 not + connected to ADIN2111 instead connected together to allow daisy-chain data + +- Inserting R41 will bypass uC controlling the relay => if board has power -> + relay has power -> PORT 1 and PORT 2 connected to ADIN2111 + + - This option is used in the first stage of testing HW and developing the + board's SW. + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: diff --git a/boards/adi/eval_adin2111ebz/adi_eval_adin2111ebz.dts b/boards/adi/eval_adin2111ebz/adi_eval_adin2111ebz.dts index 1e64014618af..245ac4af8f0a 100644 --- a/boards/adi/eval_adin2111ebz/adi_eval_adin2111ebz.dts +++ b/boards/adi/eval_adin2111ebz/adi_eval_adin2111ebz.dts @@ -109,12 +109,12 @@ slot1_partition: partition@8c000 { label = "image-1"; - reg = <0x0008C000 DT_SIZE_K(432)>; + reg = <0x0008c000 DT_SIZE_K(432)>; }; scratch_partition: partition@f8000 { label = "image-scratch"; - reg = <0x000F8000 DT_SIZE_K(16)>; + reg = <0x000f8000 DT_SIZE_K(16)>; }; storage_partition: partition@fc000 { @@ -184,11 +184,11 @@ spi-oa-protection; port1 { - local-mac-address = [00 E0 22 FE DA C9]; + local-mac-address = [00 e0 22 fe da c9]; }; port2 { - local-mac-address = [00 E0 22 FE DA D9]; + local-mac-address = [00 e0 22 fe da d9]; }; mdio { diff --git a/boards/adi/eval_adin2111ebz/adi_eval_adin2111ebz.yaml b/boards/adi/eval_adin2111ebz/adi_eval_adin2111ebz.yaml index 8c95a7748287..97d0cba14c87 100644 --- a/boards/adi/eval_adin2111ebz/adi_eval_adin2111ebz.yaml +++ b/boards/adi/eval_adin2111ebz/adi_eval_adin2111ebz.yaml @@ -1,5 +1,5 @@ identifier: adi_eval_adin2111ebz -name: ADI EVAL-ADIN2111EBZ evaulation board +name: ADI EVAL-ADIN2111EBZ evaluation board type: mcu arch: arm toolchain: diff --git a/boards/adi/max32655fthr/max32655fthr_max32655_m4.dts b/boards/adi/max32655fthr/max32655fthr_max32655_m4.dts index cfdb83d97944..cdcfd1849387 100644 --- a/boards/adi/max32655fthr/max32655fthr_max32655_m4.dts +++ b/boards/adi/max32655fthr/max32655fthr_max32655_m4.dts @@ -145,6 +145,12 @@ status = "okay"; }; +&i2c1 { + status = "okay"; + pinctrl-0 = <&i2c1_scl_p0_16 &i2c1_sda_p0_17>; + pinctrl-names = "default"; +}; + &i2c2 { status = "okay"; pinctrl-0 = <&i2c2_scl_p0_30 &i2c2_sda_p0_31>; @@ -155,6 +161,12 @@ status = "okay"; }; +&i2s0 { + status = "okay"; + pinctrl-0 = <&i2s_sck_p1_2 &i2s_ws_p1_3 &i2s_sdi_p1_4 &i2s_sdo_p1_5>; + pinctrl-names = "default"; +}; + &wdt0 { status = "okay"; }; diff --git a/boards/adi/max32657evkit/doc/index.rst b/boards/adi/max32657evkit/doc/index.rst index 99e243a9496b..323327c0d7b2 100644 --- a/boards/adi/max32657evkit/doc/index.rst +++ b/boards/adi/max32657evkit/doc/index.rst @@ -9,7 +9,7 @@ with digital signal processing (DSP) instructions, large flash and SRAM memories and the latest generation Bluetooth® 5.4 Low Energy (LE) radio. The nano-power modes increase battery life substantially. -The MAX32657 is qualified to operate at a temperature range of -20°C to +85°C. +The MAX32657 is qualified to operate at a temperature range of -20 °C to +85 °C. Bluetooth 5.4 LE radio supports Mesh, long-range (coded), and high-throughput modes. A cryptographic toolbox (CTB) provides advanced root of trust security features, including an Advanced Encryption Standard (AES) Engine, TRNG, and secure boot. @@ -344,10 +344,11 @@ using :zephyr:code-sample:`blinky` sample: :goals: build The above command will: - * Build a bootloader image (MCUboot) - * Build a TF-M (secure) firmware image - * Build Zephyr application as non-secure firmware image - * Merge them as ``tfm_merged.hex`` which contain all images. + +* Build a bootloader image (MCUboot) +* Build a TF-M (secure) firmware image +* Build Zephyr application as non-secure firmware image +* Merge them as ``tfm_merged.hex`` which contain all images. Note: @@ -517,8 +518,8 @@ see the following message in the terminal: ***** Booting Zephyr OS build v4.1.0 ***** Hello World! max32657evkit/max32657 -Building and flashing secure/non-secure with Arm |reg| TrustZone |reg| ----------------------------------------------------------------------- +Building and flashing secure/non-secure with Arm® TrustZone® +------------------------------------------------------------ The TF-M integration samples can be run using the ``max32657evkit/max32657/ns`` board target. To run we need to manually flash the resulting image (``tfm_merged.hex``) with a J-Link as follows diff --git a/boards/adi/max32658evkit/doc/index.rst b/boards/adi/max32658evkit/doc/index.rst index 89caa6766f41..5dcfd88846e4 100644 --- a/boards/adi/max32658evkit/doc/index.rst +++ b/boards/adi/max32658evkit/doc/index.rst @@ -9,7 +9,7 @@ with digital signal processing (DSP) instructions, large flash and SRAM memories and the latest generation Bluetooth® 5.4 Low Energy (LE) radio. The nano-power modes increase battery life substantially. -The MAX32658 is qualified to operate at a temperature range of -20°C to +85°C. +The MAX32658 is qualified to operate at a temperature range of -20 °C to +85 °C. Bluetooth 5.4 LE radio supports Mesh, long-range (coded), and high-throughput modes. A cryptographic toolbox (CTB) provides advanced root of trust security features, including an Advanced Encryption Standard (AES) Engine, TRNG, and secure boot. @@ -340,10 +340,11 @@ using :zephyr:code-sample:`blinky` sample: :goals: build The above command will: - * Build a bootloader image (MCUboot) - * Build a TF-M (secure) firmware image - * Build Zephyr application as non-secure firmware image - * Merge them as ``tfm_merged.hex`` which contain all images. + +* Build a bootloader image (MCUboot) +* Build a TF-M (secure) firmware image +* Build Zephyr application as non-secure firmware image +* Merge them as ``tfm_merged.hex`` which contain all images. Note: @@ -513,8 +514,8 @@ see the following message in the terminal: ***** Booting Zephyr OS build v4.1.0 ***** Hello World! max32658evkit/max32658 -Building and flashing secure/non-secure with Arm |reg| TrustZone |reg| ----------------------------------------------------------------------- +Building and flashing secure/non-secure with Arm® TrustZone® +------------------------------------------------------------ The TF-M integration samples can be run using the ``max32658evkit/max32658/ns`` board target. To run we need to manually flash the resulting image (``tfm_merged.hex``) with a J-Link as follows diff --git a/boards/adi/max32660evsys/doc/index.rst b/boards/adi/max32660evsys/doc/index.rst index c556fcbfeb9a..81cba1d497e0 100644 --- a/boards/adi/max32660evsys/doc/index.rst +++ b/boards/adi/max32660evsys/doc/index.rst @@ -30,7 +30,7 @@ Hardware - Low 1.1V VCORE Supply Voltage - 3.6V GPIO Operating Range - Internal LDO Provides Operation from Single Supply - - Wide Operating Temperature: -40°C to +105°C + - Wide Operating Temperature: -40 °C to +105 °C - Power Management Maximizes Uptime for Battery Applications diff --git a/boards/adi/max32662evkit/doc/index.rst b/boards/adi/max32662evkit/doc/index.rst index 32135be01292..fb2b7080d37a 100644 --- a/boards/adi/max32662evkit/doc/index.rst +++ b/boards/adi/max32662evkit/doc/index.rst @@ -21,7 +21,7 @@ Hardware - 16KB Unified Cache - Memory Protection Unit (MPU) - Dual- or Single-Supply Operation: 1.7V to 3.6V - - Wide Operating Temperature: -40°C to +105°C + - Wide Operating Temperature: -40 °C to +105 °C - Flexible Clocking Schemes diff --git a/boards/adi/max32670evkit/doc/index.rst b/boards/adi/max32670evkit/doc/index.rst index 4f5b57da3a67..eada6ba34b1e 100644 --- a/boards/adi/max32670evkit/doc/index.rst +++ b/boards/adi/max32670evkit/doc/index.rst @@ -30,7 +30,7 @@ Hardware - Ultra-Low 0.9V to 1.1V VCORE Supply Voltage - Internal LDO Operation from 1.7V to 3.6V SingleSupply - - Wide Operating Temperature: -40°C to +105°C + - Wide Operating Temperature: -40 °C to +105 °C - Flexible Clocking Schemes diff --git a/boards/adi/max32672evkit/doc/index.rst b/boards/adi/max32672evkit/doc/index.rst index 745adcd8a720..28f4e4b8d2d1 100644 --- a/boards/adi/max32672evkit/doc/index.rst +++ b/boards/adi/max32672evkit/doc/index.rst @@ -24,7 +24,7 @@ Hardware - 16KB Unified Cache with ECC - Resource Protection Unit (RPU) and MemoryProtection Unit (MPU) - Dual- or Single-Supply Operation, 1.7V to 3.6V - - Wide Operating Temperature: -40°C to +105°C + - Wide Operating Temperature: -40 °C to +105 °C - Flexible Clocking Schemes diff --git a/boards/adi/max32672fthr/doc/index.rst b/boards/adi/max32672fthr/doc/index.rst index c772136a8bda..ac02eb7f0247 100644 --- a/boards/adi/max32672fthr/doc/index.rst +++ b/boards/adi/max32672fthr/doc/index.rst @@ -34,7 +34,7 @@ Hardware - 16KB Unified Cache with ECC - Resource Protection Unit (RPU) and MemoryProtection Unit (MPU) - Dual- or Single-Supply Operation, 1.7V to 3.6V - - Wide Operating Temperature: -40°C to +105°C + - Wide Operating Temperature: -40 °C to +105 °C - Flexible Clocking Schemes diff --git a/boards/adi/max32672fthr/max32672fthr.dts b/boards/adi/max32672fthr/max32672fthr.dts index 397fb51a81ac..0ed07af00a13 100644 --- a/boards/adi/max32672fthr/max32672fthr.dts +++ b/boards/adi/max32672fthr/max32672fthr.dts @@ -130,7 +130,7 @@ status = "okay"; ssd1306: ssd1306@3d { - compatible = "solomon,ssd1306fb"; + compatible = "solomon,ssd1306"; reg = <0x3d>; width = <128>; height = <32>; diff --git a/boards/adi/max32675evkit/doc/index.rst b/boards/adi/max32675evkit/doc/index.rst index 6c66e204e0cd..fceae60dcc97 100644 --- a/boards/adi/max32675evkit/doc/index.rst +++ b/boards/adi/max32675evkit/doc/index.rst @@ -47,7 +47,7 @@ Hardware - TRNG Compliant to SP800-90B - Secure Nonvolatile Key Storage and AES-128/192/256 - Secure Bootloader to Protect IP/Firmware - - Wide, -40°C to +105°C Operating TemperatureRange + - Wide, -40 °C to +105 °C Operating TemperatureRange - Benefits and Features of MAX32675EVKIT: diff --git a/boards/adi/max32680evkit/doc/index.rst b/boards/adi/max32680evkit/doc/index.rst index a3c7d909efdb..a0960dcafd06 100644 --- a/boards/adi/max32680evkit/doc/index.rst +++ b/boards/adi/max32680evkit/doc/index.rst @@ -62,7 +62,7 @@ Hardware - TRNG - Secure Nonvolatile Key Storage and AES-128/192/256 - Secure Boot to Protect IP/Firmware - - Wide, -40°C to +85°C Operating Temperature + - Wide, -40 °C to +85 °C Operating Temperature - External devices connected to the MAX32680 EVKIT: diff --git a/boards/adi/sdp_k1/adi_sdp_k1.dts b/boards/adi/sdp_k1/adi_sdp_k1.dts index de7d9836bf55..7fc3e01b2f19 100644 --- a/boards/adi/sdp_k1/adi_sdp_k1.dts +++ b/boards/adi/sdp_k1/adi_sdp_k1.dts @@ -19,7 +19,7 @@ zephyr,shell-uart = &uart5; zephyr,sram = &sram0; zephyr,flash = &flash0; - zephyr,ccm = &ccm0; + zephyr,dtcm = &ccm0; }; leds { diff --git a/boards/adi/sdp_k1/doc/index.rst b/boards/adi/sdp_k1/doc/index.rst index d684c53374c9..0c0fb83db285 100644 --- a/boards/adi/sdp_k1/doc/index.rst +++ b/boards/adi/sdp_k1/doc/index.rst @@ -12,10 +12,11 @@ ADI components. - USB debug interface supporting CMSIS-DAP through a NXP Freescale microcontroller - Flexible board power supply - - USB VBUS 5 V max. 500 mA - - 5.5mm DC power jack 7 - 12 V min. 300 mA - - VIN from Arduino* compatible connectors - - VIN from 120-pin connector 5 V min. 300 mA + + - USB VBUS 5 V max. 500 mA + - 5.5mm DC power jack 7 - 12 V min. 300 mA + - VIN from Arduino* compatible connectors + - VIN from 120-pin connector 5 V min. 300 mA - 3 color LEDs (green, orange, red) and 1 status LED - One push-buttons: RESET - 16MB SDRAM @@ -29,7 +30,7 @@ Hardware ADI SDP-K1 provides the following hardware components: - STM32F469NIH6 in BGA216 package -- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU +- ARM® 32-bit Cortex®-M4 CPU with FPU - 180 MHz max CPU frequency - VDD of 1.8 V or 3.3 V - 2 MB Flash @@ -37,7 +38,7 @@ ADI SDP-K1 provides the following hardware components: - GPIO with external interrupt capability - LCD parallel interface, 8080/6800 modes - LCD TFT controller supporting up to XGA resolution -- MIPI |reg| DSI host controller supporting up to 720p 30Hz resolution +- MIPI® DSI host controller supporting up to 720p 30Hz resolution - 3x12-bit ADC with 24 channels - 2x12-bit D/A converters - RTC @@ -59,8 +60,9 @@ ADI SDP-K1 provides the following hardware components: - DMA Controller More information about STM32F469NI can be found here: - - `STM32F469NI product page`_ - - `STM32F469 reference manual`_ + +- `STM32F469NI product page`_ +- `STM32F469 reference manual`_ Supported Features ================== diff --git a/boards/aithinker/ai_m61_32s_kit/Kconfig.ai_m61_32s_kit b/boards/aithinker/ai_m61_32s_kit/Kconfig.ai_m61_32s_kit index 318e560e4e8e..2cc4ccde0155 100644 --- a/boards/aithinker/ai_m61_32s_kit/Kconfig.ai_m61_32s_kit +++ b/boards/aithinker/ai_m61_32s_kit/Kconfig.ai_m61_32s_kit @@ -1,6 +1,34 @@ -# Copyright (c) 2024-2025 MASSDRIVER EI (massdriver.space) +# Copyright (c) 2024-2026 MASSDRIVER EI (massdriver.space) # # SPDX-License-Identifier: Apache-2.0 config BOARD_AI_M61_32S_KIT - select SOC_BL618M65Q2I + select SOC_BL618M05Q2I if BOARD_REVISION_DEFAULT + select SOC_BL618M65Q2I if BOARD_REVISION_ALL + +if BOARD_AI_M61_32S_KIT + +config BOARD_REVISION_DEFAULT + bool + +config BOARD_REVISION_ALL + bool + +# Avoid adding 8 identical files +config CONSOLE + bool + default y + +config SERIAL + bool + default y + +config UART_CONSOLE + bool + default y + +config MEMC + bool + default y + +endif diff --git a/boards/aithinker/ai_m61_32s_kit/ai_m61_32s.dtsi b/boards/aithinker/ai_m61_32s_kit/ai_m61_32s.dtsi index d9f20cbd6867..ff7eee912de1 100644 --- a/boards/aithinker/ai_m61_32s_kit/ai_m61_32s.dtsi +++ b/boards/aithinker/ai_m61_32s_kit/ai_m61_32s.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2025 MASSDRIVER EI (massdriver.space) + * Copyright (c) 2025-2026 MASSDRIVER EI (massdriver.space) * * SPDX-License-Identifier: Apache-2.0 */ @@ -26,12 +26,9 @@ }; &flashctrl { - flash0: flash@A0000000 { - /* in-chip xmc flash die on ALL variant, NC pins noneffective - * in-module SOIC-8 gigadevice flash on non-ALL variant, NC pins effective - */ - compatible = "soc-nv-flash", "xmc,xm25qw64", "gd,gd25q64e"; - reg = <0xA0000000 (0x800000 - 0x2000)>; + flash0: flash@a0000000 { + compatible = "soc-nv-flash", "gd,gd25q64e"; + reg = <0xa0000000 (0x800000 - 0x2000)>; write-block-size = <256>; erase-block-size = ; diff --git a/boards/aithinker/ai_m61_32s_kit/ai_m61_32s_kit-pinctrl.dtsi b/boards/aithinker/ai_m61_32s_kit/ai_m61_32s_kit-pinctrl.dtsi index cfcf3670ef47..f9e75267840c 100644 --- a/boards/aithinker/ai_m61_32s_kit/ai_m61_32s_kit-pinctrl.dtsi +++ b/boards/aithinker/ai_m61_32s_kit/ai_m61_32s_kit-pinctrl.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2025 MASSDRIVER EI (massdriver.space) + * Copyright (c) 2025-2026 MASSDRIVER EI (massdriver.space) * * SPDX-License-Identifier: Apache-2.0 */ @@ -23,4 +23,13 @@ input-schmitt-enable; }; }; + + blue_pwm_pinctrl: pwm_pinctrl { + group1 { + pinmux = ; + bias-pull-up; + input-schmitt-enable; + drive-strength = <1>; + }; + }; }; diff --git a/boards/aithinker/ai_m61_32s_kit/ai_m61_32s_kit.dts b/boards/aithinker/ai_m61_32s_kit/ai_m61_32s_kit.dts index 7a3af709ba5f..b7f8551f6720 100644 --- a/boards/aithinker/ai_m61_32s_kit/ai_m61_32s_kit.dts +++ b/boards/aithinker/ai_m61_32s_kit/ai_m61_32s_kit.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2025 MASSDRIVER EI (massdriver.space) + * Copyright (c) 2025-2026 MASSDRIVER EI (massdriver.space) * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,66 +7,4 @@ /dts-v1/; #include "ai_m61_32s.dtsi" -#include "ai_m61_32s_kit-pinctrl.dtsi" - -/ { - model = "Ai-Thinker M61-32S development board"; - - aliases { - led0 = &blue_led; - sw0 = &button_0; - }; - - leds { - compatible = "gpio-leds"; - - blue_led: led_0 { - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; - label = "Blue - LED0"; - }; - - green_led: led_1 { - gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; - label = "Green - LED1"; - }; - - red_led: led_2 { - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - label = "Red - LED2"; - }; - - white_led: led_3 { - gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; - label = "White - LED3"; - }; - - warmwhite_led: led_4 { - gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>; - label = "Warm White - LED4"; - }; - }; - - buttons { - compatible = "gpio-keys"; - - button_0: sw0 { - gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; - zephyr,code = ; - }; - }; -}; - -&i2c0 { - status = "okay"; - clock-frequency = ; - - pinctrl-0 = <&i2c0_default>; - pinctrl-names = "default"; -}; - -&spi0 { - status = "okay"; - - pinctrl-0 = <&spi0_default>; - pinctrl-names = "default"; -}; +#include "ai_m61_32s_kit_common.dtsi" diff --git a/boards/aithinker/ai_m61_32s_kit/ai_m61_32s_kit.yaml b/boards/aithinker/ai_m61_32s_kit/ai_m61_32s_kit.yaml index a8214e0cfbdb..cb93dc1b3e1e 100644 --- a/boards/aithinker/ai_m61_32s_kit/ai_m61_32s_kit.yaml +++ b/boards/aithinker/ai_m61_32s_kit/ai_m61_32s_kit.yaml @@ -21,4 +21,5 @@ supported: - i2c - spi - flash + - pwm vendor: bflb diff --git a/boards/aithinker/ai_m61_32s_kit/ai_m61_32s_kit_ALL.overlay b/boards/aithinker/ai_m61_32s_kit/ai_m61_32s_kit_ALL.overlay new file mode 100644 index 000000000000..78ca5ad05c18 --- /dev/null +++ b/boards/aithinker/ai_m61_32s_kit/ai_m61_32s_kit_ALL.overlay @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2026 MASSDRIVER EI (massdriver.space) + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&flash0 { + /* ALL revision is BL618M65, which has an internal XMC Flash die + * instead of an external SOIC Flash. + */ + compatible = "soc-nv-flash", "xmc,xm25qw64"; +}; diff --git a/boards/aithinker/ai_m61_32s_kit/ai_m61_32s_kit_bl618m05q2i_safe_overclock.dts b/boards/aithinker/ai_m61_32s_kit/ai_m61_32s_kit_bl618m05q2i_safe_overclock.dts new file mode 100644 index 000000000000..31c58b656440 --- /dev/null +++ b/boards/aithinker/ai_m61_32s_kit/ai_m61_32s_kit_bl618m05q2i_safe_overclock.dts @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2026 MASSDRIVER EI (massdriver.space) + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include "ai_m61_32s.dtsi" +#include "ai_m61_32s_kit_common.dtsi" + +&clk_root { + /* Increased PLL speed used as FCLK */ + clocks = <&clk_wifipll BL61X_WIFIPLL_OC_480MHz>; +}; + +&clk_bclk { + /* 120 MHz BCLK and so Flash clock at this FCLK works for both revisions */ + divider = <4>; +}; + +&clk_flash { + /* 0 Units of delay for GD Flash but inverted RX */ + read-delay = <0>; + rx-clock-invert; + divider = <1>; +}; diff --git a/boards/aithinker/ai_m61_32s_kit/ai_m61_32s_kit_bl618m05q2i_safe_overclock_ALL.overlay b/boards/aithinker/ai_m61_32s_kit/ai_m61_32s_kit_bl618m05q2i_safe_overclock_ALL.overlay new file mode 100644 index 000000000000..34665912841b --- /dev/null +++ b/boards/aithinker/ai_m61_32s_kit/ai_m61_32s_kit_bl618m05q2i_safe_overclock_ALL.overlay @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2026 MASSDRIVER EI (massdriver.space) + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&flash0 { + /* ALL revision is BL618M65, which has an internal XMC Flash die + * instead of an external SOIC Flash. + */ + compatible = "soc-nv-flash", "xmc,xm25qw64"; +}; + +&clk_flash { + /* 1 Unit of delay (4 Cycles) for XMC Flash at 120 MHz Flash clock */ + read-delay = <1>; + /delete-property/ rx-clock-invert; +}; diff --git a/boards/aithinker/ai_m61_32s_kit/ai_m61_32s_kit_bl618m05q2i_unsafe_overclock.dts b/boards/aithinker/ai_m61_32s_kit/ai_m61_32s_kit_bl618m05q2i_unsafe_overclock.dts new file mode 100644 index 000000000000..32973b217c07 --- /dev/null +++ b/boards/aithinker/ai_m61_32s_kit/ai_m61_32s_kit_bl618m05q2i_unsafe_overclock.dts @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2026 MASSDRIVER EI (massdriver.space) + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include "ai_m61_32s.dtsi" +#include "ai_m61_32s_kit_common.dtsi" + +&clk_root { + /* Increased PLL speed used as FCLK */ + clocks = <&clk_wifipll BL61X_WIFIPLL_OCMAX_640MHz>; +}; + +®_soc { + /* SoC LDO at 1.25v to handle 640MHz FCLK*/ + regulator-init-microvolt = <1250000>; +}; + +/* With the settings used for their flash (Dual Out mode), the ALL and non-ALL revisions + * need different flash clock settings to work properly at 640MHz FCLK. + */ +&clk_bclk { + /* 120MHz BCLK */ + divider = <5>; +}; + +&clk_flash { + /* 0 Units of delay for GD Flash but inverted RX */ + read-delay = <0>; + rx-clock-invert; + divider = <1>; +}; diff --git a/boards/aithinker/ai_m61_32s_kit/ai_m61_32s_kit_bl618m05q2i_unsafe_overclock_ALL.overlay b/boards/aithinker/ai_m61_32s_kit/ai_m61_32s_kit_bl618m05q2i_unsafe_overclock_ALL.overlay new file mode 100644 index 000000000000..ce7067e85702 --- /dev/null +++ b/boards/aithinker/ai_m61_32s_kit/ai_m61_32s_kit_bl618m05q2i_unsafe_overclock_ALL.overlay @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2026 MASSDRIVER EI (massdriver.space) + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&flash0 { + /* ALL revision is BL618M65, which has an internal XMC Flash die + * instead of an external SOIC Flash. + */ + compatible = "soc-nv-flash", "xmc,xm25qw64"; +}; + +/* With the settings used for their flash (Dual Out mode), the ALL and non-ALL revisions + * need different flash clock settings to work properly at 640MHz FCLK. + */ + +&clk_bclk { + /* 100 + 20/3 (106.66...) MHz BCLK */ + divider = <6>; +}; + +&clk_flash { + /* 1 Unit of delay (4 Cycles) for XMC Flash at 100 + 20/3 (106.66...) MHz Flash clock */ + read-delay = <1>; + /delete-property/ rx-clock-invert; +}; diff --git a/boards/aithinker/ai_m61_32s_kit/ai_m61_32s_kit_common.dtsi b/boards/aithinker/ai_m61_32s_kit/ai_m61_32s_kit_common.dtsi new file mode 100644 index 000000000000..b16900e47073 --- /dev/null +++ b/boards/aithinker/ai_m61_32s_kit/ai_m61_32s_kit_common.dtsi @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2025-2026 MASSDRIVER EI (massdriver.space) + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "ai_m61_32s_kit-pinctrl.dtsi" + +/ { + model = "Ai-Thinker M61-32S development board"; + + aliases { + led0 = &blue_led; + sw0 = &button_0; + pwm-led0 = &blue_pwm_led; + }; + + leds { + compatible = "gpio-leds"; + + blue_led: led_0 { + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; + label = "Blue - LED0"; + }; + + green_led: led_1 { + gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + label = "Green - LED1"; + }; + + red_led: led_2 { + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + label = "Red - LED2"; + }; + + white_led: led_3 { + gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; + label = "White - LED3"; + }; + + warmwhite_led: led_4 { + gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>; + label = "Warm White - LED4"; + }; + }; + + pwmleds: pwmleds { + compatible = "pwm-leds"; + status = "disabled"; + + blue_pwm_led: led_pwm_0 { + pwms = <&pwm0 3 PWM_MSEC(1) PWM_POLARITY_NORMAL>; + label = "Blue - LED0 PWM"; + }; + + green_pwm_led: led_pwm_1 { + pwms = <&pwm0 2 PWM_MSEC(1) PWM_POLARITY_NORMAL>; + label = "Green - LED1 PWM"; + }; + + red_pwm_led: led_pwm_2 { + pwms = <&pwm0 0 PWM_MSEC(1) PWM_POLARITY_NORMAL>; + label = "Red - LED2 PWM"; + }; + + white_pwm_led: led_pwm_3 { + pwms = <&pwm0 1 PWM_MSEC(1) PWM_POLARITY_NORMAL>; + label = "White - LED3 PWM"; + }; + + warmwhite_pwm_led: led_pwm_4 { + pwms = <&pwm0 3 PWM_MSEC(1) PWM_POLARITY_NORMAL>; + label = "Warm White - LED4 PWM"; + }; + }; + + buttons { + compatible = "gpio-keys"; + + button_0: sw0 { + gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; + zephyr,code = ; + }; + }; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; +}; + +&spi0 { + status = "okay"; + + pinctrl-0 = <&spi0_default>; + pinctrl-names = "default"; +}; diff --git a/boards/aithinker/ai_m61_32s_kit/ai_m61_32s_kit_defconfig b/boards/aithinker/ai_m61_32s_kit/ai_m61_32s_kit_defconfig deleted file mode 100644 index f55755ffde6f..000000000000 --- a/boards/aithinker/ai_m61_32s_kit/ai_m61_32s_kit_defconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2025 MASSDRIVER EI (massdriver.space) -# -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y - -CONFIG_UART_CONSOLE=y - -CONFIG_MEMC=y diff --git a/boards/aithinker/ai_m61_32s_kit/board.cmake b/boards/aithinker/ai_m61_32s_kit/board.cmake index dd5219e96b90..632acd83129d 100644 --- a/boards/aithinker/ai_m61_32s_kit/board.cmake +++ b/boards/aithinker/ai_m61_32s_kit/board.cmake @@ -4,7 +4,7 @@ board_runner_args(openocd --cmd-pre-init "source [find bl61x.cfg]") -board_runner_args(openocd --use-elf --no-load --no-init) +board_runner_args(openocd --file-type=elf --no-load --no-init) board_runner_args(openocd --gdb-init "set mem inaccessible-by-default off") board_runner_args(openocd --gdb-init "set architecture riscv:rv32") board_runner_args(openocd --gdb-init "set remotetimeout 250") diff --git a/boards/aithinker/ai_m61_32s_kit/board.yml b/boards/aithinker/ai_m61_32s_kit/board.yml index 911910b4e4f9..40d0cd2f6d85 100644 --- a/boards/aithinker/ai_m61_32s_kit/board.yml +++ b/boards/aithinker/ai_m61_32s_kit/board.yml @@ -2,5 +2,15 @@ board: name: ai_m61_32s_kit full_name: Ai-Thinker M61-32S development board vendor: aithinker + revision: + format: custom + default: "DEFAULT" + exact: true + revisions: + - name: "ALL" + - name: "DEFAULT" socs: - - name: bl618m65q2i + - name: bl618m05q2i # ALL revision is bl618m65q2i, Kconfig repairs this 'error' + variants: + - name: "safe_overclock" + - name: "unsafe_overclock" diff --git a/boards/aithinker/ai_m61_32s_kit/doc/index.rst b/boards/aithinker/ai_m61_32s_kit/doc/index.rst index cd67db06aca5..678bc0363ab7 100644 --- a/boards/aithinker/ai_m61_32s_kit/doc/index.rst +++ b/boards/aithinker/ai_m61_32s_kit/doc/index.rst @@ -29,6 +29,15 @@ System Clock The M61 (BL618) Development Board is configured to run at maximum speed (320MHz) and can be overclocked to 480 MHz. +This board provides demonstration configurations for the overclocking of the BL618 SoC clocks: + +- ``ai_m61_32s_kit/bl618m05q2i/safe_overclock`` demonstrates 120MHz BCLK and 480MHz core clock on both variants. This nets a Coremark score up to 1600. +- ``ai_m61_32s_kit/bl618m05q2i/unsafe_overclock`` demonstrates 120MHz or 106MHz BCLK and 640MHz core clock with higher core voltages. This nets a Coremark score up to 2100. + +If you are using the ALL variant, please use :``ai_m61_32s_kit@ALL``. + +When overclocking, DMA and DMA-using drivers will not work properly. + Serial Port =========== @@ -69,7 +78,7 @@ Samples .. code-block:: console *** Booting Zephyr OS build v4.3.0 *** - Hello World! ai_m61_32s_kit/bl618m65q2i + Hello World! ai_m61_32s_kit/bl618m05q2i Congratulations, you have ``ai_m61_32s_kit`` configured and running Zephyr. diff --git a/boards/aithinker/ai_m61_32s_kit/pre_dt_board.cmake b/boards/aithinker/ai_m61_32s_kit/pre_dt_board.cmake new file mode 100644 index 000000000000..c3a69b990ff0 --- /dev/null +++ b/boards/aithinker/ai_m61_32s_kit/pre_dt_board.cmake @@ -0,0 +1,4 @@ +# Copyright The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") diff --git a/boards/aithinker/ai_m61_32s_kit/revision.cmake b/boards/aithinker/ai_m61_32s_kit/revision.cmake new file mode 100644 index 000000000000..f6d6fc64e4df --- /dev/null +++ b/boards/aithinker/ai_m61_32s_kit/revision.cmake @@ -0,0 +1,8 @@ +set(BOARD_REVISIONS "ALL" "DEFAULT") +if(NOT DEFINED BOARD_REVISION) + set(BOARD_REVISION "DEFAULT") +else() + if(NOT BOARD_REVISION IN_LIST BOARD_REVISIONS) + message(FATAL_ERROR "${BOARD_REVISION} is not a valid revision for ai_m61_32s_kit Accepted revisions: ${BOARD_REVISIONS}") + endif() +endif() diff --git a/boards/aithinker/ai_m62_12f_kit/ai_m62_12f.dtsi b/boards/aithinker/ai_m62_12f_kit/ai_m62_12f.dtsi index 0c861700cdba..8ac9e3eb7ea8 100644 --- a/boards/aithinker/ai_m62_12f_kit/ai_m62_12f.dtsi +++ b/boards/aithinker/ai_m62_12f_kit/ai_m62_12f.dtsi @@ -26,9 +26,9 @@ }; &flashctrl { - flash0: flash@A0000000 { + flash0: flash@a0000000 { compatible = "soc-nv-flash", "gd,gd25lq32d"; - reg = <0xA0000000 (0x400000 - 0x2000)>; + reg = <0xa0000000 (0x400000 - 0x2000)>; write-block-size = <256>; erase-block-size = ; diff --git a/boards/aithinker/ai_m62_12f_kit/ai_m62_12f_kit-pinctrl.dtsi b/boards/aithinker/ai_m62_12f_kit/ai_m62_12f_kit-pinctrl.dtsi index 285589db170f..9b4e0853fb60 100644 --- a/boards/aithinker/ai_m62_12f_kit/ai_m62_12f_kit-pinctrl.dtsi +++ b/boards/aithinker/ai_m62_12f_kit/ai_m62_12f_kit-pinctrl.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2024-2025 MASSDRIVER EI (massdriver.space) + * Copyright (c) 2024-2026 MASSDRIVER EI (massdriver.space) * * SPDX-License-Identifier: Apache-2.0 */ @@ -23,4 +23,19 @@ input-schmitt-enable; }; }; + + white_pwm_pinctrl: white_pwm_pinctrl { + group1 { + pinmux = ; + bias-pull-up; + input-schmitt-enable; + drive-strength = <1>; + }; + }; + + adc0_default: adc0_default { + group1 { + pinmux = ; + }; + }; }; diff --git a/boards/aithinker/ai_m62_12f_kit/ai_m62_12f_kit.dts b/boards/aithinker/ai_m62_12f_kit/ai_m62_12f_kit.dts index 88f17e14053f..9cc967abb9df 100644 --- a/boards/aithinker/ai_m62_12f_kit/ai_m62_12f_kit.dts +++ b/boards/aithinker/ai_m62_12f_kit/ai_m62_12f_kit.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2024-2025 MASSDRIVER EI (massdriver.space) + * Copyright (c) 2024-2026 MASSDRIVER EI (massdriver.space) * * SPDX-License-Identifier: Apache-2.0 */ @@ -14,6 +14,7 @@ aliases { led0 = &blue_led; + pwm-led0 = &white_pwm_led; sw0 = &button_0; }; @@ -46,6 +47,36 @@ }; }; + pwmleds: pwmleds { + compatible = "pwm-leds"; + status = "disabled"; + + blue_pwm_led: led_pwm_0 { + pwms = <&pwm0 0 PWM_MSEC(1) PWM_POLARITY_NORMAL>; + label = "Blue - LED0 PWM"; + }; + + green_pwm_led: led_pwm_1 { + pwms = <&pwm0 2 PWM_MSEC(1) PWM_POLARITY_NORMAL>; + label = "Green - LED1 PWM"; + }; + + red_pwm_led: led_pwm_2 { + pwms = <&pwm0 1 PWM_MSEC(1) PWM_POLARITY_NORMAL>; + label = "Red - LED2 PWM"; + }; + + white_pwm_led: led_pwm_3 { + pwms = <&pwm0 1 PWM_MSEC(1) PWM_POLARITY_NORMAL>; + label = "White - LED3 PWM"; + }; + + warmwhite_pwm_led: led_pwm_4 { + pwms = <&pwm0 3 PWM_MSEC(1) PWM_POLARITY_NORMAL>; + label = "Warm White - LED4 PWM"; + }; + }; + buttons { compatible = "gpio-keys"; @@ -54,6 +85,10 @@ zephyr,code = ; }; }; + + zephyr,user { + io-channels = <&adc0 0>; + }; }; &i2c0 { @@ -70,3 +105,19 @@ pinctrl-0 = <&spi0_default>; pinctrl-names = "default"; }; + +&adc0 { + status = "okay"; + + pinctrl-0 = <&adc0_default>; + pinctrl-names = "default"; + + channel@0 { + reg = <0>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <16>; + zephyr,input-positive = <0>; + }; +}; diff --git a/boards/aithinker/ai_m62_12f_kit/ai_m62_12f_kit.yaml b/boards/aithinker/ai_m62_12f_kit/ai_m62_12f_kit.yaml index 66afa3dafeb1..a7bdae2167f1 100644 --- a/boards/aithinker/ai_m62_12f_kit/ai_m62_12f_kit.yaml +++ b/boards/aithinker/ai_m62_12f_kit/ai_m62_12f_kit.yaml @@ -19,7 +19,9 @@ supported: - uart - dma - i2c - - display - spi - flash + - input + - pwm + - adc vendor: bflb diff --git a/boards/aithinker/ai_m62_12f_kit/board.cmake b/boards/aithinker/ai_m62_12f_kit/board.cmake index dd5219e96b90..632acd83129d 100644 --- a/boards/aithinker/ai_m62_12f_kit/board.cmake +++ b/boards/aithinker/ai_m62_12f_kit/board.cmake @@ -4,7 +4,7 @@ board_runner_args(openocd --cmd-pre-init "source [find bl61x.cfg]") -board_runner_args(openocd --use-elf --no-load --no-init) +board_runner_args(openocd --file-type=elf --no-load --no-init) board_runner_args(openocd --gdb-init "set mem inaccessible-by-default off") board_runner_args(openocd --gdb-init "set architecture riscv:rv32") board_runner_args(openocd --gdb-init "set remotetimeout 250") diff --git a/boards/aithinker/ai_m62_12f_kit/pre_dt_board.cmake b/boards/aithinker/ai_m62_12f_kit/pre_dt_board.cmake new file mode 100644 index 000000000000..c3a69b990ff0 --- /dev/null +++ b/boards/aithinker/ai_m62_12f_kit/pre_dt_board.cmake @@ -0,0 +1,4 @@ +# Copyright The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") diff --git a/boards/aithinker/ai_wb2_12f_kit/ai_wb2_12f_kit-pinctrl.dtsi b/boards/aithinker/ai_wb2_12f_kit/ai_wb2_12f_kit-pinctrl.dtsi index a60c6948db4f..ffe8585718f5 100644 --- a/boards/aithinker/ai_wb2_12f_kit/ai_wb2_12f_kit-pinctrl.dtsi +++ b/boards/aithinker/ai_wb2_12f_kit/ai_wb2_12f_kit-pinctrl.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2024-2025 MASSDRIVER EI (massdriver.space) + * Copyright (c) 2024-2026 MASSDRIVER EI (massdriver.space) * * SPDX-License-Identifier: Apache-2.0 */ @@ -23,4 +23,19 @@ input-schmitt-enable; }; }; + + blue_pwm_pinctrl: blue_pwm_pinctrl { + group1 { + pinmux = ; + bias-pull-up; + input-schmitt-enable; + drive-strength = <1>; + }; + }; + + adc0_default: adc0_default { + group1 { + pinmux = ; + }; + }; }; diff --git a/boards/aithinker/ai_wb2_12f_kit/ai_wb2_12f_kit.dts b/boards/aithinker/ai_wb2_12f_kit/ai_wb2_12f_kit.dts index 8c41dca95807..d58c3879cc6e 100644 --- a/boards/aithinker/ai_wb2_12f_kit/ai_wb2_12f_kit.dts +++ b/boards/aithinker/ai_wb2_12f_kit/ai_wb2_12f_kit.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2024-2025 MASSDRIVER EI (massdriver.space) + * Copyright (c) 2024-2026 MASSDRIVER EI (massdriver.space) * * SPDX-License-Identifier: Apache-2.0 */ @@ -14,6 +14,7 @@ aliases { led0 = &blue_led; + pwm-led0 = &blue_pwm_led; sw0 = &button_0; }; @@ -36,6 +37,26 @@ }; }; + pwmleds: pwmleds { + compatible = "pwm-leds"; + status = "disabled"; + + blue_pwm_led: led_pwm_0 { + pwms = <&pwm0 3 PWM_MSEC(1) PWM_POLARITY_NORMAL>; + label = "Blue - LED0 PWM"; + }; + + green_pwm_led: led_pwm_1 { + pwms = <&pwm0 2 PWM_MSEC(1) PWM_POLARITY_NORMAL>; + label = "Green - LED1 PWM"; + }; + + red_pwm_led: led_pwm_2 { + pwms = <&pwm0 4 PWM_MSEC(1) PWM_POLARITY_NORMAL>; + label = "Red - LED2 PWM"; + }; + }; + buttons { compatible = "gpio-keys"; @@ -44,6 +65,10 @@ zephyr,code = ; }; }; + + zephyr,user { + io-channels = <&adc0 0>; + }; }; &i2c0 { @@ -60,3 +85,19 @@ pinctrl-0 = <&spi0_default>; pinctrl-names = "default"; }; + +&adc0 { + status = "okay"; + + pinctrl-0 = <&adc0_default>; + pinctrl-names = "default"; + + channel@0 { + reg = <0>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <16>; + zephyr,input-positive = <10>; + }; +}; diff --git a/boards/aithinker/ai_wb2_12f_kit/ai_wb2_12f_kit.yaml b/boards/aithinker/ai_wb2_12f_kit/ai_wb2_12f_kit.yaml index 30bd05a43d7b..e55219b611f5 100644 --- a/boards/aithinker/ai_wb2_12f_kit/ai_wb2_12f_kit.yaml +++ b/boards/aithinker/ai_wb2_12f_kit/ai_wb2_12f_kit.yaml @@ -21,4 +21,7 @@ supported: - i2c - spi - flash + - input + - pwm + - adc vendor: bflb diff --git a/boards/aithinker/ai_wb2_12f_kit/board.cmake b/boards/aithinker/ai_wb2_12f_kit/board.cmake index 82839f838940..76cb813ca7a7 100644 --- a/boards/aithinker/ai_wb2_12f_kit/board.cmake +++ b/boards/aithinker/ai_wb2_12f_kit/board.cmake @@ -4,7 +4,7 @@ board_runner_args(openocd --cmd-pre-init "source [find bl60x.cfg]") -board_runner_args(openocd --use-elf --no-load --no-init) +board_runner_args(openocd --file-type=elf --no-load --no-init) board_runner_args(openocd --gdb-init "set mem inaccessible-by-default off") board_runner_args(openocd --gdb-init "set architecture riscv:rv32") board_runner_args(openocd --gdb-init "set remotetimeout 250") diff --git a/boards/aithinker/ai_wb2_12f_kit/pre_dt_board.cmake b/boards/aithinker/ai_wb2_12f_kit/pre_dt_board.cmake new file mode 100644 index 000000000000..c3a69b990ff0 --- /dev/null +++ b/boards/aithinker/ai_wb2_12f_kit/pre_dt_board.cmake @@ -0,0 +1,4 @@ +# Copyright The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") diff --git a/boards/aithinker/esp32_cam/support/openocd.cfg b/boards/aithinker/esp32_cam/support/openocd.cfg index 338e6e4e6eae..41411e37140e 100644 --- a/boards/aithinker/esp32_cam/support/openocd.cfg +++ b/boards/aithinker/esp32_cam/support/openocd.cfg @@ -1,5 +1,5 @@ -set ESP_RTOS none -set ESP32_ONLYCPU 1 +set ESP_RTOS Zephyr +set ESP_ONLYCPU 1 source [find interface/ftdi/esp32_devkitj_v1.cfg] source [find target/esp32.cfg] diff --git a/boards/alientek/dnesp32s3b/Kconfig.defconfig b/boards/alientek/dnesp32s3b/Kconfig.defconfig new file mode 100644 index 000000000000..61a23190e331 --- /dev/null +++ b/boards/alientek/dnesp32s3b/Kconfig.defconfig @@ -0,0 +1,28 @@ +# Copyright (c) 2025 Chen Xingyu +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_DNESP32S3B + +if DISPLAY + +# Turn on the LCD backlight +config REGULATOR + default y + +if LVGL + +config LV_Z_BITS_PER_PIXEL + default 16 + +choice LV_COLOR_DEPTH + default LV_COLOR_DEPTH_16 +endchoice + +config LV_COLOR_16_SWAP + default y + +endif # LVGL + +endif # DISPLAY + +endif # BOARD_DNESP32S3B diff --git a/boards/alientek/dnesp32s3b/dnesp32s3b-pinctrl.dtsi b/boards/alientek/dnesp32s3b/dnesp32s3b-pinctrl.dtsi index 290d8e09d494..bfe634ec21d1 100644 --- a/boards/alientek/dnesp32s3b/dnesp32s3b-pinctrl.dtsi +++ b/boards/alientek/dnesp32s3b/dnesp32s3b-pinctrl.dtsi @@ -27,4 +27,31 @@ drive-open-drain; }; }; + + lcd_cam_default: lcd_cam_default { + group1 { + pinmux = , /* LCD_D0 */ + , /* LCD_D1 */ + , /* LCD_D2 */ + , /* LCD_D3 */ + , /* LCD_D4 */ + , /* LCD_D5 */ + , /* LCD_D6 */ + , /* LCD_D7 */ + , /* LCD_WR */ + ; /* LCD_RS */ + output-enable; + bias-disable; + }; + + group2 { + /* Not really used by display, but we need to pull it up + * to avoid the floating state stucking the bus in read + * mode. + */ + pinmux = ; /* LCD_RD */ + output-enable; + bias-pull-up; + }; + }; }; diff --git a/boards/alientek/dnesp32s3b/dnesp32s3b_procpu.dts b/boards/alientek/dnesp32s3b/dnesp32s3b_procpu.dts index 63593667f2f9..834e7658e68c 100644 --- a/boards/alientek/dnesp32s3b/dnesp32s3b_procpu.dts +++ b/boards/alientek/dnesp32s3b/dnesp32s3b_procpu.dts @@ -29,6 +29,7 @@ zephyr,flash = &flash0; zephyr,code-partition = &slot0_partition; zephyr,bt-hci = &esp32_bt_hci; + zephyr,display = &st7789v; }; leds { @@ -66,6 +67,13 @@ zephyr,code = ; }; }; + + lcd_bl: LCD_BL { + compatible = "regulator-fixed"; + regulator-name = "LCD_BL"; + regulator-boot-on; + enable-gpios = <&io_expander 7 GPIO_ACTIVE_HIGH>; + }; }; &usb_serial { @@ -120,3 +128,42 @@ &esp32_bt_hci { status = "okay"; }; + +&dma { + status = "okay"; +}; + +&lcd_cam { + status = "okay"; + pinctrl-0 = <&lcd_cam_default>; + pinctrl-names = "default"; +}; + +&lcd_cam_disp { + status = "okay"; + cs-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; + + st7789v: st7789v@0 { + compatible = "sitronix,st7789v"; + reg = <0>; + mipi-max-frequency = ; + mipi-mode = "MIPI_DBI_MODE_8080_BUS_8_BIT"; + width = <320>; + height = <240>; + x-offset = <0>; + y-offset = <0>; + vcom = <0x20>; + gctrl = <0x35>; + mdac = <0x60>; /* RGB order, swap XY, mirror X */ + lcm = <0x2c>; + colmod = <0x55>; /* RGB565 16bit */ + gamma = <0x01>; + porch-param = [0c 0c 00 33 33]; + cmd2en-param = [5a 69 02 01]; + pwctrl1-param = [a4 a1]; + pvgam-param = [d0 00 02 07 0a 28 32 44 42 06 0e 12 14 17]; + nvgam-param = [d0 00 02 07 0a 28 31 54 47 0e 1c 17 1b 1e]; + ram-param = [00 f0]; + rgb-param = [40 02 14]; + }; +}; diff --git a/boards/alientek/dnesp32s3b/dnesp32s3b_procpu.yaml b/boards/alientek/dnesp32s3b/dnesp32s3b_procpu.yaml index 7e81839b5714..5979584d0ea3 100644 --- a/boards/alientek/dnesp32s3b/dnesp32s3b_procpu.yaml +++ b/boards/alientek/dnesp32s3b/dnesp32s3b_procpu.yaml @@ -5,6 +5,7 @@ arch: xtensa toolchain: - zephyr supported: + - display - gpio - uart - i2c diff --git a/boards/alientek/dnesp32s3b/doc/index.rst b/boards/alientek/dnesp32s3b/doc/index.rst index fb6222e659ee..ad4491bf5d03 100644 --- a/boards/alientek/dnesp32s3b/doc/index.rst +++ b/boards/alientek/dnesp32s3b/doc/index.rst @@ -71,6 +71,7 @@ The following code samples run out of the box on the DNESP32S3B board: * :zephyr:code-sample:`blinky` * :zephyr:code-sample:`button` +* :zephyr:code-sample:`lvgl-demos` References ********** diff --git a/boards/alientek/dnesp32s3b/support/openocd.cfg b/boards/alientek/dnesp32s3b/support/openocd.cfg index 625341a5aa87..7b2d51e21ad0 100644 --- a/boards/alientek/dnesp32s3b/support/openocd.cfg +++ b/boards/alientek/dnesp32s3b/support/openocd.cfg @@ -1,8 +1,8 @@ # Copyright (c) 2024 Joel Guittet # SPDX-License-Identifier: Apache-2.0 -set ESP_RTOS none -set ESP32_ONLYCPU 1 +set ESP_RTOS Zephyr +set ESP_ONLYCPU 1 # Source the JTAG interface configuration file source [find interface/esp_usb_jtag.cfg] diff --git a/boards/alientek/pandora_stm32l475/doc/index.rst b/boards/alientek/pandora_stm32l475/doc/index.rst index 671570b64099..1adf2fe76af2 100644 --- a/boards/alientek/pandora_stm32l475/doc/index.rst +++ b/boards/alientek/pandora_stm32l475/doc/index.rst @@ -39,47 +39,57 @@ Hardware The STM32L475VE SoC provides the following hardware features: - Ultra-low-power with FlexPowerControl (down to 130 nA Standby mode and 100 uA/MHz run mode) -- Core: ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU, frequency up to 80 MHz, 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) +- Core: ARM® 32-bit Cortex®-M4 CPU with FPU, frequency up to 80 MHz, 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) - Clock Sources: - - 4 to 48 MHz crystal oscillator - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) - - Internal low-power 32 kHz RC ( |plusminus| 5%) - - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by - LSE (better than |plusminus| 0.25 % accuracy) - - 3 PLLs for system clock, USB, audio, ADC + + - 4 to 48 MHz crystal oscillator + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC (±1%) + - Internal low-power 32 kHz RC (±5%) + - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by + LSE (better than ±0.25 % accuracy) + - 3 PLLs for system clock, USB, audio, ADC + - RTC with HW calendar, alarms and calibration - 16x timers: - - 2x 16-bit advanced motor-control - - 2x 32-bit and 7x 16-bit general purpose - - 2x 16-bit basic - - 2x low-power 16-bit timers (available in Stop mode) - - 2x watchdogs - - SysTick timer + + - 2x 16-bit advanced motor-control + - 2x 32-bit and 7x 16-bit general purpose + - 2x 16-bit basic + - 2x low-power 16-bit timers (available in Stop mode) + - 2x watchdogs + - SysTick timer + - Up to 82 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V + - Memories - - Up to 1 MB Flash, 2 banks read-while-write, proprietary code readout protection - - Up to 128 KB of SRAM including 32 KB with hardware parity check - - External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories - - Quad SPI memory interface + + - Up to 1 MB Flash, 2 banks read-while-write, proprietary code readout protection + - Up to 128 KB of SRAM including 32 KB with hardware parity check + - External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories + - Quad SPI memory interface - 4x digital filters for sigma delta modulator - Rich analog peripherals (independent supply) - - 3x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 uA/MSPS - - 2x 12-bit DAC, low-power sample and hold - - 2x operational amplifiers with built-in PGA - - 2x ultra-low-power comparators + + - 3x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 uA/MSPS + - 2x 12-bit DAC, low-power sample and hold + - 2x operational amplifiers with built-in PGA + - 2x ultra-low-power comparators + - 18x communication interfaces - - USB OTG 2.0 full-speed, LPM and BCD - - 2x SAIs (serial audio interface) - - 3x I2C FM+(1 Mbit/s), SMBus/PMBus - - 6x USARTs (ISO 7816, LIN, IrDA, modem) - - 3x SPIs (4x SPIs with the Quad SPI) - - CAN (2.0B Active) and SDMMC interface - - SWPMI single wire protocol master I/F + + - USB OTG 2.0 full-speed, LPM and BCD + - 2x SAIs (serial audio interface) + - 3x I2C FM+(1 Mbit/s), SMBus/PMBus + - 6x USARTs (ISO 7816, LIN, IrDA, modem) + - 3x SPIs (4x SPIs with the Quad SPI) + - CAN (2.0B Active) and SDMMC interface + - SWPMI single wire protocol master I/F + - 14-channel DMA controller - True random number generator - CRC calculation unit, 96-bit unique ID -- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell™ Supported Features diff --git a/boards/ambiq/apollo510_evb/apollo510_evb.dts b/boards/ambiq/apollo510_evb/apollo510_evb.dts index 0be49ee6784b..869b1d0463c5 100644 --- a/boards/ambiq/apollo510_evb/apollo510_evb.dts +++ b/boards/ambiq/apollo510_evb/apollo510_evb.dts @@ -175,7 +175,7 @@ mspi-hardware-ce-num = <0>; mspi-dqs-enable; read-command = <0x20>; - write-command = <0xA0>; + write-command = <0xa0>; command-length = "INSTR_1_BYTE"; address-length = "ADDR_4_BYTE"; rx-dummy = <7>; @@ -213,8 +213,8 @@ mspi-data-rate = "MSPI_DATA_RATE_SINGLE"; mspi-dqs-enable; mspi-hardware-ce-num = <0>; - read-command = <0xCC>; - write-command = <0x8E>; + read-command = <0xcc>; + write-command = <0x8e>; command-length = "INSTR_1_BYTE"; address-length = "ADDR_4_BYTE"; /* Avoid use of 3 byte address if Ambiq MSPI */ rx-dummy = <16>; diff --git a/boards/amd/versal2_apu/Kconfig.versal2_apu b/boards/amd/versal2_apu/Kconfig.versal2_apu new file mode 100644 index 000000000000..3db92f00b50a --- /dev/null +++ b/boards/amd/versal2_apu/Kconfig.versal2_apu @@ -0,0 +1,8 @@ +# +# Copyright (c) 2025 Advanced Micro Devices, Inc. +# +# SPDX-License-Identifier: Apache-2.0 +# + +config BOARD_VERSAL2_APU + select SOC_AMD_VERSAL2_APU diff --git a/boards/amd/versal2_apu/board.cmake b/boards/amd/versal2_apu/board.cmake new file mode 100644 index 000000000000..a624cc396d3c --- /dev/null +++ b/boards/amd/versal2_apu/board.cmake @@ -0,0 +1,7 @@ +# +# Copyright (c) 2025 Advanced Micro Devices, Inc. +# +# SPDX-License-Identifier: Apache-2.0 +# + +include(${ZEPHYR_BASE}/boards/common/xsdb.board.cmake) diff --git a/boards/amd/versal2_apu/board.yml b/boards/amd/versal2_apu/board.yml new file mode 100644 index 000000000000..afb31dac30d0 --- /dev/null +++ b/boards/amd/versal2_apu/board.yml @@ -0,0 +1,9 @@ +# Copyright (c) 2025, Advanced Micro Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board: + name: versal2_apu + full_name: AMD Versal Gen 2 APU Development Board + vendor: amd + socs: + - name: amd_versal2_apu diff --git a/boards/amd/versal2_apu/doc/index.rst b/boards/amd/versal2_apu/doc/index.rst new file mode 100644 index 000000000000..81b4b0585a82 --- /dev/null +++ b/boards/amd/versal2_apu/doc/index.rst @@ -0,0 +1,74 @@ +.. zephyr:board:: versal2_apu + +Overview +******** +This configuration provides support for the APU(A78), arm processing unit on AMD +Versal Gen 2 SOC, it can operate as following: + +* Four independent A78 clusters each having 2 A78 cores + +This processing unit is based on an ARM Cortex-A78 CPU, it also enables the following devices: + +* ARM GIC v3 Interrupt Controller +* Global Timer Counter +* SBSA UART + +Hardware +******** +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Devices +======= +System Timer +------------ + +This board configuration uses a system timer tick frequency of 100 MHz. + +Serial Port +----------- + +This board configuration uses a single serial communication channel with the +on-chip UART0. + +Memories +-------- + +Although Flash, DDR and OCM memory regions are defined in the DTS file, +all the code plus data of the application will be loaded in the sram0 region, +which points to the DDR memory. The ocm0 memory area is currently available +for usage, although nothing is placed there by default. + +Known Problems or Limitations +============================= + +The following platform features are unsupported: + +* Only the first cpu in the first cluster of the A78 subsystem is supported. + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Build and flash in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: versal2_apu + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! versal2_apu/amd_versal2_apu + + +References +********** + +1. ARMv8‑A Architecture Reference Manual (ARM DDI 0487) +2. Arm Cortex‑A78 Core Technical Reference Manual (Doc ID 101430) diff --git a/boards/amd/versal2_apu/pre_dt_board.cmake b/boards/amd/versal2_apu/pre_dt_board.cmake new file mode 100644 index 000000000000..59154956fdcb --- /dev/null +++ b/boards/amd/versal2_apu/pre_dt_board.cmake @@ -0,0 +1,9 @@ +# +# Copyright (c) 2025 Advanced Micro Devices, Inc. +# +# SPDX-License-Identifier: Apache-2.0 +# + +if(EXISTS "${BOARD_DIR}/${BOARD}.overlay") + list(APPEND EXTRA_DTC_OVERLAY_FILE "${BOARD_DIR}/${BOARD}.overlay") +endif() diff --git a/boards/amd/versal2_apu/support/xsdb.cfg b/boards/amd/versal2_apu/support/xsdb.cfg new file mode 100644 index 000000000000..8d8dc8d1d98c --- /dev/null +++ b/boards/amd/versal2_apu/support/xsdb.cfg @@ -0,0 +1,108 @@ +# Copyright (c) 2025 Advanced Micro Devices, Inc. +# +# SPDX-License-Identifier: Apache-2.0 + +proc cluster0_core0_rst { {mem "default"} } { + targets -set -filter {name =~ "Versal Gen 2*"} + + mwr -force 0xEC20001C 0x0 + # write bootloop + if {$mem eq "default"} { + mwr -force 0xbbf00000 0x14000000 + } + #cluster_0_config_0 + mwr -force 0xecc00020 0x0 + #cluster_0_pstate + mwr -force 0xecb18008 0x48 + #cluster_0_preq + mwr -force 0xecb18004 0x1 + after 400 + mwr -force 0xecb18004 0x0 + # enable lpd debug clock + set clock_mask [expr 0x1 << 25] + mask_write 0xEB5E017C [expr 0x1 << 25] [expr 0x1 << 25] + # clear lpd debug reset + mask_write 0xEB5E0398 0x1 0x0 + # clear fpd reset + mask_write 0xEB5E03D0 0x3 0x0 + # assert core reset apu0_rst + mask_write 0xEc200300 0x11 0x11 + # enable clock apu_cluster_0_clk + mask_write 0xEC20010c [expr 0x1 << 25] [expr 0x1 << 25] + # enable clock cluster 1 + mask_write 0xEC200110 [expr 0x1 << 25] [expr 0x1 << 25] + #enable clock cluster 2 + mask_write 0xEC200114 [expr 0x1 << 25] [expr 0x1 << 25] + #enable clock cluster 3 + mask_write 0xEC200118 [expr 0x1 << 25] [expr 0x1 << 25] + # clear fpd coresight reset + mwr -force 0xEC200310 0x0 + # clear cluster warm and cold resets of cluster 0 + mask_write 0xEC200300 [expr 0x1 << 8] 0 + mask_write 0xEC200300 [expr 0x1 << 9] 0 + # enable reset catch coresignt reg + mask_write 0xF0D40024 0x7 0x7 + set addr 0xbbf00000 + mwr -force 0xecc00040 0xbbf00000 + if {$mem eq "ddr"} { + set addr 0x0 + } + mwr -force 0xecc00040 $addr + + # de-assert core 0 reset + mask_write 0xec200300 0x11 0x0 + + #core0_pstate + mwr -force 0xecb10008 0x8 + #core0_preq + mwr -force 0xecb10004 0x1 + after 400 + mwr -force 0xecb10004 0x0 + + # disable reset catch + mask_write 0xF0D40024 0x7 0x0 + + targets -set -filter {name =~ "Cortex-A78AE*0.0"} + after 400 + stop + after 1000 + ta +} + +proc load_image args { + set elf_file [lindex $args 0] + set pdi_file [lindex $args 1] + set bl31_file [lindex $args 2] + set dtb_file [lindex $args 3] + + if { [info exists ::env(HW_SERVER_URL)] } { + connect -url $::env(HW_SERVER_URL) + } else { + connect + } + + device program $pdi_file + + if { [info exists ::env(HW_SERVER_URL)] } { + set hw_server_url [split $::env(HW_SERVER_URL) ":"] + set host [lindex $hw_server_url 0] + set port [lindex $hw_server_url 1] + disconnect + after 2000 + connect -host $host -port $port + after 3000 + ta + } + after 1000 + targets -set -nocase -filter {name =~ "Versal Gen 2*"} + after 100 + cluster0_core0_rst + after 100 + dow -data -force $dtb_file 0x1000000 + dow -force $elf_file + dow -force $bl31_file + con + exit +} + +load_image {*}$argv diff --git a/boards/amd/versal2_apu/versal2_apu.dts b/boards/amd/versal2_apu/versal2_apu.dts new file mode 100644 index 000000000000..c768c845d4b2 --- /dev/null +++ b/boards/amd/versal2_apu/versal2_apu.dts @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2025, Advanced Micro Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include + +/ { + compatible = "xlnx,versal2_apu"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + }; +}; + +&cpu0 { + clock-frequency = <100000000>; +}; + +&soc { + sram0: memory@0 { + compatible = "mmio-sram"; + reg = <0 0 0 DT_SIZE_M(2048)>; + }; +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; + clock-frequency = <100000000>; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + clock-frequency = <100000000>; +}; diff --git a/boards/amd/versal2_apu/versal2_apu.yaml b/boards/amd/versal2_apu/versal2_apu.yaml new file mode 100644 index 000000000000..5f71371c803f --- /dev/null +++ b/boards/amd/versal2_apu/versal2_apu.yaml @@ -0,0 +1,10 @@ +identifier: versal2_apu +name: AMD Development board for Versal Gen 2 APU +arch: arm +toolchain: + - zephyr +testing: + ignore_tags: + - net + - bluetooth +vendor: amd diff --git a/boards/amd/versal2_apu/versal2_apu_defconfig b/boards/amd/versal2_apu/versal2_apu_defconfig new file mode 100644 index 000000000000..8cbf569d6966 --- /dev/null +++ b/boards/amd/versal2_apu/versal2_apu_defconfig @@ -0,0 +1,19 @@ +# Xilinx Arm Trusted Firmware (ATF). +# Boot Flow is: Boot PDI -> TF-A -> Zephyr + +CONFIG_ARM64_VA_BITS_40=y +CONFIG_ARM64_PA_BITS_40=y +CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable serial port +CONFIG_UART_PL011=y + +# This should be commented in order to test at EL1 S (EL1 Secure) +CONFIG_ARMV8_A_NS=y diff --git a/boards/amd/versal2_rpu/versal2_rpu-qemu.dts b/boards/amd/versal2_rpu/versal2_rpu-qemu.dts index d2b4dac5de1f..26d57c783cc8 100644 --- a/boards/amd/versal2_rpu/versal2_rpu-qemu.dts +++ b/boards/amd/versal2_rpu/versal2_rpu-qemu.dts @@ -960,7 +960,7 @@ phandle = <0x10f>; }; - loader_write_cpu0_0x1@0xF1110880 { + loader_write_cpu0_0x1@0xf1110880 { compatible = "loader"; addr = <0xf1110880>; data = <0x01>; @@ -972,7 +972,7 @@ phandle = <0x110>; }; - loader_write_cpu0_0x5@0xFD1A0050 { + loader_write_cpu0_0x5@0xfd1a0050 { compatible = "loader"; addr = <0xfd1a0050>; data = <0x05>; @@ -984,7 +984,7 @@ phandle = <0x111>; }; - loader_write_cpu0_0xFF@0xF111010C { + loader_write_cpu0_0xFF@0xf111010c { compatible = "loader"; addr = <0xf111010c>; data = <0xff>; @@ -1031,7 +1031,7 @@ phandle = <0x44>; }; - loader_write_cpu0_0x80C@0xF12B0100 { + loader_write_cpu0_0x80C@0xf12b0100 { compatible = "loader"; addr = <0xf12b0100>; data = <0x80c>; @@ -1043,7 +1043,7 @@ phandle = <0x113>; }; - loader_write_cpu0_0x77@0xF1260320 { + loader_write_cpu0_0x77@0xf1260320 { compatible = "loader"; addr = <0xf1260320>; data = <0x77>; @@ -2488,7 +2488,7 @@ phandle = <0x165>; }; - loader_write_cpu0_0x1@0xEDC30440 { + loader_write_cpu0_0x1@0xedc30440 { compatible = "loader"; addr = <0xedc30440>; data = <0x01>; @@ -2500,7 +2500,7 @@ phandle = <0x166>; }; - loader_write_cpu0_0x7F@0xEDC30444 { + loader_write_cpu0_0x7F@0xedc30444 { compatible = "loader"; addr = <0xedc30444>; data = <0x7f>; @@ -2512,7 +2512,7 @@ phandle = <0x167>; }; - loader_write_cpu0_0x1@0xEDC3044c { + loader_write_cpu0_0x1@0xedc3044c { compatible = "loader"; addr = <0xedc3044c>; data = <0x01>; @@ -2524,7 +2524,7 @@ phandle = <0x168>; }; - loader_write_cpu0_0x1@0xEDC30450 { + loader_write_cpu0_0x1@0xedc30450 { compatible = "loader"; addr = <0xedc30450>; data = <0x01>; @@ -2536,7 +2536,7 @@ phandle = <0x169>; }; - loader_write_cpu0_0x1@0xEDC30460 { + loader_write_cpu0_0x1@0xedc30460 { compatible = "loader"; addr = <0xedc30460>; data = <0x01>; @@ -2548,7 +2548,7 @@ phandle = <0x16a>; }; - loader_write_cpu0_0x7f@0xEDC30464 { + loader_write_cpu0_0x7f@0xedc30464 { compatible = "loader"; addr = <0xedc30464>; data = <0x7f>; @@ -2560,7 +2560,7 @@ phandle = <0x16b>; }; - loader_write_cpu0_0x1@0xEDC3046c { + loader_write_cpu0_0x1@0xedc3046c { compatible = "loader"; addr = <0xedc3046c>; data = <0x01>; @@ -2572,7 +2572,7 @@ phandle = <0x16c>; }; - loader_write_cpu0_0x1@0xEDC30470 { + loader_write_cpu0_0x1@0xedc30470 { compatible = "loader"; addr = <0xedc30470>; data = <0x01>; @@ -2584,7 +2584,7 @@ phandle = <0x16d>; }; - loader_write_cpu0_0x3@0xED0A0098 { + loader_write_cpu0_0x3@0xed0a0098 { compatible = "loader"; addr = <0xed0a0098>; data = <0x03>; @@ -3289,7 +3289,7 @@ Cannot continue.\nTry installing libgcrypt."; phandle = <0x91>; }; - pmc_sha1@0xF1800000 { + pmc_sha1@0xf1800000 { doc-status = "complete"; compatible = "xlnx,asu_sha2"; reg = <0x00 0xf1800000 0x00 0x10000 0x00>; @@ -3941,7 +3941,7 @@ Cannot continue.\nTry installing libgcrypt."; xlnx,use-io-bus = <0x01>; phandle = <0x1a4>; - asu_io_intc@0C { + asu_io_intc@0c { #interrupt-cells = <0x01>; compatible = "xlnx,io-intc-1.02.a\0xlnx,io_intc"; interrupt-controller; @@ -4268,7 +4268,7 @@ Cannot continue.\nTry installing libgcrypt."; xlnx,use-io-bus = <0x01>; phandle = <0x1b5>; - pmc_ppu0_intc@0C { + pmc_ppu0_intc@0c { #interrupt-cells = <0x01>; compatible = "xlnx,io-intc-1.02.a\0xlnx,io_intc"; interrupt-controller; @@ -4484,7 +4484,7 @@ Cannot continue.\nTry installing libgcrypt."; xlnx,use-io-bus = <0x01>; phandle = <0x1bf>; - pmc_ppu1_intc@0C { + pmc_ppu1_intc@0c { #interrupt-cells = <0x01>; compatible = "xlnx,io-intc-1.02.a\0xlnx,io_intc"; interrupt-controller; @@ -4730,7 +4730,7 @@ Cannot continue.\nTry installing libgcrypt."; priority = <0xffffffff>; phandle = <0x1cd>; - ddrmc0_intc@0C { + ddrmc0_intc@0c { #interrupt-cells = <0x01>; compatible = "xlnx,io-intc-1.02.a\0xlnx,io_intc"; interrupt-controller; @@ -5062,7 +5062,7 @@ Cannot continue.\nTry installing libgcrypt."; phandle = <0x103>; }; - memory@0x50000000000ULL { + memory@0x50000000000ull { compatible = "qemu:memory-region"; device_type = "memory"; container = <0x0d>; @@ -5797,7 +5797,7 @@ Cannot continue.\nTry installing libgcrypt."; phandle = <0xa2>; }; - ddr_2@0x800000000ULL { + ddr_2@0x800000000ull { compatible = "qemu:memory-region-spec"; container = <0x103>; qemu,ram = <0x01>; diff --git a/boards/amd/versal2_rpu/versal2_rpu.dts b/boards/amd/versal2_rpu/versal2_rpu.dts index b2f311467c92..0d533b3afa08 100644 --- a/boards/amd/versal2_rpu/versal2_rpu.dts +++ b/boards/amd/versal2_rpu/versal2_rpu.dts @@ -25,6 +25,12 @@ compatible = "mmio-sram"; reg = <0x30000 0x7ffd0000>; }; + + /* RPU-local TCM address (system address: 0xEBA00000) */ + tcm: memory@0 { + compatible = "mmio-sram"; + reg = <0x0 DT_SIZE_K(64)>; + }; }; &ocm { diff --git a/boards/amd/versal2_rpu/versal2_rpu.yaml b/boards/amd/versal2_rpu/versal2_rpu.yaml index 91753bea822c..c45fe1827908 100644 --- a/boards/amd/versal2_rpu/versal2_rpu.yaml +++ b/boards/amd/versal2_rpu/versal2_rpu.yaml @@ -6,6 +6,7 @@ toolchain: supported: - scsi - ufs + - mbox testing: ignore_tags: - net diff --git a/boards/amd/versal_apu/Kconfig.defconfig b/boards/amd/versal_apu/Kconfig.defconfig new file mode 100644 index 000000000000..a58f7eda01a1 --- /dev/null +++ b/boards/amd/versal_apu/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2025, Advanced Micro Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_VERSAL_APU + +config BUILD_OUTPUT_BIN + default y + +endif # BOARD_VERSAL_APU diff --git a/boards/amd/versal_apu/Kconfig.versal_apu b/boards/amd/versal_apu/Kconfig.versal_apu new file mode 100644 index 000000000000..c29ece143333 --- /dev/null +++ b/boards/amd/versal_apu/Kconfig.versal_apu @@ -0,0 +1,5 @@ +# Copyright (c) 2025, Advanced Micro Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_VERSAL_APU + select SOC_VERSAL_APU diff --git a/boards/amd/versal_apu/board.cmake b/boards/amd/versal_apu/board.cmake new file mode 100644 index 000000000000..4de1e4134dc0 --- /dev/null +++ b/boards/amd/versal_apu/board.cmake @@ -0,0 +1,18 @@ +# Copyright (c) 2025, Advanced Micro Devices, Inc. +# +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_BUILD_WITH_TFA) + set(TFA_PLAT "versal") + # Add Versal specific TF-A build parameters + set(TFA_EXTRA_ARGS "TFA_NO_PM=1;PRELOADED_BL33_BASE=${CONFIG_SRAM_BASE_ADDRESS}") + if(CONFIG_TFA_MAKE_BUILD_TYPE_DEBUG) + set(BUILD_FOLDER "debug") + else() + set(BUILD_FOLDER "release") + endif() + set(XSDB_BL31_PATH ${PROJECT_BINARY_DIR}/../tfa/versal/${BUILD_FOLDER}/bl31/bl31.elf) + board_runner_args(xsdb "--bl31=${XSDB_BL31_PATH}") +endif() + +include(${ZEPHYR_BASE}/boards/common/xsdb.board.cmake) diff --git a/boards/amd/versal_apu/board.yml b/boards/amd/versal_apu/board.yml new file mode 100644 index 000000000000..9942b61f5d42 --- /dev/null +++ b/boards/amd/versal_apu/board.yml @@ -0,0 +1,9 @@ +# Copyright (c) 2025, Advanced Micro Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board: + name: versal_apu + full_name: AMD Versal APU Development Board + vendor: amd + socs: + - name: versal_apu diff --git a/boards/amd/versal_apu/doc/index.rst b/boards/amd/versal_apu/doc/index.rst new file mode 100644 index 000000000000..a78dd0576ba6 --- /dev/null +++ b/boards/amd/versal_apu/doc/index.rst @@ -0,0 +1,83 @@ +.. zephyr:board:: versal_apu + +Overview +******** +This configuration provides support for the APU (Application Processing Unit) on AMD +Versal devices. The APU can operate as follows: + +* Two independent Cortex-A72 cores + +This processing unit is based on an ARM Cortex-A72 CPU, and it enables the following devices: + +* ARM GIC v3 Interrupt Controller +* ARMv8 Generic Timer +* SBSA UART + +Hardware +******** +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Devices +======= +System Timer +------------ + +This board configuration uses a system timer tick frequency of 100 MHz. + +Serial Port +----------- + +This board configuration uses a single serial communication channel with the +on-chip UART0. + +Memories +-------- + +Although Flash, DDR and OCM memory regions are defined in the DTS file, +all the code plus data of the application will be loaded in the sram0 region, +which points to the DDR memory. The OCM memory area is currently available +for usage, although nothing is placed there by default. + +Known Problems or Limitations +============================= + +The following platform features are unsupported: + +* Only the first CPU in the APU subsystem is supported. + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +For deployment on real Versal hardware, XSDB and a PDI file are required. The PDI file contains the hardware initialization and boot configuration needed for the physical device. + +Build the application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: versal_apu + :goals: build + +Flash to real hardware with PDI file: + +.. code-block:: console + + west flash --runner xsdb --pdi /path/to/your.pdi --bl31 /path/to/your_bl31.elf + +You should see the following message on the console: + +.. code-block:: console + + Hello World! versal_apu/versal_apu + + +References +********** + +1. ARMv8-A Architecture Reference Manual (ARM DDI 0487) +2. Arm Cortex-A72 Core Technical Reference Manual (Doc ID 100095) +3. AMD Versal Technical Reference Manual diff --git a/boards/amd/versal_apu/support/xsdb.cfg b/boards/amd/versal_apu/support/xsdb.cfg new file mode 100644 index 000000000000..3a5439b8dbe1 --- /dev/null +++ b/boards/amd/versal_apu/support/xsdb.cfg @@ -0,0 +1,28 @@ +# Copyright (c) 2025 Advanced Micro Devices, Inc. +# +# SPDX-License-Identifier: Apache-2.0 + +proc load_image args { + set elf_file [lindex $args 0] + set pdi_file [lindex $args 1] + set bl31_file [lindex $args 2] + + if { [info exists ::env(HW_SERVER_URL)] } { + connect -url $::env(HW_SERVER_URL) + } else { + connect + } + + device program $pdi_file + targets -set -nocase -filter {name =~ "Versal*"} + after 100 + targets -set -nocase -filter {name =~ "*Cortex-A72 #0"} + rst -proc + after 100 + dow -force $elf_file + dow -force $bl31_file + con + exit +} + +load_image {*}$argv diff --git a/boards/amd/versal_apu/versal_apu.dts b/boards/amd/versal_apu/versal_apu.dts new file mode 100644 index 000000000000..567549995534 --- /dev/null +++ b/boards/amd/versal_apu/versal_apu.dts @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2025, Advanced Micro Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include + +/ { + compatible = "xlnx,versal_apu"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; +}; + +&cpu0 { + clock-frequency = <100000000>; +}; + +&soc { + sram0: memory@0 { + compatible = "mmio-sram"; + reg = <0x0 0x0 0x0 DT_SIZE_G(2)>; + }; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + clock-frequency = <100000000>; +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; + clock-frequency = <100000000>; +}; diff --git a/boards/amd/versal_apu/versal_apu.yaml b/boards/amd/versal_apu/versal_apu.yaml new file mode 100644 index 000000000000..983e1d1da471 --- /dev/null +++ b/boards/amd/versal_apu/versal_apu.yaml @@ -0,0 +1,10 @@ +identifier: versal_apu +name: AMD Development board for Versal APU +arch: arm64 +toolchain: + - zephyr +testing: + ignore_tags: + - net + - bluetooth +vendor: amd diff --git a/boards/amd/versal_apu/versal_apu_defconfig b/boards/amd/versal_apu/versal_apu_defconfig new file mode 100644 index 000000000000..acd175bcd80b --- /dev/null +++ b/boards/amd/versal_apu/versal_apu_defconfig @@ -0,0 +1,22 @@ +# The Zephyr build from this defconfig is expected to boot from +# Xilinx Arm Trusted Firmware (ATF). +# Boot Flow is: Boot PDI -> TF-A -> Zephyr + +CONFIG_BUILD_WITH_TFA=y + +CONFIG_ARM64_VA_BITS_40=y +CONFIG_ARM64_PA_BITS_40=y +CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable serial port +CONFIG_UART_PL011=y + +# This should be commented in order to test at EL1 S (EL1 Secure) +CONFIG_ARMV8_A_NS=y diff --git a/boards/amd/versalnet_apu/board.cmake b/boards/amd/versalnet_apu/board.cmake index 4f3d138a3c41..f3efc0ce2686 100644 --- a/boards/amd/versalnet_apu/board.cmake +++ b/boards/amd/versalnet_apu/board.cmake @@ -18,11 +18,19 @@ set(QEMU_FLAGS_${ARCH} -m 2g ) +# Add SMP support if configured maxcpus parameter value is aligned with QEMU DT +if(CONFIG_SMP AND CONFIG_MP_MAX_NUM_CPUS GREATER 1) + list(APPEND QEMU_SMP_FLAGS -smp maxcpus=20) +endif() + # Set TF-A platform for ARM Trusted Firmware builds if(CONFIG_BUILD_WITH_TFA) set(TFA_PLAT "versal_net") - # Add Versal NET specific TF-A build parameters - set(TFA_EXTRA_ARGS "TFA_NO_PM=1;PRELOADED_BL33_BASE=0x0") + # Configure TF-A memory location for Versal NET platform + # TF-A runs from DDR at address 0xf000000 (changed from default 0xbbf00000). + # This DDR location (VERSAL_NET_ATF_MEM_BASE=0xf000000) works for all possible designs. + # Note: If TF-A needs to run from OCM instead of DDR, PDI changes would be required. + set(TFA_EXTRA_ARGS "RESET_TO_BL31=1;PRELOADED_BL33_BASE=0x0;TFA_NO_PM=1;VERSAL_NET_ATF_MEM_BASE=0xf000000;VERSAL_NET_ATF_MEM_SIZE=0x50000") if(CONFIG_TFA_MAKE_BUILD_TYPE_DEBUG) set(BUILD_FOLDER "debug") else() diff --git a/boards/amd/versalnet_apu/board.yml b/boards/amd/versalnet_apu/board.yml index 0c7b0dda2908..4e9d44c86123 100644 --- a/boards/amd/versalnet_apu/board.yml +++ b/boards/amd/versalnet_apu/board.yml @@ -4,3 +4,5 @@ board: vendor: amd socs: - name: amd_versalnet_apu + variants: + - name: smp diff --git a/boards/amd/versalnet_apu/versalnet_apu-qemu.dts b/boards/amd/versalnet_apu/versalnet_apu-qemu.dts index f011af0cdd63..881f0d9fe5c1 100644 --- a/boards/amd/versalnet_apu/versalnet_apu-qemu.dts +++ b/boards/amd/versalnet_apu/versalnet_apu-qemu.dts @@ -694,7 +694,7 @@ phandle = <0xc9>; }; - loader_write_cpu0_0x1@0xF1110880 { + loader_write_cpu0_0x1@0xf1110880 { compatible = "loader"; addr = <0xf1110880>; data = <0x01>; @@ -706,7 +706,7 @@ phandle = <0xca>; }; - loader_write_cpu0_0x5@0xFD1A0050 { + loader_write_cpu0_0x5@0xfd1a0050 { compatible = "loader"; addr = <0xfd1a0050>; data = <0x05>; @@ -718,7 +718,7 @@ phandle = <0xcb>; }; - loader_write_cpu0_0xFF@0xF111010C { + loader_write_cpu0_0xFF@0xf111010c { compatible = "loader"; addr = <0xf111010c>; data = <0xff>; @@ -744,7 +744,7 @@ phandle = <0x2c>; }; - loader_write_cpu0_0x80C@0xF12B0100 { + loader_write_cpu0_0x80C@0xf12b0100 { compatible = "loader"; addr = <0xf12b0100>; data = <0x80c>; @@ -1394,7 +1394,7 @@ phandle = <0xb7>; }; - rpu_pcil@0xEB420000 { + rpu_pcil@0xeb420000 { compatible = "xlnx,rpu_pcil"; reg = <0x00 0xeb420000 0x00 0x10000 0x00>; gpio-controller; @@ -1564,7 +1564,7 @@ phandle = <0x4e>; }; - pki_rng@0x20400040000ULL { + pki_rng@0x20400040000ull { compatible = "xlnx,psx-pki-rng"; reg = <0x204 0x40000 0x00 0x20000 0x00>; interrupts = <0x9c>; @@ -2143,7 +2143,7 @@ Cannot continue.Try installing libgcrypt."; phandle = <0x6e>; }; - pmc_sha1@0xF1800000 { + pmc_sha1@0xf1800000 { doc-status = "complete"; compatible = "zynqmp,csu-sha3"; reg = <0x00 0xf1800000 0x00 0x10000 0x00>; @@ -2224,7 +2224,7 @@ Cannot continue.Try installing libgcrypt."; phandle = <0x76>; }; - pmc_err_mng@0xF1130000 { + pmc_err_mng@0xf1130000 { compatible = "xlnx,PmcErrMngmnt"; reg = <0x00 0xf1130000 0x00 0x10000 0x00>; interrupts = <0xbca>; @@ -2975,7 +2975,7 @@ Cannot continue.Try installing libgcrypt."; xlnx,use-io-bus = <0x01>; phandle = <0x139>; - pmc_ppu0_intc@0C { + pmc_ppu0_intc@0c { #interrupt-cells = <0x01>; compatible = "xlnx,io-intc-1.02.a\0xlnx,io_intc"; interrupt-controller; @@ -3191,7 +3191,7 @@ Cannot continue.Try installing libgcrypt."; xlnx,use-io-bus = <0x01>; phandle = <0x143>; - pmc_ppu1_intc@0C { + pmc_ppu1_intc@0c { #interrupt-cells = <0x01>; compatible = "xlnx,io-intc-1.02.a\0xlnx,io_intc"; interrupt-controller; @@ -3407,7 +3407,7 @@ Cannot continue.Try installing libgcrypt."; container = <0x92>; phandle = <0x14d>; - psm0_intc@0C { + psm0_intc@0c { #interrupt-cells = <0x01>; compatible = "xlnx,io-intc-1.02.a\0xlnx,io_intc"; interrupt-controller; @@ -3554,7 +3554,7 @@ Cannot continue.Try installing libgcrypt."; priority = <0xffffffff>; phandle = <0x153>; - ddrmc0_intc@0C { + ddrmc0_intc@0c { #interrupt-cells = <0x01>; compatible = "xlnx,io-intc-1.02.a\0xlnx,io_intc"; interrupt-controller; @@ -3865,7 +3865,7 @@ Cannot continue.Try installing libgcrypt."; phandle = <0xba>; }; - memory@0x50000000000ULL { + memory@0x50000000000ull { compatible = "qemu:memory-region"; device_type = "memory"; container = <0x0b>; @@ -4668,7 +4668,7 @@ Cannot continue.Try installing libgcrypt."; phandle = <0x7f>; }; - ddr_2@0x800000000ULL { + ddr_2@0x800000000ull { compatible = "qemu:memory-region-spec"; container = <0xba>; qemu,ram = <0x01>; diff --git a/boards/amd/versalnet_apu/versalnet_apu_amd_versalnet_apu_smp.dts b/boards/amd/versalnet_apu/versalnet_apu_amd_versalnet_apu_smp.dts new file mode 100644 index 000000000000..946a3df60c35 --- /dev/null +++ b/boards/amd/versalnet_apu/versalnet_apu_amd_versalnet_apu_smp.dts @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025, Advanced Micro Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include "versalnet_apu.dts" diff --git a/boards/amd/versalnet_apu/versalnet_apu_amd_versalnet_apu_smp.yaml b/boards/amd/versalnet_apu/versalnet_apu_amd_versalnet_apu_smp.yaml new file mode 100644 index 000000000000..9d2672eba624 --- /dev/null +++ b/boards/amd/versalnet_apu/versalnet_apu_amd_versalnet_apu_smp.yaml @@ -0,0 +1,11 @@ +identifier: versalnet_apu/amd_versalnet_apu/smp +name: AMD Development board for Versal NET APU +arch: arm +toolchain: + - zephyr +testing: + ignore_tags: + - net + - bluetooth + - fpu +vendor: amd diff --git a/boards/amd/versalnet_apu/versalnet_apu_amd_versalnet_apu_smp_defconfig b/boards/amd/versalnet_apu/versalnet_apu_amd_versalnet_apu_smp_defconfig new file mode 100644 index 000000000000..1a1880ebdcb8 --- /dev/null +++ b/boards/amd/versalnet_apu/versalnet_apu_amd_versalnet_apu_smp_defconfig @@ -0,0 +1,35 @@ +# The Zephyr build from this defconfig is expected to boot from +# Xilinx Arm Trusted Firmware (ATF). +# Boot Flow is: Boot PDI -> TF-A -> Zephyr +CONFIG_BUILD_WITH_TFA=y + +CONFIG_ARM64_VA_BITS_40=y +CONFIG_ARM64_PA_BITS_40=y +CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable serial port +CONFIG_UART_PL011=y + +# This should be commented in order to test at EL1 S (EL1 Secure) +CONFIG_ARMV8_A_NS=y + +# Enable Clock Manager +CONFIG_CLOCK_CONTROL=y + +# Reset Manager +CONFIG_RESET=y + +# PSCI support Enable +CONFIG_PM_CPU_OPS=y +CONFIG_PM_CPU_OPS_PSCI=y + +# Enable SMP support +CONFIG_SMP=y +CONFIG_MP_MAX_NUM_CPUS=4 diff --git a/boards/amd/versalnet_rpu/doc/index.rst b/boards/amd/versalnet_rpu/doc/index.rst index 35d3ea5f22df..1e793e6d9c5b 100644 --- a/boards/amd/versalnet_rpu/doc/index.rst +++ b/boards/amd/versalnet_rpu/doc/index.rst @@ -54,12 +54,48 @@ Programming and Debugging .. zephyr:board-supported-runners:: -Build and flash in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. +This board supports two deployment targets: + +QEMU Emulation +============== + +For QEMU target, XSDB (Xilinx System Debugger) is not used and therefore PDI +(Programmable Device Image) is not required. QEMU provides direct emulation +without needing hardware initialization files. + +Build and run with QEMU: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: versalnet_rpu + :goals: build run + +Alternatively, you can build and run separately: + +.. code-block:: console + + west build -b versalnet_rpu samples/hello_world + west build -t run + +Real Hardware +============= + +For deployment on real Versal Net hardware, XSDB and a PDI file are required. +The PDI file contains the hardware initialization and boot configuration needed +for the physical device. + +Build the application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world :board: versalnet_rpu - :goals: build flash + :goals: build + +Flash to real hardware with PDI file: + +.. code-block:: console + + west flash --runner xsdb --pdi /path/to/your.pdi You should see the following message on the console: diff --git a/boards/amd/versalnet_rpu/support/xsdb.cfg b/boards/amd/versalnet_rpu/support/xsdb.cfg index 809e974f83e5..6b7128ad783c 100644 --- a/boards/amd/versalnet_rpu/support/xsdb.cfg +++ b/boards/amd/versalnet_rpu/support/xsdb.cfg @@ -25,8 +25,8 @@ proc load_image args { after 100 # Configure timestamp generator to run global timer gracefully # Ideally these registers should be set from bootloader (cdo) - mwr -force 0xeb5b0000 0x1 mwr -force 0xeb5b0020 100000000 + mwr -force 0xeb5b0000 0x1 after 100 targets -set -nocase -filter {name =~ "*Cortex-R52 #0.0"} diff --git a/boards/amd/versalnet_rpu/versalnet_rpu.dts b/boards/amd/versalnet_rpu/versalnet_rpu.dts index bb4f708d1281..f599989aa93a 100644 --- a/boards/amd/versalnet_rpu/versalnet_rpu.dts +++ b/boards/amd/versalnet_rpu/versalnet_rpu.dts @@ -27,9 +27,14 @@ }; &soc { - sram0: memory@0 { + sram0: memory@30000 { compatible = "mmio-sram"; - reg = <0x00000 DT_SIZE_M(2048)>; + reg = <0x30000 DT_SIZE_M(2047)>; + }; + + tcm: memory@0 { + compatible = "mmio-sram"; + reg = <0x0 DT_SIZE_K(64)>; }; }; diff --git a/boards/amd/versalnet_rpu/versalnet_rpu.yaml b/boards/amd/versalnet_rpu/versalnet_rpu.yaml index 21f19ea6cced..222c68f5308f 100644 --- a/boards/amd/versalnet_rpu/versalnet_rpu.yaml +++ b/boards/amd/versalnet_rpu/versalnet_rpu.yaml @@ -10,3 +10,4 @@ testing: vendor: amd supported: - sdhc + - mbox diff --git a/boards/andestech/adp_xc7k_ae350/Kconfig.adp_xc7k b/boards/andestech/adp_xc7k_ae350/Kconfig.adp_xc7k index 8cf2c3fb842e..24493297fc02 100644 --- a/boards/andestech/adp_xc7k_ae350/Kconfig.adp_xc7k +++ b/boards/andestech/adp_xc7k_ae350/Kconfig.adp_xc7k @@ -2,5 +2,4 @@ # SPDX-License-Identifier: Apache-2.0 config BOARD_ADP_XC7K - select SOC_ANDES_AE350 if BOARD_ADP_XC7K_AE350 - select SOC_ANDES_AE350_CLIC if BOARD_ADP_XC7K_AE350_CLIC + select SOC_AE350 if BOARD_ADP_XC7K_AE350 || BOARD_ADP_XC7K_AE350_CLIC diff --git a/boards/andestech/adp_xc7k_ae350/Kconfig.defconfig b/boards/andestech/adp_xc7k_ae350/Kconfig.defconfig new file mode 100644 index 000000000000..2c8d0e6c66c7 --- /dev/null +++ b/boards/andestech/adp_xc7k_ae350/Kconfig.defconfig @@ -0,0 +1,9 @@ +# +# Copyright (c) 2026 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 +# + +choice SOC_AE350_INTERRUPT_TYPE + default SOC_AE350_INTERRUPT_TYPE_CLIC if BOARD_ADP_XC7K_AE350_CLIC + +endchoice diff --git a/boards/antmicro/myra_sip_baseboard/doc/index.rst b/boards/antmicro/myra_sip_baseboard/doc/index.rst index 0eb273c52455..9f1c47d702d3 100644 --- a/boards/antmicro/myra_sip_baseboard/doc/index.rst +++ b/boards/antmicro/myra_sip_baseboard/doc/index.rst @@ -102,14 +102,14 @@ Other board's peripherals: - Relative humidity accuracy: ±1.0% RH - Operating humidity range: 0-100% RH - - Temperature accuracy: ±0.1°C - - Operating temperature range: -40°C to 125°C + - Temperature accuracy: ±0.1 °C + - Operating temperature range: -40 °C to 125 °C - BME280 sensor: - Relative humidity accuracy: ±3% RH - - Temperature accuracy: ±1°C + - Temperature accuracy: ±1 C - Pressure accuracy: ±1 hPa - - Operating temperature range: -40°C to 85°C + - Operating temperature range: -40 °C to 85 °C - Pressure range: 300-1100 hPa - QWIIC connectors: For easy peripheral expansion. diff --git a/boards/arduino/giga_r1/arduino_giga_r1.dtsi b/boards/arduino/giga_r1/arduino_giga_r1.dtsi index 76aa69661524..166017db8e89 100644 --- a/boards/arduino/giga_r1/arduino_giga_r1.dtsi +++ b/boards/arduino/giga_r1/arduino_giga_r1.dtsi @@ -64,6 +64,7 @@ sdhc: &sdmmc1 { &sdmmc1_ck_pc12 &sdmmc1_cmd_pd2>; pinctrl-names = "default"; sdhi-on-gpios = <&gpiob 10 GPIO_ACTIVE_HIGH>; + power-delay-ms = <50>; min-bus-freq = ; max-bus-freq = ; hw-flow-control; diff --git a/boards/arduino/giga_r1/support/openocd_arduino_giga_r1_m4.cfg b/boards/arduino/giga_r1/support/openocd_arduino_giga_r1_m4.cfg index 174696ee8214..ff820c112d25 100644 --- a/boards/arduino/giga_r1/support/openocd_arduino_giga_r1_m4.cfg +++ b/boards/arduino/giga_r1/support/openocd_arduino_giga_r1_m4.cfg @@ -1,7 +1,7 @@ source [find interface/stlink-dap.cfg] transport select dapdirect_swd # If your ST-Link adapter embedded firmware dates prior version v2j24 -# DAP transport/intereface is not supported. In this case, refer to +# DAP transport/interface is not supported. In this case, refer to # https://docs.zephyrproject.org/latest/develop/flash_debug/probes.html#OpenOCD-deprecates-hla-st-link-interface set DUAL_BANK 1 diff --git a/boards/arduino/giga_r1/support/openocd_arduino_giga_r1_m7.cfg b/boards/arduino/giga_r1/support/openocd_arduino_giga_r1_m7.cfg index 5c1d0af36d1a..75e20243d417 100644 --- a/boards/arduino/giga_r1/support/openocd_arduino_giga_r1_m7.cfg +++ b/boards/arduino/giga_r1/support/openocd_arduino_giga_r1_m7.cfg @@ -1,7 +1,7 @@ source [find interface/stlink-dap.cfg] transport select dapdirect_swd # If your ST-Link adapter embedded firmware dates prior version v2j24 -# DAP transport/intereface is not supported. In this case, refer to +# DAP transport/interface is not supported. In this case, refer to # https://docs.zephyrproject.org/latest/develop/flash_debug/probes.html#OpenOCD-deprecates-hla-st-link-interface source [find target/stm32h7x.cfg] diff --git a/boards/arduino/mkrzero/arduino_mkrzero.dts b/boards/arduino/mkrzero/arduino_mkrzero.dts index 3fbf38268d79..aa98de5d00c5 100644 --- a/boards/arduino/mkrzero/arduino_mkrzero.dts +++ b/boards/arduino/mkrzero/arduino_mkrzero.dts @@ -135,7 +135,7 @@ zephyr_i2c: &sercom0 { code_partition: partition@2000 { label = "code"; - reg = <0x2000 0x3A000>; + reg = <0x2000 0x3a000>; read-only; }; diff --git a/boards/arduino/nano_33_iot/arduino_nano_33_iot.dts b/boards/arduino/nano_33_iot/arduino_nano_33_iot.dts index fed0ec2dd2b8..cdd79bddff46 100644 --- a/boards/arduino/nano_33_iot/arduino_nano_33_iot.dts +++ b/boards/arduino/nano_33_iot/arduino_nano_33_iot.dts @@ -163,7 +163,7 @@ code_partition: partition@2000 { label = "code"; - reg = <0x2000 0x3A000>; + reg = <0x2000 0x3a000>; read-only; }; diff --git a/boards/arduino/nano_matter/arduino_nano_matter.dts b/boards/arduino/nano_matter/arduino_nano_matter.dts index 9e20e508805d..dd108d99189a 100644 --- a/boards/arduino/nano_matter/arduino_nano_matter.dts +++ b/boards/arduino/nano_matter/arduino_nano_matter.dts @@ -327,13 +327,13 @@ /* Reserve 736 kB for the application in slot 0 */ slot0_partition: partition@c000 { - reg = <0x0000c000 0x000B8000>; + reg = <0x0000c000 0x000b8000>; label = "image-0"; }; /* Reserve 736 kB for the application in slot 1 */ - slot1_partition: partition@C4000 { - reg = <0x000C4000 0x000B8000>; + slot1_partition: partition@c4000 { + reg = <0x000c4000 0x000b8000>; label = "image-1"; }; diff --git a/boards/arduino/nicla_vision/arduino_nicla_vision.dtsi b/boards/arduino/nicla_vision/arduino_nicla_vision.dtsi index 7913bd683349..6a21a8ccf9cb 100644 --- a/boards/arduino/nicla_vision/arduino_nicla_vision.dtsi +++ b/boards/arduino/nicla_vision/arduino_nicla_vision.dtsi @@ -52,6 +52,7 @@ sdhc: &sdmmc2 { &sdmmc2_ck_pd6 &sdmmc2_cmd_pd7>; pinctrl-names = "default"; sdhi-on-gpios = <&gpiog 4 GPIO_ACTIVE_HIGH>; + power-delay-ms = <50>; min-bus-freq = ; max-bus-freq = ; hw-flow-control; diff --git a/boards/arduino/nicla_vision/support/openocd_arduino_nicla_vision_m4.cfg b/boards/arduino/nicla_vision/support/openocd_arduino_nicla_vision_m4.cfg index 174696ee8214..ff820c112d25 100644 --- a/boards/arduino/nicla_vision/support/openocd_arduino_nicla_vision_m4.cfg +++ b/boards/arduino/nicla_vision/support/openocd_arduino_nicla_vision_m4.cfg @@ -1,7 +1,7 @@ source [find interface/stlink-dap.cfg] transport select dapdirect_swd # If your ST-Link adapter embedded firmware dates prior version v2j24 -# DAP transport/intereface is not supported. In this case, refer to +# DAP transport/interface is not supported. In this case, refer to # https://docs.zephyrproject.org/latest/develop/flash_debug/probes.html#OpenOCD-deprecates-hla-st-link-interface set DUAL_BANK 1 diff --git a/boards/arduino/nicla_vision/support/openocd_arduino_nicla_vision_m7.cfg b/boards/arduino/nicla_vision/support/openocd_arduino_nicla_vision_m7.cfg index 5c1d0af36d1a..75e20243d417 100644 --- a/boards/arduino/nicla_vision/support/openocd_arduino_nicla_vision_m7.cfg +++ b/boards/arduino/nicla_vision/support/openocd_arduino_nicla_vision_m7.cfg @@ -1,7 +1,7 @@ source [find interface/stlink-dap.cfg] transport select dapdirect_swd # If your ST-Link adapter embedded firmware dates prior version v2j24 -# DAP transport/intereface is not supported. In this case, refer to +# DAP transport/interface is not supported. In this case, refer to # https://docs.zephyrproject.org/latest/develop/flash_debug/probes.html#OpenOCD-deprecates-hla-st-link-interface source [find target/stm32h7x.cfg] diff --git a/boards/arduino/opta/support/openocd_opta_stm32h747xx_m7.cfg b/boards/arduino/opta/support/openocd_opta_stm32h747xx_m7.cfg index 5c1d0af36d1a..75e20243d417 100644 --- a/boards/arduino/opta/support/openocd_opta_stm32h747xx_m7.cfg +++ b/boards/arduino/opta/support/openocd_opta_stm32h747xx_m7.cfg @@ -1,7 +1,7 @@ source [find interface/stlink-dap.cfg] transport select dapdirect_swd # If your ST-Link adapter embedded firmware dates prior version v2j24 -# DAP transport/intereface is not supported. In this case, refer to +# DAP transport/interface is not supported. In this case, refer to # https://docs.zephyrproject.org/latest/develop/flash_debug/probes.html#OpenOCD-deprecates-hla-st-link-interface source [find target/stm32h7x.cfg] diff --git a/boards/arduino/portenta_c33/arduino_portenta_c33.dts b/boards/arduino/portenta_c33/arduino_portenta_c33.dts index 3dda993399e8..dbf6e0b53eb1 100644 --- a/boards/arduino/portenta_c33/arduino_portenta_c33.dts +++ b/boards/arduino/portenta_c33/arduino_portenta_c33.dts @@ -308,7 +308,7 @@ storage_partition: partition@0 { label = "storage"; - reg = <0X0 DT_SIZE_K(8)>; + reg = <0x0 DT_SIZE_K(8)>; }; }; }; @@ -318,7 +318,7 @@ }; ð { - local-mac-address = [74 90 50 B0 5D E9]; + local-mac-address = [74 90 50 b0 5d e9]; status = "okay"; phy-handle = <&phy>; }; diff --git a/boards/arduino/portenta_h7/arduino_portenta_h7-common.dtsi b/boards/arduino/portenta_h7/arduino_portenta_h7-common.dtsi index 5d29727db85d..50d1e1dd79a8 100644 --- a/boards/arduino/portenta_h7/arduino_portenta_h7-common.dtsi +++ b/boards/arduino/portenta_h7/arduino_portenta_h7-common.dtsi @@ -242,6 +242,7 @@ sdhc: &sdmmc1 { &sdmmc1_ck_pc12 &sdmmc1_cmd_pd2>; pinctrl-names = "default"; sdhi-on-gpios = <&gpioj 1 GPIO_ACTIVE_HIGH>; + power-delay-ms = <50>; interrupts = <49 0>; interrupt-names = "event"; min-bus-freq = ; diff --git a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7.dts b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7.dts index afc4ca90fc9c..7a6bd8f91a81 100644 --- a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7.dts +++ b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7.dts @@ -203,9 +203,9 @@ zephyr_udc0: &usbotg_hs { reg = <0x00040000 0x00060000>; }; - slot1_partition: partition@A0000 { + slot1_partition: partition@a0000 { label = "image-1"; - reg = <0x000A0000 0x00060000>; + reg = <0x000a0000 0x00060000>; }; }; }; diff --git a/boards/arduino/portenta_h7/doc/index.rst b/boards/arduino/portenta_h7/doc/index.rst index b0eca10b6ec4..c4604b28f91f 100644 --- a/boards/arduino/portenta_h7/doc/index.rst +++ b/boards/arduino/portenta_h7/doc/index.rst @@ -36,8 +36,6 @@ information on how to build for specific revisions of the board). Applications that intend to use BLE must specify hardware revision at build time. -Currently only BLE is supported on this board, WiFi is not supported. - Fetch Binary Blobs ****************** diff --git a/boards/arduino/uno_r4/arduino_uno_r4.dts b/boards/arduino/uno_r4/arduino_uno_r4.dts index 7119ad6d049c..e369914bc4da 100644 --- a/boards/arduino/uno_r4/arduino_uno_r4.dts +++ b/boards/arduino/uno_r4/arduino_uno_r4.dts @@ -103,7 +103,7 @@ code_partition: partition@4000 { label = "code"; - reg = <0x4000 0x3C000>; + reg = <0x4000 0x3c000>; read-only; }; }; diff --git a/boards/arduino/uno_r4/arduino_uno_r4_minima.overlay b/boards/arduino/uno_r4/arduino_uno_r4_minima.overlay index 1180d99989c8..1d6bc5dd8e5e 100644 --- a/boards/arduino/uno_r4/arduino_uno_r4_minima.overlay +++ b/boards/arduino/uno_r4/arduino_uno_r4_minima.overlay @@ -105,3 +105,5 @@ arduino_i2c: &iic1 {}; arduino_spi: &spi1 {}; + +arduino_serial: &uart2 {}; diff --git a/boards/arduino/uno_r4/arduino_uno_r4_wifi.overlay b/boards/arduino/uno_r4/arduino_uno_r4_wifi.overlay index 01dfd4686b33..4b3163358fe7 100644 --- a/boards/arduino/uno_r4/arduino_uno_r4_wifi.overlay +++ b/boards/arduino/uno_r4/arduino_uno_r4_wifi.overlay @@ -124,3 +124,5 @@ zephyr_i2c: &iic0 {}; arduino_i2c: &iic1 {}; arduino_spi: &spi0 {}; + +arduino_serial: &uart2 {}; diff --git a/boards/arm/fvp_base_revc_2xaem/doc/index.rst b/boards/arm/fvp_base_revc_2xaem/doc/index.rst index b7fc607cfc1c..ff54bdcde546 100644 --- a/boards/arm/fvp_base_revc_2xaem/doc/index.rst +++ b/boards/arm/fvp_base_revc_2xaem/doc/index.rst @@ -22,21 +22,7 @@ Hardware Supported Features ================== -The following hardware features are supported: - -+-----------------------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+=======================+============+======================+ -| GICv3 | on-chip | interrupt controller | -+-----------------------+------------+----------------------+ -| PL011 UART | on-chip | serial port | -+-----------------------+------------+----------------------+ -| ARM GENERIC TIMER | on-chip | system clock | -+-----------------------+------------+----------------------+ -| SMSC_91C111 | on-chip | ethernet device | -+-----------------------+------------+----------------------+ - -The kernel currently does not support other hardware features on this platform. +.. zephyr:board-supported-hw:: Board Variants ============== diff --git a/boards/arm/mps2/Kconfig.mps2 b/boards/arm/mps2/Kconfig.mps2 index c350ffeb8cb2..811aa31a24c4 100644 --- a/boards/arm/mps2/Kconfig.mps2 +++ b/boards/arm/mps2/Kconfig.mps2 @@ -3,10 +3,10 @@ # SPDX-License-Identifier: Apache-2.0 config BOARD_MPS2 - select SOC_MPS2_AN383 if BOARD_MPS2_AN383 - select SOC_MPS2_AN385 if BOARD_MPS2_AN385 - select SOC_MPS2_AN386 if BOARD_MPS2_AN386 - select SOC_MPS2_AN500 if BOARD_MPS2_AN500 - select SOC_MPS2_AN521_CPU0 if BOARD_MPS2_AN521_CPU0 - select SOC_MPS2_AN521_CPU0 if BOARD_MPS2_AN521_CPU0_NS - select SOC_MPS2_AN521_CPU1 if BOARD_MPS2_AN521_CPU1 + select SOC_AN383 if BOARD_MPS2_AN383 + select SOC_AN385 if BOARD_MPS2_AN385 + select SOC_AN386 if BOARD_MPS2_AN386 + select SOC_AN500 if BOARD_MPS2_AN500 + select SOC_AN521_CPU0 if BOARD_MPS2_AN521_CPU0 + select SOC_AN521_CPU0 if BOARD_MPS2_AN521_CPU0_NS + select SOC_AN521_CPU1 if BOARD_MPS2_AN521_CPU1 diff --git a/boards/arm/mps2/doc/index.rst b/boards/arm/mps2/doc/index.rst index fbdfd3d0aa0e..c5830370f0bd 100644 --- a/boards/arm/mps2/doc/index.rst +++ b/boards/arm/mps2/doc/index.rst @@ -7,4 +7,7 @@ the links below to get more information about each board target. * :ref:`mps2_armv6m_board` * :ref:`mps2_armv7m_board` +Supported Features +=================== + .. zephyr:board-supported-hw:: diff --git a/boards/arm/mps2/doc/mps2_an521.rst b/boards/arm/mps2/doc/mps2_an521.rst index 35a0820841d4..b273edc4936e 100644 --- a/boards/arm/mps2/doc/mps2_an521.rst +++ b/boards/arm/mps2/doc/mps2_an521.rst @@ -150,33 +150,7 @@ The mps2/an521 board provides the following user push buttons: Supported Features =================== -The mps2/an521 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| TIMER | on-chip | timer | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by the port. -See the `MPS2 FPGA Website`_ for a complete list of MPS2+ AN521 board hardware -features. - -The default configuration can be found in -:zephyr_file:`boards/arm/mps2/mps2_an521_cpu0_defconfig`. +* Refer to :zephyr:board:`mps2` for details. Interrupt Controller ==================== @@ -390,8 +364,8 @@ boot in the Secure state. MPS2+ AN521 (CPU1) does not support the Armv8m Security Extension. -Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg| -============================================================================= +Building Secure/Non-Secure Zephyr applications with Arm® TrustZone® +=================================================================== Applications on the MPS2+ AN521 (CPU0) may contain a Secure and a Non-Secure firmware image. The Secure image can be built using either Zephyr diff --git a/boards/arm/mps2/doc/mps2_armv6m.rst b/boards/arm/mps2/doc/mps2_armv6m.rst index b390c27d96a6..cb435a30ea71 100644 --- a/boards/arm/mps2/doc/mps2_armv6m.rst +++ b/boards/arm/mps2/doc/mps2_armv6m.rst @@ -61,33 +61,7 @@ ARM V2M MPS2 AN383 provides the following hardware components: Supported Features ================== -The ``mps2/an383`` board target supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| TIMER | on-chip | counter | -+-----------+------------+-------------------------------------+ -| DUALTIMER | on-chip | counter | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by the port. -See the `V2M MPS2 Website`_ for a complete list of V2M MPS2 board hardware -features. - -The default configuration can be found in -:zephyr_file:`boards/arm/mps2/mps2_an383_defconfig` +* Refer to :zephyr:board:`mps2` for details. Interrupt Controller ==================== diff --git a/boards/arm/mps2/doc/mps2_armv7m.rst b/boards/arm/mps2/doc/mps2_armv7m.rst index 72ef21d3884c..0d728682fc28 100644 --- a/boards/arm/mps2/doc/mps2_armv7m.rst +++ b/boards/arm/mps2/doc/mps2_armv7m.rst @@ -68,34 +68,7 @@ ARM V2M MPS2 provides the following hardware components: Supported Features ================== -The ``mps2/an385``, ``mps2/an386``, and ``mps2/an500`` board targets support the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| TIMER | on-chip | counter | -+-----------+------------+-------------------------------------+ -| DUALTIMER | on-chip | counter | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by the port. -See the `V2M MPS2 Website`_ for a complete list of V2M MPS2 board hardware -features. - -The default configuration can be found in -:zephyr_file:`boards/arm/mps2/mps2_an385_defconfig` -or similarly in ``mps2_anxxx_defconfig`` for the other applicable boards. +* Refer to :zephyr:board:`mps2` for details. Interrupt Controller ==================== diff --git a/boards/arm/mps2/mps2_an521_cpu1.dts b/boards/arm/mps2/mps2_an521_cpu1.dts index acc956c42a3e..72f5d6a8e107 100644 --- a/boards/arm/mps2/mps2_an521_cpu1.dts +++ b/boards/arm/mps2/mps2_an521_cpu1.dts @@ -120,8 +120,8 @@ * https://github.com/zephyrproject-rtos/trusted-firmware-m/blob/master/platform/ext/target/arm/mps2/an521/partition/flash_layout.h */ - code: memory@38B000 { - reg = <0x0038B000 DT_SIZE_K(468)>; + code: memory@38b000 { + reg = <0x0038b000 DT_SIZE_K(468)>; }; /* This ram memory region's base address is chosen to avoid diff --git a/boards/arm/mps3/Kconfig.mps3 b/boards/arm/mps3/Kconfig.mps3 index 02d081f826ae..45127d4593b4 100644 --- a/boards/arm/mps3/Kconfig.mps3 +++ b/boards/arm/mps3/Kconfig.mps3 @@ -5,13 +5,13 @@ config BOARD_MPS3 select SOC_SERIES_MPS3 - select SOC_MPS3_CORSTONE300 if BOARD_MPS3_CORSTONE300_AN547 || \ + select SOC_CORSTONE300 if BOARD_MPS3_CORSTONE300_AN547 || \ BOARD_MPS3_CORSTONE300_AN547_NS || \ BOARD_MPS3_CORSTONE300_AN552 || \ BOARD_MPS3_CORSTONE300_AN552_NS || \ BOARD_MPS3_CORSTONE300_FVP || \ BOARD_MPS3_CORSTONE300_FVP_NS - select SOC_MPS3_CORSTONE310 if BOARD_MPS3_CORSTONE310_AN555 || \ + select SOC_CORSTONE310 if BOARD_MPS3_CORSTONE310_AN555 || \ BOARD_MPS3_CORSTONE310_AN555_NS || \ BOARD_MPS3_CORSTONE310_FVP || \ BOARD_MPS3_CORSTONE310_FVP_NS diff --git a/boards/arm/mps3/doc/index.rst b/boards/arm/mps3/doc/index.rst index 9cb944cfaa68..92987ff6888b 100644 --- a/boards/arm/mps3/doc/index.rst +++ b/boards/arm/mps3/doc/index.rst @@ -221,31 +221,7 @@ ARM MPS3 provides the following hardware components: Supported Features =================== -The ``MPS3`` board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by the port. -See the `MPS3 FPGA Website`_ for a complete list of MPS3 AN547 board hardware -features. - -The default configuration can be found in - - For AN547: :zephyr_file:`boards/arm/mps3/mps3_corstone300_an547_defconfig`. - - For AN552: :zephyr_file:`boards/arm/mps3/mps3_corstone300_an552_defconfig`. - - For FVP : :zephyr_file:`boards/arm/mps3/mps3_corstone300_fvp_defconfig`. - - For AN555: :zephyr_file:`boards/arm/mps3/mps3_corstone310_an555_defconfig`. - +.. zephyr:board-supported-hw:: Serial Port =========== @@ -352,9 +328,6 @@ For more details refer to: .. _Corstone-310 FVP: https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps -.. _MPS3 FPGA Website: - https://developer.arm.com/tools-and-software/development-boards/fpga-prototyping-boards/mps3 - .. _MPS3 AN547 Technical Reference Manual (TRM): https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/DAI0547B_SSE300_PLUS_U55_FPGA_for_mps3.pdf diff --git a/boards/arm/mps4/Kconfig.mps4 b/boards/arm/mps4/Kconfig.mps4 index 46ce14cc0620..bab6870bfd8e 100644 --- a/boards/arm/mps4/Kconfig.mps4 +++ b/boards/arm/mps4/Kconfig.mps4 @@ -3,5 +3,5 @@ config BOARD_MPS4 select SOC_SERIES_MPS4 - select SOC_MPS4_CORSTONE315 if BOARD_MPS4_CORSTONE315_FVP || BOARD_MPS4_CORSTONE315_FVP_NS - select SOC_MPS4_CORSTONE320 if BOARD_MPS4_CORSTONE320_FVP || BOARD_MPS4_CORSTONE320_FVP_NS + select SOC_CORSTONE315 if BOARD_MPS4_CORSTONE315_FVP || BOARD_MPS4_CORSTONE315_FVP_NS + select SOC_CORSTONE320 if BOARD_MPS4_CORSTONE320_FVP || BOARD_MPS4_CORSTONE320_FVP_NS diff --git a/boards/arm/v2m_beetle/doc/index.rst b/boards/arm/v2m_beetle/doc/index.rst index 49df438d3f90..203f6132ecf0 100644 --- a/boards/arm/v2m_beetle/doc/index.rst +++ b/boards/arm/v2m_beetle/doc/index.rst @@ -1,4 +1,4 @@ -.. _v2m_beetle_board: +.. zephyr:board:: v2m_beetle ARM V2M Beetle ############## @@ -49,36 +49,7 @@ ARM V2M BEETLE provides the following hardware components: Supported Features =================== -The v2m_beetle board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| TIMER | on-chip | timer | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by the port. -See the `V2M Beetle Website`_ for a complete list of V2M Beetle board hardware -features. - -The default configuration can be found in the defconfig file: - -.. code-block:: console - - boards/arm/v2m_beetle/v2m_beetle_defconfig +.. zephyr:board-supported-hw:: Interrupt Controller ==================== diff --git a/boards/arm/v2m_musca_b1/CMakeLists.txt b/boards/arm/v2m_musca_b1/CMakeLists.txt index 2ba52c47c83c..44358da90628 100644 --- a/boards/arm/v2m_musca_b1/CMakeLists.txt +++ b/boards/arm/v2m_musca_b1/CMakeLists.txt @@ -1,8 +1,15 @@ # # Copyright (c) 2019,2020 Linaro Limited +# Copyright 2026 Arm Limited and/or its affiliates # # SPDX-License-Identifier: Apache-2.0 # zephyr_library() zephyr_library_sources(pinmux.c) + +if(CONFIG_BUILD_WITH_TFM) + set_property(TARGET zephyr_property_target + APPEND PROPERTY TFM_CMAKE_OPTIONS -DCRYPTO_HW_ACCELERATOR=OFF + ) +endif() diff --git a/boards/arm/v2m_musca_b1/Kconfig.v2m_musca_b1 b/boards/arm/v2m_musca_b1/Kconfig.v2m_musca_b1 index 3171dc5033ef..0014c62d93cb 100644 --- a/boards/arm/v2m_musca_b1/Kconfig.v2m_musca_b1 +++ b/boards/arm/v2m_musca_b1/Kconfig.v2m_musca_b1 @@ -2,4 +2,4 @@ # SPDX-License-Identifier: Apache-2.0 config BOARD_V2M_MUSCA_B1 - select SOC_V2M_MUSCA_B1 + select SOC_MUSCA_B1 diff --git a/boards/arm/v2m_musca_b1/doc/index.rst b/boards/arm/v2m_musca_b1/doc/index.rst index 93a56df93409..1f292d398dbf 100644 --- a/boards/arm/v2m_musca_b1/doc/index.rst +++ b/boards/arm/v2m_musca_b1/doc/index.rst @@ -1,4 +1,4 @@ -.. _v2m_musca_b1_board: +.. zephyr:board:: v2m_musca_b1 ARM V2M Musca B1 ################ @@ -72,33 +72,7 @@ The v2m_musca_b1 board provides the following user push buttons: Supported Features =================== -The v2m_musca_b1 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| TIMER | on-chip | timer | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by the port. -See the `V2M Musca B1 Website`_ for a complete list of V2M Musca board hardware -features. - -The default configuration can be found in the defconfig file: -:zephyr_file:`boards/arm/v2m_musca_b1/v2m_musca_b1_defconfig`. +.. zephyr:board-supported-hw:: Interrupt Controller ==================== diff --git a/boards/arm/v2m_musca_b1/v2m_musca_b1_musca_b1_ns.dts b/boards/arm/v2m_musca_b1/v2m_musca_b1_musca_b1_ns.dts index c24d8c256754..550f9996b8a7 100644 --- a/boards/arm/v2m_musca_b1/v2m_musca_b1_musca_b1_ns.dts +++ b/boards/arm/v2m_musca_b1/v2m_musca_b1_musca_b1_ns.dts @@ -1,5 +1,6 @@ /* * Copyright (c) 2019 Linaro Limited + * Copyright 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,6 +8,7 @@ /dts-v1/; #include +#include / { compatible = "arm,v2m-musca"; @@ -19,6 +21,7 @@ zephyr,console = &uart1; zephyr,sram = &sram0; zephyr,flash = &flash0; + zephyr,code-partitions = &slot0_ns_partition; zephyr,shell-uart = &uart1; }; @@ -40,9 +43,31 @@ }; }; - flash0: flash@a070000 { + flash0: flash@a000000 { /* Embedded flash */ - reg = <0xa070000 0x1a0000>; + compatible = "soc-nv-flash"; + reg = <0x0a000000 DT_SIZE_M(2)>; + erase-block-size = ; + write-block-size = <4>; + #address-cells = <1>; + #size-cells = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Please see the memory layout in: + * https://git.trustedfirmware.org/plugins/gitiles/TF-M/trusted-firmware-m.git/+/refs/heads/main/platform/ext/target/arm/musca_b1/partition/flash_layout.h + */ + slot0_partition: partition@20000 { + reg = <0x20000 DT_SIZE_K(384)>; + }; + + slot0_ns_partition: partition@80000 { + reg = <0x80000 DT_SIZE_K(512)>; + }; + }; }; sram0: memory@20040000 { diff --git a/boards/arm/v2m_musca_s1/CMakeLists.txt b/boards/arm/v2m_musca_s1/CMakeLists.txt index bbb12938dcee..15313d539ab3 100644 --- a/boards/arm/v2m_musca_s1/CMakeLists.txt +++ b/boards/arm/v2m_musca_s1/CMakeLists.txt @@ -1,8 +1,15 @@ # # Copyright (c) 2019-2020 Linaro Limited +# Copyright 2026 Arm Limited and/or its affiliates # # SPDX-License-Identifier: Apache-2.0 # zephyr_library() zephyr_library_sources(pinmux.c) + +if(CONFIG_BUILD_WITH_TFM) + set_property(TARGET zephyr_property_target + APPEND PROPERTY TFM_CMAKE_OPTIONS -DCRYPTO_HW_ACCELERATOR=OFF + ) +endif() diff --git a/boards/arm/v2m_musca_s1/Kconfig.v2m_musca_s1 b/boards/arm/v2m_musca_s1/Kconfig.v2m_musca_s1 index fd5ab86f341c..0d6c6497a218 100644 --- a/boards/arm/v2m_musca_s1/Kconfig.v2m_musca_s1 +++ b/boards/arm/v2m_musca_s1/Kconfig.v2m_musca_s1 @@ -2,4 +2,4 @@ # SPDX-License-Identifier: Apache-2.0 config BOARD_V2M_MUSCA_S1 - select SOC_V2M_MUSCA_S1 + select SOC_MUSCA_S1 diff --git a/boards/arm/v2m_musca_s1/doc/index.rst b/boards/arm/v2m_musca_s1/doc/index.rst index bbcd1ba9b7eb..0298d424f363 100644 --- a/boards/arm/v2m_musca_s1/doc/index.rst +++ b/boards/arm/v2m_musca_s1/doc/index.rst @@ -1,4 +1,4 @@ -.. _v2m_musca_s1_board: +.. zephyr:board:: v2m_musca_s1 ARM V2M Musca-S1 ################ @@ -69,33 +69,7 @@ The v2m_musca_s1 board provides the following user push buttons: Supported Features =================== -The v2m_musca_s1 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| TIMER | on-chip | timer | -+-----------+------------+-------------------------------------+ -| TrustZone | on-chip | Trusted Firmware-M | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by the port. -See the `V2M Musca-S1 Website`_ for a complete list of V2M Musca-S1 board -hardware features. - -The default configuration can be found in the defconfig file: -:zephyr_file:`boards/arm/v2m_musca_s1/v2m_musca_s1_defconfig`. +.. zephyr:board-supported-hw:: Interrupt Controller ==================== diff --git a/boards/arm/v2m_musca_s1/v2m_musca_s1_musca_s1_ns.dts b/boards/arm/v2m_musca_s1/v2m_musca_s1_musca_s1_ns.dts index afe985c20f6f..8c9775ba215c 100644 --- a/boards/arm/v2m_musca_s1/v2m_musca_s1_musca_s1_ns.dts +++ b/boards/arm/v2m_musca_s1/v2m_musca_s1_musca_s1_ns.dts @@ -1,5 +1,6 @@ /* * Copyright (c) 2019-2020 Linaro Limited + * Copyright 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,6 +8,7 @@ /dts-v1/; #include +#include / { compatible = "arm,v2m-musca"; @@ -19,6 +21,7 @@ zephyr,console = &uart1; zephyr,sram = &sram0; zephyr,flash = &mram0; + zephyr,code-partitions = &slot0_ns_partition; zephyr,shell-uart = &uart1; }; @@ -40,9 +43,31 @@ }; }; - mram0: mram@a080000 { + mram0: mram@a000000 { /* Internal code eMRAM */ - reg = <0x0a080000 0x80000>; + compatible = "soc-nv-flash"; + reg = <0x0a000000 DT_SIZE_M(2)>; + erase-block-size = ; + write-block-size = <1>; + #address-cells = <1>; + #size-cells = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Please see the memory layout in: + * https://github.com/zephyrproject-rtos/trusted-firmware-m/blob/zephyr_tf-m_v2.2.2/platform/ext/target/arm/musca_s1/partition/flash_layout.h + */ + slot0_partition: partition@20000 { + reg = <0x20000 DT_SIZE_K(384)>; + }; + + slot0_ns_partition: partition@80000 { + reg = <0x80000 DT_SIZE_K(512)>; + }; + }; }; sram0: memory@20040000 { diff --git a/boards/bbc/microbit_v2/bbc_microbit_v2.dts b/boards/bbc/microbit_v2/bbc_microbit_v2.dts index 112e857df51a..2ec032af8132 100644 --- a/boards/bbc/microbit_v2/bbc_microbit_v2.dts +++ b/boards/bbc/microbit_v2/bbc_microbit_v2.dts @@ -165,27 +165,27 @@ boot_partition: partition@0 { label = "mcuboot"; - reg = <0x00000000 0xC000>; + reg = <0x00000000 0xc000>; }; slot0_partition: partition@c000 { label = "image-0"; - reg = <0x0000C000 0x32000>; + reg = <0x0000c000 0x32000>; }; slot1_partition: partition@3e000 { label = "image-1"; - reg = <0x0003E000 0x32000>; + reg = <0x0003e000 0x32000>; }; scratch_partition: partition@70000 { label = "image-scratch"; - reg = <0x00070000 0xA000>; + reg = <0x00070000 0xa000>; }; storage_partition: partition@7a000 { label = "storage"; - reg = <0x0007A000 0x00006000>; + reg = <0x0007a000 0x00006000>; }; }; }; diff --git a/boards/bcdevices/plt_demo_v2/blueclover_plt_demo_v2_nrf52832.dts b/boards/bcdevices/plt_demo_v2/blueclover_plt_demo_v2_nrf52832.dts index f712184c3444..fa889b01c4e2 100644 --- a/boards/bcdevices/plt_demo_v2/blueclover_plt_demo_v2_nrf52832.dts +++ b/boards/bcdevices/plt_demo_v2/blueclover_plt_demo_v2_nrf52832.dts @@ -136,12 +136,12 @@ slot0_partition: partition@c000 { label = "image-0"; - reg = <0x0000C000 0x32000>; + reg = <0x0000c000 0x32000>; }; slot1_partition: partition@3e000 { label = "image-1"; - reg = <0x0003E000 0x32000>; + reg = <0x0003e000 0x32000>; }; scratch_partition: partition@70000 { diff --git a/boards/beagle/beagleconnect_freedom/beagleconnect_freedom.dts b/boards/beagle/beagleconnect_freedom/beagleconnect_freedom.dts index 3187a51aceeb..5ec74a28f536 100644 --- a/boards/beagle/beagleconnect_freedom/beagleconnect_freedom.dts +++ b/boards/beagle/beagleconnect_freedom/beagleconnect_freedom.dts @@ -194,7 +194,7 @@ }; /* Allocate 128 KiB scratch for image swap */ - scratch_partition: partition@A0000 { + scratch_partition: partition@a0000 { label = "image-scratch"; reg = <0x000a0000 DT_SIZE_K(128)>; }; diff --git a/boards/beagle/beagley_ai/beagley_ai_j722s_mcu_r5f0_0.dts b/boards/beagle/beagley_ai/beagley_ai_j722s_mcu_r5f0_0.dts index 2c6f9f8c5f4f..624ebc4e11e9 100644 --- a/boards/beagle/beagley_ai/beagley_ai_j722s_mcu_r5f0_0.dts +++ b/boards/beagle/beagley_ai/beagley_ai_j722s_mcu_r5f0_0.dts @@ -23,6 +23,10 @@ zephyr,ipc_shm = &ddr0; }; + aliases { + watchdog0 = &mcu_rti0; + }; + cpus { cpu@0 { status = "okay"; @@ -63,3 +67,7 @@ &systick_timer { status = "okay"; }; + +&mcu_rti0 { + status = "okay"; +}; diff --git a/boards/bflb/bl60x/bl604e_iot_dvk/board.cmake b/boards/bflb/bl60x/bl604e_iot_dvk/board.cmake index 29a318dbdb8a..59cbba67235c 100644 --- a/boards/bflb/bl60x/bl604e_iot_dvk/board.cmake +++ b/boards/bflb/bl60x/bl604e_iot_dvk/board.cmake @@ -4,7 +4,7 @@ board_runner_args(openocd --cmd-pre-init "source [find bl60x.cfg]") -board_runner_args(openocd --use-elf --no-load --no-init) +board_runner_args(openocd --file-type=elf --no-load --no-init) board_runner_args(openocd --gdb-init "set mem inaccessible-by-default off") board_runner_args(openocd --gdb-init "set architecture riscv:rv32") board_runner_args(openocd --gdb-init "set remotetimeout 250") diff --git a/boards/bflb/bl60x/bl604e_iot_dvk/pre_dt_board.cmake b/boards/bflb/bl60x/bl604e_iot_dvk/pre_dt_board.cmake new file mode 100644 index 000000000000..c3a69b990ff0 --- /dev/null +++ b/boards/bflb/bl60x/bl604e_iot_dvk/pre_dt_board.cmake @@ -0,0 +1,4 @@ +# Copyright The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") diff --git a/boards/blackberry/index.rst b/boards/blackberry/index.rst new file mode 100644 index 000000000000..6031e708b092 --- /dev/null +++ b/boards/blackberry/index.rst @@ -0,0 +1,10 @@ +.. _boards-blackberry: + +BlackBerry +########## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/blackberry/qnxhv_vm/Kconfig.qnxhv_vm b/boards/blackberry/qnxhv_vm/Kconfig.qnxhv_vm new file mode 100644 index 000000000000..be9bb59e74b5 --- /dev/null +++ b/boards/blackberry/qnxhv_vm/Kconfig.qnxhv_vm @@ -0,0 +1,5 @@ +# Copyright (c) 2025 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QNXHV_VM + select SOC_QNXHV_VM diff --git a/boards/blackberry/qnxhv_vm/board.yml b/boards/blackberry/qnxhv_vm/board.yml new file mode 100644 index 000000000000..ec77f7c72766 --- /dev/null +++ b/boards/blackberry/qnxhv_vm/board.yml @@ -0,0 +1,6 @@ +board: + name: qnxhv_vm + full_name: QNX Hypervisor Virtual Machine + vendor: blackberry + socs: + - name: qnxhv_vm diff --git a/boards/blackberry/qnxhv_vm/doc/index.rst b/boards/blackberry/qnxhv_vm/doc/index.rst new file mode 100644 index 000000000000..22224d0eaad5 --- /dev/null +++ b/boards/blackberry/qnxhv_vm/doc/index.rst @@ -0,0 +1,115 @@ +.. zephyr:board:: qnxhv_vm + +Overview +******** + +This board enables running Zephyr as a guest inside a QNX Hypervisor virtual +machine. + +This is an example configuration. VM layouts are typically unique per product, +so you will likely need to adjust the devicetree and Kconfig options to match +your VM configuration (memory map, interrupt routing, clocks, devices, etc.). + +Hardware +******** + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +.. _qvmconf: + +QNX Hypervisor Virtual Machine Configuration +-------------------------------------------- + +The virtual hardware exposed to the guest depends on the VM configuration file. +The above features are supported by following configuration. + +.. code-block:: + + # Guest name (optional) + system zephyr + + # One vCPU + cpu + + # Guest RAM base/size + ram 0x80000000,128M + + # Virtual interrupt controller + vdev gic version 2 + + # Load Zephyr image (ELF is supported by qvm) + load ./zephyr.elf + + # PL011 UART mapped into the guest at loc, routed to a host device/endpoint + vdev pl011 + hostdev >- # QVM console (stdout/stderr), keeps early output visible + loc 0x1c090000 + intr gic:37 + + # Enable virtio-console (Need to disable CONFIG_BOOT_BANNER) + vdev virtio-console + loc 0x20000000 + intr gic:42 + + # Enable random number generator + vdev virtio-entropy + loc 0x1c0e0000 + intr gic:43 + + +Building and Running +******************** + +Build an application +==================== + +Use this board configuration to run basic Zephyr applications as a guest. +For example, build the :zephyr:code-sample:`synchronization` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :board: qnxhv_vm + :goals: build + +This produces a guest image (e.g. ``zephyr/zephyr.elf``) under the build directory. + +Create a VM Configuration file +============================== + +You also need to create ``.qvmconf`` file to configure virtual machine. +:ref:`qvmconf` is a example QVM configuration which is support by default +``qnxhv_vm`` configuration. + +Here, create a file named ``zephyr.qvmconf`` with the contents of this example. + +Running an application +====================== + +Transfer both the Zephyr image and the QVM configuration file to the QNX +Hypervisor machine, then start the VM: + +.. code-block:: console + + qvm @zephyr.qvmconf + +You will see Zephyr output: + +.. code-block:: console + + *** Booting Zephyr OS build v4.3.0-3524-g5c47f098ffc4 *** + thread_a: Hello World from cpu 0 on qnxhv_vm! + thread_b: Hello World from cpu 0 on qnxhv_vm! + thread_a: Hello World from cpu 0 on qnxhv_vm! + thread_b: Hello World from cpu 0 on qnxhv_vm! + thread_a: Hello World from cpu 0 on qnxhv_vm! + +Use :kbd:`CTRL+C` to stop the virtual machine. + + +References +********** + +- `QNX Hypervisor User's Guide (VM configuration) `_ diff --git a/boards/blackberry/qnxhv_vm/qnxhv_vm.dts b/boards/blackberry/qnxhv_vm/qnxhv_vm.dts new file mode 100644 index 000000000000..5416493dedcf --- /dev/null +++ b/boards/blackberry/qnxhv_vm/qnxhv_vm.dts @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2025 TOKITA Hiroshi + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include + +/ { + model = "QNX Hypervisor Virtual Machine"; + compatible = "blackberry,qnxhv_vm"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &qvm_console; + zephyr,shell-uart = &qvm_console; + zephyr,entropy = &virtio_entropy; + }; + + cpus { + #address-cells = <0x01>; + #size-cells = <0x00>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + enable-method = "psci"; + reg = <0x00>; + }; + }; + + uartclk: apb-pclk { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + #clock-cells = <0>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "hvc"; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + + sram0: memory@80000000 { + compatible = "mmio-sram"; + reg = <0x0 0x80000000 0x0 DT_SIZE_M(128)>; + }; + + gic: interrupt-controller@2c001000 { + compatible = "arm,gic-v2", "arm,gic"; + reg = <0x00 0x2c001000 0x00 0x00001000>, + <0x00 0x2c002000 0x00 0x00002000>; + interrupt-controller; + #interrupt-cells = <4>; + status = "okay"; + }; + + timer: timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + clock-frequency = <54000000>; + }; + + qvm_console: uart@1c090000 { + compatible = "arm,pl011"; + reg = <0x00 0x1c090000 0x00 0x1000>; + interrupts = ; + interrupt-names = "irq_0"; + clocks = <&uartclk>; + current-speed = <115200>; + status = "okay"; + }; + + virtio_mmio@20000000 { + compatible = "virtio,mmio"; + reg = <0x0 0x20000000 0x0 0x1000>; + interrupts = ; + status = "okay"; + + virtio_console: virtio-console { + compatible = "virtio,console"; + status = "okay"; + }; + }; + + virtio_mmio@1c0e0000 { + compatible = "virtio,mmio"; + reg = <0x0 0x1c0e0000 0x0 0x1000>; + interrupts = ; + status = "okay"; + + virtio_entropy: virtio-entropy { + compatible = "virtio,device4"; + status = "okay"; + }; + }; + }; +}; diff --git a/boards/blackberry/qnxhv_vm/qnxhv_vm.yaml b/boards/blackberry/qnxhv_vm/qnxhv_vm.yaml new file mode 100644 index 000000000000..8ad8ffbc4701 --- /dev/null +++ b/boards/blackberry/qnxhv_vm/qnxhv_vm.yaml @@ -0,0 +1,9 @@ +identifier: qnxhv_vm +name: QNX Hypervisor Virtual Machine +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 131072 +vendor: blackberry diff --git a/boards/blackberry/qnxhv_vm/qnxhv_vm_defconfig b/boards/blackberry/qnxhv_vm/qnxhv_vm_defconfig new file mode 100644 index 000000000000..b7d592cecb6f --- /dev/null +++ b/boards/blackberry/qnxhv_vm/qnxhv_vm_defconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2025 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/blues/cygnet/doc/index.rst b/boards/blues/cygnet/doc/index.rst index 8283eb15db69..6684cb149444 100644 --- a/boards/blues/cygnet/doc/index.rst +++ b/boards/blues/cygnet/doc/index.rst @@ -21,16 +21,16 @@ Hardware The STM32L433CC SoC provides the following hardware IPs: - Ultra-low-power with FlexPowerControl (down to 28 nA Standby mode and 84 - |micro| A/MHz run mode) -- Core: ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU, frequency up to 80 MHz, + µA/MHz run mode) +- Core: ARM® 32-bit Cortex®-M4 CPU with FPU, frequency up to 80 MHz, 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) - Clock Sources: - 32 kHz crystal oscillator for RTC (LSE) - - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) - - Internal low-power 32 kHz RC ( |plusminus| 5%) + - Internal 16 MHz factory-trimmed RC (±1%) + - Internal low-power 32 kHz RC (±5%) - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by - LSE (better than |plusminus| 0.25 % accuracy) + LSE (better than ±0.25 % accuracy) - 2 PLLs for system clock, USB, audio, ADC - RTC with HW calendar, alarms and calibration @@ -52,7 +52,7 @@ The STM32L433CC SoC provides the following hardware IPs: - Rich analog peripherals (independent supply) - 1x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 - |micro| A/MSPS + µA/MSPS - 2x 12-bit DAC output channels, low-power sample and hold - 1x operational amplifiers with built-in PGA - 2x ultra-low-power comparators diff --git a/boards/blues/swan_r5/doc/index.rst b/boards/blues/swan_r5/doc/index.rst index 0c2c796abd4c..12c7c73470ae 100644 --- a/boards/blues/swan_r5/doc/index.rst +++ b/boards/blues/swan_r5/doc/index.rst @@ -59,7 +59,7 @@ The STM32L4R5ZI SoC provides the following hardware IPs: - Ultra-low-power with FlexPowerControl (down to 130 nA Standby mode and 100 uA/MHz run mode) -- Core: ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU, adaptive +- Core: ARM® 32-bit Cortex®-M4 CPU with FPU, adaptive real-time accelerator (ART Accelerator) allowing 0-wait-state execution from Flash memory, frequency up to 120 MHz, MPU, 150 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions diff --git a/boards/blues/swan_r5/swan_r5.dts b/boards/blues/swan_r5/swan_r5.dts index 795751591c33..95e8c1f6981c 100644 --- a/boards/blues/swan_r5/swan_r5.dts +++ b/boards/blues/swan_r5/swan_r5.dts @@ -188,9 +188,9 @@ zephyr_udc0: &usbotg_fs { #size-cells = <1>; /* Reserve last 16KiB for property storage */ - storage_partition: partition@1FB000 { + storage_partition: partition@1fb000 { label = "storage"; - reg = <0x001FB000 0x00004000>; + reg = <0x001fb000 0x00004000>; }; }; }; diff --git a/boards/bytesatwork/bytesensi_l/bytesensi_l.dts b/boards/bytesatwork/bytesensi_l/bytesensi_l.dts index baf7b0209d6c..f68e66c7d5fd 100644 --- a/boards/bytesatwork/bytesensi_l/bytesensi_l.dts +++ b/boards/bytesatwork/bytesensi_l/bytesensi_l.dts @@ -43,12 +43,12 @@ slot0_partition: partition@c000 { label = "image-0"; - reg = <0x0000C000 0x32000>; + reg = <0x0000c000 0x32000>; }; slot1_partition: partition@3e000 { label = "image-1"; - reg = <0x0003E000 0x32000>; + reg = <0x0003e000 0x32000>; }; scratch_partition: partition@70000 { diff --git a/boards/circuitdojo/feather/circuitdojo_feather_nrf9160_ns.dts b/boards/circuitdojo/feather/circuitdojo_feather_nrf9160_ns.dts index ae1589e85b22..c4e93476e1fe 100644 --- a/boards/circuitdojo/feather/circuitdojo_feather_nrf9160_ns.dts +++ b/boards/circuitdojo/feather/circuitdojo_feather_nrf9160_ns.dts @@ -6,7 +6,7 @@ */ /dts-v1/; -#include +#include #include "circuitdojo_feather_nrf9160_common.dtsi" / { diff --git a/boards/cirrus/crd40l50/Kconfig.crd40l50 b/boards/cirrus/crd40l50/Kconfig.crd40l50 new file mode 100644 index 000000000000..c21d3d8c5a19 --- /dev/null +++ b/boards/cirrus/crd40l50/Kconfig.crd40l50 @@ -0,0 +1,10 @@ +# Copyright (c) 2026 Cirrus Logic, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# Required to select STM32F401XE instead of STM32F401XD because the STM32 HAL +# does not provide a #define for STM32F401xD variants. Because STM32F401xD and +# STM32F401xE microcontrollers are identical apart from the size of embedded +# flash memory, we select SOC_STM32F401XE. + +config BOARD_CRD40L50 + select SOC_STM32F401XE diff --git a/boards/cirrus/crd40l50/Kconfig.defconfig b/boards/cirrus/crd40l50/Kconfig.defconfig new file mode 100644 index 000000000000..50a2f9bf9a5a --- /dev/null +++ b/boards/cirrus/crd40l50/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Cirrus CRD40L50 Blackstar board configuration + +# Copyright (c) 2026 Cirrus Logic, Inc. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_CRD40L50 + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_CRD40L50 diff --git a/boards/cirrus/crd40l50/board.cmake b/boards/cirrus/crd40l50/board.cmake new file mode 100644 index 000000000000..10a33a180c40 --- /dev/null +++ b/boards/cirrus/crd40l50/board.cmake @@ -0,0 +1,9 @@ +# Copyright (c) 2026 Cirrus Logic, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") +board_runner_args(jlink "--device=STM32F401CD" "--speed=4000") + +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/cirrus/crd40l50/board.yml b/boards/cirrus/crd40l50/board.yml new file mode 100644 index 000000000000..ae27fb9cf9e0 --- /dev/null +++ b/boards/cirrus/crd40l50/board.yml @@ -0,0 +1,6 @@ +board: + name: crd40l50 + full_name: CRD40L50-POC-Q + vendor: cirrus + socs: + - name: stm32f401xd diff --git a/boards/cirrus/crd40l50/crd40l50.dts b/boards/cirrus/crd40l50/crd40l50.dts new file mode 100644 index 000000000000..0d807b1990eb --- /dev/null +++ b/boards/cirrus/crd40l50/crd40l50.dts @@ -0,0 +1,199 @@ +/* + * Copyright (c) 2026 Cirrus Logic, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include + +/ { + model = "Cirrus Logic CRD40L50-POC-Q"; + compatible = "cirrus,crd40l50"; + + aliases { + flash1 = &flash_1; + haptic0 = &haptic_0; + led0 = &green_led_1; + led1 = &red_led_1; + led2 = &yellow_led_1; + led3 = &yellow_led_2; + led4 = &yellow_led_3; + sw0 = &user_button; + }; + + buttons { + compatible = "gpio-keys"; + + user_button: button { + label = "User"; + gpios = <&gpioa 2 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; + + chosen { + zephyr,code-partition = &slot0_partition; + zephyr,console = &rtt0; + zephyr,flash = &flash0; + zephyr,shell-uart = &usart1; + zephyr,sram = &sram0; + }; + + leds { + compatible = "gpio-leds"; + + green_led_1: led_1 { + gpios = <&gpiob 5 GPIO_ACTIVE_HIGH>; + label = "LED PASS"; + }; + + red_led_1: led_2 { + gpios = <&gpiob 8 GPIO_ACTIVE_HIGH>; + label = "LED FAIL"; + }; + + yellow_led_1: led_3 { + gpios = <&gpiob 9 GPIO_ACTIVE_HIGH>; + label = "SEL LED 1"; + }; + + yellow_led_2: led_4 { + gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>; + label = "SEL LED 2"; + }; + + yellow_led_3: led_5 { + gpios = <&gpioa 3 GPIO_ACTIVE_HIGH>; + label = "SEL LED 3"; + }; + }; + + rtt0: rtt_chan0 { + compatible = "segger,rtt-uart"; + status = "okay"; + }; +}; + +&clk_lse { + status = "okay"; +}; + +&clk_hsi { + status = "okay"; +}; + +&pll { + status = "okay"; + + clocks = <&clk_hsi>; + + div-m = <16>; + mul-n = <336>; + div-p = <4>; + div-q = <7>; +}; + +&rcc { + clocks = <&pll>; + clock-frequency = ; + + ahb-prescaler = <1>; + apb1-prescaler = <2>; + apb2-prescaler = <1>; +}; + +&i2c1 { + status = "okay"; + + clock-frequency = ; + + pinctrl-0 = <&i2c1_scl_pb6 &i2c1_sda_pb7>; + pinctrl-1 = <&analog_pb6 &analog_pb7>; + pinctrl-names = "default", "sleep"; + + haptic_0: haptic@30 { + compatible = "cirrus,cs40l5x"; + reg = <0x30>; + + reset-gpios = <&gpiob 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + int-gpios = <&gpioh 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + + trigger-mapping = <11 12 13>; + trigger-gpios = <&gpioa 8 GPIO_PULL_UP>, + <&gpioa 9 GPIO_PULL_UP>, + <&gpiob 10 GPIO_PULL_UP>; + + flash-storage = <&flash_1>; + flash-offset = <0x0>; + + status = "okay"; + }; +}; + +&spi2 { + status = "okay"; + + cs-gpios = <&gpiob 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + + pinctrl-0 = <&spi2_sck_pb13 &spi2_miso_pb14 &spi2_mosi_pb15>; + pinctrl-1 = <&analog_pb13 &analog_pb14 &analog_pb15>; + pinctrl-names = "default", "sleep"; + + flash_1: flash@0 { + compatible = "atmel,at25xv021a"; + reg = <0>; + spi-max-frequency = <25000000>; + + size = ; + page-size = <256>; + timeout = <10>; + timeout-erase = <4000>; + + wp-gpios = <&gpiob 2 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + + status = "okay"; + }; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(64)>; + read-only; + }; + + /* + * The flash starting at offset 0x10000 and ending at + * offset 0x1ffff is reserved for use by the application. + */ + + slot0_partition: partition@20000 { + label = "image-0"; + reg = <0x00020000 DT_SIZE_K(64)>; + }; + + slot1_partition: partition@30000 { + label = "image-1"; + reg = <0x00030000 DT_SIZE_K(64)>; + }; + + scratch_partition: partition@40000 { + label = "image-scratch"; + reg = <0x00040000 DT_SIZE_K(64)>; + }; + + storage_partition: partition@50000 { + label = "storage"; + reg = <0x00050000 DT_SIZE_K(64)>; + }; + }; +}; diff --git a/boards/cirrus/crd40l50/crd40l50.yaml b/boards/cirrus/crd40l50/crd40l50.yaml new file mode 100644 index 000000000000..229f5f9bbbc0 --- /dev/null +++ b/boards/cirrus/crd40l50/crd40l50.yaml @@ -0,0 +1,14 @@ +identifier: crd40l50 +name: CRD40L50-POC-Q +type: mcu +arch: arm +toolchain: + - zephyr +supported: + - gpio + - i2c + - spi + - rtc +ram: 96 +flash: 384 +vendor: cirrus diff --git a/boards/cirrus/crd40l50/crd40l50_defconfig b/boards/cirrus/crd40l50/crd40l50_defconfig new file mode 100644 index 000000000000..54a56a4734c4 --- /dev/null +++ b/boards/cirrus/crd40l50/crd40l50_defconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2026 Cirrus Logic, Inc. +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_GPIO=y + +# Required to flash and debug with the SEGGER J-Link +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_RTT_CONSOLE=y +CONFIG_UART_RTT=y +CONFIG_USE_SEGGER_RTT=y diff --git a/boards/cirrus/crd40l50/doc/img/cirrus_crd40l50.webp b/boards/cirrus/crd40l50/doc/img/cirrus_crd40l50.webp new file mode 100644 index 000000000000..b05ccbb5f80a Binary files /dev/null and b/boards/cirrus/crd40l50/doc/img/cirrus_crd40l50.webp differ diff --git a/boards/cirrus/crd40l50/doc/index.rst b/boards/cirrus/crd40l50/doc/index.rst new file mode 100644 index 000000000000..ad3ab6fb9ebe --- /dev/null +++ b/boards/cirrus/crd40l50/doc/index.rst @@ -0,0 +1,99 @@ +.. zephyr:board:: crd40l50 + +Overview +******** + +The CRD40L50-POC-Q "Blackstar" demonstration board is a hardware platform +used to evaluate Cirrus Logic CS40L50 haptic drivers. The board provides +a set of features that enables programming the on-board STM32F401xD +microcontroller with custom sample applications, including the CS40L5x +sample provided in Zephyr's samples directory. + +Hardware +******** + +- STM32F401xD microcontroller +- AT25 SPI flash controller with 256 KiB flash memory +- 32.768 kHz crystal oscillator +- Two pass/fail LEDs, one green and one red +- Three yellow user LEDs +- One user push button +- Power source selector switch +- Actuator output for LRAs +- One Pico-Clasp connector for GPIOs +- One USB-C port for Cirrus Logic ETHapBridge connectivity +- Programming and debugging of on-board STM32F401xD through Serial Wire Debug (SWD) + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Connections and IOs +=================== + +- Molex 1053131302 connector (J4) for haptic output +- JST S2B-PH-SM4-TB(LF)(SN) connector (J5) for external power sources +- SWD header (J7) for J-Link debug probes +- Molex 203559-0607 connector (J8) for GPIOs +- USB-C port (J10) for ETHapBridge connectivity + +Programming & Debugging +*********************** + +.. zephyr:board-supported-runners:: + +Flash Using J-Link +================== + +To flash the board using the J-Link debugger, follow the steps below: + +1. Install J-Link Software + + - Download and install the `J-Link software`_ tools from Segger. + - Make sure the installed J-Link executables (e.g., ``JLink``, ``JLinkRTTViewer``) + are available in your system's PATH. + +2. Connect the Board + + - Connect the `J-Link Debug Probe`_ to the board's SWD header (J7). + - Connect the other end of the J-Link Debug Probe to your **host machine** via USB. + - Connect the VBAT connector (J5) to an external power source to **power up the board**. + +3. Build the Application + + You can build a sample Zephyr application, such as **Blinky** or **cs40l5x**, using + the ``west`` tool. Run the following commands from your Zephyr workspace: + + .. code-block:: console + + west build -b crd40l50 -p always samples/drivers/haptics/cs40l5x + + This will build the CS40L5x sample application for the ``crd40l50`` board. + +4. Flash the Device + + Once the build completes, flash the firmware using: + + .. code-block:: console + + west flash --runner jlink + + This uses the ``jlink`` runner to flash the application to the board. + +5. Observe the Result + + After flashing, interact with the Shell interface via ``JLinkRTTViewer`` to demo + the on-board CS40L50 haptics driver. + +References +********** + +.. _Cirrus Logic: + https://www.cirrus.com/support + +.. _J-Link software: + https://www.segger.com/downloads/jlink + +.. _J-Link Debug Probe: + https://www.segger.com/products/debug-probes/j-link/ diff --git a/boards/cirrus/index.rst b/boards/cirrus/index.rst new file mode 100644 index 000000000000..7cd004140cc3 --- /dev/null +++ b/boards/cirrus/index.rst @@ -0,0 +1,10 @@ +.. _boards-cirrus: + +Cirrus Logic, Inc. +################## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/common/esp32.board.cmake b/boards/common/esp32.board.cmake index 4669c2e620be..81b987bac7b1 100644 --- a/boards/common/esp32.board.cmake +++ b/boards/common/esp32.board.cmake @@ -3,13 +3,29 @@ board_set_flasher_ifnset(esp32) board_set_debugger_ifnset(openocd) -board_runner_args(openocd --no-init --no-halt --no-targets --no-load) -board_runner_args(openocd --gdb-init "set remote hardware-watchpoint-limit 2") +board_runner_args(openocd --no-halt --no-targets --no-load --target-handle _TARGETNAME_0) + +# Set hardware watchpoint limit based on SOC capabilities +if(CONFIG_SOC_SERIES_ESP32C3) + set(ESP_HW_WATCHPOINT_LIMIT 8) +elseif(CONFIG_SOC_SERIES_ESP32C6 OR CONFIG_SOC_SERIES_ESP32H2) + set(ESP_HW_WATCHPOINT_LIMIT 4) +else() + # ESP32, ESP32-S2, ESP32-S3, ESP32-C2 all have 2 watchpoints + set(ESP_HW_WATCHPOINT_LIMIT 2) +endif() +board_runner_args(openocd --gdb-init "set remote hardware-watchpoint-limit ${ESP_HW_WATCHPOINT_LIMIT}") board_runner_args(openocd --gdb-init "maintenance flush register-cache") +board_runner_args(openocd --gdb-init "mon esp appimage_offset ${CONFIG_FLASH_LOAD_OFFSET}") board_runner_args(openocd --gdb-init "mon reset halt") board_runner_args(openocd --gdb-init "thb main") +board_runner_args(openocd --file-type=bin) +board_runner_args(openocd "--flash-address=${CONFIG_FLASH_LOAD_OFFSET}") +board_runner_args(openocd --cmd-load "program_esp") +board_runner_args(openocd --cmd-verify "esp verify_bank_hash 0") + set(ESP_IDF_PATH ${ZEPHYR_HAL_ESPRESSIF_MODULE_DIR}) assert(ESP_IDF_PATH "ESP_IDF_PATH is not set") diff --git a/boards/common/xmodem1k_sender.board.cmake b/boards/common/xmodem1k_sender.board.cmake new file mode 100644 index 000000000000..26ed8368b71a --- /dev/null +++ b/boards/common/xmodem1k_sender.board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2025 Siemens Mobility GmbH +# +# SPDX-License-Identifier: Apache-2.0 + +board_set_flasher_ifnset(xmodem1k_sender) +board_finalize_runner_args(xmodem1k_sender) diff --git a/boards/croxel/croxel_cx1825/croxel_cx1825_nrf52840.dts b/boards/croxel/croxel_cx1825/croxel_cx1825_nrf52840.dts index ebcb17d6f61f..709998ba107d 100644 --- a/boards/croxel/croxel_cx1825/croxel_cx1825_nrf52840.dts +++ b/boards/croxel/croxel_cx1825/croxel_cx1825_nrf52840.dts @@ -142,12 +142,12 @@ zephyr_udc0: &usbd { boot_partition: partition@0 { label = "mcuboot"; - reg = <0x00000000 0x0000C000>; + reg = <0x00000000 0x0000c000>; }; slot0_partition: partition@c000 { label = "image-0"; - reg = <0x0000C000 0x00076000>; + reg = <0x0000c000 0x00076000>; }; slot1_partition: partition@82000 { diff --git a/boards/ct/ctcc/ctcc_nrf9161_ns.dts b/boards/ct/ctcc/ctcc_nrf9161_ns.dts index 1c23b0b8410c..f8a8e5883936 100644 --- a/boards/ct/ctcc/ctcc_nrf9161_ns.dts +++ b/boards/ct/ctcc/ctcc_nrf9161_ns.dts @@ -5,7 +5,7 @@ */ /dts-v1/; -#include +#include #include "ctcc_nrf9161_common.dtsi" / { diff --git a/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0_defconfig b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0_defconfig index d9ff32f44cc9..3f99f942388d 100644 --- a/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0_defconfig +++ b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0_defconfig @@ -9,3 +9,5 @@ CONFIG_UART_CONSOLE=y # UART driver CONFIG_SERIAL=y + +CONFIG_RUNTIME_NMI=y diff --git a/boards/cytron/index.rst b/boards/cytron/index.rst new file mode 100644 index 000000000000..b881f5d39c89 --- /dev/null +++ b/boards/cytron/index.rst @@ -0,0 +1,10 @@ +.. _boards-cytron: + +Cytron +###### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/cytron/maker_nano_rp2040/Kconfig b/boards/cytron/maker_nano_rp2040/Kconfig new file mode 100644 index 000000000000..b2243d0656a4 --- /dev/null +++ b/boards/cytron/maker_nano_rp2040/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MAKER_NANO_RP2040 + select RP2_FLASH_W25Q080 diff --git a/boards/cytron/maker_nano_rp2040/Kconfig.defconfig b/boards/cytron/maker_nano_rp2040/Kconfig.defconfig new file mode 100644 index 000000000000..1833cc939f9f --- /dev/null +++ b/boards/cytron/maker_nano_rp2040/Kconfig.defconfig @@ -0,0 +1,16 @@ +# Copyright (c) 2022 Peter Johanson +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MAKER_NANO_RP2040 + +if I2C_DW + +config I2C_DW_CLOCK_SPEED + default 125 + +endif # I2C_DW + +config USB_SELF_POWERED + default n + +endif # BOARD_MAKER_NANO_RP2040 diff --git a/boards/cytron/maker_nano_rp2040/Kconfig.maker_nano_rp2040 b/boards/cytron/maker_nano_rp2040/Kconfig.maker_nano_rp2040 new file mode 100644 index 000000000000..2143d53279c9 --- /dev/null +++ b/boards/cytron/maker_nano_rp2040/Kconfig.maker_nano_rp2040 @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MAKER_NANO_RP2040 + select SOC_RP2040 diff --git a/boards/cytron/maker_nano_rp2040/arduino_nano_connector.dtsi b/boards/cytron/maker_nano_rp2040/arduino_nano_connector.dtsi new file mode 100644 index 000000000000..02a3a02f3adf --- /dev/null +++ b/boards/cytron/maker_nano_rp2040/arduino_nano_connector.dtsi @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2022 Joylab AG + * Copyright (c) 2025 Tomas Jurena + * Copyright (c) 2025 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + arduino_header: connector { + compatible = "arduino-nano-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = , /* D0 / UART0-RX */ + , /* D1 / UART0-TX */ + , /* D2 */ + , /* D3 */ + , /* D4 */ + , /* D5 */ + , /* D6 */ + , /* D7 */ + , /* D8 */ + , /* D9 */ + , /* D10 / SPI0-CS */ + , /* D11 / SPI0-MOSI */ + , /* D12 / SPI0-MISO */ + , /* D13 / SPI0-SCK */ + , /* D14 / A0 / I2C1-SDA */ + , /* D15 / A1 / I2C1-SCL */ + , /* D16 / A2 */ + , /* D17 / A3 */ + , /* D18 / A4 / I2C0-SDA */ + , /* D19 / A5 / I2C0-SCL */ + , /* D20 / A6 */ + ; /* D21 / A7 */ + }; +}; + +arduino_nano_spi: &spi0 {}; + +arduino_nano_serial: &uart0 {}; + +arduino_nano_i2c: &i2c0 {}; diff --git a/boards/cytron/maker_nano_rp2040/board.cmake b/boards/cytron/maker_nano_rp2040/board.cmake new file mode 100644 index 000000000000..affc290a869d --- /dev/null +++ b/boards/cytron/maker_nano_rp2040/board.cmake @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2023 TOKITA Hiroshi + +board_runner_args(uf2 "--board-id=RPI-RP2") + +include(${ZEPHYR_BASE}/boards/common/uf2.board.cmake) diff --git a/boards/cytron/maker_nano_rp2040/board.yml b/boards/cytron/maker_nano_rp2040/board.yml new file mode 100644 index 000000000000..b456a2951abe --- /dev/null +++ b/boards/cytron/maker_nano_rp2040/board.yml @@ -0,0 +1,6 @@ +board: + name: maker_nano_rp2040 + full_name: Cytron Maker Nano RP2040 + vendor: cytron + socs: + - name: rp2040 diff --git a/boards/cytron/maker_nano_rp2040/doc/img/maker_nano_rp2040.webp b/boards/cytron/maker_nano_rp2040/doc/img/maker_nano_rp2040.webp new file mode 100644 index 000000000000..f45f0a7e8049 Binary files /dev/null and b/boards/cytron/maker_nano_rp2040/doc/img/maker_nano_rp2040.webp differ diff --git a/boards/cytron/maker_nano_rp2040/doc/index.rst b/boards/cytron/maker_nano_rp2040/doc/index.rst new file mode 100644 index 000000000000..90e46e051d9f --- /dev/null +++ b/boards/cytron/maker_nano_rp2040/doc/index.rst @@ -0,0 +1,212 @@ +.. zephyr:board:: maker_nano_rp2040 + +Overview +******** + +The `Cytron Maker Nano RP2040`_ board is based on the RP2040 microcontroller from Raspberry Pi Ltd. +The board has an Arduino Nano header, Maker/Qwiic/Stemma QT connectors and a mikro USB connector. + + +Hardware +******** + +- Microcontroller Raspberry Pi RP2040, with a max frequency of 133 MHz +- Dual ARM Cortex M0+ cores +- 264 kByte SRAM +- 2 Mbyte QSPI flash +- 20 GPIO pins +- 2 ADC pins +- I2C +- SPI +- UART +- Mikro USB connector +- Reset, boot and user buttons +- 2 RGB LEDs (Neopixels) +- Piezo buzzer with mute switch +- Maker/Qwiic/Stemma QT/zephyr_i2c connectors +- Status indicators for digital pins + + +Default Zephyr Peripheral Mapping +================================= + ++-------------+--------+-----------------+-------------------+ +| Label | Pin | Default pin mux | Notes | ++=============+========+=================+===================+ +| RGB LEDs | GPIO11 | PIO0 | | ++-------------+--------+-----------------+-------------------+ +| User button | GPIO20 | | Alias sw0 | ++-------------+--------+-----------------+-------------------+ +| Buzzer | GPIO22 | PWM3A | Zephyr PWM name 6 | ++-------------+--------+-----------------+-------------------+ + + +Arduino Nano header: + ++-------+--------+-----------------+-------------------+ +| Label | Pin | Default pin mux | Also in connector | ++=======+========+=================+===================+ +| 0 | GPIO0 | UART0 TX | Maker port 0 | ++-------+--------+-----------------+-------------------+ +| 1 | GPIO1 | UART0 RX | Maker port 0 | ++-------+--------+-----------------+-------------------+ +| RS | Reset | | | ++-------+--------+-----------------+-------------------+ +| G | GND | | | ++-------+--------+-----------------+-------------------+ +| 2 | GPIO2 | | (Alias led0) | ++-------+--------+-----------------+-------------------+ +| 3 | GPIO3 | | | ++-------+--------+-----------------+-------------------+ +| 4 | GPIO4 | | | ++-------+--------+-----------------+-------------------+ +| 5 | GPIO5 | | | ++-------+--------+-----------------+-------------------+ +| 6 | GPIO6 | | | ++-------+--------+-----------------+-------------------+ +| 7 | GPIO7 | | | ++-------+--------+-----------------+-------------------+ +| 8 | GPIO8 | | | ++-------+--------+-----------------+-------------------+ +| 9 | GPIO9 | | | ++-------+--------+-----------------+-------------------+ +| 17 | GPIO17 | SPI0 CS | | ++-------+--------+-----------------+-------------------+ +| 19 | GPIO19 | SPI0 MOSI | | ++-------+--------+-----------------+-------------------+ +| 16 | GPIO16 | SPI0 MISO | | ++-------+--------+-----------------+-------------------+ +| 18 | GPIO18 | SPI0 SCK | | ++-------+--------+-----------------+-------------------+ +| 3V3 | 3.3 V | | | ++-------+--------+-----------------+-------------------+ +| NC | | | | ++-------+--------+-----------------+-------------------+ +| 26 | GPIO26 | I2C1 SDA | Maker port 1 | ++-------+--------+-----------------+-------------------+ +| 27 | GPIO27 | I2C1 SCL | Maker port 1 | ++-------+--------+-----------------+-------------------+ +| 28 | GPIO28 | ADC2 | | ++-------+--------+-----------------+-------------------+ +| 29 | GPIO29 | ADC3 | | ++-------+--------+-----------------+-------------------+ +| 12 | GPIO12 | I2C0 SDA | | ++-------+--------+-----------------+-------------------+ +| 13 | GPIO13 | I2C0 SCL | | ++-------+--------+-----------------+-------------------+ +| 14 | GPIO14 | | | ++-------+--------+-----------------+-------------------+ +| 15 | GPIO15 | | | ++-------+--------+-----------------+-------------------+ +| 5V | 5 V | | | ++-------+--------+-----------------+-------------------+ +| RS | Reset | | | ++-------+--------+-----------------+-------------------+ +| G | GND | | | ++-------+--------+-----------------+-------------------+ +| VIN | Vin | | | ++-------+--------+-----------------+-------------------+ + + +Maker port 0 (pins also available in the Arduino Nano header): + ++--------+-----------------+ +| Pin | Default pin mux | ++========+=================+ +| GPIO0 | UART0 TX | ++--------+-----------------+ +| GPIO1 | UART0 RX | ++--------+-----------------+ + + +Maker port 1, also known as Qwiic/Stemma QT/zephyr_i2c. Pins also available in the Arduino +Nano header: + ++--------+-----------------+ +| Pin | Default pin mux | ++========+=================+ +| GPIO26 | I2C1 SDA | ++--------+-----------------+ +| GPIO27 | I2C1 SCL | ++--------+-----------------+ + +See also `pinout`_. + + +Supported Features +================== + +.. zephyr:board-supported-hw:: + + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +The Maker Nano RP2040 board does not expose the SWDIO and SWCLK pins, so programming must be +done via the USB port. Press and hold the BOOT button, and then press the RST button, +and the device will appear as a USB mass storage unit. +Building your application will result in a :file:`build/zephyr/zephyr.uf2` file. +Drag and drop the file to the USB mass storage unit, and the board will be reprogrammed. + +For more details on programming RP2040-based boards, see :ref:`rpi_pico_programming_and_debugging`. + + +Flashing +======== + +To run the :zephyr:code-sample:`led-strip` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/drivers/led/led_strip/ + :board: maker_nano_rp2040 + :goals: build flash + +Try also the :zephyr:code-sample:`hello_world`, :zephyr:code-sample:`blinky`, +:zephyr:code-sample:`button`, :zephyr:code-sample:`input-dump` and +:zephyr:code-sample:`adc_dt` samples. + +The use of the Maker Port 1/Qwiic/Stemma QT I2C connector is demonstrated using the +:zephyr:code-sample:`light_sensor_polling` sample and a separate shield: + +.. zephyr-app-commands:: + :zephyr-app: samples/sensor/light_polling + :board: maker_nano_rp2040 + :shield: adafruit_veml7700 + :goals: build flash + +Use the shell to control the GPIO pins: + +.. zephyr-app-commands:: + :zephyr-app: samples/sensor/sensor_shell + :board: maker_nano_rp2040 + :gen-args: -DCONFIG_GPIO=y -DCONFIG_GPIO_SHELL=y + :goals: build flash + +To set one of the GPIO pins high, use these commands in the shell, and study the indicator LEDs: + +.. code-block:: shell + + gpio conf gpio0 2 o + gpio set gpio0 2 1 + +Turn on the buzzer switch on the short side of the board. Then build using the same command +as above for the sensor_shell. Use these shell commands to turn on and off the buzzer: + +.. code-block:: shell + + pwm usec pwm@40050000 6 1000 500 + pwm usec pwm@40050000 6 1000 0 + + +References +********** + +.. target-notes:: + +.. _Cytron Maker Nano RP2040: + https://www.cytron.io/c-maker-series/p-maker-nano-rp2040-simplifying-projects-with-raspberry-pi-rp2040 + +.. _pinout: + https://docs.google.com/drawings/d/e/2PACX-1vSGwfh_1ac_UFXT4F72D0yJHaYHjDC-lfeBMLp0dc8ry57sAYtdobIFBZqrfXE6AuDTYEY9Cicto2b8/pub?w=3373&h=2867 diff --git a/boards/cytron/maker_nano_rp2040/maker_nano_rp2040-pinctrl.dtsi b/boards/cytron/maker_nano_rp2040/maker_nano_rp2040-pinctrl.dtsi new file mode 100644 index 000000000000..8574fab2b77d --- /dev/null +++ b/boards/cytron/maker_nano_rp2040/maker_nano_rp2040-pinctrl.dtsi @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2025 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + adc_default: adc_default { + group1 { + pinmux = , ; + input-enable; + }; + }; + + spi0_default: spi0_default { + group1 { + pinmux = , , ; + }; + + group2 { + pinmux = ; + input-enable; + }; + }; + + i2c0_default: i2c0_default { + group1 { + pinmux = , ; + input-enable; + }; + }; + + i2c1_default: i2c1_default { + group1 { + pinmux = , ; + input-enable; + }; + }; + + uart0_default: uart0_default { + group1 { + pinmux = ; + }; + + group2 { + pinmux = ; + input-enable; + }; + }; + + pwm_default: pwm_default { + group1 { + pinmux = ; + }; + }; + + ws2812_pio0_default: ws2812_pio0_default { + ws2812 { + pinmux = ; + }; + }; +}; diff --git a/boards/cytron/maker_nano_rp2040/maker_nano_rp2040.dts b/boards/cytron/maker_nano_rp2040/maker_nano_rp2040.dts new file mode 100644 index 000000000000..0e0dfda4ee35 --- /dev/null +++ b/boards/cytron/maker_nano_rp2040/maker_nano_rp2040.dts @@ -0,0 +1,223 @@ +/* + * Copyright (c) 2021 Yonatan Schachter + * Copyright (c) 2022 Peter Johanson + * Copyright (c) 2025 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "arduino_nano_connector.dtsi" +#include "maker_nano_rp2040-pinctrl.dtsi" + +/ { + model = "Cytron Maker Nano RP2040"; + compatible = "cytron,maker_nano_rp2040"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,flash-controller = &ssi; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,code-partition = &code_partition; + }; + + aliases { + led0 = &user_led; + led-strip = &ws2812; + sw0 = &user_button; + watchdog0 = &wdt0; + }; + + zephyr,user { + io-channels = <&adc 2>, <&adc 3>; + }; + + gpio_keys { + compatible = "gpio-keys"; + + user_button: user_button { + label = "User button"; + gpios = <&gpio0 20 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + zephyr,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + user_led: user_led { + gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; + label = "User LED"; + }; + }; + + stemma_connector: stemma_connector { + compatible = "stemma-qt-connector"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 27 0>, /* SCL */ + <1 0 &gpio0 26 0>; /* SDA */ + }; +}; + +&flash0 { + reg = <0x10000000 DT_SIZE_M(2)>; + ranges = <0x0 0x10000000 DT_SIZE_M(2)>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* Reserved memory for the second stage bootloader */ + second_stage_bootloader: partition@0 { + label = "second_stage_bootloader"; + reg = <0x00000000 0x100>; + read-only; + }; + + /* + * Usable flash. Starts at 0x100, after the bootloader. The partition + * size is 2 MB minus the 0x100 bytes taken by the bootloader. + */ + code_partition: partition@100 { + label = "code-partition"; + reg = <0x100 (DT_SIZE_M(2) - 0x100)>; + read-only; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&uart0 { + current-speed = <115200>; + status = "okay"; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&i2c0 { + status = "okay"; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + clock-frequency = ; +}; + +zephyr_i2c: &i2c1 { + status = "okay"; + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; + clock-frequency = ; +}; + +&spi0 { + pinctrl-0 = <&spi0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&timer { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&adc { + status = "okay"; + pinctrl-0 = <&adc_default>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; + + channel@1 { + reg = <1>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; + + channel@2 { + reg = <2>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; + + channel@3 { + reg = <3>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; +}; + +&pwm { + pinctrl-0 = <&pwm_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pio0 { + status = "okay"; + + pio-ws2812 { + compatible = "worldsemi,ws2812-rpi_pico-pio"; + status = "okay"; + pinctrl-0 = <&ws2812_pio0_default>; + pinctrl-names = "default"; + bit-waveform = <3>, <3>, <4>; + + ws2812: ws2812 { + status = "okay"; + gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; + chain-length = <2>; + color-mapping = ; + reset-delay = <280>; + frequency = <800000>; + }; + }; +}; + +zephyr_udc0: &usbd { + status = "okay"; +}; + +&die_temp { + status = "okay"; +}; + +&vreg { + regulator-always-on; + regulator-allowed-modes = ; +}; + +&xosc { + startup-delay-multiplier = <64>; +}; diff --git a/boards/cytron/maker_nano_rp2040/maker_nano_rp2040.yaml b/boards/cytron/maker_nano_rp2040/maker_nano_rp2040.yaml new file mode 100644 index 000000000000..28b4e271e11b --- /dev/null +++ b/boards/cytron/maker_nano_rp2040/maker_nano_rp2040.yaml @@ -0,0 +1,22 @@ +identifier: maker_nano_rp2040 +name: Cytron Maker Nano RP2040 +type: mcu +arch: arm +flash: 2048 +ram: 264 +toolchain: + - zephyr + - gnuarmemb +supported: + - adc + - clock + - counter + - dma + - flash + - gpio + - hwinfo + - i2c + - pwm + - spi + - uart + - watchdog diff --git a/boards/cytron/maker_nano_rp2040/maker_nano_rp2040_defconfig b/boards/cytron/maker_nano_rp2040/maker_nano_rp2040_defconfig new file mode 100644 index 000000000000..41b52b5618ef --- /dev/null +++ b/boards/cytron/maker_nano_rp2040/maker_nano_rp2040_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2025 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_BUILD_OUTPUT_UF2=y +CONFIG_CLOCK_CONTROL=y +CONFIG_CONSOLE=y +CONFIG_GPIO=y +CONFIG_PIO_RPI_PICO=y +CONFIG_RESET=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/cytron/maker_pi_rp2040/Kconfig b/boards/cytron/maker_pi_rp2040/Kconfig new file mode 100644 index 000000000000..57ba620750b2 --- /dev/null +++ b/boards/cytron/maker_pi_rp2040/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MAKER_PI_RP2040 + select RP2_FLASH_W25Q080 diff --git a/boards/cytron/maker_pi_rp2040/Kconfig.defconfig b/boards/cytron/maker_pi_rp2040/Kconfig.defconfig new file mode 100644 index 000000000000..e538c0388a60 --- /dev/null +++ b/boards/cytron/maker_pi_rp2040/Kconfig.defconfig @@ -0,0 +1,16 @@ +# Copyright (c) 2022 Peter Johanson +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MAKER_PI_RP2040 + +if I2C_DW + +config I2C_DW_CLOCK_SPEED + default 125 + +endif # I2C_DW + +config USB_SELF_POWERED + default n + +endif # BOARD_MAKER_PI_RP2040 diff --git a/boards/cytron/maker_pi_rp2040/Kconfig.maker_pi_rp2040 b/boards/cytron/maker_pi_rp2040/Kconfig.maker_pi_rp2040 new file mode 100644 index 000000000000..d8ff2e55b571 --- /dev/null +++ b/boards/cytron/maker_pi_rp2040/Kconfig.maker_pi_rp2040 @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MAKER_PI_RP2040 + select SOC_RP2040 diff --git a/boards/cytron/maker_pi_rp2040/board.cmake b/boards/cytron/maker_pi_rp2040/board.cmake new file mode 100644 index 000000000000..5a702fc5e030 --- /dev/null +++ b/boards/cytron/maker_pi_rp2040/board.cmake @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: Apache-2.0 +# Adapted from boards/raspberrypi/rpi_pico/board.cmake + +# This configuration allows selecting what debug adapter debugging rpi_pico +# by a command-line argument. +# It is mainly intended to support both the 'picoprobe' and 'raspberrypi-swd' +# adapter described in "Getting started with Raspberry Pi Pico". +# And any other SWD debug adapter might also be usable with this configuration. + +# Set RPI_PICO_DEBUG_ADAPTER to select debug adapter by command-line arguments. +# e.g.) west build -b rpi_pico -- -DRPI_PICO_DEBUG_ADAPTER=raspberrypi-swd +# The value is treated as a part of an interface file name that +# the debugger's configuration file. +# The value must be the 'stem' part of the name of one of the files +# in the openocd interface configuration file. +# The setting is store to CMakeCache.txt. +if("${RPI_PICO_DEBUG_ADAPTER}" STREQUAL "") + set(RPI_PICO_DEBUG_ADAPTER "cmsis-dap") +endif() + +board_runner_args(openocd --cmd-pre-init "source [find interface/${RPI_PICO_DEBUG_ADAPTER}.cfg]") +board_runner_args(openocd --cmd-pre-init "transport select swd") +board_runner_args(openocd --cmd-pre-init "source [find target/rp2040.cfg]") + +# The adapter speed is expected to be set by interface configuration. +# But if not so, set 2000 to adapter speed. +board_runner_args(openocd --cmd-pre-init "set_adapter_speed_if_not_set 2000") + +board_runner_args(jlink "--device=RP2040_M0_0") +board_runner_args(uf2 "--board-id=RPI-RP2") +board_runner_args(pyocd "--target=rp2040") + +# Default runner should be listed first +include(${ZEPHYR_BASE}/boards/common/uf2.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/blackmagicprobe.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/cytron/maker_pi_rp2040/board.yml b/boards/cytron/maker_pi_rp2040/board.yml new file mode 100644 index 000000000000..30861061a71a --- /dev/null +++ b/boards/cytron/maker_pi_rp2040/board.yml @@ -0,0 +1,6 @@ +board: + name: maker_pi_rp2040 + full_name: Cytron Maker Pi RP2040 + vendor: cytron + socs: + - name: rp2040 diff --git a/boards/cytron/maker_pi_rp2040/doc/img/maker_pi_rp2040.webp b/boards/cytron/maker_pi_rp2040/doc/img/maker_pi_rp2040.webp new file mode 100644 index 000000000000..b97c43ed72ae Binary files /dev/null and b/boards/cytron/maker_pi_rp2040/doc/img/maker_pi_rp2040.webp differ diff --git a/boards/cytron/maker_pi_rp2040/doc/index.rst b/boards/cytron/maker_pi_rp2040/doc/index.rst new file mode 100644 index 000000000000..ae9089f3d593 --- /dev/null +++ b/boards/cytron/maker_pi_rp2040/doc/index.rst @@ -0,0 +1,283 @@ +.. zephyr:board:: maker_pi_rp2040 + +Overview +******** + +The `Cytron Maker Pi RP2040`_ board is based on the RP2040 microcontroller from Raspberry Pi Ltd. +The board has motor drivers, servo headers, Grove connectors and a micro USB connector. + + +Hardware +******** + +- Microcontroller Raspberry Pi RP2040, with a max frequency of 133 MHz +- Dual ARM Cortex M0+ cores +- 264 kByte SRAM +- 2 Mbyte QSPI flash +- 17 GPIO pins +- 3 ADC pins +- Supply voltage measurement +- I2C +- UART +- Micro USB connector +- LiPo charger +- Reset, boot and 2 user buttons +- 2 RGB LEDs (Neopixels) +- Piezo buzzer with mute switch +- 4 servo ports +- 2 Motor drivers, with 4 manual test bottons +- 7 Grove connectors, of which one can be used as a Maker/Qwiic/Stemma QT/zephyr_i2c connector +- 13 status indicators for digital pins + + +Default Zephyr Peripheral Mapping +================================= + ++---------------+--------+-----------------------+-----------------+ +| Description | Pin | Default pin mux | Zephyr PWM name | ++===============+========+=======================+=================+ +| RGB LEDs | GPIO18 | PIO0 | | ++---------------+--------+-----------------------+-----------------+ +| Buzzer | GPIO22 | PWM3A | 6 | ++---------------+--------+-----------------------+-----------------+ +| Button 1 | GPIO20 | (Alias sw0) | | ++---------------+--------+-----------------------+-----------------+ +| Button 2 | GPIO21 | (Alias sw1) | | ++---------------+--------+-----------------------+-----------------+ +| Voltage sense | GPIO29 | ADC3, voltage divider | | ++---------------+--------+-----------------------+-----------------+ + +Servo header: + ++-------+--------+-----------------+-----------------+ +| Label | Pin | Default pin mux | Zephyr PWM name | ++=======+========+=================+=================+ +| GP12 | GPIO12 | PWM6A | 12 | ++-------+--------+-----------------+-----------------+ +| GP13 | GPIO13 | PWM6B | 13 | ++-------+--------+-----------------+-----------------+ +| GP14 | GPIO14 | PWM7A | 14 | ++-------+--------+-----------------+-----------------+ +| GP15 | GPIO15 | PWM7B | 15 | ++-------+--------+-----------------+-----------------+ + +Motor drivers: + ++-------+--------+-----------------+-----------------+ +| Label | Pin | Default pin mux | Zephyr PWM name | ++=======+========+=================+=================+ +| M1A | GPIO8 | PWM4A | 8 | ++-------+--------+-----------------+-----------------+ +| M1B | GPIO9 | PWM4B | 9 | ++-------+--------+-----------------+-----------------+ +| M2A | GPIO10 | PWM5A | 10 | ++-------+--------+-----------------+-----------------+ +| M2B | GPIO11 | PWM5B | 11 | ++-------+--------+-----------------+-----------------+ + +Grove connector 1: + ++-------+--------+-----------------+ +| Label | Pin | Default pin mux | ++=======+========+=================+ +| GP0 | GPIO0 | UART0 TX | ++-------+--------+-----------------+ +| GP1 | GPIO1 | UART0 RX | ++-------+--------+-----------------+ + +Grove connector 2: + +Use an adapter cable to connect Qwiic/Stemma QT sensors (that use I2C) to this connector, which +is mapped to the ``zephyr_i2c`` devicetree node label. + ++-------+--------+-----------------+ +| Label | Pin | Default pin mux | ++=======+========+=================+ +| GP2 | GPIO2 | I2C1 SDA | ++-------+--------+-----------------+ +| GP3 | GPIO3 | I2C1 SCL | ++-------+--------+-----------------+ + +Grove connector 3: + ++-------+--------+------------+ +| Label | Pin | Notes | ++=======+========+============+ +| GP4 | GPIO4 | Alias led0 | ++-------+--------+------------+ +| GP5 | GPIO5 | Alias led1 | ++-------+--------+------------+ + +Grove connector 4: + ++-------+--------+ +| Label | Pin | ++=======+========+ +| GP16 | GPIO16 | ++-------+--------+ +| GP17 | GPIO17 | ++-------+--------+ + +Grove connector 5: + ++-------+--------+-----------------+-----------------+ +| Label | Pin | Default pin mux | Notes | ++=======+========+=================+=================+ +| GP6 | GPIO6 | | | ++-------+--------+-----------------+-----------------+ +| GP26 | GPIO26 | ADC0 | Also in Grove 6 | ++-------+--------+-----------------+-----------------+ + +Grove connector 6: + ++-------+--------+-----------------+-----------------+ +| Label | Pin | Default pin mux | Notes | ++=======+========+=================+=================+ +| GP26 | GPIO26 | ADC0 | Also in Grove 5 | ++-------+--------+-----------------+-----------------+ +| GP27 | GPIO27 | ADC1 | | ++-------+--------+-----------------+-----------------+ + +Grove connector 7: + ++-------+--------+-----------------+ +| Label | Pin | Default pin mux | ++=======+========+=================+ +| GP7 | GPIO7 | | ++-------+--------+-----------------+ +| GP28 | GPIO28 | ADC2 | ++-------+--------+-----------------+ + +See also `schematic`_. + + +Supported Features +================== + +.. zephyr:board-supported-hw:: + + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +By default programming is done via the USB connector. Press and hold the BOOT button, and then +press the RST button, and the device will appear as a USB mass storage unit. +Building your application will result in a :file:`build/zephyr/zephyr.uf2` file. +Drag and drop the file to the USB mass storage unit, and the board will be reprogrammed. + +It is also possible to program and debug the board via the SWDIO and SWCLK pins in the DEBUG +connector. You must solder a 3-pin header to the board in order to use this feature. +A separate programming hardware tool is required, and for example the :command:`openocd` software +is used. Typically the ``OPENOCD`` and ``OPENOCD_DEFAULT_PATH`` values should be set when +building, and the ``--runner openocd`` argument should be used when flashing. +For more details on programming RP2040-based boards, see :ref:`rpi_pico_programming_and_debugging`. + + +Flashing +======== + +To run the :zephyr:code-sample:`blinky` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky/ + :board: maker_pi_rp2040 + :goals: build flash + +Try also the :zephyr:code-sample:`led-strip`, :zephyr:code-sample:`hello_world`, +:zephyr:code-sample:`button`, :zephyr:code-sample:`input-dump` and +:zephyr:code-sample:`adc_dt` samples. + +The use of the Maker/Qwiic/Stemma QT I2C connector (Grove 2) is demonstrated using the +:zephyr:code-sample:`light_sensor_polling` sample and a separate shield: + +.. zephyr-app-commands:: + :zephyr-app: samples/sensor/light_polling + :board: maker_pi_rp2040 + :shield: adafruit_veml7700 + :goals: build flash + +Use the shell to control the GPIO pins: + +.. zephyr-app-commands:: + :zephyr-app: samples/sensor/sensor_shell + :board: maker_pi_rp2040 + :gen-args: -DCONFIG_GPIO=y -DCONFIG_GPIO_SHELL=y + :goals: build flash + +To set one of the GPIO pins high, use these commands in the shell, and study the indicator LEDs: + +.. code-block:: shell + + gpio conf gpio0 16 o + gpio set gpio0 16 1 + +Servo motor control is done via PWM outputs. The :zephyr:code-sample:`servo-motor` +sample sets servo position timing (via an overlay file) for the output GP12: + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/servo_motor/ + :board: maker_pi_rp2040 + :goals: build flash + +It is also possible to control servos via the pwm shell: + +.. zephyr-app-commands:: + :zephyr-app: samples/sensor/sensor_shell + :board: maker_pi_rp2040 + :gen-args: -DCONFIG_PWM=y -DCONFIG_PWM_SHELL=y + :goals: build flash + +Use shell commands to set the position of the servo. Most servo motors can handle pulse +times between 800 and 2000 microseconds: + +.. code-block:: shell + + pwm usec pwm@40050000 12 20000 800 + pwm usec pwm@40050000 12 20000 2000 + +To use the buzzer, you must turn on the buzzer switch on the short side of the board. +Then build using the same command as above for the sensor_shell. +Use these shell commands to turn on and off the buzzer: + +.. code-block:: shell + + pwm usec pwm@40050000 6 1000 500 + pwm usec pwm@40050000 6 1000 0 + +You can also control the motor outputs via the shell. To set the speed of motor 1 to +100%, 50%, 20% and 0% respectively, use these commands: + +.. code-block:: shell + + pwm usec pwm@40050000 8 1000 1000 + pwm usec pwm@40050000 8 1000 500 + pwm usec pwm@40050000 8 1000 200 + pwm usec pwm@40050000 8 1000 0 + +To run the motor in the opposite direction at 80%: + +.. code-block:: shell + + pwm usec pwm@40050000 9 1000 800 + +The sensor_shell sample is used also to measure the supply voltage. This is the result when +running on a Vin voltage slightly less than 6 Volt: + +.. code-block:: shell + + sensor get vbatt + channel type=33(voltage) index=0 shift=3 num_samples=1 value=32688380776ns (5.977999) + + +References +********** + +.. target-notes:: + +.. _Cytron Maker Pi RP2040: + https://www.cytron.io/p-maker-pi-rp2040-simplifying-robotics-with-raspberry-pi-rp2040 + +.. _schematic: + https://drive.google.com/file/d/1BNqbxXScMXnL3-2YYfbR66nFCD1li71X/view diff --git a/boards/cytron/maker_pi_rp2040/grove_connectors.dtsi b/boards/cytron/maker_pi_rp2040/grove_connectors.dtsi new file mode 100644 index 000000000000..dbc5d9808468 --- /dev/null +++ b/boards/cytron/maker_pi_rp2040/grove_connectors.dtsi @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2026 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + grove_header1: grove_header1 { + compatible = "grove-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 1 0>, /* RX */ + <1 0 &gpio0 0 0>; /* TX */ + }; + + grove_header2: grove_header2 { + compatible = "grove-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 3 0>, /* SCL */ + <1 0 &gpio0 2 0>; /* SDA */ + }; + + grove_header3: grove_header3 { + compatible = "grove-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 5 0>, + <1 0 &gpio0 4 0>; + }; + + grove_header4: grove_header4 { + compatible = "grove-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 17 0>, + <1 0 &gpio0 16 0>; + }; + + grove_header5: grove_header5 { + compatible = "grove-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 26 0>, /* ADC0 */ + <1 0 &gpio0 6 0>; + }; + + grove_header6: grove_header6 { + compatible = "grove-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 27 0>, /* ADC1 */ + <1 0 &gpio0 26 0>; /* ADC0 */ + }; + + grove_header7: grove_header7 { + compatible = "grove-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 28 0>, /* ADC2 */ + <1 0 &gpio0 7 0>; + }; +}; diff --git a/boards/cytron/maker_pi_rp2040/maker_pi_rp2040-pinctrl.dtsi b/boards/cytron/maker_pi_rp2040/maker_pi_rp2040-pinctrl.dtsi new file mode 100644 index 000000000000..568e1f67521a --- /dev/null +++ b/boards/cytron/maker_pi_rp2040/maker_pi_rp2040-pinctrl.dtsi @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2025 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + adc_default: adc_default { + group1 { + pinmux = , , , ; + input-enable; + }; + }; + + i2c1_default: i2c1_default { + group1 { + pinmux = , ; + input-enable; + }; + }; + + uart0_default: uart0_default { + group1 { + pinmux = ; + }; + + group2 { + pinmux = ; + input-enable; + }; + }; + + pwm_default: pwm_default { + group1 { + pinmux = , , , , + , , , , + ; + }; + }; + + ws2812_pio0_default: ws2812_pio0_default { + ws2812 { + pinmux = ; + }; + }; +}; diff --git a/boards/cytron/maker_pi_rp2040/maker_pi_rp2040.dts b/boards/cytron/maker_pi_rp2040/maker_pi_rp2040.dts new file mode 100644 index 000000000000..010a57ea20ca --- /dev/null +++ b/boards/cytron/maker_pi_rp2040/maker_pi_rp2040.dts @@ -0,0 +1,221 @@ +/* + * Copyright (c) 2021 Yonatan Schachter + * Copyright (c) 2022 Peter Johanson + * Copyright (c) 2025 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "maker_pi_rp2040-pinctrl.dtsi" +#include "grove_connectors.dtsi" + +/ { + model = "Cytron Maker Pi RP2040"; + compatible = "cytron,maker_pi_rp2040"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,flash-controller = &ssi; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,code-partition = &code_partition; + }; + + aliases { + led-strip = &ws2812; + led0 = &led_gp4; + led1 = &led_gp5; + sw0 = &button_gp20; + sw1 = &button_gp21; + watchdog0 = &wdt0; + }; + + zephyr,user { + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>; + }; + + vbatt: vbatt { + compatible = "voltage-divider"; + io-channels = <&adc 3>; + output-ohms = <10000>; + full-ohms = <(10000 + 10000)>; + }; + + gpio_keys { + compatible = "gpio-keys"; + + button_gp20: button_gp20 { + label = "Button GP20"; + gpios = <&gpio0 20 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + zephyr,code = ; + }; + + button_gp21: button_gp21 { + label = "Button GP21"; + gpios = <&gpio0 21 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + zephyr,code = ; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + + led_gp4: led_gp4 { + gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; + label = "LED GP4"; + }; + + led_gp5: led_gp5 { + gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; + label = "LED GP5"; + }; + }; +}; + +&flash0 { + reg = <0x10000000 DT_SIZE_M(2)>; + ranges = <0x0 0x10000000 DT_SIZE_M(2)>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* Reserved memory for the second stage bootloader */ + second_stage_bootloader: partition@0 { + label = "second_stage_bootloader"; + reg = <0x00000000 0x100>; + read-only; + }; + + /* + * Usable flash. Starts at 0x100, after the bootloader. The partition + * size is 2 MB minus the 0x100 bytes taken by the bootloader. + */ + code_partition: partition@100 { + label = "code-partition"; + reg = <0x100 (DT_SIZE_M(2) - 0x100)>; + read-only; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&uart0 { + current-speed = <115200>; + status = "okay"; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +zephyr_i2c: &i2c1 { + status = "okay"; + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; + clock-frequency = ; +}; + +&timer { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&adc { + status = "okay"; + pinctrl-0 = <&adc_default>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; + + channel@1 { + reg = <1>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; + + channel@2 { + reg = <2>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; + + channel@3 { + reg = <3>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; +}; + +&pwm { + pinctrl-0 = <&pwm_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pio0 { + status = "okay"; + + pio-ws2812 { + compatible = "worldsemi,ws2812-rpi_pico-pio"; + status = "okay"; + pinctrl-0 = <&ws2812_pio0_default>; + pinctrl-names = "default"; + bit-waveform = <3>, <3>, <4>; + + ws2812: ws2812 { + status = "okay"; + gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; + chain-length = <2>; + color-mapping = ; + reset-delay = <280>; + frequency = <800000>; + }; + }; +}; + +zephyr_udc0: &usbd { + status = "okay"; +}; + +&die_temp { + status = "okay"; +}; + +&vreg { + regulator-always-on; + regulator-allowed-modes = ; +}; + +&xosc { + startup-delay-multiplier = <64>; +}; diff --git a/boards/cytron/maker_pi_rp2040/maker_pi_rp2040.yaml b/boards/cytron/maker_pi_rp2040/maker_pi_rp2040.yaml new file mode 100644 index 000000000000..91881a9a9be1 --- /dev/null +++ b/boards/cytron/maker_pi_rp2040/maker_pi_rp2040.yaml @@ -0,0 +1,21 @@ +identifier: maker_pi_rp2040 +name: Cytron Maker Pi RP2040 +type: mcu +arch: arm +flash: 2048 +ram: 264 +toolchain: + - zephyr + - gnuarmemb +supported: + - adc + - clock + - counter + - dma + - flash + - gpio + - hwinfo + - i2c + - pwm + - uart + - watchdog diff --git a/boards/cytron/maker_pi_rp2040/maker_pi_rp2040_defconfig b/boards/cytron/maker_pi_rp2040/maker_pi_rp2040_defconfig new file mode 100644 index 000000000000..40aec62529fa --- /dev/null +++ b/boards/cytron/maker_pi_rp2040/maker_pi_rp2040_defconfig @@ -0,0 +1,14 @@ +# Copyright (c) 2025 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_OUTPUT_UF2=y +CONFIG_CLOCK_CONTROL=y +CONFIG_CONSOLE=y +CONFIG_GPIO=y +CONFIG_PIO_RPI_PICO=y +CONFIG_RESET=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/cytron/maker_pi_rp2040/support/openocd.cfg b/boards/cytron/maker_pi_rp2040/support/openocd.cfg new file mode 100644 index 000000000000..34ab592b1861 --- /dev/null +++ b/boards/cytron/maker_pi_rp2040/support/openocd.cfg @@ -0,0 +1,11 @@ +# Copyright (c) 2022 Tokita, Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +# Checking and set 'adapter speed'. +# Set the adaptor speed, if unset, and given as an argument. +proc set_adapter_speed_if_not_set { speed } { + puts "checking adapter speed..." + if { [catch {adapter speed} ret] } { + adapter speed $speed + } +} diff --git a/boards/cytron/maker_uno_rp2040/Kconfig b/boards/cytron/maker_uno_rp2040/Kconfig new file mode 100644 index 000000000000..e8659306ae73 --- /dev/null +++ b/boards/cytron/maker_uno_rp2040/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MAKER_UNO_RP2040 + select RP2_FLASH_W25Q080 diff --git a/boards/cytron/maker_uno_rp2040/Kconfig.defconfig b/boards/cytron/maker_uno_rp2040/Kconfig.defconfig new file mode 100644 index 000000000000..f8af362b30f8 --- /dev/null +++ b/boards/cytron/maker_uno_rp2040/Kconfig.defconfig @@ -0,0 +1,16 @@ +# Copyright (c) 2022 Peter Johanson +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MAKER_UNO_RP2040 + +if I2C_DW + +config I2C_DW_CLOCK_SPEED + default 125 + +endif # I2C_DW + +config USB_SELF_POWERED + default n + +endif # BOARD_MAKER_UNO_RP2040 diff --git a/boards/cytron/maker_uno_rp2040/Kconfig.maker_uno_rp2040 b/boards/cytron/maker_uno_rp2040/Kconfig.maker_uno_rp2040 new file mode 100644 index 000000000000..d0b3857ac396 --- /dev/null +++ b/boards/cytron/maker_uno_rp2040/Kconfig.maker_uno_rp2040 @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MAKER_UNO_RP2040 + select SOC_RP2040 diff --git a/boards/cytron/maker_uno_rp2040/arduino_r3_connector.dtsi b/boards/cytron/maker_uno_rp2040/arduino_r3_connector.dtsi new file mode 100644 index 000000000000..0aae26417c22 --- /dev/null +++ b/boards/cytron/maker_uno_rp2040/arduino_r3_connector.dtsi @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2025 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + arduino_header: connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 26 0>, /* A0 */ + <1 0 &gpio0 27 0>, /* A1 */ + <2 0 &gpio0 28 0>, /* A2 */ + <3 0 &gpio0 29 0>, /* A3 */ + <4 0 &gpio0 20 0>, /* SDA */ + <5 0 &gpio0 21 0>, /* SCL */ + <6 0 &gpio0 1 0>, /* GP1 */ + <7 0 &gpio0 0 0>, /* GP0 */ + <8 0 &gpio0 2 0>, /* GP2 */ + <9 0 &gpio0 3 0>, /* GP3 */ + <10 0 &gpio0 4 0>, /* GP4 */ + <11 0 &gpio0 5 0>, /* GP5 */ + <12 0 &gpio0 6 0>, /* GP6 */ + <13 0 &gpio0 7 0>, /* GP7 */ + <14 0 &gpio0 8 0>, /* GP8 */ + <15 0 &gpio0 9 0>, /* GP9 */ + <16 0 &gpio0 13 0>, /* GP13 */ + <17 0 &gpio0 11 0>, /* GP11 */ + <18 0 &gpio0 12 0>, /* GP12 */ + <19 0 &gpio0 10 0>, /* GP10 */ + <20 0 &gpio0 20 0>, /* GP20 */ + <21 0 &gpio0 21 0>; /* GP21 */ + }; +}; + +arduino_i2c: &i2c0 {}; + +arduino_serial: &uart0 {}; + +arduino_spi: &spi1 {}; diff --git a/boards/cytron/maker_uno_rp2040/board.cmake b/boards/cytron/maker_uno_rp2040/board.cmake new file mode 100644 index 000000000000..affc290a869d --- /dev/null +++ b/boards/cytron/maker_uno_rp2040/board.cmake @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2023 TOKITA Hiroshi + +board_runner_args(uf2 "--board-id=RPI-RP2") + +include(${ZEPHYR_BASE}/boards/common/uf2.board.cmake) diff --git a/boards/cytron/maker_uno_rp2040/board.yml b/boards/cytron/maker_uno_rp2040/board.yml new file mode 100644 index 000000000000..453f93f47d84 --- /dev/null +++ b/boards/cytron/maker_uno_rp2040/board.yml @@ -0,0 +1,6 @@ +board: + name: maker_uno_rp2040 + full_name: Cytron Maker Uno RP2040 + vendor: cytron + socs: + - name: rp2040 diff --git a/boards/cytron/maker_uno_rp2040/doc/img/maker_uno_rp2040.webp b/boards/cytron/maker_uno_rp2040/doc/img/maker_uno_rp2040.webp new file mode 100644 index 000000000000..95e49c5b1b61 Binary files /dev/null and b/boards/cytron/maker_uno_rp2040/doc/img/maker_uno_rp2040.webp differ diff --git a/boards/cytron/maker_uno_rp2040/doc/index.rst b/boards/cytron/maker_uno_rp2040/doc/index.rst new file mode 100644 index 000000000000..de35f6efee5c --- /dev/null +++ b/boards/cytron/maker_uno_rp2040/doc/index.rst @@ -0,0 +1,293 @@ +.. zephyr:board:: maker_uno_rp2040 + +Overview +******** + +The `Cytron Maker Uno RP2040`_ board is based on the RP2040 microcontroller from Raspberry Pi Ltd. +The board has an Arduino header, several Grove connectors and a USB type C connector. + + +Hardware +******** + +- Microcontroller Raspberry Pi RP2040, with a max frequency of 133 MHz +- Dual ARM Cortex M0+ cores +- 264 kByte SRAM +- 2 Mbyte QSPI flash +- 16 GPIO pins +- 4 ADC pins +- I2C +- SPI +- UART +- USB type C connector +- LiPo charger +- Reset, boot and user buttons +- 2 RGB LEDs (Neopixels) +- Piezo buzzer with mute switch +- 4 servo ports +- Maker/Qwiic/Stemma QT/zephyr_i2c connector +- 6 Grove connectors +- Status indicators for digital pins + + +Default Zephyr Peripheral Mapping +================================= + +The RGB LEDs are connected to GPIO25, and its pin mux setting is PIO0. + +Arduino headers (note that GPIO20 and GPIO21 appear twice): + ++-------+--------+-----------------+-------------------+ +| Label | Pin | Default pin mux | Also in connector | ++=======+========+=================+===================+ +| A0 | GPIO26 | ADC0 | Grove 3 | ++-------+--------+-----------------+-------------------+ +| A1 | GPIO27 | ADC1 | Grove 4 | ++-------+--------+-----------------+-------------------+ +| A2 | GPIO28 | ADC2 | Grove 5 | ++-------+--------+-----------------+-------------------+ +| A3 | GPIO29 | ADC3 | Grove 5 | ++-------+--------+-----------------+-------------------+ +| SDA | GPIO20 | I2C0 SDA | Grove 6, Maker | ++-------+--------+-----------------+-------------------+ +| SCL | GPIO21 | I2C0 SCL | Grove 6, Maker | ++-------+--------+-----------------+-------------------+ +| GP1 | GPIO1 | UART0 RX | Grove 1 | ++-------+--------+-----------------+-------------------+ +| GP0 | GPIO0 | UART0 TX | Grove 1 | ++-------+--------+-----------------+-------------------+ +| GP2 | GPIO2 | GPIO pull-up | User button | ++-------+--------+-----------------+-------------------+ +| GP3 | GPIO3 | (Alias led0) | | ++-------+--------+-----------------+-------------------+ +| GP4 | GPIO4 | | Grove 2 | ++-------+--------+-----------------+-------------------+ +| GP5 | GPIO5 | | Grove 2 | ++-------+--------+-----------------+-------------------+ +| GP6 | GPIO6 | | Grove 3 | ++-------+--------+-----------------+-------------------+ +| GP7 | GPIO7 | | Grove 4 | ++-------+--------+-----------------+-------------------+ +| GP8 | GPIO8 | | Buzzer | ++-------+--------+-----------------+-------------------+ +| GP9 | GPIO9 | | | ++-------+--------+-----------------+-------------------+ +| GP13 | GPIO13 | SPI1 CS | | ++-------+--------+-----------------+-------------------+ +| GP11 | GPIO11 | SPI1 MOSI | SPI header | ++-------+--------+-----------------+-------------------+ +| GP12 | GPIO12 | SPI1 MISO | SPI header | ++-------+--------+-----------------+-------------------+ +| GP10 | GPIO10 | SPI1 SCK | SPI header | ++-------+--------+-----------------+-------------------+ +| GP20 | GPIO20 | I2C0 SDA | Grove 6, Maker | ++-------+--------+-----------------+-------------------+ +| GP21 | GPIO21 | I2C0 SCL | Grove 6, Maker | ++-------+--------+-----------------+-------------------+ + +SPI 6-pin header (pins also available in the Arduino header): + ++-------+--------+-----------------+ +| Label | Pin | Default pin mux | ++=======+========+=================+ +| GP10 | GPIO10 | SPI1 SCK | ++-------+--------+-----------------+ +| GP11 | GPIO11 | SPI1 MOSI | ++-------+--------+-----------------+ +| GP12 | GPIO12 | SPI1 MISO | ++-------+--------+-----------------+ + +Servo header: + ++-------+--------+-----------------+-----------------+ +| Label | Pin | Default pin mux | Zephyr PWM name | ++=======+========+=================+=================+ +| GP14 | GPIO14 | PWM7A | 14 | ++-------+--------+-----------------+-----------------+ +| GP15 | GPIO15 | PWM7B | 15 | ++-------+--------+-----------------+-----------------+ +| GP16 | GPIO16 | PWM0A | 0 | ++-------+--------+-----------------+-----------------+ +| GP17 | GPIO17 | PWM0B | 1 | ++-------+--------+-----------------+-----------------+ + +Grove connector 1 (pins also available in the Arduino header): + ++-------+--------+-----------------+ +| Label | Pin | Default pin mux | ++=======+========+=================+ +| GP1 | GPIO1 | UART0 RX | ++-------+--------+-----------------+ +| GP0 | GPIO0 | UART0 TX | ++-------+--------+-----------------+ + +Grove connector 2 (pins also available in the Arduino header): + ++-------+--------+ +| Label | Pin | ++=======+========+ +| GP4 | GPIO4 | ++-------+--------+ +| GP5 | GPIO5 | ++-------+--------+ + +Grove connector 3 (pins also available in the Arduino header): + ++-------+--------+-----------------+ +| Label | Pin | Default pin mux | ++=======+========+=================+ +| GP6 | GPIO6 | | ++-------+--------+-----------------+ +| A0 | GPIO26 | ADC0 | ++-------+--------+-----------------+ + +Grove connector 4 (pins also available in the Arduino header): + ++-------+--------+-----------------+ +| Label | Pin | Default pin mux | ++=======+========+=================+ +| GP7 | GPIO7 | | ++-------+--------+-----------------+ +| A1 | GPIO27 | ADC1 | ++-------+--------+-----------------+ + +Grove connector 5 (pins also available in the Arduino header): + ++-------+--------+-----------------+ +| Label | Pin | Default pin mux | ++=======+========+=================+ +| A2 | GPIO28 | ADC2 | ++-------+--------+-----------------+ +| A3 | GPIO29 | ADC3 | ++-------+--------+-----------------+ + +Grove connector 6 (pins also available in the Maker connector and Arduino header): + ++-------+--------+-----------------+ +| Label | Pin | Default pin mux | ++=======+========+=================+ +| GP20 | GPIO20 | I2C0 SDA | ++-------+--------+-----------------+ +| GP21 | GPIO21 | I2C0 SCL | ++-------+--------+-----------------+ + +Maker connector, also known as Qwiic/Stemma QT/zephyr_i2c. The pins are also +available in Grove 6 and the Arduino header: + ++-------+--------+-----------------+ +| Label | Pin | Default pin mux | ++=======+========+=================+ +| GP20 | GPIO20 | I2C0 SDA | ++-------+--------+-----------------+ +| GP21 | GPIO21 | I2C0 SCL | ++-------+--------+-----------------+ + +See also `schematic`_. + + +Supported Features +================== + +.. zephyr:board-supported-hw:: + + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +The Maker Uno RP2040 board does not expose the SWDIO and SWCLK pins, so programming must be +done via the USB port. Press and hold the BOOT button, and then press the RST button, +and the device will appear as a USB mass storage unit. +Building your application will result in a :file:`build/zephyr/zephyr.uf2` file. +Drag and drop the file to the USB mass storage unit, and the board will be reprogrammed. + +For more details on programming RP2040-based boards, see :ref:`rpi_pico_programming_and_debugging`. + + +Flashing +======== + +To run the :zephyr:code-sample:`led-strip` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/drivers/led/led_strip/ + :board: maker_uno_rp2040 + :goals: build flash + +Try also the :zephyr:code-sample:`hello_world`, :zephyr:code-sample:`blinky`, +:zephyr:code-sample:`button`, :zephyr:code-sample:`input-dump` and +:zephyr:code-sample:`adc_dt` samples. + +The use of the Maker/Qwiic/Stemma QT I2C connector is demonstrated using the +:zephyr:code-sample:`light_sensor_polling` sample and a separate shield: + +.. zephyr-app-commands:: + :zephyr-app: samples/sensor/light_polling + :board: maker_uno_rp2040 + :shield: adafruit_veml7700 + :goals: build flash + +Use the shell to control the GPIO pins: + +.. zephyr-app-commands:: + :zephyr-app: samples/sensor/sensor_shell + :board: maker_uno_rp2040 + :gen-args: -DCONFIG_GPIO=y -DCONFIG_GPIO_SHELL=y + :goals: build flash + +To set one of the GPIO pins high, use these commands in the shell, and study the indicator LEDs: + +.. code-block:: shell + + gpio conf gpio0 2 o + gpio set gpio0 2 1 + +Servo motor control is done via PWM outputs. The :zephyr:code-sample:`servo-motor` +sample sets servo position timing (via an overlay file) for the output GP14: + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/servo_motor/ + :board: maker_uno_rp2040 + :goals: build flash + +It is also possible to control servos via the pwm shell: + +.. zephyr-app-commands:: + :zephyr-app: samples/sensor/sensor_shell + :board: maker_uno_rp2040 + :gen-args: -DCONFIG_PWM=y -DCONFIG_PWM_SHELL=y + :goals: build flash + +Use shell commands to set the posiotion of the server. Most servo motor can handle pulse +times between 800 and 2000 microseconds: + +.. code-block:: shell + + pwm usec pwm@40050000 14 20000 800 + pwm usec pwm@40050000 14 20000 2000 + +To use the buzzer, you must set the pin mux for GPIO8 to PWM. This is done by adding ``PWM_4A_P8`` +to the ``pwm_default`` section in the +:zephyr_file:`boards/cytron/maker_uno_rp2040/maker_uno_rp2040-pinctrl.dtsi` file. +Turn on the buzzer switch on the long side of the board. Then build using the same command +as above for the sensor_shell. + +Use these shell commands to turn on and off the buzzer: + +.. code-block:: shell + + pwm usec pwm@40050000 8 1000 500 + pwm usec pwm@40050000 8 1000 0 + + +References +********** + +.. target-notes:: + +.. _Cytron Maker Uno RP2040: + https://www.cytron.io/p-maker-uno-rp2040 + +.. _schematic: + https://drive.google.com/file/d/1BNqbxXScMXnL3-2YYfbR66nFCD1li71X/view diff --git a/boards/cytron/maker_uno_rp2040/grove_connectors.dtsi b/boards/cytron/maker_uno_rp2040/grove_connectors.dtsi new file mode 100644 index 000000000000..6b2302851486 --- /dev/null +++ b/boards/cytron/maker_uno_rp2040/grove_connectors.dtsi @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2026 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + grove_header1: grove_header1 { + compatible = "grove-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 1 0>, /* RX */ + <1 0 &gpio0 0 0>; /* TX */ + }; + + grove_header2: grove_header2 { + compatible = "grove-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 5 0>, + <1 0 &gpio0 4 0>; + }; + + grove_header3: grove_header3 { + compatible = "grove-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 26 0>, /* ADC0 */ + <1 0 &gpio0 6 0>; + }; + + grove_header4: grove_header4 { + compatible = "grove-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 27 0>, /* ADC1 */ + <1 0 &gpio0 7 0>; + }; + + grove_header5: grove_header5 { + compatible = "grove-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 29 0>, /* ADC3 */ + <1 0 &gpio0 28 0>; /* ADC2 */ + }; + + grove_header6: grove_header6 { + compatible = "grove-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 21 0>, /* SCL */ + <1 0 &gpio0 20 0>; /* SDA */ + }; + + stemma_connector: stemma_connector { + compatible = "stemma-qt-connector"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 21 0>, /* SCL */ + <1 0 &gpio0 20 0>; /* SDA */ + }; +}; diff --git a/boards/cytron/maker_uno_rp2040/maker_uno_rp2040-pinctrl.dtsi b/boards/cytron/maker_uno_rp2040/maker_uno_rp2040-pinctrl.dtsi new file mode 100644 index 000000000000..952623281cf7 --- /dev/null +++ b/boards/cytron/maker_uno_rp2040/maker_uno_rp2040-pinctrl.dtsi @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2025 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + adc_default: adc_default { + group1 { + pinmux = , , , ; + input-enable; + }; + }; + + spi1_default: spi1_default { + group1 { + pinmux = , , ; + }; + + group2 { + pinmux = ; + input-enable; + }; + }; + + i2c0_default: i2c0_default { + group1 { + pinmux = , ; + input-enable; + }; + }; + + uart0_default: uart0_default { + group1 { + pinmux = ; + }; + + group2 { + pinmux = ; + input-enable; + }; + }; + + pwm_default: pwm_default { + group1 { + pinmux = , , , ; + }; + }; + + ws2812_pio0_default: ws2812_pio0_default { + ws2812 { + pinmux = ; + }; + }; +}; diff --git a/boards/cytron/maker_uno_rp2040/maker_uno_rp2040.dts b/boards/cytron/maker_uno_rp2040/maker_uno_rp2040.dts new file mode 100644 index 000000000000..5ca6466a242c --- /dev/null +++ b/boards/cytron/maker_uno_rp2040/maker_uno_rp2040.dts @@ -0,0 +1,208 @@ +/* + * Copyright (c) 2021 Yonatan Schachter + * Copyright (c) 2022 Peter Johanson + * Copyright (c) 2025 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "arduino_r3_connector.dtsi" +#include "grove_connectors.dtsi" +#include "maker_uno_rp2040-pinctrl.dtsi" + +/ { + model = "Cytron Maker Uno RP2040"; + compatible = "cytron,maker_uno_rp2040"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,flash-controller = &ssi; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,code-partition = &code_partition; + }; + + aliases { + led0 = &led_gp3; + led-strip = &ws2812; + sw0 = &user_button; + watchdog0 = &wdt0; + }; + + zephyr,user { + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>; + }; + + gpio_keys { + compatible = "gpio-keys"; + + user_button: button { + label = "User"; + gpios = <&gpio0 2 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + zephyr,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_gp3: led_gp3 { + gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; + label = "LED GP3"; + }; + }; +}; + +&flash0 { + reg = <0x10000000 DT_SIZE_M(2)>; + ranges = <0x0 0x10000000 DT_SIZE_M(2)>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* Reserved memory for the second stage bootloader */ + second_stage_bootloader: partition@0 { + label = "second_stage_bootloader"; + reg = <0x00000000 0x100>; + read-only; + }; + + /* + * Usable flash. Starts at 0x100, after the bootloader. The partition + * size is 2 MB minus the 0x100 bytes taken by the bootloader. + */ + code_partition: partition@100 { + label = "code-partition"; + reg = <0x100 (DT_SIZE_M(2) - 0x100)>; + read-only; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&uart0 { + current-speed = <115200>; + status = "okay"; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +zephyr_i2c: &i2c0 { + status = "okay"; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + clock-frequency = ; +}; + +&spi1 { + pinctrl-0 = <&spi1_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&timer { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&adc { + status = "okay"; + pinctrl-0 = <&adc_default>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; + + channel@1 { + reg = <1>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; + + channel@2 { + reg = <2>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; + + channel@3 { + reg = <3>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; +}; + +&pwm { + pinctrl-0 = <&pwm_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pio0 { + status = "okay"; + + pio-ws2812 { + compatible = "worldsemi,ws2812-rpi_pico-pio"; + status = "okay"; + pinctrl-0 = <&ws2812_pio0_default>; + pinctrl-names = "default"; + bit-waveform = <3>, <3>, <4>; + + ws2812: ws2812 { + status = "okay"; + gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; + chain-length = <2>; + color-mapping = ; + reset-delay = <280>; + frequency = <800000>; + }; + }; +}; + +zephyr_udc0: &usbd { + status = "okay"; +}; + +&die_temp { + status = "okay"; +}; + +&vreg { + regulator-always-on; + regulator-allowed-modes = ; +}; + +&xosc { + startup-delay-multiplier = <64>; +}; diff --git a/boards/cytron/maker_uno_rp2040/maker_uno_rp2040.yaml b/boards/cytron/maker_uno_rp2040/maker_uno_rp2040.yaml new file mode 100644 index 000000000000..01021a2a73bb --- /dev/null +++ b/boards/cytron/maker_uno_rp2040/maker_uno_rp2040.yaml @@ -0,0 +1,22 @@ +identifier: maker_uno_rp2040 +name: Cytron Maker Uno RP2040 +type: mcu +arch: arm +flash: 2048 +ram: 264 +toolchain: + - zephyr + - gnuarmemb +supported: + - adc + - clock + - counter + - dma + - flash + - gpio + - hwinfo + - i2c + - pwm + - spi + - uart + - watchdog diff --git a/boards/cytron/maker_uno_rp2040/maker_uno_rp2040_defconfig b/boards/cytron/maker_uno_rp2040/maker_uno_rp2040_defconfig new file mode 100644 index 000000000000..41b52b5618ef --- /dev/null +++ b/boards/cytron/maker_uno_rp2040/maker_uno_rp2040_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2025 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_BUILD_OUTPUT_UF2=y +CONFIG_CLOCK_CONTROL=y +CONFIG_CONSOLE=y +CONFIG_GPIO=y +CONFIG_PIO_RPI_PICO=y +CONFIG_RESET=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/cytron/motion_2350_pro/Kconfig.defconfig b/boards/cytron/motion_2350_pro/Kconfig.defconfig new file mode 100644 index 000000000000..dd0ddf5f3001 --- /dev/null +++ b/boards/cytron/motion_2350_pro/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2025 Stephano Cetola +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MOTION_2350_PRO + +config USB_SELF_POWERED + default n + +endif # BOARD_MOTION_2350_PRO diff --git a/boards/cytron/motion_2350_pro/Kconfig.motion_2350_pro b/boards/cytron/motion_2350_pro/Kconfig.motion_2350_pro new file mode 100644 index 000000000000..77498272ad5c --- /dev/null +++ b/boards/cytron/motion_2350_pro/Kconfig.motion_2350_pro @@ -0,0 +1,6 @@ +# Copyright (c) 2025 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MOTION_2350_PRO + select SOC_RP2350A_HAZARD3 if BOARD_MOTION_2350_PRO_RP2350A_HAZARD3 + select SOC_RP2350A_M33 if BOARD_MOTION_2350_PRO_RP2350A_M33 diff --git a/boards/cytron/motion_2350_pro/board.cmake b/boards/cytron/motion_2350_pro/board.cmake new file mode 100644 index 000000000000..5b6cbee37801 --- /dev/null +++ b/boards/cytron/motion_2350_pro/board.cmake @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: Apache-2.0 +# Adapted from boards/raspberrypi/rpi_pico2/board.cmake + +if("${RPI_PICO_DEBUG_ADAPTER}" STREQUAL "") + set(RPI_PICO_DEBUG_ADAPTER "cmsis-dap") +endif() + +board_runner_args(openocd --cmd-pre-init "source [find interface/${RPI_PICO_DEBUG_ADAPTER}.cfg]") +if(CONFIG_ARM) + board_runner_args(openocd --cmd-pre-init "source [find target/rp2350.cfg]") +else() + board_runner_args(openocd --cmd-pre-init "source [find target/rp2350-riscv.cfg]") +endif() + +# The adapter speed is expected to be set by interface configuration. +# The Raspberry Pi's OpenOCD fork doesn't, so match their documentation at +# https://www.raspberrypi.com/documentation/microcontrollers/debug-probe.html#debugging-with-swd +board_runner_args(openocd --cmd-pre-init "adapter speed 5000") +board_runner_args(probe-rs "--chip=RP235x") +board_runner_args(jlink "--device=RP2350_M33_0") +board_runner_args(uf2 "--board-id=RP2350") + +# Default runner should be listed first +include(${ZEPHYR_BASE}/boards/common/uf2.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/probe-rs.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/cytron/motion_2350_pro/board.yml b/boards/cytron/motion_2350_pro/board.yml new file mode 100644 index 000000000000..5c42b53d2f37 --- /dev/null +++ b/boards/cytron/motion_2350_pro/board.yml @@ -0,0 +1,6 @@ +board: + name: motion_2350_pro + full_name: Motion 2350 Pro + vendor: cytron + socs: + - name: rp2350a diff --git a/boards/cytron/motion_2350_pro/doc/img/motion_2350_pro.webp b/boards/cytron/motion_2350_pro/doc/img/motion_2350_pro.webp new file mode 100644 index 000000000000..f4e93968801b Binary files /dev/null and b/boards/cytron/motion_2350_pro/doc/img/motion_2350_pro.webp differ diff --git a/boards/cytron/motion_2350_pro/doc/index.rst b/boards/cytron/motion_2350_pro/doc/index.rst new file mode 100644 index 000000000000..ad2f2fee8fb3 --- /dev/null +++ b/boards/cytron/motion_2350_pro/doc/index.rst @@ -0,0 +1,298 @@ +.. zephyr:board:: motion_2350_pro + +Overview +******** + +The `Cytron Motion 2350 Pro`_ board is based on the RP2350A microcontroller from Raspberry Pi Ltd. +The board has motor drivers, servo headers, Maker connectors and a USB type C connector. + + +Hardware +******** + +- Microcontroller Raspberry Pi RP2350A, with a max frequency of 150 MHz +- Dual ARM Cortex M33 cores, and dual RISC-V Hazard3 cores. +- 520 kByte SRAM +- 2 Mbyte QSPI flash +- 12 GPIO pins +- 4 ADC pins +- I2C +- UART +- USB type C connector +- USB host (USB type A connector) +- Reset, boot and 2 user buttons +- 2 RGB LEDs (Neopixels) +- Piezo buzzer with mute switch +- 8 servo ports +- 4 Motor drivers, with 8 manual test bottons +- 3 Maker connectors, of which one can be used as a Qwiic/Stemma QT/zephyr_i2c connector +- 16 status indicators for digital pins + + +Default Zephyr Peripheral Mapping +================================= + ++---------------+--------+-----------------------------+-----------------+ +| Description | Pin | Default pin mux | Zephyr PWM name | ++===============+========+=============================+=================+ +| Button 1 | GPIO20 | (Alias sw0) | | ++---------------+--------+-----------------------------+-----------------+ +| Button 2 | GPIO21 | (Alias sw1) | | ++---------------+--------+-----------------------------+-----------------+ +| Buzzer | GPIO22 | PWM3A (also used for servo) | 6 | ++---------------+--------+-----------------------------+-----------------+ +| RGB LEDs | GPIO23 | PIO0 | | ++---------------+--------+-----------------------------+-----------------+ +| USB host D+ | GPIO24 | | | ++---------------+--------+-----------------------------+-----------------+ +| USB host D- | GPIO25 | | | ++---------------+--------+-----------------------------+-----------------+ + + +GPIO header: + ++-------+--------+-----------------+----------------------+ +| Label | Pin | Default pin mux | Also in connector | ++=======+========+=================+======================+ +| GP16 | GPIO16 | I2C0 SDA | Maker port GP16+GP17 | ++-------+--------+-----------------+----------------------+ +| GP17 | GPIO17 | I2C0 SCL | Maker port GP16+GP17 | ++-------+--------+-----------------+----------------------+ +| GP18 | GPIO18 | (Alias led0) | | ++-------+--------+-----------------+----------------------+ +| GP19 | GPIO19 | (Alias led1) | | ++-------+--------+-----------------+----------------------+ +| GP26 | GPIO26 | ADC0 | Maker port GP26+GP27 | ++-------+--------+-----------------+----------------------+ +| GP27 | GPIO27 | ADC1 | Maker port GP26+GP27 | ++-------+--------+-----------------+----------------------+ +| GP28 | GPIO28 | UART0 TX | Maker port GP28+GP29 | ++-------+--------+-----------------+----------------------+ +| GP29 | GPIO29 | UART0 RX | Maker port GP28+GP29 | ++-------+--------+-----------------+----------------------+ + + +Servo header (Note that PWM3A is also used for the buzzer): + ++-------+--------+-----------------+-----------------+ +| Label | Pin | Default pin mux | Zephyr PWM name | ++=======+========+=================+=================+ +| GP0 | GPIO0 | PWM0A | 0 | ++-------+--------+-----------------+-----------------+ +| GP1 | GPIO1 | PWM0B | 1 | ++-------+--------+-----------------+-----------------+ +| GP2 | GPIO2 | PWM1A | 2 | ++-------+--------+-----------------+-----------------+ +| GP3 | GPIO3 | PWM1B | 3 | ++-------+--------+-----------------+-----------------+ +| GP4 | GPIO4 | PWM2A | 4 | ++-------+--------+-----------------+-----------------+ +| GP5 | GPIO5 | PWM2B | 5 | ++-------+--------+-----------------+-----------------+ +| GP6 | GPIO6 | PWM3A | 6 | ++-------+--------+-----------------+-----------------+ +| GP7 | GPIO7 | PWM3B | 7 | ++-------+--------+-----------------+-----------------+ + + +Motor drivers: + ++-------+--------+-----------------+-----------------+ +| Label | Pin | Default pin mux | Zephyr PWM name | ++=======+========+=================+=================+ +| M1A | GPIO8 | PWM4A | 8 | ++-------+--------+-----------------+-----------------+ +| M1B | GPIO9 | PWM4B | 9 | ++-------+--------+-----------------+-----------------+ +| M2A | GPIO10 | PWM5A | 10 | ++-------+--------+-----------------+-----------------+ +| M2B | GPIO11 | PWM5B | 11 | ++-------+--------+-----------------+-----------------+ +| M3A | GPIO12 | PWM6A | 12 | ++-------+--------+-----------------+-----------------+ +| M3B | GPIO13 | PWM6B | 13 | ++-------+--------+-----------------+-----------------+ +| M4A | GPIO14 | PWM7A | 14 | ++-------+--------+-----------------+-----------------+ +| M4B | GPIO15 | PWM7B | 15 | ++-------+--------+-----------------+-----------------+ + + +Connector GP16+GP17: + +Connect Qwiic/Stemma QT sensors (that use I2C) to this connector. + +The pins are also available in the GPIO header. + ++-------+--------+-----------------+ +| Label | Pin | Default pin mux | ++=======+========+=================+ +| GP16 | GPIO16 | I2C0 SDA | ++-------+--------+-----------------+ +| GP17 | GPIO17 | I2C0 SCL | ++-------+--------+-----------------+ + + +Connector GP26+GP27: + +The pins are also available in the GPIO header. + ++-------+--------+-----------------+ +| Label | Pin | Default pin mux | ++=======+========+=================+ +| GP26 | GPIO26 | ADC0 | ++-------+--------+-----------------+ +| GP27 | GPIO27 | ADC1 | ++-------+--------+-----------------+ + + +Connector GP28+GP29: + +The pins are also available in the GPIO header. + ++-------+--------+-----------------+ +| Label | Pin | Default pin mux | ++=======+========+=================+ +| GP28 | GPIO28 | UART0 TX | ++-------+--------+-----------------+ +| GP29 | GPIO29 | UART0 RX | ++-------+--------+-----------------+ + +See also `pinout`_. + + +Supported Features +================== + +Note that USB host (the big USB type A connector) is not yet supported. + +.. zephyr:board-supported-hw:: + + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +By default programming is done via the USB connector. Press and hold the BOOT button, and then +press the RST button, and the device will appear as a USB mass storage unit. +Building your application will result in a :file:`build/zephyr/zephyr.uf2` file. +Drag and drop the file to the USB mass storage unit, and the board will be reprogrammed. + +It is also possible to program and debug the board via the SWDIO and SWCLK pins in the DEBUG +connector. You must solder a 3-pin header to the board in order to use this feature. +A separate programming hardware tool is required, and for example the :command:`openocd` software +is used. You might need to use Raspberry Pi's forked version of OpenOCD. +Typically the ``OPENOCD`` and ``OPENOCD_DEFAULT_PATH`` values should be set when +building, and the ``--runner openocd`` argument should be used when flashing. +For more details on programming RP2040-based and RP2350-based boards, +see :ref:`rpi_pico_programming_and_debugging`. + + +Flashing the M33 core +===================== + +To run the :zephyr:code-sample:`blinky` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky/ + :board: motion_2350_pro/rp2350a/m33 + :goals: build flash + +Try also the :zephyr:code-sample:`led-strip`, :zephyr:code-sample:`hello_world`, +:zephyr:code-sample:`button`, :zephyr:code-sample:`input-dump` and +:zephyr:code-sample:`adc_dt` samples. + +The use of the Maker/Qwiic/Stemma QT I2C connector (GP16+GP17) is demonstrated using the +:zephyr:code-sample:`light_sensor_polling` sample and a separate shield: + +.. zephyr-app-commands:: + :zephyr-app: samples/sensor/light_polling + :board: motion_2350_pro/rp2350a/m33 + :shield: adafruit_veml7700 + :goals: build flash + +Use the shell to control the GPIO pins: + +.. zephyr-app-commands:: + :zephyr-app: samples/sensor/sensor_shell + :board: motion_2350_pro/rp2350a/m33 + :gen-args: -DCONFIG_GPIO=y -DCONFIG_GPIO_SHELL=y + :goals: build flash + +To set one of the GPIO pins high, use these commands in the shell, and study the indicator LEDs: + +.. code-block:: shell + + gpio conf gpio0 18 o + gpio set gpio0 18 1 + +Servo motor control is done via PWM outputs. The :zephyr:code-sample:`servo-motor` +sample sets servo position timing (via an overlay file) for the output GP0: + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/servo_motor/ + :board: motion_2350_pro/rp2350a/m33 + :goals: build flash + +It is also possible to control servos via the pwm shell: + +.. zephyr-app-commands:: + :zephyr-app: samples/sensor/sensor_shell + :board: motion_2350_pro/rp2350a/m33 + :gen-args: -DCONFIG_PWM=y -DCONFIG_PWM_SHELL=y + :goals: build flash + +Use shell commands to set the position of the servo. Most servo motors can handle pulse +times between 800 and 2000 microseconds: + +.. code-block:: shell + + pwm usec pwm@400a8000 0 20000 800 + pwm usec pwm@400a8000 0 20000 2000 + +To use the buzzer, you must turn on the buzzer switch on the short side of the board. +Then build using the same command as above for the sensor_shell. +Use these shell commands to turn on and off the buzzer: + +.. code-block:: shell + + pwm usec pwm@400a8000 6 1000 500 + pwm usec pwm@400a8000 6 1000 0 + +You can also control the motor outputs via the shell. To set the speed of motor 1 to +100%, 50%, 20% and 0% respectively, use these commands: + +.. code-block:: shell + + pwm usec pwm@400a8000 8 1000 1000 + pwm usec pwm@400a8000 8 1000 500 + pwm usec pwm@400a8000 8 1000 200 + pwm usec pwm@400a8000 8 1000 0 + +To run the motor in the opposite direction at 80% speed: + +.. code-block:: shell + + pwm usec pwm@400a8000 9 1000 800 + + +Flashing the Hazard3 core +========================= + +The RP2350A microcontroller has two ARM M33 cores and two RISC-V Hazard3 cores. +To flash one of the Hazard3 cores, use the board argument ``motion_2350_pro/rp2350a/hazard3``. +The samples :zephyr:code-sample:`blinky` and :zephyr:code-sample:`input-dump` have been +verified for this core. Use the USB mass storage programming method described above. + + +References +********** + +.. target-notes:: + +.. _Cytron Motion 2350 Pro: + https://www.cytron.io/p-motion-2350-pro + +.. _pinout: + https://static.cytron.io/image/catalog/products/MOTION-2350-PRO/pinout-diagram-motion-2350-pro3.png diff --git a/boards/cytron/motion_2350_pro/motion_2350_pro-pinctrl.dtsi b/boards/cytron/motion_2350_pro/motion_2350_pro-pinctrl.dtsi new file mode 100644 index 000000000000..0341a3957676 --- /dev/null +++ b/boards/cytron/motion_2350_pro/motion_2350_pro-pinctrl.dtsi @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2025 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + adc_default: adc_default { + group1 { + pinmux = , ; + input-enable; + }; + }; + + i2c0_default: i2c0_default { + group1 { + pinmux = , ; + input-enable; + }; + }; + + uart0_default: uart0_default { + group1 { + pinmux = ; + }; + + group2 { + pinmux = ; + input-enable; + }; + }; + + pwm_default: pwm_default { + group1 { + pinmux = , , , , + , ; + }; + + group2 { + pinmux = , , , , + , ; + }; + + group3 { + pinmux = , , , , + ; + }; + }; + + ws2812_pio0_default: ws2812_pio0_default { + ws2812 { + pinmux = ; + }; + }; +}; diff --git a/boards/cytron/motion_2350_pro/motion_2350_pro.dtsi b/boards/cytron/motion_2350_pro/motion_2350_pro.dtsi new file mode 100644 index 000000000000..0081d0b2f167 --- /dev/null +++ b/boards/cytron/motion_2350_pro/motion_2350_pro.dtsi @@ -0,0 +1,179 @@ +/* + * Copyright (c) 2025 Stephano Cetola + * Copyright (c) 2025 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include + +#include +#include +#include +#include +#include +#include "motion_2350_pro-pinctrl.dtsi" + +/ { + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; + + aliases { + led-strip = &ws2812; + led0 = &led_gp18; + led1 = &led_gp19; + sw0 = &button_gp20; + sw1 = &button_gp21; + watchdog0 = &wdt0; + }; + + zephyr,user { + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>; + }; + + gpio_keys { + compatible = "gpio-keys"; + + button_gp20: button_gp20 { + label = "Button GP20"; + gpios = <&gpio0 20 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + zephyr,code = ; + }; + + button_gp21: button_gp21 { + label = "Button GP21"; + gpios = <&gpio0 21 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + zephyr,code = ; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + + led_gp18: led_gp18 { + gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; + label = "LED GP18"; + }; + + led_gp19: led_gp19 { + gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>; + label = "LED GP10"; + }; + }; + + stemma_connector: stemma_connector { + compatible = "stemma-qt-connector"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 17 0>, /* SCL */ + <1 0 &gpio0 16 0>; /* SDA */ + }; +}; + +&flash0 { + reg = <0x10000000 DT_SIZE_M(2)>; +}; + +&gpio0 { + status = "okay"; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +zephyr_i2c: &i2c0 { + status = "okay"; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + clock-frequency = ; +}; + +&adc { + status = "okay"; + pinctrl-0 = <&adc_default>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; + + channel@1 { + reg = <1>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; + + channel@2 { + reg = <2>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; + + channel@3 { + reg = <3>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; +}; + +&pio0 { + status = "okay"; + + pio-ws2812 { + compatible = "worldsemi,ws2812-rpi_pico-pio"; + status = "okay"; + pinctrl-0 = <&ws2812_pio0_default>; + pinctrl-names = "default"; + bit-waveform = <3>, <3>, <4>; + + ws2812: ws2812 { + status = "okay"; + gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>; + chain-length = <2>; + color-mapping = ; + reset-delay = <280>; + frequency = ; + }; + }; +}; + +&pwm { + status = "okay"; + pinctrl-0 = <&pwm_default>; + pinctrl-names = "default"; + divider-int-0 = <255>; +}; + +&timer0 { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +zephyr_udc0: &usbd { + status = "okay"; +}; diff --git a/boards/cytron/motion_2350_pro/motion_2350_pro_rp2350a_hazard3.dts b/boards/cytron/motion_2350_pro/motion_2350_pro_rp2350a_hazard3.dts new file mode 100644 index 000000000000..7108666c5187 --- /dev/null +++ b/boards/cytron/motion_2350_pro/motion_2350_pro_rp2350a_hazard3.dts @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2025 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include + +#include "motion_2350_pro.dtsi" diff --git a/boards/cytron/motion_2350_pro/motion_2350_pro_rp2350a_hazard3.yaml b/boards/cytron/motion_2350_pro/motion_2350_pro_rp2350a_hazard3.yaml new file mode 100644 index 000000000000..beef2e0d7b57 --- /dev/null +++ b/boards/cytron/motion_2350_pro/motion_2350_pro_rp2350a_hazard3.yaml @@ -0,0 +1,22 @@ +identifier: motion_2350_pro/rp2350a/hazard3 +name: Cytron Motion 2350 Pro (Hazard3) +type: mcu +arch: riscv +flash: 2048 +ram: 520 +toolchain: + - zephyr +supported: + - adc + - clock + - counter + - dma + - flash + - gpio + - hwinfo + - i2c + - pwm + - spi + - uart + - usbd + - watchdog diff --git a/boards/cytron/motion_2350_pro/motion_2350_pro_rp2350a_hazard3_defconfig b/boards/cytron/motion_2350_pro/motion_2350_pro_rp2350a_hazard3_defconfig new file mode 100644 index 000000000000..40aec62529fa --- /dev/null +++ b/boards/cytron/motion_2350_pro/motion_2350_pro_rp2350a_hazard3_defconfig @@ -0,0 +1,14 @@ +# Copyright (c) 2025 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_OUTPUT_UF2=y +CONFIG_CLOCK_CONTROL=y +CONFIG_CONSOLE=y +CONFIG_GPIO=y +CONFIG_PIO_RPI_PICO=y +CONFIG_RESET=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/cytron/motion_2350_pro/motion_2350_pro_rp2350a_m33.dts b/boards/cytron/motion_2350_pro/motion_2350_pro_rp2350a_m33.dts new file mode 100644 index 000000000000..478aeaefaf62 --- /dev/null +++ b/boards/cytron/motion_2350_pro/motion_2350_pro_rp2350a_m33.dts @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2025 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include + +#include "motion_2350_pro.dtsi" diff --git a/boards/cytron/motion_2350_pro/motion_2350_pro_rp2350a_m33.yaml b/boards/cytron/motion_2350_pro/motion_2350_pro_rp2350a_m33.yaml new file mode 100644 index 000000000000..9db99e10f556 --- /dev/null +++ b/boards/cytron/motion_2350_pro/motion_2350_pro_rp2350a_m33.yaml @@ -0,0 +1,23 @@ +identifier: motion_2350_pro/rp2350a/m33 +name: Cytron Motion 2350 Pro (Cortex M33) +type: mcu +arch: arm +flash: 2048 +ram: 520 +toolchain: + - zephyr + - gnuarmemb +supported: + - adc + - clock + - counter + - dma + - flash + - gpio + - hwinfo + - i2c + - pwm + - spi + - uart + - usbd + - watchdog diff --git a/boards/cytron/motion_2350_pro/motion_2350_pro_rp2350a_m33_defconfig b/boards/cytron/motion_2350_pro/motion_2350_pro_rp2350a_m33_defconfig new file mode 100644 index 000000000000..40aec62529fa --- /dev/null +++ b/boards/cytron/motion_2350_pro/motion_2350_pro_rp2350a_m33_defconfig @@ -0,0 +1,14 @@ +# Copyright (c) 2025 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_OUTPUT_UF2=y +CONFIG_CLOCK_CONTROL=y +CONFIG_CONSOLE=y +CONFIG_GPIO=y +CONFIG_PIO_RPI_PICO=y +CONFIG_RESET=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/deprecated.cmake b/boards/deprecated.cmake index 37432630ddb4..bc664f79b06b 100644 --- a/boards/deprecated.cmake +++ b/boards/deprecated.cmake @@ -22,27 +22,6 @@ set(arduino_uno_r4_wifi_DEPRECATED set(esp32c6_devkitc_DEPRECATED esp32c6_devkitc/esp32c6/hpcore ) -set(qemu_xtensa_DEPRECATED - qemu_xtensa/dc233c -) -set(mimx8mp_phyboard_pollux/mimx8ml8/m7_DEPRECATED - phyboard_pollux/mimx8ml8/m7 -) -set(mimx8mm_phyboard_polis/mimx8mm6/m4_DEPRECATED - phyboard_polis/mimx8mm6/m4 -) -set(mimxrt1050_evk_DEPRECATED - mimxrt1050_evk/mimxrt1052/hyperflash -) -set(mimxrt1060_evk_DEPRECATED - mimxrt1060_evk/mimxrt1064/hyperflash -) -set(mimxrt1060_evk_DEPRECATED - mimxrt1060_evk/mimxrt1062/qspi -) -set(mimxrt1060_evkb_DEPRECATED - mimxrt1060_evk@B/mimxrt1062/qspi -) set(neorv32_DEPRECATED neorv32/neorv32/up5kdemo ) @@ -79,3 +58,15 @@ set(fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a/smp_DEPRECATED set(fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a/smp/ns_DEPRECATED fvp_base_revc_2xaem/v8a/smp/ns ) +set(esp32s3_devkitm/esp32s3/procpu_DEPRECATED + esp32s3_devkitc/esp32s3/procpu +) +set(esp32s3_devkitm/esp32s3/appcpu_DEPRECATED + esp32s3_devkitc/esp32s3/appcpu +) +set(ubx_evk_iris_w1_fidelex/rw612_DEPRECATED + ubx_evk_iris_w1@fidelix/rw612 +) +set(it51xxx_evb_DEPRECATED + it515xx_evb/it51526aw +) diff --git a/boards/dfrobot/beetle_esp32c3/Kconfig b/boards/dfrobot/beetle_esp32c3/Kconfig new file mode 100644 index 000000000000..4bb5b45f36c5 --- /dev/null +++ b/boards/dfrobot/beetle_esp32c3/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2025 Mikołaj Rosowski +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 diff --git a/boards/dfrobot/beetle_esp32c3/Kconfig.beetle_esp32c3 b/boards/dfrobot/beetle_esp32c3/Kconfig.beetle_esp32c3 new file mode 100644 index 000000000000..c116088d0340 --- /dev/null +++ b/boards/dfrobot/beetle_esp32c3/Kconfig.beetle_esp32c3 @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Mikołaj Rosowski +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BEETLE_ESP32C3 + select SOC_ESP32C3_FN4 diff --git a/boards/dfrobot/beetle_esp32c3/Kconfig.sysbuild b/boards/dfrobot/beetle_esp32c3/Kconfig.sysbuild new file mode 100644 index 000000000000..861b227d7ab5 --- /dev/null +++ b/boards/dfrobot/beetle_esp32c3/Kconfig.sysbuild @@ -0,0 +1,10 @@ +# Copyright (c) 2025 Mikołaj Rosowski +# SPDX-License-Identifier: Apache-2.0 + +choice BOOTLOADER + default BOOTLOADER_MCUBOOT +endchoice + +choice BOOT_SIGNATURE_TYPE + default BOOT_SIGNATURE_TYPE_NONE +endchoice diff --git a/boards/dfrobot/beetle_esp32c3/beetle_esp32c3-pinctrl.dtsi b/boards/dfrobot/beetle_esp32c3/beetle_esp32c3-pinctrl.dtsi new file mode 100644 index 000000000000..7009c35d30c4 --- /dev/null +++ b/boards/dfrobot/beetle_esp32c3/beetle_esp32c3-pinctrl.dtsi @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2025 Mikołaj Rosowski + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +&pinctrl { + uart0_default: uart0_default { + group1 { + pinmux = ; + bias-pull-up; + }; + + group2 { + pinmux = ; + output-high; + }; + }; + + i2c0_default: i2c0_default { + group1 { + pinmux = , + ; + bias-pull-up; + drive-open-drain; + output-high; + }; + }; + + spim2_default: spim2_default { + group1 { + pinmux = , + ; + }; + + group2 { + pinmux = ; + output-low; + }; + }; + + twai_default: twai_default { + group1 { + pinmux = , + ; + }; + }; +}; diff --git a/boards/dfrobot/beetle_esp32c3/beetle_esp32c3.dts b/boards/dfrobot/beetle_esp32c3/beetle_esp32c3.dts new file mode 100644 index 000000000000..875f0ada53b7 --- /dev/null +++ b/boards/dfrobot/beetle_esp32c3/beetle_esp32c3.dts @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2025 Mikołaj Rosowski + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "beetle_esp32c3-pinctrl.dtsi" + +/ { + model = "DFRobot Beetle ESP32-C3"; + compatible = "dfrobot,beetle_esp32c3"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &usb_serial; + zephyr,shell-uart = &usb_serial; + zehpyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,canbus = &twai; + zephyr,bt-hci = &esp32_bt_hci; + }; + + aliases { + i2c-0 = &i2c0; + led0 = &blue_led; + watchdog0 = &wdt0; + }; + + leds { + compatible = "gpio-leds"; + + blue_led: led0 { + gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>; + label = "Blue LED"; + }; + }; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&usb_serial { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; +}; + +&trng0 { + status = "okay"; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&twai { + status = "okay"; + pinctrl-0 = <&twai_default>; + pinctrl-names = "default"; +}; + +&esp32_bt_hci { + status = "okay"; +}; + +&wifi { + status = "okay"; +}; diff --git a/boards/dfrobot/beetle_esp32c3/beetle_esp32c3.yaml b/boards/dfrobot/beetle_esp32c3/beetle_esp32c3.yaml new file mode 100644 index 000000000000..68c83adfa17a --- /dev/null +++ b/boards/dfrobot/beetle_esp32c3/beetle_esp32c3.yaml @@ -0,0 +1,21 @@ +identifier: beetle_esp32c3 +name: DFRobot Beetle ESP32-C3 +type: mcu +arch: riscv +toolchain: + - zephyr +supported: + - adc + - counter + - crypto + - dma + - entropy + - gpio + - i2c + - input + - nvs + - pwm + - spi + - uart + - watchdog +vendor: dfrobot diff --git a/boards/dfrobot/beetle_esp32c3/beetle_esp32c3_1_0_0.yaml b/boards/dfrobot/beetle_esp32c3/beetle_esp32c3_1_0_0.yaml new file mode 100644 index 000000000000..e67a6182d591 --- /dev/null +++ b/boards/dfrobot/beetle_esp32c3/beetle_esp32c3_1_0_0.yaml @@ -0,0 +1,20 @@ +identifier: beetle_esp32c3@1.0.0 +name: DFRobot Beetle ESP32-C3 (rev. 1.0.0) +type: mcu +arch: riscv +toolchain: + - zephyr +supported: + - adc + - counter + - crypto + - dma + - entropy + - gpio + - i2c + - nvs + - pwm + - spi + - uart + - watchdog +vendor: dfrobot diff --git a/boards/dfrobot/beetle_esp32c3/beetle_esp32c3_2_0_0.overlay b/boards/dfrobot/beetle_esp32c3/beetle_esp32c3_2_0_0.overlay new file mode 100644 index 000000000000..7cbffdfee87c --- /dev/null +++ b/boards/dfrobot/beetle_esp32c3/beetle_esp32c3_2_0_0.overlay @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2025 Mikołaj Rosowski + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + aliases { + sw0 = &boot_button; + }; + + buttons { + compatible = "gpio-keys"; + + boot_button: button0 { + gpios = <&gpio0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "BOOT button"; + zephyr,code = ; + }; + }; +}; diff --git a/boards/dfrobot/beetle_esp32c3/beetle_esp32c3_defconfig b/boards/dfrobot/beetle_esp32c3/beetle_esp32c3_defconfig new file mode 100644 index 000000000000..3213c031327e --- /dev/null +++ b/boards/dfrobot/beetle_esp32c3/beetle_esp32c3_defconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2025 Mikołaj Rosowski +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y diff --git a/boards/dfrobot/beetle_esp32c3/board.cmake b/boards/dfrobot/beetle_esp32c3/board.cmake new file mode 100644 index 000000000000..2a1c8328c92f --- /dev/null +++ b/boards/dfrobot/beetle_esp32c3/board.cmake @@ -0,0 +1,10 @@ +# Copyright (c) 2025 Mikołaj Rosowski +# SPDX-License-Identifier: Apache-2.0 + +if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*") + set(OPENOCD OPENOCD-NOTFOUND) +endif() +find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH) + +include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/dfrobot/beetle_esp32c3/board.yml b/boards/dfrobot/beetle_esp32c3/board.yml new file mode 100644 index 000000000000..1bea455d4fc4 --- /dev/null +++ b/boards/dfrobot/beetle_esp32c3/board.yml @@ -0,0 +1,12 @@ +board: + name: beetle_esp32c3 + full_name: DFRobot Beetle ESP32-C3 + vendor: dfrobot + revision: + format: major.minor.patch + default: "2.0.0" + revisions: + - name: "1.0.0" + - name: "2.0.0" + socs: + - name: esp32c3 diff --git a/boards/dfrobot/beetle_esp32c3/doc/img/beetle_esp32c3.webp b/boards/dfrobot/beetle_esp32c3/doc/img/beetle_esp32c3.webp new file mode 100644 index 000000000000..d16c9988d971 Binary files /dev/null and b/boards/dfrobot/beetle_esp32c3/doc/img/beetle_esp32c3.webp differ diff --git a/boards/dfrobot/beetle_esp32c3/doc/img/beetle_esp32c3_pinout.webp b/boards/dfrobot/beetle_esp32c3/doc/img/beetle_esp32c3_pinout.webp new file mode 100644 index 000000000000..ad85b8868368 Binary files /dev/null and b/boards/dfrobot/beetle_esp32c3/doc/img/beetle_esp32c3_pinout.webp differ diff --git a/boards/dfrobot/beetle_esp32c3/doc/index.rst b/boards/dfrobot/beetle_esp32c3/doc/index.rst new file mode 100644 index 000000000000..0ca2e7d8df4a --- /dev/null +++ b/boards/dfrobot/beetle_esp32c3/doc/index.rst @@ -0,0 +1,63 @@ +.. zephyr:board:: beetle_esp32c3 + +Overview +******** + +The `DFRobot Beetle ESP32-C3`_ board, mainly intended for IoT +applications, is based on the ESP32-C3 WiFi/Bluetooth +dual-mode chip from Espressif. + +Hardware +******** + +This board is based on the ESP32-C3 with 4MB of flash, WiFi and BLE support. +It has an USB-C port for programming and debugging, built-in battery +charging management function via TP4057 chip and 13 IO ports. + +.. include:: ../../../espressif/common/soc-esp32c3-features.rst + :start-after: espressif-soc-esp32c3-features + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Connections and IOs +=================== + +.. figure:: img/beetle_esp32c3_pinout.webp + :align: center + :alt: Beetle ESP32-C3 Pinout + + Beetle ESP32-C3 Pinout + +For more details please refer to `DFRobot Beetle ESP32-C3 Wiki`_ + +System Requirements +******************* + +.. include:: ../../../espressif/common/system-requirements.rst + :start-after: espressif-system-requirements + +Programming and debugging +************************* + +.. zephyr:board-supported-runners:: + +.. include:: ../../../espressif/common/building-flashing.rst + :start-after: espressif-building-flashing + +Debugging +========= + +.. include:: ../../../espressif/common/openocd-debugging.rst + :start-after: espressif-openocd-debugging + +References +********** + +.. target-notes:: + +.. _`DFRobot Beetle ESP32-C3`: https://www.dfrobot.com/product-2566.html + +.. _`DFRobot Beetle ESP32-C3 Wiki`: https://wiki.dfrobot.com/SKU_DFR0868_Beetle_ESP32_C3 diff --git a/boards/dfrobot/beetle_esp32c3/support/openocd.cfg b/boards/dfrobot/beetle_esp32c3/support/openocd.cfg new file mode 100644 index 000000000000..cf1bc91bbf9f --- /dev/null +++ b/boards/dfrobot/beetle_esp32c3/support/openocd.cfg @@ -0,0 +1,6 @@ +set ESP_RTOS Zephyr + +source [find interface/esp_usb_jtag.cfg] + +source [find target/esp32c3.cfg] +adapter speed 5000 diff --git a/boards/dfrobot/beetle_rp2040/beetle_rp2040.dts b/boards/dfrobot/beetle_rp2040/beetle_rp2040.dts index c1e04310a37a..5ab1b2575270 100644 --- a/boards/dfrobot/beetle_rp2040/beetle_rp2040.dts +++ b/boards/dfrobot/beetle_rp2040/beetle_rp2040.dts @@ -48,11 +48,13 @@ &flash0 { reg = <0x10000000 DT_SIZE_M(2)>; + ranges = <0x0 0x10000000 DT_SIZE_M(2)>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + ranges; /* Reserved memory for the second stage bootloader */ second_stage_bootloader: partition@0 { diff --git a/boards/dfrobot/beetle_rp2350/Kconfig.beetle_rp2350 b/boards/dfrobot/beetle_rp2350/Kconfig.beetle_rp2350 new file mode 100644 index 000000000000..435fe5470e9a --- /dev/null +++ b/boards/dfrobot/beetle_rp2350/Kconfig.beetle_rp2350 @@ -0,0 +1,6 @@ +# Copyright (c) 2026 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BEETLE_RP2350 + select SOC_RP2350A_HAZARD3 if BOARD_BEETLE_RP2350_RP2350A_HAZARD3 + select SOC_RP2350A_M33 if BOARD_BEETLE_RP2350_RP2350A_M33 diff --git a/boards/dfrobot/beetle_rp2350/Kconfig.defconfig b/boards/dfrobot/beetle_rp2350/Kconfig.defconfig new file mode 100644 index 000000000000..9e3f8d981e3d --- /dev/null +++ b/boards/dfrobot/beetle_rp2350/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2025 Stephano Cetola +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_BEETLE_RP2350 + +config USB_SELF_POWERED + default n + +endif # BOARD_BEETLE_RP2350 diff --git a/boards/dfrobot/beetle_rp2350/beetle_rp2350-pinctrl.dtsi b/boards/dfrobot/beetle_rp2350/beetle_rp2350-pinctrl.dtsi new file mode 100644 index 000000000000..fa2c3ab0a1c8 --- /dev/null +++ b/boards/dfrobot/beetle_rp2350/beetle_rp2350-pinctrl.dtsi @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2026 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + adc_default: adc_default { + group1 { + pinmux = , ; + input-enable; + }; + }; + + i2c0_default: i2c0_default { + group1 { + pinmux = , ; + input-enable; + }; + }; + + spi0_default: spi0_default { + group1 { + pinmux = , ; + }; + + group2 { + pinmux = ; + input-enable; + }; + }; + + uart0_default: uart0_default { + group1 { + pinmux = ; + }; + + group2 { + pinmux = ; + input-enable; + }; + }; +}; diff --git a/boards/dfrobot/beetle_rp2350/beetle_rp2350.dtsi b/boards/dfrobot/beetle_rp2350/beetle_rp2350.dtsi new file mode 100644 index 000000000000..e25285a27773 --- /dev/null +++ b/boards/dfrobot/beetle_rp2350/beetle_rp2350.dtsi @@ -0,0 +1,120 @@ +/* + * Copyright (c) 2025 Stephano Cetola + * Copyright (c) 2026 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include + +#include +#include +#include +#include +#include "beetle_rp2350-pinctrl.dtsi" + +/ { + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; + + aliases { + led0 = &red_led; + watchdog0 = &wdt0; + }; + + zephyr,user { + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>; + }; + + leds: leds { + compatible = "gpio-leds"; + + red_led: red_led { + gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; + label = "User LED"; + }; + }; +}; + +&flash0 { + reg = <0x10000000 DT_SIZE_M(2)>; +}; + +&gpio0 { + status = "okay"; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&i2c0 { + status = "okay"; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + clock-frequency = ; +}; + +&spi0 { + pinctrl-0 = <&spi0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&adc { + status = "okay"; + pinctrl-0 = <&adc_default>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; + + channel@1 { + reg = <1>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; + + channel@2 { + reg = <2>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; + + channel@3 { + reg = <3>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; +}; + +&timer0 { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +zephyr_udc0: &usbd { + status = "okay"; +}; diff --git a/boards/dfrobot/beetle_rp2350/beetle_rp2350_rp2350a_hazard3.dts b/boards/dfrobot/beetle_rp2350/beetle_rp2350_rp2350a_hazard3.dts new file mode 100644 index 000000000000..73e055defd82 --- /dev/null +++ b/boards/dfrobot/beetle_rp2350/beetle_rp2350_rp2350a_hazard3.dts @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2026 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include + +#include "beetle_rp2350.dtsi" diff --git a/boards/dfrobot/beetle_rp2350/beetle_rp2350_rp2350a_hazard3.yaml b/boards/dfrobot/beetle_rp2350/beetle_rp2350_rp2350a_hazard3.yaml new file mode 100644 index 000000000000..90055a10a847 --- /dev/null +++ b/boards/dfrobot/beetle_rp2350/beetle_rp2350_rp2350a_hazard3.yaml @@ -0,0 +1,22 @@ +identifier: beetle_rp2350/rp2350a/hazard3 +name: DFRobot Beetle RP2350 (Hazard3) +type: mcu +arch: riscv +flash: 2048 +ram: 520 +toolchain: + - zephyr +supported: + - adc + - clock + - counter + - dma + - flash + - gpio + - hwinfo + - i2c + - pwm + - spi + - uart + - usbd + - watchdog diff --git a/boards/dfrobot/beetle_rp2350/beetle_rp2350_rp2350a_hazard3_defconfig b/boards/dfrobot/beetle_rp2350/beetle_rp2350_rp2350a_hazard3_defconfig new file mode 100644 index 000000000000..85b60ee95c5a --- /dev/null +++ b/boards/dfrobot/beetle_rp2350/beetle_rp2350_rp2350a_hazard3_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2026 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_OUTPUT_UF2=y +CONFIG_CLOCK_CONTROL=y +CONFIG_CONSOLE=y +CONFIG_GPIO=y +CONFIG_RESET=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/dfrobot/beetle_rp2350/beetle_rp2350_rp2350a_m33.dts b/boards/dfrobot/beetle_rp2350/beetle_rp2350_rp2350a_m33.dts new file mode 100644 index 000000000000..48f9708428c4 --- /dev/null +++ b/boards/dfrobot/beetle_rp2350/beetle_rp2350_rp2350a_m33.dts @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2026 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include + +#include "beetle_rp2350.dtsi" diff --git a/boards/dfrobot/beetle_rp2350/beetle_rp2350_rp2350a_m33.yaml b/boards/dfrobot/beetle_rp2350/beetle_rp2350_rp2350a_m33.yaml new file mode 100644 index 000000000000..5d7fe671c516 --- /dev/null +++ b/boards/dfrobot/beetle_rp2350/beetle_rp2350_rp2350a_m33.yaml @@ -0,0 +1,23 @@ +identifier: beetle_rp2350/rp2350a/m33 +name: DFRobot Beetle RP2350 (Cortex M33) +type: mcu +arch: arm +flash: 2048 +ram: 520 +toolchain: + - zephyr + - gnuarmemb +supported: + - adc + - clock + - counter + - dma + - flash + - gpio + - hwinfo + - i2c + - pwm + - spi + - uart + - usbd + - watchdog diff --git a/boards/dfrobot/beetle_rp2350/beetle_rp2350_rp2350a_m33_defconfig b/boards/dfrobot/beetle_rp2350/beetle_rp2350_rp2350a_m33_defconfig new file mode 100644 index 000000000000..85b60ee95c5a --- /dev/null +++ b/boards/dfrobot/beetle_rp2350/beetle_rp2350_rp2350a_m33_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2026 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_OUTPUT_UF2=y +CONFIG_CLOCK_CONTROL=y +CONFIG_CONSOLE=y +CONFIG_GPIO=y +CONFIG_RESET=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/dfrobot/beetle_rp2350/board.cmake b/boards/dfrobot/beetle_rp2350/board.cmake new file mode 100644 index 000000000000..787e2850a863 --- /dev/null +++ b/boards/dfrobot/beetle_rp2350/board.cmake @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: Apache-2.0 +# Adapted from boards/raspberrypi/rpi_pico2/board.cmake + +if("${RPI_PICO_DEBUG_ADAPTER}" STREQUAL "") + set(RPI_PICO_DEBUG_ADAPTER "cmsis-dap") +endif() + +board_runner_args(openocd --cmd-pre-init "source [find interface/${RPI_PICO_DEBUG_ADAPTER}.cfg]") +if(CONFIG_ARM) + board_runner_args(openocd --cmd-pre-init "source [find target/rp2350.cfg]") +else() + board_runner_args(openocd --cmd-pre-init "source [find target/rp2350-riscv.cfg]") +endif() + +# The adapter speed is expected to be set by interface configuration. +# The Raspberry Pi's OpenOCD fork doesn't, so match their documentation at +# https://www.raspberrypi.com/documentation/microcontrollers/debug-probe.html#debugging-with-swd +board_runner_args(openocd --cmd-pre-init "set_adapter_speed_if_not_set 5000") +board_runner_args(probe-rs "--chip=RP235x") +board_runner_args(jlink "--device=RP2350_M33_0") +board_runner_args(uf2 "--board-id=RP2350") + +# Default runner should be listed first +include(${ZEPHYR_BASE}/boards/common/uf2.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/probe-rs.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/dfrobot/beetle_rp2350/board.yml b/boards/dfrobot/beetle_rp2350/board.yml new file mode 100644 index 000000000000..955f63413927 --- /dev/null +++ b/boards/dfrobot/beetle_rp2350/board.yml @@ -0,0 +1,6 @@ +board: + name: beetle_rp2350 + full_name: Beetle RP2350 + vendor: dfrobot + socs: + - name: rp2350a diff --git a/boards/dfrobot/beetle_rp2350/doc/img/beetle_rp2350.webp b/boards/dfrobot/beetle_rp2350/doc/img/beetle_rp2350.webp new file mode 100644 index 000000000000..7a09e59d05ea Binary files /dev/null and b/boards/dfrobot/beetle_rp2350/doc/img/beetle_rp2350.webp differ diff --git a/boards/dfrobot/beetle_rp2350/doc/index.rst b/boards/dfrobot/beetle_rp2350/doc/index.rst new file mode 100644 index 000000000000..0ac3c101ebdb --- /dev/null +++ b/boards/dfrobot/beetle_rp2350/doc/index.rst @@ -0,0 +1,145 @@ +.. zephyr:board:: beetle_rp2350 + +Overview +******** + +The `DFRobot Beetle RP2350`_ board is based on the RP2350A microcontroller from Raspberry Pi Ltd. +The board has two 8-pin headers and a USB type C connector. + + +Hardware +******** + +- Microcontroller Raspberry Pi RP2350A, with a max frequency of 150 MHz +- Dual ARM Cortex M33 cores, and dual RISC-V Hazard3 cores. +- 520 kByte SRAM +- 2 Mbyte QSPI flash +- 9 GPIO pins +- 2 ADC pins +- I2C +- UART +- SPI +- USB type C connector +- Lithium battery charger +- Reset and boot buttons +- User LED + + +Default Zephyr Peripheral Mapping +================================= + ++---------------+--------+------------+ +| Description | Pin | Comments | ++===============+========+============+ +| User LED | GPIO25 | Alias led0 | ++---------------+--------+------------+ + + +GPIO header: + ++-------+--------+-----------------+ +| Label | Pin | Default pin mux | ++=======+========+=================+ +| 0 | GPIO0 | UART0 TX | ++-------+--------+-----------------+ +| 1 | GPIO1 | UART0 RX | ++-------+--------+-----------------+ +| 4 | GPIO4 | I2C0 SDA | ++-------+--------+-----------------+ +| 5 | GPIO5 | I2C0 SCL | ++-------+--------+-----------------+ +| 8 | GPIO8 | | ++-------+--------+-----------------+ +| 9 | GPIO9 | | ++-------+--------+-----------------+ +| 16 | GPIO16 | SPI0 MISO | ++-------+--------+-----------------+ +| 18 | GPIO18 | SPI0 SCK | ++-------+--------+-----------------+ +| 19 | GPIO19 | SPI0 MOSI | ++-------+--------+-----------------+ +| 26 | GPIO26 | ADC0 | ++-------+--------+-----------------+ +| 27 | GPIO27 | ADC1 | ++-------+--------+-----------------+ + +See also `pinout`_ and `schematic`_. + + +Supported Features +================== + +.. zephyr:board-supported-hw:: + + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +By default programming is done via the USB connector. Press and hold the BOOT button, and then +press the RST button, and the device will appear as a USB mass storage unit. +Building your application will result in a :file:`build/zephyr/zephyr.uf2` file. +Drag and drop the file to the USB mass storage unit, and the board will be reprogrammed. + +It is also possible to program and debug the board via the SWDIO and SWCLK pins in the DEBUG +connector. You must solder a 3-pin or 4-pin header to the back of the board in order to use +this feature. A separate programming hardware tool is required, and for example +the :command:`openocd` software is used. You might need to use Raspberry Pi's forked +version of OpenOCD. Typically the ``OPENOCD`` and ``OPENOCD_DEFAULT_PATH`` values should be +set when building, and the ``--runner openocd`` argument should be used when flashing. +For more details on programming RP2040-based and RP2350-based boards, +see :ref:`rpi_pico_programming_and_debugging`. + + +Flashing the M33 core +===================== + +To run the :zephyr:code-sample:`blinky` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky/ + :board: beetle_rp2350/rp2350a/m33 + :goals: build flash + +Try also the :zephyr:code-sample:`hello_world` and +:zephyr:code-sample:`adc_dt` samples. + +Use the shell to control the GPIO pins: + +.. zephyr-app-commands:: + :zephyr-app: samples/sensor/sensor_shell + :board: beetle_rp2350/rp2350a/m33 + :gen-args: -DCONFIG_GPIO=y -DCONFIG_GPIO_SHELL=y + :goals: build flash + +To set one of the GPIO pins high, use these commands in the shell: + +.. code-block:: shell + + gpio conf gpio0 8 o + gpio set gpio0 8 1 + + +Flashing the Hazard3 core +========================= + +The RP2350A microcontroller has two ARM M33 cores and two RISC-V Hazard3 cores. +To flash one of the Hazard3 cores, use the board argument ``beetle_rp2350/rp2350a/hazard3``. +The sample :zephyr:code-sample:`blinky` has been verified for this core. +Use the USB mass storage programming method described above. + + +References +********** + +.. target-notes:: + +.. _DFRobot Beetle RP2350: + https://www.dfrobot.com/product-2913.html + +.. _pinout: + https://wiki.dfrobot.com/SKU_DFR1188_Beetle_RP2350#target_4 + +.. _schematic: + https://dfimg.dfrobot.com/5d57611a3416442fa39bffca/wiki/f18e5f3a683e6d8a9c8582ac6f89b023.pdf diff --git a/boards/dfrobot/beetle_rp2350/support/openocd.cfg b/boards/dfrobot/beetle_rp2350/support/openocd.cfg new file mode 100644 index 000000000000..68211b3720f7 --- /dev/null +++ b/boards/dfrobot/beetle_rp2350/support/openocd.cfg @@ -0,0 +1,11 @@ +# Copyright (c) 2022 Tokita, Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +# Checking and set 'adapter speed'. +# Set the adapter speed, if unset, and given as an argument. +proc set_adapter_speed_if_not_set { speed } { + puts "checking adapter speed..." + if { [catch {adapter speed} ret] } { + adapter speed $speed + } +} diff --git a/boards/digilent/arty_a7/board.cmake b/boards/digilent/arty_a7/board.cmake index 0596bf31add8..022297517ba2 100644 --- a/boards/digilent/arty_a7/board.cmake +++ b/boards/digilent/arty_a7/board.cmake @@ -1,10 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 if(CONFIG_BOARD_ARTY_A7_DESIGNSTART_FPGA_CORTEX_M1) - board_runner_args(openocd "--use-elf" "--config=${BOARD_DIR}/support/openocd_arty_a7_arm_designstart_m1.cfg") + board_runner_args(openocd "--file-type=elf" "--config=${BOARD_DIR}/support/openocd_arty_a7_arm_designstart_m1.cfg") board_runner_args(jlink "--device=Cortex-M1" "--reset-after-load") elseif(CONFIG_BOARD_ARTY_A7_DESIGNSTART_FPGA_CORTEX_M3) - board_runner_args(openocd "--use-elf" "--config=${BOARD_DIR}/support/openocd_arty_a7_arm_designstart_m3.cfg") + board_runner_args(openocd "--file-type=elf" "--config=${BOARD_DIR}/support/openocd_arty_a7_arm_designstart_m3.cfg") board_runner_args(jlink "--device=Cortex-M3" "--reset-after-load") endif() diff --git a/boards/digilent/zybo/board.cmake b/boards/digilent/zybo/board.cmake index 0d3dae9262ac..214f538c821c 100644 --- a/boards/digilent/zybo/board.cmake +++ b/boards/digilent/zybo/board.cmake @@ -1,5 +1,5 @@ # Copyright (c) 2022 Henrik Brix Andersen # SPDX-License-Identifier: Apache-2.0 -board_runner_args(openocd "--use-elf" "--cmd-reset-halt" "halt") +board_runner_args(openocd "--file-type=elf" "--cmd-reset-halt" "halt") include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/doiting/dt_bl10_devkit/pre_dt_board.cmake b/boards/doiting/dt_bl10_devkit/pre_dt_board.cmake new file mode 100644 index 000000000000..c3a69b990ff0 --- /dev/null +++ b/boards/doiting/dt_bl10_devkit/pre_dt_board.cmake @@ -0,0 +1,4 @@ +# Copyright The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") diff --git a/boards/doiting/dt_xt_zb1_devkit/board.cmake b/boards/doiting/dt_xt_zb1_devkit/board.cmake index f5f09ea04022..f5e3396a9870 100644 --- a/boards/doiting/dt_xt_zb1_devkit/board.cmake +++ b/boards/doiting/dt_xt_zb1_devkit/board.cmake @@ -4,7 +4,7 @@ board_runner_args(openocd --cmd-pre-init "source [find bl70x.cfg]") -board_runner_args(openocd --use-elf --no-load --no-init) +board_runner_args(openocd --file-type=elf --no-load --no-init) board_runner_args(openocd --gdb-init "set mem inaccessible-by-default off") board_runner_args(openocd --gdb-init "set architecture riscv:rv32") board_runner_args(openocd --gdb-init "set remotetimeout 250") diff --git a/boards/doiting/dt_xt_zb1_devkit/pre_dt_board.cmake b/boards/doiting/dt_xt_zb1_devkit/pre_dt_board.cmake new file mode 100644 index 000000000000..c3a69b990ff0 --- /dev/null +++ b/boards/doiting/dt_xt_zb1_devkit/pre_dt_board.cmake @@ -0,0 +1,4 @@ +# Copyright The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") diff --git a/boards/dptechnics/walter/support/openocd.cfg b/boards/dptechnics/walter/support/openocd.cfg index 2f740b4a36ab..b45e13c53d01 100644 --- a/boards/dptechnics/walter/support/openocd.cfg +++ b/boards/dptechnics/walter/support/openocd.cfg @@ -1,5 +1,5 @@ -set ESP_RTOS none -set ESP32_ONLYCPU 1 +set ESP_RTOS Zephyr +set ESP_ONLYCPU 1 # Source the JTAG interface configuration file source [find interface/esp_usb_jtag.cfg] diff --git a/boards/dragino/lsn50/doc/index.rst b/boards/dragino/lsn50/doc/index.rst index d5981b51817b..9a92ad5826ff 100644 --- a/boards/dragino/lsn50/doc/index.rst +++ b/boards/dragino/lsn50/doc/index.rst @@ -6,7 +6,7 @@ Overview The Dragino LSN50 LoRA Sensor Node for IoT allows users to develop applications with LoraWAN connectivity via the HopeRF / SX1276/SX1278. Dragino LSN50 enables a wide diversity of applications by exploiting -low-power communication, ARM |reg| Cortex |reg|-M0 core-based +low-power communication, ARM® Cortex®-M0 core-based STM32L0 Series features. This kit provides: @@ -28,13 +28,13 @@ Hardware The STM32L072CZ SoC provides the following hardware IPs: - Ultra-low-power (down to 0.29 µA Standby mode and 93 uA/MHz run mode) -- Core: ARM |reg| 32-bit Cortex |reg|-M0+ CPU, frequency up to 32 MHz +- Core: ARM® 32-bit Cortex®-M0+ CPU, frequency up to 32 MHz - Clock Sources: - 1 to 32 MHz crystal oscillator - 32 kHz crystal oscillator for RTC (LSE) - - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) - - Internal low-power 37 kHz RC ( |plusminus| 5%) + - Internal 16 MHz factory-trimmed RC (±1%) + - Internal low-power 37 kHz RC (±5%) - Internal multispeed low-power 65 kHz to 4.2 MHz RC - RTC with HW calendar, alarms and calibration - Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors @@ -67,7 +67,7 @@ The STM32L072CZ SoC provides the following hardware IPs: - 7-channel DMA controller - True random number generator - CRC calculation unit, 96-bit unique ID -- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell™ More information about STM32L072CZ can be found here: diff --git a/boards/dragino/nbsn95/doc/index.rst b/boards/dragino/nbsn95/doc/index.rst index c99e6c87bdcd..4a5be2529a7a 100644 --- a/boards/dragino/nbsn95/doc/index.rst +++ b/boards/dragino/nbsn95/doc/index.rst @@ -6,15 +6,17 @@ Overview The Dragino NBSN95 NB-IoT Sensor Node for IoT allows users to develop applications with NB-IoT connectivity via the Quectel BC95-G. Dragino NBSN95 enables a wide diversity of applications by exploiting -low-power communication, ARM |reg| Cortex |reg|-M0 core-based +low-power communication, ARM® Cortex®-M0 core-based STM32L0 Series features. This kit provides: - STM32L072CZ MCU - Quectel BC95-G NB-IoT -- Expansion connectors: - - PMOD +- Expansion connectors + + - PMOD + - Li/SOCI2 Unchargable Battery - GPIOs exposed via screw terminals on the carrier board - Housing @@ -27,13 +29,13 @@ Hardware The STM32L072CZ SoC provides the following hardware IPs: - Ultra-low-power (down to 0.29 µA Standby mode and 93 uA/MHz run mode) -- Core: ARM |reg| 32-bit Cortex |reg|-M0+ CPU, frequency up to 32 MHz +- Core: ARM® 32-bit Cortex®-M0+ CPU, frequency up to 32 MHz - Clock Sources: - 1 to 32 MHz crystal oscillator - 32 kHz crystal oscillator for RTC (LSE) - - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) - - Internal low-power 37 kHz RC ( |plusminus| 5%) + - Internal 16 MHz factory-trimmed RC (±1%) + - Internal low-power 37 kHz RC (±5%) - Internal multispeed low-power 65 kHz to 4.2 MHz RC - RTC with HW calendar, alarms and calibration - Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors @@ -66,7 +68,7 @@ The STM32L072CZ SoC provides the following hardware IPs: - 7-channel DMA controller - True random number generator - CRC calculation unit, 96-bit unique ID -- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell™ More information about STM32L072CZ can be found here: diff --git a/boards/ebyte/e73_tbb/ebyte_e73_tbb_nrf52832.dts b/boards/ebyte/e73_tbb/ebyte_e73_tbb_nrf52832.dts index cb06d4ef06c2..7ccae16ec375 100644 --- a/boards/ebyte/e73_tbb/ebyte_e73_tbb_nrf52832.dts +++ b/boards/ebyte/e73_tbb/ebyte_e73_tbb_nrf52832.dts @@ -121,12 +121,12 @@ slot0_partition: partition@c000 { label = "image-0"; - reg = <0x0000C000 0x32000>; + reg = <0x0000c000 0x32000>; }; slot1_partition: partition@3e000 { label = "image-1"; - reg = <0x0003E000 0x32000>; + reg = <0x0003e000 0x32000>; }; scratch_partition: partition@70000 { diff --git a/boards/elan/32f967_dv/32f967_dv.dts b/boards/elan/32f967_dv/32f967_dv.dts new file mode 100644 index 000000000000..bac745b10f65 --- /dev/null +++ b/boards/elan/32f967_dv/32f967_dv.dts @@ -0,0 +1,120 @@ +/* + * Copyright (c) 2024 ELAN Microelectronics Corp. + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include + +/ { + model = "ELAN EM32F967 Development Board"; + compatible = "elan,em32f967_dv"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash-controller = &em32_flash_controller; + zephyr,flash = &flash0; + }; +}; + +&clk_ahb { + status = "okay"; +}; + +&clk_apb { + clocks = <&clk_ahb>; + status = "okay"; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(272)>; +}; + +&spi2 { + status = "disabled"; + pinctrl-0 = <&spi2_sck_pb5 &spi2_miso_pb6 &spi2_mosi_pb7>; + pinctrl-names = "default"; + cs-gpios = <&gpiob 4 GPIO_ACTIVE_LOW>; +}; + +&uart1 { + status = "disabled"; + current-speed = <115200>; + pinctrl-0 = <&uart1_rx_pa1 &uart1_tx_pa2>; + pinctrl-names = "default"; +}; + +&em32_flash_controller { + status = "okay"; +}; + +&gpioa { + status = "disabled"; +}; + +&gpiob { + status = "disabled"; +}; + +zephyr_udc0: &usbd { + status = "disabled"; +}; + +&uid { + status = "disabled"; +}; + +&bbram0 { + status = "disabled"; +}; + +&trng0 { + status = "disabled"; +}; + +&wdt0 { + status = "disabled"; +}; + +&crypto0 { + status = "disabled"; +}; + +/* Enable Timer controllers */ +&timer1 { + status = "disabled"; +}; + +&timer2 { + status = "disabled"; +}; + +/* Enable RTC */ +&rtc0 { + status = "disabled"; +}; + +/* Enable PWM Controller - PWMB N output on PA3 */ +&pwm0 { + status = "disabled"; + use-port-a; /* Use Port A pins (PWM_S=0) */ + output-type = <1>; /* N output only */ + pinctrl-0 = <&pwmb_pa3_n>; + pinctrl-names = "default"; +}; + +&sysctrl { + status = "disabled"; +}; + +&pwrctrl { + status = "disabled"; +}; + +&clkctrl { + status = "disabled"; +}; diff --git a/boards/elan/32f967_dv/32f967_dv.yaml b/boards/elan/32f967_dv/32f967_dv.yaml new file mode 100644 index 000000000000..e2db179d3bd7 --- /dev/null +++ b/boards/elan/32f967_dv/32f967_dv.yaml @@ -0,0 +1,12 @@ +identifier: 32f967_dv +name: ELAN EM32F967 dv Board +vendor: elan +type: mcu +arch: arm +toolchain: + - zephyr +testing: + default: false +supported: [] +ram: 272 +flash: 536 diff --git a/boards/elan/32f967_dv/Kconfig.32f967_dv b/boards/elan/32f967_dv/Kconfig.32f967_dv new file mode 100644 index 000000000000..509d09cbcdb3 --- /dev/null +++ b/boards/elan/32f967_dv/Kconfig.32f967_dv @@ -0,0 +1,6 @@ +# Copyright (c) 2025 ELAN Microelectronics Corp. +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_32F967_DV + select SOC_EM32F967 diff --git a/boards/elan/32f967_dv/Kconfig.defconfig b/boards/elan/32f967_dv/Kconfig.defconfig new file mode 100644 index 000000000000..3b4d4df8684b --- /dev/null +++ b/boards/elan/32f967_dv/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2025 ELAN Microelectronics Corp. +# +# SPDX-License-Identifier: Apache-2.0 + +config UART_USE_RUNTIME_CONFIGURE + default n + +config UART_INTERRUPT_DRIVEN + default n + +config UART_ASYNC_API + default n diff --git a/boards/elan/32f967_dv/board.cmake b/boards/elan/32f967_dv/board.cmake new file mode 100644 index 000000000000..6b01bab2aeea --- /dev/null +++ b/boards/elan/32f967_dv/board.cmake @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_set_flasher_ifnset(misc-flasher) +board_finalize_runner_args(misc-flasher) diff --git a/boards/elan/32f967_dv/board.yml b/boards/elan/32f967_dv/board.yml new file mode 100644 index 000000000000..6c4cc335df5f --- /dev/null +++ b/boards/elan/32f967_dv/board.yml @@ -0,0 +1,6 @@ +board: + name: 32f967_dv + full_name: ELAN EM32F967 + vendor: elan + socs: + - name: em32f967 diff --git a/boards/elan/32f967_dv/doc/32f967_dv.webp b/boards/elan/32f967_dv/doc/32f967_dv.webp new file mode 100644 index 000000000000..b35dc22b19d5 Binary files /dev/null and b/boards/elan/32f967_dv/doc/32f967_dv.webp differ diff --git a/boards/elan/32f967_dv/doc/index.rst b/boards/elan/32f967_dv/doc/index.rst new file mode 100644 index 000000000000..26c1cd5e0936 --- /dev/null +++ b/boards/elan/32f967_dv/doc/index.rst @@ -0,0 +1,84 @@ +.. zephyr:board:: 32f967_dv + +Elan 32f967_dv +############## + +Overview +******** + +The Elan 32f967_dv is a B2B development board based on the Elan em32f967 +SoC (ARM Cortex-M4). This board is used to validate the initial SoC +integration with Zephyr. + +Hardware +******** + +The platform provides the following hardware components: + +- SoC: Elan em32f967 (ARM Cortex-M4) +- Maximum CPU frequency: 96 MHz +- Embedded Flash: 536 KB +- Embedded RAM: 272 KB +- UART (debug via soldered jump wires, no dedicated connector) +- SPI +- GPIO +- PWM +- USB (used for firmware flashing and application communication) +- Watchdog Timer (WDT) +- Backup domain registers (accessed via Zephyr BBRAM interface) +- True Random Number Generator (TRNG) +- Hardware Crypto Engine +- Timer +- Real-Time Clock (RTC) + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Connections and IOs +=================== + +- **UART_1 TX/RX** : PA2 / PA1 +- **SPI_2 NSS/SCK/MISO/MOSI** : PB4 / PB5 / PB6 / PB7 +- **PWM_0 LED** : PA3 + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +This board does not use a standard flashing interface such as J-Link or OpenOCD. + +Flashing +======== + +The flashing tool is distributed only to Elan's customers for production and +evaluation purposes. It is not publicly available. + +At this stage, the Zephyr ``west flash`` command is not supported. + +You can build applications in the usual way. Here is an example for +the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: 32f967_dv + :goals: build + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: 32f967_dv + :goals: debug + +References +********** + +Documentation for this board and the Elan em32f967 SoC is available to Elan customers. +Please contact Elan for datasheets, technical reference manuals, and tooling information. diff --git a/boards/elan/index.rst b/boards/elan/index.rst new file mode 100644 index 000000000000..acb4549aa9f3 --- /dev/null +++ b/boards/elan/index.rst @@ -0,0 +1,10 @@ +.. _boards-elan: + +Elan Microelectronics Corp. +########################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/element14/warp7/warp7-pinctrl.dtsi b/boards/element14/warp7/warp7-pinctrl.dtsi index 3aab4f71973d..9908742f3e4f 100644 --- a/boards/element14/warp7/warp7-pinctrl.dtsi +++ b/boards/element14/warp7/warp7-pinctrl.dtsi @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include #include &pinctrl { diff --git a/boards/element14/warp7/warp7_mcimx7d_m4.dts b/boards/element14/warp7/warp7_mcimx7d_m4.dts index 2ae4e4b7676b..6c208681b94f 100644 --- a/boards/element14/warp7/warp7_mcimx7d_m4.dts +++ b/boards/element14/warp7/warp7_mcimx7d_m4.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "warp7-pinctrl.dtsi" #include diff --git a/boards/embedsky/tq_h503a/doc/index.rst b/boards/embedsky/tq_h503a/doc/index.rst index 649fe5a7d26d..2a7cd864bdc4 100644 --- a/boards/embedsky/tq_h503a/doc/index.rst +++ b/boards/embedsky/tq_h503a/doc/index.rst @@ -3,7 +3,7 @@ Overview ******** -The Embedsky TQ-H503A board is an extremely low cost and bare-bones development board featuring an ARM |reg| Cortex |reg|-M33 core-based +The Embedsky TQ-H503A board is an extremely low cost and bare-bones development board featuring an ARM® Cortex®-M33 core-based STM32H503CBT6 microcontroller, see `STM32H503CB website`_. This is the 48-pin variant of the STM32H503x series, see `STM32H503x reference manual`_. @@ -20,10 +20,10 @@ Hardware ******** The STM32H503CB belongs to the high-performance microcontroller family -(STM32H5 series) based on the high-performance Arm |reg| Cortex |reg|-M33 32-bit +(STM32H5 series) based on the high-performance Arm® Cortex®-M33 32-bit RISC core. They operate at frequency of up to 250 MHz. -- Core: Arm |reg| Cortex |reg|-M33 CPU with FPU, MPU, 375 DMIPS (Dhrystone 2.1), +- Core: Arm® Cortex®-M33 CPU with FPU, MPU, 375 DMIPS (Dhrystone 2.1), and DSP instructions - ART Accelerator @@ -62,7 +62,7 @@ RISC core. They operate at frequency of up to 250 MHz. - 16x communication interfaces - - 2x I2Cs FM + interfaces (SMBus/PMBus |reg|) + - 2x I2Cs FM + interfaces (SMBus/PMBus®) - 2x I3Cs shared with I2C - 3x USARTs (ISO7816 interface, LIN, IrDA, modem control) - 1x LPUART diff --git a/boards/enjoydigital/litex_vexriscv/litex_vexriscv.dts b/boards/enjoydigital/litex_vexriscv/litex_vexriscv.dts index 4d20ff909e0e..8cc07204745d 100644 --- a/boards/enjoydigital/litex_vexriscv/litex_vexriscv.dts +++ b/boards/enjoydigital/litex_vexriscv/litex_vexriscv.dts @@ -297,9 +297,8 @@ gpio_out: gpio@e0005800 { compatible = "litex,gpio"; reg = <0xe0005800 0x4>; - reg-names = "control"; + reg-names = "out"; ngpios = <4>; - port-is-output; status = "okay"; gpio-controller; #gpio-cells = <2>; @@ -314,11 +313,11 @@ <0xe0006014 0x4>; interrupt-parent = <&intc0>; interrupts = <4 2>; - reg-names = "base", - "irq_mode", - "irq_edge", - "irq_pend", - "irq_en"; + reg-names = "in", + "mode", + "edge", + "ev_pending", + "ev_enable"; ngpios = <4>; status = "okay"; gpio-controller; diff --git a/boards/espressif/common/openocd-debugging.rst b/boards/espressif/common/openocd-debugging.rst index 71d75389eb79..7ec60739908d 100644 --- a/boards/espressif/common/openocd-debugging.rst +++ b/boards/espressif/common/openocd-debugging.rst @@ -2,34 +2,50 @@ .. espressif-openocd-debugging -OpenOCD -======= +OpenOCD Debugging +================= -As with much custom hardware, the ESP32 modules require patches to -OpenOCD that are not upstreamed yet. Espressif maintains their own fork of -the project. The custom OpenOCD can be obtained at `OpenOCD for ESP32`_. +Espressif chips require a custom OpenOCD build with ESP32-specific patches. +Download the latest release from `OpenOCD for ESP32`_. -The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the -``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` -parameter when building. +For detailed JTAG setup instructions, see `JTAG debugging for ESP32`_. -Further documentation can be obtained from the SoC vendor in `JTAG debugging for ESP32`_. +Zephyr Thread Awareness +----------------------- -Here is an example for building the :zephyr:code-sample:`hello_world` application. +OpenOCD supports Zephyr RTOS thread awareness, allowing GDB to: + +- List all threads with ``info threads`` +- Display thread names, priorities, and states +- Switch between thread contexts +- Show backtraces for any thread + +**Requirements:** + +- `OpenOCD ESP32 v0.12.0-esp32-20251215`_ or later +- Build with ``CONFIG_DEBUG_THREAD_INFO=y`` + +**Example:** .. zephyr-app-commands:: :zephyr-app: samples/hello_world :board: - :goals: build flash - :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= + :goals: debug + :gen-args: -DCONFIG_DEBUG_THREAD_INFO=y -DOPENOCD= -DOPENOCD_DEFAULT_PATH= + +Using a Custom OpenOCD +---------------------- -You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. +The Zephyr SDK includes a bundled OpenOCD, but it may not have ESP32 support. +To use the Espressif OpenOCD, specify the path when building: .. zephyr-app-commands:: :zephyr-app: samples/hello_world :board: :goals: debug + :gen-args: -DOPENOCD=/path/to/openocd -DOPENOCD_DEFAULT_PATH=/path/to/openocd/scripts .. _`OpenOCD for ESP32`: https://github.com/espressif/openocd-esp32/releases +.. _`OpenOCD ESP32 v0.12.0-esp32-20251215`: https://github.com/espressif/openocd-esp32/releases/tag/v0.12.0-esp32-20251215 .. _`JTAG debugging for ESP32`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/jtag-debugging/index.html diff --git a/boards/espressif/esp32_devkitc/support/openocd.cfg b/boards/espressif/esp32_devkitc/support/openocd.cfg index 338e6e4e6eae..41411e37140e 100644 --- a/boards/espressif/esp32_devkitc/support/openocd.cfg +++ b/boards/espressif/esp32_devkitc/support/openocd.cfg @@ -1,5 +1,5 @@ -set ESP_RTOS none -set ESP32_ONLYCPU 1 +set ESP_RTOS Zephyr +set ESP_ONLYCPU 1 source [find interface/ftdi/esp32_devkitj_v1.cfg] source [find target/esp32.cfg] diff --git a/boards/espressif/esp32_ethernet_kit/support/openocd.cfg b/boards/espressif/esp32_ethernet_kit/support/openocd.cfg index 338e6e4e6eae..41411e37140e 100644 --- a/boards/espressif/esp32_ethernet_kit/support/openocd.cfg +++ b/boards/espressif/esp32_ethernet_kit/support/openocd.cfg @@ -1,5 +1,5 @@ -set ESP_RTOS none -set ESP32_ONLYCPU 1 +set ESP_RTOS Zephyr +set ESP_ONLYCPU 1 source [find interface/ftdi/esp32_devkitj_v1.cfg] source [find target/esp32.cfg] diff --git a/boards/espressif/esp32c3_devkitc/support/openocd.cfg b/boards/espressif/esp32c3_devkitc/support/openocd.cfg index 92a792fecb8e..6aed93913348 100644 --- a/boards/espressif/esp32c3_devkitc/support/openocd.cfg +++ b/boards/espressif/esp32c3_devkitc/support/openocd.cfg @@ -1,4 +1,4 @@ -set ESP_RTOS none +set ESP_RTOS Zephyr # ESP32C3 has built-in JTAG interface over USB port in pins GPIO18/GPIO19 (D-/D+). # Uncomment the line below to enable USB debugging. diff --git a/boards/espressif/esp32c3_devkitm/support/openocd.cfg b/boards/espressif/esp32c3_devkitm/support/openocd.cfg index 92a792fecb8e..6aed93913348 100644 --- a/boards/espressif/esp32c3_devkitm/support/openocd.cfg +++ b/boards/espressif/esp32c3_devkitm/support/openocd.cfg @@ -1,4 +1,4 @@ -set ESP_RTOS none +set ESP_RTOS Zephyr # ESP32C3 has built-in JTAG interface over USB port in pins GPIO18/GPIO19 (D-/D+). # Uncomment the line below to enable USB debugging. diff --git a/boards/espressif/esp32c3_rust/support/openocd.cfg b/boards/espressif/esp32c3_rust/support/openocd.cfg index e846c967fb1c..f5fa2c4906b3 100644 --- a/boards/espressif/esp32c3_rust/support/openocd.cfg +++ b/boards/espressif/esp32c3_rust/support/openocd.cfg @@ -1,4 +1,4 @@ -set ESP_RTOS none +set ESP_RTOS Zephyr # ESP32C3 has built-in JTAG interface over USB port in pins GPIO18/GPIO19 (D-/D+). # Uncomment the line below to enable USB debugging. diff --git a/boards/espressif/esp32c6_devkitc/support/openocd.cfg b/boards/espressif/esp32c6_devkitc/support/openocd.cfg index d86a5517a4ca..29d5fac25c5a 100644 --- a/boards/espressif/esp32c6_devkitc/support/openocd.cfg +++ b/boards/espressif/esp32c6_devkitc/support/openocd.cfg @@ -1,4 +1,4 @@ # ESP32C6 has built-in JTAG interface over USB port in pins GPIO13/GPIO12 (D-/D+). -set ESP_RTOS none +set ESP_RTOS Zephyr source [find board/esp32c6-builtin.cfg] diff --git a/boards/espressif/esp32h2_devkitm/support/openocd.cfg b/boards/espressif/esp32h2_devkitm/support/openocd.cfg index 5dac2bad03f9..19c9b79ef7e6 100644 --- a/boards/espressif/esp32h2_devkitm/support/openocd.cfg +++ b/boards/espressif/esp32h2_devkitm/support/openocd.cfg @@ -1,4 +1,4 @@ # ESP32H2 has built-in JTAG interface over USB port in pins GPIO26/GPIO27 (D-/D+). -set ESP_RTOS none +set ESP_RTOS Zephyr source [find board/esp32h2-builtin.cfg] diff --git a/boards/espressif/esp32s2_devkitc/support/openocd.cfg b/boards/espressif/esp32s2_devkitc/support/openocd.cfg index f75d53b0b34c..6b71dc41b12f 100644 --- a/boards/espressif/esp32s2_devkitc/support/openocd.cfg +++ b/boards/espressif/esp32s2_devkitc/support/openocd.cfg @@ -1,4 +1,4 @@ -set ESP_RTOS none +set ESP_RTOS Zephyr source [find interface/ftdi/esp32s2_kaluga_v1.cfg] source [find target/esp32s2.cfg] diff --git a/boards/espressif/esp32s2_saola/support/openocd.cfg b/boards/espressif/esp32s2_saola/support/openocd.cfg index f75d53b0b34c..6b71dc41b12f 100644 --- a/boards/espressif/esp32s2_saola/support/openocd.cfg +++ b/boards/espressif/esp32s2_saola/support/openocd.cfg @@ -1,4 +1,4 @@ -set ESP_RTOS none +set ESP_RTOS Zephyr source [find interface/ftdi/esp32s2_kaluga_v1.cfg] source [find target/esp32s2.cfg] diff --git a/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_procpu.dts b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_procpu.dts index 8c1b137d26d6..846d2220e769 100644 --- a/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_procpu.dts +++ b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_procpu.dts @@ -18,6 +18,8 @@ aliases { i2c-0 = &i2c0; watchdog0 = &wdt0; + uart-0 = &uart0; + sw0 = &button0; }; chosen { @@ -29,11 +31,6 @@ zephyr,bt-hci = &esp32_bt_hci; }; - aliases { - uart-0 = &uart0; - sw0 = &button0; - }; - buttons { compatible = "gpio-keys"; diff --git a/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_procpu.yaml b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_procpu.yaml index 261ac673ae71..68853ee5caf0 100644 --- a/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_procpu.yaml +++ b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_procpu.yaml @@ -17,6 +17,7 @@ supported: - pwm - dma - input + - video - crypto - retained_mem vendor: espressif diff --git a/boards/espressif/esp32s3_devkitc/support/openocd.cfg b/boards/espressif/esp32s3_devkitc/support/openocd.cfg index 2f740b4a36ab..421b173cbd4e 100644 --- a/boards/espressif/esp32s3_devkitc/support/openocd.cfg +++ b/boards/espressif/esp32s3_devkitc/support/openocd.cfg @@ -1,7 +1,5 @@ -set ESP_RTOS none -set ESP32_ONLYCPU 1 +set ESP_RTOS Zephyr +set ESP_ONLYCPU 1 -# Source the JTAG interface configuration file source [find interface/esp_usb_jtag.cfg] -# Source the ESP32-S3 configuration file source [find target/esp32s3.cfg] diff --git a/boards/espressif/esp32s3_devkitm/Kconfig b/boards/espressif/esp32s3_devkitm/Kconfig deleted file mode 100644 index 84e633e5af22..000000000000 --- a/boards/espressif/esp32s3_devkitm/Kconfig +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 4096 if BOARD_ESP32S3_DEVKITM_ESP32S3_PROCPU - default 256 if BOARD_ESP32S3_DEVKITM_ESP32S3_APPCPU diff --git a/boards/espressif/esp32s3_devkitm/Kconfig.esp32s3_devkitm b/boards/espressif/esp32s3_devkitm/Kconfig.esp32s3_devkitm deleted file mode 100644 index b574cf3ab065..000000000000 --- a/boards/espressif/esp32s3_devkitm/Kconfig.esp32s3_devkitm +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ESP32S3_DEVKITM - select SOC_ESP32S3_MINI_N8 - select SOC_ESP32S3_PROCPU if BOARD_ESP32S3_DEVKITM_ESP32S3_PROCPU - select SOC_ESP32S3_APPCPU if BOARD_ESP32S3_DEVKITM_ESP32S3_APPCPU diff --git a/boards/espressif/esp32s3_devkitm/Kconfig.sysbuild b/boards/espressif/esp32s3_devkitm/Kconfig.sysbuild deleted file mode 100644 index 3a2d17ac5cfd..000000000000 --- a/boards/espressif/esp32s3_devkitm/Kconfig.sysbuild +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -choice BOOTLOADER - default BOOTLOADER_MCUBOOT -endchoice - -choice BOOT_SIGNATURE_TYPE - default BOOT_SIGNATURE_TYPE_NONE -endchoice diff --git a/boards/espressif/esp32s3_devkitm/board.yml b/boards/espressif/esp32s3_devkitm/board.yml deleted file mode 100644 index 0e4abbade2e7..000000000000 --- a/boards/espressif/esp32s3_devkitm/board.yml +++ /dev/null @@ -1,6 +0,0 @@ -board: - name: esp32s3_devkitm - full_name: ESP32-S3-DevKitM - vendor: espressif - socs: - - name: esp32s3 diff --git a/boards/espressif/esp32s3_devkitm/doc/img/esp32s3_devkitm.webp b/boards/espressif/esp32s3_devkitm/doc/img/esp32s3_devkitm.webp deleted file mode 100644 index aa3708f1720c..000000000000 Binary files a/boards/espressif/esp32s3_devkitm/doc/img/esp32s3_devkitm.webp and /dev/null differ diff --git a/boards/espressif/esp32s3_devkitm/doc/index.rst b/boards/espressif/esp32s3_devkitm/doc/index.rst deleted file mode 100644 index ccd6d363ce29..000000000000 --- a/boards/espressif/esp32s3_devkitm/doc/index.rst +++ /dev/null @@ -1,49 +0,0 @@ -.. zephyr:board:: esp32s3_devkitm - -Overview -******** - -The ESP32-S3-DevKitM is an entry-level development board equipped with either ESP32-S3-MINI-1 -or ESP32-S3-MINI-1U, a module named for its small size. This board integrates complete Wi-Fi -and Bluetooth Low Energy functions. For more information, check `ESP32-S3-DevKitM User Guide`_. - -Hardware -******** - -.. include:: ../../../espressif/common/soc-esp32s3-features.rst - :start-after: espressif-soc-esp32s3-features - -Supported Features -================== - -.. zephyr:board-supported-hw:: - -System Requirements -******************* - -.. include:: ../../../espressif/common/system-requirements.rst - :start-after: espressif-system-requirements - -Programming and Debugging -************************* - -.. zephyr:board-supported-runners:: - -.. include:: ../../../espressif/common/building-flashing.rst - :start-after: espressif-building-flashing - -.. include:: ../../../espressif/common/board-variants.rst - :start-after: espressif-board-variants - -Debugging -========= - -.. include:: ../../../espressif/common/openocd-debugging.rst - :start-after: espressif-openocd-debugging - -References -********** - -.. target-notes:: - -.. _`ESP32-S3-DevKitM User Guide`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/hw-reference/esp32s3/user-guide-devkitm-1.html diff --git a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm-pinctrl.dtsi b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm-pinctrl.dtsi deleted file mode 100644 index ea198b484ad0..000000000000 --- a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm-pinctrl.dtsi +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include - -&pinctrl { - uart0_default: uart0_default { - group1 { - pinmux = ; - output-high; - }; - - group2 { - pinmux = ; - bias-pull-up; - }; - }; - - uart1_default: uart1_default { - group1 { - pinmux = ; - output-high; - }; - - group2 { - pinmux = ; - bias-pull-up; - }; - }; - - i2c0_default: i2c0_default { - group1 { - pinmux = , - ; - bias-pull-up; - drive-open-drain; - output-high; - }; - }; - - i2c1_default: i2c1_default { - group1 { - pinmux = , - ; - bias-pull-up; - drive-open-drain; - output-high; - }; - }; - - i2s0_default: i2s0_default { - group1 { - pinmux = , - , - , - , - ; - }; - }; - - i2s1_default: i2s1_default { - group1 { - pinmux = , - , - , - , - ; - }; - }; - - spim2_default: spim2_default { - group1 { - pinmux = , - , - ; - }; - - group2 { - pinmux = ; - output-low; - }; - }; - - spim3_default: spim3_default { - group1 { - pinmux = , - , - ; - }; - - group2 { - pinmux = ; - output-low; - }; - }; - - twai_default: twai_default { - group1 { - pinmux = , - ; - }; - }; -}; diff --git a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_appcpu.dts b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_appcpu.dts deleted file mode 100644 index 08a9e005be31..000000000000 --- a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_appcpu.dts +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - */ -/dts-v1/; - -#include -#include -#include "esp32s3_devkitm-pinctrl.dtsi" - -/ { - model = "Espressif ESP32S3-DevkitM APPCPU"; - compatible = "espressif,esp32s3"; - - chosen { - zephyr,sram = &sram1; - zephyr,ipc_shm = &shm0; - zephyr,ipc = &ipm0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_appcpu_partition; - }; -}; - -&trng0 { - status = "okay"; -}; - -&ipm0 { - status = "okay"; -}; diff --git a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_appcpu.yaml b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_appcpu.yaml deleted file mode 100644 index 7af60717bd44..000000000000 --- a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_appcpu.yaml +++ /dev/null @@ -1,27 +0,0 @@ -identifier: esp32s3_devkitm/esp32s3/appcpu -name: ESP32-S3 DevKitM APPCPU -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - uart -testing: - ignore_tags: - - net - - bluetooth - - flash - - cpp - - posix - - watchdog - - logging - - kernel - - pm - - gpio - - crypto - - eeprom - - heap - - cmsis_rtos - - jwt - - zdsp -vendor: espressif diff --git a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu.dts b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu.dts deleted file mode 100644 index 28a8f6456eec..000000000000 --- a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu.dts +++ /dev/null @@ -1,156 +0,0 @@ -/* - * Copyright (c) 2022-2025 Espressif Systems (Shanghai) Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - */ -/dts-v1/; - -#include -#include -#include -#include -#include "esp32s3_devkitm-pinctrl.dtsi" - -/ { - model = "Espressif ESP32S3-DevkitM PROCPU"; - compatible = "espressif,esp32s3"; - - aliases { - i2c-0 = &i2c0; - watchdog0 = &wdt0; - }; - - chosen { - zephyr,sram = &sram1; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - zephyr,bt-hci = &esp32_bt_hci; - }; - - aliases { - uart-0 = &uart0; - sw0 = &button0; - }; - - buttons { - compatible = "gpio-keys"; - - button0: button_0 { - gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "BOOT Button"; - zephyr,code = ; - }; - }; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-names = "default"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&touch { - debounce-interval-ms = <30>; - href-microvolt = <2700000>; - lref-microvolt = <500000>; - href-atten-microvolt = <1000000>; - filter-mode = ; - filter-debounce-cnt = <1>; - filter-noise-thr = ; - filter-jitter-step = <4>; - filter-smooth-level = ; -}; - -&i2c0 { - clock-frequency = ; - pinctrl-0 = <&i2c0_default>; - pinctrl-names = "default"; -}; - -&i2c1 { - clock-frequency = ; - pinctrl-0 = <&i2c1_default>; - pinctrl-names = "default"; -}; - -&i2s0 { - pinctrl-0 = <&i2s0_default>; - pinctrl-names = "default"; -}; - -&i2s1 { - pinctrl-0 = <&i2s1_default>; - pinctrl-names = "default"; -}; - -&spi2 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim2_default>; - pinctrl-names = "default"; -}; - -&spi3 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim3_default>; - pinctrl-names = "default"; -}; - -&twai { - pinctrl-0 = <&twai_default>; - pinctrl-names = "default"; -}; - -&timer0 { - status = "disabled"; -}; - -&timer1 { - status = "disabled"; -}; - -&timer2 { - status = "disabled"; -}; - -&timer3 { - status = "disabled"; -}; - -&wdt0 { - status = "okay"; -}; - -&trng0 { - status = "okay"; -}; - -&usb_serial { - status = "disabled"; -}; - -&esp32_bt_hci { - status = "okay"; -}; - -&wifi { - status = "okay"; -}; - -zephyr_udc0: &usb_otg { - status = "okay"; -}; diff --git a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu.yaml b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu.yaml deleted file mode 100644 index 1a98b86d4ddd..000000000000 --- a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu.yaml +++ /dev/null @@ -1,23 +0,0 @@ -identifier: esp32s3_devkitm/esp32s3/procpu -name: ESP32-S3 DevKitM PROCPU -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - gpio - - uart - - i2c - - i2s - - spi - - can - - counter - - watchdog - - entropy - - pwm - - dma - - input - - video - - crypto - - retained_mem -vendor: espressif diff --git a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu_defconfig b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu_defconfig deleted file mode 100644 index d8fbaa879257..000000000000 --- a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu_defconfig +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_GPIO=y -CONFIG_CLOCK_CONTROL=y diff --git a/boards/espressif/esp32s3_devkitm/support/openocd.cfg b/boards/espressif/esp32s3_devkitm/support/openocd.cfg deleted file mode 100644 index 2f740b4a36ab..000000000000 --- a/boards/espressif/esp32s3_devkitm/support/openocd.cfg +++ /dev/null @@ -1,7 +0,0 @@ -set ESP_RTOS none -set ESP32_ONLYCPU 1 - -# Source the JTAG interface configuration file -source [find interface/esp_usb_jtag.cfg] -# Source the ESP32-S3 configuration file -source [find target/esp32s3.cfg] diff --git a/boards/espressif/esp32s3_eye/esp32s3_eye_procpu.dts b/boards/espressif/esp32s3_eye/esp32s3_eye_procpu.dts index 1530a9846b68..9d9e0f6d3434 100644 --- a/boards/espressif/esp32s3_eye/esp32s3_eye_procpu.dts +++ b/boards/espressif/esp32s3_eye/esp32s3_eye_procpu.dts @@ -32,7 +32,7 @@ zephyr,code-partition = &slot0_partition; zephyr,bt-hci = &esp32_bt_hci; zephyr,display = &st7789v; - zephyr,camera = &lcd_cam; + zephyr,camera = &lcd_cam_dvp; zephyr,sdhc = &sdhc0; }; @@ -109,10 +109,10 @@ porch-param = [0c 0c 00 33 33]; cmd2en-param = [5a 69 02 01]; pwctrl1-param = [a4 a1]; - pvgam-param = [D0 04 0D 11 13 2B 3F 54 4C 18 0D 0B 1F 23]; - nvgam-param = [D0 04 0C 11 13 2C 3F 44 51 2F 1F 1F 20 23]; - ram-param = [00 F0]; - rgb-param = [CD 08 14]; + pvgam-param = [d0 04 0d 11 13 2b 3f 54 4c 18 0d 0b 1f 23]; + nvgam-param = [d0 04 0c 11 13 2c 3f 44 51 2f 1f 1f 20 23]; + ram-param = [00 f0]; + rgb-param = [cd 08 14]; mipi-mode = "MIPI_DBI_MODE_SPI_4WIRE"; }; }; @@ -144,12 +144,14 @@ &lcd_cam { status = "okay"; - cam-clk = <10000000>; pinctrl-0 = <&lcd_cam_default>; pinctrl-names = "default"; +}; + +&lcd_cam_dvp { + status = "okay"; + cam-clk = <10000000>; source = <&ov2640>; - dmas = <&dma 2>; - dma-names = "rx"; port { dvp_ep_in: endpoint { diff --git a/boards/espressif/esp32s3_eye/support/openocd.cfg b/boards/espressif/esp32s3_eye/support/openocd.cfg index 2f740b4a36ab..421b173cbd4e 100644 --- a/boards/espressif/esp32s3_eye/support/openocd.cfg +++ b/boards/espressif/esp32s3_eye/support/openocd.cfg @@ -1,7 +1,5 @@ -set ESP_RTOS none -set ESP32_ONLYCPU 1 +set ESP_RTOS Zephyr +set ESP_ONLYCPU 1 -# Source the JTAG interface configuration file source [find interface/esp_usb_jtag.cfg] -# Source the ESP32-S3 configuration file source [find target/esp32s3.cfg] diff --git a/boards/espressif/esp8684_devkitm/support/openocd.cfg b/boards/espressif/esp8684_devkitm/support/openocd.cfg index 93209701b692..a024cf396087 100644 --- a/boards/espressif/esp8684_devkitm/support/openocd.cfg +++ b/boards/espressif/esp8684_devkitm/support/openocd.cfg @@ -1,4 +1,4 @@ -set ESP_RTOS none +set ESP_RTOS Zephyr # Use external JTAG interface, such as ESP-Prog source [find interface/ftdi/esp32_devkitj_v1.cfg] diff --git a/boards/espressif/esp_wrover_kit/support/openocd.cfg b/boards/espressif/esp_wrover_kit/support/openocd.cfg index 338e6e4e6eae..41411e37140e 100644 --- a/boards/espressif/esp_wrover_kit/support/openocd.cfg +++ b/boards/espressif/esp_wrover_kit/support/openocd.cfg @@ -1,5 +1,5 @@ -set ESP_RTOS none -set ESP32_ONLYCPU 1 +set ESP_RTOS Zephyr +set ESP_ONLYCPU 1 source [find interface/ftdi/esp32_devkitj_v1.cfg] source [find target/esp32.cfg] diff --git a/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_common.dtsi b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_common.dtsi index 21cecb635565..3389ad997124 100644 --- a/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_common.dtsi +++ b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_common.dtsi @@ -6,6 +6,7 @@ */ #include "bl5340_dvk_nrf5340_cpuapp_common-pinctrl.dtsi" #include +#include / { chosen { @@ -122,6 +123,7 @@ rotation = <270>; width = <320>; height = <240>; + pixel-format = ; }; }; }; @@ -373,7 +375,7 @@ }; /* 256K */ - slot1_ns_partition: partition@A0000 { + slot1_ns_partition: partition@a0000 { label = "image-1-nonsecure"; }; diff --git a/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns.dts b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns.dts index 35410c51b70c..535440fe8587 100644 --- a/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns.dts +++ b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns.dts @@ -6,7 +6,7 @@ */ /dts-v1/; -#include +#include #include "bl5340_dvk_nrf5340_cpuapp_common.dtsi" / { diff --git a/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_common.dtsi b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_common.dtsi index 8f6785d97733..b73f177a8d79 100644 --- a/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_common.dtsi +++ b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_common.dtsi @@ -39,6 +39,7 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + ranges; /* 48K */ boot_partition: partition@0 { @@ -49,7 +50,7 @@ /* 88K */ slot0_partition: partition@c000 { label = "image-0"; - reg = <0x0000C000 0x16000>; + reg = <0x0000c000 0x16000>; }; /* 88K */ diff --git a/boards/ezurio/bl5340_dvk/doc/index.rst b/boards/ezurio/bl5340_dvk/doc/index.rst index 35ce806fc535..0a77913b1131 100644 --- a/boards/ezurio/bl5340_dvk/doc/index.rst +++ b/boards/ezurio/bl5340_dvk/doc/index.rst @@ -202,8 +202,8 @@ Extension. The IDAU may configure bus accesses by the network core to have Secure attribute set; the latter allows to build and run Secure only applications on the BL5340 module. -Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg| -============================================================================= +Building Secure/Non-Secure Zephyr applications with Arm® TrustZone® +=================================================================== Applications on the BL5340 module may contain a Secure and a Non-Secure firmware image for the application core. The Secure image can be built diff --git a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp.dts b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp.dts index 0654c4139c5a..96abc76fa453 100644 --- a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp.dts +++ b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp.dts @@ -27,4 +27,4 @@ }; /* Include default memory partition configuration file */ -#include +#include diff --git a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp_ns.dts b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp_ns.dts index 59ba8bbed25a..dc11d1bd3ee3 100644 --- a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp_ns.dts +++ b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp_ns.dts @@ -9,7 +9,7 @@ #define USE_NON_SECURE_ADDRESS_MAP 1 -#include +#include #include "nrf54l_10_15_cpuapp_common.dtsi" / { @@ -29,81 +29,10 @@ }; }; -/ { - /* - * Default SRAM planning when building for nRF54L10 with ARM TrustZone-M support. - * - Lowest 72 kB SRAM allocated to Secure image (sram0_s). - * - Upper 72 kB SRAM allocated to Non-Secure image (sram0_ns). - * - * nRF54L10 has 192 kB of volatile memory (SRAM) but the last 42kB are reserved for - * the FLPR MCU. - * This static layout needs to be the same with the upstream TF-M layout in the - * header flash_layout.h of the relevant platform. Any updates in the layout - * needs to happen both in the flash_layout.h and in this file at the same time. - */ - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram0_s: image_s@20000000 { - /* Secure image memory */ - reg = <0x20000000 DT_SIZE_K(72)>; - }; - - sram0_ns: image_ns@20012000 { - /* Non-Secure image memory */ - reg = <0x20012000 DT_SIZE_K(72)>; - }; - }; -}; - -&cpuapp_rram { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* nRF54L10 has 1012 kB of non volatile memory (RRAM) but the - * last 62kB are reserved for the FLPR MCU. - * - * This static layout needs to be the same with the upstream TF-M layout in the - * header flash_layout.h of the relevant platform. Any updates in the layout - * needs to happen both in the flash_layout.h and in this file at the same time. - */ - slot0_partition: partition@0 { - label = "image-0"; - reg = <0x0000000 DT_SIZE_K(384)>; - }; - - tfm_ps_partition: partition@60000 { - label = "tfm-ps"; - reg = <0x00060000 DT_SIZE_K(16)>; - }; - - tfm_its_partition: partition@64000 { - label = "tfm-its"; - reg = <0x00064000 DT_SIZE_K(16)>; - }; - - tfm_otp_partition: partition@68000 { - label = "tfm-otp"; - reg = <0x00068000 DT_SIZE_K(8)>; - }; - - slot0_ns_partition: partition@6A000 { - label = "image-0-nonsecure"; - reg = <0x0006A000 DT_SIZE_K(494)>; - }; - - storage_partition: partition@E5800 { - label = "storage"; - reg = <0x000E5800 DT_SIZE_K(32)>; - }; - }; -}; - &uart30 { /* Disable so that TF-M can use this UART */ status = "disabled"; }; + +/* Include default memory partition configuration file */ +#include diff --git a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp.dts b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp.dts index 50a03e2d48f7..1236f74dbe6a 100644 --- a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp.dts +++ b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp.dts @@ -21,4 +21,4 @@ }; /* Include default memory partition configuration file */ -#include +#include diff --git a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp_ns.dts b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp_ns.dts index bca01b2b0624..2d18b5b88dbb 100644 --- a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp_ns.dts +++ b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp_ns.dts @@ -9,7 +9,7 @@ #define USE_NON_SECURE_ADDRESS_MAP 1 -#include +#include #include "nrf54l_10_15_cpuapp_common.dtsi" / { @@ -29,35 +29,6 @@ }; }; -/ { - /* - * Default SRAM planning when building for nRF54L15 with ARM TrustZone-M support - * - Lowest 80 kB SRAM allocated to Secure image (sram0_s). - * - Upper 80 kB SRAM allocated to Non-Secure image (sram0_ns). - * - * nRF54L15 has 256 kB of volatile memory (SRAM) but the last 96kB are reserved for - * the FLPR MCU. - * This static layout needs to be the same with the upstream TF-M layout in the - * header flash_layout.h of the relevant platform. Any updates in the layout - * needs to happen both in the flash_layout.h and in this file at the same time. - */ - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram0_s: image_s@20000000 { - /* Secure image memory */ - reg = <0x20000000 DT_SIZE_K(80)>; - }; - - sram0_ns: image_ns@20014000 { - /* Non-Secure image memory */ - reg = <0x20014000 DT_SIZE_K(80)>; - }; - }; -}; - &uart30 { /* Disable so that TF-M can use this UART */ status = "disabled"; @@ -69,4 +40,4 @@ }; /* Include default memory partition configuration file */ -#include +#include diff --git a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuflpr.dts b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuflpr.dts index 0e00b2d1e5e4..c0584b08c98c 100644 --- a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuflpr.dts +++ b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuflpr.dts @@ -34,6 +34,7 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + ranges; cpuflpr_code_partition: partition@0 { label = "image-0"; diff --git a/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp.dts b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp.dts index 00ffc3f5449c..1f1fdd24a7b4 100644 --- a/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp.dts +++ b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp.dts @@ -21,4 +21,4 @@ }; /* Include default memory partition configuration file */ -#include +#include diff --git a/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp_ns.dts b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp_ns.dts index 6530b554d343..f8c82c05e463 100644 --- a/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp_ns.dts +++ b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp_ns.dts @@ -9,7 +9,7 @@ #define USE_NON_SECURE_ADDRESS_MAP 1 -#include +#include #include "nrf54l15_cpuapp_common.dtsi" / { @@ -29,35 +29,6 @@ }; }; -/ { - /* - * Default SRAM planning when building for nRF54L15 with ARM TrustZone-M support - * - Lowest 80 kB SRAM allocated to Secure image (sram0_s). - * - Upper 80 kB SRAM allocated to Non-Secure image (sram0_ns). - * - * nRF54L15 has 256 kB of volatile memory (SRAM) but the last 96kB are reserved for - * the FLPR MCU. - * This static layout needs to be the same with the upstream TF-M layout in the - * header flash_layout.h of the relevant platform. Any updates in the layout - * needs to happen both in the flash_layout.h and in this file at the same time. - */ - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram0_s: image_s@20000000 { - /* Secure image memory */ - reg = <0x20000000 DT_SIZE_K(80)>; - }; - - sram0_ns: image_ns@20014000 { - /* Non-Secure image memory */ - reg = <0x20014000 DT_SIZE_K(80)>; - }; - }; -}; - &uart30 { /* Disable so that TF-M can use this UART */ status = "disabled"; @@ -69,4 +40,4 @@ }; /* Include default memory partition configuration file */ -#include +#include diff --git a/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuflpr.dts b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuflpr.dts index 12e280a9a90e..2211743673c0 100644 --- a/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuflpr.dts +++ b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuflpr.dts @@ -34,6 +34,7 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + ranges; cpuflpr_code_partition: partition@0 { label = "image-0"; diff --git a/boards/ezurio/bl652_dvk/bl652_dvk.dts b/boards/ezurio/bl652_dvk/bl652_dvk.dts index 23f61e4e80a5..2a42758f812e 100644 --- a/boards/ezurio/bl652_dvk/bl652_dvk.dts +++ b/boards/ezurio/bl652_dvk/bl652_dvk.dts @@ -160,12 +160,12 @@ slot0_partition: partition@c000 { label = "image-0"; - reg = <0x0000C000 0x32000>; + reg = <0x0000c000 0x32000>; }; slot1_partition: partition@3e000 { label = "image-1"; - reg = <0x0003E000 0x32000>; + reg = <0x0003e000 0x32000>; }; scratch_partition: partition@70000 { diff --git a/boards/ezurio/bl653_dvk/bl653_dvk.dts b/boards/ezurio/bl653_dvk/bl653_dvk.dts index 5279f263c362..bcf0896eb207 100644 --- a/boards/ezurio/bl653_dvk/bl653_dvk.dts +++ b/boards/ezurio/bl653_dvk/bl653_dvk.dts @@ -176,27 +176,27 @@ boot_partition: partition@0 { label = "mcuboot"; - reg = <0x00000000 0xC000>; + reg = <0x00000000 0xc000>; }; slot0_partition: partition@c000 { label = "image-0"; - reg = <0x0000C000 0x32000>; + reg = <0x0000c000 0x32000>; }; slot1_partition: partition@3e000 { label = "image-1"; - reg = <0x0003E000 0x32000>; + reg = <0x0003e000 0x32000>; }; scratch_partition: partition@70000 { label = "image-scratch"; - reg = <0x00070000 0xA000>; + reg = <0x00070000 0xa000>; }; storage_partition: partition@7a000 { label = "storage"; - reg = <0x0007A000 0x00006000>; + reg = <0x0007a000 0x00006000>; }; }; }; diff --git a/boards/ezurio/bt610/bt610.dts b/boards/ezurio/bt610/bt610.dts index 791e6c75421a..b7dd129c8be9 100644 --- a/boards/ezurio/bt610/bt610.dts +++ b/boards/ezurio/bt610/bt610.dts @@ -254,7 +254,7 @@ /* 896K */ slot0_partition: partition@18000 { label = "image-0"; - reg = <0x00018000 0x000E0000>; + reg = <0x00018000 0x000e0000>; }; /* @@ -282,19 +282,19 @@ /* 896K */ slot1_partition: partition@0 { label = "image-1"; - reg = <0x00000000 0x000E0000>; + reg = <0x00000000 0x000e0000>; }; /* 16K */ - scratch_partition: partition@E0000 { + scratch_partition: partition@e0000 { label = "image-scratch"; - reg = <0x000E0000 0x00004000>; + reg = <0x000e0000 0x00004000>; }; /* 112K */ - customer_partition: partition@E4000 { + customer_partition: partition@e4000 { label = "customer-storage"; - reg = <0x000E4000 0x0001C000>; + reg = <0x000e4000 0x0001c000>; }; /* 7MB */ diff --git a/boards/ezurio/lyra_24_dvk/Kconfig.defconfig b/boards/ezurio/lyra_24_dvk/Kconfig.defconfig new file mode 100644 index 000000000000..7a62e8426b73 --- /dev/null +++ b/boards/ezurio/lyra_24_dvk/Kconfig.defconfig @@ -0,0 +1,25 @@ +# Copyright (c) 2021, Sateesh Kotapati +# Copyright (c) 2026 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_LYRA_24_DVK_P10 || BOARD_LYRA_24_DVK_P20 || BOARD_LYRA_24_DVK_P20RF || BOARD_LYRA_24_DVK_S10 + +config REGULATOR + default y + +config LOG_BACKEND_SWO_FREQ_HZ + default 875000 + depends on LOG_BACKEND_SWO + +config FPU + default y if SOC_GECKO_USE_RAIL || BT + +if BT + +config MAIN_STACK_SIZE + default 3072 if PM + default 2304 + +endif # BT + +endif # BOARD_LYRA_24_DVK_P10 || BOARD_LYRA_24_DVK_P20 || BOARD_LYRA_24_DVK_P20RF || BOARD_LYRA_24_DVK_S10 diff --git a/boards/ezurio/lyra_24_dvk/Kconfig.lyra_24_dvk_p10 b/boards/ezurio/lyra_24_dvk/Kconfig.lyra_24_dvk_p10 new file mode 100644 index 000000000000..1ea9a0ab06dd --- /dev/null +++ b/boards/ezurio/lyra_24_dvk/Kconfig.lyra_24_dvk_p10 @@ -0,0 +1,6 @@ +# Copyright (c) 2021, Sateesh Kotapati +# Copyright (c) 2026 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_LYRA_24_DVK_P10 + select SOC_BGM240PB22VNA diff --git a/boards/ezurio/lyra_24_dvk/Kconfig.lyra_24_dvk_p20 b/boards/ezurio/lyra_24_dvk/Kconfig.lyra_24_dvk_p20 new file mode 100644 index 000000000000..a69534eb88c5 --- /dev/null +++ b/boards/ezurio/lyra_24_dvk/Kconfig.lyra_24_dvk_p20 @@ -0,0 +1,6 @@ +# Copyright (c) 2021, Sateesh Kotapati +# Copyright (c) 2026 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_LYRA_24_DVK_P20 + select SOC_BGM240PB32VNA diff --git a/boards/ezurio/lyra_24_dvk/Kconfig.lyra_24_dvk_p20rf b/boards/ezurio/lyra_24_dvk/Kconfig.lyra_24_dvk_p20rf new file mode 100644 index 000000000000..53411520f6a7 --- /dev/null +++ b/boards/ezurio/lyra_24_dvk/Kconfig.lyra_24_dvk_p20rf @@ -0,0 +1,6 @@ +# Copyright (c) 2021, Sateesh Kotapati +# Copyright (c) 2026 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_LYRA_24_DVK_P20RF + select SOC_BGM240PB32VNN diff --git a/boards/ezurio/lyra_24_dvk/Kconfig.lyra_24_dvk_s10 b/boards/ezurio/lyra_24_dvk/Kconfig.lyra_24_dvk_s10 new file mode 100644 index 000000000000..739a73a54647 --- /dev/null +++ b/boards/ezurio/lyra_24_dvk/Kconfig.lyra_24_dvk_s10 @@ -0,0 +1,6 @@ +# Copyright (c) 2021, Sateesh Kotapati +# Copyright (c) 2026 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_LYRA_24_DVK_S10 + select SOC_BGM240SB22VNA diff --git a/boards/ezurio/lyra_24_dvk/board.cmake b/boards/ezurio/lyra_24_dvk/board.cmake new file mode 100644 index 000000000000..c2d7111f1ce5 --- /dev/null +++ b/boards/ezurio/lyra_24_dvk/board.cmake @@ -0,0 +1,9 @@ +# Copyright (c) 2021, Sateesh Kotapati +# Copyright (c) 2026 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=EFR32MG24BxxxF1536" "--reset-after-load") +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) + +board_runner_args(silabs_commander "--device=${CONFIG_SOC}") +include(${ZEPHYR_BASE}/boards/common/silabs_commander.board.cmake) diff --git a/boards/ezurio/lyra_24_dvk/board.yml b/boards/ezurio/lyra_24_dvk/board.yml new file mode 100644 index 000000000000..705ef866ddf5 --- /dev/null +++ b/boards/ezurio/lyra_24_dvk/board.yml @@ -0,0 +1,21 @@ +boards: + - name: lyra_24_dvk_p10 + vendor: ezurio + full_name: Lyra 24 P10 DVK + socs: + - name: bgm240pb22vna + - name: lyra_24_dvk_p20 + vendor: ezurio + full_name: Lyra 24 P20 DVK + socs: + - name: bgm240pb32vna + - name: lyra_24_dvk_p20rf + vendor: ezurio + full_name: Lyra 24 P20RF DVK + socs: + - name: bgm240pb32vnn + - name: lyra_24_dvk_s10 + vendor: ezurio + full_name: Lyra 24 S10 DVK + socs: + - name: bgm240sb22vna diff --git a/boards/ezurio/lyra_24_dvk/doc/img/lyra_24_dvk_p10.webp b/boards/ezurio/lyra_24_dvk/doc/img/lyra_24_dvk_p10.webp new file mode 100644 index 000000000000..007662ae9e41 Binary files /dev/null and b/boards/ezurio/lyra_24_dvk/doc/img/lyra_24_dvk_p10.webp differ diff --git a/boards/ezurio/lyra_24_dvk/doc/img/lyra_24_dvk_p20.webp b/boards/ezurio/lyra_24_dvk/doc/img/lyra_24_dvk_p20.webp new file mode 100644 index 000000000000..007662ae9e41 Binary files /dev/null and b/boards/ezurio/lyra_24_dvk/doc/img/lyra_24_dvk_p20.webp differ diff --git a/boards/ezurio/lyra_24_dvk/doc/img/lyra_24_dvk_p20rf.webp b/boards/ezurio/lyra_24_dvk/doc/img/lyra_24_dvk_p20rf.webp new file mode 100644 index 000000000000..007662ae9e41 Binary files /dev/null and b/boards/ezurio/lyra_24_dvk/doc/img/lyra_24_dvk_p20rf.webp differ diff --git a/boards/ezurio/lyra_24_dvk/doc/img/lyra_24_dvk_s10.webp b/boards/ezurio/lyra_24_dvk/doc/img/lyra_24_dvk_s10.webp new file mode 100644 index 000000000000..a6b085e96050 Binary files /dev/null and b/boards/ezurio/lyra_24_dvk/doc/img/lyra_24_dvk_s10.webp differ diff --git a/boards/ezurio/lyra_24_dvk/doc/lyra_24_dvk_common_1.rst.inc b/boards/ezurio/lyra_24_dvk/doc/lyra_24_dvk_common_1.rst.inc new file mode 100644 index 000000000000..223256adfed4 --- /dev/null +++ b/boards/ezurio/lyra_24_dvk/doc/lyra_24_dvk_common_1.rst.inc @@ -0,0 +1,56 @@ +.. SPDX-License-Identifier: Apache-2.0 +.. +.. Copyright (c) 2026 Ezurio LLC + +Overview +******** + +The Lyra 24 |Lyra 24 variant| Development Kit provides support for the Ezurio Lyra 24 |Lyra 24 variant| Bluetooth Low Energy v5.4 module. + +The module is based on the Silicon Laboratories |SoC| module and includes an EFR32BG24 Arm Cortex-M33 CPU. + +The Lyra 24 |Lyra 24 variant| module incorporates the QFN package EFR32BG24 (1024kB Flash, 256kB RAM). The part features +up to |Number of IO| configurable GPIOs and BLE Radio TX Power up to |BLE TX Power|. + +The kit features a USB interface, an on-board SEGGER J-Link debugger, one user-LED and button, and +support for hardware add-on boards via a `mikroBUS`_ socket and a `Qwiic`_ connector. + +.. note:: + You can find more information about the Lyra 24 family of modules in the `Lyra 24 product brief`_ and on the `Lyra 24 website`_. + + You can find more information about the Lyra 24 |Lyra 24 variant| module in the |Datasheet Ref|. + + You can find more information about the underlying |SoC| module in the |SoC Datasheet Ref|. + + You can find more information about the underlying EFR32BG24 SoC in the `EFR32BG24 datasheet`_ + and `EFR32BG24 reference manual`_. + +Hardware +******** + +The Lyra 24 |Lyra 24 variant| DVK has two crystal oscillators as follows. + +* High-frequency 39 MHz crystal oscillator (HFXO) +* Low-frequency 32.768 kHz crystal oscillator (LFXO) + +The high-frequency crystal oscillator is fitted within the Lyra 24 |Lyra 24 variant| module. + +The low-frequency crystal oscillator is fitted to the DVK and is external to the Lyra 24 |Lyra 24 variant| module. + +The module supports an |Antenna Type| Bluetooth Low Energy antenna. + +Full details of the DVK can be found in the |User Guide Ref| and |Schematics Ref|. + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Connections and IOs +=================== + +In the following table, the column **Name** contains Pin names. For example, PA2 +means Pin number 2 on PORTA, as used in the board's datasheets and manuals. + +The **Direction** column indicates the pin direction from the module perspective, with +I indicating Input, O Output, I/O for both and N/A where not applicable. diff --git a/boards/ezurio/lyra_24_dvk/doc/lyra_24_dvk_common_2.rst.inc b/boards/ezurio/lyra_24_dvk/doc/lyra_24_dvk_common_2.rst.inc new file mode 100644 index 000000000000..30cd9fda2034 --- /dev/null +++ b/boards/ezurio/lyra_24_dvk/doc/lyra_24_dvk_common_2.rst.inc @@ -0,0 +1,58 @@ +.. SPDX-License-Identifier: Apache-2.0 +.. +.. Copyright (c) 2026 Ezurio LLC + +.. note:: + Qwiic SCL is multipexed to the same I/O as MikroBUS SCL. MikroBUS I2C based boards can be used + in conjunction with Qwiic boards by closing solder bridges SB5 and SB6. + + Qwiic SDA is multipexed to the same I/O as MikroBUS SDA. MikroBUS I2C based boards can be used + in conjunction with Qwiic boards by closing solder bridges SB9 and SB10. + + Refer to the |User Guide Ref| and |Schematics Ref| for further details. + +System Clock +============ + +The Lyra 24 |Lyra 24 variant| is configured to use the 39 MHz external oscillator on the +board, and can operate at clock speeds of up to 78 MHz. + +Serial Port +=========== + +The Lyra 24 |Lyra 24 variant| has two EUSARTs and one USART. + +* EUSART0 defaults to the mikroBUS UART. +* EUSART1 defaults to the mikroBUS SPI port. +* USART0 is connected to the board controller and is used for the console. + +Programming and Debugging +************************* + +Applications for the |Board Quoted| board can be built, flashed, and debugged in the usual way. +See :ref:`build_an_application` and :ref:`application_run` for more details on building and running. + +.. note:: + Before using the kit you should update the J-Link firmware + in `Simplicity Studio`_. + +Testing the LED and button +========================== + +The :zephyr:code-sample:`blinky` sample can be used to test the DVK LED. + +The :zephyr:code-sample:`button` sample can be used to test the DVK button. + +Bluetooth Low Energy +==================== + +To use Bluetooth Low Energy functionality, run the command below to retrieve necessary binary +blobs from the Silicon Labs HAL repository. + +.. code-block:: console + + west blobs fetch hal_silabs + +Then build the Zephyr kernel and a Bluetooth sample with the following +command. The :zephyr:code-sample:`bluetooth_observer` sample application is used in +this example. diff --git a/boards/ezurio/lyra_24_dvk/doc/lyra_24_dvk_common_3.rst.inc b/boards/ezurio/lyra_24_dvk/doc/lyra_24_dvk_common_3.rst.inc new file mode 100644 index 000000000000..8be1e8f471cd --- /dev/null +++ b/boards/ezurio/lyra_24_dvk/doc/lyra_24_dvk_common_3.rst.inc @@ -0,0 +1,24 @@ +.. SPDX-License-Identifier: Apache-2.0 +.. +.. Copyright (c) 2026 Ezurio LLC + +.. _Lyra 24 product brief: + https://www.ezurio.com/documentation/product-brief-lyra-24-series + +.. _Lyra 24 website: + https://www.ezurio.com/wireless-modules/bluetooth-modules/bluetooth-5-modules/lyra-24-series-bluetooth-5-modules + +.. _EFR32BG24 datasheet: + https://www.silabs.com/documents/public/data-sheets/efr32bg24-datasheet.pdf + +.. _EFR32BG24 reference manual: + https://www.silabs.com/documents/public/reference-manuals/efr32xg24-rm.pdf + +.. _mikroBUS: + https://www.mikroe.com/mikrobus + +.. _Qwiic: + https://www.sparkfun.com/qwiic + +.. _Simplicity Studio: + https://www.silabs.com/software-and-tools/simplicity-studio diff --git a/boards/ezurio/lyra_24_dvk/doc/lyra_24_dvk_p10.rst b/boards/ezurio/lyra_24_dvk/doc/lyra_24_dvk_p10.rst new file mode 100644 index 000000000000..8c22440e235d --- /dev/null +++ b/boards/ezurio/lyra_24_dvk/doc/lyra_24_dvk_p10.rst @@ -0,0 +1,27 @@ +.. zephyr:board:: lyra_24_dvk_p10 + +.. |Lyra 24 variant| replace:: P10 +.. |Datasheet Ref| replace:: `Lyra 24 P datasheet`_ +.. |SoC| replace:: BGM240PB22VNA +.. |SoC Datasheet Ref| replace:: `BGM240P datasheet`_ +.. |Antenna Type| replace:: on-chip +.. |Number of IO| replace:: 26 +.. |BLE TX Power| replace:: 10dBm +.. |Board Quoted| replace:: ``lyra_24_dvk_p10`` +.. |User Guide Ref| replace:: `Lyra 24 P DVK user guide`_ +.. |Schematics Ref| replace:: `Lyra 24 P10 DVK schematics`_ + +.. include:: lyra_24_dvk_common_1.rst.inc +.. include:: lyra_24_dvk_p_pinmap.rst.inc +.. include:: lyra_24_dvk_common_2.rst.inc + +.. zephyr-app-commands:: + :zephyr-app: samples/bluetooth/observer + :board: lyra_24_dvk_p10 + :goals: build + +.. include:: lyra_24_dvk_common_3.rst.inc +.. include:: lyra_24_dvk_p_references.rst.inc + +.. _Lyra 24 P10 DVK schematics: + https://www.ezurio.com/documentation/schematic-pcb-assembly-dvk-lyra-24p-devboard-integrated-antenna-10dbm-453-00142-k1 diff --git a/boards/ezurio/lyra_24_dvk/doc/lyra_24_dvk_p20.rst b/boards/ezurio/lyra_24_dvk/doc/lyra_24_dvk_p20.rst new file mode 100644 index 000000000000..e3fbf77ce619 --- /dev/null +++ b/boards/ezurio/lyra_24_dvk/doc/lyra_24_dvk_p20.rst @@ -0,0 +1,27 @@ +.. zephyr:board:: lyra_24_dvk_p20 + +.. |Lyra 24 variant| replace:: P20 +.. |Datasheet Ref| replace:: `Lyra 24 P datasheet`_ +.. |SoC| replace:: BGM240PB32VNA +.. |SoC Datasheet Ref| replace:: `BGM240P datasheet`_ +.. |Antenna Type| replace:: on-chip +.. |Number of IO| replace:: 26 +.. |BLE TX Power| replace:: 20dBm +.. |Board Quoted| replace:: ``lyra_24_dvk_p20`` +.. |User Guide Ref| replace:: `Lyra 24 P DVK user guide`_ +.. |Schematics Ref| replace:: `Lyra 24 P20 DVK schematics`_ + +.. include:: lyra_24_dvk_common_1.rst.inc +.. include:: lyra_24_dvk_p_pinmap.rst.inc +.. include:: lyra_24_dvk_common_2.rst.inc + +.. zephyr-app-commands:: + :zephyr-app: samples/bluetooth/observer + :board: lyra_24_dvk_p20 + :goals: build + +.. include:: lyra_24_dvk_common_3.rst.inc +.. include:: lyra_24_dvk_p_references.rst.inc + +.. _Lyra 24 P20 DVK schematics: + https://www.ezurio.com/documentation/schematic-pcb-assembly-dvk-lyra-24p-devboard-integrated-antenna-20dbm-453-00145-k1 diff --git a/boards/ezurio/lyra_24_dvk/doc/lyra_24_dvk_p20rf.rst b/boards/ezurio/lyra_24_dvk/doc/lyra_24_dvk_p20rf.rst new file mode 100644 index 000000000000..b4640cd259b7 --- /dev/null +++ b/boards/ezurio/lyra_24_dvk/doc/lyra_24_dvk_p20rf.rst @@ -0,0 +1,27 @@ +.. zephyr:board:: lyra_24_dvk_p20rf + +.. |Lyra 24 variant| replace:: P20RF +.. |Datasheet Ref| replace:: `Lyra 24 P datasheet`_ +.. |SoC| replace:: BGM240PB32VNN +.. |SoC Datasheet Ref| replace:: `BGM240P datasheet`_ +.. |Antenna Type| replace:: external +.. |Number of IO| replace:: 26 +.. |BLE TX Power| replace:: 20dBm +.. |Board Quoted| replace:: ``lyra_24_dvk_p20rf`` +.. |User Guide Ref| replace:: `Lyra 24 P DVK user guide`_ +.. |Schematics Ref| replace:: `Lyra 24 P20RF DVK schematics`_ + +.. include:: lyra_24_dvk_common_1.rst.inc +.. include:: lyra_24_dvk_p_pinmap.rst.inc +.. include:: lyra_24_dvk_common_2.rst.inc + +.. zephyr-app-commands:: + :zephyr-app: samples/bluetooth/observer + :board: lyra_24_dvk_p20rf + :goals: build + +.. include:: lyra_24_dvk_common_3.rst.inc +.. include:: lyra_24_dvk_p_references.rst.inc + +.. _Lyra 24 P20RF DVK schematics: + https://www.ezurio.com/documentation/schematic-pcb-assembly-dvk-lyra-24p-devboard-rf-trace-pad-20dbm-453-00148-k1 diff --git a/boards/ezurio/lyra_24_dvk/doc/lyra_24_dvk_p_pinmap.rst.inc b/boards/ezurio/lyra_24_dvk/doc/lyra_24_dvk_p_pinmap.rst.inc new file mode 100644 index 000000000000..657f97c86996 --- /dev/null +++ b/boards/ezurio/lyra_24_dvk/doc/lyra_24_dvk_p_pinmap.rst.inc @@ -0,0 +1,59 @@ +.. SPDX-License-Identifier: Apache-2.0 +.. +.. Copyright (c) 2026 Ezurio LLC + ++-------+-------------+-------------------------------------+-----------+ +| Name | Function | Usage | Direction | ++=======+=============+=====================================+===========+ +| PA0 | USART0_TX | UART Console VCOM_TX | O | ++-------+-------------+-------------------------------------+-----------+ +| PA1 | SWD_SWCLK | JLink SWCLK | I | ++-------+-------------+-------------------------------------+-----------+ +| PA2 | SWD_SWDIO | JLink SWDIO | I/O | ++-------+-------------+-------------------------------------+-----------+ +| PA3 | SWD_SWO | JLink SWO | O | ++-------+-------------+-------------------------------------+-----------+ +| PA4 | USART0_RTS | UART Console VCOM_RTS | O | ++-------+-------------+-------------------------------------+-----------+ +| PA5 | USART0_CTS | UART Console VCOM_CTS | I | ++-------+-------------+-------------------------------------+-----------+ +| PA6 | GPIO | Breakout Connector GPIO | I/O | ++-------+-------------+-------------------------------------+-----------+ +| PA7 | USART0_RX | UART Console VCOM_RX | I | ++-------+-------------+-------------------------------------+-----------+ +| PA8 | GPIO | LED 0 | O | ++-------+-------------+-------------------------------------+-----------+ +| PB0 | GPIO | mikroBUS AN | I | ++-------+-------------+-------------------------------------+-----------+ +| PB1 | EUSART0_TX | mikroBUS TX | O | ++-------+-------------+-------------------------------------+-----------+ +| PB2 | EUSART0_RX | mikroBUS RX | I | ++-------+-------------+-------------------------------------+-----------+ +| PB3 | GPIO | mikroBUS INT | I | ++-------+-------------+-------------------------------------+-----------+ +| PB4 | GPIO | mikroBUS PWM | O | ++-------+-------------+-------------------------------------+-----------+ +| PC0 | PTI_FRAME | Packet Trace Interface FRAME | O | ++-------+-------------+-------------------------------------+-----------+ +| PC1 | PTI_DATA | Packet Trace Interface DATA | O | ++-------+-------------+-------------------------------------+-----------+ +| PC2 | EUSART1_SCK | mikroBUS SCK | O | ++-------+-------------+-------------------------------------+-----------+ +| PC3 | GPIO | mikroBUS CS | O | ++-------+-------------+-------------------------------------+-----------+ +| PC4 | EUSART1_TX | mikroBUS MOSI | O | ++-------+-------------+-------------------------------------+-----------+ +| PC5 | EUSART1_RX | mikroBUS MISO | I | ++-------+-------------+-------------------------------------+-----------+ +| PC6 | GPIO | mikroBUS RST | O | ++-------+-------------+-------------------------------------+-----------+ +| PC7 | GPIO | Button 0 | I | ++-------+-------------+-------------------------------------+-----------+ +| PD0 | LFXO | LFXO | N/A | ++-------+-------------+-------------------------------------+-----------+ +| PD1 | LFXO | LFXO | N/A | ++-------+-------------+-------------------------------------+-----------+ +| PD2 | I2C0_SCL | mikroBUS SCL / Qwiic SCL | I/O | ++-------+-------------+-------------------------------------+-----------+ +| PD3 | I2C0_SDA | mikroBUS SDA / Qwiic SDA | I/O | ++-------+-------------+-------------------------------------+-----------+ diff --git a/boards/ezurio/lyra_24_dvk/doc/lyra_24_dvk_p_references.rst.inc b/boards/ezurio/lyra_24_dvk/doc/lyra_24_dvk_p_references.rst.inc new file mode 100644 index 000000000000..5b96213ee952 --- /dev/null +++ b/boards/ezurio/lyra_24_dvk/doc/lyra_24_dvk_p_references.rst.inc @@ -0,0 +1,12 @@ +.. SPDX-License-Identifier: Apache-2.0 +.. +.. Copyright (c) 2026 Ezurio LLC + +.. _Lyra 24 P datasheet: + https://www.ezurio.com/documentation/datasheet-lyra-24p + +.. _BGM240P datasheet: + https://www.silabs.com/documents/public/data-sheets/bgm240p-datasheet.pdf + +.. _Lyra 24 P DVK user guide: + https://www.ezurio.com/documentation/user-guide-lyra-24p-development-kit diff --git a/boards/ezurio/lyra_24_dvk/doc/lyra_24_dvk_s10.rst b/boards/ezurio/lyra_24_dvk/doc/lyra_24_dvk_s10.rst new file mode 100644 index 000000000000..ceffd2e064e8 --- /dev/null +++ b/boards/ezurio/lyra_24_dvk/doc/lyra_24_dvk_s10.rst @@ -0,0 +1,101 @@ +.. zephyr:board:: lyra_24_dvk_s10 + +.. |Lyra 24 variant| replace:: S10 +.. |Datasheet Ref| replace:: `Lyra 24 S datasheet`_ +.. |SoC| replace:: BGM240SB22VNA +.. |SoC Datasheet Ref| replace:: `BGM240S datasheet`_ +.. |Antenna Type| replace:: on-chip or external +.. |Number of IO| replace:: 31 +.. |BLE TX Power| replace:: 10dBm +.. |Board Quoted| replace:: ``lyra_24_dvk_s10`` +.. |User Guide Ref| replace:: `Lyra 24 S DVK user guide`_ +.. |Schematics Ref| replace:: `Lyra 24 S10 DVK schematics`_ + +.. include:: lyra_24_dvk_common_1.rst.inc + ++-------+-------------+-------------------------------------+-----------+ +| Name | Function | Usage | Direction | ++=======+=============+=====================================+===========+ +| PA0 | USART0_TX | UART Console VCOM_TX | O | ++-------+-------------+-------------------------------------+-----------+ +| PA1 | SWD_SWCLK | JLink SWCLK | I | ++-------+-------------+-------------------------------------+-----------+ +| PA2 | SWD_SWDIO | JLink SWDIO | I/O | ++-------+-------------+-------------------------------------+-----------+ +| PA3 | SWD_SWO | JLink SWO | O | ++-------+-------------+-------------------------------------+-----------+ +| PA4 | USART0_RTS | UART Console VCOM_RTS | O | ++-------+-------------+-------------------------------------+-----------+ +| PA5 | USART0_CTS | UART Console VCOM_CTS | I | ++-------+-------------+-------------------------------------+-----------+ +| PA6 | GPIO | Breakout Connector GPIO | I/O | ++-------+-------------+-------------------------------------+-----------+ +| PA7 | USART0_RX | UART Console VCOM_RX | I | ++-------+-------------+-------------------------------------+-----------+ +| PA8 | GPIO | LED 0 | O | ++-------+-------------+-------------------------------------+-----------+ +| PB0 | GPIO | mikroBUS AN | I | ++-------+-------------+-------------------------------------+-----------+ +| PB1 | EUSART0_TX | mikroBUS TX | O | ++-------+-------------+-------------------------------------+-----------+ +| PB2 | EUSART0_RX | mikroBUS RX | I | ++-------+-------------+-------------------------------------+-----------+ +| PB3 | GPIO | mikroBUS INT | I | ++-------+-------------+-------------------------------------+-----------+ +| PB4 | GPIO | mikroBUS PWM | O | ++-------+-------------+-------------------------------------+-----------+ +| PB5 | GPIO | Test Point GPIO | I/O | ++-------+-------------+-------------------------------------+-----------+ +| PC0 | PTI_FRAME | Packet Trace Interface FRAME | O | ++-------+-------------+-------------------------------------+-----------+ +| PC1 | PTI_DATA | Packet Trace Interface DATA | O | ++-------+-------------+-------------------------------------+-----------+ +| PC2 | EUSART1_SCK | mikroBUS SCK | O | ++-------+-------------+-------------------------------------+-----------+ +| PC3 | GPIO | mikroBUS CS | O | ++-------+-------------+-------------------------------------+-----------+ +| PC4 | EUSART1_TX | mikroBUS MOSI | O | ++-------+-------------+-------------------------------------+-----------+ +| PC5 | EUSART1_RX | mikroBUS MISO | I | ++-------+-------------+-------------------------------------+-----------+ +| PC6 | GPIO | mikroBUS RST | O | ++-------+-------------+-------------------------------------+-----------+ +| PC7 | GPIO | Button 0 | I | ++-------+-------------+-------------------------------------+-----------+ +| PC8 | GPIO | Test Point GPIO | I/O | ++-------+-------------+-------------------------------------+-----------+ +| PC9 | GPIO | Test Point GPIO | I/O | ++-------+-------------+-------------------------------------+-----------+ +| PD0 | LFXO | LFXO | N/A | ++-------+-------------+-------------------------------------+-----------+ +| PD1 | LFXO | LFXO | N/A | ++-------+-------------+-------------------------------------+-----------+ +| PD2 | I2C0_SCL | mikroBUS SCL / Qwiic SCL | I/O | ++-------+-------------+-------------------------------------+-----------+ +| PD3 | I2C0_SDA | mikroBUS SDA / Qwiic SDA | I/O | ++-------+-------------+-------------------------------------+-----------+ +| PD4 | GPIO | Test Point GPIO | I/O | ++-------+-------------+-------------------------------------+-----------+ +| PD5 | GPIO | Test Point GPIO | I/O | ++-------+-------------+-------------------------------------+-----------+ + +.. include:: lyra_24_dvk_common_2.rst.inc + +.. zephyr-app-commands:: + :zephyr-app: samples/bluetooth/observer + :board: lyra_24_dvk_s10 + :goals: build + +.. include:: lyra_24_dvk_common_3.rst.inc + +.. _Lyra 24 S datasheet: + https://www.ezurio.com/documentation/datasheet-lyra-24s + +.. _BGM240S datasheet: + https://www.silabs.com/documents/public/data-sheets/bgm240s-datasheet.pdf + +.. _Lyra 24 S DVK user guide: + https://www.ezurio.com/documentation/user-guide-lyra-24s-development-kit + +.. _Lyra 24 S10 DVK schematics: + https://www.ezurio.com/documentation/schematic-pcb-assembly-dvk-lyra-24s-devboard-integrated-antenna-10dbm-453-00170-k1 diff --git a/boards/ezurio/lyra_24_dvk/lyra_24_dvk-pinctrl.dtsi b/boards/ezurio/lyra_24_dvk/lyra_24_dvk-pinctrl.dtsi new file mode 100644 index 000000000000..caf2fd614c61 --- /dev/null +++ b/boards/ezurio/lyra_24_dvk/lyra_24_dvk-pinctrl.dtsi @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2024 Silicon Laboratories Inc. + * Copyright (c) 2026 Ezurio LLC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + timer0_default: timer0_default { + group0 { + pins = ; + drive-push-pull; + output-high; + }; + }; + + usart0_default: usart0_default { + group0 { + pins = , ; + drive-push-pull; + output-high; + }; + + group1 { + pins = , ; + input-enable; + silabs,input-filter; + }; + }; + + eusart1_default: eusart1_default { + group0 { + pins = , ; + drive-push-pull; + output-high; + }; + + group1 { + pins = ; + input-enable; + silabs,input-filter; + }; + }; + + i2c0_default: i2c0_default { + group0 { + pins = , ; + bias-pull-up; + drive-open-drain; + }; + }; + + eusart0_default: eusart0_default { + group0 { + pins = ; + drive-push-pull; + output-high; + }; + + group1 { + pins = ; + input-enable; + silabs,input-filter; + }; + }; + + itm_default: itm_default { + group0 { + pins = ; + drive-push-pull; + output-high; + }; + }; + + pti_default: pti_default { + group0 { + pins = , ; + drive-push-pull; + output-high; + }; + }; +}; diff --git a/boards/ezurio/lyra_24_dvk/lyra_24_dvk.dtsi b/boards/ezurio/lyra_24_dvk/lyra_24_dvk.dtsi new file mode 100644 index 000000000000..d5d6798c4ce6 --- /dev/null +++ b/boards/ezurio/lyra_24_dvk/lyra_24_dvk.dtsi @@ -0,0 +1,280 @@ +/* + * Copyright (c) 2020 TriaGnoSys GmbH + * Copyright (c) 2026 Ezurio LLC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include "lyra_24_dvk-pinctrl.dtsi" + +/ { + chosen { + zephyr,bt-hci = &bt_hci_silabs; + zephyr,code-partition = &slot0_partition; + zephyr,console = &usart0; + zephyr,flash = &flash0; + zephyr,shell-uart = &usart0; + zephyr,sram = &sram0; + zephyr,uart-pipe = &usart0; + }; + + aliases { + led0 = &led0; + pwm-led0 = &pwm_led0; + sw0 = &button0; + watchdog0 = &wdog0; + }; + + leds { + compatible = "gpio-leds"; + + led0: led_0 { + gpios = <&gpioa 8 GPIO_ACTIVE_LOW>; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + + pwm_led0: pwm_led_0 { + pwms = <&timer0_pwm 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>; + }; + }; + + buttons { + compatible = "gpio-keys"; + + button0: button_0 { + gpios = <&gpioc 7 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; + + mikrobus_header: mikrobus-connector { + compatible = "mikro-bus"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0>; + gpio-map-pass-thru = <0 GPIO_DT_FLAGS_MASK>; + gpio-map = <0 0 &gpiob 0 0>, /* AN */ + <1 0 &gpioc 6 0>, /* RST */ + <2 0 &gpioc 3 0>, /* CS */ + <3 0 &gpioc 2 0>, /* SCK */ + <4 0 &gpioc 5 0>, /* MISO */ + <5 0 &gpioc 4 0>, /* MOSI */ + <6 0 &gpiob 4 0>, /* PWM */ + <7 0 &gpiob 3 0>, /* INT */ + <8 0 &gpiob 2 0>, /* RX */ + <9 0 &gpiob 1 0>, /* TX */ + <10 0 &gpiod 2 0>, /* SCL */ + <11 0 &gpiod 3 0>; /* SDA */ + }; + + qwiic_connector: stemma-qt-connector { + compatible = "stemma-qt-connector"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0>; + gpio-map-pass-thru = <0 GPIO_DT_FLAGS_MASK>; + gpio-map = <0 0 &gpiod 2 0>, /* SCL */ + <1 0 &gpiod 3 0>; /* SDA */ + }; + + mikrobus_adc: zephyr,user { + io-channels = <&adc0 0>; + }; +}; + +&em23grpaclk { + clocks = <&lfxo>; +}; + +&em4grpaclk { + clocks = <&lfxo>; +}; + +&sysrtcclk { + clocks = <&lfxo>; +}; + +&wdog0clk { + clocks = <&lfxo>; +}; + +&wdog1clk { + clocks = <&lfxo>; +}; + +&cpu0 { + clock-frequency = <39000000>; +}; + +&hfrcodpll { + clock-frequency = ; + clocks = <&hfxo>; + dpll-autorecover; + dpll-edge = "fall"; + dpll-lock = "phase"; + dpll-m = <3839>; + dpll-n = <3839>; +}; + +&hfxo { + ctune = <140>; + precision = <50>; + status = "okay"; +}; + +&lfxo { + status = "okay"; + ctune = <63>; + precision = <50>; +}; + +&gpio { + status = "okay"; +}; + +&gpioa { + status = "okay"; +}; + +&gpiob { + status = "okay"; +}; + +&gpioc { + status = "okay"; +}; + +&gpiod { + status = "okay"; +}; + +&timer0 { + status = "okay"; + + timer0_pwm: pwm { + pinctrl-0 = <&timer0_default>; + pinctrl-names = "default"; + status = "okay"; + }; +}; + +&usart0 { + current-speed = <115200>; + pinctrl-0 = <&usart0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&dcdc { + regulator-boot-on; + regulator-initial-mode = ; + status = "okay"; +}; + +&eusart1 { + compatible = "silabs,eusart-spi"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&eusart1_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sysrtc0 { + status = "okay"; +}; + +&adc0 { + status = "okay"; +}; + +&vdac0 { + status = "okay"; +}; + +&vdac1 { + status = "okay"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&wdog0 { + status = "okay"; +}; + +&eusart0 { + compatible = "silabs,eusart-uart"; + pinctrl-0 = <&eusart0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&se { + status = "okay"; +}; + +&itm { + pinctrl-0 = <&itm_default>; + pinctrl-names = "default"; + swo-ref-frequency = ; +}; + +&bt_hci_silabs { + status = "okay"; +}; + +&pti { + pinctrl-0 = <&pti_default>; + pinctrl-names = "default"; +}; + +mikrobus_i2c: &i2c0 {}; + +mikrobus_spi: &eusart1 {}; + +mikrobus_uart: &eusart0 {}; + +zephyr_i2c: &i2c0 {}; + +zephyr_spi: &eusart1 {}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 48 kB for the bootloader */ + boot_partition: partition@0 { + reg = <0x0 DT_SIZE_K(48)>; + label = "mcuboot"; + read-only; + }; + + /* Reserve 728 kB for the application in slot 0 */ + slot0_partition: partition@c000 { + reg = <0x0000c000 DT_SIZE_K(728)>; + label = "image-0"; + }; + + /* Reserve 728 kB for the application in slot 1 */ + slot1_partition: partition@c2000 { + reg = <0x000c2000 DT_SIZE_K(728)>; + label = "image-1"; + }; + + /* Set 32 kB of storage at the end of the 1536 kB of flash */ + storage_partition: partition@178000 { + reg = <0x00178000 DT_SIZE_K(32)>; + label = "storage"; + }; + }; +}; diff --git a/boards/ezurio/lyra_24_dvk/lyra_24_dvk_p10.dts b/boards/ezurio/lyra_24_dvk/lyra_24_dvk_p10.dts new file mode 100644 index 000000000000..e3e8eecb43f1 --- /dev/null +++ b/boards/ezurio/lyra_24_dvk/lyra_24_dvk_p10.dts @@ -0,0 +1,15 @@ +/* + * Copyright The Zephyr Project Contributors + * Copyright (c) 2026 Ezurio LLC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "lyra_24_dvk.dtsi" + +/ { + model = "Ezurio Lyra 24 P10 DVK"; + compatible = "ezurio,lyra_24_dvk_p10", "silabs,efr32bg24"; +}; diff --git a/boards/ezurio/lyra_24_dvk/lyra_24_dvk_p10.yaml b/boards/ezurio/lyra_24_dvk/lyra_24_dvk_p10.yaml new file mode 100644 index 000000000000..a5c606c801f6 --- /dev/null +++ b/boards/ezurio/lyra_24_dvk/lyra_24_dvk_p10.yaml @@ -0,0 +1,28 @@ +identifier: lyra_24_dvk_p10 +name: Lyra 24 P10 DVK +type: mcu +arch: arm +ram: 256 +flash: 728 +toolchain: + - zephyr + - gnuarmemb +supported: + - adc + - bluetooth + - clock_control + - comparator + - counter + - dac + - dma + - entropy + - gpio + - flash + - i2c + - led + - pinctrl + - pwm + - spi + - uart + - watchdog +vendor: ezurio diff --git a/boards/ezurio/lyra_24_dvk/lyra_24_dvk_p10_defconfig b/boards/ezurio/lyra_24_dvk/lyra_24_dvk_p10_defconfig new file mode 100644 index 000000000000..363b0169db67 --- /dev/null +++ b/boards/ezurio/lyra_24_dvk/lyra_24_dvk_p10_defconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2022 Silicon Labs +# Copyright (c) 2026 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_REGULATOR=y diff --git a/boards/ezurio/lyra_24_dvk/lyra_24_dvk_p20.dts b/boards/ezurio/lyra_24_dvk/lyra_24_dvk_p20.dts new file mode 100644 index 000000000000..4dfcb43ca555 --- /dev/null +++ b/boards/ezurio/lyra_24_dvk/lyra_24_dvk_p20.dts @@ -0,0 +1,15 @@ +/* + * Copyright The Zephyr Project Contributors + * Copyright (c) 2026 Ezurio LLC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "lyra_24_dvk.dtsi" + +/ { + model = "Ezurio Lyra 24 P20 DVK"; + compatible = "ezurio,lyra_24_dvk_p20", "silabs,efr32bg24"; +}; diff --git a/boards/ezurio/lyra_24_dvk/lyra_24_dvk_p20.yaml b/boards/ezurio/lyra_24_dvk/lyra_24_dvk_p20.yaml new file mode 100644 index 000000000000..e3b679696b3e --- /dev/null +++ b/boards/ezurio/lyra_24_dvk/lyra_24_dvk_p20.yaml @@ -0,0 +1,28 @@ +identifier: lyra_24_dvk_p20 +name: Lyra 24 P20 DVK +type: mcu +arch: arm +ram: 256 +flash: 728 +toolchain: + - zephyr + - gnuarmemb +supported: + - adc + - bluetooth + - clock_control + - comparator + - counter + - dac + - dma + - entropy + - gpio + - flash + - i2c + - led + - pinctrl + - pwm + - spi + - uart + - watchdog +vendor: ezurio diff --git a/boards/ezurio/lyra_24_dvk/lyra_24_dvk_p20_defconfig b/boards/ezurio/lyra_24_dvk/lyra_24_dvk_p20_defconfig new file mode 100644 index 000000000000..363b0169db67 --- /dev/null +++ b/boards/ezurio/lyra_24_dvk/lyra_24_dvk_p20_defconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2022 Silicon Labs +# Copyright (c) 2026 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_REGULATOR=y diff --git a/boards/ezurio/lyra_24_dvk/lyra_24_dvk_p20rf.dts b/boards/ezurio/lyra_24_dvk/lyra_24_dvk_p20rf.dts new file mode 100644 index 000000000000..98a70116c064 --- /dev/null +++ b/boards/ezurio/lyra_24_dvk/lyra_24_dvk_p20rf.dts @@ -0,0 +1,15 @@ +/* + * Copyright The Zephyr Project Contributors + * Copyright (c) 2026 Ezurio LLC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "lyra_24_dvk.dtsi" + +/ { + model = "Ezurio Lyra 24 P20RF DVK"; + compatible = "ezurio,lyra_24_dvk_p20rf", "silabs,efr32bg24"; +}; diff --git a/boards/ezurio/lyra_24_dvk/lyra_24_dvk_p20rf.yaml b/boards/ezurio/lyra_24_dvk/lyra_24_dvk_p20rf.yaml new file mode 100644 index 000000000000..8d06182bc28d --- /dev/null +++ b/boards/ezurio/lyra_24_dvk/lyra_24_dvk_p20rf.yaml @@ -0,0 +1,28 @@ +identifier: lyra_24_dvk_p20rf +name: Lyra 24 P20RF DVK +type: mcu +arch: arm +ram: 256 +flash: 728 +toolchain: + - zephyr + - gnuarmemb +supported: + - adc + - bluetooth + - clock_control + - comparator + - counter + - dac + - dma + - entropy + - gpio + - flash + - i2c + - led + - pinctrl + - pwm + - spi + - uart + - watchdog +vendor: ezurio diff --git a/boards/ezurio/lyra_24_dvk/lyra_24_dvk_p20rf_defconfig b/boards/ezurio/lyra_24_dvk/lyra_24_dvk_p20rf_defconfig new file mode 100644 index 000000000000..363b0169db67 --- /dev/null +++ b/boards/ezurio/lyra_24_dvk/lyra_24_dvk_p20rf_defconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2022 Silicon Labs +# Copyright (c) 2026 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_REGULATOR=y diff --git a/boards/ezurio/lyra_24_dvk/lyra_24_dvk_s10.dts b/boards/ezurio/lyra_24_dvk/lyra_24_dvk_s10.dts new file mode 100644 index 000000000000..bdcbe5fec90f --- /dev/null +++ b/boards/ezurio/lyra_24_dvk/lyra_24_dvk_s10.dts @@ -0,0 +1,15 @@ +/* + * Copyright The Zephyr Project Contributors + * Copyright (c) 2026 Ezurio LLC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "lyra_24_dvk.dtsi" + +/ { + model = "Ezurio Lyra 24 S10 DVK"; + compatible = "ezurio,lyra_24_dvk_s10", "silabs,efr32bg24"; +}; diff --git a/boards/ezurio/lyra_24_dvk/lyra_24_dvk_s10.yaml b/boards/ezurio/lyra_24_dvk/lyra_24_dvk_s10.yaml new file mode 100644 index 000000000000..f616ac98c3f9 --- /dev/null +++ b/boards/ezurio/lyra_24_dvk/lyra_24_dvk_s10.yaml @@ -0,0 +1,28 @@ +identifier: lyra_24_dvk_s10 +name: Lyra 24 S10 DVK +type: mcu +arch: arm +ram: 256 +flash: 728 +toolchain: + - zephyr + - gnuarmemb +supported: + - adc + - bluetooth + - clock_control + - comparator + - counter + - dac + - dma + - entropy + - gpio + - flash + - i2c + - led + - pinctrl + - pwm + - spi + - uart + - watchdog +vendor: ezurio diff --git a/boards/ezurio/lyra_24_dvk/lyra_24_dvk_s10_defconfig b/boards/ezurio/lyra_24_dvk/lyra_24_dvk_s10_defconfig new file mode 100644 index 000000000000..363b0169db67 --- /dev/null +++ b/boards/ezurio/lyra_24_dvk/lyra_24_dvk_s10_defconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2022 Silicon Labs +# Copyright (c) 2026 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_REGULATOR=y diff --git a/boards/ezurio/lyra_24_dvk/pre_dt_board.cmake b/boards/ezurio/lyra_24_dvk/pre_dt_board.cmake new file mode 100644 index 000000000000..e0a341833fe4 --- /dev/null +++ b/boards/ezurio/lyra_24_dvk/pre_dt_board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2021 Linaro Limited +# Copyright (c) 2026 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +# SPI is implemented via usart so node name isn't spi@... +list(APPEND EXTRA_DTC_FLAGS "-Wno-spi_bus_bridge") diff --git a/boards/ezurio/lyra_dvk/Kconfig.defconfig b/boards/ezurio/lyra_dvk/Kconfig.defconfig new file mode 100644 index 000000000000..e7e04f727254 --- /dev/null +++ b/boards/ezurio/lyra_dvk/Kconfig.defconfig @@ -0,0 +1,22 @@ +# Copyright The Zephyr Project Contributors +# Copyright (c) 2026 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_LYRA_DVK_P || BOARD_LYRA_DVK_S + +config LOG_BACKEND_SWO_FREQ_HZ + default 875000 + depends on LOG_BACKEND_SWO + +config FPU + default y if SOC_GECKO_USE_RAIL || BT + +if BT + +config MAIN_STACK_SIZE + default 3072 if PM + default 2304 + +endif # BT + +endif diff --git a/boards/ezurio/lyra_dvk/Kconfig.lyra_dvk_p b/boards/ezurio/lyra_dvk/Kconfig.lyra_dvk_p new file mode 100644 index 000000000000..1bb70468e16a --- /dev/null +++ b/boards/ezurio/lyra_dvk/Kconfig.lyra_dvk_p @@ -0,0 +1,6 @@ +# Copyright The Zephyr Project Contributors +# Copyright (c) 2026 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_LYRA_DVK_P + select SOC_BGM220PC22HNA diff --git a/boards/ezurio/lyra_dvk/Kconfig.lyra_dvk_s b/boards/ezurio/lyra_dvk/Kconfig.lyra_dvk_s new file mode 100644 index 000000000000..d11b8b93609c --- /dev/null +++ b/boards/ezurio/lyra_dvk/Kconfig.lyra_dvk_s @@ -0,0 +1,6 @@ +# Copyright The Zephyr Project Contributors +# Copyright (c) 2026 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_LYRA_DVK_S + select SOC_BGM220SC22HNA diff --git a/boards/ezurio/lyra_dvk/board.cmake b/boards/ezurio/lyra_dvk/board.cmake new file mode 100644 index 000000000000..42a606a3cf90 --- /dev/null +++ b/boards/ezurio/lyra_dvk/board.cmake @@ -0,0 +1,9 @@ +# Copyright The Zephyr Project Contributors +# Copyright (c) 2026 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=EFR32BG22C224F512IM40" "--reset-after-load") +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) + +board_runner_args(silabs_commander "--device=${CONFIG_SOC}") +include(${ZEPHYR_BASE}/boards/common/silabs_commander.board.cmake) diff --git a/boards/ezurio/lyra_dvk/board.yml b/boards/ezurio/lyra_dvk/board.yml new file mode 100644 index 000000000000..8410169b2914 --- /dev/null +++ b/boards/ezurio/lyra_dvk/board.yml @@ -0,0 +1,11 @@ +boards: + - name: lyra_dvk_p + full_name: Lyra P DVK + vendor: ezurio + socs: + - name: bgm220pc22hna + - name: lyra_dvk_s + full_name: Lyra S DVK + vendor: ezurio + socs: + - name: bgm220sc22hna diff --git a/boards/ezurio/lyra_dvk/doc/img/lyra_dvk_p.webp b/boards/ezurio/lyra_dvk/doc/img/lyra_dvk_p.webp new file mode 100644 index 000000000000..03c8fee64b2e Binary files /dev/null and b/boards/ezurio/lyra_dvk/doc/img/lyra_dvk_p.webp differ diff --git a/boards/ezurio/lyra_dvk/doc/img/lyra_dvk_s.webp b/boards/ezurio/lyra_dvk/doc/img/lyra_dvk_s.webp new file mode 100644 index 000000000000..40e4a872d6d1 Binary files /dev/null and b/boards/ezurio/lyra_dvk/doc/img/lyra_dvk_s.webp differ diff --git a/boards/ezurio/lyra_dvk/doc/lyra_dvk_common_1.rst.inc b/boards/ezurio/lyra_dvk/doc/lyra_dvk_common_1.rst.inc new file mode 100644 index 000000000000..65f274d4c4c8 --- /dev/null +++ b/boards/ezurio/lyra_dvk/doc/lyra_dvk_common_1.rst.inc @@ -0,0 +1,26 @@ +.. SPDX-License-Identifier: Apache-2.0 +.. +.. Copyright (c) 2026 Ezurio LLC + +Overview +******** + +The Lyra |Lyra variant| Development Kit provides support for the Ezurio Lyra |Lyra variant| Bluetooth Low Energy v5.3 module. + +The module is based on the Silicon Laboratories |SoC| module and includes an EFR32BG22 Arm Cortex-M33 CPU. + +The Lyra |Lyra variant| module incorporates the QFN package EFR32BG22 (512kB Flash, 32kB RAM). The part features +up to |Number of IO| configurable GPIOs and BLE Radio TX Power up to |BLE TX Power|. + +The kit features a USB interface, an on-board SEGGER J-Link debugger, one user-LED and button, and +support for hardware add-on boards via a `mikroBUS`_ socket and a `Qwiic`_ connector. + +.. note:: + You can find more information about the Lyra family of modules in the `Lyra product brief`_ and on the `Lyra website`_. + + You can find more information about the Lyra |Lyra variant| module in the |Datasheet Ref|. + + You can find more information about the underlying |SoC| module in the |SoC Datasheet Ref|. + + You can find more information about the underlying EFR32BG22 SoC in the `EFR32BG22 datasheet`_ + and `EFR32BG22 reference manual`_. diff --git a/boards/ezurio/lyra_dvk/doc/lyra_dvk_common_2.rst.inc b/boards/ezurio/lyra_dvk/doc/lyra_dvk_common_2.rst.inc new file mode 100644 index 000000000000..34cc3f6c95cd --- /dev/null +++ b/boards/ezurio/lyra_dvk/doc/lyra_dvk_common_2.rst.inc @@ -0,0 +1,17 @@ +.. SPDX-License-Identifier: Apache-2.0 +.. +.. Copyright (c) 2026 Ezurio LLC + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Connections and IOs +=================== + +In the following table, the column **Name** contains Pin names. For example, PA2 +means Pin number 2 on PORTA, as used in the board's datasheets and manuals. + +The **Direction** column indicates the pin direction from the module perspective, with +I indicating Input, O Output and I/O both. diff --git a/boards/ezurio/lyra_dvk/doc/lyra_dvk_common_3.rst.inc b/boards/ezurio/lyra_dvk/doc/lyra_dvk_common_3.rst.inc new file mode 100644 index 000000000000..9dbe34e17df6 --- /dev/null +++ b/boards/ezurio/lyra_dvk/doc/lyra_dvk_common_3.rst.inc @@ -0,0 +1,54 @@ +.. SPDX-License-Identifier: Apache-2.0 +.. +.. Copyright (c) 2026 Ezurio LLC + +.. note:: + Switch SW1 is used to select I/O compatibility with legacy Bluetooth Xpress firmware. + It should be set to the C_DEV/SWO position to enable support of the SWO pin and compatibility with + the board definition files. + +System Clock +============ + +The Lyra |Lyra variant| is configured to use the 38.4 MHz external oscillator on the +board, and can operate at clock speeds of up to 76.8 MHz. + +Serial Port +=========== + +The Lyra |Lyra variant| has two USARTs and one EUART. + +* EUART0 defaults to the mikroBUS UART. +* USART0 defaults to the mikroBUS SPI port. +* USART1 is connected to the board controller and is used for the console. + +Programming and Debugging +************************* + +Applications for the |Board Quoted| board can be built, flashed, and debugged in the usual way. +See :ref:`build_an_application` and :ref:`application_run` for more details on building and running. + +.. note:: + Before using the kit, you should update the J-Link firmware + in `Simplicity Studio`_. + +Testing the LED and button +========================== + +The :zephyr:code-sample:`blinky` sample can be used to test the DVK LED. + +The :zephyr:code-sample:`button` sample can be used to test the DVK button. + +Bluetooth Low Energy +==================== + +To use Bluetooth Low Energy functionality, run the command below to retrieve necessary binary +blobs from the Silicon Labs HAL repository. + +.. code-block:: console + + west blobs fetch hal_silabs + +Then build the Zephyr kernel and a Bluetooth sample with the following +command. The :zephyr:code-sample:`bluetooth_observer` sample application is used in +this example. diff --git a/boards/ezurio/lyra_dvk/doc/lyra_dvk_common_4.rst.inc b/boards/ezurio/lyra_dvk/doc/lyra_dvk_common_4.rst.inc new file mode 100644 index 000000000000..b7254e695bc3 --- /dev/null +++ b/boards/ezurio/lyra_dvk/doc/lyra_dvk_common_4.rst.inc @@ -0,0 +1,24 @@ +.. SPDX-License-Identifier: Apache-2.0 +.. +.. Copyright (c) 2026 Ezurio LLC + +.. _Lyra product brief: + https://www.ezurio.com/documentation/product-brief-lyra-series + +.. _Lyra website: + https://www.ezurio.com/wireless-modules/bluetooth-modules/bluetooth-5-modules/lyra-series-bluetooth-53-modules + +.. _EFR32BG22 datasheet: + https://www.silabs.com/documents/public/data-sheets/efr32bg22-datasheet.pdf + +.. _EFR32BG22 reference manual: + https://www.silabs.com/documents/public/reference-manuals/efr32xg22-rm.pdf + +.. _mikroBUS: + https://www.mikroe.com/mikrobus + +.. _Qwiic: + https://www.sparkfun.com/qwiic + +.. _Simplicity Studio: + https://www.silabs.com/software-and-tools/simplicity-studio diff --git a/boards/ezurio/lyra_dvk/doc/lyra_dvk_p.rst b/boards/ezurio/lyra_dvk/doc/lyra_dvk_p.rst new file mode 100644 index 000000000000..6b0fb1f9387f --- /dev/null +++ b/boards/ezurio/lyra_dvk/doc/lyra_dvk_p.rst @@ -0,0 +1,102 @@ +.. zephyr:board:: lyra_dvk_p + +.. |Lyra variant| replace:: P +.. |Datasheet Ref| replace:: `Lyra P datasheet`_ +.. |SoC| replace:: BGM220PC22HNA +.. |SoC Datasheet Ref| replace:: `BGM220P datasheet`_ +.. |Number of IO| replace:: 24 +.. |BLE TX Power| replace:: 8dBm +.. |Board Quoted| replace:: ``lyra_dvk_p`` +.. |User Guide Ref| replace:: `Lyra P DVK user guide`_ +.. |Schematics Ref| replace:: `Lyra P DVK schematics`_ + +.. include:: lyra_dvk_common_1.rst.inc + +Hardware +******** + +The Lyra P DVK has two crystal oscillators as follows. + +* High-frequency 38.4 MHz crystal oscillator (HFXO) +* Low-frequency 32.768 kHz crystal oscillator (LFXO) + +Both crystal oscillators are fitted within the Lyra P module. + +The module supports an on-chip Bluetooth Low Energy antenna. + +Full details of the DVK can be found in the |User Guide Ref| and |Schematics Ref|. + +.. include:: lyra_dvk_common_2.rst.inc + ++-------+-------------+-------------------------------------+-----------+ +| Name | Function | Usage | Direction | ++=======+=============+=====================================+===========+ +| PA0 | USART1_TX | UART Console VCOM_TX | O | ++-------+-------------+-------------------------------------+-----------+ +| PA1 | SWD_SWCLK | JLink SWCLK | I | ++-------+-------------+-------------------------------------+-----------+ +| PA2 | SWD_SWDIO | JLink SWDIO | I/O | ++-------+-------------+-------------------------------------+-----------+ +| PA3 | SWD_SWO | JLink SWO | O | ++-------+-------------+-------------------------------------+-----------+ +| PA4 | USART1_RTS | UART Console VCOM_RTS | O | ++-------+-------------+-------------------------------------+-----------+ +| PA5 | USART1_CTS | UART Console VCOM_CTS | I | ++-------+-------------+-------------------------------------+-----------+ +| PA6 | GPIO | Breakout Connector GPIO | I/O | ++-------+-------------+-------------------------------------+-----------+ +| PA7 | USART1_RX | UART Console VCOM_RX | I | ++-------+-------------+-------------------------------------+-----------+ +| PA8 | GPIO | LED 0 | O | ++-------+-------------+-------------------------------------+-----------+ +| PB0 | GPIO | mikroBUS AN | I | ++-------+-------------+-------------------------------------+-----------+ +| PB1 | EUART0_TX | mikroBUS TX | O | ++-------+-------------+-------------------------------------+-----------+ +| PB2 | EUART0_RX | mikroBUS RX | I | ++-------+-------------+-------------------------------------+-----------+ +| PB3 | GPIO | mikroBUS INT | I | ++-------+-------------+-------------------------------------+-----------+ +| PB4 | GPIO | mikroBUS PWM | O | ++-------+-------------+-------------------------------------+-----------+ +| PC0 | PTI_FRAME | Packet Trace Interface FRAME | O | ++-------+-------------+-------------------------------------+-----------+ +| PC1 | PTI_DATA | Packet Trace Interface DATA | O | ++-------+-------------+-------------------------------------+-----------+ +| PC2 | USART0_SCK | mikroBUS SCK | O | ++-------+-------------+-------------------------------------+-----------+ +| PC3 | GPIO | mikroBUS CS | O | ++-------+-------------+-------------------------------------+-----------+ +| PC4 | USART0_TX | mikroBUS MOSI | O | ++-------+-------------+-------------------------------------+-----------+ +| PC5 | USART0_RX | mikroBUS MISO | I | ++-------+-------------+-------------------------------------+-----------+ +| PC6 | GPIO | mikroBUS RST | O | ++-------+-------------+-------------------------------------+-----------+ +| PC7 | GPIO | Button 0 | I | ++-------+-------------+-------------------------------------+-----------+ +| PD2 | I2C0_SCL | mikroBUS SCL / Qwiic SCL | I/O | ++-------+-------------+-------------------------------------+-----------+ +| PD3 | I2C0_SDA | mikroBUS SDA / Qwiic SDA | I/O | ++-------+-------------+-------------------------------------+-----------+ + +.. include:: lyra_dvk_common_3.rst.inc + +.. zephyr-app-commands:: + :zephyr-app: samples/bluetooth/observer + :board: lyra_dvk_p + :goals: build + +.. include:: lyra_dvk_common_4.rst.inc + +.. _Lyra P datasheet: + https://www.ezurio.com/documentation/datasheet-lyra-p + +.. _BGM220P datasheet: + https://www.silabs.com/documents/public/data-sheets/bgm220p-datasheet.pdf + +.. _Lyra P DVK user guide: + https://www.ezurio.com/documentation/user-guide-lyra-p-development-kit + +.. _Lyra P DVK schematics: + https://www.ezurio.com/documentation/schematic-pcb-assembly-lyra-p-dev-board diff --git a/boards/ezurio/lyra_dvk/doc/lyra_dvk_s.rst b/boards/ezurio/lyra_dvk/doc/lyra_dvk_s.rst new file mode 100644 index 000000000000..c4b996e23c1e --- /dev/null +++ b/boards/ezurio/lyra_dvk/doc/lyra_dvk_s.rst @@ -0,0 +1,106 @@ +.. zephyr:board:: lyra_dvk_s + +.. |Lyra variant| replace:: S +.. |Datasheet Ref| replace:: `Lyra S datasheet`_ +.. |SoC| replace:: BGM220SC22HNA +.. |SoC Datasheet Ref| replace:: `BGM220S datasheet`_ +.. |Number of IO| replace:: 25 +.. |BLE TX Power| replace:: 6dBm +.. |Board Quoted| replace:: ``lyra_dvk_s`` +.. |User Guide Ref| replace:: `Lyra S DVK user guide`_ +.. |Schematics Ref| replace:: `Lyra S DVK schematics`_ + +.. include:: lyra_dvk_common_1.rst.inc + +Hardware +******** + +The Lyra S DVK has two crystal oscillators as follows. + +* High-frequency 38.4 MHz crystal oscillator (HFXO) +* Low-frequency 32.768 kHz crystal oscillator (LFXO) + +The high-frequency crystal oscillator is fitted within the Lyra S module. + +The low-frequency crystal oscillator is fitted to the DVK and is external to the Lyra S module. + +The module supports an on-chip or external Bluetooth Low Energy antenna. + +Full details of the DVK can be found in the |User Guide Ref| and |Schematics Ref|. + +.. include:: lyra_dvk_common_2.rst.inc + ++-------+-------------+-------------------------------------+-----------+ +| Name | Function | Usage | Direction | ++=======+=============+=====================================+===========+ +| PA0 | USART1_TX | UART Console VCOM_TX | O | ++-------+-------------+-------------------------------------+-----------+ +| PA1 | SWD_SWCLK | JLink SWCLK | I | ++-------+-------------+-------------------------------------+-----------+ +| PA2 | SWD_SWDIO | JLink SWDIO | I/O | ++-------+-------------+-------------------------------------+-----------+ +| PA3 | SWD_SWO | JLink SWO | O | ++-------+-------------+-------------------------------------+-----------+ +| PA4 | USART1_RTS | UART Console VCOM_RTS | O | ++-------+-------------+-------------------------------------+-----------+ +| PA5 | USART1_CTS | UART Console VCOM_CTS | I | ++-------+-------------+-------------------------------------+-----------+ +| PA6 | GPIO | Button 0 | I | ++-------+-------------+-------------------------------------+-----------+ +| PA7 | USART1_RX | UART Console VCOM_RX | I | ++-------+-------------+-------------------------------------+-----------+ +| PA8 | GPIO | LED 0 | O | ++-------+-------------+-------------------------------------+-----------+ +| PB0 | GPIO | mikroBUS AN | I | ++-------+-------------+-------------------------------------+-----------+ +| PB1 | EUART0_TX | mikroBUS TX | O | ++-------+-------------+-------------------------------------+-----------+ +| PB2 | EUART0_RX | mikroBUS RX | I | ++-------+-------------+-------------------------------------+-----------+ +| PB3 | GPIO | mikroBUS INT | I | ++-------+-------------+-------------------------------------+-----------+ +| PB4 | GPIO | mikroBUS PWM | O | ++-------+-------------+-------------------------------------+-----------+ +| PC0 | PTI_FRAME | Packet Trace Interface FRAME | O | ++-------+-------------+-------------------------------------+-----------+ +| PC1 | PTI_DATA | Packet Trace Interface DATA | O | ++-------+-------------+-------------------------------------+-----------+ +| PC2 | USART0_SCK | mikroBUS SCK | O | ++-------+-------------+-------------------------------------+-----------+ +| PC3 | GPIO | mikroBUS CS | O | ++-------+-------------+-------------------------------------+-----------+ +| PC4 | USART0_TX | mikroBUS MOSI | O | ++-------+-------------+-------------------------------------+-----------+ +| PC5 | USART0_RX | mikroBUS MISO | I | ++-------+-------------+-------------------------------------+-----------+ +| PC6 | GPIO | mikroBUS RST | O | ++-------+-------------+-------------------------------------+-----------+ +| PD0 | LFXO | LFXO | N/A | ++-------+-------------+-------------------------------------+-----------+ +| PD1 | LFXO | LFXO | N/A | ++-------+-------------+-------------------------------------+-----------+ +| PD2 | I2C0_SCL | mikroBUS SCL / Qwiic SCL | I/O | ++-------+-------------+-------------------------------------+-----------+ +| PD3 | I2C0_SDA | mikroBUS SDA / Qwiic SDA | I/O | ++-------+-------------+-------------------------------------+-----------+ + +.. include:: lyra_dvk_common_3.rst.inc + +.. zephyr-app-commands:: + :zephyr-app: samples/bluetooth/observer + :board: lyra_dvk_s + :goals: build + +.. include:: lyra_dvk_common_4.rst.inc + +.. _Lyra S datasheet: + https://www.ezurio.com/documentation/datasheet-lyra-s + +.. _BGM220S datasheet: + https://www.silabs.com/documents/public/data-sheets/bgm220s-datasheet.pdf + +.. _Lyra S DVK user guide: + https://www.ezurio.com/documentation/user-guide-lyra-s-development-kit + +.. _Lyra S DVK schematics: + https://www.ezurio.com/documentation/schematic-pcb-assembly-lyra-s-dev-board diff --git a/boards/ezurio/lyra_dvk/lyra_dvk-pinctrl.dtsi b/boards/ezurio/lyra_dvk/lyra_dvk-pinctrl.dtsi new file mode 100644 index 000000000000..5d3979e1de94 --- /dev/null +++ b/boards/ezurio/lyra_dvk/lyra_dvk-pinctrl.dtsi @@ -0,0 +1,90 @@ +/* + * Copyright The Zephyr Project Contributors + * Copyright (c) 2026 Ezurio LLC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + timer0_default: timer0_default { + group0 { + pins = ; + drive-push-pull; + output-high; + }; + }; + + usart0_default: usart0_default { + group0 { + pins = , ; + drive-push-pull; + output-high; + }; + + group1 { + pins = ; + input-enable; + silabs,input-filter; + }; + }; + + usart1_default: usart1_default { + group0 { + pins = , ; + drive-push-pull; + output-high; + }; + + group1 { + pins = , ; + input-enable; + silabs,input-filter; + }; + }; + + iadc0_default: iadc0_default { + group0 { + silabs,analog-bus = ; + }; + }; + + i2c0_default: i2c0_default { + group0 { + pins = , ; + bias-pull-up; + drive-open-drain; + }; + }; + + euart0_default: euart0_default { + group0 { + pins = ; + drive-push-pull; + output-high; + }; + + group1 { + pins = ; + input-enable; + silabs,input-filter; + }; + }; + + itm_default: itm_default { + group0 { + pins = ; + drive-push-pull; + output-high; + }; + }; + + pti_default: pti_default { + group0 { + pins = , ; + drive-push-pull; + output-high; + }; + }; +}; diff --git a/boards/ezurio/lyra_dvk/lyra_dvk.dtsi b/boards/ezurio/lyra_dvk/lyra_dvk.dtsi new file mode 100644 index 000000000000..8dec8dde13c5 --- /dev/null +++ b/boards/ezurio/lyra_dvk/lyra_dvk.dtsi @@ -0,0 +1,283 @@ +/* + * Copyright The Zephyr Project Contributors + * Copyright (c) 2026 Ezurio LLC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include "lyra_dvk-pinctrl.dtsi" + +/ { + chosen { + zephyr,bt-hci = &bt_hci_silabs; + zephyr,code-partition = &slot0_partition; + zephyr,console = &usart1; + zephyr,flash = &flash0; + zephyr,shell-uart = &usart1; + zephyr,sram = &sram0; + zephyr,uart-pipe = &usart1; + }; + + aliases { + led0 = &led0; + pwm-led0 = &pwm_led0; + sw0 = &button0; + watchdog0 = &wdog0; + + /* If enabled, MCUboot uses this for recovery mode entrance */ + mcuboot-led0 = &led0; + mcuboot-button0 = &button0; + }; + + leds { + compatible = "gpio-leds"; + + led0: led_0 { + gpios = <&gpioa 8 GPIO_ACTIVE_HIGH>; + }; + }; + + mikrobus_header: mikrobus-connector { + compatible = "mikro-bus"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0>; + gpio-map-pass-thru = <0 GPIO_DT_FLAGS_MASK>; + gpio-map = <0 0 &gpiob 0 0>, /* AN */ + <1 0 &gpioc 6 0>, /* RST */ + <2 0 &gpioc 3 0>, /* CS */ + <3 0 &gpioc 2 0>, /* SCK */ + <4 0 &gpioc 5 0>, /* MISO */ + <5 0 &gpioc 4 0>, /* MOSI */ + <6 0 &gpiob 4 0>, /* PWM */ + <7 0 &gpiob 3 0>, /* INT */ + <8 0 &gpiob 2 0>, /* RX */ + <9 0 &gpiob 1 0>, /* TX */ + <10 0 &gpiod 2 0>, /* SCL */ + <11 0 &gpiod 3 0>; /* SDA */ + }; + + pwmleds { + compatible = "pwm-leds"; + + pwm_led0: pwm_led_0 { + pwms = <&timer0_pwm 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + }; + }; + + qwiic_connector: stemma-qt-connector { + compatible = "stemma-qt-connector"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0>; + gpio-map-pass-thru = <0 GPIO_DT_FLAGS_MASK>; + gpio-map = <0 0 &gpiod 2 0>, /* SCL */ + <1 0 &gpiod 3 0>; /* SDA */ + }; + + mikrobus_adc: zephyr,user { + io-channels = <&adc0 0>; + }; +}; + +&em23grpaclk { + clocks = <&lfxo>; +}; + +&em4grpaclk { + clocks = <&lfxo>; +}; + +&prortcclk { + clocks = <&lfxo>; +}; + +&rtccclk { + clocks = <&lfxo>; +}; + +&wdog0clk { + clocks = <&lfxo>; +}; + +&cpu0 { + clock-frequency = ; +}; + +&hfrcodpll { + clock-frequency = ; + clocks = <&hfxo>; + dpll-autorecover; + dpll-edge = "fall"; + dpll-lock = "phase"; + dpll-m = <3839>; + dpll-n = <3839>; +}; + +&hfxo { + ctune = <140>; + precision = <50>; + status = "okay"; +}; + +&lfxo { + ctune = <63>; + precision = <50>; + status = "okay"; +}; + +&gpio { + status = "okay"; +}; + +&gpioa { + status = "okay"; +}; + +&gpiob { + status = "okay"; +}; + +&gpioc { + status = "okay"; +}; + +&gpiod { + status = "okay"; +}; + +&timer0 { + status = "okay"; + + timer0_pwm: pwm { + pinctrl-0 = <&timer0_default>; + pinctrl-names = "default"; + status = "okay"; + }; +}; + +&usart0 { + compatible = "silabs,usart-spi"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&usart0_default>; + pinctrl-names = "default"; + cs-gpios = <&gpioc 3 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&usart1 { + compatible = "silabs,usart-uart"; + current-speed = <115200>; + pinctrl-0 = <&usart1_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&dcdc { + regulator-boot-on; + regulator-initial-mode = ; + status = "okay"; +}; + +&rtcc0 { + status = "okay"; +}; + +&adc0 { + pinctrl-0 = <&iadc0_default>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + channel@0 { + reg = <0>; + zephyr,acquisition-time = ; + zephyr,gain = "ADC_GAIN_1"; + zephyr,input-positive = ; + zephyr,reference = "ADC_REF_VDD_1"; + zephyr,resolution = <12>; + zephyr,vref-mv = <3300>; + }; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + status = "disabled"; +}; + +&wdog0 { + status = "okay"; +}; + +&euart0 { + pinctrl-0 = <&euart0_default>; + pinctrl-names = "default"; + status = "disabled"; +}; + +&trng { + status = "okay"; +}; + +&itm { + pinctrl-0 = <&itm_default>; + pinctrl-names = "default"; + swo-ref-frequency = ; +}; + +&bt_hci_silabs { + status = "okay"; +}; + +&pti { + pinctrl-0 = <&pti_default>; + pinctrl-names = "default"; +}; + +mikrobus_i2c: &i2c0 {}; + +mikrobus_spi: &usart0 {}; + +mikrobus_uart: &euart0 {}; + +zephyr_i2c: &i2c0 {}; + +zephyr_spi: &usart0 {}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 48 KiB for the bootloader */ + boot_partition: partition@0 { + reg = <0x00000000 DT_SIZE_K(48)>; + label = "mcuboot"; + read-only; + }; + + /* Reserve 224 KiB for the application in slot 0 */ + slot0_partition: partition@c000 { + reg = <0x0000c000 DT_SIZE_K(224)>; + label = "image-0"; + }; + + /* Reserve 224 KiB for the application in slot 1 */ + slot1_partition: partition@44000 { + reg = <0x00044000 DT_SIZE_K(224)>; + label = "image-1"; + }; + + /* Set 16 KiB of storage at the end of the 512 KiB of flash */ + storage_partition: partition@7c000 { + reg = <0x0007c000 DT_SIZE_K(16)>; + label = "storage"; + }; + }; +}; diff --git a/boards/ezurio/lyra_dvk/lyra_dvk_p.dts b/boards/ezurio/lyra_dvk/lyra_dvk_p.dts new file mode 100644 index 000000000000..682069384965 --- /dev/null +++ b/boards/ezurio/lyra_dvk/lyra_dvk_p.dts @@ -0,0 +1,24 @@ +/* + * Copyright The Zephyr Project Contributors + * Copyright (c) 2026 Ezurio LLC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "lyra_dvk.dtsi" + +/ { + model = "Ezurio Lyra P DVK"; + compatible = "ezurio,lyra_dvk_p", "silabs,efr32bg22"; + + buttons { + compatible = "gpio-keys"; + + button0: button_0 { + gpios = <&gpioc 7 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; +}; diff --git a/boards/ezurio/lyra_dvk/lyra_dvk_p.yaml b/boards/ezurio/lyra_dvk/lyra_dvk_p.yaml new file mode 100644 index 000000000000..a3fc634e1ecb --- /dev/null +++ b/boards/ezurio/lyra_dvk/lyra_dvk_p.yaml @@ -0,0 +1,27 @@ +identifier: lyra_dvk_p +name: Lyra P DVK +type: mcu +arch: arm +ram: 32 +flash: 224 +toolchain: + - zephyr + - gnuarmemb +supported: + - adc + - bluetooth + - clock_control + - comparator + - counter + - dma + - entropy + - gpio + - flash + - i2c + - led + - pinctrl + - pwm + - spi + - uart + - watchdog +vendor: ezurio diff --git a/boards/ezurio/lyra_dvk/lyra_dvk_p_defconfig b/boards/ezurio/lyra_dvk/lyra_dvk_p_defconfig new file mode 100644 index 000000000000..5ee421b84580 --- /dev/null +++ b/boards/ezurio/lyra_dvk/lyra_dvk_p_defconfig @@ -0,0 +1,10 @@ +# Copyright The Zephyr Project Contributors +# Copyright (c) 2026 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/ezurio/lyra_dvk/lyra_dvk_s.dts b/boards/ezurio/lyra_dvk/lyra_dvk_s.dts new file mode 100644 index 000000000000..b8f0f5db8b2b --- /dev/null +++ b/boards/ezurio/lyra_dvk/lyra_dvk_s.dts @@ -0,0 +1,24 @@ +/* + * Copyright The Zephyr Project Contributors + * Copyright (c) 2026 Ezurio LLC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "lyra_dvk.dtsi" + +/ { + model = "Ezurio Lyra S DVK"; + compatible = "ezurio,lyra_dvk_s", "silabs,efr32bg22"; + + buttons { + compatible = "gpio-keys"; + + button0: button_0 { + gpios = <&gpioa 6 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; +}; diff --git a/boards/ezurio/lyra_dvk/lyra_dvk_s.yaml b/boards/ezurio/lyra_dvk/lyra_dvk_s.yaml new file mode 100644 index 000000000000..11b37581581a --- /dev/null +++ b/boards/ezurio/lyra_dvk/lyra_dvk_s.yaml @@ -0,0 +1,27 @@ +identifier: lyra_dvk_s +name: Lyra S DVK +type: mcu +arch: arm +ram: 32 +flash: 224 +toolchain: + - zephyr + - gnuarmemb +supported: + - adc + - bluetooth + - clock_control + - comparator + - counter + - dma + - entropy + - gpio + - flash + - i2c + - led + - pinctrl + - pwm + - spi + - uart + - watchdog +vendor: ezurio diff --git a/boards/ezurio/lyra_dvk/lyra_dvk_s_defconfig b/boards/ezurio/lyra_dvk/lyra_dvk_s_defconfig new file mode 100644 index 000000000000..5ee421b84580 --- /dev/null +++ b/boards/ezurio/lyra_dvk/lyra_dvk_s_defconfig @@ -0,0 +1,10 @@ +# Copyright The Zephyr Project Contributors +# Copyright (c) 2026 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/ezurio/lyra_dvk/pre_dt_board.cmake b/boards/ezurio/lyra_dvk/pre_dt_board.cmake new file mode 100644 index 000000000000..e0a341833fe4 --- /dev/null +++ b/boards/ezurio/lyra_dvk/pre_dt_board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2021 Linaro Limited +# Copyright (c) 2026 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +# SPI is implemented via usart so node name isn't spi@... +list(APPEND EXTRA_DTC_FLAGS "-Wno-spi_bus_bridge") diff --git a/boards/ezurio/mg100/mg100.dts b/boards/ezurio/mg100/mg100.dts index f7505e18fb79..3a46456d5425 100644 --- a/boards/ezurio/mg100/mg100.dts +++ b/boards/ezurio/mg100/mg100.dts @@ -207,7 +207,7 @@ /* 896K */ slot0_partition: partition@18000 { label = "image-0"; - reg = <0x00018000 0x000E0000>; + reg = <0x00018000 0x000e0000>; }; /* @@ -235,13 +235,13 @@ /* 896K */ slot1_partition: partition@0 { label = "image-1"; - reg = <0x00000000 0x000E0000>; + reg = <0x00000000 0x000e0000>; }; /* 128K */ - scratch_partition: partition@E0000 { + scratch_partition: partition@e0000 { label = "image-scratch"; - reg = <0x000E0000 0x00020000>; + reg = <0x000e0000 0x00020000>; }; /* 7MB */ diff --git a/boards/ezurio/pinnacle_100_dvk/pinnacle_100_dvk.dts b/boards/ezurio/pinnacle_100_dvk/pinnacle_100_dvk.dts index 5660a0624d8f..f5b58ea54a9f 100644 --- a/boards/ezurio/pinnacle_100_dvk/pinnacle_100_dvk.dts +++ b/boards/ezurio/pinnacle_100_dvk/pinnacle_100_dvk.dts @@ -220,7 +220,7 @@ /* 896K */ slot0_partition: partition@18000 { label = "image-0"; - reg = <0x00018000 0x000E0000>; + reg = <0x00018000 0x000e0000>; }; /* @@ -248,13 +248,13 @@ /* 896K */ slot1_partition: partition@0 { label = "image-1"; - reg = <0x00000000 0x000E0000>; + reg = <0x00000000 0x000e0000>; }; /* 128K */ - scratch_partition: partition@E0000 { + scratch_partition: partition@e0000 { label = "image-scratch"; - reg = <0x000E0000 0x00020000>; + reg = <0x000e0000 0x00020000>; }; /* 7MB */ diff --git a/boards/ezurio/rm126x_dvk/Kconfig.defconfig b/boards/ezurio/rm126x_dvk/Kconfig.defconfig new file mode 100644 index 000000000000..d5d17b8b979a --- /dev/null +++ b/boards/ezurio/rm126x_dvk/Kconfig.defconfig @@ -0,0 +1,14 @@ +# Copyright The Zephyr Project Contributors +# Copyright (c) 2026 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_RM126X_DVK_RM1261 || BOARD_RM126X_DVK_RM1262 + +config LOG_BACKEND_SWO_FREQ_HZ + default 875000 + depends on LOG_BACKEND_SWO + +config FPU + default y + +endif diff --git a/boards/ezurio/rm126x_dvk/Kconfig.rm126x_dvk_rm1261 b/boards/ezurio/rm126x_dvk/Kconfig.rm126x_dvk_rm1261 new file mode 100644 index 000000000000..e97bf8a9c050 --- /dev/null +++ b/boards/ezurio/rm126x_dvk/Kconfig.rm126x_dvk_rm1261 @@ -0,0 +1,6 @@ +# Copyright The Zephyr Project Contributors +# Copyright (c) 2026 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RM126X_DVK_RM1261 + select SOC_EFR32BG22C224F512IM40 diff --git a/boards/ezurio/rm126x_dvk/Kconfig.rm126x_dvk_rm1262 b/boards/ezurio/rm126x_dvk/Kconfig.rm126x_dvk_rm1262 new file mode 100644 index 000000000000..3adb9e1159f1 --- /dev/null +++ b/boards/ezurio/rm126x_dvk/Kconfig.rm126x_dvk_rm1262 @@ -0,0 +1,6 @@ +# Copyright The Zephyr Project Contributors +# Copyright (c) 2026 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RM126X_DVK_RM1262 + select SOC_EFR32BG22C224F512IM40 diff --git a/boards/ezurio/rm126x_dvk/board.cmake b/boards/ezurio/rm126x_dvk/board.cmake new file mode 100644 index 000000000000..42a606a3cf90 --- /dev/null +++ b/boards/ezurio/rm126x_dvk/board.cmake @@ -0,0 +1,9 @@ +# Copyright The Zephyr Project Contributors +# Copyright (c) 2026 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=EFR32BG22C224F512IM40" "--reset-after-load") +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) + +board_runner_args(silabs_commander "--device=${CONFIG_SOC}") +include(${ZEPHYR_BASE}/boards/common/silabs_commander.board.cmake) diff --git a/boards/ezurio/rm126x_dvk/board.yml b/boards/ezurio/rm126x_dvk/board.yml new file mode 100644 index 000000000000..4038cbcb77e2 --- /dev/null +++ b/boards/ezurio/rm126x_dvk/board.yml @@ -0,0 +1,11 @@ +boards: + - name: rm126x_dvk_rm1261 + full_name: RM1261 DVK + vendor: ezurio + socs: + - name: efr32bg22c224f512im40 + - name: rm126x_dvk_rm1262 + full_name: RM1262 DVK + vendor: ezurio + socs: + - name: efr32bg22c224f512im40 diff --git a/boards/ezurio/rm126x_dvk/doc/img/rm126x_dvk_rm1261.webp b/boards/ezurio/rm126x_dvk/doc/img/rm126x_dvk_rm1261.webp new file mode 100644 index 000000000000..0979a17fae92 Binary files /dev/null and b/boards/ezurio/rm126x_dvk/doc/img/rm126x_dvk_rm1261.webp differ diff --git a/boards/ezurio/rm126x_dvk/doc/img/rm126x_dvk_rm1262.webp b/boards/ezurio/rm126x_dvk/doc/img/rm126x_dvk_rm1262.webp new file mode 100644 index 000000000000..0979a17fae92 Binary files /dev/null and b/boards/ezurio/rm126x_dvk/doc/img/rm126x_dvk_rm1262.webp differ diff --git a/boards/ezurio/rm126x_dvk/doc/rm126x_dvk_common_1.rst.inc b/boards/ezurio/rm126x_dvk/doc/rm126x_dvk_common_1.rst.inc new file mode 100644 index 000000000000..13dda7b27a12 --- /dev/null +++ b/boards/ezurio/rm126x_dvk/doc/rm126x_dvk_common_1.rst.inc @@ -0,0 +1,206 @@ +.. SPDX-License-Identifier: Apache-2.0 +.. +.. Copyright (c) 2026 Ezurio LLC + +Overview +******** + +The |RM126x variant| Development Kit provides support for the Ezurio |RM126x variant| LoRa module. + +The module includes an EFR32BG22 Arm Cortex-M33 CPU and a Semtech |SX126x variant| LoRa radio. + +The |RM126x variant| module incorporates the QFN package EFR32BG22 (512kB Flash, 32kB RAM). The part features +up to 16 configurable GPIOs and Lora Radio TX Power up to |LoRa TX Power|. + +The kit features a USB interface, an on-board SEGGER J-Link debugger, one user-LED and button, and +support for hardware add-on boards via a `mikroBUS`_ socket and a `Qwiic`_ connector. + +.. note:: + You can find more information about the RM126x family of modules in the `RM126x product brief`_, the `RM126x datasheet`_ + and on the `RM126x website`_. + + You can find more information about the underlying EFR32BG22 SoC in the `EFR32BG22 datasheet`_ + and `EFR32BG22 reference manual`_. + + You can find more information about the Semtech |SX126x variant| LoRa radio in the `SX126x datasheet`_. + +Hardware +******** + +The |RM126x variant| DVK has one crystal oscillator as follows. + +* Low-frequency 32.768 kHz crystal oscillator (LFXO) + +The crystal oscillator is fitted within the |RM126x variant| module. + +The module supports an external LoRa antenna. + +.. note:: + The MHF4 connector exposed via the |RM126x variant| shield can should be used for antenna connectivity. + +Full details of the DVK can be found in the `RM126x DVK user guide`_ and |Schematics Ref|. + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +DVK Connections and IOs +======================= + +In the following table, the column **Name** contains Pin names. For example, PA2 +means Pin number 2 on PORTA, as used in the board's datasheets and manuals. + +The **Direction** column indicates the pin direction from the module perspective, with +I indicating Input, O Output and I/O both. + ++-------+----------------------+--------------------------------------------------------+-----------+ +| Name | Function | Usage | Direction | ++=======+======================+========================================================+===========+ +| PA1 | SWD_SWCLK | JLink SWCLK | I | ++-------+----------------------+--------------------------------------------------------+-----------+ +| PA2 | SWD_SWDIO | JLink SWDIO | I/O | ++-------+----------------------+--------------------------------------------------------+-----------+ +| PA3 | SWD_SWO | JLink SWO | O | ++-------+----------------------+--------------------------------------------------------+-----------+ +| PB2 | EUART0_RTS | UART Console VCOM_RTS | O | ++-------+----------------------+--------------------------------------------------------+-----------+ +| PB3 | EUART0_RX | UART Console VCOM_RX | I | ++-------+----------------------+--------------------------------------------------------+-----------+ +| PB4 | EUART0_CTS | UART Console VCOM_CTS | I | ++-------+----------------------+--------------------------------------------------------+-----------+ +| PC0 | USART0_SCK | mikroBUS SCK | O | ++-------+----------------------+--------------------------------------------------------+-----------+ +| PC1 | GPIO | mikroBUS CS | I/O | ++-------+----------------------+--------------------------------------------------------+-----------+ +| PC2 | GPIO | mikroBUS AN | I | ++-------+----------------------+--------------------------------------------------------+-----------+ +| PC3 | GPIO | mikroBUS RST | O | ++-------+----------------------+--------------------------------------------------------+-----------+ +| PC4 | GPIO | mikroBUS PWM | O | ++-------+----------------------+--------------------------------------------------------+-----------+ +| PC5 | GPIO | mikroBUS INT / LED0 | I/O | ++-------+----------------------+--------------------------------------------------------+-----------+ +| PC6 | GPIO | Button 0 | I | ++-------+----------------------+--------------------------------------------------------+-----------+ +| PC7 | EUART0_TX | UART Console VCOM_TX | O | ++-------+----------------------+--------------------------------------------------------+-----------+ +| PD2 | USART0_RX / I2C0_SCL | mikroBUS MISO / mikroBUS RX / mikroBUS SCL / Qwiic SCL | I/O | ++-------+----------------------+--------------------------------------------------------+-----------+ +| PD3 | USART0_TX / I2C0_SDA | mikroBUS MOSI / mikroBUS TX / mikroBUS SDA / Qwiic SDA | I/O | ++-------+----------------------+--------------------------------------------------------+-----------+ + +.. note:: + MikroBUS INT and LED0 are multiplexed to the same I/O. Usage is determined by solder bridge SB4. Refer to + the `RM126x DVK user guide`_ and |Schematics Ref| for further details. + + The solder bridge defaults to the closed position to enable LED0 connectivity. + +.. note:: + MikroBUS MISO, RX and SCL are multiplexed to the same I/O. Usage is determined by solder bridges SB5, SB7 and SB8. + Refer to the `RM126x DVK user guide`_ and |Schematics Ref| for further details. + + The SB7 solder bridge defaults to closed to enable MISO connectivity. + +.. note:: + MikroBUS MOSI, TX and SDA are multiplexed to the same I/O. Usage is determined by solder bridges SB9, SB11 and SB12. + Refer to the `RM126x DVK user guide`_ and |Schematics Ref| for further details. + + The SB11 solder bridge defaults to closed to enable MOSI connectivity. + +.. note:: + Qwiic SCL is multipexed to the same I/O as MikroBUS MISO, RX and SCL. MikroBUS I2C based boards can be used + in conjunction with Qwiic based boards by closing solder bridges SB5 and SB6. + + Qwiic SDA is multipexed to the same I/O as MikroBUS MOSI, TX and SDA. MikroBUS I2C based boards can be used + in conjunction with Qwiic based boards by closing solder bridges SB9 and SB10. + + Refer to the `RM126x DVK user guide`_ and |Schematics Ref| for further details. + +EFR32BG22 To |SX126x variant| Radio Connections +=============================================== + +The following are internal to the |RM126x variant| module and describe connectivity between the +EFR32BG22 SoC and the |SX126x variant| LoRa radio. + +In the following table, the column **Name** contains Pin names. For example, PA2 +means Pin number 2 on PORTA, as used in the board's datasheets and manuals. + +The **Direction** column indicates the pin direction from the SoC perspective, with +I indicating Input and O Output. + ++-------+---------------------+------------------------------------------------+-----------+ +| Name | Function | Usage | Direction | ++=======+=====================+================================================+===========+ +| PA0 | USART1_SCK | |SX126x variant| SCK | O | ++-------+---------------------+------------------------------------------------+-----------+ +| PA4 | USART1_TX | |SX126x variant| MOSI | O | ++-------+---------------------+------------------------------------------------+-----------+ +| PA5 | GPIO | |SX126x variant| DIO1 | I | ++-------+---------------------+------------------------------------------------+-----------+ +| PA6 | GPIO | |SX126x variant| RESET | O | ++-------+---------------------+------------------------------------------------+-----------+ +| PA7 | GPIO | |SX126x variant| BUSY | I | ++-------+---------------------+------------------------------------------------+-----------+ +| PA8 | USART1_RX | |SX126x variant| MISO | I | ++-------+---------------------+------------------------------------------------+-----------+ +| PB0 | GPIO | |SX126x variant| CS | O | ++-------+---------------------+------------------------------------------------+-----------+ +| PB1 | GPIO | |SX126x variant| ANT SW | O | ++-------+---------------------+------------------------------------------------+-----------+ + +|SX126x variant| Radio Connections +================================== + +In the following table, the column **Name** contains Pin names as defined in the `SX126x datasheet`_. + +The **Direction** column indicates the pin direction from the radio perspective, with +O indicating Output. + ++-------+---------------------+------------------------------------------------+-----------+ +| Name | Function | Usage | Direction | ++=======+=====================+================================================+===========+ +| DIO2 | GPIO | RF Direction | O | ++-------+---------------------+------------------------------------------------+-----------+ +| DIO3 | GPIO | TCXO Enable | O | ++-------+---------------------+------------------------------------------------+-----------+ + +System Clock +============ + +The |RM126x variant| is configured to use the internal HFRCO oscillator as the System Clock at 38MHz. +It can operate at clock speeds of up to 80 MHz. + +Serial Port +=========== + +The |RM126x variant| has two USARTs and one EUART. + +* USART0 is mapped to the mikroBUS SPI port. +* USART1 is dedicated to the |SX126x variant| radio. +* EUART0 is connected to the board controller and is used for the console. + +Programming and Debugging +************************* + +Applications for the |Board Quoted| board can be built, flashed, and debugged in the usual way. +See :ref:`build_an_application` and :ref:`application_run` for more details on building and running. + +.. note:: + Before using the kit, you should update the J-Link firmware + in `Simplicity Studio`_. + +Testing the LED and button +========================== + +The :zephyr:code-sample:`blinky` sample can be used to test the DVK LED. + +The :zephyr:code-sample:`button` sample can be used to test the DVK button. + +Testing LoRa +============ + +The :zephyr:code-sample:`lorawan-class-a` sample can be programmed to an |RM126x variant| DVK to demonstrate +joining and uplinking to a LoRaWAN network server. + +This is built as follows. diff --git a/boards/ezurio/rm126x_dvk/doc/rm126x_dvk_common_2.rst.inc b/boards/ezurio/rm126x_dvk/doc/rm126x_dvk_common_2.rst.inc new file mode 100644 index 000000000000..950811ac2eec --- /dev/null +++ b/boards/ezurio/rm126x_dvk/doc/rm126x_dvk_common_2.rst.inc @@ -0,0 +1,33 @@ +.. SPDX-License-Identifier: Apache-2.0 +.. +.. Copyright (c) 2026 Ezurio LLC + +.. _RM126x product brief: + https://www.ezurio.com/documentation/product-brief-rm126x-series + +.. _RM126x website: + https://www.ezurio.com/wireless-modules/lorawan-modules-solutions/rm126x-ultra-low-power-lorawan-a-b-c-module + +.. _RM126x datasheet: + https://www.ezurio.com/documentation/datasheet-rm126x-lorawan-module + +.. _EFR32BG22 datasheet: + https://www.silabs.com/documents/public/data-sheets/efr32bg22-datasheet.pdf + +.. _EFR32BG22 reference manual: + https://www.silabs.com/documents/public/reference-manuals/efr32xg22-rm.pdf + +.. _SX126x datasheet: + https://semtech.my.salesforce.com/sfc/p/#E0000000JelG/a/RQ000008n3pp/qXjWn19TZmb.1MgqPZ8Vrc5V7U.M_lOAIoTZHcEAeTI + +.. _mikroBUS: + https://www.mikroe.com/mikrobus + +.. _Qwiic: + https://www.sparkfun.com/qwiic + +.. _RM126x DVK user guide: + https://www.ezurio.com/documentation/user-guide-rm126x-development-kit + +.. _Simplicity Studio: + https://www.silabs.com/software-and-tools/simplicity-studio diff --git a/boards/ezurio/rm126x_dvk/doc/rm126x_dvk_rm1261.rst b/boards/ezurio/rm126x_dvk/doc/rm126x_dvk_rm1261.rst new file mode 100644 index 000000000000..18ae90877e8c --- /dev/null +++ b/boards/ezurio/rm126x_dvk/doc/rm126x_dvk_rm1261.rst @@ -0,0 +1,19 @@ +.. zephyr:board:: rm126x_dvk_rm1261 + +.. |RM126x variant| replace:: RM1261 +.. |SX126x variant| replace:: SX1261 +.. |LoRa TX Power| replace:: 15dBm +.. |Board Quoted| replace:: ``rm126x_dvk_rm1261`` +.. |Schematics Ref| replace:: `RM1261 DVK schematics`_ + +.. include:: rm126x_dvk_common_1.rst.inc + +.. zephyr-app-commands:: + :zephyr-app: samples/subsys/lorawan/class_a + :board: rm126x_dvk_rm1261 + :goals: build + +.. include:: rm126x_dvk_common_2.rst.inc + +.. _RM1261 DVK schematics: + https://www.ezurio.com/documentation/schematic-pcb-assembly-dvk-rm1261-devboard diff --git a/boards/ezurio/rm126x_dvk/doc/rm126x_dvk_rm1262.rst b/boards/ezurio/rm126x_dvk/doc/rm126x_dvk_rm1262.rst new file mode 100644 index 000000000000..defa6b2cde95 --- /dev/null +++ b/boards/ezurio/rm126x_dvk/doc/rm126x_dvk_rm1262.rst @@ -0,0 +1,19 @@ +.. zephyr:board:: rm126x_dvk_rm1262 + +.. |RM126x variant| replace:: RM1262 +.. |SX126x variant| replace:: SX1262 +.. |LoRa TX Power| replace:: 22dBm +.. |Board Quoted| replace:: ``rm126x_dvk_rm1262`` +.. |Schematics Ref| replace:: `RM1262 DVK schematics`_ + +.. include:: rm126x_dvk_common_1.rst.inc + +.. zephyr-app-commands:: + :zephyr-app: samples/subsys/lorawan/class_a + :board: rm126x_dvk_rm1262 + :goals: build + +.. include:: rm126x_dvk_common_2.rst.inc + +.. _RM1262 DVK schematics: + https://www.ezurio.com/documentation/schematic-pcb-assembly-dvk-rm1262-devboard diff --git a/boards/ezurio/rm126x_dvk/pre_dt_board.cmake b/boards/ezurio/rm126x_dvk/pre_dt_board.cmake new file mode 100644 index 000000000000..e0a341833fe4 --- /dev/null +++ b/boards/ezurio/rm126x_dvk/pre_dt_board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2021 Linaro Limited +# Copyright (c) 2026 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +# SPI is implemented via usart so node name isn't spi@... +list(APPEND EXTRA_DTC_FLAGS "-Wno-spi_bus_bridge") diff --git a/boards/ezurio/rm126x_dvk/rm126x_dvk-pinctrl.dtsi b/boards/ezurio/rm126x_dvk/rm126x_dvk-pinctrl.dtsi new file mode 100644 index 000000000000..66a271b107b2 --- /dev/null +++ b/boards/ezurio/rm126x_dvk/rm126x_dvk-pinctrl.dtsi @@ -0,0 +1,82 @@ +/* + * Copyright The Zephyr Project Contributors + * Copyright (c) 2026 Ezurio LLC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + timer0_default: timer0_default { + group0 { + pins = ; + drive-push-pull; + output-high; + }; + }; + + usart0_default: usart0_default { + group0 { + pins = , ; + drive-push-pull; + output-high; + }; + + group1 { + pins = ; + input-enable; + silabs,input-filter; + }; + }; + + usart1_default: usart1_default { + group0 { + pins = , ; + drive-push-pull; + output-high; + }; + + group1 { + pins = ; + input-enable; + silabs,input-filter; + }; + }; + + iadc0_default: iadc0_default { + group0 { + silabs,analog-bus = ; + }; + }; + + i2c0_default: i2c0_default { + group0 { + pins = , ; + bias-pull-up; + drive-open-drain; + }; + }; + + euart0_default: euart0_default { + group0 { + pins = , ; + drive-push-pull; + output-high; + }; + + group1 { + pins = , ; + input-enable; + silabs,input-filter; + }; + }; + + itm_default: itm_default { + group0 { + pins = ; + drive-push-pull; + output-high; + }; + }; +}; diff --git a/boards/ezurio/rm126x_dvk/rm126x_dvk.dtsi b/boards/ezurio/rm126x_dvk/rm126x_dvk.dtsi new file mode 100644 index 000000000000..5606eeae0f63 --- /dev/null +++ b/boards/ezurio/rm126x_dvk/rm126x_dvk.dtsi @@ -0,0 +1,274 @@ +/* + * Copyright The Zephyr Project Contributors + * Copyright (c) 2026 Ezurio LLC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include "rm126x_dvk-pinctrl.dtsi" + +/ { + chosen { + zephyr,code-partition = &slot0_partition; + zephyr,console = &euart0; + zephyr,flash = &flash0; + zephyr,shell-uart = &euart0; + zephyr,sram = &sram0; + zephyr,uart-pipe = &euart0; + }; + + aliases { + led0 = &led0; + pwm-led0 = &pwm_led0; + sw0 = &button0; + watchdog0 = &wdog0; + lora0 = &lora0; + + /* If enabled, MCUboot uses this for recovery mode entrance */ + mcuboot-led0 = &led0; + mcuboot-button0 = &button0; + }; + + buttons { + compatible = "gpio-keys"; + + button0: button_0 { + gpios = <&gpioc 6 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + led0: led_0 { + gpios = <&gpioc 5 GPIO_ACTIVE_HIGH>; + }; + }; + + mikrobus_header: mikrobus-connector { + compatible = "mikro-bus"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0>; + gpio-map-pass-thru = <0 GPIO_DT_FLAGS_MASK>; + gpio-map = <0 0 &gpioc 2 0>, /* AN */ + <1 0 &gpioc 3 0>, /* RST */ + <2 0 &gpioc 1 0>, /* CS */ + <3 0 &gpioc 0 0>, /* SCK */ + <4 0 &gpiod 2 0>, /* MISO */ + <5 0 &gpiod 3 0>, /* MOSI */ + <6 0 &gpioc 4 0>, /* PWM */ + <7 0 &gpioc 5 0>, /* INT */ + <8 0 &gpiod 2 0>, /* RX */ + <9 0 &gpiod 3 0>, /* TX */ + <10 0 &gpiod 2 0>, /* SCL */ + <11 0 &gpiod 3 0>; /* SDA */ + }; + + pwmleds { + compatible = "pwm-leds"; + + pwm_led0: pwm_led_0 { + pwms = <&timer0_pwm 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + }; + }; + + qwiic_connector: stemma-qt-connector { + compatible = "stemma-qt-connector"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0>; + gpio-map-pass-thru = <0 GPIO_DT_FLAGS_MASK>; + gpio-map = <0 0 &gpiod 2 0>, /* SCL */ + <1 0 &gpiod 3 0>; /* SDA */ + }; + + mikrobus_adc: zephyr,user { + io-channels = <&adc0 0>; + }; +}; + +&em23grpaclk { + clocks = <&lfxo>; +}; + +&em4grpaclk { + clocks = <&lfxo>; +}; + +&prortcclk { + clocks = <&lfxo>; +}; + +&rtccclk { + clocks = <&lfxo>; +}; + +&wdog0clk { + clocks = <&lfxo>; +}; + +&cpu0 { + clock-frequency = <38000000>; +}; + +&hfrcodpll { + clock-frequency = ; +}; + +&lfxo { + status = "okay"; + ctune = <38>; + precision = <50>; +}; + +&gpio { + status = "okay"; +}; + +&gpioa { + status = "okay"; +}; + +&gpiob { + status = "okay"; +}; + +&gpioc { + status = "okay"; +}; + +&gpiod { + status = "okay"; +}; + +&timer0 { + status = "okay"; + + timer0_pwm: pwm { + pinctrl-0 = <&timer0_default>; + pinctrl-names = "default"; + status = "okay"; + }; +}; + +&usart0 { + compatible = "silabs,usart-spi"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&usart0_default>; + pinctrl-names = "default"; + cs-gpios = <&gpioc 1 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&usart1 { + compatible = "silabs,usart-spi"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&usart1_default>; + pinctrl-names = "default"; + cs-gpios = <&gpiob 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&dcdc { + regulator-boot-on; + regulator-initial-mode = ; + status = "okay"; +}; + +&rtcc0 { + status = "okay"; +}; + +&adc0 { + pinctrl-0 = <&iadc0_default>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + channel@0 { + reg = <0>; + zephyr,acquisition-time = ; + zephyr,gain = "ADC_GAIN_1"; + zephyr,input-positive = ; + zephyr,reference = "ADC_REF_VDD_1"; + zephyr,resolution = <12>; + zephyr,vref-mv = <3300>; + }; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + status = "disabled"; +}; + +&wdog0 { + status = "okay"; +}; + +&euart0 { + current-speed = <115200>; + pinctrl-0 = <&euart0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&trng { + status = "okay"; +}; + +&itm { + pinctrl-0 = <&itm_default>; + pinctrl-names = "default"; + swo-ref-frequency = ; +}; + +mikrobus_i2c: &i2c0 {}; + +mikrobus_spi: &usart0 {}; + +mikrobus_uart: &usart0 {}; + +zephyr_i2c: &i2c0 {}; + +zephyr_spi: &usart0 {}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 48 KiB for the bootloader */ + boot_partition: partition@0 { + reg = <0x00000000 DT_SIZE_K(48)>; + label = "mcuboot"; + read-only; + }; + + /* Reserve 224 KiB for the application in slot 0 */ + slot0_partition: partition@c000 { + reg = <0x0000c000 DT_SIZE_K(224)>; + label = "image-0"; + }; + + /* Reserve 224 KiB for the application in slot 1 */ + slot1_partition: partition@44000 { + reg = <0x00044000 DT_SIZE_K(224)>; + label = "image-1"; + }; + + /* Set 16 KiB of storage at the end of the 512 KiB of flash */ + storage_partition: partition@7c000 { + reg = <0x0007c000 DT_SIZE_K(16)>; + label = "storage"; + }; + }; +}; diff --git a/boards/ezurio/rm126x_dvk/rm126x_dvk_rm1261.dts b/boards/ezurio/rm126x_dvk/rm126x_dvk_rm1261.dts new file mode 100644 index 000000000000..95a4a50063ff --- /dev/null +++ b/boards/ezurio/rm126x_dvk/rm126x_dvk_rm1261.dts @@ -0,0 +1,31 @@ +/* + * Copyright The Zephyr Project Contributors + * Copyright (c) 2026 Ezurio LLC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "rm126x_dvk.dtsi" +#include + +/ { + model = "Ezurio RM1261 DVK"; + compatible = "ezurio,rm126x_dvk_rm1261", "silabs,efr32bg22"; +}; + +&usart1 { + lora0: lora@0 { + compatible = "semtech,sx1261"; + reg = <0>; + reset-gpios = <&gpioa 6 GPIO_ACTIVE_LOW>; + busy-gpios = <&gpioa 7 (GPIO_PULL_UP | GPIO_ACTIVE_HIGH)>; + antenna-enable-gpios = <&gpiob 1 GPIO_ACTIVE_LOW>; + dio1-gpios = <&gpioa 5 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; + dio2-tx-enable; + dio3-tcxo-voltage = ; + tcxo-power-startup-delay-ms = <5>; + spi-max-frequency = <1000000>; + }; +}; diff --git a/boards/ezurio/rm126x_dvk/rm126x_dvk_rm1261.yaml b/boards/ezurio/rm126x_dvk/rm126x_dvk_rm1261.yaml new file mode 100644 index 000000000000..133f11135b88 --- /dev/null +++ b/boards/ezurio/rm126x_dvk/rm126x_dvk_rm1261.yaml @@ -0,0 +1,27 @@ +identifier: rm126x_dvk_rm1261 +name: RM1261 DVK +type: mcu +arch: arm +ram: 32 +flash: 224 +toolchain: + - zephyr + - gnuarmemb +supported: + - adc + - clock_control + - comparator + - counter + - dma + - entropy + - gpio + - flash + - i2c + - led + - lora + - pinctrl + - pwm + - spi + - uart + - watchdog +vendor: ezurio diff --git a/boards/ezurio/rm126x_dvk/rm126x_dvk_rm1261_defconfig b/boards/ezurio/rm126x_dvk/rm126x_dvk_rm1261_defconfig new file mode 100644 index 000000000000..5ee421b84580 --- /dev/null +++ b/boards/ezurio/rm126x_dvk/rm126x_dvk_rm1261_defconfig @@ -0,0 +1,10 @@ +# Copyright The Zephyr Project Contributors +# Copyright (c) 2026 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/ezurio/rm126x_dvk/rm126x_dvk_rm1262.dts b/boards/ezurio/rm126x_dvk/rm126x_dvk_rm1262.dts new file mode 100644 index 000000000000..32d41444f1e6 --- /dev/null +++ b/boards/ezurio/rm126x_dvk/rm126x_dvk_rm1262.dts @@ -0,0 +1,32 @@ +/* + * Copyright The Zephyr Project Contributors + * Copyright (c) 2026 Ezurio LLC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "rm126x_dvk.dtsi" +#include + +/ { + model = "Ezurio RM1262 DVK"; + compatible = "ezurio,rm126x_dvk_rm1262", "silabs,efr32bg22"; +}; + +&usart1 { + lora0: lora@0 { + compatible = "semtech,sx1262"; + reg = <0>; + reset-gpios = <&gpioa 6 GPIO_ACTIVE_LOW>; + busy-gpios = <&gpioa 7 (GPIO_PULL_UP | GPIO_ACTIVE_HIGH)>; + antenna-enable-gpios = <&gpiob 1 GPIO_ACTIVE_LOW>; + dio1-gpios = <&gpioa 5 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; + dio2-tx-enable; + dio3-tcxo-voltage = ; + tcxo-power-startup-delay-ms = <5>; + regulator-ldo; + spi-max-frequency = <1000000>; + }; +}; diff --git a/boards/ezurio/rm126x_dvk/rm126x_dvk_rm1262.yaml b/boards/ezurio/rm126x_dvk/rm126x_dvk_rm1262.yaml new file mode 100644 index 000000000000..8a2d60aa8183 --- /dev/null +++ b/boards/ezurio/rm126x_dvk/rm126x_dvk_rm1262.yaml @@ -0,0 +1,27 @@ +identifier: rm126x_dvk_rm1262 +name: RM1262 DVK +type: mcu +arch: arm +ram: 32 +flash: 224 +toolchain: + - zephyr + - gnuarmemb +supported: + - adc + - clock_control + - comparator + - counter + - dma + - entropy + - gpio + - flash + - i2c + - led + - lora + - pinctrl + - pwm + - spi + - uart + - watchdog +vendor: ezurio diff --git a/boards/ezurio/rm126x_dvk/rm126x_dvk_rm1262_defconfig b/boards/ezurio/rm126x_dvk/rm126x_dvk_rm1262_defconfig new file mode 100644 index 000000000000..5ee421b84580 --- /dev/null +++ b/boards/ezurio/rm126x_dvk/rm126x_dvk_rm1262_defconfig @@ -0,0 +1,10 @@ +# Copyright The Zephyr Project Contributors +# Copyright (c) 2026 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/ezurio/rm1xx_dvk/rm1xx_dvk.dts b/boards/ezurio/rm1xx_dvk/rm1xx_dvk.dts index dddb743cf092..44a8066baa1c 100644 --- a/boards/ezurio/rm1xx_dvk/rm1xx_dvk.dts +++ b/boards/ezurio/rm1xx_dvk/rm1xx_dvk.dts @@ -124,13 +124,13 @@ /* 52K */ boot_partition: partition@0 { label = "mcuboot"; - reg = <0x00000000 0x0000C000>; + reg = <0x00000000 0x0000c000>; }; /* 188K */ slot0_partition: partition@c000 { label = "image-0"; - reg = <0x0000C000 0x00030000>; + reg = <0x0000c000 0x00030000>; }; /* @@ -139,7 +139,7 @@ */ storage_partition: partition@3c000 { label = "storage"; - reg = <0x0003C000 0x00004000>; + reg = <0x0003c000 0x00004000>; }; }; }; diff --git a/boards/fanke/fk750m1_vbt6/fk750m1_vbt6.dts b/boards/fanke/fk750m1_vbt6/fk750m1_vbt6.dts index 10e8798731b9..7792ea0dfdd6 100644 --- a/boards/fanke/fk750m1_vbt6/fk750m1_vbt6.dts +++ b/boards/fanke/fk750m1_vbt6/fk750m1_vbt6.dts @@ -62,10 +62,10 @@ porch-param = [0c 0c 00 33 33]; cmd2en-param = [5a 69 02 01]; pwctrl1-param = [a4 a1]; - pvgam-param = [D0 04 0D 11 13 2B 3F 54 4C 18 0D 0B 1F 23]; - nvgam-param = [D0 04 0C 11 13 2C 3F 44 51 2F 1F 1F 20 23]; - ram-param = [00 F0]; - rgb-param = [CD 08 14]; + pvgam-param = [d0 04 0d 11 13 2b 3f 54 4c 18 0d 0b 1f 23]; + nvgam-param = [d0 04 0c 11 13 2c 3f 44 51 2f 1f 1f 20 23]; + ram-param = [00 f0]; + rgb-param = [cd 08 14]; mipi-mode = "MIPI_DBI_MODE_SPI_4WIRE"; }; }; diff --git a/boards/fobe/quill_nrf52840_mesh/quill_nrf52840_mesh_common.dtsi b/boards/fobe/quill_nrf52840_mesh/quill_nrf52840_mesh_common.dtsi index aac440914bdf..b9470bd9f8c8 100644 --- a/boards/fobe/quill_nrf52840_mesh/quill_nrf52840_mesh_common.dtsi +++ b/boards/fobe/quill_nrf52840_mesh/quill_nrf52840_mesh_common.dtsi @@ -75,20 +75,20 @@ height = <240>; x-offset = <52>; y-offset = <40>; - vcom = <0x3F>; + vcom = <0x3f>; gctrl = <0x05>; - vrhs = <0x0F>; + vrhs = <0x0f>; vdvs = <0x20>; mdac = <0x00>; gamma = <0x01>; colmod = <0x05>; - lcm = <0x2C>; + lcm = <0x2c>; porch-param = [05 05 00 33 33]; - cmd2en-param = [5A 69 02 00]; - pwctrl1-param = [A4 A1]; - pvgam-param = [D0 05 09 09 08 14 28 33 3F 07 13 14 28 30]; - nvgam-param = [D0 05 09 09 08 03 24 32 32 3B 14 13 28 2F]; - ram-param = [00 F0]; + cmd2en-param = [5a 69 02 00]; + pwctrl1-param = [a4 a1]; + pvgam-param = [d0 05 09 09 08 14 28 33 3f 07 13 14 28 30]; + nvgam-param = [d0 05 09 09 08 03 24 32 32 3b 14 13 28 2f]; + ram-param = [00 f0]; rgb-param = [40 02 14]; mipi-mode = "MIPI_DBI_MODE_SPI_4WIRE"; }; diff --git a/boards/focaltech/ft9001_eval/Kconfig.ft9001_eval b/boards/focaltech/ft9001_eval/Kconfig.ft9001_eval new file mode 100644 index 000000000000..34da2097ad19 --- /dev/null +++ b/boards/focaltech/ft9001_eval/Kconfig.ft9001_eval @@ -0,0 +1,5 @@ +# Copyright (c) 2025, FocalTech Systems CO.,Ltd +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_FT9001_EVAL + select SOC_FT9001 diff --git a/boards/focaltech/ft9001_eval/board.cmake b/boards/focaltech/ft9001_eval/board.cmake new file mode 100644 index 000000000000..d882a5aff90a --- /dev/null +++ b/boards/focaltech/ft9001_eval/board.cmake @@ -0,0 +1,7 @@ +# Copyright (c) 2025, FocalTech Systems CO.,Ltd +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=FT9001" "--speed=4000") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/focaltech/ft9001_eval/board.yml b/boards/focaltech/ft9001_eval/board.yml new file mode 100644 index 000000000000..0c5e33a1c191 --- /dev/null +++ b/boards/focaltech/ft9001_eval/board.yml @@ -0,0 +1,6 @@ +board: + name: ft9001_eval + full_name: FocalTech FT9001 Evaluation Board + vendor: focaltech + socs: + - name: ft9001 diff --git a/boards/focaltech/ft9001_eval/doc/ft9001_eval.webp b/boards/focaltech/ft9001_eval/doc/ft9001_eval.webp new file mode 100644 index 000000000000..b7c6aaea7eb6 Binary files /dev/null and b/boards/focaltech/ft9001_eval/doc/ft9001_eval.webp differ diff --git a/boards/focaltech/ft9001_eval/doc/index.rst b/boards/focaltech/ft9001_eval/doc/index.rst new file mode 100644 index 000000000000..2cb3f1bcda27 --- /dev/null +++ b/boards/focaltech/ft9001_eval/doc/index.rst @@ -0,0 +1,45 @@ +:orphan: + +.. zephyr:board:: ft9001_eval + +Overview +******** + +The FT9001-EVAL board is an evaluation platform for the FocalTech FT9001 MCU +(Arm Cortex-M4F, up to 160 MHz). + +Hardware +******** + +- FocalTech FT9001 SoC (ARM Cortex-M4F compatible) +- 32 KB boot ROM +- 256 KB on-chip SRAM: + + - 224 KB standard SRAM + - 32 KB DBUS-connected SRAM + +- 2 MB external flash memory (SPI interface) +- 2x UART interfaces +- 2x SPI interfaces +- External GPIO pins with interrupt capability + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Flashing +======== + +Build and flash the :zephyr:code-sample:`hello_world` sample application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: ft9001_eval + :goals: build flash + :compact: diff --git a/boards/focaltech/ft9001_eval/ft9001_eval-pinctrl.dtsi b/boards/focaltech/ft9001_eval/ft9001_eval-pinctrl.dtsi new file mode 100644 index 000000000000..38d84c9c00ad --- /dev/null +++ b/boards/focaltech/ft9001_eval/ft9001_eval-pinctrl.dtsi @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2025, FocalTech Systems CO.,Ltd + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + usart3_default: usart3_default { + group1 { + pinmux = , + ; + }; + + group2 { + pinmux = , + ; + }; + + group3 { + pinmux = , + ; + }; + }; + + gint40_default: gint40_default { + group1 { + pinmux = ; + }; + + group2 { + pinmux = ; + }; + }; + + gint41_default: gint41_default { + group1 { + pinmux = ; + }; + + group2 { + pinmux = ; + }; + }; + + gint42_default: gint42_default { + group1 { + pinmux = ; + }; + + group2 { + pinmux = ; + }; + }; + + gint43_default: gint43_default { + group1 { + pinmux = ; + }; + + group2 { + pinmux = ; + }; + }; +}; diff --git a/boards/focaltech/ft9001_eval/ft9001_eval.dts b/boards/focaltech/ft9001_eval/ft9001_eval.dts new file mode 100644 index 000000000000..bd24ffb00ad7 --- /dev/null +++ b/boards/focaltech/ft9001_eval/ft9001_eval.dts @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2025, FocalTech Systems CO.,Ltd + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "ft9001_eval-pinctrl.dtsi" +#include + +/ { + model = "FocalTech FT9001 Evaluation Board"; + compatible = "focaltech,ft9001-eval", "focaltech,ft9001"; + + chosen { + zephyr,console = &usart2; + zephyr,shell-uart = &usart2; + zephyr,flash = &flash0; + zephyr,sram = &sram0; + zephyr,sram2 = &sramd0; + zephyr,flash-controller = &flash_ctrl; + zephyr,code-partition = &app_partition; + }; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + romcfg_partition: partition@0 { + label = "romcfg"; + reg = <0x00000000 0x00001000>; + read-only; + }; + + app_partition: partition@1000 { + label = "app"; + reg = <0x00001000 0x001ff000>; + }; + }; +}; + +&usart2 { + current-speed = <115200>; + parity = "none"; + stop-bits = "1"; + data-bits = <8>; + hw-flow-control; + status = "okay"; +}; diff --git a/boards/focaltech/ft9001_eval/ft9001_eval.yaml b/boards/focaltech/ft9001_eval/ft9001_eval.yaml new file mode 100644 index 000000000000..18b062d4c590 --- /dev/null +++ b/boards/focaltech/ft9001_eval/ft9001_eval.yaml @@ -0,0 +1,12 @@ +identifier: ft9001_eval +name: FocalTech FT9001 Evaluation Board +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +ram: 256 +flash: 2048 +supported: + - serial +vendor: focaltech diff --git a/boards/focaltech/ft9001_eval/ft9001_eval_defconfig b/boards/focaltech/ft9001_eval/ft9001_eval_defconfig new file mode 100644 index 000000000000..b45a1af7a7da --- /dev/null +++ b/boards/focaltech/ft9001_eval/ft9001_eval_defconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2025, FocalTech Systems CO.,Ltd +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/focaltech/ft9001_eval/support/openocd.cfg b/boards/focaltech/ft9001_eval/support/openocd.cfg new file mode 100644 index 000000000000..a4225eeabcd7 --- /dev/null +++ b/boards/focaltech/ft9001_eval/support/openocd.cfg @@ -0,0 +1,31 @@ +# Copyright (c) 2025, FocalTech Systems CO.,Ltd +# SPDX-License-Identifier: Apache-2.0 + +# FT9001 OpenOCD Configuration +# +# This configuration supports debugging the FT9001 evaluation board +# using CMSIS-DAP compatible debuggers (such as DAPLink, J-Link, etc.) +# +# Usage: openocd -f boards/arm/ft9001_eval/support/openocd.cfg + +source [find interface/cmsis-dap.cfg] +transport select swd + +set CHIPNAME ft9001 +set CPUTAPID 0x790007a3 + +source [find target/stm32f4x.cfg] + +reset_config trst_and_srst separate + +# Configure target events for better debugging experience +$_TARGETNAME configure -event gdb-attach { + echo "Debugger attaching: halting execution" + reset halt + gdb_breakpoint_override hard +} + +$_TARGETNAME configure -event gdb-detach { + echo "Debugger detaching: resuming execution" + resume +} diff --git a/boards/framework/framework_ledmatrix/Kconfig b/boards/framework/framework_ledmatrix/Kconfig new file mode 100644 index 000000000000..716eca330a52 --- /dev/null +++ b/boards/framework/framework_ledmatrix/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Framework Computer Inc +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_FRAMEWORK_LEDMATRIX + select RP2_FLASH_W25Q080 diff --git a/boards/framework/framework_ledmatrix/Kconfig.defconfig b/boards/framework/framework_ledmatrix/Kconfig.defconfig new file mode 100644 index 000000000000..1f6193a3b14b --- /dev/null +++ b/boards/framework/framework_ledmatrix/Kconfig.defconfig @@ -0,0 +1,19 @@ +# Copyright (c) 2025 Framework Computer Inc +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_FRAMEWORK_LEDMATRIX + +config RP2_FLASH_W25Q080 + default y + +if I2C_DW + +config I2C_DW_CLOCK_SPEED + default 125 + +endif # I2C_DW + +config USB_SELF_POWERED + default n + +endif # BOARD_FRAMEWORK_LEDMATRIX diff --git a/boards/framework/framework_ledmatrix/Kconfig.framework_ledmatrix b/boards/framework/framework_ledmatrix/Kconfig.framework_ledmatrix new file mode 100644 index 000000000000..4c3e54ff04ac --- /dev/null +++ b/boards/framework/framework_ledmatrix/Kconfig.framework_ledmatrix @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Framework Computer Inc +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_FRAMEWORK_LEDMATRIX + select SOC_RP2040 diff --git a/boards/framework/framework_ledmatrix/board.cmake b/boards/framework/framework_ledmatrix/board.cmake new file mode 100644 index 000000000000..affc290a869d --- /dev/null +++ b/boards/framework/framework_ledmatrix/board.cmake @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2023 TOKITA Hiroshi + +board_runner_args(uf2 "--board-id=RPI-RP2") + +include(${ZEPHYR_BASE}/boards/common/uf2.board.cmake) diff --git a/boards/framework/framework_ledmatrix/board.yml b/boards/framework/framework_ledmatrix/board.yml new file mode 100644 index 000000000000..8af63ebc061f --- /dev/null +++ b/boards/framework/framework_ledmatrix/board.yml @@ -0,0 +1,6 @@ +board: + name: framework_ledmatrix + full_name: Framework LED Matrix + vendor: framework + socs: + - name: rp2040 diff --git a/boards/framework/framework_ledmatrix/doc/img/framework_ledmatrix.webp b/boards/framework/framework_ledmatrix/doc/img/framework_ledmatrix.webp new file mode 100644 index 000000000000..dbea55283f8d Binary files /dev/null and b/boards/framework/framework_ledmatrix/doc/img/framework_ledmatrix.webp differ diff --git a/boards/framework/framework_ledmatrix/doc/index.rst b/boards/framework/framework_ledmatrix/doc/index.rst new file mode 100644 index 000000000000..7dbc9f539b1b --- /dev/null +++ b/boards/framework/framework_ledmatrix/doc/index.rst @@ -0,0 +1,65 @@ +.. zephyr:board:: framework_ledmatrix + +Overview +******** + +The Framework Laptop 16 compatible LED Matrix module is based on an RP2040 MCU and has an array of +9x36 white PWM LEDs controlled by a Lumissil IS31FL3741A. + +Hardware +******** + +* Dual core Arm Cortex-M0+ processor running up to 133MHz +* 264KB on-chip SRAM +* 1MB on-board QSPI flash with XIP capabilities +* Built-in 9x36 white LED matrix +* 2 way DIP Switch - one for user control, one to stay in bootloader +* USB 1.1 controller (host/device) +* 8 Programmable I/O (PIO) for custom peripherals +* 1 Watchdog timer peripheral + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Flashing +======== + +Using UF2 +--------- + +Here is an example of building the sample for enabling USB console. + +.. zephyr-app-commands:: + :zephyr-app: samples/subsys/usb/console + :board: framework_ledmatrix + :goals: build + :compact: + +You must flash the LED Matrix with an UF2 file. One option is to use West (Zephyr’s meta-tool). To +enter the UF2 flashing mode, remove the module flip the dip switch 2 and assemble it again. It will +appear on the host as a mass storage device. At this point you can flash the image file by running: + +.. code-block:: bash + + west flash + +After flashing, switch the DIP switch back again to run the firmware. + +Alternatively, you can locate the generated :file:`build/zephyr/zephyr.uf2` file and simply +drag-and-drop to the device after entering the UF2 flashing mode. + +References +********** + +* `Official Product Page`_ +* `Official Developer Documentation`_ + +.. _Official Product Page: https://frame.work/products/16-led-matrix +.. _Official Developer Documentation: https://github.com/FrameworkComputer/InputModules diff --git a/boards/framework/framework_ledmatrix/framework_ledmatrix-pinctrl.dtsi b/boards/framework/framework_ledmatrix/framework_ledmatrix-pinctrl.dtsi new file mode 100644 index 000000000000..f7cdac52e003 --- /dev/null +++ b/boards/framework/framework_ledmatrix/framework_ledmatrix-pinctrl.dtsi @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2025 Framework Computer Inc + * SPDX-License-Identifier: Apache-2.0 + */ +#include + +&pinctrl { + i2c1_default: i2c1_default { + group1 { + pinmux = , + ; + input-enable; + input-schmitt-enable; + }; + }; +}; diff --git a/boards/framework/framework_ledmatrix/framework_ledmatrix.dts b/boards/framework/framework_ledmatrix/framework_ledmatrix.dts new file mode 100644 index 000000000000..5e4f4e862a04 --- /dev/null +++ b/boards/framework/framework_ledmatrix/framework_ledmatrix.dts @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2025 Framework Computer Inc + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include "framework_ledmatrix-pinctrl.dtsi" + +/ { + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,flash-controller = &ssi; + zephyr,code-partition = &code_partition; + }; + + aliases { + /* Alias to easily get the device in C */ + led-blank-switch = &lid_closed; + rtc = &rtc; + watchdog0 = &wdt0; + }; + + gpio_keys { + compatible = "gpio-keys"; + + /* Dip switch on the back - not normally accessible during usage */ + dip1: dip1 { + gpios = <&gpio0 25 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + label = "DIP1"; + }; + + /* Pin from the EC on the mainboard - low indicating lid of the laptop is closed */ + lid_closed: lid-closed { + gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + label = "Lid closed"; + }; + }; +}; + +&flash0 { + reg = <0x10000000 DT_SIZE_M(1)>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserved memory for the second stage bootloader */ + second_stage_bootloader: partition@0 { + reg = <0x00000000 0x100>; + read-only; + }; + + /* + * Usable flash. Starts at 0x100, after the bootloader. The partition + * size is 1MB minus the 0x100 bytes taken by the bootloader. + */ + code_partition: partition@100 { + reg = <0x100 (DT_SIZE_M(1) - 0x100)>; + read-only; + }; + }; +}; + +&i2c1 { + status = "okay"; + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; + clock-frequency = ; + + is31fl3741@30 { + status = "okay"; + reg = <0x30>; + }; +}; + +&timer { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&rtc { + clocks = <&clocks RPI_PICO_CLKID_CLK_RTC>; + status = "okay"; +}; + +zephyr_udc0: &usbd { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&vreg { + regulator-always-on; + regulator-allowed-modes = ; +}; diff --git a/boards/framework/framework_ledmatrix/framework_ledmatrix.yaml b/boards/framework/framework_ledmatrix/framework_ledmatrix.yaml new file mode 100644 index 000000000000..ae933fa5deff --- /dev/null +++ b/boards/framework/framework_ledmatrix/framework_ledmatrix.yaml @@ -0,0 +1,18 @@ +identifier: framework_ledmatrix +name: Framework Laptop 16 LED Matrix +type: mcu +arch: arm +flash: 1024 +ram: 264 +toolchain: + - zephyr +supported: + - i2c + - gpio + - usb_device + - watchdog + - hwinfo + - dma + - counter + - clock +vendor: framework diff --git a/boards/framework/framework_ledmatrix/framework_ledmatrix_defconfig b/boards/framework/framework_ledmatrix/framework_ledmatrix_defconfig new file mode 100644 index 000000000000..1af1e54e1836 --- /dev/null +++ b/boards/framework/framework_ledmatrix/framework_ledmatrix_defconfig @@ -0,0 +1,16 @@ +# Copyright (c) 2025 Framework Computer Inc +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SERIAL=y +CONFIG_CONSOLE=y + +# Enable reset by default +CONFIG_RESET=y +CONFIG_CLOCK_CONTROL=y + +# Code partition needed to target the correct flash range +CONFIG_USE_DT_CODE_PARTITION=y + +# Output UF2 by default, maskrom bootloader supports it. +CONFIG_BUILD_OUTPUT_UF2=y +CONFIG_BUILD_OUTPUT_HEX=y diff --git a/boards/framework/index.rst b/boards/framework/index.rst new file mode 100644 index 000000000000..24ae8079c8dc --- /dev/null +++ b/boards/framework/index.rst @@ -0,0 +1,10 @@ +.. _boards-framework: + +Framework Computer Inc +###################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/framework/laptop16_keyboard/Kconfig.defconfig b/boards/framework/laptop16_keyboard/Kconfig.defconfig new file mode 100644 index 000000000000..08f7fe0e725d --- /dev/null +++ b/boards/framework/laptop16_keyboard/Kconfig.defconfig @@ -0,0 +1,19 @@ +# Copyright (c) 2025 The Framework Computer Inc +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_FRAMEWORK_LAPTOP16_KEYBOARD + +if I2C_DW + +config I2C_DW_CLOCK_SPEED + default 125 + +endif # I2C_DW + +config RP2_FLASH_W25Q080 + default y + +config USB_SELF_POWERED + default n + +endif # BOARD_FRAMEWORK_LAPTOP16_KEYBOARD diff --git a/boards/framework/laptop16_keyboard/Kconfig.framework_laptop16_keyboard b/boards/framework/laptop16_keyboard/Kconfig.framework_laptop16_keyboard new file mode 100644 index 000000000000..91a65d6932b2 --- /dev/null +++ b/boards/framework/laptop16_keyboard/Kconfig.framework_laptop16_keyboard @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Framework Computer Inc +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_FRAMEWORK_LAPTOP16_KEYBOARD + select SOC_RP2040 diff --git a/boards/framework/laptop16_keyboard/board.cmake b/boards/framework/laptop16_keyboard/board.cmake new file mode 100644 index 000000000000..affc290a869d --- /dev/null +++ b/boards/framework/laptop16_keyboard/board.cmake @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2023 TOKITA Hiroshi + +board_runner_args(uf2 "--board-id=RPI-RP2") + +include(${ZEPHYR_BASE}/boards/common/uf2.board.cmake) diff --git a/boards/framework/laptop16_keyboard/board.yml b/boards/framework/laptop16_keyboard/board.yml new file mode 100644 index 000000000000..95e4830c963e --- /dev/null +++ b/boards/framework/laptop16_keyboard/board.yml @@ -0,0 +1,6 @@ +boards: +- name: framework_laptop16_keyboard + full_name: Framework Laptop 16 Keyboard + vendor: framework + socs: + - name: rp2040 diff --git a/boards/framework/laptop16_keyboard/doc/img/framework_laptop16_keyboard.webp b/boards/framework/laptop16_keyboard/doc/img/framework_laptop16_keyboard.webp new file mode 100644 index 000000000000..fc0a6d9b4df8 Binary files /dev/null and b/boards/framework/laptop16_keyboard/doc/img/framework_laptop16_keyboard.webp differ diff --git a/boards/framework/laptop16_keyboard/doc/index.rst b/boards/framework/laptop16_keyboard/doc/index.rst new file mode 100644 index 000000000000..803755037623 --- /dev/null +++ b/boards/framework/laptop16_keyboard/doc/index.rst @@ -0,0 +1,88 @@ +.. zephyr:board:: framework_laptop16_keyboard + +Overview +******** + +The Framework Laptop 16 compatible Keyboard modules, based on RP2040 MCU, come in different sizes +and with per-key RGB or white backlight: + +* RGB backlight + + * ANSI Keyboard + * Macropad + +* White backlight + + * ANSI Keyboard + * ISO Keyboard + * Numpad + +Hardware +******** +* Dual core Arm Cortex-M0+ processor running up to 133MHz +* 264KB on-chip SRAM +* 1MB on-board QSPI flash with XIP capabilities +* Backlight + + * 1 PWM channel controlling the backlight + * Per-key RGB backlight + +* Numpad/Macropad: 8x4 keyboard matrix, with 21/24 keys +* Keyboard: 16x8 keyboard matrix +* 1 Analog input for key scanning +* 1 SGM48751 Mux for connecting any of the 8 KSI to the ADC input +* USB 1.1 controller (host/device) +* 8 Programmable I/O (PIO) for custom peripherals +* 1 Watchdog timer peripheral + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Flashing +======== + +Using UF2 +--------- + +Here is an example of building the sample for driving the built-in led. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky_pwm + :board: rp2040_plus + :goals: build + :compact: + +You must flash the keyboard with an UF2 file. One option is to use West (Zephyr’s meta-tool). To +enter the UF2 flashing mode, remove the module and hold down the both ALT keys (or ``1`` and ``6`` +on the numpad) while assembling (powering) it again. It will appear on the host as a mass storage +device. At this point you can flash the image file by running: + +.. code-block:: bash + + west flash + +Alternatively, you can locate the generated :file:`build/zephyr/zephyr.uf2` file and simply +drag-and-drop to the device after entering the UF2 flashing mode. + +References +********** + +* Official Product Pages + + * `Keyboard`_ + * `Numpad`_ + * `Macropad`_ + +* `Official Developer Documentation`_ + +.. _Keyboard: https://frame.work/products/keyboard-module +.. _Numpad: https://frame.work/products/16-numpad +.. _Macropad: https://frame.work/products/16-rgb-macropad +.. _Official Developer Documentation: https://github.com/FrameworkComputer/InputModules diff --git a/boards/framework/laptop16_keyboard/framework_laptop16_keyboard-pinctrl.dtsi b/boards/framework/laptop16_keyboard/framework_laptop16_keyboard-pinctrl.dtsi new file mode 100644 index 000000000000..6993c3e2c05e --- /dev/null +++ b/boards/framework/laptop16_keyboard/framework_laptop16_keyboard-pinctrl.dtsi @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2025 Framework Computer Inc + * SPDX-License-Identifier: Apache-2.0 + */ +#include + +&pinctrl { + i2c1_default: i2c1_default { + group1 { + pinmux = , + ; + input-enable; + input-schmitt-enable; + }; + }; + + pwm_ch4b_default: pwm_ch4b_default { + group1 { + pinmux = ; + }; + }; + + adc_default: adc_default { + group1 { + pinmux = ; + input-enable; + bias-pull-up; + }; + }; +}; diff --git a/boards/framework/laptop16_keyboard/framework_laptop16_keyboard.dts b/boards/framework/laptop16_keyboard/framework_laptop16_keyboard.dts new file mode 100644 index 000000000000..b3503724735f --- /dev/null +++ b/boards/framework/laptop16_keyboard/framework_laptop16_keyboard.dts @@ -0,0 +1,124 @@ +/* + * Copyright (c) 2025 Framework Computer Inc + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include "framework_laptop16_keyboard-pinctrl.dtsi" + +/ { + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,flash-controller = &ssi; + zephyr,code-partition = &code_partition; + }; + + aliases { + led0 = &caps_led; + pwm-led0 = &white_backlight_pwm; + rtc = &rtc; + watchdog0 = &wdt0; + }; + + zephyr,user { + io-channels = <&adc 2>; + }; + + leds { + compatible = "gpio-leds"; + + caps_led: led { + gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + status = "okay"; + + white_backlight_pwm: pwm { + pwms = <&pwm 9 PWM_NSEC(1000) PWM_POLARITY_NORMAL>; + label = "Backlight"; + }; + }; +}; + +&flash0 { + reg = <0x10000000 DT_SIZE_M(1)>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserved memory for the second stage bootloader */ + second_stage_bootloader: partition@0 { + reg = <0x00000000 0x100>; + read-only; + }; + + /* + * Usable flash. Starts at 0x100, after the bootloader. The partition + * size is 1MB minus the 0x100 bytes taken by the bootloader. + */ + code_partition: partition@100 { + reg = <0x100 (DT_SIZE_M(1) - 0x100)>; + read-only; + }; + }; +}; + +zephyr_udc0: &usbd { + status = "okay"; +}; + +&pwm { + status = "okay"; + /* GPIO25 is connected to channel 4B */ + pinctrl-0 = <&pwm_ch4b_default>; + pinctrl-names = "default"; + divider-int-0 = <255>; +}; + +&gpio0 { + status = "okay"; +}; + +&adc { + status = "okay"; + pinctrl-0 = <&adc_default>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + channel@2 { + reg = <2>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; +}; + +&timer { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&rtc { + clocks = <&clocks RPI_PICO_CLKID_CLK_RTC>; + status = "okay"; +}; + +&vreg { + regulator-always-on; + regulator-allowed-modes = ; +}; diff --git a/boards/framework/laptop16_keyboard/framework_laptop16_keyboard.yaml b/boards/framework/laptop16_keyboard/framework_laptop16_keyboard.yaml new file mode 100644 index 000000000000..674bf2b95405 --- /dev/null +++ b/boards/framework/laptop16_keyboard/framework_laptop16_keyboard.yaml @@ -0,0 +1,20 @@ +identifier: framework_laptop16_keyboard +name: Framework Laptop 16 Keyboard +type: mcu +arch: arm +flash: 1024 +ram: 264 +toolchain: + - zephyr +supported: + - clock + - counter + - flash + - gpio + - hwinfo + - i2c + - pwm + - usb_device + - usbd + - watchdog +vendor: framework diff --git a/boards/framework/laptop16_keyboard/framework_laptop16_keyboard_defconfig b/boards/framework/laptop16_keyboard/framework_laptop16_keyboard_defconfig new file mode 100644 index 000000000000..5ad737b66e8f --- /dev/null +++ b/boards/framework/laptop16_keyboard/framework_laptop16_keyboard_defconfig @@ -0,0 +1,19 @@ +# Copyright (c) 2025 The Framework Computer Inc +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SERIAL=y +CONFIG_CONSOLE=y + +# Enable reset by default +CONFIG_RESET=y +CONFIG_CLOCK_CONTROL=y + +# Code partition needed to target the correct flash range +CONFIG_USE_DT_CODE_PARTITION=y + +# Output UF2 by default, maskrom bootloader supports it. +CONFIG_BUILD_OUTPUT_UF2=y +CONFIG_BUILD_OUTPUT_HEX=y + +CONFIG_GPIO=y +CONFIG_PWM=y diff --git a/boards/franzininho/esp32s2_franzininho/support/openocd.cfg b/boards/franzininho/esp32s2_franzininho/support/openocd.cfg index f75d53b0b34c..6b71dc41b12f 100644 --- a/boards/franzininho/esp32s2_franzininho/support/openocd.cfg +++ b/boards/franzininho/esp32s2_franzininho/support/openocd.cfg @@ -1,4 +1,4 @@ -set ESP_RTOS none +set ESP_RTOS Zephyr source [find interface/ftdi/esp32s2_kaluga_v1.cfg] source [find target/esp32s2.cfg] diff --git a/boards/hardkernel/odroid_go/odroid_go_procpu.dts b/boards/hardkernel/odroid_go/odroid_go_procpu.dts index b51120268dd9..a02996771b46 100644 --- a/boards/hardkernel/odroid_go/odroid_go_procpu.dts +++ b/boards/hardkernel/odroid_go/odroid_go_procpu.dts @@ -155,6 +155,7 @@ disk-name = "SD"; status = "okay"; }; + spi-max-frequency = <20000000>; }; }; diff --git a/boards/heltec/heltec_wireless_stick_lite_v3/support/openocd.cfg b/boards/heltec/heltec_wireless_stick_lite_v3/support/openocd.cfg index 2f740b4a36ab..b45e13c53d01 100644 --- a/boards/heltec/heltec_wireless_stick_lite_v3/support/openocd.cfg +++ b/boards/heltec/heltec_wireless_stick_lite_v3/support/openocd.cfg @@ -1,5 +1,5 @@ -set ESP_RTOS none -set ESP32_ONLYCPU 1 +set ESP_RTOS Zephyr +set ESP_ONLYCPU 1 # Source the JTAG interface configuration file source [find interface/esp_usb_jtag.cfg] diff --git a/boards/heltec/heltec_wireless_tracker/heltec_wireless_tracker_procpu.dts b/boards/heltec/heltec_wireless_tracker/heltec_wireless_tracker_procpu.dts index 23c058bce044..b70fcb66b7fb 100644 --- a/boards/heltec/heltec_wireless_tracker/heltec_wireless_tracker_procpu.dts +++ b/boards/heltec/heltec_wireless_tracker/heltec_wireless_tracker_procpu.dts @@ -81,22 +81,22 @@ inversion-on; x-offset = <1>; y-offset = <26>; - madctl = <0xA8>; + madctl = <0xa8>; colmod = <0x05>; invctr = <7>; - vmctr1 = <0x0E>; - pwctr1 = [A2 02 84]; - pwctr2 = [C1]; - pwctr3 = [0A 00]; - pwctr4 = [8A 2A]; - pwctr5 = [8A EE]; - frmctr1 = [01 26 2E]; - frmctr2 = [01 26 2E]; - frmctr3 = [01 26 2E 01 26 2E]; - gamctrp1 = [0F 1A 0F 18 2F 28 20 22 1F 1B 23 37 00 07 02 10]; - gamctrn1 = [0F 1B 0F 17 33 2C 29 2E 30 2E 30 3B 00 07 03 10]; - caset = [00 01 00 A0]; - raset = [00 1A 00 69]; + vmctr1 = <0x0e>; + pwctr1 = [a2 02 84]; + pwctr2 = [c1]; + pwctr3 = [0a 00]; + pwctr4 = [8a 2a]; + pwctr5 = [8a ee]; + frmctr1 = [01 26 2e]; + frmctr2 = [01 26 2e]; + frmctr3 = [01 26 2e 01 26 2e]; + gamctrp1 = [0f 1a 0f 18 2f 28 20 22 1f 1b 23 37 00 07 02 10]; + gamctrn1 = [0f 1b 0f 17 33 2c 29 2e 30 2e 30 3b 00 07 03 10]; + caset = [00 01 00 a0]; + raset = [00 1a 00 69]; }; }; }; diff --git a/boards/heltec/heltec_wireless_tracker/support/openocd.cfg b/boards/heltec/heltec_wireless_tracker/support/openocd.cfg index 2f740b4a36ab..b45e13c53d01 100644 --- a/boards/heltec/heltec_wireless_tracker/support/openocd.cfg +++ b/boards/heltec/heltec_wireless_tracker/support/openocd.cfg @@ -1,5 +1,5 @@ -set ESP_RTOS none -set ESP32_ONLYCPU 1 +set ESP_RTOS Zephyr +set ESP_ONLYCPU 1 # Source the JTAG interface configuration file source [find interface/esp_usb_jtag.cfg] diff --git a/boards/holyiot/holyiot_21014/Kconfig.holyiot_21014 b/boards/holyiot/holyiot_21014/Kconfig.holyiot_21014 new file mode 100644 index 000000000000..b786816171b6 --- /dev/null +++ b/boards/holyiot/holyiot_21014/Kconfig.holyiot_21014 @@ -0,0 +1,7 @@ +# Holyiot 21014 board configuration + +# SPDX-FileCopyrightText: Copyright (c) 2025 Clunky Machines +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_HOLYIOT_21014 + select SOC_NRF52810_QFAA diff --git a/boards/holyiot/holyiot_21014/board.cmake b/boards/holyiot/holyiot_21014/board.cmake new file mode 100644 index 000000000000..ef7fbcbfe6e2 --- /dev/null +++ b/boards/holyiot/holyiot_21014/board.cmake @@ -0,0 +1,2 @@ +board_runner_args(jlink "--device=nRF52810_xxAA" "--speed=4000") +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/holyiot/holyiot_21014/board.yml b/boards/holyiot/holyiot_21014/board.yml new file mode 100644 index 000000000000..bac106d76683 --- /dev/null +++ b/boards/holyiot/holyiot_21014/board.yml @@ -0,0 +1,6 @@ +board: + name: holyiot_21014 + full_name: 21014 Module + vendor: holyiot + socs: + - name: nrf52810 diff --git a/boards/holyiot/holyiot_21014/doc/img/holyiot_21014.webp b/boards/holyiot/holyiot_21014/doc/img/holyiot_21014.webp new file mode 100644 index 000000000000..a985584a7eea Binary files /dev/null and b/boards/holyiot/holyiot_21014/doc/img/holyiot_21014.webp differ diff --git a/boards/holyiot/holyiot_21014/doc/index.rst b/boards/holyiot/holyiot_21014/doc/index.rst new file mode 100644 index 000000000000..5611ef5a54a5 --- /dev/null +++ b/boards/holyiot/holyiot_21014/doc/index.rst @@ -0,0 +1,66 @@ +.. zephyr:board:: holyiot_21014 + +Overview +******** + +The Holyiot_ 21014 module is built around the Nordic Semiconductor +`nRF52810`_ Arm Cortex-M4 SoC with 192 KiB of flash and 24 KiB of RAM. The +module have one user button and an RGB LED. + +.. figure:: img/holyiot_21014.webp + :align: center + :alt: Holyiot 21014 module + + Holyiot 21014 module + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Connections and IOs +=================== + +* Button: ``P0.31`` +* RGB LED: ``P0.29`` (red), ``P0.30`` (green), ``P0.28`` (blue) +* SPI0: ``P0.5`` (SCK), ``P0.2`` (MOSI), ``P0.3`` (MISO) + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +The board must be programmed using an external SWD probe (for example, a Segger +J-Link) connected to the SWDIO, SWCLK, VDD, and GND pads. + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install and +configure the required software. Then build and flash applications as usual +(see :ref:`build_an_application` and :ref:`application_run` for more details). + +Here is an example for the :zephyr:code-sample:`blinky` application: + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: holyiot_21014 + :goals: build flash + +Testing the LED and button +========================== + +You can test the board peripherals with the following samples: + +.. code-block:: console + + samples/basic/blinky + samples/basic/button + +References +********** + +.. target-notes:: + +.. _Holyiot: http://www.holyiot.com +.. _nRF52810: https://www.nordicsemi.com/Products/Low-power-short-range-wireless/nRF52810 diff --git a/boards/holyiot/holyiot_21014/holyiot_21014-pinctrl.dtsi b/boards/holyiot/holyiot_21014/holyiot_21014-pinctrl.dtsi new file mode 100644 index 000000000000..50f5c3762cf4 --- /dev/null +++ b/boards/holyiot/holyiot_21014/holyiot_21014-pinctrl.dtsi @@ -0,0 +1,23 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2025 Clunky Machines + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + spi0_default: spi0_default { + group1 { + psels = , + , + ; + }; + }; + + spi0_sleep: spi0_sleep { + group1 { + psels = , + , + ; + low-power-enable; + }; + }; +}; diff --git a/boards/holyiot/holyiot_21014/holyiot_21014.dts b/boards/holyiot/holyiot_21014/holyiot_21014.dts new file mode 100644 index 000000000000..8d423e6617a8 --- /dev/null +++ b/boards/holyiot/holyiot_21014/holyiot_21014.dts @@ -0,0 +1,117 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2025 Clunky Machines + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "holyiot_21014-pinctrl.dtsi" +#include + +/ { + model = "Holyiot 21014"; + compatible = "holyiot,21014"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; + + buttons { + compatible = "gpio-keys"; + + button0: button_0 { + gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; + label = "Push button switch 0"; + zephyr,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + led0_red: led_0 { + gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; + label = "Red LED 0"; + }; + + led0_green: led_1 { + gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; + label = "Green LED 0"; + }; + + led0_blue: led_2 { + gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; + label = "Blue LED 0"; + }; + }; + + aliases { + led0 = &led0_red; + led1 = &led0_green; + led2 = &led0_blue; + led0-red = &led0_red; + led0-green = &led0_green; + led0-blue = &led0_blue; + sw0 = &button0; + watchdog0 = &wdt0; + }; +}; + +® { + regulator-initial-mode = ; +}; + +&adc { + status = "okay"; +}; + +&gpiote { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&uicr { + gpio-as-nreset; +}; + +&spi0 { + compatible = "nordic,nrf-spi"; + status = "okay"; + pinctrl-0 = <&spi0_default>; + pinctrl-1 = <&spi0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x0000c000>; + }; + + slot0_partition: partition@c000 { + label = "image-0"; + reg = <0x0000c000 0x0000f000>; + }; + + slot1_partition: partition@1b000 { + label = "image-1"; + reg = <0x0001b000 0x0000f000>; + }; + + storage_partition: partition@2a000 { + label = "storage"; + reg = <0x0002a000 0x00006000>; + }; + }; +}; diff --git a/boards/holyiot/holyiot_21014/holyiot_21014.yaml b/boards/holyiot/holyiot_21014/holyiot_21014.yaml new file mode 100644 index 000000000000..dd72f8cbef28 --- /dev/null +++ b/boards/holyiot/holyiot_21014/holyiot_21014.yaml @@ -0,0 +1,13 @@ +identifier: holyiot_21014 +name: Holyiot 21014 +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +supported: + - counter + - gpio +ram: 24 +flash: 192 +vendor: holyiot diff --git a/boards/holyiot/holyiot_21014/holyiot_21014_defconfig b/boards/holyiot/holyiot_21014/holyiot_21014_defconfig new file mode 100644 index 000000000000..cee867613f06 --- /dev/null +++ b/boards/holyiot/holyiot_21014/holyiot_21014_defconfig @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 + +# 32kHz clock source +CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable RTT +CONFIG_USE_SEGGER_RTT=y + +# Enable GPIO +CONFIG_GPIO=y diff --git a/boards/holyiot/holyiot_21014/pre_dt_board.cmake b/boards/holyiot/holyiot_21014/pre_dt_board.cmake new file mode 100644 index 000000000000..3369c21d3af5 --- /dev/null +++ b/boards/holyiot/holyiot_21014/pre_dt_board.cmake @@ -0,0 +1,7 @@ +# Copyright (c) 2022 Nordic Semiconductor +# SPDX-License-Identifier: Apache-2.0 + +# Suppress "unique_unit_address_if_enabled" to handle the following overlaps: +# - power@40000000 & clock@40000000 & bprot@40000000 +# - acl@4001e000 & flash-controller@4001e000 +list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") diff --git a/boards/holyiot/holyiot_25008/Kconfig.defconfig b/boards/holyiot/holyiot_25008/Kconfig.defconfig new file mode 100644 index 000000000000..68e3d0a14deb --- /dev/null +++ b/boards/holyiot/holyiot_25008/Kconfig.defconfig @@ -0,0 +1,5 @@ +# SPDX-FileCopyrightText: Copyright (c) 2025 Clunky Machines +# SPDX-License-Identifier: Apache-2.0 + +config HW_STACK_PROTECTION + default ARCH_HAS_STACK_PROTECTION diff --git a/boards/holyiot/holyiot_25008/Kconfig.holyiot_25008 b/boards/holyiot/holyiot_25008/Kconfig.holyiot_25008 new file mode 100644 index 000000000000..ddedd60e0acd --- /dev/null +++ b/boards/holyiot/holyiot_25008/Kconfig.holyiot_25008 @@ -0,0 +1,7 @@ +# Holyiot 25008 board configuration + +# SPDX-FileCopyrightText: Copyright (c) 2025 Clunky Machines +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_HOLYIOT_25008 + select SOC_NRF54L15_CPUAPP if BOARD_HOLYIOT_25008_NRF54L15_CPUAPP diff --git a/boards/holyiot/holyiot_25008/board.cmake b/boards/holyiot/holyiot_25008/board.cmake new file mode 100644 index 000000000000..d04d9d178c48 --- /dev/null +++ b/boards/holyiot/holyiot_25008/board.cmake @@ -0,0 +1,16 @@ +# SPDX-FileCopyrightText: Copyright (c) 2025 Clunky Machines +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_SOC_NRF54L15_CPUAPP) + board_runner_args(jlink "--device=nRF54L15_M33" "--speed=4000") +endif() + +if(CONFIG_TFM_FLASH_MERGED_BINARY) + set_property(TARGET runners_yaml_props_target PROPERTY hex_file tfm_merged.hex) +endif() + +# Use system reset since the SWD header does not expose the reset pin. +board_runner_args(nrfutil "--softreset") + +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/holyiot/holyiot_25008/board.yml b/boards/holyiot/holyiot_25008/board.yml new file mode 100644 index 000000000000..56d6c0403e59 --- /dev/null +++ b/boards/holyiot/holyiot_25008/board.yml @@ -0,0 +1,6 @@ +board: + name: holyiot_25008 + full_name: HOLYIOT 25008 + vendor: holyiot + socs: + - name: nrf54l15 diff --git a/boards/holyiot/holyiot_25008/doc/img/holyiot_25008.webp b/boards/holyiot/holyiot_25008/doc/img/holyiot_25008.webp new file mode 100644 index 000000000000..6e099c5e04f5 Binary files /dev/null and b/boards/holyiot/holyiot_25008/doc/img/holyiot_25008.webp differ diff --git a/boards/holyiot/holyiot_25008/doc/index.rst b/boards/holyiot/holyiot_25008/doc/index.rst new file mode 100644 index 000000000000..57c01eb83ec3 --- /dev/null +++ b/boards/holyiot/holyiot_25008/doc/index.rst @@ -0,0 +1,54 @@ +.. zephyr:board:: holyiot_25008 + +Overview +******** + +The Holyiot 25008 module is based on the Nordic Semiconductor nRF54L15 SoC. +It includes a 32 MHz crystal (HFXO), a 32.768 kHz crystal (LFXO), one RGB LED, +one push button, and an LIS2DH12 accelerometer. + +.. figure:: img/holyiot_25008.webp + :align: center + :alt: Holyiot 25008 module + + Holyiot 25008 module + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Connections and IOs +=================== + +* UART: ``P1.04`` (TX), ``P1.05`` (RX) +* Button: ``P1.13`` +* RGB LED: ``P2.09`` (red), ``P1.10`` (green), ``P2.07`` (blue) +* LIS2DH12 (SPI): ``P2.01`` (SCK), ``P2.02`` (MOSI), ``P2.04`` (MISO), + ``P2.05`` (CS), ``P2.00`` (INT1), ``P2.03`` (INT2) + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +The board must be programmed using an external SWD probe connected to SWDIO, +SWCLK, VDD, and GND. + +Flashing +======== + +Here is an example for the :zephyr:code-sample:`blinky` application: + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: holyiot_25008/nrf54l15/cpuapp + :goals: build flash + +References +********** + +.. target-notes:: + +.. _Holyiot: http://www.holyiot.com +.. _nRF54L15: https://www.nordicsemi.com/Products/nRF54-series/nRF54L15 diff --git a/boards/holyiot/holyiot_25008/holyiot_25008_common.dtsi b/boards/holyiot/holyiot_25008/holyiot_25008_common.dtsi new file mode 100644 index 000000000000..e597ed0a497a --- /dev/null +++ b/boards/holyiot/holyiot_25008/holyiot_25008_common.dtsi @@ -0,0 +1,146 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2025 Clunky Machines + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "holyiot_25008_nrf54l15-pinctrl.dtsi" + +/ { + leds { + compatible = "gpio-leds"; + + led_red: led_r { + gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; + label = "LED R"; + }; + + led_green: led_g { + gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + label = "LED G"; + }; + + led_blue: led_b { + gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; + label = "LED B"; + }; + }; + + buttons { + compatible = "gpio-keys"; + + button0: button_0 { + gpios = <&gpio1 13 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "KEY"; + zephyr,code = ; + }; + }; + + aliases { + led0 = &led_red; + led1 = &led_green; + led2 = &led_blue; + led0-red = &led_red; + led0-green = &led_green; + led0-blue = &led_blue; + accel0 = &lis2dh; + sw0 = &button0; + watchdog0 = &wdt31; + }; +}; + +&uart20 { + current-speed = <115200>; + pinctrl-0 = <&uart20_default>; + pinctrl-1 = <&uart20_sleep>; + pinctrl-names = "default", "sleep"; + status = "okay"; +}; + +&cpuapp_sram { + status = "okay"; +}; + +&lfxo { + load-capacitors = "internal"; + load-capacitance-femtofarad = <16000>; + status = "okay"; +}; + +&hfxo { + load-capacitors = "internal"; + load-capacitance-femtofarad = <15000>; + status = "okay"; +}; + +®ulators { + status = "okay"; +}; + +&vregmain { + status = "okay"; + regulator-initial-mode = ; +}; + +&grtc { + owned-channels = <0 1 2 3 4 5 6 7 8 9 10 11>; + /* Channels 7-11 reserved for Zero Latency IRQs, 3-4 for FLPR */ + child-owned-channels = <3 4 7 8 9 10 11>; + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpiote20 { + status = "okay"; +}; + +&gpiote30 { + status = "okay"; +}; + +&wdt31 { + status = "okay"; +}; + +&radio { + status = "okay"; +}; + +&ieee802154 { + status = "okay"; +}; + +&temp { + status = "okay"; +}; + +&clock { + status = "okay"; +}; + +&spi00 { + status = "okay"; + cs-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&spi00_default>; + pinctrl-1 = <&spi00_sleep>; + pinctrl-names = "default", "sleep"; + + lis2dh: lis2dh@0 { + compatible = "st,lis2dh", "st,lis2dh12"; + reg = <0>; + spi-max-frequency = <8000000>; + irq-gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>, <&gpio2 3 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; diff --git a/boards/holyiot/holyiot_25008/holyiot_25008_nrf54l15-pinctrl.dtsi b/boards/holyiot/holyiot_25008/holyiot_25008_nrf54l15-pinctrl.dtsi new file mode 100644 index 000000000000..60e2376ffcef --- /dev/null +++ b/boards/holyiot/holyiot_25008/holyiot_25008_nrf54l15-pinctrl.dtsi @@ -0,0 +1,43 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2025 Clunky Machines + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + /omit-if-no-ref/ uart20_default: uart20_default { + group1 { + psels = ; + }; + + group2 { + psels = ; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ uart20_sleep: uart20_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; + + /omit-if-no-ref/ spi00_default: spi00_default { + group1 { + psels = , + , + ; + }; + }; + + /omit-if-no-ref/ spi00_sleep: spi00_sleep { + group1 { + psels = , + , + ; + low-power-enable; + }; + }; +}; diff --git a/boards/holyiot/holyiot_25008/holyiot_25008_nrf54l15_cpuapp.dts b/boards/holyiot/holyiot_25008/holyiot_25008_nrf54l15_cpuapp.dts new file mode 100644 index 000000000000..ad15b0c2fd38 --- /dev/null +++ b/boards/holyiot/holyiot_25008/holyiot_25008_nrf54l15_cpuapp.dts @@ -0,0 +1,30 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2025 Clunky Machines + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "holyiot_25008_common.dtsi" + +/ { + model = "HOLYIOT 25008"; + compatible = "holyiot,holyiot_25008-nrf54l15-cpuapp"; + + chosen { + zephyr,console = &uart20; + zephyr,shell-uart = &uart20; + zephyr,uart-mcumgr = &uart20; + zephyr,bt-mon-uart = &uart20; + zephyr,bt-c2h-uart = &uart20; + zephyr,flash-controller = &rram_controller; + zephyr,flash = &cpuapp_rram; + zephyr,code-partition = &slot0_partition; + zephyr,sram = &cpuapp_sram; + zephyr,ieee802154 = &ieee802154; + }; +}; + +/* Include default memory partition configuration file */ +#include diff --git a/boards/holyiot/holyiot_25008/holyiot_25008_nrf54l15_cpuapp.yaml b/boards/holyiot/holyiot_25008/holyiot_25008_nrf54l15_cpuapp.yaml new file mode 100644 index 000000000000..b99b3cd3760d --- /dev/null +++ b/boards/holyiot/holyiot_25008/holyiot_25008_nrf54l15_cpuapp.yaml @@ -0,0 +1,23 @@ +# SPDX-FileCopyrightText: Copyright (c) 2025 Clunky Machines +# SPDX-License-Identifier: Apache-2.0 + +identifier: holyiot_25008/nrf54l15/cpuapp +name: HOLYIOT-25008-nRF54L15-Application +type: mcu +arch: arm +toolchain: + - gnuarmemb + - zephyr +sysbuild: true +ram: 188 +flash: 1428 +supported: + - adc + - counter + - gpio + - pwm + - retained_mem + - sensor + - spi + - watchdog +vendor: holyiot diff --git a/boards/holyiot/holyiot_25008/holyiot_25008_nrf54l15_cpuapp_defconfig b/boards/holyiot/holyiot_25008/holyiot_25008_nrf54l15_cpuapp_defconfig new file mode 100644 index 000000000000..d84be6c682cc --- /dev/null +++ b/boards/holyiot/holyiot_25008/holyiot_25008_nrf54l15_cpuapp_defconfig @@ -0,0 +1,15 @@ +# SPDX-FileCopyrightText: Copyright (c) 2025 Clunky Machines +# SPDX-License-Identifier: Apache-2.0 + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable MPU +CONFIG_ARM_MPU=y diff --git a/boards/holyiot/yj17095/holyiot_yj17095.dts b/boards/holyiot/yj17095/holyiot_yj17095.dts index c6a396fdc989..3cb3083c6ac1 100644 --- a/boards/holyiot/yj17095/holyiot_yj17095.dts +++ b/boards/holyiot/yj17095/holyiot_yj17095.dts @@ -56,7 +56,7 @@ slot0_partition: partition@c000 { label = "image-0"; - reg = <0x0000C000 0x37000>; + reg = <0x0000c000 0x37000>; }; slot1_partition: partition@43000 { diff --git a/boards/iar/stm32f429ii_aca/doc/index.rst b/boards/iar/stm32f429ii_aca/doc/index.rst index c5b2bb56c485..403f0a7082a9 100644 --- a/boards/iar/stm32f429ii_aca/doc/index.rst +++ b/boards/iar/stm32f429ii_aca/doc/index.rst @@ -35,7 +35,7 @@ Hardware The STM32F429II-ACA evaluation board provides the following hardware components: - STM32F429II in LQFP176 package -- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU +- ARM® 32-bit Cortex®-M4 CPU with FPU - 180 MHz max CPU frequency - VDD from 1.8 V to 3.6 V - 2 MB Internal Flash diff --git a/boards/iar/stm32f429ii_aca/stm32f429ii_aca.dts b/boards/iar/stm32f429ii_aca/stm32f429ii_aca.dts index 2ef4de73bf06..4df791a7319e 100644 --- a/boards/iar/stm32f429ii_aca/stm32f429ii_aca.dts +++ b/boards/iar/stm32f429ii_aca/stm32f429ii_aca.dts @@ -18,7 +18,7 @@ chosen { zephyr,sram = &sram0; zephyr,flash = &flash0; - zephyr,ccm = &ccm0; + zephyr,dtcm = &ccm0; }; sdram2: sdram@d0000000 { diff --git a/boards/infineon/cy8ckit_041s_max/Kconfig.cy8ckit_041s_max b/boards/infineon/cy8ckit_041s_max/Kconfig.cy8ckit_041s_max new file mode 100644 index 000000000000..3051ffa83c44 --- /dev/null +++ b/boards/infineon/cy8ckit_041s_max/Kconfig.cy8ckit_041s_max @@ -0,0 +1,7 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_CY8CKIT_041S_MAX + select SOC_CY8C4149AZI_S598 diff --git a/boards/infineon/cy8ckit_041s_max/board.cmake b/boards/infineon/cy8ckit_041s_max/board.cmake new file mode 100644 index 000000000000..85b1fb6ebeae --- /dev/null +++ b/boards/infineon/cy8ckit_041s_max/board.cmake @@ -0,0 +1,7 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +# Include standard OpenOCD runner helpers +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/infineon/cy8ckit_041s_max/board.yml b/boards/infineon/cy8ckit_041s_max/board.yml new file mode 100644 index 000000000000..ac5f159fdeb4 --- /dev/null +++ b/boards/infineon/cy8ckit_041s_max/board.yml @@ -0,0 +1,11 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +board: + name: cy8ckit_041s_max + full_name: PSOC™ 4100S Max pioneer kit + vendor: infineon + socs: + - name: cy8c4149azi_s598 diff --git a/boards/infineon/cy8ckit_041s_max/cy8ckit_041s_max-pinctrl.dtsi b/boards/infineon/cy8ckit_041s_max/cy8ckit_041s_max-pinctrl.dtsi new file mode 100644 index 000000000000..f192b77eaad8 --- /dev/null +++ b/boards/infineon/cy8ckit_041s_max/cy8ckit_041s_max-pinctrl.dtsi @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Configure pin drive mode for uart pins */ +&p0_5_scb2_uart_tx { + drive-push-pull; +}; + +&p0_4_scb2_uart_rx { + input-enable; +}; diff --git a/boards/infineon/cy8ckit_041s_max/cy8ckit_041s_max.dts b/boards/infineon/cy8ckit_041s_max/cy8ckit_041s_max.dts new file mode 100644 index 000000000000..4e0256e44eaf --- /dev/null +++ b/boards/infineon/cy8ckit_041s_max/cy8ckit_041s_max.dts @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include + +#include "cy8ckit_041s_max_common.dtsi" + +/ { + model = "CY8CKIT-041S-MAX Development Board"; + compatible = "infineon,cy8ckit-041s-max", "infineon,psoc4100smax"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart2; + zephyr,shell-uart = &uart2; + }; + + aliases { + led0 = &user_led1; + }; + + leds { + compatible = "gpio-leds"; + status = "okay"; + + user_led1: led_1 { + label = "LED_1"; + gpios = <&gpio_prt7 3 GPIO_ACTIVE_LOW>; + }; + }; +}; diff --git a/boards/infineon/cy8ckit_041s_max/cy8ckit_041s_max.yaml b/boards/infineon/cy8ckit_041s_max/cy8ckit_041s_max.yaml new file mode 100644 index 000000000000..909010a1ddac --- /dev/null +++ b/boards/infineon/cy8ckit_041s_max/cy8ckit_041s_max.yaml @@ -0,0 +1,21 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +identifier: cy8ckit_041s_max +name: CY8CKIT-041S-MAX Development Board +type: mcu +arch: arm +ram: 32 +flash: 384 +toolchain: + - zephyr + - gnuarmemb +supported: + - uart + - gpio + - clock_control + - pinctrl + - i2c +vendor: infineon diff --git a/boards/infineon/cy8ckit_041s_max/cy8ckit_041s_max_common.dtsi b/boards/infineon/cy8ckit_041s_max/cy8ckit_041s_max_common.dtsi new file mode 100644 index 000000000000..89220cc928b7 --- /dev/null +++ b/boards/infineon/cy8ckit_041s_max/cy8ckit_041s_max_common.dtsi @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "cy8ckit_041s_max-pinctrl.dtsi" + +uart2: &scb2 { + compatible = "infineon,uart"; + status = "okay"; + current-speed = <115200>; + clocks = <&peri_clk_div1>; + pinctrl-0 = <&p0_5_scb2_uart_tx &p0_4_scb2_uart_rx>; + pinctrl-names = "default"; +}; + +&peri_clk_div0 { + status = "okay"; + resource-type = ; + resource-instance = <0>; +}; + +&peri_clk_div1 { + status = "okay"; + resource-type = ; + resource-instance = <2>; +}; + +&peri_clk_div2 { + status = "okay"; + resource-type = ; + resource-instance = <1>; +}; + +&peri_clk_div3 { + status = "okay"; + resource-type = ; + resource-instance = <0>; + clock-div = <11500>; +}; + +/* + * Note : use IFX_PATH_PSOC4_IMO for internal main oscillator as src + * use IFX_PATH_PSOC4_EXT for External clock as src + */ +&clk_hf { + status = "okay"; + source-path = ; +}; + +/* + * Note : use IFX_PATH_PSOC4_PUMP_GND for No clock, connect to gnd + * use IFX_PATH_PSOC4_PUMP_IMO for main IMO pump output + * use IFX_PATH_PSOC4_PUMP_HFCLK for clk_hf pump + * + * usage : The pump clock can be used for the analog pump + */ +&clk_pump { + status = "okay"; + source-path = ; +}; + +&gpio_prt7 { + status = "okay"; +}; diff --git a/boards/infineon/cy8ckit_041s_max/cy8ckit_041s_max_defconfig b/boards/infineon/cy8ckit_041s_max/cy8ckit_041s_max_defconfig new file mode 100644 index 000000000000..ab312bcd2d16 --- /dev/null +++ b/boards/infineon/cy8ckit_041s_max/cy8ckit_041s_max_defconfig @@ -0,0 +1,14 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# UART driver +CONFIG_SERIAL=y + +# Clock controller +CONFIG_CLOCK_CONTROL=y diff --git a/boards/infineon/cy8ckit_041s_max/docs/index.rst b/boards/infineon/cy8ckit_041s_max/docs/index.rst new file mode 100644 index 000000000000..2a8540f78547 --- /dev/null +++ b/boards/infineon/cy8ckit_041s_max/docs/index.rst @@ -0,0 +1,97 @@ +.. zephyr:board:: cy8ckit_041s_max + +Overview +******** + +The PSOC™ 4100S Max Pioneer Kit (CY8CKIT-041S-MAX) enables you to evaluate and develop applications using the PSOC™ 4100S Max microcontroller, part of Infineon's PSOC™ 4 family. +The device integrates an Arm Cortex-M0+ CPU running up to 48 MHz, combining programmable analog and digital subsystems to support flexible mixed-signal designs. It features up to 384 KB Flash and up to 32 KB SRAM, and includes a wide range of configurable peripherals such as SAR ADC, comparators, opamps (CTBm), CapSense™ capacitive touch sensing, and TCPWM for timer/counter/PWM functionality. + +32-bit MCU subsystem +- 48-MHz Arm® Cortex®-M0+ CPU with single-cycle multiply +- Up to 384 KB of flash with read accelerator +- Up to 32 KB of SRAM +- Direct memory access (DMA) +- Low-power 1.71 V to 5.5 V operation +- Deep sleep mode with low-power touch sensing +- Active touch detection and tracking with low power consumption +- Real Time clock support +- Power supply: 3.3 V or 5 V operation + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Building +======== + +Here is an example for building the :zephyr:code-sample:`hello_world` sample application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: cy8ckit_041s_max + :goals: build + +Flashing +======== + +The CY8CKIT-041S-MAX includes an onboard programmer/debugger (`KitProg3`_) to provide debugging, flash programming, and serial communication over USB. Flash and debug commands use OpenOCD and require a custom Infineon OpenOCD version, that supports KitProg3, to be installed. + +Infineon OpenOCD Installation +============================= + +Both the full `ModusToolbox`_ and the `ModusToolbox Programming Tools`_ packages include Infineon OpenOCD. +Installing either of these packages will also install Infineon OpenOCD. + +If neither package is installed, a minimal installation can be done by downloading the `Infineon OpenOCD`_ release for your system and manually extract the files to a location of your choice. + +.. note:: Linux requires device access rights to be set up for KitProg3. This is handled automatically by the ModusToolbox and ModusToolbox Programming Tools installations. When doing a minimal installation, this can be done manually by executing the script ``openocd/udev_rules/install_rules.sh``. + +West Commands +============= + +The path to the installed Infineon OpenOCD executable must be available to the ``west`` tool commands. There are multiple ways of doing this. The example below uses a permanent CMake argument to set the CMake variable ``OPENOCD``. + +Run ``west config`` once to set permanent CMake argument: + + .. tabs:: + .. group-tab:: Windows + + .. code-block:: shell + + west config build.cmake-args -- -DOPENOCD=path/to/infineon/openocd/bin/openocd.exe + + .. group-tab:: Linux + + .. code-block:: shell + + west config build.cmake-args -- -DOPENOCD=path/to/infineon/openocd/bin/openocd + +Once configured, you can build and flash applications: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: cy8ckit_041s_max + :goals: build flash debug + +Once the gdb console starts after executing the west debug command, you may now set breakpoints and perform other standard GDB debugging. + +References +********** + +.. target-notes:: + +.. _cy8ckit_041s_max Board Website: + https://www.infineon.com/evaluation-board/CY8CKIT-041S-MAX + +.. _ModusToolbox: + https://www.infineon.com/design-resources/development-tools/sdk/modustoolbox-software + +.. _ModusToolbox Programming Tools: + https://www.infineon.com/design-resources/development-tools/sdk/modustoolbox-software/modustoolbox-programming-tools + +.. _Infineon OpenOCD: + https://github.com/Infineon/openocd/releases/latest + +.. _KitProg3: + https://github.com/Infineon/KitProg3 diff --git a/boards/infineon/cy8ckit_041s_max/support/openocd.cfg b/boards/infineon/cy8ckit_041s_max/support/openocd.cfg new file mode 100644 index 000000000000..f7f165c28c07 --- /dev/null +++ b/boards/infineon/cy8ckit_041s_max/support/openocd.cfg @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# OpenOCD configuration for CY8CKIT-041S-MAX +# PSoC 4100S Max with KitProg3 programmer + +source [find interface/kitprog3.cfg] + +# Set transport to SWD +transport select swd + +# Set adapter speed (KitProg3 supports up to 1000 kHz for PSoC 4) +adapter speed 1000 + +# PSoC 4 family configuration +source [find target/psoc4.cfg] + +# Reset configuration +reset_config srst_only diff --git a/boards/infineon/cy8ckit_062s2_ai/cy8ckit_062s2_ai.dts b/boards/infineon/cy8ckit_062s2_ai/cy8ckit_062s2_ai.dts index 4e7b1c12d18f..ffdb91fff119 100644 --- a/boards/infineon/cy8ckit_062s2_ai/cy8ckit_062s2_ai.dts +++ b/boards/infineon/cy8ckit_062s2_ai/cy8ckit_062s2_ai.dts @@ -93,7 +93,7 @@ /* UART connected to KitProg3 */ uart5: &scb5 { - compatible = "infineon,cat1-uart"; + compatible = "infineon,uart"; status = "okay"; current-speed = <115200>; pinctrl-0 = <&p5_1_scb5_uart_tx &p5_0_scb5_uart_rx>; @@ -101,7 +101,7 @@ uart5: &scb5 { }; uart1: &scb1 { - compatible = "infineon,cat1-uart"; + compatible = "infineon,uart"; status = "okay"; current-speed = <115200>; pinctrl-0 = <&p10_0_scb1_uart_rx &p10_1_scb1_uart_tx>; @@ -109,7 +109,7 @@ uart1: &scb1 { }; i2c0: &scb0 { - compatible = "infineon,cat1-i2c"; + compatible = "infineon,i2c"; status = "okay"; #address-cells = <1>; diff --git a/boards/infineon/cy8ckit_062s2_ai/doc/index.rst b/boards/infineon/cy8ckit_062s2_ai/doc/index.rst index a7c2ad2f4f62..26903492385d 100644 --- a/boards/infineon/cy8ckit_062s2_ai/doc/index.rst +++ b/boards/infineon/cy8ckit_062s2_ai/doc/index.rst @@ -5,12 +5,12 @@ Overview The PSOC 6 AI Evaluation Kit (CY8CKIT-062S2-AI) is a cost effective and small development kit that enables design and debug of PSOC 6 MCUs. -It includes a CY8C624ABZI-S2D44 MCU which is based on a 150-MHz Arm |reg| Cortex |reg|-M4 and -a 100-MHz Arm |reg| Cortex |reg|-M0+, with 2048 KB of on-chip Flash, 1024 KB of SRAM, +It includes a CY8C624ABZI-S2D44 MCU which is based on a 150-MHz Arm® Cortex®-M4 and +a 100-MHz Arm® Cortex®-M0+, with 2048 KB of on-chip Flash, 1024 KB of SRAM, a Quad-SPI external memory interface, built-in hardware and software security features, rich analog, digital, and communication peripherals. -The board features an AIROC |reg| CYW43439 Wi-Fi & Bluetooth |reg| combo device, +The board features an AIROC® CYW43439 Wi-Fi & Bluetooth® combo device, a 512 MB NOR flash, an onboard programmer/debugger (KitProg3), USB host and device features, two user LEDs, and one push button. diff --git a/boards/infineon/cy8ckit_062s4/cy8ckit_062s4.dts b/boards/infineon/cy8ckit_062s4/cy8ckit_062s4.dts index 6992a1378dbc..41ed4640f9e3 100644 --- a/boards/infineon/cy8ckit_062s4/cy8ckit_062s4.dts +++ b/boards/infineon/cy8ckit_062s4/cy8ckit_062s4.dts @@ -68,7 +68,7 @@ }; uart2: &scb2 { - compatible = "infineon,cat1-uart"; + compatible = "infineon,uart"; status = "okay"; current-speed = <115200>; pinctrl-0 = <&p3_0_scb2_uart_rx &p3_1_scb2_uart_tx>; @@ -84,7 +84,7 @@ uart2: &scb2 { }; uart0: &scb0 { - compatible = "infineon,cat1-uart"; + compatible = "infineon,uart"; }; arduino_serial: &uart0 {}; diff --git a/boards/infineon/cy8cproto_041tp/Kconfig.cy8cproto_041tp b/boards/infineon/cy8cproto_041tp/Kconfig.cy8cproto_041tp new file mode 100644 index 000000000000..6a67a704be75 --- /dev/null +++ b/boards/infineon/cy8cproto_041tp/Kconfig.cy8cproto_041tp @@ -0,0 +1,7 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_CY8CPROTO_041TP + select SOC_CY8C4147AZQ_T495 diff --git a/boards/infineon/cy8cproto_041tp/board.cmake b/boards/infineon/cy8cproto_041tp/board.cmake new file mode 100644 index 000000000000..85b1fb6ebeae --- /dev/null +++ b/boards/infineon/cy8cproto_041tp/board.cmake @@ -0,0 +1,7 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +# Include standard OpenOCD runner helpers +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/infineon/cy8cproto_041tp/board.yml b/boards/infineon/cy8cproto_041tp/board.yml new file mode 100644 index 000000000000..04c79ee47168 --- /dev/null +++ b/boards/infineon/cy8cproto_041tp/board.yml @@ -0,0 +1,11 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +board: + name: cy8cproto_041tp + full_name: CY8CPROTO-041TP + vendor: infineon + socs: + - name: cy8c4147azq_t495 diff --git a/boards/infineon/cy8cproto_041tp/cy8cproto_041tp-pinctrl.dtsi b/boards/infineon/cy8cproto_041tp/cy8cproto_041tp-pinctrl.dtsi new file mode 100644 index 000000000000..3a3fdd13c7be --- /dev/null +++ b/boards/infineon/cy8cproto_041tp/cy8cproto_041tp-pinctrl.dtsi @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Configure pin drive mode for uart pins */ +&p5_2_scb0_uart_tx { + drive-push-pull; +}; + +&p5_1_scb0_uart_rx { + input-enable; +}; + +&p6_3_scb1_i2c_scl { + drive-open-drain; + input-enable; +}; + +&p6_4_scb1_i2c_sda { + drive-open-drain; + input-enable; +}; diff --git a/boards/infineon/cy8cproto_041tp/cy8cproto_041tp.dts b/boards/infineon/cy8cproto_041tp/cy8cproto_041tp.dts new file mode 100644 index 000000000000..e2999d9fdbd8 --- /dev/null +++ b/boards/infineon/cy8cproto_041tp/cy8cproto_041tp.dts @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include + +#include "cy8cproto_041tp_common.dtsi" + +/ { + model = "CY8CPROTO-041TP Development Board"; + compatible = "infineon,cy8cproto-041tp", "infineon,psoc4100tp"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; + + aliases { + led0 = &led; + sw0 = &user_btn; + }; + + leds { + compatible = "gpio-leds"; + status = "okay"; + + led: led { + label = "LED_0"; + gpios = <&gpio_prt5 5 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + user_btn: button { + label = "SW_0"; + gpios = <&gpio_prt5 6 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + }; + }; +}; + +&clk_wco { + status = "okay"; + clock-frequency = <32000>; /* 32 kHz */ +}; diff --git a/boards/infineon/cy8cproto_041tp/cy8cproto_041tp.yaml b/boards/infineon/cy8cproto_041tp/cy8cproto_041tp.yaml new file mode 100644 index 000000000000..780adc3f3b34 --- /dev/null +++ b/boards/infineon/cy8cproto_041tp/cy8cproto_041tp.yaml @@ -0,0 +1,19 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +identifier: cy8cproto_041tp +name: CY8CPROTO-041TP Development Board +type: mcu +arch: arm +ram: 32 +flash: 128 +toolchain: + - zephyr + - gnuarmemb +supported: + - uart + - clock_control + - pinctrl +vendor: infineon diff --git a/boards/infineon/cy8cproto_041tp/cy8cproto_041tp_common.dtsi b/boards/infineon/cy8cproto_041tp/cy8cproto_041tp_common.dtsi new file mode 100644 index 000000000000..e04a69d11ef2 --- /dev/null +++ b/boards/infineon/cy8cproto_041tp/cy8cproto_041tp_common.dtsi @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "cy8cproto_041tp-pinctrl.dtsi" + +/ { + aliases { + watchdog0 = &watchdog0; + }; +}; + +uart0: &scb0 { + compatible = "infineon,uart"; + status = "okay"; + current-speed = <115200>; + clocks = <&peri_clk_div0>; + pinctrl-0 = <&p5_2_scb0_uart_tx &p5_1_scb0_uart_rx>; + pinctrl-names = "default"; +}; + +&peri_clk_div0 { + status = "okay"; + resource-type = ; + resource-instance = <0>; +}; + +&peri_clk_div1 { + status = "okay"; + resource-type = ; + resource-instance = <1>; +}; + +&peri_clk_div2 { + status = "okay"; + resource-type = ; + resource-instance = <1>; +}; + +&peri_clk_div3 { + status = "okay"; + resource-type = ; + resource-instance = <0>; + clock-div = <11500>; +}; + +/* + * Note : use IFX_PATH_PSOC4_IMO for internal main oscillator as src + * use IFX_PATH_PSOC4_EXT for External clock as src + */ +&clk_hf { + status = "okay"; + source-path = ; +}; + +/* + * Note : use IFX_PATH_PSOC4_PUMP_GND for No clock, connect to gnd + * use IFX_PATH_PSOC4_PUMP_IMO for main IMO pump output + * use IFX_PATH_PSOC4_PUMP_HFCLK for clk_hf pump + * + * usage : The pump clock can be used for the analog pump + */ +&clk_pump { + status = "okay"; + source-path = ; +}; + +&gpio_prt4 { + status = "okay"; +}; + +&gpio_prt5 { + status = "okay"; + interrupts = <4 4>; +}; + +&watchdog0 { + status = "okay"; +}; diff --git a/boards/infineon/cy8cproto_041tp/cy8cproto_041tp_defconfig b/boards/infineon/cy8cproto_041tp/cy8cproto_041tp_defconfig new file mode 100644 index 000000000000..ab312bcd2d16 --- /dev/null +++ b/boards/infineon/cy8cproto_041tp/cy8cproto_041tp_defconfig @@ -0,0 +1,14 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# UART driver +CONFIG_SERIAL=y + +# Clock controller +CONFIG_CLOCK_CONTROL=y diff --git a/boards/infineon/cy8cproto_041tp/docs/index.rst b/boards/infineon/cy8cproto_041tp/docs/index.rst new file mode 100644 index 000000000000..9a4029ebe74c --- /dev/null +++ b/boards/infineon/cy8cproto_041tp/docs/index.rst @@ -0,0 +1,102 @@ +.. zephyr:board:: cy8cproto_041tp + +Overview +******** + +The PSOC™ 4100T Plus evaluation kit enables you to evaluate and develop applications using the PSOC™ 4100T Plus microcontroller, part of Infineon’s PSOC™ 4 family. +The device integrates an Arm Cortex-M0 CPU running up to 48 MHz, combining programmable analog and digital subsystems to support flexible mixed-signal designs. It features up to 128 KB Flash and 16 KB SRAM, and includes a wide range of configurable peripherals such as SAR ADC, comparators, opamps (CTBm), CapSense™ capacitive touch sensing, and TCPWM for timer/counter/PWM functionality. + +32-bit MCU subsystem +- 48-MHz Arm® Cortex®-M0+ CPU with single-cycle multiply +- Up to 128 KB of flash with read accelerator +- Up to 32 KB of SRAM +- Direct memory access (DMA) +- Low-power 1.71 V to 5.5 V operation +- Deep sleep mode with 6 μA always-on touch sensing +- Active touch detection and tracking with 200 μA (average) +- Real Time clock-SW is available +- Power supply: 3.3 V or 5 V operation + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Building +======== + +Here is an example for building the :zephyr:code-sample:`hello_world` sample application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: cy8cproto_041tp + :goals: build + +Flashing +======== + +The CY8CPROTO-041TP includes an onboard programmer/debugger (`KitProg3`_) to provide debugging, flash programming, and serial communication over USB. Flash and debug commands use OpenOCD and require a custom Infineon OpenOCD version, that supports KitProg3, to be installed. + +Infineon OpenOCD Installation +============================= + +Both the full `ModusToolbox`_ and the `ModusToolbox Programming Tools`_ packages include Infineon OpenOCD. +Installing either of these packages will also install Infineon OpenOCD. + +If neither package is installed, a minimal installation can be done by downloading the `Infineon OpenOCD`_ release for your system and manually extract the files to a location of your choice. + +.. note:: Linux requires device access rights to be set up for KitProg3. This is handled automatically by the ModusToolbox and ModusToolbox Programming Tools installations. When doing a minimal installation, this can be done manually by executing the script ``openocd/udev_rules/install_rules.sh``. + +West Commands +============= + +The path to the installed Infineon OpenOCD executable must be available to the ``west`` tool commands. There are multiple ways of doing this. The example below uses a permanent CMake argument to set the CMake variable ``OPENOCD``. + + .. tabs:: + .. group-tab:: Windows + + .. code-block:: shell + + # Run west config once to set permanent CMake argument + west config build.cmake-args -- -DOPENOCD=path/to/infineon/openocd/bin/openocd.exe + + # Do a pristine build once after setting CMake argument + west build -b cy8cproto_041tp -p always samples/hello_world + + west flash + west debug + + .. group-tab:: Linux + + .. code-block:: shell + + # Run west config once to set permanent CMake argument + west config build.cmake-args -- -DOPENOCD=path/to/infineon/openocd/bin/openocd + + # Do a pristine build once after setting CMake argument + west build -b cy8cproto_041tp -p always samples/hello_world + + west flash + west debug + +Once the gdb console starts after executing the west debug command, you may now set breakpoints and perform other standard GDB debugging. + +References +********** + +.. target-notes:: + +.. _cy8cproto_041tp Board Website: + https://www.infineon.com/evaluation-board/CY8CPROTO-041TP + +.. _ModusToolbox: + https://www.infineon.com/design-resources/development-tools/sdk/modustoolbox-software + +.. _ModusToolbox Programming Tools: + https://www.infineon.com/design-resources/development-tools/sdk/modustoolbox-software/modustoolbox-programming-tools + +.. _Infineon OpenOCD: + https://github.com/Infineon/openocd/releases/latest + +.. _KitProg3: + https://github.com/Infineon/KitProg3 diff --git a/boards/infineon/cy8cproto_041tp/support/openocd.cfg b/boards/infineon/cy8cproto_041tp/support/openocd.cfg new file mode 100644 index 000000000000..751be3351477 --- /dev/null +++ b/boards/infineon/cy8cproto_041tp/support/openocd.cfg @@ -0,0 +1,19 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +# Use KitProg3 interface +source [find interface/kitprog3.cfg] + +set ENABLE_ACQUIRE 0 +set PSOC4_USE_ACQUIRE 0 +transport select swd + +# Target configuration for PSoC4 +source [find target/infineon/psoc4.cfg] + +# Optional: specify a particular KitProg3 debugger if multiple are connected +if { [info exists _ZEPHYR_BOARD_SERIAL] } { + adapter serial $_ZEPHYR_BOARD_SERIAL +} diff --git a/boards/infineon/cy8cproto_062_4343w/cy8cproto_062_4343w.dts b/boards/infineon/cy8cproto_062_4343w/cy8cproto_062_4343w.dts index 5df947eccfed..e1014cf7ed23 100644 --- a/boards/infineon/cy8cproto_062_4343w/cy8cproto_062_4343w.dts +++ b/boards/infineon/cy8cproto_062_4343w/cy8cproto_062_4343w.dts @@ -34,7 +34,7 @@ }; uart5: &scb5 { - compatible = "infineon,cat1-uart"; + compatible = "infineon,uart"; status = "okay"; current-speed = <115200>; @@ -43,7 +43,7 @@ uart5: &scb5 { }; uart2: &scb2 { - compatible = "infineon,cat1-uart"; + compatible = "infineon,uart"; status = "okay"; /* The UART bus speed (current_speed) for zephyr_bt_uart should be the same @@ -77,6 +77,12 @@ uart2: &scb2 { }; }; +&clk_hf4 { + clock-div = <1>; + clocks = <&fll0>; + status = "okay"; +}; + &sdhc0 { status = "okay"; @@ -85,6 +91,13 @@ uart2: &scb2 { &p2_1_sdio_data1 &p2_2_sdio_data2 &p2_3_sdio_data3>; pinctrl-names = "default"; + bus-width = <4>; + max-bus-freq = <50000000>; + min-bus-freq = <400000>; + power-delay-ms = <1000>; + no-1-8-v; + clocks = <&clk_hf4>; + /* Wi-Fi configuration */ airoc-wifi { status = "okay"; @@ -129,7 +142,7 @@ uart2: &scb2 { }; i2c3: &scb3 { - compatible = "infineon,cat1-i2c"; + compatible = "infineon,i2c"; /* I2C pins */ pinctrl-0 = <&p6_0_scb3_i2c_scl &p6_1_scb3_i2c_sda>; diff --git a/boards/infineon/cy8cproto_063_ble/cy8cproto_063_ble.dts b/boards/infineon/cy8cproto_063_ble/cy8cproto_063_ble.dts index ea61b06df94d..94e4d7f5614c 100644 --- a/boards/infineon/cy8cproto_063_ble/cy8cproto_063_ble.dts +++ b/boards/infineon/cy8cproto_063_ble/cy8cproto_063_ble.dts @@ -81,7 +81,7 @@ }; uart5: &scb5 { - compatible = "infineon,cat1-uart"; + compatible = "infineon,uart"; status = "okay"; current-speed = <115200>; diff --git a/boards/infineon/cyw920829m2evk_02/CMakeLists.txt b/boards/infineon/cyw920829m2evk_02/CMakeLists.txt new file mode 100644 index 000000000000..103408ec1b9c --- /dev/null +++ b/boards/infineon/cyw920829m2evk_02/CMakeLists.txt @@ -0,0 +1,9 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_INFINEON_CAT1_QSPI_FLASH OR CONFIG_PM) + zephyr_include_directories(config) + zephyr_library_sources(config/qspi_memslot.c) +endif() diff --git a/boards/infineon/cyw920829m2evk_02/config/qspi_memslot.c b/boards/infineon/cyw920829m2evk_02/config/qspi_memslot.c new file mode 100644 index 000000000000..df9cebff4e51 --- /dev/null +++ b/boards/infineon/cyw920829m2evk_02/config/qspi_memslot.c @@ -0,0 +1,185 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "qspi_memslot.h" + +cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_read_cmd = {0}; + +cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_write_en_cmd = {0}; + +cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_write_dis_cmd = {0}; + +cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_erase_cmd = {0}; + +cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_chip_erase_cmd = {0}; + +cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_program_cmd = {0}; + +cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_read_sts_reg_qe_cmd = {0}; + +cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_read_sts_reg_wip_cmd = {0}; + +cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_write_sts_reg_qe_cmd = {0}; + +cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_read_sts_reg_oe_cmd = {0}; + +cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_write_sts_reg_oe_cmd = {0}; + +cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_read_latency_cmd = {0}; + +cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_write_latency_cmd = {0}; + +cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_read_sfdp_cmd = { + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x5AU, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 8U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE, +}; + +cy_stc_smif_octal_ddr_en_seq_t oe_sequence_SFDP_SlaveSlot_0 = { + .cmdSeq1Len = CY_SMIF_SFDP_ODDR_CMD_SEQ_MAX_LEN, + .cmdSeq2Len = CY_SMIF_SFDP_ODDR_CMD_SEQ_MAX_LEN, + .cmdSeq1 = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .cmdSeq2 = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, +}; + +/* Support for memories with hybrid regions is added in the version 1.50 + * Please refer to the changelog in + * https://iot-webserver.aus.cypress.com/projects/iot_release/ + * ASSETS/repo/mtb-pdl-cat1/develop/Latest/deploy/docs/ + * pdl_api_reference_manual/html/group__group__smif.html + * for more details + */ +#if (CY_SMIF_DRV_VERSION_MAJOR > 1) && (CY_SMIF_DRV_VERSION_MINOR >= 50) +static cy_stc_smif_hybrid_region_info_t sfdp_slave_slot_0_region_info_storage[16]; + +static cy_stc_smif_hybrid_region_info_t *sfdp_slave_slot_0_region_info[16] = { + &sfdp_slave_slot_0_region_info_storage[0], + &sfdp_slave_slot_0_region_info_storage[1], + &sfdp_slave_slot_0_region_info_storage[2], + &sfdp_slave_slot_0_region_info_storage[3], + &sfdp_slave_slot_0_region_info_storage[4], + &sfdp_slave_slot_0_region_info_storage[5], + &sfdp_slave_slot_0_region_info_storage[6], + &sfdp_slave_slot_0_region_info_storage[7], + &sfdp_slave_slot_0_region_info_storage[8], + &sfdp_slave_slot_0_region_info_storage[9], + &sfdp_slave_slot_0_region_info_storage[10], + &sfdp_slave_slot_0_region_info_storage[11], + &sfdp_slave_slot_0_region_info_storage[12], + &sfdp_slave_slot_0_region_info_storage[13], + &sfdp_slave_slot_0_region_info_storage[14], + &sfdp_slave_slot_0_region_info_storage[15], +}; +#endif + +cy_stc_smif_mem_device_cfg_t deviceCfg_SFDP_SlaveSlot_0 = { + /* Specifies the number of address bytes used by the memory slave device. */ + .numOfAddrBytes = 0x03U, + /* The size of the memory. */ + .memSize = 0x0000100U, + /* Specifies the Read command. */ + .readCmd = &sfdp_slave_slot_0_read_cmd, + /* Specifies the Write Enable command. */ + .writeEnCmd = &sfdp_slave_slot_0_write_en_cmd, + /* Specifies the Write Disable command. */ + .writeDisCmd = &sfdp_slave_slot_0_write_dis_cmd, + /* Specifies the Erase command. */ + .eraseCmd = &sfdp_slave_slot_0_erase_cmd, + /* Specifies the sector size of each erase. */ + .eraseSize = 0x0001000U, + /* Specifies the Chip Erase command. */ + .chipEraseCmd = &sfdp_slave_slot_0_chip_erase_cmd, + /* Specifies the Program command. */ + .programCmd = &sfdp_slave_slot_0_program_cmd, + /* Specifies the page size for programming. */ + .programSize = 0x0000100U, + /* Specifies the command to read the QE-containing status register. */ + .readStsRegQeCmd = &sfdp_slave_slot_0_read_sts_reg_qe_cmd, + /* Specifies the command to read the WIP-containing status register. */ + .readStsRegWipCmd = &sfdp_slave_slot_0_read_sts_reg_wip_cmd, + /* Specifies the read SFDP command */ + .readSfdpCmd = &sfdp_slave_slot_0_read_sfdp_cmd, + /* Specifies the command to write into the QE-containing status register. */ + .writeStsRegQeCmd = &sfdp_slave_slot_0_write_sts_reg_qe_cmd, + /* The mask for the status register. */ + .stsRegBusyMask = 0x00U, + /* The mask for the status register. */ + .stsRegQuadEnableMask = 0x00U, + /* The max time for the erase type-1 cycle-time in ms. */ + .eraseTime = 1U, + /* The max time for the chip-erase cycle-time in ms. */ + .chipEraseTime = 16U, + /* The max time for the page-program cycle-time in us. */ + .programTime = 8U, +#if (CY_SMIF_DRV_VERSION_MAJOR > 1) && (CY_SMIF_DRV_VERSION_MINOR >= 50) + /* Points to NULL or to structure with info about sectors for hybrid memory. */ + .hybridRegionCount = 0U, + .hybridRegionInfo = sfdp_slave_slot_0_region_info, +#endif + /* Specifies the command to read variable latency cycles configuration register */ + .readLatencyCmd = &sfdp_slave_slot_0_read_latency_cmd, + /* Specifies the command to write variable latency cycles configuration register */ + .writeLatencyCmd = &sfdp_slave_slot_0_write_latency_cmd, + /* Specifies the address for variable latency cycle address */ + .latencyCyclesRegAddr = 0x00U, + /* Specifies variable latency cycles Mask */ + .latencyCyclesMask = 0x00U, + /* Specifies data for memory with hybrid sectors */ + .octalDDREnableSeq = &oe_sequence_SFDP_SlaveSlot_0, + /* Specifies the command to read the OE-containing status register. */ + .readStsRegOeCmd = &sfdp_slave_slot_0_read_sts_reg_oe_cmd, + /* Specifies the command to write the OE-containing status register. */ + .writeStsRegOeCmd = &sfdp_slave_slot_0_write_sts_reg_oe_cmd, + /* QE mask for the status registers */ + .stsRegOctalEnableMask = 0x00U, + /* Octal enable register address */ + .octalEnableRegAddr = 0x00U, + /* Frequency of operation used in Octal mode */ + .freq_of_operation = CY_SMIF_100MHZ_OPERATION, +}; + +cy_stc_smif_mem_config_t sfdp_slave_slot_0 = { + /* Determines the slot number where the memory device is placed. */ + .slaveSelect = CY_SMIF_SLAVE_SELECT_0, + /* Flags. */ + .flags = CY_SMIF_FLAG_SMIF_REV_3 | CY_SMIF_FLAG_MEMORY_MAPPED | CY_SMIF_FLAG_WR_EN | + CY_SMIF_FLAG_DETECT_SFDP | CY_SMIF_FLAG_MERGE_ENABLE, + /* The data-line selection options for a slave device. */ + .dataSelect = CY_SMIF_DATA_SEL0, + /* The base address the memory slave + * Valid when the memory-mapped mode is enabled. + */ + .baseAddress = 0x60000000U, + /* The size allocated in the memory map, for the memory slave device. + * The size is allocated from the base address. Valid when the memory mapped mode is + * enabled. + */ + .memMappedSize = 0x100000U, + /* If this memory device is one of the devices in the dual quad SPI configuration. + * Valid when the memory mapped mode is enabled. + */ + .dualQuadSlots = 0, + /* The configuration of the device. */ + .deviceCfg = &deviceCfg_SFDP_SlaveSlot_0, + /** Continuous transfer merge timeout. + * After this period the memory device is deselected. A later transfer, even from a + * continuous address, starts with the overhead phases (command, address, mode, dummy + * cycles). This configuration parameter is available for CAT1B devices. + */ + .mergeTimeout = CY_SMIF_MERGE_TIMEOUT_1_CYCLE, +}; diff --git a/boards/infineon/cyw920829m2evk_02/config/qspi_memslot.h b/boards/infineon/cyw920829m2evk_02/config/qspi_memslot.h new file mode 100644 index 000000000000..ca2513550521 --- /dev/null +++ b/boards/infineon/cyw920829m2evk_02/config/qspi_memslot.h @@ -0,0 +1,18 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef QSPI_MEMSLOT_H +#define QSPI_MEMSLOT_H + +#include "cy_smif_memslot.h" + +/* Slave Select Pin */ +#define QSPI_SLAVE_SELECT (P2_0) + +extern cy_stc_smif_mem_config_t sfdp_slave_slot_0; + +#endif /*QSPI_MEMSLOT_H*/ diff --git a/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02-memory_map.dtsi b/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02-memory_map.dtsi index 7f0454ae4d59..bbe94a64160d 100644 --- a/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02-memory_map.dtsi +++ b/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02-memory_map.dtsi @@ -88,9 +88,9 @@ reg = <0x80000 0x60000>; }; - storage_partition: storage_partition@E0000 { + storage_partition: storage_partition@e0000 { compatible = "soc-nv-flash"; - reg = <0xE0000 DT_SIZE_K(64)>; + reg = <0xe0000 DT_SIZE_K(64)>; }; }; }; diff --git a/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.dtsi b/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.dtsi index bcc897ef17e7..1247bcb46833 100644 --- a/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.dtsi +++ b/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.dtsi @@ -26,7 +26,7 @@ }; uart2: &scb2 { - compatible = "infineon,cat1-uart"; + compatible = "infineon,uart"; status = "okay"; current-speed = <115200>; hw-flow-control; @@ -41,7 +41,7 @@ uart2: &scb2 { &dma0 { #address-cells = <1>; #size-cells = <0>; - compatible = "infineon,cat1-dma"; + compatible = "infineon,dma"; status = "okay"; }; diff --git a/boards/infineon/cyw920829m2evk_02/cyw920829m2ipa2.dtsi b/boards/infineon/cyw920829m2evk_02/cyw920829m2ipa2.dtsi index ef45416a5445..020ba2286713 100644 --- a/boards/infineon/cyw920829m2evk_02/cyw920829m2ipa2.dtsi +++ b/boards/infineon/cyw920829m2evk_02/cyw920829m2ipa2.dtsi @@ -11,7 +11,7 @@ / { qspi_flash: qspi_flash@40890000 { - compatible = "infineon,cat1-qspi-flash"; + compatible = "infineon,qspi-flash"; reg = <0x40890000 0x30000>; #address-cells = <1>; #size-cells = <1>; diff --git a/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk.dts b/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk.dts index bcfc3b3eb8ae..e90ff4293d08 100644 --- a/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk.dts +++ b/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk.dts @@ -27,7 +27,7 @@ }; uart3: &scb3 { - compatible = "infineon,cat1-uart"; + compatible = "infineon,uart"; status = "okay"; current-speed = <115200>; diff --git a/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk.yaml b/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk.yaml index 78acdfe1d22d..ec7983e4db39 100644 --- a/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk.yaml +++ b/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk.yaml @@ -15,5 +15,7 @@ toolchain: supported: - gpio - spi + - timer - uart + - dma vendor: infineon diff --git a/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk_psc3m5fds2afq1_ns.dts b/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk_psc3m5fds2afq1_ns.dts index 6231d9fb5729..3a79fda567b4 100644 --- a/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk_psc3m5fds2afq1_ns.dts +++ b/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk_psc3m5fds2afq1_ns.dts @@ -27,7 +27,7 @@ }; uart3: &scb3 { - compatible = "infineon,cat1-uart"; + compatible = "infineon,uart"; status = "okay"; current-speed = <115200>; diff --git a/boards/infineon/kit_pse84_ai/board.cmake b/boards/infineon/kit_pse84_ai/board.cmake index ff91a0f7ad3d..33699440154b 100644 --- a/boards/infineon/kit_pse84_ai/board.cmake +++ b/boards/infineon/kit_pse84_ai/board.cmake @@ -5,6 +5,7 @@ if(CONFIG_CPU_CORTEX_M55) # Connect to the second port for CM55 (default port is 3333) + board_runner_args(openocd "--gdb-init=disconnect") board_runner_args(openocd "--gdb-init=target extended-remote :3334") endif() diff --git a/boards/infineon/kit_pse84_ai/kit_pse84_ai_common.dtsi b/boards/infineon/kit_pse84_ai/kit_pse84_ai_common.dtsi index 08879ec8f6b5..076535698e30 100644 --- a/boards/infineon/kit_pse84_ai/kit_pse84_ai_common.dtsi +++ b/boards/infineon/kit_pse84_ai/kit_pse84_ai_common.dtsi @@ -55,7 +55,7 @@ }; uart2: &scb2 { - compatible = "infineon,cat1-uart"; + compatible = "infineon,uart"; status = "okay"; current-speed = <115200>; diff --git a/boards/infineon/kit_pse84_ai/kit_pse84_ai_m33.yaml b/boards/infineon/kit_pse84_ai/kit_pse84_ai_m33.yaml index 2bab72aed7ac..20eda5e05f7c 100644 --- a/boards/infineon/kit_pse84_ai/kit_pse84_ai_m33.yaml +++ b/boards/infineon/kit_pse84_ai/kit_pse84_ai_m33.yaml @@ -7,11 +7,12 @@ identifier: kit_pse84_ai/pse846gps2dbzc4a/m33 name: PSOC Edge84 AI Kit (M33_S) type: mcu arch: arm +ram: 5120 sysbuild: true toolchain: - zephyr supported: - clock_control - gpio - - pin_ctrl + - pinctrl - uart diff --git a/boards/infineon/kit_pse84_ai/kit_pse84_ai_m55.yaml b/boards/infineon/kit_pse84_ai/kit_pse84_ai_m55.yaml index df37cbff7085..19125395d788 100644 --- a/boards/infineon/kit_pse84_ai/kit_pse84_ai_m55.yaml +++ b/boards/infineon/kit_pse84_ai/kit_pse84_ai_m55.yaml @@ -7,11 +7,12 @@ identifier: kit_pse84_ai/pse846gps2dbzc4a/m55 name: PSOC Edge84 AI Kit (M55) type: mcu arch: arm +ram: 5120 sysbuild: true toolchain: - zephyr supported: - clock_control - gpio - - pin_ctrl + - pinctrl - uart diff --git a/boards/infineon/kit_pse84_ai/kit_pse84_ai_memory_map.dtsi b/boards/infineon/kit_pse84_ai/kit_pse84_ai_memory_map.dtsi index c8c7796de4a8..4e315583bf10 100644 --- a/boards/infineon/kit_pse84_ai/kit_pse84_ai_memory_map.dtsi +++ b/boards/infineon/kit_pse84_ai/kit_pse84_ai_memory_map.dtsi @@ -70,7 +70,7 @@ * - 2mb for each of the cores(cm33_s, cm33 and cm55) */ flash_controller: flash_controller@40250000 { - compatible = "infineon,cat1-qspi-flash-mtb-hal"; + compatible = "infineon,qspi-flash-mtb-hal"; reg = <0x40250000 0x10000>; #address-cells = <1>; #size-cells = <1>; @@ -96,7 +96,7 @@ }; m33s_xip: m33s_xip@70100400 { - reg = <0x70100400 0x1FFC00>; + reg = <0x70100400 0x1ffc00>; }; m33_xip: m33_xip@8300000 { diff --git a/boards/infineon/kit_pse84_eval/board.cmake b/boards/infineon/kit_pse84_eval/board.cmake index ff91a0f7ad3d..33699440154b 100644 --- a/boards/infineon/kit_pse84_eval/board.cmake +++ b/boards/infineon/kit_pse84_eval/board.cmake @@ -5,6 +5,7 @@ if(CONFIG_CPU_CORTEX_M55) # Connect to the second port for CM55 (default port is 3333) + board_runner_args(openocd "--gdb-init=disconnect") board_runner_args(openocd "--gdb-init=target extended-remote :3334") endif() diff --git a/boards/infineon/kit_pse84_eval/doc/index.rst b/boards/infineon/kit_pse84_eval/doc/index.rst index 2b13eb58d47d..651d9d76cce1 100644 --- a/boards/infineon/kit_pse84_eval/doc/index.rst +++ b/boards/infineon/kit_pse84_eval/doc/index.rst @@ -59,6 +59,10 @@ Please refer to `kit_pse84_eval User Manual Website`_ for more details. Programming and Debugging ************************* +.. NOTE:: + `BOOT SW` on the board **MUST** be set to `ON` for any sample applications to work. On some + boards this switch may be under the attached LCD screen. + .. zephyr:board-supported-runners:: The KIT-PSE84-EVAL includes an onboard programmer/debugger (`KitProg3`_) to provide debugging, @@ -70,6 +74,7 @@ Infineon OpenOCD and Edge Protect Security Suite (edgeprotecttools). Flashing ======== + Applications for the ``kit_pse84_eval/pse846gps2dbzc4a/m33`` board target can be built, flashed, and debugged in the usual way. See :ref:`build_an_application` and :ref:`application_run` for more details on @@ -80,9 +85,13 @@ board target need to be built using sysbuild to include the required application Enter the following command to compile ``hello_world`` for the CM55 core: -.. code-block:: console +.. zephyr-app-commands:: + :app: samples/hello_world + :board: kit_pse84_eval/pse846gps2dbzc4a/m55 + :goals: build flash + :west-args: --sysbuild + :gen-args: -DOPENOCD=path/to/infineon/openocd/bin/openocd - west build -p -b kit_pse84_eval/pse846gps2dbzc4a/m55 .\samples\hello_world --sysbuild Debugging ========= @@ -98,11 +107,6 @@ to set the CMake variable ``OPENOCD``. # Run west config once to set permanent CMake argument west config build.cmake-args -- -DOPENOCD=path/to/infineon/openocd/bin/openocd.exe - # Do a pristine build once after setting CMake argument - west build -b kit_pse84_eval/pse846gps2dbzc4a/m33 -p always samples/basic/blinky - west flash - west debug - .. group-tab:: Linux .. code-block:: shell @@ -110,11 +114,10 @@ to set the CMake variable ``OPENOCD``. # Run west config once to set permanent CMake argument west config build.cmake-args -- -DOPENOCD=path/to/infineon/openocd/bin/openocd - # Do a pristine build once after setting CMake argument - west build -b kit_pse84_eval/pse846gps2dbzc4a/m33 -p always samples/basic/blinky - - west flash - west debug +.. zephyr-app-commands:: + :app: samples/basic/blinky + :board: kit_pse84_eval/pse846gps2dbzc4a/m33 + :goals: debug Once the gdb console starts after executing the west debug command, you may now set breakpoints and perform other standard GDB debugging on the PSOC E84 CM33 core. diff --git a/boards/infineon/kit_pse84_eval/kconfig.defconfig b/boards/infineon/kit_pse84_eval/kconfig.defconfig new file mode 100644 index 000000000000..8962ddd2959a --- /dev/null +++ b/boards/infineon/kit_pse84_eval/kconfig.defconfig @@ -0,0 +1,30 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_KIT_PSE84_EVAL_PSE846GPS2DBZC4A_M55 + +if WIFI + +# Select AIROC part and module +choice AIROC_PART + default CYW55500 +endchoice + +choice CYW55500_MODULE + default CYW55513IUBG_SM +endchoice + +# Enable L2 Ethernet +config NET_L2_ETHERNET + default y + +# Heap Pool Size +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 15000 + +endif # WIFI + +endif # BOARD_KIT_PSE84_EVAL_PSE846GPS2DBZC4A_M55 diff --git a/boards/infineon/kit_pse84_eval/kit_pse84_eval_common-pinctrl.dtsi b/boards/infineon/kit_pse84_eval/kit_pse84_eval_common-pinctrl.dtsi index e536b8c9b1ed..5faf08fd3a6b 100644 --- a/boards/infineon/kit_pse84_eval/kit_pse84_eval_common-pinctrl.dtsi +++ b/boards/infineon/kit_pse84_eval/kit_pse84_eval_common-pinctrl.dtsi @@ -13,3 +13,75 @@ &p6_5_scb2_uart_rx { input-enable; }; + +&p21_0_sdhc0_card_cmd { + drive-push-pull; + input-enable; + drive-strength = "half"; +}; + +&p12_0_sdhc0_clk_card { + drive-push-pull; + input-enable; + drive-strength = "half"; +}; + +&p12_1_sdhc0_card_dat_3to0 { + drive-push-pull; + input-enable; + drive-strength = "half"; +}; + +&p12_2_sdhc0_card_dat_3to0 { + drive-push-pull; + input-enable; + drive-strength = "half"; +}; + +&p12_4_sdhc0_card_dat_3to0 { + drive-push-pull; + input-enable; + drive-strength = "half"; +}; + +&p12_5_sdhc0_card_dat_3to0 { + drive-push-pull; + input-enable; + drive-strength = "half"; +}; + +&p7_0_sdhc1_card_cmd { + drive-push-pull; + input-enable; + drive-strength = "half"; +}; + +&p7_1_sdhc1_clk_card { + drive-push-pull; + input-enable; + drive-strength = "half"; +}; + +&p7_3_sdhc1_card_dat_3to0 { + drive-push-pull; + input-enable; + drive-strength = "half"; +}; + +&p7_5_sdhc1_card_dat_3to0 { + drive-push-pull; + input-enable; + drive-strength = "half"; +}; + +&p7_6_sdhc1_card_dat_3to0 { + drive-push-pull; + input-enable; + drive-strength = "half"; +}; + +&p7_7_sdhc1_card_dat_3to0 { + drive-push-pull; + input-enable; + drive-strength = "half"; +}; diff --git a/boards/infineon/kit_pse84_eval/kit_pse84_eval_common.dtsi b/boards/infineon/kit_pse84_eval/kit_pse84_eval_common.dtsi index c4e5affbee15..307a4861594a 100644 --- a/boards/infineon/kit_pse84_eval/kit_pse84_eval_common.dtsi +++ b/boards/infineon/kit_pse84_eval/kit_pse84_eval_common.dtsi @@ -45,7 +45,7 @@ }; uart2: &scb2 { - compatible = "infineon,cat1-uart"; + compatible = "infineon,uart"; status = "okay"; current-speed = <115200>; @@ -78,6 +78,10 @@ uart2: &scb2 { status = "okay"; }; +&gpio_prt11 { + status = "okay"; +}; + &gpio_prt13 { status = "okay"; }; @@ -89,3 +93,7 @@ uart2: &scb2 { &gpio_prt16 { status = "okay"; }; + +&gpio_prt17 { + status = "okay"; +}; diff --git a/boards/infineon/kit_pse84_eval/kit_pse84_eval_m33.dts b/boards/infineon/kit_pse84_eval/kit_pse84_eval_m33.dts index bbff96224444..79f147c56ef7 100644 --- a/boards/infineon/kit_pse84_eval/kit_pse84_eval_m33.dts +++ b/boards/infineon/kit_pse84_eval/kit_pse84_eval_m33.dts @@ -31,6 +31,10 @@ }; }; +&mcwdt0 { + status = "okay"; +}; + /* For the dpll clocks declared below * The clock-frequency value is here for dts reference, but * it does not affect the frequency set by the clock_control diff --git a/boards/infineon/kit_pse84_eval/kit_pse84_eval_m33.yaml b/boards/infineon/kit_pse84_eval/kit_pse84_eval_m33.yaml index d91137ec41bc..8005f3b38d7c 100644 --- a/boards/infineon/kit_pse84_eval/kit_pse84_eval_m33.yaml +++ b/boards/infineon/kit_pse84_eval/kit_pse84_eval_m33.yaml @@ -8,12 +8,13 @@ name: PSOC Edge84 Evaluation Kit (M33_S) type: mcu arch: arm sysbuild: true +ram: 5120 toolchain: - zephyr supported: - clock_control - dma - gpio - - pin_ctrl + - pinctrl - uart - spi diff --git a/boards/infineon/kit_pse84_eval/kit_pse84_eval_m33_defconfig b/boards/infineon/kit_pse84_eval/kit_pse84_eval_m33_defconfig index cf7084e84d45..c8c4ea550b9a 100644 --- a/boards/infineon/kit_pse84_eval/kit_pse84_eval_m33_defconfig +++ b/boards/infineon/kit_pse84_eval/kit_pse84_eval_m33_defconfig @@ -8,7 +8,6 @@ CONFIG_FPU=y CONFIG_FPU_SHARING=y # General configuration -CONFIG_CORTEX_M_SYSTICK=y CONFIG_BUILD_OUTPUT_HEX=y CONFIG_ARM_MPU=y diff --git a/boards/infineon/kit_pse84_eval/kit_pse84_eval_m55.dts b/boards/infineon/kit_pse84_eval/kit_pse84_eval_m55.dts index 506c0a8e51a0..eed1ea8763f1 100644 --- a/boards/infineon/kit_pse84_eval/kit_pse84_eval_m55.dts +++ b/boards/infineon/kit_pse84_eval/kit_pse84_eval_m55.dts @@ -32,5 +32,97 @@ zephyr,sram = &m55_data; zephyr,console = &uart2; zephyr,shell-uart = &uart2; + zephyr,dtcm = &dtcm; + zephyr,itcm = &itcm; + }; + + power-states { + sleep: sleep { + compatible = "zephyr,power-state"; + power-state-name = "suspend-to-idle"; + min-residency-us = <1000000>; + }; + + deepsleep: deepsleep { + compatible = "zephyr,power-state"; + power-state-name = "suspend-to-ram"; + min-residency-us = <2000000>; + exit-latency-us = <20>; + }; + }; + + cpus { + cpu@1 { + cpu-power-states = <&sleep &deepsleep>; + }; + }; +}; + +&mcwdt1 { + status = "okay"; +}; + +&peri1_group2_8bit_0 { + status = "okay"; + resource-type = ; + resource-instance = <0>; + clock-div = <2>; +}; + +&peri1_group3_8bit_0 { + status = "okay"; + resource-type = ; + resource-instance = <1>; + clock-div = <2>; +}; + +&sdhc0 { + status = "okay"; + + /* SDIO pins */ + pinctrl-0 = <&p21_0_sdhc0_card_cmd &p12_0_sdhc0_clk_card &p12_1_sdhc0_card_dat_3to0 + &p12_2_sdhc0_card_dat_3to0 &p12_4_sdhc0_card_dat_3to0 + &p12_5_sdhc0_card_dat_3to0>; + pinctrl-names = "default"; + + clocks = <&peri1_group2_8bit_0>; + bus-width = <4>; + max-bus-freq = <50000000>; + min-bus-freq = <400000>; + power-delay-ms = <1000>; + no-1-8-v; + + /* Wi-Fi configuration */ + airoc-wifi { + status = "okay"; + compatible = "infineon,airoc-wifi"; + + /* Wi-Fi control gpios */ + wifi-reg-on-gpios = <&gpio_prt11 6 GPIO_ACTIVE_HIGH>; + wifi-host-wake-gpios = <&gpio_prt11 4 GPIO_ACTIVE_HIGH>; + }; +}; + +&sdhc1 { + status = "okay"; + + /* SDHC pins */ + pinctrl-0 = <&p7_0_sdhc1_card_cmd &p7_1_sdhc1_clk_card &p7_3_sdhc1_card_dat_3to0 + &p7_5_sdhc1_card_dat_3to0 &p7_6_sdhc1_card_dat_3to0 + &p7_7_sdhc1_card_dat_3to0>; + pinctrl-names = "default"; + + clocks = <&peri1_group3_8bit_0>; + bus-width = <4>; + max-bus-freq = <100000000>; + min-bus-freq = <400000>; + power-delay-ms = <1000>; + /* Card detect gpios */ + cd-gpios = <&gpio_prt17 7 GPIO_PULL_UP>; + + sdmmc { + compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; + status = "okay"; }; }; diff --git a/boards/infineon/kit_pse84_eval/kit_pse84_eval_m55.yaml b/boards/infineon/kit_pse84_eval/kit_pse84_eval_m55.yaml index 85a0bf3f10ca..333e396cb7a3 100644 --- a/boards/infineon/kit_pse84_eval/kit_pse84_eval_m55.yaml +++ b/boards/infineon/kit_pse84_eval/kit_pse84_eval_m55.yaml @@ -7,6 +7,7 @@ identifier: kit_pse84_eval/pse846gps2dbzc4a/m55 name: PSOC Edge84 Evaluation Kit (M55) type: mcu arch: arm +ram: 5120 sysbuild: true toolchain: - zephyr @@ -14,6 +15,7 @@ supported: - clock_control - dma - gpio - - pin_ctrl + - pinctrl - uart - spi + - sdhc diff --git a/boards/infineon/kit_pse84_eval/kit_pse84_eval_memory_map.dtsi b/boards/infineon/kit_pse84_eval/kit_pse84_eval_memory_map.dtsi index 3cb3347c9337..1f9420fa6d73 100644 --- a/boards/infineon/kit_pse84_eval/kit_pse84_eval_memory_map.dtsi +++ b/boards/infineon/kit_pse84_eval/kit_pse84_eval_memory_map.dtsi @@ -71,7 +71,7 @@ */ flash_controller: flash_controller@40250000 { - compatible = "infineon,cat1-qspi-flash"; + compatible = "infineon,qspi-flash"; reg = <0x40250000 0x10000>; #address-cells = <1>; #size-cells = <1>; diff --git a/boards/infineon/kit_t2g_b_h_evk/kit_t2g_b_h_evk_common.dtsi b/boards/infineon/kit_t2g_b_h_evk/kit_t2g_b_h_evk_common.dtsi index 45b5df0cfd0b..8cf985cb47bf 100644 --- a/boards/infineon/kit_t2g_b_h_evk/kit_t2g_b_h_evk_common.dtsi +++ b/boards/infineon/kit_t2g_b_h_evk/kit_t2g_b_h_evk_common.dtsi @@ -55,7 +55,7 @@ }; uart3: &scb3 { - compatible = "infineon,cat1-uart"; + compatible = "infineon,uart"; status = "okay"; current-speed = <115200>; diff --git a/boards/infineon/kit_t2g_b_h_lite/kit_t2g_b_h_lite_common.dtsi b/boards/infineon/kit_t2g_b_h_lite/kit_t2g_b_h_lite_common.dtsi index d09baecea197..46bf6fbdac45 100644 --- a/boards/infineon/kit_t2g_b_h_lite/kit_t2g_b_h_lite_common.dtsi +++ b/boards/infineon/kit_t2g_b_h_lite/kit_t2g_b_h_lite_common.dtsi @@ -55,7 +55,7 @@ }; uart0: &scb0 { - compatible = "infineon,cat1-uart"; + compatible = "infineon,uart"; status = "okay"; current-speed = <115200>; diff --git a/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_common.dtsi b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_common.dtsi index 43137558abcf..e6bdf31a5c76 100644 --- a/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_common.dtsi +++ b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_common.dtsi @@ -54,7 +54,7 @@ }; uart3: &scb3 { - compatible = "infineon,cat1-uart"; + compatible = "infineon,uart"; status = "okay"; current-speed = <115200>; diff --git a/boards/infineon/xmc45_relax_kit/xmc45_relax_kit.dts b/boards/infineon/xmc45_relax_kit/xmc45_relax_kit.dts index b578d244bea4..760ef20259ed 100644 --- a/boards/infineon/xmc45_relax_kit/xmc45_relax_kit.dts +++ b/boards/infineon/xmc45_relax_kit/xmc45_relax_kit.dts @@ -83,6 +83,7 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + ranges; code_partition: partition@0 { reg = <0x0 0x80000>; @@ -111,6 +112,8 @@ fifo-start-offset = <0>; fifo-tx-size = <16>; fifo-rx-size = <16>; + data-bits = <8>; + stop-bits = "1"; status = "okay"; }; diff --git a/boards/infineon/xmc47_relax_kit/xmc47_relax_kit.dts b/boards/infineon/xmc47_relax_kit/xmc47_relax_kit.dts index 11bd2f42e3c4..528142633a2d 100644 --- a/boards/infineon/xmc47_relax_kit/xmc47_relax_kit.dts +++ b/boards/infineon/xmc47_relax_kit/xmc47_relax_kit.dts @@ -102,6 +102,8 @@ fifo-start-offset = <0>; fifo-tx-size = <16>; fifo-rx-size = <16>; + data-bits = <8>; + stop-bits = "1"; status = "okay"; }; @@ -116,6 +118,8 @@ fifo-start-offset = <0>; fifo-tx-size = <0>; fifo-rx-size = <0>; + data-bits = <8>; + stop-bits = "1"; status = "okay"; }; diff --git a/boards/innblue/innblue21/innblue21_nrf9160_ns.dts b/boards/innblue/innblue21/innblue21_nrf9160_ns.dts index 2afcddfd579d..35e82e58cae6 100644 --- a/boards/innblue/innblue21/innblue21_nrf9160_ns.dts +++ b/boards/innblue/innblue21/innblue21_nrf9160_ns.dts @@ -5,7 +5,7 @@ */ /dts-v1/; -#include +#include #include "innblue21_common.dtsi" / { diff --git a/boards/innblue/innblue22/innblue22_nrf9160_ns.dts b/boards/innblue/innblue22/innblue22_nrf9160_ns.dts index 93fa33ba334c..6d1b7523e049 100644 --- a/boards/innblue/innblue22/innblue22_nrf9160_ns.dts +++ b/boards/innblue/innblue22/innblue22_nrf9160_ns.dts @@ -5,7 +5,7 @@ */ /dts-v1/; -#include +#include #include "innblue22_common.dtsi" / { diff --git a/boards/intel/adsp/Kconfig.intel_adsp b/boards/intel/adsp/Kconfig.intel_adsp index 0a29c0d13819..e4f1d6b479cb 100644 --- a/boards/intel/adsp/Kconfig.intel_adsp +++ b/boards/intel/adsp/Kconfig.intel_adsp @@ -2,16 +2,16 @@ # SPDX-License-Identifier: Apache-2.0 config BOARD_INTEL_ADSP - select SOC_INTEL_CAVS_V25 if BOARD_INTEL_ADSP_CAVS25 - select SOC_INTEL_CAVS_V25 if BOARD_INTEL_ADSP_CAVS25_TGPH - select SOC_INTEL_ACE15_MTPM if BOARD_INTEL_ADSP_ACE15_MTPM - select SOC_INTEL_ACE15_MTPM if BOARD_INTEL_ADSP_ACE15_MTPM_SIM - select SOC_INTEL_ACE20_LNL if BOARD_INTEL_ADSP_ACE20_LNL - select SOC_INTEL_ACE20_LNL if BOARD_INTEL_ADSP_ACE20_LNL_SIM - select SOC_INTEL_ACE30 if BOARD_INTEL_ADSP_ACE30_PTL - select SOC_INTEL_ACE30 if BOARD_INTEL_ADSP_ACE30_PTL_SIM - select SOC_INTEL_ACE30 if BOARD_INTEL_ADSP_ACE30_WCL - select SOC_INTEL_ACE30 if BOARD_INTEL_ADSP_ACE30_WCL_SIM - select SOC_INTEL_ACE40 if BOARD_INTEL_ADSP_ACE40_NVL - select SOC_INTEL_ACE40 if BOARD_INTEL_ADSP_ACE40_NVL_SIM - select SOC_INTEL_ACE40 if BOARD_INTEL_ADSP_ACE40_NVLS + select SOC_CAVSV25 if BOARD_INTEL_ADSP_CAVS25 + select SOC_CAVSV25 if BOARD_INTEL_ADSP_CAVS25_TGPH + select SOC_ACE15_MTPM if BOARD_INTEL_ADSP_ACE15_MTPM + select SOC_ACE15_MTPM if BOARD_INTEL_ADSP_ACE15_MTPM_SIM + select SOC_ACE20_LNL if BOARD_INTEL_ADSP_ACE20_LNL + select SOC_ACE20_LNL if BOARD_INTEL_ADSP_ACE20_LNL_SIM + select SOC_ACE30 if BOARD_INTEL_ADSP_ACE30_PTL + select SOC_ACE30 if BOARD_INTEL_ADSP_ACE30_PTL_SIM + select SOC_ACE30 if BOARD_INTEL_ADSP_ACE30_WCL + select SOC_ACE30 if BOARD_INTEL_ADSP_ACE30_WCL_SIM + select SOC_ACE40 if BOARD_INTEL_ADSP_ACE40_NVL + select SOC_ACE40 if BOARD_INTEL_ADSP_ACE40_NVL_SIM + select SOC_ACE40 if BOARD_INTEL_ADSP_ACE40_NVLS diff --git a/boards/intel/adsp/twister.yaml b/boards/intel/adsp/twister.yaml index 1882a85f9f6e..16f5fe3fe720 100644 --- a/boards/intel/adsp/twister.yaml +++ b/boards/intel/adsp/twister.yaml @@ -11,6 +11,7 @@ testing: - net - bluetooth - mcumgr + - newlib variants: intel_adsp/ace30/wcl: toolchain: @@ -27,20 +28,27 @@ variants: testing: timeout_multiplier: 8 intel_adsp/ace30/ptl: + ram: 4092 toolchain: - xt-clang - zephyr intel_adsp/ace30: twister: false + intel_adsp/ace20_lnl: + ram: 2048 intel_adsp/ace20_lnl/sim: type: sim + ram: 2048 simulation: - name: custom exec: acesim testing: timeout_multiplier: 4 + intel_adsp/ace15_mtpm: + ram: 2048 intel_adsp/ace15_mtpm/sim: type: sim + ram: 2048 simulation: - name: custom exec: acesim @@ -48,6 +56,7 @@ variants: timeout_multiplier: 4 intel_adsp/ace30/ptl/sim: type: sim + ram: 4096 simulation: - name: custom exec: acesim @@ -60,10 +69,12 @@ variants: toolchain: - xt-clang intel_adsp/ace40/nvl: + ram: 4096 toolchain: - xt-clang intel_adsp/ace40/nvl/sim: type: sim + ram: 4096 toolchain: - xt-clang simulation: diff --git a/boards/intel/ehl/doc/index.rst b/boards/intel/ehl/doc/index.rst index 16bf6c2bd226..0ebab5c5cbd8 100644 --- a/boards/intel/ehl/doc/index.rst +++ b/boards/intel/ehl/doc/index.rst @@ -12,7 +12,7 @@ This board configuration enables kernel support for the `EHL`_ board. .. note:: This board configuration works on the variant of `EHL`_ - boards containing Intel |reg| Atom |trade| SoC. + boards containing Intel® Atom™ SoC. Hardware ******** diff --git a/boards/intel/socfpga_std/cyclonev_socdk/cyclonev_socdk.dts b/boards/intel/socfpga_std/cyclonev_socdk/cyclonev_socdk.dts index 7e6f8740eae1..9243c1b3f9a1 100644 --- a/boards/intel/socfpga_std/cyclonev_socdk/cyclonev_socdk.dts +++ b/boards/intel/socfpga_std/cyclonev_socdk/cyclonev_socdk.dts @@ -14,7 +14,6 @@ compatible = "altr,socfpga-cyclonev-socdk", "altr,socfpga-cyclonev", "altr,socfpga"; ddr0: memory@0 { - name = "memory"; device_type = "memory"; reg = <0x0 0x40000000>; /* 1GB */ }; diff --git a/boards/intel/wcl/board.yml b/boards/intel/wcl/board.yml index c7fc9d37506f..88803532bceb 100644 --- a/boards/intel/wcl/board.yml +++ b/boards/intel/wcl/board.yml @@ -1,5 +1,6 @@ boards: - name: intel_wcl_crb + full_name: Wildcat Lake CRB vendor: intel socs: - name: wildcat_lake diff --git a/boards/ite/it515xx_evb/Kconfig.defconfig b/boards/ite/it515xx_evb/Kconfig.defconfig deleted file mode 100644 index e5033cdd7c32..000000000000 --- a/boards/ite/it515xx_evb/Kconfig.defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright (c) 2025 ITE Corporation. All Rights Reserved. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_IT515XX_EVB - -if PM - -config PM_DEVICE - default y - -choice PM_POLICY - default PM_POLICY_CUSTOM -endchoice - -endif # PM - -endif # BOARD_IT515XX_EVB diff --git a/boards/ite/it515xx_evb/Kconfig.it515xx_evb b/boards/ite/it515xx_evb/Kconfig.it515xx_evb deleted file mode 100644 index 123837216ab8..000000000000 --- a/boards/ite/it515xx_evb/Kconfig.it515xx_evb +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2025 ITE Corporation. All Rights Reserved. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_IT515XX_EVB - select SOC_IT51526AW diff --git a/boards/ite/it515xx_evb/board.yml b/boards/ite/it515xx_evb/board.yml deleted file mode 100644 index d4c7074979fa..000000000000 --- a/boards/ite/it515xx_evb/board.yml +++ /dev/null @@ -1,6 +0,0 @@ -board: - name: it515xx_evb - full_name: IT51XXX series - vendor: ite - socs: - - name: it51526aw diff --git a/boards/ite/it515xx_evb/doc/index.rst b/boards/ite/it515xx_evb/doc/index.rst deleted file mode 100644 index cdd3ad54735b..000000000000 --- a/boards/ite/it515xx_evb/doc/index.rst +++ /dev/null @@ -1,163 +0,0 @@ -.. zephyr:board:: it515xx_evb - -Overview -******** - -The IT51XXX is a 32-bit RISC-V microcontroller. -And a highly integrated embedded controller with system functions. -It is suitable for mobile system applications. The picture below is -the IT51526 development board (also known as it515xx_evb) and its debug card. - -.. figure:: it515xx_evb_and_debug_card.webp - :align: center - :alt: IT51526 EVB - -To find out more about ITE, visit our World Wide Web at:`ITE's website`_ - -Hardware -******** -The IT51XXX series contains different chip types(ex, it51526, it51527), -and they support different hardware features. -Listing the IT51526 hardware features as following: - -- RISC-V RV32IMC instruction set -- 4KB instruction cache size -- 128KB SRAM in total -- Built-in 32.768 kHz clock generator -- Embedded Flash, 512K/1024K-byte e-flash -- eSPI, SPI, BRAM, KBC, PECI, UART -- GPIO, PWM, ADC, INTC, WUC, Timer, Watchdog, KB scan, JTAG -- Support 3 Voltage Comparator -- Support Cryptographic Engine -- 9 SMBus hosts, 3 targets, with 12 SMBus channels, compatible with I2C -- I3C host: Support two I3C controllers, compliant with the MIPI I3C v1.0 SEPC. -- Two-wire serial interface up to 12.5MHz using Push-Pull. -- Support SDR, IBI, Hot-Join. -- I3C target: Support SDR, FIFO co-use DLM. Support Push-Pull output. - - -Supported Features -================== - -.. zephyr:board-supported-hw:: - -Programming and debugging on it51526 -************************************ - -In order to upload the application to the device, -you'll need our flash tool and Download board. -You can get them at: `ITE's website`_. - -Wiring -======= -#. Connect the Download Board to your host computer using the USB cable. - -#. Connect the it515xx_evb to the evolution motherboard. - -#. Connect the Download Board J5 to J38(GPC1 & GPC2) on the evolution motherboard. - -#. Connect the USB to UART wire to UART0 connector on the evolution motherboard. - - .. image:: it515xx_evb_wiring.webp - :align: center - :alt: it515xx_evb wiring - - .. note:: Be careful during connection! - Use separate wires to connect I2C pins with pins on the it515xx_evb board. - Wiring connection is described in the table below. - - +-------------+---------------+ - | J5 | it515xx_evb | - | Connector | J38 Connector | - +=============+===============+ - | 2 | C1 | - +-------------+---------------+ - | 3 | C2 | - +-------------+---------------+ - | 4 | GND | - +-------------+---------------+ - - For USB to UART cable, connect the evolution motherboard as below: - - +-------------+---------------+ - | USB to UART | Evolution | - | cable | motherboard | - | | UART0 | - | | Connector | - +=============+===============+ - | USB | UART0 | - +-------------+---------------+ - -Building -======== - -#. Build :zephyr:code-sample:`hello_world` application as you would normally do - (see :`Zephyr Getting Started Guide`_):. - - .. zephyr-app-commands:: - :board: it515xx_evb - :zephyr-app: samples/hello_world - :goals: build - -#. The file :file:`zephyr.bin` will be created by west. - -Flashing -======== - -Windows --------- - -Use the winflash tool to program a zephyr application -to the it515xx board flash. - -#. Flashing steps as described in the link: `Flashing steps`_. - -#. Turn on the it515xx_evb board switch, you should see ``"Hello World! it515xx_evb"`` - sent by the board. If you don't see this message, press the Reset button and the - message should appear. - -Ubuntu --------- - -#. Run your favorite terminal program to listen for output. - Under Linux the terminal should be :code:`/dev/ttyUSB0`. Do not close it. - - For example: - - .. code-block:: console - - $ minicom -D /dev/ttyUSB0 -b 115200 - -#. Open a second terminal window and use the Linux flash tool to flash your board. - - .. code-block:: console - - $ sudo ~/itetool/ite -f build/zephyr/zephyr.bin - - .. note:: The source code of ITE tool can be downloaded here: - https://www.ite.com.tw/upload/2024_01_23/6_20240123162336wu55j1Rjm4.bz2 - -#. Split first and second terminal windows to view both of them. - You should see ``"Hello World! it515xx_evb"`` in the first terminal window. - If you don't see this message, press the Reset button and the message should appear. - -Debugging -========= - -it515xx_evb board can be debugged by connecting USB to UART. We can write commands and -read messages through minicom in the Ubuntu terminal. - -Troubleshooting -=============== - -#. If the flash tool reports a failure, re-plug the 8390 Download board or - power cycle the it515xx_evb board and try again. - -References -========== - -.. target-notes:: - -.. _ITE's website: https://www.ite.com.tw/en -.. _Zephyr Getting Started Guide: https://docs.zephyrproject.org/latest/getting_started/index.html -.. _Flashing steps: https://docs.zephyrproject.org/latest/boards/ite/it82xx2_evb/doc/index.html#flashing diff --git a/boards/ite/it515xx_evb/it515xx_evb.dts b/boards/ite/it515xx_evb/it515xx_evb.dts deleted file mode 100644 index b9be1896e0cc..000000000000 --- a/boards/ite/it515xx_evb/it515xx_evb.dts +++ /dev/null @@ -1,139 +0,0 @@ -/* - * Copyright (c) 2025 ITE Corporation. All Rights Reserved. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include -#include - -/ { - model = "IT515XX EV-Board"; - compatible = "ite,it515xx-evb"; - - aliases { - i2c-0 = &i2c0; - led0 = &led0; - watchdog0 = &twd0; - pwm-0 = &pwm0; - }; - - chosen { - zephyr,console = &uart1; - zephyr,shell-uart = &uart1; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,flash-controller = &flashctrl; - }; - - leds { - compatible = "gpio-leds"; - - led0: led_0 { - gpios = <&gpioc 0 GPIO_ACTIVE_HIGH>; - label = "Green LED"; - }; - }; -}; - -&i2c0 { - status = "okay"; - clock-frequency = ; - pinctrl-0 = <&i2c0_clk_gpf2_default - &i2c0_data_gpf3_default>; - pinctrl-names = "default"; -}; - -&uart1 { - status = "okay"; - current-speed = <115200>; - clock-frequency = <1843200>; - pinctrl-0 = <&uart1_rx_gpc7_default - &uart1_tx_gpe6_default>; - pinctrl-names = "default"; -}; - -&ite_uart1_wrapper { - status = "okay"; -}; - -&kbd { - status = "okay"; - pinctrl-0 = <&ksi0_default - &ksi1_default - &ksi2_default - &ksi3_default - &ksi4_default - &ksi5_default - &ksi6_default - &ksi7_default - &kso0_default - &kso1_default - &kso2_default - &kso3_default - &kso4_default - &kso5_default - &kso6_default - &kso7_default - &kso8_default - &kso9_default - &kso10_default - &kso11_default - &kso12_default - &kso13_default - &kso14_default - &kso15_default>; - pinctrl-names = "default"; - row-size = <8>; - col-size = <16>; -}; - -&adc0 { - status = "okay"; - pinctrl-0 = <&adc0_ch3_gpi3_default>; - pinctrl-names = "default"; -}; - -/* - * test pwm: - * If we need pwm output in ITE chip power saving mode, - * then we should set pwm output frequency <=324Hz. - */ -&pwm0 { - status = "okay"; - prescaler-cx = ; - pinctrl-0 = <&pwm0_gpa0_default>; - pinctrl-names = "default"; -}; - -/* test fan */ -&pwm7 { - status = "okay"; - prescaler-cx = ; - pinctrl-0 = <&pwm7_gpa7_default>; - pinctrl-names = "default"; -}; - -/* test fan tachometer sensor */ -&tach0 { - status = "okay"; - input-pin = ; - pulses-per-round = <2>; - pinctrl-0 = <&tach0a_gpd6_default>; - pinctrl-names = "default"; -}; - -&sha256 { - status = "okay"; -}; - -/* voltage comparator for test */ -&vcmp1 { - status = "okay"; - threshold-mv = <1500>; - scan-period = <0x4>; - io-channels = <&adc0 3>; -}; diff --git a/boards/ite/it515xx_evb/it515xx_evb.yaml b/boards/ite/it515xx_evb/it515xx_evb.yaml deleted file mode 100644 index 5ac8ab272d7e..000000000000 --- a/boards/ite/it515xx_evb/it515xx_evb.yaml +++ /dev/null @@ -1,15 +0,0 @@ -identifier: it515xx_evb -name: ITE IT51XXX EVB -type: mcu -arch: riscv -toolchain: - - zephyr -ram: 128 -supported: - - flash - - gpio - - i2c - - pinctrl - - pm - - uart -vendor: ite diff --git a/boards/ite/it51xxx_evb/Kconfig.defconfig b/boards/ite/it51xxx_evb/Kconfig.defconfig new file mode 100644 index 000000000000..4f3ad984ebaa --- /dev/null +++ b/boards/ite/it51xxx_evb/Kconfig.defconfig @@ -0,0 +1,17 @@ +# Copyright (c) 2025 ITE Corporation. All Rights Reserved. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_IT51XXX_EVB + +if PM + +config PM_DEVICE + default y + +choice PM_POLICY + default PM_POLICY_CUSTOM +endchoice + +endif # PM + +endif # BOARD_IT51XXX_EVB diff --git a/boards/ite/it51xxx_evb/Kconfig.it51xxx_evb b/boards/ite/it51xxx_evb/Kconfig.it51xxx_evb new file mode 100644 index 000000000000..41719913887f --- /dev/null +++ b/boards/ite/it51xxx_evb/Kconfig.it51xxx_evb @@ -0,0 +1,5 @@ +# Copyright (c) 2025 ITE Corporation. All Rights Reserved. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_IT51XXX_EVB + select SOC_IT51526AW if BOARD_IT51XXX_EVB_IT51526AW diff --git a/boards/ite/it51xxx_evb/board.yml b/boards/ite/it51xxx_evb/board.yml new file mode 100644 index 000000000000..1c9edb2edf70 --- /dev/null +++ b/boards/ite/it51xxx_evb/board.yml @@ -0,0 +1,6 @@ +board: + name: it51xxx_evb + full_name: IT51XXX series + vendor: ite + socs: + - name: it51526aw diff --git a/boards/ite/it51xxx_evb/doc/index.rst b/boards/ite/it51xxx_evb/doc/index.rst new file mode 100644 index 000000000000..a0fdff39bcf3 --- /dev/null +++ b/boards/ite/it51xxx_evb/doc/index.rst @@ -0,0 +1,165 @@ +.. zephyr:board:: it51xxx_evb + +Overview +******** + +The IT51XXX is a 32-bit RISC-V microcontroller. +And a highly integrated embedded controller with system functions. +It is suitable for mobile system applications. The picture below is +the IT51526 development board (also known as it51xxx_evb/it51526aw) +and its debug card. + +.. figure:: it51xxx_evb_and_debug_card.webp + :align: center + :alt: IT51526 EVB + +To find out more about ITE, visit our World Wide Web at:`ITE's website`_ + +Hardware +******** +The IT51XXX series contains different chip types(ex, it51526, it51527), +and they support different hardware features. +Listing the IT51526 hardware features as following: + +- RISC-V RV32IMC instruction set +- 4KB instruction cache size +- 128KB SRAM in total +- Built-in 32.768 kHz clock generator +- Embedded Flash, 512K/1024K-byte e-flash +- eSPI, SPI, BRAM, KBC, PECI, UART +- GPIO, PWM, ADC, INTC, WUC, Timer, Watchdog, KB scan, JTAG +- Support 3 Voltage Comparator +- Support Cryptographic Engine +- 9 SMBus hosts, 3 targets, with 12 SMBus channels, compatible with I2C +- I3C host: Support two I3C controllers, compliant with the MIPI I3C v1.0 SEPC. +- Two-wire serial interface up to 12.5MHz using Push-Pull. +- Support SDR, IBI, Hot-Join. +- I3C target: Support SDR, FIFO co-use DLM. Support Push-Pull output. + + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Programming and debugging on it51526 +************************************ + +In order to upload the application to the device, +you'll need our flash tool and Download board. +You can get them at: `ITE's website`_. + +Wiring +======= +#. Connect the Download Board to your host computer using the USB cable. + +#. Connect the it51xxx_evb to the evolution motherboard. + +#. Connect the Download Board J5 to J38(GPC1 & GPC2) on the evolution motherboard. + +#. Connect the USB to UART wire to UART0 connector on the evolution motherboard. + + .. image:: it51xxx_evb_wiring.webp + :align: center + :alt: it51xxx_evb wiring + + .. note:: Be careful during connection! + Use separate wires to connect I2C pins with pins on the it51xxx_evb board. + Wiring connection is described in the table below. + + +-------------+---------------+ + | J5 | it51xxx_evb | + | Connector | J38 Connector | + +=============+===============+ + | 2 | C1 | + +-------------+---------------+ + | 3 | C2 | + +-------------+---------------+ + | 4 | GND | + +-------------+---------------+ + + For USB to UART cable, connect the evolution motherboard as below: + + +-------------+---------------+ + | USB to UART | Evolution | + | cable | motherboard | + | | UART0 | + | | Connector | + +=============+===============+ + | USB | UART0 | + +-------------+---------------+ + +Building +======== + +#. Build :zephyr:code-sample:`hello_world` application as you would normally do + (see :`Zephyr Getting Started Guide`_):. + + .. zephyr-app-commands:: + :board: it51xxx_evb/it51526aw + :zephyr-app: samples/hello_world + :goals: build + +#. The file :file:`zephyr.bin` will be created by west. + +Flashing +======== + +Windows +-------- + +Use the winflash tool to program a zephyr application +to the it51xxx/it51526aw board flash. + +#. Flashing steps as described in the link: `Flashing steps`_. + +#. Turn on the it51xxx_evb/it51526aw board switch, you should see + ``"Hello World! it51xxx_evb/it51526aw"`` sent by the board. + If you don't see this message, press the Reset button and the + message should appear. + +Ubuntu +-------- + +#. Run your favorite terminal program to listen for output. + Under Linux the terminal should be :code:`/dev/ttyUSB0`. Do not close it. + + For example: + + .. code-block:: console + + $ minicom -D /dev/ttyUSB0 -b 115200 + +#. Open a second terminal window and use the Linux flash tool to flash your board. + + .. code-block:: console + + $ sudo ~/itetool/ite -f build/zephyr/zephyr.bin + + .. note:: The source code of ITE tool can be downloaded here: + https://www.ite.com.tw/upload/2024_01_23/6_20240123162336wu55j1Rjm4.bz2 + +#. Split first and second terminal windows to view both of them. + You should see ``"Hello World! it51xxx_evb/it51526aw"`` in the first terminal window. + If you don't see this message, press the Reset button and the message should appear. + +Debugging +========= + +it51xxx_evb board can be debugged by connecting USB to UART. We can write commands and +read messages through minicom in the Ubuntu terminal. + +Troubleshooting +=============== + +#. If the flash tool reports a failure, re-plug the 8390 Download board or + power cycle the it51xxx_evb board and try again. + +References +========== + +.. target-notes:: + +.. _ITE's website: https://www.ite.com.tw/en +.. _Zephyr Getting Started Guide: https://docs.zephyrproject.org/latest/getting_started/index.html +.. _Flashing steps: https://docs.zephyrproject.org/latest/boards/ite/it82xx2_evb/doc/index.html#flashing diff --git a/boards/ite/it515xx_evb/doc/it515xx_evb_and_debug_card.webp b/boards/ite/it51xxx_evb/doc/it51xxx_evb_and_debug_card.webp similarity index 100% rename from boards/ite/it515xx_evb/doc/it515xx_evb_and_debug_card.webp rename to boards/ite/it51xxx_evb/doc/it51xxx_evb_and_debug_card.webp diff --git a/boards/ite/it515xx_evb/doc/it515xx_evb_wiring.webp b/boards/ite/it51xxx_evb/doc/it51xxx_evb_wiring.webp similarity index 100% rename from boards/ite/it515xx_evb/doc/it515xx_evb_wiring.webp rename to boards/ite/it51xxx_evb/doc/it51xxx_evb_wiring.webp diff --git a/boards/ite/it51xxx_evb/it51xxx_evb_it51526aw.dts b/boards/ite/it51xxx_evb/it51xxx_evb_it51526aw.dts new file mode 100644 index 000000000000..e3495cdc9da2 --- /dev/null +++ b/boards/ite/it51xxx_evb/it51xxx_evb_it51526aw.dts @@ -0,0 +1,139 @@ +/* + * Copyright (c) 2025 ITE Corporation. All Rights Reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include + +/ { + model = "IT51XXX EV-Board"; + compatible = "ite,it51xxx-evb"; + + aliases { + i2c-0 = &i2c0; + led0 = &led0; + watchdog0 = &twd0; + pwm-0 = &pwm0; + }; + + chosen { + zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,flash-controller = &flashctrl; + }; + + leds { + compatible = "gpio-leds"; + + led0: led_0 { + gpios = <&gpioc 0 GPIO_ACTIVE_HIGH>; + label = "Green LED"; + }; + }; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c0_clk_gpf2_default + &i2c0_data_gpf3_default>; + pinctrl-names = "default"; +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; + clock-frequency = <1843200>; + pinctrl-0 = <&uart1_rx_gpc7_default + &uart1_tx_gpe6_default>; + pinctrl-names = "default"; +}; + +&ite_uart1_wrapper { + status = "okay"; +}; + +&kbd { + status = "okay"; + pinctrl-0 = <&ksi0_default + &ksi1_default + &ksi2_default + &ksi3_default + &ksi4_default + &ksi5_default + &ksi6_default + &ksi7_default + &kso0_default + &kso1_default + &kso2_default + &kso3_default + &kso4_default + &kso5_default + &kso6_default + &kso7_default + &kso8_default + &kso9_default + &kso10_default + &kso11_default + &kso12_default + &kso13_default + &kso14_default + &kso15_default>; + pinctrl-names = "default"; + row-size = <8>; + col-size = <16>; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_ch3_gpi3_default>; + pinctrl-names = "default"; +}; + +/* + * test pwm: + * If we need pwm output in ITE chip power saving mode, + * then we should set pwm output frequency <=324Hz. + */ +&pwm0 { + status = "okay"; + prescaler-cx = ; + pinctrl-0 = <&pwm0_gpa0_default>; + pinctrl-names = "default"; +}; + +/* test fan */ +&pwm7 { + status = "okay"; + prescaler-cx = ; + pinctrl-0 = <&pwm7_gpa7_default>; + pinctrl-names = "default"; +}; + +/* test fan tachometer sensor */ +&tach0 { + status = "okay"; + input-pin = ; + pulses-per-round = <2>; + pinctrl-0 = <&tach0a_gpd6_default>; + pinctrl-names = "default"; +}; + +&sha256 { + status = "okay"; +}; + +/* voltage comparator for test */ +&vcmp1 { + status = "okay"; + threshold-mv = <1500>; + scan-period = <0x4>; + io-channels = <&adc0 3>; +}; diff --git a/boards/ite/it51xxx_evb/it51xxx_evb_it51526aw.yaml b/boards/ite/it51xxx_evb/it51xxx_evb_it51526aw.yaml new file mode 100644 index 000000000000..a9c13ede0047 --- /dev/null +++ b/boards/ite/it51xxx_evb/it51xxx_evb_it51526aw.yaml @@ -0,0 +1,15 @@ +identifier: it51xxx_evb/it51526aw +name: ITE-IT51XXX-EVB-IT51526AW +type: mcu +arch: riscv +toolchain: + - zephyr +ram: 128 +supported: + - flash + - gpio + - i2c + - pinctrl + - pm + - uart +vendor: ite diff --git a/boards/ite/it515xx_evb/it515xx_evb_defconfig b/boards/ite/it51xxx_evb/it51xxx_evb_it51526aw_defconfig similarity index 100% rename from boards/ite/it515xx_evb/it515xx_evb_defconfig rename to boards/ite/it51xxx_evb/it51xxx_evb_it51526aw_defconfig diff --git a/boards/kincony/kincony_kc868_a32/support/openocd.cfg b/boards/kincony/kincony_kc868_a32/support/openocd.cfg index 338e6e4e6eae..41411e37140e 100644 --- a/boards/kincony/kincony_kc868_a32/support/openocd.cfg +++ b/boards/kincony/kincony_kc868_a32/support/openocd.cfg @@ -1,5 +1,5 @@ -set ESP_RTOS none -set ESP32_ONLYCPU 1 +set ESP_RTOS Zephyr +set ESP_ONLYCPU 1 source [find interface/ftdi/esp32_devkitj_v1.cfg] source [find target/esp32.cfg] diff --git a/boards/kws/pico2_spe/pico2_spe.dtsi b/boards/kws/pico2_spe/pico2_spe.dtsi index f99ec6f98aa7..b4f3db7021e9 100644 --- a/boards/kws/pico2_spe/pico2_spe.dtsi +++ b/boards/kws/pico2_spe/pico2_spe.dtsi @@ -86,7 +86,7 @@ rst-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; status = "okay"; - local-mac-address = [CA 2F B7 10 23 79]; + local-mac-address = [ca 2f b7 10 23 79]; lan865x_mdio: lan865x_mdio { compatible = "microchip,lan865x-mdio"; diff --git a/boards/kws/pico_spe/pico_spe.dts b/boards/kws/pico_spe/pico_spe.dts index 1b333f69e9fe..048c18ea6276 100644 --- a/boards/kws/pico_spe/pico_spe.dts +++ b/boards/kws/pico_spe/pico_spe.dts @@ -150,7 +150,7 @@ int-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; rst-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; status = "okay"; - local-mac-address = [CA 2F B7 10 23 78]; + local-mac-address = [ca 2f b7 10 23 78]; lan865x_mdio: lan865x_mdio { compatible = "microchip,lan865x-mdio"; diff --git a/boards/lilygo/tdongle_s3/support/openocd.cfg b/boards/lilygo/tdongle_s3/support/openocd.cfg index 0b2c4909fe0e..dc401fe1b974 100644 --- a/boards/lilygo/tdongle_s3/support/openocd.cfg +++ b/boards/lilygo/tdongle_s3/support/openocd.cfg @@ -1,5 +1,5 @@ -set ESP_RTOS none -set ESP32_ONLYCPU 1 +set ESP_RTOS Zephyr +set ESP_ONLYCPU 1 source [find interface/esp_usb_jtag.cfg] diff --git a/boards/lilygo/tdongle_s3/tdongle_s3_procpu.dts b/boards/lilygo/tdongle_s3/tdongle_s3_procpu.dts index 542781c515cf..f2afc45fef85 100644 --- a/boards/lilygo/tdongle_s3/tdongle_s3_procpu.dts +++ b/boards/lilygo/tdongle_s3/tdongle_s3_procpu.dts @@ -70,16 +70,16 @@ height = <80>; inversion-on; rgb-is-inverted; - madctl = <0xBE>; + madctl = <0xbe>; x-offset = <1>; y-offset = <26>; - gamctrp1 = [02 1c 07 12 37 32 29 2d 29 25 2B 39 00 01 03 10]; - gamctrn1 = [03 1d 07 06 2E 2C 29 2D 2E 2E 37 3F 00 00 02 10]; - te-delay = <0x0A>; - vmctr1 = <0x0E>; + gamctrp1 = [02 1c 07 12 37 32 29 2d 29 25 2b 39 00 01 03 10]; + gamctrn1 = [03 1d 07 06 2e 2c 29 2d 2e 2e 37 3f 00 00 02 10]; + te-delay = <0x0a>; + vmctr1 = <0x0e>; colmod = <0x05>; caset = [00 02 00 81]; - raset = [00 01 00 A0]; + raset = [00 01 00 a0]; status = "okay"; }; }; diff --git a/boards/lilygo/ttgo_lora32/support/openocd.cfg b/boards/lilygo/ttgo_lora32/support/openocd.cfg index 338e6e4e6eae..41411e37140e 100644 --- a/boards/lilygo/ttgo_lora32/support/openocd.cfg +++ b/boards/lilygo/ttgo_lora32/support/openocd.cfg @@ -1,5 +1,5 @@ -set ESP_RTOS none -set ESP32_ONLYCPU 1 +set ESP_RTOS Zephyr +set ESP_ONLYCPU 1 source [find interface/ftdi/esp32_devkitj_v1.cfg] source [find target/esp32.cfg] diff --git a/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_procpu.dts b/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_procpu.dts index aaed6346e114..5dfd627b7fbb 100644 --- a/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_procpu.dts +++ b/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_procpu.dts @@ -68,7 +68,7 @@ pinctrl-names = "default"; ssd1306_128x64: ssd1306@3c { - compatible = "solomon,ssd1306fb"; + compatible = "solomon,ssd1306"; reg = <0x3c>; width = <128>; height = <64>; diff --git a/boards/lilygo/ttgo_t7v1_5/support/openocd.cfg b/boards/lilygo/ttgo_t7v1_5/support/openocd.cfg index 756e960dd203..2d704722bbc7 100644 --- a/boards/lilygo/ttgo_t7v1_5/support/openocd.cfg +++ b/boards/lilygo/ttgo_t7v1_5/support/openocd.cfg @@ -1,4 +1,5 @@ -set ESP_RTOS none +set ESP_RTOS Zephyr +set ESP_ONLYCPU 1 source [find interface/esp_usb_jtag.cfg] diff --git a/boards/lilygo/ttgo_t8c3/support/openocd.cfg b/boards/lilygo/ttgo_t8c3/support/openocd.cfg index 02754ff2a73c..e896e7e7f8db 100644 --- a/boards/lilygo/ttgo_t8c3/support/openocd.cfg +++ b/boards/lilygo/ttgo_t8c3/support/openocd.cfg @@ -1,4 +1,4 @@ -set ESP_RTOS none +set ESP_RTOS Zephyr source [find interface/esp_usb_jtag.cfg] diff --git a/boards/lilygo/ttgo_t8s3/support/openocd.cfg b/boards/lilygo/ttgo_t8s3/support/openocd.cfg index 0b2c4909fe0e..dc401fe1b974 100644 --- a/boards/lilygo/ttgo_t8s3/support/openocd.cfg +++ b/boards/lilygo/ttgo_t8s3/support/openocd.cfg @@ -1,5 +1,5 @@ -set ESP_RTOS none -set ESP32_ONLYCPU 1 +set ESP_RTOS Zephyr +set ESP_ONLYCPU 1 source [find interface/esp_usb_jtag.cfg] diff --git a/boards/lilygo/ttgo_tbeam/support/openocd.cfg b/boards/lilygo/ttgo_tbeam/support/openocd.cfg index 338e6e4e6eae..41411e37140e 100644 --- a/boards/lilygo/ttgo_tbeam/support/openocd.cfg +++ b/boards/lilygo/ttgo_tbeam/support/openocd.cfg @@ -1,5 +1,5 @@ -set ESP_RTOS none -set ESP32_ONLYCPU 1 +set ESP_RTOS Zephyr +set ESP_ONLYCPU 1 source [find interface/ftdi/esp32_devkitj_v1.cfg] source [find target/esp32.cfg] diff --git a/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_procpu.dts b/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_procpu.dts index fc524286776e..f0a924bae389 100644 --- a/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_procpu.dts +++ b/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_procpu.dts @@ -78,7 +78,7 @@ pinctrl-names = "default"; ssd1306_128x64: ssd1306@3c { - compatible = "solomon,ssd1306fb"; + compatible = "solomon,ssd1306"; reg = <0x3c>; width = <128>; height = <64>; diff --git a/boards/lilygo/ttgo_toiplus/support/openocd.cfg b/boards/lilygo/ttgo_toiplus/support/openocd.cfg index 02754ff2a73c..e896e7e7f8db 100644 --- a/boards/lilygo/ttgo_toiplus/support/openocd.cfg +++ b/boards/lilygo/ttgo_toiplus/support/openocd.cfg @@ -1,4 +1,4 @@ -set ESP_RTOS none +set ESP_RTOS Zephyr source [find interface/esp_usb_jtag.cfg] diff --git a/boards/lilygo/twatch_s3/Kconfig.defconfig b/boards/lilygo/twatch_s3/Kconfig.defconfig index f7e4f32af392..c8b14cc5e4e2 100644 --- a/boards/lilygo/twatch_s3/Kconfig.defconfig +++ b/boards/lilygo/twatch_s3/Kconfig.defconfig @@ -4,7 +4,7 @@ if DISPLAY choice ST7789V_PIXEL_FORMAT - default ST7789V_BGR565 + default ST7789V_RGB565X endchoice if LVGL diff --git a/boards/lilygo/twatch_s3/support/openocd.cfg b/boards/lilygo/twatch_s3/support/openocd.cfg index 0b2c4909fe0e..dc401fe1b974 100644 --- a/boards/lilygo/twatch_s3/support/openocd.cfg +++ b/boards/lilygo/twatch_s3/support/openocd.cfg @@ -1,5 +1,5 @@ -set ESP_RTOS none -set ESP32_ONLYCPU 1 +set ESP_RTOS Zephyr +set ESP_ONLYCPU 1 source [find interface/esp_usb_jtag.cfg] diff --git a/boards/longan/canbed_rp2040/Kconfig b/boards/longan/canbed_rp2040/Kconfig new file mode 100644 index 000000000000..7db1ea7cad5b --- /dev/null +++ b/boards/longan/canbed_rp2040/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2026 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_CANBED_RP2040 + select RP2_FLASH_W25Q080 diff --git a/boards/longan/canbed_rp2040/Kconfig.canbed_rp2040 b/boards/longan/canbed_rp2040/Kconfig.canbed_rp2040 new file mode 100644 index 000000000000..32f65253dcb5 --- /dev/null +++ b/boards/longan/canbed_rp2040/Kconfig.canbed_rp2040 @@ -0,0 +1,5 @@ +# Copyright (c) 2026 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_CANBED_RP2040 + select SOC_RP2040 diff --git a/boards/longan/canbed_rp2040/Kconfig.defconfig b/boards/longan/canbed_rp2040/Kconfig.defconfig new file mode 100644 index 000000000000..eb01bfdbc5d4 --- /dev/null +++ b/boards/longan/canbed_rp2040/Kconfig.defconfig @@ -0,0 +1,16 @@ +# Copyright (c) 2022 Peter Johanson +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_CANBED_RP2040 + +if I2C_DW + +config I2C_DW_CLOCK_SPEED + default 125 + +endif # I2C_DW + +config USB_SELF_POWERED + default n + +endif # BOARD_CANBED_RP2040 diff --git a/boards/longan/canbed_rp2040/board.cmake b/boards/longan/canbed_rp2040/board.cmake new file mode 100644 index 000000000000..5a702fc5e030 --- /dev/null +++ b/boards/longan/canbed_rp2040/board.cmake @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: Apache-2.0 +# Adapted from boards/raspberrypi/rpi_pico/board.cmake + +# This configuration allows selecting what debug adapter debugging rpi_pico +# by a command-line argument. +# It is mainly intended to support both the 'picoprobe' and 'raspberrypi-swd' +# adapter described in "Getting started with Raspberry Pi Pico". +# And any other SWD debug adapter might also be usable with this configuration. + +# Set RPI_PICO_DEBUG_ADAPTER to select debug adapter by command-line arguments. +# e.g.) west build -b rpi_pico -- -DRPI_PICO_DEBUG_ADAPTER=raspberrypi-swd +# The value is treated as a part of an interface file name that +# the debugger's configuration file. +# The value must be the 'stem' part of the name of one of the files +# in the openocd interface configuration file. +# The setting is store to CMakeCache.txt. +if("${RPI_PICO_DEBUG_ADAPTER}" STREQUAL "") + set(RPI_PICO_DEBUG_ADAPTER "cmsis-dap") +endif() + +board_runner_args(openocd --cmd-pre-init "source [find interface/${RPI_PICO_DEBUG_ADAPTER}.cfg]") +board_runner_args(openocd --cmd-pre-init "transport select swd") +board_runner_args(openocd --cmd-pre-init "source [find target/rp2040.cfg]") + +# The adapter speed is expected to be set by interface configuration. +# But if not so, set 2000 to adapter speed. +board_runner_args(openocd --cmd-pre-init "set_adapter_speed_if_not_set 2000") + +board_runner_args(jlink "--device=RP2040_M0_0") +board_runner_args(uf2 "--board-id=RPI-RP2") +board_runner_args(pyocd "--target=rp2040") + +# Default runner should be listed first +include(${ZEPHYR_BASE}/boards/common/uf2.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/blackmagicprobe.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/longan/canbed_rp2040/board.yml b/boards/longan/canbed_rp2040/board.yml new file mode 100644 index 000000000000..39fbbffeae26 --- /dev/null +++ b/boards/longan/canbed_rp2040/board.yml @@ -0,0 +1,6 @@ +board: + name: canbed_rp2040 + full_name: CANBed RP2040 + vendor: longan + socs: + - name: rp2040 diff --git a/boards/longan/canbed_rp2040/canbed_rp2040-pinctrl.dtsi b/boards/longan/canbed_rp2040/canbed_rp2040-pinctrl.dtsi new file mode 100644 index 000000000000..ef7f3fe06f53 --- /dev/null +++ b/boards/longan/canbed_rp2040/canbed_rp2040-pinctrl.dtsi @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2026 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + uart0_default: uart0_default { + group1 { + pinmux = ; + }; + + group2 { + pinmux = ; + input-enable; + }; + }; + + i2c1_default: i2c1_default { + group1 { + pinmux = , ; + input-enable; + }; + }; + + spi0_default: spi0_default { + group1 { + pinmux = , ; + }; + + group2 { + pinmux = ; + input-enable; + }; + }; + + adc_default: adc_default { + group1 { + pinmux = , , , ; + input-enable; + }; + }; +}; diff --git a/boards/longan/canbed_rp2040/canbed_rp2040.dts b/boards/longan/canbed_rp2040/canbed_rp2040.dts new file mode 100644 index 000000000000..1bbd74d9689f --- /dev/null +++ b/boards/longan/canbed_rp2040/canbed_rp2040.dts @@ -0,0 +1,188 @@ +/* + * Copyright (c) 2021 Yonatan Schachter + * Copyright (c) 2022 Peter Johanson + * Copyright (c) 2026 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include "canbed_rp2040-pinctrl.dtsi" + +/ { + model = "Longan Labs CANBed RP2040"; + compatible = "longan,canbed_rp2040"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,flash-controller = &ssi; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,code-partition = &code_partition; + zephyr,canbus = &mcp2515; + }; + + aliases { + watchdog0 = &wdt0; + led0 = &blue_led; + }; + + zephyr,user { + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>; + }; + + leds: leds { + compatible = "gpio-leds"; + + blue_led: blue_led { + gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; + label = "Blue LED"; + }; + }; + + stemma_connector: stemma_connector { + compatible = "stemma-qt-connector"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 7 0>, /* SCL */ + <1 0 &gpio0 6 0>; /* SDA */ + }; +}; + +&flash0 { + reg = <0x10000000 DT_SIZE_M(2)>; + ranges = <0x0 0x10000000 DT_SIZE_M(2)>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* Reserved memory for the second stage bootloader */ + second_stage_bootloader: partition@0 { + label = "second_stage_bootloader"; + reg = <0x00000000 0x100>; + read-only; + }; + + /* + * Usable flash. Starts at 0x100, after the bootloader. The partition + * size is 2 MB minus the 0x100 bytes taken by the bootloader. + */ + code_partition: partition@100 { + label = "code-partition"; + reg = <0x100 (DT_SIZE_M(2) - 0x100)>; + read-only; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&uart0 { + current-speed = <115200>; + status = "okay"; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +zephyr_i2c: &i2c1 { + status = "okay"; + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; + clock-frequency = ; +}; + +&spi0 { + pinctrl-0 = <&spi0_default>; + pinctrl-names = "default"; + status = "okay"; + cs-gpios = <&gpio0 9 GPIO_ACTIVE_LOW>; + + mcp2515: mcp2515@0 { + compatible = "microchip,mcp2515"; + spi-max-frequency = <1000000>; + int-gpios = <&gpio0 11 GPIO_ACTIVE_LOW>; + status = "okay"; + reg = <0x0>; + osc-freq = <16000000>; + + can-transceiver { + max-bitrate = <1000000>; + }; + }; +}; + +&timer { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&adc { + status = "okay"; + pinctrl-0 = <&adc_default>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; + + channel@1 { + reg = <1>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; + + channel@2 { + reg = <2>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; + + channel@3 { + reg = <3>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; +}; + +zephyr_udc0: &usbd { + status = "okay"; +}; + +&die_temp { + status = "okay"; +}; + +&vreg { + regulator-always-on; + regulator-allowed-modes = ; +}; + +&xosc { + startup-delay-multiplier = <64>; +}; diff --git a/boards/longan/canbed_rp2040/canbed_rp2040.yaml b/boards/longan/canbed_rp2040/canbed_rp2040.yaml new file mode 100644 index 000000000000..88388dfcb7f2 --- /dev/null +++ b/boards/longan/canbed_rp2040/canbed_rp2040.yaml @@ -0,0 +1,23 @@ +identifier: canbed_rp2040 +name: Longan Labs CANBed RP2040 +type: mcu +arch: arm +flash: 2048 +ram: 264 +toolchain: + - zephyr + - gnuarmemb +supported: + - adc + - can + - clock + - counter + - dma + - flash + - gpio + - hwinfo + - i2c + - pwm + - spi + - uart + - watchdog diff --git a/boards/longan/canbed_rp2040/canbed_rp2040_defconfig b/boards/longan/canbed_rp2040/canbed_rp2040_defconfig new file mode 100644 index 000000000000..85b60ee95c5a --- /dev/null +++ b/boards/longan/canbed_rp2040/canbed_rp2040_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2026 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_OUTPUT_UF2=y +CONFIG_CLOCK_CONTROL=y +CONFIG_CONSOLE=y +CONFIG_GPIO=y +CONFIG_RESET=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/longan/canbed_rp2040/doc/img/canbed_rp2040.webp b/boards/longan/canbed_rp2040/doc/img/canbed_rp2040.webp new file mode 100644 index 000000000000..2acc3dd0828f Binary files /dev/null and b/boards/longan/canbed_rp2040/doc/img/canbed_rp2040.webp differ diff --git a/boards/longan/canbed_rp2040/doc/index.rst b/boards/longan/canbed_rp2040/doc/index.rst new file mode 100644 index 000000000000..ae984a2d5fa4 --- /dev/null +++ b/boards/longan/canbed_rp2040/doc/index.rst @@ -0,0 +1,204 @@ +.. zephyr:board:: canbed_rp2040 + +Overview +******** + +The `Longan Labs CANBed RP2040`_ board is based on the RP2040 microcontroller from Raspberry Pi Ltd. +The board has a CAN bus controller and an I2C connector for easy sensor usage. +It has a micro USB connector. + + +Hardware +******** + +- Microcontroller Raspberry Pi RP2040, with a max frequency of 133 MHz +- Dual ARM Cortex M0+ cores +- 264 kByte SRAM +- 2 Mbyte QSPI flash +- 13 GPIO pins +- 4 ADC pins +- I2C +- SPI +- UART +- Micro USB connector +- Reset and boot buttons +- Blue user LED +- Grove I2C connector, compatible with Qwiic/Stemma QT if using adapter cable +- Grove UART connector +- CAN bus controller MCP2515 +- CAN bus transceiver SN65HVD230 + + +Default Zephyr Peripheral Mapping +================================= + ++-------+--------+-----------------+ +| Label | Pin | Default pin mux | ++=======+========+=================+ +| LED | GPIO18 | | ++-------+--------+-----------------+ + + +Main header (sorted according to schematic pin numbering): + ++-------+--------+-----------------+-------------------+ +| Label | Pin | Default pin mux | Also in connector | ++=======+========+=================+===================+ +| GND | | | | ++-------+--------+-----------------+-------------------+ +| 24 | GPIO24 | | | ++-------+--------+-----------------+-------------------+ +| 23 | GPIO23 | | | ++-------+--------+-----------------+-------------------+ +| 22 | GPIO22 | | | ++-------+--------+-----------------+-------------------+ +| 21 | GPIO21 | | | ++-------+--------+-----------------+-------------------+ +| SCL | GPIO7 | I2C1 SCL | I2C connector | ++-------+--------+-----------------+-------------------+ +| SDA | GPIO6 | I2C1 SDA | I2C connector | ++-------+--------+-----------------+-------------------+ +| TX | GPIO0 | UART0 TX | UART connector | ++-------+--------+-----------------+-------------------+ +| RX | GPIO1 | UART0 RX | UART connector | ++-------+--------+-----------------+-------------------+ +| 10 | GPIO10 | | | ++-------+--------+-----------------+-------------------+ +| 19 | GPIO19 | | | ++-------+--------+-----------------+-------------------+ +| 20 | GPIO20 | | | ++-------+--------+-----------------+-------------------+ +| A3 | GPIO29 | ADC3 | | ++-------+--------+-----------------+-------------------+ +| 25 | GPIO25 | | | ++-------+--------+-----------------+-------------------+ +| A0 | GPIO26 | ADC0 | | ++-------+--------+-----------------+-------------------+ +| A1 | GPIO27 | ADC1 | | ++-------+--------+-----------------+-------------------+ +| A2 | GPIO28 | ADC2 | | ++-------+--------+-----------------+-------------------+ +| 3V3 | | | | ++-------+--------+-----------------+-------------------+ + + +Grove I2C connector (pins also available in the main header): + ++-------+--------+-----------------+ +| Label | Pin | Default pin mux | ++=======+========+=================+ +| SCL | GPIO7 | I2C1 SCL | ++-------+--------+-----------------+ +| SDA | GPIO6 | I2C1 SDA | ++-------+--------+-----------------+ +| 3V3 | | | ++-------+--------+-----------------+ +| GND | | | ++-------+--------+-----------------+ + + +Grove UART connector (pins also available in the main header): + ++-------+--------+-----------------+ +| Label | Pin | Default pin mux | ++=======+========+=================+ +| RX | GPIO1 | UART0 RX | ++-------+--------+-----------------+ +| TX | GPIO0 | UART0 TX | ++-------+--------+-----------------+ +| 3V3 | | | ++-------+--------+-----------------+ +| GND | | | ++-------+--------+-----------------+ + + +SPI header: + ++-------+--------+-----------------+ +| Label | Pin | Default pin mux | ++=======+========+=================+ +| MISO | GPIO4 | SPI0 MISO | ++-------+--------+-----------------+ +| SCK | GPIO2 | SPI0 SCK | ++-------+--------+-----------------+ +| 8 | GPIO8 | | ++-------+--------+-----------------+ +| GND | | | ++-------+--------+-----------------+ +| MOSI | GPIO3 | SPI0 MOSI | ++-------+--------+-----------------+ +| 3V3 | | | ++-------+--------+-----------------+ + + +CAN controller: + ++-------+--------+-----------------+ +| Label | Pin | Default pin mux | ++=======+========+=================+ +| CANCS | GPIO9 | | ++-------+--------+-----------------+ +| INT | GPIO11 | | ++-------+--------+-----------------+ + +The CAN controller is also connected to the SPI0 pins SCK, MOSI and MISO (see above). + +See also `pinout`_. + + +Supported Features +================== + +.. zephyr:board-supported-hw:: + + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +By default programming is done via the USB connector. Press and hold the BOOT button, and then +press the RST button, and the device will appear as a USB mass storage unit. +Building your application will result in a :file:`build/zephyr/zephyr.uf2` file. +Drag and drop the file to the USB mass storage unit, and the board will be reprogrammed. + +It is also possible to program and debug the board via the SWDIO and SWCLK pins. +Then a separate programming hardware tool is required, and for example the :command:`openocd` +software is used. Typically the ``OPENOCD`` and ``OPENOCD_DEFAULT_PATH`` values should be set +when building, and the ``--runner openocd`` argument should be used when flashing. +For more details on programming RP2040-based boards, see :ref:`rpi_pico_programming_and_debugging`. + + +Flashing +======== + +To run the :zephyr:code-sample:`blinky` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky/ + :board: canbed_rp2040 + :goals: build flash + +Try also the :zephyr:code-sample:`hello_world`, :zephyr:code-sample:`adc_dt` +and :zephyr:code-sample:`can-counter` samples. + +The use of the Grove/Qwiic/Stemma QT I2C connector is demonstrated using the +:zephyr:code-sample:`light_sensor_polling` sample and a separate shield: + +.. zephyr-app-commands:: + :zephyr-app: samples/sensor/light_polling + :board: canbed_rp2040 + :shield: adafruit_veml7700 + :goals: build flash + + +References +********** + +.. target-notes:: + +.. _Longan Labs CANBed RP2040: + https://docs.longan-labs.cc/1030018/ + +.. _pinout: + https://www.longan-labs.cc/media/wysiwyg/CAN-Bus/CANBed/Details_of_CANBed-04.png diff --git a/boards/longan/canbed_rp2040/support/openocd.cfg b/boards/longan/canbed_rp2040/support/openocd.cfg new file mode 100644 index 000000000000..34ab592b1861 --- /dev/null +++ b/boards/longan/canbed_rp2040/support/openocd.cfg @@ -0,0 +1,11 @@ +# Copyright (c) 2022 Tokita, Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +# Checking and set 'adapter speed'. +# Set the adaptor speed, if unset, and given as an argument. +proc set_adapter_speed_if_not_set { speed } { + puts "checking adapter speed..." + if { [catch {adapter speed} ret] } { + adapter speed $speed + } +} diff --git a/boards/longan/index.rst b/boards/longan/index.rst new file mode 100644 index 000000000000..926738b7bc78 --- /dev/null +++ b/boards/longan/index.rst @@ -0,0 +1,10 @@ +.. _boards-longan: + +Longan Labs +########### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/luatos/esp32c3_luatos_core/support/openocd.cfg b/boards/luatos/esp32c3_luatos_core/support/openocd.cfg index 12065b5e6304..c758eb8203e4 100644 --- a/boards/luatos/esp32c3_luatos_core/support/openocd.cfg +++ b/boards/luatos/esp32c3_luatos_core/support/openocd.cfg @@ -1,5 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -set ESP_RTOS none +set ESP_RTOS Zephyr # ESP32C3 has built-in JTAG interface over USB port in pins GPIO18/GPIO19 (D-/D+). # Uncomment the line below to enable USB debugging. diff --git a/boards/luatos/esp32s3_luatos_core/support/openocd.cfg b/boards/luatos/esp32s3_luatos_core/support/openocd.cfg index 2f740b4a36ab..b45e13c53d01 100644 --- a/boards/luatos/esp32s3_luatos_core/support/openocd.cfg +++ b/boards/luatos/esp32s3_luatos_core/support/openocd.cfg @@ -1,5 +1,5 @@ -set ESP_RTOS none -set ESP32_ONLYCPU 1 +set ESP_RTOS Zephyr +set ESP_ONLYCPU 1 # Source the JTAG interface configuration file source [find interface/esp_usb_jtag.cfg] diff --git a/boards/m5stack/m5stack_atoms3/m5stack_atoms3_procpu.dts b/boards/m5stack/m5stack_atoms3/m5stack_atoms3_procpu.dts index cbc697bcdf34..5d8684322f93 100644 --- a/boards/m5stack/m5stack_atoms3/m5stack_atoms3_procpu.dts +++ b/boards/m5stack/m5stack_atoms3/m5stack_atoms3_procpu.dts @@ -83,7 +83,7 @@ pwctrl1-param = [a4 a1]; pvgam-param = [d0 00 02 07 0a 28 32 44 42 06 0e 12 14 17]; nvgam-param = [d0 00 02 07 0a 28 31 54 47 0e 1c 17 1b 1e]; - ram-param = [00 E0]; + ram-param = [00 e0]; rgb-param = [40 02 14]; mipi-mode = "MIPI_DBI_MODE_SPI_4WIRE"; }; diff --git a/boards/m5stack/m5stack_core2/m5stack_core2_procpu.dts b/boards/m5stack/m5stack_core2/m5stack_core2_procpu.dts index 42ea3d033ec0..a6949838bbec 100644 --- a/boards/m5stack/m5stack_core2/m5stack_core2_procpu.dts +++ b/boards/m5stack/m5stack_core2/m5stack_core2_procpu.dts @@ -9,7 +9,7 @@ #include "m5stack_core2-pinctrl.dtsi" #include "grove_connectors.dtsi" #include "m5stack_mbus_connectors.dtsi" -#include +#include #include #include @@ -62,7 +62,7 @@ mipi-max-frequency = <30000000>; reg = <0>; vin-supply = <&lcd_bg>; - pixel-format = ; + pixel-format = ; display-inversion; width = <320>; height = <240>; diff --git a/boards/m5stack/m5stack_core2/support/openocd.cfg b/boards/m5stack/m5stack_core2/support/openocd.cfg index 338e6e4e6eae..41411e37140e 100644 --- a/boards/m5stack/m5stack_core2/support/openocd.cfg +++ b/boards/m5stack/m5stack_core2/support/openocd.cfg @@ -1,5 +1,5 @@ -set ESP_RTOS none -set ESP32_ONLYCPU 1 +set ESP_RTOS Zephyr +set ESP_ONLYCPU 1 source [find interface/ftdi/esp32_devkitj_v1.cfg] source [find target/esp32.cfg] diff --git a/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu.dts b/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu.dts index 6a1b43d1c6eb..8420e314cb04 100644 --- a/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu.dts +++ b/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu.dts @@ -15,6 +15,8 @@ aliases { accel0 = &bmi270; magn0 = &bmm150; + light-sensor = <r553; + prox-sensor0 = <r553; }; }; @@ -29,6 +31,12 @@ status = "okay"; reg = <0x10>; }; + + ltr553: ltr553@23 { + compatible = "liteon,ltr553"; + reg = <0x23>; + status = "okay"; + }; }; ®ulator { diff --git a/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu_common.dtsi b/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu_common.dtsi index 25ed72da9938..4c8042425889 100644 --- a/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu_common.dtsi +++ b/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu_common.dtsi @@ -6,7 +6,7 @@ #include #include -#include +#include #include "m5stack_cores3-pinctrl.dtsi" #include "m5stack_mbus_connectors.dtsi" #include "grove_connectors.dtsi" @@ -51,7 +51,7 @@ mipi-max-frequency = <30000000>; reg = <0>; vin-supply = <&vcc_bl>; - pixel-format = ; + pixel-format = ; display-inversion; width = <320>; height = <240>; diff --git a/boards/m5stack/m5stack_cores3/support/openocd.cfg b/boards/m5stack/m5stack_cores3/support/openocd.cfg index 2f740b4a36ab..b45e13c53d01 100644 --- a/boards/m5stack/m5stack_cores3/support/openocd.cfg +++ b/boards/m5stack/m5stack_cores3/support/openocd.cfg @@ -1,5 +1,5 @@ -set ESP_RTOS none -set ESP32_ONLYCPU 1 +set ESP_RTOS Zephyr +set ESP_ONLYCPU 1 # Source the JTAG interface configuration file source [find interface/esp_usb_jtag.cfg] diff --git a/boards/m5stack/m5stack_fire/grove_connectors.dtsi b/boards/m5stack/m5stack_fire/grove_connectors.dtsi index b9f7dd253e39..b5764977c7d8 100644 --- a/boards/m5stack/m5stack_fire/grove_connectors.dtsi +++ b/boards/m5stack/m5stack_fire/grove_connectors.dtsi @@ -35,4 +35,6 @@ }; }; +zephyr_i2c: &i2c0 {}; + grove_uart: &uart1 {}; diff --git a/boards/m5stack/m5stack_fire/m5stack_fire-pinctrl.dtsi b/boards/m5stack/m5stack_fire/m5stack_fire-pinctrl.dtsi index 56e8ad104d8d..a2b9937b61a1 100644 --- a/boards/m5stack/m5stack_fire/m5stack_fire-pinctrl.dtsi +++ b/boards/m5stack/m5stack_fire/m5stack_fire-pinctrl.dtsi @@ -20,20 +20,12 @@ bias-pull-up; }; - uart1_rx_gpio33: uart1_rx_gpio33 { - pinmux = ; + uart1_tx_gpio16: uart1_tx_gpio16 { + pinmux = ; }; - uart2_rx_gpio13: uart2_rx_gpio13 { - pinmux = ; - }; - - uart2_tx_gpio14: uart2_rx_gpio14 { - pinmux = ; - }; - - uart1_tx_gpio32: uart1_tx_gpio32 { - pinmux = ; + uart1_rx_gpio17: uart1_rx_gpio17 { + pinmux = ; }; spim3_default: spim3_default { diff --git a/boards/m5stack/m5stack_fire/m5stack_fire_procpu.dts b/boards/m5stack/m5stack_fire/m5stack_fire_procpu.dts index 9cc132a6963f..4ab712a34a9e 100644 --- a/boards/m5stack/m5stack_fire/m5stack_fire_procpu.dts +++ b/boards/m5stack/m5stack_fire/m5stack_fire_procpu.dts @@ -10,7 +10,7 @@ #include "m5stack_fire-pinctrl.dtsi" #include "grove_connectors.dtsi" #include "m5stack_mbus_connectors.dtsi" -#include +#include #include #include @@ -95,7 +95,7 @@ compatible = "ilitek,ili9342c"; mipi-max-frequency = <30000000>; reg = <0>; - pixel-format = ; + pixel-format = ; display-inversion; width = <320>; height = <240>; @@ -122,7 +122,7 @@ &uart1 { status = "disabled"; current-speed = <115200>; - pinctrl-0 = <&uart1_rx_gpio33 &uart1_tx_gpio32>; + pinctrl-0 = <&uart1_tx_gpio16 &uart1_rx_gpio17>; pinctrl-names = "default"; }; diff --git a/boards/m5stack/m5stack_fire/support/openocd.cfg b/boards/m5stack/m5stack_fire/support/openocd.cfg index 338e6e4e6eae..41411e37140e 100644 --- a/boards/m5stack/m5stack_fire/support/openocd.cfg +++ b/boards/m5stack/m5stack_fire/support/openocd.cfg @@ -1,5 +1,5 @@ -set ESP_RTOS none -set ESP32_ONLYCPU 1 +set ESP_RTOS Zephyr +set ESP_ONLYCPU 1 source [find interface/ftdi/esp32_devkitj_v1.cfg] source [find target/esp32.cfg] diff --git a/boards/m5stack/m5stack_nanoc6/board.yml b/boards/m5stack/m5stack_nanoc6/board.yml index 129d67eb2e16..53975a09f6ab 100644 --- a/boards/m5stack/m5stack_nanoc6/board.yml +++ b/boards/m5stack/m5stack_nanoc6/board.yml @@ -1,5 +1,6 @@ board: name: m5stack_nanoc6 + full_name: NanoC6 vendor: m5stack socs: - name: esp32c6 diff --git a/boards/m5stack/m5stack_nanoc6/support/openocd.cfg b/boards/m5stack/m5stack_nanoc6/support/openocd.cfg index d86a5517a4ca..29d5fac25c5a 100644 --- a/boards/m5stack/m5stack_nanoc6/support/openocd.cfg +++ b/boards/m5stack/m5stack_nanoc6/support/openocd.cfg @@ -1,4 +1,4 @@ # ESP32C6 has built-in JTAG interface over USB port in pins GPIO13/GPIO12 (D-/D+). -set ESP_RTOS none +set ESP_RTOS Zephyr source [find board/esp32c6-builtin.cfg] diff --git a/boards/m5stack/m5stickc_plus/m5stickc_plus_procpu.dts b/boards/m5stack/m5stickc_plus/m5stickc_plus_procpu.dts index e9c090eec51e..426cb6973a3c 100644 --- a/boards/m5stack/m5stickc_plus/m5stickc_plus_procpu.dts +++ b/boards/m5stack/m5stickc_plus/m5stickc_plus_procpu.dts @@ -95,7 +95,7 @@ pwctrl1-param = [a4 a1]; pvgam-param = [d0 00 02 07 0a 28 32 44 42 06 0e 12 14 17]; nvgam-param = [d0 00 02 07 0a 28 31 54 47 0e 1c 17 1b 1e]; - ram-param = [00 F0]; + ram-param = [00 f0]; rgb-param = [40 02 14]; mipi-mode = "MIPI_DBI_MODE_SPI_4WIRE"; }; diff --git a/boards/m5stack/m5stickc_plus/support/openocd.cfg b/boards/m5stack/m5stickc_plus/support/openocd.cfg index 338e6e4e6eae..41411e37140e 100644 --- a/boards/m5stack/m5stickc_plus/support/openocd.cfg +++ b/boards/m5stack/m5stickc_plus/support/openocd.cfg @@ -1,5 +1,5 @@ -set ESP_RTOS none -set ESP32_ONLYCPU 1 +set ESP_RTOS Zephyr +set ESP_ONLYCPU 1 source [find interface/ftdi/esp32_devkitj_v1.cfg] source [find target/esp32.cfg] diff --git a/boards/m5stack/stamp_c3/support/openocd.cfg b/boards/m5stack/stamp_c3/support/openocd.cfg index 92e47fabefb3..8890eee15b25 100644 --- a/boards/m5stack/stamp_c3/support/openocd.cfg +++ b/boards/m5stack/stamp_c3/support/openocd.cfg @@ -1,7 +1,7 @@ # Copyright (c) 2022 TOKITA Hiroshi # SPDX-License-Identifier: Apache-2.0 -set ESP_RTOS none +set ESP_RTOS Zephyr source [find interface/esp_usb_jtag.cfg] diff --git a/boards/madmachine/mm_feather/mm_feather.dts b/boards/madmachine/mm_feather/mm_feather.dts index f15d9bc08c78..8fc830c038ef 100644 --- a/boards/madmachine/mm_feather/mm_feather.dts +++ b/boards/madmachine/mm_feather/mm_feather.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "mm_feather-pinctrl.dtsi" / { diff --git a/boards/madmachine/mm_swiftio/mm_swiftio.dts b/boards/madmachine/mm_swiftio/mm_swiftio.dts index 87b43498c364..159f8f38ad8a 100644 --- a/boards/madmachine/mm_swiftio/mm_swiftio.dts +++ b/boards/madmachine/mm_swiftio/mm_swiftio.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "mm_swiftio-pinctrl.dtsi" / { diff --git a/boards/makerdiary/nrf52832_mdk/nrf52832_mdk.dts b/boards/makerdiary/nrf52832_mdk/nrf52832_mdk.dts index 9cc34be37cf5..6dd7f134a595 100644 --- a/boards/makerdiary/nrf52832_mdk/nrf52832_mdk.dts +++ b/boards/makerdiary/nrf52832_mdk/nrf52832_mdk.dts @@ -153,12 +153,12 @@ slot0_partition: partition@c000 { label = "image-0"; - reg = <0x0000C000 0x32000>; + reg = <0x0000c000 0x32000>; }; slot1_partition: partition@3e000 { label = "image-1"; - reg = <0x0003E000 0x32000>; + reg = <0x0003e000 0x32000>; }; scratch_partition: partition@70000 { diff --git a/boards/mediatek/mt8186/afe-mt8186.dts b/boards/mediatek/mt8186/afe-mt8186.dts deleted file mode 100644 index 7f789adc010a..000000000000 --- a/boards/mediatek/mt8186/afe-mt8186.dts +++ /dev/null @@ -1,54 +0,0 @@ -afe_dl1: afe_dl1 { - compatible = "mediatek,afe"; - afe-name = "DL1"; - dai-id = <0>; - downlink; - base = <0x11210050 0x11210054>; - cur = <0x11210058 0x1121005c>; - end = <0x11210060 0x11210064>; - fs = <0x1121004c 24 4>; - mono = <0x1121004c 8 1>; - enable = <0x11210010 4 1>; - hd = <0x1121004c 0 1>; -}; - -afe_dl2: afe_dl2 { - compatible = "mediatek,afe"; - afe-name = "DL2"; - dai-id = <1>; - downlink; - base = <0x1121006c 0x11210070>; - cur = <0x11210074 0x11210078>; - end = <0x1121007c 0x11210080>; - fs = <0x11210068 24 4>; - mono = <0x11210068 8 1>; - enable = <0x11210010 5 1>; - hd = <0x11210068 0 1>; -}; - -afe_ul1: afe_ul1 { - compatible = "mediatek,afe"; - afe-name = "UL1"; - dai-id = <2>; - base = <0x11210378 0x1121037c>; - cur = <0x11210380 0x11210384>; - end = <0x11210388 0x1121038c>; - fs = <0x11210374 24 4>; - mono = <0x11210374 8 1>; - quad-ch = <0x11210374 11 1>; - enable = <0x11210010 31 1>; - hd = <0x11210374 0 1>; -}; - -afe_ul2: afe_ul2 { - compatible = "mediatek,afe"; - afe-name = "UL2"; - dai-id = <3>; - base = <0x11210860 0x11210864>; - cur = <0x11210868 0x1121086c>; - end = <0x11210870 0x11210874>; - fs = <0x1121085c 24 4>; - mono = <0x1121085c 8 1>; - enable = <0x11210010 16 1>; - hd = <0x1121085c 0 1>; -}; diff --git a/boards/mediatek/mt8186/board.yml b/boards/mediatek/mt8186/board.yml index 04582e157f7c..5b8635c48d3b 100644 --- a/boards/mediatek/mt8186/board.yml +++ b/boards/mediatek/mt8186/board.yml @@ -1,5 +1,6 @@ boards: - name: mt8186 + full_name: MT8186 ADSP vendor: mediatek socs: - name: mt8186 diff --git a/boards/mediatek/mt8188/afe-mt8188.dts b/boards/mediatek/mt8188/afe-mt8188.dtsi similarity index 100% rename from boards/mediatek/mt8188/afe-mt8188.dts rename to boards/mediatek/mt8188/afe-mt8188.dtsi diff --git a/boards/mediatek/mt8188/board.yml b/boards/mediatek/mt8188/board.yml index f50e9227a82c..12c22abfd94d 100644 --- a/boards/mediatek/mt8188/board.yml +++ b/boards/mediatek/mt8188/board.yml @@ -1,5 +1,6 @@ boards: - name: mt8188 + full_name: MT8188 ADSP vendor: mediatek socs: - name: mt8188 diff --git a/boards/mediatek/mt8188/mt8188_adsp.dts b/boards/mediatek/mt8188/mt8188_adsp.dts index 22e98352f4cf..d6297860934b 100644 --- a/boards/mediatek/mt8188/mt8188_adsp.dts +++ b/boards/mediatek/mt8188/mt8188_adsp.dts @@ -83,7 +83,7 @@ }; /* Generated code for AFE devices */ - #include "afe-mt8188.dts" + #include "afe-mt8188.dtsi" }; /* soc */ chosen {}; diff --git a/boards/mediatek/mt8195/afe-mt8195.dts b/boards/mediatek/mt8195/afe-mt8195.dtsi similarity index 100% rename from boards/mediatek/mt8195/afe-mt8195.dts rename to boards/mediatek/mt8195/afe-mt8195.dtsi diff --git a/boards/mediatek/mt8195/mt8195_adsp.dts b/boards/mediatek/mt8195/mt8195_adsp.dts index 856d3591522f..eeea978b11a9 100644 --- a/boards/mediatek/mt8195/mt8195_adsp.dts +++ b/boards/mediatek/mt8195/mt8195_adsp.dts @@ -95,7 +95,7 @@ }; /* Generated code for AFE devices */ - #include "afe-mt8195.dts" + #include "afe-mt8195.dtsi" }; /* soc */ chosen {}; diff --git a/boards/mediatek/mt8196/afe-mt8196.dts b/boards/mediatek/mt8196/afe-mt8196.dtsi similarity index 100% rename from boards/mediatek/mt8196/afe-mt8196.dts rename to boards/mediatek/mt8196/afe-mt8196.dtsi diff --git a/boards/mediatek/mt8196/board.yml b/boards/mediatek/mt8196/board.yml index cf5a2e276992..761ae53eed26 100644 --- a/boards/mediatek/mt8196/board.yml +++ b/boards/mediatek/mt8196/board.yml @@ -1,5 +1,6 @@ boards: - name: mt8196 + full_name: MT8196 ADSP vendor: mediatek socs: - name: mt8196 diff --git a/boards/mediatek/mt8196/mt8196_adsp.dts b/boards/mediatek/mt8196/mt8196_adsp.dts index 394921933710..250db3ed7a1f 100644 --- a/boards/mediatek/mt8196/mt8196_adsp.dts +++ b/boards/mediatek/mt8196/mt8196_adsp.dts @@ -103,7 +103,7 @@ }; /* Generated code for AFE devices */ - #include "afe-mt8196.dts" + #include "afe-mt8196.dtsi" }; /* soc */ chosen {}; diff --git a/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885.dts b/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885.dts index bf8348982c9a..4dcebe41a69e 100644 --- a/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885.dts +++ b/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885.dts @@ -16,6 +16,7 @@ chosen { zephyr,sram = &sram0; zephyr,console = &uart1; + zephyr,shell-uart = &uart1; zephyr,flash = &flash0; }; diff --git a/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853.dts b/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853.dts index 25c11f98f5cf..ba11a01e3cdd 100644 --- a/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853.dts +++ b/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853.dts @@ -15,6 +15,7 @@ chosen { zephyr,sram = &sram0; zephyr,console = &uart2; + zephyr,shell-uart = &uart2; zephyr,flash = &flash0; }; diff --git a/boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906.dts b/boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906.dts index 9d87268b2a85..17bc7bd62069 100644 --- a/boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906.dts +++ b/boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906.dts @@ -17,6 +17,7 @@ zephyr,sram = &sram0; zephyr,flash = &flash0; zephyr,console = &uart1; + zephyr,shell-uart = &uart1; }; aliases { diff --git a/boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930.dts b/boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930.dts index 72b3e4f9069b..4acfe7026c8c 100644 --- a/boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930.dts +++ b/boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930.dts @@ -17,6 +17,7 @@ zephyr,sram = &sram0; zephyr,flash = &flash0; zephyr,console = &uart1; + zephyr,shell-uart = &uart1; }; aliases { diff --git a/boards/microchip/mec_assy6941/CMakeLists.txt b/boards/microchip/mec_assy6941/CMakeLists.txt index 84b859f1f176..6b7afa2916b8 100644 --- a/boards/microchip/mec_assy6941/CMakeLists.txt +++ b/boards/microchip/mec_assy6941/CMakeLists.txt @@ -8,6 +8,8 @@ if(CONFIG_SOC_SERIES_MEC174X) set(PART_PREFIX mec174x) elseif(CONFIG_SOC_SERIES_MEC175X) set(PART_PREFIX mec175x) +elseif(CONFIG_SOC_SERIES_MEC165XB) + set(PART_PREFIX mec165xb) else() message(NOTICE "Unknown SoC series! No SPI image will be generated") endif() diff --git a/boards/microchip/mec_assy6941/mec_assy6941_mec1653b_nsz.dts b/boards/microchip/mec_assy6941/mec_assy6941_mec1653b_nsz.dts index 44129cbf3b0c..b78a1a06bdcb 100644 --- a/boards/microchip/mec_assy6941/mec_assy6941_mec1653b_nsz.dts +++ b/boards/microchip/mec_assy6941/mec_assy6941_mec1653b_nsz.dts @@ -7,7 +7,7 @@ /dts-v1/; #include -#include +#include / { model = "Microchip MEC ASSY6941 MEC1753B-NSZ evaluation board"; @@ -17,7 +17,7 @@ zephyr,sram = &sram0; zephyr,flash = &flash0; zephyr,console = &uart1; - rtimer-busy-wait-timer = &timer5; + zephyr,shell-uart = &uart1; }; power-states { @@ -51,13 +51,8 @@ status = "okay"; }; -/* We chose 32-bit basic timer 5 for use by ktimer */ -&timer5 { - status = "okay"; -}; - &uart1 { - compatible = "microchip,mec5-uart"; + compatible = "microchip,xec-uart"; status = "okay"; clock-frequency = <1843200>; current-speed = <115200>; diff --git a/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qlj.dts b/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qlj.dts index 0b885f29dc0a..ce22011ec78a 100644 --- a/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qlj.dts +++ b/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qlj.dts @@ -7,7 +7,7 @@ /dts-v1/; #include -#include +#include / { model = "Microchip MEC ASSY6941 MEC1743-QLJ evaluation board"; @@ -17,6 +17,7 @@ zephyr,sram = &sram0; zephyr,flash = &flash0; zephyr,console = &uart1; + zephyr,shell-uart = &uart1; }; power-states { @@ -51,7 +52,7 @@ }; &uart1 { - compatible = "microchip,mec5-uart"; + compatible = "microchip,xec-uart"; status = "okay"; clock-frequency = <1843200>; current-speed = <115200>; diff --git a/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qsz.dts b/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qsz.dts index b395ec21bc40..e473c8eb7995 100644 --- a/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qsz.dts +++ b/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qsz.dts @@ -7,7 +7,7 @@ /dts-v1/; #include -#include +#include / { model = "Microchip MEC ASSY6941 MEC1743-QSZ evaluation board"; @@ -17,6 +17,7 @@ zephyr,sram = &sram0; zephyr,flash = &flash0; zephyr,console = &uart1; + zephyr,shell-uart = &uart1; }; power-states { @@ -51,7 +52,7 @@ }; &uart1 { - compatible = "microchip,mec5-uart"; + compatible = "microchip,xec-uart"; status = "okay"; clock-frequency = <1843200>; current-speed = <115200>; diff --git a/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qlj.dts b/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qlj.dts index 724088b2d482..b6ba7905eecb 100644 --- a/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qlj.dts +++ b/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qlj.dts @@ -7,7 +7,7 @@ /dts-v1/; #include -#include +#include / { model = "Microchip MEC ASSY6941 MEC1753-QLJ evaluation board"; @@ -17,6 +17,7 @@ zephyr,sram = &sram0; zephyr,flash = &flash0; zephyr,console = &uart1; + zephyr,shell-uart = &uart1; }; power-states { @@ -51,7 +52,7 @@ }; &uart1 { - compatible = "microchip,mec5-uart"; + compatible = "microchip,xec-uart"; status = "okay"; clock-frequency = <1843200>; current-speed = <115200>; diff --git a/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qsz.dts b/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qsz.dts index ae51d2028555..a4b2af338a2b 100644 --- a/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qsz.dts +++ b/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qsz.dts @@ -7,7 +7,7 @@ /dts-v1/; #include -#include +#include / { model = "Microchip MEC ASSY6941 MEC1753-QSZ evaluation board"; @@ -17,6 +17,7 @@ zephyr,sram = &sram0; zephyr,flash = &flash0; zephyr,console = &uart1; + zephyr,shell-uart = &uart1; }; power-states { @@ -51,7 +52,7 @@ }; &uart1 { - compatible = "microchip,mec5-uart"; + compatible = "microchip,xec-uart"; status = "okay"; clock-frequency = <1843200>; current-speed = <115200>; diff --git a/boards/microchip/mec_assy6941/support/mec165xb_spi_cfg.txt b/boards/microchip/mec_assy6941/support/mec165xb_spi_cfg.txt new file mode 100644 index 000000000000..3aa5732f9765 --- /dev/null +++ b/boards/microchip/mec_assy6941/support/mec165xb_spi_cfg.txt @@ -0,0 +1,93 @@ +; Copyright (c) 2026, Microchip Technology Inc. +; SPDX-License-Identifier: Apache-2.0 +; MEC165xB SPI Image Generator configuration file +[SPI] +SPISizeMegabits = 128 + +[DEVICE] +DeviceSel = B +TagAddr0 = 0 +TagAddr1 = 0 +; BoardID is used by a Boot-ROM feature named PlatformID. By default PlatformID +; is disabled. If PlatformID is enabled in OTP Boot-ROM will check the image +; BoardID value with an OTP PlatformID value. Load is aborted if the ID's do +; not match. +BoardID = 0x316 + +[IMAGE "0"] +ImageLocation = 0x2000 +SpiFreqMHz = 24 +SpiReadCommand = slow +SpiDriveStrength = 4 +SpiSlewFast = false +SpiSignalControl = 0x00 +IMG1BinFile = zephyr.bin +ImageRevision = 0 +FwOffset = 0 +IMG1LoadAddress = 0xC0000 +IMG1EntryAddress = 0 +UseECDSA = false +AuthenticateKeySelt = 5 +AutoKeyRevEn = true +KeyRevPermission = 0xff +AutoRollBackProtEn = false +RollbackProtPerm031000 = 0 +RollbackProtPerm063032 = 0 +RollbackProtPerm095063 = 0 +RollbackProtPerm127096 = 0 +ECDSAPrivKeyFile = ECC384r.pem +ECDSAPrivKeyPassword = MCHPECC384r +FwEncrypt = false +AesGenECPubKeyFile = ECC384r_crt.pem +TagBuildNumber= 0 +Comp0ProgDrvStrenEN = false +Comp0WritCmdTotByts = 0 +Comp0ReadCmdByte = 0 +Comp0WritCmdByte = 0 +Comp0DrvValue = 0 +Comp0DrvMask = 0 +Comp1ProgDrvStrenEN = false +Comp1WritCmdTotByts = 0 +Comp1ReadCmdByte = 0 +Comp1WritCmdByte = 0 +Comp1DrvValue = 0 +Comp1DrvMask = 0 + +[IMAGE "1"] +ImageLocation = 0x4000 +SpiFreqMHz = 12 +SpiReadCommand = slow +SpiDriveStrength = 4 +SpiSlewFast = false +SpiSignalControl = 0x00 +IMG1BinFile = zephyr.bin +ImageRevision = 0 +FwOffset = 0 +IMG1LoadAddress = 0xC0000 +IMG1EntryAddress = 0 +UseECDSA = false +AuthenticateKeySelt = 5 +AutoKeyRevEn = true +KeyRevPermission = 0 +AutoRollBackProtEn = false +RollbackProtPerm031000 = 0 +RollbackProtPerm063032 = 0 +RollbackProtPerm095063 = 0 +RollbackProtPerm127096 = 0 +ECDSAPrivKeyFile = ECC384r.pem +ECDSAPrivKeyPassword = MCHPECC384r +FwEncrypt = false +AesGenECPubKeyFile = ECC384r_crt.pem +TagBuildNumber= 0 +Comp0ProgDrvStrenEN = false +Comp0WritCmdTotByts = 0 +Comp0ReadCmdByte = 0 +Comp0WritCmdByte = 0 +Comp0DrvValue = 0 +Comp0DrvMask = 0 +Comp1ProgDrvStrenEN = false +Comp1WritCmdTotByts = 0 +Comp1ReadCmdByte = 0 +Comp1WritCmdByte = 0 +Comp1DrvValue = 0 +Comp1DrvMask = 0 diff --git a/boards/microchip/mpfs_icicle/board.cmake b/boards/microchip/mpfs_icicle/board.cmake new file mode 100644 index 000000000000..ac01618b7116 --- /dev/null +++ b/boards/microchip/mpfs_icicle/board.cmake @@ -0,0 +1,16 @@ +# Copyright (c) 2025 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +set(SUPPORTED_EMU_PLATFORMS renode) +if(CONFIG_BOARD_MPFS_ICICLE_POLARFIRE_U54) + set(RENODE_SCRIPT ${CMAKE_CURRENT_LIST_DIR}/support/mpfs_icicle_polarfire_u54.resc) + set(RENODE_UART sysbus.mmuart1) +elseif(CONFIG_BOARD_MPFS_ICICLE_POLARFIRE_U54_SMP) + set(RENODE_SCRIPT ${CMAKE_CURRENT_LIST_DIR}/support/mpfs_icicle_polarfire_u54_smp.resc) + set(RENODE_UART sysbus.mmuart1) +elseif(CONFIG_BOARD_MPFS_ICICLE_POLARFIRE_E51) + set(RENODE_SCRIPT ${CMAKE_CURRENT_LIST_DIR}/support/mpfs_icicle_polarfire_e51.resc) + set(RENODE_UART sysbus.mmuart0) +endif() + +set(OPENOCD_USE_LOAD_IMAGE NO) diff --git a/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_e51.yaml b/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_e51.yaml index c9b5fe171375..ccd4a482e5e9 100644 --- a/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_e51.yaml +++ b/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_e51.yaml @@ -6,7 +6,14 @@ toolchain: - zephyr ram: 3840 testing: + timeout_multiplier: 8 ignore_tags: - net - bluetooth + renode: + uart: sysbus.mmuart0 + resc: boards/microchip/mpfs_icicle/support/mpfs_icicle_polarfire_e51.resc vendor: microchip +simulation: + - name: renode + exec: renode diff --git a/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54.yaml b/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54.yaml index 6a4b1c782653..a0548f63c00b 100644 --- a/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54.yaml +++ b/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54.yaml @@ -6,7 +6,14 @@ toolchain: - zephyr ram: 3840 testing: + timeout_multiplier: 8 ignore_tags: - net - bluetooth + renode: + uart: sysbus.mmuart1 + resc: boards/microchip/mpfs_icicle/support/mpfs_icicle_polarfire_u54.resc vendor: microchip +simulation: + - name: renode + exec: renode diff --git a/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54_smp.yaml b/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54_smp.yaml index ab9d74860e49..402fa428feb6 100644 --- a/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54_smp.yaml +++ b/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54_smp.yaml @@ -6,7 +6,14 @@ toolchain: - zephyr ram: 3840 testing: + timeout_multiplier: 8 ignore_tags: - net - bluetooth + renode: + uart: sysbus.mmuart1 + resc: boards/microchip/mpfs_icicle/support/mpfs_icicle_polarfire_u54_smp.resc vendor: microchip +simulation: + - name: renode + exec: renode diff --git a/boards/microchip/mpfs_icicle/support/mpfs_icicle_polarfire_e51.resc b/boards/microchip/mpfs_icicle/support/mpfs_icicle_polarfire_e51.resc new file mode 100644 index 000000000000..470139e8e094 --- /dev/null +++ b/boards/microchip/mpfs_icicle/support/mpfs_icicle_polarfire_e51.resc @@ -0,0 +1,26 @@ +# Copyright (c) 2025 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +:name: MPFS-ICICLE-KIT +:description: This script is prepared to run Zephyr on E51 core of PolarFire SoC Icicle Kit RISC-V board. + +$name?="MPFS-ICICLE-KIT" + +using sysbus +mach create $name +machine LoadPlatformDescription @platforms/boards/mpfs-icicle-kit.repl + +showAnalyzer mmuart0 +e51 PerformanceInMips 80 + +# Disable U54 cores +u54_1 IsHalted true +u54_2 IsHalted true +u54_3 IsHalted true +u54_4 IsHalted true + +macro reset +""" + sysbus LoadELF $elf +""" +runMacro $reset diff --git a/boards/microchip/mpfs_icicle/support/mpfs_icicle_polarfire_u54.resc b/boards/microchip/mpfs_icicle/support/mpfs_icicle_polarfire_u54.resc new file mode 100644 index 000000000000..a20c2b7f0e51 --- /dev/null +++ b/boards/microchip/mpfs_icicle/support/mpfs_icicle_polarfire_u54.resc @@ -0,0 +1,26 @@ +# Copyright (c) 2025 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +:name: MPFS-ICICLE-KIT +:description: This script is prepared to run Zephyr on a single U54 core of PolarFire SoC Icicle Kit RISC-V board. + +$name?="MPFS-ICICLE-KIT" + +using sysbus +mach create $name +machine LoadPlatformDescription @platforms/boards/mpfs-icicle-kit.repl + +showAnalyzer mmuart1 + +# Disable E51 core +e51 IsHalted true +# Disable U54 harts other than u54_1 (specified with RV_BOOT_HART=1) +u54_2 IsHalted true +u54_3 IsHalted true +u54_4 IsHalted true + +macro reset +""" + sysbus LoadELF $elf +""" +runMacro $reset diff --git a/boards/microchip/mpfs_icicle/support/mpfs_icicle_polarfire_u54_smp.resc b/boards/microchip/mpfs_icicle/support/mpfs_icicle_polarfire_u54_smp.resc new file mode 100644 index 000000000000..4de9928c4a4f --- /dev/null +++ b/boards/microchip/mpfs_icicle/support/mpfs_icicle_polarfire_u54_smp.resc @@ -0,0 +1,25 @@ +# Copyright (c) 2025 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +:name: MPFS-ICICLE-KIT +:description: This script is prepared to run Zephyr on U54 cores of PolarFire SoC Icicle Kit RISC-V board. + +$name?="MPFS-ICICLE-KIT" + +using sysbus +mach create $name +machine LoadPlatformDescription @platforms/boards/mpfs-icicle-kit.repl + +# Ensure determinism for multi-core tests. +machine SetSerialExecution True + +showAnalyzer mmuart1 + +# Disable E51 core +e51 IsHalted true + +macro reset +""" + sysbus LoadELF $elf +""" +runMacro $reset diff --git a/boards/microchip/pic32c/pic32cm_jh01_cpro/pic32cm_jh01_cpro-pinctrl.dtsi b/boards/microchip/pic32c/pic32cm_jh01_cpro/pic32cm_jh01_cpro-pinctrl.dtsi new file mode 100644 index 000000000000..e8f700b06f94 --- /dev/null +++ b/boards/microchip/pic32c/pic32cm_jh01_cpro/pic32cm_jh01_cpro-pinctrl.dtsi @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + sercom4_uart_default: sercom4_uart_default { + group1 { + pinmux = , + ; + }; + }; +}; diff --git a/boards/microchip/pic32c/pic32cm_jh01_cpro/pic32cm_jh01_cpro.dts b/boards/microchip/pic32c/pic32cm_jh01_cpro/pic32cm_jh01_cpro.dts index 7de914800f98..f51c4e839559 100644 --- a/boards/microchip/pic32c/pic32cm_jh01_cpro/pic32cm_jh01_cpro.dts +++ b/boards/microchip/pic32c/pic32cm_jh01_cpro/pic32cm_jh01_cpro.dts @@ -6,6 +6,7 @@ /dts-v1/; #include +#include "pic32cm_jh01_cpro-pinctrl.dtsi" #include / { @@ -15,6 +16,8 @@ chosen { zephyr,sram = &sram0; zephyr,flash = &flash0; + zephyr,console = &sercom4; + zephyr,shell-uart = &sercom4; }; aliases { @@ -124,3 +127,18 @@ }; }; }; + +&sercom4 { + compatible = "microchip,sercom-g1-uart"; + #address-cells = <1>; + #size-cells = <0>; + current-speed = <115200>; + data-bits = <8>; + parity = "none"; + stop-bits = "1"; + rxpo = <3>; + txpo = <1>; + pinctrl-0 = <&sercom4_uart_default>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/boards/microchip/pic32c/pic32cm_jh01_cpro/pic32cm_jh01_cpro.yaml b/boards/microchip/pic32c/pic32cm_jh01_cpro/pic32cm_jh01_cpro.yaml index d1b7db53376e..1eccd96ff03d 100644 --- a/boards/microchip/pic32c/pic32cm_jh01_cpro/pic32cm_jh01_cpro.yaml +++ b/boards/microchip/pic32c/pic32cm_jh01_cpro/pic32cm_jh01_cpro.yaml @@ -1,4 +1,4 @@ -# Copyright (c) 2025 Microchip Technology Inc. +# Copyright (c) 2025-2026 Microchip Technology Inc. # SPDX-License-Identifier: Apache-2.0 identifier: pic32cm_jh01_cpro @@ -13,4 +13,6 @@ supported: - clock_control - gpio - pinctrl + - reset + - uart vendor: microchip diff --git a/boards/microchip/pic32c/pic32cm_jh01_cpro/pic32cm_jh01_cpro_defconfig b/boards/microchip/pic32c/pic32cm_jh01_cpro/pic32cm_jh01_cpro_defconfig index 912a8e104237..fd05b25cd749 100644 --- a/boards/microchip/pic32c/pic32cm_jh01_cpro/pic32cm_jh01_cpro_defconfig +++ b/boards/microchip/pic32c/pic32cm_jh01_cpro/pic32cm_jh01_cpro_defconfig @@ -3,3 +3,6 @@ CONFIG_BUILD_OUTPUT_HEX=y CONFIG_ARM_MPU=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y diff --git a/boards/microchip/pic32c/pic32cx_sg41_cult/doc/index.rst b/boards/microchip/pic32c/pic32cx_sg41_cult/doc/index.rst index 69b3701e35e7..a022d55043a5 100644 --- a/boards/microchip/pic32c/pic32cx_sg41_cult/doc/index.rst +++ b/boards/microchip/pic32c/pic32cx_sg41_cult/doc/index.rst @@ -23,7 +23,9 @@ Hardware - 64 Mbit Quad SPI Flash - AT24MAC402 Serial EEPROM with EUI-48™ MAC address - Ethernet 10/100 Mbps - - RMII Interface with modular PHY Header + + - RMII Interface with modular PHY Header + - SD/SDIO card connector - Two CAN interfaces with on-board transceivers - I²C-based temperature sensor @@ -31,9 +33,13 @@ Hardware - mikroBUS header connector - Arduino Uno header connectors - CoreSight 10 connector - - 10-pin Cortex® Debug header (SWD) + + - 10-pin Cortex® Debug header (SWD) + - CoreSight 20 connector - - 20-pin Cortex Debug + ETM Connector (SWD and 4-bit Trace) + + - 20-pin Cortex Debug + ETM Connector (SWD and 4-bit Trace) + - Virtual COM port (CDC) - USB powered - Power Header and Barrel Jack connector for external power sources diff --git a/boards/microchip/pic32c/pic32cx_sg41_cult/pic32cx_sg41_cult-pinctrl.dtsi b/boards/microchip/pic32c/pic32cx_sg41_cult/pic32cx_sg41_cult-pinctrl.dtsi index c6040aab4310..b4dec783d205 100644 --- a/boards/microchip/pic32c/pic32cx_sg41_cult/pic32cx_sg41_cult-pinctrl.dtsi +++ b/boards/microchip/pic32c/pic32cx_sg41_cult/pic32cx_sg41_cult-pinctrl.dtsi @@ -14,6 +14,20 @@ }; }; + sercom6_i2c_default: sercom6_i2c_default { + group1 { + pinmux = , + ; + }; + }; + + tc5_pwm_default: tc5_pwm_default { + group1 { + pinmux = , + ; + }; + }; + tcc0_pwm_default: tcc0_pwm_default { group1 { pinmux = ; diff --git a/boards/microchip/pic32c/pic32cx_sg41_cult/pic32cx_sg41_cult.dts b/boards/microchip/pic32c/pic32cx_sg41_cult/pic32cx_sg41_cult.dts index 69bdb88777b5..15d431a67299 100644 --- a/boards/microchip/pic32c/pic32cx_sg41_cult/pic32cx_sg41_cult.dts +++ b/boards/microchip/pic32c/pic32cx_sg41_cult/pic32cx_sg41_cult.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2025 Microchip Technology Inc. + * Copyright (c) 2025-2026 Microchip Technology Inc. * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,6 +7,7 @@ /dts-v1/; #include #include "pic32cx_sg41_cult-pinctrl.dtsi" +#include #include / { @@ -20,12 +21,14 @@ zephyr,shell-uart = &sercom4; zephyr,code-partition = &slot0_partition; zephyr,flash-controller = &nvmctrl; + zephyr,entropy = &trng; }; aliases { led0 = &led1; sw0 = &button0; pwm-led0 = &pwm_led0; + rtc = &rtc; }; leds { @@ -68,6 +71,11 @@ }; }; +&rtc { + prescaler = <1024>; + status = "okay"; +}; + &flash0 { partitions { compatible = "fixed-partitions"; @@ -204,3 +212,25 @@ &dmac { status = "okay"; }; + +&sercom6 { + compatible = "microchip,sercom-g1-i2c"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = ; + pinctrl-0 = <&sercom6_i2c_default>; + pinctrl-names = "default"; + dmas = <&dmac 10 0x10>, <&dmac 11 0x11>; + dma-names = "rx", "tx"; + status = "okay"; +}; + +&tc5 { + compatible = "microchip,tc-g1-pwm"; + #pwm-cells = <3>; + pinctrl-0 = <&tc5_pwm_default>; + pinctrl-names = "default"; + max-bit-width = <16>; + prescaler = <64>; + status = "okay"; +}; diff --git a/boards/microchip/pic32c/pic32cx_sg41_cult/pic32cx_sg41_cult.yaml b/boards/microchip/pic32c/pic32cx_sg41_cult/pic32cx_sg41_cult.yaml index ca20eef5173e..ef3c2b7db4a5 100644 --- a/boards/microchip/pic32c/pic32cx_sg41_cult/pic32cx_sg41_cult.yaml +++ b/boards/microchip/pic32c/pic32cx_sg41_cult/pic32cx_sg41_cult.yaml @@ -1,4 +1,4 @@ -# Copyright (c) 2025 Microchip Technology Inc. +# Copyright (c) 2025-2026 Microchip Technology Inc. # SPDX-License-Identifier: Apache-2.0 identifier: pic32cx_sg41_cult @@ -11,10 +11,17 @@ flash: 1024 ram: 256 supported: - clock_control + - comparator - dma + - entropy - flash - gpio + - hwinfo + - i2c - pinctrl - pwm + - reset + - rtc - uart + - watchdog vendor: microchip diff --git a/boards/microchip/pic32c/pic32cx_sg61_cult/pic32cx_sg61_cult-pinctrl.dtsi b/boards/microchip/pic32c/pic32cx_sg61_cult/pic32cx_sg61_cult-pinctrl.dtsi index b19920ffe259..59463e6f07aa 100644 --- a/boards/microchip/pic32c/pic32cx_sg61_cult/pic32cx_sg61_cult-pinctrl.dtsi +++ b/boards/microchip/pic32c/pic32cx_sg61_cult/pic32cx_sg61_cult-pinctrl.dtsi @@ -14,6 +14,20 @@ }; }; + sercom6_i2c_default: sercom6_i2c_default { + group1 { + pinmux = , + ; + }; + }; + + tc5_pwm_default: tc5_pwm_default { + group1 { + pinmux = , + ; + }; + }; + tcc0_pwm_default: tcc0_pwm_default { group1 { pinmux = ; diff --git a/boards/microchip/pic32c/pic32cx_sg61_cult/pic32cx_sg61_cult.dts b/boards/microchip/pic32c/pic32cx_sg61_cult/pic32cx_sg61_cult.dts index 2bc1769a35e4..3e06b344a346 100644 --- a/boards/microchip/pic32c/pic32cx_sg61_cult/pic32cx_sg61_cult.dts +++ b/boards/microchip/pic32c/pic32cx_sg61_cult/pic32cx_sg61_cult.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2025 Microchip Technology Inc. + * Copyright (c) 2025-2026 Microchip Technology Inc. * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,6 +7,7 @@ /dts-v1/; #include #include "pic32cx_sg61_cult-pinctrl.dtsi" +#include #include / { @@ -20,12 +21,14 @@ zephyr,shell-uart = &sercom4; zephyr,code-partition = &slot0_partition; zephyr,flash-controller = &nvmctrl; + zephyr,entropy = &trng; }; aliases { led0 = &led1; sw0 = &button0; pwm-led0 = &pwm_led0; + rtc = &rtc; }; leds { @@ -62,6 +65,11 @@ }; }; +&rtc { + prescaler = <1024>; + status = "okay"; +}; + &flash0 { partitions { compatible = "fixed-partitions"; @@ -198,3 +206,25 @@ &dmac { status = "okay"; }; + +&sercom6 { + compatible = "microchip,sercom-g1-i2c"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = ; + pinctrl-0 = <&sercom6_i2c_default>; + pinctrl-names = "default"; + dmas = <&dmac 10 0x10>, <&dmac 11 0x11>; + dma-names = "rx", "tx"; + status = "okay"; +}; + +&tc5 { + compatible = "microchip,tc-g1-pwm"; + #pwm-cells = <3>; + pinctrl-0 = <&tc5_pwm_default>; + pinctrl-names = "default"; + max-bit-width = <16>; + prescaler = <64>; + status = "okay"; +}; diff --git a/boards/microchip/pic32c/pic32cx_sg61_cult/pic32cx_sg61_cult.yaml b/boards/microchip/pic32c/pic32cx_sg61_cult/pic32cx_sg61_cult.yaml index dbdf53dd402f..a801516cee49 100644 --- a/boards/microchip/pic32c/pic32cx_sg61_cult/pic32cx_sg61_cult.yaml +++ b/boards/microchip/pic32c/pic32cx_sg61_cult/pic32cx_sg61_cult.yaml @@ -1,4 +1,4 @@ -# Copyright (c) 2025 Microchip Technology Inc. +# Copyright (c) 2025-2026 Microchip Technology Inc. # SPDX-License-Identifier: Apache-2.0 identifier: pic32cx_sg61_cult @@ -11,10 +11,17 @@ flash: 1024 ram: 256 supported: - clock_control + - comparator - dma + - entropy - flash - gpio + - hwinfo + - i2c - pinctrl - pwm + - reset + - rtc - uart + - watchdog vendor: microchip diff --git a/boards/microchip/pic64gx_curiosity_kit/Kconfig.pic64gx_curiosity_kit b/boards/microchip/pic64gx_curiosity_kit/Kconfig.pic64gx_curiosity_kit new file mode 100644 index 000000000000..43944b72d610 --- /dev/null +++ b/boards/microchip/pic64gx_curiosity_kit/Kconfig.pic64gx_curiosity_kit @@ -0,0 +1,7 @@ +# Copyright (c) 2025 Microchip Technology Inc +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_PIC64GX_CURIOSITY_KIT + select SOC_PIC64GX1000_U54 if BOARD_PIC64GX_CURIOSITY_KIT_PIC64GX1000_U54 || \ + BOARD_PIC64GX_CURIOSITY_KIT_PIC64GX1000_U54_SMP + select SOC_PIC64GX1000_E51 if BOARD_PIC64GX_CURIOSITY_KIT_PIC64GX1000_E51 diff --git a/boards/microchip/pic64gx_curiosity_kit/board.cmake b/boards/microchip/pic64gx_curiosity_kit/board.cmake new file mode 100644 index 000000000000..f7270b10e7f2 --- /dev/null +++ b/boards/microchip/pic64gx_curiosity_kit/board.cmake @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 + +set(OPENOCD_USE_LOAD_IMAGE NO) + +board_runner_args(openocd --use-elf --no-load) + +if(CONFIG_BOARD_PIC64GX_CURIOSITY_KIT_PIC64GX1000_E51) + board_runner_args(openocd --gdb-client-port=3333) +elseif(CONFIG_BOARD_PIC64GX_CURIOSITY_KIT_PIC64GX1000_U54) + board_runner_args(openocd --gdb-client-port=3334) +endif() + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/microchip/pic64gx_curiosity_kit/board.yml b/boards/microchip/pic64gx_curiosity_kit/board.yml new file mode 100644 index 000000000000..fd9710620725 --- /dev/null +++ b/boards/microchip/pic64gx_curiosity_kit/board.yml @@ -0,0 +1,9 @@ +board: + name: pic64gx_curiosity_kit + full_name: pic64gx_curiosity_kit + vendor: microchip + socs: + - name: pic64gx1000 + variants: + - name: smp + cpucluster: u54 diff --git a/boards/microchip/pic64gx_curiosity_kit/doc/img/pic64gx_curiosity_kit.webp b/boards/microchip/pic64gx_curiosity_kit/doc/img/pic64gx_curiosity_kit.webp new file mode 100644 index 000000000000..37084cb5e4f0 Binary files /dev/null and b/boards/microchip/pic64gx_curiosity_kit/doc/img/pic64gx_curiosity_kit.webp differ diff --git a/boards/microchip/pic64gx_curiosity_kit/doc/index.rst b/boards/microchip/pic64gx_curiosity_kit/doc/index.rst new file mode 100644 index 000000000000..9179059bf293 --- /dev/null +++ b/boards/microchip/pic64gx_curiosity_kit/doc/index.rst @@ -0,0 +1,114 @@ +.. zephyr:board:: pic64gx_curiosity_kit + +Overview +******** + +The Microchip pic64gx_curiosity_kit board is a RISC-V based development board with a Microchip PIC64GX1000 SoC. +More information can be found on the `Microchip website `_. + +Programming and debugging +************************* + +Building +======== + +Applications for the ``pic64gx_curiosity_kit`` board configuration can be built as usual +(see :ref:`build_an_application`): + +.. zephyr-app-commands:: + :board: pic64gx_curiosity_kit/pic64gx1000/u54 + :goals: build + +.. zephyr-app-commands:: + :board: pic64gx_curiosity_kit/pic64gx1000/u54/smp + :goals: build + +Flashing +======== + +To Flash to the device, the easiest way to proceed is to load the binary using a sdcard. +The binary on the sdcard can then be loaded by the bootloader at the designated address. + +For the bootloader to be able to load the application, a payload file needs to be generated. +Please proceed as follows: + +To get the hss-payload-generator tool, please clone the following repository and build the tool: + +.. code-block:: bash + + git clone https://github.com/pic64gx/pic64gx-hart-software-services.git + cd pic64gx-hart-software-services/tools/hss-payload-generator + make + +To generate a payload: + +.. code-block:: bash + + ./hss-payload-generator -c config.yaml -v output.bin + +A payload generator config file such as the following should be used to generate a compatible with the Hart Software Services (HSS). +https://github.com/pic64gx/pic64gx-hart-software-services + +For single core: + +.. code-block:: yaml + + set-name: 'Zephyr-DDR' + + hart-entry-points: { + u54_1: '0x80000000' + } + + payloads: + build/zephyr/zephyr.elf: { + exec-addr: '0x80000000', + owner-hart: u54_1, + priv-mode: prv_m, + skip-opensbi: true, + payload-name: "zephyr" + } + +For SMP: + +.. code-block:: yaml + + set-name: 'Zephyr-SMP-DDR' + + hart-entry-points: { + u54_1: '0x80000000', + u54_2: '0x80000000', + u54_3: '0x80000000', + u54_4: '0x80000000' + } + + payloads: + build/zephyr/zephyr.elf: { + exec-addr: '0x80000000', + owner-hart: u54_1, + secondary-hart: u54_2, + secondary-hart: u54_3, + secondary-hart: u54_4, + priv-mode: prv_m, + skip-opensbi: true, + payload-name: "zephyr" + } + +Please refer to the following README.md for more information on payload generation: +https://github.com/pic64gx/pic64gx-hart-software-services/blob/pic64gx/tools/hss-payload-generator/README.md + +Then the output payload file needs to be copied to the sdcard (assuming the sdcard is mounted at /dev/sdx). + +.. code-block:: bash + + sudo dd if= of=/dev/sdx + +Debugging +========= + +Please note that in most use cases, the application must be loaded in the external DDR memory. +And therefore DDR must be initialized before loading the application or debugging the application. + +The way to proceed is to load the HSS firmware first, then load the application in DDR memory through +the HSS loader following the instructions in `Flashing`_. + +Then proceed to debug the application as usual (ie: :ref:`application_debugging`.) diff --git a/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_common.dtsi b/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_common.dtsi new file mode 100644 index 000000000000..1997446f9956 --- /dev/null +++ b/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_common.dtsi @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include + +/ { + model = "Microchip PIC64GX Curiosity Kit"; + compatible = "microchip,pic64gx-curiosity-kit", "microchip,pic64gx"; + + aliases { + led0 = &led1; + sw0 = &sw1; + i2c0 = &i2c0; + i2c1 = &i2c1; + }; + + soc { + dram: memory@80000000 { + compatible = "mmio-sram"; + reg = <0x80000000 0x40000000>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led1: led1 { + gpios = <&gpio1 2 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; + label = "LED_1"; + }; + + led2: led2 { + gpios = <&gpio1 3 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; + label = "LED_2"; + }; + + led3: led3 { + gpios = <&gpio1 4 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; + label = "LED_3"; + }; + + led4: led4 { + gpios = <&gpio1 5 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; + label = "LED_4"; + }; + + led5: led5 { + gpios = <&gpio1 6 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; + label = "LED_5"; + }; + + led6: led6 { + gpios = <&gpio1 7 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; + label = "LED_6"; + }; + + led7: led7 { + gpios = <&gpio1 8 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; + label = "LED_7"; + }; + + led8: led8 { + gpios = <&gpio1 9 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; + label = "LED_8"; + }; + }; + + keys { + compatible = "gpio-keys"; + + sw1: sw1 { + gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; + label = "SW_1"; + zephyr,code = ; + }; + + sw2: sw2 { + gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; + label = "SW_2"; + zephyr,code = ; + }; + }; +}; + +&gpio1 { + status = "okay"; + + mux-hog { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>, <3 GPIO_ACTIVE_HIGH>, + <4 GPIO_ACTIVE_HIGH>, <5 GPIO_ACTIVE_HIGH>, + <6 GPIO_ACTIVE_HIGH>, <7 GPIO_ACTIVE_HIGH>, + <8 GPIO_ACTIVE_HIGH>, <9 GPIO_ACTIVE_HIGH>; + output-low; + }; +}; + +&spi1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; diff --git a/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_defconfig b/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_defconfig new file mode 100644 index 000000000000..0501f1bf1218 --- /dev/null +++ b/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_defconfig @@ -0,0 +1,14 @@ +# Copyright (c) 2025 Microchip Technology Inc +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_BASE64=y +CONFIG_INCLUDE_RESET_VECTOR=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_XIP=n +CONFIG_INIT_STACKS=y +CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 +CONFIG_FPU=n +# GPIO driver options +CONFIG_GPIO=y diff --git a/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_e51.dts b/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_e51.dts new file mode 100644 index 000000000000..22eef350de5d --- /dev/null +++ b/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_e51.dts @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include "pic64gx_curiosity_kit_common.dtsi" + +/ { + compatible = "microchip,pic64gx-curiosity-kit", "microchip,pic64gx"; + + cpus { + cpu@1 { + status = "disabled"; + }; + + cpu@2 { + status = "disabled"; + }; + + cpu@3 { + status = "disabled"; + }; + + cpu@4 { + status = "disabled"; + }; + }; + + chosen { + zephyr,console = &mmuart0; + zephyr,shell-uart = &mmuart0; + zephyr,sram = &dram; + }; +}; + +&mmuart0 { + status = "okay"; + current-speed = <115200>; + clock-frequency = <150000000>; +}; diff --git a/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_e51.yaml b/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_e51.yaml new file mode 100644 index 000000000000..0a41b341b508 --- /dev/null +++ b/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_e51.yaml @@ -0,0 +1,12 @@ +identifier: pic64gx_curiosity_kit/pic64gx1000/e51 +name: Microchip PIC64GX Curiosity kit +type: mcu +arch: riscv +toolchain: + - zephyr +ram: 1024 +testing: + ignore_tags: + - net + - bluetooth +vendor: microchip diff --git a/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_e51_defconfig b/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_e51_defconfig new file mode 100644 index 000000000000..186867521425 --- /dev/null +++ b/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_e51_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2025 Microchip Technology Inc +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_BASE64=y +CONFIG_INCLUDE_RESET_VECTOR=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_XIP=n +CONFIG_INIT_STACKS=y +CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 +# GPIO driver options +CONFIG_GPIO=y diff --git a/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_u54.dts b/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_u54.dts new file mode 100644 index 000000000000..bca7e8338be6 --- /dev/null +++ b/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_u54.dts @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include "pic64gx_curiosity_kit_common.dtsi" + +/ { + compatible = "microchip,pic64gx-curiosity-kit", "microchip,pic64gx"; + + cpus { + cpu@0 { + status = "disabled"; + }; + }; + + chosen { + zephyr,console = &mmuart1; + zephyr,shell-uart = &mmuart1; + zephyr,sram = &dram; + }; +}; + +&mmuart1 { + status = "okay"; + current-speed = <115200>; + clock-frequency = <150000000>; +}; diff --git a/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_u54.yaml b/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_u54.yaml new file mode 100644 index 000000000000..9841884511ae --- /dev/null +++ b/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_u54.yaml @@ -0,0 +1,12 @@ +identifier: pic64gx_curiosity_kit/pic64gx1000/u54 +name: Microchip PIC64GX Curiosity kit +type: mcu +arch: riscv +toolchain: + - zephyr +ram: 1024 +testing: + ignore_tags: + - net + - bluetooth +vendor: microchip diff --git a/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_u54_defconfig b/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_u54_defconfig new file mode 100644 index 000000000000..186867521425 --- /dev/null +++ b/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_u54_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2025 Microchip Technology Inc +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_BASE64=y +CONFIG_INCLUDE_RESET_VECTOR=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_XIP=n +CONFIG_INIT_STACKS=y +CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 +# GPIO driver options +CONFIG_GPIO=y diff --git a/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_u54_smp.dts b/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_u54_smp.dts new file mode 100644 index 000000000000..4a1b709c2253 --- /dev/null +++ b/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_u54_smp.dts @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include "pic64gx_curiosity_kit_pic64gx1000_u54.dts" + +/ { + compatible = "microchip,pic64gx-curiosity-kit", "microchip,pic64gx"; + + chosen { + zephyr,console = &mmuart1; + zephyr,shell-uart = &mmuart1; + zephyr,sram = &dram; + }; +}; + +&mmuart1 { + status = "okay"; + current-speed = <115200>; + clock-frequency = <150000000>; +}; diff --git a/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_u54_smp.yaml b/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_u54_smp.yaml new file mode 100644 index 000000000000..48d2e3e30e82 --- /dev/null +++ b/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_u54_smp.yaml @@ -0,0 +1,12 @@ +identifier: pic64gx_curiosity_kit/pic64gx1000/u54/smp +name: Microchip PIC64GX Curiosity kit +type: mcu +arch: riscv +toolchain: + - zephyr +ram: 1024 +testing: + ignore_tags: + - net + - bluetooth +vendor: microchip diff --git a/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_u54_smp_defconfig b/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_u54_smp_defconfig new file mode 100644 index 000000000000..7b885a673457 --- /dev/null +++ b/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_u54_smp_defconfig @@ -0,0 +1,14 @@ +# Copyright (c) 2025 Microchip Technology Inc +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_BASE64=y +CONFIG_INCLUDE_RESET_VECTOR=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_XIP=n +CONFIG_INIT_STACKS=y +CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 +# GPIO driver options +CONFIG_GPIO=y +CONFIG_SMP=y diff --git a/boards/microchip/pic64gx_curiosity_kit/support/embedded_flashpro5.cfg b/boards/microchip/pic64gx_curiosity_kit/support/embedded_flashpro5.cfg new file mode 100644 index 000000000000..9de3a16273b3 --- /dev/null +++ b/boards/microchip/pic64gx_curiosity_kit/support/embedded_flashpro5.cfg @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: Apache-2.0 + +# +# Embedded FlashPro5 custom configuration for PIC64GX Curiosity Kit +# + +adapter speed 6000 + +adapter driver ftdi + +ftdi vid_pid 0x1514 0x200a + +# That FTDI has 4 channels (channel 0 and 1 are MPSSE-capable, 2 and 3 are bitbang +ftdi channel 0 + +# Initial Layout - data[0..15] direction[0..15] +ftdi layout_init 0x0018 0xfdfb +# Signal Data Direction Notes +# AD0 TCK 0 1 (out) Port A TCK +# AD1 TDI 0 1 (out) Port A TDI +# AD2 TDO 0 0 (in) PORT A TDO +# AD3 TMS 1 1 (out) Port A TMS +# AD4 GPIOL0 1 1 (out) Port A TRST +# AD5 GPIOL1 0 1 (out) (unused) +# AD6 GPIOL2 0 1 (out) (unused) +# AD7 GPIOL3 0 1 (out) (unused) + +# BD0 TCK 0 1 (out) FTDI_UART_B_TXD +# BD1 TDI 0 0 (in) FTDI_UART_B_RXD +# BD2 TDO 0 1 (out) (unused) +# BD3 TMS 0 1 (out) (unused) +# BD4 GPIOL0 0 1 (out) (unused) +# BD5 GPIOL1 0 1 (out) (unused) +# BD6 GPIOL2 0 1 (out) (unused) +# BD7 GPIOL2 0 1 (out) (unused) + +# Signals definition +ftdi layout_signal nTRST -data 0x0010 -oe 0x0010 diff --git a/boards/microchip/pic64gx_curiosity_kit/support/openocd.cfg b/boards/microchip/pic64gx_curiosity_kit/support/openocd.cfg new file mode 100644 index 000000000000..7f371e83bf3a --- /dev/null +++ b/boards/microchip/pic64gx_curiosity_kit/support/openocd.cfg @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Target: Pic64gx processor by Microchip Technologies +# +# https://www.microchip.com/en-us/products/microprocessors/64-bit-mpus/pic64gx +# + +adapter speed 6000 + +source [find embedded_flashpro5.cfg] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME pic64gx +} + +# Process COREID variable +if {![exists COREID]} { + set COREID -1 +} + +transport select jtag + +# PIC64GX hart id to name lookup table +array set hart_names { + 0 e51 + 1 u54_1 + 2 u54_2 + 3 u54_3 + 4 u54_4 +} + +# PIC64GX table +set pic64gx_tap_info { + PIC64GX1000 0x0f8531cf +} + +proc expected_ids {tap_list} { + set str "" + dict for {key value} $tap_list { + append str "-expected-id" " " $value " " + } + + return $str +} + +set irlen 8 +set expected_ids [expected_ids $pic64gx_tap_info] +eval jtag newtap $_CHIPNAME cpu -irlen $irlen $expected_ids -ignore-version + +if {$COREID == -1} { + # Single debug connection to all harts + set _TARGETNAME_0 $_CHIPNAME.$hart_names(0) + set _TARGETNAME_1 $_CHIPNAME.$hart_names(1) + set _TARGETNAME_2 $_CHIPNAME.$hart_names(2) + set _TARGETNAME_3 $_CHIPNAME.$hart_names(3) + set _TARGETNAME_4 $_CHIPNAME.$hart_names(4) + + target create $_TARGETNAME_0 riscv -chain-position $_CHIPNAME.cpu -coreid 0 -rtos hwthread + target create $_TARGETNAME_1 riscv -chain-position $_CHIPNAME.cpu -coreid 1 -rtos hwthread + target create $_TARGETNAME_2 riscv -chain-position $_CHIPNAME.cpu -coreid 2 -rtos hwthread + target create $_TARGETNAME_3 riscv -chain-position $_CHIPNAME.cpu -coreid 3 -rtos hwthread + target create $_TARGETNAME_4 riscv -chain-position $_CHIPNAME.cpu -coreid 4 -rtos hwthread + target smp $_TARGETNAME_1 $_TARGETNAME_2 $_TARGETNAME_3 $_TARGETNAME_4 +} else { + # Debug connection to a specific hart + set _TARGETNAME_0 $_CHIPNAME.$hart_names($COREID) + target create $_TARGETNAME_0 riscv -chain-position $_CHIPNAME.cpu -coreid $COREID +} + +# Only TRSTn supported +reset_config trst_only \ No newline at end of file diff --git a/boards/microchip/sam/sam_e54_xpro/sam_e54_xpro-pinctrl.dtsi b/boards/microchip/sam/sam_e54_xpro/sam_e54_xpro-pinctrl.dtsi index 8697ae40f4e8..861cb695a6d9 100644 --- a/boards/microchip/sam/sam_e54_xpro/sam_e54_xpro-pinctrl.dtsi +++ b/boards/microchip/sam/sam_e54_xpro/sam_e54_xpro-pinctrl.dtsi @@ -14,6 +14,15 @@ }; }; + sercom6_spi_default: sercom6_spi_default { + group1 { + pinmux = , + , + , + ; + }; + }; + sercom7_i2c_default: sercom7_i2c_default { group1 { pinmux = , @@ -26,4 +35,33 @@ pinmux = ; }; }; + + tc0_pwm_default: tc0_pwm_default { + group1 { + pinmux = , + ; + }; + }; + + adc0_default: adc0_default { + group1 { + pinmux = , /* EXT2 pin 4 */ + ; /* EXT2 pin 3 */ + }; + }; + + adc1_default: adc1_default { + group1 { + pinmux = , /* EXT1 pin 3 */ + , /* EXT1 pin 4 */ + , /* EXT3 pin 3 */ + ; /* EXT3 pin 4 */ + }; + }; + + dac_default: dac_default { + group1 { + pinmux = ; + }; + }; }; diff --git a/boards/microchip/sam/sam_e54_xpro/sam_e54_xpro.dts b/boards/microchip/sam/sam_e54_xpro/sam_e54_xpro.dts index 6ba9d58374f8..8fdee6a6529c 100644 --- a/boards/microchip/sam/sam_e54_xpro/sam_e54_xpro.dts +++ b/boards/microchip/sam/sam_e54_xpro/sam_e54_xpro.dts @@ -9,6 +9,8 @@ #include "sam_e54_xpro-pinctrl.dtsi" #include #include +#include +#include / { model = "SAM E54 Xplained Pro"; @@ -147,6 +149,14 @@ gclkgen-src = "fdpll0"; gclkgen-en = <1>; }; + + gclkgen1 { + subsystem = ; + gclkgen-div-factor = <2>; + gclkgen-src = "fdpll0"; + gclkgen-run-in-standby-en = <1>; + gclkgen-en = <1>; + }; }; gclkperiph: gclkperiph { @@ -158,6 +168,24 @@ gclkperiph-src = "gclk0"; gclkperiph-en = <1>; }; + + adc0 { + subsystem = ; + gclkperiph-src = "gclk1"; + gclkperiph-en = <0>; + }; + + adc1 { + subsystem = ; + gclkperiph-src = "gclk1"; + gclkperiph-en = <0>; + }; + + dac { + subsystem = ; + gclkperiph-src = "gclk1"; + gclkperiph-en = <0>; + }; }; mclkperiph: mclkperiph { @@ -172,21 +200,34 @@ }; &sercom2 { - status = "okay"; compatible = "microchip,sercom-g1-uart"; #address-cells = <1>; #size-cells = <0>; - current-speed = <115200>; data-bits = <8>; parity = "none"; stop-bits = "1"; - rxpo = <1>; txpo = <0>; - pinctrl-0 = <&sercom2_uart_default>; pinctrl-names = "default"; + dmas = <&dmac 1 8>, <&dmac 2 9>; + dma-names = "rx", "tx"; + status = "okay"; +}; + +&sercom6 { + compatible = "microchip,sercom-g1-spi"; + + dipo = <3>; + dopo = <0>; + + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&sercom6_spi_default>; + pinctrl-names = "default"; + status = "okay"; }; &sercom7 { @@ -196,6 +237,8 @@ clock-frequency = ; pinctrl-0 = <&sercom7_i2c_default>; pinctrl-names = "default"; + dmas = <&dmac 10 0x12>, <&dmac 11 0x13>; + dma-names = "rx", "tx"; status = "okay"; }; @@ -210,6 +253,15 @@ channels = <6>; }; +&tc0 { + compatible = "microchip,tc-g1-pwm"; + #pwm-cells = <3>; + pinctrl-0 = <&tc0_pwm_default>; + pinctrl-names = "default"; + max-bit-width = <32>; + prescaler = <1>; +}; + &portb { status = "okay"; }; @@ -217,3 +269,22 @@ &portc { status = "okay"; }; + +&adc0 { + /* ADC clock = GCLK / prescaler (60 MHz / 4 = 15 MHz) */ + prescaler = <4>; + pinctrl-0 = <&adc0_default>; + pinctrl-names = "default"; +}; + +&adc1 { + /* ADC clock = GCLK / prescaler (60 MHz / 4 = 15 MHz) */ + prescaler = <4>; + pinctrl-0 = <&adc1_default>; + pinctrl-names = "default"; +}; + +&dac { + pinctrl-0 = <&dac_default>; + pinctrl-names = "default"; +}; diff --git a/boards/microchip/sam/sam_e54_xpro/sam_e54_xpro.yaml b/boards/microchip/sam/sam_e54_xpro/sam_e54_xpro.yaml index c1a0b954219f..082077483428 100644 --- a/boards/microchip/sam/sam_e54_xpro/sam_e54_xpro.yaml +++ b/boards/microchip/sam/sam_e54_xpro/sam_e54_xpro.yaml @@ -1,4 +1,4 @@ -# Copyright (c) 2025 Microchip Technology Inc. +# Copyright (c) 2025-2026 Microchip Technology Inc. # SPDX-License-Identifier: Apache-2.0 identifier: sam_e54_xpro @@ -10,8 +10,11 @@ toolchain: flash: 1024 ram: 256 supported: + - adc - clock_control - comparator + - counter + - dac - dma - entropy - flash @@ -24,5 +27,7 @@ supported: - reset - rtc - shell + - spi - uart + - watchdog vendor: microchip diff --git a/boards/microchip/sam/sama7d65_curiosity/sama7d65_curiosity.dts b/boards/microchip/sam/sama7d65_curiosity/sama7d65_curiosity.dts index e6885b731319..04e03cce0f19 100644 --- a/boards/microchip/sam/sama7d65_curiosity/sama7d65_curiosity.dts +++ b/boards/microchip/sam/sama7d65_curiosity/sama7d65_curiosity.dts @@ -9,7 +9,7 @@ #include #include #include -#include +#include / { model = "SAMA7D65-Curiosity board"; diff --git a/boards/microchip/sam/sama7g54_ek/sama7g54_ek.dts b/boards/microchip/sam/sama7g54_ek/sama7g54_ek.dts index 8a6a9695a595..f1463a01ce1e 100644 --- a/boards/microchip/sam/sama7g54_ek/sama7g54_ek.dts +++ b/boards/microchip/sam/sama7g54_ek/sama7g54_ek.dts @@ -13,7 +13,7 @@ #include #include #include -#include +#include / { model = "SAMA7G54-EK board"; @@ -367,6 +367,12 @@ clock-frequency = ; }; +&pit64b1 { + top-alarm; + prescaler-period = <15>; + status = "okay"; +}; + &pwm { pinctrl-0 = <&pinctrl_mikrobus_pwm_default>; pinctrl-names = "default"; diff --git a/boards/microchip/sam/sama7g54_ek/sama7g54_ek.yaml b/boards/microchip/sam/sama7g54_ek/sama7g54_ek.yaml index 94ae1ce1716c..71dd44b8457e 100644 --- a/boards/microchip/sam/sama7g54_ek/sama7g54_ek.yaml +++ b/boards/microchip/sam/sama7g54_ek/sama7g54_ek.yaml @@ -10,9 +10,11 @@ toolchain: ram: 128 supported: - can + - counter - crypto - dma - entropy + - hwinfo - pwm - sdhc - shell diff --git a/boards/mikroe/clicker_2/mikroe_clicker_2.dts b/boards/mikroe/clicker_2/mikroe_clicker_2.dts index fd088435d83a..4022b279a358 100644 --- a/boards/mikroe/clicker_2/mikroe_clicker_2.dts +++ b/boards/mikroe/clicker_2/mikroe_clicker_2.dts @@ -18,7 +18,7 @@ zephyr,shell-uart = &uart4; zephyr,sram = &sram0; zephyr,flash = &flash0; - zephyr,ccm = &ccm0; + zephyr,dtcm = &ccm0; }; leds { diff --git a/boards/nxp/hexiwear/Kconfig.defconfig b/boards/mikroe/hexiwear/Kconfig.defconfig similarity index 100% rename from boards/nxp/hexiwear/Kconfig.defconfig rename to boards/mikroe/hexiwear/Kconfig.defconfig diff --git a/boards/nxp/hexiwear/Kconfig.hexiwear b/boards/mikroe/hexiwear/Kconfig.hexiwear similarity index 100% rename from boards/nxp/hexiwear/Kconfig.hexiwear rename to boards/mikroe/hexiwear/Kconfig.hexiwear diff --git a/boards/nxp/hexiwear/board.cmake b/boards/mikroe/hexiwear/board.cmake similarity index 100% rename from boards/nxp/hexiwear/board.cmake rename to boards/mikroe/hexiwear/board.cmake diff --git a/boards/mikroe/hexiwear/board.yml b/boards/mikroe/hexiwear/board.yml new file mode 100644 index 000000000000..9ae1a49cc20c --- /dev/null +++ b/boards/mikroe/hexiwear/board.yml @@ -0,0 +1,7 @@ +board: + name: hexiwear + full_name: Hexiwear + vendor: mikroe + socs: + - name: mk64f12 + - name: mkw40z4 diff --git a/boards/nxp/hexiwear/doc/hexiwear_k64.jpg b/boards/mikroe/hexiwear/doc/hexiwear_k64.jpg similarity index 100% rename from boards/nxp/hexiwear/doc/hexiwear_k64.jpg rename to boards/mikroe/hexiwear/doc/hexiwear_k64.jpg diff --git a/boards/mikroe/hexiwear/doc/index.rst b/boards/mikroe/hexiwear/doc/index.rst new file mode 100644 index 000000000000..ad17c98f294a --- /dev/null +++ b/boards/mikroe/hexiwear/doc/index.rst @@ -0,0 +1,517 @@ +.. _hexiwear: + +Hexiwear +######## + +Overview +******** + +Hexiwear is powered by a Kinetis K64 microcontroller based on the ARM Cortex-M4 +core. Another Kinetis wireless MCU, the KW40Z, provides Bluetooth Low Energy +connectivity. Hexiwear also integrates a wide variety of sensors, as well as a +user interface consisting of a 1.1" 96px x 96px full color OLED display and six +capacitive buttons with haptic feedback. + +- Eye-catching Smart Watch form factor with powerful, low power Kinetis K6x MCU + and 6 on-board sensors. +- Designed for wearable applications with the onboard rechargeable battery, + OLED screen and onboard sensors such as optical heart rate, accelerometer, + magnetometer and gyroscope. +- Designed for IoT end node applications with the onboard sensor's such as + temperature, pressure, humidity and ambient light. +- Flexibility to let you add the sensors of your choice nearly 200 additional + sensors through click boards. + +.. image:: hexiwear_k64.jpg + :align: center + :alt: Hexiwear + +Hardware +******** + +- Main MCU: NXP Kinetis K64x (ARM Cortex-M4, 120 MHz, 1M Flash, 256K SRAM) +- Wireless MCU: NXP Kinetis KW4x (ARM Cortex-M0+, Bluetooth Low Energy & + 802.15.4 radio) +- 6-axis combo Accelerometer and Magnetometer NXP FXOS8700 +- 3-Axis Gyroscope: NXP FXAS21002 +- Absolute Pressure sensor NXP MPL3115 +- Li-Ion/Li-Po Battery Charger NXP MC34671 +- Optical heart rate sensor Maxim MAX30101 +- Ambient Light sensor, Humidity and Temperature sensor +- 1.1" full color OLED display +- Haptic feedback engine +- 190 mAh 2C Li-Po battery +- Capacitive touch interface +- RGB LED + +For more information about the K64F SoC and Hexiwear board: + +- `K64F Website`_ +- `K64F Datasheet`_ +- `K64F Reference Manual`_ +- `Hexiwear Website`_ +- `Hexiwear Fact Sheet`_ +- `Hexiwear Schematics`_ + +Supported Features +================== + +The hexiwear/mk64f12 board variant supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | soc flash | ++-----------+------------+-------------------------------------+ +| SENSOR | off-chip | fxos8700 polling; | +| | | fxos8700 trigger; | +| | | fxas21002 polling; | +| | | fxas21002 trigger; | +| | | max30101 polling | ++-----------+------------+-------------------------------------+ +| RNGA | on-chip | entropy; | +| | | random | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: + + :zephyr_file:`boards/mikroe/hexiwear/hexiwear_mk64f12_defconfig` + +Other hardware features are not currently supported by the port. + +Connections and IOs +=================== + +The K64F SoC has five pairs of pinmux/gpio controllers. + ++-------+-----------------+---------------------------+ +| Name | Function | Usage | ++=======+=================+===========================+ +| PTA29 | GPIO | LDO_EN | ++-------+-----------------+---------------------------+ +| PTB0 | I2C0_SCL | I2C / MAX30101 | ++-------+-----------------+---------------------------+ +| PTB1 | I2C0_SDA | I2C / MAX30101 | ++-------+-----------------+---------------------------+ +| PTB12 | GPIO | 3V3B EN | ++-------+-----------------+---------------------------+ +| PTB16 | UART0_RX | UART Console | ++-------+-----------------+---------------------------+ +| PTB17 | UART0_TX | UART Console | ++-------+-----------------+---------------------------+ +| PTC8 | GPIO / PWM | Red LED | ++-------+-----------------+---------------------------+ +| PTC9 | GPIO / PWM | Green LED | ++-------+-----------------+---------------------------+ +| PTC10 | I2C1_SCL | I2C / FXOS8700 / FXAS21002| ++-------+-----------------+---------------------------+ +| PTC11 | I2C1_SDA | I2C / FXOS8700 / FXAS21002| ++-------+-----------------+---------------------------+ +| PTC14 | GPIO | Battery sense enable | ++-------+-----------------+---------------------------+ +| PTC18 | GPIO | FXAS21002 INT2 | ++-------+-----------------+---------------------------+ +| PTD0 | GPIO / PWM | Blue LED | ++-------+-----------------+---------------------------+ +| PTD13 | GPIO | FXOS8700 INT2 | ++-------+-----------------+---------------------------+ +| PTE24 | UART4_RX | UART BT HCI | ++-------+-----------------+---------------------------+ +| PTE25 | UART4_TX | UART BT HCI | ++-------+-----------------+---------------------------+ + +.. note:: + + To enable battery sensing, you will need to enable the ``en_bat_sens`` + regulator in Devicetree. Similarly, to enable devices connected to the 1V8 + or 3V3 power rails (sensors), you will need to enable the ``en_ldo`` + and ``en_3v3b`` regulators in Devicetree. + +System Clock +============ + +The K64F SoC is configured to use the 12 MHz external oscillator on the board +with the on-chip PLL to generate a 120 MHz system clock. + +Serial Port +=========== + +The K64F SoC has six UARTs. One is configured for the console, another for BT +HCI, and the remaining are not used. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`, +but because Segger RTT is required for a console on KW40Z, we recommend that +you reconfigure the board for the :ref:`opensda-jlink-onboard-debug-probe`. + +.. note:: + OpenSDA is shared between the K64 and the KW40Z via switches, therefore only + one SoC can be flashed, debugged, or have an open console at a time. + +Option 1: :ref:`opensda-jlink-onboard-debug-probe` (Recommended) +---------------------------------------------------------------- + +Install the :ref:`jlink-debug-host-tools` and make sure they are in your search +path. + +Follow the instructions in :ref:`opensda-jlink-onboard-debug-probe` to program +the `OpenSDA J-Link Generic Firmware for V2.1 Bootloader`_. Check that switches +SW1 and SW2 are **on**, and SW3 and SW4 are **off** to ensure K64F SWD signals +are connected to the OpenSDA microcontroller. + +Option 2: :ref:`opensda-daplink-onboard-debug-probe` +---------------------------------------------------- + +Install the :ref:`pyocd-debug-host-tools` and make sure they are in your search +path. + +Follow the instructions in :ref:`opensda-daplink-onboard-debug-probe` to +program the `OpenSDA DAPLink Hexiwear Firmware`_. Check that switches SW1 and +SW2 are **on**, and SW3 and SW4 are **off** to ensure K64F SWD signals are +connected to the OpenSDA microcontroller. + +Add the arguments ``-DBOARD_FLASH_RUNNER=pyocd`` and +``-DBOARD_DEBUG_RUNNER=pyocd`` when you invoke ``west build`` to override the +default runner from J-Link to pyOCD: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: hexiwear/mk64f12 + :gen-args: -DBOARD_FLASH_RUNNER=pyocd -DBOARD_DEBUG_RUNNER=pyocd + :goals: build + +Configuring a Console +===================== + +Regardless of your choice in debug probe, we will use the OpenSDA +microcontroller as a usb-to-serial adapter for the serial console. + +Connect a USB cable from your PC to CN1. + +Use the following settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: hexiwear/mk64f12 + :goals: flash + +Open a serial terminal, reset the board (press the T4 button), and you should +see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-rc1 ***** + Hello World! hexiwear + +Debugging +========= + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: hexiwear/mk64f12 + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-rc1 ***** + Hello World! hexiwear + +Using Bluetooth +*************** + +Configure the KW40Z as a Bluetooth controller +============================================= + +The K64 can support Zephyr Bluetooth host applications when you configure the +KW40Z as a Bluetooth controller. + +#. Download and install the `KW40Z Connectivity Software`_. This package + contains Bluetooth controller application for the KW40Z. +#. Flash the file ``tools/binaries/BLE_HCI_Modem.bin`` to the KW40Z. + +Now you can build and run the sample Zephyr Bluetooth host applications on the +K64. You do not need to repeat this step each time you flash a new Bluetooth +host application to the K64. + +Peripheral Heart Rate Sensor +============================ + +Navigate to the Zephyr ``samples/bluetooth/peripheral_hr`` sample +application, then build and flash it to the Hexiwear K64. Make sure +the OpenSDA switches on the docking station are configured for the +K64. + +.. zephyr-app-commands:: + :zephyr-app: samples/bluetooth/peripheral_hr + :board: hexiwear/mk64f12 + :goals: build flash + +Reset the KW40Z and the K64 using the push buttons on the docking station. + +Install the Kinetis BLE Toolbox on your smartphone: + +- `Kinetis BLE Toolbox for iOS`_ +- `Kinetis BLE Toolbox for Android`_ + +Open the app, tap the **Heart Rate** feature, and you should see a **Zephyr +Heartrate Sensor** device. Tap the **Zephyr Heartrate Sensor** device and you +will then see a plot of the heart rate data that updates once per second. + + +.. _Hexiwear Website: + https://www.mikroe.com/hexiwear + +.. _Hexiwear Fact Sheet: + https://www.nxp.com/docs/en/fact-sheet/HEXIWEAR-FS.pdf + +.. _Hexiwear Schematics: + http://cdn-docs.mikroe.com/images/c/c0/Sch_Hexiwear_MainBoard_v106c.pdf + +.. _K64F Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/kinetis-cortex-m-mcus/k-seriesperformancem4/k6x-ethernet/kinetis-k64-120-mhz-256kb-sram-microcontrollers-mcus-based-on-arm-cortex-m4-core:K64_120 + +.. _K64F Datasheet: + https://www.nxp.com/docs/en/data-sheet/K64P144M120SF5.pdf + +.. _K64F Reference Manual: + https://www.nxp.com/docs/en/reference-manual/K64P144M120SF5RM.pdf + +.. _OpenSDA J-Link Generic Firmware for V2.1 Bootloader: + https://www.segger.com/downloads/jlink/OpenSDA_V2_1 + +.. _OpenSDA DAPLink Hexiwear Firmware: + https://github.com/MikroElektronika/HEXIWEAR/blob/master/HW/HEXIWEAR_DockingStation/HEXIWEAR_DockingStation_DAPLINK_FW.bin + +.. _KW40Z Connectivity Software: + https://www.nxp.com/webapp/Download?colCode=KW40Z-CONNECTIVITY-SOFTWARE&appType=license&location=null&fpsp=1&WT_TYPE=Protocol%20Stacks&WT_VENDOR=FREESCALE&WT_FILE_FORMAT=exe&WT_ASSET=Downloads&fileExt=.exe&Parent_nodeId=1432854896956716810497&Parent_pageType=product + +.. _Kinetis BLE Toolbox for iOS: + https://itunes.apple.com/us/app/kinetis-ble-toolbox/id1049036961?mt=8 + +.. _Kinetis BLE Toolbox for Android: + https://play.google.com/store/apps/details?id=com.freescale.kinetisbletoolbox + + +Hexiwear KW40Z +############## + +Overview +******** + +The KW40Z is a secondary SoC on the board that provides wireless connectivity +with a multimode BLE and 802.15.4 radio. + +For more information about the KW40Z SoC: + +- `KW40Z Website`_ +- `KW40Z Datasheet`_ +- `KW40Z Reference Manual`_ + +Supported Features +================== + +The hexiwear/mkw40z4 board variant supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| RTT | on-chip | console | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | soc flash | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: + + :zephyr_file:`boards/mikroe/hexiwear/hexiwear_mkw40z4_defconfig` + +Other hardware features are not currently supported by the port. + +Connections and IOs +=================== + +The KW40Z SoC has three pairs of pinmux/gpio controllers, but only one is +currently enabled (PORTC/GPIOC) for the hexiwear/mkw40z4 board. + ++-------+-----------------+---------------------------+ +| Name | Function | Usage | ++=======+=================+===========================+ +| PTB1 | ADC | ADC0 channel 1 | ++-------+-----------------+---------------------------+ +| PTC6 | UART0_RX | UART BT HCI | ++-------+-----------------+---------------------------+ +| PTC7 | UART0_TX | UART BT HCI | ++-------+-----------------+---------------------------+ + +System Clock +============ + +The KW40Z SoC is configured to use the 32 MHz external oscillator on the board +with the on-chip FLL to generate a 40 MHz system clock. + +Serial Port +=========== + +The KW40Z SoC has one UART, which is used for BT HCI. There is no UART +available for a console. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`, +but because Segger RTT is required for a console, you must reconfigure the +board for one of the following debug probes instead. + +:ref:`opensda-jlink-onboard-debug-probe` +---------------------------------------- + +Install the :ref:`jlink-debug-host-tools` and make sure they are in your search +path. + +Follow the instructions in :ref:`opensda-jlink-onboard-debug-probe` to program +the `OpenSDA J-Link Generic Firmware for V2.1 Bootloader`_. Check that switches +SW1 and SW2 are **off**, and SW3 and SW4 are **on** to ensure KW40Z SWD signals +are connected to the OpenSDA microcontroller. + +Configuring a Console +===================== + +The console is available using `Segger RTT`_. + +Connect a USB cable from your PC to CN1. + +Once you have started a debug session, run telnet: + +.. code-block:: console + + $ telnet localhost 19021 + Trying 127.0.0.1... + Connected to localhost. + Escape character is '^]'. + SEGGER J-Link V6.44 - Real time terminal output + J-Link OpenSDA 2 compiled Feb 28 2017 19:27:57 V1.0, SN=621000000 + Process: JLinkGDBServerCLExe + +Flashing +======== + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: hexiwear/mkw40z4 + :goals: flash + +The Segger RTT console is only available during a debug session. Use ``attach`` +to start one: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: hexiwear/mkw40z4 + :goals: attach + +Run telnet as shown earlier, and you should see the following message in the +terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-rc1 ***** + Hello World! hexiwear + +Debugging +========= + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: hexiwear/mkw40z4 + :goals: debug + +Run telnet as shown earlier, step through the application in your debugger, and +you should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-rc1 ***** + Hello World! hexiwear + +.. _KW40Z Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/kinetis-cortex-m-mcus/w-serieswireless-conn.m0-plus-m4/kinetis-kw40z-2.4-ghz-dual-mode-ble-and-802.15.4-wireless-radio-microcontroller-mcu-based-on-arm-cortex-m0-plus-core:KW40Z + +.. _KW40Z Datasheet: + https://www.nxp.com/docs/en/data-sheet/MKW40Z160.pdf + +.. _KW40Z Reference Manual: + https://www.nxp.com/webapp/Download?colCode=MKW40Z160RM + +.. _Segger RTT: + https://www.segger.com/products/debug-probes/j-link/technology/about-real-time-transfer/ + +.. _OpenSDA J-Link Generic Firmware for V2.1 Bootloader: + https://www.segger.com/downloads/jlink/OpenSDA_V2_1 diff --git a/boards/nxp/hexiwear/hexiwear_mk64f12-pinctrl.dtsi b/boards/mikroe/hexiwear/hexiwear_mk64f12-pinctrl.dtsi similarity index 100% rename from boards/nxp/hexiwear/hexiwear_mk64f12-pinctrl.dtsi rename to boards/mikroe/hexiwear/hexiwear_mk64f12-pinctrl.dtsi diff --git a/boards/nxp/hexiwear/hexiwear_mk64f12.dts b/boards/mikroe/hexiwear/hexiwear_mk64f12.dts similarity index 97% rename from boards/nxp/hexiwear/hexiwear_mk64f12.dts rename to boards/mikroe/hexiwear/hexiwear_mk64f12.dts index 6ac4661aebd0..5db8502ea4f4 100644 --- a/boards/nxp/hexiwear/hexiwear_mk64f12.dts +++ b/boards/mikroe/hexiwear/hexiwear_mk64f12.dts @@ -7,13 +7,13 @@ /dts-v1/; -#include +#include #include #include "hexiwear_mk64f12-pinctrl.dtsi" / { model = "Hexiwear K64 board"; - compatible = "nxp,hexiwear", "nxp,k64f", "nxp,k6x"; + compatible = "mikroe,hexiwear", "nxp,k64f", "nxp,k6x"; aliases { led0 = &green_led; diff --git a/boards/nxp/hexiwear/hexiwear_mk64f12.yaml b/boards/mikroe/hexiwear/hexiwear_mk64f12.yaml similarity index 92% rename from boards/nxp/hexiwear/hexiwear_mk64f12.yaml rename to boards/mikroe/hexiwear/hexiwear_mk64f12.yaml index f545c591d96f..171032e915a7 100644 --- a/boards/nxp/hexiwear/hexiwear_mk64f12.yaml +++ b/boards/mikroe/hexiwear/hexiwear_mk64f12.yaml @@ -13,4 +13,4 @@ supported: - i2c - pwm - watchdog -vendor: nxp +vendor: mikroe diff --git a/boards/nxp/hexiwear/hexiwear_mk64f12_defconfig b/boards/mikroe/hexiwear/hexiwear_mk64f12_defconfig similarity index 100% rename from boards/nxp/hexiwear/hexiwear_mk64f12_defconfig rename to boards/mikroe/hexiwear/hexiwear_mk64f12_defconfig diff --git a/boards/nxp/hexiwear/hexiwear_mkw40z4-pinctrl.dtsi b/boards/mikroe/hexiwear/hexiwear_mkw40z4-pinctrl.dtsi similarity index 100% rename from boards/nxp/hexiwear/hexiwear_mkw40z4-pinctrl.dtsi rename to boards/mikroe/hexiwear/hexiwear_mkw40z4-pinctrl.dtsi diff --git a/boards/nxp/hexiwear/hexiwear_mkw40z4.dts b/boards/mikroe/hexiwear/hexiwear_mkw40z4.dts similarity index 84% rename from boards/nxp/hexiwear/hexiwear_mkw40z4.dts rename to boards/mikroe/hexiwear/hexiwear_mkw40z4.dts index c75ca229d345..6cdaa8cabed5 100644 --- a/boards/nxp/hexiwear/hexiwear_mkw40z4.dts +++ b/boards/mikroe/hexiwear/hexiwear_mkw40z4.dts @@ -1,8 +1,12 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ /dts-v1/; -#include +#include #include "hexiwear_mkw40z4-pinctrl.dtsi" / { diff --git a/boards/nxp/hexiwear/hexiwear_mkw40z4.yaml b/boards/mikroe/hexiwear/hexiwear_mkw40z4.yaml similarity index 91% rename from boards/nxp/hexiwear/hexiwear_mkw40z4.yaml rename to boards/mikroe/hexiwear/hexiwear_mkw40z4.yaml index e0e49ea82e99..f7cea0894c0a 100644 --- a/boards/nxp/hexiwear/hexiwear_mkw40z4.yaml +++ b/boards/mikroe/hexiwear/hexiwear_mkw40z4.yaml @@ -10,4 +10,4 @@ toolchain: testing: ignore_tags: - net -vendor: nxp +vendor: mikroe diff --git a/boards/nxp/hexiwear/hexiwear_mkw40z4_defconfig b/boards/mikroe/hexiwear/hexiwear_mkw40z4_defconfig similarity index 100% rename from boards/nxp/hexiwear/hexiwear_mkw40z4_defconfig rename to boards/mikroe/hexiwear/hexiwear_mkw40z4_defconfig diff --git a/boards/mikroe/mini_m4_for_stm32/doc/mikroe_mini_m4_for_stm32.rst b/boards/mikroe/mini_m4_for_stm32/doc/mikroe_mini_m4_for_stm32.rst index 59d728b3c87e..cc2f40dd956c 100644 --- a/boards/mikroe/mini_m4_for_stm32/doc/mikroe_mini_m4_for_stm32.rst +++ b/boards/mikroe/mini_m4_for_stm32/doc/mikroe_mini_m4_for_stm32.rst @@ -3,7 +3,7 @@ Overview ******** -MINI-M4 for STM32 is a small ARM® Cortex |reg|-M4 development board containing +MINI-M4 for STM32 is a small ARM® Cortex®-M4 development board containing an `STM32F415RG`_ microcontroller. It is pin compatible with PIC16F887 and PIC18(L)F45K20 microcontrollers and it perfectly fits into a standard DIP40 socket. The board is equipped with a 16MHz SMD crystal oscillator, and diff --git a/boards/mikroe/mini_m4_for_stm32/mikroe_mini_m4_for_stm32.dts b/boards/mikroe/mini_m4_for_stm32/mikroe_mini_m4_for_stm32.dts index c4fcefacb5b4..6b57785a196d 100644 --- a/boards/mikroe/mini_m4_for_stm32/mikroe_mini_m4_for_stm32.dts +++ b/boards/mikroe/mini_m4_for_stm32/mikroe_mini_m4_for_stm32.dts @@ -17,7 +17,7 @@ zephyr,shell-uart = &usart2; zephyr,sram = &sram0; zephyr,flash = &flash0; - zephyr,ccm = &ccm0; + zephyr,dtcm = &ccm0; }; leds { diff --git a/boards/mikroe/quail/mikroe_quail.dts b/boards/mikroe/quail/mikroe_quail.dts index 2064b9be0777..3b22131acd5c 100644 --- a/boards/mikroe/quail/mikroe_quail.dts +++ b/boards/mikroe/quail/mikroe_quail.dts @@ -17,7 +17,7 @@ zephyr,sram = &sram0; zephyr,flash = &flash0; zephyr,flash-controller = &flash1; - zephyr,ccm = &ccm0; + zephyr,dtcm = &ccm0; }; leds { diff --git a/boards/mxchip/az3166_iotdevkit/az3166_iotdevkit.dts b/boards/mxchip/az3166_iotdevkit/az3166_iotdevkit.dts index e01b8d52eff6..b24be56345b4 100644 --- a/boards/mxchip/az3166_iotdevkit/az3166_iotdevkit.dts +++ b/boards/mxchip/az3166_iotdevkit/az3166_iotdevkit.dts @@ -171,7 +171,7 @@ }; ssd1306: ssd1306@3c { - compatible = "solomon,ssd1306fb"; + compatible = "solomon,ssd1306"; reg = <0x3c>; width = <128>; height = <64>; diff --git a/boards/native/common/natsim_config.cmake b/boards/native/common/natsim_config.cmake index 41e5341b3509..4c9a163e0bac 100644 --- a/boards/native/common/natsim_config.cmake +++ b/boards/native/common/natsim_config.cmake @@ -13,6 +13,10 @@ if(SYSROOT_DIR) target_link_options(native_simulator INTERFACE "--sysroot=${SYSROOT_DIR}") endif() +if(CONFIG_NATIVE_SIMULATOR_STATIC_LINKING) + target_link_options(native_simulator INTERFACE "-static") +endif() + if("${LINKER}" STREQUAL "lld") target_link_options(native_simulator INTERFACE "-fuse-ld=lld") endif() diff --git a/boards/native/common/sdl/CMakeLists.txt b/boards/native/common/sdl/CMakeLists.txt index fb6c7bd559e1..c09f2468aeb0 100644 --- a/boards/native/common/sdl/CMakeLists.txt +++ b/boards/native/common/sdl/CMakeLists.txt @@ -2,8 +2,6 @@ zephyr_library() -zephyr_library_compile_definitions(NO_POSIX_CHEATS) - find_package(PkgConfig REQUIRED) pkg_search_module(SDL2 REQUIRED sdl2) diff --git a/boards/native/native_sim/CMakeLists.txt b/boards/native/native_sim/CMakeLists.txt index 7c0d6b3f7c6e..490d1bbc5230 100644 --- a/boards/native/native_sim/CMakeLists.txt +++ b/boards/native/native_sim/CMakeLists.txt @@ -2,8 +2,6 @@ zephyr_library() -zephyr_library_compile_definitions(NO_POSIX_CHEATS) - zephyr_library_sources( cmdline.c cpu_wait.c diff --git a/boards/native/native_sim/native_sim.dts b/boards/native/native_sim/native_sim.dts index 86f78c133ee4..128562a7f506 100644 --- a/boards/native/native_sim/native_sim.dts +++ b/boards/native/native_sim/native_sim.dts @@ -77,12 +77,12 @@ boot_partition: partition@0 { label = "mcuboot"; - reg = <0x00000000 0x0000C000>; + reg = <0x00000000 0x0000c000>; }; slot0_partition: partition@c000 { label = "image-0"; - reg = <0x0000C000 0x00069000>; + reg = <0x0000c000 0x00069000>; }; slot1_partition: partition@75000 { @@ -109,6 +109,12 @@ size = ; }; + otp0: otp { + compatible = "zephyr,otp-emul"; + size = ; + status = "okay"; + }; + i2c0: i2c@100 { status = "okay"; compatible = "zephyr,i2c-emul-controller"; diff --git a/boards/native/nrf_bsim/common/cmsis/cmsis.c b/boards/native/nrf_bsim/common/cmsis/cmsis.c index dac5f82e699e..c241e3a7b3d6 100644 --- a/boards/native/nrf_bsim/common/cmsis/cmsis.c +++ b/boards/native/nrf_bsim/common/cmsis/cmsis.c @@ -97,3 +97,156 @@ void __SEV(void) { nrfbsim_SEV_model(); } + +/* + * Implement the following ARM instructions + * + * - STR Exclusive(8,16 & 32bit) (__STREX{B,H,W}) + * - LDR Exclusive(8,16 & 32bit) (__LDREX{B,H,W}) + * - CLREX : Exclusive lock removal (__CLREX) + * + * Description: + * From ARMs description it is relatively unclear how the LDREX/STREX/CLREX + * are really implemented in M4/M33 devices. + * + * The current model simply sets a local monitor (local to the processor) + * exclusive lock for the current MCU when a LDREX is executed. + * STREX check this lock, and succeeds if set, fails otherwise. + * The lock is cleared whenever STREX or CLREX are run, or when we return + * from an interrupt handler. + * See Arm v8-M Architecture Reference Manual: "B9.2 The local monitors" and + * "B9.4 Exclusive access instructions and the monitors". + * + * The address is ignored, and we do not model a "system/global" monitor. + * The access width is ignored from the locking point of view. + * In principle this model would seem to fulfill the functionality described + * by ARM. + * + * Note that as the POSIX arch will not make an embedded + * thread lose context while just executing its own code, and it does not + * allow parallel embedded SW threads to execute at the same exact time, + * there is no real need to protect atomicity. + * But, some embedded code may use this instructions in between busy waits, + * and expect that an interrupt in the meanwhile will indeed cause a + * following STREX to fail. + * + * As this ARM exclusive access monitor mechanism can in principle be + * used for other, unexpected, purposes, this simple replacement may not be + * enough. + */ + +static bool ex_lock; /* LDREX/STREX/CLREX lock state */ + +bool nrfbsim_STREXlock_model(void) +{ + if (ex_lock == false) { + return true; + } + + ex_lock = false; + return false; +} + +void nrfbsim_clear_excl_access(void) +{ + ex_lock = false; +} + +/** + * \brief Pretend to execute a STR Exclusive (8 bit) + * \details Executes an exclusive STR instruction for 8 bit values. + * \param [in] value Value to store + * \param [in] ptr Pointer to location + * \return 0 Function succeeded + * \return 1 Function did not succeeded (value not changed) + */ +uint32_t __STREXB(uint8_t value, volatile uint8_t *ptr) +{ + if (nrfbsim_STREXlock_model()) { + return 1; + } + *ptr = value; + return 0; +} + +/** + * \brief Pretend to execute a STR Exclusive (16 bit) + * \details Executes a exclusive STR instruction for 16 bit values. + * \param [in] value Value to store + * \param [in] ptr Pointer to location + * \return 0 Function succeeded + * \return 1 Function did not succeeded (value not changed) + */ +uint32_t __STREXH(uint16_t value, volatile uint16_t *ptr) +{ + if (nrfbsim_STREXlock_model()) { + return 1; + } + *ptr = value; + return 0; +} + +/** + * \brief Pretend to execute a STR Exclusive (32 bit) + * \details Executes a exclusive~ STR instruction for 32 bit values. + * \param [in] value Value to store + * \param [in] ptr Pointer to location + * \return 0 Function succeeded + * \return 1 Function did not succeeded (value not changed) + */ +uint32_t __STREXW(uint32_t value, volatile uint32_t *ptr) +{ + if (nrfbsim_STREXlock_model()) { + return 1; + } + *ptr = value; + return 0; +} + +/** + * \brief Pretend to execute a LDR Exclusive (8 bit) + * \details Executes an exclusive LDR instruction for 8 bit value. + * Meaning, set an exclusive lock, and load the stored value + * \param [in] ptr Pointer to data + * \return value of type uint8_t at (*ptr) + */ +uint8_t __LDREXB(volatile uint8_t *ptr) +{ + ex_lock = true; + return *ptr; +} + +/** + * \brief Pretend to execute a LDR Exclusive (16 bit) + * \details Executes an ~exclusive~ LDR instruction for 16 bit value. + * Meaning, set an exclusive lock, and load the stored value + * \param [in] ptr Pointer to data + * \return value of type uint8_t at (*ptr) + */ +uint16_t __LDREXH(volatile uint16_t *ptr) +{ + ex_lock = true; + return *ptr; +} + +/** + * \brief Execute a LDR Exclusive (32 bit) + * \details Executes an exclusive LDR instruction for 32 bit value. + * Meaning, set an exclusive lock, and load the stored value + * \param [in] ptr Pointer to data + * \return value of type uint8_t at (*ptr) + */ +uint32_t __LDREXW(volatile uint32_t *ptr) +{ + ex_lock = true; + return *ptr; +} + +/** + * \brief Remove the exclusive lock + * \details Removes the exclusive lock which is created by LDREX + */ +void __CLREX(void) +{ + ex_lock = false; +} diff --git a/boards/native/nrf_bsim/common/cmsis/cmsis.h b/boards/native/nrf_bsim/common/cmsis/cmsis.h index 25a9fe4d6578..490e9af8025c 100644 --- a/boards/native/nrf_bsim/common/cmsis/cmsis.h +++ b/boards/native/nrf_bsim/common/cmsis/cmsis.h @@ -36,6 +36,8 @@ void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority); uint32_t NVIC_GetPriority(IRQn_Type IRQn); void NVIC_SystemReset(void); +void nrfbsim_clear_excl_access(void); + #ifdef __cplusplus } #endif diff --git a/boards/native/nrf_bsim/common/cmsis/cmsis_instr.h b/boards/native/nrf_bsim/common/cmsis/cmsis_instr.h index e3dfd2aad232..619c68d75490 100644 --- a/boards/native/nrf_bsim/common/cmsis/cmsis_instr.h +++ b/boards/native/nrf_bsim/common/cmsis/cmsis_instr.h @@ -40,116 +40,13 @@ void __WFE(void); void __WFI(void); void __SEV(void); -/* - * Implement the following ARM intrinsics as non-exclusive accesses - * - * - STR Exclusive(8,16 & 32bit) (__STREX{B,H,W}) - * - LDR Exclusive(8,16 & 32bit) (__LDREX{B,H,W}) - * - CLREX : Exclusive lock removal (__CLREX) - no-op - * - * Description: - * These accesses always succeed, and do NOT set any kind of internal - * exclusive access flag; - * There is no local/global memory monitors, MPU control of what are - * shareable regions, exclusive reservations granules, automatic clearing - * on context switch, or so. - * - * This should be enough for the expected uses of LDR/STREXB - * (locking mutexes or guarding other atomic operations, inside a few lines - * of code in the same function): As the POSIX arch will not make an embedded - * thread lose context while just executing its own code, and it does not - * allow parallel embedded SW threads to execute at the same exact time, - * there is no actual need to protect atomicity. - * - * But as this ARM exclusive access monitor mechanism can in principle be - * used for other, unexpected, purposes, this simple replacement may not be - * enough. - */ - -/** - * \brief Pretend to execute a STR Exclusive (8 bit) - * \details Executes a ~exclusive~ STR instruction for 8 bit values. - * \param [in] value Value to store - * \param [in] ptr Pointer to location - * \return 0 Function succeeded (always) - */ -static inline uint32_t __STREXB(uint8_t value, volatile uint8_t *ptr) -{ - *ptr = value; - return 0; -} - -/** - * \brief Pretend to execute a STR Exclusive (16 bit) - * \details Executes a ~exclusive~ STR instruction for 16 bit values. - * \param [in] value Value to store - * \param [in] ptr Pointer to location - * \return 0 Function succeeded (always) - */ -static inline uint32_t __STREXH(uint16_t value, volatile uint16_t *ptr) -{ - *ptr = value; - return 0; -} - -/** - * \brief Pretend to execute a STR Exclusive (32 bit) - * \details Executes a ~exclusive~ STR instruction for 32 bit values. - * \param [in] value Value to store - * \param [in] ptr Pointer to location - * \return 0 Function succeeded (always) - */ -static inline uint32_t __STREXW(uint32_t value, volatile uint32_t *ptr) -{ - *ptr = value; - return 0; -} - -/** - * \brief Pretend to execute a LDR Exclusive (8 bit) - * \details Executes an ~exclusive~ LDR instruction for 8 bit value. - * Meaning, it does not set a exclusive lock, - * instead just loads the stored value - * \param [in] ptr Pointer to data - * \return value of type uint8_t at (*ptr) - */ -static inline uint8_t __LDREXB(volatile uint8_t *ptr) -{ - return *ptr; -} - -/** - * \brief Pretend to execute a LDR Exclusive (16 bit) - * \details Executes an ~exclusive~ LDR instruction for 16 bit value. - * Meaning, it does not set a exclusive lock, - * instead just loads the stored value - * \param [in] ptr Pointer to data - * \return value of type uint8_t at (*ptr) - */ -static inline uint16_t __LDREXH(volatile uint16_t *ptr) -{ - return *ptr; -} - -/** - * \brief Pretend to execute a LDR Exclusive (32 bit) - * \details Executes an ~exclusive~ LDR instruction for 32 bit value. - * Meaning, it does not set a exclusive lock, - * instead just loads the stored value - * \param [in] ptr Pointer to data - * \return value of type uint8_t at (*ptr) - */ -static inline uint32_t __LDREXW(volatile uint32_t *ptr) -{ - return *ptr; -} - -/** - * \brief Pretend to remove the exclusive lock - * \details The real function would removes the exclusive lock which is created - * by LDREX, this one does nothing - */ -static inline void __CLREX(void) { /* Nothing to be done */ } +uint32_t __STREXB(uint8_t value, volatile uint8_t *ptr); +uint32_t __STREXH(uint16_t value, volatile uint16_t *ptr); +uint32_t __STREXW(uint32_t value, volatile uint32_t *ptr); +uint8_t __LDREXB(volatile uint8_t *ptr); +uint16_t __LDREXH(volatile uint16_t *ptr); +uint32_t __LDREXW(volatile uint32_t *ptr); +void __CLREX(void); /** * \brief Model of an ARM CLZ instruction diff --git a/boards/native/nrf_bsim/irq_handler.c b/boards/native/nrf_bsim/irq_handler.c index 74d0dc5889ee..502be495def7 100644 --- a/boards/native/nrf_bsim/irq_handler.c +++ b/boards/native/nrf_bsim/irq_handler.c @@ -117,6 +117,7 @@ void posix_irq_handler(void) currently_running_irq = irq_nbr; vector_to_irq(irq_nbr, &may_swap); + nrfbsim_clear_excl_access(); currently_running_irq = last_running_irq; hw_irq_ctrl_reeval_level_irq(cpu_n, irq_nbr); diff --git a/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet.dts b/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet.dts index 567e87869d39..94f1ee0ccbbd 100644 --- a/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet.dts +++ b/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet.dts @@ -55,11 +55,13 @@ &flash1 { reg = <0x01000000 DT_SIZE_K(256)>; + ranges = <0x0 0x01000000 DT_SIZE_K(256)>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + ranges; storage_partition: partition@0 { label = "storage"; diff --git a/boards/nordic/nrf21540dk/nrf21540dk_nrf52840-pinctrl.dtsi b/boards/nordic/nrf21540dk/nrf21540dk_nrf52840-pinctrl.dtsi index d1da980ec5cf..a59b81a35b06 100644 --- a/boards/nordic/nrf21540dk/nrf21540dk_nrf52840-pinctrl.dtsi +++ b/boards/nordic/nrf21540dk/nrf21540dk_nrf52840-pinctrl.dtsi @@ -19,12 +19,17 @@ uart0_sleep: uart0_sleep { group1 { - psels = , - , + psels = , , ; low-power-enable; }; + + group2 { + psels = ; + low-power-enable; + bias-pull-up; + }; }; uart1_default: uart1_default { diff --git a/boards/nordic/nrf21540dk/nrf21540dk_nrf52840.dts b/boards/nordic/nrf21540dk/nrf21540dk_nrf52840.dts index 7368127a72a6..801782c35efe 100644 --- a/boards/nordic/nrf21540dk/nrf21540dk_nrf52840.dts +++ b/boards/nordic/nrf21540dk/nrf21540dk_nrf52840.dts @@ -279,12 +279,12 @@ fem_spi: &spi3 { boot_partition: partition@0 { label = "mcuboot"; - reg = <0x00000000 0x0000C000>; + reg = <0x00000000 0x0000c000>; }; slot0_partition: partition@c000 { label = "image-0"; - reg = <0x0000C000 0x00076000>; + reg = <0x0000c000 0x00076000>; }; slot1_partition: partition@82000 { diff --git a/boards/nordic/nrf51dk/nrf51dk_nrf51822-pinctrl.dtsi b/boards/nordic/nrf51dk/nrf51dk_nrf51822-pinctrl.dtsi index c806e25f8ce4..e7399e0ccee2 100644 --- a/boards/nordic/nrf51dk/nrf51dk_nrf51822-pinctrl.dtsi +++ b/boards/nordic/nrf51dk/nrf51dk_nrf51822-pinctrl.dtsi @@ -15,12 +15,17 @@ uart0_sleep: uart0_sleep { group1 { - psels = , - , + psels = , , ; low-power-enable; }; + + group2 { + psels = ; + low-power-enable; + bias-pull-up; + }; }; i2c0_default: i2c0_default { diff --git a/boards/nordic/nrf52833dk/nrf52833dk_nrf52820-pinctrl.dtsi b/boards/nordic/nrf52833dk/nrf52833dk_nrf52820-pinctrl.dtsi index 0a2dd6da3ef2..2973c48ac6f7 100644 --- a/boards/nordic/nrf52833dk/nrf52833dk_nrf52820-pinctrl.dtsi +++ b/boards/nordic/nrf52833dk/nrf52833dk_nrf52820-pinctrl.dtsi @@ -19,12 +19,17 @@ uart0_sleep: uart0_sleep { group1 { - psels = , - , + psels = , , ; low-power-enable; }; + + group2 { + psels = ; + low-power-enable; + bias-pull-up; + }; }; i2c0_default: i2c0_default { diff --git a/boards/nordic/nrf52833dk/nrf52833dk_nrf52820.dts b/boards/nordic/nrf52833dk/nrf52833dk_nrf52820.dts index 04c90fbbb017..6516a779928f 100644 --- a/boards/nordic/nrf52833dk/nrf52833dk_nrf52820.dts +++ b/boards/nordic/nrf52833dk/nrf52833dk_nrf52820.dts @@ -167,12 +167,12 @@ boot_partition: partition@0 { label = "mcuboot"; - reg = <0x00000000 0xC000>; + reg = <0x00000000 0xc000>; }; - slot0_partition: partition@C000 { + slot0_partition: partition@c000 { label = "image-0"; - reg = <0x0000C000 0x17000>; + reg = <0x0000c000 0x17000>; }; slot1_partition: partition@23000 { diff --git a/boards/nordic/nrf52833dk/nrf52833dk_nrf52833-pinctrl.dtsi b/boards/nordic/nrf52833dk/nrf52833dk_nrf52833-pinctrl.dtsi index bddbc2f5a365..e5de1ae3986e 100644 --- a/boards/nordic/nrf52833dk/nrf52833dk_nrf52833-pinctrl.dtsi +++ b/boards/nordic/nrf52833dk/nrf52833dk_nrf52833-pinctrl.dtsi @@ -19,12 +19,17 @@ uart0_sleep: uart0_sleep { group1 { - psels = , - , + psels = , , ; low-power-enable; }; + + group2 { + psels = ; + low-power-enable; + bias-pull-up; + }; }; uart1_default: uart1_default { diff --git a/boards/nordic/nrf52833dk/nrf52833dk_nrf52833.dts b/boards/nordic/nrf52833dk/nrf52833dk_nrf52833.dts index d7f5b3ba0b92..098632f622b5 100644 --- a/boards/nordic/nrf52833dk/nrf52833dk_nrf52833.dts +++ b/boards/nordic/nrf52833dk/nrf52833dk_nrf52833.dts @@ -237,12 +237,12 @@ arduino_spi: &spi3 { boot_partition: partition@0 { label = "mcuboot"; - reg = <0x00000000 0xC000>; + reg = <0x00000000 0xc000>; }; slot0_partition: partition@c000 { label = "image-0"; - reg = <0x0000C000 0x37000>; + reg = <0x0000c000 0x37000>; }; slot1_partition: partition@43000 { @@ -252,7 +252,7 @@ arduino_spi: &spi3 { storage_partition: partition@7a000 { label = "storage"; - reg = <0x0007A000 0x00006000>; + reg = <0x0007a000 0x00006000>; }; }; }; diff --git a/boards/nordic/nrf52840dk/Kconfig.defconfig b/boards/nordic/nrf52840dk/Kconfig.defconfig index 96aa4159c27e..f7f8c8e47090 100644 --- a/boards/nordic/nrf52840dk/Kconfig.defconfig +++ b/boards/nordic/nrf52840dk/Kconfig.defconfig @@ -8,4 +8,11 @@ if BOARD_NRF52840DK config HW_STACK_PROTECTION default ARCH_HAS_STACK_PROTECTION +if NORDIC_QSPI_NOR + +config NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE + default 4096 if MCUBOOT || BOOTLOADER_MCUBOOT + +endif # NORDIC_QSPI_NOR + endif # BOARD_NRF52840DK diff --git a/boards/nordic/nrf52840dk/doc/index.rst b/boards/nordic/nrf52840dk/doc/index.rst index 1c7c30449f9e..c9fc919764e5 100644 --- a/boards/nordic/nrf52840dk/doc/index.rst +++ b/boards/nordic/nrf52840dk/doc/index.rst @@ -71,6 +71,10 @@ built, flashed, and debugged in the usual way. See :ref:`build_an_application` and :ref:`application_run` for more details on building and running. +The nRF52840 DK supports programming and debugging external boards with +nRF51 Series or nRF52 Series System on Chip (SoC)s. For more information, +see the documentation on `nRF52840 DK Debug output`_. + Flashing ======== @@ -190,5 +194,6 @@ References .. _nRF52840 DK website: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52840-DK .. _nRF52840 Product Specification: https://docs.nordicsemi.com/bundle/ps_nrf52840/page/keyfeatures_html5.html .. _nRF52840 DK Hardware guide: https://docs.nordicsemi.com/bundle/ug_nrf52840_dk/page/UG/dk/intro.html +.. _nRF52840 DK Debug output: https://docs.nordicsemi.com/bundle/ug_nrf52840_dk/page/UG/dk/hw_debug_out.html .. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html .. _nRF52811 website: https://www.nordicsemi.com/Products/Low-power-short-range-wireless/nRF52811 diff --git a/boards/nordic/nrf52840dk/nrf52840dk_nrf52811-pinctrl.dtsi b/boards/nordic/nrf52840dk/nrf52840dk_nrf52811-pinctrl.dtsi index c3706043f4f4..ad768eb029c2 100644 --- a/boards/nordic/nrf52840dk/nrf52840dk_nrf52811-pinctrl.dtsi +++ b/boards/nordic/nrf52840dk/nrf52840dk_nrf52811-pinctrl.dtsi @@ -19,12 +19,17 @@ uart0_sleep: uart0_sleep { group1 { - psels = , - , + psels = , , ; low-power-enable; }; + + group2 { + psels = ; + low-power-enable; + bias-pull-up; + }; }; i2c0_default: i2c0_default { diff --git a/boards/nordic/nrf52840dk/nrf52840dk_nrf52811.dts b/boards/nordic/nrf52840dk/nrf52840dk_nrf52811.dts index 35a9e6403012..6dc7731389f8 100644 --- a/boards/nordic/nrf52840dk/nrf52840dk_nrf52811.dts +++ b/boards/nordic/nrf52840dk/nrf52840dk_nrf52811.dts @@ -175,7 +175,7 @@ slot0_partition: partition@c000 { label = "image-0"; - reg = <0x0000C000 0xe000>; + reg = <0x0000c000 0xe000>; }; slot1_partition: partition@1a000 { diff --git a/boards/nordic/nrf52840dk/nrf52840dk_nrf52840-pinctrl.dtsi b/boards/nordic/nrf52840dk/nrf52840dk_nrf52840-pinctrl.dtsi index 152a6e95b5f8..39dacdcb77b5 100644 --- a/boards/nordic/nrf52840dk/nrf52840dk_nrf52840-pinctrl.dtsi +++ b/boards/nordic/nrf52840dk/nrf52840dk_nrf52840-pinctrl.dtsi @@ -19,12 +19,17 @@ uart0_sleep: uart0_sleep { group1 { - psels = , - , + psels = , , ; low-power-enable; }; + + group2 { + psels = ; + low-power-enable; + bias-pull-up; + }; }; uart1_default: uart1_default { diff --git a/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840-pinctrl.dtsi b/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840-pinctrl.dtsi index cf2b8523b8e0..5b5460ab4cfa 100644 --- a/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840-pinctrl.dtsi +++ b/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840-pinctrl.dtsi @@ -19,12 +19,17 @@ uart0_sleep: uart0_sleep { group1 { - psels = , - , + psels = , , ; low-power-enable; }; + + group2 { + psels = ; + low-power-enable; + bias-pull-up; + }; }; i2c0_default: i2c0_default { diff --git a/boards/nordic/nrf52dk/nrf52dk_nrf52805-pinctrl.dtsi b/boards/nordic/nrf52dk/nrf52dk_nrf52805-pinctrl.dtsi index 00d60d2cbecc..ba8f5c146817 100644 --- a/boards/nordic/nrf52dk/nrf52dk_nrf52805-pinctrl.dtsi +++ b/boards/nordic/nrf52dk/nrf52dk_nrf52805-pinctrl.dtsi @@ -47,11 +47,16 @@ uart0_sleep: uart0_sleep { group1 { - psels = , - , + psels = , , ; low-power-enable; }; + + group2 { + psels = ; + low-power-enable; + bias-pull-up; + }; }; }; diff --git a/boards/nordic/nrf52dk/nrf52dk_nrf52805.dts b/boards/nordic/nrf52dk/nrf52dk_nrf52805.dts index 8f1ff01454dd..a27bae1c72cf 100644 --- a/boards/nordic/nrf52dk/nrf52dk_nrf52805.dts +++ b/boards/nordic/nrf52dk/nrf52dk_nrf52805.dts @@ -150,7 +150,7 @@ slot0_partition: partition@c000 { label = "image-0"; - reg = <0x0000C000 0xe000>; + reg = <0x0000c000 0xe000>; }; slot1_partition: partition@1a000 { diff --git a/boards/nordic/nrf52dk/nrf52dk_nrf52810-pinctrl.dtsi b/boards/nordic/nrf52dk/nrf52dk_nrf52810-pinctrl.dtsi index bec21acc20f5..7b53da139756 100644 --- a/boards/nordic/nrf52dk/nrf52dk_nrf52810-pinctrl.dtsi +++ b/boards/nordic/nrf52dk/nrf52dk_nrf52810-pinctrl.dtsi @@ -15,12 +15,17 @@ uart0_sleep: uart0_sleep { group1 { - psels = , - , + psels = , , ; low-power-enable; }; + + group2 { + psels = ; + low-power-enable; + bias-pull-up; + }; }; i2c0_default: i2c0_default { diff --git a/boards/nordic/nrf52dk/nrf52dk_nrf52810.dts b/boards/nordic/nrf52dk/nrf52dk_nrf52810.dts index e9a50ea9ac50..8c72a1b5fa30 100644 --- a/boards/nordic/nrf52dk/nrf52dk_nrf52810.dts +++ b/boards/nordic/nrf52dk/nrf52dk_nrf52810.dts @@ -152,7 +152,7 @@ slot0_partition: partition@c000 { label = "image-0"; - reg = <0x0000C000 0xe000>; + reg = <0x0000c000 0xe000>; }; slot1_partition: partition@1a000 { diff --git a/boards/nordic/nrf52dk/nrf52dk_nrf52832-pinctrl.dtsi b/boards/nordic/nrf52dk/nrf52dk_nrf52832-pinctrl.dtsi index 15a9920877d6..2eaa58687393 100644 --- a/boards/nordic/nrf52dk/nrf52dk_nrf52832-pinctrl.dtsi +++ b/boards/nordic/nrf52dk/nrf52dk_nrf52832-pinctrl.dtsi @@ -15,12 +15,17 @@ uart0_sleep: uart0_sleep { group1 { - psels = , - , + psels = , , ; low-power-enable; }; + + group2 { + psels = ; + low-power-enable; + bias-pull-up; + }; }; i2c0_default: i2c0_default { diff --git a/boards/nordic/nrf52dk/nrf52dk_nrf52832.dts b/boards/nordic/nrf52dk/nrf52dk_nrf52832.dts index 2f7a08013580..9f1b167c2165 100644 --- a/boards/nordic/nrf52dk/nrf52dk_nrf52832.dts +++ b/boards/nordic/nrf52dk/nrf52dk_nrf52832.dts @@ -239,7 +239,7 @@ arduino_spi: &spi2 { slot0_partition: partition@c000 { label = "image-0"; - reg = <0x0000C000 0x37000>; + reg = <0x0000c000 0x37000>; }; slot1_partition: partition@43000 { diff --git a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_common-pinctrl.dtsi b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_common-pinctrl.dtsi index 6f835be43c6b..7201a806fe44 100644 --- a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_common-pinctrl.dtsi +++ b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_common-pinctrl.dtsi @@ -45,12 +45,17 @@ uart0_sleep: uart0_sleep { group1 { - psels = , - , + psels = , , ; low-power-enable; }; + + group2 { + psels = ; + low-power-enable; + bias-pull-up; + }; }; uart1_default: uart1_default { diff --git a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_ns.dts b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_ns.dts index 8b906eb1c9a2..577fdbd13f87 100644 --- a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_ns.dts +++ b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_ns.dts @@ -5,7 +5,7 @@ */ /dts-v1/; -#include +#include #include "nrf5340_audio_dk_nrf5340_cpuapp_common.dtsi" / { diff --git a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpunet-pinctrl.dtsi b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpunet-pinctrl.dtsi index 869788437579..2af3c58d2064 100644 --- a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpunet-pinctrl.dtsi +++ b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpunet-pinctrl.dtsi @@ -19,12 +19,17 @@ uart0_sleep: uart0_sleep { group1 { - psels = , - , + psels = , , ; low-power-enable; }; + + group2 { + psels = ; + low-power-enable; + bias-pull-up; + }; }; spi0_default: spi0_default { diff --git a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpunet.dts b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpunet.dts index 71c19f48e09a..11d75635e32e 100644 --- a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpunet.dts +++ b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpunet.dts @@ -61,6 +61,7 @@ arduino_spi: &spi0 { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + ranges; boot_partition: partition@0 { label = "mcuboot"; @@ -69,12 +70,12 @@ arduino_spi: &spi0 { slot0_partition: partition@c000 { label = "image-0"; - reg = <0x0000C000 0x12000>; + reg = <0x0000c000 0x12000>; }; slot1_partition: partition@1e000 { label = "image-1"; - reg = <0x0001E000 0x12000>; + reg = <0x0001e000 0x12000>; }; storage_partition: partition@3a000 { diff --git a/boards/nordic/nrf5340dk/Kconfig.defconfig b/boards/nordic/nrf5340dk/Kconfig.defconfig index 497113310bfa..7cfbc6731930 100644 --- a/boards/nordic/nrf5340dk/Kconfig.defconfig +++ b/boards/nordic/nrf5340dk/Kconfig.defconfig @@ -6,6 +6,13 @@ config HW_STACK_PROTECTION default ARCH_HAS_STACK_PROTECTION +if NORDIC_QSPI_NOR + +config NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE + default 4096 if MCUBOOT || BOOTLOADER_MCUBOOT + +endif # NORDIC_QSPI_NOR + if BOARD_NRF5340DK_NRF5340_CPUAPP || BOARD_NRF5340DK_NRF5340_CPUAPP_NS # Code Partition: diff --git a/boards/nordic/nrf5340dk/doc/index.rst b/boards/nordic/nrf5340dk/doc/index.rst index e896701d5563..91e7fa0ac1ba 100644 --- a/boards/nordic/nrf5340dk/doc/index.rst +++ b/boards/nordic/nrf5340dk/doc/index.rst @@ -102,8 +102,8 @@ nRF5340 IDAU may configure bus accesses by the nRF5340 network core to have Secure attribute set; the latter allows to build and run Secure only applications on the nRF5340 SoC. -Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg| -============================================================================= +Building Secure/Non-Secure Zephyr applications with Arm® TrustZone® +=================================================================== Applications on the nRF5340 may contain a Secure and a Non-Secure firmware image for the application core. The Secure image can be built using either diff --git a/boards/nordic/nrf5340dk/nrf5340_cpuapp_common-pinctrl.dtsi b/boards/nordic/nrf5340dk/nrf5340_cpuapp_common-pinctrl.dtsi index ed1f278f5d1b..a5d70c602310 100644 --- a/boards/nordic/nrf5340dk/nrf5340_cpuapp_common-pinctrl.dtsi +++ b/boards/nordic/nrf5340dk/nrf5340_cpuapp_common-pinctrl.dtsi @@ -34,12 +34,17 @@ uart0_sleep: uart0_sleep { group1 { - psels = , - , + psels = , , ; low-power-enable; }; + + group2 { + psels = ; + low-power-enable; + bias-pull-up; + }; }; pwm0_default: pwm0_default { diff --git a/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp_ns.dts b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp_ns.dts index dbd4a770be3d..453d62507863 100644 --- a/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp_ns.dts +++ b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp_ns.dts @@ -5,7 +5,7 @@ */ /dts-v1/; -#include +#include #include "nrf5340_cpuapp_common.dtsi" / { diff --git a/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpunet-pinctrl.dtsi b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpunet-pinctrl.dtsi index 30f638a7eae7..a8f5c5f357d3 100644 --- a/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpunet-pinctrl.dtsi +++ b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpunet-pinctrl.dtsi @@ -19,12 +19,17 @@ uart0_sleep: uart0_sleep { group1 { - psels = , - , + psels = , , ; low-power-enable; }; + + group2 { + psels = ; + low-power-enable; + bias-pull-up; + }; }; i2c0_default: i2c0_default { diff --git a/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpunet.dts b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpunet.dts index e3899d435d7f..69c9cd860730 100644 --- a/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpunet.dts +++ b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpunet.dts @@ -80,6 +80,7 @@ arduino_spi: &spi0 { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + ranges; boot_partition: partition@0 { label = "mcuboot"; @@ -88,7 +89,7 @@ arduino_spi: &spi0 { slot0_partition: partition@c000 { label = "image-0"; - reg = <0x0000C000 0x17000>; + reg = <0x0000c000 0x17000>; }; slot1_partition: partition@23000 { diff --git a/boards/nordic/nrf54h20dk/Kconfig.defconfig b/boards/nordic/nrf54h20dk/Kconfig.defconfig index 069ed7b6eba6..42758666c55d 100644 --- a/boards/nordic/nrf54h20dk/Kconfig.defconfig +++ b/boards/nordic/nrf54h20dk/Kconfig.defconfig @@ -17,10 +17,13 @@ config ROM_START_OFFSET if !USE_DT_CODE_PARTITION +DT_CHOSEN_Z_FLASH := zephyr,flash + # Application core firmware must start at this offset when not using MCUboot. # However, the default 'zephyr,code-partition' in DT is set for MCUboot. config FLASH_LOAD_OFFSET - default $(dt_nodelabel_reg_addr_hex,cpuapp_boot_partition) + default $(sub_hex, $(dt_nodelabel_reg_addr_hex,cpuapp_boot_partition), \ + $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))) # This is meant to span 'cpuapp_boot_partition' and 'cpuapp_slot0_partition' # in the default memory map. diff --git a/boards/nordic/nrf54h20dk/board.cmake b/boards/nordic/nrf54h20dk/board.cmake index b9383042b0c7..cabb050253e9 100644 --- a/boards/nordic/nrf54h20dk/board.cmake +++ b/boards/nordic/nrf54h20dk/board.cmake @@ -20,6 +20,7 @@ if(CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUPPR OR CONFIG_BOARD_NRF54H20DK_NRF54H20_C set(JLINKSCRIPTFILE ${CMAKE_CURRENT_LIST_DIR}/support/nrf54h20_cpuflpr.JLinkScript) endif() - board_runner_args(jlink "--device=RISC-V" "--speed=4000" "-if SW" "--tool-opt=-jlinkscriptfile ${JLINKSCRIPTFILE}") + # Workaround: Use device nRF54L15_RV32 until nRF54H20_RV32 is defined. + board_runner_args(jlink "--device=nRF54L15_RV32" "--speed=4000" "--tool-opt=-jlinkscriptfile ${JLINKSCRIPTFILE}") include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) endif() diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-common.dtsi b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-common.dtsi index b0cb997de947..72d78b9c739c 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-common.dtsi +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-common.dtsi @@ -9,13 +9,8 @@ #include "nrf54h20dk_nrf54h20-pinctrl.dtsi" &hfxo { - status = "okay"; accuracy-ppm = <30>; }; -&lfxo { - status = "okay"; -}; - /* Get a node label for wi-fi spi to use in shield files */ wifi_spi: &spi130 {}; diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map.dtsi b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map.dtsi index fa1b601974b0..675e4555ac26 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map.dtsi +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map.dtsi @@ -130,6 +130,7 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + ranges; cpuapp_boot_partition: partition@30000 { reg = <0x30000 DT_SIZE_K(64)>; diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-pinctrl.dtsi b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-pinctrl.dtsi index 0e2ab313df9b..3bf93c920e57 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-pinctrl.dtsi +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-pinctrl.dtsi @@ -19,8 +19,13 @@ /omit-if-no-ref/ uart120_sleep: uart120_sleep { group1 { low-power-enable; - psels = , - ; + psels = ; + }; + + group2 { + low-power-enable; + bias-pull-up; + psels = ; }; }; @@ -40,11 +45,16 @@ /omit-if-no-ref/ uart135_sleep: uart135_sleep { group1 { low-power-enable; - psels = , - , + psels = , , ; }; + + group2 { + psels = ; + low-power-enable; + bias-pull-up; + }; }; /omit-if-no-ref/ uart136_default: uart136_default { @@ -63,11 +73,16 @@ /omit-if-no-ref/ uart136_sleep: uart136_sleep { group1 { low-power-enable; - psels = , - , + psels = , , ; }; + + group2 { + psels = ; + low-power-enable; + bias-pull-up; + }; }; /omit-if-no-ref/ exmif_default: exmif_default { diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts index 5e13af28c2ba..c534e1bd91c8 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts @@ -44,6 +44,7 @@ watchdog0 = &wdt010; mcuboot-button0 = &button0; mcuboot-led0 = &led0; + rtt-custom-section = &cpuapp_tcm_region; }; buttons { @@ -219,9 +220,10 @@ slot3_partition: &cpurad_slot1_partition { memory-regions = <&cpuapp_dma_region>; }; +/* Leave one channel for CPURAD */ &gpiote130 { status = "okay"; - owned-channels = <0 1 2 3 4 5 6 7>; + owned-channels = <0 1 2 3 4 5 6>; }; &gpio0 { @@ -321,6 +323,14 @@ zephyr_udc0: &usbhs { pinctrl-names = "default"; }; +&hfxo { + status = "okay"; +}; + +&lfxo { + status = "okay"; +}; + &pwm130 { status = "okay"; pinctrl-0 = <&pwm130_default>; @@ -334,26 +344,24 @@ zephyr_udc0: &usbhs { status = "okay"; }; -/* Trim this RAM block for power management related features. */ &cpuapp_ram0 { - reg = <0x22000000 (DT_SIZE_K(32) - 256)>; - ranges = <0x0 0x22000000 (0x8000 - 0x100)>; -}; + cpuapp_tcm_region: cpuapp_ram0@0 { + compatible = "zephyr,memory-region"; + reg = <0x00000000 (DT_SIZE_K(32) - 256)>; + zephyr,memory-region = "APP_RAM0"; + }; -/ { - soc { - /* cache control functions - must be executed from local SRAM */ - pm_ramfunc: cpuapp_s2ram@22007f00 { - compatible = "zephyr,memory-region", "mmio-sram"; - reg = <0x22007f00 192>; - zephyr,memory-region = "PMLocalRamfunc"; - }; + /* cache control functions - must be executed from local SRAM */ + pm_ramfunc: cpuapp_s2ram@7f00 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x00007f00 192>; + zephyr,memory-region = "PMLocalRamfunc"; + }; - /* run-time common S2RAM cpu context RAM */ - pm_s2ram: cpuapp_s2ram@22007fe0 { - compatible = "zephyr,memory-region", "mmio-sram"; - reg = <0x22007fe0 32>; - zephyr,memory-region = "pm_s2ram_context"; - }; + /* run-time common S2RAM cpu context RAM */ + pm_s2ram: cpuapp_s2ram@7fe0 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x00007fe0 32>; + zephyr,memory-region = "pm_s2ram_context"; }; }; diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts index d5fea020431f..cf88e536d43c 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts @@ -95,6 +95,14 @@ slot1_partition: &cpurad_slot1_partition { status = "okay"; }; +&hfxo { + status = "okay"; +}; + +&lfxo { + status = "okay"; +}; + &uart135 { status = "okay"; memory-regions = <&cpurad_dma_region>; @@ -135,3 +143,12 @@ zephyr_udc0: &usbhs { }; }; }; + +/* For coex-grant GPIO */ +&gpiote130 { + owned-channels = <7>; +}; + +&lfclk { + status = "okay"; +}; diff --git a/boards/nordic/nrf54l15dk/Kconfig.defconfig b/boards/nordic/nrf54l15dk/Kconfig.defconfig index f57b30c2c42d..70bbff4b47f8 100644 --- a/boards/nordic/nrf54l15dk/Kconfig.defconfig +++ b/boards/nordic/nrf54l15dk/Kconfig.defconfig @@ -4,6 +4,13 @@ config HW_STACK_PROTECTION default ARCH_HAS_STACK_PROTECTION +if SPI_NOR + +config SPI_NOR_FLASH_LAYOUT_PAGE_SIZE + default 4096 if MCUBOOT || BOOTLOADER_MCUBOOT + +endif # SPI_NOR + if BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS || BOARD_NRF54L15DK_NRF54L10_CPUAPP_NS config BOARD_NRF54L15DK diff --git a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l10_cpuapp.dts b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l10_cpuapp.dts index e3ee6b5434fc..c94d2a178133 100644 --- a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l10_cpuapp.dts +++ b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l10_cpuapp.dts @@ -26,4 +26,4 @@ }; /* Include default memory partition configuration file */ -#include +#include diff --git a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l10_cpuapp_ns.dts b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l10_cpuapp_ns.dts index af0d14163345..5ed2c41c29cb 100644 --- a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l10_cpuapp_ns.dts +++ b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l10_cpuapp_ns.dts @@ -8,7 +8,7 @@ #define USE_NON_SECURE_ADDRESS_MAP 1 -#include +#include #include "nrf54l_05_10_15_cpuapp_common.dtsi" / { @@ -28,81 +28,10 @@ }; }; -/ { - /* - * Default SRAM planning when building for nRF54L10 with ARM TrustZone-M support. - * - Lowest 72 kB SRAM allocated to Secure image (sram0_s). - * - Upper 72 kB SRAM allocated to Non-Secure image (sram0_ns). - * - * nRF54L10 has 192 kB of volatile memory (SRAM) but the last 42kB are reserved for - * the FLPR MCU. - * This static layout needs to be the same with the upstream TF-M layout in the - * header flash_layout.h of the relevant platform. Any updates in the layout - * needs to happen both in the flash_layout.h and in this file at the same time. - */ - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram0_s: image_s@20000000 { - /* Secure image memory */ - reg = <0x20000000 DT_SIZE_K(72)>; - }; - - sram0_ns: image_ns@20012000 { - /* Non-Secure image memory */ - reg = <0x20012000 DT_SIZE_K(72)>; - }; - }; -}; - -&cpuapp_rram { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* nRF54L10 has 1012 kB of non volatile memory (RRAM) but the - * last 62kB are reserved for the FLPR MCU. - * - * This static layout needs to be the same with the upstream TF-M layout in the - * header flash_layout.h of the relevant platform. Any updates in the layout - * needs to happen both in the flash_layout.h and in this file at the same time. - */ - slot0_partition: partition@0 { - label = "image-0"; - reg = <0x0000000 DT_SIZE_K(384)>; - }; - - tfm_ps_partition: partition@60000 { - label = "tfm-ps"; - reg = <0x00060000 DT_SIZE_K(16)>; - }; - - tfm_its_partition: partition@64000 { - label = "tfm-its"; - reg = <0x00064000 DT_SIZE_K(16)>; - }; - - tfm_otp_partition: partition@68000 { - label = "tfm-otp"; - reg = <0x00068000 DT_SIZE_K(8)>; - }; - - slot0_ns_partition: partition@6A000 { - label = "image-0-nonsecure"; - reg = <0x0006A000 DT_SIZE_K(494)>; - }; - - storage_partition: partition@E5800 { - label = "storage"; - reg = <0x000E5800 DT_SIZE_K(32)>; - }; - }; -}; - &uart30 { /* Disable so that TF-M can use this UART */ status = "disabled"; }; + +/* Include default memory partition configuration file */ +#include diff --git a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp.dts b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp.dts index 6e6629025612..6ece56bf004a 100644 --- a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp.dts +++ b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp.dts @@ -20,4 +20,4 @@ }; /* Include default memory partition configuration file */ -#include +#include diff --git a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp_ns.dts b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp_ns.dts index f78a1f864e2f..196245a12dbc 100644 --- a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp_ns.dts +++ b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp_ns.dts @@ -8,7 +8,7 @@ #define USE_NON_SECURE_ADDRESS_MAP 1 -#include +#include #include "nrf54l_05_10_15_cpuapp_common.dtsi" / { @@ -28,35 +28,6 @@ }; }; -/ { - /* - * Default SRAM planning when building for nRF54L15 with ARM TrustZone-M support - * - Lowest 80 kB SRAM allocated to Secure image (sram0_s). - * - Upper 80 kB SRAM allocated to Non-Secure image (sram0_ns). - * - * nRF54L15 has 256 kB of volatile memory (SRAM) but the last 96kB are reserved for - * the FLPR MCU. - * This static layout needs to be the same with the upstream TF-M layout in the - * header flash_layout.h of the relevant platform. Any updates in the layout - * needs to happen both in the flash_layout.h and in this file at the same time. - */ - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram0_s: image_s@20000000 { - /* Secure image memory */ - reg = <0x20000000 DT_SIZE_K(80)>; - }; - - sram0_ns: image_ns@20014000 { - /* Non-Secure image memory */ - reg = <0x20014000 DT_SIZE_K(80)>; - }; - }; -}; - &uart30 { /* Disable so that TF-M can use this UART */ status = "disabled"; @@ -68,4 +39,4 @@ }; /* Include default memory partition configuration file */ -#include +#include diff --git a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuflpr.dts b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuflpr.dts index eae0b605eb4b..58bdd2bf59bf 100644 --- a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuflpr.dts +++ b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuflpr.dts @@ -38,6 +38,7 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + ranges; cpuflpr_code_partition: partition@0 { label = "image-0"; diff --git a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l_05_10_15-pinctrl.dtsi b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l_05_10_15-pinctrl.dtsi index 6f36b4e71129..54c2f0241ad0 100644 --- a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l_05_10_15-pinctrl.dtsi +++ b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l_05_10_15-pinctrl.dtsi @@ -19,12 +19,17 @@ /omit-if-no-ref/ uart20_sleep: uart20_sleep { group1 { - psels = , - , + psels = , , ; low-power-enable; }; + + group2 { + psels = ; + low-power-enable; + bias-pull-up; + }; }; /omit-if-no-ref/ uart30_default: uart30_default { diff --git a/boards/nordic/nrf54l15tag/Kconfig b/boards/nordic/nrf54l15tag/Kconfig new file mode 100644 index 000000000000..e2f267bb829e --- /dev/null +++ b/boards/nordic/nrf54l15tag/Kconfig @@ -0,0 +1,30 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +# nRF54L15 TAG board configuration + +if BOARD_NRF54L15TAG_NRF54L15_CPUAPP_NS + +DT_NRF_MPC := $(dt_nodelabel_path,nrf_mpc) + +config NRF_TRUSTZONE_FLASH_REGION_SIZE + hex + default $(dt_node_int_prop_hex,$(DT_NRF_MPC),override-granularity) + help + This defines the flash region size from the TrustZone perspective. + It is used when configuring the TrustZone and when setting alignments + requirements for the partitions. + This abstraction allows us to configure TrustZone without depending + on peripheral-specific symbols. + +config NRF_TRUSTZONE_RAM_REGION_SIZE + hex + default $(dt_node_int_prop_hex,$(DT_NRF_MPC),override-granularity) + help + This defines the RAM region size from the TrustZone perspective. + It is used when configuring the TrustZone and when setting alignments + requirements for the partitions. + This abstraction allows us to configure TrustZone without depending + on peripheral specific symbols. + +endif # BOARD_NRF54L15TAG_NRF54L15_CPUAPP_NS diff --git a/boards/nordic/nrf54l15tag/Kconfig.defconfig b/boards/nordic/nrf54l15tag/Kconfig.defconfig new file mode 100644 index 000000000000..20fad4b04be6 --- /dev/null +++ b/boards/nordic/nrf54l15tag/Kconfig.defconfig @@ -0,0 +1,27 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config HW_STACK_PROTECTION + default ARCH_HAS_STACK_PROTECTION + +if SPI_NOR + +config SPI_NOR_FLASH_LAYOUT_PAGE_SIZE + default 4096 if MCUBOOT || BOOTLOADER_MCUBOOT + +endif # SPI_NOR + +if BOARD_NRF54L15TAG_NRF54L15_CPUAPP_NS + +config BOARD_NRF54L15TAG + select USE_DT_CODE_PARTITION + +config HAS_BT_CTLR + default BT + +# By default, if we build for a Non-Secure version of the board, +# enable building with TF-M as the Secure Execution Environment. +config BUILD_WITH_TFM + default y + +endif # BOARD_NRF54L15TAG_NRF54L15_CPUAPP_NS diff --git a/boards/nordic/nrf54l15tag/Kconfig.nrf54l15tag b/boards/nordic/nrf54l15tag/Kconfig.nrf54l15tag new file mode 100644 index 000000000000..48a6fb2c79f0 --- /dev/null +++ b/boards/nordic/nrf54l15tag/Kconfig.nrf54l15tag @@ -0,0 +1,8 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF54L15TAG + select SOC_NRF54L15_CPUAPP if BOARD_NRF54L15TAG_NRF54L15_CPUAPP || \ + BOARD_NRF54L15TAG_NRF54L15_CPUAPP_NS + select SOC_NRF54L15_CPUFLPR if BOARD_NRF54L15TAG_NRF54L15_CPUFLPR || \ + BOARD_NRF54L15TAG_NRF54L15_CPUFLPR_XIP diff --git a/boards/nordic/nrf54l15tag/board.cmake b/boards/nordic/nrf54l15tag/board.cmake new file mode 100644 index 000000000000..8750e32d0bb4 --- /dev/null +++ b/boards/nordic/nrf54l15tag/board.cmake @@ -0,0 +1,19 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_SOC_NRF54L15_CPUAPP) + board_runner_args(jlink "--device=nRF54L15_M33" "--speed=4000") +elseif(CONFIG_SOC_NRF54L15_CPUFLPR) + board_runner_args(jlink "--device=nRF54L15_RV32") +endif() + +if(CONFIG_TRUSTED_EXECUTION_NONSECURE) + set(TFM_PUBLIC_KEY_FORMAT "full") +endif() + +if(CONFIG_TFM_FLASH_MERGED_BINARY) + set_property(TARGET runners_yaml_props_target PROPERTY hex_file tfm_merged.hex) +endif() + +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/nordic/nrf54l15tag/board.yml b/boards/nordic/nrf54l15tag/board.yml new file mode 100644 index 000000000000..c482665487be --- /dev/null +++ b/boards/nordic/nrf54l15tag/board.yml @@ -0,0 +1,48 @@ +board: + name: nrf54l15tag + full_name: nRF54L15 TAG + vendor: nordic + socs: + - name: nrf54l15 + variants: + - name: xip + cpucluster: cpuflpr + - name: ns + cpucluster: cpuapp +runners: + run_once: + '--recover': + - runners: + - nrfjprog + - nrfutil + run: first + groups: + - boards: + - nrf54l15tag/nrf54l15/cpuapp + - nrf54l15tag/nrf54l15/cpuapp/ns + - nrf54l15tag/nrf54l15/cpuflpr + - nrf54l15tag/nrf54l15/cpuflpr/xip + '--erase': + - runners: + - nrfjprog + - jlink + - nrfutil + run: first + groups: + - boards: + - nrf54l15tag/nrf54l15/cpuapp + - nrf54l15tag/nrf54l15/cpuapp/ns + - nrf54l15tag/nrf54l15/cpuflpr + - nrf54l15tag/nrf54l15/cpuflpr/xip + '--reset': + - runners: + - nrfjprog + - jlink + - nrfutil + run: last + groups: + - boards: + - nrf54l15tag/nrf54l15/cpuapp + - nrf54l15tag/nrf54l15/cpuapp/ns + - nrf54l15tag/nrf54l15/cpuflpr + - nrf54l15tag/nrf54l15/cpuflpr/xip diff --git a/boards/nordic/nrf54l15tag/doc/img/nrf54l15tag.webp b/boards/nordic/nrf54l15tag/doc/img/nrf54l15tag.webp new file mode 100644 index 000000000000..49e4ab27d06e Binary files /dev/null and b/boards/nordic/nrf54l15tag/doc/img/nrf54l15tag.webp differ diff --git a/boards/nordic/nrf54l15tag/doc/img/nrf54l15tag_debug.webp b/boards/nordic/nrf54l15tag/doc/img/nrf54l15tag_debug.webp new file mode 100644 index 000000000000..a3a0ce478f49 Binary files /dev/null and b/boards/nordic/nrf54l15tag/doc/img/nrf54l15tag_debug.webp differ diff --git a/boards/nordic/nrf54l15tag/doc/index.rst b/boards/nordic/nrf54l15tag/doc/index.rst new file mode 100644 index 000000000000..7fa73f5346a8 --- /dev/null +++ b/boards/nordic/nrf54l15tag/doc/index.rst @@ -0,0 +1,85 @@ +.. zephyr:board:: nrf54l15tag + +Overview +******** + +The nRF54L15 TAG is a hardware development platform used to design and develop applications for the +nrf54L15 SoC. + +Hardware +******** + +The nRF54L15 TAG has a number of exposed pins which can be used for application specific purposes. +The following is the default availability (no optional components mounted by user). + +* P0.01 Available +* P0.02 Available +* P0.04 Available +* P1.02 Available +* P1.03 Available +* P1.11 SCL (i2c21) +* P1.12 SDA (i2c21) +* P1.13 Available +* P1.14 Available +* P2.05 Reserved +* P2.06 Available +* P2.07 Available + +.. note:: By default the ANT1 antenna is connected to the SoC using GPIO Hogs. + +Supported Features +****************** + +.. zephyr:board-supported-hw:: + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +The nRF54L15 TAG is programmed and debugged using the onboard debugger of an nRF54L DK as +depicted below: + +.. figure:: img/nrf54l15tag_debug.webp + :align: center + :alt: nRF54L15 TAG debugging + + nRF54L15 TAG debugging (Credit: Nordic Semiconductor) + +Once the nRF54L15 TAG is inserted into the DK's ``DEBUG OUT`` header, the nRF54L DK's onboard +debugger is rerouted from the DK's nRF54L15 SoC to the TAG's nRF54L15 SoC. Once powered, the TAG's +nRF54L15 SoC is then programmed and debugged just like the nRF54L15 SoC of an nRF54L DK, see +:zephyr:board:`nrf54l15dk`. + +.. warning:: + + Do not apply 3.3V to ``VDD SWD0`` or the ``VDD`` on the TAG in general if a coin cell battery + is inserted. + +The nRF54L15 TAG is not powered from the ``DEBUG OUT`` header by default. To power the nRF54L15 +TAG, either insert a CR2032 coin cell battery into its battery holder, **OR** apply 3.3V to the +``VDD SWD0`` pin on the nRF54L DK to power the TAG externally. + +Using an nRF54L15 DK, the DK can be configured to set VDD to 3.3V, and a jumper between any +of the DK's ``VDDIO`` pins and the ``VDD SWD0`` pin can be connected. + +Console and logging +******************* + +To get console and logging output, enable Segger RTT using the :ref:`snippet-rtt-console` snippet: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nrf54l15tag/nrf54l15/cpuapp + :goals: build flash + :west-args: --snippet rtt-console + :compact: + +or enable the NUS service using the :ref:`snippet-nus-console` snippet: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nrf54l15tag/nrf54l15/cpuapp + :goals: build flash + :west-args: --snippet nus-console + :compact: diff --git a/boards/nordic/nrf54l15tag/nrf54l15tag_common.dtsi b/boards/nordic/nrf54l15tag/nrf54l15tag_common.dtsi new file mode 100644 index 000000000000..f197704373cb --- /dev/null +++ b/boards/nordic/nrf54l15tag/nrf54l15tag_common.dtsi @@ -0,0 +1,190 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + aliases { + led0 = &led1_blue; + sw0 = &button0; + }; + + leds { + compatible = "gpio-leds"; + + led1_red: led1_red { + gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; + label = "LED 1 red"; + }; + + led1_green: led1_green { + gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; + label = "LED 1 green"; + }; + + led1_blue: led1_blue { + gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; + label = "LED 1 blue"; + }; + + led2_red: led2_red { + status = "disabled"; + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + label = "LED 2 red"; + }; + + led2_green: led2_green { + status = "disabled"; + gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; + label = "LED 2 green"; + }; + + led2_blue: led2_blue { + status = "disabled"; + gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; + label = "LED 2 blue"; + }; + }; + + rgb_led_1: rgb_led_1 { + compatible = "leds-group-multicolor"; + + leds = <&led1_red>, + <&led1_green>, + <&led1_blue>; + + color-mapping = , + , + ; + }; + + rgb_led_2: rgb_led_2 { + status = "disabled"; + compatible = "leds-group-multicolor"; + + leds = <&led2_red>, + <&led2_green>, + <&led2_blue>; + + color-mapping = , + , + ; + }; + + buttons { + compatible = "gpio-keys"; + + button0: button0 { + gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 0"; + zephyr,code = ; + }; + + button1: button1 { + status = "disabled"; + gpios = <&gpio0 1 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 1"; + zephyr,code = ; + }; + }; + + sky13348: sky13348 { + compatible = "skyworks,sky13348"; + v1-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + v2-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + }; +}; + +&pinctrl { + i2c21_default: i2c21_default { + group1 { + psels = , + ; + }; + }; + + i2c21_sleep: i2c21_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; + + spi22_default: spi22_default { + group1 { + psels = , + , + ; + }; + }; + + spi22_sleep: spi22_sleep { + group1 { + psels = , + , + ; + low-power-enable; + }; + }; +}; + +&i2c21 { + pinctrl-0 = <&i2c21_default>; + pinctrl-1 = <&i2c21_sleep>; + pinctrl-names = "default", "sleep"; + zephyr,concat-buf-size = <256>; + clock-frequency = ; + + bme688: bme688@76 { + status = "disabled"; + compatible = "bosch,bme680"; + reg = <0x76>; + }; + + adxl367: adxl367@1d { + status = "disabled"; + compatible = "adi,adxl367"; + reg = <0x1d>; + }; +}; + +&spi22 { + pinctrl-0 = <&spi22_default>; + pinctrl-1 = <&spi22_sleep>; + pinctrl-names = "default", "sleep"; + overrun-character = <0x00>; + cs-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + + bmi270: bmi270@0 { + status = "disabled"; + compatible = "bosch,bmi270"; + reg = <0>; + spi-max-frequency = ; + irq-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpiote20 { + status = "okay"; +}; + +&gpiote30 { + status = "okay"; +}; diff --git a/boards/nordic/nrf54l15tag/nrf54l15tag_cpuapp_common.dtsi b/boards/nordic/nrf54l15tag/nrf54l15tag_cpuapp_common.dtsi new file mode 100644 index 000000000000..592a84ee751c --- /dev/null +++ b/boards/nordic/nrf54l15tag/nrf54l15tag_cpuapp_common.dtsi @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "nrf54l15tag_common.dtsi" + +/ { + chosen { + zephyr,flash-controller = &rram_controller; + zephyr,flash = &cpuapp_rram; + zephyr,ieee802154 = &ieee802154; + zephyr,boot-mode = &boot_mode0; + }; + + aliases { + mcuboot-led0 = &led1_blue; + mcuboot-button0 = &button0; + }; +}; + +&grtc { + owned-channels = <0 1 2 3 4 5 6 7 8 9 10 11>; + /* Channels 7-11 reserved for Zero Latency IRQs, 3-4 for FLPR */ + child-owned-channels = <3 4 7 8 9 10 11>; + status = "okay"; +}; + +&lfxo { + status = "okay"; + load-capacitors = "internal"; + load-capacitance-femtofarad = <9000>; +}; + +&hfxo { + status = "okay"; + load-capacitors = "internal"; + load-capacitance-femtofarad = <8000>; +}; + +&radio { + status = "okay"; +}; + +&ieee802154 { + status = "okay"; +}; + +&temp { + status = "okay"; +}; + +&clock { + status = "okay"; +}; + +®ulators { + status = "okay"; +}; + +&vregmain { + status = "okay"; + regulator-initial-mode = ; +}; + +&gpregret1 { + status = "okay"; + + boot_mode0: boot_mode@0 { + compatible = "zephyr,retention"; + status = "okay"; + reg = <0x0 0x1>; + }; +}; + +&adc { + status = "okay"; +}; + +&i2c21 { + status = "okay"; +}; + +&bme688 { + status = "okay"; +}; + +&adxl367 { + status = "okay"; +}; + +&spi22 { + status = "okay"; +}; + +&bmi270 { + status = "okay"; +}; + +/* Initially connect ANT1 to SoC */ +&gpio1 { + antenna_switch_v1 { + gpio-hog; + gpios = <9 GPIO_ACTIVE_HIGH>; + output-high; + }; + + antenna_switch_v2 { + gpio-hog; + gpios = <10 GPIO_ACTIVE_HIGH>; + output-low; + }; +}; diff --git a/boards/nordic/nrf54l15tag/nrf54l15tag_cpuflpr_common.dtsi b/boards/nordic/nrf54l15tag/nrf54l15tag_cpuflpr_common.dtsi new file mode 100644 index 000000000000..96c440092450 --- /dev/null +++ b/boards/nordic/nrf54l15tag/nrf54l15tag_cpuflpr_common.dtsi @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#include "nrf54l15tag_common.dtsi" + +/ { + chosen { + zephyr,code-partition = &cpuflpr_code_partition; + zephyr,flash = &cpuflpr_rram; + zephyr,sram = &cpuflpr_sram; + }; +}; + +&grtc { + owned-channels = <3 4>; + status = "okay"; +}; diff --git a/boards/nordic/nrf54l15tag/nrf54l15tag_nrf54l15_cpuapp.dts b/boards/nordic/nrf54l15tag/nrf54l15tag_nrf54l15_cpuapp.dts new file mode 100644 index 000000000000..e1ef8ccb4069 --- /dev/null +++ b/boards/nordic/nrf54l15tag/nrf54l15tag_nrf54l15_cpuapp.dts @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include + +#include "nrf54l15tag_cpuapp_common.dtsi" + +/ { + compatible = "nordic,nrf54l15tag_nrf54l15_cpuapp"; + model = "Nordic nRF54L15 TAG nRF54L15 Application MCU"; + + chosen { + zephyr,flash = &cpuapp_rram; + zephyr,sram = &cpuapp_sram; + zephyr,code-partition = &slot0_partition; + }; +}; + +&uicr { + nfct-pins-as-gpios; +}; diff --git a/boards/nordic/nrf54l15tag/nrf54l15tag_nrf54l15_cpuapp.yaml b/boards/nordic/nrf54l15tag/nrf54l15tag_nrf54l15_cpuapp.yaml new file mode 100644 index 000000000000..7e6152eb79f1 --- /dev/null +++ b/boards/nordic/nrf54l15tag/nrf54l15tag_nrf54l15_cpuapp.yaml @@ -0,0 +1,24 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +identifier: nrf54l15tag/nrf54l15/cpuapp +name: nRF54l15-TAG-nRF54l15-Application +type: mcu +arch: arm +toolchain: + - gnuarmemb + - zephyr +sysbuild: true +ram: 188 +flash: 664 +supported: + - adc + - counter + - dmic + - gpio + - i2c + - i2s + - pwm + - retained_mem + - spi + - watchdog diff --git a/boards/nordic/nrf54l15tag/nrf54l15tag_nrf54l15_cpuapp_defconfig b/boards/nordic/nrf54l15tag/nrf54l15tag_nrf54l15_cpuapp_defconfig new file mode 100644 index 000000000000..5d5bca8f9693 --- /dev/null +++ b/boards/nordic/nrf54l15tag/nrf54l15tag_nrf54l15_cpuapp_defconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_GPIO=y +CONFIG_ARM_MPU=y diff --git a/boards/nordic/nrf54l15tag/nrf54l15tag_nrf54l15_cpuapp_ns.dts b/boards/nordic/nrf54l15tag/nrf54l15tag_nrf54l15_cpuapp_ns.dts new file mode 100644 index 000000000000..9d17ea870c5c --- /dev/null +++ b/boards/nordic/nrf54l15tag/nrf54l15tag_nrf54l15_cpuapp_ns.dts @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#define USE_NON_SECURE_ADDRESS_MAP 1 + +#include +#include + +#include "nrf54l15tag_cpuapp_common.dtsi" + +/ { + compatible = "nordic,nrf54l15tag_nrf54l15-cpuapp"; + model = "Nordic nRF54L15 TAG nRF54L15 Application MCU"; + + /delete-node/ rng; + + psa_rng: psa-rng { + status = "okay"; + }; + + chosen { + zephyr,sram = &sram0_ns; + zephyr,code-partition = &slot0_ns_partition; + zephyr,entropy = &psa_rng; + }; +}; diff --git a/boards/nordic/nrf54l15tag/nrf54l15tag_nrf54l15_cpuapp_ns.yaml b/boards/nordic/nrf54l15tag/nrf54l15tag_nrf54l15_cpuapp_ns.yaml new file mode 100644 index 000000000000..dd1315aaeac2 --- /dev/null +++ b/boards/nordic/nrf54l15tag/nrf54l15tag_nrf54l15_cpuapp_ns.yaml @@ -0,0 +1,23 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +identifier: nrf54l15tag/nrf54l15/cpuapp/ns +name: nRF54l15-TAG-nRF54l15-Application-Non-Secure +type: mcu +arch: arm +toolchain: + - gnuarmemb + - zephyr +ram: 128 +flash: 512 +supported: + - adc + - counter + - gpio + - i2c + - i2s + - pwm + - spi + - watchdog +vendor: nordic +sysbuild: true diff --git a/boards/nordic/nrf54l15tag/nrf54l15tag_nrf54l15_cpuapp_ns_defconfig b/boards/nordic/nrf54l15tag/nrf54l15tag_nrf54l15_cpuapp_ns_defconfig new file mode 100644 index 000000000000..b1d9e1219343 --- /dev/null +++ b/boards/nordic/nrf54l15tag/nrf54l15tag_nrf54l15_cpuapp_ns_defconfig @@ -0,0 +1,31 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y +CONFIG_ARM_TRUSTZONE_M=y + +# This Board implies building Non-Secure firmware +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +# Don't enable the cache in the non-secure image as it is a +# secure-only peripheral on 54l +CONFIG_CACHE_MANAGEMENT=n +CONFIG_EXTERNAL_CACHE=n + +CONFIG_GPIO=y + +# Start SYSCOUNTER on driver init +CONFIG_NRF_GRTC_START_SYSCOUNTER=y + +# Disable TFM BL2 since it is not supported +CONFIG_TFM_BL2=n + +# No UART available for TF-M log output +CONFIG_TFM_LOG_LEVEL_SILENCE=y + +# The oscillators are configured as secure and cannot be configured +# from the non secure application directly. This needs to be set +# otherwise nrfx will try to configure them, resulting in a bus +# fault. +CONFIG_NRF_SKIP_CLOCK_CONFIG=y diff --git a/boards/nordic/nrf54l15tag/nrf54l15tag_nrf54l15_cpuflpr.dts b/boards/nordic/nrf54l15tag/nrf54l15tag_nrf54l15_cpuflpr.dts new file mode 100644 index 000000000000..d1e39d3e5d96 --- /dev/null +++ b/boards/nordic/nrf54l15tag/nrf54l15tag_nrf54l15_cpuflpr.dts @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include "nrf54l15tag_cpuflpr_common.dtsi" + +/ { + model = "Nordic nRF54L15 TAG nRF54L15 FLPR MCU"; + compatible = "nordic,nrf54l15tag_nrf54l15-cpuflpr"; + + soc { + /* Resize SRAM partition */ + /delete-node/ memory@2002f000; + + cpuflpr_sram: memory@20028000 { + compatible = "mmio-sram"; + reg = <0x20028000 DT_SIZE_K(96)>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x20028000 0x18000>; + }; + }; +}; + +&cpuflpr_rram { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + cpuflpr_code_partition: partition@0 { + label = "image-0"; + reg = <0x0 DT_SIZE_K(96)>; + }; + }; +}; diff --git a/boards/nordic/nrf54l15tag/nrf54l15tag_nrf54l15_cpuflpr.yaml b/boards/nordic/nrf54l15tag/nrf54l15tag_nrf54l15_cpuflpr.yaml new file mode 100644 index 000000000000..02dffd2f5162 --- /dev/null +++ b/boards/nordic/nrf54l15tag/nrf54l15tag_nrf54l15_cpuflpr.yaml @@ -0,0 +1,17 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +identifier: nrf54l15tag/nrf54l15/cpuflpr +name: nRF54L15-TAG-nRF54L15-Fast-Lightweight-Peripheral-Processor +type: mcu +arch: riscv +toolchain: + - zephyr +sysbuild: true +ram: 96 +flash: 96 +supported: + - counter + - gpio + - i2c + - spi diff --git a/boards/nordic/nrf54l15tag/nrf54l15tag_nrf54l15_cpuflpr_defconfig b/boards/nordic/nrf54l15tag/nrf54l15tag_nrf54l15_cpuflpr_defconfig new file mode 100644 index 000000000000..706e58db3f28 --- /dev/null +++ b/boards/nordic/nrf54l15tag/nrf54l15tag_nrf54l15_cpuflpr_defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_GPIO=y +CONFIG_USE_DT_CODE_PARTITION=y + +# Execute from SRAM +CONFIG_XIP=n diff --git a/boards/nordic/nrf54l15tag/nrf54l15tag_nrf54l15_cpuflpr_xip.dts b/boards/nordic/nrf54l15tag/nrf54l15tag_nrf54l15_cpuflpr_xip.dts new file mode 100644 index 000000000000..26bdbe51a22d --- /dev/null +++ b/boards/nordic/nrf54l15tag/nrf54l15tag_nrf54l15_cpuflpr_xip.dts @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include "nrf54l15tag_cpuflpr_common.dtsi" + +/ { + model = "Nordic nRF54L15 TAG nRF54L15 FLPR MCU"; + compatible = "nordic,nrf54l15tag_nrf54l15-cpuflpr"; +}; + +&cpuflpr_rram { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + cpuflpr_code_partition: partition@0 { + label = "image-0"; + reg = <0x0 DT_SIZE_K(96)>; + }; + }; +}; diff --git a/boards/nordic/nrf54l15tag/nrf54l15tag_nrf54l15_cpuflpr_xip.yaml b/boards/nordic/nrf54l15tag/nrf54l15tag_nrf54l15_cpuflpr_xip.yaml new file mode 100644 index 000000000000..ccf6a310a637 --- /dev/null +++ b/boards/nordic/nrf54l15tag/nrf54l15tag_nrf54l15_cpuflpr_xip.yaml @@ -0,0 +1,17 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +identifier: nrf54l15tag/nrf54l15/cpuflpr/xip +name: nRF54L15-TAG-nRF54L15-Fast-Lightweight-Peripheral-Processor (RRAM XIP) +type: mcu +arch: riscv +toolchain: + - zephyr +sysbuild: true +ram: 68 +flash: 96 +supported: + - counter + - gpio + - i2c + - spi diff --git a/boards/nordic/nrf54l15tag/nrf54l15tag_nrf54l15_cpuflpr_xip_defconfig b/boards/nordic/nrf54l15tag/nrf54l15tag_nrf54l15_cpuflpr_xip_defconfig new file mode 100644 index 000000000000..36b6c6c6fc1d --- /dev/null +++ b/boards/nordic/nrf54l15tag/nrf54l15tag_nrf54l15_cpuflpr_xip_defconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_GPIO=y + +# Execute from RRAM +CONFIG_XIP=y diff --git a/boards/nordic/nrf54lm20dk/nrf54lm20a_cpuapp_common.dtsi b/boards/nordic/nrf54lm20dk/nrf54lm20a_cpuapp_common.dtsi index f0946efb543f..6ab124d0fb84 100644 --- a/boards/nordic/nrf54lm20dk/nrf54lm20a_cpuapp_common.dtsi +++ b/boards/nordic/nrf54lm20dk/nrf54lm20a_cpuapp_common.dtsi @@ -18,7 +18,6 @@ zephyr,bt-c2h-uart = &uart20; zephyr,flash-controller = &rram_controller; zephyr,flash = &cpuapp_rram; - zephyr,bt-hci = &bt_hci_controller; zephyr,ieee802154 = &ieee802154; }; @@ -98,10 +97,6 @@ status = "okay"; }; -&bt_hci_controller { - status = "okay"; -}; - &ieee802154 { status = "okay"; }; diff --git a/boards/nordic/nrf54lm20dk/nrf54lm20dk_nrf54lm20a-pinctrl.dtsi b/boards/nordic/nrf54lm20dk/nrf54lm20dk_nrf54lm20a-pinctrl.dtsi index b68222f8cb1f..d6a6dbadd146 100644 --- a/boards/nordic/nrf54lm20dk/nrf54lm20dk_nrf54lm20a-pinctrl.dtsi +++ b/boards/nordic/nrf54lm20dk/nrf54lm20dk_nrf54lm20a-pinctrl.dtsi @@ -19,12 +19,17 @@ /omit-if-no-ref/ uart20_sleep: uart20_sleep { group1 { - psels = , - , + psels = , , ; low-power-enable; }; + + group2 { + psels = ; + low-power-enable; + bias-pull-up; + }; }; /omit-if-no-ref/ pwm20_default: pwm20_default { diff --git a/boards/nordic/nrf54lm20dk/nrf54lm20dk_nrf54lm20a_cpuapp.dts b/boards/nordic/nrf54lm20dk/nrf54lm20dk_nrf54lm20a_cpuapp.dts index 2e79bbb98215..ef47e866e4c4 100644 --- a/boards/nordic/nrf54lm20dk/nrf54lm20dk_nrf54lm20a_cpuapp.dts +++ b/boards/nordic/nrf54lm20dk/nrf54lm20dk_nrf54lm20a_cpuapp.dts @@ -7,7 +7,7 @@ /dts-v1/; #include "nrf54lm20a_cpuapp_common.dtsi" -#include +#include / { compatible = "nordic,nrf54lm20dk_nrf54lm20a-cpuapp"; @@ -19,9 +19,5 @@ }; }; -&bt_hci_controller { - status = "okay"; -}; - /* Get a node label for wi-fi spi to use in shield files */ wifi_spi: &spi22 {}; diff --git a/boards/nordic/nrf54lm20dk/nrf54lm20dk_nrf54lm20a_cpuapp_ns.dts b/boards/nordic/nrf54lm20dk/nrf54lm20dk_nrf54lm20a_cpuapp_ns.dts index 04cb9d04a60c..78da8edbccd4 100644 --- a/boards/nordic/nrf54lm20dk/nrf54lm20dk_nrf54lm20a_cpuapp_ns.dts +++ b/boards/nordic/nrf54lm20dk/nrf54lm20dk_nrf54lm20a_cpuapp_ns.dts @@ -27,34 +27,6 @@ }; }; -/ { - /* - * Default SRAM planning when building for nRF54LM20A with ARM TrustZone-M support - * - Lowest 208 kB SRAM allocated to Secure image (sram0_s). - * - Upper 208 kB SRAM allocated to Non-Secure image (sram0_ns). - * - * nRF54LM20A has 512 kB of volatile memory (SRAM), but 96kB is allocated for the FLPR MCU. - * This static layout needs to be the same with the upstream TF-M layout in the - * header flash_layout.h of the relevant platform. Any updates in the layout - * needs to happen both in the flash_layout.h and in this file at the same time. - */ - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram0_s: image_s@20000000 { - /* Secure image memory */ - reg = <0x20000000 DT_SIZE_K(208)>; - }; - - sram0_ns: image_ns@20034000 { - /* Non-Secure image memory */ - reg = <0x20034000 DT_SIZE_K(208)>; - }; - }; -}; - &bt_hci_controller { status = "disabled"; }; @@ -65,4 +37,4 @@ }; /* Include default memory partition configuration file */ -#include +#include diff --git a/boards/nordic/nrf54lm20dk/nrf54lm20dk_nrf54lm20a_cpuflpr.dts b/boards/nordic/nrf54lm20dk/nrf54lm20dk_nrf54lm20a_cpuflpr.dts index 3097d3f2775e..11d72c63dfe8 100644 --- a/boards/nordic/nrf54lm20dk/nrf54lm20dk_nrf54lm20a_cpuflpr.dts +++ b/boards/nordic/nrf54lm20dk/nrf54lm20dk_nrf54lm20a_cpuflpr.dts @@ -30,6 +30,7 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + ranges; cpuflpr_code_partition: partition@0 { label = "image-0"; diff --git a/boards/nordic/nrf7002dk/Kconfig.defconfig b/boards/nordic/nrf7002dk/Kconfig.defconfig index 48510d6e24f8..a6cf1d7fbca1 100644 --- a/boards/nordic/nrf7002dk/Kconfig.defconfig +++ b/boards/nordic/nrf7002dk/Kconfig.defconfig @@ -8,4 +8,11 @@ if BOARD_NRF7002DK config HW_STACK_PROTECTION default ARCH_HAS_STACK_PROTECTION +if SPI_NOR + +config SPI_NOR_FLASH_LAYOUT_PAGE_SIZE + default 4096 if MCUBOOT || BOOTLOADER_MCUBOOT + +endif # SPI_NOR + endif # BOARD_NRF7002DK diff --git a/boards/nordic/nrf7002dk/doc/index.rst b/boards/nordic/nrf7002dk/doc/index.rst index ff9d7c754711..7f1026456cc5 100644 --- a/boards/nordic/nrf7002dk/doc/index.rst +++ b/boards/nordic/nrf7002dk/doc/index.rst @@ -104,8 +104,8 @@ The nRF5340 network core does not support the Armv8-M Security Extension. nRF5340 IDAU can configure bus accesses by the nRF5340 network core to have the secure attribute set. This allows to build and run secure-only applications on the nRF5340 SoC. -Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg| -============================================================================= +Building Secure/Non-Secure Zephyr applications with Arm® TrustZone® +=================================================================== Applications on the nRF5340 may contain a Secure and a Non-Secure firmware image for the application core. The Secure image can be built using either diff --git a/boards/nordic/nrf7002dk/nrf5340_cpuapp_common_pinctrl.dtsi b/boards/nordic/nrf7002dk/nrf5340_cpuapp_common_pinctrl.dtsi index 9a17443b3dc0..ebd915ce817e 100644 --- a/boards/nordic/nrf7002dk/nrf5340_cpuapp_common_pinctrl.dtsi +++ b/boards/nordic/nrf7002dk/nrf5340_cpuapp_common_pinctrl.dtsi @@ -1,3 +1,8 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor + * SPDX-License-Identifier: Apache-2.0 + */ + &pinctrl { i2c1_default: i2c1_default { group1 { @@ -29,12 +34,17 @@ uart0_sleep: uart0_sleep { group1 { - psels = , - , + psels = , , ; low-power-enable; }; + + group2 { + psels = ; + low-power-enable; + bias-pull-up; + }; }; pwm0_default: pwm0_default { diff --git a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet.dts b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet.dts index 5e4fd288089b..044e38e497e8 100644 --- a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet.dts +++ b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet.dts @@ -154,6 +154,7 @@ arduino_spi: &spi0 { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + ranges; boot_partition: partition@0 { label = "mcuboot"; @@ -162,7 +163,7 @@ arduino_spi: &spi0 { slot0_partition: partition@c000 { label = "image-0"; - reg = <0x0000C000 0x17000>; + reg = <0x0000c000 0x17000>; }; slot1_partition: partition@23000 { diff --git a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet_pinctrl.dtsi b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet_pinctrl.dtsi index 0abcb4724d53..2413b7c7db48 100644 --- a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet_pinctrl.dtsi +++ b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet_pinctrl.dtsi @@ -1,3 +1,8 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor + * SPDX-License-Identifier: Apache-2.0 + */ + &pinctrl { uart0_default: uart0_default { group1 { @@ -14,12 +19,17 @@ uart0_sleep: uart0_sleep { group1 { - psels = , - , + psels = , , ; low-power-enable; }; + + group2 { + psels = ; + low-power-enable; + bias-pull-up; + }; }; i2c0_default: i2c0_default { diff --git a/boards/nordic/nrf7120dk/Kconfig b/boards/nordic/nrf7120dk/Kconfig new file mode 100644 index 000000000000..7232ebc06d2e --- /dev/null +++ b/boards/nordic/nrf7120dk/Kconfig @@ -0,0 +1,30 @@ +# Copyright (c) 2026 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +# nRF7120 DK board configuration + +if BOARD_NRF7120DK_NRF7120_CPUAPP_NS + +DT_NRF_MPC_REGION := $(dt_nodelabel_path,nrf_mpc_region) + +config NRF_TRUSTZONE_FLASH_REGION_SIZE + hex + default $(dt_node_int_prop_hex,$(DT_NRF_MPC_REGION),override-granularity) + help + This defines the flash region size from the TrustZone perspective. + It is used when configuring the TrustZone and when setting alignments + requirements for the partitions. + This abstraction allows us to configure TrustZone without depending + on peripheral-specific symbols. + +config NRF_TRUSTZONE_RAM_REGION_SIZE + hex + default $(dt_node_int_prop_hex,$(DT_NRF_MPC_REGION),override-granularity) + help + This defines the RAM region size from the TrustZone perspective. + It is used when configuring the TrustZone and when setting alignments + requirements for the partitions. + This abstraction allows us to configure TrustZone without depending + on peripheral specific symbols. + +endif # BOARD_NRF7120DK_NRF7120_CPUAPP_NS diff --git a/boards/nordic/nrf7120dk/Kconfig.defconfig b/boards/nordic/nrf7120dk/Kconfig.defconfig new file mode 100644 index 000000000000..cfd142f10b5e --- /dev/null +++ b/boards/nordic/nrf7120dk/Kconfig.defconfig @@ -0,0 +1,36 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config HW_STACK_PROTECTION + default ARCH_HAS_STACK_PROTECTION + +if BOARD_NRF7120DK_NRF7120_CPUAPP + +config HAS_BT_CTLR + default BT + +config ROM_START_OFFSET + default 0x800 if BOOTLOADER_MCUBOOT + +endif # BOARD_NRF7120DK_NRF7120_CPUAPP + +if BOARD_NRF7120DK_NRF7120_CPUAPP_NS + +config BOARD_NRF7120DK + select USE_DT_CODE_PARTITION + +config HAS_BT_CTLR + default BT + +# By default, if we build for a Non-Secure version of the board, +# enable building with TF-M as the Secure Execution Environment. +config BUILD_WITH_TFM + default y + +# By default, if we build with TF-M, instruct build system to +# flash the combined TF-M (Secure) & Zephyr (Non Secure) image +config TFM_FLASH_MERGED_BINARY + default y + depends on BUILD_WITH_TFM + +endif # BOARD_NRF7120DK_NRF7120_CPUAPP_NS diff --git a/boards/nordic/nrf7120dk/Kconfig.nrf7120dk b/boards/nordic/nrf7120dk/Kconfig.nrf7120dk new file mode 100644 index 000000000000..37223f60bcd4 --- /dev/null +++ b/boards/nordic/nrf7120dk/Kconfig.nrf7120dk @@ -0,0 +1,7 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 +config BOARD_NRF7120DK + select SOC_NRF7120_ENGA_CPUAPP if BOARD_NRF7120DK_NRF7120_CPUAPP || \ + BOARD_NRF7120DK_NRF7120_CPUAPP_NS + select SOC_NRF7120_ENGA_CPUFLPR if BOARD_NRF7120DK_NRF7120_CPUFLPR || \ + BOARD_NRF7120DK_NRF7120_CPUFLPR_XIP diff --git a/boards/nordic/nrf7120dk/board.cmake b/boards/nordic/nrf7120dk/board.cmake new file mode 100644 index 000000000000..5756f8c462ac --- /dev/null +++ b/boards/nordic/nrf7120dk/board.cmake @@ -0,0 +1,20 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_SOC_NRF7120_ENGA_CPUAPP) + board_runner_args(jlink "--device=cortex-m33" "--speed=4000") +elseif(CONFIG_SOC_NRF7120_ENGA_CPUFLPR) + board_runner_args(jlink "--speed=4000") +endif() + +if(CONFIG_SOC_SERIES_NRF71 AND CONFIG_TRUSTED_EXECUTION_NONSECURE) + set(TFM_PUBLIC_KEY_FORMAT "full") +endif() + +if(CONFIG_TFM_FLASH_MERGED_BINARY) + set_property(TARGET runners_yaml_props_target PROPERTY hex_file tfm_merged.hex) +endif() + +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) +include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/nordic/nrf7120dk/board.yml b/boards/nordic/nrf7120dk/board.yml new file mode 100644 index 000000000000..c6c5d74623df --- /dev/null +++ b/boards/nordic/nrf7120dk/board.yml @@ -0,0 +1,11 @@ +board: + name: nrf7120dk + full_name: nRF7120 DK + vendor: nordic + socs: + - name: nrf7120 + variants: + - name: xip + cpucluster: cpuflpr + - name: ns + cpucluster: cpuapp diff --git a/boards/nordic/nrf7120dk/doc/index.rst b/boards/nordic/nrf7120dk/doc/index.rst new file mode 100644 index 000000000000..c84f502e5d45 --- /dev/null +++ b/boards/nordic/nrf7120dk/doc/index.rst @@ -0,0 +1,87 @@ +.. zephyr:board:: nrf7120dk + +Overview +******** + +The nRF7120 Development Kit hardware provides support for the Nordic Semiconductor +nRF7120 Arm Cortex-M33 CPU. + +Hardware +******** + +nRF7120 DK has two crystal oscillators: + +* High-frequency 64 MHz crystal oscillator (HFXO) +* Low-frequency 32.768 kHz crystal oscillator (LFXO) + +The crystal oscillators can be configured to use either +internal or external capacitors. + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Applications for the ``nrf7120dk/nrf7120/cpuapp`` board target can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +Applications for the ``nrf7120dk/nrf7120/cpuflpr`` board target need +to be built using sysbuild to include the ``vpr_launcher`` image for the application core. + +Enter the following command to compile ``hello_world`` for the FLPR core: + +.. code-block:: console + + west build -p -b nrf7120dk/nrf7120/cpuflpr --sysbuild + + +Flashing +======== + +As an example, this section shows how to build and flash the :zephyr:code-sample:`hello_world` +application. + +.. warning:: + + When programming the device, you might get an error similar to the following message:: + + ERROR: The operation attempted is unavailable due to readback protection in + ERROR: your device. Please use --recover to unlock the device. + + This error occurs when readback protection is enabled. + To disable the readback protection, you must *recover* your device. + + Enter the following command to recover the core:: + + west flash --recover + + The ``--recover`` command erases the flash memory and then writes a small binary into + the recovered flash memory. + This binary prevents the readback protection from enabling itself again after a pin + reset or power cycle. + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. + +To build and program the sample to the nRF7120 DK, complete the following steps: + +First, connect the nRF7120 DK to you computer using the IMCU USB port on the DK. +Next, build the sample by running the following command: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nrf7120dk/nrf7120/cpuapp + :goals: build flash + +Testing the LEDs and buttons in the nRF7120 DK +************************************************ + +Test the nRF7120 DK with a :zephyr:code-sample:`blinky` sample. diff --git a/boards/nordic/nrf7120dk/nrf7120_cpuapp_common.dtsi b/boards/nordic/nrf7120dk/nrf7120_cpuapp_common.dtsi new file mode 100644 index 000000000000..71e1ed593ec0 --- /dev/null +++ b/boards/nordic/nrf7120dk/nrf7120_cpuapp_common.dtsi @@ -0,0 +1,174 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* This file is common to the secure and non-secure domain */ + +#include +#include "nrf7120dk_nrf7120-common.dtsi" + +/ { + chosen { + zephyr,console = &uart20; + zephyr,shell-uart = &uart20; + zephyr,uart-mcumgr = &uart20; + zephyr,bt-mon-uart = &uart20; + zephyr,bt-c2h-uart = &uart20; + zephyr,flash = &cpuapp_mram; + zephyr,ieee802154 = &ieee802154; + zephyr,wifi = &wlan0; + }; + + /* TODO: Fine tune the sizes */ + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ipc_shm_area_cpuapp_cpuuma: memory@200c0000 { + compatible = "mmio-sram"; + reg = <0x200c0000 0x2000>; + ranges = <0x0 0x200c0000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + status = "okay"; + + ipc_shm_cpuapp_cpuuma_0: memory@0 { + reg = <0x0 DT_SIZE_K(2)>; + }; + + ipc_shm_cpuuma_cpuapp_0: memory@800 { + reg = <0x800 DT_SIZE_K(2)>; + }; + + ipc_shm_cpuapp_cpuuma_1: memory@1000 { + reg = <0x1000 DT_SIZE_K(2)>; + }; + + ipc_shm_cpuuma_cpuapp_1: memory@1800 { + reg = <0x1800 DT_SIZE_K(2)>; + }; + }; + }; + + ipc { + ipc0: ipc0 { + compatible = "zephyr,ipc-icmsg"; + tx-region = <&ipc_shm_cpuapp_cpuuma_0>; + rx-region = <&ipc_shm_cpuuma_cpuapp_0>; + mboxes = <&wifi_bellboard 2>, + <&cpuapp_bellboard 0>; + mbox-names = "tx", "rx"; + status = "okay"; + }; + + ipc1: ipc1 { + compatible = "zephyr,ipc-icmsg"; + tx-region = <&ipc_shm_cpuapp_cpuuma_1>; + rx-region = <&ipc_shm_cpuuma_cpuapp_1>; + mboxes = <&wifi_bellboard 3>, + <&cpuapp_bellboard 1>; + mbox-names = "tx", "rx"; + status = "okay"; + }; + }; +}; + +&cpuapp_sram { + status = "okay"; +}; + +&grtc { + owned-channels = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>; + /* Channels 7-11 reserved for Zero Latency IRQs, 3-4 for FLPR */ + child-owned-channels = <3 4 7 8 9 10 11>; + status = "okay"; +}; + +&uart20 { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&gpiote20 { + status = "okay"; +}; + +&gpiote30 { + status = "okay"; +}; + +&radio { + status = "okay"; +}; + +&ieee802154 { + status = "okay"; +}; + +&temp { + status = "okay"; +}; + +&clock { + status = "okay"; +}; + +&spi00 { + status = "okay"; + cs-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&spi00_default>; + pinctrl-1 = <&spi00_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&adc { + status = "okay"; +}; + +&pwr_antswc { + status = "okay"; +}; + +&wifi { + status = "okay"; +}; + +&audio_auxpll { + nordic,frequency = ; + status = "okay"; +}; + +&cpuapp_bellboard { + status = "okay"; +}; + +&wifi_bellboard { + status = "okay"; +}; + +&qspi00 { + status = "okay"; + op-mode = "MSPI_OP_MODE_CONTROLLER"; +}; diff --git a/boards/nordic/nrf7120dk/nrf7120dk_nrf7120-common.dtsi b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120-common.dtsi new file mode 100644 index 000000000000..50a219c56a0d --- /dev/null +++ b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120-common.dtsi @@ -0,0 +1,126 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "nrf7120dk_nrf7120-pinctrl.dtsi" + +/ { + leds { + compatible = "gpio-leds"; + + led0: led_0 { + gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; + label = "Green LED 0"; + }; + + led1: led_1 { + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + label = "Green LED 1"; + }; + + led2: led_2 { + gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; + label = "Green LED 2"; + }; + + led3: led_3 { + gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + label = "Green LED 3"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + /* + * PWM signal can be exposed on GPIO pin only within same domain. + * There is only one domain which contains both PWM and GPIO: + * PWM20/21/22 and GPIO Port P1. + * Only LEDs connected to P1 can work with PWM, for example LED1. + */ + + pwm_led1: pwm_led_1 { + pwms = <&pwm20 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + }; + }; + + buttons { + compatible = "gpio-keys"; + + button0: button_0 { + gpios = <&gpio1 13 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 0"; + zephyr,code = ; + }; + + button1: button_1 { + gpios = <&gpio1 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 1"; + zephyr,code = ; + }; + + button2: button_2 { + gpios = <&gpio1 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 2"; + zephyr,code = ; + }; + + button3: button_3 { + gpios = <&gpio0 4 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 3"; + zephyr,code = ; + }; + }; + + aliases { + led0 = &led0; + led1 = &led1; + led2 = &led2; + led3 = &led3; + pwm-led0 = &pwm_led1; + sw0 = &button0; + sw1 = &button1; + sw2 = &button2; + sw3 = &button3; + watchdog0 = &wdt31; + }; +}; + +&uart00 { + current-speed = <115200>; + pinctrl-0 = <&uart00_default>; + pinctrl-1 = <&uart00_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&uart20 { + current-speed = <115200>; + pinctrl-0 = <&uart20_default>; + pinctrl-1 = <&uart20_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&uart30 { + current-speed = <115200>; + pinctrl-0 = <&uart30_default>; + pinctrl-1 = <&uart30_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&pwm20 { + status = "okay"; + pinctrl-0 = <&pwm20_default>; + pinctrl-1 = <&pwm20_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&nfct { + status = "okay"; +}; + +&qspi00 { + pinctrl-0 = <&qspi00_default>; + pinctrl-1 = <&qspi00_sleep>; + pinctrl-names = "default", "sleep"; +}; diff --git a/boards/nordic/nrf7120dk/nrf7120dk_nrf7120-pinctrl.dtsi b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120-pinctrl.dtsi new file mode 100644 index 000000000000..4e307df24894 --- /dev/null +++ b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120-pinctrl.dtsi @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + /omit-if-no-ref/ uart20_default: uart20_default { + group1 { + psels = , + ; + }; + + group2 { + psels = , + ; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ uart20_sleep: uart20_sleep { + group1 { + psels = , + , + , + ; + low-power-enable; + }; + }; + + /omit-if-no-ref/ uart30_default: uart30_default { + group1 { + psels = , + ; + }; + + group2 { + psels = , + ; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ uart30_sleep: uart30_sleep { + group1 { + psels = , + , + , + ; + low-power-enable; + }; + }; + + /omit-if-no-ref/ spi00_default: spi00_default { + group1 { + psels = , + , + ; + }; + }; + + /omit-if-no-ref/ spi00_sleep: spi00_sleep { + group1 { + psels = , + , + ; + low-power-enable; + }; + }; + + /omit-if-no-ref/ pwm20_default: pwm20_default { + group1 { + psels = ; + }; + }; + + /omit-if-no-ref/ pwm20_sleep: pwm20_sleep { + group1 { + psels = ; + low-power-enable; + }; + }; + + /omit-if-no-ref/ uart00_default: uart00_default { + group1 { + psels = , + ; + }; + + group2 { + psels = , + ; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ uart00_sleep: uart00_sleep { + group1 { + psels = , + , + , + ; + low-power-enable; + }; + }; + + /omit-if-no-ref/ qspi00_default: qspi00_default { + group1 { + psels = , + , + , + , + , + ; + nordic,drive-mode = ; + }; + }; + + /omit-if-no-ref/ qspi00_sleep: qspi00_sleep { + group1 { + low-power-enable; + psels = , + , + , + , + , + ; + }; + }; +}; diff --git a/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuapp.dts b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuapp.dts new file mode 100644 index 000000000000..3e0ef75f6bed --- /dev/null +++ b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuapp.dts @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include "nrf7120_cpuapp_common.dtsi" + +/ { + compatible = "nordic,nrf7120dk_nrf7120-cpuapp"; + model = "Nordic nRF7120 DK nRF7120 Application MCU"; + + chosen { + zephyr,code-partition = &slot0_partition; + zephyr,sram = &cpuapp_sram; + }; +}; + +#include diff --git a/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuapp.yaml b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuapp.yaml new file mode 100644 index 000000000000..7d746d495b12 --- /dev/null +++ b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuapp.yaml @@ -0,0 +1,24 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +identifier: nrf7120dk/nrf7120/cpuapp +name: nRF7120-DK-nRF7120-Application +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +sysbuild: true +ram: 512 +flash: 1992 +supported: + - adc + - counter + - gpio + - i2c + - pwm + - spi + - watchdog + - i2s + - wifi diff --git a/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuapp_defconfig b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuapp_defconfig new file mode 100644 index 000000000000..8ff96446de24 --- /dev/null +++ b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuapp_defconfig @@ -0,0 +1,25 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# MPU-based null-pointer dereferencing detection cannot +# be applied as the (0x0 - 0x400) is unmapped for this target. +CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y + +# Start SYSCOUNTER on driver init +CONFIG_NRF_GRTC_START_SYSCOUNTER=y diff --git a/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuapp_ns.dts b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuapp_ns.dts new file mode 100644 index 000000000000..56f2104393d4 --- /dev/null +++ b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuapp_ns.dts @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#define USE_NON_SECURE_ADDRESS_MAP 1 + +#include "nrf7120_cpuapp_common.dtsi" + +/ { + compatible = "nordic,nrf7120dk_nrf7120-cpuapp"; + model = "Nordic nRF7120 DK nRF7120 Application MCU"; + + chosen { + zephyr,code-partition = &slot0_ns_partition; + zephyr,sram = &cpuapp_sram; + }; +}; + +&uart30 { + /* Disable so that TF-M can use this UART */ + status = "disabled"; +}; + +#include diff --git a/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuapp_ns.yaml b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuapp_ns.yaml new file mode 100644 index 000000000000..3891b38e52a0 --- /dev/null +++ b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuapp_ns.yaml @@ -0,0 +1,22 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +identifier: nrf7120dk/nrf7120/cpuapp/ns +name: nRF7120-DK-nRF7120-Application-Non-Secure +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 896 +flash: 512 +supported: + - adc + - gpio + - i2c + - spi + - counter + - watchdog + - adc + - i2s diff --git a/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuapp_ns_defconfig b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuapp_ns_defconfig new file mode 100644 index 000000000000..771440c64940 --- /dev/null +++ b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuapp_ns_defconfig @@ -0,0 +1,37 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# This Board implies building Non-Secure firmware +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +# Use devicetree code partition for TF-M +CONFIG_USE_DT_CODE_PARTITION=y + +# Don't enable the cache in the non-secure image as it is a +# secure-only peripheral on 71x series +CONFIG_CACHE_MANAGEMENT=n +CONFIG_EXTERNAL_CACHE=n + +CONFIG_UART_CONSOLE=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y + +# Enable GPIO +CONFIG_GPIO=y + +# Start SYSCOUNTER on driver init +CONFIG_NRF_GRTC_START_SYSCOUNTER=y + +# Disable TFM BL2 since it is not supported +CONFIG_TFM_BL2=n diff --git a/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuflpr.dts b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuflpr.dts new file mode 100644 index 000000000000..0497918a3195 --- /dev/null +++ b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuflpr.dts @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "nrf7120dk_nrf7120-common.dtsi" + +/ { + model = "Nordic nRF7120 DK nRF7120 FLPR MCU"; + compatible = "nordic,nrf7120dk_nrf7120-cpuflpr"; + + chosen { + zephyr,console = &uart00; + zephyr,shell-uart = &uart00; + zephyr,code-partition = &cpuflpr_code_partition; + zephyr,flash = &cpuflpr_mram; + zephyr,sram = &ram03_sram; + }; +}; + +/* RAM03 is single cycle access for FLPR core while RAM01 is 2 cycle access */ +&ram03_sram { + status = "okay"; + reg = <0x200e0000 DT_SIZE_K(120)>; + ranges = <0x0 0x200e0000 0x1e000>; +}; + +&cpuflpr_mram { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + cpuflpr_code_partition: partition@0 { + label = "image-0"; + reg = <0 DT_SIZE_K(116)>; + }; + }; +}; + +&grtc { + owned-channels = <3 4>; + status = "okay"; +}; + +&uart00 { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&gpiote20 { + status = "okay"; +}; + +&gpiote30 { + status = "okay"; +}; diff --git a/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuflpr.yaml b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuflpr.yaml new file mode 100644 index 000000000000..e04eb2653f35 --- /dev/null +++ b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuflpr.yaml @@ -0,0 +1,17 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +identifier: nrf7120dk/nrf7120/cpuflpr +name: nRF7120-DK-nRF7120-Fast-Lightweight-Peripheral-Processor +type: mcu +arch: riscv +toolchain: + - zephyr +sysbuild: true +ram: 124 +flash: 116 +supported: + - counter + - gpio + - i2c + - spi diff --git a/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuflpr_defconfig b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuflpr_defconfig new file mode 100644 index 000000000000..90cf13bdee5e --- /dev/null +++ b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuflpr_defconfig @@ -0,0 +1,17 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable GPIO +CONFIG_GPIO=y + +CONFIG_USE_DT_CODE_PARTITION=y + +# Execute from SRAM +CONFIG_XIP=n diff --git a/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuflpr_xip.dts b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuflpr_xip.dts new file mode 100644 index 000000000000..8c0b6285416e --- /dev/null +++ b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuflpr_xip.dts @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "nrf7120dk_nrf7120_cpuflpr.dts" diff --git a/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuflpr_xip.yaml b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuflpr_xip.yaml new file mode 100644 index 000000000000..a08c578b03c6 --- /dev/null +++ b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuflpr_xip.yaml @@ -0,0 +1,17 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +identifier: nrf7120dk/nrf7120/cpuflpr/xip +name: nRF7120-DK-nRF7120-Fast-Lightweight-Peripheral-Processor (MRAM XIP) +type: mcu +arch: riscv +toolchain: + - zephyr +sysbuild: true +ram: 124 +flash: 116 +supported: + - counter + - gpio + - i2c + - spi diff --git a/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuflpr_xip_defconfig b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuflpr_xip_defconfig new file mode 100644 index 000000000000..f0b4a7dc2802 --- /dev/null +++ b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuflpr_xip_defconfig @@ -0,0 +1,15 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable GPIO +CONFIG_GPIO=y + +# Execute from MRAM +CONFIG_XIP=y diff --git a/boards/nordic/nrf9131ek/doc/index.rst b/boards/nordic/nrf9131ek/doc/index.rst index 98bf55e3d6d8..cdff10ba828a 100644 --- a/boards/nordic/nrf9131ek/doc/index.rst +++ b/boards/nordic/nrf9131ek/doc/index.rst @@ -73,8 +73,8 @@ Programming and Debugging ``nrf9131ek/nrf9131`` supports the Armv8m Security Extension, and by default boots in the Secure state. -Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg| -============================================================================= +Building Secure/Non-Secure Zephyr applications with Arm® TrustZone® +=================================================================== Applications on the nRF9131 may contain a Secure and a Non-Secure firmware image. The Secure image can be built using either Zephyr or diff --git a/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_common-pinctrl.dtsi b/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_common-pinctrl.dtsi index edb6d869bf62..3bf954e021c9 100644 --- a/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_common-pinctrl.dtsi +++ b/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_common-pinctrl.dtsi @@ -19,12 +19,17 @@ uart0_sleep: uart0_sleep { group1 { - psels = , - , + psels = , , ; low-power-enable; }; + + group2 { + psels = ; + low-power-enable; + bias-pull-up; + }; }; uart1_default: uart1_default { diff --git a/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_ns.dts b/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_ns.dts index 7dcf700bcf6f..987940b973ed 100644 --- a/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_ns.dts +++ b/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_ns.dts @@ -5,7 +5,7 @@ */ /dts-v1/; -#include +#include #include "nrf9131ek_nrf9131_common.dtsi" / { diff --git a/boards/nordic/nrf9151dk/doc/index.rst b/boards/nordic/nrf9151dk/doc/index.rst index a688062d2dd4..3b742dc2a976 100644 --- a/boards/nordic/nrf9151dk/doc/index.rst +++ b/boards/nordic/nrf9151dk/doc/index.rst @@ -76,8 +76,8 @@ Programming and Debugging ``nrf9151dk/nrf9151`` supports the Armv8m Security Extension, and by default boots in the Secure state. -Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg| -============================================================================= +Building Secure/Non-Secure Zephyr applications with Arm® TrustZone® +=================================================================== The process requires the following steps: diff --git a/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_common-pinctrl.dtsi b/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_common-pinctrl.dtsi index 2685cc354ec5..ce045be9157f 100644 --- a/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_common-pinctrl.dtsi +++ b/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_common-pinctrl.dtsi @@ -19,12 +19,17 @@ uart0_sleep: uart0_sleep { group1 { - psels = , - , + psels = , , ; low-power-enable; }; + + group2 { + psels = ; + low-power-enable; + bias-pull-up; + }; }; uart1_default: uart1_default { diff --git a/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_ns.dts b/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_ns.dts index 8074695d251b..b7d2fab385e8 100644 --- a/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_ns.dts +++ b/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_ns.dts @@ -5,7 +5,7 @@ */ /dts-v1/; -#include +#include #include "nrf9151dk_nrf9151_common.dtsi" / { diff --git a/boards/nordic/nrf9160dk/Kconfig.defconfig b/boards/nordic/nrf9160dk/Kconfig.defconfig index f27b36a40d16..8dba84f88ad3 100644 --- a/boards/nordic/nrf9160dk/Kconfig.defconfig +++ b/boards/nordic/nrf9160dk/Kconfig.defconfig @@ -20,6 +20,13 @@ config BT_WAIT_NOP config I2C default $(dt_compat_on_bus,$(DT_COMPAT_NXP_PCAL6408A),i2c) +if SPI_NOR && BOARD_REVISION = "0.14.0" + +config SPI_NOR_FLASH_LAYOUT_PAGE_SIZE + default 4096 if MCUBOOT || BOOTLOADER_MCUBOOT + +endif # SPI_NOR && BOARD_REVISION = "0.14.0" + endif # BOARD_NRF9160DK_NRF9160 || BOARD_NRF9160DK_NRF9160_NS if BOARD_NRF9160DK_NRF52840 diff --git a/boards/nordic/nrf9160dk/doc/index.rst b/boards/nordic/nrf9160dk/doc/index.rst index a91cf76547b1..f8d8c8b05f51 100644 --- a/boards/nordic/nrf9160dk/doc/index.rst +++ b/boards/nordic/nrf9160dk/doc/index.rst @@ -147,8 +147,8 @@ Programming and Debugging nrf9160dk/nrf9160 supports the Armv8m Security Extension, and by default boots in the Secure state. -Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg| -============================================================================= +Building Secure/Non-Secure Zephyr applications with Arm® TrustZone® +=================================================================== Applications on the nRF9160 may contain a Secure and a Non-Secure firmware image. The Secure image can be built using either Zephyr or diff --git a/boards/nordic/nrf9160dk/nrf9160dk_nrf52840-pinctrl.dtsi b/boards/nordic/nrf9160dk/nrf9160dk_nrf52840-pinctrl.dtsi index 22eae1b3b6c2..69a3c104bd50 100644 --- a/boards/nordic/nrf9160dk/nrf9160dk_nrf52840-pinctrl.dtsi +++ b/boards/nordic/nrf9160dk/nrf9160dk_nrf52840-pinctrl.dtsi @@ -19,11 +19,16 @@ uart0_sleep: uart0_sleep { group1 { - psels = , - , + psels = , , ; low-power-enable; }; + + group2 { + psels = ; + low-power-enable; + bias-pull-up; + }; }; }; diff --git a/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_common-pinctrl.dtsi b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_common-pinctrl.dtsi index 8ca261027d11..493ccab64d54 100644 --- a/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_common-pinctrl.dtsi +++ b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_common-pinctrl.dtsi @@ -19,12 +19,17 @@ uart0_sleep: uart0_sleep { group1 { - psels = , - , + psels = , , ; low-power-enable; }; + + group2 { + psels = ; + low-power-enable; + bias-pull-up; + }; }; uart1_default: uart1_default { diff --git a/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_ns.dts b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_ns.dts index 1bac60d26622..2b72f59da11c 100644 --- a/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_ns.dts +++ b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_ns.dts @@ -5,7 +5,7 @@ */ /dts-v1/; -#include +#include #include "nrf9160dk_nrf9160_common.dtsi" / { diff --git a/boards/nordic/nrf9161dk/doc/index.rst b/boards/nordic/nrf9161dk/doc/index.rst index 00e2e702823e..1d0cd055fabe 100644 --- a/boards/nordic/nrf9161dk/doc/index.rst +++ b/boards/nordic/nrf9161dk/doc/index.rst @@ -83,8 +83,8 @@ Programming and Debugging ``nrf9161dk/nrf9161`` supports the Armv8m Security Extension, and by default boots in the Secure state. -Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg| -============================================================================= +Building Secure/Non-Secure Zephyr applications with Arm® TrustZone® +=================================================================== The process requires the following steps: diff --git a/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_common-pinctrl.dtsi b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_common-pinctrl.dtsi index 2685cc354ec5..ce045be9157f 100644 --- a/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_common-pinctrl.dtsi +++ b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_common-pinctrl.dtsi @@ -19,12 +19,17 @@ uart0_sleep: uart0_sleep { group1 { - psels = , - , + psels = , , ; low-power-enable; }; + + group2 { + psels = ; + low-power-enable; + bias-pull-up; + }; }; uart1_default: uart1_default { diff --git a/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_ns.dts b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_ns.dts index 1bb0c0f2512c..e465dfe1a79b 100644 --- a/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_ns.dts +++ b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_ns.dts @@ -5,7 +5,7 @@ */ /dts-v1/; -#include +#include #include "nrf9161dk_nrf9161_common.dtsi" / { diff --git a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280-memory_map.dtsi b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280-memory_map.dtsi index 75ef062c1024..4be968ed3df2 100644 --- a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280-memory_map.dtsi +++ b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280-memory_map.dtsi @@ -189,6 +189,7 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + ranges; cpuapp_boot_partition: partition@312000 { reg = <0x312000 DT_SIZE_K(64)>; @@ -202,12 +203,12 @@ reg = <0x376000 DT_SIZE_K(440)>; }; - cpuppr_code_partition: partition@3E4000 { - reg = <0x3E4000 DT_SIZE_K(64)>; + cpuppr_code_partition: partition@3e4000 { + reg = <0x3e4000 DT_SIZE_K(64)>; }; - cpuflpr_code_partition: partition@3F4000 { - reg = <0x3F4000 DT_SIZE_K(48)>; + cpuflpr_code_partition: partition@3f4000 { + reg = <0x3f4000 DT_SIZE_K(48)>; }; cpurad_slot0_partition: partition@400000 { diff --git a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280-pinctrl.dtsi b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280-pinctrl.dtsi index 709fda74f89f..b00d9e0082d6 100644 --- a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280-pinctrl.dtsi +++ b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280-pinctrl.dtsi @@ -21,11 +21,16 @@ /omit-if-no-ref/ uart135_sleep: uart135_sleep { group1 { low-power-enable; - psels = , - , + psels = , , ; }; + + group2 { + psels = ; + low-power-enable; + bias-pull-up; + }; }; /omit-if-no-ref/ uart136_default: uart136_default { @@ -44,11 +49,16 @@ /omit-if-no-ref/ uart136_sleep: uart136_sleep { group1 { low-power-enable; - psels = , - , + psels = , , ; }; + + group2 { + psels = ; + low-power-enable; + bias-pull-up; + }; }; /omit-if-no-ref/ exmif_default: exmif_default { diff --git a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp.dts b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp.dts index ee8588622a52..0a12dafab84a 100644 --- a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp.dts +++ b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp.dts @@ -133,7 +133,7 @@ * - Bell 18: cpurad * - Bells 24, 25, 29, 31: cpucell */ - nordic,interrupt-mapping = <0xA3042041 0>; + nordic,interrupt-mapping = <0xa3042041 0>; }; &cpurad_bellboard { diff --git a/boards/nordic/thingy52/thingy52_nrf52832-pinctrl.dtsi b/boards/nordic/thingy52/thingy52_nrf52832-pinctrl.dtsi index df96e0c27c7c..5b4953cfffeb 100644 --- a/boards/nordic/thingy52/thingy52_nrf52832-pinctrl.dtsi +++ b/boards/nordic/thingy52/thingy52_nrf52832-pinctrl.dtsi @@ -13,9 +13,14 @@ uart0_sleep: uart0_sleep { group1 { - psels = , - ; + psels = ; + low-power-enable; + }; + + group2 { + psels = ; low-power-enable; + bias-pull-up; }; }; diff --git a/boards/nordic/thingy52/thingy52_nrf52832.dts b/boards/nordic/thingy52/thingy52_nrf52832.dts index e081ae877ce2..a023b06e55b9 100644 --- a/boards/nordic/thingy52/thingy52_nrf52832.dts +++ b/boards/nordic/thingy52/thingy52_nrf52832.dts @@ -206,12 +206,12 @@ slot0_partition: partition@c000 { label = "image-0"; - reg = <0x0000C000 0x32000>; + reg = <0x0000c000 0x32000>; }; slot1_partition: partition@3e000 { label = "image-1"; - reg = <0x0003E000 0x32000>; + reg = <0x0003e000 0x32000>; }; scratch_partition: partition@70000 { diff --git a/boards/nordic/thingy53/Kconfig.defconfig b/boards/nordic/thingy53/Kconfig.defconfig index c1139f0dca10..c5b54f30cb79 100644 --- a/boards/nordic/thingy53/Kconfig.defconfig +++ b/boards/nordic/thingy53/Kconfig.defconfig @@ -6,6 +6,13 @@ config HW_STACK_PROTECTION default ARCH_HAS_STACK_PROTECTION +if NORDIC_QSPI_NOR + +config NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE + default 4096 if MCUBOOT || BOOTLOADER_MCUBOOT + +endif # NORDIC_QSPI_NOR + if BOARD_THINGY53_NRF5340_CPUAPP || BOARD_THINGY53_NRF5340_CPUAPP_NS # Code Partition: diff --git a/boards/nordic/thingy53/thingy53_nrf5340_common-pinctrl.dtsi b/boards/nordic/thingy53/thingy53_nrf5340_common-pinctrl.dtsi index fbd084a152c6..76dd258cfe85 100644 --- a/boards/nordic/thingy53/thingy53_nrf5340_common-pinctrl.dtsi +++ b/boards/nordic/thingy53/thingy53_nrf5340_common-pinctrl.dtsi @@ -77,12 +77,17 @@ uart0_sleep: uart0_sleep { group1 { - psels = , - , + psels = , , ; low-power-enable; }; + + group2 { + psels = ; + low-power-enable; + bias-pull-up; + }; }; qspi_default: qspi_default { diff --git a/boards/nordic/thingy53/thingy53_nrf5340_cpuapp_ns.dts b/boards/nordic/thingy53/thingy53_nrf5340_cpuapp_ns.dts index fee8c98c10b2..6991df96bb77 100644 --- a/boards/nordic/thingy53/thingy53_nrf5340_cpuapp_ns.dts +++ b/boards/nordic/thingy53/thingy53_nrf5340_cpuapp_ns.dts @@ -5,7 +5,7 @@ */ /dts-v1/; -#include +#include #include "thingy53_nrf5340_common.dtsi" #include <../boards/common/usb/cdc_acm_serial.dtsi> diff --git a/boards/nordic/thingy53/thingy53_nrf5340_cpunet-pinctrl.dtsi b/boards/nordic/thingy53/thingy53_nrf5340_cpunet-pinctrl.dtsi index 76d1fd8bad50..566521568f8f 100644 --- a/boards/nordic/thingy53/thingy53_nrf5340_cpunet-pinctrl.dtsi +++ b/boards/nordic/thingy53/thingy53_nrf5340_cpunet-pinctrl.dtsi @@ -15,12 +15,17 @@ uart0_sleep: uart0_sleep { group1 { - psels = , - , + psels = , , ; low-power-enable; }; + + group2 { + psels = ; + low-power-enable; + bias-pull-up; + }; }; spi0_default: spi0_default { diff --git a/boards/nordic/thingy53/thingy53_nrf5340_cpunet.dts b/boards/nordic/thingy53/thingy53_nrf5340_cpunet.dts index 6da36791d5ec..d74952119839 100644 --- a/boards/nordic/thingy53/thingy53_nrf5340_cpunet.dts +++ b/boards/nordic/thingy53/thingy53_nrf5340_cpunet.dts @@ -145,6 +145,7 @@ fem_spi: &spi0 { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + ranges; boot_partition: partition@0 { label = "mcuboot"; @@ -153,7 +154,7 @@ fem_spi: &spi0 { slot0_partition: partition@c000 { label = "image-0"; - reg = <0x0000C000 0x17000>; + reg = <0x0000c000 0x17000>; }; slot1_partition: partition@23000 { diff --git a/boards/norik/octopus_io_board/octopus_io_board_nrf9160_ns.dts b/boards/norik/octopus_io_board/octopus_io_board_nrf9160_ns.dts index fa24ffbf5650..1e80b5c101ab 100644 --- a/boards/norik/octopus_io_board/octopus_io_board_nrf9160_ns.dts +++ b/boards/norik/octopus_io_board/octopus_io_board_nrf9160_ns.dts @@ -4,7 +4,7 @@ */ /dts-v1/; -#include +#include #include "octopus_io_board_common.dtsi" / { diff --git a/boards/norik/octopus_som/octopus_som_nrf9160_ns.dts b/boards/norik/octopus_som/octopus_som_nrf9160_ns.dts index 3cd80c2ca33a..7cff43bf21a9 100644 --- a/boards/norik/octopus_som/octopus_som_nrf9160_ns.dts +++ b/boards/norik/octopus_som/octopus_som_nrf9160_ns.dts @@ -4,7 +4,7 @@ */ /dts-v1/; -#include +#include #include "octopus_som_common.dtsi" / { diff --git a/boards/nuvoton/numaker_gai_m55m1/Kconfig.numaker_gai_m55m1 b/boards/nuvoton/numaker_gai_m55m1/Kconfig.numaker_gai_m55m1 new file mode 100644 index 000000000000..eb944229d642 --- /dev/null +++ b/boards/nuvoton/numaker_gai_m55m1/Kconfig.numaker_gai_m55m1 @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Nuvoton NuMaker NUGESTUREAI M55M1 board configuration +# +# Copyright (c) 2026 Nuvoton Technology Corporation. + +config BOARD_NUMAKER_GAI_M55M1 + select SOC_M55M1XXX diff --git a/boards/nuvoton/numaker_gai_m55m1/board.cmake b/boards/nuvoton/numaker_gai_m55m1/board.cmake new file mode 100644 index 000000000000..834a265466e1 --- /dev/null +++ b/boards/nuvoton/numaker_gai_m55m1/board.cmake @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(pyocd "--target=m55m1h2ljae") + +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/nuvoton/numaker_gai_m55m1/board.yml b/boards/nuvoton/numaker_gai_m55m1/board.yml new file mode 100644 index 000000000000..4c87158715c9 --- /dev/null +++ b/boards/nuvoton/numaker_gai_m55m1/board.yml @@ -0,0 +1,6 @@ +board: + name: numaker_gai_m55m1 + full_name: NUMAKER NUGESTUREAI M55M1 + vendor: nuvoton + socs: + - name: m55m1xxx diff --git a/boards/nuvoton/numaker_gai_m55m1/doc/gai_m55m1.webp b/boards/nuvoton/numaker_gai_m55m1/doc/gai_m55m1.webp new file mode 100644 index 000000000000..df06076e5d2d Binary files /dev/null and b/boards/nuvoton/numaker_gai_m55m1/doc/gai_m55m1.webp differ diff --git a/boards/nuvoton/numaker_gai_m55m1/doc/index.rst b/boards/nuvoton/numaker_gai_m55m1/doc/index.rst new file mode 100644 index 000000000000..ad0bbb9d5187 --- /dev/null +++ b/boards/nuvoton/numaker_gai_m55m1/doc/index.rst @@ -0,0 +1,88 @@ +.. zephyr:board:: numaker_gai_m55m1 + +Overview +******** + +The NuMaker M55M1 is an Internet of Things (IoT) application focused platform +specially developed by Nuvoton. The NuGestureAI-M55M1 is based on the NuMicro® M55M1 +series MCU with ARM® -Cortex®-M55 core. + +Features +======== +- 32-bit Arm Cortex®-M55 M55M1H2LJAE MCU +- Core clock up to 220 MHz +- 2 MB embedded Dual Bank Flash and 1344 KB SRAM +- 128 KB DTCM and 64 KB ITCM +- USB 2.0 Full-Speed OTG / Device +- USB 1.1 Host +- One push-button is for reset +- Two LEDs: one is for power indication and the other is for user-defined +- One SWD connector + +More information about the board can be found at the `NuMaker M55M1 User Manual`_. + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +The on-board 12-MHz crystal allows the device to run at its maximum operating speed of 220 MHz. + +More details about the supported peripherals are available in `M55M1 TRM`_ + +Building and Flashing +********************* + +.. zephyr:board-supported-runners:: + +Flashing +======== + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +On board debugger Nu-link2 can emulate UART0 as a virtual COM port over usb, +To enable this, set ISW1 DIP switch 1-3 (TXD RXD VOM) to ON. +Connect the NuMaker-M55M1 to your host computer using the USB port, then +run a serial host program to connect with your board. For example: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: numaker_gai_m55m1 + :goals: flash + +Debugging +========= + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: numaker_gai_m55m1 + :goals: debug + +Step through the application in your debugger. + +VS Code Support +=============== + +Here is to go through VS Code instead of command line. + +Please install Nuvoton NuMicro Cortex-M Pack and follow getting start guide of this pack. +This pack is a complete development toolkit for Nuvoton’s NuMicro Cortex-M microcontrollers +in Visual Studio Code. +URL of this pack is +https://marketplace.visualstudio.com/items?itemName=Nuvoton.nuvoton-numicro-cortex-m-pack + +References +********** + +.. target-notes:: + +.. _NuMaker M55M1 User Manual: + https://www.nuvoton.com/products/microcontrollers/arm-cortex-m55-mcus/m55m1-series/ +.. _M55M1 TRM: + https://www.nuvoton.com/products/microcontrollers/arm-cortex-m55-mcus/m55m1-series/ diff --git a/boards/nuvoton/numaker_gai_m55m1/numaker_gai_m55m1-pinctrl.dtsi b/boards/nuvoton/numaker_gai_m55m1/numaker_gai_m55m1-pinctrl.dtsi new file mode 100644 index 000000000000..eb3800b70d98 --- /dev/null +++ b/boards/nuvoton/numaker_gai_m55m1/numaker_gai_m55m1-pinctrl.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2026 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "pinctrl/m55m1h2l-pinctrl.h" + +&pinctrl { + uart5_default: uart5_default { + group0 { + pinmux = , + ; + }; + }; + + uart2_default: uart2_default { + group0 { + pinmux = , + ; + }; + }; +}; diff --git a/boards/nuvoton/numaker_gai_m55m1/numaker_gai_m55m1.dts b/boards/nuvoton/numaker_gai_m55m1/numaker_gai_m55m1.dts new file mode 100644 index 000000000000..a31a9b954ca0 --- /dev/null +++ b/boards/nuvoton/numaker_gai_m55m1/numaker_gai_m55m1.dts @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2026 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "numaker_gai_m55m1-pinctrl.dtsi" +#include + +/ { + model = "Nuvoton NuMaker GestureAI M55M1 board"; + compatible = "nuvoton,numaker-m55m1"; + + aliases { + led0 = &yellow_led; + sw0 = &btn0; + }; + + chosen { + zephyr,console = &uart5; + zephyr,shell-uart = &uart5; + zephyr,sram = &sram0; + zephyr,dtcm = &dtcm; + zephyr,itcm = &itcm; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; + + leds { + compatible = "gpio-leds"; + + yellow_led: led_0 { + gpios = <&gpioa 7 GPIO_ACTIVE_LOW>; + label = "User LD0"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + btn0: btn0 { + label = "BTN0"; + gpios = <&gpioa 4 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; +}; + +&scc { + lxt = "disable"; + hxt = "enable"; +}; + +&gpioa { + status = "okay"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x0 0xfe00>; + }; + + slot0_partition: partition@fe00 { + label = "image-0"; + reg = <0xfe00 0xf4000>; + }; + + slot1_partition: partition@103e00 { + label = "image-1"; + reg = <0x103e00 0xf4000>; + }; + + storage_partition: partition@1f7e00 { + label = "storage"; + reg = <0x1f7e00 0x8200>; + }; + }; +}; + +&sram0 { + reg = <0x20100000 DT_SIZE_K(1344)>; +}; + +&uart5 { + current-speed = <115200>; + pinctrl-0 = <&uart5_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* On enabled, husbd phy is required HXT. */ +zephyr_udc0: &hsusbd { + /* Needn't pinctrl for pins being dedicated */ + status = "okay"; +}; diff --git a/boards/nuvoton/numaker_gai_m55m1/numaker_gai_m55m1.yaml b/boards/nuvoton/numaker_gai_m55m1/numaker_gai_m55m1.yaml new file mode 100644 index 000000000000..65fe23d8e290 --- /dev/null +++ b/boards/nuvoton/numaker_gai_m55m1/numaker_gai_m55m1.yaml @@ -0,0 +1,16 @@ +# Copyright (c) 2026 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +identifier: numaker_gai_m55m1 +name: NUVOTON NUMAKER-GAI-M55M1 Kit +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +ram: 1536 +flash: 2048 +supported: + - gpio + - usb +vendor: nuvoton diff --git a/boards/nuvoton/numaker_gai_m55m1/numaker_gai_m55m1_defconfig b/boards/nuvoton/numaker_gai_m55m1/numaker_gai_m55m1_defconfig new file mode 100644 index 000000000000..903b01170325 --- /dev/null +++ b/boards/nuvoton/numaker_gai_m55m1/numaker_gai_m55m1_defconfig @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_GPIO=y + +# Enable system clock controller driver +CONFIG_CLOCK_CONTROL=y +CONFIG_CLOCK_CONTROL_NUMAKER_SCC=y + +# Enable UART driver +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/nuvoton/numaker_gai_m55m1/support/openocd.cfg b/boards/nuvoton/numaker_gai_m55m1/support/openocd.cfg new file mode 100644 index 000000000000..c393f756c4de --- /dev/null +++ b/boards/nuvoton/numaker_gai_m55m1/support/openocd.cfg @@ -0,0 +1,2 @@ +source [find interface/nulink.cfg] +source [find target/numicro.cfg] diff --git a/boards/nxp/common/board-footer.rst.inc b/boards/nxp/common/board-footer.rst.inc index 65740d828c3d..abc2c054ff54 100644 --- a/boards/nxp/common/board-footer.rst.inc +++ b/boards/nxp/common/board-footer.rst.inc @@ -1,22 +1,26 @@ Support Resources for Zephyr ============================ +- `NXP Board Support Status`_ - `NXP Zephyr Downstream Software Development Kit`_ -- `MCUXpresso for VS Code`_, `wiki`_ documentation and `Zephyr lab guides`_ +- `MCUXpresso for VS Code documentation`_, and `Zephyr lab guides`_ - `NXP Zephyr Knowledge Hub`_ - `NXP’s Zephyr landing page`_ (including training resources) - `NXP Support Community forum for Zephyr`_ +.. _NXP Board Support Status: + https://github.com/nxp-zephyr/nxp-zsdk/blob/main/doc/releases/Board-Support-Status.md + .. _NXP Zephyr Downstream Software Development Kit: https://github.com/nxp-zephyr/nxp-zsdk .. _MCUXpresso for VS Code: https://www.nxp.com/design/design-center/software/embedded-software/mcuxpresso-for-visual-studio-code:MCUXPRESSO-VSC?tid=vanMCUXPRESSO-VSC -.. _wiki: - https://github.com/nxp-mcuxpresso/vscode-for-mcux/wiki +.. _MCUXpresso for VS Code documentation: + https://mcuxpresso.nxp.com/mcux-vscode .. _Zephyr lab guides: - https://github.com/nxp-mcuxpresso/vscode-for-mcux/wiki/Training-Zephyr-Getting-Started + https://mcuxpresso.nxp.com/mcux-vscode/latest/html/Training-Zephyr-Getting-Started.html .. _NXP Zephyr Knowledge Hub: https://community.nxp.com/t5/Zephyr-Project-Knowledge-Base/Zephyr-Knowledge-Hub/ta-p/2008548 diff --git a/boards/nxp/frdm_imx91/board.cmake b/boards/nxp/frdm_imx91/board.cmake new file mode 100644 index 000000000000..aef990660faf --- /dev/null +++ b/boards/nxp/frdm_imx91/board.cmake @@ -0,0 +1,7 @@ +# +# SPDX-FileCopyrightText: Copyright 2026 NXP +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=MIMX9131" "--no-reset" "--flash-sram") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/nxp/frdm_imx91/doc/index.rst b/boards/nxp/frdm_imx91/doc/index.rst index a4c628cd81ce..4997665812a8 100644 --- a/boards/nxp/frdm_imx91/doc/index.rst +++ b/boards/nxp/frdm_imx91/doc/index.rst @@ -104,6 +104,13 @@ uSDHC2 for testing: Programming and Debugging ************************* +.. zephyr:board-supported-runners:: + +There are multiple methods to program and debug Zephyr + +Option 1. Boot Zephyr by Using U-Boot Command +============================================= + U-Boot "go" command is used to load and kick Zephyr to Cortex-A55 Core. Stop the board at U-Boot command line, then need to download Zephyr binary image into @@ -149,4 +156,55 @@ display the following console output: thread_a: Hello World from cpu 0 on frdm_imx91! thread_b: Hello World from cpu 0 on frdm_imx91! +Option 2. Boot Zephyr by Using JLink Runner +=========================================== + +Hardware Setup +-------------- + +The default runner for the board is JLink runner, there is one SWD connnector P14 on +the FRDM-IMX91 board, connect P14 to J-Link debugger with Pin1 of P14 connect to SWDCLK, +Pin2 of P14 connect to SWDIO, and Pin3 of P14 connect to GND, the VCC of J-Link debugger +could connect to P1 of P12 connector. + +Flash and Run +------------- + +Power up the board and stop the board at U-Boot command line. + +Then use "west flash" command to load the zephyr.bin image from the host computer and +start the Zephyr application on A55 core. + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :host-os: unix + :board: frdm_imx91/mimx9131 + :goals: flash + +Then the following log could be found on UART1 console: + +.. code-block:: console + + + *** Booting Zephyr OS build v4.3.0-1976-g8f0df404c2ee *** + Hello World! frdm_imx91/mimx9131 + +Debug +----- + +Power up the board and stop the board at U-Boot command line. + +Then use "west debug" command to load the zephyr.bin image from the host computer and +debug the Zephyr application on A55 core. + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :host-os: unix + :board: frdm_imx91/mimx9131 + :goals: debug + .. include:: ../../common/board-footer.rst.inc diff --git a/boards/nxp/frdm_imx93/Kconfig.defconfig b/boards/nxp/frdm_imx93/Kconfig.defconfig index fc59366b9114..04a10d3bedc7 100644 --- a/boards/nxp/frdm_imx93/Kconfig.defconfig +++ b/boards/nxp/frdm_imx93/Kconfig.defconfig @@ -42,6 +42,9 @@ configdefault NET_MGMT_EVENT_STACK_SIZE configdefault NET_SOCKETS_SERVICE_STACK_SIZE default 8192 +configdefault UDC_WORKQUEUE_STACK_SIZE + default 4096 + endif # BOARD_FRDM_IMX93_MIMX9352_A55 if IMX_USDHC diff --git a/boards/nxp/frdm_imx93/board.cmake b/boards/nxp/frdm_imx93/board.cmake new file mode 100644 index 000000000000..8e6c3322b769 --- /dev/null +++ b/boards/nxp/frdm_imx93/board.cmake @@ -0,0 +1,11 @@ +# +# SPDX-FileCopyrightText: Copyright 2026 NXP +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_SOC_MIMX9352_A55) + +board_runner_args(jlink "--device=MIMX9352_A55_0" "--no-reset" "--flash-sram") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) + +endif() diff --git a/boards/nxp/frdm_imx93/doc/index.rst b/boards/nxp/frdm_imx93/doc/index.rst index 3bfbc071c254..1b61cebe2a94 100644 --- a/boards/nxp/frdm_imx93/doc/index.rst +++ b/boards/nxp/frdm_imx93/doc/index.rst @@ -122,6 +122,13 @@ Note: The overlay only supports ``mimx9352/a55``, but can be extended to support Programming and Debugging (A55) ******************************* +.. zephyr:board-supported-runners:: + +There are multiple methods to program and debug Zephyr + +Option 1. Boot Zephyr by Using U-Boot Command +============================================= + U-Boot "cpu" command is used to load and kick Zephyr to Cortex-A secondary Core, Currently it is supported in : `Real-Time Edge U-Boot`_ (use the branch "uboot_vxxxx.xx-y.y.y, xxxx.xx is uboot version and y.y.y is Real-Time Edge Software version, for example @@ -171,6 +178,63 @@ display the following console output: thread_a: Hello World from cpu 0 on frdm_imx93! thread_b: Hello World from cpu 0 on frdm_imx93! +Option 2. Boot Zephyr by Using JLink Runner +=========================================== + +Hardware Setup +-------------- + + +The default runner for the board is JLink runner, there is one SWD connnector P14 on +the FRDM-IMX93 board. + +Refer to `NXP online document`_ to rework FRDM-IMX93 board and connect SWD connector P14 +to J-Link debugger. + +.. _NXP online document: + https://community.nxp.com/t5/FRDM-Training-Hub/How-to-use-J-link-on-FRDM-IMX93/ta-p/2122902 + + +Flash and Run +------------- + +Power up the board and stop the board at U-Boot command line. + +Then use "west flash" command to load the zephyr.bin image from the host computer and +start the Zephyr application on A55 core. + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :host-os: unix + :board: frdm_imx93/mimx9352/a55 + :goals: flash + +Then the following log could be found on UART1 console: + +.. code-block:: console + + + *** Booting Zephyr OS build v4.3.0-1976-g8f0df404c2ee *** + Hello World! frdm_imx93/mimx9352 + +Debug +----- + +Power up the board and stop the board at U-Boot command line. + +Then use "west debug" command to load the zephyr.bin image from the host computer and +debug the Zephyr application on A55 core. + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :host-os: unix + :board: frdm_imx93/mimx9352/a55 + :goals: debug + System Reboot (A55) =================== diff --git a/boards/nxp/frdm_imx93/frdm_imx93_mimx9352_a55.dts b/boards/nxp/frdm_imx93/frdm_imx93_mimx9352_a55.dts index fd6ee72e88ae..59cb63e558b9 100644 --- a/boards/nxp/frdm_imx93/frdm_imx93_mimx9352_a55.dts +++ b/boards/nxp/frdm_imx93/frdm_imx93_mimx9352_a55.dts @@ -227,3 +227,7 @@ }; display_i2c: &lpi2c1 {}; + +zephyr_udc0: &usb1 { + status = "okay"; +}; diff --git a/boards/nxp/frdm_imx93/frdm_imx93_mimx9352_a55.yaml b/boards/nxp/frdm_imx93/frdm_imx93_mimx9352_a55.yaml index c9f4df5f8189..a4a76f58a5ce 100644 --- a/boards/nxp/frdm_imx93/frdm_imx93_mimx9352_a55.yaml +++ b/boards/nxp/frdm_imx93/frdm_imx93_mimx9352_a55.yaml @@ -21,6 +21,7 @@ supported: - can - net - watchdog + - usbd testing: ignore_tags: - bluetooth diff --git a/boards/nxp/frdm_imx93/frdm_imx93_mimx9352_m33.dts b/boards/nxp/frdm_imx93/frdm_imx93_mimx9352_m33.dts index ae433a87e272..0340ac7a5dd0 100644 --- a/boards/nxp/frdm_imx93/frdm_imx93_mimx9352_m33.dts +++ b/boards/nxp/frdm_imx93/frdm_imx93_mimx9352_m33.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "frdm_imx93-pinctrl.dtsi" #include diff --git a/boards/nxp/frdm_k22f/frdm_k22f.dts b/boards/nxp/frdm_k22f/frdm_k22f.dts index 0ca83d4f905c..14110c05075c 100644 --- a/boards/nxp/frdm_k22f/frdm_k22f.dts +++ b/boards/nxp/frdm_k22f/frdm_k22f.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include +#include #include #include "frdm_k22f-pinctrl.dtsi" #include @@ -231,14 +231,14 @@ zephyr_uhc0: &usbh { reg = <0x00010000 DT_SIZE_K(182)>; }; - slot1_partition: partition@3D800 { + slot1_partition: partition@3d800 { label = "image-1"; - reg = <0x0003D800 DT_SIZE_K(182)>; + reg = <0x0003d800 DT_SIZE_K(182)>; }; - storage_partition: partition@6B000 { + storage_partition: partition@6b000 { label = "storage"; - reg = <0x0006B000 DT_SIZE_K(84)>; + reg = <0x0006b000 DT_SIZE_K(84)>; }; }; }; diff --git a/boards/nxp/frdm_k32l2b3/frdm_k32l2b3.dts b/boards/nxp/frdm_k32l2b3/frdm_k32l2b3.dts index 98795b2703ac..95fddf3c71d6 100644 --- a/boards/nxp/frdm_k32l2b3/frdm_k32l2b3.dts +++ b/boards/nxp/frdm_k32l2b3/frdm_k32l2b3.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include #include "frdm_k32l2b3-pinctrl.dtsi" diff --git a/boards/nxp/frdm_k64f/frdm_k64f.dts b/boards/nxp/frdm_k64f/frdm_k64f.dts index f337a24a0f6d..58c7d35c7d76 100644 --- a/boards/nxp/frdm_k64f/frdm_k64f.dts +++ b/boards/nxp/frdm_k64f/frdm_k64f.dts @@ -1,8 +1,12 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ /dts-v1/; -#include +#include #include "frdm_k64f-pinctrl.dtsi" #include #include @@ -173,6 +177,7 @@ arduino_spi: &spi0 { disk-name = "SD"; status = "okay"; }; + spi-max-frequency = ; }; }; diff --git a/boards/nxp/frdm_k82f/frdm_k82f.dts b/boards/nxp/frdm_k82f/frdm_k82f.dts index 434008d12931..b038349f64c7 100644 --- a/boards/nxp/frdm_k82f/frdm_k82f.dts +++ b/boards/nxp/frdm_k82f/frdm_k82f.dts @@ -7,7 +7,7 @@ /dts-v1/; #include -#include +#include #include #include "frdm_k82f-pinctrl.dtsi" #include diff --git a/boards/nxp/frdm_ke15z/doc/index.rst b/boards/nxp/frdm_ke15z/doc/index.rst index 42a5f13050b5..a134482dabb3 100644 --- a/boards/nxp/frdm_ke15z/doc/index.rst +++ b/boards/nxp/frdm_ke15z/doc/index.rst @@ -37,7 +37,7 @@ Supported Features System Clock ============ -The KE15 SoC is configured to run at 48 MHz using the FIRC. +The KE15 SoC is configured to run at 72 MHz using the LPFLL. Serial Port =========== diff --git a/boards/nxp/frdm_ke15z/frdm_ke15z-pinctrl.dtsi b/boards/nxp/frdm_ke15z/frdm_ke15z-pinctrl.dtsi index 78f93888f925..0e94db0b02fa 100644 --- a/boards/nxp/frdm_ke15z/frdm_ke15z-pinctrl.dtsi +++ b/boards/nxp/frdm_ke15z/frdm_ke15z-pinctrl.dtsi @@ -6,6 +6,14 @@ #include &pinctrl { + adc0_default: adc0_default { + group0 { + pinmux = ; + drive-strength = "low"; + slew-rate = "slow"; + }; + }; + lpuart1_default: lpuart1_default { group0 { pinmux = , diff --git a/boards/nxp/frdm_ke15z/frdm_ke15z.dts b/boards/nxp/frdm_ke15z/frdm_ke15z.dts index 68d5f27ba71c..2cead345b9b7 100644 --- a/boards/nxp/frdm_ke15z/frdm_ke15z.dts +++ b/boards/nxp/frdm_ke15z/frdm_ke15z.dts @@ -1,12 +1,12 @@ /* - * Copyright 2024 NXP + * Copyright 2024-2025 NXP * * SPDX-License-Identifier: Apache-2.0 */ /dts-v1/; -#include +#include #include "frdm_ke15z-pinctrl.dtsi" #include #include @@ -16,6 +16,7 @@ compatible = "nxp,ke15z", "nxp,mke15z7"; aliases { + watchdog0 = &wdog; led0 = &green_led; led1 = &blue_led; led2 = &red_led; @@ -102,6 +103,14 @@ pinctrl-names = "default"; }; +&adc0 { + status = "okay"; + sample-time = <12>; + vref-mv = <3300>; + pinctrl-0 = <&adc0_default>; + pinctrl-names = "default"; +}; + &gpiob { status = "okay"; }; @@ -109,3 +118,7 @@ &gpiod { status = "okay"; }; + +&wdog { + status = "okay"; +}; diff --git a/boards/nxp/frdm_ke15z/frdm_ke15z.yaml b/boards/nxp/frdm_ke15z/frdm_ke15z.yaml index c7296fc12ea3..faa24903d8d3 100644 --- a/boards/nxp/frdm_ke15z/frdm_ke15z.yaml +++ b/boards/nxp/frdm_ke15z/frdm_ke15z.yaml @@ -8,6 +8,8 @@ toolchain: flash: 256 ram: 24 supported: + - adc - flash - gpio - uart + - watchdog diff --git a/boards/nxp/frdm_ke16z/frdm_ke16z.dts b/boards/nxp/frdm_ke16z/frdm_ke16z.dts index 673b25498b0d..50bef3d4bb0c 100644 --- a/boards/nxp/frdm_ke16z/frdm_ke16z.dts +++ b/boards/nxp/frdm_ke16z/frdm_ke16z.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "frdm_ke16z-pinctrl.dtsi" #include diff --git a/boards/nxp/frdm_ke17z/doc/index.rst b/boards/nxp/frdm_ke17z/doc/index.rst index f99b6b7ac776..5e1d505f79db 100644 --- a/boards/nxp/frdm_ke17z/doc/index.rst +++ b/boards/nxp/frdm_ke17z/doc/index.rst @@ -39,7 +39,7 @@ Supported Features System Clock ============ -The KE17Z SoC is configured to run at 48 MHz using the FIRC. +The KE17Z SoC is configured to run at 72 MHz using the LPFLL. Serial Port =========== diff --git a/boards/nxp/frdm_ke17z/frdm_ke17z.dts b/boards/nxp/frdm_ke17z/frdm_ke17z.dts index 173c2298a99a..69ad94424fcf 100644 --- a/boards/nxp/frdm_ke17z/frdm_ke17z.dts +++ b/boards/nxp/frdm_ke17z/frdm_ke17z.dts @@ -1,12 +1,12 @@ /* - * Copyright 2024 NXP + * Copyright 2024-2025 NXP * * SPDX-License-Identifier: Apache-2.0 */ /dts-v1/; -#include +#include #include "frdm_ke17z-pinctrl.dtsi" #include #include @@ -36,6 +36,7 @@ zephyr,uart-mcumgr = &lpuart0; zephyr,console = &lpuart0; zephyr,shell-uart = &lpuart0; + zephyr,cortex-m-idle-timer = &lptmr0; }; leds { @@ -126,11 +127,6 @@ min-residency-us = <1>; }; -&stop { - min-residency-us = <20000>; - exit-latency-us = <13>; -}; - &lpuart0 { dmas = <&edma 1 2>, <&edma 2 3>; dma-names = "rx", "tx"; diff --git a/boards/nxp/frdm_ke17z512/doc/index.rst b/boards/nxp/frdm_ke17z512/doc/index.rst index 710564561c2e..ad7e82e07e3d 100644 --- a/boards/nxp/frdm_ke17z512/doc/index.rst +++ b/boards/nxp/frdm_ke17z512/doc/index.rst @@ -40,7 +40,7 @@ Supported Features System Clock ============ -The KE17Z9 SoC is configured to run at 48 MHz using the FIRC. +The KE17Z9 SoC is configured to run at 72 MHz using the LPFLL. Serial Port =========== diff --git a/boards/nxp/frdm_ke17z512/frdm_ke17z512.dts b/boards/nxp/frdm_ke17z512/frdm_ke17z512.dts index 4a27fbc89e77..dab675ff14c2 100644 --- a/boards/nxp/frdm_ke17z512/frdm_ke17z512.dts +++ b/boards/nxp/frdm_ke17z512/frdm_ke17z512.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "frdm_ke17z512-pinctrl.dtsi" #include #include diff --git a/boards/nxp/frdm_kl25z/doc/index.rst b/boards/nxp/frdm_kl25z/doc/index.rst index 06cbe4db6dad..570e8530aa7c 100644 --- a/boards/nxp/frdm_kl25z/doc/index.rst +++ b/boards/nxp/frdm_kl25z/doc/index.rst @@ -4,8 +4,8 @@ Overview ******** The Freedom KL25Z is an ultra-low-cost development platform for -Kinetis |reg| L Series KL1x (KL14/15) and KL2x (KL24/25) MCUs built -on ARM |reg| Cortex |reg|-M0+ processor. +Kinetis® L Series KL1x (KL14/15) and KL2x (KL24/25) MCUs built +on ARM® Cortex®-M0+ processor. The FRDM-KL25Z features include easy access to MCU I/O, battery-ready, low-power operation, a standard-based form factor with expansion board diff --git a/boards/nxp/frdm_kl25z/frdm_kl25z.dts b/boards/nxp/frdm_kl25z/frdm_kl25z.dts index 4dedaec6b45f..e94938191d55 100644 --- a/boards/nxp/frdm_kl25z/frdm_kl25z.dts +++ b/boards/nxp/frdm_kl25z/frdm_kl25z.dts @@ -1,8 +1,12 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ /dts-v1/; -#include +#include #include "frdm_kl25z-pinctrl.dtsi" #include #include diff --git a/boards/nxp/frdm_kw41z/doc/index.rst b/boards/nxp/frdm_kw41z/doc/index.rst index 1fb022370890..5fc48205b641 100644 --- a/boards/nxp/frdm_kw41z/doc/index.rst +++ b/boards/nxp/frdm_kw41z/doc/index.rst @@ -3,15 +3,15 @@ Overview ******** -The FRDM-KW41Z is a development kit enabled by the Kinetis |reg| W series -KW41Z/31Z/21Z (KW41Z) family built on ARM |reg| Cortex |reg|-M0+ processor with -integrated 2.4 GHz transceiver supporting Bluetooth |reg| Smart/Bluetooth -|reg| Low Energy -(BLE) v4.2, Generic FSK, IEEE |reg| 802.15.4 and Thread. +The FRDM-KW41Z is a development kit enabled by the Kinetis® W series +KW41Z/31Z/21Z (KW41Z) family built on ARM® Cortex®-M0+ processor with +integrated 2.4 GHz transceiver supporting Bluetooth® Smart/Bluetooth® +Low Energy +(BLE) v4.2, Generic FSK, IEEE® 802.15.4 and Thread. The FRDM-KW41Z kit contains two Freedom boards that can be used as a development board or a shield to connect to a host processor. The FRDM-KW41Z is -form-factor compatible with the Arduino |trade| R3 pin layout for more expansion +form-factor compatible with the Arduino™ R3 pin layout for more expansion options. The FRDM-KW41Z highly-sensitive, optimized 2.4 GHz radio features a PCB @@ -28,8 +28,8 @@ Hardware - SMA RF Connector - RF regulatory certified - Serial Flash for OTA firmware upgrades -- On board NXP FXOS8700CQ digital sensor, 3D Accelerometer ( |plusminus| 2g/ - |plusminus| 4g/ |plusminus| 8g) + 3D +- On board NXP FXOS8700CQ digital sensor, 3D Accelerometer (±2g/ + ±4g/ ±8g) + 3D Magnetometer - OpenSDA and JTAG debug diff --git a/boards/nxp/frdm_kw41z/frdm_kw41z.dts b/boards/nxp/frdm_kw41z/frdm_kw41z.dts index a898ac91b1b9..4af985aa705e 100644 --- a/boards/nxp/frdm_kw41z/frdm_kw41z.dts +++ b/boards/nxp/frdm_kw41z/frdm_kw41z.dts @@ -1,8 +1,12 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ /dts-v1/; -#include +#include #include "frdm_kw41z-pinctrl.dtsi" #include #include diff --git a/boards/nxp/frdm_mcxa153/frdm_mcxa153.dts b/boards/nxp/frdm_mcxa153/frdm_mcxa153.dts index 299e324f2267..0a974e56ccee 100644 --- a/boards/nxp/frdm_mcxa153/frdm_mcxa153.dts +++ b/boards/nxp/frdm_mcxa153/frdm_mcxa153.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "frdm_mcxa153-pinctrl.dtsi" #include #include @@ -36,6 +36,7 @@ zephyr,console = &lpuart0; zephyr,shell-uart = &lpuart0; zephyr,edac = &erm0; + zephyr,cortex-m-idle-timer = &lptmr0; }; leds { @@ -168,9 +169,9 @@ reg = <0x00012000 DT_SIZE_K(40)>; }; - storage_partition: partition@1C000 { + storage_partition: partition@1c000 { label = "storage"; - reg = <0x0001C000 DT_SIZE_K(16)>; + reg = <0x0001c000 DT_SIZE_K(16)>; }; }; }; @@ -219,12 +220,6 @@ pinctrl-names = "default"; }; -&lpcmp0 { - status = "okay"; - pinctrl-0 = <&pinmux_lpcmp0>; - pinctrl-names = "default"; -}; - &lpi2c0 { status = "okay"; pinctrl-0 = <&pinmux_lpi2c0>; diff --git a/boards/nxp/frdm_mcxa153/frdm_mcxa153.yaml b/boards/nxp/frdm_mcxa153/frdm_mcxa153.yaml index 252b7233cc6f..96915a6de2c0 100644 --- a/boards/nxp/frdm_mcxa153/frdm_mcxa153.yaml +++ b/boards/nxp/frdm_mcxa153/frdm_mcxa153.yaml @@ -5,7 +5,7 @@ # identifier: frdm_mcxa153 -name: NXP FRDM MCXA153 +name: NXP FRDM-MCXA153 type: mcu arch: arm ram: 24 diff --git a/boards/nxp/frdm_mcxa156/doc/index.rst b/boards/nxp/frdm_mcxa156/doc/index.rst index 73583587752f..accb1680b445 100644 --- a/boards/nxp/frdm_mcxa156/doc/index.rst +++ b/boards/nxp/frdm_mcxa156/doc/index.rst @@ -36,6 +36,15 @@ Supported Features .. zephyr:board-supported-hw:: +Shields for Supported Features +============================== + +Some features in the table above are tested with Zephyr shields. These shields +are tested on this board: + +- :ref:`lcd_par_s035` - supports the Display interface. This board uses the + MIPI_DBI interface of the shield, connected to the FlexIO on-chip peripheral. + Connections and IOs =================== diff --git a/boards/nxp/frdm_mcxa156/frdm_mcxa156.dts b/boards/nxp/frdm_mcxa156/frdm_mcxa156.dts index c9bc5607ca3b..9d064b162aa8 100644 --- a/boards/nxp/frdm_mcxa156/frdm_mcxa156.dts +++ b/boards/nxp/frdm_mcxa156/frdm_mcxa156.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "frdm_mcxa156-pinctrl.dtsi" #include #include @@ -38,6 +38,7 @@ zephyr,shell-uart = &lpuart0; zephyr,uart-mcumgr = &lpuart0; zephyr,canbus = &flexcan0; + zephyr,cortex-m-idle-timer = &lptmr0; }; leds { @@ -229,12 +230,6 @@ zephyr_mipi_dbi_parallel: &flexio0_lcd { pinctrl-names = "default"; }; -&lpcmp0 { - status = "okay"; - pinctrl-0 = <&pinmux_lpcmp0>; - pinctrl-names = "default"; -}; - &opamp0 { status = "okay"; pinctrl-0 = <&pinmux_opamp0>; diff --git a/boards/nxp/frdm_mcxa156/frdm_mcxa156.yaml b/boards/nxp/frdm_mcxa156/frdm_mcxa156.yaml index af20bcd7445b..c9be3adf3b5f 100644 --- a/boards/nxp/frdm_mcxa156/frdm_mcxa156.yaml +++ b/boards/nxp/frdm_mcxa156/frdm_mcxa156.yaml @@ -5,7 +5,7 @@ # identifier: frdm_mcxa156 -name: NXP FRDM MCXA156 +name: NXP FRDM-MCXA156 type: mcu arch: arm ram: 128 diff --git a/boards/nxp/frdm_mcxa344/board.c b/boards/nxp/frdm_mcxa344/board.c index 4163c88b0bd1..c8b77fad3e90 100644 --- a/boards/nxp/frdm_mcxa344/board.c +++ b/boards/nxp/frdm_mcxa344/board.c @@ -109,6 +109,11 @@ void board_early_init_hook(void) CLOCK_AttachClk(kFRO_HF_to_CTIMER2); #endif +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcan0)) + CLOCK_SetClockDiv(kCLOCK_DivFLEXCAN0, 3U); + CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCAN0); +#endif + #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio0)) RESET_ReleasePeripheralReset(kGPIO0_RST_SHIFT_RSTn); CLOCK_EnableClock(kCLOCK_GateGPIO0); @@ -134,6 +139,38 @@ void board_early_init_hook(void) CLOCK_EnableClock(kCLOCK_GateGPIO4); #endif +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpadc0)) + CLOCK_SetClockDiv(kCLOCK_DivADC, 3u); + CLOCK_AttachClk(kFRO_HF_to_ADC); + CLOCK_EnableClock(kCLOCK_GateADC0); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpadc1)) + CLOCK_SetClockDiv(kCLOCK_DivADC, 3u); + CLOCK_AttachClk(kFRO_HF_to_ADC); + CLOCK_EnableClock(kCLOCK_GateADC1); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpi2c0)) + CLOCK_SetClockDiv(kCLOCK_DivLPI2C0, 1u); + CLOCK_AttachClk(kFRO_LF_DIV_to_LPI2C0); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpi2c1)) + CLOCK_SetClockDiv(kCLOCK_DivLPI2C1, 1u); + CLOCK_AttachClk(kFRO_LF_DIV_to_LPI2C1); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpspi0)) + CLOCK_SetClockDiv(kCLOCK_DivLPSPI0, 1u); + CLOCK_AttachClk(kFRO_LF_DIV_to_LPSPI0); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpspi1)) + CLOCK_SetClockDiv(kCLOCK_DivLPSPI1, 1u); + CLOCK_AttachClk(kFRO_LF_DIV_to_LPSPI1); +#endif + #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lptmr0)) /* @@ -177,6 +214,10 @@ void board_early_init_hook(void) RESET_ReleasePeripheralReset(kLPUART3_RST_SHIFT_RSTn); #endif +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(wwdt0)) + CLOCK_SetClockDiv(kCLOCK_DivWWDT0, 1u); +#endif + /* Set SystemCoreClock variable. */ SystemCoreClock = CLOCK_INIT_CORE_CLOCK; } diff --git a/boards/nxp/frdm_mcxa344/frdm_mcxa344-pinctrl.dtsi b/boards/nxp/frdm_mcxa344/frdm_mcxa344-pinctrl.dtsi index cc94e3423317..cb5e019047c4 100644 --- a/boards/nxp/frdm_mcxa344/frdm_mcxa344-pinctrl.dtsi +++ b/boards/nxp/frdm_mcxa344/frdm_mcxa344-pinctrl.dtsi @@ -6,6 +6,72 @@ #include &pinctrl { + pinmux_flexcan0: pinmux_flexcan0 { + group0 { + pinmux = , + ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + }; + }; + + pinmux_lpadc0: pinmux_lpadc0 { + group0 { + pinmux = ; + slew-rate = "fast"; + drive-strength = "low"; + }; + }; + + pinmux_lpi2c0: pinmux_lpi2c0 { + group0 { + pinmux = , + ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + bias-pull-up; + drive-open-drain; + }; + }; + + pinmux_lpi2c1: pinmux_lpi2c1 { + group0 { + pinmux = , + ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + bias-pull-up; + drive-open-drain; + }; + }; + + pinmux_lpspi0: pinmux_lpspi0 { + group0 { + pinmux = , + , + , + ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + }; + }; + + pinmux_lpspi1: pinmux_lpspi1 { + group0 { + pinmux = , + , + , + ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + }; + }; + pinmux_lpuart2: pinmux_lpuart2 { group0 { pinmux = , diff --git a/boards/nxp/frdm_mcxa344/frdm_mcxa344.dts b/boards/nxp/frdm_mcxa344/frdm_mcxa344.dts index 7ab11baf64ee..35ac56bc9184 100644 --- a/boards/nxp/frdm_mcxa344/frdm_mcxa344.dts +++ b/boards/nxp/frdm_mcxa344/frdm_mcxa344.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "frdm_mcxa344-pinctrl.dtsi" #include #include @@ -21,6 +21,8 @@ led2 = &blue_led; sw0 = &user_button_2; sw1 = &user_button_3; + watchdog0 = &wwdt0; + die-temp0 = &temp0; }; chosen { @@ -30,6 +32,7 @@ zephyr,code-partition = &slot0_partition; zephyr,console = &lpuart2; zephyr,shell-uart = &lpuart2; + zephyr,canbus = &flexcan0; }; leds { @@ -126,9 +129,9 @@ reg = <0x00004000 DT_SIZE_K(100)>; }; - slot1_partition: partition@1D000 { + slot1_partition: partition@1d000 { label = "image-1"; - reg = <0x0001D000 DT_SIZE_K(100)>; + reg = <0x0001d000 DT_SIZE_K(100)>; }; storage_partition: partition@36000 { @@ -138,6 +141,12 @@ }; }; +&flexcan0 { + status = "okay"; + pinctrl-0 = <&pinmux_flexcan0>; + pinctrl-names = "default"; +}; + &gpio0 { status = "okay"; }; @@ -158,6 +167,30 @@ status = "okay"; }; +&lpadc0 { + status = "okay"; + pinctrl-0 = <&pinmux_lpadc0>; + pinctrl-names = "default"; +}; + +&lpi2c0 { + status = "okay"; + pinctrl-0 = <&pinmux_lpi2c0>; + pinctrl-names = "default"; +}; + +&lpi2c1 { + status = "okay"; + pinctrl-0 = <&pinmux_lpi2c1>; + pinctrl-names = "default"; +}; + +&lpspi1 { + status = "okay"; + pinctrl-0 = <&pinmux_lpspi1>; + pinctrl-names = "default"; +}; + &lptmr0 { status = "okay"; }; @@ -168,3 +201,7 @@ pinctrl-0 = <&pinmux_lpuart2>; pinctrl-names = "default"; }; + +&wwdt0 { + status = "okay"; +}; diff --git a/boards/nxp/frdm_mcxa344/frdm_mcxa344.yaml b/boards/nxp/frdm_mcxa344/frdm_mcxa344.yaml index 073b5099c13d..2c855103b521 100644 --- a/boards/nxp/frdm_mcxa344/frdm_mcxa344.yaml +++ b/boards/nxp/frdm_mcxa344/frdm_mcxa344.yaml @@ -5,7 +5,7 @@ # identifier: frdm_mcxa344 -name: NXP FRDM MCXA344 +name: NXP FRDM-MCXA344 type: mcu arch: arm ram: 48 @@ -14,9 +14,14 @@ toolchain: - zephyr - gnuarmemb supported: + - adc - arduino_gpio + - can - counter - flash - gpio + - i2c + - spi - uart + - watchdog vendor: nxp diff --git a/boards/nxp/frdm_mcxa577/CMakeLists.txt b/boards/nxp/frdm_mcxa577/CMakeLists.txt new file mode 100644 index 000000000000..c06b9273965c --- /dev/null +++ b/boards/nxp/frdm_mcxa577/CMakeLists.txt @@ -0,0 +1,8 @@ +# +# Copyright 2025 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_library() +zephyr_library_sources(board.c) diff --git a/boards/nxp/frdm_mcxa577/Kconfig b/boards/nxp/frdm_mcxa577/Kconfig new file mode 100644 index 000000000000..d7c509900da3 --- /dev/null +++ b/boards/nxp/frdm_mcxa577/Kconfig @@ -0,0 +1,5 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_FRDM_MCXA577 + select BOARD_EARLY_INIT_HOOK diff --git a/boards/nxp/frdm_mcxa577/Kconfig.frdm_mcxa577 b/boards/nxp/frdm_mcxa577/Kconfig.frdm_mcxa577 new file mode 100644 index 000000000000..f27d6eff76fc --- /dev/null +++ b/boards/nxp/frdm_mcxa577/Kconfig.frdm_mcxa577 @@ -0,0 +1,6 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_FRDM_MCXA577 + select SOC_MCXA577 + select SOC_PART_NUMBER_MCXA577VLL diff --git a/boards/nxp/frdm_mcxa577/board.c b/boards/nxp/frdm_mcxa577/board.c new file mode 100644 index 000000000000..06f8e8bb30f0 --- /dev/null +++ b/boards/nxp/frdm_mcxa577/board.c @@ -0,0 +1,260 @@ +/* + * Copyright 2025 NXP + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include +#include +#include +#include + +/* Core clock frequency: 200MHz from PLL */ +#define CLOCK_INIT_CORE_CLOCK 200000000U +/* System clock frequency. */ +extern uint32_t SystemCoreClock; + +void board_early_init_hook(void) +{ + spc_active_mode_core_ldo_option_t ldoOption; + spc_sram_voltage_config_t sramOption; + + /* Get the CPU Core frequency */ + CLOCK_SetupFRO12MClocking(); + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); + CLOCK_SetClockDiv(kCLOCK_DivFRO_HF, 1); + CLOCK_SetClockDiv(kCLOCK_DivFRO_LF, 1); + + /* Set the LDO_CORE VDD regulator level */ + ldoOption.CoreLDOVoltage = kSPC_CoreLDO_OverDriveVoltage; + ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; + (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); + /* Configure Flash to support different voltage level and frequency */ + CLOCK_SetFLASHAccessCyclesForFreq(CLOCK_INIT_CORE_CLOCK, kOD_Mode); + /* Specifies the operating voltage for the SRAM's read/write timing margin */ + sramOption.operateVoltage = kSPC_sramOperateAt1P2V; + sramOption.requestVoltageUpdate = true; + (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); + + /*!< Set up system dividers */ + CLOCK_SetClockDiv(kCLOCK_DivFRO_HF, 4U); /* !< Set SYSCON.FROHFDIV divider to value 4 */ + CLOCK_SetupFROHFClocking(192000000U); /*!< Enable FRO HF(192MHz) output */ + CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */ + CLOCK_SetupExtClocking(24000000U); /*!< Enable OSC with 24000000 HZ */ + CLOCK_SetSysOscMonitorMode( + kSCG_SysOscMonitorDisable); /* System OSC Clock Monitor is disabled */ + + /*!< Set up PLL1 */ + const pll_setup_t pll1Setup = {.pllctrl = SCG_SPLLCTRL_SOURCE(0U) | SCG_SPLLCTRL_SELI(53U) | + SCG_SPLLCTRL_SELP(26U) | + SCG_SPLLCTRL_BYPASSPOSTDIV2_MASK, + .pllndiv = SCG_SPLLNDIV_NDIV(6U), + .pllpdiv = SCG_SPLLPDIV_PDIV(2U), + .pllmdiv = SCG_SPLLMDIV_MDIV(100U), + .pllRate = 200000000U}; + CLOCK_SetPLL1Freq(&pll1Setup); /*!< Configure PLL1 to the desired values */ + CLOCK_SetPll1MonitorMode(kSCG_Pll1MonitorDisable); /* Pll1 Monitor is disabled */ + + CLOCK_AttachClk(kPll1Clk_to_MAIN_CLK); /* !< Switch MAIN_CLK to kPll1Clk */ + + /*!< Set up dividers */ + CLOCK_SetClockDiv(kCLOCK_DivFRO_LF, 1U); /* !< Set SYSCON.FROLFDIV divider to value 1 */ + CLOCK_SetClockDiv(kCLOCK_DivPLL1CLK, 4U); /* !< Set SYSCON.PLL1CLKDIV divider to value 4 */ + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(porta)) + RESET_ReleasePeripheralReset(kPORT0_RST_SHIFT_RSTn); + CLOCK_EnableClock(kCLOCK_GatePORT0); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(portb)) + RESET_ReleasePeripheralReset(kPORT1_RST_SHIFT_RSTn); + CLOCK_EnableClock(kCLOCK_GatePORT1); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(portc)) + RESET_ReleasePeripheralReset(kPORT2_RST_SHIFT_RSTn); + CLOCK_EnableClock(kCLOCK_GatePORT2); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(portd)) + RESET_ReleasePeripheralReset(kPORT3_RST_SHIFT_RSTn); + CLOCK_EnableClock(kCLOCK_GatePORT3); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(porte)) + RESET_ReleasePeripheralReset(kPORT4_RST_SHIFT_RSTn); + CLOCK_EnableClock(kCLOCK_GatePORT4); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(portf)) + CLOCK_EnableClock(kCLOCK_GatePORT5); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio0)) + RESET_ReleasePeripheralReset(kGPIO0_RST_SHIFT_RSTn); + CLOCK_EnableClock(kCLOCK_GateGPIO0); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio1)) + RESET_ReleasePeripheralReset(kGPIO1_RST_SHIFT_RSTn); + CLOCK_EnableClock(kCLOCK_GateGPIO1); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio2)) + RESET_ReleasePeripheralReset(kGPIO2_RST_SHIFT_RSTn); + CLOCK_EnableClock(kCLOCK_GateGPIO2); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio3)) + RESET_ReleasePeripheralReset(kGPIO3_RST_SHIFT_RSTn); + CLOCK_EnableClock(kCLOCK_GateGPIO3); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio4)) + RESET_ReleasePeripheralReset(kGPIO4_RST_SHIFT_RSTn); + CLOCK_EnableClock(kCLOCK_GateGPIO4); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio5)) + CLOCK_EnableClock(kCLOCK_GateGPIO5); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart0)) + CLOCK_SetClockDiv(kCLOCK_DivLPUART0, 1u); + CLOCK_AttachClk(kFRO_LF_DIV_to_LPUART0); + RESET_ReleasePeripheralReset(kLPUART0_RST_SHIFT_RSTn); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart1)) + CLOCK_SetClockDiv(kCLOCK_DivLPUART1, 1u); + CLOCK_AttachClk(kPll1ClkDiv_to_LPUART1); + RESET_ReleasePeripheralReset(kLPUART1_RST_SHIFT_RSTn); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart2)) + CLOCK_SetClockDiv(kCLOCK_DivLPUART2, 1u); + CLOCK_AttachClk(kFRO_LF_DIV_to_LPUART2); + RESET_ReleasePeripheralReset(kLPUART2_RST_SHIFT_RSTn); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart3)) + CLOCK_SetClockDiv(kCLOCK_DivLPUART3, 1u); + CLOCK_AttachClk(kFRO_LF_DIV_to_LPUART3); + RESET_ReleasePeripheralReset(kLPUART3_RST_SHIFT_RSTn); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart4)) + CLOCK_SetClockDiv(kCLOCK_DivLPUART4, 1u); + CLOCK_AttachClk(kFRO_LF_DIV_to_LPUART4); + RESET_ReleasePeripheralReset(kLPUART4_RST_SHIFT_RSTn); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart5)) + CLOCK_SetClockDiv(kCLOCK_DivLPUART5, 1u); + CLOCK_AttachClk(kFRO_LF_DIV_to_LPUART5); + RESET_ReleasePeripheralReset(kLPUART5_RST_SHIFT_RSTn); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpi2c0)) + CLOCK_SetClockDiv(kCLOCK_DivLPI2C0, 1u); + CLOCK_AttachClk(kFRO_LF_DIV_to_LPI2C0); + RESET_ReleasePeripheralReset(kLPI2C0_RST_SHIFT_RSTn); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpi2c1)) + CLOCK_SetClockDiv(kCLOCK_DivLPI2C1, 1u); + CLOCK_AttachClk(kFRO_LF_DIV_to_LPI2C1); + RESET_ReleasePeripheralReset(kLPI2C1_RST_SHIFT_RSTn); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpi2c2)) + CLOCK_SetClockDiv(kCLOCK_DivLPI2C2, 1u); + CLOCK_AttachClk(kFRO_LF_DIV_to_LPI2C2); + RESET_ReleasePeripheralReset(kLPI2C2_RST_SHIFT_RSTn); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpi2c3)) + CLOCK_SetClockDiv(kCLOCK_DivLPI2C3, 1u); + CLOCK_AttachClk(kFRO_LF_DIV_to_LPI2C3); + RESET_ReleasePeripheralReset(kLPI2C3_RST_SHIFT_RSTn); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpi2c4)) + CLOCK_SetClockDiv(kCLOCK_DivLPI2C4, 1u); + CLOCK_AttachClk(kFRO_LF_DIV_to_LPI2C4); + RESET_ReleasePeripheralReset(kLPI2C4_RST_SHIFT_RSTn); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ctimer0)) + CLOCK_SetClockDiv(kCLOCK_DivCTIMER0, 1u); + CLOCK_AttachClk(kPll1ClkDiv_to_CTIMER0); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ctimer1)) + CLOCK_SetClockDiv(kCLOCK_DivCTIMER1, 1u); + CLOCK_AttachClk(kPll1ClkDiv_to_CTIMER1); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ctimer2)) + CLOCK_SetClockDiv(kCLOCK_DivCTIMER2, 1u); + CLOCK_AttachClk(kPll1ClkDiv_to_CTIMER2); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ctimer3)) + CLOCK_SetClockDiv(kCLOCK_DivCTIMER3, 1u); + CLOCK_AttachClk(kPll1ClkDiv_to_CTIMER3); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ctimer4)) + CLOCK_SetClockDiv(kCLOCK_DivCTIMER4, 1u); + CLOCK_AttachClk(kPll1ClkDiv_to_CTIMER4); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lptmr0)) + +/* + * Clock Select Decides what input source the lptmr will clock from + * + * 0 <- Reserved + * 1 <- 16K FRO + * 2 <- Reserved + * 3 <- Combination of clocks configured in MRCC_LPTMR0_CLKSEL[MUX] field + */ +#if DT_PROP(DT_NODELABEL(lptmr0), clk_source) == 0x1 + CLOCK_SetupFRO16KClocking(kCLKE_16K_SYSTEM | kCLKE_16K_COREMAIN | kCLKE_16K_VBAT); +#elif DT_PROP(DT_NODELABEL(lptmr0), clk_source) == 0x3 + CLOCK_AttachClk(kFRO_LF_DIV_to_LPTMR0); + CLOCK_SetClockDiv(kCLOCK_DivLPTMR0, 1u); +#endif /* DT_PROP(DT_NODELABEL(lptmr0), clk_source) */ + +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(edma0)) + RESET_ReleasePeripheralReset(kDMA0_RST_SHIFT_RSTn); + CLOCK_EnableClock(kCLOCK_GateDMA0); + /* Release DMA0 request */ + for (uint8_t i = 0; i < AHBSC_SEC_GP_REG_COUNT/2; i++) { + AHBSC->SEC_GP_REG[i] = 0xFFFFFFFF; + } +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(edma1)) + RESET_ReleasePeripheralReset(kDMA1_RST_SHIFT_RSTn); + CLOCK_EnableClock(kCLOCK_GateDMA1); + /* Release DMA1 request */ + for (uint8_t i = AHBSC_SEC_GP_REG_COUNT/2; i < AHBSC_SEC_GP_REG_COUNT; i++) { + AHBSC->SEC_GP_REG[i] = 0xFFFFFFFF; + } +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(wwdt0)) + CLOCK_SetClockDiv(kCLOCK_DivWWDT0, 1u); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(wwdt1)) + CLOCK_SetClockDiv(kCLOCK_DivWWDT1, 1u); +#endif + + /* Set SystemCoreClock variable. */ + SystemCoreClock = CLOCK_INIT_CORE_CLOCK; +} diff --git a/boards/nxp/frdm_mcxa577/board.cmake b/boards/nxp/frdm_mcxa577/board.cmake new file mode 100644 index 000000000000..661ad2e4f430 --- /dev/null +++ b/boards/nxp/frdm_mcxa577/board.cmake @@ -0,0 +1,13 @@ +# +# Copyright 2025 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +board_runner_args(jlink "--device=MCXA577") +board_runner_args(linkserver "--device=MCXA577:FRDM-MCXA577") +board_runner_args(pyocd "--target=MCXA577") + +include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/nxp/frdm_mcxa577/board.yml b/boards/nxp/frdm_mcxa577/board.yml new file mode 100644 index 000000000000..67736950e571 --- /dev/null +++ b/boards/nxp/frdm_mcxa577/board.yml @@ -0,0 +1,6 @@ +board: + name: frdm_mcxa577 + full_name: FRDM-MCXA577 + vendor: nxp + socs: + - name: mcxa577 diff --git a/boards/nxp/frdm_mcxa577/doc/frdm_mcxa577.webp b/boards/nxp/frdm_mcxa577/doc/frdm_mcxa577.webp new file mode 100644 index 000000000000..7412adb76ac8 Binary files /dev/null and b/boards/nxp/frdm_mcxa577/doc/frdm_mcxa577.webp differ diff --git a/boards/nxp/frdm_mcxa577/doc/index.rst b/boards/nxp/frdm_mcxa577/doc/index.rst new file mode 100644 index 000000000000..9f075d82b2e1 --- /dev/null +++ b/boards/nxp/frdm_mcxa577/doc/index.rst @@ -0,0 +1,169 @@ +.. zephyr:board:: frdm_mcxa577 + +Overview +******** + +FRDM-MCXA577 is a compact and scalable development board for rapid prototyping of MCX A577 +MCUs. They offer industry standard headers for easy access to the MCUs input/output (I/O), +integrated open-standard serial interfaces, external flash memory and an onboard MCU-Link +debugger. + +Hardware +******** + +- MCX-A577 Arm Cortex-M33 microcontroller running at 12MHz +- 2048KB dual-bank on chip Flash +- 640 KB RAM +- 2x FlexCAN with FD, 1x RGB LED, 3x SW buttons +- On-board MCU-Link debugger with CMSIS-DAP +- Arduino Header, SmartDMA/Camera Header, mikroBUS + +For more information about the MCX-A577 SoC and FRDM-MCXA577 board, see: + +- `MCX-A577 SoC Website`_ +- `FRDM-MCXA577 Website`_ +- `FRDM-MCXA577 User Guide`_ + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Shields for Supported Features +============================== + +Some features in the table above are tested with Zephyr shields. These shields +are tested on this board: + +- :ref:`lcd_par_s035` - supports the Display interface. This board uses the + MIPI_DBI interface of the shield, connected to the FlexIO on-chip peripheral. + +Connections and IOs +=================== + +The MCX-A577 SoC has 5 gpio controllers and has pinmux registers which +can be used to configure the functionality of a pin. + ++------------+-----------------+----------------------------+ +| Name | Function | Usage | ++============+=================+============================+ +| PIO0_2 | UART | UART RX | ++------------+-----------------+----------------------------+ +| PIO0_3 | UART | UART TX | ++------------+-----------------+----------------------------+ + +System Clock +============ + +The MCX-A577 SoC is configured to use FRO LF running at 12MHz as a source for +the system clock. + +Serial Port +=========== + +The FRDM-MCXA577 SoC has 6 LPUART interfaces for serial communication. +LPUART0 is configured as UART for the console. + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the MCU-Link CMSIS-DAP Onboard Debug Probe. + +Using LinkServer +---------------- + +Linkserver is the default runner for this board, and supports the factory +default MCU-Link firmware. Follow the instructions in +:ref:`mcu-link-cmsis-onboard-debug-probe` to reprogram the default MCU-Link +firmware. This only needs to be done if the default onboard debug circuit +firmware was changed. To put the board in ``ISP mode`` to program the firmware, +short jumper JP4. + +Using J-Link +------------ + +There are two options. The onboard debug circuit can be updated with Segger +J-Link firmware by following the instructions in +:ref:`mcu-link-jlink-onboard-debug-probe`. +To be able to program the firmware, you need to put the board in ``ISP mode`` +by shortening the jumper JP4. +The second option is to attach a :ref:`jlink-external-debug-probe` to the +10-pin SWD connector (J11) of the board. Additionally, the jumper JP6 must +be shorted. +For both options use the ``-r jlink`` option with west to use the jlink runner. + +.. code-block:: console + + west flash -r jlink + +Configuring a Console +===================== + +Connect a USB cable from your PC to J13, and use the serial terminal of your choice +(minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: frdm_mcxa577 + :goals: flash + +Open a serial terminal, reset the board (press the RESET button), and you should +see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build v3.6.0-4478-ge6c3a42f5f52 *** + Hello World! frdm_mcxa577/mcxa577 + +Debugging +========= + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: frdm_mcxa577/mcxa577 + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build v3.6.0-4478-ge6c3a42f5f52 *** + Hello World! frdm_mcxa577/mcxa577 + +Troubleshooting +=============== + +.. include:: ../../common/segger-ecc-systemview.rst.inc + +.. include:: ../../common/board-footer.rst.inc + +.. _MCX-A577 SoC Website: + https://www.nxp.com/products/MCX-A57X + +.. _FRDM-MCXA577 Website: + https://www.nxp.com/design/design-center/development-boards-and-designs/FRDM-MCXA577 + +.. _FRDM-MCXA577 User Guide: + https://www.nxp.com/document/guide/getting-started-with-frdm-mcxa577:GS-FRDM-MCXA577 diff --git a/boards/nxp/frdm_mcxa577/frdm_mcxa577-pinctrl.dtsi b/boards/nxp/frdm_mcxa577/frdm_mcxa577-pinctrl.dtsi new file mode 100644 index 000000000000..eee06d3ce3c5 --- /dev/null +++ b/boards/nxp/frdm_mcxa577/frdm_mcxa577-pinctrl.dtsi @@ -0,0 +1,28 @@ +/* + * Copyright 2025 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + pinmux_lpuart0: pinmux_lpuart0 { + group0 { + pinmux = , + ; + drive-strength = "low"; + slew-rate = "fast"; + input-enable; + }; + }; + + pinmux_lpuart1: pinmux_lpuart1 { + group0 { + pinmux = , + ; + drive-strength = "low"; + slew-rate = "fast"; + input-enable; + }; + }; +}; diff --git a/boards/nxp/frdm_mcxa577/frdm_mcxa577.dts b/boards/nxp/frdm_mcxa577/frdm_mcxa577.dts new file mode 100644 index 000000000000..52eabb98dfaa --- /dev/null +++ b/boards/nxp/frdm_mcxa577/frdm_mcxa577.dts @@ -0,0 +1,177 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "frdm_mcxa577-pinctrl.dtsi" +#include +#include + +/ { + model = "NXP FRDM_MCXA577 board"; + compatible = "nxp,mcxa577", "nxp,mcx"; + + aliases { + led0 = &red_led; + led1 = &green_led; + led2 = &blue_led; + sw0 = &user_button_2; + sw1 = &user_button_3; + watchdog0 = &wwdt0; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash; + zephyr,flash-controller = &fmu; + zephyr,code-partition = &slot0_partition; + zephyr,console = &lpuart1; + zephyr,shell-uart = &lpuart1; + }; + + leds { + compatible = "gpio-leds"; + + red_led: led_0 { + gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; + label = "Red LED"; + }; + + green_led: led_1 { + gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; + label = "Green LED"; + }; + + blue_led: led_2 { + gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; + label = "Blue LED"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + user_button_2: button_2 { + label = "User SW2"; + gpios = <&gpio3 17 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + + user_button_3: button_3 { + label = "User SW3"; + gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; + + arduino_header: arduino-connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&gpio5 { + status = "okay"; +}; + +&lpuart1 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&pinmux_lpuart1>; + pinctrl-names = "default"; +}; + +&ctimer0 { + status = "okay"; +}; + +&lptmr0 { + status = "okay"; +}; + +&edma0 { + status = "okay"; +}; + +&wwdt0 { + status = "okay"; +}; + +&flash { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(128)>; + read-only; + }; + + slot0_partition: partition@20000 { + label = "image-0"; + reg = <0x00020000 DT_SIZE_K(896)>; + }; + + slot1_partition: partition@100000 { + label = "image-1"; + reg = <0x00100000 DT_SIZE_K(896)>; + }; + + storage_partition: partition@1e0000 { + label = "storage"; + reg = <0x001e0000 DT_SIZE_K(128)>; + }; + }; +}; diff --git a/boards/nxp/frdm_mcxa577/frdm_mcxa577.yaml b/boards/nxp/frdm_mcxa577/frdm_mcxa577.yaml new file mode 100644 index 000000000000..13e8ca0a222a --- /dev/null +++ b/boards/nxp/frdm_mcxa577/frdm_mcxa577.yaml @@ -0,0 +1,22 @@ +# +# Copyright 2025 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: frdm_mcxa577 +name: NXP FRDM-MCXA577 +type: mcu +arch: arm +ram: 640 +flash: 2048 +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio + - uart + - counter + - dma + - watchdog +vendor: nxp diff --git a/boards/nxp/frdm_mcxa577/frdm_mcxa577_defconfig b/boards/nxp/frdm_mcxa577/frdm_mcxa577_defconfig new file mode 100644 index 000000000000..9c025d7429c2 --- /dev/null +++ b/boards/nxp/frdm_mcxa577/frdm_mcxa577_defconfig @@ -0,0 +1,18 @@ +# +# Copyright 2025 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_GPIO=y +CONFIG_LPADC_DO_OFFSET_CALIBRATION=y + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_TRUSTED_EXECUTION_SECURE=y diff --git a/boards/nxp/frdm_mcxaxx6/board.c b/boards/nxp/frdm_mcxaxx6/board.c index 6e36191b1c5f..261aefc4dc83 100644 --- a/boards/nxp/frdm_mcxaxx6/board.c +++ b/boards/nxp/frdm_mcxaxx6/board.c @@ -309,6 +309,17 @@ void board_early_init_hook(void) RESET_ReleasePeripheralReset(kTRNG0_RST_SHIFT_RSTn); #endif +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcan0)) + CLOCK_SetClockDiv(kCLOCK_DivFLEXCAN0, 1U); + CLOCK_SetClockDiv(kCLOCK_DivFRO_HF, 1U); + CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCAN0); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usb)) + RESET_PeripheralReset(kUSB0_RST_SHIFT_RSTn); + CLOCK_EnableUsbfsClock(); +#endif + /* Set SystemCoreClock variable. */ SystemCoreClock = CLOCK_INIT_CORE_CLOCK; } diff --git a/boards/nxp/frdm_mcxaxx6/board_common.dtsi b/boards/nxp/frdm_mcxaxx6/board_common.dtsi index 9f6bbbc20cfb..fb4f61db79fe 100644 --- a/boards/nxp/frdm_mcxaxx6/board_common.dtsi +++ b/boards/nxp/frdm_mcxaxx6/board_common.dtsi @@ -5,6 +5,7 @@ */ #include +#include / { compatible = "nxp,mcx"; @@ -26,6 +27,8 @@ zephyr,code-partition = &slot0_partition; zephyr,console = &lpuart2; zephyr,shell-uart = &lpuart2; + zephyr,cortex-m-idle-timer = &lptmr0; + zephyr,canbus = &flexcan0; }; leds { @@ -62,6 +65,35 @@ zephyr,code = ; }; }; + + arduino_header: arduino-connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = , + , + , + , + , + , + , /* GPIO, Not a RX */ + , /* GPIO, Not a TX */ + , + , + , + , + , + , + , + , + , /* CS */ + , /* MOSI */ + , /* MISO */ + , /* SCK */ + , /* SDA */ + ; /* SCL */ + }; }; /* Port configurations */ @@ -138,12 +170,6 @@ pinctrl-names = "default"; }; -/* Comparator configuration */ -&lpcmp0 { - pinctrl-0 = <&pinmux_lpcmp0>; - pinctrl-names = "default"; -}; - /* I2C configurations */ &lpi2c1 { status = "okay"; @@ -207,3 +233,9 @@ &lptmr0 { status = "okay"; }; + +&flexcan0 { + status = "okay"; + pinctrl-0 = <&pinmux_flexcan0>; + pinctrl-names = "default"; +}; diff --git a/boards/nxp/frdm_mcxaxx6/frdm_mcxa266-pinctrl.dtsi b/boards/nxp/frdm_mcxaxx6/frdm_mcxa266-pinctrl.dtsi index ac4fe928a054..b849c2c2d1a2 100644 --- a/boards/nxp/frdm_mcxaxx6/frdm_mcxa266-pinctrl.dtsi +++ b/boards/nxp/frdm_mcxaxx6/frdm_mcxa266-pinctrl.dtsi @@ -126,4 +126,14 @@ slew-rate = "fast"; }; }; + + pinmux_flexcan0: pinmux_flexcan0 { + group0 { + pinmux = , + ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + }; + }; }; diff --git a/boards/nxp/frdm_mcxaxx6/frdm_mcxa266.dts b/boards/nxp/frdm_mcxaxx6/frdm_mcxa266.dts index d615167a293d..fca1e4f2945a 100644 --- a/boards/nxp/frdm_mcxaxx6/frdm_mcxa266.dts +++ b/boards/nxp/frdm_mcxaxx6/frdm_mcxa266.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "frdm_mcxa266-pinctrl.dtsi" #include "board_common.dtsi" #include @@ -47,3 +47,8 @@ &flexio0 { status = "okay"; }; + +zephyr_udc0: &usb { + status = "okay"; + num-bidir-endpoints = <8>; +}; diff --git a/boards/nxp/frdm_mcxaxx6/frdm_mcxa266.yaml b/boards/nxp/frdm_mcxaxx6/frdm_mcxa266.yaml index 67b32fd9efe0..41babeba153d 100644 --- a/boards/nxp/frdm_mcxaxx6/frdm_mcxa266.yaml +++ b/boards/nxp/frdm_mcxaxx6/frdm_mcxa266.yaml @@ -5,7 +5,7 @@ # identifier: frdm_mcxa266 -name: NXP FRDM MCXA266 +name: NXP FRDM-MCXA266 type: mcu arch: arm ram: 240 @@ -25,4 +25,7 @@ supported: - dma - i3c - entropy + - can + - arduino_gpio + - usbd vendor: nxp diff --git a/boards/nxp/frdm_mcxaxx6/frdm_mcxa346-pinctrl.dtsi b/boards/nxp/frdm_mcxaxx6/frdm_mcxa346-pinctrl.dtsi index cffd3bdf85c8..792d36eda497 100644 --- a/boards/nxp/frdm_mcxaxx6/frdm_mcxa346-pinctrl.dtsi +++ b/boards/nxp/frdm_mcxaxx6/frdm_mcxa346-pinctrl.dtsi @@ -118,4 +118,14 @@ slew-rate = "fast"; }; }; + + pinmux_flexcan0: pinmux_flexcan0 { + group0 { + pinmux = , + ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + }; + }; }; diff --git a/boards/nxp/frdm_mcxaxx6/frdm_mcxa346.dts b/boards/nxp/frdm_mcxaxx6/frdm_mcxa346.dts index 920dc05456da..121fa27532e6 100644 --- a/boards/nxp/frdm_mcxaxx6/frdm_mcxa346.dts +++ b/boards/nxp/frdm_mcxaxx6/frdm_mcxa346.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "frdm_mcxa346-pinctrl.dtsi" #include "board_common.dtsi" diff --git a/boards/nxp/frdm_mcxaxx6/frdm_mcxa346.yaml b/boards/nxp/frdm_mcxaxx6/frdm_mcxa346.yaml index 24c6ef2d11da..039a545847e2 100644 --- a/boards/nxp/frdm_mcxaxx6/frdm_mcxa346.yaml +++ b/boards/nxp/frdm_mcxaxx6/frdm_mcxa346.yaml @@ -5,7 +5,7 @@ # identifier: frdm_mcxa346 -name: NXP FRDM MCXA346 +name: NXP FRDM-MCXA346 type: mcu arch: arm ram: 240 @@ -24,4 +24,6 @@ supported: - counter - dma - opamp + - can + - arduino_gpio vendor: nxp diff --git a/boards/nxp/frdm_mcxaxx6/frdm_mcxa366-pinctrl.dtsi b/boards/nxp/frdm_mcxaxx6/frdm_mcxa366-pinctrl.dtsi index 965b6f3e84c6..3877abf0528e 100644 --- a/boards/nxp/frdm_mcxaxx6/frdm_mcxa366-pinctrl.dtsi +++ b/boards/nxp/frdm_mcxaxx6/frdm_mcxa366-pinctrl.dtsi @@ -136,4 +136,14 @@ slew-rate = "fast"; }; }; + + pinmux_flexcan0: pinmux_flexcan0 { + group0 { + pinmux = , + ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + }; + }; }; diff --git a/boards/nxp/frdm_mcxaxx6/frdm_mcxa366.dts b/boards/nxp/frdm_mcxaxx6/frdm_mcxa366.dts index f3a3c4e8722e..6cf46426c9b6 100644 --- a/boards/nxp/frdm_mcxaxx6/frdm_mcxa366.dts +++ b/boards/nxp/frdm_mcxaxx6/frdm_mcxa366.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "frdm_mcxa366-pinctrl.dtsi" #include "board_common.dtsi" #include @@ -58,3 +58,8 @@ &flexio0 { status = "okay"; }; + +zephyr_udc0: &usb { + status = "okay"; + num-bidir-endpoints = <8>; +}; diff --git a/boards/nxp/frdm_mcxaxx6/frdm_mcxa366.yaml b/boards/nxp/frdm_mcxaxx6/frdm_mcxa366.yaml index a18599ffef3c..0655c805003d 100644 --- a/boards/nxp/frdm_mcxaxx6/frdm_mcxa366.yaml +++ b/boards/nxp/frdm_mcxaxx6/frdm_mcxa366.yaml @@ -5,7 +5,7 @@ # identifier: frdm_mcxa366 -name: NXP FRDM MCXA366 +name: NXP FRDM-MCXA366 type: mcu arch: arm ram: 240 @@ -26,4 +26,7 @@ supported: - i3c - opamp - entropy + - can + - arduino_gpio + - usbd vendor: nxp diff --git a/boards/nxp/frdm_mcxc242/frdm_mcxc242.dts b/boards/nxp/frdm_mcxc242/frdm_mcxc242.dts index a8c5d844efaa..db3053313969 100644 --- a/boards/nxp/frdm_mcxc242/frdm_mcxc242.dts +++ b/boards/nxp/frdm_mcxc242/frdm_mcxc242.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include +#include #include "frdm_mcxc242-pinctrl.dtsi" #include diff --git a/boards/nxp/frdm_mcxc444/frdm_mcxc444.dts b/boards/nxp/frdm_mcxc444/frdm_mcxc444.dts index ef8f66c349d8..72c1c6f2a4bb 100644 --- a/boards/nxp/frdm_mcxc444/frdm_mcxc444.dts +++ b/boards/nxp/frdm_mcxc444/frdm_mcxc444.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "frdm_mcxc444-pinctrl.dtsi" #include @@ -188,10 +188,47 @@ i2c0: &i2c0 { status = "okay"; pinctrl-0 = <&pinmux_tpm0>; pinctrl-names = "default"; - clocks = <&sim KINETIS_SIM_MCGPCLK 0x103C 24>; + clocks = <&sim KINETIS_SIM_MCGPCLK 0x103c 24>; }; zephyr_udc0: &usb { status = "okay"; num-bidir-endpoints = <8>; }; + +&dma { + status = "okay"; +}; + +&dac { + status = "okay"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(64)>; + read-only; + }; + + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 DT_SIZE_K(80)>; + }; + + slot1_partition: partition@24000 { + label = "image-1"; + reg = <0x00024000 DT_SIZE_K(80)>; + }; + + storage_partition: partition@38000 { + label = "storage"; + reg = <0x00038000 DT_SIZE_K(32)>; + }; + }; +}; diff --git a/boards/nxp/frdm_mcxc444/frdm_mcxc444.yaml b/boards/nxp/frdm_mcxc444/frdm_mcxc444.yaml index 26fa057959cf..6ad047ff3715 100644 --- a/boards/nxp/frdm_mcxc444/frdm_mcxc444.yaml +++ b/boards/nxp/frdm_mcxc444/frdm_mcxc444.yaml @@ -24,6 +24,8 @@ supported: - usb_device - usbd - watchdog + - dma + - dac testing: ignore_tags: - net diff --git a/boards/nxp/frdm_mcxe247/board.c b/boards/nxp/frdm_mcxe247/board.c index c2c2ceb3fecf..ec1ac0b00dbb 100644 --- a/boards/nxp/frdm_mcxe247/board.c +++ b/boards/nxp/frdm_mcxe247/board.c @@ -16,7 +16,7 @@ #define ASSERT_ASYNC_CLK_DIV_VALID(val, str) \ BUILD_ASSERT(val == 0 || val == 1 || val == 2 || val == 4 || \ - val == 8 || val == 16 || val == 2 || val == 64, str) + val == 8 || val == 16 || val == 32 || val == 64, str) #define kSCG_AsyncClkDivBy0 kSCG_AsyncClkDisable @@ -181,6 +181,15 @@ __weak void clock_init(void) CLOCK_GetCurSysClkConfig(¤t); } while (current.src != scg_sys_clk_config.src); +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcan0)) + CLOCK_EnableClock(kCLOCK_Can0); +#endif +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcan1)) + CLOCK_EnableClock(kCLOCK_Can1); +#endif +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcan2)) + CLOCK_EnableClock(kCLOCK_Can2); +#endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart0)) CLOCK_SetIpSrc(kCLOCK_Lpuart0, DT_CLOCKS_CELL(DT_NODELABEL(lpuart0), ip_source)); @@ -214,7 +223,7 @@ __weak void clock_init(void) DT_CLOCKS_CELL(DT_NODELABEL(lpspi2), ip_source)); #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(adc0)) - CLOCK_SetIpSrc(kCLOCK_Adc0 + CLOCK_SetIpSrc(kCLOCK_Adc0, DT_CLOCKS_CELL(DT_NODELABEL(adc0), ip_source)); #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(adc1)) @@ -258,8 +267,7 @@ __weak void clock_init(void) DT_CLOCKS_CELL(DT_NODELABEL(ftm7), ip_source)); #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ewm0)) - CLOCK_SetIpSrc(kCLOCK_Ewm0, - DT_CLOCKS_CELL(DT_NODELABEL(ewm0), ip_source)); + CLOCK_EnableClock(kCLOCK_Ewm0); #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexio0)) CLOCK_SetIpSrc(kCLOCK_Flexio0, diff --git a/boards/nxp/frdm_mcxe247/doc/index.rst b/boards/nxp/frdm_mcxe247/doc/index.rst index 11cd6e608c93..ad140b730f6d 100644 --- a/boards/nxp/frdm_mcxe247/doc/index.rst +++ b/boards/nxp/frdm_mcxe247/doc/index.rst @@ -70,6 +70,16 @@ PORTB/GPIOB, PORTC/GPIOC, PORTD/GPIOD, and PORTE/GPIOE). +-------+-------------+---------------------------+ | PTA3 | I2C0_SCL | I2C sensor | +-------+-------------+---------------------------+ +| PTA0 | ADC0 | ADC0 Channel 0 | ++-------+-------------+---------------------------+ +| PTA1 | ADC0 | ADC0 Channel 1 | ++-------+-------------+---------------------------+ +| PTA0 | CMP0 | CMP0 IN 0 | ++-------+-------------+---------------------------+ +| PTE5 | FLEXCAN0 | CAN0 TX | ++-------+-------------+---------------------------+ +| PTE4 | FLEXCAN0 | CAN0 RX | ++-------+-------------+---------------------------+ System Clock ============ diff --git a/boards/nxp/frdm_mcxe247/frdm_mcxe247-pinctrl.dtsi b/boards/nxp/frdm_mcxe247/frdm_mcxe247-pinctrl.dtsi index 2f7ad4be2507..5cd0f8d6e254 100644 --- a/boards/nxp/frdm_mcxe247/frdm_mcxe247-pinctrl.dtsi +++ b/boards/nxp/frdm_mcxe247/frdm_mcxe247-pinctrl.dtsi @@ -25,4 +25,71 @@ slew-rate = "slow"; }; }; + + pinmux_lpi2c0: pinmux_lpi2c0 { + group0 { + pinmux = , + ; + drive-strength = "low"; + slew-rate = "slow"; + input-enable; + }; + }; + + pinmux_lpi2c1: pinmux_lpi2c1 { + group0 { + pinmux = , + ; + drive-strength = "low"; + slew-rate = "slow"; + input-enable; + }; + }; + + pinmux_lpspi1: pinmux_lpspi1 { + group0 { + pinmux = , + , + , + ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + }; + }; + + pinmux_adc0: pinmux_adc0 { + group0 { + pinmux = , + ; + drive-strength = "low"; + slew-rate = "slow"; + }; + }; + + pinmux_cmp0: pinmux_cmp0 { + group0 { + pinmux = ; + drive-strength = "high"; + slew-rate = "fast"; + }; + }; + + pinmux_flexcan0: pinmux_flexcan0 { + group0 { + pinmux = , + ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + }; + }; + + flexio_pwm_default: flexio_pwm_default { + group0 { + pinmux = ; + drive-strength = "low"; + slew-rate = "slow"; + }; + }; }; diff --git a/boards/nxp/frdm_mcxe247/frdm_mcxe247.dts b/boards/nxp/frdm_mcxe247/frdm_mcxe247.dts index 7f508a22b864..8220d3fa4b32 100644 --- a/boards/nxp/frdm_mcxe247/frdm_mcxe247.dts +++ b/boards/nxp/frdm_mcxe247/frdm_mcxe247.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "frdm_mcxe247-pinctrl.dtsi" #include #include @@ -22,6 +22,7 @@ sw0 = &user_button_2; sw1 = &user_button_3; rtc = &counter_rtc; + accel0 = &fxls8974; }; chosen { @@ -31,6 +32,7 @@ zephyr,shell-uart = &lpuart2; zephyr,canbus = &flexcan0; zephyr,edac = &erm0; + zephyr,crc = &crc; }; leds { @@ -98,6 +100,20 @@ }; }; +&adc0 { + status = "okay"; + sample-time = <12>; + vref-mv = <3300>; + pinctrl-0 = <&pinmux_adc0>; + pinctrl-names = "default"; +}; + +&cmp0 { + status = "okay"; + pinctrl-0 = <&pinmux_cmp0>; + pinctrl-names = "default"; +}; + &cpu0 { clock-frequency = <80000000>; }; @@ -136,10 +152,20 @@ clock-div = <4>; }; +&fircdiv1_clk { + clock-div = <8>; +}; + &fircdiv2_clk { clock-div = <1>; }; +&flexcan0 { + pinctrl-0 = <&pinmux_flexcan0>; + pinctrl-names = "default"; + status = "okay"; +}; + &soscdiv2_clk { clock-div = <1>; }; @@ -202,6 +228,30 @@ status = "okay"; }; +&lpi2c0 { + pinctrl-0 = <&pinmux_lpi2c0>; + pinctrl-names = "default"; + status = "okay"; + + fxls8974: fxls8974@18 { + compatible = "nxp,fxls8974"; + reg = <0x18>; + status = "okay"; + }; +}; + +&lpi2c1 { + pinctrl-0 = <&pinmux_lpi2c1>; + pinctrl-names = "default"; + status = "okay"; +}; + +&lpspi1 { + status = "okay"; + pinctrl-0 = <&pinmux_lpspi1>; + pinctrl-names = "default"; +}; + &edma { status = "okay"; }; @@ -213,3 +263,15 @@ &counter_rtc { status = "okay"; }; + +&crc { + status = "okay"; +}; + +&ftm0 { + status = "okay"; +}; + +&wdog { + status = "okay"; +}; diff --git a/boards/nxp/frdm_mcxe247/frdm_mcxe247.yaml b/boards/nxp/frdm_mcxe247/frdm_mcxe247.yaml index 1946cb7b2801..0eb717c5f584 100644 --- a/boards/nxp/frdm_mcxe247/frdm_mcxe247.yaml +++ b/boards/nxp/frdm_mcxe247/frdm_mcxe247.yaml @@ -14,7 +14,17 @@ toolchain: - zephyr - gnuarmemb supported: + - adc + - can - uart + - i2c + - spi - gpio + - adc - arduino_gpio + - comparator + - dma + - counter + - pwm + - watchdog vendor: nxp diff --git a/boards/nxp/frdm_mcxe31b/doc/index.rst b/boards/nxp/frdm_mcxe31b/doc/index.rst index 7e2eb3780def..b714dbf67ef8 100644 --- a/boards/nxp/frdm_mcxe31b/doc/index.rst +++ b/boards/nxp/frdm_mcxe31b/doc/index.rst @@ -58,6 +58,10 @@ controller, refer to the device reference manual. +-------+-------------+---------------------------+ | PTE14 | LPUART5_TX | UART Console | +-------+-------------+---------------------------+ +| PTA7 | FLEXCAN0 | CAN0 TX | ++-------+-------------+---------------------------+ +| PTA6 | FLEXCAN0 | CAN0 RX | ++-------+-------------+---------------------------+ System Clock ============ diff --git a/boards/nxp/frdm_mcxe31b/frdm_mcxe31b-pinctrl.dtsi b/boards/nxp/frdm_mcxe31b/frdm_mcxe31b-pinctrl.dtsi index 8054c30c49f4..454c816d3ced 100644 --- a/boards/nxp/frdm_mcxe31b/frdm_mcxe31b-pinctrl.dtsi +++ b/boards/nxp/frdm_mcxe31b/frdm_mcxe31b-pinctrl.dtsi @@ -13,6 +13,18 @@ }; }; + pinmux_lpuart_2: pinmux_lpuart_2 { + group1 { + pinmux = ; + output-enable; + }; + + group2 { + pinmux = ; + input-enable; + }; + }; + pinmux_lpuart_5: pinmux_lpuart_5 { group1 { pinmux = ; @@ -24,4 +36,16 @@ input-enable; }; }; + + pinmux_flexcan_0: pinmux_flexcan_0 { + group1 { + pinmux = ; + input-enable; + }; + + group2 { + pinmux = ; + output-enable; + }; + }; }; diff --git a/boards/nxp/frdm_mcxe31b/frdm_mcxe31b.dts b/boards/nxp/frdm_mcxe31b/frdm_mcxe31b.dts index ad17f368bb10..7305719c6afd 100644 --- a/boards/nxp/frdm_mcxe31b/frdm_mcxe31b.dts +++ b/boards/nxp/frdm_mcxe31b/frdm_mcxe31b.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "frdm_mcxe31b-pinctrl.dtsi" #include #include @@ -34,6 +34,7 @@ zephyr,console = &lpuart_5; zephyr,edac = &erm0; zephyr,shell-uart = &lpuart_5; + zephyr,canbus = &flexcan_0; }; leds { @@ -99,6 +100,10 @@ clock-frequency = ; }; +&edma { + status = "okay"; +}; + &erm0 { status = "okay"; }; @@ -119,6 +124,13 @@ status = "okay"; }; +&lpuart_2 { + pinctrl-0 = <&pinmux_lpuart_2>; + pinctrl-names = "default"; + dmas = <&edma 16 38>, <&edma 17 39>; + dma-names = "tx", "rx"; +}; + &lpuart_5 { status = "okay"; current-speed = <115200>; @@ -128,6 +140,12 @@ dma-names = "tx", "rx"; }; +&flexcan_0 { + pinctrl-0 = <&pinmux_flexcan_0>; + pinctrl-names = "default"; + status = "okay"; +}; + &gpioc_l { status = "okay"; }; @@ -159,6 +177,10 @@ overdrive = <12>; }; +&pit_0 { + status = "okay"; +}; + &pll { status = "okay"; workmode = "Integer"; @@ -204,3 +226,10 @@ &swt_0 { status = "okay"; }; + +&adc_0 { + status = "okay"; +}; + +/* Add lpuart2 label to lpuart_2. */ +lpuart2: &lpuart_2 {}; diff --git a/boards/nxp/frdm_mcxe31b/frdm_mcxe31b.yaml b/boards/nxp/frdm_mcxe31b/frdm_mcxe31b.yaml index 0186ca24ab4d..adc7728fc3f3 100644 --- a/boards/nxp/frdm_mcxe31b/frdm_mcxe31b.yaml +++ b/boards/nxp/frdm_mcxe31b/frdm_mcxe31b.yaml @@ -2,7 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 identifier: frdm_mcxe31b -name: NXP FRDM MCXE31B +name: NXP FRDM-MCXE31B type: mcu arch: arm ram: 288 @@ -12,7 +12,10 @@ toolchain: - gnuarmemb supported: - arduino_gpio + - can - gpio - rtc + - dma - watchdog + - adc vendor: nxp diff --git a/boards/nxp/frdm_mcxn236/board.c b/boards/nxp/frdm_mcxn236/board.c index 4ffd297e6af4..6ffeead0722d 100644 --- a/boards/nxp/frdm_mcxn236/board.c +++ b/boards/nxp/frdm_mcxn236/board.c @@ -211,8 +211,8 @@ void board_early_init_hook(void) #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcan1)) - CLOCK_SetClkDiv(kCLOCK_DivFlexcan1Clk, 1U); - CLOCK_AttachClk(kFRO_HF_to_FLEXCAN1); + CLOCK_SetClkDiv(kCLOCK_DivFlexcan1Clk, 3U); + CLOCK_AttachClk(kPLL0_to_FLEXCAN1); #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(vref)) diff --git a/boards/nxp/frdm_mcxn236/doc/index.rst b/boards/nxp/frdm_mcxn236/doc/index.rst index a4833766e826..746c1af475be 100644 --- a/boards/nxp/frdm_mcxn236/doc/index.rst +++ b/boards/nxp/frdm_mcxn236/doc/index.rst @@ -37,6 +37,16 @@ Supported Features .. zephyr:board-supported-hw:: +Shields for Supported Features +============================== + +Some features in the table above are tested with Zephyr shields. These shields +are tested on this board: + +- :ref:`lcd_par_s035` - supports the Display interface. This board uses the + MIPI_DBI interface of the shield, connected to the FlexIO on-chip peripheral. +- :ref:`dvp_20pin_ov7670` - supports the SmartDMA video interface. + Connections and IOs =================== diff --git a/boards/nxp/frdm_mcxn236/frdm_mcxn236.dts b/boards/nxp/frdm_mcxn236/frdm_mcxn236.dts index 0c1ea84eeae1..30c691645611 100644 --- a/boards/nxp/frdm_mcxn236/frdm_mcxn236.dts +++ b/boards/nxp/frdm_mcxn236/frdm_mcxn236.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "frdm_mcxn236-pinctrl.dtsi" #include #include @@ -279,10 +279,6 @@ zephyr_udc0: &usb1 { tx-cal-45-dm-ohms = <7>; }; -&lpcmp0 { - status = "okay"; -}; - &i3c1 { status = "okay"; }; @@ -344,13 +340,13 @@ nxp_8080_touch_panel_i2c: &flexcomm2_lpi2c2 { clock-frequency = ; }; -/* - * MCXN236 board uses OS timer as the kernel timer - * In case we need to switch to SYSTICK timer, then - * replace &os_timer with &systick +/* The MCXN236 can use ostimer as the kernel timer. + * We enable it in the dts, and which specific timer + * to use as the system timer can be controlled through + * Kconfig option based on application requirements. */ &os_timer { - status = "disabled"; + status = "okay"; }; &systick { @@ -385,9 +381,9 @@ nxp_8080_touch_panel_i2c: &flexcomm2_lpi2c2 { reg = <0x0084000 DT_SIZE_K(440)>; }; - storage_partition: partition@F0000 { + storage_partition: partition@f0000 { label = "storage"; - reg = <0x000F0000 DT_SIZE_K(64)>; + reg = <0x000f0000 DT_SIZE_K(64)>; }; }; }; @@ -402,11 +398,6 @@ nxp_8080_touch_panel_i2c: &flexcomm2_lpi2c2 { pinctrl-names = "default"; }; -&lpcmp0 { - pinctrl-0 = <&pinmux_lpcmp0>; - pinctrl-names = "default"; -}; - &flexcan1 { pinctrl-0 = <&pinmux_flexcan1>; pinctrl-names = "default"; diff --git a/boards/nxp/frdm_mcxn236/frdm_mcxn236.yaml b/boards/nxp/frdm_mcxn236/frdm_mcxn236.yaml index d366a7c74b53..24c031088172 100644 --- a/boards/nxp/frdm_mcxn236/frdm_mcxn236.yaml +++ b/boards/nxp/frdm_mcxn236/frdm_mcxn236.yaml @@ -5,7 +5,7 @@ # identifier: frdm_mcxn236 -name: NXP FRDM MCXN236 +name: NXP FRDM-MCXN236 type: mcu arch: arm ram: 256 diff --git a/boards/nxp/frdm_mcxn947/CMakeLists.txt b/boards/nxp/frdm_mcxn947/CMakeLists.txt index d12527c90b1e..def454d5950d 100644 --- a/boards/nxp/frdm_mcxn947/CMakeLists.txt +++ b/boards/nxp/frdm_mcxn947/CMakeLists.txt @@ -9,7 +9,6 @@ zephyr_library_sources(board.c) if(CONFIG_FLEXSPI_CONFIG_BLOCK_OFFSET) # Include flash configuration block - zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) zephyr_library_sources(xip/mcxn_flexspi_nor_config.c) zephyr_library_include_directories(xip) endif() diff --git a/boards/nxp/frdm_mcxn947/Kconfig.frdm_mcxn947 b/boards/nxp/frdm_mcxn947/Kconfig.frdm_mcxn947 index fde729ba7363..73af92c4b8a9 100644 --- a/boards/nxp/frdm_mcxn947/Kconfig.frdm_mcxn947 +++ b/boards/nxp/frdm_mcxn947/Kconfig.frdm_mcxn947 @@ -1,7 +1,7 @@ -# Copyright 2024 NXP +# Copyright 2024-2025 NXP # SPDX-License-Identifier: Apache-2.0 config BOARD_FRDM_MCXN947 - select SOC_MCXN947_CPU0 if BOARD_FRDM_MCXN947_MCXN947_CPU0 || BOARD_FRDM_MCXN947_MCXN947_CPU0_QSPI + select SOC_MCXN947_CPU0 if BOARD_FRDM_MCXN947_MCXN947_CPU0 || BOARD_FRDM_MCXN947_MCXN947_CPU0_QSPI || BOARD_FRDM_MCXN947_MCXN947_CPU0_NS select SOC_MCXN947_CPU1 if BOARD_FRDM_MCXN947_MCXN947_CPU1 select SOC_PART_NUMBER_MCXN947VDF diff --git a/boards/nxp/frdm_mcxn947/board.c b/boards/nxp/frdm_mcxn947/board.c index 2ac3f1696774..22f548b21dc1 100644 --- a/boards/nxp/frdm_mcxn947/board.c +++ b/boards/nxp/frdm_mcxn947/board.c @@ -291,8 +291,8 @@ void board_early_init_hook(void) #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcan0)) - CLOCK_SetClkDiv(kCLOCK_DivFlexcan0Clk, 1U); - CLOCK_AttachClk(kFRO_HF_to_FLEXCAN0); + CLOCK_SetClkDiv(kCLOCK_DivFlexcan0Clk, 3U); + CLOCK_AttachClk(kPLL0_to_FLEXCAN0); #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usdhc0)) diff --git a/boards/nxp/frdm_mcxn947/board.cmake b/boards/nxp/frdm_mcxn947/board.cmake index f26f08890bfb..716926504f5c 100644 --- a/boards/nxp/frdm_mcxn947/board.cmake +++ b/boards/nxp/frdm_mcxn947/board.cmake @@ -1,5 +1,5 @@ # -# Copyright 2024 NXP +# Copyright 2024-2025 NXP # # SPDX-License-Identifier: Apache-2.0 # @@ -35,3 +35,8 @@ board_runner_args(pyocd "--target=mcxn947") include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) + +if(CONFIG_BUILD_WITH_TFM) + # Flash merged TF-M + Zephyr binary + set_property(TARGET runners_yaml_props_target PROPERTY hex_file tfm_merged.hex) +endif() diff --git a/boards/nxp/frdm_mcxn947/board.yml b/boards/nxp/frdm_mcxn947/board.yml index dd17fc68dc48..a3f5e3a49052 100644 --- a/boards/nxp/frdm_mcxn947/board.yml +++ b/boards/nxp/frdm_mcxn947/board.yml @@ -7,3 +7,5 @@ board: variants: - name: qspi cpucluster: 'cpu0' + - name: ns + cpucluster: 'cpu0' diff --git a/boards/nxp/frdm_mcxn947/doc/index.rst b/boards/nxp/frdm_mcxn947/doc/index.rst index f98a07965a80..f7d2a9088f14 100644 --- a/boards/nxp/frdm_mcxn947/doc/index.rst +++ b/boards/nxp/frdm_mcxn947/doc/index.rst @@ -39,6 +39,16 @@ Supported Features .. zephyr:board-supported-hw:: +Shields for Supported Features +============================== + +Some features in the table above are tested with Zephyr shields. These shields +are tested on this board: + +- :ref:`lcd_par_s035` - supports the Display interface. This board uses the + MIPI_DBI interface of the shield, connected to the FlexIO on-chip peripheral. +- :ref:`dvp_20pin_ov7670` - supports the SmartDMA video interface. + Dual Core samples ***************** @@ -359,10 +369,10 @@ Troubleshooting https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/mcx-arm-cortex-m/mcx-n-series-microcontrollers/mcx-n94x-54x-highly-integrated-multicore-mcus-with-on-chip-accelerators-intelligent-peripherals-and-advanced-security:MCX-N94X-N54X .. _MCX-N947 Datasheet: - https://www.nxp.com/docs/en/data-sheet/MCXNx4xDS.pdf + https://www.nxp.com/docs/en/data-sheet/MCXNP184M150F70.pdf .. _MCX-N947 Reference Manual: - https://www.nxp.com/webapp/Download?colCode=MCXNX4XRM + https://www.nxp.com/webapp/Download?colCode=MCXNP184M150F70RM .. _FRDM-MCXN947 Website: https://www.nxp.com/design/design-center/development-boards/general-purpose-mcus/frdm-development-board-for-mcx-n94-n54-mcus:FRDM-MCXN947 diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi b/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi index 8cd46a48393c..91b037d0f805 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi @@ -263,6 +263,7 @@ arduino_serial: &flexcomm2_lpuart2 {}; compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + ranges; /* * Partition sizes must be aligned @@ -278,9 +279,9 @@ arduino_serial: &flexcomm2_lpuart2 {}; reg = <0x00014000 DT_SIZE_K(984)>; }; - slot1_partition: partition@10A000 { + slot1_partition: partition@10a000 { label = "image-1"; - reg = <0x0010A000 DT_SIZE_K(984)>; + reg = <0x0010a000 DT_SIZE_K(984)>; }; /* storage_partition is placed in WINBOND flash memory*/ }; @@ -384,11 +385,6 @@ zephyr_mipi_dbi_parallel: &flexio0_lcd { pinctrl-names = "default"; }; -&lpcmp0 { - pinctrl-0 = <&pinmux_lpcmp0>; - pinctrl-names = "default"; -}; - &opamp0 { pinctrl-0 = <&pinmux_opamp0>; pinctrl-names = "default"; diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dtsi b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dtsi index cd40cd6e56e6..ef3881936298 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dtsi +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dtsi @@ -10,7 +10,7 @@ */ /dts-v1/; -#include +#include #include "frdm_mcxn947.dtsi" / { @@ -252,10 +252,6 @@ zephyr_udc0: &usb1 { tx-cal-45-dm-ohms = <7>; }; -&lpcmp0 { - status = "okay"; -}; - &opamp0 { status = "okay"; }; diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml index 0fd1ac9dbb0a..b25b6235a90a 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml @@ -5,7 +5,7 @@ # identifier: frdm_mcxn947/mcxn947/cpu0 -name: NXP FRDM MCXN947 (CPU0) +name: NXP FRDM-MCXN947 (CPU0) type: mcu arch: arm ram: 320 @@ -28,6 +28,7 @@ supported: - i2c - i2s - i3c + - netif:eth - nvs - pwm - regulator @@ -35,6 +36,7 @@ supported: - sdhc - spi - usb_device + - usbd - video - watchdog vendor: nxp diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_ns.dts b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_ns.dts new file mode 100644 index 000000000000..0765362ef507 --- /dev/null +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_ns.dts @@ -0,0 +1,327 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "frdm_mcxn947.dtsi" + +/ { + model = "NXP FRDM_N94 board"; + compatible = "nxp,mcxn947", "nxp,mcx"; + + cpus { + /delete-node/ cpu@1; + }; + + chosen { + zephyr,sram = &non_secure_ram; + zephyr,flash = &flash; + zephyr,code-partition = &slot0_ns_partition; + zephyr,flash-controller = &fmu; + zephyr,uart-mcumgr = &flexcomm4_lpuart4; + zephyr,console = &flexcomm4_lpuart4; + zephyr,shell-uart = &flexcomm4_lpuart4; + zephyr,canbus = &flexcan0; + zephyr,entropy = &trng; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* RAM split used by TFM */ + secure_ram: partition@20000000 { + label = "secure-memory"; + reg = <0x20000000 DT_SIZE_K(196)>; + }; + + non_secure_ram: partition@20030000 { + label = "non-secure-memory"; + reg = <0x20030000 DT_SIZE_K(128)>; + }; + }; +}; + +&flash { + /delete-node/ partitions; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* + * All partition sizes must be aligned to the flash memory sector size (8 KB). + * + * This flash layout must exactly match the upstream TF-M layout defined in + * the platform-specific `flash_layout.h`. Any modification to the layout + * must be applied consistently in both `flash_layout.h` and this file. + * + * BL2 / MCUBoot + */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(64)>; /* 64 KB */ + }; + + /* Secure image - primary */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 DT_SIZE_K(288)>; /* 288 KB */ + }; + + /* Non-secure image - primary */ + slot0_ns_partition: partition@58000 { + label = "image-0-nonsecure"; + reg = <0x00058000 DT_SIZE_K(256)>; /* 256 KB */ + }; + + /* Secure image - secondary */ + slot1_partition: partition@98000 { + label = "image-1-secondary"; + reg = <0x00098000 DT_SIZE_K(288)>; /* 288 KB */ + }; + + /* Non-secure image - secondary */ + slot1_ns_partition: partition@e0000 { + label = "image-1-non-secure"; + reg = <0x000e0000 DT_SIZE_K(256)>; /* 256 KB */ + }; + + /* Protected Storage (PS) */ + tfm_ps_partition: partition@120000 { + label = "tfm-ps"; + reg = <0x00120000 DT_SIZE_K(16)>; /* 16 KB */ + }; + + /* Internal Trusted Storage (ITS) */ + tfm_its_partition: partition@124000 { + label = "tfm-its"; + reg = <0x00124000 DT_SIZE_K(16)>; /* 16 KB */ + }; + + /* OTP / NV counters */ + tfm_otp_partition: partition@128000 { + label = "tfm-otp"; + reg = <0x00128000 DT_SIZE_K(8)>; /* 8 KB */ + }; + }; +}; + +/* + * Default for this board is to allocate SRAM0-5 to cpu0 but the + * application can have an application specific device tree to + * allocate the SRAM0-7 differently. + * + * For example, SRAM0-6 could be allocated to cpu0 with only SRAM7 + * for cpu1. This would require the value of sram0 to have a DT_SIZE_K + * of 384. You would have to make updates to cpu1 sram settings as well. + */ + +&mbox { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&green_led { + status = "okay"; +}; + +&red_led { + status = "okay"; +}; + +&user_button_2 { + status = "okay"; +}; + +&edma0 { + status = "okay"; +}; + +&flexcomm1 { + status = "okay"; +}; + +&flexcomm1_lpspi1 { + status = "okay"; +}; + +&flexcomm2 { + status = "okay"; +}; + +&flexcomm2_lpi2c2 { + status = "okay"; +}; + +/* + *LPFLEXCOMM supports UART and I2C on the same instance, enable this for + * LFLEXCOMM2 + */ +&flexcomm2_lpuart2 { + status = "okay"; +}; + +&flexcomm4 { + status = "okay"; +}; + +&flexcomm4_lpuart4 { + status = "okay"; +}; + +&flexcomm7 { + status = "okay"; +}; + +&flexcomm7_lpi2c7 { + status = "okay"; +}; + +&flexspi { + status = "okay"; +}; + +&w25q64jvssiq { + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + storage_partition: partition@0 { + label = "storage"; + reg = <0x0 DT_SIZE_M(8)>; + }; + }; +}; + +&dac0 { + status = "okay"; +}; + +&enet { + status = "okay"; +}; + +&enet_mac { + status = "okay"; +}; + +&enet_mdio { + status = "okay"; +}; + +&phy { + status = "okay"; +}; + +&wwdt0 { + status = "okay"; +}; + +&flexpwm1_pwm0 { + status = "okay"; +}; + +&flexcan0 { + status = "okay"; +}; + +&ctimer0 { + status = "okay"; +}; + +&usdhc0 { + status = "okay"; + + sdmmc { + compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; + status = "okay"; + }; +}; + +&vref { + status = "okay"; +}; + +&lpadc0 { + status = "okay"; +}; + +zephyr_udc0: &usb1 { + status = "okay"; + phy-handle = <&usbphy1>; +}; + +&usbphy1 { + status = "okay"; + tx-d-cal = <4>; + tx-cal-45-dp-ohms = <7>; + tx-cal-45-dm-ohms = <7>; +}; + +&lptmr0 { + status = "okay"; +}; + +&i3c1 { + status = "okay"; +}; + +&flexio0 { + status = "okay"; +}; + +&mrt0_channel0 { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&sc_timer { + status = "okay"; +}; + +&sai1 { + status = "okay"; +}; + +&sai0 { + status = "okay"; +}; + +&fmu { + status = "okay"; +}; + +&trng { + /* Disable TRNG in NS to avoid auto-enabling csprng_available option */ + status = "disabled"; +}; diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_ns.yaml b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_ns.yaml new file mode 100644 index 000000000000..cf4043936abe --- /dev/null +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_ns.yaml @@ -0,0 +1,17 @@ +# +# Copyright 2025 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: frdm_mcxn947/mcxn947/cpu0/ns +name: NXP FRDM-MCXN947 (CPU0) (Non-Secure) +type: mcu +arch: arm +ram: 128 +flash: 512 +toolchain: + - zephyr + - gnuarmemb +supported: [] +vendor: nxp diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_ns_defconfig b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_ns_defconfig new file mode 100644 index 000000000000..66adee8f206b --- /dev/null +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_ns_defconfig @@ -0,0 +1,19 @@ +# +# Copyright 2025-2026 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_GPIO=y + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +CONFIG_TFM_BL2=y +CONFIG_BUILD_WITH_TFM=y +CONFIG_FLASH_BASE_ADDRESS=0x58000 diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_qspi.dts b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_qspi.dts index 16652d83fff3..d6b7a7059009 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_qspi.dts +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_qspi.dts @@ -28,6 +28,7 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + ranges; boot_partition: partition@0 { label = "mcuboot"; diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_qspi.yaml b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_qspi.yaml index ca5461e8df4c..8a1f10e06caf 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_qspi.yaml +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_qspi.yaml @@ -5,7 +5,7 @@ # identifier: frdm_mcxn947/mcxn947/cpu0/qspi -name: NXP FRDM MCXN947 QSPI (CPU0) +name: NXP FRDM-MCXN947 (CPU0) (QSPI) type: mcu arch: arm ram: 320 @@ -33,5 +33,6 @@ supported: - sdhc - spi - usb_device + - usbd - watchdog vendor: nxp diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu1.dts b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu1.dts index 78fc22c12a71..70cd4a21285a 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu1.dts +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu1.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "frdm_mcxn947.dtsi" / { diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu1.yaml b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu1.yaml index 62335a40f84a..92264551d8c2 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu1.yaml +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu1.yaml @@ -5,7 +5,7 @@ # identifier: frdm_mcxn947/mcxn947/cpu1 -name: NXP FRDM MCXN947 (CPU1) +name: NXP FRDM-MCXN947 (CPU1) type: mcu arch: arm ram: 64 diff --git a/boards/nxp/frdm_mcxn947/xip/mcxn_flexspi_nor_config.h b/boards/nxp/frdm_mcxn947/xip/mcxn_flexspi_nor_config.h index 49ed7a5699f6..800a92345c52 100644 --- a/boards/nxp/frdm_mcxn947/xip/mcxn_flexspi_nor_config.h +++ b/boards/nxp/frdm_mcxn947/xip/mcxn_flexspi_nor_config.h @@ -109,7 +109,7 @@ enum { FLEXSPI_MISC_OFFSET_SAFE_CONFIG_FREQ_ENABLE = 4, /* Bit for Pad setting override enable */ FLEXSPI_MISC_OFFSET_PAD_SETTING_OVERRIDE_ENABLE = 5, - /* Bit for DDR clock confiuration indication. */ + /* Bit for DDR clock configuration indication. */ FLEXSPI_MISC_OFFSET_DDR_MODE_ENABLE = 6, }; @@ -239,7 +239,7 @@ typedef struct flexspi_config { * 8 - Octal */ uint8_t sflash_pad_type; - /* [0x046-0x046] Serial Flash Frequencey, device specific + /* [0x046-0x046] Serial Flash Frequency, device specific * definitions, See System Boot Chapter for more details */ uint8_t serial_clk_freq; @@ -355,7 +355,7 @@ typedef struct _flexspi_nor_config { uint8_t need_exit_nocmd_mode; /* Half the Serial Clock for non-read command: true/false */ uint8_t half_clk_for_non_read_cmd; - /* Need to Restore NoCmd mode after IP commmand execution */ + /* Need to Restore NoCmd mode after IP command execution */ uint8_t need_restore_nocmd_mode; /* Block size */ uint32_t block_size; diff --git a/boards/nxp/frdm_mcxw23/doc/index.rst b/boards/nxp/frdm_mcxw23/doc/index.rst index eaf5ed522c2d..dfb4e6fa5655 100644 --- a/boards/nxp/frdm_mcxw23/doc/index.rst +++ b/boards/nxp/frdm_mcxw23/doc/index.rst @@ -198,6 +198,14 @@ should see the following message in the terminal: *** Booting Zephyr OS build v4.2.0-2105-g48f2ffda26de *** Hello World! frdm_mcxw23/mcxw236 +Power Management +================ + +When Power Management is enabled :kconfig:option:`CONFIG_PM`, OSTIMER is used as +OS tick timer. + +Limitation: Wakeup pin can't be used as wakeup source in Standby mode. + .. include:: ../../common/board-footer.rst.inc .. _MCXW23 SoC Website: diff --git a/boards/nxp/frdm_mcxw23/dts/bypass_first_32k.overlay b/boards/nxp/frdm_mcxw23/dts/bypass_first_32k.overlay index 7b61d0957bab..51d95fefdacd 100644 --- a/boards/nxp/frdm_mcxw23/dts/bypass_first_32k.overlay +++ b/boards/nxp/frdm_mcxw23/dts/bypass_first_32k.overlay @@ -5,5 +5,5 @@ */ &sram0 { - reg = <0x2000C000 DT_SIZE_K(80)>; + reg = <0x2000c000 DT_SIZE_K(80)>; }; diff --git a/boards/nxp/frdm_mcxw23/frdm_mcxw23.dts b/boards/nxp/frdm_mcxw23/frdm_mcxw23.dts index 2bbd3cb17e36..99984503fb70 100644 --- a/boards/nxp/frdm_mcxw23/frdm_mcxw23.dts +++ b/boards/nxp/frdm_mcxw23/frdm_mcxw23.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "frdm_mcxw23_common.dtsi" / { diff --git a/boards/nxp/frdm_mcxw23/frdm_mcxw23_common.dtsi b/boards/nxp/frdm_mcxw23/frdm_mcxw23_common.dtsi index 205594e59d76..c40b2b4795dc 100644 --- a/boards/nxp/frdm_mcxw23/frdm_mcxw23_common.dtsi +++ b/boards/nxp/frdm_mcxw23/frdm_mcxw23_common.dtsi @@ -176,15 +176,14 @@ pinctrl-names = "default"; }; -/* - * MCXW23 FRDM board uses SYSTICK timer as the kernel timer. - * In case we need to switch to OS timer, then - * replace &systick with &os_timer - */ &systick { status = "okay"; }; +&os_timer { + status = "okay"; +}; + &wwdt0 { status = "okay"; }; diff --git a/boards/nxp/frdm_mcxw71/frdm_mcxw71.dts b/boards/nxp/frdm_mcxw71/frdm_mcxw71.dts index ded93d3e91d5..0a246ce17145 100644 --- a/boards/nxp/frdm_mcxw71/frdm_mcxw71.dts +++ b/boards/nxp/frdm_mcxw71/frdm_mcxw71.dts @@ -5,7 +5,7 @@ /dts-v1/; -#include +#include #include "frdm_mcxw71-pinctrl.dtsi" #include #include @@ -138,6 +138,8 @@ }; }; +arduino_i2c: &lpi2c1 {}; + &lpspi1 { status = "okay"; pinctrl-0 = <&pinmux_lpspi1>; @@ -184,17 +186,17 @@ reg = <0x10000 DT_SIZE_K(424)>; }; - slot1_partition: partition@7A000 { - reg = <0x7A000 DT_SIZE_K(424)>; + slot1_partition: partition@7a000 { + reg = <0x7a000 DT_SIZE_K(424)>; }; - storage_partition: partition@E4000 { - reg = <0xE4000 DT_SIZE_K(104)>; + storage_partition: partition@e4000 { + reg = <0xe4000 DT_SIZE_K(104)>; }; - hw_params_partition: partition@FE000 { + hw_params_partition: partition@fe000 { label = "hw-parameters"; - reg = <0xFE000 DT_SIZE_K(8)>; + reg = <0xfe000 DT_SIZE_K(8)>; }; }; }; diff --git a/boards/nxp/frdm_mcxw71/frdm_mcxw71.yaml b/boards/nxp/frdm_mcxw71/frdm_mcxw71.yaml index 08f7b29929a4..fc6992b00e46 100644 --- a/boards/nxp/frdm_mcxw71/frdm_mcxw71.yaml +++ b/boards/nxp/frdm_mcxw71/frdm_mcxw71.yaml @@ -5,7 +5,7 @@ # identifier: frdm_mcxw71 -name: NXP FRDM_MCXW71 +name: NXP FRDM-MCXW71 type: mcu arch: arm ram: 64 @@ -15,6 +15,7 @@ toolchain: - gnuarmemb supported: - adc + - arduino_i2c - can - counter - dma diff --git a/boards/nxp/frdm_mcxw72/frdm_mcxw72_mcxw727c_cpu0.dts b/boards/nxp/frdm_mcxw72/frdm_mcxw72_mcxw727c_cpu0.dts index cf753867af50..8a8d0bfbbd1a 100644 --- a/boards/nxp/frdm_mcxw72/frdm_mcxw72_mcxw727c_cpu0.dts +++ b/boards/nxp/frdm_mcxw72/frdm_mcxw72_mcxw727c_cpu0.dts @@ -5,7 +5,7 @@ /dts-v1/; -#include +#include #include "frdm_mcxw72-pinctrl.dtsi" #include #include @@ -134,13 +134,13 @@ reg = <0x0 DT_SIZE_K(2024)>; }; - storage_partition: partition@1FA000 { - reg = <0x1FA000 DT_SIZE_K(16)>; + storage_partition: partition@1fa000 { + reg = <0x1fa000 DT_SIZE_K(16)>; }; - hw_params_partition: partition@1FE000 { + hw_params_partition: partition@1fe000 { label = "hw-parameters"; - reg = <0x1FE000 DT_SIZE_K(8)>; + reg = <0x1fe000 DT_SIZE_K(8)>; }; }; }; diff --git a/boards/nxp/frdm_mcxw72/frdm_mcxw72_mcxw727c_cpu0.yaml b/boards/nxp/frdm_mcxw72/frdm_mcxw72_mcxw727c_cpu0.yaml index 010a6973f410..27fdbc9c0976 100644 --- a/boards/nxp/frdm_mcxw72/frdm_mcxw72_mcxw727c_cpu0.yaml +++ b/boards/nxp/frdm_mcxw72/frdm_mcxw72_mcxw727c_cpu0.yaml @@ -1,5 +1,5 @@ identifier: frdm_mcxw72/mcxw727c/cpu0 -name: NXP FRDM_MCXW72 +name: NXP FRDM-MCXW72 type: mcu arch: arm ram: 264 diff --git a/boards/nxp/frdm_rw612/CMakeLists.txt b/boards/nxp/frdm_rw612/CMakeLists.txt index 441e31cdcdd1..cd5c71177429 100644 --- a/boards/nxp/frdm_rw612/CMakeLists.txt +++ b/boards/nxp/frdm_rw612/CMakeLists.txt @@ -10,7 +10,6 @@ dt_nodelabel(xtal32 NODELABEL "xtal32") dt_node_has_status(xtal32_status PATH ${xtal32} STATUS okay) if(CONFIG_NXP_RW6XX_BOOT_HEADER) - zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) # This FCB is specific to the flash on this board, it won't work # for boards with different flash chips. If you flash this FCB # onto a board with a different flash chip you may break it. diff --git a/boards/nxp/frdm_rw612/board.yml b/boards/nxp/frdm_rw612/board.yml index 17ec6bda8298..2415eb687dc2 100644 --- a/boards/nxp/frdm_rw612/board.yml +++ b/boards/nxp/frdm_rw612/board.yml @@ -1,6 +1,6 @@ board: name: frdm_rw612 - full_name: FRDM_RW612 + full_name: FRDM-RW612 vendor: nxp socs: - name: rw612 diff --git a/boards/nxp/frdm_rw612/doc/index.rst b/boards/nxp/frdm_rw612/doc/index.rst index e058d1d618c5..53dfff11d5f3 100644 --- a/boards/nxp/frdm_rw612/doc/index.rst +++ b/boards/nxp/frdm_rw612/doc/index.rst @@ -29,6 +29,15 @@ Supported Features Power modes 1, 2 and 3 are supported when using System Power Management. +Shields for Supported Features +============================== + +Some features in the table above are tested with Zephyr shields. These shields +are tested on this board: + +- :ref:`lcd_par_s035` - supports the Display interface. This board uses the + SPI interface of the shield, connected to the LCDIC on-chip peripheral. + Programming and Debugging ************************* diff --git a/boards/nxp/frdm_rw612/frdm_rw612.dts b/boards/nxp/frdm_rw612/frdm_rw612.dts index 39a58571779b..043cd083c9d7 100644 --- a/boards/nxp/frdm_rw612/frdm_rw612.dts +++ b/boards/nxp/frdm_rw612/frdm_rw612.dts @@ -6,5 +6,5 @@ /dts-v1/; -#include +#include #include "frdm_rw612_common.dtsi" diff --git a/boards/nxp/frdm_rw612/frdm_rw612.yaml b/boards/nxp/frdm_rw612/frdm_rw612.yaml index 7efe02807c44..c12572f90136 100644 --- a/boards/nxp/frdm_rw612/frdm_rw612.yaml +++ b/boards/nxp/frdm_rw612/frdm_rw612.yaml @@ -5,7 +5,7 @@ # identifier: frdm_rw612 -name: NXP FRDM_RW612 +name: NXP FRDM-RW612 type: mcu arch: arm toolchain: @@ -33,4 +33,5 @@ supported: - dac - netif:eth - netif:openthread + - comparator vendor: nxp diff --git a/boards/nxp/frdm_rw612/frdm_rw612_common.dtsi b/boards/nxp/frdm_rw612/frdm_rw612_common.dtsi index 1d4e20a9ff70..c346301132b4 100644 --- a/boards/nxp/frdm_rw612/frdm_rw612_common.dtsi +++ b/boards/nxp/frdm_rw612/frdm_rw612_common.dtsi @@ -232,7 +232,7 @@ mikrobus_serial: &flexcomm0 {}; compatible = "microchip,ksz8081"; reg = <2>; status = "okay"; - reset-gpios = <&hsgpio1 23 GPIO_ACTIVE_HIGH>; + reset-gpios = <&hsgpio1 23 GPIO_ACTIVE_LOW>; int-gpios = <&hsgpio0 21 GPIO_ACTIVE_HIGH>; microchip,interface-type = "rmii"; }; diff --git a/boards/nxp/hexiwear/board.yml b/boards/nxp/hexiwear/board.yml deleted file mode 100644 index 63a0e80de9ad..000000000000 --- a/boards/nxp/hexiwear/board.yml +++ /dev/null @@ -1,7 +0,0 @@ -board: - name: hexiwear - full_name: Hexiwear - vendor: nxp - socs: - - name: mk64f12 - - name: mkw40z4 diff --git a/boards/nxp/hexiwear/doc/index.rst b/boards/nxp/hexiwear/doc/index.rst deleted file mode 100644 index bb77f1ce0fa2..000000000000 --- a/boards/nxp/hexiwear/doc/index.rst +++ /dev/null @@ -1,519 +0,0 @@ -.. _hexiwear: - -Hexiwear -######## - -Overview -******** - -Hexiwear is powered by a Kinetis K64 microcontroller based on the ARM Cortex-M4 -core. Another Kinetis wireless MCU, the KW40Z, provides Bluetooth Low Energy -connectivity. Hexiwear also integrates a wide variety of sensors, as well as a -user interface consisting of a 1.1" 96px x 96px full color OLED display and six -capacitive buttons with haptic feedback. - -- Eye-catching Smart Watch form factor with powerful, low power Kinetis K6x MCU - and 6 on-board sensors. -- Designed for wearable applications with the onboard rechargeable battery, - OLED screen and onboard sensors such as optical heart rate, accelerometer, - magnetometer and gyroscope. -- Designed for IoT end node applications with the onboard sensor's such as - temperature, pressure, humidity and ambient light. -- Flexibility to let you add the sensors of your choice nearly 200 additional - sensors through click boards. - -.. image:: hexiwear_k64.jpg - :align: center - :alt: Hexiwear - -Hardware -******** - -- Main MCU: NXP Kinetis K64x (ARM Cortex-M4, 120 MHz, 1M Flash, 256K SRAM) -- Wireless MCU: NXP Kinetis KW4x (ARM Cortex-M0+, Bluetooth Low Energy & - 802.15.4 radio) -- 6-axis combo Accelerometer and Magnetometer NXP FXOS8700 -- 3-Axis Gyroscope: NXP FXAS21002 -- Absolute Pressure sensor NXP MPL3115 -- Li-Ion/Li-Po Battery Charger NXP MC34671 -- Optical heart rate sensor Maxim MAX30101 -- Ambient Light sensor, Humidity and Temperature sensor -- 1.1" full color OLED display -- Haptic feedback engine -- 190 mAh 2C Li-Po battery -- Capacitive touch interface -- RGB LED - -For more information about the K64F SoC and Hexiwear board: - -- `K64F Website`_ -- `K64F Datasheet`_ -- `K64F Reference Manual`_ -- `Hexiwear Website`_ -- `Hexiwear Fact Sheet`_ -- `Hexiwear Schematics`_ - -Supported Features -================== - -The hexiwear/mk64f12 board variant supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | soc flash | -+-----------+------------+-------------------------------------+ -| SENSOR | off-chip | fxos8700 polling; | -| | | fxos8700 trigger; | -| | | fxas21002 polling; | -| | | fxas21002 trigger; | -| | | max30101 polling | -+-----------+------------+-------------------------------------+ -| RNGA | on-chip | entropy; | -| | | random | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - :zephyr_file:`boards/nxp/hexiwear/hexiwear_mk64f12_defconfig` - -Other hardware features are not currently supported by the port. - -Connections and IOs -=================== - -The K64F SoC has five pairs of pinmux/gpio controllers. - -+-------+-----------------+---------------------------+ -| Name | Function | Usage | -+=======+=================+===========================+ -| PTA29 | GPIO | LDO_EN | -+-------+-----------------+---------------------------+ -| PTB0 | I2C0_SCL | I2C / MAX30101 | -+-------+-----------------+---------------------------+ -| PTB1 | I2C0_SDA | I2C / MAX30101 | -+-------+-----------------+---------------------------+ -| PTB12 | GPIO | 3V3B EN | -+-------+-----------------+---------------------------+ -| PTB16 | UART0_RX | UART Console | -+-------+-----------------+---------------------------+ -| PTB17 | UART0_TX | UART Console | -+-------+-----------------+---------------------------+ -| PTC8 | GPIO / PWM | Red LED | -+-------+-----------------+---------------------------+ -| PTC9 | GPIO / PWM | Green LED | -+-------+-----------------+---------------------------+ -| PTC10 | I2C1_SCL | I2C / FXOS8700 / FXAS21002| -+-------+-----------------+---------------------------+ -| PTC11 | I2C1_SDA | I2C / FXOS8700 / FXAS21002| -+-------+-----------------+---------------------------+ -| PTC14 | GPIO | Battery sense enable | -+-------+-----------------+---------------------------+ -| PTC18 | GPIO | FXAS21002 INT2 | -+-------+-----------------+---------------------------+ -| PTD0 | GPIO / PWM | Blue LED | -+-------+-----------------+---------------------------+ -| PTD13 | GPIO | FXOS8700 INT2 | -+-------+-----------------+---------------------------+ -| PTE24 | UART4_RX | UART BT HCI | -+-------+-----------------+---------------------------+ -| PTE25 | UART4_TX | UART BT HCI | -+-------+-----------------+---------------------------+ - -.. note:: - - To enable battery sensing, you will need to enable the ``en_bat_sens`` - regulator in Devicetree. Similarly, to enable devices connected to the 1V8 - or 3V3 power rails (sensors), you will need to enable the ``en_ldo`` - and ``en_3v3b`` regulators in Devicetree. - -System Clock -============ - -The K64F SoC is configured to use the 12 MHz external oscillator on the board -with the on-chip PLL to generate a 120 MHz system clock. - -Serial Port -=========== - -The K64F SoC has six UARTs. One is configured for the console, another for BT -HCI, and the remaining are not used. - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Configuring a Debug Probe -========================= - -A debug probe is used for both flashing and debugging the board. This board is -configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`, -but because Segger RTT is required for a console on KW40Z, we recommend that -you reconfigure the board for the :ref:`opensda-jlink-onboard-debug-probe`. - -.. note:: - OpenSDA is shared between the K64 and the KW40Z via switches, therefore only - one SoC can be flashed, debugged, or have an open console at a time. - -Option 1: :ref:`opensda-jlink-onboard-debug-probe` (Recommended) ----------------------------------------------------------------- - -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. - -Follow the instructions in :ref:`opensda-jlink-onboard-debug-probe` to program -the `OpenSDA J-Link Generic Firmware for V2.1 Bootloader`_. Check that switches -SW1 and SW2 are **on**, and SW3 and SW4 are **off** to ensure K64F SWD signals -are connected to the OpenSDA microcontroller. - -Option 2: :ref:`opensda-daplink-onboard-debug-probe` ----------------------------------------------------- - -Install the :ref:`pyocd-debug-host-tools` and make sure they are in your search -path. - -Follow the instructions in :ref:`opensda-daplink-onboard-debug-probe` to -program the `OpenSDA DAPLink Hexiwear Firmware`_. Check that switches SW1 and -SW2 are **on**, and SW3 and SW4 are **off** to ensure K64F SWD signals are -connected to the OpenSDA microcontroller. - -Add the arguments ``-DBOARD_FLASH_RUNNER=pyocd`` and -``-DBOARD_DEBUG_RUNNER=pyocd`` when you invoke ``west build`` to override the -default runner from J-Link to pyOCD: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: hexiwear/mk64f12 - :gen-args: -DBOARD_FLASH_RUNNER=pyocd -DBOARD_DEBUG_RUNNER=pyocd - :goals: build - -Configuring a Console -===================== - -Regardless of your choice in debug probe, we will use the OpenSDA -microcontroller as a usb-to-serial adapter for the serial console. - -Connect a USB cable from your PC to CN1. - -Use the following settings with your serial terminal of choice (minicom, putty, -etc.): - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Flashing -======== - -Here is an example for the :zephyr:code-sample:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: hexiwear/mk64f12 - :goals: flash - -Open a serial terminal, reset the board (press the T4 button), and you should -see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-rc1 ***** - Hello World! hexiwear - -Debugging -========= - -Here is an example for the :zephyr:code-sample:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: hexiwear/mk64f12 - :goals: debug - -Open a serial terminal, step through the application in your debugger, and you -should see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-rc1 ***** - Hello World! hexiwear - -Using Bluetooth -*************** - -Configure the KW40Z as a Bluetooth controller -============================================= - -The K64 can support Zephyr Bluetooth host applications when you configure the -KW40Z as a Bluetooth controller. - -#. Download and install the `KW40Z Connectivity Software`_. This package - contains Bluetooth controller application for the KW40Z. -#. Flash the file ``tools/binaries/BLE_HCI_Modem.bin`` to the KW40Z. - -Now you can build and run the sample Zephyr Bluetooth host applications on the -K64. You do not need to repeat this step each time you flash a new Bluetooth -host application to the K64. - -Peripheral Heart Rate Sensor -============================ - -Navigate to the Zephyr ``samples/bluetooth/peripheral_hr`` sample -application, then build and flash it to the Hexiwear K64. Make sure -the OpenSDA switches on the docking station are configured for the -K64. - -.. zephyr-app-commands:: - :zephyr-app: samples/bluetooth/peripheral_hr - :board: hexiwear/mk64f12 - :goals: build flash - -Reset the KW40Z and the K64 using the push buttons on the docking station. - -Install the Kinetis BLE Toolbox on your smartphone: - -- `Kinetis BLE Toolbox for iOS`_ -- `Kinetis BLE Toolbox for Android`_ - -Open the app, tap the **Heart Rate** feature, and you should see a **Zephyr -Heartrate Sensor** device. Tap the **Zephyr Heartrate Sensor** device and you -will then see a plot of the heart rate data that updates once per second. - - -.. _Hexiwear Website: - https://www.mikroe.com/hexiwear - -.. _Hexiwear Fact Sheet: - https://www.nxp.com/docs/en/fact-sheet/HEXIWEAR-FS.pdf - -.. _Hexiwear Schematics: - http://cdn-docs.mikroe.com/images/c/c0/Sch_Hexiwear_MainBoard_v106c.pdf - -.. _K64F Website: - https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/kinetis-cortex-m-mcus/k-seriesperformancem4/k6x-ethernet/kinetis-k64-120-mhz-256kb-sram-microcontrollers-mcus-based-on-arm-cortex-m4-core:K64_120 - -.. _K64F Datasheet: - https://www.nxp.com/docs/en/data-sheet/K64P144M120SF5.pdf - -.. _K64F Reference Manual: - https://www.nxp.com/docs/en/reference-manual/K64P144M120SF5RM.pdf - -.. _OpenSDA J-Link Generic Firmware for V2.1 Bootloader: - https://www.segger.com/downloads/jlink/OpenSDA_V2_1 - -.. _OpenSDA DAPLink Hexiwear Firmware: - https://github.com/MikroElektronika/HEXIWEAR/blob/master/HW/HEXIWEAR_DockingStation/HEXIWEAR_DockingStation_DAPLINK_FW.bin - -.. _KW40Z Connectivity Software: - https://www.nxp.com/webapp/Download?colCode=KW40Z-CONNECTIVITY-SOFTWARE&appType=license&location=null&fpsp=1&WT_TYPE=Protocol%20Stacks&WT_VENDOR=FREESCALE&WT_FILE_FORMAT=exe&WT_ASSET=Downloads&fileExt=.exe&Parent_nodeId=1432854896956716810497&Parent_pageType=product - -.. _Kinetis BLE Toolbox for iOS: - https://itunes.apple.com/us/app/kinetis-ble-toolbox/id1049036961?mt=8 - -.. _Kinetis BLE Toolbox for Android: - https://play.google.com/store/apps/details?id=com.freescale.kinetisbletoolbox - - -Hexiwear KW40Z -############## - -Overview -******** - -The KW40Z is a secondary SoC on the board that provides wireless connectivity -with a multimode BLE and 802.15.4 radio. - -For more information about the KW40Z SoC: - -- `KW40Z Website`_ -- `KW40Z Datasheet`_ -- `KW40Z Reference Manual`_ - -Supported Features -================== - -The hexiwear/mkw40z4 board variant supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| RTT | on-chip | console | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | soc flash | -+-----------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - :zephyr_file:`boards/nxp/hexiwear/hexiwear_mkw40z4_defconfig` - -Other hardware features are not currently supported by the port. - -Connections and IOs -=================== - -The KW40Z SoC has three pairs of pinmux/gpio controllers, but only one is -currently enabled (PORTC/GPIOC) for the hexiwear/mkw40z4 board. - -+-------+-----------------+---------------------------+ -| Name | Function | Usage | -+=======+=================+===========================+ -| PTB1 | ADC | ADC0 channel 1 | -+-------+-----------------+---------------------------+ -| PTC6 | UART0_RX | UART BT HCI | -+-------+-----------------+---------------------------+ -| PTC7 | UART0_TX | UART BT HCI | -+-------+-----------------+---------------------------+ - -System Clock -============ - -The KW40Z SoC is configured to use the 32 MHz external oscillator on the board -with the on-chip FLL to generate a 40 MHz system clock. - -Serial Port -=========== - -The KW40Z SoC has one UART, which is used for BT HCI. There is no UART -available for a console. - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Configuring a Debug Probe -========================= - -A debug probe is used for both flashing and debugging the board. This board is -configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`, -but because Segger RTT is required for a console, you must reconfigure the -board for one of the following debug probes instead. - -:ref:`opensda-jlink-onboard-debug-probe` ----------------------------------------- - -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. - -Follow the instructions in :ref:`opensda-jlink-onboard-debug-probe` to program -the `OpenSDA J-Link Generic Firmware for V2.1 Bootloader`_. Check that switches -SW1 and SW2 are **off**, and SW3 and SW4 are **on** to ensure KW40Z SWD signals -are connected to the OpenSDA microcontroller. - -Configuring a Console -===================== - -The console is available using `Segger RTT`_. - -Connect a USB cable from your PC to CN1. - -Once you have started a debug session, run telnet: - -.. code-block:: console - - $ telnet localhost 19021 - Trying 127.0.0.1... - Connected to localhost. - Escape character is '^]'. - SEGGER J-Link V6.44 - Real time terminal output - J-Link OpenSDA 2 compiled Feb 28 2017 19:27:57 V1.0, SN=621000000 - Process: JLinkGDBServerCLExe - -Flashing -======== - -Here is an example for the :zephyr:code-sample:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: hexiwear/mkw40z4 - :goals: flash - -The Segger RTT console is only available during a debug session. Use ``attach`` -to start one: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: hexiwear/mkw40z4 - :goals: attach - -Run telnet as shown earlier, and you should see the following message in the -terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-rc1 ***** - Hello World! hexiwear - -Debugging -========= - -Here is an example for the :zephyr:code-sample:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: hexiwear/mkw40z4 - :goals: debug - -Run telnet as shown earlier, step through the application in your debugger, and -you should see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-rc1 ***** - Hello World! hexiwear - -.. include:: ../../common/board-footer.rst.inc - -.. _KW40Z Website: - https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/kinetis-cortex-m-mcus/w-serieswireless-conn.m0-plus-m4/kinetis-kw40z-2.4-ghz-dual-mode-ble-and-802.15.4-wireless-radio-microcontroller-mcu-based-on-arm-cortex-m0-plus-core:KW40Z - -.. _KW40Z Datasheet: - https://www.nxp.com/docs/en/data-sheet/MKW40Z160.pdf - -.. _KW40Z Reference Manual: - https://www.nxp.com/webapp/Download?colCode=MKW40Z160RM - -.. _Segger RTT: - https://www.segger.com/products/debug-probes/j-link/technology/about-real-time-transfer/ - -.. _OpenSDA J-Link Generic Firmware for V2.1 Bootloader: - https://www.segger.com/downloads/jlink/OpenSDA_V2_1 diff --git a/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_m4.dts b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_m4.dts index e7680d1286f1..656b9ef7a65f 100644 --- a/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_m4.dts +++ b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_m4.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "imx8mm_evk-pinctrl.dtsi" diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7.dts b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7.dts index 2b05cab20cec..bdcb9a90d0a4 100644 --- a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7.dts +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "imx8mp_evk-pinctrl.dtsi" / { diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr.dts b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr.dts index ba805ef7cbf9..9cb30b6a2ccb 100644 --- a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr.dts +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "imx8mp_evk-pinctrl.dtsi" / { diff --git a/boards/nxp/imx8mq_evk/imx8mq_evk_mimx8mq6_m4.dts b/boards/nxp/imx8mq_evk/imx8mq_evk_mimx8mq6_m4.dts index 7809ce505f7c..9ee969efc54b 100644 --- a/boards/nxp/imx8mq_evk/imx8mq_evk_mimx8mq6_m4.dts +++ b/boards/nxp/imx8mq_evk/imx8mq_evk_mimx8mq6_m4.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "imx8mq_evk-pinctrl.dtsi" / { diff --git a/boards/nxp/imx93_evk/imx93_evk_mimx9352_m33.dts b/boards/nxp/imx93_evk/imx93_evk_mimx9352_m33.dts index fbab194989f8..168fd4be2a0b 100644 --- a/boards/nxp/imx93_evk/imx93_evk_mimx9352_m33.dts +++ b/boards/nxp/imx93_evk/imx93_evk_mimx9352_m33.dts @@ -1,12 +1,11 @@ /* - * Copyright 2024-2025 NXP - * + * SPDX-FileCopyrightText: Copyright 2024-2026 NXP * SPDX-License-Identifier: Apache-2.0 */ /dts-v1/; -#include +#include #include "imx93_evk-pinctrl.dtsi" #include @@ -72,6 +71,13 @@ pinctrl-names = "default"; }; +&lpi2c2 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c2_default>; + pinctrl-names = "default"; +}; + &sar_adc1 { status = "okay"; }; diff --git a/boards/nxp/imx93_evk/imx93_evk_mimx9352_m33.yaml b/boards/nxp/imx93_evk/imx93_evk_mimx9352_m33.yaml index 62a2c3f06ec8..0f69285d14df 100644 --- a/boards/nxp/imx93_evk/imx93_evk_mimx9352_m33.yaml +++ b/boards/nxp/imx93_evk/imx93_evk_mimx9352_m33.yaml @@ -15,4 +15,5 @@ supported: - uart - pwm - adc + - i2c vendor: nxp diff --git a/boards/nxp/imx943_evk/Kconfig.imx943_evk b/boards/nxp/imx943_evk/Kconfig.imx943_evk index 37ab2872ded2..cc3b0922f878 100644 --- a/boards/nxp/imx943_evk/Kconfig.imx943_evk +++ b/boards/nxp/imx943_evk/Kconfig.imx943_evk @@ -2,7 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 config BOARD_IMX943_EVK - select SOC_MIMX94398_A55 if BOARD_IMX943_EVK_MIMX94398_A55 + select SOC_MIMX94398_A55 if BOARD_IMX943_EVK_MIMX94398_A55 || BOARD_IMX943_EVK_MIMX94398_A55_SMP select SOC_MIMX94398_M33 if BOARD_IMX943_EVK_MIMX94398_M33 || BOARD_IMX943_EVK_MIMX94398_M33_DDR select SOC_MIMX94398_M7_0 if BOARD_IMX943_EVK_MIMX94398_M7_0 select SOC_MIMX94398_M7_1 if BOARD_IMX943_EVK_MIMX94398_M7_1 diff --git a/boards/nxp/imx943_evk/board.yml b/boards/nxp/imx943_evk/board.yml index 568781db2cc9..b3ac421c6cd1 100644 --- a/boards/nxp/imx943_evk/board.yml +++ b/boards/nxp/imx943_evk/board.yml @@ -7,3 +7,5 @@ board: variants: - name: ddr cpucluster: m33 + - name: smp + cpucluster: a55 diff --git a/boards/nxp/imx943_evk/doc/index.rst b/boards/nxp/imx943_evk/doc/index.rst index 13ec782f4807..c7e44253915d 100644 --- a/boards/nxp/imx943_evk/doc/index.rst +++ b/boards/nxp/imx943_evk/doc/index.rst @@ -73,6 +73,10 @@ For A55 Core, ENET0, ENETC1, ENETC2 ports are enabled by default, so no overlay needed, but NETC depends on GIC ITS, so need to make sure to allocate heap memory to be larger than 851968 byes by setting CONFIG_HEAP_MEM_POOL_SIZE. +On the EVK board, switch port0 and port2 are connected to both SGMII port (SGMII-swp0 +and SGMII-swp1) and 100M port (swp0 and swp1), currently only 100M port (swp0 and swp1) +is enabled, so could connect to 100M port for verify two switch ports. + The two switch ports could be verified via :zephyr:code-sample:`dsa` on M33 core or on A55 Core, for example for A55 Core: @@ -201,7 +205,24 @@ Then the following log could be found on UART1 console: *** Booting Zephyr OS build v4.1.0-3650-gdb71736adb68 *** Hello World! imx943_evk/mimx94398/a55 -.. include:: ../../common/board-footer.rst.inc +Cortex-A55 SMP +============== + +The default SMP variant runs on all four Cortex-A Core, it could be changed by +disabling some A55 Core nodes in dts and change :kconfig:option:`CONFIG_MP_MAX_NUM_CPUS` +to the count of enabled A55 Cores in dts. + +Building SMP kernel, for example, with the :zephyr:code-sample:`synchronization` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :host-os: unix + :board: imx943_evk/mimx94398/a55/smp + :goals: build + +For different booting method, need to make sure SMP Zephyr to be started from the first +CPU Core listed in "cpus" dts node, so the first A55 Core in default SMP variant dts +is Core0, it could be booted by U-Boot "go" command, J-Link runner or SPSDK runner. Programming and Debugging (M33 in NETC MIX, M7_0 in M7MIX0, M7_1 in M7MIX1) *************************************************************************** @@ -428,3 +449,5 @@ and UART8, below bcu (`bcu 1.1.113 download`_) configuration is needed to use UA .. _i.MX Linux BSP release: https://www.nxp.com/design/design-center/software/embedded-software/i-mx-software/embedded-linux-for-i-mx-applications-processors:IMXLINUX + +.. include:: ../../common/board-footer.rst.inc diff --git a/boards/nxp/imx943_evk/imx943_evk_mimx94398_a55.dts b/boards/nxp/imx943_evk/imx943_evk_mimx94398_a55.dts index ae6ab2dee668..18e37f321cb6 100644 --- a/boards/nxp/imx943_evk/imx943_evk_mimx94398_a55.dts +++ b/boards/nxp/imx943_evk/imx943_evk_mimx94398_a55.dts @@ -1,5 +1,5 @@ /* - * Copyright 2025 NXP + * Copyright 2025-2026 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -13,6 +13,10 @@ model = "NXP i.MX943 A55"; compatible = "fsl,mimx943"; + aliases { + watchdog0 = &wdog4; + }; + chosen { zephyr,console = &lpuart1; zephyr,shell-uart = &lpuart1; @@ -53,13 +57,13 @@ phy0: phy@2 { compatible = "ethernet-phy"; - reg = <0xf>; + reg = <0x2>; status = "disabled"; }; phy1: phy@3 { compatible = "ethernet-phy"; - reg = <0x10>; + reg = <0x3>; status = "disabled"; }; @@ -133,3 +137,13 @@ zephyr,random-mac-address; status = "disabled"; }; + +&wdog4 { + status = "okay"; +}; + +&lpi2c6 { + pinctrl-0 = <&lpi2c6_default>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/boards/nxp/imx943_evk/imx943_evk_mimx94398_a55.yaml b/boards/nxp/imx943_evk/imx943_evk_mimx94398_a55.yaml index fd9927ef343c..52e5d8c872e5 100644 --- a/boards/nxp/imx943_evk/imx943_evk_mimx94398_a55.yaml +++ b/boards/nxp/imx943_evk/imx943_evk_mimx94398_a55.yaml @@ -1,5 +1,5 @@ # -# Copyright 2025 NXP +# Copyright 2025-2026 NXP # # SPDX-License-Identifier: Apache-2.0 # @@ -15,6 +15,8 @@ ram: 10240 supported: - counter - gpio + - i2c - net - uart + - watchdog vendor: nxp diff --git a/boards/nxp/imx943_evk/imx943_evk_mimx94398_a55_smp.dts b/boards/nxp/imx943_evk/imx943_evk_mimx94398_a55_smp.dts new file mode 100644 index 000000000000..99f5e6eeb132 --- /dev/null +++ b/boards/nxp/imx943_evk/imx943_evk_mimx94398_a55_smp.dts @@ -0,0 +1,48 @@ +/* + * SPDX-FileCopyrightText: Copyright 2026 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include "imx943_evk_mimx94398_a55.dts" + +/ { + model = "NXP i.MX943 A55"; + compatible = "fsl,mimx943"; + + chosen { + zephyr,console = &lpuart1; + zephyr,shell-uart = &lpuart1; + /* sram node actually locates at DDR DRAM */ + zephyr,sram = &dram; + }; + + psci { + compatible = "arm,psci-1.1"; + method = "smc"; + }; + + cpus { + cpu@0 { + status = "okay"; + }; + + cpu@100 { + status = "okay"; + }; + + cpu@200 { + status = "okay"; + }; + + cpu@300 { + status = "okay"; + }; + }; + + dram: memory@d0000000 { + reg = <0xd0000000 DT_SIZE_M(10)>; + }; +}; diff --git a/boards/nxp/imx943_evk/imx943_evk_mimx94398_a55_smp.yaml b/boards/nxp/imx943_evk/imx943_evk_mimx94398_a55_smp.yaml new file mode 100644 index 000000000000..3d970a802f45 --- /dev/null +++ b/boards/nxp/imx943_evk/imx943_evk_mimx94398_a55_smp.yaml @@ -0,0 +1,20 @@ +# +# SPDX-FileCopyrightText: Copyright 2026 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: imx943_evk/mimx94398/a55/smp +name: NXP i.MX943 EVK A55 SMP +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 10240 +supported: + - counter + - gpio + - net + - uart +vendor: nxp diff --git a/boards/nxp/imx943_evk/imx943_evk_mimx94398_a55_smp_defconfig b/boards/nxp/imx943_evk/imx943_evk_mimx94398_a55_smp_defconfig new file mode 100644 index 000000000000..759218d6c9e9 --- /dev/null +++ b/boards/nxp/imx943_evk/imx943_evk_mimx94398_a55_smp_defconfig @@ -0,0 +1,38 @@ +# +# SPDX-FileCopyrightText: Copyright 2026 NXP +# +# SPDX-License-Identifier: Apache-2.0 + +# ARM Options +CONFIG_AARCH64_IMAGE_HEADER=y +CONFIG_ARMV8_A_NS=y + +# MMU Options +CONFIG_MAX_XLAT_TABLES=24 + +# Cache Options +CONFIG_CACHE_MANAGEMENT=y +CONFIG_DCACHE_LINE_SIZE_DETECT=y +CONFIG_ICACHE_LINE_SIZE_DETECT=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n +CONFIG_KERNEL_DIRECT_MAP=y + +# SMP +CONFIG_SMP=y +CONFIG_MP_MAX_NUM_CPUS=4 +CONFIG_PM_CPU_OPS=y + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_CLOCK_CONTROL=y + +CONFIG_MBOX=y +CONFIG_ARM_SCMI=y diff --git a/boards/nxp/imx943_evk/imx943_evk_mimx94398_cm.dtsi b/boards/nxp/imx943_evk/imx943_evk_mimx94398_cm.dtsi index aa0bc4c9e29b..e91d88c5c553 100644 --- a/boards/nxp/imx943_evk/imx943_evk_mimx94398_cm.dtsi +++ b/boards/nxp/imx943_evk/imx943_evk_mimx94398_cm.dtsi @@ -4,8 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ -/dts-v1/; - &emdio { pinctrl-0 = <&emdio_default>; pinctrl-names = "default"; diff --git a/boards/nxp/imx943_evk/imx943_evk_mimx94398_m33.dts b/boards/nxp/imx943_evk/imx943_evk_mimx94398_m33.dts index 44a3a65520d6..4ca99823d243 100644 --- a/boards/nxp/imx943_evk/imx943_evk_mimx94398_m33.dts +++ b/boards/nxp/imx943_evk/imx943_evk_mimx94398_m33.dts @@ -6,8 +6,9 @@ /dts-v1/; -#include +#include #include "imx943_evk-pinctrl.dtsi" +#include "imx943_evk_mimx94398_cm.dtsi" / { model = "NXP i.MX943 EVK board"; @@ -22,66 +23,6 @@ }; }; -&emdio { - pinctrl-0 = <&emdio_default>; - pinctrl-names = "default"; - status = "disabled"; - - phy0: phy@2 { - compatible = "ethernet-phy"; - reg = <0x2>; - status = "disabled"; - }; - - phy1: phy@3 { - compatible = "ethernet-phy"; - reg = <0x3>; - status = "disabled"; - }; - - phy2: phy@5 { - compatible = "realtek,rtl8211f"; - reg = <0x5>; - status = "disabled"; - }; - - phy3: phy@6 { - compatible = "realtek,rtl8211f"; - reg = <0x6>; - status = "disabled"; - }; - - phy4: phy@7 { - compatible = "realtek,rtl8211f"; - reg = <0x7>; - status = "disabled"; - }; -}; - -&enetc_psi0 { - pinctrl-0 = <ð2_default>; - pinctrl-names = "default"; - phy-handle = <&phy2>; - phy-connection-type = "rgmii"; - status = "disabled"; -}; - -&enetc_psi1 { - pinctrl-0 = <ð3_default>; - pinctrl-names = "default"; - phy-handle = <&phy3>; - phy-connection-type = "rgmii"; - status = "disabled"; -}; - -&enetc_psi2 { - pinctrl-0 = <ð4_default>; - pinctrl-names = "default"; - phy-handle = <&phy4>; - phy-connection-type = "rgmii"; - status = "disabled"; -}; - &flexio1 { status = "okay"; @@ -96,6 +37,7 @@ pin-id = <5>; prescaler = <1>; }; + status = "okay"; }; }; @@ -147,3 +89,11 @@ &gpt_hw_timer1 { status = "okay"; }; + +&edma2 { + status = "okay"; +}; + +&edma4 { + status = "okay"; +}; diff --git a/boards/nxp/imx943_evk/imx943_evk_mimx94398_m7_0.dts b/boards/nxp/imx943_evk/imx943_evk_mimx94398_m7_0.dts index 1499a02213a5..ae7728ee92e3 100644 --- a/boards/nxp/imx943_evk/imx943_evk_mimx94398_m7_0.dts +++ b/boards/nxp/imx943_evk/imx943_evk_mimx94398_m7_0.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "imx943_evk-pinctrl.dtsi" / { @@ -36,6 +36,7 @@ pin-id = <5>; prescaler = <1>; }; + status = "okay"; }; }; diff --git a/boards/nxp/imx943_evk/imx943_evk_mimx94398_m7_1.dts b/boards/nxp/imx943_evk/imx943_evk_mimx94398_m7_1.dts index 06075021693b..8ce4dbe3c106 100644 --- a/boards/nxp/imx943_evk/imx943_evk_mimx94398_m7_1.dts +++ b/boards/nxp/imx943_evk/imx943_evk_mimx94398_m7_1.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "imx943_evk-pinctrl.dtsi" / { @@ -36,6 +36,7 @@ pin-id = <5>; prescaler = <1>; }; + status = "okay"; }; }; diff --git a/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.dts b/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.dts index 7e513f583660..979382fe7d5d 100644 --- a/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.dts +++ b/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "imx95_evk-pinctrl.dtsi" / { @@ -91,9 +91,9 @@ reg = <0x00720000 DT_SIZE_M(7)>; }; - storage_partition: partition@E20000 { + storage_partition: partition@e20000 { label = "storage"; - reg = <0x00E20000 (DT_SIZE_M(2) - DT_SIZE_K(128))>; + reg = <0x00e20000 (DT_SIZE_M(2) - DT_SIZE_K(128))>; }; }; }; diff --git a/boards/nxp/imx95_evk_15x15/Kconfig.imx95_evk_15x15 b/boards/nxp/imx95_evk_15x15/Kconfig.imx95_evk_15x15 index 7ec64a53b836..828e05fcc363 100644 --- a/boards/nxp/imx95_evk_15x15/Kconfig.imx95_evk_15x15 +++ b/boards/nxp/imx95_evk_15x15/Kconfig.imx95_evk_15x15 @@ -3,4 +3,6 @@ config BOARD_IMX95_EVK_15X15 select SOC_MIMX9596_A55 if BOARD_IMX95_EVK_15X15_MIMX9596_A55 - select SOC_PART_NUMBER_MIMX9596AVTXN + select SOC_MIMX9596_M7 if BOARD_IMX95_EVK_15X15_MIMX9596_M7 + # Use a part number that exists in MCUX device headers for both A55 and M7. + select SOC_PART_NUMBER_MIMX9596AVZXN diff --git a/boards/nxp/imx95_evk_15x15/imx95_evk_15x15-pinctrl.dtsi b/boards/nxp/imx95_evk_15x15/imx95_evk_15x15-pinctrl.dtsi index 657f985ca8bb..fbbafe1e3958 100644 --- a/boards/nxp/imx95_evk_15x15/imx95_evk_15x15-pinctrl.dtsi +++ b/boards/nxp/imx95_evk_15x15/imx95_evk_15x15-pinctrl.dtsi @@ -4,6 +4,7 @@ */ #include +#include "../imx95_evk/imx95_evk-pinctrl.dtsi" &pinctrl { emdio_default: emdio_default { diff --git a/boards/nxp/imx95_evk_15x15/imx95_evk_15x15_mimx9596_m7.dts b/boards/nxp/imx95_evk_15x15/imx95_evk_15x15_mimx9596_m7.dts new file mode 100644 index 000000000000..fc6e6ec34b6f --- /dev/null +++ b/boards/nxp/imx95_evk_15x15/imx95_evk_15x15_mimx9596_m7.dts @@ -0,0 +1,84 @@ +/* + * Copyright 2026 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "imx95_evk_15x15-pinctrl.dtsi" + +/ { + model = "NXP i.MX95 15x15 EVK board (M7)"; + compatible = "nxp,imx95_evk_15x15"; + + chosen { + /* TCM */ + zephyr,flash = &itcm; + zephyr,sram = &dtcm; + + zephyr,flash-controller = &mt35xu01gbba; + zephyr,console = &lpuart3; + zephyr,shell-uart = &lpuart3; + }; +}; + +/* Enable eDMA used by LPUART async API tests (LPUART dmas -> &edma2). */ +&edma2 { + status = "okay"; +}; + +/* Mirror the EVK M7 defaults */ +&emdio { + pinctrl-0 = <&emdio_default>; + pinctrl-names = "default"; + status = "okay"; + + phy0: phy@1 { + compatible = "realtek,rtl8211f"; + reg = <0x1>; + status = "okay"; + }; +}; + +&enetc_psi0 { + local-mac-address = [00 00 00 01 02 00]; + pinctrl-0 = <ð0_default>; + pinctrl-names = "default"; + phy-handle = <&phy0>; + phy-connection-type = "rgmii"; + status = "okay"; +}; + +&enetc_ptp_clock { + status = "okay"; +}; + +&flexspi { + status = "okay"; + ahb-prefetch; + ahb-read-addr-opt; + rx-clock-source = <1>; + pinctrl-0 = <&flexspi_default>; + pinctrl-names = "default"; + + mt35xu01gbba: mt35xu01gbba@0 { + compatible = "nxp,imx-flexspi-nor"; + size = ; + reg = <0>; + spi-max-frequency = ; + status = "okay"; + jedec-id = [2c 5b 1b]; + erase-block-size = ; + write-block-size = <2>; + }; +}; + +/* Enable UART used by chosen zephyr,console / zephyr,shell-uart */ +&lpuart3 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&lpuart3_default>; + pinctrl-names = "default"; +}; diff --git a/boards/nxp/imx95_evk_15x15/imx95_evk_15x15_mimx9596_m7.yaml b/boards/nxp/imx95_evk_15x15/imx95_evk_15x15_mimx9596_m7.yaml new file mode 100644 index 000000000000..6dd5c4eccb74 --- /dev/null +++ b/boards/nxp/imx95_evk_15x15/imx95_evk_15x15_mimx9596_m7.yaml @@ -0,0 +1,26 @@ +# +# Copyright 2026 NXP +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: imx95_evk_15x15/mimx9596/m7 +name: NXP i.MX95 15x15 EVK (M7) +type: mcu +arch: arm +ram: 256 +flash: 256 +toolchain: + - zephyr + - gnuarmemb +supported: + - uart + - i2c + - pwm + - spi + - netif:eth + - counter + - dma +testing: + binaries: + - flash.bin +vendor: nxp diff --git a/boards/nxp/imx95_evk_15x15/imx95_evk_15x15_mimx9596_m7_defconfig b/boards/nxp/imx95_evk_15x15/imx95_evk_15x15_mimx9596_m7_defconfig new file mode 100644 index 000000000000..c46c05575bcb --- /dev/null +++ b/boards/nxp/imx95_evk_15x15/imx95_evk_15x15_mimx9596_m7_defconfig @@ -0,0 +1,16 @@ +# +# Copyright 2026 NXP +# SPDX-License-Identifier: Apache-2.0 +# + +# Keep aligned with imx95_evk M7 defconfig +CONFIG_CLOCK_CONTROL=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y +CONFIG_XIP=y +CONFIG_MBOX=y +CONFIG_MBOX_INIT_PRIORITY=0 +CONFIG_ARM_SCMI=y +CONFIG_ARM_SCMI_NXP_VENDOR_EXTENSIONS=y diff --git a/boards/nxp/lpcxpresso11u68/lpcxpresso11u68.dts b/boards/nxp/lpcxpresso11u68/lpcxpresso11u68.dts index cdb4f72387b0..5b2c1d4ae7ae 100644 --- a/boards/nxp/lpcxpresso11u68/lpcxpresso11u68.dts +++ b/boards/nxp/lpcxpresso11u68/lpcxpresso11u68.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include #include diff --git a/boards/nxp/lpcxpresso11u68/lpcxpresso11u68.yaml b/boards/nxp/lpcxpresso11u68/lpcxpresso11u68.yaml index 192ca797f629..395d7ef378b1 100644 --- a/boards/nxp/lpcxpresso11u68/lpcxpresso11u68.yaml +++ b/boards/nxp/lpcxpresso11u68/lpcxpresso11u68.yaml @@ -1,5 +1,5 @@ identifier: lpcxpresso11u68 -name: NXP LPCxpresso 11U68 +name: NXP LPCxpresso11U68 type: mcu arch: arm ram: 32 diff --git a/boards/nxp/lpcxpresso51u68/lpcxpresso51u68.dts b/boards/nxp/lpcxpresso51u68/lpcxpresso51u68.dts index 120b0565494a..ef91c3537864 100644 --- a/boards/nxp/lpcxpresso51u68/lpcxpresso51u68.dts +++ b/boards/nxp/lpcxpresso51u68/lpcxpresso51u68.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "lpcxpresso51u68-pinctrl.dtsi" #include diff --git a/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m0.dts b/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m0.dts index e753dd2fadd0..dc3f86f778b1 100644 --- a/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m0.dts +++ b/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m0.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "lpcxpresso54114.dtsi" / { diff --git a/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m0.yaml b/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m0.yaml index 8294367fcbd0..17cc1eb2d2d8 100644 --- a/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m0.yaml +++ b/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m0.yaml @@ -5,7 +5,7 @@ # identifier: lpcxpresso54114/lpc54114/m0 -name: NXP LPCXpresso54114 M0 +name: NXP LPCXpresso54114 (M0) type: mcu arch: arm ram: 32 diff --git a/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m4.dts b/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m4.dts index 17a45a0f5d58..f4109d68575b 100644 --- a/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m4.dts +++ b/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m4.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "lpcxpresso54114.dtsi" #include diff --git a/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m4.yaml b/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m4.yaml index f1f13fb5cdae..8e0db4faf46f 100644 --- a/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m4.yaml +++ b/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m4.yaml @@ -5,7 +5,7 @@ # identifier: lpcxpresso54114/lpc54114/m4 -name: NXP LPCXpresso54114 M4 +name: NXP LPCXpresso54114 (M4) type: mcu arch: arm ram: 64 diff --git a/boards/nxp/lpcxpresso55s06/lpcxpresso55s06.dts b/boards/nxp/lpcxpresso55s06/lpcxpresso55s06.dts index 8ed9291b68ff..b43efc349402 100644 --- a/boards/nxp/lpcxpresso55s06/lpcxpresso55s06.dts +++ b/boards/nxp/lpcxpresso55s06/lpcxpresso55s06.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "lpcxpresso55s06_common.dtsi" / { diff --git a/boards/nxp/lpcxpresso55s16/lpcxpresso55s16.dts b/boards/nxp/lpcxpresso55s16/lpcxpresso55s16.dts index 0baeb3e62932..776c1ec5d25e 100644 --- a/boards/nxp/lpcxpresso55s16/lpcxpresso55s16.dts +++ b/boards/nxp/lpcxpresso55s16/lpcxpresso55s16.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include +#include #include "lpcxpresso55s16_common.dtsi" / { diff --git a/boards/nxp/lpcxpresso55s28/lpcxpresso55s28.dts b/boards/nxp/lpcxpresso55s28/lpcxpresso55s28.dts index 08f9ef600cf9..287c0f840ff4 100644 --- a/boards/nxp/lpcxpresso55s28/lpcxpresso55s28.dts +++ b/boards/nxp/lpcxpresso55s28/lpcxpresso55s28.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include +#include #include "lpcxpresso55s28_common.dtsi" #include @@ -33,6 +33,7 @@ zephyr,shell-uart = &flexcomm0; zephyr,entropy = &rng; zephyr,flash-controller = &iap; + zephyr,crc = &crc; }; gpio_keys { @@ -118,9 +119,9 @@ reg = <0x00008000 DT_SIZE_K(208)>; }; - slot1_partition: partition@3C000 { + slot1_partition: partition@3c000 { label = "image-1"; - reg = <0x0003C000 DT_SIZE_K(208)>; + reg = <0x0003c000 DT_SIZE_K(208)>; }; storage_partition: partition@70000 { @@ -167,3 +168,7 @@ zephyr_uhc1: &usbhhs { disk-name = "SD"; }; }; + +&crc { + status = "okay"; +}; diff --git a/boards/nxp/lpcxpresso55s28/lpcxpresso55s28_common.dtsi b/boards/nxp/lpcxpresso55s28/lpcxpresso55s28_common.dtsi index 6a2531d23b60..9e1373772db3 100644 --- a/boards/nxp/lpcxpresso55s28/lpcxpresso55s28_common.dtsi +++ b/boards/nxp/lpcxpresso55s28/lpcxpresso55s28_common.dtsi @@ -21,19 +21,19 @@ compatible = "gpio-leds"; green_led: led_1 { - gpios = <&gpio1 7 0>; + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; label = "User LD2"; status = "disabled"; }; blue_led: led_2 { - gpios = <&gpio1 4 0>; + gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; label = "User LD3"; status = "disabled"; }; red_led: led_3 { - gpios = <&gpio1 6 0>; + gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; label = "User LD4"; status = "disabled"; }; diff --git a/boards/nxp/lpcxpresso55s36/lpcxpresso55s36-pinctrl.dtsi b/boards/nxp/lpcxpresso55s36/lpcxpresso55s36-pinctrl.dtsi index 306da273f3c1..d3ba959c8abe 100644 --- a/boards/nxp/lpcxpresso55s36/lpcxpresso55s36-pinctrl.dtsi +++ b/boards/nxp/lpcxpresso55s36/lpcxpresso55s36-pinctrl.dtsi @@ -135,4 +135,12 @@ nxp,analog-mode; }; }; + + pinmux_hscmp0: pinmux_hscmp0 { + group0 { + pinmux = ; + slew-rate = "standard"; + nxp,analog-mode; + }; + }; }; diff --git a/boards/nxp/lpcxpresso55s36/lpcxpresso55s36.dts b/boards/nxp/lpcxpresso55s36/lpcxpresso55s36.dts index 46da74e55e31..cd717e393035 100644 --- a/boards/nxp/lpcxpresso55s36/lpcxpresso55s36.dts +++ b/boards/nxp/lpcxpresso55s36/lpcxpresso55s36.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "lpcxpresso55s36-pinctrl.dtsi" #include #include @@ -214,3 +214,9 @@ zephyr_udc0: &usbfs { pinctrl-0 = <&pinmux_opamp0>; pinctrl-names = "default"; }; + +&hscmp0 { + status = "okay"; + pinctrl-0 = <&pinmux_hscmp0>; + pinctrl-names = "default"; +}; diff --git a/boards/nxp/lpcxpresso55s36/lpcxpresso55s36.yaml b/boards/nxp/lpcxpresso55s36/lpcxpresso55s36.yaml index 68c9e00555b0..1cbf188bbf4c 100644 --- a/boards/nxp/lpcxpresso55s36/lpcxpresso55s36.yaml +++ b/boards/nxp/lpcxpresso55s36/lpcxpresso55s36.yaml @@ -23,4 +23,5 @@ supported: - pwm - usb_device - usbd + - comparator vendor: nxp diff --git a/boards/nxp/lpcxpresso55s69/doc/index.rst b/boards/nxp/lpcxpresso55s69/doc/index.rst index be66a72e689c..4cd6feb3dec0 100644 --- a/boards/nxp/lpcxpresso55s69/doc/index.rst +++ b/boards/nxp/lpcxpresso55s69/doc/index.rst @@ -268,8 +268,8 @@ see the following message in the terminal: ***** Booting Zephyr OS v3.7.0 ***** Hello World! lpcxpresso55s69/lpc55s69/cpu0 -Building and flashing secure/non-secure with Arm |reg| TrustZone |reg| ----------------------------------------------------------------------- +Building and flashing secure/non-secure with Arm® TrustZone® +------------------------------------------------------------ The TF-M integration samples can be run using the ``lpcxpresso55s69/lpc55s69/cpu0/ns`` target. To run we need to manually flash the resulting image (``tfm_merged.hex``) with a J-Link as follows diff --git a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0.dts b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0.dts index f25e69c574c3..499ecb627f33 100644 --- a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0.dts +++ b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "lpcxpresso55s69.dtsi" #include #include diff --git a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns.dts b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns.dts index 9bad03c71dd2..8985d7210234 100644 --- a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns.dts +++ b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "lpcxpresso55s69.dtsi" #include diff --git a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns.yaml b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns.yaml index ee3a4348eb02..ab0331e7bf61 100644 --- a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns.yaml +++ b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns.yaml @@ -5,7 +5,7 @@ # identifier: lpcxpresso55s69/lpc55s69/cpu0/ns -name: NXP LPCXpresso55S69 (Non-Secure) +name: NXP LPCXpresso55S69 (CPU0) (Non-Secure) type: mcu arch: arm ram: 136 diff --git a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu1.dts b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu1.dts index 2e8760b9961e..80db2ad4e8f6 100644 --- a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu1.dts +++ b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu1.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "lpcxpresso55s69.dtsi" / { diff --git a/boards/nxp/mcx_nx4x_evk/CMakeLists.txt b/boards/nxp/mcx_nx4x_evk/CMakeLists.txt index d12527c90b1e..def454d5950d 100644 --- a/boards/nxp/mcx_nx4x_evk/CMakeLists.txt +++ b/boards/nxp/mcx_nx4x_evk/CMakeLists.txt @@ -9,7 +9,6 @@ zephyr_library_sources(board.c) if(CONFIG_FLEXSPI_CONFIG_BLOCK_OFFSET) # Include flash configuration block - zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) zephyr_library_sources(xip/mcxn_flexspi_nor_config.c) zephyr_library_include_directories(xip) endif() diff --git a/boards/nxp/mcx_nx4x_evk/board.c b/boards/nxp/mcx_nx4x_evk/board.c index 1389e7bf285a..32f7e27de7de 100644 --- a/boards/nxp/mcx_nx4x_evk/board.c +++ b/boards/nxp/mcx_nx4x_evk/board.c @@ -286,8 +286,8 @@ void board_early_init_hook(void) #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcan0)) - CLOCK_SetClkDiv(kCLOCK_DivFlexcan0Clk, 1U); - CLOCK_AttachClk(kFRO_HF_to_FLEXCAN0); + CLOCK_SetClkDiv(kCLOCK_DivFlexcan0Clk, 3U); + CLOCK_AttachClk(kPLL0_to_FLEXCAN0); #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usdhc0)) diff --git a/boards/nxp/mcx_nx4x_evk/doc/mcx_n9xx_evk.rst b/boards/nxp/mcx_nx4x_evk/doc/mcx_n9xx_evk.rst index b64e2477f323..1f0872f01347 100644 --- a/boards/nxp/mcx_nx4x_evk/doc/mcx_n9xx_evk.rst +++ b/boards/nxp/mcx_nx4x_evk/doc/mcx_n9xx_evk.rst @@ -41,10 +41,12 @@ Supported Features Shields for Supported Features ============================== + Some features in the table above are tested with Zephyr shields. These shields are tested on this board: + - :ref:`lcd_par_s035` - supports the Display interface. This board uses the -MIPI_DBI interface of the shield, connected to the FlexIO on-chip peripheral. + MIPI_DBI interface of the shield, connected to the FlexIO on-chip peripheral. Dual Core samples ***************** @@ -360,10 +362,10 @@ Troubleshooting https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/mcx-arm-cortex-m/mcx-n-series-microcontrollers/mcx-n94x-54x-highly-integrated-multicore-mcus-with-on-chip-accelerators-intelligent-peripherals-and-advanced-security:MCX-N94X-N54X .. _MCX-N947 Datasheet: - https://www.nxp.com/docs/en/data-sheet/MCXNx4xDS.pdf + https://www.nxp.com/docs/en/data-sheet/MCXNP184M150F70.pdf .. _MCX-N947 Reference Manual: - https://www.nxp.com/webapp/Download?colCode=MCXNX4XRM + https://www.nxp.com/webapp/Download?colCode=MCXNP184M150F70RM .. _MCX-N9XX-EVK Website: https://www.nxp.com/design/design-center/development-boards-and-designs/MCX-N9XX-EVK diff --git a/boards/nxp/mcx_nx4x_evk/mcx_n5xx_evk.dtsi b/boards/nxp/mcx_nx4x_evk/mcx_n5xx_evk.dtsi index 70a54d021dad..6432962fc427 100644 --- a/boards/nxp/mcx_nx4x_evk/mcx_n5xx_evk.dtsi +++ b/boards/nxp/mcx_nx4x_evk/mcx_n5xx_evk.dtsi @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include #include "mcx_nx4x_evk.dtsi" #include "mcx_n5xx_evk-pinctrl.dtsi" diff --git a/boards/nxp/mcx_nx4x_evk/mcx_n9xx_evk-pinctrl.dtsi b/boards/nxp/mcx_nx4x_evk/mcx_n9xx_evk-pinctrl.dtsi index c5f71871869d..63eff21b8500 100644 --- a/boards/nxp/mcx_nx4x_evk/mcx_n9xx_evk-pinctrl.dtsi +++ b/boards/nxp/mcx_nx4x_evk/mcx_n9xx_evk-pinctrl.dtsi @@ -34,9 +34,9 @@ }; }; - pinmux_lpcmp2: pinmux_lpcmp2 { + pinmux_lpcmp0: pinmux_lpcmp0 { group0 { - pinmux = ; + pinmux = ; drive-strength = "low"; slew-rate = "fast"; bias-pull-up; diff --git a/boards/nxp/mcx_nx4x_evk/mcx_n9xx_evk.dtsi b/boards/nxp/mcx_nx4x_evk/mcx_n9xx_evk.dtsi index 094daa03e933..cb0bcbab1b9d 100644 --- a/boards/nxp/mcx_nx4x_evk/mcx_n9xx_evk.dtsi +++ b/boards/nxp/mcx_nx4x_evk/mcx_n9xx_evk.dtsi @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include #include "mcx_nx4x_evk.dtsi" #include "mcx_n9xx_evk-pinctrl.dtsi" @@ -12,8 +12,3 @@ pinctrl-0 = <&pinmux_flexpwm1_pwm0>; pinctrl-names = "default"; }; - -&lpcmp2 { - pinctrl-0 = <&pinmux_lpcmp2>; - pinctrl-names = "default"; -}; diff --git a/boards/nxp/mcx_nx4x_evk/mcx_n9xx_evk_mcxn947_cpu0.dtsi b/boards/nxp/mcx_nx4x_evk/mcx_n9xx_evk_mcxn947_cpu0.dtsi index fbe9e75a772d..031bbc98ac24 100644 --- a/boards/nxp/mcx_nx4x_evk/mcx_n9xx_evk_mcxn947_cpu0.dtsi +++ b/boards/nxp/mcx_nx4x_evk/mcx_n9xx_evk_mcxn947_cpu0.dtsi @@ -22,7 +22,3 @@ &flexpwm1_pwm0 { status = "okay"; }; - -&lpcmp2 { - status = "okay"; -}; diff --git a/boards/nxp/mcx_nx4x_evk/mcx_n9xx_evk_mcxn947_cpu0.yaml b/boards/nxp/mcx_nx4x_evk/mcx_n9xx_evk_mcxn947_cpu0.yaml index dd0b5d2e7732..9bf4a314b0f7 100644 --- a/boards/nxp/mcx_nx4x_evk/mcx_n9xx_evk_mcxn947_cpu0.yaml +++ b/boards/nxp/mcx_nx4x_evk/mcx_n9xx_evk_mcxn947_cpu0.yaml @@ -25,6 +25,7 @@ supported: - i2s - i3c - nvs + - netif:eth - pwm - regulator - rtc diff --git a/boards/nxp/mcx_nx4x_evk/mcx_n9xx_evk_mcxn947_cpu0_qspi.yaml b/boards/nxp/mcx_nx4x_evk/mcx_n9xx_evk_mcxn947_cpu0_qspi.yaml index c2b1422dfe4c..9a47d0dc8f68 100644 --- a/boards/nxp/mcx_nx4x_evk/mcx_n9xx_evk_mcxn947_cpu0_qspi.yaml +++ b/boards/nxp/mcx_nx4x_evk/mcx_n9xx_evk_mcxn947_cpu0_qspi.yaml @@ -5,7 +5,7 @@ # identifier: mcx_n9xx_evk/mcxn947/cpu0/qspi -name: NXP MCX-N9XX-EVK QSPI (CPU0) +name: NXP MCX-N9XX-EVK (CPU0) (QSPI) type: mcu arch: arm ram: 320 diff --git a/boards/nxp/mcx_nx4x_evk/mcx_n9xx_evk_mcxn947_cpu1.dts b/boards/nxp/mcx_nx4x_evk/mcx_n9xx_evk_mcxn947_cpu1.dts index 68ee11d26595..0eaa069fd032 100644 --- a/boards/nxp/mcx_nx4x_evk/mcx_n9xx_evk_mcxn947_cpu1.dts +++ b/boards/nxp/mcx_nx4x_evk/mcx_n9xx_evk_mcxn947_cpu1.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "mcx_n9xx_evk.dtsi" / { diff --git a/boards/nxp/mcx_nx4x_evk/mcx_nx4x_evk-pinctrl.dtsi b/boards/nxp/mcx_nx4x_evk/mcx_nx4x_evk-pinctrl.dtsi index 36412f7a75f6..1075a1242d35 100644 --- a/boards/nxp/mcx_nx4x_evk/mcx_nx4x_evk-pinctrl.dtsi +++ b/boards/nxp/mcx_nx4x_evk/mcx_nx4x_evk-pinctrl.dtsi @@ -47,6 +47,7 @@ slew-rate = "fast"; drive-strength = "low"; input-enable; + bias-pull-up; }; }; @@ -57,6 +58,7 @@ slew-rate = "fast"; drive-strength = "low"; input-enable; + bias-pull-up; }; }; @@ -261,4 +263,31 @@ input-enable; }; }; + + flexpwm0_pwm0_default: flexpwm0_pwm0_default { + group0 { + pinmux = ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + }; + }; + + flexpwm0_pwm1_default: flexpwm0_pwm1_default { + group0 { + pinmux = ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + }; + }; + + flexpwm0_pwm2_default: flexpwm0_pwm2_default { + group0 { + pinmux = ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + }; + }; }; diff --git a/boards/nxp/mcx_nx4x_evk/mcx_nx4x_evk.dtsi b/boards/nxp/mcx_nx4x_evk/mcx_nx4x_evk.dtsi index 8332a3eea471..8087c6d5e975 100644 --- a/boards/nxp/mcx_nx4x_evk/mcx_nx4x_evk.dtsi +++ b/boards/nxp/mcx_nx4x_evk/mcx_nx4x_evk.dtsi @@ -5,6 +5,7 @@ */ #include +#include #include / { @@ -40,6 +41,23 @@ }; }; + pwmleds { + compatible = "pwm-leds"; + status = "disabled"; + + green_pwm_led: green_pwm_led { + pwms = <&flexpwm0_pwm0 2 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + }; + + blue_pwm_led: blue_pwm_led { + pwms = <&flexpwm0_pwm1 2 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + }; + + red_pwm_led: red_pwm_led { + pwms = <&flexpwm0_pwm2 2 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + }; + }; + gpio_keys { compatible = "gpio-keys"; @@ -146,9 +164,9 @@ nxp_8080_touch_panel_i2c: &flexcomm2_lpi2c2 { reg = <0x00014000 DT_SIZE_K(984)>; }; - slot1_partition: partition@10A000 { + slot1_partition: partition@10a000 { label = "image-1"; - reg = <0x0010A000 DT_SIZE_K(984)>; + reg = <0x0010a000 DT_SIZE_K(984)>; }; /* storage_partition is placed in WINBOND flash memory*/ @@ -172,7 +190,7 @@ nxp_8080_touch_panel_i2c: &flexcomm2_lpi2c2 { size = ; reg = <0>; spi-max-frequency = ; - jedec-id = [ef 40 17]; + jedec-id = [ef 60 17]; erase-block-size = ; write-block-size = <1>; cs-interval-unit = <1>; @@ -258,3 +276,18 @@ zephyr_mipi_dbi_parallel: &flexio0_lcd { pinctrl-0 = <&pinmux_sctimer>; pinctrl-names = "default"; }; + +&flexpwm0_pwm0 { + pinctrl-0 = <&flexpwm0_pwm0_default>; + pinctrl-names = "default"; +}; + +&flexpwm0_pwm1 { + pinctrl-0 = <&flexpwm0_pwm1_default>; + pinctrl-names = "default"; +}; + +&flexpwm0_pwm2 { + pinctrl-0 = <&flexpwm0_pwm2_default>; + pinctrl-names = "default"; +}; diff --git a/boards/nxp/mcx_nx4x_evk/mcx_nx4x_evk_cpu0.dtsi b/boards/nxp/mcx_nx4x_evk/mcx_nx4x_evk_cpu0.dtsi index a9da2b8fdef5..1d7b181f31ed 100644 --- a/boards/nxp/mcx_nx4x_evk/mcx_nx4x_evk_cpu0.dtsi +++ b/boards/nxp/mcx_nx4x_evk/mcx_nx4x_evk_cpu0.dtsi @@ -23,6 +23,7 @@ zephyr,shell-uart = &flexcomm4_lpuart4; zephyr,canbus = &flexcan0; zephyr,code-cpu1-partition = &slot1_partition; + zephyr,cortex-m-idle-timer = &lptmr0; }; aliases { @@ -247,3 +248,15 @@ zephyr_udc0: &usb1 { &sai1 { status = "okay"; }; + +&flexpwm0_pwm0 { + status = "okay"; +}; + +&flexpwm0_pwm1 { + status = "okay"; +}; + +&flexpwm0_pwm2 { + status = "okay"; +}; diff --git a/boards/nxp/mcx_nx4x_evk/xip/mcxn_flexspi_nor_config.h b/boards/nxp/mcx_nx4x_evk/xip/mcxn_flexspi_nor_config.h index 49ed7a5699f6..800a92345c52 100644 --- a/boards/nxp/mcx_nx4x_evk/xip/mcxn_flexspi_nor_config.h +++ b/boards/nxp/mcx_nx4x_evk/xip/mcxn_flexspi_nor_config.h @@ -109,7 +109,7 @@ enum { FLEXSPI_MISC_OFFSET_SAFE_CONFIG_FREQ_ENABLE = 4, /* Bit for Pad setting override enable */ FLEXSPI_MISC_OFFSET_PAD_SETTING_OVERRIDE_ENABLE = 5, - /* Bit for DDR clock confiuration indication. */ + /* Bit for DDR clock configuration indication. */ FLEXSPI_MISC_OFFSET_DDR_MODE_ENABLE = 6, }; @@ -239,7 +239,7 @@ typedef struct flexspi_config { * 8 - Octal */ uint8_t sflash_pad_type; - /* [0x046-0x046] Serial Flash Frequencey, device specific + /* [0x046-0x046] Serial Flash Frequency, device specific * definitions, See System Boot Chapter for more details */ uint8_t serial_clk_freq; @@ -355,7 +355,7 @@ typedef struct _flexspi_nor_config { uint8_t need_exit_nocmd_mode; /* Half the Serial Clock for non-read command: true/false */ uint8_t half_clk_for_non_read_cmd; - /* Need to Restore NoCmd mode after IP commmand execution */ + /* Need to Restore NoCmd mode after IP command execution */ uint8_t need_restore_nocmd_mode; /* Block size */ uint32_t block_size; diff --git a/boards/nxp/mcxw23_evk/doc/index.rst b/boards/nxp/mcxw23_evk/doc/index.rst index 866dc06715f6..49285337fe9b 100644 --- a/boards/nxp/mcxw23_evk/doc/index.rst +++ b/boards/nxp/mcxw23_evk/doc/index.rst @@ -180,6 +180,14 @@ should see the following message in the terminal: *** Booting Zephyr OS build v4.2.0-2105-g9da1d56da9e7 *** Hello World! mcxw23_evk/mcxw236 +Power Management +================ + +When Power Management is enabled :kconfig:option:`CONFIG_PM`, OSTIMER is used as +OS tick timer. + +Limitation: Wakeup pin can't be used as wakeup source in Standby mode. + .. include:: ../../common/board-footer.rst.inc .. _MCXW23 SoC Website: diff --git a/boards/nxp/mcxw23_evk/dts/bypass_first_32k.overlay b/boards/nxp/mcxw23_evk/dts/bypass_first_32k.overlay index 7b61d0957bab..51d95fefdacd 100644 --- a/boards/nxp/mcxw23_evk/dts/bypass_first_32k.overlay +++ b/boards/nxp/mcxw23_evk/dts/bypass_first_32k.overlay @@ -5,5 +5,5 @@ */ &sram0 { - reg = <0x2000C000 DT_SIZE_K(80)>; + reg = <0x2000c000 DT_SIZE_K(80)>; }; diff --git a/boards/nxp/mcxw23_evk/mcxw23_evk.dts b/boards/nxp/mcxw23_evk/mcxw23_evk.dts index 94760f959a4e..7476ad2f1c48 100644 --- a/boards/nxp/mcxw23_evk/mcxw23_evk.dts +++ b/boards/nxp/mcxw23_evk/mcxw23_evk.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "mcxw23_evk_common.dtsi" / { diff --git a/boards/nxp/mcxw23_evk/mcxw23_evk_common.dtsi b/boards/nxp/mcxw23_evk/mcxw23_evk_common.dtsi index c21e8e277696..75e8ed58a176 100644 --- a/boards/nxp/mcxw23_evk/mcxw23_evk_common.dtsi +++ b/boards/nxp/mcxw23_evk/mcxw23_evk_common.dtsi @@ -156,15 +156,14 @@ pinctrl-names = "default"; }; -/* - * MCXW23 EVK board uses SYSTICK timer as the kernel timer. - * In case we need to switch to OS timer, then - * replace &systick with &os_timer - */ &systick { status = "okay"; }; +&os_timer { + status = "okay"; +}; + &wwdt0 { status = "okay"; }; diff --git a/boards/nxp/mcxw72_evk/mcxw72_evk_mcxw727c_cpu0.dts b/boards/nxp/mcxw72_evk/mcxw72_evk_mcxw727c_cpu0.dts index 672f7712c6cf..d0cd34a10b19 100644 --- a/boards/nxp/mcxw72_evk/mcxw72_evk_mcxw727c_cpu0.dts +++ b/boards/nxp/mcxw72_evk/mcxw72_evk_mcxw727c_cpu0.dts @@ -5,7 +5,7 @@ /dts-v1/; -#include +#include #include "mcxw72_evk-pinctrl.dtsi" #include #include @@ -134,13 +134,13 @@ reg = <0x0 DT_SIZE_K(2024)>; }; - storage_partition: partition@1FA000 { - reg = <0x1FA000 DT_SIZE_K(16)>; + storage_partition: partition@1fa000 { + reg = <0x1fa000 DT_SIZE_K(16)>; }; - hw_params_partition: partition@1FE000 { + hw_params_partition: partition@1fe000 { label = "hw-parameters"; - reg = <0x1FE000 DT_SIZE_K(8)>; + reg = <0x1fe000 DT_SIZE_K(8)>; }; }; }; diff --git a/boards/nxp/mcxw72_evk/mcxw72_evk_mcxw727c_cpu0.yaml b/boards/nxp/mcxw72_evk/mcxw72_evk_mcxw727c_cpu0.yaml index f3f9a54cf1da..518afbadeaa3 100644 --- a/boards/nxp/mcxw72_evk/mcxw72_evk_mcxw727c_cpu0.yaml +++ b/boards/nxp/mcxw72_evk/mcxw72_evk_mcxw727c_cpu0.yaml @@ -1,5 +1,5 @@ identifier: mcxw72_evk/mcxw727c/cpu0 -name: NXP MCXW72_EVK +name: NXP MCXW72-EVK type: mcu arch: arm ram: 264 diff --git a/boards/nxp/mimxrt1010_evk/CMakeLists.txt b/boards/nxp/mimxrt1010_evk/CMakeLists.txt index 08fee53a4117..0ec99819388c 100644 --- a/boards/nxp/mimxrt1010_evk/CMakeLists.txt +++ b/boards/nxp/mimxrt1010_evk/CMakeLists.txt @@ -17,8 +17,6 @@ if(CONFIG_NXP_IMXRT_BOOT_HEADER) # This flash configuration block may need modification if another # flash chip is used on your custom board. See NXP AN12238 for more # information. - zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) - zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) zephyr_library_sources(xip/evkmimxrt1010_flexspi_nor_config.c) zephyr_library_include_directories(xip) endif() diff --git a/boards/nxp/mimxrt1010_evk/mimxrt1010_evk.dts b/boards/nxp/mimxrt1010_evk/mimxrt1010_evk.dts index bf416dae98e7..e56067bceeb3 100644 --- a/boards/nxp/mimxrt1010_evk/mimxrt1010_evk.dts +++ b/boards/nxp/mimxrt1010_evk/mimxrt1010_evk.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include +#include #include "mimxrt1010_evk-pinctrl.dtsi" #include #include @@ -130,9 +130,9 @@ arduino_serial: &lpuart1 {}; reg = <0x00720000 DT_SIZE_M(7)>; }; - storage_partition: partition@E20000 { + storage_partition: partition@e20000 { label = "storage"; - reg = <0x00E20000 (DT_SIZE_M(2) - DT_SIZE_K(128))>; + reg = <0x00e20000 (DT_SIZE_M(2) - DT_SIZE_K(128))>; }; }; }; diff --git a/boards/nxp/mimxrt1010_evk/xip/evkmimxrt1010_flexspi_nor_config.c b/boards/nxp/mimxrt1010_evk/xip/evkmimxrt1010_flexspi_nor_config.c index f98b40271b1f..05947cf5fda6 100644 --- a/boards/nxp/mimxrt1010_evk/xip/evkmimxrt1010_flexspi_nor_config.c +++ b/boards/nxp/mimxrt1010_evk/xip/evkmimxrt1010_flexspi_nor_config.c @@ -7,7 +7,7 @@ #include "evkmimxrt1010_flexspi_nor_config.h" -#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) __attribute__((section(".boot_hdr.conf"), used)) const flexspi_nor_config_t qspi_flash_config = { @@ -63,4 +63,4 @@ const flexspi_nor_config_t qspi_flash_config = { .is_uniform_block_size = false, }; -#endif /* XIP_BOOT_HEADER_ENABLE */ +#endif /* defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) */ diff --git a/boards/nxp/mimxrt1010_evk/xip/evkmimxrt1010_flexspi_nor_config.h b/boards/nxp/mimxrt1010_evk/xip/evkmimxrt1010_flexspi_nor_config.h index 8240795e0d29..c757440148d2 100644 --- a/boards/nxp/mimxrt1010_evk/xip/evkmimxrt1010_flexspi_nor_config.h +++ b/boards/nxp/mimxrt1010_evk/xip/evkmimxrt1010_flexspi_nor_config.h @@ -112,7 +112,7 @@ enum { FLEXSPI_MISC_OFFSET_SAFE_CONFIG_FREQ_ENABLE = 4, /* Bit for Pad setting override enable */ FLEXSPI_MISC_OFFSET_PAD_SETTING_OVERRIDE_ENABLE = 5, - /* Bit for DDR clock confiuration indication. */ + /* Bit for DDR clock configuration indication. */ FLEXSPI_MISC_OFFSET_DDR_MODE_ENABLE = 6, }; @@ -238,7 +238,7 @@ typedef struct flexspi_config { * 8 - Octal */ uint8_t sflash_pad_type; - /* [0x046-0x046] Serial Flash Frequencey, device specific + /* [0x046-0x046] Serial Flash Frequency, device specific * definitions, See System Boot Chapter for more details */ uint8_t serial_clk_freq; @@ -352,7 +352,7 @@ typedef struct _flexspi_nor_config { uint8_t need_exit_nocmd_mode; /* Half the Serial Clock for non-read command: true/false */ uint8_t half_clk_for_non_read_cmd; - /* Need to Restore NoCmd mode after IP commmand execution */ + /* Need to Restore NoCmd mode after IP command execution */ uint8_t need_restore_nocmd_mode; /* Block size */ uint32_t block_size; diff --git a/boards/nxp/mimxrt1015_evk/CMakeLists.txt b/boards/nxp/mimxrt1015_evk/CMakeLists.txt index c4c7adf0e77d..1c022b96173d 100644 --- a/boards/nxp/mimxrt1015_evk/CMakeLists.txt +++ b/boards/nxp/mimxrt1015_evk/CMakeLists.txt @@ -16,8 +16,6 @@ if(CONFIG_NXP_IMXRT_BOOT_HEADER) # This flash configuration block may need modification if another # flash chip is used on your custom board. See NXP AN12238 for more # information. - zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) - zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) zephyr_library_sources(xip/evkmimxrt1015_flexspi_nor_config.c) zephyr_library_include_directories(xip) endif() diff --git a/boards/nxp/mimxrt1015_evk/mimxrt1015_evk.dts b/boards/nxp/mimxrt1015_evk/mimxrt1015_evk.dts index 22f2cab4767d..5c5af52cd593 100644 --- a/boards/nxp/mimxrt1015_evk/mimxrt1015_evk.dts +++ b/boards/nxp/mimxrt1015_evk/mimxrt1015_evk.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "mimxrt1015_evk-pinctrl.dtsi" #include #include @@ -127,9 +127,9 @@ arduino_serial: &lpuart4 { reg = <0x00720000 DT_SIZE_M(7)>; }; - storage_partition: partition@E20000 { + storage_partition: partition@e20000 { label = "storage"; - reg = <0x00E20000 (DT_SIZE_M(2) - DT_SIZE_K(128))>; + reg = <0x00e20000 (DT_SIZE_M(2) - DT_SIZE_K(128))>; }; }; }; diff --git a/boards/nxp/mimxrt1015_evk/xip/evkmimxrt1015_flexspi_nor_config.c b/boards/nxp/mimxrt1015_evk/xip/evkmimxrt1015_flexspi_nor_config.c index 2828312818c9..5582b4754c51 100644 --- a/boards/nxp/mimxrt1015_evk/xip/evkmimxrt1015_flexspi_nor_config.c +++ b/boards/nxp/mimxrt1015_evk/xip/evkmimxrt1015_flexspi_nor_config.c @@ -7,7 +7,7 @@ #include "evkmimxrt1015_flexspi_nor_config.h" -#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) __attribute__((section(".boot_hdr.conf"), used)) const flexspi_nor_config_t qspi_flash_config = { @@ -65,4 +65,4 @@ const flexspi_nor_config_t qspi_flash_config = { .is_uniform_block_size = false, }; -#endif /* XIP_BOOT_HEADER_ENABLE */ +#endif /* defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) */ diff --git a/boards/nxp/mimxrt1015_evk/xip/evkmimxrt1015_flexspi_nor_config.h b/boards/nxp/mimxrt1015_evk/xip/evkmimxrt1015_flexspi_nor_config.h index 80c383d33b58..5c305246f943 100644 --- a/boards/nxp/mimxrt1015_evk/xip/evkmimxrt1015_flexspi_nor_config.h +++ b/boards/nxp/mimxrt1015_evk/xip/evkmimxrt1015_flexspi_nor_config.h @@ -111,7 +111,7 @@ enum { FLEXSPI_MISC_OFFSET_SAFE_CONFIG_FREQ_ENABLE = 4, /* Bit for Pad setting override enable */ FLEXSPI_MISC_OFFSET_PAD_SETTING_OVERRIDE_ENABLE = 5, - /* Bit for DDR clock confiuration indication. */ + /* Bit for DDR clock configuration indication. */ FLEXSPI_MISC_OFFSET_DDR_MODE_ENABLE = 6, }; @@ -237,7 +237,7 @@ typedef struct flexspi_config { * 8 - Octal */ uint8_t sflash_pad_type; - /* [0x046-0x046] Serial Flash Frequencey, device specific + /* [0x046-0x046] Serial Flash Frequency, device specific * definitions, See System Boot Chapter for more details */ uint8_t serial_clk_freq; @@ -351,7 +351,7 @@ typedef struct _flexspi_nor_config { uint8_t need_exit_nocmd_mode; /* Half the Serial Clock for non-read command: true/false */ uint8_t half_clk_for_non_read_cmd; - /* Need to Restore NoCmd mode after IP commmand execution */ + /* Need to Restore NoCmd mode after IP command execution */ uint8_t need_restore_nocmd_mode; /* Block size */ uint32_t block_size; diff --git a/boards/nxp/mimxrt1020_evk/CMakeLists.txt b/boards/nxp/mimxrt1020_evk/CMakeLists.txt index 1ae0fae86e2d..fc7a8481d7c1 100644 --- a/boards/nxp/mimxrt1020_evk/CMakeLists.txt +++ b/boards/nxp/mimxrt1020_evk/CMakeLists.txt @@ -16,15 +16,12 @@ if(CONFIG_NXP_IMXRT_BOOT_HEADER) # This flash configuration block may need modification if another # flash chip is used on your custom board. See NXP AN12238 for more # information. - zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) - zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) zephyr_library_sources(xip/evkmimxrt1020_flexspi_nor_config.c) zephyr_library_include_directories(xip) endif() if(CONFIG_DEVICE_CONFIGURATION_DATA) # This device configuration block may need modification if another # SDRAM chip is used on your custom board. - zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) zephyr_library_sources(dcd/dcd.c) else() if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000) diff --git a/boards/nxp/mimxrt1020_evk/dcd/dcd.c b/boards/nxp/mimxrt1020_evk/dcd/dcd.c index 3b679f893d1a..87913fa6a878 100644 --- a/boards/nxp/mimxrt1020_evk/dcd/dcd.c +++ b/boards/nxp/mimxrt1020_evk/dcd/dcd.c @@ -7,8 +7,8 @@ #include "dcd.h" -#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) -#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) +#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) +#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_DEVICE_CONFIGURATION_DATA) __attribute__((section(".boot_hdr.dcd_data"), used)) const uint8_t dcd_data[] = { @@ -591,5 +591,5 @@ const uint8_t dcd_data[] = { #else const uint8_t dcd_data[] = {0x00}; -#endif /* XIP_BOOT_HEADER_DCD_ENABLE */ -#endif /* XIP_BOOT_HEADER_ENABLE */ +#endif /* defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_DEVICE_CONFIGURATION_DATA) */ +#endif /* defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) */ diff --git a/boards/nxp/mimxrt1020_evk/mimxrt1020_evk.dts b/boards/nxp/mimxrt1020_evk/mimxrt1020_evk.dts index 23f61740ce64..bd66fe122de3 100644 --- a/boards/nxp/mimxrt1020_evk/mimxrt1020_evk.dts +++ b/boards/nxp/mimxrt1020_evk/mimxrt1020_evk.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "mimxrt1020_evk-pinctrl.dtsi" #include #include @@ -160,7 +160,7 @@ arduino_serial: &lpuart2 { compatible = "microchip,ksz8081"; reg = <0>; status = "okay"; - reset-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; int-gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; microchip,interface-type = "rmii"; }; diff --git a/boards/nxp/mimxrt1020_evk/xip/evkmimxrt1020_flexspi_nor_config.c b/boards/nxp/mimxrt1020_evk/xip/evkmimxrt1020_flexspi_nor_config.c index fc93d11de5f3..8d9fb1dc8c7e 100644 --- a/boards/nxp/mimxrt1020_evk/xip/evkmimxrt1020_flexspi_nor_config.c +++ b/boards/nxp/mimxrt1020_evk/xip/evkmimxrt1020_flexspi_nor_config.c @@ -7,7 +7,7 @@ #include "evkmimxrt1020_flexspi_nor_config.h" -#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) __attribute__((section(".boot_hdr.conf"), used)) #define FLASH_DUMMY_CYCLES 0x08 @@ -85,4 +85,4 @@ const flexspi_nor_config_t qspi_flash_config = { .is_uniform_block_size = false, }; -#endif /* XIP_BOOT_HEADER_ENABLE */ +#endif /* defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) */ diff --git a/boards/nxp/mimxrt1020_evk/xip/evkmimxrt1020_flexspi_nor_config.h b/boards/nxp/mimxrt1020_evk/xip/evkmimxrt1020_flexspi_nor_config.h index 56195bfb7495..54150ab8eafd 100644 --- a/boards/nxp/mimxrt1020_evk/xip/evkmimxrt1020_flexspi_nor_config.h +++ b/boards/nxp/mimxrt1020_evk/xip/evkmimxrt1020_flexspi_nor_config.h @@ -111,7 +111,7 @@ enum { FLEXSPI_MISC_OFFSET_SAFE_CONFIG_FREQ_ENABLE = 4, /* Bit for Pad setting override enable */ FLEXSPI_MISC_OFFSET_PAD_SETTING_OVERRIDE_ENABLE = 5, - /* Bit for DDR clock confiuration indication. */ + /* Bit for DDR clock configuration indication. */ FLEXSPI_MISC_OFFSET_DDR_MODE_ENABLE = 6, }; @@ -241,7 +241,7 @@ typedef struct flexspi_config { * 8 - Octal */ uint8_t sflash_pad_type; - /* [0x046-0x046] Serial Flash Frequencey, device specific + /* [0x046-0x046] Serial Flash Frequency, device specific * definitions, See System Boot Chapter for more details */ uint8_t serial_clk_freq; @@ -355,7 +355,7 @@ typedef struct _flexspi_nor_config { uint8_t need_exit_nocmd_mode; /* Half the Serial Clock for non-read command: true/false */ uint8_t half_clk_for_non_read_cmd; - /* Need to Restore NoCmd mode after IP commmand execution */ + /* Need to Restore NoCmd mode after IP command execution */ uint8_t need_restore_nocmd_mode; /* Block size */ uint32_t block_size; diff --git a/boards/nxp/mimxrt1024_evk/CMakeLists.txt b/boards/nxp/mimxrt1024_evk/CMakeLists.txt index 22d2fcdd8ae7..bbca78b36d8f 100644 --- a/boards/nxp/mimxrt1024_evk/CMakeLists.txt +++ b/boards/nxp/mimxrt1024_evk/CMakeLists.txt @@ -16,15 +16,12 @@ if(CONFIG_NXP_IMXRT_BOOT_HEADER) # This flash configuration block may need modification if another # flash chip is used on your custom board. See NXP AN12238 for more # information. - zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) - zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) zephyr_library_sources(xip/evkmimxrt1024_flexspi_nor_config.c) zephyr_library_include_directories(xip) endif() if(CONFIG_DEVICE_CONFIGURATION_DATA) # This device configuration block may need modification if another # SDRAM chip is used on your custom board. - zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) zephyr_library_sources(dcd/dcd.c) else() if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000) diff --git a/boards/nxp/mimxrt1024_evk/dcd/dcd.c b/boards/nxp/mimxrt1024_evk/dcd/dcd.c index e274fbdf84a7..3d42bdcf3ff7 100644 --- a/boards/nxp/mimxrt1024_evk/dcd/dcd.c +++ b/boards/nxp/mimxrt1024_evk/dcd/dcd.c @@ -7,8 +7,8 @@ #include "dcd.h" -#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) -#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) +#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) +#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_DEVICE_CONFIGURATION_DATA) __attribute__((section(".boot_hdr.dcd_data"), used)) const uint8_t dcd_data[] = { @@ -591,5 +591,5 @@ const uint8_t dcd_data[] = { #else const uint8_t dcd_data[] = {0x00}; -#endif /* XIP_BOOT_HEADER_DCD_ENABLE */ -#endif /* XIP_BOOT_HEADER_ENABLE */ +#endif /* defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_DEVICE_CONFIGURATION_DATA) */ +#endif /* defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) */ diff --git a/boards/nxp/mimxrt1024_evk/mimxrt1024_evk.dts b/boards/nxp/mimxrt1024_evk/mimxrt1024_evk.dts index 29a39b7f66f8..cfaafc4e59da 100644 --- a/boards/nxp/mimxrt1024_evk/mimxrt1024_evk.dts +++ b/boards/nxp/mimxrt1024_evk/mimxrt1024_evk.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "mimxrt1024_evk-pinctrl.dtsi" #include #include @@ -127,9 +127,9 @@ arduino_serial: &lpuart2 { reg = <0x00201000 DT_SIZE_K(1924)>; }; - storage_partition: partition@3E2000 { + storage_partition: partition@3e2000 { label = "storage"; - reg = <0x003E2000 DT_SIZE_K(120)>; + reg = <0x003e2000 DT_SIZE_K(120)>; }; }; }; @@ -152,7 +152,7 @@ arduino_serial: &lpuart2 { compatible = "microchip,ksz8081"; reg = <0>; status = "okay"; - reset-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; int-gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; microchip,interface-type = "rmii"; }; diff --git a/boards/nxp/mimxrt1024_evk/xip/evkmimxrt1024_flexspi_nor_config.c b/boards/nxp/mimxrt1024_evk/xip/evkmimxrt1024_flexspi_nor_config.c index cc9061961842..fb507f74a42a 100644 --- a/boards/nxp/mimxrt1024_evk/xip/evkmimxrt1024_flexspi_nor_config.c +++ b/boards/nxp/mimxrt1024_evk/xip/evkmimxrt1024_flexspi_nor_config.c @@ -7,7 +7,7 @@ #include "evkmimxrt1024_flexspi_nor_config.h" -#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) __attribute__((section(".boot_hdr.conf"), used)) const flexspi_nor_config_t qspi_flash_config = { @@ -65,4 +65,4 @@ const flexspi_nor_config_t qspi_flash_config = { .is_uniform_block_size = false, }; -#endif /* XIP_BOOT_HEADER_ENABLE */ +#endif /* defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) */ diff --git a/boards/nxp/mimxrt1024_evk/xip/evkmimxrt1024_flexspi_nor_config.h b/boards/nxp/mimxrt1024_evk/xip/evkmimxrt1024_flexspi_nor_config.h index 870c6fc7fdc6..e358bf6d87c2 100644 --- a/boards/nxp/mimxrt1024_evk/xip/evkmimxrt1024_flexspi_nor_config.h +++ b/boards/nxp/mimxrt1024_evk/xip/evkmimxrt1024_flexspi_nor_config.h @@ -111,7 +111,7 @@ enum { FLEXSPI_MISC_OFFSET_SAFE_CONFIG_FREQ_ENABLE = 4, /* Bit for Pad setting override enable */ FLEXSPI_MISC_OFFSET_PAD_SETTING_OVERRIDE_ENABLE = 5, - /* Bit for DDR clock confiuration indication. */ + /* Bit for DDR clock configuration indication. */ FLEXSPI_MISC_OFFSET_DDR_MODE_ENABLE = 6, }; @@ -237,7 +237,7 @@ typedef struct flexspi_config { * 8 - Octal */ uint8_t sflash_pad_type; - /* [0x046-0x046] Serial Flash Frequencey, device specific + /* [0x046-0x046] Serial Flash Frequency, device specific * definitions, See System Boot Chapter for more details */ uint8_t serial_clk_freq; @@ -351,7 +351,7 @@ typedef struct _flexspi_nor_config { uint8_t need_exit_nocmd_mode; /* Half the Serial Clock for non-read command: true/false */ uint8_t half_clk_for_non_read_cmd; - /* Need to Restore NoCmd mode after IP commmand execution */ + /* Need to Restore NoCmd mode after IP command execution */ uint8_t need_restore_nocmd_mode; /* Block size */ uint32_t block_size; diff --git a/boards/nxp/mimxrt1040_evk/CMakeLists.txt b/boards/nxp/mimxrt1040_evk/CMakeLists.txt index deea9bbcc9d9..776655ecdea1 100644 --- a/boards/nxp/mimxrt1040_evk/CMakeLists.txt +++ b/boards/nxp/mimxrt1040_evk/CMakeLists.txt @@ -21,15 +21,12 @@ if(CONFIG_NXP_IMXRT_BOOT_HEADER) # This flash configuration block may need modification if another # flash chip is used on your custom board. See NXP AN12238 for more # information. - zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) - zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) zephyr_library_sources(xip/evkmimxrt1040_flexspi_nor_config.c) zephyr_library_include_directories(xip) endif() if(CONFIG_DEVICE_CONFIGURATION_DATA) # This device configuration block may need modification if another # SDRAM chip is used on your custom board. - zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) zephyr_library_sources(dcd/dcd.c) else() if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000) diff --git a/boards/nxp/mimxrt1040_evk/Kconfig.defconfig b/boards/nxp/mimxrt1040_evk/Kconfig.defconfig index 87cdb61799a5..f53272558695 100644 --- a/boards/nxp/mimxrt1040_evk/Kconfig.defconfig +++ b/boards/nxp/mimxrt1040_evk/Kconfig.defconfig @@ -9,4 +9,7 @@ config DEVICE_CONFIGURATION_DATA config NXP_IMX_EXTERNAL_SDRAM default y +configdefault NET_L2_ETHERNET + default y if DT_HAS_NXP_ENET_ENABLED + endif # BOARD_MIMXRT1040_EVK diff --git a/boards/nxp/mimxrt1040_evk/dcd/dcd.c b/boards/nxp/mimxrt1040_evk/dcd/dcd.c index a58f89a75235..685a155c30b7 100644 --- a/boards/nxp/mimxrt1040_evk/dcd/dcd.c +++ b/boards/nxp/mimxrt1040_evk/dcd/dcd.c @@ -7,8 +7,8 @@ #include "dcd.h" -#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) -#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) +#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) +#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_DEVICE_CONFIGURATION_DATA) __attribute__((section(".boot_hdr.dcd_data"), used)) const uint8_t dcd_data[] = { @@ -615,5 +615,5 @@ const uint8_t dcd_data[] = { #else const uint8_t dcd_data[] = {0x00}; -#endif /* XIP_BOOT_HEADER_DCD_ENABLE */ -#endif /* XIP_BOOT_HEADER_ENABLE */ +#endif /* defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_DEVICE_CONFIGURATION_DATA) */ +#endif /* defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) */ diff --git a/boards/nxp/mimxrt1040_evk/doc/index.rst b/boards/nxp/mimxrt1040_evk/doc/index.rst index 2ca8ae4b04e5..11d70e024bef 100644 --- a/boards/nxp/mimxrt1040_evk/doc/index.rst +++ b/boards/nxp/mimxrt1040_evk/doc/index.rst @@ -92,6 +92,25 @@ Supported Features Zephyr. Therefore, the mimxrt1064_evk board may have additional features already supported, which can also be re-used on this mimxrt1040_evk board. +Shields for Supported Features +============================== + +Some features in the table above are tested with Zephyr shields. These shields +are tested on this board: + +- :ref:`rk043fn02h_ct` and :ref:`rk043fn66hs_ctg` - support the Display interface. +- :ref:`nxp_m2_wifi_bt` - Rev C version is tested with this shield to attach any M.2 module + with BT HCI UART interface and Wi-Fi SDIO interface. The shield binds the required NXP + HCI driver or SDIO driver to perform firmware-load and other setup configurations + for NXP SoC IW416/IW612/IW610. + +For the :ref:`nxp_m2_wifi_bt` shield, the following hardware rework needs to be applied, + +- Solder 0 ohm resistors for R96, and R93. +- Remove resistors from R497, R498, R456 and R457. + +And due to pin conflict issue, the PCM interface of Bluetooth module cannot be supported. + Connections and IOs =================== @@ -292,12 +311,6 @@ steps: Bluetooth Module ---------------- -For the :ref:`nxp_m2_wifi_bt` shield, the following hardware rework needs to be applied, -Solder 0 ohm resistors for R96, and R93. -Remove resistors from R497, R498, R456 and R457. - -And due to pin conflict issue, the PCM interface of Bluetooth module cannot be supported. - For the debugger fails to connect with the following error, please refer to the next section. WiFi Module diff --git a/boards/nxp/mimxrt1040_evk/mimxrt1040_evk-pinctrl.dtsi b/boards/nxp/mimxrt1040_evk/mimxrt1040_evk-pinctrl.dtsi index ef34bea94090..aec855de37e3 100644 --- a/boards/nxp/mimxrt1040_evk/mimxrt1040_evk-pinctrl.dtsi +++ b/boards/nxp/mimxrt1040_evk/mimxrt1040_evk-pinctrl.dtsi @@ -20,6 +20,55 @@ }; }; + pinmux_enet: pinmux_enet { + group0 { + pinmux = <&iomuxc_gpio_b1_10_enet_ref_clk>; + bias-disable; + drive-strength = "r0-6"; + slew-rate = "fast"; + nxp,speed = "50-mhz"; + input-enable; + }; + + group1 { + pinmux = <&iomuxc_gpio_b1_04_enet_rx_data0>, + <&iomuxc_gpio_b1_05_enet_rx_data1>, + <&iomuxc_gpio_b1_06_enet_rx_en>, + <&iomuxc_gpio_b1_07_enet_tx_data0>, + <&iomuxc_gpio_b1_08_enet_tx_data1>, + <&iomuxc_gpio_b1_09_enet_tx_en>, + <&iomuxc_gpio_b1_11_enet_rx_er>; + drive-strength = "r0-5"; + bias-pull-up; + bias-pull-up-value = "100k"; + slew-rate = "fast"; + nxp,speed = "200-mhz"; + }; + }; + + pinmux_enet_mdio: pinmux_enet_mdio { + group0 { + pinmux = <&iomuxc_gpio_emc_40_enet_mdc>, + <&iomuxc_gpio_emc_41_enet_mdio>, + <&iomuxc_gpio_sd_b1_04_gpio3_io04>; + drive-strength = "r0-5"; + bias-pull-up; + bias-pull-up-value = "100k"; + slew-rate = "fast"; + nxp,speed = "200-mhz"; + }; + }; + + pinmux_ptp: pinmux_ptp { + group0 { + pinmux = <&iomuxc_gpio_ad_b1_02_enet_1588_event2_out>, + <&iomuxc_gpio_ad_b1_03_enet_1588_event2_in>; + drive-strength = "r0-6"; + slew-rate = "slow"; + nxp,speed = "100-mhz"; + }; + }; + /* Route PWM1 A3 to J16, pin 6 on arduino header */ pinmux_flexpwm1_pwm3: pinmux_flexpwm1_pwm3 { group0 { diff --git a/boards/nxp/mimxrt1040_evk/mimxrt1040_evk.dts b/boards/nxp/mimxrt1040_evk/mimxrt1040_evk.dts index 78b8ca72c24e..a5cb3b62a6b0 100644 --- a/boards/nxp/mimxrt1040_evk/mimxrt1040_evk.dts +++ b/boards/nxp/mimxrt1040_evk/mimxrt1040_evk.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "mimxrt1040_evk-pinctrl.dtsi" #include #include @@ -173,6 +173,35 @@ pinctrl-names = "default", "sleep"; }; +&enet_mac { + status = "okay"; + pinctrl-0 = <&pinmux_enet>; + pinctrl-names = "default"; + phy-handle = <&phy>; + zephyr,random-mac-address; + phy-connection-type = "rmii"; +}; + +&enet_mdio { + status = "okay"; + pinctrl-0 = <&pinmux_enet_mdio>; + pinctrl-names = "default"; + + phy: phy@0 { + compatible = "microchip,ksz8081"; + reg = <0>; + status = "okay"; + reset-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; + microchip,interface-type = "rmii"; + }; +}; + +&enet_ptp_clock { + status = "okay"; + pinctrl-0 = <&pinmux_ptp>; + pinctrl-names = "default"; +}; + &flexpwm1_pwm3 { status = "okay"; pinctrl-0 = <&pinmux_flexpwm1_pwm3>; diff --git a/boards/nxp/mimxrt1040_evk/mimxrt1040_evk.yaml b/boards/nxp/mimxrt1040_evk/mimxrt1040_evk.yaml index de7742a9c13c..1af828c609fb 100644 --- a/boards/nxp/mimxrt1040_evk/mimxrt1040_evk.yaml +++ b/boards/nxp/mimxrt1040_evk/mimxrt1040_evk.yaml @@ -20,6 +20,7 @@ supported: - flash - gpio - i2c + - netif:eth - pwm - spi - rtc diff --git a/boards/nxp/mimxrt1040_evk/xip/evkmimxrt1040_flexspi_nor_config.c b/boards/nxp/mimxrt1040_evk/xip/evkmimxrt1040_flexspi_nor_config.c index d18458aed615..d3d0fb1ff896 100644 --- a/boards/nxp/mimxrt1040_evk/xip/evkmimxrt1040_flexspi_nor_config.c +++ b/boards/nxp/mimxrt1040_evk/xip/evkmimxrt1040_flexspi_nor_config.c @@ -7,7 +7,7 @@ #include "evkmimxrt1040_flexspi_nor_config.h" -#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) __attribute__((section(".boot_hdr.conf"), used)) const flexspi_nor_config_t qspi_flash_config = { @@ -60,4 +60,4 @@ const flexspi_nor_config_t qspi_flash_config = { .is_uniform_block_size = false, }; -#endif /* XIP_BOOT_HEADER_ENABLE */ +#endif /* defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) */ diff --git a/boards/nxp/mimxrt1040_evk/xip/evkmimxrt1040_flexspi_nor_config.h b/boards/nxp/mimxrt1040_evk/xip/evkmimxrt1040_flexspi_nor_config.h index 7dd4084f24a8..b9105c13ef74 100644 --- a/boards/nxp/mimxrt1040_evk/xip/evkmimxrt1040_flexspi_nor_config.h +++ b/boards/nxp/mimxrt1040_evk/xip/evkmimxrt1040_flexspi_nor_config.h @@ -113,7 +113,7 @@ enum { FLEXSPI_MISC_OFFSET_SAFE_CONFIG_FREQ_ENABLE = 4, /* Bit for Pad setting override enable */ FLEXSPI_MISC_OFFSET_PAD_SETTING_OVERRIDE_ENABLE = 5, - /* Bit for DDR clock confiuration indication. */ + /* Bit for DDR clock configuration indication. */ FLEXSPI_MISC_OFFSET_DDR_MODE_ENABLE = 6, }; @@ -239,7 +239,7 @@ typedef struct flexspi_config { * 8 - Octal */ uint8_t sflash_pad_type; - /* [0x046-0x046] Serial Flash Frequencey, device specific + /* [0x046-0x046] Serial Flash Frequency, device specific * definitions, See System Boot Chapter for more details */ uint8_t serial_clk_freq; @@ -353,7 +353,7 @@ typedef struct _flexspi_nor_config { uint8_t need_exit_nocmd_mode; /* Half the Serial Clock for non-read command: true/false */ uint8_t half_clk_for_non_read_cmd; - /* Need to Restore NoCmd mode after IP commmand execution */ + /* Need to Restore NoCmd mode after IP command execution */ uint8_t need_restore_nocmd_mode; /* Block size */ uint32_t block_size; diff --git a/boards/nxp/mimxrt1050_evk/CMakeLists.txt b/boards/nxp/mimxrt1050_evk/CMakeLists.txt index 3efb8f6f72e8..e1d74f9e584e 100644 --- a/boards/nxp/mimxrt1050_evk/CMakeLists.txt +++ b/boards/nxp/mimxrt1050_evk/CMakeLists.txt @@ -27,15 +27,12 @@ if(CONFIG_NXP_IMXRT_BOOT_HEADER) # This flash configuration block may need modification if another # flash chip is used on your custom board. See NXP AN12238 for more # information. - zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) - zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) zephyr_library_sources(xip/${FLASH_CONF}) zephyr_library_include_directories(xip) endif() if(CONFIG_DEVICE_CONFIGURATION_DATA) # This device configuration block may need modification if another # SDRAM chip is used on your custom board. - zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) zephyr_library_sources(dcd/dcd.c) else() if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000) diff --git a/boards/nxp/mimxrt1050_evk/dcd/dcd.c b/boards/nxp/mimxrt1050_evk/dcd/dcd.c index 181fa387fb0f..65b10524db08 100644 --- a/boards/nxp/mimxrt1050_evk/dcd/dcd.c +++ b/boards/nxp/mimxrt1050_evk/dcd/dcd.c @@ -7,8 +7,8 @@ #include "dcd.h" -#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) -#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) +#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) +#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_DEVICE_CONFIGURATION_DATA) __attribute__((section(".boot_hdr.dcd_data"), used)) const uint8_t dcd_data[] = { @@ -615,5 +615,5 @@ const uint8_t dcd_data[] = { #else const uint8_t dcd_data[] = {0x00}; -#endif /* XIP_BOOT_HEADER_DCD_ENABLE */ -#endif /* XIP_BOOT_HEADER_ENABLE */ +#endif /* defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_DEVICE_CONFIGURATION_DATA) */ +#endif /* defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) */ diff --git a/boards/nxp/mimxrt1050_evk/doc/index.rst b/boards/nxp/mimxrt1050_evk/doc/index.rst index d949bc2f6b6f..e026ba3f6e16 100644 --- a/boards/nxp/mimxrt1050_evk/doc/index.rst +++ b/boards/nxp/mimxrt1050_evk/doc/index.rst @@ -105,6 +105,16 @@ Supported Features Zephyr. Therefore, the mimxrt1064_evk board may have additional features already supported, which can also be re-used on this mimxrt1050_evk board. +Shields for Supported Features +============================== + +Some features in the table above are tested with Zephyr shields. These shields +are tested on this board: + +- :ref:`rk043fn02h_ct` and :ref:`rk043fn66hs_ctg` - support the Display interface. +- :ref:`dvp_fpc24_mt9m114` - supports the CSI video/camera interface. + + Connections and IOs =================== diff --git a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk.dtsi b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk.dtsi index 499d43d1fb41..e7fa4345541e 100644 --- a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk.dtsi +++ b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk.dtsi @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "mimxrt1050_evk-pinctrl.dtsi" #include #include @@ -200,7 +200,7 @@ zephyr_lcdif: &lcdif { compatible = "microchip,ksz8081"; reg = <0>; status = "okay"; - reset-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; int-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; microchip,interface-type = "rmii"; }; diff --git a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.yaml b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.yaml index e05c61c13acc..752e98b34d60 100644 --- a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.yaml +++ b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.yaml @@ -5,7 +5,7 @@ # identifier: mimxrt1050_evk/mimxrt1052/qspi -name: NXP MIMXRT1050-EVK-QSPI +name: NXP MIMXRT1050-EVK (QSPI) type: mcu arch: arm toolchain: diff --git a/boards/nxp/mimxrt1050_evk/xip/evkbimxrt1050_flexspi_nor_config.c b/boards/nxp/mimxrt1050_evk/xip/evkbimxrt1050_flexspi_nor_config.c index 07452d6ea3bf..071d25ab50b8 100644 --- a/boards/nxp/mimxrt1050_evk/xip/evkbimxrt1050_flexspi_nor_config.c +++ b/boards/nxp/mimxrt1050_evk/xip/evkbimxrt1050_flexspi_nor_config.c @@ -7,7 +7,7 @@ #include "evkbimxrt1050_flexspi_nor_config.h" -#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) __attribute__((section(".boot_hdr.conf"), used)) const flexspi_nor_config_t hyperflash_config = { @@ -224,4 +224,4 @@ const flexspi_nor_config_t hyperflash_config = { .is_uniform_block_size = true, }; -#endif /* XIP_BOOT_HEADER_ENABLE */ +#endif /* defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) */ diff --git a/boards/nxp/mimxrt1050_evk/xip/evkbimxrt1050_flexspi_nor_config.h b/boards/nxp/mimxrt1050_evk/xip/evkbimxrt1050_flexspi_nor_config.h index 013e4f0852a5..6ee8b2085ccc 100644 --- a/boards/nxp/mimxrt1050_evk/xip/evkbimxrt1050_flexspi_nor_config.h +++ b/boards/nxp/mimxrt1050_evk/xip/evkbimxrt1050_flexspi_nor_config.h @@ -112,7 +112,7 @@ enum { FLEXSPI_MISC_OFFSET_SAFE_CONFIG_FREQ_ENABLE = 4, /* Bit for Pad setting override enable */ FLEXSPI_MISC_OFFSET_PAD_SETTING_OVERRIDE_ENABLE = 5, - /* Bit for DDR clock confiuration indication. */ + /* Bit for DDR clock configuration indication. */ FLEXSPI_MISC_OFFSET_DDR_MODE_ENABLE = 6, }; @@ -238,7 +238,7 @@ typedef struct flexspi_config { * 8 - Octal */ uint8_t sflash_pad_type; - /* [0x046-0x046] Serial Flash Frequencey, device specific + /* [0x046-0x046] Serial Flash Frequency, device specific * definitions, See System Boot Chapter for more details */ uint8_t serial_clk_freq; @@ -352,7 +352,7 @@ typedef struct _flexspi_nor_config { uint8_t need_exit_nocmd_mode; /* Half the Serial Clock for non-read command: true/false */ uint8_t half_clk_for_non_read_cmd; - /* Need to Restore NoCmd mode after IP commmand execution */ + /* Need to Restore NoCmd mode after IP command execution */ uint8_t need_restore_nocmd_mode; /* Block size */ uint32_t block_size; diff --git a/boards/nxp/mimxrt1050_evk/xip/evkbimxrt1050_flexspi_nor_qspi_config.c b/boards/nxp/mimxrt1050_evk/xip/evkbimxrt1050_flexspi_nor_qspi_config.c index a6ffc8774910..750e4e127226 100644 --- a/boards/nxp/mimxrt1050_evk/xip/evkbimxrt1050_flexspi_nor_qspi_config.c +++ b/boards/nxp/mimxrt1050_evk/xip/evkbimxrt1050_flexspi_nor_qspi_config.c @@ -7,7 +7,7 @@ #include "evkbimxrt1050_flexspi_nor_config.h" -#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) __attribute__((section(".boot_hdr.conf"), used)) const flexspi_nor_config_t qspi_flash_config = { @@ -34,4 +34,4 @@ const flexspi_nor_config_t qspi_flash_config = { .block_size = 64u * 1024u, .is_uniform_block_size = false, }; -#endif /* XIP_BOOT_HEADER_ENABLE */ +#endif /* defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) */ diff --git a/boards/nxp/mimxrt1060_evk/CMakeLists.txt b/boards/nxp/mimxrt1060_evk/CMakeLists.txt index 4d293e42d6e9..b8b001960bcb 100644 --- a/boards/nxp/mimxrt1060_evk/CMakeLists.txt +++ b/boards/nxp/mimxrt1060_evk/CMakeLists.txt @@ -37,15 +37,12 @@ if(CONFIG_NXP_IMXRT_BOOT_HEADER) # This flash configuration block may need modification if another # flash chip is used on your custom board. See NXP AN12238 for more # information. - zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) - zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) zephyr_library_sources(${RT1060_BOARD_DIR}/xip/${FLASH_CONF}) zephyr_library_include_directories(${RT1060_BOARD_DIR}/xip) endif() if(CONFIG_DEVICE_CONFIGURATION_DATA) # This device configuration data block may need modification if another # SDRAM chip is used on your custom board. - zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) zephyr_library_sources(${RT1060_BOARD_DIR}/dcd/dcd.c) else() if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000) diff --git a/boards/nxp/mimxrt1060_evk/dcd/dcd.c b/boards/nxp/mimxrt1060_evk/dcd/dcd.c index f76c1e1d16ce..c6271de1a848 100644 --- a/boards/nxp/mimxrt1060_evk/dcd/dcd.c +++ b/boards/nxp/mimxrt1060_evk/dcd/dcd.c @@ -7,8 +7,8 @@ #include "dcd.h" -#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) -#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) +#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) +#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_DEVICE_CONFIGURATION_DATA) __attribute__((section(".boot_hdr.dcd_data"), used)) const uint8_t dcd_data[] = { @@ -615,5 +615,5 @@ const uint8_t dcd_data[] = { #else const uint8_t dcd_data[] = {0x00}; -#endif /* XIP_BOOT_HEADER_DCD_ENABLE */ -#endif /* XIP_BOOT_HEADER_ENABLE */ +#endif /* defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_DEVICE_CONFIGURATION_DATA) */ +#endif /* defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) */ diff --git a/boards/nxp/mimxrt1060_evk/doc/index.rst b/boards/nxp/mimxrt1060_evk/doc/index.rst index 51ea8409db69..1b598cd4d456 100644 --- a/boards/nxp/mimxrt1060_evk/doc/index.rst +++ b/boards/nxp/mimxrt1060_evk/doc/index.rst @@ -105,6 +105,19 @@ Supported Features Zephyr. Therefore, the mimxrt1064_evk board may have additional features already supported, which can also be re-used on this mimxrt1060_evk board. +Shields for Supported Features +============================== + +Some features in the table above are tested with Zephyr shields. These shields +are tested on this board: + +- :ref:`nxp_m2_wifi_bt` - Rev C version is tested with this shield to attach any M.2 module + with BT HCI UART interface and Wi-Fi SDIO interface. The shield binds the required NXP + HCI driver or SDIO driver to perform firmware-load and other setup configurations + for NXP SoC IW416/IW612/IW610. +- :ref:`rk043fn02h_ct` and :ref:`rk043fn66hs_ctg` - support the Display interface. +- :ref:`dvp_fpc24_mt9m114` - supports the CSI video/camera interface. + Connections and I/Os ==================== @@ -446,14 +459,6 @@ should see the following message in the terminal: ***** Booting Zephyr OS v1.14.0-rc1 ***** Hello World! mimxrt1060_evk//qspi -Shield for M.2 Wi-Fi and BT Interface -===================================== - -Rev C version is tested with :ref:`nxp_m2_wifi_bt` shield to attach any M.2 module -with BT HCI UART interface and Wi-Fi SDIO interface. The shield binds the required NXP -HCI driver or SDIO driver to perform firmware-load and other setup configurations -for NXP SoC IW416/IW612/IW610. - Troubleshooting =============== diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk.dtsi b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk.dtsi index 087cff325fbc..16fd8e5b7b38 100644 --- a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk.dtsi +++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk.dtsi @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "mimxrt1060_evk-pinctrl.dtsi" #include #include @@ -178,7 +178,7 @@ arduino_i2c: &lpi2c1 { compatible = "microchip,ksz8081"; reg = <0>; status = "okay"; - reset-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; int-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; microchip,interface-type = "rmii"; }; diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.yaml b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.yaml index acf3d6016ff3..e87daa765bda 100644 --- a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.yaml +++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.yaml @@ -5,7 +5,7 @@ # identifier: mimxrt1060_evk/mimxrt1062/hyperflash -name: NXP MIMXRT1060-EVK-HYPERFLASH +name: NXP MIMXRT1060-EVK (HyperFlash) type: mcu arch: arm toolchain: diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi_C.overlay b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi_C.overlay index 63862a724c02..c4d2f4a4ba1f 100644 --- a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi_C.overlay +++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi_C.overlay @@ -40,7 +40,7 @@ audio_codec: wm8962@1a { compatible = "wolfson,wm8962"; reg = <0x1a>; - clocks = <&ccm IMX_CCM_SAI1_CLK 0x7C 18>; + clocks = <&ccm IMX_CCM_SAI1_CLK 0x7c 18>; clock-names = "mclk"; }; }; @@ -86,9 +86,9 @@ reg = <0x00720000 DT_SIZE_M(7)>; }; - storage_partition: partition@E20000 { + storage_partition: partition@e20000 { label = "storage"; - reg = <0x00E20000 (DT_SIZE_M(2) - DT_SIZE_K(128))>; + reg = <0x00e20000 (DT_SIZE_M(2) - DT_SIZE_K(128))>; }; }; }; diff --git a/boards/nxp/mimxrt1060_evk/xip/evkbmimxrt1060_flexspi_nor_config.c b/boards/nxp/mimxrt1060_evk/xip/evkbmimxrt1060_flexspi_nor_config.c index 26fecbb51aac..bef955817996 100644 --- a/boards/nxp/mimxrt1060_evk/xip/evkbmimxrt1060_flexspi_nor_config.c +++ b/boards/nxp/mimxrt1060_evk/xip/evkbmimxrt1060_flexspi_nor_config.c @@ -7,7 +7,7 @@ #include "evkbmimxrt1060_flexspi_nor_config.h" -#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) __attribute__((section(".boot_hdr.conf"), used)) const flexspi_nor_config_t qspi_flash_config = { @@ -65,4 +65,4 @@ const flexspi_nor_config_t qspi_flash_config = { .is_uniform_block_size = false, }; -#endif /* XIP_BOOT_HEADER_ENABLE */ +#endif /* defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) */ diff --git a/boards/nxp/mimxrt1060_evk/xip/evkbmimxrt1060_flexspi_nor_config.h b/boards/nxp/mimxrt1060_evk/xip/evkbmimxrt1060_flexspi_nor_config.h index fb5149c7d929..0b31a4510145 100644 --- a/boards/nxp/mimxrt1060_evk/xip/evkbmimxrt1060_flexspi_nor_config.h +++ b/boards/nxp/mimxrt1060_evk/xip/evkbmimxrt1060_flexspi_nor_config.h @@ -113,7 +113,7 @@ enum { FLEXSPI_MISC_OFFSET_SAFE_CONFIG_FREQ_ENABLE = 4, /* Bit for Pad setting override enable */ FLEXSPI_MISC_OFFSET_PAD_SETTING_OVERRIDE_ENABLE = 5, - /* Bit for DDR clock confiuration indication. */ + /* Bit for DDR clock configuration indication. */ FLEXSPI_MISC_OFFSET_DDR_MODE_ENABLE = 6, }; @@ -239,7 +239,7 @@ typedef struct flexspi_config { * 8 - Octal */ uint8_t sflash_pad_type; - /* [0x046-0x046] Serial Flash Frequencey, device specific + /* [0x046-0x046] Serial Flash Frequency, device specific * definitions, See System Boot Chapter for more details */ uint8_t serial_clk_freq; @@ -353,7 +353,7 @@ typedef struct _flexspi_nor_config { uint8_t need_exit_nocmd_mode; /* Half the Serial Clock for non-read command: true/false */ uint8_t half_clk_for_non_read_cmd; - /* Need to Restore NoCmd mode after IP commmand execution */ + /* Need to Restore NoCmd mode after IP command execution */ uint8_t need_restore_nocmd_mode; /* Block size */ uint32_t block_size; diff --git a/boards/nxp/mimxrt1060_evk/xip/evkmimxrt1060_flexspi_nor_config.c b/boards/nxp/mimxrt1060_evk/xip/evkmimxrt1060_flexspi_nor_config.c index 2aa0a43fbfc6..fe61574d79cf 100644 --- a/boards/nxp/mimxrt1060_evk/xip/evkmimxrt1060_flexspi_nor_config.c +++ b/boards/nxp/mimxrt1060_evk/xip/evkmimxrt1060_flexspi_nor_config.c @@ -7,7 +7,7 @@ #include "evkmimxrt1060_flexspi_nor_config.h" -#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) __attribute__((section(".boot_hdr.conf"), used)) const flexspi_nor_config_t qspi_flash_config = { @@ -65,4 +65,4 @@ const flexspi_nor_config_t qspi_flash_config = { .is_uniform_block_size = false, }; -#endif /* XIP_BOOT_HEADER_ENABLE */ +#endif /* defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) */ diff --git a/boards/nxp/mimxrt1060_evk/xip/evkmimxrt1060_flexspi_nor_config.h b/boards/nxp/mimxrt1060_evk/xip/evkmimxrt1060_flexspi_nor_config.h index 34f571df7f14..688eef989981 100644 --- a/boards/nxp/mimxrt1060_evk/xip/evkmimxrt1060_flexspi_nor_config.h +++ b/boards/nxp/mimxrt1060_evk/xip/evkmimxrt1060_flexspi_nor_config.h @@ -113,7 +113,7 @@ enum { FLEXSPI_MISC_OFFSET_SAFE_CONFIG_FREQ_ENABLE = 4, /* Bit for Pad setting override enable */ FLEXSPI_MISC_OFFSET_PAD_SETTING_OVERRIDE_ENABLE = 5, - /* Bit for DDR clock confiuration indication. */ + /* Bit for DDR clock configuration indication. */ FLEXSPI_MISC_OFFSET_DDR_MODE_ENABLE = 6, }; @@ -239,7 +239,7 @@ typedef struct flexspi_config { * 8 - Octal */ uint8_t sflash_pad_type; - /* [0x046-0x046] Serial Flash Frequencey, device specific + /* [0x046-0x046] Serial Flash Frequency, device specific * definitions, See System Boot Chapter for more details */ uint8_t serial_clk_freq; @@ -353,7 +353,7 @@ typedef struct _flexspi_nor_config { uint8_t need_exit_nocmd_mode; /* Half the Serial Clock for non-read command: true/false */ uint8_t half_clk_for_non_read_cmd; - /* Need to Restore NoCmd mode after IP commmand execution */ + /* Need to Restore NoCmd mode after IP command execution */ uint8_t need_restore_nocmd_mode; /* Block size */ uint32_t block_size; diff --git a/boards/nxp/mimxrt1062_fmurt6/CMakeLists.txt b/boards/nxp/mimxrt1062_fmurt6/CMakeLists.txt index 2d0bfaecab48..53801bc95061 100644 --- a/boards/nxp/mimxrt1062_fmurt6/CMakeLists.txt +++ b/boards/nxp/mimxrt1062_fmurt6/CMakeLists.txt @@ -18,8 +18,6 @@ if(CONFIG_NXP_IMXRT_BOOT_HEADER) # Include flash configuration block for RT1050 EVK from NXP's HAL. # This configuration block may need modification if another flash chip is # used on your custom board. See NXP AN12238 for more information. - zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) - zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) zephyr_library_sources(${RT1062_BOARD_DIR}/xip/${FLASH_CONF}) zephyr_library_include_directories(${RT1062_BOARD_DIR}/xip) endif() @@ -27,7 +25,6 @@ if(CONFIG_NXP_IMXRT_BOOT_HEADER) # Include device configuration data block for RT1050 EVK from NXP's HAL. # This configuration block may need modification if another SDRAM chip # is used on your custom board. - zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) zephyr_library_sources(${RT1062_BOARD_DIR}/dcd/dcd.c) endif() endif() diff --git a/boards/nxp/mimxrt1062_fmurt6/board.yml b/boards/nxp/mimxrt1062_fmurt6/board.yml index 60541a7f3614..bf397cc5dd35 100644 --- a/boards/nxp/mimxrt1062_fmurt6/board.yml +++ b/boards/nxp/mimxrt1062_fmurt6/board.yml @@ -1,6 +1,6 @@ board: name: mimxrt1062_fmurt6 - full_name: FMURT6 + full_name: MIMXRT1062-FMURT6 vendor: nxp socs: - name: mimxrt1062 diff --git a/boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6.dts b/boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6.dts index 4b5826281ca5..98f56bfddac2 100644 --- a/boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6.dts +++ b/boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "mimxrt1062_fmurt6-pinctrl.dtsi" #include #include diff --git a/boards/nxp/mimxrt1064_evk/CMakeLists.txt b/boards/nxp/mimxrt1064_evk/CMakeLists.txt index 0b2ef8b7db9d..6068fd2d2e64 100644 --- a/boards/nxp/mimxrt1064_evk/CMakeLists.txt +++ b/boards/nxp/mimxrt1064_evk/CMakeLists.txt @@ -21,15 +21,12 @@ if(CONFIG_NXP_IMXRT_BOOT_HEADER) # This flash configuration block may need modification if another # flash chip is used on your custom board. See NXP AN12238 for more # information. - zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) - zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) zephyr_library_sources(xip/evkmimxrt1064_flexspi_nor_config.c) zephyr_library_include_directories(xip) endif() if(CONFIG_DEVICE_CONFIGURATION_DATA) # This device configuration block may need modification if another # SDRAM chip is used on your custom board. - zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) zephyr_library_sources(dcd/dcd.c) else() if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000) diff --git a/boards/nxp/mimxrt1064_evk/dcd/dcd.c b/boards/nxp/mimxrt1064_evk/dcd/dcd.c index bc20b441af10..1811934e9374 100644 --- a/boards/nxp/mimxrt1064_evk/dcd/dcd.c +++ b/boards/nxp/mimxrt1064_evk/dcd/dcd.c @@ -8,8 +8,8 @@ #include "dcd.h" -#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) -#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) +#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) +#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_DEVICE_CONFIGURATION_DATA) __attribute__((section(".boot_hdr.dcd_data"), used)) /* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */ @@ -617,5 +617,5 @@ const uint8_t dcd_data[] = { #else const uint8_t dcd_data[] = {0x00}; -#endif /* XIP_BOOT_HEADER_DCD_ENABLE */ -#endif /* XIP_BOOT_HEADER_ENABLE */ +#endif /* defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_DEVICE_CONFIGURATION_DATA) */ +#endif /* defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) */ diff --git a/boards/nxp/mimxrt1064_evk/doc/index.rst b/boards/nxp/mimxrt1064_evk/doc/index.rst index 439f222a7d1a..792886bb6d5e 100644 --- a/boards/nxp/mimxrt1064_evk/doc/index.rst +++ b/boards/nxp/mimxrt1064_evk/doc/index.rst @@ -98,6 +98,15 @@ this board with new support for Zephyr features. .. zephyr:board-supported-hw:: +Shields for Supported Features +============================== + +Some features in the table above are tested with Zephyr shields. These shields +are tested on this board: + +- :ref:`rk043fn02h_ct` and :ref:`rk043fn66hs_ctg` - support the Display interface. +- :ref:`dvp_fpc24_mt9m114` - supports the CSI video/camera interface. + Connections and I/Os ==================== diff --git a/boards/nxp/mimxrt1064_evk/mimxrt1064_evk.dts b/boards/nxp/mimxrt1064_evk/mimxrt1064_evk.dts index 8a353bca0a6e..3a2b1279bed4 100644 --- a/boards/nxp/mimxrt1064_evk/mimxrt1064_evk.dts +++ b/boards/nxp/mimxrt1064_evk/mimxrt1064_evk.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "mimxrt1064_evk-pinctrl.dtsi" #include #include @@ -85,7 +85,7 @@ compatible = "pwm-leds"; green_pwm_led: green_pwm_led { - pwms = <&flexpwm2_pwm3 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + pwms = <&flexpwm2_pwm3 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>; }; }; @@ -244,7 +244,7 @@ arduino_serial: &lpuart3 { compatible = "microchip,ksz8081"; reg = <0>; status = "okay"; - reset-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; int-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; microchip,interface-type = "rmii"; }; diff --git a/boards/nxp/mimxrt1064_evk/xip/evkmimxrt1064_flexspi_nor_config.c b/boards/nxp/mimxrt1064_evk/xip/evkmimxrt1064_flexspi_nor_config.c index 29fa415bc5b3..ef8b5b00f24d 100644 --- a/boards/nxp/mimxrt1064_evk/xip/evkmimxrt1064_flexspi_nor_config.c +++ b/boards/nxp/mimxrt1064_evk/xip/evkmimxrt1064_flexspi_nor_config.c @@ -7,7 +7,7 @@ #include "evkmimxrt1064_flexspi_nor_config.h" -#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) __attribute__((section(".boot_hdr.conf"), used)) const flexspi_nor_config_t qspi_flash_config = { @@ -65,4 +65,4 @@ const flexspi_nor_config_t qspi_flash_config = { .is_uniform_block_size = false, }; -#endif /* XIP_BOOT_HEADER_ENABLE */ +#endif /* defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) */ diff --git a/boards/nxp/mimxrt1064_evk/xip/evkmimxrt1064_flexspi_nor_config.h b/boards/nxp/mimxrt1064_evk/xip/evkmimxrt1064_flexspi_nor_config.h index f4332cefb454..87cb391d86fb 100644 --- a/boards/nxp/mimxrt1064_evk/xip/evkmimxrt1064_flexspi_nor_config.h +++ b/boards/nxp/mimxrt1064_evk/xip/evkmimxrt1064_flexspi_nor_config.h @@ -113,7 +113,7 @@ enum { FLEXSPI_MISC_OFFSET_SAFE_CONFIG_FREQ_ENABLE = 4, /* Bit for Pad setting override enable */ FLEXSPI_MISC_OFFSET_PAD_SETTING_OVERRIDE_ENABLE = 5, - /* Bit for DDR clock confiuration indication. */ + /* Bit for DDR clock configuration indication. */ FLEXSPI_MISC_OFFSET_DDR_MODE_ENABLE = 6, }; @@ -237,7 +237,7 @@ typedef struct flexspi_config { * 8 - Octal */ uint8_t sflash_pad_type; - /* [0x046-0x046] Serial Flash Frequencey, device specific + /* [0x046-0x046] Serial Flash Frequency, device specific * definitions, See System Boot Chapter for more details */ uint8_t serial_clk_freq; @@ -351,7 +351,7 @@ typedef struct _flexspi_nor_config { uint8_t need_exit_nocmd_mode; /* Half the Serial Clock for non-read command: true/false */ uint8_t half_clk_for_non_read_cmd; - /* Need to Restore NoCmd mode after IP commmand execution */ + /* Need to Restore NoCmd mode after IP command execution */ uint8_t need_restore_nocmd_mode; /* Block size */ uint32_t block_size; diff --git a/boards/nxp/mimxrt1160_evk/CMakeLists.txt b/boards/nxp/mimxrt1160_evk/CMakeLists.txt index 9f08c80b8bfe..a4662e7fdee2 100644 --- a/boards/nxp/mimxrt1160_evk/CMakeLists.txt +++ b/boards/nxp/mimxrt1160_evk/CMakeLists.txt @@ -16,15 +16,12 @@ if(CONFIG_NXP_IMXRT_BOOT_HEADER) # This flash configuration block may need modification if another # flash chip is used on your custom board. See NXP AN12238 for more # information. - zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) - zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) zephyr_library_sources(xip/evkmimxrt1160_flexspi_nor_config.c) zephyr_library_include_directories(xip) endif() if(CONFIG_DEVICE_CONFIGURATION_DATA) # This device configuration block may need modification if another # SDRAM chip is used on your custom board. - zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) zephyr_library_sources(dcd/dcd.c) else() if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000) diff --git a/boards/nxp/mimxrt1160_evk/dcd/dcd.c b/boards/nxp/mimxrt1160_evk/dcd/dcd.c index 4d906f3d7d67..34b3f80dd400 100644 --- a/boards/nxp/mimxrt1160_evk/dcd/dcd.c +++ b/boards/nxp/mimxrt1160_evk/dcd/dcd.c @@ -7,8 +7,8 @@ #include "dcd.h" -#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) -#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) +#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) +#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_DEVICE_CONFIGURATION_DATA) __attribute__((section(".boot_hdr.dcd_data"), used)) const uint8_t dcd_data[] = { @@ -745,5 +745,5 @@ const uint8_t dcd_data[] = { #else const uint8_t dcd_data[] = {0x00}; -#endif /* XIP_BOOT_HEADER_DCD_ENABLE */ -#endif /* XIP_BOOT_HEADER_ENABLE */ +#endif /* defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_DEVICE_CONFIGURATION_DATA) */ +#endif /* defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) */ diff --git a/boards/nxp/mimxrt1160_evk/doc/index.rst b/boards/nxp/mimxrt1160_evk/doc/index.rst index 85d5d1aa3acd..99f710714c7c 100644 --- a/boards/nxp/mimxrt1160_evk/doc/index.rst +++ b/boards/nxp/mimxrt1160_evk/doc/index.rst @@ -101,6 +101,16 @@ Supported Features Zephyr. Therefore, the mimxrt1170_evk board may have additional features already supported, which can also be re-used on this mimxrt1160_evk board: +Shields for Supported Features +============================== + +Some features in the table above are tested with Zephyr shields. These shields +are tested on this board: + +- :ref:`rk055hdmipi4m`, :ref:`rk055hdmipi4ma0` and :ref:`g1120b0mipi` - support + the MIPI-DSI display interface. +- :ref:`nxp_btb44_ov5640` - supports the MIPI-CSI video/camera interface. + Connections and I/Os ==================== diff --git a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk.dtsi b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk.dtsi index 9f5ded1dbe7e..9e090e6fc3aa 100644 --- a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk.dtsi +++ b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk.dtsi @@ -5,7 +5,7 @@ */ #include "mimxrt1160_evk-pinctrl.dtsi" -#include +#include #include / { @@ -128,9 +128,9 @@ reg = <0x00720000 DT_SIZE_M(7)>; }; - storage_partition: partition@E20000 { + storage_partition: partition@e20000 { label = "storage"; - reg = <0x00E20000 (DT_SIZE_M(2) - DT_SIZE_K(128))>; + reg = <0x00e20000 (DT_SIZE_M(2) - DT_SIZE_K(128))>; }; }; }; @@ -160,7 +160,7 @@ compatible = "microchip,ksz8081"; reg = <0>; status = "okay"; - reset-gpios = <&gpio12 12 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio12 12 GPIO_ACTIVE_LOW>; int-gpios = <&gpio9 11 GPIO_ACTIVE_HIGH>; microchip,interface-type = "rmii"; }; diff --git a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4.dts b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4.dts index 581be06d8caf..729146aa8a39 100644 --- a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4.dts +++ b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "mimxrt1160_evk.dtsi" / { diff --git a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4.yaml b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4.yaml index 445f170f5730..a1a3f487a3f9 100644 --- a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4.yaml +++ b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4.yaml @@ -5,7 +5,7 @@ # identifier: mimxrt1160_evk/mimxrt1166/cm4 -name: NXP MIMXRT1160-EVK CM4 +name: NXP MIMXRT1160-EVK (CM4) type: mcu arch: arm toolchain: diff --git a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7.dts b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7.dts index 8e91ed2a5636..bc4dd1427d7d 100644 --- a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7.dts +++ b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "mimxrt1160_evk.dtsi" / { diff --git a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7.yaml b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7.yaml index d803d9332e38..e5929321e915 100644 --- a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7.yaml +++ b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7.yaml @@ -5,7 +5,7 @@ # identifier: mimxrt1160_evk/mimxrt1166/cm7 -name: NXP MIMXRT1160-EVK CM7 +name: NXP MIMXRT1160-EVK (CM7) type: mcu arch: arm toolchain: diff --git a/boards/nxp/mimxrt1160_evk/xip/evkmimxrt1160_flexspi_nor_config.c b/boards/nxp/mimxrt1160_evk/xip/evkmimxrt1160_flexspi_nor_config.c index b16ebfcff253..22fc88c7b6c2 100644 --- a/boards/nxp/mimxrt1160_evk/xip/evkmimxrt1160_flexspi_nor_config.c +++ b/boards/nxp/mimxrt1160_evk/xip/evkmimxrt1160_flexspi_nor_config.c @@ -7,7 +7,7 @@ #include "evkmimxrt1160_flexspi_nor_config.h" -#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) __attribute__((section(".boot_hdr.conf"), used)) #define FLASH_DUMMY_CYCLES 0x09 @@ -89,4 +89,4 @@ const flexspi_nor_config_t qspi_flash_config = { .is_uniform_block_size = false, }; -#endif /* XIP_BOOT_HEADER_ENABLE */ +#endif /* defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) */ diff --git a/boards/nxp/mimxrt1160_evk/xip/evkmimxrt1160_flexspi_nor_config.h b/boards/nxp/mimxrt1160_evk/xip/evkmimxrt1160_flexspi_nor_config.h index e9d12927697f..f1acb4d41b50 100644 --- a/boards/nxp/mimxrt1160_evk/xip/evkmimxrt1160_flexspi_nor_config.h +++ b/boards/nxp/mimxrt1160_evk/xip/evkmimxrt1160_flexspi_nor_config.h @@ -112,7 +112,7 @@ enum { FLEXSPI_MISC_OFFSET_SAFE_CONFIG_FREQ_ENABLE = 4, /* Bit for Pad setting override enable */ FLEXSPI_MISC_OFFSET_PAD_SETTING_OVERRIDE_ENABLE = 5, - /* Bit for DDR clock confiuration indication. */ + /* Bit for DDR clock configuration indication. */ FLEXSPI_MISC_OFFSET_DDR_MODE_ENABLE = 6, }; @@ -242,7 +242,7 @@ typedef struct flexspi_config { * 8 - Octal */ uint8_t sflash_pad_type; - /* [0x046-0x046] Serial Flash Frequencey, device specific + /* [0x046-0x046] Serial Flash Frequency, device specific * definitions, See System Boot Chapter for more details */ uint8_t serial_clk_freq; @@ -358,7 +358,7 @@ typedef struct _flexspi_nor_config { uint8_t need_exit_nocmd_mode; /* Half the Serial Clock for non-read command: true/false */ uint8_t half_clk_for_non_read_cmd; - /* Need to Restore NoCmd mode after IP commmand execution */ + /* Need to Restore NoCmd mode after IP command execution */ uint8_t need_restore_nocmd_mode; /* Block size */ uint32_t block_size; diff --git a/boards/nxp/mimxrt1170_evk/CMakeLists.txt b/boards/nxp/mimxrt1170_evk/CMakeLists.txt index 8ef240f3df9f..9c64a98be757 100644 --- a/boards/nxp/mimxrt1170_evk/CMakeLists.txt +++ b/boards/nxp/mimxrt1170_evk/CMakeLists.txt @@ -21,15 +21,13 @@ if(CONFIG_NXP_IMXRT_BOOT_HEADER) # This flash configuration block may need modification if another # flash chip is used on your custom board. See NXP AN12238 for more # information. - zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) - zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) zephyr_library_sources(xip/${RT1170_BOARD_NAME}_flexspi_nor_config.c) zephyr_library_include_directories(xip) endif() if(CONFIG_EXTERNAL_MEM_CONFIG_DATA) # This external memory configuration data block may need modification # if another SDRAM chip is used on your custom board. - zephyr_compile_definitions(XIP_BOOT_HEADER_XMCD_ENABLE=1) + zephyr_library_compile_definitions(XIP_BOOT_HEADER_XMCD_ENABLE=1) zephyr_library_sources(xmcd/xmcd.c) else() if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000) diff --git a/boards/nxp/mimxrt1170_evk/board.yml b/boards/nxp/mimxrt1170_evk/board.yml index fce50aef20b3..a4e836fd3182 100644 --- a/boards/nxp/mimxrt1170_evk/board.yml +++ b/boards/nxp/mimxrt1170_evk/board.yml @@ -1,6 +1,6 @@ board: name: mimxrt1170_evk - full_name: MIMXRT1170-EVK/EVKB + full_name: MIMXRT1170-EVK vendor: nxp socs: - name: mimxrt1176 diff --git a/boards/nxp/mimxrt1170_evk/dcd/dcd.c b/boards/nxp/mimxrt1170_evk/dcd/dcd.c index 81a1ec826ec5..c8b675eb9a5b 100644 --- a/boards/nxp/mimxrt1170_evk/dcd/dcd.c +++ b/boards/nxp/mimxrt1170_evk/dcd/dcd.c @@ -7,8 +7,8 @@ #include "dcd.h" -#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) -#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) +#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) +#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_DEVICE_CONFIGURATION_DATA) __attribute__((section(".boot_hdr.dcd_data"), used)) const uint8_t dcd_data[] = { @@ -883,5 +883,5 @@ const uint8_t dcd_data[] = { #else const uint8_t dcd_data[] = {0x00}; -#endif /* XIP_BOOT_HEADER_DCD_ENABLE */ -#endif /* XIP_BOOT_HEADER_ENABLE */ +#endif /* defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_DEVICE_CONFIGURATION_DATA) */ +#endif /* defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) */ diff --git a/boards/nxp/mimxrt1170_evk/doc/index.rst b/boards/nxp/mimxrt1170_evk/doc/index.rst index ccf0b3887d9b..df16929b57f3 100644 --- a/boards/nxp/mimxrt1170_evk/doc/index.rst +++ b/boards/nxp/mimxrt1170_evk/doc/index.rst @@ -107,6 +107,20 @@ Zephyr, to better enable the entire RT11xx family. .. zephyr:board-supported-hw:: +Shields for Supported Features +============================== + +Some features in the table above are tested with Zephyr shields. These shields +are tested on this board: + +- :ref:`rk055hdmipi4m`, :ref:`rk055hdmipi4ma0` and :ref:`g1120b0mipi` - support + the MIPI-DSI display interface. +- :ref:`nxp_btb44_ov5640` - supports the MIPI-CSI video/camera interface. +- :ref:`nxp_m2_wifi_bt` - EVK RevB version is tested with this shield to attach any M.2 module + with BT HCI UART interface and Wi-Fi SDIO interface. The shield binds the required NXP + HCI driver or SDIO driver to perform firmware-load and other setup configurations + for NXP SoC IW416/IW612/IW610. + Connections and I/Os ==================== @@ -388,11 +402,6 @@ should see the following message in the terminal: ***** Booting Zephyr OS v3.4.0-xxxx-xxxxxxxxxxxxx ***** Hello World! mimxrt1170_evk -.. note:: - If you want to run any bluetooth sample on the mimxrt1170_evk@B device (build using - ``-DBOARD=mimxrt1170_evk@B/mimxrt1176/cm7``), the extended Bluetooth module needs to be - installed on the M.2 interface. - ENET1G Driver ============= diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk-pinctrl.dtsi b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk-pinctrl.dtsi index 9b60004c9f96..93fc31befc70 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk-pinctrl.dtsi +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk-pinctrl.dtsi @@ -326,6 +326,19 @@ }; }; + pinmux_sai3: pinmux_sai3 { + group0 { + pinmux = <&iomuxc_gpio_emc_b2_17_sai3_mclk>, + <&iomuxc_gpio_emc_b2_16_sai3_tx_sync>, + <&iomuxc_gpio_emc_b2_15_sai3_tx_bclk>, + <&iomuxc_gpio_emc_b2_14_sai3_tx_data>, + <&iomuxc_gpio_emc_b2_13_sai3_rx_data>; + drive-strength = "high"; + slew-rate = "fast"; + input-enable; + }; + }; + pinmux_sai4: pinmux_sai4 { group0 { pinmux = <&iomuxc_lpsr_gpio_lpsr_09_sai4_tx_data>, diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk.dtsi b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk.dtsi index ab2f9dfb2219..a01f73c1d022 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk.dtsi +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk.dtsi @@ -5,7 +5,7 @@ */ #include "mimxrt1170_evk-pinctrl.dtsi" -#include +#include #include #include @@ -154,7 +154,7 @@ arduino_serial: &lpuart2 { compatible = "microchip,ksz8081"; reg = <0>; status = "okay"; - reset-gpios = <&gpio12 12 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio12 12 GPIO_ACTIVE_LOW>; int-gpios = <&gpio9 11 GPIO_ACTIVE_HIGH>; microchip,interface-type = "rmii"; }; @@ -236,6 +236,11 @@ arduino_spi: &lpspi1 { pinctrl-names = "default"; }; +&sai3 { + pinctrl-0 = <&pinmux_sai3>; + pinctrl-names = "default"; +}; + &lpadc1 { pinctrl-0 = <&pinmux_lpadc1>; pinctrl-names = "default"; @@ -293,9 +298,9 @@ arduino_spi: &lpspi1 { reg = <0x00720000 DT_SIZE_M(7)>; }; - storage_partition: partition@E20000 { + storage_partition: partition@e20000 { label = "storage"; - reg = <0x00E20000 (DT_SIZE_M(2) - DT_SIZE_K(128))>; + reg = <0x00e20000 (DT_SIZE_M(2) - DT_SIZE_K(128))>; }; }; }; diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.dts b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.dts index 397b91b150a2..f03bbf057969 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.dts +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "mimxrt1170_evk.dtsi" / { diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.yaml b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.yaml index 4056069d8aa9..a66b47c46781 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.yaml +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.yaml @@ -5,7 +5,7 @@ # identifier: mimxrt1170_evk@A/mimxrt1176/cm4 -name: NXP MIMXRT1170-EVK CM4 +name: NXP MIMXRT1170-EVK (CM4) type: mcu arch: arm toolchain: diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_B.overlay b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_B.overlay index 64236b4ce536..44e4487c78f5 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_B.overlay +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_B.overlay @@ -57,9 +57,9 @@ reg = <0x00720000 DT_SIZE_M(7)>; }; - storage_partition: partition@E20000 { + storage_partition: partition@e20000 { label = "storage"; - reg = <0x00E20000 (DT_SIZE_M(50) - DT_SIZE_K(128))>; + reg = <0x00e20000 (DT_SIZE_M(50) - DT_SIZE_K(128))>; }; }; }; diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_B.yaml b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_B.yaml index af866754ca76..083c299b2c92 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_B.yaml +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_B.yaml @@ -5,7 +5,7 @@ # identifier: mimxrt1170_evk@B/mimxrt1176/cm4 -name: NXP MIMXRT1170-EVKB CM4 +name: NXP MIMXRT1170-EVKB (CM4) type: mcu arch: arm toolchain: diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.dts b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.dts index dd3dda62ee21..49e11272fd24 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.dts +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "mimxrt1170_evk.dtsi" / { diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.yaml b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.yaml index 46587fb95477..452968e2b344 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.yaml +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.yaml @@ -5,7 +5,7 @@ # identifier: mimxrt1170_evk@A/mimxrt1176/cm7 -name: NXP MIMXRT1170-EVK CM7 +name: NXP MIMXRT1170-EVK (CM7) type: mcu arch: arm toolchain: diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.overlay b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.overlay index a073a86d6a83..27d5325b0f77 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.overlay +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.overlay @@ -60,9 +60,9 @@ reg = <0x00720000 DT_SIZE_M(7)>; }; - storage_partition: partition@E20000 { + storage_partition: partition@e20000 { label = "storage"; - reg = <0x00E20000 (DT_SIZE_M(50) - DT_SIZE_K(128))>; + reg = <0x00e20000 (DT_SIZE_M(50) - DT_SIZE_K(128))>; }; }; }; diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.yaml b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.yaml index 009aebd98e20..e71986bc2ae5 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.yaml +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.yaml @@ -5,7 +5,7 @@ # identifier: mimxrt1170_evk@B/mimxrt1176/cm7 -name: NXP MIMXRT1170-EVKB CM7 +name: NXP MIMXRT1170-EVKB (CM7) type: mcu arch: arm toolchain: diff --git a/boards/nxp/mimxrt1170_evk/xip/evkbmimxrt1170_flexspi_nor_config.c b/boards/nxp/mimxrt1170_evk/xip/evkbmimxrt1170_flexspi_nor_config.c index 890e8cc1b56b..4bd28d273bea 100644 --- a/boards/nxp/mimxrt1170_evk/xip/evkbmimxrt1170_flexspi_nor_config.c +++ b/boards/nxp/mimxrt1170_evk/xip/evkbmimxrt1170_flexspi_nor_config.c @@ -7,7 +7,7 @@ #include "evkbmimxrt1170_flexspi_nor_config.h" -#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) __attribute__((section(".boot_hdr.conf"), used)) #define FLASH_DUMMY_CYCLES 0x08 @@ -88,4 +88,4 @@ const flexspi_nor_config_t qspi_flash_config = { .is_uniform_block_size = false, }; -#endif /* XIP_BOOT_HEADER_ENABLE */ +#endif /* defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) */ diff --git a/boards/nxp/mimxrt1170_evk/xip/evkbmimxrt1170_flexspi_nor_config.h b/boards/nxp/mimxrt1170_evk/xip/evkbmimxrt1170_flexspi_nor_config.h index bc9c9e523ffe..7199ab1e63d9 100644 --- a/boards/nxp/mimxrt1170_evk/xip/evkbmimxrt1170_flexspi_nor_config.h +++ b/boards/nxp/mimxrt1170_evk/xip/evkbmimxrt1170_flexspi_nor_config.h @@ -112,7 +112,7 @@ enum { FLEXSPI_MISC_OFFSET_SAFE_CONFIG_FREQ_ENABLE = 4, /* Bit for Pad setting override enable */ FLEXSPI_MISC_OFFSET_PAD_SETTING_OVERRIDE_ENABLE = 5, - /* Bit for DDR clock confiuration indication. */ + /* Bit for DDR clock configuration indication. */ FLEXSPI_MISC_OFFSET_DDR_MODE_ENABLE = 6, }; @@ -242,7 +242,7 @@ typedef struct flexspi_config { * 8 - Octal */ uint8_t sflash_pad_type; - /* [0x046-0x046] Serial Flash Frequencey, device specific + /* [0x046-0x046] Serial Flash Frequency, device specific * definitions, See System Boot Chapter for more details */ uint8_t serial_clk_freq; @@ -358,7 +358,7 @@ typedef struct _flexspi_nor_config { uint8_t need_exit_nocmd_mode; /* Half the Serial Clock for non-read command: true/false */ uint8_t half_clk_for_non_read_cmd; - /* Need to Restore NoCmd mode after IP commmand execution */ + /* Need to Restore NoCmd mode after IP command execution */ uint8_t need_restore_nocmd_mode; /* Block size */ uint32_t block_size; diff --git a/boards/nxp/mimxrt1170_evk/xip/evkmimxrt1170_flexspi_nor_config.c b/boards/nxp/mimxrt1170_evk/xip/evkmimxrt1170_flexspi_nor_config.c index 5b46ac3c9fc4..9dfae4d92511 100644 --- a/boards/nxp/mimxrt1170_evk/xip/evkmimxrt1170_flexspi_nor_config.c +++ b/boards/nxp/mimxrt1170_evk/xip/evkmimxrt1170_flexspi_nor_config.c @@ -7,7 +7,7 @@ #include "evkmimxrt1170_flexspi_nor_config.h" -#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) __attribute__((section(".boot_hdr.conf"), used)) #define FLASH_DUMMY_CYCLES 0x09 @@ -86,4 +86,4 @@ const flexspi_nor_config_t qspi_flash_config = { .is_uniform_block_size = false, }; -#endif /* XIP_BOOT_HEADER_ENABLE */ +#endif /* defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) */ diff --git a/boards/nxp/mimxrt1170_evk/xip/evkmimxrt1170_flexspi_nor_config.h b/boards/nxp/mimxrt1170_evk/xip/evkmimxrt1170_flexspi_nor_config.h index 1b986f32dd81..b7f05c5d966d 100644 --- a/boards/nxp/mimxrt1170_evk/xip/evkmimxrt1170_flexspi_nor_config.h +++ b/boards/nxp/mimxrt1170_evk/xip/evkmimxrt1170_flexspi_nor_config.h @@ -113,7 +113,7 @@ enum { FLEXSPI_MISC_OFFSET_SAFE_CONFIG_FREQ_ENABLE = 4, /* Bit for Pad setting override enable */ FLEXSPI_MISC_OFFSET_PAD_SETTING_OVERRIDE_ENABLE = 5, - /* Bit for DDR clock confiuration indication. */ + /* Bit for DDR clock configuration indication. */ FLEXSPI_MISC_OFFSET_DDR_MODE_ENABLE = 6, }; @@ -239,7 +239,7 @@ typedef struct flexspi_config { * 8 - Octal */ uint8_t sflash_pad_type; - /* [0x046-0x046] Serial Flash Frequencey, device specific + /* [0x046-0x046] Serial Flash Frequency, device specific * definitions, See System Boot Chapter for more details */ uint8_t serial_clk_freq; @@ -355,7 +355,7 @@ typedef struct _flexspi_nor_config { uint8_t need_exit_nocmd_mode; /* Half the Serial Clock for non-read command: true/false */ uint8_t half_clk_for_non_read_cmd; - /* Need to Restore NoCmd mode after IP commmand execution */ + /* Need to Restore NoCmd mode after IP command execution */ uint8_t need_restore_nocmd_mode; /* Block size */ uint32_t block_size; diff --git a/boards/nxp/mimxrt1170_evk/xmcd/xmcd.c b/boards/nxp/mimxrt1170_evk/xmcd/xmcd.c index 3c2e848afda7..317db623859f 100644 --- a/boards/nxp/mimxrt1170_evk/xmcd/xmcd.c +++ b/boards/nxp/mimxrt1170_evk/xmcd/xmcd.c @@ -7,7 +7,7 @@ #include "xmcd.h" -#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) #if defined(XIP_BOOT_HEADER_XMCD_ENABLE) && (XIP_BOOT_HEADER_XMCD_ENABLE == 1) __attribute__((section(".boot_hdr.xmcd_data"), used)) @@ -31,4 +31,4 @@ const uint32_t xmcd_data[] = { 0x02}; #endif /* XIP_BOOT_HEADER_XMCD_ENABLE */ -#endif /* XIP_BOOT_HEADER_ENABLE */ +#endif /* defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) */ diff --git a/boards/nxp/mimxrt1180_evk/CMakeLists.txt b/boards/nxp/mimxrt1180_evk/CMakeLists.txt index 2867e065c54a..63e75a83b28d 100644 --- a/boards/nxp/mimxrt1180_evk/CMakeLists.txt +++ b/boards/nxp/mimxrt1180_evk/CMakeLists.txt @@ -28,13 +28,12 @@ if(CONFIG_NXP_IMXRT_BOOT_HEADER) if(CONFIG_BOOT_FLEXSPI_NOR) # This flash configuration block may need modification if another # flash chip is used on your custom board. - zephyr_compile_definitions(XIP_EXTERNAL_FLASH=1) - zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) + zephyr_library_compile_definitions(XIP_EXTERNAL_FLASH=1) zephyr_library_sources(xip/evkmimxrt1180_flexspi_nor_config.c) zephyr_library_include_directories(xip) endif() if(CONFIG_EXTERNAL_MEM_CONFIG_DATA AND CONFIG_NXP_IMX_EXTERNAL_HYPERRAM) - zephyr_compile_definitions(USE_HYPERRAM) - zephyr_library_sources(xip/evkmimxrt1180_flexspi_nor_config.c) + zephyr_library_compile_definitions(USE_HYPERRAM) + zephyr_library_sources(xip/evkmimxrt1180_flexspi_nor_config.c) endif() endif() diff --git a/boards/nxp/mimxrt1180_evk/Kconfig.defconfig b/boards/nxp/mimxrt1180_evk/Kconfig.defconfig index 6f3f7c263be5..ab6cc49963d2 100644 --- a/boards/nxp/mimxrt1180_evk/Kconfig.defconfig +++ b/boards/nxp/mimxrt1180_evk/Kconfig.defconfig @@ -29,17 +29,18 @@ config BUILD_OUTPUT_INFO_HEADER default y DT_CHOSEN_IMAGE_M7 = nxp,m7-partition +DT_CHOSEN_ZEPHYR_FLASH = zephyr,flash -# Only adjust LMA if running from ITCM +# Only adjust LMA if running from RAM if !CM7_BOOT_FROM_FLASH -# Adjust the offset of the output image if building for RT118x SOC ITCM +# Adjust the offset of the output image if building for RT118x SOC in RAM FLEXSPI_BASE := $(dt_nodelabel_reg_addr_hex,flexspi,1) -ITCM_BASE := $(dt_nodelabel_reg_addr_hex,itcm,1) +M7_CODE_BASE := $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_ZEPHYR_FLASH)) IMAGE_M7_ADDR := $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_IMAGE_M7)) config BUILD_OUTPUT_ADJUST_LMA - default "($(IMAGE_M7_ADDR) + $(FLEXSPI_BASE) - $(ITCM_BASE))" + default "($(IMAGE_M7_ADDR) + $(FLEXSPI_BASE) - $(M7_CODE_BASE))" endif # !CM7_BOOT_FROM_FLASH endif # SECOND_CORE_MCUX && BOARD_MIMXRT1180_EVK_MIMXRT1189_CM7 diff --git a/boards/nxp/mimxrt1180_evk/cm33_sram_dtcm.overlay b/boards/nxp/mimxrt1180_evk/cm33_sram_dtcm.overlay new file mode 100644 index 000000000000..345322f0dc9c --- /dev/null +++ b/boards/nxp/mimxrt1180_evk/cm33_sram_dtcm.overlay @@ -0,0 +1,21 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Remove property from DTCM: zephyr,memory-region = "DTCM"; */ +/delete-node/ &dtcm; + +/ { + chosen { + zephyr,sram = &dtcm; + }; + + soc { + dtcm: memory@30000000 { + compatible = "nmmio-sram"; + reg = <0x30000000 DT_SIZE_K(128)>; + }; + }; +}; diff --git a/boards/nxp/mimxrt1180_evk/cm7/mpu_regions.c b/boards/nxp/mimxrt1180_evk/cm7/mpu_regions.c index cd444ea4ec67..63693357a308 100644 --- a/boards/nxp/mimxrt1180_evk/cm7/mpu_regions.c +++ b/boards/nxp/mimxrt1180_evk/cm7/mpu_regions.c @@ -7,6 +7,12 @@ #include #include +#ifdef CONFIG_ARM_MPU_SRAM_WRITE_THROUGH +#define ARM_MPU_SRAM_REGION_ATTR REGION_RAM_WT_ATTR +#else +#define ARM_MPU_SRAM_REGION_ATTR REGION_RAM_ATTR +#endif + #define MEMORY_REGION_SIZE_KB(SIZE) (SIZE / 1024) #define ITCM_SIZE DT_REG_SIZE_BY_IDX(DT_NODELABEL(itcm), 0) @@ -60,7 +66,7 @@ static const struct arm_mpu_region mpu_regions[] = { #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ocram1)) MPU_REGION_ENTRY("OCRAM1", REGION_OCRAM1_SHM_BASE_ADDRESS, - REGION_RAM_ATTR(REGION_OCRAM1_SHM_SIZE)), + ARM_MPU_SRAM_REGION_ATTR(REGION_OCRAM1_SHM_SIZE)), #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ocram2)) @@ -70,7 +76,7 @@ static const struct arm_mpu_region mpu_regions[] = { #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(hyperram0)) MPU_REGION_ENTRY("HYPER_RAM", REGION_HYPER_RAM_BASE_ADDRESS, - REGION_RAM_ATTR(REGION_HYPER_RAM_SIZE)), + ARM_MPU_SRAM_REGION_ATTR(REGION_HYPER_RAM_SIZE)), #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(w25q128jw)) diff --git a/boards/nxp/mimxrt1180_evk/cm7_code_hyperram.overlay b/boards/nxp/mimxrt1180_evk/cm7_code_hyperram.overlay new file mode 100644 index 000000000000..2ea5cc199312 --- /dev/null +++ b/boards/nxp/mimxrt1180_evk/cm7_code_hyperram.overlay @@ -0,0 +1,42 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include + +/ { + chosen { + zephyr,flash = &hyperram0; + zephyr,code-partition = &slot1_partition; + }; +}; + +&flexspi2 { + status = "okay"; +}; + +&hyperram0 { + /* + * Currently, HyperRAM on this board must be accessed under XIP mode, + * so that the ROM bootloader can initialize it by reading the XMCD configuration. + * These XMCD configurations are stored in the default settings file + * `xip/evkmimxrt1180_flexspi_nor_config.c`. (If modifications are needed, + * please refer to the examples and the "System Boot" chapter in the + * RT1180 Reference Manual.) + * The CM33 core of the MIMXRT1180_EVK runs in XIP mode and uses the + * HyperRAM space as the RAM region by default. Therefore, the status of the + * full hyperram0 memory node is set to "okay" for cm33 core. + * At this point, the CM7 core can also access the HyperRAM. + * However, since the entire HyperRAM region is occupied in the CM33's DTS, + * users can allocate the HyperRAM reasonably so that both cores (CM33 and CM7) + * can use HyperRAM as their RAM region. + * + * If not configured by the ROM bootloader, the user must ensure the hyperram0 + * device is enabled in the DTS, otherwise, the user must set 'status = "disabled"; + * Note: mpu_region.c uses the status property from the DTS to configure the + * corresponding MPU settings. + */ + zephyr,memory-attr = ; + status = "okay"; +}; diff --git a/boards/nxp/mimxrt1180_evk/doc/index.rst b/boards/nxp/mimxrt1180_evk/doc/index.rst index 43f5081179c6..fad0f84fccd0 100644 --- a/boards/nxp/mimxrt1180_evk/doc/index.rst +++ b/boards/nxp/mimxrt1180_evk/doc/index.rst @@ -128,6 +128,17 @@ The MIMXRT1180 SoC is configured to use SysTick as the system clock source, running at 240MHz. When targeting the M7 core, SysTick will also be used, running at 792MHz +ITCM and DTCM +============= + +If placing ``zephyr,flash`` in ITCM or ``zephyr,sram`` in DTCM, the property +``zephyr,memory-region`` should be deleted from the memory device node. +For example, this overlay moves the CM33 ``zephyr,sram`` to DTCM: + +.. code-block:: none + + boards/nxp/mimxrt1180_evk/cm33_sram_dtcm.overlay + Serial Port =========== @@ -177,23 +188,28 @@ starting the CM7 core. CM7 Execution Modes =================== -The CM7 core can execute code in two different modes: +The CM7 core is enabled to execute code in three memory options: -1. **ITCM Mode (Default)**: The CM7 code is copied from flash to ITCM (Instruction Tightly Coupled Memory) +1. **ITCM (Default)**: The CM7 code is copied from flash to ITCM (Instruction Tightly Coupled Memory) and executed from there. This provides faster execution but is limited by the ITCM size. -2. **Flash Mode**: The CM7 code is executed directly from flash memory (XIP - eXecute In Place). +2. **Flash**: The CM7 code is executed directly from flash memory (XIP - eXecute In Place). This allows for larger code size but may be slower than ITCM execution. When booting CM7 from Flash the TRDC execution permissions has to be set by CM33 core. -Configuring CM7 Execution Mode -============================== +3. **HyperRAM**: The CM7 code is copied from flash to external HyperRAM and executed from there. + This allows for larger code size but may be slower than ITCM execution. Be aware, the CM33 + default data placement ``zephyr,sram`` is in HyperRAM. Ensure the CM33 and CM7 are not using overlapping + regions in HyperRAM. One option given below moves the CM33 data to DTCM. + +Configuring CM7 Execution memory +================================ -To configure the CM7 execution mode, you can use the following Kconfig option: +To configure the memory for CM7 execution, you can use the following Kconfig option: .. code-block:: none - CONFIG_CM7_BOOT_FROM_FLASH=n # For ITCM execution (default) + CONFIG_CM7_BOOT_FROM_FLASH=n # For RAM execution, ITCM or HyperRAM (default) CONFIG_CM7_BOOT_FROM_FLASH=y # For flash execution When building with west, you can specify this option on the command line: @@ -212,6 +228,11 @@ When building with west, you can specify this option on the command line: -Dremote_EXTRA_DTC_OVERLAY_FILE=${ZEPHYR_BASE}/boards/nxp/mimxrt1180_evk/cm7_flash_boot.overlay \ -DCONFIG_CM7_BOOT_FROM_FLASH=y -Dremote_CONFIG_CM7_BOOT_FROM_FLASH=y + # For HyperRAM execution + west build -b mimxrt1180_evk//cm33 samples/drivers/mbox --sysbuild -- \ + -Dremote_EXTRA_DTC_OVERLAY_FILE=${ZEPHYR_BASE}/boards/nxp/mimxrt1180_evk/cm7_code_hyperram.overlay \ + -DEXTRA_DTC_OVERLAY_FILE=${ZEPHYR_BASE}/boards/nxp/mimxrt1180_evk/cm33_sram_dtcm.overlay + Flash Boot Overlay ================== @@ -224,17 +245,44 @@ the flash memory properly. The overlay file is located at: This overlay configures the CM7 core to use the flash memory for code execution instead of ITCM. +HyperRAM Execution Overlay +========================== + +When executing the CM7 core from HyperRAM, you need to apply a device tree overlay. An example +overlay file is located at: + +.. code-block:: none + + boards/nxp/mimxrt1180_evk/cm7_code_hyperram.overlay + +The MPU attributes for the board also need to be changed in this file: + +.. code-block:: none + + boards/nxp/mimxrt1180_evk/cm7/mpu_regions.c + +Changing the line below enables execution from the HyperRAM region by setting the flash attribute: + +.. code-block:: none + + #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(hyperram0)) + MPU_REGION_ENTRY("HYPER_RAM", REGION_HYPER_RAM_BASE_ADDRESS, + - REGION_RAM_ATTR(REGION_HYPER_RAM_SIZE)), + + REGION_FLASH_ATTR(REGION_HYPER_RAM_SIZE)), + #endif + Memory Usage ============ -* **ITCM Mode**: The CM7 code is copied from flash to ITCM. -* **Flash Mode**: The CM7 code is executed directly from flash, which allows for larger code size. +* **from RAM**: The CM7 code is copied from flash to ITCM or HyperRAM. +* **from Flash**: The CM7 code is executed directly from flash, which allows for larger code size than ITCM. Performance Considerations ========================== -* **ITCM Mode**: Provides faster execution due to the low-latency ITCM memory. -* **Flash Mode**: May be slower due to flash memory access times, but allows for larger code size. +* **from ITCM**: Provides faster execution due to the low-latency internal ITCM memory. +* **from external memory**: External flash or HyperRAM may be slower due to memory access times, + but allows for larger code size. Dual Core samples Debugging =========================== diff --git a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk.dtsi b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk.dtsi index 5b21283a7041..220216046328 100644 --- a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk.dtsi +++ b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk.dtsi @@ -232,9 +232,9 @@ reg = <0x00720000 DT_SIZE_M(7)>; }; - storage_partition: partition@E20000 { + storage_partition: partition@e20000 { label = "storage"; - reg = <0x00E20000 (DT_SIZE_M(2) - DT_SIZE_K(128))>; + reg = <0x00e20000 (DT_SIZE_M(2) - DT_SIZE_K(128))>; }; }; }; diff --git a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.dts b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.dts index b651020aa748..75fb926fbfdf 100644 --- a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.dts +++ b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "mimxrt1180_evk.dtsi" / { diff --git a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.yaml b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.yaml index ae2a0c86bcc4..4d3e8da3aef2 100644 --- a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.yaml +++ b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.yaml @@ -5,7 +5,7 @@ # identifier: mimxrt1180_evk/mimxrt1189/cm33 -name: NXP MIMXRT1180-EVK CM33 +name: NXP MIMXRT1180-EVK (CM33) type: mcu arch: arm toolchain: diff --git a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.dts b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.dts index cb6e2019cf2a..25714d42ed92 100644 --- a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.dts +++ b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "mimxrt1180_evk.dtsi" / { diff --git a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.yaml b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.yaml index 6d23f30f31c3..a44dbf609b77 100644 --- a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.yaml +++ b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.yaml @@ -5,7 +5,7 @@ # identifier: mimxrt1180_evk/mimxrt1189/cm7 -name: NXP MIMXRT1180-EVK CM7 +name: NXP MIMXRT1180-EVK (CM7) type: mcu arch: arm toolchain: diff --git a/boards/nxp/mimxrt1180_evk/xip/evkmimxrt1180_flexspi_nor_config.c b/boards/nxp/mimxrt1180_evk/xip/evkmimxrt1180_flexspi_nor_config.c index 72b1328e0103..613f859278ca 100644 --- a/boards/nxp/mimxrt1180_evk/xip/evkmimxrt1180_flexspi_nor_config.c +++ b/boards/nxp/mimxrt1180_evk/xip/evkmimxrt1180_flexspi_nor_config.c @@ -8,8 +8,8 @@ #include "evkmimxrt1180_flexspi_nor_config.h" /* clang-format off */ -#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1) && \ - defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1) && \ + defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) /* clang-format on */ #if defined(USE_HYPERRAM) diff --git a/boards/nxp/mimxrt1180_evk/xip/evkmimxrt1180_flexspi_nor_config.h b/boards/nxp/mimxrt1180_evk/xip/evkmimxrt1180_flexspi_nor_config.h index 07e52dbceb09..c9b8a03e165e 100644 --- a/boards/nxp/mimxrt1180_evk/xip/evkmimxrt1180_flexspi_nor_config.h +++ b/boards/nxp/mimxrt1180_evk/xip/evkmimxrt1180_flexspi_nor_config.h @@ -190,7 +190,7 @@ typedef struct flexspi_config { * 8 - Octal */ uint8_t sflash_pad_type; - /* [0x046-0x046] Serial Flash Frequencey, device specific + /* [0x046-0x046] Serial Flash Frequency, device specific * definitions, See System Boot Chapter for more details */ uint8_t serial_clk_freq; diff --git a/boards/nxp/mimxrt595_evk/CMakeLists.txt b/boards/nxp/mimxrt595_evk/CMakeLists.txt index 328d2e248185..598380da19df 100644 --- a/boards/nxp/mimxrt595_evk/CMakeLists.txt +++ b/boards/nxp/mimxrt595_evk/CMakeLists.txt @@ -16,15 +16,13 @@ if(CONFIG_NXP_IMXRT_BOOT_HEADER) "the MIMXRT595-EVK, but targeting a custom board. You may need to " "update your flash configuration block data") endif() + # This flash configuration block may need modification if another # flash chip is used on your custom board. See NXP AN13304 for more # information. - zephyr_compile_definitions(BOOT_HEADER_ENABLE=1) - zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) zephyr_library_sources(flash_config/flash_config.c) zephyr_library_include_directories(flash_config) endif() - # Add custom linker section to relocate framebuffers to PSRAM zephyr_linker_sources_ifdef(CONFIG_LV_Z_VDB_CUSTOM_SECTION SECTIONS dc_ram.ld) diff --git a/boards/nxp/mimxrt595_evk/doc/index.rst b/boards/nxp/mimxrt595_evk/doc/index.rst index 6094544e0436..dad03fd5008f 100644 --- a/boards/nxp/mimxrt595_evk/doc/index.rst +++ b/boards/nxp/mimxrt595_evk/doc/index.rst @@ -60,6 +60,15 @@ already supported, which can also be re-used on this mimxrt595_evk board. .. zephyr:board-supported-hw:: +Shields for Supported Features +============================== + +Some features in the table above are tested with Zephyr shields. These shields +are tested on this board: + +- :ref:`rk055hdmipi4m`, :ref:`rk055hdmipi4ma0` and :ref:`g1120b0mipi` - support + the MIPI-DSI display interface. + Connections and IOs =================== diff --git a/boards/nxp/mimxrt595_evk/flash_config/flash_config.c b/boards/nxp/mimxrt595_evk/flash_config/flash_config.c index a0c7a7392e06..b2660f47f869 100644 --- a/boards/nxp/mimxrt595_evk/flash_config/flash_config.c +++ b/boards/nxp/mimxrt595_evk/flash_config/flash_config.c @@ -6,7 +6,7 @@ */ #include "flash_config.h" -#if defined(BOOT_HEADER_ENABLE) && (BOOT_HEADER_ENABLE == 1) +#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && (CONFIG_NXP_IMXRT_BOOT_HEADER == 1) __attribute__((section(".flash_conf"), used)) const flexspi_nor_config_t flash_config = { @@ -105,4 +105,4 @@ const flexspi_nor_config_t flash_config = { .flashStateCtx = 0x07008200u, }; -#endif /* BOOT_HEADER_ENABLE */ +#endif /* defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && (CONFIG_NXP_IMXRT_BOOT_HEADER == 1) */ diff --git a/boards/nxp/mimxrt595_evk/flash_config/flash_config.h b/boards/nxp/mimxrt595_evk/flash_config/flash_config.h index 7b6ae4ac83b0..6332e9d62d8a 100644 --- a/boards/nxp/mimxrt595_evk/flash_config/flash_config.h +++ b/boards/nxp/mimxrt595_evk/flash_config/flash_config.h @@ -88,7 +88,7 @@ enum { FLEXSPI_MISC_OFFSET_SAFE_CONFIG_FREQ_ENABLE = 4, /* Bit for Pad setting override enable */ FLEXSPI_MISC_OFFSET_PAD_SETTING_OVERRIDE_ENABLE = 5, - /* Bit for DDR clock confiuration indication. */ + /* Bit for DDR clock configuration indication. */ FLEXSPI_MISC_OFFSET_DDR_MODE_ENABLE = 6, /* Bit for DLLCR settings under all modes */ FLEXSPI_MISC_OFFSET_USE_VALID_TIME_FOR_ALL_FREQ = 7, diff --git a/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.dts b/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.dts index f92a4f529b75..11f6b8464754 100644 --- a/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.dts +++ b/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include #include @@ -135,6 +135,14 @@ enable-gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; regulator-boot-on; }; + + psram: memory@0x38000000 { + compatible = "zephyr,memory-region"; + device_type = "memory"; + reg = <0x38000000 0x8000000>; + status = "okay"; + zephyr,memory-region = "FLEXSPI2"; + }; }; /* @@ -347,6 +355,14 @@ arduino_serial: &flexcomm12 { zephyr_udc0: &usbhs { status = "okay"; + phy-handle = <&usbphy>; +}; + +&usbphy { + status = "okay"; + tx-d-cal = <12>; + tx-cal-45-dp-ohms = <6>; + tx-cal-45-dm-ohms = <6>; }; &ctimer0 { @@ -379,6 +395,7 @@ zephyr_udc0: &usbhs { disk-name = "SD2"; status = "okay"; }; + pinctrl-0 = <&pinmux_usdhc>; pinctrl-names = "default"; mmc-hs200-1_8v; diff --git a/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.yaml b/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.yaml index 65739236386e..a3e054963f30 100644 --- a/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.yaml +++ b/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.yaml @@ -14,6 +14,7 @@ toolchain: ram: 4608 flash: 65536 supported: + - adc - arduino_gpio - arduino_i2c - arduino_serial @@ -28,5 +29,6 @@ supported: - sdhc - spi - usb_device + - usbd - watchdog vendor: nxp diff --git a/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_f1.yaml b/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_f1.yaml index 48245feebc68..a51f88ed0268 100644 --- a/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_f1.yaml +++ b/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_f1.yaml @@ -1,5 +1,5 @@ identifier: mimxrt595_evk/mimxrt595s/f1 -name: i.MXRT595 Fusion F1 DSP +name: NXP MIMXRT595-EVK (Fusion F1 DSP) type: mcu arch: xtensa toolchain: diff --git a/boards/nxp/mimxrt685_evk/CMakeLists.txt b/boards/nxp/mimxrt685_evk/CMakeLists.txt index cfe2c2f07cf8..af3af08eedaf 100644 --- a/boards/nxp/mimxrt685_evk/CMakeLists.txt +++ b/boards/nxp/mimxrt685_evk/CMakeLists.txt @@ -18,11 +18,10 @@ if(CONFIG_NXP_IMXRT_BOOT_HEADER) "the MIMXRT685-EVK, but targeting a custom board. You may need to " "update your flash configuration block data") endif() + # This flash configuration block may need modification if another # flash chip is used on your custom board. See NXP AN13386 for more # information. - zephyr_compile_definitions(BOOT_HEADER_ENABLE=1) - zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) zephyr_library_sources(flash_config/flash_config.c) zephyr_library_include_directories(flash_config) endif() diff --git a/boards/nxp/mimxrt685_evk/doc/index.rst b/boards/nxp/mimxrt685_evk/doc/index.rst index 530b314da0c0..9490f6a8e755 100644 --- a/boards/nxp/mimxrt685_evk/doc/index.rst +++ b/boards/nxp/mimxrt685_evk/doc/index.rst @@ -305,17 +305,19 @@ earlier packages and ``xt-lang`` newer ones) and the To build a project: - Set up toolchain environment - - No special configuration needed for the GCC variant in the Zephyr SDK. - - For the proprietary Xtensa toolchain, set ``XTENSA_CORE``, - ``XTENSA_TOOLCHAIN_PATH`` and ``TOOLCHAIN_VER`` according to your - installed version. ``ZEPHYR_TOOLCHAIN_VARIANT`` should be either ``xcc`` - or ``xt-clang``. + + - No special configuration needed for the GCC variant in the Zephyr SDK. + - For the proprietary Xtensa toolchain, set ``XTENSA_CORE``, + ``XTENSA_TOOLCHAIN_PATH`` and ``TOOLCHAIN_VER`` according to your + installed version. ``ZEPHYR_TOOLCHAIN_VARIANT`` should be either ``xcc`` + or ``xt-clang``. + - Build the project with: -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mimxrt685_evk/mimxrt685s/hifi4 - :goals: build + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mimxrt685_evk/mimxrt685s/hifi4 + :goals: build Debugging can be directly carried out using the J-Link GDB server with ``xt-gdb`` (Xtensa proprietary) or ``gdb`` (Zephyr SDK) connected. It's diff --git a/boards/nxp/mimxrt685_evk/flash_config/flash_config.c b/boards/nxp/mimxrt685_evk/flash_config/flash_config.c index f7e7453a53e0..8a8098c2409c 100644 --- a/boards/nxp/mimxrt685_evk/flash_config/flash_config.c +++ b/boards/nxp/mimxrt685_evk/flash_config/flash_config.c @@ -6,7 +6,7 @@ */ #include "flash_config.h" -#if defined(BOOT_HEADER_ENABLE) && (BOOT_HEADER_ENABLE == 1) +#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && (CONFIG_NXP_IMXRT_BOOT_HEADER == 1) __attribute__((section(".flash_conf"), used)) const flexspi_nor_config_t flexspi_config = { @@ -135,4 +135,4 @@ const flexspi_nor_config_t flexspi_config = { .flash_state_ctx = 0x07008100u, }; -#endif /* BOOT_HEADER_ENABLE */ +#endif /* defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && (CONFIG_NXP_IMXRT_BOOT_HEADER == 1) */ diff --git a/boards/nxp/mimxrt685_evk/flash_config/flash_config.h b/boards/nxp/mimxrt685_evk/flash_config/flash_config.h index dede879429f1..0dc8055c7bc0 100644 --- a/boards/nxp/mimxrt685_evk/flash_config/flash_config.h +++ b/boards/nxp/mimxrt685_evk/flash_config/flash_config.h @@ -95,7 +95,7 @@ enum { FLEXSPI_MISC_OFFSET_WORD_ADDRESSABLE_ENABLE = 3, /* Bit for Safe Configuration Frequency enable */ FLEXSPI_MISC_OFFSET_SAFE_CONFIG_FREQ_ENABLE = 4, - /* Bit for DDR clock confiuration indication. */ + /* Bit for DDR clock configuration indication. */ FLEXSPI_MISC_OFFSET_DDR_MODE_ENABLE = 6, }; @@ -201,7 +201,7 @@ typedef struct flexspi_config { * 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal */ uint8_t sflash_pad_type; - /* !< [0x046-0x046] Serial Flash Frequencey, + /* !< [0x046-0x046] Serial Flash Frequency, * device specific definitions, * See System Boot Chapter for more details */ @@ -275,7 +275,7 @@ typedef struct _flexspi_nor_config { uint8_t need_exit_nocmd_mode; /* !< Half the Serial Clock for non-read command: true/false */ uint8_t half_clk_for_non_read_cmd; - /* !< Need to Restore NoCmd mode after IP commmand execution */ + /* !< Need to Restore NoCmd mode after IP command execution */ uint8_t need_restore_nocmd_mode; /* !< Block size */ uint32_t block_size; diff --git a/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.dts b/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.dts index c6399ba494a0..4cd11d7f2fb5 100644 --- a/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.dts +++ b/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include #include #include @@ -361,6 +361,7 @@ i2s1: &flexcomm3 { disk-name = "SD"; status = "okay"; }; + pinctrl-0 = <&pinmux_usdhc>; pinctrl-names = "default"; }; diff --git a/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.yaml b/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.yaml index 8e861a3a3e57..055eb40d144a 100644 --- a/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.yaml +++ b/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.yaml @@ -14,6 +14,7 @@ toolchain: ram: 4608 flash: 65536 supported: + - adc - arduino_gpio - arduino_i2c - arduino_serial diff --git a/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_hifi4.yaml b/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_hifi4.yaml index 86cd87801adb..f0684da96fdc 100644 --- a/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_hifi4.yaml +++ b/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_hifi4.yaml @@ -5,7 +5,7 @@ # identifier: mimxrt685_evk/mimxrt685s/hifi4 -name: NXP MIMXRT685-EVK (HiFi 4) +name: NXP MIMXRT685-EVK (HiFi4) type: mcu arch: xtensa ram: 64 diff --git a/boards/nxp/mimxrt700_evk/CMakeLists.txt b/boards/nxp/mimxrt700_evk/CMakeLists.txt index ea4dff764b2d..98f67d466db2 100644 --- a/boards/nxp/mimxrt700_evk/CMakeLists.txt +++ b/boards/nxp/mimxrt700_evk/CMakeLists.txt @@ -16,11 +16,10 @@ if(CONFIG_NXP_IMXRT_BOOT_HEADER) "the MIMXRT7xx-EVK, but targeting a custom board. You may need to " "update your flash configuration block data") endif() + # This flash configuration block may need modification if another # flash chip is used on your custom board. See NXP AN13304 for more # information. - zephyr_compile_definitions(BOOT_HEADER_ENABLE=1) - zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) zephyr_library_sources(flash_config/flash_config.c) zephyr_library_include_directories(flash_config) endif() diff --git a/boards/nxp/mimxrt700_evk/board.c b/boards/nxp/mimxrt700_evk/board.c index 25c924cbca3b..508efebde0e7 100644 --- a/boards/nxp/mimxrt700_evk/board.c +++ b/boards/nxp/mimxrt700_evk/board.c @@ -467,6 +467,15 @@ void board_early_init_hook(void) #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(wwdt0)) CLOCK_AttachClk(kLPOSC_to_WWDT0); + /* ROM may change ITRC OUT3_SEL0 and OUT4_SEL0, which will select + * WWDT0-2 as input for ITRC. When a WWDT timeout happened the + * event will first assert and trigger a ITRC reset, This ITRC + * reset is faster than WWDT reset and reset the system before + * a WWDT reset. Change back the OUT3_SEL0 and OUT4_SEL0 to allow + * RSTCTL capturing WWDT reset event. + */ + ITRC->OUT_SEL[3][0] = 0xAAAAAA0A; + ITRC->OUT_SEL[4][0] = 0xAAAAAA0A; #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai0)) diff --git a/boards/nxp/mimxrt700_evk/doc/index.rst b/boards/nxp/mimxrt700_evk/doc/index.rst index 8395f1fdcf8a..510c68496cad 100644 --- a/boards/nxp/mimxrt700_evk/doc/index.rst +++ b/boards/nxp/mimxrt700_evk/doc/index.rst @@ -24,12 +24,16 @@ Hardware ******** - Main Compute Subsystem: - - Arm Cortex-M33 up to 325 MHz - - HiFi 4 DSP up to 325 MHz - - eIQ Neutron NPU up to 325 MHz -- Sense Compute Subsystem: - - Arm Cortex-M33 up to 250 MHz - - HiFi 1 DSP up to 250 MHz + + - Arm Cortex-M33 up to 325 MHz + - HiFi 4 DSP up to 325 MHz + - eIQ Neutron NPU up to 325 MHz + +- Sense Compute Subsystem + + - Arm Cortex-M33 up to 250 MHz + - HiFi 1 DSP up to 250 MHz + - 7.5 MB on-chip SRAM - Three xSPI interfaces for off-chip memory expansion, supporting up to 16b wide external memories up to 250 MHz DDR - eUSB support with integrated PHY @@ -248,8 +252,40 @@ directly, but some modifications are required (see for a list). The display sample can be built for this module like so: .. zephyr-app-commands:: - :board: mimxrt700_evk + :board: mimxrt700_evk/mimxrt798s/cm33_cpu0 :shield: g1120b0mipi :zephyr-app: samples/drivers/display :goals: build :compact: + +NXP RK055HDMIPI4MA0 720p MIPI Display +===================================== + +The :ref:`rk055hdmipi4ma0` connects to the board's MIPI connector J52 +directly, but some modifications are required (see +:zephyr_file:`boards/shields/rk055hdmipi4ma0/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.overlay` +for a list). This panel has a 720p resolution which needs large frame buffer(s) so PSRAM memory +region must be used, which needs to connect JP45 1-2. The display sample can be built for this +module like so: + +.. zephyr-app-commands:: + :board: mimxrt700_evk/mimxrt798s/cm33_cpu0 + :shield: rk055hdmipi4ma0 + :zephyr-app: samples/drivers/display + :goals: build + :compact: + +NXP ZC143AC72MIPI MIPI Display +============================== + +The :ref:`zc143ac72mipi` connects to the board's MIPI connector J26 +directly, but some modifications are required (see +:zephyr_file:`boards/shields/zc143ac72mipi/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.overlay` +for a list). The display sample can be built for this module like so: + +.. zephyr-app-commands:: + :board: mimxrt700_evk/mimxrt798s/cm33_cpu0 + :shield: zc143ac72mipi + :zephyr-app: samples/drivers/display + :goals: build + :compact: diff --git a/boards/nxp/mimxrt700_evk/flash_config/flash_config.c b/boards/nxp/mimxrt700_evk/flash_config/flash_config.c index ea5d6d3c9de6..2bdc1cc03616 100644 --- a/boards/nxp/mimxrt700_evk/flash_config/flash_config.c +++ b/boards/nxp/mimxrt700_evk/flash_config/flash_config.c @@ -5,7 +5,7 @@ */ #include "flash_config.h" -#if defined(BOOT_HEADER_ENABLE) && (BOOT_HEADER_ENABLE == 1) +#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && (CONFIG_NXP_IMXRT_BOOT_HEADER == 1) __attribute__((section(".flash_conf"), used)) const fc_static_platform_config_t flash_config = { @@ -139,4 +139,4 @@ const fc_static_platform_config_t flash_config = { #endif }; -#endif /* BOOT_HEADER_ENABLE */ +#endif /* defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && (CONFIG_NXP_IMXRT_BOOT_HEADER == 1) */ diff --git a/boards/nxp/mimxrt700_evk/flash_config/flash_config.h b/boards/nxp/mimxrt700_evk/flash_config/flash_config.h index 0b0dcbd62636..5347fcb4e873 100644 --- a/boards/nxp/mimxrt700_evk/flash_config/flash_config.h +++ b/boards/nxp/mimxrt700_evk/flash_config/flash_config.h @@ -96,7 +96,7 @@ enum { FC_XSPI_MISC_OFFSET_WORD_ADDRESSABLE_ENABLE = 3, /* !< Bit for Safe Configuration Frequency enable */ FC_XSPI_MISC_OFFSET_SAFE_CONFIG_FREQ_ENABLE = 4, - /* !< Bit for DDR clock confiuration indication. */ + /* !< Bit for DDR clock configuration indication. */ FC_XSPI_MISC_OFFSET_DDR_MODE_ENABLE = 6, }; @@ -194,7 +194,7 @@ typedef struct xspi_config { *1 - Single, 2 - Dual, 4 - Quad, 8 - Octal */ uint8_t sflash_pad_type; - /* !< [0x046-0x046] Serial Flash Frequencey + /* !< [0x046-0x046] Serial Flash Frequency * 1: 30 mhz * 2: 50 mhz * 3: 60 mhz @@ -295,7 +295,7 @@ typedef struct _fc_xspi_nor_config { uint8_t need_exit_nocmd_mode; /* !< Half the Serial Clock for non-read command: true/false */ uint8_t half_clk_for_non_read_cmd; - /* !< Need to Restore NoCmd mode after IP commmand execution */ + /* !< Need to Restore NoCmd mode after IP command execution */ uint8_t need_restore_nocmd_mode; /* !< Block size */ uint32_t block_size; diff --git a/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0.dts b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0.dts index cb6d72561cdb..0fd6f234781a 100644 --- a/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0.dts +++ b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include #include #include "mimxrt700_evk-pinctrl.dtsi" @@ -109,6 +109,15 @@ zephyr,memory-region = "PSRAM"; }; }; + + /* Memory region controlled by XSPI2, can be used by media domain masters. */ + psram2: memory@70000000 { + compatible = "zephyr,memory-region"; + device_type = "memory"; + reg = <0x70000000 0x8000000>; + status = "okay"; + zephyr,memory-region = "PSRAM2"; + }; }; &ctimer0 { @@ -386,9 +395,9 @@ zephyr_lcdif: &lcdif {}; reg = <0x00720000 DT_SIZE_M(7)>; }; - storage_partition: partition@E20000 { + storage_partition: partition@e20000 { label = "storage"; - reg = <0x00E20000 (DT_SIZE_M(2) - DT_SIZE_K(128))>; + reg = <0x00e20000 (DT_SIZE_M(2) - DT_SIZE_K(128))>; }; }; }; @@ -457,6 +466,7 @@ zephyr_udc0: &usb0 { disk-name = "SD2"; status = "okay"; }; + pinctrl-0 = <&pinmux_usdhc>; pinctrl-names = "default"; mmc-hs200-1_8v; diff --git a/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0.yaml b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0.yaml index eeade2809eaa..0c208f2fd854 100644 --- a/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0.yaml +++ b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0.yaml @@ -5,7 +5,7 @@ # identifier: mimxrt700_evk/mimxrt798s/cm33_cpu0 -name: NXP MIMXRT700-EVK (CM33_CPU0) +name: NXP MIMXRT700-EVK (CPU0) type: mcu arch: arm ram: 512 diff --git a/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu1.dts b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu1.dts index 43ff70ffb76e..a3cf1b3b4997 100644 --- a/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu1.dts +++ b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu1.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include #include "mimxrt700_evk-pinctrl.dtsi" #include diff --git a/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu1.yaml b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu1.yaml index 13f0b3b76602..8867a4488bf1 100644 --- a/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu1.yaml +++ b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu1.yaml @@ -5,7 +5,7 @@ # identifier: mimxrt700_evk/mimxrt798s/cm33_cpu1 -name: NXP MIMXRT700-EVK (CM33_CPU1) +name: NXP MIMXRT700-EVK (CPU1) type: mcu arch: arm ram: 256 diff --git a/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_hifi1.yaml b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_hifi1.yaml index 7c3bee257ef9..8617853f99b7 100644 --- a/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_hifi1.yaml +++ b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_hifi1.yaml @@ -5,7 +5,7 @@ # identifier: mimxrt700_evk/mimxrt798s/hifi1 -name: NXP MIMXRT700-EVK HiFi1 +name: NXP MIMXRT700-EVK (HiFi1) type: mcu arch: xtensa toolchain: diff --git a/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_hifi4.yaml b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_hifi4.yaml index 925a17ac4664..da3dd26e465f 100644 --- a/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_hifi4.yaml +++ b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_hifi4.yaml @@ -5,7 +5,7 @@ # identifier: mimxrt700_evk/mimxrt798s/hifi4 -name: NXP MIMXRT700-EVK HiFi4 +name: NXP MIMXRT700-EVK (HiFi4) type: mcu arch: xtensa toolchain: diff --git a/boards/nxp/mr_canhubk3/Kconfig.defconfig b/boards/nxp/mr_canhubk3/Kconfig.defconfig index 86a0fbbdb667..9773db8b68df 100644 --- a/boards/nxp/mr_canhubk3/Kconfig.defconfig +++ b/boards/nxp/mr_canhubk3/Kconfig.defconfig @@ -12,13 +12,16 @@ endif # SERIAL if SPI +config GPIO_INIT_PRIORITY + default 10 + config SPI_INIT_PRIORITY - default 50 + default 10 if WDT_NXP_FS26 config WDT_NXP_FS26_INIT_PRIORITY - default 51 + default 10 endif # WDT_NXP_FS26 endif # SPI diff --git a/boards/nxp/mr_canhubk3/doc/index.rst b/boards/nxp/mr_canhubk3/doc/index.rst index 570a2157c630..1ef1eba1203c 100644 --- a/boards/nxp/mr_canhubk3/doc/index.rst +++ b/boards/nxp/mr_canhubk3/doc/index.rst @@ -12,20 +12,22 @@ Hardware ******** - NXP S32K344 - - Arm Cortex-M7 (Lock-Step), 160 MHz (Max.) - - 4 MB of program flash, with ECC - - 320 KB RAM, with ECC - - Ethernet 100 Mbps, CAN FD, FlexIO, QSPI - - 12-bit 1 Msps ADC, 16-bit eMIOS timer + + - Arm Cortex-M7 (Lock-Step), 160 MHz (Max.) + - 4 MB of program flash, with ECC + - 320 KB RAM, with ECC + - Ethernet 100 Mbps, CAN FD, FlexIO, QSPI + - 12-bit 1 Msps ADC, 16-bit eMIOS timer - `NXP FS26 Safety System Basis Chip`_ -- Interfaces: - - Console UART - - 6x CAN FD - - 100Base-T1 Ethernet - - JST-GH connectors and I/O headers for I2C, SPI, GPIO, - PWM, etc. +- Interfaces + + - Console UART + - 6x CAN FD + - 100Base-T1 Ethernet + - JST-GH connectors and I/O headers for I2C, SPI, GPIO, + PWM, etc. More information about the hardware and design resources can be found at `NXP MR-CANHUBK3`_ website. @@ -143,12 +145,9 @@ flexcan5 | PTC11 | PTC11_CAN0_RX P22/P23 and support maximum 32 message buffers for concurrent active instances with 8 bytes payload. We need to pay attention to configuration options: - 1. :kconfig:option:`CONFIG_CAN_MAX_MB` must be less or equal than the + 1. :kconfig:option:`CONFIG_CAN_MCUX_FLEXCAN_MAX_FILTERS` must be less than the maximum number of message buffers that is according to the table below. - 2. :kconfig:option:`CONFIG_CAN_MAX_FILTER` must be less or equal than - :kconfig:option:`CONFIG_CAN_MAX_MB`. - =============== ========== ================ ================ Devicetree node Payload Hardware support Software support =============== ========== ================ ================ diff --git a/boards/nxp/mr_canhubk3/mr_canhubk3_common.dtsi b/boards/nxp/mr_canhubk3/mr_canhubk3_common.dtsi index 6b2b5b3fb172..29bd96f0bfc3 100644 --- a/boards/nxp/mr_canhubk3/mr_canhubk3_common.dtsi +++ b/boards/nxp/mr_canhubk3/mr_canhubk3_common.dtsi @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include #include #include #include @@ -395,7 +395,7 @@ status = "okay"; ssd1306: ssd1306@3c { - compatible = "solomon,ssd1306fb"; + compatible = "solomon,ssd1306"; reg = <0x3c>; width = <128>; height = <32>; @@ -475,7 +475,7 @@ status = "okay"; reg = <0x12>; int-gpios = <&gpiod_l 5 GPIO_ACTIVE_LOW>; - master-slave = "slave"; + master-slave = "auto"; }; }; diff --git a/boards/nxp/rd_rw612_bga/CMakeLists.txt b/boards/nxp/rd_rw612_bga/CMakeLists.txt index 246474cdd68e..1d59012a81f9 100644 --- a/boards/nxp/rd_rw612_bga/CMakeLists.txt +++ b/boards/nxp/rd_rw612_bga/CMakeLists.txt @@ -15,8 +15,6 @@ if(CONFIG_NXP_RW6XX_BOOT_HEADER) "the RD_RW612_BGA, but targeting a custom board. You may need to " "update your flash configuration block data") endif() - zephyr_compile_definitions(BOOT_HEADER_ENABLE=1) - zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) zephyr_library_sources(MX25U51245GZ4I00_FCB.c) endif() diff --git a/boards/nxp/rd_rw612_bga/dts/goworld_16880_lcm.overlay b/boards/nxp/rd_rw612_bga/dts/goworld_16880_lcm.overlay index 3f338f241a3a..5085022b4fad 100644 --- a/boards/nxp/rd_rw612_bga/dts/goworld_16880_lcm.overlay +++ b/boards/nxp/rd_rw612_bga/dts/goworld_16880_lcm.overlay @@ -46,15 +46,15 @@ width = <480>; invert-mode = "1-dot"; frmctl1 = [80 10]; - bpc = [1F 50 00 20]; - dfc = [8A 07 3B]; + bpc = [1f 50 00 20]; + dfc = [8a 07 3b]; pwr1 = [80 64]; pwr2 = <0x13>; - pwr3 = <0xA7>; + pwr3 = <0xa7>; vcmpctl = <0x09>; - doca = [40 8A 00 00 29 19 A5 38]; - pgc = [F0 06 0B 07 06 05 2E 33 47 3A 17 16 2E 31]; - ngc = [F0 09 0D 09 08 23 2E 33 46 38 13 13 2C 32]; + doca = [40 8a 00 00 29 19 a5 38]; + pgc = [f0 06 0b 07 06 05 2e 33 47 3a 17 16 2e 31]; + ngc = [f0 09 0d 09 08 23 2e 33 46 38 13 13 2c 32]; madctl = <0x28>; }; }; diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi b/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi index 9d9333053486..bdfc2f33f359 100644 --- a/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi +++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include #include "rd_rw612_bga-pinctrl.dtsi" #include #include @@ -257,6 +257,10 @@ zephyr_udc0: &usb_otg { status = "okay"; }; +zephyr_uhc0: &usbh { + status = "okay"; +}; + &dma0 { status = "okay"; }; diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml b/boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml index a47f0063dae9..dc71244aa10f 100644 --- a/boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml +++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml @@ -5,7 +5,7 @@ # identifier: rd_rw612_bga -name: NXP RD_RW612_BGA +name: NXP RD-RW612-BGA type: mcu arch: arm toolchain: @@ -28,6 +28,7 @@ supported: - pwm - spi - usb_device + - usb_host - watchdog - netif:eth - netif:openthread diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga_rw612_ethernet.dts b/boards/nxp/rd_rw612_bga/rd_rw612_bga_rw612_ethernet.dts index 6792e819adcb..32d80aa5e93d 100644 --- a/boards/nxp/rd_rw612_bga/rd_rw612_bga_rw612_ethernet.dts +++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga_rw612_ethernet.dts @@ -33,7 +33,7 @@ compatible = "microchip,ksz8081"; reg = <2>; status = "okay"; - reset-gpios = <&hsgpio1 23 GPIO_ACTIVE_HIGH>; + reset-gpios = <&hsgpio1 23 GPIO_ACTIVE_LOW>; int-gpios = <&hsgpio0 21 GPIO_ACTIVE_HIGH>; microchip,interface-type = "rmii"; }; diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga_rw612_ethernet.yaml b/boards/nxp/rd_rw612_bga/rd_rw612_bga_rw612_ethernet.yaml index dbdff161607e..ec8e5acec716 100644 --- a/boards/nxp/rd_rw612_bga/rd_rw612_bga_rw612_ethernet.yaml +++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga_rw612_ethernet.yaml @@ -5,7 +5,7 @@ # identifier: rd_rw612_bga/rw612/ethernet -name: NXP RD_RW612_BGA ETHERNET +name: NXP RD-RW612-BGA (Ethernet) type: mcu arch: arm toolchain: diff --git a/boards/nxp/rddrone_fmuk66/rddrone_fmuk66.dts b/boards/nxp/rddrone_fmuk66/rddrone_fmuk66.dts index ebd2cd80cee8..52201ff3cfed 100644 --- a/boards/nxp/rddrone_fmuk66/rddrone_fmuk66.dts +++ b/boards/nxp/rddrone_fmuk66/rddrone_fmuk66.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include #include "rddrone_fmuk66-pinctrl.dtsi" #include @@ -253,14 +253,14 @@ zephyr_udc0: &usbotg { reg = <0x00010000 DT_SIZE_K(932)>; }; - slot1_partition: partition@F9000 { + slot1_partition: partition@f9000 { label = "image-1"; - reg = <0x000F9000 DT_SIZE_K(932)>; + reg = <0x000f9000 DT_SIZE_K(932)>; }; - storage_partition: partition@1E2000 { + storage_partition: partition@1e2000 { label = "storage"; - reg = <0x001E2000 DT_SIZE_K(120)>; + reg = <0x001e2000 DT_SIZE_K(120)>; }; }; }; diff --git a/boards/nxp/s32k148_evb/s32k148_evb.dts b/boards/nxp/s32k148_evb/s32k148_evb.dts index 3bae75751051..e176bb341bc5 100644 --- a/boards/nxp/s32k148_evb/s32k148_evb.dts +++ b/boards/nxp/s32k148_evb/s32k148_evb.dts @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include "s32k148_evb-pinctrl.dtsi" / { diff --git a/boards/nxp/s32k5xxcvb/Kconfig.s32k5xxcvb b/boards/nxp/s32k5xxcvb/Kconfig.s32k5xxcvb new file mode 100644 index 000000000000..f69fd6331122 --- /dev/null +++ b/boards/nxp/s32k5xxcvb/Kconfig.s32k5xxcvb @@ -0,0 +1,7 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_S32K5XXCVB + select SOC_S32K566_M7 if BOARD_S32K5XXCVB_S32K566_M7 + select SOC_S32K566_R52 if BOARD_S32K5XXCVB_S32K566_R52 + select SOC_PART_NUMBER_S32K566JAMJGS if BOARD_S32K5XXCVB diff --git a/boards/nxp/s32k5xxcvb/board.cmake b/boards/nxp/s32k5xxcvb/board.cmake new file mode 100644 index 000000000000..c16a5f6026cc --- /dev/null +++ b/boards/nxp/s32k5xxcvb/board.cmake @@ -0,0 +1,21 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(trace32 + "--startup-args" + "elfFile=${PROJECT_BINARY_DIR}/${KERNEL_ELF_NAME}" +) + +if(${CONFIG_XIP}) + board_runner_args(trace32 "loadTo=mram") +else() + board_runner_args(trace32 "loadTo=sram") +endif() + +if(${CONFIG_CPU_CORTEX_M7}) + board_runner_args(trace32 "coreType=m7") +else() + board_runner_args(trace32 "coreType=r52") +endif() + +include(${ZEPHYR_BASE}/boards/common/trace32.board.cmake) diff --git a/boards/nxp/s32k5xxcvb/board.yml b/boards/nxp/s32k5xxcvb/board.yml new file mode 100644 index 000000000000..733249f25410 --- /dev/null +++ b/boards/nxp/s32k5xxcvb/board.yml @@ -0,0 +1,6 @@ +board: + name: s32k5xxcvb + full_name: S32K5XXCVB + vendor: nxp + socs: + - name: s32k566 diff --git a/boards/nxp/s32k5xxcvb/doc/index.rst b/boards/nxp/s32k5xxcvb/doc/index.rst new file mode 100644 index 000000000000..fc6a12e4d1ae --- /dev/null +++ b/boards/nxp/s32k5xxcvb/doc/index.rst @@ -0,0 +1,197 @@ +.. zephyr:board:: s32k5xxcvb + +Overview +******** + +The NXP S32K5XXCVB board is based on the `NXP S32K5 Series`_ family of automotive microcontrollers (MCUs), +which expands the S32K3 series to deliver higher performance, larger memory, and increased vehicle network +communication capability, all with lower power consumption. + +The S32K5 MCU features: +- Compute-focused Arm Cortex-R52 cores +- Platform-focused Arm Cortex-M7 cores +- Low-power-focused Arm Cortex-M4 core + +Zephyr OS is ported to run on both the Cortex-M7 and Cortex-R52 cores. + +- ``s32k5xxcvb/s32k566/m7``, for S32K566 Cortex-M7, code executed from code MRAM by default. +- ``s32k5xxcvb/s32k566/r52``, for S32K566 Cortex-R52, code executed from code MRAM by default. + +Hardware +******** + +- NXP S32K566 + - Arm Cortex-M7 (6 cores with two options 3 x Lock-Step or 2 x Lock-Step + 2 x Single-Core, + option 2 is configured by default). + - Arm Cortex-R52 (contains an R52 cluster with two Cortex-R52 cores). + - 1.5 MB SRAM for Cortex-M7, with ECC + - 1 MB of SRAM connected to the Cortex-R52, with ECC + - 32 MB of Code Magnetic RAM for all cores, with ECC + - Ethernet switch integrated, CAN FD/XL, QSPI + - 14-bit 3 Msps ADC, 24-bit eMIOS timer and more. + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Connections and IOs +=================== + +The Port columns in the Reference Manual (RM) are organized into ports and pins to ensure consistency with +the GPIO driver used in this Zephyr port. + +The table below summarizes the mapping between the Port columns in the RM and Zephyr’s ports and pins. +Please consider this mapping when using the GPIO driver or configuring pin multiplexing for device drivers. + ++-------------------+--------------------+ +| Ports in RM | Zephyr Ports/Pins | ++===================+====================+ +| GPIO0 - GPIO15 | PA0 - PA15 | ++-------------------+--------------------+ +| GPIO16 - GPIO31 | PB0 - PB15 | ++-------------------+--------------------+ +| GPIO32 - GPIO47 | PC0 - PC15 | ++-------------------+--------------------+ +| GPIO48 - GPIO63 | PD0 - PD15 | ++-------------------+--------------------+ +| GPIO64 - GPIO78 | PE0 - PE14 | ++-------------------+--------------------+ +| GPIO80 - GPIO95 | PF0 - PF15 | ++-------------------+--------------------+ +| GPIO96 - GPIO111 | PG0 - PG15 | ++-------------------+--------------------+ +| GPIO112 - GPIO127 | PH0 - PH15 | ++-------------------+--------------------+ +| GPIO128 - GPIO138 | PI0 - PI10 | ++-------------------+--------------------+ +| GPIO160 - GPIO175 | PK0 - PK15 | ++-------------------+--------------------+ +| GPIO176 - GPIO191 | PL0 - PL15 | ++-------------------+--------------------+ +| GPIO192 - GPIO207 | PM0 - PM15 | ++-------------------+--------------------+ +| GPIO208 - GPIO223 | PN0 - PN15 | ++-------------------+--------------------+ +| GPIO224 - GPIO239 | PO0 - PO15 | ++-------------------+--------------------+ +| GPIO240 - GPIO254 | PP0 - PP14 | ++-------------------+--------------------+ +| GPIO256 - GPIO263 | PQ0 - PQ7 | ++-------------------+--------------------+ +| GPIO304 - GPIO319 | PT0 - PT15 | ++-------------------+--------------------+ +| GPIO320 - GPIO335 | PU0 - PU15 | ++-------------------+--------------------+ +| GPIO336 - GPIO351 | PV0 - PV15 | ++-------------------+--------------------+ +| GPIO352 - GPIO363 | PW0 - PW11 | ++-------------------+--------------------+ + +LEDs +---- + +The board has three user RGB LEDs: + +======================= ===== ==== +Devicetree node Color Pin +======================= ===== ==== +led0 / user_led_red Red PP1 +led1 / user_led_green Green PO2 +led2 / user_led_blue Blue PN10 +======================= ===== ==== + +The user can control the LEDs in any way. An output of ``1`` illuminates the LED. + +Buttons +------- + +The board has two user buttons: + +======================= ======= === +Devicetree node Label Pin +======================= ======= === +sw0 / user_button_0 USERSW0 PF3 +sw1 / user_button_1 USERSW1 PF9 +======================= ======= === + +System Clock +============ + +- The Arm Cortex-M7: 200 MHz. +- The Arm Cortex-R52: 800 MHz. + +Set-up the Board +================ + +Connect the external debugger probe to the board's JTAG Cortex ETM connector (``J17``) +and to the host computer via USB or Ethernet, as supported by the probe. + +NXP S32K5XX-MB Shield +===================== + +This Zephyr shield, :ref:`nxp_s32k5xx_mb` expands the board’s available I/O connectivity + +The shield provides access to the following feature: +- Serial UART + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Applications for the ``s32k5xxcvb`` board can be built in the usual way as +documented in :ref:`build_an_application`. + +This board supports West runners for the following debug tools: + +- :ref:`Lauterbach TRACE32 ` + +Follow the installation steps of the debug tool you plan to use before loading +your firmware. + +Debugging +========= + +You can build and debug the :zephyr:code-sample:`hello_world` sample for the board +``s32k5xxcvb/s32k566/m7`` with: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: s32k5xxcvb/s32k566/m7 + :goals: build debug + +Flashing +======== + +Follow these steps if you just want to download the application to the board and run. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: s32k5xxcvb/s32k566/m7 + :goals: build flash + :compact: + +Core selection +============== + +This Zephyr port can only run single core. By default, Zephyr runs on the first core +of the selected board. To execute Zephyr application on other core, all runner parameters +must be overridden from command line: + +.. code-block:: console + + west --startup-args elfFile= coreType= loadTo= core= + +Where ```` is the path to the Zephyr application ELF in the output +directory. + +.. include:: ../../common/board-footer.rst.inc + +References +********** + +.. target-notes:: + +.. _NXP S32K5 Series: + https://www.nxp.com/products/S32K5 diff --git a/boards/nxp/s32k5xxcvb/s32k5xxcvb_s32k566-pinctrl.dtsi b/boards/nxp/s32k5xxcvb/s32k5xxcvb_s32k566-pinctrl.dtsi new file mode 100644 index 000000000000..39b63de69efd --- /dev/null +++ b/boards/nxp/s32k5xxcvb/s32k5xxcvb_s32k566-pinctrl.dtsi @@ -0,0 +1,55 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + eirq1_default: eirq1_default { + group1 { + pinmux = , ; + input-enable; + }; + }; + + flexcan0_default: flexcan0_default { + group1 { + pinmux = ; + output-enable; + }; + + group2 { + pinmux = ; + input-enable; + }; + }; + + xspi0_default: xspi0_default { + group1 { + pinmux = <(PB1_XSPI_DQSFA_I | PB1_XSPI_DQSFA_O)>, + , + <(PC9_XSPI_IOFA0_I | PC9_XSPI_IOFA0_O)>, + <(PB8_XSPI_IOFA1_I | PB8_XSPI_IOFA1_O)>, + <(PB15_XSPI_IOFA2_I | PB15_XSPI_IOFA2_O)>, + <(PC8_XSPI_IOFA3_I | PC8_XSPI_IOFA3_O)>, + <(PC0_XSPI_IOFA4_I | PC0_XSPI_IOFA4_O)>, + <(PB9_XSPI_IOFA5_I | PB9_XSPI_IOFA5_O)>, + <(PC10_XSPI_IOFA6_I | PC10_XSPI_IOFA6_O)>, + <(PA11_XSPI_IOFA7_I | PA11_XSPI_IOFA7_O)>; + output-enable; + input-enable; + bias-pull-up; + }; + + group2 { + pinmux = , + , + , + ; + output-enable; + bias-pull-up; + }; + }; +}; diff --git a/boards/nxp/s32k5xxcvb/s32k5xxcvb_s32k566.dtsi b/boards/nxp/s32k5xxcvb/s32k5xxcvb_s32k566.dtsi new file mode 100644 index 000000000000..03739ef3a3cb --- /dev/null +++ b/boards/nxp/s32k5xxcvb/s32k5xxcvb_s32k566.dtsi @@ -0,0 +1,173 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include "s32k5xxcvb_s32k566-pinctrl.dtsi" +#include + +/ { + aliases { + led0 = &user_led_red; + led1 = &user_led_green; + led2 = &user_led_blue; + sw0 = &user_button_0; + sw1 = &user_button_1; + watchdog0 = &swt_startup; + }; + + chosen { + zephyr,canbus = &flexcan0; + }; + + leds { + compatible = "gpio-leds"; + + user_led_red: user_led_red { + gpios = <&gpiop 1 GPIO_ACTIVE_HIGH>; + label = "RGBLED0_RED"; + }; + + user_led_green: user_led_green { + gpios = <&gpioo 2 GPIO_ACTIVE_HIGH>; + label = "RGBLED0_GREEN"; + }; + + user_led_blue: user_led_blue { + gpios = <&gpion 10 GPIO_ACTIVE_HIGH>; + label = "RGBLED0_BLUE"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + user_button_0: button_0 { + label = "USERSW0"; + gpios = <&gpiof 3 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + + user_button_1: button_1 { + label = "USERSW1"; + gpios = <&gpiof 9 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; +}; + +&gpiof { + status = "okay"; +}; + +&gpion { + status = "okay"; +}; + +&gpioo { + status = "okay"; +}; + +&gpiop { + status = "okay"; +}; + +&eirq1 { + pinctrl-0 = <&eirq1_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&flexcan0 { + pinctrl-0 = <&flexcan0_default>; + pinctrl-names = "default"; +}; + +&swt_startup { + status = "okay"; +}; + +&xspi0 { + pinctrl-0 = <&xspi0_default>; + pinctrl-names = "default"; + data-rate = "DDR"; + column-space = <3>; + word-addressable; + cs-hold-time = <6>; + cs-setup-time = <4>; + hold-time-2x; + sample-delay-half-cycle; + a-dll-ref-counter = <2>; + a-dll-resolution = <8>; + a-dll-coarse-delay = <6>; + a-dll-fine-delay = <7>; + a-dll-tap-select = <2>; + a-dll-mode = "BYPASSED"; + a-rx-clock-source = "EXTERNAL_DQS"; + a-io2-idle-high; + a-io3-idle-high; + enable-hresp-mask; + ahb-buffers-masters = <0 1 2 3>; + ahb-buffers-sizes = <1024 1024 1024 1024>; + ahb-buffers-all-masters; + a-differential-clock; + ahb-timeout = <3>; + dqs-as-an-output; + error-payload-high = <0x12345678>; + error-payload-low = <0x87654321>; + transaction-timeout = <0xFFFFFFFF>; + arbitration-timeout = <0xFFFFFFFF>; + status = "okay"; + + sfp_mdad { + compatible = "nxp,s32-xspi-sfp-mdad"; + + mdad_0: mdad_0 { + domain-id = <0>; + secure-attribute = <(NXP_S32_XSPI_NON_SECURE | NXP_S32_XSPI_SECURE)>; + }; + }; + + sfp_frad { + compatible = "nxp,s32-xspi-sfp-frad"; + #address-cells = <1>; + #size-cells = <1>; + + frad_0: frad@0 { + reg = <0x0 0xFFFFFFFF>; + master-domain-acp-policy = <(NXP_S32_XSPI_NON_SECURE | + NXP_S32_XSPI_SECURE | + NXP_S32_XSPI_PRIVILEGE)>; + }; + }; + + /* HyperRAM IS66WVH8M8DAL */ + is66wvh8m8dall: flash-controller@0 { + compatible = "nxp,s32-xspi-hyperram"; + reg = <0>; + jedec-id = [0c 83 0c 83 0c 83 0c 83 0c 83]; + device-id-word-addr = <0x000>; + size = ; + write-block-size = <2>; + initial-latency-cycles = <7>; + master-clock-type = "SINGLE_ENDED"; + max-program-buffer-size = <256>; + drive-strength-ohm = <34>; + refresh-interval-multiplier = "1"; + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + storage_partition: partition@0 { + label = "storage"; + reg = <0x00000 0x10000>; + }; + }; + }; +}; diff --git a/boards/nxp/s32k5xxcvb/s32k5xxcvb_s32k566_m7.dts b/boards/nxp/s32k5xxcvb/s32k5xxcvb_s32k566_m7.dts new file mode 100644 index 000000000000..ce4e48a2d548 --- /dev/null +++ b/boards/nxp/s32k5xxcvb/s32k5xxcvb_s32k566_m7.dts @@ -0,0 +1,20 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "s32k5xxcvb_s32k566.dtsi" + +/ { + model = "NXP S32K566CVB on Cortex-M7 cores"; + compatible = "nxp,s32k566cvb"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &cmram; + }; +}; diff --git a/boards/nxp/s32k5xxcvb/s32k5xxcvb_s32k566_m7.yaml b/boards/nxp/s32k5xxcvb/s32k5xxcvb_s32k566_m7.yaml new file mode 100644 index 000000000000..3f19b46bc38d --- /dev/null +++ b/boards/nxp/s32k5xxcvb/s32k5xxcvb_s32k566_m7.yaml @@ -0,0 +1,22 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +identifier: s32k5xxcvb/s32k566/m7 +name: NXP S32K5XXCVB M7 +type: mcu +arch: arm +ram: 512 +flash: 32768 +toolchain: + - zephyr +supported: + - adc + - can + - spi + - gpio + - pwm + - counter + - i2c + - watchdog + - flash +vendor: nxp diff --git a/boards/nxp/s32k5xxcvb/s32k5xxcvb_s32k566_m7_defconfig b/boards/nxp/s32k5xxcvb/s32k5xxcvb_s32k566_m7_defconfig new file mode 100644 index 000000000000..d640a2662da5 --- /dev/null +++ b/boards/nxp/s32k5xxcvb/s32k5xxcvb_s32k566_m7_defconfig @@ -0,0 +1,9 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y +CONFIG_CLOCK_CONTROL=y + +# Run from Code MRAM +CONFIG_XIP=y diff --git a/boards/nxp/s32k5xxcvb/s32k5xxcvb_s32k566_r52.dts b/boards/nxp/s32k5xxcvb/s32k5xxcvb_s32k566_r52.dts new file mode 100644 index 000000000000..1efb069a5933 --- /dev/null +++ b/boards/nxp/s32k5xxcvb/s32k5xxcvb_s32k566_r52.dts @@ -0,0 +1,19 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "s32k5xxcvb_s32k566.dtsi" + +/ { + model = "NXP S32K566CVB on Cortex-R52 cores"; + compatible = "nxp,s32k566cvb"; + + chosen { + zephyr,sram = &cpe_sram; + zephyr,flash = &cmram; + }; +}; diff --git a/boards/nxp/s32k5xxcvb/s32k5xxcvb_s32k566_r52.yaml b/boards/nxp/s32k5xxcvb/s32k5xxcvb_s32k566_r52.yaml new file mode 100644 index 000000000000..b6a583f9f9ae --- /dev/null +++ b/boards/nxp/s32k5xxcvb/s32k5xxcvb_s32k566_r52.yaml @@ -0,0 +1,22 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +identifier: s32k5xxcvb/s32k566/r52 +name: NXP S32K5XXCVB R52 +type: mcu +arch: arm +ram: 1024 +flash: 32768 +toolchain: + - zephyr +supported: + - adc + - can + - spi + - gpio + - pwm + - counter + - i2c + - watchdog + - flash +vendor: nxp diff --git a/boards/nxp/s32k5xxcvb/s32k5xxcvb_s32k566_r52_defconfig b/boards/nxp/s32k5xxcvb/s32k5xxcvb_s32k566_r52_defconfig new file mode 100644 index 000000000000..39a24d48122c --- /dev/null +++ b/boards/nxp/s32k5xxcvb/s32k5xxcvb_s32k566_r52_defconfig @@ -0,0 +1,8 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_CLOCK_CONTROL=y + +# Run from Code MRAM +CONFIG_XIP=y diff --git a/boards/nxp/s32k5xxcvb/support/debug.cmm b/boards/nxp/s32k5xxcvb/support/debug.cmm new file mode 100644 index 000000000000..b0f4df774d70 --- /dev/null +++ b/boards/nxp/s32k5xxcvb/support/debug.cmm @@ -0,0 +1,13 @@ +;******************************************************************************* +; Copyright 2025 NXP * +; SPDX-License-Identifier: Apache-2.0 * +; * +; Lauterbach TRACE32 start-up script for debugging s32k5xxcvb * +; * +;******************************************************************************* + +ENTRY %LINE &args + +DO ~~~~/startup.cmm command=debug &args + +ENDDO diff --git a/boards/nxp/s32k5xxcvb/support/flash.cmm b/boards/nxp/s32k5xxcvb/support/flash.cmm new file mode 100644 index 000000000000..0703c172d8bf --- /dev/null +++ b/boards/nxp/s32k5xxcvb/support/flash.cmm @@ -0,0 +1,13 @@ +;******************************************************************************* +; Copyright 2025 NXP * +; SPDX-License-Identifier: Apache-2.0 * +; * +; Lauterbach TRACE32 start-up script for flashing s32k5xxcvb * +; * +;******************************************************************************* + +ENTRY %LINE &args + +DO ~~~~/startup.cmm command=flash &args + +ENDDO diff --git a/boards/nxp/s32k5xxcvb/support/startup.cmm b/boards/nxp/s32k5xxcvb/support/startup.cmm new file mode 100644 index 000000000000..9d115727c6a5 --- /dev/null +++ b/boards/nxp/s32k5xxcvb/support/startup.cmm @@ -0,0 +1,152 @@ +;******************************************************************************* +; Copyright 2025 NXP * +; SPDX-License-Identifier: Apache-2.0 * +; * +; Lauterbach Trace32 start-up script for s32k5xxcvb * +; * +; Parameters: * +; - command operation to execute * +; valid values: flash, debug * +; default: debug * +; - elfFile filepath of ELF to load * +; - coreType type of the application core * +; valid values: m7, r52 * +; - core core index * +; valid values: 0 to 3 * +; default: 0 * +; - loadTo if "mram", the application will be downloaded to SoC * +; MRAM by a flash programming routine; if "sram" it * +; will be downloaded to SoC SRAM. * +; valid values: mram, sram * +; * +;******************************************************************************* + +ENTRY %LINE &args +LOCAL &coreId &cpuName &sramInitTarget + +&command=STRing.SCANAndExtract("&args","command=","debug") +&elfFile=STRing.SCANAndExtract("&args","elfFile=","") +&coreType=STRing.SCANAndExtract("&args","coreType=","") +&core=STRing.SCANAndExtract("&args","core=","0") +&loadTo=STRing.SCANAndExtract("&args","loadTo=","") + +IF ("&elfFile"=="") +( + PRINT %ERROR "Missing ELF file path" + PLIST + STOP + ENDDO +) + +IF ("&coreType"!="m7"&&"&coreType"!="r52") +( + PRINT %ERROR "Invalid core type: &coreType" + PLIST + STOP + ENDDO +) + +IF ("&coreType"=="m7") +( + IF (&core<0||&core>3) + ( + PRINT %ERROR "Invalid core number: &core" + ) + + &cpuName="M7" + &sramInitTarget="CM7" +) +ELSE +( + IF (&core<0||&core>1) + ( + PRINT %ERROR "Invalid core number: &core" + ) + + &cpuName="R52-CPE" + &sramInitTarget="CPE" +) + +; Trace32 indexes are offset by 1 +&coreId=&core+1 + +RESet +SYStem.CPU S32K566-&cpuName +CORE.ASSIGN &coreId +SYStem.CONFIG.DEBUGPORTTYPE SWD +SYStem.MemAccess DAP +SYStem.JtagClock 10MHz +Trace.DISable +SYStem.Mode.Prepare + +DO ~~/demo/arm/hardware/s32k5/misc/s32k5_init_sram.cmm &sramInitTarget + +IF ("&loadTo"=="mram") +( + Data.LOAD.Elf &elfFile /NoCODE + &image_start = ADDRESS.OFFSET(__rom_region_start) + &image_end = ADDRESS.OFFSET(__rom_region_start)+ADDRESS.OFFSET(_flash_used) + + ; Ensure 4-bit alignment at the end + &image_end=&image_end|0xF + + ; Create image and add IVT header, if not part of the ELF file + Data.Set VM:0x08000000..0x080000FF %Long 0x0 + Data.Set VM:0x08000000 %Long 0x710001D1 ; Magic number + Data.Set VM:0x08000004 %Long 0x031E0000 ; Boot configuration word (enable all M7 and R52) + IF ("&coreType"=="m7") + ( + Data.Set VM:0x08000040+(&core*4) %Long ADDRESS.OFFSET(_vector_start) + ) + ELSE + ( + Data.Set VM:0x08000060+(&core*4) %Long ADDRESS.OFFSET(_vector_start) + ) + + Data.Set VM:&image_start..&image_end %Long 0x0 + + Data.LOAD.Elf &elfFile /VM /NosYmbol + + ; Only declares flash, does not execute flash programming + DO ~~/demo/arm/flash/s32k5.cmm PREPAREONLY + FLASH.Program ALL + + ; Create image and add IVT header + Data.COPY VM:0x08000000..0x080000FF EAXI:0x08000000 /Quad + Data.COPY VM:&image_start..&image_end EAXI:&image_start /Quad + + FLASH.Program OFF + + ; Reset the processor + SYStem.Up + IF ("&coreType"=="r52") + ( + ; CPE.GPR Thumb bit is enabled after reset + R.S T 0 + ) +) +ELSE +( + Data.LOAD.Elf &elfFile +) + +IF ("&command"=="flash") +( + ; Execute the application and quit + Go + QUIT +) +ELSE +( + ; Setup minimal debug environment + WinCLEAR + SETUP.Var.%SpotLight + WinPOS 0. 0. 120. 30. + List.auto + WinPOS 125. 0. 80. 10. + Frame.view + WinPOS 125. 18. + Register.view /SpotLight +) + +ENDDO diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.dts b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.dts index e38e8b51792e..f40fe20d877f 100644 --- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.dts +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.dts @@ -5,7 +5,7 @@ */ /dts-v1/; -#include +#include #include "s32z2xxdc2_s32z270.dtsi" / { diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.dts b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.dts index f8792f880f35..960ed341ec65 100644 --- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.dts +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.dts @@ -5,7 +5,7 @@ */ /dts-v1/; -#include +#include #include "s32z2xxdc2_s32z270.dtsi" / { diff --git a/boards/nxp/twr_ke18f/twr_ke18f.dts b/boards/nxp/twr_ke18f/twr_ke18f.dts index 070bc52b55f2..fbdb74efb406 100644 --- a/boards/nxp/twr_ke18f/twr_ke18f.dts +++ b/boards/nxp/twr_ke18f/twr_ke18f.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include #include #include "twr_ke18f-pinctrl.dtsi" diff --git a/boards/nxp/twr_kv58f220m/twr_kv58f220m.dts b/boards/nxp/twr_kv58f220m/twr_kv58f220m.dts index 4af2188aef3a..2b66eb5e6071 100644 --- a/boards/nxp/twr_kv58f220m/twr_kv58f220m.dts +++ b/boards/nxp/twr_kv58f220m/twr_kv58f220m.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "twr_kv58f220m-pinctrl.dtsi" #include @@ -137,14 +137,14 @@ reg = <0x00010000 DT_SIZE_K(424)>; }; - slot1_partition: partition@7A000 { + slot1_partition: partition@7a000 { label = "image-1"; - reg = <0x0007A000 DT_SIZE_K(424)>; + reg = <0x0007a000 DT_SIZE_K(424)>; }; - storage_partition: partition@E4000 { + storage_partition: partition@e4000 { label = "storage"; - reg = <0x000E4000 DT_SIZE_K(112)>; + reg = <0x000e4000 DT_SIZE_K(112)>; }; }; }; diff --git a/boards/nxp/ucans32k1sic/doc/index.rst b/boards/nxp/ucans32k1sic/doc/index.rst index 9a0ec3adcbbb..d876afb5a803 100644 --- a/boards/nxp/ucans32k1sic/doc/index.rst +++ b/boards/nxp/ucans32k1sic/doc/index.rst @@ -12,18 +12,20 @@ Hardware ******** - NXP S32K146 - - Arm Cortex-M4F @ up to 112 Mhz - - 1 MB Flash - - 128 KB SRAM - - up to 127 I/Os - - 3x FlexCAN with 2x FD - - eDMA, 12-bit ADC, MPU, ECC and more. + + - Arm Cortex-M4F @ up to 112 Mhz + - 1 MB Flash + - 128 KB SRAM + - up to 127 I/Os + - 3x FlexCAN with 2x FD + - eDMA, 12-bit ADC, MPU, ECC and more. - Interfaces: - - DCD-LZ debug interface with SWD + Console / UART - - Dual CAN FD PHYs with dual connectors for daisy chain operation - - JST-GH DroneCode compliant standard connectors and I/O headers - - user RGB LED and button. + + - DCD-LZ debug interface with SWD + Console / UART + - Dual CAN FD PHYs with dual connectors for daisy chain operation + - JST-GH DroneCode compliant standard connectors and I/O headers + - User RGB LED and button. More information about the hardware and design resources can be found at `NXP UCANS32K1SIC`_ website. diff --git a/boards/nxp/ucans32k1sic/ucans32k1sic.dts b/boards/nxp/ucans32k1sic/ucans32k1sic.dts index d86d53b139d5..9aa6b9e18371 100644 --- a/boards/nxp/ucans32k1sic/ucans32k1sic.dts +++ b/boards/nxp/ucans32k1sic/ucans32k1sic.dts @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include "ucans32k1sic-pinctrl.dtsi" / { diff --git a/boards/nxp/usb_kw24d512/usb_kw24d512.dts b/boards/nxp/usb_kw24d512/usb_kw24d512.dts index 5494ddd8f0c3..fbb3b6ad75f7 100644 --- a/boards/nxp/usb_kw24d512/usb_kw24d512.dts +++ b/boards/nxp/usb_kw24d512/usb_kw24d512.dts @@ -1,8 +1,12 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ /dts-v1/; -#include +#include #include "usb_kw24d512-pinctrl.dtsi" #include diff --git a/boards/nxp/vmu_rt1170/CMakeLists.txt b/boards/nxp/vmu_rt1170/CMakeLists.txt index db5f2b91259b..0758d8ca0a4c 100644 --- a/boards/nxp/vmu_rt1170/CMakeLists.txt +++ b/boards/nxp/vmu_rt1170/CMakeLists.txt @@ -10,8 +10,6 @@ if(CONFIG_NXP_IMXRT_BOOT_HEADER) # This flash configuration block may need modification if another # flash chip is used on your custom board. See NXP AN12238 for more # information. - zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) - zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) zephyr_library_sources(flexspi_nor_config.c) zephyr_library_include_directories(xip) endif() diff --git a/boards/nxp/vmu_rt1170/Kconfig.vmu_rt1170 b/boards/nxp/vmu_rt1170/Kconfig.vmu_rt1170 index 081124dd1a82..04413f043eec 100644 --- a/boards/nxp/vmu_rt1170/Kconfig.vmu_rt1170 +++ b/boards/nxp/vmu_rt1170/Kconfig.vmu_rt1170 @@ -1,6 +1,8 @@ +# # Copyright 2023 NXP # SPDX-License-Identifier: Apache-2.0 config BOARD_VMU_RT1170 select SOC_MIMXRT1176_CM7 if BOARD_VMU_RT1170_MIMXRT1176_CM7 + select SOC_MIMXRT1176_CM4 if BOARD_VMU_RT1170_MIMXRT1176_CM4 select SOC_PART_NUMBER_MIMXRT1176DVMAA diff --git a/boards/nxp/vmu_rt1170/vmu_rt1170.dtsi b/boards/nxp/vmu_rt1170/vmu_rt1170.dtsi index a18e6003c996..8dfd33ee932a 100644 --- a/boards/nxp/vmu_rt1170/vmu_rt1170.dtsi +++ b/boards/nxp/vmu_rt1170/vmu_rt1170.dtsi @@ -5,7 +5,7 @@ */ #include "vmu_rt1170-pinctrl.dtsi" -#include +#include / { aliases { diff --git a/boards/nxp/vmu_rt1170/vmu_rt1170_mimxrt1176_cm4.dts b/boards/nxp/vmu_rt1170/vmu_rt1170_mimxrt1176_cm4.dts new file mode 100644 index 000000000000..0dcebe2161be --- /dev/null +++ b/boards/nxp/vmu_rt1170/vmu_rt1170_mimxrt1176_cm4.dts @@ -0,0 +1,42 @@ +/* + * Copyright 2026 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include "vmu_rt1170.dtsi" +#include + +/ { + model = "NXP VMU RT1170 (CM4)"; + compatible = "nxp,mimxrt1176"; + + chosen { + /* Follow mimxrt1170_evk CM4 choices */ + zephyr,sram = &sram1; + zephyr,console = &lpuart1; + zephyr,shell-uart = &lpuart1; + zephyr,canbus = &flexcan2; + zephyr,flash-controller = &mx25um51345g; + zephyr,flash = &ocram_m4_itcm; + nxp,m4-partition = &slot1_partition; + zephyr,ipc = &mailbox_b; + }; +}; + +&lpuart1 { + status = "okay"; + current-speed = <115200>; +}; + +&mailbox_b { + status = "okay"; +}; + +&systick { + status = "okay"; +}; diff --git a/boards/nxp/vmu_rt1170/vmu_rt1170_mimxrt1176_cm4.yaml b/boards/nxp/vmu_rt1170/vmu_rt1170_mimxrt1176_cm4.yaml new file mode 100644 index 000000000000..3f243349cdc8 --- /dev/null +++ b/boards/nxp/vmu_rt1170/vmu_rt1170_mimxrt1176_cm4.yaml @@ -0,0 +1,15 @@ +# +# Copyright 2026 NXP +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: vmu_rt1170/mimxrt1176/cm4 +name: NXP VMU RT1170 (CM4) +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +ram: 128 +flash: 128 +vendor: nxp diff --git a/boards/nxp/vmu_rt1170/vmu_rt1170_mimxrt1176_cm4_defconfig b/boards/nxp/vmu_rt1170/vmu_rt1170_mimxrt1176_cm4_defconfig new file mode 100644 index 000000000000..1304c980270d --- /dev/null +++ b/boards/nxp/vmu_rt1170/vmu_rt1170_mimxrt1176_cm4_defconfig @@ -0,0 +1,11 @@ +# +# Copyright 2026 NXP +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y + +# CM4 core; keep minimal for hello_world. diff --git a/boards/nxp/vmu_rt1170/vmu_rt1170_mimxrt1176_cm7.dts b/boards/nxp/vmu_rt1170/vmu_rt1170_mimxrt1176_cm7.dts index 623ca7c278ba..74e0cf794248 100644 --- a/boards/nxp/vmu_rt1170/vmu_rt1170_mimxrt1176_cm7.dts +++ b/boards/nxp/vmu_rt1170/vmu_rt1170_mimxrt1176_cm7.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include #include "vmu_rt1170.dtsi" #include @@ -525,6 +525,7 @@ &enet1g_phy { status = "okay"; int-gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>; + master-slave = "auto"; }; zephyr_udc0: &usb1 { diff --git a/boards/nxp/vmu_rt1170/xip/evkmimxrt1170_flexspi_nor_config.c b/boards/nxp/vmu_rt1170/xip/evkmimxrt1170_flexspi_nor_config.c index 1b3cffd78e29..3b668f34aa9e 100644 --- a/boards/nxp/vmu_rt1170/xip/evkmimxrt1170_flexspi_nor_config.c +++ b/boards/nxp/vmu_rt1170/xip/evkmimxrt1170_flexspi_nor_config.c @@ -7,7 +7,7 @@ #include "evkmimxrt1170_flexspi_nor_config.h" -#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) __attribute__((section(".boot_hdr.conf"), used)) #define FLASH_DUMMY_CYCLES 0x09 @@ -86,4 +86,4 @@ const flexspi_nor_config_t qspi_flash_config = { .block_size = 64u * 1024u, .is_uniform_block_size = false, }; -#endif /* XIP_BOOT_HEADER_ENABLE */ +#endif /* defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) */ diff --git a/boards/nxp/vmu_rt1170/xip/evkmimxrt1170_flexspi_nor_config.h b/boards/nxp/vmu_rt1170/xip/evkmimxrt1170_flexspi_nor_config.h index 4e8fba474961..95cb2e88240b 100644 --- a/boards/nxp/vmu_rt1170/xip/evkmimxrt1170_flexspi_nor_config.h +++ b/boards/nxp/vmu_rt1170/xip/evkmimxrt1170_flexspi_nor_config.h @@ -113,7 +113,7 @@ enum { FLEXSPI_MISC_OFFSET_SAFE_CONFIG_FREQ_ENABLE = 4, /* Bit for Pad setting override enable */ FLEXSPI_MISC_OFFSET_PAD_SETTING_OVERRIDE_ENABLE = 5, - /* Bit for DDR clock confiuration indication. */ + /* Bit for DDR clock configuration indication. */ FLEXSPI_MISC_OFFSET_DDR_MODE_ENABLE = 6, }; @@ -239,7 +239,7 @@ typedef struct flexspi_config { * 8 - Octal */ uint8_t sflash_pad_type; - /* [0x046-0x046] Serial Flash Frequencey, device specific + /* [0x046-0x046] Serial Flash Frequency, device specific * definitions, See System Boot Chapter for more details */ uint8_t serial_clk_freq; @@ -355,7 +355,7 @@ typedef struct _flexspi_nor_config { uint8_t need_exit_nocmd_mode; /* Half the Serial Clock for non-read command: true/false */ uint8_t half_clk_for_non_read_cmd; - /* Need to Restore NoCmd mode after IP commmand execution */ + /* Need to Restore NoCmd mode after IP command execution */ uint8_t need_restore_nocmd_mode; /* Block size */ uint32_t block_size; diff --git a/boards/olimex/olimex_esp32_evb/support/openocd.cfg b/boards/olimex/olimex_esp32_evb/support/openocd.cfg index 338e6e4e6eae..41411e37140e 100644 --- a/boards/olimex/olimex_esp32_evb/support/openocd.cfg +++ b/boards/olimex/olimex_esp32_evb/support/openocd.cfg @@ -1,5 +1,5 @@ -set ESP_RTOS none -set ESP32_ONLYCPU 1 +set ESP_RTOS Zephyr +set ESP_ONLYCPU 1 source [find interface/ftdi/esp32_devkitj_v1.cfg] source [find target/esp32.cfg] diff --git a/boards/olimex/stm32_e407/olimex_stm32_e407.dts b/boards/olimex/stm32_e407/olimex_stm32_e407.dts index 6bcf16b54faa..3887d4af347f 100644 --- a/boards/olimex/stm32_e407/olimex_stm32_e407.dts +++ b/boards/olimex/stm32_e407/olimex_stm32_e407.dts @@ -18,7 +18,7 @@ zephyr,shell-uart = &usart1; zephyr,sram = &sram0; zephyr,flash = &flash0; - zephyr,ccm = &ccm0; + zephyr,dtcm = &ccm0; }; leds { diff --git a/boards/olimex/stm32_h405/olimex_stm32_h405.dts b/boards/olimex/stm32_h405/olimex_stm32_h405.dts index bdb5e1b588fd..95a4a82defd1 100644 --- a/boards/olimex/stm32_h405/olimex_stm32_h405.dts +++ b/boards/olimex/stm32_h405/olimex_stm32_h405.dts @@ -18,7 +18,7 @@ zephyr,shell-uart = &usart2; zephyr,sram = &sram0; zephyr,flash = &flash0; - zephyr,ccm = &ccm0; + zephyr,dtcm = &ccm0; }; leds { diff --git a/boards/olimex/stm32_h407/olimex_stm32_h407.dts b/boards/olimex/stm32_h407/olimex_stm32_h407.dts index dc2ea9a3c71f..78c5fef78761 100644 --- a/boards/olimex/stm32_h407/olimex_stm32_h407.dts +++ b/boards/olimex/stm32_h407/olimex_stm32_h407.dts @@ -18,7 +18,7 @@ zephyr,shell-uart = &usart2; zephyr,sram = &sram0; zephyr,flash = &flash0; - zephyr,ccm = &ccm0; + zephyr,dtcm = &ccm0; }; leds { diff --git a/boards/olimex/stm32_p405/olimex_stm32_p405.dts b/boards/olimex/stm32_p405/olimex_stm32_p405.dts index 6257a0ee97dc..e69c347f83a3 100644 --- a/boards/olimex/stm32_p405/olimex_stm32_p405.dts +++ b/boards/olimex/stm32_p405/olimex_stm32_p405.dts @@ -18,7 +18,7 @@ zephyr,shell-uart = &usart2; zephyr,sram = &sram0; zephyr,flash = &flash0; - zephyr,ccm = &ccm0; + zephyr,dtcm = &ccm0; zephyr,canbus = &can1; }; diff --git a/boards/openhwgroup/cv32a6_genesys_2/board.cmake b/boards/openhwgroup/cv32a6_genesys_2/board.cmake index 921ea08b8c76..558e77721460 100644 --- a/boards/openhwgroup/cv32a6_genesys_2/board.cmake +++ b/boards/openhwgroup/cv32a6_genesys_2/board.cmake @@ -1,7 +1,7 @@ # Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH # SPDX-License-Identifier: Apache-2.0 board_runner_args(openocd "--config=${BOARD_DIR}/support/ariane.cfg") -board_runner_args(openocd "--use-elf") +board_runner_args(openocd "--file-type=elf") board_runner_args(openocd "--verify") board_runner_args(openocd "--cmd-pre-init=riscv.cpu configure -work-area-phys 0x90000000 -work-area-size 16780000") diff --git a/boards/openhwgroup/cv32a6_genesys_2/board.yml b/boards/openhwgroup/cv32a6_genesys_2/board.yml index 64fbf0833829..2aae44c91914 100644 --- a/boards/openhwgroup/cv32a6_genesys_2/board.yml +++ b/boards/openhwgroup/cv32a6_genesys_2/board.yml @@ -2,6 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 board: name: cv32a6_genesys_2 + full_name: Digilent CV32A6 on Genesys 2 vendor: openhwgroup socs: - name: cv32a6 diff --git a/boards/openhwgroup/cv64a6_genesys_2/Kconfig.cv64a6_genesys_2 b/boards/openhwgroup/cv64a6_genesys_2/Kconfig.cv64a6_genesys_2 index 1a983093e994..fd698942dcca 100644 --- a/boards/openhwgroup/cv64a6_genesys_2/Kconfig.cv64a6_genesys_2 +++ b/boards/openhwgroup/cv64a6_genesys_2/Kconfig.cv64a6_genesys_2 @@ -1,4 +1,4 @@ # Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH # SPDX-License-Identifier: Apache-2.0 config BOARD_CV64A6_GENESYS_2 - select SOC_CV64A6_IMAFDC + select SOC_CV64A6 diff --git a/boards/openhwgroup/cv64a6_genesys_2/board.cmake b/boards/openhwgroup/cv64a6_genesys_2/board.cmake index 921ea08b8c76..558e77721460 100644 --- a/boards/openhwgroup/cv64a6_genesys_2/board.cmake +++ b/boards/openhwgroup/cv64a6_genesys_2/board.cmake @@ -1,7 +1,7 @@ # Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH # SPDX-License-Identifier: Apache-2.0 board_runner_args(openocd "--config=${BOARD_DIR}/support/ariane.cfg") -board_runner_args(openocd "--use-elf") +board_runner_args(openocd "--file-type=elf") board_runner_args(openocd "--verify") board_runner_args(openocd "--cmd-pre-init=riscv.cpu configure -work-area-phys 0x90000000 -work-area-size 16780000") diff --git a/boards/openhwgroup/cv64a6_genesys_2/board.yml b/boards/openhwgroup/cv64a6_genesys_2/board.yml index 293fab13c58f..70b0a877748f 100644 --- a/boards/openhwgroup/cv64a6_genesys_2/board.yml +++ b/boards/openhwgroup/cv64a6_genesys_2/board.yml @@ -2,6 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 board: name: cv64a6_genesys_2 + full_name: Digilent CV64A6 on Genesys 2 vendor: openhwgroup socs: - - name: cv64a6_imafdc + - name: cv64a6 diff --git a/boards/openhwgroup/cv64a6_genesys_2/doc/index.rst b/boards/openhwgroup/cv64a6_genesys_2/doc/index.rst index 090332078de7..48acc5f18ac2 100644 --- a/boards/openhwgroup/cv64a6_genesys_2/doc/index.rst +++ b/boards/openhwgroup/cv64a6_genesys_2/doc/index.rst @@ -44,7 +44,7 @@ Loading the FPGA configuration You need to build a bitstream with Xilinx Vivado and load it into the FPGA before you can load zephyr onto the board. Please refer to the CVA6 documentation for the required steps. -This configuration is compatible with the following build target: cv64a6_imafdc_sv39 +This configuration is compatible with the following build target: cv64a6_sv39 Flashing ======== diff --git a/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_ri5cy.dts b/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_ri5cy.dts index e3c4f20166f5..a2aa5736737d 100644 --- a/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_ri5cy.dts +++ b/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_ri5cy.dts @@ -59,7 +59,7 @@ boot_partition: partition@f4000 { label = "mcuboot"; - reg = <0x000f4000 0x0000C000>; + reg = <0x000f4000 0x0000c000>; }; }; }; diff --git a/boards/others/black_f407ve/black_f407ve.dts b/boards/others/black_f407ve/black_f407ve.dts index 1026096069d0..83e843cde303 100644 --- a/boards/others/black_f407ve/black_f407ve.dts +++ b/boards/others/black_f407ve/black_f407ve.dts @@ -18,7 +18,7 @@ zephyr,shell-uart = &usart1; zephyr,sram = &sram0; zephyr,flash = &flash0; - zephyr,ccm = &ccm0; + zephyr,dtcm = &ccm0; zephyr,canbus = &can2; }; diff --git a/boards/others/black_f407ve/doc/index.rst b/boards/others/black_f407ve/doc/index.rst index b15012459fcd..cc3b7dc1f3fb 100644 --- a/boards/others/black_f407ve/doc/index.rst +++ b/boards/others/black_f407ve/doc/index.rst @@ -13,13 +13,13 @@ Here are some highlights of the BLACK_F407VE board: board and easy probing - Flexible board power supply: - - USB VBUS or external source (3.3V, 5V) - - Power management access point + - USB VBUS or external source (3.3V, 5V) + - Power management access point - Three LEDs: - - 3.3 V power on (LD0) - - Two user LEDs: green (LD1), green (LD2) + - 3.3 V power on (LD0) + - Two user LEDs: green (LD1), green (LD2) - Four push-buttons: RESET, K0, K1 and WK_UP - Mini-AB connector @@ -39,7 +39,7 @@ Hardware BLACK_F407VE board provides the following hardware components: - STM32F407VET6 in LQFP100 package -- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU +- ARM® 32-bit Cortex®-M4 CPU with FPU - 168 MHz max CPU frequency - VDD from 1.8 V to 3.6 V - 8MHz system crystal @@ -76,7 +76,7 @@ BLACK_F407VE board provides the following hardware components: - Dimensions: 85.1mm x 72.45mm More information about STM32F407VE SOC can be found here: - - `STM32F407VE on www.st.com`_ +- `STM32F407VE on www.st.com`_ Supported Features ================== diff --git a/boards/others/black_f407zg_pro/black_f407zg_pro.dts b/boards/others/black_f407zg_pro/black_f407zg_pro.dts index 0673d17c38de..9d224a47e35e 100644 --- a/boards/others/black_f407zg_pro/black_f407zg_pro.dts +++ b/boards/others/black_f407zg_pro/black_f407zg_pro.dts @@ -18,7 +18,7 @@ zephyr,shell-uart = &usart2; zephyr,sram = &sram0; zephyr,flash = &flash0; - zephyr,ccm = &ccm0; + zephyr,dtcm = &ccm0; zephyr,canbus = &can2; }; diff --git a/boards/others/black_f407zg_pro/doc/index.rst b/boards/others/black_f407zg_pro/doc/index.rst index db45dd7b539f..23fce38c70e5 100644 --- a/boards/others/black_f407zg_pro/doc/index.rst +++ b/boards/others/black_f407zg_pro/doc/index.rst @@ -13,13 +13,13 @@ Here are some highlights of the BLACK_F407ZG_PRO board: board and easy probing - Flexible board power supply: - - USB VBUS or external source (3.3V, 5V) - - Power management access point + - USB VBUS or external source (3.3V, 5V) + - Power management access point - Three LEDs: - - 3.3 V power on (LD0) - - Two user LEDs: green (LD1), green (LD2) + - 3.3 V power on (LD0) + - Two user LEDs: green (LD1), green (LD2) - Four push-buttons: RESET, K0, K1 and WK_UP - Mini-AB connector @@ -36,7 +36,7 @@ Hardware BLACK_F407ZG_PRO board provides the following hardware components: - STM32F407ZGT6 in LQFP144 package -- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU +- ARM® 32-bit Cortex®-M4 CPU with FPU - 168 MHz max CPU frequency - VDD from 1.8 V to 3.6 V - 8MHz system crystal @@ -73,7 +73,7 @@ BLACK_F407ZG_PRO board provides the following hardware components: - Dimensions: 102.5mm x 74.56mm More information about STM32F407ZG SOC can be found here: - - `STM32F407ZG on www.st.com`_ +- `STM32F407ZG on www.st.com`_ Supported Features ================== diff --git a/boards/others/doit_esp32_devkit_v1/support/openocd.cfg b/boards/others/doit_esp32_devkit_v1/support/openocd.cfg index 338e6e4e6eae..41411e37140e 100644 --- a/boards/others/doit_esp32_devkit_v1/support/openocd.cfg +++ b/boards/others/doit_esp32_devkit_v1/support/openocd.cfg @@ -1,5 +1,5 @@ -set ESP_RTOS none -set ESP32_ONLYCPU 1 +set ESP_RTOS Zephyr +set ESP_ONLYCPU 1 source [find interface/ftdi/esp32_devkitj_v1.cfg] source [find target/esp32.cfg] diff --git a/boards/others/esp32c3_lckfb/Kconfig b/boards/others/esp32c3_lckfb/Kconfig new file mode 100644 index 000000000000..6a4f947820a6 --- /dev/null +++ b/boards/others/esp32c3_lckfb/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2025 LCKFB +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 diff --git a/boards/others/esp32c3_lckfb/Kconfig.esp32c3_lckfb b/boards/others/esp32c3_lckfb/Kconfig.esp32c3_lckfb new file mode 100644 index 000000000000..0e674285c1c3 --- /dev/null +++ b/boards/others/esp32c3_lckfb/Kconfig.esp32c3_lckfb @@ -0,0 +1,7 @@ +# ESP32C3 LCKFB board configuration +# +# Copyright (c) 2025 LCKFB +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ESP32C3_LCKFB + select SOC_ESP32C3 diff --git a/boards/others/esp32c3_lckfb/Kconfig.sysbuild b/boards/others/esp32c3_lckfb/Kconfig.sysbuild new file mode 100644 index 000000000000..72e00d39b797 --- /dev/null +++ b/boards/others/esp32c3_lckfb/Kconfig.sysbuild @@ -0,0 +1,10 @@ +# Copyright (c) 2025 LCKFB +# SPDX-License-Identifier: Apache-2.0 + +choice BOOTLOADER + default BOOTLOADER_MCUBOOT +endchoice + +choice BOOT_SIGNATURE_TYPE + default BOOT_SIGNATURE_TYPE_NONE +endchoice diff --git a/boards/espressif/esp32s3_devkitm/board.cmake b/boards/others/esp32c3_lckfb/board.cmake similarity index 100% rename from boards/espressif/esp32s3_devkitm/board.cmake rename to boards/others/esp32c3_lckfb/board.cmake diff --git a/boards/others/esp32c3_lckfb/board.yml b/boards/others/esp32c3_lckfb/board.yml new file mode 100644 index 000000000000..7f6e8471fee5 --- /dev/null +++ b/boards/others/esp32c3_lckfb/board.yml @@ -0,0 +1,6 @@ +board: + name: esp32c3_lckfb + full_name: ESP32-C3 Development Board (LCKFB) + vendor: others + socs: + - name: esp32c3 diff --git a/boards/others/esp32c3_lckfb/doc/img/esp32c3_lckfb.webp b/boards/others/esp32c3_lckfb/doc/img/esp32c3_lckfb.webp new file mode 100644 index 000000000000..4bee856646a3 Binary files /dev/null and b/boards/others/esp32c3_lckfb/doc/img/esp32c3_lckfb.webp differ diff --git a/boards/others/esp32c3_lckfb/doc/index.rst b/boards/others/esp32c3_lckfb/doc/index.rst new file mode 100644 index 000000000000..051764d87d40 --- /dev/null +++ b/boards/others/esp32c3_lckfb/doc/index.rst @@ -0,0 +1,52 @@ +.. zephyr:board:: esp32c3_lckfb + +Overview +******** + +The LCKFB ESP32-C3 is a feature-rich development board built around the ESP32-C3 SoC with 8 MB of onboard SPI flash. It offers full Wi-Fi and Bluetooth Low Energy connectivity, complemented by a comprehensive set of sensors, audio capabilities, and display interfaces. + +The board is designed for IoT applications requiring motion sensing, environmental monitoring, +audio processing, and graphical display capabilities. + +For more information, check `LCKFB ESP32-C3 Development Board`_. + +Hardware +******** + +.. include:: ../../../espressif/common/soc-esp32c3-features.rst + :start-after: espressif-soc-esp32c3-features + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +System Requirements +******************* + +.. include:: ../../../espressif/common/system-requirements.rst + :start-after: espressif-system-requirements + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +.. include:: ../../../espressif/common/building-flashing.rst + :start-after: espressif-building-flashing + +.. include:: ../../../espressif/common/board-variants.rst + :start-after: espressif-board-variants + +Debugging +========= + +.. include:: ../../../espressif/common/openocd-debugging.rst + :start-after: espressif-openocd-debugging + +References +********** + +.. target-notes:: + +.. _`LCKFB ESP32-C3 Development Board`: https://wiki.lckfb.com/zh-hans/szpi-esp32c3/ diff --git a/boards/others/esp32c3_lckfb/esp32c3_lckfb-pinctrl.dtsi b/boards/others/esp32c3_lckfb/esp32c3_lckfb-pinctrl.dtsi new file mode 100644 index 000000000000..85a5a184a530 --- /dev/null +++ b/boards/others/esp32c3_lckfb/esp32c3_lckfb-pinctrl.dtsi @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2025 LCKFB + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +&pinctrl { + uart0_default: uart0_default { + group1 { + pinmux = ; + output-high; + }; + + group2 { + pinmux = ; + bias-pull-up; + }; + }; + + spim2_default: spim2_default { + group1 { + pinmux = , + ; + }; + + group2 { + pinmux = ; + output-low; + }; + }; + + i2c0_default: i2c0_default { + group1 { + pinmux = , + ; + bias-pull-up; + drive-open-drain; + output-high; + }; + }; + + i2s_default: i2s_default { + group1 { + pinmux = , + , + ; + }; + }; +}; diff --git a/boards/others/esp32c3_lckfb/esp32c3_lckfb.dts b/boards/others/esp32c3_lckfb/esp32c3_lckfb.dts new file mode 100644 index 000000000000..8a050dc62123 --- /dev/null +++ b/boards/others/esp32c3_lckfb/esp32c3_lckfb.dts @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2025 LCKFB + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "esp32c3_lckfb-pinctrl.dtsi" +#include +#include + +/ { + model = "LCKFB ESP32-C3 Development Board"; + compatible = "espressif,esp32c3"; + + chosen { + zephyr,sram = &sram1; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,bt-hci = &esp32_bt_hci; + }; + + aliases { + sw0 = &user_button1; + i2c-0 = &i2c0; + watchdog0 = &wdt0; + }; + + gpio_keys { + compatible = "gpio-keys"; + + user_button1: button_1 { + label = "User Button"; + gpios = <&gpio0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + }; + }; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&usb_serial { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; +}; + +&i2s { + pinctrl-0 = <&i2s_default>; + pinctrl-names = "default"; +}; + +&trng0 { + status = "okay"; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&timer0 { + status = "disabled"; +}; + +&timer1 { + status = "disabled"; +}; + +&esp32_bt_hci { + status = "okay"; +}; + +&wifi { + status = "okay"; +}; + +/* Override flash size to 8MB + * esp32c3_common.dtsi does not define a default flash size, + * and this board uses 8MB flash, so we need to specify it explicitly. + */ +&flash0 { + reg = <0x0 DT_SIZE_M(8)>; +}; diff --git a/boards/others/esp32c3_lckfb/esp32c3_lckfb.yaml b/boards/others/esp32c3_lckfb/esp32c3_lckfb.yaml new file mode 100644 index 000000000000..f3c6245be69c --- /dev/null +++ b/boards/others/esp32c3_lckfb/esp32c3_lckfb.yaml @@ -0,0 +1,21 @@ +identifier: esp32c3_lckfb +name: ESP32-C3 (LCKFB) +type: mcu +arch: riscv +toolchain: + - zephyr +supported: + - adc + - gpio + - i2c + - i2s + - watchdog + - uart + - dma + - pwm + - spi + - counter + - entropy + - crypto + - retained_mem +vendor: others diff --git a/boards/others/esp32c3_lckfb/esp32c3_lckfb_defconfig b/boards/others/esp32c3_lckfb/esp32c3_lckfb_defconfig new file mode 100644 index 000000000000..187793c76e8c --- /dev/null +++ b/boards/others/esp32c3_lckfb/esp32c3_lckfb_defconfig @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y diff --git a/boards/others/esp32c3_lckfb/support/openocd.cfg b/boards/others/esp32c3_lckfb/support/openocd.cfg new file mode 100644 index 000000000000..6aed93913348 --- /dev/null +++ b/boards/others/esp32c3_lckfb/support/openocd.cfg @@ -0,0 +1,11 @@ +set ESP_RTOS Zephyr + +# ESP32C3 has built-in JTAG interface over USB port in pins GPIO18/GPIO19 (D-/D+). +# Uncomment the line below to enable USB debugging. +# source [find interface/esp_usb_jtag.cfg] + +# Otherwise, use external JTAG programmer as ESP-Prog +source [find interface/ftdi/esp32_devkitj_v1.cfg] + +source [find target/esp32c3.cfg] +adapter speed 5000 diff --git a/boards/others/esp32c3_supermini/support/openocd.cfg b/boards/others/esp32c3_supermini/support/openocd.cfg index 7fa9d1362475..540169f08ba5 100644 --- a/boards/others/esp32c3_supermini/support/openocd.cfg +++ b/boards/others/esp32c3_supermini/support/openocd.cfg @@ -1,7 +1,7 @@ # Copyright (c) 2024 Arrel Neumiller # SPDX-License-Identifier: Apache-2.0 -set ESP_RTOS none +set ESP_RTOS Zephyr # ESP32C3 has built-in JTAG interface over USB port in pins GPIO18/GPIO19 (D-/D+). # Uncomment the line below to enable USB debugging. diff --git a/boards/others/icev_wireless/support/openocd.cfg b/boards/others/icev_wireless/support/openocd.cfg index 7421637880c7..cf1bc91bbf9f 100644 --- a/boards/others/icev_wireless/support/openocd.cfg +++ b/boards/others/icev_wireless/support/openocd.cfg @@ -1,4 +1,4 @@ -set ESP_RTOS none +set ESP_RTOS Zephyr source [find interface/esp_usb_jtag.cfg] diff --git a/boards/others/neorv32/Kconfig b/boards/others/neorv32/Kconfig deleted file mode 100644 index 816f2ae1543c..000000000000 --- a/boards/others/neorv32/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright (c) 2021,2025 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NEORV32_NEORV32_MINIMALBOOT - -config BOARD_NEORV32 - select RISCV_ISA_RV32I - -endif # BOARD_NEORV32_NEORV32_MINIMALBOOT - -if BOARD_NEORV32_NEORV32_UP5KDEMO - -config BOARD_NEORV32 - select RISCV_ISA_RV32I - select RISCV_ISA_EXT_M - -endif # BOARD_NEORV32_NEORV32_UP5KDEMO diff --git a/boards/others/neorv32/board.cmake b/boards/others/neorv32/board.cmake index 56bb9fc1a380..cfcc885b896b 100644 --- a/boards/others/neorv32/board.cmake +++ b/boards/others/neorv32/board.cmake @@ -1,7 +1,7 @@ # Copyright (c) 2021,2025 Henrik Brix Andersen # SPDX-License-Identifier: Apache-2.0 -board_runner_args(openocd "--use-elf" "--cmd-reset-halt" "halt") +board_runner_args(openocd "--file-type=elf" "--cmd-reset-halt" "halt") include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) if("${BOARD_QUALIFIERS}" STREQUAL "/neorv32") diff --git a/boards/others/neorv32/doc/index.rst b/boards/others/neorv32/doc/index.rst index 62e78d1ef592..731fc5521529 100644 --- a/boards/others/neorv32/doc/index.rst +++ b/boards/others/neorv32/doc/index.rst @@ -53,8 +53,8 @@ enabled: - Zicsr (Control and Status Register (CSR) Instructions, always enabled) - Zifencei (Instruction-fetch fence, always enabled) -Other supported RISC-V ISA extensions must be enabled via Kconfig on the board level, and the -``riscv,isa`` devicetree property of the ``cpu0`` node must be set accordingly. +Other supported RISC-V ISA extensions can be enabled by changing the ``riscv,isa-extensions`` +devicetree property of the ``cpu0`` node accordingly. Core Local Interruptor ====================== diff --git a/boards/others/neorv32/neorv32_neorv32_minimalboot.dts b/boards/others/neorv32/neorv32_neorv32_minimalboot.dts index 690a5b16c465..3f445a12f5bb 100644 --- a/boards/others/neorv32/neorv32_neorv32_minimalboot.dts +++ b/boards/others/neorv32/neorv32_neorv32_minimalboot.dts @@ -109,7 +109,8 @@ }; &cpu0 { - riscv,isa = "rv32i_zicsr_zifencei"; + riscv,isa-base = "rv32i"; + riscv,isa-extensions = "i", "zicsr", "zifencei"; }; &bootrom { diff --git a/boards/others/neorv32/neorv32_neorv32_up5kdemo.dts b/boards/others/neorv32/neorv32_neorv32_up5kdemo.dts index 96f0546bcfae..a40a12715b0a 100644 --- a/boards/others/neorv32/neorv32_neorv32_up5kdemo.dts +++ b/boards/others/neorv32/neorv32_neorv32_up5kdemo.dts @@ -109,7 +109,8 @@ }; &cpu0 { - riscv,isa = "rv32im_zicsr_zifencei"; + riscv,isa-base = "rv32i"; + riscv,isa-extensions = "i", "m", "zicsr", "zifencei"; }; &bootrom { diff --git a/boards/others/stm32f401_mini/doc/index.rst b/boards/others/stm32f401_mini/doc/index.rst index e007f48c6941..5d0bffcfb4a2 100644 --- a/boards/others/stm32f401_mini/doc/index.rst +++ b/boards/others/stm32f401_mini/doc/index.rst @@ -14,7 +14,7 @@ The STM32F401CC based board provides the following hardware components: - STM32F401CCU6 in UFQFPN48 package -- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU +- ARM® 32-bit Cortex®-M4 CPU with FPU - 84 MHz max CPU frequency - VDD from 1.7 V to 3.6 V - 256 KB Flash diff --git a/boards/panasonic/pan1770_evb/pan1770_evb.dts b/boards/panasonic/pan1770_evb/pan1770_evb.dts index fa2fd75e6cc5..9ce07b12ac45 100644 --- a/boards/panasonic/pan1770_evb/pan1770_evb.dts +++ b/boards/panasonic/pan1770_evb/pan1770_evb.dts @@ -265,12 +265,12 @@ arduino_spi: &spi3 { boot_partition: partition@0 { label = "mcuboot"; - reg = <0x000000000 0x0000C000>; + reg = <0x000000000 0x0000c000>; }; slot0_partition: partition@c000 { label = "image-0"; - reg = <0x0000C000 0x00067000>; + reg = <0x0000c000 0x00067000>; }; slot1_partition: partition@73000 { diff --git a/boards/panasonic/pan1780_evb/pan1780_evb.dts b/boards/panasonic/pan1780_evb/pan1780_evb.dts index 27cfc4208e31..72585a723f36 100644 --- a/boards/panasonic/pan1780_evb/pan1780_evb.dts +++ b/boards/panasonic/pan1780_evb/pan1780_evb.dts @@ -265,12 +265,12 @@ arduino_spi: &spi3 { boot_partition: partition@0 { label = "mcuboot"; - reg = <0x000000000 0x0000C000>; + reg = <0x000000000 0x0000c000>; }; slot0_partition: partition@c000 { label = "image-0"; - reg = <0x0000C000 0x00067000>; + reg = <0x0000c000 0x00067000>; }; slot1_partition: partition@73000 { diff --git a/boards/panasonic/pan1782_evb/pan1782_evb.dts b/boards/panasonic/pan1782_evb/pan1782_evb.dts index 7186348edd5a..f9b027606ef5 100644 --- a/boards/panasonic/pan1782_evb/pan1782_evb.dts +++ b/boards/panasonic/pan1782_evb/pan1782_evb.dts @@ -191,27 +191,27 @@ arduino_spi: &spi3 { boot_partition: partition@0 { label = "mcuboot"; - reg = <0x000000000 0xC000>; + reg = <0x000000000 0xc000>; }; slot0_partition: partition@c000 { label = "image-0"; - reg = <0x0000C000 0x32000>; + reg = <0x0000c000 0x32000>; }; slot1_partition: partition@3e000 { label = "image-1"; - reg = <0x0003E000 0x32000>; + reg = <0x0003e000 0x32000>; }; scratch_partition: partition@70000 { label = "image-scratch"; - reg = <0x00070000 0xA000>; + reg = <0x00070000 0xa000>; }; storage_partition: partition@7a000 { label = "storage"; - reg = <0x0007A000 0x00006000>; + reg = <0x0007a000 0x00006000>; }; }; }; diff --git a/boards/panasonic/pan1783/pan1783_nrf5340_cpunet_common.dtsi b/boards/panasonic/pan1783/pan1783_nrf5340_cpunet_common.dtsi index f75e5aa0ea7c..f25de361d20c 100644 --- a/boards/panasonic/pan1783/pan1783_nrf5340_cpunet_common.dtsi +++ b/boards/panasonic/pan1783/pan1783_nrf5340_cpunet_common.dtsi @@ -185,6 +185,7 @@ arduino_spi: &spi0 { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + ranges; boot_partition: partition@0 { label = "mcuboot"; @@ -193,7 +194,7 @@ arduino_spi: &spi0 { slot0_partition: partition@c000 { label = "image-0"; - reg = <0x0000C000 0x17000>; + reg = <0x0000c000 0x17000>; }; slot1_partition: partition@23000 { diff --git a/boards/panasonic/panb611evb/panb611evb_nrf54l15_cpuapp.dts b/boards/panasonic/panb611evb/panb611evb_nrf54l15_cpuapp.dts index 25b838667289..f7b9b478e9af 100644 --- a/boards/panasonic/panb611evb/panb611evb_nrf54l15_cpuapp.dts +++ b/boards/panasonic/panb611evb/panb611evb_nrf54l15_cpuapp.dts @@ -20,4 +20,4 @@ }; /* Include default memory partition configuration file */ -#include +#include diff --git a/boards/panasonic/panb611evb/panb611evb_nrf54l15_cpuapp_ns.dts b/boards/panasonic/panb611evb/panb611evb_nrf54l15_cpuapp_ns.dts index cebc30ff0899..301c2c990444 100644 --- a/boards/panasonic/panb611evb/panb611evb_nrf54l15_cpuapp_ns.dts +++ b/boards/panasonic/panb611evb/panb611evb_nrf54l15_cpuapp_ns.dts @@ -8,7 +8,7 @@ #define USE_NON_SECURE_ADDRESS_MAP 1 -#include +#include #include "panb611evb_nrf54l15_cpuapp_common.dtsi" / { @@ -28,35 +28,6 @@ }; }; -/ { - /* - * Default SRAM planning when building for nRF54L15 with ARM TrustZone-M support - * - Lowest 80 kB SRAM allocated to Secure image (sram0_s). - * - Upper 80 kB SRAM allocated to Non-Secure image (sram0_ns). - * - * nRF54L15 has 256 kB of volatile memory (SRAM) but the last 96kB are reserved for - * the FLPR MCU. - * This static layout needs to be the same with the upstream TF-M layout in the - * header flash_layout.h of the relevant platform. Any updates in the layout - * needs to happen both in the flash_layout.h and in this file at the same time. - */ - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram0_s: image_s@20000000 { - /* Secure image memory */ - reg = <0x20000000 DT_SIZE_K(80)>; - }; - - sram0_ns: image_ns@20014000 { - /* Non-Secure image memory */ - reg = <0x20014000 DT_SIZE_K(80)>; - }; - }; -}; - &uart20 { /* Disable so that TF-M can use this UART */ status = "disabled"; @@ -68,4 +39,4 @@ }; /* Include default memory partition configuration file */ -#include +#include diff --git a/boards/panasonic/panb611evb/panb611evb_nrf54l15_cpuflpr.dts b/boards/panasonic/panb611evb/panb611evb_nrf54l15_cpuflpr.dts index bd40a2f837be..3dc55b73513d 100644 --- a/boards/panasonic/panb611evb/panb611evb_nrf54l15_cpuflpr.dts +++ b/boards/panasonic/panb611evb/panb611evb_nrf54l15_cpuflpr.dts @@ -33,6 +33,7 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + ranges; cpuflpr_code_partition: partition@0 { label = "image-0"; diff --git a/boards/particle/argon/doc/index.rst b/boards/particle/argon/doc/index.rst index adc9dc6d2a29..0667125f1d46 100644 --- a/boards/particle/argon/doc/index.rst +++ b/boards/particle/argon/doc/index.rst @@ -11,9 +11,9 @@ for programming. It is equipped with a onboard LIPO circuit and conforms to the Adafruit Feather formfactor. -The Particle Argon provides support for the Nordic Semiconductor nRF52840 ARM -|reg| Cortex |reg|-M4F SoC with an integrated 2.4 GHz transceiver supporting -Bluetooth |reg| Low Energy and IEEE |reg| 802.15.4. +The Particle Argon provides support for the Nordic Semiconductor nRF52840 ARM® +Cortex®-M4F SoC with an integrated 2.4 GHz transceiver supporting +Bluetooth® Low Energy and IEEE® 802.15.4. For more information about the Particle Argon board: diff --git a/boards/particle/boron/doc/index.rst b/boards/particle/boron/doc/index.rst index fcdff03cc8fd..789c5ab4a0fd 100644 --- a/boards/particle/boron/doc/index.rst +++ b/boards/particle/boron/doc/index.rst @@ -12,8 +12,8 @@ It is equipped with a onboard LIPO circuit and conforms to the Adafruit Feather formfactor. The Particle Boron board provides support for the Nordic Semiconductor nRF52840 -ARM |reg| Cortex |reg|-M4F SoC with an integrated 2.4 GHz transceiver supporting -Bluetooth |reg| Low Energy and IEEE |reg| 802.15.4. +ARM® Cortex®-M4F SoC with an integrated 2.4 GHz transceiver supporting +Bluetooth® Low Energy and IEEE® 802.15.4. For more information about the Particle Boron board: diff --git a/boards/particle/xenon/doc/index.rst b/boards/particle/xenon/doc/index.rst index 4f6cf37fcf4b..7813180506e0 100644 --- a/boards/particle/xenon/doc/index.rst +++ b/boards/particle/xenon/doc/index.rst @@ -11,8 +11,8 @@ It is equipped with a onboard LIPO circuit and conforms to the Adafruit Feather formfactor. The Particle Xenon board provides support for the Nordic Semiconductor nRF52840 -ARM |reg| Cortex |reg|-M4F SoC with an integrated 2.4 GHz transceiver supporting -Bluetooth |reg| Low Energy and IEEE |reg| 802.15.4. +ARM® Cortex®-M4F SoC with an integrated 2.4 GHz transceiver supporting +Bluetooth® Low Energy and IEEE® 802.15.4. For more information about the Particle Xenon board: diff --git a/boards/pcbcupid/glyph_c6/support/openocd.cfg b/boards/pcbcupid/glyph_c6/support/openocd.cfg index d86a5517a4ca..29d5fac25c5a 100644 --- a/boards/pcbcupid/glyph_c6/support/openocd.cfg +++ b/boards/pcbcupid/glyph_c6/support/openocd.cfg @@ -1,4 +1,4 @@ # ESP32C6 has built-in JTAG interface over USB port in pins GPIO13/GPIO12 (D-/D+). -set ESP_RTOS none +set ESP_RTOS Zephyr source [find board/esp32c6-builtin.cfg] diff --git a/boards/pcbcupid/glyph_h2/Kconfig b/boards/pcbcupid/glyph_h2/Kconfig new file mode 100644 index 000000000000..c96fa92d3431 --- /dev/null +++ b/boards/pcbcupid/glyph_h2/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 diff --git a/boards/pcbcupid/glyph_h2/Kconfig.glyph_h2 b/boards/pcbcupid/glyph_h2/Kconfig.glyph_h2 new file mode 100644 index 000000000000..880d2a0d720c --- /dev/null +++ b/boards/pcbcupid/glyph_h2/Kconfig.glyph_h2 @@ -0,0 +1,9 @@ +# Glyph-H2 board configuration + +# Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd. +# Copyright (c) 2026 Muhammed Asif + +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_GLYPH_H2 + select SOC_ESP32_H2_MINI_H4 diff --git a/boards/pcbcupid/glyph_h2/Kconfig.sysbuild b/boards/pcbcupid/glyph_h2/Kconfig.sysbuild new file mode 100644 index 000000000000..95e4e1d10397 --- /dev/null +++ b/boards/pcbcupid/glyph_h2/Kconfig.sysbuild @@ -0,0 +1,10 @@ +# Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +choice BOOTLOADER + default BOOTLOADER_MCUBOOT +endchoice + +choice BOOT_SIGNATURE_TYPE + default BOOT_SIGNATURE_TYPE_NONE +endchoice diff --git a/boards/pcbcupid/glyph_h2/board.cmake b/boards/pcbcupid/glyph_h2/board.cmake new file mode 100644 index 000000000000..2f04d1fe8861 --- /dev/null +++ b/boards/pcbcupid/glyph_h2/board.cmake @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*") + set(OPENOCD OPENOCD-NOTFOUND) +endif() +find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH) + +include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/pcbcupid/glyph_h2/board.yml b/boards/pcbcupid/glyph_h2/board.yml new file mode 100644 index 000000000000..e2def8ffe04d --- /dev/null +++ b/boards/pcbcupid/glyph_h2/board.yml @@ -0,0 +1,6 @@ +board: + name: glyph_h2 + full_name: Glyph-H2 + vendor: pcbcupid + socs: + - name: esp32h2 diff --git a/boards/pcbcupid/glyph_h2/doc/img/glyph_h2.webp b/boards/pcbcupid/glyph_h2/doc/img/glyph_h2.webp new file mode 100644 index 000000000000..b104572c3175 Binary files /dev/null and b/boards/pcbcupid/glyph_h2/doc/img/glyph_h2.webp differ diff --git a/boards/pcbcupid/glyph_h2/doc/index.rst b/boards/pcbcupid/glyph_h2/doc/index.rst new file mode 100644 index 000000000000..9f44b1800130 --- /dev/null +++ b/boards/pcbcupid/glyph_h2/doc/index.rst @@ -0,0 +1,63 @@ +.. zephyr:board:: glyph_h2 + +Overview +******** + +Glyph-H2 is an entry-level development board based on the ESP32-H2-MINI-1 module, +which integrates Bluetooth® Low Energy (LE) and IEEE 802.15.4 connectivity. It features +the ESP32-H2 SoC — a 32-bit RISC-V core designed for low-power, secure wireless communication, +supporting Bluetooth 5 (LE), Bluetooth Mesh, Thread, Matter, and Zigbee protocols. +This module is ideal for a wide range of low-power IoT applications. + +For details on getting started, check `Glyph-H2`_. + +Hardware +******** + +.. include:: ../../../espressif/common/soc-esp32h2-features.rst + :start-after: espressif-soc-esp32h2-features + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +System Requirements +******************* + +Espressif HAL requires Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +.. include:: ../../../espressif/common/building-flashing.rst + :start-after: espressif-building-flashing + +.. include:: ../../../espressif/common/board-variants.rst + :start-after: espressif-board-variants + +Debugging +========= + +.. include:: ../../../espressif/common/openocd-debugging.rst + :start-after: espressif-openocd-debugging + +References +********** + +.. target-notes:: + +.. _`Glyph-H2`: https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32h2/esp32-h2-devkitm-1/user_guide.html +.. _`ESP32-H2 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf +.. _`ESP32-H2 Technical Reference Manual`: https://www.espressif.com/sites/default/files/documentation/esp32-h2_technical_reference_manual_en.pdf diff --git a/boards/pcbcupid/glyph_h2/glyph_h2-pinctrl.dtsi b/boards/pcbcupid/glyph_h2/glyph_h2-pinctrl.dtsi new file mode 100644 index 000000000000..c03db30a48ff --- /dev/null +++ b/boards/pcbcupid/glyph_h2/glyph_h2-pinctrl.dtsi @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd. + * Copyright (c) 2026 Muhammed Asif + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +&pinctrl { + uart0_default: uart0_default { + group1 { + pinmux = ; + output-high; + }; + + group2 { + pinmux = ; + bias-pull-up; + }; + }; +}; diff --git a/boards/pcbcupid/glyph_h2/glyph_h2.dts b/boards/pcbcupid/glyph_h2/glyph_h2.dts new file mode 100644 index 000000000000..aa3b67cc3190 --- /dev/null +++ b/boards/pcbcupid/glyph_h2/glyph_h2.dts @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd. + * Copyright (c) 2026 Muhammed Asif + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "glyph_h2-pinctrl.dtsi" +#include +#include + +/ { + model = "PCB Cupid Glyph-H2"; + compatible = "pcbcupid,glyph_h2"; + + chosen { + zephyr,sram = &sramhp; + zephyr,console = &usb_serial; + zephyr,shell-uart = &usb_serial; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; + + aliases { + sw0 = &user_button1; + watchdog0 = &wdt0; + led0 = &red_led; + }; + + leds: leds { + compatible = "gpio-leds"; + + red_led: led_0 { + gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; + label = "User LED0"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + user_button1: button_1 { + label = "User SW1"; + gpios = <&gpio0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + }; + }; +}; + +&uart0 { + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&usb_serial { + current-speed = <115200>; + status = "okay"; +}; diff --git a/boards/pcbcupid/glyph_h2/glyph_h2.yaml b/boards/pcbcupid/glyph_h2/glyph_h2.yaml new file mode 100644 index 000000000000..f8eed8736044 --- /dev/null +++ b/boards/pcbcupid/glyph_h2/glyph_h2.yaml @@ -0,0 +1,10 @@ +identifier: glyph_h2/esp32h2 +name: Glyph-H2 +vendor: pcbcupid +type: mcu +arch: riscv +toolchain: + - zephyr +supported: + - gpio + - uart diff --git a/boards/pcbcupid/glyph_h2/glyph_h2_defconfig b/boards/pcbcupid/glyph_h2/glyph_h2_defconfig new file mode 100644 index 000000000000..187793c76e8c --- /dev/null +++ b/boards/pcbcupid/glyph_h2/glyph_h2_defconfig @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y diff --git a/boards/pcbcupid/glyph_h2/support/openocd.cfg b/boards/pcbcupid/glyph_h2/support/openocd.cfg new file mode 100644 index 000000000000..19c9b79ef7e6 --- /dev/null +++ b/boards/pcbcupid/glyph_h2/support/openocd.cfg @@ -0,0 +1,4 @@ +# ESP32H2 has built-in JTAG interface over USB port in pins GPIO26/GPIO27 (D-/D+). +set ESP_RTOS Zephyr + +source [find board/esp32h2-builtin.cfg] diff --git a/boards/phytec/phyboard_atlas/CMakeLists.txt b/boards/phytec/phyboard_atlas/CMakeLists.txt new file mode 100644 index 000000000000..576a480cdaa6 --- /dev/null +++ b/boards/phytec/phyboard_atlas/CMakeLists.txt @@ -0,0 +1,32 @@ +# +# Copyright 2025 PHYTEC America, LLC +# +# SPDX-License-Identifier: Apache-2.0 +# + +if(CONFIG_NXP_IMXRT_BOOT_HEADER) + zephyr_library() + set(RT1170_BOARD_NAME "phycore_rt1170") + + if(CONFIG_BOOT_FLEXSPI_NOR) + zephyr_library_sources(xip/${RT1170_BOARD_NAME}_flexspi_nor_config.c) + zephyr_library_include_directories(xip) + endif() + + if(CONFIG_EXTERNAL_MEM_CONFIG_DATA) + zephyr_library_compile_definitions(XIP_BOOT_HEADER_XMCD_ENABLE=1) + zephyr_library_sources(xmcd/xmcd.c) + else() + if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000) + message(WARNING "You are using SDRAM as RAM but no external memory" + "configuration data (XMCD) is included. This configuration may not boot") + endif() + endif() + +endif() + +if(CONFIG_MCUX_GPT_TIMER) + message(WARNING "You appear to be using the GPT hardware timer. " + "This timer will enable lower power modes, but at the cost of reduced " + "hardware timer resolution") +endif() diff --git a/boards/phytec/phyboard_atlas/Kconfig.defconfig b/boards/phytec/phyboard_atlas/Kconfig.defconfig new file mode 100644 index 000000000000..799a446d568b --- /dev/null +++ b/boards/phytec/phyboard_atlas/Kconfig.defconfig @@ -0,0 +1,37 @@ +# PHYBOARD-ATLAS + +# Copyright (c) 2025 PHYTEC America, LLC +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_PHYBOARD_ATLAS + +if CPU_CORTEX_M7 + +# Use External Memory Configuration Data (XMCD) by default when booting primary core (M7) +config EXTERNAL_MEM_CONFIG_DATA + default y + +config NXP_IMX_EXTERNAL_SDRAM + default y + +configdefault NET_L2_ETHERNET + default y # No cache memory support is required for driver + +endif # CPU_CORTEX_M7 + +if SECOND_CORE_MCUX && CPU_CORTEX_M4 + +config BUILD_OUTPUT_INFO_HEADER + default y + +DT_CHOSEN_IMAGE_M4 = nxp,m4-partition + +# Adjust the offset of the output image if building for RT11xx SOC +config BUILD_OUTPUT_ADJUST_LMA + default "($(dt_chosen_reg_addr_hex,$(DT_CHOSEN_IMAGE_M4)) + \ + $(dt_node_reg_addr_hex,/soc/spi@400cc000,1)) - \ + $(dt_node_reg_addr_hex,/soc/ocram@20200000)" + +endif # SECOND_CORE_MCUX && CPU_CORTEX_M4 + +endif # BOARD_PHYBOARD_ATLAS diff --git a/boards/phytec/phyboard_atlas/Kconfig.phyboard_atlas b/boards/phytec/phyboard_atlas/Kconfig.phyboard_atlas new file mode 100644 index 000000000000..cb3c0a77ff7d --- /dev/null +++ b/boards/phytec/phyboard_atlas/Kconfig.phyboard_atlas @@ -0,0 +1,8 @@ +# +# Copyright 2025 PHYTEC America, LLC +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_PHYBOARD_ATLAS + select SOC_PART_NUMBER_MIMXRT1176DVMAA + select SOC_MIMXRT1176_CM7 if BOARD_PHYBOARD_ATLAS_MIMXRT1176_CM7 diff --git a/boards/phytec/phyboard_atlas/board.cmake b/boards/phytec/phyboard_atlas/board.cmake new file mode 100644 index 000000000000..c2f0b61896bf --- /dev/null +++ b/boards/phytec/phyboard_atlas/board.cmake @@ -0,0 +1,27 @@ +# +# Copyright 2025 PHYTEC America, LLC +# +# SPDX-License-Identifier: Apache-2.0 +# + +if(CONFIG_SOC_MIMXRT1176_CM7 OR CONFIG_SECOND_CORE_MCUX) + board_runner_args(linkserver "--no-reset") + board_runner_args(pyocd "--target=mimxrt1170_cm7") + board_runner_args(jlink "--device=MIMXRT1176xxxA_M7") + board_runner_args(jlink "--no-reset") + + board_runner_args(linkserver "--device=MIMXRT1176xxxxx:MIMXRT1170-EVK") + board_runner_args(linkserver "--core=cm7") +elseif(CONFIG_SOC_MIMXRT1176_CM4) + board_runner_args(pyocd "--target=mimxrt1170_cm4") + # Note: Use J-Link version 7.50 or later. Debugging only supports running + # the CM4 image, since the board’s default boot core is CM7. + board_runner_args(jlink "--device=MIMXRT1176xxxA_M4") + + board_runner_args(linkserver "--device=MIMXRT1176xxxxx:MIMXRT1170-EVK") + board_runner_args(linkserver "--core=cm4") +endif() + +include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/phytec/phyboard_atlas/board.yml b/boards/phytec/phyboard_atlas/board.yml new file mode 100644 index 000000000000..acde92130990 --- /dev/null +++ b/boards/phytec/phyboard_atlas/board.yml @@ -0,0 +1,6 @@ +board: + name: phyboard_atlas + full_name: phyBOARD-Atlas i.MX RT1170 + vendor: phytec + socs: + - name: mimxrt1176 diff --git a/boards/phytec/phyboard_atlas/dcd/dcd.c b/boards/phytec/phyboard_atlas/dcd/dcd.c new file mode 100644 index 000000000000..c8b675eb9a5b --- /dev/null +++ b/boards/phytec/phyboard_atlas/dcd/dcd.c @@ -0,0 +1,887 @@ +/* + * Copyright 2020-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "dcd.h" + +#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) +#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_DEVICE_CONFIGURATION_DATA) +__attribute__((section(".boot_hdr.dcd_data"), used)) + +const uint8_t dcd_data[] = { + /* HEADER */ + /* Tag */ + 0xD2, + /* Image Length */ + 0x04, 0xB8, + /* Version */ + 0x41, + + /* COMMANDS */ + + /* group: 'Imported Commands' */ + /* #1.1-129, command header bytes for merged 'Write - value' command */ + 0xCC, 0x04, 0x0C, 0x04, + /* #1.1, command: write_value, address: + * CCM_CLOCK_ROOT4_CONTROL, + * value: 0x00, 0x703, size: 4 + */ + 0x40, 0xCC, 0x02, 0x00, 0x00, 0x00, 0x07, 0x03, + /* #1.2, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_00, + * value: 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0x10, 0x00, 0x00, 0x00, 0x00, + /* #1.3, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_01, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, + /* #1.4, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_02, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00, + /* #1.5, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_03, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00, + /* #1.6, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_04, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00, + /* #1.7, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_05, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00, + /* #1.8, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_06, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00, + /* #1.9, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_07, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00, + /* #1.10, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_08, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00, + /* #1.11, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_09, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00, + /* #1.12, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_10, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00, + /* #1.13, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_11, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00, + /* #1.14, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_12, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00, + /* #1.15, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_13, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00, + /* #1.16, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_14, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00, + /* #1.17, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_15, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00, + /* #1.18, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_16, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00, + /* #1.19, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_17, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00, + /* #1.20, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_18, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00, + /* #1.21, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_19, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00, + /* #1.22, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_20, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00, + /* #1.23, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_21, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00, + /* #1.24, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_22, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00, + /* #1.25, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_23, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00, + /* #1.26, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_24, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00, + /* #1.27, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_25, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00, + /* #1.28, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_26, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00, + /* #1.29, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_27, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00, + /* #1.30, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_28, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, + /* #1.31, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_29, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00, + /* #1.32, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_30, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00, + /* #1.33, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_31, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00, + /* #1.34, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_32, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00, + /* #1.35, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_33, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00, + /* #1.36, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_34, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00, + /* #1.37, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_35, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00, + /* #1.38, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_36, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00, + /* #1.39, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_37, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00, + /* #1.40, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_38, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00, + /* #1.41, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_39, + * value: 0x00, 0x10, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x10, + /* #1.42, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_00, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0xB8, 0x00, 0x00, 0x00, 0x00, + /* #1.43, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_01, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0xBC, 0x00, 0x00, 0x00, 0x00, + /* #1.44, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_02, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0xC0, 0x00, 0x00, 0x00, 0x00, + /* #1.45, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_03, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0xC4, 0x00, 0x00, 0x00, 0x00, + /* #1.46, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_04, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0xC8, 0x00, 0x00, 0x00, 0x00, + /* #1.47, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_05, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0xCC, 0x00, 0x00, 0x00, 0x00, + /* #1.48, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_06, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0xD0, 0x00, 0x00, 0x00, 0x00, + /* #1.49, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_07, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0xD4, 0x00, 0x00, 0x00, 0x00, + /* #1.50, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_08, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0xD8, 0x00, 0x00, 0x00, 0x00, + /* #1.51, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_09, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0xDC, 0x00, 0x00, 0x00, 0x00, + /* #1.52, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_10, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0xE0, 0x00, 0x00, 0x00, 0x00, + /* #1.53, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_11, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0xE4, 0x00, 0x00, 0x00, 0x00, + /* #1.54, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_12, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0xE8, 0x00, 0x00, 0x00, 0x00, + /* #1.55, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_13, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0xEC, 0x00, 0x00, 0x00, 0x00, + /* #1.56, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_14, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0xF0, 0x00, 0x00, 0x00, 0x00, + /* #1.57, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_15, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0xF4, 0x00, 0x00, 0x00, 0x00, + /* #1.58, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_16, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0xF8, 0x00, 0x00, 0x00, 0x00, + /* #1.59, command: write_value, address: + * IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_17, + * value: 0x00, 0x00, + * size: 4 + */ + 0x40, 0x0E, 0x80, 0xFC, 0x00, 0x00, 0x00, 0x00, + /* #1.60, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_00, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x82, 0x54, 0x00, 0x00, 0x00, 0x08, + /* #1.61, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_01, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x82, 0x58, 0x00, 0x00, 0x00, 0x08, + /* #1.62, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_02, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x82, 0x5C, 0x00, 0x00, 0x00, 0x08, + /* #1.63, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_03, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x82, 0x60, 0x00, 0x00, 0x00, 0x08, + /* #1.64, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_04, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x82, 0x64, 0x00, 0x00, 0x00, 0x08, + /* #1.65, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_05, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x82, 0x68, 0x00, 0x00, 0x00, 0x08, + /* #1.66, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_06, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x82, 0x6C, 0x00, 0x00, 0x00, 0x08, + /* #1.67, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_07, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x82, 0x70, 0x00, 0x00, 0x00, 0x08, + /* #1.68, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_08, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x82, 0x74, 0x00, 0x00, 0x00, 0x08, + /* #1.69, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_09, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x82, 0x78, 0x00, 0x00, 0x00, 0x08, + /* #1.70, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_10, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x82, 0x7C, 0x00, 0x00, 0x00, 0x08, + /* #1.71, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_11, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x82, 0x80, 0x00, 0x00, 0x00, 0x08, + /* #1.72, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_12, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x82, 0x84, 0x00, 0x00, 0x00, 0x08, + /* #1.73, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_13, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x82, 0x88, 0x00, 0x00, 0x00, 0x08, + /* #1.74, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_14, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x82, 0x8C, 0x00, 0x00, 0x00, 0x08, + /* #1.75, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_15, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x82, 0x90, 0x00, 0x00, 0x00, 0x08, + /* #1.76, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_16, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x82, 0x94, 0x00, 0x00, 0x00, 0x08, + /* #1.77, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_17, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x82, 0x98, 0x00, 0x00, 0x00, 0x08, + /* #1.78, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_18, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x82, 0x9C, 0x00, 0x00, 0x00, 0x08, + /* #1.79, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_19, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x82, 0xA0, 0x00, 0x00, 0x00, 0x08, + /* #1.80, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_20, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x82, 0xA4, 0x00, 0x00, 0x00, 0x08, + /* #1.81, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_21, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x82, 0xA8, 0x00, 0x00, 0x00, 0x08, + /* #1.82, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_22, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x82, 0xAC, 0x00, 0x00, 0x00, 0x08, + /* #1.83, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_23, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x82, 0xB0, 0x00, 0x00, 0x00, 0x08, + /* #1.84, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_24, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x82, 0xB4, 0x00, 0x00, 0x00, 0x08, + /* #1.85, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_25, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x82, 0xB8, 0x00, 0x00, 0x00, 0x08, + /* #1.86, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_26, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x82, 0xBC, 0x00, 0x00, 0x00, 0x08, + /* #1.87, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_27, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x82, 0xC0, 0x00, 0x00, 0x00, 0x08, + /* #1.88, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_28, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x82, 0xC4, 0x00, 0x00, 0x00, 0x08, + /* #1.89, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_29, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x82, 0xC8, 0x00, 0x00, 0x00, 0x08, + /* #1.90, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_30, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x82, 0xCC, 0x00, 0x00, 0x00, 0x08, + /* #1.91, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_31, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x82, 0xD0, 0x00, 0x00, 0x00, 0x08, + /* #1.92, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_32, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x82, 0xD4, 0x00, 0x00, 0x00, 0x08, + /* #1.93, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_33, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x82, 0xD8, 0x00, 0x00, 0x00, 0x08, + /* #1.94, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_34, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x82, 0xDC, 0x00, 0x00, 0x00, 0x08, + /* #1.95, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_35, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x82, 0xE0, 0x00, 0x00, 0x00, 0x08, + /* #1.96, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_36, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x82, 0xE4, 0x00, 0x00, 0x00, 0x08, + /* #1.97, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_37, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x82, 0xE8, 0x00, 0x00, 0x00, 0x08, + /* #1.98, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_38, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x82, 0xEC, 0x00, 0x00, 0x00, 0x08, + /* #1.99, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_39, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x82, 0xF0, 0x00, 0x00, 0x00, 0x08, + /* #1.100, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_00, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x82, 0xFC, 0x00, 0x00, 0x00, 0x08, + /* #1.101, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_01, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x83, 0x00, 0x00, 0x00, 0x00, 0x08, + /* #1.102, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_02, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x83, 0x04, 0x00, 0x00, 0x00, 0x08, + /* #1.103, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_03, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x83, 0x08, 0x00, 0x00, 0x00, 0x08, + /* #1.104, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_04, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x83, 0x0C, 0x00, 0x00, 0x00, 0x08, + /* #1.105, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_05, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x83, 0x10, 0x00, 0x00, 0x00, 0x08, + /* #1.106, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_06, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x83, 0x14, 0x00, 0x00, 0x00, 0x08, + /* #1.107, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_07, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x83, 0x18, 0x00, 0x00, 0x00, 0x08, + /* #1.108, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_08, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x83, 0x1C, 0x00, 0x00, 0x00, 0x08, + /* #1.109, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_09, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x83, 0x20, 0x00, 0x00, 0x00, 0x08, + /* #1.110, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_10, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x83, 0x24, 0x00, 0x00, 0x00, 0x08, + /* #1.111, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_11, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x83, 0x28, 0x00, 0x00, 0x00, 0x08, + /* #1.112, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_12, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x83, 0x2C, 0x00, 0x00, 0x00, 0x08, + /* #1.113, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_13, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x83, 0x30, 0x00, 0x00, 0x00, 0x08, + /* #1.114, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_14, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x83, 0x34, 0x00, 0x00, 0x00, 0x08, + /* #1.115, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_15, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x83, 0x38, 0x00, 0x00, 0x00, 0x08, + /* #1.116, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_16, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x83, 0x3C, 0x00, 0x00, 0x00, 0x08, + /* #1.117, command: write_value, address: + * IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_17, + * value: 0x00, 0x08, + * size: 4 + */ + 0x40, 0x0E, 0x83, 0x40, 0x00, 0x00, 0x00, 0x08, + /* #1.118, command: write_value, address: + * SEMC_MCR, + * value: 0x00, 0x10000004, size: 4 + */ + 0x40, 0x0D, 0x40, 0x00, 0x10, 0x00, 0x00, 0x04, + /* #1.119, command: write_value, address: + * SEMC_BMCR0, + * value: 0x00, 0x81, size: 4 + */ + 0x40, 0x0D, 0x40, 0x08, 0x00, 0x00, 0x00, 0x81, + /* #1.120, command: write_value, address: + * SEMC_BMCR1, + * value: 0x00, 0x81, size: 4 + */ + 0x40, 0x0D, 0x40, 0x0C, 0x00, 0x00, 0x00, 0x81, + /* #1.121, command: write_value, address: + * SEMC_BR0, + * value: 0x00, 0x8000001D, size: 4 + */ + 0x40, 0x0D, 0x40, 0x10, 0x80, 0x00, 0x00, 0x1D, + /* #1.122, command: write_value, address: + * SEMC_SDRAMCR0, + * value: 0x00, 0xF32, size: 4 + */ + 0x40, 0x0D, 0x40, 0x40, 0x00, 0x00, 0x0F, 0x32, + /* #1.123, command: write_value, address: + * SEMC_SDRAMCR1, + * value: 0x00, 0x772A22, size: 4 + */ + 0x40, 0x0D, 0x40, 0x44, 0x00, 0x77, 0x2A, 0x22, + /* #1.124, command: write_value, address: + * SEMC_SDRAMCR2, + * value: 0x00, 0x10A0D, size: 4 + */ + 0x40, 0x0D, 0x40, 0x48, 0x00, 0x01, 0x0A, 0x0D, + /* #1.125, command: write_value, address: + * SEMC_SDRAMCR3, + * value: 0x00, 0x21210408, size: 4 + */ + 0x40, 0x0D, 0x40, 0x4C, 0x21, 0x21, 0x04, 0x08, + /* #1.126, command: write_value, address: + * SEMC_IPCR0, + * value: 0x00, 0x80000000, size: 4 + */ + 0x40, 0x0D, 0x40, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #1.127, command: write_value, address: + * SEMC_IPCR1, + * value: 0x00, 0x02, size: 4 + */ + 0x40, 0x0D, 0x40, 0x94, 0x00, 0x00, 0x00, 0x02, + /* #1.128, command: write_value, address: + * SEMC_IPCR2, + * value: 0x00, 0x00, size: 4 + */ + 0x40, 0x0D, 0x40, 0x98, 0x00, 0x00, 0x00, 0x00, + /* #1.129, command: write_value, address: + * SEMC_IPCMD, + * value: 0x00, 0xA55A000F, size: 4 + */ + 0x40, 0x0D, 0x40, 0x9C, 0xA5, 0x5A, 0x00, 0x0F, + /* #2, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #3, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #4, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #5, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #6, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #7.1-2, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x14, 0x04, + /* #7.1, command: write_value, address: + * SEMC_INTR, + * value: 0x00, 0x03, size: 4 + */ + 0x40, 0x0D, 0x40, 0x3C, 0x00, 0x00, 0x00, 0x03, + /* #7.2, command: write_value, address: + * SEMC_IPCMD, + * value: 0x00, 0xA55A000C, size: 4 + */ + 0x40, 0x0D, 0x40, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, + /* #8, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #9, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #10, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #11, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #12, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #13.1-2, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x14, 0x04, + /* #13.1, command: write_value, address: + * SEMC_INTR, + * value: 0x00, 0x03, size: 4 + */ + 0x40, 0x0D, 0x40, 0x3C, 0x00, 0x00, 0x00, 0x03, + /* #13.2, command: write_value, address: + * SEMC_IPCMD, + * value: 0x00, 0xA55A000C, size: 4 + */ + 0x40, 0x0D, 0x40, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, + /* #14, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #15, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #16, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #17, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #18, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #19.1-3, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x1C, 0x04, + /* #19.1, command: write_value, address: + * SEMC_INTR, + * value: 0x00, 0x03, size: 4 + */ + 0x40, 0x0D, 0x40, 0x3C, 0x00, 0x00, 0x00, 0x03, + /* #19.2, command: write_value, address: + * SEMC_IPTXDAT, + * value: 0x00, 0x33, size: 4 + */ + 0x40, 0x0D, 0x40, 0xA0, 0x00, 0x00, 0x00, 0x33, + /* #19.3, command: write_value, address: + * SEMC_IPCMD, + * value: 0x00, 0xA55A000A, size: 4 + */ + 0x40, 0x0D, 0x40, 0x9C, 0xA5, 0x5A, 0x00, 0x0A, + /* #20, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #21, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #22, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #23, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #24, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #25.1-2, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x14, 0x04, + /* #25.1, command: write_value, address: + * SEMC_INTR, + * value: 0x00, 0x03, size: 4 + */ + 0x40, 0x0D, 0x40, 0x3C, 0x00, 0x00, 0x00, 0x03, + /* #25.2, command: write_value, address: + * SEMC_SDRAMCR3, + * value: 0x00, 0x21210409, size: 4 + */ + 0x40, 0x0D, 0x40, 0x4C, 0x21, 0x21, 0x04, 0x09}; +/* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */ + +#else +const uint8_t dcd_data[] = {0x00}; +#endif /* defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_DEVICE_CONFIGURATION_DATA) */ +#endif /* defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) */ diff --git a/boards/phytec/phyboard_atlas/dcd/dcd.h b/boards/phytec/phyboard_atlas/dcd/dcd.h new file mode 100644 index 000000000000..21ba0522bc0d --- /dev/null +++ b/boards/phytec/phyboard_atlas/dcd/dcd.h @@ -0,0 +1,18 @@ +/* + * Copyright 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef DCD_ +#define DCD_ + +#include + +#define DCD_TAG_HEADER (0xD2) +#define DCD_VERSION (0x41) +#define DCD_TAG_HEADER_SHIFT (24) +#define DCD_ARRAY_SIZE 1 + +#endif /* DCD_ */ diff --git a/boards/phytec/phyboard_atlas/doc/img/phyboard_atlas.webp b/boards/phytec/phyboard_atlas/doc/img/phyboard_atlas.webp new file mode 100644 index 000000000000..54954bca017e Binary files /dev/null and b/boards/phytec/phyboard_atlas/doc/img/phyboard_atlas.webp differ diff --git a/boards/phytec/phyboard_atlas/doc/index.rst b/boards/phytec/phyboard_atlas/doc/index.rst new file mode 100644 index 000000000000..e28e88894bb3 --- /dev/null +++ b/boards/phytec/phyboard_atlas/doc/index.rst @@ -0,0 +1,346 @@ +.. zephyr:board:: phyboard_atlas + +Overview +******** + +The PHYTEC phyBOARD-Atlas i.MX RT1170 features the phyCORE-i.MX RT1170 System on +Module. The phyCORE-i.MX RT1170 module is based on the NXP dual core i.MX RT1170 +which runs the Cortex-M7 core at 1 GHz and on the Cortex-M4 at 400 MHz. + +Hardware +******** + +- MIMXRT1176DVMAA MCU + + - 1GHz Cortex-M7 & 400Mhz Cortex-M4 + - 2MB SRAM with 512KB of TCM for Cortex-M7 and 256KB of TCM for Cortex-M4 + +- Memory + + - 512 Mbit SDRAM + - 128 Mbit QSPI Flash + - 512 Mbit Octal Flash + +- Interfaces + + - MicroSD: 1x microSD Card slot + - USB: 2x USB 2.0 OTG + - Ethernet: 1x 10/100/1000BASE-T & 1x 10/100BASE-T (RJ45) + - Expansion: 1x M.2 Connector + - Display: 1x MIPI-DSI + - Camera: 1x MIPI CSI + - Audio: Standard Audio Interface + - Serial: 1x RS232 (2x5 pin header) + 1x RS485 + - UART: 1x via Expansion Interface + - CAN: 1x CAN (2x5 pin header) + - LED: 1x RGB User LED + - Expansion Interface: 60-pin + - Security: OPTIGA™ TPM SLB 9670 TPM 2.0 + - Power Input: USB-C 5V/3A + +- Debug + + - Micro USB serial debug interface + - JTAG: via Expansion Interface + +For more information about phyCORE-i.MX RT1170 & phyBOARD-Atlas i.MX RT1170 +board, see these references: + +- `phyCORE-i.MX RT1170 Product Page`_ +- `phyBOARD-Atlas i.MX RT1170 Product Page`_ + +External Memory +=============== + +This platform has the following external memories: + ++----------------------+------------+-------------------------------------+ +| Device | Controller | Status | ++======================+============+=====================================+ +| MT48LC16M16A2B4-7EIT | SEMC | Enabled via device configuration | +| SDRAM | | data (DCD) block, which sets up | +| | | the SEMC at boot time | ++----------------------+------------+-------------------------------------+ +| MX25U12832FM2I02 | FLEXSPI | Enabled via flash configuration | +| QSPI flash | | block (FCB), which sets up the | +| | | FLEXSPI at boot time. | ++----------------------+------------+-------------------------------------+ + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Connections and I/Os +==================== + +The MIMXRT1170 SoC has six pairs of pinmux/gpio controllers. + ++---------------------------+----------------------+-------------------------------+ +| Name | Function | Usage | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_35 | GPIO | User button | ++---------------------------+----------------------+-------------------------------+ +| GPIO_SNVS_08 | GPIO | Red LED (SOM) | ++---------------------------+----------------------+-------------------------------+ +| GPIO_SNVS_09 | GPIO | Green LED (SOM) | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_14 | GPIO | Red LED (Carrier Board) | ++---------------------------+----------------------+-------------------------------+ +| GPIO_LPSR_13 | GPIO | Green LED (Carrier Board) | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_18 | LPI2C2_SCL | EEPROM | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_19 | LPI2C2_SDA | EEPROM | ++---------------------------+----------------------+-------------------------------+ +| GPIO_LPSR_08 | LPI2C5_SCL | Accelerometer, CODEC, Display | ++---------------------------+----------------------+-------------------------------+ +| GPIO_LPSR_09 | LPI2C5_SDA | Accelerometer, CODEC, Display | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_24 | LPUART1_TX | UART Console (CM7) | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_25 | LPUART1_RX | UART Console (CM7) | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_28 | LPUART5_TX | UART | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_29 | LPUART5_RX | UART | ++---------------------------+----------------------+-------------------------------+ +| GPIO_EMC_B1_40 | LPUART6_TX | UART Console (CM4) | ++---------------------------+----------------------+-------------------------------+ +| GPIO_EMC_B1_41 | LPUART6_RX | UART Console (CM4) | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_00 | CTP_INT | Display | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_01 | CTP_RST_B | Display | ++---------------------------+----------------------+-------------------------------+ +| GPIO_DISP_B2_05 | PWR_EN | Display | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_30 | Backlight_CTL | Display | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_32 | ENET_MDC | Ethernet | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_33 | ENET_MDIO | Ethernet | ++---------------------------+----------------------+-------------------------------+ +| GPIO_DISP_B2_02 | ENET_TX_DATA00 | Ethernet | ++---------------------------+----------------------+-------------------------------+ +| GPIO_DISP_B2_03 | ENET_TX_DATA01 | Ethernet | ++---------------------------+----------------------+-------------------------------+ +| GPIO_DISP_B2_04 | ENET_TX_EN | Ethernet | ++---------------------------+----------------------+-------------------------------+ +| GPIO_DISP_B2_05 | ENET_TX_CLK | Ethernet | ++---------------------------+----------------------+-------------------------------+ +| GPIO_DISP_B2_06 | ENET_RX_DATA00 | Ethernet | ++---------------------------+----------------------+-------------------------------+ +| GPIO_DISP_B2_07 | ENET_RX_DATA01 | Ethernet | ++---------------------------+----------------------+-------------------------------+ +| GPIO_DISP_B2_08 | ENET_RX_EN | Ethernet | ++---------------------------+----------------------+-------------------------------+ +| GPIO_DISP_B2_09 | ENET_RX_ER | Ethernet | ++---------------------------+----------------------+-------------------------------+ +| GPIO_EMC_B2_19 | ENET_RGMII_MDC | Ethernet 1G | ++---------------------------+----------------------+-------------------------------+ +| GPIO_EMC_B2_20 | ENET_RGMII_MDIO | Ethernet 1G | ++---------------------------+----------------------+-------------------------------+ +| GPIO_DISP_B1_09 | ENET_RGMII_TX_DATA00 | Ethernet 1G | ++---------------------------+----------------------+-------------------------------+ +| GPIO_DISP_B1_08 | ENET_RGMII_TX_DATA01 | Ethernet 1G | ++---------------------------+----------------------+-------------------------------+ +| GPIO_DISP_B1_07 | ENET_RGMII_TX_DATA02 | Ethernet 1G | ++---------------------------+----------------------+-------------------------------+ +| GPIO_DISP_B1_06 | ENET_RGMII_TX_DATA03 | Ethernet 1G | ++---------------------------+----------------------+-------------------------------+ +| GPIO_DISP_B1_10 | ENET_RGMII_TX_EN | Ethernet 1G | ++---------------------------+----------------------+-------------------------------+ +| GPIO_DISP_B1_11 | ENET_RGMII_TX_CLK | Ethernet 1G | ++---------------------------+----------------------+-------------------------------+ +| GPIO_DISP_B1_02 | ENET_RGMII_RX_DATA00 | Ethernet 1G | ++---------------------------+----------------------+-------------------------------+ +| GPIO_DISP_B1_03 | ENET_RGMII_RX_DATA01 | Ethernet 1G | ++---------------------------+----------------------+-------------------------------+ +| GPIO_DISP_B1_04 | ENET_RGMII_RX_DATA02 | Ethernet 1G | ++---------------------------+----------------------+-------------------------------+ +| GPIO_DISP_B1_05 | ENET_RGMII_RX_DATA03 | Ethernet 1G | ++---------------------------+----------------------+-------------------------------+ +| GPIO_DISP_B1_00 | ENET_RGMII_RX_EN | Ethernet 1G | ++---------------------------+----------------------+-------------------------------+ +| GPIO_DISP_B1_01 | ENET_RGMII_RX_CLK | Ethernet 1G | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_02 | LPUART8_TX | RS-232 | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_03 | LPUART8_RX | RS-232 | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_04 | LPUART8_CTS | RS-232 | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_05 | LPUART8_RTS | RS-232 | ++---------------------------+----------------------+-------------------------------+ +| GPIO_SD_B2_05 | FLEXSPI1_DQS | Flash Programming | ++---------------------------+----------------------+-------------------------------+ +| GPIO_SD_B2_06 | FLEXSPI1_SS0 | Flash Programming | ++---------------------------+----------------------+-------------------------------+ +| GPIO_SD_B2_07 | FLEXSPI1_SCLK | Flash Programming | ++---------------------------+----------------------+-------------------------------+ +| GPIO_SD_B2_08 | FLEXSPI1_DATA00 | Flash Programming | ++---------------------------+----------------------+-------------------------------+ +| GPIO_SD_B2_09 | FLEXSPI1_DATA01 | Flash Programming | ++---------------------------+----------------------+-------------------------------+ +| GPIO_SD_B2_10 | FLEXSPI1_DATA02 | Flash Programming | ++---------------------------+----------------------+-------------------------------+ +| GPIO_SD_B2_11 | FLEXSPI1_DATA03 | Flash Programming | ++---------------------------+----------------------+-------------------------------+ +| GPIO_LPSR_00 | CAN3_TX | FlexCAN | ++---------------------------+----------------------+-------------------------------+ +| GPIO_LPSR_01 | CAN3_RX | FlexCAN | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_17_SAI1_MCLK | SAI_MCLK | CODEC/SAI | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_20_SAI1_RX_DATA00 | SAI1_RX_DATA00 | CODEC/SAI | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_21_SAI1_TX_DATA00 | SAI1_TX_DATA00 | CODEC/SAI | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_22_SAI1_TX_BCLK | SAI1_TX_BCLK | CODEC/SAI | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_23_SAI1_TX_SYNC | SAI1_TX_SYNC | CODEC/SAI | ++---------------------------+----------------------+-------------------------------+ +| GPIO_SD_B1_00 | USDHC1_CMD | SDHC | ++---------------------------+----------------------+-------------------------------+ +| GPIO_SD_B1_01 | USDHC1_CLK | SDHC | ++---------------------------+----------------------+-------------------------------+ +| GPIO_SD_B1_02 | USDHC1_DATA0 | SDHC | ++---------------------------+----------------------+-------------------------------+ +| GPIO_SD_B1_03 | USDHC1_DATA1 | SDHC | ++---------------------------+----------------------+-------------------------------+ +| GPIO_SD_B1_04 | USDHC1_DATA2 | SDHC | ++---------------------------+----------------------+-------------------------------+ +| GPIO_SD_B1_05 | USDHC1_DATA3 | SDHC | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_09 | USB_OTG1_ID | USB | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_10 | USB_OTG1_PWR | USB | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_11 | USB_OTG1_OC | USB | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_08 | USB_OTG2_ID | USB | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_07 | USB_OTG2_PWR | USB | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_06 | USB_OTG2_OC | USB | ++---------------------------+----------------------+-------------------------------+ + +Dual Core samples +***************** + ++-----------+------------------+------------------+ +| Core | Boot Address | Comment | ++===========+==================+==================+ +| Cortex M7 | 0x30000000[630K] | primary core | ++-----------+------------------+------------------+ +| Cortex M4 | 0x20020000[96k] | boots from OCRAM | ++-----------+------------------+------------------+ + ++----------+------------------+-----------------------+ +| Memory | Address[Size] | Comment | ++==========+==================+=======================+ +| flexspi1 | 0x30000000[16M] | Cortex M7 flash | ++----------+------------------+-----------------------+ +| sdram0 | 0x80030000[64M] | Cortex M7 ram | ++----------+------------------+-----------------------+ +| ocram | 0x20020000[512K] | Cortex M4 "flash" | ++----------+------------------+-----------------------+ +| sram1 | 0x20000000[128K] | Cortex M4 ram | ++----------+------------------+-----------------------+ +| ocram2 | 0x200C0000[512K] | Mailbox/shared memory | ++----------+------------------+-----------------------+ + +Only the first 16K of ocram2 has the correct MPU region attributes set to be +used as shared memory + +System Clock +============ + +The MIMXRT1170 SoC is configured to use SysTick as the system clock source, +running at 996MHz. When targeting the M4 core, SysTick will also be used, +running at 400MHz + +When power management is enabled, the 32 KHz low frequency +oscillator on the board will be used as a source for the GPT timer to +generate a system clock. This clock enables lower power states, at the +cost of reduced resolution + +Serial Port +=========== + +The MIMXRT1170 SoC has 12 UARTs. ``LPUART1`` is configured for the console for +the CM7 and ``LPUART6`` is configured for the console of the CM4. ``LPUART8`` is +configured for RS-232. Remaining are not used. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Console +===================== + +We will use the on-board FTDI UART-to-USB IC that converts the two internal +UARTs to USB (X15). + +Use the following settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: phyboard_atlas/mimxrt1176/cm7 + :goals: flash + +You should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v4.1.0-xxxx-xxxxxxxxxxxxx ***** + Hello World! phyboard_atlas/mimxrt1176/cm7 + +Debugging +========= + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: phyboard_atlas/mimxrt1176/cm7 + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v4.1.0-xxxx-xxxxxxxxxxxxx ***** + Hello World! phyboard_atlas/mimxrt1176/cm7 + +.. note:: + Use J-Link version 7.50 or later. Debugging only supports running the CM4 image, since the board’s default boot core is CM7. + +References +********** + +.. target-notes:: + +.. _phyCORE-i.MX RT1170 Product Page: + https://www.phytec.com/product/phycore-rt1170 + +.. _phyBOARD-Atlas i.MX RT1170 Product Page: + https://www.phytec.com/product/phyboard-rt1170-development-kit/ + +.. _AN13264: + https://www.nxp.com/docs/en/application-note/AN13264.pdf diff --git a/boards/phytec/phyboard_atlas/phyboard_atlas-pinctrl.dtsi b/boards/phytec/phyboard_atlas/phyboard_atlas-pinctrl.dtsi new file mode 100644 index 000000000000..c983e6490ef7 --- /dev/null +++ b/boards/phytec/phyboard_atlas/phyboard_atlas-pinctrl.dtsi @@ -0,0 +1,325 @@ +/* + * Copyright (c) 2025 PHYTEC America LLC + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + pinmux_csi: pinmux_csi { + group0 { + pinmux = <&iomuxc_gpio_disp_b2_14_gpio11_io15>; + drive-strength = "high"; + bias-pull-down; + slew-rate = "fast"; + }; + + group1 { + pinmux = <&iomuxc_gpio_ad_26_gpio9_io25>; + drive-strength = "high"; + bias-pull-up; + slew-rate = "fast"; + }; + }; + + pinmux_enet: pinmux_enet { + group0 { + pinmux = <&iomuxc_gpio_disp_b2_08_enet_rx_en>, + <&iomuxc_gpio_disp_b2_09_enet_rx_er>; + drive-strength = "high"; + bias-pull-down; + slew-rate = "fast"; + }; + + group1 { + pinmux = <&iomuxc_gpio_disp_b2_06_enet_rdata00>, + <&iomuxc_gpio_disp_b2_07_enet_rdata01>; + drive-strength = "high"; + bias-pull-down; + slew-rate = "fast"; + input-enable; + }; + + group2 { + pinmux = <&iomuxc_gpio_disp_b2_02_enet_tdata00>, + <&iomuxc_gpio_disp_b2_03_enet_tdata01>, + <&iomuxc_gpio_disp_b2_04_enet_tx_en>; + drive-strength = "high"; + slew-rate = "fast"; + }; + + group3 { + pinmux = <&iomuxc_gpio_disp_b2_05_enet_ref_clk>; + drive-strength = "high"; + slew-rate = "slow"; + input-enable; + }; + }; + + pinmux_enet_mdio: pinmux_enet_mdio { + group0 { + pinmux = <&iomuxc_gpio_ad_32_enet_mdc>, + <&iomuxc_gpio_ad_33_enet_mdio>; + drive-strength = "high"; + slew-rate = "fast"; + }; + }; + + pinmux_lcdif: pinmux_lcdif { + group0 { + pinmux = <&iomuxc_gpio_ad_30_gpio9_io29>, + <&iomuxc_gpio_ad_31_gpio9_io30>; + drive-strength = "high"; + bias-pull-down; + slew-rate = "fast"; + }; + + group1 { + pinmux = <&iomuxc_gpio_disp_b2_15_gpio11_io16>; + drive-strength = "high"; + bias-pull-up; + slew-rate = "fast"; + }; + }; + + pinmux_lpi2c1: pinmux_lpi2c1 { + group0 { + pinmux = <&iomuxc_gpio_ad_08_lpi2c1_scl>, + <&iomuxc_gpio_ad_09_lpi2c1_sda>; + drive-strength = "normal"; + drive-open-drain; + slew-rate = "fast"; + input-enable; + }; + }; + + pinmux_lpi2c2: pinmux_lpi2c2 { + group0 { + pinmux = <&iomuxc_gpio_ad_18_lpi2c2_scl>, + <&iomuxc_gpio_ad_19_lpi2c2_sda>; + drive-strength = "high"; + slew-rate = "fast"; + input-enable; + }; + }; + + pinmux_lpi2c5: pinmux_lpi2c5 { + group0 { + pinmux = <&iomuxc_lpsr_gpio_lpsr_08_lpi2c5_sda>, + <&iomuxc_lpsr_gpio_lpsr_09_lpi2c5_scl>; + drive-strength = "normal"; + drive-open-drain; + slew-rate = "fast"; + input-enable; + }; + }; + + pinmux_lpspi1: pinmux_lpspi1 { + group0 { + pinmux = <&iomuxc_gpio_ad_29_lpspi1_pcs0>, + <&iomuxc_gpio_ad_28_lpspi1_sck>, + <&iomuxc_gpio_ad_31_lpspi1_sdi>, + <&iomuxc_gpio_ad_30_lpspi1_sdo>; + drive-strength = "high"; + slew-rate = "fast"; + }; + }; + + pinmux_lpspi5: pinmux_lpspi5 { + group0 { + pinmux = <&iomuxc_lpsr_gpio_lpsr_03_lpspi5_pcs0>, + <&iomuxc_lpsr_gpio_lpsr_06_lpspi5_pcs1>, + <&iomuxc_lpsr_gpio_lpsr_07_lpspi5_pcs2>, + <&iomuxc_lpsr_gpio_lpsr_02_lpspi5_sck>, + <&iomuxc_lpsr_gpio_lpsr_05_lpspi5_sdi>, + <&iomuxc_lpsr_gpio_lpsr_04_lpspi5_sdo>; + drive-strength = "high"; + slew-rate = "fast"; + }; + }; + + pinmux_lpuart1: pinmux_lpuart1 { + group0 { + pinmux = <&iomuxc_gpio_ad_25_lpuart1_rx>, + <&iomuxc_gpio_ad_24_lpuart1_tx>; + drive-strength = "high"; + slew-rate = "fast"; + }; + }; + + pinmux_lpuart1_sleep: pinmux_lpuart1_sleep { + group0 { + pinmux = <&iomuxc_gpio_ad_25_gpio_mux3_io24>; + drive-strength = "high"; + bias-pull-up; + slew-rate = "fast"; + }; + + group1 { + pinmux = <&iomuxc_gpio_ad_24_lpuart1_tx>; + drive-strength = "high"; + slew-rate = "fast"; + }; + }; + + pinmux_lpuart2: pinmux_lpuart2 { + group0 { + pinmux = <&iomuxc_gpio_disp_b2_11_lpuart2_rx>, + <&iomuxc_gpio_disp_b2_10_lpuart2_tx>; + drive-strength = "high"; + slew-rate = "fast"; + }; + }; + + pinmux_lpuart2_sleep: pinmux_lpuart2_sleep { + group0 { + pinmux = <&iomuxc_gpio_disp_b2_11_gpio_mux5_io12>; + drive-strength = "high"; + bias-pull-up; + slew-rate = "fast"; + }; + + group1 { + pinmux = <&iomuxc_gpio_disp_b2_10_lpuart2_tx>; + drive-strength = "high"; + slew-rate = "fast"; + }; + }; + + pinmux_lpuart5: pinmux_lpuart5 { + group0 { + pinmux = <&iomuxc_gpio_ad_29_lpuart5_rx>, + <&iomuxc_gpio_ad_28_lpuart5_tx>; + drive-strength = "high"; + slew-rate = "fast"; + }; + }; + + pinmux_lpuart5_sleep: pinmux_lpuart5_sleep { + group0 { + pinmux = <&iomuxc_gpio_ad_29_gpio_mux3_io28>; + drive-strength = "high"; + bias-pull-up; + slew-rate = "fast"; + }; + + group1 { + pinmux = <&iomuxc_gpio_ad_28_lpuart5_tx>; + drive-strength = "high"; + slew-rate = "fast"; + }; + }; + + pinmux_lpuart6: pinmux_lpuart6 { + group0 { + pinmux = <&iomuxc_gpio_emc_b1_41_lpuart6_rx>, + <&iomuxc_gpio_emc_b1_40_lpuart6_tx>; + drive-strength = "high"; + slew-rate = "fast"; + }; + }; + + pinmux_lpuart6_sleep: pinmux_lpuart6_sleep { + group0 { + pinmux = <&iomuxc_gpio_emc_b1_41_gpio_mux2_io09>; + drive-strength = "high"; + bias-pull-up; + slew-rate = "fast"; + }; + + group1 { + pinmux = <&iomuxc_gpio_emc_b1_40_lpuart6_tx>; + drive-strength = "high"; + slew-rate = "fast"; + }; + }; + + pinmux_lpuart8: pinmux_lpuart8 { + group0 { + pinmux = <&iomuxc_gpio_ad_03_lpuart8_rx>, + <&iomuxc_gpio_ad_02_lpuart8_tx>; + drive-strength = "high"; + slew-rate = "fast"; + }; + }; + + pinmux_lpuart8_sleep: pinmux_lpuart8_sleep { + group0 { + pinmux = <&iomuxc_gpio_ad_03_gpio9_io02>; + drive-strength = "high"; + bias-pull-up; + slew-rate = "fast"; + }; + + group1 { + pinmux = <&iomuxc_gpio_ad_02_lpuart8_tx>; + drive-strength = "high"; + slew-rate = "fast"; + }; + }; + + pinmux_lpuart8_flowcontrol: pinmux_lpuart8_flowcontrol { + group0 { + pinmux = <&iomuxc_gpio_ad_03_lpuart8_rx>, + <&iomuxc_gpio_ad_02_lpuart8_tx>, + <&iomuxc_gpio_ad_04_lpuart8_cts_b>, + <&iomuxc_gpio_ad_05_lpuart8_rts_b>; + drive-strength = "high"; + slew-rate = "fast"; + }; + }; + + pinmux_flexcan3: pinmux_flexcan3 { + group0 { + pinmux = <&iomuxc_lpsr_gpio_lpsr_01_can3_rx>, + <&iomuxc_lpsr_gpio_lpsr_00_can3_tx>; + drive-strength = "high"; + slew-rate = "fast"; + }; + }; + + pinmux_sai1: pinmux_sai1 { + group0 { + pinmux = <&iomuxc_gpio_ad_17_sai1_mclk>, + <&iomuxc_gpio_ad_20_sai1_rx_data00>, + <&iomuxc_gpio_ad_21_sai1_tx_data00>, + <&iomuxc_gpio_ad_22_sai1_tx_bclk>, + <&iomuxc_gpio_ad_23_sai1_tx_sync>; + drive-strength = "high"; + slew-rate = "fast"; + input-enable; + }; + }; + + pinmux_usdhc1: pinmux_usdhc1 { + group0 { + pinmux = <&iomuxc_gpio_sd_b1_00_usdhc1_cmd>, + <&iomuxc_gpio_sd_b1_01_usdhc1_clk>, + <&iomuxc_gpio_sd_b1_02_usdhc1_data0>, + <&iomuxc_gpio_sd_b1_03_usdhc1_data1>, + <&iomuxc_gpio_sd_b1_04_usdhc1_data2>, + <&iomuxc_gpio_sd_b1_05_usdhc1_data3>; + bias-pull-up; + input-enable; + }; + }; + + /* removes pull on dat3 for card detect */ + pinmux_usdhc1_dat3_nopull: pinmux_usdhc1_dat3_nopull { + group0 { + pinmux = <&iomuxc_gpio_sd_b1_05_usdhc1_data3>; + bias-disable; + input-enable; + }; + + group1 { + pinmux = <&iomuxc_gpio_sd_b1_00_usdhc1_cmd>, + <&iomuxc_gpio_sd_b1_01_usdhc1_clk>, + <&iomuxc_gpio_sd_b1_02_usdhc1_data0>, + <&iomuxc_gpio_sd_b1_03_usdhc1_data1>, + <&iomuxc_gpio_sd_b1_04_usdhc1_data2>; + bias-pull-up; + input-enable; + }; + }; +}; diff --git a/boards/phytec/phyboard_atlas/phyboard_atlas.dtsi b/boards/phytec/phyboard_atlas/phyboard_atlas.dtsi new file mode 100644 index 000000000000..cb9d9ce78281 --- /dev/null +++ b/boards/phytec/phyboard_atlas/phyboard_atlas.dtsi @@ -0,0 +1,211 @@ +/* + * Copyright (c) 2025 PHYTEC America LLC + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "phyboard_atlas-pinctrl.dtsi" +#include + +/ { + aliases { + accel0 = &icm40627; + eeprom0 = &eeprom0; + i2s-codec-tx = &sai1; + led0 = &som_green_led; + led1 = &som_red_led; + led3 = &board_red_led; + led4 = &board_green_led; + sdhc0 = &usdhc1; + sdram0 = &sdram0; + sw0 = &user_button; + watchdog0 = &wdog1; + }; + + gpio_keys { + compatible = "gpio-keys"; + + user_button: button-1 { + label = "User Button"; + gpios = <&gpio4 2 GPIO_ACTIVE_HIGH>; + zephyr,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + board_red_led: led-3 { + label = "Red LED1 D4"; + gpios = <&gpio9 13 GPIO_ACTIVE_HIGH>; + }; + + board_green_led: led-4 { + label = "Green LED2 D11"; + gpios = <&gpio12 13 GPIO_ACTIVE_HIGH>; + }; + }; + + expansion_header: connector { + compatible = "gpio-nexus"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <11 0 &gpio4 1 0>, /* Pin 11, GPIO_AD_34 */ + <27 0 &gpio3 25 0>, /* Pin 27, EXP_AD_26 */ + <29 0 &gpio3 26 0>, /* Pin 29, EXP_AD_27 */ + <31 0 &gpio5 1 0>, /* Pin 31, GPIO_DISP_B2_00 */ + <33 0 &gpio13 3 0>, /* Pin 33, GPIO_SNVS_00 */ + <35 0 &gpio13 4 0>, /* Pin 35, GPIO_SNVS_01 */ + <36 0 &gpio13 5 0>, /* Pin 36, GPIO_SNVS_02 */ + <37 0 &gpio13 6 0>, /* Pin 37, GPIO_SNVS_03 */ + <38 0 &gpio13 7 1>, /* Pin 38, GPIO_SNVS_04 */ + <40 0 &gpio13 8 1>; /* Pin 40, GPIO_SNVS_05 */ + }; + + transceiver0: can-phy0 { + compatible = "can-transceiver-gpio"; + standby-gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; +}; + +&enet_mac { + status = "okay"; + pinctrl-0 = <&pinmux_enet>; + pinctrl-names = "default"; + phy-handle = <&phy>; + phy-connection-type = "rmii"; + zephyr,random-mac-address; +}; + +&enet_mdio { + status = "okay"; + pinctrl-0 = <&pinmux_enet_mdio>; + pinctrl-names = "default"; + + phy: phy@1 { + compatible = "microchip,ksz8081"; + reg = <1>; + status = "okay"; + microchip,interface-type = "rmii"; + }; +}; + +&enet_ptp_clock { + status = "okay"; +}; + +&csi { + pinctrl-0 = <&pinmux_csi>; + pinctrl-names = "default"; +}; + +&flexcan3 { + pinctrl-0 = <&pinmux_flexcan3>; + pinctrl-names = "default"; +}; + +&lcdif { + pinctrl-0 = <&pinmux_lcdif>; + pinctrl-names = "default"; +}; + +&lpi2c1 { + pinctrl-0 = <&pinmux_lpi2c1>; + pinctrl-names = "default"; +}; + +&lpi2c2 { + pinctrl-0 = <&pinmux_lpi2c2>; + pinctrl-names = "default"; +}; + +&lpi2c5 { + pinctrl-0 = <&pinmux_lpi2c5>; + pinctrl-names = "default"; + status = "okay"; + + audio_codec: tlv320aic3110@18 { + compatible = "ti,tlv320aic3110"; + reg = <0x18>; + status = "okay"; + clocks = <&ccm IMX_CCM_SAI1_CLK 0x2004 4>; + clock-names = "mclk"; + }; + + icm40627: icm40627@6b { + compatible = "invensense,icm40627"; + reg = <0x6b>; + status = "okay"; + accel-hz = <1000>; + accel-fs = <16>; + gyro-hz = <1000>; + gyro-fs = <2000>; + int-gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>, + <&gpio3 26 GPIO_ACTIVE_HIGH>; + }; +}; + +&lpspi1 { + pinctrl-0 = <&pinmux_lpspi1>; + pinctrl-names = "default"; +}; + +&lpspi5 { + pinctrl-0 = <&pinmux_lpspi5>; + pinctrl-names = "default"; +}; + +&lpuart1 { + pinctrl-0 = <&pinmux_lpuart1>; + pinctrl-1 = <&pinmux_lpuart1_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&lpuart2 { + pinctrl-0 = <&pinmux_lpuart2>; + pinctrl-1 = <&pinmux_lpuart2_sleep>; + pinctrl-names = "default", "sleep"; + current-speed = <115200>; + status = "okay"; +}; + +&lpuart5 { + pinctrl-0 = <&pinmux_lpuart5>; + pinctrl-1 = <&pinmux_lpuart5_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&lpuart6 { + pinctrl-0 = <&pinmux_lpuart6>; + pinctrl-1 = <&pinmux_lpuart6_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&lpuart8 { + pinctrl-0 = <&pinmux_lpuart8_flowcontrol>; + pinctrl-1 = <&pinmux_lpuart8_sleep>; + pinctrl-names = "default", "sleep"; + hw-flow-control; +}; + +&pxp { + status = "okay"; +}; + +&sai1 { + pinctrl-0 = <&pinmux_sai1>; + pinctrl-names = "default"; + clock-mux = <1>; + pre-div = <0>; + podf = <2>; + nxp,tx-dma-channel = <8>; + nxp,rx-dma-channel = <9>; +}; + +&usdhc1 { + pinctrl-0 = <&pinmux_usdhc1>; + pinctrl-1 = <&pinmux_usdhc1_dat3_nopull>; + pinctrl-names = "default", "nopull"; +}; diff --git a/boards/phytec/phyboard_atlas/phyboard_atlas_mimxrt1176_cm7.dts b/boards/phytec/phyboard_atlas/phyboard_atlas_mimxrt1176_cm7.dts new file mode 100644 index 000000000000..e2bef87442e7 --- /dev/null +++ b/boards/phytec/phyboard_atlas/phyboard_atlas_mimxrt1176_cm7.dts @@ -0,0 +1,152 @@ +/* + * Copyright (c) 2025 PHYTEC America LLC + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "phyboard_atlas.dtsi" + +/ { + model = "PHYTEC phyBOARD-Atlas i.MX RT1170 CM7"; + compatible = "phytec,phyboard_atlas"; + + aliases { + mipi-dsi = &mipi_dsi; + }; + + chosen { + zephyr,console = &lpuart1; + zephyr,shell-uart = &lpuart1; + zephyr,canbus = &flexcan3; + }; + + nxp_mipi_connector: mipi-connector { + compatible = "gpio-nexus"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio9 29 0>, /* Pin 1, LEDK */ + <21 0 &gpio9 30 0>, /* Pin 21, RESET */ + <28 0 &gpio9 0 0>, /* Pin 28, CTP_RST */ + <29 0 &gpio2 31 0>, /* Pin 29, CTP_INT */ + <32 0 &gpio11 16 0>, /* Pin 32, PWR_EN */ + <34 0 &gpio9 29 0>; /* Pin 34, BL_PWM */ + }; + + nxp_cam_connector: cam-connector { + compatible = "nxp,cam-44pins-connector"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <9 0 &gpio11 15 0>, /* Pin 9, RESETB */ + <17 0 &gpio9 25 0>; /* Pin 17, PWDN */ + }; +}; + +&user_button { + status = "okay"; +}; + +&board_green_led { + status = "okay"; +}; + +&board_red_led { + status = "okay"; +}; + +&flexcan3 { + status = "okay"; + phys = <&transceiver0>; +}; + +&lpspi1 { + dmas = <&edma0 0 36>, <&edma0 1 37>; + dma-names = "rx", "tx"; + status = "disabled"; /* LPSPI1 conflicts with LPUART5 */ +}; + +&lpspi5 { + status = "okay"; +}; + +&edma0 { + status = "okay"; +}; + +&lpuart1 { + status = "okay"; + current-speed = <115200>; +}; + +&lpuart5 { + status = "okay"; + current-speed = <115200>; +}; + +&lpuart8 { + status = "okay"; + current-speed = <115200>; +}; + +nxp_mipi_i2c: &lpi2c5 { + pinctrl-0 = <&pinmux_lpi2c5>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; +}; + +&sai1 { + status = "okay"; +}; + +zephyr_udc0: &usb1 { + status = "okay"; + phy-handle = <&usbphy1>; +}; + +&usbphy1 { + status = "okay"; + tx-d-cal = <7>; + tx-cal-45-dp-ohms = <6>; + tx-cal-45-dm-ohms = <6>; +}; + +&usb2 { + status = "disabled"; + phy-handle = <&usbphy2>; +}; + +&usbphy2 { + status = "okay"; + tx-d-cal = <7>; + tx-cal-45-dp-ohms = <6>; + tx-cal-45-dm-ohms = <6>; +}; + +&usdhc1 { + status = "okay"; + detect-dat3; + no-1-8-v; + + sdmmc { + compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; + status = "okay"; + }; +}; + +zephyr_lcdif: &lcdif {}; + +zephyr_mipi_dsi: &mipi_dsi { + dphy-ref-frequency = <24000000>; + phy-clock = <792000000>; +}; + +nxp_cam_i2c: &lpi2c2 {}; + +nxp_mipi_csi: &mipi_csi2rx {}; + +nxp_csi: &csi {}; diff --git a/boards/phytec/phyboard_atlas/phyboard_atlas_mimxrt1176_cm7.yaml b/boards/phytec/phyboard_atlas/phyboard_atlas_mimxrt1176_cm7.yaml new file mode 100644 index 000000000000..e42d9304dcdc --- /dev/null +++ b/boards/phytec/phyboard_atlas/phyboard_atlas_mimxrt1176_cm7.yaml @@ -0,0 +1,29 @@ +# Copyright (c) 2025 PHYTEC America LLC +# SPDX-License-Identifier: Apache-2.0 + +identifier: phyboard_atlas/mimxrt1176/cm7 +name: PHYTEC phyBOARD-Atlas i.MX RT1170 CM7 +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 256 +flash: 16384 +supported: + - can + - dac + - display + - dma + - flash + - gpio + - i2c + - i2s + - mipi_dsi + - netif:eth + - spi + - uart + - usb_device + - usbd +vendor: phytec diff --git a/boards/phytec/phyboard_atlas/phyboard_atlas_mimxrt1176_cm7_defconfig b/boards/phytec/phyboard_atlas/phyboard_atlas_mimxrt1176_cm7_defconfig new file mode 100644 index 000000000000..311064af8a38 --- /dev/null +++ b/boards/phytec/phyboard_atlas/phyboard_atlas_mimxrt1176_cm7_defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2025 PHYTEC America LLC +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/phytec/phyboard_atlas/phyboard_atlas_mimxrt1176_cm7_usb2.overlay b/boards/phytec/phyboard_atlas/phyboard_atlas_mimxrt1176_cm7_usb2.overlay new file mode 100644 index 000000000000..4caaf115f2c4 --- /dev/null +++ b/boards/phytec/phyboard_atlas/phyboard_atlas_mimxrt1176_cm7_usb2.overlay @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 PHYTEC America LLC + * SPDX-License-Identifier: Apache-2.0 + */ + +/delete-node/ &zephyr_udc0; + +zephyr_udc0: &usb2 {}; diff --git a/boards/phytec/phyboard_atlas/xip/phycore_rt1170_flexspi_nor_config.c b/boards/phytec/phyboard_atlas/xip/phycore_rt1170_flexspi_nor_config.c new file mode 100644 index 000000000000..e817c6f3cc99 --- /dev/null +++ b/boards/phytec/phyboard_atlas/xip/phycore_rt1170_flexspi_nor_config.c @@ -0,0 +1,89 @@ +/* + * Copyright 2018-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "phycore_rt1170_flexspi_nor_config.h" + +#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) +__attribute__((section(".boot_hdr.conf"), used)) + +#define FLASH_DUMMY_CYCLES 0x09 +#define FLASH_DUMMY_VALUE 0x09 + +const flexspi_nor_config_t qspi_flash_config = { + .mem_config = { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .read_sample_clk_src = + FLEXSPI_READ_SAMPLE_CLK_LOOPBACK_FROM_DQS_PAD, + .cs_hold_time = 3u, + .cs_setup_time = 3u, + /* Enable DDR mode, Wordaddassable, Safe configuration, Differential clock */ + .controller_misc_option = 0x10, + .device_type = FLEXSPI_DEVICE_TYPE_SERIAL_NOR, + .sflash_pad_type = SERIAL_FLASH_4_PADS, + .serial_clk_freq = FLEXSPI_SERIAL_CLK_133MHZ, + .sflash_a1_size = 16u * 1024u * 1024u, + /* Enable flash configuration feature */ + .config_cmd_enable = 1u, + .config_mode_type[0] = DEVICE_CONFIG_CMD_TYPE_GENERIC, + /* Set configuration command sequences */ + .config_cmd_seqs[0] = { + .seq_num = 1, + .seq_id = 12, + .reserved = 0, + }, + /* Prepare setting value for Read Register in flash */ + .config_cmd_args[0] = (FLASH_DUMMY_VALUE << 3), + .lookup_table = { + /* Read LUTs */ + [0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, + 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18), + [1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, + FLASH_DUMMY_CYCLES, READ_SDR, FLEXSPI_4PAD, + 0x04), + + /* Read Status LUTs */ + [4 * 1 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, + 0x05, READ_SDR, FLEXSPI_1PAD, 0x04), + + /* Write Enable LUTs */ + [4 * 3 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, + 0x06, STOP, FLEXSPI_1PAD, 0x0), + + /* Erase Sector LUTs */ + [4 * 5 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, + 0x20, RADDR_SDR, FLEXSPI_1PAD, 0x18), + + /* Erase Block LUTs */ + [4 * 8 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, + 0xD8, RADDR_SDR, FLEXSPI_1PAD, 0x18), + + /* Pape Program LUTs */ + [4 * 9 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, + 0x02, RADDR_SDR, FLEXSPI_1PAD, 0x18), + [4 * 9 + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, + 0x04, STOP, FLEXSPI_1PAD, 0x0), + + /* Erase Chip LUTs */ + [4 * 11 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, + 0x60, STOP, FLEXSPI_1PAD, 0x0), + + /* Set Read Register LUTs */ + [4 * 12 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, + 0xC0, WRITE_SDR, FLEXSPI_1PAD, 0x01), + [4 * 12 + 1] = FLEXSPI_LUT_SEQ(STOP, FLEXSPI_1PAD, + 0x00, 0, 0, 0), + }, + }, + .page_size = 256u, + .sector_size = 4u * 1024u, + .ipcmd_serial_clk_freq = 0x1, + .block_size = 64u * 1024u, + .is_uniform_block_size = false, +}; + +#endif /* defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) */ diff --git a/boards/phytec/phyboard_atlas/xip/phycore_rt1170_flexspi_nor_config.h b/boards/phytec/phyboard_atlas/xip/phycore_rt1170_flexspi_nor_config.h new file mode 100644 index 000000000000..a43425e7d0bc --- /dev/null +++ b/boards/phytec/phyboard_atlas/xip/phycore_rt1170_flexspi_nor_config.h @@ -0,0 +1,375 @@ +/* + * Copyright 2018-2020, 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef PHYCORE_FLEXSPI_NOR_CONFIG_ +#define PHYCORE_FLEXSPI_NOR_CONFIG_ + +#include +#include +#include "fsl_common.h" + +/* FLEXSPI memory config block related definitions */ +#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) /* ascii "FCFB" Big Endian */ +#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) /* V1.4.0 */ +#define FLEXSPI_CFG_BLK_SIZE (512) + +/* FLEXSPI Feature related definitions */ +#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 + +/* Lookup table related definitions */ +#define CMD_INDEX_READ 0 +#define CMD_INDEX_READSTATUS 1 +#define CMD_INDEX_WRITEENABLE 2 +#define CMD_INDEX_WRITE 4 + +#define CMD_LUT_SEQ_IDX_READ 0 +#define CMD_LUT_SEQ_IDX_READSTATUS 1 +#define CMD_LUT_SEQ_IDX_WRITEENABLE 3 +#define CMD_LUT_SEQ_IDX_WRITE 9 + +#define CMD_SDR 0x01 +#define CMD_DDR 0x21 +#define RADDR_SDR 0x02 +#define RADDR_DDR 0x22 +#define CADDR_SDR 0x03 +#define CADDR_DDR 0x23 +#define MODE1_SDR 0x04 +#define MODE1_DDR 0x24 +#define MODE2_SDR 0x05 +#define MODE2_DDR 0x25 +#define MODE4_SDR 0x06 +#define MODE4_DDR 0x26 +#define MODE8_SDR 0x07 +#define MODE8_DDR 0x27 +#define WRITE_SDR 0x08 +#define WRITE_DDR 0x28 +#define READ_SDR 0x09 +#define READ_DDR 0x29 +#define LEARN_SDR 0x0A +#define LEARN_DDR 0x2A +#define DATSZ_SDR 0x0B +#define DATSZ_DDR 0x2B +#define DUMMY_SDR 0x0C +#define DUMMY_DDR 0x2C +#define DUMMY_RWDS_SDR 0x0D +#define DUMMY_RWDS_DDR 0x2D +#define JMP_ON_CS 0x1F +#define STOP 0 + +#define FLEXSPI_1PAD 0 +#define FLEXSPI_2PAD 1 +#define FLEXSPI_4PAD 2 +#define FLEXSPI_8PAD 3 + +#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | \ + FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ + FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) + +/*! @brief Definitions for FlexSPI Serial Clock Frequency */ +typedef enum flexspi_serial_clock_freq { + FLEXSPI_SERIAL_CLK_30MHZ = 1, + FLEXSPI_SERIAL_CLK_50MHZ = 2, + FLEXSPI_SERIAL_CLK_60MHZ = 3, + FLEXSPI_SERIAL_CLK_80MHZ = 4, + FLEXSPI_SERIAL_CLK_100MHZ = 5, + FLEXSPI_SERIAL_CLK_120MHZ = 6, + FLEXSPI_SERIAL_CLK_133MHZ = 7, + FLEXSPI_SERIAL_CLK_166MHZ = 8, + FLEXSPI_SERIAL_CLK_200MHZ = 9, +} flexspi_serial_clk_freq_t; + +/*! @brief FlexSPI clock configuration type */ +enum { + /* Clock configure for SDR mode */ + FLEXSPI_CLK_SDR, + /* Clock configurat for DDR mode */ + FLEXSPI_CLK_DDR, +}; + +/*! @brief FlexSPI Read Sample Clock Source definition */ +typedef enum flexspi_read_sample_clk_source { + FLEXSPI_READ_SAMPLE_CLK_LOOPBACK_INTERNALLY = 0, + FLEXSPI_READ_SAMPLE_CLK_LOOPBACK_FROM_DQS_PAD = 1, + FLEXSPI_READ_SAMPLE_CLK_LOOPBACK_FROM_SCK_PAD = 2, + FLEXSPI_READ_SAMPLE_CLK_EXTERNAL_INPUT_FROM_DQS_PAD = 3, +} flexspi_read_sample_clk_t; + +/*! @brief Misc feature bit definitions */ +enum { + /* Bit for Differential clock enable */ + FLEXSPI_MISC_OFFSET_DIFF_CLK_ENABLE = 0, + /* Bit for CK2 enable */ + FLEXSPI_MISC_OFFSET_CK2_ENABLE = 1, + /* Bit for Parallel mode enable */ + FLEXSPI_MISC_OFFSET_PARALLEL_ENABLE = 2, + /* Bit for Word Addressable enable */ + FLEXSPI_MISC_OFFSET_WORD_ADDRESSABLE_ENABLE = 3, + /* Bit for Safe Configuration Frequency enable */ + FLEXSPI_MISC_OFFSET_SAFE_CONFIG_FREQ_ENABLE = 4, + /* Bit for Pad setting override enable */ + FLEXSPI_MISC_OFFSET_PAD_SETTING_OVERRIDE_ENABLE = 5, + /* Bit for DDR clock configuration indication. */ + FLEXSPI_MISC_OFFSET_DDR_MODE_ENABLE = 6, +}; + +/*! @brief Flash Type Definition */ +enum { + /* Flash devices are Serial NOR */ + FLEXSPI_DEVICE_TYPE_SERIAL_NOR = 1, + /* Flash devices are Serial NAND */ + FLEXSPI_DEVICE_TYPE_SERIAL_NAND = 2, + /* Flash devices are Serial RAM/HyperFLASH */ + FLEXSPI_DEVICE_TYPE_SERIAL_RAM = 3, + /* Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND */ + FLEXSPI_DEVICE_TYPE_MCP_NOR_NAND = 0x12, + /* Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs */ + FLEXSPI_DEVICE_TYPE_MCP_NOR_RAM = 0x13, +}; + +/*! @brief Flash Pad Definitions */ +enum { + SERIAL_FLASH_1_PADS = 1, + SERIAL_FLASH_2_PADS = 2, + SERIAL_FLASH_4_PADS = 4, + SERIAL_FLASH_8_PADS = 8, +}; + +/*! @brief FlexSPI LUT Sequence structure */ +typedef struct _lut_sequence { + uint8_t seq_num; /* Sequence Number, valid number: 1-16 */ + uint8_t seq_id; /* Sequence Index, valid number: 0-15 */ + uint16_t reserved; +} flexspi_lut_seq_t; + +/*! @brief Flash Configuration Command Type */ +enum { + /* Generic command, for example: configure dummy cycles, + * drive strength, etc + */ + DEVICE_CONFIG_CMD_TYPE_GENERIC, + /* Quad Enable command */ + DEVICE_CONFIG_CMD_TYPE_QUAD_ENABLE, + /* Switch from SPI to DPI/QPI/OPI mode */ + DEVICE_CONFIG_CMD_TYPE_SPI2XPI, + /* Switch from DPI/QPI/OPI to SPI mode */ + DEVICE_CONFIG_CMD_TYPE_XPI2SPI, + /* Switch to 0-4-4/0-8-8 mode */ + DEVICE_CONFIG_CMD_TYPE_SPI2NOCMD, + /* Reset device command */ + DEVICE_CONFIG_CMD_TYPE_RESET, +}; + +/*! @brief FlexSPI Memory Configuration Block */ +typedef struct flexspi_config { + /* [0x000-0x003] Tag, fixed value 0x42464346UL */ + uint32_t tag; + /* [0x004-0x007] Version, [31:24] -'V', + * [23:16] - Major, + * [15:8] - Minor, + * [7:0] - bugfix + */ + uint32_t version; + /* [0x008-0x00b] Reserved for future use */ + uint32_t reserved0; + /* [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 */ + uint8_t read_sample_clk_src; + /* [0x00d-0x00d] CS hold time, default value: 3 */ + uint8_t cs_hold_time; + /* [0x00e-0x00e] CS setup time, default value: 3 */ + uint8_t cs_setup_time; + /* [0x00f-0x00f] Column Address with, for HyperBus protocol, + * it is fixed to 3, For Serial NAND, need to refer to datasheet + */ + uint8_t column_address_width; + /* [0x010-0x010] Device Mode Configure enable flag, + * 1 - Enable, 0 - Disable + */ + uint8_t device_mode_cfg_enable; + /* [0x011-0x011] Specify the configuration command type:Quad Enable, + * DPI/QPI/OPI switch, Generic configuration, etc. + */ + uint8_t device_mode_type; + /* [0x012-0x013] Wait time for all configuration commands, + * unit: 100us, Used for DPI/QPI/OPI switch or reset command + */ + uint16_t wait_time_cfg_commands; + /* [0x014-0x017] Device mode sequence info, + * [7:0] - LUT sequence id, + * [15:8] - LUt sequence number, + * [31:16] Reserved + */ + flexspi_lut_seq_t device_mode_seq; + /* [0x018-0x01b] Argument/Parameter for device configuration */ + uint32_t device_mode_arg; + /* [0x01c-0x01c] Configure command Enable Flag, + * 1 - Enable, 0 - Disable + */ + uint8_t config_cmd_enable; + /* [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe */ + uint8_t config_mode_type[3]; + /* [0x020-0x02b] Sequence info for Device Configuration command, + * similar as deviceModeSeq + */ + flexspi_lut_seq_t config_cmd_seqs[3]; + /* [0x02c-0x02f] Reserved for future use */ + uint32_t reserved1; + /* [0x030-0x03b] Arguments/Parameters for + * device Configuration commands + */ + uint32_t config_cmd_args[3]; + /* [0x03c-0x03f] Reserved for future use */ + uint32_t reserved2; + /* [0x040-0x043] Controller Misc Options, see Misc feature bit + * definitions for more details + */ + uint32_t controller_misc_option; + /* [0x044-0x044] Device Type: + * See Flash Type Definition for more details + */ + uint8_t device_type; + /* [0x045-0x045] Serial Flash Pad Type: + * 1 - Single, + * 2 - Dual, + * 4 - Quad, + * 8 - Octal + */ + uint8_t sflash_pad_type; + /* [0x046-0x046] Serial Flash Frequency, device specific + * definitions, See System Boot Chapter for more details + */ + uint8_t serial_clk_freq; + /* [0x047-0x047] LUT customization Enable, it is required if + * the program/erase cannot be done using 1 LUT sequence, + * currently, only applicable to HyperFLASH + */ + uint8_t lut_custom_seq_enable; + /* [0x048-0x04f] Reserved for future use */ + uint32_t reserved3[2]; + /* [0x050-0x053] Size of Flash connected to A1 */ + uint32_t sflash_a1_size; + /* [0x054-0x057] Size of Flash connected to A2 */ + uint32_t sflash_a2_size; + /* [0x058-0x05b] Size of Flash connected to B1 */ + uint32_t sflash_b1_size; + /* [0x05c-0x05f] Size of Flash connected to B2 */ + uint32_t sflash_b2_size; + /* [0x060-0x063] CS pad setting override value */ + uint32_t cs_pad_setting_override; + /* [0x064-0x067] SCK pad setting override value */ + uint32_t sclk_pad_setting_override; + /* [0x068-0x06b] data pad setting override value */ + uint32_t data_pad_setting_override; + /* [0x06c-0x06f] DQS pad setting override value */ + uint32_t dqs_pad_setting_override; + /* [0x070-0x073] Timeout threshold for read status command */ + uint32_t timeout_in_ms; + /* [0x074-0x077] CS deselect interval between two commands */ + uint32_t command_interval; + /* [0x078-0x07b] CLK edge to data valid time + * for PORT A and PORT B, in terms of 0.1ns + */ + uint16_t data_valid_time[2]; + /* [0x07c-0x07d] Busy offset, valid value: 0-31 */ + uint16_t busy_offset; + /* [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 + * when flash device is busy, 1 - busy flag is 0 when + * flash device is busy + */ + uint16_t busy_bit_polarity; + /* [0x080-0x17f] Lookup table holds Flash command sequences */ + uint32_t lookup_table[64]; + /* [0x180-0x1af] Customizable LUT Sequences */ + flexspi_lut_seq_t lut_custom_seq[12]; + /* [0x1b0-0x1bf] Reserved for future use */ + uint32_t reserved4[4]; +} flexspi_mem_config_t; + +#define NOR_CMD_INDEX_READ CMD_INDEX_READ /* 0 */ +#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS /* 1 */ +#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE /* 2 */ +#define NOR_CMD_INDEX_ERASESECTOR 3 /* 3 */ +#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE /* 4 */ +#define NOR_CMD_INDEX_CHIPERASE 5 /* 5 */ +#define NOR_CMD_INDEX_DUMMY 6 /* 6 */ +#define NOR_CMD_INDEX_ERASEBLOCK 7 /* 7 */ + +/* 0 READ LUT sequence id in lookupTable stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ +/* 1 Read Status LUT sequence id in lookupTable stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS CMD_LUT_SEQ_IDX_READSTATUS +/* 2 Read status DPI/QPI/OPI sequence id in + * lookupTable stored in config block + */ +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI 2 +/* 3 Write Enable sequence id in lookupTable stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE CMD_LUT_SEQ_IDX_WRITEENABLE +/* 4 Write Enable DPI/QPI/OPI sequence id in + * lookupTable stored in config block + */ +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI 4 +/* 5 Erase Sector sequence id in lookupTable stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 +/* 8 Erase Block sequence id in lookupTable stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 +/* 9 Program sequence id in lookupTable stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM CMD_LUT_SEQ_IDX_WRITE +/* 11 Chip Erase sequence in lookupTable id stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 +/* 13 Read SFDP sequence in lookupTable id stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 +/* 14 Restore 0-4-4/0-8-8 mode sequence id in + * lookupTable stored in config block + */ +#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD 14 +/* 15 Exit 0-4-4/0-8-8 mode sequence id in + * lookupTable stored in config blobk + */ +#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD 15 + +/* + * Serial NOR configuration block + */ +typedef struct _flexspi_nor_config { + /* Common memory configuration info via FlexSPI */ + flexspi_mem_config_t mem_config; + /* Page size of Serial NOR */ + uint32_t page_size; + /* Sector size of Serial NOR */ + uint32_t sector_size; + /* Clock frequency for IP command */ + uint8_t ipcmd_serial_clk_freq; + /* Sector/Block size is the same */ + uint8_t is_uniform_block_size; + /* The data order is swapped in OPI DDR mode */ + uint8_t is_data_order_swapped; + /* Reserved for future use */ + uint8_t reserved0; + /* Serial NOR Flash type: 0/1/2/3 */ + uint8_t serial_nor_type; + /* Need to exit NoCmd mode before other IP command */ + uint8_t need_exit_nocmd_mode; + /* Half the Serial Clock for non-read command: true/false */ + uint8_t half_clk_for_non_read_cmd; + /* Need to Restore NoCmd mode after IP command execution */ + uint8_t need_restore_nocmd_mode; + /* Block size */ + uint32_t block_size; + /* Flash State Context after being configured */ + uint32_t flash_state_ctx; + /* Reserved for future use */ + uint32_t reserve2[10]; +} flexspi_nor_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif +#endif /* #ifndef PHYCORE_FLEXSPI_NOR_CONFIG_ */ diff --git a/boards/phytec/phyboard_atlas/xmcd/xmcd.c b/boards/phytec/phyboard_atlas/xmcd/xmcd.c new file mode 100644 index 000000000000..4f4893dbb999 --- /dev/null +++ b/boards/phytec/phyboard_atlas/xmcd/xmcd.c @@ -0,0 +1,34 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "xmcd.h" + +#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) + +#if defined(XIP_BOOT_HEADER_XMCD_ENABLE) && (XIP_BOOT_HEADER_XMCD_ENABLE == 1) +__attribute__((section(".boot_hdr.xmcd_data"), used)) + +const uint32_t xmcd_data[] = { + /* Tag = 0xC, Version = 0, Memory Interface: SEMC, + * Instance: 0 - ignored, + * Configuration block type: 0 - Ignored(Handled inside + * the SDRAM configuration structure) + * Configuration block size: 13 (4-byte header + 9-byte + * option block) + */ + 0xC010000Du, + /* Magic_number = 0xA1, Version = 1, + * Config_option: Simplified, SDRAM clock: 198MHz + */ + 0xC60001A1u, + /* SDRAM CS0 size: 64MBytes */ + 0x00010000u, + /* Port_size: 32-bit */ + 0x02u}; + +#endif /* XIP_BOOT_HEADER_XMCD_ENABLE */ +#endif /* defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR) */ diff --git a/boards/phytec/phyboard_atlas/xmcd/xmcd.h b/boards/phytec/phyboard_atlas/xmcd/xmcd.h new file mode 100644 index 000000000000..82933b423917 --- /dev/null +++ b/boards/phytec/phyboard_atlas/xmcd/xmcd.h @@ -0,0 +1,13 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef XMCD_ +#define XMCD_ + +#include + +#endif /* XMCD_ */ diff --git a/boards/phytec/phyboard_nash/phyboard_nash_m33.dts b/boards/phytec/phyboard_nash/phyboard_nash_m33.dts index e1fcbe244b01..62f0b3a036f1 100644 --- a/boards/phytec/phyboard_nash/phyboard_nash_m33.dts +++ b/boards/phytec/phyboard_nash/phyboard_nash_m33.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "phyboard_nash-pinctrl.dtsi" / { diff --git a/boards/phytec/phyboard_polis/phyboard_polis_mimx8mm6_m4.dts b/boards/phytec/phyboard_polis/phyboard_polis_mimx8mm6_m4.dts index d48eed6f685b..e9ee0be44303 100644 --- a/boards/phytec/phyboard_polis/phyboard_polis_mimx8mm6_m4.dts +++ b/boards/phytec/phyboard_polis/phyboard_polis_mimx8mm6_m4.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "phyboard_polis-pinctrl.dtsi" / { diff --git a/boards/phytec/phyboard_pollux/doc/index.rst b/boards/phytec/phyboard_pollux/doc/index.rst index 17fadbd781d2..3e326c3745c0 100644 --- a/boards/phytec/phyboard_pollux/doc/index.rst +++ b/boards/phytec/phyboard_pollux/doc/index.rst @@ -111,9 +111,10 @@ GPIO The pinmuxing for the GPIOs is the standard pinmuxing of the mimx8mp devicetree created by NXP and can be found at -:zephyr_file:`dts/arm/nxp/nxp_imx8ml_m7.dtsi`. The Pinout of the phyBOARD-Polis +:zephyr_file:`dts/arm/nxp/imx/nxp_imx8ml_m7.dtsi`. The Pinout of the phyBOARD-Polis can be found at the `PHYTEC website`_. + I2C --- diff --git a/boards/phytec/phyboard_pollux/phyboard_pollux_mimx8ml8_m7.dts b/boards/phytec/phyboard_pollux/phyboard_pollux_mimx8ml8_m7.dts index ce0b98e49a23..668fe385ccf4 100644 --- a/boards/phytec/phyboard_pollux/phyboard_pollux_mimx8ml8_m7.dts +++ b/boards/phytec/phyboard_pollux/phyboard_pollux_mimx8ml8_m7.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include #include "phyboard_pollux-pinctrl.dtsi" diff --git a/boards/phytec/reel_board/doc/index.rst b/boards/phytec/reel_board/doc/index.rst index e710106dcc52..091f76ff0495 100644 --- a/boards/phytec/reel_board/doc/index.rst +++ b/boards/phytec/reel_board/doc/index.rst @@ -24,9 +24,9 @@ Zephyr OS in these kinds of use cases: * product, name or price tag * interactive badge for meetings and conferences -The board provides support for the Nordic Semiconductor nRF52840 ARM |reg| -Cortex |reg|-M4F SoC with an integrated 2.4 GHz transceiver supporting Bluetooth -|reg| Low Energy and IEEE |reg| 802.15.4. +The board provides support for the Nordic Semiconductor nRF52840 ARM® +Cortex®-M4F SoC with an integrated 2.4 GHz transceiver supporting Bluetooth® +Low Energy and IEEE® 802.15.4. The schematic can be found on the `reel board website`_. diff --git a/boards/phytec/reel_board/reel_board.dts b/boards/phytec/reel_board/reel_board.dts index 4c8997a1c4e4..b819d372cdc9 100644 --- a/boards/phytec/reel_board/reel_board.dts +++ b/boards/phytec/reel_board/reel_board.dts @@ -72,9 +72,9 @@ border-waveform = <0x71>; dummy-line = <0x1a>; gate-line-width = <0x08>; - lut = [22 55 AA 55 AA 55 AA 11 + lut = [22 55 aa 55 aa 55 aa 11 00 00 00 00 00 00 00 00 - 1E 1E 1E 1E 1E 1E 1E 1E + 1e 1e 1e 1e 1e 1e 1e 1e 01 00 00 00 00]; }; @@ -87,7 +87,7 @@ gate-line-width = <0x08>; lut = [18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - 0F 01 00 00 00 00 00 00 + 0f 01 00 00 00 00 00 00 00 00 00 00 00]; }; }; diff --git a/boards/phytec/reel_board/reel_board_nrf52840_2.overlay b/boards/phytec/reel_board/reel_board_nrf52840_2.overlay index d2766240872b..f2749f66f205 100644 --- a/boards/phytec/reel_board/reel_board_nrf52840_2.overlay +++ b/boards/phytec/reel_board/reel_board_nrf52840_2.overlay @@ -99,7 +99,7 @@ 40 00 00 00 00 00 00 /* LUT2: WB: VS0..6 */ 80 00 00 00 00 00 00 /* LUT3: WW: VS0..6 */ 00 00 00 00 00 00 00 /* LUT4: VCOM: VS0..6 */ - 0A 00 00 00 04 /* TP0A TP0B TP0C TP0D RP0 */ + 0a 00 00 00 04 /* TP0A TP0B TP0C TP0D RP0 */ 00 00 00 00 00 /* TP1A TP1B TP1C TP1D RP1 */ 00 00 00 00 00 /* TP2A TP2B TP2C TP2D RP2 */ 00 00 00 00 00 /* TP3A TP3B TP3C TP3D RP3 */ diff --git a/boards/pimoroni/pico_plus2/pico_plus2.dtsi b/boards/pimoroni/pico_plus2/pico_plus2.dtsi index 892b7e1e3b53..3497a3626261 100644 --- a/boards/pimoroni/pico_plus2/pico_plus2.dtsi +++ b/boards/pimoroni/pico_plus2/pico_plus2.dtsi @@ -144,10 +144,16 @@ zephyr_udc0: &usbd { pico_spi: &spi0 {}; +pico_spi0: &spi0 {}; + +pico_i2c: &i2c0 {}; + pico_i2c0: &i2c0 {}; pico_i2c1: &i2c1 {}; pico_serial: &uart0 {}; +pico_serial0: &uart0 {}; + zephyr_i2c: &i2c0 {}; diff --git a/boards/pimoroni/pico_plus2/pico_plus2_rp2350b_hazard3.yaml b/boards/pimoroni/pico_plus2/pico_plus2_rp2350b_hazard3.yaml index a36a820a21bc..4347a7f063cc 100644 --- a/boards/pimoroni/pico_plus2/pico_plus2_rp2350b_hazard3.yaml +++ b/boards/pimoroni/pico_plus2/pico_plus2_rp2350b_hazard3.yaml @@ -14,6 +14,10 @@ supported: - gpio - hwinfo - i2c + - pico_gpio + - pico_i2c + - pico_serial + - pico_spi - pwm - spi - usbd diff --git a/boards/pimoroni/pico_plus2/pico_plus2_rp2350b_m33.yaml b/boards/pimoroni/pico_plus2/pico_plus2_rp2350b_m33.yaml index a3ac06cff12c..c8713cfacee3 100644 --- a/boards/pimoroni/pico_plus2/pico_plus2_rp2350b_m33.yaml +++ b/boards/pimoroni/pico_plus2/pico_plus2_rp2350b_m33.yaml @@ -15,6 +15,10 @@ supported: - gpio - hwinfo - i2c + - pico_gpio + - pico_i2c + - pico_serial + - pico_spi - pwm - spi - usbd diff --git a/boards/pimoroni/tiny2040/Kconfig b/boards/pimoroni/tiny2040/Kconfig new file mode 100644 index 000000000000..f00270131578 --- /dev/null +++ b/boards/pimoroni/tiny2040/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2026 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_TINY2040 + select RP2_FLASH_W25Q080 diff --git a/boards/pimoroni/tiny2040/Kconfig.defconfig b/boards/pimoroni/tiny2040/Kconfig.defconfig new file mode 100644 index 000000000000..f6f207e10859 --- /dev/null +++ b/boards/pimoroni/tiny2040/Kconfig.defconfig @@ -0,0 +1,16 @@ +# Copyright (c) 2022 Peter Johanson +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_TINY2040 + +if I2C_DW + +config I2C_DW_CLOCK_SPEED + default 125 + +endif # I2C_DW + +config USB_SELF_POWERED + default n + +endif # BOARD_TINY2040 diff --git a/boards/pimoroni/tiny2040/Kconfig.tiny2040 b/boards/pimoroni/tiny2040/Kconfig.tiny2040 new file mode 100644 index 000000000000..aa88ea3dc72d --- /dev/null +++ b/boards/pimoroni/tiny2040/Kconfig.tiny2040 @@ -0,0 +1,5 @@ +# Copyright (c) 2026 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_TINY2040 + select SOC_RP2040 diff --git a/boards/pimoroni/tiny2040/board.cmake b/boards/pimoroni/tiny2040/board.cmake new file mode 100644 index 000000000000..414bfe8d9583 --- /dev/null +++ b/boards/pimoroni/tiny2040/board.cmake @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: Apache-2.0 +# Adapted from boards/raspberrypi/rpi_pico/board.cmake + +# This configuration allows selecting what debug adapter debugging rpi_pico +# by a command-line argument. +# It is mainly intended to support both the 'picoprobe' and 'raspberrypi-swd' +# adapter described in "Getting started with Raspberry Pi Pico". +# And any other SWD debug adapter might also be usable with this configuration. + +# Set RPI_PICO_DEBUG_ADAPTER to select debug adapter by command-line arguments. +# e.g.) west build -b rpi_pico -- -DRPI_PICO_DEBUG_ADAPTER=raspberrypi-swd +# The value is treated as a part of an interface file name that +# the debugger's configuration file. +# The value must be the 'stem' part of the name of one of the files +# in the openocd interface configuration file. +# The setting is stored to CMakeCache.txt. +if("${RPI_PICO_DEBUG_ADAPTER}" STREQUAL "") + set(RPI_PICO_DEBUG_ADAPTER "cmsis-dap") +endif() + +board_runner_args(openocd --cmd-pre-init "source [find interface/${RPI_PICO_DEBUG_ADAPTER}.cfg]") +board_runner_args(openocd --cmd-pre-init "transport select swd") +board_runner_args(openocd --cmd-pre-init "source [find target/rp2040.cfg]") + +# The adapter speed is expected to be set by interface configuration. +# But if not so, set 2000 to adapter speed. +board_runner_args(openocd --cmd-pre-init "set_adapter_speed_if_not_set 2000") + +board_runner_args(jlink "--device=RP2040_M0_0") +board_runner_args(uf2 "--board-id=RPI-RP2") +board_runner_args(pyocd "--target=rp2040") + +# Default runner should be listed first +include(${ZEPHYR_BASE}/boards/common/uf2.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/blackmagicprobe.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/pimoroni/tiny2040/board.yml b/boards/pimoroni/tiny2040/board.yml new file mode 100644 index 000000000000..92d431dfd464 --- /dev/null +++ b/boards/pimoroni/tiny2040/board.yml @@ -0,0 +1,6 @@ +board: + name: tiny2040 + full_name: Pimoroni Tiny 2040 + vendor: pimoroni + socs: + - name: rp2040 diff --git a/boards/pimoroni/tiny2040/doc/img/tiny2040.webp b/boards/pimoroni/tiny2040/doc/img/tiny2040.webp new file mode 100644 index 000000000000..ee61dff751ce Binary files /dev/null and b/boards/pimoroni/tiny2040/doc/img/tiny2040.webp differ diff --git a/boards/pimoroni/tiny2040/doc/index.rst b/boards/pimoroni/tiny2040/doc/index.rst new file mode 100644 index 000000000000..a452feb96c3f --- /dev/null +++ b/boards/pimoroni/tiny2040/doc/index.rst @@ -0,0 +1,128 @@ +.. zephyr:board:: tiny2040 + +Overview +******** + +The `Pimoroni Tiny 2040`_ board is based on the RP2040 microcontroller from Raspberry Pi Ltd. +The board has two 8-pin headers and a USB type C connector. + + +Hardware +******** + +- Microcontroller Raspberry Pi RP2040, with a max frequency of 133 MHz +- Dual ARM Cortex M0+ cores +- 264 kByte SRAM +- 8 Mbyte QSPI flash +- 8 GPIO pins +- 4 ADC pins +- I2C +- SPI +- UART +- USB type C connector +- Reset and boot buttons +- RGB user LED (red, green and blue controlled individually) + + +Default Zephyr Peripheral Mapping +================================= + ++---------------+--------+------------+ +| Description | Pin | Comments | ++===============+========+============+ +| Red LED | GPIO18 | Alias led0 | ++---------------+--------+------------+ +| Green LED | GPIO19 | Alias led1 | ++---------------+--------+------------+ +| Blue LED | GPIO20 | Alias led2 | ++---------------+--------+------------+ +| BOOT button | GPIO23 | Alias sw0 | ++---------------+--------+------------+ + + +GPIO header: + ++-------+--------+-----------------+ +| Label | Pin | Default pin mux | ++=======+========+=================+ +| 0 | GPIO0 | UART0 TX | ++-------+--------+-----------------+ +| 1 | GPIO1 | UART0 RX | ++-------+--------+-----------------+ +| 2 | GPIO2 | I2C1 SDA | ++-------+--------+-----------------+ +| 3 | GPIO3 | I2C1 SCL | ++-------+--------+-----------------+ +| 4 | GPIO4 | | ++-------+--------+-----------------+ +| 5 | GPIO5 | | ++-------+--------+-----------------+ +| 6 | GPIO6 | | ++-------+--------+-----------------+ +| 7 | GPIO7 | | ++-------+--------+-----------------+ +| A0 | GPIO26 | ADC0 | ++-------+--------+-----------------+ +| A1 | GPIO27 | ADC1 | ++-------+--------+-----------------+ +| A2 | GPIO28 | ADC2 | ++-------+--------+-----------------+ +| A3 | GPIO29 | ADC3 | ++-------+--------+-----------------+ + +See also `schematic`_. + + +Supported Features +================== + +.. zephyr:board-supported-hw:: + + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +By default programming is done via the USB connector. Press and hold the BOOT button, and then +press the RST button, and the device will appear as a USB mass storage unit. +Building your application will result in a :file:`build/zephyr/zephyr.uf2` file. +Drag and drop the file to the USB mass storage unit, and the board will be reprogrammed. + +It is also possible to program and debug the board via the SWDIO and SWCLK pins. +Then a separate programming hardware tool is required, and for example the :command:`openocd` +software is used. Typically the ``OPENOCD`` and ``OPENOCD_DEFAULT_PATH`` values should be set +when building, and the ``--runner openocd`` argument should be used when flashing. +For more details on programming RP2040-based boards, see :ref:`rpi_pico_programming_and_debugging`. + + +Flashing +======== + +To run the :zephyr:code-sample:`blinky` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky/ + :board: tiny2040 + :goals: build flash + +Note that the red, green and blue parts of the RGB LED are controlled individually by GPIO pins. +By default the red color is blinking when running the sample. The sample does not configure the +GPIO pins for the green and blue parts, which is why these might show a dim light. +See the implementation for the :zephyr:code-sample:`blinky` how the configuration is done, +if you would like to control the other colors. + +Try also the :zephyr:code-sample:`hello_world`, :zephyr:code-sample:`button`, +:zephyr:code-sample:`input-dump` and :zephyr:code-sample:`adc_dt` samples. + + +References +********** + +.. target-notes:: + +.. _Pimoroni Tiny 2040: + https://shop.pimoroni.com/products/tiny-2040 + +.. _schematic: + https://cdn.shopify.com/s/files/1/0174/1800/files/Tiny2040_PIM558_schematic.pdf diff --git a/boards/pimoroni/tiny2040/support/openocd.cfg b/boards/pimoroni/tiny2040/support/openocd.cfg new file mode 100644 index 000000000000..34ab592b1861 --- /dev/null +++ b/boards/pimoroni/tiny2040/support/openocd.cfg @@ -0,0 +1,11 @@ +# Copyright (c) 2022 Tokita, Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +# Checking and set 'adapter speed'. +# Set the adaptor speed, if unset, and given as an argument. +proc set_adapter_speed_if_not_set { speed } { + puts "checking adapter speed..." + if { [catch {adapter speed} ret] } { + adapter speed $speed + } +} diff --git a/boards/pimoroni/tiny2040/tiny2040-pinctrl.dtsi b/boards/pimoroni/tiny2040/tiny2040-pinctrl.dtsi new file mode 100644 index 000000000000..a1f7d743ead3 --- /dev/null +++ b/boards/pimoroni/tiny2040/tiny2040-pinctrl.dtsi @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2026 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + uart0_default: uart0_default { + group1 { + pinmux = ; + }; + + group2 { + pinmux = ; + input-enable; + }; + }; + + i2c1_default: i2c1_default { + group1 { + pinmux = , ; + input-enable; + }; + }; + + adc_default: adc_default { + group1 { + pinmux = , , , ; + input-enable; + }; + }; +}; diff --git a/boards/pimoroni/tiny2040/tiny2040.dts b/boards/pimoroni/tiny2040/tiny2040.dts new file mode 100644 index 000000000000..99d6e714511c --- /dev/null +++ b/boards/pimoroni/tiny2040/tiny2040.dts @@ -0,0 +1,180 @@ +/* + * Copyright (c) 2021 Yonatan Schachter + * Copyright (c) 2022 Peter Johanson + * Copyright (c) 2026 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "tiny2040-pinctrl.dtsi" + +/ { + model = "Pimoroni Tiny 2040"; + compatible = "pimoroni,tiny2040"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,flash-controller = &ssi; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,code-partition = &code_partition; + }; + + aliases { + watchdog0 = &wdt0; + led0 = &red_led; + led1 = &green_led; + led2 = &blue_led; + sw0 = &boot_button; + }; + + zephyr,user { + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>; + }; + + leds: leds { + compatible = "gpio-leds"; + + red_led: red_led { + gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; + label = "Red LED"; + }; + + green_led: green_led { + gpios = <&gpio0 19 GPIO_ACTIVE_LOW>; + label = "Green LED"; + }; + + blue_led: blue_led { + gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; + label = "Blue LED"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + boot_button: boot_button { + label = "Boot button"; + gpios = <&gpio0 23 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + zephyr,code = ; + }; + }; +}; + +&flash0 { + reg = <0x10000000 DT_SIZE_M(8)>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserved memory for the second stage bootloader */ + second_stage_bootloader: partition@0 { + label = "second_stage_bootloader"; + reg = <0x00000000 0x100>; + read-only; + }; + + /* + * Usable flash. Starts at 0x100, after the bootloader. The partition + * size is 8 MB minus the 0x100 bytes taken by the bootloader. + */ + code_partition: partition@100 { + label = "code-partition"; + reg = <0x100 (DT_SIZE_M(8) - 0x100)>; + read-only; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&uart0 { + current-speed = <115200>; + status = "okay"; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&i2c1 { + status = "okay"; + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; + clock-frequency = ; +}; + +&timer { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&adc { + status = "okay"; + pinctrl-0 = <&adc_default>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; + + channel@1 { + reg = <1>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; + + channel@2 { + reg = <2>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; + + channel@3 { + reg = <3>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; +}; + +zephyr_udc0: &usbd { + status = "okay"; +}; + +&die_temp { + status = "okay"; +}; + +&vreg { + regulator-always-on; + regulator-allowed-modes = ; +}; + +&xosc { + startup-delay-multiplier = <64>; +}; diff --git a/boards/pimoroni/tiny2040/tiny2040.yaml b/boards/pimoroni/tiny2040/tiny2040.yaml new file mode 100644 index 000000000000..91f7ce5f08d5 --- /dev/null +++ b/boards/pimoroni/tiny2040/tiny2040.yaml @@ -0,0 +1,22 @@ +identifier: tiny2040 +name: Pimoroni Tiny 2040 +type: mcu +arch: arm +flash: 8192 +ram: 264 +toolchain: + - zephyr + - gnuarmemb +supported: + - adc + - clock + - counter + - dma + - flash + - gpio + - hwinfo + - i2c + - pwm + - spi + - uart + - watchdog diff --git a/boards/pimoroni/tiny2040/tiny2040_defconfig b/boards/pimoroni/tiny2040/tiny2040_defconfig new file mode 100644 index 000000000000..85b60ee95c5a --- /dev/null +++ b/boards/pimoroni/tiny2040/tiny2040_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2026 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_OUTPUT_UF2=y +CONFIG_CLOCK_CONTROL=y +CONFIG_CONSOLE=y +CONFIG_GPIO=y +CONFIG_RESET=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/pine64/pinetime_devkit0/pinetime_devkit0.dts b/boards/pine64/pinetime_devkit0/pinetime_devkit0.dts index e5a3cd0473f6..b69c5ddfb328 100644 --- a/boards/pine64/pinetime_devkit0/pinetime_devkit0.dts +++ b/boards/pine64/pinetime_devkit0/pinetime_devkit0.dts @@ -109,10 +109,10 @@ porch-param = [0c 0c 00 33 33]; cmd2en-param = [5a 69 02 01]; pwctrl1-param = [a4 a1]; - pvgam-param = [D0 04 0D 11 13 2B 3F 54 4C 18 0D 0B 1F 23]; - nvgam-param = [D0 04 0C 11 13 2C 3F 44 51 2F 1F 1F 20 23]; - ram-param = [00 F0]; - rgb-param = [CD 08 14]; + pvgam-param = [d0 04 0d 11 13 2b 3f 54 4c 18 0d 0b 1f 23]; + nvgam-param = [d0 04 0c 11 13 2c 3f 44 51 2f 1f 1f 20 23]; + ram-param = [00 f0]; + rgb-param = [cd 08 14]; mipi-mode = "MIPI_DBI_MODE_SPI_4WIRE"; }; }; @@ -236,7 +236,7 @@ /* main firmware partition */ slot0_partition: partition@c000 { label = "image-0"; - reg = <0x0000C000 0x74000>; + reg = <0x0000c000 0x74000>; }; }; }; diff --git a/boards/pjrc/teensy4/teensy40.dts b/boards/pjrc/teensy4/teensy40.dts index 463da4002e85..8acf032186aa 100644 --- a/boards/pjrc/teensy4/teensy40.dts +++ b/boards/pjrc/teensy4/teensy40.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "teensy4-pinctrl.dtsi" #include #include diff --git a/boards/pjrc/teensy4/teensy41.dts b/boards/pjrc/teensy4/teensy41.dts index e2f43dccf972..79633f987486 100644 --- a/boards/pjrc/teensy4/teensy41.dts +++ b/boards/pjrc/teensy4/teensy41.dts @@ -9,6 +9,10 @@ / { model = "PJRC TEENSY 4.1 board"; + aliases { + sdhc0 = &usdhc1; + }; + chosen { zephyr,flash-controller = &w25q64jvxgim; zephyr,flash = &w25q64jvxgim; diff --git a/boards/qemu/riscv32_xip/Kconfig.qemu_riscv32_xip b/boards/qemu/riscv32_xip/Kconfig.qemu_riscv32_xip index 69842cdb1834..36efd8301aef 100644 --- a/boards/qemu/riscv32_xip/Kconfig.qemu_riscv32_xip +++ b/boards/qemu/riscv32_xip/Kconfig.qemu_riscv32_xip @@ -2,4 +2,4 @@ # SPDX-License-Identifier: Apache-2.0 config BOARD_QEMU_RISCV32_XIP - select SOC_SIFIVE_FREEDOM_FE310_G002 + select SOC_FE310_G002 diff --git a/boards/qemu/riscv32e/qemu_riscv32e.dts b/boards/qemu/riscv32e/qemu_riscv32e.dts index 403d75cb7420..0ed55c7a965f 100644 --- a/boards/qemu/riscv32e/qemu_riscv32e.dts +++ b/boards/qemu/riscv32e/qemu_riscv32e.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include +#include / { chosen { diff --git a/boards/qorvo/decawave_dwm1001_dev/decawave_dwm1001_dev.dts b/boards/qorvo/decawave_dwm1001_dev/decawave_dwm1001_dev.dts index d78f4df1f20f..ea8021b88644 100644 --- a/boards/qorvo/decawave_dwm1001_dev/decawave_dwm1001_dev.dts +++ b/boards/qorvo/decawave_dwm1001_dev/decawave_dwm1001_dev.dts @@ -178,12 +178,12 @@ slot0_partition: partition@c000 { label = "image-0"; - reg = <0x0000C000 0x32000>; + reg = <0x0000c000 0x32000>; }; slot1_partition: partition@3e000 { label = "image-1"; - reg = <0x0003E000 0x32000>; + reg = <0x0003e000 0x32000>; }; scratch_partition: partition@70000 { diff --git a/boards/qorvo/decawave_dwm3001cdk/decawave_dwm3001cdk.dts b/boards/qorvo/decawave_dwm3001cdk/decawave_dwm3001cdk.dts index 9ce633a01c63..44481be48bd6 100644 --- a/boards/qorvo/decawave_dwm3001cdk/decawave_dwm3001cdk.dts +++ b/boards/qorvo/decawave_dwm3001cdk/decawave_dwm3001cdk.dts @@ -139,12 +139,12 @@ boot_partition: partition@0 { label = "mcuboot"; - reg = <0x00000000 0xC000>; + reg = <0x00000000 0xc000>; }; slot0_partition: partition@c000 { label = "image-0"; - reg = <0x0000C000 0x38000>; + reg = <0x0000c000 0x38000>; }; slot1_partition: partition@44000 { @@ -154,7 +154,7 @@ storage_partition: partition@7a000 { label = "storage"; - reg = <0x0007A000 0x00006000>; + reg = <0x0007a000 0x00006000>; }; }; }; diff --git a/boards/rakwireless/rak11160/Kconfig.rak11160 b/boards/rakwireless/rak11160/Kconfig.rak11160 new file mode 100644 index 000000000000..cf75f12d0a7e --- /dev/null +++ b/boards/rakwireless/rak11160/Kconfig.rak11160 @@ -0,0 +1,5 @@ +# Copyright (c) 2025 RAKwireless Technology Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RAK11160 + select SOC_STM32WLE5XX diff --git a/boards/rakwireless/rak11160/board.cmake b/boards/rakwireless/rak11160/board.cmake new file mode 100644 index 000000000000..d343c2f98fb9 --- /dev/null +++ b/boards/rakwireless/rak11160/board.cmake @@ -0,0 +1,12 @@ +# Copyright (c) 2025 RAKwireless Technology Co., Ltd. +# Sercan Erat +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(pyocd "--target=stm32wle5ccux") +board_runner_args(pyocd "--flash-opt=-O cmsis_dap.limit_packets=1") +board_runner_args(jlink "--device=STM32WLE5CC" "--speed=4000" "--reset-after-load") +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") + +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/rakwireless/rak11160/board.yml b/boards/rakwireless/rak11160/board.yml new file mode 100644 index 000000000000..dba3f6317cb7 --- /dev/null +++ b/boards/rakwireless/rak11160/board.yml @@ -0,0 +1,6 @@ +board: + name: rak11160 + full_name: RAK11160 + vendor: rakwireless + socs: + - name: stm32wle5xx diff --git a/boards/rakwireless/rak11160/doc/img/rak11160.webp b/boards/rakwireless/rak11160/doc/img/rak11160.webp new file mode 100644 index 000000000000..da2acb5aa0bc Binary files /dev/null and b/boards/rakwireless/rak11160/doc/img/rak11160.webp differ diff --git a/boards/rakwireless/rak11160/doc/index.rst b/boards/rakwireless/rak11160/doc/index.rst new file mode 100644 index 000000000000..c53d259b9bb3 --- /dev/null +++ b/boards/rakwireless/rak11160/doc/index.rst @@ -0,0 +1,79 @@ +.. zephyr:board:: rak11160 + +Overview +******** + +RAK11160 is a WisDuo module based on the STM32WLE5 MCU with integrated LoRa +transceiver. It uses an Espressif ESP8684H2 co-processor to support Bluetooth +and WiFi connectivity. This module is ideal for various IoT applications such as +home automation, sensor networks, building automation, and other IoT network +applications. + +Hardware +******** + +The module has below hardware features: +- STM32WLE5CC MCU with LPWAN single-core Cortex®-M4 at 48 MHz +- 256-Kbyte Flash memory and 64-Kbyte SRAM +- RF transceiver LoRa® modulations +- Hardware encryption AES256-bit and a true random number generator +- SMA connectors for the LORA antenna and BLE/WiFi antenna +- 32-bit single core RISC-V ESP8684 MCU +- 2 MB in ESP8684 MCU flash +- ESP8684 MCU support 802.11b/g/n +- A Bluetooth LE subsystem that supports features of Bluetooth 5 and Bluetooth Mesh + +.. image:: img/rak11160.webp + :align: center + :alt: RAK11160-pinout + +For more information about the RAK3112 stamp module: + +- `WisDuo RAK11160 Website`_ +- `STM32WLE5CC on www.st.com`_ +- `ESP8684 on www.espressif.com`_ + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Building & Flashing +******************* + +.. zephyr:board-supported-runners:: + +Connect the board to your host computer and build and flash an application. +The sample application :zephyr:code-sample:`hello_world` is used for this example. +Build the Zephyr kernel and application, then flash it to the device: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rak11160 + :goals: build flash + +Run a serial terminal to connect with your board. By default, ``usart1`` is +accessible via the USB to TTL converter. + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +.. code-block:: console + + Hello World! rak11160/stm32wle5xx + +References +********** + +.. target-notes:: + +.. _WisDuo RAK11160 Website: + https://docs.rakwireless.com/product-categories/wisduo/rak11160-module/overview + +.. _STM32WLE5CC on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32wle5cc.html + +.. _ESP8684 on www.espressif.com: + https://www.espressif.com/sites/default/files/documentation/esp8684_datasheet_en.pdf diff --git a/boards/rakwireless/rak11160/rak11160.dts b/boards/rakwireless/rak11160/rak11160.dts new file mode 100644 index 000000000000..bdb1c0ff2346 --- /dev/null +++ b/boards/rakwireless/rak11160/rak11160.dts @@ -0,0 +1,174 @@ +/* + * Copyright (c) 2025 RAKwireless Technology Co., Ltd. + * Sercan Erat + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include + +/ { + model = "RAKWireless RAK11160 WisDuo LPWAN Module"; + compatible = "stm32,rak11160_stm32wl"; + + chosen { + zephyr,console = &usart1; + zephyr,shell-uart = &usart1; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; + + leds { + compatible = "gpio-leds"; + + blue_led: led_2 { + gpios = <&gpioa 1 GPIO_ACTIVE_HIGH>; + label = "Blue LED"; + }; + + green_led: led_1 { + gpios = <&gpioa 10 GPIO_ACTIVE_HIGH>; + label = "Green LED"; + }; + }; + + /* Regulator controlling ESP8684 enable */ + esp8684_enable: esp8684-enable { + compatible = "regulator-fixed"; + regulator-name = "esp8684_enable"; + enable-gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>; + regulator-boot-off; + }; + + aliases { + led0 = &green_led; + lora0 = &lora; + watchdog0 = &iwdg; + }; +}; + +&pll { + div-m = <1>; + mul-n = <3>; + div-r = <2>; + div-q = <2>; + clocks = <&clk_hse>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; + clock-frequency = ; + cpu1-prescaler = <1>; + ahb3-prescaler = <1>; + apb1-prescaler = <1>; + apb2-prescaler = <1>; +}; + +&clk_hse { + status = "okay"; + clock-frequency = ; + hse-tcxo; +}; + +&clk_lse { + status = "okay"; + clock-frequency = <32768>; +}; + +&subghzspi { + status = "okay"; + + lora: radio@0 { + status = "okay"; + antenna-enable-gpios = <&gpiob 8 GPIO_ACTIVE_HIGH>; + tx-enable-gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>; + rx-enable-gpios = <&gpioc 13 GPIO_ACTIVE_LOW>; + dio3-tcxo-voltage = ; + tcxo-power-startup-delay-ms = <5>; + power-amplifier-output = "rfo-hp"; + rfo-hp-max-power = <22>; + }; +}; + +&usart1 { + pinctrl-0 = <&usart1_tx_pb6 &usart1_rx_pb7>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; + + espc2 { + compatible = "espressif,esp-at"; + status = "okay"; + }; +}; + +&usart2 { + pinctrl-0 = <&usart2_tx_pa2 &usart2_rx_pa3>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_scl_pa12 &i2c2_sda_pa11>; + pinctrl-names = "default"; + status = "okay"; + clock-frequency = ; +}; + +&spi1 { + pinctrl-0 = <&spi1_nss_pa4 &spi1_sck_pa5 + &spi1_miso_pa6 &spi1_mosi_pa7>; + pinctrl-names = "default"; + status = "okay"; +}; + +&rtc { + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>, + <&rcc STM32_SRC_LSE RTC_SEL(1)>; + status = "okay"; +}; + +&iwdg { + status = "okay"; +}; + +&aes { + status = "okay"; +}; + +&rng { + status = "okay"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(32)>; + read-only; + }; + + slot0_partition: partition@8000 { + label = "image-0"; + reg = <0x00008000 DT_SIZE_K(108)>; + }; + + slot1_partition: partition@23000 { + label = "image-1"; + reg = <0x00023000 DT_SIZE_K(108)>; + }; + + storage_partition: partition@3e000 { + label = "storage"; + reg = <0x0003e000 DT_SIZE_K(8)>; + }; + }; +}; diff --git a/boards/rakwireless/rak11160/rak11160.yaml b/boards/rakwireless/rak11160/rak11160.yaml new file mode 100644 index 000000000000..f7975116da64 --- /dev/null +++ b/boards/rakwireless/rak11160/rak11160.yaml @@ -0,0 +1,19 @@ +identifier: rak11160 +name: RAK11160 +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +ram: 64 +flash: 256 +supported: + - counter + - gpio + - i2c + - nvs + - spi + - uart + - watchdog + - lora +vendor: rak diff --git a/boards/rakwireless/rak11160/rak11160_defconfig b/boards/rakwireless/rak11160/rak11160_defconfig new file mode 100644 index 000000000000..a5fbfda97edb --- /dev/null +++ b/boards/rakwireless/rak11160/rak11160_defconfig @@ -0,0 +1,21 @@ +# Enable UART driver +CONFIG_SERIAL=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable Clocks +CONFIG_CLOCK_CONTROL=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Regulator +CONFIG_REGULATOR=y diff --git a/boards/rakwireless/rak3112/support/openocd.cfg b/boards/rakwireless/rak3112/support/openocd.cfg index 2f740b4a36ab..b45e13c53d01 100644 --- a/boards/rakwireless/rak3112/support/openocd.cfg +++ b/boards/rakwireless/rak3112/support/openocd.cfg @@ -1,5 +1,5 @@ -set ESP_RTOS none -set ESP32_ONLYCPU 1 +set ESP_RTOS Zephyr +set ESP_ONLYCPU 1 # Source the JTAG interface configuration file source [find interface/esp_usb_jtag.cfg] diff --git a/boards/raspberrypi/rpi_4b/CMakeLists.txt b/boards/raspberrypi/rpi_4b/CMakeLists.txt deleted file mode 100644 index 9881313609aa..000000000000 --- a/boards/raspberrypi/rpi_4b/CMakeLists.txt +++ /dev/null @@ -1 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/raspberrypi/rpi_4b/Kconfig.defconfig b/boards/raspberrypi/rpi_4b/Kconfig.defconfig deleted file mode 100644 index 70e623172483..000000000000 --- a/boards/raspberrypi/rpi_4b/Kconfig.defconfig +++ /dev/null @@ -1,2 +0,0 @@ -# Copyright 2023 honglin leng -# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/raspberrypi/rpi_4b/board.cmake b/boards/raspberrypi/rpi_4b/board.cmake deleted file mode 100644 index 9881313609aa..000000000000 --- a/boards/raspberrypi/rpi_4b/board.cmake +++ /dev/null @@ -1 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/raspberrypi/rpi_4b/doc/img/rpi_4b.webp b/boards/raspberrypi/rpi_4b/doc/img/rpi_4b.webp new file mode 100644 index 000000000000..0515d8858e70 Binary files /dev/null and b/boards/raspberrypi/rpi_4b/doc/img/rpi_4b.webp differ diff --git a/boards/raspberrypi/rpi_4b/doc/index.rst b/boards/raspberrypi/rpi_4b/doc/index.rst index b0c658faf2d3..8a4b2751a961 100644 --- a/boards/raspberrypi/rpi_4b/doc/index.rst +++ b/boards/raspberrypi/rpi_4b/doc/index.rst @@ -2,11 +2,30 @@ Overview ******** -see + +The `Raspberry Pi 4`_ is the fourth generation of the Raspberry Pi flagship series of +single-board computers. It is based on the Broadcom BCM2711 SoC which features a +quad-core 64-bit ARM Cortex-A72 CPU and is available in 1, 2, 4 or 8 GB of LPDDR4 RAM. Hardware ******** -see + +- Broadcom BCM2711, Quad core Cortex-A72 (ARM v8) 64-bit SoC @ 1.8GHz +- 1GB, 2GB, 4GB or 8GB LPDDR4-3200 SDRAM (depending on model) +- 2.4 GHz and 5.0 GHz IEEE 802.11ac wireless, Bluetooth 5.0, BLE +- Gigabit Ethernet +- 2 USB 3.0 ports; 2 USB 2.0 ports. +- Raspberry Pi standard 40 pin GPIO header (fully backwards compatible with previous boards) +- 2 × micro-HDMI® ports (up to 4kp60 supported) +- 2-lane MIPI DSI display port +- 2-lane MIPI CSI camera port +- 4-pole stereo audio and composite video port +- H.265 (4kp60 decode), H264 (1080p60 decode, 1080p30 encode) +- OpenGL ES 3.1, Vulkan 1.0 +- Micro-SD card slot for loading operating system and data storage +- 5V DC via USB-C connector (minimum 3A) +- 5V DC via GPIO header (minimum 3A) +- Power over Ethernet (PoE) enabled (requires separate PoE HAT) Supported Features ================== @@ -46,3 +65,14 @@ the serial console (GPIO 14/15): *** Booting Zephyr OS build XXXXXXXXXXXX *** Hello World! Raspberry Pi 4 Model B! + +References +********** + +.. target-notes:: + +.. _Raspberry Pi 4: + https://pip.raspberrypi.com/documents/RP-008344-DS-raspberry-pi-4-product-brief.pdf/ + +.. _Raspberry Pi 4 Schematic: + https://datasheets.raspberrypi.com/rpi4/raspberry-pi-4-reduced-schematics.pdf diff --git a/boards/raspberrypi/rpi_4b/rpi_4b.dts b/boards/raspberrypi/rpi_4b/rpi_4b.dts index e7e1faad4357..822da49a559d 100644 --- a/boards/raspberrypi/rpi_4b/rpi_4b.dts +++ b/boards/raspberrypi/rpi_4b/rpi_4b.dts @@ -11,7 +11,7 @@ / { model = "Raspberry Pi 4 Model B"; - compatible = "raspberrypi,4-model-b", "brcm,bcm2838"; + compatible = "raspberrypi,4-model-b", "brcm,bcm2711"; #address-cells = <1>; #size-cells = <1>; diff --git a/boards/raspberrypi/rpi_5/doc/index.rst b/boards/raspberrypi/rpi_5/doc/index.rst index e73e65570dbe..9b1a99f4a52a 100644 --- a/boards/raspberrypi/rpi_5/doc/index.rst +++ b/boards/raspberrypi/rpi_5/doc/index.rst @@ -12,7 +12,7 @@ Hardware - VideoCore VII GPU, supporting OpenGL ES 3.1, Vulkan 1.2 - Dual 4Kp60 HDMI® display output with HDR support - 4Kp60 HEVC decoder -- LPDDR4X-4267 SDRAM (4GB and 8GB SKUs available at launch) +- LPDDR4X-4267 SDRAM (1GB, 2GB, 4GB, 8GB and 16GB SKUs available) - Dual-band 802.11ac Wi-Fi® - Bluetooth 5.0 / Bluetooth Low Energy (BLE) - microSD card slot, with support for high-speed SDR104 mode @@ -46,7 +46,7 @@ In brief, 2. Save three files below in the root directory. * config.txt * zephyr.bin - * `bcm2712-rpi-5.dtb`_ + * `bcm2712-rpi-5-b.dtb`_ 3. Insert the Micro SD card and power on the Raspberry Pi 5. then, You will see the Raspberry Pi 5 running the :file:`zephyr.bin`. @@ -57,7 +57,6 @@ config.txt .. code-block:: text kernel=zephyr.bin - arm_64bit=1 zephyr.bin @@ -98,7 +97,6 @@ config.txt .. code-block:: text kernel=zephyr.bin - arm_64bit=1 enable_uart=1 uart_2ndstage=1 @@ -135,8 +133,29 @@ When you power on the Raspberry Pi 5, you will see the following output in the s .. _Raspberry Pi hardware: https://www.raspberrypi.com/documentation/computers/raspberry-pi.html -.. _bcm2712-rpi-5.dtb: +.. _bcm2712-rpi-5-b.dtb: https://github.com/raspberrypi/firmware/raw/master/boot/bcm2712-rpi-5-b.dtb .. _Raspberry Pi Debug Probe: https://www.raspberrypi.com/products/debug-probe/ + +XEN Dom0 +======== + +The Raspberry Pi 5 platform can be used to run as Xen Zephyr Dom0. For such +purposes the ``xen_dom0`` snippet can be used. + +Run below command as an example of RPI 5 Zephyr build as Dom0: + +.. code-block:: bash + + west build -b rpi_5 -p always -S xen_dom0 samples/hello_world + +It is expected to be used with special application performing Xen Domain-0/Dom0 functions. + +.. note:: + + The "hypervisor@x" and "memory@x" DT nodes need to be specified in + DT application overlay with values provided on the Xen boot, because + normaly Xen will update DT for the target Kernel, but this is not possible + in case of Zephyr. More details described in :ref:`xen_dom0`. diff --git a/boards/raspberrypi/rpi_5/rpi_5.dts b/boards/raspberrypi/rpi_5/rpi_5_bcm2712.dts similarity index 100% rename from boards/raspberrypi/rpi_5/rpi_5.dts rename to boards/raspberrypi/rpi_5/rpi_5_bcm2712.dts diff --git a/boards/raspberrypi/rpi_5/rpi_5.yaml b/boards/raspberrypi/rpi_5/rpi_5_bcm2712.yaml similarity index 100% rename from boards/raspberrypi/rpi_5/rpi_5.yaml rename to boards/raspberrypi/rpi_5/rpi_5_bcm2712.yaml diff --git a/boards/raspberrypi/rpi_5/rpi_5_defconfig b/boards/raspberrypi/rpi_5/rpi_5_bcm2712_defconfig similarity index 100% rename from boards/raspberrypi/rpi_5/rpi_5_defconfig rename to boards/raspberrypi/rpi_5/rpi_5_bcm2712_defconfig diff --git a/boards/raspberrypi/rpi_pico/rpi_pico-common.dtsi b/boards/raspberrypi/rpi_pico/rpi_pico-common.dtsi index d333fdd57b51..21a45a13114e 100644 --- a/boards/raspberrypi/rpi_pico/rpi_pico-common.dtsi +++ b/boards/raspberrypi/rpi_pico/rpi_pico-common.dtsi @@ -155,8 +155,14 @@ zephyr_udc0: &usbd { pico_spi: &spi0 {}; +pico_spi0: &spi0 {}; + +pico_i2c: &i2c0 {}; + pico_i2c0: &i2c0 {}; pico_i2c1: &i2c1 {}; pico_serial: &uart0 {}; + +pico_serial0: &uart0 {}; diff --git a/boards/raspberrypi/rpi_pico/rpi_pico.yaml b/boards/raspberrypi/rpi_pico/rpi_pico.yaml index 03e2673ce72c..345b3ed6601d 100644 --- a/boards/raspberrypi/rpi_pico/rpi_pico.yaml +++ b/boards/raspberrypi/rpi_pico/rpi_pico.yaml @@ -8,6 +8,10 @@ toolchain: - zephyr - gnuarmemb supported: + - pico_gpio + - pico_i2c + - pico_spi + - pico_serial - uart - gpio - adc diff --git a/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_mcuboot.yaml b/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_mcuboot.yaml index 217130faea82..a9c6cdede5e6 100644 --- a/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_mcuboot.yaml +++ b/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_mcuboot.yaml @@ -8,6 +8,10 @@ toolchain: - zephyr - gnuarmemb supported: + - pico_gpio + - pico_i2c + - pico_spi + - pico_serial - uart - gpio - adc diff --git a/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w.yaml b/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w.yaml index f06ac1ce74cf..f5557978ed00 100644 --- a/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w.yaml +++ b/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w.yaml @@ -8,6 +8,10 @@ toolchain: - zephyr - gnuarmemb supported: + - pico_gpio + - pico_i2c + - pico_spi + - pico_serial - uart - gpio - adc diff --git a/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w_mcuboot.yaml b/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w_mcuboot.yaml index 9471ae9fdd95..e32ea3190a40 100644 --- a/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w_mcuboot.yaml +++ b/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w_mcuboot.yaml @@ -8,6 +8,10 @@ toolchain: - zephyr - gnuarmemb supported: + - pico_gpio + - pico_i2c + - pico_spi + - pico_serial - uart - gpio - adc diff --git a/boards/raspberrypi/rpi_pico2/Kconfig.defconfig b/boards/raspberrypi/rpi_pico2/Kconfig.defconfig index f0c7c0a89a24..c18d88b8eb4f 100644 --- a/boards/raspberrypi/rpi_pico2/Kconfig.defconfig +++ b/boards/raspberrypi/rpi_pico2/Kconfig.defconfig @@ -17,4 +17,11 @@ config WHD_DISABLE_SDIO_PULLUP_DURING_SPI_SLEEP endif # WIFI_AIROC +if I2C_DW + +config I2C_DW_CLOCK_SPEED + default 150 + +endif # I2C_DW + endif # BOARD_RPI_PICO2 diff --git a/boards/raspberrypi/rpi_pico2/doc/index.rst b/boards/raspberrypi/rpi_pico2/doc/index.rst index 8d542955735f..437743a206a7 100644 --- a/boards/raspberrypi/rpi_pico2/doc/index.rst +++ b/boards/raspberrypi/rpi_pico2/doc/index.rst @@ -55,7 +55,32 @@ Below is an example of building and flashing the :zephyr:code-sample:`blinky` ap :goals: build flash :flash-args: --openocd /usr/local/bin/openocd -The blinky sample is not yet supported on Pico 2W, so try the :zephyr:code-sample:`wifi-shell` application to connect to the network: +The blinky sample is not yet supported on Pico 2W, so try the :zephyr:code-sample:`wifi-shell` application to connect to the network. + +Wi-Fi Firmware Setup +===================== + +Before building applications for the Pico 2W variant, you must fetch the required Wi-Fi firmware blobs. +The Infineon CYW43439 chip requires proprietary firmware and CLM (Country Localization Module) files. + +Run the following command to download these blobs: + +.. code-block:: console + + west blobs fetch hal_infineon + +This command downloads the necessary firmware files from Infineon's repositories, including: + +- ``43439A0.bin`` - Wi-Fi firmware for CYW43439 +- ``43439A0.clm_blob`` - Country localization data + +You only need to run this command once per workspace. Without these blobs, the build will fail with +CMake errors about missing firmware files. + +Building Wi-Fi Applications +============================ + +After fetching the blobs, you can build Wi-Fi applications: .. zephyr-app-commands:: :zephyr-app: samples/net/wifi/shell diff --git a/boards/raspberrypi/rpi_pico2/rpi_pico2.dtsi b/boards/raspberrypi/rpi_pico2/rpi_pico2.dtsi index 12f9c5ed44d4..6f951b1a24e3 100644 --- a/boards/raspberrypi/rpi_pico2/rpi_pico2.dtsi +++ b/boards/raspberrypi/rpi_pico2/rpi_pico2.dtsi @@ -113,8 +113,24 @@ gpio0_lo: &gpio0 { status = "okay"; }; +&rng { + status = "okay"; +}; + zephyr_udc0: &usbd { status = "okay"; }; +pico_spi: &spi0 {}; + +pico_spi0: &spi0 {}; + +pico_i2c: &i2c0 {}; + +pico_i2c0: &i2c0 {}; + +pico_i2c1: &i2c1 {}; + pico_serial: &uart0 {}; + +pico_serial0: &uart0 {}; diff --git a/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_hazard3.yaml b/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_hazard3.yaml index 3f6a61329ee1..52f70031db07 100644 --- a/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_hazard3.yaml +++ b/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_hazard3.yaml @@ -14,6 +14,10 @@ supported: - gpio - hwinfo - i2c + - pico_gpio + - pico_i2c + - pico_serial + - pico_spi - pwm - spi - uart diff --git a/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33.yaml b/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33.yaml index f83082393e07..2229e95c912c 100644 --- a/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33.yaml +++ b/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33.yaml @@ -11,10 +11,16 @@ supported: - adc - clock - counter + - crypto - dma + - entropy - gpio - hwinfo - i2c + - pico_gpio + - pico_i2c + - pico_serial + - pico_spi - pwm - spi - uart diff --git a/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_mcuboot.yaml b/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_mcuboot.yaml index a6febee0bae9..52bfb56a28af 100644 --- a/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_mcuboot.yaml +++ b/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_mcuboot.yaml @@ -15,6 +15,10 @@ supported: - gpio - hwinfo - i2c + - pico_gpio + - pico_i2c + - pico_serial + - pico_spi - pwm - spi - uart diff --git a/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_w.yaml b/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_w.yaml index afed35e60ed9..098419786163 100644 --- a/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_w.yaml +++ b/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_w.yaml @@ -15,6 +15,10 @@ supported: - gpio - hwinfo - i2c + - pico_gpio + - pico_i2c + - pico_serial + - pico_spi - pwm - spi - uart diff --git a/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_w_mcuboot.yaml b/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_w_mcuboot.yaml index 6efa0e2922da..e0ec0439984d 100644 --- a/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_w_mcuboot.yaml +++ b/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_w_mcuboot.yaml @@ -15,6 +15,10 @@ supported: - gpio - hwinfo - i2c + - pico_gpio + - pico_i2c + - pico_serial + - pico_spi - pwm - spi - uart diff --git a/boards/raytac/an54lq_db_15/doc/index.rst b/boards/raytac/an54lq_db_15/doc/index.rst index 4ae7cb312933..d59c67f9669c 100644 --- a/boards/raytac/an54lq_db_15/doc/index.rst +++ b/boards/raytac/an54lq_db_15/doc/index.rst @@ -29,7 +29,7 @@ internal or external capacitors. - A recommended 3rd-party module by Nordic Semiconductor. - Intended for Bluetooth specification BT6 - Intended for FCC, IC, CE, Telec (MIC), KC, SRRC, NCC, RCM, WPC -- 128 MHz ARM® Cortex |reg|-M33 processor with TrustZone® technology +- 128 MHz ARM® Cortex®-M33 processor with TrustZone® technology - 128 MHz RISC-V coprocessor with TrustZone® technology - 1.5MB Flash Memory / 256KB RAM - RoHS & Reach Compliant. diff --git a/boards/raytac/an54lq_db_15/raytac_an54lq_db_15_nrf54l15_cpuapp.dts b/boards/raytac/an54lq_db_15/raytac_an54lq_db_15_nrf54l15_cpuapp.dts index 7fa21fafd021..b57c2d3f8b4e 100644 --- a/boards/raytac/an54lq_db_15/raytac_an54lq_db_15_nrf54l15_cpuapp.dts +++ b/boards/raytac/an54lq_db_15/raytac_an54lq_db_15_nrf54l15_cpuapp.dts @@ -21,4 +21,4 @@ }; /* Include default memory partition configuration file */ -#include +#include diff --git a/boards/raytac/an54lq_db_15/raytac_an54lq_db_15_nrf54l15_cpuapp_ns.dts b/boards/raytac/an54lq_db_15/raytac_an54lq_db_15_nrf54l15_cpuapp_ns.dts index 8582e62d2f23..3d0ab9ac71c1 100644 --- a/boards/raytac/an54lq_db_15/raytac_an54lq_db_15_nrf54l15_cpuapp_ns.dts +++ b/boards/raytac/an54lq_db_15/raytac_an54lq_db_15_nrf54l15_cpuapp_ns.dts @@ -9,7 +9,7 @@ #define USE_NON_SECURE_ADDRESS_MAP 1 -#include +#include #include "raytac_an54lq_db_15_cpuapp_common.dtsi" / { @@ -29,35 +29,6 @@ }; }; -/ { - /* - * Default SRAM planning when building for nRF54L15 with ARM TrustZone-M support - * - Lowest 80 kB SRAM allocated to Secure image (sram0_s). - * - Upper 80 kB SRAM allocated to Non-Secure image (sram0_ns). - * - * nRF54L15 has 256 kB of volatile memory (SRAM) but the last 96kB are reserved for - * the FLPR MCU. - * This static layout needs to be the same with the upstream TF-M layout in the - * header flash_layout.h of the relevant platform. Any updates in the layout - * needs to happen both in the flash_layout.h and in this file at the same time. - */ - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram0_s: image_s@20000000 { - /* Secure image memory */ - reg = <0x20000000 DT_SIZE_K(80)>; - }; - - sram0_ns: image_ns@20014000 { - /* Non-Secure image memory */ - reg = <0x20014000 DT_SIZE_K(80)>; - }; - }; -}; - &uart30 { /* Disable so that TF-M can use this UART */ status = "disabled"; @@ -69,4 +40,4 @@ }; /* Include default memory partition configuration file */ -#include +#include diff --git a/boards/raytac/an54lq_db_15/raytac_an54lq_db_15_nrf54l15_cpuflpr.dts b/boards/raytac/an54lq_db_15/raytac_an54lq_db_15_nrf54l15_cpuflpr.dts index 582bbf6d7c3a..76a52b128622 100644 --- a/boards/raytac/an54lq_db_15/raytac_an54lq_db_15_nrf54l15_cpuflpr.dts +++ b/boards/raytac/an54lq_db_15/raytac_an54lq_db_15_nrf54l15_cpuflpr.dts @@ -34,6 +34,7 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + ranges; cpuflpr_code_partition: partition@0 { label = "image-0"; diff --git a/boards/raytac/an7002q_db/doc/index.rst b/boards/raytac/an7002q_db/doc/index.rst index 518f20bb8844..244c7df7743e 100644 --- a/boards/raytac/an7002q_db/doc/index.rst +++ b/boards/raytac/an7002q_db/doc/index.rst @@ -101,8 +101,8 @@ The nRF5340 network core does not support the Armv8-M Security Extension. nRF5340 IDAU can configure bus accesses by the nRF5340 network core to have the secure attribute set. This allows to build and run secure-only applications on the nRF5340 SoC. -Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg| -============================================================================= +Building Secure/Non-Secure Zephyr applications with Arm® TrustZone® +=================================================================== Applications on the nRF5340 may contain a Secure and a Non-Secure firmware image for the application core. The Secure image can be built using either diff --git a/boards/raytac/an7002q_db/raytac_an7002q_db_nrf5340_cpunet.dts b/boards/raytac/an7002q_db/raytac_an7002q_db_nrf5340_cpunet.dts index 8a4a4f65ab62..cd362309e198 100644 --- a/boards/raytac/an7002q_db/raytac_an7002q_db_nrf5340_cpunet.dts +++ b/boards/raytac/an7002q_db/raytac_an7002q_db_nrf5340_cpunet.dts @@ -125,6 +125,7 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + ranges; boot_partition: partition@0 { label = "mcuboot"; @@ -133,7 +134,7 @@ slot0_partition: partition@c000 { label = "image-0"; - reg = <0x0000C000 0x17000>; + reg = <0x0000c000 0x17000>; }; slot1_partition: partition@23000 { diff --git a/boards/raytac/mdbt50q_cx_40_dongle/doc/index.rst b/boards/raytac/mdbt50q_cx_40_dongle/doc/index.rst index 44879de194d0..b1fb298d76e3 100644 --- a/boards/raytac/mdbt50q_cx_40_dongle/doc/index.rst +++ b/boards/raytac/mdbt50q_cx_40_dongle/doc/index.rst @@ -14,7 +14,7 @@ Semiconductor nRF52840 ARM Cortex-M4F CPU and the following devices: - Supports BT5 Long Range Feature - Deployed Raytac MDBT50Q-P1M Module - Certifications: FCC, IC, CE, UKCA, Telec (MIC), KC, SRRC, NCC, RCM, WPC -- 32-bit ARM® Cortex |reg| M4F CPU +- 32-bit ARM® Cortex® M4F CPU - 1MB Flash Memory / 256kB RAM - RoHS & Reach Compliant. - Dimension：26.2 x 15.1 x 6.8 mm (excluding Type C USB Connector) diff --git a/boards/raytac/mdbt50q_db_33/doc/index.rst b/boards/raytac/mdbt50q_db_33/doc/index.rst index 087971f5bb15..5d6e0a3dd063 100644 --- a/boards/raytac/mdbt50q_db_33/doc/index.rst +++ b/boards/raytac/mdbt50q_db_33/doc/index.rst @@ -34,7 +34,7 @@ Hardware - BT5.2&BT5.1&BT5 Bluetooth Specification Certified - Supports BT5 Long Range Features - Certifications: FCC, IC, CE, Telec(MIC), KC, SRRC, NCC, RCM, WPC -- 32-bit ARM® Cortex |reg| M4F CPU +- 32-bit ARM® Cortex® M4F CPU - 512kB Flash Memory/128kB RAM - RoHs & Reach Compliant. - 42 GPIO diff --git a/boards/raytac/mdbt50q_db_40/doc/index.rst b/boards/raytac/mdbt50q_db_40/doc/index.rst index 99b370b8a067..2d409d0cf438 100644 --- a/boards/raytac/mdbt50q_db_40/doc/index.rst +++ b/boards/raytac/mdbt50q_db_40/doc/index.rst @@ -34,7 +34,7 @@ Hardware - BT5.2&BT5.1&BT5 Bluetooth Specification Certified - Supports BT5 Long Range Features - Certifications: FCC, IC, CE, Telec(MIC), KC, SRRC, NCC, RCM, WPC -- 32-bit ARM® Cortex |reg| M4F CPU +- 32-bit ARM® Cortex® M4F CPU - 1MB Flash Memory/256kB RAM - RoHs & Reach Compliant. - 48 GPIO diff --git a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp.dts b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp.dts index 20808f45c83a..57a13a05c530 100644 --- a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp.dts +++ b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp.dts @@ -6,7 +6,7 @@ /dts-v1/; #include -#include "raytac_mdbt53_db_40_nrf5340_cpuapp_common.dts" +#include "raytac_mdbt53_db_40_nrf5340_cpuapp_common.dtsi" / { model = "Raytac MDBT53-DB-40 NRF5340 Application"; diff --git a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_common.dts b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_common.dtsi similarity index 100% rename from boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_common.dts rename to boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_common.dtsi diff --git a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_ns.dts b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_ns.dts index 332a163d07a7..135ba2108481 100644 --- a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_ns.dts +++ b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_ns.dts @@ -5,8 +5,8 @@ */ /dts-v1/; -#include -#include "raytac_mdbt53_db_40_nrf5340_cpuapp_common.dts" +#include +#include "raytac_mdbt53_db_40_nrf5340_cpuapp_common.dtsi" / { model = "Raytac MDBT53-DB-40 NRF5340 Application"; diff --git a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet_common.dts b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet_common.dts index 6e8e5183d8aa..85802f9c8766 100644 --- a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet_common.dts +++ b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet_common.dts @@ -35,6 +35,7 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + ranges; boot_partition: partition@0 { label = "mcuboot"; @@ -43,7 +44,7 @@ slot0_partition: partition@c000 { label = "image-0"; - reg = <0x0000C000 0x17000>; + reg = <0x0000c000 0x17000>; }; slot1_partition: partition@23000 { diff --git a/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp.dts b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp.dts index a1ebf2d3b105..5484db516019 100644 --- a/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp.dts +++ b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp.dts @@ -6,7 +6,7 @@ /dts-v1/; #include -#include "raytac_mdbt53v_db_40_nrf5340_cpuapp_common.dts" +#include "raytac_mdbt53v_db_40_nrf5340_cpuapp_common.dtsi" / { model = "Raytac MDBT53V-DB-40 NRF5340 Application"; diff --git a/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_common.dts b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_common.dtsi similarity index 100% rename from boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_common.dts rename to boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_common.dtsi diff --git a/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns.dts b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns.dts index e196d21e1580..8ff76906d414 100644 --- a/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns.dts +++ b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns.dts @@ -5,8 +5,8 @@ */ /dts-v1/; -#include -#include "raytac_mdbt53v_db_40_nrf5340_cpuapp_common.dts" +#include +#include "raytac_mdbt53v_db_40_nrf5340_cpuapp_common.dtsi" / { model = "Raytac MDBT53V-DB-40 NRF5340 Application"; diff --git a/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet_common.dts b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet_common.dts index 6e8e5183d8aa..85802f9c8766 100644 --- a/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet_common.dts +++ b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet_common.dts @@ -35,6 +35,7 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + ranges; boot_partition: partition@0 { label = "mcuboot"; @@ -43,7 +44,7 @@ slot0_partition: partition@c000 { label = "image-0"; - reg = <0x0000C000 0x17000>; + reg = <0x0000c000 0x17000>; }; slot1_partition: partition@23000 { diff --git a/boards/realtek/rtl872xd_evb/Kconfig.rtl872xd_evb b/boards/realtek/rtl872xd_evb/Kconfig.rtl872xd_evb new file mode 100644 index 000000000000..2d696fe9ad2f --- /dev/null +++ b/boards/realtek/rtl872xd_evb/Kconfig.rtl872xd_evb @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Realtek Semiconductor Corp. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RTL872XD_EVB + select SOC_RTL872XD diff --git a/boards/realtek/rtl872xd_evb/board.cmake b/boards/realtek/rtl872xd_evb/board.cmake new file mode 100644 index 000000000000..79ab10f7e1d8 --- /dev/null +++ b/boards/realtek/rtl872xd_evb/board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Realtek Semiconductor Corp. +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=Cortex-M33" "--speed=4000") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/realtek/rtl872xd_evb/board.yml b/boards/realtek/rtl872xd_evb/board.yml new file mode 100644 index 000000000000..17eb0cdcfd3d --- /dev/null +++ b/boards/realtek/rtl872xd_evb/board.yml @@ -0,0 +1,6 @@ +board: + name: rtl872xd_evb + full_name: RTL872xD Evaluation Board + vendor: realtek + socs: + - name: rtl872xd diff --git a/boards/realtek/rtl872xd_evb/doc/index.rst b/boards/realtek/rtl872xd_evb/doc/index.rst new file mode 100644 index 000000000000..6f9fcc98f728 --- /dev/null +++ b/boards/realtek/rtl872xd_evb/doc/index.rst @@ -0,0 +1,90 @@ +.. zephyr:board:: rtl872xd_evb + +Overview +******** + +The Realtek RTL872xD Series is a Combo SoC that supports dual-band Wi-Fi 4 (2.4GHz + 5GHz) and +BLE 5.0 specifications. With ultra-low power consumption, complete encryption strategy and abundant +peripheral resources, it is widely in various products such as Home appliance control panel, +Smart door, Smart toy, Smart voice, Smart remote control, Bluetooth gateway, Headset, Wi-Fi gamepad, +Smart POS, etc. For more information, check `RTL872XD-EVB`_. + +The features include the following: + +- Dual cores: Real-M300 and Real-M200 +- 512KB + 64KB on-chip SRAM +- 802.11 a/b/g/n 1 x 1, 2.4GHz + 5GHz +- Supports BLE 5.0 +- Peripheral Interface: + + - Multi-communication interfaces: SPI x 2, UART x 4, I2C x 1 + - Hardware Key-scan interface supports up to 36 keys + - Hardware Quad-decoder supports statistical and comparison functions + - Hardware IR transceiver can easily adapt to various IR protocols + - SDIO/USB high speed interface (both host and slave) + - Supports real-time clock together with 18 channels of PWM output + - Supports 5 channels of touch pad and 6 channels of GDMA + - Supports 7 channels of normal 12-bit ADC and 1 channel of VBAT + - Integrated LCDC supports both RGB and I8080 interfaces + - Integrated hardware crypto engine supports AES256/192/128 and SHA256 + - Integrated audio codec + +For more information, Get application note and datasheet at `RTL872xCS/D Series`_ depending on chip you use. + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Prerequisites +************* + +Realtek HAL requires binary blobs in order work. Run the command below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_realtek + +.. note:: + + It is recommended running the command above after ``west update``. + +Building +******** + +Here is an example for building the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rtl872xd_evb + :goals: build + +Flashing +******** + +When the build finishes, downloading images into flash by `AmebaImageTool`_: + +See the ApplicationNote chapter Image Tool from documentation links for more details. + +#. Environment Requirements: EX. WinXP, Win 7 or later, Microsoft .NET Framework 4.0. +#. Connect chip and PC with USB wire. +#. Choose the Device profiles according to the chip you use. +#. Select the corresponding serial port and transmission baud rate. The default baud rate is 1500000. +#. Select the images to be programmed and set the start address and end address according to the flash layout, refer to [ameba_flashcfg.c/Flash_layout]. +#. Click the Download button and start. The progress bar will show the download progress of each image and the log window will show the operation status. + +.. note:: + + For an empty chip, the bootloader and app image shall be downloaded. + +Debugging +********* + +Using SWD through PB3(SWD_CLK) and PA27(SWD_DAT). + +References +********** + +.. _`RTL872XD-EVB`: https://www.realmcu.com/en/Home/Products/RTL872xCS-RTL872xD-Series# +.. _`RTL872xCS/D Series`: https://www.realmcu.com +.. _`AmebaImageTool`: https://github.com/Ameba-AIoT/ameba-rtos/tree/master/tools/ameba/ImageTool_Legacy/AmebaImageTool.exe diff --git a/boards/realtek/rtl872xd_evb/doc/rtl872xd_evb.webp b/boards/realtek/rtl872xd_evb/doc/rtl872xd_evb.webp new file mode 100644 index 000000000000..15314fd6c2b9 Binary files /dev/null and b/boards/realtek/rtl872xd_evb/doc/rtl872xd_evb.webp differ diff --git a/boards/realtek/rtl872xd_evb/rtl872xd_evb-pinctrl.dtsi b/boards/realtek/rtl872xd_evb/rtl872xd_evb-pinctrl.dtsi new file mode 100644 index 000000000000..2418704899b9 --- /dev/null +++ b/boards/realtek/rtl872xd_evb/rtl872xd_evb-pinctrl.dtsi @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2024 Realtek Semiconductor Corp. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + compatible = "realtek,ameba-pinctrl"; + + /* PA30 is SWD_CLK, PA31 is SWD_DAT(both pull-up internally) */ + loguart_default: loguart_default { + group1 { + pinmux = , /* RXD */ + ; /* TXD */ + bias-pull-up; + }; + }; +}; diff --git a/boards/realtek/rtl872xd_evb/rtl872xd_evb.dts b/boards/realtek/rtl872xd_evb/rtl872xd_evb.dts new file mode 100644 index 000000000000..dbc9c3499b83 --- /dev/null +++ b/boards/realtek/rtl872xd_evb/rtl872xd_evb.dts @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2024 Realtek Semiconductor Corp. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "rtl872xd_evb-pinctrl.dtsi" + +/ { + model = "RealTek AmebaD RTL872XD EVB"; + compatible = "realtek,rtl872xd_evb"; + + chosen { + zephyr,console = &loguart; + zephyr,shell-uart = &loguart; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; +}; + +&flash0 { + reg = <0x0e000020 DT_SIZE_M(4)>; +}; + +&loguart { + status = "okay"; +}; + +&gpioa { + status = "okay"; +}; + +&gpiob { + status = "okay"; +}; diff --git a/boards/realtek/rtl872xd_evb/rtl872xd_evb.yaml b/boards/realtek/rtl872xd_evb/rtl872xd_evb.yaml new file mode 100644 index 000000000000..fa0b4d3cbe1b --- /dev/null +++ b/boards/realtek/rtl872xd_evb/rtl872xd_evb.yaml @@ -0,0 +1,16 @@ +# Copyright (c) 2024 Realtek Semiconductor Corp. +# SPDX-License-Identifier: Apache-2.0 + +identifier: rtl872xd_evb +name: Realtek rtl872xd evaluation board +vendor: realtek +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +ram: 512 +flash: 4096 +supported: + - pinctrl + - serial diff --git a/boards/realtek/rtl872xd_evb/rtl872xd_evb_defconfig b/boards/realtek/rtl872xd_evb/rtl872xd_evb_defconfig new file mode 100644 index 000000000000..79f80e3ba4de --- /dev/null +++ b/boards/realtek/rtl872xd_evb/rtl872xd_evb_defconfig @@ -0,0 +1,15 @@ +# Copyright (c) 2024 Realtek Semiconductor Corp. +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_HW_STACK_PROTECTION=y + +# This board implies building Non-Secure firmware +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable LogUart +CONFIG_SERIAL=y + +CONFIG_GPIO=y diff --git a/boards/realtek/rtl872xda_evb/Kconfig.rtl872xda_evb b/boards/realtek/rtl872xda_evb/Kconfig.rtl872xda_evb new file mode 100644 index 000000000000..f9f0c70e7162 --- /dev/null +++ b/boards/realtek/rtl872xda_evb/Kconfig.rtl872xda_evb @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Realtek Semiconductor Corp. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RTL872XDA_EVB + select SOC_RTL8721DX diff --git a/boards/realtek/rtl872xda_evb/board.cmake b/boards/realtek/rtl872xda_evb/board.cmake new file mode 100644 index 000000000000..e63da5e6ab42 --- /dev/null +++ b/boards/realtek/rtl872xda_evb/board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Realtek Semiconductor Corp. +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=Cortex-M55" "--speed=4000") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/realtek/rtl872xda_evb/board.yml b/boards/realtek/rtl872xda_evb/board.yml new file mode 100644 index 000000000000..fecae3eac711 --- /dev/null +++ b/boards/realtek/rtl872xda_evb/board.yml @@ -0,0 +1,6 @@ +board: + name: rtl872xda_evb + full_name: RTL8721Dx Evaluation Board + vendor: realtek + socs: + - name: rtl8721dx diff --git a/boards/realtek/rtl872xda_evb/doc/index.rst b/boards/realtek/rtl872xda_evb/doc/index.rst new file mode 100644 index 000000000000..92e7f5f4b241 --- /dev/null +++ b/boards/realtek/rtl872xda_evb/doc/index.rst @@ -0,0 +1,96 @@ +.. zephyr:board:: rtl872xda_evb + +Overview +******** + +The Realtek RTL8721Dx Series is a Combo SoC that supports dual-band Wi-Fi 4 (2.4GHz + 5GHz) and +BLE 5.0 specifications. With excellent ultra-low power consumption, enhanced encryption strategy +(PSA Level 2), and abundant peripheral resources, it is widely used in smart home appliance, +line controller, smart door lock, battery camera, smart remote controller, Wi-Fi Speaker, Wi-Fi +Full MAC NIC, BLE gateway, and smart POS, etc. For more information, check `RTL872XDA-EVB`_. + +The features include the following: + +- Dual cores: Real-M300 and Real-M200 +- 512KB on-chip SRAM +- 802.11 a/b/g/n 1 x 1, 2.4GHz + 5GHz +- Supports BLE 5.0 +- Peripheral Interface: + + - Multi-communication interfaces: SPI x 2, UART x 4, I2C x 2 + - Hardware Key-Scan interface supports up to 8*8 (64) keys + - Hardware IR transceiver can easily adapt to various IR protocols + - Supports Real-Time Clock timer together with 10 basic timers + - Supports 8 channels of PWM timer and 1 capture timer + - Supports 7 channels of general 12-bit ADC and 1 channel of VBAT + - Supports 4 channels of touch pad + - Supports 8 independent channels of GDMA + - Supports USB 2.0 full-speed device mode + - Supports SDIO device with 1-bit and 4-bit mode + - Embeds a serial LEDC to control the external LED lamps + - Integrated Pixel Processing Engine (PPE) to process pixel data faster + - Integrated OSPI display interface supports screens with OSPI/QSPI/SPI interfaces + - Integrated audio codec supports 2 channels DMIC interface + - I2S x 2: up to 384kHz sampling rate + +- Cryptographic hardware acceleration (TRNG, ECC, SHA-2, AES) + +For more information, Get application note and datasheet at `RTL8721Dx Series`_ depending on chip you use. + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Prerequisites +************* + +Realtek HAL requires binary blobs in order work. Run the command below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_realtek + +.. note:: + + It is recommended running the command above after ``west update``. + +Building +******** + +Here is an example for building the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rtl872xda_evb + :goals: buil + +Flashing +******** + +When the build finishes, downloading images into flash by `AmebaImageTool`_: + +See the ApplicationNote chapter Image Tool from documentation links for more details. + +#. Environment Requirements: EX. WinXP, Win 7 or later, Microsoft .NET Framework 4.0. +#. Connect chip and PC with USB wire. +#. Choose the Device profiles according to the chip you use. +#. Select the corresponding serial port and transmission baud rate. The default baud rate is 1500000. +#. Select the images to be programmed and set the start address and end address according to the flash layout, refer to [ameba_flashcfg.c/Flash_layout]. +#. Click the Download button and start. The progress bar will show the download progress of each image and the log window will show the operation status. + +.. note:: + + For an empty chip, the bootloader and app image shall be downloaded. + +Debugging +********* + +Using SWD through PA30(SWD_CLK) and PA31(SWD_DAT). + +References +********** + +.. _`RTL872XDA-EVB`: https://www.realmcu.com/en/Home/Product/add965ea-d661-4a63-9514-d18b6912f8ab# +.. _`RTL8721Dx Series`: https://www.realmcu.com +.. _`AmebaImageTool`: https://github.com/Ameba-AIoT/ameba-rtos/blob/master/tools/ameba/ImageTool/AmebaImageTool.exe diff --git a/boards/realtek/rtl872xda_evb/doc/rtl872xda_evb.webp b/boards/realtek/rtl872xda_evb/doc/rtl872xda_evb.webp new file mode 100644 index 000000000000..dff4bf60705b Binary files /dev/null and b/boards/realtek/rtl872xda_evb/doc/rtl872xda_evb.webp differ diff --git a/boards/realtek/rtl872xda_evb/rtl872xda_evb-pinctrl.dtsi b/boards/realtek/rtl872xda_evb/rtl872xda_evb-pinctrl.dtsi new file mode 100644 index 000000000000..b91aa74f31ad --- /dev/null +++ b/boards/realtek/rtl872xda_evb/rtl872xda_evb-pinctrl.dtsi @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2024 Realtek Semiconductor Corp. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + compatible = "realtek,ameba-pinctrl"; + + /* PA30 is SWD_CLK, PA31 is SWD_DAT(both pull-up internally) */ + loguart_default: loguart_default { + group1 { + pinmux = , /* RXD */ + ; /* TXD */ + bias-pull-up; + }; + }; +}; diff --git a/boards/realtek/rtl872xda_evb/rtl872xda_evb.dts b/boards/realtek/rtl872xda_evb/rtl872xda_evb.dts new file mode 100644 index 000000000000..c45b01368d0b --- /dev/null +++ b/boards/realtek/rtl872xda_evb/rtl872xda_evb.dts @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2024 Realtek Semiconductor Corp. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "rtl872xda_evb-pinctrl.dtsi" + +/ { + model = "RealTek AmebaDplus RTL872XDA EVB"; + compatible = "realtek,rtl872xda_evb"; + + chosen { + zephyr,console = &loguart; + zephyr,shell-uart = &loguart; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; +}; + +&flash0 { + reg = <0x0e000020 DT_SIZE_M(4)>; +}; + +&loguart { + status = "okay"; +}; diff --git a/boards/realtek/rtl872xda_evb/rtl872xda_evb.yaml b/boards/realtek/rtl872xda_evb/rtl872xda_evb.yaml new file mode 100644 index 000000000000..64e415c56c30 --- /dev/null +++ b/boards/realtek/rtl872xda_evb/rtl872xda_evb.yaml @@ -0,0 +1,16 @@ +# Copyright (c) 2024 Realtek Semiconductor Corp. +# SPDX-License-Identifier: Apache-2.0 + +identifier: rtl872xda_evb +name: Realtek rtl872xda evaluation board +vendor: realtek +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +ram: 512 +flash: 4096 +supported: + - pinctrl + - serial diff --git a/boards/realtek/rtl872xda_evb/rtl872xda_evb_defconfig b/boards/realtek/rtl872xda_evb/rtl872xda_evb_defconfig new file mode 100644 index 000000000000..3e16c302accf --- /dev/null +++ b/boards/realtek/rtl872xda_evb/rtl872xda_evb_defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Realtek Semiconductor Corp. +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable LogUart +CONFIG_SERIAL=y diff --git a/boards/realtek/rts5817_maa_evb/Kconfig.rts5817_maa_evb b/boards/realtek/rts5817_maa_evb/Kconfig.rts5817_maa_evb new file mode 100644 index 000000000000..f755c8794f14 --- /dev/null +++ b/boards/realtek/rts5817_maa_evb/Kconfig.rts5817_maa_evb @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Realtek Semiconductor, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RTS5817_MAA_EVB + select SOC_RTS5817 diff --git a/boards/realtek/rts5817_maa_evb/board.cmake b/boards/realtek/rts5817_maa_evb/board.cmake new file mode 100644 index 000000000000..b9ad78c8d159 --- /dev/null +++ b/boards/realtek/rts5817_maa_evb/board.cmake @@ -0,0 +1,7 @@ +# Copyright (c) 2025 Realtek Semiconductor, Inc. +# SPDX-License-Identifier: Apache-2.0 +set_property(TARGET runners_yaml_props_target PROPERTY bin_file zephyr.rts5817.bin) + +board_set_flasher_ifnset(rtsflash) +board_runner_args(rtsflash "--pid=0bda:5817" "--alt=0") +board_finalize_runner_args(rtsflash) diff --git a/boards/realtek/rts5817_maa_evb/board.yml b/boards/realtek/rts5817_maa_evb/board.yml new file mode 100644 index 000000000000..e37a713e41bb --- /dev/null +++ b/boards/realtek/rts5817_maa_evb/board.yml @@ -0,0 +1,9 @@ +# Copyright (c) 2025 Realtek Semiconductor, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board: + name: rts5817_maa_evb + full_name: RTS5817 MAA Evaluation Board + vendor: realtek + socs: + - name: rts5817 diff --git a/boards/realtek/rts5817_maa_evb/doc/img/rts5817_maa_evb.webp b/boards/realtek/rts5817_maa_evb/doc/img/rts5817_maa_evb.webp new file mode 100644 index 000000000000..9b34a5aeb17b Binary files /dev/null and b/boards/realtek/rts5817_maa_evb/doc/img/rts5817_maa_evb.webp differ diff --git a/boards/realtek/rts5817_maa_evb/doc/index.rst b/boards/realtek/rts5817_maa_evb/doc/index.rst new file mode 100644 index 000000000000..009b6b12306b --- /dev/null +++ b/boards/realtek/rts5817_maa_evb/doc/index.rst @@ -0,0 +1,71 @@ +.. zephyr:board:: rts5817_maa_evb + +Overview +******** + +The RTS5817 MAA EVB is a development platform to evaluate the Realtek RTS5817 MAA fingerprint chip. +The RTS5817 MAA chip contains a high-performance MCU and a fingerprint sensor. + +.. figure:: img/rts5817_maa_evb.webp + :width: 400px + :align: center + :alt: rts5817_maa_evb + +Hardware +******** + +- 240MHz single-core 32-bit CPU with I-cache 32KB, D-cache 16KB +- 48KB boot ROM +- 256KB on-chip SRAM +- 1KB PUFrt OTP +- 2MB Flash +- USB2.0 full speed/high speed device +- Up to 11 GPIO +- 2 x UART +- 2 x Timer +- 2 x SPI, one can support slave mode +- Watchdog +- DMA +- Temperature sensor +- Cryptographic hardware acceleration (RNG, SHA, AES) +- Fingerprint matching hardware acceleration (MAC, popcount, convolution, etc.) +- SWD for debug + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Building +======== + +#. Build :zephyr:code-sample:`hello_world` application as you would normally do. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rts5817_maa_evb + :goals: build + +#. The file ``zephyr.rts5817.bin`` will be created if the build system can build successfully. + This binary image can be found under file "build/zephyr/". + +Flashing +======== + +#. Short the two pins of ``J6`` to enter force rom mode (see `RTS5817MAA_EVB_User_Guide`_). +#. Connect the board to your host computer using USB. +#. Use ``west flash`` command to flash the image. +#. Disconnect the two pins of ``J6`` and reboot, The :zephyr:code-sample:`hello_world` application is running. + +References +********** + +.. target-notes:: + +.. _RTS5817MAA_EVB_User_Guide: + https://github.com/RtkFP/Doc/blob/main/RTS5817MAA_EVB%20User%20Guide_V1.0.pdf diff --git a/boards/realtek/rts5817_maa_evb/rts5817_maa_evb-pinctrl.dtsi b/boards/realtek/rts5817_maa_evb/rts5817_maa_evb-pinctrl.dtsi new file mode 100644 index 000000000000..5c787ca27609 --- /dev/null +++ b/boards/realtek/rts5817_maa_evb/rts5817_maa_evb-pinctrl.dtsi @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2025 Realtek Semiconductor, Inc. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + uart0_default: uart0_default { + group0 { + pinmux = , ; + }; + }; + + /omit-if-no-ref/ sensor_spi_default: sensor_spi_default { + group0 { + pinmux = , , + ; + power-source = ; + bias-pull-down; + }; + + group1 { + pinmux = , ; + power-source = ; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ ssi_master_default: ssi_master_default { + group0 { + pinmux = , , + , ; + bias-pull-down; + }; + }; +}; diff --git a/boards/realtek/rts5817_maa_evb/rts5817_maa_evb.dts b/boards/realtek/rts5817_maa_evb/rts5817_maa_evb.dts new file mode 100644 index 000000000000..f4da721a7ebf --- /dev/null +++ b/boards/realtek/rts5817_maa_evb/rts5817_maa_evb.dts @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2025 Realtek Semiconductor, Inc. + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "rts5817_maa_evb-pinctrl.dtsi" + +/ { + model = "Realtek rts5817_maa_evb"; + compatible = "realtek,rts5817_maa_evb"; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; +}; + +&clks { + status = "okay"; +}; + +&reset { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_default>; + current-speed = <115200>; + status = "okay"; +}; + +&uart1 { + status = "disabled"; +}; diff --git a/boards/realtek/rts5817_maa_evb/rts5817_maa_evb.yaml b/boards/realtek/rts5817_maa_evb/rts5817_maa_evb.yaml new file mode 100644 index 000000000000..f03a3cb39143 --- /dev/null +++ b/boards/realtek/rts5817_maa_evb/rts5817_maa_evb.yaml @@ -0,0 +1,15 @@ +# Copyright (c) 2025 Realtek Semiconductor, Inc. +# SPDX-License-Identifier: Apache-2.0 + +identifier: rts5817_maa_evb +name: RTS5817 Platform for fingerprint +type: mcu +arch: arm +ram: 256 +flash: 2048 +toolchain: + - zephyr + - gnuarmemb +testing: + default: true +vendor: realtek diff --git a/boards/realtek/rts5817_maa_evb/rts5817_maa_evb_defconfig b/boards/realtek/rts5817_maa_evb/rts5817_maa_evb_defconfig new file mode 100644 index 000000000000..2aedae85b96e --- /dev/null +++ b/boards/realtek/rts5817_maa_evb/rts5817_maa_evb_defconfig @@ -0,0 +1,17 @@ +# Copyright (c) 2025 Realtek Semiconductor, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# Enable clocks +CONFIG_CLOCK_CONTROL=y + +# Enable reset +CONFIG_RESET=y + +# Enable serial console +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable watchdog +CONFIG_WATCHDOG=y +CONFIG_WDT_DISABLE_AT_BOOT=y diff --git a/boards/renesas/cpkcor_ra8d1b/CMakeLists.txt b/boards/renesas/cpkcor_ra8d1b/CMakeLists.txt new file mode 100644 index 000000000000..0a8bbb60fffe --- /dev/null +++ b/boards/renesas/cpkcor_ra8d1b/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) diff --git a/boards/renesas/cpkcor_ra8d1b/Kconfig.cpkcor_ra8d1b b/boards/renesas/cpkcor_ra8d1b/Kconfig.cpkcor_ra8d1b new file mode 100644 index 000000000000..beb8a0b0c1cf --- /dev/null +++ b/boards/renesas/cpkcor_ra8d1b/Kconfig.cpkcor_ra8d1b @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Jisheng Zhang +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_CPKCOR_RA8D1B + select SOC_R7FA8D1BHECBD diff --git a/boards/renesas/cpkcor_ra8d1b/board.cmake b/boards/renesas/cpkcor_ra8d1b/board.cmake new file mode 100644 index 000000000000..06ba0e171694 --- /dev/null +++ b/boards/renesas/cpkcor_ra8d1b/board.cmake @@ -0,0 +1,8 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=R7FA8D1BH") +board_runner_args(pyocd "--target=R7FA8D1BH") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/renesas/cpkcor_ra8d1b/board.yml b/boards/renesas/cpkcor_ra8d1b/board.yml new file mode 100644 index 000000000000..ac660c9a7803 --- /dev/null +++ b/boards/renesas/cpkcor_ra8d1b/board.yml @@ -0,0 +1,6 @@ +board: + name: cpkcor_ra8d1b + full_name: CPKCOR RA8D1B board + vendor: renesas + socs: + - name: r7fa8d1bhecbd diff --git a/boards/renesas/cpkcor_ra8d1b/cpkcor_ra8d1b-pinctrl.dtsi b/boards/renesas/cpkcor_ra8d1b/cpkcor_ra8d1b-pinctrl.dtsi new file mode 100644 index 000000000000..343e04b15695 --- /dev/null +++ b/boards/renesas/cpkcor_ra8d1b/cpkcor_ra8d1b-pinctrl.dtsi @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * Copyright (c) 2025 Jisheng Zhang + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci3_default: sci3_default { + group1 { + /* tx */ + psels = ; + drive-strength = "medium"; + }; + + group2 { + /* rx */ + psels = ; + }; + }; + + usbhs_default: usbhs_default { + group1 { + psels = ; /* USBHS-VBUS */ + drive-strength = "high"; + }; + }; + + adc0_default: adc0_default { + group1 { + /* input */ + psels = ; + renesas,analog-enable; + }; + }; + + dac0_default: dac0_default { + group1 { + /* output */ + psels = ; + renesas,analog-enable; + }; + }; + + sdram_default: sdram_default { + group1 { + psels = , /* SDRAM_A1 */ + , /* SDRAM_A2 */ + , /* SDRAM_A3 */ + , /* SDRAM_A4 */ + , /* SDRAM_A5 */ + , /* SDRAM_A6 */ + , /* SDRAM_A7 */ + , /* SDRAM_A8 */ + , /* SDRAM_A9 */ + , /* SDRAM_A10 */ + , /* SDRAM_A11 */ + , /* SDRAM_A12 */ + , /* SDRAM_A13 */ + , /* SDRAM_A14 */ + , /* SDRAM_A15 */ + , /* SDRAM_CAS */ + , /* SDRAM_CKE */ + , /* SDRAM_DQ0 */ + , /* SDRAM_DQ1 */ + , /* SDRAM_DQ2 */ + , /* SDRAM_DQ3 */ + , /* SDRAM_DQ4 */ + , /* SDRAM_DQ5 */ + , /* SDRAM_DQ6 */ + , /* SDRAM_DQ7 */ + , /* SDRAM_DQ8 */ + , /* SDRAM_DQ9 */ + , /* SDRAM_DQ10 */ + , /* SDRAM_DQ11 */ + , /* SDRAM_DQ12 */ + , /* SDRAM_DQ13 */ + , /* SDRAM_DQ14 */ + , /* SDRAM_DQ15 */ + , /* SDRAM_DQM0 */ + , /* SDRAM_DQM1 */ + , /* SDRAM_RAS */ + , /* SDRAM_SDCS */ + ; /* SDRAM_WE */ + drive-strength = "high"; + }; + + group2 { + psels = ; /* SDRAM_SDCLK */ + drive-strength = "highspeed-high"; + }; + }; + + sdhc1_default: sdhc1_default { + group1 { + psels = , /* SDCD */ + , /* SDCMD */ + , /* SDDATA0 */ + , /* SDDATA1 */ + , /* SDDATA2 */ + ; /* SDDATA3 */ + drive-strength = "high"; + }; + + group2 { + psels = ; /* SDCLK */ + drive-strength = "highspeed-high"; + }; + }; +}; diff --git a/boards/renesas/cpkcor_ra8d1b/cpkcor_ra8d1b.dts b/boards/renesas/cpkcor_ra8d1b/cpkcor_ra8d1b.dts new file mode 100644 index 000000000000..1ddc19d6b15d --- /dev/null +++ b/boards/renesas/cpkcor_ra8d1b/cpkcor_ra8d1b.dts @@ -0,0 +1,251 @@ +/* + * Copyright (c) 2025 Jisheng Zhang + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include "cpkcor_ra8d1b-pinctrl.dtsi" + +/ { + model = "Renesas CPKCOR-RA8D1B"; + compatible = "renesas,ra8d1", "renesas,ra8"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,itcm = &itcm; + zephyr,dtcm = &dtcm; + zephyr,console = &uart3; + zephyr,shell-uart = &uart3; + zephyr,entropy = &trng; + zephyr,flash-controller = &flash; + zephyr,crc = &crc; + }; + + leds { + compatible = "gpio-leds"; + + led0: led0 { + gpios = <&ioporta 1 GPIO_ACTIVE_HIGH>; + label = "LED1"; + }; + }; + + buttons { + compatible = "gpio-keys"; + + button0: s1 { + gpios = <&ioport0 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "User Button"; + zephyr,code = ; + }; + }; + + sdram1: sdram@68000000 { + compatible = "zephyr,memory-region", "mmio-sram"; + device_type = "memory"; + reg = <0x68000000 DT_SIZE_M(32)>; /* 256 Mbits */ + zephyr,memory-region = "SDRAM"; + status = "okay"; + }; + + aliases { + led0 = &led0; + sw0 = &button0; + watchdog0 = &wdt; + sdhc0 = &sdhc1; + }; +}; + +&xtal { + clock-frequency = ; + mosel = <0>; + #clock-cells = <0>; + status = "okay"; +}; + +&subclk { + status = "okay"; +}; + +&pll { + status = "okay"; + div = <4>; + mul = <160 0>; + + pllp { + status = "okay"; + }; + + pllq { + div = <4>; + freq = ; + status = "okay"; + }; + + pllr { + status = "okay"; + }; +}; + +&pll2 { + status = "okay"; + clocks = <&xtal>; + div = <3>; + mul = <100 0>; + + pll2p { + status = "okay"; + freq = ; + div = <4>; + }; +}; + +&sciclk { + clocks = <&pllp>; + div = <4>; + status = "okay"; +}; + +&uclk { + clocks = <&pllq>; + div = <5>; + status = "okay"; +}; + +&ioport0 { + status = "okay"; +}; + +&ioporta { + status = "okay"; +}; + +&sci3 { + pinctrl-0 = <&sci3_default>; + pinctrl-names = "default"; + status = "okay"; + + uart3: uart { + current-speed = <115200>; + status = "okay"; + }; +}; + +&trng { + status = "okay"; +}; + +&flash1 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + storage_partition: partition@0 { + label = "storage"; + reg = <0x0 DT_SIZE_K(12)>; + }; + }; +}; + +&usbhs { + pinctrl-0 = <&usbhs_default>; + pinctrl-names = "default"; + maximum-speed = "high-speed"; + status = "okay"; + + zephyr_udc0: udc { + status = "okay"; + }; +}; + +&usbhs_phy { + phys-clock-src = "xtal"; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_default>; + pinctrl-names = "default"; +}; + +&dac0 { + pinctrl-0 = <&dac0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&port_irq12 { + interrupts = <88 12>; + status = "okay"; +}; + +&sdram { + pinctrl-0 = <&sdram_default>; + pinctrl-names = "default"; + status = "okay"; + auto-refresh-interval = ; + auto-refresh-count = ; + precharge-cycle-count = ; + multiplex-addr-shift = "8-bit"; + endian-mode = "little-endian"; + continuous-access; + bus-width = "16-bit"; + + bank@0 { + reg = <0>; + renesas,ra-sdram-timing = ; + }; +}; + +&wdt { + status = "okay"; +}; + +&ulpt0 { + status = "okay"; + + timer { + status = "okay"; + }; +}; + +&ulpt1 { + status = "okay"; + + timer { + status = "okay"; + }; +}; + +&crc { + status = "okay"; +}; + +&sdhc1 { + pinctrl-names = "default"; + interrupt-names = "accs", "card", "dma-req"; + interrupts = <60 12>, <61 12>, <62 12>; + pinctrl-0 = <&sdhc1_default>; + status = "okay"; + + sdmmc { + compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; + status = "okay"; + }; +}; diff --git a/boards/renesas/cpkcor_ra8d1b/cpkcor_ra8d1b.yaml b/boards/renesas/cpkcor_ra8d1b/cpkcor_ra8d1b.yaml new file mode 100644 index 000000000000..4315fcda698b --- /dev/null +++ b/boards/renesas/cpkcor_ra8d1b/cpkcor_ra8d1b.yaml @@ -0,0 +1,16 @@ +identifier: cpkcor_ra8d1b +name: Renesas CPKCOR-RA8D1B +type: mcu +arch: arm +ram: 1024 +flash: 2016 +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio + - uart + - watchdog + - usbd + - memc +vendor: renesas diff --git a/boards/renesas/cpkcor_ra8d1b/cpkcor_ra8d1b_defconfig b/boards/renesas/cpkcor_ra8d1b/cpkcor_ra8d1b_defconfig new file mode 100644 index 000000000000..1b679557be4e --- /dev/null +++ b/boards/renesas/cpkcor_ra8d1b/cpkcor_ra8d1b_defconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2025 Jisheng Zhang +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Enable Console +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y diff --git a/boards/renesas/cpkcor_ra8d1b/doc/index.rst b/boards/renesas/cpkcor_ra8d1b/doc/index.rst new file mode 100644 index 000000000000..3c15ca8076ea --- /dev/null +++ b/boards/renesas/cpkcor_ra8d1b/doc/index.rst @@ -0,0 +1,76 @@ +.. zephyr:board:: cpkcor_ra8d1b + +Overview +******** + +The CPKCOR-RA8D1B, based on the Renesas Cortex-M85 architecture RA8D1 chip, offers engineers a convenient evelopment platform for study, evaluation and development. + +Key Features + +- Arm Cortex-M85 +- 480MHz frequency, on-chip 2MB Flash, 1MB SRAM +- 32MB-SDRAM +- 16MB-QSPI Flash +- TF card slot +- USB2.0 high speed host/device controller via. Type-C interface + +More information about the board can be found at the `CPKCOR-RA8D1B website`_. + +Hardware +******** +Detailed Hardware features for the RA8D1 MCU group can be found at `RA8D1 Group User's Manual Hardware`_ + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Applications for the ``cpkcor_ra8d1b`` board can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +**Note:** Only support from SDK v0.16.6 in which GCC for Cortex Arm-M85 was available. +To build for CPKCOR-RA8D1B user need to get and install GNU Arm Embedded toolchain from https://github.com/zephyrproject-rtos/sdk-ng/releases/tag/v0.16.6 + +Flashing +======== + +Program can be flashed to CPKCOR-RA8D1B via the on-board SEGGER J-Link debugger. + +To flash the program to board + +1. Connect to J-LINK OB via USB port to host PC + +2. Execute west command + + .. code-block:: console + + west flash + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: cpkcor_ra8d1b + :maybe-skip-config: + :goals: debug + +References +********** +.. target-notes:: + +.. _CPKCOR-RA8D1B Website: + https://github.com/renesas/cpk_examples/blob/main/cpkcor_ra8d1b + +.. _RA8D1 Group User's Manual Hardware: + https://www.renesas.com/us/en/document/mah/ra8d1-group-users-manual-hardware diff --git a/boards/renesas/da14695_dk_usb/dts/da14695_dk_usb_mipi_dbi.overlay b/boards/renesas/da14695_dk_usb/dts/da14695_dk_usb_mipi_dbi.overlay index acc98c5f2a94..3a7e41c8c96b 100644 --- a/boards/renesas/da14695_dk_usb/dts/da14695_dk_usb_mipi_dbi.overlay +++ b/boards/renesas/da14695_dk_usb/dts/da14695_dk_usb_mipi_dbi.overlay @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include #include / { @@ -52,7 +52,7 @@ reg = <0>; width = <240>; height = <320>; - pixel-format = ; + pixel-format = ; rotation = <0>; }; }; diff --git a/boards/renesas/da14695_dk_usb/dts/da14695_dk_usb_psram.overlay b/boards/renesas/da14695_dk_usb/dts/da14695_dk_usb_psram.overlay index e44f1484bc5c..f1e0f2ed807f 100644 --- a/boards/renesas/da14695_dk_usb/dts/da14695_dk_usb_psram.overlay +++ b/boards/renesas/da14695_dk_usb/dts/da14695_dk_usb_psram.overlay @@ -19,9 +19,9 @@ status = "okay"; is-ram; dev-size = ; - dev-type = <0x5D>; - dev-id = <0x0D>; - dev-density = <0xE040>; + dev-type = <0x5d>; + dev-id = <0x0d>; + dev-density = <0xe040>; reset-delay-us = <50>; read-cs-idle-min-ns = <18>; tcem-max-us = <2>; @@ -30,7 +30,7 @@ extra-byte-enable; extra-byte = <0x0>; dummy-bytes-count = "dummy-bytes-count2"; - read-cmd = <0xEB>; + read-cmd = <0xeb>; write-cmd = <0x38>; rx-inst-mode = "quad-spi"; rx-addr-mode = "quad-spi"; diff --git a/boards/renesas/da1469x_dk_pro/dts/da1469x_dk_pro_mipi_dbi.overlay b/boards/renesas/da1469x_dk_pro/dts/da1469x_dk_pro_mipi_dbi.overlay index acc98c5f2a94..bd8b6cef95f6 100644 --- a/boards/renesas/da1469x_dk_pro/dts/da1469x_dk_pro_mipi_dbi.overlay +++ b/boards/renesas/da1469x_dk_pro/dts/da1469x_dk_pro_mipi_dbi.overlay @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include #include / { @@ -52,7 +52,7 @@ reg = <0>; width = <240>; height = <320>; - pixel-format = ; + pixel-format = ; rotation = <0>; }; }; diff --git a/boards/renesas/da1469x_dk_pro/dts/da1469x_dk_pro_psram.overlay b/boards/renesas/da1469x_dk_pro/dts/da1469x_dk_pro_psram.overlay index e44f1484bc5c..f1e0f2ed807f 100644 --- a/boards/renesas/da1469x_dk_pro/dts/da1469x_dk_pro_psram.overlay +++ b/boards/renesas/da1469x_dk_pro/dts/da1469x_dk_pro_psram.overlay @@ -19,9 +19,9 @@ status = "okay"; is-ram; dev-size = ; - dev-type = <0x5D>; - dev-id = <0x0D>; - dev-density = <0xE040>; + dev-type = <0x5d>; + dev-id = <0x0d>; + dev-density = <0xe040>; reset-delay-us = <50>; read-cs-idle-min-ns = <18>; tcem-max-us = <2>; @@ -30,7 +30,7 @@ extra-byte-enable; extra-byte = <0x0>; dummy-bytes-count = "dummy-bytes-count2"; - read-cmd = <0xEB>; + read-cmd = <0xeb>; write-cmd = <0x38>; rx-inst-mode = "quad-spi"; rx-addr-mode = "quad-spi"; diff --git a/boards/renesas/ek_ra2a1/ek_ra2a1-pinctrl.dtsi b/boards/renesas/ek_ra2a1/ek_ra2a1-pinctrl.dtsi index b18dd709a6e8..5cdbb9f77609 100644 --- a/boards/renesas/ek_ra2a1/ek_ra2a1-pinctrl.dtsi +++ b/boards/renesas/ek_ra2a1/ek_ra2a1-pinctrl.dtsi @@ -45,6 +45,14 @@ }; }; + adc0_default: adc0_default { + group1 { + /* input */ + psels = ; + renesas,analog-enable; + }; + }; + dac0_default: dac0_default { group1 { /* output */ diff --git a/boards/renesas/ek_ra2a1/ek_ra2a1.dts b/boards/renesas/ek_ra2a1/ek_ra2a1.dts index 142c58724bfa..22315fb8e653 100644 --- a/boards/renesas/ek_ra2a1/ek_ra2a1.dts +++ b/boards/renesas/ek_ra2a1/ek_ra2a1.dts @@ -7,6 +7,7 @@ #include #include +#include #include #include "ek_ra2a1-pinctrl.dtsi" @@ -120,6 +121,14 @@ status = "okay"; }; +&adc0 { + pinctrl-0 = <&adc0_default>; + pinctrl-names = "default"; + interrupts = <13 3>; + interrupt-names = "scanend"; + status = "okay"; +}; + &dac0 { pinctrl-0 = <&dac0_default>; pinctrl-names = "default"; @@ -150,7 +159,7 @@ ssdiv = "1.00"; so = <0x108>; snum = <0x01>; - sdpa = <0x0B>; + sdpa = <0x0b>; on-freq = <3>; off-freq = <3>; drift-freq = <255>; diff --git a/boards/renesas/ek_ra2l1/ek_ra2l1-pinctrl.dtsi b/boards/renesas/ek_ra2l1/ek_ra2l1-pinctrl.dtsi index 84b6a4e0411f..6ce573055fe8 100644 --- a/boards/renesas/ek_ra2l1/ek_ra2l1-pinctrl.dtsi +++ b/boards/renesas/ek_ra2l1/ek_ra2l1-pinctrl.dtsi @@ -12,6 +12,33 @@ }; }; + sci9_default: sci9_default { + group1 { + /* tx rx */ + psels = , + ; + }; + }; + + iic0_default: iic0_default { + group1 { + /* SCL0 SDA0 */ + psels = , + ; + drive-strength = "medium"; + }; + }; + + spi0_default: spi0_default { + group1 { + /* MISO MOSI RSPCK SSL */ + psels = , + , + , + ; + }; + }; + adc0_default: adc0_default { group1 { /* input */ diff --git a/boards/renesas/ek_ra2l1/ek_ra2l1.dts b/boards/renesas/ek_ra2l1/ek_ra2l1.dts index acb99dd23778..e9a29b456a83 100644 --- a/boards/renesas/ek_ra2l1/ek_ra2l1.dts +++ b/boards/renesas/ek_ra2l1/ek_ra2l1.dts @@ -39,6 +39,69 @@ gpios = <&ioport5 3 GPIO_ACTIVE_HIGH>; label = "LED1"; }; + + led2: led2 { + gpios = <&ioport5 4 GPIO_ACTIVE_HIGH>; + label = "LED2"; + }; + + led3: led3 { + gpios = <&ioport5 5 GPIO_ACTIVE_HIGH>; + label = "LED3"; + }; + }; + + pmod1_header: pmod-connector-1 { + compatible = "digilent,pmod"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &ioport1 3 0>, /* IO1 */ + <1 0 &ioport1 1 0>, /* IO2 */ + <2 0 &ioport1 0 0>, /* IO3 */ + <3 0 &ioport1 2 0>, /* IO4 */ + <4 0 &ioport4 2 0>, /* IO5 */ + <5 0 &ioport2 8 0>, /* IO6 */ + <6 0 &ioport1 5 0>, /* IO7 */ + <7 0 &ioport1 6 0>; /* IO8 */ + }; + + pmod2_header: pmod-connector-2 { + compatible = "digilent,pmod"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &ioport2 5 0>, /* IO1 */ + <1 0 &ioport2 3 0>, /* IO2 */ + <2 0 &ioport2 2 0>, /* IO3 */ + <3 0 &ioport2 4 0>, /* IO4 */ + <4 0 &ioport4 9 0>, /* IO5 */ + <5 0 &ioport3 3 0>, /* IO6 */ + <6 0 &ioport2 6 0>, /* IO7 */ + <7 0 &ioport3 4 0>; /* IO8 */ + }; + + mikrobus_header: mikrobus-connector { + compatible = "mikro-bus"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &ioport0 0 0>, /* AN */ + <1 0 &ioport2 7 0>, /* RST */ + <2 0 &ioport1 3 0>, /* CS */ + <3 0 &ioport1 2 0>, /* SCK */ + <4 0 &ioport1 0 0>, /* MISO */ + <5 0 &ioport1 1 0>, /* MOSI */ + /* +3.3V */ + /* GND */ + <6 0 &ioport4 0 0>, /* PWM */ + <7 0 &ioport1 10 0>, /* INT */ + <8 0 &ioport4 10 0>, /* RX */ + <9 0 &ioport4 11 0>, /* TX */ + <10 0 &ioport4 8 0>, /* SCL */ + <11 0 &ioport4 7 0>; /* SDA */ + /* +5V */ + /* GND */ }; buttons { @@ -59,6 +122,7 @@ aliases { led0 = &led1; + led1 = &led2; sw0 = &button0; sw1 = &button1; watchdog0 = &wdt; @@ -73,6 +137,22 @@ status = "okay"; }; +&ioport1 { + status = "okay"; +}; + +&ioport2 { + status = "okay"; +}; + +&ioport3 { + status = "okay"; +}; + +&ioport4 { + status = "okay"; +}; + &sci0 { pinctrl-0 = <&sci0_default>; pinctrl-names = "default"; @@ -84,6 +164,36 @@ }; }; +&sci9 { + pinctrl-0 = <&sci9_default>; + pinctrl-names = "default"; + status = "okay"; + + uart9: uart { + current-speed = <115200>; + status = "okay"; + }; +}; + +&iic0 { + pinctrl-0 = <&iic0_default>; + pinctrl-names = "default"; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <28 1>, <29 1>, <30 1>, <31 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + clock-frequency = ; +}; + +&spi0 { + pinctrl-0 = <&spi0_default>; + pinctrl-names = "default"; + interrupts = <16 1>, <17 1>, <18 1>, <19 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + status = "okay"; +}; + &wdt { status = "okay"; }; @@ -132,3 +242,19 @@ }; }; }; + +pmod1_spi: &spi0 {}; + +pmod2_serial: &uart9 {}; + +pmod_spi: &pmod1_spi {}; + +pmod_serial: &pmod2_serial {}; + +pmod_header: &pmod1_header {}; + +mikrobus_serial: &uart0 {}; + +mikrobus_i2c: &iic0 {}; + +mikrobus_spi: &spi0 {}; diff --git a/boards/renesas/ek_ra4e2/ek_ra4e2.dts b/boards/renesas/ek_ra4e2/ek_ra4e2.dts index 75643d16b91c..22d3f66185d8 100644 --- a/boards/renesas/ek_ra4e2/ek_ra4e2.dts +++ b/boards/renesas/ek_ra4e2/ek_ra4e2.dts @@ -213,7 +213,7 @@ storage_partition: partition@0 { label = "storage"; - reg = <0X0 DT_SIZE_K(4)>; + reg = <0x0 DT_SIZE_K(4)>; }; }; }; diff --git a/boards/renesas/ek_ra4l1/ek_ra4l1-pinctrl.dtsi b/boards/renesas/ek_ra4l1/ek_ra4l1-pinctrl.dtsi index 135d40e0976e..d9b7236f953a 100644 --- a/boards/renesas/ek_ra4l1/ek_ra4l1-pinctrl.dtsi +++ b/boards/renesas/ek_ra4l1/ek_ra4l1-pinctrl.dtsi @@ -4,6 +4,14 @@ */ &pinctrl { + sci1_default: sci1_default { + group1 { + /* tx rx */ + psels = , + ; + }; + }; + sci5_default: sci5_default { group1 { /* tx rx */ diff --git a/boards/renesas/ek_ra4l1/ek_ra4l1.dts b/boards/renesas/ek_ra4l1/ek_ra4l1.dts index 2aed4a8db709..19f8bc593c1c 100644 --- a/boards/renesas/ek_ra4l1/ek_ra4l1.dts +++ b/boards/renesas/ek_ra4l1/ek_ra4l1.dts @@ -9,6 +9,8 @@ #include #include #include +#include + #include "ek_ra4l1-pinctrl.dtsi" / { @@ -44,6 +46,58 @@ }; }; + mikrobus_header: mikrobus-connector { + compatible = "mikro-bus"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &ioport5 10 0>, /* AN */ + <1 0 &ioport1 13 0>, /* RST */ + <2 0 &ioport2 4 0>, /* CS */ + <3 0 &ioport2 9 0>, /* SCK */ + <4 0 &ioport2 10 0>, /* MISO */ + <5 0 &ioport2 11 0>, /* MOSI */ + /* +3.3V */ + /* GND */ + <6 0 &ioport4 5 0>, /* PWM */ + <7 0 &ioport4 3 0>, /* INT */ + <8 0 &ioport6 8 0>, /* RX */ + <9 0 &ioport1 15 0>, /* TX */ + <10 0 &ioport4 0 0>, /* SCL */ + <11 0 &ioport4 1 0>; /* SDA */ + /* +5V */ + /* GND */ + }; + + arduino_header: arduino-connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + buttons { compatible = "gpio-keys"; @@ -110,6 +164,19 @@ status = "okay"; }; +&sci1 { + pinctrl-0 = <&sci1_default>; + pinctrl-names = "default"; + interrupts = <32 1>, <33 1>, <34 1>, <35 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + status = "okay"; + + uart1: uart { + current-speed = <115200>; + status = "okay"; + }; +}; + &sci5 { pinctrl-0 = <&sci5_default>; pinctrl-names = "default"; @@ -129,6 +196,10 @@ status = "okay"; }; +&ioport2 { + status = "okay"; +}; + &ioport4 { status = "okay"; }; @@ -230,3 +301,7 @@ &crc { status = "okay"; }; + +mikrobus_serial: &uart1 {}; + +arduino_serial: &uart1 {}; diff --git a/boards/renesas/ek_ra4m2/ek_ra4m2.dts b/boards/renesas/ek_ra4m2/ek_ra4m2.dts index 04bfe461a2fc..486d9411116d 100644 --- a/boards/renesas/ek_ra4m2/ek_ra4m2.dts +++ b/boards/renesas/ek_ra4m2/ek_ra4m2.dts @@ -175,7 +175,7 @@ storage_partition: partition@0 { label = "storage"; - reg = <0X0 DT_SIZE_K(8)>; + reg = <0x0 DT_SIZE_K(8)>; }; }; }; diff --git a/boards/renesas/ek_ra4m3/ek_ra4m3.dts b/boards/renesas/ek_ra4m3/ek_ra4m3.dts index 0d00778baa37..5b7db6c3becc 100644 --- a/boards/renesas/ek_ra4m3/ek_ra4m3.dts +++ b/boards/renesas/ek_ra4m3/ek_ra4m3.dts @@ -173,7 +173,7 @@ storage_partition: partition@0 { label = "storage"; - reg = <0X0 DT_SIZE_K(8)>; + reg = <0x0 DT_SIZE_K(8)>; }; }; }; diff --git a/boards/renesas/ek_ra4w1/ek_ra4w1.dts b/boards/renesas/ek_ra4w1/ek_ra4w1.dts index 856d0e983dfc..9b3d6cff463b 100644 --- a/boards/renesas/ek_ra4w1/ek_ra4w1.dts +++ b/boards/renesas/ek_ra4w1/ek_ra4w1.dts @@ -56,10 +56,6 @@ }; }; -&subclk { - status = "okay"; -}; - &sci0 { pinctrl-0 = <&sci0_default>; pinctrl-names = "default"; diff --git a/boards/renesas/ek_ra6e2/ek_ra6e2.dts b/boards/renesas/ek_ra6e2/ek_ra6e2.dts index 2b806a5dce7f..ac5e1e64e7eb 100644 --- a/boards/renesas/ek_ra6e2/ek_ra6e2.dts +++ b/boards/renesas/ek_ra6e2/ek_ra6e2.dts @@ -189,7 +189,7 @@ storage_partition: partition@0 { label = "storage"; - reg = <0X0 DT_SIZE_K(4)>; + reg = <0x0 DT_SIZE_K(4)>; }; }; }; diff --git a/boards/renesas/ek_ra6m1/ek_ra6m1.dts b/boards/renesas/ek_ra6m1/ek_ra6m1.dts index ce09e71c8afb..9b429c7a5308 100644 --- a/boards/renesas/ek_ra6m1/ek_ra6m1.dts +++ b/boards/renesas/ek_ra6m1/ek_ra6m1.dts @@ -143,7 +143,7 @@ storage_partition: partition@0 { label = "storage"; - reg = <0X0 DT_SIZE_K(8)>; + reg = <0x0 DT_SIZE_K(8)>; }; }; }; diff --git a/boards/renesas/ek_ra6m2/ek_ra6m2.dts b/boards/renesas/ek_ra6m2/ek_ra6m2.dts index 3de37950b8e9..73ea49c3d956 100644 --- a/boards/renesas/ek_ra6m2/ek_ra6m2.dts +++ b/boards/renesas/ek_ra6m2/ek_ra6m2.dts @@ -139,7 +139,7 @@ storage_partition: partition@0 { label = "storage"; - reg = <0X0 DT_SIZE_K(32)>; + reg = <0x0 DT_SIZE_K(32)>; }; }; }; diff --git a/boards/renesas/ek_ra6m3/ek_ra6m3.dts b/boards/renesas/ek_ra6m3/ek_ra6m3.dts index ce22f083a3fe..44eb89fd38b9 100644 --- a/boards/renesas/ek_ra6m3/ek_ra6m3.dts +++ b/boards/renesas/ek_ra6m3/ek_ra6m3.dts @@ -190,7 +190,7 @@ storage_partition: partition@0 { label = "storage"; - reg = <0X0 DT_SIZE_K(64)>; + reg = <0x0 DT_SIZE_K(64)>; }; }; }; diff --git a/boards/renesas/ek_ra6m4/ek_ra6m4.dts b/boards/renesas/ek_ra6m4/ek_ra6m4.dts index bf49ef63b040..4b4a6db6cb9c 100644 --- a/boards/renesas/ek_ra6m4/ek_ra6m4.dts +++ b/boards/renesas/ek_ra6m4/ek_ra6m4.dts @@ -10,6 +10,7 @@ #include #include #include +#include #include "ek_ra6m4-pinctrl.dtsi" @@ -46,6 +47,14 @@ }; }; + pwmleds { + compatible = "pwm-leds"; + + pwm_led1: pwm_led1 { + pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + }; + }; + mikrobus_header: mikrobus-connector { compatible = "mikro-bus"; #gpio-cells = <2>; @@ -146,6 +155,7 @@ aliases { led0 = &led1; + pwm-led0 = &pwm_led1; sw0 = &button0; sw1 = &button1; watchdog0 = &wdt; @@ -303,7 +313,7 @@ storage_partition: partition@0 { label = "storage"; - reg = <0X0 DT_SIZE_K(8)>; + reg = <0x0 DT_SIZE_K(8)>; }; }; }; @@ -352,7 +362,7 @@ pmod_header: &pmod2_header {}; }; ð { - local-mac-address = [74 90 50 B0 6D 5D]; + local-mac-address = [74 90 50 b0 6d 5d]; status = "okay"; phy-handle = <&phy>; }; diff --git a/boards/renesas/ek_ra6m4/ek_ra6m4.yaml b/boards/renesas/ek_ra6m4/ek_ra6m4.yaml index 85317151ba31..d7893d9d92dc 100644 --- a/boards/renesas/ek_ra6m4/ek_ra6m4.yaml +++ b/boards/renesas/ek_ra6m4/ek_ra6m4.yaml @@ -12,4 +12,5 @@ supported: - usbd - watchdog - counter + - pwm vendor: renesas diff --git a/boards/renesas/ek_ra6m5/ek_ra6m5.dts b/boards/renesas/ek_ra6m5/ek_ra6m5.dts index 28e844b3a1fb..6f63b055b1f4 100644 --- a/boards/renesas/ek_ra6m5/ek_ra6m5.dts +++ b/boards/renesas/ek_ra6m5/ek_ra6m5.dts @@ -284,7 +284,7 @@ storage_partition: partition@0 { label = "storage"; - reg = <0X0 DT_SIZE_K(8)>; + reg = <0x0 DT_SIZE_K(8)>; }; }; }; @@ -316,7 +316,7 @@ arduino_spi: &spi0 {}; }; ð { - local-mac-address = [74 90 50 B0 6D 5C]; + local-mac-address = [74 90 50 b0 6d 5c]; status = "okay"; phy-handle = <&phy>; }; diff --git a/boards/renesas/ek_ra8d1/CMakeLists.txt b/boards/renesas/ek_ra8d1/CMakeLists.txt index f52c37df7391..fd8969482903 100644 --- a/boards/renesas/ek_ra8d1/CMakeLists.txt +++ b/boards/renesas/ek_ra8d1/CMakeLists.txt @@ -1,10 +1,7 @@ -# Copyright (c) 2024 Renesas Electronics Corporation +# Copyright (c) 2024-2025 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 zephyr_include_directories(.) zephyr_library() zephyr_library_sources(board.c) - -zephyr_linker_sources_ifdef(CONFIG_MEMC - SECTIONS sdram.ld) diff --git a/boards/renesas/ek_ra8d1/Kconfig.defconfig b/boards/renesas/ek_ra8d1/Kconfig.defconfig index 23b19904e5b0..c8317b7acf4b 100644 --- a/boards/renesas/ek_ra8d1/Kconfig.defconfig +++ b/boards/renesas/ek_ra8d1/Kconfig.defconfig @@ -6,26 +6,4 @@ if BOARD_EK_RA8D1 configdefault NET_L2_ETHERNET default y -if DISPLAY - -if SHIELD_RTKMIPILCDB00000BE || SHIELD_RTK7EKA6M3B00001BU - -config MEMC - default y - -config RENESAS_RA_GLCDC_FRAME_BUFFER_SECTION - default ".sdram" - depends on RENESAS_RA_GLCDC - -endif # SHIELD_RTKMIPILCDB00000BE || SHIELD_RTK7EKA6M3B00001BU - -endif # DISPLAY - -if LVGL - -config LV_Z_VDB_CUSTOM_SECTION - default y - -endif # LVGL - endif # BOARD_EK_RA8D1 diff --git a/boards/renesas/ek_ra8d1/ek_ra8d1.dts b/boards/renesas/ek_ra8d1/ek_ra8d1.dts index ce3a34657dc2..83be7187b5f2 100644 --- a/boards/renesas/ek_ra8d1/ek_ra8d1.dts +++ b/boards/renesas/ek_ra8d1/ek_ra8d1.dts @@ -319,7 +319,7 @@ storage_partition: partition@0 { label = "storage"; - reg = <0X0 DT_SIZE_K(12)>; + reg = <0x0 DT_SIZE_K(12)>; }; }; }; @@ -367,7 +367,7 @@ }; ð { - local-mac-address = [74 90 50 B0 5D E9]; + local-mac-address = [74 90 50 b0 5d e9]; status = "okay"; phy-handle = <&phy>; }; @@ -425,11 +425,11 @@ pinctrl-0 = <&sdram_default>; pinctrl-names = "default"; status = "okay"; - auto-refresh-interval = ; - auto-refresh-count = ; + auto-refresh-interval = ; + auto-refresh-count = ; precharge-cycle-count = ; multiplex-addr-shift = "10-bit"; - edian-mode = "little-endian"; + endian-mode = "little-endian"; continuous-access; bus-width = "16-bit"; diff --git a/boards/renesas/ek_ra8d1/sdram.ld b/boards/renesas/ek_ra8d1/sdram.ld deleted file mode 100644 index 5855e663d095..000000000000 --- a/boards/renesas/ek_ra8d1/sdram.ld +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright (c) 2024 Renesas Electronics Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#if DT_NODE_HAS_STATUS(DT_NODELABEL(sdram1), okay) - -SECTION_DATA_PROLOGUE(.sdram,(NOLOAD),) -{ - __SDRAM_Start = .; - KEEP(*(.sdram*)) -#ifdef CONFIG_LVGL - KEEP(*(.lvgl_buf*)) -#endif - __SDRAM_End = .; -} GROUP_LINK_IN(SDRAM) - -#endif diff --git a/boards/renesas/ek_ra8d2/CMakeLists.txt b/boards/renesas/ek_ra8d2/CMakeLists.txt index 6e7e11bab968..0a8bbb60fffe 100644 --- a/boards/renesas/ek_ra8d2/CMakeLists.txt +++ b/boards/renesas/ek_ra8d2/CMakeLists.txt @@ -2,6 +2,3 @@ # SPDX-License-Identifier: Apache-2.0 zephyr_include_directories(.) - -zephyr_linker_sources_ifdef(CONFIG_MEMC - SECTIONS sdram.ld) diff --git a/boards/renesas/ek_ra8d2/ek_ra8d2.dtsi b/boards/renesas/ek_ra8d2/ek_ra8d2.dtsi index 85d6734513c4..d2a2c7b02db2 100644 --- a/boards/renesas/ek_ra8d2/ek_ra8d2.dtsi +++ b/boards/renesas/ek_ra8d2/ek_ra8d2.dtsi @@ -203,11 +203,11 @@ pinctrl-0 = <&sdram_default>; pinctrl-names = "default"; status = "okay"; - auto-refresh-interval = ; - auto-refresh-count = ; + auto-refresh-interval = ; + auto-refresh-count = ; precharge-cycle-count = ; multiplex-addr-shift = "9-bit"; - edian-mode = "little-endian"; + endian-mode = "little-endian"; continuous-access; bus-width = "32-bit"; diff --git a/boards/renesas/ek_ra8d2/sdram.ld b/boards/renesas/ek_ra8d2/sdram.ld deleted file mode 100644 index 44d2efd360cc..000000000000 --- a/boards/renesas/ek_ra8d2/sdram.ld +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright (c) 2025 Renesas Electronics Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#if DT_NODE_HAS_STATUS(DT_NODELABEL(sdram1), okay) - -SECTION_DATA_PROLOGUE(.sdram,(NOLOAD),) -{ - __SDRAM_Start = .; - KEEP(*(.sdram*)) -#ifdef CONFIG_LVGL - KEEP(*(.lvgl_buf*)) -#endif - __SDRAM_End = .; -} GROUP_LINK_IN(SDRAM) - -#endif diff --git a/boards/renesas/ek_ra8m1/ek_ra8m1.dts b/boards/renesas/ek_ra8m1/ek_ra8m1.dts index 9cec8fe638dc..de68c6933123 100644 --- a/boards/renesas/ek_ra8m1/ek_ra8m1.dts +++ b/boards/renesas/ek_ra8m1/ek_ra8m1.dts @@ -371,7 +371,7 @@ mikrobus_spi: &spi1 {}; storage_partition: partition@0 { label = "storage"; - reg = <0X0 DT_SIZE_K(12)>; + reg = <0x0 DT_SIZE_K(12)>; }; }; }; @@ -397,7 +397,7 @@ pmod_serial: &pmod1_serial {}; pmod_header: &pmod1_header {}; ð { - local-mac-address = [74 90 50 B0 6D 5A]; + local-mac-address = [74 90 50 b0 6d 5a]; status = "okay"; phy-handle = <&phy>; }; diff --git a/boards/renesas/ek_ra8p1/CMakeLists.txt b/boards/renesas/ek_ra8p1/CMakeLists.txt index 6e7e11bab968..0a8bbb60fffe 100644 --- a/boards/renesas/ek_ra8p1/CMakeLists.txt +++ b/boards/renesas/ek_ra8p1/CMakeLists.txt @@ -2,6 +2,3 @@ # SPDX-License-Identifier: Apache-2.0 zephyr_include_directories(.) - -zephyr_linker_sources_ifdef(CONFIG_MEMC - SECTIONS sdram.ld) diff --git a/boards/renesas/ek_ra8p1/doc/index.rst b/boards/renesas/ek_ra8p1/doc/index.rst index 26652e6bd580..c2e8971bf58d 100644 --- a/boards/renesas/ek_ra8p1/doc/index.rst +++ b/boards/renesas/ek_ra8p1/doc/index.rst @@ -105,16 +105,16 @@ starting the CM33 core. Memory Usage ============ -By default, Flash (MRAM) and SRAM are split evenly between the two cores. -Users can manually change the address and size for Flash and SRAM as follows node: +By default, MRAM (Flash) and SRAM are split evenly between the two cores. +Users can manually change the address and size for MRAM (Flash) and SRAM as follows node: - - CPU0: &flash0, &sram0 - - CPU1: &flash1, &sram1 + - CPU0: &code_mram_cm85, &sram0 + - CPU1: &code_mram_cm33, &sram1 .. note:: - - Flash usable range: 0x0200_0000 ... 0x0290_0000 - - SRAM usable range: 0x2200_0000 ... 0x221D_4000 + - MRAM usable range: 0x0200_0000 ... 0x0210_0000 (1 MB) + - SRAM usable range: 0x2200_0000 ... 0x221A_0000 (1664 KB) Dual Core Flashing ================== @@ -147,6 +147,16 @@ see the following message in the terminal: ***** Booting Zephyr OS v4.2.0-xxx-xxxxxxxxxxxxx ***** Hello World! ek_ra8p1/r7ka8p1kflcac/cm85 +For the CM33 core, you can use the ``--sysbuild`` flow to build a minimal first-core launcher image that +starts the CM33 core. + +.. zephyr-app-commands:: + :tool: west + :zephyr-app: samples/hello_world + :board: ek_ra8p1/r7ka8p1kflcac/cm33 + :goals: build flash + :west-args: --sysbuild + Flashing ======== diff --git a/boards/renesas/ek_ra8p1/ek_ra8p1.dtsi b/boards/renesas/ek_ra8p1/ek_ra8p1.dtsi index 7a1a2a05bdcc..f123a2fefc94 100644 --- a/boards/renesas/ek_ra8p1/ek_ra8p1.dtsi +++ b/boards/renesas/ek_ra8p1/ek_ra8p1.dtsi @@ -143,6 +143,12 @@ &ioport1 { status = "okay"; + + mipi_dphy_gpio: mipi-dphy-enable { + gpio-hog; + gpios = <8 GPIO_ACTIVE_LOW>; + output-low; + }; }; &ioport2 { @@ -197,11 +203,11 @@ pinctrl-0 = <&sdram_default>; pinctrl-names = "default"; status = "okay"; - auto-refresh-interval = ; - auto-refresh-count = ; + auto-refresh-interval = ; + auto-refresh-count = ; precharge-cycle-count = ; multiplex-addr-shift = "9-bit"; - edian-mode = "little-endian"; + endian-mode = "little-endian"; continuous-access; bus-width = "32-bit"; diff --git a/boards/renesas/ek_ra8p1/ek_ra8p1_r7ka8p1kflcac_cm85.dts b/boards/renesas/ek_ra8p1/ek_ra8p1_r7ka8p1kflcac_cm85.dts index 4923dcc87cce..17e0de1f992d 100644 --- a/boards/renesas/ek_ra8p1/ek_ra8p1_r7ka8p1kflcac_cm85.dts +++ b/boards/renesas/ek_ra8p1/ek_ra8p1_r7ka8p1kflcac_cm85.dts @@ -25,6 +25,19 @@ aliases { led0 = &led1; sw0 = &button0; + mipi-dsi = &mipi_dsi; + }; + + renesas_mipi_connector: mipi-connector { + compatible = "renesas,ra-gpio-mipi-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <14 0 &ioport5 11 0>, /* IIC_SDA */ + <15 0 &ioport5 14 0>, /* DISP_BLEN */ + <16 0 &ioport5 12 0>, /* IIC_SCL */ + <17 0 &ioport1 11 0>, /* DISP_INT */ + <18 0 &ioport6 6 0>; /* DISP_RST */ }; }; @@ -171,8 +184,22 @@ }; }; +&mipi_dsi { + interrupts = <24 12>, <25 12>, <26 12>, <27 12>, <28 12>, <29 12>; + interrupt-names = "sq0", "sq1", "vm", "rcv", "ferr", "ppi"; +}; + +&lcdif { + interrupts = <30 1>; + interrupt-names = "line"; +}; + zephyr_lcdif: &lcdif {}; +zephyr_mipi_dsi: &mipi_dsi {}; + +renesas_mipi_i2c: &iic1 {}; + pmod_sd_shield: &sdhc0 {}; arducam_ffc_40pin_i2c: &iic1 {}; diff --git a/boards/renesas/ek_ra8p1/sdram.ld b/boards/renesas/ek_ra8p1/sdram.ld deleted file mode 100644 index 44d2efd360cc..000000000000 --- a/boards/renesas/ek_ra8p1/sdram.ld +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright (c) 2025 Renesas Electronics Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#if DT_NODE_HAS_STATUS(DT_NODELABEL(sdram1), okay) - -SECTION_DATA_PROLOGUE(.sdram,(NOLOAD),) -{ - __SDRAM_Start = .; - KEEP(*(.sdram*)) -#ifdef CONFIG_LVGL - KEEP(*(.lvgl_buf*)) -#endif - __SDRAM_End = .; -} GROUP_LINK_IN(SDRAM) - -#endif diff --git a/boards/renesas/ek_rx261/ek_rx261-pinctrl.dtsi b/boards/renesas/ek_rx261/ek_rx261-pinctrl.dtsi index a7aee5391fad..f3699eb3c7ff 100644 --- a/boards/renesas/ek_rx261/ek_rx261-pinctrl.dtsi +++ b/boards/renesas/ek_rx261/ek_rx261-pinctrl.dtsi @@ -20,4 +20,19 @@ ; }; }; + + i2c0_default: i2c0_default { + group1 { + psels = , /* SDA P13*/ + ; /* SCL P12*/ + }; + }; + + adc_default: adc_default { + group1 { + /* input */ + psels = ; + renesas,analog-enable; + }; + }; }; diff --git a/boards/renesas/ek_rx261/ek_rx261.dts b/boards/renesas/ek_rx261/ek_rx261.dts index d31fa30a0101..9ef757f9ed40 100644 --- a/boards/renesas/ek_rx261/ek_rx261.dts +++ b/boards/renesas/ek_rx261/ek_rx261.dts @@ -9,6 +9,8 @@ #include #include #include "ek_rx261-pinctrl.dtsi" +#include +#include / { model = "Renesas EK-RX261 KIT"; @@ -17,6 +19,7 @@ chosen { zephyr,sram = &sram0; zephyr,flash = &code_flash; + zephyr,flash-controller = &flash; zephyr,console = &uart6; zephyr,shell-uart = &uart6; }; @@ -40,10 +43,29 @@ }; }; + buttons { + compatible = "gpio-keys"; + + sw1: button1 { + label = "Key"; + gpios = <&ioportd 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + }; + + sw2: button2 { + label = "Key"; + gpios = <&ioport3 2 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + }; + }; + aliases { led0 = &led1; led1 = &led2; led2 = &led3; + + sw0 = &sw1; + sw1 = &sw2; }; }; @@ -102,3 +124,37 @@ ssl-assert = <0>; status = "okay"; }; + +&data_flash { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + storage_partition: partition@0 { + label = "storage"; + reg = <0x0 DT_SIZE_K(8)>; + }; + }; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + clock-frequency = ; + status = "okay"; +}; + +&adc { + pinctrl-0 = <&adc_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&port_irq0 { + status = "okay"; +}; + +&port_irq1 { + status = "okay"; +}; diff --git a/boards/renesas/fpb_ra4e1/fpb_ra4e1.dts b/boards/renesas/fpb_ra4e1/fpb_ra4e1.dts index 4f62f92bc014..d01787531b91 100644 --- a/boards/renesas/fpb_ra4e1/fpb_ra4e1.dts +++ b/boards/renesas/fpb_ra4e1/fpb_ra4e1.dts @@ -152,7 +152,7 @@ storage_partition: partition@0 { label = "storage"; - reg = <0X0 DT_SIZE_K(8)>; + reg = <0x0 DT_SIZE_K(8)>; }; }; }; diff --git a/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts b/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts index 61a1bc73235c..81dd91984002 100644 --- a/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts +++ b/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts @@ -93,10 +93,6 @@ status = "okay"; }; -&subclk { - status = "okay"; -}; - &pll { clocks = <&hoco>; div = <2>; @@ -112,7 +108,7 @@ storage_partition: partition@0 { label = "storage"; - reg = <0X0 DT_SIZE_K(8)>; + reg = <0x0 DT_SIZE_K(8)>; }; }; }; diff --git a/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts b/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts index e5965dd83c49..26dd38f38bb3 100644 --- a/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts +++ b/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts @@ -90,7 +90,7 @@ storage_partition: partition@0 { label = "storage"; - reg = <0X0 DT_SIZE_K(4)>; + reg = <0x0 DT_SIZE_K(4)>; }; }; }; diff --git a/boards/renesas/fpb_rx140/Kconfig.fpb_rx140 b/boards/renesas/fpb_rx140/Kconfig.fpb_rx140 new file mode 100644 index 000000000000..bb24550f6199 --- /dev/null +++ b/boards/renesas/fpb_rx140/Kconfig.fpb_rx140 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_FPB_RX140 + select SOC_R5F51406BGFN diff --git a/boards/renesas/fpb_rx140/board.cmake b/boards/renesas/fpb_rx140/board.cmake new file mode 100644 index 000000000000..2c4355c7fad8 --- /dev/null +++ b/boards/renesas/fpb_rx140/board.cmake @@ -0,0 +1,9 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +# options after "--tool-opt=" are directly passed to the tool. So instead of "--iface=JTAG" you could also write "--tool-opt=-if JTAG" +board_runner_args(jlink "--device=R5F51406" "--iface=FINE" "--speed=1000" "--tool-opt=-jtagconf -1,-1 -autoconnect 1") +board_runner_args(rfp "--device=RX100" "--tool=e2l" "--interface=fine" "--erase") + +include(${ZEPHYR_BASE}/boards/common/rfp.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/renesas/fpb_rx140/board.yml b/boards/renesas/fpb_rx140/board.yml new file mode 100644 index 000000000000..72b8ee0161b4 --- /dev/null +++ b/boards/renesas/fpb_rx140/board.yml @@ -0,0 +1,6 @@ +board: + name: fpb_rx140 + full_name: Fast Prototyping Board for RX140 + vendor: renesas + socs: + - name: r5f51406bgfn diff --git a/boards/renesas/fpb_rx140/doc/fpb_rx140.webp b/boards/renesas/fpb_rx140/doc/fpb_rx140.webp new file mode 100644 index 000000000000..ce5bd178803b Binary files /dev/null and b/boards/renesas/fpb_rx140/doc/fpb_rx140.webp differ diff --git a/boards/renesas/fpb_rx140/doc/index.rst b/boards/renesas/fpb_rx140/doc/index.rst new file mode 100644 index 000000000000..b6ed1898ede7 --- /dev/null +++ b/boards/renesas/fpb_rx140/doc/index.rst @@ -0,0 +1,148 @@ +.. zephyr:board:: fpb_rx140 + +Overview +******** + +The Fast Prototyping Board for RX140 MCU Group comes equipped with an RX140 MCU +(R5F51406BGFN). The board is inexpensive for RX140 evaluation and prototype development of +various applications. It has an emulator circuit so you can write/debug programs just by +connecting it to a PC with a USB cable. In addition, it has high expandability with Arduino Uno +and two Pmod™ connectors as standard, and through-hole access to all pins of the +microcontroller. + +**MCU Native Pin Access** + +- R5F51406ADFN MCU + + - Max 48MHz, 32-bit RXv2 core (RXv2) + - 256 KB Flash, 64 KB RAM + - 80-pin, LFQFP package + +- Native pin access through 2 x 40-pin male headers (not fitted) +- RX MCU current measurement point for precision current consumption measurement +- RX MCU on-chip oscillators as main clock +- Providing 32.768 kHz crystal oscillator as sub clock + +**System Control and Ecosystem Access** + +- Two 5 V input sources + + - USB + - External power supply (using 2-pin header [not fitted]) + +- On-board debugger / programmer (E2 emulator On Board (referred as E2OB, FINE Interface)) + +- User LEDs and switches + + - Two User LEDs (green) + - Power LED (green) indicating availability of regulated power + - Debug LED (yellow) indicating the debug connection + - One User switch + - One Reset switch + +- Two popular ecosystem expansions + + - Two Digilent PmodTM + - Arduino® (Uno R3) connector + +Hardware +******** +Detailed hardware features can be found at: + +- RX140 MCU: `RX140 Group User's Manual Hardware`_ +- FPB-RX140: `FPB_RX140 - User's Manual`_ + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Applications for the ``fpb_rx140`` board can be built, flashed, and debugged using standard +Zephyr workflows. Refer to :ref:`build_an_application` and :ref:`application_run` for more details. + +**Note:** Currently, the RX140 is built and programmed using the Renesas GCC RX toolchain. +Please follow the steps below to program it onto the board: + + - Download and install GCC for RX toolchain: + + https://llvm-gcc-renesas.com/rx-download-toolchains/ + + - Set env variable: + + .. code-block:: console + + export ZEPHYR_TOOLCHAIN_VARIANT=cross-compile + export CROSS_COMPILE=/bin/rx-elf- + + - Build the Blinky Sample for FPB-RX140 + + .. code-block:: console + + cd ~/zephyrproject/zephyr + west build -p always -b fpb_rx140 samples/basic/blinky + +Flashing +======== + +The program can be flashed to RSK-RX140 using the **E2OB** by connecting the board to the host PC +and open Jumper J4. +Here’s an example for building and flashing the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rsk_rx140 + :goals: build flash + +Debugging +========= + +You can use `Renesas Debug extension`_ on Visual Studio Code for a visual debug interface. +The configuration for launch.json is as below. + +.. code-block:: json + + { + "version": "0.2.0", + "configurations": [ + { + "type": "renesas-hardware", + "request": "launch", + "name": "RX140 Renesas Debugging E2lite", + "target": { + "deviceFamily": "RX", + "device": "R5F51406", + "debuggerType": "E2LITE" + "serverParameters": [ + "-uUseFine=", "1", + "-w=", "0", + ], + } + } + ] + } + +References +********** + +- `FPB_RX140 Website`_ +- `RX140 MCU group Website`_ + +.. _FPB_RX140 Website: + https://www.renesas.com/en/design-resources/boards-kits/fpb-rx140 + +.. _RX140 MCU group Website: + https://www.renesas.com/en/products/rx140 + +.. _FPB_RX140 - User's Manual: + https://www.renesas.com/en/document/mat/fpb-rx140-v1-users-manual + +.. _RX140 Group User's Manual Hardware: + https://www.renesas.com/en/document/mah/rx140-group-users-manual-hardware-rev120 + +.. _Renesas Debug extension: + https://marketplace.visualstudio.com/items?itemName=RenesasElectronicsCorporation.renesas-debug diff --git a/boards/renesas/fpb_rx140/fpb_rx140-pinctrl.dtsi b/boards/renesas/fpb_rx140/fpb_rx140-pinctrl.dtsi new file mode 100644 index 000000000000..01b66421b27a --- /dev/null +++ b/boards/renesas/fpb_rx140/fpb_rx140-pinctrl.dtsi @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci5_default: sci5_default { + group1 { + psels = , /* TX */ + ; /* RX */ + }; + }; + + adc_default: adc_default { + group1 { + /* input */ + psels = ; + renesas,analog-enable; + }; + }; + + rspi0_default: rspi0_default { + group1 { + psels = , + , + , + ; + }; + }; + + i2c0_default: i2c0_default { + group1 { + psels = , /* SDA P17 */ + ; /* SCL P16 */ + }; + }; + + pwm1_default: pwm1_default { + group1 { + psels = ; /* P20 MTIOC1A*/ + }; + }; +}; diff --git a/boards/renesas/fpb_rx140/fpb_rx140.dts b/boards/renesas/fpb_rx140/fpb_rx140.dts new file mode 100644 index 000000000000..980dae16643c --- /dev/null +++ b/boards/renesas/fpb_rx140/fpb_rx140.dts @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include "fpb_rx140-pinctrl.dtsi" +#include +#include + +/ { + model = "Renesas FPB-RX140 KIT"; + compatible = "renesas,fpb_rx140"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &code_flash; + zephyr,flash-controller = &flash; + zephyr,console = &uart5; + zephyr,shell-uart = &uart5; + }; + + leds { + compatible = "gpio-leds"; + + led1: led1 { + gpios = <&ioport2 0 GPIO_ACTIVE_LOW>; + label = "LED1"; + }; + + led2: led2 { + gpios = <&ioport3 2 GPIO_ACTIVE_LOW>; + label = "LED2"; + }; + }; + + buttons { + compatible = "gpio-keys"; + + sw1: button { + label = "sw1"; + gpios = <&ioport3 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + }; + }; + + aliases { + led0 = &led1; + led1 = &led2; + sw0 = &sw1; + watchdog0 = &iwdt; + }; +}; + +&subclk { + status = "okay"; +}; + +&pclkblock { + clocks = <&hoco>; +}; + +&cmt { + clock-frequency = <3000000>; + status = "okay"; +}; + +&ioport2 { + status = "okay"; +}; + +&ioport3 { + status = "okay"; +}; + +&port_irq0 { + status = "okay"; +}; + +&mtu1 { + status = "okay"; + pinctrl-0 = <&pwm1_default>; + pinctrl-names = "default"; + + pwm1: pwm { + status = "okay"; + }; +}; + +&sci5 { + pinctrl-0 = <&sci5_default>; + pinctrl-names = "default"; + status = "okay"; + + uart5: uart { + current-speed = <115200>; + status = "okay"; + }; +}; + +&rspi0 { + pinctrl-0 = <&rspi0_default>; + pinctrl-names = "default"; + ssl-assert = <0>; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + clock-frequency = ; + status = "okay"; +}; + +&data_flash { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + storage_partition: partition@0 { + label = "storage"; + reg = <0X0 DT_SIZE_K(8)>; + }; + }; +}; + +&iwdt { + window-start = <0x3000>; + window-end = <0x0300>; + status = "okay"; +}; diff --git a/boards/renesas/fpb_rx140/fpb_rx140.yaml b/boards/renesas/fpb_rx140/fpb_rx140.yaml new file mode 100644 index 000000000000..4af8a8a48722 --- /dev/null +++ b/boards/renesas/fpb_rx140/fpb_rx140.yaml @@ -0,0 +1,14 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +identifier: fpb_rx140 +name: Fast Prototyping Board for RX140 +type: mcu +arch: rx +toolchain: + - cross-compile +supported: + - gpio + - serial +ram: 64 +flash: 256 diff --git a/boards/renesas/fpb_rx140/fpb_rx140_defconfig b/boards/renesas/fpb_rx140/fpb_rx140_defconfig new file mode 100644 index 000000000000..c23cdd58f2a0 --- /dev/null +++ b/boards/renesas/fpb_rx140/fpb_rx140_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/renesas/fpb_rx261/fpb_rx261-pinctrl.dtsi b/boards/renesas/fpb_rx261/fpb_rx261-pinctrl.dtsi index f1615e47d5bf..1d7887fd286e 100644 --- a/boards/renesas/fpb_rx261/fpb_rx261-pinctrl.dtsi +++ b/boards/renesas/fpb_rx261/fpb_rx261-pinctrl.dtsi @@ -20,4 +20,19 @@ ; }; }; + + i2c0_default: i2c0_default { + group1 { + psels = , /* SDA P13*/ + ; /* SCL P12*/ + }; + }; + + adc_default: adc_default { + group1 { + /* input */ + psels = ; + renesas,analog-enable; + }; + }; }; diff --git a/boards/renesas/fpb_rx261/fpb_rx261.dts b/boards/renesas/fpb_rx261/fpb_rx261.dts index d27e2d184542..d9877e56c4be 100644 --- a/boards/renesas/fpb_rx261/fpb_rx261.dts +++ b/boards/renesas/fpb_rx261/fpb_rx261.dts @@ -9,6 +9,8 @@ #include #include #include "fpb_rx261-pinctrl.dtsi" +#include +#include / { model = "Renesas FPB-RX261"; @@ -17,6 +19,7 @@ chosen { zephyr,sram = &sram0; zephyr,flash = &code_flash; + zephyr,flash-controller = &flash; zephyr,console = &uart5; zephyr,shell-uart = &uart5; }; @@ -35,9 +38,21 @@ }; }; + buttons { + compatible = "gpio-keys"; + + sw1: button1 { + label = "Key"; + gpios = <&ioport3 2 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + }; + }; + aliases { led0 = &led1; led1 = &led2; + + sw0 = &sw1; }; }; @@ -91,3 +106,37 @@ ssl-assert = <0>; status = "okay"; }; + +&data_flash { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + storage_partition: partition@0 { + label = "storage"; + reg = <0x0 DT_SIZE_K(8)>; + }; + }; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + clock-frequency = ; + status = "okay"; +}; + +&adc { + pinctrl-0 = <&adc_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&port_irq1 { + status = "okay"; +}; + +&port_irq2 { + status = "okay"; +}; diff --git a/boards/renesas/mck_ra8t1/mck_ra8t1.dts b/boards/renesas/mck_ra8t1/mck_ra8t1.dts index 90528485d355..09ca045200f6 100644 --- a/boards/renesas/mck_ra8t1/mck_ra8t1.dts +++ b/boards/renesas/mck_ra8t1/mck_ra8t1.dts @@ -63,10 +63,6 @@ status = "okay"; }; -&subclk { - status = "okay"; -}; - &pll { status = "okay"; @@ -171,7 +167,7 @@ storage_partition: partition@0 { label = "storage"; - reg = <0X0 DT_SIZE_K(12)>; + reg = <0x0 DT_SIZE_K(12)>; }; }; }; @@ -204,7 +200,7 @@ }; ð { - local-mac-address = [74 90 50 6D 81 75]; + local-mac-address = [74 90 50 6d 81 75]; status = "okay"; phy-handle = <&phy>; }; diff --git a/boards/renesas/mck_ra8t2/Kconfig.mck_ra8t2 b/boards/renesas/mck_ra8t2/Kconfig.mck_ra8t2 index ba0ca76b5d2f..28da044ae41e 100644 --- a/boards/renesas/mck_ra8t2/Kconfig.mck_ra8t2 +++ b/boards/renesas/mck_ra8t2/Kconfig.mck_ra8t2 @@ -2,5 +2,5 @@ # SPDX-License-Identifier: Apache-2.0 config BOARD_MCK_RA8T2 - select SOC_R7KA8T2LFECAC_CM85 if BOARD_MCK_RA8T2_R7KA8T2LFECAC_CM85 - select SOC_R7KA8T2LFECAC_CM33 if BOARD_MCK_RA8T2_R7KA8T2LFECAC_CM33 + select SOC_R7KA8T2LFLCAC_CM85 if BOARD_MCK_RA8T2_R7KA8T2LFLCAC_CM85 + select SOC_R7KA8T2LFLCAC_CM33 if BOARD_MCK_RA8T2_R7KA8T2LFLCAC_CM33 diff --git a/boards/renesas/mck_ra8t2/board.cmake b/boards/renesas/mck_ra8t2/board.cmake index 39712afe86e8..9430935aab35 100644 --- a/boards/renesas/mck_ra8t2/board.cmake +++ b/boards/renesas/mck_ra8t2/board.cmake @@ -1,7 +1,7 @@ # Copyright (c) 2025 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 -if(CONFIG_SOC_R7KA8T2LFECAC_CM85) +if(CONFIG_SOC_R7KA8T2LFLCAC_CM85) board_runner_args(jlink "--device=R7KA8T2LF_CPU0" "--reset-after-load") endif() diff --git a/boards/renesas/mck_ra8t2/board.yml b/boards/renesas/mck_ra8t2/board.yml index 2981b49915b4..81358c562bab 100644 --- a/boards/renesas/mck_ra8t2/board.yml +++ b/boards/renesas/mck_ra8t2/board.yml @@ -3,4 +3,4 @@ board: full_name: RA8T2 Motor Control Kit vendor: renesas socs: - - name: r7ka8t2lfecac + - name: r7ka8t2lflcac diff --git a/boards/renesas/mck_ra8t2/doc/index.rst b/boards/renesas/mck_ra8t2/doc/index.rst index c3f9dd728894..dcbc8e323751 100644 --- a/boards/renesas/mck_ra8t2/doc/index.rst +++ b/boards/renesas/mck_ra8t2/doc/index.rst @@ -88,7 +88,7 @@ Here is an example for the :zephyr:code-sample:`hello_world` application on CM85 .. zephyr-app-commands:: :zephyr-app: samples/hello_world - :board: mck_ra8t2/r7ka8t2lfecac/cm85 + :board: mck_ra8t2/r7ka8t2lflcac/cm85 :goals: flash Open a serial terminal, reset the board (push the reset switch S1), and you should @@ -97,7 +97,7 @@ see the following message in the terminal: .. code-block:: console ***** Booting Zephyr OS v4.2.0-xxx-xxxxxxxxxxxxx ***** - Hello World! mck_ra8t2/r7ka8t2lfecac/cm85 + Hello World! mck_ra8t2/r7ka8t2lflcac/cm85 Flashing ======== @@ -128,7 +128,7 @@ To build the sample application using sysbuild use the command: .. zephyr-app-commands:: :tool: west :zephyr-app: samples/hello_world - :board: mck_ra8t2/r7ka8t2lfecac/cm85 + :board: mck_ra8t2/r7ka8t2lflcac/cm85 :goals: build flash :west-args: --sysbuild :gen-args: -DSB_CONFIG_BOOTLOADER_MCUBOOT=y @@ -188,7 +188,7 @@ You should see the following message in the terminal: I: Image version: v0.0.0 I: Jumping to the first image slot *** Booting Zephyr OS build v4.2.0-6156-ged85ac9ffda9 *** - Hello World! mck_ra8t2/r7ka8t2lfecac/cm85 + Hello World! mck_ra8t2/r7ka8t2lflcac/cm85 References ********** diff --git a/boards/renesas/mck_ra8t2/mck_ra8t2.dtsi b/boards/renesas/mck_ra8t2/mck_ra8t2.dtsi index 31a12eac7840..161dbe0d6546 100644 --- a/boards/renesas/mck_ra8t2/mck_ra8t2.dtsi +++ b/boards/renesas/mck_ra8t2/mck_ra8t2.dtsi @@ -51,10 +51,6 @@ status = "okay"; }; -&subclk { - status = "okay"; -}; - &pll { status = "okay"; diff --git a/boards/renesas/mck_ra8t2/mck_ra8t2_r7ka8t2lfecac_cm85.dts b/boards/renesas/mck_ra8t2/mck_ra8t2_r7ka8t2lfecac_cm85.dts deleted file mode 100644 index 2603cf3fb959..000000000000 --- a/boards/renesas/mck_ra8t2/mck_ra8t2_r7ka8t2lfecac_cm85.dts +++ /dev/null @@ -1,134 +0,0 @@ -/* - * Copyright (c) 2025 Renesas Electronics Corporation - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "mck_ra8t2.dtsi" - -/ { - model = "Renesas MCK-RA8T2"; - compatible = "renesas,ra8t2", "renesas,ra8"; - - chosen { - zephyr,sram = &sram0; - zephyr,flash = &code_mram_cm85; - zephyr,flash-controller = &mram_ctrl; - zephyr,code-partition = &slot0_partition; - zephyr,console = &uart9; - zephyr,shell-uart = &uart9; - }; - - aliases { - led0 = &led1; - sdhc0 = &sdhc0; - }; -}; - -&sci9 { - pinctrl-0 = <&sci9_default>; - pinctrl-names = "default"; - interrupts = <0 1>, <1 1>, <2 1>, <3 1>; - interrupt-names = "rxi", "txi", "tei", "eri"; - status = "okay"; - - uart9: uart { - current-speed = <115200>; - status = "okay"; - }; -}; - -&sci4 { - pinctrl-0 = <&sci4_default>; - pinctrl-names = "default"; - interrupts = <4 1>, <5 1>, <6 1>, <7 1>; - interrupt-names = "rxi", "txi", "tei", "eri"; - status = "okay"; - - uart4: uart { - current-speed = <115200>; - status = "okay"; - }; -}; - -&spi0 { - pinctrl-0 = <&spi0_default>; - pinctrl-names = "default"; - interrupts = <8 1>, <9 1>, <10 1>, <11 1>; - interrupt-names = "rxi", "txi", "tei", "eri"; - status = "okay"; -}; - -&ulpt0 { - interrupts = <12 1>; - interrupt-names = "ulpti"; - status = "okay"; - - timer { - status = "okay"; - }; -}; - -&ulpt1 { - status = "okay"; - - timer { - status = "okay"; - }; -}; - -&sdhc0 { - pinctrl-0 = <&sdhc0_default>; - pinctrl-names = "default"; - enable-gpios = <&ioportb 6 GPIO_ACTIVE_HIGH>; - interrupt-names = "accs", "card", "dma-req"; - interrupts = <13 1>, <14 1>, <15 1>; - status = "okay"; - - sdmmc { - compatible = "zephyr,sdmmc-disk"; - disk-name = "SD"; - status = "okay"; - }; -}; - -&usbfs { - pinctrl-0 = <&usbfs_default>; - interrupts = <16 12>, <17 12>; - interrupt-names = "usbfs-i", "usbfs-r"; - status = "okay"; - - zephyr_udc0: udc { - status = "okay"; - }; -}; - -&code_mram_cm85 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x0 DT_SIZE_K(64)>; - }; - - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x10000 DT_SIZE_K(464)>; - }; - - slot1_partition: partition@84000 { - label = "image-1"; - reg = <0x84000 DT_SIZE_K(464)>; - }; - - storage_partition: partition@f8000 { - label = "storage"; - reg = <0xf8000 DT_SIZE_K(32)>; - }; - }; -}; diff --git a/boards/renesas/mck_ra8t2/mck_ra8t2_r7ka8t2lfecac_cm85.yaml b/boards/renesas/mck_ra8t2/mck_ra8t2_r7ka8t2lfecac_cm85.yaml deleted file mode 100644 index 94277f34b2c4..000000000000 --- a/boards/renesas/mck_ra8t2/mck_ra8t2_r7ka8t2lfecac_cm85.yaml +++ /dev/null @@ -1,13 +0,0 @@ -identifier: mck_ra8t2/r7ka8t2lfecac/cm85 -name: Renesas MCK-RA8T2 -type: mcu -arch: arm -ram: 1664 -flash: 1024 -toolchain: - - zephyr - - gnuarmemb -supported: - - gpio - - uart -vendor: renesas diff --git a/boards/renesas/mck_ra8t2/mck_ra8t2_r7ka8t2lflcac_cm85.dts b/boards/renesas/mck_ra8t2/mck_ra8t2_r7ka8t2lflcac_cm85.dts new file mode 100644 index 000000000000..e88d85f6a234 --- /dev/null +++ b/boards/renesas/mck_ra8t2/mck_ra8t2_r7ka8t2lflcac_cm85.dts @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "mck_ra8t2.dtsi" + +/ { + model = "Renesas MCK-RA8T2"; + compatible = "renesas,ra8t2", "renesas,ra8"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &code_mram_cm85; + zephyr,flash-controller = &mram_ctrl; + zephyr,code-partition = &slot0_partition; + zephyr,console = &uart9; + zephyr,shell-uart = &uart9; + }; + + aliases { + led0 = &led1; + sdhc0 = &sdhc0; + }; +}; + +&sci9 { + pinctrl-0 = <&sci9_default>; + pinctrl-names = "default"; + interrupts = <0 1>, <1 1>, <2 1>, <3 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + status = "okay"; + + uart9: uart { + current-speed = <115200>; + status = "okay"; + }; +}; + +&sci4 { + pinctrl-0 = <&sci4_default>; + pinctrl-names = "default"; + interrupts = <4 1>, <5 1>, <6 1>, <7 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + status = "okay"; + + uart4: uart { + current-speed = <115200>; + status = "okay"; + }; +}; + +&spi0 { + pinctrl-0 = <&spi0_default>; + pinctrl-names = "default"; + interrupts = <8 1>, <9 1>, <10 1>, <11 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + status = "okay"; +}; + +&ulpt0 { + interrupts = <12 1>; + interrupt-names = "ulpti"; + status = "okay"; + + timer { + status = "okay"; + }; +}; + +&ulpt1 { + status = "okay"; + + timer { + status = "okay"; + }; +}; + +&sdhc0 { + pinctrl-0 = <&sdhc0_default>; + pinctrl-names = "default"; + enable-gpios = <&ioportb 6 GPIO_ACTIVE_HIGH>; + interrupt-names = "accs", "card", "dma-req"; + interrupts = <13 1>, <14 1>, <15 1>; + status = "okay"; + + sdmmc { + compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; + status = "okay"; + }; +}; + +&usbfs { + pinctrl-0 = <&usbfs_default>; + interrupts = <16 12>, <17 12>; + interrupt-names = "usbfs-i", "usbfs-r"; + status = "okay"; + + zephyr_udc0: udc { + status = "okay"; + }; +}; + +&code_mram_cm85 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x0 DT_SIZE_K(64)>; + }; + + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x10000 DT_SIZE_K(464)>; + }; + + slot1_partition: partition@84000 { + label = "image-1"; + reg = <0x84000 DT_SIZE_K(464)>; + }; + + storage_partition: partition@f8000 { + label = "storage"; + reg = <0xf8000 DT_SIZE_K(32)>; + }; + }; +}; diff --git a/boards/renesas/mck_ra8t2/mck_ra8t2_r7ka8t2lflcac_cm85.yaml b/boards/renesas/mck_ra8t2/mck_ra8t2_r7ka8t2lflcac_cm85.yaml new file mode 100644 index 000000000000..a1dbd0715dcf --- /dev/null +++ b/boards/renesas/mck_ra8t2/mck_ra8t2_r7ka8t2lflcac_cm85.yaml @@ -0,0 +1,13 @@ +identifier: mck_ra8t2/r7ka8t2lflcac/cm85 +name: Renesas MCK-RA8T2 +type: mcu +arch: arm +ram: 1664 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio + - uart +vendor: renesas diff --git a/boards/renesas/mck_ra8t2/mck_ra8t2_r7ka8t2lfecac_cm85_defconfig b/boards/renesas/mck_ra8t2/mck_ra8t2_r7ka8t2lflcac_cm85_defconfig similarity index 100% rename from boards/renesas/mck_ra8t2/mck_ra8t2_r7ka8t2lfecac_cm85_defconfig rename to boards/renesas/mck_ra8t2/mck_ra8t2_r7ka8t2lflcac_cm85_defconfig diff --git a/boards/renesas/rcar_h3ulcb/board.cmake b/boards/renesas/rcar_h3ulcb/board.cmake index 963f11d9f47d..a4f7eb2566d0 100644 --- a/boards/renesas/rcar_h3ulcb/board.cmake +++ b/boards/renesas/rcar_h3ulcb/board.cmake @@ -1,6 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 if(CONFIG_BOARD_RCAR_H3ULCB_R8A77951_R7) - board_runner_args(openocd "--use-elf") + board_runner_args(openocd "--file-type=elf") include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) endif() diff --git a/boards/renesas/rcar_h3ulcb/doc/index.rst b/boards/renesas/rcar_h3ulcb/doc/index.rst index 4203262958b8..ecc772336449 100644 --- a/boards/renesas/rcar_h3ulcb/doc/index.rst +++ b/boards/renesas/rcar_h3ulcb/doc/index.rst @@ -4,10 +4,10 @@ Overview ******** R-Car H3ULCB starter kit board is based on the R-Car H3 SoC that features basic functions for next-generation car navigation systems. -It is composed of a quad Cortex |reg|-A57, a quad Cortex |reg|-A53 cluster and a -dual lockstep Cortex |reg|-R7. +It is composed of a quad Cortex®-A57, a quad Cortex®-A53 cluster and a +dual lockstep Cortex®-R7. -Zephyr OS support is available for both Cortex |reg|-A cores & Cortex |reg|-R7 core. +Zephyr OS support is available for both Cortex®-A cores & Cortex®-R7 core. More information about the H3 SoC can be found at `Renesas R-Car H3 chip`_. diff --git a/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_a57.dts b/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_a57.dts index fdb378490a9b..73f7a8ae8bf3 100644 --- a/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_a57.dts +++ b/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_a57.dts @@ -21,7 +21,7 @@ }; ram: memory@48000000 { - device_type = "mmio-sram"; + device_type = "memory"; reg = <0x0 0x48000000 0x0 DT_SIZE_M(512)>; }; @@ -99,6 +99,7 @@ disk-name = "SD2"; status = "disabled"; }; + bus-width = <8>; mmc-hs200-1_8v; mmc-hs400-1_8v; diff --git a/boards/renesas/rcar_salvator_x/board.cmake b/boards/renesas/rcar_salvator_x/board.cmake index b106c562c540..928cdf5e8927 100644 --- a/boards/renesas/rcar_salvator_x/board.cmake +++ b/boards/renesas/rcar_salvator_x/board.cmake @@ -1,3 +1,3 @@ # SPDX-License-Identifier: Apache-2.0 -board_runner_args(openocd "--use-elf") +board_runner_args(openocd "--file-type=elf") include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/renesas/rcar_salvator_xs/rcar_salvator_xs.dts b/boards/renesas/rcar_salvator_xs/rcar_salvator_xs.dts index 152e4a63e381..692e8d1c221b 100644 --- a/boards/renesas/rcar_salvator_xs/rcar_salvator_xs.dts +++ b/boards/renesas/rcar_salvator_xs/rcar_salvator_xs.dts @@ -25,7 +25,7 @@ }; ram: memory@48000000 { - device_type = "mmio-sram"; + device_type = "memory"; reg = <0x0 0x48000000 0x0 DT_SIZE_M(512)>; }; }; diff --git a/boards/renesas/rcar_spider_s4/board.cmake b/boards/renesas/rcar_spider_s4/board.cmake index 01310776d4c7..4c632ce63a54 100644 --- a/boards/renesas/rcar_spider_s4/board.cmake +++ b/boards/renesas/rcar_spider_s4/board.cmake @@ -1,5 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 if(CONFIG_BOARD_RCAR_SPIDER_S4_R8A779F0_R52) - board_runner_args(openocd "--use-elf") + board_runner_args(openocd "--file-type=elf") include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) endif() diff --git a/boards/renesas/rcar_spider_s4/doc/index.rst b/boards/renesas/rcar_spider_s4/doc/index.rst index 703feb03bde2..84c3fd08d358 100644 --- a/boards/renesas/rcar_spider_s4/doc/index.rst +++ b/boards/renesas/rcar_spider_s4/doc/index.rst @@ -4,8 +4,8 @@ Overview ******** R-Car S4 Spider board is based on the R-Car S4 SoC made for Car -Server/Communication Gateway and that is composed of a octo Cortex |reg|-A55, a -dual lockstep Cortex |reg|-R52 and a double dual lockstep G4MH. +Server/Communication Gateway and that is composed of a octo Cortex®-A55, a +dual lockstep Cortex®-R52 and a double dual lockstep G4MH. The R-Car S4 SoC enables the launch of Car Server/CoGW with high performance, high-speed networking, high security and high functional safety levels that are @@ -19,7 +19,7 @@ basic software such as Linux BSP and hypervisors. The Renesas R-Car Spider board is the Renesas R-Car S4 reference board and is designed for evaluating features and performance of this SoC. -Zephyr OS support is available for both Cortex |reg|-A cores & Cortex |reg|-R52 core. +Zephyr OS support is available for both Cortex®-A cores & Cortex®-R52 core. More information about the S4 SoC can be found at `Renesas R-Car S4 chip`_. diff --git a/boards/renesas/rcar_spider_s4/rcar_spider_s4_r8a779f0_a55.dts b/boards/renesas/rcar_spider_s4/rcar_spider_s4_r8a779f0_a55.dts index 90a576961ad3..e2e6e8217b35 100644 --- a/boards/renesas/rcar_spider_s4/rcar_spider_s4_r8a779f0_a55.dts +++ b/boards/renesas/rcar_spider_s4/rcar_spider_s4_r8a779f0_a55.dts @@ -20,7 +20,7 @@ }; ram: memory@48000000 { - device_type = "mmio-sram"; + device_type = "memory"; reg = <0x0 0x48000000 0x0 DT_SIZE_M(512)>; }; }; diff --git a/boards/renesas/rsk_rx130/rsk_rx130.dts b/boards/renesas/rsk_rx130/rsk_rx130.dts index 92b04bcf6ec0..6c15d97e411a 100644 --- a/boards/renesas/rsk_rx130/rsk_rx130.dts +++ b/boards/renesas/rsk_rx130/rsk_rx130.dts @@ -196,7 +196,7 @@ storage_partition: partition@0 { label = "storage"; - reg = <0X0 DT_SIZE_K(8)>; + reg = <0x0 DT_SIZE_K(8)>; }; }; }; diff --git a/boards/renesas/rsk_rx140/Kconfig.rsk_rx140 b/boards/renesas/rsk_rx140/Kconfig.rsk_rx140 new file mode 100644 index 000000000000..d40e8e633b4f --- /dev/null +++ b/boards/renesas/rsk_rx140/Kconfig.rsk_rx140 @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RSK_RX140 + select SOC_R5F51406BDFN diff --git a/boards/renesas/rsk_rx140/board.cmake b/boards/renesas/rsk_rx140/board.cmake new file mode 100644 index 000000000000..2c4355c7fad8 --- /dev/null +++ b/boards/renesas/rsk_rx140/board.cmake @@ -0,0 +1,9 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +# options after "--tool-opt=" are directly passed to the tool. So instead of "--iface=JTAG" you could also write "--tool-opt=-if JTAG" +board_runner_args(jlink "--device=R5F51406" "--iface=FINE" "--speed=1000" "--tool-opt=-jtagconf -1,-1 -autoconnect 1") +board_runner_args(rfp "--device=RX100" "--tool=e2l" "--interface=fine" "--erase") + +include(${ZEPHYR_BASE}/boards/common/rfp.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/renesas/rsk_rx140/board.yml b/boards/renesas/rsk_rx140/board.yml new file mode 100644 index 000000000000..9a2f00910253 --- /dev/null +++ b/boards/renesas/rsk_rx140/board.yml @@ -0,0 +1,6 @@ +board: + name: rsk_rx140 + full_name: Renesas Starter Kit for RX140 + vendor: renesas + socs: + - name: r5f51406bdfn diff --git a/boards/renesas/rsk_rx140/doc/index.rst b/boards/renesas/rsk_rx140/doc/index.rst new file mode 100644 index 000000000000..1ce4926b02f0 --- /dev/null +++ b/boards/renesas/rsk_rx140/doc/index.rst @@ -0,0 +1,151 @@ +.. zephyr:board:: rsk_rx140 + +Overview +******** + +The Renesas Starter Kit for RX140 is an evaluation and starter kit for developers who are new +to the RX140 MCU family (Program Flash 256KB, RAM 64KB, Pin Count 80-pin). +The kit includes an LCD display module and an on-chip debugging emulator + +**MCU Native Pin Access** + +The RSK-RX140 includes: + +- 48-MHz, 32-bit RX140 MCU (R5F51406BDFN, 80-pin LFQFP package) +- Direct MCU pin access through standard headers for easy peripheral integration +- On-board 8 MHz crystal, 32.768 kHz sub-clock, and internal oscillators +- Multiple low power consumption modes + +**System Control and Debugging** + +- USB Mini-B connector for serial communication (via on-board RL78/G1C USB-to-Serial MCU) +- Power source options: + + - USB-powered + - External DC supply (5V input jack) + - Debugger supply (E2 Lite) + +- Debugging support: + + - Via E2 Lite debugger (14-pin connector) + +- User LEDs and buttons: + + - Four User LEDs (green, orange, red x2) + - Power LED (green) + - One Reset button, three User buttons + - One potentiometer (connected to ADC input) + +- Ecosystem expansions: + + - Two Digilent Pmod connectors (LCD and Spare) + - On-board 2Kbit I2C EEPROM + +**Special Feature Access** + +- Capacitive touch sensing (slider x1, buttons x2) +- CAN and LIN transceivers +- IEC60730 compliance support +- Security functions (built-in Trusted Secure IP) + +Hardware +******** +Detailed hardware features can be found at: + +- RX140 MCU: `RX140 Group User's Manual Hardware`_ +- RSK-RX140: `RSK_RX140 - User's Manual`_ + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Applications for the ``rsk_rx140`` board can be built, flashed, and debugged using standard +Zephyr workflows. Refer to :ref:`build_an_application` and :ref:`application_run` for more details. + +**Note:** Currently, the RX140 is built and programmed using the Renesas GCC RX toolchain. +Please follow the steps below to program it onto the board: + + - Download and install GCC for RX toolchain: + + https://llvm-gcc-renesas.com/rx-download-toolchains/ + + - Set env variable: + + .. code-block:: console + + export ZEPHYR_TOOLCHAIN_VARIANT=cross-compile + export CROSS_COMPILE=/bin/rx-elf- + + - Build the Blinky Sample for RSK-RX140 + + .. code-block:: console + + cd ~/zephyrproject/zephyr + west build -p always -b rsk_rx140 samples/basic/blinky + +Flashing +======== + +The program can be flashed to RSK-RX140 using the **E2 Lite debugger** by +connecting the board's 14-pin debug connector to the host PC. +Here’s an example for building and flashing the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rsk_rx140 + :goals: build flash + +Debugging +========= + +You can use `Renesas Debug extension`_ on Visual Studio Code for a visual debug interface. +The configuration for launch.json is as below. + +.. code-block:: json + + { + "version": "0.2.0", + "configurations": [ + { + "type": "renesas-hardware", + "request": "launch", + "name": "RX140 Renesas Debugging E2lite", + "target": { + "deviceFamily": "RX", + "device": "R5F51406", + "debuggerType": "E2LITE" + "serverParameters": [ + "-uUseFine=", "1", + "-w=", "0", + ], + } + } + ] + } + +References +********** + +- `RSK_RX140 Website`_ +- `RX140 MCU group Website`_ + +.. _RSK_RX140 Website: + https://www.renesas.com/en/design-resources/boards-kits/rsk-rx140 + +.. _RX140 MCU group Website: + https://www.renesas.com/en/products/rx140 + +.. _RSK_RX140 - User's Manual: + https://www.renesas.com/en/document/mat/renesas-starter-kit-rx140-users-manual + +.. _RX140 Group User's Manual Hardware: + https://www.renesas.com/en/document/mah/rx140-group-users-manual-hardware-rev120 + +.. _Renesas Debug extension: + https://marketplace.visualstudio.com/items?itemName=RenesasElectronicsCorporation.renesas-debug diff --git a/boards/renesas/rsk_rx140/doc/rsk_rx140.webp b/boards/renesas/rsk_rx140/doc/rsk_rx140.webp new file mode 100644 index 000000000000..38ec20beffd3 Binary files /dev/null and b/boards/renesas/rsk_rx140/doc/rsk_rx140.webp differ diff --git a/boards/renesas/rsk_rx140/rsk_rx140-pinctrl.dtsi b/boards/renesas/rsk_rx140/rsk_rx140-pinctrl.dtsi new file mode 100644 index 000000000000..748fcaded924 --- /dev/null +++ b/boards/renesas/rsk_rx140/rsk_rx140-pinctrl.dtsi @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci1_default: sci1_default { + group1 { + psels = , /* TX */ + ; /* RX */ + }; + }; + + adc_default: adc_default { + group1 { + /* input */ + psels = ; + renesas,analog-enable; + }; + }; + + rspi0_default: rspi0_default { + group1 { + psels = , + , + , + ; + }; + }; + + i2c0_default: i2c0_default { + group1 { + psels = , /* SDA P13*/ + ; /* SCL P12*/ + }; + }; + + pwm1_default: pwm1_default { + group1 { + psels = ; /* P20 MTIOC1A J2-PIN2*/ + }; + }; +}; diff --git a/boards/renesas/rsk_rx140/rsk_rx140.dts b/boards/renesas/rsk_rx140/rsk_rx140.dts new file mode 100644 index 000000000000..aa4af39c7f37 --- /dev/null +++ b/boards/renesas/rsk_rx140/rsk_rx140.dts @@ -0,0 +1,142 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include "rsk_rx140-pinctrl.dtsi" +#include +#include + +/ { + model = "Renesas RSK-RX140 KIT"; + compatible = "renesas,rsk_rx140"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &code_flash; + zephyr,flash-controller = &flash; + zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + }; + + leds { + compatible = "gpio-leds"; + + led1: led1 { + gpios = <&ioport0 4 GPIO_ACTIVE_LOW>; + label = "LED1"; + }; + + led3: led3 { + gpios = <&ioport0 7 GPIO_ACTIVE_LOW>; + label = "LED3"; + }; + }; + + buttons { + compatible = "gpio-keys"; + + sw1: button { + label = "sw1"; + gpios = <&ioport3 1 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + }; + }; + + aliases { + led0 = &led1; + led1 = &led3; + watchdog0 = &iwdt; + }; +}; + +&xtal { + clock-frequency = ; + mosel = <0>; + #clock-cells = <0>; + status = "okay"; +}; + +&subclk { + status = "okay"; +}; + +&pll { + status = "okay"; +}; + +&cmt { + clock-frequency = <3000000>; + status = "okay"; +}; + +&ioport0 { + status = "okay"; +}; + +&ioport3 { + status = "okay"; +}; + +&port_irq1 { + status = "okay"; +}; + +&mtu1 { + status = "okay"; + pinctrl-0 = <&pwm1_default>; + pinctrl-names = "default"; + + pwm1: pwm { + status = "okay"; + }; +}; + +&sci1 { + pinctrl-0 = <&sci1_default>; + pinctrl-names = "default"; + status = "okay"; + + uart1: uart { + current-speed = <115200>; + status = "okay"; + }; +}; + +&rspi0 { + pinctrl-0 = <&rspi0_default>; + pinctrl-names = "default"; + ssl-assert = <0>; + status = "okay"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + clock-frequency = ; + status = "okay"; +}; + +&data_flash { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + storage_partition: partition@0 { + label = "storage"; + reg = <0X0 DT_SIZE_K(8)>; + }; + }; +}; + +&iwdt { + window-start = <0x3000>; + window-end = <0x0300>; + status = "okay"; +}; diff --git a/boards/renesas/rsk_rx140/rsk_rx140.yaml b/boards/renesas/rsk_rx140/rsk_rx140.yaml new file mode 100644 index 000000000000..90f9b47ff69d --- /dev/null +++ b/boards/renesas/rsk_rx140/rsk_rx140.yaml @@ -0,0 +1,14 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +identifier: rsk_rx140 +name: Renesas Starter Kit for RX140 +type: mcu +arch: rx +toolchain: + - cross-compile +supported: + - gpio + - serial +ram: 64 +flash: 256 diff --git a/boards/renesas/rsk_rx140/rsk_rx140_defconfig b/boards/renesas/rsk_rx140/rsk_rx140_defconfig new file mode 100644 index 000000000000..c23cdd58f2a0 --- /dev/null +++ b/boards/renesas/rsk_rx140/rsk_rx140_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/renesas/rza2m_evk/rza2m_evk-pinctrl.dtsi b/boards/renesas/rza2m_evk/rza2m_evk-pinctrl.dtsi index 8d076ece20e3..014307309b77 100644 --- a/boards/renesas/rza2m_evk/rza2m_evk-pinctrl.dtsi +++ b/boards/renesas/rza2m_evk/rza2m_evk-pinctrl.dtsi @@ -13,4 +13,31 @@ ; /* RXD */ }; }; + + /omit-if-no-ref/ adc_default: adc_default { + adc-pinmux { + pinmux = ; /* AN006 */ + }; + }; + + /omit-if-no-ref/ gpt3_pins: gpt3 { + gpt3-pinmux { + pinmux = , /* GTIOCA */ + ; /* GTIOCB */ + }; + }; + + /omit-if-no-ref/ gpt5_pins: gpt5 { + gpt5-pinmux { + pinmux = , /* GTIOCA */ + ; /* GTIOCB */ + }; + }; + + /omit-if-no-ref/ i2c3_default: i2c3_default { + i2c3-pinmux { + pinmux = , /* RIIC3SCL */ + ; /* RIIC3SDA */ + }; + }; }; diff --git a/boards/renesas/rza2m_evk/rza2m_evk.dts b/boards/renesas/rza2m_evk/rza2m_evk.dts index cb38dae33c10..b987b40a6fd7 100644 --- a/boards/renesas/rza2m_evk/rza2m_evk.dts +++ b/boards/renesas/rza2m_evk/rza2m_evk.dts @@ -52,9 +52,9 @@ read-only; }; - slot0_partition: partition@E000 { + slot0_partition: partition@e000 { label = "image-0"; - reg = <0x0000E000 (DT_SIZE_M(64) - DT_SIZE_K(56))>; + reg = <0x0000e000 (DT_SIZE_M(64) - DT_SIZE_K(56))>; read-only; }; }; @@ -88,3 +88,15 @@ current-speed = <115200>; status = "okay"; }; + +&adc { + pinctrl-0 = <&adc_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2c3 { + pinctrl-0 = <&i2c3_default>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/boards/renesas/rza2m_evk/rza2m_evk.yaml b/boards/renesas/rza2m_evk/rza2m_evk.yaml index 402c81a73ef5..719b8a30df0a 100644 --- a/boards/renesas/rza2m_evk/rza2m_evk.yaml +++ b/boards/renesas/rza2m_evk/rza2m_evk.yaml @@ -6,6 +6,9 @@ toolchain: - zephyr - gnuarmemb supported: + - adc + - i2c - uart - gpio + - pwm vendor: renesas diff --git a/boards/renesas/rzg2l_smarc/rzg2l_smarc-pinctrl.dtsi b/boards/renesas/rzg2l_smarc/rzg2l_smarc-pinctrl.dtsi index 7990abe700e6..7c1899c43ac0 100644 --- a/boards/renesas/rzg2l_smarc/rzg2l_smarc-pinctrl.dtsi +++ b/boards/renesas/rzg2l_smarc/rzg2l_smarc-pinctrl.dtsi @@ -20,4 +20,16 @@ ; /* RXD */ }; }; + + /omit-if-no-ref/ gpt3_pins: gpt3 { + gpt3-pinmux { + pinmux = ; /* GTIOCB */ + }; + }; + + /omit-if-no-ref/ gpt6_pins: gpt6 { + gpt6-pinmux { + pinmux = ; /* GTIOCA */ + }; + }; }; diff --git a/boards/renesas/rzg2l_smarc/rzg2l_smarc_r9a07g044l23gbg_cm33.dts b/boards/renesas/rzg2l_smarc/rzg2l_smarc_r9a07g044l23gbg_cm33.dts index 7dc022ec4272..09195dc27cb5 100644 --- a/boards/renesas/rzg2l_smarc/rzg2l_smarc_r9a07g044l23gbg_cm33.dts +++ b/boards/renesas/rzg2l_smarc/rzg2l_smarc_r9a07g044l23gbg_cm33.dts @@ -32,3 +32,7 @@ pinctrl-names = "default"; status = "okay"; }; + +&adc { + status = "okay"; +}; diff --git a/boards/renesas/rzg2l_smarc/rzg2l_smarc_r9a07g044l23gbg_cm33.yaml b/boards/renesas/rzg2l_smarc/rzg2l_smarc_r9a07g044l23gbg_cm33.yaml index f2f11f6f5d8c..73f024bc9659 100644 --- a/boards/renesas/rzg2l_smarc/rzg2l_smarc_r9a07g044l23gbg_cm33.yaml +++ b/boards/renesas/rzg2l_smarc/rzg2l_smarc_r9a07g044l23gbg_cm33.yaml @@ -6,5 +6,7 @@ toolchain: - zephyr - gnuarmemb supported: + - adc - uart - gpio + - pwm diff --git a/boards/renesas/rzg2lc_smarc/rzg2lc_smarc-pinctrl.dtsi b/boards/renesas/rzg2lc_smarc/rzg2lc_smarc-pinctrl.dtsi index ecae377d2a40..654a749c30d8 100644 --- a/boards/renesas/rzg2lc_smarc/rzg2lc_smarc-pinctrl.dtsi +++ b/boards/renesas/rzg2lc_smarc/rzg2lc_smarc-pinctrl.dtsi @@ -20,4 +20,16 @@ ; /* RXD */ }; }; + + /omit-if-no-ref/ gpt6_pins: gpt6 { + gpt6-pinmux { + pinmux = ; /* GTIOCA */ + }; + }; + + /omit-if-no-ref/ gpt7_pins: gpt7 { + gpt7-pinmux { + pinmux = ; /* GTIOCB */ + }; + }; }; diff --git a/boards/renesas/rzg2lc_smarc/rzg2lc_smarc_r9a07g044c22gbg_cm33.yaml b/boards/renesas/rzg2lc_smarc/rzg2lc_smarc_r9a07g044c22gbg_cm33.yaml index 5d0aac9cdb14..cd6ea91be013 100644 --- a/boards/renesas/rzg2lc_smarc/rzg2lc_smarc_r9a07g044c22gbg_cm33.yaml +++ b/boards/renesas/rzg2lc_smarc/rzg2lc_smarc_r9a07g044c22gbg_cm33.yaml @@ -8,3 +8,4 @@ toolchain: supported: - uart - gpio + - pwm diff --git a/boards/renesas/rzg2ul_smarc/rzg2ul_smarc_r9a07g043u11gbg_cm33.dts b/boards/renesas/rzg2ul_smarc/rzg2ul_smarc_r9a07g043u11gbg_cm33.dts index 56d363e2fa54..07d86b7c82c3 100644 --- a/boards/renesas/rzg2ul_smarc/rzg2ul_smarc_r9a07g043u11gbg_cm33.dts +++ b/boards/renesas/rzg2ul_smarc/rzg2ul_smarc_r9a07g043u11gbg_cm33.dts @@ -23,3 +23,7 @@ reg = <0x60010000 DT_SIZE_M(46)>; }; }; + +&adc { + status = "okay"; +}; diff --git a/boards/renesas/rzg2ul_smarc/rzg2ul_smarc_r9a07g043u11gbg_cm33.yaml b/boards/renesas/rzg2ul_smarc/rzg2ul_smarc_r9a07g043u11gbg_cm33.yaml index c547a2c5385e..39af63f176a4 100644 --- a/boards/renesas/rzg2ul_smarc/rzg2ul_smarc_r9a07g043u11gbg_cm33.yaml +++ b/boards/renesas/rzg2ul_smarc/rzg2ul_smarc_r9a07g043u11gbg_cm33.yaml @@ -6,5 +6,6 @@ toolchain: - zephyr - gnuarmemb supported: + - adc - uart - gpio diff --git a/boards/renesas/rzn2l_rsk/rzn2l_rsk.dts b/boards/renesas/rzn2l_rsk/rzn2l_rsk.dts index c08c80df0903..f29fca88939b 100644 --- a/boards/renesas/rzn2l_rsk/rzn2l_rsk.dts +++ b/boards/renesas/rzn2l_rsk/rzn2l_rsk.dts @@ -103,7 +103,7 @@ }; &gpio16 { - irqs = <3 7>; + irqs = <&irq7 3>; status = "okay"; }; diff --git a/boards/renesas/rzt2l_rsk/rzt2l_rsk-pinctrl.dtsi b/boards/renesas/rzt2l_rsk/rzt2l_rsk-pinctrl.dtsi index 4f63c4a83678..da63daa0f7e9 100644 --- a/boards/renesas/rzt2l_rsk/rzt2l_rsk-pinctrl.dtsi +++ b/boards/renesas/rzt2l_rsk/rzt2l_rsk-pinctrl.dtsi @@ -20,4 +20,18 @@ input-enable; }; }; + + /omit-if-no-ref/ gpt5_pins: gpt5 { + gpt5-pinmux { + pinmux = , /* GTIOCA */ + ; /* GTIOCB */ + }; + }; + + /omit-if-no-ref/ gpt6_pins: gpt6 { + gpt6-pinmux { + pinmux = , /* GTIOCA */ + ; /* GTIOCB */ + }; + }; }; diff --git a/boards/renesas/rzt2l_rsk/rzt2l_rsk.dts b/boards/renesas/rzt2l_rsk/rzt2l_rsk.dts index 00fe010130d0..682fa5d42752 100644 --- a/boards/renesas/rzt2l_rsk/rzt2l_rsk.dts +++ b/boards/renesas/rzt2l_rsk/rzt2l_rsk.dts @@ -74,7 +74,7 @@ }; &gpio16 { - irqs = <3 7>; + irqs = <&irq7 3>; status = "okay"; }; @@ -92,3 +92,11 @@ pinctrl-names = "default"; status = "okay"; }; + +&adc0 { + status = "okay"; +}; + +&adc1 { + status = "okay"; +}; diff --git a/boards/renesas/rzt2l_rsk/rzt2l_rsk.yaml b/boards/renesas/rzt2l_rsk/rzt2l_rsk.yaml index 6bfd1397438c..ff82a45447ae 100644 --- a/boards/renesas/rzt2l_rsk/rzt2l_rsk.yaml +++ b/boards/renesas/rzt2l_rsk/rzt2l_rsk.yaml @@ -8,6 +8,8 @@ arch: arm toolchain: - zephyr supported: + - adc - uart - gpio + - pwm vendor: renesas diff --git a/boards/renesas/rzt2m_rsk/rzt2m_rsk_r9a07g075m24gbg_cr520.dts b/boards/renesas/rzt2m_rsk/rzt2m_rsk_r9a07g075m24gbg_cr520.dts index 6606eb199508..aac9b1e409a8 100644 --- a/boards/renesas/rzt2m_rsk/rzt2m_rsk_r9a07g075m24gbg_cr520.dts +++ b/boards/renesas/rzt2m_rsk/rzt2m_rsk_r9a07g075m24gbg_cr520.dts @@ -94,7 +94,7 @@ }; &gpio10 { - irqs = <5 2>; + irqs = <&irq2 5>; status = "okay"; }; diff --git a/boards/renesas/rzv2h_evk/rzv2h_evk-pinctrl.dtsi b/boards/renesas/rzv2h_evk/rzv2h_evk-pinctrl.dtsi index cb87c2794f5d..48c697400307 100644 --- a/boards/renesas/rzv2h_evk/rzv2h_evk-pinctrl.dtsi +++ b/boards/renesas/rzv2h_evk/rzv2h_evk-pinctrl.dtsi @@ -14,4 +14,18 @@ drive-strength = <1>; }; }; + + /omit-if-no-ref/ gpt3_pins: gpt3 { + gpt3-pinmux { + pinmux = , /* GTIOCA */ + ; /* GTIOCB */ + }; + }; + + /omit-if-no-ref/ gpt5_pins: gpt5 { + gpt5-pinmux { + pinmux = , /* GTIOCA */ + ; /* GTIOCB */ + }; + }; }; diff --git a/boards/renesas/rzv2h_evk/rzv2h_evk_r9a09g057h44gbg_cm33.dts b/boards/renesas/rzv2h_evk/rzv2h_evk_r9a09g057h44gbg_cm33.dts index e9714ad044ba..a3a287020d83 100644 --- a/boards/renesas/rzv2h_evk/rzv2h_evk_r9a09g057h44gbg_cm33.dts +++ b/boards/renesas/rzv2h_evk/rzv2h_evk_r9a09g057h44gbg_cm33.dts @@ -65,3 +65,7 @@ status = "okay"; }; }; + +&adc0 { + status = "okay"; +}; diff --git a/boards/renesas/rzv2h_evk/rzv2h_evk_r9a09g057h44gbg_cm33.yaml b/boards/renesas/rzv2h_evk/rzv2h_evk_r9a09g057h44gbg_cm33.yaml index 9e45f21aa046..837c9a246007 100644 --- a/boards/renesas/rzv2h_evk/rzv2h_evk_r9a09g057h44gbg_cm33.yaml +++ b/boards/renesas/rzv2h_evk/rzv2h_evk_r9a09g057h44gbg_cm33.yaml @@ -6,6 +6,8 @@ toolchain: - zephyr - gnuarmemb supported: + - adc - uart - gpio + - pwm vendor: renesas diff --git a/boards/renesas/rzv2h_evk/rzv2h_evk_r9a09g057h44gbg_cr8_0.dts b/boards/renesas/rzv2h_evk/rzv2h_evk_r9a09g057h44gbg_cr8_0.dts index 2c21be97b990..6fd6bd568f2b 100644 --- a/boards/renesas/rzv2h_evk/rzv2h_evk_r9a09g057h44gbg_cr8_0.dts +++ b/boards/renesas/rzv2h_evk/rzv2h_evk_r9a09g057h44gbg_cr8_0.dts @@ -58,3 +58,7 @@ status = "okay"; }; }; + +&adc0 { + status = "okay"; +}; diff --git a/boards/renesas/rzv2h_evk/rzv2h_evk_r9a09g057h44gbg_cr8_0.yaml b/boards/renesas/rzv2h_evk/rzv2h_evk_r9a09g057h44gbg_cr8_0.yaml index 1195932fbc85..a26d2d2c5a31 100644 --- a/boards/renesas/rzv2h_evk/rzv2h_evk_r9a09g057h44gbg_cr8_0.yaml +++ b/boards/renesas/rzv2h_evk/rzv2h_evk_r9a09g057h44gbg_cr8_0.yaml @@ -6,6 +6,8 @@ toolchain: - zephyr - gnuarmemb supported: + - adc - uart - gpio + - pwm vendor: renesas diff --git a/boards/renesas/rzv2n_evk/rzv2n_evk-pinctrl.dtsi b/boards/renesas/rzv2n_evk/rzv2n_evk-pinctrl.dtsi index bbd5d1f77b7a..be72aa0d485c 100644 --- a/boards/renesas/rzv2n_evk/rzv2n_evk-pinctrl.dtsi +++ b/boards/renesas/rzv2n_evk/rzv2n_evk-pinctrl.dtsi @@ -13,4 +13,18 @@ ; /* RXD */ }; }; + + /omit-if-no-ref/ gpt3_pins: gpt3 { + gpt3-pinmux { + pinmux = , /* GTIOCA */ + ; /* GTIOCB */ + }; + }; + + /omit-if-no-ref/ gpt5_pins: gpt5 { + gpt5-pinmux { + pinmux = , /* GTIOCA */ + ; /* GTIOCB */ + }; + }; }; diff --git a/boards/renesas/rzv2n_evk/rzv2n_evk_r9a09g056n48gbg_cm33.dts b/boards/renesas/rzv2n_evk/rzv2n_evk_r9a09g056n48gbg_cm33.dts index 9f560ddf782a..71bb12193c4f 100644 --- a/boards/renesas/rzv2n_evk/rzv2n_evk_r9a09g056n48gbg_cm33.dts +++ b/boards/renesas/rzv2n_evk/rzv2n_evk_r9a09g056n48gbg_cm33.dts @@ -69,3 +69,15 @@ &gpio0 { status = "okay"; }; + +&adc0 { + status = "okay"; +}; + +&adc1 { + status = "okay"; +}; + +&adc2 { + status = "okay"; +}; diff --git a/boards/renesas/rzv2n_evk/rzv2n_evk_r9a09g056n48gbg_cm33.yaml b/boards/renesas/rzv2n_evk/rzv2n_evk_r9a09g056n48gbg_cm33.yaml index 7bdedda75f7e..2b3c629947b0 100644 --- a/boards/renesas/rzv2n_evk/rzv2n_evk_r9a09g056n48gbg_cm33.yaml +++ b/boards/renesas/rzv2n_evk/rzv2n_evk_r9a09g056n48gbg_cm33.yaml @@ -6,6 +6,8 @@ toolchain: - zephyr - gnuarmemb supported: + - adc - uart - gpio + - pwm vendor: renesas diff --git a/boards/renesas/voice_ra4e1/voice_ra4e1.dts b/boards/renesas/voice_ra4e1/voice_ra4e1.dts index 5e616c0933aa..46a6de50b45a 100644 --- a/boards/renesas/voice_ra4e1/voice_ra4e1.dts +++ b/boards/renesas/voice_ra4e1/voice_ra4e1.dts @@ -121,7 +121,7 @@ storage_partition: partition@0 { label = "storage"; - reg = <0X0 DT_SIZE_K(8)>; + reg = <0x0 DT_SIZE_K(8)>; }; }; }; diff --git a/boards/ruiside/art_pi/art_pi.dts b/boards/ruiside/art_pi/art_pi.dts index bf5836571e86..c1ae16b23da4 100644 --- a/boards/ruiside/art_pi/art_pi.dts +++ b/boards/ruiside/art_pi/art_pi.dts @@ -30,7 +30,7 @@ sdram1: memory@c0000000 { compatible = "zephyr,memory-region", "mmio-sram"; device_type = "memory"; - reg = <0xC0000000 0x00600000>; /* Use 6 MB MAX 32MB */ + reg = <0xc0000000 0x00600000>; /* Use 6 MB MAX 32MB */ zephyr,memory-region = "SDRAM1"; zephyr,memory-attr = ; }; @@ -195,10 +195,10 @@ clocks = <&rcc STM32_CLOCK(APB3, 3)>, <&rcc STM32_SRC_PLL3_R NO_SEL>; width = <800>; height = <480>; - pixel-format = ; - def-back-color-red = <0X00>; - def-back-color-green = <0X00>; - def-back-color-blue = <0X00>; + pixel-format = ; + def-back-color-red = <0x00>; + def-back-color-green = <0x00>; + def-back-color-blue = <0x00>; display-timings { compatible = "zephyr,panel-timing"; @@ -352,7 +352,7 @@ zephyr_udc0: &usbotg_fs { status = "okay"; phy-connection-type = "rmii"; phy-handle = <ð_phy>; - local-mac-address = [00 80 E1 2A 75 01]; + local-mac-address = [00 80 e1 2a 75 01]; pinctrl-0 = <ð_ref_clk_pa1 ð_crs_dv_pa7 ð_rxd0_pc4 diff --git a/boards/ruiside/art_pi/doc/index.rst b/boards/ruiside/art_pi/doc/index.rst index 7a04a46d56c5..0339219d3daa 100644 --- a/boards/ruiside/art_pi/doc/index.rst +++ b/boards/ruiside/art_pi/doc/index.rst @@ -34,7 +34,7 @@ Hardware ART-Pi provides the following hardware components: The STM32H750xx devices are a high-performance microcontrollers family (STM32H7 -Series) based on the high-performance Arm |reg| Cortex |reg|-M7 32-bit RISC core. +Series) based on the high-performance Arm® Cortex®-M7 32-bit RISC core. They operate at a frequency of up to 480 MHz. More information about STM32H750xx can be found here: diff --git a/boards/ruiside/art_pi2/doc/index.rst b/boards/ruiside/art_pi2/doc/index.rst index 7dee5755e9be..afcaf0bf4913 100644 --- a/boards/ruiside/art_pi2/doc/index.rst +++ b/boards/ruiside/art_pi2/doc/index.rst @@ -33,7 +33,7 @@ Hardware ART-Pi2 provides the following hardware components: The STM32H7R7xx devices are a high-performance microcontrollers family (STM32H7 -Series) based on the high-performance Arm |reg| Cortex |reg|-M7 32-bit RISC core. +Series) based on the high-performance Arm® Cortex®-M7 32-bit RISC core. They operate at a frequency of up to 600 MHz. More information about STM32H7R7 can be found here: diff --git a/boards/ruiside/ra8d1_vision_board/ra8d1_vision_board.dts b/boards/ruiside/ra8d1_vision_board/ra8d1_vision_board.dts index f5323c0d154e..2c4079c6e9d0 100644 --- a/boards/ruiside/ra8d1_vision_board/ra8d1_vision_board.dts +++ b/boards/ruiside/ra8d1_vision_board/ra8d1_vision_board.dts @@ -165,7 +165,7 @@ storage_partition: partition@0 { label = "storage"; - reg = <0X0 DT_SIZE_K(12)>; + reg = <0x0 DT_SIZE_K(12)>; }; }; }; @@ -179,11 +179,11 @@ pinctrl-0 = <&sdram_default>; pinctrl-names = "default"; status = "okay"; - auto-refresh-interval = ; - auto-refresh-count = ; + auto-refresh-interval = ; + auto-refresh-count = ; precharge-cycle-count = ; multiplex-addr-shift = "9-bit"; - edian-mode = "little-endian"; + endian-mode = "little-endian"; continuous-access; bus-width = "16-bit"; diff --git a/boards/ruuvi/ruuvitag/ruuvi_ruuvitag.dts b/boards/ruuvi/ruuvitag/ruuvi_ruuvitag.dts index ef8188bc607c..c66c02e06ef9 100644 --- a/boards/ruuvi/ruuvitag/ruuvi_ruuvitag.dts +++ b/boards/ruuvi/ruuvitag/ruuvi_ruuvitag.dts @@ -119,12 +119,12 @@ slot0_partition: partition@c000 { label = "image-0"; - reg = <0x0000C000 0x32000>; + reg = <0x0000c000 0x32000>; }; slot1_partition: partition@3e000 { label = "image-1"; - reg = <0x0003E000 0x32000>; + reg = <0x0003e000 0x32000>; }; scratch_partition: partition@70000 { diff --git a/boards/sc/scobc_a1/board.cmake b/boards/sc/scobc_a1/board.cmake index da21e7505568..c0d5610d80f8 100644 --- a/boards/sc/scobc_a1/board.cmake +++ b/boards/sc/scobc_a1/board.cmake @@ -1,5 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -board_runner_args(openocd "--use-elf" "--config=${BOARD_DIR}/support/scobc-a1.cfg") +board_runner_args(openocd "--file-type=elf" "--config=${BOARD_DIR}/support/scobc-a1.cfg") include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/sc/scobc_v1/scobc_v1_versal_rpu.dts b/boards/sc/scobc_v1/scobc_v1_versal_rpu.dts index 55fa434618a4..7ccb050d5358 100644 --- a/boards/sc/scobc_v1/scobc_v1_versal_rpu.dts +++ b/boards/sc/scobc_v1/scobc_v1_versal_rpu.dts @@ -6,6 +6,7 @@ /dts-v1/; #include +#include / { model = "SC-OBC Module V1 Versal Cortex-R5F"; @@ -21,16 +22,10 @@ &uart1 { status = "okay"; current-speed = <115200>; - clock-frequency = <100000000>; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - clock-frequency = <100000000>; + clock-frequency = ; }; &ttc0 { status = "okay"; - clock-frequency = <150000000>; + clock-frequency = ; }; diff --git a/boards/seagate/faze/faze.dts b/boards/seagate/faze/faze.dts index b5bfc60c76bb..e55ee6ef5a0a 100644 --- a/boards/seagate/faze/faze.dts +++ b/boards/seagate/faze/faze.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include #include diff --git a/boards/seco/stm32f3_seco_d23/doc/index.rst b/boards/seco/stm32f3_seco_d23/doc/index.rst index 10517105ae74..e788586531f0 100644 --- a/boards/seco/stm32f3_seco_d23/doc/index.rst +++ b/boards/seco/stm32f3_seco_d23/doc/index.rst @@ -24,7 +24,7 @@ Hardware SECO SBC-3.5-PX30 provides the following hardware components: - STM32F302VCT6 - - ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU + - ARM® 32-bit Cortex®-M4 CPU with FPU - 256 KB Flash - 40 KB SRAM - 72 MHz max CPU frequency diff --git a/boards/seeed/wio_terminal/wio_terminal.dts b/boards/seeed/wio_terminal/wio_terminal.dts index d50411aee2ad..62ce11f0aaef 100644 --- a/boards/seeed/wio_terminal/wio_terminal.dts +++ b/boards/seeed/wio_terminal/wio_terminal.dts @@ -8,7 +8,7 @@ #include "wio_terminal-pinctrl.dtsi" #include "grove_connectors.dtsi" #include "raspberrypi_40pins_connector.dtsi" -#include +#include #include / { @@ -148,7 +148,7 @@ compatible = "ilitek,ili9341"; mipi-max-frequency = <24000000>; reg = <0>; - pixel-format = ; + pixel-format = ; rotation = <270>; width = <320>; height = <240>; diff --git a/boards/seeed/xiao_esp32c3/support/openocd.cfg b/boards/seeed/xiao_esp32c3/support/openocd.cfg index 7421637880c7..cf1bc91bbf9f 100644 --- a/boards/seeed/xiao_esp32c3/support/openocd.cfg +++ b/boards/seeed/xiao_esp32c3/support/openocd.cfg @@ -1,4 +1,4 @@ -set ESP_RTOS none +set ESP_RTOS Zephyr source [find interface/esp_usb_jtag.cfg] diff --git a/boards/seeed/xiao_esp32c6/support/openocd.cfg b/boards/seeed/xiao_esp32c6/support/openocd.cfg index d86a5517a4ca..29d5fac25c5a 100644 --- a/boards/seeed/xiao_esp32c6/support/openocd.cfg +++ b/boards/seeed/xiao_esp32c6/support/openocd.cfg @@ -1,4 +1,4 @@ # ESP32C6 has built-in JTAG interface over USB port in pins GPIO13/GPIO12 (D-/D+). -set ESP_RTOS none +set ESP_RTOS Zephyr source [find board/esp32c6-builtin.cfg] diff --git a/boards/seeed/xiao_esp32s3/support/openocd.cfg b/boards/seeed/xiao_esp32s3/support/openocd.cfg index 2f740b4a36ab..b45e13c53d01 100644 --- a/boards/seeed/xiao_esp32s3/support/openocd.cfg +++ b/boards/seeed/xiao_esp32s3/support/openocd.cfg @@ -1,5 +1,5 @@ -set ESP_RTOS none -set ESP32_ONLYCPU 1 +set ESP_RTOS Zephyr +set ESP_ONLYCPU 1 # Source the JTAG interface configuration file source [find interface/esp_usb_jtag.cfg] diff --git a/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu_sense.dts b/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu_sense.dts index 3e18fa58ac20..b7230df00e29 100644 --- a/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu_sense.dts +++ b/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu_sense.dts @@ -13,7 +13,7 @@ compatible = "seeed,xiao-esp32s3"; chosen { - zephyr,camera = &lcd_cam; + zephyr,camera = &lcd_cam_dvp; }; }; @@ -43,12 +43,14 @@ &lcd_cam { status = "okay"; - cam-clk = <10000000>; pinctrl-0 = <&lcd_cam_default>; pinctrl-names = "default"; +}; + +&lcd_cam_dvp { + status = "okay"; + cam-clk = <10000000>; source = <&ov2640>; - dmas = <&dma 2>; - dma-names = "rx"; port { dvp_ep_in: endpoint { @@ -71,6 +73,7 @@ disk-name = "SD"; status = "okay"; }; + spi-max-frequency = <20000000>; }; }; diff --git a/boards/seeed/xiao_mg24/xiao_mg24.dts b/boards/seeed/xiao_mg24/xiao_mg24.dts index 0cf0e6cd0aa6..233a28e0d3ea 100644 --- a/boards/seeed/xiao_mg24/xiao_mg24.dts +++ b/boards/seeed/xiao_mg24/xiao_mg24.dts @@ -292,13 +292,13 @@ /* Reserve 736 kB for the application in slot 0 */ slot0_partition: partition@c000 { - reg = <0x0000c000 0x000B8000>; + reg = <0x0000c000 0x000b8000>; label = "image-0"; }; /* Reserve 736 kB for the application in slot 1 */ - slot1_partition: partition@C4000 { - reg = <0x000C4000 0x000B8000>; + slot1_partition: partition@c4000 { + reg = <0x000c4000 0x000b8000>; label = "image-1"; }; diff --git a/boards/seeed/xiao_nrf54l15/doc/index.rst b/boards/seeed/xiao_nrf54l15/doc/index.rst index 960b210d772a..8d680e0b487a 100644 --- a/boards/seeed/xiao_nrf54l15/doc/index.rst +++ b/boards/seeed/xiao_nrf54l15/doc/index.rst @@ -94,7 +94,7 @@ Reset the board and you should see the following message in the terminal: https://www.seeedstudio.com/XIAO-nRF54L15-Sense-p-6494 .. _XIAO nRF54L15 Wiki: - https://wiki.seeedstudio.com/getting_started_with_xiao_nrf54l15/ + https://wiki.seeedstudio.com/xiao_nrf54l15_sense_getting_started .. _nRF54L15 Website: https://www.nordicsemi.com/Products/nRF54L15 diff --git a/boards/seeed/xiao_nrf54l15/seeed_xiao_connector.dtsi b/boards/seeed/xiao_nrf54l15/seeed_xiao_connector.dtsi index 220e1d57f32a..f505ce0f1e9d 100644 --- a/boards/seeed/xiao_nrf54l15/seeed_xiao_connector.dtsi +++ b/boards/seeed/xiao_nrf54l15/seeed_xiao_connector.dtsi @@ -18,7 +18,12 @@ <7 0 &gpio2 7 0>, /* D7 */ <8 0 &gpio2 1 0>, /* D8 */ <9 0 &gpio2 4 0>, /* D9 */ - <10 0 &gpio2 2 0>; /* D10 */ + <10 0 &gpio2 2 0>, /* D10 */ + <11 0 &gpio0 3 0>, /* D11 */ + <12 0 &gpio0 4 0>, /* D12 */ + <13 0 &gpio2 10 0>, /* D13 */ + <14 0 &gpio2 9 0>, /* D14 */ + <15 0 &gpio2 6 0>; /* D15 */ }; }; diff --git a/boards/seeed/xiao_nrf54l15/support/openocd.cfg b/boards/seeed/xiao_nrf54l15/support/openocd.cfg index 82f6bb5f25bb..8ec6b496f65a 100644 --- a/boards/seeed/xiao_nrf54l15/support/openocd.cfg +++ b/boards/seeed/xiao_nrf54l15/support/openocd.cfg @@ -66,4 +66,117 @@ if {![using_hla]} { proc nrf54l-load {file} { mww 0x5004b500 0x101 load_image $file -} \ No newline at end of file +} + +# Define CTRL_AP_NUM explicitly to avoid variable errors +set CTRL_AP_NUM 2 + +# Custom _nrf_check_ap_lock for nRF54L (adjusted unlocked_value to 1, based on PyOCD's CSW check) +proc _nrf_check_ap_lock { ctrl_ap_num unlocked_value } { + set target [target current] + set dap [$target cget -dap] + set err [catch {set APPROTECTSTATUS [$dap apreg $ctrl_ap_num 0xc]}] ;# 0xc is ERASEPROTECTSTATUS register + if {$err == 0 && $APPROTECTSTATUS < $unlocked_value} { + echo "\[$target\] device has AP lock engaged, trying recover." + poll off + return 1 + } + return 0 +} + +# Custom _nrf_ctrl_ap_recover for nRF54L (adjusted IDR to 0x32880000) +proc _nrf_ctrl_ap_recover { ctrl_ap_num {is_cpunet 0} } { + set target [target current] + set dap [$target cget -dap] + + set IDR [$dap apreg $ctrl_ap_num 0xfc] + if {$IDR != 0x32880000} { ;# IDR for nRF54L CTRL-AP + echo "Error: Cannot access nRF54L CTRL-AP! (IDR: 0x$IDR)" + return + } + + poll off + + # Reset and trigger ERASEALL task + $dap apreg $ctrl_ap_num 4 0 ;# CTRL_AP_ERASEALL = 0x004 + $dap apreg $ctrl_ap_num 4 1 + + # First, wait for BUSY state + set timeout 300 ;# ~30s + for {set i 0} {$i < $timeout} {incr i} { + set ERASEALLSTATUS [$dap apreg $ctrl_ap_num 8] + if {$ERASEALLSTATUS == 2} { ;# BUSY status + break + } + if {$ERASEALLSTATUS == 3} { ;# ERROR status + echo "Error: Erase failed with ERROR status." + return + } + sleep 100 + } + if {$i >= $timeout} { + echo "Error: Timeout waiting for BUSY status." + return + } + + # Then, wait for READYTORESET state + for {set i 0} {$i < $timeout} {incr i} { + set ERASEALLSTATUS [$dap apreg $ctrl_ap_num 8] + if {$ERASEALLSTATUS == 1} { ;# READYTORESET status + echo "\[$target\] device has been successfully erased and unlocked." + break + } + if {$ERASEALLSTATUS == 3} { ;# ERROR status + echo "Error: Erase failed with ERROR status." + break + } + sleep 100 + } + if {$i >= $timeout} { + echo "Error: Timeout waiting for READYTORESET status." + return + } + + # Short delay before reset + sleep 10 + + # Assert reset: write 2 then 0 + $dap apreg $ctrl_ap_num 0 2 ;# CTRL_AP_RESET = 0x000 + sleep 10 + $dap apreg $ctrl_ap_num 0 0 + + # Reset ERASEALL task + $dap apreg $ctrl_ap_num 4 0 + + if { $is_cpunet } { + reset init + } else { + sleep 200 ;# Slightly increased delay + $target arp_examine + poll on + } +} + +lappend _telnet_autocomplete_skip _nrf_check_ap_lock _nrf_ctrl_ap_recover + +if { ![using_hla] } { + # Check AP lock on examine-fail and auto-recover if locked + $_TARGETNAME configure -event examine-fail { + global CTRL_AP_NUM + set target [target current] + if { [_nrf_check_ap_lock $CTRL_AP_NUM 1] } { + nrf54l_mass_erase + $target arp_examine ;# Re-examine after recover + } + } + + # Mass erase and unlock the device using proprietary nRF CTRL-AP (AP #2) + proc nrf54l_mass_erase {} { + global CTRL_AP_NUM + _nrf_ctrl_ap_recover $CTRL_AP_NUM ;# No cpunet for nRF54L + } + add_help_text nrf54l_mass_erase "Mass erase flash and unlock nRF54L device" +} + +flash bank $_CHIPNAME.flash nrf5 0x00000000 0x0017D000 0 0 $_TARGETNAME +# flash bank $_CHIPNAME.uicr nrf5 0x00FFD000 0 0 0 $_TARGETNAME diff --git a/boards/seeed/xiao_nrf54l15/xiao_nrf54l15_nrf54l15_cpuapp.dts b/boards/seeed/xiao_nrf54l15/xiao_nrf54l15_nrf54l15_cpuapp.dts index 039872381e52..eadd1a478964 100644 --- a/boards/seeed/xiao_nrf54l15/xiao_nrf54l15_nrf54l15_cpuapp.dts +++ b/boards/seeed/xiao_nrf54l15/xiao_nrf54l15_nrf54l15_cpuapp.dts @@ -1,4 +1,5 @@ /* + * Copyright (c) 2025 Seeed Technology Co., Ltd. * SPDX-License-Identifier: Apache-2.0 */ @@ -44,13 +45,15 @@ zephyr,code-partition = &slot0_partition; zephyr,sram = &cpuapp_sram; zephyr,flash = &cpuapp_rram; + zephyr,flash-controller = &rram_controller; zephyr,console = &uart20; zephyr,shell-uart = &uart20; nordic,rpc-uart = &uart20; + zephyr,ieee802154 = &ieee802154; }; aliases { - imu0 = &lsm6dso; + imu0 = &lsm6ds3tr_c; }; }; @@ -84,12 +87,10 @@ &i2c30 { status = "okay"; - lsm6dso: lsm6dso@6a { - compatible = "st,lsm6dso"; + lsm6ds3tr_c: lsm6ds3tr-c@6a { + compatible = "st,lsm6dsl"; reg = <0x6a>; irq-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; - accel-pm = ; - gyro-pm = ; status = "okay"; }; }; @@ -147,5 +148,31 @@ dmic_dev: &pdm20 { status = "okay"; }; +&hfxo { + load-capacitors = "internal"; + load-capacitance-femtofarad = <16000>; + status = "okay"; +}; + +&ieee802154 { + status = "okay"; +}; + +&temp { + status = "okay"; +}; + +&radio { + status = "okay"; +}; + +&nfct { + status = "okay"; +}; + +&clock { + status = "okay"; +}; + /* Include default memory partition configuration file */ -#include +#include diff --git a/boards/seeed/xiao_nrf54l15/xiao_nrf54l15_nrf54l15_cpuflpr.dts b/boards/seeed/xiao_nrf54l15/xiao_nrf54l15_nrf54l15_cpuflpr.dts index 42d316aaa485..20a7b22e46c0 100644 --- a/boards/seeed/xiao_nrf54l15/xiao_nrf54l15_nrf54l15_cpuflpr.dts +++ b/boards/seeed/xiao_nrf54l15/xiao_nrf54l15_nrf54l15_cpuflpr.dts @@ -31,6 +31,7 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + ranges; cpuflpr_code_partition: partition@0 { label = "image-0"; diff --git a/boards/seeed/xiao_rp2040/xiao_rp2040.dts b/boards/seeed/xiao_rp2040/xiao_rp2040.dts index 263da6f5f147..bf4cb37cd33e 100644 --- a/boards/seeed/xiao_rp2040/xiao_rp2040.dts +++ b/boards/seeed/xiao_rp2040/xiao_rp2040.dts @@ -74,11 +74,13 @@ * 2MB of flash minus the 0x100 used for the second stage bootloader */ reg = <0x10000000 DT_SIZE_M(2)>; + ranges = <0x0 0x10000000 DT_SIZE_M(2)>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + ranges; /* Reserved memory for the second stage bootloader */ second_stage_bootloader: partition@0 { diff --git a/boards/segger/ip_k66f/ip_k66f.dts b/boards/segger/ip_k66f/ip_k66f.dts index 15fbb62d1911..1fa65fa425a9 100644 --- a/boards/segger/ip_k66f/ip_k66f.dts +++ b/boards/segger/ip_k66f/ip_k66f.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "ip_k66f-pinctrl.dtsi" diff --git a/boards/segger/trb_stm32f407/segger_trb_stm32f407.dts b/boards/segger/trb_stm32f407/segger_trb_stm32f407.dts index 505a154f44f1..6779c3f868ba 100644 --- a/boards/segger/trb_stm32f407/segger_trb_stm32f407.dts +++ b/boards/segger/trb_stm32f407/segger_trb_stm32f407.dts @@ -14,7 +14,7 @@ chosen { zephyr,sram = &sram0; zephyr,flash = &flash0; - zephyr,ccm = &ccm0; + zephyr,dtcm = &ccm0; }; aliases { diff --git a/boards/shields/abrobot_esp32c3_oled/abrobot_sh1106_72x40.overlay b/boards/shields/abrobot_esp32c3_oled/abrobot_sh1106_72x40.overlay index 7160e706c87f..109befad278f 100644 --- a/boards/shields/abrobot_esp32c3_oled/abrobot_sh1106_72x40.overlay +++ b/boards/shields/abrobot_esp32c3_oled/abrobot_sh1106_72x40.overlay @@ -23,7 +23,7 @@ height = <40>; segment-offset = <30>; page-offset = <0>; - display-offset = <0xC>; + display-offset = <0xc>; multiplex-ratio = <0x27>; prechargep = <0x22>; ready-time-ms = <10>; diff --git a/boards/shields/adafruit_2_8_tft_touch_v2/boards/rd_rw612_bga.overlay b/boards/shields/adafruit_2_8_tft_touch_v2/boards/rd_rw612_bga.overlay index 9a6ed1d8541d..95de85a08658 100644 --- a/boards/shields/adafruit_2_8_tft_touch_v2/boards/rd_rw612_bga.overlay +++ b/boards/shields/adafruit_2_8_tft_touch_v2/boards/rd_rw612_bga.overlay @@ -5,6 +5,7 @@ */ #include +#include / { chosen { @@ -44,7 +45,7 @@ reg = <0>; width = <320>; height = <240>; - pixel-format = ; + pixel-format = ; rotation = <90>; frmctr1 = [00 18]; pwctrl1 = [23 00]; diff --git a/boards/shields/adafruit_2_8_tft_touch_v2/dts/adafruit_2_8_tft_touch_v2.dtsi b/boards/shields/adafruit_2_8_tft_touch_v2/dts/adafruit_2_8_tft_touch_v2.dtsi index 7eca206f6a02..5868c02118df 100644 --- a/boards/shields/adafruit_2_8_tft_touch_v2/dts/adafruit_2_8_tft_touch_v2.dtsi +++ b/boards/shields/adafruit_2_8_tft_touch_v2/dts/adafruit_2_8_tft_touch_v2.dtsi @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include #include / { @@ -27,7 +27,7 @@ reg = <0>; width = <320>; height = <240>; - pixel-format = ; + pixel-format = ; rotation = <90>; frmctr1 = [00 18]; pwctrl1 = [23 00]; diff --git a/boards/shields/adafruit_featherwing_128x32_oled/adafruit_featherwing_128x32_oled.overlay b/boards/shields/adafruit_featherwing_128x32_oled/adafruit_featherwing_128x32_oled.overlay index 585d214847ea..6e90dd042d6b 100644 --- a/boards/shields/adafruit_featherwing_128x32_oled/adafruit_featherwing_128x32_oled.overlay +++ b/boards/shields/adafruit_featherwing_128x32_oled/adafruit_featherwing_128x32_oled.overlay @@ -39,7 +39,7 @@ &feather_i2c { ssd1306_ssd1306_128x32: ssd1306@3c { - compatible = "solomon,ssd1306fb"; + compatible = "solomon,ssd1306"; reg = <0x3c>; width = <128>; height = <32>; diff --git a/boards/shields/adafruit_hts221/Kconfig.shield b/boards/shields/adafruit_hts221/Kconfig.shield new file mode 100644 index 000000000000..f7f427c5ca98 --- /dev/null +++ b/boards/shields/adafruit_hts221/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright (c) 2026 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_ADAFRUIT_HTS221 + def_bool $(shields_list_contains,adafruit_hts221) diff --git a/boards/shields/adafruit_hts221/adafruit_hts221.overlay b/boards/shields/adafruit_hts221/adafruit_hts221.overlay new file mode 100644 index 000000000000..8a244d3c10a9 --- /dev/null +++ b/boards/shields/adafruit_hts221/adafruit_hts221.overlay @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2026 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + dht0 = &adafruit_hts221; + }; +}; + +&zephyr_i2c { + status = "okay"; + + adafruit_hts221: hts221@5f { + status = "okay"; + compatible = "st,hts221"; + reg = <0x5f>; + }; +}; diff --git a/boards/shields/adafruit_hts221/doc/adafruit_hts221.webp b/boards/shields/adafruit_hts221/doc/adafruit_hts221.webp new file mode 100644 index 000000000000..c39662fc629e Binary files /dev/null and b/boards/shields/adafruit_hts221/doc/adafruit_hts221.webp differ diff --git a/boards/shields/adafruit_hts221/doc/index.rst b/boards/shields/adafruit_hts221/doc/index.rst new file mode 100644 index 000000000000..0f6ecb2d0aa7 --- /dev/null +++ b/boards/shields/adafruit_hts221/doc/index.rst @@ -0,0 +1,63 @@ +.. _adafruit_hts221: + +Adafruit HTS221 Shield +###################### + +Overview +******** + +The `Adafruit HTS221 Temperature and Humidity Sensor Shield`_ features +a `ST Microelectronics HTS221 Humidity and Temperature Sensor`_ and two STEMMA QT connectors. +It measures temperature and humidity. + +.. figure:: adafruit_hts221.webp + :align: center + :alt: Adafruit HTS221 Shield + + Adafruit HTS221 Shield (Credit: Adafruit) + + +Requirements +************ + +This shield can be used with boards which provide an I2C connector, for example STEMMA QT or +Qwiic connectors. The target board must define a ``zephyr_i2c`` node label. +See :ref:`shields` for more details. + + +Pin Assignments +=============== + ++--------------+------------------------------------+ +| Shield Pin | Function | ++==============+====================================+ +| SDA | I2C SDA | ++--------------+------------------------------------+ +| SCL | I2C SCL | ++--------------+------------------------------------+ +| DRDY | Data ready output | ++--------------+------------------------------------+ +| CS | Keep at high level to use I2C mode | ++--------------+------------------------------------+ + +See :dtcompatible:`st,hts221` for details on possible devicetree settings, for example if you +are using the DRDY pin. + + +Programming +*********** + +Set ``--shield adafruit_hts221`` when you invoke ``west build``. For example +when running the :zephyr:code-sample:`dht_polling` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/sensor/dht_polling + :board: adafruit_feather_scorpio_rp2040 + :shield: adafruit_hts221 + :goals: build flash + +.. _Adafruit HTS221 Temperature and Humidity Sensor Shield: + https://learn.adafruit.com/adafruit-hts221-temperature-humidity-sensor + +.. _ST Microelectronics HTS221 Humidity and Temperature Sensor: + https://www.st.com/resource/en/datasheet/hts221.pdf diff --git a/boards/shields/adafruit_hts221/shield.yml b/boards/shields/adafruit_hts221/shield.yml new file mode 100644 index 000000000000..546ffd6f5b1f --- /dev/null +++ b/boards/shields/adafruit_hts221/shield.yml @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2026, Jonas Berg + +shield: + name: adafruit_hts221 + full_name: Adafruit HTS221 Temperature and Humidity Sensor Shield + vendor: adafruit + supported_features: + - sensor diff --git a/boards/shields/adafruit_ina3221/Kconfig.shield b/boards/shields/adafruit_ina3221/Kconfig.shield new file mode 100644 index 000000000000..a659be9823fa --- /dev/null +++ b/boards/shields/adafruit_ina3221/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright (c) 2026 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_ADAFRUIT_INA3221 + def_bool $(shields_list_contains,adafruit_ina3221) diff --git a/boards/shields/adafruit_ina3221/adafruit_ina3221.overlay b/boards/shields/adafruit_ina3221/adafruit_ina3221.overlay new file mode 100644 index 000000000000..05084ccca456 --- /dev/null +++ b/boards/shields/adafruit_ina3221/adafruit_ina3221.overlay @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2026 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&zephyr_i2c { + status = "okay"; + + adafruit_ina3221: ina3221@40 { + status = "okay"; + compatible = "ti,ina3221"; + reg = <0x40>; + shunt-resistors = <50>, <50>, <50>; + }; +}; diff --git a/boards/shields/adafruit_ina3221/doc/adafruit_ina3221.webp b/boards/shields/adafruit_ina3221/doc/adafruit_ina3221.webp new file mode 100644 index 000000000000..029fdf94214f Binary files /dev/null and b/boards/shields/adafruit_ina3221/doc/adafruit_ina3221.webp differ diff --git a/boards/shields/adafruit_ina3221/doc/index.rst b/boards/shields/adafruit_ina3221/doc/index.rst new file mode 100644 index 000000000000..2cf030f79ab3 --- /dev/null +++ b/boards/shields/adafruit_ina3221/doc/index.rst @@ -0,0 +1,99 @@ +.. _adafruit_ina3221: + +Adafruit INA3221 Shield +####################### + + +Overview +******** + +The `Adafruit INA3221 Triple Power Monitor Shield`_ features +a `TI INA3221 current sensor`_ and two STEMMA QT connectors. +It measures current and bus voltage on three channels. + +.. figure:: adafruit_ina3221.webp + :align: center + :alt: Adafruit INA3221 Shield + + Adafruit INA3221 Shield (Credit: Adafruit) + + +Requirements +************ + +This shield can be used with boards which provide an I2C connector, for example STEMMA QT +or Qwiic connectors. The target board must define a ``zephyr_i2c`` node label. +See :ref:`shields` for more details. + + +Pin Assignments +=============== + ++--------------+-------------------------------+ +| Shield Pin | Function | ++==============+===============================+ +| SCL | I2C SCL | ++--------------+-------------------------------+ +| SDA | I2C SDA | ++--------------+-------------------------------+ +| VIN3+ | Current sense pos, channel 3 | ++--------------+-------------------------------+ +| VIN3- | Current sense neg, channel 3 | ++--------------+-------------------------------+ +| VIN2+ | Current sense pos, channel 2 | ++--------------+-------------------------------+ +| VIN2- | Current sense neg, channel 2 | ++--------------+-------------------------------+ +| VIN1+ | Current sense pos, channel 1 | ++--------------+-------------------------------+ +| VIN1- | Current sense neg, channel 1 | ++--------------+-------------------------------+ +| WRN | Interrupt for current level | ++--------------+-------------------------------+ +| CRI | Interrupt for overcurrent | ++--------------+-------------------------------+ +| TC | Interrupt for timing control | ++--------------+-------------------------------+ +| VALID | Interrupt for power valid | ++--------------+-------------------------------+ +| VPU | Pull up voltage for VALID pin | ++--------------+-------------------------------+ + +See :dtcompatible:`ti,ina3221` for documentation on how to adjust the +devicetree file, for example to adjust the sample averaging. + + +Programming +*********** + +Set ``--shield adafruit_ina3221`` when you invoke ``west build``. For example +when running the :zephyr:code-sample:`sensor_shell` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/sensor/sensor_shell + :board: adafruit_feather_canbus_rp2040 + :shield: adafruit_ina3221 + :goals: build flash + +Use the shell command to show voltage, current and power on channel 1. This example has a +voltage and current of approximately 5 Volt and 3 mA, respectively: + +.. code-block:: console + + uart:~$ sensor get ina3221@40 + channel type=33(voltage) index=0 shift=3 num_samples=1 value=63920453436ns (5.079999) + channel type=35(current) index=0 shift=3 num_samples=1 value=63920453436ns (0.003199) + channel type=36(power) index=0 shift=3 num_samples=1 value=63920453436ns (0.016255) + +Use this command to select channel 2 instead of channel 1: + +.. code-block:: console + + uart:~$ sensor attr_set ina3221@40 voltage 19 2 + + +.. _Adafruit INA3221 Triple Power Monitor Shield: + https://learn.adafruit.com/adafruit-ina3221-breakout + +.. _TI INA3221 Current sensor: + https://www.ti.com/product/INA3221 diff --git a/boards/shields/adafruit_ina3221/shield.yml b/boards/shields/adafruit_ina3221/shield.yml new file mode 100644 index 000000000000..f148a3562108 --- /dev/null +++ b/boards/shields/adafruit_ina3221/shield.yml @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2026, Jonas Berg + +shield: + name: adafruit_ina3221 + full_name: Adafruit INA3221 Triple Power Monitor Shield + vendor: adafruit + supported_features: + - sensor diff --git a/boards/shields/adafruit_max17048/Kconfig.shield b/boards/shields/adafruit_max17048/Kconfig.shield new file mode 100644 index 000000000000..66940330fa57 --- /dev/null +++ b/boards/shields/adafruit_max17048/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright (c) 2026 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_ADAFRUIT_MAX17048 + def_bool $(shields_list_contains,adafruit_max17048) diff --git a/boards/shields/adafruit_max17048/adafruit_max17048.overlay b/boards/shields/adafruit_max17048/adafruit_max17048.overlay new file mode 100644 index 000000000000..a90cb7e6b0ef --- /dev/null +++ b/boards/shields/adafruit_max17048/adafruit_max17048.overlay @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2026 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + fuel-gauge0 = &adafruit_max17048; + }; +}; + +&zephyr_i2c { + status = "okay"; + + adafruit_max17048: max17048@36 { + status = "okay"; + compatible = "maxim,max17048"; + reg = <0x36>; + }; +}; diff --git a/boards/shields/adafruit_max17048/doc/adafruit_max17048.webp b/boards/shields/adafruit_max17048/doc/adafruit_max17048.webp new file mode 100644 index 000000000000..4fdf824af804 Binary files /dev/null and b/boards/shields/adafruit_max17048/doc/adafruit_max17048.webp differ diff --git a/boards/shields/adafruit_max17048/doc/index.rst b/boards/shields/adafruit_max17048/doc/index.rst new file mode 100644 index 000000000000..48f2203d2afd --- /dev/null +++ b/boards/shields/adafruit_max17048/doc/index.rst @@ -0,0 +1,63 @@ +.. _adafruit_max17048: + +Adafruit MAX17048 Shield +######################## + + +Overview +******** + +The `Adafruit MAX17048 Fuel Gauge Shield`_ features +an `Analog Devices MAX17048 Fuel Gauge`_ and two STEMMA QT connectors. +It measures voltage and state-of-charge of a lithium ion or lithium polymer cell. + +.. figure:: adafruit_max17048.webp + :align: center + :alt: Adafruit MAX17048 Shield + + Adafruit MAX17048 Shield (Credit: Adafruit) + + +Requirements +************ + +This shield can be used with boards which provide an I2C connector, for example STEMMA QT +or Qwiic connectors. The target board must define a ``zephyr_i2c`` node label. +See :ref:`shields` for more details. + + +Pin Assignments +=============== + ++--------------+-------------------------------+ +| Shield Pin | Function | ++==============+===============================+ +| SCL | I2C SCL | ++--------------+-------------------------------+ +| SDA | I2C SDA | ++--------------+-------------------------------+ +| INT | Interrupt output | ++--------------+-------------------------------+ +| QStart | Quick-start reset input | ++--------------+-------------------------------+ + +See :dtcompatible:`maxim,max17048` for documentation on how to adjust the devicetree file. + + +Programming +*********** + +Set ``--shield adafruit_max17048`` when you invoke ``west build``. For example when running +the :zephyr:code-sample:`fuel_gauge` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/drivers/fuel_gauge + :board: adafruit_feather_canbus_rp2040 + :shield: adafruit_max17048 + :goals: build flash + +.. _Adafruit MAX17048 Fuel Gauge Shield: + https://learn.adafruit.com/adafruit-max17048-lipoly-liion-fuel-gauge-and-battery-monitor + +.. _Analog Devices MAX17048 Fuel Gauge: + https://www.analog.com/en/products/max17048.html diff --git a/boards/shields/adafruit_max17048/shield.yml b/boards/shields/adafruit_max17048/shield.yml new file mode 100644 index 000000000000..143e6a907ae5 --- /dev/null +++ b/boards/shields/adafruit_max17048/shield.yml @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2026, Jonas Berg + +shield: + name: adafruit_max17048 + full_name: Adafruit MAX17048 Fuel Gauge Shield + vendor: adafruit + supported_features: + - fuel-gauge diff --git a/boards/shields/arduino_giga_display_shield/arduino_giga_display_shield.overlay b/boards/shields/arduino_giga_display_shield/arduino_giga_display_shield.overlay index 5da125332dbd..0c74cc361b8d 100644 --- a/boards/shields/arduino_giga_display_shield/arduino_giga_display_shield.overlay +++ b/boards/shields/arduino_giga_display_shield/arduino_giga_display_shield.overlay @@ -14,21 +14,21 @@ data-lanes = <2>; pixel-format = ; rotation = <0>; - gip-e0 = [E0 00 00 02]; - gip-e1 = [E1 08 00 0A 00 07 00 09 00 00 33 33]; - gip-e2 = [E2 00 00 00 00 00 00 00 00 00 00 00 00 00]; - gip-e3 = [E3 00 00 33 33]; - gip-e4 = [E4 44 44]; - gip-e5 = [E5 0E 60 A0 A0 10 60 A0 A0 0A 60 A0 A0 0C 60 A0 A0]; - gip-e6 = [E6 00 00 33 33]; - gip-e7 = [E7 44 44]; - gip-e8 = [E8 0D 60 A0 A0 0F 60 A0 A0 09 60 A0 A0 0B 60 A0 A0]; - gip-eb = [EB 02 01 E4 E4 44 00 40]; - gip-ec = [EC 02 01]; - gip-ed = [ED AB 89 76 54 01 FF FF FF FF FF FF 10 45 67 98 BA]; - gip-ed = [ED AB 89 76 54 01 FF FF FF FF FF FF 10 45 67 98 BA]; - pvgamctrl = [B0 40 C9 91 0D 12 07 02 09 09 1F 04 50 0F E4 29 DF]; - nvgamctrl = [B1 40 CB D0 11 92 07 00 08 07 1C 06 53 12 63 EB DF]; + gip-e0 = [e0 00 00 02]; + gip-e1 = [e1 08 00 0a 00 07 00 09 00 00 33 33]; + gip-e2 = [e2 00 00 00 00 00 00 00 00 00 00 00 00 00]; + gip-e3 = [e3 00 00 33 33]; + gip-e4 = [e4 44 44]; + gip-e5 = [e5 0e 60 a0 a0 10 60 a0 a0 0a 60 a0 a0 0c 60 a0 a0]; + gip-e6 = [e6 00 00 33 33]; + gip-e7 = [e7 44 44]; + gip-e8 = [e8 0d 60 a0 a0 0f 60 a0 a0 09 60 a0 a0 0b 60 a0 a0]; + gip-eb = [eb 02 01 e4 e4 44 00 40]; + gip-ec = [ec 02 01]; + gip-ed = [ed ab 89 76 54 01 ff ff ff ff ff ff 10 45 67 98 ba]; + gip-ed = [ed ab 89 76 54 01 ff ff ff ff ff ff 10 45 67 98 ba]; + pvgamctrl = [b0 40 c9 91 0d 12 07 02 09 09 1f 04 50 0f e4 29 df]; + nvgamctrl = [b1 40 cb d0 11 92 07 00 08 07 1c 06 53 12 63 eb df]; display-timings { compatible = "zephyr,panel-timing"; diff --git a/boards/shields/arduino_giga_display_shield/boards/arduino_giga_r1_m7.overlay b/boards/shields/arduino_giga_display_shield/boards/arduino_giga_r1_m7.overlay index 6ad74c37e098..6c074cbee9f3 100644 --- a/boards/shields/arduino_giga_display_shield/boards/arduino_giga_r1_m7.overlay +++ b/boards/shields/arduino_giga_display_shield/boards/arduino_giga_r1_m7.overlay @@ -17,11 +17,6 @@ }; }; -&sdram1 { - /* Frame buffer memory cache will cause screen flickering. */ - zephyr,memory-attr = ; -}; - &zephyr_lcd_controller { status = "okay"; ext-sdram = <&sdram1>; @@ -30,7 +25,7 @@ def-back-color-red = <0>; def-back-color-green = <0>; def-back-color-blue = <0>; - pixel-format = ; + pixel-format = ; disp-on-gpios = <&gpioc 6 GPIO_ACTIVE_HIGH>; bl-ctrl-gpios = <&gpiob 12 GPIO_ACTIVE_HIGH>; diff --git a/boards/shields/boostxl_ulpsense/doc/index.rst b/boards/shields/boostxl_ulpsense/doc/index.rst index 3521ff47c26b..ed6fadbc726f 100644 --- a/boards/shields/boostxl_ulpsense/doc/index.rst +++ b/boards/shields/boostxl_ulpsense/doc/index.rst @@ -7,7 +7,7 @@ Overview ******** The Ultra-low Power Sensor BoosterPack (BOOSTXL-ULPSENSE) adds analog and -digital sensors to a TI LaunchPad |trade| development kit. The plug-in module +digital sensors to a TI LaunchPad™ development kit. The plug-in module features inductive flow meter measurement circuits, two capacitive touch buttons, a light sensor, a reed switch, and an ultra-low power accelerometer. @@ -17,7 +17,7 @@ More information about the board can be found at the Requirements ************ -This shield can be used with any TI LaunchPad |trade| development kit with +This shield can be used with any TI LaunchPad™ development kit with BoosterPack connectors. Programming diff --git a/boards/shields/buydisplay_2_8_tft_touch_arduino/buydisplay_2_8_tft_touch_arduino.overlay b/boards/shields/buydisplay_2_8_tft_touch_arduino/buydisplay_2_8_tft_touch_arduino.overlay index cbb1b2b93885..a49cf610ae2c 100644 --- a/boards/shields/buydisplay_2_8_tft_touch_arduino/buydisplay_2_8_tft_touch_arduino.overlay +++ b/boards/shields/buydisplay_2_8_tft_touch_arduino/buydisplay_2_8_tft_touch_arduino.overlay @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include #include / { @@ -28,7 +28,7 @@ reg = <0>; width = <240>; height = <320>; - pixel-format = ; + pixel-format = ; rotation = <0>; frmctr1 = [00 18]; pwctrl1 = [23 00]; diff --git a/boards/shields/buydisplay_3_5_tft_touch_arduino/buydisplay_3_5_tft_touch_arduino.overlay b/boards/shields/buydisplay_3_5_tft_touch_arduino/buydisplay_3_5_tft_touch_arduino.overlay index 5d7bde3e3a55..238233dcae08 100644 --- a/boards/shields/buydisplay_3_5_tft_touch_arduino/buydisplay_3_5_tft_touch_arduino.overlay +++ b/boards/shields/buydisplay_3_5_tft_touch_arduino/buydisplay_3_5_tft_touch_arduino.overlay @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include #include / { @@ -26,7 +26,7 @@ compatible = "ilitek,ili9488"; mipi-max-frequency = <25000000>; reg = <0>; - pixel-format = ; + pixel-format = ; width = <320>; height = <480>; rotation = <0>; diff --git a/boards/shields/frdm_kw41z/doc/index.rst b/boards/shields/frdm_kw41z/doc/index.rst index 1b7ed8ffa890..52a5b4f4f3b4 100644 --- a/boards/shields/frdm_kw41z/doc/index.rst +++ b/boards/shields/frdm_kw41z/doc/index.rst @@ -6,11 +6,11 @@ NXP FRDM-KW41Z Shield Overview ******** -The FRDM-KW41Z is a development kit enabled by the Kinetis |reg| W series -KW41Z/31Z/21Z (KW41Z) family built on ARM |reg| Cortex |reg|-M0+ processor with -integrated 2.4 GHz transceiver supporting Bluetooth |reg| Smart/Bluetooth -|reg| Low Energy -(BLE) v4.2, Generic FSK, IEEE |reg| 802.15.4 and Thread. +The FRDM-KW41Z is a development kit enabled by the Kinetis® W series +KW41Z/31Z/21Z (KW41Z) family built on ARM® Cortex®-M0+ processor with +integrated 2.4 GHz transceiver supporting Bluetooth® Smart/Bluetooth® +Low Energy +(BLE) v4.2, Generic FSK, IEEE® 802.15.4 and Thread. The FRDM-KW41Z can be used as a standalone board or as an Arduino shield. This document covers usage as a shield; see :zephyr:board:`frdm_kw41z` for usage as a diff --git a/boards/shields/frdm_stbc_agm01/doc/index.rst b/boards/shields/frdm_stbc_agm01/doc/index.rst index 3a46e67d308f..86ced2c7eae9 100644 --- a/boards/shields/frdm_stbc_agm01/doc/index.rst +++ b/boards/shields/frdm_stbc_agm01/doc/index.rst @@ -6,6 +6,8 @@ NXP FRDM-STBC-AGM01 Overview ******** +The FRDM-STBC-AGM01 product is no longer manufactured (discontinued). + The FRDM-STBC-AGM01 is an NXP Freedom development board with FXOS8700 and FXAS21002. This 9-axis solution (FXAS21002C Gyroscope, + FXOS8700CQ E-compass sensor) is compatible with any board that diff --git a/boards/shields/g1120b0mipi/Kconfig.defconfig b/boards/shields/g1120b0mipi/Kconfig.defconfig index dd96ec88e06c..3ebe16c71ecd 100644 --- a/boards/shields/g1120b0mipi/Kconfig.defconfig +++ b/boards/shields/g1120b0mipi/Kconfig.defconfig @@ -3,22 +3,11 @@ if SHIELD_G1120B0MIPI -if LVGL # Enable input subsystem for FT5336 driver config INPUT default y -if MIPI_DSI_MCUX_2L -# Enable color swap in driver - -config MIPI_DSI_MCUX_2L_SWAP16 - default y - -endif # MIPI_DSI_MCUX_2L - -# Swap 16 bit color setting for LVGL, to send high byte first -configdefault LV_COLOR_16_SWAP - default y if !MIPI_DSI_MCUX_2L_SWAP16 +if LVGL config LV_Z_VDB_SIZE default 16 diff --git a/boards/shields/g1120b0mipi/boards/mimxrt595_evk_mimxrt595s_cm33.conf b/boards/shields/g1120b0mipi/boards/mimxrt595_evk_mimxrt595s_cm33.conf index ffe50a964edd..7e817c2a35e7 100644 --- a/boards/shields/g1120b0mipi/boards/mimxrt595_evk_mimxrt595s_cm33.conf +++ b/boards/shields/g1120b0mipi/boards/mimxrt595_evk_mimxrt595s_cm33.conf @@ -1,2 +1,4 @@ # Enable DMA, so that DSI MCUX will use SMARTDMA CONFIG_DMA=y +CONFIG_MIPI_DSI_MCUX_2L_SWAP16=y +CONFIG_LV_COLOR_16_SWAP=n diff --git a/boards/shields/g1120b0mipi/boards/mimxrt595_evk_mimxrt595s_cm33.overlay b/boards/shields/g1120b0mipi/boards/mimxrt595_evk_mimxrt595s_cm33.overlay index 7e9a98e68b96..94797404c03d 100644 --- a/boards/shields/g1120b0mipi/boards/mimxrt595_evk_mimxrt595s_cm33.overlay +++ b/boards/shields/g1120b0mipi/boards/mimxrt595_evk_mimxrt595s_cm33.overlay @@ -8,8 +8,8 @@ * so the SMARTDMA will continue functioning after deep sleep */ &suspend { - deep-sleep-config = <0xC800>, + deep-sleep-config = <0xc800>, <0x80030004>, - <0xFFFFFFFF>, + <0xffffffff>, <0>; }; diff --git a/boards/shields/g1120b0mipi/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.conf b/boards/shields/g1120b0mipi/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.conf index 768bb57bef21..346a06418fed 100644 --- a/boards/shields/g1120b0mipi/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.conf +++ b/boards/shields/g1120b0mipi/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.conf @@ -1,2 +1,4 @@ CONFIG_REGULATOR=y CONFIG_DCACHE=n +CONFIG_MIPI_DSI_MCUX_2L_SWAP16=y +CONFIG_LV_COLOR_16_SWAP=n diff --git a/boards/shields/lcd_par_s035/lcd_par_s035_8080.overlay b/boards/shields/lcd_par_s035/lcd_par_s035_8080.overlay index a58ef1a7cf67..7d006f661f8a 100644 --- a/boards/shields/lcd_par_s035/lcd_par_s035_8080.overlay +++ b/boards/shields/lcd_par_s035/lcd_par_s035_8080.overlay @@ -29,9 +29,9 @@ irq-gpios = <&nxp_lcd_8080_connector 9 GPIO_ACTIVE_HIGH>; zephyr,deferred-init; swapped-x-y; - inverted-y; - screen-width = <480>; - screen-height = <320>; + inverted-x; + screen-width = <320>; + screen-height = <480>; }; }; @@ -51,15 +51,15 @@ width = <480>; invert-mode = "1-dot"; frmctl1 = [80 10]; - bpc = [1F 50 00 20]; - dfc = [8A 07 3B]; + bpc = [1f 50 00 20]; + dfc = [8a 07 3b]; pwr1 = [80 64]; pwr2 = <0x13>; - pwr3 = <0xA7>; + pwr3 = <0xa7>; vcmpctl = <0x09>; - doca = [40 8A 00 00 29 19 A5 33]; - pgc = [F0 06 0B 07 06 05 2E 33 47 3A 17 16 2E 31]; - ngc = [F0 09 0D 09 08 23 2E 33 46 38 13 13 2C 32]; + doca = [40 8a 00 00 29 19 a5 33]; + pgc = [f0 06 0b 07 06 05 2e 33 47 3a 17 16 2e 31]; + ngc = [f0 09 0d 09 08 23 2e 33 46 38 13 13 2c 32]; madctl = <0x28>; color-invert; zephyr,deferred-init; diff --git a/boards/shields/lcd_par_s035/lcd_par_s035_spi.overlay b/boards/shields/lcd_par_s035/lcd_par_s035_spi.overlay index 374c3af53888..7ac70db8252d 100644 --- a/boards/shields/lcd_par_s035/lcd_par_s035_spi.overlay +++ b/boards/shields/lcd_par_s035/lcd_par_s035_spi.overlay @@ -30,9 +30,9 @@ irq-gpios = <&nxp_lcd_pmod_connector 12 GPIO_ACTIVE_HIGH>; zephyr,deferred-init; swapped-x-y; - inverted-y; - screen-width = <480>; - screen-height = <320>; + inverted-x; + screen-width = <320>; + screen-height = <480>; }; }; @@ -59,15 +59,15 @@ width = <480>; invert-mode = "1-dot"; frmctl1 = [80 10]; - bpc = [1F 50 00 20]; - dfc = [8A 07 3B]; + bpc = [1f 50 00 20]; + dfc = [8a 07 3b]; pwr1 = [80 64]; pwr2 = <0x13>; - pwr3 = <0xA7>; + pwr3 = <0xa7>; vcmpctl = <0x09>; - doca = [40 8A 00 00 29 19 A5 33]; - pgc = [F0 06 0B 07 06 05 2E 33 47 3A 17 16 2E 31]; - ngc = [F0 09 0D 09 08 23 2E 33 46 38 13 13 2C 32]; + doca = [40 8a 00 00 29 19 a5 33]; + pgc = [f0 06 0b 07 06 05 2e 33 47 3a 17 16 2e 31]; + ngc = [f0 09 0d 09 08 23 2e 33 46 38 13 13 2c 32]; madctl = <0x28>; color-invert; zephyr,deferred-init; diff --git a/boards/shields/m5stack_cardputer/m5stack_cardputer.overlay b/boards/shields/m5stack_cardputer/m5stack_cardputer.overlay index 8befb2a66f29..d546518607be 100644 --- a/boards/shields/m5stack_cardputer/m5stack_cardputer.overlay +++ b/boards/shields/m5stack_cardputer/m5stack_cardputer.overlay @@ -49,7 +49,7 @@ pwctrl1-param = [a4 a1]; pvgam-param = [d0 00 02 07 0a 28 32 44 42 06 0e 12 14 17]; nvgam-param = [d0 00 02 07 0a 28 31 54 47 0e 1c 17 1b 1e]; - ram-param = [00 F0]; + ram-param = [00 f0]; rgb-param = [40 02 14]; mipi-mode = "MIPI_DBI_MODE_SPI_4WIRE"; }; diff --git a/boards/shields/mcp2515/Kconfig.shield b/boards/shields/mcp2515/Kconfig.shield index 5cb2ae7d7b90..f6f3bc93e04c 100644 --- a/boards/shields/mcp2515/Kconfig.shield +++ b/boards/shields/mcp2515/Kconfig.shield @@ -9,3 +9,6 @@ config SHIELD_KEYESTUDIO_CAN_BUS_KS0411 config SHIELD_ADAFRUIT_CAN_PICOWBELL def_bool $(shields_list_contains,adafruit_can_picowbell) + +config SHIELD_SEEED_XIAO_CAN + def_bool $(shields_list_contains,seeed_xiao_can) diff --git a/boards/shields/mcp2515/doc/index.rst b/boards/shields/mcp2515/doc/index.rst index 3ea59df46864..84f7ac33e2d2 100644 --- a/boards/shields/mcp2515/doc/index.rst +++ b/boards/shields/mcp2515/doc/index.rst @@ -336,12 +336,104 @@ For more information about the Adafruit PiCowbell CAN Bus shield: - `MCP2515 Datasheet`_ - `TJA1051 Datasheet`_ +Seeed Studio XIAO CAN Bus Shield +******************************** + +Overview +-------- + +The Seeed Studio XIAO CAN Bus Shield is specifically designed to work with +`Seeed Studio XIAO series`_ development boards. It uses the Microchip MCP2515 +CAN controller with an SN65HVD230 high speed CAN transceiver. The shield has +an Seeed Studio XIAO compatible hardware interface. + +.. figure:: seeed_xiao_can.jpg + :align: center + :alt: Seeed Studio XIAO CAN Bus Shield + + Seeed Studio XIAO CAN Bus Shield + +Hardware +-------- + +The Seeed Studio XIAO CAN Bus Shield requires the SPI chip-select and interrupt +line on Seeed Studio XIAO header pins that are not standardized for Zephyr. +They conflict with the standardized use of the first UART on pin D6 (TX) and +D7 (RX). The shield resolves this conflict by disabling the UART. + +This means that the Zephyr console can no longer be accessed via the serial +interface, an alternative such as the USB CDC/ACM class must be used instead, +e.g. with ``--snippet cdc-acm-console`` when you invoke ``west build``. + +- MCP2515 + + - Stand-Alone CAN 2.0B Controller + - Up to 1Mb/s baud rate + - Standard and extended data and remote frames + - 3x Tx Buffers + - 2x Rx Buffers + - 6x 29-bit Filters + - 2x 29-bit Masks + - Interrupt output + - One shot mode + - High speed SPI interface (10 MHz) + +- SN65HVD230 + + - Fully compatible with the “ISO 11898” standard + - High speed (up to 1 Mbaud) + +- Connectivity + + - Screw terminal block - 3-pin 3.5mm (CAN) + - Solder pad for CAN bus termination + - Seeed Studio XIAO compatible (SPI) + ++-------+-----------------------+---------------------------+ +| Name | Function (original) | Usage | ++=======+=======================+===========================+ +| D0 | None | | ++-------+-----------------------+---------------------------+ +| D1 | None | | ++-------+-----------------------+---------------------------+ +| D2 | None | | ++-------+-----------------------+---------------------------+ +| D3 | None | | ++-------+-----------------------+---------------------------+ +| D4 | None (I2C-SDA) | | ++-------+-----------------------+---------------------------+ +| D5 | None (I2C-SCL) | | ++-------+-----------------------+---------------------------+ +| D6 | GPIO_ACTIVE_LOW (TX) | MCP2515 - INT | ++-------+-----------------------+---------------------------+ +| D7 | SPI-CS (RX) | MCP2515 | ++-------+-----------------------+---------------------------+ +| D8 | SPI-CLK | MCP2515 | ++-------+-----------------------+---------------------------+ +| D9 | SPI-MOSI | MCP2515 | ++-------+-----------------------+---------------------------+ +| D10 | SPI-MISO | MCP2515 | ++-------+-----------------------+---------------------------+ + + +- Power Supply + + - 3.3V ~ 5V + +For more information about the Seeed Studio XIAO CAN Bus shield: + +- `Seeed Studio Website`_ +- `Seeed Studio Wiki`_ +- `MCP2515 Datasheet`_ +- `SN65HVD230 Datasheet`_ + Programming *********** Set ``--shield dfrobot_can_bus_v2_0`` or ``--shield keyestudio_can_bus_ks0411`` -or ``--shield adafruit_can_picowbell`` when you invoke ``west build`` or ``cmake`` in your Zephyr application. For -example: +or ``--shield adafruit_can_picowbell`` or ``--shield seeed_xiao_can`` +when you invoke ``west build`` or ``cmake`` in your Zephyr application. +For example: .. zephyr-app-commands:: :zephyr-app: samples/drivers/can/counter @@ -364,6 +456,14 @@ example: :shield: adafruit_can_picowbell :goals: build +.. zephyr-app-commands:: + :zephyr-app: samples/drivers/can/counter + :tool: all + :board: xiao_rp2040 + :shield: seeed_xiao_can + :snippets: cdc-acm-console + :goals: build + .. _DFRobot Website: https://www.dfrobot.com/product-1444.html @@ -393,3 +493,15 @@ example: .. _TJA1051 Datasheet: https://www.nxp.com/docs/en/data-sheet/TJA1051.pdf + +.. _Seeed Studio XIAO series: + https://wiki.seeedstudio.com/SeeedStudio_XIAO_Series_Introduction + +.. _Seeed Studio Website: + https://www.seeedstudio.com/Seeed-Studio-CAN-Bus-Breakout-Board-for-XIAO-and-QT-Py-p-5702.html + +.. _Seeed Studio Wiki: + https://wiki.seeedstudio.com/xiao-can-bus-expansion + +.. _SN65HVD230 Datasheet: + https://www.ti.com/lit/ds/symlink/sn65hvd230.pdf diff --git a/boards/shields/mcp2515/doc/seeed_xiao_can.jpg b/boards/shields/mcp2515/doc/seeed_xiao_can.jpg new file mode 100644 index 000000000000..016b001d23f7 Binary files /dev/null and b/boards/shields/mcp2515/doc/seeed_xiao_can.jpg differ diff --git a/boards/shields/mcp2515/seeed_xiao_can.conf b/boards/shields/mcp2515/seeed_xiao_can.conf new file mode 100644 index 000000000000..8b3816bc3d4e --- /dev/null +++ b/boards/shields/mcp2515/seeed_xiao_can.conf @@ -0,0 +1,6 @@ +# SPDX-FileCopyrightText: Copyright (c) 2026 Navimatix GmbH +# SPDX-FileCopyrightText: Copyright (c) 2026 TiaC Systems +# SPDX-License-Identifier: Apache-2.0 + +# Enable access to XIAO D6 & D7 (CS & INT), when disabled by default on board. +CONFIG_GPIO=y diff --git a/boards/shields/mcp2515/seeed_xiao_can.overlay b/boards/shields/mcp2515/seeed_xiao_can.overlay new file mode 100644 index 000000000000..f7fe2e321aa9 --- /dev/null +++ b/boards/shields/mcp2515/seeed_xiao_can.overlay @@ -0,0 +1,34 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2026 Navimatix GmbH + * SPDX-FileCopyrightText: Copyright (c) 2026 TiaC Systems + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Disable XIAO serial function, avoid conflict with CS & INT. */ +&xiao_serial { + status = "disabled"; +}; + +&xiao_spi { + status = "okay"; + cs-gpios = <&xiao_d 7 GPIO_ACTIVE_LOW>; + + mcp2515_seeed_xiao_can: can@0 { + compatible = "microchip,mcp2515"; + spi-max-frequency = <1000000>; + int-gpios = <&xiao_d 6 GPIO_ACTIVE_LOW>; + status = "okay"; + reg = <0x0>; + osc-freq = <16000000>; + + can-transceiver { + max-bitrate = <1000000>; + }; + }; +}; + +/ { + chosen { + zephyr,canbus = &mcp2515_seeed_xiao_can; + }; +}; diff --git a/boards/shields/mcp2515/shield.yml b/boards/shields/mcp2515/shield.yml index e5fca9355fc3..ab06a0ecf2bf 100644 --- a/boards/shields/mcp2515/shield.yml +++ b/boards/shields/mcp2515/shield.yml @@ -16,3 +16,9 @@ shields: vendor: others supported_features: - can + + - name: seeed_xiao_can + full_name: XIAO CAN Bus Shield + vendor: seeed + supported_features: + - can diff --git a/boards/shields/mikroe_3d_hall_3_click/doc/index.rst b/boards/shields/mikroe_3d_hall_3_click/doc/index.rst index bd6128f711b6..ce57fc88e8d9 100644 --- a/boards/shields/mikroe_3d_hall_3_click/doc/index.rst +++ b/boards/shields/mikroe_3d_hall_3_click/doc/index.rst @@ -25,7 +25,7 @@ programmable interrupt engine, allowing firmware optimization. Requirements ************ -This shield can only be used with a board that provides a mikroBUS |trade| socket and defines a +This shield can only be used with a board that provides a mikroBUS™ socket and defines a ``mikrobus_i2c`` node label for the mikroBUS™ I2C interface. See :ref:`shields` for more details. Programming diff --git a/boards/shields/mikroe_accel13_click/doc/index.rst b/boards/shields/mikroe_accel13_click/doc/index.rst index 4290dfa2138c..69aad732af32 100644 --- a/boards/shields/mikroe_accel13_click/doc/index.rst +++ b/boards/shields/mikroe_accel13_click/doc/index.rst @@ -7,7 +7,7 @@ Overview ******** The MikroElektronika ACCEL 13 Click carries the `IIS2DLPC`_ ultra-low -power triaxial accelerometer sensor in a `mikroBUS`_ |trade| form factor. +power triaxial accelerometer sensor in a `mikroBUS™`_ form factor. The `IIS2DLPC`_ sensor supports both SPI and I2C bus protocols. Currently only I2C is supported for this shield. @@ -46,7 +46,7 @@ example: .. _IIS2DLPC: https://www.st.com/en/mems-and-sensors/iis2dlpc.html -.. _mikroBUS: +.. _mikroBUS™: https://www.mikroe.com/mikrobus .. _IIS2DLPC Datasheet: diff --git a/boards/shields/mikroe_adc_click/doc/index.rst b/boards/shields/mikroe_adc_click/doc/index.rst index c75d322a334c..682003593cc1 100644 --- a/boards/shields/mikroe_adc_click/doc/index.rst +++ b/boards/shields/mikroe_adc_click/doc/index.rst @@ -7,7 +7,7 @@ Overview ******** The MikroElektronika ADC Click carries the `MCP3204`_ 12-bit -Analog-to-Digital converter in a `mikroBUS`_ |trade| form factor. +Analog-to-Digital converter in a `mikroBUS™`_ form factor. .. figure:: adc-click.jpg :align: center @@ -43,7 +43,7 @@ example: .. _MCP3204: https://www.microchip.com/wwwproducts/en/en010533 -.. _mikroBUS: +.. _mikroBUS™: https://www.mikroe.com/mikrobus .. _MCP3204 Datasheet: diff --git a/boards/shields/mikroe_air_quality_3_click/doc/index.rst b/boards/shields/mikroe_air_quality_3_click/doc/index.rst index 268f132a1430..3775b99bce2e 100644 --- a/boards/shields/mikroe_air_quality_3_click/doc/index.rst +++ b/boards/shields/mikroe_air_quality_3_click/doc/index.rst @@ -26,8 +26,8 @@ temperature compensating element, which allows for increased measurement accurac Requirements ************ -This shield can only be used with a board that provides a mikroBUS |trade| socket and defines a -``mikrobus_i2c`` node label for the mikroBUS |trade| I2C interface. See :ref:`shields` for more +This shield can only be used with a board that provides a mikroBUS™ socket and defines a +``mikrobus_i2c`` node label for the mikroBUS™ I2C interface. See :ref:`shields` for more details. Programming diff --git a/boards/shields/mikroe_ambient_2_click/doc/index.rst b/boards/shields/mikroe_ambient_2_click/doc/index.rst index b724d6c48668..53e2a267363b 100644 --- a/boards/shields/mikroe_ambient_2_click/doc/index.rst +++ b/boards/shields/mikroe_ambient_2_click/doc/index.rst @@ -13,7 +13,7 @@ This board features the OPT3001, a digital output ambient light sensor with an I interrupt from Texas Instruments. The sensor's spectral response tightly matches the human eye's photopic response and includes significant (99%) infrared rejection. It has a flexible and wide operating range for the ambient light sensor with a resolution of 0.01lux and full detectable -illumination of 83865.6lux over a 23-bit effective dynamic range. This Click board |trade| is the +illumination of 83865.6lux over a 23-bit effective dynamic range. This Click board™ is the most suitable for obtaining ambient light data in applications such as automatic residential and commercial lighting management. @@ -28,8 +28,8 @@ Requirements ************ -This shield can only be used with a board that provides a mikroBUS |trade| socket and defines a -``mikrobus_i2c`` node label for the mikroBUS |trade| I2C interface. See :ref:`shields` for more +This shield can only be used with a board that provides a mikroBUS™ socket and defines a +``mikrobus_i2c`` node label for the mikroBUS™ I2C interface. See :ref:`shields` for more details. Programming diff --git a/boards/shields/mikroe_ble_tiny_click/doc/index.rst b/boards/shields/mikroe_ble_tiny_click/doc/index.rst index ffa721f24500..495bd619414d 100644 --- a/boards/shields/mikroe_ble_tiny_click/doc/index.rst +++ b/boards/shields/mikroe_ble_tiny_click/doc/index.rst @@ -7,7 +7,7 @@ Overview ******** The MikroElektronika BLE TINY Click carries the Renesas `DA14531MOD`_ Bluetooth -LE module in a `mikroBUS`_ |trade| form factor. +LE module in a `mikroBUS™`_ form factor. .. figure:: ble-tiny-click.webp :align: center @@ -18,7 +18,7 @@ LE module in a `mikroBUS`_ |trade| form factor. Requirements ************ -This shield can only be used with a board that provides a mikroBUS |trade| +This shield can only be used with a board that provides a mikroBUS™ socket and defines the ``mikrobus_serial`` node label (see :ref:`shields` for more details). @@ -75,7 +75,7 @@ References .. _DA14531MOD: https://www.renesas.com/us/en/products/wireless-connectivity/bluetooth-low-energy/da14531mod-smartbond-tiny-bluetooth-low-energy-module -.. _mikroBUS: +.. _mikroBUS™: https://www.mikroe.com/mikrobus .. _DA14531MOD Datasheet: diff --git a/boards/shields/mikroe_can_fd_6_click/Kconfig.shield b/boards/shields/mikroe_can_fd_6_click/Kconfig.shield new file mode 100644 index 000000000000..ce9664540002 --- /dev/null +++ b/boards/shields/mikroe_can_fd_6_click/Kconfig.shield @@ -0,0 +1,6 @@ +# SPDX-FileCopyrightText: Copyright (c) 2025 Navimatix GmbH +# SPDX-FileCopyrightText: Copyright (c) 2025 TiaC Systems +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_MIKROE_CAN_FD_6_CLICK + def_bool $(shields_list_contains,mikroe_can_fd_6_click) diff --git a/boards/shields/mikroe_can_fd_6_click/doc/index.rst b/boards/shields/mikroe_can_fd_6_click/doc/index.rst new file mode 100644 index 000000000000..13885ae98ed8 --- /dev/null +++ b/boards/shields/mikroe_can_fd_6_click/doc/index.rst @@ -0,0 +1,51 @@ +.. _mikroe_can_fd_6_click_shield: + +MikroElektronika CAN FD 6 Click +############################### + +Overview +-------- + +The CAN FD 6 Click shield has a `TI TCAN4550-Q1`_ automotive system +basis chip (SBC) with integrated CAN FD controller via a SPI interface +and a integrated high-speed CAN FD transceiver with up to 5 Mbps. + +More information about the shield can be found at +`Mikroe CAN FD 6 click`_. + +.. figure:: mikroe_can_fd_6_click.webp + :align: center + :alt: MikroElektronika CAN FD 6 Click + + MikroElektronika CAN FD 6 Click (Credit: MikroElektronika) + +Requirements +************ + +The shield uses a mikroBUS interface. The target board must define the +``mikrobus_spi`` and ``mikrobus_header`` node labels (see :ref:`shields` +for more details). The target board must also support level triggered +interrupts and SPI clock frequency of up to 18 MHz. + +Programming +*********** + +Set ``--shield mikroe_can_fd_6_click`` when you invoke ``west build``, +for example: + +.. zephyr-app-commands:: + :zephyr-app: samples/drivers/can/counter + :board: mikroe_stm32_m4_clicker + :shield: mikroe_can_fd_6_click + :goals: build flash + +References +********** + +.. target-notes:: + +.. _Mikroe CAN FD 6 click: + https://www.mikroe.com/can-fd-6-click + +.. _TI TCAN4550-Q1: + https://www.ti.com/product/TCAN4550-Q1 diff --git a/boards/shields/mikroe_can_fd_6_click/doc/mikroe_can_fd_6_click.webp b/boards/shields/mikroe_can_fd_6_click/doc/mikroe_can_fd_6_click.webp new file mode 100644 index 000000000000..55c3c41f126f Binary files /dev/null and b/boards/shields/mikroe_can_fd_6_click/doc/mikroe_can_fd_6_click.webp differ diff --git a/boards/shields/mikroe_can_fd_6_click/mikroe_can_fd_6_click.overlay b/boards/shields/mikroe_can_fd_6_click/mikroe_can_fd_6_click.overlay new file mode 100644 index 000000000000..4bafde879a64 --- /dev/null +++ b/boards/shields/mikroe_can_fd_6_click/mikroe_can_fd_6_click.overlay @@ -0,0 +1,37 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2025 Navimatix GmbH + * SPDX-FileCopyrightText: Copyright (c) 2025 TiaC Systems + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&mikrobus_spi { + status = "okay"; + cs-gpios = <&mikrobus_header 2 GPIO_ACTIVE_LOW>; + + tcan4x5x_mikroe_can_fd_6_click: tcan4x5x@0 { + compatible = "ti,tcan4x5x"; + reg = <0>; + spi-max-frequency = <18000000>; + status = "okay"; + + clock-frequency = <40000000>; + device-state-gpios = <&mikrobus_header 0 GPIO_ACTIVE_HIGH>; + device-wake-gpios = <&mikrobus_header 6 GPIO_ACTIVE_HIGH>; + reset-gpios = <&mikrobus_header 1 GPIO_ACTIVE_HIGH>; + int-gpios = <&mikrobus_header 7 GPIO_ACTIVE_LOW>; + bosch,mram-cfg = <0x0 15 15 7 7 0 10 10>; + + can-transceiver { + max-bitrate = <8000000>; + }; + }; +}; + +/ { + chosen { + zephyr,canbus = &tcan4x5x_mikroe_can_fd_6_click; + }; +}; diff --git a/boards/shields/mikroe_can_fd_6_click/shield.yml b/boards/shields/mikroe_can_fd_6_click/shield.yml new file mode 100644 index 000000000000..ed6850e7d4b9 --- /dev/null +++ b/boards/shields/mikroe_can_fd_6_click/shield.yml @@ -0,0 +1,10 @@ +# SPDX-FileCopyrightText: Copyright (c) 2025 Navimatix GmbH +# SPDX-FileCopyrightText: Copyright (c) 2025 TiaC Systems +# SPDX-License-Identifier: Apache-2.0 + +shield: + name: mikroe_can_fd_6_click + full_name: CAN FD 6 Click + vendor: mikroe + supported_features: + - can diff --git a/boards/shields/mikroe_illuminance_click/doc/index.rst b/boards/shields/mikroe_illuminance_click/doc/index.rst index 97c7d4505fbc..51ac1e9b788a 100644 --- a/boards/shields/mikroe_illuminance_click/doc/index.rst +++ b/boards/shields/mikroe_illuminance_click/doc/index.rst @@ -11,7 +11,7 @@ features ams OSRAM TSL2583, a very-high sensitivity light-to-digital converter t intensity to a digital signal output capable of the direct I2C interface. It combines one broadband photodiode (visible plus infrared) and one infrared-responding photodiode on a single CMOS integrated circuit capable of providing a near-photopic response over an effective 16-bit dynamic -range (16-bit resolution). This Click board |trade| is suitable for general-purpose light sensing +range (16-bit resolution). This Click board™ is suitable for general-purpose light sensing applications to extend battery life and provide optimum viewing in diverse lighting conditions. .. figure:: images/mikroe_illuminance_click.webp @@ -24,8 +24,8 @@ applications to extend battery life and provide optimum viewing in diverse light Requirements ************ -This shield can only be used with a board that provides a mikroBUS |trade| socket and defines a -``mikrobus_i2c`` node label for the mikroBUS |trade| I2C interface. See :ref:`shields` for more +This shield can only be used with a board that provides a mikroBUS™ socket and defines a +``mikrobus_i2c`` node label for the mikroBUS™ I2C interface. See :ref:`shields` for more details. Programming diff --git a/boards/shields/mikroe_ir_gesture_click/doc/index.rst b/boards/shields/mikroe_ir_gesture_click/doc/index.rst index 996e2a3236fc..16adba66f29a 100644 --- a/boards/shields/mikroe_ir_gesture_click/doc/index.rst +++ b/boards/shields/mikroe_ir_gesture_click/doc/index.rst @@ -29,8 +29,8 @@ switch replacement, and more. Requirements ************ -This shield can only be used with a board that provides a mikroBUS |trade| socket and defines a -``mikrobus_i2c`` node label for the mikroBUS |trade| I2C interface. See :ref:`shields` for more +This shield can only be used with a board that provides a mikroBUS™ socket and defines a +``mikrobus_i2c`` node label for the mikroBUS™ I2C interface. See :ref:`shields` for more details. Programming diff --git a/boards/shields/mikroe_lsm6dsl_click/doc/index.rst b/boards/shields/mikroe_lsm6dsl_click/doc/index.rst index c2284b53da67..b58747e0687a 100644 --- a/boards/shields/mikroe_lsm6dsl_click/doc/index.rst +++ b/boards/shields/mikroe_lsm6dsl_click/doc/index.rst @@ -10,7 +10,7 @@ Overview LSM6DSL high-performance 3-axis digital accelerometer and 3-axis digital gyroscope. The click is designed to run on a 3.3V power supply. `LSM6DSL Click`_ communicates with the target micro-controller over SPI or I2C interface, with additional functionality provided by the INT pin on -the mikroBUS |trade| line. +the mikroBUS™ line. .. figure:: images/mikroe_lsm6dsl_click.webp :align: center @@ -22,8 +22,8 @@ the mikroBUS |trade| line. Requirements ************ -This shield can only be used with a board that provides a mikroBUS |trade| socket and defines a -``mikrobus_spi`` node label for the mikroBUS |trade| SPI interface. See :ref:`shields` for more +This shield can only be used with a board that provides a mikroBUS™ socket and defines a +``mikrobus_spi`` node label for the mikroBUS™ SPI interface. See :ref:`shields` for more details. Programming diff --git a/boards/shields/mikroe_mcp2518fd_click/Kconfig.shield b/boards/shields/mikroe_mcp2518fd_click/Kconfig.shield deleted file mode 100644 index 5db87f809c78..000000000000 --- a/boards/shields/mikroe_mcp2518fd_click/Kconfig.shield +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2023 Andriy Gelman -# SPDX-License-Identifier: Apache-2.0 - -config SHIELD_MIKROE_MCP2518FD_CLICK - def_bool $(shields_list_contains,mikroe_mcp2518fd_click) diff --git a/boards/shields/mikroe_mcp2518fd_click/doc/index.rst b/boards/shields/mikroe_mcp2518fd_click/doc/index.rst deleted file mode 100644 index e54bf7509c7f..000000000000 --- a/boards/shields/mikroe_mcp2518fd_click/doc/index.rst +++ /dev/null @@ -1,41 +0,0 @@ -.. _mikroe_mcp2518fd_click_shield: - -MikroElektronika MCP2518FD Click shield -####################################### - -Overview --------- - -MCP2518FD Click shield has a MCP2518FD CAN FD controller via a SPI -interface and a high-speed ATA6563 CAN transceiver. - -More information about the shield can be found at -`Mikroe MCP2518FD click`_. - -Requirements -************ - -The shield uses a mikroBUS interface. The target board must define -a ``mikrobus_spi`` and ``mikrobus_header`` node labels -(see :ref:`shields` for more details). The target board must also -support level triggered interrupts. - -Programming -*********** - -Set ``--shield mikroe_mcp2518fd_click`` when you invoke ``west build``, -for example: - -.. zephyr-app-commands:: - :zephyr-app: samples/drivers/can/counter - :board: lpcxpresso55s28 - :shield: mikroe_mcp2518fd_click - :goals: build flash - -References -********** - -.. target-notes:: - -.. _Mikroe MCP2518FD click: - https://www.mikroe.com/mcp2518fd-click diff --git a/boards/shields/mikroe_mcp2518fd_click/shield.yml b/boards/shields/mikroe_mcp2518fd_click/shield.yml deleted file mode 100644 index 817ea25ca7fe..000000000000 --- a/boards/shields/mikroe_mcp2518fd_click/shield.yml +++ /dev/null @@ -1,6 +0,0 @@ -shield: - name: mikroe_mcp2518fd_click - full_name: MikroElektronika MCP2518FD Click shield - vendor: mikroe - supported_features: - - can diff --git a/boards/shields/mikroe_mcp251x_click/Kconfig.shield b/boards/shields/mikroe_mcp251x_click/Kconfig.shield new file mode 100644 index 000000000000..17c2b867c513 --- /dev/null +++ b/boards/shields/mikroe_mcp251x_click/Kconfig.shield @@ -0,0 +1,9 @@ +# SPDX-FileCopyrightText: Copyright (c) 2026 Navimatix GmbH +# SPDX-FileCopyrightText: Copyright (c) 2026 TiaC Systems +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_MIKROE_CAN_SPI_CLICK + def_bool $(shields_list_contains,mikroe_can_spi_click) + +config SHIELD_MIKROE_MCP25625_CLICK + def_bool $(shields_list_contains,mikroe_mcp25625_click) diff --git a/boards/shields/mikroe_mcp251x_click/doc/index.rst b/boards/shields/mikroe_mcp251x_click/doc/index.rst new file mode 100644 index 000000000000..92dfd81443f3 --- /dev/null +++ b/boards/shields/mikroe_mcp251x_click/doc/index.rst @@ -0,0 +1,108 @@ +.. _mikroe_mcp251x_click_shield: + +MikroElektronika MCP251x Click shields +###################################### + +Zephyr supports a few different MikroElektronika Click shields carrying the +Microchip `External CAN Controllers`_, either with or without integrated +`CAN Transceiver`_. + +.. _mikroe_can_spi_click_shield: + +MikroElektronika CAN SPI 3.3V/5V Click shield +********************************************* + +Overview +-------- + +The CAN SPI 3.3V/5V Click shield has a `MCP2515`_ stand-alone CAN controller +via a SPI interface and a high-speed `SN65HVD230`_ CAN transceiver. + +More information about the shield can be found at +`Mikroe CAN SPI 3.3V click`_ and `Mikroe CAN SPI 5V click`_. + +.. figure:: mikroe_can_spi_click.webp + :align: center + :alt: MikroElektronika CAN SPI 3.3V/5V Click + + MikroElektronika CAN SPI 3.3V/5V Click (Credit: MikroElektronika) + +.. _mikroe_mcp25625_click_shield: + +MikroElektronika MCP25625 Click shield +************************************** + +Overview +-------- + +The MCP25625 Click shield has a `MCP25625`_ CAN controller via a SPI +interface with an integrated high-speed `MCP2562`_ CAN transceiver. This +CAN controller is software compatible with the stand-alone `MCP2515`_ +CAN controller. + +More information about the shield can be found at +`Mikroe MCP25625 click`_. + +.. figure:: mikroe_mcp25625_click.webp + :align: center + :alt: MikroElektronika MCP25625 Click + + MikroElektronika MCP25625 Click (Credit: MikroElektronika) + +Requirements +************ + +These shields use a mikroBUS interface. The target board must define the +``mikrobus_spi`` and ``mikrobus_header`` node labels (see :ref:`shields` +for more details). The target board must also support level triggered +interrupts and SPI clock frequency of up to 10 MHz. + +Programming +*********** + +Set ``--shield mikroe_can_spi_click`` or ``--shield mikroe_mcp25625_click`` +when you invoke ``west build``, for example: + +.. zephyr-app-commands:: + :zephyr-app: samples/drivers/can/counter + :board: lpcxpresso55s28 + :shield: mikroe_can_spi_click + :goals: build flash + +.. zephyr-app-commands:: + :zephyr-app: samples/drivers/can/counter + :board: lpcxpresso55s28 + :shield: mikroe_mcp25625_click + :goals: build flash + +References +********** + +.. target-notes:: + +.. _External CAN Controllers: + https://www.microchip.com/en-us/products/interface-and-connectivity/can/can-external-controllers + +.. _CAN Transceiver: + https://www.microchip.com/en-us/products/interface-and-connectivity/can/can-transceivers + +.. _SN65HVD230: + https://www.ti.com/product/SN65HVD230 + +.. _MCP2515: + https://www.microchip.com/en-us/product/MCP2515 + +.. _MCP2562: + https://www.microchip.com/en-us/product/MCP2562 + +.. _MCP25625: + https://www.microchip.com/en-us/product/MCP25625 + +.. _Mikroe CAN SPI 3.3V click: + https://www.mikroe.com/can-spi-33v-click + +.. _Mikroe CAN SPI 5V click: + https://www.mikroe.com/can-spi-5v-click + +.. _Mikroe MCP25625 click: + https://www.mikroe.com/mcp25625-click diff --git a/boards/shields/mikroe_mcp251x_click/doc/mikroe_can_spi_click.webp b/boards/shields/mikroe_mcp251x_click/doc/mikroe_can_spi_click.webp new file mode 100644 index 000000000000..a9ddb4b929fb Binary files /dev/null and b/boards/shields/mikroe_mcp251x_click/doc/mikroe_can_spi_click.webp differ diff --git a/boards/shields/mikroe_mcp251x_click/doc/mikroe_mcp25625_click.webp b/boards/shields/mikroe_mcp251x_click/doc/mikroe_mcp25625_click.webp new file mode 100644 index 000000000000..d0d642b8a4c6 Binary files /dev/null and b/boards/shields/mikroe_mcp251x_click/doc/mikroe_mcp25625_click.webp differ diff --git a/boards/shields/mikroe_mcp251x_click/mikroe_can_spi_click.overlay b/boards/shields/mikroe_mcp251x_click/mikroe_can_spi_click.overlay new file mode 100644 index 000000000000..0bdb0fec338b --- /dev/null +++ b/boards/shields/mikroe_mcp251x_click/mikroe_can_spi_click.overlay @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2026 Navimatix GmbH + * SPDX-FileCopyrightText: Copyright (c) 2026 TiaC Systems + * SPDX-License-Identifier: Apache-2.0 + */ + +&mikrobus_spi { + cs-gpios = <&mikrobus_header 2 GPIO_ACTIVE_LOW>; + + mcp2515_mikroe_can_spi_click: mcp2515@0 { + compatible = "microchip,mcp2515"; + status = "okay"; + + spi-max-frequency = <10000000>; + int-gpios = <&mikrobus_header 7 GPIO_ACTIVE_LOW>; + reg = <0x0>; + osc-freq = <10000000>; + + can-transceiver { + max-bitrate = <1000000>; + }; + }; +}; + +/ { + chosen { + zephyr,canbus = &mcp2515_mikroe_can_spi_click; + }; +}; diff --git a/boards/shields/mikroe_mcp251x_click/mikroe_mcp25625_click.overlay b/boards/shields/mikroe_mcp251x_click/mikroe_mcp25625_click.overlay new file mode 100644 index 000000000000..acfc31207a86 --- /dev/null +++ b/boards/shields/mikroe_mcp251x_click/mikroe_mcp25625_click.overlay @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2026 Navimatix GmbH + * SPDX-FileCopyrightText: Copyright (c) 2026 TiaC Systems + * SPDX-License-Identifier: Apache-2.0 + */ + +&mikrobus_spi { + cs-gpios = <&mikrobus_header 2 GPIO_ACTIVE_LOW>; + + mcp25625_mikroe_mcp25625_click: mcp25625@0 { + compatible = "microchip,mcp2515"; + status = "okay"; + + spi-max-frequency = <10000000>; + int-gpios = <&mikrobus_header 7 GPIO_ACTIVE_LOW>; + reg = <0x0>; + osc-freq = <20000000>; + + can-transceiver { + max-bitrate = <1000000>; + }; + }; +}; + +/ { + chosen { + zephyr,canbus = &mcp25625_mikroe_mcp25625_click; + }; +}; diff --git a/boards/shields/mikroe_mcp251x_click/shield.yml b/boards/shields/mikroe_mcp251x_click/shield.yml new file mode 100644 index 000000000000..1ec61a6006a7 --- /dev/null +++ b/boards/shields/mikroe_mcp251x_click/shield.yml @@ -0,0 +1,16 @@ +# SPDX-FileCopyrightText: Copyright (c) 2026 Navimatix GmbH +# SPDX-FileCopyrightText: Copyright (c) 2026 TiaC Systems +# SPDX-License-Identifier: Apache-2.0 + +shields: + - name: mikroe_can_spi_click + full_name: MikroElektronika CAN SPI Click shield + vendor: mikroe + supported_features: + - can + + - name: mikroe_mcp25625_click + full_name: MikroElektronika MCP25625 Click shield + vendor: mikroe + supported_features: + - can diff --git a/boards/shields/mikroe_mcp251xfd_click/Kconfig.shield b/boards/shields/mikroe_mcp251xfd_click/Kconfig.shield new file mode 100644 index 000000000000..6e9e35de0919 --- /dev/null +++ b/boards/shields/mikroe_mcp251xfd_click/Kconfig.shield @@ -0,0 +1,13 @@ +# SPDX-FileCopyrightText: Copyright (c) 2023 Andriy Gelman +# SPDX-FileCopyrightText: Copyright (c) 2026 Navimatix GmbH +# SPDX-FileCopyrightText: Copyright (c) 2026 TiaC Systems +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_MIKROE_MCP2517FD_CLICK + def_bool $(shields_list_contains,mikroe_mcp2517fd_click) + +config SHIELD_MIKROE_MCP2518FD_CLICK + def_bool $(shields_list_contains,mikroe_mcp2518fd_click) + +config SHIELD_MIKROE_MCP251863_CLICK + def_bool $(shields_list_contains,mikroe_mcp251863_click) diff --git a/boards/shields/mikroe_mcp251xfd_click/doc/index.rst b/boards/shields/mikroe_mcp251xfd_click/doc/index.rst new file mode 100644 index 000000000000..fa6ceb4982c6 --- /dev/null +++ b/boards/shields/mikroe_mcp251xfd_click/doc/index.rst @@ -0,0 +1,135 @@ +.. _mikroe_mcp251xfd_click_shield: + +MikroElektronika MCP251xFD Click shields +######################################## + +Zephyr supports a few different MikroElektronika Click shields carrying the +Microchip `External CAN FD Controllers`_, either with or without integrated +`CAN FD Transceiver`_. + +.. _mikroe_mcp2517fd_click_shield: + +MikroElektronika MCP2517FD Click shield +*************************************** + +Overview +-------- + +The MCP2517FD Click shield has a `MCP2517FD`_ CAN FD controller via a SPI +interface and a high-speed `ATA6563`_ CAN transceiver. + +More information about the shield can be found at +`Mikroe MCP2517FD click`_. + +.. figure:: mikroe_mcp2517fd_click.webp + :align: center + :alt: MikroElektronika MCP2517FD Click + + MikroElektronika MCP2517FD Click (Credit: MikroElektronika) + +.. _mikroe_mcp2518fd_click_shield: + +MikroElektronika MCP2518FD Click shield +*************************************** + +Overview +-------- + +The MCP2518FD Click shield has a `MCP2518FD`_ CAN FD controller via a SPI +interface and a high-speed `ATA6563`_ CAN transceiver. + +More information about the shield can be found at +`Mikroe MCP2518FD click`_. + +.. figure:: mikroe_mcp2518fd_click.webp + :align: center + :alt: MikroElektronika MCP2518FD Click + + MikroElektronika MCP2518FD Click (Credit: MikroElektronika) + +.. _mikroe_mcp251863_click_shield: + +MikroElektronika MCP251863 Click shield +*************************************** + +Overview +-------- + +The MCP251863 Click shield has a `MCP251863`_ CAN FD controller via a SPI +interface with an integrated high-speed `ATA6563`_ CAN transceiver. This +CAN FD controller is software compatible with the stand-alone `MCP2518FD`_ +CAN FD controller. + +More information about the shield can be found at +`Mikroe MCP251863 click`_. + +.. figure:: mikroe_mcp251863_click.webp + :align: center + :alt: MikroElektronika MCP251863 Click + + MikroElektronika MCP251863 Click (Credit: MikroElektronika) + +Requirements +************ + +These shields use a mikroBUS interface. The target board must define the +``mikrobus_spi`` and ``mikrobus_header`` node labels (see :ref:`shields` +for more details). The target board must also support level triggered +interrupts and SPI clock frequency of up to 18 MHz. + +Programming +*********** + +Set ``--shield mikroe_mcp2517fd_click`` or ``--shield mikroe_mcp2518fd_click`` +or ``--shield mikroe_mcp251863_click`` when you invoke ``west build``, +for example: + +.. zephyr-app-commands:: + :zephyr-app: samples/drivers/can/counter + :board: lpcxpresso55s28 + :shield: mikroe_mcp2517fd_click + :goals: build flash + +.. zephyr-app-commands:: + :zephyr-app: samples/drivers/can/counter + :board: lpcxpresso55s28 + :shield: mikroe_mcp2518fd_click + :goals: build flash + +.. zephyr-app-commands:: + :zephyr-app: samples/drivers/can/counter + :board: lpcxpresso55s28 + :shield: mikroe_mcp251863_click + :goals: build flash + +References +********** + +.. target-notes:: + +.. _External CAN FD Controllers: + https://www.microchip.com/en-us/products/interface-and-connectivity/can/can-external-controllers + +.. _CAN FD Transceiver: + https://www.microchip.com/en-us/products/interface-and-connectivity/can/can-transceivers + +.. _ATA6563: + https://www.microchip.com/en-us/product/ATA6563 + +.. _MCP2517FD: + https://www.microchip.com/en-us/product/MCP2517FD + +.. _MCP2518FD: + https://www.microchip.com/en-us/product/MCP2518FD + +.. _MCP251863: + https://www.microchip.com/en-us/product/MCP251863 + +.. _Mikroe MCP2517FD click: + https://www.mikroe.com/mcp2517fd-click + +.. _Mikroe MCP2518FD click: + https://www.mikroe.com/mcp2518fd-click + +.. _Mikroe MCP251863 click: + https://www.mikroe.com/mcp251863-click diff --git a/boards/shields/mikroe_mcp251xfd_click/doc/mikroe_mcp2517fd_click.webp b/boards/shields/mikroe_mcp251xfd_click/doc/mikroe_mcp2517fd_click.webp new file mode 100644 index 000000000000..255b8499fe3c Binary files /dev/null and b/boards/shields/mikroe_mcp251xfd_click/doc/mikroe_mcp2517fd_click.webp differ diff --git a/boards/shields/mikroe_mcp251xfd_click/doc/mikroe_mcp251863_click.webp b/boards/shields/mikroe_mcp251xfd_click/doc/mikroe_mcp251863_click.webp new file mode 100644 index 000000000000..325cdeb34ca1 Binary files /dev/null and b/boards/shields/mikroe_mcp251xfd_click/doc/mikroe_mcp251863_click.webp differ diff --git a/boards/shields/mikroe_mcp251xfd_click/doc/mikroe_mcp2518fd_click.webp b/boards/shields/mikroe_mcp251xfd_click/doc/mikroe_mcp2518fd_click.webp new file mode 100644 index 000000000000..06e7c8019b2d Binary files /dev/null and b/boards/shields/mikroe_mcp251xfd_click/doc/mikroe_mcp2518fd_click.webp differ diff --git a/boards/shields/mikroe_mcp251xfd_click/mikroe_mcp2517fd_click.overlay b/boards/shields/mikroe_mcp251xfd_click/mikroe_mcp2517fd_click.overlay new file mode 100644 index 000000000000..a62ca249f127 --- /dev/null +++ b/boards/shields/mikroe_mcp251xfd_click/mikroe_mcp2517fd_click.overlay @@ -0,0 +1,25 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2026 Navimatix GmbH + * SPDX-FileCopyrightText: Copyright (c) 2026 TiaC Systems + * SPDX-License-Identifier: Apache-2.0 + */ + +&mikrobus_spi { + cs-gpios = <&mikrobus_header 2 GPIO_ACTIVE_LOW>; + + mcp2517fd_mikroe_mcp2517fd_click: mcp2517fd@0 { + compatible = "microchip,mcp251xfd"; + status = "okay"; + + spi-max-frequency = <18000000>; + int-gpios = <&mikrobus_header 7 GPIO_ACTIVE_LOW>; + reg = <0x0>; + osc-freq = <40000000>; + }; +}; + +/ { + chosen { + zephyr,canbus = &mcp2517fd_mikroe_mcp2517fd_click; + }; +}; diff --git a/boards/shields/mikroe_mcp251xfd_click/mikroe_mcp251863_click.overlay b/boards/shields/mikroe_mcp251xfd_click/mikroe_mcp251863_click.overlay new file mode 100644 index 000000000000..ecdcda01b246 --- /dev/null +++ b/boards/shields/mikroe_mcp251xfd_click/mikroe_mcp251863_click.overlay @@ -0,0 +1,25 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2026 Navimatix GmbH + * SPDX-FileCopyrightText: Copyright (c) 2026 TiaC Systems + * SPDX-License-Identifier: Apache-2.0 + */ + +&mikrobus_spi { + cs-gpios = <&mikrobus_header 2 GPIO_ACTIVE_LOW>; + + mcp251863_mikroe_mcp251863_click: mcp251863@0 { + compatible = "microchip,mcp251xfd"; + status = "okay"; + + spi-max-frequency = <18000000>; + int-gpios = <&mikrobus_header 7 GPIO_ACTIVE_LOW>; + reg = <0x0>; + osc-freq = <40000000>; + }; +}; + +/ { + chosen { + zephyr,canbus = &mcp251863_mikroe_mcp251863_click; + }; +}; diff --git a/boards/shields/mikroe_mcp2518fd_click/mikroe_mcp2518fd_click.overlay b/boards/shields/mikroe_mcp251xfd_click/mikroe_mcp2518fd_click.overlay similarity index 78% rename from boards/shields/mikroe_mcp2518fd_click/mikroe_mcp2518fd_click.overlay rename to boards/shields/mikroe_mcp251xfd_click/mikroe_mcp2518fd_click.overlay index 5836f654438f..c5e0fce74289 100644 --- a/boards/shields/mikroe_mcp2518fd_click/mikroe_mcp2518fd_click.overlay +++ b/boards/shields/mikroe_mcp251xfd_click/mikroe_mcp2518fd_click.overlay @@ -1,3 +1,8 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 Andriy Gelman + * SPDX-License-Identifier: Apache-2.0 + */ + &mikrobus_spi { cs-gpios = <&mikrobus_header 2 GPIO_ACTIVE_LOW>; diff --git a/boards/shields/mikroe_mcp251xfd_click/shield.yml b/boards/shields/mikroe_mcp251xfd_click/shield.yml new file mode 100644 index 000000000000..a5216e43d69c --- /dev/null +++ b/boards/shields/mikroe_mcp251xfd_click/shield.yml @@ -0,0 +1,23 @@ +# SPDX-FileCopyrightText: Copyright (c) 2023 Andriy Gelman +# SPDX-FileCopyrightText: Copyright (c) 2026 Navimatix GmbH +# SPDX-FileCopyrightText: Copyright (c) 2026 TiaC Systems +# SPDX-License-Identifier: Apache-2.0 + +shields: + - name: mikroe_mcp2517fd_click + full_name: MikroElektronika MCP2517FD Click shield + vendor: mikroe + supported_features: + - can + + - name: mikroe_mcp2518fd_click + full_name: MikroElektronika MCP2518FD Click shield + vendor: mikroe + supported_features: + - can + + - name: mikroe_mcp251863_click + full_name: MikroElektronika MCP251863 Click shield + vendor: mikroe + supported_features: + - can diff --git a/boards/shields/mikroe_pressure_3_click/doc/index.rst b/boards/shields/mikroe_pressure_3_click/doc/index.rst index 591a6c63961c..d360353f2400 100644 --- a/boards/shields/mikroe_pressure_3_click/doc/index.rst +++ b/boards/shields/mikroe_pressure_3_click/doc/index.rst @@ -8,10 +8,10 @@ Overview `Pressure 3 Click`_ is a compact add-on board that contains a board-mount pressure sensor. -This board features the DPS310, a digital XENSIV |trade| barometric pressure sensor for portable +This board features the DPS310, a digital XENSIV™ barometric pressure sensor for portable devices from Infineon. It is a fast sensor with a typical measurement time of 27.6ms for Standard mode, down to 3.6ms in Low precision mode. The DPS310 has an operating range from 300 up to 1200hPa -with a relative accuracy of 0.06hPa and absolute accuracy of 1hPa. This Click board |trade| makes +with a relative accuracy of 0.06hPa and absolute accuracy of 1hPa. This Click board™ makes the perfect solution for developing portable weather station applications, indoor navigation, drone altitude control, and similar applications that rely on barometric pressure measurements. @@ -25,8 +25,8 @@ altitude control, and similar applications that rely on barometric pressure meas Requirements ************ -This shield can only be used with a board that provides a mikroBUS |trade| socket and defines a -``mikrobus_i2c`` node label for the mikroBUS |trade| I2C interface. See :ref:`shields` for more +This shield can only be used with a board that provides a mikroBUS™ socket and defines a +``mikrobus_i2c`` node label for the mikroBUS™ I2C interface. See :ref:`shields` for more details. Programming diff --git a/boards/shields/mikroe_proximity_9_click/doc/index.rst b/boards/shields/mikroe_proximity_9_click/doc/index.rst index effeb6419345..b219e7410f14 100644 --- a/boards/shields/mikroe_proximity_9_click/doc/index.rst +++ b/boards/shields/mikroe_proximity_9_click/doc/index.rst @@ -12,7 +12,7 @@ Filtron™ technology The 940nm IRED emitter, along with the low noise analog front end, and the PS/ALS photo-sensitive elements, is integrated on the VCNL4040 IC, ensuring very accurate and reliable measurements. The -proprietary Filtron |trade| technology provides response near to the human eye spectral response, +proprietary Filtron™ technology provides response near to the human eye spectral response, providing the background light cancellation. The programmable interrupt engine allows for the development of an optimized firmware, reducing the MCU workload and power consumption. @@ -26,8 +26,8 @@ development of an optimized firmware, reducing the MCU workload and power consum Requirements ************ -This shield can only be used with a board that provides a mikroBUS |trade| socket and defines a -``mikrobus_i2c`` node label for the mikroBUS |trade| I2C interface. See :ref:`shields` for more +This shield can only be used with a board that provides a mikroBUS™ socket and defines a +``mikrobus_i2c`` node label for the mikroBUS™ I2C interface. See :ref:`shields` for more details. Programming diff --git a/boards/shields/mikroe_weather_click/doc/index.rst b/boards/shields/mikroe_weather_click/doc/index.rst index 80143d80117f..57e41713405c 100644 --- a/boards/shields/mikroe_weather_click/doc/index.rst +++ b/boards/shields/mikroe_weather_click/doc/index.rst @@ -7,7 +7,7 @@ Overview ******** The MikroElektronika `Weather Click`_ features the `BME280`_ integrated -environmental sensor in a `mikroBUS`_ |trade| form factor. The sensor can +environmental sensor in a `mikroBUS™`_ form factor. The sensor can measure relative humidity, barometric pressure, and ambient temperature. .. figure:: weather-click.webp @@ -19,9 +19,9 @@ measure relative humidity, barometric pressure, and ambient temperature. Requirements ************ -This shield can only be used with a board that provides a mikroBUS |trade| -socket and defines a ``mikrobus_i2c`` node label for the mikroBUS |trade| I2C -interface or a ``mikrobus_spi`` node label for the mikroBUS |trade| SPI +This shield can only be used with a board that provides a mikroBUS™ +socket and defines a ``mikrobus_i2c`` node label for the mikroBUS™ I2C +interface or a ``mikrobus_spi`` node label for the mikroBUS™ SPI interface (see :ref:`shields` for more details). .. note:: @@ -63,5 +63,5 @@ example: .. _BME280 Datasheet: https://www.bosch-sensortec.com/media/boschsensortec/downloads/datasheets/bst-bme280-ds002.pdf -.. _mikroBUS: +.. _mikroBUS™: https://www.mikroe.com/mikrobus diff --git a/boards/shields/nrf7002eb/Kconfig.shield b/boards/shields/nrf7002eb/Kconfig.shield index e369cfe3de42..03c85ebdb2a5 100644 --- a/boards/shields/nrf7002eb/Kconfig.shield +++ b/boards/shields/nrf7002eb/Kconfig.shield @@ -6,3 +6,6 @@ config SHIELD_NRF7002EB config SHIELD_NRF7002EB_COEX def_bool $(shields_list_contains,nrf7002eb_coex) + +config SHIELD_NRF7002EB_COEX_SA + def_bool $(shields_list_contains,nrf7002eb_coex_sa) diff --git a/boards/shields/nrf7002eb/doc/index.rst b/boards/shields/nrf7002eb/doc/index.rst index 637f91ae21b4..7b7ce2108a91 100644 --- a/boards/shields/nrf7002eb/doc/index.rst +++ b/boards/shields/nrf7002eb/doc/index.rst @@ -51,6 +51,7 @@ edge-connector on some boards, like earlier revisions of the Thingy53 than v1.0. - ``nrf7002eb``: The default variant. - ``nrf7002eb_coex``: Variant which includes the COEX pins. +- ``nrf7002eb_coex_sa``: Variant which includes the COEX pins and is standalone. SR Co-existence *************** diff --git a/boards/shields/nrf7002eb/nrf7002eb_coex_sa.overlay b/boards/shields/nrf7002eb/nrf7002eb_coex_sa.overlay new file mode 100644 index 000000000000..e65c2f776a31 --- /dev/null +++ b/boards/shields/nrf7002eb/nrf7002eb_coex_sa.overlay @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + nrf_radio_coex: coex { + compatible = "nordic,nrf7002-coex"; + status = "okay"; + + status0-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + req-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + grant-gpios = <&gpio1 3 (GPIO_PULL_DOWN | GPIO_ACTIVE_LOW)>; + }; +}; + +&gpio1 { + status = "okay"; +}; + +&gpiote130 { + status = "okay"; +}; diff --git a/boards/shields/nrf7002eb/shield.yml b/boards/shields/nrf7002eb/shield.yml index 43ab36ad9951..f765158d0f7e 100644 --- a/boards/shields/nrf7002eb/shield.yml +++ b/boards/shields/nrf7002eb/shield.yml @@ -10,3 +10,9 @@ shields: vendor: nordic supported_features: - wifi + + - name: nrf7002eb_coex_sa + full_name: nRF7002 Evaluation Board Shield (SR Co-Existence) standalone + vendor: nordic + supported_features: + - wifi diff --git a/boards/shields/nxp_m2_wifi_bt/Kconfig.defconfig b/boards/shields/nxp_m2_wifi_bt/Kconfig.defconfig index 3efd1552628a..62b4afd7272b 100644 --- a/boards/shields/nxp_m2_wifi_bt/Kconfig.defconfig +++ b/boards/shields/nxp_m2_wifi_bt/Kconfig.defconfig @@ -124,6 +124,9 @@ endif # WIFI_NM_HOSTAPD_AP endif # WIFI +configdefault IMX_USDHC_DAT3_DETECT_RETRY + default 10 + endif # SHIELD_NXP_M2_2LL_WIFI_BT if (BT_NXP_IW416) || (BT_NXP_NW612) || (BT_NXP_IW610) || (NXP_IW416) || (NXP_IW61X) || (NXP_IW610) @@ -140,7 +143,7 @@ config MAIN_STACK_SIZE default 2560 configdefault FPU - default y if CPU_HAS_FPU + default y configdefault LIBLC3 default y if BT_NXP_NW612 && BT_AUDIO && FPU diff --git a/boards/shields/nxp_m2_wifi_bt/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay b/boards/shields/nxp_m2_wifi_bt/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay index 3471cb7b7d14..f56255c0d32c 100644 --- a/boards/shields/nxp_m2_wifi_bt/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay +++ b/boards/shields/nxp_m2_wifi_bt/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay @@ -1,5 +1,5 @@ /* - * Copyright 2025 NXP + * Copyright 2025-2026 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -23,6 +23,7 @@ m2_bt_module: m2_bt_module { sdio-reset-gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; w-disable-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>; + wakeup-bt-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; }; }; }; diff --git a/boards/shields/nxp_m2_wifi_bt/nxp_m2_1xk_wifi_bt.overlay b/boards/shields/nxp_m2_wifi_bt/nxp_m2_1xk_wifi_bt.overlay index 6129f6f5519b..ab5bbe980427 100644 --- a/boards/shields/nxp_m2_wifi_bt/nxp_m2_1xk_wifi_bt.overlay +++ b/boards/shields/nxp_m2_wifi_bt/nxp_m2_1xk_wifi_bt.overlay @@ -32,7 +32,6 @@ &m2_wifi_sdio { nxp_wifi { compatible = "nxp,wifi"; - oob-gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; wakeup-gpios = <&gpio1 26 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/boards/shields/nxp_m2_wifi_bt/nxp_m2_2el_wifi_bt.overlay b/boards/shields/nxp_m2_wifi_bt/nxp_m2_2el_wifi_bt.overlay index 5fb1406d636f..7f89234bd809 100644 --- a/boards/shields/nxp_m2_wifi_bt/nxp_m2_2el_wifi_bt.overlay +++ b/boards/shields/nxp_m2_wifi_bt/nxp_m2_2el_wifi_bt.overlay @@ -1,5 +1,5 @@ /* - * Copyright 2025 NXP + * Copyright 2025-2026 NXP * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/boards/shields/nxp_s32k5xx_mb/Kconfig.shield b/boards/shields/nxp_s32k5xx_mb/Kconfig.shield new file mode 100644 index 000000000000..b25dd7a135b3 --- /dev/null +++ b/boards/shields/nxp_s32k5xx_mb/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_NXP_S32K5XX_MB + def_bool $(shields_list_contains,nxp_s32k5xx_mb) diff --git a/boards/shields/nxp_s32k5xx_mb/doc/index.rst b/boards/shields/nxp_s32k5xx_mb/doc/index.rst new file mode 100644 index 000000000000..fcca15fed44d --- /dev/null +++ b/boards/shields/nxp_s32k5xx_mb/doc/index.rst @@ -0,0 +1,146 @@ +.. _nxp_s32k5xx_mb: + +NXP S32K5XX-MB Shield +##################### + +Overview +******** + +This Zephyr shield (NXP S32K5XX motherboard) increases the I/O connectivity available to the for :zephyr:board:`s32k5xxcvb` board. + +GPIO Pin Matrix +*************** + +Refer to the table below for the mapping between the Jxxx symbols in the schematic and the GPIO pin matrix in the board layout. + ++----+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+ +| | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | ++====+=======+=======+=======+=======+=======+=======+=======+=======+=======+=======+ +| A | | | | | | | J207 | J173 | J139 | J447 | ++----+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+ +| B | | | | | | | J208 | J174 | J140 | J105 | ++----+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+ +| C | J404 | J370 | J338 | J305 | J273 | J241 | J209 | J175 | J141 | J106 | ++----+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+ +| D | J405 | J371 | J339 | J306 | J274 | J242 | J210 | J176 | J142 | J107 | ++----+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+ +| E | J406 | J372 | J340 | J307 | J275 | J243 | J211 | J177 | J143 | J108 | ++----+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+ +| F | J407 | J373 | J341 | J308 | J276 | J244 | J212 | J178 | J144 | J109 | ++----+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+ +| G | J408 | J374 | J342 | J309 | J277 | J245 | J213 | J179 | J145 | J110 | ++----+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+ +| H | J409 | J375 | J343 | J310 | J278 | J246 | J214 | J180 | J146 | J111 | ++----+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+ +| I | J410 | J376 | J344 | J311 | J279 | J247 | J215 | J181 | J147 | J112 | ++----+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+ +| J | J411 | J377 | J345 | J312 | J280 | J248 | J216 | J182 | J148 | J113 | ++----+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+ +| K | J412 | J378 | J346 | J313 | J281 | J249 | J217 | J183 | J149 | J114 | ++----+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+ +| L | J413 | J379 | J347 | J314 | J282 | J250 | J218 | J184 | J150 | J115 | ++----+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+ +| M | J414 | J380 | J348 | J315 | J283 | J251 | J219 | J185 | J151 | J116 | ++----+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+ +| N | J415 | J381 | J349 | J316 | J284 | J252 | J220 | J186 | J152 | J117 | ++----+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+ +| O | J416 | J382 | J350 | J317 | J285 | J253 | J221 | J187 | J153 | J118 | ++----+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+ +| P | J417 | J383 | J351 | J318 | J286 | J254 | J222 | J188 | J154 | J119 | ++----+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+ +| Q | J418 | J384 | J352 | J319 | J287 | J255 | J223 | J189 | J155 | J120 | ++----+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+ +| R | J419 | J385 | J353 | J320 | J288 | J256 | J224 | J190 | J156 | J121 | ++----+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+ +| S | J420 | J386 | J354 | J321 | J289 | J257 | J225 | J191 | J157 | J122 | ++----+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+ +| T | J421 | J387 | J355 | J322 | J290 | J258 | J226 | J192 | J158 | J123 | ++----+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+ +| U | J422 | J388 | J356 | J323 | J291 | J259 | J227 | J193 | J159 | J124 | ++----+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+ +| V | J423 | J389 | J357 | J324 | J292 | J260 | J228 | J194 | J160 | J125 | ++----+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+ +| W | J424 | J390 | J358 | J325 | J293 | J261 | J229 | J195 | J161 | J126 | ++----+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+ +| X | J425 | J391 | J359 | J326 | J294 | J262 | J230 | J196 | J162 | J127 | ++----+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+ +| Y | J426 | J392 | J360 | J327 | J295 | J263 | J231 | J197 | J163 | J128 | ++----+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+ +| Z | J427 | J393 | J361 | J328 | J296 | J264 | J232 | J198 | J164 | J129 | ++----+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+ +| AA | J428 | J394 | J362 | J329 | J297 | J265 | J233 | J199 | J165 | J130 | ++----+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+ +| AB | J429 | J395 | J363 | J330 | J298 | J266 | J234 | J200 | J166 | J131 | ++----+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+ +| AC | J430 | J396 | J364 | J331 | J299 | J267 | J235 | J201 | J167 | J132 | ++----+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+ +| AD | J431 | J397 | J365 | J332 | J300 | J268 | J236 | J202 | J168 | J133 | ++----+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+ +| AE | J432 | J398 | J366 | J333 | J301 | J269 | J237 | J203 | J169 | J134 | ++----+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+ +| AF | J433 | J399 | J367 | J334 | J302 | J270 | J238 | J204 | J170 | J135 | ++----+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+ +| AG | J434 | J400 | J368 | J335 | J303 | J271 | J239 | J205 | J171 | J136 | ++----+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+ +| AH | J435 | J401 | J369 | J336 | J304 | J272 | J240 | J206 | J172 | J137 | ++----+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+ +| AI | J437 | J438 | J439 | J440 | J441 | J442 | J443 | J444 | J445 | J446 | ++----+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+ + +Set-up the Board +================ + +First, make sure the motherboard is properly connected to :zephyr:board:`s32k5xxcvb` board. + +A USB to serial converter (e.g., CH340) is required to visualize the serial output, connect it to the board as shown below: + + ++---------------------+------------------+ +| CH340 Converter Pin | GPIO Pin Matrix | ++=====================+==================+ +| TXD | O5 | ++---------------------+------------------+ +| RXD | P5 | ++---------------------+------------------+ +| GND | AI10 | ++---------------------+------------------+ + + +Run your favorite terminal program to listen for output. For example, using the cross-platform `pySerial miniterm`_ terminal: + +.. code-block:: console + + python -m serial.tools.miniterm 115200 + +Replace ```` with the port where the board can be found. For example, +under Linux, ``/dev/ttyUSB0``. + +Programming +*********** + +Below are the supported shields to be used with ``--shield