ram: Generate behavioral models

[rovinski]

Add an argument -write_behavioral_verilog [filename] to generate_ram to generate a simple behavioral model of the RAM. The model should be in pure Verilog (not SystemVerilog) for maximum compatibility. Ideally, it should just be a parameterized Verilog module with the parameters determined by the other arguments to generate_ram.

[rovinski]

Assigned to @tnguy19