diff --git a/bench-smem-m5-baseline.txt b/bench-smem-m5-baseline.txt new file mode 100644 index 00000000000..395b4a2fb51 --- /dev/null +++ b/bench-smem-m5-baseline.txt @@ -0,0 +1,362 @@ +=== SMEM M5 Benchmark: baseline === +Model: Qwen3.5-35B-A3B-Q8_0.gguf +Date: Sat Mar 28 21:45:40 CDT 2026 + +--- turbo3 @ short --- +ggml_metal_device_init: testing tensor API for f16 support +ggml_metal_library_compile_pipeline: compiling pipeline: base = 'dummy_kernel', name = 'dummy_kernel' +ggml_metal_library_compile_pipeline: loaded dummy_kernel 0x105cffcb0 | th_max = 1024 | th_width = 32 +ggml_metal_device_init: testing tensor API for bfloat support +ggml_metal_library_compile_pipeline: compiling pipeline: base = 'dummy_kernel', name = 'dummy_kernel' +ggml_metal_library_compile_pipeline: loaded dummy_kernel 0x105cfeb30 | th_max = 1024 | th_width = 32 +ggml_metal_library_init: using embedded metal library +ggml_metal_library_init: turbo3 sparse V dequant enabled +ggml_metal_library_init: loaded in 6.440 sec +ggml_metal_rsets_init: creating a residency set collection (keep_alive = 180 s) +ggml_metal_device_init: GPU name: MTL0 +ggml_metal_device_init: GPU family: MTLGPUFamilyApple10 (1010) +ggml_metal_device_init: GPU family: MTLGPUFamilyCommon3 (3003) +ggml_metal_device_init: GPU family: MTLGPUFamilyMetal4 (5002) +ggml_metal_device_init: simdgroup reduction = true +ggml_metal_device_init: simdgroup matrix mul. = true +ggml_metal_device_init: has unified memory = true +ggml_metal_device_init: has bfloat = true +ggml_metal_device_init: has tensor = true +ggml_metal_device_init: use residency sets = true +ggml_metal_device_init: use shared buffers = true +ggml_metal_device_init: recommendedMaxWorkingSetSize = 115448.73 MB +| model | size | params | backend | threads | type_k | type_v | fa | test | t/s | +| ------------------------------ | ---------: | ---------: | ---------- | ------: | -----: | -----: | -: | --------------: | -------------------: | +| qwen35moe 35B.A3B Q8_0 | 34.36 GiB | 34.66 B | MTL,BLAS | 1 | turbo3 | turbo3 | 1 | tg128 | 78.47 ± 0.56 | + +build: 13afec1 (178) + +--- turbo3 @ 8192 --- +ggml_metal_device_init: testing tensor API for f16 support +ggml_metal_library_compile_pipeline: compiling pipeline: base = 'dummy_kernel', name = 'dummy_kernel' +ggml_metal_library_compile_pipeline: loaded dummy_kernel 0x1040cfae0 | th_max = 1024 | th_width = 32 +ggml_metal_device_init: testing tensor API for bfloat support +ggml_metal_library_compile_pipeline: compiling pipeline: base = 'dummy_kernel', name = 'dummy_kernel' +ggml_metal_library_compile_pipeline: loaded dummy_kernel 0x1040ce960 | th_max = 1024 | th_width = 32 +ggml_metal_library_init: using embedded metal library +ggml_metal_library_init: turbo3 sparse V dequant enabled +ggml_metal_library_init: loaded in 0.010 sec +ggml_metal_rsets_init: creating a residency set collection (keep_alive = 180 s) +ggml_metal_device_init: GPU name: MTL0 +ggml_metal_device_init: GPU family: MTLGPUFamilyApple10 (1010) +ggml_metal_device_init: GPU family: MTLGPUFamilyCommon3 (3003) +ggml_metal_device_init: GPU family: MTLGPUFamilyMetal4 (5002) +ggml_metal_device_init: simdgroup reduction = true +ggml_metal_device_init: simdgroup matrix mul. = true +ggml_metal_device_init: has unified memory = true +ggml_metal_device_init: has bfloat = true +ggml_metal_device_init: has tensor = true +ggml_metal_device_init: use residency sets = true +ggml_metal_device_init: use shared buffers = true +ggml_metal_device_init: recommendedMaxWorkingSetSize = 115448.73 MB +| model | size | params | backend | threads | type_k | type_v | fa | test | t/s | +| ------------------------------ | ---------: | ---------: | ---------- | ------: | -----: | -----: | -: | --------------: | -------------------: | +| qwen35moe 35B.A3B Q8_0 | 34.36 GiB | 34.66 B | MTL,BLAS | 1 | turbo3 | turbo3 | 1 | pp8192 | 2144.16 ± 30.18 | +| qwen35moe 35B.A3B Q8_0 | 34.36 GiB | 34.66 B | MTL,BLAS | 1 | turbo3 | turbo3 | 1 | tg128 | 78.90 ± 0.24 | + +build: 13afec1 (178) + +--- turbo3 @ 16384 --- +ggml_metal_device_init: testing tensor API for f16 support +ggml_metal_library_compile_pipeline: compiling pipeline: base = 'dummy_kernel', name = 'dummy_kernel' +ggml_metal_library_compile_pipeline: loaded dummy_kernel 0x10500fc00 | th_max = 1024 | th_width = 32 +ggml_metal_device_init: testing tensor API for bfloat support +ggml_metal_library_compile_pipeline: compiling pipeline: base = 'dummy_kernel', name = 'dummy_kernel' +ggml_metal_library_compile_pipeline: loaded dummy_kernel 0x10500ea80 | th_max = 1024 | th_width = 32 +ggml_metal_library_init: using embedded metal library +ggml_metal_library_init: turbo3 sparse V dequant enabled +ggml_metal_library_init: loaded in 0.008 sec +ggml_metal_rsets_init: creating a residency set collection (keep_alive = 180 s) +ggml_metal_device_init: GPU name: MTL0 +ggml_metal_device_init: GPU family: MTLGPUFamilyApple10 (1010) +ggml_metal_device_init: GPU family: MTLGPUFamilyCommon3 (3003) +ggml_metal_device_init: GPU family: MTLGPUFamilyMetal4 (5002) +ggml_metal_device_init: simdgroup reduction = true +ggml_metal_device_init: simdgroup matrix mul. = true +ggml_metal_device_init: has unified memory = true +ggml_metal_device_init: has bfloat = true +ggml_metal_device_init: has tensor = true +ggml_metal_device_init: use residency sets = true +ggml_metal_device_init: use shared buffers = true +ggml_metal_device_init: recommendedMaxWorkingSetSize = 115448.73 MB +| model | size | params | backend | threads | type_k | type_v | fa | test | t/s | +| ------------------------------ | ---------: | ---------: | ---------- | ------: | -----: | -----: | -: | --------------: | -------------------: | +| qwen35moe 35B.A3B Q8_0 | 34.36 GiB | 34.66 B | MTL,BLAS | 1 | turbo3 | turbo3 | 1 | pp16384 | 1704.41 ± 21.63 | +| qwen35moe 35B.A3B Q8_0 | 34.36 GiB | 34.66 B | MTL,BLAS | 1 | turbo3 | turbo3 | 1 | tg128 | 78.64 ± 0.44 | + +build: 13afec1 (178) + +--- turbo3 @ 32768 --- +ggml_metal_device_init: testing tensor API for f16 support +ggml_metal_library_compile_pipeline: compiling pipeline: base = 'dummy_kernel', name = 'dummy_kernel' +ggml_metal_library_compile_pipeline: loaded dummy_kernel 0x101c8fb00 | th_max = 1024 | th_width = 32 +ggml_metal_device_init: testing tensor API for bfloat support +ggml_metal_library_compile_pipeline: compiling pipeline: base = 'dummy_kernel', name = 'dummy_kernel' +ggml_metal_library_compile_pipeline: loaded dummy_kernel 0x101c8e980 | th_max = 1024 | th_width = 32 +ggml_metal_library_init: using embedded metal library +ggml_metal_library_init: turbo3 sparse V dequant enabled +ggml_metal_library_init: loaded in 0.013 sec +ggml_metal_rsets_init: creating a residency set collection (keep_alive = 180 s) +ggml_metal_device_init: GPU name: MTL0 +ggml_metal_device_init: GPU family: MTLGPUFamilyApple10 (1010) +ggml_metal_device_init: GPU family: MTLGPUFamilyCommon3 (3003) +ggml_metal_device_init: GPU family: MTLGPUFamilyMetal4 (5002) +ggml_metal_device_init: simdgroup reduction = true +ggml_metal_device_init: simdgroup matrix mul. = true +ggml_metal_device_init: has unified memory = true +ggml_metal_device_init: has bfloat = true +ggml_metal_device_init: has tensor = true +ggml_metal_device_init: use residency sets = true +ggml_metal_device_init: use shared buffers = true +ggml_metal_device_init: recommendedMaxWorkingSetSize = 115448.73 MB +| model | size | params | backend | threads | type_k | type_v | fa | test | t/s | +| ------------------------------ | ---------: | ---------: | ---------- | ------: | -----: | -----: | -: | --------------: | -------------------: | +| qwen35moe 35B.A3B Q8_0 | 34.36 GiB | 34.66 B | MTL,BLAS | 1 | turbo3 | turbo3 | 1 | pp32768 | 1238.85 ± 6.06 | +| qwen35moe 35B.A3B Q8_0 | 34.36 GiB | 34.66 B | MTL,BLAS | 1 | turbo3 | turbo3 | 1 | tg128 | 78.17 ± 0.69 | + +build: 13afec1 (178) + +--- turbo4 @ short --- +ggml_metal_device_init: testing tensor API for f16 support +ggml_metal_library_compile_pipeline: compiling pipeline: base = 'dummy_kernel', name = 'dummy_kernel' +ggml_metal_library_compile_pipeline: loaded dummy_kernel 0x103c17f70 | th_max = 1024 | th_width = 32 +ggml_metal_device_init: testing tensor API for bfloat support +ggml_metal_library_compile_pipeline: compiling pipeline: base = 'dummy_kernel', name = 'dummy_kernel' +ggml_metal_library_compile_pipeline: loaded dummy_kernel 0x103c16df0 | th_max = 1024 | th_width = 32 +ggml_metal_library_init: using embedded metal library +ggml_metal_library_init: turbo3 sparse V dequant enabled +ggml_metal_library_init: loaded in 0.008 sec +ggml_metal_rsets_init: creating a residency set collection (keep_alive = 180 s) +ggml_metal_device_init: GPU name: MTL0 +ggml_metal_device_init: GPU family: MTLGPUFamilyApple10 (1010) +ggml_metal_device_init: GPU family: MTLGPUFamilyCommon3 (3003) +ggml_metal_device_init: GPU family: MTLGPUFamilyMetal4 (5002) +ggml_metal_device_init: simdgroup reduction = true +ggml_metal_device_init: simdgroup matrix mul. = true +ggml_metal_device_init: has unified memory = true +ggml_metal_device_init: has bfloat = true +ggml_metal_device_init: has tensor = true +ggml_metal_device_init: use residency sets = true +ggml_metal_device_init: use shared buffers = true +ggml_metal_device_init: recommendedMaxWorkingSetSize = 115448.73 MB +| model | size | params | backend | threads | type_k | type_v | fa | test | t/s | +| ------------------------------ | ---------: | ---------: | ---------- | ------: | -----: | -----: | -: | --------------: | -------------------: | +| qwen35moe 35B.A3B Q8_0 | 34.36 GiB | 34.66 B | MTL,BLAS | 1 | turbo4 | turbo4 | 1 | tg128 | 80.40 ± 0.72 | + +build: 13afec1 (178) + +--- turbo4 @ 8192 --- +ggml_metal_device_init: testing tensor API for f16 support +ggml_metal_library_compile_pipeline: compiling pipeline: base = 'dummy_kernel', name = 'dummy_kernel' +ggml_metal_library_compile_pipeline: loaded dummy_kernel 0x103e57d30 | th_max = 1024 | th_width = 32 +ggml_metal_device_init: testing tensor API for bfloat support +ggml_metal_library_compile_pipeline: compiling pipeline: base = 'dummy_kernel', name = 'dummy_kernel' +ggml_metal_library_compile_pipeline: loaded dummy_kernel 0x103e56bb0 | th_max = 1024 | th_width = 32 +ggml_metal_library_init: using embedded metal library +ggml_metal_library_init: turbo3 sparse V dequant enabled +ggml_metal_library_init: loaded in 0.010 sec +ggml_metal_rsets_init: creating a residency set collection (keep_alive = 180 s) +ggml_metal_device_init: GPU name: MTL0 +ggml_metal_device_init: GPU family: MTLGPUFamilyApple10 (1010) +ggml_metal_device_init: GPU family: MTLGPUFamilyCommon3 (3003) +ggml_metal_device_init: GPU family: MTLGPUFamilyMetal4 (5002) +ggml_metal_device_init: simdgroup reduction = true +ggml_metal_device_init: simdgroup matrix mul. = true +ggml_metal_device_init: has unified memory = true +ggml_metal_device_init: has bfloat = true +ggml_metal_device_init: has tensor = true +ggml_metal_device_init: use residency sets = true +ggml_metal_device_init: use shared buffers = true +ggml_metal_device_init: recommendedMaxWorkingSetSize = 115448.73 MB +| model | size | params | backend | threads | type_k | type_v | fa | test | t/s | +| ------------------------------ | ---------: | ---------: | ---------- | ------: | -----: | -----: | -: | --------------: | -------------------: | +| qwen35moe 35B.A3B Q8_0 | 34.36 GiB | 34.66 B | MTL,BLAS | 1 | turbo4 | turbo4 | 1 | pp8192 | 2048.90 ± 43.42 | +| qwen35moe 35B.A3B Q8_0 | 34.36 GiB | 34.66 B | MTL,BLAS | 1 | turbo4 | turbo4 | 1 | tg128 | 79.84 ± 0.95 | + +build: 13afec1 (178) + +--- turbo4 @ 16384 --- +ggml_metal_device_init: testing tensor API for f16 support +ggml_metal_library_compile_pipeline: compiling pipeline: base = 'dummy_kernel', name = 'dummy_kernel' +ggml_metal_library_compile_pipeline: loaded dummy_kernel 0x1060bf740 | th_max = 1024 | th_width = 32 +ggml_metal_device_init: testing tensor API for bfloat support +ggml_metal_library_compile_pipeline: compiling pipeline: base = 'dummy_kernel', name = 'dummy_kernel' +ggml_metal_library_compile_pipeline: loaded dummy_kernel 0x1060be5c0 | th_max = 1024 | th_width = 32 +ggml_metal_library_init: using embedded metal library +ggml_metal_library_init: turbo3 sparse V dequant enabled +ggml_metal_library_init: loaded in 0.009 sec +ggml_metal_rsets_init: creating a residency set collection (keep_alive = 180 s) +ggml_metal_device_init: GPU name: MTL0 +ggml_metal_device_init: GPU family: MTLGPUFamilyApple10 (1010) +ggml_metal_device_init: GPU family: MTLGPUFamilyCommon3 (3003) +ggml_metal_device_init: GPU family: MTLGPUFamilyMetal4 (5002) +ggml_metal_device_init: simdgroup reduction = true +ggml_metal_device_init: simdgroup matrix mul. = true +ggml_metal_device_init: has unified memory = true +ggml_metal_device_init: has bfloat = true +ggml_metal_device_init: has tensor = true +ggml_metal_device_init: use residency sets = true +ggml_metal_device_init: use shared buffers = true +ggml_metal_device_init: recommendedMaxWorkingSetSize = 115448.73 MB +| model | size | params | backend | threads | type_k | type_v | fa | test | t/s | +| ------------------------------ | ---------: | ---------: | ---------- | ------: | -----: | -----: | -: | --------------: | -------------------: | +| qwen35moe 35B.A3B Q8_0 | 34.36 GiB | 34.66 B | MTL,BLAS | 1 | turbo4 | turbo4 | 1 | pp16384 | 1605.18 ± 20.70 | +| qwen35moe 35B.A3B Q8_0 | 34.36 GiB | 34.66 B | MTL,BLAS | 1 | turbo4 | turbo4 | 1 | tg128 | 79.45 ± 1.55 | + +build: 13afec1 (178) + +--- turbo4 @ 32768 --- +ggml_metal_device_init: testing tensor API for f16 support +ggml_metal_library_compile_pipeline: compiling pipeline: base = 'dummy_kernel', name = 'dummy_kernel' +ggml_metal_library_compile_pipeline: loaded dummy_kernel 0x1040ef870 | th_max = 1024 | th_width = 32 +ggml_metal_device_init: testing tensor API for bfloat support +ggml_metal_library_compile_pipeline: compiling pipeline: base = 'dummy_kernel', name = 'dummy_kernel' +ggml_metal_library_compile_pipeline: loaded dummy_kernel 0x1040ee6f0 | th_max = 1024 | th_width = 32 +ggml_metal_library_init: using embedded metal library +ggml_metal_library_init: turbo3 sparse V dequant enabled +ggml_metal_library_init: loaded in 0.010 sec +ggml_metal_rsets_init: creating a residency set collection (keep_alive = 180 s) +ggml_metal_device_init: GPU name: MTL0 +ggml_metal_device_init: GPU family: MTLGPUFamilyApple10 (1010) +ggml_metal_device_init: GPU family: MTLGPUFamilyCommon3 (3003) +ggml_metal_device_init: GPU family: MTLGPUFamilyMetal4 (5002) +ggml_metal_device_init: simdgroup reduction = true +ggml_metal_device_init: simdgroup matrix mul. = true +ggml_metal_device_init: has unified memory = true +ggml_metal_device_init: has bfloat = true +ggml_metal_device_init: has tensor = true +ggml_metal_device_init: use residency sets = true +ggml_metal_device_init: use shared buffers = true +ggml_metal_device_init: recommendedMaxWorkingSetSize = 115448.73 MB +| model | size | params | backend | threads | type_k | type_v | fa | test | t/s | +| ------------------------------ | ---------: | ---------: | ---------- | ------: | -----: | -----: | -: | --------------: | -------------------: | +| qwen35moe 35B.A3B Q8_0 | 34.36 GiB | 34.66 B | MTL,BLAS | 1 | turbo4 | turbo4 | 1 | pp32768 | 1157.30 ± 8.01 | +| qwen35moe 35B.A3B Q8_0 | 34.36 GiB | 34.66 B | MTL,BLAS | 1 | turbo4 | turbo4 | 1 | tg128 | 80.64 ± 0.72 | + +build: 13afec1 (178) + +--- q8_0 @ short --- +ggml_metal_device_init: testing tensor API for f16 support +ggml_metal_library_compile_pipeline: compiling pipeline: base = 'dummy_kernel', name = 'dummy_kernel' +ggml_metal_library_compile_pipeline: loaded dummy_kernel 0x1055e78c0 | th_max = 1024 | th_width = 32 +ggml_metal_device_init: testing tensor API for bfloat support +ggml_metal_library_compile_pipeline: compiling pipeline: base = 'dummy_kernel', name = 'dummy_kernel' +ggml_metal_library_compile_pipeline: loaded dummy_kernel 0x1055e6740 | th_max = 1024 | th_width = 32 +ggml_metal_library_init: using embedded metal library +ggml_metal_library_init: turbo3 sparse V dequant enabled +ggml_metal_library_init: loaded in 0.008 sec +ggml_metal_rsets_init: creating a residency set collection (keep_alive = 180 s) +ggml_metal_device_init: GPU name: MTL0 +ggml_metal_device_init: GPU family: MTLGPUFamilyApple10 (1010) +ggml_metal_device_init: GPU family: MTLGPUFamilyCommon3 (3003) +ggml_metal_device_init: GPU family: MTLGPUFamilyMetal4 (5002) +ggml_metal_device_init: simdgroup reduction = true +ggml_metal_device_init: simdgroup matrix mul. = true +ggml_metal_device_init: has unified memory = true +ggml_metal_device_init: has bfloat = true +ggml_metal_device_init: has tensor = true +ggml_metal_device_init: use residency sets = true +ggml_metal_device_init: use shared buffers = true +ggml_metal_device_init: recommendedMaxWorkingSetSize = 115448.73 MB +| model | size | params | backend | threads | type_k | type_v | fa | test | t/s | +| ------------------------------ | ---------: | ---------: | ---------- | ------: | -----: | -----: | -: | --------------: | -------------------: | +| qwen35moe 35B.A3B Q8_0 | 34.36 GiB | 34.66 B | MTL,BLAS | 1 | q8_0 | q8_0 | 1 | tg128 | 85.48 ± 1.34 | + +build: 13afec1 (178) + +--- q8_0 @ 8192 --- +ggml_metal_device_init: testing tensor API for f16 support +ggml_metal_library_compile_pipeline: compiling pipeline: base = 'dummy_kernel', name = 'dummy_kernel' +ggml_metal_library_compile_pipeline: loaded dummy_kernel 0x105ac8540 | th_max = 1024 | th_width = 32 +ggml_metal_device_init: testing tensor API for bfloat support +ggml_metal_library_compile_pipeline: compiling pipeline: base = 'dummy_kernel', name = 'dummy_kernel' +ggml_metal_library_compile_pipeline: loaded dummy_kernel 0x105ac73c0 | th_max = 1024 | th_width = 32 +ggml_metal_library_init: using embedded metal library +ggml_metal_library_init: turbo3 sparse V dequant enabled +ggml_metal_library_init: loaded in 0.010 sec +ggml_metal_rsets_init: creating a residency set collection (keep_alive = 180 s) +ggml_metal_device_init: GPU name: MTL0 +ggml_metal_device_init: GPU family: MTLGPUFamilyApple10 (1010) +ggml_metal_device_init: GPU family: MTLGPUFamilyCommon3 (3003) +ggml_metal_device_init: GPU family: MTLGPUFamilyMetal4 (5002) +ggml_metal_device_init: simdgroup reduction = true +ggml_metal_device_init: simdgroup matrix mul. = true +ggml_metal_device_init: has unified memory = true +ggml_metal_device_init: has bfloat = true +ggml_metal_device_init: has tensor = true +ggml_metal_device_init: use residency sets = true +ggml_metal_device_init: use shared buffers = true +ggml_metal_device_init: recommendedMaxWorkingSetSize = 115448.73 MB +| model | size | params | backend | threads | type_k | type_v | fa | test | t/s | +| ------------------------------ | ---------: | ---------: | ---------- | ------: | -----: | -----: | -: | --------------: | -------------------: | +| qwen35moe 35B.A3B Q8_0 | 34.36 GiB | 34.66 B | MTL,BLAS | 1 | q8_0 | q8_0 | 1 | pp8192 | 2106.47 ± 64.66 | +| qwen35moe 35B.A3B Q8_0 | 34.36 GiB | 34.66 B | MTL,BLAS | 1 | q8_0 | q8_0 | 1 | tg128 | 76.72 ± 2.13 | + +build: 13afec1 (178) + +--- q8_0 @ 16384 --- +ggml_metal_device_init: testing tensor API for f16 support +ggml_metal_library_compile_pipeline: compiling pipeline: base = 'dummy_kernel', name = 'dummy_kernel' +ggml_metal_library_compile_pipeline: loaded dummy_kernel 0x103fefa70 | th_max = 1024 | th_width = 32 +ggml_metal_device_init: testing tensor API for bfloat support +ggml_metal_library_compile_pipeline: compiling pipeline: base = 'dummy_kernel', name = 'dummy_kernel' +ggml_metal_library_compile_pipeline: loaded dummy_kernel 0x103fee8f0 | th_max = 1024 | th_width = 32 +ggml_metal_library_init: using embedded metal library +ggml_metal_library_init: turbo3 sparse V dequant enabled +ggml_metal_library_init: loaded in 0.008 sec +ggml_metal_rsets_init: creating a residency set collection (keep_alive = 180 s) +ggml_metal_device_init: GPU name: MTL0 +ggml_metal_device_init: GPU family: MTLGPUFamilyApple10 (1010) +ggml_metal_device_init: GPU family: MTLGPUFamilyCommon3 (3003) +ggml_metal_device_init: GPU family: MTLGPUFamilyMetal4 (5002) +ggml_metal_device_init: simdgroup reduction = true +ggml_metal_device_init: simdgroup matrix mul. = true +ggml_metal_device_init: has unified memory = true +ggml_metal_device_init: has bfloat = true +ggml_metal_device_init: has tensor = true +ggml_metal_device_init: use residency sets = true +ggml_metal_device_init: use shared buffers = true +ggml_metal_device_init: recommendedMaxWorkingSetSize = 115448.73 MB +| model | size | params | backend | threads | type_k | type_v | fa | test | t/s | +| ------------------------------ | ---------: | ---------: | ---------- | ------: | -----: | -----: | -: | --------------: | -------------------: | +| qwen35moe 35B.A3B Q8_0 | 34.36 GiB | 34.66 B | MTL,BLAS | 1 | q8_0 | q8_0 | 1 | pp16384 | 1723.71 ± 28.56 | +| qwen35moe 35B.A3B Q8_0 | 34.36 GiB | 34.66 B | MTL,BLAS | 1 | q8_0 | q8_0 | 1 | tg128 | 78.09 ± 3.70 | + +build: 13afec1 (178) + +--- q8_0 @ 32768 --- +ggml_metal_device_init: testing tensor API for f16 support +ggml_metal_library_compile_pipeline: compiling pipeline: base = 'dummy_kernel', name = 'dummy_kernel' +ggml_metal_library_compile_pipeline: loaded dummy_kernel 0x1035f7b10 | th_max = 1024 | th_width = 32 +ggml_metal_device_init: testing tensor API for bfloat support +ggml_metal_library_compile_pipeline: compiling pipeline: base = 'dummy_kernel', name = 'dummy_kernel' +ggml_metal_library_compile_pipeline: loaded dummy_kernel 0x1035f6990 | th_max = 1024 | th_width = 32 +ggml_metal_library_init: using embedded metal library +ggml_metal_library_init: turbo3 sparse V dequant enabled +ggml_metal_library_init: loaded in 0.008 sec +ggml_metal_rsets_init: creating a residency set collection (keep_alive = 180 s) +ggml_metal_device_init: GPU name: MTL0 +ggml_metal_device_init: GPU family: MTLGPUFamilyApple10 (1010) +ggml_metal_device_init: GPU family: MTLGPUFamilyCommon3 (3003) +ggml_metal_device_init: GPU family: MTLGPUFamilyMetal4 (5002) +ggml_metal_device_init: simdgroup reduction = true +ggml_metal_device_init: simdgroup matrix mul. = true +ggml_metal_device_init: has unified memory = true +ggml_metal_device_init: has bfloat = true +ggml_metal_device_init: has tensor = true +ggml_metal_device_init: use residency sets = true +ggml_metal_device_init: use shared buffers = true +ggml_metal_device_init: recommendedMaxWorkingSetSize = 115448.73 MB +| model | size | params | backend | threads | type_k | type_v | fa | test | t/s | +| ------------------------------ | ---------: | ---------: | ---------- | ------: | -----: | -----: | -: | --------------: | -------------------: | +| qwen35moe 35B.A3B Q8_0 | 34.36 GiB | 34.66 B | MTL,BLAS | 1 | q8_0 | q8_0 | 1 | pp32768 | 1216.99 ± 28.64 | +| qwen35moe 35B.A3B Q8_0 | 34.36 GiB | 34.66 B | MTL,BLAS | 1 | q8_0 | q8_0 | 1 | tg128 | 86.83 ± 0.34 | + +build: 13afec1 (178) + +=== Done: baseline === diff --git a/bench-smem-m5-smem.txt b/bench-smem-m5-smem.txt new file mode 100644 index 00000000000..106696ec7ce --- /dev/null +++ b/bench-smem-m5-smem.txt @@ -0,0 +1,413 @@ +=== SMEM M5 Benchmark: smem === +Model: Qwen3.5-35B-A3B-Q8_0.gguf +Date: Sat Mar 28 22:02:19 CDT 2026 + +--- turbo3 @ short --- +ggml_metal_device_init: testing tensor API for f16 support +ggml_metal_library_compile_pipeline: compiling pipeline: base = 'dummy_kernel', name = 'dummy_kernel' +ggml_metal_library_compile_pipeline: loaded dummy_kernel 0x104fbb670 | th_max = 1024 | th_width = 32 +ggml_metal_device_init: testing tensor API for bfloat support +ggml_metal_library_compile_pipeline: compiling pipeline: base = 'dummy_kernel', name = 'dummy_kernel' +ggml_metal_library_compile_pipeline: loaded dummy_kernel 0x104fbb5f0 | th_max = 1024 | th_width = 32 +ggml_metal_library_init: using embedded metal library +ggml_metal_library_init: turbo3 sparse V dequant enabled +ggml_metal_library_init: loaded in 7.366 sec +ggml_metal_rsets_init: creating a residency set collection (keep_alive = 180 s) +ggml_metal_device_init: GPU name: MTL0 +ggml_metal_device_init: GPU family: MTLGPUFamilyApple10 (1010) +ggml_metal_device_init: GPU family: MTLGPUFamilyCommon3 (3003) +ggml_metal_device_init: GPU family: MTLGPUFamilyMetal4 (5002) +ggml_metal_device_init: simdgroup reduction = true +ggml_metal_device_init: simdgroup matrix mul. = true +ggml_metal_device_init: has unified memory = true +ggml_metal_device_init: has bfloat = true +ggml_metal_device_init: has tensor = true +ggml_metal_device_init: use residency sets = true +ggml_metal_device_init: use shared buffers = true +ggml_metal_device_init: recommendedMaxWorkingSetSize = 115448.73 MB +| model | size | params | backend | threads | type_k | type_v | fa | test | t/s | +| ------------------------------ | ---------: | ---------: | ---------- | ------: | -----: | -----: | -: | --------------: | -------------------: | +| qwen35moe 35B.A3B Q8_0 | 34.36 GiB | 34.66 B | MTL,BLAS | 1 | turbo3 | turbo3 | 1 | tg128 | 18.39 ± 0.76 | + +build: 13afec1 (178) + +--- turbo3 @ 8192 --- +ggml_metal_device_init: testing tensor API for f16 support +ggml_metal_library_compile_pipeline: compiling pipeline: base = 'dummy_kernel', name = 'dummy_kernel' +ggml_metal_library_compile_pipeline: loaded dummy_kernel 0x101ee3e50 | th_max = 1024 | th_width = 32 +ggml_metal_device_init: testing tensor API for bfloat support +ggml_metal_library_compile_pipeline: compiling pipeline: base = 'dummy_kernel', name = 'dummy_kernel' +ggml_metal_library_compile_pipeline: loaded dummy_kernel 0x101ee3dd0 | th_max = 1024 | th_width = 32 +ggml_metal_library_init: using embedded metal library +ggml_metal_library_init: turbo3 sparse V dequant enabled +ggml_metal_library_init: loaded in 0.009 sec +ggml_metal_rsets_init: creating a residency set collection (keep_alive = 180 s) +ggml_metal_device_init: GPU name: MTL0 +ggml_metal_device_init: GPU family: MTLGPUFamilyApple10 (1010) +ggml_metal_device_init: GPU family: MTLGPUFamilyCommon3 (3003) +ggml_metal_device_init: GPU family: MTLGPUFamilyMetal4 (5002) +ggml_metal_device_init: simdgroup reduction = true +ggml_metal_device_init: simdgroup matrix mul. = true +ggml_metal_device_init: has unified memory = true +ggml_metal_device_init: has bfloat = true +ggml_metal_device_init: has tensor = true +ggml_metal_device_init: use residency sets = true +ggml_metal_device_init: use shared buffers = true +ggml_metal_device_init: recommendedMaxWorkingSetSize = 115448.73 MB +| model | size | params | backend | threads | type_k | type_v | fa | test | t/s | +| ------------------------------ | ---------: | ---------: | ---------- | ------: | -----: | -----: | -: | --------------: | -------------------: | +| qwen35moe 35B.A3B Q8_0 | 34.36 GiB | 34.66 B | MTL,BLAS | 1 | turbo3 | turbo3 | 1 | pp16384 | 1337.26 ± 261.92 | +| model | size | params | backend | threads | type_k | type_v | fa | test | t/s | +| ------------------------------ | ---------: | ---------: | ---------- | ------: | -----: | -----: | -: | --------------: | -------------------: | +| qwen35moe 35B.A3B Q8_0 | 34.36 GiB | 34.66 B | MTL,BLAS | 1 | turbo3 | turbo3 | 1 | pp8192 | 1442.03 ± 393.22 | +| qwen35moe 35B.A3B Q8_0 | 34.36 GiB | 34.66 B | MTL,BLAS | 1 | turbo3 | turbo3 | 1 | tg128 | 40.38 ± 18.10 | + +build: 13afec1 (178) + +--- turbo3 @ 32768 --- +ggml_metal_device_init: testing tensor API for f16 support +ggml_metal_library_compile_pipeline: compiling pipeline: base = 'dummy_kernel', name = 'dummy_kernel' +ggml_metal_library_compile_pipeline: loaded dummy_kernel 0x105a3f890 | th_max = 1024 | th_width = 32 +ggml_metal_device_init: testing tensor API for bfloat support +ggml_metal_library_compile_pipeline: compiling pipeline: base = 'dummy_kernel', name = 'dummy_kernel' +ggml_metal_library_compile_pipeline: loaded dummy_kernel 0x105a3e710 | th_max = 1024 | th_width = 32 +ggml_metal_library_init: using embedded metal library +ggml_metal_library_init: turbo3 sparse V dequant enabled +ggml_metal_library_init: turbo3/4 SMEM pre-dequant enabled +ggml_metal_library_init: loaded in 0.010 sec +ggml_metal_rsets_init: creating a residency set collection (keep_alive = 180 s) +ggml_metal_device_init: GPU name: MTL0 +ggml_metal_device_init: GPU family: MTLGPUFamilyApple10 (1010) +ggml_metal_device_init: GPU family: MTLGPUFamilyCommon3 (3003) +ggml_metal_device_init: GPU family: MTLGPUFamilyMetal4 (5002) +ggml_metal_device_init: simdgroup reduction = true +ggml_metal_device_init: simdgroup matrix mul. = true +ggml_metal_device_init: has unified memory = true +ggml_metal_device_init: has bfloat = true +ggml_metal_device_init: has tensor = true +ggml_metal_device_init: use residency sets = true +ggml_metal_device_init: use shared buffers = true +ggml_metal_device_init: recommendedMaxWorkingSetSize = 115448.73 MB +| qwen35moe 35B.A3B Q8_0 | 34.36 GiB | 34.66 B | MTL,BLAS | 1 | turbo3 | turbo3 | 1 | tg128 | 58.20 ± 8.75 | + +build: 13afec1 (178) + +--- turbo3 @ 16384 --- +ggml_metal_device_init: testing tensor API for f16 support +ggml_metal_library_compile_pipeline: compiling pipeline: base = 'dummy_kernel', name = 'dummy_kernel' +ggml_metal_library_compile_pipeline: loaded dummy_kernel 0x103d7b200 | th_max = 1024 | th_width = 32 +ggml_metal_device_init: testing tensor API for bfloat support +ggml_metal_library_compile_pipeline: compiling pipeline: base = 'dummy_kernel', name = 'dummy_kernel' +ggml_metal_library_compile_pipeline: loaded dummy_kernel 0x103d7b180 | th_max = 1024 | th_width = 32 +ggml_metal_library_init: using embedded metal library +ggml_metal_library_init: turbo3 sparse V dequant enabled +ggml_metal_library_init: loaded in 0.009 sec +ggml_metal_rsets_init: creating a residency set collection (keep_alive = 180 s) +ggml_metal_device_init: GPU name: MTL0 +ggml_metal_device_init: GPU family: MTLGPUFamilyApple10 (1010) +ggml_metal_device_init: GPU family: MTLGPUFamilyCommon3 (3003) +ggml_metal_device_init: GPU family: MTLGPUFamilyMetal4 (5002) +ggml_metal_device_init: simdgroup reduction = true +ggml_metal_device_init: simdgroup matrix mul. = true +ggml_metal_device_init: has unified memory = true +ggml_metal_device_init: has bfloat = true +ggml_metal_device_init: has tensor = true +ggml_metal_device_init: use residency sets = true +ggml_metal_device_init: use shared buffers = true +ggml_metal_device_init: recommendedMaxWorkingSetSize = 115448.73 MB +| model | size | params | backend | threads | type_k | type_v | fa | test | t/s | +| ------------------------------ | ---------: | ---------: | ---------- | ------: | -----: | -----: | -: | --------------: | -------------------: | +| qwen35moe 35B.A3B Q8_0 | 34.36 GiB | 34.66 B | MTL,BLAS | 1 | turbo3 | turbo3 | 1 | pp16384 | 792.76 ± 57.30 | +| qwen35moe 35B.A3B Q8_0 | 34.36 GiB | 34.66 B | MTL,BLAS | 1 | turbo3 | turbo3 | 1 | tg128 | 16.47 ± 1.39 | + +build: 13afec1 (178) + +--- turbo3 @ 32768 --- +ggml_metal_device_init: testing tensor API for f16 support +ggml_metal_library_compile_pipeline: compiling pipeline: base = 'dummy_kernel', name = 'dummy_kernel' +ggml_metal_library_compile_pipeline: loaded dummy_kernel 0x104dc31e0 | th_max = 1024 | th_width = 32 +ggml_metal_device_init: testing tensor API for bfloat support +ggml_metal_library_compile_pipeline: compiling pipeline: base = 'dummy_kernel', name = 'dummy_kernel' +ggml_metal_library_compile_pipeline: loaded dummy_kernel 0x104dc3160 | th_max = 1024 | th_width = 32 +ggml_metal_library_init: using embedded metal library +ggml_metal_library_init: turbo3 sparse V dequant enabled +ggml_metal_library_init: loaded in 0.009 sec +ggml_metal_rsets_init: creating a residency set collection (keep_alive = 180 s) +ggml_metal_device_init: GPU name: MTL0 +ggml_metal_device_init: GPU family: MTLGPUFamilyApple10 (1010) +ggml_metal_device_init: GPU family: MTLGPUFamilyCommon3 (3003) +ggml_metal_device_init: GPU family: MTLGPUFamilyMetal4 (5002) +ggml_metal_device_init: simdgroup reduction = true +ggml_metal_device_init: simdgroup matrix mul. = true +ggml_metal_device_init: has unified memory = true +ggml_metal_device_init: has bfloat = true +ggml_metal_device_init: has tensor = true +ggml_metal_device_init: use residency sets = true +ggml_metal_device_init: use shared buffers = true +ggml_metal_device_init: recommendedMaxWorkingSetSize = 115448.73 MB +| model | size | params | backend | threads | type_k | type_v | fa | test | t/s | +| ------------------------------ | ---------: | ---------: | ---------- | ------: | -----: | -----: | -: | --------------: | -------------------: | +| qwen35moe 35B.A3B Q8_0 | 34.36 GiB | 34.66 B | MTL,BLAS | 1 | turbo3 | turbo3 | 1 | pp32768 | 806.43 ± 177.53 | +| qwen35moe 35B.A3B Q8_0 | 34.36 GiB | 34.66 B | MTL,BLAS | 1 | turbo3 | turbo3 | 1 | tg128 | 16.19 ± 1.11 | + +build: 13afec1 (178) + +--- turbo4 @ short --- +ggml_metal_device_init: testing tensor API for f16 support +ggml_metal_library_compile_pipeline: compiling pipeline: base = 'dummy_kernel', name = 'dummy_kernel' +ggml_metal_library_compile_pipeline: loaded dummy_kernel 0x105ccfa30 | th_max = 1024 | th_width = 32 +ggml_metal_device_init: testing tensor API for bfloat support +ggml_metal_library_compile_pipeline: compiling pipeline: base = 'dummy_kernel', name = 'dummy_kernel' +ggml_metal_library_compile_pipeline: loaded dummy_kernel 0x105cce8b0 | th_max = 1024 | th_width = 32 +ggml_metal_library_init: using embedded metal library +ggml_metal_library_init: turbo3 sparse V dequant enabled +ggml_metal_library_init: turbo3/4 SMEM pre-dequant enabled +ggml_metal_library_init: loaded in 0.008 sec +ggml_metal_rsets_init: creating a residency set collection (keep_alive = 180 s) +ggml_metal_device_init: GPU name: MTL0 +ggml_metal_device_init: GPU family: MTLGPUFamilyApple10 (1010) +ggml_metal_device_init: GPU family: MTLGPUFamilyCommon3 (3003) +ggml_metal_device_init: GPU family: MTLGPUFamilyMetal4 (5002) +ggml_metal_device_init: simdgroup reduction = true +ggml_metal_device_init: simdgroup matrix mul. = true +ggml_metal_device_init: has unified memory = true +ggml_metal_device_init: has bfloat = true +ggml_metal_device_init: has tensor = true +ggml_metal_device_init: use residency sets = true +ggml_metal_device_init: use shared buffers = true +ggml_metal_device_init: recommendedMaxWorkingSetSize = 115448.73 MB +| model | size | params | backend | threads | type_k | type_v | fa | test | t/s | +| ------------------------------ | ---------: | ---------: | ---------- | ------: | -----: | -----: | -: | --------------: | -------------------: | +| qwen35moe 35B.A3B Q8_0 | 34.36 GiB | 34.66 B | MTL,BLAS | 1 | turbo4 | turbo4 | 1 | tg128 | 16.93 ± 0.97 | + +build: 13afec1 (178) + +--- turbo4 @ 8192 --- +ggml_metal_device_init: testing tensor API for f16 support +ggml_metal_library_compile_pipeline: compiling pipeline: base = 'dummy_kernel', name = 'dummy_kernel' +ggml_metal_library_compile_pipeline: loaded dummy_kernel 0x10561bc80 | th_max = 1024 | th_width = 32 +ggml_metal_device_init: testing tensor API for bfloat support +ggml_metal_library_compile_pipeline: compiling pipeline: base = 'dummy_kernel', name = 'dummy_kernel' +ggml_metal_library_compile_pipeline: loaded dummy_kernel 0x10561ab00 | th_max = 1024 | th_width = 32 +ggml_metal_library_init: using embedded metal library +ggml_metal_library_init: turbo3 sparse V dequant enabled +ggml_metal_library_init: turbo3/4 SMEM pre-dequant enabled +ggml_metal_library_init: loaded in 0.008 sec +ggml_metal_rsets_init: creating a residency set collection (keep_alive = 180 s) +ggml_metal_device_init: GPU name: MTL0 +ggml_metal_device_init: GPU family: MTLGPUFamilyApple10 (1010) +ggml_metal_device_init: GPU family: MTLGPUFamilyCommon3 (3003) +ggml_metal_device_init: GPU family: MTLGPUFamilyMetal4 (5002) +ggml_metal_device_init: simdgroup reduction = true +ggml_metal_device_init: simdgroup matrix mul. = true +ggml_metal_device_init: has unified memory = true +ggml_metal_device_init: has bfloat = true +ggml_metal_device_init: has tensor = true +ggml_metal_device_init: use residency sets = true +ggml_metal_device_init: use shared buffers = true +ggml_metal_device_init: recommendedMaxWorkingSetSize = 115448.73 MB +| model | size | params | backend | threads | type_k | type_v | fa | test | t/s | +| ------------------------------ | ---------: | ---------: | ---------- | ------: | -----: | -----: | -: | --------------: | -------------------: | +| qwen35moe 35B.A3B Q8_0 | 34.36 GiB | 34.66 B | MTL,BLAS | 1 | turbo4 | turbo4 | 1 | pp8192 | 942.18 ± 77.19 | +| model | size | params | backend | threads | type_k | type_v | fa | test | t/s | +| ------------------------------ | ---------: | ---------: | ---------- | ------: | -----: | -----: | -: | --------------: | -------------------: | +| qwen35moe 35B.A3B Q8_0 | 34.36 GiB | 34.66 B | MTL,BLAS | 1 | turbo3 | turbo3 | 1 | pp32768 | 941.24 ± 180.34 | +| qwen35moe 35B.A3B Q8_0 | 34.36 GiB | 34.66 B | MTL,BLAS | 1 | turbo4 | turbo4 | 1 | tg128 | 44.84 ± 18.74 | + +build: 13afec1 (178) + +--- turbo4 @ 16384 --- +ggml_metal_device_init: testing tensor API for f16 support +ggml_metal_library_compile_pipeline: compiling pipeline: base = 'dummy_kernel', name = 'dummy_kernel' +ggml_metal_library_compile_pipeline: loaded dummy_kernel 0x1038a3d70 | th_max = 1024 | th_width = 32 +ggml_metal_device_init: testing tensor API for bfloat support +ggml_metal_library_compile_pipeline: compiling pipeline: base = 'dummy_kernel', name = 'dummy_kernel' +ggml_metal_library_compile_pipeline: loaded dummy_kernel 0x1038a2bf0 | th_max = 1024 | th_width = 32 +ggml_metal_library_init: using embedded metal library +ggml_metal_library_init: turbo3 sparse V dequant enabled +ggml_metal_library_init: turbo3/4 SMEM pre-dequant enabled +ggml_metal_library_init: loaded in 0.008 sec +ggml_metal_rsets_init: creating a residency set collection (keep_alive = 180 s) +ggml_metal_device_init: GPU name: MTL0 +ggml_metal_device_init: GPU family: MTLGPUFamilyApple10 (1010) +ggml_metal_device_init: GPU family: MTLGPUFamilyCommon3 (3003) +ggml_metal_device_init: GPU family: MTLGPUFamilyMetal4 (5002) +ggml_metal_device_init: simdgroup reduction = true +ggml_metal_device_init: simdgroup matrix mul. = true +ggml_metal_device_init: has unified memory = true +ggml_metal_device_init: has bfloat = true +ggml_metal_device_init: has tensor = true +ggml_metal_device_init: use residency sets = true +ggml_metal_device_init: use shared buffers = true +ggml_metal_device_init: recommendedMaxWorkingSetSize = 115448.73 MB +| qwen35moe 35B.A3B Q8_0 | 34.36 GiB | 34.66 B | MTL,BLAS | 1 | turbo3 | turbo3 | 1 | tg128 | 61.97 ± 9.79 | + +build: 13afec1 (178) + +--- turbo4 @ short --- +ggml_metal_device_init: testing tensor API for f16 support +ggml_metal_library_compile_pipeline: compiling pipeline: base = 'dummy_kernel', name = 'dummy_kernel' +ggml_metal_library_compile_pipeline: loaded dummy_kernel 0x10170b580 | th_max = 1024 | th_width = 32 +ggml_metal_device_init: testing tensor API for bfloat support +ggml_metal_library_compile_pipeline: compiling pipeline: base = 'dummy_kernel', name = 'dummy_kernel' +ggml_metal_library_compile_pipeline: loaded dummy_kernel 0x10170b500 | th_max = 1024 | th_width = 32 +ggml_metal_library_init: using embedded metal library +ggml_metal_library_init: turbo3 sparse V dequant enabled +ggml_metal_library_init: loaded in 0.008 sec +ggml_metal_rsets_init: creating a residency set collection (keep_alive = 180 s) +ggml_metal_device_init: GPU name: MTL0 +ggml_metal_device_init: GPU family: MTLGPUFamilyApple10 (1010) +ggml_metal_device_init: GPU family: MTLGPUFamilyCommon3 (3003) +ggml_metal_device_init: GPU family: MTLGPUFamilyMetal4 (5002) +ggml_metal_device_init: simdgroup reduction = true +ggml_metal_device_init: simdgroup matrix mul. = true +ggml_metal_device_init: has unified memory = true +ggml_metal_device_init: has bfloat = true +ggml_metal_device_init: has tensor = true +ggml_metal_device_init: use residency sets = true +ggml_metal_device_init: use shared buffers = true +ggml_metal_device_init: recommendedMaxWorkingSetSize = 115448.73 MB +| model | size | params | backend | threads | type_k | type_v | fa | test | t/s | +| ------------------------------ | ---------: | ---------: | ---------- | ------: | -----: | -----: | -: | --------------: | -------------------: | +| qwen35moe 35B.A3B Q8_0 | 34.36 GiB | 34.66 B | MTL,BLAS | 1 | turbo4 | turbo4 | 1 | tg128 | 17.82 ± 0.64 | + +build: 13afec1 (178) + +--- turbo4 @ 8192 --- +ggml_metal_device_init: testing tensor API for f16 support +ggml_metal_library_compile_pipeline: compiling pipeline: base = 'dummy_kernel', name = 'dummy_kernel' +ggml_metal_library_compile_pipeline: loaded dummy_kernel 0x103dab490 | th_max = 1024 | th_width = 32 +ggml_metal_device_init: testing tensor API for bfloat support +ggml_metal_library_compile_pipeline: compiling pipeline: base = 'dummy_kernel', name = 'dummy_kernel' +ggml_metal_library_compile_pipeline: loaded dummy_kernel 0x103dab410 | th_max = 1024 | th_width = 32 +ggml_metal_library_init: using embedded metal library +ggml_metal_library_init: turbo3 sparse V dequant enabled +ggml_metal_library_init: loaded in 0.009 sec +ggml_metal_rsets_init: creating a residency set collection (keep_alive = 180 s) +ggml_metal_device_init: GPU name: MTL0 +ggml_metal_device_init: GPU family: MTLGPUFamilyApple10 (1010) +ggml_metal_device_init: GPU family: MTLGPUFamilyCommon3 (3003) +ggml_metal_device_init: GPU family: MTLGPUFamilyMetal4 (5002) +ggml_metal_device_init: simdgroup reduction = true +ggml_metal_device_init: simdgroup matrix mul. = true +ggml_metal_device_init: has unified memory = true +ggml_metal_device_init: has bfloat = true +ggml_metal_device_init: has tensor = true +ggml_metal_device_init: use residency sets = true +ggml_metal_device_init: use shared buffers = true +ggml_metal_device_init: recommendedMaxWorkingSetSize = 115448.73 MB +| model | size | params | backend | threads | type_k | type_v | fa | test | t/s | +| ------------------------------ | ---------: | ---------: | ---------- | ------: | -----: | -----: | -: | --------------: | -------------------: | +| qwen35moe 35B.A3B Q8_0 | 34.36 GiB | 34.66 B | MTL,BLAS | 1 | turbo4 | turbo4 | 1 | pp16384 | 1187.08 ± 274.35 | +| model | size | params | backend | threads | type_k | type_v | fa | test | t/s | +| ------------------------------ | ---------: | ---------: | ---------- | ------: | -----: | -----: | -: | --------------: | -------------------: | +| qwen35moe 35B.A3B Q8_0 | 34.36 GiB | 34.66 B | MTL,BLAS | 1 | turbo4 | turbo4 | 1 | pp8192 | 1098.56 ± 217.82 | +| qwen35moe 35B.A3B Q8_0 | 34.36 GiB | 34.66 B | MTL,BLAS | 1 | turbo4 | turbo4 | 1 | tg128 | 50.13 ± 12.92 | + +build: 13afec1 (178) + +--- turbo4 @ 32768 --- +ggml_metal_device_init: testing tensor API for f16 support +ggml_metal_library_compile_pipeline: compiling pipeline: base = 'dummy_kernel', name = 'dummy_kernel' +ggml_metal_library_compile_pipeline: loaded dummy_kernel 0x105f20300 | th_max = 1024 | th_width = 32 +ggml_metal_device_init: testing tensor API for bfloat support +ggml_metal_library_compile_pipeline: compiling pipeline: base = 'dummy_kernel', name = 'dummy_kernel' +ggml_metal_library_compile_pipeline: loaded dummy_kernel 0x105f1f180 | th_max = 1024 | th_width = 32 +ggml_metal_library_init: using embedded metal library +ggml_metal_library_init: turbo3 sparse V dequant enabled +ggml_metal_library_init: turbo3/4 SMEM pre-dequant enabled +ggml_metal_library_init: loaded in 0.008 sec +ggml_metal_rsets_init: creating a residency set collection (keep_alive = 180 s) +ggml_metal_device_init: GPU name: MTL0 +ggml_metal_device_init: GPU family: MTLGPUFamilyApple10 (1010) +ggml_metal_device_init: GPU family: MTLGPUFamilyCommon3 (3003) +ggml_metal_device_init: GPU family: MTLGPUFamilyMetal4 (5002) +ggml_metal_device_init: simdgroup reduction = true +ggml_metal_device_init: simdgroup matrix mul. = true +ggml_metal_device_init: has unified memory = true +ggml_metal_device_init: has bfloat = true +ggml_metal_device_init: has tensor = true +ggml_metal_device_init: use residency sets = true +ggml_metal_device_init: use shared buffers = true +ggml_metal_device_init: recommendedMaxWorkingSetSize = 115448.73 MB +| qwen35moe 35B.A3B Q8_0 | 34.36 GiB | 34.66 B | MTL,BLAS | 1 | turbo4 | turbo4 | 1 | tg128 | 58.25 ± 4.07 | + +build: 13afec1 (178) + +--- turbo4 @ 16384 --- +ggml_metal_device_init: testing tensor API for f16 support +ggml_metal_library_compile_pipeline: compiling pipeline: base = 'dummy_kernel', name = 'dummy_kernel' +ggml_metal_library_compile_pipeline: loaded dummy_kernel 0x10588f220 | th_max = 1024 | th_width = 32 +ggml_metal_device_init: testing tensor API for bfloat support +ggml_metal_library_compile_pipeline: compiling pipeline: base = 'dummy_kernel', name = 'dummy_kernel' +ggml_metal_library_compile_pipeline: loaded dummy_kernel 0x10588f1a0 | th_max = 1024 | th_width = 32 +ggml_metal_library_init: using embedded metal library +ggml_metal_library_init: turbo3 sparse V dequant enabled +ggml_metal_library_init: loaded in 0.008 sec +ggml_metal_rsets_init: creating a residency set collection (keep_alive = 180 s) +ggml_metal_device_init: GPU name: MTL0 +ggml_metal_device_init: GPU family: MTLGPUFamilyApple10 (1010) +ggml_metal_device_init: GPU family: MTLGPUFamilyCommon3 (3003) +ggml_metal_device_init: GPU family: MTLGPUFamilyMetal4 (5002) +ggml_metal_device_init: simdgroup reduction = true +ggml_metal_device_init: simdgroup matrix mul. = true +ggml_metal_device_init: has unified memory = true +ggml_metal_device_init: has bfloat = true +ggml_metal_device_init: has tensor = true +ggml_metal_device_init: use residency sets = true +ggml_metal_device_init: use shared buffers = true +ggml_metal_device_init: recommendedMaxWorkingSetSize = 115448.73 MB +| model | size | params | backend | threads | type_k | type_v | fa | test | t/s | +| ------------------------------ | ---------: | ---------: | ---------- | ------: | -----: | -----: | -: | --------------: | -------------------: | +| qwen35moe 35B.A3B Q8_0 | 34.36 GiB | 34.66 B | MTL,BLAS | 1 | turbo4 | turbo4 | 1 | pp16384 | 755.20 ± 28.45 | +| qwen35moe 35B.A3B Q8_0 | 34.36 GiB | 34.66 B | MTL,BLAS | 1 | turbo4 | turbo4 | 1 | tg128 | 15.58 ± 1.31 | + +build: 13afec1 (178) + +--- turbo4 @ 32768 --- +ggml_metal_device_init: testing tensor API for f16 support +ggml_metal_library_compile_pipeline: compiling pipeline: base = 'dummy_kernel', name = 'dummy_kernel' +ggml_metal_library_compile_pipeline: loaded dummy_kernel 0x1018533e0 | th_max = 1024 | th_width = 32 +ggml_metal_device_init: testing tensor API for bfloat support +ggml_metal_library_compile_pipeline: compiling pipeline: base = 'dummy_kernel', name = 'dummy_kernel' +ggml_metal_library_compile_pipeline: loaded dummy_kernel 0x101853360 | th_max = 1024 | th_width = 32 +ggml_metal_library_init: using embedded metal library +ggml_metal_library_init: turbo3 sparse V dequant enabled +ggml_metal_library_init: loaded in 0.009 sec +ggml_metal_rsets_init: creating a residency set collection (keep_alive = 180 s) +ggml_metal_device_init: GPU name: MTL0 +ggml_metal_device_init: GPU family: MTLGPUFamilyApple10 (1010) +ggml_metal_device_init: GPU family: MTLGPUFamilyCommon3 (3003) +ggml_metal_device_init: GPU family: MTLGPUFamilyMetal4 (5002) +ggml_metal_device_init: simdgroup reduction = true +ggml_metal_device_init: simdgroup matrix mul. = true +ggml_metal_device_init: has unified memory = true +ggml_metal_device_init: has bfloat = true +ggml_metal_device_init: has tensor = true +ggml_metal_device_init: use residency sets = true +ggml_metal_device_init: use shared buffers = true +ggml_metal_device_init: recommendedMaxWorkingSetSize = 115448.73 MB +| model | size | params | backend | threads | type_k | type_v | fa | test | t/s | +| ------------------------------ | ---------: | ---------: | ---------- | ------: | -----: | -----: | -: | --------------: | -------------------: | +| qwen35moe 35B.A3B Q8_0 | 34.36 GiB | 34.66 B | MTL,BLAS | 1 | turbo4 | turbo4 | 1 | pp32768 | 732.00 ± 172.10 | +| qwen35moe 35B.A3B Q8_0 | 34.36 GiB | 34.66 B | MTL,BLAS | 1 | turbo4 | turbo4 | 1 | tg128 | 16.29 ± 1.78 | + +build: 13afec1 (178) + +SKIP: q8_0 + smem (q8_0 unaffected by SMEM) +SKIP: q8_0 + smem (q8_0 unaffected by SMEM) +SKIP: q8_0 + smem (q8_0 unaffected by SMEM) +SKIP: q8_0 + smem (q8_0 unaffected by SMEM) +=== Done: smem === +| model | size | params | backend | threads | type_k | type_v | fa | test | t/s | +| ------------------------------ | ---------: | ---------: | ---------- | ------: | -----: | -----: | -: | --------------: | -------------------: | +| qwen35moe 35B.A3B Q8_0 | 34.36 GiB | 34.66 B | MTL,BLAS | 1 | turbo4 | turbo4 | 1 | pp32768 | 1018.88 ± 235.19 | +| qwen35moe 35B.A3B Q8_0 | 34.36 GiB | 34.66 B | MTL,BLAS | 1 | turbo4 | turbo4 | 1 | tg128 | 81.62 ± 0.05 | + +build: 13afec1 (178) + +SKIP: q8_0 + smem (q8_0 unaffected by SMEM) +SKIP: q8_0 + smem (q8_0 unaffected by SMEM) +SKIP: q8_0 + smem (q8_0 unaffected by SMEM) +SKIP: q8_0 + smem (q8_0 unaffected by SMEM) +=== Done: smem === diff --git a/common/arg.cpp b/common/arg.cpp index 2e0f46db519..8c1d7850143 100644 --- a/common/arg.cpp +++ b/common/arg.cpp @@ -387,6 +387,9 @@ const std::vector kv_cache_types = { GGML_TYPE_IQ4_NL, GGML_TYPE_Q5_0, GGML_TYPE_Q5_1, + GGML_TYPE_TURBO2_0, + GGML_TYPE_TURBO3_0, + GGML_TYPE_TURBO4_0, }; static ggml_type kv_cache_type_from_str(const std::string & s) { diff --git a/common/common.cpp b/common/common.cpp index 16f78debd02..825df65ab4f 100644 --- a/common/common.cpp +++ b/common/common.cpp @@ -41,6 +41,12 @@ #include #include #include +#ifndef fileno +#define fileno _fileno +#endif +#ifndef isatty +#define isatty _isatty +#endif #else #include #include diff --git a/ggml/include/ggml.h b/ggml/include/ggml.h index 669f66b650f..94dc0944278 100644 --- a/ggml/include/ggml.h +++ b/ggml/include/ggml.h @@ -181,7 +181,7 @@ # define GGML_API __declspec(dllimport) extern # endif # else -# define GGML_API __attribute__ ((visibility ("default"))) extern +# define GGML_API __attribute__ ((visibility ("default"))) # endif #else # define GGML_API extern @@ -428,7 +428,12 @@ extern "C" { // GGML_TYPE_IQ4_NL_8_8 = 38, GGML_TYPE_MXFP4 = 39, // MXFP4 (1 block) GGML_TYPE_NVFP4 = 40, // NVFP4 (4 blocks, E4M3 scale) - GGML_TYPE_COUNT = 41, + GGML_TYPE_TURBO3_0 = 41, // TurboQuant 3-bit KV cache: 2-bit PolarQuant + 1-bit QJL + GGML_TYPE_TURBO4_0 = 42, // TurboQuant 4-bit KV cache: 3-bit PolarQuant + 1-bit QJL + GGML_TYPE_TURBO2_0 = 43, // TurboQuant 2-bit KV cache: 2-bit PolarQuant (no QJL) + GGML_TYPE_TQ3_1S = 44, // TurboQuant 3-bit weight: WHT-rotated 8-level Lloyd-Max, block_size=32 + GGML_TYPE_TQ4_1S = 45, // TurboQuant 4-bit weight: WHT-rotated 16-level Lloyd-Max, block_size=32 + GGML_TYPE_COUNT = 46, }; // precision @@ -559,6 +564,7 @@ extern "C" { GGML_OP_RWKV_WKV7, GGML_OP_SOLVE_TRI, GGML_OP_GATED_DELTA_NET, + GGML_OP_TURBO_WHT, GGML_OP_UNARY, @@ -2481,6 +2487,16 @@ extern "C" { struct ggml_tensor * beta, struct ggml_tensor * state); + // TurboQuant Walsh-Hadamard Transform (O(d log d) rotation for KV cache compression) + // Applies WHT rotation to 128-element groups along ne[0]: sign1 → butterfly → sign2 → normalize + // direction: 0 = forward (signs1 → WHT → signs2), 1 = inverse (signs2 → WHT → signs1) + GGML_API struct ggml_tensor * ggml_turbo_wht( + struct ggml_context * ctx, + struct ggml_tensor * a, + int direction, + int group_size, // 0 = auto (64 or 128 from ne[0]) + struct ggml_tensor * scale); // NULL = no InnerQ scaling + // custom operators typedef void (*ggml_custom1_op_t)(struct ggml_tensor * dst , const struct ggml_tensor * a, int ith, int nth, void * userdata); diff --git a/ggml/src/CMakeLists.txt b/ggml/src/CMakeLists.txt index 78853304d9f..23515f9d36e 100644 --- a/ggml/src/CMakeLists.txt +++ b/ggml/src/CMakeLists.txt @@ -205,6 +205,7 @@ add_library(ggml-base ggml-threading.h ggml-quants.c ggml-quants.h + ggml-turbo-quant.c gguf.cpp) set_target_properties(ggml-base PROPERTIES diff --git a/ggml/src/ggml-common.h b/ggml/src/ggml-common.h index 92cf739e7a7..76e3e8f6553 100644 --- a/ggml/src/ggml-common.h +++ b/ggml/src/ggml-common.h @@ -266,6 +266,97 @@ typedef struct { } block_tq2_0; static_assert(sizeof(block_tq2_0) == sizeof(ggml_half) + QK_K / 4, "wrong tq2_0 block size/padding"); +// TurboQuant 3-bit MSE-only: 3-bit PolarQuant indices (no QJL) +// Storage block size = 32 (matches q4_0 for optimal GPU parallelism) +// Transform group size = 128 (head_dim, for rotation Gaussianization) +// Per block: norm(fp16) + 2-bit indices (8 bytes) + 1-bit extra (4 bytes) = 14 bytes per 32 values +// = 3.5 bits/value → 4.6× compression vs fp16 +// The 3-bit index is split: lower 2 bits in qs[], upper 1 bit in signs[] +#define QK_TURBO3 128 // Block size 128: one block per rotation group, eliminates redundant norms +#define QK_TURBO3_GROUP 128 // rotation group size = head_dim +// Derived: FA template nl parameters (auto-scale with block size) +#define NL_TURBO3 (QK_TURBO3 / 16) // non-vec FA iterations per block +#define NL_TURBO3_VEC (QK_TURBO3 / 4) // vec FA iterations per block +typedef struct { + ggml_half norm; // 2 bytes: vector L2 norm (for rescaling) + uint8_t qs[QK_TURBO3 / 4]; // 8 bytes: lower 2-bit indices (4 per byte) + uint8_t signs[QK_TURBO3 / 8]; // 4 bytes: upper 1-bit of 3-bit index (8 per byte) +} block_turbo3_0; // 14 bytes total +static_assert(sizeof(block_turbo3_0) == sizeof(ggml_half) + QK_TURBO3/4 + QK_TURBO3/8, "wrong turbo3_0 block size/padding"); + +// TurboQuant 4-bit: 3-bit PolarQuant indices + 1-bit QJL signs +// TURBO4_USE_4BIT: switch between 4-bit PolarQuant (new) and 3-bit+QJL (legacy) +// Default: 4-bit on all backends (Metal + CUDA validated) +#ifndef TURBO4_USE_4BIT +# define TURBO4_USE_4BIT 1 +#endif + +#define QK_TURBO4 128 + +#if TURBO4_USE_4BIT +// 4-bit PolarQuant: 16 optimal centroids, nibble packed, no QJL +// Per block: norm(fp16) + rnorm(fp16, reserved) + 4-bit indices (64 bytes) +// = 68 bytes per 128 values = 4.25 bits/value → 3.8× compression vs fp16 +typedef struct { + ggml_half norm; // 2 bytes + ggml_half rnorm; // 2 bytes (reserved, unused in 4-bit mode) + uint8_t qs[QK_TURBO4 / 2]; // 64 bytes: 4-bit PolarQuant indices (nibble packed) +} block_turbo4_0; // 68 bytes total +static_assert(sizeof(block_turbo4_0) == 68, "wrong turbo4_0 block size"); +#else +// Legacy 3-bit PolarQuant + 1-bit QJL (original paper design) +// Per block: norm(fp16) + rnorm(fp16) + 3-bit indices (48 bytes) + 1-bit QJL signs (16 bytes) +// = 68 bytes per 128 values = 4.25 bits/value → 3.8× compression vs fp16 +typedef struct { + ggml_half norm; // 2 bytes + ggml_half rnorm; // 2 bytes: residual norm for QJL scale + uint8_t qs[QK_TURBO4 * 3 / 8]; // 48 bytes: 3-bit PolarQuant indices + uint8_t signs[QK_TURBO4 / 8]; // 16 bytes: 1-bit QJL signs +} block_turbo4_0; // 68 bytes total +static_assert(sizeof(block_turbo4_0) == 2*sizeof(ggml_half) + QK_TURBO4*3/8 + QK_TURBO4/8, "wrong turbo4_0 block size"); +#endif + +static_assert(QK_TURBO4 == 128, "turbo4 kernels assume QK_TURBO4 == 128"); + +// TurboQuant 2-bit: 2-bit PolarQuant indices only (no QJL) +// Per block: norm(fp16) + 2-bit indices (8 bytes) = 10 bytes per 32 values +// = 2.5 bits/value → 6.4× compression vs fp16 +// 4 centroids (Lloyd-Max for N(0, 1/128)): {-0.133462, -0.039994, 0.039994, 0.133462} +#define QK_TURBO2 128 // Block size 128: one block per rotation group +#define QK_TURBO2_GROUP 128 // rotation group size = head_dim +// Derived: FA template nl parameters (auto-scale with block size) +#define NL_TURBO2 (QK_TURBO2 / 16) // non-vec FA iterations per block +#define NL_TURBO2_VEC (QK_TURBO2 / 4) // vec FA iterations per block +typedef struct { + ggml_half norm; // 2 bytes: corrected L2 norm + uint8_t qs[QK_TURBO2 / 4]; // 8 bytes: 2-bit indices (4 per byte) +} block_turbo2_0; // 10 bytes total +static_assert(sizeof(block_turbo2_0) == sizeof(ggml_half) + QK_TURBO2/4, "wrong turbo2_0 block size/padding"); + +// TQ3_1S: WHT-rotated 3-bit weight quantization (8-level Lloyd-Max for N(0,1)) +// Block size 32, dual half-block scales (d0 for [0..15], d1 for [16..31]) +// Per block: d0(fp16) + d1(fp16) + 3-bit indices packed (12 bytes) = 16 bytes per 32 values +// = 4.0 bits/value +#define QK_TQ3_0 32 +typedef struct { + ggml_half d0; // 2 bytes: scale for first 16 elements + ggml_half d1; // 2 bytes: scale for last 16 elements + uint8_t qs[QK_TQ3_0 * 3 / 8]; // 12 bytes: 3-bit indices packed (4 groups of 8 in 3 bytes) +} block_tq3_1s; // 16 bytes total +static_assert(sizeof(block_tq3_1s) == 16, "wrong tq3_1s block size"); + +// TQ4_1S: WHT-rotated 4-bit weight quantization (16-level Lloyd-Max for N(0,1)) +// Block size 32, dual half-block scales (d0 for [0..15], d1 for [16..31]) +// Per block: d0(fp16) + d1(fp16) + 4-bit indices packed (16 bytes) = 20 bytes per 32 values +// = 5.0 bits/value +#define QK_TQ4_1S 32 +typedef struct { + ggml_half d0; // 2 bytes: scale for first 16 elements + ggml_half d1; // 2 bytes: scale for last 16 elements + uint8_t qs[QK_TQ4_1S / 2]; // 16 bytes: 4-bit indices nibble-packed +} block_tq4_1s; // 20 bytes total +static_assert(sizeof(block_tq4_1s) == 20, "wrong tq4_1s block size"); + // // Super-block quantization structures // diff --git a/ggml/src/ggml-cpu/ggml-cpu.c b/ggml/src/ggml-cpu/ggml-cpu.c index 7486acc2b5d..963449a4cb5 100644 --- a/ggml/src/ggml-cpu/ggml-cpu.c +++ b/ggml/src/ggml-cpu/ggml-cpu.c @@ -7,6 +7,7 @@ #include "ggml-cpu-impl.h" #include "ggml-impl.h" #include "quants.h" +#include "ggml-quants.h" #include "ggml-threading.h" #include "unary-ops.h" #include "binary-ops.h" @@ -204,6 +205,23 @@ typedef pthread_t ggml_thread_t; #include #endif +// Forward declarations — defined below, after utility functions +static void ggml_vec_dot_turbo3_0_f32(int n, float * GGML_RESTRICT s, size_t bs, + const void * GGML_RESTRICT vx, size_t bx, + const void * GGML_RESTRICT vy, size_t by, int nrc); +static void ggml_vec_dot_turbo2_0_f32(int n, float * GGML_RESTRICT s, size_t bs, + const void * GGML_RESTRICT vx, size_t bx, + const void * GGML_RESTRICT vy, size_t by, int nrc); +static void ggml_vec_dot_turbo4_0_f32(int n, float * GGML_RESTRICT s, size_t bs, + const void * GGML_RESTRICT vx, size_t bx, + const void * GGML_RESTRICT vy, size_t by, int nrc); +static void ggml_vec_dot_tq3_1s_q8_0(int n, float * GGML_RESTRICT s, size_t bs, + const void * GGML_RESTRICT vx, size_t bx, + const void * GGML_RESTRICT vy, size_t by, int nrc); +static void ggml_vec_dot_tq4_1s_q8_0(int n, float * GGML_RESTRICT s, size_t bs, + const void * GGML_RESTRICT vx, size_t bx, + const void * GGML_RESTRICT vy, size_t by, int nrc); + static const struct ggml_type_traits_cpu type_traits_cpu[GGML_TYPE_COUNT] = { [GGML_TYPE_F32] = { .from_float = (ggml_from_float_t) ggml_cpu_fp32_to_fp32, @@ -393,6 +411,36 @@ static const struct ggml_type_traits_cpu type_traits_cpu[GGML_TYPE_COUNT] = { [GGML_TYPE_I32] = { .from_float = (ggml_from_float_t) ggml_cpu_fp32_to_i32, }, + [GGML_TYPE_TURBO3_0] = { + .from_float = (ggml_from_float_t) quantize_row_turbo3_0_ref, + .vec_dot = (ggml_vec_dot_t) ggml_vec_dot_turbo3_0_f32, + .vec_dot_type = GGML_TYPE_F32, + .nrows = 1, + }, + [GGML_TYPE_TURBO2_0] = { + .from_float = (ggml_from_float_t) quantize_row_turbo2_0_ref, + .vec_dot = (ggml_vec_dot_t) ggml_vec_dot_turbo2_0_f32, + .vec_dot_type = GGML_TYPE_F32, + .nrows = 1, + }, + [GGML_TYPE_TURBO4_0] = { + .from_float = (ggml_from_float_t) quantize_row_turbo4_0_ref, + .vec_dot = (ggml_vec_dot_t) ggml_vec_dot_turbo4_0_f32, + .vec_dot_type = GGML_TYPE_F32, + .nrows = 1, + }, + [GGML_TYPE_TQ3_1S] = { + .from_float = (ggml_from_float_t) quantize_row_tq3_1s_ref, + .vec_dot = (ggml_vec_dot_t) ggml_vec_dot_tq3_1s_q8_0, + .vec_dot_type = GGML_TYPE_Q8_0, + .nrows = 1, + }, + [GGML_TYPE_TQ4_1S] = { + .from_float = (ggml_from_float_t) quantize_row_tq4_1s_ref, + .vec_dot = (ggml_vec_dot_t) ggml_vec_dot_tq4_1s_q8_0, + .vec_dot_type = GGML_TYPE_Q8_0, + .nrows = 1, + }, }; const struct ggml_type_traits_cpu * ggml_get_type_traits_cpu(enum ggml_type type) { @@ -2031,6 +2079,10 @@ static void ggml_compute_forward(struct ggml_compute_params * params, struct ggm { ggml_compute_forward_gated_delta_net(params, tensor); } break; + case GGML_OP_TURBO_WHT: + { + ggml_compute_forward_turbo_wht(params, tensor); + } break; case GGML_OP_MAP_CUSTOM1: { ggml_compute_forward_map_custom1(params, tensor); @@ -2211,6 +2263,7 @@ static int ggml_get_n_tasks(struct ggml_tensor * node, int n_threads) { case GGML_OP_COUNT_EQUAL: case GGML_OP_SOLVE_TRI: case GGML_OP_GATED_DELTA_NET: + case GGML_OP_TURBO_WHT: { n_tasks = n_threads; } break; @@ -2929,6 +2982,10 @@ struct ggml_cplan ggml_graph_plan( const int64_t S_v = node->src[2]->ne[0]; cur = S_v * sizeof(float) * n_tasks; } break; + case GGML_OP_TURBO_WHT: + { + cur = 0; // no extra workspace needed + } break; case GGML_OP_COUNT: { GGML_ABORT("fatal error"); @@ -3313,6 +3370,119 @@ enum ggml_status ggml_graph_compute_with_ctx(struct ggml_context * ctx, struct g return ggml_graph_compute(cgraph, &cplan); } +// TurboQuant3 vec_dot: dequantize turbo3 block to f32, then dot with f32 operand. +// Used by CPU flash attention for models with D not supported by CUDA FA (e.g. D=192). +static void ggml_vec_dot_turbo3_0_f32(int n, float * GGML_RESTRICT s, size_t bs, + const void * GGML_RESTRICT vx, size_t bx, + const void * GGML_RESTRICT vy, size_t by, int nrc) { + GGML_ASSERT(nrc == 1); + GGML_UNUSED(bs); GGML_UNUSED(bx); GGML_UNUSED(by); GGML_UNUSED(nrc); + + // Dequantize turbo3 to f32 temp buffer, then dot + float * tmp = (float *)malloc(n * sizeof(float)); + GGML_ASSERT(tmp != NULL); + ggml_get_type_traits(GGML_TYPE_TURBO3_0)->to_float(vx, tmp, n); + + const float * y = (const float *)vy; + float sum = 0.0f; + for (int i = 0; i < n; i++) { + sum += tmp[i] * y[i]; + } + free(tmp); + *s = sum; +} + +// TurboQuant2 vec_dot: dequantize turbo2 block to f32, then dot with f32 operand. +static void ggml_vec_dot_turbo2_0_f32(int n, float * GGML_RESTRICT s, size_t bs, + const void * GGML_RESTRICT vx, size_t bx, + const void * GGML_RESTRICT vy, size_t by, int nrc) { + GGML_ASSERT(nrc == 1); + GGML_UNUSED(bs); GGML_UNUSED(bx); GGML_UNUSED(by); GGML_UNUSED(nrc); + + float * tmp = (float *)malloc(n * sizeof(float)); + GGML_ASSERT(tmp != NULL); + ggml_get_type_traits(GGML_TYPE_TURBO2_0)->to_float(vx, tmp, n); + + const float * y = (const float *)vy; + float sum = 0.0f; + for (int i = 0; i < n; i++) { + sum += tmp[i] * y[i]; + } + free(tmp); + *s = sum; +} + +// TurboQuant4 vec_dot: dequantize turbo4 block to f32, then dot with f32 operand. +static void ggml_vec_dot_turbo4_0_f32(int n, float * GGML_RESTRICT s, size_t bs, + const void * GGML_RESTRICT vx, size_t bx, + const void * GGML_RESTRICT vy, size_t by, int nrc) { + GGML_ASSERT(nrc == 1); + GGML_UNUSED(bs); GGML_UNUSED(bx); GGML_UNUSED(by); GGML_UNUSED(nrc); + + float * tmp = (float *)malloc(n * sizeof(float)); + GGML_ASSERT(tmp != NULL); + ggml_get_type_traits(GGML_TYPE_TURBO4_0)->to_float(vx, tmp, n); + + const float * y = (const float *)vy; + float sum = 0.0f; + for (int i = 0; i < n; i++) { + sum += tmp[i] * y[i]; + } + free(tmp); + *s = sum; +} + +// TQ3_1S vec_dot: dequantize tq3_1s block to f32, then dot with q8_0. +// TODO: optimize with SIMD intrinsics for ARM NEON / AVX2 +static void ggml_vec_dot_tq3_1s_q8_0(int n, float * GGML_RESTRICT s, size_t bs, + const void * GGML_RESTRICT vx, size_t bx, + const void * GGML_RESTRICT vy, size_t by, int nrc) { + GGML_ASSERT(nrc == 1); + GGML_UNUSED(bs); GGML_UNUSED(bx); GGML_UNUSED(by); GGML_UNUSED(nrc); + + float * tmp = (float *)malloc(n * sizeof(float)); + GGML_ASSERT(tmp != NULL); + ggml_get_type_traits(GGML_TYPE_TQ3_1S)->to_float(vx, tmp, n); + + // Dequantize q8_0 and dot + float * tmp2 = (float *)malloc(n * sizeof(float)); + GGML_ASSERT(tmp2 != NULL); + ggml_get_type_traits(GGML_TYPE_Q8_0)->to_float(vy, tmp2, n); + + float sum = 0.0f; + for (int i = 0; i < n; i++) { + sum += tmp[i] * tmp2[i]; + } + free(tmp); + free(tmp2); + *s = sum; +} + +// TQ4_1S vec_dot: dequantize tq4_1s block to f32, then dot with q8_0. +// TODO: optimize with SIMD intrinsics +static void ggml_vec_dot_tq4_1s_q8_0(int n, float * GGML_RESTRICT s, size_t bs, + const void * GGML_RESTRICT vx, size_t bx, + const void * GGML_RESTRICT vy, size_t by, int nrc) { + GGML_ASSERT(nrc == 1); + GGML_UNUSED(bs); GGML_UNUSED(bx); GGML_UNUSED(by); GGML_UNUSED(nrc); + + float * tmp = (float *)malloc(n * sizeof(float)); + GGML_ASSERT(tmp != NULL); + ggml_get_type_traits(GGML_TYPE_TQ4_1S)->to_float(vx, tmp, n); + + float * tmp2 = (float *)malloc(n * sizeof(float)); + GGML_ASSERT(tmp2 != NULL); + ggml_get_type_traits(GGML_TYPE_Q8_0)->to_float(vy, tmp2, n); + + float sum = 0.0f; + for (int i = 0; i < n; i++) { + sum += tmp[i] * tmp2[i]; + } + free(tmp); + free(tmp2); + *s = sum; +} + void ggml_cpu_fp32_to_fp32(const float * x, float * y, int64_t n) { memcpy(y, x, n * sizeof(float)); } diff --git a/ggml/src/ggml-cpu/ops.cpp b/ggml/src/ggml-cpu/ops.cpp index 765ce07f06c..6760d0b28e0 100644 --- a/ggml/src/ggml-cpu/ops.cpp +++ b/ggml/src/ggml-cpu/ops.cpp @@ -12,6 +12,8 @@ #include #include +extern "C" GGML_API int turbo3_cpu_wht_group_size; + // ggml_compute_forward_dup static void ggml_compute_forward_dup_same_cont( @@ -678,6 +680,8 @@ void ggml_compute_forward_add( case GGML_TYPE_Q6_K: case GGML_TYPE_TQ1_0: case GGML_TYPE_TQ2_0: + case GGML_TYPE_TQ3_1S: + case GGML_TYPE_TQ4_1S: case GGML_TYPE_IQ2_XXS: case GGML_TYPE_IQ2_XS: case GGML_TYPE_IQ3_XXS: @@ -1128,6 +1132,8 @@ void ggml_compute_forward_add1( case GGML_TYPE_Q6_K: case GGML_TYPE_TQ1_0: case GGML_TYPE_TQ2_0: + case GGML_TYPE_TQ3_1S: + case GGML_TYPE_TQ4_1S: case GGML_TYPE_IQ2_XXS: case GGML_TYPE_IQ2_XS: case GGML_TYPE_IQ3_XXS: @@ -1257,6 +1263,8 @@ void ggml_compute_forward_acc( case GGML_TYPE_Q6_K: case GGML_TYPE_TQ1_0: case GGML_TYPE_TQ2_0: + case GGML_TYPE_TQ3_1S: + case GGML_TYPE_TQ4_1S: case GGML_TYPE_IQ2_XXS: case GGML_TYPE_IQ2_XS: case GGML_TYPE_IQ3_XXS: @@ -4345,6 +4353,8 @@ void ggml_compute_forward_out_prod( case GGML_TYPE_Q6_K: case GGML_TYPE_TQ1_0: case GGML_TYPE_TQ2_0: + case GGML_TYPE_TQ3_1S: + case GGML_TYPE_TQ4_1S: case GGML_TYPE_IQ2_XXS: case GGML_TYPE_IQ2_XS: case GGML_TYPE_IQ3_XXS: @@ -4621,6 +4631,8 @@ void ggml_compute_forward_set( case GGML_TYPE_Q6_K: case GGML_TYPE_TQ1_0: case GGML_TYPE_TQ2_0: + case GGML_TYPE_TQ3_1S: + case GGML_TYPE_TQ4_1S: case GGML_TYPE_IQ2_XXS: case GGML_TYPE_IQ2_XS: case GGML_TYPE_IQ3_XXS: @@ -4844,6 +4856,8 @@ void ggml_compute_forward_get_rows( case GGML_TYPE_Q6_K: case GGML_TYPE_TQ1_0: case GGML_TYPE_TQ2_0: + case GGML_TYPE_TQ3_1S: + case GGML_TYPE_TQ4_1S: case GGML_TYPE_IQ2_XXS: case GGML_TYPE_IQ2_XS: case GGML_TYPE_IQ3_XXS: @@ -4926,6 +4940,13 @@ static void ggml_compute_forward_set_rows_f32( ggml_from_float_t const from_float = ggml_get_type_traits_cpu(dst->type)->from_float; + // For turbo types: communicate WHT group size to the quantize function via global + if (dst->type == GGML_TYPE_TURBO3_0 || dst->type == GGML_TYPE_TURBO4_0 || dst->type == GGML_TYPE_TURBO2_0) { + int gs = 0; + memcpy(&gs, dst->op_params, sizeof(int)); + turbo3_cpu_wht_group_size = (gs == 64 || gs == 128) ? gs : 0; + } + for (int64_t i03 = 0; i03 < ne03; ++i03) { for (int64_t i02 = 0; i02 < ne02; ++i02) { for (int64_t i = ir0; i < ir1; ++i) { @@ -5569,6 +5590,8 @@ void ggml_compute_forward_clamp( case GGML_TYPE_Q6_K: case GGML_TYPE_TQ1_0: case GGML_TYPE_TQ2_0: + case GGML_TYPE_TQ3_1S: + case GGML_TYPE_TQ4_1S: case GGML_TYPE_IQ2_XXS: case GGML_TYPE_IQ2_XS: case GGML_TYPE_IQ3_XXS: @@ -10608,6 +10631,104 @@ void ggml_compute_forward_gated_delta_net( } } +// ggml_compute_forward_turbo_wht + +// WHT sign arrays (must match Metal shader turbo_wht_signs1/2) +static const float turbo_wht_s1[128] = {-1,1,1,-1,-1,1,-1,1,-1,-1,1,1,1,1,1,1,1,-1,1,-1,1,-1,-1,1,1,1,-1,1,1,-1,-1,-1,-1,1,1,-1,1,1,-1,1,-1,1,1,-1,-1,1,-1,1,1,1,1,-1,-1,-1,-1,-1,1,-1,1,1,1,1,-1,1,-1,-1,1,-1,-1,-1,1,-1,-1,-1,1,-1,-1,-1,1,1,1,-1,-1,1,1,1,-1,-1,1,1,-1,1,1,-1,1,-1,-1,1,1,-1,1,-1,1,-1,1,1,1,1,-1,1,-1,1,1,-1,1,1,-1,-1,-1,-1,-1,1,1,-1,1,1,-1,1}; +static const float turbo_wht_s2[128] = {1,1,1,1,-1,1,1,-1,1,-1,-1,-1,1,-1,-1,-1,1,1,-1,-1,1,-1,1,-1,1,-1,-1,1,-1,1,1,1,1,1,-1,-1,-1,1,-1,-1,-1,-1,-1,-1,1,1,1,-1,1,-1,1,1,1,-1,-1,1,-1,-1,-1,-1,-1,-1,1,1,1,-1,1,-1,-1,-1,-1,1,-1,1,-1,1,-1,-1,1,1,-1,1,-1,1,1,-1,1,-1,-1,-1,-1,1,-1,-1,1,-1,1,-1,1,1,1,-1,-1,1,-1,1,-1,1,1,-1,-1,1,-1,1,-1,1,1,-1,1,-1,1,-1,-1,-1,-1,-1,1,-1}; + +static void ggml_compute_forward_turbo_wht_f32( + const ggml_compute_params * params, + ggml_tensor * dst) { + const ggml_tensor * src = dst->src[0]; + const ggml_tensor * scale_tensor = dst->src[1]; // InnerQ scale_inv (may be NULL) + const float * src_data = (const float *) src->data; + float * dst_data = (float *) dst->data; + const float * scale_inv = scale_tensor ? (const float *) scale_tensor->data : NULL; + + int direction; + int group_size; + memcpy(&direction, dst->op_params + 0, sizeof(int)); + memcpy(&group_size, dst->op_params + sizeof(int), sizeof(int)); + + const int64_t head_dim = src->ne[0]; + const int64_t n_heads = ggml_nelements(src) / head_dim; + const int64_t groups_per_head = head_dim / group_size; + const int tail_size = (int)(head_dim % group_size); + const int64_t n_groups = groups_per_head * n_heads; + + const float inv_sqrt = 1.0f / sqrtf((float)group_size); + + // Parallel over groups + const int64_t ith = params->ith; + const int64_t nth = params->nth; + const int64_t grp_start = (n_groups * ith) / nth; + const int64_t grp_end = (n_groups * (ith + 1)) / nth; + + // Select sign arrays: for 64-group, use first 64 elements of the 128-element arrays + const float * s_first = (direction == 0) ? turbo_wht_s1 : turbo_wht_s2; + const float * s_second = (direction == 0) ? turbo_wht_s2 : turbo_wht_s1; + + for (int64_t g = grp_start; g < grp_end; g++) { + const int64_t head_idx = g / groups_per_head; + const int64_t grp_in_head = g % groups_per_head; + const int64_t base = head_idx * head_dim + grp_in_head * group_size; + + float x[128]; // max group_size + const float * in = src_data + base; + + // InnerQ forward: apply scale_inv BEFORE signs+WHT (for Q pre-rotation) + if (direction == 0 && scale_inv != NULL) { + for (int i = 0; i < group_size; i++) x[i] = in[i] * scale_inv[i % group_size]; + } else { + for (int i = 0; i < group_size; i++) x[i] = in[i]; + } + + // Apply first signs + for (int i = 0; i < group_size; i++) x[i] *= s_first[i]; + + // WHT butterfly (log2(group_size) stages) + for (int h = 1; h < group_size; h *= 2) { + for (int i = 0; i < group_size; i += h * 2) { + for (int j = i; j < i + h; j++) { + float a = x[j], b = x[j + h]; + x[j] = a + b; + x[j + h] = a - b; + } + } + } + + // Normalize + second signs + float * out = dst_data + base; + for (int i = 0; i < group_size; i++) { + float val = x[i] * inv_sqrt * s_second[i]; + // InnerQ inverse: apply scale_inv AFTER WHT+signs (for V un-rotation) + if (direction == 1 && scale_inv != NULL) { + val *= scale_inv[i % group_size]; + } + out[i] = val; + } + } + + // Copy tail elements unchanged (identity pass-through) + if (tail_size > 0 && ith == 0) { + const int64_t tail_offset = groups_per_head * group_size; + for (int64_t h = 0; h < n_heads; h++) { + const int64_t base = h * head_dim + tail_offset; + memcpy(dst_data + base, src_data + base, tail_size * sizeof(float)); + } + } +} + +void ggml_compute_forward_turbo_wht( + const ggml_compute_params * params, + ggml_tensor * dst) { + switch (dst->src[0]->type) { + case GGML_TYPE_F32: ggml_compute_forward_turbo_wht_f32(params, dst); break; + default: GGML_ABORT("fatal error"); + } +} + // ggml_compute_forward_rwkv_wkv7 static void ggml_compute_forward_rwkv_wkv7_f32( diff --git a/ggml/src/ggml-cpu/ops.h b/ggml/src/ggml-cpu/ops.h index 3fa1443abc4..da8761a341a 100644 --- a/ggml/src/ggml-cpu/ops.h +++ b/ggml/src/ggml-cpu/ops.h @@ -103,6 +103,7 @@ void ggml_compute_forward_rwkv_wkv7(const struct ggml_compute_params * params, s void ggml_compute_forward_solve_tri(const struct ggml_compute_params * params, struct ggml_tensor * dst); void ggml_compute_forward_gla(const struct ggml_compute_params * params, struct ggml_tensor * dst); void ggml_compute_forward_gated_delta_net(const struct ggml_compute_params * params, struct ggml_tensor * dst); +void ggml_compute_forward_turbo_wht(const struct ggml_compute_params * params, struct ggml_tensor * dst); void ggml_compute_forward_map_custom1(const struct ggml_compute_params * params, struct ggml_tensor * dst); void ggml_compute_forward_map_custom2(const struct ggml_compute_params * params, struct ggml_tensor * dst); void ggml_compute_forward_map_custom3(const struct ggml_compute_params * params, struct ggml_tensor * dst); diff --git a/ggml/src/ggml-cuda/CMakeLists.txt b/ggml/src/ggml-cuda/CMakeLists.txt index 419862101d1..f2a797224af 100644 --- a/ggml/src/ggml-cuda/CMakeLists.txt +++ b/ggml/src/ggml-cuda/CMakeLists.txt @@ -120,7 +120,22 @@ if (CUDAToolkit_FOUND) template-instances/fattn-vec-instance-f16-f16.cu template-instances/fattn-vec-instance-q4_0-q4_0.cu template-instances/fattn-vec-instance-q8_0-q8_0.cu - template-instances/fattn-vec-instance-bf16-bf16.cu) + template-instances/fattn-vec-instance-bf16-bf16.cu + template-instances/fattn-vec-instance-turbo3_0-turbo3_0.cu + template-instances/fattn-vec-instance-turbo3_0-q8_0.cu + template-instances/fattn-vec-instance-q8_0-turbo3_0.cu + template-instances/fattn-vec-instance-turbo2_0-turbo2_0.cu + template-instances/fattn-vec-instance-turbo2_0-q8_0.cu + template-instances/fattn-vec-instance-q8_0-turbo2_0.cu + template-instances/fattn-vec-instance-turbo3_0-turbo2_0.cu + template-instances/fattn-vec-instance-turbo2_0-turbo3_0.cu + template-instances/fattn-vec-instance-turbo4_0-turbo4_0.cu + template-instances/fattn-vec-instance-turbo4_0-q8_0.cu + template-instances/fattn-vec-instance-q8_0-turbo4_0.cu + template-instances/fattn-vec-instance-turbo4_0-turbo3_0.cu + template-instances/fattn-vec-instance-turbo3_0-turbo4_0.cu + template-instances/fattn-vec-instance-turbo4_0-turbo2_0.cu + template-instances/fattn-vec-instance-turbo2_0-turbo4_0.cu) endif() ggml_add_backend_library(ggml-cuda diff --git a/ggml/src/ggml-cuda/convert.cu b/ggml/src/ggml-cuda/convert.cu index 79ccfe568a2..ca26089ee35 100644 --- a/ggml/src/ggml-cuda/convert.cu +++ b/ggml/src/ggml-cuda/convert.cu @@ -1,5 +1,6 @@ #include "convert.cuh" #include "dequantize.cuh" +#include "turbo-quant.cuh" #include @@ -756,6 +757,16 @@ to_fp16_cuda_t ggml_get_to_fp16_cuda(ggml_type type) { return dequantize_row_mxfp4_cuda; case GGML_TYPE_NVFP4: return dequantize_row_nvfp4_cuda; + case GGML_TYPE_TURBO3_0: + return dequantize_block_cont_cuda; + case GGML_TYPE_TURBO2_0: + return dequantize_block_cont_cuda; + case GGML_TYPE_TURBO4_0: + return dequantize_block_cont_cuda; + case GGML_TYPE_TQ4_1S: + return dequantize_block_cont_cuda; + case GGML_TYPE_TQ3_1S: + return dequantize_block_cont_cuda; case GGML_TYPE_F32: return convert_unary_cont_cuda; case GGML_TYPE_BF16: @@ -809,6 +820,16 @@ to_fp32_cuda_t ggml_get_to_fp32_cuda(ggml_type type) { return dequantize_row_mxfp4_cuda; case GGML_TYPE_NVFP4: return dequantize_row_nvfp4_cuda; + case GGML_TYPE_TURBO3_0: + return dequantize_block_cont_cuda; + case GGML_TYPE_TURBO2_0: + return dequantize_block_cont_cuda; + case GGML_TYPE_TURBO4_0: + return dequantize_block_cont_cuda; + case GGML_TYPE_TQ4_1S: + return dequantize_block_cont_cuda; + case GGML_TYPE_TQ3_1S: + return dequantize_block_cont_cuda; case GGML_TYPE_F16: return convert_unary_cont_cuda; case GGML_TYPE_BF16: @@ -832,6 +853,16 @@ to_fp16_nc_cuda_t ggml_get_to_fp16_nc_cuda(ggml_type type) { return dequantize_block_cuda; case GGML_TYPE_Q8_0: return dequantize_block_cuda; + case GGML_TYPE_TURBO3_0: + return dequantize_block_cuda; + case GGML_TYPE_TURBO2_0: + return dequantize_block_cuda; + case GGML_TYPE_TURBO4_0: + return dequantize_block_cuda; + case GGML_TYPE_TQ4_1S: + return dequantize_block_cuda; + case GGML_TYPE_TQ3_1S: + return dequantize_block_cuda; case GGML_TYPE_BF16: return convert_unary_cuda; default: @@ -874,6 +905,16 @@ to_fp32_nc_cuda_t ggml_get_to_fp32_nc_cuda(ggml_type type) { return dequantize_block_cuda; case GGML_TYPE_Q8_0: return dequantize_block_cuda; + case GGML_TYPE_TURBO3_0: + return dequantize_block_cuda; + case GGML_TYPE_TURBO2_0: + return dequantize_block_cuda; + case GGML_TYPE_TURBO4_0: + return dequantize_block_cuda; + case GGML_TYPE_TQ4_1S: + return dequantize_block_cuda; + case GGML_TYPE_TQ3_1S: + return dequantize_block_cuda; case GGML_TYPE_BF16: return convert_unary_cuda; default: diff --git a/ggml/src/ggml-cuda/dequantize.cuh b/ggml/src/ggml-cuda/dequantize.cuh index e060fb29fdc..157dfd3ea8d 100644 --- a/ggml/src/ggml-cuda/dequantize.cuh +++ b/ggml/src/ggml-cuda/dequantize.cuh @@ -1,4 +1,5 @@ #include "common.cuh" +#include "turbo-quant.cuh" static __device__ __forceinline__ void dequantize_q4_0(const void * vx, const int64_t ib, const int iqs, float2 & v){ const block_q4_0 * x = (const block_q4_0 *) vx; @@ -75,3 +76,104 @@ static __device__ __forceinline__ void dequantize_q8_0(const void * vx, const in v.x *= d; v.y *= d; } + +// Turbo4: 4-bit PolarQuant (nibble packed), block size 128 +// iqs is the element index within the block (even), produces elements iqs and iqs+1 +static __device__ __forceinline__ void dequantize_turbo4_0(const void * vx, const int64_t ib, const int iqs, float2 & v){ + const block_turbo4_0 * x = (const block_turbo4_0 *) vx; + const float norm = __half2float(x[ib].norm); + v.x = turbo4_dequant_element(&x[ib], iqs + 0, norm); + v.y = turbo4_dequant_element(&x[ib], iqs + 1, norm); +} + +// Turbo3: 3-bit PolarQuant (2-bit qs + 1-bit sign), block size 32 +// iqs is the element index within the block (even), produces elements iqs and iqs+1 +static __device__ __forceinline__ void dequantize_turbo3_0(const void * vx, const int64_t ib, const int iqs, float2 & v){ + const block_turbo3_0 * x = (const block_turbo3_0 *) vx; + const float norm = __half2float(x[ib].norm); + v.x = turbo3_dequant_element(&x[ib], iqs + 0, norm); + v.y = turbo3_dequant_element(&x[ib], iqs + 1, norm); +} + +// Turbo2: 2-bit PolarQuant (2-bit qs only, no sign), block size 32 +static __device__ __forceinline__ void dequantize_turbo2_0(const void * vx, const int64_t ib, const int iqs, float2 & v){ + const block_turbo2_0 * x = (const block_turbo2_0 *) vx; + const float norm = __half2float(x[ib].norm); + v.x = turbo2_dequant_element(&x[ib], iqs + 0, norm); + v.y = turbo2_dequant_element(&x[ib], iqs + 1, norm); +} + +// TQ4_1S: 4-bit weight type with inverse WHT, block size 32, dual half-block scales +// Cold path only (convert.cu) — dequants full block, applies inverse RHT, returns pair +static __device__ __forceinline__ void dequantize_tq4_1s(const void * vx, const int64_t ib, const int iqs, float2 & v) { + const block_tq4_1s * x = (const block_tq4_1s *) vx; + const float d0 = __half2float(x[ib].d0); + const float d1 = __half2float(x[ib].d1); + + // Dequant full block (centroid lookup + scale) + float buf[32]; + for (int j = 0; j < 32; j++) { + uint8_t idx = (x[ib].qs[j / 2] >> ((j & 1) * 4)) & 0xF; + float d = (j < 16) ? d0 : d1; + buf[j] = TQ4_CENTROIDS_WEIGHT[idx] * d; + } + + // Inverse RHT: WHT butterfly then normalize+unsign + for (int step = 1; step < 32; step <<= 1) { + for (int i = 0; i < 32; i += step << 1) { + for (int j = i; j < i + step; j++) { + float a = buf[j], b = buf[j + step]; + buf[j] = a + b; buf[j + step] = a - b; + } + } + } + const float inv_sqrt32 = 0.17677669529663688f; + for (int j = 0; j < 32; j++) buf[j] *= inv_sqrt32 * TQ_WEIGHT_SIGNS[j]; + + v.x = buf[iqs]; + v.y = buf[iqs + 1]; +} + +// TQ3_1S: 3-bit weight type with inverse WHT, block size 32, dual half-block scales +// 3-bit packing: 4 groups of 8 indices in 3 bytes each (24 bits = 8 * 3-bit) +static __device__ __forceinline__ void dequantize_tq3_1s(const void * vx, const int64_t ib, const int iqs, float2 & v) { + const block_tq3_1s * x = (const block_tq3_1s *) vx; + const float d0 = __half2float(x[ib].d0); + const float d1 = __half2float(x[ib].d1); + + // Unpack all 32 3-bit indices (4 groups of 8 in 3 bytes) + float buf[32]; + for (int g = 0; g < 4; g++) { + const uint8_t * qp = x[ib].qs + g * 3; + uint8_t idx[8]; + idx[0] = qp[0] & 7; + idx[1] = (qp[0] >> 3) & 7; + idx[2] = ((qp[0] >> 6) | (qp[1] << 2)) & 7; + idx[3] = (qp[1] >> 1) & 7; + idx[4] = (qp[1] >> 4) & 7; + idx[5] = ((qp[1] >> 7) | (qp[2] << 1)) & 7; + idx[6] = (qp[2] >> 2) & 7; + idx[7] = (qp[2] >> 5) & 7; + + for (int i = 0; i < 8; i++) { + int j = g * 8 + i; + float d = (j < 16) ? d0 : d1; + buf[j] = TQ3_CENTROIDS_WEIGHT[idx[i]] * d; + } + } + + // Inverse RHT: WHT butterfly then normalize+unsign + for (int step = 1; step < 32; step <<= 1) { + for (int i = 0; i < 32; i += step << 1) { + for (int j = i; j < i + step; j++) { + float a = buf[j], b = buf[j + step]; + buf[j] = a + b; buf[j + step] = a - b; + } + } + } + const float inv_sqrt32 = 0.17677669529663688f; + for (int j = 0; j < 32; j++) buf[j] *= inv_sqrt32 * TQ_WEIGHT_SIGNS[j]; + + v.x = buf[iqs]; + v.y = buf[iqs + 1]; +} diff --git a/ggml/src/ggml-cuda/fattn-common.cuh b/ggml/src/ggml-cuda/fattn-common.cuh index c59a4db3999..06d97da0823 100644 --- a/ggml/src/ggml-cuda/fattn-common.cuh +++ b/ggml/src/ggml-cuda/fattn-common.cuh @@ -3,6 +3,7 @@ #include "common.cuh" #include "convert.cuh" #include "vecdotq.cuh" +#include "turbo-quant.cuh" #include @@ -288,6 +289,164 @@ static __device__ __forceinline__ float vec_dot_fattn_vec_KQ_q8_0( return sum; } +// Turbo3 KQ dot product: dequantize K from turbo3 blocks, dot with Q (float2/half2) +// Uses float Q path (like f16), not q8_1 integer path. +// Q_v is half2[] or float2[] with D/2 pairs, partitioned nthreads-strided. +// +// Matches the f16 pattern: outer loop steps by nthreads*cpy_ne, inner loop +// processes cpy_ne pairs per thread per iteration so Q_v and K indices stay aligned. +// elem0 = 2*k_KQ is always even, so elem0 and elem0+1 always share the same +// turbo3 block (ib), qs byte, and signs byte — loaded once per pair. +template +static __device__ __forceinline__ float vec_dot_fattn_vec_KQ_turbo3_0( + const char * __restrict__ K_c, const void * __restrict__ Q_v, const int * __restrict__ Q_q8, const void * __restrict__ Q_ds_v) { + + const block_turbo3_0 * K_turbo = (const block_turbo3_0 *) K_c; + GGML_UNUSED(Q_q8); + GGML_UNUSED(Q_ds_v); + + constexpr int cpy_nb = ggml_cuda_get_max_cpy_bytes(); + constexpr int cpy_ne = cpy_nb / 4; + + float sum = 0.0f; + +#pragma unroll + for (int k_KQ_0 = 0; k_KQ_0 < D/2; k_KQ_0 += nthreads*cpy_ne) { +#pragma unroll + for (int k_KQ_1 = 0; k_KQ_1 < cpy_ne; ++k_KQ_1) { + const int k_KQ = k_KQ_0 + (threadIdx.x % nthreads)*cpy_ne + k_KQ_1; + + // elem0 is always even; elem0 and elem1 are always in the same block, + // the same qs byte (j0%4 ∈ {0,2}), and the same signs byte (j0%8 ∈ {0,2,4,6}). + const int elem0 = k_KQ * 2; // always even + const int ib = elem0 / QK_TURBO3; // shared block index + const int j0 = elem0 % QK_TURBO3; // always even, 0..30 + + // Single loads for the shared block fields + const float norm = __half2float(K_turbo[ib].norm); + const uint8_t qs_byte = K_turbo[ib].qs[j0 / 4]; // covers both j0 and j0+1 + const uint8_t sgn_byte = K_turbo[ib].signs[j0 / 8]; // covers both j0 and j0+1 + + // Extract 3-bit indices for elem0 and elem1 from shared bytes + const int shift = (j0 % 4) * 2; // 0 or 4 + const uint8_t idx0 = ((qs_byte >> shift) & 0x3) | (((sgn_byte >> (j0 % 8)) & 0x1) << 2); + const uint8_t idx1 = ((qs_byte >> (shift+2)) & 0x3) | (((sgn_byte >> (j0 % 8 + 1)) & 0x1) << 2); + + float2 kv; + kv.x = TURBO_CENTROIDS_3BIT[idx0] * norm; + kv.y = TURBO_CENTROIDS_3BIT[idx1] * norm; + +#ifdef V_DOT2_F32_F16_AVAILABLE + const half2 qv = ((const half2 *) Q_v)[k_KQ_0/nthreads + k_KQ_1]; + ggml_cuda_mad(sum, make_float2(kv.x, kv.y), __half22float2(qv)); +#else + const float2 qv = ((const float2 *) Q_v)[k_KQ_0/nthreads + k_KQ_1]; + sum += kv.x * qv.x + kv.y * qv.y; +#endif // V_DOT2_F32_F16_AVAILABLE + } + } + + return sum; +} + +// Turbo2 KQ dot product: dequantize K from turbo2 blocks, dot with Q (float2/half2) +// Same structure as turbo3 but reads 2-bit indices from qs only (no signs). +template +static __device__ __forceinline__ float vec_dot_fattn_vec_KQ_turbo2_0( + const char * __restrict__ K_c, const void * __restrict__ Q_v, const int * __restrict__ Q_q8, const void * __restrict__ Q_ds_v) { + + const block_turbo2_0 * K_turbo = (const block_turbo2_0 *) K_c; + GGML_UNUSED(Q_q8); + GGML_UNUSED(Q_ds_v); + + constexpr int cpy_nb = ggml_cuda_get_max_cpy_bytes(); + constexpr int cpy_ne = cpy_nb / 4; + + float sum = 0.0f; + +#pragma unroll + for (int k_KQ_0 = 0; k_KQ_0 < D/2; k_KQ_0 += nthreads*cpy_ne) { +#pragma unroll + for (int k_KQ_1 = 0; k_KQ_1 < cpy_ne; ++k_KQ_1) { + const int k_KQ = k_KQ_0 + (threadIdx.x % nthreads)*cpy_ne + k_KQ_1; + + const int elem0 = k_KQ * 2; + const int ib = elem0 / QK_TURBO2; + const int j0 = elem0 % QK_TURBO2; + + const float norm = __half2float(K_turbo[ib].norm); + const uint8_t qs_byte = K_turbo[ib].qs[j0 / 4]; + + const int shift = (j0 % 4) * 2; + const uint8_t idx0 = (qs_byte >> shift) & 0x3; + const uint8_t idx1 = (qs_byte >> (shift+2)) & 0x3; + + float2 kv; + kv.x = TURBO_CENTROIDS_2BIT[idx0] * norm; + kv.y = TURBO_CENTROIDS_2BIT[idx1] * norm; + +#ifdef V_DOT2_F32_F16_AVAILABLE + const half2 qv = ((const half2 *) Q_v)[k_KQ_0/nthreads + k_KQ_1]; + ggml_cuda_mad(sum, make_float2(kv.x, kv.y), __half22float2(qv)); +#else + const float2 qv = ((const float2 *) Q_v)[k_KQ_0/nthreads + k_KQ_1]; + sum += kv.x * qv.x + kv.y * qv.y; +#endif // V_DOT2_F32_F16_AVAILABLE + } + } + + return sum; +} + +// Turbo4 KQ dot product: dequantize K from turbo4 blocks, dot with Q (float2/half2) +// 4-bit nibble packed: qs[j/2] >> ((j%2)*4) & 0xF +template +static __device__ __forceinline__ float vec_dot_fattn_vec_KQ_turbo4_0( + const char * __restrict__ K_c, const void * __restrict__ Q_v, const int * __restrict__ Q_q8, const void * __restrict__ Q_ds_v) { + + const block_turbo4_0 * K_turbo = (const block_turbo4_0 *) K_c; + GGML_UNUSED(Q_q8); + GGML_UNUSED(Q_ds_v); + + constexpr int cpy_nb = ggml_cuda_get_max_cpy_bytes(); + constexpr int cpy_ne = cpy_nb / 4; + + float sum = 0.0f; + +#pragma unroll + for (int k_KQ_0 = 0; k_KQ_0 < D/2; k_KQ_0 += nthreads*cpy_ne) { +#pragma unroll + for (int k_KQ_1 = 0; k_KQ_1 < cpy_ne; ++k_KQ_1) { + const int k_KQ = k_KQ_0 + (threadIdx.x % nthreads)*cpy_ne + k_KQ_1; + + const int elem0 = k_KQ * 2; // always even + const int ib = elem0 / QK_TURBO4; // block index + const int j0 = elem0 % QK_TURBO4; // always even + + const float norm = __half2float(K_turbo[ib].norm); + // Both j0 and j0+1 are adjacent nibbles: j0/2 == (j0+1)/2 when j0 is even + const uint8_t qs_byte = K_turbo[ib].qs[j0 / 2]; + + const uint8_t idx0 = (qs_byte >> 0) & 0xF; // low nibble = j0 + const uint8_t idx1 = (qs_byte >> 4) & 0xF; // high nibble = j0+1 + + float2 kv; + kv.x = TURBO_CENTROIDS_4BIT[idx0] * norm; + kv.y = TURBO_CENTROIDS_4BIT[idx1] * norm; + +#ifdef V_DOT2_F32_F16_AVAILABLE + const half2 qv = ((const half2 *) Q_v)[k_KQ_0/nthreads + k_KQ_1]; + ggml_cuda_mad(sum, make_float2(kv.x, kv.y), __half22float2(qv)); +#else + const float2 qv = ((const float2 *) Q_v)[k_KQ_0/nthreads + k_KQ_1]; + sum += kv.x * qv.x + kv.y * qv.y; +#endif // V_DOT2_F32_F16_AVAILABLE + } + } + + return sum; +} + template static __device__ __forceinline__ void quantize_q8_1_to_shared( const float * __restrict__ x, const float scale, int * __restrict__ yq32, void * __restrict__ yds) { @@ -577,6 +736,186 @@ static __device__ __forceinline__ void dequantize_V_q8_0(const void * __restrict } } +// Turbo3 V dequantize: extract `ne` float/half values at position i0. +// +// Optimised for the ne==4 path (used by the VEC kernel with turbo3 V): +// i0 is always a multiple of 4 from the VEC kernel access pattern, so all 4 +// elements share one qs byte and one signs byte — we load each once. +template +static __device__ __forceinline__ void dequantize_V_turbo3_0(const void * __restrict__ vx, void * __restrict__ dst, const int64_t i0) { + const block_turbo3_0 * x = (const block_turbo3_0 *) vx; + + const int64_t ib = i0 / QK_TURBO3; + const int j0 = i0 % QK_TURBO3; + const float norm = __half2float(x[ib].norm); + + static_assert(ne == 2 || ne == 4, "bad ne"); + + if constexpr (ne == 4) { + // When j0 % 4 == 0 (always true from VEC kernel), all 4 elements share one + // qs byte (4 elements per byte) and one signs byte (8 elements per byte). + const uint8_t qs_byte = x[ib].qs[j0 / 4]; + const uint8_t sgn_byte = x[ib].signs[j0 / 8]; + const int shift_s = j0 % 8; // 0 or 4 + + const uint8_t idx0 = ((qs_byte >> 0) & 0x3) | (((sgn_byte >> (shift_s+0)) & 0x1) << 2); + const uint8_t idx1 = ((qs_byte >> 2) & 0x3) | (((sgn_byte >> (shift_s+1)) & 0x1) << 2); + const uint8_t idx2 = ((qs_byte >> 4) & 0x3) | (((sgn_byte >> (shift_s+2)) & 0x1) << 2); + const uint8_t idx3 = ((qs_byte >> 6) & 0x3) | (((sgn_byte >> (shift_s+3)) & 0x1) << 2); + +#ifdef FP16_AVAILABLE + if constexpr (std::is_same_v) { + ((half2 *) dst)[0] = make_half2( + __float2half(TURBO_CENTROIDS_3BIT[idx0] * norm), + __float2half(TURBO_CENTROIDS_3BIT[idx1] * norm)); + ((half2 *) dst)[1] = make_half2( + __float2half(TURBO_CENTROIDS_3BIT[idx2] * norm), + __float2half(TURBO_CENTROIDS_3BIT[idx3] * norm)); + } else +#endif // FP16_AVAILABLE + if constexpr (std::is_same_v) { + ((float2 *) dst)[0] = make_float2( + TURBO_CENTROIDS_3BIT[idx0] * norm, + TURBO_CENTROIDS_3BIT[idx1] * norm); + ((float2 *) dst)[1] = make_float2( + TURBO_CENTROIDS_3BIT[idx2] * norm, + TURBO_CENTROIDS_3BIT[idx3] * norm); + } else { + static_assert(std::is_same_v, "unsupported type"); + } + } else { // ne == 2 +#ifdef FP16_AVAILABLE + if constexpr (std::is_same_v) { + float v0 = turbo3_dequant_element(&x[ib], j0, norm); + float v1 = turbo3_dequant_element(&x[ib], j0+1, norm); + ((half2 *) dst)[0] = make_half2(__float2half(v0), __float2half(v1)); + } else +#endif // FP16_AVAILABLE + if constexpr (std::is_same_v) { + ((float *) dst)[0] = turbo3_dequant_element(&x[ib], j0, norm); + ((float *) dst)[1] = turbo3_dequant_element(&x[ib], j0+1, norm); + } else { + static_assert(std::is_same_v, "unsupported type"); + } + } +} + +// Turbo2 V dequantize: extract `ne` float/half values at position i0. +template +static __device__ __forceinline__ void dequantize_V_turbo2_0(const void * __restrict__ vx, void * __restrict__ dst, const int64_t i0) { + const block_turbo2_0 * x = (const block_turbo2_0 *) vx; + + const int64_t ib = i0 / QK_TURBO2; + const int j0 = i0 % QK_TURBO2; + const float norm = __half2float(x[ib].norm); + + static_assert(ne == 2 || ne == 4, "bad ne"); + + if constexpr (ne == 4) { + const uint8_t qs_byte = x[ib].qs[j0 / 4]; + + const uint8_t idx0 = (qs_byte >> 0) & 0x3; + const uint8_t idx1 = (qs_byte >> 2) & 0x3; + const uint8_t idx2 = (qs_byte >> 4) & 0x3; + const uint8_t idx3 = (qs_byte >> 6) & 0x3; + +#ifdef FP16_AVAILABLE + if constexpr (std::is_same_v) { + ((half2 *) dst)[0] = make_half2( + __float2half(TURBO_CENTROIDS_2BIT[idx0] * norm), + __float2half(TURBO_CENTROIDS_2BIT[idx1] * norm)); + ((half2 *) dst)[1] = make_half2( + __float2half(TURBO_CENTROIDS_2BIT[idx2] * norm), + __float2half(TURBO_CENTROIDS_2BIT[idx3] * norm)); + } else +#endif // FP16_AVAILABLE + if constexpr (std::is_same_v) { + ((float2 *) dst)[0] = make_float2( + TURBO_CENTROIDS_2BIT[idx0] * norm, + TURBO_CENTROIDS_2BIT[idx1] * norm); + ((float2 *) dst)[1] = make_float2( + TURBO_CENTROIDS_2BIT[idx2] * norm, + TURBO_CENTROIDS_2BIT[idx3] * norm); + } else { + static_assert(std::is_same_v, "unsupported type"); + } + } else { // ne == 2 +#ifdef FP16_AVAILABLE + if constexpr (std::is_same_v) { + float v0 = turbo2_dequant_element(&x[ib], j0, norm); + float v1 = turbo2_dequant_element(&x[ib], j0+1, norm); + ((half2 *) dst)[0] = make_half2(__float2half(v0), __float2half(v1)); + } else +#endif // FP16_AVAILABLE + if constexpr (std::is_same_v) { + ((float *) dst)[0] = turbo2_dequant_element(&x[ib], j0, norm); + ((float *) dst)[1] = turbo2_dequant_element(&x[ib], j0+1, norm); + } else { + static_assert(std::is_same_v, "unsupported type"); + } + } +} + +// Turbo4 V dequantize: extract `ne` float/half values at position i0. +// 4-bit nibble packed, block size 128. +template +static __device__ __forceinline__ void dequantize_V_turbo4_0(const void * __restrict__ vx, void * __restrict__ dst, const int64_t i0) { + const block_turbo4_0 * x = (const block_turbo4_0 *) vx; + + const int64_t ib = i0 / QK_TURBO4; + const int j0 = i0 % QK_TURBO4; + const float norm = __half2float(x[ib].norm); + + static_assert(ne == 2 || ne == 4, "bad ne"); + + if constexpr (ne == 4) { + // j0 is always a multiple of 4 from the VEC kernel access pattern. + // 4 consecutive elements span 2 qs bytes: j0/2 and j0/2+1. + const uint8_t qs_byte0 = x[ib].qs[j0 / 2]; // elements j0, j0+1 + const uint8_t qs_byte1 = x[ib].qs[j0 / 2 + 1]; // elements j0+2, j0+3 + + const uint8_t idx0 = (qs_byte0 >> 0) & 0xF; + const uint8_t idx1 = (qs_byte0 >> 4) & 0xF; + const uint8_t idx2 = (qs_byte1 >> 0) & 0xF; + const uint8_t idx3 = (qs_byte1 >> 4) & 0xF; + +#ifdef FP16_AVAILABLE + if constexpr (std::is_same_v) { + ((half2 *) dst)[0] = make_half2( + __float2half(TURBO_CENTROIDS_4BIT[idx0] * norm), + __float2half(TURBO_CENTROIDS_4BIT[idx1] * norm)); + ((half2 *) dst)[1] = make_half2( + __float2half(TURBO_CENTROIDS_4BIT[idx2] * norm), + __float2half(TURBO_CENTROIDS_4BIT[idx3] * norm)); + } else +#endif // FP16_AVAILABLE + if constexpr (std::is_same_v) { + ((float2 *) dst)[0] = make_float2( + TURBO_CENTROIDS_4BIT[idx0] * norm, + TURBO_CENTROIDS_4BIT[idx1] * norm); + ((float2 *) dst)[1] = make_float2( + TURBO_CENTROIDS_4BIT[idx2] * norm, + TURBO_CENTROIDS_4BIT[idx3] * norm); + } else { + static_assert(std::is_same_v, "unsupported type"); + } + } else { // ne == 2 +#ifdef FP16_AVAILABLE + if constexpr (std::is_same_v) { + float v0 = turbo4_dequant_element(&x[ib], j0, norm); + float v1 = turbo4_dequant_element(&x[ib], j0+1, norm); + ((half2 *) dst)[0] = make_half2(__float2half(v0), __float2half(v1)); + } else +#endif // FP16_AVAILABLE + if constexpr (std::is_same_v) { + ((float *) dst)[0] = turbo4_dequant_element(&x[ib], j0, norm); + ((float *) dst)[1] = turbo4_dequant_element(&x[ib], j0+1, norm); + } else { + static_assert(std::is_same_v, "unsupported type"); + } + } +} + template constexpr __device__ vec_dot_KQ_t get_vec_dot_KQ() { if constexpr (type_K == GGML_TYPE_F16) { @@ -593,6 +932,12 @@ constexpr __device__ vec_dot_KQ_t get_vec_dot_KQ() { return vec_dot_fattn_vec_KQ_q8_0; } else if constexpr (type_K == GGML_TYPE_BF16) { return vec_dot_fattn_vec_KQ_bf16; + } else if constexpr (type_K == GGML_TYPE_TURBO3_0) { + return vec_dot_fattn_vec_KQ_turbo3_0; + } else if constexpr (type_K == GGML_TYPE_TURBO2_0) { + return vec_dot_fattn_vec_KQ_turbo2_0; + } else if constexpr (type_K == GGML_TYPE_TURBO4_0) { + return vec_dot_fattn_vec_KQ_turbo4_0; } else { static_assert(type_K == -1, "bad type"); return nullptr; @@ -615,6 +960,12 @@ constexpr __device__ dequantize_V_t get_dequantize_V() { return dequantize_V_q8_0; } else if constexpr (type_V == GGML_TYPE_BF16) { return dequantize_V_bf16; + } else if constexpr (type_V == GGML_TYPE_TURBO3_0) { + return dequantize_V_turbo3_0; + } else if constexpr (type_V == GGML_TYPE_TURBO2_0) { + return dequantize_V_turbo2_0; + } else if constexpr (type_V == GGML_TYPE_TURBO4_0) { + return dequantize_V_turbo4_0; } else { static_assert(type_V == -1, "bad type"); return nullptr; diff --git a/ggml/src/ggml-cuda/fattn-mma-f16.cuh b/ggml/src/ggml-cuda/fattn-mma-f16.cuh index b613ae61fb8..8989b313810 100644 --- a/ggml/src/ggml-cuda/fattn-mma-f16.cuh +++ b/ggml/src/ggml-cuda/fattn-mma-f16.cuh @@ -76,6 +76,11 @@ static constexpr __host__ __device__ fattn_mma_config ggml_cuda_fattn_mma_get_co GGML_CUDA_FATTN_MMA_CONFIG_CASE(576, 512, 32, 128, 2, 32, 160, 128, 128, 1, false); GGML_CUDA_FATTN_MMA_CONFIG_CASE(576, 512, 64, 256, 1, 32, 160, 128, 128, 1, false); + GGML_CUDA_FATTN_MMA_CONFIG_CASE(640, 512, 8, 64, 4, 32, 288, 256, 128, 1, false); + GGML_CUDA_FATTN_MMA_CONFIG_CASE(640, 512, 16, 64, 4, 32, 288, 256, 128, 1, false); + GGML_CUDA_FATTN_MMA_CONFIG_CASE(640, 512, 32, 128, 2, 32, 160, 128, 128, 1, false); + GGML_CUDA_FATTN_MMA_CONFIG_CASE(640, 512, 64, 256, 1, 32, 160, 128, 128, 1, false); + return fattn_mma_config(32, 1, 0, 0, 0, 0, 0, false); } @@ -95,6 +100,11 @@ static constexpr __host__ __device__ fattn_mma_config ggml_cuda_fattn_mma_get_co GGML_CUDA_FATTN_MMA_CONFIG_CASE(576, 512, 32, 128, 2, 32, 160, 128, 128, 1, false); GGML_CUDA_FATTN_MMA_CONFIG_CASE(576, 512, 64, 256, 1, 32, 160, 128, 128, 1, false); + GGML_CUDA_FATTN_MMA_CONFIG_CASE(640, 512, 8, 64, 4, 32, 96, 64, 128, 1, false); + GGML_CUDA_FATTN_MMA_CONFIG_CASE(640, 512, 16, 64, 4, 32, 96, 64, 128, 1, false); + GGML_CUDA_FATTN_MMA_CONFIG_CASE(640, 512, 32, 128, 2, 32, 160, 128, 128, 1, false); + GGML_CUDA_FATTN_MMA_CONFIG_CASE(640, 512, 64, 256, 1, 32, 160, 128, 128, 1, false); + return ggml_cuda_fattn_mma_get_config_ampere(DKQ, DV, ncols); } @@ -109,6 +119,11 @@ static constexpr __host__ __device__ fattn_mma_config ggml_cuda_fattn_mma_get_co GGML_CUDA_FATTN_MMA_CONFIG_CASE(576, 512, 32, 128, 2, 32, 160, 128, 64, 1, false); GGML_CUDA_FATTN_MMA_CONFIG_CASE(576, 512, 64, 256, 1, 32, 160, 128, 64, 1, false); + GGML_CUDA_FATTN_MMA_CONFIG_CASE(640, 512, 8, 64, 4, 32, 288, 256, 64, 1, false); + GGML_CUDA_FATTN_MMA_CONFIG_CASE(640, 512, 16, 64, 4, 32, 288, 256, 64, 1, false); + GGML_CUDA_FATTN_MMA_CONFIG_CASE(640, 512, 32, 128, 2, 32, 160, 128, 64, 1, false); + GGML_CUDA_FATTN_MMA_CONFIG_CASE(640, 512, 64, 256, 1, 32, 160, 128, 64, 1, false); + // TODO tune specifically for Volta return ggml_cuda_fattn_mma_get_config_ampere(DKQ, DV, ncols); } @@ -126,6 +141,10 @@ static constexpr __host__ __device__ fattn_mma_config ggml_cuda_fattn_mma_get_co GGML_CUDA_FATTN_MMA_CONFIG_CASE(576, 512, 32, 128, 2, 32, 160, 128, 128, 1, false); GGML_CUDA_FATTN_MMA_CONFIG_CASE(576, 512, 64, 256, 1, 32, 160, 128, 128, 1, false); + GGML_CUDA_FATTN_MMA_CONFIG_CASE(640, 512, 16, 64, 4, 32, 96, 64, 128, 1, false); + GGML_CUDA_FATTN_MMA_CONFIG_CASE(640, 512, 32, 128, 2, 32, 160, 128, 128, 1, false); + GGML_CUDA_FATTN_MMA_CONFIG_CASE(640, 512, 64, 256, 1, 32, 160, 128, 128, 1, false); + // TODO tune specifically for RDNA return ggml_cuda_fattn_mma_get_config_ampere(DKQ, DV, ncols); } @@ -1854,3 +1873,8 @@ extern DECL_FATTN_MMA_F16_CASE(576, 512, 8, 4); extern DECL_FATTN_MMA_F16_CASE(576, 512, 16, 4); extern DECL_FATTN_MMA_F16_CASE(576, 512, 1, 32); extern DECL_FATTN_MMA_F16_CASE(576, 512, 2, 32); + +// D=640: padded turbo KV cache for GLM-4.7 Flash (ncols2=16 only) +extern DECL_FATTN_MMA_F16_CASE(640, 512, 1, 16); +extern DECL_FATTN_MMA_F16_CASE(640, 512, 2, 16); +extern DECL_FATTN_MMA_F16_CASE(640, 512, 4, 16); diff --git a/ggml/src/ggml-cuda/fattn-tile.cu b/ggml/src/ggml-cuda/fattn-tile.cu index 25b16e83cac..5680f842da9 100644 --- a/ggml/src/ggml-cuda/fattn-tile.cu +++ b/ggml/src/ggml-cuda/fattn-tile.cu @@ -42,10 +42,17 @@ void ggml_cuda_flash_attn_ext_tile(ggml_backend_cuda_context & ctx, ggml_tensor GGML_ASSERT(V->ne[0] == K->ne[0]); ggml_cuda_flash_attn_ext_tile_case<512, 512>(ctx, dst); } break; +#ifndef GGML_USE_HIP + // D>=576 tile kernels exceed HIP local memory limit (67584 > 65536) case 576: { GGML_ASSERT(V->ne[0] == 512); ggml_cuda_flash_attn_ext_tile_case<576, 512>(ctx, dst); } break; + case 640: { + GGML_ASSERT(V->ne[0] == 512); + ggml_cuda_flash_attn_ext_tile_case<640, 512>(ctx, dst); + } break; +#endif default: { GGML_ABORT("Unsupported head size"); } break; diff --git a/ggml/src/ggml-cuda/fattn-tile.cuh b/ggml/src/ggml-cuda/fattn-tile.cuh index 26721cc4c7d..be4f3281a5b 100644 --- a/ggml/src/ggml-cuda/fattn-tile.cuh +++ b/ggml/src/ggml-cuda/fattn-tile.cuh @@ -76,6 +76,10 @@ static constexpr __host__ __device__ uint32_t ggml_cuda_fattn_tile_get_config_nv GGML_CUDA_FATTN_TILE_CONFIG_CASE(576, 512, 8, 256, 2, 64, 64) GGML_CUDA_FATTN_TILE_CONFIG_CASE(576, 512, 16, 256, 2, 64, 64) + GGML_CUDA_FATTN_TILE_CONFIG_CASE(640, 512, 4, 128, 2, 64, 64) + GGML_CUDA_FATTN_TILE_CONFIG_CASE(640, 512, 8, 256, 2, 64, 64) + GGML_CUDA_FATTN_TILE_CONFIG_CASE(640, 512, 16, 256, 2, 64, 64) + return 0; } @@ -136,6 +140,10 @@ static constexpr __host__ __device__ uint32_t ggml_cuda_fattn_tile_get_config_nv GGML_CUDA_FATTN_TILE_CONFIG_CASE(576, 512, 8, 256, 2, 32, 64) GGML_CUDA_FATTN_TILE_CONFIG_CASE(576, 512, 16, 256, 2, 32, 64) + GGML_CUDA_FATTN_TILE_CONFIG_CASE(640, 512, 4, 128, 2, 32, 64) + GGML_CUDA_FATTN_TILE_CONFIG_CASE(640, 512, 8, 256, 2, 32, 64) + GGML_CUDA_FATTN_TILE_CONFIG_CASE(640, 512, 16, 256, 2, 32, 64) + return 0; } @@ -205,6 +213,11 @@ static constexpr __host__ __device__ uint32_t ggml_cuda_fattn_tile_get_config_am GGML_CUDA_FATTN_TILE_CONFIG_CASE(576, 512, 16, 256, 2, 64, 64) GGML_CUDA_FATTN_TILE_CONFIG_CASE(576, 512, 32, 512, 1, 128, 64) + GGML_CUDA_FATTN_TILE_CONFIG_CASE(640, 512, 4, 128, 2, 64, 64) + GGML_CUDA_FATTN_TILE_CONFIG_CASE(640, 512, 8, 256, 2, 64, 64) + GGML_CUDA_FATTN_TILE_CONFIG_CASE(640, 512, 16, 256, 2, 64, 64) + GGML_CUDA_FATTN_TILE_CONFIG_CASE(640, 512, 32, 512, 1, 128, 64) + return 0; } @@ -274,6 +287,11 @@ static constexpr __host__ __device__ uint32_t ggml_cuda_fattn_tile_get_config_am GGML_CUDA_FATTN_TILE_CONFIG_CASE(576, 512, 16, 256, 4, 64, 64) GGML_CUDA_FATTN_TILE_CONFIG_CASE(576, 512, 32, 256, 2, 128, 64) + GGML_CUDA_FATTN_TILE_CONFIG_CASE(640, 512, 4, 128, 2, 64, 64) + GGML_CUDA_FATTN_TILE_CONFIG_CASE(640, 512, 8, 256, 2, 64, 64) + GGML_CUDA_FATTN_TILE_CONFIG_CASE(640, 512, 16, 256, 4, 64, 64) + GGML_CUDA_FATTN_TILE_CONFIG_CASE(640, 512, 32, 256, 2, 128, 64) + return 0; } @@ -1205,7 +1223,7 @@ static void launch_fattn_tile_switch_ncols2(ggml_backend_cuda_context & ctx, ggm const int gqa_ratio = Q->ne[2] / K->ne[2]; // On NVIDIA (Pascal and older) the GQA optimizations seem to be detrimental in some cases. - // However, for DKQ == 576, DV == 512 only the kernel variant with GQA optimizations is implemented. + // However, for DKQ == 576/640, DV == 512 only the kernel variant with GQA optimizations is implemented. const bool nvidia = GGML_CUDA_CC_IS_NVIDIA(ggml_cuda_info().devices[ggml_cuda_get_device()].cc); const int gqa_limit = nvidia && gqa_ratio <= 4 && DV <= 256 ? 16 : INT_MAX; const bool use_gqa_opt = mask && max_bias == 0.0f && Q->ne[1] <= gqa_limit && K->ne[1] % FATTN_KQ_STRIDE == 0; @@ -1277,3 +1295,4 @@ extern DECL_FATTN_TILE_CASE(128, 128); extern DECL_FATTN_TILE_CASE(256, 256); extern DECL_FATTN_TILE_CASE(512, 512); extern DECL_FATTN_TILE_CASE(576, 512); +extern DECL_FATTN_TILE_CASE(640, 512); diff --git a/ggml/src/ggml-cuda/fattn-vec.cuh b/ggml/src/ggml-cuda/fattn-vec.cuh index f0bd42a5761..40270a192dd 100644 --- a/ggml/src/ggml-cuda/fattn-vec.cuh +++ b/ggml/src/ggml-cuda/fattn-vec.cuh @@ -75,17 +75,20 @@ static __global__ void flash_attn_ext_vec( #endif // GGML_USE_HIP constexpr int nthreads = ggml_cuda_fattn_vec_get_nthreads_device(); - constexpr int nthreads_KQ = (type_K == GGML_TYPE_F16 || type_K == GGML_TYPE_BF16) ? 128 / cpy_nb : nthreads_KQ_q; - constexpr int nthreads_V = (type_V == GGML_TYPE_F16 || type_V == GGML_TYPE_BF16) ? 128 / cpy_nb : nthreads_V_q; + // Turbo3 uses the float Q path (like f16/bf16), not q8_1 integer path + constexpr bool K_is_unquantized = (type_K == GGML_TYPE_F16 || type_K == GGML_TYPE_BF16 || type_K == GGML_TYPE_TURBO3_0 || type_K == GGML_TYPE_TURBO2_0 || type_K == GGML_TYPE_TURBO4_0); + constexpr bool V_is_unquantized = (type_V == GGML_TYPE_F16 || type_V == GGML_TYPE_BF16 || type_V == GGML_TYPE_TURBO3_0 || type_V == GGML_TYPE_TURBO2_0 || type_V == GGML_TYPE_TURBO4_0); + constexpr int nthreads_KQ = K_is_unquantized ? 128 / cpy_nb : nthreads_KQ_q; + constexpr int nthreads_V = V_is_unquantized ? ((type_V == GGML_TYPE_TURBO3_0 || type_V == GGML_TYPE_TURBO2_0 || type_V == GGML_TYPE_TURBO4_0) ? nthreads_V_q : 128 / cpy_nb) : nthreads_V_q; static_assert(WARP_SIZE % nthreads_KQ == 0, "bad nthreads_K"); static_assert(WARP_SIZE % nthreads_V == 0, "bad nthreads_V"); - constexpr int V_rows_per_thread = (type_V == GGML_TYPE_F16 || type_V == GGML_TYPE_BF16) ? 2*cpy_ne : 4; + constexpr int V_rows_per_thread = V_is_unquantized ? ((type_V == GGML_TYPE_TURBO3_0 || type_V == GGML_TYPE_TURBO2_0 || type_V == GGML_TYPE_TURBO4_0) ? 4 : 2*cpy_ne) : 4; constexpr int V_cols_per_iter = WARP_SIZE / nthreads_V; constexpr vec_dot_KQ_t vec_dot_KQ = get_vec_dot_KQ(); - constexpr bool Q_q8_1 = type_K != GGML_TYPE_F16 && type_K != GGML_TYPE_BF16; + constexpr bool Q_q8_1 = !K_is_unquantized; #ifdef V_DOT2_F32_F16_AVAILABLE constexpr dequantize_V_t dequantize_V = get_dequantize_V(); #else @@ -120,6 +123,14 @@ static __global__ void flash_attn_ext_vec( __shared__ float KQ[ne_KQ > ne_combine ? ne_KQ : ne_combine]; #endif // V_DOT2_F32_F16_AVAILABLE + // Sparse V: skip V dequant for positions with negligible attention weights. + // At long context, most V positions contribute < 1e-6 to the output — skipping + // their dequant saves significant compute (especially for quantized V types). + constexpr float sparse_v_threshold_f = 1e-6f; +#ifdef V_DOT2_F32_F16_AVAILABLE + const half sparse_v_threshold_h = __float2half(sparse_v_threshold_f); +#endif + float KQ_max[ncols]; float KQ_sum[ncols]; #pragma unroll @@ -320,6 +331,17 @@ static __global__ void flash_attn_ext_vec( for (int j = 0; j < ncols; ++j) { KQ_k[j] = __half2half2(KQ[j*nthreads + k]); } + + // Sparse V: skip V dequant if all attention weights for this position are negligible + { + bool dominated = true; +#pragma unroll + for (int j = 0; j < ncols; ++j) { + if (__hgt(__low2half(KQ_k[j]), sparse_v_threshold_h)) { dominated = false; break; } + } + if (dominated) { continue; } + } + #pragma unroll for (int i_VKQ_0 = 0; i_VKQ_0 < D/2; i_VKQ_0 += nthreads_V*V_rows_per_thread/2) { half2 tmp[V_rows_per_thread/2]; @@ -349,6 +371,17 @@ static __global__ void flash_attn_ext_vec( for (int j = 0; j < ncols; ++j) { KQ_k[j] = KQ[j*nthreads + k]; } + + // Sparse V: skip V dequant if all attention weights for this position are negligible + { + bool dominated = true; +#pragma unroll + for (int j = 0; j < ncols; ++j) { + if (KQ_k[j] >= sparse_v_threshold_f) { dominated = false; break; } + } + if (dominated) { continue; } + } + #pragma unroll for (int i_VKQ_0 = 0; i_VKQ_0 < D/2; i_VKQ_0 += nthreads_V*V_rows_per_thread/2) { float2 tmp[V_rows_per_thread/2]; @@ -598,3 +631,72 @@ EXTERN_DECL_FATTN_VEC_CASES(256, GGML_TYPE_Q5_0) EXTERN_DECL_FATTN_VEC_CASES(256, GGML_TYPE_Q5_1) EXTERN_DECL_FATTN_VEC_CASES(256, GGML_TYPE_Q8_0) EXTERN_DECL_FATTN_VEC_CASES(256, GGML_TYPE_BF16) + +// TurboQuant3 — turbo3 K + turbo3 V (KV cache uses same type) +extern DECL_FATTN_VEC_CASE( 64, GGML_TYPE_TURBO3_0, GGML_TYPE_TURBO3_0); +extern DECL_FATTN_VEC_CASE(128, GGML_TYPE_TURBO3_0, GGML_TYPE_TURBO3_0); +extern DECL_FATTN_VEC_CASE(256, GGML_TYPE_TURBO3_0, GGML_TYPE_TURBO3_0); + +// Mixed turbo3/q8_0 KV cache types +extern DECL_FATTN_VEC_CASE( 64, GGML_TYPE_TURBO3_0, GGML_TYPE_Q8_0); +extern DECL_FATTN_VEC_CASE(128, GGML_TYPE_TURBO3_0, GGML_TYPE_Q8_0); +extern DECL_FATTN_VEC_CASE(256, GGML_TYPE_TURBO3_0, GGML_TYPE_Q8_0); + +extern DECL_FATTN_VEC_CASE( 64, GGML_TYPE_Q8_0, GGML_TYPE_TURBO3_0); +extern DECL_FATTN_VEC_CASE(128, GGML_TYPE_Q8_0, GGML_TYPE_TURBO3_0); +extern DECL_FATTN_VEC_CASE(256, GGML_TYPE_Q8_0, GGML_TYPE_TURBO3_0); + +// TurboQuant2 -- turbo2 K + turbo2 V +extern DECL_FATTN_VEC_CASE( 64, GGML_TYPE_TURBO2_0, GGML_TYPE_TURBO2_0); +extern DECL_FATTN_VEC_CASE(128, GGML_TYPE_TURBO2_0, GGML_TYPE_TURBO2_0); +extern DECL_FATTN_VEC_CASE(256, GGML_TYPE_TURBO2_0, GGML_TYPE_TURBO2_0); + +// Mixed turbo2/q8_0 KV cache types +extern DECL_FATTN_VEC_CASE( 64, GGML_TYPE_TURBO2_0, GGML_TYPE_Q8_0); +extern DECL_FATTN_VEC_CASE(128, GGML_TYPE_TURBO2_0, GGML_TYPE_Q8_0); +extern DECL_FATTN_VEC_CASE(256, GGML_TYPE_TURBO2_0, GGML_TYPE_Q8_0); + +extern DECL_FATTN_VEC_CASE( 64, GGML_TYPE_Q8_0, GGML_TYPE_TURBO2_0); +extern DECL_FATTN_VEC_CASE(128, GGML_TYPE_Q8_0, GGML_TYPE_TURBO2_0); +extern DECL_FATTN_VEC_CASE(256, GGML_TYPE_Q8_0, GGML_TYPE_TURBO2_0); + +// Mixed turbo3/turbo2 KV cache types +extern DECL_FATTN_VEC_CASE( 64, GGML_TYPE_TURBO3_0, GGML_TYPE_TURBO2_0); +extern DECL_FATTN_VEC_CASE(128, GGML_TYPE_TURBO3_0, GGML_TYPE_TURBO2_0); +extern DECL_FATTN_VEC_CASE(256, GGML_TYPE_TURBO3_0, GGML_TYPE_TURBO2_0); + +extern DECL_FATTN_VEC_CASE( 64, GGML_TYPE_TURBO2_0, GGML_TYPE_TURBO3_0); +extern DECL_FATTN_VEC_CASE(128, GGML_TYPE_TURBO2_0, GGML_TYPE_TURBO3_0); +extern DECL_FATTN_VEC_CASE(256, GGML_TYPE_TURBO2_0, GGML_TYPE_TURBO3_0); + +// TurboQuant4 — turbo4 K + turbo4 V (KV cache uses same type) +extern DECL_FATTN_VEC_CASE( 64, GGML_TYPE_TURBO4_0, GGML_TYPE_TURBO4_0); +extern DECL_FATTN_VEC_CASE(128, GGML_TYPE_TURBO4_0, GGML_TYPE_TURBO4_0); +extern DECL_FATTN_VEC_CASE(256, GGML_TYPE_TURBO4_0, GGML_TYPE_TURBO4_0); + +// Mixed turbo4/q8_0 KV cache types +extern DECL_FATTN_VEC_CASE( 64, GGML_TYPE_TURBO4_0, GGML_TYPE_Q8_0); +extern DECL_FATTN_VEC_CASE(128, GGML_TYPE_TURBO4_0, GGML_TYPE_Q8_0); +extern DECL_FATTN_VEC_CASE(256, GGML_TYPE_TURBO4_0, GGML_TYPE_Q8_0); + +extern DECL_FATTN_VEC_CASE( 64, GGML_TYPE_Q8_0, GGML_TYPE_TURBO4_0); +extern DECL_FATTN_VEC_CASE(128, GGML_TYPE_Q8_0, GGML_TYPE_TURBO4_0); +extern DECL_FATTN_VEC_CASE(256, GGML_TYPE_Q8_0, GGML_TYPE_TURBO4_0); + +// Mixed turbo4/turbo3 KV cache types +extern DECL_FATTN_VEC_CASE( 64, GGML_TYPE_TURBO4_0, GGML_TYPE_TURBO3_0); +extern DECL_FATTN_VEC_CASE(128, GGML_TYPE_TURBO4_0, GGML_TYPE_TURBO3_0); +extern DECL_FATTN_VEC_CASE(256, GGML_TYPE_TURBO4_0, GGML_TYPE_TURBO3_0); + +extern DECL_FATTN_VEC_CASE( 64, GGML_TYPE_TURBO3_0, GGML_TYPE_TURBO4_0); +extern DECL_FATTN_VEC_CASE(128, GGML_TYPE_TURBO3_0, GGML_TYPE_TURBO4_0); +extern DECL_FATTN_VEC_CASE(256, GGML_TYPE_TURBO3_0, GGML_TYPE_TURBO4_0); + +// Mixed turbo4/turbo2 KV cache types +extern DECL_FATTN_VEC_CASE( 64, GGML_TYPE_TURBO4_0, GGML_TYPE_TURBO2_0); +extern DECL_FATTN_VEC_CASE(128, GGML_TYPE_TURBO4_0, GGML_TYPE_TURBO2_0); +extern DECL_FATTN_VEC_CASE(256, GGML_TYPE_TURBO4_0, GGML_TYPE_TURBO2_0); + +extern DECL_FATTN_VEC_CASE( 64, GGML_TYPE_TURBO2_0, GGML_TYPE_TURBO4_0); +extern DECL_FATTN_VEC_CASE(128, GGML_TYPE_TURBO2_0, GGML_TYPE_TURBO4_0); +extern DECL_FATTN_VEC_CASE(256, GGML_TYPE_TURBO2_0, GGML_TYPE_TURBO4_0); diff --git a/ggml/src/ggml-cuda/fattn.cu b/ggml/src/ggml-cuda/fattn.cu index addf93205ef..ee547d72432 100644 --- a/ggml/src/ggml-cuda/fattn.cu +++ b/ggml/src/ggml-cuda/fattn.cu @@ -195,6 +195,17 @@ static void ggml_cuda_flash_attn_ext_mma_f16(ggml_backend_cuda_context & ctx, gg ggml_cuda_flash_attn_ext_mma_f16_switch_ncols1<576, 512, 4>(ctx, dst); } } break; + case 640: { + // Padded turbo KV cache for GLM-4.7 Flash (K head_dim=576 zero-padded to 640). + // D=640 shared memory (Q storage = ncols*(DKQ/2+4)*4) exceeds hardware limit at ncols1>=4. + // Cap at ncols1=2 (ncols=32): Q=32*324*4=41KB + KV≈37KB = ~78KB total. + GGML_ASSERT(V->ne[0] == 512); + if (Q->ne[1] <= 1) { + ggml_cuda_flash_attn_ext_mma_f16_case<640, 512, 1, 16>(ctx, dst); + } else { + ggml_cuda_flash_attn_ext_mma_f16_case<640, 512, 2, 16>(ctx, dst); + } + } break; default: GGML_ABORT("fatal error"); break; @@ -284,6 +295,39 @@ static void ggml_cuda_flash_attn_ext_vec(ggml_backend_cuda_context & ctx, ggml_t FATTN_VEC_CASES_ALL_D(GGML_TYPE_BF16, GGML_TYPE_BF16) #endif // GGML_CUDA_FA_ALL_QUANTS + // TurboQuant3 KV cache types (always enabled) + FATTN_VEC_CASES_ALL_D(GGML_TYPE_TURBO3_0, GGML_TYPE_TURBO3_0) + + // Mixed turbo3/q8_0 KV cache types + FATTN_VEC_CASES_ALL_D(GGML_TYPE_TURBO3_0, GGML_TYPE_Q8_0) + FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q8_0, GGML_TYPE_TURBO3_0) + + // TurboQuant2 KV cache types (always enabled) + FATTN_VEC_CASES_ALL_D(GGML_TYPE_TURBO2_0, GGML_TYPE_TURBO2_0) + + // Mixed turbo2/q8_0 KV cache types + FATTN_VEC_CASES_ALL_D(GGML_TYPE_TURBO2_0, GGML_TYPE_Q8_0) + FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q8_0, GGML_TYPE_TURBO2_0) + + // Mixed turbo3/turbo2 KV cache types + FATTN_VEC_CASES_ALL_D(GGML_TYPE_TURBO3_0, GGML_TYPE_TURBO2_0) + FATTN_VEC_CASES_ALL_D(GGML_TYPE_TURBO2_0, GGML_TYPE_TURBO3_0) + + // TurboQuant4 KV cache types (always enabled) + FATTN_VEC_CASES_ALL_D(GGML_TYPE_TURBO4_0, GGML_TYPE_TURBO4_0) + + // Mixed turbo4/q8_0 KV cache types + FATTN_VEC_CASES_ALL_D(GGML_TYPE_TURBO4_0, GGML_TYPE_Q8_0) + FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q8_0, GGML_TYPE_TURBO4_0) + + // Mixed turbo4/turbo3 KV cache types + FATTN_VEC_CASES_ALL_D(GGML_TYPE_TURBO4_0, GGML_TYPE_TURBO3_0) + FATTN_VEC_CASES_ALL_D(GGML_TYPE_TURBO3_0, GGML_TYPE_TURBO4_0) + + // Mixed turbo4/turbo2 KV cache types + FATTN_VEC_CASES_ALL_D(GGML_TYPE_TURBO4_0, GGML_TYPE_TURBO2_0) + FATTN_VEC_CASES_ALL_D(GGML_TYPE_TURBO2_0, GGML_TYPE_TURBO4_0) + GGML_ABORT("fatal error"); } @@ -353,6 +397,7 @@ static best_fattn_kernel ggml_cuda_get_best_fattn_kernel(const int device, const } break; case 576: + case 640: if (V->ne[0] != 512) { return BEST_FATTN_KERNEL_NONE; } @@ -366,7 +411,13 @@ static best_fattn_kernel ggml_cuda_get_best_fattn_kernel(const int device, const #ifndef GGML_CUDA_FA_ALL_QUANTS if (K->type != V->type) { - return BEST_FATTN_KERNEL_NONE; + // Allow mixed turbo KV types (any combination of turbo2, turbo3, q8_0) + auto is_turbo = [](ggml_type t) { + return t == GGML_TYPE_TURBO2_0 || t == GGML_TYPE_TURBO3_0 || t == GGML_TYPE_TURBO4_0 || t == GGML_TYPE_Q8_0; + }; + if (!is_turbo(K->type) || !is_turbo(V->type)) { + return BEST_FATTN_KERNEL_NONE; + } } #endif // GGML_CUDA_FA_ALL_QUANTS @@ -384,6 +435,24 @@ static best_fattn_kernel ggml_cuda_get_best_fattn_kernel(const int device, const case GGML_TYPE_Q8_0: case GGML_TYPE_BF16: break; + case GGML_TYPE_TURBO3_0: + // turbo3 VEC kernel instantiated for D in {64, 128, 256}. + if (K->ne[0] % 64 != 0) { + return BEST_FATTN_KERNEL_NONE; + } + break; + case GGML_TYPE_TURBO2_0: + // turbo2 VEC kernel instantiated for D in {64, 128, 256}. + if (K->ne[0] % 64 != 0) { + return BEST_FATTN_KERNEL_NONE; + } + break; + case GGML_TYPE_TURBO4_0: + // turbo4 VEC kernel instantiated for D in {64, 128, 256}. + if (K->ne[0] % 64 != 0) { + return BEST_FATTN_KERNEL_NONE; + } + break; default: return BEST_FATTN_KERNEL_NONE; } @@ -422,7 +491,7 @@ static best_fattn_kernel ggml_cuda_get_best_fattn_kernel(const int device, const if (volta_mma_available(cc) && Q->ne[0] != 40 && Q->ne[0] != 72) { int gqa_ratio_eff = 1; - const int ncols2_max = Q->ne[0] == 576 ? 16 : 8; + const int ncols2_max = (Q->ne[0] == 576 || Q->ne[0] == 640) ? 16 : 8; while (gqa_ratio % (2*gqa_ratio_eff) == 0 && gqa_ratio_eff < ncols2_max) { gqa_ratio_eff *= 2; } @@ -436,7 +505,7 @@ static best_fattn_kernel ggml_cuda_get_best_fattn_kernel(const int device, const } // Use the WMMA kernel if possible: - if (ggml_cuda_should_use_wmma_fattn(cc) && K->ne[1] % FATTN_KQ_STRIDE == 0 && Q->ne[0] != 40 && Q->ne[0] != 72 && Q->ne[0] != 512 && Q->ne[0] != 576) { + if (ggml_cuda_should_use_wmma_fattn(cc) && K->ne[1] % FATTN_KQ_STRIDE == 0 && Q->ne[0] != 40 && Q->ne[0] != 72 && Q->ne[0] != 512 && Q->ne[0] != 576 && Q->ne[0] != 640) { if (can_use_vector_kernel && Q->ne[1] <= 2) { return BEST_FATTN_KERNEL_VEC; } @@ -458,7 +527,7 @@ static best_fattn_kernel ggml_cuda_get_best_fattn_kernel(const int device, const } } int gqa_ratio_eff = 1; - const int ncols2_max = Q->ne[0] == 576 ? 16 : 8; + const int ncols2_max = (Q->ne[0] == 576 || Q->ne[0] == 640) ? 16 : 8; while (gqa_ratio % (2*gqa_ratio_eff) == 0 && gqa_ratio_eff < ncols2_max) { gqa_ratio_eff *= 2; } @@ -469,7 +538,7 @@ static best_fattn_kernel ggml_cuda_get_best_fattn_kernel(const int device, const } // Use MFMA flash attention for CDNA (MI100+): - if (amd_mfma_available(cc) && Q->ne[0] != 40 && Q->ne[0] != 72 && Q->ne[0] != 256 && Q->ne[0] != 512 && Q->ne[0] != 576) { + if (amd_mfma_available(cc) && Q->ne[0] != 40 && Q->ne[0] != 72 && Q->ne[0] != 256 && Q->ne[0] != 512 && Q->ne[0] != 576 && Q->ne[0] != 640) { const int64_t eff_nq = Q->ne[1] * (gqa_opt_applies ? gqa_ratio : 1); // MMA vs tile crossover benchmarked on MI300X @ d32768: // hsk=64 (gqa=4): MMA wins at eff >= 128 (+11%) diff --git a/ggml/src/ggml-cuda/ggml-cuda.cu b/ggml/src/ggml-cuda/ggml-cuda.cu index 75b62129ade..e9f8ce4d59f 100644 --- a/ggml/src/ggml-cuda/ggml-cuda.cu +++ b/ggml/src/ggml-cuda/ggml-cuda.cu @@ -56,6 +56,8 @@ #include "ggml-cuda/gated_delta_net.cuh" #include "ggml-cuda/set.cuh" #include "ggml-cuda/set-rows.cuh" +#include "ggml-cuda/turbo-wht.cuh" +#include "ggml-cuda/mmvq-tq.cuh" #include "ggml-cuda/pad_reflect_1d.cuh" #include "ggml-cuda/solve_tri.cuh" #include "ggml-cuda/tri.cuh" @@ -644,6 +646,33 @@ static void ggml_backend_cuda_buffer_set_tensor(ggml_backend_buffer_t buffer, gg ggml_backend_cuda_buffer_context * ctx = (ggml_backend_cuda_buffer_context *)buffer->context; ggml_cuda_set_device(ctx->device); + + // TQ4_1S → q8_0 load-time conversion + if (tensor->type == GGML_TYPE_TQ4_1S && offset == 0 && size == ggml_nbytes(tensor)) { + const int64_t n_elements = ggml_nelements(tensor); + + // Upload TQ4_1S to a temp GPU buffer + void * tmp_tq4; + CUDA_CHECK(cudaMalloc(&tmp_tq4, size)); + CUDA_CHECK(cudaMemcpyAsync(tmp_tq4, data, size, cudaMemcpyHostToDevice, cudaStreamPerThread)); + + // Convert TQ4_1S (tmp) → q8_0 (tensor->data, which has q8_0-sized allocation) + ggml_cuda_convert_tq4_1s_to_q8_0(tmp_tq4, tensor->data, n_elements, cudaStreamPerThread); + CUDA_CHECK(cudaStreamSynchronize(cudaStreamPerThread)); + + CUDA_CHECK(cudaFree(tmp_tq4)); + + // Update tensor metadata to q8_0 + tensor->type = GGML_TYPE_Q8_0; + tensor->nb[0] = ggml_type_size(GGML_TYPE_Q8_0); + tensor->nb[1] = tensor->nb[0] * (tensor->ne[0] / ggml_blck_size(GGML_TYPE_Q8_0)); + for (int i = 2; i < GGML_MAX_DIMS; i++) { + tensor->nb[i] = tensor->nb[i-1] * tensor->ne[i-1]; + } + + return; + } + CUDA_CHECK(cudaMemcpyAsync((char *)tensor->data + offset, data, size, cudaMemcpyHostToDevice, cudaStreamPerThread)); CUDA_CHECK(cudaStreamSynchronize(cudaStreamPerThread)); } @@ -742,6 +771,13 @@ static size_t ggml_backend_cuda_buffer_type_get_alloc_size(ggml_backend_buffer_t size_t size = ggml_nbytes(tensor); int64_t ne0 = tensor->ne[0]; + // TQ4_1S → q8_0 load-time conversion: allocate q8_0-sized space in VRAM + if (tensor->type == GGML_TYPE_TQ4_1S) { + // q8_0 block: 34 bytes per 32 elements. TQ4_1S block: 20 bytes per 32 elements. + const int64_t n_blocks = ggml_nelements(tensor) / QK_TQ4_1S; + size = n_blocks * sizeof(block_q8_0); + } + if (ggml_is_quantized(tensor->type)) { if (ne0 % MATRIX_ROW_PADDING != 0) { GGML_ASSERT(tensor->nb[0] == ggml_element_size(tensor)); @@ -2211,7 +2247,9 @@ static bool ggml_cuda_should_fuse_mul_mat_vec_q(const ggml_tensor * tensor) { ggml_nbytes(src0) != ggml_backend_buffer_get_alloc_size(src0->buffer, src0) && src0->view_src; - bool use_mul_mat_vec_q = ggml_is_quantized(src0->type) && !bad_padding_clear && src1->type == GGML_TYPE_F32 && + const bool is_tq_weight = (src0->type == GGML_TYPE_TQ4_1S || src0->type == GGML_TYPE_TQ3_1S); + bool use_mul_mat_vec_q = ggml_is_quantized(src0->type) && !bad_padding_clear && !is_tq_weight && + src1->type == GGML_TYPE_F32 && dst->type == GGML_TYPE_F32 && src1->ne[1] <= MMVQ_MAX_BATCH_SIZE; // fusion is not universally faster on Pascal @@ -2253,10 +2291,12 @@ static void ggml_cuda_mul_mat(ggml_backend_cuda_context & ctx, const ggml_tensor && src1->type == GGML_TYPE_F32 && dst->type == GGML_TYPE_F32; bool use_mul_mat_f = !ggml_is_quantized(src0->type) && src1->type == GGML_TYPE_F32 && dst->type == GGML_TYPE_F32; - bool use_mul_mat_vec_q = ggml_is_quantized(src0->type) && !bad_padding_clear + // TQ weight types use dequant-to-f16 cuBLAS path only (no mmvq/mmq kernels) + const bool is_tq_weight = (src0->type == GGML_TYPE_TQ4_1S || src0->type == GGML_TYPE_TQ3_1S); + bool use_mul_mat_vec_q = ggml_is_quantized(src0->type) && !bad_padding_clear && !is_tq_weight && src1->type == GGML_TYPE_F32 && dst->type == GGML_TYPE_F32 && src1->ne[1] <= MMVQ_MAX_BATCH_SIZE; - bool use_mul_mat_q = ggml_is_quantized(src0->type) && !bad_padding_clear + bool use_mul_mat_q = ggml_is_quantized(src0->type) && !bad_padding_clear && !is_tq_weight && src1->type == GGML_TYPE_F32 && dst->type == GGML_TYPE_F32; bool any_gpus_with_slow_fp16 = false; @@ -2320,6 +2360,9 @@ static void ggml_cuda_mul_mat(ggml_backend_cuda_context & ctx, const ggml_tensor ggml_cuda_op_mul_mat(ctx, src0, src1, dst, ggml_cuda_op_mul_mat_vec_q, quantize_row_q8_1_cuda); } else if (use_mul_mat_q) { ggml_cuda_op_mul_mat(ctx, src0, src1, dst, ggml_cuda_op_mul_mat_q, quantize_mmq_q8_1_cuda); + } else if (!split && is_tq_weight && src1->ne[1] == 1) { + // Fused TQ weight mul_mat_vec with pre-rotated activations via warp shuffle WHT + ggml_cuda_mul_mat_vec_tq(ctx, src0, src1, dst); } else { ggml_cuda_op_mul_mat(ctx, src0, src1, dst, ggml_cuda_op_mul_mat_cublas, nullptr); } @@ -2339,16 +2382,18 @@ static void ggml_cuda_mul_mat_id(ggml_backend_cuda_context & ctx, ggml_tensor * const int cc = ggml_cuda_info().devices[ggml_cuda_get_device()].cc; // [TAG_MUL_MAT_ID_CUDA_GRAPHS] + // TQ weight types use dequant-to-f16 cuBLAS path only (no mmvq/mmq kernels) + const bool is_tq_weight_id = (src0->type == GGML_TYPE_TQ4_1S || src0->type == GGML_TYPE_TQ3_1S); if (src1->type == GGML_TYPE_F32 && dst->type == GGML_TYPE_F32) { static_assert(MMVQ_MAX_BATCH_SIZE == MMVF_MAX_BATCH_SIZE); if (ne2 <= MMVQ_MAX_BATCH_SIZE) { - if (ggml_is_quantized(src0->type)) { + if (ggml_is_quantized(src0->type) && !is_tq_weight_id) { const int mmvq_mmid_max = get_mmvq_mmid_max_batch(src0->type, cc); if (ne2 <= mmvq_mmid_max) { ggml_cuda_mul_mat_vec_q(ctx, src0, src1, ids, dst); return; } - } else { + } else if (!ggml_is_quantized(src0->type)) { if (GGML_CUDA_CC_IS_AMD(cc)) { ggml_cuda_mul_mat_vec_f(ctx, src0, src1, ids, dst); return; @@ -2511,6 +2556,9 @@ static bool ggml_cuda_compute_forward(ggml_backend_cuda_context & ctx, struct gg case GGML_OP_SET_ROWS: ggml_cuda_op_set_rows(ctx, dst); break; + case GGML_OP_TURBO_WHT: + ggml_cuda_turbo_wht(ctx, dst); + break; case GGML_OP_SET: ggml_cuda_op_set(ctx, dst); break; @@ -2947,10 +2995,11 @@ static bool ggml_cuda_graph_check_compability(ggml_cgraph * cgraph) { } // [TAG_MUL_MAT_ID_CUDA_GRAPHS] + const bool is_tq_w = (node->src[0]->type == GGML_TYPE_TQ4_1S || node->src[0]->type == GGML_TYPE_TQ3_1S); if (node->op == GGML_OP_MUL_MAT_ID) { const int cc = ggml_cuda_info().devices[ggml_cuda_get_device()].cc; const int mmvq_mmid_max = get_mmvq_mmid_max_batch(node->src[0]->type, cc); - if (!ggml_is_quantized(node->src[0]->type) || node->ne[2] > mmvq_mmid_max) { + if (!ggml_is_quantized(node->src[0]->type) || is_tq_w || node->ne[2] > mmvq_mmid_max) { // under these conditions, the mul_mat_id operation will need to synchronize the stream, so we cannot use CUDA graphs // TODO: figure out a way to enable for larger batch sizes, without hurting performance // ref: https://github.com/ggml-org/llama.cpp/pull/18958 @@ -4808,6 +4857,8 @@ static bool ggml_backend_cuda_device_supports_op(ggml_backend_dev_t dev, const g case GGML_TYPE_IQ4_NL: case GGML_TYPE_IQ4_XS: case GGML_TYPE_BF16: + case GGML_TYPE_TQ4_1S: + case GGML_TYPE_TQ3_1S: return true; default: return false; @@ -4827,6 +4878,8 @@ static bool ggml_backend_cuda_device_supports_op(ggml_backend_dev_t dev, const g case GGML_TYPE_Q5_0: case GGML_TYPE_Q5_1: case GGML_TYPE_Q8_0: + case GGML_TYPE_TQ4_1S: + case GGML_TYPE_TQ3_1S: return true; default: return false; @@ -4838,9 +4891,18 @@ static bool ggml_backend_cuda_device_supports_op(ggml_backend_dev_t dev, const g } break; case GGML_OP_SET_ROWS: { + // turbo types require head_dim divisible by appropriate group size + if ((op->type == GGML_TYPE_TURBO3_0 || op->type == GGML_TYPE_TURBO2_0) && op->src[0]->ne[0] % 64 != 0) { + return false; + } + // turbo4 block size is 128, so head_dim must be divisible by 128 + if (op->type == GGML_TYPE_TURBO4_0 && op->src[0]->ne[0] % 128 != 0) { + return false; + } return (op->type == GGML_TYPE_F32 || op->type == GGML_TYPE_F16 || op->type == GGML_TYPE_BF16 || op->type == GGML_TYPE_Q4_0 || op->type == GGML_TYPE_Q4_1 || op->type == GGML_TYPE_Q5_0 || - op->type == GGML_TYPE_Q5_1 || op->type == GGML_TYPE_Q8_0 || op->type == GGML_TYPE_IQ4_NL) && + op->type == GGML_TYPE_Q5_1 || op->type == GGML_TYPE_Q8_0 || op->type == GGML_TYPE_IQ4_NL || + op->type == GGML_TYPE_TURBO3_0 || op->type == GGML_TYPE_TURBO2_0 || op->type == GGML_TYPE_TURBO4_0) && op->src[0]->type == GGML_TYPE_F32 && (op->src[1]->type == GGML_TYPE_I64 || op->src[1]->type == GGML_TYPE_I32); } break; @@ -4967,6 +5029,9 @@ static bool ggml_backend_cuda_device_supports_op(ggml_backend_dev_t dev, const g case GGML_OP_CLAMP: case GGML_OP_LOG: return true; + case GGML_OP_TURBO_WHT: + return op->src[0]->type == GGML_TYPE_F32 && op->type == GGML_TYPE_F32 && + op->src[0]->ne[0] % 32 == 0; // supports 32, 64, and 128 WHT groups case GGML_OP_SSM_SCAN: { if (op->src[3]->ne[0] == 1) { // Mamba2 diff --git a/ggml/src/ggml-cuda/mmvq-tq.cu b/ggml/src/ggml-cuda/mmvq-tq.cu new file mode 100644 index 00000000000..d7ed7561873 --- /dev/null +++ b/ggml/src/ggml-cuda/mmvq-tq.cu @@ -0,0 +1,371 @@ +/* + * Fused mul_mat_vec for TQ4_1S / TQ3_1S weight types. + * + * V12: Single-phase fused kernel with shmem activation sharing. + * All warps cooperatively rotate activation into shared memory, + * then each warp processes one row reading from shmem (broadcast). + * + * Eliminates: + * - Global memory scratch buffer (no CUDA graph incompatibility) + * - Separate pre-rotation kernel launch + * - 2x activation bandwidth (was: write global + read global per row) + * + * V12 avoids the NR0 regression that killed V3/V6/V11 — the single + * __syncthreads is OUTSIDE the dot product loop (between rotation and + * mmvq phases), not inside it. + * + * Falls back to V8 two-phase if shmem exceeds 48 KB (ncols > 12288). + * + * Based on signalnine's V8 two-phase kernel (commit b107175). + * Optimization by TheTom. + */ + +#include "mmvq-tq.cuh" +#include "turbo-quant.cuh" + +#define MMVQ_TQ_NWARPS 8 + +// ============================================================================ +// V8 two-phase kernels (fallback for very large ncols that exceed shmem) +// ============================================================================ + +static __global__ void tq_prerotate_activation_v8( + const float * __restrict__ src, + float * __restrict__ dst, + const int n_elements) { + + const int block_idx = blockIdx.x * blockDim.y + threadIdx.y; + const int lane = threadIdx.x; + const int offset = block_idx * 32 + lane; + if (offset >= n_elements) return; + + float val = src[offset]; + val *= TQ_WEIGHT_SIGNS[lane]; + + #pragma unroll + for (int h = 1; h < 32; h <<= 1) { + float o = __shfl_xor_sync(0xffffffff, val, h); + val = (lane & h) ? (o - val) : (val + o); + } + val *= 0.17677669529663688f; + dst[offset] = val; +} + +static __global__ void mul_mat_vec_tq4_1s_v8( + const void * __restrict__ vx, + const float * __restrict__ vy_rot, + float * __restrict__ dst, + const int ncols_x, + const int nrows_x) { + + const int row = blockIdx.x * MMVQ_TQ_NWARPS + threadIdx.y; + if (row >= nrows_x) return; + + const int lane = threadIdx.x; + const int blocks_per_row = ncols_x / QK_TQ4_1S; + const block_tq4_1s * x_row = ((const block_tq4_1s *) vx) + (int64_t)row * blocks_per_row; + + float sum = 0.0f; + + for (int ib = 0; ib < blocks_per_row; ib++) { + const float act = vy_rot[ib * QK_TQ4_1S + lane]; + const float d = (lane < 16) ? __half2float(x_row[ib].d0) : __half2float(x_row[ib].d1); + const uint8_t idx = (x_row[ib].qs[lane / 2] >> ((lane & 1) * 4)) & 0xF; + + sum += act * TQ4_CENTROIDS_WEIGHT[idx] * d; + } + + #pragma unroll + for (int offset = 16; offset > 0; offset >>= 1) + sum += __shfl_xor_sync(0xffffffff, sum, offset); + + if (lane == 0) dst[row] = sum; +} + +static __device__ __forceinline__ uint8_t tq3_extract_index(const uint8_t * __restrict__ qs, int lane) { + const int group = lane / 8; + const int lane_in_group = lane % 8; + const uint8_t * qp = qs + group * 3; + const uint32_t packed = (uint32_t)qp[0] | ((uint32_t)qp[1] << 8) | ((uint32_t)qp[2] << 16); + return (packed >> (lane_in_group * 3)) & 7; +} + +static __global__ void mul_mat_vec_tq3_1s_v8( + const void * __restrict__ vx, + const float * __restrict__ vy_rot, + float * __restrict__ dst, + const int ncols_x, + const int nrows_x) { + + const int row = blockIdx.x * MMVQ_TQ_NWARPS + threadIdx.y; + if (row >= nrows_x) return; + + const int lane = threadIdx.x; + const int blocks_per_row = ncols_x / QK_TQ3_0; + const block_tq3_1s * x_row = ((const block_tq3_1s *) vx) + (int64_t)row * blocks_per_row; + + float sum = 0.0f; + + for (int ib = 0; ib < blocks_per_row; ib++) { + const float act = vy_rot[ib * QK_TQ3_0 + lane]; + const float d = (lane < 16) ? __half2float(x_row[ib].d0) : __half2float(x_row[ib].d1); + const uint8_t idx = tq3_extract_index(x_row[ib].qs, lane); + + sum += act * TQ3_CENTROIDS_WEIGHT[idx] * d; + } + + #pragma unroll + for (int offset = 16; offset > 0; offset >>= 1) + sum += __shfl_xor_sync(0xffffffff, sum, offset); + + if (lane == 0) dst[row] = sum; +} + +// ============================================================================ +// V12: Single-phase fused kernel — rotate in shmem, no global scratch +// +// All 8 warps cooperatively WHT-rotate activation into shared memory. +// Then each warp processes one row doing centroid×scale dot product +// reading activation from shmem (broadcast reads from L1). +// +// The key insight: the single __syncthreads is between the two phases +// (rotation vs dot product), NOT inside the inner dot product loop. +// This is why V3/V11 regressed (sync per block) but V12 should not. +// ============================================================================ + +static __global__ void mul_mat_vec_tq4_1s_v12( + const void * __restrict__ vx, + const float * __restrict__ vy, // UNROTATED activation (raw src1) + float * __restrict__ dst, + const int ncols_x, + const int nrows_x) { + + extern __shared__ float s_act[]; // ncols_x floats + + const int lane = threadIdx.x; // 0-31 + const int warp_id = threadIdx.y; // 0 to MMVQ_TQ_NWARPS-1 + const int blocks_per_row = ncols_x / QK_TQ4_1S; + + // Phase 1: ALL warps cooperatively pre-rotate activation into shmem. + // Each warp handles a strided subset of 32-element blocks. + // 8 warps × 32 threads = 256 threads rotating in parallel. + for (int ib = warp_id; ib < blocks_per_row; ib += MMVQ_TQ_NWARPS) { + float val = vy[ib * 32 + lane]; + val *= TQ_WEIGHT_SIGNS[lane]; + + #pragma unroll + for (int h = 1; h < 32; h <<= 1) { + float o = __shfl_xor_sync(0xffffffff, val, h); + val = (lane & h) ? (o - val) : (val + o); + } + val *= 0.17677669529663688f; // 1/sqrt(32) + s_act[ib * 32 + lane] = val; + } + __syncthreads(); // ONE sync — between rotation and dot product, NOT in inner loop + + // Phase 2: Each warp processes one row using shmem activation (broadcast reads). + const int row = blockIdx.x * MMVQ_TQ_NWARPS + warp_id; + if (row >= nrows_x) return; + + const block_tq4_1s * x_row = ((const block_tq4_1s *) vx) + (int64_t)row * blocks_per_row; + float sum = 0.0f; + + for (int ib = 0; ib < blocks_per_row; ib++) { + const float act = s_act[ib * 32 + lane]; + const float d = (lane < 16) ? __half2float(x_row[ib].d0) : __half2float(x_row[ib].d1); + const uint8_t idx = (x_row[ib].qs[lane / 2] >> ((lane & 1) * 4)) & 0xF; + sum += act * TQ4_CENTROIDS_WEIGHT[idx] * d; + } + + #pragma unroll + for (int offset = 16; offset > 0; offset >>= 1) + sum += __shfl_xor_sync(0xffffffff, sum, offset); + + if (lane == 0) dst[row] = sum; +} + +static __global__ void mul_mat_vec_tq3_1s_v12( + const void * __restrict__ vx, + const float * __restrict__ vy, // UNROTATED activation (raw src1) + float * __restrict__ dst, + const int ncols_x, + const int nrows_x) { + + extern __shared__ float s_act[]; + + const int lane = threadIdx.x; + const int warp_id = threadIdx.y; + const int blocks_per_row = ncols_x / QK_TQ3_0; + + // Phase 1: cooperative rotation into shmem + for (int ib = warp_id; ib < blocks_per_row; ib += MMVQ_TQ_NWARPS) { + float val = vy[ib * 32 + lane]; + val *= TQ_WEIGHT_SIGNS[lane]; + + #pragma unroll + for (int h = 1; h < 32; h <<= 1) { + float o = __shfl_xor_sync(0xffffffff, val, h); + val = (lane & h) ? (o - val) : (val + o); + } + val *= 0.17677669529663688f; + s_act[ib * 32 + lane] = val; + } + __syncthreads(); + + // Phase 2: mmvq from shmem + const int row = blockIdx.x * MMVQ_TQ_NWARPS + warp_id; + if (row >= nrows_x) return; + + const block_tq3_1s * x_row = ((const block_tq3_1s *) vx) + (int64_t)row * blocks_per_row; + float sum = 0.0f; + + for (int ib = 0; ib < blocks_per_row; ib++) { + const float act = s_act[ib * 32 + lane]; + const float d = (lane < 16) ? __half2float(x_row[ib].d0) : __half2float(x_row[ib].d1); + const uint8_t idx = tq3_extract_index(x_row[ib].qs, lane); + sum += act * TQ3_CENTROIDS_WEIGHT[idx] * d; + } + + #pragma unroll + for (int offset = 16; offset > 0; offset >>= 1) + sum += __shfl_xor_sync(0xffffffff, sum, offset); + + if (lane == 0) dst[row] = sum; +} + +// ============================================================================ +// Dispatch — V12 shmem when it fits, V8 two-phase fallback +// ============================================================================ + +void ggml_cuda_mul_mat_vec_tq(ggml_backend_cuda_context & ctx, + const ggml_tensor * src0, + const ggml_tensor * src1, + ggml_tensor * dst) { + GGML_ASSERT(src0->type == GGML_TYPE_TQ4_1S || src0->type == GGML_TYPE_TQ3_1S); + GGML_ASSERT(src1->type == GGML_TYPE_F32); + GGML_ASSERT(dst->type == GGML_TYPE_F32); + GGML_ASSERT(src1->ne[1] == 1); + + const int ncols_x = src0->ne[0]; + const int nrows_x = src0->ne[1]; + GGML_ASSERT(ncols_x % 32 == 0); + + const void * src0_d = src0->data; + const float * src1_d = (const float *) src1->data; + float * dst_d = (float *) dst->data; + cudaStream_t stream = ctx.stream(); + + const size_t shmem_needed = (size_t)ncols_x * sizeof(float); + + // V12: single kernel, activation in shmem (fits for all models up to ncols=12288) + // V8 fallback: two-phase with global scratch (for hypothetical future huge models) + if (shmem_needed <= 48 * 1024) { + const dim3 block(WARP_SIZE, MMVQ_TQ_NWARPS); + const dim3 grid((nrows_x + MMVQ_TQ_NWARPS - 1) / MMVQ_TQ_NWARPS); + + if (src0->type == GGML_TYPE_TQ4_1S) { + mul_mat_vec_tq4_1s_v12<<>>(src0_d, src1_d, dst_d, ncols_x, nrows_x); + } else { + mul_mat_vec_tq3_1s_v12<<>>(src0_d, src1_d, dst_d, ncols_x, nrows_x); + } + } else { + // V8 fallback: two-phase with global scratch buffer + static float * d_act_buf = nullptr; + static size_t d_act_buf_size = 0; + + cudaStreamCaptureStatus capture_status; + cudaStreamIsCapturing(stream, &capture_status); + + if (capture_status != cudaStreamCaptureStatusNone) { + GGML_ASSERT(d_act_buf != nullptr && d_act_buf_size >= shmem_needed && + "TQ scratch buffer not pre-allocated before graph capture"); + } else { + if (shmem_needed > d_act_buf_size) { + if (d_act_buf) cudaFree(d_act_buf); + cudaMalloc(&d_act_buf, shmem_needed); + d_act_buf_size = shmem_needed; + } + } + + { + const int n_blocks = ncols_x / 32; + const dim3 rot_block(32, 4); + const dim3 rot_grid((n_blocks + 3) / 4); + tq_prerotate_activation_v8<<>>(src1_d, d_act_buf, ncols_x); + } + + { + const dim3 block(WARP_SIZE, MMVQ_TQ_NWARPS); + const dim3 grid((nrows_x + MMVQ_TQ_NWARPS - 1) / MMVQ_TQ_NWARPS); + + if (src0->type == GGML_TYPE_TQ4_1S) { + mul_mat_vec_tq4_1s_v8<<>>(src0_d, d_act_buf, dst_d, ncols_x, nrows_x); + } else { + mul_mat_vec_tq3_1s_v8<<>>(src0_d, d_act_buf, dst_d, ncols_x, nrows_x); + } + } + } +} + +// ============================================================================ +// Load-time conversion: TQ4_1S → q8_0 +// +// Fused kernel: dequant TQ4_1S (centroid lookup + inverse WHT) → quantize q8_0. +// One warp (32 threads) per block of 32 elements. +// Used at model load to convert TQ4_1S weights to q8_0 in VRAM for dp4a decode. +// ============================================================================ + +static __global__ void k_convert_tq4_1s_to_q8_0( + const block_tq4_1s * __restrict__ src, + block_q8_0 * __restrict__ dst, + const int n_blocks) { + + const int block_idx = blockIdx.x * blockDim.y + threadIdx.y; + if (block_idx >= n_blocks) return; + + const int lane = threadIdx.x; + const block_tq4_1s * blk = &src[block_idx]; + + // Step 1: Dequant — centroid lookup × half-block scale + const float d_scale = (lane < 16) ? __half2float(blk->d0) : __half2float(blk->d1); + const uint8_t idx = (blk->qs[lane / 2] >> ((lane & 1) * 4)) & 0xF; + float val = TQ4_CENTROIDS_WEIGHT[idx] * d_scale; + + // Step 2: Inverse WHT via warp shuffle (same as dequant path) + #pragma unroll + for (int h = 1; h < 32; h <<= 1) { + float o = __shfl_xor_sync(0xffffffff, val, h); + val = (lane & h) ? (o - val) : (val + o); + } + val *= 0.17677669529663688f; // 1/sqrt(32) + val *= TQ_WEIGHT_SIGNS[lane]; + + // Step 3: Quantize to q8_0 — find block amax, compute scale, round + float amax = fabsf(val); + #pragma unroll + for (int off = 16; off > 0; off >>= 1) + amax = fmaxf(amax, __shfl_xor_sync(0xffffffff, amax, off)); + + const float d = amax / 127.0f; + const float id = (d > 0.0f) ? 127.0f / amax : 0.0f; + + // Step 4: Write q8_0 block + dst[block_idx].qs[lane] = (int8_t)roundf(val * id); + if (lane == 0) { + dst[block_idx].d = __float2half(d); + } +} + +void ggml_cuda_convert_tq4_1s_to_q8_0(const void * src_tq4, void * dst_q8, int64_t n_elements, cudaStream_t stream) { + GGML_ASSERT(n_elements % QK_TQ4_1S == 0); + const int n_blocks = n_elements / QK_TQ4_1S; + + const int wpb = 4; // warps per CUDA block + const dim3 block(32, wpb); + const dim3 grid((n_blocks + wpb - 1) / wpb); + + k_convert_tq4_1s_to_q8_0<<>>( + (const block_tq4_1s *)src_tq4, + (block_q8_0 *)dst_q8, + n_blocks); +} diff --git a/ggml/src/ggml-cuda/mmvq-tq.cuh b/ggml/src/ggml-cuda/mmvq-tq.cuh new file mode 100644 index 00000000000..3315a062c3e --- /dev/null +++ b/ggml/src/ggml-cuda/mmvq-tq.cuh @@ -0,0 +1,8 @@ +#pragma once + +#include "common.cuh" + +void ggml_cuda_mul_mat_vec_tq(ggml_backend_cuda_context & ctx, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst); + +// Load-time conversion: TQ4_1S → q8_0 in VRAM (dequant + requantize) +void ggml_cuda_convert_tq4_1s_to_q8_0(const void * src_tq4, void * dst_q8, int64_t n_elements, cudaStream_t stream); diff --git a/ggml/src/ggml-cuda/set-rows.cu b/ggml/src/ggml-cuda/set-rows.cu index 631de7e8fa5..2f43961665f 100644 --- a/ggml/src/ggml-cuda/set-rows.cu +++ b/ggml/src/ggml-cuda/set-rows.cu @@ -1,5 +1,6 @@ #include "set-rows.cuh" #include "cpy-utils.cuh" +#include "turbo-quant.cuh" typedef void (*set_rows_kernel_t)(const char * src, char * dst); @@ -209,6 +210,928 @@ static void set_rows_cuda( } } +// ---- TurboQuant3 set_rows: GROUP_SIZE-element groups with WHT rotation + norm correction ---- +// +// Templated on GROUP_SIZE (128 or 64). +// Parallel kernel: one CUDA block per group, GROUP_SIZE threads per block. +// Thread j handles element j within the group. +// +// Steps (all parallel): +// 1. Load element j from global memory +// 2. Parallel L2 norm (warp reduce + inter-warp via shared memory) +// 3. Normalize +// 4. Forward WHT (log2(GROUP_SIZE) butterfly stages, shared memory) +// 5. Quantize element j to 3-bit centroid index +// 6. Pack qs (warp shuffle) and signs (__ballot_sync) into turbo3 block, no atomics +// 7. Parallel reconstruction norm (same pattern as step 2) +// 8. Write corrected norm (one thread per sub-block) + +template +__launch_bounds__(128) // max of 128 or 64 +static __global__ void k_set_rows_turbo3( + const float * __restrict__ src0, + const idx_t * __restrict__ src1, + block_turbo3_0 * __restrict__ dst, + const int64_t ne00, + const int64_t ne01, + const int64_t ne10, + const int64_t ne11, + const int64_t ne12, + const int64_t ne13, + const int64_t s01, + const int64_t s02, + const int64_t s03, + const int64_t s10, + const int64_t s11, + const int64_t s12, + const int64_t s1, + const int64_t s2, + const int64_t s3) { + + static_assert(GROUP_SIZE == 128 || GROUP_SIZE == 64, "GROUP_SIZE must be 128 or 64"); + + // blockIdx.x = flat group index; threadIdx.x = element within group (0..GROUP_SIZE-1) + const int j = threadIdx.x; + + // Decode blockIdx.x → (i_grp, i01, i02, i03) + constexpr int blocks_per_group = GROUP_SIZE / QK_TURBO3; + const int64_t n_groups_per_row = ne00 / GROUP_SIZE; + const int64_t g = blockIdx.x; + const int64_t i_grp = g % n_groups_per_row; + int64_t tmp = g / n_groups_per_row; + const int64_t i01 = tmp % ne01; + tmp = tmp / ne01; + const int64_t i02 = tmp % ne12; + const int64_t i03 = tmp / ne12; + + const int64_t i12 = i02; + const int64_t i11 = i01 % ne11; + const int64_t i10 = i01; + + const int64_t dst_row = *(src1 + i10*s10 + i11*s11 + i12*s12); + const float * src_row = src0 + i01*s01 + i02*s02 + i03*s03; + block_turbo3_0 * dst_row_ptr = (block_turbo3_0 *)((char *)dst + dst_row*s1 + i02*s2 + i03*s3); + block_turbo3_0 * blk_base = dst_row_ptr + i_grp * blocks_per_group; + + // ---- Step 1: Load element j (coalesced) ---- + __shared__ float x[GROUP_SIZE]; + x[j] = src_row[i_grp * GROUP_SIZE + j]; + __syncthreads(); + + // ---- InnerQ: calibrate on original (unscaled) values ---- + if (d_innerq_calibrating) { + atomicAdd(&d_innerq_sq_accum[j], x[j] * x[j]); + if (j == 0) atomicAdd(&d_innerq_count, 1); + } + + // ---- InnerQ: apply channel scale (only when active) ---- + if (d_innerq_active) { + x[j] *= d_innerq_scale[j]; + } + __syncthreads(); + + // ---- Step 2: Parallel L2 norm ---- + constexpr int n_warps = GROUP_SIZE / WARP_SIZE; + __shared__ float warp_accum[n_warps]; + float v = x[j]; + float v2 = v * v; + for (int offset = WARP_SIZE / 2; offset > 0; offset >>= 1) + v2 += __shfl_xor_sync(0xffffffff, v2, offset); + if (j % WARP_SIZE == 0) + warp_accum[j / WARP_SIZE] = v2; + __syncthreads(); + + __shared__ float s_norm_sq; + if (j == 0) { + float total = 0.0f; + for (int w = 0; w < n_warps; w++) total += warp_accum[w]; + s_norm_sq = total; + } + __syncthreads(); + const float grp_norm = sqrtf(s_norm_sq); + const float inv_norm = (grp_norm > 1e-10f) ? 1.0f / grp_norm : 0.0f; + + // ---- Step 3: Normalize ---- + x[j] *= inv_norm; + __syncthreads(); + + // ---- Step 4: Forward WHT (signs1 → butterfly → signs2, normalized) ---- + if (GROUP_SIZE == 128) { + x[j] *= TURBO_WHT_SIGNS1[j]; + } else { + x[j] *= TURBO_WHT_SIGNS1_64[j]; + } + __syncthreads(); + +#define WHT_STAGE_SHARED(h) \ + if (j % (2*(h)) < (h)) { float a = x[j], b = x[j+(h)]; x[j] = a+b; x[j+(h)] = a-b; } \ + __syncthreads(); + + // Butterfly stages: loop from h=1 to h WARP_SIZE, multiple warps + // share one block and write to different byte offsets within it. + const int warp_id = j / WARP_SIZE; + const int lane = j % WARP_SIZE; + const int elem_in_block = j % QK_TURBO3; + block_turbo3_0 * blk = blk_base + (j / QK_TURBO3); + + // Pack qs: 4 elements per byte, 2 bits each. + // All 4 threads in a qs-group gather their low2 bits via shuffle. + const int qs_byte_idx = elem_in_block / 4; + const uint8_t my_low2 = idx & 0x3; + uint8_t qs_byte = 0; +#pragma unroll + for (int k = 0; k < 4; k++) { + uint8_t contrib = __shfl_sync(0xffffffff, my_low2, (lane & ~3) + k); + qs_byte |= contrib << (k * 2); + } + if (lane % 4 == 0) blk->qs[qs_byte_idx] = qs_byte; + + // Pack signs: 8 elements per byte, 1 bit each. __ballot_sync across warp. + // Ballot is per-warp (32 bits); extract local byte, write to global position in block. + const uint32_t ballot = __ballot_sync(0xffffffff, (idx >> 2) & 1); + const int local_signs_byte = lane / 8; // byte within 32-bit ballot (0..3) + const int global_signs_byte = elem_in_block / 8; // byte within block's signs array + const uint8_t signs_byte = (uint8_t)((ballot >> (local_signs_byte * 8)) & 0xFF); + if (lane % 8 == 0) blk->signs[global_signs_byte] = signs_byte; + + // ---- Step 7: Reconstruction norm (parallel, same pattern as step 2) ---- + const float c = TURBO_CENTROIDS_3BIT[idx]; + float rc = c * c; + for (int offset = WARP_SIZE / 2; offset > 0; offset >>= 1) + rc += __shfl_xor_sync(0xffffffff, rc, offset); + if (j % WARP_SIZE == 0) + warp_accum[j / WARP_SIZE] = rc; + __syncthreads(); + + __shared__ float s_recon_sq; + if (j == 0) { + float total = 0.0f; + for (int w = 0; w < n_warps; w++) total += warp_accum[w]; + s_recon_sq = total; + } + __syncthreads(); + const float recon_norm = sqrtf(s_recon_sq); + const float corrected_norm = (recon_norm > 1e-10f) ? grp_norm / recon_norm : grp_norm; + + // ---- Step 8: Write corrected norm (one per turbo3 block) ---- + if (elem_in_block == 0) blk->norm = __float2half(corrected_norm); + + GGML_UNUSED(ne10); + GGML_UNUSED(ne13); +} + +// ---- TurboQuant3 tail kernel: straight 3-bit quantize without WHT rotation ---- +// +// For head dims not divisible by 128 (e.g. 576 = 4*128 + 64), the remainder +// elements can't use the 128-element WHT. They are quantised directly into +// standard turbo3 blocks. Q is also NOT rotated for these positions (the graph +// guards on ne[0] % 128), so stays in the original space. +// +// One CUDA block per row, with tail_size threads (must be multiple of 32). + +template +static __global__ void k_set_rows_turbo3_tail( + const float * __restrict__ src0, + const idx_t * __restrict__ src1, + block_turbo3_0 * __restrict__ dst, + const int64_t ne00, + const int64_t ne01, + const int64_t ne10, + const int64_t ne11, + const int64_t ne12, + const int64_t ne13, + const int64_t s01, + const int64_t s02, + const int64_t s03, + const int64_t s10, + const int64_t s11, + const int64_t s12, + const int64_t s1, + const int64_t s2, + const int64_t s3, + const int tail_size) { + + const int j = threadIdx.x; // 0 .. tail_size-1 + + // Decode blockIdx.x → (i01, i02, i03) + int64_t tmp = blockIdx.x; + const int64_t i01 = tmp % ne01; tmp /= ne01; + const int64_t i02 = tmp % ne12; + const int64_t i03 = tmp / ne12; + + const int64_t i11 = i01 % ne11; + const int64_t i10 = i01; + const int64_t i12 = i02; + + const int64_t dst_row = *(src1 + i10*s10 + i11*s11 + i12*s12); + const float * src_row = src0 + i01*s01 + i02*s02 + i03*s03; + block_turbo3_0 * dst_row_ptr = (block_turbo3_0 *)((char *)dst + dst_row*s1 + i02*s2 + i03*s3); + + // Tail starts after all full 128-element groups + const int64_t n_full = ne00 / QK_TURBO3_GROUP; + const int64_t tail_start = n_full * QK_TURBO3_GROUP; + block_turbo3_0 * blk_base = dst_row_ptr + n_full * (QK_TURBO3_GROUP / QK_TURBO3); + + // ---- Load ---- + const float val = src_row[tail_start + j]; + + // ---- L2 norm over the tail group (warp reduce + inter-warp) ---- + const int n_warps = tail_size / WARP_SIZE; + const int warp_id = j / WARP_SIZE; + const int lane = j % WARP_SIZE; + + __shared__ float warp_accum[4]; // max 3 warps (tail ≤ 96) + float v2 = val * val; + for (int offset = WARP_SIZE / 2; offset > 0; offset >>= 1) + v2 += __shfl_xor_sync(0xffffffff, v2, offset); + if (lane == 0) warp_accum[warp_id] = v2; + __syncthreads(); + + __shared__ float s_norm_sq; + if (j == 0) { + float total = 0.0f; + for (int w = 0; w < n_warps; w++) total += warp_accum[w]; + s_norm_sq = total; + } + __syncthreads(); + const float grp_norm = sqrtf(s_norm_sq); + const float inv_norm = (grp_norm > 1e-10f) ? 1.0f / grp_norm : 0.0f; + + // ---- Normalize (no WHT!) ---- + const float rv = val * inv_norm; + + // ---- Quantize ---- + const uint8_t idx = turbo_nearest_centroid_3bit(rv); + + // ---- Pack qs and signs (same warp-cooperative logic) ---- + block_turbo3_0 * blk = blk_base + warp_id; + + const uint8_t my_low2 = idx & 0x3; + uint8_t qs_byte = 0; +#pragma unroll + for (int k = 0; k < 4; k++) { + uint8_t contrib = __shfl_sync(0xffffffff, my_low2, (lane & ~3) + k); + qs_byte |= contrib << (k * 2); + } + if (lane % 4 == 0) blk->qs[lane / 4] = qs_byte; + + const uint32_t ballot = __ballot_sync(0xffffffff, (idx >> 2) & 1); + const int signs_byte_idx = lane / 8; + const uint8_t signs_byte = (uint8_t)((ballot >> (signs_byte_idx * 8)) & 0xFF); + if (lane % 8 == 0) blk->signs[signs_byte_idx] = signs_byte; + + // ---- Reconstruction norm ---- + const float c = TURBO_CENTROIDS_3BIT[idx]; + float rc = c * c; + for (int offset = WARP_SIZE / 2; offset > 0; offset >>= 1) + rc += __shfl_xor_sync(0xffffffff, rc, offset); + if (lane == 0) warp_accum[warp_id] = rc; + __syncthreads(); + + __shared__ float s_recon_sq; + if (j == 0) { + float total = 0.0f; + for (int w = 0; w < n_warps; w++) total += warp_accum[w]; + s_recon_sq = total; + } + __syncthreads(); + const float recon_norm = sqrtf(s_recon_sq); + const float corrected_norm = (recon_norm > 1e-10f) ? grp_norm / recon_norm : grp_norm; + + if (lane == 0) blk->norm = __float2half(corrected_norm); + + GGML_UNUSED(ne10); + GGML_UNUSED(ne13); +} + +template +static void set_rows_cuda_turbo3( + ggml_backend_cuda_context & ctx, + const ggml_tensor * src0, + const ggml_tensor * src1, + ggml_tensor * dst) { + + const float * src0_d = (const float *)src0->data; + const idx_t * src1_d = (const idx_t *)src1->data; + + GGML_TENSOR_BINARY_OP_LOCALS + GGML_ASSERT(ne00 % QK_TURBO3 == 0); // must be block-aligned (32) + + cudaStream_t stream = ctx.stream(); + + // Read WHT group size from op_params (set by llama-kv-cache.cpp based on head_dim). + // Default to 128 if not set (backward compat with head_dim=128 models). + int group_size = 128; + memcpy(&group_size, dst->op_params, sizeof(int)); + if (group_size != 64 && group_size != 128) group_size = 128; + GGML_ASSERT(ne00 % group_size == 0); + + const int64_t n_full_groups = ne00 / group_size; + const int tail_size = (int)(ne00 % group_size); + + const int64_t s01 = nb01/sizeof(float); + const int64_t s02 = nb02/sizeof(float); + const int64_t s03 = nb03/sizeof(float); + const int64_t s10 = nb10/sizeof(idx_t); + const int64_t s11 = nb11/sizeof(idx_t); + const int64_t s12 = nb12/sizeof(idx_t); + + // InnerQ: check/finalize calibration before kernel launch + turbo_innerq_check_finalize(group_size, ne00); + + // Launch 1: full groups with WHT rotation + if (n_full_groups > 0) { + const int64_t ne_total = n_full_groups * ne01 * ne02 * ne03; + if (group_size == 128) { + k_set_rows_turbo3<<<(int)ne_total, 128, 0, stream>>>( + src0_d, src1_d, (block_turbo3_0 *)dst->data, + ne00, ne01, ne10, ne11, ne12, ne13, + s01, s02, s03, s10, s11, s12, + nb1, nb2, nb3); + } else { + k_set_rows_turbo3<<<(int)ne_total, 64, 0, stream>>>( + src0_d, src1_d, (block_turbo3_0 *)dst->data, + ne00, ne01, ne10, ne11, ne12, ne13, + s01, s02, s03, s10, s11, s12, + nb1, nb2, nb3); + } + } + + // Launch 2: tail elements (no WHT, straight quantize) + // Not needed for 64-aligned dims but kept for potential future use + if (tail_size > 0) { + GGML_ASSERT(tail_size % QK_TURBO3 == 0); // tail must be block-aligned + const int64_t n_rows = ne01 * ne02 * ne03; + k_set_rows_turbo3_tail<<<(int)n_rows, tail_size, 0, stream>>>( + src0_d, src1_d, (block_turbo3_0 *)dst->data, + ne00, ne01, ne10, ne11, ne12, ne13, + s01, s02, s03, s10, s11, s12, + nb1, nb2, nb3, tail_size); + } +} + +// ---- TurboQuant2 set_rows: GROUP_SIZE-element groups with WHT rotation + norm correction ---- +// +// Same structure as turbo3 but 2-bit quantization only (no signs byte). + +template +__launch_bounds__(128) +static __global__ void k_set_rows_turbo2( + const float * __restrict__ src0, + const idx_t * __restrict__ src1, + block_turbo2_0 * __restrict__ dst, + const int64_t ne00, + const int64_t ne01, + const int64_t ne10, + const int64_t ne11, + const int64_t ne12, + const int64_t ne13, + const int64_t s01, + const int64_t s02, + const int64_t s03, + const int64_t s10, + const int64_t s11, + const int64_t s12, + const int64_t s1, + const int64_t s2, + const int64_t s3) { + + static_assert(GROUP_SIZE == 128 || GROUP_SIZE == 64, "GROUP_SIZE must be 128 or 64"); + + const int j = threadIdx.x; + + constexpr int blocks_per_group = GROUP_SIZE / QK_TURBO2; + const int64_t n_groups_per_row = ne00 / GROUP_SIZE; + const int64_t g = blockIdx.x; + const int64_t i_grp = g % n_groups_per_row; + int64_t tmp = g / n_groups_per_row; + const int64_t i01 = tmp % ne01; + tmp = tmp / ne01; + const int64_t i02 = tmp % ne12; + const int64_t i03 = tmp / ne12; + + const int64_t i12 = i02; + const int64_t i11 = i01 % ne11; + const int64_t i10 = i01; + + const int64_t dst_row = *(src1 + i10*s10 + i11*s11 + i12*s12); + const float * src_row = src0 + i01*s01 + i02*s02 + i03*s03; + block_turbo2_0 * dst_row_ptr = (block_turbo2_0 *)((char *)dst + dst_row*s1 + i02*s2 + i03*s3); + block_turbo2_0 * blk_base = dst_row_ptr + i_grp * blocks_per_group; + + // ---- Step 1: Load element j (coalesced) ---- + __shared__ float x[GROUP_SIZE]; + x[j] = src_row[i_grp * GROUP_SIZE + j]; + __syncthreads(); + + // ---- InnerQ: calibrate on original (unscaled) values ---- + if (d_innerq_calibrating) { + atomicAdd(&d_innerq_sq_accum[j], x[j] * x[j]); + if (j == 0) atomicAdd(&d_innerq_count, 1); + } + + // ---- InnerQ: apply channel scale (only when active) ---- + if (d_innerq_active) { + x[j] *= d_innerq_scale[j]; + } + __syncthreads(); + + // ---- Step 2: Parallel L2 norm ---- + constexpr int n_warps = GROUP_SIZE / WARP_SIZE; + __shared__ float warp_accum[n_warps]; + float v = x[j]; + float v2 = v * v; + for (int offset = WARP_SIZE / 2; offset > 0; offset >>= 1) + v2 += __shfl_xor_sync(0xffffffff, v2, offset); + if (j % WARP_SIZE == 0) + warp_accum[j / WARP_SIZE] = v2; + __syncthreads(); + + __shared__ float s_norm_sq; + if (j == 0) { + float total = 0.0f; + for (int w = 0; w < n_warps; w++) total += warp_accum[w]; + s_norm_sq = total; + } + __syncthreads(); + const float grp_norm = sqrtf(s_norm_sq); + const float inv_norm = (grp_norm > 1e-10f) ? 1.0f / grp_norm : 0.0f; + + // ---- Step 3: Normalize ---- + x[j] *= inv_norm; + __syncthreads(); + + // ---- Step 4: Forward WHT ---- + if (GROUP_SIZE == 128) { + x[j] *= TURBO_WHT_SIGNS1[j]; + } else { + x[j] *= TURBO_WHT_SIGNS1_64[j]; + } + __syncthreads(); + +#define WHT_STAGE_SHARED_T2(h) \ + if (j % (2*(h)) < (h)) { float a = x[j], b = x[j+(h)]; x[j] = a+b; x[j+(h)] = a-b; } \ + __syncthreads(); + + WHT_STAGE_SHARED_T2(1) + WHT_STAGE_SHARED_T2(2) + WHT_STAGE_SHARED_T2(4) + WHT_STAGE_SHARED_T2(8) + WHT_STAGE_SHARED_T2(16) + WHT_STAGE_SHARED_T2(32) + if (GROUP_SIZE == 128) { WHT_STAGE_SHARED_T2(64) } +#undef WHT_STAGE_SHARED_T2 + + constexpr float inv_sqrt_group = (GROUP_SIZE == 128) ? 0.08838834764831845f : 0.125f; + if (GROUP_SIZE == 128) { + x[j] = x[j] * inv_sqrt_group * TURBO_WHT_SIGNS2[j]; + } else { + x[j] = x[j] * inv_sqrt_group * TURBO_WHT_SIGNS2_64[j]; + } + __syncthreads(); + + // ---- Step 5: Quantize element j to 2-bit centroid ---- + const float rv = x[j]; + const uint8_t idx = turbo_nearest_centroid_2bit(rv); + + // ---- Step 6: Pack qs (warp-cooperative, no atomics) ---- + // Each warp handles 32 elements. With QK_TURBO2 > WARP_SIZE, multiple warps + // share one block and write to different byte offsets within it. + const int warp_id = j / WARP_SIZE; + const int lane = j % WARP_SIZE; + const int elem_in_block = j % QK_TURBO2; + block_turbo2_0 * blk = blk_base + (j / QK_TURBO2); + + // Pack qs: 4 elements per byte, 2 bits each. + const uint8_t my_bits = idx & 0x3; + uint8_t qs_byte = 0; +#pragma unroll + for (int k = 0; k < 4; k++) { + uint8_t contrib = __shfl_sync(0xffffffff, my_bits, (lane & ~3) + k); + qs_byte |= contrib << (k * 2); + } + if (lane % 4 == 0) blk->qs[elem_in_block / 4] = qs_byte; + + // No signs packing needed for turbo2 + + // ---- Step 7: Reconstruction norm ---- + const float c = TURBO_CENTROIDS_2BIT[idx]; + float rc = c * c; + for (int offset = WARP_SIZE / 2; offset > 0; offset >>= 1) + rc += __shfl_xor_sync(0xffffffff, rc, offset); + if (j % WARP_SIZE == 0) + warp_accum[j / WARP_SIZE] = rc; + __syncthreads(); + + __shared__ float s_recon_sq; + if (j == 0) { + float total = 0.0f; + for (int w = 0; w < n_warps; w++) total += warp_accum[w]; + s_recon_sq = total; + } + __syncthreads(); + const float recon_norm = sqrtf(s_recon_sq); + const float corrected_norm = (recon_norm > 1e-10f) ? grp_norm / recon_norm : grp_norm; + + // ---- Step 8: Write corrected norm (one per turbo2 block) ---- + if (elem_in_block == 0) blk->norm = __float2half(corrected_norm); + + GGML_UNUSED(ne10); + GGML_UNUSED(ne13); +} + +// ---- TurboQuant2 tail kernel: straight 2-bit quantize without WHT rotation ---- + +template +static __global__ void k_set_rows_turbo2_tail( + const float * __restrict__ src0, + const idx_t * __restrict__ src1, + block_turbo2_0 * __restrict__ dst, + const int64_t ne00, + const int64_t ne01, + const int64_t ne10, + const int64_t ne11, + const int64_t ne12, + const int64_t ne13, + const int64_t s01, + const int64_t s02, + const int64_t s03, + const int64_t s10, + const int64_t s11, + const int64_t s12, + const int64_t s1, + const int64_t s2, + const int64_t s3, + const int tail_size) { + + const int j = threadIdx.x; + + int64_t tmp = blockIdx.x; + const int64_t i01 = tmp % ne01; tmp /= ne01; + const int64_t i02 = tmp % ne12; + const int64_t i03 = tmp / ne12; + + const int64_t i11 = i01 % ne11; + const int64_t i10 = i01; + const int64_t i12 = i02; + + const int64_t dst_row = *(src1 + i10*s10 + i11*s11 + i12*s12); + const float * src_row = src0 + i01*s01 + i02*s02 + i03*s03; + block_turbo2_0 * dst_row_ptr = (block_turbo2_0 *)((char *)dst + dst_row*s1 + i02*s2 + i03*s3); + + const int64_t n_full = ne00 / QK_TURBO2_GROUP; + const int64_t tail_start = n_full * QK_TURBO2_GROUP; + block_turbo2_0 * blk_base = dst_row_ptr + n_full * (QK_TURBO2_GROUP / QK_TURBO2); + + // ---- Load ---- + const float val = src_row[tail_start + j]; + + // ---- L2 norm ---- + const int n_warps = tail_size / WARP_SIZE; + const int warp_id = j / WARP_SIZE; + const int lane = j % WARP_SIZE; + + __shared__ float warp_accum[4]; + float v2 = val * val; + for (int offset = WARP_SIZE / 2; offset > 0; offset >>= 1) + v2 += __shfl_xor_sync(0xffffffff, v2, offset); + if (lane == 0) warp_accum[warp_id] = v2; + __syncthreads(); + + __shared__ float s_norm_sq; + if (j == 0) { + float total = 0.0f; + for (int w = 0; w < n_warps; w++) total += warp_accum[w]; + s_norm_sq = total; + } + __syncthreads(); + const float grp_norm = sqrtf(s_norm_sq); + const float inv_norm = (grp_norm > 1e-10f) ? 1.0f / grp_norm : 0.0f; + + // ---- Normalize (no WHT!) ---- + const float rv = val * inv_norm; + + // ---- Quantize ---- + const uint8_t idx = turbo_nearest_centroid_2bit(rv); + + // ---- Pack qs ---- + block_turbo2_0 * blk = blk_base + warp_id; + + const uint8_t my_bits = idx & 0x3; + uint8_t qs_byte = 0; +#pragma unroll + for (int k = 0; k < 4; k++) { + uint8_t contrib = __shfl_sync(0xffffffff, my_bits, (lane & ~3) + k); + qs_byte |= contrib << (k * 2); + } + if (lane % 4 == 0) blk->qs[lane / 4] = qs_byte; + + // ---- Reconstruction norm ---- + const float c = TURBO_CENTROIDS_2BIT[idx]; + float rc = c * c; + for (int offset = WARP_SIZE / 2; offset > 0; offset >>= 1) + rc += __shfl_xor_sync(0xffffffff, rc, offset); + if (lane == 0) warp_accum[warp_id] = rc; + __syncthreads(); + + __shared__ float s_recon_sq; + if (j == 0) { + float total = 0.0f; + for (int w = 0; w < n_warps; w++) total += warp_accum[w]; + s_recon_sq = total; + } + __syncthreads(); + const float recon_norm = sqrtf(s_recon_sq); + const float corrected_norm = (recon_norm > 1e-10f) ? grp_norm / recon_norm : grp_norm; + + if (lane == 0) blk->norm = __float2half(corrected_norm); + + GGML_UNUSED(ne10); + GGML_UNUSED(ne13); + GGML_UNUSED(ne00); +} + +template +static void set_rows_cuda_turbo2( + ggml_backend_cuda_context & ctx, + const ggml_tensor * src0, + const ggml_tensor * src1, + ggml_tensor * dst) { + + const float * src0_d = (const float *)src0->data; + const idx_t * src1_d = (const idx_t *)src1->data; + + GGML_TENSOR_BINARY_OP_LOCALS + GGML_ASSERT(ne00 % QK_TURBO2 == 0); + + cudaStream_t stream = ctx.stream(); + + int group_size = 128; + memcpy(&group_size, dst->op_params, sizeof(int)); + if (group_size != 64 && group_size != 128) group_size = 128; + GGML_ASSERT(ne00 % group_size == 0); + + const int64_t n_full_groups = ne00 / group_size; + const int tail_size = (int)(ne00 % group_size); + + const int64_t s01 = nb01/sizeof(float); + const int64_t s02 = nb02/sizeof(float); + const int64_t s03 = nb03/sizeof(float); + const int64_t s10 = nb10/sizeof(idx_t); + const int64_t s11 = nb11/sizeof(idx_t); + const int64_t s12 = nb12/sizeof(idx_t); + + // InnerQ: check/finalize calibration before kernel launch + turbo_innerq_check_finalize(group_size, ne00); + + if (n_full_groups > 0) { + const int64_t ne_total = n_full_groups * ne01 * ne02 * ne03; + if (group_size == 128) { + k_set_rows_turbo2<<<(int)ne_total, 128, 0, stream>>>( + src0_d, src1_d, (block_turbo2_0 *)dst->data, + ne00, ne01, ne10, ne11, ne12, ne13, + s01, s02, s03, s10, s11, s12, + nb1, nb2, nb3); + } else { + k_set_rows_turbo2<<<(int)ne_total, 64, 0, stream>>>( + src0_d, src1_d, (block_turbo2_0 *)dst->data, + ne00, ne01, ne10, ne11, ne12, ne13, + s01, s02, s03, s10, s11, s12, + nb1, nb2, nb3); + } + } + + if (tail_size > 0) { + GGML_ASSERT(tail_size % QK_TURBO2 == 0); + const int64_t n_rows = ne01 * ne02 * ne03; + k_set_rows_turbo2_tail<<<(int)n_rows, tail_size, 0, stream>>>( + src0_d, src1_d, (block_turbo2_0 *)dst->data, + ne00, ne01, ne10, ne11, ne12, ne13, + s01, s02, s03, s10, s11, s12, + nb1, nb2, nb3, tail_size); + } +} + +// ---- TurboQuant4 set_rows: 128-element groups with WHT rotation + 4-bit quantization ---- +// +// turbo4 block size IS the WHT group size (128), so 1 CUDA block = 1 turbo4 block. +// 128 threads per block, thread j handles element j. +// 4-bit centroids (16 values), nibble packed: qs[j/2] |= (idx & 0xF) << ((j%2)*4) + +template +__launch_bounds__(128) +static __global__ void k_set_rows_turbo4( + const float * __restrict__ src0, + const idx_t * __restrict__ src1, + block_turbo4_0 * __restrict__ dst, + const int64_t ne00, + const int64_t ne01, + const int64_t ne10, + const int64_t ne11, + const int64_t ne12, + const int64_t ne13, + const int64_t s01, + const int64_t s02, + const int64_t s03, + const int64_t s10, + const int64_t s11, + const int64_t s12, + const int64_t s1, + const int64_t s2, + const int64_t s3) { + + // blockIdx.x = flat block index; threadIdx.x = element within block (0..127) + const int j = threadIdx.x; + + // Decode blockIdx.x → (i_blk, i01, i02, i03) + const int64_t n_blocks_per_row = ne00 / QK_TURBO4; + const int64_t g = blockIdx.x; + const int64_t i_blk = g % n_blocks_per_row; + int64_t tmp = g / n_blocks_per_row; + const int64_t i01 = tmp % ne01; + tmp = tmp / ne01; + const int64_t i02 = tmp % ne12; + const int64_t i03 = tmp / ne12; + + const int64_t i12 = i02; + const int64_t i11 = i01 % ne11; + const int64_t i10 = i01; + + const int64_t dst_row = *(src1 + i10*s10 + i11*s11 + i12*s12); + const float * src_row = src0 + i01*s01 + i02*s02 + i03*s03; + block_turbo4_0 * dst_row_ptr = (block_turbo4_0 *)((char *)dst + dst_row*s1 + i02*s2 + i03*s3); + block_turbo4_0 * blk = dst_row_ptr + i_blk; + + // ---- Step 1: Load element j (coalesced) ---- + __shared__ float x[128]; + x[j] = src_row[i_blk * QK_TURBO4 + j]; + __syncthreads(); + + // ---- InnerQ: calibrate on original (unscaled) values ---- + if (d_innerq_calibrating) { + atomicAdd(&d_innerq_sq_accum[j], x[j] * x[j]); + if (j == 0) atomicAdd(&d_innerq_count, 1); + } + + // ---- InnerQ: apply channel scale (only when active) ---- + if (d_innerq_active) { + x[j] *= d_innerq_scale[j]; + } + __syncthreads(); + + // ---- Step 2: Parallel L2 norm ---- + constexpr int n_warps = 128 / WARP_SIZE; // = 4 + __shared__ float warp_accum[n_warps]; + float v = x[j]; + float v2 = v * v; + for (int offset = WARP_SIZE / 2; offset > 0; offset >>= 1) + v2 += __shfl_xor_sync(0xffffffff, v2, offset); + if (j % WARP_SIZE == 0) + warp_accum[j / WARP_SIZE] = v2; + __syncthreads(); + + __shared__ float s_norm_sq; + if (j == 0) { + float total = 0.0f; + for (int w = 0; w < n_warps; w++) total += warp_accum[w]; + s_norm_sq = total; + } + __syncthreads(); + const float grp_norm = sqrtf(s_norm_sq); + const float inv_norm = (grp_norm > 1e-10f) ? 1.0f / grp_norm : 0.0f; + + // ---- Step 3: Normalize ---- + x[j] *= inv_norm; + __syncthreads(); + + // ---- Step 4: Forward WHT (signs1 → butterfly → signs2, normalized) ---- + x[j] *= TURBO_WHT_SIGNS1[j]; + __syncthreads(); + +#define WHT_STAGE_SHARED_T4(h) \ + if (j % (2*(h)) < (h)) { float a = x[j], b = x[j+(h)]; x[j] = a+b; x[j+(h)] = a-b; } \ + __syncthreads(); + + WHT_STAGE_SHARED_T4(1) + WHT_STAGE_SHARED_T4(2) + WHT_STAGE_SHARED_T4(4) + WHT_STAGE_SHARED_T4(8) + WHT_STAGE_SHARED_T4(16) + WHT_STAGE_SHARED_T4(32) + WHT_STAGE_SHARED_T4(64) +#undef WHT_STAGE_SHARED_T4 + + constexpr float inv_sqrt_128 = 0.08838834764831845f; + x[j] = x[j] * inv_sqrt_128 * TURBO_WHT_SIGNS2[j]; + __syncthreads(); + + // ---- Step 5: Quantize element j to 4-bit centroid ---- + const float rv = x[j]; + const uint8_t idx = turbo_nearest_centroid_4bit(rv); + + // ---- Step 6: Pack qs (nibble packed, warp-cooperative) ---- + // 2 elements per byte, 4 bits each. + // Thread pairs (j, j+1) share a qs byte. + const int lane = j % WARP_SIZE; + const uint8_t my_nibble = idx & 0xF; + uint8_t qs_byte = 0; + // Gather nibble from partner thread + uint8_t partner_nibble = __shfl_sync(0xffffffff, my_nibble, lane ^ 1); + if (j % 2 == 0) { + qs_byte = my_nibble | (partner_nibble << 4); + blk->qs[j / 2] = qs_byte; + } + + // ---- Step 7: Reconstruction norm (parallel) ---- + const float c = TURBO_CENTROIDS_4BIT[idx]; + float rc = c * c; + for (int offset = WARP_SIZE / 2; offset > 0; offset >>= 1) + rc += __shfl_xor_sync(0xffffffff, rc, offset); + if (j % WARP_SIZE == 0) + warp_accum[j / WARP_SIZE] = rc; + __syncthreads(); + + __shared__ float s_recon_sq; + if (j == 0) { + float total = 0.0f; + for (int w = 0; w < n_warps; w++) total += warp_accum[w]; + s_recon_sq = total; + } + __syncthreads(); + const float recon_norm = sqrtf(s_recon_sq); + const float corrected_norm = (recon_norm > 1e-10f) ? grp_norm / recon_norm : grp_norm; + + // ---- Step 8: Write corrected norm and zero rnorm (one thread) ---- + if (j == 0) { + blk->norm = __float2half(corrected_norm); + blk->rnorm = __float2half(0.0f); + } + + GGML_UNUSED(ne10); + GGML_UNUSED(ne13); +} + +template +static void set_rows_cuda_turbo4( + ggml_backend_cuda_context & ctx, + const ggml_tensor * src0, + const ggml_tensor * src1, + ggml_tensor * dst) { + + const float * src0_d = (const float *)src0->data; + const idx_t * src1_d = (const idx_t *)src1->data; + + GGML_TENSOR_BINARY_OP_LOCALS + GGML_ASSERT(ne00 % QK_TURBO4 == 0); // must be block-aligned (128) + + cudaStream_t stream = ctx.stream(); + + // turbo4 block size = WHT group size = 128, always + const int64_t n_blocks = ne00 / QK_TURBO4; + + const int64_t s01 = nb01/sizeof(float); + const int64_t s02 = nb02/sizeof(float); + const int64_t s03 = nb03/sizeof(float); + const int64_t s10 = nb10/sizeof(idx_t); + const int64_t s11 = nb11/sizeof(idx_t); + const int64_t s12 = nb12/sizeof(idx_t); + + // InnerQ: check/finalize calibration before kernel launch + turbo_innerq_check_finalize(QK_TURBO4, ne00); + + if (n_blocks > 0) { + const int64_t ne_total = n_blocks * ne01 * ne02 * ne03; + k_set_rows_turbo4<<<(int)ne_total, 128, 0, stream>>>( + src0_d, src1_d, (block_turbo4_0 *)dst->data, + ne00, ne01, ne10, ne11, ne12, ne13, + s01, s02, s03, s10, s11, s12, + nb1, nb2, nb3); + } +} + template static void set_rows_cuda(ggml_backend_cuda_context & ctx, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { const src_t * src0_d = (const src_t *)src0->data; @@ -309,6 +1232,12 @@ static void set_rows_cuda(ggml_backend_cuda_context & ctx, const ggml_tensor * s nb1, nb2, nb3, stream ); + } else if (dst->type == GGML_TYPE_TURBO3_0) { + set_rows_cuda_turbo3(ctx, src0, src1, dst); + } else if (dst->type == GGML_TYPE_TURBO2_0) { + set_rows_cuda_turbo2(ctx, src0, src1, dst); + } else if (dst->type == GGML_TYPE_TURBO4_0) { + set_rows_cuda_turbo4(ctx, src0, src1, dst); } else { GGML_ABORT("unsupported type %s", ggml_type_name(dst->type)); } diff --git a/ggml/src/ggml-cuda/template-instances/fattn-mma-f16-instance-ncols1_1-ncols2_16.cu b/ggml/src/ggml-cuda/template-instances/fattn-mma-f16-instance-ncols1_1-ncols2_16.cu index fb26abeb0da..b643d1d2daa 100644 --- a/ggml/src/ggml-cuda/template-instances/fattn-mma-f16-instance-ncols1_1-ncols2_16.cu +++ b/ggml/src/ggml-cuda/template-instances/fattn-mma-f16-instance-ncols1_1-ncols2_16.cu @@ -3,3 +3,4 @@ #include "../fattn-mma-f16.cuh" DECL_FATTN_MMA_F16_CASE(576, 512, 1, 16); +DECL_FATTN_MMA_F16_CASE(640, 512, 1, 16); diff --git a/ggml/src/ggml-cuda/template-instances/fattn-mma-f16-instance-ncols1_2-ncols2_16.cu b/ggml/src/ggml-cuda/template-instances/fattn-mma-f16-instance-ncols1_2-ncols2_16.cu index f011a208cd2..2580167449c 100644 --- a/ggml/src/ggml-cuda/template-instances/fattn-mma-f16-instance-ncols1_2-ncols2_16.cu +++ b/ggml/src/ggml-cuda/template-instances/fattn-mma-f16-instance-ncols1_2-ncols2_16.cu @@ -3,3 +3,4 @@ #include "../fattn-mma-f16.cuh" DECL_FATTN_MMA_F16_CASE(576, 512, 2, 16); +DECL_FATTN_MMA_F16_CASE(640, 512, 2, 16); diff --git a/ggml/src/ggml-cuda/template-instances/fattn-mma-f16-instance-ncols1_4-ncols2_16.cu b/ggml/src/ggml-cuda/template-instances/fattn-mma-f16-instance-ncols1_4-ncols2_16.cu index f5fd0e2369c..585e13d42ff 100644 --- a/ggml/src/ggml-cuda/template-instances/fattn-mma-f16-instance-ncols1_4-ncols2_16.cu +++ b/ggml/src/ggml-cuda/template-instances/fattn-mma-f16-instance-ncols1_4-ncols2_16.cu @@ -3,3 +3,4 @@ #include "../fattn-mma-f16.cuh" DECL_FATTN_MMA_F16_CASE(576, 512, 4, 16); +DECL_FATTN_MMA_F16_CASE(640, 512, 4, 16); diff --git a/ggml/src/ggml-cuda/template-instances/fattn-tile-instance-dkq640-dv512.cu b/ggml/src/ggml-cuda/template-instances/fattn-tile-instance-dkq640-dv512.cu new file mode 100644 index 00000000000..c68a841ad41 --- /dev/null +++ b/ggml/src/ggml-cuda/template-instances/fattn-tile-instance-dkq640-dv512.cu @@ -0,0 +1,5 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../fattn-tile.cuh" + +DECL_FATTN_TILE_CASE(640, 512); diff --git a/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q8_0-turbo2_0.cu b/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q8_0-turbo2_0.cu new file mode 100644 index 00000000000..3630d871af4 --- /dev/null +++ b/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q8_0-turbo2_0.cu @@ -0,0 +1,7 @@ +// Mixed KV: q8_0 K + turbo2 V + +#include "../fattn-vec.cuh" + +DECL_FATTN_VEC_CASE( 64, GGML_TYPE_Q8_0, GGML_TYPE_TURBO2_0); +DECL_FATTN_VEC_CASE(128, GGML_TYPE_Q8_0, GGML_TYPE_TURBO2_0); +DECL_FATTN_VEC_CASE(256, GGML_TYPE_Q8_0, GGML_TYPE_TURBO2_0); diff --git a/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q8_0-turbo3_0.cu b/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q8_0-turbo3_0.cu new file mode 100644 index 00000000000..c8a4d9f8993 --- /dev/null +++ b/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q8_0-turbo3_0.cu @@ -0,0 +1,7 @@ +// Mixed KV: q8_0 K + turbo3 V + +#include "../fattn-vec.cuh" + +DECL_FATTN_VEC_CASE( 64, GGML_TYPE_Q8_0, GGML_TYPE_TURBO3_0); +DECL_FATTN_VEC_CASE(128, GGML_TYPE_Q8_0, GGML_TYPE_TURBO3_0); +DECL_FATTN_VEC_CASE(256, GGML_TYPE_Q8_0, GGML_TYPE_TURBO3_0); diff --git a/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q8_0-turbo4_0.cu b/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q8_0-turbo4_0.cu new file mode 100644 index 00000000000..1646ef05dd1 --- /dev/null +++ b/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q8_0-turbo4_0.cu @@ -0,0 +1,7 @@ +// Mixed KV: q8_0 K + turbo4 V + +#include "../fattn-vec.cuh" + +DECL_FATTN_VEC_CASE( 64, GGML_TYPE_Q8_0, GGML_TYPE_TURBO4_0); +DECL_FATTN_VEC_CASE(128, GGML_TYPE_Q8_0, GGML_TYPE_TURBO4_0); +DECL_FATTN_VEC_CASE(256, GGML_TYPE_Q8_0, GGML_TYPE_TURBO4_0); diff --git a/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-turbo2_0-q8_0.cu b/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-turbo2_0-q8_0.cu new file mode 100644 index 00000000000..c9cd1afa8eb --- /dev/null +++ b/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-turbo2_0-q8_0.cu @@ -0,0 +1,7 @@ +// Mixed KV: turbo2 K + q8_0 V + +#include "../fattn-vec.cuh" + +DECL_FATTN_VEC_CASE( 64, GGML_TYPE_TURBO2_0, GGML_TYPE_Q8_0); +DECL_FATTN_VEC_CASE(128, GGML_TYPE_TURBO2_0, GGML_TYPE_Q8_0); +DECL_FATTN_VEC_CASE(256, GGML_TYPE_TURBO2_0, GGML_TYPE_Q8_0); diff --git a/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-turbo2_0-turbo2_0.cu b/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-turbo2_0-turbo2_0.cu new file mode 100644 index 00000000000..f68422d398a --- /dev/null +++ b/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-turbo2_0-turbo2_0.cu @@ -0,0 +1,7 @@ +// TurboQuant2 CUDA flash attention vec kernel instantiation + +#include "../fattn-vec.cuh" + +DECL_FATTN_VEC_CASE( 64, GGML_TYPE_TURBO2_0, GGML_TYPE_TURBO2_0); +DECL_FATTN_VEC_CASE(128, GGML_TYPE_TURBO2_0, GGML_TYPE_TURBO2_0); +DECL_FATTN_VEC_CASE(256, GGML_TYPE_TURBO2_0, GGML_TYPE_TURBO2_0); diff --git a/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-turbo2_0-turbo3_0.cu b/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-turbo2_0-turbo3_0.cu new file mode 100644 index 00000000000..334ad2098b5 --- /dev/null +++ b/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-turbo2_0-turbo3_0.cu @@ -0,0 +1,7 @@ +// Mixed KV: turbo2 K + turbo3 V + +#include "../fattn-vec.cuh" + +DECL_FATTN_VEC_CASE( 64, GGML_TYPE_TURBO2_0, GGML_TYPE_TURBO3_0); +DECL_FATTN_VEC_CASE(128, GGML_TYPE_TURBO2_0, GGML_TYPE_TURBO3_0); +DECL_FATTN_VEC_CASE(256, GGML_TYPE_TURBO2_0, GGML_TYPE_TURBO3_0); diff --git a/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-turbo2_0-turbo4_0.cu b/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-turbo2_0-turbo4_0.cu new file mode 100644 index 00000000000..56177a4cae9 --- /dev/null +++ b/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-turbo2_0-turbo4_0.cu @@ -0,0 +1,7 @@ +// Mixed KV: turbo2 K + turbo4 V + +#include "../fattn-vec.cuh" + +DECL_FATTN_VEC_CASE( 64, GGML_TYPE_TURBO2_0, GGML_TYPE_TURBO4_0); +DECL_FATTN_VEC_CASE(128, GGML_TYPE_TURBO2_0, GGML_TYPE_TURBO4_0); +DECL_FATTN_VEC_CASE(256, GGML_TYPE_TURBO2_0, GGML_TYPE_TURBO4_0); diff --git a/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-turbo3_0-q8_0.cu b/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-turbo3_0-q8_0.cu new file mode 100644 index 00000000000..601e4da41d4 --- /dev/null +++ b/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-turbo3_0-q8_0.cu @@ -0,0 +1,7 @@ +// Mixed KV: turbo3 K + q8_0 V + +#include "../fattn-vec.cuh" + +DECL_FATTN_VEC_CASE( 64, GGML_TYPE_TURBO3_0, GGML_TYPE_Q8_0); +DECL_FATTN_VEC_CASE(128, GGML_TYPE_TURBO3_0, GGML_TYPE_Q8_0); +DECL_FATTN_VEC_CASE(256, GGML_TYPE_TURBO3_0, GGML_TYPE_Q8_0); diff --git a/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-turbo3_0-turbo2_0.cu b/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-turbo3_0-turbo2_0.cu new file mode 100644 index 00000000000..f8a5932537e --- /dev/null +++ b/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-turbo3_0-turbo2_0.cu @@ -0,0 +1,7 @@ +// Mixed KV: turbo3 K + turbo2 V + +#include "../fattn-vec.cuh" + +DECL_FATTN_VEC_CASE( 64, GGML_TYPE_TURBO3_0, GGML_TYPE_TURBO2_0); +DECL_FATTN_VEC_CASE(128, GGML_TYPE_TURBO3_0, GGML_TYPE_TURBO2_0); +DECL_FATTN_VEC_CASE(256, GGML_TYPE_TURBO3_0, GGML_TYPE_TURBO2_0); diff --git a/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-turbo3_0-turbo3_0.cu b/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-turbo3_0-turbo3_0.cu new file mode 100644 index 00000000000..0322a3b0d09 --- /dev/null +++ b/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-turbo3_0-turbo3_0.cu @@ -0,0 +1,7 @@ +// TurboQuant3 CUDA flash attention vec kernel instantiation + +#include "../fattn-vec.cuh" + +DECL_FATTN_VEC_CASE( 64, GGML_TYPE_TURBO3_0, GGML_TYPE_TURBO3_0); +DECL_FATTN_VEC_CASE(128, GGML_TYPE_TURBO3_0, GGML_TYPE_TURBO3_0); +DECL_FATTN_VEC_CASE(256, GGML_TYPE_TURBO3_0, GGML_TYPE_TURBO3_0); diff --git a/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-turbo3_0-turbo4_0.cu b/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-turbo3_0-turbo4_0.cu new file mode 100644 index 00000000000..0634006716a --- /dev/null +++ b/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-turbo3_0-turbo4_0.cu @@ -0,0 +1,7 @@ +// Mixed KV: turbo3 K + turbo4 V + +#include "../fattn-vec.cuh" + +DECL_FATTN_VEC_CASE( 64, GGML_TYPE_TURBO3_0, GGML_TYPE_TURBO4_0); +DECL_FATTN_VEC_CASE(128, GGML_TYPE_TURBO3_0, GGML_TYPE_TURBO4_0); +DECL_FATTN_VEC_CASE(256, GGML_TYPE_TURBO3_0, GGML_TYPE_TURBO4_0); diff --git a/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-turbo4_0-q8_0.cu b/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-turbo4_0-q8_0.cu new file mode 100644 index 00000000000..7e1e4c74340 --- /dev/null +++ b/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-turbo4_0-q8_0.cu @@ -0,0 +1,7 @@ +// Mixed KV: turbo4 K + q8_0 V + +#include "../fattn-vec.cuh" + +DECL_FATTN_VEC_CASE( 64, GGML_TYPE_TURBO4_0, GGML_TYPE_Q8_0); +DECL_FATTN_VEC_CASE(128, GGML_TYPE_TURBO4_0, GGML_TYPE_Q8_0); +DECL_FATTN_VEC_CASE(256, GGML_TYPE_TURBO4_0, GGML_TYPE_Q8_0); diff --git a/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-turbo4_0-turbo2_0.cu b/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-turbo4_0-turbo2_0.cu new file mode 100644 index 00000000000..a0cffecf86a --- /dev/null +++ b/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-turbo4_0-turbo2_0.cu @@ -0,0 +1,7 @@ +// Mixed KV: turbo4 K + turbo2 V + +#include "../fattn-vec.cuh" + +DECL_FATTN_VEC_CASE( 64, GGML_TYPE_TURBO4_0, GGML_TYPE_TURBO2_0); +DECL_FATTN_VEC_CASE(128, GGML_TYPE_TURBO4_0, GGML_TYPE_TURBO2_0); +DECL_FATTN_VEC_CASE(256, GGML_TYPE_TURBO4_0, GGML_TYPE_TURBO2_0); diff --git a/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-turbo4_0-turbo3_0.cu b/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-turbo4_0-turbo3_0.cu new file mode 100644 index 00000000000..54e93bd9cd3 --- /dev/null +++ b/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-turbo4_0-turbo3_0.cu @@ -0,0 +1,7 @@ +// Mixed KV: turbo4 K + turbo3 V + +#include "../fattn-vec.cuh" + +DECL_FATTN_VEC_CASE( 64, GGML_TYPE_TURBO4_0, GGML_TYPE_TURBO3_0); +DECL_FATTN_VEC_CASE(128, GGML_TYPE_TURBO4_0, GGML_TYPE_TURBO3_0); +DECL_FATTN_VEC_CASE(256, GGML_TYPE_TURBO4_0, GGML_TYPE_TURBO3_0); diff --git a/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-turbo4_0-turbo4_0.cu b/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-turbo4_0-turbo4_0.cu new file mode 100644 index 00000000000..b49c683291d --- /dev/null +++ b/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-turbo4_0-turbo4_0.cu @@ -0,0 +1,7 @@ +// TurboQuant4 CUDA flash attention vec kernel instantiation + +#include "../fattn-vec.cuh" + +DECL_FATTN_VEC_CASE( 64, GGML_TYPE_TURBO4_0, GGML_TYPE_TURBO4_0); +DECL_FATTN_VEC_CASE(128, GGML_TYPE_TURBO4_0, GGML_TYPE_TURBO4_0); +DECL_FATTN_VEC_CASE(256, GGML_TYPE_TURBO4_0, GGML_TYPE_TURBO4_0); diff --git a/ggml/src/ggml-cuda/turbo-innerq.cu b/ggml/src/ggml-cuda/turbo-innerq.cu new file mode 100644 index 00000000000..af8b7f3f8e0 --- /dev/null +++ b/ggml/src/ggml-cuda/turbo-innerq.cu @@ -0,0 +1,32 @@ +#include "turbo-innerq.cuh" +#include + +// Host-side shared state for InnerQ cross-TU communication +TURBO_IQ_API bool g_innerq_finalized = false; +TURBO_IQ_API float g_innerq_scale_inv_host[INNERQ_MAX_CHANNELS] = { + 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, + 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, + 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, + 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 +}; + +static bool g_innerq_tensor_needs_update = false; + +void turbo_innerq_publish(const float * scale_inv, int group_size) { + for (int i = 0; i < group_size && i < INNERQ_MAX_CHANNELS; i++) { + g_innerq_scale_inv_host[i] = scale_inv[i]; + } + for (int i = group_size; i < INNERQ_MAX_CHANNELS; i++) { + g_innerq_scale_inv_host[i] = 1.0f; + } + g_innerq_finalized = true; + g_innerq_tensor_needs_update = true; +} + +TURBO_IQ_API bool turbo_innerq_needs_tensor_update(void) { + return g_innerq_tensor_needs_update; +} + +TURBO_IQ_API void turbo_innerq_mark_tensor_updated(void) { + g_innerq_tensor_needs_update = false; +} diff --git a/ggml/src/ggml-cuda/turbo-innerq.cuh b/ggml/src/ggml-cuda/turbo-innerq.cuh new file mode 100644 index 00000000000..42ca1b07eb4 --- /dev/null +++ b/ggml/src/ggml-cuda/turbo-innerq.cuh @@ -0,0 +1,30 @@ +#pragma once + +// TurboQuant InnerQ per-channel equalization — cross-TU shared state +// The host-side state lives in turbo-innerq.cu; device-side state is per-TU +// in turbo-quant.cuh (only set-rows.cu needs device access). + +#define INNERQ_MAX_CHANNELS 128 + +#if defined(_WIN32) && !defined(__MINGW32__) +# ifdef GGML_BACKEND_BUILD +# define TURBO_IQ_API __declspec(dllexport) +# else +# define TURBO_IQ_API __declspec(dllimport) +# endif +#else +# define TURBO_IQ_API __attribute__((visibility("default"))) +#endif + +// Host-side shared state (defined in turbo-innerq.cu) +TURBO_IQ_API extern bool g_innerq_finalized; +TURBO_IQ_API extern float g_innerq_scale_inv_host[INNERQ_MAX_CHANNELS]; + +// Called from set-rows.cu after InnerQ finalization to publish scale_inv +void turbo_innerq_publish(const float * scale_inv, int group_size); + +// Called from llama-kv-cache.cpp (or equivalent) to check if tensor needs update +TURBO_IQ_API bool turbo_innerq_needs_tensor_update(void); + +// Called after tensor update to clear the flag +TURBO_IQ_API void turbo_innerq_mark_tensor_updated(void); diff --git a/ggml/src/ggml-cuda/turbo-quant.cuh b/ggml/src/ggml-cuda/turbo-quant.cuh new file mode 100644 index 00000000000..11d8de75620 --- /dev/null +++ b/ggml/src/ggml-cuda/turbo-quant.cuh @@ -0,0 +1,453 @@ +/* + * TurboQuant CUDA kernels for KV cache compression + * Based on: arXiv 2504.19874 (ICLR 2026) + * + * Implements GGML_TYPE_TURBO3_0 (3-bit PolarQuant, block size 32) + * Constants, WHT rotation, quantize/dequantize device functions. + */ + +#pragma once + +#include "common.cuh" +#include "turbo-innerq.cuh" +#include +#include + +// ---- Quantization ratios for dequantize_block template ---- +#define QR_TURBO3 1 // Each dequantize call produces 2 consecutive elements (like q8_0) +#define QR_TURBO2 1 // Each dequantize call produces 2 consecutive elements (like q8_0) +#define QR_TURBO4 1 // Each dequantize call produces 2 consecutive elements (like q8_0) + +// ---- 2-bit centroids (Lloyd-Max for N(0, 1/128)) ---- + +static __constant__ float TURBO_CENTROIDS_2BIT[4] = { + -0.133462f, -0.039994f, 0.039994f, 0.133462f +}; + +static __constant__ float TURBO_MID_2BIT[3] = { + -0.086728f, 0.0f, 0.086728f +}; + +// ---- 3-bit centroids (Lloyd-Max for N(0, 1/128)) ---- + +static __constant__ float TURBO_CENTROIDS_3BIT[8] = { + -0.190685f, -0.117832f, -0.065717f, -0.021460f, + 0.021460f, 0.065717f, 0.117832f, 0.190685f +}; + +// ---- Midpoints for nearest centroid lookup ---- + +static __constant__ float TURBO_MID_3BIT[7] = { + -0.154259f, -0.091775f, -0.043589f, 0.0f, + 0.043589f, 0.091775f, 0.154259f +}; + +// ---- WHT sign arrays (seed=42) ---- + +static __constant__ float TURBO_WHT_SIGNS1[128] = { + -1.0f, 1.0f, 1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, -1.0f, 1.0f, 1.0f, 1.0f, 1.0f, 1.0f, 1.0f, + 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, -1.0f, 1.0f, 1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, -1.0f, -1.0f, + -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, + 1.0f, 1.0f, 1.0f, -1.0f, -1.0f, -1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, 1.0f, 1.0f, -1.0f, 1.0f, + -1.0f, -1.0f, 1.0f, -1.0f, -1.0f, -1.0f, 1.0f, -1.0f, -1.0f, -1.0f, 1.0f, -1.0f, -1.0f, -1.0f, 1.0f, 1.0f, + 1.0f, -1.0f, -1.0f, 1.0f, 1.0f, 1.0f, -1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, -1.0f, + -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, 1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, + 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, -1.0f, -1.0f, -1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f +}; + +static __constant__ float TURBO_WHT_SIGNS2[128] = { + 1.0f, 1.0f, 1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, -1.0f, -1.0f, -1.0f, 1.0f, -1.0f, -1.0f, -1.0f, + 1.0f, 1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, 1.0f, + 1.0f, 1.0f, -1.0f, -1.0f, -1.0f, 1.0f, -1.0f, -1.0f, -1.0f, -1.0f, -1.0f, -1.0f, 1.0f, 1.0f, 1.0f, -1.0f, + 1.0f, -1.0f, 1.0f, 1.0f, 1.0f, -1.0f, -1.0f, 1.0f, -1.0f, -1.0f, -1.0f, -1.0f, -1.0f, -1.0f, 1.0f, 1.0f, + 1.0f, -1.0f, 1.0f, -1.0f, -1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, -1.0f, 1.0f, 1.0f, + -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, -1.0f, -1.0f, -1.0f, -1.0f, 1.0f, -1.0f, -1.0f, 1.0f, -1.0f, + 1.0f, -1.0f, 1.0f, 1.0f, 1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, -1.0f, 1.0f, + -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, -1.0f, -1.0f, -1.0f, -1.0f, 1.0f, -1.0f +}; + +// ---- 64-element WHT sign arrays (first 64 of the 128-element arrays) ---- + +static __constant__ float TURBO_WHT_SIGNS1_64[64] = { + -1.0f, 1.0f, 1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, -1.0f, 1.0f, 1.0f, 1.0f, 1.0f, 1.0f, 1.0f, + 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, -1.0f, 1.0f, 1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, -1.0f, -1.0f, + -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, + 1.0f, 1.0f, 1.0f, -1.0f, -1.0f, -1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, 1.0f, 1.0f, -1.0f, 1.0f +}; + +static __constant__ float TURBO_WHT_SIGNS2_64[64] = { + 1.0f, 1.0f, 1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, -1.0f, -1.0f, -1.0f, 1.0f, -1.0f, -1.0f, -1.0f, + 1.0f, 1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, 1.0f, + 1.0f, 1.0f, -1.0f, -1.0f, -1.0f, 1.0f, -1.0f, -1.0f, -1.0f, -1.0f, -1.0f, -1.0f, 1.0f, 1.0f, 1.0f, -1.0f, + 1.0f, -1.0f, 1.0f, 1.0f, 1.0f, -1.0f, -1.0f, 1.0f, -1.0f, -1.0f, -1.0f, -1.0f, -1.0f, -1.0f, 1.0f, 1.0f +}; + +// ---- Fast Walsh-Hadamard Transform (in-place, normalized) ---- +// O(n log n) = 896 ops for n=128 + +static __device__ __forceinline__ void turbo_fwht_128(float * x) { + for (int h = 1; h < 128; h *= 2) { + for (int i = 0; i < 128; i += h * 2) { + for (int j = i; j < i + h; j++) { + float a = x[j]; + float b = x[j + h]; + x[j] = a + b; + x[j + h] = a - b; + } + } + } + const float inv_sqrt_128 = 0.08838834764831845f; + for (int i = 0; i < 128; i++) { + x[i] *= inv_sqrt_128; + } +} + +// ---- Fast Walsh-Hadamard Transform for 64-element groups ---- +// O(n log n) = 384 ops for n=64 + +static __device__ __forceinline__ void turbo_fwht_64(float * x) { + for (int h = 1; h < 64; h *= 2) { + for (int i = 0; i < 64; i += h * 2) { + for (int j = i; j < i + h; j++) { + float a = x[j]; + float b = x[j + h]; + x[j] = a + b; + x[j + h] = a - b; + } + } + } + const float inv_sqrt_64 = 0.125f; + for (int i = 0; i < 64; i++) { + x[i] *= inv_sqrt_64; + } +} + +// ---- Forward rotation: signs1 → FWHT → signs2 ---- + +static __device__ __forceinline__ void turbo_rotate_forward(float * x) { + for (int i = 0; i < 128; i++) x[i] *= TURBO_WHT_SIGNS1[i]; + turbo_fwht_128(x); + for (int i = 0; i < 128; i++) x[i] *= TURBO_WHT_SIGNS2[i]; +} + +// ---- Forward rotation for 64-element groups ---- + +static __device__ __forceinline__ void turbo_rotate_forward_64(float * x) { + for (int i = 0; i < 64; i++) x[i] *= TURBO_WHT_SIGNS1_64[i]; + turbo_fwht_64(x); + for (int i = 0; i < 64; i++) x[i] *= TURBO_WHT_SIGNS2_64[i]; +} + +// ---- InnerQ per-channel equalization ---- +// Equalizes K channel variances before WHT rotation to reduce quantization error. +// Enabled via TURBO_INNERQ=N env var (N = calibration token count). +// Math: = preserves dot products. +// INNERQ_MAX_CHANNELS is defined in turbo-innerq.cuh + +static __device__ float d_innerq_scale[INNERQ_MAX_CHANNELS]; +static __device__ float d_innerq_scale_inv[INNERQ_MAX_CHANNELS]; +static __device__ float d_innerq_sq_accum[INNERQ_MAX_CHANNELS]; +static __device__ int d_innerq_count; +static __device__ int d_innerq_active; // 0 = scales are identity, 1 = scales applied +static __device__ int d_innerq_calibrating; // 1 = accumulating K² stats + +static int innerq_enabled = 0; // host: 0=off, 1=calibrating, 2=active +static int innerq_target_tokens = 0; +static float innerq_strength = 0.5f; +static bool innerq_initialized = false; + +// Host: read TURBO_INNERQ env, start calibration if enabled +static void turbo_innerq_init(void) { + if (innerq_initialized) return; + innerq_initialized = true; + + const char * env = getenv("TURBO_INNERQ"); + if (!env || atoi(env) <= 0) { + innerq_enabled = 0; + return; + } + innerq_target_tokens = atoi(env); + innerq_enabled = 1; // calibrating + + const char * env_str = getenv("TURBO_INNERQ_STRENGTH"); + if (env_str) innerq_strength = atof(env_str); + if (innerq_strength <= 0.0f || innerq_strength > 1.0f) innerq_strength = 0.5f; + + // Zero accumulators and set calibrating flag on device + float zeros[INNERQ_MAX_CHANNELS] = {0}; + int zero = 0, one = 1; + cudaMemcpyToSymbol(d_innerq_sq_accum, zeros, sizeof(zeros)); + cudaMemcpyToSymbol(d_innerq_count, &zero, sizeof(int)); + cudaMemcpyToSymbol(d_innerq_active, &zero, sizeof(int)); + cudaMemcpyToSymbol(d_innerq_calibrating, &one, sizeof(int)); + + GGML_LOG_INFO("%s: InnerQ calibration started (target=%d tokens, strength=%.2f)\n", + __func__, innerq_target_tokens, innerq_strength); +} + +// Host: finalize calibration — compute scales, upload, activate +static void turbo_innerq_finalize(int group_size) { + // Read accumulators from device + float sq_accum[INNERQ_MAX_CHANNELS]; + int count = 0; + cudaMemcpyFromSymbol(sq_accum, d_innerq_sq_accum, group_size * sizeof(float)); + cudaMemcpyFromSymbol(&count, d_innerq_count, sizeof(int)); + + if (count <= 0) { + GGML_LOG_WARN("%s: InnerQ calibration got 0 tokens, disabling\n", __func__); + innerq_enabled = 0; + int zero = 0; + cudaMemcpyToSymbol(d_innerq_calibrating, &zero, sizeof(int)); + return; + } + + // Compute per-channel RMS + float rms[INNERQ_MAX_CHANNELS]; + float mean_rms = 0.0f; + float max_ratio = 0.0f, min_ratio = 1e30f; + for (int i = 0; i < group_size; i++) { + rms[i] = sqrtf(sq_accum[i] / (float)count); + mean_rms += rms[i]; + } + mean_rms /= (float)group_size; + + // Compute scale[i] = (mean_rms / channel_rms[i])^strength, clamp to [0.5, 2.0] + float scale[INNERQ_MAX_CHANNELS]; + float scale_inv[INNERQ_MAX_CHANNELS]; + for (int i = 0; i < group_size; i++) { + float ratio = (rms[i] > 1e-10f) ? (mean_rms / rms[i]) : 1.0f; + float s = powf(ratio, innerq_strength); + if (s < 0.5f) s = 0.5f; + if (s > 2.0f) s = 2.0f; + scale[i] = s; + scale_inv[i] = 1.0f / s; + if (ratio > max_ratio) max_ratio = ratio; + if (ratio < min_ratio) min_ratio = ratio; + } + + // Auto-skip if max channel ratio < 1.2 (already balanced) + if (max_ratio < 1.2f && min_ratio > (1.0f / 1.2f)) { + GGML_LOG_INFO("%s: InnerQ auto-disabled (channels already balanced, max_ratio=%.3f)\n", + __func__, max_ratio); + innerq_enabled = 0; + int zero = 0; + cudaMemcpyToSymbol(d_innerq_calibrating, &zero, sizeof(int)); + return; + } + + // Stop calibrating, upload scales, activate + int zero = 0, one = 1; + cudaMemcpyToSymbol(d_innerq_calibrating, &zero, sizeof(int)); + cudaMemcpyToSymbol(d_innerq_scale, scale, group_size * sizeof(float)); + cudaMemcpyToSymbol(d_innerq_scale_inv, scale_inv, group_size * sizeof(float)); + cudaDeviceSynchronize(); // ensure scales are visible before activating + cudaMemcpyToSymbol(d_innerq_active, &one, sizeof(int)); + + innerq_enabled = 2; // active + + // Publish scale_inv to shared host state for cross-TU tensor update + turbo_innerq_publish(scale_inv, group_size); + + GGML_LOG_INFO("%s: InnerQ finalized (%d tokens, max_ratio=%.3f, min_ratio=%.3f)\n", + __func__, count, max_ratio, min_ratio); +} + +// Host: called before each set_rows kernel launch +static void turbo_innerq_check_finalize(int group_size, int64_t ne00) { + if (!innerq_initialized) { + turbo_innerq_init(); + } + if (innerq_enabled == 0) return; + + // InnerQ only works when each WHT group = one head (group_size == head_dim). + // For standard models: ne00 = n_heads * head_dim, group_size = head_dim → ne00 % group_size == 0, fine. + // For non-standard models (head_dim > group_size, e.g. GLM 576 → 64-group): + // ne00 = head_dim (single head), group_size = 64, ne00/group_size = 9 groups per head → WRONG. + // Detect: if ne00 / group_size doesn't divide evenly into standard head counts (1,2,4,8,16,32,64,128), + // it's likely multi-group-per-head. Simpler check: group_size < 128 means head_dim > 128. + const bool multi_group_per_head = (group_size < 128); // 64-group → head_dim > 128, multi-group + if (multi_group_per_head) { + if (innerq_enabled == 1) { + GGML_LOG_WARN("%s: InnerQ disabled (ne00=%lld != group_size=%d, multi-group heads)\n", + __func__, (long long)ne00, group_size); + innerq_enabled = 0; + int zero = 0; + cudaMemcpyToSymbol(d_innerq_calibrating, &zero, sizeof(int)); + } + return; + } + + // Check if calibration is complete + if (innerq_enabled == 1) { + int count = 0; + cudaMemcpyFromSymbol(&count, d_innerq_count, sizeof(int)); + if (count >= innerq_target_tokens) { + turbo_innerq_finalize(group_size); + } + } +} + +// Host: check if InnerQ is currently active (finalized) +static bool turbo_innerq_is_active(void) { + return innerq_enabled == 2; +} + +// ---- 4-bit centroids (Lloyd-Max for N(0, 1/128)) ---- + +static __constant__ float TURBO_CENTROIDS_4BIT[16] = { + -0.173926f, -0.117195f, -0.089527f, -0.068756f, + -0.051262f, -0.035597f, -0.020989f, -0.006938f, + 0.006938f, 0.020989f, 0.035597f, 0.051262f, + 0.068756f, 0.089527f, 0.117195f, 0.173926f +}; + +// ---- Midpoints for nearest 4-bit centroid lookup ---- + +static __constant__ float TURBO_MID_4BIT[15] = { + -0.145561f, -0.103361f, -0.079142f, -0.060009f, + -0.043430f, -0.028293f, -0.013964f, 0.000000f, + 0.013964f, 0.028293f, 0.043430f, 0.060009f, + 0.079142f, 0.103361f, 0.145561f +}; + +// ---- Nearest 4-bit centroid index ---- + +static __device__ __forceinline__ uint8_t turbo_nearest_centroid_4bit(float val) { + if (val < TURBO_MID_4BIT[ 0]) return 0; + else if (val < TURBO_MID_4BIT[ 1]) return 1; + else if (val < TURBO_MID_4BIT[ 2]) return 2; + else if (val < TURBO_MID_4BIT[ 3]) return 3; + else if (val < TURBO_MID_4BIT[ 4]) return 4; + else if (val < TURBO_MID_4BIT[ 5]) return 5; + else if (val < TURBO_MID_4BIT[ 6]) return 6; + else if (val < TURBO_MID_4BIT[ 7]) return 7; + else if (val < TURBO_MID_4BIT[ 8]) return 8; + else if (val < TURBO_MID_4BIT[ 9]) return 9; + else if (val < TURBO_MID_4BIT[10]) return 10; + else if (val < TURBO_MID_4BIT[11]) return 11; + else if (val < TURBO_MID_4BIT[12]) return 12; + else if (val < TURBO_MID_4BIT[13]) return 13; + else if (val < TURBO_MID_4BIT[14]) return 14; + else return 15; +} + +// ---- Per-block quantize for turbo4 (128 elements, expects already-rotated input) ---- + +static __device__ void quantize_f32_turbo4_0_block(const float * __restrict__ src, + block_turbo4_0 * __restrict__ dst) { + for (int j = 0; j < QK_TURBO4 / 2; j++) dst->qs[j] = 0; + + for (int j = 0; j < QK_TURBO4; j++) { + uint8_t idx = turbo_nearest_centroid_4bit(src[j]); + dst->qs[j / 2] |= (idx & 0xF) << ((j % 2) * 4); + } +} + +// ---- Inline dequant helper: extract one float from turbo4 block ---- + +static __device__ __forceinline__ float turbo4_dequant_element( + const block_turbo4_0 * __restrict__ x, int j, float norm) { + uint8_t idx = (x->qs[j / 2] >> ((j % 2) * 4)) & 0xF; + return TURBO_CENTROIDS_4BIT[idx] * norm; +} + +// ---- Nearest 3-bit centroid index ---- + +static __device__ __forceinline__ uint8_t turbo_nearest_centroid_3bit(float val) { + if (val < TURBO_MID_3BIT[0]) return 0; + else if (val < TURBO_MID_3BIT[1]) return 1; + else if (val < TURBO_MID_3BIT[2]) return 2; + else if (val < TURBO_MID_3BIT[3]) return 3; + else if (val < TURBO_MID_3BIT[4]) return 4; + else if (val < TURBO_MID_3BIT[5]) return 5; + else if (val < TURBO_MID_3BIT[6]) return 6; + else return 7; +} + +// ---- Per-block quantize (32 elements, expects already-rotated input) ---- +// Used by set_rows after group-level WHT rotation + +static __device__ void quantize_f32_turbo3_0_block(const float * __restrict__ src, + block_turbo3_0 * __restrict__ dst) { + for (int j = 0; j < QK_TURBO3 / 4; j++) dst->qs[j] = 0; + for (int j = 0; j < QK_TURBO3 / 8; j++) dst->signs[j] = 0; + + for (int j = 0; j < QK_TURBO3; j++) { + uint8_t idx = turbo_nearest_centroid_3bit(src[j]); + dst->qs[j / 4] |= (idx & 0x3) << ((j % 4) * 2); + if (idx & 0x4) { + dst->signs[j / 8] |= (1 << (j % 8)); + } + } +} + +// ---- Inline dequant helper: extract one float from turbo3 block ---- + +static __device__ __forceinline__ float turbo3_dequant_element( + const block_turbo3_0 * __restrict__ x, int j, float norm) { + uint8_t low2 = (x->qs[j / 4] >> ((j % 4) * 2)) & 0x3; + uint8_t hi1 = (x->signs[j / 8] >> (j % 8)) & 0x1; + uint8_t idx = low2 | (hi1 << 2); + return TURBO_CENTROIDS_3BIT[idx] * norm; +} + +// ---- Nearest 2-bit centroid index ---- + +static __device__ __forceinline__ uint8_t turbo_nearest_centroid_2bit(float val) { + if (val < TURBO_MID_2BIT[0]) return 0; + else if (val < TURBO_MID_2BIT[1]) return 1; + else if (val < TURBO_MID_2BIT[2]) return 2; + else return 3; +} + +// ---- Per-block quantize for turbo2 (32 elements, expects already-rotated input) ---- + +static __device__ void quantize_f32_turbo2_0_block(const float * __restrict__ src, + block_turbo2_0 * __restrict__ dst) { + for (int j = 0; j < QK_TURBO2 / 4; j++) dst->qs[j] = 0; + + for (int j = 0; j < QK_TURBO2; j++) { + uint8_t idx = turbo_nearest_centroid_2bit(src[j]); + dst->qs[j / 4] |= (idx & 0x3) << ((j % 4) * 2); + } +} + +// ---- Inline dequant helper: extract one float from turbo2 block ---- + +static __device__ __forceinline__ float turbo2_dequant_element( + const block_turbo2_0 * __restrict__ x, int j, float norm) { + uint8_t idx = (x->qs[j / 4] >> ((j % 4) * 2)) & 0x3; + return TURBO_CENTROIDS_2BIT[idx] * norm; +} + +// ============================================================================ +// Weight compression types (TQ3_1S, TQ4_1S) +// These use N(0,1) centroids (NOT N(0,1/128) like KV cache types) +// and require inverse WHT (RHT) after centroid lookup. +// ============================================================================ + +#define QR_TQ4_1S 1 // dequantize produces 2 consecutive elements +#define QR_TQ3_1S 1 + +// ---- Weight centroids: Lloyd-Max for N(0,1) ---- + +static __constant__ float TQ4_CENTROIDS_WEIGHT[16] = { + -2.732590f, -2.069017f, -1.618046f, -1.256231f, + -0.942340f, -0.656759f, -0.388048f, -0.128395f, + 0.128395f, 0.388048f, 0.656759f, 0.942340f, + 1.256231f, 1.618046f, 2.069017f, 2.732590f +}; + +static __constant__ float TQ3_CENTROIDS_WEIGHT[8] = { + -1.996684f, -1.291398f, -0.740341f, -0.247508f, + 0.230106f, 0.725222f, 1.277503f, 1.988943f +}; + +// ---- Sign array for weight WHT (golden ratio hash, 32 elements) ---- + +static __constant__ float TQ_WEIGHT_SIGNS[32] = { + +1.0f, -1.0f, +1.0f, -1.0f, +1.0f, +1.0f, -1.0f, +1.0f, + -1.0f, -1.0f, +1.0f, -1.0f, +1.0f, +1.0f, -1.0f, +1.0f, + -1.0f, -1.0f, +1.0f, -1.0f, +1.0f, -1.0f, -1.0f, +1.0f, + -1.0f, +1.0f, +1.0f, -1.0f, +1.0f, -1.0f, -1.0f, +1.0f +}; diff --git a/ggml/src/ggml-cuda/turbo-wht.cu b/ggml/src/ggml-cuda/turbo-wht.cu new file mode 100644 index 00000000000..65805f148ef --- /dev/null +++ b/ggml/src/ggml-cuda/turbo-wht.cu @@ -0,0 +1,189 @@ +#include "turbo-quant.cuh" +#include "turbo-wht.cuh" + +// ─── CUDA kernel ────────────────────────────────────────────────────────────── +// +// Templated on direction and group_size (128 or 64). +// One block per group, group_size threads per block. +// direction: 0 = forward (signs1 → WHT → signs2), 1 = inverse (signs2 → WHT → signs1) +// +// When head_dim is not a multiple of group_size, only the full groups +// within each head are processed. Tail elements are left unchanged (identity). +// +// Algorithm mirrors the CPU implementation in ggml-cpu/ops.cpp: +// 1. Apply s_first elementwise +// 2. Radix-2 Hadamard butterfly (log2(group_size) stages, in-place) +// 3. Normalize by 1/sqrt(group_size) and apply s_second elementwise +// +// InnerQ scale_inv: when non-null, applies per-channel inverse scaling for +// Q/V equalization. For forward (Q rotation): multiply BEFORE signs+WHT. +// For inverse (V un-rotation): multiply AFTER WHT+signs. + +template +static __global__ void k_turbo_wht_f32(const float * __restrict__ src, + float * __restrict__ dst, + const float * __restrict__ scale_inv, + int64_t n_groups, + int64_t head_dim, + int64_t groups_per_head) { + static_assert(group_size == 128 || group_size == 64 || group_size == 32, "group_size must be 128, 64, or 32"); + + const int64_t g = blockIdx.x; + if (g >= n_groups) return; + + const int t = threadIdx.x; // 0 .. group_size-1 + + // Map group index to position in the tensor: + // each head has groups_per_head full groups, then a gap of tail elements. + const int64_t head_idx = g / groups_per_head; + const int64_t grp_in_head = g % groups_per_head; + const int64_t base = head_idx * head_dim + grp_in_head * group_size; + + __shared__ float x[group_size]; + + // Load from global memory + x[t] = src[base + t]; + __syncthreads(); + + // InnerQ forward: apply scale_inv BEFORE signs+WHT (for Q pre-rotation) + if (direction == 0 && scale_inv != nullptr) { + x[t] *= scale_inv[t % group_size]; + __syncthreads(); + } + + // Apply first sign array + if (group_size == 128) { + x[t] *= (direction == 0) ? TURBO_WHT_SIGNS1[t] : TURBO_WHT_SIGNS2[t]; + } else if (group_size == 64) { + x[t] *= (direction == 0) ? TURBO_WHT_SIGNS1_64[t] : TURBO_WHT_SIGNS2_64[t]; + } else { + // group_size == 32: TQ weight signs (same for forward and inverse) + x[t] *= TQ_WEIGHT_SIGNS[t]; + } + __syncthreads(); + + // WHT butterfly — log2(group_size) stages. + // In stage h, threads where (t % (2h)) < h read x[t] and x[t+h], + // then write x[t] = a+b and x[t+h] = a-b. Each active thread + // owns a disjoint pair, so no intra-stage conflicts exist. +#define WHT_STAGE(h) \ + if (t % (2*(h)) < (h)) { float a = x[t], b = x[t+(h)]; x[t] = a+b; x[t+(h)] = a-b; } \ + __syncthreads(); + + WHT_STAGE(1) + WHT_STAGE(2) + WHT_STAGE(4) + WHT_STAGE(8) + WHT_STAGE(16) + if (group_size >= 64) { WHT_STAGE(32) } + if (group_size == 128) { WHT_STAGE(64) } +#undef WHT_STAGE + + // Normalize and apply second sign array, write to output + constexpr float inv_sqrt = (group_size == 128) ? 0.08838834764831845f : + (group_size == 64) ? 0.125f : + 0.17677669529663688f; // 1/sqrt(32) + float result; + if (group_size == 128) { + result = x[t] * inv_sqrt * + ((direction == 0) ? TURBO_WHT_SIGNS2[t] : TURBO_WHT_SIGNS1[t]); + } else if (group_size == 64) { + result = x[t] * inv_sqrt * + ((direction == 0) ? TURBO_WHT_SIGNS2_64[t] : TURBO_WHT_SIGNS1_64[t]); + } else { + // group_size == 32: normalize only (signs already applied before butterfly) + result = x[t] * inv_sqrt; + } + + // InnerQ inverse: apply scale_inv AFTER WHT+signs (for V un-rotation) + if (direction == 1 && scale_inv != nullptr) { + result *= scale_inv[t % group_size]; + } + + dst[base + t] = result; +} + +// ─── Simple copy kernel for tail elements (identity pass-through) ──────────── + +static __global__ void k_turbo_wht_copy_tail(const float * __restrict__ src, + float * __restrict__ dst, + int64_t n_heads, + int64_t head_dim, + int64_t tail_offset, + int tail_size) { + const int64_t i = (int64_t)blockIdx.x * blockDim.x + threadIdx.x; + if (i >= n_heads * tail_size) return; + + const int64_t head_idx = i / tail_size; + const int64_t tail_elem = i % tail_size; + const int64_t offset = head_idx * head_dim + tail_offset + tail_elem; + dst[offset] = src[offset]; +} + +// ─── Dispatch ───────────────────────────────────────────────────────────────── + +void ggml_cuda_turbo_wht(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { + const ggml_tensor * src = dst->src[0]; + const ggml_tensor * scale_tensor = dst->src[1]; // InnerQ scale_inv (may be NULL) + + GGML_ASSERT(src->type == GGML_TYPE_F32); + GGML_ASSERT(dst->type == GGML_TYPE_F32); + GGML_ASSERT(ggml_is_contiguous(src)); + GGML_ASSERT(ggml_is_contiguous(dst)); + + int direction; + int group_size; + memcpy(&direction, dst->op_params + 0, sizeof(int)); + memcpy(&group_size, dst->op_params + sizeof(int), sizeof(int)); + + const int64_t head_dim = src->ne[0]; + const int64_t n_heads = ggml_nelements(src) / head_dim; + + GGML_ASSERT(group_size == 32 || group_size == 64 || group_size == 128); + const int64_t groups_per_head = head_dim / group_size; + const int tail_size = (int)(head_dim % group_size); + const int64_t n_groups = groups_per_head * n_heads; + + const float * src_ptr = (const float *) src->data; + float * dst_ptr = (float *) dst->data; + const float * scale_inv_ptr = scale_tensor ? (const float *) scale_tensor->data : nullptr; + + cudaStream_t stream = ctx.stream(); + + // Process full groups + if (n_groups > 0) { + dim3 blocks(n_groups); + if (group_size == 128) { + dim3 threads(128); + if (direction == 0) { + k_turbo_wht_f32<0, 128><<>>(src_ptr, dst_ptr, scale_inv_ptr, n_groups, head_dim, groups_per_head); + } else { + k_turbo_wht_f32<1, 128><<>>(src_ptr, dst_ptr, scale_inv_ptr, n_groups, head_dim, groups_per_head); + } + } else if (group_size == 64) { + dim3 threads(64); + if (direction == 0) { + k_turbo_wht_f32<0, 64><<>>(src_ptr, dst_ptr, scale_inv_ptr, n_groups, head_dim, groups_per_head); + } else { + k_turbo_wht_f32<1, 64><<>>(src_ptr, dst_ptr, scale_inv_ptr, n_groups, head_dim, groups_per_head); + } + } else { + dim3 threads(32); + if (direction == 0) { + k_turbo_wht_f32<0, 32><<>>(src_ptr, dst_ptr, scale_inv_ptr, n_groups, head_dim, groups_per_head); + } else { + k_turbo_wht_f32<1, 32><<>>(src_ptr, dst_ptr, scale_inv_ptr, n_groups, head_dim, groups_per_head); + } + } + } + + // Pass through tail elements unchanged (no rotation) + // Not needed for 64-aligned dims but kept for completeness + if (tail_size > 0) { + const int64_t total_tail = n_heads * tail_size; + const int block_sz = 256; + const int n_blocks = (int)((total_tail + block_sz - 1) / block_sz); + k_turbo_wht_copy_tail<<>>( + src_ptr, dst_ptr, n_heads, head_dim, groups_per_head * group_size, tail_size); + } +} diff --git a/ggml/src/ggml-cuda/turbo-wht.cuh b/ggml/src/ggml-cuda/turbo-wht.cuh new file mode 100644 index 00000000000..3038a1ab082 --- /dev/null +++ b/ggml/src/ggml-cuda/turbo-wht.cuh @@ -0,0 +1,5 @@ +#pragma once + +#include "common.cuh" + +void ggml_cuda_turbo_wht(ggml_backend_cuda_context & ctx, ggml_tensor * dst); diff --git a/ggml/src/ggml-cuda/vendors/hip.h b/ggml/src/ggml-cuda/vendors/hip.h index 9d9ba1ee219..792fe27b6c3 100644 --- a/ggml/src/ggml-cuda/vendors/hip.h +++ b/ggml/src/ggml-cuda/vendors/hip.h @@ -28,11 +28,32 @@ #define CU_MEM_LOCATION_TYPE_DEVICE hipMemLocationTypeDevice #define CU_MEM_ACCESS_FLAGS_PROT_READWRITE hipMemAccessFlagsProtReadWrite #define CU_CHECK(fn) {hipError_t err = fn; if(err != hipSuccess) { GGML_ABORT("HipVMM Failure: %s\n", hipGetErrorString(err)); }} -#define __shfl_sync(mask, var, laneMask, width) __shfl(var, laneMask, width) -#define __shfl_up_sync(mask, var, laneMask, width) __shfl_up(var, laneMask, width) -#define __shfl_xor_sync(mask, var, laneMask, width) __shfl_xor(var, laneMask, width) +// __shfl_sync: support both 3-arg (mask, var, srcLane) and 4-arg (mask, var, srcLane, width) calls +// HIP ignores the mask but requires it to be 64-bit, so we cast explicitly. +#define __SHFL_SYNC_3(mask, var, srcLane) __shfl(var, srcLane, warpSize) +#define __SHFL_SYNC_4(mask, var, srcLane, width) __shfl(var, srcLane, width) +#define __SHFL_GET_MACRO(_1, _2, _3, _4, NAME, ...) NAME +#define __shfl_sync(...) __SHFL_GET_MACRO(__VA_ARGS__, __SHFL_SYNC_4, __SHFL_SYNC_3)(__VA_ARGS__) +// __shfl_up_sync: support 3-arg and 4-arg calls (HIP ignores mask) +#define __SHFL_UP_SYNC_3(mask, var, delta) __shfl_up(var, delta, warpSize) +#define __SHFL_UP_SYNC_4(mask, var, delta, width) __shfl_up(var, delta, width) +#define __SHFL_UP_GET(_1, _2, _3, _4, NAME, ...) NAME +#define __shfl_up_sync(...) __SHFL_UP_GET(__VA_ARGS__, __SHFL_UP_SYNC_4, __SHFL_UP_SYNC_3)(__VA_ARGS__) + +// __shfl_xor_sync: support 3-arg and 4-arg calls (HIP ignores mask) +#define __SHFL_XOR_SYNC_3(mask, var, laneMask) __shfl_xor(var, laneMask, warpSize) +#define __SHFL_XOR_SYNC_4(mask, var, laneMask, width) __shfl_xor(var, laneMask, width) +#define __SHFL_XOR_GET(_1, _2, _3, _4, NAME, ...) NAME +#define __shfl_xor_sync(...) __SHFL_XOR_GET(__VA_ARGS__, __SHFL_XOR_SYNC_4, __SHFL_XOR_SYNC_3)(__VA_ARGS__) + +// __shfl_down_sync: support 3-arg and 4-arg calls (HIP ignores mask) +#define __SHFL_DOWN_SYNC_3(mask, var, delta) __shfl_down(var, delta, warpSize) +#define __SHFL_DOWN_SYNC_4(mask, var, delta, width) __shfl_down(var, delta, width) +#define __SHFL_DOWN_GET(_1, _2, _3, _4, NAME, ...) NAME +#define __shfl_down_sync(...) __SHFL_DOWN_GET(__VA_ARGS__, __SHFL_DOWN_SYNC_4, __SHFL_DOWN_SYNC_3)(__VA_ARGS__) #define __all_sync(mask, var) __all(var) #define __any_sync(mask, var) __any(var) +#define __ballot_sync(mask, var) ((uint32_t)__ballot(var)) #define cublasStrsmBatched hipblasStrsmBatched #define cublasCreate hipblasCreate #define cublasDestroy hipblasDestroy @@ -113,6 +134,10 @@ #define cudaStreamPerThread hipStreamPerThread #define cudaStreamSynchronize hipStreamSynchronize #define cudaStreamWaitEvent hipStreamWaitEvent +#define cudaMemcpyToSymbol hipMemcpyToSymbol +#define cudaMemcpyFromSymbol hipMemcpyFromSymbol +#define cudaMemcpyHostToDevice hipMemcpyHostToDevice +#define cudaMemcpyDeviceToHost hipMemcpyDeviceToHost #define cudaGraphExec_t hipGraphExec_t #define cudaGraphNode_t hipGraphNode_t #define cudaKernelNodeParams hipKernelNodeParams @@ -125,6 +150,9 @@ #define cudaGraphNodeTypeKernel hipGraphNodeTypeKernel #define cudaGraphInstantiate hipGraphInstantiate #define cudaStreamEndCapture hipStreamEndCapture +#define cudaStreamCaptureStatus hipStreamCaptureStatus +#define cudaStreamIsCapturing hipStreamIsCapturing +#define cudaStreamCaptureStatusNone hipStreamCaptureStatusNone #define cudaGraphDestroy hipGraphDestroy #define cudaGraphKernelNodeSetParams hipGraphKernelNodeSetParams #define cudaErrorInvalidDeviceFunction hipErrorInvalidDeviceFunction diff --git a/ggml/src/ggml-hip/CMakeLists.txt b/ggml/src/ggml-hip/CMakeLists.txt index 291b4837455..168d69b992a 100644 --- a/ggml/src/ggml-hip/CMakeLists.txt +++ b/ggml/src/ggml-hip/CMakeLists.txt @@ -58,6 +58,8 @@ list(APPEND GGML_HEADERS_ROCM "../../include/ggml-cuda.h") file(GLOB GGML_SOURCES_ROCM "../ggml-cuda/*.cu") file(GLOB SRCS "../ggml-cuda/template-instances/fattn-tile*.cu") +# Exclude D>=576 tile kernels: exceed HIP local memory limit (67584 > 65536) +list(FILTER SRCS EXCLUDE REGEX "dkq(576|640)") list(APPEND GGML_SOURCES_ROCM ${SRCS}) file(GLOB SRCS "../ggml-cuda/template-instances/fattn-mma*.cu") list(APPEND GGML_SOURCES_ROCM ${SRCS}) @@ -75,7 +77,22 @@ else() ../ggml-cuda/template-instances/fattn-vec-instance-f16-f16.cu ../ggml-cuda/template-instances/fattn-vec-instance-q4_0-q4_0.cu ../ggml-cuda/template-instances/fattn-vec-instance-q8_0-q8_0.cu - ../ggml-cuda/template-instances/fattn-vec-instance-bf16-bf16.cu) + ../ggml-cuda/template-instances/fattn-vec-instance-bf16-bf16.cu + ../ggml-cuda/template-instances/fattn-vec-instance-turbo3_0-turbo3_0.cu + ../ggml-cuda/template-instances/fattn-vec-instance-turbo3_0-q8_0.cu + ../ggml-cuda/template-instances/fattn-vec-instance-q8_0-turbo3_0.cu + ../ggml-cuda/template-instances/fattn-vec-instance-turbo2_0-turbo2_0.cu + ../ggml-cuda/template-instances/fattn-vec-instance-turbo2_0-q8_0.cu + ../ggml-cuda/template-instances/fattn-vec-instance-q8_0-turbo2_0.cu + ../ggml-cuda/template-instances/fattn-vec-instance-turbo3_0-turbo2_0.cu + ../ggml-cuda/template-instances/fattn-vec-instance-turbo2_0-turbo3_0.cu + ../ggml-cuda/template-instances/fattn-vec-instance-turbo4_0-turbo4_0.cu + ../ggml-cuda/template-instances/fattn-vec-instance-turbo4_0-q8_0.cu + ../ggml-cuda/template-instances/fattn-vec-instance-q8_0-turbo4_0.cu + ../ggml-cuda/template-instances/fattn-vec-instance-turbo4_0-turbo3_0.cu + ../ggml-cuda/template-instances/fattn-vec-instance-turbo3_0-turbo4_0.cu + ../ggml-cuda/template-instances/fattn-vec-instance-turbo4_0-turbo2_0.cu + ../ggml-cuda/template-instances/fattn-vec-instance-turbo2_0-turbo4_0.cu) endif() ggml_add_backend_library(ggml-hip diff --git a/ggml/src/ggml-metal/ggml-metal-device.cpp b/ggml/src/ggml-metal/ggml-metal-device.cpp index 89539bd7615..b97a9e8234f 100644 --- a/ggml/src/ggml-metal/ggml-metal-device.cpp +++ b/ggml/src/ggml-metal/ggml-metal-device.cpp @@ -646,6 +646,23 @@ ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_solve_tri(ggml_m return res; } +ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_turbo_wht(ggml_metal_library_t lib) { + const char * name = "kernel_turbo_wht"; + + ggml_metal_pipeline_with_params res = ggml_metal_library_get_pipeline(lib, name); + if (!res.pipeline) { + // No function constants needed — compile with empty cv + ggml_metal_cv_t cv = ggml_metal_cv_init(); + res = ggml_metal_library_compile_pipeline(lib, name, name, cv); + ggml_metal_cv_free(cv); + } + + res.nsg = 1; + res.smem = 0; + + return res; +} + ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_mul_mv_ext(ggml_metal_library_t lib, ggml_type tsrc0, ggml_type tsrc1, int nsg, int nxpsg, int r1ptg) { char base[256]; char name[256]; @@ -762,6 +779,18 @@ ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_mul_mv(ggml_meta nr0 = N_R0_Q8_0; smem = 32*sizeof(float)*N_R0_Q8_0; } break; + case GGML_TYPE_TQ3_1S: + { + nsg = N_SG_TQ3_1S; + nr0 = N_R0_TQ3_1S; + smem = 32*sizeof(float)*N_R0_TQ3_1S; + } break; + case GGML_TYPE_TQ4_1S: + { + nsg = N_SG_TQ4_1S; + nr0 = N_R0_TQ4_1S; + smem = 32*sizeof(float)*N_R0_TQ4_1S; + } break; case GGML_TYPE_MXFP4: { nsg = N_SG_MXFP4; @@ -844,6 +873,12 @@ ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_mul_mv(ggml_meta nr0 = N_R0_IQ4_XS; smem = 32*sizeof(float); } break; + case GGML_TYPE_TURBO3_0: + { + nsg = N_SG_TURBO3; + nr0 = N_R0_TURBO3; + smem = 32*sizeof(float)*N_R0_TURBO3; + } break; default: { GGML_LOG_ERROR("Asserting on type %d\n", (int) tsrc0); @@ -873,6 +908,81 @@ ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_mul_mv(ggml_meta return res; } +// TQ3_1S / TQ4_1S rotated variant: uses dequantize_*_rotated (no inverse RHT) +ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_mul_mm_tq_rotated(ggml_metal_library_t lib, const ggml_tensor * op) { + char base[256]; + char name[256]; + + const ggml_type tsrc0 = op->src[0]->type; + const ggml_type tsrc1 = op->src[1]->type; + + const bool bc_inp = op->src[0]->ne[0] % 32 != 0; + const bool bc_out = op->ne[0] % 64 != 0 || op->ne[1] % 32 != 0; + + snprintf(base, 256, "kernel_mul_mm_%s_rotated_%s", ggml_type_name(tsrc0), ggml_type_name(tsrc1)); + snprintf(name, 256, "%s_bci=%d_bco=%d", base, bc_inp, bc_out); + + ggml_metal_pipeline_with_params res = ggml_metal_library_get_pipeline(lib, name); + if (!res.pipeline) { + ggml_metal_cv_t cv = ggml_metal_cv_init(); + + ggml_metal_cv_set_bool(cv, bc_inp, FC_MUL_MM + 0); + ggml_metal_cv_set_bool(cv, bc_out, FC_MUL_MM + 1); + + res = ggml_metal_library_compile_pipeline(lib, base, name, cv); + + ggml_metal_cv_free(cv); + } + + res.smem = bc_out ? 8192 : 4096 + 2048; + + return res; +} + +// TQ3_1S / TQ4_1S rotated MUL_MAT_ID variant +ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_mul_mm_id_tq_rotated(ggml_metal_library_t lib, const ggml_tensor * op) { + char base[256]; + char name[256]; + + const ggml_type tsrc0 = op->src[0]->type; + const ggml_type tsrc1 = op->src[1]->type; + + const bool bc_inp = op->src[0]->ne[0] % 32 != 0; + + snprintf(base, 256, "kernel_mul_mm_id_%s_rotated_%s", ggml_type_name(tsrc0), ggml_type_name(tsrc1)); + snprintf(name, 256, "%s_bci=%d", base, bc_inp); + + ggml_metal_pipeline_with_params res = ggml_metal_library_get_pipeline(lib, name); + if (!res.pipeline) { + ggml_metal_cv_t cv = ggml_metal_cv_init(); + + ggml_metal_cv_set_bool(cv, bc_inp, FC_MUL_MM + 0); + + res = ggml_metal_library_compile_pipeline(lib, base, name, cv); + + ggml_metal_cv_free(cv); + } + + res.smem = 8192; + + return res; +} + +// TQ3_1S / TQ4_1S activation pre-rotation pipeline (shared by both) +ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_tq3_rotate_act(ggml_metal_library_t lib, bool inverse) { + char name[256]; + const char * base = inverse ? "kernel_tq3_unrotate_act" : "kernel_tq3_rotate_act"; + + snprintf(name, 256, "%s", base); + + ggml_metal_pipeline_with_params res = ggml_metal_library_get_pipeline(lib, name); + if (!res.pipeline) { + res = ggml_metal_library_compile_pipeline(lib, base, name, nullptr); + } + + return res; +} + ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_mul_mm_id_map0(ggml_metal_library_t lib, int ne02, int ne20) { char base[256]; char name[256]; @@ -974,6 +1084,18 @@ ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_mul_mv_id(ggml_m nr0 = N_R0_Q8_0; smem = 32*sizeof(float)*N_R0_Q8_0; } break; + case GGML_TYPE_TQ3_1S: + { + nsg = N_SG_TQ3_1S; + nr0 = N_R0_TQ3_1S; + smem = 32*sizeof(float)*N_R0_TQ3_1S; + } break; + case GGML_TYPE_TQ4_1S: + { + nsg = N_SG_TQ4_1S; + nr0 = N_R0_TQ4_1S; + smem = 32*sizeof(float)*N_R0_TQ4_1S; + } break; case GGML_TYPE_MXFP4: { nsg = N_SG_MXFP4; @@ -1056,6 +1178,12 @@ ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_mul_mv_id(ggml_m nr0 = N_R0_IQ4_XS; smem = 32*sizeof(float); } break; + case GGML_TYPE_TURBO3_0: + { + nsg = N_SG_TURBO3; + nr0 = N_R0_TURBO3; + smem = 32*sizeof(float)*N_R0_TURBO3; + } break; default: { GGML_LOG_ERROR("Asserting on type %d\n", (int)op->src[2]->type); @@ -1321,12 +1449,17 @@ ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_flash_attn_ext( // do bounds checks for the mask? const bool bc_mask = op->src[3] && (op->src[3]->ne[1] % 8 != 0); - snprintf(base, 256, "kernel_%s_%s_dk%d_dv%d", + // Asymmetric K/V: always encode both K and V types in the pipeline name. + // Symmetric case: ktype == vtype, so the name just has the type twice. + // This avoids ambiguity if a type name contains underscores (e.g. q4_0). + snprintf(base, 256, "kernel_%s_k%s_v%s_dk%d_dv%d", "flash_attn_ext", ggml_type_name(op->src[1]->type), + ggml_type_name(op->src[2]->type), dk, dv); + snprintf(name, 256, "%s_mask=%d_sinks=%d_bias=%d_scap=%d_kvpad=%d_bcm=%d_ns10=%d_ns20=%d_nsg=%d", base, has_mask, @@ -1384,12 +1517,16 @@ ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_flash_attn_ext_v const int32_t ns10 = op->src[1]->nb[1]/op->src[1]->nb[0]; const int32_t ns20 = op->src[2]->nb[1]/op->src[2]->nb[0]; - snprintf(base, 256, "kernel_%s_%s_dk%d_dv%d", + // Asymmetric K/V: always encode both K and V types in the pipeline name. + // Uses k/v prefix to avoid ambiguity with type names containing underscores. + snprintf(base, 256, "kernel_%s_k%s_v%s_dk%d_dv%d", "flash_attn_ext_vec", ggml_type_name(op->src[1]->type), + ggml_type_name(op->src[2]->type), dk, dv); + snprintf(name, 256, "%s_mask=%d_sink=%d_bias=%d_scap=%d_kvpad=%d_ns10=%d_ns20=%d_nsg=%d_nwg=%d", base, has_mask, diff --git a/ggml/src/ggml-metal/ggml-metal-device.h b/ggml/src/ggml-metal/ggml-metal-device.h index de43f819312..db4f4624a70 100644 --- a/ggml/src/ggml-metal/ggml-metal-device.h +++ b/ggml/src/ggml-metal/ggml-metal-device.h @@ -127,8 +127,12 @@ struct ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_ssm_scan struct ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_rwkv (ggml_metal_library_t lib, const struct ggml_tensor * op); struct ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_gated_delta_net (ggml_metal_library_t lib, const struct ggml_tensor * op); struct ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_solve_tri (ggml_metal_library_t lib, const struct ggml_tensor * op); +struct ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_turbo_wht (ggml_metal_library_t lib); struct ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_mul_mv_ext (ggml_metal_library_t lib, enum ggml_type tsrc0, enum ggml_type tsrc1, int nsg, int nxpsg, int r1ptg); struct ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_mul_mm (ggml_metal_library_t lib, const struct ggml_tensor * op); +struct ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_mul_mm_tq_rotated(ggml_metal_library_t lib, const struct ggml_tensor * op); +struct ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_mul_mm_id_tq_rotated(ggml_metal_library_t lib, const struct ggml_tensor * op); +struct ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_tq3_rotate_act (ggml_metal_library_t lib, bool inverse); struct ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_mul_mv (ggml_metal_library_t lib, const struct ggml_tensor * op); struct ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_mul_mm_id_map0 (ggml_metal_library_t lib, int ne02, int ne20); struct ggml_metal_pipeline_with_params ggml_metal_library_get_pipeline_mul_mm_id (ggml_metal_library_t lib, const struct ggml_tensor * op); diff --git a/ggml/src/ggml-metal/ggml-metal-device.m b/ggml/src/ggml-metal/ggml-metal-device.m index 17d51b11b6e..9c2fb1cb82f 100644 --- a/ggml/src/ggml-metal/ggml-metal-device.m +++ b/ggml/src/ggml-metal/ggml-metal-device.m @@ -224,6 +224,43 @@ ggml_metal_library_t ggml_metal_library_init(ggml_metal_device_t dev) { [prep setObject:@"1" forKey:@"GGML_METAL_EMBED_LIBRARY"]; #endif + // TurboQuant: auto-select dequant path based on hardware + // M1/M2/M3/M4 (no tensor API): 4-mag LUT (+38-45% decode at long ctx) + // M5+ (has tensor API): 8-entry full LUT (best decode speed) + { + const char * force_4mag = getenv("TURBO_FORCE_4MAG"); + // Always compile with 4-mag support. The dispatch code selects + // 4-mag vs 8-LUT based on context depth at runtime. + // Pre-M5: always 4-mag (constant cache too slow) + // M5+: 4-mag for mid-context (8K-20K), 8-LUT otherwise + if (!ggml_metal_device_get_props(dev)->has_tensor || (force_4mag && force_4mag[0] == '1')) { + [prep setObject:@"1" forKey:@"TURBO_USE_4MAG"]; + GGML_LOG_INFO("%s: turbo3 using 4-mag LUT%s\n", __func__, + force_4mag ? " (forced)" : " (pre-M5 hardware)"); + } + // Sparse V dequant: skip V for negligible attention weights + // Enabled by default on all Metal (validated: PPL identical, NIAH 9/9, 30+ testers) + // Opt-out via TURBO_SPARSE_V=0 + const char * sparse_v_env = getenv("TURBO_SPARSE_V"); + const bool sparse_v_disabled = sparse_v_env && sparse_v_env[0] == '0'; + if (!sparse_v_disabled) { + [prep setObject:@"1" forKey:@"TURBO_SPARSE_V"]; + GGML_LOG_INFO("%s: turbo3 sparse V dequant enabled (opt-out: TURBO_SPARSE_V=0)\n", __func__); + } + // TODO: context-adaptive dispatch — compile both 4-mag and 8-LUT + // FA kernel instantiations, select based on ne11 (KV cache size) + // at dispatch time in ggml_metal_op_flash_attn_ext() + } + + // TurboQuant profiling: set TURBO_PROFILE_MODE env var (0-4) + { + const char * pm = getenv("TURBO_PROFILE_MODE"); + if (pm && pm[0] >= '0' && pm[0] <= '4') { + [prep setObject:[NSString stringWithUTF8String:pm] forKey:@"TURBO_PROFILE_MODE"]; + GGML_LOG_INFO("%s: TURBO_PROFILE_MODE=%s\n", __func__, pm); + } + } + MTLCompileOptions * options = [MTLCompileOptions new]; options.preprocessorMacros = prep; @@ -1157,7 +1194,23 @@ bool ggml_metal_device_supports_op(ggml_metal_device_t dev, const struct ggml_te return false; } if (op->src[1]->type != op->src[2]->type) { - return false; + // Allow asymmetric K/V for supported mixed pairs: + // - turbo x turbo (any combination) + // - q8_0 x turbo (either direction) + const bool k_is_turbo = (op->src[1]->type == GGML_TYPE_TURBO2_0 || + op->src[1]->type == GGML_TYPE_TURBO3_0 || + op->src[1]->type == GGML_TYPE_TURBO4_0); + const bool v_is_turbo = (op->src[2]->type == GGML_TYPE_TURBO2_0 || + op->src[2]->type == GGML_TYPE_TURBO3_0 || + op->src[2]->type == GGML_TYPE_TURBO4_0); + const bool k_is_q8 = (op->src[1]->type == GGML_TYPE_Q8_0); + const bool v_is_q8 = (op->src[2]->type == GGML_TYPE_Q8_0); + const bool supported = (k_is_turbo && v_is_turbo) || + (k_is_q8 && v_is_turbo) || + (k_is_turbo && v_is_q8); + if (!supported) { + return false; + } } return has_simdgroup_mm; // TODO: over-restricted for vec-kernels case GGML_OP_SSM_CONV: @@ -1168,10 +1221,14 @@ bool ggml_metal_device_supports_op(ggml_metal_device_t dev, const struct ggml_te return true; case GGML_OP_GATED_DELTA_NET: return has_simdgroup_reduction && op->src[2]->ne[0] % 32 == 0; + case GGML_OP_TURBO_WHT: + return op->src[0]->ne[0] % 128 == 0; case GGML_OP_SOLVE_TRI: case GGML_OP_MUL_MAT: case GGML_OP_MUL_MAT_ID: - return has_simdgroup_reduction && op->src[0]->type != GGML_TYPE_NVFP4; + return has_simdgroup_reduction && + op->src[0]->type != GGML_TYPE_NVFP4 && + op->src[0]->type != GGML_TYPE_TURBO4_0; case GGML_OP_SET: case GGML_OP_CPY: case GGML_OP_DUP: @@ -1215,6 +1272,8 @@ bool ggml_metal_device_supports_op(ggml_metal_device_t dev, const struct ggml_te case GGML_TYPE_Q5_0: case GGML_TYPE_Q5_1: case GGML_TYPE_Q8_0: + case GGML_TYPE_TQ3_1S: + case GGML_TYPE_TQ4_1S: switch (op->type) { case GGML_TYPE_F32: case GGML_TYPE_F16: @@ -1229,7 +1288,9 @@ bool ggml_metal_device_supports_op(ggml_metal_device_t dev, const struct ggml_te }; } case GGML_OP_GET_ROWS: - return op->src[0]->type != GGML_TYPE_NVFP4; + return op->src[0]->type != GGML_TYPE_NVFP4 && + op->src[0]->type != GGML_TYPE_TURBO3_0 && + op->src[0]->type != GGML_TYPE_TURBO4_0; case GGML_OP_SET_ROWS: { if (op->src[0]->type != GGML_TYPE_F32) { @@ -1246,6 +1307,9 @@ bool ggml_metal_device_supports_op(ggml_metal_device_t dev, const struct ggml_te case GGML_TYPE_Q5_0: case GGML_TYPE_Q5_1: case GGML_TYPE_IQ4_NL: + case GGML_TYPE_TURBO2_0: + case GGML_TYPE_TURBO3_0: + case GGML_TYPE_TURBO4_0: return true; default: return false; diff --git a/ggml/src/ggml-metal/ggml-metal-impl.h b/ggml/src/ggml-metal/ggml-metal-impl.h index eb2253e029a..7766add31c1 100644 --- a/ggml/src/ggml-metal/ggml-metal-impl.h +++ b/ggml/src/ggml-metal/ggml-metal-impl.h @@ -68,6 +68,15 @@ #define N_R0_IQ4_XS 2 #define N_SG_IQ4_XS 2 +#define N_R0_TURBO3 2 +#define N_SG_TURBO3 2 + +#define N_R0_TQ3_1S 8 +#define N_SG_TQ3_1S 2 + +#define N_R0_TQ4_1S 8 +#define N_SG_TQ4_1S 2 + // function constants offsets #define FC_FLASH_ATTN_EXT_PAD 100 #define FC_FLASH_ATTN_EXT_BLK 200 @@ -85,6 +94,7 @@ #define FC_SUM_ROWS 1400 #define FC_UPSCALE 1500 #define FC_GATED_DELTA_NET 1600 +#define FC_TURBO_WHT 1700 // op-specific constants #define OP_FLASH_ATTN_EXT_NQPSG 8 @@ -872,6 +882,11 @@ typedef struct { uint64_t nb3; } ggml_metal_kargs_gated_delta_net; +typedef struct { + int64_t n_elements; // total elements in tensor + int32_t direction; // 0 = forward, 1 = inverse +} ggml_metal_kargs_turbo_wht; + typedef struct { int32_t ne00; int32_t ne01; diff --git a/ggml/src/ggml-metal/ggml-metal-ops.cpp b/ggml/src/ggml-metal/ggml-metal-ops.cpp index 3cda21be43e..8bf628a2808 100644 --- a/ggml/src/ggml-metal/ggml-metal-ops.cpp +++ b/ggml/src/ggml-metal/ggml-metal-ops.cpp @@ -337,6 +337,10 @@ static int ggml_metal_op_encode_impl(ggml_metal_op_t ctx, int idx) { { n_fuse = ggml_metal_op_gated_delta_net(ctx, idx); } break; + case GGML_OP_TURBO_WHT: + { + n_fuse = ggml_metal_op_turbo_wht(ctx, idx); + } break; case GGML_OP_SOLVE_TRI: { n_fuse = ggml_metal_op_solve_tri(ctx, idx); @@ -1645,6 +1649,39 @@ int ggml_metal_op_gated_delta_net(ggml_metal_op_t ctx, int idx) { return 1; } +int ggml_metal_op_turbo_wht(ggml_metal_op_t ctx, int idx) { + ggml_tensor * op = ctx->node(idx); + + ggml_metal_library_t lib = ctx->lib; + ggml_metal_encoder_t enc = ctx->enc; + + int direction; + memcpy(&direction, op->op_params, sizeof(int)); + + const int64_t n_elements = ggml_nelements(op->src[0]); + const int64_t n_groups = n_elements / 128; + + auto pipeline = ggml_metal_library_get_pipeline_turbo_wht(lib); + + ggml_metal_kargs_turbo_wht args = { + /*.n_elements =*/ n_elements, + /*.direction =*/ direction, + }; + + int ida = 0; + ggml_metal_encoder_set_pipeline(enc, pipeline); + ggml_metal_encoder_set_bytes (enc, &args, sizeof(args), ida++); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[0]), ida++); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op), ida++); + + // One thread per 128-element group, 256 threads per threadgroup + const int threads_per_tg = 256; + const int n_threadgroups = (n_groups + threads_per_tg - 1) / threads_per_tg; + ggml_metal_encoder_dispatch_threadgroups(enc, n_threadgroups, 1, 1, threads_per_tg, 1, 1); + + return 1; +} + int ggml_metal_op_solve_tri(ggml_metal_op_t ctx, int idx) { ggml_tensor * op = ctx->node(idx); @@ -2054,6 +2091,9 @@ int ggml_metal_op_mul_mat(ggml_metal_op_t ctx, int idx) { op->src[0]->type == GGML_TYPE_Q8_0 || op->src[0]->type == GGML_TYPE_MXFP4 || op->src[0]->type == GGML_TYPE_IQ4_NL || + op->src[0]->type == GGML_TYPE_TURBO3_0 || + op->src[0]->type == GGML_TYPE_TQ3_1S || + op->src[0]->type == GGML_TYPE_TQ4_1S || false) && (ne11 >= 2 && ne11 <= 8) ) || ( @@ -2143,47 +2183,102 @@ int ggml_metal_op_mul_mat(ggml_metal_op_t ctx, int idx) { !ggml_is_transposed(op->src[1]) && // for now the matrix-matrix multiplication kernel only works on A14+/M1+ SoCs // AMD GPU and older A-chips will reuse matrix-vector multiplication kernel - props_dev->has_simdgroup_mm && ne00 >= 64 && ne11 > ne11_mm_min) { - //GGML_LOG_INFO("matrix: ne00 = %6d, ne01 = %6d, ne02 = %6d, ne11 = %6d, ne12 = %6d\n", ne00, ne01, ne02, ne11, ne12); + props_dev->has_simdgroup_mm && ne00 >= 64 && + (ne11 > ne11_mm_min || ((op->src[0]->type == GGML_TYPE_TQ3_1S || op->src[0]->type == GGML_TYPE_TQ4_1S) && ne11 > 1))) { + // TQ3_1S/TQ4_1S with ne11=1 uses specialized V2.1 fused mul_mv kernel - // some Metal matrix data types require aligned pointers - // ref: https://developer.apple.com/metal/Metal-Shading-Language-Specification.pdf (Table 2.5) - //switch (op->src[0]->type) { - // case GGML_TYPE_F32: GGML_ASSERT(nb01 % 16 == 0); break; - // case GGML_TYPE_F16: GGML_ASSERT(nb01 % 8 == 0); break; - // case GGML_TYPE_BF16: GGML_ASSERT(nb01 % 8 == 0); break; - // default: break; - //} + const bool is_tq_weight = (op->src[0]->type == GGML_TYPE_TQ3_1S || op->src[0]->type == GGML_TYPE_TQ4_1S); - auto pipeline = ggml_metal_library_get_pipeline_mul_mm(lib, op); + // TQ weight optimization: pre-rotate activations, use no-RHT dequant, then un-rotate + if (is_tq_weight && ne00 % 32 == 0) { + // Step 1: Forward-rotate src1 in-place + const int64_t n_act = (int64_t)ne10 * ne11 * ne12 * ne13; + int64_t n_act_val = n_act; - ggml_metal_kargs_mul_mm args = { - /*.ne00 =*/ ne00, - /*.ne02 =*/ ne02, - /*.nb01 =*/ nb01, - /*.nb02 =*/ nb02, - /*.nb03 =*/ nb03, - /*.ne12 =*/ ne12, - /*.nb10 =*/ nb10, - /*.nb11 =*/ nb11, - /*.nb12 =*/ nb12, - /*.nb13 =*/ nb13, - /*.ne0 =*/ ne0, - /*.ne1 =*/ ne1, - /*.r2 =*/ r2, - /*.r3 =*/ r3, - }; + auto pipeline_rot = ggml_metal_library_get_pipeline_tq3_rotate_act(lib, false); + ggml_metal_encoder_set_pipeline(enc, pipeline_rot); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[1]), 0); + ggml_metal_encoder_set_bytes (enc, &n_act_val, sizeof(n_act_val), 1); + ggml_metal_encoder_dispatch_threadgroups(enc, (int)(n_act_val / 32), 1, 1, 32, 1, 1); - ggml_metal_encoder_set_pipeline(enc, pipeline); - ggml_metal_encoder_set_bytes (enc, &args, sizeof(args), 0); - ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[0]), 1); - ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[1]), 2); - ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op), 3); + // Memory barrier between rotate and matmul + ggml_metal_op_concurrency_reset(ctx); - const size_t smem = pipeline.smem; + // Step 2: Dispatch rotated mul_mm (uses no-RHT dequant) + auto pipeline_mm = ggml_metal_library_get_pipeline_mul_mm_tq_rotated(lib, op); - ggml_metal_encoder_set_threadgroup_memory_size(enc, smem, 0); - ggml_metal_encoder_dispatch_threadgroups(enc, ((ne11 + 31)/32), ((ne01 + 63)/64), ne12*ne13, 128, 1, 1); + ggml_metal_kargs_mul_mm args = { + /*.ne00 =*/ ne00, + /*.ne02 =*/ ne02, + /*.nb01 =*/ nb01, + /*.nb02 =*/ nb02, + /*.nb03 =*/ nb03, + /*.ne12 =*/ ne12, + /*.nb10 =*/ nb10, + /*.nb11 =*/ nb11, + /*.nb12 =*/ nb12, + /*.nb13 =*/ nb13, + /*.ne0 =*/ ne0, + /*.ne1 =*/ ne1, + /*.r2 =*/ r2, + /*.r3 =*/ r3, + }; + + ggml_metal_encoder_set_pipeline(enc, pipeline_mm); + ggml_metal_encoder_set_bytes (enc, &args, sizeof(args), 0); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[0]), 1); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[1]), 2); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op), 3); + + const size_t smem = pipeline_mm.smem; + ggml_metal_encoder_set_threadgroup_memory_size(enc, smem, 0); + ggml_metal_encoder_dispatch_threadgroups(enc, ((ne11 + 31)/32), ((ne01 + 63)/64), ne12*ne13, 128, 1, 1); + + // Memory barrier between matmul and unrotate + ggml_metal_op_concurrency_reset(ctx); + + // Step 3: Inverse-rotate src1 to restore original values + auto pipeline_unrot = ggml_metal_library_get_pipeline_tq3_rotate_act(lib, true); + ggml_metal_encoder_set_pipeline(enc, pipeline_unrot); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[1]), 0); + ggml_metal_encoder_set_bytes (enc, &n_act_val, sizeof(n_act_val), 1); + ggml_metal_encoder_dispatch_threadgroups(enc, (int)(n_act_val / 32), 1, 1, 32, 1, 1); + + // Barrier: ensure unrotate completes before any subsequent op reads src1 + // Without this, mixing TQ and non-TQ tensors in the same layer corrupts src1 + ggml_metal_op_concurrency_reset(ctx); + } else { + // Non-TQ weight or unaligned: use standard mul_mm path + auto pipeline = ggml_metal_library_get_pipeline_mul_mm(lib, op); + + ggml_metal_kargs_mul_mm args = { + /*.ne00 =*/ ne00, + /*.ne02 =*/ ne02, + /*.nb01 =*/ nb01, + /*.nb02 =*/ nb02, + /*.nb03 =*/ nb03, + /*.ne12 =*/ ne12, + /*.nb10 =*/ nb10, + /*.nb11 =*/ nb11, + /*.nb12 =*/ nb12, + /*.nb13 =*/ nb13, + /*.ne0 =*/ ne0, + /*.ne1 =*/ ne1, + /*.r2 =*/ r2, + /*.r3 =*/ r3, + }; + + ggml_metal_encoder_set_pipeline(enc, pipeline); + ggml_metal_encoder_set_bytes (enc, &args, sizeof(args), 0); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[0]), 1); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[1]), 2); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op), 3); + + const size_t smem = pipeline.smem; + + ggml_metal_encoder_set_threadgroup_memory_size(enc, smem, 0); + ggml_metal_encoder_dispatch_threadgroups(enc, ((ne11 + 31)/32), ((ne01 + 63)/64), ne12*ne13, 128, 1, 1); + } } else { auto pipeline = ggml_metal_library_get_pipeline_mul_mv(lib, op); @@ -2226,7 +2321,9 @@ int ggml_metal_op_mul_mat(ggml_metal_op_t ctx, int idx) { if (op->src[0]->type == GGML_TYPE_F32 || op->src[0]->type == GGML_TYPE_F16 || op->src[0]->type == GGML_TYPE_BF16 || - op->src[0]->type == GGML_TYPE_Q8_0) { + op->src[0]->type == GGML_TYPE_Q8_0 || + op->src[0]->type == GGML_TYPE_TQ3_1S || + op->src[0]->type == GGML_TYPE_TQ4_1S) { ggml_metal_encoder_dispatch_threadgroups(enc, ((ne01 + nr0 - 1)/(nr0)), ((ne11 + nr1 - 1)/nr1), ne12*ne13, 32, nsg, 1); } else { ggml_metal_encoder_dispatch_threadgroups(enc, ((ne01 + nr0*nsg - 1)/(nr0*nsg)), ((ne11 + nr1 - 1)/nr1), ne12*ne13, 32, nsg, 1); @@ -2345,40 +2442,98 @@ int ggml_metal_op_mul_mat_id(ggml_metal_op_t ctx, int idx) { ggml_metal_op_concurrency_reset(ctx); { - auto pipeline = ggml_metal_library_get_pipeline_mul_mm_id(lib, op); - - ggml_metal_kargs_mul_mm_id args = { - /*.ne00 =*/ ne00, - /*.ne02 =*/ ne02, - /*.nb01 =*/ nb01, - /*.nb02 =*/ nb02, - /*.nb03 =*/ nb03, - /*.ne11 =*/ ne11, // n_expert_used (bcast) - /*.nb10 =*/ nb10, - /*.nb11 =*/ nb11, - /*.nb12 =*/ nb12, - /*.nb13 =*/ nb13, - /*.ne20 =*/ ne20, // n_expert_used - /*.ne21 =*/ ne21, // n_tokens - /*.ne0 =*/ ne0, - /*.ne1 =*/ ne1, - /*.r2 =*/ r2, - /*.r3 =*/ r3, - }; + const bool is_tq_weight = (op->src[0]->type == GGML_TYPE_TQ3_1S || op->src[0]->type == GGML_TYPE_TQ4_1S); - ggml_metal_encoder_set_pipeline(enc, pipeline); - ggml_metal_encoder_set_bytes (enc, &args, sizeof(args), 0); - ggml_metal_encoder_set_buffer (enc, bid_src0, 1); - ggml_metal_encoder_set_buffer (enc, bid_src1, 2); - ggml_metal_encoder_set_buffer (enc, bid_tpe, 3); - ggml_metal_encoder_set_buffer (enc, bid_ids, 4); - ggml_metal_encoder_set_buffer (enc, bid_dst, 5); + // TQ weight MoE: pre-rotate activations for rotated dispatch + if (is_tq_weight && ne00 % 32 == 0) { + const int64_t n_act = (int64_t)ne10 * ne11 * ne12 * ne13; + int64_t n_act_val = n_act; - const size_t smem = pipeline.smem; + auto pipeline_rot = ggml_metal_library_get_pipeline_tq3_rotate_act(lib, false); + ggml_metal_encoder_set_pipeline(enc, pipeline_rot); + ggml_metal_encoder_set_buffer (enc, bid_src1, 0); + ggml_metal_encoder_set_bytes (enc, &n_act_val, sizeof(n_act_val), 1); + ggml_metal_encoder_dispatch_threadgroups(enc, (int)(n_act_val / 32), 1, 1, 32, 1, 1); - ggml_metal_encoder_set_threadgroup_memory_size(enc, smem, 0); + ggml_metal_op_concurrency_reset(ctx); + + auto pipeline = ggml_metal_library_get_pipeline_mul_mm_id_tq_rotated(lib, op); + + ggml_metal_kargs_mul_mm_id args = { + /*.ne00 =*/ ne00, + /*.ne02 =*/ ne02, + /*.nb01 =*/ nb01, + /*.nb02 =*/ nb02, + /*.nb03 =*/ nb03, + /*.ne11 =*/ ne11, + /*.nb10 =*/ nb10, + /*.nb11 =*/ nb11, + /*.nb12 =*/ nb12, + /*.nb13 =*/ nb13, + /*.ne20 =*/ ne20, + /*.ne21 =*/ ne21, + /*.ne0 =*/ ne0, + /*.ne1 =*/ ne1, + /*.r2 =*/ r2, + /*.r3 =*/ r3, + }; + + ggml_metal_encoder_set_pipeline(enc, pipeline); + ggml_metal_encoder_set_bytes (enc, &args, sizeof(args), 0); + ggml_metal_encoder_set_buffer (enc, bid_src0, 1); + ggml_metal_encoder_set_buffer (enc, bid_src1, 2); + ggml_metal_encoder_set_buffer (enc, bid_tpe, 3); + ggml_metal_encoder_set_buffer (enc, bid_ids, 4); + ggml_metal_encoder_set_buffer (enc, bid_dst, 5); + + const size_t smem = pipeline.smem; + ggml_metal_encoder_set_threadgroup_memory_size(enc, smem, 0); + ggml_metal_encoder_dispatch_threadgroups(enc, (ne21 + 31)/32, (ne01 + 63)/64, ne02, 128, 1, 1); - ggml_metal_encoder_dispatch_threadgroups(enc, (ne21 + 31)/32, (ne01 + 63)/64, ne02, 128, 1, 1); + ggml_metal_op_concurrency_reset(ctx); + + auto pipeline_unrot = ggml_metal_library_get_pipeline_tq3_rotate_act(lib, true); + ggml_metal_encoder_set_pipeline(enc, pipeline_unrot); + ggml_metal_encoder_set_buffer (enc, bid_src1, 0); + ggml_metal_encoder_set_bytes (enc, &n_act_val, sizeof(n_act_val), 1); + ggml_metal_encoder_dispatch_threadgroups(enc, (int)(n_act_val / 32), 1, 1, 32, 1, 1); + + // Barrier: ensure unrotate completes before any subsequent op reads src1 + ggml_metal_op_concurrency_reset(ctx); + } else { + auto pipeline = ggml_metal_library_get_pipeline_mul_mm_id(lib, op); + + ggml_metal_kargs_mul_mm_id args = { + /*.ne00 =*/ ne00, + /*.ne02 =*/ ne02, + /*.nb01 =*/ nb01, + /*.nb02 =*/ nb02, + /*.nb03 =*/ nb03, + /*.ne11 =*/ ne11, + /*.nb10 =*/ nb10, + /*.nb11 =*/ nb11, + /*.nb12 =*/ nb12, + /*.nb13 =*/ nb13, + /*.ne20 =*/ ne20, + /*.ne21 =*/ ne21, + /*.ne0 =*/ ne0, + /*.ne1 =*/ ne1, + /*.r2 =*/ r2, + /*.r3 =*/ r3, + }; + + ggml_metal_encoder_set_pipeline(enc, pipeline); + ggml_metal_encoder_set_bytes (enc, &args, sizeof(args), 0); + ggml_metal_encoder_set_buffer (enc, bid_src0, 1); + ggml_metal_encoder_set_buffer (enc, bid_src1, 2); + ggml_metal_encoder_set_buffer (enc, bid_tpe, 3); + ggml_metal_encoder_set_buffer (enc, bid_ids, 4); + ggml_metal_encoder_set_buffer (enc, bid_dst, 5); + + const size_t smem = pipeline.smem; + ggml_metal_encoder_set_threadgroup_memory_size(enc, smem, 0); + ggml_metal_encoder_dispatch_threadgroups(enc, (ne21 + 31)/32, (ne01 + 63)/64, ne02, 128, 1, 1); + } } } else { auto pipeline = ggml_metal_library_get_pipeline_mul_mv_id(lib, op); @@ -2431,7 +2586,9 @@ int ggml_metal_op_mul_mat_id(ggml_metal_op_t ctx, int idx) { if (op->src[0]->type == GGML_TYPE_F32 || op->src[0]->type == GGML_TYPE_F16 || op->src[0]->type == GGML_TYPE_BF16 || - op->src[0]->type == GGML_TYPE_Q8_0) { + op->src[0]->type == GGML_TYPE_Q8_0 || + op->src[0]->type == GGML_TYPE_TQ3_1S || + op->src[0]->type == GGML_TYPE_TQ4_1S) { ggml_metal_encoder_dispatch_threadgroups(enc, (ne01 + nr0 - 1)/(nr0), (_ne1 + nr1 - 1)/nr1, ne123, 32, nsg, 1); } else { ggml_metal_encoder_dispatch_threadgroups(enc, (ne01 + nr0*nsg - 1)/(nr0*nsg), (_ne1 + nr1 - 1)/nr1, ne123, 32, nsg, 1); @@ -2494,6 +2651,17 @@ bool ggml_metal_op_flash_attn_ext_use_vec(const ggml_tensor * op) { const int64_t ne01 = op->src[0]->ne[1]; // batch size // use vec kernel if the batch size is small and if the head size is supported + // EXPERIMENT: force non-vec for turbo3 on pre-M5 hardware. + // The vec kernel uses nl=8 (4 elements per dequant call) which has 4x more + // loop iterations than the non-vec nl=2 path. On M2 Pro, this loop overhead + // dominates — the non-vec path may be faster even for batch=1. + const ggml_type ktype = op->src[1]->type; + if (ktype == GGML_TYPE_TURBO2_0 || ktype == GGML_TYPE_TURBO3_0 || ktype == GGML_TYPE_TURBO4_0) { + const char * force_nonvec = getenv("TURBO_FORCE_NONVEC"); + if (force_nonvec && force_nonvec[0] == '1') { + return false; // force non-vec path + } + } return (ne01 < 20) && (ne00 % 32 == 0); } @@ -2633,7 +2801,22 @@ int ggml_metal_op_flash_attn_ext(ggml_metal_op_t ctx, int idx) { GGML_ASSERT(ne00 % 4 == 0); GGML_ASSERT(op->src[0]->type == GGML_TYPE_F32); - GGML_ASSERT(op->src[1]->type == op->src[2]->type); + + // Allow asymmetric K/V quantization for supported mixed pairs + { + const ggml_type type_k = op->src[1]->type; + const ggml_type type_v = op->src[2]->type; + if (type_k != type_v) { + const bool k_is_turbo = (type_k == GGML_TYPE_TURBO2_0 || type_k == GGML_TYPE_TURBO3_0 || type_k == GGML_TYPE_TURBO4_0); + const bool v_is_turbo = (type_v == GGML_TYPE_TURBO2_0 || type_v == GGML_TYPE_TURBO3_0 || type_v == GGML_TYPE_TURBO4_0); + const bool k_is_q8 = (type_k == GGML_TYPE_Q8_0); + const bool v_is_q8 = (type_v == GGML_TYPE_Q8_0); + const bool supported = (k_is_turbo && v_is_turbo) || + (k_is_q8 && v_is_turbo) || + (k_is_turbo && v_is_q8); + GGML_ASSERT(supported && "asymmetric K/V types only supported for turbo and q8_0 mixed pairs"); + } + } //GGML_ASSERT(ggml_are_same_shape (src1, src2)); GGML_ASSERT(ne11 == ne21); @@ -2918,7 +3101,8 @@ int ggml_metal_op_flash_attn_ext(ggml_metal_op_t ctx, int idx) { // ne20*(nsg) // each simdgroup has a full f32 head vector in shared mem to accumulate results // -#define FATTN_SMEM(nsg) (GGML_PAD(((GGML_PAD(ne00, 128) + 4*ncpsg + 2*GGML_PAD(ne20, 128))*(nsg))*(sizeof(float)/2), 16)) +// Extra 128 floats (512 bytes) for TurboQuant pre-dequantized block cache in threadgroup memory +#define FATTN_SMEM(nsg) (GGML_PAD(((GGML_PAD(ne00, 128) + 4*ncpsg + 2*GGML_PAD(ne20, 128))*(nsg))*(sizeof(float)/2) + 128*sizeof(float), 16)) int64_t nsg = 1; diff --git a/ggml/src/ggml-metal/ggml-metal-ops.h b/ggml/src/ggml-metal/ggml-metal-ops.h index 50e3c5c77a1..1b5f7319b92 100644 --- a/ggml/src/ggml-metal/ggml-metal-ops.h +++ b/ggml/src/ggml-metal/ggml-metal-ops.h @@ -59,6 +59,7 @@ int ggml_metal_op_ssm_conv (ggml_metal_op_t ctx, int idx); int ggml_metal_op_ssm_scan (ggml_metal_op_t ctx, int idx); int ggml_metal_op_rwkv (ggml_metal_op_t ctx, int idx); int ggml_metal_op_gated_delta_net (ggml_metal_op_t ctx, int idx); +int ggml_metal_op_turbo_wht (ggml_metal_op_t ctx, int idx); int ggml_metal_op_solve_tri (ggml_metal_op_t ctx, int idx); int ggml_metal_op_set (ggml_metal_op_t ctx, int idx); int ggml_metal_op_cpy (ggml_metal_op_t ctx, int idx); diff --git a/ggml/src/ggml-metal/ggml-metal.metal b/ggml/src/ggml-metal/ggml-metal.metal index 2074211594c..887c2750f2d 100644 --- a/ggml/src/ggml-metal/ggml-metal.metal +++ b/ggml/src/ggml-metal/ggml-metal.metal @@ -345,6 +345,975 @@ void quantize_iq4_nl(device const float * src, device block_iq4_nl & dst) { dst.d = sumq2 > 0 ? sumqx/sumq2 : d; } +// ----- TurboQuant quantize/dequantize with Fast Walsh-Hadamard rotation ----- +// Uses O(d log d) WHT instead of O(d²) dense matvec (18× fewer operations) +// 512 bytes of sign arrays instead of 256KB of dense matrices +// ===== INLINED turbo-wht.h ===== +// TurboQuant Fast Walsh-Hadamard rotation for Metal +// Replaces 256KB dense matrices with 512 bytes of sign arrays + O(d log d) butterfly +// Generated with seed=42 (rotation) and seed=1042 (QJL) + +// --- Rotation sign arrays --- +constant float turbo_wht_signs1[128] = { + -1.0f, 1.0f, 1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, -1.0f, 1.0f, 1.0f, 1.0f, 1.0f, 1.0f, 1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, -1.0f, 1.0f, 1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, -1.0f, -1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, 1.0f, 1.0f, -1.0f, -1.0f, -1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, 1.0f, 1.0f, -1.0f, 1.0f, -1.0f, -1.0f, 1.0f, -1.0f, -1.0f, -1.0f, 1.0f, -1.0f, -1.0f, -1.0f, 1.0f, -1.0f, -1.0f, -1.0f, 1.0f, 1.0f, 1.0f, -1.0f, -1.0f, 1.0f, 1.0f, 1.0f, -1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, -1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, 1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, -1.0f, -1.0f, -1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f}; +constant float turbo_wht_signs2[128] = { + 1.0f, 1.0f, 1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, -1.0f, -1.0f, -1.0f, 1.0f, -1.0f, -1.0f, -1.0f, 1.0f, 1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, 1.0f, 1.0f, 1.0f, -1.0f, -1.0f, -1.0f, 1.0f, -1.0f, -1.0f, -1.0f, -1.0f, -1.0f, -1.0f, 1.0f, 1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, 1.0f, -1.0f, -1.0f, 1.0f, -1.0f, -1.0f, -1.0f, -1.0f, -1.0f, -1.0f, 1.0f, 1.0f, 1.0f, -1.0f, 1.0f, -1.0f, -1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, -1.0f, -1.0f, -1.0f, -1.0f, 1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, 1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, -1.0f, -1.0f, -1.0f, -1.0f, 1.0f, -1.0f}; + +// --- Pre-packed half4 sign arrays for vectorized WHT (eliminates float→half conversion) --- +constant half4 turbo_wht_signs1_h4[32] = { + half4(-1.0h, 1.0h, 1.0h, -1.0h), half4(-1.0h, 1.0h, -1.0h, 1.0h), + half4(-1.0h, -1.0h, 1.0h, 1.0h), half4(1.0h, 1.0h, 1.0h, 1.0h), + half4(1.0h, -1.0h, 1.0h, -1.0h), half4(1.0h, -1.0h, -1.0h, 1.0h), + half4(1.0h, 1.0h, -1.0h, 1.0h), half4(1.0h, -1.0h, -1.0h, -1.0h), + half4(-1.0h, 1.0h, 1.0h, -1.0h), half4(1.0h, 1.0h, -1.0h, 1.0h), + half4(-1.0h, 1.0h, 1.0h, -1.0h), half4(-1.0h, 1.0h, -1.0h, 1.0h), + half4(1.0h, 1.0h, 1.0h, -1.0h), half4(-1.0h, -1.0h, -1.0h, -1.0h), + half4(1.0h, -1.0h, 1.0h, 1.0h), half4(1.0h, 1.0h, -1.0h, 1.0h), + half4(-1.0h, -1.0h, 1.0h, -1.0h), half4(-1.0h, -1.0h, 1.0h, -1.0h), + half4(-1.0h, -1.0h, 1.0h, -1.0h), half4(-1.0h, -1.0h, 1.0h, 1.0h), + half4(1.0h, -1.0h, -1.0h, 1.0h), half4(1.0h, 1.0h, -1.0h, -1.0h), + half4(1.0h, 1.0h, -1.0h, 1.0h), half4(1.0h, -1.0h, 1.0h, -1.0h), + half4(-1.0h, 1.0h, 1.0h, -1.0h), half4(1.0h, -1.0h, 1.0h, -1.0h), + half4(1.0h, 1.0h, 1.0h, 1.0h), half4(-1.0h, 1.0h, -1.0h, 1.0h), + half4(1.0h, -1.0h, 1.0h, 1.0h), half4(-1.0h, -1.0h, -1.0h, -1.0h), + half4(-1.0h, 1.0h, 1.0h, -1.0h), half4(1.0h, 1.0h, -1.0h, 1.0h) +}; +constant half4 turbo_wht_signs2_h4[32] = { + half4(1.0h, 1.0h, 1.0h, 1.0h), half4(-1.0h, 1.0h, 1.0h, -1.0h), + half4(1.0h, -1.0h, -1.0h, -1.0h), half4(1.0h, -1.0h, -1.0h, -1.0h), + half4(1.0h, 1.0h, -1.0h, -1.0h), half4(1.0h, -1.0h, 1.0h, -1.0h), + half4(1.0h, -1.0h, -1.0h, 1.0h), half4(-1.0h, 1.0h, 1.0h, 1.0h), + half4(1.0h, 1.0h, -1.0h, -1.0h), half4(-1.0h, 1.0h, -1.0h, -1.0h), + half4(-1.0h, -1.0h, -1.0h, -1.0h), half4(1.0h, 1.0h, 1.0h, -1.0h), + half4(1.0h, -1.0h, 1.0h, 1.0h), half4(1.0h, -1.0h, -1.0h, 1.0h), + half4(-1.0h, -1.0h, -1.0h, -1.0h), half4(-1.0h, -1.0h, 1.0h, 1.0h), + half4(1.0h, -1.0h, 1.0h, -1.0h), half4(-1.0h, -1.0h, -1.0h, 1.0h), + half4(-1.0h, 1.0h, -1.0h, 1.0h), half4(-1.0h, -1.0h, 1.0h, 1.0h), + half4(-1.0h, 1.0h, -1.0h, 1.0h), half4(1.0h, -1.0h, 1.0h, -1.0h), + half4(-1.0h, -1.0h, -1.0h, 1.0h), half4(-1.0h, -1.0h, 1.0h, -1.0h), + half4(1.0h, -1.0h, 1.0h, 1.0h), half4(1.0h, -1.0h, -1.0h, 1.0h), + half4(-1.0h, 1.0h, -1.0h, 1.0h), half4(1.0h, -1.0h, -1.0h, 1.0h), + half4(-1.0h, 1.0h, -1.0h, 1.0h), half4(1.0h, -1.0h, 1.0h, -1.0h), + half4(1.0h, -1.0h, -1.0h, -1.0h), half4(-1.0h, -1.0h, 1.0h, -1.0h) +}; + +// --- QJL sign arrays --- +constant float turbo_qjl_wht_signs1[128] = { + 1.0f, -1.0f, -1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, -1.0f, -1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, -1.0f, -1.0f, 1.0f, 1.0f, 1.0f, 1.0f, 1.0f, -1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, 1.0f, -1.0f, 1.0f, 1.0f, 1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, -1.0f, -1.0f, 1.0f, 1.0f, 1.0f, 1.0f, 1.0f, 1.0f, -1.0f, -1.0f, 1.0f, 1.0f, -1.0f, -1.0f, -1.0f, -1.0f, -1.0f, 1.0f, 1.0f, 1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, 1.0f, 1.0f, 1.0f, 1.0f, 1.0f, 1.0f, -1.0f, 1.0f, -1.0f, -1.0f, 1.0f, -1.0f, -1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, 1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, 1.0f, -1.0f, -1.0f, 1.0f, -1.0f, -1.0f, -1.0f, -1.0f, -1.0f, -1.0f, -1.0f}; +constant float turbo_qjl_wht_signs2[128] = { + 1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, -1.0f, 1.0f, 1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, 1.0f, -1.0f, 1.0f, -1.0f, -1.0f, -1.0f, -1.0f, 1.0f, 1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, -1.0f, -1.0f, -1.0f, -1.0f, 1.0f, 1.0f, 1.0f, 1.0f, 1.0f, 1.0f, 1.0f, 1.0f, 1.0f, -1.0f, -1.0f, 1.0f, 1.0f, 1.0f, 1.0f, 1.0f, 1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, -1.0f, -1.0f, 1.0f, 1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, 1.0f, 1.0f, 1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, -1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, 1.0f, 1.0f, -1.0f, 1.0f, 1.0f, 1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, 1.0f, 1.0f, -1.0f}; + +// --- Fast Walsh-Hadamard Transform (in-place, normalized) --- +// O(n log n) = 896 operations for n=128, vs O(n²) = 16384 for dense matvec +static void turbo_fwht_128(thread float * x) { + for (int h = 1; h < 128; h *= 2) { + for (int i = 0; i < 128; i += h * 2) { + for (int j = i; j < i + h; j++) { + float a = x[j]; + float b = x[j + h]; + x[j] = a + b; + x[j + h] = a - b; + } + } + } + // Normalize by 1/sqrt(128) + const float inv_sqrt_128 = 0.08838834764831845f; // 1/sqrt(128) + for (int i = 0; i < 128; i++) { + x[i] *= inv_sqrt_128; + } +} + +// --- Forward rotation: signs1 → FWHT → signs2 --- +static void turbo_rotate_forward(thread float * x, constant float * s1, constant float * s2) { + for (int i = 0; i < 128; i++) x[i] *= s1[i]; + turbo_fwht_128(x); + for (int i = 0; i < 128; i++) x[i] *= s2[i]; +} + +// --- Inverse rotation: signs2 → FWHT → signs1 (FWHT is its own inverse) --- +static void turbo_rotate_inverse(thread float * x, constant float * s1, constant float * s2) { + for (int i = 0; i < 128; i++) x[i] *= s2[i]; + turbo_fwht_128(x); + for (int i = 0; i < 128; i++) x[i] *= s1[i]; +} + +// ===== END turbo-wht.h ===== + +// 2-bit centroids for d=128 (scaled by 1/sqrt(128)) +constant float turbo_centroids_2bit[4] = { -0.133462f, -0.039994f, 0.039994f, 0.133462f }; +// 3-bit centroids for d=128 +constant float turbo_centroids_3bit[8] = { + -0.190685f, -0.117832f, -0.065717f, -0.021460f, + 0.021460f, 0.065717f, 0.117832f, 0.190685f +}; +// Midpoints for 2-bit nearest centroid lookup +constant float turbo_mid_2bit[3] = { -0.086728f, 0.0f, 0.086728f }; +// Midpoints for 3-bit +constant float turbo_mid_3bit[7] = { -0.154259f, -0.091775f, -0.043589f, 0.0f, 0.043589f, 0.091775f, 0.154259f }; + +// 4-bit PolarQuant centroids (16 levels) — optimal for N(0, 1/sqrt(128)) +constant float turbo_centroids_4bit[16] = { + -0.173926f, -0.117195f, -0.089527f, -0.068756f, + -0.051262f, -0.035597f, -0.020989f, -0.006938f, + 0.006938f, 0.020989f, 0.035597f, 0.051262f, + 0.068756f, 0.089527f, 0.117195f, 0.173926f +}; +constant float turbo_mid_4bit[15] = { + -0.145560f, -0.103361f, -0.079142f, -0.060009f, + -0.043430f, -0.028293f, -0.013963f, 0.000000f, + 0.013963f, 0.028293f, 0.043430f, 0.060009f, + 0.079142f, 0.103361f, 0.145560f +}; + +// Half-precision 4-bit centroid LUT for vec path +constant half turbo_centroids_4bit_h[16] = { + -0.173926h, -0.117195h, -0.089527h, -0.068756h, + -0.051262h, -0.035597h, -0.020989h, -0.006938h, + 0.006938h, 0.020989h, 0.035597h, 0.051262h, + 0.068756h, 0.089527h, 0.117195h, 0.173926h +}; + +// 8-entry magnitude LUT for 4-bit (positive half, ascending) +// idx 8-15 are positive: mag = centroids_4bit[idx] +// idx 0-7 are negative: mag = centroids_4bit[15 - idx] with sign flip +// sign = (idx >> 3) ? +1 : -1 +// mag_idx = (idx & 7) for positive, (7 - (idx & 7)) for negative — but +// since centroids are symmetric ascending, just use: mag[idx & 7] for idx>=8, +// mag[7 - (idx & 7)] for idx<8. Simpler: mag[idx >= 8 ? idx & 7 : 7 - (idx & 7)] +constant half turbo_mag_4bit_h[8] = { + 0.006938h, 0.020989h, 0.035597h, 0.051262h, + 0.068756h, 0.089527h, 0.117195h, 0.173926h +}; + +// Half-precision 2-bit centroid LUT for vec path +constant half turbo_centroids_2bit_h[4] = { + -0.133462h, -0.039994h, 0.039994h, 0.133462h +}; + +// Quantize 32 elements into one block_turbo2_0 (NO rotation — rotation happens +// at the 128-element group level in kernel_set_rows_turbo) +void quantize_turbo2_0(device const float * src, device block_turbo2_0 & dst) { +#pragma METAL fp math_mode(safe) + float norm_sq = 0.0f; + for (int j = 0; j < QK_TURBO2; j++) norm_sq += src[j] * src[j]; + float norm = sqrt(norm_sq); + float inv_norm = norm > 1e-10f ? 1.0f / norm : 0.0f; + dst.norm = half(norm); + + for (int j = 0; j < QK_TURBO2 / 4; j++) dst.qs[j] = 0; + + for (int j = 0; j < QK_TURBO2; j++) { + float val = src[j] * inv_norm; + uint8_t idx; + if (val < turbo_mid_2bit[0]) idx = 0; + else if (val < turbo_mid_2bit[1]) idx = 1; + else if (val < turbo_mid_2bit[2]) idx = 2; + else idx = 3; + + dst.qs[j / 4] |= (idx & 0x3) << ((j % 4) * 2); + } +} + +// Quantize 32 elements into one block_turbo3_0 (NO rotation — rotation happens +// at the 128-element group level in kernel_set_rows_turbo) +void quantize_turbo3_0(device const float * src, device block_turbo3_0 & dst) { +#pragma METAL fp math_mode(safe) + // Compute norm for this 32-element sub-block + float norm_sq = 0.0f; + for (int j = 0; j < QK_TURBO3; j++) norm_sq += src[j] * src[j]; + float norm = sqrt(norm_sq); + float inv_norm = norm > 1e-10f ? 1.0f / norm : 0.0f; + dst.norm = half(norm); + + // Quantize to 3-bit centroids + for (int j = 0; j < QK_TURBO3 / 4; j++) dst.qs[j] = 0; + for (int j = 0; j < QK_TURBO3 / 8; j++) dst.signs[j] = 0; + + for (int j = 0; j < QK_TURBO3; j++) { + float val = src[j] * inv_norm; + uint8_t idx; + if (val < turbo_mid_3bit[0]) idx = 0; + else if (val < turbo_mid_3bit[1]) idx = 1; + else if (val < turbo_mid_3bit[2]) idx = 2; + else if (val < turbo_mid_3bit[3]) idx = 3; + else if (val < turbo_mid_3bit[4]) idx = 4; + else if (val < turbo_mid_3bit[5]) idx = 5; + else if (val < turbo_mid_3bit[6]) idx = 6; + else idx = 7; + + dst.qs[j / 4] |= (idx & 0x3) << ((j % 4) * 2); + if (idx & 0x4) { + dst.signs[j / 8] |= (1 << (j % 8)); + } + } +} + +void quantize_turbo4_0(device const float * src, device block_turbo4_0 & dst) { +#pragma METAL fp math_mode(safe) + // 4-bit PolarQuant: normalize → rotate → quantize to 16 centroids → nibble pack + float norm_sq = 0.0f; + for (int j = 0; j < 128; j++) norm_sq += src[j] * src[j]; + float grp_norm = sqrt(norm_sq); + float inv_norm = grp_norm > 1e-10f ? 1.0f / grp_norm : 0.0f; + + float x[128]; + for (int j = 0; j < 128; j++) x[j] = src[j] * inv_norm; + turbo_rotate_forward(x, turbo_wht_signs1, turbo_wht_signs2); + + for (int j = 0; j < QK_TURBO4 / 2; j++) dst.qs[j] = 0; + + float recon_norm_sq = 0.0f; + for (int j = 0; j < 128; j++) { + float val = x[j]; + uint8_t idx; + if (val < turbo_mid_4bit[ 0]) idx = 0; + else if (val < turbo_mid_4bit[ 1]) idx = 1; + else if (val < turbo_mid_4bit[ 2]) idx = 2; + else if (val < turbo_mid_4bit[ 3]) idx = 3; + else if (val < turbo_mid_4bit[ 4]) idx = 4; + else if (val < turbo_mid_4bit[ 5]) idx = 5; + else if (val < turbo_mid_4bit[ 6]) idx = 6; + else if (val < turbo_mid_4bit[ 7]) idx = 7; + else if (val < turbo_mid_4bit[ 8]) idx = 8; + else if (val < turbo_mid_4bit[ 9]) idx = 9; + else if (val < turbo_mid_4bit[10]) idx = 10; + else if (val < turbo_mid_4bit[11]) idx = 11; + else if (val < turbo_mid_4bit[12]) idx = 12; + else if (val < turbo_mid_4bit[13]) idx = 13; + else if (val < turbo_mid_4bit[14]) idx = 14; + else idx = 15; + + dst.qs[j / 2] |= (idx & 0xF) << ((j % 2) * 4); + recon_norm_sq += turbo_centroids_4bit[idx] * turbo_centroids_4bit[idx]; + } + + dst.rnorm = half(0.0f); + float recon_norm = sqrt(recon_norm_sq); + dst.norm = half((recon_norm > 1e-10f) ? grp_norm / recon_norm : grp_norm); +} + +// ----- turbo3 dequantize with per-thread block cache ----- +// The rotation requires all 128 elements. Flash attention calls dequantize +// up to 32× per block (once per 4-element chunk). We cache the full +// dequantized block per thread and only recompute when the block pointer changes. + +// turbo3 dequant — full block dequantize with inverse rotation +// Must process all 128 elements to apply WHT inverse rotation +// Half-precision vectorized WHT for faster dequant. +// Uses half4 vectors for 4-wide SIMD throughput on Apple GPU. +// Centroids fit in fp16 (max |val| = 0.19), butterfly stays in range. +static void turbo_fwht_128_half4(thread half4 * v) { + // 32 half4 vectors = 128 elements + // Stage h=1: butterfly between elements 0,1 and 2,3 within each half4 + for (int i = 0; i < 32; i++) { + half4 a = v[i]; + v[i] = half4(a.x + a.y, a.x - a.y, a.z + a.w, a.z - a.w); + } + // Stage h=2: butterfly between elements 0,2 and 1,3 within each half4 + for (int i = 0; i < 32; i++) { + half4 a = v[i]; + v[i] = half4(a.x + a.z, a.y + a.w, a.x - a.z, a.y - a.w); + } + // Stages h=4,8,16,32,64: butterfly between half4 vectors + for (int h = 4; h < 128; h *= 2) { + int vec_stride = h / 4; // distance in half4 units + for (int i = 0; i < 32; i++) { + int group_pos = i % (2 * vec_stride); + if (group_pos < vec_stride) { + int partner = i + vec_stride; + half4 a = v[i]; + half4 b = v[partner]; + v[i] = a + b; + v[partner] = a - b; + } + } + } + // Normalize + const half4 inv_sqrt_128 = half4(0.08838834764831845h); + for (int i = 0; i < 32; i++) { + v[i] *= inv_sqrt_128; + } +} + +// ----- turbo2 dequantize ----- +// 2-bit indices (4 centroids), no signs byte. Simpler than turbo3. +// Block size 32, nl=2 for non-vec (32/16), nl=8 for vec (32/4). + +// Non-vec: 16 elements per call (il ∈ {0,1}), returns type4x4 +template +void dequantize_turbo2_0(device const block_turbo2_0 * xb, short il, thread type4x4 & reg) { + const float norm = float(xb->norm); + // il=0 → elements 0-15 (qs bytes 0-3) + // il=1 → elements 16-31 (qs bytes 4-7) + const int qs_off = il * 4; + float4x4 reg_f; + for (int g = 0; g < 4; g++) { + const uint8_t qb = xb->qs[qs_off + g]; + reg_f[g] = float4( + turbo_centroids_2bit[(qb ) & 0x03] * norm, + turbo_centroids_2bit[(qb >> 2) & 0x03] * norm, + turbo_centroids_2bit[(qb >> 4) & 0x03] * norm, + turbo_centroids_2bit[(qb >> 6) ] * norm + ); + } + reg = (type4x4) reg_f; +} + +// Vec: 4 elements per call (il ∈ {0..7}), returns type4 +template +void dequantize_turbo2_0_t4(device const block_turbo2_0 * xb, short il, thread type4 & reg) { + const float norm = float(xb->norm); + // il selects which byte of qs (each byte has 4 x 2-bit values) + const uint8_t qb = xb->qs[il]; + reg = type4(float4( + float(turbo_centroids_2bit_h[(qb ) & 0x03]) * norm, + float(turbo_centroids_2bit_h[(qb >> 2) & 0x03]) * norm, + float(turbo_centroids_2bit_h[(qb >> 4) & 0x03]) * norm, + float(turbo_centroids_2bit_h[(qb >> 6) ]) * norm + )); +} + +// Block-32 dequant: no WHT needed (graph handles rotation). Just centroid lookup + norm scale. +// With QK_TURBO3=32: nl=2 for non-vec FA (32/16), nl=8 for vec FA (32/4). +// Much less redundant work than block-128. + +// Optimized turbo3 dequant: batch byte reads, unrolled index extraction. +// Non-vec: 16 elements per call (il ∈ {0,1}), returns type4x4 +template +void dequantize_turbo3_0(device const block_turbo3_0 * xb, short il, thread type4x4 & reg) { + const float norm = float(xb->norm); + // il=0 → elements 0-15 (qs bytes 0-3, signs bytes 0-1) + // il=1 → elements 16-31 (qs bytes 4-7, signs bytes 2-3) + const int qs_off = il * 4; + float4x4 reg_f; + for (int g = 0; g < 4; g++) { + // g iterates over 4 groups of 4 elements within our 16 + // element index within block: il*16 + g*4 + k, k=0..3 + const uint8_t qb = xb->qs[qs_off + g]; + // signs byte index: (il*16 + g*4) / 8 = il*2 + g/2 + const uint8_t sb = xb->signs[il * 2 + g / 2]; + const int sshift = (g & 1) * 4; + + reg_f[g] = float4( + turbo_centroids_3bit[(qb & 0x03) | (((sb >> (sshift + 0)) & 1) << 2)] * norm, + turbo_centroids_3bit[((qb >> 2) & 0x03) | (((sb >> (sshift + 1)) & 1) << 2)] * norm, + turbo_centroids_3bit[((qb >> 4) & 0x03) | (((sb >> (sshift + 2)) & 1) << 2)] * norm, + turbo_centroids_3bit[((qb >> 6) & 0x03) | (((sb >> (sshift + 3)) & 1) << 2)] * norm + ); + } + reg = (type4x4) reg_f; +} + +// Half-precision centroid LUT for vec path — reduces constant cache pressure at long context. +// Register LUT (cn[8] = centroid*norm in thread registers) was tested but caused register +// spill on Metal, making it slower. Constant half LUT + float norm broadcast remains the +// fastest approach on Apple Silicon. On CUDA, register LUT works better (see @spiritbuun). +constant half turbo_centroids_3bit_h[8] = { + -0.190685h, -0.117832h, -0.065717h, -0.021460h, + 0.021460h, 0.065717h, 0.117832h, 0.190685h +}; + +// 256-entry dequant LUTs: qb byte -> half4 of 4 centroids +// s0 = sign-bit 0 (c[q]), s1 = sign-bit 1 (c[q|4]) +// c[q|4] = -c[3-q] (mirror-reversal, NOT simple negation) +constant half4 turbo3_qb_lut_s0[256] = { + half4(-0.190685h, -0.190685h, -0.190685h, -0.190685h), + half4(-0.117832h, -0.190685h, -0.190685h, -0.190685h), + half4(-0.065717h, -0.190685h, -0.190685h, -0.190685h), + half4(-0.021460h, -0.190685h, -0.190685h, -0.190685h), + half4(-0.190685h, -0.117832h, -0.190685h, -0.190685h), + half4(-0.117832h, -0.117832h, -0.190685h, -0.190685h), + half4(-0.065717h, -0.117832h, -0.190685h, -0.190685h), + half4(-0.021460h, -0.117832h, -0.190685h, -0.190685h), + half4(-0.190685h, -0.065717h, -0.190685h, -0.190685h), + half4(-0.117832h, -0.065717h, -0.190685h, -0.190685h), + half4(-0.065717h, -0.065717h, -0.190685h, -0.190685h), + half4(-0.021460h, -0.065717h, -0.190685h, -0.190685h), + half4(-0.190685h, -0.021460h, -0.190685h, -0.190685h), + half4(-0.117832h, -0.021460h, -0.190685h, -0.190685h), + half4(-0.065717h, -0.021460h, -0.190685h, -0.190685h), + half4(-0.021460h, -0.021460h, -0.190685h, -0.190685h), + half4(-0.190685h, -0.190685h, -0.117832h, -0.190685h), + half4(-0.117832h, -0.190685h, -0.117832h, -0.190685h), + half4(-0.065717h, -0.190685h, -0.117832h, -0.190685h), + half4(-0.021460h, -0.190685h, -0.117832h, -0.190685h), + half4(-0.190685h, -0.117832h, -0.117832h, -0.190685h), + half4(-0.117832h, -0.117832h, -0.117832h, -0.190685h), + half4(-0.065717h, -0.117832h, -0.117832h, -0.190685h), + half4(-0.021460h, -0.117832h, -0.117832h, -0.190685h), + half4(-0.190685h, -0.065717h, -0.117832h, -0.190685h), + half4(-0.117832h, -0.065717h, -0.117832h, -0.190685h), + half4(-0.065717h, -0.065717h, -0.117832h, -0.190685h), + half4(-0.021460h, -0.065717h, -0.117832h, -0.190685h), + half4(-0.190685h, -0.021460h, -0.117832h, -0.190685h), + half4(-0.117832h, -0.021460h, -0.117832h, -0.190685h), + half4(-0.065717h, -0.021460h, -0.117832h, -0.190685h), + half4(-0.021460h, -0.021460h, -0.117832h, -0.190685h), + half4(-0.190685h, -0.190685h, -0.065717h, -0.190685h), + half4(-0.117832h, -0.190685h, -0.065717h, -0.190685h), + half4(-0.065717h, -0.190685h, -0.065717h, -0.190685h), + half4(-0.021460h, -0.190685h, -0.065717h, -0.190685h), + half4(-0.190685h, -0.117832h, -0.065717h, -0.190685h), + half4(-0.117832h, -0.117832h, -0.065717h, -0.190685h), + half4(-0.065717h, -0.117832h, -0.065717h, -0.190685h), + half4(-0.021460h, -0.117832h, -0.065717h, -0.190685h), + half4(-0.190685h, -0.065717h, -0.065717h, -0.190685h), + half4(-0.117832h, -0.065717h, -0.065717h, -0.190685h), + half4(-0.065717h, -0.065717h, -0.065717h, -0.190685h), + half4(-0.021460h, -0.065717h, -0.065717h, -0.190685h), + half4(-0.190685h, -0.021460h, -0.065717h, -0.190685h), + half4(-0.117832h, -0.021460h, -0.065717h, -0.190685h), + half4(-0.065717h, -0.021460h, -0.065717h, -0.190685h), + half4(-0.021460h, -0.021460h, -0.065717h, -0.190685h), + half4(-0.190685h, -0.190685h, -0.021460h, -0.190685h), + half4(-0.117832h, -0.190685h, -0.021460h, -0.190685h), + half4(-0.065717h, -0.190685h, -0.021460h, -0.190685h), + half4(-0.021460h, -0.190685h, -0.021460h, -0.190685h), + half4(-0.190685h, -0.117832h, -0.021460h, -0.190685h), + half4(-0.117832h, -0.117832h, -0.021460h, -0.190685h), + half4(-0.065717h, -0.117832h, -0.021460h, -0.190685h), + half4(-0.021460h, -0.117832h, -0.021460h, -0.190685h), + half4(-0.190685h, -0.065717h, -0.021460h, -0.190685h), + half4(-0.117832h, -0.065717h, -0.021460h, -0.190685h), + half4(-0.065717h, -0.065717h, -0.021460h, -0.190685h), + half4(-0.021460h, -0.065717h, -0.021460h, -0.190685h), + half4(-0.190685h, -0.021460h, -0.021460h, -0.190685h), + half4(-0.117832h, -0.021460h, -0.021460h, -0.190685h), + half4(-0.065717h, -0.021460h, -0.021460h, -0.190685h), + half4(-0.021460h, -0.021460h, -0.021460h, -0.190685h), + half4(-0.190685h, -0.190685h, -0.190685h, -0.117832h), + half4(-0.117832h, -0.190685h, -0.190685h, -0.117832h), + half4(-0.065717h, -0.190685h, -0.190685h, -0.117832h), + half4(-0.021460h, -0.190685h, -0.190685h, -0.117832h), + half4(-0.190685h, -0.117832h, -0.190685h, -0.117832h), + half4(-0.117832h, -0.117832h, -0.190685h, -0.117832h), + half4(-0.065717h, -0.117832h, -0.190685h, -0.117832h), + half4(-0.021460h, -0.117832h, -0.190685h, -0.117832h), + half4(-0.190685h, -0.065717h, -0.190685h, -0.117832h), + half4(-0.117832h, -0.065717h, -0.190685h, -0.117832h), + half4(-0.065717h, -0.065717h, -0.190685h, -0.117832h), + half4(-0.021460h, -0.065717h, -0.190685h, -0.117832h), + half4(-0.190685h, -0.021460h, -0.190685h, -0.117832h), + half4(-0.117832h, -0.021460h, -0.190685h, -0.117832h), + half4(-0.065717h, -0.021460h, -0.190685h, -0.117832h), + half4(-0.021460h, -0.021460h, -0.190685h, -0.117832h), + half4(-0.190685h, -0.190685h, -0.117832h, -0.117832h), + half4(-0.117832h, -0.190685h, -0.117832h, -0.117832h), + half4(-0.065717h, -0.190685h, -0.117832h, -0.117832h), + half4(-0.021460h, -0.190685h, -0.117832h, -0.117832h), + half4(-0.190685h, -0.117832h, -0.117832h, -0.117832h), + half4(-0.117832h, -0.117832h, -0.117832h, -0.117832h), + half4(-0.065717h, -0.117832h, -0.117832h, -0.117832h), + half4(-0.021460h, -0.117832h, -0.117832h, -0.117832h), + half4(-0.190685h, -0.065717h, -0.117832h, -0.117832h), + half4(-0.117832h, -0.065717h, -0.117832h, -0.117832h), + half4(-0.065717h, -0.065717h, -0.117832h, -0.117832h), + half4(-0.021460h, -0.065717h, -0.117832h, -0.117832h), + half4(-0.190685h, -0.021460h, -0.117832h, -0.117832h), + half4(-0.117832h, -0.021460h, -0.117832h, -0.117832h), + half4(-0.065717h, -0.021460h, -0.117832h, -0.117832h), + half4(-0.021460h, -0.021460h, -0.117832h, -0.117832h), + half4(-0.190685h, -0.190685h, -0.065717h, -0.117832h), + half4(-0.117832h, -0.190685h, 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+0.190685h, +0.117832h), + half4(+0.190685h, +0.190685h, +0.190685h, +0.117832h), + half4(+0.021460h, +0.021460h, +0.021460h, +0.190685h), + half4(+0.065717h, +0.021460h, +0.021460h, +0.190685h), + half4(+0.117832h, +0.021460h, +0.021460h, +0.190685h), + half4(+0.190685h, +0.021460h, +0.021460h, +0.190685h), + half4(+0.021460h, +0.065717h, +0.021460h, +0.190685h), + half4(+0.065717h, +0.065717h, +0.021460h, +0.190685h), + half4(+0.117832h, +0.065717h, +0.021460h, +0.190685h), + half4(+0.190685h, +0.065717h, +0.021460h, +0.190685h), + half4(+0.021460h, +0.117832h, +0.021460h, +0.190685h), + half4(+0.065717h, +0.117832h, +0.021460h, +0.190685h), + half4(+0.117832h, +0.117832h, +0.021460h, +0.190685h), + half4(+0.190685h, +0.117832h, +0.021460h, +0.190685h), + half4(+0.021460h, +0.190685h, +0.021460h, +0.190685h), + half4(+0.065717h, +0.190685h, +0.021460h, +0.190685h), + half4(+0.117832h, +0.190685h, +0.021460h, +0.190685h), + half4(+0.190685h, +0.190685h, +0.021460h, +0.190685h), + half4(+0.021460h, +0.021460h, +0.065717h, +0.190685h), + half4(+0.065717h, +0.021460h, +0.065717h, +0.190685h), + half4(+0.117832h, +0.021460h, +0.065717h, +0.190685h), + half4(+0.190685h, +0.021460h, +0.065717h, +0.190685h), + half4(+0.021460h, +0.065717h, +0.065717h, +0.190685h), + half4(+0.065717h, +0.065717h, +0.065717h, +0.190685h), + half4(+0.117832h, +0.065717h, +0.065717h, +0.190685h), + half4(+0.190685h, +0.065717h, +0.065717h, +0.190685h), + half4(+0.021460h, +0.117832h, +0.065717h, +0.190685h), + half4(+0.065717h, +0.117832h, +0.065717h, +0.190685h), + half4(+0.117832h, +0.117832h, +0.065717h, +0.190685h), + half4(+0.190685h, +0.117832h, +0.065717h, +0.190685h), + half4(+0.021460h, +0.190685h, +0.065717h, +0.190685h), + half4(+0.065717h, +0.190685h, +0.065717h, +0.190685h), + half4(+0.117832h, +0.190685h, +0.065717h, +0.190685h), + half4(+0.190685h, +0.190685h, +0.065717h, +0.190685h), + half4(+0.021460h, +0.021460h, +0.117832h, +0.190685h), + half4(+0.065717h, +0.021460h, +0.117832h, +0.190685h), + half4(+0.117832h, +0.021460h, +0.117832h, +0.190685h), + half4(+0.190685h, +0.021460h, +0.117832h, +0.190685h), + half4(+0.021460h, +0.065717h, +0.117832h, +0.190685h), + half4(+0.065717h, +0.065717h, +0.117832h, +0.190685h), + half4(+0.117832h, +0.065717h, +0.117832h, +0.190685h), + half4(+0.190685h, +0.065717h, +0.117832h, +0.190685h), + half4(+0.021460h, +0.117832h, +0.117832h, +0.190685h), + half4(+0.065717h, +0.117832h, +0.117832h, +0.190685h), + half4(+0.117832h, +0.117832h, +0.117832h, +0.190685h), + half4(+0.190685h, +0.117832h, +0.117832h, +0.190685h), + half4(+0.021460h, +0.190685h, +0.117832h, +0.190685h), + half4(+0.065717h, +0.190685h, +0.117832h, +0.190685h), + half4(+0.117832h, +0.190685h, +0.117832h, +0.190685h), + half4(+0.190685h, +0.190685h, +0.117832h, +0.190685h), + half4(+0.021460h, +0.021460h, +0.190685h, +0.190685h), + half4(+0.065717h, +0.021460h, +0.190685h, +0.190685h), + half4(+0.117832h, +0.021460h, +0.190685h, +0.190685h), + half4(+0.190685h, +0.021460h, +0.190685h, +0.190685h), + half4(+0.021460h, +0.065717h, +0.190685h, +0.190685h), + half4(+0.065717h, +0.065717h, +0.190685h, +0.190685h), + half4(+0.117832h, +0.065717h, +0.190685h, +0.190685h), + half4(+0.190685h, +0.065717h, +0.190685h, +0.190685h), + half4(+0.021460h, +0.117832h, +0.190685h, +0.190685h), + half4(+0.065717h, +0.117832h, +0.190685h, +0.190685h), + half4(+0.117832h, +0.117832h, +0.190685h, +0.190685h), + half4(+0.190685h, +0.117832h, +0.190685h, +0.190685h), + half4(+0.021460h, +0.190685h, +0.190685h, +0.190685h), + half4(+0.065717h, +0.190685h, +0.190685h, +0.190685h), + half4(+0.117832h, +0.190685h, +0.190685h, +0.190685h), + half4(+0.190685h, +0.190685h, +0.190685h, +0.190685h) +}; + +// 4-entry magnitude LUT (positive values only, ascending order) +// Used with ALU sign application to halve constant cache divergence +constant half turbo_mag_3bit_h[4] = { + 0.021460h, 0.065717h, 0.117832h, 0.190685h +}; + +// 2-entry PAIR LUT: each entry is a half2 containing two adjacent magnitudes. +// Only 2 possible constant addresses per lookup (vs 4 for mag LUT, 8 for full). +// bit1 selects the pair, bit0 selects within the pair via ternary. +constant half2 turbo_mag_pairs_h[2] = { + half2(0.021460h, 0.065717h), // pair 0: mag indices 0,1 + half2(0.117832h, 0.190685h), // pair 1: mag indices 2,3 +}; + +// Vec: 4 elements per call (il ∈ {0..7}), returns type4 +// Dual 256-entry LUT: qb indexes both s0/s1 tables, select() picks per sign bit +template +void dequantize_turbo3_0_t4(device const block_turbo3_0 * xb, short il, thread type4 & reg) { + const float norm = float(xb->norm); + const uint8_t qb = xb->qs[il]; + const uint8_t sb = xb->signs[il >> 1]; + const int sshift = (il & 1) << 2; + + // Two vector LUT lookups (sign=0 and sign=1 variants) + half4 base0 = turbo3_qb_lut_s0[qb]; + half4 base1 = turbo3_qb_lut_s1[qb]; + + // Extract 4 sign bits and select per-element + uint sb4 = (sb >> sshift) & 0x0F; + bool4 smask = bool4(sb4 & 1, sb4 & 2, sb4 & 4, sb4 & 8); + float4 centroids = float4(select(base0, base1, smask)); + reg = type4(centroids * norm); +} + +// ----- turbo4 dequantize with per-thread block cache ----- + +static void turbo4_dequantize_full_block(device const block_turbo4_0 * xb, thread float * cache) { + const float norm = float(xb->norm); + + // 4-bit nibble unpack — 2 elements per byte, simple and fast + for (int j = 0; j < 128; j++) { + uint8_t idx = (xb->qs[j / 2] >> ((j % 2) * 4)) & 0xF; + cache[j] = turbo_centroids_4bit[idx] * norm; + } +} + +template +void dequantize_turbo4_0(device const block_turbo4_0 * xb, short il, thread type4x4 & reg) { + // Direct 16-element extraction — 4-bit nibble unpack + const float norm = float(xb->norm); + const int base = il * 16; + float4x4 reg_f; + + for (int g = 0; g < 4; g++) { + for (int k = 0; k < 4; k++) { + const int j = base + g * 4 + k; + uint8_t idx = (xb->qs[j / 2] >> ((j % 2) * 4)) & 0xF; + reg_f[g][k] = turbo_centroids_4bit[idx] * norm; + } + } + reg = (type4x4) reg_f; +} + +template +void dequantize_turbo4_0_t4(device const block_turbo4_0 * xb, short il, thread type4 & reg) { + // Direct 16-entry half LUT — fastest on M5 Max (constant cache not the bottleneck) + // 8-mag LUT tested: -3% on M5 due to ternary branch overhead. Keep for M1/M2 if needed. + const float norm = float(xb->norm); + const device uint8_t * qs = xb->qs + il * 2; + const uint8_t qb0 = qs[0]; + const uint8_t qb1 = qs[1]; + + reg = type4(float4( + float(turbo_centroids_4bit_h[(qb0 ) & 0xF]) * norm, + float(turbo_centroids_4bit_h[(qb0 >> 4) & 0xF]) * norm, + float(turbo_centroids_4bit_h[(qb1 ) & 0xF]) * norm, + float(turbo_centroids_4bit_h[(qb1 >> 4) & 0xF]) * norm + )); +} + template void dequantize_q4_1(device const block_q4_1 * xb, short il, thread type4x4 & reg) { device const uint16_t * qs = ((device const uint16_t *)xb + 2); @@ -898,6 +1867,271 @@ void dequantize_iq4_xs(device const block_iq4_xs * xb, short il, thread type4x4 } } +// ============================================================================ +// TQ3_1S / TQ4_1S: WHT-rotated weight quantization constants and dequant +// ============================================================================ + +constant float tq3_centroids[8] = { + -1.996684f, -1.291398f, -0.740341f, -0.247508f, + 0.230106f, 0.725222f, 1.277503f, 1.988943f, +}; + +constant float tq4_centroids[16] = { + -2.732590f, -2.069017f, -1.618046f, -1.256231f, + -0.942340f, -0.656759f, -0.388048f, -0.128395f, + 0.128395f, 0.388048f, 0.656759f, 0.942340f, + 1.256231f, 1.618046f, 2.069017f, 2.732590f, +}; + +constant float tq3_signs[32] = { + +1.0f, -1.0f, +1.0f, -1.0f, +1.0f, +1.0f, -1.0f, +1.0f, + -1.0f, -1.0f, +1.0f, -1.0f, +1.0f, +1.0f, -1.0f, +1.0f, + -1.0f, -1.0f, +1.0f, -1.0f, +1.0f, -1.0f, -1.0f, +1.0f, + -1.0f, +1.0f, +1.0f, -1.0f, +1.0f, -1.0f, -1.0f, +1.0f, +}; + +constant float tq3_inv_sqrt32 = 0.17677669529663688f; // 1/sqrt(32) + +// Unpack 32 x 3-bit indices from 12 bytes (4 groups of 3 bytes = 8 indices each) +inline void tq3_unpack_indices(device const uint8_t * qs, thread uint8_t * indices) { + for (int g = 0; g < 4; g++) { + device const uint8_t * qp = qs + g * 3; + thread uint8_t * idx = indices + g * 8; + idx[0] = qp[0] & 7; + idx[1] = (qp[0] >> 3) & 7; + idx[2] = ((qp[0] >> 6) | (qp[1] << 2)) & 7; + idx[3] = (qp[1] >> 1) & 7; + idx[4] = (qp[1] >> 4) & 7; + idx[5] = ((qp[1] >> 7) | (qp[2] << 1)) & 7; + idx[6] = (qp[2] >> 2) & 7; + idx[7] = (qp[2] >> 5) & 7; + } +} + +// Unpack 8 indices from a single 3-byte group +inline void tq3_unpack_group(device const uint8_t * qp, thread uint8_t * idx) { + idx[0] = qp[0] & 7; + idx[1] = (qp[0] >> 3) & 7; + idx[2] = ((qp[0] >> 6) | (qp[1] << 2)) & 7; + idx[3] = (qp[1] >> 1) & 7; + idx[4] = (qp[1] >> 4) & 7; + idx[5] = ((qp[1] >> 7) | (qp[2] << 1)) & 7; + idx[6] = (qp[2] >> 2) & 7; + idx[7] = (qp[2] >> 5) & 7; +} + +// In-place inverse RHT: WHT butterfly + normalize + undo sign flips +inline void tq3_rht_inverse(thread float * buf) { + for (int step = 1; step < 32; step <<= 1) { + for (int i = 0; i < 32; i += step << 1) { + for (int j = i; j < i + step; j++) { + float a = buf[j]; + float b = buf[j + step]; + buf[j] = a + b; + buf[j + step] = a - b; + } + } + } + for (int i = 0; i < 32; i++) { + buf[i] *= tq3_inv_sqrt32 * tq3_signs[i]; + } +} + +// TQ3_1S dequant: 4x4 with inverse RHT +template +void dequantize_tq3_1s(device const block_tq3_1s * xb, short il, thread type4x4 & reg) { + const float d0 = float(xb->d0); + const float d1 = float(xb->d1); + + uint8_t indices[32]; + tq3_unpack_indices(xb->qs, indices); + + float buf[32]; + for (int j = 0; j < 16; j++) buf[j] = tq3_centroids[indices[j]] * d0; + for (int j = 16; j < 32; j++) buf[j] = tq3_centroids[indices[j]] * d1; + + tq3_rht_inverse(buf); + + float4x4 reg_f; + for (int i = 0; i < 4; i++) { + for (int k = 0; k < 4; k++) { + reg_f[i][k] = buf[il * 16 + i * 4 + k]; + } + } + reg = (type4x4) reg_f; +} + +// TQ3_1S dequant: t4 with inverse RHT +template +void dequantize_tq3_1s_t4(device const block_tq3_1s * xb, short il, thread type4 & reg) { + const float d0 = float(xb->d0); + const float d1 = float(xb->d1); + + uint8_t indices[32]; + tq3_unpack_indices(xb->qs, indices); + + float buf[32]; + for (int j = 0; j < 16; j++) buf[j] = tq3_centroids[indices[j]] * d0; + for (int j = 16; j < 32; j++) buf[j] = tq3_centroids[indices[j]] * d1; + + tq3_rht_inverse(buf); + + int off = il * 4; + reg = (type4) float4(buf[off], buf[off + 1], buf[off + 2], buf[off + 3]); +} + +// TQ3_1S: No-RHT dequant for 4x4 (pre-rotated activations) +template +void dequantize_tq3_1s_rotated(device const block_tq3_1s * xb, short il, thread type4x4 & reg) { + const float d0 = float(xb->d0); + const float d1 = float(xb->d1); + + uint8_t indices[32]; + tq3_unpack_indices(xb->qs, indices); + + float4x4 reg_f; + for (int i = 0; i < 4; i++) { + for (int k = 0; k < 4; k++) { + int j = il * 16 + i * 4 + k; + float d = (j < 16) ? d0 : d1; + reg_f[i][k] = tq3_centroids[indices[j]] * d; + } + } + reg = (type4x4) reg_f; +} + +// TQ3_1S: No-RHT dequant for t4 (pre-rotated activations) +template +void dequantize_tq3_1s_rotated_t4(device const block_tq3_1s * xb, short il, thread type4 & reg) { + const float d0 = float(xb->d0); + const float d1 = float(xb->d1); + + const short g = il / 2; + const short g_off = (il % 2) * 4; + + uint8_t idx[8]; + tq3_unpack_group(xb->qs + g * 3, idx); + + const float d = (il < 4) ? d0 : d1; + reg = (type4) float4( + tq3_centroids[idx[g_off + 0]] * d, + tq3_centroids[idx[g_off + 1]] * d, + tq3_centroids[idx[g_off + 2]] * d, + tq3_centroids[idx[g_off + 3]] * d + ); +} + +// TQ4_1S dequant: 4x4 with inverse RHT +template +void dequantize_tq4_1s(device const block_tq4_1s * xb, short il, thread type4x4 & reg) { + const float d0 = float(xb->d0); + const float d1 = float(xb->d1); + + float buf[32]; + for (int j = 0; j < 32; j++) { + uint8_t idx = (xb->qs[j / 2] >> ((j & 1) * 4)) & 0xF; + float d = (j < 16) ? d0 : d1; + buf[j] = tq4_centroids[idx] * d; + } + + tq3_rht_inverse(buf); + + float4x4 reg_f; + for (int i = 0; i < 4; i++) { + for (int k = 0; k < 4; k++) { + reg_f[i][k] = buf[il * 16 + i * 4 + k]; + } + } + reg = (type4x4) reg_f; +} + +// TQ4_1S dequant: t4 with inverse RHT +template +void dequantize_tq4_1s_t4(device const block_tq4_1s * xb, short il, thread type4 & reg) { + const float d0 = float(xb->d0); + const float d1 = float(xb->d1); + + float buf[32]; + for (int j = 0; j < 32; j++) { + uint8_t idx = (xb->qs[j / 2] >> ((j & 1) * 4)) & 0xF; + float d = (j < 16) ? d0 : d1; + buf[j] = tq4_centroids[idx] * d; + } + + tq3_rht_inverse(buf); + + int off = il * 4; + reg = (type4) float4(buf[off], buf[off + 1], buf[off + 2], buf[off + 3]); +} + +// TQ4_1S: No-RHT dequant for 4x4 (pre-rotated activations) +template +void dequantize_tq4_1s_rotated(device const block_tq4_1s * xb, short il, thread type4x4 & reg) { + const float d0 = float(xb->d0); + const float d1 = float(xb->d1); + + float4x4 reg_f; + for (int i = 0; i < 4; i++) { + for (int k = 0; k < 4; k++) { + int j = il * 16 + i * 4 + k; + uint8_t idx = (xb->qs[j / 2] >> ((j & 1) * 4)) & 0xF; + float d = (j < 16) ? d0 : d1; + reg_f[i][k] = tq4_centroids[idx] * d; + } + } + reg = (type4x4) reg_f; +} + +// TQ4_1S: No-RHT dequant for t4 (pre-rotated activations) +template +void dequantize_tq4_1s_rotated_t4(device const block_tq4_1s * xb, short il, thread type4 & reg) { + const float d0 = float(xb->d0); + const float d1 = float(xb->d1); + + int off = il * 4; + float4 vals; + for (int i = 0; i < 4; i++) { + int j = off + i; + uint8_t idx = (xb->qs[j / 2] >> ((j & 1) * 4)) & 0xF; + float d = (j < 16) ? d0 : d1; + vals[i] = tq4_centroids[idx] * d; + } + reg = (type4) vals; +} + +// Shared pre-rotation kernels (used by both TQ3 and TQ4 for mul_mm path) +kernel void kernel_tq3_rotate_act( + device float * x [[buffer(0)]], + constant int64_t & n [[buffer(1)]], + uint tpig [[thread_position_in_grid]], + ushort tiisg [[thread_index_in_simdgroup]]) { + const int64_t base = ((int64_t)tpig / 32) * 32; + if (base >= n) return; + + float val = x[base + tiisg] * tq3_signs[tiisg]; + for (ushort step = 1; step < 32; step <<= 1) { + float other = simd_shuffle_xor(val, step); + val = (tiisg & step) ? (other - val) : (other + val); + } + x[base + tiisg] = val * tq3_inv_sqrt32; +} + +kernel void kernel_tq3_unrotate_act( + device float * x [[buffer(0)]], + constant int64_t & n [[buffer(1)]], + uint tpig [[thread_position_in_grid]], + ushort tiisg [[thread_index_in_simdgroup]]) { + const int64_t base = ((int64_t)tpig / 32) * 32; + if (base >= n) return; + + float val = x[base + tiisg]; + for (ushort step = 1; step < 32; step <<= 1) { + float other = simd_shuffle_xor(val, step); + val = (tiisg & step) ? (other - val) : (other + val); + } + x[base + tiisg] = val * tq3_inv_sqrt32 * tq3_signs[tiisg]; +} + enum ggml_sort_order { GGML_SORT_ORDER_ASC, GGML_SORT_ORDER_DESC, @@ -2675,6 +3909,99 @@ template [[host_name("kernel_gated_delta_net_f32_2")]] kernel kernel_gated_delta template [[host_name("kernel_gated_delta_net_f32_4")]] kernel kernel_gated_delta_net_t kernel_gated_delta_net_impl; #endif +// ===== TurboQuant4 bulk dequant to fp16 (for prefill FA) ===== +// Dequants turbo4 blocks → half buffer. Dispatch before f16 FA during prefill. +// Each thread processes one 128-element block. +kernel void kernel_turbo4_dequant_f16( + device const block_turbo4_0 * src [[buffer(0)]], + device half * dst [[buffer(1)]], + constant uint & n_blocks [[buffer(2)]], + uint tgpig [[threadgroup_position_in_grid]], + uint tiitg [[thread_index_in_threadgroup]], + uint ntg [[threads_per_threadgroup]]) { + const uint blk_idx = tgpig * ntg + tiitg; + if (blk_idx >= n_blocks) return; + + device const block_turbo4_0 & blk = src[blk_idx]; + device half * out = dst + blk_idx * QK_TURBO4; + const half norm_h = blk.norm; + + // 4-bit nibble unpack → centroid → scale by norm → write fp16 + for (int j = 0; j < QK_TURBO4; j += 2) { + const uint8_t qb = blk.qs[j / 2]; + out[j ] = turbo_centroids_4bit_h[(qb ) & 0xF] * norm_h; + out[j + 1] = turbo_centroids_4bit_h[(qb >> 4) & 0xF] * norm_h; + } +} + +// ===== TurboQuant Walsh-Hadamard Transform kernel ===== +// O(d log d) rotation for 128-element groups. Replaces dense 128x128 matmul. +// Each thread processes one 128-element group using half4 vectorized butterfly. +// Uses the same WHT signs already defined (turbo_wht_signs1/2, turbo_wht_signs1_h4/2_h4). + +kernel void kernel_turbo_wht( + constant ggml_metal_kargs_turbo_wht & args, + device const float * src [[buffer(1)]], + device float * dst [[buffer(2)]], + uint tgpig [[threadgroup_position_in_grid]], + uint tiitg [[thread_index_in_threadgroup]], + uint ntg [[threads_per_threadgroup]]) { + // Each thread handles one 128-element group + const int64_t group_idx = tgpig * ntg + tiitg; + const int64_t n_groups = args.n_elements / 128; + if (group_idx >= n_groups) return; + + const device float * in = src + group_idx * 128; + device float * out = dst + group_idx * 128; + + // Load into half4 vectors for fast butterfly + half4 v[32]; + const bool is_inverse = (args.direction == 1); + + // Apply first signs (s1 for fwd, s2 for inv) + for (int i = 0; i < 32; i++) { + float4 f = float4(in[i*4], in[i*4+1], in[i*4+2], in[i*4+3]); + half4 s = is_inverse ? turbo_wht_signs2_h4[i] : turbo_wht_signs1_h4[i]; + v[i] = half4(f) * s; + } + + // WHT butterfly (7 stages, vectorized half4) + // h=1: within each half4 + for (int i = 0; i < 32; i++) { + half4 a = v[i]; + v[i] = half4(a.x + a.y, a.x - a.y, a.z + a.w, a.z - a.w); + } + // h=2: within each half4 + for (int i = 0; i < 32; i++) { + half4 a = v[i]; + v[i] = half4(a.x + a.z, a.y + a.w, a.x - a.z, a.y - a.w); + } + // h=4..64: between half4 vectors + for (int h = 4; h < 128; h *= 2) { + int vec_stride = h / 4; + for (int i = 0; i < 32; i++) { + int group_pos = i % (2 * vec_stride); + if (group_pos < vec_stride) { + int partner = i + vec_stride; + half4 a = v[i], b = v[partner]; + v[i] = a + b; + v[partner] = a - b; + } + } + } + + // Apply second signs + normalize, write output as fp32 + const half4 inv_sqrt = half4(0.08838834764831845h); + for (int i = 0; i < 32; i++) { + half4 s = is_inverse ? turbo_wht_signs1_h4[i] : turbo_wht_signs2_h4[i]; + float4 f = float4(v[i] * inv_sqrt * s); + out[i*4] = f.x; + out[i*4+1] = f.y; + out[i*4+2] = f.z; + out[i*4+3] = f.w; + } +} + constant short FC_solve_tri_nsg [[function_constant(FC_SOLVE_TRI + 0)]]; constant short FC_solve_tri_n [[function_constant(FC_SOLVE_TRI + 1)]]; constant short FC_solve_tri_k [[function_constant(FC_SOLVE_TRI + 2)]]; @@ -3472,6 +4799,273 @@ kernel void kernel_mul_mv_q8_0_f32( kernel_mul_mv_q8_0_f32_impl(args, src0, src1, dst, shmem, tgpig, tiisg, sgitg); } +// turbo3 mat-vec kernel: dequantize turbo3 blocks and compute dot product with f32 src1 +template +void kernel_mul_mv_turbo3_f32_impl( + args_t args, + device const char * src0, + device const char * src1, + device char * dst, + threadgroup char * shmem, + uint3 tgpig, + ushort tiisg, + ushort sgitg) { + const short NSG = FC_mul_mv_nsg; + + constexpr short NW = N_SIMDWIDTH; + constexpr short NQ = 2; + + const int nb = args.ne00/QK_TURBO3; + + const int r0 = tgpig.x*NR0; + const int r1 = tgpig.y; + const int im = tgpig.z; + + const uint i12 = im%args.ne12; + const uint i13 = im/args.ne12; + + const uint64_t offset1 = r1*args.nb11 + (i12)*args.nb12 + (i13)*args.nb13; + + device const float * y = (device const float *) (src1 + offset1); + + device const block_turbo3_0 * ax[NR0]; + FOR_UNROLL (short row = 0; row < NR0; ++row) { + const uint64_t offset0 = (r0 + row)*args.nb01 + (i12/args.r2)*args.nb02 + (i13/args.r3)*args.nb03; + ax[row] = (device const block_turbo3_0 *) ((device char *) src0 + offset0); + } + + float sumf[NR0] = { 0.f }; + + const short ix = tiisg/(NW/NQ); + const short il = tiisg%(NW/NQ); + + const int ib0 = sgitg*NQ + ix; + + device const float * yb = y + ib0*QK_TURBO3 + il*8; + + for (int ib = ib0; ib < nb; ib += NSG*NQ) { + float yl[8]; + FOR_UNROLL (short i = 0; i < 8; ++i) { + yl[i] = yb[i]; + } + + FOR_UNROLL (short row = 0; row < NR0; ++row) { + device const block_turbo3_0 * xb = ax[row] + ib; + const float norm = float(xb->norm); + + float sum = 0.f; + for (short g = 0; g < 2; ++g) { + const short qs_idx = il*2 + g; + const short signs_idx = il; + const short sshift = (qs_idx & 1) * 4; + + const uint8_t qb = xb->qs[qs_idx]; + const uint8_t sb = xb->signs[signs_idx]; + + sum += turbo_centroids_3bit[(qb & 0x03) | (((sb >> (sshift + 0)) & 1) << 2)] * yl[g*4 + 0]; + sum += turbo_centroids_3bit[((qb >> 2) & 0x03) | (((sb >> (sshift + 1)) & 1) << 2)] * yl[g*4 + 1]; + sum += turbo_centroids_3bit[((qb >> 4) & 0x03) | (((sb >> (sshift + 2)) & 1) << 2)] * yl[g*4 + 2]; + sum += turbo_centroids_3bit[((qb >> 6) & 0x03) | (((sb >> (sshift + 3)) & 1) << 2)] * yl[g*4 + 3]; + } + + sumf[row] += sum * norm; + } + + yb += NSG*NQ*QK_TURBO3; + } + + device float * dst_f32 = (device float *) dst + (uint64_t)im*args.ne0*args.ne1 + (uint64_t)r1*args.ne0; + + helper_mv_reduce_and_write(dst_f32, sumf, r0, args.ne01, tiisg, sgitg, shmem); +} + +[[host_name("kernel_mul_mv_turbo3_f32")]] +kernel void kernel_mul_mv_turbo3_f32( + constant ggml_metal_kargs_mul_mv & args, + device const char * src0, + device const char * src1, + device char * dst, + threadgroup char * shmem [[threadgroup(0)]], + uint3 tgpig[[threadgroup_position_in_grid]], + ushort tiisg[[thread_index_in_simdgroup]], + ushort sgitg[[simdgroup_index_in_threadgroup]]) { + kernel_mul_mv_turbo3_f32_impl(args, src0, src1, dst, shmem, tgpig, tiisg, sgitg); +} + +// ============================================================================ +// TQ3_1S V2.1 fused mat-vec: zero threadgroup memory for rotation, single simd_sum +// Each thread handles one element of the 32-element WHT block, rotates in-register +// ============================================================================ +template +void kernel_mul_mv_tq3_1s_f32_impl( + args_t args, + device const char * src0, + device const char * src1, + device char * dst, + threadgroup char * shmem, + uint3 tgpig, + ushort tiisg, + ushort sgitg) { + const short NSG = FC_mul_mv_nsg; + + const int nb = args.ne00 / 32; + + const int r0 = tgpig.x * NR0; + const int r1 = tgpig.y; + const int im = tgpig.z; + + const uint i12 = im % args.ne12; + const uint i13 = im / args.ne12; + + const uint64_t offset1 = r1*args.nb11 + (i12)*args.nb12 + (i13)*args.nb13; + device const float * y = (device const float *) (src1 + offset1); + + device const block_tq3_1s * ax[NR0]; + FOR_UNROLL (short row = 0; row < NR0; ++row) { + const uint64_t offset0 = (r0 + row)*args.nb01 + (i12/args.r2)*args.nb02 + (i13/args.r3)*args.nb03; + ax[row] = (device const block_tq3_1s *) ((device char *) src0 + offset0); + } + + // V2.1: accumulate across ALL blocks, single simd_sum at the end + float my_sum[NR0] = { 0.f }; + + for (int ib = sgitg; ib < nb; ib += NSG) { + // Load and rotate one activation element in-register + float val = y[ib * 32 + tiisg]; + val *= tq3_signs[tiisg]; + for (ushort step = 1; step < 32; step <<= 1) { + float other = simd_shuffle_xor(val, step); + val = (tiisg & step) ? (other - val) : (other + val); + } + val *= tq3_inv_sqrt32; + + FOR_UNROLL (short row = 0; row < NR0; ++row) { + device const block_tq3_1s * blk = &ax[row][ib]; + const float d = (tiisg < 16) ? float(blk->d0) : float(blk->d1); + + // Unpack this thread's 3-bit index using switch on tiisg%8 + const short g = tiisg / 8; // group index (0..3) + const short gi = tiisg % 8; // index within group + device const uint8_t * qp = blk->qs + g * 3; + + uint8_t idx; + switch (gi) { + case 0: idx = qp[0] & 7; break; + case 1: idx = (qp[0] >> 3) & 7; break; + case 2: idx = ((qp[0] >> 6) | (qp[1] << 2)) & 7; break; + case 3: idx = (qp[1] >> 1) & 7; break; + case 4: idx = (qp[1] >> 4) & 7; break; + case 5: idx = ((qp[1] >> 7) | (qp[2] << 1)) & 7; break; + case 6: idx = (qp[2] >> 2) & 7; break; + case 7: idx = (qp[2] >> 5) & 7; break; + } + + my_sum[row] += tq3_centroids[idx] * d * val; + } + } + + // Single simd_sum at the end (V2.1 key optimization) + float sumf[NR0] = { 0.f }; + FOR_UNROLL (short row = 0; row < NR0; ++row) { + sumf[row] = simd_sum(my_sum[row]); + } + + device float * dst_f32 = (device float *) dst + (uint64_t)im*args.ne0*args.ne1 + (uint64_t)r1*args.ne0; + + helper_mv_reduce_and_write(dst_f32, sumf, r0, args.ne01, tiisg, sgitg, shmem); +} + +[[host_name("kernel_mul_mv_tq3_1s_f32")]] +kernel void kernel_mul_mv_tq3_1s_f32( + constant ggml_metal_kargs_mul_mv & args, + device const char * src0, + device const char * src1, + device char * dst, + threadgroup char * shmem [[threadgroup(0)]], + uint3 tgpig[[threadgroup_position_in_grid]], + ushort tiisg[[thread_index_in_simdgroup]], + ushort sgitg[[simdgroup_index_in_threadgroup]]) { + kernel_mul_mv_tq3_1s_f32_impl(args, src0, src1, dst, shmem, tgpig, tiisg, sgitg); +} + +// ============================================================================ +// TQ4_1S V2.1 fused mat-vec: zero threadgroup memory for rotation, single simd_sum +// ============================================================================ +template +void kernel_mul_mv_tq4_1s_f32_impl( + args_t args, + device const char * src0, + device const char * src1, + device char * dst, + threadgroup char * shmem, + uint3 tgpig, + ushort tiisg, + ushort sgitg) { + const short NSG = FC_mul_mv_nsg; + + const int nb = args.ne00 / 32; + + const int r0 = tgpig.x * NR0; + const int r1 = tgpig.y; + const int im = tgpig.z; + + const uint i12 = im % args.ne12; + const uint i13 = im / args.ne12; + + const uint64_t offset1 = r1*args.nb11 + (i12)*args.nb12 + (i13)*args.nb13; + device const float * y = (device const float *) (src1 + offset1); + + device const block_tq4_1s * ax[NR0]; + FOR_UNROLL (short row = 0; row < NR0; ++row) { + const uint64_t offset0 = (r0 + row)*args.nb01 + (i12/args.r2)*args.nb02 + (i13/args.r3)*args.nb03; + ax[row] = (device const block_tq4_1s *) ((device char *) src0 + offset0); + } + + float my_sum[NR0] = { 0.f }; + + for (int ib = sgitg; ib < nb; ib += NSG) { + float val = y[ib * 32 + tiisg]; + val *= tq3_signs[tiisg]; + for (ushort step = 1; step < 32; step <<= 1) { + float other = simd_shuffle_xor(val, step); + val = (tiisg & step) ? (other - val) : (other + val); + } + val *= tq3_inv_sqrt32; + + FOR_UNROLL (short row = 0; row < NR0; ++row) { + device const block_tq4_1s * blk = &ax[row][ib]; + const float d = (tiisg < 16) ? float(blk->d0) : float(blk->d1); + + // TQ4: simple nibble unpack + uint8_t idx = (blk->qs[tiisg / 2] >> ((tiisg & 1) * 4)) & 0xF; + + my_sum[row] += tq4_centroids[idx] * d * val; + } + } + + float sumf[NR0] = { 0.f }; + FOR_UNROLL (short row = 0; row < NR0; ++row) { + sumf[row] = simd_sum(my_sum[row]); + } + + device float * dst_f32 = (device float *) dst + (uint64_t)im*args.ne0*args.ne1 + (uint64_t)r1*args.ne0; + + helper_mv_reduce_and_write(dst_f32, sumf, r0, args.ne01, tiisg, sgitg, shmem); +} + +[[host_name("kernel_mul_mv_tq4_1s_f32")]] +kernel void kernel_mul_mv_tq4_1s_f32( + constant ggml_metal_kargs_mul_mv & args, + device const char * src0, + device const char * src1, + device char * dst, + threadgroup char * shmem [[threadgroup(0)]], + uint3 tgpig[[threadgroup_position_in_grid]], + ushort tiisg[[thread_index_in_simdgroup]], + ushort sgitg[[simdgroup_index_in_threadgroup]]) { + kernel_mul_mv_tq4_1s_f32_impl(args, src0, src1, dst, shmem, tgpig, tiisg, sgitg); +} + // mat-vec kernel processing in chunks of float4 // chpb - chunks per quantization block template @@ -3764,6 +5358,21 @@ template [[host_name("kernel_mul_mv_ext_iq4_nl_f32_r1_3")]] kernel mul_mv_ext_q4 template [[host_name("kernel_mul_mv_ext_iq4_nl_f32_r1_4")]] kernel mul_mv_ext_q4_f32_t kernel_mul_mv_ext_q4_f32_disp<4, block_iq4_nl, 32, dequantize_iq4_nl_t4>; template [[host_name("kernel_mul_mv_ext_iq4_nl_f32_r1_5")]] kernel mul_mv_ext_q4_f32_t kernel_mul_mv_ext_q4_f32_disp<5, block_iq4_nl, 32, dequantize_iq4_nl_t4>; +template [[host_name("kernel_mul_mv_ext_turbo3_f32_r1_2")]] kernel mul_mv_ext_q4_f32_t kernel_mul_mv_ext_q4_f32_disp<2, block_turbo3_0, 32, dequantize_turbo3_0_t4>; +template [[host_name("kernel_mul_mv_ext_turbo3_f32_r1_3")]] kernel mul_mv_ext_q4_f32_t kernel_mul_mv_ext_q4_f32_disp<3, block_turbo3_0, 32, dequantize_turbo3_0_t4>; +template [[host_name("kernel_mul_mv_ext_turbo3_f32_r1_4")]] kernel mul_mv_ext_q4_f32_t kernel_mul_mv_ext_q4_f32_disp<4, block_turbo3_0, 32, dequantize_turbo3_0_t4>; +template [[host_name("kernel_mul_mv_ext_turbo3_f32_r1_5")]] kernel mul_mv_ext_q4_f32_t kernel_mul_mv_ext_q4_f32_disp<5, block_turbo3_0, 32, dequantize_turbo3_0_t4>; + +template [[host_name("kernel_mul_mv_ext_tq3_1s_f32_r1_2")]] kernel mul_mv_ext_q4_f32_t kernel_mul_mv_ext_q4_f32_disp<2, block_tq3_1s, 2, dequantize_tq3_1s_t4>; +template [[host_name("kernel_mul_mv_ext_tq3_1s_f32_r1_3")]] kernel mul_mv_ext_q4_f32_t kernel_mul_mv_ext_q4_f32_disp<3, block_tq3_1s, 2, dequantize_tq3_1s_t4>; +template [[host_name("kernel_mul_mv_ext_tq3_1s_f32_r1_4")]] kernel mul_mv_ext_q4_f32_t kernel_mul_mv_ext_q4_f32_disp<4, block_tq3_1s, 2, dequantize_tq3_1s_t4>; +template [[host_name("kernel_mul_mv_ext_tq3_1s_f32_r1_5")]] kernel mul_mv_ext_q4_f32_t kernel_mul_mv_ext_q4_f32_disp<5, block_tq3_1s, 2, dequantize_tq3_1s_t4>; + +template [[host_name("kernel_mul_mv_ext_tq4_1s_f32_r1_2")]] kernel mul_mv_ext_q4_f32_t kernel_mul_mv_ext_q4_f32_disp<2, block_tq4_1s, 2, dequantize_tq4_1s_t4>; +template [[host_name("kernel_mul_mv_ext_tq4_1s_f32_r1_3")]] kernel mul_mv_ext_q4_f32_t kernel_mul_mv_ext_q4_f32_disp<3, block_tq4_1s, 2, dequantize_tq4_1s_t4>; +template [[host_name("kernel_mul_mv_ext_tq4_1s_f32_r1_4")]] kernel mul_mv_ext_q4_f32_t kernel_mul_mv_ext_q4_f32_disp<4, block_tq4_1s, 2, dequantize_tq4_1s_t4>; +template [[host_name("kernel_mul_mv_ext_tq4_1s_f32_r1_5")]] kernel mul_mv_ext_q4_f32_t kernel_mul_mv_ext_q4_f32_disp<5, block_tq4_1s, 2, dequantize_tq4_1s_t4>; + template [[host_name("kernel_mul_mv_ext_q4_K_f32_r1_2")]] kernel mul_mv_ext_q4x4_f32_t kernel_mul_mv_ext_q4x4_f32_disp<2, block_q4_K, 256, dequantize_q4_K>; template [[host_name("kernel_mul_mv_ext_q4_K_f32_r1_3")]] kernel mul_mv_ext_q4x4_f32_t kernel_mul_mv_ext_q4x4_f32_disp<3, block_q4_K, 256, dequantize_q4_K>; template [[host_name("kernel_mul_mv_ext_q4_K_f32_r1_4")]] kernel mul_mv_ext_q4x4_f32_t kernel_mul_mv_ext_q4x4_f32_disp<4, block_q4_K, 256, dequantize_q4_K>; @@ -6272,135 +7881,346 @@ kernel void kernel_flash_attn_ext( typedef decltype(kernel_flash_attn_ext) flash_attn_ext_t; -template [[host_name("kernel_flash_attn_ext_f32_dk32_dv32" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_f32_dk40_dv40" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_f32_dk48_dv48" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_f32_dk64_dv64" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_f32_dk72_dv72" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_f32_dk80_dv80" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_f32_dk96_dv96" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_f32_dk112_dv112")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_f32_dk128_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_f32_dk192_dv192")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_f32_dk192_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_f32_dk256_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_f32_dk320_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_f32_dk512_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_f32_dk576_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; - -template [[host_name("kernel_flash_attn_ext_f16_dk32_dv32" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_f16_dk40_dv40" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_f16_dk48_dv48" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_f16_dk64_dv64" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_f16_dk72_dv72" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_f16_dk80_dv80" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_f16_dk96_dv96" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_f16_dk112_dv112")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_f16_dk128_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_f16_dk192_dv192")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_f16_dk192_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_f16_dk256_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_f16_dk320_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_f16_dk512_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_f16_dk576_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kf32_vf32_dk32_dv32" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kf32_vf32_dk40_dv40" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kf32_vf32_dk48_dv48" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kf32_vf32_dk64_dv64" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kf32_vf32_dk72_dv72" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kf32_vf32_dk80_dv80" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kf32_vf32_dk96_dv96" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kf32_vf32_dk112_dv112")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kf32_vf32_dk128_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kf32_vf32_dk192_dv192")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kf32_vf32_dk192_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kf32_vf32_dk256_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kf32_vf32_dk320_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kf32_vf32_dk512_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kf32_vf32_dk576_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; + +template [[host_name("kernel_flash_attn_ext_kf16_vf16_dk32_dv32" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kf16_vf16_dk40_dv40" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kf16_vf16_dk48_dv48" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kf16_vf16_dk64_dv64" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kf16_vf16_dk72_dv72" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kf16_vf16_dk80_dv80" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kf16_vf16_dk96_dv96" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kf16_vf16_dk112_dv112")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kf16_vf16_dk128_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kf16_vf16_dk192_dv192")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kf16_vf16_dk192_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kf16_vf16_dk256_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kf16_vf16_dk320_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kf16_vf16_dk512_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kf16_vf16_dk576_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; #if defined(GGML_METAL_HAS_BF16) -template [[host_name("kernel_flash_attn_ext_bf16_dk32_dv32" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_bf16_dk40_dv40" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_bf16_dk48_dv48" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_bf16_dk64_dv64" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_bf16_dk72_dv72" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_bf16_dk80_dv80" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_bf16_dk96_dv96" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_bf16_dk112_dv112")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_bf16_dk128_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_bf16_dk192_dv192")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_bf16_dk192_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_bf16_dk256_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_bf16_dk320_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_bf16_dk512_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_bf16_dk576_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kbf16_vbf16_dk32_dv32" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kbf16_vbf16_dk40_dv40" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kbf16_vbf16_dk48_dv48" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kbf16_vbf16_dk64_dv64" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kbf16_vbf16_dk72_dv72" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kbf16_vbf16_dk80_dv80" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kbf16_vbf16_dk96_dv96" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kbf16_vbf16_dk112_dv112")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kbf16_vbf16_dk128_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kbf16_vbf16_dk192_dv192")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kbf16_vbf16_dk192_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kbf16_vbf16_dk256_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kbf16_vbf16_dk320_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kbf16_vbf16_dk512_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kbf16_vbf16_dk576_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; #endif -template [[host_name("kernel_flash_attn_ext_q4_0_dk32_dv32" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q4_0_dk40_dv40" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q4_0_dk48_dv48" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q4_0_dk64_dv64" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q4_0_dk72_dv72" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q4_0_dk80_dv80" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q4_0_dk96_dv96" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q4_0_dk112_dv112")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q4_0_dk128_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q4_0_dk192_dv192")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q4_0_dk192_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q4_0_dk256_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q4_0_dk320_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q4_0_dk512_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q4_0_dk576_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; - -template [[host_name("kernel_flash_attn_ext_q4_1_dk32_dv32" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q4_1_dk40_dv40" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q4_1_dk48_dv48" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q4_1_dk64_dv64" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q4_1_dk72_dv72" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q4_1_dk80_dv80" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q4_1_dk96_dv96" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q4_1_dk112_dv112")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q4_1_dk128_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q4_1_dk192_dv192")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q4_1_dk192_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q4_1_dk256_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q4_1_dk320_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q4_1_dk512_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q4_1_dk576_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; - -template [[host_name("kernel_flash_attn_ext_q5_0_dk32_dv32" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q5_0_dk40_dv40" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q5_0_dk48_dv48" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q5_0_dk64_dv64" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q5_0_dk72_dv72" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q5_0_dk80_dv80" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q5_0_dk96_dv96" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q5_0_dk112_dv112")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q5_0_dk128_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q5_0_dk192_dv192")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q5_0_dk192_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q5_0_dk256_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q5_0_dk320_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q5_0_dk512_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q5_0_dk576_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; - -template [[host_name("kernel_flash_attn_ext_q5_1_dk32_dv32" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q5_1_dk40_dv40" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q5_1_dk48_dv48" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q5_1_dk64_dv64" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q5_1_dk72_dv72" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q5_1_dk80_dv80" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q5_1_dk96_dv96" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q5_1_dk112_dv112")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q5_1_dk128_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q5_1_dk192_dv192")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q5_1_dk192_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q5_1_dk256_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q5_1_dk320_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q5_1_dk512_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q5_1_dk576_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; - -template [[host_name("kernel_flash_attn_ext_q8_0_dk32_dv32" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q8_0_dk40_dv40" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q8_0_dk48_dv48" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q8_0_dk64_dv64" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q8_0_dk72_dv72" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q8_0_dk80_dv80" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q8_0_dk96_dv96" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q8_0_dk112_dv112")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q8_0_dk128_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q8_0_dk192_dv192")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q8_0_dk192_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q8_0_dk256_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q8_0_dk320_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q8_0_dk512_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q8_0_dk576_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq4_0_vq4_0_dk32_dv32" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq4_0_vq4_0_dk40_dv40" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq4_0_vq4_0_dk48_dv48" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq4_0_vq4_0_dk64_dv64" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq4_0_vq4_0_dk72_dv72" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq4_0_vq4_0_dk80_dv80" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq4_0_vq4_0_dk96_dv96" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq4_0_vq4_0_dk112_dv112")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq4_0_vq4_0_dk128_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq4_0_vq4_0_dk192_dv192")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq4_0_vq4_0_dk192_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq4_0_vq4_0_dk256_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq4_0_vq4_0_dk320_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq4_0_vq4_0_dk512_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq4_0_vq4_0_dk576_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; + +template [[host_name("kernel_flash_attn_ext_kq4_1_vq4_1_dk32_dv32" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq4_1_vq4_1_dk40_dv40" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq4_1_vq4_1_dk48_dv48" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq4_1_vq4_1_dk64_dv64" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq4_1_vq4_1_dk72_dv72" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq4_1_vq4_1_dk80_dv80" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq4_1_vq4_1_dk96_dv96" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq4_1_vq4_1_dk112_dv112")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq4_1_vq4_1_dk128_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq4_1_vq4_1_dk192_dv192")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq4_1_vq4_1_dk192_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq4_1_vq4_1_dk256_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq4_1_vq4_1_dk320_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq4_1_vq4_1_dk512_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq4_1_vq4_1_dk576_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; + +template [[host_name("kernel_flash_attn_ext_kq5_0_vq5_0_dk32_dv32" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq5_0_vq5_0_dk40_dv40" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq5_0_vq5_0_dk48_dv48" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq5_0_vq5_0_dk64_dv64" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq5_0_vq5_0_dk72_dv72" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq5_0_vq5_0_dk80_dv80" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq5_0_vq5_0_dk96_dv96" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq5_0_vq5_0_dk112_dv112")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq5_0_vq5_0_dk128_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq5_0_vq5_0_dk192_dv192")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq5_0_vq5_0_dk192_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq5_0_vq5_0_dk256_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq5_0_vq5_0_dk320_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq5_0_vq5_0_dk512_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq5_0_vq5_0_dk576_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; + +template [[host_name("kernel_flash_attn_ext_kq5_1_vq5_1_dk32_dv32" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq5_1_vq5_1_dk40_dv40" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq5_1_vq5_1_dk48_dv48" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq5_1_vq5_1_dk64_dv64" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq5_1_vq5_1_dk72_dv72" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq5_1_vq5_1_dk80_dv80" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq5_1_vq5_1_dk96_dv96" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq5_1_vq5_1_dk112_dv112")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq5_1_vq5_1_dk128_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq5_1_vq5_1_dk192_dv192")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq5_1_vq5_1_dk192_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq5_1_vq5_1_dk256_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq5_1_vq5_1_dk320_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq5_1_vq5_1_dk512_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq5_1_vq5_1_dk576_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; + +template [[host_name("kernel_flash_attn_ext_kq8_0_vq8_0_dk32_dv32" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vq8_0_dk40_dv40" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vq8_0_dk48_dv48" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vq8_0_dk64_dv64" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vq8_0_dk72_dv72" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vq8_0_dk80_dv80" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vq8_0_dk96_dv96" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vq8_0_dk112_dv112")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vq8_0_dk128_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vq8_0_dk192_dv192")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vq8_0_dk192_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vq8_0_dk256_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vq8_0_dk320_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vq8_0_dk512_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vq8_0_dk576_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; + +// TurboQuant non-vec flash attention (nl=NL_TURBO3=QK_TURBO3/16) +template [[host_name("kernel_flash_attn_ext_kturbo3_vturbo3_dk32_dv32" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo3_vturbo3_dk64_dv64" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo3_vturbo3_dk96_dv96" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo3_vturbo3_dk128_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo3_vturbo3_dk192_dv192")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo3_vturbo3_dk192_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo3_vturbo3_dk256_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo3_vturbo3_dk320_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo3_vturbo3_dk512_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo3_vturbo3_dk576_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; + +// TurboQuant2 non-vec flash attention (nl=NL_TURBO2=QK_TURBO2/16) +template [[host_name("kernel_flash_attn_ext_kturbo2_vturbo2_dk32_dv32" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo2_vturbo2_dk64_dv64" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo2_vturbo2_dk96_dv96" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo2_vturbo2_dk128_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo2_vturbo2_dk192_dv192")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo2_vturbo2_dk192_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo2_vturbo2_dk256_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo2_vturbo2_dk320_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo2_vturbo2_dk512_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo2_vturbo2_dk576_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; + +// TurboQuant4 non-vec flash attention (block size 128, nl=8) +template [[host_name("kernel_flash_attn_ext_kturbo4_vturbo4_dk32_dv32" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo4_vturbo4_dk64_dv64" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo4_vturbo4_dk96_dv96" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo4_vturbo4_dk128_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo4_vturbo4_dk192_dv192")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo4_vturbo4_dk192_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo4_vturbo4_dk256_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo4_vturbo4_dk320_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo4_vturbo4_dk512_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo4_vturbo4_dk576_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; + +// Asymmetric K/V TurboQuant non-vec flash attention — turbo2 K, turbo3 V +template [[host_name("kernel_flash_attn_ext_kturbo2_vturbo3_dk32_dv32" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo2_vturbo3_dk64_dv64" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo2_vturbo3_dk96_dv96" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo2_vturbo3_dk128_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo2_vturbo3_dk192_dv192")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo2_vturbo3_dk192_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo2_vturbo3_dk256_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo2_vturbo3_dk320_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo2_vturbo3_dk512_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo2_vturbo3_dk576_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; + +// Asymmetric K/V TurboQuant non-vec flash attention — turbo3 K, turbo2 V +template [[host_name("kernel_flash_attn_ext_kturbo3_vturbo2_dk32_dv32" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo3_vturbo2_dk64_dv64" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo3_vturbo2_dk96_dv96" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo3_vturbo2_dk128_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo3_vturbo2_dk192_dv192")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo3_vturbo2_dk192_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo3_vturbo2_dk256_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo3_vturbo2_dk320_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo3_vturbo2_dk512_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo3_vturbo2_dk576_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; + +// Asymmetric K/V TurboQuant non-vec flash attention — turbo2 K, turbo4 V +template [[host_name("kernel_flash_attn_ext_kturbo2_vturbo4_dk32_dv32" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo2_vturbo4_dk64_dv64" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo2_vturbo4_dk96_dv96" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo2_vturbo4_dk128_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo2_vturbo4_dk192_dv192")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo2_vturbo4_dk192_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo2_vturbo4_dk256_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo2_vturbo4_dk320_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo2_vturbo4_dk512_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo2_vturbo4_dk576_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; + +// Asymmetric K/V TurboQuant non-vec flash attention — turbo4 K, turbo2 V +template [[host_name("kernel_flash_attn_ext_kturbo4_vturbo2_dk32_dv32" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo4_vturbo2_dk64_dv64" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo4_vturbo2_dk96_dv96" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo4_vturbo2_dk128_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo4_vturbo2_dk192_dv192")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo4_vturbo2_dk192_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo4_vturbo2_dk256_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo4_vturbo2_dk320_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo4_vturbo2_dk512_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo4_vturbo2_dk576_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; + +// Asymmetric K/V TurboQuant non-vec flash attention — turbo3 K, turbo4 V +template [[host_name("kernel_flash_attn_ext_kturbo3_vturbo4_dk32_dv32" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo3_vturbo4_dk64_dv64" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo3_vturbo4_dk96_dv96" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo3_vturbo4_dk128_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo3_vturbo4_dk192_dv192")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo3_vturbo4_dk192_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo3_vturbo4_dk256_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo3_vturbo4_dk320_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo3_vturbo4_dk512_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo3_vturbo4_dk576_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; + +// Asymmetric K/V TurboQuant non-vec flash attention — turbo4 K, turbo3 V +template [[host_name("kernel_flash_attn_ext_kturbo4_vturbo3_dk32_dv32" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo4_vturbo3_dk64_dv64" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo4_vturbo3_dk96_dv96" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo4_vturbo3_dk128_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo4_vturbo3_dk192_dv192")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo4_vturbo3_dk192_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo4_vturbo3_dk256_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo4_vturbo3_dk320_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo4_vturbo3_dk512_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo4_vturbo3_dk576_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; + + +// Asymmetric q8_0 K, turbo2 V — non-vec flash attention +template [[host_name("kernel_flash_attn_ext_kq8_0_vturbo2_dk32_dv32")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vturbo2_dk40_dv40")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vturbo2_dk48_dv48")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vturbo2_dk64_dv64")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vturbo2_dk72_dv72")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vturbo2_dk80_dv80")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vturbo2_dk96_dv96")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vturbo2_dk112_dv112")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vturbo2_dk128_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vturbo2_dk192_dv192")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vturbo2_dk192_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vturbo2_dk256_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vturbo2_dk320_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vturbo2_dk512_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vturbo2_dk576_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; + +// Asymmetric turbo2 K, q8_0 V — non-vec flash attention +template [[host_name("kernel_flash_attn_ext_kturbo2_vq8_0_dk32_dv32")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo2_vq8_0_dk40_dv40")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo2_vq8_0_dk48_dv48")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo2_vq8_0_dk64_dv64")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo2_vq8_0_dk72_dv72")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo2_vq8_0_dk80_dv80")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo2_vq8_0_dk96_dv96")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo2_vq8_0_dk112_dv112")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo2_vq8_0_dk128_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo2_vq8_0_dk192_dv192")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo2_vq8_0_dk192_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo2_vq8_0_dk256_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo2_vq8_0_dk320_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo2_vq8_0_dk512_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo2_vq8_0_dk576_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; + +// Asymmetric q8_0 K, turbo3 V — non-vec flash attention +template [[host_name("kernel_flash_attn_ext_kq8_0_vturbo3_dk32_dv32")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vturbo3_dk40_dv40")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vturbo3_dk48_dv48")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vturbo3_dk64_dv64")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vturbo3_dk72_dv72")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vturbo3_dk80_dv80")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vturbo3_dk96_dv96")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vturbo3_dk112_dv112")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vturbo3_dk128_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vturbo3_dk192_dv192")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vturbo3_dk192_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vturbo3_dk256_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vturbo3_dk320_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vturbo3_dk512_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vturbo3_dk576_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; + +// Asymmetric turbo3 K, q8_0 V — non-vec flash attention +template [[host_name("kernel_flash_attn_ext_kturbo3_vq8_0_dk32_dv32")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo3_vq8_0_dk40_dv40")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo3_vq8_0_dk48_dv48")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo3_vq8_0_dk64_dv64")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo3_vq8_0_dk72_dv72")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo3_vq8_0_dk80_dv80")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo3_vq8_0_dk96_dv96")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo3_vq8_0_dk112_dv112")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo3_vq8_0_dk128_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo3_vq8_0_dk192_dv192")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo3_vq8_0_dk192_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo3_vq8_0_dk256_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo3_vq8_0_dk320_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo3_vq8_0_dk512_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo3_vq8_0_dk576_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; + +// Asymmetric q8_0 K, turbo4 V — non-vec flash attention +template [[host_name("kernel_flash_attn_ext_kq8_0_vturbo4_dk32_dv32")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vturbo4_dk40_dv40")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vturbo4_dk48_dv48")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vturbo4_dk64_dv64")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vturbo4_dk72_dv72")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vturbo4_dk80_dv80")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vturbo4_dk96_dv96")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vturbo4_dk112_dv112")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vturbo4_dk128_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vturbo4_dk192_dv192")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vturbo4_dk192_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vturbo4_dk256_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vturbo4_dk320_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vturbo4_dk512_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kq8_0_vturbo4_dk576_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; + +// Asymmetric turbo4 K, q8_0 V — non-vec flash attention +template [[host_name("kernel_flash_attn_ext_kturbo4_vq8_0_dk32_dv32")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo4_vq8_0_dk40_dv40")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo4_vq8_0_dk48_dv48")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo4_vq8_0_dk64_dv64")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo4_vq8_0_dk72_dv72")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo4_vq8_0_dk80_dv80")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo4_vq8_0_dk96_dv96")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo4_vq8_0_dk112_dv112")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo4_vq8_0_dk128_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo4_vq8_0_dk192_dv192")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo4_vq8_0_dk192_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo4_vq8_0_dk256_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo4_vq8_0_dk320_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo4_vq8_0_dk512_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_kturbo4_vq8_0_dk576_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; #undef FA_TYPES #undef FA_TYPES_BF @@ -6616,6 +8436,71 @@ kernel void kernel_flash_attn_ext_vec( } else { device const kd4_t * pk = (device const kd4_t *) (k + ((ic + NE*cc + ty)*args.nb11)); +#if TURBO_USE_4MAG && TURBO_FUSED_BLOCK_DOT + // FUSED BLOCK DOT: flip computation order. + // Instead of per-element: score += centroid[idx] * norm * Q[j] + // Do per-centroid: score += mag[c] * norm * sum(Q[j] where mi[j]==c) + // + // 4 centroid iterations × masked Q accumulation replaces + // 32 per-element constant memory lookups. + // float(mi==c) is branchless on Apple GPU (comparison → 0/1). + { + FOR_UNROLL (short ii = 0; ii < DK4/NL; ++ii) { + const short i = ii*NL + tx; + const short blk_idx = i / nl_k; + const short il = i % nl_k; + + device const block_turbo3_0 * xb = ((device const block_turbo3_0 *)pk) + blk_idx; + const float norm = float(xb->norm); + const uint8_t qb = xb->qs[il]; + const uint8_t sb = xb->signs[il >> 1]; + const int sshift = (il & 1) << 2; + + // Extract magnitude indices (with XOR sign reversal) + const uint8_t s0 = (sb >> (sshift )) & 1; + const uint8_t s1 = (sb >> (sshift + 1)) & 1; + const uint8_t s2 = (sb >> (sshift + 2)) & 1; + const uint8_t s3 = (sb >> (sshift + 3)) & 1; + + const uint mi0 = uint((qb ) & 0x03) ^ (s0 ? 0u : 3u); + const uint mi1 = uint((qb >> 2) & 0x03) ^ (s1 ? 0u : 3u); + const uint mi2 = uint((qb >> 4) & 0x03) ^ (s2 ? 0u : 3u); + const uint mi3 = uint((qb >> 6) ) ^ (s3 ? 0u : 3u); + + // Sign multipliers (branchless: 2*s - 1) + const float sg0 = 2.0f * float(s0) - 1.0f; + const float sg1 = 2.0f * float(s1) - 1.0f; + const float sg2 = 2.0f * float(s2) - 1.0f; + const float sg3 = 2.0f * float(s3) - 1.0f; + + // Q values for this thread's 4 elements + const float4 qv = (float4) sq4[i]; + + // Accumulate per-centroid: for each magnitude c, + // sum Q[j]*sign[j] where mi[j]==c + // float(mi==c) is 0.0 or 1.0 — branchless comparison + float score = 0.0f; + for (uint c = 0; c < 4; c++) { + float signed_q_sum = + qv.x * sg0 * float(mi0 == c) + + qv.y * sg1 * float(mi1 == c) + + qv.z * sg2 * float(mi2 == c) + + qv.w * sg3 * float(mi3 == c); + + // ONE constant read per centroid (shared across all elements) + score += float(turbo_mag_3bit_h[c]) * signed_q_sum; + } + + mqk[cc] += score * norm; + } + } + // Each iteration, 8 threads share a block (NL=8 for turbo3). + // Threads 0-3 within the block each hold one mag×norm value. + // Other threads use simd_shuffle to read the right value by mi index. + // + // This eliminates BOTH constant memory AND branches from the inner loop. + // The shuffle is a single-cycle cross-lane operation. +#else k4_t mk; FOR_UNROLL (short ii = 0; ii < DK4/NL; ++ii) { @@ -6625,6 +8510,7 @@ kernel void kernel_flash_attn_ext_vec( mqk[cc] += dot((float4) mk, (float4) sq4[i]); } +#endif } if (NE == 1) { @@ -6725,6 +8611,13 @@ kernel void kernel_flash_attn_ext_vec( } } else { FOR_UNROLL (short cc = 0; cc < C/NE; ++cc) { +#if TURBO_SPARSE_V + // SPARSE V DEQUANT: skip V for positions with negligible attention weight. + // At 32K context, ~90%+ of attention weights are near zero. + // Skipping their V dequant saves ~50% of total dequant cost. + const float attn_weight = float(ss[NE*cc + ty]); + if (attn_weight < 1e-6f) continue; // skip negligible positions +#endif device const vd4_t * pv4 = (device const vd4_t *) (v + ((ic + NE*cc + ty)*args.nb21)); FOR_UNROLL (short ii = 0; ii < DV4/NL; ++ii) { @@ -6893,115 +8786,264 @@ kernel void kernel_flash_attn_ext_vec( typedef decltype(kernel_flash_attn_ext_vec) flash_attn_ext_vec_t; -template [[host_name("kernel_flash_attn_ext_vec_f32_dk32_dv32")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_f16_dk32_dv32")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kf32_vf32_dk32_dv32")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kf16_vf16_dk32_dv32")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; #if defined(GGML_METAL_HAS_BF16) -template [[host_name("kernel_flash_attn_ext_vec_bf16_dk32_dv32")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kbf16_vbf16_dk32_dv32")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; #endif -template [[host_name("kernel_flash_attn_ext_vec_q4_0_dk32_dv32")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q4_1_dk32_dv32")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q5_0_dk32_dv32")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q5_1_dk32_dv32")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q8_0_dk32_dv32")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; - -template [[host_name("kernel_flash_attn_ext_vec_f32_dk64_dv64")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_f16_dk64_dv64")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq4_0_vq4_0_dk32_dv32")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq4_1_vq4_1_dk32_dv32")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq5_0_vq5_0_dk32_dv32")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq5_1_vq5_1_dk32_dv32")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq8_0_vq8_0_dk32_dv32")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; + +template [[host_name("kernel_flash_attn_ext_vec_kf32_vf32_dk64_dv64")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kf16_vf16_dk64_dv64")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; #if defined(GGML_METAL_HAS_BF16) -template [[host_name("kernel_flash_attn_ext_vec_bf16_dk64_dv64")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kbf16_vbf16_dk64_dv64")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; #endif -template [[host_name("kernel_flash_attn_ext_vec_q4_0_dk64_dv64")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q4_1_dk64_dv64")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q5_0_dk64_dv64")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q5_1_dk64_dv64")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q8_0_dk64_dv64")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; - -template [[host_name("kernel_flash_attn_ext_vec_f32_dk96_dv96")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_f16_dk96_dv96")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq4_0_vq4_0_dk64_dv64")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq4_1_vq4_1_dk64_dv64")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq5_0_vq5_0_dk64_dv64")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq5_1_vq5_1_dk64_dv64")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq8_0_vq8_0_dk64_dv64")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; + +template [[host_name("kernel_flash_attn_ext_vec_kf32_vf32_dk96_dv96")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kf16_vf16_dk96_dv96")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; #if defined(GGML_METAL_HAS_BF16) -template [[host_name("kernel_flash_attn_ext_vec_bf16_dk96_dv96")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kbf16_vbf16_dk96_dv96")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; #endif -template [[host_name("kernel_flash_attn_ext_vec_q4_0_dk96_dv96")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q4_1_dk96_dv96")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q5_0_dk96_dv96")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q5_1_dk96_dv96")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q8_0_dk96_dv96")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; - -template [[host_name("kernel_flash_attn_ext_vec_f32_dk128_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_f16_dk128_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq4_0_vq4_0_dk96_dv96")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq4_1_vq4_1_dk96_dv96")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq5_0_vq5_0_dk96_dv96")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq5_1_vq5_1_dk96_dv96")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq8_0_vq8_0_dk96_dv96")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; + +template [[host_name("kernel_flash_attn_ext_vec_kf32_vf32_dk128_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kf16_vf16_dk128_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; #if defined(GGML_METAL_HAS_BF16) -template [[host_name("kernel_flash_attn_ext_vec_bf16_dk128_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kbf16_vbf16_dk128_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; #endif -template [[host_name("kernel_flash_attn_ext_vec_q4_0_dk128_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q4_1_dk128_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q5_0_dk128_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q5_1_dk128_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q8_0_dk128_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; - -template [[host_name("kernel_flash_attn_ext_vec_f32_dk192_dv192")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_f16_dk192_dv192")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq4_0_vq4_0_dk128_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq4_1_vq4_1_dk128_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq5_0_vq5_0_dk128_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq5_1_vq5_1_dk128_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq8_0_vq8_0_dk128_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo3_vturbo3_dk128_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo4_vturbo4_dk128_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; + +template [[host_name("kernel_flash_attn_ext_vec_kf32_vf32_dk192_dv192")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kf16_vf16_dk192_dv192")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; #if defined(GGML_METAL_HAS_BF16) -template [[host_name("kernel_flash_attn_ext_vec_bf16_dk192_dv192")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kbf16_vbf16_dk192_dv192")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; #endif -template [[host_name("kernel_flash_attn_ext_vec_q4_0_dk192_dv192")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q4_1_dk192_dv192")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q5_0_dk192_dv192")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q5_1_dk192_dv192")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q8_0_dk192_dv192")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; - -template [[host_name("kernel_flash_attn_ext_vec_f32_dk192_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_f16_dk192_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq4_0_vq4_0_dk192_dv192")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq4_1_vq4_1_dk192_dv192")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq5_0_vq5_0_dk192_dv192")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq5_1_vq5_1_dk192_dv192")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq8_0_vq8_0_dk192_dv192")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo3_vturbo3_dk192_dv192")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo4_vturbo4_dk192_dv192")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; + +template [[host_name("kernel_flash_attn_ext_vec_kf32_vf32_dk192_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kf16_vf16_dk192_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; #if defined(GGML_METAL_HAS_BF16) -template [[host_name("kernel_flash_attn_ext_vec_bf16_dk192_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kbf16_vbf16_dk192_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; #endif -template [[host_name("kernel_flash_attn_ext_vec_q4_0_dk192_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q4_1_dk192_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q5_0_dk192_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q5_1_dk192_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q8_0_dk192_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; - -template [[host_name("kernel_flash_attn_ext_vec_f32_dk256_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_f16_dk256_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq4_0_vq4_0_dk192_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq4_1_vq4_1_dk192_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq5_0_vq5_0_dk192_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq5_1_vq5_1_dk192_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq8_0_vq8_0_dk192_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo3_vturbo3_dk192_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo4_vturbo4_dk192_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; + +template [[host_name("kernel_flash_attn_ext_vec_kf32_vf32_dk256_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kf16_vf16_dk256_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; #if defined(GGML_METAL_HAS_BF16) -template [[host_name("kernel_flash_attn_ext_vec_bf16_dk256_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kbf16_vbf16_dk256_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; #endif -template [[host_name("kernel_flash_attn_ext_vec_q4_0_dk256_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q4_1_dk256_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q5_0_dk256_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q5_1_dk256_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q8_0_dk256_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; - -template [[host_name("kernel_flash_attn_ext_vec_f32_dk320_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_f16_dk320_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq4_0_vq4_0_dk256_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq4_1_vq4_1_dk256_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq5_0_vq5_0_dk256_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq5_1_vq5_1_dk256_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq8_0_vq8_0_dk256_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo3_vturbo3_dk256_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo4_vturbo4_dk256_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +// TurboQuant flash attention - dk256_dv256 + +template [[host_name("kernel_flash_attn_ext_vec_kf32_vf32_dk320_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kf16_vf16_dk320_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; #if defined(GGML_METAL_HAS_BF16) -template [[host_name("kernel_flash_attn_ext_vec_bf16_dk320_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kbf16_vbf16_dk320_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; #endif -template [[host_name("kernel_flash_attn_ext_vec_q4_0_dk320_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q4_1_dk320_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q5_0_dk320_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q5_1_dk320_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q8_0_dk320_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; - -template [[host_name("kernel_flash_attn_ext_vec_f32_dk512_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_f16_dk512_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq4_0_vq4_0_dk320_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq4_1_vq4_1_dk320_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq5_0_vq5_0_dk320_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq5_1_vq5_1_dk320_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq8_0_vq8_0_dk320_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo3_vturbo3_dk320_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo4_vturbo4_dk320_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; + +template [[host_name("kernel_flash_attn_ext_vec_kf32_vf32_dk512_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kf16_vf16_dk512_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; #if defined(GGML_METAL_HAS_BF16) -template [[host_name("kernel_flash_attn_ext_vec_bf16_dk512_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kbf16_vbf16_dk512_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; #endif -template [[host_name("kernel_flash_attn_ext_vec_q4_0_dk512_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q4_1_dk512_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q5_0_dk512_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q5_1_dk512_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q8_0_dk512_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; - -template [[host_name("kernel_flash_attn_ext_vec_f32_dk576_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_f16_dk576_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq4_0_vq4_0_dk512_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq4_1_vq4_1_dk512_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq5_0_vq5_0_dk512_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq5_1_vq5_1_dk512_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq8_0_vq8_0_dk512_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo3_vturbo3_dk512_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo4_vturbo4_dk512_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; + +template [[host_name("kernel_flash_attn_ext_vec_kf32_vf32_dk576_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kf16_vf16_dk576_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; #if defined(GGML_METAL_HAS_BF16) -template [[host_name("kernel_flash_attn_ext_vec_bf16_dk576_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kbf16_vbf16_dk576_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; #endif -template [[host_name("kernel_flash_attn_ext_vec_q4_0_dk576_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q4_1_dk576_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q5_0_dk576_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q5_1_dk576_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q8_0_dk576_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq4_0_vq4_0_dk576_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq4_1_vq4_1_dk576_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq5_0_vq5_0_dk576_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq5_1_vq5_1_dk576_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq8_0_vq8_0_dk576_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo3_vturbo3_dk576_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo4_vturbo4_dk576_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo2_vturbo2_dk128_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo2_vturbo2_dk192_dv192")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo2_vturbo2_dk192_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo2_vturbo2_dk256_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo2_vturbo2_dk320_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo2_vturbo2_dk512_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo2_vturbo2_dk576_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; + +// Asymmetric K/V TurboQuant vec flash attention — turbo2 K, turbo3 V +template [[host_name("kernel_flash_attn_ext_vec_kturbo2_vturbo3_dk128_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo2_vturbo3_dk192_dv192")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo2_vturbo3_dk192_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo2_vturbo3_dk256_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo2_vturbo3_dk320_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo2_vturbo3_dk512_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo2_vturbo3_dk576_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; + +// Asymmetric K/V TurboQuant vec flash attention — turbo3 K, turbo2 V +template [[host_name("kernel_flash_attn_ext_vec_kturbo3_vturbo2_dk128_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo3_vturbo2_dk192_dv192")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo3_vturbo2_dk192_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo3_vturbo2_dk256_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo3_vturbo2_dk320_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo3_vturbo2_dk512_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo3_vturbo2_dk576_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; + +// Asymmetric K/V TurboQuant vec flash attention — turbo2 K, turbo4 V +template [[host_name("kernel_flash_attn_ext_vec_kturbo2_vturbo4_dk128_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo2_vturbo4_dk192_dv192")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo2_vturbo4_dk192_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo2_vturbo4_dk256_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo2_vturbo4_dk320_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo2_vturbo4_dk512_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo2_vturbo4_dk576_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; + +// Asymmetric K/V TurboQuant vec flash attention — turbo4 K, turbo2 V +template [[host_name("kernel_flash_attn_ext_vec_kturbo4_vturbo2_dk128_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo4_vturbo2_dk192_dv192")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo4_vturbo2_dk192_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo4_vturbo2_dk256_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo4_vturbo2_dk320_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo4_vturbo2_dk512_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo4_vturbo2_dk576_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; + +// Asymmetric K/V TurboQuant vec flash attention — turbo3 K, turbo4 V +template [[host_name("kernel_flash_attn_ext_vec_kturbo3_vturbo4_dk128_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo3_vturbo4_dk192_dv192")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo3_vturbo4_dk192_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo3_vturbo4_dk256_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo3_vturbo4_dk320_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo3_vturbo4_dk512_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo3_vturbo4_dk576_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; + +// Asymmetric K/V TurboQuant vec flash attention — turbo4 K, turbo3 V +template [[host_name("kernel_flash_attn_ext_vec_kturbo4_vturbo3_dk128_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo4_vturbo3_dk192_dv192")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo4_vturbo3_dk192_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo4_vturbo3_dk256_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo4_vturbo3_dk320_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo4_vturbo3_dk512_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo4_vturbo3_dk576_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; + + +// Asymmetric q8_0 K, turbo2 V — vec flash attention +template [[host_name("kernel_flash_attn_ext_vec_kq8_0_vturbo2_dk32_dv32")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq8_0_vturbo2_dk64_dv64")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq8_0_vturbo2_dk96_dv96")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq8_0_vturbo2_dk128_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq8_0_vturbo2_dk192_dv192")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq8_0_vturbo2_dk192_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq8_0_vturbo2_dk256_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq8_0_vturbo2_dk320_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq8_0_vturbo2_dk512_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq8_0_vturbo2_dk576_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; + +// Asymmetric turbo2 K, q8_0 V — vec flash attention +template [[host_name("kernel_flash_attn_ext_vec_kturbo2_vq8_0_dk32_dv32")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo2_vq8_0_dk64_dv64")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo2_vq8_0_dk96_dv96")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo2_vq8_0_dk128_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo2_vq8_0_dk192_dv192")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo2_vq8_0_dk192_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo2_vq8_0_dk256_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo2_vq8_0_dk320_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo2_vq8_0_dk512_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo2_vq8_0_dk576_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; + +// Asymmetric q8_0 K, turbo3 V — vec flash attention +template [[host_name("kernel_flash_attn_ext_vec_kq8_0_vturbo3_dk32_dv32")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq8_0_vturbo3_dk64_dv64")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq8_0_vturbo3_dk96_dv96")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq8_0_vturbo3_dk128_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq8_0_vturbo3_dk192_dv192")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq8_0_vturbo3_dk192_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq8_0_vturbo3_dk256_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq8_0_vturbo3_dk320_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq8_0_vturbo3_dk512_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq8_0_vturbo3_dk576_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; + +// Asymmetric turbo3 K, q8_0 V — vec flash attention +template [[host_name("kernel_flash_attn_ext_vec_kturbo3_vq8_0_dk32_dv32")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo3_vq8_0_dk64_dv64")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo3_vq8_0_dk96_dv96")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo3_vq8_0_dk128_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo3_vq8_0_dk192_dv192")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo3_vq8_0_dk192_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo3_vq8_0_dk256_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo3_vq8_0_dk320_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo3_vq8_0_dk512_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo3_vq8_0_dk576_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; + +// Asymmetric q8_0 K, turbo4 V — vec flash attention +template [[host_name("kernel_flash_attn_ext_vec_kq8_0_vturbo4_dk32_dv32")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq8_0_vturbo4_dk64_dv64")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq8_0_vturbo4_dk96_dv96")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq8_0_vturbo4_dk128_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq8_0_vturbo4_dk192_dv192")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq8_0_vturbo4_dk192_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq8_0_vturbo4_dk256_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq8_0_vturbo4_dk320_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq8_0_vturbo4_dk512_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kq8_0_vturbo4_dk576_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; + +// Asymmetric turbo4 K, q8_0 V — vec flash attention +template [[host_name("kernel_flash_attn_ext_vec_kturbo4_vq8_0_dk32_dv32")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo4_vq8_0_dk64_dv64")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo4_vq8_0_dk96_dv96")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo4_vq8_0_dk128_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo4_vq8_0_dk192_dv192")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo4_vq8_0_dk192_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo4_vq8_0_dk256_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo4_vq8_0_dk320_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo4_vq8_0_dk512_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_kturbo4_vq8_0_dk576_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; #undef FA_TYPES #undef FA_TYPES_F32 @@ -7185,6 +9227,11 @@ template [[host_name("kernel_cpy_q5_0_f16")]] kernel cpy_q_f_t kernel_cpy_q_f32< template [[host_name("kernel_cpy_q5_1_f16")]] kernel cpy_q_f_t kernel_cpy_q_f32; template [[host_name("kernel_cpy_q8_0_f16")]] kernel cpy_q_f_t kernel_cpy_q_f32; +template [[host_name("kernel_cpy_tq3_1s_f32")]] kernel cpy_q_f_t kernel_cpy_q_f32; +template [[host_name("kernel_cpy_tq3_1s_f16")]] kernel cpy_q_f_t kernel_cpy_q_f32; +template [[host_name("kernel_cpy_tq4_1s_f32")]] kernel cpy_q_f_t kernel_cpy_q_f32; +template [[host_name("kernel_cpy_tq4_1s_f16")]] kernel cpy_q_f_t kernel_cpy_q_f32; + kernel void kernel_concat( constant ggml_metal_kargs_concat & args, device const char * src0, @@ -9025,6 +11072,255 @@ kernel void kernel_set_rows_q32( } } +// TurboQuant set_rows kernel — block size 128 (QK_TURBO3/QK_TURBO4) +// TurboQuant SET_ROWS kernel — processes QK_TURBO3_GROUP (128) elements per iteration, +// writes QK_TURBO3_GROUP/QK_TURBO3 (4) blocks per iteration. +// The rotation operates on 128 elements, then results are split into 32-element blocks. +template +kernel void kernel_set_rows_turbo( + constant ggml_metal_kargs_set_rows & args, + device const void * src0, + device const void * src1, + device float * dst, + uint3 tgpig[[threadgroup_position_in_grid]], + uint tiitg[[thread_index_in_threadgroup]], + uint3 tptg [[threads_per_threadgroup]]) { + const int32_t i03 = tgpig.z; + const int32_t i02 = tgpig.y; + const int32_t i12 = i03%args.ne12; + const int32_t i11 = i02%args.ne11; + const int32_t i01 = tgpig.x*tptg.y + tiitg/tptg.x; + if (i01 >= args.ne01) return; + + const int32_t i10 = i01; + const TI i1 = ((const device TI *) ((const device char *) src1 + i10*args.nb10 + i11*args.nb11 + i12*args.nb12))[0]; + + device block_q * dst_row = ( device block_q *) (( device char *) dst + i1*args.nb1 + i02*args.nb2 + i03*args.nb3); + const device float * src_row = (const device float *) ((const device char *) src0 + i01*args.nb01 + i02*args.nb02 + i03*args.nb03); + + // Process in groups of 4 blocks (128 elements) for rotation + const int blocks_per_group = QK_TURBO3_GROUP / QK; // 128/32 = 4 + const int n_groups = args.nk0 / blocks_per_group; + + for (int grp = tiitg%tptg.x; grp < n_groups; grp += tptg.x) { + const device float * grp_src = src_row + QK_TURBO3_GROUP * grp; + + // Normalize and rotate the full 128-element group + float norm_sq = 0.0f; + for (int j = 0; j < QK_TURBO3_GROUP; j++) norm_sq += grp_src[j] * grp_src[j]; + float grp_norm = sqrt(norm_sq); + float inv_norm = grp_norm > 1e-10f ? 1.0f / grp_norm : 0.0f; + + float x[128]; + for (int j = 0; j < 128; j++) x[j] = grp_src[j] * inv_norm; + turbo_rotate_forward(x, turbo_wht_signs1, turbo_wht_signs2); + + // Split into 4 blocks of 32 elements each + // All blocks store the SAME group norm — centroids are in normalized space + // Norm correction (ported from @spiritbuun's CUDA implementation): + // Accumulate ||centroid_vector||^2 across all 128 elements, then store + // grp_norm / ||centroid_vector|| instead of raw grp_norm. This makes + // dequantized vectors have the exact original L2 norm at zero decode cost. + float recon_norm_sq = 0.0f; + + for (int b = 0; b < blocks_per_group; b++) { + device block_q & blk = dst_row[grp * blocks_per_group + b]; + const int off = b * QK; + + for (int j = 0; j < QK / 4; j++) blk.qs[j] = 0; + for (int j = 0; j < QK / 8; j++) blk.signs[j] = 0; + + // Quantize rotated values to 3-bit centroids + for (int j = 0; j < QK; j++) { + float rv = x[off + j]; // rotated, normalized value + uint8_t idx; + if (rv < turbo_mid_3bit[0]) idx = 0; + else if (rv < turbo_mid_3bit[1]) idx = 1; + else if (rv < turbo_mid_3bit[2]) idx = 2; + else if (rv < turbo_mid_3bit[3]) idx = 3; + else if (rv < turbo_mid_3bit[4]) idx = 4; + else if (rv < turbo_mid_3bit[5]) idx = 5; + else if (rv < turbo_mid_3bit[6]) idx = 6; + else idx = 7; + + blk.qs[j / 4] |= (idx & 0x3) << ((j % 4) * 2); + if (idx & 0x4) blk.signs[j / 8] |= (1 << (j % 8)); + + // Accumulate centroid reconstruction norm for norm correction + float c = turbo_centroids_3bit[idx]; + recon_norm_sq += c * c; + } + } + + // Norm correction: store corrected norm so dequant(x) has exact original L2 norm. + // Zero decode cost — dequant already multiplies by stored norm. + float recon_norm = sqrt(recon_norm_sq); + float corrected_norm = (recon_norm > 1e-10f) ? grp_norm / recon_norm : grp_norm; + for (int b = 0; b < blocks_per_group; b++) { + dst_row[grp * blocks_per_group + b].norm = half(corrected_norm); + } + } +} + +// TurboQuant2 SET_ROWS kernel — 2-bit PolarQuant, 4 centroids, no signs byte. +// Same 128-element group WHT rotation as turbo3, but simpler quantization. +template +kernel void kernel_set_rows_turbo2( + constant ggml_metal_kargs_set_rows & args, + device const void * src0, + device const void * src1, + device float * dst, + uint3 tgpig[[threadgroup_position_in_grid]], + uint tiitg[[thread_index_in_threadgroup]], + uint3 tptg [[threads_per_threadgroup]]) { + const int32_t i03 = tgpig.z; + const int32_t i02 = tgpig.y; + const int32_t i12 = i03%args.ne12; + const int32_t i11 = i02%args.ne11; + const int32_t i01 = tgpig.x*tptg.y + tiitg/tptg.x; + if (i01 >= args.ne01) return; + + const int32_t i10 = i01; + const TI i1 = ((const device TI *) ((const device char *) src1 + i10*args.nb10 + i11*args.nb11 + i12*args.nb12))[0]; + + device block_turbo2_0 * dst_row = ( device block_turbo2_0 *) (( device char *) dst + i1*args.nb1 + i02*args.nb2 + i03*args.nb3); + const device float * src_row = (const device float *) ((const device char *) src0 + i01*args.nb01 + i02*args.nb02 + i03*args.nb03); + + // Process in groups of 4 blocks (128 elements) for rotation + const int blocks_per_group = QK_TURBO2_GROUP / QK_TURBO2; // 128/32 = 4 + const int n_groups = args.nk0 / blocks_per_group; + + for (int grp = tiitg%tptg.x; grp < n_groups; grp += tptg.x) { + const device float * grp_src = src_row + QK_TURBO2_GROUP * grp; + + float norm_sq = 0.0f; + for (int j = 0; j < QK_TURBO2_GROUP; j++) norm_sq += grp_src[j] * grp_src[j]; + float grp_norm = sqrt(norm_sq); + float inv_norm = grp_norm > 1e-10f ? 1.0f / grp_norm : 0.0f; + + float x[128]; + for (int j = 0; j < 128; j++) x[j] = grp_src[j] * inv_norm; + turbo_rotate_forward(x, turbo_wht_signs1, turbo_wht_signs2); + + float recon_norm_sq = 0.0f; + + for (int b = 0; b < blocks_per_group; b++) { + device block_turbo2_0 & blk = dst_row[grp * blocks_per_group + b]; + const int off = b * QK_TURBO2; + + for (int j = 0; j < QK_TURBO2 / 4; j++) blk.qs[j] = 0; + + for (int j = 0; j < QK_TURBO2; j++) { + float rv = x[off + j]; + uint8_t idx; + if (rv < turbo_mid_2bit[0]) idx = 0; + else if (rv < turbo_mid_2bit[1]) idx = 1; + else if (rv < turbo_mid_2bit[2]) idx = 2; + else idx = 3; + + blk.qs[j / 4] |= (idx & 0x3) << ((j % 4) * 2); + + float c = turbo_centroids_2bit[idx]; + recon_norm_sq += c * c; + } + } + + float recon_norm = sqrt(recon_norm_sq); + float corrected_norm = (recon_norm > 1e-10f) ? grp_norm / recon_norm : grp_norm; + for (int b = 0; b < blocks_per_group; b++) { + dst_row[grp * blocks_per_group + b].norm = half(corrected_norm); + } + } +} + +// TurboQuant4 SET_ROWS kernel — processes 128 elements per block. +// Unlike turbo3 (4x32 blocks), turbo4 uses single 128-element blocks +// with packed 3-bit indices and QJL signs. +template +kernel void kernel_set_rows_turbo4( + constant ggml_metal_kargs_set_rows & args, + device const void * src0, + device const void * src1, + device float * dst, + uint3 tgpig[[threadgroup_position_in_grid]], + uint tiitg[[thread_index_in_threadgroup]], + uint3 tptg [[threads_per_threadgroup]]) { + const int32_t i03 = tgpig.z; + const int32_t i02 = tgpig.y; + const int32_t i12 = i03%args.ne12; + const int32_t i11 = i02%args.ne11; + const int32_t i01 = tgpig.x*tptg.y + tiitg/tptg.x; + if (i01 >= args.ne01) return; + + const int32_t i10 = i01; + const TI i1 = ((const device TI *) ((const device char *) src1 + i10*args.nb10 + i11*args.nb11 + i12*args.nb12))[0]; + + device block_turbo4_0 * dst_row = ( device block_turbo4_0 *) (( device char *) dst + i1*args.nb1 + i02*args.nb2 + i03*args.nb3); + const device float * src_row = (const device float *) ((const device char *) src0 + i01*args.nb01 + i02*args.nb02 + i03*args.nb03); + + // Each block is one 128-element group (nk0 = ne0 / QK_TURBO4) + const int n_blocks = args.nk0; + + for (int blk_idx = tiitg%tptg.x; blk_idx < n_blocks; blk_idx += tptg.x) { + const device float * blk_src = src_row + QK_TURBO4 * blk_idx; + device block_turbo4_0 & blk = dst_row[blk_idx]; + + // Step 1: Compute norm + normalize + float norm_sq = 0.0f; + for (int j = 0; j < QK_TURBO4; j++) norm_sq += blk_src[j] * blk_src[j]; + float grp_norm = sqrt(norm_sq); + float inv_norm = grp_norm > 1e-10f ? 1.0f / grp_norm : 0.0f; + + float x[128]; + float normalized[128]; + for (int j = 0; j < 128; j++) { + normalized[j] = blk_src[j] * inv_norm; + x[j] = normalized[j]; + } + + // Step 2: WHT rotate in-place + turbo_rotate_forward(x, turbo_wht_signs1, turbo_wht_signs2); + + // Step 3: 4-bit PolarQuant — nibble packing (2 indices per byte) + for (int j = 0; j < QK_TURBO4 / 2; j++) blk.qs[j] = 0; + // qs[64] covers full nibble range — no signs field in 4-bit struct + + float recon_norm_sq = 0.0f; + for (int j = 0; j < 128; j++) { + float val = x[j]; + uint8_t idx; + if (val < turbo_mid_4bit[ 0]) idx = 0; + else if (val < turbo_mid_4bit[ 1]) idx = 1; + else if (val < turbo_mid_4bit[ 2]) idx = 2; + else if (val < turbo_mid_4bit[ 3]) idx = 3; + else if (val < turbo_mid_4bit[ 4]) idx = 4; + else if (val < turbo_mid_4bit[ 5]) idx = 5; + else if (val < turbo_mid_4bit[ 6]) idx = 6; + else if (val < turbo_mid_4bit[ 7]) idx = 7; + else if (val < turbo_mid_4bit[ 8]) idx = 8; + else if (val < turbo_mid_4bit[ 9]) idx = 9; + else if (val < turbo_mid_4bit[10]) idx = 10; + else if (val < turbo_mid_4bit[11]) idx = 11; + else if (val < turbo_mid_4bit[12]) idx = 12; + else if (val < turbo_mid_4bit[13]) idx = 13; + else if (val < turbo_mid_4bit[14]) idx = 14; + else idx = 15; + + // 4-bit nibble pack: 2 elements per byte + blk.qs[j / 2] |= (idx & 0xF) << ((j % 2) * 4); + + float c = turbo_centroids_4bit[idx]; + recon_norm_sq += c * c; + } + + blk.rnorm = half(0.0f); // reserved field, unused in 4-bit mode + + // Norm correction + float recon_norm = sqrt(recon_norm_sq); + blk.norm = half((recon_norm > 1e-10f) ? grp_norm / recon_norm : grp_norm); + } +} + template kernel void kernel_set_rows_f( constant ggml_metal_kargs_set_rows & args, @@ -9781,6 +12077,8 @@ template [[host_name("kernel_get_rows_q4_1")]] kernel get_rows_q_t kernel_get template [[host_name("kernel_get_rows_q5_0")]] kernel get_rows_q_t kernel_get_rows_q; template [[host_name("kernel_get_rows_q5_1")]] kernel get_rows_q_t kernel_get_rows_q; template [[host_name("kernel_get_rows_q8_0")]] kernel get_rows_q_t kernel_get_rows_q; +template [[host_name("kernel_get_rows_tq3_1s")]] kernel get_rows_q_t kernel_get_rows_q; +template [[host_name("kernel_get_rows_tq4_1s")]] kernel get_rows_q_t kernel_get_rows_q; template [[host_name("kernel_get_rows_mxfp4")]] kernel get_rows_q_t kernel_get_rows_q; template [[host_name("kernel_get_rows_q2_K")]] kernel get_rows_q_t kernel_get_rows_q; template [[host_name("kernel_get_rows_q3_K")]] kernel get_rows_q_t kernel_get_rows_q; @@ -9827,6 +12125,24 @@ template [[host_name("kernel_set_rows_q5_1_i32")]] kernel set_rows_q32_t kerne template [[host_name("kernel_set_rows_iq4_nl_i64")]] kernel set_rows_q32_t kernel_set_rows_q32; template [[host_name("kernel_set_rows_iq4_nl_i32")]] kernel set_rows_q32_t kernel_set_rows_q32; +// TurboQuant3 set_rows instantiations (4x32-element blocks per 128-element group) +typedef decltype(kernel_set_rows_turbo) set_rows_turbo3_t; + +template [[host_name("kernel_set_rows_turbo3_i64")]] kernel set_rows_turbo3_t kernel_set_rows_turbo; +template [[host_name("kernel_set_rows_turbo3_i32")]] kernel set_rows_turbo3_t kernel_set_rows_turbo; + +// TurboQuant2 set_rows instantiations (dedicated kernel, 4x32-element blocks, no signs) +typedef decltype(kernel_set_rows_turbo2) set_rows_turbo2_t; + +template [[host_name("kernel_set_rows_turbo2_i64")]] kernel set_rows_turbo2_t kernel_set_rows_turbo2; +template [[host_name("kernel_set_rows_turbo2_i32")]] kernel set_rows_turbo2_t kernel_set_rows_turbo2; + +// TurboQuant4 set_rows instantiations (dedicated kernel, 128-element blocks with QJL) +typedef decltype(kernel_set_rows_turbo4) set_rows_turbo4_t; + +template [[host_name("kernel_set_rows_turbo4_i64")]] kernel set_rows_turbo4_t kernel_set_rows_turbo4; +template [[host_name("kernel_set_rows_turbo4_i32")]] kernel set_rows_turbo4_t kernel_set_rows_turbo4; + // // matrix-matrix multiplication // @@ -9843,6 +12159,10 @@ template [[host_name("kernel_mul_mm_q4_1_f32")]] kernel mul_mm_t kernel_mul_m template [[host_name("kernel_mul_mm_q5_0_f32")]] kernel mul_mm_t kernel_mul_mm; template [[host_name("kernel_mul_mm_q5_1_f32")]] kernel mul_mm_t kernel_mul_mm; template [[host_name("kernel_mul_mm_q8_0_f32")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_tq3_1s_f32")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_tq3_1s_rotated_f32")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_tq4_1s_f32")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_tq4_1s_rotated_f32")]] kernel mul_mm_t kernel_mul_mm; template [[host_name("kernel_mul_mm_mxfp4_f32")]] kernel mul_mm_t kernel_mul_mm; template [[host_name("kernel_mul_mm_q2_K_f32")]] kernel mul_mm_t kernel_mul_mm; template [[host_name("kernel_mul_mm_q3_K_f32")]] kernel mul_mm_t kernel_mul_mm; @@ -9858,6 +12178,8 @@ template [[host_name("kernel_mul_mm_iq1_s_f32")]] kernel mul_mm_t kernel_mul_m template [[host_name("kernel_mul_mm_iq1_m_f32")]] kernel mul_mm_t kernel_mul_mm; template [[host_name("kernel_mul_mm_iq4_nl_f32")]] kernel mul_mm_t kernel_mul_mm; template [[host_name("kernel_mul_mm_iq4_xs_f32")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_turbo3_f32")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_turbo4_f32")]] kernel mul_mm_t kernel_mul_mm; template [[host_name("kernel_mul_mm_f32_f16")]] kernel mul_mm_t kernel_mul_mm; template [[host_name("kernel_mul_mm_f16_f16")]] kernel mul_mm_t kernel_mul_mm; @@ -9866,6 +12188,10 @@ template [[host_name("kernel_mul_mm_q4_1_f16")]] kernel mul_mm_t kernel_mul_m template [[host_name("kernel_mul_mm_q5_0_f16")]] kernel mul_mm_t kernel_mul_mm; template [[host_name("kernel_mul_mm_q5_1_f16")]] kernel mul_mm_t kernel_mul_mm; template [[host_name("kernel_mul_mm_q8_0_f16")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_tq3_1s_f16")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_tq3_1s_rotated_f16")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_tq4_1s_f16")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_tq4_1s_rotated_f16")]] kernel mul_mm_t kernel_mul_mm; template [[host_name("kernel_mul_mm_mxfp4_f16")]] kernel mul_mm_t kernel_mul_mm; template [[host_name("kernel_mul_mm_q2_K_f16")]] kernel mul_mm_t kernel_mul_mm; template [[host_name("kernel_mul_mm_q3_K_f16")]] kernel mul_mm_t kernel_mul_mm; @@ -9881,6 +12207,8 @@ template [[host_name("kernel_mul_mm_iq1_s_f16")]] kernel mul_mm_t kernel_mul_m template [[host_name("kernel_mul_mm_iq1_m_f16")]] kernel mul_mm_t kernel_mul_mm; template [[host_name("kernel_mul_mm_iq4_nl_f16")]] kernel mul_mm_t kernel_mul_mm; template [[host_name("kernel_mul_mm_iq4_xs_f16")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_turbo3_f16")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_turbo4_f16")]] kernel mul_mm_t kernel_mul_mm; // // indirect matrix-matrix multiplication @@ -9898,6 +12226,10 @@ template [[host_name("kernel_mul_mm_id_q4_1_f32")]] kernel mul_mm_id kernel_m template [[host_name("kernel_mul_mm_id_q5_0_f32")]] kernel mul_mm_id kernel_mul_mm_id; template [[host_name("kernel_mul_mm_id_q5_1_f32")]] kernel mul_mm_id kernel_mul_mm_id; template [[host_name("kernel_mul_mm_id_q8_0_f32")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_tq3_1s_f32")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_tq3_1s_rotated_f32")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_tq4_1s_f32")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_tq4_1s_rotated_f32")]] kernel mul_mm_id kernel_mul_mm_id; template [[host_name("kernel_mul_mm_id_mxfp4_f32")]] kernel mul_mm_id kernel_mul_mm_id; template [[host_name("kernel_mul_mm_id_q2_K_f32")]] kernel mul_mm_id kernel_mul_mm_id; template [[host_name("kernel_mul_mm_id_q3_K_f32")]] kernel mul_mm_id kernel_mul_mm_id; @@ -9913,6 +12245,8 @@ template [[host_name("kernel_mul_mm_id_iq1_s_f32")]] kernel mul_mm_id kernel_m template [[host_name("kernel_mul_mm_id_iq1_m_f32")]] kernel mul_mm_id kernel_mul_mm_id; template [[host_name("kernel_mul_mm_id_iq4_nl_f32")]] kernel mul_mm_id kernel_mul_mm_id; template [[host_name("kernel_mul_mm_id_iq4_xs_f32")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_turbo3_f32")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_turbo4_f32")]] kernel mul_mm_id kernel_mul_mm_id; template [[host_name("kernel_mul_mm_id_f32_f16")]] kernel mul_mm_id kernel_mul_mm_id; template [[host_name("kernel_mul_mm_id_f16_f16")]] kernel mul_mm_id kernel_mul_mm_id; @@ -9921,6 +12255,10 @@ template [[host_name("kernel_mul_mm_id_q4_1_f16")]] kernel mul_mm_id kernel_m template [[host_name("kernel_mul_mm_id_q5_0_f16")]] kernel mul_mm_id kernel_mul_mm_id; template [[host_name("kernel_mul_mm_id_q5_1_f16")]] kernel mul_mm_id kernel_mul_mm_id; template [[host_name("kernel_mul_mm_id_q8_0_f16")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_tq3_1s_f16")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_tq3_1s_rotated_f16")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_tq4_1s_f16")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_tq4_1s_rotated_f16")]] kernel mul_mm_id kernel_mul_mm_id; template [[host_name("kernel_mul_mm_id_mxfp4_f16")]] kernel mul_mm_id kernel_mul_mm_id; template [[host_name("kernel_mul_mm_id_q2_K_f16")]] kernel mul_mm_id kernel_mul_mm_id; template [[host_name("kernel_mul_mm_id_q3_K_f16")]] kernel mul_mm_id kernel_mul_mm_id; @@ -9936,6 +12274,8 @@ template [[host_name("kernel_mul_mm_id_iq1_s_f16")]] kernel mul_mm_id kernel_m template [[host_name("kernel_mul_mm_id_iq1_m_f16")]] kernel mul_mm_id kernel_mul_mm_id; template [[host_name("kernel_mul_mm_id_iq4_nl_f16")]] kernel mul_mm_id kernel_mul_mm_id; template [[host_name("kernel_mul_mm_id_iq4_xs_f16")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_turbo3_f16")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_turbo4_f16")]] kernel mul_mm_id kernel_mul_mm_id; // // matrix-vector multiplication @@ -10069,6 +12409,9 @@ template [[host_name("kernel_mul_mv_id_bf16_f32_4")]] kernel kernel_mul_mv_id_4 #endif template [[host_name("kernel_mul_mv_id_q8_0_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; +template [[host_name("kernel_mul_mv_id_turbo3_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; +template [[host_name("kernel_mul_mv_id_tq3_1s_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; +template [[host_name("kernel_mul_mv_id_tq4_1s_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; template [[host_name("kernel_mul_mv_id_q4_0_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; template [[host_name("kernel_mul_mv_id_q4_1_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; diff --git a/ggml/src/ggml-metal/turbo-matrices.h b/ggml/src/ggml-metal/turbo-matrices.h new file mode 100644 index 00000000000..3574911bb52 --- /dev/null +++ b/ggml/src/ggml-metal/turbo-matrices.h @@ -0,0 +1,8207 @@ +// Auto-generated TurboQuant rotation and QJL matrices +// Generated from Python turboquant with seed=42 (rotation) and seed=1042 (QJL) +// DO NOT EDIT — regenerate with benchmarks/generate_metal_matrices.py + +constant float turbo_rotation_mtl[16384] = { + 2.82600336e-02f, -8.67175311e-02f, 7.18313754e-02f, 8.69530439e-02f, -2.14736775e-01f, -9.97434929e-02f, -9.84738488e-03f, -4.04329076e-02f, + -1.69240665e-02f, -1.16859086e-01f, 2.81025153e-02f, 8.68710950e-02f, 4.89934646e-02f, 7.75201619e-02f, 6.60289153e-02f, -7.96402022e-02f, + 3.34256254e-02f, -8.21288452e-02f, 3.31802666e-02f, 1.21842464e-02f, 3.17789391e-02f, -1.53055266e-02f, 7.82487988e-02f, -9.44225490e-03f, + -7.80701414e-02f, -6.16059415e-02f, -2.67151147e-02f, 3.94275598e-02f, 8.89857411e-02f, 2.81025060e-02f, 1.35718212e-01f, -4.66006100e-02f, + -2.67406590e-02f, 2.97649484e-02f, 5.17363176e-02f, 1.72317579e-01f, -6.10202849e-02f, -7.49400854e-02f, -1.04280241e-01f, 8.23100507e-02f, + 8.70125070e-02f, 1.00102223e-01f, 9.90511291e-03f, 3.08756400e-02f, 8.10532495e-02f, 4.83206213e-02f, 7.53946230e-02f, -3.25834341e-02f, + 1.95403881e-02f, -8.48887023e-03f, 5.06697930e-02f, -7.99585357e-02f, -1.36392057e-01f, 3.73734422e-02f, -6.90489113e-02f, -1.60822034e-01f, + -4.22835769e-03f, 1.43416658e-01f, -5.66069633e-02f, 2.43057217e-02f, -2.50643909e-01f, -8.97793507e-04f, -3.89356166e-02f, 3.18646729e-02f, + 4.90970239e-02f, 3.80970016e-02f, -4.28960063e-02f, -3.93266939e-02f, -2.37147026e-02f, -9.04553160e-02f, -1.71422049e-01f, -1.17236793e-01f, + -1.17076650e-01f, 6.62306920e-02f, 1.58756137e-01f, -3.88484858e-02f, 6.66186512e-02f, 8.35609436e-02f, 1.15794942e-01f, -1.21478429e-02f, + 1.82576835e-01f, -5.85689209e-02f, -6.51450604e-02f, 3.72549854e-02f, -1.64549321e-01f, 2.14362815e-02f, 2.44116061e-03f, 6.31230548e-02f, + 9.78827327e-02f, 4.58243564e-02f, -4.45412397e-02f, 4.44438308e-02f, 1.27062723e-01f, 3.82545181e-02f, -2.61128992e-02f, -1.72933578e-01f, + -1.42546639e-01f, -1.60269558e-01f, 1.04717433e-01f, -1.80072282e-02f, 7.75879398e-02f, 7.58307055e-02f, 4.74542230e-02f, 2.36138608e-03f, + -1.89899325e-01f, 7.51865506e-02f, -4.33282331e-02f, 4.41071540e-02f, 3.60562876e-02f, 9.35823321e-02f, -3.94118205e-02f, -2.63573807e-02f, + 6.24631457e-02f, -1.26043588e-01f, 2.24035326e-02f, -1.60270676e-01f, 1.56700149e-01f, 8.29595793e-03f, -8.02326649e-02f, -7.29508847e-02f, + -1.48169667e-01f, -3.32537070e-02f, -1.20963648e-01f, -2.17543110e-01f, 3.24618705e-02f, 1.10951796e-01f, 1.05127292e-02f, 5.74578810e-03f, + -5.93317598e-02f, -9.76941958e-02f, -3.98431495e-02f, -1.15324661e-01f, 5.38127795e-02f, -1.96396653e-02f, -9.90145430e-02f, -1.00666285e-01f, + 4.92317565e-02f, 8.33406448e-02f, 1.84119999e-01f, 2.60870099e-01f, -1.20893391e-02f, -6.91213310e-02f, -1.08464889e-01f, 4.79829237e-02f, + -9.48027372e-02f, -6.33704886e-02f, -5.22563308e-02f, -3.86491641e-02f, -9.83506907e-03f, -2.15524957e-02f, -3.89348008e-02f, -7.95023963e-02f, + -1.23175174e-01f, -2.43162625e-02f, -1.30570550e-02f, 1.20763697e-01f, 4.39689532e-02f, 9.98850018e-02f, -6.44270331e-02f, -5.62599786e-02f, + -1.25691041e-01f, -5.21586277e-02f, 1.61904186e-01f, -9.90369692e-02f, 2.10904796e-02f, 1.95709467e-02f, 8.84430408e-02f, -9.00557116e-02f, + -3.46034556e-03f, 3.87430016e-04f, -5.89115508e-02f, 3.04734241e-02f, 1.70401540e-02f, -8.61348435e-02f, -1.02928750e-01f, 1.50330085e-02f, + 8.84824693e-02f, 5.78373782e-02f, -3.73937935e-02f, 8.72358754e-02f, 7.97277763e-02f, 1.76846292e-02f, -2.30141040e-02f, 7.09971189e-02f, + -2.14520618e-02f, 1.79698393e-01f, 2.63713375e-02f, -6.86059147e-02f, -1.59536436e-01f, 9.51379910e-02f, 1.11320917e-03f, -1.08684301e-02f, + -2.45013572e-02f, 1.01451308e-01f, -6.09642230e-02f, -1.01581439e-01f, 7.75500983e-02f, 5.66286519e-02f, 1.47749055e-02f, -7.17169344e-02f, + -2.95142159e-02f, 1.45612434e-01f, -8.51485953e-02f, -3.26383822e-02f, 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-5.61933994e-01f, 8.98649991e-01f, + 4.87988204e-01f, 3.37603778e-01f, 4.95752841e-01f, -7.06252277e-01f, -1.28126931e+00f, 6.53017998e-01f, -2.36034989e+00f, 3.73941809e-01f, + -3.87035072e-01f, -5.33323407e-01f, -1.36294961e+00f, -1.21843302e+00f, -1.57491818e-01f, -2.29859138e+00f, -2.79846072e-01f, 4.01442647e-01f, + -1.26508570e+00f, -7.05365479e-01f, -1.18259752e+00f, 4.55338150e-01f, -1.86351967e+00f, 5.75556457e-01f, 2.38490954e-01f, 1.76491773e+00f, + 3.70481968e-01f, -1.20471823e+00f, -2.81762064e-01f, 3.15798074e-01f, 2.54140782e+00f, 7.39951909e-01f, 9.96319175e-01f, 2.32283860e-01f, + -7.14402378e-01f, 1.31616735e+00f, 1.34807050e+00f, -8.36144537e-02f, -7.17967808e-01f, 1.22908926e+00f, 7.62344301e-01f, -1.08050179e+00f, + 1.23759973e+00f, -1.39673591e+00f, -8.72120023e-01f, 1.84099555e+00f, -1.17961609e+00f, 6.02439523e-01f, -1.80175856e-01f, 7.94080496e-01f, + -6.74650550e-01f, 7.04131648e-02f, 1.20566392e+00f, 4.59349692e-01f, -1.56535909e-01f, -5.54040670e-01f, -6.36142433e-01f, -1.43642545e+00f, + -1.53930172e-01f, 2.08253980e+00f, 5.43519676e-01f, -4.00805354e-01f, 9.03731883e-01f, -1.57881069e+00f, -3.08827937e-01f, 5.61064541e-01f, +}; diff --git a/ggml/src/ggml-metal/turbo-wht.h b/ggml/src/ggml-metal/turbo-wht.h new file mode 100644 index 00000000000..68cdd90b2ae --- /dev/null +++ b/ggml/src/ggml-metal/turbo-wht.h @@ -0,0 +1,49 @@ +// TurboQuant Fast Walsh-Hadamard rotation for Metal +// Replaces 256KB dense matrices with 512 bytes of sign arrays + O(d log d) butterfly +// Generated with seed=42 (rotation) and seed=1042 (QJL) + +// --- Rotation sign arrays --- +constant float turbo_wht_signs1[128] = { + -1.0f, 1.0f, 1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, -1.0f, 1.0f, 1.0f, 1.0f, 1.0f, 1.0f, 1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, -1.0f, 1.0f, 1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, -1.0f, -1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, 1.0f, 1.0f, -1.0f, -1.0f, -1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, 1.0f, 1.0f, -1.0f, 1.0f, -1.0f, -1.0f, 1.0f, -1.0f, -1.0f, -1.0f, 1.0f, -1.0f, -1.0f, -1.0f, 1.0f, -1.0f, -1.0f, -1.0f, 1.0f, 1.0f, 1.0f, -1.0f, -1.0f, 1.0f, 1.0f, 1.0f, -1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, -1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, 1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, -1.0f, -1.0f, -1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f}; +constant float turbo_wht_signs2[128] = { + 1.0f, 1.0f, 1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, -1.0f, -1.0f, -1.0f, 1.0f, -1.0f, -1.0f, -1.0f, 1.0f, 1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, 1.0f, 1.0f, 1.0f, -1.0f, -1.0f, -1.0f, 1.0f, -1.0f, -1.0f, -1.0f, -1.0f, -1.0f, -1.0f, 1.0f, 1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, 1.0f, -1.0f, -1.0f, 1.0f, -1.0f, -1.0f, -1.0f, -1.0f, -1.0f, -1.0f, 1.0f, 1.0f, 1.0f, -1.0f, 1.0f, -1.0f, -1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, -1.0f, -1.0f, -1.0f, -1.0f, 1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, 1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, -1.0f, -1.0f, -1.0f, -1.0f, 1.0f, -1.0f}; + +// --- QJL sign arrays --- +constant float turbo_qjl_wht_signs1[128] = { + 1.0f, -1.0f, -1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, -1.0f, -1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, -1.0f, -1.0f, 1.0f, 1.0f, 1.0f, 1.0f, 1.0f, -1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, 1.0f, -1.0f, 1.0f, 1.0f, 1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, -1.0f, -1.0f, 1.0f, 1.0f, 1.0f, 1.0f, 1.0f, 1.0f, -1.0f, -1.0f, 1.0f, 1.0f, -1.0f, -1.0f, -1.0f, -1.0f, -1.0f, 1.0f, 1.0f, 1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, 1.0f, 1.0f, 1.0f, 1.0f, 1.0f, 1.0f, -1.0f, 1.0f, -1.0f, -1.0f, 1.0f, -1.0f, -1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, 1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, 1.0f, -1.0f, -1.0f, 1.0f, -1.0f, -1.0f, -1.0f, -1.0f, -1.0f, -1.0f, -1.0f}; +constant float turbo_qjl_wht_signs2[128] = { + 1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, -1.0f, 1.0f, 1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, 1.0f, -1.0f, 1.0f, -1.0f, -1.0f, -1.0f, -1.0f, 1.0f, 1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, -1.0f, -1.0f, -1.0f, -1.0f, 1.0f, 1.0f, 1.0f, 1.0f, 1.0f, 1.0f, 1.0f, 1.0f, 1.0f, -1.0f, -1.0f, 1.0f, 1.0f, 1.0f, 1.0f, 1.0f, 1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, -1.0f, -1.0f, 1.0f, 1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, 1.0f, 1.0f, 1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, -1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, 1.0f, -1.0f, 1.0f, 1.0f, 1.0f, -1.0f, 1.0f, 1.0f, 1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, 1.0f, 1.0f, -1.0f}; + +// --- Fast Walsh-Hadamard Transform (in-place, normalized) --- +// O(n log n) = 896 operations for n=128, vs O(n²) = 16384 for dense matvec +static void turbo_fwht_128(thread float * x) { + for (int h = 1; h < 128; h *= 2) { + for (int i = 0; i < 128; i += h * 2) { + for (int j = i; j < i + h; j++) { + float a = x[j]; + float b = x[j + h]; + x[j] = a + b; + x[j + h] = a - b; + } + } + } + // Normalize by 1/sqrt(128) + const float inv_sqrt_128 = 0.08838834764831845f; // 1/sqrt(128) + for (int i = 0; i < 128; i++) { + x[i] *= inv_sqrt_128; + } +} + +// --- Forward rotation: signs1 → FWHT → signs2 --- +static void turbo_rotate_forward(thread float * x, constant float * s1, constant float * s2) { + for (int i = 0; i < 128; i++) x[i] *= s1[i]; + turbo_fwht_128(x); + for (int i = 0; i < 128; i++) x[i] *= s2[i]; +} + +// --- Inverse rotation: signs2 → FWHT → signs1 (FWHT is its own inverse) --- +static void turbo_rotate_inverse(thread float * x, constant float * s1, constant float * s2) { + for (int i = 0; i < 128; i++) x[i] *= s2[i]; + turbo_fwht_128(x); + for (int i = 0; i < 128; i++) x[i] *= s1[i]; +} diff --git a/ggml/src/ggml-quants.c b/ggml/src/ggml-quants.c index 48695a61ea3..ade0568c87e 100644 --- a/ggml/src/ggml-quants.c +++ b/ggml/src/ggml-quants.c @@ -5405,6 +5405,14 @@ bool ggml_validate_row_data(enum ggml_type type, const void * data, size_t nbyte case GGML_TYPE_I64: // nothing to validate break; + case GGML_TYPE_TQ3_1S: + case GGML_TYPE_TQ4_1S: + case GGML_TYPE_TURBO3_0: + case GGML_TYPE_TURBO4_0: + case GGML_TYPE_TURBO2_0: + // WHT-rotated / TurboQuant types: just validate scales are not NaN/Inf + // TODO: add more thorough validation if needed + break; default: { fprintf(stderr, "%s: invalid type %d\n", __func__, type); diff --git a/ggml/src/ggml-quants.h b/ggml/src/ggml-quants.h index 00604f75c0e..457c7b66e7a 100644 --- a/ggml/src/ggml-quants.h +++ b/ggml/src/ggml-quants.h @@ -99,6 +99,27 @@ GGML_API size_t quantize_q8_0(const float * GGML_RESTRICT src, void * GGML_RESTR GGML_API size_t quantize_mxfp4(const float * GGML_RESTRICT src, void * GGML_RESTRICT dst, int64_t nrows, int64_t n_per_row, const float * imatrix); GGML_API size_t quantize_nvfp4(const float * GGML_RESTRICT src, void * GGML_RESTRICT dst, int64_t nrows, int64_t n_per_row, const float * imatrix); +// TurboQuant KV cache compression (arXiv 2504.19874) +GGML_API void quantize_row_turbo3_0_ref(const float * GGML_RESTRICT x, block_turbo3_0 * GGML_RESTRICT y, int64_t k); +GGML_API void quantize_row_turbo4_0_ref(const float * GGML_RESTRICT x, block_turbo4_0 * GGML_RESTRICT y, int64_t k); +GGML_API void dequantize_row_turbo3_0(const block_turbo3_0 * GGML_RESTRICT x, float * GGML_RESTRICT y, int64_t k); +GGML_API void dequantize_row_turbo4_0(const block_turbo4_0 * GGML_RESTRICT x, float * GGML_RESTRICT y, int64_t k); +GGML_API size_t quantize_turbo3_0(const float * GGML_RESTRICT src, void * GGML_RESTRICT dst, int64_t nrows, int64_t n_per_row, const float * imatrix); +GGML_API size_t quantize_turbo4_0(const float * GGML_RESTRICT src, void * GGML_RESTRICT dst, int64_t nrows, int64_t n_per_row, const float * imatrix); +GGML_API void quantize_row_turbo2_0_ref(const float * GGML_RESTRICT x, block_turbo2_0 * GGML_RESTRICT y, int64_t k); +GGML_API void dequantize_row_turbo2_0(const block_turbo2_0 * GGML_RESTRICT x, float * GGML_RESTRICT y, int64_t k); +GGML_API size_t quantize_turbo2_0(const float * GGML_RESTRICT src, void * GGML_RESTRICT dst, int64_t nrows, int64_t n_per_row, const float * imatrix); + +// TQ3_1S: WHT-rotated 3-bit weight quantization (8-level Lloyd-Max) +GGML_API void quantize_row_tq3_1s_ref(const float * GGML_RESTRICT x, block_tq3_1s * GGML_RESTRICT y, int64_t k); +GGML_API void dequantize_row_tq3_1s(const block_tq3_1s * GGML_RESTRICT x, float * GGML_RESTRICT y, int64_t k); +GGML_API size_t quantize_tq3_1s(const float * GGML_RESTRICT src, void * GGML_RESTRICT dst, int64_t nrows, int64_t n_per_row, const float * imatrix); + +// TQ4_1S: WHT-rotated 4-bit weight quantization (16-level Lloyd-Max) +GGML_API void quantize_row_tq4_1s_ref(const float * GGML_RESTRICT x, block_tq4_1s * GGML_RESTRICT y, int64_t k); +GGML_API void dequantize_row_tq4_1s(const block_tq4_1s * GGML_RESTRICT x, float * GGML_RESTRICT y, int64_t k); +GGML_API size_t quantize_tq4_1s(const float * GGML_RESTRICT src, void * GGML_RESTRICT dst, int64_t nrows, int64_t n_per_row, const float * imatrix); + GGML_API void iq2xs_init_impl(enum ggml_type type); GGML_API void iq2xs_free_impl(enum ggml_type type); GGML_API void iq3xs_init_impl(int grid_size); diff --git a/ggml/src/ggml-turbo-quant.c b/ggml/src/ggml-turbo-quant.c new file mode 100644 index 00000000000..9813756b310 --- /dev/null +++ b/ggml/src/ggml-turbo-quant.c @@ -0,0 +1,995 @@ +/* + * TurboQuant: KV cache compression via PolarQuant + QJL + * Based on: arXiv 2504.19874 (ICLR 2026) + * + * Implements GGML_TYPE_TURBO2_0 (2-bit), GGML_TYPE_TURBO3_0 (3-bit) and + * GGML_TYPE_TURBO4_0 (4-bit) for use as --cache-type-k turboN in llama-server. + */ + +#include "ggml-quants.h" +#include "ggml-common.h" +#include "ggml-impl.h" + +#define _USE_MATH_DEFINES +#include +#include +#include +#include + +#ifndef M_PI +#define M_PI 3.14159265358979323846 +#endif + +/* Global: WHT group size for CPU quantize path (set by CPU SET_ROWS handler) */ +GGML_API int turbo3_cpu_wht_group_size = 0; + +/* ---------- constants ---------- */ + +#define TURBO_SEED_ROTATION 42 +#define TURBO_SEED_QJL 1042 +#define TURBO_D 128 /* rotation group size = head_dim (independent of block size) */ +#define TURBO_QJL_CONST 1.2533141373155003f /* sqrt(pi/2) */ + +/* Optimal centroids from paper (scaled by 1/sqrt(d)) */ +/* 2-bit: {±0.453, ±1.51} / sqrt(d) */ +static const float CENTROIDS_2BIT[4] = { -0.133462f, -0.039994f, 0.039994f, 0.133462f }; + +/* 3-bit: Lloyd-Max for N(0, 1/128), pre-computed */ +static const float CENTROIDS_3BIT[8] = { + -0.190685f, -0.117832f, -0.065717f, -0.021460f, + 0.021460f, 0.065717f, 0.117832f, 0.190685f +}; + +/* ---------- rotation matrix (lazy init) ---------- */ + +static float turbo_rotation[TURBO_D * TURBO_D]; +static float turbo_rotation_t[TURBO_D * TURBO_D]; /* transpose */ +static int turbo_rotation_initialized = 0; + +/* Simple LCG PRNG for deterministic rotation generation */ +static uint64_t turbo_prng_state; + +static void turbo_prng_seed(uint64_t seed) { + turbo_prng_state = seed; +} + +static double turbo_prng_normal(void) { + /* Box-Muller transform from uniform LCG */ + turbo_prng_state = turbo_prng_state * 6364136223846793005ULL + 1442695040888963407ULL; + double u1 = (double)(turbo_prng_state >> 11) / (double)(1ULL << 53); + if (u1 < 1e-15) u1 = 1e-15; + turbo_prng_state = turbo_prng_state * 6364136223846793005ULL + 1442695040888963407ULL; + double u2 = (double)(turbo_prng_state >> 11) / (double)(1ULL << 53); + return sqrt(-2.0 * log(u1)) * cos(2.0 * M_PI * u2); +} + +static void turbo_init_rotation(void) { + if (turbo_rotation_initialized) return; + + const int d = TURBO_D; + + /* Generate random Gaussian matrix */ + turbo_prng_seed(TURBO_SEED_ROTATION); + float G[TURBO_D * TURBO_D]; + for (int i = 0; i < d * d; i++) { + G[i] = (float)turbo_prng_normal(); + } + + /* QR decomposition via modified Gram-Schmidt */ + /* Q stored column-major in turbo_rotation */ + memcpy(turbo_rotation, G, d * d * sizeof(float)); + + for (int j = 0; j < d; j++) { + /* Normalize column j */ + float norm = 0.0f; + for (int i = 0; i < d; i++) { + norm += turbo_rotation[i * d + j] * turbo_rotation[i * d + j]; + } + norm = sqrtf(norm); + if (norm > 1e-10f) { + for (int i = 0; i < d; i++) { + turbo_rotation[i * d + j] /= norm; + } + } + + /* Orthogonalize remaining columns against j */ + for (int k = j + 1; k < d; k++) { + float dot = 0.0f; + for (int i = 0; i < d; i++) { + dot += turbo_rotation[i * d + j] * turbo_rotation[i * d + k]; + } + for (int i = 0; i < d; i++) { + turbo_rotation[i * d + k] -= dot * turbo_rotation[i * d + j]; + } + } + } + + /* Compute transpose */ + for (int i = 0; i < d; i++) { + for (int j = 0; j < d; j++) { + turbo_rotation_t[i * d + j] = turbo_rotation[j * d + i]; + } + } + + turbo_rotation_initialized = 1; +} + +/* ---------- QJL projection matrix (lazy init, seed-based) ---------- */ + +static float turbo_qjl_matrix[TURBO_D * TURBO_D]; +static float turbo_qjl_matrix_t[TURBO_D * TURBO_D]; +static int turbo_qjl_initialized = 0; + +static void turbo_init_qjl(void) { + if (turbo_qjl_initialized) return; + + const int d = TURBO_D; + turbo_prng_seed(TURBO_SEED_QJL); + + for (int i = 0; i < d * d; i++) { + turbo_qjl_matrix[i] = (float)turbo_prng_normal(); + } + + /* Transpose */ + for (int i = 0; i < d; i++) { + for (int j = 0; j < d; j++) { + turbo_qjl_matrix_t[i * d + j] = turbo_qjl_matrix[j * d + i]; + } + } + + turbo_qjl_initialized = 1; +} + +/* ---------- helper: matrix-vector multiply ---------- */ + +static void matvec(const float * M, const float * x, float * y, int d) { + /* y = M @ x, M is row-major d×d */ + for (int i = 0; i < d; i++) { + float sum = 0.0f; + for (int j = 0; j < d; j++) { + sum += M[i * d + j] * x[j]; + } + y[i] = sum; + } +} + +/* ---------- nearest centroid ---------- */ + +static int nearest_centroid_2bit(float val) { + /* Binary search on midpoints: {-0.133, -0.040, 0.040, 0.133} */ + if (val < -0.086728f) return 0; /* midpoint(-0.133, -0.040) */ + if (val < 0.000000f) return 1; /* midpoint(-0.040, 0.040) */ + if (val < 0.086728f) return 2; /* midpoint(0.040, 0.133) */ + return 3; +} + +static int nearest_centroid_3bit(float val) { + /* 8 centroids, find nearest via midpoints */ + if (val < -0.154259f) return 0; + if (val < -0.091775f) return 1; + if (val < -0.043589f) return 2; + if (val < 0.000000f) return 3; + if (val < 0.043589f) return 4; + if (val < 0.091775f) return 5; + if (val < 0.154259f) return 6; + return 7; +} + +static int nearest_centroid_4bit(float val) { + /* 16 centroids, optimal for N(0, 1/sqrt(128)), find nearest via midpoints */ + if (val < -0.145560f) return 0; + if (val < -0.103361f) return 1; + if (val < -0.079142f) return 2; + if (val < -0.060009f) return 3; + if (val < -0.043430f) return 4; + if (val < -0.028293f) return 5; + if (val < -0.013963f) return 6; + if (val < 0.000000f) return 7; + if (val < 0.013963f) return 8; + if (val < 0.028293f) return 9; + if (val < 0.043430f) return 10; + if (val < 0.060009f) return 11; + if (val < 0.079142f) return 12; + if (val < 0.103361f) return 13; + if (val < 0.145560f) return 14; + return 15; +} + +/* ---------- WHT sign arrays (must match CUDA/Metal, seed=42) ---------- */ + +static const float turbo_cpu_s1[128] = { + -1,1,1,-1,-1,1,-1,1,-1,-1,1,1,1,1,1,1,1,-1,1,-1,1,-1,-1,1,1,1,-1,1,1,-1,-1,-1, + -1,1,1,-1,1,1,-1,1,-1,1,1,-1,-1,1,-1,1,1,1,1,-1,-1,-1,-1,-1,1,-1,1,1,1,1,-1,1, + -1,-1,1,-1,-1,-1,1,-1,-1,-1,1,-1,-1,-1,1,1,1,-1,-1,1,1,1,-1,-1,1,1,-1,1,1,-1,1,-1, + -1,1,1,-1,1,-1,1,-1,1,1,1,1,-1,1,-1,1,1,-1,1,1,-1,-1,-1,-1,-1,1,1,-1,1,1,-1,1 +}; + +static const float turbo_cpu_s2[128] = { + 1,1,1,1,-1,1,1,-1,1,-1,-1,-1,1,-1,-1,-1,1,1,-1,-1,1,-1,1,-1,1,-1,-1,1,-1,1,1,1, + 1,1,-1,-1,-1,1,-1,-1,-1,-1,-1,-1,1,1,1,-1,1,-1,1,1,1,-1,-1,1,-1,-1,-1,-1,-1,-1,1,1, + 1,-1,1,-1,-1,-1,-1,1,-1,1,-1,1,-1,-1,1,1,-1,1,-1,1,1,-1,1,-1,-1,-1,-1,1,-1,-1,1,-1, + 1,-1,1,1,1,-1,-1,1,-1,1,-1,1,1,-1,-1,1,-1,1,-1,1,1,-1,1,-1,1,-1,-1,-1,-1,-1,1,-1 +}; + +/* ---------- CPU forward WHT (in-place, group_size elements) ---------- */ + +static void turbo_cpu_fwht(float * x, int group_size) { + const float * s1 = turbo_cpu_s1; + const float * s2 = turbo_cpu_s2; + const float inv_sqrt = (group_size == 128) ? 0.08838834764831845f : 0.125f; + + // signs1 + for (int i = 0; i < group_size; i++) x[i] *= s1[i]; + + // butterfly stages + for (int h = 1; h < group_size; h *= 2) { + for (int i = 0; i < group_size; i += h * 2) { + for (int j = i; j < i + h; j++) { + float a = x[j], b = x[j + h]; + x[j] = a + b; + x[j + h] = a - b; + } + } + } + + // normalize + signs2 + for (int i = 0; i < group_size; i++) x[i] *= inv_sqrt * s2[i]; +} + +/* ---------- TURBO3_0: 3-bit PolarQuant with WHT rotation ---------- */ + +void quantize_row_turbo3_0_ref(const float * GGML_RESTRICT x, block_turbo3_0 * GGML_RESTRICT y, int64_t k) { + assert(k % QK_TURBO3 == 0); + + // Read WHT group size from global (set by CPU SET_ROWS handler before each call). + // Fallback: 128 if row is 128-aligned, else 64. + extern int turbo3_cpu_wht_group_size; + int group_size = turbo3_cpu_wht_group_size; + if (group_size != 64 && group_size != 128) { + group_size = (k % 128 == 0) ? 128 : 64; + } + if (k % group_size != 0) group_size = (group_size == 128) ? 64 : 128; + assert(k % group_size == 0); + + const int n_groups = k / group_size; + const int blocks_per_group = group_size / QK_TURBO3; + + for (int g = 0; g < n_groups; g++) { + const float * grp_src = x + g * group_size; + block_turbo3_0 * grp_dst = y + g * blocks_per_group; + + // 1. L2 norm over the group + float norm_sq = 0.0f; + float buf[128]; // max group_size + for (int j = 0; j < group_size; j++) { + buf[j] = grp_src[j]; + norm_sq += buf[j] * buf[j]; + } + float grp_norm = sqrtf(norm_sq); + float inv_norm = (grp_norm > 1e-10f) ? 1.0f / grp_norm : 0.0f; + + // 2. Normalize + for (int j = 0; j < group_size; j++) buf[j] *= inv_norm; + + // 3. Forward WHT rotation + turbo_cpu_fwht(buf, group_size); + + // 4. Quantize + pack into sub-blocks + float recon_sq = 0.0f; + for (int b = 0; b < blocks_per_group; b++) { + block_turbo3_0 * blk = &grp_dst[b]; + const int off = b * QK_TURBO3; + + memset(blk->qs, 0, QK_TURBO3 / 4); + memset(blk->signs, 0, QK_TURBO3 / 8); + + for (int j = 0; j < QK_TURBO3; j++) { + int idx = nearest_centroid_3bit(buf[off + j]); + blk->qs[j / 4] |= (idx & 0x3) << ((j % 4) * 2); + if (idx & 0x4) { + blk->signs[j / 8] |= (1 << (j % 8)); + } + recon_sq += CENTROIDS_3BIT[idx] * CENTROIDS_3BIT[idx]; + } + } + + // 5. Corrected norm: grp_norm / recon_norm (matching CUDA kernel) + float recon_norm = sqrtf(recon_sq); + float corrected = (recon_norm > 1e-10f) ? grp_norm / recon_norm : grp_norm; + for (int b = 0; b < blocks_per_group; b++) { + grp_dst[b].norm = GGML_FP32_TO_FP16(corrected); + } + } +} + +void dequantize_row_turbo3_0(const block_turbo3_0 * GGML_RESTRICT x, float * GGML_RESTRICT y, int64_t k) { + // Stub — Metal shader handles dequant on GPU. + assert(k % QK_TURBO3 == 0); + const int nb = k / QK_TURBO3; + for (int block = 0; block < nb; block++) { + float norm = GGML_FP16_TO_FP32(x[block].norm); + for (int j = 0; j < QK_TURBO3; j++) { + uint8_t low2 = (x[block].qs[j/4] >> ((j%4)*2)) & 0x3; + uint8_t hi1 = (x[block].signs[j/8] >> (j%8)) & 0x1; + uint8_t idx = low2 | (hi1 << 2); + y[block * QK_TURBO3 + j] = CENTROIDS_3BIT[idx] * norm; + } + } +} + +size_t quantize_turbo3_0(const float * GGML_RESTRICT src, void * GGML_RESTRICT dst, + int64_t nrows, int64_t n_per_row, const float * imatrix) { + GGML_UNUSED(imatrix); + assert(n_per_row % QK_TURBO3 == 0); + + size_t row_size = (n_per_row / QK_TURBO3) * sizeof(block_turbo3_0); + for (int64_t row = 0; row < nrows; row++) { + quantize_row_turbo3_0_ref( + src + row * n_per_row, + (block_turbo3_0 *)((char *)dst + row * row_size), + n_per_row + ); + } + return nrows * row_size; +} + +/* ---------- TURBO2_0: 2-bit PolarQuant (no QJL) ---------- */ + +void quantize_row_turbo2_0_ref(const float * GGML_RESTRICT x, block_turbo2_0 * GGML_RESTRICT y, int64_t k) { + assert(k % QK_TURBO2 == 0); + + extern int turbo3_cpu_wht_group_size; + int group_size = turbo3_cpu_wht_group_size; + if (group_size != 64 && group_size != 128) { + group_size = (k % 128 == 0) ? 128 : 64; + } + if (k % group_size != 0) group_size = (group_size == 128) ? 64 : 128; + assert(k % group_size == 0); + + const int n_groups = k / group_size; + const int blocks_per_group = group_size / QK_TURBO2; + + for (int g = 0; g < n_groups; g++) { + const float * grp_src = x + g * group_size; + block_turbo2_0 * grp_dst = y + g * blocks_per_group; + + /* 1. L2 norm over the group */ + float norm_sq = 0.0f; + float buf[128]; + for (int j = 0; j < group_size; j++) { + buf[j] = grp_src[j]; + norm_sq += buf[j] * buf[j]; + } + float grp_norm = sqrtf(norm_sq); + float inv_norm = (grp_norm > 1e-10f) ? 1.0f / grp_norm : 0.0f; + + /* 2. Normalize */ + for (int j = 0; j < group_size; j++) buf[j] *= inv_norm; + + /* 3. Forward WHT rotation */ + turbo_cpu_fwht(buf, group_size); + + /* 4. Quantize + pack into sub-blocks */ + float recon_sq = 0.0f; + for (int b = 0; b < blocks_per_group; b++) { + block_turbo2_0 * blk = &grp_dst[b]; + const int off = b * QK_TURBO2; + + memset(blk->qs, 0, QK_TURBO2 / 4); + + for (int j = 0; j < QK_TURBO2; j++) { + int idx = nearest_centroid_2bit(buf[off + j]); + blk->qs[j / 4] |= (idx & 0x3) << ((j % 4) * 2); + recon_sq += CENTROIDS_2BIT[idx] * CENTROIDS_2BIT[idx]; + } + } + + /* 5. Corrected norm */ + float recon_norm = sqrtf(recon_sq); + float corrected = (recon_norm > 1e-10f) ? grp_norm / recon_norm : grp_norm; + for (int b = 0; b < blocks_per_group; b++) { + grp_dst[b].norm = GGML_FP32_TO_FP16(corrected); + } + } +} + +void dequantize_row_turbo2_0(const block_turbo2_0 * GGML_RESTRICT x, float * GGML_RESTRICT y, int64_t k) { + assert(k % QK_TURBO2 == 0); + const int nb = k / QK_TURBO2; + for (int block = 0; block < nb; block++) { + float norm = GGML_FP16_TO_FP32(x[block].norm); + for (int j = 0; j < QK_TURBO2; j++) { + uint8_t idx = (x[block].qs[j/4] >> ((j%4)*2)) & 0x3; + y[block * QK_TURBO2 + j] = CENTROIDS_2BIT[idx] * norm; + } + } +} + +size_t quantize_turbo2_0(const float * GGML_RESTRICT src, void * GGML_RESTRICT dst, + int64_t nrows, int64_t n_per_row, const float * imatrix) { + GGML_UNUSED(imatrix); + assert(n_per_row % QK_TURBO2 == 0); + + size_t row_size = (n_per_row / QK_TURBO2) * sizeof(block_turbo2_0); + for (int64_t row = 0; row < nrows; row++) { + quantize_row_turbo2_0_ref( + src + row * n_per_row, + (block_turbo2_0 *)((char *)dst + row * row_size), + n_per_row + ); + } + return nrows * row_size; +} + +/* ---------- TURBO4_0: 3-bit PolarQuant + 1-bit QJL ---------- */ + +void quantize_row_turbo4_0_ref(const float * GGML_RESTRICT x, block_turbo4_0 * GGML_RESTRICT y, int64_t k) { + turbo_init_rotation(); + turbo_init_qjl(); + + assert(k % QK_TURBO4 == 0); + const int nb = k / QK_TURBO4; + const int d = QK_TURBO4; + + for (int block = 0; block < nb; block++) { + const float * src = x + block * d; + + /* Step 1: Extract norm */ + float norm_sq = 0.0f; + for (int i = 0; i < d; i++) norm_sq += src[i] * src[i]; + float norm = sqrtf(norm_sq); + + /* Normalize */ + float normalized[TURBO_D]; + if (norm > 1e-10f) { + const float inv = 1.0f / norm; + for (int i = 0; i < d; i++) normalized[i] = src[i] * inv; + } else { + memset(normalized, 0, d * sizeof(float)); + } + + /* Step 2: Forward WHT rotation (matches CUDA set_rows) */ + float rotated[TURBO_D]; + memcpy(rotated, normalized, d * sizeof(float)); + turbo_cpu_fwht(rotated, d); + +#if TURBO4_USE_4BIT + /* Step 3: 4-bit quantization (16 centroids) */ + static const float CENTROIDS_4BIT[16] = { + -0.173926f, -0.117195f, -0.089527f, -0.068756f, + -0.051262f, -0.035597f, -0.020989f, -0.006938f, + 0.006938f, 0.020989f, 0.035597f, 0.051262f, + 0.068756f, 0.089527f, 0.117195f, 0.173926f + }; + uint8_t indices[TURBO_D]; + for (int i = 0; i < d; i++) { + indices[i] = (uint8_t)nearest_centroid_4bit(rotated[i]); + } + + /* Norm correction */ + float recon_norm_sq = 0.0f; + for (int i = 0; i < d; i++) { + recon_norm_sq += CENTROIDS_4BIT[indices[i]] * CENTROIDS_4BIT[indices[i]]; + } + float recon_norm = sqrtf(recon_norm_sq); + float corrected_norm = (recon_norm > 1e-10f) ? norm / recon_norm : norm; + y[block].norm = GGML_FP32_TO_FP16(corrected_norm); +#else + /* Step 3: 3-bit quantization (8 centroids) */ + uint8_t indices[TURBO_D]; + for (int i = 0; i < d; i++) { + indices[i] = (uint8_t)nearest_centroid_3bit(rotated[i]); + } + + /* Step 4: Residual */ + float reconstructed[TURBO_D]; + for (int i = 0; i < d; i++) { + reconstructed[i] = CENTROIDS_3BIT[indices[i]]; + } + float mse_recon[TURBO_D]; + matvec(turbo_rotation_t, reconstructed, mse_recon, d); + + float residual[TURBO_D]; + for (int i = 0; i < d; i++) { + residual[i] = normalized[i] - mse_recon[i]; + } + + /* Step 5: QJL */ + float projected[TURBO_D]; + matvec(turbo_qjl_matrix, residual, projected, d); +#endif + + /* Pack */ +#if !TURBO4_USE_4BIT + y[block].norm = GGML_FP32_TO_FP16(norm); +#endif + +#if TURBO4_USE_4BIT + /* 4-bit PolarQuant: nibble pack into qs[64] */ + memset(y[block].qs, 0, d / 2); + for (int i = 0; i < d; i++) { + y[block].qs[i / 2] |= (uint8_t)((indices[i] & 0xF) << ((i % 2) * 4)); + } + y[block].rnorm = GGML_FP32_TO_FP16(0.0f); +#else + /* Legacy 3-bit + QJL: pack 3-bit indices + QJL signs */ + memset(y[block].qs, 0, d * 3 / 8); + for (int i = 0; i < d; i++) { + int bit_offset = i * 3; + int byte_idx = bit_offset / 8; + int bit_pos = bit_offset % 8; + uint16_t val = (uint16_t)(indices[i] & 0x7); + y[block].qs[byte_idx] |= (uint8_t)(val << bit_pos); + if (bit_pos > 5 && byte_idx + 1 < d * 3 / 8) { + y[block].qs[byte_idx + 1] |= (uint8_t)(val >> (8 - bit_pos)); + } + } + memset(y[block].signs, 0, d / 8); + for (int i = 0; i < d; i++) { + if (projected[i] >= 0.0f) { + y[block].signs[i / 8] |= (1 << (i % 8)); + } + } +#endif + } +} + +void dequantize_row_turbo4_0(const block_turbo4_0 * GGML_RESTRICT x, float * GGML_RESTRICT y, int64_t k) { + turbo_init_rotation(); + + assert(k % QK_TURBO4 == 0); + const int nb = k / QK_TURBO4; + const int d = QK_TURBO4; + +#if TURBO4_USE_4BIT + /* 4-bit PolarQuant: nibble unpack → centroid → inverse rotate → scale */ + /* TODO: add proper 4-bit centroid table to C code (currently only in Metal) */ + static const float CENTROIDS_4BIT[16] = { + -0.173926f, -0.117195f, -0.089527f, -0.068756f, + -0.051262f, -0.035597f, -0.020989f, -0.006938f, + 0.006938f, 0.020989f, 0.035597f, 0.051262f, + 0.068756f, 0.089527f, 0.117195f, 0.173926f + }; + for (int block = 0; block < nb; block++) { + float norm = GGML_FP16_TO_FP32(x[block].norm); + float * dst = y + block * d; + for (int i = 0; i < d; i++) { + uint8_t idx = (x[block].qs[i / 2] >> ((i % 2) * 4)) & 0xF; + dst[i] = CENTROIDS_4BIT[idx] * norm; + } + /* No inverse WHT, dequant stays in the rotated domain. + * Q is WHT-rotated by the graph, so gives correct attention scores. + * The inverse WHT is applied to the attention output via GGML_OP_TURBO_WHT (direction=1) in the graph. + */ + } +#else + /* Legacy 3-bit + QJL dequant */ + turbo_init_qjl(); + for (int block = 0; block < nb; block++) { + float norm = GGML_FP16_TO_FP32(x[block].norm); + + uint8_t indices[TURBO_D]; + for (int i = 0; i < d; i++) { + int bit_offset = i * 3; + int byte_idx = bit_offset / 8; + int bit_pos = bit_offset % 8; + uint16_t raw = (uint16_t)x[block].qs[byte_idx]; + if (byte_idx + 1 < d * 3 / 8) { + raw |= (uint16_t)x[block].qs[byte_idx + 1] << 8; + } + indices[i] = (uint8_t)((raw >> bit_pos) & 0x7); + } + + float signs[TURBO_D]; + for (int i = 0; i < d; i++) { + signs[i] = (x[block].signs[i / 8] & (1 << (i % 8))) ? 1.0f : -1.0f; + } + + float rnorm = GGML_FP16_TO_FP32(x[block].rnorm); + const float qjl_scale = TURBO_QJL_CONST / (float)d * rnorm; + + float rotated_recon[TURBO_D]; + for (int i = 0; i < d; i++) { + rotated_recon[i] = CENTROIDS_3BIT[indices[i]]; + } + float mse_recon[TURBO_D]; + matvec(turbo_rotation_t, rotated_recon, mse_recon, d); + + float qjl_recon[TURBO_D]; + matvec(turbo_qjl_matrix_t, signs, qjl_recon, d); + for (int i = 0; i < d; i++) { + qjl_recon[i] *= qjl_scale; + } + + float * dst = y + block * d; + for (int i = 0; i < d; i++) { + dst[i] = (mse_recon[i] + qjl_recon[i]) * norm; + } + } +#endif +} + +size_t quantize_turbo4_0(const float * GGML_RESTRICT src, void * GGML_RESTRICT dst, + int64_t nrows, int64_t n_per_row, const float * imatrix) { + GGML_UNUSED(imatrix); + assert(n_per_row % QK_TURBO4 == 0); + + size_t row_size = (n_per_row / QK_TURBO4) * sizeof(block_turbo4_0); + for (int64_t row = 0; row < nrows; row++) { + quantize_row_turbo4_0_ref( + src + row * n_per_row, + (block_turbo4_0 *)((char *)dst + row * row_size), + n_per_row + ); + } + return nrows * row_size; +} + +/* ================================================================== */ +/* TQ3_1S / TQ4_1S: WHT-rotated weight quantization */ +/* ================================================================== */ + +/* Lloyd-Max centroids for N(0,1) — shared with Metal shaders */ +static const float TQ3_0_CENTROIDS[8] = { + -1.996684f, -1.291398f, -0.740341f, -0.247508f, + 0.230106f, 0.725222f, 1.277503f, 1.988943f +}; + +static const float TQ4_0_CENTROIDS[16] = { + -2.732590f, -2.069017f, -1.618046f, -1.256231f, + -0.942340f, -0.656759f, -0.388048f, -0.128395f, + 0.128395f, 0.388048f, 0.656759f, 0.942340f, + 1.256231f, 1.618046f, 2.069017f, 2.732590f, +}; + +/* WHT sign pattern (golden ratio hash, 32-element blocks) — shared by TQ3 and TQ4 */ +static const float TQ3_0_SIGNS[32] = { + +1.0f, -1.0f, +1.0f, -1.0f, +1.0f, +1.0f, -1.0f, +1.0f, + -1.0f, -1.0f, +1.0f, -1.0f, +1.0f, +1.0f, -1.0f, +1.0f, + -1.0f, -1.0f, +1.0f, -1.0f, +1.0f, -1.0f, -1.0f, +1.0f, + -1.0f, +1.0f, +1.0f, -1.0f, +1.0f, -1.0f, -1.0f, +1.0f, +}; + +#define TQ_BLOCK_SIZE 32 +#define TQ_INV_SQRT32 0.17677669529663688f /* 1/sqrt(32) */ + +/* Forward RHT: sign flips -> WHT butterfly -> normalize */ +static void tq3_0_rht_forward(float * buf) { + for (int i = 0; i < TQ_BLOCK_SIZE; i++) buf[i] *= TQ3_0_SIGNS[i]; + for (int step = 1; step < TQ_BLOCK_SIZE; step <<= 1) { + for (int i = 0; i < TQ_BLOCK_SIZE; i += step << 1) { + for (int j = i; j < i + step; j++) { + float a = buf[j], b = buf[j + step]; + buf[j] = a + b; + buf[j + step] = a - b; + } + } + } + for (int i = 0; i < TQ_BLOCK_SIZE; i++) buf[i] *= TQ_INV_SQRT32; +} + +/* Inverse RHT: WHT butterfly -> normalize + unsign */ +static void tq3_0_rht_inverse(float * buf) { + for (int step = 1; step < TQ_BLOCK_SIZE; step <<= 1) { + for (int i = 0; i < TQ_BLOCK_SIZE; i += step << 1) { + for (int j = i; j < i + step; j++) { + float a = buf[j], b = buf[j + step]; + buf[j] = a + b; + buf[j + step] = a - b; + } + } + } + for (int i = 0; i < TQ_BLOCK_SIZE; i++) buf[i] *= TQ_INV_SQRT32 * TQ3_0_SIGNS[i]; +} + +/* Nearest centroid for TQ3 (8 centroids) */ +static int tq3_0_choose_index(float val) { + /* Binary search on midpoints of TQ3_0_CENTROIDS */ + if (val < -1.644041f) return 0; + if (val < -1.015870f) return 1; + if (val < -0.493925f) return 2; + if (val < -0.008701f) return 3; + if (val < 0.477664f) return 4; + if (val < 1.001363f) return 5; + if (val < 1.633223f) return 6; + return 7; +} + +/* Nearest centroid for TQ4 (16 centroids) */ +static int tq4_0_choose_index(float val) { + /* Binary search on midpoints of TQ4_0_CENTROIDS */ + if (val < -2.400804f) return 0; + if (val < -1.843532f) return 1; + if (val < -1.437139f) return 2; + if (val < -1.099286f) return 3; + if (val < -0.799550f) return 4; + if (val < -0.522404f) return 5; + if (val < -0.258222f) return 6; + if (val < 0.000000f) return 7; + if (val < 0.258222f) return 8; + if (val < 0.522404f) return 9; + if (val < 0.799550f) return 10; + if (val < 1.099286f) return 11; + if (val < 1.437139f) return 12; + if (val < 1.843532f) return 13; + if (val < 2.400804f) return 14; + return 15; +} + +/* ---------- TQ3_1S quantization ---------- */ + +void quantize_row_tq3_1s_ref(const float * GGML_RESTRICT x, block_tq3_1s * GGML_RESTRICT y, int64_t k) { + assert(k % QK_TQ3_0 == 0); + const int nb = k / QK_TQ3_0; + + for (int block = 0; block < nb; block++) { + const float * src_blk = x + block * QK_TQ3_0; + block_tq3_1s * blk = &y[block]; + + /* 1. Forward RHT */ + float buf[TQ_BLOCK_SIZE]; + memcpy(buf, src_blk, TQ_BLOCK_SIZE * sizeof(float)); + tq3_0_rht_forward(buf); + + /* 2. Split into two halves, compute RMS per half */ + float rms0 = 0.0f, rms1 = 0.0f; + for (int j = 0; j < 16; j++) rms0 += buf[j] * buf[j]; + for (int j = 16; j < 32; j++) rms1 += buf[j] * buf[j]; + rms0 = sqrtf(rms0 / 16.0f); + rms1 = sqrtf(rms1 / 16.0f); + + /* 3. Scale search (9 points) */ + static const float scales[] = { 0.6f, 0.7f, 0.8f, 0.9f, 1.0f, 1.1f, 1.2f, 1.35f, 1.5f }; + float best_d0 = rms0, best_d1 = rms1; + float best_err = 1e30f; + + for (int si = 0; si < 9; si++) { + float d0 = rms0 * scales[si]; + float d1 = rms1 * scales[si]; + float inv0 = (d0 > 1e-10f) ? 1.0f / d0 : 0.0f; + float inv1 = (d1 > 1e-10f) ? 1.0f / d1 : 0.0f; + + float err = 0.0f; + for (int j = 0; j < 16; j++) { + int idx = tq3_0_choose_index(buf[j] * inv0); + float diff = buf[j] - TQ3_0_CENTROIDS[idx] * d0; + err += diff * diff; + } + for (int j = 16; j < 32; j++) { + int idx = tq3_0_choose_index(buf[j] * inv1); + float diff = buf[j] - TQ3_0_CENTROIDS[idx] * d1; + err += diff * diff; + } + if (err < best_err) { + best_err = err; + best_d0 = d0; + best_d1 = d1; + } + } + + /* 4. Iterative refinement (6 iterations) */ + for (int iter = 0; iter < 6; iter++) { + float inv0 = (best_d0 > 1e-10f) ? 1.0f / best_d0 : 0.0f; + float inv1 = (best_d1 > 1e-10f) ? 1.0f / best_d1 : 0.0f; + + float num0 = 0.0f, den0 = 0.0f; + float num1 = 0.0f, den1 = 0.0f; + for (int j = 0; j < 16; j++) { + int idx = tq3_0_choose_index(buf[j] * inv0); + float c = TQ3_0_CENTROIDS[idx]; + num0 += buf[j] * c; + den0 += c * c; + } + for (int j = 16; j < 32; j++) { + int idx = tq3_0_choose_index(buf[j] * inv1); + float c = TQ3_0_CENTROIDS[idx]; + num1 += buf[j] * c; + den1 += c * c; + } + if (den0 > 1e-10f) best_d0 = num0 / den0; + if (den1 > 1e-10f) best_d1 = num1 / den1; + } + + /* 5. Final quantize + pack */ + float inv0 = (best_d0 > 1e-10f) ? 1.0f / best_d0 : 0.0f; + float inv1 = (best_d1 > 1e-10f) ? 1.0f / best_d1 : 0.0f; + + blk->d0 = GGML_FP32_TO_FP16(best_d0); + blk->d1 = GGML_FP32_TO_FP16(best_d1); + memset(blk->qs, 0, QK_TQ3_0 * 3 / 8); + + /* TQ3 packing: 4 groups of 8 indices packed into 3 bytes each */ + for (int g = 0; g < 4; g++) { + uint8_t indices[8]; + for (int i = 0; i < 8; i++) { + int j = g * 8 + i; + float inv = (j < 16) ? inv0 : inv1; + indices[i] = (uint8_t)tq3_0_choose_index(buf[j] * inv); + } + uint8_t * qp = blk->qs + g * 3; + qp[0] = (indices[0] & 7) | ((indices[1] & 7) << 3) | ((indices[2] & 3) << 6); + qp[1] = ((indices[2] >> 2) & 1) | ((indices[3] & 7) << 1) | ((indices[4] & 7) << 4) | ((indices[5] & 1) << 7); + qp[2] = ((indices[5] >> 1) & 3) | ((indices[6] & 7) << 2) | ((indices[7] & 7) << 5); + } + } +} + +void dequantize_row_tq3_1s(const block_tq3_1s * GGML_RESTRICT x, float * GGML_RESTRICT y, int64_t k) { + assert(k % QK_TQ3_0 == 0); + const int nb = k / QK_TQ3_0; + + for (int blk_i = 0; blk_i < nb; blk_i++) { + float d0 = GGML_FP16_TO_FP32(x[blk_i].d0); + float d1 = GGML_FP16_TO_FP32(x[blk_i].d1); + + /* Unpack 3-bit indices */ + float buf[32]; + for (int g = 0; g < 4; g++) { + const uint8_t * qp = x[blk_i].qs + g * 3; + uint8_t idx[8]; + idx[0] = qp[0] & 7; + idx[1] = (qp[0] >> 3) & 7; + idx[2] = ((qp[0] >> 6) | (qp[1] << 2)) & 7; + idx[3] = (qp[1] >> 1) & 7; + idx[4] = (qp[1] >> 4) & 7; + idx[5] = ((qp[1] >> 7) | (qp[2] << 1)) & 7; + idx[6] = (qp[2] >> 2) & 7; + idx[7] = (qp[2] >> 5) & 7; + + for (int i = 0; i < 8; i++) { + int j = g * 8 + i; + float d = (j < 16) ? d0 : d1; + buf[j] = TQ3_0_CENTROIDS[idx[i]] * d; + } + } + + /* Inverse RHT */ + tq3_0_rht_inverse(buf); + + memcpy(y + blk_i * QK_TQ3_0, buf, QK_TQ3_0 * sizeof(float)); + } +} + +size_t quantize_tq3_1s(const float * GGML_RESTRICT src, void * GGML_RESTRICT dst, + int64_t nrows, int64_t n_per_row, const float * imatrix) { + GGML_UNUSED(imatrix); + assert(n_per_row % QK_TQ3_0 == 0); + + size_t row_size = (n_per_row / QK_TQ3_0) * sizeof(block_tq3_1s); + for (int64_t row = 0; row < nrows; row++) { + quantize_row_tq3_1s_ref( + src + row * n_per_row, + (block_tq3_1s *)((char *)dst + row * row_size), + n_per_row + ); + } + return nrows * row_size; +} + +/* ---------- TQ4_1S quantization ---------- */ + +void quantize_row_tq4_1s_ref(const float * GGML_RESTRICT x, block_tq4_1s * GGML_RESTRICT y, int64_t k) { + assert(k % QK_TQ4_1S == 0); + const int nb = k / QK_TQ4_1S; + + for (int block = 0; block < nb; block++) { + const float * src_blk = x + block * QK_TQ4_1S; + block_tq4_1s * blk = &y[block]; + + /* 1. Forward RHT */ + float buf[TQ_BLOCK_SIZE]; + memcpy(buf, src_blk, TQ_BLOCK_SIZE * sizeof(float)); + tq3_0_rht_forward(buf); + + /* 2. Split into two halves, compute RMS per half */ + float rms0 = 0.0f, rms1 = 0.0f; + for (int j = 0; j < 16; j++) rms0 += buf[j] * buf[j]; + for (int j = 16; j < 32; j++) rms1 += buf[j] * buf[j]; + rms0 = sqrtf(rms0 / 16.0f); + rms1 = sqrtf(rms1 / 16.0f); + + /* 3. Scale search (9 points) */ + static const float scales[] = { 0.6f, 0.7f, 0.8f, 0.9f, 1.0f, 1.1f, 1.2f, 1.35f, 1.5f }; + float best_d0 = rms0, best_d1 = rms1; + float best_err = 1e30f; + + for (int si = 0; si < 9; si++) { + float d0 = rms0 * scales[si]; + float d1 = rms1 * scales[si]; + float inv0 = (d0 > 1e-10f) ? 1.0f / d0 : 0.0f; + float inv1 = (d1 > 1e-10f) ? 1.0f / d1 : 0.0f; + + float err = 0.0f; + for (int j = 0; j < 16; j++) { + int idx = tq4_0_choose_index(buf[j] * inv0); + float diff = buf[j] - TQ4_0_CENTROIDS[idx] * d0; + err += diff * diff; + } + for (int j = 16; j < 32; j++) { + int idx = tq4_0_choose_index(buf[j] * inv1); + float diff = buf[j] - TQ4_0_CENTROIDS[idx] * d1; + err += diff * diff; + } + if (err < best_err) { + best_err = err; + best_d0 = d0; + best_d1 = d1; + } + } + + /* 4. Iterative refinement (6 iterations) */ + for (int iter = 0; iter < 6; iter++) { + float inv0 = (best_d0 > 1e-10f) ? 1.0f / best_d0 : 0.0f; + float inv1 = (best_d1 > 1e-10f) ? 1.0f / best_d1 : 0.0f; + + float num0 = 0.0f, den0 = 0.0f; + float num1 = 0.0f, den1 = 0.0f; + for (int j = 0; j < 16; j++) { + int idx = tq4_0_choose_index(buf[j] * inv0); + float c = TQ4_0_CENTROIDS[idx]; + num0 += buf[j] * c; + den0 += c * c; + } + for (int j = 16; j < 32; j++) { + int idx = tq4_0_choose_index(buf[j] * inv1); + float c = TQ4_0_CENTROIDS[idx]; + num1 += buf[j] * c; + den1 += c * c; + } + if (den0 > 1e-10f) best_d0 = num0 / den0; + if (den1 > 1e-10f) best_d1 = num1 / den1; + } + + /* 5. Final quantize + pack (nibble packing) */ + float inv0 = (best_d0 > 1e-10f) ? 1.0f / best_d0 : 0.0f; + float inv1 = (best_d1 > 1e-10f) ? 1.0f / best_d1 : 0.0f; + + blk->d0 = GGML_FP32_TO_FP16(best_d0); + blk->d1 = GGML_FP32_TO_FP16(best_d1); + memset(blk->qs, 0, QK_TQ4_1S / 2); + + for (int j = 0; j < QK_TQ4_1S; j++) { + float inv = (j < 16) ? inv0 : inv1; + int idx = tq4_0_choose_index(buf[j] * inv); + blk->qs[j / 2] |= (uint8_t)((idx & 0xF) << ((j & 1) * 4)); + } + } +} + +void dequantize_row_tq4_1s(const block_tq4_1s * GGML_RESTRICT x, float * GGML_RESTRICT y, int64_t k) { + assert(k % QK_TQ4_1S == 0); + const int nb = k / QK_TQ4_1S; + + for (int blk_i = 0; blk_i < nb; blk_i++) { + float d0 = GGML_FP16_TO_FP32(x[blk_i].d0); + float d1 = GGML_FP16_TO_FP32(x[blk_i].d1); + + float buf[32]; + for (int j = 0; j < 32; j++) { + uint8_t idx = (x[blk_i].qs[j / 2] >> ((j & 1) * 4)) & 0xF; + float d = (j < 16) ? d0 : d1; + buf[j] = TQ4_0_CENTROIDS[idx] * d; + } + + /* Inverse RHT */ + tq3_0_rht_inverse(buf); + + memcpy(y + blk_i * QK_TQ4_1S, buf, QK_TQ4_1S * sizeof(float)); + } +} + +size_t quantize_tq4_1s(const float * GGML_RESTRICT src, void * GGML_RESTRICT dst, + int64_t nrows, int64_t n_per_row, const float * imatrix) { + GGML_UNUSED(imatrix); + assert(n_per_row % QK_TQ4_1S == 0); + + size_t row_size = (n_per_row / QK_TQ4_1S) * sizeof(block_tq4_1s); + for (int64_t row = 0; row < nrows; row++) { + quantize_row_tq4_1s_ref( + src + row * n_per_row, + (block_tq4_1s *)((char *)dst + row * row_size), + n_per_row + ); + } + return nrows * row_size; +} diff --git a/ggml/src/ggml.c b/ggml/src/ggml.c index e9b6720c0af..87b447a030a 100644 --- a/ggml/src/ggml.c +++ b/ggml/src/ggml.c @@ -726,6 +726,46 @@ static const struct ggml_type_traits type_traits[GGML_TYPE_COUNT] = { .to_float = (ggml_to_float_t) dequantize_row_nvfp4, .from_float_ref = (ggml_from_float_t)quantize_row_nvfp4_ref, }, + [GGML_TYPE_TURBO3_0] = { + .type_name = "turbo3", + .blck_size = QK_TURBO3, + .type_size = sizeof(block_turbo3_0), + .is_quantized = true, + .to_float = (ggml_to_float_t) dequantize_row_turbo3_0, + .from_float_ref = (ggml_from_float_t) quantize_row_turbo3_0_ref, + }, + [GGML_TYPE_TURBO4_0] = { + .type_name = "turbo4", + .blck_size = QK_TURBO4, + .type_size = sizeof(block_turbo4_0), + .is_quantized = true, + .to_float = (ggml_to_float_t) dequantize_row_turbo4_0, + .from_float_ref = (ggml_from_float_t) quantize_row_turbo4_0_ref, + }, + [GGML_TYPE_TURBO2_0] = { + .type_name = "turbo2", + .blck_size = QK_TURBO2, + .type_size = sizeof(block_turbo2_0), + .is_quantized = true, + .to_float = (ggml_to_float_t) dequantize_row_turbo2_0, + .from_float_ref = (ggml_from_float_t) quantize_row_turbo2_0_ref, + }, + [GGML_TYPE_TQ3_1S] = { + .type_name = "tq3_1s", + .blck_size = QK_TQ3_0, + .type_size = sizeof(block_tq3_1s), + .is_quantized = true, + .to_float = (ggml_to_float_t) dequantize_row_tq3_1s, + .from_float_ref = (ggml_from_float_t) quantize_row_tq3_1s_ref, + }, + [GGML_TYPE_TQ4_1S] = { + .type_name = "tq4_1s", + .blck_size = QK_TQ4_1S, + .type_size = sizeof(block_tq4_1s), + .is_quantized = true, + .to_float = (ggml_to_float_t) dequantize_row_tq4_1s, + .from_float_ref = (ggml_from_float_t) quantize_row_tq4_1s_ref, + }, [GGML_TYPE_Q2_K] = { .type_name = "q2_K", .blck_size = QK_K, @@ -1040,6 +1080,7 @@ static const char * GGML_OP_NAME[GGML_OP_COUNT] = { "RWKV_WKV7", "SOLVE_TRI", "GATED_DELTA_NET", + "TURBO_WHT", "UNARY", @@ -1057,7 +1098,7 @@ static const char * GGML_OP_NAME[GGML_OP_COUNT] = { "GLU", }; -static_assert(GGML_OP_COUNT == 96, "GGML_OP_COUNT != 96"); +static_assert(GGML_OP_COUNT == 97, "GGML_OP_COUNT != 97"); static const char * GGML_OP_SYMBOL[GGML_OP_COUNT] = { "none", @@ -1150,6 +1191,7 @@ static const char * GGML_OP_SYMBOL[GGML_OP_COUNT] = { "rwkv_wkv7(r, w, k, v, a, b, s)", "A X = B, A triangular, solve X", "gated_delta_net(q, k, v, g, beta, s)", + "turbo_wht(a)", "unary(x)", @@ -1167,7 +1209,7 @@ static const char * GGML_OP_SYMBOL[GGML_OP_COUNT] = { "glu(x)", }; -static_assert(GGML_OP_COUNT == 96, "GGML_OP_COUNT != 96"); +static_assert(GGML_OP_COUNT == 97, "GGML_OP_COUNT != 97"); static_assert(GGML_OP_POOL_COUNT == 2, "GGML_OP_POOL_COUNT != 2"); @@ -6194,6 +6236,38 @@ struct ggml_tensor * ggml_gated_delta_net( return result; } +// ggml_turbo_wht + +struct ggml_tensor * ggml_turbo_wht( + struct ggml_context * ctx, + struct ggml_tensor * a, + int direction, + int group_size, + struct ggml_tensor * scale) { + GGML_ASSERT(ggml_is_contiguous(a)); + GGML_ASSERT(a->type == GGML_TYPE_F32); + GGML_ASSERT(direction == 0 || direction == 1); + + // Auto-detect group size from tensor dimension if not specified + if (group_size == 0) { + group_size = (a->ne[0] % 128 == 0) ? 128 : 64; + } + GGML_ASSERT(group_size == 32 || group_size == 64 || group_size == 128); + GGML_ASSERT(a->ne[0] % group_size == 0); + + struct ggml_tensor * result = ggml_new_tensor(ctx, GGML_TYPE_F32, 4, a->ne); + + result->op = GGML_OP_TURBO_WHT; + result->src[0] = a; + result->src[1] = scale; // InnerQ scale_inv (NULL = no scaling) + + // Store direction and group_size in op_params + memcpy(result->op_params + 0, &direction, sizeof(int)); + memcpy(result->op_params + sizeof(int), &group_size, sizeof(int)); + + return result; +} + //////////////////////////////////////////////////////////////////////////////// struct ggml_hash_set ggml_hash_set_new(size_t size) { @@ -7675,6 +7749,11 @@ size_t ggml_quantize_chunk( case GGML_TYPE_IQ1_M: result = quantize_iq1_m (src + start, (char *) dst + start_row * row_size, nrows, n_per_row, imatrix); break; case GGML_TYPE_IQ4_NL: result = quantize_iq4_nl (src + start, (char *) dst + start_row * row_size, nrows, n_per_row, imatrix); break; case GGML_TYPE_IQ4_XS: result = quantize_iq4_xs (src + start, (char *) dst + start_row * row_size, nrows, n_per_row, imatrix); break; + case GGML_TYPE_TURBO3_0: result = quantize_turbo3_0(src + start, (char *) dst + start_row * row_size, nrows, n_per_row, imatrix); break; + case GGML_TYPE_TURBO4_0: result = quantize_turbo4_0(src + start, (char *) dst + start_row * row_size, nrows, n_per_row, imatrix); break; + case GGML_TYPE_TURBO2_0: result = quantize_turbo2_0(src + start, (char *) dst + start_row * row_size, nrows, n_per_row, imatrix); break; + case GGML_TYPE_TQ3_1S: result = quantize_tq3_1s(src + start, (char *) dst + start_row * row_size, nrows, n_per_row, imatrix); break; + case GGML_TYPE_TQ4_1S: result = quantize_tq4_1s(src + start, (char *) dst + start_row * row_size, nrows, n_per_row, imatrix); break; case GGML_TYPE_F16: { size_t elemsize = sizeof(ggml_fp16_t); diff --git a/include/llama.h b/include/llama.h index a940f9d648a..c7d3d4dbf16 100644 --- a/include/llama.h +++ b/include/llama.h @@ -154,6 +154,8 @@ extern "C" { LLAMA_FTYPE_MOSTLY_TQ2_0 = 37, // except 1d tensors LLAMA_FTYPE_MOSTLY_MXFP4_MOE = 38, // except 1d tensors LLAMA_FTYPE_MOSTLY_NVFP4 = 39, // except 1d tensors + LLAMA_FTYPE_MOSTLY_TQ3_1S = 43, // except 1d tensors + LLAMA_FTYPE_MOSTLY_TQ4_1S = 44, // except 1d tensors LLAMA_FTYPE_GUESSED = 1024, // not specified in the model file }; diff --git a/scripts/bench-smem-m5.sh b/scripts/bench-smem-m5.sh new file mode 100755 index 00000000000..9916af6f11e --- /dev/null +++ b/scripts/bench-smem-m5.sh @@ -0,0 +1,58 @@ +#!/bin/bash +# SMEM Pre-Dequant Benchmark — M5 Max +# Tests SMEM vs baseline at multiple context depths +# +# BEFORE RUNNING: +# 1. cd /Users/tom/local_llms/llama.cpp +# 2. git checkout experiment/smem-pre-dequant +# 3. Build WITHOUT SMEM first (baseline): +# cmake --build build -j12 +# 4. Run: ./scripts/bench-smem-m5.sh baseline +# 5. Build WITH SMEM: +# TURBO_SMEM_DEQUANT=1 cmake --build build -j12 +# 6. Run: ./scripts/bench-smem-m5.sh smem +# +# Uses Qwen3.5-35B-A3B (MoE, fits in memory, attention-heavy) + +set -e + +LABEL="${1:-baseline}" +LLAMA_BENCH="/Users/tom/local_llms/llama.cpp/build/bin/llama-bench" +MODEL="/Users/tom/local_llms/models/Qwen3.5-35B-A3B-Q8_0.gguf" +OUTFILE="/Users/tom/local_llms/llama.cpp/bench-smem-m5-${LABEL}.txt" + +CONTEXTS=(0 8192 16384 32768) +KV_TYPES=("turbo3" "turbo4" "q8_0") + +echo "=== SMEM M5 Benchmark: ${LABEL} ===" | tee "$OUTFILE" +echo "Model: $(basename $MODEL)" | tee -a "$OUTFILE" +echo "Date: $(date)" | tee -a "$OUTFILE" +echo "" | tee -a "$OUTFILE" + +for ctk in "${KV_TYPES[@]}"; do + for p in "${CONTEXTS[@]}"; do + if [[ "$ctk" == "q8_0" && "$LABEL" == "smem" ]]; then + echo "SKIP: q8_0 + smem (q8_0 unaffected by SMEM)" | tee -a "$OUTFILE" + continue + fi + + depth_label="short" + [[ $p -gt 0 ]] && depth_label="${p}" + + echo "--- ${ctk} @ ${depth_label} ---" | tee -a "$OUTFILE" + + ctv="$ctk" + $LLAMA_BENCH \ + -m "$MODEL" \ + -ngl 99 -fa 1 \ + -ctk "$ctk" -ctv "$ctv" \ + -t 1 \ + -p "$p" -n 128 \ + 2>&1 | tee -a "$OUTFILE" + + echo "" | tee -a "$OUTFILE" + done +done + +echo "=== Done: ${LABEL} ===" | tee -a "$OUTFILE" +echo "Results saved to: $OUTFILE" diff --git a/scripts/turbo-quality-gate.sh b/scripts/turbo-quality-gate.sh new file mode 100755 index 00000000000..4fc3427c33a --- /dev/null +++ b/scripts/turbo-quality-gate.sh @@ -0,0 +1,80 @@ +#!/bin/bash +# TurboQuant quality + speed gate — run BEFORE pushing any changes +# Checks: (1) perplexity within 5% of q8_0, (2) context scaling ratio > 0.95 +# +# Usage: bash scripts/turbo-quality-gate.sh +# Exit 0 = PASS, Exit 1 = FAIL + +set -e + +LLAMA=${LLAMA:-~/local_llms/llama.cpp/build-turbo/bin} +MODEL=${MODEL:-~/local_llms/models/Qwen3.5-35B-A3B-Q8_0.gguf} +WIKI=${WIKI:-~/local_llms/llama.cpp/wikitext-2-raw/wiki.test.raw} + +if [ ! -f "$WIKI" ]; then + echo "Downloading wikitext-2..." + bash ~/local_llms/llama.cpp/scripts/get-wikitext-2.sh +fi + +FAIL=0 + +echo "========================================" +echo " TurboQuant Quality + Speed Gate" +echo "========================================" +echo "" + +# --- Test 1: Perplexity --- +echo "[1/2] Running perplexity check (8 chunks)..." +PPL_TURBO=$($LLAMA/llama-perplexity -m $MODEL -f $WIKI -c 512 -ctk turbo3 -ctv turbo3 -fa on --chunks 8 -ngl 99 2>&1 | grep "Final" | grep -oE 'PPL = [0-9.]+' | grep -oE '[0-9.]+') + +if [ -z "$PPL_TURBO" ]; then + echo " FAIL: Could not get turbo3 perplexity (crash or timeout)" + FAIL=1 +else + BASELINE_PPL=6.111 + MAX_PPL=$(echo "$BASELINE_PPL * 1.05" | bc) + PPL_OK=$(echo "$PPL_TURBO < $MAX_PPL" | bc) + if [ "$PPL_OK" -eq 1 ]; then + echo " PASS: turbo3 PPL = $PPL_TURBO (< $MAX_PPL, within 5% of q8_0 $BASELINE_PPL)" + else + echo " FAIL: turbo3 PPL = $PPL_TURBO (> $MAX_PPL, exceeds 5% threshold)" + FAIL=1 + fi +fi +echo "" + +# --- Test 2: Context Scaling --- +echo "[2/2] Running context scaling check (4K prefill)..." +TURBO_TPS=$($LLAMA/llama-perplexity -m $MODEL -f $WIKI -c 4096 -ctk turbo3 -ctv turbo3 -fa on --chunks 4 -ngl 99 2>&1 | grep "prompt eval" | grep -oE '[0-9.]+ tokens per second' | grep -oE '[0-9.]+') +Q8_TPS=$($LLAMA/llama-perplexity -m $MODEL -f $WIKI -c 4096 -ctk q8_0 -ctv q8_0 -fa on --chunks 4 -ngl 99 2>&1 | grep "prompt eval" | grep -oE '[0-9.]+ tokens per second' | grep -oE '[0-9.]+') + +if [ -z "$TURBO_TPS" ] || [ -z "$Q8_TPS" ]; then + echo " FAIL: Could not measure speed (crash or timeout)" + echo " turbo3=$TURBO_TPS q8_0=$Q8_TPS" + FAIL=1 +else + RATIO=$(echo "scale=4; $TURBO_TPS / $Q8_TPS" | bc) + RATIO_OK=$(echo "$RATIO > 0.95" | bc) + if [ "$RATIO_OK" -eq 1 ]; then + echo " PASS: turbo3/q8_0 = ${RATIO}x at 4K context (> 0.95 threshold)" + echo " turbo3 = $TURBO_TPS tok/s, q8_0 = $Q8_TPS tok/s" + else + echo " FAIL: turbo3/q8_0 = ${RATIO}x at 4K context (< 0.95 threshold)" + echo " turbo3 = $TURBO_TPS tok/s, q8_0 = $Q8_TPS tok/s" + echo " Context scaling regression detected!" + FAIL=1 + fi +fi +echo "" + +# --- Summary --- +echo "========================================" +if [ "$FAIL" -eq 0 ]; then + echo " ALL CHECKS PASSED" + echo "========================================" + exit 0 +else + echo " CHECKS FAILED — DO NOT PUSH" + echo "========================================" + exit 1 +fi diff --git a/src/llama-context.cpp b/src/llama-context.cpp index a808e3e4542..e0f4957b350 100644 --- a/src/llama-context.cpp +++ b/src/llama-context.cpp @@ -2944,8 +2944,16 @@ llama_context * llama_init_from_model( if (params.flash_attn_type == LLAMA_FLASH_ATTN_TYPE_AUTO && ggml_is_quantized(params.type_k)) { const uint32_t blck_size = ggml_blck_size(params.type_k); + const bool k_is_turbo = (params.type_k == GGML_TYPE_TURBO2_0 || + params.type_k == GGML_TYPE_TURBO3_0 || + params.type_k == GGML_TYPE_TURBO4_0); for (uint32_t il = 0; il < model->hparams.n_layer; ++il) { - if (model->hparams.n_embd_head_k(il) % blck_size != 0) { + uint32_t head_k = model->hparams.n_embd_head_k(il); + // Turbo types zero-pad heads to next multiple of 128 in llama-kv-cache.cpp + if (k_is_turbo && head_k % 128 != 0) { + head_k = ((head_k + 127) / 128) * 128; + } + if (head_k % blck_size != 0) { LLAMA_LOG_ERROR("%s: K cache type %s with block size %u does not divide n_embd_head_k=%u\n", __func__, ggml_type_name(params.type_k), blck_size, model->hparams.n_embd_head_k(il)); return nullptr; @@ -2955,8 +2963,17 @@ llama_context * llama_init_from_model( if (params.flash_attn_type == LLAMA_FLASH_ATTN_TYPE_AUTO && ggml_is_quantized(params.type_v)) { const uint32_t blck_size = ggml_blck_size(params.type_v); + const bool v_is_turbo = (params.type_v == GGML_TYPE_TURBO2_0 || + params.type_v == GGML_TYPE_TURBO3_0 || + params.type_v == GGML_TYPE_TURBO4_0); + const bool is_mla = model->hparams.is_mla(); for (uint32_t il = 0; il < model->hparams.n_layer; ++il) { - if (model->hparams.n_embd_head_v(il) % blck_size != 0) { + uint32_t head_v = model->hparams.n_embd_head_v(il); + // Turbo types zero-pad; MLA has no separate V cache (V = view of K) + if (v_is_turbo && !is_mla && head_v % 128 != 0) { + head_v = ((head_v + 127) / 128) * 128; + } + if (head_v % blck_size != 0) { LLAMA_LOG_ERROR("%s: V cache type %s with block size %u does not divide n_embd_head_v=%u\n", __func__, ggml_type_name(params.type_v), blck_size, model->hparams.n_embd_head_v(il)); return nullptr; @@ -2964,6 +2981,14 @@ llama_context * llama_init_from_model( } } + // TurboQuant cache types require flash attention — auto-enable if disabled + if (params.flash_attn_type == LLAMA_FLASH_ATTN_TYPE_DISABLED && + (params.type_k == GGML_TYPE_TURBO3_0 || params.type_k == GGML_TYPE_TURBO4_0 || + params.type_v == GGML_TYPE_TURBO3_0 || params.type_v == GGML_TYPE_TURBO4_0)) { + LLAMA_LOG_WARN("%s: turbo cache types require flash_attn — enabling automatically\n", __func__); + params.flash_attn_type = LLAMA_FLASH_ATTN_TYPE_ENABLED; + } + if (ggml_is_quantized(params.type_v) && params.flash_attn_type == LLAMA_FLASH_ATTN_TYPE_DISABLED) { LLAMA_LOG_ERROR("%s: V cache quantization requires flash_attn\n", __func__); return nullptr; diff --git a/src/llama-graph.cpp b/src/llama-graph.cpp index 0e7d96ca10d..d5bf1632db1 100644 --- a/src/llama-graph.cpp +++ b/src/llama-graph.cpp @@ -1851,6 +1851,10 @@ ggml_tensor * llm_graph_context::build_attn_mha( k = ggml_permute(ctx0, k, 0, 2, 1, 3); v = ggml_permute(ctx0, v, 0, 2, 1, 3); + // TurboQuant note: graph-side Q rotation (pre-rotate-queries) is implemented below + // in the flash-attn path. The VEC kernel bug (wrong Q/K stride in + // vec_dot_fattn_vec_KQ_turbo3_0) was fixed in fattn-common.cuh to match f16 pattern. + ggml_tensor * cur; const bool use_flash_attn = cparams.flash_attn && kq_b == nullptr; @@ -1877,6 +1881,20 @@ ggml_tensor * llm_graph_context::build_attn_mha( ggml_flash_attn_ext_add_sinks(cur, sinks); ggml_flash_attn_ext_set_prec (cur, GGML_PREC_F32); + // TurboQuant: inverse WHT on FA output when V values are WHT-rotated. + // For MLA, V is a view of K with different ne[0] (e.g. V=512, K=576). + // Group size must come from K (which determines the WHT rotation), not V. + if (v->type == GGML_TYPE_TURBO3_0 || v->type == GGML_TYPE_TURBO4_0 || v->type == GGML_TYPE_TURBO2_0) { + const bool k_is_turbo = (k->type == GGML_TYPE_TURBO3_0 || k->type == GGML_TYPE_TURBO4_0 || k->type == GGML_TYPE_TURBO2_0); + const ggml_tensor * group_src = k_is_turbo ? k : v; + const int turbo_group = (group_src->ne[0] % 128 == 0) ? 128 : 64; + if (cur->ne[0] % turbo_group == 0) { + if (!ggml_is_contiguous(cur)) { cur = ggml_cont(ctx0, cur); } + ggml_tensor * innerq_scale = mctx ? mctx->get_turbo_innerq_scale_inv() : nullptr; + cur = ggml_turbo_wht(ctx0, cur, 1, turbo_group, innerq_scale); // 1 = inverse + } + } + if (v_mla) { #if 0 // v_mla can be applied as a matrix-vector multiplication with broadcasting across dimension 3 == n_tokens. @@ -1943,6 +1961,18 @@ ggml_tensor * llm_graph_context::build_attn_mha( ggml_tensor * kqv = ggml_mul_mat(ctx0, v, kq); cb(kqv, "kqv", il); + // TurboQuant: inverse WHT on attention output (non-FA path) + if (v->type == GGML_TYPE_TURBO3_0 || v->type == GGML_TYPE_TURBO4_0 || v->type == GGML_TYPE_TURBO2_0) { + const bool k_is_turbo = (k->type == GGML_TYPE_TURBO3_0 || k->type == GGML_TYPE_TURBO4_0 || k->type == GGML_TYPE_TURBO2_0); + const ggml_tensor * group_src = k_is_turbo ? k : v; + const int turbo_group = (group_src->ne[0] % 128 == 0) ? 128 : 64; + if (kqv->ne[0] % turbo_group == 0) { + if (!ggml_is_contiguous(kqv)) { kqv = ggml_cont(ctx0, kqv); } + ggml_tensor * innerq_scale = mctx ? mctx->get_turbo_innerq_scale_inv() : nullptr; + kqv = ggml_turbo_wht(ctx0, kqv, 1, turbo_group, innerq_scale); + } + } + // for MLA with the absorption optimization, we need to "decompress" from MQA back to MHA if (v_mla) { kqv = ggml_mul_mat(ctx0, v_mla, kqv); @@ -1960,6 +1990,8 @@ ggml_tensor * llm_graph_context::build_attn_mha( } } + // TurboQuant: graph-side inverse WHT on attention output (undoes V rotation) + ggml_build_forward_expand(gf, cur); return cur; @@ -2118,9 +2150,42 @@ ggml_tensor * llm_graph_context::build_attn( ggml_tensor * k = mctx_cur->get_k(ctx0, il); ggml_tensor * v = mctx_cur->get_v(ctx0, il); + // TurboQuant pre-rotate-queries: O(d log d) WHT rotation via custom op + // Q shape: (n_embd_head, n_head, n_tokens) + // For zero-padded models (head_dim not 128-aligned), pad Q to match padded K dim first. + if (k->type == GGML_TYPE_TURBO3_0 || k->type == GGML_TYPE_TURBO4_0 || k->type == GGML_TYPE_TURBO2_0) { + // Pad Q per-head to next multiple of 128 if needed + if (q->ne[0] % 128 != 0) { + const int64_t pad = ((q->ne[0] + 127) / 128) * 128 - q->ne[0]; + q = ggml_pad(ctx0, q, pad, 0, 0, 0); + } + if (!ggml_is_contiguous(q)) { q = ggml_cont(ctx0, q); } + ggml_tensor * innerq_scale = mctx_cur->get_turbo_innerq_scale_inv(); + q = ggml_turbo_wht(ctx0, q, 0, 0, innerq_scale); // 0 = forward, 0 = auto group size from q->ne[0] + } + ggml_tensor * cur = build_attn_mha(q, k, v, kq_b, kq_mask, sinks, v_mla, kq_scale, il); cb(cur, "kqv_out", il); + // TurboQuant: if V was padded, the output has padded dimensions. + // Extract original V head_dim after inverse WHT (applied inside build_attn_mha). + if (k->type == GGML_TYPE_TURBO3_0 || k->type == GGML_TYPE_TURBO4_0 || k->type == GGML_TYPE_TURBO2_0) { + const int64_t orig_v_head = hparams.n_embd_head_v(il); + // cur is 2D: (n_embd_head * n_head, n_tokens) after build_attn_mha + const int64_t padded_v_head = v->ne[0]; + if (padded_v_head != orig_v_head) { + // Reshape to 4D, extract original head_dim, reshape back to 2D + const int64_t n_head_v = hparams.n_head_kv(il); + const int64_t n_tokens_cur = cur->ne[1]; + cur = ggml_reshape_3d(ctx0, cur, padded_v_head, n_head_v, n_tokens_cur); + // ggml_view_3d to extract first orig_v_head elements per head + cur = ggml_view_3d(ctx0, cur, orig_v_head, n_head_v, n_tokens_cur, + cur->nb[1], cur->nb[2], 0); + cur = ggml_cont(ctx0, cur); + cur = ggml_reshape_2d(ctx0, cur, orig_v_head * n_head_v, n_tokens_cur); + } + } + if (inp->self_v_rot) { cur = ggml_mul_mat_aux(ctx0, cur, inp->self_v_rot); } @@ -2203,9 +2268,39 @@ ggml_tensor * llm_graph_context::build_attn( ggml_tensor * k = mctx_cur->get_k(ctx0, il); ggml_tensor * v = ggml_view_4d(ctx0, k, v_cur->ne[0], k->ne[1], k->ne[2], k->ne[3], k->nb[1], k->nb[2], k->nb[3], 0); + // TurboQuant: pre-rotate Q for K-only (MLA) attention + // For zero-padded models, pad Q to match padded K dim first. + if (k->type == GGML_TYPE_TURBO3_0 || k->type == GGML_TYPE_TURBO4_0 || k->type == GGML_TYPE_TURBO2_0) { + // Pad Q per-head to next multiple of 128 if needed + if (q->ne[0] % 128 != 0) { + const int64_t pad = ((q->ne[0] + 127) / 128) * 128 - q->ne[0]; + q = ggml_pad(ctx0, q, pad, 0, 0, 0); + } + if (!ggml_is_contiguous(q)) { q = ggml_cont(ctx0, q); } + ggml_tensor * innerq_scale = mctx_cur->get_turbo_innerq_scale_inv(); + q = ggml_turbo_wht(ctx0, q, 0, 0, innerq_scale); // 0 = forward, 0 = auto group size + } + ggml_tensor * cur = build_attn_mha(q, k, v, kq_b, kq_mask, sinks, v_mla, kq_scale, il); cb(cur, "kqv_out", il); + // TurboQuant: if V was padded (MLA: V is view of K, may have padded dim), + // extract original V head_dim after inverse WHT. + if (k->type == GGML_TYPE_TURBO3_0 || k->type == GGML_TYPE_TURBO4_0 || k->type == GGML_TYPE_TURBO2_0) { + const int64_t orig_v_head = v_cur->ne[0]; // original V head_dim from model + const int64_t padded_v_head = v->ne[0]; // padded V head_dim in cache + if (padded_v_head != orig_v_head) { + // cur is 2D: (padded_v_head * n_head, n_tokens) after build_attn_mha + const int64_t n_head_v = hparams.n_head_kv(il); + const int64_t n_tokens_cur = cur->ne[1]; + cur = ggml_reshape_3d(ctx0, cur, padded_v_head, n_head_v, n_tokens_cur); + cur = ggml_view_3d(ctx0, cur, orig_v_head, n_head_v, n_tokens_cur, + cur->nb[1], cur->nb[2], 0); + cur = ggml_cont(ctx0, cur); + cur = ggml_reshape_2d(ctx0, cur, orig_v_head * n_head_v, n_tokens_cur); + } + } + if (wo) { cur = build_lora_mm(wo, cur); if (arch == LLM_ARCH_GLM4 || arch == LLM_ARCH_GLM4_MOE) { @@ -2282,9 +2377,35 @@ ggml_tensor * llm_graph_context::build_attn( ggml_tensor * k = mctx_cur->get_k(ctx0, il); ggml_tensor * v = mctx_cur->get_v(ctx0, il); + // TurboQuant: pre-rotate Q for ISWA attention (pad to 128-aligned if needed) + if (k->type == GGML_TYPE_TURBO3_0 || k->type == GGML_TYPE_TURBO4_0 || k->type == GGML_TYPE_TURBO2_0) { + if (q->ne[0] % 128 != 0) { + const int64_t pad = ((q->ne[0] + 127) / 128) * 128 - q->ne[0]; + q = ggml_pad(ctx0, q, pad, 0, 0, 0); + } + if (!ggml_is_contiguous(q)) { q = ggml_cont(ctx0, q); } + ggml_tensor * innerq_scale = mctx_cur->get_turbo_innerq_scale_inv(); + q = ggml_turbo_wht(ctx0, q, 0, 0, innerq_scale); + } + ggml_tensor * cur = build_attn_mha(q, k, v, kq_b, kq_mask, sinks, v_mla, kq_scale, il); cb(cur, "kqv_out", il); + // TurboQuant: if V was padded, extract original V head_dim after inverse WHT + if (k->type == GGML_TYPE_TURBO3_0 || k->type == GGML_TYPE_TURBO4_0 || k->type == GGML_TYPE_TURBO2_0) { + const int64_t orig_v_head = hparams.n_embd_head_v(il); + const int64_t padded_v_head = v->ne[0]; + if (padded_v_head != orig_v_head) { + const int64_t n_head_v = hparams.n_head_kv(il); + const int64_t n_tokens_cur = cur->ne[1]; + cur = ggml_reshape_3d(ctx0, cur, padded_v_head, n_head_v, n_tokens_cur); + cur = ggml_view_3d(ctx0, cur, orig_v_head, n_head_v, n_tokens_cur, + cur->nb[1], cur->nb[2], 0); + cur = ggml_cont(ctx0, cur); + cur = ggml_reshape_2d(ctx0, cur, orig_v_head * n_head_v, n_tokens_cur); + } + } + if (inp->self_v_rot) { cur = ggml_mul_mat_aux(ctx0, cur, inp->self_v_rot); } diff --git a/src/llama-kv-cache.cpp b/src/llama-kv-cache.cpp index 3e0fd3107f3..c55a5326640 100644 --- a/src/llama-kv-cache.cpp +++ b/src/llama-kv-cache.cpp @@ -72,6 +72,30 @@ static ggml_tensor * ggml_mul_mat_aux( return res; } +// InnerQ: cross-TU shared state for CUDA per-channel equalization. +// These are defined in ggml-cuda/turbo-innerq.cu (when CUDA is enabled). +// When CUDA is not available, we provide stub implementations. +#ifndef INNERQ_MAX_CHANNELS +#define INNERQ_MAX_CHANNELS 128 +#endif + +#ifdef GGML_USE_CUDA +#if defined(_WIN32) && !defined(__MINGW32__) +# define TURBO_IQ_IMPORT __declspec(dllimport) +#else +# define TURBO_IQ_IMPORT +#endif +extern TURBO_IQ_IMPORT bool g_innerq_finalized; +extern TURBO_IQ_IMPORT float g_innerq_scale_inv_host[INNERQ_MAX_CHANNELS]; +TURBO_IQ_IMPORT bool turbo_innerq_needs_tensor_update(void); +TURBO_IQ_IMPORT void turbo_innerq_mark_tensor_updated(void); +#else +static bool g_innerq_finalized = false; +static float g_innerq_scale_inv_host[INNERQ_MAX_CHANNELS] = {}; +static bool turbo_innerq_needs_tensor_update(void) { return false; } +static void turbo_innerq_mark_tensor_updated(void) {} +#endif + // // llama_kv_cache // @@ -110,7 +134,8 @@ llama_kv_cache::llama_kv_cache( auto it = ctx_map.find(buft); if (it == ctx_map.end()) { ggml_init_params params = { - /*.mem_size =*/ size_t(2u*(1 + n_stream)*n_layer_kv*ggml_tensor_overhead()), + // +3 for turbo rotation matrices (turbo_rotation + turbo_rotation_inv + turbo_innerq_scale_inv) + /*.mem_size =*/ size_t((2u*(1 + n_stream)*n_layer_kv + 3)*ggml_tensor_overhead()), /*.mem_buffer =*/ NULL, /*.no_alloc =*/ true, }; @@ -191,11 +216,107 @@ llama_kv_cache::llama_kv_cache( throw std::runtime_error("failed to create ggml context for kv cache"); } + // TurboQuant zero-padding: for models with non-128-aligned head_dim (e.g. DeepSeek + // head_dim_k=192), pad each head to the next multiple of 128. The padded zeros don't + // affect dot products since WHT preserves inner products: + // = = + <0, 0> = + const uint32_t n_embd_head_k = hparams.n_embd_head_k(il); + + const bool has_k = true; const bool has_v = !is_mla; - ggml_tensor * k = has_k ? ggml_new_tensor_3d(ctx, type_k, n_embd_k_gqa, kv_size, n_stream) : nullptr; - ggml_tensor * v = has_v ? ggml_new_tensor_3d(ctx, type_v, n_embd_v_gqa, kv_size, n_stream) : nullptr; + // Layer-adaptive: use higher precision for quality-sensitive layers + // Config: TURBO_LAYER_ADAPTIVE env var controls the strategy + // 0 = uniform (default) + // 1 = q8_0 K+V for first+last 4 layers + // 2 = q8_0 K+V for last 8 layers + // 5 = Boundary V: first2+last2 V=turbo4, rest V=turbo2 (K unchanged) + // 6 = V-only: last 8 V=turbo4, rest V=turbo2 (K unchanged) + // 7 = Boundary V (recommended): first2+last2 V=q8_0, rest V=turbo2 (K unchanged) + ggml_type layer_type_k = type_k; + ggml_type layer_type_v = type_v; + { + static const int adaptive_mode = [&]() { + const char * env = getenv("TURBO_LAYER_ADAPTIVE"); + if (env) { + int mode = atoi(env); + if (mode > 0) { + LLAMA_LOG_INFO("llama_kv_cache: layer-adaptive mode %d enabled (env)\n", mode); + } + return mode; + } + // Auto-enable Boundary V (mode 7) when V is turbo2 + if (type_v == GGML_TYPE_TURBO2_0 && hparams.n_layer >= 8) { + LLAMA_LOG_INFO("llama_kv_cache: Boundary V auto-enabled for turbo2-V (opt-out: TURBO_LAYER_ADAPTIVE=0)\n"); + return 7; + } + return 0; + }(); + const bool is_turbo = (type_k == GGML_TYPE_TURBO3_0 || type_k == GGML_TYPE_TURBO4_0 || type_k == GGML_TYPE_TURBO2_0); + const bool v_is_turbo = (type_v == GGML_TYPE_TURBO3_0 || type_v == GGML_TYPE_TURBO4_0 || type_v == GGML_TYPE_TURBO2_0); + const uint32_t n_layer = hparams.n_layer; + if (adaptive_mode == 1 && is_turbo && n_layer >= 8) { + if (il < 4 || il >= n_layer - 4) { + layer_type_k = GGML_TYPE_Q8_0; + layer_type_v = GGML_TYPE_Q8_0; + } + } else if (adaptive_mode == 2 && is_turbo && n_layer >= 8) { + if (il >= n_layer - 8) { + layer_type_k = GGML_TYPE_Q8_0; + layer_type_v = GGML_TYPE_Q8_0; + } + } else if (adaptive_mode == 5 && v_is_turbo && n_layer >= 8) { + // Boundary V (turbo4 boundaries): first2+last2 V=turbo4, rest V=turbo2 + const bool is_boundary = (il < 2 || il >= n_layer - 2); + layer_type_v = is_boundary ? GGML_TYPE_TURBO4_0 : GGML_TYPE_TURBO2_0; + if (il == 0) { + LLAMA_LOG_INFO("llama_kv_cache: Boundary V mode 5: first2+last2 V=turbo4, rest V=turbo2\n"); + } + } else if (adaptive_mode == 6 && v_is_turbo && n_layer >= 8) { + // V-only: last 8 V=turbo4, rest V=turbo2 + layer_type_v = (il >= n_layer - 8) ? GGML_TYPE_TURBO4_0 : GGML_TYPE_TURBO2_0; + if (il == 0) { + LLAMA_LOG_INFO("llama_kv_cache: V-only LA mode 6: last8 V=turbo4, rest V=turbo2\n"); + } + } else if (adaptive_mode == 7 && v_is_turbo && n_layer >= 8) { + // Boundary V (recommended): first2+last2 V=q8_0, rest V=turbo2 + const bool is_boundary = (il < 2 || il >= n_layer - 2); + layer_type_v = is_boundary ? GGML_TYPE_Q8_0 : GGML_TYPE_TURBO2_0; + if (il == 0) { + LLAMA_LOG_INFO("llama_kv_cache: Boundary V mode 7: first2+last2 V=q8_0, rest V=turbo2\n"); + } + } + } + // For turbo types, pad K head_dim to next multiple of 128 for full WHT groups + uint32_t n_embd_k_gqa_eff = n_embd_k_gqa; + const bool k_is_turbo = (layer_type_k == GGML_TYPE_TURBO3_0 || layer_type_k == GGML_TYPE_TURBO4_0 || layer_type_k == GGML_TYPE_TURBO2_0); + if (k_is_turbo && n_embd_head_k % 128 != 0) { + const uint32_t padded_head_k = ((n_embd_head_k + 127) / 128) * 128; + const uint32_t n_head_kv = n_embd_k_gqa / n_embd_head_k; + n_embd_k_gqa_eff = n_head_kv * padded_head_k; + if (il == 0) { + LLAMA_LOG_INFO("%s: turbo zero-padding K head_dim %u -> %u (cache %u -> %u)\n", + __func__, n_embd_head_k, padded_head_k, n_embd_k_gqa, n_embd_k_gqa_eff); + } + } + + // For turbo types, pad V head_dim to next multiple of 128 if needed + const uint32_t n_embd_head_v = hparams.n_embd_head_v(il); + uint32_t n_embd_v_gqa_eff = n_embd_v_gqa; + const bool v_is_turbo = (layer_type_v == GGML_TYPE_TURBO3_0 || layer_type_v == GGML_TYPE_TURBO4_0 || layer_type_v == GGML_TYPE_TURBO2_0); + if (v_is_turbo && !is_mla && n_embd_head_v % 128 != 0) { + const uint32_t padded_head_v = ((n_embd_head_v + 127) / 128) * 128; + const uint32_t n_head_kv = n_embd_v_gqa / n_embd_head_v; + n_embd_v_gqa_eff = n_head_kv * padded_head_v; + if (il == 0) { + LLAMA_LOG_INFO("%s: turbo zero-padding V head_dim %u -> %u (cache %u -> %u)\n", + __func__, n_embd_head_v, padded_head_v, n_embd_v_gqa, n_embd_v_gqa_eff); + } + } + + ggml_tensor * k = has_k ? ggml_new_tensor_3d(ctx, layer_type_k, n_embd_k_gqa_eff, kv_size, n_stream) : nullptr; + ggml_tensor * v = has_v ? ggml_new_tensor_3d(ctx, layer_type_v, n_embd_v_gqa_eff, kv_size, n_stream) : nullptr; has_k && ggml_format_name(k, "cache_k_l%d", il); has_v && ggml_format_name(v, "cache_v_l%d", il); @@ -204,13 +325,26 @@ llama_kv_cache::llama_kv_cache( std::vector v_stream; for (uint32_t s = 0; s < n_stream; ++s) { - k_stream.push_back(has_k ? ggml_view_2d(ctx, k, n_embd_k_gqa, kv_size, k->nb[1], s*k->nb[2]) : nullptr); - v_stream.push_back(has_v ? ggml_view_2d(ctx, v, n_embd_v_gqa, kv_size, v->nb[1], s*v->nb[2]) : nullptr); + k_stream.push_back(has_k ? ggml_view_2d(ctx, k, n_embd_k_gqa_eff, kv_size, k->nb[1], s*k->nb[2]) : nullptr); + v_stream.push_back(has_v ? ggml_view_2d(ctx, v, n_embd_v_gqa_eff, kv_size, v->nb[1], s*v->nb[2]) : nullptr); } map_layer_ids[il] = layers.size(); layers.push_back({ il, k, v, k_stream, v_stream, }); + + // TurboQuant: create rotation matrix tensors (once, shared across layers) + if (turbo_rotation == nullptr && + (type_k == GGML_TYPE_TURBO3_0 || type_k == GGML_TYPE_TURBO4_0 || type_k == GGML_TYPE_TURBO2_0)) { + turbo_rotation = ggml_new_tensor_2d(ctx, GGML_TYPE_F32, 128, 128); + ggml_format_name(turbo_rotation, "turbo_rotation"); // R^T + turbo_rotation_inv = ggml_new_tensor_2d(ctx, GGML_TYPE_F32, 128, 128); + ggml_format_name(turbo_rotation_inv, "turbo_rotation_inv"); // R + + // InnerQ: per-channel scale_inv tensor (128 floats, initialized to all 1.0) + turbo_innerq_scale_inv = ggml_new_tensor_1d(ctx, GGML_TYPE_F32, INNERQ_MAX_CHANNELS); + ggml_format_name(turbo_innerq_scale_inv, "turbo_innerq_scale_inv"); + } } if (reuse) { @@ -255,6 +389,28 @@ llama_kv_cache::llama_kv_cache( LLAMA_LOG_INFO("%s: %10s KV buffer size = %8.2f MiB\n", __func__, ggml_backend_buffer_name(buf), ggml_backend_buffer_get_size(buf)/1024.0/1024.0); ggml_backend_buffer_clear(buf, 0); + + // Fill turbo rotation matrices AFTER buffer clear (clear zeroes everything) + if (turbo_rotation != nullptr && turbo_rotation->buffer != nullptr && !model.hparams.no_alloc) { + #include "turbo-rotation-data.h" + // ggml is column-major; C arrays are row-major. Storing a row-major matrix + // into ggml implicitly transposes it. ggml_mul_mat(A, x) computes A^T @ x. + // To get R @ q: store R^T → ggml sees (R^T)^T_col = R → mul_mat gives R @ q. Wait no — + // store R so ggml col-major reads it as R^T, then mul_mat gives (R^T)^T = R. ✓ + // Store R for Q forward rotation, R^T for V inverse rotation + // ggml_mul_mat(A,x) computes A@x for row-major stored A (verified by test) + ggml_backend_tensor_set(turbo_rotation, TURBO_ROTATION_R, 0, 128 * 128 * sizeof(float)); + ggml_backend_tensor_set(turbo_rotation_inv, TURBO_ROTATION_RT, 0, 128 * 128 * sizeof(float)); + + // Initialize InnerQ scale_inv to all 1.0 (identity scaling) + if (turbo_innerq_scale_inv != nullptr && turbo_innerq_scale_inv->buffer != nullptr) { + float ones[INNERQ_MAX_CHANNELS]; + for (int i = 0; i < INNERQ_MAX_CHANNELS; i++) ones[i] = 1.0f; + ggml_backend_tensor_set(turbo_innerq_scale_inv, ones, 0, INNERQ_MAX_CHANNELS * sizeof(float)); + } + + LLAMA_LOG_INFO("%s: TurboQuant rotation matrices initialized (128x128)\n", __func__); + } ctxs_bufs.emplace_back(std::move(ctx), buf); } @@ -268,10 +424,15 @@ llama_kv_cache::llama_kv_cache( ggml_type_name(type_v), (float)memory_size_v / (1024.0f * 1024.0f)); } + // TurboQuant: disable upstream graph-level activation rotation by default. + // Our fork uses kernel-level WHT rotation (simd_shuffle_xor in Metal/CUDA) + // which is independent and more efficient. The upstream rotation adds extra + // graph nodes that cause hash table overflow on some models (e.g. Phi-4). + // Users can re-enable with LLAMA_ATTN_ROT_DISABLE=0 if needed. const char * LLAMA_ATTN_ROT_DISABLE = getenv("LLAMA_ATTN_ROT_DISABLE"); - const bool attn_rot_disable = LLAMA_ATTN_ROT_DISABLE ? atoi(LLAMA_ATTN_ROT_DISABLE) : false; + const bool attn_rot_disable = LLAMA_ATTN_ROT_DISABLE ? atoi(LLAMA_ATTN_ROT_DISABLE) : true; if (attn_rot_disable) { - LLAMA_LOG_WARN("%s: attention rotation force disabled (LLAMA_ATTN_ROT_DISABLE)\n", __func__); + LLAMA_LOG_INFO("%s: upstream attention rotation disabled (TurboQuant uses kernel-level WHT)\n", __func__); } attn_rot_k = @@ -324,6 +485,20 @@ void llama_kv_cache::clear(bool data) { for (auto & [_, buf] : ctxs_bufs) { ggml_backend_buffer_clear(buf.get(), 0); } + + // Re-initialize turbo rotation matrices after buffer clear (clear zeroes everything) + if (turbo_rotation != nullptr && turbo_rotation->buffer != nullptr) { + #include "turbo-rotation-data.h" + ggml_backend_tensor_set(turbo_rotation, TURBO_ROTATION_R, 0, 128 * 128 * sizeof(float)); + ggml_backend_tensor_set(turbo_rotation_inv, TURBO_ROTATION_RT, 0, 128 * 128 * sizeof(float)); + + // Re-initialize InnerQ scale_inv to all 1.0 + if (turbo_innerq_scale_inv != nullptr && turbo_innerq_scale_inv->buffer != nullptr) { + float ones[INNERQ_MAX_CHANNELS]; + for (int i = 0; i < INNERQ_MAX_CHANNELS; i++) ones[i] = 1.0f; + ggml_backend_tensor_set(turbo_innerq_scale_inv, ones, 0, INNERQ_MAX_CHANNELS * sizeof(float)); + } + } } } @@ -1137,13 +1312,24 @@ ggml_tensor * llama_kv_cache::get_k(ggml_context * ctx, int32_t il, uint32_t n_k const uint64_t kv_size = get_size(); const uint64_t n_embd_k_gqa = k->ne[0]; - assert(n_embd_k_gqa == hparams.n_embd_k_gqa(il)); + // For turbo-padded caches, n_embd_k_gqa may be larger than hparams value + const bool k_is_turbo = (k->type == GGML_TYPE_TURBO3_0 || k->type == GGML_TYPE_TURBO4_0 || k->type == GGML_TYPE_TURBO2_0); + if (k_is_turbo) { + assert(n_embd_k_gqa >= hparams.n_embd_k_gqa(il)); + } else { + assert(n_embd_k_gqa == hparams.n_embd_k_gqa(il)); + } + + // Use padded head_dim for turbo types so the full padded data is returned + const uint32_t head_k = hparams.n_embd_head_k(il); + const uint32_t head_k_eff = (k_is_turbo && head_k % 128 != 0) + ? ((head_k + 127) / 128) * 128 : head_k; const uint32_t ns = sinfo.s1 - sinfo.s0 + 1; return ggml_view_4d(ctx, k, - hparams.n_embd_head_k(il), hparams.n_head_kv(il), n_kv, ns, - ggml_row_size(k->type, hparams.n_embd_head_k(il)), + head_k_eff, hparams.n_head_kv(il), n_kv, ns, + ggml_row_size(k->type, head_k_eff), ggml_row_size(k->type, n_embd_k_gqa), ggml_row_size(k->type, n_embd_k_gqa*kv_size), ggml_row_size(k->type, n_embd_k_gqa*kv_size)*sinfo.s0); @@ -1157,27 +1343,33 @@ ggml_tensor * llama_kv_cache::get_v(ggml_context * ctx, int32_t il, uint32_t n_k const uint64_t kv_size = get_size(); const uint64_t n_embd_v_gqa = v->ne[0]; - // [TAG_V_CACHE_VARIABLE] + // [TAG_V_CACHE_VARIABLE] — for turbo-padded V, cache may be larger assert(n_embd_v_gqa >= hparams.n_embd_v_gqa(il)); + // Use padded head_dim for turbo types + const bool v_is_turbo = (v->type == GGML_TYPE_TURBO3_0 || v->type == GGML_TYPE_TURBO4_0 || v->type == GGML_TYPE_TURBO2_0); + const uint32_t head_v = hparams.n_embd_head_v(il); + const uint32_t head_v_eff = (v_is_turbo && head_v % 128 != 0) + ? ((head_v + 127) / 128) * 128 : head_v; + const uint32_t ns = sinfo.s1 - sinfo.s0 + 1; if (!v_trans) { // note: v->nb[1] <= v->nb[2] return ggml_view_4d(ctx, v, - hparams.n_embd_head_v(il), hparams.n_head_kv(il), n_kv, ns, - ggml_row_size(v->type, hparams.n_embd_head_v(il)), // v->nb[1] - ggml_row_size(v->type, n_embd_v_gqa), // v->nb[2] - ggml_row_size(v->type, n_embd_v_gqa*kv_size), // v->nb[3] + head_v_eff, hparams.n_head_kv(il), n_kv, ns, + ggml_row_size(v->type, head_v_eff), // v->nb[1] + ggml_row_size(v->type, n_embd_v_gqa), // v->nb[2] + ggml_row_size(v->type, n_embd_v_gqa*kv_size), // v->nb[3] ggml_row_size(v->type, n_embd_v_gqa*kv_size)*sinfo.s0); } // note: v->nb[1] > v->nb[2] return ggml_view_4d(ctx, v, - n_kv, hparams.n_head_kv(il), hparams.n_embd_head_v(il), ns, - ggml_row_size(v->type, kv_size*hparams.n_embd_head_v(il)), // v->nb[1] - ggml_row_size(v->type, kv_size), // v->nb[2] - ggml_row_size(v->type, kv_size*n_embd_v_gqa), // v->nb[3] + n_kv, hparams.n_head_kv(il), head_v_eff, ns, + ggml_row_size(v->type, kv_size*head_v_eff), // v->nb[1] + ggml_row_size(v->type, kv_size), // v->nb[2] + ggml_row_size(v->type, kv_size*n_embd_v_gqa), // v->nb[3] ggml_row_size(v->type, kv_size*n_embd_v_gqa)*sinfo.s0); } @@ -1188,11 +1380,22 @@ ggml_tensor * llama_kv_cache::cpy_k(ggml_context * ctx, ggml_tensor * k_cur, ggm ggml_tensor * k = layers[ikv].k; - const int64_t n_embd_head = k_cur->ne[0]; + int64_t n_embd_head = k_cur->ne[0]; const int64_t n_head = k_cur->ne[1]; const int64_t n_tokens = k_cur->ne[2]; - const int64_t n_embd_gqa = n_embd_head*n_head; + // Turbo zero-padding: pad each head to next multiple of 128 before merging dims. + // k_cur shape here is (n_embd_head, n_head, n_tokens). + // ggml_pad pads ne[0] with zeros — exactly what we need per-head. + const bool k_is_turbo = (k->type == GGML_TYPE_TURBO3_0 || k->type == GGML_TYPE_TURBO4_0 || k->type == GGML_TYPE_TURBO2_0); + const bool k_needs_pad = k_is_turbo && (n_embd_head % 128 != 0); + if (k_needs_pad) { + const int64_t pad_amount = ((n_embd_head + 127) / 128) * 128 - n_embd_head; + k_cur = ggml_pad(ctx, k_cur, pad_amount, 0, 0, 0); + n_embd_head = k_cur->ne[0]; // now 128-aligned + } + + int64_t n_embd_gqa = n_embd_head * n_head; // we can merge dims 0 and 1 // TODO: add ggml helper function for this? @@ -1213,7 +1416,16 @@ ggml_tensor * llama_kv_cache::cpy_k(ggml_context * ctx, ggml_tensor * k_cur, ggm } // store the current K values into the cache - return ggml_set_rows(ctx, k, k_cur, k_idxs); + ggml_tensor * result = ggml_set_rows(ctx, k, k_cur, k_idxs); + + // For turbo: store WHT group size in op_params so the CUDA kernel knows. + // With zero-padding, all groups are always full 128-element WHT groups. + if (k_is_turbo) { + int32_t wht_group = 128; // always 128 with padding + memcpy(result->op_params, &wht_group, sizeof(int32_t)); + } + + return result; } ggml_tensor * llama_kv_cache::cpy_v(ggml_context * ctx, ggml_tensor * v_cur, ggml_tensor * v_idxs, int32_t il, const slot_info & sinfo) const { @@ -1223,11 +1435,20 @@ ggml_tensor * llama_kv_cache::cpy_v(ggml_context * ctx, ggml_tensor * v_cur, ggm auto * v = layers[ikv].v; - const int64_t n_embd_head = v_cur->ne[0]; + int64_t n_embd_head = v_cur->ne[0]; const int64_t n_head = v_cur->ne[1]; const int64_t n_tokens = v_cur->ne[2]; - const int64_t n_embd_gqa = n_embd_head*n_head; + // Turbo zero-padding: pad V head_dim to next multiple of 128 + const bool v_is_turbo = (v->type == GGML_TYPE_TURBO3_0 || v->type == GGML_TYPE_TURBO4_0 || v->type == GGML_TYPE_TURBO2_0); + const bool v_needs_pad = v_is_turbo && (n_embd_head % 128 != 0); + if (v_needs_pad) { + const int64_t pad_amount = ((n_embd_head + 127) / 128) * 128 - n_embd_head; + v_cur = ggml_pad(ctx, v_cur, pad_amount, 0, 0, 0); + n_embd_head = v_cur->ne[0]; // now 128-aligned + } + + int64_t n_embd_gqa = n_embd_head * n_head; // we can merge dims 0 and 1 GGML_ASSERT(ggml_row_size(v_cur->type, n_embd_head) == v_cur->nb[1]); @@ -1248,7 +1469,13 @@ ggml_tensor * llama_kv_cache::cpy_v(ggml_context * ctx, ggml_tensor * v_cur, ggm v = ggml_reshape_2d(ctx, v, n_embd_gqa, kv_size*n_stream); } - return ggml_set_rows(ctx, v, v_cur, v_idxs); + ggml_tensor * result = ggml_set_rows(ctx, v, v_cur, v_idxs); + // With zero-padding, all groups are always full 128-element WHT groups + if (v_is_turbo) { + int32_t wht_group = 128; // always 128 with padding + memcpy(result->op_params, &wht_group, sizeof(int32_t)); + } + return result; } if (ggml_row_size(v_cur->type, n_embd_gqa) == v_cur->nb[2]) { @@ -1967,10 +2194,11 @@ void llama_kv_cache::state_write_data(llama_io_write_i & io, const cell_ranges_t for (const auto & layer : layers) { const uint32_t il = layer.il; - const uint32_t n_embd_k_gqa = hparams.n_embd_k_gqa(il); - auto * k = layer.k_stream[cr.strm]; + // Use actual tensor width (may be padded for turbo types: e.g. 576→640) + const uint32_t n_embd_k_gqa = (uint32_t) k->ne[0]; + // Write key type const int32_t k_type_i = (int32_t) k->type; io.write(&k_type_i, sizeof(k_type_i)); @@ -1991,13 +2219,14 @@ void llama_kv_cache::state_write_data(llama_io_write_i & io, const cell_ranges_t for (const auto & layer : layers) { const uint32_t il = layer.il; - const uint32_t n_embd_v_gqa = hparams.n_embd_v_gqa(il); - auto * v = layer.v_stream[cr.strm]; if (!v) { continue; } + // Use actual tensor width (may be padded for turbo types) + const uint32_t n_embd_v_gqa = (uint32_t) v->ne[0]; + // Write value type const int32_t v_type_i = (int32_t) v->type; io.write(&v_type_i, sizeof(v_type_i)); @@ -2199,10 +2428,11 @@ bool llama_kv_cache::state_read_data(llama_io_read_i & io, uint32_t strm, uint32 for (const auto & layer : layers) { const uint32_t il = layer.il; - const uint32_t n_embd_k_gqa = hparams.n_embd_k_gqa(il); - auto * k = layer.k_stream[strm]; + // Use actual tensor width (may be padded for turbo types) + const uint32_t n_embd_k_gqa = (uint32_t) k->ne[0]; + // Read type of key int32_t k_type_i_ref; io.read_to(&k_type_i_ref, sizeof(k_type_i_ref)); @@ -2240,13 +2470,14 @@ bool llama_kv_cache::state_read_data(llama_io_read_i & io, uint32_t strm, uint32 for (const auto & layer : layers) { const uint32_t il = layer.il; - const uint32_t n_embd_v_gqa = hparams.n_embd_v_gqa(il); - auto * v = layer.v_stream[strm]; if (!v) { continue; } + // Use actual tensor width (may be padded for turbo types) + const uint32_t n_embd_v_gqa = (uint32_t) v->ne[0]; + // Read type of value int32_t v_type_i_ref; io.read_to(&v_type_i_ref, sizeof(v_type_i_ref)); @@ -2406,6 +2637,16 @@ bool llama_kv_cache_context::apply() { kv->apply_ubatch(sinfos[i_cur], ubatches[i_cur]); n_kv = kv->get_n_kv(sinfos[i_cur]); + // InnerQ: check if CUDA calibration finalized and tensor needs update + if (kv->get_turbo_innerq_scale_inv() != nullptr && turbo_innerq_needs_tensor_update()) { + ggml_tensor * t = kv->get_turbo_innerq_scale_inv(); + if (t->buffer != nullptr) { + ggml_backend_tensor_set(t, g_innerq_scale_inv_host, 0, INNERQ_MAX_CHANNELS * sizeof(float)); + turbo_innerq_mark_tensor_updated(); + LLAMA_LOG_INFO("%s: InnerQ scale_inv tensor updated\n", __func__); + } + } + return true; } @@ -2439,6 +2680,26 @@ ggml_tensor * llama_kv_cache_context::get_v(ggml_context * ctx, int32_t il) cons return kv->get_v(ctx, il, n_kv, sinfos[i_cur]); } +ggml_tensor * llama_kv_cache_context::get_turbo_rotation() const { + return kv->get_turbo_rotation(); +} + +ggml_tensor * llama_kv_cache_context::get_turbo_rotation_inv() const { + return kv->get_turbo_rotation_inv(); +} + +ggml_tensor * llama_kv_cache_context::get_turbo_rot_forward() const { + return kv->get_turbo_rotation(); +} + +ggml_tensor * llama_kv_cache_context::get_turbo_rot_inverse() const { + return kv->get_turbo_rotation_inv(); +} + +ggml_tensor * llama_kv_cache_context::get_turbo_innerq_scale_inv() const { + return kv->get_turbo_innerq_scale_inv(); +} + ggml_tensor * llama_kv_cache_context::cpy_k(ggml_context * ctx, ggml_tensor * k_cur, ggml_tensor * k_idxs, int32_t il) const { return kv->cpy_k(ctx, k_cur, k_idxs, il, sinfos[i_cur]); } diff --git a/src/llama-kv-cache.h b/src/llama-kv-cache.h index d4569a06f71..ab366c944f8 100644 --- a/src/llama-kv-cache.h +++ b/src/llama-kv-cache.h @@ -165,6 +165,15 @@ class llama_kv_cache : public llama_memory_i { ggml_tensor * get_k(ggml_context * ctx, int32_t il, uint32_t n_kv, const slot_info & sinfo) const; ggml_tensor * get_v(ggml_context * ctx, int32_t il, uint32_t n_kv, const slot_info & sinfo) const; + // TurboQuant: get rotation matrices (stored as row-major C arrays) + // turbo_rotation = R (forward rotation, for Q pre-rotate-queries) + // turbo_rotation_inv = R^T = R^{-1} (inverse rotation, for V output un-rotation) + ggml_tensor * get_turbo_rotation() const { return turbo_rotation; } + ggml_tensor * get_turbo_rotation_inv() const { return turbo_rotation_inv; } + + // TurboQuant InnerQ: per-channel scale_inv for Q/V equalization + ggml_tensor * get_turbo_innerq_scale_inv() const { return turbo_innerq_scale_inv; } + // store k_cur and v_cur in the cache based on the provided head location ggml_tensor * cpy_k(ggml_context * ctx, ggml_tensor * k_cur, ggml_tensor * k_idxs, int32_t il, const slot_info & sinfo) const; ggml_tensor * cpy_v(ggml_context * ctx, ggml_tensor * v_cur, ggml_tensor * v_idxs, int32_t il, const slot_info & sinfo) const; @@ -265,6 +274,13 @@ class llama_kv_cache : public llama_memory_i { std::vector layers; + // TurboQuant rotation matrices (128x128, row-major stored) + ggml_tensor * turbo_rotation = nullptr; // R (forward rotation) + ggml_tensor * turbo_rotation_inv = nullptr; // R^T = R^{-1} (inverse rotation) + + // TurboQuant InnerQ: per-channel scale_inv for Q/V equalization (128 floats) + ggml_tensor * turbo_innerq_scale_inv = nullptr; + // model layer id -> KV cache layer id std::unordered_map map_layer_ids; @@ -352,6 +368,17 @@ class llama_kv_cache_context : public llama_memory_context_i { ggml_tensor * get_k(ggml_context * ctx, int32_t il) const; ggml_tensor * get_v(ggml_context * ctx, int32_t il) const; + // TurboQuant rotation accessors + ggml_tensor * get_turbo_rotation() const; + ggml_tensor * get_turbo_rotation_inv() const; + + // Override virtual methods from llama_memory_context_i + ggml_tensor * get_turbo_rot_forward() const override; + ggml_tensor * get_turbo_rot_inverse() const override; + + // TurboQuant InnerQ: per-channel scale_inv for Q/V equalization + ggml_tensor * get_turbo_innerq_scale_inv() const override; + // store k_cur and v_cur in the cache based on the provided head location // note: the heads in k_cur and v_cur should be laid out contiguously in memory // - k_cur [n_embd_head_k, n_head_k, n_tokens] diff --git a/src/llama-memory-hybrid.cpp b/src/llama-memory-hybrid.cpp index 4ce1af592c1..b3755d5768b 100644 --- a/src/llama-memory-hybrid.cpp +++ b/src/llama-memory-hybrid.cpp @@ -263,6 +263,18 @@ const llama_kv_cache_context * llama_memory_hybrid_context::get_attn() const { return static_cast(ctx_attn.get()); } +ggml_tensor * llama_memory_hybrid_context::get_turbo_rot_forward() const { + return ctx_attn ? ctx_attn->get_turbo_rot_forward() : nullptr; +} + +ggml_tensor * llama_memory_hybrid_context::get_turbo_rot_inverse() const { + return ctx_attn ? ctx_attn->get_turbo_rot_inverse() : nullptr; +} + +ggml_tensor * llama_memory_hybrid_context::get_turbo_innerq_scale_inv() const { + return ctx_attn ? ctx_attn->get_turbo_innerq_scale_inv() : nullptr; +} + const llama_memory_recurrent_context * llama_memory_hybrid_context::get_recr() const { return static_cast(ctx_recr.get()); } diff --git a/src/llama-memory-hybrid.h b/src/llama-memory-hybrid.h index 558cafdf984..87dd3487692 100644 --- a/src/llama-memory-hybrid.h +++ b/src/llama-memory-hybrid.h @@ -119,6 +119,11 @@ class llama_memory_hybrid_context : public llama_memory_context_i { llama_memory_status get_status() const override; const llama_ubatch & get_ubatch() const override; + // TurboQuant: delegate to the KV cache context + ggml_tensor * get_turbo_rot_forward() const override; + ggml_tensor * get_turbo_rot_inverse() const override; + ggml_tensor * get_turbo_innerq_scale_inv() const override; + // // llama_memory_hybrid_context // diff --git a/src/llama-memory.h b/src/llama-memory.h index 4a157b91fdb..2704096da71 100644 --- a/src/llama-memory.h +++ b/src/llama-memory.h @@ -59,6 +59,15 @@ struct llama_memory_context_i { // get the status of the memory context - used for error handling and checking if any updates would be applied virtual llama_memory_status get_status() const = 0; + + // TurboQuant: get rotation tensors for pre-rotate-queries optimization + // Returns null for non-turbo memory types. Override in KV cache contexts. + virtual ggml_tensor * get_turbo_rot_forward() const { return nullptr; } + virtual ggml_tensor * get_turbo_rot_inverse() const { return nullptr; } + + // TurboQuant InnerQ: get per-channel scale_inv tensor for Q/V equalization + // Returns nullptr when InnerQ is not active. Override in KV cache contexts. + virtual ggml_tensor * get_turbo_innerq_scale_inv() const { return nullptr; } }; using llama_memory_context_ptr = std::unique_ptr; diff --git a/src/llama-model-loader.cpp b/src/llama-model-loader.cpp index 3d549cae5b6..b8d1853d7b9 100644 --- a/src/llama-model-loader.cpp +++ b/src/llama-model-loader.cpp @@ -55,6 +55,8 @@ static std::string llama_model_ftype_name(llama_ftype ftype) { case LLAMA_FTYPE_MOSTLY_Q6_K: return "Q6_K"; case LLAMA_FTYPE_MOSTLY_TQ1_0: return "TQ1_0 - 1.69 bpw ternary"; case LLAMA_FTYPE_MOSTLY_TQ2_0: return "TQ2_0 - 2.06 bpw ternary"; + case LLAMA_FTYPE_MOSTLY_TQ3_1S: return "TQ3_1S - 4.0 bpw WHT-rotated 3-bit"; + case LLAMA_FTYPE_MOSTLY_TQ4_1S: return "TQ4_1S - 5.0 bpw WHT-rotated 4-bit"; case LLAMA_FTYPE_MOSTLY_IQ2_XXS: return "IQ2_XXS - 2.0625 bpw"; case LLAMA_FTYPE_MOSTLY_IQ2_XS: return "IQ2_XS - 2.3125 bpw"; case LLAMA_FTYPE_MOSTLY_IQ2_S: return "IQ2_S - 2.5 bpw"; @@ -747,6 +749,8 @@ llama_model_loader::llama_model_loader( case GGML_TYPE_Q6_K: ftype = LLAMA_FTYPE_MOSTLY_Q6_K; break; case GGML_TYPE_TQ1_0: ftype = LLAMA_FTYPE_MOSTLY_TQ1_0; break; case GGML_TYPE_TQ2_0: ftype = LLAMA_FTYPE_MOSTLY_TQ2_0; break; + case GGML_TYPE_TQ3_1S: ftype = LLAMA_FTYPE_MOSTLY_TQ3_1S; break; + case GGML_TYPE_TQ4_1S: ftype = LLAMA_FTYPE_MOSTLY_TQ4_1S; break; case GGML_TYPE_IQ2_XXS: ftype = LLAMA_FTYPE_MOSTLY_IQ2_XXS; break; case GGML_TYPE_IQ2_XS: ftype = LLAMA_FTYPE_MOSTLY_IQ2_XS; break; case GGML_TYPE_IQ2_S: ftype = LLAMA_FTYPE_MOSTLY_IQ2_S; break; diff --git a/src/llama-quant.cpp b/src/llama-quant.cpp index 322cb313f1c..51aaf79fdff 100644 --- a/src/llama-quant.cpp +++ b/src/llama-quant.cpp @@ -816,6 +816,8 @@ ggml_type llama_ftype_get_default_type(llama_ftype ftype) { case LLAMA_FTYPE_MOSTLY_Q6_K: return GGML_TYPE_Q6_K; case LLAMA_FTYPE_MOSTLY_TQ1_0: return GGML_TYPE_TQ1_0; case LLAMA_FTYPE_MOSTLY_TQ2_0: return GGML_TYPE_TQ2_0; + case LLAMA_FTYPE_MOSTLY_TQ3_1S: return GGML_TYPE_TQ3_1S; + case LLAMA_FTYPE_MOSTLY_TQ4_1S: return GGML_TYPE_TQ4_1S; case LLAMA_FTYPE_MOSTLY_IQ2_XXS: return GGML_TYPE_IQ2_XXS; case LLAMA_FTYPE_MOSTLY_IQ2_XS: return GGML_TYPE_IQ2_XS; case LLAMA_FTYPE_MOSTLY_IQ2_S: return GGML_TYPE_IQ2_XS; diff --git a/src/turbo-rotation-data-32.h b/src/turbo-rotation-data-32.h new file mode 100644 index 00000000000..1b6037714dd --- /dev/null +++ b/src/turbo-rotation-data-32.h @@ -0,0 +1,71 @@ +// Pre-computed 32x32 rotation matrices for TurboQuant (group_size=32, seed=42) + +static const float TURBO_ROTATION_R_32[1024] = { + -1.76776695e-01f, 1.76776695e-01f, -1.76776695e-01f, -1.76776695e-01f, -1.76776695e-01f, 1.76776695e-01f, -1.76776695e-01f, -1.76776695e-01f, -1.76776695e-01f, 1.76776695e-01f, -1.76776695e-01f, -1.76776695e-01f, -1.76776695e-01f, -1.76776695e-01f, 1.76776695e-01f, -1.76776695e-01f, 1.76776695e-01f, 1.76776695e-01f, 1.76776695e-01f, -1.76776695e-01f, 1.76776695e-01f, -1.76776695e-01f, 1.76776695e-01f, 1.76776695e-01f, 1.76776695e-01f, 1.76776695e-01f, 1.76776695e-01f, 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TurboQuant pre-rotate-queries + +static const float TURBO_ROTATION_RT[128*128] = { + -8.83883461e-02f, -8.83883461e-02f, -8.83883461e-02f, -8.83883461e-02f, 8.83883461e-02f, -8.83883461e-02f, -8.83883461e-02f, 8.83883461e-02f, + -8.83883461e-02f, 8.83883461e-02f, 8.83883461e-02f, 8.83883461e-02f, -8.83883461e-02f, 8.83883461e-02f, 8.83883461e-02f, 8.83883461e-02f, + -8.83883461e-02f, -8.83883461e-02f, 8.83883461e-02f, 8.83883461e-02f, -8.83883461e-02f, 8.83883461e-02f, -8.83883461e-02f, 8.83883461e-02f, + -8.83883461e-02f, 8.83883461e-02f, 8.83883461e-02f, -8.83883461e-02f, 8.83883461e-02f, -8.83883461e-02f, -8.83883461e-02f, -8.83883461e-02f, + -8.83883461e-02f, -8.83883461e-02f, 8.83883461e-02f, 8.83883461e-02f, 8.83883461e-02f, -8.83883461e-02f, 8.83883461e-02f, 8.83883461e-02f, + 8.83883461e-02f, 8.83883461e-02f, 8.83883461e-02f, 8.83883461e-02f, -8.83883461e-02f, -8.83883461e-02f, -8.83883461e-02f, 8.83883461e-02f, + -8.83883461e-02f, 8.83883461e-02f, -8.83883461e-02f, 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8.83883461e-02f, 8.83883461e-02f, 8.83883461e-02f, 8.83883461e-02f, 8.83883461e-02f, -8.83883461e-02f, -8.83883461e-02f, + 8.83883461e-02f, -8.83883461e-02f, -8.83883461e-02f, 8.83883461e-02f, 8.83883461e-02f, 8.83883461e-02f, -8.83883461e-02f, -8.83883461e-02f, + 8.83883461e-02f, 8.83883461e-02f, -8.83883461e-02f, 8.83883461e-02f, 8.83883461e-02f, -8.83883461e-02f, -8.83883461e-02f, 8.83883461e-02f, + 8.83883461e-02f, 8.83883461e-02f, 8.83883461e-02f, 8.83883461e-02f, 8.83883461e-02f, -8.83883461e-02f, 8.83883461e-02f, 8.83883461e-02f, +}; diff --git a/tests/test-turbo-quant.c b/tests/test-turbo-quant.c new file mode 100644 index 00000000000..d5c37bad671 --- /dev/null +++ b/tests/test-turbo-quant.c @@ -0,0 +1,54 @@ +#include +#include +#include + +extern void quantize_row_turbo3_0_ref(const float * x, void * y, long long k); +extern void dequantize_row_turbo3_0(const void * x, float * y, long long k); +extern void quantize_row_turbo4_0_ref(const float * x, void * y, long long k); +extern void dequantize_row_turbo4_0(const void * x, float * y, long long k); + +int main(void) { + const int d = 128; + char buf[256]; + float input[128], output[128]; + float mse, cosv, ni, no; + + printf("=== TurboQuant C Round-Trip Test ===\n\n"); + + /* Test 1: basis vector */ + memset(input, 0, sizeof(input)); + input[0] = 1.0f; + quantize_row_turbo3_0_ref(input, buf, d); + dequantize_row_turbo3_0(buf, output, d); + printf("Test 1 (turbo3): e0 = [1, 0, ...]\n"); + printf(" In: [%.6f, %.6f, %.6f, %.6f]\n", input[0], input[1], input[2], input[3]); + printf(" Out: [%.6f, %.6f, %.6f, %.6f]\n", output[0], output[1], output[2], output[3]); + mse = cosv = ni = no = 0; + for (int i = 0; i < d; i++) { mse += (input[i]-output[i])*(input[i]-output[i]); cosv += input[i]*output[i]; ni += input[i]*input[i]; no += output[i]*output[i]; } + printf(" MSE=%.8f Cosine=%.6f OutNorm=%.6f\n\n", mse/d, ni > 0 && no > 0 ? cosv/sqrtf(ni)/sqrtf(no) : 0, sqrtf(no)); + + /* Test 2: large-norm vector */ + for (int i = 0; i < d; i++) input[i] = sinf(i*0.1f+0.5f) * 10.0f; + quantize_row_turbo3_0_ref(input, buf, d); + dequantize_row_turbo3_0(buf, output, d); + printf("Test 2 (turbo3): sin*10\n"); + printf(" In: [%.4f, %.4f, %.4f, %.4f]\n", input[0], input[1], input[2], input[3]); + printf(" Out: [%.4f, %.4f, %.4f, %.4f]\n", output[0], output[1], output[2], output[3]); + mse = cosv = ni = no = 0; + for (int i = 0; i < d; i++) { mse += (input[i]-output[i])*(input[i]-output[i]); cosv += input[i]*output[i]; ni += input[i]*input[i]; no += output[i]*output[i]; } + printf(" MSE=%.8f Cosine=%.6f InNorm=%.2f OutNorm=%.2f\n\n", mse/d, cosv/sqrtf(ni)/sqrtf(no), sqrtf(ni), sqrtf(no)); + + /* Test 3: turbo4 */ + for (int i = 0; i < d; i++) input[i] = cosf(i*0.2f) * 5.0f; + quantize_row_turbo4_0_ref(input, buf, d); + dequantize_row_turbo4_0(buf, output, d); + printf("Test 3 (turbo4): cos*5\n"); + printf(" In: [%.4f, %.4f, %.4f, %.4f]\n", input[0], input[1], input[2], input[3]); + printf(" Out: [%.4f, %.4f, %.4f, %.4f]\n", output[0], output[1], output[2], output[3]); + mse = cosv = ni = no = 0; + for (int i = 0; i < d; i++) { mse += (input[i]-output[i])*(input[i]-output[i]); cosv += input[i]*output[i]; ni += input[i]*input[i]; no += output[i]*output[i]; } + printf(" MSE=%.8f Cosine=%.6f\n\n", mse/d, cosv/sqrtf(ni)/sqrtf(no)); + + printf("=== Done ===\n"); + return 0; +} diff --git a/tools/llama-bench/llama-bench.cpp b/tools/llama-bench/llama-bench.cpp index 0a23f698537..60c2f4110e8 100644 --- a/tools/llama-bench/llama-bench.cpp +++ b/tools/llama-bench/llama-bench.cpp @@ -483,6 +483,15 @@ static ggml_type ggml_type_from_name(const std::string & s) { if (s == "iq4_nl") { return GGML_TYPE_IQ4_NL; } + if (s == "turbo2") { + return GGML_TYPE_TURBO2_0; + } + if (s == "turbo3") { + return GGML_TYPE_TURBO3_0; + } + if (s == "turbo4") { + return GGML_TYPE_TURBO4_0; + } return GGML_TYPE_COUNT; } diff --git a/tools/quantize/quantize.cpp b/tools/quantize/quantize.cpp index b727c9dd39f..6a69a21fa61 100644 --- a/tools/quantize/quantize.cpp +++ b/tools/quantize/quantize.cpp @@ -42,6 +42,8 @@ static const std::vector QUANT_OPTIONS = { { "IQ1_M", LLAMA_FTYPE_MOSTLY_IQ1_M, " 1.75 bpw quantization", }, { "TQ1_0", LLAMA_FTYPE_MOSTLY_TQ1_0, " 1.69 bpw ternarization", }, { "TQ2_0", LLAMA_FTYPE_MOSTLY_TQ2_0, " 2.06 bpw ternarization", }, + { "TQ3_1S", LLAMA_FTYPE_MOSTLY_TQ3_1S, " 4.00 bpw WHT-rotated", }, + { "TQ4_1S", LLAMA_FTYPE_MOSTLY_TQ4_1S, " 5.00 bpw WHT-rotated", }, { "Q2_K", LLAMA_FTYPE_MOSTLY_Q2_K, " 2.96G, +3.5199 ppl @ Llama-3-8B", }, { "Q2_K_S", LLAMA_FTYPE_MOSTLY_Q2_K_S, " 2.96G, +3.1836 ppl @ Llama-3-8B", }, { "IQ3_XXS", LLAMA_FTYPE_MOSTLY_IQ3_XXS, " 3.06 bpw quantization", }, diff --git a/tools/server/server-context.cpp b/tools/server/server-context.cpp index bd2552f75f2..268ae5d4307 100644 --- a/tools/server/server-context.cpp +++ b/tools/server/server-context.cpp @@ -758,8 +758,8 @@ struct server_context_impl { int n_ctx_slot = llama_n_ctx_seq(ctx); if (n_ctx_slot > n_ctx_train) { - SRV_WRN("the slot context (%d) exceeds the training context of the model (%d) - capping\n", n_ctx_slot, n_ctx_train); - n_ctx_slot = n_ctx_train; + SRV_WRN("the slot context (%d) exceeds the training context of the model (%d) - using rope scaling to extend\n", n_ctx_slot, n_ctx_train); + // Do not cap: caller has configured rope scaling (--rope-scale / --rope-scaling yarn) to handle extended context. } slots.clear();