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frame_buffer.qsf
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110 lines (108 loc) · 5.38 KB
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2018 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
# Date created = 23:24:01 October 30, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# frame_buffer_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone 10 LP"
set_global_assignment -name DEVICE 10CL025YE144I7G
set_global_assignment -name TOP_LEVEL_ENTITY frame_buffer_top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:24:01 OCTOBER 30, 2019"
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_location_assignment PIN_23 -to clk_50
set_location_assignment PIN_106 -to tmds[0]
set_location_assignment PIN_105 -to tmds[1]
set_location_assignment PIN_98 -to tmds[2]
set_location_assignment PIN_7 -to tmds[3]
set_location_assignment PIN_100 -to tmds[4]
set_location_assignment PIN_99 -to tmds[5]
set_location_assignment PIN_103 -to tmds[6]
set_location_assignment PIN_101 -to tmds[7]
set_global_assignment -name ENABLE_OCT_DONE OFF
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_location_assignment PIN_28 -to addr[0]
set_location_assignment PIN_31 -to addr[1]
set_location_assignment PIN_32 -to addr[2]
set_location_assignment PIN_33 -to addr[3]
set_location_assignment PIN_39 -to addr[4]
set_location_assignment PIN_42 -to addr[5]
set_location_assignment PIN_43 -to addr[6]
set_location_assignment PIN_44 -to addr[7]
set_location_assignment PIN_46 -to addr[8]
set_location_assignment PIN_49 -to addr[9]
set_location_assignment PIN_50 -to addr[10]
set_location_assignment PIN_51 -to addr[11]
set_location_assignment PIN_58 -to dq[0]
set_location_assignment PIN_59 -to dq[1]
set_location_assignment PIN_60 -to dq[2]
set_location_assignment PIN_65 -to dq[3]
set_location_assignment PIN_66 -to dq[4]
set_location_assignment PIN_67 -to dq[5]
set_location_assignment PIN_68 -to dq[6]
set_location_assignment PIN_69 -to dq[7]
set_location_assignment PIN_71 -to ba[0]
set_location_assignment PIN_72 -to ba[1]
set_location_assignment PIN_80 -to cas_n
set_location_assignment PIN_85 -to dqm
set_location_assignment PIN_83 -to ras_n
set_location_assignment PIN_77 -to we_n
set_location_assignment PIN_24 -to key[0]
set_location_assignment PIN_25 -to key[1]
set_location_assignment PIN_76 -to clk_n
set_global_assignment -name VERILOG_FILE altddio_out1.v
set_global_assignment -name VERILOG_FILE sopc/synthesis/sopc.v
set_global_assignment -name QSYS_FILE sopc.qsys
set_global_assignment -name BDF_FILE frame_buffer_top.bdf
set_global_assignment -name VERILOG_FILE hdmi_any.v
set_global_assignment -name VERILOG_FILE rgb8_rgb24.v
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top