mico_cpu/msg_file.log at master · Visual-e/mico_cpu · GitHub

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SCUBA, Version Diamond (64-bit) 3.10.1.112
Wed Nov 29 00:28:55 2017

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.

BEGIN SCUBA Module Synthesis

    Issued command   : D:\dev\lattice\lscc\diamond\3.10_x64\ispfpga\bin\nt64\scuba.exe -w -n main_pll -lang verilog -synth lse -arch xo2c00 -type pll -fin 50 -fclkop 74 -fclkop_tol 2.0 -fclkos 100 -fclkos_tol 0.0 -trimp 0 -phasep 0 -trimp_r -trims 0 -phases 0 -trims_r -phase_cntl STATIC -fb_mode 1 -lock
    Circuit name     : main_pll
    Module type      : pll
    Module Version   : 5.7
    Ports            :
    Inputs       : CLKI
    Outputs      : CLKOP, CLKOS, LOCK
    I/O buffer       : not inserted
    EDIF output      : main_pll.edn
    Verilog output   : main_pll.v
    Verilog template : main_pll_tmpl.v
    Verilog purpose  : for synthesis and simulation
    Bus notation     : big endian
    Report output    : main_pll.srp
    Estimated Resource Usage:

END   SCUBA Module Synthesis