From 1540d8cbf8134efa69a691de9dc8b760152de1fa Mon Sep 17 00:00:00 2001 From: zhangrj Date: Sat, 26 Jul 2025 16:48:19 +0800 Subject: [PATCH 1/7] tlb ptw single hit/miss testcase added --- .../classical_version/env/itlb_wrapper.py | 131 ++++++++++++++++++ .../test_tlb_receive_ptw_resp.py | 130 ++++++++++++++++- utils/__init__.py | 0 utils/value_util.py | 2 + 4 files changed, 262 insertions(+), 1 deletion(-) create mode 100644 utils/__init__.py create mode 100644 utils/value_util.py diff --git a/ut_frontend/itlb/classical_version/env/itlb_wrapper.py b/ut_frontend/itlb/classical_version/env/itlb_wrapper.py index a833cb23..035ad401 100644 --- a/ut_frontend/itlb/classical_version/env/itlb_wrapper.py +++ b/ut_frontend/itlb/classical_version/env/itlb_wrapper.py @@ -20,6 +20,7 @@ import toffee.funcov as fc from dut.TLB import * +from utils.value_util import other_than from .itlb_consts import * from queue import Queue from comm import get_version_checker, get_out_dir, UT_FCOV @@ -414,6 +415,136 @@ def rand_ptw_resp(self, vpn, asid, s2xlate): # TODO return randPPN + def init_dut_for_nostage_hit(self, vpn, asid, ppn, ppn_low): + # prepare data + addr_low = vpn & 0b111 + ## ctrl signals + self.ctrl.io_ptw_resp_valid.value = 1 + self.ctrl.io_ptw_resp_bits_s2xlate.value = 0b00 + # initialize conditions + self.ptw_resp_s1.entry_tag.value = vpn >> 3 + self.ptw_resp_s1.entry_asid.value = asid + self.ptw_resp_s1.entry_vmid.value = DONTCARE + self.ptw_resp_s1.entry_n.value = UNUSED0 + self.ptw_resp_s1.entry_pbmt.value = UNUSED0 + self.ptw_resp_s1.entry_perm_d.value = UNUSED0 + self.ptw_resp_s1.entry_perm_a.value = UNUSED0 + self.ptw_resp_s1.entry_perm_g.value = UNUSED0 + self.ptw_resp_s1.entry_perm_u.value = UNUSED0 + self.ptw_resp_s1.entry_perm_x.value = UNUSED1 + self.ptw_resp_s1.entry_perm_w.value = UNUSED0 + self.ptw_resp_s1.entry_perm_r.value = UNUSED0 + self.ptw_resp_s1.entry_level.value = UNUSED0 + self.ptw_resp_s1.entry_v.value = 1 + self.ptw_resp_s1.entry_ppn.value = ppn >> 3 + self.ptw_resp_s1.addr_low.value = addr_low + ppn_low_dict = { + 0: self.ptw_resp_s1.ppn_low_0, + 1: self.ptw_resp_s1.ppn_low_1, + 2: self.ptw_resp_s1.ppn_low_2, + 3: self.ptw_resp_s1.ppn_low_3, + 4: self.ptw_resp_s1.ppn_low_4, + 5: self.ptw_resp_s1.ppn_low_5, + 6: self.ptw_resp_s1.ppn_low_6, + 7: self.ptw_resp_s1.ppn_low_7 + } + valididx_dict = { + 0: self.ptw_resp_s1.valididx_0, + 1: self.ptw_resp_s1.valididx_1, + 2: self.ptw_resp_s1.valididx_2, + 3: self.ptw_resp_s1.valididx_3, + 4: self.ptw_resp_s1.valididx_4, + 5: self.ptw_resp_s1.valididx_5, + 6: self.ptw_resp_s1.valididx_6, + 7: self.ptw_resp_s1.valididx_7 + } + pteidx_dict = { + 0: self.ptw_resp_s1.pteidx_0, + 1: self.ptw_resp_s1.pteidx_1, + 2: self.ptw_resp_s1.pteidx_2, + 3: self.ptw_resp_s1.pteidx_3, + 4: self.ptw_resp_s1.pteidx_4, + 5: self.ptw_resp_s1.pteidx_5, + 6: self.ptw_resp_s1.pteidx_6, + 7: self.ptw_resp_s1.pteidx_7 + } + for i in range(8): + if i == addr_low: + ppn_low_dict[i].value = ppn & 0b111 + valididx_dict[i].value = 1 + else: + ppn_low_dict[i].value = ppn_low[i] + valididx_dict[i].value = 0 + pteidx_dict[addr_low].value = 1 + self.ptw_resp_s1.pf.value = UNUSED0 + self.ptw_resp_s1.af.value = UNUSED0 + + + def init_dut_for_nostage_miss(self, vpn, asid, ppn, ppn_low): + # prepare data + addr_low = vpn & 0b111 + ## ctrl signals + self.ctrl.io_ptw_resp_valid.value = 1 + self.ctrl.io_ptw_resp_bits_s2xlate.value = 0b00 + # initialize conditions + self.ptw_resp_s1.entry_tag.value = other_than(vpn >> 3) + self.ptw_resp_s1.entry_asid.value = asid + self.ptw_resp_s1.entry_vmid.value = DONTCARE + self.ptw_resp_s1.entry_n.value = UNUSED0 + self.ptw_resp_s1.entry_pbmt.value = UNUSED0 + self.ptw_resp_s1.entry_perm_d.value = UNUSED0 + self.ptw_resp_s1.entry_perm_a.value = UNUSED0 + self.ptw_resp_s1.entry_perm_g.value = UNUSED0 + self.ptw_resp_s1.entry_perm_u.value = UNUSED0 + self.ptw_resp_s1.entry_perm_x.value = UNUSED1 + self.ptw_resp_s1.entry_perm_w.value = UNUSED0 + self.ptw_resp_s1.entry_perm_r.value = UNUSED0 + self.ptw_resp_s1.entry_level.value = UNUSED0 + self.ptw_resp_s1.entry_v.value = 1 + self.ptw_resp_s1.entry_ppn.value = ppn >> 3 + self.ptw_resp_s1.addr_low.value = addr_low + ppn_low_dict = { + 0: self.ptw_resp_s1.ppn_low_0, + 1: self.ptw_resp_s1.ppn_low_1, + 2: self.ptw_resp_s1.ppn_low_2, + 3: self.ptw_resp_s1.ppn_low_3, + 4: self.ptw_resp_s1.ppn_low_4, + 5: self.ptw_resp_s1.ppn_low_5, + 6: self.ptw_resp_s1.ppn_low_6, + 7: self.ptw_resp_s1.ppn_low_7 + } + valididx_dict = { + 0: self.ptw_resp_s1.valididx_0, + 1: self.ptw_resp_s1.valididx_1, + 2: self.ptw_resp_s1.valididx_2, + 3: self.ptw_resp_s1.valididx_3, + 4: self.ptw_resp_s1.valididx_4, + 5: self.ptw_resp_s1.valididx_5, + 6: self.ptw_resp_s1.valididx_6, + 7: self.ptw_resp_s1.valididx_7 + } + pteidx_dict = { + 0: self.ptw_resp_s1.pteidx_0, + 1: self.ptw_resp_s1.pteidx_1, + 2: self.ptw_resp_s1.pteidx_2, + 3: self.ptw_resp_s1.pteidx_3, + 4: self.ptw_resp_s1.pteidx_4, + 5: self.ptw_resp_s1.pteidx_5, + 6: self.ptw_resp_s1.pteidx_6, + 7: self.ptw_resp_s1.pteidx_7 + } + for i in range(8): + if i == addr_low: + ppn_low_dict[i].value = ppn & 0b111 + valididx_dict[i].value = 1 + else: + ppn_low_dict[i].value = ppn_low[i] + valididx_dict[i].value = 0 + pteidx_dict[addr_low].value = 1 + self.ptw_resp_s1.pf.value = UNUSED0 + self.ptw_resp_s1.af.value = UNUSED0 + + class TLBrwWrapper(toffee.Bundle): """ Support TLB read/write only. diff --git a/ut_frontend/itlb/classical_version/test_tlb_receive_ptw_resp.py b/ut_frontend/itlb/classical_version/test_tlb_receive_ptw_resp.py index 23aee122..70af9e91 100644 --- a/ut_frontend/itlb/classical_version/test_tlb_receive_ptw_resp.py +++ b/ut_frontend/itlb/classical_version/test_tlb_receive_ptw_resp.py @@ -64,4 +64,132 @@ def test_receive_ptw_resp_nonstage(tlb_fixture): assert(tlb.requestor_0.resp.paddr_0.value == ((ppn << 12) | offset)) assert(tlb.requestor_0.resp.miss.value == 0) # reset - tlb.reset() \ No newline at end of file + tlb.reset() + + +def test_receive_ptw_resp_nonstage_single_hit(tlb_fixture): + """ + no stage，单次miss + """ + # connect to fixture + tlb = tlb_fixture + tlb.set_default_value() + # reset + tlb.reset() + + # add clock + tlb.dut.xclock.StepRis(lambda _: g.sample()) + + ################################################################################ + # requestor_0 + ################################################################################ + # generate signals + signals = _gen_signal_rand() + # initialize dut with signals + tlb.init_dut_for_nostage_hit(signals["vpn"], signals["asid"], signals["ppn"], signals["ppn_low"]) + tlb.csr.satp.asid.value = signals["asid"] + # step to next cycle + tlb.dut.Step() + # check whether PTW resp is stored + tlb.requestor_0.req.valid.value = 1 + tlb.requestor_1.req.valid.value = 0 + tlb.requestor_2.req.valid.value = 0 + tlb.requestor_0.req.bits_vaddr.value = (signals["vpn"] << 12) | signals["offset"] + # step to next cycle + tlb.dut.Step(2) + # assert result + assert (tlb.requestor_0.resp.paddr_0.value == ((signals["ppn"] << 12) | signals["offset"])) + assert (tlb.requestor_0.resp.miss.value == 0) + + ################################################################################ + # requestor_1 + ################################################################################ + # generate signals + signals = _gen_signal_rand() + # initialize dut with signals + tlb.init_dut_for_nostage_hit(signals["vpn"], signals["asid"], signals["ppn"], signals["ppn_low"]) + tlb.csr.satp.asid.value = signals["asid"] + # step to next cycle + tlb.dut.Step() + # check whether PTW resp is stored + tlb.requestor_0.req.valid.value = 0 + tlb.requestor_1.req.valid.value = 1 + tlb.requestor_2.req.valid.value = 0 + tlb.requestor_1.req.bits_vaddr.value = (signals["vpn"] << 12) | signals["offset"] + # step to next cycle + tlb.dut.Step(2) + # assert result + assert (tlb.requestor_1.resp.paddr_0.value == ((signals["ppn"] << 12) | signals["offset"])) + assert (tlb.requestor_1.resp.miss.value == 0) + + +def test_receive_ptw_resp_nonstage_single_miss(tlb_fixture): + """ + no stage，单次miss + """ + # connect to fixture + tlb = tlb_fixture + tlb.set_default_value() + # reset + tlb.reset() + + # add clock + tlb.dut.xclock.StepRis(lambda _: g.sample()) + + ################################################################################ + # requestor_0 + ################################################################################ + # generate signals + signals = _gen_signal_rand() + # initialize dut with signals + tlb.init_dut_for_nostage_miss(signals["vpn"], signals["asid"], signals["ppn"], signals["ppn_low"]) + tlb.csr.satp.asid.value = signals["asid"] + # step to next cycle + tlb.dut.Step() + # check whether PTW resp is stored + tlb.requestor_0.req.valid.value = 1 + tlb.requestor_1.req.valid.value = 0 + tlb.requestor_2.req.valid.value = 0 + tlb.requestor_0.req.bits_vaddr.value = (signals["vpn"] << 12) | signals["offset"] + # step to next cycle + tlb.dut.Step(2) + # assert result + assert (tlb.requestor_0.resp.miss.value == 1) + + ################################################################################ + # requestor_1 + ################################################################################ + # generate signals + signals = _gen_signal_rand() + # initialize dut with signals + tlb.init_dut_for_nostage_miss(signals["vpn"], signals["asid"], signals["ppn"], signals["ppn_low"]) + tlb.csr.satp.asid.value = signals["asid"] + # step to next cycle + tlb.dut.Step() + # check whether PTW resp is stored + tlb.requestor_0.req.valid.value = 0 + tlb.requestor_1.req.valid.value = 1 + tlb.requestor_2.req.valid.value = 0 + tlb.requestor_1.req.bits_vaddr.value = (signals["vpn"] << 12) | signals["offset"] + # step to next cycle + tlb.dut.Step(2) + # assert result + assert (tlb.requestor_1.resp.miss.value == 1) + + +def _gen_signal_rand() -> dict: + vaddr = random.randint(0, 2 ** 50 - 1) + asid = random.randint(0, 2 ** 16 - 1) + vpn = vaddr >> 12 + offset = vaddr & 0xfff + ppn = random.randint(0, 2 ** 36 - 1) + ppn_low = [random.randint(0, 2 ** 3 - 1) for _ in range(8)] + valid_idx = [random.choice([0, 1]) for _ in range(8)] + return { + "asid": asid, + "vpn": vpn, + "offset": offset, + "ppn": ppn, + "ppn_low": ppn_low, + "valid_idx": valid_idx, + } \ No newline at end of file diff --git a/utils/__init__.py b/utils/__init__.py new file mode 100644 index 00000000..e69de29b diff --git a/utils/value_util.py b/utils/value_util.py new file mode 100644 index 00000000..f7c8844a --- /dev/null +++ b/utils/value_util.py @@ -0,0 +1,2 @@ +def other_than(value): + return value ^ 1 From ad83d3016226a6d110393d1186dea0c8933de212 Mon Sep 17 00:00:00 2001 From: zhangrj Date: Wed, 30 Jul 2025 17:19:46 +0800 Subject: [PATCH 2/7] tlb ptw single hit/miss testcase added --- .../classical_version/env/itlb_wrapper.py | 27 +++- .../test_tlb_receive_ptw_resp.py | 126 +++++++++++++----- utils/__init__.py | 0 utils/value_util.py | 2 - 4 files changed, 115 insertions(+), 40 deletions(-) delete mode 100644 utils/__init__.py delete mode 100644 utils/value_util.py diff --git a/ut_frontend/itlb/classical_version/env/itlb_wrapper.py b/ut_frontend/itlb/classical_version/env/itlb_wrapper.py index 035ad401..a3e36522 100644 --- a/ut_frontend/itlb/classical_version/env/itlb_wrapper.py +++ b/ut_frontend/itlb/classical_version/env/itlb_wrapper.py @@ -20,7 +20,7 @@ import toffee.funcov as fc from dut.TLB import * -from utils.value_util import other_than +from ut_frontend.itlb.classical_version.env.itlb_utils import other_than from .itlb_consts import * from queue import Queue from comm import get_version_checker, get_out_dir, UT_FCOV @@ -281,6 +281,14 @@ def reset(self): self.dut.reset.value = 0 # print(">>> RESET FINISHED !") + def cleanup_requestor(self, requestor: int): + self.reset() + self.flushPipe[requestor].value = 1 + self.dut.Step() + self.flushPipe[requestor].value = 0 + self.dut.Step(2) + # print(f">>> CLEANUP requestor_{i} FINISHED !") + def gene_rand_TLBreq(self): """ generate random TLB request @@ -289,6 +297,23 @@ def gene_rand_TLBreq(self): req_vaddr = random.randint(0, 2 ** 50 - 1) return req_valid, req_vaddr + def gene_rand_TLBsignal_batch(self) -> dict: + vaddr = random.randint(0, 2 ** 50 - 1) + asid = random.randint(0, 2 ** 16 - 1) + vpn = vaddr >> 12 + offset = vaddr & 0xfff + ppn = random.randint(0, 2 ** 36 - 1) + ppn_low = [random.randint(0, 2 ** 3 - 1) for _ in range(8)] + valid_idx = [random.choice([0, 1]) for _ in range(8)] + return { + "asid": asid, + "vpn": vpn, + "offset": offset, + "ppn": ppn, + "ppn_low": ppn_low, + "valid_idx": valid_idx, + } + def rand_req0(self): """ send random TLB request from requestor0 diff --git a/ut_frontend/itlb/classical_version/test_tlb_receive_ptw_resp.py b/ut_frontend/itlb/classical_version/test_tlb_receive_ptw_resp.py index 70af9e91..25dc4c36 100644 --- a/ut_frontend/itlb/classical_version/test_tlb_receive_ptw_resp.py +++ b/ut_frontend/itlb/classical_version/test_tlb_receive_ptw_resp.py @@ -15,9 +15,12 @@ from .env import * import inspect +ROUND_NUM = 1000 +ROUND_SIZE = 30 + ### CASE EXAMPLE # Running the following test case will show a pass: -def test_receive_ptw_resp_nonstage(tlb_fixture): +def _test_receive_ptw_resp_nonstage(tlb_fixture): """ Func: receive PTW response under nonstage condition and stored it into TLB entry subfunc1: TODO @@ -80,17 +83,31 @@ def test_receive_ptw_resp_nonstage_single_hit(tlb_fixture): # add clock tlb.dut.xclock.StepRis(lambda _: g.sample()) - ################################################################################ - # requestor_0 - ################################################################################ + for _ in range(ROUND_NUM): + for _ in range(ROUND_SIZE): + _do_test_receive_ptw_resp_nonstage_hit_requestor_0(tlb) + tlb.cleanup_requestor(0) + + for _ in range(ROUND_NUM): + for _ in range(ROUND_SIZE): + _do_test_receive_ptw_resp_nonstage_hit_requestor_1(tlb) + tlb.cleanup_requestor(1) + + for _ in range(ROUND_NUM): + for _ in range(ROUND_SIZE): + _do_test_receive_ptw_resp_nonstage_hit_requestor_2(tlb) + tlb.cleanup_requestor(2) + + +def _do_test_receive_ptw_resp_nonstage_hit_requestor_0(tlb): # generate signals - signals = _gen_signal_rand() + signals = tlb.gene_rand_TLBsignal_batch() # initialize dut with signals tlb.init_dut_for_nostage_hit(signals["vpn"], signals["asid"], signals["ppn"], signals["ppn_low"]) tlb.csr.satp.asid.value = signals["asid"] # step to next cycle tlb.dut.Step() - # check whether PTW resp is stored + # switch requestor tlb.requestor_0.req.valid.value = 1 tlb.requestor_1.req.valid.value = 0 tlb.requestor_2.req.valid.value = 0 @@ -101,17 +118,16 @@ def test_receive_ptw_resp_nonstage_single_hit(tlb_fixture): assert (tlb.requestor_0.resp.paddr_0.value == ((signals["ppn"] << 12) | signals["offset"])) assert (tlb.requestor_0.resp.miss.value == 0) - ################################################################################ - # requestor_1 - ################################################################################ + +def _do_test_receive_ptw_resp_nonstage_hit_requestor_1(tlb): # generate signals - signals = _gen_signal_rand() + signals = tlb.gene_rand_TLBsignal_batch() # initialize dut with signals tlb.init_dut_for_nostage_hit(signals["vpn"], signals["asid"], signals["ppn"], signals["ppn_low"]) tlb.csr.satp.asid.value = signals["asid"] # step to next cycle tlb.dut.Step() - # check whether PTW resp is stored + # switch requestor tlb.requestor_0.req.valid.value = 0 tlb.requestor_1.req.valid.value = 1 tlb.requestor_2.req.valid.value = 0 @@ -123,6 +139,27 @@ def test_receive_ptw_resp_nonstage_single_hit(tlb_fixture): assert (tlb.requestor_1.resp.miss.value == 0) +def _do_test_receive_ptw_resp_nonstage_hit_requestor_2(tlb): + # generate signals + signals = tlb.gene_rand_TLBsignal_batch() + # initialize dut with signals + tlb.init_dut_for_nostage_hit(signals["vpn"], signals["asid"], signals["ppn"], signals["ppn_low"]) + tlb.csr.satp.asid.value = signals["asid"] + # step to next cycle + tlb.dut.Step() + # switch requestor + tlb.requestor_0.req.valid.value = 0 + tlb.requestor_1.req.valid.value = 0 + tlb.requestor_2.req.valid.value = 1 + tlb.ctrl.io_requestor_2_resp_ready.value = 1 + tlb.requestor_2.req.bits_vaddr.value = (signals["vpn"] << 12) | signals["offset"] + # step to next cycle + tlb.dut.Step(2) + # assert result + assert (tlb.requestor_2.resp.paddr_0.value == ((signals["ppn"] << 12) | signals["offset"])) + assert (tlb.requestor_2.resp.miss.value == 0) + + def test_receive_ptw_resp_nonstage_single_miss(tlb_fixture): """ no stage，单次miss @@ -136,17 +173,31 @@ def test_receive_ptw_resp_nonstage_single_miss(tlb_fixture): # add clock tlb.dut.xclock.StepRis(lambda _: g.sample()) - ################################################################################ - # requestor_0 - ################################################################################ + for _ in range(ROUND_NUM): + for _ in range(ROUND_SIZE): + _do_test_receive_ptw_resp_nonstage_miss_requestor_0(tlb) + tlb.cleanup_requestor(0) + + for _ in range(ROUND_NUM): + for _ in range(ROUND_SIZE): + _do_test_receive_ptw_resp_nonstage_miss_requestor_1(tlb) + tlb.cleanup_requestor(1) + + for _ in range(ROUND_NUM): + for _ in range(ROUND_SIZE): + _do_test_receive_ptw_resp_nonstage_miss_requestor_2(tlb) + tlb.cleanup_requestor(2) # cleanup requestor 2 after each missing + + +def _do_test_receive_ptw_resp_nonstage_miss_requestor_0(tlb): # generate signals - signals = _gen_signal_rand() + signals = tlb.gene_rand_TLBsignal_batch() # initialize dut with signals tlb.init_dut_for_nostage_miss(signals["vpn"], signals["asid"], signals["ppn"], signals["ppn_low"]) tlb.csr.satp.asid.value = signals["asid"] # step to next cycle tlb.dut.Step() - # check whether PTW resp is stored + # switch requestor tlb.requestor_0.req.valid.value = 1 tlb.requestor_1.req.valid.value = 0 tlb.requestor_2.req.valid.value = 0 @@ -156,17 +207,16 @@ def test_receive_ptw_resp_nonstage_single_miss(tlb_fixture): # assert result assert (tlb.requestor_0.resp.miss.value == 1) - ################################################################################ - # requestor_1 - ################################################################################ + +def _do_test_receive_ptw_resp_nonstage_miss_requestor_1(tlb): # generate signals - signals = _gen_signal_rand() + signals = tlb.gene_rand_TLBsignal_batch() # initialize dut with signals tlb.init_dut_for_nostage_miss(signals["vpn"], signals["asid"], signals["ppn"], signals["ppn_low"]) tlb.csr.satp.asid.value = signals["asid"] # step to next cycle tlb.dut.Step() - # check whether PTW resp is stored + # switch requestor tlb.requestor_0.req.valid.value = 0 tlb.requestor_1.req.valid.value = 1 tlb.requestor_2.req.valid.value = 0 @@ -177,19 +227,21 @@ def test_receive_ptw_resp_nonstage_single_miss(tlb_fixture): assert (tlb.requestor_1.resp.miss.value == 1) -def _gen_signal_rand() -> dict: - vaddr = random.randint(0, 2 ** 50 - 1) - asid = random.randint(0, 2 ** 16 - 1) - vpn = vaddr >> 12 - offset = vaddr & 0xfff - ppn = random.randint(0, 2 ** 36 - 1) - ppn_low = [random.randint(0, 2 ** 3 - 1) for _ in range(8)] - valid_idx = [random.choice([0, 1]) for _ in range(8)] - return { - "asid": asid, - "vpn": vpn, - "offset": offset, - "ppn": ppn, - "ppn_low": ppn_low, - "valid_idx": valid_idx, - } \ No newline at end of file +def _do_test_receive_ptw_resp_nonstage_miss_requestor_2(tlb): + # generate signals + signals = tlb.gene_rand_TLBsignal_batch() + # initialize dut with signals + tlb.init_dut_for_nostage_miss(signals["vpn"], signals["asid"], signals["ppn"], signals["ppn_low"]) + tlb.csr.satp.asid.value = signals["asid"] + # step to next cycle + tlb.dut.Step() + # switch requestor + tlb.requestor_0.req.valid.value = 0 + tlb.requestor_1.req.valid.value = 0 + tlb.requestor_2.req.valid.value = 1 + tlb.ctrl.io_requestor_2_resp_ready.value = 1 + tlb.requestor_2.req.bits_vaddr.value = (signals["vpn"] << 12) | signals["offset"] + # step to next cycle + tlb.dut.Step(2) + # assert result + assert (tlb.requestor_2.resp.miss.value == 1) diff --git a/utils/__init__.py b/utils/__init__.py deleted file mode 100644 index e69de29b..00000000 diff --git a/utils/value_util.py b/utils/value_util.py deleted file mode 100644 index f7c8844a..00000000 --- a/utils/value_util.py +++ /dev/null @@ -1,2 +0,0 @@ -def other_than(value): - return value ^ 1 From 7344f960574a8b4b7cadef2467c107b77ad0090e Mon Sep 17 00:00:00 2001 From: zhangrj Date: Wed, 30 Jul 2025 17:21:11 +0800 Subject: [PATCH 3/7] tlb utils added --- ut_frontend/itlb/classical_version/env/itlb_utils.py | 2 ++ 1 file changed, 2 insertions(+) create mode 100644 ut_frontend/itlb/classical_version/env/itlb_utils.py diff --git a/ut_frontend/itlb/classical_version/env/itlb_utils.py b/ut_frontend/itlb/classical_version/env/itlb_utils.py new file mode 100644 index 00000000..f7c8844a --- /dev/null +++ b/ut_frontend/itlb/classical_version/env/itlb_utils.py @@ -0,0 +1,2 @@ +def other_than(value): + return value ^ 1 From 2cf1f624dc9c99e86961cde47d9b62dbb0a89926 Mon Sep 17 00:00:00 2001 From: zhangrj Date: Wed, 30 Jul 2025 17:22:32 +0800 Subject: [PATCH 4/7] recover testcase test_receive_ptw_resp_nonstage --- ut_frontend/itlb/classical_version/test_tlb_receive_ptw_resp.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ut_frontend/itlb/classical_version/test_tlb_receive_ptw_resp.py b/ut_frontend/itlb/classical_version/test_tlb_receive_ptw_resp.py index 25dc4c36..2510c940 100644 --- a/ut_frontend/itlb/classical_version/test_tlb_receive_ptw_resp.py +++ b/ut_frontend/itlb/classical_version/test_tlb_receive_ptw_resp.py @@ -20,7 +20,7 @@ ### CASE EXAMPLE # Running the following test case will show a pass: -def _test_receive_ptw_resp_nonstage(tlb_fixture): +def test_receive_ptw_resp_nonstage(tlb_fixture): """ Func: receive PTW response under nonstage condition and stored it into TLB entry subfunc1: TODO From 2a7b3ada19c5892002b7443ae56c4430f806f349 Mon Sep 17 00:00:00 2001 From: zhangrj Date: Thu, 31 Jul 2025 19:09:09 +0800 Subject: [PATCH 5/7] valid-ready cases added, testcase refactored --- .../test_tlb_receive_ptw_resp.py | 251 +++++++++++++++++- 1 file changed, 248 insertions(+), 3 deletions(-) diff --git a/ut_frontend/itlb/classical_version/test_tlb_receive_ptw_resp.py b/ut_frontend/itlb/classical_version/test_tlb_receive_ptw_resp.py index 2510c940..96b3389f 100644 --- a/ut_frontend/itlb/classical_version/test_tlb_receive_ptw_resp.py +++ b/ut_frontend/itlb/classical_version/test_tlb_receive_ptw_resp.py @@ -70,9 +70,9 @@ def test_receive_ptw_resp_nonstage(tlb_fixture): tlb.reset() -def test_receive_ptw_resp_nonstage_single_hit(tlb_fixture): +def test_receive_ptw_resp_nonstage_single_hit_icache(tlb_fixture): """ - no stage，单次miss + no stage，单次hit """ # connect to fixture tlb = tlb_fixture @@ -93,6 +93,20 @@ def test_receive_ptw_resp_nonstage_single_hit(tlb_fixture): _do_test_receive_ptw_resp_nonstage_hit_requestor_1(tlb) tlb.cleanup_requestor(1) + +def test_receive_ptw_resp_nonstage_single_hit_ifu(tlb_fixture): + """ + no stage，单次hit + """ + # connect to fixture + tlb = tlb_fixture + tlb.set_default_value() + # reset + tlb.reset() + + # add clock + tlb.dut.xclock.StepRis(lambda _: g.sample()) + for _ in range(ROUND_NUM): for _ in range(ROUND_SIZE): _do_test_receive_ptw_resp_nonstage_hit_requestor_2(tlb) @@ -160,7 +174,7 @@ def _do_test_receive_ptw_resp_nonstage_hit_requestor_2(tlb): assert (tlb.requestor_2.resp.miss.value == 0) -def test_receive_ptw_resp_nonstage_single_miss(tlb_fixture): +def test_receive_ptw_resp_nonstage_single_miss_icache(tlb_fixture): """ no stage，单次miss """ @@ -183,6 +197,20 @@ def test_receive_ptw_resp_nonstage_single_miss(tlb_fixture): _do_test_receive_ptw_resp_nonstage_miss_requestor_1(tlb) tlb.cleanup_requestor(1) + +def test_receive_ptw_resp_nonstage_single_miss_ifu(tlb_fixture): + """ + no stage，单次miss + """ + # connect to fixture + tlb = tlb_fixture + tlb.set_default_value() + # reset + tlb.reset() + + # add clock + tlb.dut.xclock.StepRis(lambda _: g.sample()) + for _ in range(ROUND_NUM): for _ in range(ROUND_SIZE): _do_test_receive_ptw_resp_nonstage_miss_requestor_2(tlb) @@ -245,3 +273,220 @@ def _do_test_receive_ptw_resp_nonstage_miss_requestor_2(tlb): tlb.dut.Step(2) # assert result assert (tlb.requestor_2.resp.miss.value == 1) + + +def test_receive_ptw_resp_nonstage_valid_icache(tlb_fixture): + """ + no stage，valid有效性 + """ + # connect to fixture + tlb = tlb_fixture + tlb.set_default_value() + # reset + tlb.reset() + + # add clock + tlb.dut.xclock.StepRis(lambda _: g.sample()) + + for _ in range(ROUND_NUM): + for _ in range(ROUND_SIZE): + _do_test_receive_ptw_resp_nonstage_valid_requestor_0(tlb) + tlb.cleanup_requestor(0) + _do_test_receive_ptw_resp_nonstage_invalid_requestor_0(tlb) + tlb.cleanup_requestor(0) + + for _ in range(ROUND_NUM): + for _ in range(ROUND_SIZE): + _do_test_receive_ptw_resp_nonstage_valid_requestor_1(tlb) + tlb.cleanup_requestor(1) + _do_test_receive_ptw_resp_nonstage_invalid_requestor_1(tlb) + tlb.cleanup_requestor(1) + + +def test_receive_ptw_resp_nonstage_valid_ifu(tlb_fixture): + """ + no stage，valid-ready有效性 + """ + # connect to fixture + tlb = tlb_fixture + tlb.set_default_value() + # reset + tlb.reset() + + # add clock + tlb.dut.xclock.StepRis(lambda _: g.sample()) + + for _ in range(ROUND_NUM): + for _ in range(ROUND_SIZE): + _do_test_receive_ptw_resp_nonstage_valid_ready_requestor_2(tlb) + tlb.cleanup_requestor(2) + _do_test_receive_ptw_resp_nonstage_invalid_ready_requestor_2(tlb) + tlb.cleanup_requestor(2) + _do_test_receive_ptw_resp_nonstage_valid_busy_requestor_2(tlb) + tlb.cleanup_requestor(2) + _do_test_receive_ptw_resp_nonstage_invalid_busy_requestor_2(tlb) + tlb.cleanup_requestor(2) + + +def _do_test_receive_ptw_resp_nonstage_valid_requestor_0(tlb): + # generate signals + signals = tlb.gene_rand_TLBsignal_batch() + # initialize dut with signals + tlb.init_dut_for_nostage_hit(signals["vpn"], signals["asid"], signals["ppn"], signals["ppn_low"]) + tlb.csr.satp.asid.value = signals["asid"] + # step to next cycle + tlb.dut.Step() + # switch requestor + tlb.requestor_0.req.valid.value = 1 + tlb.requestor_1.req.valid.value = 0 + tlb.requestor_2.req.valid.value = 0 + tlb.requestor_0.req.bits_vaddr.value = (signals["vpn"] << 12) | signals["offset"] + # step to next cycle + tlb.dut.Step(2) + # assert result + assert (tlb.requestor_0.resp.paddr_0.value == ((signals["ppn"] << 12) | signals["offset"])) + assert (tlb.requestor_0.resp.miss.value == 0) + + +def _do_test_receive_ptw_resp_nonstage_invalid_requestor_0(tlb): + # generate signals + signals = tlb.gene_rand_TLBsignal_batch() + # initialize dut with signals + tlb.init_dut_for_nostage_miss(signals["vpn"], signals["asid"], signals["ppn"], signals["ppn_low"]) + tlb.csr.satp.asid.value = signals["asid"] + # step to next cycle + tlb.dut.Step() + # switch requestor + tlb.requestor_0.req.valid.value = 0 + tlb.requestor_1.req.valid.value = 0 + tlb.requestor_2.req.valid.value = 0 + tlb.requestor_0.req.bits_vaddr.value = (signals["vpn"] << 12) | signals["offset"] + # step to next cycle + tlb.dut.Step(2) + # assert result, no hit anyway + assert not (tlb.requestor_0.resp.miss.value == 0 and + tlb.requestor_0.resp.paddr_0.value == ((signals["ppn"] << 12) | signals["offset"])) + + +def _do_test_receive_ptw_resp_nonstage_valid_requestor_1(tlb): + # generate signals + signals = tlb.gene_rand_TLBsignal_batch() + # initialize dut with signals + tlb.init_dut_for_nostage_hit(signals["vpn"], signals["asid"], signals["ppn"], signals["ppn_low"]) + tlb.csr.satp.asid.value = signals["asid"] + # step to next cycle + tlb.dut.Step() + # switch requestor + tlb.requestor_0.req.valid.value = 0 + tlb.requestor_1.req.valid.value = 1 + tlb.requestor_2.req.valid.value = 0 + tlb.requestor_1.req.bits_vaddr.value = (signals["vpn"] << 12) | signals["offset"] + # step to next cycle + tlb.dut.Step(2) + # assert result + assert (tlb.requestor_1.resp.paddr_0.value == ((signals["ppn"] << 12) | signals["offset"])) + assert (tlb.requestor_1.resp.miss.value == 0) + + +def _do_test_receive_ptw_resp_nonstage_invalid_requestor_1(tlb): + # generate signals + signals = tlb.gene_rand_TLBsignal_batch() + # initialize dut with signals + tlb.init_dut_for_nostage_miss(signals["vpn"], signals["asid"], signals["ppn"], signals["ppn_low"]) + tlb.csr.satp.asid.value = signals["asid"] + # step to next cycle + tlb.dut.Step() + # switch requestor + tlb.requestor_0.req.valid.value = 0 + tlb.requestor_1.req.valid.value = 0 + tlb.requestor_2.req.valid.value = 0 + tlb.requestor_1.req.bits_vaddr.value = (signals["vpn"] << 12) | signals["offset"] + # step to next cycle + tlb.dut.Step(2) + # assert result, no hit anyway + assert not (tlb.requestor_1.resp.miss.value == 0 and + tlb.requestor_1.resp.paddr_0.value == ((signals["ppn"] << 12) | signals["offset"])) + + +def _do_test_receive_ptw_resp_nonstage_valid_ready_requestor_2(tlb): + # generate signals + signals = tlb.gene_rand_TLBsignal_batch() + # initialize dut with signals + tlb.init_dut_for_nostage_hit(signals["vpn"], signals["asid"], signals["ppn"], signals["ppn_low"]) + tlb.csr.satp.asid.value = signals["asid"] + # step to next cycle + tlb.dut.Step() + # switch requestor + tlb.requestor_0.req.valid.value = 0 + tlb.requestor_1.req.valid.value = 0 + tlb.requestor_2.req.valid.value = 1 + tlb.ctrl.io_requestor_2_resp_ready.value = 1 + tlb.requestor_2.req.bits_vaddr.value = (signals["vpn"] << 12) | signals["offset"] + # step to next cycle + tlb.dut.Step(2) + # assert result + assert (tlb.requestor_2.resp.paddr_0.value == ((signals["ppn"] << 12) | signals["offset"])) + assert (tlb.requestor_2.resp.miss.value == 0) + + +def _do_test_receive_ptw_resp_nonstage_invalid_ready_requestor_2(tlb): + # generate signals + signals = tlb.gene_rand_TLBsignal_batch() + # initialize dut with signals + tlb.init_dut_for_nostage_miss(signals["vpn"], signals["asid"], signals["ppn"], signals["ppn_low"]) + tlb.csr.satp.asid.value = signals["asid"] + # step to next cycle + tlb.dut.Step() + # switch requestor + tlb.requestor_0.req.valid.value = 0 + tlb.requestor_1.req.valid.value = 0 + tlb.requestor_2.req.valid.value = 0 + tlb.ctrl.io_requestor_2_resp_ready.value = 1 + tlb.requestor_2.req.bits_vaddr.value = (signals["vpn"] << 12) | signals["offset"] + # step to next cycle + tlb.dut.Step(2) + # assert result, no hit anyway + assert not (tlb.requestor_2.resp.miss.value == 0 and + tlb.requestor_2.resp.paddr_0.value == ((signals["ppn"] << 12) | signals["offset"])) + + +def _do_test_receive_ptw_resp_nonstage_valid_busy_requestor_2(tlb): + # generate signals + signals = tlb.gene_rand_TLBsignal_batch() + # initialize dut with signals + tlb.init_dut_for_nostage_miss(signals["vpn"], signals["asid"], signals["ppn"], signals["ppn_low"]) + tlb.csr.satp.asid.value = signals["asid"] + # step to next cycle + tlb.dut.Step() + # switch requestor + tlb.requestor_0.req.valid.value = 0 + tlb.requestor_1.req.valid.value = 0 + tlb.requestor_2.req.valid.value = 1 + tlb.ctrl.io_requestor_2_resp_ready.value = 0 + tlb.requestor_2.req.bits_vaddr.value = (signals["vpn"] << 12) | signals["offset"] + # step to next cycle + tlb.dut.Step(2) + # assert result, no hit anyway + assert not (tlb.requestor_2.resp.miss.value == 0 and + tlb.requestor_2.resp.paddr_0.value == ((signals["ppn"] << 12) | signals["offset"])) + + +def _do_test_receive_ptw_resp_nonstage_invalid_busy_requestor_2(tlb): + # generate signals + signals = tlb.gene_rand_TLBsignal_batch() + # initialize dut with signals + tlb.init_dut_for_nostage_miss(signals["vpn"], signals["asid"], signals["ppn"], signals["ppn_low"]) + tlb.csr.satp.asid.value = signals["asid"] + # step to next cycle + tlb.dut.Step() + # switch requestor + tlb.requestor_0.req.valid.value = 0 + tlb.requestor_1.req.valid.value = 0 + tlb.requestor_2.req.valid.value = 0 + tlb.ctrl.io_requestor_2_resp_ready.value = 0 + tlb.requestor_2.req.bits_vaddr.value = (signals["vpn"] << 12) | signals["offset"] + # step to next cycle + tlb.dut.Step(2) + # assert result, no hit anyway + assert not (tlb.requestor_2.resp.miss.value == 0 and + tlb.requestor_2.resp.paddr_0.value == ((signals["ppn"] << 12) | signals["offset"])) From 627059ba850e5def4a2e58faa7a705b01794d96e Mon Sep 17 00:00:00 2001 From: zhangrj Date: Fri, 1 Aug 2025 17:54:15 +0800 Subject: [PATCH 6/7] testcase refactored --- .../itlb/classical_version/base_components.py | 303 ++++++++++++++++++ .../test_tlb_receive_ptw_resp.py | 137 +------- 2 files changed, 314 insertions(+), 126 deletions(-) create mode 100644 ut_frontend/itlb/classical_version/base_components.py diff --git a/ut_frontend/itlb/classical_version/base_components.py b/ut_frontend/itlb/classical_version/base_components.py new file mode 100644 index 00000000..05f303de --- /dev/null +++ b/ut_frontend/itlb/classical_version/base_components.py @@ -0,0 +1,303 @@ +################################################################################ +# hit +################################################################################ + +def hit_nonStage_requestor_0(tlb): + # generate signals + signals = tlb.gene_rand_TLBsignal_batch() + # initialize dut with signals + tlb.init_dut_for_nostage_hit(signals["vpn"], signals["asid"], signals["ppn"], signals["ppn_low"]) + tlb.csr.satp.asid.value = signals["asid"] + # step to next cycle + tlb.dut.Step() + # switch requestor + tlb.requestor_0.req.valid.value = 1 + tlb.requestor_1.req.valid.value = 0 + tlb.requestor_2.req.valid.value = 0 + tlb.requestor_0.req.bits_vaddr.value = (signals["vpn"] << 12) | signals["offset"] + # step to next cycle + tlb.dut.Step(2) + # assert result + assert (tlb.requestor_0.resp.paddr_0.value == ((signals["ppn"] << 12) | signals["offset"])) + assert (tlb.requestor_0.resp.miss.value == 0) + + +def hit_nonStage_requestor_1(tlb): + # generate signals + signals = tlb.gene_rand_TLBsignal_batch() + # initialize dut with signals + tlb.init_dut_for_nostage_hit(signals["vpn"], signals["asid"], signals["ppn"], signals["ppn_low"]) + tlb.csr.satp.asid.value = signals["asid"] + # step to next cycle + tlb.dut.Step() + # switch requestor + tlb.requestor_0.req.valid.value = 0 + tlb.requestor_1.req.valid.value = 1 + tlb.requestor_2.req.valid.value = 0 + tlb.requestor_1.req.bits_vaddr.value = (signals["vpn"] << 12) | signals["offset"] + # step to next cycle + tlb.dut.Step(2) + # assert result + assert (tlb.requestor_1.resp.paddr_0.value == ((signals["ppn"] << 12) | signals["offset"])) + assert (tlb.requestor_1.resp.miss.value == 0) + + +def hit_nonStage_requestor_2(tlb): + # generate signals + signals = tlb.gene_rand_TLBsignal_batch() + # initialize dut with signals + tlb.init_dut_for_nostage_hit(signals["vpn"], signals["asid"], signals["ppn"], signals["ppn_low"]) + tlb.csr.satp.asid.value = signals["asid"] + # step to next cycle + tlb.dut.Step() + # switch requestor + tlb.requestor_0.req.valid.value = 0 + tlb.requestor_1.req.valid.value = 0 + tlb.requestor_2.req.valid.value = 1 + tlb.ctrl.io_requestor_2_resp_ready.value = 1 + tlb.requestor_2.req.bits_vaddr.value = (signals["vpn"] << 12) | signals["offset"] + # step to next cycle + tlb.dut.Step(2) + # assert result + assert (tlb.requestor_2.resp.paddr_0.value == ((signals["ppn"] << 12) | signals["offset"])) + assert (tlb.requestor_2.resp.miss.value == 0) + + +################################################################################ +# miss +################################################################################ + +# no stage +def miss_nonStage_requestor_0(tlb): + # generate signals + signals = tlb.gene_rand_TLBsignal_batch() + # initialize dut with signals + tlb.init_dut_for_nostage_miss(signals["vpn"], signals["asid"], signals["ppn"], signals["ppn_low"]) + tlb.csr.satp.asid.value = signals["asid"] + # step to next cycle + tlb.dut.Step() + # switch requestor + tlb.requestor_0.req.valid.value = 1 + tlb.requestor_1.req.valid.value = 0 + tlb.requestor_2.req.valid.value = 0 + tlb.requestor_0.req.bits_vaddr.value = (signals["vpn"] << 12) | signals["offset"] + # step to next cycle + tlb.dut.Step(2) + # assert result + assert (tlb.requestor_0.resp.miss.value == 1) + + +def miss_nonStage_requestor_1(tlb): + # generate signals + signals = tlb.gene_rand_TLBsignal_batch() + # initialize dut with signals + tlb.init_dut_for_nostage_miss(signals["vpn"], signals["asid"], signals["ppn"], signals["ppn_low"]) + tlb.csr.satp.asid.value = signals["asid"] + # step to next cycle + tlb.dut.Step() + # switch requestor + tlb.requestor_0.req.valid.value = 0 + tlb.requestor_1.req.valid.value = 1 + tlb.requestor_2.req.valid.value = 0 + tlb.requestor_1.req.bits_vaddr.value = (signals["vpn"] << 12) | signals["offset"] + # step to next cycle + tlb.dut.Step(2) + # assert result + assert (tlb.requestor_1.resp.miss.value == 1) + + +def miss_nonStage_requestor_2(tlb): + # generate signals + signals = tlb.gene_rand_TLBsignal_batch() + # initialize dut with signals + tlb.init_dut_for_nostage_miss(signals["vpn"], signals["asid"], signals["ppn"], signals["ppn_low"]) + tlb.csr.satp.asid.value = signals["asid"] + # step to next cycle + tlb.dut.Step() + # switch requestor + tlb.requestor_0.req.valid.value = 0 + tlb.requestor_1.req.valid.value = 0 + tlb.requestor_2.req.valid.value = 1 + tlb.ctrl.io_requestor_2_resp_ready.value = 1 + tlb.requestor_2.req.bits_vaddr.value = (signals["vpn"] << 12) | signals["offset"] + # step to next cycle + tlb.dut.Step(2) + # assert result + assert (tlb.requestor_2.resp.miss.value == 1) + + +# only stage 1 +def miss_onlyStage1_requestor_0(tlb): + # generate signals + signals = tlb.gene_rand_TLBsignal_batch() + # initialize dut with signals + tlb.init_dut_for_onlyStage1_miss(signals["vpn"], signals["asid"], signals["ppn"], signals["ppn_low"]) + tlb.csr.satp.asid.value = signals["asid"] + # step to next cycle + tlb.dut.Step() + # switch requestor + tlb.requestor_0.req.valid.value = 1 + tlb.requestor_1.req.valid.value = 0 + tlb.requestor_2.req.valid.value = 0 + tlb.requestor_0.req.bits_vaddr.value = (signals["vpn"] << 12) | signals["offset"] + # step to next cycle + tlb.dut.Step(2) + # assert result + assert (tlb.requestor_0.resp.miss.value == 1) + + +def miss_onlyStage1_requestor_1(tlb): + # generate signals + signals = tlb.gene_rand_TLBsignal_batch() + # initialize dut with signals + tlb.init_dut_for_onlyStage1_miss(signals["vpn"], signals["asid"], signals["ppn"], signals["ppn_low"]) + tlb.csr.satp.asid.value = signals["asid"] + # step to next cycle + tlb.dut.Step() + # switch requestor + tlb.requestor_0.req.valid.value = 0 + tlb.requestor_1.req.valid.value = 1 + tlb.requestor_2.req.valid.value = 0 + tlb.requestor_1.req.bits_vaddr.value = (signals["vpn"] << 12) | signals["offset"] + # step to next cycle + tlb.dut.Step(2) + # assert result + assert (tlb.requestor_1.resp.miss.value == 1) + + +def miss_onlyStage1_requestor_2(tlb): + # generate signals + signals = tlb.gene_rand_TLBsignal_batch() + # initialize dut with signals + tlb.init_dut_for_onlyStage1_miss(signals["vpn"], signals["asid"], signals["ppn"], signals["ppn_low"]) + tlb.csr.satp.asid.value = signals["asid"] + # step to next cycle + tlb.dut.Step() + # switch requestor + tlb.requestor_0.req.valid.value = 0 + tlb.requestor_1.req.valid.value = 0 + tlb.requestor_2.req.valid.value = 1 + tlb.ctrl.io_requestor_2_resp_ready.value = 1 + tlb.requestor_2.req.bits_vaddr.value = (signals["vpn"] << 12) | signals["offset"] + # step to next cycle + tlb.dut.Step(2) + # assert result + assert (tlb.requestor_2.resp.miss.value == 1) + + +# only stage 2 +def miss_onlyStage2_requestor_0(tlb): + # generate signals + signals = tlb.gene_rand_TLBsignal_batch() + # initialize dut with signals + tlb.init_dut_for_onlyStage2_miss(signals["vpn"], signals["asid"], signals["ppn"], signals["ppn_low"]) + tlb.csr.satp.asid.value = signals["asid"] + # step to next cycle + tlb.dut.Step() + # switch requestor + tlb.requestor_0.req.valid.value = 1 + tlb.requestor_1.req.valid.value = 0 + tlb.requestor_2.req.valid.value = 0 + tlb.requestor_0.req.bits_vaddr.value = (signals["vpn"] << 12) | signals["offset"] + # step to next cycle + tlb.dut.Step(2) + # assert result + assert (tlb.requestor_0.resp.miss.value == 1) + + +def miss_onlyStage2_requestor_1(tlb): + # generate signals + signals = tlb.gene_rand_TLBsignal_batch() + # initialize dut with signals + tlb.init_dut_for_onlyStage2_miss(signals["vpn"], signals["asid"], signals["ppn"], signals["ppn_low"]) + tlb.csr.satp.asid.value = signals["asid"] + # step to next cycle + tlb.dut.Step() + # switch requestor + tlb.requestor_0.req.valid.value = 0 + tlb.requestor_1.req.valid.value = 1 + tlb.requestor_2.req.valid.value = 0 + tlb.requestor_1.req.bits_vaddr.value = (signals["vpn"] << 12) | signals["offset"] + # step to next cycle + tlb.dut.Step(2) + # assert result + assert (tlb.requestor_1.resp.miss.value == 1) + + +def miss_onlyStage2_requestor_2(tlb): + # generate signals + signals = tlb.gene_rand_TLBsignal_batch() + # initialize dut with signals + tlb.init_dut_for_onlyStage2_miss(signals["vpn"], signals["asid"], signals["ppn"], signals["ppn_low"]) + tlb.csr.satp.asid.value = signals["asid"] + # step to next cycle + tlb.dut.Step() + # switch requestor + tlb.requestor_0.req.valid.value = 0 + tlb.requestor_1.req.valid.value = 0 + tlb.requestor_2.req.valid.value = 1 + tlb.ctrl.io_requestor_2_resp_ready.value = 1 + tlb.requestor_2.req.bits_vaddr.value = (signals["vpn"] << 12) | signals["offset"] + # step to next cycle + tlb.dut.Step(2) + # assert result + assert (tlb.requestor_2.resp.miss.value == 1) + + +# all stage +def miss_allStage_requestor_0(tlb): + # generate signals + signals = tlb.gene_rand_TLBsignal_batch() + # initialize dut with signals + tlb.init_dut_for_allStage_miss(signals["vpn"], signals["asid"], signals["ppn"], signals["ppn_low"]) + tlb.csr.satp.asid.value = signals["asid"] + # step to next cycle + tlb.dut.Step() + # switch requestor + tlb.requestor_0.req.valid.value = 1 + tlb.requestor_1.req.valid.value = 0 + tlb.requestor_2.req.valid.value = 0 + tlb.requestor_0.req.bits_vaddr.value = (signals["vpn"] << 12) | signals["offset"] + # step to next cycle + tlb.dut.Step(2) + # assert result + assert (tlb.requestor_0.resp.miss.value == 1) + + +def miss_allStage_requestor_1(tlb): + # generate signals + signals = tlb.gene_rand_TLBsignal_batch() + # initialize dut with signals + tlb.init_dut_for_allStage_miss(signals["vpn"], signals["asid"], signals["ppn"], signals["ppn_low"]) + tlb.csr.satp.asid.value = signals["asid"] + # step to next cycle + tlb.dut.Step() + # switch requestor + tlb.requestor_0.req.valid.value = 0 + tlb.requestor_1.req.valid.value = 1 + tlb.requestor_2.req.valid.value = 0 + tlb.requestor_1.req.bits_vaddr.value = (signals["vpn"] << 12) | signals["offset"] + # step to next cycle + tlb.dut.Step(2) + # assert result + assert (tlb.requestor_1.resp.miss.value == 1) + + +def miss_allStage_requestor_2(tlb): + # generate signals + signals = tlb.gene_rand_TLBsignal_batch() + # initialize dut with signals + tlb.init_dut_for_allStage_miss(signals["vpn"], signals["asid"], signals["ppn"], signals["ppn_low"]) + tlb.csr.satp.asid.value = signals["asid"] + # step to next cycle + tlb.dut.Step() + # switch requestor + tlb.requestor_0.req.valid.value = 0 + tlb.requestor_1.req.valid.value = 0 + tlb.requestor_2.req.valid.value = 1 + tlb.ctrl.io_requestor_2_resp_ready.value = 1 + tlb.requestor_2.req.bits_vaddr.value = (signals["vpn"] << 12) | signals["offset"] + # step to next cycle + tlb.dut.Step(2) + # assert result + assert (tlb.requestor_2.resp.miss.value == 1) diff --git a/ut_frontend/itlb/classical_version/test_tlb_receive_ptw_resp.py b/ut_frontend/itlb/classical_version/test_tlb_receive_ptw_resp.py index 96b3389f..e083fe68 100644 --- a/ut_frontend/itlb/classical_version/test_tlb_receive_ptw_resp.py +++ b/ut_frontend/itlb/classical_version/test_tlb_receive_ptw_resp.py @@ -13,7 +13,11 @@ #**************************************************************************************/ from .env import * -import inspect + +from ut_frontend.itlb.classical_version.base_components import hit_nonStage_requestor_0, \ + hit_nonStage_requestor_1, hit_nonStage_requestor_2, \ + miss_nonStage_requestor_0, miss_nonStage_requestor_1, \ + miss_nonStage_requestor_2 ROUND_NUM = 1000 ROUND_SIZE = 30 @@ -85,12 +89,12 @@ def test_receive_ptw_resp_nonstage_single_hit_icache(tlb_fixture): for _ in range(ROUND_NUM): for _ in range(ROUND_SIZE): - _do_test_receive_ptw_resp_nonstage_hit_requestor_0(tlb) + hit_nonStage_requestor_0(tlb) tlb.cleanup_requestor(0) for _ in range(ROUND_NUM): for _ in range(ROUND_SIZE): - _do_test_receive_ptw_resp_nonstage_hit_requestor_1(tlb) + hit_nonStage_requestor_1(tlb) tlb.cleanup_requestor(1) @@ -109,71 +113,10 @@ def test_receive_ptw_resp_nonstage_single_hit_ifu(tlb_fixture): for _ in range(ROUND_NUM): for _ in range(ROUND_SIZE): - _do_test_receive_ptw_resp_nonstage_hit_requestor_2(tlb) + hit_nonStage_requestor_2(tlb) tlb.cleanup_requestor(2) -def _do_test_receive_ptw_resp_nonstage_hit_requestor_0(tlb): - # generate signals - signals = tlb.gene_rand_TLBsignal_batch() - # initialize dut with signals - tlb.init_dut_for_nostage_hit(signals["vpn"], signals["asid"], signals["ppn"], signals["ppn_low"]) - tlb.csr.satp.asid.value = signals["asid"] - # step to next cycle - tlb.dut.Step() - # switch requestor - tlb.requestor_0.req.valid.value = 1 - tlb.requestor_1.req.valid.value = 0 - tlb.requestor_2.req.valid.value = 0 - tlb.requestor_0.req.bits_vaddr.value = (signals["vpn"] << 12) | signals["offset"] - # step to next cycle - tlb.dut.Step(2) - # assert result - assert (tlb.requestor_0.resp.paddr_0.value == ((signals["ppn"] << 12) | signals["offset"])) - assert (tlb.requestor_0.resp.miss.value == 0) - - -def _do_test_receive_ptw_resp_nonstage_hit_requestor_1(tlb): - # generate signals - signals = tlb.gene_rand_TLBsignal_batch() - # initialize dut with signals - tlb.init_dut_for_nostage_hit(signals["vpn"], signals["asid"], signals["ppn"], signals["ppn_low"]) - tlb.csr.satp.asid.value = signals["asid"] - # step to next cycle - tlb.dut.Step() - # switch requestor - tlb.requestor_0.req.valid.value = 0 - tlb.requestor_1.req.valid.value = 1 - tlb.requestor_2.req.valid.value = 0 - tlb.requestor_1.req.bits_vaddr.value = (signals["vpn"] << 12) | signals["offset"] - # step to next cycle - tlb.dut.Step(2) - # assert result - assert (tlb.requestor_1.resp.paddr_0.value == ((signals["ppn"] << 12) | signals["offset"])) - assert (tlb.requestor_1.resp.miss.value == 0) - - -def _do_test_receive_ptw_resp_nonstage_hit_requestor_2(tlb): - # generate signals - signals = tlb.gene_rand_TLBsignal_batch() - # initialize dut with signals - tlb.init_dut_for_nostage_hit(signals["vpn"], signals["asid"], signals["ppn"], signals["ppn_low"]) - tlb.csr.satp.asid.value = signals["asid"] - # step to next cycle - tlb.dut.Step() - # switch requestor - tlb.requestor_0.req.valid.value = 0 - tlb.requestor_1.req.valid.value = 0 - tlb.requestor_2.req.valid.value = 1 - tlb.ctrl.io_requestor_2_resp_ready.value = 1 - tlb.requestor_2.req.bits_vaddr.value = (signals["vpn"] << 12) | signals["offset"] - # step to next cycle - tlb.dut.Step(2) - # assert result - assert (tlb.requestor_2.resp.paddr_0.value == ((signals["ppn"] << 12) | signals["offset"])) - assert (tlb.requestor_2.resp.miss.value == 0) - - def test_receive_ptw_resp_nonstage_single_miss_icache(tlb_fixture): """ no stage，单次miss @@ -189,12 +132,12 @@ def test_receive_ptw_resp_nonstage_single_miss_icache(tlb_fixture): for _ in range(ROUND_NUM): for _ in range(ROUND_SIZE): - _do_test_receive_ptw_resp_nonstage_miss_requestor_0(tlb) + miss_nonStage_requestor_0(tlb) tlb.cleanup_requestor(0) for _ in range(ROUND_NUM): for _ in range(ROUND_SIZE): - _do_test_receive_ptw_resp_nonstage_miss_requestor_1(tlb) + miss_nonStage_requestor_1(tlb) tlb.cleanup_requestor(1) @@ -213,68 +156,10 @@ def test_receive_ptw_resp_nonstage_single_miss_ifu(tlb_fixture): for _ in range(ROUND_NUM): for _ in range(ROUND_SIZE): - _do_test_receive_ptw_resp_nonstage_miss_requestor_2(tlb) + miss_nonStage_requestor_2(tlb) tlb.cleanup_requestor(2) # cleanup requestor 2 after each missing -def _do_test_receive_ptw_resp_nonstage_miss_requestor_0(tlb): - # generate signals - signals = tlb.gene_rand_TLBsignal_batch() - # initialize dut with signals - tlb.init_dut_for_nostage_miss(signals["vpn"], signals["asid"], signals["ppn"], signals["ppn_low"]) - tlb.csr.satp.asid.value = signals["asid"] - # step to next cycle - tlb.dut.Step() - # switch requestor - tlb.requestor_0.req.valid.value = 1 - tlb.requestor_1.req.valid.value = 0 - tlb.requestor_2.req.valid.value = 0 - tlb.requestor_0.req.bits_vaddr.value = (signals["vpn"] << 12) | signals["offset"] - # step to next cycle - tlb.dut.Step(2) - # assert result - assert (tlb.requestor_0.resp.miss.value == 1) - - -def _do_test_receive_ptw_resp_nonstage_miss_requestor_1(tlb): - # generate signals - signals = tlb.gene_rand_TLBsignal_batch() - # initialize dut with signals - tlb.init_dut_for_nostage_miss(signals["vpn"], signals["asid"], signals["ppn"], signals["ppn_low"]) - tlb.csr.satp.asid.value = signals["asid"] - # step to next cycle - tlb.dut.Step() - # switch requestor - tlb.requestor_0.req.valid.value = 0 - tlb.requestor_1.req.valid.value = 1 - tlb.requestor_2.req.valid.value = 0 - tlb.requestor_1.req.bits_vaddr.value = (signals["vpn"] << 12) | signals["offset"] - # step to next cycle - tlb.dut.Step(2) - # assert result - assert (tlb.requestor_1.resp.miss.value == 1) - - -def _do_test_receive_ptw_resp_nonstage_miss_requestor_2(tlb): - # generate signals - signals = tlb.gene_rand_TLBsignal_batch() - # initialize dut with signals - tlb.init_dut_for_nostage_miss(signals["vpn"], signals["asid"], signals["ppn"], signals["ppn_low"]) - tlb.csr.satp.asid.value = signals["asid"] - # step to next cycle - tlb.dut.Step() - # switch requestor - tlb.requestor_0.req.valid.value = 0 - tlb.requestor_1.req.valid.value = 0 - tlb.requestor_2.req.valid.value = 1 - tlb.ctrl.io_requestor_2_resp_ready.value = 1 - tlb.requestor_2.req.bits_vaddr.value = (signals["vpn"] << 12) | signals["offset"] - # step to next cycle - tlb.dut.Step(2) - # assert result - assert (tlb.requestor_2.resp.miss.value == 1) - - def test_receive_ptw_resp_nonstage_valid_icache(tlb_fixture): """ no stage，valid有效性 From 85150c394d33107d42bf742bb6c66b7179849e26 Mon Sep 17 00:00:00 2001 From: zhangrj Date: Tue, 12 Aug 2025 05:20:16 +0800 Subject: [PATCH 7/7] signals returning added in base components --- .../itlb/classical_version/base_components.py | 60 ++++++++++++++----- 1 file changed, 45 insertions(+), 15 deletions(-) diff --git a/ut_frontend/itlb/classical_version/base_components.py b/ut_frontend/itlb/classical_version/base_components.py index 05f303de..545819b6 100644 --- a/ut_frontend/itlb/classical_version/base_components.py +++ b/ut_frontend/itlb/classical_version/base_components.py @@ -2,7 +2,7 @@ # hit ################################################################################ -def hit_nonStage_requestor_0(tlb): +def hit_nonStage_requestor_0(tlb) -> dict: # generate signals signals = tlb.gene_rand_TLBsignal_batch() # initialize dut with signals @@ -20,9 +20,11 @@ def hit_nonStage_requestor_0(tlb): # assert result assert (tlb.requestor_0.resp.paddr_0.value == ((signals["ppn"] << 12) | signals["offset"])) assert (tlb.requestor_0.resp.miss.value == 0) + # return signals + return signals -def hit_nonStage_requestor_1(tlb): +def hit_nonStage_requestor_1(tlb) -> dict: # generate signals signals = tlb.gene_rand_TLBsignal_batch() # initialize dut with signals @@ -40,9 +42,11 @@ def hit_nonStage_requestor_1(tlb): # assert result assert (tlb.requestor_1.resp.paddr_0.value == ((signals["ppn"] << 12) | signals["offset"])) assert (tlb.requestor_1.resp.miss.value == 0) + # return signals + return signals -def hit_nonStage_requestor_2(tlb): +def hit_nonStage_requestor_2(tlb) -> dict: # generate signals signals = tlb.gene_rand_TLBsignal_batch() # initialize dut with signals @@ -61,6 +65,8 @@ def hit_nonStage_requestor_2(tlb): # assert result assert (tlb.requestor_2.resp.paddr_0.value == ((signals["ppn"] << 12) | signals["offset"])) assert (tlb.requestor_2.resp.miss.value == 0) + # return signals + return signals ################################################################################ @@ -68,7 +74,7 @@ def hit_nonStage_requestor_2(tlb): ################################################################################ # no stage -def miss_nonStage_requestor_0(tlb): +def miss_nonStage_requestor_0(tlb) -> dict: # generate signals signals = tlb.gene_rand_TLBsignal_batch() # initialize dut with signals @@ -85,9 +91,11 @@ def miss_nonStage_requestor_0(tlb): tlb.dut.Step(2) # assert result assert (tlb.requestor_0.resp.miss.value == 1) + # return signals + return signals -def miss_nonStage_requestor_1(tlb): +def miss_nonStage_requestor_1(tlb) -> dict: # generate signals signals = tlb.gene_rand_TLBsignal_batch() # initialize dut with signals @@ -104,9 +112,11 @@ def miss_nonStage_requestor_1(tlb): tlb.dut.Step(2) # assert result assert (tlb.requestor_1.resp.miss.value == 1) + # return signals + return signals -def miss_nonStage_requestor_2(tlb): +def miss_nonStage_requestor_2(tlb) -> dict: # generate signals signals = tlb.gene_rand_TLBsignal_batch() # initialize dut with signals @@ -124,10 +134,12 @@ def miss_nonStage_requestor_2(tlb): tlb.dut.Step(2) # assert result assert (tlb.requestor_2.resp.miss.value == 1) + # return signals + return signals # only stage 1 -def miss_onlyStage1_requestor_0(tlb): +def miss_onlyStage1_requestor_0(tlb) -> dict: # generate signals signals = tlb.gene_rand_TLBsignal_batch() # initialize dut with signals @@ -144,9 +156,11 @@ def miss_onlyStage1_requestor_0(tlb): tlb.dut.Step(2) # assert result assert (tlb.requestor_0.resp.miss.value == 1) + # return signals + return signals -def miss_onlyStage1_requestor_1(tlb): +def miss_onlyStage1_requestor_1(tlb) -> dict: # generate signals signals = tlb.gene_rand_TLBsignal_batch() # initialize dut with signals @@ -163,9 +177,11 @@ def miss_onlyStage1_requestor_1(tlb): tlb.dut.Step(2) # assert result assert (tlb.requestor_1.resp.miss.value == 1) + # return signals + return signals -def miss_onlyStage1_requestor_2(tlb): +def miss_onlyStage1_requestor_2(tlb) -> dict: # generate signals signals = tlb.gene_rand_TLBsignal_batch() # initialize dut with signals @@ -183,10 +199,12 @@ def miss_onlyStage1_requestor_2(tlb): tlb.dut.Step(2) # assert result assert (tlb.requestor_2.resp.miss.value == 1) + # return signals + return signals # only stage 2 -def miss_onlyStage2_requestor_0(tlb): +def miss_onlyStage2_requestor_0(tlb) -> dict: # generate signals signals = tlb.gene_rand_TLBsignal_batch() # initialize dut with signals @@ -203,9 +221,11 @@ def miss_onlyStage2_requestor_0(tlb): tlb.dut.Step(2) # assert result assert (tlb.requestor_0.resp.miss.value == 1) + # return signals + return signals -def miss_onlyStage2_requestor_1(tlb): +def miss_onlyStage2_requestor_1(tlb) -> dict: # generate signals signals = tlb.gene_rand_TLBsignal_batch() # initialize dut with signals @@ -222,9 +242,11 @@ def miss_onlyStage2_requestor_1(tlb): tlb.dut.Step(2) # assert result assert (tlb.requestor_1.resp.miss.value == 1) + # return signals + return signals -def miss_onlyStage2_requestor_2(tlb): +def miss_onlyStage2_requestor_2(tlb) -> dict: # generate signals signals = tlb.gene_rand_TLBsignal_batch() # initialize dut with signals @@ -242,10 +264,12 @@ def miss_onlyStage2_requestor_2(tlb): tlb.dut.Step(2) # assert result assert (tlb.requestor_2.resp.miss.value == 1) + # return signals + return signals # all stage -def miss_allStage_requestor_0(tlb): +def miss_allStage_requestor_0(tlb) -> dict: # generate signals signals = tlb.gene_rand_TLBsignal_batch() # initialize dut with signals @@ -262,9 +286,11 @@ def miss_allStage_requestor_0(tlb): tlb.dut.Step(2) # assert result assert (tlb.requestor_0.resp.miss.value == 1) + # return signals + return signals -def miss_allStage_requestor_1(tlb): +def miss_allStage_requestor_1(tlb) -> dict: # generate signals signals = tlb.gene_rand_TLBsignal_batch() # initialize dut with signals @@ -281,9 +307,11 @@ def miss_allStage_requestor_1(tlb): tlb.dut.Step(2) # assert result assert (tlb.requestor_1.resp.miss.value == 1) + # return signals + return signals -def miss_allStage_requestor_2(tlb): +def miss_allStage_requestor_2(tlb) -> dict: # generate signals signals = tlb.gene_rand_TLBsignal_batch() # initialize dut with signals @@ -301,3 +329,5 @@ def miss_allStage_requestor_2(tlb): tlb.dut.Step(2) # assert result assert (tlb.requestor_2.resp.miss.value == 1) + # return signals + return signals