From 1b315bf62ccc2f09faa22a3cf083b938669c85bf Mon Sep 17 00:00:00 2001 From: jhua-xilinx Date: Tue, 12 May 2026 15:53:43 +0800 Subject: [PATCH] Delete ced/Xilinx/IPI/Versal Multi-Rate GTY directory Archiving the multi-rate GTY CED. IBERT CED supercedes this CED. --- .../IPI/Versal Multi-Rate GTY/README.md | 189 ----------- .../IPI/Versal Multi-Rate GTY/design.xml | 22 -- ced/Xilinx/IPI/Versal Multi-Rate GTY/init.tcl | 28 -- .../IPI/Versal Multi-Rate GTY/license.txt | 15 - .../Versal Multi-Rate GTY/multirate_gty.png | Bin 20825 -> 0 bytes ced/Xilinx/IPI/Versal Multi-Rate GTY/run.tcl | 315 ------------------ .../IPI/Versal Multi-Rate GTY/xitem.json | 33 -- 7 files changed, 602 deletions(-) delete mode 100644 ced/Xilinx/IPI/Versal Multi-Rate GTY/README.md delete mode 100644 ced/Xilinx/IPI/Versal Multi-Rate GTY/design.xml delete mode 100644 ced/Xilinx/IPI/Versal Multi-Rate GTY/init.tcl delete mode 100644 ced/Xilinx/IPI/Versal Multi-Rate GTY/license.txt delete mode 100644 ced/Xilinx/IPI/Versal Multi-Rate GTY/multirate_gty.png delete mode 100644 ced/Xilinx/IPI/Versal Multi-Rate GTY/run.tcl delete mode 100644 ced/Xilinx/IPI/Versal Multi-Rate GTY/xitem.json diff --git a/ced/Xilinx/IPI/Versal Multi-Rate GTY/README.md b/ced/Xilinx/IPI/Versal Multi-Rate GTY/README.md deleted file mode 100644 index e4a035f..0000000 --- a/ced/Xilinx/IPI/Versal Multi-Rate GTY/README.md +++ /dev/null @@ -1,189 +0,0 @@ - -# VCK190/VMK180 Example Design : Multi-Rate GTY -## Objective -This example describes a Versal GTY multi-rate design using the following configuration: -* Two rates: 10G and 25G switchable line rates -* Single GTY lane connected through SFP on VCK190/VMK180 evaluation board - -## Required Hardware and Tools -2021.2 Vivado -VCK190/VMK180 -Boot Mode: JTAG -## Block Diagram -![image](https://user-images.githubusercontent.com/73725387/130385300-5c8fe56e-b1cf-4689-8d79-fb331f3e9125.png) - -On the board, the design targets the following configuration: -* Single lane on Bank 105 GTY2, which connects to SFP0 (lower connector of the 2x SFP28 stack). -* Bank 105 REFCLK0, which is sourced from zSFP Si570 CLK. Default frequency is 156.25MHz. -* Bank 705 Si570 LPDDR4_CLK2 for APB3CLK. Default frequency is 200MHz. - -## Design Steps -1. Download the example design from XHub Stores. Open example design and select the targeted Board (VCK190 or VMK180) -2. Confirm in the top level **multirate_gty.xdc** that `create_clock` frequencies and LOC constraints match your design. If you have changed REFCLK frequency or the pin locations, modify accordingly. -3. Run through synthesis, implementation and generate PDI. Make sure timing is clean. - -## Hardware Setup - -#### Board Connections -* Connect power cable -* Connect USB-C/JTAG cable -* Insert SFP28 loopback module into the lower 2x SFP28 connector (SFP0) -![image](https://user-images.githubusercontent.com/73725387/100336967-a7605500-2f8b-11eb-8d83-a07fa2970935.png) - -## Running the Design on VCK190/VMK180 -#### 1. Initialization -Power up and program the pdi. Add all VIO probes to the dashboard. Hardware manager should look like the below post pdi programming. -* The default line rate is 10G (rate_sel = probe_out1[3:0] = 0x0) -* Link is up: link_status_out = 1 -* TX/RX reset has completed: tx/rx_resetdone_out = 1 -* LCPLL is locked: hsclk1_lcplllock = 1 - -![image](https://user-images.githubusercontent.com/73725387/100337338-19d13500-2f8c-11eb-99e9-1189303dd187.png) - -#### 2. Rate change to 25G -* Change rate_sel = probe_out1[3:0] = 0x1. This will change the line rate to 25G (CONFIG1) -* Reset sequence is automatically applied. tx/rx_resetdone toggles and return back to 1 when rate change operation has completed - -![image](https://user-images.githubusercontent.com/73725387/100337445-3bcab780-2f8c-11eb-9a27-9301f9719720.png) - -#### 3. In-system IBERT Eye Scan -Versal ACAP has runtime IBERT capability built-in to all GTY designs. Let's run eye scans for 10G and 25G links. - -* In **Serial I/O Links** Tab, choose **Create Links**. -* Create link for CH2.TX → CH2.RX. The design is only running single lane on GTY2. -* The created link and its link status is shown below. **Note**: Status is expected to show "No link" for an in-system IBERT setup. The data pattern is sourced from the custom design and not from IBERT. IBERT pattern checker receives unexpected data therefore IBERT link status is unknown. -* Right-click on **Link 0** and select **Create Scan**. -* Toggle between rate_sel = 0x0 and 0x1 to change line rates between 10G/25G. Run scan after each rate change to obtain 10G and 25G eye scans. - -![image](https://user-images.githubusercontent.com/73725387/100337683-906e3280-2f8c-11eb-8fb0-d1db3f29e05a.png) - -![image](https://user-images.githubusercontent.com/73725387/100337708-98c66d80-2f8c-11eb-95f1-e1334de38752.png) - -![image](https://user-images.githubusercontent.com/73725387/100337743-a2e86c00-2f8c-11eb-9186-1987bef74457.png) - -![image](https://user-images.githubusercontent.com/73725387/100337790-ae3b9780-2f8c-11eb-8b18-bc0607c70f1d.png) - -10G Eye Scan -![image](https://user-images.githubusercontent.com/73725387/100337832-b7c4ff80-2f8c-11eb-9797-990d1b16d3c1.png) - -25G Eye Scan -![image](https://user-images.githubusercontent.com/73725387/100337857-bd224a00-2f8c-11eb-8179-a72459dad018.png) - - -#### 4. IBERT Debug Capability -The custom GTY design can also be converted to an IBERT design during runtime. -* In **hw_vio_1**, set rate_sel = probe_out1 = 0x0. This sets the GTY to default rate of 10G (CONFIG0). -* In **Serial I/O Links** tab, change TX/RX Pattern to PRBS 31. This switches the data source to IBERT pattern generator/checker. -* Status now shows the 10G line rate, with 0 bit errors. - -![image](https://user-images.githubusercontent.com/73725387/100338048-f8bd1400-2f8c-11eb-9822-1b57992f556d.png) - -![image](https://user-images.githubusercontent.com/73725387/100338081-007cb880-2f8d-11eb-85e8-fa388ddde8af.png) -**Note**: In the VIO, the bridge_ip/link_status_out is expected to go down since the pattern checker is now through IBERT and not through the generator/checker inside gt_bridge_ip. - -10G Eye Scan -![image](https://user-images.githubusercontent.com/73725387/100338109-083c5d00-2f8d-11eb-8fef-c33ab6ff05b2.png) - -* Change rate_sel = probe_out1 = 0x1. This changes the rate to 25G (CONFIG1). -* Change TX/RX Pattern to something else then back to PRBS 31. This allows IBERT to re-sync to the new line rate. -* Apply RX Reset to reset error counter. -* Status now shows the 25G line rate, with 0 bit errors. - -![image](https://user-images.githubusercontent.com/73725387/100338291-40dc3680-2f8d-11eb-8322-ca7adc046d8c.png) -![image](https://user-images.githubusercontent.com/73725387/100338309-48034480-2f8d-11eb-9d03-281e32da11d2.png) -**Note**: In the VIO, the bridge_ip/link_status_out is expected to go down since the pattern checker is now through IBERT and not through the generator/checker inside gt_bridge_ip. - -25G Eye Scan -![image](https://user-images.githubusercontent.com/73725387/100338324-4cc7f880-2f8d-11eb-861c-30da07f718a7.png) - -The following **Appendix: Vivado Steps** in this README will walk through the steps to create this design in Vivado manually. - -## Appendix: Vivado Steps -#### 1. Create project targeting VMK180 Board - -![image](https://user-images.githubusercontent.com/73725387/119452016-b9c50c80-bcea-11eb-9ea5-9c5faaef94b6.png) -#### 2. Create Block Design - -![image](https://user-images.githubusercontent.com/73725387/100334096-30758d00-2f88-11eb-87d5-41aaadc03f22.png) - -#### 3. Create gt_bridge_ip -Add gt_bridge_ip to IPI. Configure the bridge_ip and transceiver through customization GUI. In this example, we will run one GT lane targeting two line rates, 10G and 25G. - -* Set **Number of lanes** = 1. **TX/RX master clk source** = TX0/RX0 -* Open the transceiver sub-GUI through **Transceiver Configs** button -![image](https://user-images.githubusercontent.com/73725387/100334207-53a03c80-2f88-11eb-92a1-565561706541.png) -* For **CONFIG0**, set **Line rate** = 10.3125, **PLL type** = LCPLL, **Requested reference clock** = 156.25. Check that the **Actual reference clock** is also 156.25. -* Click on the "+" button to add a new configuration **CONFIG1**. -* For **CONFIG1**, set **Line rate** = 25.78125, **PLL type** = LCPLL, **Requested reference clock** = 156.25. Check that the **Actual reference clock** is also 156.25. -![image](https://user-images.githubusercontent.com/73725387/100334551-cad5d080-2f88-11eb-848d-220eebab68b1.png) -![image](https://user-images.githubusercontent.com/73725387/100334584-d45f3880-2f88-11eb-85a1-62f2f101d939.png) -* Add a gt_quad_base IP to IPI. **Note**: This step is only required because we are running a customized connection for block automation to target Channel 2. If the design uses Channel 0, block automation can be run with gt_bridge_ip alone. -* Click on **Run Block Automation**. This will automatically instantiate the auxiliary blocks needed to connect GT clocks. - * Choose **Customized_Connection** and select gt_quad_base_0 **Lane_2**. - -![image](https://user-images.githubusercontent.com/73725387/100334904-34ee7580-2f89-11eb-843a-eea09834371c.png) -![image](https://user-images.githubusercontent.com/73725387/100334954-433c9180-2f89-11eb-9142-41f7739daf0a.png) -![image](https://user-images.githubusercontent.com/73725387/100334969-4a639f80-2f89-11eb-94fe-8cd96750cdaa.png) -![image](https://user-images.githubusercontent.com/73725387/100335029-59e2e880-2f89-11eb-9d12-6f002a5cfdd2.png) - -#### 4. Add VIO for hardware debug visibility -1. Keep MGTREFCLK and GT_Serial ports. Remove all other external ports which were automatically created by block automation. GTY controls and status monitoring will be done through VIO instead. -2. Instantiate VIO in block design -3. Customize for 4 inputs and 2 outputs, and connect as follows: - * probe_in0 = gt_bridge_ip/link_status_out - * probe_in1 = gt_bridge_ip/tx_resetdone_out - * probe_in2 = gt_bridge_ip/rx_resetdone_out - * probe_in3 = gt_quad_base/hsclk1_lcplllock - * probe_out0 = gt_bridge_ip/gtreset_in - * probe_out1 = gt_bridge_ip/rate_sel (4-bits) - -![image](https://user-images.githubusercontent.com/73725387/100335596-0329de80-2f8a-11eb-9e16-1255f80dac0d.png) -![image](https://user-images.githubusercontent.com/73725387/100335633-0fae3700-2f8a-11eb-9545-24d0eef1a785.png) -![image](https://user-images.githubusercontent.com/73725387/100335654-15a41800-2f8a-11eb-8fed-868f84fe6d63.png) -![image](https://user-images.githubusercontent.com/73725387/100335667-1b99f900-2f8a-11eb-8797-d4e497b1dfa4.png) -![image](https://user-images.githubusercontent.com/73725387/100335698-218fda00-2f8a-11eb-8c97-ef760f7085ac.png) - -#### 5. Add CIPS IP -The PMC is incorporated into the CIPS IP and must be configured for the Versal device to boot properly. Therefore, all Versal designs must include CIPS IP. -- In the **Board** tab, drag-and-drop the **PS-PMC Fixed IO** instance onto the block design canvas. -- **Run Block Automation** to apply board presets. -![image](https://user-images.githubusercontent.com/73725387/130386107-95360c14-2508-4f43-bcb7-cf1924cfa1b9.png) -![image](https://user-images.githubusercontent.com/73725387/121114525-af197580-c7c8-11eb-847f-2a6ed5bdc6e7.png) -![image](https://user-images.githubusercontent.com/73725387/121114406-7aa5b980-c7c8-11eb-8b15-7016cc29edaf.png) - -#### 6. Add APB3CLK connections -We will drive the APB3CLK and VIO clock using a PL output clock from the CIPS IP. -1. Open the CIPS IP and navigate to **Next** > **PS PMC** > **Clocking** > **Output Clocks**. -2. Set **PL CLK 0** to 100 MHz. -3. Connect versal_cips_0/**pl0_ref_clk** to gt_bridge_ip_0/**apb3clk**, gt_quad_base_0/**apb3clk**, and axis_vio_0/**clk**. -![image](https://user-images.githubusercontent.com/73725387/130386307-c9a98d53-c66d-4433-91d0-00b980b59d68.png) -![image](https://user-images.githubusercontent.com/73725387/130386319-ef72c9a2-6e15-4c87-80fe-3c6206da3699.png) - -#### 7. Create HDL wrapper -In the **Sources** window, right-click on the block design (design_1.bd) and select **Create HDL Wrapper**. Let Vivado manage. -![image](https://user-images.githubusercontent.com/73725387/100336397-fc4f9b80-2f8a-11eb-8241-6c0b46c27f70.png) - -#### 8. Add REFCLK and VIO set_false_path constraints -* Create a xdc file -File > Add Sources > Add or create constraints > Create file -![image](https://user-images.githubusercontent.com/73725387/119454889-e9294880-bced-11eb-8e2e-c6565687febd.png) -* Add MGTREFCLK create_clock constraint to top level xdc: - ```tcl - create_clock -period 6.400 -name {gt_bridge_ip_0_diff_gt_ref_clock_clk_p[0]} [get_ports {gt_bridge_ip_0_diff_gt_ref_clock_clk_p[0]}] - ``` -* Add false_path constraints for the VIO input/output pins. The VIO is in apb3clk domain and the probed pins are in GT/RXUSRCLK domain. There are clock domain crossings from and to the VIO and these paths can be safely ignored. - - ```tcl - set_false_path -through [get_pins -hier *axis_vio*probe*out*] - set_false_path -through [get_pins -hier *axis_vio*probe*in*] - ``` - -#### 8. Synthesis and IO planning -* Run synthesis, and open synthesized design -* The GT/REFCLK locations are defined during pin planning. After synthesis, set the pin locations as follows in the **I/O Ports** tab. **Note**: It is important to lock GT and REFCLK locations before implementation for optimized placement and routing. -* Click **Save**. - -![image](https://user-images.githubusercontent.com/73725387/100336581-36b93880-2f8b-11eb-8669-1f4662038feb.png) - -#### 9. Implementation and PDI generation -Run implementation and generate PDI. Make sure timing is clean. diff --git a/ced/Xilinx/IPI/Versal Multi-Rate GTY/design.xml b/ced/Xilinx/IPI/Versal Multi-Rate GTY/design.xml deleted file mode 100644 index 51ca1a1..0000000 --- a/ced/Xilinx/IPI/Versal Multi-Rate GTY/design.xml +++ /dev/null @@ -1,22 +0,0 @@ - - - - - xilinx.com - - design - - multirate_gty - - Multi-Rate GTY - - This design demonstrates the usage of the Versal GTY on Xilinx VCK190 and VMK180 boards. The design implements multi-rate GTY at 10G and 25G switchable line rates and communicates through SFP connector. Reset, rate switching, and status ports are connected to VIO core to control and monitor GTY on hardware. - - 1.0 - - init.tcl - - multirate_gty.png - - - diff --git a/ced/Xilinx/IPI/Versal Multi-Rate GTY/init.tcl b/ced/Xilinx/IPI/Versal Multi-Rate GTY/init.tcl deleted file mode 100644 index b6abd5f..0000000 --- a/ced/Xilinx/IPI/Versal Multi-Rate GTY/init.tcl +++ /dev/null @@ -1,28 +0,0 @@ -# ######################################################################## -# Copyright (C) 2019, Xilinx Inc - All rights reserved - -# Licensed under the Apache License, Version 2.0 (the "License"). You may -# not use this file except in compliance with the License. A copy of the -# License is located at - - # http://www.apache.org/licenses/LICENSE-2.0 - -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# ######################################################################## - -set currentFile [file normalize [info script]] -variable currentDir [file dirname $currentFile] - -source -notrace "$currentDir/run.tcl" - -proc getSupportedParts {} { - return "" -} - -proc getSupportedBoards {} { - return [get_board_parts -filter {(BOARD_NAME =~"*vck190*" && VENDOR_NAME=="xilinx.com" ) || (BOARD_NAME =~"*vmk180*" && VENDOR_NAME=="xilinx.com" )} -latest_file_version] -} diff --git a/ced/Xilinx/IPI/Versal Multi-Rate GTY/license.txt b/ced/Xilinx/IPI/Versal Multi-Rate GTY/license.txt deleted file mode 100644 index f74982d..0000000 --- a/ced/Xilinx/IPI/Versal Multi-Rate GTY/license.txt +++ /dev/null @@ -1,15 +0,0 @@ -######################################################################### -Copyright (C) 2019, Xilinx Inc - All rights reserved - -Licensed under the Apache License, Version 2.0 (the "License"). You may -not use this file except in compliance with the License. A copy of the -License is located at - -http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 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You may -# not use this file except in compliance with the License. A copy of the -# License is located at - - # http://www.apache.org/licenses/LICENSE-2.0 - -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# ######################################################################## - -proc createDesign {design_name options} { - -################################################################## -# DESIGN PROCs -################################################################## - - - -# Procedure to create entire design; Provide argument to make -# procedure reusable. If parentCell is "", will use root. -proc create_root_design { parentCell design_name temp_options} { - -# puts "create_root_design" - -set board_part [get_property NAME [current_board_part]] -set board_name [get_property BOARD_NAME [current_board]] -set fpga_part [get_property PART_NAME [current_board_part]] - -puts "INFO: $board_name is selected" -puts "INFO: $board_part is selected" -puts "INFO: $fpga_part is selected" - - # Create interface ports - set GT_Serial [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 GT_Serial ] - - - set gt_bridge_ip_0_diff_gt_ref_clock [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 gt_bridge_ip_0_diff_gt_ref_clock ] - set_property -dict [ list \ - CONFIG.FREQ_HZ {156250000} \ - ] $gt_bridge_ip_0_diff_gt_ref_clock - - - # Create ports - - # Create instance: axis_vio_0, and set properties - set axis_vio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_vio axis_vio_0 ] - set_property -dict [ list \ - CONFIG.C_NUM_PROBE_IN {4} \ - CONFIG.C_NUM_PROBE_OUT {2} \ - CONFIG.C_PROBE_OUT1_WIDTH {4} \ - ] $axis_vio_0 - - # Create instance: bufg_gt, and set properties - set bufg_gt [ create_bd_cell -type ip -vlnv xilinx.com:ip:bufg_gt bufg_gt ] - - # Create instance: bufg_gt_1, and set properties - set bufg_gt_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:bufg_gt bufg_gt_1 ] - - # Create instance: gt_bridge_ip_0, and set properties - set gt_bridge_ip_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:gt_bridge_ip gt_bridge_ip_0 ] - set_property -dict [ list \ - CONFIG.IP_LR0_SETTINGS {PRESET None RX_PAM_SEL NRZ TX_PAM_SEL NRZ RX_GRAY_BYP true TX_GRAY_BYP true\ -RX_GRAY_LITTLEENDIAN true TX_GRAY_LITTLEENDIAN true RX_PRECODE_BYP true\ -TX_PRECODE_BYP true RX_PRECODE_LITTLEENDIAN false TX_PRECODE_LITTLEENDIAN false\ -INTERNAL_PRESET None GT_TYPE GTY GT_DIRECTION DUPLEX TX_LINE_RATE 10.3125\ -TX_PLL_TYPE LCPLL TX_REFCLK_FREQUENCY 156.25 TX_ACTUAL_REFCLK_FREQUENCY\ -156.250000000000 TX_FRACN_ENABLED false TX_FRACN_NUMERATOR 0 TX_REFCLK_SOURCE\ -R0 TX_DATA_ENCODING RAW TX_USER_DATA_WIDTH 32 TX_INT_DATA_WIDTH 32\ -TX_BUFFER_MODE 1 TX_BUFFER_BYPASS_MODE Fast_Sync TX_PIPM_ENABLE false\ -TX_OUTCLK_SOURCE TXOUTCLKPMA TXPROGDIV_FREQ_ENABLE false TXPROGDIV_FREQ_SOURCE\ -LCPLL TXPROGDIV_FREQ_VAL 322.265625 TX_DIFF_SWING_EMPH_MODE CUSTOM\ -TX_64B66B_SCRAMBLER false TX_64B66B_ENCODER false TX_64B66B_CRC false\ -TX_RATE_GROUP A RX_LINE_RATE 10.3125 RX_PLL_TYPE LCPLL RX_REFCLK_FREQUENCY\ -156.25 RX_ACTUAL_REFCLK_FREQUENCY 156.250000000000 RX_FRACN_ENABLED false\ -RX_FRACN_NUMERATOR 0 RX_REFCLK_SOURCE R0 RX_DATA_DECODING RAW\ -RX_USER_DATA_WIDTH 32 RX_INT_DATA_WIDTH 32 RX_BUFFER_MODE 1 RX_OUTCLK_SOURCE\ -RXOUTCLKPMA RXPROGDIV_FREQ_ENABLE false RXPROGDIV_FREQ_SOURCE LCPLL\ -RXPROGDIV_FREQ_VAL 322.265625 INS_LOSS_NYQ 20 RX_EQ_MODE AUTO RX_COUPLING AC\ -RX_TERMINATION PROGRAMMABLE RX_RATE_GROUP A RX_TERMINATION_PROG_VALUE 800\ -RX_PPM_OFFSET 0 RX_64B66B_DESCRAMBLER false RX_64B66B_DECODER false\ -RX_64B66B_CRC false OOB_ENABLE false RX_COMMA_ALIGN_WORD 1\ -RX_COMMA_SHOW_REALIGN_ENABLE true PCIE_ENABLE false TX_LANE_DESKEW_HDMI_ENABLE\ -false RX_COMMA_P_ENABLE false RX_COMMA_M_ENABLE false RX_COMMA_DOUBLE_ENABLE\ -false RX_COMMA_P_VAL 0101111100 RX_COMMA_M_VAL 1010000011 RX_COMMA_MASK\ -0000000000 RX_SLIDE_MODE OFF RX_SSC_PPM 0 RX_CB_NUM_SEQ 0 RX_CB_LEN_SEQ 1\ -RX_CB_MAX_SKEW 1 RX_CB_MAX_LEVEL 1 RX_CB_MASK_0_0 false RX_CB_VAL_0_0 00000000\ -RX_CB_K_0_0 false RX_CB_DISP_0_0 false RX_CB_MASK_0_1 false RX_CB_VAL_0_1\ -00000000 RX_CB_K_0_1 false RX_CB_DISP_0_1 false RX_CB_MASK_0_2 false\ -RX_CB_VAL_0_2 00000000 RX_CB_K_0_2 false RX_CB_DISP_0_2 false RX_CB_MASK_0_3\ -false RX_CB_VAL_0_3 00000000 RX_CB_K_0_3 false RX_CB_DISP_0_3 false\ -RX_CB_MASK_1_0 false RX_CB_VAL_1_0 00000000 RX_CB_K_1_0 false RX_CB_DISP_1_0\ -false RX_CB_MASK_1_1 false RX_CB_VAL_1_1 00000000 RX_CB_K_1_1 false\ -RX_CB_DISP_1_1 false RX_CB_MASK_1_2 false RX_CB_VAL_1_2 00000000 RX_CB_K_1_2\ -false RX_CB_DISP_1_2 false RX_CB_MASK_1_3 false RX_CB_VAL_1_3 00000000\ -RX_CB_K_1_3 false RX_CB_DISP_1_3 false RX_CC_NUM_SEQ 0 RX_CC_LEN_SEQ 1\ -RX_CC_PERIODICITY 5000 RX_CC_KEEP_IDLE DISABLE RX_CC_PRECEDENCE ENABLE\ -RX_CC_REPEAT_WAIT 0 RX_CC_VAL\ -00000000000000000000000000000000000000000000000000000000000000000000000000000000\ -RX_CC_MASK_0_0 false RX_CC_VAL_0_0 00000000 RX_CC_K_0_0 false RX_CC_DISP_0_0\ -false RX_CC_MASK_0_1 false RX_CC_VAL_0_1 00000000 RX_CC_K_0_1 false\ -RX_CC_DISP_0_1 false RX_CC_MASK_0_2 false RX_CC_VAL_0_2 00000000 RX_CC_K_0_2\ -false RX_CC_DISP_0_2 false RX_CC_MASK_0_3 false RX_CC_VAL_0_3 00000000\ -RX_CC_K_0_3 false RX_CC_DISP_0_3 false RX_CC_MASK_1_0 false RX_CC_VAL_1_0\ -00000000 RX_CC_K_1_0 false RX_CC_DISP_1_0 false RX_CC_MASK_1_1 false\ -RX_CC_VAL_1_1 00000000 RX_CC_K_1_1 false RX_CC_DISP_1_1 false RX_CC_MASK_1_2\ -false RX_CC_VAL_1_2 00000000 RX_CC_K_1_2 false RX_CC_DISP_1_2 false\ -RX_CC_MASK_1_3 false RX_CC_VAL_1_3 00000000 RX_CC_K_1_3 false RX_CC_DISP_1_3\ -false PCIE_USERCLK2_FREQ 250 PCIE_USERCLK_FREQ 250 RX_JTOL_FC 6.1862627\ -RX_JTOL_LF_SLOPE -20 RX_BUFFER_BYPASS_MODE Fast_Sync RX_BUFFER_BYPASS_MODE_LANE\ -MULTI RX_BUFFER_RESET_ON_CB_CHANGE ENABLE RX_BUFFER_RESET_ON_COMMAALIGN DISABLE\ -RX_BUFFER_RESET_ON_RATE_CHANGE ENABLE TX_BUFFER_RESET_ON_RATE_CHANGE ENABLE\ -RESET_SEQUENCE_INTERVAL 0 RX_COMMA_PRESET NONE RX_COMMA_VALID_ONLY 0}\ - CONFIG.IP_LR1_SETTINGS {PRESET None RX_PAM_SEL NRZ TX_PAM_SEL NRZ RX_GRAY_BYP true TX_GRAY_BYP true\ -RX_GRAY_LITTLEENDIAN true TX_GRAY_LITTLEENDIAN true RX_PRECODE_BYP true\ -TX_PRECODE_BYP true RX_PRECODE_LITTLEENDIAN false TX_PRECODE_LITTLEENDIAN false\ -INTERNAL_PRESET None GT_TYPE GTY GT_DIRECTION DUPLEX TX_LINE_RATE 25.78125\ -TX_PLL_TYPE LCPLL TX_REFCLK_FREQUENCY 156.25 TX_ACTUAL_REFCLK_FREQUENCY\ -156.250000000000 TX_FRACN_ENABLED true TX_FRACN_NUMERATOR 0 TX_REFCLK_SOURCE R0\ -TX_DATA_ENCODING RAW TX_USER_DATA_WIDTH 64 TX_INT_DATA_WIDTH 64 TX_BUFFER_MODE\ -1 TX_BUFFER_BYPASS_MODE Fast_Sync TX_PIPM_ENABLE false TX_OUTCLK_SOURCE\ -TXOUTCLKPMA TXPROGDIV_FREQ_ENABLE false TXPROGDIV_FREQ_SOURCE LCPLL\ -TXPROGDIV_FREQ_VAL 322.265625 TX_DIFF_SWING_EMPH_MODE CUSTOM\ -TX_64B66B_SCRAMBLER false TX_64B66B_ENCODER false TX_64B66B_CRC false\ -TX_RATE_GROUP A RX_LINE_RATE 25.78125 RX_PLL_TYPE LCPLL RX_REFCLK_FREQUENCY\ -156.25 RX_ACTUAL_REFCLK_FREQUENCY 156.250000000000 RX_FRACN_ENABLED true\ -RX_FRACN_NUMERATOR 0 RX_REFCLK_SOURCE R0 RX_DATA_DECODING RAW\ -RX_USER_DATA_WIDTH 64 RX_INT_DATA_WIDTH 64 RX_BUFFER_MODE 1 RX_OUTCLK_SOURCE\ -RXOUTCLKPMA RXPROGDIV_FREQ_ENABLE false RXPROGDIV_FREQ_SOURCE LCPLL\ -RXPROGDIV_FREQ_VAL 322.265625 INS_LOSS_NYQ 20 RX_EQ_MODE AUTO RX_COUPLING AC\ -RX_TERMINATION PROGRAMMABLE RX_RATE_GROUP A RX_TERMINATION_PROG_VALUE 800\ -RX_PPM_OFFSET 0 RX_64B66B_DESCRAMBLER false RX_64B66B_DECODER false\ -RX_64B66B_CRC false OOB_ENABLE false RX_COMMA_ALIGN_WORD 1\ -RX_COMMA_SHOW_REALIGN_ENABLE true PCIE_ENABLE false TX_LANE_DESKEW_HDMI_ENABLE\ -false RX_COMMA_P_ENABLE false RX_COMMA_M_ENABLE false RX_COMMA_DOUBLE_ENABLE\ -false RX_COMMA_P_VAL 0101111100 RX_COMMA_M_VAL 1010000011 RX_COMMA_MASK\ -0000000000 RX_SLIDE_MODE OFF RX_SSC_PPM 0 RX_CB_NUM_SEQ 0 RX_CB_LEN_SEQ 1\ -RX_CB_MAX_SKEW 1 RX_CB_MAX_LEVEL 1 RX_CB_MASK_0_0 false RX_CB_VAL_0_0 00000000\ -RX_CB_K_0_0 false RX_CB_DISP_0_0 false RX_CB_MASK_0_1 false RX_CB_VAL_0_1\ -00000000 RX_CB_K_0_1 false RX_CB_DISP_0_1 false RX_CB_MASK_0_2 false\ -RX_CB_VAL_0_2 00000000 RX_CB_K_0_2 false RX_CB_DISP_0_2 false RX_CB_MASK_0_3\ -false RX_CB_VAL_0_3 00000000 RX_CB_K_0_3 false RX_CB_DISP_0_3 false\ -RX_CB_MASK_1_0 false RX_CB_VAL_1_0 00000000 RX_CB_K_1_0 false RX_CB_DISP_1_0\ -false RX_CB_MASK_1_1 false RX_CB_VAL_1_1 00000000 RX_CB_K_1_1 false\ -RX_CB_DISP_1_1 false RX_CB_MASK_1_2 false RX_CB_VAL_1_2 00000000 RX_CB_K_1_2\ -false RX_CB_DISP_1_2 false RX_CB_MASK_1_3 false RX_CB_VAL_1_3 00000000\ -RX_CB_K_1_3 false RX_CB_DISP_1_3 false RX_CC_NUM_SEQ 0 RX_CC_LEN_SEQ 1\ -RX_CC_PERIODICITY 5000 RX_CC_KEEP_IDLE DISABLE RX_CC_PRECEDENCE ENABLE\ -RX_CC_REPEAT_WAIT 0 RX_CC_VAL\ -00000000000000000000000000000000000000000000000000000000000000000000000000000000\ -RX_CC_MASK_0_0 false RX_CC_VAL_0_0 00000000 RX_CC_K_0_0 false RX_CC_DISP_0_0\ -false RX_CC_MASK_0_1 false RX_CC_VAL_0_1 00000000 RX_CC_K_0_1 false\ -RX_CC_DISP_0_1 false RX_CC_MASK_0_2 false RX_CC_VAL_0_2 00000000 RX_CC_K_0_2\ -false RX_CC_DISP_0_2 false RX_CC_MASK_0_3 false RX_CC_VAL_0_3 00000000\ -RX_CC_K_0_3 false RX_CC_DISP_0_3 false RX_CC_MASK_1_0 false RX_CC_VAL_1_0\ -00000000 RX_CC_K_1_0 false RX_CC_DISP_1_0 false RX_CC_MASK_1_1 false\ -RX_CC_VAL_1_1 00000000 RX_CC_K_1_1 false RX_CC_DISP_1_1 false RX_CC_MASK_1_2\ -false RX_CC_VAL_1_2 00000000 RX_CC_K_1_2 false RX_CC_DISP_1_2 false\ -RX_CC_MASK_1_3 false RX_CC_VAL_1_3 00000000 RX_CC_K_1_3 false RX_CC_DISP_1_3\ -false PCIE_USERCLK2_FREQ 250 PCIE_USERCLK_FREQ 250 RX_JTOL_FC 10\ -RX_JTOL_LF_SLOPE -20 RX_BUFFER_BYPASS_MODE Fast_Sync RX_BUFFER_BYPASS_MODE_LANE\ -MULTI RX_BUFFER_RESET_ON_CB_CHANGE ENABLE RX_BUFFER_RESET_ON_COMMAALIGN DISABLE\ -RX_BUFFER_RESET_ON_RATE_CHANGE ENABLE TX_BUFFER_RESET_ON_RATE_CHANGE ENABLE\ -RESET_SEQUENCE_INTERVAL 0 RX_COMMA_PRESET NONE RX_COMMA_VALID_ONLY 0}\ - CONFIG.IP_NO_OF_LANES {1} \ - ] $gt_bridge_ip_0 - - # Create instance: gt_quad_base_0, and set properties - set gt_quad_base_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:gt_quad_base gt_quad_base_0 ] - set_property -dict [ list \ - CONFIG.PORTS_INFO_DICT {\ - LANE_SEL_DICT {unconnected {RX0 RX1 RX3 TX0 TX1 TX3} PROT0 {RX2 TX2}}\ - GT_TYPE {GTY}\ - REG_CONF_INTF {APB3_INTF}\ - BOARD_PARAMETER {}\ - } \ - CONFIG.QUAD_USAGE {\ - TX_QUAD_CH {TXQuad_0_/gt_quad_base_0 {/gt_quad_base_0\ - undef,undef,design_1_gt_bridge_ip_0_0.IP_CH0,undef MSTRCLK 0,0,1,0\ - IS_CURRENT_QUAD 1}}\ - RX_QUAD_CH {RXQuad_0_/gt_quad_base_0 {/gt_quad_base_0\ - undef,undef,design_1_gt_bridge_ip_0_0.IP_CH0,undef MSTRCLK 0,0,1,0\ - IS_CURRENT_QUAD 1}}\ - } \ - CONFIG.REFCLK_STRING {HSCLK1_LCPLLGTREFCLK0 refclk_PROT0_R0_156.25_MHz_unique1} \ - ] $gt_quad_base_0 - - # Create instance: urlp, and set properties - set urlp [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic urlp ] - set_property -dict [ list \ - CONFIG.C_SIZE {1} \ - ] $urlp - - # Create instance: util_ds_buf, and set properties - set util_ds_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf util_ds_buf ] - set_property -dict [ list \ - CONFIG.C_BUF_TYPE {IBUFDSGTE} \ - ] $util_ds_buf - - # Create instance: versal_cips_0, and set properties - set versal_cips_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:versal_cips versal_cips_0 ] - apply_bd_automation -rule xilinx.com:bd_rule:cips -config { board_preset {Yes} boot_config {Custom} configure_noc {Add new AXI NoC} debug_config {JTAG} design_flow {Full System} mc_type {None} num_mc {1} pl_clocks {1} pl_resets {None}} [get_bd_cells versal_cips_0] - set_property -dict [list CONFIG.PS_PMC_CONFIG { CLOCK_MODE Custom PMC_CRP_PL0_REF_CTRL_FREQMHZ 100} CONFIG.CLOCK_MODE {Custom}] [get_bd_cells versal_cips_0] - - # Create instance: xlcp, and set properties - set xlcp [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat xlcp ] - set_property -dict [ list \ - CONFIG.NUM_PORTS {1} \ - ] $xlcp - - # Create interface connections - connect_bd_intf_net -intf_net gt_bridge_ip_0_GT_RX0 [get_bd_intf_pins gt_bridge_ip_0/GT_RX0] [get_bd_intf_pins gt_quad_base_0/RX2_GT_IP_Interface] - connect_bd_intf_net -intf_net gt_bridge_ip_0_GT_TX0 [get_bd_intf_pins gt_bridge_ip_0/GT_TX0] [get_bd_intf_pins gt_quad_base_0/TX2_GT_IP_Interface] - connect_bd_intf_net -intf_net gt_bridge_ip_0_diff_gt_ref_clock_1 [get_bd_intf_ports gt_bridge_ip_0_diff_gt_ref_clock] [get_bd_intf_pins util_ds_buf/CLK_IN_D] - connect_bd_intf_net -intf_net gt_quad_base_0_GT_Serial [get_bd_intf_ports GT_Serial] [get_bd_intf_pins gt_quad_base_0/GT_Serial] - - # Create port connections - connect_bd_net -net axis_vio_0_probe_out0 [get_bd_pins axis_vio_0/probe_out0] [get_bd_pins gt_bridge_ip_0/gtreset_in] - connect_bd_net -net axis_vio_0_probe_out1 [get_bd_pins axis_vio_0/probe_out1] [get_bd_pins gt_bridge_ip_0/rate_sel] - connect_bd_net -net bufg_gt_1_usrclk [get_bd_pins bufg_gt_1/usrclk] [get_bd_pins gt_bridge_ip_0/gt_txusrclk] [get_bd_pins gt_quad_base_0/ch2_txusrclk] - connect_bd_net -net bufg_gt_usrclk [get_bd_pins bufg_gt/usrclk] [get_bd_pins gt_bridge_ip_0/gt_rxusrclk] [get_bd_pins gt_quad_base_0/ch2_rxusrclk] - connect_bd_net -net gt_bridge_ip_0_link_status_out [get_bd_pins axis_vio_0/probe_in0] [get_bd_pins gt_bridge_ip_0/link_status_out] - connect_bd_net -net gt_bridge_ip_0_rx_resetdone_out [get_bd_pins axis_vio_0/probe_in2] [get_bd_pins gt_bridge_ip_0/rx_resetdone_out] - connect_bd_net -net gt_bridge_ip_0_tx_resetdone_out [get_bd_pins axis_vio_0/probe_in1] [get_bd_pins gt_bridge_ip_0/tx_resetdone_out] - connect_bd_net -net gt_quad_base_0_ch2_rxoutclk [get_bd_pins bufg_gt/outclk] [get_bd_pins gt_quad_base_0/ch2_rxoutclk] - connect_bd_net -net gt_quad_base_0_ch2_txoutclk [get_bd_pins bufg_gt_1/outclk] [get_bd_pins gt_quad_base_0/ch2_txoutclk] - connect_bd_net -net gt_quad_base_0_gtpowergood [get_bd_pins gt_quad_base_0/gtpowergood] [get_bd_pins xlcp/In0] - connect_bd_net -net gt_quad_base_0_hsclk1_lcplllock [get_bd_pins axis_vio_0/probe_in3] [get_bd_pins gt_quad_base_0/hsclk1_lcplllock] - connect_bd_net -net urlp_Res [get_bd_pins gt_bridge_ip_0/gtpowergood] [get_bd_pins urlp/Res] - connect_bd_net -net util_ds_buf_0_IBUF_OUT [get_bd_pins axis_vio_0/clk] [get_bd_pins gt_bridge_ip_0/apb3clk] [get_bd_pins gt_quad_base_0/apb3clk] [get_bd_pins versal_cips_0/pl0_ref_clk] - connect_bd_net -net util_ds_buf_IBUF_OUT [get_bd_pins gt_quad_base_0/GT_REFCLK0] [get_bd_pins util_ds_buf/IBUF_OUT] - connect_bd_net -net xlcp_dout [get_bd_pins urlp/Op1] [get_bd_pins xlcp/dout] - - # Create address segments - - assign_bd_address - validate_bd_design - regenerate_bd_layout - make_wrapper -files [get_files $design_name.bd] -top -import -quiet - - puts "INFO: End of create_root_design" -} - - # - # Create XDC with location and timing constraints - # - proc make_xdc {design_name} { - load librdi_iptasks[info sharedlibextension] - set filepathdir [file join [get_property DIRECTORY [current_project]] ${design_name}.xdc] - set outputfile [open $filepathdir w] - - set coord "X0Y5" - puts $outputfile "#GTY Location Bank 105 QUAD_$coord" - set inst "${design_name}_i/gt_quad_base_0/inst/quad_inst" - puts $outputfile "set_property LOC GTY_QUAD_${coord} \[get_cells $inst\]" - puts $outputfile "" - - set ref_coord "X0Y11" - puts $outputfile "#Refclk Location Bank 105 $ref_coord" - set inst "${design_name}_i/util_ds_buf/U0/USE_IBUFDS_GTE5.GEN_IBUFDS_GTE5\[0\].IBUFDS_GTE5_I" - puts $outputfile "set_property LOC GTY_REFCLK_${ref_coord} \[get_cells $inst\]" - - set refclk_freq "156.25" - puts $outputfile "#Refclk $refclk_freq MHz" - set ref_period [expr 1000 / $refclk_freq] - set name "ip_0" - puts $outputfile "create_clock -period ${ref_period} \[get_ports gt_bridge_${name}_diff_gt_ref_clock_clk_p\[0\]\]" - puts $outputfile "" - - puts $outputfile "#vio false_path" - puts $outputfile "set_false_path -through \[get_pins -hier *axis_vio*probe*out*\]" - puts $outputfile "set_false_path -through \[get_pins -hier *axis_vio*probe*in*\]" - - close $outputfile - - import_files -fileset constrs_1 -norecurse "$filepathdir" - } - - -################################################################## -# MAIN FLOW -################################################################## - -create_root_design "" $design_name $options -make_xdc $design_name - # close_bd_design [get_bd_designs $design_name] - # set bdDesignPath [file join [get_property directory [current_project]] [current_project].srcs sources_1 bd $design_name] - open_bd_design [get_bd_files $design_name] - # Add USER_COMMENTS on $design_name - set_property USER_COMMENTS.comment_0 {} [current_bd_design] - -regenerate_bd_layout -layout_string { - "ActiveEmotionalView":"Default View", - "comment_0":"1. Refer to README.md in below url: - https://github.com/Xilinx/XilinxCEDStore/tree/master/ced/Xilinx/IPI/Versal%20Multi-Rate%20GTY - 2. Verify constraints in top level xdc - 3. Synthesize and open synthesized design to verify GTY and REFCLK pin assignments. - 3. Select Generate Device Image in the Flow Navigator to create .pdi image. - 4. Program pdi and refer to README.md for board bringup and enabling IBERT in hardware manager.", - "commentid":"comment_0|", - "font_comment_0":"18", - "guistr":"# # String gsaved with Nlview 7.0r4 2019-12-20 bk=1.5203 VDI=41 GEI=36 GUI=JA:10.0 TLS - # -string -flagsOSRD - preplace cgraphic comment_0 place top 407 -200 textcolor 4 linecolor 3 - ", - "linktoobj_comment_0":"", - "linktotype_comment_0":"bd_design" } - save_bd_design -} diff --git a/ced/Xilinx/IPI/Versal Multi-Rate GTY/xitem.json b/ced/Xilinx/IPI/Versal Multi-Rate GTY/xitem.json deleted file mode 100644 index 5637a53..0000000 --- a/ced/Xilinx/IPI/Versal Multi-Rate GTY/xitem.json +++ /dev/null @@ -1,33 +0,0 @@ -{ - "config": { - "items": [ - { - "infra": { - "name": "multirategty", - "display": "Multi-Rate GTY", - "revision": "1.0", - "description": "A Versal example design that demonstrates Multi-Rate GTY", - "company": "xilinx.com", - "company_display": "Xilinx", - "author": "jhua", - "contributors": [ - { - "group": "Xilinx", - "url": "www.xilinx.com" - } - ], - "category": "Versal", - "website": "www.xilinx.com", - "is_active" : true, - "search-keywords": [ - "GTY", - "xilinx.com", - "example" - ] - } - } - ] - }, - "_major" : 1, - "_minor" : 0 -}