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common.cpp
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2888 lines (2445 loc) · 88.1 KB
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/*****************************************************************************
* common.cpp - Common code used by all the HDA miniports.
*****************************************************************************
* Copyright (c) 2025 Drew Hoffman
* Released under MIT License
* Code from BleskOS and Microsoft's driver samples used under MIT license.
*
* Implmentation of the common code object. This class deals with interrupts
* for the device, and is a collection of common code used by all the
* miniports.
*/
#include "stdunk.h"
#include "common.h"
#include "codec.h"
#define STR_MODULENAME "HDACommon: "
#define BDLE_FLAG_IOC 0x01
typedef struct _BDLE {
ULONG64 Address;
ULONG Length;
ULONG Flags;
} BDLE;
#define CHUNK_SIZE 1792 //100ms of 44khz 16bit stereo rounded up to nearest 128b
/*****************************************************************************
* CAdapterCommon
*****************************************************************************
* Adapter common object.
*/
class CAdapterCommon
: public IAdapterCommon,
public IAdapterPowerManagement,
public CUnknown
{
private:
PMDL mdl;
KSPIN_LOCK QLock;
PDMA_ADAPTER DMA_Adapter;
PDEVICE_DESCRIPTION pDeviceDescription;
//PCI IDs
USHORT pci_ven;
USHORT pci_dev;
PUCHAR pConfigMem;
USHORT codec_ven;
USHORT codec_dev;
// MMIO registers
volatile PUCHAR m_pHDARegisters;
PUCHAR Base;
USHORT InputStreamBase;
USHORT OutputStreamBase;
// CORB/RIRB buffers
// need to be in different 4k pages
volatile PULONG RirbMemVirt;
PHYSICAL_ADDRESS RirbMemPhys;
USHORT RirbPointer;
USHORT RirbNumberOfEntries;
volatile PULONG CorbMemVirt;
PHYSICAL_ADDRESS CorbMemPhys;
USHORT CorbPointer;
USHORT CorbNumberOfEntries;
volatile PULONG BdlMemVirt;
PHYSICAL_ADDRESS BdlMemPhys;
USHORT BdlPointer;
USHORT BdlNumberOfEntries;
volatile PULONG DmaPosVirt;
PHYSICAL_ADDRESS DmaPosPhys;
ULONG bad_dpos_count;
// Output buffer information
PULONG OutputBufferList;
PVOID BufVirtualAddress;
PHYSICAL_ADDRESS BufLogicalAddress;
UCHAR interrupt;
ULONG memLength;
UCHAR codecNumber;
UCHAR nSDO;
UCHAR FirstOutputStream;
USHORT statests;
BOOLEAN is64OK;
ULONG communication_type;
ULONG debug_kludge;
// Codec array - packed array of initialized codecs (not sparse)
HDA_Codec* pCodecs[16];
UCHAR codecCount; // Number of actually initialized codecs
BOOLEAN m_bDMAInitialized; // DMA initialized flag
BOOLEAN m_bCORBInitialized; // CORB initialized flag
BOOLEAN m_bRIRBInitialized; // RIRB initialized flag
PDEVICE_OBJECT m_pDeviceObject; // Device object used for registry access.
DEVICE_POWER_STATE m_PowerState; // Current power state of the device.
PINTERRUPTSYNC m_pInterruptSync;
PUCHAR m_pWaveBase;
PUCHAR m_pUartBase;
PPORTWAVECYCLIC m_pPortWave;
PPORTDMUS m_pPortUart;
PSERVICEGROUP m_pServiceGroupWave;
ULONGLONG m_startTime;
BOOL m_bCaptureActive;
BYTE MixerSettings[DSP_MIX_MAXREGS];
HDA_INTERRUPT_TYPE AcknowledgeIRQ
( void
);
BOOLEAN AdapterISR
( void
);
STDMETHODIMP_(NTSTATUS) ReadWriteConfigSpace(
IN PDEVICE_OBJECT DeviceObject,
IN ULONG ReadOrWrite, // 0 for read, 1 for write
IN PVOID Buffer,
IN ULONG Offset,
IN ULONG Length
);
STDMETHODIMP_(NTSTATUS) WriteConfigSpaceByte(UCHAR offset, UCHAR andByte, UCHAR orByte);
STDMETHODIMP_(NTSTATUS) WriteConfigSpaceWord(UCHAR offset, USHORT andWord, USHORT orWord);
STDMETHODIMP_(BOOLEAN) ReadRegistryBoolean(
IN PCWSTR ValueName,
IN BOOLEAN DefaultValue
);
public:
DECLARE_STD_UNKNOWN();
DEFINE_STD_CONSTRUCTOR(CAdapterCommon);
~CAdapterCommon();
/*****************************************************************************
* IAdapterCommon methods
*/
STDMETHODIMP_(NTSTATUS) Init
(
IN PRESOURCELIST ResourceList,
IN PDEVICE_OBJECT DeviceObject
);
STDMETHODIMP_(PINTERRUPTSYNC) GetInterruptSync
( void
);
STDMETHODIMP_(PDEVICE_DESCRIPTION) GetDeviceDescription
( void
);
STDMETHODIMP_(PUNKNOWN *) WavePortDriverDest
( void
);
STDMETHODIMP_(PUNKNOWN *) MidiPortDriverDest
( void
);
STDMETHODIMP_(void) SetWaveServiceGroup
(
IN PSERVICEGROUP ServiceGroup
);
STDMETHODIMP_(BYTE) ReadController
( void
);
STDMETHODIMP_(BOOLEAN) WriteController
(
IN BYTE Value
);
STDMETHODIMP_(NTSTATUS) ResetController
( void
);
STDMETHODIMP_(NTSTATUS) hda_stop_stream
( void
);
STDMETHODIMP_(void) MixerRegWrite
(
IN BYTE Index,
IN BYTE Value
);
STDMETHODIMP_(BYTE) MixerRegRead
(
IN BYTE Index
);
STDMETHODIMP_(void) MixerReset
( void
);
STDMETHODIMP RestoreMixerSettingsFromRegistry
( void
);
STDMETHODIMP SaveMixerSettingsToRegistry
( void
);
STDMETHODIMP_(NTSTATUS) ProgramSampleRate
(
IN DWORD dwSampleRate
);
STDMETHODIMP_(NTSTATUS) InitHDAController (void);
STDMETHODIMP_(ULONG) hda_send_verb(ULONG codec, ULONG node, ULONG verb, ULONG command);
static ULONG SendVerb(CAdapterCommon* pAdapter, ULONG codec, ULONG node, ULONG verb, ULONG command);
STDMETHODIMP_(PULONG) get_bdl_mem(void);
STDMETHODIMP_(ULONG) hda_get_actual_stream_position(void);
STDMETHODIMP_(UCHAR) hda_get_node_type(ULONG codec, ULONG node);
STDMETHODIMP_(ULONG) hda_get_node_connection_entries(ULONG codec, ULONG node, ULONG connection_entries_number);
STDMETHODIMP_(BOOLEAN) hda_is_headphone_connected (void);
STDMETHODIMP_(void) hda_set_node_gain(ULONG codec, ULONG node, ULONG node_type, ULONG capabilities, ULONG gain, UCHAR ch);
STDMETHODIMP_(void) hda_set_volume(ULONG volume, UCHAR ch);
STDMETHODIMP_(void) hda_start_sound (void);
STDMETHODIMP_(void) hda_stop_sound (void);
STDMETHODIMP_(void) hda_check_headphone_connection_change(void);
STDMETHODIMP_(UCHAR) hda_is_supported_sample_rate(ULONG sample_rate);
STDMETHODIMP_(void) hda_enable_pin_output(ULONG codec, ULONG pin_node);
STDMETHODIMP_(void) hda_disable_pin_output(ULONG codec, ULONG pin_node);
STDMETHODIMP_(NTSTATUS) hda_showtime(PDMACHANNEL DmaChannel);
STDMETHODIMP_(USHORT) hda_return_sound_data_format(ULONG sample_rate, ULONG channels, ULONG bits_per_sample);
STDMETHODIMP_(UCHAR) readUCHAR(USHORT reg);
STDMETHODIMP_(void) writeUCHAR(USHORT reg, UCHAR value);
STDMETHODIMP_(void) setUCHARBit(USHORT reg, UCHAR flag);
STDMETHODIMP_(void) clearUCHARBit(USHORT reg, UCHAR flag);
STDMETHODIMP_(USHORT) readUSHORT(USHORT reg);
STDMETHODIMP_(void) writeUSHORT(USHORT reg, USHORT value);
STDMETHODIMP_(ULONG) readULONG(USHORT reg);
STDMETHODIMP_(void) writeULONG(USHORT reg, ULONG value);
STDMETHODIMP_(void) setULONGBit(USHORT reg, ULONG flag);
STDMETHODIMP_(void) clearULONGBit(USHORT reg, ULONG flag);
/*************************************************************************
* IAdapterPowerManagement implementation
*
* This macro is from PORTCLS.H. It lists all the interface's functions.
*/
IMP_IAdapterPowerManagement;
friend
NTSTATUS
NewAdapterCommon
(
OUT PADAPTERCOMMON * OutAdapterCommon,
IN PRESOURCELIST ResourceList
);
friend
NTSTATUS
InterruptServiceRoutine
(
IN PINTERRUPTSYNC InterruptSync,
IN PVOID DynamicContext
);
};
static
MIXERSETTING DefaultMixerSettings[] =
{
{ L"LeftMasterVol", DSP_MIX_MASTERVOLIDX_L, 0xD8 },
{ L"RightMasterVol", DSP_MIX_MASTERVOLIDX_R, 0xD8 },
{ L"LeftWaveVol", DSP_MIX_VOICEVOLIDX_L, 0xD8 },
{ L"RightWaveVol", DSP_MIX_VOICEVOLIDX_R, 0xD8 },
{ L"LeftMidiVol", DSP_MIX_FMVOLIDX_L, 0xD8 },
{ L"RightMidiVol", DSP_MIX_FMVOLIDX_R, 0xD8 },
{ L"LeftCDVol", DSP_MIX_CDVOLIDX_L, 0xD8 },
{ L"RightCDVol", DSP_MIX_CDVOLIDX_R, 0xD8 },
{ L"LeftLineInVol", DSP_MIX_LINEVOLIDX_L, 0xD8 },
{ L"RightLineInVol", DSP_MIX_LINEVOLIDX_R, 0xD8 },
{ L"MicVol", DSP_MIX_MICVOLIDX, 0xD8 },
{ L"PcSpkrVol", DSP_MIX_SPKRVOLIDX, 0x00 },
{ L"OutputMixer", DSP_MIX_OUTMIXIDX, 0x1E },
{ L"LeftInputMixer", DSP_MIX_ADCMIXIDX_L, 0x55 },
{ L"RightInputMixer", DSP_MIX_ADCMIXIDX_R, 0x2B },
{ L"LeftInputGain", DSP_MIX_INGAINIDX_L, 0x00 },
{ L"RightInputGain", DSP_MIX_INGAINIDX_R, 0x00 },
{ L"LeftOutputGain", DSP_MIX_OUTGAINIDX_L, 0x80 },
{ L"RightOutputGain", DSP_MIX_OUTGAINIDX_R, 0x80 },
{ L"MicAGC", DSP_MIX_AGCIDX, 0x01 },
{ L"LeftTreble", DSP_MIX_TREBLEIDX_L, 0x80 },
{ L"RightTreble", DSP_MIX_TREBLEIDX_R, 0x80 },
{ L"LeftBass", DSP_MIX_BASSIDX_L, 0x80 },
{ L"RightBass", DSP_MIX_BASSIDX_R, 0x80 },
};
//driver settings via registry keys
static BOOLEAN skipControllerReset;
static BOOLEAN skipCodecReset;
static BOOLEAN useAltOut;
static BOOLEAN useSPDIF;
static BOOLEAN useDisabledPins;
static BOOLEAN useDmaPos;
static REG_BOOL_SETTING g_BooleanSettings[] =
{
{ L"SkipControllerReset", &skipControllerReset, FALSE },
{ L"SkipCodecReset", &skipCodecReset, FALSE },
{ L"UseAltOut", &useAltOut, FALSE },
{ L"UseSPDIF", &useSPDIF, TRUE },
{ L"UseDisabledPins", &useDisabledPins, FALSE },
{ L"UseDmaPos", &useDmaPos, FALSE },
};
#pragma code_seg("PAGE")
/*****************************************************************************
* NewAdapterCommon()
*****************************************************************************
* Create a new adapter common object.
*/
NTSTATUS
NewAdapterCommon
(
OUT PUNKNOWN * Unknown,
IN REFCLSID,
IN PUNKNOWN UnknownOuter OPTIONAL,
IN POOL_TYPE PoolType
)
{
PAGED_CODE();
ASSERT(Unknown);
STD_CREATE_BODY_
(
CAdapterCommon,
Unknown,
UnknownOuter,
PoolType,
PADAPTERCOMMON
);
}
//100ms of 2ch 16 bit audio 4410 * 2 * 2
ULONG audBufSize = MAXLEN_DMA_BUFFER;
ULONG BdlSize = 256 * 16; //256 entries, 16 bytes each
/*****************************************************************************
* CAdapterCommon::Init()
*****************************************************************************
* Initialize an adapter common object.
*/
NTSTATUS
CAdapterCommon::
Init
(
IN PRESOURCELIST ResourceList,
IN PDEVICE_OBJECT DeviceObject
)
{
PAGED_CODE();
ASSERT(ResourceList);
ASSERT(DeviceObject);
NTSTATUS ntStatus = STATUS_SUCCESS;
PHYSICAL_ADDRESS physAddr = {0};
DOUT (DBG_PRINT, ("[CAdapterCommon::Init]"));
ULONG i;
//
// Save the device object
//
m_pDeviceObject = DeviceObject;
//Make sure cache line size set in device object is >= 128 byte for alignment reasons
DOUT(DBG_SYSINFO, ("Initial PDO align was %d",
m_pDeviceObject -> AlignmentRequirement));
if (m_pDeviceObject -> AlignmentRequirement < FILE_128_BYTE_ALIGNMENT) {
m_pDeviceObject -> AlignmentRequirement = FILE_128_BYTE_ALIGNMENT;
DOUT(DBG_SYSINFO, ("Adjusted it to %d",
m_pDeviceObject -> AlignmentRequirement));
}
//init spin lock for protecting the CORB/RIRB or PIO
KeInitializeSpinLock(&QLock);
//Read settings from registry
for (i = 0; i < ARRAY_COUNT(g_BooleanSettings); ++i){
*g_BooleanSettings[i].Variable =
ReadRegistryBoolean(g_BooleanSettings[i].ValueName,
g_BooleanSettings[i].DefaultValue);
}
// Initialize codec array
codecCount = 0;
for (i = 0; i < 16; i++) {
pCodecs[i] = NULL;
}
//send an IRP asking the bus driver to read all of configspace
//asking the PnP Config manager does NOT work since we're still in the middle of StartDevice()
ULONG pci_ven = 0;
ULONG pci_dev = 0;
pConfigMem = (PUCHAR)ExAllocatePoolWithTag(NonPagedPool, 256,'gfcP');
ntStatus = ReadWriteConfigSpace(
m_pDeviceObject,
0, //read
pConfigMem, // Buffer to store the configuration data
0, // Offset into the configuration space
256 // Number of bytes to read
);
if (!NT_SUCCESS (ntStatus)){
DbgPrint( "\nPCI Configspace Read Failed! 0x%X\n", ntStatus);
return ntStatus;
} else {
PUSHORT pConfigMemS = (PUSHORT)pConfigMem;
//VID and PID are first 2 words of configspace
pci_ven = (USHORT)pConfigMemS[0];
pci_dev = (USHORT)pConfigMemS[1];
DbgPrint( "\nHDA Controller: VID:0x%04X PID:0x%04X : ", pci_ven, pci_dev);
}
USHORT tmp;
//apply device-specific config space patches depending on the VID/PID
switch (pci_ven){
case 0x1002: //ATI
case 0x1022: //AMD
if ( (pci_dev == 0x437b) || (pci_dev == 0x4383) //ATI SB
|| (pci_dev == 0x780d) //Hudson
|| (pci_dev == 0x1457) || (pci_dev == 0x1487) //AMD Ryzen
|| (pci_dev == 0x157a) || (pci_dev == 0x15e3) //AMD APU
){
DbgPrint( "ATI/AMD SB450/600/APU Snoop\n");
//Enable Snoop
ntStatus = WriteConfigSpaceByte(0x42,
~0x03, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
//should read back & confirm it was set.
} else if ( (pci_dev == 0x0002) || (pci_dev == 0x1308)
|| (pci_dev == 0x157a) || (pci_dev == 0x15b3)
){
DbgPrint( "ATI/AMD HDMI No Snoop\n");
//Disable Snoop
ntStatus = WriteConfigSpaceByte(0x42,
~ATI_SB450_HDAUDIO_ENABLE_SNOOP, 0);
} else {
DbgPrint( "ATI/AMD Other\n");
}
break;
case 0x10de: //nvidia
if ( (pci_dev == 0x026c) || (pci_dev == 0x0371) //MCP5x
|| (pci_dev == 0x03e4) || (pci_dev == 0x03f0) //MCP61
|| (pci_dev == 0x044a) || (pci_dev == 0x044b) //MCP65
|| (pci_dev == 0x055c) || (pci_dev == 0x055d) //MCP67
|| (pci_dev == 0x0774) || (pci_dev == 0x0775) //MCP77
|| (pci_dev == 0x0776) || (pci_dev == 0x0777) //MCP77
|| (pci_dev == 0x07fc) || (pci_dev == 0x07fd) //MCP73
|| (pci_dev == 0x0ac0) || (pci_dev == 0x0ac1) //MCP79
|| (pci_dev == 0x0ac2) || (pci_dev == 0x0ac3) //MCP79
|| (pci_dev == 0x0d94) || (pci_dev == 0x0d95) //MCP89
|| (pci_dev == 0x0d96) || (pci_dev == 0x0d97) //MCP
){
DbgPrint( "Nvidia MCP\n");
ntStatus = WriteConfigSpaceByte(0x4e,
~NVIDIA_HDA_ENABLE_COHBITS, NVIDIA_HDA_ENABLE_COHBITS);
} else{
DbgPrint("Nvidia HDMI\n");
}
break;
case 0x8086: //Intel
switch (pci_dev){
case 0x2668://ICH6
case 0x27D8://ICH7
DbgPrint( "Intel ICH6/7\n");
//set device 27 function 0 configspace offset 40h bit 0 to 1
//to enable HDA link mode (if it isnt already)
ntStatus = WriteConfigSpaceByte(0x40, 0xfe, 0x01);
break;
//ICH
case 0x269a:
case 0x284b:
case 0x2911:
case 0x293e:
case 0x293f:
case 0x3a3e: //ICH8
case 0x3a6e: //ICH9
DbgPrint( "Intel ICH\n"); //these don't need nosnoop flag changed (?)
break;
//PCH
case 0x1c20:
case 0x1d20:
case 0x1e20:
case 0x8c20:
case 0x8ca0:
case 0x8d20:
case 0x8d21:
case 0xa1f0:
case 0xa270:
case 0x9c20:
case 0x9c21:
case 0x9ca0:
//SKL
case 0xa170:
case 0x9d70:
case 0xa171:
case 0x9d71:
case 0xa2f0:
case 0xa348:
case 0x9dc8:
case 0x02c8:
case 0x06c8:
case 0xf1c8:
case 0xa3f0:
case 0xf0c8:
case 0x34c8:
case 0x3dc8:
case 0x4dc8:
case 0xa0c8:
case 0x43c8:
case 0x490d:
case 0x7da0:
case 0x51c8:
case 0x51cc:
case 0x4b55:
case 0x4b58:
case 0x5a98:
case 0x1a98:
case 0x3198:
//HDMI
case 0x0a0c:
case 0x0c0c:
case 0x0d0c:
case 0x160c:
//SCH
case 0x3b56:
case 0x811b:
case 0x080a:
case 0x0f04:
case 0x2284:
DbgPrint( "Intel PCH/SCH/SKL/HDMI\n");
//disable no-snoop transaction feature (clear bit 11) if it is set
tmp = *((PUSHORT)(pConfigMem + INTEL_SCH_HDA_DEVC));
if((tmp & INTEL_SCH_HDA_DEVC_NOSNOOP) != 0){
DbgPrint( "0x%X - disabling nosnoop transactions\n", tmp);
ntStatus = WriteConfigSpaceWord(INTEL_SCH_HDA_DEVC,
~((USHORT)INTEL_SCH_HDA_DEVC_NOSNOOP), 0);
} else {
DbgPrint( "0x%X - snoop already ok\n", tmp);
}
break;
default:
DbgPrint( "Unknown intel chipset PID %X\n", pci_dev);
}
break;
case 0x10b9://ULI M5461
DbgPrint( "ULI\n");
//disable and zero out BAR1 on this hardware;
//it advertises 64 bit addressing support but can't deliver
//not that we can use it anyway in 9x.
//this is according to ALSA.
//TODO: test this if i can find this rare chipset
ntStatus = WriteConfigSpaceWord(0x40,0xffef,0x0010);
ntStatus = WriteConfigSpaceWord(0x14,0x0000,0x0000);
ntStatus = WriteConfigSpaceWord(0x16,0x0000,0x0000);
break;
default:
DbgPrint( "unknown or no special patches\n");
break;
}
//Set TCSEL (offset 44h in config space, lowest 3 bits) to 0 on some hardware to avoid crackling/static.
//the Watlers and MPXPlay drivers set this byte on all but ATI controllers
//I'm not sure if class 0 is the highest or lowest priority. some hardware defaults to traffic class 7
if(pci_ven != 0x1002){
ntStatus = WriteConfigSpaceByte(0x44, 0xf8, 0x0);
}
if (!NT_SUCCESS (ntStatus)){
DbgPrint( "\nPCI Config Space Write Failed! 0x%X\n", ntStatus);
//return ntStatus; //is failure fatal? i dont think so
}
//there may be multiple instances of this driver loaded at once
//on systems with HDMI display audio support for instance
//but it should be one driver object per HDA controller.
//which may access multiple codecs
//for now only sending 1 output audio stream to all
//
//Get the memory base address for the HDA controller registers.
// note we only want the first BAR
// on Skylake and newer mobile chipsets,
// there is a DSP interface at BAR2 for Intel Smart Sound Technology
// TODO: fix adapter.cpp to check for this better
DOUT(DBG_SYSINFO, ("%d Resources in List", ResourceList->NumberOfEntries() ));
for (i = 0; i < ResourceList->NumberOfEntries(); i++) {
PCM_PARTIAL_RESOURCE_DESCRIPTOR desc = ResourceList->FindTranslatedEntry(CmResourceTypeMemory, i);
if (desc) {
if (!memLength) {
physAddr = desc->u.Memory.Start;
memLength = desc->u.Memory.Length;
}
DOUT(DBG_SYSINFO, ("Resource %d: Phys Addr = 0x%08lX%08lX, Mem Length = %lX",
i, physAddr.HighPart, physAddr.LowPart, memLength));
} else {
// get interrupt resource too if there is one
desc = ResourceList->FindTranslatedEntry(CmResourceTypeInterrupt, i);
if (desc) {
// interrupt = desc->u.Interrupt.Vector;
DOUT(DBG_SYSINFO, ("Resource %d: Affinity %d, Level %d, Vector = 0x%X",
i, desc->u.Interrupt.Affinity, desc->u.Interrupt.Level, desc->u.Interrupt.Vector));
}
}
}
if (!memLength) {
DOUT (DBG_ERROR, ("No memory for HD Audio controller registers"));
return STATUS_INSUFFICIENT_RESOURCES;
}
//Map the HDA controller PCI registers into kernel memory
m_pHDARegisters = (PUCHAR) MmMapIoSpace(physAddr, memLength, MmNonCached);
if (!m_pHDARegisters) {
DOUT (DBG_ERROR, ("Failed to map HD Audio registers to kernel mem"));
return STATUS_NO_MEMORY;
} else if (memLength < 16383) {
DOUT (DBG_ERROR, ("BAR0 is too small to be HDA"));
return STATUS_BUFFER_TOO_SMALL;
} else {
DOUT(DBG_SYSINFO, ("Virt Addr = 0x%X, Mem Length = 0x%X", m_pHDARegisters, memLength));
}
Base = (PUCHAR)m_pHDARegisters;
#if (DBG)
//try reading something from the mapped memory and see if it makes sense as hda registers
//for (i = 0; i < 16; i++) {
// DOUT(DBG_SYSINFO, ("Reg %d 0x%X", i, ((PUCHAR)m_pHDARegisters)[i] ));
//}
#endif
//read capabilities
USHORT caps = readUSHORT(0x00);
//check 64OK flag
is64OK = caps & 1;
//TODO check that we have at least 1 output or bidirectional stream engine
DOUT( DBG_SYSINFO, ("Version: %d.%d", readUCHAR(0x03), readUCHAR(0x02) ));
//offsets for stream engines
InputStreamBase = (0x80);
UCHAR numCaptureStreams = ((caps >> 8) & 0xF);
UCHAR numPlaybackStreams = ((caps >> 12) & 0xf);
if(!numCaptureStreams && !numPlaybackStreams){
DOUT(DBG_ERROR, ("Capabilities reports no streams. Guessing 4"));
//TODO check on ULI and ATI systems that report weird caps!
FirstOutputStream = 4;
} else {
FirstOutputStream = numCaptureStreams;
}
OutputStreamBase = HDA_STREAMBASE(FirstOutputStream); //skip input streams ports
switch((caps >> 1) & 0x3){
case 0:
nSDO = 1;
break;
case 1:
nSDO = 2;
break;
case 2:
nSDO = 4;
break;
}
DOUT( DBG_SYSINFO, ("caps 0x%X: input streams:%d output streams:%d bd streams:%d SDOs:%d 64ok:%d",
caps,
((caps >> 8) & 0xF),
((caps >> 12) & 0xF),
((caps >> 3) & 0x1f),
nSDO,
is64OK
));
//allocate common buffers
//for CORB, RIRB, BDL buffer, DMA position buffer
//the spec doesn't tell you this, but these can NOT share a 4k page
//so we need a separate mapping for each one.
//create device description object for our DMA
pDeviceDescription = (PDEVICE_DESCRIPTION)ExAllocatePool (PagedPool,
sizeof (DEVICE_DESCRIPTION));
if (!pDeviceDescription) {
return STATUS_INSUFFICIENT_RESOURCES;
}
//zero that struct
RtlZeroMemory(pDeviceDescription, sizeof (DEVICE_DESCRIPTION));
pDeviceDescription -> Version = DEVICE_DESCRIPTION_VERSION;
pDeviceDescription -> Master = TRUE; //is a bus master
pDeviceDescription -> ScatterGather = FALSE; //false for this purpose
pDeviceDescription -> DemandMode = FALSE;
pDeviceDescription -> AutoInitialize = FALSE;
pDeviceDescription -> Dma32BitAddresses = TRUE;
pDeviceDescription -> IgnoreCount = FALSE;
pDeviceDescription -> Reserved1 = FALSE;
pDeviceDescription -> Dma64BitAddresses = is64OK; //it might. doesnt matter to win98
pDeviceDescription -> DmaChannel = 0;
pDeviceDescription -> InterfaceType = PCIBus; //assumed to be cache-coherent
pDeviceDescription -> MaximumLength = BdlSize + 4096 + 8192;
//number of "map registers" doesn't matter at all here, but i need somewhere to put it
ULONG nMapRegisters = 0;
DMA_Adapter = IoGetDmaAdapter (
m_pDeviceObject,
pDeviceDescription,
&nMapRegisters );
DOUT(DBG_SYSINFO, ("Map Registers = %d", nMapRegisters));
//now we call the AllocateCommonBuffer function pointer in that struct
//Allocate RIRB
PVOID RirbVirtualAddress = NULL;
PPHYSICAL_ADDRESS pRirbLogicalAddress = NULL;
RirbVirtualAddress = DMA_Adapter->DmaOperations->AllocateCommonBuffer (
DMA_Adapter,
2048,
pRirbLogicalAddress, //out param
FALSE ); //CacheEnabled is probably ignored
RirbMemPhys = *pRirbLogicalAddress;
RirbMemVirt = (PULONG) RirbVirtualAddress;
//mdl = IoAllocateMdl(VirtualAddress, 8192, FALSE, FALSE, NULL);
DOUT(DBG_SYSINFO, ("RIRB Virt Addr = 0x%X,", RirbMemVirt));
DOUT(DBG_SYSINFO, ("RIRB Phys Addr = 0x%X,", RirbMemPhys));
if (!RirbMemVirt) {
DOUT(DBG_ERROR, ("Couldn't map virt RIRB Space"));
return STATUS_BUFFER_TOO_SMALL;
}
if (RirbMemPhys.QuadPart == 0) {
DOUT(DBG_ERROR, ("Couldn't map phys RIRB Space"));
return STATUS_NO_MEMORY;
}
if (is64OK == FALSE) {
ASSERT(RirbMemPhys.HighPart == 0);
}
//check 128-byte alignment of what we received
ASSERT( (RirbMemPhys.LowPart & 0x7F) == 0);
//allocate CORB
PVOID CorbVirtualAddress = NULL;
PPHYSICAL_ADDRESS pCorbLogicalAddress = NULL;
CorbVirtualAddress = DMA_Adapter->DmaOperations->AllocateCommonBuffer (
DMA_Adapter,
1024,
pCorbLogicalAddress, //out param
FALSE ); //CacheEnabled is probably ignored
CorbMemPhys = *pCorbLogicalAddress;
CorbMemVirt = (PULONG) CorbVirtualAddress;
DOUT(DBG_SYSINFO, ("Corb Virt Addr = 0x%X,", CorbMemVirt));
DOUT(DBG_SYSINFO, ("Corb Phys Addr = 0x%X,", CorbMemPhys));
if (!CorbMemVirt) {
DOUT(DBG_ERROR, ("Couldn't map virt Corb Space"));
return STATUS_BUFFER_TOO_SMALL;
}
if (CorbMemPhys.QuadPart == 0) {
DOUT(DBG_ERROR, ("Couldn't map phys Corb Space"));
return STATUS_NO_MEMORY;
}
if (is64OK == FALSE) {
ASSERT(CorbMemPhys.HighPart == 0);
}
//check 128-byte alignment of what we received
ASSERT( (CorbMemPhys.LowPart & 0x7F) == 0);
//allocate BDL
PVOID BdlVirtualAddress = NULL;
PPHYSICAL_ADDRESS pBdlLogicalAddress = NULL;
BdlVirtualAddress = DMA_Adapter->DmaOperations->AllocateCommonBuffer (
DMA_Adapter,
BdlSize,
pBdlLogicalAddress, //out param
FALSE ); //CacheEnabled is probably ignored
BdlMemPhys = *pBdlLogicalAddress;
BdlMemVirt = (PULONG) BdlVirtualAddress;
if (!BdlMemVirt) {
DOUT(DBG_ERROR, ("Couldn't map virt BDL Space"));
return STATUS_BUFFER_TOO_SMALL;
}
if (BdlMemPhys.QuadPart == 0) {
DOUT(DBG_ERROR, ("Couldn't map phys BDL Space"));
return STATUS_NO_MEMORY;
}
if (is64OK == FALSE) {
ASSERT(BdlMemPhys.HighPart == 0);
}
//allocate DMA Position Buffer
PVOID DmaVirtualAddress = NULL;
PPHYSICAL_ADDRESS pDmaLogicalAddress = NULL;
DmaVirtualAddress = DMA_Adapter->DmaOperations->AllocateCommonBuffer (
DMA_Adapter,
1024,
pDmaLogicalAddress, //out param
FALSE ); //CacheEnabled is probably ignored
DmaPosPhys = *pDmaLogicalAddress;
DmaPosVirt = (PULONG) DmaVirtualAddress;
if (!DmaPosVirt) {
DOUT(DBG_ERROR, ("Couldn't map virt DMA Position Buffer"));
return STATUS_BUFFER_TOO_SMALL;
}
if (DmaPosPhys.QuadPart == 0) {
DOUT(DBG_ERROR, ("Couldn't map phys DMA Position Buffer"));
return STATUS_NO_MEMORY;
}
if (is64OK == FALSE) {
ASSERT(DmaPosPhys.HighPart == 0);
}
if (!NT_SUCCESS (ntStatus)){
DbgPrint( "\nBuffer Mapping Failed! 0x%X\n", ntStatus);
return ntStatus;
}
// Not mapping an audio buffer yet, that happens when the
// Wave miniport calls showtime()
//
// Reset the controller and init registers
//
DbgPrint( ("\nInit HDA Controller!\n"));
ntStatus = InitHDAController ();
if (!NT_SUCCESS (ntStatus)){
DbgPrint( "\nResetController Failed! 0x%X\n", ntStatus);
return ntStatus;
} else {
DbgPrint( "\nResetController Succeeded! 0x%X\n", ntStatus);
}
//
// Hook up the interrupt.
//
ntStatus = PcNewInterruptSync( // See portcls.h
&m_pInterruptSync, // Save object ptr
NULL, // OuterUnknown(optional).
ResourceList, // He gets IRQ from ResourceList.
0, // Resource Index
InterruptSyncModeNormal // Run ISRs once until we get SUCCESS
);
if (!NT_SUCCESS(ntStatus) || m_pInterruptSync == NULL) {
DbgPrint("PcNewInterruptSync failed: 0x%X\n", ntStatus);
return ntStatus;
}
// run this ISR first
ntStatus = m_pInterruptSync->RegisterServiceRoutine(InterruptServiceRoutine,PVOID(this),FALSE);
if (!NT_SUCCESS(ntStatus)) {
DbgPrint("RegisterServiceRoutine failed: 0x%X\n", ntStatus);
m_pInterruptSync->Release();
m_pInterruptSync = NULL;
return ntStatus;
}
ntStatus = m_pInterruptSync->Connect();
if (!NT_SUCCESS(ntStatus)) {
DbgPrint("InterruptSync->Connect failed: 0x%X\n", ntStatus);
m_pInterruptSync->Release();
m_pInterruptSync = NULL;
return ntStatus;
}
DbgPrint("Init Finished Successfully!\n");
return ntStatus;
}
/*****************************************************************************
* CAdapterCommon::~CAdapterCommon()
*****************************************************************************
* Destructor.
*/
CAdapterCommon::
~CAdapterCommon
( void
)
{
PAGED_CODE();
_DbgPrintF(DEBUGLVL_VERBOSE,("[CAdapterCommon::~CAdapterCommon]"));
//At least try to stop the stream before destruction
hda_stop_stream ();
//Delete all initialized codec objects (packed in pCodecs[0..codecCount-1])
for (UCHAR i = 0; i < codecCount; i++) {
if (pCodecs[i] != NULL) {
delete pCodecs[i];
pCodecs[i] = NULL;
}
}
//do NOT free the audio buffer now minwave is managing it
//free DMA buffers
if((RirbMemVirt != NULL) && (DMA_Adapter!= NULL)){
DOUT (DBG_PRINT, ("freeing rirb buffer"));
DMA_Adapter->DmaOperations->FreeCommonBuffer(
DMA_Adapter,
2048,
RirbMemPhys,
RirbMemVirt,
FALSE );
RirbMemVirt = NULL;
}
if((CorbMemVirt != NULL) && (DMA_Adapter!= NULL)){
DOUT (DBG_PRINT, ("freeing Corb buffer"));
DMA_Adapter->DmaOperations->FreeCommonBuffer(
DMA_Adapter,
2048,
CorbMemPhys,
CorbMemVirt,
FALSE );
CorbMemVirt = NULL;
}
if((BdlMemVirt != NULL) && (DMA_Adapter!= NULL)){
DOUT (DBG_PRINT, ("freeing Bdl buffer"));
DMA_Adapter->DmaOperations->FreeCommonBuffer(
DMA_Adapter,
2048,
BdlMemPhys,
BdlMemVirt,
FALSE );
BdlMemVirt = NULL;
}
if((DmaPosVirt != NULL) && (DMA_Adapter!= NULL)){
DOUT (DBG_PRINT, ("freeing Dma buffer"));
DMA_Adapter->DmaOperations->FreeCommonBuffer(
DMA_Adapter,
2048,
DmaPosPhys,
DmaPosVirt,
FALSE );
DmaPosVirt = NULL;
}
//free DMA adapter object
if (DMA_Adapter) {
DMA_Adapter->DmaOperations->PutDmaAdapter(DMA_Adapter);
DMA_Adapter = NULL;
}
//free device description
if (pDeviceDescription) {
ExFreePool(pDeviceDescription);
pDeviceDescription = NULL;
}
//free device description
if (pConfigMem) {
ExFreePool(pConfigMem);
pConfigMem = NULL;
}
//free PCI BAR space